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Merge remote-tracking branches 'regulator/topic/rc5t619' and 'regulator/topic/stm32...
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / broadcom / bgmac.c
CommitLineData
dd4544f0
RM		 1/*
2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
3 *
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
5 *
6 * Licensed under the GNU/GPL. See COPYING for details.
7 */
8
dd4544f0 9
f6a95a24
JM		 10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12#include <linux/bcma/bcma.h>
dd4544f0 13#include <linux/etherdevice.h>
282ccf6e 14#include <linux/interrupt.h>
138173d4 15#include <linux/bcm47xx_nvram.h>
13bf7760
RK		 16#include <linux/phy.h>
17#include <linux/phy_fixed.h>
f6a95a24 18#include "bgmac.h"
dd4544f0 19
f6a95a24 20static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask,
dd4544f0
RM		 21 u32 value, int timeout)
22{
23 u32 val;
24 int i;
25
26 for (i = 0; i < timeout / 10; i++) {
f6a95a24 27 val = bgmac_read(bgmac, reg);
dd4544f0
RM		 28 if ((val & mask) == value)
29 return true;
30 udelay(10);
31 }
f6a95a24 32 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg);
dd4544f0
RM		 33 return false;
34}
35
36/**************************************************
37 * DMA
38 **************************************************/
39
40static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
41{
42 u32 val;
43 int i;
44
45 if (!ring->mmio_base)
46 return;
47
48 /* Suspend DMA TX ring first.
49 * bgmac_wait_value doesn't support waiting for any of few values, so
50 * implement whole loop here.
51 */
52 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
53 BGMAC_DMA_TX_SUSPEND);
54 for (i = 0; i < 10000 / 10; i++) {
55 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
56 val &= BGMAC_DMA_TX_STAT;
57 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
58 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
59 val == BGMAC_DMA_TX_STAT_STOPPED) {
60 i = 0;
61 break;
62 }
63 udelay(10);
64 }
65 if (i)
d00a8281
JM		 66 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
67 ring->mmio_base, val);
dd4544f0
RM		 68
69 /* Remove SUSPEND bit */
70 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
f6a95a24 71 if (!bgmac_wait_value(bgmac,
dd4544f0
RM		 72 ring->mmio_base + BGMAC_DMA_TX_STATUS,
73 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
74 10000)) {
d00a8281
JM		 75 dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
76 ring->mmio_base);
dd4544f0
RM		 77 udelay(300);
78 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
79 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
d00a8281
JM		 80 dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n",
81 ring->mmio_base);
dd4544f0
RM		 82 }
83}
84
85static void bgmac_dma_tx_enable(struct bgmac *bgmac,
86 struct bgmac_dma_ring *ring)
87{
88 u32 ctl;
89
90 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
db791eb2 91 if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) {
56ceecde
HM		 92 ctl &= ~BGMAC_DMA_TX_BL_MASK;
93 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
94
95 ctl &= ~BGMAC_DMA_TX_MR_MASK;
96 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
97
98 ctl &= ~BGMAC_DMA_TX_PC_MASK;
99 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
100
101 ctl &= ~BGMAC_DMA_TX_PT_MASK;
102 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
103 }
dd4544f0
RM		 104 ctl |= BGMAC_DMA_TX_ENABLE;
105 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
106 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
107}
108
9cde9450
FF		 109static void
110bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
111 int i, int len, u32 ctl0)
112{
113 struct bgmac_slot_info *slot;
114 struct bgmac_dma_desc *dma_desc;
115 u32 ctl1;
116
29ba877e 117 if (i == BGMAC_TX_RING_SLOTS - 1)
9cde9450
FF		 118 ctl0 |= BGMAC_DESC_CTL0_EOT;
119
120 ctl1 = len & BGMAC_DESC_CTL1_LEN;
121
122 slot = &ring->slots[i];
123 dma_desc = &ring->cpu_base[i];
124 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
125 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
126 dma_desc->ctl0 = cpu_to_le32(ctl0);
127 dma_desc->ctl1 = cpu_to_le32(ctl1);
128}
129
dd4544f0
RM		 130static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
131 struct bgmac_dma_ring *ring,
132 struct sk_buff *skb)
133{
a0b68486 134 struct device *dma_dev = bgmac->dma_dev;
dd4544f0 135 struct net_device *net_dev = bgmac->net_dev;
b38c83dd
FF		 136 int index = ring->end % BGMAC_TX_RING_SLOTS;
137 struct bgmac_slot_info *slot = &ring->slots[index];
9cde9450
FF		 138 int nr_frags;
139 u32 flags;
9cde9450 140 int i;
dd4544f0
RM		 141
142 if (skb->len > BGMAC_DESC_CTL1_LEN) {
d00a8281 143 netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len);
9cde9450 144 goto err_drop;
dd4544f0
RM		 145 }
146
9cde9450
FF		 147 if (skb->ip_summed == CHECKSUM_PARTIAL)
148 skb_checksum_help(skb);
149
150 nr_frags = skb_shinfo(skb)->nr_frags;
151
b38c83dd
FF		 152 /* ring->end - ring->start will return the number of valid slots,
153 * even when ring->end overflows
154 */
155 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
d00a8281 156 netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n");
dd4544f0
RM		 157 netif_stop_queue(net_dev);
158 return NETDEV_TX_BUSY;
159 }
160
9cde9450 161 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
dd4544f0 162 DMA_TO_DEVICE);
9cde9450
FF		 163 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
164 goto err_dma_head;
dd4544f0 165
9cde9450
FF		 166 flags = BGMAC_DESC_CTL0_SOF;
167 if (!nr_frags)
168 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
dd4544f0 169
9cde9450
FF		 170 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
171 flags = 0;
172
173 for (i = 0; i < nr_frags; i++) {
174 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
175 int len = skb_frag_size(frag);
176
177 index = (index + 1) % BGMAC_TX_RING_SLOTS;
178 slot = &ring->slots[index];
179 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
180 len, DMA_TO_DEVICE);
181 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
182 goto err_dma;
183
184 if (i == nr_frags - 1)
185 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
186
187 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
188 }
189
190 slot->skb = skb;
b38c83dd 191 ring->end += nr_frags + 1;
49a467b4
HM		 192 netdev_sent_queue(net_dev, skb->len);
193
dd4544f0
RM		 194 wmb();
195
196 /* Increase ring->end to point empty slot. We tell hardware the first
197 * slot it should *not* read.
198 */
dd4544f0 199 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
9900303e 200 ring->index_base +
b38c83dd
FF		 201 (ring->end % BGMAC_TX_RING_SLOTS) *
202 sizeof(struct bgmac_dma_desc));
dd4544f0 203
b38c83dd 204 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
dd4544f0
RM		 205 netif_stop_queue(net_dev);
206
207 return NETDEV_TX_OK;
208
9cde9450
FF		 209err_dma:
210 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
211 DMA_TO_DEVICE);
212
e86663c4 213 while (i-- > 0) {
9cde9450
FF		 214 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
215 struct bgmac_slot_info *slot = &ring->slots[index];
216 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
217 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
218
219 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
220 }
221
222err_dma_head:
d00a8281
JM		 223 netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n",
224 ring->mmio_base);
9cde9450
FF		 225
226err_drop:
dd4544f0 227 dev_kfree_skb(skb);
6d490f62
FF		 228 net_dev->stats.tx_dropped++;
229 net_dev->stats.tx_errors++;
dd4544f0
RM		 230 return NETDEV_TX_OK;
231}
232
233/* Free transmitted packets */
234static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
235{
a0b68486 236 struct device *dma_dev = bgmac->dma_dev;
dd4544f0
RM		 237 int empty_slot;
238 bool freed = false;
49a467b4 239 unsigned bytes_compl = 0, pkts_compl = 0;
dd4544f0
RM		 240
241 /* The last slot that hardware didn't consume yet */
242 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
243 empty_slot &= BGMAC_DMA_TX_STATDPTR;
9900303e
RM		 244 empty_slot -= ring->index_base;
245 empty_slot &= BGMAC_DMA_TX_STATDPTR;
dd4544f0
RM		 246 empty_slot /= sizeof(struct bgmac_dma_desc);
247
b38c83dd
FF		 248 while (ring->start != ring->end) {
249 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
250 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
d2b13233 251 u32 ctl0, ctl1;
b38c83dd 252 int len;
dd4544f0 253
b38c83dd
FF		 254 if (slot_idx == empty_slot)
255 break;
9cde9450 256
d2b13233 257 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
b38c83dd
FF		 258 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
259 len = ctl1 & BGMAC_DESC_CTL1_LEN;
d2b13233 260 if (ctl0 & BGMAC_DESC_CTL0_SOF)
dd4544f0 261 /* Unmap no longer used buffer */
9cde9450
FF		 262 dma_unmap_single(dma_dev, slot->dma_addr, len,
263 DMA_TO_DEVICE);
264 else
265 dma_unmap_page(dma_dev, slot->dma_addr, len,
266 DMA_TO_DEVICE);
dd4544f0 267
9cde9450 268 if (slot->skb) {
6d490f62
FF		 269 bgmac->net_dev->stats.tx_bytes += slot->skb->len;
270 bgmac->net_dev->stats.tx_packets++;
49a467b4
HM		 271 bytes_compl += slot->skb->len;
272 pkts_compl++;
273
dd4544f0
RM		 274 /* Free memory! :) */
275 dev_kfree_skb(slot->skb);
276 slot->skb = NULL;
dd4544f0
RM		 277 }
278
9cde9450 279 slot->dma_addr = 0;
b38c83dd 280 ring->start++;
dd4544f0
RM		 281 freed = true;
282 }
283
9cde9450
FF		 284 if (!pkts_compl)
285 return;
286
49a467b4
HM		 287 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
288
9cde9450 289 if (netif_queue_stopped(bgmac->net_dev))
dd4544f0
RM		 290 netif_wake_queue(bgmac->net_dev);
291}
292
293static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
294{
295 if (!ring->mmio_base)
296 return;
297
298 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
f6a95a24 299 if (!bgmac_wait_value(bgmac,
dd4544f0
RM		 300 ring->mmio_base + BGMAC_DMA_RX_STATUS,
301 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
302 10000))
d00a8281
JM		 303 dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n",
304 ring->mmio_base);
dd4544f0
RM		 305}
306
307static void bgmac_dma_rx_enable(struct bgmac *bgmac,
308 struct bgmac_dma_ring *ring)
309{
310 u32 ctl;
311
312 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
fcdefcca
AG		 313
314 /* preserve ONLY bits 16-17 from current hardware value */
315 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
316
db791eb2 317 if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) {
56ceecde
HM		 318 ctl &= ~BGMAC_DMA_RX_BL_MASK;
319 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
320
321 ctl &= ~BGMAC_DMA_RX_PC_MASK;
322 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
323
324 ctl &= ~BGMAC_DMA_RX_PT_MASK;
325 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
326 }
dd4544f0
RM		 327 ctl |= BGMAC_DMA_RX_ENABLE;
328 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
329 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
330 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
331 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
332}
333
334static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
335 struct bgmac_slot_info *slot)
336{
a0b68486 337 struct device *dma_dev = bgmac->dma_dev;
b757a62e 338 dma_addr_t dma_addr;
dd4544f0 339 struct bgmac_rx_header *rx;
45c9b3c0 340 void *buf;
dd4544f0
RM		 341
342 /* Alloc skb */
45c9b3c0
FF		 343 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
344 if (!buf)
dd4544f0 345 return -ENOMEM;
dd4544f0
RM		 346
347 /* Poison - if everything goes fine, hardware will overwrite it */
4b62dce4 348 rx = buf + BGMAC_RX_BUF_OFFSET;
dd4544f0
RM		 349 rx->len = cpu_to_le16(0xdead);
350 rx->flags = cpu_to_le16(0xbeef);
351
352 /* Map skb for the DMA */
4b62dce4
FF		 353 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
354 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
b757a62e 355 if (dma_mapping_error(dma_dev, dma_addr)) {
d00a8281 356 netdev_err(bgmac->net_dev, "DMA mapping error\n");
45c9b3c0 357 put_page(virt_to_head_page(buf));
dd4544f0
RM		 358 return -ENOMEM;
359 }
b757a62e
NH		 360
361 /* Update the slot */
45c9b3c0 362 slot->buf = buf;
b757a62e
NH		 363 slot->dma_addr = dma_addr;
364
dd4544f0
RM		 365 return 0;
366}
367
4668ae1f
FF		 368static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
369 struct bgmac_dma_ring *ring)
370{
371 dma_wmb();
372
373 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
374 ring->index_base +
375 ring->end * sizeof(struct bgmac_dma_desc));
376}
377
d549c76b
RM		 378static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
379 struct bgmac_dma_ring *ring, int desc_idx)
380{
381 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
382 u32 ctl0 = 0, ctl1 = 0;
383
29ba877e 384 if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
d549c76b
RM		 385 ctl0 |= BGMAC_DESC_CTL0_EOT;
386 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
387 /* Is there any BGMAC device that requires extension? */
388 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
389 * B43_DMA64_DCTL1_ADDREXT_MASK;
390 */
391
392 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
393 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
394 dma_desc->ctl0 = cpu_to_le32(ctl0);
395 dma_desc->ctl1 = cpu_to_le32(ctl1);
4668ae1f
FF		 396
397 ring->end = desc_idx;
d549c76b
RM		 398}
399
56faacd0
FF		 400static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
401 struct bgmac_slot_info *slot)
402{
403 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
404
405 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
406 DMA_FROM_DEVICE);
407 rx->len = cpu_to_le16(0xdead);
408 rx->flags = cpu_to_le16(0xbeef);
409 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
410 DMA_FROM_DEVICE);
411}
412
dd4544f0
RM		 413static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
414 int weight)
415{
416 u32 end_slot;
417 int handled = 0;
418
419 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
420 end_slot &= BGMAC_DMA_RX_STATDPTR;
9900303e
RM		 421 end_slot -= ring->index_base;
422 end_slot &= BGMAC_DMA_RX_STATDPTR;
dd4544f0
RM		 423 end_slot /= sizeof(struct bgmac_dma_desc);
424
4668ae1f 425 while (ring->start != end_slot) {
a0b68486 426 struct device *dma_dev = bgmac->dma_dev;
dd4544f0 427 struct bgmac_slot_info *slot = &ring->slots[ring->start];
4b62dce4 428 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
45c9b3c0
FF		 429 struct sk_buff *skb;
430 void *buf = slot->buf;
56faacd0 431 dma_addr_t dma_addr = slot->dma_addr;
dd4544f0
RM		 432 u16 len, flags;
433
56faacd0
FF		 434 do {
435 /* Prepare new skb as replacement */
436 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
437 bgmac_dma_rx_poison_buf(dma_dev, slot);
438 break;
439 }
dd4544f0 440
56faacd0
FF		 441 /* Unmap buffer to make it accessible to the CPU */
442 dma_unmap_single(dma_dev, dma_addr,
443 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
dd4544f0 444
56faacd0
FF		 445 /* Get info from the header */
446 len = le16_to_cpu(rx->len);
447 flags = le16_to_cpu(rx->flags);
92b9ccd3
RM		 448
449 /* Check for poison and drop or pass the packet */
450 if (len == 0xdead && flags == 0xbeef) {
d00a8281
JM		 451 netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n",
452 ring->start);
56faacd0 453 put_page(virt_to_head_page(buf));
6d490f62 454 bgmac->net_dev->stats.rx_errors++;
92b9ccd3
RM		 455 break;
456 }
457
6a6c7084 458 if (len > BGMAC_RX_ALLOC_SIZE) {
d00a8281
JM		 459 netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n",
460 ring->start);
6a6c7084 461 put_page(virt_to_head_page(buf));
6d490f62
FF		 462 bgmac->net_dev->stats.rx_length_errors++;
463 bgmac->net_dev->stats.rx_errors++;
6a6c7084
FF		 464 break;
465 }
466
02e71127
HM		 467 /* Omit CRC. */
468 len -= ETH_FCS_LEN;
469
45c9b3c0 470 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
750afbf8 471 if (unlikely(!skb)) {
d00a8281 472 netdev_err(bgmac->net_dev, "build_skb failed\n");
f1640c3d 473 put_page(virt_to_head_page(buf));
6d490f62 474 bgmac->net_dev->stats.rx_errors++;
f1640c3d 475 break;
476 }
4b62dce4
FF		 477 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
478 BGMAC_RX_BUF_OFFSET + len);
479 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
480 BGMAC_RX_BUF_OFFSET);
dd4544f0 481
92b9ccd3
RM		 482 skb_checksum_none_assert(skb);
483 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
6d490f62
FF		 484 bgmac->net_dev->stats.rx_bytes += len;
485 bgmac->net_dev->stats.rx_packets++;
45c9b3c0 486 napi_gro_receive(&bgmac->napi, skb);
92b9ccd3
RM		 487 handled++;
488 } while (0);
dd4544f0 489
56faacd0
FF		 490 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
491
dd4544f0
RM		 492 if (++ring->start >= BGMAC_RX_RING_SLOTS)
493 ring->start = 0;
494
495 if (handled >= weight) /* Should never be greater */
496 break;
497 }
498
4668ae1f
FF		 499 bgmac_dma_rx_update_index(bgmac, ring);
500
dd4544f0
RM		 501 return handled;
502}
503
504/* Does ring support unaligned addressing? */
505static bool bgmac_dma_unaligned(struct bgmac *bgmac,
506 struct bgmac_dma_ring *ring,
507 enum bgmac_dma_ring_type ring_type)
508{
509 switch (ring_type) {
510 case BGMAC_DMA_RING_TX:
511 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
512 0xff0);
513 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
514 return true;
515 break;
516 case BGMAC_DMA_RING_RX:
517 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
518 0xff0);
519 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
520 return true;
521 break;
522 }
523 return false;
524}
525
45c9b3c0
FF		 526static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
527 struct bgmac_dma_ring *ring)
dd4544f0 528{
a0b68486 529 struct device *dma_dev = bgmac->dma_dev;
9cde9450 530 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
dd4544f0 531 struct bgmac_slot_info *slot;
dd4544f0
RM		 532 int i;
533
29ba877e 534 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
9cde9450
FF		 535 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN;
536
dd4544f0 537 slot = &ring->slots[i];
9cde9450
FF		 538 dev_kfree_skb(slot->skb);
539
540 if (!slot->dma_addr)
541 continue;
542
543 if (slot->skb)
544 dma_unmap_single(dma_dev, slot->dma_addr,
545 len, DMA_TO_DEVICE);
546 else
547 dma_unmap_page(dma_dev, slot->dma_addr,
548 len, DMA_TO_DEVICE);
dd4544f0 549 }
45c9b3c0
FF		 550}
551
552static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
553 struct bgmac_dma_ring *ring)
554{
a0b68486 555 struct device *dma_dev = bgmac->dma_dev;
45c9b3c0
FF		 556 struct bgmac_slot_info *slot;
557 int i;
558
29ba877e 559 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
45c9b3c0 560 slot = &ring->slots[i];
56faacd0 561 if (!slot->dma_addr)
45c9b3c0 562 continue;
dd4544f0 563
56faacd0
FF		 564 dma_unmap_single(dma_dev, slot->dma_addr,
565 BGMAC_RX_BUF_SIZE,
566 DMA_FROM_DEVICE);
45c9b3c0 567 put_page(virt_to_head_page(slot->buf));
56faacd0 568 slot->dma_addr = 0;
dd4544f0
RM		 569 }
570}
571
45c9b3c0 572static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
29ba877e
FF		 573 struct bgmac_dma_ring *ring,
574 int num_slots)
45c9b3c0 575{
a0b68486 576 struct device *dma_dev = bgmac->dma_dev;
45c9b3c0
FF		 577 int size;
578
579 if (!ring->cpu_base)
580 return;
581
582 /* Free ring of descriptors */
29ba877e 583 size = num_slots * sizeof(struct bgmac_dma_desc);
45c9b3c0
FF		 584 dma_free_coherent(dma_dev, size, ring->cpu_base,
585 ring->dma_base);
586}
587
74b6f291 588static void bgmac_dma_cleanup(struct bgmac *bgmac)
dd4544f0
RM		 589{
590 int i;
591
74b6f291 592 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
45c9b3c0 593 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
74b6f291
FF		 594
595 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
45c9b3c0 596 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
74b6f291
FF		 597}
598
599static void bgmac_dma_free(struct bgmac *bgmac)
600{
601 int i;
602
603 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
29ba877e
FF		 604 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
605 BGMAC_TX_RING_SLOTS);
74b6f291
FF		 606
607 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
29ba877e
FF		 608 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
609 BGMAC_RX_RING_SLOTS);
dd4544f0
RM		 610}
611
612static int bgmac_dma_alloc(struct bgmac *bgmac)
613{
a0b68486 614 struct device *dma_dev = bgmac->dma_dev;
dd4544f0
RM		 615 struct bgmac_dma_ring *ring;
616 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
617 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
618 int size; /* ring size: different for Tx and Rx */
619 int err;
620 int i;
621
622 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
623 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
624
a163bdb0
AS		 625 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
626 if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) {
627 dev_err(bgmac->dev, "Core does not report 64-bit DMA\n");
628 return -ENOTSUPP;
629 }
dd4544f0
RM		 630 }
631
632 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
633 ring = &bgmac->tx_ring[i];
dd4544f0 634 ring->mmio_base = ring_base[i];
dd4544f0
RM		 635
636 /* Alloc ring of descriptors */
29ba877e 637 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
dd4544f0
RM		 638 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
639 &ring->dma_base,
640 GFP_KERNEL);
641 if (!ring->cpu_base) {
d00a8281
JM		 642 dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n",
643 ring->mmio_base);
dd4544f0
RM		 644 goto err_dma_free;
645 }
dd4544f0 646
9900303e
RM		 647 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
648 BGMAC_DMA_RING_TX);
649 if (ring->unaligned)
650 ring->index_base = lower_32_bits(ring->dma_base);
651 else
652 ring->index_base = 0;
653
dd4544f0
RM		 654 /* No need to alloc TX slots yet */
655 }
656
657 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
658 ring = &bgmac->rx_ring[i];
dd4544f0 659 ring->mmio_base = ring_base[i];
dd4544f0
RM		 660
661 /* Alloc ring of descriptors */
29ba877e 662 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
dd4544f0
RM		 663 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
664 &ring->dma_base,
665 GFP_KERNEL);
666 if (!ring->cpu_base) {
d00a8281
JM		 667 dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n",
668 ring->mmio_base);
dd4544f0
RM		 669 err = -ENOMEM;
670 goto err_dma_free;
671 }
dd4544f0 672
9900303e
RM		 673 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
674 BGMAC_DMA_RING_RX);
675 if (ring->unaligned)
676 ring->index_base = lower_32_bits(ring->dma_base);
677 else
678 ring->index_base = 0;
dd4544f0
RM		 679 }
680
681 return 0;
682
683err_dma_free:
684 bgmac_dma_free(bgmac);
685 return -ENOMEM;
686}
687
74b6f291 688static int bgmac_dma_init(struct bgmac *bgmac)
dd4544f0
RM		 689{
690 struct bgmac_dma_ring *ring;
74b6f291 691 int i, err;
dd4544f0
RM		 692
693 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
694 ring = &bgmac->tx_ring[i];
695
9900303e
RM		 696 if (!ring->unaligned)
697 bgmac_dma_tx_enable(bgmac, ring);
dd4544f0
RM		 698 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
699 lower_32_bits(ring->dma_base));
700 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
701 upper_32_bits(ring->dma_base));
9900303e
RM		 702 if (ring->unaligned)
703 bgmac_dma_tx_enable(bgmac, ring);
dd4544f0
RM		 704
705 ring->start = 0;
706 ring->end = 0; /* Points the slot that should *not* be read */
707 }
708
709 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
70a737b7
RM		 710 int j;
711
dd4544f0
RM		 712 ring = &bgmac->rx_ring[i];
713
9900303e
RM		 714 if (!ring->unaligned)
715 bgmac_dma_rx_enable(bgmac, ring);
dd4544f0
RM		 716 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
717 lower_32_bits(ring->dma_base));
718 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
719 upper_32_bits(ring->dma_base));
9900303e
RM		 720 if (ring->unaligned)
721 bgmac_dma_rx_enable(bgmac, ring);
dd4544f0 722
4668ae1f
FF		 723 ring->start = 0;
724 ring->end = 0;
29ba877e 725 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
74b6f291
FF		 726 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
727 if (err)
728 goto error;
729
d549c76b 730 bgmac_dma_rx_setup_desc(bgmac, ring, j);
74b6f291 731 }
dd4544f0 732
4668ae1f 733 bgmac_dma_rx_update_index(bgmac, ring);
dd4544f0 734 }
74b6f291
FF		 735
736 return 0;
737
738error:
739 bgmac_dma_cleanup(bgmac);
740 return err;
dd4544f0
RM		 741}
742
dd4544f0
RM		 743
744/**************************************************
745 * Chip ops
746 **************************************************/
747
748/* TODO: can we just drop @force? Can we don't reset MAC at all if there is
749 * nothing to change? Try if after stabilizng driver.
750 */
751static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
752 bool force)
753{
754 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
755 u32 new_val = (cmdcfg & mask) | set;
db791eb2 756 u32 cmdcfg_sr;
dd4544f0 757
db791eb2
JM		 758 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
759 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
760 else
761 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
762
763 bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr);
dd4544f0
RM		 764 udelay(2);
765
766 if (new_val != cmdcfg || force)
767 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
768
db791eb2 769 bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr);
dd4544f0
RM		 770 udelay(2);
771}
772
4e209001
HM		 773static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
774{
775 u32 tmp;
776
777 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
778 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
779 tmp = (addr[4] << 8) | addr[5];
780 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
781}
782
c6edfe10
HM		 783static void bgmac_set_rx_mode(struct net_device *net_dev)
784{
785 struct bgmac *bgmac = netdev_priv(net_dev);
786
787 if (net_dev->flags & IFF_PROMISC)
e9ba1039 788 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
c6edfe10 789 else
e9ba1039 790 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
c6edfe10
HM		 791}
792
dd4544f0
RM		 793#if 0 /* We don't use that regs yet */
794static void bgmac_chip_stats_update(struct bgmac *bgmac)
795{
796 int i;
797
db791eb2 798 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) {
dd4544f0
RM		 799 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
800 bgmac->mib_tx_regs[i] =
801 bgmac_read(bgmac,
802 BGMAC_TX_GOOD_OCTETS + (i * 4));
803 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
804 bgmac->mib_rx_regs[i] =
805 bgmac_read(bgmac,
806 BGMAC_RX_GOOD_OCTETS + (i * 4));
807 }
808
809 /* TODO: what else? how to handle BCM4706? Specs are needed */
810}
811#endif
812
813static void bgmac_clear_mib(struct bgmac *bgmac)
814{
815 int i;
816
db791eb2 817 if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)
dd4544f0
RM		 818 return;
819
820 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
821 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
822 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
823 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
824 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
825}
826
827/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
5824d2d1 828static void bgmac_mac_speed(struct bgmac *bgmac)
dd4544f0
RM		 829{
830 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
831 u32 set = 0;
832
5824d2d1
RM		 833 switch (bgmac->mac_speed) {
834 case SPEED_10:
dd4544f0 835 set |= BGMAC_CMDCFG_ES_10;
5824d2d1
RM		 836 break;
837 case SPEED_100:
dd4544f0 838 set |= BGMAC_CMDCFG_ES_100;
5824d2d1
RM		 839 break;
840 case SPEED_1000:
dd4544f0 841 set |= BGMAC_CMDCFG_ES_1000;
5824d2d1 842 break;
6df4aff9
HM		 843 case SPEED_2500:
844 set |= BGMAC_CMDCFG_ES_2500;
845 break;
5824d2d1 846 default:
d00a8281
JM		 847 dev_err(bgmac->dev, "Unsupported speed: %d\n",
848 bgmac->mac_speed);
5824d2d1
RM		 849 }
850
851 if (bgmac->mac_duplex == DUPLEX_HALF)
dd4544f0 852 set |= BGMAC_CMDCFG_HD;
5824d2d1 853
dd4544f0
RM		 854 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
855}
856
857static void bgmac_miiconfig(struct bgmac *bgmac)
858{
db791eb2 859 if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) {
a163bdb0
AS		 860 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
861 bgmac_idm_write(bgmac, BCMA_IOCTL,
862 bgmac_idm_read(bgmac, BCMA_IOCTL) |
863 0x40 | BGMAC_BCMA_IOCTL_SW_CLKEN);
864 }
6df4aff9 865 bgmac->mac_speed = SPEED_2500;
5824d2d1
RM		 866 bgmac->mac_duplex = DUPLEX_FULL;
867 bgmac_mac_speed(bgmac);
6df4aff9 868 } else {
db791eb2
JM		 869 u8 imode;
870
6df4aff9
HM		 871 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
872 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
873 if (imode == 0 || imode == 1) {
874 bgmac->mac_speed = SPEED_100;
875 bgmac->mac_duplex = DUPLEX_FULL;
876 bgmac_mac_speed(bgmac);
877 }
dd4544f0
RM		 878 }
879}
880
a163bdb0
AS		 881static void bgmac_chip_reset_idm_config(struct bgmac *bgmac)
882{
883 u32 iost;
884
885 iost = bgmac_idm_read(bgmac, BCMA_IOST);
886 if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED)
887 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
888
889 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
890 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) {
891 u32 flags = 0;
892
893 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
894 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
895 if (!bgmac->has_robosw)
896 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
897 }
898 bgmac_clk_enable(bgmac, flags);
899 }
900
901 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
902 bgmac_idm_write(bgmac, BCMA_IOCTL,
903 bgmac_idm_read(bgmac, BCMA_IOCTL) &
904 ~BGMAC_BCMA_IOCTL_SW_RESET);
905}
906
dd4544f0
RM		 907/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
908static void bgmac_chip_reset(struct bgmac *bgmac)
909{
db791eb2 910 u32 cmdcfg_sr;
dd4544f0
RM		 911 int i;
912
f6a95a24 913 if (bgmac_clk_enabled(bgmac)) {
dd4544f0
RM		 914 if (!bgmac->stats_grabbed) {
915 /* bgmac_chip_stats_update(bgmac); */
916 bgmac->stats_grabbed = true;
917 }
918
919 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
920 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
921
922 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
923 udelay(1);
924
925 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
926 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
927
928 /* TODO: Clear software multicast filter list */
929 }
930
a163bdb0
AS		 931 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK))
932 bgmac_chip_reset_idm_config(bgmac);
dd4544f0 933
6df4aff9 934 /* Request Misc PLL for corerev > 2 */
db791eb2 935 if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) {
1a0ab767
RM		 936 bgmac_set(bgmac, BCMA_CLKCTLST,
937 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
f6a95a24 938 bgmac_wait_value(bgmac, BCMA_CLKCTLST,
1a0ab767
RM		 939 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
940 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
dd4544f0
RM		 941 1000);
942 }
943
db791eb2 944 if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) {
dd4544f0
RM		 945 u8 et_swtype = 0;
946 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
6a391e7b 947 BGMAC_CHIPCTL_1_IF_TYPE_MII;
3647268d 948 char buf[4];
dd4544f0 949
3647268d 950 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
dd4544f0 951 if (kstrtou8(buf, 0, &et_swtype))
d00a8281
JM		 952 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
953 buf);
dd4544f0
RM		 954 et_swtype &= 0x0f;
955 et_swtype <<= 4;
956 sw_type = et_swtype;
db791eb2 957 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) {
e2d8f646
RM		 958 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RMII |
959 BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
db791eb2 960 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) {
b5a4c2f3
HM		 961 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
962 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
dd4544f0 963 }
f6a95a24
JM		 964 bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
965 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
966 sw_type);
1cb94db3
RM		 967 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE) {
968 u32 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_MII |
969 BGMAC_CHIPCTL_4_SW_TYPE_EPHY;
970 u8 et_swtype = 0;
971 char buf[4];
972
973 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
974 if (kstrtou8(buf, 0, &et_swtype))
975 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
976 buf);
977 sw_type = (et_swtype & 0x0f) << 12;
978 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII) {
979 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_RGMII |
980 BGMAC_CHIPCTL_4_SW_TYPE_RGMII;
981 }
982 bgmac_cco_ctl_maskset(bgmac, 4, ~(BGMAC_CHIPCTL_4_IF_TYPE_MASK |
983 BGMAC_CHIPCTL_4_SW_TYPE_MASK),
984 sw_type);
985 } else if (bgmac->feature_flags & BGMAC_FEAT_CC7_IF_TYPE_RGMII) {
986 bgmac_cco_ctl_maskset(bgmac, 7, ~BGMAC_CHIPCTL_7_IF_TYPE_MASK,
987 BGMAC_CHIPCTL_7_IF_TYPE_RGMII);
dd4544f0
RM		 988 }
989
dd4544f0
RM		 990 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
991 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
992 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
993 * be keps until taking MAC out of the reset.
994 */
db791eb2
JM		 995 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
996 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
997 else
998 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
999
dd4544f0
RM		 1000 bgmac_cmdcfg_maskset(bgmac,
1001 ~(BGMAC_CMDCFG_TE |
1002 BGMAC_CMDCFG_RE |
1003 BGMAC_CMDCFG_RPI |
1004 BGMAC_CMDCFG_TAI |
1005 BGMAC_CMDCFG_HD |
1006 BGMAC_CMDCFG_ML |
1007 BGMAC_CMDCFG_CFE |
1008 BGMAC_CMDCFG_RL |
1009 BGMAC_CMDCFG_RED |
1010 BGMAC_CMDCFG_PE |
1011 BGMAC_CMDCFG_TPI |
1012 BGMAC_CMDCFG_PAD_EN |
1013 BGMAC_CMDCFG_PF),
1014 BGMAC_CMDCFG_PROM |
1015 BGMAC_CMDCFG_NLC |
1016 BGMAC_CMDCFG_CFE |
db791eb2 1017 cmdcfg_sr,
dd4544f0 1018 false);
d469962f
RM		 1019 bgmac->mac_speed = SPEED_UNKNOWN;
1020 bgmac->mac_duplex = DUPLEX_UNKNOWN;
dd4544f0
RM		 1021
1022 bgmac_clear_mib(bgmac);
db791eb2 1023 if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL)
f6a95a24
JM		 1024 bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0,
1025 BCMA_GMAC_CMN_PC_MTE);
dd4544f0
RM		 1026 else
1027 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1028 bgmac_miiconfig(bgmac);
55954f3b
JM		 1029 if (bgmac->mii_bus)
1030 bgmac->mii_bus->reset(bgmac->mii_bus);
dd4544f0 1031
49a467b4 1032 netdev_reset_queue(bgmac->net_dev);
dd4544f0
RM		 1033}
1034
1035static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1036{
1037 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1038}
1039
1040static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1041{
1042 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
4160815f 1043 bgmac_read(bgmac, BGMAC_INT_MASK);
dd4544f0
RM		 1044}
1045
1046/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1047static void bgmac_enable(struct bgmac *bgmac)
1048{
db791eb2 1049 u32 cmdcfg_sr;
dd4544f0
RM		 1050 u32 cmdcfg;
1051 u32 mode;
db791eb2
JM		 1052
1053 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
1054 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
1055 else
1056 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
dd4544f0
RM		 1057
1058 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1059 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
db791eb2 1060 cmdcfg_sr, true);
dd4544f0
RM		 1061 udelay(2);
1062 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1063 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1064
1065 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1066 BGMAC_DS_MM_SHIFT;
cdb26d33 1067 if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0)
dd4544f0 1068 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
cdb26d33 1069 if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) && mode == 2)
f6a95a24
JM		 1070 bgmac_cco_ctl_maskset(bgmac, 1, ~0,
1071 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
dd4544f0 1072
db791eb2
JM		 1073 if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 |
1074 BGMAC_FEAT_FLW_CTRL2)) {
1075 u32 fl_ctl;
1076
1077 if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1)
dd4544f0 1078 fl_ctl = 0x2300e1;
db791eb2
JM		 1079 else
1080 fl_ctl = 0x03cb04cb;
1081
dd4544f0
RM		 1082 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1083 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
dd4544f0
RM		 1084 }
1085
db791eb2
JM		 1086 if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) {
1087 u32 rxq_ctl;
1088 u16 bp_clk;
1089 u8 mdp;
1090
6df4aff9
HM		 1091 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1092 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
f6a95a24 1093 bp_clk = bgmac_get_bus_clock(bgmac) / 1000000;
6df4aff9
HM		 1094 mdp = (bp_clk * 128 / 1000) - 3;
1095 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1096 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1097 }
dd4544f0
RM		 1098}
1099
1100/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
74b6f291 1101static void bgmac_chip_init(struct bgmac *bgmac)
dd4544f0 1102{
dd5c5d03
JM		 1103 /* Clear any erroneously pending interrupts */
1104 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1105
dd4544f0
RM		 1106 /* 1 interrupt per received frame */
1107 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1108
1109 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1110 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1111
c6edfe10 1112 bgmac_set_rx_mode(bgmac->net_dev);
dd4544f0 1113
4e209001 1114 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
dd4544f0
RM		 1115
1116 if (bgmac->loopback)
e9ba1039 1117 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
dd4544f0 1118 else
e9ba1039 1119 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
dd4544f0
RM		 1120
1121 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1122
74b6f291 1123 bgmac_chip_intrs_on(bgmac);
dd4544f0
RM		 1124
1125 bgmac_enable(bgmac);
1126}
1127
1128static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1129{
1130 struct bgmac *bgmac = netdev_priv(dev_id);
1131
1132 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1133 int_status &= bgmac->int_mask;
1134
1135 if (!int_status)
1136 return IRQ_NONE;
1137
eb64e292
FF		 1138 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1139 if (int_status)
d00a8281 1140 dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status);
dd4544f0
RM		 1141
1142 /* Disable new interrupts until handling existing ones */
1143 bgmac_chip_intrs_off(bgmac);
1144
dd4544f0
RM		 1145 napi_schedule(&bgmac->napi);
1146
1147 return IRQ_HANDLED;
1148}
1149
1150static int bgmac_poll(struct napi_struct *napi, int weight)
1151{
1152 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
dd4544f0
RM		 1153 int handled = 0;
1154
eb64e292
FF		 1155 /* Ack */
1156 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
dd4544f0 1157
eb64e292
FF		 1158 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1159 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
dd4544f0 1160
eb64e292
FF		 1161 /* Poll again if more events arrived in the meantime */
1162 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
e580267d 1163 return weight;
dd4544f0 1164
43f159c6 1165 if (handled < weight) {
6ad20165 1166 napi_complete_done(napi, handled);
43f159c6
HM		 1167 bgmac_chip_intrs_on(bgmac);
1168 }
dd4544f0
RM		 1169
1170 return handled;
1171}
1172
1173/**************************************************
1174 * net_device_ops
1175 **************************************************/
1176
1177static int bgmac_open(struct net_device *net_dev)
1178{
1179 struct bgmac *bgmac = netdev_priv(net_dev);
1180 int err = 0;
1181
1182 bgmac_chip_reset(bgmac);
74b6f291
FF		 1183
1184 err = bgmac_dma_init(bgmac);
1185 if (err)
1186 return err;
1187
dd4544f0 1188 /* Specs say about reclaiming rings here, but we do that in DMA init */
74b6f291 1189 bgmac_chip_init(bgmac);
dd4544f0 1190
f6a95a24 1191 err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED,
dd4544f0
RM		 1192 KBUILD_MODNAME, net_dev);
1193 if (err < 0) {
d00a8281 1194 dev_err(bgmac->dev, "IRQ request error: %d!\n", err);
74b6f291
FF		 1195 bgmac_dma_cleanup(bgmac);
1196 return err;
dd4544f0
RM		 1197 }
1198 napi_enable(&bgmac->napi);
1199
b21fcb25 1200 phy_start(net_dev->phydev);
4e34da4d 1201
c3897f2a
FF		 1202 netif_start_queue(net_dev);
1203
74b6f291 1204 return 0;
dd4544f0
RM		 1205}
1206
1207static int bgmac_stop(struct net_device *net_dev)
1208{
1209 struct bgmac *bgmac = netdev_priv(net_dev);
1210
1211 netif_carrier_off(net_dev);
1212
b21fcb25 1213 phy_stop(net_dev->phydev);
4e34da4d 1214
dd4544f0
RM		 1215 napi_disable(&bgmac->napi);
1216 bgmac_chip_intrs_off(bgmac);
f6a95a24 1217 free_irq(bgmac->irq, net_dev);
dd4544f0
RM		 1218
1219 bgmac_chip_reset(bgmac);
74b6f291 1220 bgmac_dma_cleanup(bgmac);
dd4544f0
RM		 1221
1222 return 0;
1223}
1224
1225static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1226 struct net_device *net_dev)
1227{
1228 struct bgmac *bgmac = netdev_priv(net_dev);
1229 struct bgmac_dma_ring *ring;
1230
1231 /* No QOS support yet */
1232 ring = &bgmac->tx_ring[0];
1233 return bgmac_dma_tx_add(bgmac, ring, skb);
1234}
1235
4e209001
HM		 1236static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1237{
1238 struct bgmac *bgmac = netdev_priv(net_dev);
fa42245d 1239 struct sockaddr *sa = addr;
4e209001
HM		 1240 int ret;
1241
1242 ret = eth_prepare_mac_addr_change(net_dev, addr);
1243 if (ret < 0)
1244 return ret;
fa42245d
HV		 1245
1246 ether_addr_copy(net_dev->dev_addr, sa->sa_data);
1247 bgmac_write_mac_address(bgmac, net_dev->dev_addr);
1248
4e209001
HM		 1249 eth_commit_mac_addr_change(net_dev, addr);
1250 return 0;
1251}
1252
dd4544f0
RM		 1253static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1254{
69c58852
HM		 1255 if (!netif_running(net_dev))
1256 return -EINVAL;
1257
b21fcb25 1258 return phy_mii_ioctl(net_dev->phydev, ifr, cmd);
dd4544f0
RM		 1259}
1260
1261static const struct net_device_ops bgmac_netdev_ops = {
1262 .ndo_open = bgmac_open,
1263 .ndo_stop = bgmac_stop,
1264 .ndo_start_xmit = bgmac_start_xmit,
c6edfe10 1265 .ndo_set_rx_mode = bgmac_set_rx_mode,
4e209001 1266 .ndo_set_mac_address = bgmac_set_mac_address,
522c5907 1267 .ndo_validate_addr = eth_validate_addr,
dd4544f0
RM		 1268 .ndo_do_ioctl = bgmac_ioctl,
1269};
1270
1271/**************************************************
1272 * ethtool_ops
1273 **************************************************/
1274
f6613d4f
FF		 1275struct bgmac_stat {
1276 u8 size;
1277 u32 offset;
1278 const char *name;
1279};
1280
1281static struct bgmac_stat bgmac_get_strings_stats[] = {
1282 { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" },
1283 { 4, BGMAC_TX_GOOD_PKTS, "tx_good" },
1284 { 8, BGMAC_TX_OCTETS, "tx_octets" },
1285 { 4, BGMAC_TX_PKTS, "tx_pkts" },
1286 { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" },
1287 { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" },
1288 { 4, BGMAC_TX_LEN_64, "tx_64" },
1289 { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" },
1290 { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" },
1291 { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" },
1292 { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" },
1293 { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" },
1294 { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" },
1295 { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" },
1296 { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" },
1297 { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" },
1298 { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" },
1299 { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" },
1300 { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" },
1301 { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" },
1302 { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" },
1303 { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" },
1304 { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" },
1305 { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" },
1306 { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" },
1307 { 4, BGMAC_TX_DEFERED, "tx_defered" },
1308 { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" },
1309 { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" },
1310 { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" },
1311 { 4, BGMAC_TX_Q0_PKTS, "tx_q0" },
1312 { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" },
1313 { 4, BGMAC_TX_Q1_PKTS, "tx_q1" },
1314 { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" },
1315 { 4, BGMAC_TX_Q2_PKTS, "tx_q2" },
1316 { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" },
1317 { 4, BGMAC_TX_Q3_PKTS, "tx_q3" },
1318 { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" },
1319 { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" },
1320 { 4, BGMAC_RX_GOOD_PKTS, "rx_good" },
1321 { 8, BGMAC_RX_OCTETS, "rx_octets" },
1322 { 4, BGMAC_RX_PKTS, "rx_pkts" },
1323 { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" },
1324 { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" },
1325 { 4, BGMAC_RX_LEN_64, "rx_64" },
1326 { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" },
1327 { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" },
1328 { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" },
1329 { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" },
1330 { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" },
1331 { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" },
1332 { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" },
1333 { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" },
1334 { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" },
1335 { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" },
1336 { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" },
1337 { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" },
1338 { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" },
1339 { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" },
1340 { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" },
1341 { 4, BGMAC_RX_CRC_ERRS, "rx_crc" },
1342 { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" },
1343 { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" },
1344 { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" },
1345 { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" },
1346 { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" },
1347 { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" },
1348};
1349
1350#define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats)
1351
1352static int bgmac_get_sset_count(struct net_device *dev, int string_set)
1353{
1354 switch (string_set) {
1355 case ETH_SS_STATS:
1356 return BGMAC_STATS_LEN;
1357 }
1358
1359 return -EOPNOTSUPP;
1360}
1361
1362static void bgmac_get_strings(struct net_device *dev, u32 stringset,
1363 u8 *data)
1364{
1365 int i;
1366
1367 if (stringset != ETH_SS_STATS)
1368 return;
1369
1370 for (i = 0; i < BGMAC_STATS_LEN; i++)
1371 strlcpy(data + i * ETH_GSTRING_LEN,
1372 bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN);
1373}
1374
1375static void bgmac_get_ethtool_stats(struct net_device *dev,
1376 struct ethtool_stats *ss, uint64_t *data)
1377{
1378 struct bgmac *bgmac = netdev_priv(dev);
1379 const struct bgmac_stat *s;
1380 unsigned int i;
1381 u64 val;
1382
1383 if (!netif_running(dev))
1384 return;
1385
1386 for (i = 0; i < BGMAC_STATS_LEN; i++) {
1387 s = &bgmac_get_strings_stats[i];
1388 val = 0;
1389 if (s->size == 8)
1390 val = (u64)bgmac_read(bgmac, s->offset + 4) << 32;
1391 val |= bgmac_read(bgmac, s->offset);
1392 data[i] = val;
1393 }
1394}
1395
dd4544f0
RM		 1396static void bgmac_get_drvinfo(struct net_device *net_dev,
1397 struct ethtool_drvinfo *info)
1398{
1399 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
f6a95a24 1400 strlcpy(info->bus_info, "AXI", sizeof(info->bus_info));
dd4544f0
RM		 1401}
1402
1403static const struct ethtool_ops bgmac_ethtool_ops = {
f6613d4f
FF		 1404 .get_strings = bgmac_get_strings,
1405 .get_sset_count = bgmac_get_sset_count,
1406 .get_ethtool_stats = bgmac_get_ethtool_stats,
dd4544f0 1407 .get_drvinfo = bgmac_get_drvinfo,
904632a2
PR		 1408 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1409 .set_link_ksettings = phy_ethtool_set_link_ksettings,
dd4544f0
RM		 1410};
1411
11e5e76e
RM		 1412/**************************************************
1413 * MII
1414 **************************************************/
1415
1676aba5 1416void bgmac_adjust_link(struct net_device *net_dev)
5824d2d1
RM		 1417{
1418 struct bgmac *bgmac = netdev_priv(net_dev);
b21fcb25 1419 struct phy_device *phy_dev = net_dev->phydev;
5824d2d1
RM		 1420 bool update = false;
1421
1422 if (phy_dev->link) {
1423 if (phy_dev->speed != bgmac->mac_speed) {
1424 bgmac->mac_speed = phy_dev->speed;
1425 update = true;
1426 }
1427
1428 if (phy_dev->duplex != bgmac->mac_duplex) {
1429 bgmac->mac_duplex = phy_dev->duplex;
1430 update = true;
1431 }
1432 }
1433
1434 if (update) {
1435 bgmac_mac_speed(bgmac);
1436 phy_print_status(phy_dev);
1437 }
1438}
1676aba5 1439EXPORT_SYMBOL_GPL(bgmac_adjust_link);
5824d2d1 1440
1676aba5 1441int bgmac_phy_connect_direct(struct bgmac *bgmac)
c25b23b8
RM		 1442{
1443 struct fixed_phy_status fphy_status = {
1444 .link = 1,
1445 .speed = SPEED_1000,
1446 .duplex = DUPLEX_FULL,
1447 };
1448 struct phy_device *phy_dev;
1449 int err;
1450
4db78d31 1451 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
c25b23b8 1452 if (!phy_dev || IS_ERR(phy_dev)) {
d00a8281 1453 dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
c25b23b8
RM		 1454 return -ENODEV;
1455 }
1456
1457 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1458 PHY_INTERFACE_MODE_MII);
1459 if (err) {
d00a8281 1460 dev_err(bgmac->dev, "Connecting PHY failed\n");
c25b23b8
RM		 1461 return err;
1462 }
1463
c25b23b8
RM		 1464 return err;
1465}
1676aba5 1466EXPORT_SYMBOL_GPL(bgmac_phy_connect_direct);
11e5e76e 1467
34a5102c 1468struct bgmac *bgmac_alloc(struct device *dev)
dd4544f0
RM		 1469{
1470 struct net_device *net_dev;
1471 struct bgmac *bgmac;
dd4544f0 1472
dd4544f0 1473 /* Allocation and references */
34a5102c 1474 net_dev = devm_alloc_etherdev(dev, sizeof(*bgmac));
dd4544f0 1475 if (!net_dev)
34a5102c 1476 return NULL;
f6a95a24 1477
dd4544f0 1478 net_dev->netdev_ops = &bgmac_netdev_ops;
7ad24ea4 1479 net_dev->ethtool_ops = &bgmac_ethtool_ops;
34a5102c 1480
dd4544f0 1481 bgmac = netdev_priv(net_dev);
34a5102c 1482 bgmac->dev = dev;
dd4544f0 1483 bgmac->net_dev = net_dev;
34a5102c
RM		 1484
1485 return bgmac;
1486}
1487EXPORT_SYMBOL_GPL(bgmac_alloc);
1488
1489int bgmac_enet_probe(struct bgmac *bgmac)
1490{
1491 struct net_device *net_dev = bgmac->net_dev;
1492 int err;
1493
f6a95a24
JM		 1494 net_dev->irq = bgmac->irq;
1495 SET_NETDEV_DEV(net_dev, bgmac->dev);
f3537b34 1496 dev_set_drvdata(bgmac->dev, bgmac);
f6a95a24 1497
6850f8b5 1498 if (!is_valid_ether_addr(net_dev->dev_addr)) {
f6a95a24 1499 dev_err(bgmac->dev, "Invalid MAC addr: %pM\n",
6850f8b5
TK		 1500 net_dev->dev_addr);
1501 eth_hw_addr_random(net_dev);
f6a95a24 1502 dev_warn(bgmac->dev, "Using random MAC: %pM\n",
6850f8b5 1503 net_dev->dev_addr);
dd4544f0 1504 }
dd4544f0 1505
f6a95a24
JM		 1506 /* This (reset &) enable is not preset in specs or reference driver but
1507 * Broadcom does it in arch PCI code when enabling fake PCI device.
1508 */
1509 bgmac_clk_enable(bgmac, 0);
dd4544f0 1510
1cb94db3 1511 /* This seems to be fixing IRQ by assigning OOB #6 to the core */
a163bdb0
AS		 1512 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
1513 if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6)
1514 bgmac_idm_write(bgmac, BCMA_OOB_SEL_OUT_A30, 0x86);
1515 }
1cb94db3 1516
dd4544f0
RM		 1517 bgmac_chip_reset(bgmac);
1518
1519 err = bgmac_dma_alloc(bgmac);
1520 if (err) {
d00a8281 1521 dev_err(bgmac->dev, "Unable to alloc memory for DMA\n");
34a5102c 1522 goto err_out;
dd4544f0
RM		 1523 }
1524
1525 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
edb15d83 1526 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
dd4544f0
RM		 1527 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1528
6216642f
HM		 1529 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1530
1676aba5 1531 err = bgmac_phy_connect(bgmac);
11e5e76e 1532 if (err) {
d00a8281 1533 dev_err(bgmac->dev, "Cannot connect to phy\n");
f6a95a24 1534 goto err_dma_free;
11e5e76e
RM		 1535 }
1536
9cde9450
FF		 1537 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1538 net_dev->hw_features = net_dev->features;
1539 net_dev->vlan_features = net_dev->features;
1540
dd4544f0
RM		 1541 err = register_netdev(bgmac->net_dev);
1542 if (err) {
d00a8281 1543 dev_err(bgmac->dev, "Cannot register net device\n");
55954f3b 1544 goto err_phy_disconnect;
dd4544f0
RM		 1545 }
1546
1547 netif_carrier_off(net_dev);
1548
dd4544f0
RM		 1549 return 0;
1550
55954f3b
JM		 1551err_phy_disconnect:
1552 phy_disconnect(net_dev->phydev);
dd4544f0
RM		 1553err_dma_free:
1554 bgmac_dma_free(bgmac);
34a5102c 1555err_out:
dd4544f0
RM		 1556
1557 return err;
1558}
f6a95a24 1559EXPORT_SYMBOL_GPL(bgmac_enet_probe);
dd4544f0 1560
f6a95a24 1561void bgmac_enet_remove(struct bgmac *bgmac)
dd4544f0 1562{
dd4544f0 1563 unregister_netdev(bgmac->net_dev);
55954f3b 1564 phy_disconnect(bgmac->net_dev->phydev);
6216642f 1565 netif_napi_del(&bgmac->napi);
dd4544f0 1566 bgmac_dma_free(bgmac);
dd4544f0
RM		 1567 free_netdev(bgmac->net_dev);
1568}
f6a95a24 1569EXPORT_SYMBOL_GPL(bgmac_enet_remove);
dd4544f0 1570
f3537b34
JZ		 1571int bgmac_enet_suspend(struct bgmac *bgmac)
1572{
1573 if (!netif_running(bgmac->net_dev))
1574 return 0;
1575
1576 phy_stop(bgmac->net_dev->phydev);
1577
1578 netif_stop_queue(bgmac->net_dev);
1579
1580 napi_disable(&bgmac->napi);
1581
1582 netif_tx_lock(bgmac->net_dev);
1583 netif_device_detach(bgmac->net_dev);
1584 netif_tx_unlock(bgmac->net_dev);
1585
1586 bgmac_chip_intrs_off(bgmac);
1587 bgmac_chip_reset(bgmac);
1588 bgmac_dma_cleanup(bgmac);
1589
1590 return 0;
1591}
1592EXPORT_SYMBOL_GPL(bgmac_enet_suspend);
1593
1594int bgmac_enet_resume(struct bgmac *bgmac)
1595{
1596 int rc;
1597
1598 if (!netif_running(bgmac->net_dev))
1599 return 0;
1600
1601 rc = bgmac_dma_init(bgmac);
1602 if (rc)
1603 return rc;
1604
1605 bgmac_chip_init(bgmac);
1606
1607 napi_enable(&bgmac->napi);
1608
1609 netif_tx_lock(bgmac->net_dev);
1610 netif_device_attach(bgmac->net_dev);
1611 netif_tx_unlock(bgmac->net_dev);
1612
1613 netif_start_queue(bgmac->net_dev);
1614
1615 phy_start(bgmac->net_dev->phydev);
1616
1617 return 0;
1618}
1619EXPORT_SYMBOL_GPL(bgmac_enet_resume);
1620
dd4544f0
RM		 1621MODULE_AUTHOR("Rafał Miłecki");
1622MODULE_LICENSE("GPL");
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