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b6016b76 MC |
1 | /* bnx2.c: Broadcom NX2 network driver. |
2 | * | |
8a56d243 | 3 | * Copyright (c) 2004-2013 Broadcom Corporation |
b6016b76 MC |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Written by: Michael Chan (mchan@broadcom.com) | |
10 | */ | |
11 | ||
3a9c6a49 | 12 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
f2a4f052 MC |
13 | |
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | ||
555069da | 17 | #include <linux/stringify.h> |
f2a4f052 MC |
18 | #include <linux/kernel.h> |
19 | #include <linux/timer.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/vmalloc.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/pci.h> | |
f2a4f052 MC |
26 | #include <linux/netdevice.h> |
27 | #include <linux/etherdevice.h> | |
28 | #include <linux/skbuff.h> | |
29 | #include <linux/dma-mapping.h> | |
1977f032 | 30 | #include <linux/bitops.h> |
f2a4f052 MC |
31 | #include <asm/io.h> |
32 | #include <asm/irq.h> | |
33 | #include <linux/delay.h> | |
34 | #include <asm/byteorder.h> | |
c86a31f4 | 35 | #include <asm/page.h> |
f2a4f052 MC |
36 | #include <linux/time.h> |
37 | #include <linux/ethtool.h> | |
38 | #include <linux/mii.h> | |
01789349 | 39 | #include <linux/if.h> |
f2a4f052 | 40 | #include <linux/if_vlan.h> |
f2a4f052 | 41 | #include <net/ip.h> |
de081fa5 | 42 | #include <net/tcp.h> |
f2a4f052 | 43 | #include <net/checksum.h> |
f2a4f052 MC |
44 | #include <linux/workqueue.h> |
45 | #include <linux/crc32.h> | |
46 | #include <linux/prefetch.h> | |
29b12174 | 47 | #include <linux/cache.h> |
57579f76 | 48 | #include <linux/firmware.h> |
706bf240 | 49 | #include <linux/log2.h> |
cd709aa9 | 50 | #include <linux/aer.h> |
f2a4f052 | 51 | |
4edd473f MC |
52 | #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) |
53 | #define BCM_CNIC 1 | |
54 | #include "cnic_if.h" | |
55 | #endif | |
b6016b76 MC |
56 | #include "bnx2.h" |
57 | #include "bnx2_fw.h" | |
b3448b0b | 58 | |
b6016b76 | 59 | #define DRV_MODULE_NAME "bnx2" |
487d9edc MC |
60 | #define DRV_MODULE_VERSION "2.2.5" |
61 | #define DRV_MODULE_RELDATE "December 20, 2013" | |
c2c20ef4 | 62 | #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw" |
22fa159d | 63 | #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw" |
c2c20ef4 | 64 | #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw" |
22fa159d MC |
65 | #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw" |
66 | #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw" | |
b6016b76 MC |
67 | |
68 | #define RUN_AT(x) (jiffies + (x)) | |
69 | ||
70 | /* Time in jiffies before concluding the transmitter is hung. */ | |
71 | #define TX_TIMEOUT (5*HZ) | |
72 | ||
cfd95a63 | 73 | static char version[] = |
b6016b76 MC |
74 | "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
75 | ||
76 | MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); | |
453a9c6e | 77 | MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver"); |
b6016b76 MC |
78 | MODULE_LICENSE("GPL"); |
79 | MODULE_VERSION(DRV_MODULE_VERSION); | |
57579f76 MC |
80 | MODULE_FIRMWARE(FW_MIPS_FILE_06); |
81 | MODULE_FIRMWARE(FW_RV2P_FILE_06); | |
82 | MODULE_FIRMWARE(FW_MIPS_FILE_09); | |
83 | MODULE_FIRMWARE(FW_RV2P_FILE_09); | |
078b0735 | 84 | MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax); |
b6016b76 MC |
85 | |
86 | static int disable_msi = 0; | |
87 | ||
1c8bb760 | 88 | module_param(disable_msi, int, S_IRUGO); |
b6016b76 MC |
89 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); |
90 | ||
91 | typedef enum { | |
92 | BCM5706 = 0, | |
93 | NC370T, | |
94 | NC370I, | |
95 | BCM5706S, | |
96 | NC370F, | |
5b0c76ad MC |
97 | BCM5708, |
98 | BCM5708S, | |
bac0dff6 | 99 | BCM5709, |
27a005b8 | 100 | BCM5709S, |
7bb0a04f | 101 | BCM5716, |
1caacecb | 102 | BCM5716S, |
b6016b76 MC |
103 | } board_t; |
104 | ||
105 | /* indexed by board_t, above */ | |
fefa8645 | 106 | static struct { |
b6016b76 | 107 | char *name; |
cfd95a63 | 108 | } board_info[] = { |
b6016b76 MC |
109 | { "Broadcom NetXtreme II BCM5706 1000Base-T" }, |
110 | { "HP NC370T Multifunction Gigabit Server Adapter" }, | |
111 | { "HP NC370i Multifunction Gigabit Server Adapter" }, | |
112 | { "Broadcom NetXtreme II BCM5706 1000Base-SX" }, | |
113 | { "HP NC370F Multifunction Gigabit Server Adapter" }, | |
5b0c76ad MC |
114 | { "Broadcom NetXtreme II BCM5708 1000Base-T" }, |
115 | { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, | |
bac0dff6 | 116 | { "Broadcom NetXtreme II BCM5709 1000Base-T" }, |
27a005b8 | 117 | { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, |
7bb0a04f | 118 | { "Broadcom NetXtreme II BCM5716 1000Base-T" }, |
1caacecb | 119 | { "Broadcom NetXtreme II BCM5716 1000Base-SX" }, |
b6016b76 MC |
120 | }; |
121 | ||
7bb0a04f | 122 | static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = { |
b6016b76 MC |
123 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, |
124 | PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T }, | |
125 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | |
126 | PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I }, | |
127 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | |
128 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 }, | |
5b0c76ad MC |
129 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708, |
130 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 }, | |
b6016b76 MC |
131 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, |
132 | PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F }, | |
133 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, | |
134 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S }, | |
5b0c76ad MC |
135 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S, |
136 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S }, | |
bac0dff6 MC |
137 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709, |
138 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 }, | |
27a005b8 MC |
139 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S, |
140 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S }, | |
7bb0a04f MC |
141 | { PCI_VENDOR_ID_BROADCOM, 0x163b, |
142 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 }, | |
1caacecb | 143 | { PCI_VENDOR_ID_BROADCOM, 0x163c, |
1f2435e5 | 144 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S }, |
b6016b76 MC |
145 | { 0, } |
146 | }; | |
147 | ||
0ced9d01 | 148 | static const struct flash_spec flash_table[] = |
b6016b76 | 149 | { |
e30372c9 MC |
150 | #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE) |
151 | #define NONBUFFERED_FLAGS (BNX2_NV_WREN) | |
b6016b76 | 152 | /* Slow EEPROM */ |
37137709 | 153 | {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, |
e30372c9 | 154 | BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, |
b6016b76 MC |
155 | SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, |
156 | "EEPROM - slow"}, | |
37137709 MC |
157 | /* Expansion entry 0001 */ |
158 | {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 159 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
160 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
161 | "Entry 0001"}, | |
b6016b76 MC |
162 | /* Saifun SA25F010 (non-buffered flash) */ |
163 | /* strap, cfg1, & write1 need updates */ | |
37137709 | 164 | {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, |
e30372c9 | 165 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
b6016b76 MC |
166 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, |
167 | "Non-buffered flash (128kB)"}, | |
168 | /* Saifun SA25F020 (non-buffered flash) */ | |
169 | /* strap, cfg1, & write1 need updates */ | |
37137709 | 170 | {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, |
e30372c9 | 171 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
b6016b76 MC |
172 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, |
173 | "Non-buffered flash (256kB)"}, | |
37137709 MC |
174 | /* Expansion entry 0100 */ |
175 | {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 176 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
177 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
178 | "Entry 0100"}, | |
179 | /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ | |
6aa20a22 | 180 | {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, |
e30372c9 | 181 | NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, |
37137709 MC |
182 | ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, |
183 | "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, | |
184 | /* Entry 0110: ST M45PE20 (non-buffered flash)*/ | |
185 | {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, | |
e30372c9 | 186 | NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, |
37137709 MC |
187 | ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, |
188 | "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, | |
189 | /* Saifun SA25F005 (non-buffered flash) */ | |
190 | /* strap, cfg1, & write1 need updates */ | |
191 | {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 192 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
193 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, |
194 | "Non-buffered flash (64kB)"}, | |
195 | /* Fast EEPROM */ | |
196 | {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, | |
e30372c9 | 197 | BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, |
37137709 MC |
198 | SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, |
199 | "EEPROM - fast"}, | |
200 | /* Expansion entry 1001 */ | |
201 | {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 202 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
203 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
204 | "Entry 1001"}, | |
205 | /* Expansion entry 1010 */ | |
206 | {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 207 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
208 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
209 | "Entry 1010"}, | |
210 | /* ATMEL AT45DB011B (buffered flash) */ | |
211 | {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, | |
e30372c9 | 212 | BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, |
37137709 MC |
213 | BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, |
214 | "Buffered flash (128kB)"}, | |
215 | /* Expansion entry 1100 */ | |
216 | {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 217 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
218 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
219 | "Entry 1100"}, | |
220 | /* Expansion entry 1101 */ | |
221 | {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 222 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
223 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
224 | "Entry 1101"}, | |
225 | /* Ateml Expansion entry 1110 */ | |
226 | {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, | |
e30372c9 | 227 | BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, |
37137709 MC |
228 | BUFFERED_FLASH_BYTE_ADDR_MASK, 0, |
229 | "Entry 1110 (Atmel)"}, | |
230 | /* ATMEL AT45DB021B (buffered flash) */ | |
231 | {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, | |
e30372c9 | 232 | BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, |
37137709 MC |
233 | BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, |
234 | "Buffered flash (256kB)"}, | |
b6016b76 MC |
235 | }; |
236 | ||
0ced9d01 | 237 | static const struct flash_spec flash_5709 = { |
e30372c9 MC |
238 | .flags = BNX2_NV_BUFFERED, |
239 | .page_bits = BCM5709_FLASH_PAGE_BITS, | |
240 | .page_size = BCM5709_FLASH_PAGE_SIZE, | |
241 | .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, | |
242 | .total_size = BUFFERED_FLASH_TOTAL_SIZE*2, | |
243 | .name = "5709 Buffered flash (256kB)", | |
244 | }; | |
245 | ||
b6016b76 MC |
246 | MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); |
247 | ||
4327ba43 | 248 | static void bnx2_init_napi(struct bnx2 *bp); |
f048fa9c | 249 | static void bnx2_del_napi(struct bnx2 *bp); |
4327ba43 | 250 | |
35e9010b | 251 | static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr) |
e89bbf10 | 252 | { |
2f8af120 | 253 | u32 diff; |
e89bbf10 | 254 | |
11848b96 MC |
255 | /* Tell compiler to fetch tx_prod and tx_cons from memory. */ |
256 | barrier(); | |
faac9c4b MC |
257 | |
258 | /* The ring uses 256 indices for 255 entries, one of them | |
259 | * needs to be skipped. | |
260 | */ | |
35e9010b | 261 | diff = txr->tx_prod - txr->tx_cons; |
2bc4078e | 262 | if (unlikely(diff >= BNX2_TX_DESC_CNT)) { |
faac9c4b | 263 | diff &= 0xffff; |
2bc4078e MC |
264 | if (diff == BNX2_TX_DESC_CNT) |
265 | diff = BNX2_MAX_TX_DESC_CNT; | |
faac9c4b | 266 | } |
807540ba | 267 | return bp->tx_ring_size - diff; |
e89bbf10 MC |
268 | } |
269 | ||
b6016b76 MC |
270 | static u32 |
271 | bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) | |
272 | { | |
1b8227c4 MC |
273 | u32 val; |
274 | ||
275 | spin_lock_bh(&bp->indirect_lock); | |
e503e066 MC |
276 | BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); |
277 | val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW); | |
1b8227c4 MC |
278 | spin_unlock_bh(&bp->indirect_lock); |
279 | return val; | |
b6016b76 MC |
280 | } |
281 | ||
282 | static void | |
283 | bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) | |
284 | { | |
1b8227c4 | 285 | spin_lock_bh(&bp->indirect_lock); |
e503e066 MC |
286 | BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); |
287 | BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val); | |
1b8227c4 | 288 | spin_unlock_bh(&bp->indirect_lock); |
b6016b76 MC |
289 | } |
290 | ||
2726d6e1 MC |
291 | static void |
292 | bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val) | |
293 | { | |
294 | bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val); | |
295 | } | |
296 | ||
297 | static u32 | |
298 | bnx2_shmem_rd(struct bnx2 *bp, u32 offset) | |
299 | { | |
807540ba | 300 | return bnx2_reg_rd_ind(bp, bp->shmem_base + offset); |
2726d6e1 MC |
301 | } |
302 | ||
b6016b76 MC |
303 | static void |
304 | bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) | |
305 | { | |
306 | offset += cid_addr; | |
1b8227c4 | 307 | spin_lock_bh(&bp->indirect_lock); |
4ce45e02 | 308 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
59b47d8a MC |
309 | int i; |
310 | ||
e503e066 MC |
311 | BNX2_WR(bp, BNX2_CTX_CTX_DATA, val); |
312 | BNX2_WR(bp, BNX2_CTX_CTX_CTRL, | |
313 | offset | BNX2_CTX_CTX_CTRL_WRITE_REQ); | |
59b47d8a | 314 | for (i = 0; i < 5; i++) { |
e503e066 | 315 | val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL); |
59b47d8a MC |
316 | if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) |
317 | break; | |
318 | udelay(5); | |
319 | } | |
320 | } else { | |
e503e066 MC |
321 | BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset); |
322 | BNX2_WR(bp, BNX2_CTX_DATA, val); | |
59b47d8a | 323 | } |
1b8227c4 | 324 | spin_unlock_bh(&bp->indirect_lock); |
b6016b76 MC |
325 | } |
326 | ||
4edd473f MC |
327 | #ifdef BCM_CNIC |
328 | static int | |
329 | bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info) | |
330 | { | |
331 | struct bnx2 *bp = netdev_priv(dev); | |
332 | struct drv_ctl_io *io = &info->data.io; | |
333 | ||
334 | switch (info->cmd) { | |
335 | case DRV_CTL_IO_WR_CMD: | |
336 | bnx2_reg_wr_ind(bp, io->offset, io->data); | |
337 | break; | |
338 | case DRV_CTL_IO_RD_CMD: | |
339 | io->data = bnx2_reg_rd_ind(bp, io->offset); | |
340 | break; | |
341 | case DRV_CTL_CTX_WR_CMD: | |
342 | bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data); | |
343 | break; | |
344 | default: | |
345 | return -EINVAL; | |
346 | } | |
347 | return 0; | |
348 | } | |
349 | ||
350 | static void bnx2_setup_cnic_irq_info(struct bnx2 *bp) | |
351 | { | |
352 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
353 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; | |
354 | int sb_id; | |
355 | ||
356 | if (bp->flags & BNX2_FLAG_USING_MSIX) { | |
357 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
358 | bnapi->cnic_present = 0; | |
359 | sb_id = bp->irq_nvecs; | |
360 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
361 | } else { | |
362 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
363 | bnapi->cnic_tag = bnapi->last_status_idx; | |
364 | bnapi->cnic_present = 1; | |
365 | sb_id = 0; | |
366 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
367 | } | |
368 | ||
369 | cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector; | |
370 | cp->irq_arr[0].status_blk = (void *) | |
371 | ((unsigned long) bnapi->status_blk.msi + | |
372 | (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id)); | |
373 | cp->irq_arr[0].status_blk_num = sb_id; | |
374 | cp->num_irq = 1; | |
375 | } | |
376 | ||
377 | static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops, | |
378 | void *data) | |
379 | { | |
380 | struct bnx2 *bp = netdev_priv(dev); | |
381 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
382 | ||
383 | if (ops == NULL) | |
384 | return -EINVAL; | |
385 | ||
386 | if (cp->drv_state & CNIC_DRV_STATE_REGD) | |
387 | return -EBUSY; | |
388 | ||
41c2178a MC |
389 | if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN)) |
390 | return -ENODEV; | |
391 | ||
4edd473f MC |
392 | bp->cnic_data = data; |
393 | rcu_assign_pointer(bp->cnic_ops, ops); | |
394 | ||
395 | cp->num_irq = 0; | |
396 | cp->drv_state = CNIC_DRV_STATE_REGD; | |
397 | ||
398 | bnx2_setup_cnic_irq_info(bp); | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
403 | static int bnx2_unregister_cnic(struct net_device *dev) | |
404 | { | |
405 | struct bnx2 *bp = netdev_priv(dev); | |
406 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; | |
407 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
408 | ||
c5a88950 | 409 | mutex_lock(&bp->cnic_lock); |
4edd473f MC |
410 | cp->drv_state = 0; |
411 | bnapi->cnic_present = 0; | |
2cfa5a04 | 412 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
c5a88950 | 413 | mutex_unlock(&bp->cnic_lock); |
4edd473f MC |
414 | synchronize_rcu(); |
415 | return 0; | |
416 | } | |
417 | ||
61c2fc4b | 418 | static struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev) |
4edd473f MC |
419 | { |
420 | struct bnx2 *bp = netdev_priv(dev); | |
421 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
422 | ||
7625eb2f MC |
423 | if (!cp->max_iscsi_conn) |
424 | return NULL; | |
425 | ||
4edd473f MC |
426 | cp->drv_owner = THIS_MODULE; |
427 | cp->chip_id = bp->chip_id; | |
428 | cp->pdev = bp->pdev; | |
429 | cp->io_base = bp->regview; | |
430 | cp->drv_ctl = bnx2_drv_ctl; | |
431 | cp->drv_register_cnic = bnx2_register_cnic; | |
432 | cp->drv_unregister_cnic = bnx2_unregister_cnic; | |
433 | ||
434 | return cp; | |
435 | } | |
4edd473f MC |
436 | |
437 | static void | |
438 | bnx2_cnic_stop(struct bnx2 *bp) | |
439 | { | |
440 | struct cnic_ops *c_ops; | |
441 | struct cnic_ctl_info info; | |
442 | ||
c5a88950 | 443 | mutex_lock(&bp->cnic_lock); |
13707f9e ED |
444 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
445 | lockdep_is_held(&bp->cnic_lock)); | |
4edd473f MC |
446 | if (c_ops) { |
447 | info.cmd = CNIC_CTL_STOP_CMD; | |
448 | c_ops->cnic_ctl(bp->cnic_data, &info); | |
449 | } | |
c5a88950 | 450 | mutex_unlock(&bp->cnic_lock); |
4edd473f MC |
451 | } |
452 | ||
453 | static void | |
454 | bnx2_cnic_start(struct bnx2 *bp) | |
455 | { | |
456 | struct cnic_ops *c_ops; | |
457 | struct cnic_ctl_info info; | |
458 | ||
c5a88950 | 459 | mutex_lock(&bp->cnic_lock); |
13707f9e ED |
460 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
461 | lockdep_is_held(&bp->cnic_lock)); | |
4edd473f MC |
462 | if (c_ops) { |
463 | if (!(bp->flags & BNX2_FLAG_USING_MSIX)) { | |
464 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; | |
465 | ||
466 | bnapi->cnic_tag = bnapi->last_status_idx; | |
467 | } | |
468 | info.cmd = CNIC_CTL_START_CMD; | |
469 | c_ops->cnic_ctl(bp->cnic_data, &info); | |
470 | } | |
c5a88950 | 471 | mutex_unlock(&bp->cnic_lock); |
4edd473f MC |
472 | } |
473 | ||
474 | #else | |
475 | ||
476 | static void | |
477 | bnx2_cnic_stop(struct bnx2 *bp) | |
478 | { | |
479 | } | |
480 | ||
481 | static void | |
482 | bnx2_cnic_start(struct bnx2 *bp) | |
483 | { | |
484 | } | |
485 | ||
486 | #endif | |
487 | ||
b6016b76 MC |
488 | static int |
489 | bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) | |
490 | { | |
491 | u32 val1; | |
492 | int i, ret; | |
493 | ||
583c28e5 | 494 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
e503e066 | 495 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); |
b6016b76 MC |
496 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; |
497 | ||
e503e066 MC |
498 | BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); |
499 | BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); | |
b6016b76 MC |
500 | |
501 | udelay(40); | |
502 | } | |
503 | ||
504 | val1 = (bp->phy_addr << 21) | (reg << 16) | | |
505 | BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT | | |
506 | BNX2_EMAC_MDIO_COMM_START_BUSY; | |
e503e066 | 507 | BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1); |
b6016b76 MC |
508 | |
509 | for (i = 0; i < 50; i++) { | |
510 | udelay(10); | |
511 | ||
e503e066 | 512 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); |
b6016b76 MC |
513 | if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { |
514 | udelay(5); | |
515 | ||
e503e066 | 516 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); |
b6016b76 MC |
517 | val1 &= BNX2_EMAC_MDIO_COMM_DATA; |
518 | ||
519 | break; | |
520 | } | |
521 | } | |
522 | ||
523 | if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) { | |
524 | *val = 0x0; | |
525 | ret = -EBUSY; | |
526 | } | |
527 | else { | |
528 | *val = val1; | |
529 | ret = 0; | |
530 | } | |
531 | ||
583c28e5 | 532 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
e503e066 | 533 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); |
b6016b76 MC |
534 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; |
535 | ||
e503e066 MC |
536 | BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); |
537 | BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); | |
b6016b76 MC |
538 | |
539 | udelay(40); | |
540 | } | |
541 | ||
542 | return ret; | |
543 | } | |
544 | ||
545 | static int | |
546 | bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) | |
547 | { | |
548 | u32 val1; | |
549 | int i, ret; | |
550 | ||
583c28e5 | 551 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
e503e066 | 552 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); |
b6016b76 MC |
553 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; |
554 | ||
e503e066 MC |
555 | BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); |
556 | BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); | |
b6016b76 MC |
557 | |
558 | udelay(40); | |
559 | } | |
560 | ||
561 | val1 = (bp->phy_addr << 21) | (reg << 16) | val | | |
562 | BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | | |
563 | BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; | |
e503e066 | 564 | BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1); |
6aa20a22 | 565 | |
b6016b76 MC |
566 | for (i = 0; i < 50; i++) { |
567 | udelay(10); | |
568 | ||
e503e066 | 569 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); |
b6016b76 MC |
570 | if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { |
571 | udelay(5); | |
572 | break; | |
573 | } | |
574 | } | |
575 | ||
576 | if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) | |
577 | ret = -EBUSY; | |
578 | else | |
579 | ret = 0; | |
580 | ||
583c28e5 | 581 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
e503e066 | 582 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); |
b6016b76 MC |
583 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; |
584 | ||
e503e066 MC |
585 | BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); |
586 | BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); | |
b6016b76 MC |
587 | |
588 | udelay(40); | |
589 | } | |
590 | ||
591 | return ret; | |
592 | } | |
593 | ||
594 | static void | |
595 | bnx2_disable_int(struct bnx2 *bp) | |
596 | { | |
b4b36042 MC |
597 | int i; |
598 | struct bnx2_napi *bnapi; | |
599 | ||
600 | for (i = 0; i < bp->irq_nvecs; i++) { | |
601 | bnapi = &bp->bnx2_napi[i]; | |
e503e066 | 602 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
b4b36042 MC |
603 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); |
604 | } | |
e503e066 | 605 | BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); |
b6016b76 MC |
606 | } |
607 | ||
608 | static void | |
609 | bnx2_enable_int(struct bnx2 *bp) | |
610 | { | |
b4b36042 MC |
611 | int i; |
612 | struct bnx2_napi *bnapi; | |
35efa7c1 | 613 | |
b4b36042 MC |
614 | for (i = 0; i < bp->irq_nvecs; i++) { |
615 | bnapi = &bp->bnx2_napi[i]; | |
1269a8a6 | 616 | |
e503e066 MC |
617 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
618 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
619 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT | | |
620 | bnapi->last_status_idx); | |
b6016b76 | 621 | |
e503e066 MC |
622 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
623 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
624 | bnapi->last_status_idx); | |
b4b36042 | 625 | } |
e503e066 | 626 | BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); |
b6016b76 MC |
627 | } |
628 | ||
629 | static void | |
630 | bnx2_disable_int_sync(struct bnx2 *bp) | |
631 | { | |
b4b36042 MC |
632 | int i; |
633 | ||
b6016b76 | 634 | atomic_inc(&bp->intr_sem); |
3767546c MC |
635 | if (!netif_running(bp->dev)) |
636 | return; | |
637 | ||
b6016b76 | 638 | bnx2_disable_int(bp); |
b4b36042 MC |
639 | for (i = 0; i < bp->irq_nvecs; i++) |
640 | synchronize_irq(bp->irq_tbl[i].vector); | |
b6016b76 MC |
641 | } |
642 | ||
35efa7c1 MC |
643 | static void |
644 | bnx2_napi_disable(struct bnx2 *bp) | |
645 | { | |
b4b36042 MC |
646 | int i; |
647 | ||
648 | for (i = 0; i < bp->irq_nvecs; i++) | |
649 | napi_disable(&bp->bnx2_napi[i].napi); | |
35efa7c1 MC |
650 | } |
651 | ||
652 | static void | |
653 | bnx2_napi_enable(struct bnx2 *bp) | |
654 | { | |
b4b36042 MC |
655 | int i; |
656 | ||
657 | for (i = 0; i < bp->irq_nvecs; i++) | |
658 | napi_enable(&bp->bnx2_napi[i].napi); | |
35efa7c1 MC |
659 | } |
660 | ||
b6016b76 | 661 | static void |
212f9934 | 662 | bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic) |
b6016b76 | 663 | { |
212f9934 MC |
664 | if (stop_cnic) |
665 | bnx2_cnic_stop(bp); | |
b6016b76 | 666 | if (netif_running(bp->dev)) { |
35efa7c1 | 667 | bnx2_napi_disable(bp); |
b6016b76 | 668 | netif_tx_disable(bp->dev); |
b6016b76 | 669 | } |
b7466560 | 670 | bnx2_disable_int_sync(bp); |
a0ba6760 | 671 | netif_carrier_off(bp->dev); /* prevent tx timeout */ |
b6016b76 MC |
672 | } |
673 | ||
674 | static void | |
212f9934 | 675 | bnx2_netif_start(struct bnx2 *bp, bool start_cnic) |
b6016b76 MC |
676 | { |
677 | if (atomic_dec_and_test(&bp->intr_sem)) { | |
678 | if (netif_running(bp->dev)) { | |
706bf240 | 679 | netif_tx_wake_all_queues(bp->dev); |
a0ba6760 MC |
680 | spin_lock_bh(&bp->phy_lock); |
681 | if (bp->link_up) | |
682 | netif_carrier_on(bp->dev); | |
683 | spin_unlock_bh(&bp->phy_lock); | |
35efa7c1 | 684 | bnx2_napi_enable(bp); |
b6016b76 | 685 | bnx2_enable_int(bp); |
212f9934 MC |
686 | if (start_cnic) |
687 | bnx2_cnic_start(bp); | |
b6016b76 MC |
688 | } |
689 | } | |
690 | } | |
691 | ||
35e9010b MC |
692 | static void |
693 | bnx2_free_tx_mem(struct bnx2 *bp) | |
694 | { | |
695 | int i; | |
696 | ||
697 | for (i = 0; i < bp->num_tx_rings; i++) { | |
698 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
699 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; | |
700 | ||
701 | if (txr->tx_desc_ring) { | |
36227e88 SG |
702 | dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE, |
703 | txr->tx_desc_ring, | |
704 | txr->tx_desc_mapping); | |
35e9010b MC |
705 | txr->tx_desc_ring = NULL; |
706 | } | |
707 | kfree(txr->tx_buf_ring); | |
708 | txr->tx_buf_ring = NULL; | |
709 | } | |
710 | } | |
711 | ||
bb4f98ab MC |
712 | static void |
713 | bnx2_free_rx_mem(struct bnx2 *bp) | |
714 | { | |
715 | int i; | |
716 | ||
717 | for (i = 0; i < bp->num_rx_rings; i++) { | |
718 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
719 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
720 | int j; | |
721 | ||
722 | for (j = 0; j < bp->rx_max_ring; j++) { | |
723 | if (rxr->rx_desc_ring[j]) | |
36227e88 SG |
724 | dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, |
725 | rxr->rx_desc_ring[j], | |
726 | rxr->rx_desc_mapping[j]); | |
bb4f98ab MC |
727 | rxr->rx_desc_ring[j] = NULL; |
728 | } | |
25b0b999 | 729 | vfree(rxr->rx_buf_ring); |
bb4f98ab MC |
730 | rxr->rx_buf_ring = NULL; |
731 | ||
732 | for (j = 0; j < bp->rx_max_pg_ring; j++) { | |
733 | if (rxr->rx_pg_desc_ring[j]) | |
36227e88 SG |
734 | dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, |
735 | rxr->rx_pg_desc_ring[j], | |
736 | rxr->rx_pg_desc_mapping[j]); | |
3298a738 | 737 | rxr->rx_pg_desc_ring[j] = NULL; |
bb4f98ab | 738 | } |
25b0b999 | 739 | vfree(rxr->rx_pg_ring); |
bb4f98ab MC |
740 | rxr->rx_pg_ring = NULL; |
741 | } | |
742 | } | |
743 | ||
35e9010b MC |
744 | static int |
745 | bnx2_alloc_tx_mem(struct bnx2 *bp) | |
746 | { | |
747 | int i; | |
748 | ||
749 | for (i = 0; i < bp->num_tx_rings; i++) { | |
750 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
751 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; | |
752 | ||
753 | txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); | |
754 | if (txr->tx_buf_ring == NULL) | |
755 | return -ENOMEM; | |
756 | ||
757 | txr->tx_desc_ring = | |
36227e88 SG |
758 | dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE, |
759 | &txr->tx_desc_mapping, GFP_KERNEL); | |
35e9010b MC |
760 | if (txr->tx_desc_ring == NULL) |
761 | return -ENOMEM; | |
762 | } | |
763 | return 0; | |
764 | } | |
765 | ||
bb4f98ab MC |
766 | static int |
767 | bnx2_alloc_rx_mem(struct bnx2 *bp) | |
768 | { | |
769 | int i; | |
770 | ||
771 | for (i = 0; i < bp->num_rx_rings; i++) { | |
772 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
773 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
774 | int j; | |
775 | ||
776 | rxr->rx_buf_ring = | |
89bf67f1 | 777 | vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring); |
bb4f98ab MC |
778 | if (rxr->rx_buf_ring == NULL) |
779 | return -ENOMEM; | |
780 | ||
bb4f98ab MC |
781 | for (j = 0; j < bp->rx_max_ring; j++) { |
782 | rxr->rx_desc_ring[j] = | |
36227e88 SG |
783 | dma_alloc_coherent(&bp->pdev->dev, |
784 | RXBD_RING_SIZE, | |
785 | &rxr->rx_desc_mapping[j], | |
786 | GFP_KERNEL); | |
bb4f98ab MC |
787 | if (rxr->rx_desc_ring[j] == NULL) |
788 | return -ENOMEM; | |
789 | ||
790 | } | |
791 | ||
792 | if (bp->rx_pg_ring_size) { | |
89bf67f1 | 793 | rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE * |
bb4f98ab MC |
794 | bp->rx_max_pg_ring); |
795 | if (rxr->rx_pg_ring == NULL) | |
796 | return -ENOMEM; | |
797 | ||
bb4f98ab MC |
798 | } |
799 | ||
800 | for (j = 0; j < bp->rx_max_pg_ring; j++) { | |
801 | rxr->rx_pg_desc_ring[j] = | |
36227e88 SG |
802 | dma_alloc_coherent(&bp->pdev->dev, |
803 | RXBD_RING_SIZE, | |
804 | &rxr->rx_pg_desc_mapping[j], | |
805 | GFP_KERNEL); | |
bb4f98ab MC |
806 | if (rxr->rx_pg_desc_ring[j] == NULL) |
807 | return -ENOMEM; | |
808 | ||
809 | } | |
810 | } | |
811 | return 0; | |
812 | } | |
813 | ||
b6016b76 MC |
814 | static void |
815 | bnx2_free_mem(struct bnx2 *bp) | |
816 | { | |
13daffa2 | 817 | int i; |
43e80b89 | 818 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; |
13daffa2 | 819 | |
35e9010b | 820 | bnx2_free_tx_mem(bp); |
bb4f98ab | 821 | bnx2_free_rx_mem(bp); |
35e9010b | 822 | |
59b47d8a MC |
823 | for (i = 0; i < bp->ctx_pages; i++) { |
824 | if (bp->ctx_blk[i]) { | |
2bc4078e | 825 | dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE, |
36227e88 SG |
826 | bp->ctx_blk[i], |
827 | bp->ctx_blk_mapping[i]); | |
59b47d8a MC |
828 | bp->ctx_blk[i] = NULL; |
829 | } | |
830 | } | |
43e80b89 | 831 | if (bnapi->status_blk.msi) { |
36227e88 SG |
832 | dma_free_coherent(&bp->pdev->dev, bp->status_stats_size, |
833 | bnapi->status_blk.msi, | |
834 | bp->status_blk_mapping); | |
43e80b89 | 835 | bnapi->status_blk.msi = NULL; |
0f31f994 | 836 | bp->stats_blk = NULL; |
b6016b76 | 837 | } |
b6016b76 MC |
838 | } |
839 | ||
840 | static int | |
841 | bnx2_alloc_mem(struct bnx2 *bp) | |
842 | { | |
35e9010b | 843 | int i, status_blk_size, err; |
43e80b89 MC |
844 | struct bnx2_napi *bnapi; |
845 | void *status_blk; | |
b6016b76 | 846 | |
0f31f994 MC |
847 | /* Combine status and statistics blocks into one allocation. */ |
848 | status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); | |
f86e82fb | 849 | if (bp->flags & BNX2_FLAG_MSIX_CAP) |
b4b36042 MC |
850 | status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC * |
851 | BNX2_SBLK_MSIX_ALIGN_SIZE); | |
0f31f994 MC |
852 | bp->status_stats_size = status_blk_size + |
853 | sizeof(struct statistics_block); | |
854 | ||
ede23fa8 JP |
855 | status_blk = dma_zalloc_coherent(&bp->pdev->dev, bp->status_stats_size, |
856 | &bp->status_blk_mapping, GFP_KERNEL); | |
43e80b89 | 857 | if (status_blk == NULL) |
b6016b76 MC |
858 | goto alloc_mem_err; |
859 | ||
43e80b89 MC |
860 | bnapi = &bp->bnx2_napi[0]; |
861 | bnapi->status_blk.msi = status_blk; | |
862 | bnapi->hw_tx_cons_ptr = | |
863 | &bnapi->status_blk.msi->status_tx_quick_consumer_index0; | |
864 | bnapi->hw_rx_cons_ptr = | |
865 | &bnapi->status_blk.msi->status_rx_quick_consumer_index0; | |
f86e82fb | 866 | if (bp->flags & BNX2_FLAG_MSIX_CAP) { |
379b39a2 | 867 | for (i = 1; i < bp->irq_nvecs; i++) { |
43e80b89 MC |
868 | struct status_block_msix *sblk; |
869 | ||
870 | bnapi = &bp->bnx2_napi[i]; | |
b4b36042 | 871 | |
64699336 | 872 | sblk = (status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i); |
43e80b89 MC |
873 | bnapi->status_blk.msix = sblk; |
874 | bnapi->hw_tx_cons_ptr = | |
875 | &sblk->status_tx_quick_consumer_index; | |
876 | bnapi->hw_rx_cons_ptr = | |
877 | &sblk->status_rx_quick_consumer_index; | |
b4b36042 MC |
878 | bnapi->int_num = i << 24; |
879 | } | |
880 | } | |
35efa7c1 | 881 | |
43e80b89 | 882 | bp->stats_blk = status_blk + status_blk_size; |
b6016b76 | 883 | |
0f31f994 | 884 | bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; |
b6016b76 | 885 | |
4ce45e02 | 886 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
2bc4078e | 887 | bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE; |
59b47d8a MC |
888 | if (bp->ctx_pages == 0) |
889 | bp->ctx_pages = 1; | |
890 | for (i = 0; i < bp->ctx_pages; i++) { | |
36227e88 | 891 | bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev, |
2bc4078e | 892 | BNX2_PAGE_SIZE, |
36227e88 SG |
893 | &bp->ctx_blk_mapping[i], |
894 | GFP_KERNEL); | |
59b47d8a MC |
895 | if (bp->ctx_blk[i] == NULL) |
896 | goto alloc_mem_err; | |
897 | } | |
898 | } | |
35e9010b | 899 | |
bb4f98ab MC |
900 | err = bnx2_alloc_rx_mem(bp); |
901 | if (err) | |
902 | goto alloc_mem_err; | |
903 | ||
35e9010b MC |
904 | err = bnx2_alloc_tx_mem(bp); |
905 | if (err) | |
906 | goto alloc_mem_err; | |
907 | ||
b6016b76 MC |
908 | return 0; |
909 | ||
910 | alloc_mem_err: | |
911 | bnx2_free_mem(bp); | |
912 | return -ENOMEM; | |
913 | } | |
914 | ||
e3648b3d MC |
915 | static void |
916 | bnx2_report_fw_link(struct bnx2 *bp) | |
917 | { | |
918 | u32 fw_link_status = 0; | |
919 | ||
583c28e5 | 920 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
921 | return; |
922 | ||
e3648b3d MC |
923 | if (bp->link_up) { |
924 | u32 bmsr; | |
925 | ||
926 | switch (bp->line_speed) { | |
927 | case SPEED_10: | |
928 | if (bp->duplex == DUPLEX_HALF) | |
929 | fw_link_status = BNX2_LINK_STATUS_10HALF; | |
930 | else | |
931 | fw_link_status = BNX2_LINK_STATUS_10FULL; | |
932 | break; | |
933 | case SPEED_100: | |
934 | if (bp->duplex == DUPLEX_HALF) | |
935 | fw_link_status = BNX2_LINK_STATUS_100HALF; | |
936 | else | |
937 | fw_link_status = BNX2_LINK_STATUS_100FULL; | |
938 | break; | |
939 | case SPEED_1000: | |
940 | if (bp->duplex == DUPLEX_HALF) | |
941 | fw_link_status = BNX2_LINK_STATUS_1000HALF; | |
942 | else | |
943 | fw_link_status = BNX2_LINK_STATUS_1000FULL; | |
944 | break; | |
945 | case SPEED_2500: | |
946 | if (bp->duplex == DUPLEX_HALF) | |
947 | fw_link_status = BNX2_LINK_STATUS_2500HALF; | |
948 | else | |
949 | fw_link_status = BNX2_LINK_STATUS_2500FULL; | |
950 | break; | |
951 | } | |
952 | ||
953 | fw_link_status |= BNX2_LINK_STATUS_LINK_UP; | |
954 | ||
955 | if (bp->autoneg) { | |
956 | fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED; | |
957 | ||
ca58c3af MC |
958 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
959 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | |
e3648b3d MC |
960 | |
961 | if (!(bmsr & BMSR_ANEGCOMPLETE) || | |
583c28e5 | 962 | bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) |
e3648b3d MC |
963 | fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET; |
964 | else | |
965 | fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE; | |
966 | } | |
967 | } | |
968 | else | |
969 | fw_link_status = BNX2_LINK_STATUS_LINK_DOWN; | |
970 | ||
2726d6e1 | 971 | bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status); |
e3648b3d MC |
972 | } |
973 | ||
9b1084b8 MC |
974 | static char * |
975 | bnx2_xceiver_str(struct bnx2 *bp) | |
976 | { | |
807540ba | 977 | return (bp->phy_port == PORT_FIBRE) ? "SerDes" : |
583c28e5 | 978 | ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" : |
807540ba | 979 | "Copper"); |
9b1084b8 MC |
980 | } |
981 | ||
b6016b76 MC |
982 | static void |
983 | bnx2_report_link(struct bnx2 *bp) | |
984 | { | |
985 | if (bp->link_up) { | |
986 | netif_carrier_on(bp->dev); | |
3a9c6a49 JP |
987 | netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex", |
988 | bnx2_xceiver_str(bp), | |
989 | bp->line_speed, | |
990 | bp->duplex == DUPLEX_FULL ? "full" : "half"); | |
b6016b76 MC |
991 | |
992 | if (bp->flow_ctrl) { | |
993 | if (bp->flow_ctrl & FLOW_CTRL_RX) { | |
3a9c6a49 | 994 | pr_cont(", receive "); |
b6016b76 | 995 | if (bp->flow_ctrl & FLOW_CTRL_TX) |
3a9c6a49 | 996 | pr_cont("& transmit "); |
b6016b76 MC |
997 | } |
998 | else { | |
3a9c6a49 | 999 | pr_cont(", transmit "); |
b6016b76 | 1000 | } |
3a9c6a49 | 1001 | pr_cont("flow control ON"); |
b6016b76 | 1002 | } |
3a9c6a49 JP |
1003 | pr_cont("\n"); |
1004 | } else { | |
b6016b76 | 1005 | netif_carrier_off(bp->dev); |
3a9c6a49 JP |
1006 | netdev_err(bp->dev, "NIC %s Link is Down\n", |
1007 | bnx2_xceiver_str(bp)); | |
b6016b76 | 1008 | } |
e3648b3d MC |
1009 | |
1010 | bnx2_report_fw_link(bp); | |
b6016b76 MC |
1011 | } |
1012 | ||
1013 | static void | |
1014 | bnx2_resolve_flow_ctrl(struct bnx2 *bp) | |
1015 | { | |
1016 | u32 local_adv, remote_adv; | |
1017 | ||
1018 | bp->flow_ctrl = 0; | |
6aa20a22 | 1019 | if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != |
b6016b76 MC |
1020 | (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { |
1021 | ||
1022 | if (bp->duplex == DUPLEX_FULL) { | |
1023 | bp->flow_ctrl = bp->req_flow_ctrl; | |
1024 | } | |
1025 | return; | |
1026 | } | |
1027 | ||
1028 | if (bp->duplex != DUPLEX_FULL) { | |
1029 | return; | |
1030 | } | |
1031 | ||
583c28e5 | 1032 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
4ce45e02 | 1033 | (BNX2_CHIP(bp) == BNX2_CHIP_5708)) { |
5b0c76ad MC |
1034 | u32 val; |
1035 | ||
1036 | bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); | |
1037 | if (val & BCM5708S_1000X_STAT1_TX_PAUSE) | |
1038 | bp->flow_ctrl |= FLOW_CTRL_TX; | |
1039 | if (val & BCM5708S_1000X_STAT1_RX_PAUSE) | |
1040 | bp->flow_ctrl |= FLOW_CTRL_RX; | |
1041 | return; | |
1042 | } | |
1043 | ||
ca58c3af MC |
1044 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
1045 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | |
b6016b76 | 1046 | |
583c28e5 | 1047 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
b6016b76 MC |
1048 | u32 new_local_adv = 0; |
1049 | u32 new_remote_adv = 0; | |
1050 | ||
1051 | if (local_adv & ADVERTISE_1000XPAUSE) | |
1052 | new_local_adv |= ADVERTISE_PAUSE_CAP; | |
1053 | if (local_adv & ADVERTISE_1000XPSE_ASYM) | |
1054 | new_local_adv |= ADVERTISE_PAUSE_ASYM; | |
1055 | if (remote_adv & ADVERTISE_1000XPAUSE) | |
1056 | new_remote_adv |= ADVERTISE_PAUSE_CAP; | |
1057 | if (remote_adv & ADVERTISE_1000XPSE_ASYM) | |
1058 | new_remote_adv |= ADVERTISE_PAUSE_ASYM; | |
1059 | ||
1060 | local_adv = new_local_adv; | |
1061 | remote_adv = new_remote_adv; | |
1062 | } | |
1063 | ||
1064 | /* See Table 28B-3 of 802.3ab-1999 spec. */ | |
1065 | if (local_adv & ADVERTISE_PAUSE_CAP) { | |
1066 | if(local_adv & ADVERTISE_PAUSE_ASYM) { | |
1067 | if (remote_adv & ADVERTISE_PAUSE_CAP) { | |
1068 | bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1069 | } | |
1070 | else if (remote_adv & ADVERTISE_PAUSE_ASYM) { | |
1071 | bp->flow_ctrl = FLOW_CTRL_RX; | |
1072 | } | |
1073 | } | |
1074 | else { | |
1075 | if (remote_adv & ADVERTISE_PAUSE_CAP) { | |
1076 | bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1077 | } | |
1078 | } | |
1079 | } | |
1080 | else if (local_adv & ADVERTISE_PAUSE_ASYM) { | |
1081 | if ((remote_adv & ADVERTISE_PAUSE_CAP) && | |
1082 | (remote_adv & ADVERTISE_PAUSE_ASYM)) { | |
1083 | ||
1084 | bp->flow_ctrl = FLOW_CTRL_TX; | |
1085 | } | |
1086 | } | |
1087 | } | |
1088 | ||
27a005b8 MC |
1089 | static int |
1090 | bnx2_5709s_linkup(struct bnx2 *bp) | |
1091 | { | |
1092 | u32 val, speed; | |
1093 | ||
1094 | bp->link_up = 1; | |
1095 | ||
1096 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); | |
1097 | bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val); | |
1098 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1099 | ||
1100 | if ((bp->autoneg & AUTONEG_SPEED) == 0) { | |
1101 | bp->line_speed = bp->req_line_speed; | |
1102 | bp->duplex = bp->req_duplex; | |
1103 | return 0; | |
1104 | } | |
1105 | speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK; | |
1106 | switch (speed) { | |
1107 | case MII_BNX2_GP_TOP_AN_SPEED_10: | |
1108 | bp->line_speed = SPEED_10; | |
1109 | break; | |
1110 | case MII_BNX2_GP_TOP_AN_SPEED_100: | |
1111 | bp->line_speed = SPEED_100; | |
1112 | break; | |
1113 | case MII_BNX2_GP_TOP_AN_SPEED_1G: | |
1114 | case MII_BNX2_GP_TOP_AN_SPEED_1GKV: | |
1115 | bp->line_speed = SPEED_1000; | |
1116 | break; | |
1117 | case MII_BNX2_GP_TOP_AN_SPEED_2_5G: | |
1118 | bp->line_speed = SPEED_2500; | |
1119 | break; | |
1120 | } | |
1121 | if (val & MII_BNX2_GP_TOP_AN_FD) | |
1122 | bp->duplex = DUPLEX_FULL; | |
1123 | else | |
1124 | bp->duplex = DUPLEX_HALF; | |
1125 | return 0; | |
1126 | } | |
1127 | ||
b6016b76 | 1128 | static int |
5b0c76ad MC |
1129 | bnx2_5708s_linkup(struct bnx2 *bp) |
1130 | { | |
1131 | u32 val; | |
1132 | ||
1133 | bp->link_up = 1; | |
1134 | bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); | |
1135 | switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) { | |
1136 | case BCM5708S_1000X_STAT1_SPEED_10: | |
1137 | bp->line_speed = SPEED_10; | |
1138 | break; | |
1139 | case BCM5708S_1000X_STAT1_SPEED_100: | |
1140 | bp->line_speed = SPEED_100; | |
1141 | break; | |
1142 | case BCM5708S_1000X_STAT1_SPEED_1G: | |
1143 | bp->line_speed = SPEED_1000; | |
1144 | break; | |
1145 | case BCM5708S_1000X_STAT1_SPEED_2G5: | |
1146 | bp->line_speed = SPEED_2500; | |
1147 | break; | |
1148 | } | |
1149 | if (val & BCM5708S_1000X_STAT1_FD) | |
1150 | bp->duplex = DUPLEX_FULL; | |
1151 | else | |
1152 | bp->duplex = DUPLEX_HALF; | |
1153 | ||
1154 | return 0; | |
1155 | } | |
1156 | ||
1157 | static int | |
1158 | bnx2_5706s_linkup(struct bnx2 *bp) | |
b6016b76 MC |
1159 | { |
1160 | u32 bmcr, local_adv, remote_adv, common; | |
1161 | ||
1162 | bp->link_up = 1; | |
1163 | bp->line_speed = SPEED_1000; | |
1164 | ||
ca58c3af | 1165 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 MC |
1166 | if (bmcr & BMCR_FULLDPLX) { |
1167 | bp->duplex = DUPLEX_FULL; | |
1168 | } | |
1169 | else { | |
1170 | bp->duplex = DUPLEX_HALF; | |
1171 | } | |
1172 | ||
1173 | if (!(bmcr & BMCR_ANENABLE)) { | |
1174 | return 0; | |
1175 | } | |
1176 | ||
ca58c3af MC |
1177 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
1178 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | |
b6016b76 MC |
1179 | |
1180 | common = local_adv & remote_adv; | |
1181 | if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { | |
1182 | ||
1183 | if (common & ADVERTISE_1000XFULL) { | |
1184 | bp->duplex = DUPLEX_FULL; | |
1185 | } | |
1186 | else { | |
1187 | bp->duplex = DUPLEX_HALF; | |
1188 | } | |
1189 | } | |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | static int | |
1195 | bnx2_copper_linkup(struct bnx2 *bp) | |
1196 | { | |
1197 | u32 bmcr; | |
1198 | ||
4016badd MC |
1199 | bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX; |
1200 | ||
ca58c3af | 1201 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 MC |
1202 | if (bmcr & BMCR_ANENABLE) { |
1203 | u32 local_adv, remote_adv, common; | |
1204 | ||
1205 | bnx2_read_phy(bp, MII_CTRL1000, &local_adv); | |
1206 | bnx2_read_phy(bp, MII_STAT1000, &remote_adv); | |
1207 | ||
1208 | common = local_adv & (remote_adv >> 2); | |
1209 | if (common & ADVERTISE_1000FULL) { | |
1210 | bp->line_speed = SPEED_1000; | |
1211 | bp->duplex = DUPLEX_FULL; | |
1212 | } | |
1213 | else if (common & ADVERTISE_1000HALF) { | |
1214 | bp->line_speed = SPEED_1000; | |
1215 | bp->duplex = DUPLEX_HALF; | |
1216 | } | |
1217 | else { | |
ca58c3af MC |
1218 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
1219 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | |
b6016b76 MC |
1220 | |
1221 | common = local_adv & remote_adv; | |
1222 | if (common & ADVERTISE_100FULL) { | |
1223 | bp->line_speed = SPEED_100; | |
1224 | bp->duplex = DUPLEX_FULL; | |
1225 | } | |
1226 | else if (common & ADVERTISE_100HALF) { | |
1227 | bp->line_speed = SPEED_100; | |
1228 | bp->duplex = DUPLEX_HALF; | |
1229 | } | |
1230 | else if (common & ADVERTISE_10FULL) { | |
1231 | bp->line_speed = SPEED_10; | |
1232 | bp->duplex = DUPLEX_FULL; | |
1233 | } | |
1234 | else if (common & ADVERTISE_10HALF) { | |
1235 | bp->line_speed = SPEED_10; | |
1236 | bp->duplex = DUPLEX_HALF; | |
1237 | } | |
1238 | else { | |
1239 | bp->line_speed = 0; | |
1240 | bp->link_up = 0; | |
1241 | } | |
1242 | } | |
1243 | } | |
1244 | else { | |
1245 | if (bmcr & BMCR_SPEED100) { | |
1246 | bp->line_speed = SPEED_100; | |
1247 | } | |
1248 | else { | |
1249 | bp->line_speed = SPEED_10; | |
1250 | } | |
1251 | if (bmcr & BMCR_FULLDPLX) { | |
1252 | bp->duplex = DUPLEX_FULL; | |
1253 | } | |
1254 | else { | |
1255 | bp->duplex = DUPLEX_HALF; | |
1256 | } | |
1257 | } | |
1258 | ||
4016badd MC |
1259 | if (bp->link_up) { |
1260 | u32 ext_status; | |
1261 | ||
1262 | bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status); | |
1263 | if (ext_status & EXT_STATUS_MDIX) | |
1264 | bp->phy_flags |= BNX2_PHY_FLAG_MDIX; | |
1265 | } | |
1266 | ||
b6016b76 MC |
1267 | return 0; |
1268 | } | |
1269 | ||
83e3fc89 | 1270 | static void |
bb4f98ab | 1271 | bnx2_init_rx_context(struct bnx2 *bp, u32 cid) |
83e3fc89 | 1272 | { |
bb4f98ab | 1273 | u32 val, rx_cid_addr = GET_CID_ADDR(cid); |
83e3fc89 MC |
1274 | |
1275 | val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; | |
1276 | val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; | |
1277 | val |= 0x02 << 8; | |
1278 | ||
22fa159d MC |
1279 | if (bp->flow_ctrl & FLOW_CTRL_TX) |
1280 | val |= BNX2_L2CTX_FLOW_CTRL_ENABLE; | |
83e3fc89 | 1281 | |
83e3fc89 MC |
1282 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); |
1283 | } | |
1284 | ||
bb4f98ab MC |
1285 | static void |
1286 | bnx2_init_all_rx_contexts(struct bnx2 *bp) | |
1287 | { | |
1288 | int i; | |
1289 | u32 cid; | |
1290 | ||
1291 | for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) { | |
1292 | if (i == 1) | |
1293 | cid = RX_RSS_CID; | |
1294 | bnx2_init_rx_context(bp, cid); | |
1295 | } | |
1296 | } | |
1297 | ||
344478db | 1298 | static void |
b6016b76 MC |
1299 | bnx2_set_mac_link(struct bnx2 *bp) |
1300 | { | |
1301 | u32 val; | |
1302 | ||
e503e066 | 1303 | BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); |
b6016b76 MC |
1304 | if (bp->link_up && (bp->line_speed == SPEED_1000) && |
1305 | (bp->duplex == DUPLEX_HALF)) { | |
e503e066 | 1306 | BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); |
b6016b76 MC |
1307 | } |
1308 | ||
1309 | /* Configure the EMAC mode register. */ | |
e503e066 | 1310 | val = BNX2_RD(bp, BNX2_EMAC_MODE); |
b6016b76 MC |
1311 | |
1312 | val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | | |
5b0c76ad | 1313 | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | |
59b47d8a | 1314 | BNX2_EMAC_MODE_25G_MODE); |
b6016b76 MC |
1315 | |
1316 | if (bp->link_up) { | |
5b0c76ad MC |
1317 | switch (bp->line_speed) { |
1318 | case SPEED_10: | |
4ce45e02 | 1319 | if (BNX2_CHIP(bp) != BNX2_CHIP_5706) { |
59b47d8a | 1320 | val |= BNX2_EMAC_MODE_PORT_MII_10M; |
5b0c76ad MC |
1321 | break; |
1322 | } | |
1323 | /* fall through */ | |
1324 | case SPEED_100: | |
1325 | val |= BNX2_EMAC_MODE_PORT_MII; | |
1326 | break; | |
1327 | case SPEED_2500: | |
59b47d8a | 1328 | val |= BNX2_EMAC_MODE_25G_MODE; |
5b0c76ad MC |
1329 | /* fall through */ |
1330 | case SPEED_1000: | |
1331 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
1332 | break; | |
1333 | } | |
b6016b76 MC |
1334 | } |
1335 | else { | |
1336 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
1337 | } | |
1338 | ||
1339 | /* Set the MAC to operate in the appropriate duplex mode. */ | |
1340 | if (bp->duplex == DUPLEX_HALF) | |
1341 | val |= BNX2_EMAC_MODE_HALF_DUPLEX; | |
e503e066 | 1342 | BNX2_WR(bp, BNX2_EMAC_MODE, val); |
b6016b76 MC |
1343 | |
1344 | /* Enable/disable rx PAUSE. */ | |
1345 | bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; | |
1346 | ||
1347 | if (bp->flow_ctrl & FLOW_CTRL_RX) | |
1348 | bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; | |
e503e066 | 1349 | BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); |
b6016b76 MC |
1350 | |
1351 | /* Enable/disable tx PAUSE. */ | |
e503e066 | 1352 | val = BNX2_RD(bp, BNX2_EMAC_TX_MODE); |
b6016b76 MC |
1353 | val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; |
1354 | ||
1355 | if (bp->flow_ctrl & FLOW_CTRL_TX) | |
1356 | val |= BNX2_EMAC_TX_MODE_FLOW_EN; | |
e503e066 | 1357 | BNX2_WR(bp, BNX2_EMAC_TX_MODE, val); |
b6016b76 MC |
1358 | |
1359 | /* Acknowledge the interrupt. */ | |
e503e066 | 1360 | BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); |
b6016b76 | 1361 | |
22fa159d | 1362 | bnx2_init_all_rx_contexts(bp); |
b6016b76 MC |
1363 | } |
1364 | ||
27a005b8 MC |
1365 | static void |
1366 | bnx2_enable_bmsr1(struct bnx2 *bp) | |
1367 | { | |
583c28e5 | 1368 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
4ce45e02 | 1369 | (BNX2_CHIP(bp) == BNX2_CHIP_5709)) |
27a005b8 MC |
1370 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1371 | MII_BNX2_BLK_ADDR_GP_STATUS); | |
1372 | } | |
1373 | ||
1374 | static void | |
1375 | bnx2_disable_bmsr1(struct bnx2 *bp) | |
1376 | { | |
583c28e5 | 1377 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
4ce45e02 | 1378 | (BNX2_CHIP(bp) == BNX2_CHIP_5709)) |
27a005b8 MC |
1379 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1380 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1381 | } | |
1382 | ||
605a9e20 MC |
1383 | static int |
1384 | bnx2_test_and_enable_2g5(struct bnx2 *bp) | |
1385 | { | |
1386 | u32 up1; | |
1387 | int ret = 1; | |
1388 | ||
583c28e5 | 1389 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
605a9e20 MC |
1390 | return 0; |
1391 | ||
1392 | if (bp->autoneg & AUTONEG_SPEED) | |
1393 | bp->advertising |= ADVERTISED_2500baseX_Full; | |
1394 | ||
4ce45e02 | 1395 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
27a005b8 MC |
1396 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); |
1397 | ||
605a9e20 MC |
1398 | bnx2_read_phy(bp, bp->mii_up1, &up1); |
1399 | if (!(up1 & BCM5708S_UP1_2G5)) { | |
1400 | up1 |= BCM5708S_UP1_2G5; | |
1401 | bnx2_write_phy(bp, bp->mii_up1, up1); | |
1402 | ret = 0; | |
1403 | } | |
1404 | ||
4ce45e02 | 1405 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
27a005b8 MC |
1406 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1407 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1408 | ||
605a9e20 MC |
1409 | return ret; |
1410 | } | |
1411 | ||
1412 | static int | |
1413 | bnx2_test_and_disable_2g5(struct bnx2 *bp) | |
1414 | { | |
1415 | u32 up1; | |
1416 | int ret = 0; | |
1417 | ||
583c28e5 | 1418 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
605a9e20 MC |
1419 | return 0; |
1420 | ||
4ce45e02 | 1421 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
27a005b8 MC |
1422 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); |
1423 | ||
605a9e20 MC |
1424 | bnx2_read_phy(bp, bp->mii_up1, &up1); |
1425 | if (up1 & BCM5708S_UP1_2G5) { | |
1426 | up1 &= ~BCM5708S_UP1_2G5; | |
1427 | bnx2_write_phy(bp, bp->mii_up1, up1); | |
1428 | ret = 1; | |
1429 | } | |
1430 | ||
4ce45e02 | 1431 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
27a005b8 MC |
1432 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1433 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1434 | ||
605a9e20 MC |
1435 | return ret; |
1436 | } | |
1437 | ||
1438 | static void | |
1439 | bnx2_enable_forced_2g5(struct bnx2 *bp) | |
1440 | { | |
cbd6890c MC |
1441 | u32 uninitialized_var(bmcr); |
1442 | int err; | |
605a9e20 | 1443 | |
583c28e5 | 1444 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
605a9e20 MC |
1445 | return; |
1446 | ||
4ce45e02 | 1447 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
27a005b8 MC |
1448 | u32 val; |
1449 | ||
1450 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1451 | MII_BNX2_BLK_ADDR_SERDES_DIG); | |
cbd6890c MC |
1452 | if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { |
1453 | val &= ~MII_BNX2_SD_MISC1_FORCE_MSK; | |
1454 | val |= MII_BNX2_SD_MISC1_FORCE | | |
1455 | MII_BNX2_SD_MISC1_FORCE_2_5G; | |
1456 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); | |
1457 | } | |
27a005b8 MC |
1458 | |
1459 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1460 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
cbd6890c | 1461 | err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
27a005b8 | 1462 | |
4ce45e02 | 1463 | } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { |
cbd6890c MC |
1464 | err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1465 | if (!err) | |
1466 | bmcr |= BCM5708S_BMCR_FORCE_2500; | |
c7079857 ED |
1467 | } else { |
1468 | return; | |
605a9e20 MC |
1469 | } |
1470 | ||
cbd6890c MC |
1471 | if (err) |
1472 | return; | |
1473 | ||
605a9e20 MC |
1474 | if (bp->autoneg & AUTONEG_SPEED) { |
1475 | bmcr &= ~BMCR_ANENABLE; | |
1476 | if (bp->req_duplex == DUPLEX_FULL) | |
1477 | bmcr |= BMCR_FULLDPLX; | |
1478 | } | |
1479 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | |
1480 | } | |
1481 | ||
1482 | static void | |
1483 | bnx2_disable_forced_2g5(struct bnx2 *bp) | |
1484 | { | |
cbd6890c MC |
1485 | u32 uninitialized_var(bmcr); |
1486 | int err; | |
605a9e20 | 1487 | |
583c28e5 | 1488 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
605a9e20 MC |
1489 | return; |
1490 | ||
4ce45e02 | 1491 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
27a005b8 MC |
1492 | u32 val; |
1493 | ||
1494 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1495 | MII_BNX2_BLK_ADDR_SERDES_DIG); | |
cbd6890c MC |
1496 | if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { |
1497 | val &= ~MII_BNX2_SD_MISC1_FORCE; | |
1498 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); | |
1499 | } | |
27a005b8 MC |
1500 | |
1501 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1502 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
cbd6890c | 1503 | err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
27a005b8 | 1504 | |
4ce45e02 | 1505 | } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { |
cbd6890c MC |
1506 | err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1507 | if (!err) | |
1508 | bmcr &= ~BCM5708S_BMCR_FORCE_2500; | |
c7079857 ED |
1509 | } else { |
1510 | return; | |
605a9e20 MC |
1511 | } |
1512 | ||
cbd6890c MC |
1513 | if (err) |
1514 | return; | |
1515 | ||
605a9e20 MC |
1516 | if (bp->autoneg & AUTONEG_SPEED) |
1517 | bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART; | |
1518 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | |
1519 | } | |
1520 | ||
b2fadeae MC |
1521 | static void |
1522 | bnx2_5706s_force_link_dn(struct bnx2 *bp, int start) | |
1523 | { | |
1524 | u32 val; | |
1525 | ||
1526 | bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL); | |
1527 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); | |
1528 | if (start) | |
1529 | bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); | |
1530 | else | |
1531 | bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); | |
1532 | } | |
1533 | ||
b6016b76 MC |
1534 | static int |
1535 | bnx2_set_link(struct bnx2 *bp) | |
1536 | { | |
1537 | u32 bmsr; | |
1538 | u8 link_up; | |
1539 | ||
80be4434 | 1540 | if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) { |
b6016b76 MC |
1541 | bp->link_up = 1; |
1542 | return 0; | |
1543 | } | |
1544 | ||
583c28e5 | 1545 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
1546 | return 0; |
1547 | ||
b6016b76 MC |
1548 | link_up = bp->link_up; |
1549 | ||
27a005b8 MC |
1550 | bnx2_enable_bmsr1(bp); |
1551 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
1552 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
1553 | bnx2_disable_bmsr1(bp); | |
b6016b76 | 1554 | |
583c28e5 | 1555 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
4ce45e02 | 1556 | (BNX2_CHIP(bp) == BNX2_CHIP_5706)) { |
a2724e25 | 1557 | u32 val, an_dbg; |
b6016b76 | 1558 | |
583c28e5 | 1559 | if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { |
b2fadeae | 1560 | bnx2_5706s_force_link_dn(bp, 0); |
583c28e5 | 1561 | bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; |
b2fadeae | 1562 | } |
e503e066 | 1563 | val = BNX2_RD(bp, BNX2_EMAC_STATUS); |
a2724e25 MC |
1564 | |
1565 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); | |
1566 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | |
1567 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | |
1568 | ||
1569 | if ((val & BNX2_EMAC_STATUS_LINK) && | |
1570 | !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC)) | |
b6016b76 MC |
1571 | bmsr |= BMSR_LSTATUS; |
1572 | else | |
1573 | bmsr &= ~BMSR_LSTATUS; | |
1574 | } | |
1575 | ||
1576 | if (bmsr & BMSR_LSTATUS) { | |
1577 | bp->link_up = 1; | |
1578 | ||
583c28e5 | 1579 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
4ce45e02 | 1580 | if (BNX2_CHIP(bp) == BNX2_CHIP_5706) |
5b0c76ad | 1581 | bnx2_5706s_linkup(bp); |
4ce45e02 | 1582 | else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) |
5b0c76ad | 1583 | bnx2_5708s_linkup(bp); |
4ce45e02 | 1584 | else if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
27a005b8 | 1585 | bnx2_5709s_linkup(bp); |
b6016b76 MC |
1586 | } |
1587 | else { | |
1588 | bnx2_copper_linkup(bp); | |
1589 | } | |
1590 | bnx2_resolve_flow_ctrl(bp); | |
1591 | } | |
1592 | else { | |
583c28e5 | 1593 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
605a9e20 MC |
1594 | (bp->autoneg & AUTONEG_SPEED)) |
1595 | bnx2_disable_forced_2g5(bp); | |
b6016b76 | 1596 | |
583c28e5 | 1597 | if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) { |
b2fadeae MC |
1598 | u32 bmcr; |
1599 | ||
1600 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | |
1601 | bmcr |= BMCR_ANENABLE; | |
1602 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | |
1603 | ||
583c28e5 | 1604 | bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; |
b2fadeae | 1605 | } |
b6016b76 MC |
1606 | bp->link_up = 0; |
1607 | } | |
1608 | ||
1609 | if (bp->link_up != link_up) { | |
1610 | bnx2_report_link(bp); | |
1611 | } | |
1612 | ||
1613 | bnx2_set_mac_link(bp); | |
1614 | ||
1615 | return 0; | |
1616 | } | |
1617 | ||
1618 | static int | |
1619 | bnx2_reset_phy(struct bnx2 *bp) | |
1620 | { | |
1621 | int i; | |
1622 | u32 reg; | |
1623 | ||
ca58c3af | 1624 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); |
b6016b76 MC |
1625 | |
1626 | #define PHY_RESET_MAX_WAIT 100 | |
1627 | for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { | |
1628 | udelay(10); | |
1629 | ||
ca58c3af | 1630 | bnx2_read_phy(bp, bp->mii_bmcr, ®); |
b6016b76 MC |
1631 | if (!(reg & BMCR_RESET)) { |
1632 | udelay(20); | |
1633 | break; | |
1634 | } | |
1635 | } | |
1636 | if (i == PHY_RESET_MAX_WAIT) { | |
1637 | return -EBUSY; | |
1638 | } | |
1639 | return 0; | |
1640 | } | |
1641 | ||
1642 | static u32 | |
1643 | bnx2_phy_get_pause_adv(struct bnx2 *bp) | |
1644 | { | |
1645 | u32 adv = 0; | |
1646 | ||
1647 | if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == | |
1648 | (FLOW_CTRL_RX | FLOW_CTRL_TX)) { | |
1649 | ||
583c28e5 | 1650 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
b6016b76 MC |
1651 | adv = ADVERTISE_1000XPAUSE; |
1652 | } | |
1653 | else { | |
1654 | adv = ADVERTISE_PAUSE_CAP; | |
1655 | } | |
1656 | } | |
1657 | else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { | |
583c28e5 | 1658 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
b6016b76 MC |
1659 | adv = ADVERTISE_1000XPSE_ASYM; |
1660 | } | |
1661 | else { | |
1662 | adv = ADVERTISE_PAUSE_ASYM; | |
1663 | } | |
1664 | } | |
1665 | else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { | |
583c28e5 | 1666 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
b6016b76 MC |
1667 | adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1668 | } | |
1669 | else { | |
1670 | adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
1671 | } | |
1672 | } | |
1673 | return adv; | |
1674 | } | |
1675 | ||
a2f13890 | 1676 | static int bnx2_fw_sync(struct bnx2 *, u32, int, int); |
0d8a6571 | 1677 | |
b6016b76 | 1678 | static int |
0d8a6571 | 1679 | bnx2_setup_remote_phy(struct bnx2 *bp, u8 port) |
52d07b1f HH |
1680 | __releases(&bp->phy_lock) |
1681 | __acquires(&bp->phy_lock) | |
0d8a6571 MC |
1682 | { |
1683 | u32 speed_arg = 0, pause_adv; | |
1684 | ||
1685 | pause_adv = bnx2_phy_get_pause_adv(bp); | |
1686 | ||
1687 | if (bp->autoneg & AUTONEG_SPEED) { | |
1688 | speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG; | |
1689 | if (bp->advertising & ADVERTISED_10baseT_Half) | |
1690 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF; | |
1691 | if (bp->advertising & ADVERTISED_10baseT_Full) | |
1692 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL; | |
1693 | if (bp->advertising & ADVERTISED_100baseT_Half) | |
1694 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF; | |
1695 | if (bp->advertising & ADVERTISED_100baseT_Full) | |
1696 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL; | |
1697 | if (bp->advertising & ADVERTISED_1000baseT_Full) | |
1698 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL; | |
1699 | if (bp->advertising & ADVERTISED_2500baseX_Full) | |
1700 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; | |
1701 | } else { | |
1702 | if (bp->req_line_speed == SPEED_2500) | |
1703 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; | |
1704 | else if (bp->req_line_speed == SPEED_1000) | |
1705 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL; | |
1706 | else if (bp->req_line_speed == SPEED_100) { | |
1707 | if (bp->req_duplex == DUPLEX_FULL) | |
1708 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL; | |
1709 | else | |
1710 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF; | |
1711 | } else if (bp->req_line_speed == SPEED_10) { | |
1712 | if (bp->req_duplex == DUPLEX_FULL) | |
1713 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL; | |
1714 | else | |
1715 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF; | |
1716 | } | |
1717 | } | |
1718 | ||
1719 | if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP)) | |
1720 | speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE; | |
c26736ec | 1721 | if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM)) |
0d8a6571 MC |
1722 | speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE; |
1723 | ||
1724 | if (port == PORT_TP) | |
1725 | speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE | | |
1726 | BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED; | |
1727 | ||
2726d6e1 | 1728 | bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg); |
0d8a6571 MC |
1729 | |
1730 | spin_unlock_bh(&bp->phy_lock); | |
a2f13890 | 1731 | bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0); |
0d8a6571 MC |
1732 | spin_lock_bh(&bp->phy_lock); |
1733 | ||
1734 | return 0; | |
1735 | } | |
1736 | ||
1737 | static int | |
1738 | bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port) | |
52d07b1f HH |
1739 | __releases(&bp->phy_lock) |
1740 | __acquires(&bp->phy_lock) | |
b6016b76 | 1741 | { |
605a9e20 | 1742 | u32 adv, bmcr; |
b6016b76 MC |
1743 | u32 new_adv = 0; |
1744 | ||
583c28e5 | 1745 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
807540ba | 1746 | return bnx2_setup_remote_phy(bp, port); |
0d8a6571 | 1747 | |
b6016b76 MC |
1748 | if (!(bp->autoneg & AUTONEG_SPEED)) { |
1749 | u32 new_bmcr; | |
5b0c76ad MC |
1750 | int force_link_down = 0; |
1751 | ||
605a9e20 MC |
1752 | if (bp->req_line_speed == SPEED_2500) { |
1753 | if (!bnx2_test_and_enable_2g5(bp)) | |
1754 | force_link_down = 1; | |
1755 | } else if (bp->req_line_speed == SPEED_1000) { | |
1756 | if (bnx2_test_and_disable_2g5(bp)) | |
1757 | force_link_down = 1; | |
1758 | } | |
ca58c3af | 1759 | bnx2_read_phy(bp, bp->mii_adv, &adv); |
80be4434 MC |
1760 | adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); |
1761 | ||
ca58c3af | 1762 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
605a9e20 | 1763 | new_bmcr = bmcr & ~BMCR_ANENABLE; |
80be4434 | 1764 | new_bmcr |= BMCR_SPEED1000; |
605a9e20 | 1765 | |
4ce45e02 | 1766 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
27a005b8 MC |
1767 | if (bp->req_line_speed == SPEED_2500) |
1768 | bnx2_enable_forced_2g5(bp); | |
1769 | else if (bp->req_line_speed == SPEED_1000) { | |
1770 | bnx2_disable_forced_2g5(bp); | |
1771 | new_bmcr &= ~0x2000; | |
1772 | } | |
1773 | ||
4ce45e02 | 1774 | } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { |
605a9e20 MC |
1775 | if (bp->req_line_speed == SPEED_2500) |
1776 | new_bmcr |= BCM5708S_BMCR_FORCE_2500; | |
1777 | else | |
1778 | new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500; | |
5b0c76ad MC |
1779 | } |
1780 | ||
b6016b76 | 1781 | if (bp->req_duplex == DUPLEX_FULL) { |
5b0c76ad | 1782 | adv |= ADVERTISE_1000XFULL; |
b6016b76 MC |
1783 | new_bmcr |= BMCR_FULLDPLX; |
1784 | } | |
1785 | else { | |
5b0c76ad | 1786 | adv |= ADVERTISE_1000XHALF; |
b6016b76 MC |
1787 | new_bmcr &= ~BMCR_FULLDPLX; |
1788 | } | |
5b0c76ad | 1789 | if ((new_bmcr != bmcr) || (force_link_down)) { |
b6016b76 MC |
1790 | /* Force a link down visible on the other side */ |
1791 | if (bp->link_up) { | |
ca58c3af | 1792 | bnx2_write_phy(bp, bp->mii_adv, adv & |
5b0c76ad MC |
1793 | ~(ADVERTISE_1000XFULL | |
1794 | ADVERTISE_1000XHALF)); | |
ca58c3af | 1795 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr | |
b6016b76 MC |
1796 | BMCR_ANRESTART | BMCR_ANENABLE); |
1797 | ||
1798 | bp->link_up = 0; | |
1799 | netif_carrier_off(bp->dev); | |
ca58c3af | 1800 | bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); |
80be4434 | 1801 | bnx2_report_link(bp); |
b6016b76 | 1802 | } |
ca58c3af MC |
1803 | bnx2_write_phy(bp, bp->mii_adv, adv); |
1804 | bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); | |
605a9e20 MC |
1805 | } else { |
1806 | bnx2_resolve_flow_ctrl(bp); | |
1807 | bnx2_set_mac_link(bp); | |
b6016b76 MC |
1808 | } |
1809 | return 0; | |
1810 | } | |
1811 | ||
605a9e20 | 1812 | bnx2_test_and_enable_2g5(bp); |
5b0c76ad | 1813 | |
b6016b76 MC |
1814 | if (bp->advertising & ADVERTISED_1000baseT_Full) |
1815 | new_adv |= ADVERTISE_1000XFULL; | |
1816 | ||
1817 | new_adv |= bnx2_phy_get_pause_adv(bp); | |
1818 | ||
ca58c3af MC |
1819 | bnx2_read_phy(bp, bp->mii_adv, &adv); |
1820 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | |
b6016b76 MC |
1821 | |
1822 | bp->serdes_an_pending = 0; | |
1823 | if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { | |
1824 | /* Force a link down visible on the other side */ | |
1825 | if (bp->link_up) { | |
ca58c3af | 1826 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
80be4434 MC |
1827 | spin_unlock_bh(&bp->phy_lock); |
1828 | msleep(20); | |
1829 | spin_lock_bh(&bp->phy_lock); | |
b6016b76 MC |
1830 | } |
1831 | ||
ca58c3af MC |
1832 | bnx2_write_phy(bp, bp->mii_adv, new_adv); |
1833 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | | |
b6016b76 | 1834 | BMCR_ANENABLE); |
f8dd064e MC |
1835 | /* Speed up link-up time when the link partner |
1836 | * does not autonegotiate which is very common | |
1837 | * in blade servers. Some blade servers use | |
1838 | * IPMI for kerboard input and it's important | |
1839 | * to minimize link disruptions. Autoneg. involves | |
1840 | * exchanging base pages plus 3 next pages and | |
1841 | * normally completes in about 120 msec. | |
1842 | */ | |
40105c0b | 1843 | bp->current_interval = BNX2_SERDES_AN_TIMEOUT; |
f8dd064e MC |
1844 | bp->serdes_an_pending = 1; |
1845 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
605a9e20 MC |
1846 | } else { |
1847 | bnx2_resolve_flow_ctrl(bp); | |
1848 | bnx2_set_mac_link(bp); | |
b6016b76 MC |
1849 | } |
1850 | ||
1851 | return 0; | |
1852 | } | |
1853 | ||
1854 | #define ETHTOOL_ALL_FIBRE_SPEED \ | |
583c28e5 | 1855 | (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \ |
deaf391b MC |
1856 | (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\ |
1857 | (ADVERTISED_1000baseT_Full) | |
b6016b76 MC |
1858 | |
1859 | #define ETHTOOL_ALL_COPPER_SPEED \ | |
1860 | (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ | |
1861 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ | |
1862 | ADVERTISED_1000baseT_Full) | |
1863 | ||
1864 | #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ | |
1865 | ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) | |
6aa20a22 | 1866 | |
b6016b76 MC |
1867 | #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) |
1868 | ||
0d8a6571 MC |
1869 | static void |
1870 | bnx2_set_default_remote_link(struct bnx2 *bp) | |
1871 | { | |
1872 | u32 link; | |
1873 | ||
1874 | if (bp->phy_port == PORT_TP) | |
2726d6e1 | 1875 | link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK); |
0d8a6571 | 1876 | else |
2726d6e1 | 1877 | link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK); |
0d8a6571 MC |
1878 | |
1879 | if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) { | |
1880 | bp->req_line_speed = 0; | |
1881 | bp->autoneg |= AUTONEG_SPEED; | |
1882 | bp->advertising = ADVERTISED_Autoneg; | |
1883 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) | |
1884 | bp->advertising |= ADVERTISED_10baseT_Half; | |
1885 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL) | |
1886 | bp->advertising |= ADVERTISED_10baseT_Full; | |
1887 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) | |
1888 | bp->advertising |= ADVERTISED_100baseT_Half; | |
1889 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL) | |
1890 | bp->advertising |= ADVERTISED_100baseT_Full; | |
1891 | if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) | |
1892 | bp->advertising |= ADVERTISED_1000baseT_Full; | |
1893 | if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) | |
1894 | bp->advertising |= ADVERTISED_2500baseX_Full; | |
1895 | } else { | |
1896 | bp->autoneg = 0; | |
1897 | bp->advertising = 0; | |
1898 | bp->req_duplex = DUPLEX_FULL; | |
1899 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10) { | |
1900 | bp->req_line_speed = SPEED_10; | |
1901 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) | |
1902 | bp->req_duplex = DUPLEX_HALF; | |
1903 | } | |
1904 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100) { | |
1905 | bp->req_line_speed = SPEED_100; | |
1906 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) | |
1907 | bp->req_duplex = DUPLEX_HALF; | |
1908 | } | |
1909 | if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) | |
1910 | bp->req_line_speed = SPEED_1000; | |
1911 | if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) | |
1912 | bp->req_line_speed = SPEED_2500; | |
1913 | } | |
1914 | } | |
1915 | ||
deaf391b MC |
1916 | static void |
1917 | bnx2_set_default_link(struct bnx2 *bp) | |
1918 | { | |
ab59859d HH |
1919 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
1920 | bnx2_set_default_remote_link(bp); | |
1921 | return; | |
1922 | } | |
0d8a6571 | 1923 | |
deaf391b MC |
1924 | bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; |
1925 | bp->req_line_speed = 0; | |
583c28e5 | 1926 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
deaf391b MC |
1927 | u32 reg; |
1928 | ||
1929 | bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; | |
1930 | ||
2726d6e1 | 1931 | reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG); |
deaf391b MC |
1932 | reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; |
1933 | if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { | |
1934 | bp->autoneg = 0; | |
1935 | bp->req_line_speed = bp->line_speed = SPEED_1000; | |
1936 | bp->req_duplex = DUPLEX_FULL; | |
1937 | } | |
1938 | } else | |
1939 | bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; | |
1940 | } | |
1941 | ||
df149d70 MC |
1942 | static void |
1943 | bnx2_send_heart_beat(struct bnx2 *bp) | |
1944 | { | |
1945 | u32 msg; | |
1946 | u32 addr; | |
1947 | ||
1948 | spin_lock(&bp->indirect_lock); | |
1949 | msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK); | |
1950 | addr = bp->shmem_base + BNX2_DRV_PULSE_MB; | |
e503e066 MC |
1951 | BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr); |
1952 | BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg); | |
df149d70 MC |
1953 | spin_unlock(&bp->indirect_lock); |
1954 | } | |
1955 | ||
0d8a6571 MC |
1956 | static void |
1957 | bnx2_remote_phy_event(struct bnx2 *bp) | |
1958 | { | |
1959 | u32 msg; | |
1960 | u8 link_up = bp->link_up; | |
1961 | u8 old_port; | |
1962 | ||
2726d6e1 | 1963 | msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); |
0d8a6571 | 1964 | |
df149d70 MC |
1965 | if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED) |
1966 | bnx2_send_heart_beat(bp); | |
1967 | ||
1968 | msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED; | |
1969 | ||
0d8a6571 MC |
1970 | if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN) |
1971 | bp->link_up = 0; | |
1972 | else { | |
1973 | u32 speed; | |
1974 | ||
1975 | bp->link_up = 1; | |
1976 | speed = msg & BNX2_LINK_STATUS_SPEED_MASK; | |
1977 | bp->duplex = DUPLEX_FULL; | |
1978 | switch (speed) { | |
1979 | case BNX2_LINK_STATUS_10HALF: | |
1980 | bp->duplex = DUPLEX_HALF; | |
7947c9ce | 1981 | /* fall through */ |
0d8a6571 MC |
1982 | case BNX2_LINK_STATUS_10FULL: |
1983 | bp->line_speed = SPEED_10; | |
1984 | break; | |
1985 | case BNX2_LINK_STATUS_100HALF: | |
1986 | bp->duplex = DUPLEX_HALF; | |
7947c9ce | 1987 | /* fall through */ |
0d8a6571 MC |
1988 | case BNX2_LINK_STATUS_100BASE_T4: |
1989 | case BNX2_LINK_STATUS_100FULL: | |
1990 | bp->line_speed = SPEED_100; | |
1991 | break; | |
1992 | case BNX2_LINK_STATUS_1000HALF: | |
1993 | bp->duplex = DUPLEX_HALF; | |
7947c9ce | 1994 | /* fall through */ |
0d8a6571 MC |
1995 | case BNX2_LINK_STATUS_1000FULL: |
1996 | bp->line_speed = SPEED_1000; | |
1997 | break; | |
1998 | case BNX2_LINK_STATUS_2500HALF: | |
1999 | bp->duplex = DUPLEX_HALF; | |
7947c9ce | 2000 | /* fall through */ |
0d8a6571 MC |
2001 | case BNX2_LINK_STATUS_2500FULL: |
2002 | bp->line_speed = SPEED_2500; | |
2003 | break; | |
2004 | default: | |
2005 | bp->line_speed = 0; | |
2006 | break; | |
2007 | } | |
2008 | ||
0d8a6571 MC |
2009 | bp->flow_ctrl = 0; |
2010 | if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != | |
2011 | (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { | |
2012 | if (bp->duplex == DUPLEX_FULL) | |
2013 | bp->flow_ctrl = bp->req_flow_ctrl; | |
2014 | } else { | |
2015 | if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED) | |
2016 | bp->flow_ctrl |= FLOW_CTRL_TX; | |
2017 | if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED) | |
2018 | bp->flow_ctrl |= FLOW_CTRL_RX; | |
2019 | } | |
2020 | ||
2021 | old_port = bp->phy_port; | |
2022 | if (msg & BNX2_LINK_STATUS_SERDES_LINK) | |
2023 | bp->phy_port = PORT_FIBRE; | |
2024 | else | |
2025 | bp->phy_port = PORT_TP; | |
2026 | ||
2027 | if (old_port != bp->phy_port) | |
2028 | bnx2_set_default_link(bp); | |
2029 | ||
0d8a6571 MC |
2030 | } |
2031 | if (bp->link_up != link_up) | |
2032 | bnx2_report_link(bp); | |
2033 | ||
2034 | bnx2_set_mac_link(bp); | |
2035 | } | |
2036 | ||
2037 | static int | |
2038 | bnx2_set_remote_link(struct bnx2 *bp) | |
2039 | { | |
2040 | u32 evt_code; | |
2041 | ||
2726d6e1 | 2042 | evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB); |
0d8a6571 MC |
2043 | switch (evt_code) { |
2044 | case BNX2_FW_EVT_CODE_LINK_EVENT: | |
2045 | bnx2_remote_phy_event(bp); | |
2046 | break; | |
2047 | case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT: | |
2048 | default: | |
df149d70 | 2049 | bnx2_send_heart_beat(bp); |
0d8a6571 MC |
2050 | break; |
2051 | } | |
2052 | return 0; | |
2053 | } | |
2054 | ||
b6016b76 MC |
2055 | static int |
2056 | bnx2_setup_copper_phy(struct bnx2 *bp) | |
52d07b1f HH |
2057 | __releases(&bp->phy_lock) |
2058 | __acquires(&bp->phy_lock) | |
b6016b76 | 2059 | { |
d17e53bd | 2060 | u32 bmcr, adv_reg, new_adv = 0; |
b6016b76 MC |
2061 | u32 new_bmcr; |
2062 | ||
ca58c3af | 2063 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 | 2064 | |
d17e53bd MC |
2065 | bnx2_read_phy(bp, bp->mii_adv, &adv_reg); |
2066 | adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP | | |
2067 | ADVERTISE_PAUSE_ASYM); | |
2068 | ||
2069 | new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising); | |
2070 | ||
b6016b76 | 2071 | if (bp->autoneg & AUTONEG_SPEED) { |
d17e53bd | 2072 | u32 adv1000_reg; |
37f07023 | 2073 | u32 new_adv1000 = 0; |
b6016b76 | 2074 | |
d17e53bd | 2075 | new_adv |= bnx2_phy_get_pause_adv(bp); |
b6016b76 MC |
2076 | |
2077 | bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg); | |
2078 | adv1000_reg &= PHY_ALL_1000_SPEED; | |
2079 | ||
37f07023 | 2080 | new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising); |
37f07023 MC |
2081 | if ((adv1000_reg != new_adv1000) || |
2082 | (adv_reg != new_adv) || | |
b6016b76 MC |
2083 | ((bmcr & BMCR_ANENABLE) == 0)) { |
2084 | ||
37f07023 MC |
2085 | bnx2_write_phy(bp, bp->mii_adv, new_adv); |
2086 | bnx2_write_phy(bp, MII_CTRL1000, new_adv1000); | |
ca58c3af | 2087 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | |
b6016b76 MC |
2088 | BMCR_ANENABLE); |
2089 | } | |
2090 | else if (bp->link_up) { | |
2091 | /* Flow ctrl may have changed from auto to forced */ | |
2092 | /* or vice-versa. */ | |
2093 | ||
2094 | bnx2_resolve_flow_ctrl(bp); | |
2095 | bnx2_set_mac_link(bp); | |
2096 | } | |
2097 | return 0; | |
2098 | } | |
2099 | ||
d17e53bd MC |
2100 | /* advertise nothing when forcing speed */ |
2101 | if (adv_reg != new_adv) | |
2102 | bnx2_write_phy(bp, bp->mii_adv, new_adv); | |
2103 | ||
b6016b76 MC |
2104 | new_bmcr = 0; |
2105 | if (bp->req_line_speed == SPEED_100) { | |
2106 | new_bmcr |= BMCR_SPEED100; | |
2107 | } | |
2108 | if (bp->req_duplex == DUPLEX_FULL) { | |
2109 | new_bmcr |= BMCR_FULLDPLX; | |
2110 | } | |
2111 | if (new_bmcr != bmcr) { | |
2112 | u32 bmsr; | |
b6016b76 | 2113 | |
ca58c3af MC |
2114 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
2115 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | |
6aa20a22 | 2116 | |
b6016b76 MC |
2117 | if (bmsr & BMSR_LSTATUS) { |
2118 | /* Force link down */ | |
ca58c3af | 2119 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
a16dda0e MC |
2120 | spin_unlock_bh(&bp->phy_lock); |
2121 | msleep(50); | |
2122 | spin_lock_bh(&bp->phy_lock); | |
2123 | ||
ca58c3af MC |
2124 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
2125 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | |
b6016b76 MC |
2126 | } |
2127 | ||
ca58c3af | 2128 | bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); |
b6016b76 MC |
2129 | |
2130 | /* Normally, the new speed is setup after the link has | |
2131 | * gone down and up again. In some cases, link will not go | |
2132 | * down so we need to set up the new speed here. | |
2133 | */ | |
2134 | if (bmsr & BMSR_LSTATUS) { | |
2135 | bp->line_speed = bp->req_line_speed; | |
2136 | bp->duplex = bp->req_duplex; | |
2137 | bnx2_resolve_flow_ctrl(bp); | |
2138 | bnx2_set_mac_link(bp); | |
2139 | } | |
27a005b8 MC |
2140 | } else { |
2141 | bnx2_resolve_flow_ctrl(bp); | |
2142 | bnx2_set_mac_link(bp); | |
b6016b76 MC |
2143 | } |
2144 | return 0; | |
2145 | } | |
2146 | ||
2147 | static int | |
0d8a6571 | 2148 | bnx2_setup_phy(struct bnx2 *bp, u8 port) |
52d07b1f HH |
2149 | __releases(&bp->phy_lock) |
2150 | __acquires(&bp->phy_lock) | |
b6016b76 MC |
2151 | { |
2152 | if (bp->loopback == MAC_LOOPBACK) | |
2153 | return 0; | |
2154 | ||
583c28e5 | 2155 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
807540ba | 2156 | return bnx2_setup_serdes_phy(bp, port); |
b6016b76 MC |
2157 | } |
2158 | else { | |
807540ba | 2159 | return bnx2_setup_copper_phy(bp); |
b6016b76 MC |
2160 | } |
2161 | } | |
2162 | ||
27a005b8 | 2163 | static int |
9a120bc5 | 2164 | bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy) |
27a005b8 MC |
2165 | { |
2166 | u32 val; | |
2167 | ||
2168 | bp->mii_bmcr = MII_BMCR + 0x10; | |
2169 | bp->mii_bmsr = MII_BMSR + 0x10; | |
2170 | bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1; | |
2171 | bp->mii_adv = MII_ADVERTISE + 0x10; | |
2172 | bp->mii_lpa = MII_LPA + 0x10; | |
2173 | bp->mii_up1 = MII_BNX2_OVER1G_UP1; | |
2174 | ||
2175 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER); | |
2176 | bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); | |
2177 | ||
2178 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
9a120bc5 MC |
2179 | if (reset_phy) |
2180 | bnx2_reset_phy(bp); | |
27a005b8 MC |
2181 | |
2182 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); | |
2183 | ||
2184 | bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val); | |
2185 | val &= ~MII_BNX2_SD_1000XCTL1_AUTODET; | |
2186 | val |= MII_BNX2_SD_1000XCTL1_FIBER; | |
2187 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); | |
2188 | ||
2189 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); | |
2190 | bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val); | |
583c28e5 | 2191 | if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) |
27a005b8 MC |
2192 | val |= BCM5708S_UP1_2G5; |
2193 | else | |
2194 | val &= ~BCM5708S_UP1_2G5; | |
2195 | bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); | |
2196 | ||
2197 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG); | |
2198 | bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val); | |
2199 | val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM; | |
2200 | bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); | |
2201 | ||
2202 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0); | |
2203 | ||
2204 | val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN | | |
2205 | MII_BNX2_CL73_BAM_NP_AFT_BP_EN; | |
2206 | bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); | |
2207 | ||
2208 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
2209 | ||
2210 | return 0; | |
2211 | } | |
2212 | ||
b6016b76 | 2213 | static int |
9a120bc5 | 2214 | bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy) |
5b0c76ad MC |
2215 | { |
2216 | u32 val; | |
2217 | ||
9a120bc5 MC |
2218 | if (reset_phy) |
2219 | bnx2_reset_phy(bp); | |
27a005b8 MC |
2220 | |
2221 | bp->mii_up1 = BCM5708S_UP1; | |
2222 | ||
5b0c76ad MC |
2223 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); |
2224 | bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); | |
2225 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); | |
2226 | ||
2227 | bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val); | |
2228 | val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN; | |
2229 | bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); | |
2230 | ||
2231 | bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val); | |
2232 | val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN; | |
2233 | bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); | |
2234 | ||
583c28e5 | 2235 | if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) { |
5b0c76ad MC |
2236 | bnx2_read_phy(bp, BCM5708S_UP1, &val); |
2237 | val |= BCM5708S_UP1_2G5; | |
2238 | bnx2_write_phy(bp, BCM5708S_UP1, val); | |
2239 | } | |
2240 | ||
4ce45e02 MC |
2241 | if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) || |
2242 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) || | |
2243 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) { | |
5b0c76ad MC |
2244 | /* increase tx signal amplitude */ |
2245 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | |
2246 | BCM5708S_BLK_ADDR_TX_MISC); | |
2247 | bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val); | |
2248 | val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM; | |
2249 | bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); | |
2250 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); | |
2251 | } | |
2252 | ||
2726d6e1 | 2253 | val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) & |
5b0c76ad MC |
2254 | BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK; |
2255 | ||
2256 | if (val) { | |
2257 | u32 is_backplane; | |
2258 | ||
2726d6e1 | 2259 | is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); |
5b0c76ad MC |
2260 | if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) { |
2261 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | |
2262 | BCM5708S_BLK_ADDR_TX_MISC); | |
2263 | bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); | |
2264 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | |
2265 | BCM5708S_BLK_ADDR_DIG); | |
2266 | } | |
2267 | } | |
2268 | return 0; | |
2269 | } | |
2270 | ||
2271 | static int | |
9a120bc5 | 2272 | bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy) |
b6016b76 | 2273 | { |
9a120bc5 MC |
2274 | if (reset_phy) |
2275 | bnx2_reset_phy(bp); | |
27a005b8 | 2276 | |
583c28e5 | 2277 | bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; |
b6016b76 | 2278 | |
4ce45e02 | 2279 | if (BNX2_CHIP(bp) == BNX2_CHIP_5706) |
e503e066 | 2280 | BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); |
b6016b76 MC |
2281 | |
2282 | if (bp->dev->mtu > 1500) { | |
2283 | u32 val; | |
2284 | ||
2285 | /* Set extended packet length bit */ | |
2286 | bnx2_write_phy(bp, 0x18, 0x7); | |
2287 | bnx2_read_phy(bp, 0x18, &val); | |
2288 | bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); | |
2289 | ||
2290 | bnx2_write_phy(bp, 0x1c, 0x6c00); | |
2291 | bnx2_read_phy(bp, 0x1c, &val); | |
2292 | bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); | |
2293 | } | |
2294 | else { | |
2295 | u32 val; | |
2296 | ||
2297 | bnx2_write_phy(bp, 0x18, 0x7); | |
2298 | bnx2_read_phy(bp, 0x18, &val); | |
2299 | bnx2_write_phy(bp, 0x18, val & ~0x4007); | |
2300 | ||
2301 | bnx2_write_phy(bp, 0x1c, 0x6c00); | |
2302 | bnx2_read_phy(bp, 0x1c, &val); | |
2303 | bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); | |
2304 | } | |
2305 | ||
2306 | return 0; | |
2307 | } | |
2308 | ||
2309 | static int | |
9a120bc5 | 2310 | bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy) |
b6016b76 | 2311 | { |
5b0c76ad MC |
2312 | u32 val; |
2313 | ||
9a120bc5 MC |
2314 | if (reset_phy) |
2315 | bnx2_reset_phy(bp); | |
27a005b8 | 2316 | |
583c28e5 | 2317 | if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) { |
b6016b76 MC |
2318 | bnx2_write_phy(bp, 0x18, 0x0c00); |
2319 | bnx2_write_phy(bp, 0x17, 0x000a); | |
2320 | bnx2_write_phy(bp, 0x15, 0x310b); | |
2321 | bnx2_write_phy(bp, 0x17, 0x201f); | |
2322 | bnx2_write_phy(bp, 0x15, 0x9506); | |
2323 | bnx2_write_phy(bp, 0x17, 0x401f); | |
2324 | bnx2_write_phy(bp, 0x15, 0x14e2); | |
2325 | bnx2_write_phy(bp, 0x18, 0x0400); | |
2326 | } | |
2327 | ||
583c28e5 | 2328 | if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) { |
b659f44e MC |
2329 | bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, |
2330 | MII_BNX2_DSP_EXPAND_REG | 0x8); | |
2331 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); | |
2332 | val &= ~(1 << 8); | |
2333 | bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); | |
2334 | } | |
2335 | ||
b6016b76 | 2336 | if (bp->dev->mtu > 1500) { |
b6016b76 MC |
2337 | /* Set extended packet length bit */ |
2338 | bnx2_write_phy(bp, 0x18, 0x7); | |
2339 | bnx2_read_phy(bp, 0x18, &val); | |
2340 | bnx2_write_phy(bp, 0x18, val | 0x4000); | |
2341 | ||
2342 | bnx2_read_phy(bp, 0x10, &val); | |
2343 | bnx2_write_phy(bp, 0x10, val | 0x1); | |
2344 | } | |
2345 | else { | |
b6016b76 MC |
2346 | bnx2_write_phy(bp, 0x18, 0x7); |
2347 | bnx2_read_phy(bp, 0x18, &val); | |
2348 | bnx2_write_phy(bp, 0x18, val & ~0x4007); | |
2349 | ||
2350 | bnx2_read_phy(bp, 0x10, &val); | |
2351 | bnx2_write_phy(bp, 0x10, val & ~0x1); | |
2352 | } | |
2353 | ||
5b0c76ad | 2354 | /* ethernet@wirespeed */ |
41033b65 MC |
2355 | bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL); |
2356 | bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val); | |
2357 | val |= AUX_CTL_MISC_CTL_WR | AUX_CTL_MISC_CTL_WIRESPEED; | |
2358 | ||
2359 | /* auto-mdix */ | |
2360 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) | |
2361 | val |= AUX_CTL_MISC_CTL_AUTOMDIX; | |
2362 | ||
2363 | bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val); | |
b6016b76 MC |
2364 | return 0; |
2365 | } | |
2366 | ||
2367 | ||
2368 | static int | |
9a120bc5 | 2369 | bnx2_init_phy(struct bnx2 *bp, int reset_phy) |
52d07b1f HH |
2370 | __releases(&bp->phy_lock) |
2371 | __acquires(&bp->phy_lock) | |
b6016b76 MC |
2372 | { |
2373 | u32 val; | |
2374 | int rc = 0; | |
2375 | ||
583c28e5 MC |
2376 | bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK; |
2377 | bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY; | |
b6016b76 | 2378 | |
ca58c3af MC |
2379 | bp->mii_bmcr = MII_BMCR; |
2380 | bp->mii_bmsr = MII_BMSR; | |
27a005b8 | 2381 | bp->mii_bmsr1 = MII_BMSR; |
ca58c3af MC |
2382 | bp->mii_adv = MII_ADVERTISE; |
2383 | bp->mii_lpa = MII_LPA; | |
2384 | ||
e503e066 | 2385 | BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); |
b6016b76 | 2386 | |
583c28e5 | 2387 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
2388 | goto setup_phy; |
2389 | ||
b6016b76 MC |
2390 | bnx2_read_phy(bp, MII_PHYSID1, &val); |
2391 | bp->phy_id = val << 16; | |
2392 | bnx2_read_phy(bp, MII_PHYSID2, &val); | |
2393 | bp->phy_id |= val & 0xffff; | |
2394 | ||
583c28e5 | 2395 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
4ce45e02 | 2396 | if (BNX2_CHIP(bp) == BNX2_CHIP_5706) |
9a120bc5 | 2397 | rc = bnx2_init_5706s_phy(bp, reset_phy); |
4ce45e02 | 2398 | else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) |
9a120bc5 | 2399 | rc = bnx2_init_5708s_phy(bp, reset_phy); |
4ce45e02 | 2400 | else if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
9a120bc5 | 2401 | rc = bnx2_init_5709s_phy(bp, reset_phy); |
b6016b76 MC |
2402 | } |
2403 | else { | |
9a120bc5 | 2404 | rc = bnx2_init_copper_phy(bp, reset_phy); |
b6016b76 MC |
2405 | } |
2406 | ||
0d8a6571 MC |
2407 | setup_phy: |
2408 | if (!rc) | |
2409 | rc = bnx2_setup_phy(bp, bp->phy_port); | |
b6016b76 MC |
2410 | |
2411 | return rc; | |
2412 | } | |
2413 | ||
2414 | static int | |
2415 | bnx2_set_mac_loopback(struct bnx2 *bp) | |
2416 | { | |
2417 | u32 mac_mode; | |
2418 | ||
e503e066 | 2419 | mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE); |
b6016b76 MC |
2420 | mac_mode &= ~BNX2_EMAC_MODE_PORT; |
2421 | mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK; | |
e503e066 | 2422 | BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode); |
b6016b76 MC |
2423 | bp->link_up = 1; |
2424 | return 0; | |
2425 | } | |
2426 | ||
bc5a0690 MC |
2427 | static int bnx2_test_link(struct bnx2 *); |
2428 | ||
2429 | static int | |
2430 | bnx2_set_phy_loopback(struct bnx2 *bp) | |
2431 | { | |
2432 | u32 mac_mode; | |
2433 | int rc, i; | |
2434 | ||
2435 | spin_lock_bh(&bp->phy_lock); | |
ca58c3af | 2436 | rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | |
bc5a0690 MC |
2437 | BMCR_SPEED1000); |
2438 | spin_unlock_bh(&bp->phy_lock); | |
2439 | if (rc) | |
2440 | return rc; | |
2441 | ||
2442 | for (i = 0; i < 10; i++) { | |
2443 | if (bnx2_test_link(bp) == 0) | |
2444 | break; | |
80be4434 | 2445 | msleep(100); |
bc5a0690 MC |
2446 | } |
2447 | ||
e503e066 | 2448 | mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE); |
bc5a0690 MC |
2449 | mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | |
2450 | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | | |
59b47d8a | 2451 | BNX2_EMAC_MODE_25G_MODE); |
bc5a0690 MC |
2452 | |
2453 | mac_mode |= BNX2_EMAC_MODE_PORT_GMII; | |
e503e066 | 2454 | BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode); |
bc5a0690 MC |
2455 | bp->link_up = 1; |
2456 | return 0; | |
2457 | } | |
2458 | ||
ecdbf6e0 JH |
2459 | static void |
2460 | bnx2_dump_mcp_state(struct bnx2 *bp) | |
2461 | { | |
2462 | struct net_device *dev = bp->dev; | |
2463 | u32 mcp_p0, mcp_p1; | |
2464 | ||
2465 | netdev_err(dev, "<--- start MCP states dump --->\n"); | |
4ce45e02 | 2466 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
ecdbf6e0 JH |
2467 | mcp_p0 = BNX2_MCP_STATE_P0; |
2468 | mcp_p1 = BNX2_MCP_STATE_P1; | |
2469 | } else { | |
2470 | mcp_p0 = BNX2_MCP_STATE_P0_5708; | |
2471 | mcp_p1 = BNX2_MCP_STATE_P1_5708; | |
2472 | } | |
2473 | netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n", | |
2474 | bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1)); | |
2475 | netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n", | |
2476 | bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE), | |
2477 | bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE), | |
2478 | bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK)); | |
2479 | netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n", | |
2480 | bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER), | |
2481 | bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER), | |
2482 | bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION)); | |
2483 | netdev_err(dev, "DEBUG: shmem states:\n"); | |
2484 | netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]", | |
2485 | bnx2_shmem_rd(bp, BNX2_DRV_MB), | |
2486 | bnx2_shmem_rd(bp, BNX2_FW_MB), | |
2487 | bnx2_shmem_rd(bp, BNX2_LINK_STATUS)); | |
2488 | pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB)); | |
2489 | netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]", | |
2490 | bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE), | |
2491 | bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE)); | |
2492 | pr_cont(" condition[%08x]\n", | |
2493 | bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION)); | |
13e63517 | 2494 | DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE); |
ecdbf6e0 JH |
2495 | DP_SHMEM_LINE(bp, 0x3cc); |
2496 | DP_SHMEM_LINE(bp, 0x3dc); | |
2497 | DP_SHMEM_LINE(bp, 0x3ec); | |
2498 | netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc)); | |
2499 | netdev_err(dev, "<--- end MCP states dump --->\n"); | |
2500 | } | |
2501 | ||
b6016b76 | 2502 | static int |
a2f13890 | 2503 | bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent) |
b6016b76 MC |
2504 | { |
2505 | int i; | |
2506 | u32 val; | |
2507 | ||
b6016b76 MC |
2508 | bp->fw_wr_seq++; |
2509 | msg_data |= bp->fw_wr_seq; | |
2510 | ||
2726d6e1 | 2511 | bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); |
b6016b76 | 2512 | |
a2f13890 MC |
2513 | if (!ack) |
2514 | return 0; | |
2515 | ||
b6016b76 | 2516 | /* wait for an acknowledgement. */ |
40105c0b | 2517 | for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) { |
b090ae2b | 2518 | msleep(10); |
b6016b76 | 2519 | |
2726d6e1 | 2520 | val = bnx2_shmem_rd(bp, BNX2_FW_MB); |
b6016b76 MC |
2521 | |
2522 | if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) | |
2523 | break; | |
2524 | } | |
b090ae2b MC |
2525 | if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0) |
2526 | return 0; | |
b6016b76 MC |
2527 | |
2528 | /* If we timed out, inform the firmware that this is the case. */ | |
b090ae2b | 2529 | if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) { |
b6016b76 MC |
2530 | msg_data &= ~BNX2_DRV_MSG_CODE; |
2531 | msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; | |
2532 | ||
2726d6e1 | 2533 | bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); |
ecdbf6e0 JH |
2534 | if (!silent) { |
2535 | pr_err("fw sync timeout, reset code = %x\n", msg_data); | |
2536 | bnx2_dump_mcp_state(bp); | |
2537 | } | |
b6016b76 | 2538 | |
b6016b76 MC |
2539 | return -EBUSY; |
2540 | } | |
2541 | ||
b090ae2b MC |
2542 | if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK) |
2543 | return -EIO; | |
2544 | ||
b6016b76 MC |
2545 | return 0; |
2546 | } | |
2547 | ||
59b47d8a MC |
2548 | static int |
2549 | bnx2_init_5709_context(struct bnx2 *bp) | |
2550 | { | |
2551 | int i, ret = 0; | |
2552 | u32 val; | |
2553 | ||
2554 | val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12); | |
2bc4078e | 2555 | val |= (BNX2_PAGE_BITS - 8) << 16; |
e503e066 | 2556 | BNX2_WR(bp, BNX2_CTX_COMMAND, val); |
641bdcd5 | 2557 | for (i = 0; i < 10; i++) { |
e503e066 | 2558 | val = BNX2_RD(bp, BNX2_CTX_COMMAND); |
641bdcd5 MC |
2559 | if (!(val & BNX2_CTX_COMMAND_MEM_INIT)) |
2560 | break; | |
2561 | udelay(2); | |
2562 | } | |
2563 | if (val & BNX2_CTX_COMMAND_MEM_INIT) | |
2564 | return -EBUSY; | |
2565 | ||
59b47d8a MC |
2566 | for (i = 0; i < bp->ctx_pages; i++) { |
2567 | int j; | |
2568 | ||
352f7687 | 2569 | if (bp->ctx_blk[i]) |
2bc4078e | 2570 | memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE); |
352f7687 MC |
2571 | else |
2572 | return -ENOMEM; | |
2573 | ||
e503e066 MC |
2574 | BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0, |
2575 | (bp->ctx_blk_mapping[i] & 0xffffffff) | | |
2576 | BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID); | |
2577 | BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1, | |
2578 | (u64) bp->ctx_blk_mapping[i] >> 32); | |
2579 | BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i | | |
2580 | BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); | |
59b47d8a MC |
2581 | for (j = 0; j < 10; j++) { |
2582 | ||
e503e066 | 2583 | val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL); |
59b47d8a MC |
2584 | if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) |
2585 | break; | |
2586 | udelay(5); | |
2587 | } | |
2588 | if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) { | |
2589 | ret = -EBUSY; | |
2590 | break; | |
2591 | } | |
2592 | } | |
2593 | return ret; | |
2594 | } | |
2595 | ||
b6016b76 MC |
2596 | static void |
2597 | bnx2_init_context(struct bnx2 *bp) | |
2598 | { | |
2599 | u32 vcid; | |
2600 | ||
2601 | vcid = 96; | |
2602 | while (vcid) { | |
2603 | u32 vcid_addr, pcid_addr, offset; | |
7947b20e | 2604 | int i; |
b6016b76 MC |
2605 | |
2606 | vcid--; | |
2607 | ||
4ce45e02 | 2608 | if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { |
b6016b76 MC |
2609 | u32 new_vcid; |
2610 | ||
2611 | vcid_addr = GET_PCID_ADDR(vcid); | |
2612 | if (vcid & 0x8) { | |
2613 | new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7); | |
2614 | } | |
2615 | else { | |
2616 | new_vcid = vcid; | |
2617 | } | |
2618 | pcid_addr = GET_PCID_ADDR(new_vcid); | |
2619 | } | |
2620 | else { | |
2621 | vcid_addr = GET_CID_ADDR(vcid); | |
2622 | pcid_addr = vcid_addr; | |
2623 | } | |
2624 | ||
7947b20e MC |
2625 | for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) { |
2626 | vcid_addr += (i << PHY_CTX_SHIFT); | |
2627 | pcid_addr += (i << PHY_CTX_SHIFT); | |
b6016b76 | 2628 | |
e503e066 MC |
2629 | BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); |
2630 | BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); | |
b6016b76 | 2631 | |
7947b20e MC |
2632 | /* Zero out the context. */ |
2633 | for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) | |
62a8313c | 2634 | bnx2_ctx_wr(bp, vcid_addr, offset, 0); |
7947b20e | 2635 | } |
b6016b76 MC |
2636 | } |
2637 | } | |
2638 | ||
2639 | static int | |
2640 | bnx2_alloc_bad_rbuf(struct bnx2 *bp) | |
2641 | { | |
2642 | u16 *good_mbuf; | |
2643 | u32 good_mbuf_cnt; | |
2644 | u32 val; | |
2645 | ||
2646 | good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL); | |
e404decb | 2647 | if (good_mbuf == NULL) |
b6016b76 | 2648 | return -ENOMEM; |
b6016b76 | 2649 | |
e503e066 | 2650 | BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, |
b6016b76 MC |
2651 | BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); |
2652 | ||
2653 | good_mbuf_cnt = 0; | |
2654 | ||
2655 | /* Allocate a bunch of mbufs and save the good ones in an array. */ | |
2726d6e1 | 2656 | val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); |
b6016b76 | 2657 | while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { |
2726d6e1 MC |
2658 | bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND, |
2659 | BNX2_RBUF_COMMAND_ALLOC_REQ); | |
b6016b76 | 2660 | |
2726d6e1 | 2661 | val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC); |
b6016b76 MC |
2662 | |
2663 | val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; | |
2664 | ||
2665 | /* The addresses with Bit 9 set are bad memory blocks. */ | |
2666 | if (!(val & (1 << 9))) { | |
2667 | good_mbuf[good_mbuf_cnt] = (u16) val; | |
2668 | good_mbuf_cnt++; | |
2669 | } | |
2670 | ||
2726d6e1 | 2671 | val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); |
b6016b76 MC |
2672 | } |
2673 | ||
2674 | /* Free the good ones back to the mbuf pool thus discarding | |
2675 | * all the bad ones. */ | |
2676 | while (good_mbuf_cnt) { | |
2677 | good_mbuf_cnt--; | |
2678 | ||
2679 | val = good_mbuf[good_mbuf_cnt]; | |
2680 | val = (val << 9) | val | 1; | |
2681 | ||
2726d6e1 | 2682 | bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val); |
b6016b76 MC |
2683 | } |
2684 | kfree(good_mbuf); | |
2685 | return 0; | |
2686 | } | |
2687 | ||
2688 | static void | |
5fcaed01 | 2689 | bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos) |
b6016b76 MC |
2690 | { |
2691 | u32 val; | |
b6016b76 MC |
2692 | |
2693 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
2694 | ||
e503e066 | 2695 | BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val); |
b6016b76 | 2696 | |
6aa20a22 | 2697 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | |
b6016b76 MC |
2698 | (mac_addr[4] << 8) | mac_addr[5]; |
2699 | ||
e503e066 | 2700 | BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val); |
b6016b76 MC |
2701 | } |
2702 | ||
47bf4246 | 2703 | static inline int |
a2df00aa | 2704 | bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp) |
47bf4246 MC |
2705 | { |
2706 | dma_addr_t mapping; | |
2bc4078e MC |
2707 | struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; |
2708 | struct bnx2_rx_bd *rxbd = | |
2709 | &rxr->rx_pg_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; | |
a2df00aa | 2710 | struct page *page = alloc_page(gfp); |
47bf4246 MC |
2711 | |
2712 | if (!page) | |
2713 | return -ENOMEM; | |
36227e88 | 2714 | mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE, |
47bf4246 | 2715 | PCI_DMA_FROMDEVICE); |
36227e88 | 2716 | if (dma_mapping_error(&bp->pdev->dev, mapping)) { |
3d16af86 BL |
2717 | __free_page(page); |
2718 | return -EIO; | |
2719 | } | |
2720 | ||
47bf4246 | 2721 | rx_pg->page = page; |
1a4ccc2d | 2722 | dma_unmap_addr_set(rx_pg, mapping, mapping); |
47bf4246 MC |
2723 | rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; |
2724 | rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
2725 | return 0; | |
2726 | } | |
2727 | ||
2728 | static void | |
bb4f98ab | 2729 | bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index) |
47bf4246 | 2730 | { |
2bc4078e | 2731 | struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; |
47bf4246 MC |
2732 | struct page *page = rx_pg->page; |
2733 | ||
2734 | if (!page) | |
2735 | return; | |
2736 | ||
36227e88 SG |
2737 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping), |
2738 | PAGE_SIZE, PCI_DMA_FROMDEVICE); | |
47bf4246 MC |
2739 | |
2740 | __free_page(page); | |
2741 | rx_pg->page = NULL; | |
2742 | } | |
2743 | ||
b6016b76 | 2744 | static inline int |
dd2bc8e9 | 2745 | bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp) |
b6016b76 | 2746 | { |
dd2bc8e9 | 2747 | u8 *data; |
2bc4078e | 2748 | struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[index]; |
b6016b76 | 2749 | dma_addr_t mapping; |
2bc4078e MC |
2750 | struct bnx2_rx_bd *rxbd = |
2751 | &rxr->rx_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; | |
b6016b76 | 2752 | |
dd2bc8e9 ED |
2753 | data = kmalloc(bp->rx_buf_size, gfp); |
2754 | if (!data) | |
b6016b76 | 2755 | return -ENOMEM; |
b6016b76 | 2756 | |
dd2bc8e9 ED |
2757 | mapping = dma_map_single(&bp->pdev->dev, |
2758 | get_l2_fhdr(data), | |
2759 | bp->rx_buf_use_size, | |
36227e88 SG |
2760 | PCI_DMA_FROMDEVICE); |
2761 | if (dma_mapping_error(&bp->pdev->dev, mapping)) { | |
dd2bc8e9 | 2762 | kfree(data); |
3d16af86 BL |
2763 | return -EIO; |
2764 | } | |
b6016b76 | 2765 | |
dd2bc8e9 | 2766 | rx_buf->data = data; |
1a4ccc2d | 2767 | dma_unmap_addr_set(rx_buf, mapping, mapping); |
b6016b76 MC |
2768 | |
2769 | rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; | |
2770 | rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
2771 | ||
bb4f98ab | 2772 | rxr->rx_prod_bseq += bp->rx_buf_use_size; |
b6016b76 MC |
2773 | |
2774 | return 0; | |
2775 | } | |
2776 | ||
da3e4fbe | 2777 | static int |
35efa7c1 | 2778 | bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event) |
b6016b76 | 2779 | { |
43e80b89 | 2780 | struct status_block *sblk = bnapi->status_blk.msi; |
b6016b76 | 2781 | u32 new_link_state, old_link_state; |
da3e4fbe | 2782 | int is_set = 1; |
b6016b76 | 2783 | |
da3e4fbe MC |
2784 | new_link_state = sblk->status_attn_bits & event; |
2785 | old_link_state = sblk->status_attn_bits_ack & event; | |
b6016b76 | 2786 | if (new_link_state != old_link_state) { |
da3e4fbe | 2787 | if (new_link_state) |
e503e066 | 2788 | BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event); |
da3e4fbe | 2789 | else |
e503e066 | 2790 | BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event); |
da3e4fbe MC |
2791 | } else |
2792 | is_set = 0; | |
2793 | ||
2794 | return is_set; | |
2795 | } | |
2796 | ||
2797 | static void | |
35efa7c1 | 2798 | bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi) |
da3e4fbe | 2799 | { |
74ecc62d MC |
2800 | spin_lock(&bp->phy_lock); |
2801 | ||
2802 | if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) | |
b6016b76 | 2803 | bnx2_set_link(bp); |
35efa7c1 | 2804 | if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT)) |
0d8a6571 MC |
2805 | bnx2_set_remote_link(bp); |
2806 | ||
74ecc62d MC |
2807 | spin_unlock(&bp->phy_lock); |
2808 | ||
b6016b76 MC |
2809 | } |
2810 | ||
ead7270b | 2811 | static inline u16 |
35efa7c1 | 2812 | bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi) |
ead7270b MC |
2813 | { |
2814 | u16 cons; | |
2815 | ||
43e80b89 MC |
2816 | /* Tell compiler that status block fields can change. */ |
2817 | barrier(); | |
2818 | cons = *bnapi->hw_tx_cons_ptr; | |
581daf7e | 2819 | barrier(); |
2bc4078e | 2820 | if (unlikely((cons & BNX2_MAX_TX_DESC_CNT) == BNX2_MAX_TX_DESC_CNT)) |
ead7270b MC |
2821 | cons++; |
2822 | return cons; | |
2823 | } | |
2824 | ||
57851d84 MC |
2825 | static int |
2826 | bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) | |
b6016b76 | 2827 | { |
35e9010b | 2828 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; |
b6016b76 | 2829 | u16 hw_cons, sw_cons, sw_ring_cons; |
706bf240 | 2830 | int tx_pkt = 0, index; |
e9831909 | 2831 | unsigned int tx_bytes = 0; |
706bf240 BL |
2832 | struct netdev_queue *txq; |
2833 | ||
2834 | index = (bnapi - bp->bnx2_napi); | |
2835 | txq = netdev_get_tx_queue(bp->dev, index); | |
b6016b76 | 2836 | |
35efa7c1 | 2837 | hw_cons = bnx2_get_hw_tx_cons(bnapi); |
35e9010b | 2838 | sw_cons = txr->tx_cons; |
b6016b76 MC |
2839 | |
2840 | while (sw_cons != hw_cons) { | |
2bc4078e | 2841 | struct bnx2_sw_tx_bd *tx_buf; |
b6016b76 MC |
2842 | struct sk_buff *skb; |
2843 | int i, last; | |
2844 | ||
2bc4078e | 2845 | sw_ring_cons = BNX2_TX_RING_IDX(sw_cons); |
b6016b76 | 2846 | |
35e9010b | 2847 | tx_buf = &txr->tx_buf_ring[sw_ring_cons]; |
b6016b76 | 2848 | skb = tx_buf->skb; |
1d39ed56 | 2849 | |
d62fda08 ED |
2850 | /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */ |
2851 | prefetch(&skb->end); | |
2852 | ||
b6016b76 | 2853 | /* partial BD completions possible with TSO packets */ |
d62fda08 | 2854 | if (tx_buf->is_gso) { |
b6016b76 MC |
2855 | u16 last_idx, last_ring_idx; |
2856 | ||
d62fda08 ED |
2857 | last_idx = sw_cons + tx_buf->nr_frags + 1; |
2858 | last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1; | |
2bc4078e | 2859 | if (unlikely(last_ring_idx >= BNX2_MAX_TX_DESC_CNT)) { |
b6016b76 MC |
2860 | last_idx++; |
2861 | } | |
2862 | if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { | |
2863 | break; | |
2864 | } | |
2865 | } | |
1d39ed56 | 2866 | |
36227e88 | 2867 | dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), |
e95524a7 | 2868 | skb_headlen(skb), PCI_DMA_TODEVICE); |
b6016b76 MC |
2869 | |
2870 | tx_buf->skb = NULL; | |
d62fda08 | 2871 | last = tx_buf->nr_frags; |
b6016b76 MC |
2872 | |
2873 | for (i = 0; i < last; i++) { | |
2bc4078e | 2874 | struct bnx2_sw_tx_bd *tx_buf; |
e95524a7 | 2875 | |
2bc4078e MC |
2876 | sw_cons = BNX2_NEXT_TX_BD(sw_cons); |
2877 | ||
2878 | tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(sw_cons)]; | |
36227e88 | 2879 | dma_unmap_page(&bp->pdev->dev, |
2bc4078e | 2880 | dma_unmap_addr(tx_buf, mapping), |
9e903e08 | 2881 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
e95524a7 | 2882 | PCI_DMA_TODEVICE); |
b6016b76 MC |
2883 | } |
2884 | ||
2bc4078e | 2885 | sw_cons = BNX2_NEXT_TX_BD(sw_cons); |
b6016b76 | 2886 | |
e9831909 | 2887 | tx_bytes += skb->len; |
745720e5 | 2888 | dev_kfree_skb(skb); |
57851d84 MC |
2889 | tx_pkt++; |
2890 | if (tx_pkt == budget) | |
2891 | break; | |
b6016b76 | 2892 | |
d62fda08 ED |
2893 | if (hw_cons == sw_cons) |
2894 | hw_cons = bnx2_get_hw_tx_cons(bnapi); | |
b6016b76 MC |
2895 | } |
2896 | ||
e9831909 | 2897 | netdev_tx_completed_queue(txq, tx_pkt, tx_bytes); |
35e9010b MC |
2898 | txr->hw_tx_cons = hw_cons; |
2899 | txr->tx_cons = sw_cons; | |
706bf240 | 2900 | |
2f8af120 | 2901 | /* Need to make the tx_cons update visible to bnx2_start_xmit() |
706bf240 | 2902 | * before checking for netif_tx_queue_stopped(). Without the |
2f8af120 MC |
2903 | * memory barrier, there is a small possibility that bnx2_start_xmit() |
2904 | * will miss it and cause the queue to be stopped forever. | |
2905 | */ | |
2906 | smp_mb(); | |
b6016b76 | 2907 | |
706bf240 | 2908 | if (unlikely(netif_tx_queue_stopped(txq)) && |
35e9010b | 2909 | (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) { |
706bf240 BL |
2910 | __netif_tx_lock(txq, smp_processor_id()); |
2911 | if ((netif_tx_queue_stopped(txq)) && | |
35e9010b | 2912 | (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) |
706bf240 BL |
2913 | netif_tx_wake_queue(txq); |
2914 | __netif_tx_unlock(txq); | |
b6016b76 | 2915 | } |
706bf240 | 2916 | |
57851d84 | 2917 | return tx_pkt; |
b6016b76 MC |
2918 | } |
2919 | ||
1db82f2a | 2920 | static void |
bb4f98ab | 2921 | bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, |
a1f60190 | 2922 | struct sk_buff *skb, int count) |
1db82f2a | 2923 | { |
2bc4078e MC |
2924 | struct bnx2_sw_pg *cons_rx_pg, *prod_rx_pg; |
2925 | struct bnx2_rx_bd *cons_bd, *prod_bd; | |
1db82f2a | 2926 | int i; |
3d16af86 | 2927 | u16 hw_prod, prod; |
bb4f98ab | 2928 | u16 cons = rxr->rx_pg_cons; |
1db82f2a | 2929 | |
3d16af86 BL |
2930 | cons_rx_pg = &rxr->rx_pg_ring[cons]; |
2931 | ||
2932 | /* The caller was unable to allocate a new page to replace the | |
2933 | * last one in the frags array, so we need to recycle that page | |
2934 | * and then free the skb. | |
2935 | */ | |
2936 | if (skb) { | |
2937 | struct page *page; | |
2938 | struct skb_shared_info *shinfo; | |
2939 | ||
2940 | shinfo = skb_shinfo(skb); | |
2941 | shinfo->nr_frags--; | |
b7b6a688 IC |
2942 | page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]); |
2943 | __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL); | |
3d16af86 BL |
2944 | |
2945 | cons_rx_pg->page = page; | |
2946 | dev_kfree_skb(skb); | |
2947 | } | |
2948 | ||
2949 | hw_prod = rxr->rx_pg_prod; | |
2950 | ||
1db82f2a | 2951 | for (i = 0; i < count; i++) { |
2bc4078e | 2952 | prod = BNX2_RX_PG_RING_IDX(hw_prod); |
1db82f2a | 2953 | |
bb4f98ab MC |
2954 | prod_rx_pg = &rxr->rx_pg_ring[prod]; |
2955 | cons_rx_pg = &rxr->rx_pg_ring[cons]; | |
2bc4078e MC |
2956 | cons_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(cons)] |
2957 | [BNX2_RX_IDX(cons)]; | |
2958 | prod_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(prod)] | |
2959 | [BNX2_RX_IDX(prod)]; | |
1db82f2a | 2960 | |
1db82f2a MC |
2961 | if (prod != cons) { |
2962 | prod_rx_pg->page = cons_rx_pg->page; | |
2963 | cons_rx_pg->page = NULL; | |
1a4ccc2d FT |
2964 | dma_unmap_addr_set(prod_rx_pg, mapping, |
2965 | dma_unmap_addr(cons_rx_pg, mapping)); | |
1db82f2a MC |
2966 | |
2967 | prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; | |
2968 | prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; | |
2969 | ||
2970 | } | |
2bc4078e MC |
2971 | cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(cons)); |
2972 | hw_prod = BNX2_NEXT_RX_BD(hw_prod); | |
1db82f2a | 2973 | } |
bb4f98ab MC |
2974 | rxr->rx_pg_prod = hw_prod; |
2975 | rxr->rx_pg_cons = cons; | |
1db82f2a MC |
2976 | } |
2977 | ||
b6016b76 | 2978 | static inline void |
dd2bc8e9 ED |
2979 | bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, |
2980 | u8 *data, u16 cons, u16 prod) | |
b6016b76 | 2981 | { |
2bc4078e MC |
2982 | struct bnx2_sw_bd *cons_rx_buf, *prod_rx_buf; |
2983 | struct bnx2_rx_bd *cons_bd, *prod_bd; | |
236b6394 | 2984 | |
bb4f98ab MC |
2985 | cons_rx_buf = &rxr->rx_buf_ring[cons]; |
2986 | prod_rx_buf = &rxr->rx_buf_ring[prod]; | |
b6016b76 | 2987 | |
36227e88 | 2988 | dma_sync_single_for_device(&bp->pdev->dev, |
1a4ccc2d | 2989 | dma_unmap_addr(cons_rx_buf, mapping), |
601d3d18 | 2990 | BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE); |
b6016b76 | 2991 | |
bb4f98ab | 2992 | rxr->rx_prod_bseq += bp->rx_buf_use_size; |
b6016b76 | 2993 | |
dd2bc8e9 | 2994 | prod_rx_buf->data = data; |
b6016b76 | 2995 | |
236b6394 MC |
2996 | if (cons == prod) |
2997 | return; | |
b6016b76 | 2998 | |
1a4ccc2d FT |
2999 | dma_unmap_addr_set(prod_rx_buf, mapping, |
3000 | dma_unmap_addr(cons_rx_buf, mapping)); | |
236b6394 | 3001 | |
2bc4078e MC |
3002 | cons_bd = &rxr->rx_desc_ring[BNX2_RX_RING(cons)][BNX2_RX_IDX(cons)]; |
3003 | prod_bd = &rxr->rx_desc_ring[BNX2_RX_RING(prod)][BNX2_RX_IDX(prod)]; | |
236b6394 MC |
3004 | prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; |
3005 | prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; | |
b6016b76 MC |
3006 | } |
3007 | ||
dd2bc8e9 ED |
3008 | static struct sk_buff * |
3009 | bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data, | |
a1f60190 MC |
3010 | unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr, |
3011 | u32 ring_idx) | |
85833c62 MC |
3012 | { |
3013 | int err; | |
3014 | u16 prod = ring_idx & 0xffff; | |
dd2bc8e9 | 3015 | struct sk_buff *skb; |
85833c62 | 3016 | |
dd2bc8e9 | 3017 | err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); |
85833c62 | 3018 | if (unlikely(err)) { |
dd2bc8e9 ED |
3019 | bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod); |
3020 | error: | |
1db82f2a MC |
3021 | if (hdr_len) { |
3022 | unsigned int raw_len = len + 4; | |
3023 | int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT; | |
3024 | ||
bb4f98ab | 3025 | bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); |
1db82f2a | 3026 | } |
dd2bc8e9 | 3027 | return NULL; |
85833c62 MC |
3028 | } |
3029 | ||
36227e88 | 3030 | dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, |
85833c62 | 3031 | PCI_DMA_FROMDEVICE); |
d3836f21 | 3032 | skb = build_skb(data, 0); |
dd2bc8e9 ED |
3033 | if (!skb) { |
3034 | kfree(data); | |
3035 | goto error; | |
3036 | } | |
3037 | skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET); | |
1db82f2a MC |
3038 | if (hdr_len == 0) { |
3039 | skb_put(skb, len); | |
dd2bc8e9 | 3040 | return skb; |
1db82f2a MC |
3041 | } else { |
3042 | unsigned int i, frag_len, frag_size, pages; | |
2bc4078e | 3043 | struct bnx2_sw_pg *rx_pg; |
bb4f98ab MC |
3044 | u16 pg_cons = rxr->rx_pg_cons; |
3045 | u16 pg_prod = rxr->rx_pg_prod; | |
1db82f2a MC |
3046 | |
3047 | frag_size = len + 4 - hdr_len; | |
3048 | pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT; | |
3049 | skb_put(skb, hdr_len); | |
3050 | ||
3051 | for (i = 0; i < pages; i++) { | |
3d16af86 BL |
3052 | dma_addr_t mapping_old; |
3053 | ||
1db82f2a MC |
3054 | frag_len = min(frag_size, (unsigned int) PAGE_SIZE); |
3055 | if (unlikely(frag_len <= 4)) { | |
3056 | unsigned int tail = 4 - frag_len; | |
3057 | ||
bb4f98ab MC |
3058 | rxr->rx_pg_cons = pg_cons; |
3059 | rxr->rx_pg_prod = pg_prod; | |
3060 | bnx2_reuse_rx_skb_pages(bp, rxr, NULL, | |
a1f60190 | 3061 | pages - i); |
1db82f2a MC |
3062 | skb->len -= tail; |
3063 | if (i == 0) { | |
3064 | skb->tail -= tail; | |
3065 | } else { | |
3066 | skb_frag_t *frag = | |
3067 | &skb_shinfo(skb)->frags[i - 1]; | |
9e903e08 | 3068 | skb_frag_size_sub(frag, tail); |
1db82f2a | 3069 | skb->data_len -= tail; |
1db82f2a | 3070 | } |
dd2bc8e9 | 3071 | return skb; |
1db82f2a | 3072 | } |
bb4f98ab | 3073 | rx_pg = &rxr->rx_pg_ring[pg_cons]; |
1db82f2a | 3074 | |
3d16af86 BL |
3075 | /* Don't unmap yet. If we're unable to allocate a new |
3076 | * page, we need to recycle the page and the DMA addr. | |
3077 | */ | |
1a4ccc2d | 3078 | mapping_old = dma_unmap_addr(rx_pg, mapping); |
1db82f2a MC |
3079 | if (i == pages - 1) |
3080 | frag_len -= 4; | |
3081 | ||
3082 | skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); | |
3083 | rx_pg->page = NULL; | |
3084 | ||
bb4f98ab | 3085 | err = bnx2_alloc_rx_page(bp, rxr, |
2bc4078e | 3086 | BNX2_RX_PG_RING_IDX(pg_prod), |
a2df00aa | 3087 | GFP_ATOMIC); |
1db82f2a | 3088 | if (unlikely(err)) { |
bb4f98ab MC |
3089 | rxr->rx_pg_cons = pg_cons; |
3090 | rxr->rx_pg_prod = pg_prod; | |
3091 | bnx2_reuse_rx_skb_pages(bp, rxr, skb, | |
a1f60190 | 3092 | pages - i); |
dd2bc8e9 | 3093 | return NULL; |
1db82f2a MC |
3094 | } |
3095 | ||
36227e88 | 3096 | dma_unmap_page(&bp->pdev->dev, mapping_old, |
3d16af86 BL |
3097 | PAGE_SIZE, PCI_DMA_FROMDEVICE); |
3098 | ||
1db82f2a MC |
3099 | frag_size -= frag_len; |
3100 | skb->data_len += frag_len; | |
a1f4e8bc | 3101 | skb->truesize += PAGE_SIZE; |
1db82f2a MC |
3102 | skb->len += frag_len; |
3103 | ||
2bc4078e MC |
3104 | pg_prod = BNX2_NEXT_RX_BD(pg_prod); |
3105 | pg_cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(pg_cons)); | |
1db82f2a | 3106 | } |
bb4f98ab MC |
3107 | rxr->rx_pg_prod = pg_prod; |
3108 | rxr->rx_pg_cons = pg_cons; | |
1db82f2a | 3109 | } |
dd2bc8e9 | 3110 | return skb; |
85833c62 MC |
3111 | } |
3112 | ||
c09c2627 | 3113 | static inline u16 |
35efa7c1 | 3114 | bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi) |
c09c2627 | 3115 | { |
bb4f98ab MC |
3116 | u16 cons; |
3117 | ||
43e80b89 MC |
3118 | /* Tell compiler that status block fields can change. */ |
3119 | barrier(); | |
3120 | cons = *bnapi->hw_rx_cons_ptr; | |
581daf7e | 3121 | barrier(); |
2bc4078e | 3122 | if (unlikely((cons & BNX2_MAX_RX_DESC_CNT) == BNX2_MAX_RX_DESC_CNT)) |
c09c2627 MC |
3123 | cons++; |
3124 | return cons; | |
3125 | } | |
3126 | ||
b6016b76 | 3127 | static int |
35efa7c1 | 3128 | bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) |
b6016b76 | 3129 | { |
bb4f98ab | 3130 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; |
b6016b76 MC |
3131 | u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; |
3132 | struct l2_fhdr *rx_hdr; | |
1db82f2a | 3133 | int rx_pkt = 0, pg_ring_used = 0; |
b6016b76 | 3134 | |
35efa7c1 | 3135 | hw_cons = bnx2_get_hw_rx_cons(bnapi); |
bb4f98ab MC |
3136 | sw_cons = rxr->rx_cons; |
3137 | sw_prod = rxr->rx_prod; | |
b6016b76 MC |
3138 | |
3139 | /* Memory barrier necessary as speculative reads of the rx | |
3140 | * buffer can be ahead of the index in the status block | |
3141 | */ | |
3142 | rmb(); | |
3143 | while (sw_cons != hw_cons) { | |
1db82f2a | 3144 | unsigned int len, hdr_len; |
ade2bfe7 | 3145 | u32 status; |
2bc4078e | 3146 | struct bnx2_sw_bd *rx_buf, *next_rx_buf; |
b6016b76 | 3147 | struct sk_buff *skb; |
236b6394 | 3148 | dma_addr_t dma_addr; |
dd2bc8e9 | 3149 | u8 *data; |
2bc4078e | 3150 | u16 next_ring_idx; |
b6016b76 | 3151 | |
2bc4078e MC |
3152 | sw_ring_cons = BNX2_RX_RING_IDX(sw_cons); |
3153 | sw_ring_prod = BNX2_RX_RING_IDX(sw_prod); | |
b6016b76 | 3154 | |
bb4f98ab | 3155 | rx_buf = &rxr->rx_buf_ring[sw_ring_cons]; |
dd2bc8e9 ED |
3156 | data = rx_buf->data; |
3157 | rx_buf->data = NULL; | |
aabef8b2 | 3158 | |
dd2bc8e9 ED |
3159 | rx_hdr = get_l2_fhdr(data); |
3160 | prefetch(rx_hdr); | |
236b6394 | 3161 | |
1a4ccc2d | 3162 | dma_addr = dma_unmap_addr(rx_buf, mapping); |
236b6394 | 3163 | |
36227e88 | 3164 | dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr, |
601d3d18 BL |
3165 | BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, |
3166 | PCI_DMA_FROMDEVICE); | |
b6016b76 | 3167 | |
2bc4078e MC |
3168 | next_ring_idx = BNX2_RX_RING_IDX(BNX2_NEXT_RX_BD(sw_cons)); |
3169 | next_rx_buf = &rxr->rx_buf_ring[next_ring_idx]; | |
dd2bc8e9 ED |
3170 | prefetch(get_l2_fhdr(next_rx_buf->data)); |
3171 | ||
1db82f2a | 3172 | len = rx_hdr->l2_fhdr_pkt_len; |
990ec380 | 3173 | status = rx_hdr->l2_fhdr_status; |
b6016b76 | 3174 | |
1db82f2a MC |
3175 | hdr_len = 0; |
3176 | if (status & L2_FHDR_STATUS_SPLIT) { | |
3177 | hdr_len = rx_hdr->l2_fhdr_ip_xsum; | |
3178 | pg_ring_used = 1; | |
3179 | } else if (len > bp->rx_jumbo_thresh) { | |
3180 | hdr_len = bp->rx_jumbo_thresh; | |
3181 | pg_ring_used = 1; | |
3182 | } | |
3183 | ||
990ec380 MC |
3184 | if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC | |
3185 | L2_FHDR_ERRORS_PHY_DECODE | | |
3186 | L2_FHDR_ERRORS_ALIGNMENT | | |
3187 | L2_FHDR_ERRORS_TOO_SHORT | | |
3188 | L2_FHDR_ERRORS_GIANT_FRAME))) { | |
3189 | ||
dd2bc8e9 | 3190 | bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons, |
990ec380 MC |
3191 | sw_ring_prod); |
3192 | if (pg_ring_used) { | |
3193 | int pages; | |
3194 | ||
3195 | pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT; | |
3196 | ||
3197 | bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); | |
3198 | } | |
3199 | goto next_rx; | |
3200 | } | |
3201 | ||
1db82f2a | 3202 | len -= 4; |
b6016b76 | 3203 | |
5d5d0015 | 3204 | if (len <= bp->rx_copy_thresh) { |
dd2bc8e9 ED |
3205 | skb = netdev_alloc_skb(bp->dev, len + 6); |
3206 | if (skb == NULL) { | |
3207 | bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons, | |
85833c62 MC |
3208 | sw_ring_prod); |
3209 | goto next_rx; | |
3210 | } | |
b6016b76 MC |
3211 | |
3212 | /* aligned copy */ | |
dd2bc8e9 ED |
3213 | memcpy(skb->data, |
3214 | (u8 *)rx_hdr + BNX2_RX_OFFSET - 6, | |
3215 | len + 6); | |
3216 | skb_reserve(skb, 6); | |
3217 | skb_put(skb, len); | |
b6016b76 | 3218 | |
dd2bc8e9 | 3219 | bnx2_reuse_rx_data(bp, rxr, data, |
b6016b76 MC |
3220 | sw_ring_cons, sw_ring_prod); |
3221 | ||
dd2bc8e9 ED |
3222 | } else { |
3223 | skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr, | |
3224 | (sw_ring_cons << 16) | sw_ring_prod); | |
3225 | if (!skb) | |
3226 | goto next_rx; | |
3227 | } | |
f22828e8 | 3228 | if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && |
7d0fd211 | 3229 | !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) |
86a9bad3 | 3230 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rx_hdr->l2_fhdr_vlan_tag); |
f22828e8 | 3231 | |
b6016b76 MC |
3232 | skb->protocol = eth_type_trans(skb, bp->dev); |
3233 | ||
3234 | if ((len > (bp->dev->mtu + ETH_HLEN)) && | |
d1e100ba | 3235 | (ntohs(skb->protocol) != 0x8100)) { |
b6016b76 | 3236 | |
745720e5 | 3237 | dev_kfree_skb(skb); |
b6016b76 MC |
3238 | goto next_rx; |
3239 | ||
3240 | } | |
3241 | ||
bc8acf2c | 3242 | skb_checksum_none_assert(skb); |
8d7dfc2b | 3243 | if ((bp->dev->features & NETIF_F_RXCSUM) && |
b6016b76 MC |
3244 | (status & (L2_FHDR_STATUS_TCP_SEGMENT | |
3245 | L2_FHDR_STATUS_UDP_DATAGRAM))) { | |
3246 | ||
ade2bfe7 MC |
3247 | if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM | |
3248 | L2_FHDR_ERRORS_UDP_XSUM)) == 0)) | |
b6016b76 MC |
3249 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
3250 | } | |
fdc8541d MC |
3251 | if ((bp->dev->features & NETIF_F_RXHASH) && |
3252 | ((status & L2_FHDR_STATUS_USE_RXHASH) == | |
3253 | L2_FHDR_STATUS_USE_RXHASH)) | |
cf1bfd6a TH |
3254 | skb_set_hash(skb, rx_hdr->l2_fhdr_hash, |
3255 | PKT_HASH_TYPE_L3); | |
b6016b76 | 3256 | |
0c8dfc83 | 3257 | skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]); |
7d0fd211 | 3258 | napi_gro_receive(&bnapi->napi, skb); |
b6016b76 MC |
3259 | rx_pkt++; |
3260 | ||
3261 | next_rx: | |
2bc4078e MC |
3262 | sw_cons = BNX2_NEXT_RX_BD(sw_cons); |
3263 | sw_prod = BNX2_NEXT_RX_BD(sw_prod); | |
b6016b76 MC |
3264 | |
3265 | if ((rx_pkt == budget)) | |
3266 | break; | |
f4e418f7 MC |
3267 | |
3268 | /* Refresh hw_cons to see if there is new work */ | |
3269 | if (sw_cons == hw_cons) { | |
35efa7c1 | 3270 | hw_cons = bnx2_get_hw_rx_cons(bnapi); |
f4e418f7 MC |
3271 | rmb(); |
3272 | } | |
b6016b76 | 3273 | } |
bb4f98ab MC |
3274 | rxr->rx_cons = sw_cons; |
3275 | rxr->rx_prod = sw_prod; | |
b6016b76 | 3276 | |
1db82f2a | 3277 | if (pg_ring_used) |
e503e066 | 3278 | BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); |
1db82f2a | 3279 | |
e503e066 | 3280 | BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod); |
b6016b76 | 3281 | |
e503e066 | 3282 | BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); |
b6016b76 MC |
3283 | |
3284 | mmiowb(); | |
3285 | ||
3286 | return rx_pkt; | |
3287 | ||
3288 | } | |
3289 | ||
3290 | /* MSI ISR - The only difference between this and the INTx ISR | |
3291 | * is that the MSI interrupt is always serviced. | |
3292 | */ | |
3293 | static irqreturn_t | |
7d12e780 | 3294 | bnx2_msi(int irq, void *dev_instance) |
b6016b76 | 3295 | { |
f0ea2e63 MC |
3296 | struct bnx2_napi *bnapi = dev_instance; |
3297 | struct bnx2 *bp = bnapi->bp; | |
b6016b76 | 3298 | |
43e80b89 | 3299 | prefetch(bnapi->status_blk.msi); |
e503e066 | 3300 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
b6016b76 MC |
3301 | BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | |
3302 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
3303 | ||
3304 | /* Return here if interrupt is disabled. */ | |
73eef4cd MC |
3305 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) |
3306 | return IRQ_HANDLED; | |
b6016b76 | 3307 | |
288379f0 | 3308 | napi_schedule(&bnapi->napi); |
b6016b76 | 3309 | |
73eef4cd | 3310 | return IRQ_HANDLED; |
b6016b76 MC |
3311 | } |
3312 | ||
8e6a72c4 MC |
3313 | static irqreturn_t |
3314 | bnx2_msi_1shot(int irq, void *dev_instance) | |
3315 | { | |
f0ea2e63 MC |
3316 | struct bnx2_napi *bnapi = dev_instance; |
3317 | struct bnx2 *bp = bnapi->bp; | |
8e6a72c4 | 3318 | |
43e80b89 | 3319 | prefetch(bnapi->status_blk.msi); |
8e6a72c4 MC |
3320 | |
3321 | /* Return here if interrupt is disabled. */ | |
3322 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) | |
3323 | return IRQ_HANDLED; | |
3324 | ||
288379f0 | 3325 | napi_schedule(&bnapi->napi); |
8e6a72c4 MC |
3326 | |
3327 | return IRQ_HANDLED; | |
3328 | } | |
3329 | ||
b6016b76 | 3330 | static irqreturn_t |
7d12e780 | 3331 | bnx2_interrupt(int irq, void *dev_instance) |
b6016b76 | 3332 | { |
f0ea2e63 MC |
3333 | struct bnx2_napi *bnapi = dev_instance; |
3334 | struct bnx2 *bp = bnapi->bp; | |
43e80b89 | 3335 | struct status_block *sblk = bnapi->status_blk.msi; |
b6016b76 MC |
3336 | |
3337 | /* When using INTx, it is possible for the interrupt to arrive | |
3338 | * at the CPU before the status block posted prior to the | |
3339 | * interrupt. Reading a register will flush the status block. | |
3340 | * When using MSI, the MSI message will always complete after | |
3341 | * the status block write. | |
3342 | */ | |
35efa7c1 | 3343 | if ((sblk->status_idx == bnapi->last_status_idx) && |
e503e066 | 3344 | (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) & |
b6016b76 | 3345 | BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) |
73eef4cd | 3346 | return IRQ_NONE; |
b6016b76 | 3347 | |
e503e066 | 3348 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
b6016b76 MC |
3349 | BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | |
3350 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
3351 | ||
b8a7ce7b MC |
3352 | /* Read back to deassert IRQ immediately to avoid too many |
3353 | * spurious interrupts. | |
3354 | */ | |
e503e066 | 3355 | BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); |
b8a7ce7b | 3356 | |
b6016b76 | 3357 | /* Return here if interrupt is shared and is disabled. */ |
73eef4cd MC |
3358 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) |
3359 | return IRQ_HANDLED; | |
b6016b76 | 3360 | |
288379f0 | 3361 | if (napi_schedule_prep(&bnapi->napi)) { |
35efa7c1 | 3362 | bnapi->last_status_idx = sblk->status_idx; |
288379f0 | 3363 | __napi_schedule(&bnapi->napi); |
b8a7ce7b | 3364 | } |
b6016b76 | 3365 | |
73eef4cd | 3366 | return IRQ_HANDLED; |
b6016b76 MC |
3367 | } |
3368 | ||
f4e418f7 | 3369 | static inline int |
43e80b89 | 3370 | bnx2_has_fast_work(struct bnx2_napi *bnapi) |
f4e418f7 | 3371 | { |
35e9010b | 3372 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; |
bb4f98ab | 3373 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; |
f4e418f7 | 3374 | |
bb4f98ab | 3375 | if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) || |
35e9010b | 3376 | (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)) |
f4e418f7 | 3377 | return 1; |
43e80b89 MC |
3378 | return 0; |
3379 | } | |
3380 | ||
3381 | #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \ | |
3382 | STATUS_ATTN_BITS_TIMER_ABORT) | |
3383 | ||
3384 | static inline int | |
3385 | bnx2_has_work(struct bnx2_napi *bnapi) | |
3386 | { | |
3387 | struct status_block *sblk = bnapi->status_blk.msi; | |
3388 | ||
3389 | if (bnx2_has_fast_work(bnapi)) | |
3390 | return 1; | |
f4e418f7 | 3391 | |
4edd473f MC |
3392 | #ifdef BCM_CNIC |
3393 | if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx)) | |
3394 | return 1; | |
3395 | #endif | |
3396 | ||
da3e4fbe MC |
3397 | if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != |
3398 | (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS)) | |
f4e418f7 MC |
3399 | return 1; |
3400 | ||
3401 | return 0; | |
3402 | } | |
3403 | ||
efba0180 MC |
3404 | static void |
3405 | bnx2_chk_missed_msi(struct bnx2 *bp) | |
3406 | { | |
3407 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; | |
3408 | u32 msi_ctrl; | |
3409 | ||
3410 | if (bnx2_has_work(bnapi)) { | |
e503e066 | 3411 | msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL); |
efba0180 MC |
3412 | if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE)) |
3413 | return; | |
3414 | ||
3415 | if (bnapi->last_status_idx == bp->idle_chk_status_idx) { | |
e503e066 MC |
3416 | BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl & |
3417 | ~BNX2_PCICFG_MSI_CONTROL_ENABLE); | |
3418 | BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl); | |
efba0180 MC |
3419 | bnx2_msi(bp->irq_tbl[0].vector, bnapi); |
3420 | } | |
3421 | } | |
3422 | ||
3423 | bp->idle_chk_status_idx = bnapi->last_status_idx; | |
3424 | } | |
3425 | ||
4edd473f MC |
3426 | #ifdef BCM_CNIC |
3427 | static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi) | |
3428 | { | |
3429 | struct cnic_ops *c_ops; | |
3430 | ||
3431 | if (!bnapi->cnic_present) | |
3432 | return; | |
3433 | ||
3434 | rcu_read_lock(); | |
3435 | c_ops = rcu_dereference(bp->cnic_ops); | |
3436 | if (c_ops) | |
3437 | bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data, | |
3438 | bnapi->status_blk.msi); | |
3439 | rcu_read_unlock(); | |
3440 | } | |
3441 | #endif | |
3442 | ||
43e80b89 | 3443 | static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi) |
b6016b76 | 3444 | { |
43e80b89 | 3445 | struct status_block *sblk = bnapi->status_blk.msi; |
da3e4fbe MC |
3446 | u32 status_attn_bits = sblk->status_attn_bits; |
3447 | u32 status_attn_bits_ack = sblk->status_attn_bits_ack; | |
b6016b76 | 3448 | |
da3e4fbe MC |
3449 | if ((status_attn_bits & STATUS_ATTN_EVENTS) != |
3450 | (status_attn_bits_ack & STATUS_ATTN_EVENTS)) { | |
b6016b76 | 3451 | |
35efa7c1 | 3452 | bnx2_phy_int(bp, bnapi); |
bf5295bb MC |
3453 | |
3454 | /* This is needed to take care of transient status | |
3455 | * during link changes. | |
3456 | */ | |
e503e066 MC |
3457 | BNX2_WR(bp, BNX2_HC_COMMAND, |
3458 | bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
3459 | BNX2_RD(bp, BNX2_HC_COMMAND); | |
b6016b76 | 3460 | } |
43e80b89 MC |
3461 | } |
3462 | ||
3463 | static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi, | |
3464 | int work_done, int budget) | |
3465 | { | |
3466 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; | |
3467 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
b6016b76 | 3468 | |
35e9010b | 3469 | if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons) |
57851d84 | 3470 | bnx2_tx_int(bp, bnapi, 0); |
b6016b76 | 3471 | |
bb4f98ab | 3472 | if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) |
35efa7c1 | 3473 | work_done += bnx2_rx_int(bp, bnapi, budget - work_done); |
6aa20a22 | 3474 | |
6f535763 DM |
3475 | return work_done; |
3476 | } | |
3477 | ||
f0ea2e63 MC |
3478 | static int bnx2_poll_msix(struct napi_struct *napi, int budget) |
3479 | { | |
3480 | struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); | |
3481 | struct bnx2 *bp = bnapi->bp; | |
3482 | int work_done = 0; | |
3483 | struct status_block_msix *sblk = bnapi->status_blk.msix; | |
3484 | ||
3485 | while (1) { | |
3486 | work_done = bnx2_poll_work(bp, bnapi, work_done, budget); | |
3487 | if (unlikely(work_done >= budget)) | |
3488 | break; | |
3489 | ||
3490 | bnapi->last_status_idx = sblk->status_idx; | |
3491 | /* status idx must be read before checking for more work. */ | |
3492 | rmb(); | |
3493 | if (likely(!bnx2_has_fast_work(bnapi))) { | |
3494 | ||
288379f0 | 3495 | napi_complete(napi); |
e503e066 MC |
3496 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
3497 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
3498 | bnapi->last_status_idx); | |
f0ea2e63 MC |
3499 | break; |
3500 | } | |
3501 | } | |
3502 | return work_done; | |
3503 | } | |
3504 | ||
6f535763 DM |
3505 | static int bnx2_poll(struct napi_struct *napi, int budget) |
3506 | { | |
35efa7c1 MC |
3507 | struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); |
3508 | struct bnx2 *bp = bnapi->bp; | |
6f535763 | 3509 | int work_done = 0; |
43e80b89 | 3510 | struct status_block *sblk = bnapi->status_blk.msi; |
6f535763 DM |
3511 | |
3512 | while (1) { | |
43e80b89 MC |
3513 | bnx2_poll_link(bp, bnapi); |
3514 | ||
35efa7c1 | 3515 | work_done = bnx2_poll_work(bp, bnapi, work_done, budget); |
f4e418f7 | 3516 | |
4edd473f MC |
3517 | #ifdef BCM_CNIC |
3518 | bnx2_poll_cnic(bp, bnapi); | |
3519 | #endif | |
3520 | ||
35efa7c1 | 3521 | /* bnapi->last_status_idx is used below to tell the hw how |
6dee6421 MC |
3522 | * much work has been processed, so we must read it before |
3523 | * checking for more work. | |
3524 | */ | |
35efa7c1 | 3525 | bnapi->last_status_idx = sblk->status_idx; |
efba0180 MC |
3526 | |
3527 | if (unlikely(work_done >= budget)) | |
3528 | break; | |
3529 | ||
6dee6421 | 3530 | rmb(); |
35efa7c1 | 3531 | if (likely(!bnx2_has_work(bnapi))) { |
288379f0 | 3532 | napi_complete(napi); |
f86e82fb | 3533 | if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { |
e503e066 MC |
3534 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
3535 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
3536 | bnapi->last_status_idx); | |
6dee6421 | 3537 | break; |
6f535763 | 3538 | } |
e503e066 MC |
3539 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
3540 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
3541 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT | | |
3542 | bnapi->last_status_idx); | |
3543 | ||
3544 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | |
3545 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
3546 | bnapi->last_status_idx); | |
6f535763 DM |
3547 | break; |
3548 | } | |
b6016b76 MC |
3549 | } |
3550 | ||
bea3348e | 3551 | return work_done; |
b6016b76 MC |
3552 | } |
3553 | ||
932ff279 | 3554 | /* Called with rtnl_lock from vlan functions and also netif_tx_lock |
b6016b76 MC |
3555 | * from set_multicast. |
3556 | */ | |
3557 | static void | |
3558 | bnx2_set_rx_mode(struct net_device *dev) | |
3559 | { | |
972ec0d4 | 3560 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 3561 | u32 rx_mode, sort_mode; |
ccffad25 | 3562 | struct netdev_hw_addr *ha; |
b6016b76 | 3563 | int i; |
b6016b76 | 3564 | |
9f52b564 MC |
3565 | if (!netif_running(dev)) |
3566 | return; | |
3567 | ||
c770a65c | 3568 | spin_lock_bh(&bp->phy_lock); |
b6016b76 MC |
3569 | |
3570 | rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | | |
3571 | BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); | |
3572 | sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; | |
f646968f | 3573 | if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
7d0fd211 | 3574 | (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) |
b6016b76 | 3575 | rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; |
b6016b76 MC |
3576 | if (dev->flags & IFF_PROMISC) { |
3577 | /* Promiscuous mode. */ | |
3578 | rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; | |
7510873d MC |
3579 | sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | |
3580 | BNX2_RPM_SORT_USER0_PROM_VLAN; | |
b6016b76 MC |
3581 | } |
3582 | else if (dev->flags & IFF_ALLMULTI) { | |
3583 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
e503e066 MC |
3584 | BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), |
3585 | 0xffffffff); | |
b6016b76 MC |
3586 | } |
3587 | sort_mode |= BNX2_RPM_SORT_USER0_MC_EN; | |
3588 | } | |
3589 | else { | |
3590 | /* Accept one or more multicast(s). */ | |
b6016b76 MC |
3591 | u32 mc_filter[NUM_MC_HASH_REGISTERS]; |
3592 | u32 regidx; | |
3593 | u32 bit; | |
3594 | u32 crc; | |
3595 | ||
3596 | memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS); | |
3597 | ||
22bedad3 JP |
3598 | netdev_for_each_mc_addr(ha, dev) { |
3599 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
b6016b76 MC |
3600 | bit = crc & 0xff; |
3601 | regidx = (bit & 0xe0) >> 5; | |
3602 | bit &= 0x1f; | |
3603 | mc_filter[regidx] |= (1 << bit); | |
3604 | } | |
3605 | ||
3606 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
e503e066 MC |
3607 | BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), |
3608 | mc_filter[i]); | |
b6016b76 MC |
3609 | } |
3610 | ||
3611 | sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN; | |
3612 | } | |
3613 | ||
32e7bfc4 | 3614 | if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) { |
5fcaed01 BL |
3615 | rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; |
3616 | sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | | |
3617 | BNX2_RPM_SORT_USER0_PROM_VLAN; | |
3618 | } else if (!(dev->flags & IFF_PROMISC)) { | |
5fcaed01 | 3619 | /* Add all entries into to the match filter list */ |
ccffad25 | 3620 | i = 0; |
32e7bfc4 | 3621 | netdev_for_each_uc_addr(ha, dev) { |
ccffad25 | 3622 | bnx2_set_mac_addr(bp, ha->addr, |
5fcaed01 BL |
3623 | i + BNX2_START_UNICAST_ADDRESS_INDEX); |
3624 | sort_mode |= (1 << | |
3625 | (i + BNX2_START_UNICAST_ADDRESS_INDEX)); | |
ccffad25 | 3626 | i++; |
5fcaed01 BL |
3627 | } |
3628 | ||
3629 | } | |
3630 | ||
b6016b76 MC |
3631 | if (rx_mode != bp->rx_mode) { |
3632 | bp->rx_mode = rx_mode; | |
e503e066 | 3633 | BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); |
b6016b76 MC |
3634 | } |
3635 | ||
e503e066 MC |
3636 | BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); |
3637 | BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode); | |
3638 | BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); | |
b6016b76 | 3639 | |
c770a65c | 3640 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
3641 | } |
3642 | ||
7880b72e | 3643 | static int |
57579f76 MC |
3644 | check_fw_section(const struct firmware *fw, |
3645 | const struct bnx2_fw_file_section *section, | |
3646 | u32 alignment, bool non_empty) | |
3647 | { | |
3648 | u32 offset = be32_to_cpu(section->offset); | |
3649 | u32 len = be32_to_cpu(section->len); | |
3650 | ||
3651 | if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3) | |
3652 | return -EINVAL; | |
3653 | if ((non_empty && len == 0) || len > fw->size - offset || | |
3654 | len & (alignment - 1)) | |
3655 | return -EINVAL; | |
3656 | return 0; | |
3657 | } | |
3658 | ||
7880b72e | 3659 | static int |
57579f76 MC |
3660 | check_mips_fw_entry(const struct firmware *fw, |
3661 | const struct bnx2_mips_fw_file_entry *entry) | |
3662 | { | |
3663 | if (check_fw_section(fw, &entry->text, 4, true) || | |
3664 | check_fw_section(fw, &entry->data, 4, false) || | |
3665 | check_fw_section(fw, &entry->rodata, 4, false)) | |
3666 | return -EINVAL; | |
3667 | return 0; | |
3668 | } | |
3669 | ||
7880b72e | 3670 | static void bnx2_release_firmware(struct bnx2 *bp) |
3671 | { | |
3672 | if (bp->rv2p_firmware) { | |
3673 | release_firmware(bp->mips_firmware); | |
3674 | release_firmware(bp->rv2p_firmware); | |
3675 | bp->rv2p_firmware = NULL; | |
3676 | } | |
3677 | } | |
3678 | ||
3679 | static int bnx2_request_uncached_firmware(struct bnx2 *bp) | |
b6016b76 | 3680 | { |
57579f76 | 3681 | const char *mips_fw_file, *rv2p_fw_file; |
5ee1c326 BB |
3682 | const struct bnx2_mips_fw_file *mips_fw; |
3683 | const struct bnx2_rv2p_fw_file *rv2p_fw; | |
57579f76 MC |
3684 | int rc; |
3685 | ||
4ce45e02 | 3686 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
57579f76 | 3687 | mips_fw_file = FW_MIPS_FILE_09; |
4ce45e02 MC |
3688 | if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) || |
3689 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1)) | |
078b0735 MC |
3690 | rv2p_fw_file = FW_RV2P_FILE_09_Ax; |
3691 | else | |
3692 | rv2p_fw_file = FW_RV2P_FILE_09; | |
57579f76 MC |
3693 | } else { |
3694 | mips_fw_file = FW_MIPS_FILE_06; | |
3695 | rv2p_fw_file = FW_RV2P_FILE_06; | |
3696 | } | |
3697 | ||
3698 | rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev); | |
3699 | if (rc) { | |
3a9c6a49 | 3700 | pr_err("Can't load firmware file \"%s\"\n", mips_fw_file); |
7880b72e | 3701 | goto out; |
57579f76 MC |
3702 | } |
3703 | ||
3704 | rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev); | |
3705 | if (rc) { | |
3a9c6a49 | 3706 | pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file); |
7880b72e | 3707 | goto err_release_mips_firmware; |
57579f76 | 3708 | } |
5ee1c326 BB |
3709 | mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; |
3710 | rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; | |
3711 | if (bp->mips_firmware->size < sizeof(*mips_fw) || | |
3712 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) || | |
3713 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) || | |
3714 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) || | |
3715 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) || | |
3716 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) { | |
3a9c6a49 | 3717 | pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file); |
7880b72e | 3718 | rc = -EINVAL; |
3719 | goto err_release_firmware; | |
57579f76 | 3720 | } |
5ee1c326 BB |
3721 | if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) || |
3722 | check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) || | |
3723 | check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) { | |
3a9c6a49 | 3724 | pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file); |
7880b72e | 3725 | rc = -EINVAL; |
3726 | goto err_release_firmware; | |
57579f76 | 3727 | } |
7880b72e | 3728 | out: |
3729 | return rc; | |
57579f76 | 3730 | |
7880b72e | 3731 | err_release_firmware: |
3732 | release_firmware(bp->rv2p_firmware); | |
3733 | bp->rv2p_firmware = NULL; | |
3734 | err_release_mips_firmware: | |
3735 | release_firmware(bp->mips_firmware); | |
3736 | goto out; | |
3737 | } | |
3738 | ||
3739 | static int bnx2_request_firmware(struct bnx2 *bp) | |
3740 | { | |
3741 | return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp); | |
57579f76 MC |
3742 | } |
3743 | ||
3744 | static u32 | |
3745 | rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code) | |
3746 | { | |
3747 | switch (idx) { | |
3748 | case RV2P_P1_FIXUP_PAGE_SIZE_IDX: | |
3749 | rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK; | |
3750 | rv2p_code |= RV2P_BD_PAGE_SIZE; | |
3751 | break; | |
3752 | } | |
3753 | return rv2p_code; | |
3754 | } | |
3755 | ||
3756 | static int | |
3757 | load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc, | |
3758 | const struct bnx2_rv2p_fw_file_entry *fw_entry) | |
3759 | { | |
3760 | u32 rv2p_code_len, file_offset; | |
3761 | __be32 *rv2p_code; | |
b6016b76 | 3762 | int i; |
57579f76 MC |
3763 | u32 val, cmd, addr; |
3764 | ||
3765 | rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len); | |
3766 | file_offset = be32_to_cpu(fw_entry->rv2p.offset); | |
3767 | ||
3768 | rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); | |
b6016b76 | 3769 | |
57579f76 MC |
3770 | if (rv2p_proc == RV2P_PROC1) { |
3771 | cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR; | |
3772 | addr = BNX2_RV2P_PROC1_ADDR_CMD; | |
3773 | } else { | |
3774 | cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR; | |
3775 | addr = BNX2_RV2P_PROC2_ADDR_CMD; | |
d25be1d3 | 3776 | } |
b6016b76 MC |
3777 | |
3778 | for (i = 0; i < rv2p_code_len; i += 8) { | |
e503e066 | 3779 | BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code)); |
b6016b76 | 3780 | rv2p_code++; |
e503e066 | 3781 | BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code)); |
b6016b76 MC |
3782 | rv2p_code++; |
3783 | ||
57579f76 | 3784 | val = (i / 8) | cmd; |
e503e066 | 3785 | BNX2_WR(bp, addr, val); |
57579f76 MC |
3786 | } |
3787 | ||
3788 | rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); | |
3789 | for (i = 0; i < 8; i++) { | |
3790 | u32 loc, code; | |
3791 | ||
3792 | loc = be32_to_cpu(fw_entry->fixup[i]); | |
3793 | if (loc && ((loc * 4) < rv2p_code_len)) { | |
3794 | code = be32_to_cpu(*(rv2p_code + loc - 1)); | |
e503e066 | 3795 | BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code); |
57579f76 MC |
3796 | code = be32_to_cpu(*(rv2p_code + loc)); |
3797 | code = rv2p_fw_fixup(rv2p_proc, i, loc, code); | |
e503e066 | 3798 | BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code); |
57579f76 MC |
3799 | |
3800 | val = (loc / 2) | cmd; | |
e503e066 | 3801 | BNX2_WR(bp, addr, val); |
b6016b76 MC |
3802 | } |
3803 | } | |
3804 | ||
3805 | /* Reset the processor, un-stall is done later. */ | |
3806 | if (rv2p_proc == RV2P_PROC1) { | |
e503e066 | 3807 | BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET); |
b6016b76 MC |
3808 | } |
3809 | else { | |
e503e066 | 3810 | BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); |
b6016b76 | 3811 | } |
57579f76 MC |
3812 | |
3813 | return 0; | |
b6016b76 MC |
3814 | } |
3815 | ||
af3ee519 | 3816 | static int |
57579f76 MC |
3817 | load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, |
3818 | const struct bnx2_mips_fw_file_entry *fw_entry) | |
b6016b76 | 3819 | { |
57579f76 MC |
3820 | u32 addr, len, file_offset; |
3821 | __be32 *data; | |
b6016b76 MC |
3822 | u32 offset; |
3823 | u32 val; | |
3824 | ||
3825 | /* Halt the CPU. */ | |
2726d6e1 | 3826 | val = bnx2_reg_rd_ind(bp, cpu_reg->mode); |
b6016b76 | 3827 | val |= cpu_reg->mode_value_halt; |
2726d6e1 MC |
3828 | bnx2_reg_wr_ind(bp, cpu_reg->mode, val); |
3829 | bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); | |
b6016b76 MC |
3830 | |
3831 | /* Load the Text area. */ | |
57579f76 MC |
3832 | addr = be32_to_cpu(fw_entry->text.addr); |
3833 | len = be32_to_cpu(fw_entry->text.len); | |
3834 | file_offset = be32_to_cpu(fw_entry->text.offset); | |
3835 | data = (__be32 *)(bp->mips_firmware->data + file_offset); | |
ea1f8d5c | 3836 | |
57579f76 MC |
3837 | offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); |
3838 | if (len) { | |
b6016b76 MC |
3839 | int j; |
3840 | ||
57579f76 MC |
3841 | for (j = 0; j < (len / 4); j++, offset += 4) |
3842 | bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); | |
b6016b76 MC |
3843 | } |
3844 | ||
57579f76 MC |
3845 | /* Load the Data area. */ |
3846 | addr = be32_to_cpu(fw_entry->data.addr); | |
3847 | len = be32_to_cpu(fw_entry->data.len); | |
3848 | file_offset = be32_to_cpu(fw_entry->data.offset); | |
3849 | data = (__be32 *)(bp->mips_firmware->data + file_offset); | |
b6016b76 | 3850 | |
57579f76 MC |
3851 | offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); |
3852 | if (len) { | |
b6016b76 MC |
3853 | int j; |
3854 | ||
57579f76 MC |
3855 | for (j = 0; j < (len / 4); j++, offset += 4) |
3856 | bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); | |
b6016b76 MC |
3857 | } |
3858 | ||
3859 | /* Load the Read-Only area. */ | |
57579f76 MC |
3860 | addr = be32_to_cpu(fw_entry->rodata.addr); |
3861 | len = be32_to_cpu(fw_entry->rodata.len); | |
3862 | file_offset = be32_to_cpu(fw_entry->rodata.offset); | |
3863 | data = (__be32 *)(bp->mips_firmware->data + file_offset); | |
3864 | ||
3865 | offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); | |
3866 | if (len) { | |
b6016b76 MC |
3867 | int j; |
3868 | ||
57579f76 MC |
3869 | for (j = 0; j < (len / 4); j++, offset += 4) |
3870 | bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); | |
b6016b76 MC |
3871 | } |
3872 | ||
3873 | /* Clear the pre-fetch instruction. */ | |
2726d6e1 | 3874 | bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); |
57579f76 MC |
3875 | |
3876 | val = be32_to_cpu(fw_entry->start_addr); | |
3877 | bnx2_reg_wr_ind(bp, cpu_reg->pc, val); | |
b6016b76 MC |
3878 | |
3879 | /* Start the CPU. */ | |
2726d6e1 | 3880 | val = bnx2_reg_rd_ind(bp, cpu_reg->mode); |
b6016b76 | 3881 | val &= ~cpu_reg->mode_value_halt; |
2726d6e1 MC |
3882 | bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); |
3883 | bnx2_reg_wr_ind(bp, cpu_reg->mode, val); | |
af3ee519 MC |
3884 | |
3885 | return 0; | |
b6016b76 MC |
3886 | } |
3887 | ||
fba9fe91 | 3888 | static int |
b6016b76 MC |
3889 | bnx2_init_cpus(struct bnx2 *bp) |
3890 | { | |
57579f76 MC |
3891 | const struct bnx2_mips_fw_file *mips_fw = |
3892 | (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; | |
3893 | const struct bnx2_rv2p_fw_file *rv2p_fw = | |
3894 | (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; | |
3895 | int rc; | |
b6016b76 MC |
3896 | |
3897 | /* Initialize the RV2P processor. */ | |
57579f76 MC |
3898 | load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1); |
3899 | load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2); | |
b6016b76 MC |
3900 | |
3901 | /* Initialize the RX Processor. */ | |
57579f76 | 3902 | rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp); |
fba9fe91 MC |
3903 | if (rc) |
3904 | goto init_cpu_err; | |
3905 | ||
b6016b76 | 3906 | /* Initialize the TX Processor. */ |
57579f76 | 3907 | rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp); |
fba9fe91 MC |
3908 | if (rc) |
3909 | goto init_cpu_err; | |
3910 | ||
b6016b76 | 3911 | /* Initialize the TX Patch-up Processor. */ |
57579f76 | 3912 | rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat); |
fba9fe91 MC |
3913 | if (rc) |
3914 | goto init_cpu_err; | |
3915 | ||
b6016b76 | 3916 | /* Initialize the Completion Processor. */ |
57579f76 | 3917 | rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com); |
fba9fe91 MC |
3918 | if (rc) |
3919 | goto init_cpu_err; | |
3920 | ||
d43584c8 | 3921 | /* Initialize the Command Processor. */ |
57579f76 | 3922 | rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp); |
b6016b76 | 3923 | |
fba9fe91 | 3924 | init_cpu_err: |
fba9fe91 | 3925 | return rc; |
b6016b76 MC |
3926 | } |
3927 | ||
b6a23e91 MC |
3928 | static void |
3929 | bnx2_setup_wol(struct bnx2 *bp) | |
3930 | { | |
3931 | int i; | |
3932 | u32 val, wol_msg; | |
3933 | ||
3934 | if (bp->wol) { | |
3935 | u32 advertising; | |
3936 | u8 autoneg; | |
3937 | ||
3938 | autoneg = bp->autoneg; | |
3939 | advertising = bp->advertising; | |
3940 | ||
3941 | if (bp->phy_port == PORT_TP) { | |
3942 | bp->autoneg = AUTONEG_SPEED; | |
3943 | bp->advertising = ADVERTISED_10baseT_Half | | |
3944 | ADVERTISED_10baseT_Full | | |
3945 | ADVERTISED_100baseT_Half | | |
3946 | ADVERTISED_100baseT_Full | | |
3947 | ADVERTISED_Autoneg; | |
3948 | } | |
3949 | ||
3950 | spin_lock_bh(&bp->phy_lock); | |
3951 | bnx2_setup_phy(bp, bp->phy_port); | |
3952 | spin_unlock_bh(&bp->phy_lock); | |
3953 | ||
3954 | bp->autoneg = autoneg; | |
3955 | bp->advertising = advertising; | |
3956 | ||
3957 | bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); | |
3958 | ||
3959 | val = BNX2_RD(bp, BNX2_EMAC_MODE); | |
3960 | ||
3961 | /* Enable port mode. */ | |
3962 | val &= ~BNX2_EMAC_MODE_PORT; | |
3963 | val |= BNX2_EMAC_MODE_MPKT_RCVD | | |
3964 | BNX2_EMAC_MODE_ACPI_RCVD | | |
3965 | BNX2_EMAC_MODE_MPKT; | |
3966 | if (bp->phy_port == PORT_TP) { | |
3967 | val |= BNX2_EMAC_MODE_PORT_MII; | |
3968 | } else { | |
3969 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
3970 | if (bp->line_speed == SPEED_2500) | |
3971 | val |= BNX2_EMAC_MODE_25G_MODE; | |
3972 | } | |
3973 | ||
3974 | BNX2_WR(bp, BNX2_EMAC_MODE, val); | |
3975 | ||
3976 | /* receive all multicast */ | |
3977 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
3978 | BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | |
3979 | 0xffffffff); | |
3980 | } | |
3981 | BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE); | |
3982 | ||
3983 | val = 1 | BNX2_RPM_SORT_USER0_BC_EN | BNX2_RPM_SORT_USER0_MC_EN; | |
3984 | BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); | |
3985 | BNX2_WR(bp, BNX2_RPM_SORT_USER0, val); | |
3986 | BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA); | |
3987 | ||
3988 | /* Need to enable EMAC and RPM for WOL. */ | |
3989 | BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | |
3990 | BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE | | |
3991 | BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE | | |
3992 | BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE); | |
3993 | ||
3994 | val = BNX2_RD(bp, BNX2_RPM_CONFIG); | |
3995 | val &= ~BNX2_RPM_CONFIG_ACPI_ENA; | |
3996 | BNX2_WR(bp, BNX2_RPM_CONFIG, val); | |
3997 | ||
3998 | wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | |
3999 | } else { | |
4000 | wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | |
4001 | } | |
4002 | ||
4003 | if (!(bp->flags & BNX2_FLAG_NO_WOL)) | |
4004 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 1, 0); | |
4005 | ||
4006 | } | |
4007 | ||
b6016b76 | 4008 | static int |
829ca9a3 | 4009 | bnx2_set_power_state(struct bnx2 *bp, pci_power_t state) |
b6016b76 | 4010 | { |
b6016b76 | 4011 | switch (state) { |
829ca9a3 | 4012 | case PCI_D0: { |
b6016b76 MC |
4013 | u32 val; |
4014 | ||
6d5e85c7 MC |
4015 | pci_enable_wake(bp->pdev, PCI_D0, false); |
4016 | pci_set_power_state(bp->pdev, PCI_D0); | |
b6016b76 | 4017 | |
e503e066 | 4018 | val = BNX2_RD(bp, BNX2_EMAC_MODE); |
b6016b76 MC |
4019 | val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; |
4020 | val &= ~BNX2_EMAC_MODE_MPKT; | |
e503e066 | 4021 | BNX2_WR(bp, BNX2_EMAC_MODE, val); |
b6016b76 | 4022 | |
e503e066 | 4023 | val = BNX2_RD(bp, BNX2_RPM_CONFIG); |
b6016b76 | 4024 | val &= ~BNX2_RPM_CONFIG_ACPI_ENA; |
e503e066 | 4025 | BNX2_WR(bp, BNX2_RPM_CONFIG, val); |
b6016b76 MC |
4026 | break; |
4027 | } | |
829ca9a3 | 4028 | case PCI_D3hot: { |
b6a23e91 | 4029 | bnx2_setup_wol(bp); |
6d5e85c7 | 4030 | pci_wake_from_d3(bp->pdev, bp->wol); |
4ce45e02 MC |
4031 | if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || |
4032 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) { | |
b6016b76 MC |
4033 | |
4034 | if (bp->wol) | |
6d5e85c7 MC |
4035 | pci_set_power_state(bp->pdev, PCI_D3hot); |
4036 | } else { | |
4037 | pci_set_power_state(bp->pdev, PCI_D3hot); | |
b6016b76 | 4038 | } |
b6016b76 MC |
4039 | |
4040 | /* No more memory access after this point until | |
4041 | * device is brought back to D0. | |
4042 | */ | |
b6016b76 MC |
4043 | break; |
4044 | } | |
4045 | default: | |
4046 | return -EINVAL; | |
4047 | } | |
4048 | return 0; | |
4049 | } | |
4050 | ||
4051 | static int | |
4052 | bnx2_acquire_nvram_lock(struct bnx2 *bp) | |
4053 | { | |
4054 | u32 val; | |
4055 | int j; | |
4056 | ||
4057 | /* Request access to the flash interface. */ | |
e503e066 | 4058 | BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2); |
b6016b76 | 4059 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { |
e503e066 | 4060 | val = BNX2_RD(bp, BNX2_NVM_SW_ARB); |
b6016b76 MC |
4061 | if (val & BNX2_NVM_SW_ARB_ARB_ARB2) |
4062 | break; | |
4063 | ||
4064 | udelay(5); | |
4065 | } | |
4066 | ||
4067 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4068 | return -EBUSY; | |
4069 | ||
4070 | return 0; | |
4071 | } | |
4072 | ||
4073 | static int | |
4074 | bnx2_release_nvram_lock(struct bnx2 *bp) | |
4075 | { | |
4076 | int j; | |
4077 | u32 val; | |
4078 | ||
4079 | /* Relinquish nvram interface. */ | |
e503e066 | 4080 | BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2); |
b6016b76 MC |
4081 | |
4082 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
e503e066 | 4083 | val = BNX2_RD(bp, BNX2_NVM_SW_ARB); |
b6016b76 MC |
4084 | if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2)) |
4085 | break; | |
4086 | ||
4087 | udelay(5); | |
4088 | } | |
4089 | ||
4090 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4091 | return -EBUSY; | |
4092 | ||
4093 | return 0; | |
4094 | } | |
4095 | ||
4096 | ||
4097 | static int | |
4098 | bnx2_enable_nvram_write(struct bnx2 *bp) | |
4099 | { | |
4100 | u32 val; | |
4101 | ||
e503e066 MC |
4102 | val = BNX2_RD(bp, BNX2_MISC_CFG); |
4103 | BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI); | |
b6016b76 | 4104 | |
e30372c9 | 4105 | if (bp->flash_info->flags & BNX2_NV_WREN) { |
b6016b76 MC |
4106 | int j; |
4107 | ||
e503e066 MC |
4108 | BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); |
4109 | BNX2_WR(bp, BNX2_NVM_COMMAND, | |
4110 | BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT); | |
b6016b76 MC |
4111 | |
4112 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4113 | udelay(5); | |
4114 | ||
e503e066 | 4115 | val = BNX2_RD(bp, BNX2_NVM_COMMAND); |
b6016b76 MC |
4116 | if (val & BNX2_NVM_COMMAND_DONE) |
4117 | break; | |
4118 | } | |
4119 | ||
4120 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4121 | return -EBUSY; | |
4122 | } | |
4123 | return 0; | |
4124 | } | |
4125 | ||
4126 | static void | |
4127 | bnx2_disable_nvram_write(struct bnx2 *bp) | |
4128 | { | |
4129 | u32 val; | |
4130 | ||
e503e066 MC |
4131 | val = BNX2_RD(bp, BNX2_MISC_CFG); |
4132 | BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN); | |
b6016b76 MC |
4133 | } |
4134 | ||
4135 | ||
4136 | static void | |
4137 | bnx2_enable_nvram_access(struct bnx2 *bp) | |
4138 | { | |
4139 | u32 val; | |
4140 | ||
e503e066 | 4141 | val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); |
b6016b76 | 4142 | /* Enable both bits, even on read. */ |
e503e066 MC |
4143 | BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE, |
4144 | val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); | |
b6016b76 MC |
4145 | } |
4146 | ||
4147 | static void | |
4148 | bnx2_disable_nvram_access(struct bnx2 *bp) | |
4149 | { | |
4150 | u32 val; | |
4151 | ||
e503e066 | 4152 | val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); |
b6016b76 | 4153 | /* Disable both bits, even after read. */ |
e503e066 | 4154 | BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE, |
b6016b76 MC |
4155 | val & ~(BNX2_NVM_ACCESS_ENABLE_EN | |
4156 | BNX2_NVM_ACCESS_ENABLE_WR_EN)); | |
4157 | } | |
4158 | ||
4159 | static int | |
4160 | bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset) | |
4161 | { | |
4162 | u32 cmd; | |
4163 | int j; | |
4164 | ||
e30372c9 | 4165 | if (bp->flash_info->flags & BNX2_NV_BUFFERED) |
b6016b76 MC |
4166 | /* Buffered flash, no erase needed */ |
4167 | return 0; | |
4168 | ||
4169 | /* Build an erase command */ | |
4170 | cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR | | |
4171 | BNX2_NVM_COMMAND_DOIT; | |
4172 | ||
4173 | /* Need to clear DONE bit separately. */ | |
e503e066 | 4174 | BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); |
b6016b76 MC |
4175 | |
4176 | /* Address of the NVRAM to read from. */ | |
e503e066 | 4177 | BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); |
b6016b76 MC |
4178 | |
4179 | /* Issue an erase command. */ | |
e503e066 | 4180 | BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); |
b6016b76 MC |
4181 | |
4182 | /* Wait for completion. */ | |
4183 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4184 | u32 val; | |
4185 | ||
4186 | udelay(5); | |
4187 | ||
e503e066 | 4188 | val = BNX2_RD(bp, BNX2_NVM_COMMAND); |
b6016b76 MC |
4189 | if (val & BNX2_NVM_COMMAND_DONE) |
4190 | break; | |
4191 | } | |
4192 | ||
4193 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4194 | return -EBUSY; | |
4195 | ||
4196 | return 0; | |
4197 | } | |
4198 | ||
4199 | static int | |
4200 | bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) | |
4201 | { | |
4202 | u32 cmd; | |
4203 | int j; | |
4204 | ||
4205 | /* Build the command word. */ | |
4206 | cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags; | |
4207 | ||
e30372c9 MC |
4208 | /* Calculate an offset of a buffered flash, not needed for 5709. */ |
4209 | if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { | |
b6016b76 MC |
4210 | offset = ((offset / bp->flash_info->page_size) << |
4211 | bp->flash_info->page_bits) + | |
4212 | (offset % bp->flash_info->page_size); | |
4213 | } | |
4214 | ||
4215 | /* Need to clear DONE bit separately. */ | |
e503e066 | 4216 | BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); |
b6016b76 MC |
4217 | |
4218 | /* Address of the NVRAM to read from. */ | |
e503e066 | 4219 | BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); |
b6016b76 MC |
4220 | |
4221 | /* Issue a read command. */ | |
e503e066 | 4222 | BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); |
b6016b76 MC |
4223 | |
4224 | /* Wait for completion. */ | |
4225 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4226 | u32 val; | |
4227 | ||
4228 | udelay(5); | |
4229 | ||
e503e066 | 4230 | val = BNX2_RD(bp, BNX2_NVM_COMMAND); |
b6016b76 | 4231 | if (val & BNX2_NVM_COMMAND_DONE) { |
e503e066 | 4232 | __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ)); |
b491edd5 | 4233 | memcpy(ret_val, &v, 4); |
b6016b76 MC |
4234 | break; |
4235 | } | |
4236 | } | |
4237 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4238 | return -EBUSY; | |
4239 | ||
4240 | return 0; | |
4241 | } | |
4242 | ||
4243 | ||
4244 | static int | |
4245 | bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) | |
4246 | { | |
b491edd5 AV |
4247 | u32 cmd; |
4248 | __be32 val32; | |
b6016b76 MC |
4249 | int j; |
4250 | ||
4251 | /* Build the command word. */ | |
4252 | cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags; | |
4253 | ||
e30372c9 MC |
4254 | /* Calculate an offset of a buffered flash, not needed for 5709. */ |
4255 | if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { | |
b6016b76 MC |
4256 | offset = ((offset / bp->flash_info->page_size) << |
4257 | bp->flash_info->page_bits) + | |
4258 | (offset % bp->flash_info->page_size); | |
4259 | } | |
4260 | ||
4261 | /* Need to clear DONE bit separately. */ | |
e503e066 | 4262 | BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); |
b6016b76 MC |
4263 | |
4264 | memcpy(&val32, val, 4); | |
b6016b76 MC |
4265 | |
4266 | /* Write the data. */ | |
e503e066 | 4267 | BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32)); |
b6016b76 MC |
4268 | |
4269 | /* Address of the NVRAM to write to. */ | |
e503e066 | 4270 | BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); |
b6016b76 MC |
4271 | |
4272 | /* Issue the write command. */ | |
e503e066 | 4273 | BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); |
b6016b76 MC |
4274 | |
4275 | /* Wait for completion. */ | |
4276 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4277 | udelay(5); | |
4278 | ||
e503e066 | 4279 | if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE) |
b6016b76 MC |
4280 | break; |
4281 | } | |
4282 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4283 | return -EBUSY; | |
4284 | ||
4285 | return 0; | |
4286 | } | |
4287 | ||
4288 | static int | |
4289 | bnx2_init_nvram(struct bnx2 *bp) | |
4290 | { | |
4291 | u32 val; | |
e30372c9 | 4292 | int j, entry_count, rc = 0; |
0ced9d01 | 4293 | const struct flash_spec *flash; |
b6016b76 | 4294 | |
4ce45e02 | 4295 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
e30372c9 MC |
4296 | bp->flash_info = &flash_5709; |
4297 | goto get_flash_size; | |
4298 | } | |
4299 | ||
b6016b76 | 4300 | /* Determine the selected interface. */ |
e503e066 | 4301 | val = BNX2_RD(bp, BNX2_NVM_CFG1); |
b6016b76 | 4302 | |
ff8ac609 | 4303 | entry_count = ARRAY_SIZE(flash_table); |
b6016b76 | 4304 | |
b6016b76 MC |
4305 | if (val & 0x40000000) { |
4306 | ||
4307 | /* Flash interface has been reconfigured */ | |
4308 | for (j = 0, flash = &flash_table[0]; j < entry_count; | |
37137709 MC |
4309 | j++, flash++) { |
4310 | if ((val & FLASH_BACKUP_STRAP_MASK) == | |
4311 | (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { | |
b6016b76 MC |
4312 | bp->flash_info = flash; |
4313 | break; | |
4314 | } | |
4315 | } | |
4316 | } | |
4317 | else { | |
37137709 | 4318 | u32 mask; |
b6016b76 MC |
4319 | /* Not yet been reconfigured */ |
4320 | ||
37137709 MC |
4321 | if (val & (1 << 23)) |
4322 | mask = FLASH_BACKUP_STRAP_MASK; | |
4323 | else | |
4324 | mask = FLASH_STRAP_MASK; | |
4325 | ||
b6016b76 MC |
4326 | for (j = 0, flash = &flash_table[0]; j < entry_count; |
4327 | j++, flash++) { | |
4328 | ||
37137709 | 4329 | if ((val & mask) == (flash->strapping & mask)) { |
b6016b76 MC |
4330 | bp->flash_info = flash; |
4331 | ||
4332 | /* Request access to the flash interface. */ | |
4333 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
4334 | return rc; | |
4335 | ||
4336 | /* Enable access to flash interface */ | |
4337 | bnx2_enable_nvram_access(bp); | |
4338 | ||
4339 | /* Reconfigure the flash interface */ | |
e503e066 MC |
4340 | BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1); |
4341 | BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2); | |
4342 | BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3); | |
4343 | BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1); | |
b6016b76 MC |
4344 | |
4345 | /* Disable access to flash interface */ | |
4346 | bnx2_disable_nvram_access(bp); | |
4347 | bnx2_release_nvram_lock(bp); | |
4348 | ||
4349 | break; | |
4350 | } | |
4351 | } | |
4352 | } /* if (val & 0x40000000) */ | |
4353 | ||
4354 | if (j == entry_count) { | |
4355 | bp->flash_info = NULL; | |
3a9c6a49 | 4356 | pr_alert("Unknown flash/EEPROM type\n"); |
1122db71 | 4357 | return -ENODEV; |
b6016b76 MC |
4358 | } |
4359 | ||
e30372c9 | 4360 | get_flash_size: |
2726d6e1 | 4361 | val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2); |
1122db71 MC |
4362 | val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK; |
4363 | if (val) | |
4364 | bp->flash_size = val; | |
4365 | else | |
4366 | bp->flash_size = bp->flash_info->total_size; | |
4367 | ||
b6016b76 MC |
4368 | return rc; |
4369 | } | |
4370 | ||
4371 | static int | |
4372 | bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf, | |
4373 | int buf_size) | |
4374 | { | |
4375 | int rc = 0; | |
4376 | u32 cmd_flags, offset32, len32, extra; | |
4377 | ||
4378 | if (buf_size == 0) | |
4379 | return 0; | |
4380 | ||
4381 | /* Request access to the flash interface. */ | |
4382 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
4383 | return rc; | |
4384 | ||
4385 | /* Enable access to flash interface */ | |
4386 | bnx2_enable_nvram_access(bp); | |
4387 | ||
4388 | len32 = buf_size; | |
4389 | offset32 = offset; | |
4390 | extra = 0; | |
4391 | ||
4392 | cmd_flags = 0; | |
4393 | ||
4394 | if (offset32 & 3) { | |
4395 | u8 buf[4]; | |
4396 | u32 pre_len; | |
4397 | ||
4398 | offset32 &= ~3; | |
4399 | pre_len = 4 - (offset & 3); | |
4400 | ||
4401 | if (pre_len >= len32) { | |
4402 | pre_len = len32; | |
4403 | cmd_flags = BNX2_NVM_COMMAND_FIRST | | |
4404 | BNX2_NVM_COMMAND_LAST; | |
4405 | } | |
4406 | else { | |
4407 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
4408 | } | |
4409 | ||
4410 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
4411 | ||
4412 | if (rc) | |
4413 | return rc; | |
4414 | ||
4415 | memcpy(ret_buf, buf + (offset & 3), pre_len); | |
4416 | ||
4417 | offset32 += 4; | |
4418 | ret_buf += pre_len; | |
4419 | len32 -= pre_len; | |
4420 | } | |
4421 | if (len32 & 3) { | |
4422 | extra = 4 - (len32 & 3); | |
4423 | len32 = (len32 + 4) & ~3; | |
4424 | } | |
4425 | ||
4426 | if (len32 == 4) { | |
4427 | u8 buf[4]; | |
4428 | ||
4429 | if (cmd_flags) | |
4430 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
4431 | else | |
4432 | cmd_flags = BNX2_NVM_COMMAND_FIRST | | |
4433 | BNX2_NVM_COMMAND_LAST; | |
4434 | ||
4435 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
4436 | ||
4437 | memcpy(ret_buf, buf, 4 - extra); | |
4438 | } | |
4439 | else if (len32 > 0) { | |
4440 | u8 buf[4]; | |
4441 | ||
4442 | /* Read the first word. */ | |
4443 | if (cmd_flags) | |
4444 | cmd_flags = 0; | |
4445 | else | |
4446 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
4447 | ||
4448 | rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags); | |
4449 | ||
4450 | /* Advance to the next dword. */ | |
4451 | offset32 += 4; | |
4452 | ret_buf += 4; | |
4453 | len32 -= 4; | |
4454 | ||
4455 | while (len32 > 4 && rc == 0) { | |
4456 | rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0); | |
4457 | ||
4458 | /* Advance to the next dword. */ | |
4459 | offset32 += 4; | |
4460 | ret_buf += 4; | |
4461 | len32 -= 4; | |
4462 | } | |
4463 | ||
4464 | if (rc) | |
4465 | return rc; | |
4466 | ||
4467 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
4468 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
4469 | ||
4470 | memcpy(ret_buf, buf, 4 - extra); | |
4471 | } | |
4472 | ||
4473 | /* Disable access to flash interface */ | |
4474 | bnx2_disable_nvram_access(bp); | |
4475 | ||
4476 | bnx2_release_nvram_lock(bp); | |
4477 | ||
4478 | return rc; | |
4479 | } | |
4480 | ||
4481 | static int | |
4482 | bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, | |
4483 | int buf_size) | |
4484 | { | |
4485 | u32 written, offset32, len32; | |
e6be763f | 4486 | u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL; |
b6016b76 MC |
4487 | int rc = 0; |
4488 | int align_start, align_end; | |
4489 | ||
4490 | buf = data_buf; | |
4491 | offset32 = offset; | |
4492 | len32 = buf_size; | |
4493 | align_start = align_end = 0; | |
4494 | ||
4495 | if ((align_start = (offset32 & 3))) { | |
4496 | offset32 &= ~3; | |
c873879c MC |
4497 | len32 += align_start; |
4498 | if (len32 < 4) | |
4499 | len32 = 4; | |
b6016b76 MC |
4500 | if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) |
4501 | return rc; | |
4502 | } | |
4503 | ||
4504 | if (len32 & 3) { | |
c873879c MC |
4505 | align_end = 4 - (len32 & 3); |
4506 | len32 += align_end; | |
4507 | if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4))) | |
4508 | return rc; | |
b6016b76 MC |
4509 | } |
4510 | ||
4511 | if (align_start || align_end) { | |
e6be763f MC |
4512 | align_buf = kmalloc(len32, GFP_KERNEL); |
4513 | if (align_buf == NULL) | |
b6016b76 MC |
4514 | return -ENOMEM; |
4515 | if (align_start) { | |
e6be763f | 4516 | memcpy(align_buf, start, 4); |
b6016b76 MC |
4517 | } |
4518 | if (align_end) { | |
e6be763f | 4519 | memcpy(align_buf + len32 - 4, end, 4); |
b6016b76 | 4520 | } |
e6be763f MC |
4521 | memcpy(align_buf + align_start, data_buf, buf_size); |
4522 | buf = align_buf; | |
b6016b76 MC |
4523 | } |
4524 | ||
e30372c9 | 4525 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
ae181bc4 MC |
4526 | flash_buffer = kmalloc(264, GFP_KERNEL); |
4527 | if (flash_buffer == NULL) { | |
4528 | rc = -ENOMEM; | |
4529 | goto nvram_write_end; | |
4530 | } | |
4531 | } | |
4532 | ||
b6016b76 MC |
4533 | written = 0; |
4534 | while ((written < len32) && (rc == 0)) { | |
4535 | u32 page_start, page_end, data_start, data_end; | |
4536 | u32 addr, cmd_flags; | |
4537 | int i; | |
b6016b76 MC |
4538 | |
4539 | /* Find the page_start addr */ | |
4540 | page_start = offset32 + written; | |
4541 | page_start -= (page_start % bp->flash_info->page_size); | |
4542 | /* Find the page_end addr */ | |
4543 | page_end = page_start + bp->flash_info->page_size; | |
4544 | /* Find the data_start addr */ | |
4545 | data_start = (written == 0) ? offset32 : page_start; | |
4546 | /* Find the data_end addr */ | |
6aa20a22 | 4547 | data_end = (page_end > offset32 + len32) ? |
b6016b76 MC |
4548 | (offset32 + len32) : page_end; |
4549 | ||
4550 | /* Request access to the flash interface. */ | |
4551 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
4552 | goto nvram_write_end; | |
4553 | ||
4554 | /* Enable access to flash interface */ | |
4555 | bnx2_enable_nvram_access(bp); | |
4556 | ||
4557 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
e30372c9 | 4558 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
b6016b76 MC |
4559 | int j; |
4560 | ||
4561 | /* Read the whole page into the buffer | |
4562 | * (non-buffer flash only) */ | |
4563 | for (j = 0; j < bp->flash_info->page_size; j += 4) { | |
4564 | if (j == (bp->flash_info->page_size - 4)) { | |
4565 | cmd_flags |= BNX2_NVM_COMMAND_LAST; | |
4566 | } | |
4567 | rc = bnx2_nvram_read_dword(bp, | |
6aa20a22 JG |
4568 | page_start + j, |
4569 | &flash_buffer[j], | |
b6016b76 MC |
4570 | cmd_flags); |
4571 | ||
4572 | if (rc) | |
4573 | goto nvram_write_end; | |
4574 | ||
4575 | cmd_flags = 0; | |
4576 | } | |
4577 | } | |
4578 | ||
4579 | /* Enable writes to flash interface (unlock write-protect) */ | |
4580 | if ((rc = bnx2_enable_nvram_write(bp)) != 0) | |
4581 | goto nvram_write_end; | |
4582 | ||
b6016b76 MC |
4583 | /* Loop to write back the buffer data from page_start to |
4584 | * data_start */ | |
4585 | i = 0; | |
e30372c9 | 4586 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
c873879c MC |
4587 | /* Erase the page */ |
4588 | if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) | |
4589 | goto nvram_write_end; | |
4590 | ||
4591 | /* Re-enable the write again for the actual write */ | |
4592 | bnx2_enable_nvram_write(bp); | |
4593 | ||
b6016b76 MC |
4594 | for (addr = page_start; addr < data_start; |
4595 | addr += 4, i += 4) { | |
6aa20a22 | 4596 | |
b6016b76 MC |
4597 | rc = bnx2_nvram_write_dword(bp, addr, |
4598 | &flash_buffer[i], cmd_flags); | |
4599 | ||
4600 | if (rc != 0) | |
4601 | goto nvram_write_end; | |
4602 | ||
4603 | cmd_flags = 0; | |
4604 | } | |
4605 | } | |
4606 | ||
4607 | /* Loop to write the new data from data_start to data_end */ | |
bae25761 | 4608 | for (addr = data_start; addr < data_end; addr += 4, i += 4) { |
b6016b76 | 4609 | if ((addr == page_end - 4) || |
e30372c9 | 4610 | ((bp->flash_info->flags & BNX2_NV_BUFFERED) && |
b6016b76 MC |
4611 | (addr == data_end - 4))) { |
4612 | ||
4613 | cmd_flags |= BNX2_NVM_COMMAND_LAST; | |
4614 | } | |
4615 | rc = bnx2_nvram_write_dword(bp, addr, buf, | |
4616 | cmd_flags); | |
4617 | ||
4618 | if (rc != 0) | |
4619 | goto nvram_write_end; | |
4620 | ||
4621 | cmd_flags = 0; | |
4622 | buf += 4; | |
4623 | } | |
4624 | ||
4625 | /* Loop to write back the buffer data from data_end | |
4626 | * to page_end */ | |
e30372c9 | 4627 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
b6016b76 MC |
4628 | for (addr = data_end; addr < page_end; |
4629 | addr += 4, i += 4) { | |
6aa20a22 | 4630 | |
b6016b76 MC |
4631 | if (addr == page_end-4) { |
4632 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
4633 | } | |
4634 | rc = bnx2_nvram_write_dword(bp, addr, | |
4635 | &flash_buffer[i], cmd_flags); | |
4636 | ||
4637 | if (rc != 0) | |
4638 | goto nvram_write_end; | |
4639 | ||
4640 | cmd_flags = 0; | |
4641 | } | |
4642 | } | |
4643 | ||
4644 | /* Disable writes to flash interface (lock write-protect) */ | |
4645 | bnx2_disable_nvram_write(bp); | |
4646 | ||
4647 | /* Disable access to flash interface */ | |
4648 | bnx2_disable_nvram_access(bp); | |
4649 | bnx2_release_nvram_lock(bp); | |
4650 | ||
4651 | /* Increment written */ | |
4652 | written += data_end - data_start; | |
4653 | } | |
4654 | ||
4655 | nvram_write_end: | |
e6be763f MC |
4656 | kfree(flash_buffer); |
4657 | kfree(align_buf); | |
b6016b76 MC |
4658 | return rc; |
4659 | } | |
4660 | ||
0d8a6571 | 4661 | static void |
7c62e83b | 4662 | bnx2_init_fw_cap(struct bnx2 *bp) |
0d8a6571 | 4663 | { |
7c62e83b | 4664 | u32 val, sig = 0; |
0d8a6571 | 4665 | |
583c28e5 | 4666 | bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP; |
7c62e83b MC |
4667 | bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN; |
4668 | ||
4669 | if (!(bp->flags & BNX2_FLAG_ASF_ENABLE)) | |
4670 | bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; | |
0d8a6571 | 4671 | |
2726d6e1 | 4672 | val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB); |
0d8a6571 MC |
4673 | if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE) |
4674 | return; | |
4675 | ||
7c62e83b MC |
4676 | if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) { |
4677 | bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; | |
4678 | sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN; | |
4679 | } | |
4680 | ||
4681 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && | |
4682 | (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) { | |
4683 | u32 link; | |
4684 | ||
583c28e5 | 4685 | bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; |
0d8a6571 | 4686 | |
7c62e83b MC |
4687 | link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); |
4688 | if (link & BNX2_LINK_STATUS_SERDES_LINK) | |
0d8a6571 MC |
4689 | bp->phy_port = PORT_FIBRE; |
4690 | else | |
4691 | bp->phy_port = PORT_TP; | |
489310a4 | 4692 | |
7c62e83b MC |
4693 | sig |= BNX2_DRV_ACK_CAP_SIGNATURE | |
4694 | BNX2_FW_CAP_REMOTE_PHY_CAPABLE; | |
0d8a6571 | 4695 | } |
7c62e83b MC |
4696 | |
4697 | if (netif_running(bp->dev) && sig) | |
4698 | bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig); | |
0d8a6571 MC |
4699 | } |
4700 | ||
b4b36042 MC |
4701 | static void |
4702 | bnx2_setup_msix_tbl(struct bnx2 *bp) | |
4703 | { | |
e503e066 | 4704 | BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN); |
b4b36042 | 4705 | |
e503e066 MC |
4706 | BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR); |
4707 | BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR); | |
b4b36042 MC |
4708 | } |
4709 | ||
b6016b76 MC |
4710 | static int |
4711 | bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) | |
4712 | { | |
4713 | u32 val; | |
4714 | int i, rc = 0; | |
489310a4 | 4715 | u8 old_port; |
b6016b76 MC |
4716 | |
4717 | /* Wait for the current PCI transaction to complete before | |
4718 | * issuing a reset. */ | |
4ce45e02 MC |
4719 | if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) || |
4720 | (BNX2_CHIP(bp) == BNX2_CHIP_5708)) { | |
e503e066 MC |
4721 | BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, |
4722 | BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | | |
4723 | BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | | |
4724 | BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | | |
4725 | BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); | |
4726 | val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); | |
a5dac108 EW |
4727 | udelay(5); |
4728 | } else { /* 5709 */ | |
e503e066 | 4729 | val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); |
a5dac108 | 4730 | val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; |
e503e066 MC |
4731 | BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); |
4732 | val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); | |
a5dac108 EW |
4733 | |
4734 | for (i = 0; i < 100; i++) { | |
4735 | msleep(1); | |
e503e066 | 4736 | val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL); |
a5dac108 EW |
4737 | if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND)) |
4738 | break; | |
4739 | } | |
4740 | } | |
b6016b76 | 4741 | |
b090ae2b | 4742 | /* Wait for the firmware to tell us it is ok to issue a reset. */ |
a2f13890 | 4743 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1); |
b090ae2b | 4744 | |
b6016b76 MC |
4745 | /* Deposit a driver reset signature so the firmware knows that |
4746 | * this is a soft reset. */ | |
2726d6e1 MC |
4747 | bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE, |
4748 | BNX2_DRV_RESET_SIGNATURE_MAGIC); | |
b6016b76 | 4749 | |
b6016b76 MC |
4750 | /* Do a dummy read to force the chip to complete all current transaction |
4751 | * before we issue a reset. */ | |
e503e066 | 4752 | val = BNX2_RD(bp, BNX2_MISC_ID); |
b6016b76 | 4753 | |
4ce45e02 | 4754 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
e503e066 MC |
4755 | BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); |
4756 | BNX2_RD(bp, BNX2_MISC_COMMAND); | |
234754d5 | 4757 | udelay(5); |
b6016b76 | 4758 | |
234754d5 MC |
4759 | val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | |
4760 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; | |
b6016b76 | 4761 | |
e503e066 | 4762 | BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); |
b6016b76 | 4763 | |
234754d5 MC |
4764 | } else { |
4765 | val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
4766 | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | | |
4767 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; | |
4768 | ||
4769 | /* Chip reset. */ | |
e503e066 | 4770 | BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); |
234754d5 | 4771 | |
594a9dfa MC |
4772 | /* Reading back any register after chip reset will hang the |
4773 | * bus on 5706 A0 and A1. The msleep below provides plenty | |
4774 | * of margin for write posting. | |
4775 | */ | |
4ce45e02 MC |
4776 | if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || |
4777 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) | |
8e545881 | 4778 | msleep(20); |
b6016b76 | 4779 | |
234754d5 MC |
4780 | /* Reset takes approximate 30 usec */ |
4781 | for (i = 0; i < 10; i++) { | |
e503e066 | 4782 | val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG); |
234754d5 MC |
4783 | if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | |
4784 | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) | |
4785 | break; | |
4786 | udelay(10); | |
4787 | } | |
4788 | ||
4789 | if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
4790 | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { | |
3a9c6a49 | 4791 | pr_err("Chip reset did not complete\n"); |
234754d5 MC |
4792 | return -EBUSY; |
4793 | } | |
b6016b76 MC |
4794 | } |
4795 | ||
4796 | /* Make sure byte swapping is properly configured. */ | |
e503e066 | 4797 | val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0); |
b6016b76 | 4798 | if (val != 0x01020304) { |
3a9c6a49 | 4799 | pr_err("Chip not in correct endian mode\n"); |
b6016b76 MC |
4800 | return -ENODEV; |
4801 | } | |
4802 | ||
b6016b76 | 4803 | /* Wait for the firmware to finish its initialization. */ |
a2f13890 | 4804 | rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0); |
b090ae2b MC |
4805 | if (rc) |
4806 | return rc; | |
b6016b76 | 4807 | |
0d8a6571 | 4808 | spin_lock_bh(&bp->phy_lock); |
489310a4 | 4809 | old_port = bp->phy_port; |
7c62e83b | 4810 | bnx2_init_fw_cap(bp); |
583c28e5 MC |
4811 | if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) && |
4812 | old_port != bp->phy_port) | |
0d8a6571 MC |
4813 | bnx2_set_default_remote_link(bp); |
4814 | spin_unlock_bh(&bp->phy_lock); | |
4815 | ||
4ce45e02 | 4816 | if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { |
b6016b76 MC |
4817 | /* Adjust the voltage regular to two steps lower. The default |
4818 | * of this register is 0x0000000e. */ | |
e503e066 | 4819 | BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); |
b6016b76 MC |
4820 | |
4821 | /* Remove bad rbuf memory from the free pool. */ | |
4822 | rc = bnx2_alloc_bad_rbuf(bp); | |
4823 | } | |
4824 | ||
c441b8d2 | 4825 | if (bp->flags & BNX2_FLAG_USING_MSIX) { |
b4b36042 | 4826 | bnx2_setup_msix_tbl(bp); |
c441b8d2 | 4827 | /* Prevent MSIX table reads and write from timing out */ |
e503e066 | 4828 | BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL, |
c441b8d2 MC |
4829 | BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN); |
4830 | } | |
b4b36042 | 4831 | |
b6016b76 MC |
4832 | return rc; |
4833 | } | |
4834 | ||
4835 | static int | |
4836 | bnx2_init_chip(struct bnx2 *bp) | |
4837 | { | |
d8026d93 | 4838 | u32 val, mtu; |
b4b36042 | 4839 | int rc, i; |
b6016b76 MC |
4840 | |
4841 | /* Make sure the interrupt is not active. */ | |
e503e066 | 4842 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); |
b6016b76 MC |
4843 | |
4844 | val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | | |
4845 | BNX2_DMA_CONFIG_DATA_WORD_SWAP | | |
4846 | #ifdef __BIG_ENDIAN | |
6aa20a22 | 4847 | BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | |
b6016b76 | 4848 | #endif |
6aa20a22 | 4849 | BNX2_DMA_CONFIG_CNTL_WORD_SWAP | |
b6016b76 MC |
4850 | DMA_READ_CHANS << 12 | |
4851 | DMA_WRITE_CHANS << 16; | |
4852 | ||
4853 | val |= (0x2 << 20) | (1 << 11); | |
4854 | ||
f86e82fb | 4855 | if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133)) |
b6016b76 MC |
4856 | val |= (1 << 23); |
4857 | ||
4ce45e02 MC |
4858 | if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) && |
4859 | (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) && | |
4860 | !(bp->flags & BNX2_FLAG_PCIX)) | |
b6016b76 MC |
4861 | val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; |
4862 | ||
e503e066 | 4863 | BNX2_WR(bp, BNX2_DMA_CONFIG, val); |
b6016b76 | 4864 | |
4ce45e02 | 4865 | if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { |
e503e066 | 4866 | val = BNX2_RD(bp, BNX2_TDMA_CONFIG); |
b6016b76 | 4867 | val |= BNX2_TDMA_CONFIG_ONE_DMA; |
e503e066 | 4868 | BNX2_WR(bp, BNX2_TDMA_CONFIG, val); |
b6016b76 MC |
4869 | } |
4870 | ||
f86e82fb | 4871 | if (bp->flags & BNX2_FLAG_PCIX) { |
b6016b76 MC |
4872 | u16 val16; |
4873 | ||
4874 | pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, | |
4875 | &val16); | |
4876 | pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, | |
4877 | val16 & ~PCI_X_CMD_ERO); | |
4878 | } | |
4879 | ||
e503e066 MC |
4880 | BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, |
4881 | BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | | |
4882 | BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | | |
4883 | BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); | |
b6016b76 MC |
4884 | |
4885 | /* Initialize context mapping and zero out the quick contexts. The | |
4886 | * context block must have already been enabled. */ | |
4ce45e02 | 4887 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
641bdcd5 MC |
4888 | rc = bnx2_init_5709_context(bp); |
4889 | if (rc) | |
4890 | return rc; | |
4891 | } else | |
59b47d8a | 4892 | bnx2_init_context(bp); |
b6016b76 | 4893 | |
fba9fe91 MC |
4894 | if ((rc = bnx2_init_cpus(bp)) != 0) |
4895 | return rc; | |
4896 | ||
b6016b76 MC |
4897 | bnx2_init_nvram(bp); |
4898 | ||
5fcaed01 | 4899 | bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); |
b6016b76 | 4900 | |
e503e066 | 4901 | val = BNX2_RD(bp, BNX2_MQ_CONFIG); |
b6016b76 MC |
4902 | val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; |
4903 | val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; | |
4ce45e02 | 4904 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
4edd473f | 4905 | val |= BNX2_MQ_CONFIG_BIN_MQ_MODE; |
4ce45e02 | 4906 | if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax) |
4edd473f MC |
4907 | val |= BNX2_MQ_CONFIG_HALT_DIS; |
4908 | } | |
68c9f75a | 4909 | |
e503e066 | 4910 | BNX2_WR(bp, BNX2_MQ_CONFIG, val); |
b6016b76 MC |
4911 | |
4912 | val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); | |
e503e066 MC |
4913 | BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); |
4914 | BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val); | |
b6016b76 | 4915 | |
2bc4078e | 4916 | val = (BNX2_PAGE_BITS - 8) << 24; |
e503e066 | 4917 | BNX2_WR(bp, BNX2_RV2P_CONFIG, val); |
b6016b76 MC |
4918 | |
4919 | /* Configure page size. */ | |
e503e066 | 4920 | val = BNX2_RD(bp, BNX2_TBDR_CONFIG); |
b6016b76 | 4921 | val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; |
2bc4078e | 4922 | val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40; |
e503e066 | 4923 | BNX2_WR(bp, BNX2_TBDR_CONFIG, val); |
b6016b76 MC |
4924 | |
4925 | val = bp->mac_addr[0] + | |
4926 | (bp->mac_addr[1] << 8) + | |
4927 | (bp->mac_addr[2] << 16) + | |
4928 | bp->mac_addr[3] + | |
4929 | (bp->mac_addr[4] << 8) + | |
4930 | (bp->mac_addr[5] << 16); | |
e503e066 | 4931 | BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); |
b6016b76 MC |
4932 | |
4933 | /* Program the MTU. Also include 4 bytes for CRC32. */ | |
d8026d93 MC |
4934 | mtu = bp->dev->mtu; |
4935 | val = mtu + ETH_HLEN + ETH_FCS_LEN; | |
b6016b76 MC |
4936 | if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) |
4937 | val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; | |
e503e066 | 4938 | BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); |
b6016b76 | 4939 | |
d8026d93 MC |
4940 | if (mtu < 1500) |
4941 | mtu = 1500; | |
4942 | ||
4943 | bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu)); | |
4944 | bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu)); | |
4945 | bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu)); | |
4946 | ||
155d5561 | 4947 | memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size); |
b4b36042 MC |
4948 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) |
4949 | bp->bnx2_napi[i].last_status_idx = 0; | |
4950 | ||
efba0180 MC |
4951 | bp->idle_chk_status_idx = 0xffff; |
4952 | ||
b6016b76 MC |
4953 | bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE; |
4954 | ||
4955 | /* Set up how to generate a link change interrupt. */ | |
e503e066 | 4956 | BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); |
b6016b76 | 4957 | |
e503e066 MC |
4958 | BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L, |
4959 | (u64) bp->status_blk_mapping & 0xffffffff); | |
4960 | BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); | |
b6016b76 | 4961 | |
e503e066 MC |
4962 | BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L, |
4963 | (u64) bp->stats_blk_mapping & 0xffffffff); | |
4964 | BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H, | |
4965 | (u64) bp->stats_blk_mapping >> 32); | |
b6016b76 | 4966 | |
e503e066 MC |
4967 | BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, |
4968 | (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); | |
b6016b76 | 4969 | |
e503e066 MC |
4970 | BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, |
4971 | (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); | |
b6016b76 | 4972 | |
e503e066 MC |
4973 | BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP, |
4974 | (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); | |
b6016b76 | 4975 | |
e503e066 | 4976 | BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); |
b6016b76 | 4977 | |
e503e066 | 4978 | BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); |
b6016b76 | 4979 | |
e503e066 MC |
4980 | BNX2_WR(bp, BNX2_HC_COM_TICKS, |
4981 | (bp->com_ticks_int << 16) | bp->com_ticks); | |
b6016b76 | 4982 | |
e503e066 MC |
4983 | BNX2_WR(bp, BNX2_HC_CMD_TICKS, |
4984 | (bp->cmd_ticks_int << 16) | bp->cmd_ticks); | |
b6016b76 | 4985 | |
61d9e3fa | 4986 | if (bp->flags & BNX2_FLAG_BROKEN_STATS) |
e503e066 | 4987 | BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0); |
02537b06 | 4988 | else |
e503e066 MC |
4989 | BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); |
4990 | BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ | |
b6016b76 | 4991 | |
4ce45e02 | 4992 | if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) |
8e6a72c4 | 4993 | val = BNX2_HC_CONFIG_COLLECT_STATS; |
b6016b76 | 4994 | else { |
8e6a72c4 MC |
4995 | val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE | |
4996 | BNX2_HC_CONFIG_COLLECT_STATS; | |
b6016b76 MC |
4997 | } |
4998 | ||
efde73a3 | 4999 | if (bp->flags & BNX2_FLAG_USING_MSIX) { |
e503e066 MC |
5000 | BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, |
5001 | BNX2_HC_MSIX_BIT_VECTOR_VAL); | |
c76c0475 | 5002 | |
5e9ad9e1 MC |
5003 | val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; |
5004 | } | |
5005 | ||
5006 | if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) | |
cf7474a6 | 5007 | val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM; |
5e9ad9e1 | 5008 | |
e503e066 | 5009 | BNX2_WR(bp, BNX2_HC_CONFIG, val); |
5e9ad9e1 | 5010 | |
22fa159d MC |
5011 | if (bp->rx_ticks < 25) |
5012 | bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1); | |
5013 | else | |
5014 | bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0); | |
5015 | ||
5e9ad9e1 MC |
5016 | for (i = 1; i < bp->irq_nvecs; i++) { |
5017 | u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) + | |
5018 | BNX2_HC_SB_CONFIG_1; | |
5019 | ||
e503e066 | 5020 | BNX2_WR(bp, base, |
c76c0475 | 5021 | BNX2_HC_SB_CONFIG_1_TX_TMR_MODE | |
5e9ad9e1 | 5022 | BNX2_HC_SB_CONFIG_1_RX_TMR_MODE | |
c76c0475 MC |
5023 | BNX2_HC_SB_CONFIG_1_ONE_SHOT); |
5024 | ||
e503e066 | 5025 | BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF, |
c76c0475 MC |
5026 | (bp->tx_quick_cons_trip_int << 16) | |
5027 | bp->tx_quick_cons_trip); | |
5028 | ||
e503e066 | 5029 | BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF, |
c76c0475 MC |
5030 | (bp->tx_ticks_int << 16) | bp->tx_ticks); |
5031 | ||
e503e066 MC |
5032 | BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF, |
5033 | (bp->rx_quick_cons_trip_int << 16) | | |
5e9ad9e1 | 5034 | bp->rx_quick_cons_trip); |
8e6a72c4 | 5035 | |
e503e066 | 5036 | BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF, |
5e9ad9e1 MC |
5037 | (bp->rx_ticks_int << 16) | bp->rx_ticks); |
5038 | } | |
8e6a72c4 | 5039 | |
b6016b76 | 5040 | /* Clear internal stats counters. */ |
e503e066 | 5041 | BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); |
b6016b76 | 5042 | |
e503e066 | 5043 | BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS); |
b6016b76 MC |
5044 | |
5045 | /* Initialize the receive filter. */ | |
5046 | bnx2_set_rx_mode(bp->dev); | |
5047 | ||
4ce45e02 | 5048 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
e503e066 | 5049 | val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); |
0aa38df7 | 5050 | val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; |
e503e066 | 5051 | BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); |
0aa38df7 | 5052 | } |
b090ae2b | 5053 | rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, |
a2f13890 | 5054 | 1, 0); |
b6016b76 | 5055 | |
e503e066 MC |
5056 | BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT); |
5057 | BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS); | |
b6016b76 MC |
5058 | |
5059 | udelay(20); | |
5060 | ||
e503e066 | 5061 | bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND); |
bf5295bb | 5062 | |
b090ae2b | 5063 | return rc; |
b6016b76 MC |
5064 | } |
5065 | ||
c76c0475 MC |
5066 | static void |
5067 | bnx2_clear_ring_states(struct bnx2 *bp) | |
5068 | { | |
5069 | struct bnx2_napi *bnapi; | |
35e9010b | 5070 | struct bnx2_tx_ring_info *txr; |
bb4f98ab | 5071 | struct bnx2_rx_ring_info *rxr; |
c76c0475 MC |
5072 | int i; |
5073 | ||
5074 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { | |
5075 | bnapi = &bp->bnx2_napi[i]; | |
35e9010b | 5076 | txr = &bnapi->tx_ring; |
bb4f98ab | 5077 | rxr = &bnapi->rx_ring; |
c76c0475 | 5078 | |
35e9010b MC |
5079 | txr->tx_cons = 0; |
5080 | txr->hw_tx_cons = 0; | |
bb4f98ab MC |
5081 | rxr->rx_prod_bseq = 0; |
5082 | rxr->rx_prod = 0; | |
5083 | rxr->rx_cons = 0; | |
5084 | rxr->rx_pg_prod = 0; | |
5085 | rxr->rx_pg_cons = 0; | |
c76c0475 MC |
5086 | } |
5087 | } | |
5088 | ||
59b47d8a | 5089 | static void |
35e9010b | 5090 | bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr) |
59b47d8a MC |
5091 | { |
5092 | u32 val, offset0, offset1, offset2, offset3; | |
62a8313c | 5093 | u32 cid_addr = GET_CID_ADDR(cid); |
59b47d8a | 5094 | |
4ce45e02 | 5095 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
59b47d8a MC |
5096 | offset0 = BNX2_L2CTX_TYPE_XI; |
5097 | offset1 = BNX2_L2CTX_CMD_TYPE_XI; | |
5098 | offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI; | |
5099 | offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI; | |
5100 | } else { | |
5101 | offset0 = BNX2_L2CTX_TYPE; | |
5102 | offset1 = BNX2_L2CTX_CMD_TYPE; | |
5103 | offset2 = BNX2_L2CTX_TBDR_BHADDR_HI; | |
5104 | offset3 = BNX2_L2CTX_TBDR_BHADDR_LO; | |
5105 | } | |
5106 | val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; | |
62a8313c | 5107 | bnx2_ctx_wr(bp, cid_addr, offset0, val); |
59b47d8a MC |
5108 | |
5109 | val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); | |
62a8313c | 5110 | bnx2_ctx_wr(bp, cid_addr, offset1, val); |
59b47d8a | 5111 | |
35e9010b | 5112 | val = (u64) txr->tx_desc_mapping >> 32; |
62a8313c | 5113 | bnx2_ctx_wr(bp, cid_addr, offset2, val); |
59b47d8a | 5114 | |
35e9010b | 5115 | val = (u64) txr->tx_desc_mapping & 0xffffffff; |
62a8313c | 5116 | bnx2_ctx_wr(bp, cid_addr, offset3, val); |
59b47d8a | 5117 | } |
b6016b76 MC |
5118 | |
5119 | static void | |
35e9010b | 5120 | bnx2_init_tx_ring(struct bnx2 *bp, int ring_num) |
b6016b76 | 5121 | { |
2bc4078e | 5122 | struct bnx2_tx_bd *txbd; |
c76c0475 MC |
5123 | u32 cid = TX_CID; |
5124 | struct bnx2_napi *bnapi; | |
35e9010b | 5125 | struct bnx2_tx_ring_info *txr; |
c76c0475 | 5126 | |
35e9010b MC |
5127 | bnapi = &bp->bnx2_napi[ring_num]; |
5128 | txr = &bnapi->tx_ring; | |
5129 | ||
5130 | if (ring_num == 0) | |
5131 | cid = TX_CID; | |
5132 | else | |
5133 | cid = TX_TSS_CID + ring_num - 1; | |
b6016b76 | 5134 | |
2f8af120 MC |
5135 | bp->tx_wake_thresh = bp->tx_ring_size / 2; |
5136 | ||
2bc4078e | 5137 | txbd = &txr->tx_desc_ring[BNX2_MAX_TX_DESC_CNT]; |
6aa20a22 | 5138 | |
35e9010b MC |
5139 | txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32; |
5140 | txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff; | |
b6016b76 | 5141 | |
35e9010b MC |
5142 | txr->tx_prod = 0; |
5143 | txr->tx_prod_bseq = 0; | |
6aa20a22 | 5144 | |
35e9010b MC |
5145 | txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; |
5146 | txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; | |
b6016b76 | 5147 | |
35e9010b | 5148 | bnx2_init_tx_context(bp, cid, txr); |
b6016b76 MC |
5149 | } |
5150 | ||
5151 | static void | |
2bc4078e MC |
5152 | bnx2_init_rxbd_rings(struct bnx2_rx_bd *rx_ring[], dma_addr_t dma[], |
5153 | u32 buf_size, int num_rings) | |
b6016b76 | 5154 | { |
b6016b76 | 5155 | int i; |
2bc4078e | 5156 | struct bnx2_rx_bd *rxbd; |
6aa20a22 | 5157 | |
5d5d0015 | 5158 | for (i = 0; i < num_rings; i++) { |
13daffa2 | 5159 | int j; |
b6016b76 | 5160 | |
5d5d0015 | 5161 | rxbd = &rx_ring[i][0]; |
2bc4078e | 5162 | for (j = 0; j < BNX2_MAX_RX_DESC_CNT; j++, rxbd++) { |
5d5d0015 | 5163 | rxbd->rx_bd_len = buf_size; |
13daffa2 MC |
5164 | rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; |
5165 | } | |
5d5d0015 | 5166 | if (i == (num_rings - 1)) |
13daffa2 MC |
5167 | j = 0; |
5168 | else | |
5169 | j = i + 1; | |
5d5d0015 MC |
5170 | rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32; |
5171 | rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff; | |
13daffa2 | 5172 | } |
5d5d0015 MC |
5173 | } |
5174 | ||
5175 | static void | |
bb4f98ab | 5176 | bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) |
5d5d0015 MC |
5177 | { |
5178 | int i; | |
5179 | u16 prod, ring_prod; | |
bb4f98ab MC |
5180 | u32 cid, rx_cid_addr, val; |
5181 | struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num]; | |
5182 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
5183 | ||
5184 | if (ring_num == 0) | |
5185 | cid = RX_CID; | |
5186 | else | |
5187 | cid = RX_RSS_CID + ring_num - 1; | |
5188 | ||
5189 | rx_cid_addr = GET_CID_ADDR(cid); | |
5d5d0015 | 5190 | |
bb4f98ab | 5191 | bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping, |
5d5d0015 MC |
5192 | bp->rx_buf_use_size, bp->rx_max_ring); |
5193 | ||
bb4f98ab | 5194 | bnx2_init_rx_context(bp, cid); |
83e3fc89 | 5195 | |
4ce45e02 | 5196 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
e503e066 MC |
5197 | val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5); |
5198 | BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM); | |
83e3fc89 MC |
5199 | } |
5200 | ||
62a8313c | 5201 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); |
47bf4246 | 5202 | if (bp->rx_pg_ring_size) { |
bb4f98ab MC |
5203 | bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring, |
5204 | rxr->rx_pg_desc_mapping, | |
47bf4246 MC |
5205 | PAGE_SIZE, bp->rx_max_pg_ring); |
5206 | val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; | |
62a8313c MC |
5207 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); |
5208 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, | |
5e9ad9e1 | 5209 | BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num); |
47bf4246 | 5210 | |
bb4f98ab | 5211 | val = (u64) rxr->rx_pg_desc_mapping[0] >> 32; |
62a8313c | 5212 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); |
47bf4246 | 5213 | |
bb4f98ab | 5214 | val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; |
62a8313c | 5215 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); |
47bf4246 | 5216 | |
4ce45e02 | 5217 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
e503e066 | 5218 | BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); |
47bf4246 | 5219 | } |
b6016b76 | 5220 | |
bb4f98ab | 5221 | val = (u64) rxr->rx_desc_mapping[0] >> 32; |
62a8313c | 5222 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); |
b6016b76 | 5223 | |
bb4f98ab | 5224 | val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff; |
62a8313c | 5225 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); |
b6016b76 | 5226 | |
bb4f98ab | 5227 | ring_prod = prod = rxr->rx_pg_prod; |
47bf4246 | 5228 | for (i = 0; i < bp->rx_pg_ring_size; i++) { |
a2df00aa | 5229 | if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) { |
3a9c6a49 JP |
5230 | netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n", |
5231 | ring_num, i, bp->rx_pg_ring_size); | |
47bf4246 | 5232 | break; |
b929e53c | 5233 | } |
2bc4078e MC |
5234 | prod = BNX2_NEXT_RX_BD(prod); |
5235 | ring_prod = BNX2_RX_PG_RING_IDX(prod); | |
47bf4246 | 5236 | } |
bb4f98ab | 5237 | rxr->rx_pg_prod = prod; |
47bf4246 | 5238 | |
bb4f98ab | 5239 | ring_prod = prod = rxr->rx_prod; |
236b6394 | 5240 | for (i = 0; i < bp->rx_ring_size; i++) { |
dd2bc8e9 | 5241 | if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) { |
3a9c6a49 JP |
5242 | netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n", |
5243 | ring_num, i, bp->rx_ring_size); | |
b6016b76 | 5244 | break; |
b929e53c | 5245 | } |
2bc4078e MC |
5246 | prod = BNX2_NEXT_RX_BD(prod); |
5247 | ring_prod = BNX2_RX_RING_IDX(prod); | |
b6016b76 | 5248 | } |
bb4f98ab | 5249 | rxr->rx_prod = prod; |
b6016b76 | 5250 | |
bb4f98ab MC |
5251 | rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX; |
5252 | rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ; | |
5253 | rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX; | |
b6016b76 | 5254 | |
e503e066 MC |
5255 | BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); |
5256 | BNX2_WR16(bp, rxr->rx_bidx_addr, prod); | |
bb4f98ab | 5257 | |
e503e066 | 5258 | BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); |
b6016b76 MC |
5259 | } |
5260 | ||
35e9010b MC |
5261 | static void |
5262 | bnx2_init_all_rings(struct bnx2 *bp) | |
5263 | { | |
5264 | int i; | |
5e9ad9e1 | 5265 | u32 val; |
35e9010b MC |
5266 | |
5267 | bnx2_clear_ring_states(bp); | |
5268 | ||
e503e066 | 5269 | BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0); |
35e9010b MC |
5270 | for (i = 0; i < bp->num_tx_rings; i++) |
5271 | bnx2_init_tx_ring(bp, i); | |
5272 | ||
5273 | if (bp->num_tx_rings > 1) | |
e503e066 MC |
5274 | BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) | |
5275 | (TX_TSS_CID << 7)); | |
35e9010b | 5276 | |
e503e066 | 5277 | BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0); |
5e9ad9e1 MC |
5278 | bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0); |
5279 | ||
bb4f98ab MC |
5280 | for (i = 0; i < bp->num_rx_rings; i++) |
5281 | bnx2_init_rx_ring(bp, i); | |
5e9ad9e1 MC |
5282 | |
5283 | if (bp->num_rx_rings > 1) { | |
22fa159d | 5284 | u32 tbl_32 = 0; |
5e9ad9e1 MC |
5285 | |
5286 | for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) { | |
22fa159d MC |
5287 | int shift = (i % 8) << 2; |
5288 | ||
5289 | tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift; | |
5290 | if ((i % 8) == 7) { | |
e503e066 MC |
5291 | BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32); |
5292 | BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) | | |
22fa159d MC |
5293 | BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK | |
5294 | BNX2_RLUP_RSS_COMMAND_WRITE | | |
5295 | BNX2_RLUP_RSS_COMMAND_HASH_MASK); | |
5296 | tbl_32 = 0; | |
5297 | } | |
5e9ad9e1 MC |
5298 | } |
5299 | ||
5300 | val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI | | |
5301 | BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI; | |
5302 | ||
e503e066 | 5303 | BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val); |
5e9ad9e1 MC |
5304 | |
5305 | } | |
35e9010b MC |
5306 | } |
5307 | ||
5d5d0015 | 5308 | static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size) |
13daffa2 | 5309 | { |
5d5d0015 | 5310 | u32 max, num_rings = 1; |
13daffa2 | 5311 | |
2bc4078e MC |
5312 | while (ring_size > BNX2_MAX_RX_DESC_CNT) { |
5313 | ring_size -= BNX2_MAX_RX_DESC_CNT; | |
13daffa2 MC |
5314 | num_rings++; |
5315 | } | |
5316 | /* round to next power of 2 */ | |
5d5d0015 | 5317 | max = max_size; |
13daffa2 MC |
5318 | while ((max & num_rings) == 0) |
5319 | max >>= 1; | |
5320 | ||
5321 | if (num_rings != max) | |
5322 | max <<= 1; | |
5323 | ||
5d5d0015 MC |
5324 | return max; |
5325 | } | |
5326 | ||
5327 | static void | |
5328 | bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) | |
5329 | { | |
84eaa187 | 5330 | u32 rx_size, rx_space, jumbo_size; |
5d5d0015 MC |
5331 | |
5332 | /* 8 for CRC and VLAN */ | |
d89cb6af | 5333 | rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8; |
5d5d0015 | 5334 | |
84eaa187 | 5335 | rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD + |
dd2bc8e9 | 5336 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
84eaa187 | 5337 | |
601d3d18 | 5338 | bp->rx_copy_thresh = BNX2_RX_COPY_THRESH; |
47bf4246 MC |
5339 | bp->rx_pg_ring_size = 0; |
5340 | bp->rx_max_pg_ring = 0; | |
5341 | bp->rx_max_pg_ring_idx = 0; | |
f86e82fb | 5342 | if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) { |
84eaa187 MC |
5343 | int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; |
5344 | ||
5345 | jumbo_size = size * pages; | |
2bc4078e MC |
5346 | if (jumbo_size > BNX2_MAX_TOTAL_RX_PG_DESC_CNT) |
5347 | jumbo_size = BNX2_MAX_TOTAL_RX_PG_DESC_CNT; | |
84eaa187 MC |
5348 | |
5349 | bp->rx_pg_ring_size = jumbo_size; | |
5350 | bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size, | |
2bc4078e MC |
5351 | BNX2_MAX_RX_PG_RINGS); |
5352 | bp->rx_max_pg_ring_idx = | |
5353 | (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1; | |
601d3d18 | 5354 | rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET; |
84eaa187 MC |
5355 | bp->rx_copy_thresh = 0; |
5356 | } | |
5d5d0015 MC |
5357 | |
5358 | bp->rx_buf_use_size = rx_size; | |
dd2bc8e9 ED |
5359 | /* hw alignment + build_skb() overhead*/ |
5360 | bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) + | |
5361 | NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
d89cb6af | 5362 | bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET; |
5d5d0015 | 5363 | bp->rx_ring_size = size; |
2bc4078e MC |
5364 | bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS); |
5365 | bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1; | |
13daffa2 MC |
5366 | } |
5367 | ||
b6016b76 MC |
5368 | static void |
5369 | bnx2_free_tx_skbs(struct bnx2 *bp) | |
5370 | { | |
5371 | int i; | |
5372 | ||
35e9010b MC |
5373 | for (i = 0; i < bp->num_tx_rings; i++) { |
5374 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
5375 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; | |
5376 | int j; | |
b6016b76 | 5377 | |
35e9010b | 5378 | if (txr->tx_buf_ring == NULL) |
b6016b76 | 5379 | continue; |
b6016b76 | 5380 | |
2bc4078e MC |
5381 | for (j = 0; j < BNX2_TX_DESC_CNT; ) { |
5382 | struct bnx2_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; | |
35e9010b | 5383 | struct sk_buff *skb = tx_buf->skb; |
e95524a7 | 5384 | int k, last; |
35e9010b MC |
5385 | |
5386 | if (skb == NULL) { | |
2bc4078e | 5387 | j = BNX2_NEXT_TX_BD(j); |
35e9010b MC |
5388 | continue; |
5389 | } | |
5390 | ||
36227e88 | 5391 | dma_unmap_single(&bp->pdev->dev, |
1a4ccc2d | 5392 | dma_unmap_addr(tx_buf, mapping), |
e95524a7 AD |
5393 | skb_headlen(skb), |
5394 | PCI_DMA_TODEVICE); | |
b6016b76 | 5395 | |
35e9010b | 5396 | tx_buf->skb = NULL; |
b6016b76 | 5397 | |
e95524a7 | 5398 | last = tx_buf->nr_frags; |
2bc4078e MC |
5399 | j = BNX2_NEXT_TX_BD(j); |
5400 | for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) { | |
5401 | tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(j)]; | |
36227e88 | 5402 | dma_unmap_page(&bp->pdev->dev, |
1a4ccc2d | 5403 | dma_unmap_addr(tx_buf, mapping), |
9e903e08 | 5404 | skb_frag_size(&skb_shinfo(skb)->frags[k]), |
e95524a7 AD |
5405 | PCI_DMA_TODEVICE); |
5406 | } | |
35e9010b | 5407 | dev_kfree_skb(skb); |
b6016b76 | 5408 | } |
e9831909 | 5409 | netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); |
b6016b76 | 5410 | } |
b6016b76 MC |
5411 | } |
5412 | ||
5413 | static void | |
5414 | bnx2_free_rx_skbs(struct bnx2 *bp) | |
5415 | { | |
5416 | int i; | |
5417 | ||
bb4f98ab MC |
5418 | for (i = 0; i < bp->num_rx_rings; i++) { |
5419 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
5420 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
5421 | int j; | |
b6016b76 | 5422 | |
bb4f98ab MC |
5423 | if (rxr->rx_buf_ring == NULL) |
5424 | return; | |
b6016b76 | 5425 | |
bb4f98ab | 5426 | for (j = 0; j < bp->rx_max_ring_idx; j++) { |
2bc4078e | 5427 | struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[j]; |
dd2bc8e9 | 5428 | u8 *data = rx_buf->data; |
b6016b76 | 5429 | |
dd2bc8e9 | 5430 | if (data == NULL) |
bb4f98ab | 5431 | continue; |
b6016b76 | 5432 | |
36227e88 | 5433 | dma_unmap_single(&bp->pdev->dev, |
1a4ccc2d | 5434 | dma_unmap_addr(rx_buf, mapping), |
bb4f98ab MC |
5435 | bp->rx_buf_use_size, |
5436 | PCI_DMA_FROMDEVICE); | |
b6016b76 | 5437 | |
dd2bc8e9 | 5438 | rx_buf->data = NULL; |
bb4f98ab | 5439 | |
dd2bc8e9 | 5440 | kfree(data); |
bb4f98ab MC |
5441 | } |
5442 | for (j = 0; j < bp->rx_max_pg_ring_idx; j++) | |
5443 | bnx2_free_rx_page(bp, rxr, j); | |
b6016b76 MC |
5444 | } |
5445 | } | |
5446 | ||
5447 | static void | |
5448 | bnx2_free_skbs(struct bnx2 *bp) | |
5449 | { | |
5450 | bnx2_free_tx_skbs(bp); | |
5451 | bnx2_free_rx_skbs(bp); | |
5452 | } | |
5453 | ||
5454 | static int | |
5455 | bnx2_reset_nic(struct bnx2 *bp, u32 reset_code) | |
5456 | { | |
5457 | int rc; | |
5458 | ||
5459 | rc = bnx2_reset_chip(bp, reset_code); | |
5460 | bnx2_free_skbs(bp); | |
5461 | if (rc) | |
5462 | return rc; | |
5463 | ||
fba9fe91 MC |
5464 | if ((rc = bnx2_init_chip(bp)) != 0) |
5465 | return rc; | |
5466 | ||
35e9010b | 5467 | bnx2_init_all_rings(bp); |
b6016b76 MC |
5468 | return 0; |
5469 | } | |
5470 | ||
5471 | static int | |
9a120bc5 | 5472 | bnx2_init_nic(struct bnx2 *bp, int reset_phy) |
b6016b76 MC |
5473 | { |
5474 | int rc; | |
5475 | ||
5476 | if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) | |
5477 | return rc; | |
5478 | ||
80be4434 | 5479 | spin_lock_bh(&bp->phy_lock); |
9a120bc5 | 5480 | bnx2_init_phy(bp, reset_phy); |
b6016b76 | 5481 | bnx2_set_link(bp); |
543a827d MC |
5482 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
5483 | bnx2_remote_phy_event(bp); | |
0d8a6571 | 5484 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
5485 | return 0; |
5486 | } | |
5487 | ||
74bf4ba3 MC |
5488 | static int |
5489 | bnx2_shutdown_chip(struct bnx2 *bp) | |
5490 | { | |
5491 | u32 reset_code; | |
5492 | ||
5493 | if (bp->flags & BNX2_FLAG_NO_WOL) | |
5494 | reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; | |
5495 | else if (bp->wol) | |
5496 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | |
5497 | else | |
5498 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | |
5499 | ||
5500 | return bnx2_reset_chip(bp, reset_code); | |
5501 | } | |
5502 | ||
b6016b76 MC |
5503 | static int |
5504 | bnx2_test_registers(struct bnx2 *bp) | |
5505 | { | |
5506 | int ret; | |
5bae30c9 | 5507 | int i, is_5709; |
f71e1309 | 5508 | static const struct { |
b6016b76 MC |
5509 | u16 offset; |
5510 | u16 flags; | |
5bae30c9 | 5511 | #define BNX2_FL_NOT_5709 1 |
b6016b76 MC |
5512 | u32 rw_mask; |
5513 | u32 ro_mask; | |
5514 | } reg_tbl[] = { | |
5515 | { 0x006c, 0, 0x00000000, 0x0000003f }, | |
5516 | { 0x0090, 0, 0xffffffff, 0x00000000 }, | |
5517 | { 0x0094, 0, 0x00000000, 0x00000000 }, | |
5518 | ||
5bae30c9 MC |
5519 | { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 }, |
5520 | { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5521 | { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5522 | { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff }, | |
5523 | { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 }, | |
5524 | { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, | |
5525 | { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff }, | |
5526 | { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5527 | { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5528 | ||
5529 | { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5530 | { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5531 | { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
5532 | { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
5533 | { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
5534 | { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
5535 | ||
5536 | { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, | |
5537 | { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 }, | |
5538 | { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 }, | |
b6016b76 MC |
5539 | |
5540 | { 0x1000, 0, 0x00000000, 0x00000001 }, | |
15b169cc | 5541 | { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 }, |
b6016b76 MC |
5542 | |
5543 | { 0x1408, 0, 0x01c00800, 0x00000000 }, | |
5544 | { 0x149c, 0, 0x8000ffff, 0x00000000 }, | |
5545 | { 0x14a8, 0, 0x00000000, 0x000001ff }, | |
5b0c76ad | 5546 | { 0x14ac, 0, 0x0fffffff, 0x10000000 }, |
b6016b76 MC |
5547 | { 0x14b0, 0, 0x00000002, 0x00000001 }, |
5548 | { 0x14b8, 0, 0x00000000, 0x00000000 }, | |
5549 | { 0x14c0, 0, 0x00000000, 0x00000009 }, | |
5550 | { 0x14c4, 0, 0x00003fff, 0x00000000 }, | |
5551 | { 0x14cc, 0, 0x00000000, 0x00000001 }, | |
5552 | { 0x14d0, 0, 0xffffffff, 0x00000000 }, | |
b6016b76 MC |
5553 | |
5554 | { 0x1800, 0, 0x00000000, 0x00000001 }, | |
5555 | { 0x1804, 0, 0x00000000, 0x00000003 }, | |
b6016b76 MC |
5556 | |
5557 | { 0x2800, 0, 0x00000000, 0x00000001 }, | |
5558 | { 0x2804, 0, 0x00000000, 0x00003f01 }, | |
5559 | { 0x2808, 0, 0x0f3f3f03, 0x00000000 }, | |
5560 | { 0x2810, 0, 0xffff0000, 0x00000000 }, | |
5561 | { 0x2814, 0, 0xffff0000, 0x00000000 }, | |
5562 | { 0x2818, 0, 0xffff0000, 0x00000000 }, | |
5563 | { 0x281c, 0, 0xffff0000, 0x00000000 }, | |
5564 | { 0x2834, 0, 0xffffffff, 0x00000000 }, | |
5565 | { 0x2840, 0, 0x00000000, 0xffffffff }, | |
5566 | { 0x2844, 0, 0x00000000, 0xffffffff }, | |
5567 | { 0x2848, 0, 0xffffffff, 0x00000000 }, | |
5568 | { 0x284c, 0, 0xf800f800, 0x07ff07ff }, | |
5569 | ||
5570 | { 0x2c00, 0, 0x00000000, 0x00000011 }, | |
5571 | { 0x2c04, 0, 0x00000000, 0x00030007 }, | |
5572 | ||
b6016b76 MC |
5573 | { 0x3c00, 0, 0x00000000, 0x00000001 }, |
5574 | { 0x3c04, 0, 0x00000000, 0x00070000 }, | |
5575 | { 0x3c08, 0, 0x00007f71, 0x07f00000 }, | |
5576 | { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 }, | |
5577 | { 0x3c10, 0, 0xffffffff, 0x00000000 }, | |
5578 | { 0x3c14, 0, 0x00000000, 0xffffffff }, | |
5579 | { 0x3c18, 0, 0x00000000, 0xffffffff }, | |
5580 | { 0x3c1c, 0, 0xfffff000, 0x00000000 }, | |
5581 | { 0x3c20, 0, 0xffffff00, 0x00000000 }, | |
b6016b76 MC |
5582 | |
5583 | { 0x5004, 0, 0x00000000, 0x0000007f }, | |
5584 | { 0x5008, 0, 0x0f0007ff, 0x00000000 }, | |
b6016b76 | 5585 | |
b6016b76 MC |
5586 | { 0x5c00, 0, 0x00000000, 0x00000001 }, |
5587 | { 0x5c04, 0, 0x00000000, 0x0003000f }, | |
5588 | { 0x5c08, 0, 0x00000003, 0x00000000 }, | |
5589 | { 0x5c0c, 0, 0x0000fff8, 0x00000000 }, | |
5590 | { 0x5c10, 0, 0x00000000, 0xffffffff }, | |
5591 | { 0x5c80, 0, 0x00000000, 0x0f7113f1 }, | |
5592 | { 0x5c84, 0, 0x00000000, 0x0000f333 }, | |
5593 | { 0x5c88, 0, 0x00000000, 0x00077373 }, | |
5594 | { 0x5c8c, 0, 0x00000000, 0x0007f737 }, | |
5595 | ||
5596 | { 0x6808, 0, 0x0000ff7f, 0x00000000 }, | |
5597 | { 0x680c, 0, 0xffffffff, 0x00000000 }, | |
5598 | { 0x6810, 0, 0xffffffff, 0x00000000 }, | |
5599 | { 0x6814, 0, 0xffffffff, 0x00000000 }, | |
5600 | { 0x6818, 0, 0xffffffff, 0x00000000 }, | |
5601 | { 0x681c, 0, 0xffffffff, 0x00000000 }, | |
5602 | { 0x6820, 0, 0x00ff00ff, 0x00000000 }, | |
5603 | { 0x6824, 0, 0x00ff00ff, 0x00000000 }, | |
5604 | { 0x6828, 0, 0x00ff00ff, 0x00000000 }, | |
5605 | { 0x682c, 0, 0x03ff03ff, 0x00000000 }, | |
5606 | { 0x6830, 0, 0x03ff03ff, 0x00000000 }, | |
5607 | { 0x6834, 0, 0x03ff03ff, 0x00000000 }, | |
5608 | { 0x6838, 0, 0x03ff03ff, 0x00000000 }, | |
5609 | { 0x683c, 0, 0x0000ffff, 0x00000000 }, | |
5610 | { 0x6840, 0, 0x00000ff0, 0x00000000 }, | |
5611 | { 0x6844, 0, 0x00ffff00, 0x00000000 }, | |
5612 | { 0x684c, 0, 0xffffffff, 0x00000000 }, | |
5613 | { 0x6850, 0, 0x7f7f7f7f, 0x00000000 }, | |
5614 | { 0x6854, 0, 0x7f7f7f7f, 0x00000000 }, | |
5615 | { 0x6858, 0, 0x7f7f7f7f, 0x00000000 }, | |
5616 | { 0x685c, 0, 0x7f7f7f7f, 0x00000000 }, | |
5617 | { 0x6908, 0, 0x00000000, 0x0001ff0f }, | |
5618 | { 0x690c, 0, 0x00000000, 0x0ffe00f0 }, | |
5619 | ||
5620 | { 0xffff, 0, 0x00000000, 0x00000000 }, | |
5621 | }; | |
5622 | ||
5623 | ret = 0; | |
5bae30c9 | 5624 | is_5709 = 0; |
4ce45e02 | 5625 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
5bae30c9 MC |
5626 | is_5709 = 1; |
5627 | ||
b6016b76 MC |
5628 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { |
5629 | u32 offset, rw_mask, ro_mask, save_val, val; | |
5bae30c9 MC |
5630 | u16 flags = reg_tbl[i].flags; |
5631 | ||
5632 | if (is_5709 && (flags & BNX2_FL_NOT_5709)) | |
5633 | continue; | |
b6016b76 MC |
5634 | |
5635 | offset = (u32) reg_tbl[i].offset; | |
5636 | rw_mask = reg_tbl[i].rw_mask; | |
5637 | ro_mask = reg_tbl[i].ro_mask; | |
5638 | ||
14ab9b86 | 5639 | save_val = readl(bp->regview + offset); |
b6016b76 | 5640 | |
14ab9b86 | 5641 | writel(0, bp->regview + offset); |
b6016b76 | 5642 | |
14ab9b86 | 5643 | val = readl(bp->regview + offset); |
b6016b76 MC |
5644 | if ((val & rw_mask) != 0) { |
5645 | goto reg_test_err; | |
5646 | } | |
5647 | ||
5648 | if ((val & ro_mask) != (save_val & ro_mask)) { | |
5649 | goto reg_test_err; | |
5650 | } | |
5651 | ||
14ab9b86 | 5652 | writel(0xffffffff, bp->regview + offset); |
b6016b76 | 5653 | |
14ab9b86 | 5654 | val = readl(bp->regview + offset); |
b6016b76 MC |
5655 | if ((val & rw_mask) != rw_mask) { |
5656 | goto reg_test_err; | |
5657 | } | |
5658 | ||
5659 | if ((val & ro_mask) != (save_val & ro_mask)) { | |
5660 | goto reg_test_err; | |
5661 | } | |
5662 | ||
14ab9b86 | 5663 | writel(save_val, bp->regview + offset); |
b6016b76 MC |
5664 | continue; |
5665 | ||
5666 | reg_test_err: | |
14ab9b86 | 5667 | writel(save_val, bp->regview + offset); |
b6016b76 MC |
5668 | ret = -ENODEV; |
5669 | break; | |
5670 | } | |
5671 | return ret; | |
5672 | } | |
5673 | ||
5674 | static int | |
5675 | bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size) | |
5676 | { | |
f71e1309 | 5677 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, |
b6016b76 MC |
5678 | 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; |
5679 | int i; | |
5680 | ||
5681 | for (i = 0; i < sizeof(test_pattern) / 4; i++) { | |
5682 | u32 offset; | |
5683 | ||
5684 | for (offset = 0; offset < size; offset += 4) { | |
5685 | ||
2726d6e1 | 5686 | bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]); |
b6016b76 | 5687 | |
2726d6e1 | 5688 | if (bnx2_reg_rd_ind(bp, start + offset) != |
b6016b76 MC |
5689 | test_pattern[i]) { |
5690 | return -ENODEV; | |
5691 | } | |
5692 | } | |
5693 | } | |
5694 | return 0; | |
5695 | } | |
5696 | ||
5697 | static int | |
5698 | bnx2_test_memory(struct bnx2 *bp) | |
5699 | { | |
5700 | int ret = 0; | |
5701 | int i; | |
5bae30c9 | 5702 | static struct mem_entry { |
b6016b76 MC |
5703 | u32 offset; |
5704 | u32 len; | |
5bae30c9 | 5705 | } mem_tbl_5706[] = { |
b6016b76 | 5706 | { 0x60000, 0x4000 }, |
5b0c76ad | 5707 | { 0xa0000, 0x3000 }, |
b6016b76 MC |
5708 | { 0xe0000, 0x4000 }, |
5709 | { 0x120000, 0x4000 }, | |
5710 | { 0x1a0000, 0x4000 }, | |
5711 | { 0x160000, 0x4000 }, | |
5712 | { 0xffffffff, 0 }, | |
5bae30c9 MC |
5713 | }, |
5714 | mem_tbl_5709[] = { | |
5715 | { 0x60000, 0x4000 }, | |
5716 | { 0xa0000, 0x3000 }, | |
5717 | { 0xe0000, 0x4000 }, | |
5718 | { 0x120000, 0x4000 }, | |
5719 | { 0x1a0000, 0x4000 }, | |
5720 | { 0xffffffff, 0 }, | |
b6016b76 | 5721 | }; |
5bae30c9 MC |
5722 | struct mem_entry *mem_tbl; |
5723 | ||
4ce45e02 | 5724 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
5bae30c9 MC |
5725 | mem_tbl = mem_tbl_5709; |
5726 | else | |
5727 | mem_tbl = mem_tbl_5706; | |
b6016b76 MC |
5728 | |
5729 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
5730 | if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset, | |
5731 | mem_tbl[i].len)) != 0) { | |
5732 | return ret; | |
5733 | } | |
5734 | } | |
6aa20a22 | 5735 | |
b6016b76 MC |
5736 | return ret; |
5737 | } | |
5738 | ||
bc5a0690 MC |
5739 | #define BNX2_MAC_LOOPBACK 0 |
5740 | #define BNX2_PHY_LOOPBACK 1 | |
5741 | ||
b6016b76 | 5742 | static int |
bc5a0690 | 5743 | bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) |
b6016b76 MC |
5744 | { |
5745 | unsigned int pkt_size, num_pkts, i; | |
dd2bc8e9 ED |
5746 | struct sk_buff *skb; |
5747 | u8 *data; | |
b6016b76 | 5748 | unsigned char *packet; |
bc5a0690 | 5749 | u16 rx_start_idx, rx_idx; |
b6016b76 | 5750 | dma_addr_t map; |
2bc4078e MC |
5751 | struct bnx2_tx_bd *txbd; |
5752 | struct bnx2_sw_bd *rx_buf; | |
b6016b76 MC |
5753 | struct l2_fhdr *rx_hdr; |
5754 | int ret = -ENODEV; | |
c76c0475 | 5755 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; |
35e9010b | 5756 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; |
bb4f98ab | 5757 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; |
c76c0475 MC |
5758 | |
5759 | tx_napi = bnapi; | |
b6016b76 | 5760 | |
35e9010b | 5761 | txr = &tx_napi->tx_ring; |
bb4f98ab | 5762 | rxr = &bnapi->rx_ring; |
bc5a0690 MC |
5763 | if (loopback_mode == BNX2_MAC_LOOPBACK) { |
5764 | bp->loopback = MAC_LOOPBACK; | |
5765 | bnx2_set_mac_loopback(bp); | |
5766 | } | |
5767 | else if (loopback_mode == BNX2_PHY_LOOPBACK) { | |
583c28e5 | 5768 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
489310a4 MC |
5769 | return 0; |
5770 | ||
80be4434 | 5771 | bp->loopback = PHY_LOOPBACK; |
bc5a0690 MC |
5772 | bnx2_set_phy_loopback(bp); |
5773 | } | |
5774 | else | |
5775 | return -EINVAL; | |
b6016b76 | 5776 | |
84eaa187 | 5777 | pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4); |
932f3772 | 5778 | skb = netdev_alloc_skb(bp->dev, pkt_size); |
b6cbc3b6 JL |
5779 | if (!skb) |
5780 | return -ENOMEM; | |
b6016b76 | 5781 | packet = skb_put(skb, pkt_size); |
d458cdf7 JP |
5782 | memcpy(packet, bp->dev->dev_addr, ETH_ALEN); |
5783 | memset(packet + ETH_ALEN, 0x0, 8); | |
b6016b76 MC |
5784 | for (i = 14; i < pkt_size; i++) |
5785 | packet[i] = (unsigned char) (i & 0xff); | |
5786 | ||
36227e88 SG |
5787 | map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, |
5788 | PCI_DMA_TODEVICE); | |
5789 | if (dma_mapping_error(&bp->pdev->dev, map)) { | |
3d16af86 BL |
5790 | dev_kfree_skb(skb); |
5791 | return -EIO; | |
5792 | } | |
b6016b76 | 5793 | |
e503e066 MC |
5794 | BNX2_WR(bp, BNX2_HC_COMMAND, |
5795 | bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
bf5295bb | 5796 | |
e503e066 | 5797 | BNX2_RD(bp, BNX2_HC_COMMAND); |
b6016b76 MC |
5798 | |
5799 | udelay(5); | |
35efa7c1 | 5800 | rx_start_idx = bnx2_get_hw_rx_cons(bnapi); |
b6016b76 | 5801 | |
b6016b76 MC |
5802 | num_pkts = 0; |
5803 | ||
2bc4078e | 5804 | txbd = &txr->tx_desc_ring[BNX2_TX_RING_IDX(txr->tx_prod)]; |
b6016b76 MC |
5805 | |
5806 | txbd->tx_bd_haddr_hi = (u64) map >> 32; | |
5807 | txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; | |
5808 | txbd->tx_bd_mss_nbytes = pkt_size; | |
5809 | txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; | |
5810 | ||
5811 | num_pkts++; | |
2bc4078e | 5812 | txr->tx_prod = BNX2_NEXT_TX_BD(txr->tx_prod); |
35e9010b | 5813 | txr->tx_prod_bseq += pkt_size; |
b6016b76 | 5814 | |
e503e066 MC |
5815 | BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod); |
5816 | BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); | |
b6016b76 MC |
5817 | |
5818 | udelay(100); | |
5819 | ||
e503e066 MC |
5820 | BNX2_WR(bp, BNX2_HC_COMMAND, |
5821 | bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
bf5295bb | 5822 | |
e503e066 | 5823 | BNX2_RD(bp, BNX2_HC_COMMAND); |
b6016b76 MC |
5824 | |
5825 | udelay(5); | |
5826 | ||
36227e88 | 5827 | dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE); |
745720e5 | 5828 | dev_kfree_skb(skb); |
b6016b76 | 5829 | |
35e9010b | 5830 | if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod) |
b6016b76 | 5831 | goto loopback_test_done; |
b6016b76 | 5832 | |
35efa7c1 | 5833 | rx_idx = bnx2_get_hw_rx_cons(bnapi); |
b6016b76 MC |
5834 | if (rx_idx != rx_start_idx + num_pkts) { |
5835 | goto loopback_test_done; | |
5836 | } | |
5837 | ||
bb4f98ab | 5838 | rx_buf = &rxr->rx_buf_ring[rx_start_idx]; |
dd2bc8e9 | 5839 | data = rx_buf->data; |
b6016b76 | 5840 | |
dd2bc8e9 ED |
5841 | rx_hdr = get_l2_fhdr(data); |
5842 | data = (u8 *)rx_hdr + BNX2_RX_OFFSET; | |
b6016b76 | 5843 | |
36227e88 | 5844 | dma_sync_single_for_cpu(&bp->pdev->dev, |
1a4ccc2d | 5845 | dma_unmap_addr(rx_buf, mapping), |
dd2bc8e9 | 5846 | bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); |
b6016b76 | 5847 | |
ade2bfe7 | 5848 | if (rx_hdr->l2_fhdr_status & |
b6016b76 MC |
5849 | (L2_FHDR_ERRORS_BAD_CRC | |
5850 | L2_FHDR_ERRORS_PHY_DECODE | | |
5851 | L2_FHDR_ERRORS_ALIGNMENT | | |
5852 | L2_FHDR_ERRORS_TOO_SHORT | | |
5853 | L2_FHDR_ERRORS_GIANT_FRAME)) { | |
5854 | ||
5855 | goto loopback_test_done; | |
5856 | } | |
5857 | ||
5858 | if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) { | |
5859 | goto loopback_test_done; | |
5860 | } | |
5861 | ||
5862 | for (i = 14; i < pkt_size; i++) { | |
dd2bc8e9 | 5863 | if (*(data + i) != (unsigned char) (i & 0xff)) { |
b6016b76 MC |
5864 | goto loopback_test_done; |
5865 | } | |
5866 | } | |
5867 | ||
5868 | ret = 0; | |
5869 | ||
5870 | loopback_test_done: | |
5871 | bp->loopback = 0; | |
5872 | return ret; | |
5873 | } | |
5874 | ||
bc5a0690 MC |
5875 | #define BNX2_MAC_LOOPBACK_FAILED 1 |
5876 | #define BNX2_PHY_LOOPBACK_FAILED 2 | |
5877 | #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \ | |
5878 | BNX2_PHY_LOOPBACK_FAILED) | |
5879 | ||
5880 | static int | |
5881 | bnx2_test_loopback(struct bnx2 *bp) | |
5882 | { | |
5883 | int rc = 0; | |
5884 | ||
5885 | if (!netif_running(bp->dev)) | |
5886 | return BNX2_LOOPBACK_FAILED; | |
5887 | ||
5888 | bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); | |
5889 | spin_lock_bh(&bp->phy_lock); | |
9a120bc5 | 5890 | bnx2_init_phy(bp, 1); |
bc5a0690 MC |
5891 | spin_unlock_bh(&bp->phy_lock); |
5892 | if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK)) | |
5893 | rc |= BNX2_MAC_LOOPBACK_FAILED; | |
5894 | if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK)) | |
5895 | rc |= BNX2_PHY_LOOPBACK_FAILED; | |
5896 | return rc; | |
5897 | } | |
5898 | ||
b6016b76 MC |
5899 | #define NVRAM_SIZE 0x200 |
5900 | #define CRC32_RESIDUAL 0xdebb20e3 | |
5901 | ||
5902 | static int | |
5903 | bnx2_test_nvram(struct bnx2 *bp) | |
5904 | { | |
b491edd5 | 5905 | __be32 buf[NVRAM_SIZE / 4]; |
b6016b76 MC |
5906 | u8 *data = (u8 *) buf; |
5907 | int rc = 0; | |
5908 | u32 magic, csum; | |
5909 | ||
5910 | if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0) | |
5911 | goto test_nvram_done; | |
5912 | ||
5913 | magic = be32_to_cpu(buf[0]); | |
5914 | if (magic != 0x669955aa) { | |
5915 | rc = -ENODEV; | |
5916 | goto test_nvram_done; | |
5917 | } | |
5918 | ||
5919 | if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0) | |
5920 | goto test_nvram_done; | |
5921 | ||
5922 | csum = ether_crc_le(0x100, data); | |
5923 | if (csum != CRC32_RESIDUAL) { | |
5924 | rc = -ENODEV; | |
5925 | goto test_nvram_done; | |
5926 | } | |
5927 | ||
5928 | csum = ether_crc_le(0x100, data + 0x100); | |
5929 | if (csum != CRC32_RESIDUAL) { | |
5930 | rc = -ENODEV; | |
5931 | } | |
5932 | ||
5933 | test_nvram_done: | |
5934 | return rc; | |
5935 | } | |
5936 | ||
5937 | static int | |
5938 | bnx2_test_link(struct bnx2 *bp) | |
5939 | { | |
5940 | u32 bmsr; | |
5941 | ||
9f52b564 MC |
5942 | if (!netif_running(bp->dev)) |
5943 | return -ENODEV; | |
5944 | ||
583c28e5 | 5945 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
489310a4 MC |
5946 | if (bp->link_up) |
5947 | return 0; | |
5948 | return -ENODEV; | |
5949 | } | |
c770a65c | 5950 | spin_lock_bh(&bp->phy_lock); |
27a005b8 MC |
5951 | bnx2_enable_bmsr1(bp); |
5952 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
5953 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
5954 | bnx2_disable_bmsr1(bp); | |
c770a65c | 5955 | spin_unlock_bh(&bp->phy_lock); |
6aa20a22 | 5956 | |
b6016b76 MC |
5957 | if (bmsr & BMSR_LSTATUS) { |
5958 | return 0; | |
5959 | } | |
5960 | return -ENODEV; | |
5961 | } | |
5962 | ||
5963 | static int | |
5964 | bnx2_test_intr(struct bnx2 *bp) | |
5965 | { | |
5966 | int i; | |
b6016b76 MC |
5967 | u16 status_idx; |
5968 | ||
5969 | if (!netif_running(bp->dev)) | |
5970 | return -ENODEV; | |
5971 | ||
e503e066 | 5972 | status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; |
b6016b76 MC |
5973 | |
5974 | /* This register is not touched during run-time. */ | |
e503e066 MC |
5975 | BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); |
5976 | BNX2_RD(bp, BNX2_HC_COMMAND); | |
b6016b76 MC |
5977 | |
5978 | for (i = 0; i < 10; i++) { | |
e503e066 | 5979 | if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != |
b6016b76 MC |
5980 | status_idx) { |
5981 | ||
5982 | break; | |
5983 | } | |
5984 | ||
5985 | msleep_interruptible(10); | |
5986 | } | |
5987 | if (i < 10) | |
5988 | return 0; | |
5989 | ||
5990 | return -ENODEV; | |
5991 | } | |
5992 | ||
38ea3686 | 5993 | /* Determining link for parallel detection. */ |
b2fadeae MC |
5994 | static int |
5995 | bnx2_5706_serdes_has_link(struct bnx2 *bp) | |
5996 | { | |
5997 | u32 mode_ctl, an_dbg, exp; | |
5998 | ||
38ea3686 MC |
5999 | if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL) |
6000 | return 0; | |
6001 | ||
b2fadeae MC |
6002 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL); |
6003 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl); | |
6004 | ||
6005 | if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET)) | |
6006 | return 0; | |
6007 | ||
6008 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); | |
6009 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | |
6010 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | |
6011 | ||
f3014c0c | 6012 | if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID)) |
b2fadeae MC |
6013 | return 0; |
6014 | ||
6015 | bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1); | |
6016 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp); | |
6017 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp); | |
6018 | ||
6019 | if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */ | |
6020 | return 0; | |
6021 | ||
6022 | return 1; | |
6023 | } | |
6024 | ||
b6016b76 | 6025 | static void |
48b01e2d | 6026 | bnx2_5706_serdes_timer(struct bnx2 *bp) |
b6016b76 | 6027 | { |
b2fadeae MC |
6028 | int check_link = 1; |
6029 | ||
48b01e2d | 6030 | spin_lock(&bp->phy_lock); |
b2fadeae | 6031 | if (bp->serdes_an_pending) { |
48b01e2d | 6032 | bp->serdes_an_pending--; |
b2fadeae MC |
6033 | check_link = 0; |
6034 | } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { | |
48b01e2d | 6035 | u32 bmcr; |
b6016b76 | 6036 | |
ac392abc | 6037 | bp->current_interval = BNX2_TIMER_INTERVAL; |
cd339a0e | 6038 | |
ca58c3af | 6039 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 | 6040 | |
48b01e2d | 6041 | if (bmcr & BMCR_ANENABLE) { |
b2fadeae | 6042 | if (bnx2_5706_serdes_has_link(bp)) { |
48b01e2d MC |
6043 | bmcr &= ~BMCR_ANENABLE; |
6044 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
ca58c3af | 6045 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); |
583c28e5 | 6046 | bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT; |
48b01e2d | 6047 | } |
b6016b76 | 6048 | } |
48b01e2d MC |
6049 | } |
6050 | else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && | |
583c28e5 | 6051 | (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) { |
48b01e2d | 6052 | u32 phy2; |
b6016b76 | 6053 | |
48b01e2d MC |
6054 | bnx2_write_phy(bp, 0x17, 0x0f01); |
6055 | bnx2_read_phy(bp, 0x15, &phy2); | |
6056 | if (phy2 & 0x20) { | |
6057 | u32 bmcr; | |
cd339a0e | 6058 | |
ca58c3af | 6059 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
48b01e2d | 6060 | bmcr |= BMCR_ANENABLE; |
ca58c3af | 6061 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); |
b6016b76 | 6062 | |
583c28e5 | 6063 | bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; |
48b01e2d MC |
6064 | } |
6065 | } else | |
ac392abc | 6066 | bp->current_interval = BNX2_TIMER_INTERVAL; |
b6016b76 | 6067 | |
a2724e25 | 6068 | if (check_link) { |
b2fadeae MC |
6069 | u32 val; |
6070 | ||
6071 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); | |
6072 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); | |
6073 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); | |
6074 | ||
a2724e25 MC |
6075 | if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) { |
6076 | if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) { | |
6077 | bnx2_5706s_force_link_dn(bp, 1); | |
6078 | bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN; | |
6079 | } else | |
6080 | bnx2_set_link(bp); | |
6081 | } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC)) | |
6082 | bnx2_set_link(bp); | |
b2fadeae | 6083 | } |
48b01e2d MC |
6084 | spin_unlock(&bp->phy_lock); |
6085 | } | |
b6016b76 | 6086 | |
f8dd064e MC |
6087 | static void |
6088 | bnx2_5708_serdes_timer(struct bnx2 *bp) | |
6089 | { | |
583c28e5 | 6090 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
6091 | return; |
6092 | ||
583c28e5 | 6093 | if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) { |
f8dd064e MC |
6094 | bp->serdes_an_pending = 0; |
6095 | return; | |
6096 | } | |
b6016b76 | 6097 | |
f8dd064e MC |
6098 | spin_lock(&bp->phy_lock); |
6099 | if (bp->serdes_an_pending) | |
6100 | bp->serdes_an_pending--; | |
6101 | else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { | |
6102 | u32 bmcr; | |
b6016b76 | 6103 | |
ca58c3af | 6104 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
f8dd064e | 6105 | if (bmcr & BMCR_ANENABLE) { |
605a9e20 | 6106 | bnx2_enable_forced_2g5(bp); |
40105c0b | 6107 | bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT; |
f8dd064e | 6108 | } else { |
605a9e20 | 6109 | bnx2_disable_forced_2g5(bp); |
f8dd064e | 6110 | bp->serdes_an_pending = 2; |
ac392abc | 6111 | bp->current_interval = BNX2_TIMER_INTERVAL; |
b6016b76 | 6112 | } |
b6016b76 | 6113 | |
f8dd064e | 6114 | } else |
ac392abc | 6115 | bp->current_interval = BNX2_TIMER_INTERVAL; |
b6016b76 | 6116 | |
f8dd064e MC |
6117 | spin_unlock(&bp->phy_lock); |
6118 | } | |
6119 | ||
48b01e2d MC |
6120 | static void |
6121 | bnx2_timer(unsigned long data) | |
6122 | { | |
6123 | struct bnx2 *bp = (struct bnx2 *) data; | |
b6016b76 | 6124 | |
48b01e2d MC |
6125 | if (!netif_running(bp->dev)) |
6126 | return; | |
b6016b76 | 6127 | |
48b01e2d MC |
6128 | if (atomic_read(&bp->intr_sem) != 0) |
6129 | goto bnx2_restart_timer; | |
b6016b76 | 6130 | |
efba0180 MC |
6131 | if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) == |
6132 | BNX2_FLAG_USING_MSI) | |
6133 | bnx2_chk_missed_msi(bp); | |
6134 | ||
df149d70 | 6135 | bnx2_send_heart_beat(bp); |
b6016b76 | 6136 | |
2726d6e1 MC |
6137 | bp->stats_blk->stat_FwRxDrop = |
6138 | bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT); | |
b6016b76 | 6139 | |
02537b06 | 6140 | /* workaround occasional corrupted counters */ |
61d9e3fa | 6141 | if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks) |
e503e066 MC |
6142 | BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | |
6143 | BNX2_HC_COMMAND_STATS_NOW); | |
02537b06 | 6144 | |
583c28e5 | 6145 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
4ce45e02 | 6146 | if (BNX2_CHIP(bp) == BNX2_CHIP_5706) |
f8dd064e | 6147 | bnx2_5706_serdes_timer(bp); |
27a005b8 | 6148 | else |
f8dd064e | 6149 | bnx2_5708_serdes_timer(bp); |
b6016b76 MC |
6150 | } |
6151 | ||
6152 | bnx2_restart_timer: | |
cd339a0e | 6153 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
b6016b76 MC |
6154 | } |
6155 | ||
8e6a72c4 MC |
6156 | static int |
6157 | bnx2_request_irq(struct bnx2 *bp) | |
6158 | { | |
6d866ffc | 6159 | unsigned long flags; |
b4b36042 MC |
6160 | struct bnx2_irq *irq; |
6161 | int rc = 0, i; | |
8e6a72c4 | 6162 | |
f86e82fb | 6163 | if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX) |
6d866ffc MC |
6164 | flags = 0; |
6165 | else | |
6166 | flags = IRQF_SHARED; | |
b4b36042 MC |
6167 | |
6168 | for (i = 0; i < bp->irq_nvecs; i++) { | |
6169 | irq = &bp->irq_tbl[i]; | |
c76c0475 | 6170 | rc = request_irq(irq->vector, irq->handler, flags, irq->name, |
f0ea2e63 | 6171 | &bp->bnx2_napi[i]); |
b4b36042 MC |
6172 | if (rc) |
6173 | break; | |
6174 | irq->requested = 1; | |
6175 | } | |
8e6a72c4 MC |
6176 | return rc; |
6177 | } | |
6178 | ||
6179 | static void | |
a29ba9d2 | 6180 | __bnx2_free_irq(struct bnx2 *bp) |
8e6a72c4 | 6181 | { |
b4b36042 MC |
6182 | struct bnx2_irq *irq; |
6183 | int i; | |
8e6a72c4 | 6184 | |
b4b36042 MC |
6185 | for (i = 0; i < bp->irq_nvecs; i++) { |
6186 | irq = &bp->irq_tbl[i]; | |
6187 | if (irq->requested) | |
f0ea2e63 | 6188 | free_irq(irq->vector, &bp->bnx2_napi[i]); |
b4b36042 | 6189 | irq->requested = 0; |
6d866ffc | 6190 | } |
a29ba9d2 MC |
6191 | } |
6192 | ||
6193 | static void | |
6194 | bnx2_free_irq(struct bnx2 *bp) | |
6195 | { | |
6196 | ||
6197 | __bnx2_free_irq(bp); | |
f86e82fb | 6198 | if (bp->flags & BNX2_FLAG_USING_MSI) |
b4b36042 | 6199 | pci_disable_msi(bp->pdev); |
f86e82fb | 6200 | else if (bp->flags & BNX2_FLAG_USING_MSIX) |
b4b36042 MC |
6201 | pci_disable_msix(bp->pdev); |
6202 | ||
f86e82fb | 6203 | bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI); |
b4b36042 MC |
6204 | } |
6205 | ||
6206 | static void | |
5e9ad9e1 | 6207 | bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) |
b4b36042 | 6208 | { |
f2a2dfeb | 6209 | int i, total_vecs; |
57851d84 | 6210 | struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC]; |
4e1d0de9 MC |
6211 | struct net_device *dev = bp->dev; |
6212 | const int len = sizeof(bp->irq_tbl[0].name); | |
57851d84 | 6213 | |
b4b36042 | 6214 | bnx2_setup_msix_tbl(bp); |
e503e066 MC |
6215 | BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); |
6216 | BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE); | |
6217 | BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE); | |
57851d84 | 6218 | |
e2eb8e38 BL |
6219 | /* Need to flush the previous three writes to ensure MSI-X |
6220 | * is setup properly */ | |
e503e066 | 6221 | BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL); |
e2eb8e38 | 6222 | |
57851d84 MC |
6223 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { |
6224 | msix_ent[i].entry = i; | |
6225 | msix_ent[i].vector = 0; | |
6226 | } | |
6227 | ||
379b39a2 MC |
6228 | total_vecs = msix_vecs; |
6229 | #ifdef BCM_CNIC | |
6230 | total_vecs++; | |
6231 | #endif | |
f2a2dfeb AG |
6232 | total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, |
6233 | BNX2_MIN_MSIX_VEC, total_vecs); | |
6234 | if (total_vecs < 0) | |
57851d84 MC |
6235 | return; |
6236 | ||
379b39a2 MC |
6237 | msix_vecs = total_vecs; |
6238 | #ifdef BCM_CNIC | |
6239 | msix_vecs--; | |
6240 | #endif | |
5e9ad9e1 | 6241 | bp->irq_nvecs = msix_vecs; |
f86e82fb | 6242 | bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; |
379b39a2 | 6243 | for (i = 0; i < total_vecs; i++) { |
57851d84 | 6244 | bp->irq_tbl[i].vector = msix_ent[i].vector; |
69010313 MC |
6245 | snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); |
6246 | bp->irq_tbl[i].handler = bnx2_msi_1shot; | |
6247 | } | |
6d866ffc MC |
6248 | } |
6249 | ||
657d92fe | 6250 | static int |
6d866ffc MC |
6251 | bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) |
6252 | { | |
0a742128 | 6253 | int cpus = netif_get_num_default_rss_queues(); |
b033281f MC |
6254 | int msix_vecs; |
6255 | ||
6256 | if (!bp->num_req_rx_rings) | |
6257 | msix_vecs = max(cpus + 1, bp->num_req_tx_rings); | |
6258 | else if (!bp->num_req_tx_rings) | |
6259 | msix_vecs = max(cpus, bp->num_req_rx_rings); | |
6260 | else | |
6261 | msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings); | |
6262 | ||
6263 | msix_vecs = min(msix_vecs, RX_MAX_RINGS); | |
5e9ad9e1 | 6264 | |
6d866ffc MC |
6265 | bp->irq_tbl[0].handler = bnx2_interrupt; |
6266 | strcpy(bp->irq_tbl[0].name, bp->dev->name); | |
b4b36042 MC |
6267 | bp->irq_nvecs = 1; |
6268 | bp->irq_tbl[0].vector = bp->pdev->irq; | |
6269 | ||
3d5f3a7b | 6270 | if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi) |
5e9ad9e1 | 6271 | bnx2_enable_msix(bp, msix_vecs); |
6d866ffc | 6272 | |
f86e82fb DM |
6273 | if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi && |
6274 | !(bp->flags & BNX2_FLAG_USING_MSIX)) { | |
6d866ffc | 6275 | if (pci_enable_msi(bp->pdev) == 0) { |
f86e82fb | 6276 | bp->flags |= BNX2_FLAG_USING_MSI; |
4ce45e02 | 6277 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
f86e82fb | 6278 | bp->flags |= BNX2_FLAG_ONE_SHOT_MSI; |
6d866ffc MC |
6279 | bp->irq_tbl[0].handler = bnx2_msi_1shot; |
6280 | } else | |
6281 | bp->irq_tbl[0].handler = bnx2_msi; | |
b4b36042 MC |
6282 | |
6283 | bp->irq_tbl[0].vector = bp->pdev->irq; | |
6d866ffc MC |
6284 | } |
6285 | } | |
706bf240 | 6286 | |
b033281f MC |
6287 | if (!bp->num_req_tx_rings) |
6288 | bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs); | |
6289 | else | |
6290 | bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings); | |
6291 | ||
6292 | if (!bp->num_req_rx_rings) | |
6293 | bp->num_rx_rings = bp->irq_nvecs; | |
6294 | else | |
6295 | bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings); | |
6296 | ||
657d92fe | 6297 | netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings); |
706bf240 | 6298 | |
657d92fe | 6299 | return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings); |
8e6a72c4 MC |
6300 | } |
6301 | ||
b6016b76 MC |
6302 | /* Called with rtnl_lock */ |
6303 | static int | |
6304 | bnx2_open(struct net_device *dev) | |
6305 | { | |
972ec0d4 | 6306 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6307 | int rc; |
6308 | ||
7880b72e | 6309 | rc = bnx2_request_firmware(bp); |
6310 | if (rc < 0) | |
6311 | goto out; | |
6312 | ||
1b2f922f MC |
6313 | netif_carrier_off(dev); |
6314 | ||
b6016b76 MC |
6315 | bnx2_disable_int(bp); |
6316 | ||
657d92fe BH |
6317 | rc = bnx2_setup_int_mode(bp, disable_msi); |
6318 | if (rc) | |
6319 | goto open_err; | |
4327ba43 | 6320 | bnx2_init_napi(bp); |
35e9010b | 6321 | bnx2_napi_enable(bp); |
b6016b76 | 6322 | rc = bnx2_alloc_mem(bp); |
2739a8bb MC |
6323 | if (rc) |
6324 | goto open_err; | |
b6016b76 | 6325 | |
8e6a72c4 | 6326 | rc = bnx2_request_irq(bp); |
2739a8bb MC |
6327 | if (rc) |
6328 | goto open_err; | |
b6016b76 | 6329 | |
9a120bc5 | 6330 | rc = bnx2_init_nic(bp, 1); |
2739a8bb MC |
6331 | if (rc) |
6332 | goto open_err; | |
6aa20a22 | 6333 | |
cd339a0e | 6334 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
b6016b76 MC |
6335 | |
6336 | atomic_set(&bp->intr_sem, 0); | |
6337 | ||
354fcd77 MC |
6338 | memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block)); |
6339 | ||
b6016b76 MC |
6340 | bnx2_enable_int(bp); |
6341 | ||
f86e82fb | 6342 | if (bp->flags & BNX2_FLAG_USING_MSI) { |
b6016b76 MC |
6343 | /* Test MSI to make sure it is working |
6344 | * If MSI test fails, go back to INTx mode | |
6345 | */ | |
6346 | if (bnx2_test_intr(bp) != 0) { | |
3a9c6a49 | 6347 | netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n"); |
b6016b76 MC |
6348 | |
6349 | bnx2_disable_int(bp); | |
8e6a72c4 | 6350 | bnx2_free_irq(bp); |
b6016b76 | 6351 | |
6d866ffc MC |
6352 | bnx2_setup_int_mode(bp, 1); |
6353 | ||
9a120bc5 | 6354 | rc = bnx2_init_nic(bp, 0); |
b6016b76 | 6355 | |
8e6a72c4 MC |
6356 | if (!rc) |
6357 | rc = bnx2_request_irq(bp); | |
6358 | ||
b6016b76 | 6359 | if (rc) { |
b6016b76 | 6360 | del_timer_sync(&bp->timer); |
2739a8bb | 6361 | goto open_err; |
b6016b76 MC |
6362 | } |
6363 | bnx2_enable_int(bp); | |
6364 | } | |
6365 | } | |
f86e82fb | 6366 | if (bp->flags & BNX2_FLAG_USING_MSI) |
3a9c6a49 | 6367 | netdev_info(dev, "using MSI\n"); |
f86e82fb | 6368 | else if (bp->flags & BNX2_FLAG_USING_MSIX) |
3a9c6a49 | 6369 | netdev_info(dev, "using MSIX\n"); |
b6016b76 | 6370 | |
706bf240 | 6371 | netif_tx_start_all_queues(dev); |
7880b72e | 6372 | out: |
6373 | return rc; | |
2739a8bb MC |
6374 | |
6375 | open_err: | |
6376 | bnx2_napi_disable(bp); | |
6377 | bnx2_free_skbs(bp); | |
6378 | bnx2_free_irq(bp); | |
6379 | bnx2_free_mem(bp); | |
f048fa9c | 6380 | bnx2_del_napi(bp); |
7880b72e | 6381 | bnx2_release_firmware(bp); |
6382 | goto out; | |
b6016b76 MC |
6383 | } |
6384 | ||
6385 | static void | |
c4028958 | 6386 | bnx2_reset_task(struct work_struct *work) |
b6016b76 | 6387 | { |
c4028958 | 6388 | struct bnx2 *bp = container_of(work, struct bnx2, reset_task); |
cd634019 | 6389 | int rc; |
efdfad32 | 6390 | u16 pcicmd; |
b6016b76 | 6391 | |
51bf6bb4 MC |
6392 | rtnl_lock(); |
6393 | if (!netif_running(bp->dev)) { | |
6394 | rtnl_unlock(); | |
afdc08b9 | 6395 | return; |
51bf6bb4 | 6396 | } |
afdc08b9 | 6397 | |
212f9934 | 6398 | bnx2_netif_stop(bp, true); |
b6016b76 | 6399 | |
efdfad32 MC |
6400 | pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd); |
6401 | if (!(pcicmd & PCI_COMMAND_MEMORY)) { | |
6402 | /* in case PCI block has reset */ | |
6403 | pci_restore_state(bp->pdev); | |
6404 | pci_save_state(bp->pdev); | |
6405 | } | |
cd634019 MC |
6406 | rc = bnx2_init_nic(bp, 1); |
6407 | if (rc) { | |
6408 | netdev_err(bp->dev, "failed to reset NIC, closing\n"); | |
6409 | bnx2_napi_enable(bp); | |
6410 | dev_close(bp->dev); | |
6411 | rtnl_unlock(); | |
6412 | return; | |
6413 | } | |
b6016b76 MC |
6414 | |
6415 | atomic_set(&bp->intr_sem, 1); | |
212f9934 | 6416 | bnx2_netif_start(bp, true); |
51bf6bb4 | 6417 | rtnl_unlock(); |
b6016b76 MC |
6418 | } |
6419 | ||
555069da MC |
6420 | #define BNX2_FTQ_ENTRY(ftq) { __stringify(ftq##FTQ_CTL), BNX2_##ftq##FTQ_CTL } |
6421 | ||
6422 | static void | |
6423 | bnx2_dump_ftq(struct bnx2 *bp) | |
6424 | { | |
6425 | int i; | |
6426 | u32 reg, bdidx, cid, valid; | |
6427 | struct net_device *dev = bp->dev; | |
6428 | static const struct ftq_reg { | |
6429 | char *name; | |
6430 | u32 off; | |
6431 | } ftq_arr[] = { | |
6432 | BNX2_FTQ_ENTRY(RV2P_P), | |
6433 | BNX2_FTQ_ENTRY(RV2P_T), | |
6434 | BNX2_FTQ_ENTRY(RV2P_M), | |
6435 | BNX2_FTQ_ENTRY(TBDR_), | |
6436 | BNX2_FTQ_ENTRY(TDMA_), | |
6437 | BNX2_FTQ_ENTRY(TXP_), | |
6438 | BNX2_FTQ_ENTRY(TXP_), | |
6439 | BNX2_FTQ_ENTRY(TPAT_), | |
6440 | BNX2_FTQ_ENTRY(RXP_C), | |
6441 | BNX2_FTQ_ENTRY(RXP_), | |
6442 | BNX2_FTQ_ENTRY(COM_COMXQ_), | |
6443 | BNX2_FTQ_ENTRY(COM_COMTQ_), | |
6444 | BNX2_FTQ_ENTRY(COM_COMQ_), | |
6445 | BNX2_FTQ_ENTRY(CP_CPQ_), | |
6446 | }; | |
6447 | ||
6448 | netdev_err(dev, "<--- start FTQ dump --->\n"); | |
6449 | for (i = 0; i < ARRAY_SIZE(ftq_arr); i++) | |
6450 | netdev_err(dev, "%s %08x\n", ftq_arr[i].name, | |
6451 | bnx2_reg_rd_ind(bp, ftq_arr[i].off)); | |
6452 | ||
6453 | netdev_err(dev, "CPU states:\n"); | |
6454 | for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000) | |
6455 | netdev_err(dev, "%06x mode %x state %x evt_mask %x pc %x pc %x instr %x\n", | |
6456 | reg, bnx2_reg_rd_ind(bp, reg), | |
6457 | bnx2_reg_rd_ind(bp, reg + 4), | |
6458 | bnx2_reg_rd_ind(bp, reg + 8), | |
6459 | bnx2_reg_rd_ind(bp, reg + 0x1c), | |
6460 | bnx2_reg_rd_ind(bp, reg + 0x1c), | |
6461 | bnx2_reg_rd_ind(bp, reg + 0x20)); | |
6462 | ||
6463 | netdev_err(dev, "<--- end FTQ dump --->\n"); | |
6464 | netdev_err(dev, "<--- start TBDC dump --->\n"); | |
6465 | netdev_err(dev, "TBDC free cnt: %ld\n", | |
e503e066 | 6466 | BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT); |
555069da MC |
6467 | netdev_err(dev, "LINE CID BIDX CMD VALIDS\n"); |
6468 | for (i = 0; i < 0x20; i++) { | |
6469 | int j = 0; | |
6470 | ||
e503e066 MC |
6471 | BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i); |
6472 | BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE, | |
6473 | BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ); | |
6474 | BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB); | |
6475 | while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) & | |
555069da MC |
6476 | BNX2_TBDC_COMMAND_CMD_REG_ARB) && j < 100) |
6477 | j++; | |
6478 | ||
e503e066 MC |
6479 | cid = BNX2_RD(bp, BNX2_TBDC_CID); |
6480 | bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX); | |
6481 | valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE); | |
555069da MC |
6482 | netdev_err(dev, "%02x %06x %04lx %02x [%x]\n", |
6483 | i, cid, bdidx & BNX2_TBDC_BDIDX_BDIDX, | |
6484 | bdidx >> 24, (valid >> 8) & 0x0ff); | |
6485 | } | |
6486 | netdev_err(dev, "<--- end TBDC dump --->\n"); | |
6487 | } | |
6488 | ||
20175c57 MC |
6489 | static void |
6490 | bnx2_dump_state(struct bnx2 *bp) | |
6491 | { | |
6492 | struct net_device *dev = bp->dev; | |
ecdbf6e0 | 6493 | u32 val1, val2; |
5804a8fb MC |
6494 | |
6495 | pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1); | |
6496 | netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n", | |
6497 | atomic_read(&bp->intr_sem), val1); | |
6498 | pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1); | |
6499 | pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2); | |
6500 | netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2); | |
b98eba52 | 6501 | netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n", |
e503e066 MC |
6502 | BNX2_RD(bp, BNX2_EMAC_TX_STATUS), |
6503 | BNX2_RD(bp, BNX2_EMAC_RX_STATUS)); | |
b98eba52 | 6504 | netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n", |
e503e066 | 6505 | BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL)); |
3a9c6a49 | 6506 | netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n", |
e503e066 | 6507 | BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS)); |
20175c57 | 6508 | if (bp->flags & BNX2_FLAG_USING_MSIX) |
3a9c6a49 | 6509 | netdev_err(dev, "DEBUG: PBA[%08x]\n", |
e503e066 | 6510 | BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE)); |
20175c57 MC |
6511 | } |
6512 | ||
b6016b76 MC |
6513 | static void |
6514 | bnx2_tx_timeout(struct net_device *dev) | |
6515 | { | |
972ec0d4 | 6516 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6517 | |
555069da | 6518 | bnx2_dump_ftq(bp); |
20175c57 | 6519 | bnx2_dump_state(bp); |
ecdbf6e0 | 6520 | bnx2_dump_mcp_state(bp); |
20175c57 | 6521 | |
b6016b76 MC |
6522 | /* This allows the netif to be shutdown gracefully before resetting */ |
6523 | schedule_work(&bp->reset_task); | |
6524 | } | |
6525 | ||
932ff279 | 6526 | /* Called with netif_tx_lock. |
2f8af120 MC |
6527 | * bnx2_tx_int() runs without netif_tx_lock unless it needs to call |
6528 | * netif_wake_queue(). | |
b6016b76 | 6529 | */ |
61357325 | 6530 | static netdev_tx_t |
b6016b76 MC |
6531 | bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) |
6532 | { | |
972ec0d4 | 6533 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6534 | dma_addr_t mapping; |
2bc4078e MC |
6535 | struct bnx2_tx_bd *txbd; |
6536 | struct bnx2_sw_tx_bd *tx_buf; | |
b6016b76 MC |
6537 | u32 len, vlan_tag_flags, last_frag, mss; |
6538 | u16 prod, ring_prod; | |
6539 | int i; | |
706bf240 BL |
6540 | struct bnx2_napi *bnapi; |
6541 | struct bnx2_tx_ring_info *txr; | |
6542 | struct netdev_queue *txq; | |
6543 | ||
6544 | /* Determine which tx ring we will be placed on */ | |
6545 | i = skb_get_queue_mapping(skb); | |
6546 | bnapi = &bp->bnx2_napi[i]; | |
6547 | txr = &bnapi->tx_ring; | |
6548 | txq = netdev_get_tx_queue(dev, i); | |
b6016b76 | 6549 | |
35e9010b | 6550 | if (unlikely(bnx2_tx_avail(bp, txr) < |
a550c99b | 6551 | (skb_shinfo(skb)->nr_frags + 1))) { |
706bf240 | 6552 | netif_tx_stop_queue(txq); |
3a9c6a49 | 6553 | netdev_err(dev, "BUG! Tx ring full when queue awake!\n"); |
b6016b76 MC |
6554 | |
6555 | return NETDEV_TX_BUSY; | |
6556 | } | |
6557 | len = skb_headlen(skb); | |
35e9010b | 6558 | prod = txr->tx_prod; |
2bc4078e | 6559 | ring_prod = BNX2_TX_RING_IDX(prod); |
b6016b76 MC |
6560 | |
6561 | vlan_tag_flags = 0; | |
84fa7933 | 6562 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
b6016b76 MC |
6563 | vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; |
6564 | } | |
6565 | ||
eab6d18d | 6566 | if (vlan_tx_tag_present(skb)) { |
b6016b76 MC |
6567 | vlan_tag_flags |= |
6568 | (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); | |
6569 | } | |
7d0fd211 | 6570 | |
fde82055 | 6571 | if ((mss = skb_shinfo(skb)->gso_size)) { |
a1efb4b6 | 6572 | u32 tcp_opt_len; |
eddc9ec5 | 6573 | struct iphdr *iph; |
b6016b76 | 6574 | |
b6016b76 MC |
6575 | vlan_tag_flags |= TX_BD_FLAGS_SW_LSO; |
6576 | ||
4666f87a MC |
6577 | tcp_opt_len = tcp_optlen(skb); |
6578 | ||
6579 | if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { | |
6580 | u32 tcp_off = skb_transport_offset(skb) - | |
6581 | sizeof(struct ipv6hdr) - ETH_HLEN; | |
ab6a5bb6 | 6582 | |
4666f87a MC |
6583 | vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) | |
6584 | TX_BD_FLAGS_SW_FLAGS; | |
6585 | if (likely(tcp_off == 0)) | |
6586 | vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK; | |
6587 | else { | |
6588 | tcp_off >>= 3; | |
6589 | vlan_tag_flags |= ((tcp_off & 0x3) << | |
6590 | TX_BD_FLAGS_TCP6_OFF0_SHL) | | |
6591 | ((tcp_off & 0x10) << | |
6592 | TX_BD_FLAGS_TCP6_OFF4_SHL); | |
6593 | mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL; | |
6594 | } | |
6595 | } else { | |
4666f87a | 6596 | iph = ip_hdr(skb); |
4666f87a MC |
6597 | if (tcp_opt_len || (iph->ihl > 5)) { |
6598 | vlan_tag_flags |= ((iph->ihl - 5) + | |
6599 | (tcp_opt_len >> 2)) << 8; | |
6600 | } | |
b6016b76 | 6601 | } |
4666f87a | 6602 | } else |
b6016b76 | 6603 | mss = 0; |
b6016b76 | 6604 | |
36227e88 SG |
6605 | mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE); |
6606 | if (dma_mapping_error(&bp->pdev->dev, mapping)) { | |
3d16af86 BL |
6607 | dev_kfree_skb(skb); |
6608 | return NETDEV_TX_OK; | |
6609 | } | |
6610 | ||
35e9010b | 6611 | tx_buf = &txr->tx_buf_ring[ring_prod]; |
b6016b76 | 6612 | tx_buf->skb = skb; |
1a4ccc2d | 6613 | dma_unmap_addr_set(tx_buf, mapping, mapping); |
b6016b76 | 6614 | |
35e9010b | 6615 | txbd = &txr->tx_desc_ring[ring_prod]; |
b6016b76 MC |
6616 | |
6617 | txbd->tx_bd_haddr_hi = (u64) mapping >> 32; | |
6618 | txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
6619 | txbd->tx_bd_mss_nbytes = len | (mss << 16); | |
6620 | txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START; | |
6621 | ||
6622 | last_frag = skb_shinfo(skb)->nr_frags; | |
d62fda08 ED |
6623 | tx_buf->nr_frags = last_frag; |
6624 | tx_buf->is_gso = skb_is_gso(skb); | |
b6016b76 MC |
6625 | |
6626 | for (i = 0; i < last_frag; i++) { | |
9e903e08 | 6627 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
b6016b76 | 6628 | |
2bc4078e MC |
6629 | prod = BNX2_NEXT_TX_BD(prod); |
6630 | ring_prod = BNX2_TX_RING_IDX(prod); | |
35e9010b | 6631 | txbd = &txr->tx_desc_ring[ring_prod]; |
b6016b76 | 6632 | |
9e903e08 | 6633 | len = skb_frag_size(frag); |
b7b6a688 | 6634 | mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len, |
5d6bcdfe | 6635 | DMA_TO_DEVICE); |
36227e88 | 6636 | if (dma_mapping_error(&bp->pdev->dev, mapping)) |
e95524a7 | 6637 | goto dma_error; |
1a4ccc2d | 6638 | dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping, |
e95524a7 | 6639 | mapping); |
b6016b76 MC |
6640 | |
6641 | txbd->tx_bd_haddr_hi = (u64) mapping >> 32; | |
6642 | txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
6643 | txbd->tx_bd_mss_nbytes = len | (mss << 16); | |
6644 | txbd->tx_bd_vlan_tag_flags = vlan_tag_flags; | |
6645 | ||
6646 | } | |
6647 | txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; | |
6648 | ||
94bf91ba VZ |
6649 | /* Sync BD data before updating TX mailbox */ |
6650 | wmb(); | |
6651 | ||
e9831909 ED |
6652 | netdev_tx_sent_queue(txq, skb->len); |
6653 | ||
2bc4078e | 6654 | prod = BNX2_NEXT_TX_BD(prod); |
35e9010b | 6655 | txr->tx_prod_bseq += skb->len; |
b6016b76 | 6656 | |
e503e066 MC |
6657 | BNX2_WR16(bp, txr->tx_bidx_addr, prod); |
6658 | BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); | |
b6016b76 MC |
6659 | |
6660 | mmiowb(); | |
6661 | ||
35e9010b | 6662 | txr->tx_prod = prod; |
b6016b76 | 6663 | |
35e9010b | 6664 | if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) { |
706bf240 | 6665 | netif_tx_stop_queue(txq); |
11848b96 MC |
6666 | |
6667 | /* netif_tx_stop_queue() must be done before checking | |
6668 | * tx index in bnx2_tx_avail() below, because in | |
6669 | * bnx2_tx_int(), we update tx index before checking for | |
6670 | * netif_tx_queue_stopped(). | |
6671 | */ | |
6672 | smp_mb(); | |
35e9010b | 6673 | if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh) |
706bf240 | 6674 | netif_tx_wake_queue(txq); |
b6016b76 MC |
6675 | } |
6676 | ||
e95524a7 AD |
6677 | return NETDEV_TX_OK; |
6678 | dma_error: | |
6679 | /* save value of frag that failed */ | |
6680 | last_frag = i; | |
6681 | ||
6682 | /* start back at beginning and unmap skb */ | |
6683 | prod = txr->tx_prod; | |
2bc4078e | 6684 | ring_prod = BNX2_TX_RING_IDX(prod); |
e95524a7 AD |
6685 | tx_buf = &txr->tx_buf_ring[ring_prod]; |
6686 | tx_buf->skb = NULL; | |
36227e88 | 6687 | dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), |
e95524a7 AD |
6688 | skb_headlen(skb), PCI_DMA_TODEVICE); |
6689 | ||
6690 | /* unmap remaining mapped pages */ | |
6691 | for (i = 0; i < last_frag; i++) { | |
2bc4078e MC |
6692 | prod = BNX2_NEXT_TX_BD(prod); |
6693 | ring_prod = BNX2_TX_RING_IDX(prod); | |
e95524a7 | 6694 | tx_buf = &txr->tx_buf_ring[ring_prod]; |
36227e88 | 6695 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), |
9e903e08 | 6696 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
e95524a7 AD |
6697 | PCI_DMA_TODEVICE); |
6698 | } | |
6699 | ||
6700 | dev_kfree_skb(skb); | |
b6016b76 MC |
6701 | return NETDEV_TX_OK; |
6702 | } | |
6703 | ||
6704 | /* Called with rtnl_lock */ | |
6705 | static int | |
6706 | bnx2_close(struct net_device *dev) | |
6707 | { | |
972ec0d4 | 6708 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6709 | |
bea3348e | 6710 | bnx2_disable_int_sync(bp); |
35efa7c1 | 6711 | bnx2_napi_disable(bp); |
d2e553bc | 6712 | netif_tx_disable(dev); |
b6016b76 | 6713 | del_timer_sync(&bp->timer); |
74bf4ba3 | 6714 | bnx2_shutdown_chip(bp); |
8e6a72c4 | 6715 | bnx2_free_irq(bp); |
b6016b76 MC |
6716 | bnx2_free_skbs(bp); |
6717 | bnx2_free_mem(bp); | |
f048fa9c | 6718 | bnx2_del_napi(bp); |
b6016b76 MC |
6719 | bp->link_up = 0; |
6720 | netif_carrier_off(bp->dev); | |
b6016b76 MC |
6721 | return 0; |
6722 | } | |
6723 | ||
354fcd77 MC |
6724 | static void |
6725 | bnx2_save_stats(struct bnx2 *bp) | |
6726 | { | |
6727 | u32 *hw_stats = (u32 *) bp->stats_blk; | |
6728 | u32 *temp_stats = (u32 *) bp->temp_stats_blk; | |
6729 | int i; | |
6730 | ||
6731 | /* The 1st 10 counters are 64-bit counters */ | |
6732 | for (i = 0; i < 20; i += 2) { | |
6733 | u32 hi; | |
6734 | u64 lo; | |
6735 | ||
c9885fe5 PR |
6736 | hi = temp_stats[i] + hw_stats[i]; |
6737 | lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1]; | |
354fcd77 MC |
6738 | if (lo > 0xffffffff) |
6739 | hi++; | |
c9885fe5 PR |
6740 | temp_stats[i] = hi; |
6741 | temp_stats[i + 1] = lo & 0xffffffff; | |
354fcd77 MC |
6742 | } |
6743 | ||
6744 | for ( ; i < sizeof(struct statistics_block) / 4; i++) | |
c9885fe5 | 6745 | temp_stats[i] += hw_stats[i]; |
354fcd77 MC |
6746 | } |
6747 | ||
5d07bf26 ED |
6748 | #define GET_64BIT_NET_STATS64(ctr) \ |
6749 | (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo)) | |
b6016b76 | 6750 | |
a4743058 | 6751 | #define GET_64BIT_NET_STATS(ctr) \ |
354fcd77 MC |
6752 | GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \ |
6753 | GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr) | |
b6016b76 | 6754 | |
a4743058 | 6755 | #define GET_32BIT_NET_STATS(ctr) \ |
354fcd77 MC |
6756 | (unsigned long) (bp->stats_blk->ctr + \ |
6757 | bp->temp_stats_blk->ctr) | |
a4743058 | 6758 | |
5d07bf26 ED |
6759 | static struct rtnl_link_stats64 * |
6760 | bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats) | |
b6016b76 | 6761 | { |
972ec0d4 | 6762 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6763 | |
5d07bf26 | 6764 | if (bp->stats_blk == NULL) |
b6016b76 | 6765 | return net_stats; |
5d07bf26 | 6766 | |
b6016b76 | 6767 | net_stats->rx_packets = |
a4743058 MC |
6768 | GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) + |
6769 | GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) + | |
6770 | GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts); | |
b6016b76 MC |
6771 | |
6772 | net_stats->tx_packets = | |
a4743058 MC |
6773 | GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) + |
6774 | GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) + | |
6775 | GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts); | |
b6016b76 MC |
6776 | |
6777 | net_stats->rx_bytes = | |
a4743058 | 6778 | GET_64BIT_NET_STATS(stat_IfHCInOctets); |
b6016b76 MC |
6779 | |
6780 | net_stats->tx_bytes = | |
a4743058 | 6781 | GET_64BIT_NET_STATS(stat_IfHCOutOctets); |
b6016b76 | 6782 | |
6aa20a22 | 6783 | net_stats->multicast = |
6fdae995 | 6784 | GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts); |
b6016b76 | 6785 | |
6aa20a22 | 6786 | net_stats->collisions = |
a4743058 | 6787 | GET_32BIT_NET_STATS(stat_EtherStatsCollisions); |
b6016b76 | 6788 | |
6aa20a22 | 6789 | net_stats->rx_length_errors = |
a4743058 MC |
6790 | GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) + |
6791 | GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts); | |
b6016b76 | 6792 | |
6aa20a22 | 6793 | net_stats->rx_over_errors = |
a4743058 MC |
6794 | GET_32BIT_NET_STATS(stat_IfInFTQDiscards) + |
6795 | GET_32BIT_NET_STATS(stat_IfInMBUFDiscards); | |
b6016b76 | 6796 | |
6aa20a22 | 6797 | net_stats->rx_frame_errors = |
a4743058 | 6798 | GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors); |
b6016b76 | 6799 | |
6aa20a22 | 6800 | net_stats->rx_crc_errors = |
a4743058 | 6801 | GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors); |
b6016b76 MC |
6802 | |
6803 | net_stats->rx_errors = net_stats->rx_length_errors + | |
6804 | net_stats->rx_over_errors + net_stats->rx_frame_errors + | |
6805 | net_stats->rx_crc_errors; | |
6806 | ||
6807 | net_stats->tx_aborted_errors = | |
a4743058 MC |
6808 | GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) + |
6809 | GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions); | |
b6016b76 | 6810 | |
4ce45e02 MC |
6811 | if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) || |
6812 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0)) | |
b6016b76 MC |
6813 | net_stats->tx_carrier_errors = 0; |
6814 | else { | |
6815 | net_stats->tx_carrier_errors = | |
a4743058 | 6816 | GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors); |
b6016b76 MC |
6817 | } |
6818 | ||
6819 | net_stats->tx_errors = | |
a4743058 | 6820 | GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) + |
b6016b76 MC |
6821 | net_stats->tx_aborted_errors + |
6822 | net_stats->tx_carrier_errors; | |
6823 | ||
cea94db9 | 6824 | net_stats->rx_missed_errors = |
a4743058 MC |
6825 | GET_32BIT_NET_STATS(stat_IfInFTQDiscards) + |
6826 | GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) + | |
6827 | GET_32BIT_NET_STATS(stat_FwRxDrop); | |
cea94db9 | 6828 | |
b6016b76 MC |
6829 | return net_stats; |
6830 | } | |
6831 | ||
6832 | /* All ethtool functions called with rtnl_lock */ | |
6833 | ||
6834 | static int | |
6835 | bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
6836 | { | |
972ec0d4 | 6837 | struct bnx2 *bp = netdev_priv(dev); |
7b6b8347 | 6838 | int support_serdes = 0, support_copper = 0; |
b6016b76 MC |
6839 | |
6840 | cmd->supported = SUPPORTED_Autoneg; | |
583c28e5 | 6841 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
7b6b8347 MC |
6842 | support_serdes = 1; |
6843 | support_copper = 1; | |
6844 | } else if (bp->phy_port == PORT_FIBRE) | |
6845 | support_serdes = 1; | |
6846 | else | |
6847 | support_copper = 1; | |
6848 | ||
6849 | if (support_serdes) { | |
b6016b76 MC |
6850 | cmd->supported |= SUPPORTED_1000baseT_Full | |
6851 | SUPPORTED_FIBRE; | |
583c28e5 | 6852 | if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) |
605a9e20 | 6853 | cmd->supported |= SUPPORTED_2500baseX_Full; |
b6016b76 | 6854 | |
b6016b76 | 6855 | } |
7b6b8347 | 6856 | if (support_copper) { |
b6016b76 MC |
6857 | cmd->supported |= SUPPORTED_10baseT_Half | |
6858 | SUPPORTED_10baseT_Full | | |
6859 | SUPPORTED_100baseT_Half | | |
6860 | SUPPORTED_100baseT_Full | | |
6861 | SUPPORTED_1000baseT_Full | | |
6862 | SUPPORTED_TP; | |
6863 | ||
b6016b76 MC |
6864 | } |
6865 | ||
7b6b8347 MC |
6866 | spin_lock_bh(&bp->phy_lock); |
6867 | cmd->port = bp->phy_port; | |
b6016b76 MC |
6868 | cmd->advertising = bp->advertising; |
6869 | ||
6870 | if (bp->autoneg & AUTONEG_SPEED) { | |
6871 | cmd->autoneg = AUTONEG_ENABLE; | |
70739497 | 6872 | } else { |
b6016b76 MC |
6873 | cmd->autoneg = AUTONEG_DISABLE; |
6874 | } | |
6875 | ||
6876 | if (netif_carrier_ok(dev)) { | |
70739497 | 6877 | ethtool_cmd_speed_set(cmd, bp->line_speed); |
b6016b76 | 6878 | cmd->duplex = bp->duplex; |
4016badd MC |
6879 | if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) { |
6880 | if (bp->phy_flags & BNX2_PHY_FLAG_MDIX) | |
6881 | cmd->eth_tp_mdix = ETH_TP_MDI_X; | |
6882 | else | |
6883 | cmd->eth_tp_mdix = ETH_TP_MDI; | |
6884 | } | |
b6016b76 MC |
6885 | } |
6886 | else { | |
70739497 | 6887 | ethtool_cmd_speed_set(cmd, -1); |
b6016b76 MC |
6888 | cmd->duplex = -1; |
6889 | } | |
7b6b8347 | 6890 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
6891 | |
6892 | cmd->transceiver = XCVR_INTERNAL; | |
6893 | cmd->phy_address = bp->phy_addr; | |
6894 | ||
6895 | return 0; | |
6896 | } | |
6aa20a22 | 6897 | |
b6016b76 MC |
6898 | static int |
6899 | bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
6900 | { | |
972ec0d4 | 6901 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6902 | u8 autoneg = bp->autoneg; |
6903 | u8 req_duplex = bp->req_duplex; | |
6904 | u16 req_line_speed = bp->req_line_speed; | |
6905 | u32 advertising = bp->advertising; | |
7b6b8347 MC |
6906 | int err = -EINVAL; |
6907 | ||
6908 | spin_lock_bh(&bp->phy_lock); | |
6909 | ||
6910 | if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE) | |
6911 | goto err_out_unlock; | |
6912 | ||
583c28e5 MC |
6913 | if (cmd->port != bp->phy_port && |
6914 | !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)) | |
7b6b8347 | 6915 | goto err_out_unlock; |
b6016b76 | 6916 | |
d6b14486 MC |
6917 | /* If device is down, we can store the settings only if the user |
6918 | * is setting the currently active port. | |
6919 | */ | |
6920 | if (!netif_running(dev) && cmd->port != bp->phy_port) | |
6921 | goto err_out_unlock; | |
6922 | ||
b6016b76 MC |
6923 | if (cmd->autoneg == AUTONEG_ENABLE) { |
6924 | autoneg |= AUTONEG_SPEED; | |
6925 | ||
beb499af MC |
6926 | advertising = cmd->advertising; |
6927 | if (cmd->port == PORT_TP) { | |
6928 | advertising &= ETHTOOL_ALL_COPPER_SPEED; | |
6929 | if (!advertising) | |
b6016b76 | 6930 | advertising = ETHTOOL_ALL_COPPER_SPEED; |
beb499af MC |
6931 | } else { |
6932 | advertising &= ETHTOOL_ALL_FIBRE_SPEED; | |
6933 | if (!advertising) | |
6934 | advertising = ETHTOOL_ALL_FIBRE_SPEED; | |
b6016b76 MC |
6935 | } |
6936 | advertising |= ADVERTISED_Autoneg; | |
6937 | } | |
6938 | else { | |
25db0338 | 6939 | u32 speed = ethtool_cmd_speed(cmd); |
7b6b8347 | 6940 | if (cmd->port == PORT_FIBRE) { |
25db0338 DD |
6941 | if ((speed != SPEED_1000 && |
6942 | speed != SPEED_2500) || | |
80be4434 | 6943 | (cmd->duplex != DUPLEX_FULL)) |
7b6b8347 | 6944 | goto err_out_unlock; |
80be4434 | 6945 | |
25db0338 | 6946 | if (speed == SPEED_2500 && |
583c28e5 | 6947 | !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
7b6b8347 | 6948 | goto err_out_unlock; |
25db0338 | 6949 | } else if (speed == SPEED_1000 || speed == SPEED_2500) |
7b6b8347 MC |
6950 | goto err_out_unlock; |
6951 | ||
b6016b76 | 6952 | autoneg &= ~AUTONEG_SPEED; |
25db0338 | 6953 | req_line_speed = speed; |
b6016b76 MC |
6954 | req_duplex = cmd->duplex; |
6955 | advertising = 0; | |
6956 | } | |
6957 | ||
6958 | bp->autoneg = autoneg; | |
6959 | bp->advertising = advertising; | |
6960 | bp->req_line_speed = req_line_speed; | |
6961 | bp->req_duplex = req_duplex; | |
6962 | ||
d6b14486 MC |
6963 | err = 0; |
6964 | /* If device is down, the new settings will be picked up when it is | |
6965 | * brought up. | |
6966 | */ | |
6967 | if (netif_running(dev)) | |
6968 | err = bnx2_setup_phy(bp, cmd->port); | |
b6016b76 | 6969 | |
7b6b8347 | 6970 | err_out_unlock: |
c770a65c | 6971 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 | 6972 | |
7b6b8347 | 6973 | return err; |
b6016b76 MC |
6974 | } |
6975 | ||
6976 | static void | |
6977 | bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
6978 | { | |
972ec0d4 | 6979 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6980 | |
68aad78c RJ |
6981 | strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); |
6982 | strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); | |
6983 | strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); | |
6984 | strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version)); | |
b6016b76 MC |
6985 | } |
6986 | ||
244ac4f4 MC |
6987 | #define BNX2_REGDUMP_LEN (32 * 1024) |
6988 | ||
6989 | static int | |
6990 | bnx2_get_regs_len(struct net_device *dev) | |
6991 | { | |
6992 | return BNX2_REGDUMP_LEN; | |
6993 | } | |
6994 | ||
6995 | static void | |
6996 | bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p) | |
6997 | { | |
6998 | u32 *p = _p, i, offset; | |
6999 | u8 *orig_p = _p; | |
7000 | struct bnx2 *bp = netdev_priv(dev); | |
b6bc7650 JP |
7001 | static const u32 reg_boundaries[] = { |
7002 | 0x0000, 0x0098, 0x0400, 0x045c, | |
7003 | 0x0800, 0x0880, 0x0c00, 0x0c10, | |
7004 | 0x0c30, 0x0d08, 0x1000, 0x101c, | |
7005 | 0x1040, 0x1048, 0x1080, 0x10a4, | |
7006 | 0x1400, 0x1490, 0x1498, 0x14f0, | |
7007 | 0x1500, 0x155c, 0x1580, 0x15dc, | |
7008 | 0x1600, 0x1658, 0x1680, 0x16d8, | |
7009 | 0x1800, 0x1820, 0x1840, 0x1854, | |
7010 | 0x1880, 0x1894, 0x1900, 0x1984, | |
7011 | 0x1c00, 0x1c0c, 0x1c40, 0x1c54, | |
7012 | 0x1c80, 0x1c94, 0x1d00, 0x1d84, | |
7013 | 0x2000, 0x2030, 0x23c0, 0x2400, | |
7014 | 0x2800, 0x2820, 0x2830, 0x2850, | |
7015 | 0x2b40, 0x2c10, 0x2fc0, 0x3058, | |
7016 | 0x3c00, 0x3c94, 0x4000, 0x4010, | |
7017 | 0x4080, 0x4090, 0x43c0, 0x4458, | |
7018 | 0x4c00, 0x4c18, 0x4c40, 0x4c54, | |
7019 | 0x4fc0, 0x5010, 0x53c0, 0x5444, | |
7020 | 0x5c00, 0x5c18, 0x5c80, 0x5c90, | |
7021 | 0x5fc0, 0x6000, 0x6400, 0x6428, | |
7022 | 0x6800, 0x6848, 0x684c, 0x6860, | |
7023 | 0x6888, 0x6910, 0x8000 | |
7024 | }; | |
244ac4f4 MC |
7025 | |
7026 | regs->version = 0; | |
7027 | ||
7028 | memset(p, 0, BNX2_REGDUMP_LEN); | |
7029 | ||
7030 | if (!netif_running(bp->dev)) | |
7031 | return; | |
7032 | ||
7033 | i = 0; | |
7034 | offset = reg_boundaries[0]; | |
7035 | p += offset; | |
7036 | while (offset < BNX2_REGDUMP_LEN) { | |
e503e066 | 7037 | *p++ = BNX2_RD(bp, offset); |
244ac4f4 MC |
7038 | offset += 4; |
7039 | if (offset == reg_boundaries[i + 1]) { | |
7040 | offset = reg_boundaries[i + 2]; | |
7041 | p = (u32 *) (orig_p + offset); | |
7042 | i += 2; | |
7043 | } | |
7044 | } | |
7045 | } | |
7046 | ||
b6016b76 MC |
7047 | static void |
7048 | bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
7049 | { | |
972ec0d4 | 7050 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7051 | |
f86e82fb | 7052 | if (bp->flags & BNX2_FLAG_NO_WOL) { |
b6016b76 MC |
7053 | wol->supported = 0; |
7054 | wol->wolopts = 0; | |
7055 | } | |
7056 | else { | |
7057 | wol->supported = WAKE_MAGIC; | |
7058 | if (bp->wol) | |
7059 | wol->wolopts = WAKE_MAGIC; | |
7060 | else | |
7061 | wol->wolopts = 0; | |
7062 | } | |
7063 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
7064 | } | |
7065 | ||
7066 | static int | |
7067 | bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
7068 | { | |
972ec0d4 | 7069 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7070 | |
7071 | if (wol->wolopts & ~WAKE_MAGIC) | |
7072 | return -EINVAL; | |
7073 | ||
7074 | if (wol->wolopts & WAKE_MAGIC) { | |
f86e82fb | 7075 | if (bp->flags & BNX2_FLAG_NO_WOL) |
b6016b76 MC |
7076 | return -EINVAL; |
7077 | ||
7078 | bp->wol = 1; | |
7079 | } | |
7080 | else { | |
7081 | bp->wol = 0; | |
7082 | } | |
6d5e85c7 MC |
7083 | |
7084 | device_set_wakeup_enable(&bp->pdev->dev, bp->wol); | |
7085 | ||
b6016b76 MC |
7086 | return 0; |
7087 | } | |
7088 | ||
7089 | static int | |
7090 | bnx2_nway_reset(struct net_device *dev) | |
7091 | { | |
972ec0d4 | 7092 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7093 | u32 bmcr; |
7094 | ||
9f52b564 MC |
7095 | if (!netif_running(dev)) |
7096 | return -EAGAIN; | |
7097 | ||
b6016b76 MC |
7098 | if (!(bp->autoneg & AUTONEG_SPEED)) { |
7099 | return -EINVAL; | |
7100 | } | |
7101 | ||
c770a65c | 7102 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 7103 | |
583c28e5 | 7104 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
7b6b8347 MC |
7105 | int rc; |
7106 | ||
7107 | rc = bnx2_setup_remote_phy(bp, bp->phy_port); | |
7108 | spin_unlock_bh(&bp->phy_lock); | |
7109 | return rc; | |
7110 | } | |
7111 | ||
b6016b76 | 7112 | /* Force a link down visible on the other side */ |
583c28e5 | 7113 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
ca58c3af | 7114 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
c770a65c | 7115 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
7116 | |
7117 | msleep(20); | |
7118 | ||
c770a65c | 7119 | spin_lock_bh(&bp->phy_lock); |
f8dd064e | 7120 | |
40105c0b | 7121 | bp->current_interval = BNX2_SERDES_AN_TIMEOUT; |
f8dd064e MC |
7122 | bp->serdes_an_pending = 1; |
7123 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
b6016b76 MC |
7124 | } |
7125 | ||
ca58c3af | 7126 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 | 7127 | bmcr &= ~BMCR_LOOPBACK; |
ca58c3af | 7128 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); |
b6016b76 | 7129 | |
c770a65c | 7130 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
7131 | |
7132 | return 0; | |
7133 | } | |
7134 | ||
7959ea25 ON |
7135 | static u32 |
7136 | bnx2_get_link(struct net_device *dev) | |
7137 | { | |
7138 | struct bnx2 *bp = netdev_priv(dev); | |
7139 | ||
7140 | return bp->link_up; | |
7141 | } | |
7142 | ||
b6016b76 MC |
7143 | static int |
7144 | bnx2_get_eeprom_len(struct net_device *dev) | |
7145 | { | |
972ec0d4 | 7146 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7147 | |
1122db71 | 7148 | if (bp->flash_info == NULL) |
b6016b76 MC |
7149 | return 0; |
7150 | ||
1122db71 | 7151 | return (int) bp->flash_size; |
b6016b76 MC |
7152 | } |
7153 | ||
7154 | static int | |
7155 | bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
7156 | u8 *eebuf) | |
7157 | { | |
972ec0d4 | 7158 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7159 | int rc; |
7160 | ||
1064e944 | 7161 | /* parameters already validated in ethtool_get_eeprom */ |
b6016b76 MC |
7162 | |
7163 | rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); | |
7164 | ||
7165 | return rc; | |
7166 | } | |
7167 | ||
7168 | static int | |
7169 | bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
7170 | u8 *eebuf) | |
7171 | { | |
972ec0d4 | 7172 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7173 | int rc; |
7174 | ||
1064e944 | 7175 | /* parameters already validated in ethtool_set_eeprom */ |
b6016b76 MC |
7176 | |
7177 | rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); | |
7178 | ||
7179 | return rc; | |
7180 | } | |
7181 | ||
7182 | static int | |
7183 | bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) | |
7184 | { | |
972ec0d4 | 7185 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7186 | |
7187 | memset(coal, 0, sizeof(struct ethtool_coalesce)); | |
7188 | ||
7189 | coal->rx_coalesce_usecs = bp->rx_ticks; | |
7190 | coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip; | |
7191 | coal->rx_coalesce_usecs_irq = bp->rx_ticks_int; | |
7192 | coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int; | |
7193 | ||
7194 | coal->tx_coalesce_usecs = bp->tx_ticks; | |
7195 | coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip; | |
7196 | coal->tx_coalesce_usecs_irq = bp->tx_ticks_int; | |
7197 | coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int; | |
7198 | ||
7199 | coal->stats_block_coalesce_usecs = bp->stats_ticks; | |
7200 | ||
7201 | return 0; | |
7202 | } | |
7203 | ||
7204 | static int | |
7205 | bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) | |
7206 | { | |
972ec0d4 | 7207 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7208 | |
7209 | bp->rx_ticks = (u16) coal->rx_coalesce_usecs; | |
7210 | if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; | |
7211 | ||
6aa20a22 | 7212 | bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; |
b6016b76 MC |
7213 | if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; |
7214 | ||
7215 | bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; | |
7216 | if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; | |
7217 | ||
7218 | bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq; | |
7219 | if (bp->rx_quick_cons_trip_int > 0xff) | |
7220 | bp->rx_quick_cons_trip_int = 0xff; | |
7221 | ||
7222 | bp->tx_ticks = (u16) coal->tx_coalesce_usecs; | |
7223 | if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; | |
7224 | ||
7225 | bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames; | |
7226 | if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; | |
7227 | ||
7228 | bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq; | |
7229 | if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; | |
7230 | ||
7231 | bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq; | |
7232 | if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = | |
7233 | 0xff; | |
7234 | ||
7235 | bp->stats_ticks = coal->stats_block_coalesce_usecs; | |
61d9e3fa | 7236 | if (bp->flags & BNX2_FLAG_BROKEN_STATS) { |
02537b06 MC |
7237 | if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC) |
7238 | bp->stats_ticks = USEC_PER_SEC; | |
7239 | } | |
7ea6920e MC |
7240 | if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS) |
7241 | bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS; | |
7242 | bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS; | |
b6016b76 MC |
7243 | |
7244 | if (netif_running(bp->dev)) { | |
212f9934 | 7245 | bnx2_netif_stop(bp, true); |
9a120bc5 | 7246 | bnx2_init_nic(bp, 0); |
212f9934 | 7247 | bnx2_netif_start(bp, true); |
b6016b76 MC |
7248 | } |
7249 | ||
7250 | return 0; | |
7251 | } | |
7252 | ||
7253 | static void | |
7254 | bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
7255 | { | |
972ec0d4 | 7256 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7257 | |
2bc4078e MC |
7258 | ering->rx_max_pending = BNX2_MAX_TOTAL_RX_DESC_CNT; |
7259 | ering->rx_jumbo_max_pending = BNX2_MAX_TOTAL_RX_PG_DESC_CNT; | |
b6016b76 MC |
7260 | |
7261 | ering->rx_pending = bp->rx_ring_size; | |
47bf4246 | 7262 | ering->rx_jumbo_pending = bp->rx_pg_ring_size; |
b6016b76 | 7263 | |
2bc4078e | 7264 | ering->tx_max_pending = BNX2_MAX_TX_DESC_CNT; |
b6016b76 MC |
7265 | ering->tx_pending = bp->tx_ring_size; |
7266 | } | |
7267 | ||
7268 | static int | |
b033281f | 7269 | bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq) |
b6016b76 | 7270 | { |
13daffa2 | 7271 | if (netif_running(bp->dev)) { |
354fcd77 MC |
7272 | /* Reset will erase chipset stats; save them */ |
7273 | bnx2_save_stats(bp); | |
7274 | ||
212f9934 | 7275 | bnx2_netif_stop(bp, true); |
13daffa2 | 7276 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); |
b033281f MC |
7277 | if (reset_irq) { |
7278 | bnx2_free_irq(bp); | |
7279 | bnx2_del_napi(bp); | |
7280 | } else { | |
7281 | __bnx2_free_irq(bp); | |
7282 | } | |
13daffa2 MC |
7283 | bnx2_free_skbs(bp); |
7284 | bnx2_free_mem(bp); | |
7285 | } | |
7286 | ||
5d5d0015 MC |
7287 | bnx2_set_rx_ring_size(bp, rx); |
7288 | bp->tx_ring_size = tx; | |
b6016b76 MC |
7289 | |
7290 | if (netif_running(bp->dev)) { | |
b033281f MC |
7291 | int rc = 0; |
7292 | ||
7293 | if (reset_irq) { | |
7294 | rc = bnx2_setup_int_mode(bp, disable_msi); | |
7295 | bnx2_init_napi(bp); | |
7296 | } | |
7297 | ||
7298 | if (!rc) | |
7299 | rc = bnx2_alloc_mem(bp); | |
13daffa2 | 7300 | |
a29ba9d2 MC |
7301 | if (!rc) |
7302 | rc = bnx2_request_irq(bp); | |
7303 | ||
6fefb65e MC |
7304 | if (!rc) |
7305 | rc = bnx2_init_nic(bp, 0); | |
7306 | ||
7307 | if (rc) { | |
7308 | bnx2_napi_enable(bp); | |
7309 | dev_close(bp->dev); | |
13daffa2 | 7310 | return rc; |
6fefb65e | 7311 | } |
e9f26c49 MC |
7312 | #ifdef BCM_CNIC |
7313 | mutex_lock(&bp->cnic_lock); | |
7314 | /* Let cnic know about the new status block. */ | |
7315 | if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD) | |
7316 | bnx2_setup_cnic_irq_info(bp); | |
7317 | mutex_unlock(&bp->cnic_lock); | |
7318 | #endif | |
212f9934 | 7319 | bnx2_netif_start(bp, true); |
b6016b76 | 7320 | } |
b6016b76 MC |
7321 | return 0; |
7322 | } | |
7323 | ||
5d5d0015 MC |
7324 | static int |
7325 | bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
7326 | { | |
7327 | struct bnx2 *bp = netdev_priv(dev); | |
7328 | int rc; | |
7329 | ||
2bc4078e MC |
7330 | if ((ering->rx_pending > BNX2_MAX_TOTAL_RX_DESC_CNT) || |
7331 | (ering->tx_pending > BNX2_MAX_TX_DESC_CNT) || | |
5d5d0015 MC |
7332 | (ering->tx_pending <= MAX_SKB_FRAGS)) { |
7333 | ||
7334 | return -EINVAL; | |
7335 | } | |
b033281f MC |
7336 | rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending, |
7337 | false); | |
5d5d0015 MC |
7338 | return rc; |
7339 | } | |
7340 | ||
b6016b76 MC |
7341 | static void |
7342 | bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
7343 | { | |
972ec0d4 | 7344 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7345 | |
7346 | epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); | |
7347 | epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); | |
7348 | epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); | |
7349 | } | |
7350 | ||
7351 | static int | |
7352 | bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
7353 | { | |
972ec0d4 | 7354 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7355 | |
7356 | bp->req_flow_ctrl = 0; | |
7357 | if (epause->rx_pause) | |
7358 | bp->req_flow_ctrl |= FLOW_CTRL_RX; | |
7359 | if (epause->tx_pause) | |
7360 | bp->req_flow_ctrl |= FLOW_CTRL_TX; | |
7361 | ||
7362 | if (epause->autoneg) { | |
7363 | bp->autoneg |= AUTONEG_FLOW_CTRL; | |
7364 | } | |
7365 | else { | |
7366 | bp->autoneg &= ~AUTONEG_FLOW_CTRL; | |
7367 | } | |
7368 | ||
9f52b564 MC |
7369 | if (netif_running(dev)) { |
7370 | spin_lock_bh(&bp->phy_lock); | |
7371 | bnx2_setup_phy(bp, bp->phy_port); | |
7372 | spin_unlock_bh(&bp->phy_lock); | |
7373 | } | |
b6016b76 MC |
7374 | |
7375 | return 0; | |
7376 | } | |
7377 | ||
14ab9b86 | 7378 | static struct { |
b6016b76 | 7379 | char string[ETH_GSTRING_LEN]; |
790dab2f | 7380 | } bnx2_stats_str_arr[] = { |
b6016b76 MC |
7381 | { "rx_bytes" }, |
7382 | { "rx_error_bytes" }, | |
7383 | { "tx_bytes" }, | |
7384 | { "tx_error_bytes" }, | |
7385 | { "rx_ucast_packets" }, | |
7386 | { "rx_mcast_packets" }, | |
7387 | { "rx_bcast_packets" }, | |
7388 | { "tx_ucast_packets" }, | |
7389 | { "tx_mcast_packets" }, | |
7390 | { "tx_bcast_packets" }, | |
7391 | { "tx_mac_errors" }, | |
7392 | { "tx_carrier_errors" }, | |
7393 | { "rx_crc_errors" }, | |
7394 | { "rx_align_errors" }, | |
7395 | { "tx_single_collisions" }, | |
7396 | { "tx_multi_collisions" }, | |
7397 | { "tx_deferred" }, | |
7398 | { "tx_excess_collisions" }, | |
7399 | { "tx_late_collisions" }, | |
7400 | { "tx_total_collisions" }, | |
7401 | { "rx_fragments" }, | |
7402 | { "rx_jabbers" }, | |
7403 | { "rx_undersize_packets" }, | |
7404 | { "rx_oversize_packets" }, | |
7405 | { "rx_64_byte_packets" }, | |
7406 | { "rx_65_to_127_byte_packets" }, | |
7407 | { "rx_128_to_255_byte_packets" }, | |
7408 | { "rx_256_to_511_byte_packets" }, | |
7409 | { "rx_512_to_1023_byte_packets" }, | |
7410 | { "rx_1024_to_1522_byte_packets" }, | |
7411 | { "rx_1523_to_9022_byte_packets" }, | |
7412 | { "tx_64_byte_packets" }, | |
7413 | { "tx_65_to_127_byte_packets" }, | |
7414 | { "tx_128_to_255_byte_packets" }, | |
7415 | { "tx_256_to_511_byte_packets" }, | |
7416 | { "tx_512_to_1023_byte_packets" }, | |
7417 | { "tx_1024_to_1522_byte_packets" }, | |
7418 | { "tx_1523_to_9022_byte_packets" }, | |
7419 | { "rx_xon_frames" }, | |
7420 | { "rx_xoff_frames" }, | |
7421 | { "tx_xon_frames" }, | |
7422 | { "tx_xoff_frames" }, | |
7423 | { "rx_mac_ctrl_frames" }, | |
7424 | { "rx_filtered_packets" }, | |
790dab2f | 7425 | { "rx_ftq_discards" }, |
b6016b76 | 7426 | { "rx_discards" }, |
cea94db9 | 7427 | { "rx_fw_discards" }, |
b6016b76 MC |
7428 | }; |
7429 | ||
0db83cd8 | 7430 | #define BNX2_NUM_STATS ARRAY_SIZE(bnx2_stats_str_arr) |
790dab2f | 7431 | |
b6016b76 MC |
7432 | #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4) |
7433 | ||
f71e1309 | 7434 | static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = { |
b6016b76 MC |
7435 | STATS_OFFSET32(stat_IfHCInOctets_hi), |
7436 | STATS_OFFSET32(stat_IfHCInBadOctets_hi), | |
7437 | STATS_OFFSET32(stat_IfHCOutOctets_hi), | |
7438 | STATS_OFFSET32(stat_IfHCOutBadOctets_hi), | |
7439 | STATS_OFFSET32(stat_IfHCInUcastPkts_hi), | |
7440 | STATS_OFFSET32(stat_IfHCInMulticastPkts_hi), | |
7441 | STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi), | |
7442 | STATS_OFFSET32(stat_IfHCOutUcastPkts_hi), | |
7443 | STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi), | |
7444 | STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi), | |
7445 | STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors), | |
6aa20a22 JG |
7446 | STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), |
7447 | STATS_OFFSET32(stat_Dot3StatsFCSErrors), | |
7448 | STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), | |
7449 | STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), | |
7450 | STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), | |
7451 | STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), | |
7452 | STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), | |
7453 | STATS_OFFSET32(stat_Dot3StatsLateCollisions), | |
7454 | STATS_OFFSET32(stat_EtherStatsCollisions), | |
7455 | STATS_OFFSET32(stat_EtherStatsFragments), | |
7456 | STATS_OFFSET32(stat_EtherStatsJabbers), | |
7457 | STATS_OFFSET32(stat_EtherStatsUndersizePkts), | |
7458 | STATS_OFFSET32(stat_EtherStatsOverrsizePkts), | |
7459 | STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), | |
7460 | STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), | |
7461 | STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), | |
7462 | STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), | |
7463 | STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), | |
7464 | STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), | |
7465 | STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), | |
7466 | STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), | |
7467 | STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), | |
7468 | STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), | |
7469 | STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), | |
7470 | STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), | |
7471 | STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), | |
7472 | STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), | |
7473 | STATS_OFFSET32(stat_XonPauseFramesReceived), | |
7474 | STATS_OFFSET32(stat_XoffPauseFramesReceived), | |
7475 | STATS_OFFSET32(stat_OutXonSent), | |
7476 | STATS_OFFSET32(stat_OutXoffSent), | |
7477 | STATS_OFFSET32(stat_MacControlFramesReceived), | |
7478 | STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), | |
790dab2f | 7479 | STATS_OFFSET32(stat_IfInFTQDiscards), |
6aa20a22 | 7480 | STATS_OFFSET32(stat_IfInMBUFDiscards), |
cea94db9 | 7481 | STATS_OFFSET32(stat_FwRxDrop), |
b6016b76 MC |
7482 | }; |
7483 | ||
7484 | /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are | |
7485 | * skipped because of errata. | |
6aa20a22 | 7486 | */ |
14ab9b86 | 7487 | static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = { |
b6016b76 MC |
7488 | 8,0,8,8,8,8,8,8,8,8, |
7489 | 4,0,4,4,4,4,4,4,4,4, | |
7490 | 4,4,4,4,4,4,4,4,4,4, | |
7491 | 4,4,4,4,4,4,4,4,4,4, | |
790dab2f | 7492 | 4,4,4,4,4,4,4, |
b6016b76 MC |
7493 | }; |
7494 | ||
5b0c76ad MC |
7495 | static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = { |
7496 | 8,0,8,8,8,8,8,8,8,8, | |
7497 | 4,4,4,4,4,4,4,4,4,4, | |
7498 | 4,4,4,4,4,4,4,4,4,4, | |
7499 | 4,4,4,4,4,4,4,4,4,4, | |
790dab2f | 7500 | 4,4,4,4,4,4,4, |
5b0c76ad MC |
7501 | }; |
7502 | ||
b6016b76 MC |
7503 | #define BNX2_NUM_TESTS 6 |
7504 | ||
14ab9b86 | 7505 | static struct { |
b6016b76 MC |
7506 | char string[ETH_GSTRING_LEN]; |
7507 | } bnx2_tests_str_arr[BNX2_NUM_TESTS] = { | |
7508 | { "register_test (offline)" }, | |
7509 | { "memory_test (offline)" }, | |
7510 | { "loopback_test (offline)" }, | |
7511 | { "nvram_test (online)" }, | |
7512 | { "interrupt_test (online)" }, | |
7513 | { "link_test (online)" }, | |
7514 | }; | |
7515 | ||
7516 | static int | |
b9f2c044 | 7517 | bnx2_get_sset_count(struct net_device *dev, int sset) |
b6016b76 | 7518 | { |
b9f2c044 JG |
7519 | switch (sset) { |
7520 | case ETH_SS_TEST: | |
7521 | return BNX2_NUM_TESTS; | |
7522 | case ETH_SS_STATS: | |
7523 | return BNX2_NUM_STATS; | |
7524 | default: | |
7525 | return -EOPNOTSUPP; | |
7526 | } | |
b6016b76 MC |
7527 | } |
7528 | ||
7529 | static void | |
7530 | bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) | |
7531 | { | |
972ec0d4 | 7532 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7533 | |
7534 | memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); | |
7535 | if (etest->flags & ETH_TEST_FL_OFFLINE) { | |
80be4434 MC |
7536 | int i; |
7537 | ||
212f9934 | 7538 | bnx2_netif_stop(bp, true); |
b6016b76 MC |
7539 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG); |
7540 | bnx2_free_skbs(bp); | |
7541 | ||
7542 | if (bnx2_test_registers(bp) != 0) { | |
7543 | buf[0] = 1; | |
7544 | etest->flags |= ETH_TEST_FL_FAILED; | |
7545 | } | |
7546 | if (bnx2_test_memory(bp) != 0) { | |
7547 | buf[1] = 1; | |
7548 | etest->flags |= ETH_TEST_FL_FAILED; | |
7549 | } | |
bc5a0690 | 7550 | if ((buf[2] = bnx2_test_loopback(bp)) != 0) |
b6016b76 | 7551 | etest->flags |= ETH_TEST_FL_FAILED; |
b6016b76 | 7552 | |
9f52b564 MC |
7553 | if (!netif_running(bp->dev)) |
7554 | bnx2_shutdown_chip(bp); | |
b6016b76 | 7555 | else { |
9a120bc5 | 7556 | bnx2_init_nic(bp, 1); |
212f9934 | 7557 | bnx2_netif_start(bp, true); |
b6016b76 MC |
7558 | } |
7559 | ||
7560 | /* wait for link up */ | |
80be4434 MC |
7561 | for (i = 0; i < 7; i++) { |
7562 | if (bp->link_up) | |
7563 | break; | |
7564 | msleep_interruptible(1000); | |
7565 | } | |
b6016b76 MC |
7566 | } |
7567 | ||
7568 | if (bnx2_test_nvram(bp) != 0) { | |
7569 | buf[3] = 1; | |
7570 | etest->flags |= ETH_TEST_FL_FAILED; | |
7571 | } | |
7572 | if (bnx2_test_intr(bp) != 0) { | |
7573 | buf[4] = 1; | |
7574 | etest->flags |= ETH_TEST_FL_FAILED; | |
7575 | } | |
7576 | ||
7577 | if (bnx2_test_link(bp) != 0) { | |
7578 | buf[5] = 1; | |
7579 | etest->flags |= ETH_TEST_FL_FAILED; | |
7580 | ||
7581 | } | |
7582 | } | |
7583 | ||
7584 | static void | |
7585 | bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf) | |
7586 | { | |
7587 | switch (stringset) { | |
7588 | case ETH_SS_STATS: | |
7589 | memcpy(buf, bnx2_stats_str_arr, | |
7590 | sizeof(bnx2_stats_str_arr)); | |
7591 | break; | |
7592 | case ETH_SS_TEST: | |
7593 | memcpy(buf, bnx2_tests_str_arr, | |
7594 | sizeof(bnx2_tests_str_arr)); | |
7595 | break; | |
7596 | } | |
7597 | } | |
7598 | ||
b6016b76 MC |
7599 | static void |
7600 | bnx2_get_ethtool_stats(struct net_device *dev, | |
7601 | struct ethtool_stats *stats, u64 *buf) | |
7602 | { | |
972ec0d4 | 7603 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7604 | int i; |
7605 | u32 *hw_stats = (u32 *) bp->stats_blk; | |
354fcd77 | 7606 | u32 *temp_stats = (u32 *) bp->temp_stats_blk; |
14ab9b86 | 7607 | u8 *stats_len_arr = NULL; |
b6016b76 MC |
7608 | |
7609 | if (hw_stats == NULL) { | |
7610 | memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS); | |
7611 | return; | |
7612 | } | |
7613 | ||
4ce45e02 MC |
7614 | if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || |
7615 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) || | |
7616 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) || | |
7617 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0)) | |
b6016b76 | 7618 | stats_len_arr = bnx2_5706_stats_len_arr; |
5b0c76ad MC |
7619 | else |
7620 | stats_len_arr = bnx2_5708_stats_len_arr; | |
b6016b76 MC |
7621 | |
7622 | for (i = 0; i < BNX2_NUM_STATS; i++) { | |
354fcd77 MC |
7623 | unsigned long offset; |
7624 | ||
b6016b76 MC |
7625 | if (stats_len_arr[i] == 0) { |
7626 | /* skip this counter */ | |
7627 | buf[i] = 0; | |
7628 | continue; | |
7629 | } | |
354fcd77 MC |
7630 | |
7631 | offset = bnx2_stats_offset_arr[i]; | |
b6016b76 MC |
7632 | if (stats_len_arr[i] == 4) { |
7633 | /* 4-byte counter */ | |
354fcd77 MC |
7634 | buf[i] = (u64) *(hw_stats + offset) + |
7635 | *(temp_stats + offset); | |
b6016b76 MC |
7636 | continue; |
7637 | } | |
7638 | /* 8-byte counter */ | |
354fcd77 MC |
7639 | buf[i] = (((u64) *(hw_stats + offset)) << 32) + |
7640 | *(hw_stats + offset + 1) + | |
7641 | (((u64) *(temp_stats + offset)) << 32) + | |
7642 | *(temp_stats + offset + 1); | |
b6016b76 MC |
7643 | } |
7644 | } | |
7645 | ||
7646 | static int | |
2e17e1aa | 7647 | bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state) |
b6016b76 | 7648 | { |
972ec0d4 | 7649 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7650 | |
2e17e1aa | 7651 | switch (state) { |
7652 | case ETHTOOL_ID_ACTIVE: | |
e503e066 MC |
7653 | bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG); |
7654 | BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC); | |
fce55922 | 7655 | return 1; /* cycle on/off once per second */ |
b6016b76 | 7656 | |
2e17e1aa | 7657 | case ETHTOOL_ID_ON: |
e503e066 MC |
7658 | BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE | |
7659 | BNX2_EMAC_LED_1000MB_OVERRIDE | | |
7660 | BNX2_EMAC_LED_100MB_OVERRIDE | | |
7661 | BNX2_EMAC_LED_10MB_OVERRIDE | | |
7662 | BNX2_EMAC_LED_TRAFFIC_OVERRIDE | | |
7663 | BNX2_EMAC_LED_TRAFFIC); | |
2e17e1aa | 7664 | break; |
b6016b76 | 7665 | |
2e17e1aa | 7666 | case ETHTOOL_ID_OFF: |
e503e066 | 7667 | BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE); |
2e17e1aa | 7668 | break; |
9f52b564 | 7669 | |
2e17e1aa | 7670 | case ETHTOOL_ID_INACTIVE: |
e503e066 MC |
7671 | BNX2_WR(bp, BNX2_EMAC_LED, 0); |
7672 | BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save); | |
2e17e1aa | 7673 | break; |
7674 | } | |
9f52b564 | 7675 | |
b6016b76 MC |
7676 | return 0; |
7677 | } | |
7678 | ||
c8f44aff MM |
7679 | static netdev_features_t |
7680 | bnx2_fix_features(struct net_device *dev, netdev_features_t features) | |
4666f87a MC |
7681 | { |
7682 | struct bnx2 *bp = netdev_priv(dev); | |
7683 | ||
8d7dfc2b | 7684 | if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) |
f646968f | 7685 | features |= NETIF_F_HW_VLAN_CTAG_RX; |
8d7dfc2b MM |
7686 | |
7687 | return features; | |
4666f87a MC |
7688 | } |
7689 | ||
fdc8541d | 7690 | static int |
c8f44aff | 7691 | bnx2_set_features(struct net_device *dev, netdev_features_t features) |
fdc8541d | 7692 | { |
7d0fd211 | 7693 | struct bnx2 *bp = netdev_priv(dev); |
7d0fd211 | 7694 | |
7c810477 | 7695 | /* TSO with VLAN tag won't work with current firmware */ |
f646968f | 7696 | if (features & NETIF_F_HW_VLAN_CTAG_TX) |
8d7dfc2b MM |
7697 | dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO); |
7698 | else | |
7699 | dev->vlan_features &= ~NETIF_F_ALL_TSO; | |
7d0fd211 | 7700 | |
f646968f | 7701 | if ((!!(features & NETIF_F_HW_VLAN_CTAG_RX) != |
7d0fd211 JG |
7702 | !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) && |
7703 | netif_running(dev)) { | |
7704 | bnx2_netif_stop(bp, false); | |
8d7dfc2b | 7705 | dev->features = features; |
7d0fd211 JG |
7706 | bnx2_set_rx_mode(dev); |
7707 | bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1); | |
7708 | bnx2_netif_start(bp, false); | |
8d7dfc2b | 7709 | return 1; |
7d0fd211 JG |
7710 | } |
7711 | ||
7712 | return 0; | |
fdc8541d MC |
7713 | } |
7714 | ||
b033281f MC |
7715 | static void bnx2_get_channels(struct net_device *dev, |
7716 | struct ethtool_channels *channels) | |
7717 | { | |
7718 | struct bnx2 *bp = netdev_priv(dev); | |
7719 | u32 max_rx_rings = 1; | |
7720 | u32 max_tx_rings = 1; | |
7721 | ||
7722 | if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) { | |
7723 | max_rx_rings = RX_MAX_RINGS; | |
7724 | max_tx_rings = TX_MAX_RINGS; | |
7725 | } | |
7726 | ||
7727 | channels->max_rx = max_rx_rings; | |
7728 | channels->max_tx = max_tx_rings; | |
7729 | channels->max_other = 0; | |
7730 | channels->max_combined = 0; | |
7731 | channels->rx_count = bp->num_rx_rings; | |
7732 | channels->tx_count = bp->num_tx_rings; | |
7733 | channels->other_count = 0; | |
7734 | channels->combined_count = 0; | |
7735 | } | |
7736 | ||
7737 | static int bnx2_set_channels(struct net_device *dev, | |
7738 | struct ethtool_channels *channels) | |
7739 | { | |
7740 | struct bnx2 *bp = netdev_priv(dev); | |
7741 | u32 max_rx_rings = 1; | |
7742 | u32 max_tx_rings = 1; | |
7743 | int rc = 0; | |
7744 | ||
7745 | if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) { | |
7746 | max_rx_rings = RX_MAX_RINGS; | |
7747 | max_tx_rings = TX_MAX_RINGS; | |
7748 | } | |
7749 | if (channels->rx_count > max_rx_rings || | |
7750 | channels->tx_count > max_tx_rings) | |
7751 | return -EINVAL; | |
7752 | ||
7753 | bp->num_req_rx_rings = channels->rx_count; | |
7754 | bp->num_req_tx_rings = channels->tx_count; | |
7755 | ||
7756 | if (netif_running(dev)) | |
7757 | rc = bnx2_change_ring_size(bp, bp->rx_ring_size, | |
7758 | bp->tx_ring_size, true); | |
7759 | ||
7760 | return rc; | |
7761 | } | |
7762 | ||
7282d491 | 7763 | static const struct ethtool_ops bnx2_ethtool_ops = { |
b6016b76 MC |
7764 | .get_settings = bnx2_get_settings, |
7765 | .set_settings = bnx2_set_settings, | |
7766 | .get_drvinfo = bnx2_get_drvinfo, | |
244ac4f4 MC |
7767 | .get_regs_len = bnx2_get_regs_len, |
7768 | .get_regs = bnx2_get_regs, | |
b6016b76 MC |
7769 | .get_wol = bnx2_get_wol, |
7770 | .set_wol = bnx2_set_wol, | |
7771 | .nway_reset = bnx2_nway_reset, | |
7959ea25 | 7772 | .get_link = bnx2_get_link, |
b6016b76 MC |
7773 | .get_eeprom_len = bnx2_get_eeprom_len, |
7774 | .get_eeprom = bnx2_get_eeprom, | |
7775 | .set_eeprom = bnx2_set_eeprom, | |
7776 | .get_coalesce = bnx2_get_coalesce, | |
7777 | .set_coalesce = bnx2_set_coalesce, | |
7778 | .get_ringparam = bnx2_get_ringparam, | |
7779 | .set_ringparam = bnx2_set_ringparam, | |
7780 | .get_pauseparam = bnx2_get_pauseparam, | |
7781 | .set_pauseparam = bnx2_set_pauseparam, | |
b6016b76 MC |
7782 | .self_test = bnx2_self_test, |
7783 | .get_strings = bnx2_get_strings, | |
2e17e1aa | 7784 | .set_phys_id = bnx2_set_phys_id, |
b6016b76 | 7785 | .get_ethtool_stats = bnx2_get_ethtool_stats, |
b9f2c044 | 7786 | .get_sset_count = bnx2_get_sset_count, |
b033281f MC |
7787 | .get_channels = bnx2_get_channels, |
7788 | .set_channels = bnx2_set_channels, | |
b6016b76 MC |
7789 | }; |
7790 | ||
7791 | /* Called with rtnl_lock */ | |
7792 | static int | |
7793 | bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
7794 | { | |
14ab9b86 | 7795 | struct mii_ioctl_data *data = if_mii(ifr); |
972ec0d4 | 7796 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7797 | int err; |
7798 | ||
7799 | switch(cmd) { | |
7800 | case SIOCGMIIPHY: | |
7801 | data->phy_id = bp->phy_addr; | |
7802 | ||
7803 | /* fallthru */ | |
7804 | case SIOCGMIIREG: { | |
7805 | u32 mii_regval; | |
7806 | ||
583c28e5 | 7807 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
7b6b8347 MC |
7808 | return -EOPNOTSUPP; |
7809 | ||
dad3e452 MC |
7810 | if (!netif_running(dev)) |
7811 | return -EAGAIN; | |
7812 | ||
c770a65c | 7813 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 7814 | err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); |
c770a65c | 7815 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
7816 | |
7817 | data->val_out = mii_regval; | |
7818 | ||
7819 | return err; | |
7820 | } | |
7821 | ||
7822 | case SIOCSMIIREG: | |
583c28e5 | 7823 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
7b6b8347 MC |
7824 | return -EOPNOTSUPP; |
7825 | ||
dad3e452 MC |
7826 | if (!netif_running(dev)) |
7827 | return -EAGAIN; | |
7828 | ||
c770a65c | 7829 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 7830 | err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); |
c770a65c | 7831 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
7832 | |
7833 | return err; | |
7834 | ||
7835 | default: | |
7836 | /* do nothing */ | |
7837 | break; | |
7838 | } | |
7839 | return -EOPNOTSUPP; | |
7840 | } | |
7841 | ||
7842 | /* Called with rtnl_lock */ | |
7843 | static int | |
7844 | bnx2_change_mac_addr(struct net_device *dev, void *p) | |
7845 | { | |
7846 | struct sockaddr *addr = p; | |
972ec0d4 | 7847 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7848 | |
73eef4cd | 7849 | if (!is_valid_ether_addr(addr->sa_data)) |
504f9b5a | 7850 | return -EADDRNOTAVAIL; |
73eef4cd | 7851 | |
b6016b76 MC |
7852 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7853 | if (netif_running(dev)) | |
5fcaed01 | 7854 | bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); |
b6016b76 MC |
7855 | |
7856 | return 0; | |
7857 | } | |
7858 | ||
7859 | /* Called with rtnl_lock */ | |
7860 | static int | |
7861 | bnx2_change_mtu(struct net_device *dev, int new_mtu) | |
7862 | { | |
972ec0d4 | 7863 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7864 | |
7865 | if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) || | |
7866 | ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE)) | |
7867 | return -EINVAL; | |
7868 | ||
7869 | dev->mtu = new_mtu; | |
b033281f MC |
7870 | return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size, |
7871 | false); | |
b6016b76 MC |
7872 | } |
7873 | ||
257ddbda | 7874 | #ifdef CONFIG_NET_POLL_CONTROLLER |
b6016b76 MC |
7875 | static void |
7876 | poll_bnx2(struct net_device *dev) | |
7877 | { | |
972ec0d4 | 7878 | struct bnx2 *bp = netdev_priv(dev); |
b2af2c1d | 7879 | int i; |
b6016b76 | 7880 | |
b2af2c1d | 7881 | for (i = 0; i < bp->irq_nvecs; i++) { |
1bf1e347 MC |
7882 | struct bnx2_irq *irq = &bp->irq_tbl[i]; |
7883 | ||
7884 | disable_irq(irq->vector); | |
7885 | irq->handler(irq->vector, &bp->bnx2_napi[i]); | |
7886 | enable_irq(irq->vector); | |
b2af2c1d | 7887 | } |
b6016b76 MC |
7888 | } |
7889 | #endif | |
7890 | ||
cfd95a63 | 7891 | static void |
253c8b75 MC |
7892 | bnx2_get_5709_media(struct bnx2 *bp) |
7893 | { | |
e503e066 | 7894 | u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); |
253c8b75 MC |
7895 | u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID; |
7896 | u32 strap; | |
7897 | ||
7898 | if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) | |
7899 | return; | |
7900 | else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { | |
583c28e5 | 7901 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
253c8b75 MC |
7902 | return; |
7903 | } | |
7904 | ||
7905 | if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) | |
7906 | strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; | |
7907 | else | |
7908 | strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; | |
7909 | ||
aefd90e4 | 7910 | if (bp->func == 0) { |
253c8b75 MC |
7911 | switch (strap) { |
7912 | case 0x4: | |
7913 | case 0x5: | |
7914 | case 0x6: | |
583c28e5 | 7915 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
253c8b75 MC |
7916 | return; |
7917 | } | |
7918 | } else { | |
7919 | switch (strap) { | |
7920 | case 0x1: | |
7921 | case 0x2: | |
7922 | case 0x4: | |
583c28e5 | 7923 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
253c8b75 MC |
7924 | return; |
7925 | } | |
7926 | } | |
7927 | } | |
7928 | ||
cfd95a63 | 7929 | static void |
883e5151 MC |
7930 | bnx2_get_pci_speed(struct bnx2 *bp) |
7931 | { | |
7932 | u32 reg; | |
7933 | ||
e503e066 | 7934 | reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS); |
883e5151 MC |
7935 | if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { |
7936 | u32 clkreg; | |
7937 | ||
f86e82fb | 7938 | bp->flags |= BNX2_FLAG_PCIX; |
883e5151 | 7939 | |
e503e066 | 7940 | clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); |
883e5151 MC |
7941 | |
7942 | clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; | |
7943 | switch (clkreg) { | |
7944 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: | |
7945 | bp->bus_speed_mhz = 133; | |
7946 | break; | |
7947 | ||
7948 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: | |
7949 | bp->bus_speed_mhz = 100; | |
7950 | break; | |
7951 | ||
7952 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: | |
7953 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: | |
7954 | bp->bus_speed_mhz = 66; | |
7955 | break; | |
7956 | ||
7957 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: | |
7958 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: | |
7959 | bp->bus_speed_mhz = 50; | |
7960 | break; | |
7961 | ||
7962 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: | |
7963 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: | |
7964 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: | |
7965 | bp->bus_speed_mhz = 33; | |
7966 | break; | |
7967 | } | |
7968 | } | |
7969 | else { | |
7970 | if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) | |
7971 | bp->bus_speed_mhz = 66; | |
7972 | else | |
7973 | bp->bus_speed_mhz = 33; | |
7974 | } | |
7975 | ||
7976 | if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) | |
f86e82fb | 7977 | bp->flags |= BNX2_FLAG_PCI_32BIT; |
883e5151 MC |
7978 | |
7979 | } | |
7980 | ||
cfd95a63 | 7981 | static void |
76d99061 MC |
7982 | bnx2_read_vpd_fw_ver(struct bnx2 *bp) |
7983 | { | |
df25bc38 | 7984 | int rc, i, j; |
76d99061 | 7985 | u8 *data; |
df25bc38 | 7986 | unsigned int block_end, rosize, len; |
76d99061 | 7987 | |
012093f6 MC |
7988 | #define BNX2_VPD_NVRAM_OFFSET 0x300 |
7989 | #define BNX2_VPD_LEN 128 | |
76d99061 MC |
7990 | #define BNX2_MAX_VER_SLEN 30 |
7991 | ||
7992 | data = kmalloc(256, GFP_KERNEL); | |
7993 | if (!data) | |
7994 | return; | |
7995 | ||
012093f6 MC |
7996 | rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN, |
7997 | BNX2_VPD_LEN); | |
76d99061 MC |
7998 | if (rc) |
7999 | goto vpd_done; | |
8000 | ||
012093f6 MC |
8001 | for (i = 0; i < BNX2_VPD_LEN; i += 4) { |
8002 | data[i] = data[i + BNX2_VPD_LEN + 3]; | |
8003 | data[i + 1] = data[i + BNX2_VPD_LEN + 2]; | |
8004 | data[i + 2] = data[i + BNX2_VPD_LEN + 1]; | |
8005 | data[i + 3] = data[i + BNX2_VPD_LEN]; | |
76d99061 MC |
8006 | } |
8007 | ||
df25bc38 MC |
8008 | i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA); |
8009 | if (i < 0) | |
8010 | goto vpd_done; | |
76d99061 | 8011 | |
df25bc38 MC |
8012 | rosize = pci_vpd_lrdt_size(&data[i]); |
8013 | i += PCI_VPD_LRDT_TAG_SIZE; | |
8014 | block_end = i + rosize; | |
76d99061 | 8015 | |
df25bc38 MC |
8016 | if (block_end > BNX2_VPD_LEN) |
8017 | goto vpd_done; | |
76d99061 | 8018 | |
df25bc38 MC |
8019 | j = pci_vpd_find_info_keyword(data, i, rosize, |
8020 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
8021 | if (j < 0) | |
8022 | goto vpd_done; | |
76d99061 | 8023 | |
df25bc38 | 8024 | len = pci_vpd_info_field_size(&data[j]); |
76d99061 | 8025 | |
df25bc38 MC |
8026 | j += PCI_VPD_INFO_FLD_HDR_SIZE; |
8027 | if (j + len > block_end || len != 4 || | |
8028 | memcmp(&data[j], "1028", 4)) | |
8029 | goto vpd_done; | |
4067a854 | 8030 | |
df25bc38 MC |
8031 | j = pci_vpd_find_info_keyword(data, i, rosize, |
8032 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
8033 | if (j < 0) | |
8034 | goto vpd_done; | |
4067a854 | 8035 | |
df25bc38 | 8036 | len = pci_vpd_info_field_size(&data[j]); |
4067a854 | 8037 | |
df25bc38 MC |
8038 | j += PCI_VPD_INFO_FLD_HDR_SIZE; |
8039 | if (j + len > block_end || len > BNX2_MAX_VER_SLEN) | |
76d99061 | 8040 | goto vpd_done; |
df25bc38 MC |
8041 | |
8042 | memcpy(bp->fw_version, &data[j], len); | |
8043 | bp->fw_version[len] = ' '; | |
76d99061 MC |
8044 | |
8045 | vpd_done: | |
8046 | kfree(data); | |
8047 | } | |
8048 | ||
cfd95a63 | 8049 | static int |
b6016b76 MC |
8050 | bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) |
8051 | { | |
8052 | struct bnx2 *bp; | |
58fc2ea4 | 8053 | int rc, i, j; |
b6016b76 | 8054 | u32 reg; |
40453c83 | 8055 | u64 dma_mask, persist_dma_mask; |
cd709aa9 | 8056 | int err; |
b6016b76 | 8057 | |
b6016b76 | 8058 | SET_NETDEV_DEV(dev, &pdev->dev); |
972ec0d4 | 8059 | bp = netdev_priv(dev); |
b6016b76 MC |
8060 | |
8061 | bp->flags = 0; | |
8062 | bp->phy_flags = 0; | |
8063 | ||
354fcd77 MC |
8064 | bp->temp_stats_blk = |
8065 | kzalloc(sizeof(struct statistics_block), GFP_KERNEL); | |
8066 | ||
8067 | if (bp->temp_stats_blk == NULL) { | |
8068 | rc = -ENOMEM; | |
8069 | goto err_out; | |
8070 | } | |
8071 | ||
b6016b76 MC |
8072 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ |
8073 | rc = pci_enable_device(pdev); | |
8074 | if (rc) { | |
3a9c6a49 | 8075 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
b6016b76 MC |
8076 | goto err_out; |
8077 | } | |
8078 | ||
8079 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
9b91cf9d | 8080 | dev_err(&pdev->dev, |
3a9c6a49 | 8081 | "Cannot find PCI device base address, aborting\n"); |
b6016b76 MC |
8082 | rc = -ENODEV; |
8083 | goto err_out_disable; | |
8084 | } | |
8085 | ||
8086 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
8087 | if (rc) { | |
3a9c6a49 | 8088 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
b6016b76 MC |
8089 | goto err_out_disable; |
8090 | } | |
8091 | ||
8092 | pci_set_master(pdev); | |
8093 | ||
85768271 | 8094 | bp->pm_cap = pdev->pm_cap; |
b6016b76 | 8095 | if (bp->pm_cap == 0) { |
9b91cf9d | 8096 | dev_err(&pdev->dev, |
3a9c6a49 | 8097 | "Cannot find power management capability, aborting\n"); |
b6016b76 MC |
8098 | rc = -EIO; |
8099 | goto err_out_release; | |
8100 | } | |
8101 | ||
b6016b76 MC |
8102 | bp->dev = dev; |
8103 | bp->pdev = pdev; | |
8104 | ||
8105 | spin_lock_init(&bp->phy_lock); | |
1b8227c4 | 8106 | spin_lock_init(&bp->indirect_lock); |
c5a88950 MC |
8107 | #ifdef BCM_CNIC |
8108 | mutex_init(&bp->cnic_lock); | |
8109 | #endif | |
c4028958 | 8110 | INIT_WORK(&bp->reset_task, bnx2_reset_task); |
b6016b76 | 8111 | |
c0357e97 FR |
8112 | bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID + |
8113 | TX_MAX_TSS_RINGS + 1)); | |
b6016b76 | 8114 | if (!bp->regview) { |
3a9c6a49 | 8115 | dev_err(&pdev->dev, "Cannot map register space, aborting\n"); |
b6016b76 MC |
8116 | rc = -ENOMEM; |
8117 | goto err_out_release; | |
8118 | } | |
8119 | ||
8120 | /* Configure byte swap and enable write to the reg_window registers. | |
8121 | * Rely on CPU to do target byte swapping on big endian systems | |
8122 | * The chip's target access swapping will not swap all accesses | |
8123 | */ | |
e503e066 MC |
8124 | BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, |
8125 | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | | |
8126 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); | |
b6016b76 | 8127 | |
e503e066 | 8128 | bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID); |
b6016b76 | 8129 | |
4ce45e02 | 8130 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
e82760e7 JM |
8131 | if (!pci_is_pcie(pdev)) { |
8132 | dev_err(&pdev->dev, "Not PCIE, aborting\n"); | |
883e5151 MC |
8133 | rc = -EIO; |
8134 | goto err_out_unmap; | |
8135 | } | |
f86e82fb | 8136 | bp->flags |= BNX2_FLAG_PCIE; |
4ce45e02 | 8137 | if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax) |
f86e82fb | 8138 | bp->flags |= BNX2_FLAG_JUMBO_BROKEN; |
c239f279 MC |
8139 | |
8140 | /* AER (Advanced Error Reporting) hooks */ | |
8141 | err = pci_enable_pcie_error_reporting(pdev); | |
4bb9ebc7 MC |
8142 | if (!err) |
8143 | bp->flags |= BNX2_FLAG_AER_ENABLED; | |
c239f279 | 8144 | |
883e5151 | 8145 | } else { |
59b47d8a MC |
8146 | bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); |
8147 | if (bp->pcix_cap == 0) { | |
8148 | dev_err(&pdev->dev, | |
3a9c6a49 | 8149 | "Cannot find PCIX capability, aborting\n"); |
59b47d8a MC |
8150 | rc = -EIO; |
8151 | goto err_out_unmap; | |
8152 | } | |
61d9e3fa | 8153 | bp->flags |= BNX2_FLAG_BROKEN_STATS; |
59b47d8a MC |
8154 | } |
8155 | ||
4ce45e02 MC |
8156 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709 && |
8157 | BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) { | |
555a8428 | 8158 | if (pdev->msix_cap) |
f86e82fb | 8159 | bp->flags |= BNX2_FLAG_MSIX_CAP; |
b4b36042 MC |
8160 | } |
8161 | ||
4ce45e02 MC |
8162 | if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 && |
8163 | BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) { | |
555a8428 | 8164 | if (pdev->msi_cap) |
f86e82fb | 8165 | bp->flags |= BNX2_FLAG_MSI_CAP; |
8e6a72c4 MC |
8166 | } |
8167 | ||
40453c83 | 8168 | /* 5708 cannot support DMA addresses > 40-bit. */ |
4ce45e02 | 8169 | if (BNX2_CHIP(bp) == BNX2_CHIP_5708) |
50cf156a | 8170 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
40453c83 | 8171 | else |
6a35528a | 8172 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
40453c83 MC |
8173 | |
8174 | /* Configure DMA attributes. */ | |
8175 | if (pci_set_dma_mask(pdev, dma_mask) == 0) { | |
8176 | dev->features |= NETIF_F_HIGHDMA; | |
8177 | rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask); | |
8178 | if (rc) { | |
8179 | dev_err(&pdev->dev, | |
3a9c6a49 | 8180 | "pci_set_consistent_dma_mask failed, aborting\n"); |
40453c83 MC |
8181 | goto err_out_unmap; |
8182 | } | |
284901a9 | 8183 | } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) { |
3a9c6a49 | 8184 | dev_err(&pdev->dev, "System does not support DMA, aborting\n"); |
40453c83 MC |
8185 | goto err_out_unmap; |
8186 | } | |
8187 | ||
f86e82fb | 8188 | if (!(bp->flags & BNX2_FLAG_PCIE)) |
883e5151 | 8189 | bnx2_get_pci_speed(bp); |
b6016b76 MC |
8190 | |
8191 | /* 5706A0 may falsely detect SERR and PERR. */ | |
4ce45e02 | 8192 | if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { |
e503e066 | 8193 | reg = BNX2_RD(bp, PCI_COMMAND); |
b6016b76 | 8194 | reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); |
e503e066 | 8195 | BNX2_WR(bp, PCI_COMMAND, reg); |
4ce45e02 | 8196 | } else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) && |
f86e82fb | 8197 | !(bp->flags & BNX2_FLAG_PCIX)) { |
b6016b76 | 8198 | |
9b91cf9d | 8199 | dev_err(&pdev->dev, |
3a9c6a49 | 8200 | "5706 A1 can only be used in a PCIX bus, aborting\n"); |
b6016b76 MC |
8201 | goto err_out_unmap; |
8202 | } | |
8203 | ||
8204 | bnx2_init_nvram(bp); | |
8205 | ||
2726d6e1 | 8206 | reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE); |
e3648b3d | 8207 | |
aefd90e4 MC |
8208 | if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID) |
8209 | bp->func = 1; | |
8210 | ||
e3648b3d | 8211 | if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == |
24cb230b | 8212 | BNX2_SHM_HDR_SIGNATURE_SIG) { |
aefd90e4 | 8213 | u32 off = bp->func << 2; |
24cb230b | 8214 | |
2726d6e1 | 8215 | bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off); |
24cb230b | 8216 | } else |
e3648b3d MC |
8217 | bp->shmem_base = HOST_VIEW_SHMEM_BASE; |
8218 | ||
b6016b76 MC |
8219 | /* Get the permanent MAC address. First we need to make sure the |
8220 | * firmware is actually running. | |
8221 | */ | |
2726d6e1 | 8222 | reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE); |
b6016b76 MC |
8223 | |
8224 | if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != | |
8225 | BNX2_DEV_INFO_SIGNATURE_MAGIC) { | |
3a9c6a49 | 8226 | dev_err(&pdev->dev, "Firmware not running, aborting\n"); |
b6016b76 MC |
8227 | rc = -ENODEV; |
8228 | goto err_out_unmap; | |
8229 | } | |
8230 | ||
76d99061 MC |
8231 | bnx2_read_vpd_fw_ver(bp); |
8232 | ||
8233 | j = strlen(bp->fw_version); | |
2726d6e1 | 8234 | reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV); |
76d99061 | 8235 | for (i = 0; i < 3 && j < 24; i++) { |
58fc2ea4 MC |
8236 | u8 num, k, skip0; |
8237 | ||
76d99061 MC |
8238 | if (i == 0) { |
8239 | bp->fw_version[j++] = 'b'; | |
8240 | bp->fw_version[j++] = 'c'; | |
8241 | bp->fw_version[j++] = ' '; | |
8242 | } | |
58fc2ea4 MC |
8243 | num = (u8) (reg >> (24 - (i * 8))); |
8244 | for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { | |
8245 | if (num >= k || !skip0 || k == 1) { | |
8246 | bp->fw_version[j++] = (num / k) + '0'; | |
8247 | skip0 = 0; | |
8248 | } | |
8249 | } | |
8250 | if (i != 2) | |
8251 | bp->fw_version[j++] = '.'; | |
8252 | } | |
2726d6e1 | 8253 | reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE); |
846f5c62 MC |
8254 | if (reg & BNX2_PORT_FEATURE_WOL_ENABLED) |
8255 | bp->wol = 1; | |
8256 | ||
8257 | if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) { | |
f86e82fb | 8258 | bp->flags |= BNX2_FLAG_ASF_ENABLE; |
c2d3db8c MC |
8259 | |
8260 | for (i = 0; i < 30; i++) { | |
2726d6e1 | 8261 | reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); |
c2d3db8c MC |
8262 | if (reg & BNX2_CONDITION_MFW_RUN_MASK) |
8263 | break; | |
8264 | msleep(10); | |
8265 | } | |
8266 | } | |
2726d6e1 | 8267 | reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); |
58fc2ea4 MC |
8268 | reg &= BNX2_CONDITION_MFW_RUN_MASK; |
8269 | if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN && | |
8270 | reg != BNX2_CONDITION_MFW_RUN_NONE) { | |
2726d6e1 | 8271 | u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR); |
58fc2ea4 | 8272 | |
76d99061 MC |
8273 | if (j < 32) |
8274 | bp->fw_version[j++] = ' '; | |
8275 | for (i = 0; i < 3 && j < 28; i++) { | |
2726d6e1 | 8276 | reg = bnx2_reg_rd_ind(bp, addr + i * 4); |
3aeb7d22 | 8277 | reg = be32_to_cpu(reg); |
58fc2ea4 MC |
8278 | memcpy(&bp->fw_version[j], ®, 4); |
8279 | j += 4; | |
8280 | } | |
8281 | } | |
b6016b76 | 8282 | |
2726d6e1 | 8283 | reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER); |
b6016b76 MC |
8284 | bp->mac_addr[0] = (u8) (reg >> 8); |
8285 | bp->mac_addr[1] = (u8) reg; | |
8286 | ||
2726d6e1 | 8287 | reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER); |
b6016b76 MC |
8288 | bp->mac_addr[2] = (u8) (reg >> 24); |
8289 | bp->mac_addr[3] = (u8) (reg >> 16); | |
8290 | bp->mac_addr[4] = (u8) (reg >> 8); | |
8291 | bp->mac_addr[5] = (u8) reg; | |
8292 | ||
2bc4078e | 8293 | bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT; |
932f3772 | 8294 | bnx2_set_rx_ring_size(bp, 255); |
b6016b76 | 8295 | |
cf7474a6 | 8296 | bp->tx_quick_cons_trip_int = 2; |
b6016b76 | 8297 | bp->tx_quick_cons_trip = 20; |
cf7474a6 | 8298 | bp->tx_ticks_int = 18; |
b6016b76 | 8299 | bp->tx_ticks = 80; |
6aa20a22 | 8300 | |
cf7474a6 MC |
8301 | bp->rx_quick_cons_trip_int = 2; |
8302 | bp->rx_quick_cons_trip = 12; | |
b6016b76 MC |
8303 | bp->rx_ticks_int = 18; |
8304 | bp->rx_ticks = 18; | |
8305 | ||
7ea6920e | 8306 | bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS; |
b6016b76 | 8307 | |
ac392abc | 8308 | bp->current_interval = BNX2_TIMER_INTERVAL; |
b6016b76 | 8309 | |
5b0c76ad MC |
8310 | bp->phy_addr = 1; |
8311 | ||
b6016b76 | 8312 | /* Disable WOL support if we are running on a SERDES chip. */ |
4ce45e02 | 8313 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
253c8b75 | 8314 | bnx2_get_5709_media(bp); |
4ce45e02 | 8315 | else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT) |
583c28e5 | 8316 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
bac0dff6 | 8317 | |
0d8a6571 | 8318 | bp->phy_port = PORT_TP; |
583c28e5 | 8319 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
0d8a6571 | 8320 | bp->phy_port = PORT_FIBRE; |
2726d6e1 | 8321 | reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); |
846f5c62 | 8322 | if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) { |
f86e82fb | 8323 | bp->flags |= BNX2_FLAG_NO_WOL; |
846f5c62 MC |
8324 | bp->wol = 0; |
8325 | } | |
4ce45e02 | 8326 | if (BNX2_CHIP(bp) == BNX2_CHIP_5706) { |
38ea3686 MC |
8327 | /* Don't do parallel detect on this board because of |
8328 | * some board problems. The link will not go down | |
8329 | * if we do parallel detect. | |
8330 | */ | |
8331 | if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP && | |
8332 | pdev->subsystem_device == 0x310c) | |
8333 | bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL; | |
8334 | } else { | |
5b0c76ad | 8335 | bp->phy_addr = 2; |
5b0c76ad | 8336 | if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) |
583c28e5 | 8337 | bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; |
5b0c76ad | 8338 | } |
4ce45e02 MC |
8339 | } else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 || |
8340 | BNX2_CHIP(bp) == BNX2_CHIP_5708) | |
583c28e5 | 8341 | bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX; |
4ce45e02 MC |
8342 | else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 && |
8343 | (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax || | |
8344 | BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx)) | |
583c28e5 | 8345 | bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC; |
b6016b76 | 8346 | |
7c62e83b MC |
8347 | bnx2_init_fw_cap(bp); |
8348 | ||
4ce45e02 MC |
8349 | if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) || |
8350 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) || | |
8351 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) || | |
e503e066 | 8352 | !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) { |
f86e82fb | 8353 | bp->flags |= BNX2_FLAG_NO_WOL; |
846f5c62 MC |
8354 | bp->wol = 0; |
8355 | } | |
dda1e390 | 8356 | |
6d5e85c7 MC |
8357 | if (bp->flags & BNX2_FLAG_NO_WOL) |
8358 | device_set_wakeup_capable(&bp->pdev->dev, false); | |
8359 | else | |
8360 | device_set_wakeup_enable(&bp->pdev->dev, bp->wol); | |
8361 | ||
4ce45e02 | 8362 | if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { |
b6016b76 MC |
8363 | bp->tx_quick_cons_trip_int = |
8364 | bp->tx_quick_cons_trip; | |
8365 | bp->tx_ticks_int = bp->tx_ticks; | |
8366 | bp->rx_quick_cons_trip_int = | |
8367 | bp->rx_quick_cons_trip; | |
8368 | bp->rx_ticks_int = bp->rx_ticks; | |
8369 | bp->comp_prod_trip_int = bp->comp_prod_trip; | |
8370 | bp->com_ticks_int = bp->com_ticks; | |
8371 | bp->cmd_ticks_int = bp->cmd_ticks; | |
8372 | } | |
8373 | ||
f9317a40 MC |
8374 | /* Disable MSI on 5706 if AMD 8132 bridge is found. |
8375 | * | |
8376 | * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes | |
8377 | * with byte enables disabled on the unused 32-bit word. This is legal | |
8378 | * but causes problems on the AMD 8132 which will eventually stop | |
8379 | * responding after a while. | |
8380 | * | |
8381 | * AMD believes this incompatibility is unique to the 5706, and | |
88187dfa | 8382 | * prefers to locally disable MSI rather than globally disabling it. |
f9317a40 | 8383 | */ |
4ce45e02 | 8384 | if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) { |
f9317a40 MC |
8385 | struct pci_dev *amd_8132 = NULL; |
8386 | ||
8387 | while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD, | |
8388 | PCI_DEVICE_ID_AMD_8132_BRIDGE, | |
8389 | amd_8132))) { | |
f9317a40 | 8390 | |
44c10138 AK |
8391 | if (amd_8132->revision >= 0x10 && |
8392 | amd_8132->revision <= 0x13) { | |
f9317a40 MC |
8393 | disable_msi = 1; |
8394 | pci_dev_put(amd_8132); | |
8395 | break; | |
8396 | } | |
8397 | } | |
8398 | } | |
8399 | ||
deaf391b | 8400 | bnx2_set_default_link(bp); |
b6016b76 MC |
8401 | bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; |
8402 | ||
cd339a0e | 8403 | init_timer(&bp->timer); |
ac392abc | 8404 | bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL); |
cd339a0e MC |
8405 | bp->timer.data = (unsigned long) bp; |
8406 | bp->timer.function = bnx2_timer; | |
8407 | ||
7625eb2f | 8408 | #ifdef BCM_CNIC |
41c2178a MC |
8409 | if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN) |
8410 | bp->cnic_eth_dev.max_iscsi_conn = | |
8411 | (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) & | |
8412 | BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT; | |
4bd9b0ff | 8413 | bp->cnic_probe = bnx2_cnic_probe; |
7625eb2f | 8414 | #endif |
c239f279 MC |
8415 | pci_save_state(pdev); |
8416 | ||
b6016b76 MC |
8417 | return 0; |
8418 | ||
8419 | err_out_unmap: | |
4bb9ebc7 | 8420 | if (bp->flags & BNX2_FLAG_AER_ENABLED) { |
c239f279 | 8421 | pci_disable_pcie_error_reporting(pdev); |
4bb9ebc7 MC |
8422 | bp->flags &= ~BNX2_FLAG_AER_ENABLED; |
8423 | } | |
c239f279 | 8424 | |
c0357e97 FR |
8425 | pci_iounmap(pdev, bp->regview); |
8426 | bp->regview = NULL; | |
b6016b76 MC |
8427 | |
8428 | err_out_release: | |
8429 | pci_release_regions(pdev); | |
8430 | ||
8431 | err_out_disable: | |
8432 | pci_disable_device(pdev); | |
b6016b76 MC |
8433 | |
8434 | err_out: | |
8435 | return rc; | |
8436 | } | |
8437 | ||
cfd95a63 | 8438 | static char * |
883e5151 MC |
8439 | bnx2_bus_string(struct bnx2 *bp, char *str) |
8440 | { | |
8441 | char *s = str; | |
8442 | ||
f86e82fb | 8443 | if (bp->flags & BNX2_FLAG_PCIE) { |
883e5151 MC |
8444 | s += sprintf(s, "PCI Express"); |
8445 | } else { | |
8446 | s += sprintf(s, "PCI"); | |
f86e82fb | 8447 | if (bp->flags & BNX2_FLAG_PCIX) |
883e5151 | 8448 | s += sprintf(s, "-X"); |
f86e82fb | 8449 | if (bp->flags & BNX2_FLAG_PCI_32BIT) |
883e5151 MC |
8450 | s += sprintf(s, " 32-bit"); |
8451 | else | |
8452 | s += sprintf(s, " 64-bit"); | |
8453 | s += sprintf(s, " %dMHz", bp->bus_speed_mhz); | |
8454 | } | |
8455 | return str; | |
8456 | } | |
8457 | ||
f048fa9c MC |
8458 | static void |
8459 | bnx2_del_napi(struct bnx2 *bp) | |
8460 | { | |
8461 | int i; | |
8462 | ||
8463 | for (i = 0; i < bp->irq_nvecs; i++) | |
8464 | netif_napi_del(&bp->bnx2_napi[i].napi); | |
8465 | } | |
8466 | ||
8467 | static void | |
35efa7c1 MC |
8468 | bnx2_init_napi(struct bnx2 *bp) |
8469 | { | |
b4b36042 | 8470 | int i; |
35efa7c1 | 8471 | |
4327ba43 | 8472 | for (i = 0; i < bp->irq_nvecs; i++) { |
35e9010b MC |
8473 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; |
8474 | int (*poll)(struct napi_struct *, int); | |
8475 | ||
8476 | if (i == 0) | |
8477 | poll = bnx2_poll; | |
8478 | else | |
f0ea2e63 | 8479 | poll = bnx2_poll_msix; |
35e9010b MC |
8480 | |
8481 | netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64); | |
b4b36042 MC |
8482 | bnapi->bp = bp; |
8483 | } | |
35efa7c1 MC |
8484 | } |
8485 | ||
0421eae6 SH |
8486 | static const struct net_device_ops bnx2_netdev_ops = { |
8487 | .ndo_open = bnx2_open, | |
8488 | .ndo_start_xmit = bnx2_start_xmit, | |
8489 | .ndo_stop = bnx2_close, | |
5d07bf26 | 8490 | .ndo_get_stats64 = bnx2_get_stats64, |
0421eae6 SH |
8491 | .ndo_set_rx_mode = bnx2_set_rx_mode, |
8492 | .ndo_do_ioctl = bnx2_ioctl, | |
8493 | .ndo_validate_addr = eth_validate_addr, | |
8494 | .ndo_set_mac_address = bnx2_change_mac_addr, | |
8495 | .ndo_change_mtu = bnx2_change_mtu, | |
8d7dfc2b MM |
8496 | .ndo_fix_features = bnx2_fix_features, |
8497 | .ndo_set_features = bnx2_set_features, | |
0421eae6 | 8498 | .ndo_tx_timeout = bnx2_tx_timeout, |
257ddbda | 8499 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0421eae6 SH |
8500 | .ndo_poll_controller = poll_bnx2, |
8501 | #endif | |
8502 | }; | |
8503 | ||
cfd95a63 | 8504 | static int |
b6016b76 MC |
8505 | bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
8506 | { | |
8507 | static int version_printed = 0; | |
c0357e97 | 8508 | struct net_device *dev; |
b6016b76 | 8509 | struct bnx2 *bp; |
0795af57 | 8510 | int rc; |
883e5151 | 8511 | char str[40]; |
b6016b76 MC |
8512 | |
8513 | if (version_printed++ == 0) | |
3a9c6a49 | 8514 | pr_info("%s", version); |
b6016b76 MC |
8515 | |
8516 | /* dev zeroed in init_etherdev */ | |
706bf240 | 8517 | dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS); |
b6016b76 MC |
8518 | if (!dev) |
8519 | return -ENOMEM; | |
8520 | ||
8521 | rc = bnx2_init_board(pdev, dev); | |
c0357e97 FR |
8522 | if (rc < 0) |
8523 | goto err_free; | |
b6016b76 | 8524 | |
0421eae6 | 8525 | dev->netdev_ops = &bnx2_netdev_ops; |
b6016b76 | 8526 | dev->watchdog_timeo = TX_TIMEOUT; |
b6016b76 | 8527 | dev->ethtool_ops = &bnx2_ethtool_ops; |
b6016b76 | 8528 | |
972ec0d4 | 8529 | bp = netdev_priv(dev); |
b6016b76 | 8530 | |
1b2f922f MC |
8531 | pci_set_drvdata(pdev, dev); |
8532 | ||
d458cdf7 | 8533 | memcpy(dev->dev_addr, bp->mac_addr, ETH_ALEN); |
1b2f922f | 8534 | |
8d7dfc2b MM |
8535 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
8536 | NETIF_F_TSO | NETIF_F_TSO_ECN | | |
8537 | NETIF_F_RXHASH | NETIF_F_RXCSUM; | |
8538 | ||
4ce45e02 | 8539 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
8d7dfc2b MM |
8540 | dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; |
8541 | ||
8542 | dev->vlan_features = dev->hw_features; | |
f646968f | 8543 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
8d7dfc2b | 8544 | dev->features |= dev->hw_features; |
01789349 | 8545 | dev->priv_flags |= IFF_UNICAST_FLT; |
8d7dfc2b | 8546 | |
b6016b76 | 8547 | if ((rc = register_netdev(dev))) { |
9b91cf9d | 8548 | dev_err(&pdev->dev, "Cannot register net device\n"); |
57579f76 | 8549 | goto error; |
b6016b76 MC |
8550 | } |
8551 | ||
c0357e97 FR |
8552 | netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, " |
8553 | "node addr %pM\n", board_info[ent->driver_data].name, | |
4ce45e02 MC |
8554 | ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A', |
8555 | ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4), | |
c0357e97 FR |
8556 | bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0), |
8557 | pdev->irq, dev->dev_addr); | |
b6016b76 | 8558 | |
b6016b76 | 8559 | return 0; |
57579f76 MC |
8560 | |
8561 | error: | |
fda4d85d | 8562 | pci_iounmap(pdev, bp->regview); |
57579f76 MC |
8563 | pci_release_regions(pdev); |
8564 | pci_disable_device(pdev); | |
c0357e97 | 8565 | err_free: |
57579f76 MC |
8566 | free_netdev(dev); |
8567 | return rc; | |
b6016b76 MC |
8568 | } |
8569 | ||
cfd95a63 | 8570 | static void |
b6016b76 MC |
8571 | bnx2_remove_one(struct pci_dev *pdev) |
8572 | { | |
8573 | struct net_device *dev = pci_get_drvdata(pdev); | |
972ec0d4 | 8574 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
8575 | |
8576 | unregister_netdev(dev); | |
8577 | ||
8333a46a | 8578 | del_timer_sync(&bp->timer); |
cd634019 | 8579 | cancel_work_sync(&bp->reset_task); |
8333a46a | 8580 | |
c0357e97 | 8581 | pci_iounmap(bp->pdev, bp->regview); |
b6016b76 | 8582 | |
354fcd77 MC |
8583 | kfree(bp->temp_stats_blk); |
8584 | ||
4bb9ebc7 | 8585 | if (bp->flags & BNX2_FLAG_AER_ENABLED) { |
c239f279 | 8586 | pci_disable_pcie_error_reporting(pdev); |
4bb9ebc7 MC |
8587 | bp->flags &= ~BNX2_FLAG_AER_ENABLED; |
8588 | } | |
cd709aa9 | 8589 | |
7880b72e | 8590 | bnx2_release_firmware(bp); |
8591 | ||
c239f279 | 8592 | free_netdev(dev); |
cd709aa9 | 8593 | |
b6016b76 MC |
8594 | pci_release_regions(pdev); |
8595 | pci_disable_device(pdev); | |
b6016b76 MC |
8596 | } |
8597 | ||
8598 | static int | |
28fb4eb4 | 8599 | bnx2_suspend(struct device *device) |
b6016b76 | 8600 | { |
28fb4eb4 | 8601 | struct pci_dev *pdev = to_pci_dev(device); |
b6016b76 | 8602 | struct net_device *dev = pci_get_drvdata(pdev); |
972ec0d4 | 8603 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 8604 | |
28fb4eb4 MC |
8605 | if (netif_running(dev)) { |
8606 | cancel_work_sync(&bp->reset_task); | |
8607 | bnx2_netif_stop(bp, true); | |
8608 | netif_device_detach(dev); | |
8609 | del_timer_sync(&bp->timer); | |
8610 | bnx2_shutdown_chip(bp); | |
8611 | __bnx2_free_irq(bp); | |
8612 | bnx2_free_skbs(bp); | |
8613 | } | |
8614 | bnx2_setup_wol(bp); | |
b6016b76 MC |
8615 | return 0; |
8616 | } | |
8617 | ||
8618 | static int | |
28fb4eb4 | 8619 | bnx2_resume(struct device *device) |
b6016b76 | 8620 | { |
28fb4eb4 | 8621 | struct pci_dev *pdev = to_pci_dev(device); |
b6016b76 | 8622 | struct net_device *dev = pci_get_drvdata(pdev); |
972ec0d4 | 8623 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
8624 | |
8625 | if (!netif_running(dev)) | |
8626 | return 0; | |
8627 | ||
829ca9a3 | 8628 | bnx2_set_power_state(bp, PCI_D0); |
b6016b76 | 8629 | netif_device_attach(dev); |
28fb4eb4 | 8630 | bnx2_request_irq(bp); |
9a120bc5 | 8631 | bnx2_init_nic(bp, 1); |
212f9934 | 8632 | bnx2_netif_start(bp, true); |
b6016b76 MC |
8633 | return 0; |
8634 | } | |
8635 | ||
28fb4eb4 MC |
8636 | #ifdef CONFIG_PM_SLEEP |
8637 | static SIMPLE_DEV_PM_OPS(bnx2_pm_ops, bnx2_suspend, bnx2_resume); | |
8638 | #define BNX2_PM_OPS (&bnx2_pm_ops) | |
8639 | ||
8640 | #else | |
8641 | ||
8642 | #define BNX2_PM_OPS NULL | |
8643 | ||
8644 | #endif /* CONFIG_PM_SLEEP */ | |
6ff2da49 WX |
8645 | /** |
8646 | * bnx2_io_error_detected - called when PCI error is detected | |
8647 | * @pdev: Pointer to PCI device | |
8648 | * @state: The current pci connection state | |
8649 | * | |
8650 | * This function is called after a PCI bus error affecting | |
8651 | * this device has been detected. | |
8652 | */ | |
8653 | static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev, | |
8654 | pci_channel_state_t state) | |
8655 | { | |
8656 | struct net_device *dev = pci_get_drvdata(pdev); | |
8657 | struct bnx2 *bp = netdev_priv(dev); | |
8658 | ||
8659 | rtnl_lock(); | |
8660 | netif_device_detach(dev); | |
8661 | ||
2ec3de26 DN |
8662 | if (state == pci_channel_io_perm_failure) { |
8663 | rtnl_unlock(); | |
8664 | return PCI_ERS_RESULT_DISCONNECT; | |
8665 | } | |
8666 | ||
6ff2da49 | 8667 | if (netif_running(dev)) { |
212f9934 | 8668 | bnx2_netif_stop(bp, true); |
6ff2da49 WX |
8669 | del_timer_sync(&bp->timer); |
8670 | bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); | |
8671 | } | |
8672 | ||
8673 | pci_disable_device(pdev); | |
8674 | rtnl_unlock(); | |
8675 | ||
8676 | /* Request a slot slot reset. */ | |
8677 | return PCI_ERS_RESULT_NEED_RESET; | |
8678 | } | |
8679 | ||
8680 | /** | |
8681 | * bnx2_io_slot_reset - called after the pci bus has been reset. | |
8682 | * @pdev: Pointer to PCI device | |
8683 | * | |
8684 | * Restart the card from scratch, as if from a cold-boot. | |
8685 | */ | |
8686 | static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev) | |
8687 | { | |
8688 | struct net_device *dev = pci_get_drvdata(pdev); | |
8689 | struct bnx2 *bp = netdev_priv(dev); | |
02481bc6 MC |
8690 | pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; |
8691 | int err = 0; | |
6ff2da49 WX |
8692 | |
8693 | rtnl_lock(); | |
8694 | if (pci_enable_device(pdev)) { | |
8695 | dev_err(&pdev->dev, | |
3a9c6a49 | 8696 | "Cannot re-enable PCI device after reset\n"); |
cd709aa9 JF |
8697 | } else { |
8698 | pci_set_master(pdev); | |
8699 | pci_restore_state(pdev); | |
8700 | pci_save_state(pdev); | |
8701 | ||
25bfb1dd | 8702 | if (netif_running(dev)) |
02481bc6 | 8703 | err = bnx2_init_nic(bp, 1); |
25bfb1dd | 8704 | |
02481bc6 MC |
8705 | if (!err) |
8706 | result = PCI_ERS_RESULT_RECOVERED; | |
8707 | } | |
8708 | ||
8709 | if (result != PCI_ERS_RESULT_RECOVERED && netif_running(dev)) { | |
8710 | bnx2_napi_enable(bp); | |
8711 | dev_close(dev); | |
6ff2da49 | 8712 | } |
cd709aa9 | 8713 | rtnl_unlock(); |
6ff2da49 | 8714 | |
4bb9ebc7 | 8715 | if (!(bp->flags & BNX2_FLAG_AER_ENABLED)) |
c239f279 MC |
8716 | return result; |
8717 | ||
cd709aa9 JF |
8718 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
8719 | if (err) { | |
8720 | dev_err(&pdev->dev, | |
8721 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", | |
8722 | err); /* non-fatal, continue */ | |
6ff2da49 WX |
8723 | } |
8724 | ||
cd709aa9 | 8725 | return result; |
6ff2da49 WX |
8726 | } |
8727 | ||
8728 | /** | |
8729 | * bnx2_io_resume - called when traffic can start flowing again. | |
8730 | * @pdev: Pointer to PCI device | |
8731 | * | |
8732 | * This callback is called when the error recovery driver tells us that | |
8733 | * its OK to resume normal operation. | |
8734 | */ | |
8735 | static void bnx2_io_resume(struct pci_dev *pdev) | |
8736 | { | |
8737 | struct net_device *dev = pci_get_drvdata(pdev); | |
8738 | struct bnx2 *bp = netdev_priv(dev); | |
8739 | ||
8740 | rtnl_lock(); | |
8741 | if (netif_running(dev)) | |
212f9934 | 8742 | bnx2_netif_start(bp, true); |
6ff2da49 WX |
8743 | |
8744 | netif_device_attach(dev); | |
8745 | rtnl_unlock(); | |
8746 | } | |
8747 | ||
25bfb1dd MC |
8748 | static void bnx2_shutdown(struct pci_dev *pdev) |
8749 | { | |
8750 | struct net_device *dev = pci_get_drvdata(pdev); | |
8751 | struct bnx2 *bp; | |
8752 | ||
8753 | if (!dev) | |
8754 | return; | |
8755 | ||
8756 | bp = netdev_priv(dev); | |
8757 | if (!bp) | |
8758 | return; | |
8759 | ||
8760 | rtnl_lock(); | |
8761 | if (netif_running(dev)) | |
8762 | dev_close(bp->dev); | |
8763 | ||
8764 | if (system_state == SYSTEM_POWER_OFF) | |
8765 | bnx2_set_power_state(bp, PCI_D3hot); | |
8766 | ||
8767 | rtnl_unlock(); | |
8768 | } | |
8769 | ||
fda4d85d | 8770 | static const struct pci_error_handlers bnx2_err_handler = { |
6ff2da49 WX |
8771 | .error_detected = bnx2_io_error_detected, |
8772 | .slot_reset = bnx2_io_slot_reset, | |
8773 | .resume = bnx2_io_resume, | |
8774 | }; | |
8775 | ||
b6016b76 | 8776 | static struct pci_driver bnx2_pci_driver = { |
14ab9b86 PH |
8777 | .name = DRV_MODULE_NAME, |
8778 | .id_table = bnx2_pci_tbl, | |
8779 | .probe = bnx2_init_one, | |
cfd95a63 | 8780 | .remove = bnx2_remove_one, |
28fb4eb4 | 8781 | .driver.pm = BNX2_PM_OPS, |
6ff2da49 | 8782 | .err_handler = &bnx2_err_handler, |
25bfb1dd | 8783 | .shutdown = bnx2_shutdown, |
b6016b76 MC |
8784 | }; |
8785 | ||
5a4123f3 | 8786 | module_pci_driver(bnx2_pci_driver); |