]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/net/ethernet/broadcom/bnx2.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Revert "bnx2: Search VPD with pci_vpd_find_ro_info_keyword()"
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnx2.c
CommitLineData
2e0bf125 1/* bnx2.c: QLogic bnx2 network driver.
b6016b76 2 *
28c4ec0d 3 * Copyright (c) 2004-2014 Broadcom Corporation
2e0bf125 4 * Copyright (c) 2014-2015 QLogic Corporation
b6016b76
MC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 *
10 * Written by: Michael Chan (mchan@broadcom.com)
11 */
12
3a9c6a49 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
f2a4f052
MC		 14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17
555069da 18#include <linux/stringify.h>
f2a4f052
MC		 19#include <linux/kernel.h>
20#include <linux/timer.h>
21#include <linux/errno.h>
22#include <linux/ioport.h>
23#include <linux/slab.h>
24#include <linux/vmalloc.h>
25#include <linux/interrupt.h>
26#include <linux/pci.h>
f2a4f052
MC		 27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/skbuff.h>
30#include <linux/dma-mapping.h>
1977f032 31#include <linux/bitops.h>
f2a4f052
MC		 32#include <asm/io.h>
33#include <asm/irq.h>
34#include <linux/delay.h>
35#include <asm/byteorder.h>
c86a31f4 36#include <asm/page.h>
f2a4f052
MC		 37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
01789349 40#include <linux/if.h>
f2a4f052 41#include <linux/if_vlan.h>
f2a4f052 42#include <net/ip.h>
de081fa5 43#include <net/tcp.h>
f2a4f052 44#include <net/checksum.h>
f2a4f052
MC		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
29b12174 48#include <linux/cache.h>
57579f76 49#include <linux/firmware.h>
706bf240 50#include <linux/log2.h>
cd709aa9 51#include <linux/aer.h>
6df77862 52#include <linux/crash_dump.h>
f2a4f052 53
da556d6a 54#if IS_ENABLED(CONFIG_CNIC)
4edd473f
MC		 55#define BCM_CNIC 1
56#include "cnic_if.h"
57#endif
b6016b76
MC		 58#include "bnx2.h"
59#include "bnx2_fw.h"
b3448b0b 60
b6016b76 61#define DRV_MODULE_NAME "bnx2"
c2c20ef4 62#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw"
22fa159d 63#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
c2c20ef4 64#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw"
22fa159d
MC		 65#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
66#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
b6016b76
MC		 67
68#define RUN_AT(x) (jiffies + (x))
69
70/* Time in jiffies before concluding the transmitter is hung. */
71#define TX_TIMEOUT (5*HZ)
72
b6016b76 73MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
2e0bf125 74MODULE_DESCRIPTION("QLogic BCM5706/5708/5709/5716 Driver");
b6016b76 75MODULE_LICENSE("GPL");
57579f76
MC		 76MODULE_FIRMWARE(FW_MIPS_FILE_06);
77MODULE_FIRMWARE(FW_RV2P_FILE_06);
78MODULE_FIRMWARE(FW_MIPS_FILE_09);
79MODULE_FIRMWARE(FW_RV2P_FILE_09);
078b0735 80MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
b6016b76
MC		 81
82static int disable_msi = 0;
83
d3757ba4 84module_param(disable_msi, int, 0444);
b6016b76
MC		 85MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
86
87typedef enum {
88 BCM5706 = 0,
89 NC370T,
90 NC370I,
91 BCM5706S,
92 NC370F,
5b0c76ad
MC		 93 BCM5708,
94 BCM5708S,
bac0dff6 95 BCM5709,
27a005b8 96 BCM5709S,
7bb0a04f 97 BCM5716,
1caacecb 98 BCM5716S,
b6016b76
MC		 99} board_t;
100
101/* indexed by board_t, above */
fefa8645 102static struct {
b6016b76 103 char *name;
cfd95a63 104} board_info[] = {
b6016b76
MC		 105 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
106 { "HP NC370T Multifunction Gigabit Server Adapter" },
107 { "HP NC370i Multifunction Gigabit Server Adapter" },
108 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
109 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 110 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
111 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 112 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 113 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
7bb0a04f 114 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
1caacecb 115 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
b6016b76
MC		 116 };
117
9baa3c34 118static const struct pci_device_id bnx2_pci_tbl[] = {
b6016b76
MC		 119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
120 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
122 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
128 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 133 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 135 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
7bb0a04f
MC		 137 { PCI_VENDOR_ID_BROADCOM, 0x163b,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
1caacecb 139 { PCI_VENDOR_ID_BROADCOM, 0x163c,
1f2435e5 140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
b6016b76
MC		 141 { 0, }
142};
143
0ced9d01 144static const struct flash_spec flash_table[] =
b6016b76 145{
e30372c9
MC		 146#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
147#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 148 /* Slow EEPROM */
37137709 149 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 150 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 151 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
152 "EEPROM - slow"},
37137709
MC		 153 /* Expansion entry 0001 */
154 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 155 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 156 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
157 "Entry 0001"},
b6016b76
MC		 158 /* Saifun SA25F010 (non-buffered flash) */
159 /* strap, cfg1, & write1 need updates */
37137709 160 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 161 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 162 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
163 "Non-buffered flash (128kB)"},
164 /* Saifun SA25F020 (non-buffered flash) */
165 /* strap, cfg1, & write1 need updates */
37137709 166 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 167 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 168 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
169 "Non-buffered flash (256kB)"},
37137709
MC		 170 /* Expansion entry 0100 */
171 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 173 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
174 "Entry 0100"},
175 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 176 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 177 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 178 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
179 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
180 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
181 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
184 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
185 /* Saifun SA25F005 (non-buffered flash) */
186 /* strap, cfg1, & write1 need updates */
187 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
190 "Non-buffered flash (64kB)"},
191 /* Fast EEPROM */
192 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 193 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 194 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
195 "EEPROM - fast"},
196 /* Expansion entry 1001 */
197 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200 "Entry 1001"},
201 /* Expansion entry 1010 */
202 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1010"},
206 /* ATMEL AT45DB011B (buffered flash) */
207 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 209 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
210 "Buffered flash (128kB)"},
211 /* Expansion entry 1100 */
212 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 213 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 214 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
215 "Entry 1100"},
216 /* Expansion entry 1101 */
217 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220 "Entry 1101"},
221 /* Ateml Expansion entry 1110 */
222 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 223 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 224 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
225 "Entry 1110 (Atmel)"},
226 /* ATMEL AT45DB021B (buffered flash) */
227 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 229 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
230 "Buffered flash (256kB)"},
b6016b76
MC		 231};
232
0ced9d01 233static const struct flash_spec flash_5709 = {
e30372c9
MC		 234 .flags = BNX2_NV_BUFFERED,
235 .page_bits = BCM5709_FLASH_PAGE_BITS,
236 .page_size = BCM5709_FLASH_PAGE_SIZE,
237 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
238 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
239 .name = "5709 Buffered flash (256kB)",
240};
241
b6016b76
MC		 242MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
243
4327ba43 244static void bnx2_init_napi(struct bnx2 *bp);
f048fa9c 245static void bnx2_del_napi(struct bnx2 *bp);
4327ba43 246
35e9010b 247static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
e89bbf10 248{
2f8af120 249 u32 diff;
e89bbf10 250
faac9c4b
MC		 251 /* The ring uses 256 indices for 255 entries, one of them
252 * needs to be skipped.
253 */
b668534c 254 diff = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);
2bc4078e 255 if (unlikely(diff >= BNX2_TX_DESC_CNT)) {
faac9c4b 256 diff &= 0xffff;
2bc4078e
MC		 257 if (diff == BNX2_TX_DESC_CNT)
258 diff = BNX2_MAX_TX_DESC_CNT;
faac9c4b 259 }
807540ba 260 return bp->tx_ring_size - diff;
e89bbf10
MC		 261}
262
b6016b76
MC		 263static u32
264bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
265{
6bc80629 266 unsigned long flags;
1b8227c4
MC		 267 u32 val;
268
6bc80629 269 spin_lock_irqsave(&bp->indirect_lock, flags);
e503e066
MC		 270 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
271 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);
6bc80629 272 spin_unlock_irqrestore(&bp->indirect_lock, flags);
1b8227c4 273 return val;
b6016b76
MC		 274}
275
276static void
277bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
278{
6bc80629
IV		 279 unsigned long flags;
280
281 spin_lock_irqsave(&bp->indirect_lock, flags);
e503e066
MC		 282 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
283 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
6bc80629 284 spin_unlock_irqrestore(&bp->indirect_lock, flags);
b6016b76
MC		 285}
286
2726d6e1
MC		 287static void
288bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
289{
290 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
291}
292
293static u32
294bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
295{
807540ba 296 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
2726d6e1
MC		 297}
298
b6016b76
MC		 299static void
300bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
301{
6bc80629
IV		 302 unsigned long flags;
303
b6016b76 304 offset += cid_addr;
6bc80629 305 spin_lock_irqsave(&bp->indirect_lock, flags);
4ce45e02 306 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
59b47d8a
MC		 307 int i;
308
e503e066
MC		 309 BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);
310 BNX2_WR(bp, BNX2_CTX_CTX_CTRL,
311 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
59b47d8a 312 for (i = 0; i < 5; i++) {
e503e066 313 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);
59b47d8a
MC		 314 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
315 break;
316 udelay(5);
317 }
318 } else {
e503e066
MC		 319 BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);
320 BNX2_WR(bp, BNX2_CTX_DATA, val);
59b47d8a 321 }
6bc80629 322 spin_unlock_irqrestore(&bp->indirect_lock, flags);
b6016b76
MC		 323}
324
4edd473f
MC		 325#ifdef BCM_CNIC
326static int
327bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
328{
329 struct bnx2 *bp = netdev_priv(dev);
330 struct drv_ctl_io *io = &info->data.io;
331
332 switch (info->cmd) {
333 case DRV_CTL_IO_WR_CMD:
334 bnx2_reg_wr_ind(bp, io->offset, io->data);
335 break;
336 case DRV_CTL_IO_RD_CMD:
337 io->data = bnx2_reg_rd_ind(bp, io->offset);
338 break;
339 case DRV_CTL_CTX_WR_CMD:
340 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
341 break;
342 default:
343 return -EINVAL;
344 }
345 return 0;
346}
347
348static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
349{
350 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
351 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
352 int sb_id;
353
354 if (bp->flags & BNX2_FLAG_USING_MSIX) {
355 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
356 bnapi->cnic_present = 0;
357 sb_id = bp->irq_nvecs;
358 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
359 } else {
360 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
361 bnapi->cnic_tag = bnapi->last_status_idx;
362 bnapi->cnic_present = 1;
363 sb_id = 0;
364 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
365 }
366
367 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
368 cp->irq_arr[0].status_blk = (void *)
369 ((unsigned long) bnapi->status_blk.msi +
370 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
371 cp->irq_arr[0].status_blk_num = sb_id;
372 cp->num_irq = 1;
373}
374
375static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
376 void *data)
377{
378 struct bnx2 *bp = netdev_priv(dev);
379 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
380
b8aac410 381 if (!ops)
4edd473f
MC		 382 return -EINVAL;
383
384 if (cp->drv_state & CNIC_DRV_STATE_REGD)
385 return -EBUSY;
386
41c2178a
MC		 387 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))
388 return -ENODEV;
389
4edd473f
MC		 390 bp->cnic_data = data;
391 rcu_assign_pointer(bp->cnic_ops, ops);
392
393 cp->num_irq = 0;
394 cp->drv_state = CNIC_DRV_STATE_REGD;
395
396 bnx2_setup_cnic_irq_info(bp);
397
398 return 0;
399}
400
401static int bnx2_unregister_cnic(struct net_device *dev)
402{
403 struct bnx2 *bp = netdev_priv(dev);
404 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
405 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
406
c5a88950 407 mutex_lock(&bp->cnic_lock);
4edd473f
MC		 408 cp->drv_state = 0;
409 bnapi->cnic_present = 0;
2cfa5a04 410 RCU_INIT_POINTER(bp->cnic_ops, NULL);
c5a88950 411 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 412 synchronize_rcu();
413 return 0;
414}
415
61c2fc4b 416static struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
4edd473f
MC		 417{
418 struct bnx2 *bp = netdev_priv(dev);
419 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
420
7625eb2f
MC		 421 if (!cp->max_iscsi_conn)
422 return NULL;
423
4edd473f
MC		 424 cp->drv_owner = THIS_MODULE;
425 cp->chip_id = bp->chip_id;
426 cp->pdev = bp->pdev;
427 cp->io_base = bp->regview;
428 cp->drv_ctl = bnx2_drv_ctl;
429 cp->drv_register_cnic = bnx2_register_cnic;
430 cp->drv_unregister_cnic = bnx2_unregister_cnic;
431
432 return cp;
433}
4edd473f
MC		 434
435static void
436bnx2_cnic_stop(struct bnx2 *bp)
437{
438 struct cnic_ops *c_ops;
439 struct cnic_ctl_info info;
440
c5a88950 441 mutex_lock(&bp->cnic_lock);
13707f9e
ED		 442 c_ops = rcu_dereference_protected(bp->cnic_ops,
443 lockdep_is_held(&bp->cnic_lock));
4edd473f
MC		 444 if (c_ops) {
445 info.cmd = CNIC_CTL_STOP_CMD;
446 c_ops->cnic_ctl(bp->cnic_data, &info);
447 }
c5a88950 448 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 449}
450
451static void
452bnx2_cnic_start(struct bnx2 *bp)
453{
454 struct cnic_ops *c_ops;
455 struct cnic_ctl_info info;
456
c5a88950 457 mutex_lock(&bp->cnic_lock);
13707f9e
ED		 458 c_ops = rcu_dereference_protected(bp->cnic_ops,
459 lockdep_is_held(&bp->cnic_lock));
4edd473f
MC		 460 if (c_ops) {
461 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
462 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
463
464 bnapi->cnic_tag = bnapi->last_status_idx;
465 }
466 info.cmd = CNIC_CTL_START_CMD;
467 c_ops->cnic_ctl(bp->cnic_data, &info);
468 }
c5a88950 469 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 470}
471
472#else
473
474static void
475bnx2_cnic_stop(struct bnx2 *bp)
476{
477}
478
479static void
480bnx2_cnic_start(struct bnx2 *bp)
481{
482}
483
484#endif
485
b6016b76
MC		 486static int
487bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
488{
489 u32 val1;
490 int i, ret;
491
583c28e5 492 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
e503e066 493 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 494 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
495
e503e066
MC		 496 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
497 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 498
499 udelay(40);
500 }
501
502 val1 = (bp->phy_addr << 21) | (reg << 16) |
503 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
504 BNX2_EMAC_MDIO_COMM_START_BUSY;
e503e066 505 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
b6016b76
MC		 506
507 for (i = 0; i < 50; i++) {
508 udelay(10);
509
e503e066 510 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
b6016b76
MC		 511 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
512 udelay(5);
513
e503e066 514 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
b6016b76
MC		 515 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
516
517 break;
518 }
519 }
520
521 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
522 *val = 0x0;
523 ret = -EBUSY;
524 }
525 else {
526 *val = val1;
527 ret = 0;
528 }
529
583c28e5 530 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
e503e066 531 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 532 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
533
e503e066
MC		 534 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
535 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 536
537 udelay(40);
538 }
539
540 return ret;
541}
542
543static int
544bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
545{
546 u32 val1;
547 int i, ret;
548
583c28e5 549 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
e503e066 550 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 551 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
552
e503e066
MC		 553 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
554 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 555
556 udelay(40);
557 }
558
559 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
560 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
561 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
e503e066 562 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 563
b6016b76
MC		 564 for (i = 0; i < 50; i++) {
565 udelay(10);
566
e503e066 567 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
b6016b76
MC		 568 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
569 udelay(5);
570 break;
571 }
572 }
573
574 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
90e4403a 575 ret = -EBUSY;
b6016b76
MC		 576 else
577 ret = 0;
578
583c28e5 579 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
e503e066 580 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 581 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
582
e503e066
MC		 583 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
584 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 585
586 udelay(40);
587 }
588
589 return ret;
590}
591
592static void
593bnx2_disable_int(struct bnx2 *bp)
594{
b4b36042
MC		 595 int i;
596 struct bnx2_napi *bnapi;
597
598 for (i = 0; i < bp->irq_nvecs; i++) {
599 bnapi = &bp->bnx2_napi[i];
e503e066 600 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
b4b36042
MC		 601 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
602 }
e503e066 603 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
b6016b76
MC		 604}
605
606static void
607bnx2_enable_int(struct bnx2 *bp)
608{
b4b36042
MC		 609 int i;
610 struct bnx2_napi *bnapi;
35efa7c1 611
b4b36042
MC		 612 for (i = 0; i < bp->irq_nvecs; i++) {
613 bnapi = &bp->bnx2_napi[i];
1269a8a6 614
e503e066
MC		 615 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
616 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
617 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
618 bnapi->last_status_idx);
b6016b76 619
e503e066
MC		 620 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
621 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
622 bnapi->last_status_idx);
b4b36042 623 }
e503e066 624 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 625}
626
627static void
628bnx2_disable_int_sync(struct bnx2 *bp)
629{
b4b36042
MC		 630 int i;
631
b6016b76 632 atomic_inc(&bp->intr_sem);
3767546c
MC		 633 if (!netif_running(bp->dev))
634 return;
635
b6016b76 636 bnx2_disable_int(bp);
b4b36042
MC		 637 for (i = 0; i < bp->irq_nvecs; i++)
638 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 639}
640
35efa7c1
MC		 641static void
642bnx2_napi_disable(struct bnx2 *bp)
643{
b4b36042
MC		 644 int i;
645
646 for (i = 0; i < bp->irq_nvecs; i++)
647 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 648}
649
650static void
651bnx2_napi_enable(struct bnx2 *bp)
652{
b4b36042
MC		 653 int i;
654
655 for (i = 0; i < bp->irq_nvecs; i++)
656 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 657}
658
b6016b76 659static void
212f9934 660bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
b6016b76 661{
212f9934
MC		 662 if (stop_cnic)
663 bnx2_cnic_stop(bp);
b6016b76 664 if (netif_running(bp->dev)) {
35efa7c1 665 bnx2_napi_disable(bp);
b6016b76 666 netif_tx_disable(bp->dev);
b6016b76 667 }
b7466560 668 bnx2_disable_int_sync(bp);
a0ba6760 669 netif_carrier_off(bp->dev); /* prevent tx timeout */
b6016b76
MC		 670}
671
672static void
212f9934 673bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
b6016b76
MC		 674{
675 if (atomic_dec_and_test(&bp->intr_sem)) {
676 if (netif_running(bp->dev)) {
706bf240 677 netif_tx_wake_all_queues(bp->dev);
a0ba6760
MC		 678 spin_lock_bh(&bp->phy_lock);
679 if (bp->link_up)
680 netif_carrier_on(bp->dev);
681 spin_unlock_bh(&bp->phy_lock);
35efa7c1 682 bnx2_napi_enable(bp);
b6016b76 683 bnx2_enable_int(bp);
212f9934
MC		 684 if (start_cnic)
685 bnx2_cnic_start(bp);
b6016b76
MC		 686 }
687 }
688}
689
35e9010b
MC		 690static void
691bnx2_free_tx_mem(struct bnx2 *bp)
692{
693 int i;
694
695 for (i = 0; i < bp->num_tx_rings; i++) {
696 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
697 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
698
699 if (txr->tx_desc_ring) {
36227e88
SG		 700 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
701 txr->tx_desc_ring,
702 txr->tx_desc_mapping);
35e9010b
MC		 703 txr->tx_desc_ring = NULL;
704 }
705 kfree(txr->tx_buf_ring);
706 txr->tx_buf_ring = NULL;
707 }
708}
709
bb4f98ab
MC		 710static void
711bnx2_free_rx_mem(struct bnx2 *bp)
712{
713 int i;
714
715 for (i = 0; i < bp->num_rx_rings; i++) {
716 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
717 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
718 int j;
719
720 for (j = 0; j < bp->rx_max_ring; j++) {
721 if (rxr->rx_desc_ring[j])
36227e88
SG		 722 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
723 rxr->rx_desc_ring[j],
724 rxr->rx_desc_mapping[j]);
bb4f98ab
MC		 725 rxr->rx_desc_ring[j] = NULL;
726 }
25b0b999 727 vfree(rxr->rx_buf_ring);
bb4f98ab
MC		 728 rxr->rx_buf_ring = NULL;
729
730 for (j = 0; j < bp->rx_max_pg_ring; j++) {
731 if (rxr->rx_pg_desc_ring[j])
36227e88
SG		 732 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
733 rxr->rx_pg_desc_ring[j],
734 rxr->rx_pg_desc_mapping[j]);
3298a738 735 rxr->rx_pg_desc_ring[j] = NULL;
bb4f98ab 736 }
25b0b999 737 vfree(rxr->rx_pg_ring);
bb4f98ab
MC		 738 rxr->rx_pg_ring = NULL;
739 }
740}
741
35e9010b
MC		 742static int
743bnx2_alloc_tx_mem(struct bnx2 *bp)
744{
745 int i;
746
747 for (i = 0; i < bp->num_tx_rings; i++) {
748 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
749 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
750
751 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
b8aac410 752 if (!txr->tx_buf_ring)
35e9010b
MC		 753 return -ENOMEM;
754
755 txr->tx_desc_ring =
36227e88
SG		 756 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
757 &txr->tx_desc_mapping, GFP_KERNEL);
b8aac410 758 if (!txr->tx_desc_ring)
35e9010b
MC		 759 return -ENOMEM;
760 }
761 return 0;
762}
763
bb4f98ab
MC		 764static int
765bnx2_alloc_rx_mem(struct bnx2 *bp)
766{
767 int i;
768
769 for (i = 0; i < bp->num_rx_rings; i++) {
770 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
771 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
772 int j;
773
774 rxr->rx_buf_ring =
fad953ce 775 vzalloc(array_size(SW_RXBD_RING_SIZE, bp->rx_max_ring));
b8aac410 776 if (!rxr->rx_buf_ring)
bb4f98ab
MC		 777 return -ENOMEM;
778
bb4f98ab
MC		 779 for (j = 0; j < bp->rx_max_ring; j++) {
780 rxr->rx_desc_ring[j] =
36227e88
SG		 781 dma_alloc_coherent(&bp->pdev->dev,
782 RXBD_RING_SIZE,
783 &rxr->rx_desc_mapping[j],
784 GFP_KERNEL);
b8aac410 785 if (!rxr->rx_desc_ring[j])
bb4f98ab
MC		 786 return -ENOMEM;
787
788 }
789
790 if (bp->rx_pg_ring_size) {
fad953ce
KC		 791 rxr->rx_pg_ring =
792 vzalloc(array_size(SW_RXPG_RING_SIZE,
793 bp->rx_max_pg_ring));
b8aac410 794 if (!rxr->rx_pg_ring)
bb4f98ab
MC		 795 return -ENOMEM;
796
bb4f98ab
MC		 797 }
798
799 for (j = 0; j < bp->rx_max_pg_ring; j++) {
800 rxr->rx_pg_desc_ring[j] =
36227e88
SG		 801 dma_alloc_coherent(&bp->pdev->dev,
802 RXBD_RING_SIZE,
803 &rxr->rx_pg_desc_mapping[j],
804 GFP_KERNEL);
b8aac410 805 if (!rxr->rx_pg_desc_ring[j])
bb4f98ab
MC		 806 return -ENOMEM;
807
808 }
809 }
810 return 0;
811}
812
8fae307c 813static void
814bnx2_free_stats_blk(struct net_device *dev)
815{
816 struct bnx2 *bp = netdev_priv(dev);
817
818 if (bp->status_blk) {
819 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
820 bp->status_blk,
821 bp->status_blk_mapping);
822 bp->status_blk = NULL;
823 bp->stats_blk = NULL;
824 }
825}
826
827static int
828bnx2_alloc_stats_blk(struct net_device *dev)
829{
830 int status_blk_size;
831 void *status_blk;
832 struct bnx2 *bp = netdev_priv(dev);
833
834 /* Combine status and statistics blocks into one allocation. */
835 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
836 if (bp->flags & BNX2_FLAG_MSIX_CAP)
837 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
838 BNX2_SBLK_MSIX_ALIGN_SIZE);
839 bp->status_stats_size = status_blk_size +
840 sizeof(struct statistics_block);
750afb08
LC		 841 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
842 &bp->status_blk_mapping, GFP_KERNEL);
b8aac410 843 if (!status_blk)
8fae307c 844 return -ENOMEM;
845
846 bp->status_blk = status_blk;
847 bp->stats_blk = status_blk + status_blk_size;
848 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
849
850 return 0;
851}
852
b6016b76
MC		 853static void
854bnx2_free_mem(struct bnx2 *bp)
855{
13daffa2 856 int i;
43e80b89 857 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
13daffa2 858
35e9010b 859 bnx2_free_tx_mem(bp);
bb4f98ab 860 bnx2_free_rx_mem(bp);
35e9010b 861
59b47d8a
MC		 862 for (i = 0; i < bp->ctx_pages; i++) {
863 if (bp->ctx_blk[i]) {
2bc4078e 864 dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE,
36227e88
SG		 865 bp->ctx_blk[i],
866 bp->ctx_blk_mapping[i]);
59b47d8a
MC		 867 bp->ctx_blk[i] = NULL;
868 }
869 }
8fae307c 870
871 if (bnapi->status_blk.msi)
43e80b89 872 bnapi->status_blk.msi = NULL;
b6016b76
MC		 873}
874
875static int
876bnx2_alloc_mem(struct bnx2 *bp)
877{
8fae307c 878 int i, err;
43e80b89 879 struct bnx2_napi *bnapi;
b6016b76 880
43e80b89 881 bnapi = &bp->bnx2_napi[0];
8fae307c 882 bnapi->status_blk.msi = bp->status_blk;
43e80b89
MC		 883 bnapi->hw_tx_cons_ptr =
884 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
885 bnapi->hw_rx_cons_ptr =
886 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
f86e82fb 887 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
379b39a2 888 for (i = 1; i < bp->irq_nvecs; i++) {
43e80b89
MC		 889 struct status_block_msix *sblk;
890
891 bnapi = &bp->bnx2_napi[i];
b4b36042 892
8fae307c 893 sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i);
43e80b89
MC		 894 bnapi->status_blk.msix = sblk;
895 bnapi->hw_tx_cons_ptr =
896 &sblk->status_tx_quick_consumer_index;
897 bnapi->hw_rx_cons_ptr =
898 &sblk->status_rx_quick_consumer_index;
b4b36042
MC		 899 bnapi->int_num = i << 24;
900 }
901 }
35efa7c1 902
4ce45e02 903 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
2bc4078e 904 bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE;
59b47d8a
MC		 905 if (bp->ctx_pages == 0)
906 bp->ctx_pages = 1;
907 for (i = 0; i < bp->ctx_pages; i++) {
36227e88 908 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
2bc4078e 909 BNX2_PAGE_SIZE,
36227e88
SG		 910 &bp->ctx_blk_mapping[i],
911 GFP_KERNEL);
b8aac410 912 if (!bp->ctx_blk[i])
59b47d8a
MC		 913 goto alloc_mem_err;
914 }
915 }
35e9010b 916
bb4f98ab
MC		 917 err = bnx2_alloc_rx_mem(bp);
918 if (err)
919 goto alloc_mem_err;
920
35e9010b
MC		 921 err = bnx2_alloc_tx_mem(bp);
922 if (err)
923 goto alloc_mem_err;
924
b6016b76
MC		 925 return 0;
926
927alloc_mem_err:
928 bnx2_free_mem(bp);
929 return -ENOMEM;
930}
931
e3648b3d
MC		 932static void
933bnx2_report_fw_link(struct bnx2 *bp)
934{
935 u32 fw_link_status = 0;
936
583c28e5 937 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 938 return;
939
e3648b3d
MC		 940 if (bp->link_up) {
941 u32 bmsr;
942
943 switch (bp->line_speed) {
944 case SPEED_10:
945 if (bp->duplex == DUPLEX_HALF)
946 fw_link_status = BNX2_LINK_STATUS_10HALF;
947 else
948 fw_link_status = BNX2_LINK_STATUS_10FULL;
949 break;
950 case SPEED_100:
951 if (bp->duplex == DUPLEX_HALF)
952 fw_link_status = BNX2_LINK_STATUS_100HALF;
953 else
954 fw_link_status = BNX2_LINK_STATUS_100FULL;
955 break;
956 case SPEED_1000:
957 if (bp->duplex == DUPLEX_HALF)
958 fw_link_status = BNX2_LINK_STATUS_1000HALF;
959 else
960 fw_link_status = BNX2_LINK_STATUS_1000FULL;
961 break;
962 case SPEED_2500:
963 if (bp->duplex == DUPLEX_HALF)
964 fw_link_status = BNX2_LINK_STATUS_2500HALF;
965 else
966 fw_link_status = BNX2_LINK_STATUS_2500FULL;
967 break;
968 }
969
970 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
971
972 if (bp->autoneg) {
973 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
974
ca58c3af
MC		 975 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
976 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 977
978 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 979 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 980 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
981 else
982 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
983 }
984 }
985 else
986 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
987
2726d6e1 988 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 989}
990
9b1084b8
MC		 991static char *
992bnx2_xceiver_str(struct bnx2 *bp)
993{
807540ba 994 return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 995 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
807540ba 996 "Copper");
9b1084b8
MC		 997}
998
b6016b76
MC		 999static void
1000bnx2_report_link(struct bnx2 *bp)
1001{
1002 if (bp->link_up) {
1003 netif_carrier_on(bp->dev);
3a9c6a49
JP		 1004 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
1005 bnx2_xceiver_str(bp),
1006 bp->line_speed,
1007 bp->duplex == DUPLEX_FULL ? "full" : "half");
b6016b76
MC		 1008
1009 if (bp->flow_ctrl) {
1010 if (bp->flow_ctrl & FLOW_CTRL_RX) {
3a9c6a49 1011 pr_cont(", receive ");
b6016b76 1012 if (bp->flow_ctrl & FLOW_CTRL_TX)
3a9c6a49 1013 pr_cont("& transmit ");
b6016b76
MC		 1014 }
1015 else {
3a9c6a49 1016 pr_cont(", transmit ");
b6016b76 1017 }
3a9c6a49 1018 pr_cont("flow control ON");
b6016b76 1019 }
3a9c6a49
JP		 1020 pr_cont("\n");
1021 } else {
b6016b76 1022 netif_carrier_off(bp->dev);
3a9c6a49
JP		 1023 netdev_err(bp->dev, "NIC %s Link is Down\n",
1024 bnx2_xceiver_str(bp));
b6016b76 1025 }
e3648b3d
MC		 1026
1027 bnx2_report_fw_link(bp);
b6016b76
MC		 1028}
1029
1030static void
1031bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1032{
1033 u32 local_adv, remote_adv;
1034
1035 bp->flow_ctrl = 0;
6aa20a22 1036 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 1037 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1038
1039 if (bp->duplex == DUPLEX_FULL) {
1040 bp->flow_ctrl = bp->req_flow_ctrl;
1041 }
1042 return;
1043 }
1044
1045 if (bp->duplex != DUPLEX_FULL) {
1046 return;
1047 }
1048
583c28e5 1049 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4ce45e02 1050 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
5b0c76ad
MC		 1051 u32 val;
1052
1053 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1054 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1055 bp->flow_ctrl |= FLOW_CTRL_TX;
1056 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1057 bp->flow_ctrl |= FLOW_CTRL_RX;
1058 return;
1059 }
1060
ca58c3af
MC		 1061 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1062 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 1063
583c28e5 1064 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1065 u32 new_local_adv = 0;
1066 u32 new_remote_adv = 0;
1067
1068 if (local_adv & ADVERTISE_1000XPAUSE)
1069 new_local_adv |= ADVERTISE_PAUSE_CAP;
1070 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1071 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1072 if (remote_adv & ADVERTISE_1000XPAUSE)
1073 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1074 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1075 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1076
1077 local_adv = new_local_adv;
1078 remote_adv = new_remote_adv;
1079 }
1080
1081 /* See Table 28B-3 of 802.3ab-1999 spec. */
1082 if (local_adv & ADVERTISE_PAUSE_CAP) {
1083 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1084 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1085 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1086 }
1087 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1088 bp->flow_ctrl = FLOW_CTRL_RX;
1089 }
1090 }
1091 else {
1092 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1093 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1094 }
1095 }
1096 }
1097 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1098 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1099 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1100
1101 bp->flow_ctrl = FLOW_CTRL_TX;
1102 }
1103 }
1104}
1105
27a005b8
MC		 1106static int
1107bnx2_5709s_linkup(struct bnx2 *bp)
1108{
1109 u32 val, speed;
1110
1111 bp->link_up = 1;
1112
1113 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1114 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1116
1117 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1118 bp->line_speed = bp->req_line_speed;
1119 bp->duplex = bp->req_duplex;
1120 return 0;
1121 }
1122 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1123 switch (speed) {
1124 case MII_BNX2_GP_TOP_AN_SPEED_10:
1125 bp->line_speed = SPEED_10;
1126 break;
1127 case MII_BNX2_GP_TOP_AN_SPEED_100:
1128 bp->line_speed = SPEED_100;
1129 break;
1130 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1131 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1132 bp->line_speed = SPEED_1000;
1133 break;
1134 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1135 bp->line_speed = SPEED_2500;
1136 break;
1137 }
1138 if (val & MII_BNX2_GP_TOP_AN_FD)
1139 bp->duplex = DUPLEX_FULL;
1140 else
1141 bp->duplex = DUPLEX_HALF;
1142 return 0;
1143}
1144
b6016b76 1145static int
5b0c76ad
MC		 1146bnx2_5708s_linkup(struct bnx2 *bp)
1147{
1148 u32 val;
1149
1150 bp->link_up = 1;
1151 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1152 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1153 case BCM5708S_1000X_STAT1_SPEED_10:
1154 bp->line_speed = SPEED_10;
1155 break;
1156 case BCM5708S_1000X_STAT1_SPEED_100:
1157 bp->line_speed = SPEED_100;
1158 break;
1159 case BCM5708S_1000X_STAT1_SPEED_1G:
1160 bp->line_speed = SPEED_1000;
1161 break;
1162 case BCM5708S_1000X_STAT1_SPEED_2G5:
1163 bp->line_speed = SPEED_2500;
1164 break;
1165 }
1166 if (val & BCM5708S_1000X_STAT1_FD)
1167 bp->duplex = DUPLEX_FULL;
1168 else
1169 bp->duplex = DUPLEX_HALF;
1170
1171 return 0;
1172}
1173
1174static int
1175bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 1176{
1177 u32 bmcr, local_adv, remote_adv, common;
1178
1179 bp->link_up = 1;
1180 bp->line_speed = SPEED_1000;
1181
ca58c3af 1182 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1183 if (bmcr & BMCR_FULLDPLX) {
1184 bp->duplex = DUPLEX_FULL;
1185 }
1186 else {
1187 bp->duplex = DUPLEX_HALF;
1188 }
1189
1190 if (!(bmcr & BMCR_ANENABLE)) {
1191 return 0;
1192 }
1193
ca58c3af
MC		 1194 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1195 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1196
1197 common = local_adv & remote_adv;
1198 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1199
1200 if (common & ADVERTISE_1000XFULL) {
1201 bp->duplex = DUPLEX_FULL;
1202 }
1203 else {
1204 bp->duplex = DUPLEX_HALF;
1205 }
1206 }
1207
1208 return 0;
1209}
1210
1211static int
1212bnx2_copper_linkup(struct bnx2 *bp)
1213{
1214 u32 bmcr;
1215
4016badd
MC		 1216 bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX;
1217
ca58c3af 1218 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1219 if (bmcr & BMCR_ANENABLE) {
1220 u32 local_adv, remote_adv, common;
1221
1222 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1223 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1224
1225 common = local_adv & (remote_adv >> 2);
1226 if (common & ADVERTISE_1000FULL) {
1227 bp->line_speed = SPEED_1000;
1228 bp->duplex = DUPLEX_FULL;
1229 }
1230 else if (common & ADVERTISE_1000HALF) {
1231 bp->line_speed = SPEED_1000;
1232 bp->duplex = DUPLEX_HALF;
1233 }
1234 else {
ca58c3af
MC		 1235 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1236 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1237
1238 common = local_adv & remote_adv;
1239 if (common & ADVERTISE_100FULL) {
1240 bp->line_speed = SPEED_100;
1241 bp->duplex = DUPLEX_FULL;
1242 }
1243 else if (common & ADVERTISE_100HALF) {
1244 bp->line_speed = SPEED_100;
1245 bp->duplex = DUPLEX_HALF;
1246 }
1247 else if (common & ADVERTISE_10FULL) {
1248 bp->line_speed = SPEED_10;
1249 bp->duplex = DUPLEX_FULL;
1250 }
1251 else if (common & ADVERTISE_10HALF) {
1252 bp->line_speed = SPEED_10;
1253 bp->duplex = DUPLEX_HALF;
1254 }
1255 else {
1256 bp->line_speed = 0;
1257 bp->link_up = 0;
1258 }
1259 }
1260 }
1261 else {
1262 if (bmcr & BMCR_SPEED100) {
1263 bp->line_speed = SPEED_100;
1264 }
1265 else {
1266 bp->line_speed = SPEED_10;
1267 }
1268 if (bmcr & BMCR_FULLDPLX) {
1269 bp->duplex = DUPLEX_FULL;
1270 }
1271 else {
1272 bp->duplex = DUPLEX_HALF;
1273 }
1274 }
1275
4016badd
MC		 1276 if (bp->link_up) {
1277 u32 ext_status;
1278
1279 bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status);
1280 if (ext_status & EXT_STATUS_MDIX)
1281 bp->phy_flags |= BNX2_PHY_FLAG_MDIX;
1282 }
1283
b6016b76
MC		 1284 return 0;
1285}
1286
83e3fc89 1287static void
bb4f98ab 1288bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
83e3fc89 1289{
bb4f98ab 1290 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
83e3fc89
MC		 1291
1292 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1293 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1294 val |= 0x02 << 8;
1295
22fa159d
MC		 1296 if (bp->flow_ctrl & FLOW_CTRL_TX)
1297 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
83e3fc89 1298
83e3fc89
MC		 1299 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1300}
1301
bb4f98ab
MC		 1302static void
1303bnx2_init_all_rx_contexts(struct bnx2 *bp)
1304{
1305 int i;
1306 u32 cid;
1307
1308 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1309 if (i == 1)
1310 cid = RX_RSS_CID;
1311 bnx2_init_rx_context(bp, cid);
1312 }
1313}
1314
344478db 1315static void
b6016b76
MC		 1316bnx2_set_mac_link(struct bnx2 *bp)
1317{
1318 u32 val;
1319
e503e066 1320 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
b6016b76
MC		 1321 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1322 (bp->duplex == DUPLEX_HALF)) {
e503e066 1323 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
b6016b76
MC		 1324 }
1325
1326 /* Configure the EMAC mode register. */
e503e066 1327 val = BNX2_RD(bp, BNX2_EMAC_MODE);
b6016b76
MC		 1328
1329 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1330 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1331 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1332
1333 if (bp->link_up) {
5b0c76ad
MC		 1334 switch (bp->line_speed) {
1335 case SPEED_10:
4ce45e02 1336 if (BNX2_CHIP(bp) != BNX2_CHIP_5706) {
59b47d8a 1337 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1338 break;
1339 }
df561f66 1340 fallthrough;
5b0c76ad
MC		 1341 case SPEED_100:
1342 val |= BNX2_EMAC_MODE_PORT_MII;
1343 break;
1344 case SPEED_2500:
59b47d8a 1345 val |= BNX2_EMAC_MODE_25G_MODE;
df561f66 1346 fallthrough;
5b0c76ad
MC		 1347 case SPEED_1000:
1348 val |= BNX2_EMAC_MODE_PORT_GMII;
1349 break;
1350 }
b6016b76
MC		 1351 }
1352 else {
1353 val |= BNX2_EMAC_MODE_PORT_GMII;
1354 }
1355
1356 /* Set the MAC to operate in the appropriate duplex mode. */
1357 if (bp->duplex == DUPLEX_HALF)
1358 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
e503e066 1359 BNX2_WR(bp, BNX2_EMAC_MODE, val);
b6016b76
MC		 1360
1361 /* Enable/disable rx PAUSE. */
1362 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1363
1364 if (bp->flow_ctrl & FLOW_CTRL_RX)
1365 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
e503e066 1366 BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
b6016b76
MC		 1367
1368 /* Enable/disable tx PAUSE. */
e503e066 1369 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);
b6016b76
MC		 1370 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1371
1372 if (bp->flow_ctrl & FLOW_CTRL_TX)
1373 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
e503e066 1374 BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);
b6016b76
MC		 1375
1376 /* Acknowledge the interrupt. */
e503e066 1377 BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
b6016b76 1378
22fa159d 1379 bnx2_init_all_rx_contexts(bp);
b6016b76
MC		 1380}
1381
27a005b8
MC		 1382static void
1383bnx2_enable_bmsr1(struct bnx2 *bp)
1384{
583c28e5 1385 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4ce45e02 1386 (BNX2_CHIP(bp) == BNX2_CHIP_5709))
27a005b8
MC		 1387 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1388 MII_BNX2_BLK_ADDR_GP_STATUS);
1389}
1390
1391static void
1392bnx2_disable_bmsr1(struct bnx2 *bp)
1393{
583c28e5 1394 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4ce45e02 1395 (BNX2_CHIP(bp) == BNX2_CHIP_5709))
27a005b8
MC		 1396 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1397 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1398}
1399
605a9e20
MC		 1400static int
1401bnx2_test_and_enable_2g5(struct bnx2 *bp)
1402{
1403 u32 up1;
1404 int ret = 1;
1405
583c28e5 1406 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1407 return 0;
1408
1409 if (bp->autoneg & AUTONEG_SPEED)
1410 bp->advertising |= ADVERTISED_2500baseX_Full;
1411
4ce45e02 1412 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
27a005b8
MC		 1413 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1414
605a9e20
MC		 1415 bnx2_read_phy(bp, bp->mii_up1, &up1);
1416 if (!(up1 & BCM5708S_UP1_2G5)) {
1417 up1 |= BCM5708S_UP1_2G5;
1418 bnx2_write_phy(bp, bp->mii_up1, up1);
1419 ret = 0;
1420 }
1421
4ce45e02 1422 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
27a005b8
MC		 1423 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1424 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1425
605a9e20
MC		 1426 return ret;
1427}
1428
1429static int
1430bnx2_test_and_disable_2g5(struct bnx2 *bp)
1431{
1432 u32 up1;
1433 int ret = 0;
1434
583c28e5 1435 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1436 return 0;
1437
4ce45e02 1438 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
27a005b8
MC		 1439 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1440
605a9e20
MC		 1441 bnx2_read_phy(bp, bp->mii_up1, &up1);
1442 if (up1 & BCM5708S_UP1_2G5) {
1443 up1 &= ~BCM5708S_UP1_2G5;
1444 bnx2_write_phy(bp, bp->mii_up1, up1);
1445 ret = 1;
1446 }
1447
4ce45e02 1448 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
27a005b8
MC		 1449 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1450 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1451
605a9e20
MC		 1452 return ret;
1453}
1454
1455static void
1456bnx2_enable_forced_2g5(struct bnx2 *bp)
1457{
3f649ab7 1458 u32 bmcr;
cbd6890c 1459 int err;
605a9e20 1460
583c28e5 1461 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1462 return;
1463
4ce45e02 1464 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
27a005b8
MC		 1465 u32 val;
1466
1467 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1468 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1469 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1470 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1471 val |= MII_BNX2_SD_MISC1_FORCE |
1472 MII_BNX2_SD_MISC1_FORCE_2_5G;
1473 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1474 }
27a005b8
MC		 1475
1476 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1477 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1478 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8 1479
4ce45e02 1480 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
cbd6890c
MC		 1481 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1482 if (!err)
1483 bmcr |= BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1484 } else {
1485 return;
605a9e20
MC		 1486 }
1487
cbd6890c
MC		 1488 if (err)
1489 return;
1490
605a9e20
MC		 1491 if (bp->autoneg & AUTONEG_SPEED) {
1492 bmcr &= ~BMCR_ANENABLE;
1493 if (bp->req_duplex == DUPLEX_FULL)
1494 bmcr |= BMCR_FULLDPLX;
1495 }
1496 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1497}
1498
1499static void
1500bnx2_disable_forced_2g5(struct bnx2 *bp)
1501{
3f649ab7 1502 u32 bmcr;
cbd6890c 1503 int err;
605a9e20 1504
583c28e5 1505 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1506 return;
1507
4ce45e02 1508 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
27a005b8
MC		 1509 u32 val;
1510
1511 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1512 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1513 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1514 val &= ~MII_BNX2_SD_MISC1_FORCE;
1515 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1516 }
27a005b8
MC		 1517
1518 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1519 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1520 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8 1521
4ce45e02 1522 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
cbd6890c
MC		 1523 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1524 if (!err)
1525 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1526 } else {
1527 return;
605a9e20
MC		 1528 }
1529
cbd6890c
MC		 1530 if (err)
1531 return;
1532
605a9e20
MC		 1533 if (bp->autoneg & AUTONEG_SPEED)
1534 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1535 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1536}
1537
b2fadeae
MC		 1538static void
1539bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1540{
1541 u32 val;
1542
1543 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1544 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1545 if (start)
1546 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1547 else
1548 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1549}
1550
b6016b76
MC		 1551static int
1552bnx2_set_link(struct bnx2 *bp)
1553{
1554 u32 bmsr;
1555 u8 link_up;
1556
80be4434 1557 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1558 bp->link_up = 1;
1559 return 0;
1560 }
1561
583c28e5 1562 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1563 return 0;
1564
b6016b76
MC		 1565 link_up = bp->link_up;
1566
27a005b8
MC		 1567 bnx2_enable_bmsr1(bp);
1568 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1569 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1570 bnx2_disable_bmsr1(bp);
b6016b76 1571
583c28e5 1572 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4ce45e02 1573 (BNX2_CHIP(bp) == BNX2_CHIP_5706)) {
a2724e25 1574 u32 val, an_dbg;
b6016b76 1575
583c28e5 1576 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1577 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1578 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1579 }
e503e066 1580 val = BNX2_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1581
1582 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1583 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1584 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1585
1586 if ((val & BNX2_EMAC_STATUS_LINK) &&
1587 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1588 bmsr |= BMSR_LSTATUS;
1589 else
1590 bmsr &= ~BMSR_LSTATUS;
1591 }
1592
1593 if (bmsr & BMSR_LSTATUS) {
1594 bp->link_up = 1;
1595
583c28e5 1596 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
4ce45e02 1597 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
5b0c76ad 1598 bnx2_5706s_linkup(bp);
4ce45e02 1599 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
5b0c76ad 1600 bnx2_5708s_linkup(bp);
4ce45e02 1601 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
27a005b8 1602 bnx2_5709s_linkup(bp);
b6016b76
MC		 1603 }
1604 else {
1605 bnx2_copper_linkup(bp);
1606 }
1607 bnx2_resolve_flow_ctrl(bp);
1608 }
1609 else {
583c28e5 1610 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1611 (bp->autoneg & AUTONEG_SPEED))
1612 bnx2_disable_forced_2g5(bp);
b6016b76 1613
583c28e5 1614 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1615 u32 bmcr;
1616
1617 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1618 bmcr |= BMCR_ANENABLE;
1619 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1620
583c28e5 1621 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1622 }
b6016b76
MC		 1623 bp->link_up = 0;
1624 }
1625
1626 if (bp->link_up != link_up) {
1627 bnx2_report_link(bp);
1628 }
1629
1630 bnx2_set_mac_link(bp);
1631
1632 return 0;
1633}
1634
1635static int
1636bnx2_reset_phy(struct bnx2 *bp)
1637{
1638 int i;
1639 u32 reg;
1640
ca58c3af 1641 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1642
1643#define PHY_RESET_MAX_WAIT 100
1644 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1645 udelay(10);
1646
ca58c3af 1647 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1648 if (!(reg & BMCR_RESET)) {
1649 udelay(20);
1650 break;
1651 }
1652 }
1653 if (i == PHY_RESET_MAX_WAIT) {
1654 return -EBUSY;
1655 }
1656 return 0;
1657}
1658
1659static u32
1660bnx2_phy_get_pause_adv(struct bnx2 *bp)
1661{
1662 u32 adv = 0;
1663
1664 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1665 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1666
583c28e5 1667 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1668 adv = ADVERTISE_1000XPAUSE;
1669 }
1670 else {
1671 adv = ADVERTISE_PAUSE_CAP;
1672 }
1673 }
1674 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1675 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1676 adv = ADVERTISE_1000XPSE_ASYM;
1677 }
1678 else {
1679 adv = ADVERTISE_PAUSE_ASYM;
1680 }
1681 }
1682 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1683 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1684 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1685 }
1686 else {
1687 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1688 }
1689 }
1690 return adv;
1691}
1692
a2f13890 1693static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
0d8a6571 1694
b6016b76 1695static int
0d8a6571 1696bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1697__releases(&bp->phy_lock)
1698__acquires(&bp->phy_lock)
0d8a6571
MC		 1699{
1700 u32 speed_arg = 0, pause_adv;
1701
1702 pause_adv = bnx2_phy_get_pause_adv(bp);
1703
1704 if (bp->autoneg & AUTONEG_SPEED) {
1705 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1706 if (bp->advertising & ADVERTISED_10baseT_Half)
1707 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1708 if (bp->advertising & ADVERTISED_10baseT_Full)
1709 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1710 if (bp->advertising & ADVERTISED_100baseT_Half)
1711 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1712 if (bp->advertising & ADVERTISED_100baseT_Full)
1713 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1714 if (bp->advertising & ADVERTISED_1000baseT_Full)
1715 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1716 if (bp->advertising & ADVERTISED_2500baseX_Full)
1717 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1718 } else {
1719 if (bp->req_line_speed == SPEED_2500)
1720 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1721 else if (bp->req_line_speed == SPEED_1000)
1722 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1723 else if (bp->req_line_speed == SPEED_100) {
1724 if (bp->req_duplex == DUPLEX_FULL)
1725 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1726 else
1727 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1728 } else if (bp->req_line_speed == SPEED_10) {
1729 if (bp->req_duplex == DUPLEX_FULL)
1730 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1731 else
1732 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1733 }
1734 }
1735
1736 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1737 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1738 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1739 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1740
1741 if (port == PORT_TP)
1742 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1743 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1744
2726d6e1 1745 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1746
1747 spin_unlock_bh(&bp->phy_lock);
a2f13890 1748 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
0d8a6571
MC		 1749 spin_lock_bh(&bp->phy_lock);
1750
1751 return 0;
1752}
1753
1754static int
1755bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1756__releases(&bp->phy_lock)
1757__acquires(&bp->phy_lock)
b6016b76 1758{
605a9e20 1759 u32 adv, bmcr;
b6016b76
MC		 1760 u32 new_adv = 0;
1761
583c28e5 1762 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
807540ba 1763 return bnx2_setup_remote_phy(bp, port);
0d8a6571 1764
b6016b76
MC		 1765 if (!(bp->autoneg & AUTONEG_SPEED)) {
1766 u32 new_bmcr;
5b0c76ad
MC		 1767 int force_link_down = 0;
1768
605a9e20
MC		 1769 if (bp->req_line_speed == SPEED_2500) {
1770 if (!bnx2_test_and_enable_2g5(bp))
1771 force_link_down = 1;
1772 } else if (bp->req_line_speed == SPEED_1000) {
1773 if (bnx2_test_and_disable_2g5(bp))
1774 force_link_down = 1;
1775 }
ca58c3af 1776 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1777 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1778
ca58c3af 1779 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1780 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1781 new_bmcr |= BMCR_SPEED1000;
605a9e20 1782
4ce45e02 1783 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
27a005b8
MC		 1784 if (bp->req_line_speed == SPEED_2500)
1785 bnx2_enable_forced_2g5(bp);
1786 else if (bp->req_line_speed == SPEED_1000) {
1787 bnx2_disable_forced_2g5(bp);
1788 new_bmcr &= ~0x2000;
1789 }
1790
4ce45e02 1791 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
605a9e20
MC		 1792 if (bp->req_line_speed == SPEED_2500)
1793 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1794 else
1795 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1796 }
1797
b6016b76 1798 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1799 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1800 new_bmcr |= BMCR_FULLDPLX;
1801 }
1802 else {
5b0c76ad 1803 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1804 new_bmcr &= ~BMCR_FULLDPLX;
1805 }
5b0c76ad 1806 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1807 /* Force a link down visible on the other side */
1808 if (bp->link_up) {
ca58c3af 1809 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1810 ~(ADVERTISE_1000XFULL |
1811 ADVERTISE_1000XHALF));
ca58c3af 1812 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1813 BMCR_ANRESTART | BMCR_ANENABLE);
1814
1815 bp->link_up = 0;
1816 netif_carrier_off(bp->dev);
ca58c3af 1817 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1818 bnx2_report_link(bp);
b6016b76 1819 }
ca58c3af
MC		 1820 bnx2_write_phy(bp, bp->mii_adv, adv);
1821 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1822 } else {
1823 bnx2_resolve_flow_ctrl(bp);
1824 bnx2_set_mac_link(bp);
b6016b76
MC		 1825 }
1826 return 0;
1827 }
1828
605a9e20 1829 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1830
b6016b76
MC		 1831 if (bp->advertising & ADVERTISED_1000baseT_Full)
1832 new_adv |= ADVERTISE_1000XFULL;
1833
1834 new_adv |= bnx2_phy_get_pause_adv(bp);
1835
ca58c3af
MC		 1836 bnx2_read_phy(bp, bp->mii_adv, &adv);
1837 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1838
1839 bp->serdes_an_pending = 0;
1840 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1841 /* Force a link down visible on the other side */
1842 if (bp->link_up) {
ca58c3af 1843 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1844 spin_unlock_bh(&bp->phy_lock);
1845 msleep(20);
1846 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1847 }
1848
ca58c3af
MC		 1849 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1850 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1851 BMCR_ANENABLE);
f8dd064e
MC		 1852 /* Speed up link-up time when the link partner
1853 * does not autonegotiate which is very common
1854 * in blade servers. Some blade servers use
1855 * IPMI for kerboard input and it's important
1856 * to minimize link disruptions. Autoneg. involves
1857 * exchanging base pages plus 3 next pages and
1858 * normally completes in about 120 msec.
1859 */
40105c0b 1860 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 1861 bp->serdes_an_pending = 1;
1862 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1863 } else {
1864 bnx2_resolve_flow_ctrl(bp);
1865 bnx2_set_mac_link(bp);
b6016b76
MC		 1866 }
1867
1868 return 0;
1869}
1870
1871#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1872 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1873 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1874 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1875
1876#define ETHTOOL_ALL_COPPER_SPEED \
1877 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1878 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1879 ADVERTISED_1000baseT_Full)
1880
1881#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1882 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1883
b6016b76
MC		 1884#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1885
0d8a6571
MC		 1886static void
1887bnx2_set_default_remote_link(struct bnx2 *bp)
1888{
1889 u32 link;
1890
1891 if (bp->phy_port == PORT_TP)
2726d6e1 1892 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1893 else
2726d6e1 1894 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1895
1896 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1897 bp->req_line_speed = 0;
1898 bp->autoneg |= AUTONEG_SPEED;
1899 bp->advertising = ADVERTISED_Autoneg;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1901 bp->advertising |= ADVERTISED_10baseT_Half;
1902 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1903 bp->advertising |= ADVERTISED_10baseT_Full;
1904 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1905 bp->advertising |= ADVERTISED_100baseT_Half;
1906 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1907 bp->advertising |= ADVERTISED_100baseT_Full;
1908 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1909 bp->advertising |= ADVERTISED_1000baseT_Full;
1910 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1911 bp->advertising |= ADVERTISED_2500baseX_Full;
1912 } else {
1913 bp->autoneg = 0;
1914 bp->advertising = 0;
1915 bp->req_duplex = DUPLEX_FULL;
1916 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1917 bp->req_line_speed = SPEED_10;
1918 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1919 bp->req_duplex = DUPLEX_HALF;
1920 }
1921 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1922 bp->req_line_speed = SPEED_100;
1923 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1924 bp->req_duplex = DUPLEX_HALF;
1925 }
1926 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1927 bp->req_line_speed = SPEED_1000;
1928 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1929 bp->req_line_speed = SPEED_2500;
1930 }
1931}
1932
deaf391b
MC		 1933static void
1934bnx2_set_default_link(struct bnx2 *bp)
1935{
ab59859d
HH		 1936 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1937 bnx2_set_default_remote_link(bp);
1938 return;
1939 }
0d8a6571 1940
deaf391b
MC		 1941 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1942 bp->req_line_speed = 0;
583c28e5 1943 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1944 u32 reg;
1945
1946 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1947
2726d6e1 1948 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1949 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1950 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1951 bp->autoneg = 0;
1952 bp->req_line_speed = bp->line_speed = SPEED_1000;
1953 bp->req_duplex = DUPLEX_FULL;
1954 }
1955 } else
1956 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1957}
1958
df149d70
MC		 1959static void
1960bnx2_send_heart_beat(struct bnx2 *bp)
1961{
1962 u32 msg;
1963 u32 addr;
1964
1965 spin_lock(&bp->indirect_lock);
1966 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1967 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
e503e066
MC		 1968 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1969 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
df149d70
MC		 1970 spin_unlock(&bp->indirect_lock);
1971}
1972
0d8a6571
MC		 1973static void
1974bnx2_remote_phy_event(struct bnx2 *bp)
1975{
1976 u32 msg;
1977 u8 link_up = bp->link_up;
1978 u8 old_port;
1979
2726d6e1 1980 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1981
df149d70
MC		 1982 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1983 bnx2_send_heart_beat(bp);
1984
1985 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1986
0d8a6571
MC		 1987 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1988 bp->link_up = 0;
1989 else {
1990 u32 speed;
1991
1992 bp->link_up = 1;
1993 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1994 bp->duplex = DUPLEX_FULL;
1995 switch (speed) {
1996 case BNX2_LINK_STATUS_10HALF:
1997 bp->duplex = DUPLEX_HALF;
df561f66 1998 fallthrough;
0d8a6571
MC		 1999 case BNX2_LINK_STATUS_10FULL:
2000 bp->line_speed = SPEED_10;
2001 break;
2002 case BNX2_LINK_STATUS_100HALF:
2003 bp->duplex = DUPLEX_HALF;
df561f66 2004 fallthrough;
0d8a6571
MC		 2005 case BNX2_LINK_STATUS_100BASE_T4:
2006 case BNX2_LINK_STATUS_100FULL:
2007 bp->line_speed = SPEED_100;
2008 break;
2009 case BNX2_LINK_STATUS_1000HALF:
2010 bp->duplex = DUPLEX_HALF;
df561f66 2011 fallthrough;
0d8a6571
MC		 2012 case BNX2_LINK_STATUS_1000FULL:
2013 bp->line_speed = SPEED_1000;
2014 break;
2015 case BNX2_LINK_STATUS_2500HALF:
2016 bp->duplex = DUPLEX_HALF;
df561f66 2017 fallthrough;
0d8a6571
MC		 2018 case BNX2_LINK_STATUS_2500FULL:
2019 bp->line_speed = SPEED_2500;
2020 break;
2021 default:
2022 bp->line_speed = 0;
2023 break;
2024 }
2025
0d8a6571
MC		 2026 bp->flow_ctrl = 0;
2027 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2028 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2029 if (bp->duplex == DUPLEX_FULL)
2030 bp->flow_ctrl = bp->req_flow_ctrl;
2031 } else {
2032 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2033 bp->flow_ctrl |= FLOW_CTRL_TX;
2034 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2035 bp->flow_ctrl |= FLOW_CTRL_RX;
2036 }
2037
2038 old_port = bp->phy_port;
2039 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2040 bp->phy_port = PORT_FIBRE;
2041 else
2042 bp->phy_port = PORT_TP;
2043
2044 if (old_port != bp->phy_port)
2045 bnx2_set_default_link(bp);
2046
0d8a6571
MC		 2047 }
2048 if (bp->link_up != link_up)
2049 bnx2_report_link(bp);
2050
2051 bnx2_set_mac_link(bp);
2052}
2053
2054static int
2055bnx2_set_remote_link(struct bnx2 *bp)
2056{
2057 u32 evt_code;
2058
2726d6e1 2059 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 2060 switch (evt_code) {
2061 case BNX2_FW_EVT_CODE_LINK_EVENT:
2062 bnx2_remote_phy_event(bp);
2063 break;
2064 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2065 default:
df149d70 2066 bnx2_send_heart_beat(bp);
0d8a6571
MC		 2067 break;
2068 }
2069 return 0;
2070}
2071
b6016b76
MC		 2072static int
2073bnx2_setup_copper_phy(struct bnx2 *bp)
52d07b1f
HH		 2074__releases(&bp->phy_lock)
2075__acquires(&bp->phy_lock)
b6016b76 2076{
d17e53bd 2077 u32 bmcr, adv_reg, new_adv = 0;
b6016b76
MC		 2078 u32 new_bmcr;
2079
ca58c3af 2080 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 2081
d17e53bd
MC		 2082 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2083 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2084 ADVERTISE_PAUSE_ASYM);
2085
2086 new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising);
2087
b6016b76 2088 if (bp->autoneg & AUTONEG_SPEED) {
d17e53bd 2089 u32 adv1000_reg;
37f07023 2090 u32 new_adv1000 = 0;
b6016b76 2091
d17e53bd 2092 new_adv |= bnx2_phy_get_pause_adv(bp);
b6016b76
MC		 2093
2094 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2095 adv1000_reg &= PHY_ALL_1000_SPEED;
2096
37f07023 2097 new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);
37f07023
MC		 2098 if ((adv1000_reg != new_adv1000) ||
2099 (adv_reg != new_adv) ||
b6016b76
MC		 2100 ((bmcr & BMCR_ANENABLE) == 0)) {
2101
37f07023
MC		 2102 bnx2_write_phy(bp, bp->mii_adv, new_adv);
2103 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);
ca58c3af 2104 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 2105 BMCR_ANENABLE);
2106 }
2107 else if (bp->link_up) {
2108 /* Flow ctrl may have changed from auto to forced */
2109 /* or vice-versa. */
2110
2111 bnx2_resolve_flow_ctrl(bp);
2112 bnx2_set_mac_link(bp);
2113 }
2114 return 0;
2115 }
2116
d17e53bd
MC		 2117 /* advertise nothing when forcing speed */
2118 if (adv_reg != new_adv)
2119 bnx2_write_phy(bp, bp->mii_adv, new_adv);
2120
b6016b76
MC		 2121 new_bmcr = 0;
2122 if (bp->req_line_speed == SPEED_100) {
2123 new_bmcr |= BMCR_SPEED100;
2124 }
2125 if (bp->req_duplex == DUPLEX_FULL) {
2126 new_bmcr |= BMCR_FULLDPLX;
2127 }
2128 if (new_bmcr != bmcr) {
2129 u32 bmsr;
b6016b76 2130
ca58c3af
MC		 2131 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2132 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 2133
b6016b76
MC		 2134 if (bmsr & BMSR_LSTATUS) {
2135 /* Force link down */
ca58c3af 2136 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 2137 spin_unlock_bh(&bp->phy_lock);
2138 msleep(50);
2139 spin_lock_bh(&bp->phy_lock);
2140
ca58c3af
MC		 2141 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2142 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 2143 }
2144
ca58c3af 2145 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 2146
2147 /* Normally, the new speed is setup after the link has
2148 * gone down and up again. In some cases, link will not go
2149 * down so we need to set up the new speed here.
2150 */
2151 if (bmsr & BMSR_LSTATUS) {
2152 bp->line_speed = bp->req_line_speed;
2153 bp->duplex = bp->req_duplex;
2154 bnx2_resolve_flow_ctrl(bp);
2155 bnx2_set_mac_link(bp);
2156 }
27a005b8
MC		 2157 } else {
2158 bnx2_resolve_flow_ctrl(bp);
2159 bnx2_set_mac_link(bp);
b6016b76
MC		 2160 }
2161 return 0;
2162}
2163
2164static int
0d8a6571 2165bnx2_setup_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 2166__releases(&bp->phy_lock)
2167__acquires(&bp->phy_lock)
b6016b76
MC		 2168{
2169 if (bp->loopback == MAC_LOOPBACK)
2170 return 0;
2171
583c28e5 2172 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
807540ba 2173 return bnx2_setup_serdes_phy(bp, port);
b6016b76
MC		 2174 }
2175 else {
807540ba 2176 return bnx2_setup_copper_phy(bp);
b6016b76
MC		 2177 }
2178}
2179
27a005b8 2180static int
9a120bc5 2181bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 2182{
2183 u32 val;
2184
2185 bp->mii_bmcr = MII_BMCR + 0x10;
2186 bp->mii_bmsr = MII_BMSR + 0x10;
2187 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2188 bp->mii_adv = MII_ADVERTISE + 0x10;
2189 bp->mii_lpa = MII_LPA + 0x10;
2190 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2191
2192 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2193 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2194
2195 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 2196 if (reset_phy)
2197 bnx2_reset_phy(bp);
27a005b8
MC		 2198
2199 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2200
2201 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2202 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2203 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2204 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2205
2206 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2207 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 2208 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 2209 val |= BCM5708S_UP1_2G5;
2210 else
2211 val &= ~BCM5708S_UP1_2G5;
2212 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2213
2214 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2215 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2216 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2217 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2218
2219 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2220
2221 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2222 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2223 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2224
2225 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2226
2227 return 0;
2228}
2229
b6016b76 2230static int
9a120bc5 2231bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 2232{
2233 u32 val;
2234
9a120bc5
MC		 2235 if (reset_phy)
2236 bnx2_reset_phy(bp);
27a005b8
MC		 2237
2238 bp->mii_up1 = BCM5708S_UP1;
2239
5b0c76ad
MC		 2240 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2241 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2242 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2243
2244 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2245 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2246 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2247
2248 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2249 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2250 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2251
583c28e5 2252 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 2253 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2254 val |= BCM5708S_UP1_2G5;
2255 bnx2_write_phy(bp, BCM5708S_UP1, val);
2256 }
2257
4ce45e02
MC		 2258 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||
2259 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||
2260 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) {
5b0c76ad
MC		 2261 /* increase tx signal amplitude */
2262 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2263 BCM5708S_BLK_ADDR_TX_MISC);
2264 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2265 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2266 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2267 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2268 }
2269
2726d6e1 2270 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 2271 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2272
2273 if (val) {
2274 u32 is_backplane;
2275
2726d6e1 2276 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 2277 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2278 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2279 BCM5708S_BLK_ADDR_TX_MISC);
2280 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2281 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2282 BCM5708S_BLK_ADDR_DIG);
2283 }
2284 }
2285 return 0;
2286}
2287
2288static int
9a120bc5 2289bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2290{
9a120bc5
MC		 2291 if (reset_phy)
2292 bnx2_reset_phy(bp);
27a005b8 2293
583c28e5 2294 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 2295
4ce45e02 2296 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
e503e066 2297 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76 2298
e1c6dcca 2299 if (bp->dev->mtu > ETH_DATA_LEN) {
b6016b76
MC		 2300 u32 val;
2301
2302 /* Set extended packet length bit */
2303 bnx2_write_phy(bp, 0x18, 0x7);
2304 bnx2_read_phy(bp, 0x18, &val);
2305 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2306
2307 bnx2_write_phy(bp, 0x1c, 0x6c00);
2308 bnx2_read_phy(bp, 0x1c, &val);
2309 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2310 }
2311 else {
2312 u32 val;
2313
2314 bnx2_write_phy(bp, 0x18, 0x7);
2315 bnx2_read_phy(bp, 0x18, &val);
2316 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2317
2318 bnx2_write_phy(bp, 0x1c, 0x6c00);
2319 bnx2_read_phy(bp, 0x1c, &val);
2320 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2321 }
2322
2323 return 0;
2324}
2325
2326static int
9a120bc5 2327bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2328{
5b0c76ad
MC		 2329 u32 val;
2330
9a120bc5
MC		 2331 if (reset_phy)
2332 bnx2_reset_phy(bp);
27a005b8 2333
583c28e5 2334 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2335 bnx2_write_phy(bp, 0x18, 0x0c00);
2336 bnx2_write_phy(bp, 0x17, 0x000a);
2337 bnx2_write_phy(bp, 0x15, 0x310b);
2338 bnx2_write_phy(bp, 0x17, 0x201f);
2339 bnx2_write_phy(bp, 0x15, 0x9506);
2340 bnx2_write_phy(bp, 0x17, 0x401f);
2341 bnx2_write_phy(bp, 0x15, 0x14e2);
2342 bnx2_write_phy(bp, 0x18, 0x0400);
2343 }
2344
583c28e5 2345 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2346 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2347 MII_BNX2_DSP_EXPAND_REG | 0x8);
2348 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2349 val &= ~(1 << 8);
2350 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2351 }
2352
e1c6dcca 2353 if (bp->dev->mtu > ETH_DATA_LEN) {
b6016b76
MC		 2354 /* Set extended packet length bit */
2355 bnx2_write_phy(bp, 0x18, 0x7);
2356 bnx2_read_phy(bp, 0x18, &val);
2357 bnx2_write_phy(bp, 0x18, val | 0x4000);
2358
2359 bnx2_read_phy(bp, 0x10, &val);
2360 bnx2_write_phy(bp, 0x10, val | 0x1);
2361 }
2362 else {
b6016b76
MC		 2363 bnx2_write_phy(bp, 0x18, 0x7);
2364 bnx2_read_phy(bp, 0x18, &val);
2365 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2366
2367 bnx2_read_phy(bp, 0x10, &val);
2368 bnx2_write_phy(bp, 0x10, val & ~0x1);
2369 }
2370
5b0c76ad 2371 /* ethernet@wirespeed */
41033b65
MC		 2372 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL);
2373 bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val);
2374 val |= AUX_CTL_MISC_CTL_WR | AUX_CTL_MISC_CTL_WIRESPEED;
2375
2376 /* auto-mdix */
2377 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
2378 val |= AUX_CTL_MISC_CTL_AUTOMDIX;
2379
2380 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);
b6016b76
MC		 2381 return 0;
2382}
2383
2384
2385static int
9a120bc5 2386bnx2_init_phy(struct bnx2 *bp, int reset_phy)
52d07b1f
HH		 2387__releases(&bp->phy_lock)
2388__acquires(&bp->phy_lock)
b6016b76
MC		 2389{
2390 u32 val;
2391 int rc = 0;
2392
583c28e5
MC		 2393 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2394 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2395
ca58c3af
MC		 2396 bp->mii_bmcr = MII_BMCR;
2397 bp->mii_bmsr = MII_BMSR;
27a005b8 2398 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2399 bp->mii_adv = MII_ADVERTISE;
2400 bp->mii_lpa = MII_LPA;
2401
e503e066 2402 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
b6016b76 2403
583c28e5 2404 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2405 goto setup_phy;
2406
b6016b76
MC		 2407 bnx2_read_phy(bp, MII_PHYSID1, &val);
2408 bp->phy_id = val << 16;
2409 bnx2_read_phy(bp, MII_PHYSID2, &val);
2410 bp->phy_id |= val & 0xffff;
2411
583c28e5 2412 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
4ce45e02 2413 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
9a120bc5 2414 rc = bnx2_init_5706s_phy(bp, reset_phy);
4ce45e02 2415 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
9a120bc5 2416 rc = bnx2_init_5708s_phy(bp, reset_phy);
4ce45e02 2417 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
9a120bc5 2418 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2419 }
2420 else {
9a120bc5 2421 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2422 }
2423
0d8a6571
MC		 2424setup_phy:
2425 if (!rc)
2426 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2427
2428 return rc;
2429}
2430
2431static int
2432bnx2_set_mac_loopback(struct bnx2 *bp)
2433{
2434 u32 mac_mode;
2435
e503e066 2436 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
b6016b76
MC		 2437 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2438 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
e503e066 2439 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
b6016b76
MC		 2440 bp->link_up = 1;
2441 return 0;
2442}
2443
bc5a0690
MC		 2444static int bnx2_test_link(struct bnx2 *);
2445
2446static int
2447bnx2_set_phy_loopback(struct bnx2 *bp)
2448{
2449 u32 mac_mode;
2450 int rc, i;
2451
2452 spin_lock_bh(&bp->phy_lock);
ca58c3af 2453 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2454 BMCR_SPEED1000);
2455 spin_unlock_bh(&bp->phy_lock);
2456 if (rc)
2457 return rc;
2458
2459 for (i = 0; i < 10; i++) {
2460 if (bnx2_test_link(bp) == 0)
2461 break;
80be4434 2462 msleep(100);
bc5a0690
MC		 2463 }
2464
e503e066 2465 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
bc5a0690
MC		 2466 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2467 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2468 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2469
2470 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
e503e066 2471 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
bc5a0690
MC		 2472 bp->link_up = 1;
2473 return 0;
2474}
2475
ecdbf6e0
JH		 2476static void
2477bnx2_dump_mcp_state(struct bnx2 *bp)
2478{
2479 struct net_device *dev = bp->dev;
2480 u32 mcp_p0, mcp_p1;
2481
2482 netdev_err(dev, "<--- start MCP states dump --->\n");
4ce45e02 2483 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
ecdbf6e0
JH		 2484 mcp_p0 = BNX2_MCP_STATE_P0;
2485 mcp_p1 = BNX2_MCP_STATE_P1;
2486 } else {
2487 mcp_p0 = BNX2_MCP_STATE_P0_5708;
2488 mcp_p1 = BNX2_MCP_STATE_P1_5708;
2489 }
2490 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
2491 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
2492 netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n",
2493 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),
2494 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),
2495 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));
2496 netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n",
2497 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2498 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2499 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));
2500 netdev_err(dev, "DEBUG: shmem states:\n");
2501 netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]",
2502 bnx2_shmem_rd(bp, BNX2_DRV_MB),
2503 bnx2_shmem_rd(bp, BNX2_FW_MB),
2504 bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
2505 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
2506 netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]",
2507 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
2508 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
2509 pr_cont(" condition[%08x]\n",
2510 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
13e63517 2511 DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);
ecdbf6e0
JH		 2512 DP_SHMEM_LINE(bp, 0x3cc);
2513 DP_SHMEM_LINE(bp, 0x3dc);
2514 DP_SHMEM_LINE(bp, 0x3ec);
2515 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
2516 netdev_err(dev, "<--- end MCP states dump --->\n");
2517}
2518
b6016b76 2519static int
a2f13890 2520bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
b6016b76
MC		 2521{
2522 int i;
2523 u32 val;
2524
b6016b76
MC		 2525 bp->fw_wr_seq++;
2526 msg_data |= bp->fw_wr_seq;
a8d9bc2e 2527 bp->fw_last_msg = msg_data;
b6016b76 2528
2726d6e1 2529 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2530
a2f13890
MC		 2531 if (!ack)
2532 return 0;
2533
b6016b76 2534 /* wait for an acknowledgement. */
40105c0b 2535 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
b090ae2b 2536 msleep(10);
b6016b76 2537
2726d6e1 2538 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2539
2540 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2541 break;
2542 }
b090ae2b
MC		 2543 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2544 return 0;
b6016b76
MC		 2545
2546 /* If we timed out, inform the firmware that this is the case. */
b090ae2b 2547 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
b6016b76
MC		 2548 msg_data &= ~BNX2_DRV_MSG_CODE;
2549 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2550
2726d6e1 2551 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
ecdbf6e0
JH		 2552 if (!silent) {
2553 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2554 bnx2_dump_mcp_state(bp);
2555 }
b6016b76 2556
b6016b76
MC		 2557 return -EBUSY;
2558 }
2559
b090ae2b
MC		 2560 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2561 return -EIO;
2562
b6016b76
MC		 2563 return 0;
2564}
2565
59b47d8a
MC		 2566static int
2567bnx2_init_5709_context(struct bnx2 *bp)
2568{
2569 int i, ret = 0;
2570 u32 val;
2571
2572 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2bc4078e 2573 val |= (BNX2_PAGE_BITS - 8) << 16;
e503e066 2574 BNX2_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5 2575 for (i = 0; i < 10; i++) {
e503e066 2576 val = BNX2_RD(bp, BNX2_CTX_COMMAND);
641bdcd5
MC		 2577 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2578 break;
2579 udelay(2);
2580 }
2581 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2582 return -EBUSY;
2583
59b47d8a
MC		 2584 for (i = 0; i < bp->ctx_pages; i++) {
2585 int j;
2586
352f7687 2587 if (bp->ctx_blk[i])
2bc4078e 2588 memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE);
352f7687
MC		 2589 else
2590 return -ENOMEM;
2591
e503e066
MC		 2592 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2593 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2594 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2595 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2596 (u64) bp->ctx_blk_mapping[i] >> 32);
2597 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2598 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
59b47d8a
MC		 2599 for (j = 0; j < 10; j++) {
2600
e503e066 2601 val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
59b47d8a
MC		 2602 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2603 break;
2604 udelay(5);
2605 }
2606 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2607 ret = -EBUSY;
2608 break;
2609 }
2610 }
2611 return ret;
2612}
2613
b6016b76
MC		 2614static void
2615bnx2_init_context(struct bnx2 *bp)
2616{
2617 u32 vcid;
2618
2619 vcid = 96;
2620 while (vcid) {
2621 u32 vcid_addr, pcid_addr, offset;
7947b20e 2622 int i;
b6016b76
MC		 2623
2624 vcid--;
2625
4ce45e02 2626 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
b6016b76
MC		 2627 u32 new_vcid;
2628
2629 vcid_addr = GET_PCID_ADDR(vcid);
2630 if (vcid & 0x8) {
2631 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2632 }
2633 else {
2634 new_vcid = vcid;
2635 }
2636 pcid_addr = GET_PCID_ADDR(new_vcid);
2637 }
2638 else {
2639 vcid_addr = GET_CID_ADDR(vcid);
2640 pcid_addr = vcid_addr;
2641 }
2642
7947b20e
MC		 2643 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2644 vcid_addr += (i << PHY_CTX_SHIFT);
2645 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2646
e503e066
MC		 2647 BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2648 BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2649
7947b20e
MC		 2650 /* Zero out the context. */
2651 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2652 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2653 }
b6016b76
MC		 2654 }
2655}
2656
2657static int
2658bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2659{
2660 u16 *good_mbuf;
2661 u32 good_mbuf_cnt;
2662 u32 val;
2663
6da2ec56 2664 good_mbuf = kmalloc_array(512, sizeof(u16), GFP_KERNEL);
b8aac410 2665 if (!good_mbuf)
b6016b76 2666 return -ENOMEM;
b6016b76 2667
e503e066 2668 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
b6016b76
MC		 2669 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2670
2671 good_mbuf_cnt = 0;
2672
2673 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2674 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2675 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2676 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2677 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2678
2726d6e1 2679 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2680
2681 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2682
2683 /* The addresses with Bit 9 set are bad memory blocks. */
2684 if (!(val & (1 << 9))) {
2685 good_mbuf[good_mbuf_cnt] = (u16) val;
2686 good_mbuf_cnt++;
2687 }
2688
2726d6e1 2689 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2690 }
2691
2692 /* Free the good ones back to the mbuf pool thus discarding
2693 * all the bad ones. */
2694 while (good_mbuf_cnt) {
2695 good_mbuf_cnt--;
2696
2697 val = good_mbuf[good_mbuf_cnt];
2698 val = (val << 9) | val | 1;
2699
2726d6e1 2700 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2701 }
2702 kfree(good_mbuf);
2703 return 0;
2704}
2705
2706static void
5fcaed01 2707bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
b6016b76
MC		 2708{
2709 u32 val;
b6016b76
MC		 2710
2711 val = (mac_addr[0] << 8) | mac_addr[1];
2712
e503e066 2713 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
b6016b76 2714
6aa20a22 2715 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2716 (mac_addr[4] << 8) | mac_addr[5];
2717
e503e066 2718 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
b6016b76
MC		 2719}
2720
47bf4246 2721static inline int
a2df00aa 2722bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
47bf4246
MC		 2723{
2724 dma_addr_t mapping;
2bc4078e
MC		 2725 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2726 struct bnx2_rx_bd *rxbd =
2727 &rxr->rx_pg_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)];
a2df00aa 2728 struct page *page = alloc_page(gfp);
47bf4246
MC		 2729
2730 if (!page)
2731 return -ENOMEM;
36227e88 2732 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
47bf4246 2733 PCI_DMA_FROMDEVICE);
36227e88 2734 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 2735 __free_page(page);
2736 return -EIO;
2737 }
2738
47bf4246 2739 rx_pg->page = page;
1a4ccc2d 2740 dma_unmap_addr_set(rx_pg, mapping, mapping);
47bf4246
MC		 2741 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2742 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2743 return 0;
2744}
2745
2746static void
bb4f98ab 2747bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246 2748{
2bc4078e 2749 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246
MC		 2750 struct page *page = rx_pg->page;
2751
2752 if (!page)
2753 return;
2754
36227e88
SG		 2755 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2756 PAGE_SIZE, PCI_DMA_FROMDEVICE);
47bf4246
MC		 2757
2758 __free_page(page);
2759 rx_pg->page = NULL;
2760}
2761
b6016b76 2762static inline int
dd2bc8e9 2763bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
b6016b76 2764{
dd2bc8e9 2765 u8 *data;
2bc4078e 2766 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[index];
b6016b76 2767 dma_addr_t mapping;
2bc4078e
MC		 2768 struct bnx2_rx_bd *rxbd =
2769 &rxr->rx_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)];
b6016b76 2770
dd2bc8e9
ED		 2771 data = kmalloc(bp->rx_buf_size, gfp);
2772 if (!data)
b6016b76 2773 return -ENOMEM;
b6016b76 2774
dd2bc8e9
ED		 2775 mapping = dma_map_single(&bp->pdev->dev,
2776 get_l2_fhdr(data),
2777 bp->rx_buf_use_size,
36227e88
SG		 2778 PCI_DMA_FROMDEVICE);
2779 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
dd2bc8e9 2780 kfree(data);
3d16af86
BL		 2781 return -EIO;
2782 }
b6016b76 2783
dd2bc8e9 2784 rx_buf->data = data;
1a4ccc2d 2785 dma_unmap_addr_set(rx_buf, mapping, mapping);
b6016b76
MC		 2786
2787 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2788 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2789
bb4f98ab 2790 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2791
2792 return 0;
2793}
2794
da3e4fbe 2795static int
35efa7c1 2796bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2797{
43e80b89 2798 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76 2799 u32 new_link_state, old_link_state;
da3e4fbe 2800 int is_set = 1;
b6016b76 2801
da3e4fbe
MC		 2802 new_link_state = sblk->status_attn_bits & event;
2803 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2804 if (new_link_state != old_link_state) {
da3e4fbe 2805 if (new_link_state)
e503e066 2806 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
da3e4fbe 2807 else
e503e066 2808 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
da3e4fbe
MC		 2809 } else
2810 is_set = 0;
2811
2812 return is_set;
2813}
2814
2815static void
35efa7c1 2816bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2817{
74ecc62d
MC		 2818 spin_lock(&bp->phy_lock);
2819
2820 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2821 bnx2_set_link(bp);
35efa7c1 2822 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2823 bnx2_set_remote_link(bp);
2824
74ecc62d
MC		 2825 spin_unlock(&bp->phy_lock);
2826
b6016b76
MC		 2827}
2828
ead7270b 2829static inline u16
35efa7c1 2830bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2831{
2832 u16 cons;
2833
b668534c
ED		 2834 cons = READ_ONCE(*bnapi->hw_tx_cons_ptr);
2835
2bc4078e 2836 if (unlikely((cons & BNX2_MAX_TX_DESC_CNT) == BNX2_MAX_TX_DESC_CNT))
ead7270b
MC		 2837 cons++;
2838 return cons;
2839}
2840
57851d84
MC		 2841static int
2842bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2843{
35e9010b 2844 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
b6016b76 2845 u16 hw_cons, sw_cons, sw_ring_cons;
706bf240 2846 int tx_pkt = 0, index;
e9831909 2847 unsigned int tx_bytes = 0;
706bf240
BL		 2848 struct netdev_queue *txq;
2849
2850 index = (bnapi - bp->bnx2_napi);
2851 txq = netdev_get_tx_queue(bp->dev, index);
b6016b76 2852
35efa7c1 2853 hw_cons = bnx2_get_hw_tx_cons(bnapi);
35e9010b 2854 sw_cons = txr->tx_cons;
b6016b76
MC		 2855
2856 while (sw_cons != hw_cons) {
2bc4078e 2857 struct bnx2_sw_tx_bd *tx_buf;
b6016b76
MC		 2858 struct sk_buff *skb;
2859 int i, last;
2860
2bc4078e 2861 sw_ring_cons = BNX2_TX_RING_IDX(sw_cons);
b6016b76 2862
35e9010b 2863 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
b6016b76 2864 skb = tx_buf->skb;
1d39ed56 2865
d62fda08
ED		 2866 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2867 prefetch(&skb->end);
2868
b6016b76 2869 /* partial BD completions possible with TSO packets */
d62fda08 2870 if (tx_buf->is_gso) {
b6016b76
MC		 2871 u16 last_idx, last_ring_idx;
2872
d62fda08
ED		 2873 last_idx = sw_cons + tx_buf->nr_frags + 1;
2874 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2bc4078e 2875 if (unlikely(last_ring_idx >= BNX2_MAX_TX_DESC_CNT)) {
b6016b76
MC		 2876 last_idx++;
2877 }
2878 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2879 break;
2880 }
2881 }
1d39ed56 2882
36227e88 2883 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7 2884 skb_headlen(skb), PCI_DMA_TODEVICE);
b6016b76
MC		 2885
2886 tx_buf->skb = NULL;
d62fda08 2887 last = tx_buf->nr_frags;
b6016b76
MC		 2888
2889 for (i = 0; i < last; i++) {
2bc4078e 2890 struct bnx2_sw_tx_bd *tx_buf;
e95524a7 2891
2bc4078e
MC		 2892 sw_cons = BNX2_NEXT_TX_BD(sw_cons);
2893
2894 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(sw_cons)];
36227e88 2895 dma_unmap_page(&bp->pdev->dev,
2bc4078e 2896 dma_unmap_addr(tx_buf, mapping),
9e903e08 2897 skb_frag_size(&skb_shinfo(skb)->frags[i]),
e95524a7 2898 PCI_DMA_TODEVICE);
b6016b76
MC		 2899 }
2900
2bc4078e 2901 sw_cons = BNX2_NEXT_TX_BD(sw_cons);
b6016b76 2902
e9831909 2903 tx_bytes += skb->len;
f458b2ee 2904 dev_kfree_skb_any(skb);
57851d84
MC		 2905 tx_pkt++;
2906 if (tx_pkt == budget)
2907 break;
b6016b76 2908
d62fda08
ED		 2909 if (hw_cons == sw_cons)
2910 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2911 }
2912
e9831909 2913 netdev_tx_completed_queue(txq, tx_pkt, tx_bytes);
35e9010b
MC		 2914 txr->hw_tx_cons = hw_cons;
2915 txr->tx_cons = sw_cons;
706bf240 2916
2f8af120 2917 /* Need to make the tx_cons update visible to bnx2_start_xmit()
706bf240 2918 * before checking for netif_tx_queue_stopped(). Without the
2f8af120
MC		 2919 * memory barrier, there is a small possibility that bnx2_start_xmit()
2920 * will miss it and cause the queue to be stopped forever.
2921 */
2922 smp_mb();
b6016b76 2923
706bf240 2924 if (unlikely(netif_tx_queue_stopped(txq)) &&
35e9010b 2925 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
706bf240
BL		 2926 __netif_tx_lock(txq, smp_processor_id());
2927 if ((netif_tx_queue_stopped(txq)) &&
35e9010b 2928 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
706bf240
BL		 2929 netif_tx_wake_queue(txq);
2930 __netif_tx_unlock(txq);
b6016b76 2931 }
706bf240 2932
57851d84 2933 return tx_pkt;
b6016b76
MC		 2934}
2935
1db82f2a 2936static void
bb4f98ab 2937bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
a1f60190 2938 struct sk_buff *skb, int count)
1db82f2a 2939{
2bc4078e
MC		 2940 struct bnx2_sw_pg *cons_rx_pg, *prod_rx_pg;
2941 struct bnx2_rx_bd *cons_bd, *prod_bd;
1db82f2a 2942 int i;
3d16af86 2943 u16 hw_prod, prod;
bb4f98ab 2944 u16 cons = rxr->rx_pg_cons;
1db82f2a 2945
3d16af86
BL		 2946 cons_rx_pg = &rxr->rx_pg_ring[cons];
2947
2948 /* The caller was unable to allocate a new page to replace the
2949 * last one in the frags array, so we need to recycle that page
2950 * and then free the skb.
2951 */
2952 if (skb) {
2953 struct page *page;
2954 struct skb_shared_info *shinfo;
2955
2956 shinfo = skb_shinfo(skb);
2957 shinfo->nr_frags--;
b7b6a688
IC		 2958 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]);
2959 __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL);
3d16af86
BL		 2960
2961 cons_rx_pg->page = page;
2962 dev_kfree_skb(skb);
2963 }
2964
2965 hw_prod = rxr->rx_pg_prod;
2966
1db82f2a 2967 for (i = 0; i < count; i++) {
2bc4078e 2968 prod = BNX2_RX_PG_RING_IDX(hw_prod);
1db82f2a 2969
bb4f98ab
MC		 2970 prod_rx_pg = &rxr->rx_pg_ring[prod];
2971 cons_rx_pg = &rxr->rx_pg_ring[cons];
2bc4078e
MC		 2972 cons_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(cons)]
2973 [BNX2_RX_IDX(cons)];
2974 prod_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(prod)]
2975 [BNX2_RX_IDX(prod)];
1db82f2a 2976
1db82f2a
MC		 2977 if (prod != cons) {
2978 prod_rx_pg->page = cons_rx_pg->page;
2979 cons_rx_pg->page = NULL;
1a4ccc2d
FT		 2980 dma_unmap_addr_set(prod_rx_pg, mapping,
2981 dma_unmap_addr(cons_rx_pg, mapping));
1db82f2a
MC		 2982
2983 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2984 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2985
2986 }
2bc4078e
MC		 2987 cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(cons));
2988 hw_prod = BNX2_NEXT_RX_BD(hw_prod);
1db82f2a 2989 }
bb4f98ab
MC		 2990 rxr->rx_pg_prod = hw_prod;
2991 rxr->rx_pg_cons = cons;
1db82f2a
MC		 2992}
2993
b6016b76 2994static inline void
dd2bc8e9
ED		 2995bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2996 u8 *data, u16 cons, u16 prod)
b6016b76 2997{
2bc4078e
MC		 2998 struct bnx2_sw_bd *cons_rx_buf, *prod_rx_buf;
2999 struct bnx2_rx_bd *cons_bd, *prod_bd;
236b6394 3000
bb4f98ab
MC		 3001 cons_rx_buf = &rxr->rx_buf_ring[cons];
3002 prod_rx_buf = &rxr->rx_buf_ring[prod];
b6016b76 3003
36227e88 3004 dma_sync_single_for_device(&bp->pdev->dev,
1a4ccc2d 3005 dma_unmap_addr(cons_rx_buf, mapping),
601d3d18 3006 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 3007
bb4f98ab 3008 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 3009
dd2bc8e9 3010 prod_rx_buf->data = data;
b6016b76 3011
236b6394
MC		 3012 if (cons == prod)
3013 return;
b6016b76 3014
1a4ccc2d
FT		 3015 dma_unmap_addr_set(prod_rx_buf, mapping,
3016 dma_unmap_addr(cons_rx_buf, mapping));
236b6394 3017
2bc4078e
MC		 3018 cons_bd = &rxr->rx_desc_ring[BNX2_RX_RING(cons)][BNX2_RX_IDX(cons)];
3019 prod_bd = &rxr->rx_desc_ring[BNX2_RX_RING(prod)][BNX2_RX_IDX(prod)];
236b6394
MC		 3020 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
3021 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 3022}
3023
dd2bc8e9
ED		 3024static struct sk_buff *
3025bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,
a1f60190
MC		 3026 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
3027 u32 ring_idx)
85833c62
MC		 3028{
3029 int err;
3030 u16 prod = ring_idx & 0xffff;
dd2bc8e9 3031 struct sk_buff *skb;
85833c62 3032
dd2bc8e9 3033 err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
85833c62 3034 if (unlikely(err)) {
dd2bc8e9
ED		 3035 bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);
3036error:
1db82f2a
MC		 3037 if (hdr_len) {
3038 unsigned int raw_len = len + 4;
3039 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
3040
bb4f98ab 3041 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
1db82f2a 3042 }
dd2bc8e9 3043 return NULL;
85833c62
MC		 3044 }
3045
36227e88 3046 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
85833c62 3047 PCI_DMA_FROMDEVICE);
d3836f21 3048 skb = build_skb(data, 0);
dd2bc8e9
ED		 3049 if (!skb) {
3050 kfree(data);
3051 goto error;
3052 }
3053 skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET);
1db82f2a
MC		 3054 if (hdr_len == 0) {
3055 skb_put(skb, len);
dd2bc8e9 3056 return skb;
1db82f2a
MC		 3057 } else {
3058 unsigned int i, frag_len, frag_size, pages;
2bc4078e 3059 struct bnx2_sw_pg *rx_pg;
bb4f98ab
MC		 3060 u16 pg_cons = rxr->rx_pg_cons;
3061 u16 pg_prod = rxr->rx_pg_prod;
1db82f2a
MC		 3062
3063 frag_size = len + 4 - hdr_len;
3064 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3065 skb_put(skb, hdr_len);
3066
3067 for (i = 0; i < pages; i++) {
3d16af86
BL		 3068 dma_addr_t mapping_old;
3069
1db82f2a
MC		 3070 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3071 if (unlikely(frag_len <= 4)) {
3072 unsigned int tail = 4 - frag_len;
3073
bb4f98ab
MC		 3074 rxr->rx_pg_cons = pg_cons;
3075 rxr->rx_pg_prod = pg_prod;
3076 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
a1f60190 3077 pages - i);
1db82f2a
MC		 3078 skb->len -= tail;
3079 if (i == 0) {
3080 skb->tail -= tail;
3081 } else {
3082 skb_frag_t *frag =
3083 &skb_shinfo(skb)->frags[i - 1];
9e903e08 3084 skb_frag_size_sub(frag, tail);
1db82f2a 3085 skb->data_len -= tail;
1db82f2a 3086 }
dd2bc8e9 3087 return skb;
1db82f2a 3088 }
bb4f98ab 3089 rx_pg = &rxr->rx_pg_ring[pg_cons];
1db82f2a 3090
3d16af86
BL		 3091 /* Don't unmap yet. If we're unable to allocate a new
3092 * page, we need to recycle the page and the DMA addr.
3093 */
1a4ccc2d 3094 mapping_old = dma_unmap_addr(rx_pg, mapping);
1db82f2a
MC		 3095 if (i == pages - 1)
3096 frag_len -= 4;
3097
3098 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3099 rx_pg->page = NULL;
3100
bb4f98ab 3101 err = bnx2_alloc_rx_page(bp, rxr,
2bc4078e 3102 BNX2_RX_PG_RING_IDX(pg_prod),
a2df00aa 3103 GFP_ATOMIC);
1db82f2a 3104 if (unlikely(err)) {
bb4f98ab
MC		 3105 rxr->rx_pg_cons = pg_cons;
3106 rxr->rx_pg_prod = pg_prod;
3107 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
a1f60190 3108 pages - i);
dd2bc8e9 3109 return NULL;
1db82f2a
MC		 3110 }
3111
36227e88 3112 dma_unmap_page(&bp->pdev->dev, mapping_old,
3d16af86
BL		 3113 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3114
1db82f2a
MC		 3115 frag_size -= frag_len;
3116 skb->data_len += frag_len;
a1f4e8bc 3117 skb->truesize += PAGE_SIZE;
1db82f2a
MC		 3118 skb->len += frag_len;
3119
2bc4078e
MC		 3120 pg_prod = BNX2_NEXT_RX_BD(pg_prod);
3121 pg_cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(pg_cons));
1db82f2a 3122 }
bb4f98ab
MC		 3123 rxr->rx_pg_prod = pg_prod;
3124 rxr->rx_pg_cons = pg_cons;
1db82f2a 3125 }
dd2bc8e9 3126 return skb;
85833c62
MC		 3127}
3128
c09c2627 3129static inline u16
35efa7c1 3130bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 3131{
bb4f98ab
MC		 3132 u16 cons;
3133
b668534c
ED		 3134 cons = READ_ONCE(*bnapi->hw_rx_cons_ptr);
3135
2bc4078e 3136 if (unlikely((cons & BNX2_MAX_RX_DESC_CNT) == BNX2_MAX_RX_DESC_CNT))
c09c2627
MC		 3137 cons++;
3138 return cons;
3139}
3140
b6016b76 3141static int
35efa7c1 3142bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 3143{
bb4f98ab 3144 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76
MC		 3145 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3146 struct l2_fhdr *rx_hdr;
1db82f2a 3147 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 3148
310c4d4e
EB		 3149 if (budget <= 0)
3150 return rx_pkt;
3151
35efa7c1 3152 hw_cons = bnx2_get_hw_rx_cons(bnapi);
bb4f98ab
MC		 3153 sw_cons = rxr->rx_cons;
3154 sw_prod = rxr->rx_prod;
b6016b76
MC		 3155
3156 /* Memory barrier necessary as speculative reads of the rx
3157 * buffer can be ahead of the index in the status block
3158 */
3159 rmb();
3160 while (sw_cons != hw_cons) {
1db82f2a 3161 unsigned int len, hdr_len;
ade2bfe7 3162 u32 status;
2bc4078e 3163 struct bnx2_sw_bd *rx_buf, *next_rx_buf;
b6016b76 3164 struct sk_buff *skb;
236b6394 3165 dma_addr_t dma_addr;
dd2bc8e9 3166 u8 *data;
2bc4078e 3167 u16 next_ring_idx;
b6016b76 3168
2bc4078e
MC		 3169 sw_ring_cons = BNX2_RX_RING_IDX(sw_cons);
3170 sw_ring_prod = BNX2_RX_RING_IDX(sw_prod);
b6016b76 3171
bb4f98ab 3172 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
dd2bc8e9
ED		 3173 data = rx_buf->data;
3174 rx_buf->data = NULL;
aabef8b2 3175
dd2bc8e9
ED		 3176 rx_hdr = get_l2_fhdr(data);
3177 prefetch(rx_hdr);
236b6394 3178
1a4ccc2d 3179 dma_addr = dma_unmap_addr(rx_buf, mapping);
236b6394 3180
36227e88 3181 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
601d3d18
BL		 3182 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3183 PCI_DMA_FROMDEVICE);
b6016b76 3184
2bc4078e
MC		 3185 next_ring_idx = BNX2_RX_RING_IDX(BNX2_NEXT_RX_BD(sw_cons));
3186 next_rx_buf = &rxr->rx_buf_ring[next_ring_idx];
dd2bc8e9
ED		 3187 prefetch(get_l2_fhdr(next_rx_buf->data));
3188
1db82f2a 3189 len = rx_hdr->l2_fhdr_pkt_len;
990ec380 3190 status = rx_hdr->l2_fhdr_status;
b6016b76 3191
1db82f2a
MC		 3192 hdr_len = 0;
3193 if (status & L2_FHDR_STATUS_SPLIT) {
3194 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3195 pg_ring_used = 1;
3196 } else if (len > bp->rx_jumbo_thresh) {
3197 hdr_len = bp->rx_jumbo_thresh;
3198 pg_ring_used = 1;
3199 }
3200
990ec380
MC		 3201 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3202 L2_FHDR_ERRORS_PHY_DECODE |
3203 L2_FHDR_ERRORS_ALIGNMENT |
3204 L2_FHDR_ERRORS_TOO_SHORT |
3205 L2_FHDR_ERRORS_GIANT_FRAME))) {
3206
dd2bc8e9 3207 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
990ec380
MC		 3208 sw_ring_prod);
3209 if (pg_ring_used) {
3210 int pages;
3211
3212 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3213
3214 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3215 }
3216 goto next_rx;
3217 }
3218
1db82f2a 3219 len -= 4;
b6016b76 3220
5d5d0015 3221 if (len <= bp->rx_copy_thresh) {
dd2bc8e9 3222 skb = netdev_alloc_skb(bp->dev, len + 6);
b8aac410 3223 if (!skb) {
dd2bc8e9 3224 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
85833c62
MC		 3225 sw_ring_prod);
3226 goto next_rx;
3227 }
b6016b76
MC		 3228
3229 /* aligned copy */
dd2bc8e9
ED		 3230 memcpy(skb->data,
3231 (u8 *)rx_hdr + BNX2_RX_OFFSET - 6,
3232 len + 6);
3233 skb_reserve(skb, 6);
3234 skb_put(skb, len);
b6016b76 3235
dd2bc8e9 3236 bnx2_reuse_rx_data(bp, rxr, data,
b6016b76
MC		 3237 sw_ring_cons, sw_ring_prod);
3238
dd2bc8e9
ED		 3239 } else {
3240 skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,
3241 (sw_ring_cons << 16) | sw_ring_prod);
3242 if (!skb)
3243 goto next_rx;
3244 }
f22828e8 3245 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
7d0fd211 3246 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
86a9bad3 3247 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rx_hdr->l2_fhdr_vlan_tag);
f22828e8 3248
b6016b76
MC		 3249 skb->protocol = eth_type_trans(skb, bp->dev);
3250
1b0ecb28
VY		 3251 if (len > (bp->dev->mtu + ETH_HLEN) &&
3252 skb->protocol != htons(0x8100) &&
3253 skb->protocol != htons(ETH_P_8021AD)) {
b6016b76 3254
745720e5 3255 dev_kfree_skb(skb);
b6016b76
MC		 3256 goto next_rx;
3257
3258 }
3259
bc8acf2c 3260 skb_checksum_none_assert(skb);
8d7dfc2b 3261 if ((bp->dev->features & NETIF_F_RXCSUM) &&
b6016b76
MC		 3262 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3263 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3264
ade2bfe7
MC		 3265 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3266 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 3267 skb->ip_summed = CHECKSUM_UNNECESSARY;
3268 }
fdc8541d
MC		 3269 if ((bp->dev->features & NETIF_F_RXHASH) &&
3270 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3271 L2_FHDR_STATUS_USE_RXHASH))
cf1bfd6a
TH		 3272 skb_set_hash(skb, rx_hdr->l2_fhdr_hash,
3273 PKT_HASH_TYPE_L3);
b6016b76 3274
0c8dfc83 3275 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
7d0fd211 3276 napi_gro_receive(&bnapi->napi, skb);
b6016b76
MC		 3277 rx_pkt++;
3278
3279next_rx:
2bc4078e
MC		 3280 sw_cons = BNX2_NEXT_RX_BD(sw_cons);
3281 sw_prod = BNX2_NEXT_RX_BD(sw_prod);
b6016b76 3282
6dc5aa21 3283 if (rx_pkt == budget)
b6016b76 3284 break;
f4e418f7
MC		 3285
3286 /* Refresh hw_cons to see if there is new work */
3287 if (sw_cons == hw_cons) {
35efa7c1 3288 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 3289 rmb();
3290 }
b6016b76 3291 }
bb4f98ab
MC		 3292 rxr->rx_cons = sw_cons;
3293 rxr->rx_prod = sw_prod;
b6016b76 3294
1db82f2a 3295 if (pg_ring_used)
e503e066 3296 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
1db82f2a 3297
e503e066 3298 BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod);
b6016b76 3299
e503e066 3300 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76 3301
b6016b76
MC		 3302 return rx_pkt;
3303
3304}
3305
3306/* MSI ISR - The only difference between this and the INTx ISR
3307 * is that the MSI interrupt is always serviced.
3308 */
3309static irqreturn_t
7d12e780 3310bnx2_msi(int irq, void *dev_instance)
b6016b76 3311{
f0ea2e63
MC		 3312 struct bnx2_napi *bnapi = dev_instance;
3313 struct bnx2 *bp = bnapi->bp;
b6016b76 3314
43e80b89 3315 prefetch(bnapi->status_blk.msi);
e503e066 3316 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
b6016b76
MC		 3317 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3318 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3319
3320 /* Return here if interrupt is disabled. */
73eef4cd
MC		 3321 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3322 return IRQ_HANDLED;
b6016b76 3323
288379f0 3324 napi_schedule(&bnapi->napi);
b6016b76 3325
73eef4cd 3326 return IRQ_HANDLED;
b6016b76
MC		 3327}
3328
8e6a72c4
MC		 3329static irqreturn_t
3330bnx2_msi_1shot(int irq, void *dev_instance)
3331{
f0ea2e63
MC		 3332 struct bnx2_napi *bnapi = dev_instance;
3333 struct bnx2 *bp = bnapi->bp;
8e6a72c4 3334
43e80b89 3335 prefetch(bnapi->status_blk.msi);
8e6a72c4
MC		 3336
3337 /* Return here if interrupt is disabled. */
3338 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3339 return IRQ_HANDLED;
3340
288379f0 3341 napi_schedule(&bnapi->napi);
8e6a72c4
MC		 3342
3343 return IRQ_HANDLED;
3344}
3345
b6016b76 3346static irqreturn_t
7d12e780 3347bnx2_interrupt(int irq, void *dev_instance)
b6016b76 3348{
f0ea2e63
MC		 3349 struct bnx2_napi *bnapi = dev_instance;
3350 struct bnx2 *bp = bnapi->bp;
43e80b89 3351 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76
MC		 3352
3353 /* When using INTx, it is possible for the interrupt to arrive
3354 * at the CPU before the status block posted prior to the
3355 * interrupt. Reading a register will flush the status block.
3356 * When using MSI, the MSI message will always complete after
3357 * the status block write.
3358 */
35efa7c1 3359 if ((sblk->status_idx == bnapi->last_status_idx) &&
e503e066 3360 (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &
b6016b76 3361 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 3362 return IRQ_NONE;
b6016b76 3363
e503e066 3364 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
b6016b76
MC		 3365 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3366 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3367
b8a7ce7b
MC		 3368 /* Read back to deassert IRQ immediately to avoid too many
3369 * spurious interrupts.
3370 */
e503e066 3371 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
b8a7ce7b 3372
b6016b76 3373 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 3374 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3375 return IRQ_HANDLED;
b6016b76 3376
288379f0 3377 if (napi_schedule_prep(&bnapi->napi)) {
35efa7c1 3378 bnapi->last_status_idx = sblk->status_idx;
288379f0 3379 __napi_schedule(&bnapi->napi);
b8a7ce7b 3380 }
b6016b76 3381
73eef4cd 3382 return IRQ_HANDLED;
b6016b76
MC		 3383}
3384
f4e418f7 3385static inline int
43e80b89 3386bnx2_has_fast_work(struct bnx2_napi *bnapi)
f4e418f7 3387{
35e9010b 3388 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 3389 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
f4e418f7 3390
bb4f98ab 3391 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
35e9010b 3392 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
f4e418f7 3393 return 1;
43e80b89
MC		 3394 return 0;
3395}
3396
3397#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3398 STATUS_ATTN_BITS_TIMER_ABORT)
3399
3400static inline int
3401bnx2_has_work(struct bnx2_napi *bnapi)
3402{
3403 struct status_block *sblk = bnapi->status_blk.msi;
3404
3405 if (bnx2_has_fast_work(bnapi))
3406 return 1;
f4e418f7 3407
4edd473f
MC		 3408#ifdef BCM_CNIC
3409 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3410 return 1;
3411#endif
3412
da3e4fbe
MC		 3413 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3414 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3415 return 1;
3416
3417 return 0;
3418}
3419
efba0180
MC		 3420static void
3421bnx2_chk_missed_msi(struct bnx2 *bp)
3422{
3423 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3424 u32 msi_ctrl;
3425
3426 if (bnx2_has_work(bnapi)) {
e503e066 3427 msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);
efba0180
MC		 3428 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3429 return;
3430
3431 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
e503e066
MC		 3432 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3433 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3434 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
efba0180
MC		 3435 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3436 }
3437 }
3438
3439 bp->idle_chk_status_idx = bnapi->last_status_idx;
3440}
3441
4edd473f
MC		 3442#ifdef BCM_CNIC
3443static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3444{
3445 struct cnic_ops *c_ops;
3446
3447 if (!bnapi->cnic_present)
3448 return;
3449
3450 rcu_read_lock();
3451 c_ops = rcu_dereference(bp->cnic_ops);
3452 if (c_ops)
3453 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3454 bnapi->status_blk.msi);
3455 rcu_read_unlock();
3456}
3457#endif
3458
43e80b89 3459static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
b6016b76 3460{
43e80b89 3461 struct status_block *sblk = bnapi->status_blk.msi;
da3e4fbe
MC		 3462 u32 status_attn_bits = sblk->status_attn_bits;
3463 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3464
da3e4fbe
MC		 3465 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3466 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3467
35efa7c1 3468 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3469
3470 /* This is needed to take care of transient status
3471 * during link changes.
3472 */
e503e066
MC		 3473 BNX2_WR(bp, BNX2_HC_COMMAND,
3474 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3475 BNX2_RD(bp, BNX2_HC_COMMAND);
b6016b76 3476 }
43e80b89
MC		 3477}
3478
3479static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3480 int work_done, int budget)
3481{
3482 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3483 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76 3484
35e9010b 3485 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
57851d84 3486 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3487
bb4f98ab 3488 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
35efa7c1 3489 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3490
6f535763
DM		 3491 return work_done;
3492}
3493
f0ea2e63
MC		 3494static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3495{
3496 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3497 struct bnx2 *bp = bnapi->bp;
3498 int work_done = 0;
3499 struct status_block_msix *sblk = bnapi->status_blk.msix;
3500
3501 while (1) {
3502 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3503 if (unlikely(work_done >= budget))
3504 break;
3505
3506 bnapi->last_status_idx = sblk->status_idx;
3507 /* status idx must be read before checking for more work. */
3508 rmb();
3509 if (likely(!bnx2_has_fast_work(bnapi))) {
3510
6ad20165 3511 napi_complete_done(napi, work_done);
e503e066
MC		 3512 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3513 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3514 bnapi->last_status_idx);
f0ea2e63
MC		 3515 break;
3516 }
3517 }
3518 return work_done;
3519}
3520
6f535763
DM		 3521static int bnx2_poll(struct napi_struct *napi, int budget)
3522{
35efa7c1
MC		 3523 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3524 struct bnx2 *bp = bnapi->bp;
6f535763 3525 int work_done = 0;
43e80b89 3526 struct status_block *sblk = bnapi->status_blk.msi;
6f535763
DM		 3527
3528 while (1) {
43e80b89
MC		 3529 bnx2_poll_link(bp, bnapi);
3530
35efa7c1 3531 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3532
4edd473f
MC		 3533#ifdef BCM_CNIC
3534 bnx2_poll_cnic(bp, bnapi);
3535#endif
3536
35efa7c1 3537 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3538 * much work has been processed, so we must read it before
3539 * checking for more work.
3540 */
35efa7c1 3541 bnapi->last_status_idx = sblk->status_idx;
efba0180
MC		 3542
3543 if (unlikely(work_done >= budget))
3544 break;
3545
6dee6421 3546 rmb();
35efa7c1 3547 if (likely(!bnx2_has_work(bnapi))) {
6ad20165 3548 napi_complete_done(napi, work_done);
f86e82fb 3549 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
e503e066
MC		 3550 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3551 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3552 bnapi->last_status_idx);
6dee6421 3553 break;
6f535763 3554 }
e503e066
MC		 3555 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3556 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3557 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3558 bnapi->last_status_idx);
3559
3560 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3561 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3562 bnapi->last_status_idx);
6f535763
DM		 3563 break;
3564 }
b6016b76
MC		 3565 }
3566
bea3348e 3567 return work_done;
b6016b76
MC		 3568}
3569
932ff279 3570/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3571 * from set_multicast.
3572 */
3573static void
3574bnx2_set_rx_mode(struct net_device *dev)
3575{
972ec0d4 3576 struct bnx2 *bp = netdev_priv(dev);
b6016b76 3577 u32 rx_mode, sort_mode;
ccffad25 3578 struct netdev_hw_addr *ha;
b6016b76 3579 int i;
b6016b76 3580
9f52b564
MC		 3581 if (!netif_running(dev))
3582 return;
3583
c770a65c 3584 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3585
3586 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3587 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3588 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
f646968f 3589 if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
7d0fd211 3590 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
b6016b76 3591 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3592 if (dev->flags & IFF_PROMISC) {
3593 /* Promiscuous mode. */
3594 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3595 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3596 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3597 }
3598 else if (dev->flags & IFF_ALLMULTI) {
3599 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
e503e066
MC		 3600 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3601 0xffffffff);
90e4403a 3602 }
b6016b76
MC		 3603 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3604 }
3605 else {
3606 /* Accept one or more multicast(s). */
b6016b76
MC		 3607 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3608 u32 regidx;
3609 u32 bit;
3610 u32 crc;
3611
3612 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3613
22bedad3
JP		 3614 netdev_for_each_mc_addr(ha, dev) {
3615 crc = ether_crc_le(ETH_ALEN, ha->addr);
b6016b76
MC		 3616 bit = crc & 0xff;
3617 regidx = (bit & 0xe0) >> 5;
3618 bit &= 0x1f;
3619 mc_filter[regidx] |= (1 << bit);
3620 }
3621
3622 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
e503e066
MC		 3623 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3624 mc_filter[i]);
b6016b76
MC		 3625 }
3626
3627 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3628 }
3629
32e7bfc4 3630 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
5fcaed01
BL		 3631 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3632 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3633 BNX2_RPM_SORT_USER0_PROM_VLAN;
3634 } else if (!(dev->flags & IFF_PROMISC)) {
5fcaed01 3635 /* Add all entries into to the match filter list */
ccffad25 3636 i = 0;
32e7bfc4 3637 netdev_for_each_uc_addr(ha, dev) {
ccffad25 3638 bnx2_set_mac_addr(bp, ha->addr,
5fcaed01
BL		 3639 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3640 sort_mode |= (1 <<
3641 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
ccffad25 3642 i++;
5fcaed01
BL		 3643 }
3644
3645 }
3646
b6016b76
MC		 3647 if (rx_mode != bp->rx_mode) {
3648 bp->rx_mode = rx_mode;
e503e066 3649 BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
b6016b76
MC		 3650 }
3651
e503e066
MC		 3652 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3653 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3654 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
b6016b76 3655
c770a65c 3656 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3657}
3658
7880b72e 3659static int
57579f76
MC		 3660check_fw_section(const struct firmware *fw,
3661 const struct bnx2_fw_file_section *section,
3662 u32 alignment, bool non_empty)
3663{
3664 u32 offset = be32_to_cpu(section->offset);
3665 u32 len = be32_to_cpu(section->len);
3666
3667 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3668 return -EINVAL;
3669 if ((non_empty && len == 0) || len > fw->size - offset ||
3670 len & (alignment - 1))
3671 return -EINVAL;
3672 return 0;
3673}
3674
7880b72e 3675static int
57579f76
MC		 3676check_mips_fw_entry(const struct firmware *fw,
3677 const struct bnx2_mips_fw_file_entry *entry)
3678{
3679 if (check_fw_section(fw, &entry->text, 4, true) ||
3680 check_fw_section(fw, &entry->data, 4, false) ||
3681 check_fw_section(fw, &entry->rodata, 4, false))
3682 return -EINVAL;
3683 return 0;
3684}
3685
7880b72e 3686static void bnx2_release_firmware(struct bnx2 *bp)
3687{
3688 if (bp->rv2p_firmware) {
3689 release_firmware(bp->mips_firmware);
3690 release_firmware(bp->rv2p_firmware);
3691 bp->rv2p_firmware = NULL;
3692 }
3693}
3694
3695static int bnx2_request_uncached_firmware(struct bnx2 *bp)
b6016b76 3696{
57579f76 3697 const char *mips_fw_file, *rv2p_fw_file;
5ee1c326
BB		 3698 const struct bnx2_mips_fw_file *mips_fw;
3699 const struct bnx2_rv2p_fw_file *rv2p_fw;
57579f76
MC		 3700 int rc;
3701
4ce45e02 3702 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
57579f76 3703 mips_fw_file = FW_MIPS_FILE_09;
4ce45e02
MC		 3704 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) ||
3705 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1))
078b0735
MC		 3706 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3707 else
3708 rv2p_fw_file = FW_RV2P_FILE_09;
57579f76
MC		 3709 } else {
3710 mips_fw_file = FW_MIPS_FILE_06;
3711 rv2p_fw_file = FW_RV2P_FILE_06;
3712 }
3713
3714 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3715 if (rc) {
3a9c6a49 3716 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
7880b72e 3717 goto out;
57579f76
MC		 3718 }
3719
3720 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3721 if (rc) {
3a9c6a49 3722 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
7880b72e 3723 goto err_release_mips_firmware;
57579f76 3724 }
5ee1c326
BB		 3725 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3726 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3727 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3728 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3729 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3730 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3731 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3732 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3a9c6a49 3733 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
7880b72e 3734 rc = -EINVAL;
3735 goto err_release_firmware;
57579f76 3736 }
5ee1c326
BB		 3737 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3738 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3739 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3a9c6a49 3740 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
7880b72e 3741 rc = -EINVAL;
3742 goto err_release_firmware;
57579f76 3743 }
7880b72e 3744out:
3745 return rc;
57579f76 3746
7880b72e 3747err_release_firmware:
3748 release_firmware(bp->rv2p_firmware);
3749 bp->rv2p_firmware = NULL;
3750err_release_mips_firmware:
3751 release_firmware(bp->mips_firmware);
3752 goto out;
3753}
3754
3755static int bnx2_request_firmware(struct bnx2 *bp)
3756{
3757 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);
57579f76
MC		 3758}
3759
3760static u32
3761rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3762{
3763 switch (idx) {
3764 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3765 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3766 rv2p_code |= RV2P_BD_PAGE_SIZE;
3767 break;
3768 }
3769 return rv2p_code;
3770}
3771
3772static int
3773load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3774 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3775{
3776 u32 rv2p_code_len, file_offset;
3777 __be32 *rv2p_code;
b6016b76 3778 int i;
57579f76
MC		 3779 u32 val, cmd, addr;
3780
3781 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3782 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3783
3784 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
b6016b76 3785
57579f76
MC		 3786 if (rv2p_proc == RV2P_PROC1) {
3787 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3788 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3789 } else {
3790 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3791 addr = BNX2_RV2P_PROC2_ADDR_CMD;
d25be1d3 3792 }
b6016b76
MC		 3793
3794 for (i = 0; i < rv2p_code_len; i += 8) {
e503e066 3795 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
b6016b76 3796 rv2p_code++;
e503e066 3797 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
b6016b76
MC		 3798 rv2p_code++;
3799
57579f76 3800 val = (i / 8) | cmd;
e503e066 3801 BNX2_WR(bp, addr, val);
57579f76
MC		 3802 }
3803
3804 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3805 for (i = 0; i < 8; i++) {
3806 u32 loc, code;
3807
3808 loc = be32_to_cpu(fw_entry->fixup[i]);
3809 if (loc && ((loc * 4) < rv2p_code_len)) {
3810 code = be32_to_cpu(*(rv2p_code + loc - 1));
e503e066 3811 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
57579f76
MC		 3812 code = be32_to_cpu(*(rv2p_code + loc));
3813 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
e503e066 3814 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);
57579f76
MC		 3815
3816 val = (loc / 2) | cmd;
e503e066 3817 BNX2_WR(bp, addr, val);
b6016b76
MC		 3818 }
3819 }
3820
3821 /* Reset the processor, un-stall is done later. */
3822 if (rv2p_proc == RV2P_PROC1) {
e503e066 3823 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
b6016b76
MC		 3824 }
3825 else {
e503e066 3826 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
b6016b76 3827 }
57579f76
MC		 3828
3829 return 0;
b6016b76
MC		 3830}
3831
af3ee519 3832static int
57579f76
MC		 3833load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3834 const struct bnx2_mips_fw_file_entry *fw_entry)
b6016b76 3835{
57579f76
MC		 3836 u32 addr, len, file_offset;
3837 __be32 *data;
b6016b76
MC		 3838 u32 offset;
3839 u32 val;
3840
3841 /* Halt the CPU. */
2726d6e1 3842 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3843 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3844 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3845 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3846
3847 /* Load the Text area. */
57579f76
MC		 3848 addr = be32_to_cpu(fw_entry->text.addr);
3849 len = be32_to_cpu(fw_entry->text.len);
3850 file_offset = be32_to_cpu(fw_entry->text.offset);
3851 data = (__be32 *)(bp->mips_firmware->data + file_offset);
ea1f8d5c 3852
57579f76
MC		 3853 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3854 if (len) {
b6016b76
MC		 3855 int j;
3856
57579f76
MC		 3857 for (j = 0; j < (len / 4); j++, offset += 4)
3858 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3859 }
3860
57579f76
MC		 3861 /* Load the Data area. */
3862 addr = be32_to_cpu(fw_entry->data.addr);
3863 len = be32_to_cpu(fw_entry->data.len);
3864 file_offset = be32_to_cpu(fw_entry->data.offset);
3865 data = (__be32 *)(bp->mips_firmware->data + file_offset);
b6016b76 3866
57579f76
MC		 3867 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3868 if (len) {
b6016b76
MC		 3869 int j;
3870
57579f76
MC		 3871 for (j = 0; j < (len / 4); j++, offset += 4)
3872 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3873 }
3874
3875 /* Load the Read-Only area. */
57579f76
MC		 3876 addr = be32_to_cpu(fw_entry->rodata.addr);
3877 len = be32_to_cpu(fw_entry->rodata.len);
3878 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3879 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3880
3881 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3882 if (len) {
b6016b76
MC		 3883 int j;
3884
57579f76
MC		 3885 for (j = 0; j < (len / 4); j++, offset += 4)
3886 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3887 }
3888
3889 /* Clear the pre-fetch instruction. */
2726d6e1 3890 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
57579f76
MC		 3891
3892 val = be32_to_cpu(fw_entry->start_addr);
3893 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
b6016b76
MC		 3894
3895 /* Start the CPU. */
2726d6e1 3896 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3897 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3898 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3899 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3900
3901 return 0;
b6016b76
MC		 3902}
3903
fba9fe91 3904static int
b6016b76
MC		 3905bnx2_init_cpus(struct bnx2 *bp)
3906{
57579f76
MC		 3907 const struct bnx2_mips_fw_file *mips_fw =
3908 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3909 const struct bnx2_rv2p_fw_file *rv2p_fw =
3910 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3911 int rc;
b6016b76
MC		 3912
3913 /* Initialize the RV2P processor. */
57579f76
MC		 3914 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3915 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
b6016b76
MC		 3916
3917 /* Initialize the RX Processor. */
57579f76 3918 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
fba9fe91
MC		 3919 if (rc)
3920 goto init_cpu_err;
3921
b6016b76 3922 /* Initialize the TX Processor. */
57579f76 3923 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
fba9fe91
MC		 3924 if (rc)
3925 goto init_cpu_err;
3926
b6016b76 3927 /* Initialize the TX Patch-up Processor. */
57579f76 3928 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
fba9fe91
MC		 3929 if (rc)
3930 goto init_cpu_err;
3931
b6016b76 3932 /* Initialize the Completion Processor. */
57579f76 3933 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
fba9fe91
MC		 3934 if (rc)
3935 goto init_cpu_err;
3936
d43584c8 3937 /* Initialize the Command Processor. */
57579f76 3938 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
b6016b76 3939
fba9fe91 3940init_cpu_err:
fba9fe91 3941 return rc;
b6016b76
MC		 3942}
3943
b6a23e91
MC		 3944static void
3945bnx2_setup_wol(struct bnx2 *bp)
3946{
3947 int i;
3948 u32 val, wol_msg;
3949
3950 if (bp->wol) {
3951 u32 advertising;
3952 u8 autoneg;
3953
3954 autoneg = bp->autoneg;
3955 advertising = bp->advertising;
3956
3957 if (bp->phy_port == PORT_TP) {
3958 bp->autoneg = AUTONEG_SPEED;
3959 bp->advertising = ADVERTISED_10baseT_Half |
3960 ADVERTISED_10baseT_Full |
3961 ADVERTISED_100baseT_Half |
3962 ADVERTISED_100baseT_Full |
3963 ADVERTISED_Autoneg;
3964 }
3965
3966 spin_lock_bh(&bp->phy_lock);
3967 bnx2_setup_phy(bp, bp->phy_port);
3968 spin_unlock_bh(&bp->phy_lock);
3969
3970 bp->autoneg = autoneg;
3971 bp->advertising = advertising;
3972
3973 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3974
3975 val = BNX2_RD(bp, BNX2_EMAC_MODE);
3976
3977 /* Enable port mode. */
3978 val &= ~BNX2_EMAC_MODE_PORT;
3979 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3980 BNX2_EMAC_MODE_ACPI_RCVD |
3981 BNX2_EMAC_MODE_MPKT;
3982 if (bp->phy_port == PORT_TP) {
3983 val |= BNX2_EMAC_MODE_PORT_MII;
3984 } else {
3985 val |= BNX2_EMAC_MODE_PORT_GMII;
3986 if (bp->line_speed == SPEED_2500)
3987 val |= BNX2_EMAC_MODE_25G_MODE;
3988 }
3989
3990 BNX2_WR(bp, BNX2_EMAC_MODE, val);
3991
3992 /* receive all multicast */
3993 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3994 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3995 0xffffffff);
3996 }
3997 BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);
3998
3999 val = 1 | BNX2_RPM_SORT_USER0_BC_EN | BNX2_RPM_SORT_USER0_MC_EN;
4000 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
4001 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);
4002 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);
4003
4004 /* Need to enable EMAC and RPM for WOL. */
4005 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4006 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
4007 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
4008 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
4009
4010 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
4011 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
4012 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4013
4014 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4015 } else {
4016 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4017 }
4018
a8d9bc2e
MC		 4019 if (!(bp->flags & BNX2_FLAG_NO_WOL)) {
4020 u32 val;
4021
4022 wol_msg |= BNX2_DRV_MSG_DATA_WAIT3;
4023 if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) {
4024 bnx2_fw_sync(bp, wol_msg, 1, 0);
4025 return;
4026 }
4027 /* Tell firmware not to power down the PHY yet, otherwise
4028 * the chip will take a long time to respond to MMIO reads.
4029 */
4030 val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
4031 bnx2_shmem_wr(bp, BNX2_PORT_FEATURE,
4032 val | BNX2_PORT_FEATURE_ASF_ENABLED);
4033 bnx2_fw_sync(bp, wol_msg, 1, 0);
4034 bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val);
4035 }
b6a23e91
MC		 4036
4037}
4038
b6016b76 4039static int
829ca9a3 4040bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76 4041{
b6016b76 4042 switch (state) {
829ca9a3 4043 case PCI_D0: {
b6016b76
MC		 4044 u32 val;
4045
6d5e85c7
MC		 4046 pci_enable_wake(bp->pdev, PCI_D0, false);
4047 pci_set_power_state(bp->pdev, PCI_D0);
b6016b76 4048
e503e066 4049 val = BNX2_RD(bp, BNX2_EMAC_MODE);
b6016b76
MC		 4050 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
4051 val &= ~BNX2_EMAC_MODE_MPKT;
e503e066 4052 BNX2_WR(bp, BNX2_EMAC_MODE, val);
b6016b76 4053
e503e066 4054 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
b6016b76 4055 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
e503e066 4056 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
b6016b76
MC		 4057 break;
4058 }
829ca9a3 4059 case PCI_D3hot: {
b6a23e91 4060 bnx2_setup_wol(bp);
6d5e85c7 4061 pci_wake_from_d3(bp->pdev, bp->wol);
4ce45e02
MC		 4062 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
4063 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) {
b6016b76
MC		 4064
4065 if (bp->wol)
6d5e85c7 4066 pci_set_power_state(bp->pdev, PCI_D3hot);
a8d9bc2e
MC		 4067 break;
4068
4069 }
4070 if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4071 u32 val;
4072
4073 /* Tell firmware not to power down the PHY yet,
4074 * otherwise the other port may not respond to
4075 * MMIO reads.
4076 */
4077 val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
4078 val &= ~BNX2_CONDITION_PM_STATE_MASK;
4079 val |= BNX2_CONDITION_PM_STATE_UNPREP;
4080 bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val);
b6016b76 4081 }
a8d9bc2e 4082 pci_set_power_state(bp->pdev, PCI_D3hot);
b6016b76
MC		 4083
4084 /* No more memory access after this point until
4085 * device is brought back to D0.
4086 */
b6016b76
MC		 4087 break;
4088 }
4089 default:
4090 return -EINVAL;
4091 }
4092 return 0;
4093}
4094
4095static int
4096bnx2_acquire_nvram_lock(struct bnx2 *bp)
4097{
4098 u32 val;
4099 int j;
4100
4101 /* Request access to the flash interface. */
e503e066 4102 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
b6016b76 4103 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
e503e066 4104 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
b6016b76
MC		 4105 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4106 break;
4107
4108 udelay(5);
4109 }
4110
4111 if (j >= NVRAM_TIMEOUT_COUNT)
4112 return -EBUSY;
4113
4114 return 0;
4115}
4116
4117static int
4118bnx2_release_nvram_lock(struct bnx2 *bp)
4119{
4120 int j;
4121 u32 val;
4122
4123 /* Relinquish nvram interface. */
e503e066 4124 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
b6016b76
MC		 4125
4126 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
e503e066 4127 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
b6016b76
MC		 4128 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4129 break;
4130
4131 udelay(5);
4132 }
4133
4134 if (j >= NVRAM_TIMEOUT_COUNT)
4135 return -EBUSY;
4136
4137 return 0;
4138}
4139
4140
4141static int
4142bnx2_enable_nvram_write(struct bnx2 *bp)
4143{
4144 u32 val;
4145
e503e066
MC		 4146 val = BNX2_RD(bp, BNX2_MISC_CFG);
4147 BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
b6016b76 4148
e30372c9 4149 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 4150 int j;
4151
e503e066
MC		 4152 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4153 BNX2_WR(bp, BNX2_NVM_COMMAND,
4154 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
b6016b76
MC		 4155
4156 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4157 udelay(5);
4158
e503e066 4159 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
b6016b76
MC		 4160 if (val & BNX2_NVM_COMMAND_DONE)
4161 break;
4162 }
4163
4164 if (j >= NVRAM_TIMEOUT_COUNT)
4165 return -EBUSY;
4166 }
4167 return 0;
4168}
4169
4170static void
4171bnx2_disable_nvram_write(struct bnx2 *bp)
4172{
4173 u32 val;
4174
e503e066
MC		 4175 val = BNX2_RD(bp, BNX2_MISC_CFG);
4176 BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
b6016b76
MC		 4177}
4178
4179
4180static void
4181bnx2_enable_nvram_access(struct bnx2 *bp)
4182{
4183 u32 val;
4184
e503e066 4185 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
b6016b76 4186 /* Enable both bits, even on read. */
e503e066
MC		 4187 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4188 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
b6016b76
MC		 4189}
4190
4191static void
4192bnx2_disable_nvram_access(struct bnx2 *bp)
4193{
4194 u32 val;
4195
e503e066 4196 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
b6016b76 4197 /* Disable both bits, even after read. */
e503e066 4198 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4199 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4200 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4201}
4202
4203static int
4204bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4205{
4206 u32 cmd;
4207 int j;
4208
e30372c9 4209 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 4210 /* Buffered flash, no erase needed */
4211 return 0;
4212
4213 /* Build an erase command */
4214 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4215 BNX2_NVM_COMMAND_DOIT;
4216
4217 /* Need to clear DONE bit separately. */
e503e066 4218 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
b6016b76
MC		 4219
4220 /* Address of the NVRAM to read from. */
e503e066 4221 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
b6016b76
MC		 4222
4223 /* Issue an erase command. */
e503e066 4224 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
b6016b76
MC		 4225
4226 /* Wait for completion. */
4227 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4228 u32 val;
4229
4230 udelay(5);
4231
e503e066 4232 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
b6016b76
MC		 4233 if (val & BNX2_NVM_COMMAND_DONE)
4234 break;
4235 }
4236
4237 if (j >= NVRAM_TIMEOUT_COUNT)
4238 return -EBUSY;
4239
4240 return 0;
4241}
4242
4243static int
4244bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4245{
4246 u32 cmd;
4247 int j;
4248
4249 /* Build the command word. */
4250 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4251
e30372c9
MC		 4252 /* Calculate an offset of a buffered flash, not needed for 5709. */
4253 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4254 offset = ((offset / bp->flash_info->page_size) <<
4255 bp->flash_info->page_bits) +
4256 (offset % bp->flash_info->page_size);
4257 }
4258
4259 /* Need to clear DONE bit separately. */
e503e066 4260 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
b6016b76
MC		 4261
4262 /* Address of the NVRAM to read from. */
e503e066 4263 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
b6016b76
MC		 4264
4265 /* Issue a read command. */
e503e066 4266 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
b6016b76
MC		 4267
4268 /* Wait for completion. */
4269 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4270 u32 val;
4271
4272 udelay(5);
4273
e503e066 4274 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
b6016b76 4275 if (val & BNX2_NVM_COMMAND_DONE) {
e503e066 4276 __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));
b491edd5 4277 memcpy(ret_val, &v, 4);
b6016b76
MC		 4278 break;
4279 }
4280 }
4281 if (j >= NVRAM_TIMEOUT_COUNT)
4282 return -EBUSY;
4283
4284 return 0;
4285}
4286
4287
4288static int
4289bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4290{
b491edd5
AV		 4291 u32 cmd;
4292 __be32 val32;
b6016b76
MC		 4293 int j;
4294
4295 /* Build the command word. */
4296 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4297
e30372c9
MC		 4298 /* Calculate an offset of a buffered flash, not needed for 5709. */
4299 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4300 offset = ((offset / bp->flash_info->page_size) <<
4301 bp->flash_info->page_bits) +
4302 (offset % bp->flash_info->page_size);
4303 }
4304
4305 /* Need to clear DONE bit separately. */
e503e066 4306 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
b6016b76
MC		 4307
4308 memcpy(&val32, val, 4);
b6016b76
MC		 4309
4310 /* Write the data. */
e503e066 4311 BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 4312
4313 /* Address of the NVRAM to write to. */
e503e066 4314 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
b6016b76
MC		 4315
4316 /* Issue the write command. */
e503e066 4317 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
b6016b76
MC		 4318
4319 /* Wait for completion. */
4320 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4321 udelay(5);
4322
e503e066 4323 if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
b6016b76
MC		 4324 break;
4325 }
4326 if (j >= NVRAM_TIMEOUT_COUNT)
4327 return -EBUSY;
4328
4329 return 0;
4330}
4331
4332static int
4333bnx2_init_nvram(struct bnx2 *bp)
4334{
4335 u32 val;
e30372c9 4336 int j, entry_count, rc = 0;
0ced9d01 4337 const struct flash_spec *flash;
b6016b76 4338
4ce45e02 4339 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
e30372c9
MC		 4340 bp->flash_info = &flash_5709;
4341 goto get_flash_size;
4342 }
4343
b6016b76 4344 /* Determine the selected interface. */
e503e066 4345 val = BNX2_RD(bp, BNX2_NVM_CFG1);
b6016b76 4346
ff8ac609 4347 entry_count = ARRAY_SIZE(flash_table);
b6016b76 4348
b6016b76
MC		 4349 if (val & 0x40000000) {
4350
4351 /* Flash interface has been reconfigured */
4352 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 4353 j++, flash++) {
4354 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4355 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 4356 bp->flash_info = flash;
4357 break;
4358 }
4359 }
4360 }
4361 else {
37137709 4362 u32 mask;
b6016b76
MC		 4363 /* Not yet been reconfigured */
4364
37137709
MC		 4365 if (val & (1 << 23))
4366 mask = FLASH_BACKUP_STRAP_MASK;
4367 else
4368 mask = FLASH_STRAP_MASK;
4369
b6016b76
MC		 4370 for (j = 0, flash = &flash_table[0]; j < entry_count;
4371 j++, flash++) {
4372
37137709 4373 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 4374 bp->flash_info = flash;
4375
4376 /* Request access to the flash interface. */
4377 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4378 return rc;
4379
4380 /* Enable access to flash interface */
4381 bnx2_enable_nvram_access(bp);
4382
4383 /* Reconfigure the flash interface */
e503e066
MC		 4384 BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);
4385 BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);
4386 BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);
4387 BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);
b6016b76
MC		 4388
4389 /* Disable access to flash interface */
4390 bnx2_disable_nvram_access(bp);
4391 bnx2_release_nvram_lock(bp);
4392
4393 break;
4394 }
4395 }
4396 } /* if (val & 0x40000000) */
4397
4398 if (j == entry_count) {
4399 bp->flash_info = NULL;
3a9c6a49 4400 pr_alert("Unknown flash/EEPROM type\n");
1122db71 4401 return -ENODEV;
b6016b76
MC		 4402 }
4403
e30372c9 4404get_flash_size:
2726d6e1 4405 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 4406 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4407 if (val)
4408 bp->flash_size = val;
4409 else
4410 bp->flash_size = bp->flash_info->total_size;
4411
b6016b76
MC		 4412 return rc;
4413}
4414
4415static int
4416bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4417 int buf_size)
4418{
4419 int rc = 0;
4420 u32 cmd_flags, offset32, len32, extra;
4421
4422 if (buf_size == 0)
4423 return 0;
4424
4425 /* Request access to the flash interface. */
4426 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4427 return rc;
4428
4429 /* Enable access to flash interface */
4430 bnx2_enable_nvram_access(bp);
4431
4432 len32 = buf_size;
4433 offset32 = offset;
4434 extra = 0;
4435
4436 cmd_flags = 0;
4437
4438 if (offset32 & 3) {
4439 u8 buf[4];
4440 u32 pre_len;
4441
4442 offset32 &= ~3;
4443 pre_len = 4 - (offset & 3);
4444
4445 if (pre_len >= len32) {
4446 pre_len = len32;
4447 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4448 BNX2_NVM_COMMAND_LAST;
4449 }
4450 else {
4451 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4452 }
4453
4454 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4455
4456 if (rc)
4457 return rc;
4458
4459 memcpy(ret_buf, buf + (offset & 3), pre_len);
4460
4461 offset32 += 4;
4462 ret_buf += pre_len;
4463 len32 -= pre_len;
4464 }
4465 if (len32 & 3) {
4466 extra = 4 - (len32 & 3);
4467 len32 = (len32 + 4) & ~3;
4468 }
4469
4470 if (len32 == 4) {
4471 u8 buf[4];
4472
4473 if (cmd_flags)
4474 cmd_flags = BNX2_NVM_COMMAND_LAST;
4475 else
4476 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4477 BNX2_NVM_COMMAND_LAST;
4478
4479 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4480
4481 memcpy(ret_buf, buf, 4 - extra);
4482 }
4483 else if (len32 > 0) {
4484 u8 buf[4];
4485
4486 /* Read the first word. */
4487 if (cmd_flags)
4488 cmd_flags = 0;
4489 else
4490 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4491
4492 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4493
4494 /* Advance to the next dword. */
4495 offset32 += 4;
4496 ret_buf += 4;
4497 len32 -= 4;
4498
4499 while (len32 > 4 && rc == 0) {
4500 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4501
4502 /* Advance to the next dword. */
4503 offset32 += 4;
4504 ret_buf += 4;
4505 len32 -= 4;
4506 }
4507
4508 if (rc)
4509 return rc;
4510
4511 cmd_flags = BNX2_NVM_COMMAND_LAST;
4512 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4513
4514 memcpy(ret_buf, buf, 4 - extra);
4515 }
4516
4517 /* Disable access to flash interface */
4518 bnx2_disable_nvram_access(bp);
4519
4520 bnx2_release_nvram_lock(bp);
4521
4522 return rc;
4523}
4524
4525static int
4526bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4527 int buf_size)
4528{
4529 u32 written, offset32, len32;
e6be763f 4530 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4531 int rc = 0;
4532 int align_start, align_end;
4533
4534 buf = data_buf;
4535 offset32 = offset;
4536 len32 = buf_size;
4537 align_start = align_end = 0;
4538
4539 if ((align_start = (offset32 & 3))) {
4540 offset32 &= ~3;
c873879c
MC		 4541 len32 += align_start;
4542 if (len32 < 4)
4543 len32 = 4;
b6016b76
MC		 4544 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4545 return rc;
4546 }
4547
4548 if (len32 & 3) {
c873879c
MC		 4549 align_end = 4 - (len32 & 3);
4550 len32 += align_end;
4551 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4552 return rc;
b6016b76
MC		 4553 }
4554
4555 if (align_start || align_end) {
e6be763f 4556 align_buf = kmalloc(len32, GFP_KERNEL);
b8aac410 4557 if (!align_buf)
b6016b76
MC		 4558 return -ENOMEM;
4559 if (align_start) {
e6be763f 4560 memcpy(align_buf, start, 4);
b6016b76
MC		 4561 }
4562 if (align_end) {
e6be763f 4563 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4564 }
e6be763f
MC		 4565 memcpy(align_buf + align_start, data_buf, buf_size);
4566 buf = align_buf;
b6016b76
MC		 4567 }
4568
e30372c9 4569 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4 4570 flash_buffer = kmalloc(264, GFP_KERNEL);
b8aac410 4571 if (!flash_buffer) {
ae181bc4
MC		 4572 rc = -ENOMEM;
4573 goto nvram_write_end;
4574 }
4575 }
4576
b6016b76
MC		 4577 written = 0;
4578 while ((written < len32) && (rc == 0)) {
4579 u32 page_start, page_end, data_start, data_end;
4580 u32 addr, cmd_flags;
4581 int i;
b6016b76
MC		 4582
4583 /* Find the page_start addr */
4584 page_start = offset32 + written;
4585 page_start -= (page_start % bp->flash_info->page_size);
4586 /* Find the page_end addr */
4587 page_end = page_start + bp->flash_info->page_size;
4588 /* Find the data_start addr */
4589 data_start = (written == 0) ? offset32 : page_start;
4590 /* Find the data_end addr */
6aa20a22 4591 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4592 (offset32 + len32) : page_end;
4593
4594 /* Request access to the flash interface. */
4595 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4596 goto nvram_write_end;
4597
4598 /* Enable access to flash interface */
4599 bnx2_enable_nvram_access(bp);
4600
4601 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4602 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4603 int j;
4604
4605 /* Read the whole page into the buffer
4606 * (non-buffer flash only) */
4607 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4608 if (j == (bp->flash_info->page_size - 4)) {
4609 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4610 }
4611 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4612 page_start + j,
4613 &flash_buffer[j],
b6016b76
MC		 4614 cmd_flags);
4615
4616 if (rc)
4617 goto nvram_write_end;
4618
4619 cmd_flags = 0;
4620 }
4621 }
4622
4623 /* Enable writes to flash interface (unlock write-protect) */
4624 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4625 goto nvram_write_end;
4626
b6016b76
MC		 4627 /* Loop to write back the buffer data from page_start to
4628 * data_start */
4629 i = 0;
e30372c9 4630 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4631 /* Erase the page */
4632 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4633 goto nvram_write_end;
4634
4635 /* Re-enable the write again for the actual write */
4636 bnx2_enable_nvram_write(bp);
4637
b6016b76
MC		 4638 for (addr = page_start; addr < data_start;
4639 addr += 4, i += 4) {
6aa20a22 4640
b6016b76
MC		 4641 rc = bnx2_nvram_write_dword(bp, addr,
4642 &flash_buffer[i], cmd_flags);
4643
4644 if (rc != 0)
4645 goto nvram_write_end;
4646
4647 cmd_flags = 0;
4648 }
4649 }
4650
4651 /* Loop to write the new data from data_start to data_end */
bae25761 4652 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4653 if ((addr == page_end - 4) ||
e30372c9 4654 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4655 (addr == data_end - 4))) {
4656
4657 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4658 }
4659 rc = bnx2_nvram_write_dword(bp, addr, buf,
4660 cmd_flags);
4661
4662 if (rc != 0)
4663 goto nvram_write_end;
4664
4665 cmd_flags = 0;
4666 buf += 4;
4667 }
4668
4669 /* Loop to write back the buffer data from data_end
4670 * to page_end */
e30372c9 4671 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4672 for (addr = data_end; addr < page_end;
4673 addr += 4, i += 4) {
6aa20a22 4674
b6016b76
MC		 4675 if (addr == page_end-4) {
4676 cmd_flags = BNX2_NVM_COMMAND_LAST;
90e4403a 4677 }
b6016b76
MC		 4678 rc = bnx2_nvram_write_dword(bp, addr,
4679 &flash_buffer[i], cmd_flags);
4680
4681 if (rc != 0)
4682 goto nvram_write_end;
4683
4684 cmd_flags = 0;
4685 }
4686 }
4687
4688 /* Disable writes to flash interface (lock write-protect) */
4689 bnx2_disable_nvram_write(bp);
4690
4691 /* Disable access to flash interface */
4692 bnx2_disable_nvram_access(bp);
4693 bnx2_release_nvram_lock(bp);
4694
4695 /* Increment written */
4696 written += data_end - data_start;
4697 }
4698
4699nvram_write_end:
e6be763f
MC		 4700 kfree(flash_buffer);
4701 kfree(align_buf);
b6016b76
MC		 4702 return rc;
4703}
4704
0d8a6571 4705static void
7c62e83b 4706bnx2_init_fw_cap(struct bnx2 *bp)
0d8a6571 4707{
7c62e83b 4708 u32 val, sig = 0;
0d8a6571 4709
583c28e5 4710 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
7c62e83b
MC		 4711 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4712
4713 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4714 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
0d8a6571 4715
2726d6e1 4716 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4717 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4718 return;
4719
7c62e83b
MC		 4720 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4721 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4722 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4723 }
4724
4725 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4726 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4727 u32 link;
4728
583c28e5 4729 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4730
7c62e83b
MC		 4731 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4732 if (link & BNX2_LINK_STATUS_SERDES_LINK)
0d8a6571
MC		 4733 bp->phy_port = PORT_FIBRE;
4734 else
4735 bp->phy_port = PORT_TP;
489310a4 4736
7c62e83b
MC		 4737 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4738 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
0d8a6571 4739 }
7c62e83b
MC		 4740
4741 if (netif_running(bp->dev) && sig)
4742 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
0d8a6571
MC		 4743}
4744
b4b36042
MC		 4745static void
4746bnx2_setup_msix_tbl(struct bnx2 *bp)
4747{
e503e066 4748 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
b4b36042 4749
e503e066
MC		 4750 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4751 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
b4b36042
MC		 4752}
4753
6df77862
BH		 4754static void
4755bnx2_wait_dma_complete(struct bnx2 *bp)
b6016b76
MC		 4756{
4757 u32 val;
6df77862 4758 int i;
b6016b76 4759
6df77862
BH		 4760 /*
4761 * Wait for the current PCI transaction to complete before
4762 * issuing a reset.
4763 */
4ce45e02
MC		 4764 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
4765 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
e503e066
MC		 4766 BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4767 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4768 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4769 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4770 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4771 val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
a5dac108
EW		 4772 udelay(5);
4773 } else { /* 5709 */
e503e066 4774 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
a5dac108 4775 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
e503e066
MC		 4776 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4777 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
a5dac108
EW		 4778
4779 for (i = 0; i < 100; i++) {
4780 msleep(1);
e503e066 4781 val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
a5dac108
EW		 4782 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4783 break;
4784 }
4785 }
b6016b76 4786
6df77862
BH		 4787 return;
4788}
4789
4790
4791static int
4792bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4793{
4794 u32 val;
4795 int i, rc = 0;
4796 u8 old_port;
4797
4798 /* Wait for the current PCI transaction to complete before
4799 * issuing a reset. */
4800 bnx2_wait_dma_complete(bp);
4801
b090ae2b 4802 /* Wait for the firmware to tell us it is ok to issue a reset. */
a2f13890 4803 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
b090ae2b 4804
b6016b76
MC		 4805 /* Deposit a driver reset signature so the firmware knows that
4806 * this is a soft reset. */
2726d6e1
MC		 4807 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4808 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4809
b6016b76
MC		 4810 /* Do a dummy read to force the chip to complete all current transaction
4811 * before we issue a reset. */
e503e066 4812 val = BNX2_RD(bp, BNX2_MISC_ID);
b6016b76 4813
4ce45e02 4814 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
e503e066
MC		 4815 BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4816 BNX2_RD(bp, BNX2_MISC_COMMAND);
234754d5 4817 udelay(5);
b6016b76 4818
234754d5
MC		 4819 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4820 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4821
e503e066 4822 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4823
234754d5
MC		 4824 } else {
4825 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4826 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4827 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4828
4829 /* Chip reset. */
e503e066 4830 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
234754d5 4831
594a9dfa
MC		 4832 /* Reading back any register after chip reset will hang the
4833 * bus on 5706 A0 and A1. The msleep below provides plenty
4834 * of margin for write posting.
4835 */
4ce45e02
MC		 4836 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
4837 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1))
8e545881 4838 msleep(20);
b6016b76 4839
234754d5
MC		 4840 /* Reset takes approximate 30 usec */
4841 for (i = 0; i < 10; i++) {
e503e066 4842 val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);
234754d5
MC		 4843 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4844 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4845 break;
4846 udelay(10);
4847 }
4848
4849 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4850 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3a9c6a49 4851 pr_err("Chip reset did not complete\n");
234754d5
MC		 4852 return -EBUSY;
4853 }
b6016b76
MC		 4854 }
4855
4856 /* Make sure byte swapping is properly configured. */
e503e066 4857 val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);
b6016b76 4858 if (val != 0x01020304) {
3a9c6a49 4859 pr_err("Chip not in correct endian mode\n");
b6016b76
MC		 4860 return -ENODEV;
4861 }
4862
b6016b76 4863 /* Wait for the firmware to finish its initialization. */
a2f13890 4864 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
b090ae2b
MC		 4865 if (rc)
4866 return rc;
b6016b76 4867
0d8a6571 4868 spin_lock_bh(&bp->phy_lock);
489310a4 4869 old_port = bp->phy_port;
7c62e83b 4870 bnx2_init_fw_cap(bp);
583c28e5
MC		 4871 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4872 old_port != bp->phy_port)
0d8a6571
MC		 4873 bnx2_set_default_remote_link(bp);
4874 spin_unlock_bh(&bp->phy_lock);
4875
4ce45e02 4876 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
b6016b76
MC		 4877 /* Adjust the voltage regular to two steps lower. The default
4878 * of this register is 0x0000000e. */
e503e066 4879 BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
b6016b76
MC		 4880
4881 /* Remove bad rbuf memory from the free pool. */
4882 rc = bnx2_alloc_bad_rbuf(bp);
4883 }
4884
c441b8d2 4885 if (bp->flags & BNX2_FLAG_USING_MSIX) {
b4b36042 4886 bnx2_setup_msix_tbl(bp);
c441b8d2 4887 /* Prevent MSIX table reads and write from timing out */
e503e066 4888 BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,
c441b8d2
MC		 4889 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4890 }
b4b36042 4891
b6016b76
MC		 4892 return rc;
4893}
4894
4895static int
4896bnx2_init_chip(struct bnx2 *bp)
4897{
d8026d93 4898 u32 val, mtu;
b4b36042 4899 int rc, i;
b6016b76
MC		 4900
4901 /* Make sure the interrupt is not active. */
e503e066 4902 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
b6016b76
MC		 4903
4904 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4905 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4906#ifdef __BIG_ENDIAN
6aa20a22 4907 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4908#endif
6aa20a22 4909 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4910 DMA_READ_CHANS << 12 |
4911 DMA_WRITE_CHANS << 16;
4912
4913 val |= (0x2 << 20) | (1 << 11);
4914
f86e82fb 4915 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4916 val |= (1 << 23);
4917
4ce45e02
MC		 4918 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) &&
4919 (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) &&
4920 !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4921 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4922
e503e066 4923 BNX2_WR(bp, BNX2_DMA_CONFIG, val);
b6016b76 4924
4ce45e02 4925 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
e503e066 4926 val = BNX2_RD(bp, BNX2_TDMA_CONFIG);
b6016b76 4927 val |= BNX2_TDMA_CONFIG_ONE_DMA;
e503e066 4928 BNX2_WR(bp, BNX2_TDMA_CONFIG, val);
b6016b76
MC		 4929 }
4930
f86e82fb 4931 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4932 u16 val16;
4933
4934 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4935 &val16);
4936 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4937 val16 & ~PCI_X_CMD_ERO);
4938 }
4939
e503e066
MC		 4940 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4941 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4942 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4943 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
b6016b76
MC		 4944
4945 /* Initialize context mapping and zero out the quick contexts. The
4946 * context block must have already been enabled. */
4ce45e02 4947 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
641bdcd5
MC		 4948 rc = bnx2_init_5709_context(bp);
4949 if (rc)
4950 return rc;
4951 } else
59b47d8a 4952 bnx2_init_context(bp);
b6016b76 4953
fba9fe91
MC		 4954 if ((rc = bnx2_init_cpus(bp)) != 0)
4955 return rc;
4956
b6016b76
MC		 4957 bnx2_init_nvram(bp);
4958
5fcaed01 4959 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76 4960
e503e066 4961 val = BNX2_RD(bp, BNX2_MQ_CONFIG);
b6016b76
MC		 4962 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4963 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4ce45e02 4964 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4edd473f 4965 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4ce45e02 4966 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)
4edd473f
MC		 4967 val |= BNX2_MQ_CONFIG_HALT_DIS;
4968 }
68c9f75a 4969
e503e066 4970 BNX2_WR(bp, BNX2_MQ_CONFIG, val);
b6016b76
MC		 4971
4972 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
e503e066
MC		 4973 BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4974 BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);
b6016b76 4975
2bc4078e 4976 val = (BNX2_PAGE_BITS - 8) << 24;
e503e066 4977 BNX2_WR(bp, BNX2_RV2P_CONFIG, val);
b6016b76
MC		 4978
4979 /* Configure page size. */
e503e066 4980 val = BNX2_RD(bp, BNX2_TBDR_CONFIG);
b6016b76 4981 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
2bc4078e 4982 val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40;
e503e066 4983 BNX2_WR(bp, BNX2_TBDR_CONFIG, val);
b6016b76
MC		 4984
4985 val = bp->mac_addr[0] +
4986 (bp->mac_addr[1] << 8) +
4987 (bp->mac_addr[2] << 16) +
4988 bp->mac_addr[3] +
4989 (bp->mac_addr[4] << 8) +
4990 (bp->mac_addr[5] << 16);
e503e066 4991 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
b6016b76
MC		 4992
4993 /* Program the MTU. Also include 4 bytes for CRC32. */
d8026d93
MC		 4994 mtu = bp->dev->mtu;
4995 val = mtu + ETH_HLEN + ETH_FCS_LEN;
e1c6dcca 4996 if (val > (MAX_ETHERNET_PACKET_SIZE + ETH_HLEN + 4))
b6016b76 4997 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
e503e066 4998 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
b6016b76 4999
e1c6dcca
JW		 5000 if (mtu < ETH_DATA_LEN)
5001 mtu = ETH_DATA_LEN;
d8026d93
MC		 5002
5003 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
5004 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
5005 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
5006
155d5561 5007 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
b4b36042
MC		 5008 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5009 bp->bnx2_napi[i].last_status_idx = 0;
5010
efba0180
MC		 5011 bp->idle_chk_status_idx = 0xffff;
5012
b6016b76 5013 /* Set up how to generate a link change interrupt. */
e503e066 5014 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
b6016b76 5015
e503e066
MC		 5016 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,
5017 (u64) bp->status_blk_mapping & 0xffffffff);
5018 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
b6016b76 5019
e503e066
MC		 5020 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
5021 (u64) bp->stats_blk_mapping & 0xffffffff);
5022 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
5023 (u64) bp->stats_blk_mapping >> 32);
b6016b76 5024
e503e066
MC		 5025 BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
5026 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
b6016b76 5027
e503e066
MC		 5028 BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
5029 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
b6016b76 5030
e503e066
MC		 5031 BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,
5032 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
b6016b76 5033
e503e066 5034 BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
b6016b76 5035
e503e066 5036 BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
b6016b76 5037
e503e066
MC		 5038 BNX2_WR(bp, BNX2_HC_COM_TICKS,
5039 (bp->com_ticks_int << 16) | bp->com_ticks);
b6016b76 5040
e503e066
MC		 5041 BNX2_WR(bp, BNX2_HC_CMD_TICKS,
5042 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
b6016b76 5043
61d9e3fa 5044 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
e503e066 5045 BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);
02537b06 5046 else
e503e066
MC		 5047 BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
5048 BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
b6016b76 5049
4ce45e02 5050 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)
8e6a72c4 5051 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 5052 else {
8e6a72c4
MC		 5053 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
5054 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 5055 }
5056
efde73a3 5057 if (bp->flags & BNX2_FLAG_USING_MSIX) {
e503e066
MC		 5058 BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
5059 BNX2_HC_MSIX_BIT_VECTOR_VAL);
c76c0475 5060
5e9ad9e1
MC		 5061 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
5062 }
5063
5064 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
cf7474a6 5065 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5e9ad9e1 5066
e503e066 5067 BNX2_WR(bp, BNX2_HC_CONFIG, val);
5e9ad9e1 5068
22fa159d
MC		 5069 if (bp->rx_ticks < 25)
5070 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
5071 else
5072 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
5073
5e9ad9e1
MC		 5074 for (i = 1; i < bp->irq_nvecs; i++) {
5075 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
5076 BNX2_HC_SB_CONFIG_1;
5077
e503e066 5078 BNX2_WR(bp, base,
c76c0475 5079 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5e9ad9e1 5080 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
c76c0475
MC		 5081 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
5082
e503e066 5083 BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 5084 (bp->tx_quick_cons_trip_int << 16) |
5085 bp->tx_quick_cons_trip);
5086
e503e066 5087 BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 5088 (bp->tx_ticks_int << 16) | bp->tx_ticks);
5089
e503e066
MC		 5090 BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5091 (bp->rx_quick_cons_trip_int << 16) |
5e9ad9e1 5092 bp->rx_quick_cons_trip);
8e6a72c4 5093
e503e066 5094 BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
5e9ad9e1
MC		 5095 (bp->rx_ticks_int << 16) | bp->rx_ticks);
5096 }
8e6a72c4 5097
b6016b76 5098 /* Clear internal stats counters. */
e503e066 5099 BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
b6016b76 5100
e503e066 5101 BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 5102
5103 /* Initialize the receive filter. */
5104 bnx2_set_rx_mode(bp->dev);
5105
4ce45e02 5106 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
e503e066 5107 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
0aa38df7 5108 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
e503e066 5109 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
0aa38df7 5110 }
b090ae2b 5111 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
a2f13890 5112 1, 0);
b6016b76 5113
e503e066
MC		 5114 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
5115 BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
b6016b76
MC		 5116
5117 udelay(20);
5118
e503e066 5119 bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);
bf5295bb 5120
b090ae2b 5121 return rc;
b6016b76
MC		 5122}
5123
c76c0475
MC		 5124static void
5125bnx2_clear_ring_states(struct bnx2 *bp)
5126{
5127 struct bnx2_napi *bnapi;
35e9010b 5128 struct bnx2_tx_ring_info *txr;
bb4f98ab 5129 struct bnx2_rx_ring_info *rxr;
c76c0475
MC		 5130 int i;
5131
5132 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5133 bnapi = &bp->bnx2_napi[i];
35e9010b 5134 txr = &bnapi->tx_ring;
bb4f98ab 5135 rxr = &bnapi->rx_ring;
c76c0475 5136
35e9010b
MC		 5137 txr->tx_cons = 0;
5138 txr->hw_tx_cons = 0;
bb4f98ab
MC		 5139 rxr->rx_prod_bseq = 0;
5140 rxr->rx_prod = 0;
5141 rxr->rx_cons = 0;
5142 rxr->rx_pg_prod = 0;
5143 rxr->rx_pg_cons = 0;
c76c0475
MC		 5144 }
5145}
5146
59b47d8a 5147static void
35e9010b 5148bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
59b47d8a
MC		 5149{
5150 u32 val, offset0, offset1, offset2, offset3;
62a8313c 5151 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a 5152
4ce45e02 5153 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
59b47d8a
MC		 5154 offset0 = BNX2_L2CTX_TYPE_XI;
5155 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5156 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5157 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5158 } else {
5159 offset0 = BNX2_L2CTX_TYPE;
5160 offset1 = BNX2_L2CTX_CMD_TYPE;
5161 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5162 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5163 }
5164 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 5165 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 5166
5167 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 5168 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a 5169
35e9010b 5170 val = (u64) txr->tx_desc_mapping >> 32;
62a8313c 5171 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a 5172
35e9010b 5173 val = (u64) txr->tx_desc_mapping & 0xffffffff;
62a8313c 5174 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 5175}
b6016b76
MC		 5176
5177static void
35e9010b 5178bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
b6016b76 5179{
2bc4078e 5180 struct bnx2_tx_bd *txbd;
c76c0475
MC		 5181 u32 cid = TX_CID;
5182 struct bnx2_napi *bnapi;
35e9010b 5183 struct bnx2_tx_ring_info *txr;
c76c0475 5184
35e9010b
MC		 5185 bnapi = &bp->bnx2_napi[ring_num];
5186 txr = &bnapi->tx_ring;
5187
5188 if (ring_num == 0)
5189 cid = TX_CID;
5190 else
5191 cid = TX_TSS_CID + ring_num - 1;
b6016b76 5192
2f8af120
MC		 5193 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5194
2bc4078e 5195 txbd = &txr->tx_desc_ring[BNX2_MAX_TX_DESC_CNT];
6aa20a22 5196
35e9010b
MC		 5197 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5198 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
b6016b76 5199
35e9010b
MC		 5200 txr->tx_prod = 0;
5201 txr->tx_prod_bseq = 0;
6aa20a22 5202
35e9010b
MC		 5203 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5204 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 5205
35e9010b 5206 bnx2_init_tx_context(bp, cid, txr);
b6016b76
MC		 5207}
5208
5209static void
2bc4078e
MC		 5210bnx2_init_rxbd_rings(struct bnx2_rx_bd *rx_ring[], dma_addr_t dma[],
5211 u32 buf_size, int num_rings)
b6016b76 5212{
b6016b76 5213 int i;
2bc4078e 5214 struct bnx2_rx_bd *rxbd;
6aa20a22 5215
5d5d0015 5216 for (i = 0; i < num_rings; i++) {
13daffa2 5217 int j;
b6016b76 5218
5d5d0015 5219 rxbd = &rx_ring[i][0];
2bc4078e 5220 for (j = 0; j < BNX2_MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 5221 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 5222 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5223 }
5d5d0015 5224 if (i == (num_rings - 1))
13daffa2
MC		 5225 j = 0;
5226 else
5227 j = i + 1;
5d5d0015
MC		 5228 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5229 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 5230 }
5d5d0015
MC		 5231}
5232
5233static void
bb4f98ab 5234bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5d5d0015
MC		 5235{
5236 int i;
5237 u16 prod, ring_prod;
bb4f98ab
MC		 5238 u32 cid, rx_cid_addr, val;
5239 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5240 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5241
5242 if (ring_num == 0)
5243 cid = RX_CID;
5244 else
5245 cid = RX_RSS_CID + ring_num - 1;
5246
5247 rx_cid_addr = GET_CID_ADDR(cid);
5d5d0015 5248
bb4f98ab 5249 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5d5d0015
MC		 5250 bp->rx_buf_use_size, bp->rx_max_ring);
5251
bb4f98ab 5252 bnx2_init_rx_context(bp, cid);
83e3fc89 5253
4ce45e02 5254 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
e503e066
MC		 5255 val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);
5256 BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
83e3fc89
MC		 5257 }
5258
62a8313c 5259 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246 5260 if (bp->rx_pg_ring_size) {
bb4f98ab
MC		 5261 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5262 rxr->rx_pg_desc_mapping,
47bf4246
MC		 5263 PAGE_SIZE, bp->rx_max_pg_ring);
5264 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 5265 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5266 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5e9ad9e1 5267 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
47bf4246 5268
bb4f98ab 5269 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
62a8313c 5270 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246 5271
bb4f98ab 5272 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 5273 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246 5274
4ce45e02 5275 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
e503e066 5276 BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
47bf4246 5277 }
b6016b76 5278
bb4f98ab 5279 val = (u64) rxr->rx_desc_mapping[0] >> 32;
62a8313c 5280 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 5281
bb4f98ab 5282 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
62a8313c 5283 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 5284
bb4f98ab 5285 ring_prod = prod = rxr->rx_pg_prod;
47bf4246 5286 for (i = 0; i < bp->rx_pg_ring_size; i++) {
a2df00aa 5287 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5288 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5289 ring_num, i, bp->rx_pg_ring_size);
47bf4246 5290 break;
b929e53c 5291 }
2bc4078e
MC		 5292 prod = BNX2_NEXT_RX_BD(prod);
5293 ring_prod = BNX2_RX_PG_RING_IDX(prod);
47bf4246 5294 }
bb4f98ab 5295 rxr->rx_pg_prod = prod;
47bf4246 5296
bb4f98ab 5297 ring_prod = prod = rxr->rx_prod;
236b6394 5298 for (i = 0; i < bp->rx_ring_size; i++) {
dd2bc8e9 5299 if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5300 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5301 ring_num, i, bp->rx_ring_size);
b6016b76 5302 break;
b929e53c 5303 }
2bc4078e
MC		 5304 prod = BNX2_NEXT_RX_BD(prod);
5305 ring_prod = BNX2_RX_RING_IDX(prod);
b6016b76 5306 }
bb4f98ab 5307 rxr->rx_prod = prod;
b6016b76 5308
bb4f98ab
MC		 5309 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5310 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5311 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
b6016b76 5312
e503e066
MC		 5313 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5314 BNX2_WR16(bp, rxr->rx_bidx_addr, prod);
bb4f98ab 5315
e503e066 5316 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 5317}
5318
35e9010b
MC		 5319static void
5320bnx2_init_all_rings(struct bnx2 *bp)
5321{
5322 int i;
5e9ad9e1 5323 u32 val;
35e9010b
MC		 5324
5325 bnx2_clear_ring_states(bp);
5326
e503e066 5327 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);
35e9010b
MC		 5328 for (i = 0; i < bp->num_tx_rings; i++)
5329 bnx2_init_tx_ring(bp, i);
5330
5331 if (bp->num_tx_rings > 1)
e503e066
MC		 5332 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5333 (TX_TSS_CID << 7));
35e9010b 5334
e503e066 5335 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5e9ad9e1
MC		 5336 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5337
bb4f98ab
MC		 5338 for (i = 0; i < bp->num_rx_rings; i++)
5339 bnx2_init_rx_ring(bp, i);
5e9ad9e1
MC		 5340
5341 if (bp->num_rx_rings > 1) {
22fa159d 5342 u32 tbl_32 = 0;
5e9ad9e1
MC		 5343
5344 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
22fa159d
MC		 5345 int shift = (i % 8) << 2;
5346
5347 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
5348 if ((i % 8) == 7) {
e503e066
MC		 5349 BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5350 BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
22fa159d
MC		 5351 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
5352 BNX2_RLUP_RSS_COMMAND_WRITE |
5353 BNX2_RLUP_RSS_COMMAND_HASH_MASK);
5354 tbl_32 = 0;
5355 }
5e9ad9e1
MC		 5356 }
5357
5358 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5359 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5360
e503e066 5361 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5e9ad9e1
MC		 5362
5363 }
35e9010b
MC		 5364}
5365
5d5d0015 5366static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 5367{
5d5d0015 5368 u32 max, num_rings = 1;
13daffa2 5369
2bc4078e
MC		 5370 while (ring_size > BNX2_MAX_RX_DESC_CNT) {
5371 ring_size -= BNX2_MAX_RX_DESC_CNT;
13daffa2
MC		 5372 num_rings++;
5373 }
5374 /* round to next power of 2 */
5d5d0015 5375 max = max_size;
13daffa2
MC		 5376 while ((max & num_rings) == 0)
5377 max >>= 1;
5378
5379 if (num_rings != max)
5380 max <<= 1;
5381
5d5d0015
MC		 5382 return max;
5383}
5384
5385static void
5386bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5387{
84eaa187 5388 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 5389
5390 /* 8 for CRC and VLAN */
d89cb6af 5391 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 5392
84eaa187 5393 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
dd2bc8e9 5394 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
84eaa187 5395
601d3d18 5396 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 5397 bp->rx_pg_ring_size = 0;
5398 bp->rx_max_pg_ring = 0;
5399 bp->rx_max_pg_ring_idx = 0;
f86e82fb 5400 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 5401 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5402
5403 jumbo_size = size * pages;
2bc4078e
MC		 5404 if (jumbo_size > BNX2_MAX_TOTAL_RX_PG_DESC_CNT)
5405 jumbo_size = BNX2_MAX_TOTAL_RX_PG_DESC_CNT;
84eaa187
MC		 5406
5407 bp->rx_pg_ring_size = jumbo_size;
5408 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
2bc4078e
MC		 5409 BNX2_MAX_RX_PG_RINGS);
5410 bp->rx_max_pg_ring_idx =
5411 (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1;
601d3d18 5412 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 5413 bp->rx_copy_thresh = 0;
5414 }
5d5d0015
MC		 5415
5416 bp->rx_buf_use_size = rx_size;
dd2bc8e9
ED		 5417 /* hw alignment + build_skb() overhead*/
5418 bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +
5419 NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
d89cb6af 5420 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015 5421 bp->rx_ring_size = size;
2bc4078e
MC		 5422 bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS);
5423 bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1;
13daffa2
MC		 5424}
5425
b6016b76
MC		 5426static void
5427bnx2_free_tx_skbs(struct bnx2 *bp)
5428{
5429 int i;
5430
35e9010b
MC		 5431 for (i = 0; i < bp->num_tx_rings; i++) {
5432 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5433 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5434 int j;
b6016b76 5435
b8aac410 5436 if (!txr->tx_buf_ring)
b6016b76 5437 continue;
b6016b76 5438
2bc4078e
MC		 5439 for (j = 0; j < BNX2_TX_DESC_CNT; ) {
5440 struct bnx2_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
35e9010b 5441 struct sk_buff *skb = tx_buf->skb;
e95524a7 5442 int k, last;
35e9010b 5443
b8aac410 5444 if (!skb) {
2bc4078e 5445 j = BNX2_NEXT_TX_BD(j);
35e9010b
MC		 5446 continue;
5447 }
5448
36227e88 5449 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5450 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5451 skb_headlen(skb),
5452 PCI_DMA_TODEVICE);
b6016b76 5453
35e9010b 5454 tx_buf->skb = NULL;
b6016b76 5455
e95524a7 5456 last = tx_buf->nr_frags;
2bc4078e
MC		 5457 j = BNX2_NEXT_TX_BD(j);
5458 for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) {
5459 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(j)];
36227e88 5460 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 5461 dma_unmap_addr(tx_buf, mapping),
9e903e08 5462 skb_frag_size(&skb_shinfo(skb)->frags[k]),
e95524a7
AD		 5463 PCI_DMA_TODEVICE);
5464 }
35e9010b 5465 dev_kfree_skb(skb);
b6016b76 5466 }
e9831909 5467 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
b6016b76 5468 }
b6016b76
MC		 5469}
5470
5471static void
5472bnx2_free_rx_skbs(struct bnx2 *bp)
5473{
5474 int i;
5475
bb4f98ab
MC		 5476 for (i = 0; i < bp->num_rx_rings; i++) {
5477 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5478 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5479 int j;
b6016b76 5480
b8aac410 5481 if (!rxr->rx_buf_ring)
bb4f98ab 5482 return;
b6016b76 5483
bb4f98ab 5484 for (j = 0; j < bp->rx_max_ring_idx; j++) {
2bc4078e 5485 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[j];
dd2bc8e9 5486 u8 *data = rx_buf->data;
b6016b76 5487
b8aac410 5488 if (!data)
bb4f98ab 5489 continue;
b6016b76 5490
36227e88 5491 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5492 dma_unmap_addr(rx_buf, mapping),
bb4f98ab
MC		 5493 bp->rx_buf_use_size,
5494 PCI_DMA_FROMDEVICE);
b6016b76 5495
dd2bc8e9 5496 rx_buf->data = NULL;
bb4f98ab 5497
dd2bc8e9 5498 kfree(data);
bb4f98ab
MC		 5499 }
5500 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5501 bnx2_free_rx_page(bp, rxr, j);
b6016b76
MC		 5502 }
5503}
5504
5505static void
5506bnx2_free_skbs(struct bnx2 *bp)
5507{
5508 bnx2_free_tx_skbs(bp);
5509 bnx2_free_rx_skbs(bp);
5510}
5511
5512static int
5513bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5514{
5515 int rc;
5516
5517 rc = bnx2_reset_chip(bp, reset_code);
5518 bnx2_free_skbs(bp);
5519 if (rc)
5520 return rc;
5521
fba9fe91
MC		 5522 if ((rc = bnx2_init_chip(bp)) != 0)
5523 return rc;
5524
35e9010b 5525 bnx2_init_all_rings(bp);
b6016b76
MC		 5526 return 0;
5527}
5528
5529static int
9a120bc5 5530bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 5531{
5532 int rc;
5533
5534 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5535 return rc;
5536
80be4434 5537 spin_lock_bh(&bp->phy_lock);
9a120bc5 5538 bnx2_init_phy(bp, reset_phy);
b6016b76 5539 bnx2_set_link(bp);
543a827d
MC		 5540 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5541 bnx2_remote_phy_event(bp);
0d8a6571 5542 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5543 return 0;
5544}
5545
74bf4ba3
MC		 5546static int
5547bnx2_shutdown_chip(struct bnx2 *bp)
5548{
5549 u32 reset_code;
5550
5551 if (bp->flags & BNX2_FLAG_NO_WOL)
5552 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5553 else if (bp->wol)
5554 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5555 else
5556 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5557
5558 return bnx2_reset_chip(bp, reset_code);
5559}
5560
b6016b76
MC		 5561static int
5562bnx2_test_registers(struct bnx2 *bp)
5563{
5564 int ret;
5bae30c9 5565 int i, is_5709;
f71e1309 5566 static const struct {
b6016b76
MC		 5567 u16 offset;
5568 u16 flags;
5bae30c9 5569#define BNX2_FL_NOT_5709 1
b6016b76
MC		 5570 u32 rw_mask;
5571 u32 ro_mask;
5572 } reg_tbl[] = {
5573 { 0x006c, 0, 0x00000000, 0x0000003f },
5574 { 0x0090, 0, 0xffffffff, 0x00000000 },
5575 { 0x0094, 0, 0x00000000, 0x00000000 },
5576
5bae30c9
MC		 5577 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5578 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5579 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5580 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5581 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5582 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5583 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5584 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5585 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5586
5587 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5588 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5589 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5590 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5591 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5592 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5593
5594 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5595 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5596 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 5597
5598 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 5599 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 5600
5601 { 0x1408, 0, 0x01c00800, 0x00000000 },
5602 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5603 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 5604 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 5605 { 0x14b0, 0, 0x00000002, 0x00000001 },
5606 { 0x14b8, 0, 0x00000000, 0x00000000 },
5607 { 0x14c0, 0, 0x00000000, 0x00000009 },
5608 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5609 { 0x14cc, 0, 0x00000000, 0x00000001 },
5610 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 5611
5612 { 0x1800, 0, 0x00000000, 0x00000001 },
5613 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 5614
5615 { 0x2800, 0, 0x00000000, 0x00000001 },
5616 { 0x2804, 0, 0x00000000, 0x00003f01 },
5617 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5618 { 0x2810, 0, 0xffff0000, 0x00000000 },
5619 { 0x2814, 0, 0xffff0000, 0x00000000 },
5620 { 0x2818, 0, 0xffff0000, 0x00000000 },
5621 { 0x281c, 0, 0xffff0000, 0x00000000 },
5622 { 0x2834, 0, 0xffffffff, 0x00000000 },
5623 { 0x2840, 0, 0x00000000, 0xffffffff },
5624 { 0x2844, 0, 0x00000000, 0xffffffff },
5625 { 0x2848, 0, 0xffffffff, 0x00000000 },
5626 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5627
5628 { 0x2c00, 0, 0x00000000, 0x00000011 },
5629 { 0x2c04, 0, 0x00000000, 0x00030007 },
5630
b6016b76
MC		 5631 { 0x3c00, 0, 0x00000000, 0x00000001 },
5632 { 0x3c04, 0, 0x00000000, 0x00070000 },
5633 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5634 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5635 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5636 { 0x3c14, 0, 0x00000000, 0xffffffff },
5637 { 0x3c18, 0, 0x00000000, 0xffffffff },
5638 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5639 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 5640
5641 { 0x5004, 0, 0x00000000, 0x0000007f },
5642 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 5643
b6016b76
MC		 5644 { 0x5c00, 0, 0x00000000, 0x00000001 },
5645 { 0x5c04, 0, 0x00000000, 0x0003000f },
5646 { 0x5c08, 0, 0x00000003, 0x00000000 },
5647 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5648 { 0x5c10, 0, 0x00000000, 0xffffffff },
5649 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5650 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5651 { 0x5c88, 0, 0x00000000, 0x00077373 },
5652 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5653
5654 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5655 { 0x680c, 0, 0xffffffff, 0x00000000 },
5656 { 0x6810, 0, 0xffffffff, 0x00000000 },
5657 { 0x6814, 0, 0xffffffff, 0x00000000 },
5658 { 0x6818, 0, 0xffffffff, 0x00000000 },
5659 { 0x681c, 0, 0xffffffff, 0x00000000 },
5660 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5661 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5662 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5663 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5664 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5665 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5666 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5667 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5668 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5669 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5670 { 0x684c, 0, 0xffffffff, 0x00000000 },
5671 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5672 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5673 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5674 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5675 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5676 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5677
5678 { 0xffff, 0, 0x00000000, 0x00000000 },
5679 };
5680
5681 ret = 0;
5bae30c9 5682 is_5709 = 0;
4ce45e02 5683 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
5bae30c9
MC		 5684 is_5709 = 1;
5685
b6016b76
MC		 5686 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5687 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5688 u16 flags = reg_tbl[i].flags;
5689
5690 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5691 continue;
b6016b76
MC		 5692
5693 offset = (u32) reg_tbl[i].offset;
5694 rw_mask = reg_tbl[i].rw_mask;
5695 ro_mask = reg_tbl[i].ro_mask;
5696
14ab9b86 5697 save_val = readl(bp->regview + offset);
b6016b76 5698
14ab9b86 5699 writel(0, bp->regview + offset);
b6016b76 5700
14ab9b86 5701 val = readl(bp->regview + offset);
b6016b76
MC		 5702 if ((val & rw_mask) != 0) {
5703 goto reg_test_err;
5704 }
5705
5706 if ((val & ro_mask) != (save_val & ro_mask)) {
5707 goto reg_test_err;
5708 }
5709
14ab9b86 5710 writel(0xffffffff, bp->regview + offset);
b6016b76 5711
14ab9b86 5712 val = readl(bp->regview + offset);
b6016b76
MC		 5713 if ((val & rw_mask) != rw_mask) {
5714 goto reg_test_err;
5715 }
5716
5717 if ((val & ro_mask) != (save_val & ro_mask)) {
5718 goto reg_test_err;
5719 }
5720
14ab9b86 5721 writel(save_val, bp->regview + offset);
b6016b76
MC		 5722 continue;
5723
5724reg_test_err:
14ab9b86 5725 writel(save_val, bp->regview + offset);
b6016b76
MC		 5726 ret = -ENODEV;
5727 break;
5728 }
5729 return ret;
5730}
5731
5732static int
5733bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5734{
f71e1309 5735 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5736 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5737 int i;
5738
5739 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5740 u32 offset;
5741
5742 for (offset = 0; offset < size; offset += 4) {
5743
2726d6e1 5744 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5745
2726d6e1 5746 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5747 test_pattern[i]) {
5748 return -ENODEV;
5749 }
5750 }
5751 }
5752 return 0;
5753}
5754
5755static int
5756bnx2_test_memory(struct bnx2 *bp)
5757{
5758 int ret = 0;
5759 int i;
5bae30c9 5760 static struct mem_entry {
b6016b76
MC		 5761 u32 offset;
5762 u32 len;
5bae30c9 5763 } mem_tbl_5706[] = {
b6016b76 5764 { 0x60000, 0x4000 },
5b0c76ad 5765 { 0xa0000, 0x3000 },
b6016b76
MC		 5766 { 0xe0000, 0x4000 },
5767 { 0x120000, 0x4000 },
5768 { 0x1a0000, 0x4000 },
5769 { 0x160000, 0x4000 },
5770 { 0xffffffff, 0 },
5bae30c9
MC		 5771 },
5772 mem_tbl_5709[] = {
5773 { 0x60000, 0x4000 },
5774 { 0xa0000, 0x3000 },
5775 { 0xe0000, 0x4000 },
5776 { 0x120000, 0x4000 },
5777 { 0x1a0000, 0x4000 },
5778 { 0xffffffff, 0 },
b6016b76 5779 };
5bae30c9
MC		 5780 struct mem_entry *mem_tbl;
5781
4ce45e02 5782 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
5bae30c9
MC		 5783 mem_tbl = mem_tbl_5709;
5784 else
5785 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5786
5787 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5788 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5789 mem_tbl[i].len)) != 0) {
5790 return ret;
5791 }
5792 }
6aa20a22 5793
b6016b76
MC		 5794 return ret;
5795}
5796
bc5a0690
MC		 5797#define BNX2_MAC_LOOPBACK 0
5798#define BNX2_PHY_LOOPBACK 1
5799
b6016b76 5800static int
bc5a0690 5801bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5802{
5803 unsigned int pkt_size, num_pkts, i;
dd2bc8e9
ED		 5804 struct sk_buff *skb;
5805 u8 *data;
b6016b76 5806 unsigned char *packet;
bc5a0690 5807 u16 rx_start_idx, rx_idx;
b6016b76 5808 dma_addr_t map;
2bc4078e
MC		 5809 struct bnx2_tx_bd *txbd;
5810 struct bnx2_sw_bd *rx_buf;
b6016b76
MC		 5811 struct l2_fhdr *rx_hdr;
5812 int ret = -ENODEV;
c76c0475 5813 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
196709f4
CIK		 5814 struct bnx2_tx_ring_info *txr;
5815 struct bnx2_rx_ring_info *rxr;
c76c0475
MC		 5816
5817 tx_napi = bnapi;
b6016b76 5818
35e9010b 5819 txr = &tx_napi->tx_ring;
bb4f98ab 5820 rxr = &bnapi->rx_ring;
bc5a0690
MC		 5821 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5822 bp->loopback = MAC_LOOPBACK;
5823 bnx2_set_mac_loopback(bp);
5824 }
5825 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5826 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5827 return 0;
5828
80be4434 5829 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5830 bnx2_set_phy_loopback(bp);
5831 }
5832 else
5833 return -EINVAL;
b6016b76 5834
84eaa187 5835 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5836 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5837 if (!skb)
5838 return -ENOMEM;
b6016b76 5839 packet = skb_put(skb, pkt_size);
d458cdf7
JP		 5840 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
5841 memset(packet + ETH_ALEN, 0x0, 8);
b6016b76
MC		 5842 for (i = 14; i < pkt_size; i++)
5843 packet[i] = (unsigned char) (i & 0xff);
5844
36227e88
SG		 5845 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5846 PCI_DMA_TODEVICE);
5847 if (dma_mapping_error(&bp->pdev->dev, map)) {
3d16af86
BL		 5848 dev_kfree_skb(skb);
5849 return -EIO;
5850 }
b6016b76 5851
e503e066
MC		 5852 BNX2_WR(bp, BNX2_HC_COMMAND,
5853 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
bf5295bb 5854
e503e066 5855 BNX2_RD(bp, BNX2_HC_COMMAND);
b6016b76
MC		 5856
5857 udelay(5);
35efa7c1 5858 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5859
b6016b76
MC		 5860 num_pkts = 0;
5861
2bc4078e 5862 txbd = &txr->tx_desc_ring[BNX2_TX_RING_IDX(txr->tx_prod)];
b6016b76
MC		 5863
5864 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5865 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5866 txbd->tx_bd_mss_nbytes = pkt_size;
5867 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5868
5869 num_pkts++;
2bc4078e 5870 txr->tx_prod = BNX2_NEXT_TX_BD(txr->tx_prod);
35e9010b 5871 txr->tx_prod_bseq += pkt_size;
b6016b76 5872
e503e066
MC		 5873 BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5874 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 5875
5876 udelay(100);
5877
e503e066
MC		 5878 BNX2_WR(bp, BNX2_HC_COMMAND,
5879 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
bf5295bb 5880
e503e066 5881 BNX2_RD(bp, BNX2_HC_COMMAND);
b6016b76
MC		 5882
5883 udelay(5);
5884
36227e88 5885 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5886 dev_kfree_skb(skb);
b6016b76 5887
35e9010b 5888 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
b6016b76 5889 goto loopback_test_done;
b6016b76 5890
35efa7c1 5891 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5892 if (rx_idx != rx_start_idx + num_pkts) {
5893 goto loopback_test_done;
5894 }
5895
bb4f98ab 5896 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
dd2bc8e9 5897 data = rx_buf->data;
b6016b76 5898
dd2bc8e9
ED		 5899 rx_hdr = get_l2_fhdr(data);
5900 data = (u8 *)rx_hdr + BNX2_RX_OFFSET;
b6016b76 5901
36227e88 5902 dma_sync_single_for_cpu(&bp->pdev->dev,
1a4ccc2d 5903 dma_unmap_addr(rx_buf, mapping),
dd2bc8e9 5904 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
b6016b76 5905
ade2bfe7 5906 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5907 (L2_FHDR_ERRORS_BAD_CRC |
5908 L2_FHDR_ERRORS_PHY_DECODE |
5909 L2_FHDR_ERRORS_ALIGNMENT |
5910 L2_FHDR_ERRORS_TOO_SHORT |
5911 L2_FHDR_ERRORS_GIANT_FRAME)) {
5912
5913 goto loopback_test_done;
5914 }
5915
5916 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5917 goto loopback_test_done;
5918 }
5919
5920 for (i = 14; i < pkt_size; i++) {
dd2bc8e9 5921 if (*(data + i) != (unsigned char) (i & 0xff)) {
b6016b76
MC		 5922 goto loopback_test_done;
5923 }
5924 }
5925
5926 ret = 0;
5927
5928loopback_test_done:
5929 bp->loopback = 0;
5930 return ret;
5931}
5932
bc5a0690
MC		 5933#define BNX2_MAC_LOOPBACK_FAILED 1
5934#define BNX2_PHY_LOOPBACK_FAILED 2
5935#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5936 BNX2_PHY_LOOPBACK_FAILED)
5937
5938static int
5939bnx2_test_loopback(struct bnx2 *bp)
5940{
5941 int rc = 0;
5942
5943 if (!netif_running(bp->dev))
5944 return BNX2_LOOPBACK_FAILED;
5945
5946 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5947 spin_lock_bh(&bp->phy_lock);
9a120bc5 5948 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5949 spin_unlock_bh(&bp->phy_lock);
5950 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5951 rc |= BNX2_MAC_LOOPBACK_FAILED;
5952 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5953 rc |= BNX2_PHY_LOOPBACK_FAILED;
5954 return rc;
5955}
5956
b6016b76
MC		 5957#define NVRAM_SIZE 0x200
5958#define CRC32_RESIDUAL 0xdebb20e3
5959
5960static int
5961bnx2_test_nvram(struct bnx2 *bp)
5962{
b491edd5 5963 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5964 u8 *data = (u8 *) buf;
5965 int rc = 0;
5966 u32 magic, csum;
5967
5968 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5969 goto test_nvram_done;
5970
5971 magic = be32_to_cpu(buf[0]);
5972 if (magic != 0x669955aa) {
5973 rc = -ENODEV;
5974 goto test_nvram_done;
5975 }
5976
5977 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5978 goto test_nvram_done;
5979
5980 csum = ether_crc_le(0x100, data);
5981 if (csum != CRC32_RESIDUAL) {
5982 rc = -ENODEV;
5983 goto test_nvram_done;
5984 }
5985
5986 csum = ether_crc_le(0x100, data + 0x100);
5987 if (csum != CRC32_RESIDUAL) {
5988 rc = -ENODEV;
5989 }
5990
5991test_nvram_done:
5992 return rc;
5993}
5994
5995static int
5996bnx2_test_link(struct bnx2 *bp)
5997{
5998 u32 bmsr;
5999
9f52b564
MC		 6000 if (!netif_running(bp->dev))
6001 return -ENODEV;
6002
583c28e5 6003 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 6004 if (bp->link_up)
6005 return 0;
6006 return -ENODEV;
6007 }
c770a65c 6008 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 6009 bnx2_enable_bmsr1(bp);
6010 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
6011 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
6012 bnx2_disable_bmsr1(bp);
c770a65c 6013 spin_unlock_bh(&bp->phy_lock);
6aa20a22 6014
b6016b76
MC		 6015 if (bmsr & BMSR_LSTATUS) {
6016 return 0;
6017 }
6018 return -ENODEV;
6019}
6020
6021static int
6022bnx2_test_intr(struct bnx2 *bp)
6023{
6024 int i;
b6016b76
MC		 6025 u16 status_idx;
6026
6027 if (!netif_running(bp->dev))
6028 return -ENODEV;
6029
e503e066 6030 status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
b6016b76
MC		 6031
6032 /* This register is not touched during run-time. */
e503e066
MC		 6033 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
6034 BNX2_RD(bp, BNX2_HC_COMMAND);
b6016b76
MC		 6035
6036 for (i = 0; i < 10; i++) {
e503e066 6037 if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
b6016b76
MC		 6038 status_idx) {
6039
6040 break;
6041 }
6042
6043 msleep_interruptible(10);
6044 }
6045 if (i < 10)
6046 return 0;
6047
6048 return -ENODEV;
6049}
6050
38ea3686 6051/* Determining link for parallel detection. */
b2fadeae
MC		 6052static int
6053bnx2_5706_serdes_has_link(struct bnx2 *bp)
6054{
6055 u32 mode_ctl, an_dbg, exp;
6056
38ea3686
MC		 6057 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
6058 return 0;
6059
b2fadeae
MC		 6060 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
6061 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
6062
6063 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
6064 return 0;
6065
6066 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6067 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
6068 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
6069
f3014c0c 6070 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 6071 return 0;
6072
6073 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
6074 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6075 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6076
6077 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
6078 return 0;
6079
6080 return 1;
6081}
6082
b6016b76 6083static void
48b01e2d 6084bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 6085{
b2fadeae
MC		 6086 int check_link = 1;
6087
48b01e2d 6088 spin_lock(&bp->phy_lock);
b2fadeae 6089 if (bp->serdes_an_pending) {
48b01e2d 6090 bp->serdes_an_pending--;
b2fadeae
MC		 6091 check_link = 0;
6092 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 6093 u32 bmcr;
b6016b76 6094
ac392abc 6095 bp->current_interval = BNX2_TIMER_INTERVAL;
cd339a0e 6096
ca58c3af 6097 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6098
48b01e2d 6099 if (bmcr & BMCR_ANENABLE) {
b2fadeae 6100 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 6101 bmcr &= ~BMCR_ANENABLE;
6102 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 6103 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 6104 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 6105 }
b6016b76 6106 }
48b01e2d
MC		 6107 }
6108 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 6109 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 6110 u32 phy2;
b6016b76 6111
48b01e2d
MC		 6112 bnx2_write_phy(bp, 0x17, 0x0f01);
6113 bnx2_read_phy(bp, 0x15, &phy2);
6114 if (phy2 & 0x20) {
6115 u32 bmcr;
cd339a0e 6116
ca58c3af 6117 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 6118 bmcr |= BMCR_ANENABLE;
ca58c3af 6119 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 6120
583c28e5 6121 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 6122 }
6123 } else
ac392abc 6124 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6125
a2724e25 6126 if (check_link) {
b2fadeae
MC		 6127 u32 val;
6128
6129 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6130 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6131 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6132
a2724e25
MC		 6133 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6134 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6135 bnx2_5706s_force_link_dn(bp, 1);
6136 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6137 } else
6138 bnx2_set_link(bp);
6139 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6140 bnx2_set_link(bp);
b2fadeae 6141 }
48b01e2d
MC		 6142 spin_unlock(&bp->phy_lock);
6143}
b6016b76 6144
f8dd064e
MC		 6145static void
6146bnx2_5708_serdes_timer(struct bnx2 *bp)
6147{
583c28e5 6148 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 6149 return;
6150
583c28e5 6151 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 6152 bp->serdes_an_pending = 0;
6153 return;
6154 }
b6016b76 6155
f8dd064e
MC		 6156 spin_lock(&bp->phy_lock);
6157 if (bp->serdes_an_pending)
6158 bp->serdes_an_pending--;
6159 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6160 u32 bmcr;
b6016b76 6161
ca58c3af 6162 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 6163 if (bmcr & BMCR_ANENABLE) {
605a9e20 6164 bnx2_enable_forced_2g5(bp);
40105c0b 6165 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
f8dd064e 6166 } else {
605a9e20 6167 bnx2_disable_forced_2g5(bp);
f8dd064e 6168 bp->serdes_an_pending = 2;
ac392abc 6169 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6170 }
b6016b76 6171
f8dd064e 6172 } else
ac392abc 6173 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6174
f8dd064e
MC		 6175 spin_unlock(&bp->phy_lock);
6176}
6177
48b01e2d 6178static void
e99e88a9 6179bnx2_timer(struct timer_list *t)
48b01e2d 6180{
e99e88a9 6181 struct bnx2 *bp = from_timer(bp, t, timer);
b6016b76 6182
48b01e2d
MC		 6183 if (!netif_running(bp->dev))
6184 return;
b6016b76 6185
48b01e2d
MC		 6186 if (atomic_read(&bp->intr_sem) != 0)
6187 goto bnx2_restart_timer;
b6016b76 6188
efba0180
MC		 6189 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6190 BNX2_FLAG_USING_MSI)
6191 bnx2_chk_missed_msi(bp);
6192
df149d70 6193 bnx2_send_heart_beat(bp);
b6016b76 6194
2726d6e1
MC		 6195 bp->stats_blk->stat_FwRxDrop =
6196 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 6197
02537b06 6198 /* workaround occasional corrupted counters */
61d9e3fa 6199 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
e503e066
MC		 6200 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6201 BNX2_HC_COMMAND_STATS_NOW);
02537b06 6202
583c28e5 6203 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
4ce45e02 6204 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
f8dd064e 6205 bnx2_5706_serdes_timer(bp);
27a005b8 6206 else
f8dd064e 6207 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 6208 }
6209
6210bnx2_restart_timer:
cd339a0e 6211 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6212}
6213
8e6a72c4
MC		 6214static int
6215bnx2_request_irq(struct bnx2 *bp)
6216{
6d866ffc 6217 unsigned long flags;
b4b36042
MC		 6218 struct bnx2_irq *irq;
6219 int rc = 0, i;
8e6a72c4 6220
f86e82fb 6221 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 6222 flags = 0;
6223 else
6224 flags = IRQF_SHARED;
b4b36042
MC		 6225
6226 for (i = 0; i < bp->irq_nvecs; i++) {
6227 irq = &bp->irq_tbl[i];
c76c0475 6228 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
f0ea2e63 6229 &bp->bnx2_napi[i]);
b4b36042
MC		 6230 if (rc)
6231 break;
6232 irq->requested = 1;
6233 }
8e6a72c4
MC		 6234 return rc;
6235}
6236
6237static void
a29ba9d2 6238__bnx2_free_irq(struct bnx2 *bp)
8e6a72c4 6239{
b4b36042
MC		 6240 struct bnx2_irq *irq;
6241 int i;
8e6a72c4 6242
b4b36042
MC		 6243 for (i = 0; i < bp->irq_nvecs; i++) {
6244 irq = &bp->irq_tbl[i];
6245 if (irq->requested)
f0ea2e63 6246 free_irq(irq->vector, &bp->bnx2_napi[i]);
b4b36042 6247 irq->requested = 0;
6d866ffc 6248 }
a29ba9d2
MC		 6249}
6250
6251static void
6252bnx2_free_irq(struct bnx2 *bp)
6253{
6254
6255 __bnx2_free_irq(bp);
f86e82fb 6256 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 6257 pci_disable_msi(bp->pdev);
f86e82fb 6258 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 6259 pci_disable_msix(bp->pdev);
6260
f86e82fb 6261 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 6262}
6263
6264static void
5e9ad9e1 6265bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
b4b36042 6266{
f2a2dfeb 6267 int i, total_vecs;
57851d84 6268 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
4e1d0de9
MC		 6269 struct net_device *dev = bp->dev;
6270 const int len = sizeof(bp->irq_tbl[0].name);
57851d84 6271
b4b36042 6272 bnx2_setup_msix_tbl(bp);
e503e066
MC		 6273 BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6274 BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6275 BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84 6276
e2eb8e38
BL		 6277 /* Need to flush the previous three writes to ensure MSI-X
6278 * is setup properly */
e503e066 6279 BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);
e2eb8e38 6280
57851d84
MC		 6281 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6282 msix_ent[i].entry = i;
6283 msix_ent[i].vector = 0;
6284 }
6285
379b39a2
MC		 6286 total_vecs = msix_vecs;
6287#ifdef BCM_CNIC
6288 total_vecs++;
6289#endif
f2a2dfeb
AG		 6290 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent,
6291 BNX2_MIN_MSIX_VEC, total_vecs);
6292 if (total_vecs < 0)
57851d84
MC		 6293 return;
6294
379b39a2
MC		 6295 msix_vecs = total_vecs;
6296#ifdef BCM_CNIC
6297 msix_vecs--;
6298#endif
5e9ad9e1 6299 bp->irq_nvecs = msix_vecs;
f86e82fb 6300 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
379b39a2 6301 for (i = 0; i < total_vecs; i++) {
57851d84 6302 bp->irq_tbl[i].vector = msix_ent[i].vector;
69010313
MC		 6303 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6304 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6305 }
6d866ffc
MC		 6306}
6307
657d92fe 6308static int
6d866ffc
MC		 6309bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6310{
0a742128 6311 int cpus = netif_get_num_default_rss_queues();
b033281f
MC		 6312 int msix_vecs;
6313
6314 if (!bp->num_req_rx_rings)
6315 msix_vecs = max(cpus + 1, bp->num_req_tx_rings);
6316 else if (!bp->num_req_tx_rings)
6317 msix_vecs = max(cpus, bp->num_req_rx_rings);
6318 else
6319 msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings);
6320
6321 msix_vecs = min(msix_vecs, RX_MAX_RINGS);
5e9ad9e1 6322
6d866ffc
MC		 6323 bp->irq_tbl[0].handler = bnx2_interrupt;
6324 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 6325 bp->irq_nvecs = 1;
6326 bp->irq_tbl[0].vector = bp->pdev->irq;
6327
3d5f3a7b 6328 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5e9ad9e1 6329 bnx2_enable_msix(bp, msix_vecs);
6d866ffc 6330
f86e82fb
DM		 6331 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6332 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 6333 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 6334 bp->flags |= BNX2_FLAG_USING_MSI;
4ce45e02 6335 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
f86e82fb 6336 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 6337 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6338 } else
6339 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 6340
6341 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 6342 }
6343 }
706bf240 6344
b033281f
MC		 6345 if (!bp->num_req_tx_rings)
6346 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6347 else
6348 bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings);
6349
6350 if (!bp->num_req_rx_rings)
6351 bp->num_rx_rings = bp->irq_nvecs;
6352 else
6353 bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings);
6354
657d92fe 6355 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
706bf240 6356
657d92fe 6357 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
8e6a72c4
MC		 6358}
6359
b6016b76
MC		 6360/* Called with rtnl_lock */
6361static int
6362bnx2_open(struct net_device *dev)
6363{
972ec0d4 6364 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6365 int rc;
6366
5d0d4b91
BH		 6367 rc = bnx2_request_firmware(bp);
6368 if (rc < 0)
6369 goto out;
6370
1b2f922f
MC		 6371 netif_carrier_off(dev);
6372
b6016b76
MC		 6373 bnx2_disable_int(bp);
6374
657d92fe
BH		 6375 rc = bnx2_setup_int_mode(bp, disable_msi);
6376 if (rc)
6377 goto open_err;
4327ba43 6378 bnx2_init_napi(bp);
35e9010b 6379 bnx2_napi_enable(bp);
b6016b76 6380 rc = bnx2_alloc_mem(bp);
2739a8bb
MC		 6381 if (rc)
6382 goto open_err;
b6016b76 6383
8e6a72c4 6384 rc = bnx2_request_irq(bp);
2739a8bb
MC		 6385 if (rc)
6386 goto open_err;
b6016b76 6387
9a120bc5 6388 rc = bnx2_init_nic(bp, 1);
2739a8bb
MC		 6389 if (rc)
6390 goto open_err;
6aa20a22 6391
cd339a0e 6392 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6393
6394 atomic_set(&bp->intr_sem, 0);
6395
354fcd77
MC		 6396 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6397
b6016b76
MC		 6398 bnx2_enable_int(bp);
6399
f86e82fb 6400 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 6401 /* Test MSI to make sure it is working
6402 * If MSI test fails, go back to INTx mode
6403 */
6404 if (bnx2_test_intr(bp) != 0) {
3a9c6a49 6405 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
b6016b76
MC		 6406
6407 bnx2_disable_int(bp);
8e6a72c4 6408 bnx2_free_irq(bp);
b6016b76 6409
6d866ffc
MC		 6410 bnx2_setup_int_mode(bp, 1);
6411
9a120bc5 6412 rc = bnx2_init_nic(bp, 0);
b6016b76 6413
8e6a72c4
MC		 6414 if (!rc)
6415 rc = bnx2_request_irq(bp);
6416
b6016b76 6417 if (rc) {
b6016b76 6418 del_timer_sync(&bp->timer);
2739a8bb 6419 goto open_err;
b6016b76
MC		 6420 }
6421 bnx2_enable_int(bp);
6422 }
6423 }
f86e82fb 6424 if (bp->flags & BNX2_FLAG_USING_MSI)
3a9c6a49 6425 netdev_info(dev, "using MSI\n");
f86e82fb 6426 else if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49 6427 netdev_info(dev, "using MSIX\n");
b6016b76 6428
706bf240 6429 netif_tx_start_all_queues(dev);
7880b72e 6430out:
6431 return rc;
2739a8bb
MC		 6432
6433open_err:
6434 bnx2_napi_disable(bp);
6435 bnx2_free_skbs(bp);
6436 bnx2_free_irq(bp);
6437 bnx2_free_mem(bp);
f048fa9c 6438 bnx2_del_napi(bp);
5d0d4b91 6439 bnx2_release_firmware(bp);
7880b72e 6440 goto out;
b6016b76
MC		 6441}
6442
6443static void
c4028958 6444bnx2_reset_task(struct work_struct *work)
b6016b76 6445{
c4028958 6446 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
cd634019 6447 int rc;
efdfad32 6448 u16 pcicmd;
b6016b76 6449
51bf6bb4
MC		 6450 rtnl_lock();
6451 if (!netif_running(bp->dev)) {
6452 rtnl_unlock();
afdc08b9 6453 return;
51bf6bb4 6454 }
afdc08b9 6455
212f9934 6456 bnx2_netif_stop(bp, true);
b6016b76 6457
efdfad32
MC		 6458 pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd);
6459 if (!(pcicmd & PCI_COMMAND_MEMORY)) {
6460 /* in case PCI block has reset */
6461 pci_restore_state(bp->pdev);
6462 pci_save_state(bp->pdev);
6463 }
cd634019
MC		 6464 rc = bnx2_init_nic(bp, 1);
6465 if (rc) {
6466 netdev_err(bp->dev, "failed to reset NIC, closing\n");
6467 bnx2_napi_enable(bp);
6468 dev_close(bp->dev);
6469 rtnl_unlock();
6470 return;
6471 }
b6016b76
MC		 6472
6473 atomic_set(&bp->intr_sem, 1);
212f9934 6474 bnx2_netif_start(bp, true);
51bf6bb4 6475 rtnl_unlock();
b6016b76
MC		 6476}
6477
555069da
MC		 6478#define BNX2_FTQ_ENTRY(ftq) { __stringify(ftq##FTQ_CTL), BNX2_##ftq##FTQ_CTL }
6479
6480static void
6481bnx2_dump_ftq(struct bnx2 *bp)
6482{
6483 int i;
6484 u32 reg, bdidx, cid, valid;
6485 struct net_device *dev = bp->dev;
6486 static const struct ftq_reg {
6487 char *name;
6488 u32 off;
6489 } ftq_arr[] = {
6490 BNX2_FTQ_ENTRY(RV2P_P),
6491 BNX2_FTQ_ENTRY(RV2P_T),
6492 BNX2_FTQ_ENTRY(RV2P_M),
6493 BNX2_FTQ_ENTRY(TBDR_),
6494 BNX2_FTQ_ENTRY(TDMA_),
6495 BNX2_FTQ_ENTRY(TXP_),
6496 BNX2_FTQ_ENTRY(TXP_),
6497 BNX2_FTQ_ENTRY(TPAT_),
6498 BNX2_FTQ_ENTRY(RXP_C),
6499 BNX2_FTQ_ENTRY(RXP_),
6500 BNX2_FTQ_ENTRY(COM_COMXQ_),
6501 BNX2_FTQ_ENTRY(COM_COMTQ_),
6502 BNX2_FTQ_ENTRY(COM_COMQ_),
6503 BNX2_FTQ_ENTRY(CP_CPQ_),
6504 };
6505
6506 netdev_err(dev, "<--- start FTQ dump --->\n");
6507 for (i = 0; i < ARRAY_SIZE(ftq_arr); i++)
6508 netdev_err(dev, "%s %08x\n", ftq_arr[i].name,
6509 bnx2_reg_rd_ind(bp, ftq_arr[i].off));
6510
6511 netdev_err(dev, "CPU states:\n");
6512 for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000)
6513 netdev_err(dev, "%06x mode %x state %x evt_mask %x pc %x pc %x instr %x\n",
6514 reg, bnx2_reg_rd_ind(bp, reg),
6515 bnx2_reg_rd_ind(bp, reg + 4),
6516 bnx2_reg_rd_ind(bp, reg + 8),
6517 bnx2_reg_rd_ind(bp, reg + 0x1c),
6518 bnx2_reg_rd_ind(bp, reg + 0x1c),
6519 bnx2_reg_rd_ind(bp, reg + 0x20));
6520
6521 netdev_err(dev, "<--- end FTQ dump --->\n");
6522 netdev_err(dev, "<--- start TBDC dump --->\n");
6523 netdev_err(dev, "TBDC free cnt: %ld\n",
e503e066 6524 BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);
555069da
MC		 6525 netdev_err(dev, "LINE CID BIDX CMD VALIDS\n");
6526 for (i = 0; i < 0x20; i++) {
6527 int j = 0;
6528
e503e066
MC		 6529 BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);
6530 BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,
6531 BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ);
6532 BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);
6533 while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &
555069da
MC		 6534 BNX2_TBDC_COMMAND_CMD_REG_ARB) && j < 100)
6535 j++;
6536
e503e066
MC		 6537 cid = BNX2_RD(bp, BNX2_TBDC_CID);
6538 bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);
6539 valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);
555069da
MC		 6540 netdev_err(dev, "%02x %06x %04lx %02x [%x]\n",
6541 i, cid, bdidx & BNX2_TBDC_BDIDX_BDIDX,
6542 bdidx >> 24, (valid >> 8) & 0x0ff);
6543 }
6544 netdev_err(dev, "<--- end TBDC dump --->\n");
6545}
6546
20175c57
MC		 6547static void
6548bnx2_dump_state(struct bnx2 *bp)
6549{
6550 struct net_device *dev = bp->dev;
ecdbf6e0 6551 u32 val1, val2;
5804a8fb
MC		 6552
6553 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6554 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6555 atomic_read(&bp->intr_sem), val1);
6556 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6557 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6558 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
b98eba52 6559 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
e503e066
MC		 6560 BNX2_RD(bp, BNX2_EMAC_TX_STATUS),
6561 BNX2_RD(bp, BNX2_EMAC_RX_STATUS));
b98eba52 6562 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
e503e066 6563 BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
3a9c6a49 6564 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
e503e066 6565 BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
20175c57 6566 if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49 6567 netdev_err(dev, "DEBUG: PBA[%08x]\n",
e503e066 6568 BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
20175c57
MC		 6569}
6570
b6016b76 6571static void
0290bd29 6572bnx2_tx_timeout(struct net_device *dev, unsigned int txqueue)
b6016b76 6573{
972ec0d4 6574 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6575
555069da 6576 bnx2_dump_ftq(bp);
20175c57 6577 bnx2_dump_state(bp);
ecdbf6e0 6578 bnx2_dump_mcp_state(bp);
20175c57 6579
b6016b76
MC		 6580 /* This allows the netif to be shutdown gracefully before resetting */
6581 schedule_work(&bp->reset_task);
6582}
6583
932ff279 6584/* Called with netif_tx_lock.
2f8af120
MC		 6585 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6586 * netif_wake_queue().
b6016b76 6587 */
61357325 6588static netdev_tx_t
b6016b76
MC		 6589bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6590{
972ec0d4 6591 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6592 dma_addr_t mapping;
2bc4078e
MC		 6593 struct bnx2_tx_bd *txbd;
6594 struct bnx2_sw_tx_bd *tx_buf;
b6016b76
MC		 6595 u32 len, vlan_tag_flags, last_frag, mss;
6596 u16 prod, ring_prod;
6597 int i;
706bf240
BL		 6598 struct bnx2_napi *bnapi;
6599 struct bnx2_tx_ring_info *txr;
6600 struct netdev_queue *txq;
6601
6602 /* Determine which tx ring we will be placed on */
6603 i = skb_get_queue_mapping(skb);
6604 bnapi = &bp->bnx2_napi[i];
6605 txr = &bnapi->tx_ring;
6606 txq = netdev_get_tx_queue(dev, i);
b6016b76 6607
35e9010b 6608 if (unlikely(bnx2_tx_avail(bp, txr) <
a550c99b 6609 (skb_shinfo(skb)->nr_frags + 1))) {
706bf240 6610 netif_tx_stop_queue(txq);
3a9c6a49 6611 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
b6016b76
MC		 6612
6613 return NETDEV_TX_BUSY;
6614 }
6615 len = skb_headlen(skb);
35e9010b 6616 prod = txr->tx_prod;
2bc4078e 6617 ring_prod = BNX2_TX_RING_IDX(prod);
b6016b76
MC		 6618
6619 vlan_tag_flags = 0;
84fa7933 6620 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 6621 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6622 }
6623
df8a39de 6624 if (skb_vlan_tag_present(skb)) {
b6016b76 6625 vlan_tag_flags |=
df8a39de 6626 (TX_BD_FLAGS_VLAN_TAG | (skb_vlan_tag_get(skb) << 16));
b6016b76 6627 }
7d0fd211 6628
fde82055 6629 if ((mss = skb_shinfo(skb)->gso_size)) {
a1efb4b6 6630 u32 tcp_opt_len;
eddc9ec5 6631 struct iphdr *iph;
b6016b76 6632
b6016b76
MC		 6633 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6634
4666f87a
MC		 6635 tcp_opt_len = tcp_optlen(skb);
6636
6637 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6638 u32 tcp_off = skb_transport_offset(skb) -
6639 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 6640
4666f87a
MC		 6641 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6642 TX_BD_FLAGS_SW_FLAGS;
6643 if (likely(tcp_off == 0))
6644 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6645 else {
6646 tcp_off >>= 3;
6647 vlan_tag_flags |= ((tcp_off & 0x3) <<
6648 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6649 ((tcp_off & 0x10) <<
6650 TX_BD_FLAGS_TCP6_OFF4_SHL);
6651 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6652 }
6653 } else {
4666f87a 6654 iph = ip_hdr(skb);
4666f87a
MC		 6655 if (tcp_opt_len || (iph->ihl > 5)) {
6656 vlan_tag_flags |= ((iph->ihl - 5) +
6657 (tcp_opt_len >> 2)) << 8;
6658 }
b6016b76 6659 }
4666f87a 6660 } else
b6016b76 6661 mss = 0;
b6016b76 6662
36227e88
SG		 6663 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
6664 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
f458b2ee 6665 dev_kfree_skb_any(skb);
3d16af86
BL		 6666 return NETDEV_TX_OK;
6667 }
6668
35e9010b 6669 tx_buf = &txr->tx_buf_ring[ring_prod];
b6016b76 6670 tx_buf->skb = skb;
1a4ccc2d 6671 dma_unmap_addr_set(tx_buf, mapping, mapping);
b6016b76 6672
35e9010b 6673 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6674
6675 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6676 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6677 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6678 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6679
6680 last_frag = skb_shinfo(skb)->nr_frags;
d62fda08
ED		 6681 tx_buf->nr_frags = last_frag;
6682 tx_buf->is_gso = skb_is_gso(skb);
b6016b76
MC		 6683
6684 for (i = 0; i < last_frag; i++) {
9e903e08 6685 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
b6016b76 6686
2bc4078e
MC		 6687 prod = BNX2_NEXT_TX_BD(prod);
6688 ring_prod = BNX2_TX_RING_IDX(prod);
35e9010b 6689 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76 6690
9e903e08 6691 len = skb_frag_size(frag);
b7b6a688 6692 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,
5d6bcdfe 6693 DMA_TO_DEVICE);
36227e88 6694 if (dma_mapping_error(&bp->pdev->dev, mapping))
e95524a7 6695 goto dma_error;
1a4ccc2d 6696 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
e95524a7 6697 mapping);
b6016b76
MC		 6698
6699 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6700 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6701 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6702 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6703
6704 }
6705 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6706
94bf91ba
VZ		 6707 /* Sync BD data before updating TX mailbox */
6708 wmb();
6709
e9831909
ED		 6710 netdev_tx_sent_queue(txq, skb->len);
6711
2bc4078e 6712 prod = BNX2_NEXT_TX_BD(prod);
35e9010b 6713 txr->tx_prod_bseq += skb->len;
b6016b76 6714
e503e066
MC		 6715 BNX2_WR16(bp, txr->tx_bidx_addr, prod);
6716 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76 6717
35e9010b 6718 txr->tx_prod = prod;
b6016b76 6719
35e9010b 6720 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
706bf240 6721 netif_tx_stop_queue(txq);
11848b96
MC		 6722
6723 /* netif_tx_stop_queue() must be done before checking
6724 * tx index in bnx2_tx_avail() below, because in
6725 * bnx2_tx_int(), we update tx index before checking for
6726 * netif_tx_queue_stopped().
6727 */
6728 smp_mb();
35e9010b 6729 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
706bf240 6730 netif_tx_wake_queue(txq);
b6016b76
MC		 6731 }
6732
e95524a7
AD		 6733 return NETDEV_TX_OK;
6734dma_error:
6735 /* save value of frag that failed */
6736 last_frag = i;
6737
6738 /* start back at beginning and unmap skb */
6739 prod = txr->tx_prod;
2bc4078e 6740 ring_prod = BNX2_TX_RING_IDX(prod);
e95524a7
AD		 6741 tx_buf = &txr->tx_buf_ring[ring_prod];
6742 tx_buf->skb = NULL;
36227e88 6743 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6744 skb_headlen(skb), PCI_DMA_TODEVICE);
6745
6746 /* unmap remaining mapped pages */
6747 for (i = 0; i < last_frag; i++) {
2bc4078e
MC		 6748 prod = BNX2_NEXT_TX_BD(prod);
6749 ring_prod = BNX2_TX_RING_IDX(prod);
e95524a7 6750 tx_buf = &txr->tx_buf_ring[ring_prod];
36227e88 6751 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
9e903e08 6752 skb_frag_size(&skb_shinfo(skb)->frags[i]),
e95524a7
AD		 6753 PCI_DMA_TODEVICE);
6754 }
6755
f458b2ee 6756 dev_kfree_skb_any(skb);
b6016b76
MC		 6757 return NETDEV_TX_OK;
6758}
6759
6760/* Called with rtnl_lock */
6761static int
6762bnx2_close(struct net_device *dev)
6763{
972ec0d4 6764 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6765
bea3348e 6766 bnx2_disable_int_sync(bp);
35efa7c1 6767 bnx2_napi_disable(bp);
d2e553bc 6768 netif_tx_disable(dev);
b6016b76 6769 del_timer_sync(&bp->timer);
74bf4ba3 6770 bnx2_shutdown_chip(bp);
8e6a72c4 6771 bnx2_free_irq(bp);
b6016b76
MC		 6772 bnx2_free_skbs(bp);
6773 bnx2_free_mem(bp);
f048fa9c 6774 bnx2_del_napi(bp);
b6016b76
MC		 6775 bp->link_up = 0;
6776 netif_carrier_off(bp->dev);
b6016b76
MC		 6777 return 0;
6778}
6779
354fcd77
MC		 6780static void
6781bnx2_save_stats(struct bnx2 *bp)
6782{
6783 u32 *hw_stats = (u32 *) bp->stats_blk;
6784 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6785 int i;
6786
6787 /* The 1st 10 counters are 64-bit counters */
6788 for (i = 0; i < 20; i += 2) {
6789 u32 hi;
6790 u64 lo;
6791
c9885fe5
PR		 6792 hi = temp_stats[i] + hw_stats[i];
6793 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
354fcd77
MC		 6794 if (lo > 0xffffffff)
6795 hi++;
c9885fe5
PR		 6796 temp_stats[i] = hi;
6797 temp_stats[i + 1] = lo & 0xffffffff;
354fcd77
MC		 6798 }
6799
6800 for ( ; i < sizeof(struct statistics_block) / 4; i++)
c9885fe5 6801 temp_stats[i] += hw_stats[i];
354fcd77
MC		 6802}
6803
5d07bf26
ED		 6804#define GET_64BIT_NET_STATS64(ctr) \
6805 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
b6016b76 6806
a4743058 6807#define GET_64BIT_NET_STATS(ctr) \
354fcd77
MC		 6808 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6809 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
b6016b76 6810
a4743058 6811#define GET_32BIT_NET_STATS(ctr) \
354fcd77
MC		 6812 (unsigned long) (bp->stats_blk->ctr + \
6813 bp->temp_stats_blk->ctr)
a4743058 6814
bc1f4470 6815static void
5d07bf26 6816bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
b6016b76 6817{
972ec0d4 6818 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6819
b8aac410 6820 if (!bp->stats_blk)
bc1f4470 6821 return;
5d07bf26 6822
b6016b76 6823 net_stats->rx_packets =
a4743058
MC		 6824 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6825 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6826 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
b6016b76
MC		 6827
6828 net_stats->tx_packets =
a4743058
MC		 6829 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6830 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6831 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
b6016b76
MC		 6832
6833 net_stats->rx_bytes =
a4743058 6834 GET_64BIT_NET_STATS(stat_IfHCInOctets);
b6016b76
MC		 6835
6836 net_stats->tx_bytes =
a4743058 6837 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
b6016b76 6838
6aa20a22 6839 net_stats->multicast =
6fdae995 6840 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
b6016b76 6841
6aa20a22 6842 net_stats->collisions =
a4743058 6843 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
b6016b76 6844
6aa20a22 6845 net_stats->rx_length_errors =
a4743058
MC		 6846 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6847 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
b6016b76 6848
6aa20a22 6849 net_stats->rx_over_errors =
a4743058
MC		 6850 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6851 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
b6016b76 6852
6aa20a22 6853 net_stats->rx_frame_errors =
a4743058 6854 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
b6016b76 6855
6aa20a22 6856 net_stats->rx_crc_errors =
a4743058 6857 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
b6016b76
MC		 6858
6859 net_stats->rx_errors = net_stats->rx_length_errors +
6860 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6861 net_stats->rx_crc_errors;
6862
6863 net_stats->tx_aborted_errors =
a4743058
MC		 6864 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6865 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
b6016b76 6866
4ce45e02
MC		 6867 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
6868 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))
b6016b76
MC		 6869 net_stats->tx_carrier_errors = 0;
6870 else {
6871 net_stats->tx_carrier_errors =
a4743058 6872 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
b6016b76
MC		 6873 }
6874
6875 net_stats->tx_errors =
a4743058 6876 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
b6016b76
MC		 6877 net_stats->tx_aborted_errors +
6878 net_stats->tx_carrier_errors;
6879
cea94db9 6880 net_stats->rx_missed_errors =
a4743058
MC		 6881 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6882 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6883 GET_32BIT_NET_STATS(stat_FwRxDrop);
cea94db9 6884
b6016b76
MC		 6885}
6886
6887/* All ethtool functions called with rtnl_lock */
6888
6889static int
08e10d4d
PR		 6890bnx2_get_link_ksettings(struct net_device *dev,
6891 struct ethtool_link_ksettings *cmd)
b6016b76 6892{
972ec0d4 6893 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6894 int support_serdes = 0, support_copper = 0;
08e10d4d 6895 u32 supported, advertising;
b6016b76 6896
08e10d4d 6897 supported = SUPPORTED_Autoneg;
583c28e5 6898 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6899 support_serdes = 1;
6900 support_copper = 1;
6901 } else if (bp->phy_port == PORT_FIBRE)
6902 support_serdes = 1;
6903 else
6904 support_copper = 1;
6905
6906 if (support_serdes) {
08e10d4d 6907 supported |= SUPPORTED_1000baseT_Full |
b6016b76 6908 SUPPORTED_FIBRE;
583c28e5 6909 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
08e10d4d 6910 supported |= SUPPORTED_2500baseX_Full;
b6016b76 6911 }
7b6b8347 6912 if (support_copper) {
08e10d4d 6913 supported |= SUPPORTED_10baseT_Half |
b6016b76
MC		 6914 SUPPORTED_10baseT_Full |
6915 SUPPORTED_100baseT_Half |
6916 SUPPORTED_100baseT_Full |
6917 SUPPORTED_1000baseT_Full |
6918 SUPPORTED_TP;
b6016b76
MC		 6919 }
6920
7b6b8347 6921 spin_lock_bh(&bp->phy_lock);
08e10d4d
PR		 6922 cmd->base.port = bp->phy_port;
6923 advertising = bp->advertising;
b6016b76
MC		 6924
6925 if (bp->autoneg & AUTONEG_SPEED) {
08e10d4d 6926 cmd->base.autoneg = AUTONEG_ENABLE;
70739497 6927 } else {
08e10d4d 6928 cmd->base.autoneg = AUTONEG_DISABLE;
b6016b76
MC		 6929 }
6930
6931 if (netif_carrier_ok(dev)) {
08e10d4d
PR		 6932 cmd->base.speed = bp->line_speed;
6933 cmd->base.duplex = bp->duplex;
4016badd
MC		 6934 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) {
6935 if (bp->phy_flags & BNX2_PHY_FLAG_MDIX)
08e10d4d 6936 cmd->base.eth_tp_mdix = ETH_TP_MDI_X;
4016badd 6937 else
08e10d4d 6938 cmd->base.eth_tp_mdix = ETH_TP_MDI;
4016badd 6939 }
b6016b76
MC		 6940 }
6941 else {
08e10d4d
PR		 6942 cmd->base.speed = SPEED_UNKNOWN;
6943 cmd->base.duplex = DUPLEX_UNKNOWN;
b6016b76 6944 }
7b6b8347 6945 spin_unlock_bh(&bp->phy_lock);
b6016b76 6946
08e10d4d
PR		 6947 cmd->base.phy_address = bp->phy_addr;
6948
6949 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
6950 supported);
6951 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
6952 advertising);
b6016b76
MC		 6953
6954 return 0;
6955}
6aa20a22 6956
b6016b76 6957static int
08e10d4d
PR		 6958bnx2_set_link_ksettings(struct net_device *dev,
6959 const struct ethtool_link_ksettings *cmd)
b6016b76 6960{
972ec0d4 6961 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6962 u8 autoneg = bp->autoneg;
6963 u8 req_duplex = bp->req_duplex;
6964 u16 req_line_speed = bp->req_line_speed;
6965 u32 advertising = bp->advertising;
7b6b8347
MC		 6966 int err = -EINVAL;
6967
6968 spin_lock_bh(&bp->phy_lock);
6969
08e10d4d 6970 if (cmd->base.port != PORT_TP && cmd->base.port != PORT_FIBRE)
7b6b8347
MC		 6971 goto err_out_unlock;
6972
08e10d4d 6973 if (cmd->base.port != bp->phy_port &&
583c28e5 6974 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6975 goto err_out_unlock;
b6016b76 6976
d6b14486
MC		 6977 /* If device is down, we can store the settings only if the user
6978 * is setting the currently active port.
6979 */
08e10d4d 6980 if (!netif_running(dev) && cmd->base.port != bp->phy_port)
d6b14486
MC		 6981 goto err_out_unlock;
6982
08e10d4d 6983 if (cmd->base.autoneg == AUTONEG_ENABLE) {
b6016b76
MC		 6984 autoneg |= AUTONEG_SPEED;
6985
08e10d4d
PR		 6986 ethtool_convert_link_mode_to_legacy_u32(
6987 &advertising, cmd->link_modes.advertising);
6988
6989 if (cmd->base.port == PORT_TP) {
beb499af
MC		 6990 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6991 if (!advertising)
b6016b76 6992 advertising = ETHTOOL_ALL_COPPER_SPEED;
beb499af
MC		 6993 } else {
6994 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6995 if (!advertising)
6996 advertising = ETHTOOL_ALL_FIBRE_SPEED;
b6016b76
MC		 6997 }
6998 advertising |= ADVERTISED_Autoneg;
6999 }
7000 else {
08e10d4d
PR		 7001 u32 speed = cmd->base.speed;
7002
7003 if (cmd->base.port == PORT_FIBRE) {
25db0338
DD		 7004 if ((speed != SPEED_1000 &&
7005 speed != SPEED_2500) ||
08e10d4d 7006 (cmd->base.duplex != DUPLEX_FULL))
7b6b8347 7007 goto err_out_unlock;
80be4434 7008
25db0338 7009 if (speed == SPEED_2500 &&
583c28e5 7010 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 7011 goto err_out_unlock;
25db0338 7012 } else if (speed == SPEED_1000 || speed == SPEED_2500)
7b6b8347
MC		 7013 goto err_out_unlock;
7014
b6016b76 7015 autoneg &= ~AUTONEG_SPEED;
25db0338 7016 req_line_speed = speed;
08e10d4d 7017 req_duplex = cmd->base.duplex;
b6016b76
MC		 7018 advertising = 0;
7019 }
7020
7021 bp->autoneg = autoneg;
7022 bp->advertising = advertising;
7023 bp->req_line_speed = req_line_speed;
7024 bp->req_duplex = req_duplex;
7025
d6b14486
MC		 7026 err = 0;
7027 /* If device is down, the new settings will be picked up when it is
7028 * brought up.
7029 */
7030 if (netif_running(dev))
08e10d4d 7031 err = bnx2_setup_phy(bp, cmd->base.port);
b6016b76 7032
7b6b8347 7033err_out_unlock:
c770a65c 7034 spin_unlock_bh(&bp->phy_lock);
b6016b76 7035
7b6b8347 7036 return err;
b6016b76
MC		 7037}
7038
7039static void
7040bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7041{
972ec0d4 7042 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7043
68aad78c 7044 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
68aad78c
RJ		 7045 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
7046 strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));
b6016b76
MC		 7047}
7048
244ac4f4
MC		 7049#define BNX2_REGDUMP_LEN (32 * 1024)
7050
7051static int
7052bnx2_get_regs_len(struct net_device *dev)
7053{
7054 return BNX2_REGDUMP_LEN;
7055}
7056
7057static void
7058bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
7059{
7060 u32 *p = _p, i, offset;
7061 u8 *orig_p = _p;
7062 struct bnx2 *bp = netdev_priv(dev);
b6bc7650
JP		 7063 static const u32 reg_boundaries[] = {
7064 0x0000, 0x0098, 0x0400, 0x045c,
7065 0x0800, 0x0880, 0x0c00, 0x0c10,
7066 0x0c30, 0x0d08, 0x1000, 0x101c,
7067 0x1040, 0x1048, 0x1080, 0x10a4,
7068 0x1400, 0x1490, 0x1498, 0x14f0,
7069 0x1500, 0x155c, 0x1580, 0x15dc,
7070 0x1600, 0x1658, 0x1680, 0x16d8,
7071 0x1800, 0x1820, 0x1840, 0x1854,
7072 0x1880, 0x1894, 0x1900, 0x1984,
7073 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
7074 0x1c80, 0x1c94, 0x1d00, 0x1d84,
7075 0x2000, 0x2030, 0x23c0, 0x2400,
7076 0x2800, 0x2820, 0x2830, 0x2850,
7077 0x2b40, 0x2c10, 0x2fc0, 0x3058,
7078 0x3c00, 0x3c94, 0x4000, 0x4010,
7079 0x4080, 0x4090, 0x43c0, 0x4458,
7080 0x4c00, 0x4c18, 0x4c40, 0x4c54,
7081 0x4fc0, 0x5010, 0x53c0, 0x5444,
7082 0x5c00, 0x5c18, 0x5c80, 0x5c90,
7083 0x5fc0, 0x6000, 0x6400, 0x6428,
7084 0x6800, 0x6848, 0x684c, 0x6860,
7085 0x6888, 0x6910, 0x8000
7086 };
244ac4f4
MC		 7087
7088 regs->version = 0;
7089
7090 memset(p, 0, BNX2_REGDUMP_LEN);
7091
7092 if (!netif_running(bp->dev))
7093 return;
7094
7095 i = 0;
7096 offset = reg_boundaries[0];
7097 p += offset;
7098 while (offset < BNX2_REGDUMP_LEN) {
e503e066 7099 *p++ = BNX2_RD(bp, offset);
244ac4f4
MC		 7100 offset += 4;
7101 if (offset == reg_boundaries[i + 1]) {
7102 offset = reg_boundaries[i + 2];
7103 p = (u32 *) (orig_p + offset);
7104 i += 2;
7105 }
7106 }
7107}
7108
b6016b76
MC		 7109static void
7110bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7111{
972ec0d4 7112 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7113
f86e82fb 7114 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 7115 wol->supported = 0;
7116 wol->wolopts = 0;
7117 }
7118 else {
7119 wol->supported = WAKE_MAGIC;
7120 if (bp->wol)
7121 wol->wolopts = WAKE_MAGIC;
7122 else
7123 wol->wolopts = 0;
7124 }
7125 memset(&wol->sopass, 0, sizeof(wol->sopass));
7126}
7127
7128static int
7129bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7130{
972ec0d4 7131 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7132
7133 if (wol->wolopts & ~WAKE_MAGIC)
7134 return -EINVAL;
7135
7136 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 7137 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 7138 return -EINVAL;
7139
7140 bp->wol = 1;
7141 }
7142 else {
7143 bp->wol = 0;
7144 }
6d5e85c7
MC		 7145
7146 device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
7147
b6016b76
MC		 7148 return 0;
7149}
7150
7151static int
7152bnx2_nway_reset(struct net_device *dev)
7153{
972ec0d4 7154 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7155 u32 bmcr;
7156
9f52b564
MC		 7157 if (!netif_running(dev))
7158 return -EAGAIN;
7159
b6016b76
MC		 7160 if (!(bp->autoneg & AUTONEG_SPEED)) {
7161 return -EINVAL;
7162 }
7163
c770a65c 7164 spin_lock_bh(&bp->phy_lock);
b6016b76 7165
583c28e5 7166 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 7167 int rc;
7168
7169 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
7170 spin_unlock_bh(&bp->phy_lock);
7171 return rc;
7172 }
7173
b6016b76 7174 /* Force a link down visible on the other side */
583c28e5 7175 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 7176 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 7177 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7178
7179 msleep(20);
7180
c770a65c 7181 spin_lock_bh(&bp->phy_lock);
f8dd064e 7182
40105c0b 7183 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 7184 bp->serdes_an_pending = 1;
7185 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 7186 }
7187
ca58c3af 7188 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 7189 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 7190 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 7191
c770a65c 7192 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7193
7194 return 0;
7195}
7196
7959ea25
ON		 7197static u32
7198bnx2_get_link(struct net_device *dev)
7199{
7200 struct bnx2 *bp = netdev_priv(dev);
7201
7202 return bp->link_up;
7203}
7204
b6016b76
MC		 7205static int
7206bnx2_get_eeprom_len(struct net_device *dev)
7207{
972ec0d4 7208 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7209
b8aac410 7210 if (!bp->flash_info)
b6016b76
MC		 7211 return 0;
7212
1122db71 7213 return (int) bp->flash_size;
b6016b76
MC		 7214}
7215
7216static int
7217bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7218 u8 *eebuf)
7219{
972ec0d4 7220 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7221 int rc;
7222
1064e944 7223 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 7224
7225 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7226
7227 return rc;
7228}
7229
7230static int
7231bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7232 u8 *eebuf)
7233{
972ec0d4 7234 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7235 int rc;
7236
1064e944 7237 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 7238
7239 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7240
7241 return rc;
7242}
7243
7244static int
7245bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7246{
972ec0d4 7247 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7248
7249 memset(coal, 0, sizeof(struct ethtool_coalesce));
7250
7251 coal->rx_coalesce_usecs = bp->rx_ticks;
7252 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7253 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7254 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7255
7256 coal->tx_coalesce_usecs = bp->tx_ticks;
7257 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7258 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7259 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7260
7261 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7262
7263 return 0;
7264}
7265
7266static int
7267bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7268{
972ec0d4 7269 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7270
7271 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7272 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7273
6aa20a22 7274 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 7275 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7276
7277 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7278 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7279
7280 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7281 if (bp->rx_quick_cons_trip_int > 0xff)
7282 bp->rx_quick_cons_trip_int = 0xff;
7283
7284 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7285 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7286
7287 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7288 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7289
7290 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7291 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7292
7293 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7294 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7295 0xff;
7296
7297 bp->stats_ticks = coal->stats_block_coalesce_usecs;
61d9e3fa 7298 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
02537b06
MC		 7299 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7300 bp->stats_ticks = USEC_PER_SEC;
7301 }
7ea6920e
MC		 7302 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7303 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7304 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7305
7306 if (netif_running(bp->dev)) {
212f9934 7307 bnx2_netif_stop(bp, true);
9a120bc5 7308 bnx2_init_nic(bp, 0);
212f9934 7309 bnx2_netif_start(bp, true);
b6016b76
MC		 7310 }
7311
7312 return 0;
7313}
7314
7315static void
7316bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7317{
972ec0d4 7318 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7319
2bc4078e
MC		 7320 ering->rx_max_pending = BNX2_MAX_TOTAL_RX_DESC_CNT;
7321 ering->rx_jumbo_max_pending = BNX2_MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 7322
7323 ering->rx_pending = bp->rx_ring_size;
47bf4246 7324 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76 7325
2bc4078e 7326 ering->tx_max_pending = BNX2_MAX_TX_DESC_CNT;
b6016b76
MC		 7327 ering->tx_pending = bp->tx_ring_size;
7328}
7329
7330static int
b033281f 7331bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq)
b6016b76 7332{
13daffa2 7333 if (netif_running(bp->dev)) {
354fcd77
MC		 7334 /* Reset will erase chipset stats; save them */
7335 bnx2_save_stats(bp);
7336
212f9934 7337 bnx2_netif_stop(bp, true);
13daffa2 7338 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
b033281f
MC		 7339 if (reset_irq) {
7340 bnx2_free_irq(bp);
7341 bnx2_del_napi(bp);
7342 } else {
7343 __bnx2_free_irq(bp);
7344 }
13daffa2
MC		 7345 bnx2_free_skbs(bp);
7346 bnx2_free_mem(bp);
7347 }
7348
5d5d0015
MC		 7349 bnx2_set_rx_ring_size(bp, rx);
7350 bp->tx_ring_size = tx;
b6016b76
MC		 7351
7352 if (netif_running(bp->dev)) {
b033281f
MC		 7353 int rc = 0;
7354
7355 if (reset_irq) {
7356 rc = bnx2_setup_int_mode(bp, disable_msi);
7357 bnx2_init_napi(bp);
7358 }
7359
7360 if (!rc)
7361 rc = bnx2_alloc_mem(bp);
13daffa2 7362
a29ba9d2
MC		 7363 if (!rc)
7364 rc = bnx2_request_irq(bp);
7365
6fefb65e
MC		 7366 if (!rc)
7367 rc = bnx2_init_nic(bp, 0);
7368
7369 if (rc) {
7370 bnx2_napi_enable(bp);
7371 dev_close(bp->dev);
13daffa2 7372 return rc;
6fefb65e 7373 }
e9f26c49
MC		 7374#ifdef BCM_CNIC
7375 mutex_lock(&bp->cnic_lock);
7376 /* Let cnic know about the new status block. */
7377 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7378 bnx2_setup_cnic_irq_info(bp);
7379 mutex_unlock(&bp->cnic_lock);
7380#endif
212f9934 7381 bnx2_netif_start(bp, true);
b6016b76 7382 }
b6016b76
MC		 7383 return 0;
7384}
7385
5d5d0015
MC		 7386static int
7387bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7388{
7389 struct bnx2 *bp = netdev_priv(dev);
7390 int rc;
7391
2bc4078e
MC		 7392 if ((ering->rx_pending > BNX2_MAX_TOTAL_RX_DESC_CNT) ||
7393 (ering->tx_pending > BNX2_MAX_TX_DESC_CNT) ||
5d5d0015
MC		 7394 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7395
7396 return -EINVAL;
7397 }
b033281f
MC		 7398 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending,
7399 false);
5d5d0015
MC		 7400 return rc;
7401}
7402
b6016b76
MC		 7403static void
7404bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7405{
972ec0d4 7406 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7407
7408 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7409 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7410 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7411}
7412
7413static int
7414bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7415{
972ec0d4 7416 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7417
7418 bp->req_flow_ctrl = 0;
7419 if (epause->rx_pause)
7420 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7421 if (epause->tx_pause)
7422 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7423
7424 if (epause->autoneg) {
7425 bp->autoneg |= AUTONEG_FLOW_CTRL;
7426 }
7427 else {
7428 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7429 }
7430
9f52b564
MC		 7431 if (netif_running(dev)) {
7432 spin_lock_bh(&bp->phy_lock);
7433 bnx2_setup_phy(bp, bp->phy_port);
7434 spin_unlock_bh(&bp->phy_lock);
7435 }
b6016b76
MC		 7436
7437 return 0;
7438}
7439
14ab9b86 7440static struct {
b6016b76 7441 char string[ETH_GSTRING_LEN];
790dab2f 7442} bnx2_stats_str_arr[] = {
b6016b76
MC		 7443 { "rx_bytes" },
7444 { "rx_error_bytes" },
7445 { "tx_bytes" },
7446 { "tx_error_bytes" },
7447 { "rx_ucast_packets" },
7448 { "rx_mcast_packets" },
7449 { "rx_bcast_packets" },
7450 { "tx_ucast_packets" },
7451 { "tx_mcast_packets" },
7452 { "tx_bcast_packets" },
7453 { "tx_mac_errors" },
7454 { "tx_carrier_errors" },
7455 { "rx_crc_errors" },
7456 { "rx_align_errors" },
7457 { "tx_single_collisions" },
7458 { "tx_multi_collisions" },
7459 { "tx_deferred" },
7460 { "tx_excess_collisions" },
7461 { "tx_late_collisions" },
7462 { "tx_total_collisions" },
7463 { "rx_fragments" },
7464 { "rx_jabbers" },
7465 { "rx_undersize_packets" },
7466 { "rx_oversize_packets" },
7467 { "rx_64_byte_packets" },
7468 { "rx_65_to_127_byte_packets" },
7469 { "rx_128_to_255_byte_packets" },
7470 { "rx_256_to_511_byte_packets" },
7471 { "rx_512_to_1023_byte_packets" },
7472 { "rx_1024_to_1522_byte_packets" },
7473 { "rx_1523_to_9022_byte_packets" },
7474 { "tx_64_byte_packets" },
7475 { "tx_65_to_127_byte_packets" },
7476 { "tx_128_to_255_byte_packets" },
7477 { "tx_256_to_511_byte_packets" },
7478 { "tx_512_to_1023_byte_packets" },
7479 { "tx_1024_to_1522_byte_packets" },
7480 { "tx_1523_to_9022_byte_packets" },
7481 { "rx_xon_frames" },
7482 { "rx_xoff_frames" },
7483 { "tx_xon_frames" },
7484 { "tx_xoff_frames" },
7485 { "rx_mac_ctrl_frames" },
7486 { "rx_filtered_packets" },
790dab2f 7487 { "rx_ftq_discards" },
b6016b76 7488 { "rx_discards" },
cea94db9 7489 { "rx_fw_discards" },
b6016b76
MC		 7490};
7491
0db83cd8 7492#define BNX2_NUM_STATS ARRAY_SIZE(bnx2_stats_str_arr)
790dab2f 7493
b6016b76
MC		 7494#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7495
f71e1309 7496static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7497 STATS_OFFSET32(stat_IfHCInOctets_hi),
7498 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7499 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7500 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7501 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7502 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7503 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7504 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7505 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7506 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7507 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 7508 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7509 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7510 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7511 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7512 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7513 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7514 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7515 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7516 STATS_OFFSET32(stat_EtherStatsCollisions),
7517 STATS_OFFSET32(stat_EtherStatsFragments),
7518 STATS_OFFSET32(stat_EtherStatsJabbers),
7519 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7520 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7521 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7522 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7523 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7524 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7525 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7526 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7527 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7528 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7529 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7530 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7531 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7532 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7533 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7534 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7535 STATS_OFFSET32(stat_XonPauseFramesReceived),
7536 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7537 STATS_OFFSET32(stat_OutXonSent),
7538 STATS_OFFSET32(stat_OutXoffSent),
7539 STATS_OFFSET32(stat_MacControlFramesReceived),
7540 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
790dab2f 7541 STATS_OFFSET32(stat_IfInFTQDiscards),
6aa20a22 7542 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 7543 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 7544};
7545
7546/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7547 * skipped because of errata.
6aa20a22 7548 */
14ab9b86 7549static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7550 8,0,8,8,8,8,8,8,8,8,
7551 4,0,4,4,4,4,4,4,4,4,
7552 4,4,4,4,4,4,4,4,4,4,
7553 4,4,4,4,4,4,4,4,4,4,
790dab2f 7554 4,4,4,4,4,4,4,
b6016b76
MC		 7555};
7556
5b0c76ad
MC		 7557static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7558 8,0,8,8,8,8,8,8,8,8,
7559 4,4,4,4,4,4,4,4,4,4,
7560 4,4,4,4,4,4,4,4,4,4,
7561 4,4,4,4,4,4,4,4,4,4,
790dab2f 7562 4,4,4,4,4,4,4,
5b0c76ad
MC		 7563};
7564
b6016b76
MC		 7565#define BNX2_NUM_TESTS 6
7566
14ab9b86 7567static struct {
b6016b76
MC		 7568 char string[ETH_GSTRING_LEN];
7569} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7570 { "register_test (offline)" },
7571 { "memory_test (offline)" },
7572 { "loopback_test (offline)" },
7573 { "nvram_test (online)" },
7574 { "interrupt_test (online)" },
7575 { "link_test (online)" },
7576};
7577
7578static int
b9f2c044 7579bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 7580{
b9f2c044
JG		 7581 switch (sset) {
7582 case ETH_SS_TEST:
7583 return BNX2_NUM_TESTS;
7584 case ETH_SS_STATS:
7585 return BNX2_NUM_STATS;
7586 default:
7587 return -EOPNOTSUPP;
7588 }
b6016b76
MC		 7589}
7590
7591static void
7592bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7593{
972ec0d4 7594 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7595
7596 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7597 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 7598 int i;
7599
212f9934 7600 bnx2_netif_stop(bp, true);
b6016b76
MC		 7601 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7602 bnx2_free_skbs(bp);
7603
7604 if (bnx2_test_registers(bp) != 0) {
7605 buf[0] = 1;
7606 etest->flags |= ETH_TEST_FL_FAILED;
7607 }
7608 if (bnx2_test_memory(bp) != 0) {
7609 buf[1] = 1;
7610 etest->flags |= ETH_TEST_FL_FAILED;
7611 }
bc5a0690 7612 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 7613 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76 7614
9f52b564
MC		 7615 if (!netif_running(bp->dev))
7616 bnx2_shutdown_chip(bp);
b6016b76 7617 else {
9a120bc5 7618 bnx2_init_nic(bp, 1);
212f9934 7619 bnx2_netif_start(bp, true);
b6016b76
MC		 7620 }
7621
7622 /* wait for link up */
80be4434
MC		 7623 for (i = 0; i < 7; i++) {
7624 if (bp->link_up)
7625 break;
7626 msleep_interruptible(1000);
7627 }
b6016b76
MC		 7628 }
7629
7630 if (bnx2_test_nvram(bp) != 0) {
7631 buf[3] = 1;
7632 etest->flags |= ETH_TEST_FL_FAILED;
7633 }
7634 if (bnx2_test_intr(bp) != 0) {
7635 buf[4] = 1;
7636 etest->flags |= ETH_TEST_FL_FAILED;
7637 }
7638
7639 if (bnx2_test_link(bp) != 0) {
7640 buf[5] = 1;
7641 etest->flags |= ETH_TEST_FL_FAILED;
7642
7643 }
7644}
7645
7646static void
7647bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7648{
7649 switch (stringset) {
7650 case ETH_SS_STATS:
7651 memcpy(buf, bnx2_stats_str_arr,
7652 sizeof(bnx2_stats_str_arr));
7653 break;
7654 case ETH_SS_TEST:
7655 memcpy(buf, bnx2_tests_str_arr,
7656 sizeof(bnx2_tests_str_arr));
7657 break;
7658 }
7659}
7660
b6016b76
MC		 7661static void
7662bnx2_get_ethtool_stats(struct net_device *dev,
7663 struct ethtool_stats *stats, u64 *buf)
7664{
972ec0d4 7665 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7666 int i;
7667 u32 *hw_stats = (u32 *) bp->stats_blk;
354fcd77 7668 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
14ab9b86 7669 u8 *stats_len_arr = NULL;
b6016b76 7670
b8aac410 7671 if (!hw_stats) {
b6016b76
MC		 7672 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7673 return;
7674 }
7675
4ce45e02
MC		 7676 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
7677 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) ||
7678 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) ||
7679 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))
b6016b76 7680 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 7681 else
7682 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 7683
7684 for (i = 0; i < BNX2_NUM_STATS; i++) {
354fcd77
MC		 7685 unsigned long offset;
7686
b6016b76
MC		 7687 if (stats_len_arr[i] == 0) {
7688 /* skip this counter */
7689 buf[i] = 0;
7690 continue;
7691 }
354fcd77
MC		 7692
7693 offset = bnx2_stats_offset_arr[i];
b6016b76
MC		 7694 if (stats_len_arr[i] == 4) {
7695 /* 4-byte counter */
354fcd77
MC		 7696 buf[i] = (u64) *(hw_stats + offset) +
7697 *(temp_stats + offset);
b6016b76
MC		 7698 continue;
7699 }
7700 /* 8-byte counter */
354fcd77
MC		 7701 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7702 *(hw_stats + offset + 1) +
7703 (((u64) *(temp_stats + offset)) << 32) +
7704 *(temp_stats + offset + 1);
b6016b76
MC		 7705 }
7706}
7707
7708static int
2e17e1aa 7709bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state)
b6016b76 7710{
972ec0d4 7711 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7712
2e17e1aa 7713 switch (state) {
7714 case ETHTOOL_ID_ACTIVE:
e503e066
MC		 7715 bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);
7716 BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
fce55922 7717 return 1; /* cycle on/off once per second */
b6016b76 7718
2e17e1aa 7719 case ETHTOOL_ID_ON:
e503e066
MC		 7720 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7721 BNX2_EMAC_LED_1000MB_OVERRIDE |
7722 BNX2_EMAC_LED_100MB_OVERRIDE |
7723 BNX2_EMAC_LED_10MB_OVERRIDE |
7724 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7725 BNX2_EMAC_LED_TRAFFIC);
2e17e1aa 7726 break;
b6016b76 7727
2e17e1aa 7728 case ETHTOOL_ID_OFF:
e503e066 7729 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
2e17e1aa 7730 break;
9f52b564 7731
2e17e1aa 7732 case ETHTOOL_ID_INACTIVE:
e503e066
MC		 7733 BNX2_WR(bp, BNX2_EMAC_LED, 0);
7734 BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);
2e17e1aa 7735 break;
7736 }
9f52b564 7737
b6016b76
MC		 7738 return 0;
7739}
7740
fdc8541d 7741static int
c8f44aff 7742bnx2_set_features(struct net_device *dev, netdev_features_t features)
fdc8541d 7743{
7d0fd211 7744 struct bnx2 *bp = netdev_priv(dev);
7d0fd211 7745
7c810477 7746 /* TSO with VLAN tag won't work with current firmware */
f646968f 7747 if (features & NETIF_F_HW_VLAN_CTAG_TX)
8d7dfc2b
MM		 7748 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO);
7749 else
7750 dev->vlan_features &= ~NETIF_F_ALL_TSO;
7d0fd211 7751
f646968f 7752 if ((!!(features & NETIF_F_HW_VLAN_CTAG_RX) !=
7d0fd211
JG		 7753 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
7754 netif_running(dev)) {
7755 bnx2_netif_stop(bp, false);
8d7dfc2b 7756 dev->features = features;
7d0fd211
JG		 7757 bnx2_set_rx_mode(dev);
7758 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
7759 bnx2_netif_start(bp, false);
8d7dfc2b 7760 return 1;
7d0fd211
JG		 7761 }
7762
7763 return 0;
fdc8541d
MC		 7764}
7765
b033281f
MC		 7766static void bnx2_get_channels(struct net_device *dev,
7767 struct ethtool_channels *channels)
7768{
7769 struct bnx2 *bp = netdev_priv(dev);
7770 u32 max_rx_rings = 1;
7771 u32 max_tx_rings = 1;
7772
7773 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
7774 max_rx_rings = RX_MAX_RINGS;
7775 max_tx_rings = TX_MAX_RINGS;
7776 }
7777
7778 channels->max_rx = max_rx_rings;
7779 channels->max_tx = max_tx_rings;
7780 channels->max_other = 0;
7781 channels->max_combined = 0;
7782 channels->rx_count = bp->num_rx_rings;
7783 channels->tx_count = bp->num_tx_rings;
7784 channels->other_count = 0;
7785 channels->combined_count = 0;
7786}
7787
7788static int bnx2_set_channels(struct net_device *dev,
7789 struct ethtool_channels *channels)
7790{
7791 struct bnx2 *bp = netdev_priv(dev);
7792 u32 max_rx_rings = 1;
7793 u32 max_tx_rings = 1;
7794 int rc = 0;
7795
7796 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
7797 max_rx_rings = RX_MAX_RINGS;
7798 max_tx_rings = TX_MAX_RINGS;
7799 }
7800 if (channels->rx_count > max_rx_rings ||
7801 channels->tx_count > max_tx_rings)
7802 return -EINVAL;
7803
7804 bp->num_req_rx_rings = channels->rx_count;
7805 bp->num_req_tx_rings = channels->tx_count;
7806
7807 if (netif_running(dev))
7808 rc = bnx2_change_ring_size(bp, bp->rx_ring_size,
7809 bp->tx_ring_size, true);
7810
7811 return rc;
7812}
7813
7282d491 7814static const struct ethtool_ops bnx2_ethtool_ops = {
05c53145
JK		 7815 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
7816 ETHTOOL_COALESCE_MAX_FRAMES |
7817 ETHTOOL_COALESCE_USECS_IRQ |
7818 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
7819 ETHTOOL_COALESCE_STATS_BLOCK_USECS,
b6016b76 7820 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 7821 .get_regs_len = bnx2_get_regs_len,
7822 .get_regs = bnx2_get_regs,
b6016b76
MC		 7823 .get_wol = bnx2_get_wol,
7824 .set_wol = bnx2_set_wol,
7825 .nway_reset = bnx2_nway_reset,
7959ea25 7826 .get_link = bnx2_get_link,
b6016b76
MC		 7827 .get_eeprom_len = bnx2_get_eeprom_len,
7828 .get_eeprom = bnx2_get_eeprom,
7829 .set_eeprom = bnx2_set_eeprom,
7830 .get_coalesce = bnx2_get_coalesce,
7831 .set_coalesce = bnx2_set_coalesce,
7832 .get_ringparam = bnx2_get_ringparam,
7833 .set_ringparam = bnx2_set_ringparam,
7834 .get_pauseparam = bnx2_get_pauseparam,
7835 .set_pauseparam = bnx2_set_pauseparam,
b6016b76
MC		 7836 .self_test = bnx2_self_test,
7837 .get_strings = bnx2_get_strings,
2e17e1aa 7838 .set_phys_id = bnx2_set_phys_id,
b6016b76 7839 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 7840 .get_sset_count = bnx2_get_sset_count,
b033281f
MC		 7841 .get_channels = bnx2_get_channels,
7842 .set_channels = bnx2_set_channels,
08e10d4d
PR		 7843 .get_link_ksettings = bnx2_get_link_ksettings,
7844 .set_link_ksettings = bnx2_set_link_ksettings,
b6016b76
MC		 7845};
7846
7847/* Called with rtnl_lock */
7848static int
7849bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7850{
14ab9b86 7851 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 7852 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7853 int err;
7854
7855 switch(cmd) {
7856 case SIOCGMIIPHY:
7857 data->phy_id = bp->phy_addr;
7858
df561f66 7859 fallthrough;
b6016b76
MC		 7860 case SIOCGMIIREG: {
7861 u32 mii_regval;
7862
583c28e5 7863 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7864 return -EOPNOTSUPP;
7865
dad3e452
MC		 7866 if (!netif_running(dev))
7867 return -EAGAIN;
7868
c770a65c 7869 spin_lock_bh(&bp->phy_lock);
b6016b76 7870 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 7871 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7872
7873 data->val_out = mii_regval;
7874
7875 return err;
7876 }
7877
7878 case SIOCSMIIREG:
583c28e5 7879 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7880 return -EOPNOTSUPP;
7881
dad3e452
MC		 7882 if (!netif_running(dev))
7883 return -EAGAIN;
7884
c770a65c 7885 spin_lock_bh(&bp->phy_lock);
b6016b76 7886 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 7887 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7888
7889 return err;
7890
7891 default:
7892 /* do nothing */
7893 break;
7894 }
7895 return -EOPNOTSUPP;
7896}
7897
7898/* Called with rtnl_lock */
7899static int
7900bnx2_change_mac_addr(struct net_device *dev, void *p)
7901{
7902 struct sockaddr *addr = p;
972ec0d4 7903 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7904
73eef4cd 7905 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 7906 return -EADDRNOTAVAIL;
73eef4cd 7907
b6016b76
MC		 7908 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7909 if (netif_running(dev))
5fcaed01 7910 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 7911
7912 return 0;
7913}
7914
7915/* Called with rtnl_lock */
7916static int
7917bnx2_change_mtu(struct net_device *dev, int new_mtu)
7918{
972ec0d4 7919 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7920
b6016b76 7921 dev->mtu = new_mtu;
b033281f
MC		 7922 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,
7923 false);
b6016b76
MC		 7924}
7925
257ddbda 7926#ifdef CONFIG_NET_POLL_CONTROLLER
b6016b76
MC		 7927static void
7928poll_bnx2(struct net_device *dev)
7929{
972ec0d4 7930 struct bnx2 *bp = netdev_priv(dev);
b2af2c1d 7931 int i;
b6016b76 7932
b2af2c1d 7933 for (i = 0; i < bp->irq_nvecs; i++) {
1bf1e347
MC		 7934 struct bnx2_irq *irq = &bp->irq_tbl[i];
7935
7936 disable_irq(irq->vector);
7937 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7938 enable_irq(irq->vector);
b2af2c1d 7939 }
b6016b76
MC		 7940}
7941#endif
7942
cfd95a63 7943static void
253c8b75
MC		 7944bnx2_get_5709_media(struct bnx2 *bp)
7945{
e503e066 7946 u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
253c8b75
MC		 7947 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7948 u32 strap;
7949
7950 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7951 return;
7952 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7953 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7954 return;
7955 }
7956
7957 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7958 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7959 else
7960 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7961
aefd90e4 7962 if (bp->func == 0) {
253c8b75
MC		 7963 switch (strap) {
7964 case 0x4:
7965 case 0x5:
7966 case 0x6:
583c28e5 7967 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7968 return;
7969 }
7970 } else {
7971 switch (strap) {
7972 case 0x1:
7973 case 0x2:
7974 case 0x4:
583c28e5 7975 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7976 return;
7977 }
7978 }
7979}
7980
cfd95a63 7981static void
883e5151
MC		 7982bnx2_get_pci_speed(struct bnx2 *bp)
7983{
7984 u32 reg;
7985
e503e066 7986 reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);
883e5151
MC		 7987 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7988 u32 clkreg;
7989
f86e82fb 7990 bp->flags |= BNX2_FLAG_PCIX;
883e5151 7991
e503e066 7992 clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
883e5151
MC		 7993
7994 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7995 switch (clkreg) {
7996 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7997 bp->bus_speed_mhz = 133;
7998 break;
7999
8000 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
8001 bp->bus_speed_mhz = 100;
8002 break;
8003
8004 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
8005 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
8006 bp->bus_speed_mhz = 66;
8007 break;
8008
8009 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
8010 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
8011 bp->bus_speed_mhz = 50;
8012 break;
8013
8014 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
8015 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
8016 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
8017 bp->bus_speed_mhz = 33;
8018 break;
8019 }
8020 }
8021 else {
8022 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
8023 bp->bus_speed_mhz = 66;
8024 else
8025 bp->bus_speed_mhz = 33;
8026 }
8027
8028 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 8029 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 8030
8031}
8032
cfd95a63 8033static void
76d99061
MC		 8034bnx2_read_vpd_fw_ver(struct bnx2 *bp)
8035{
df25bc38 8036 int rc, i, j;
76d99061 8037 u8 *data;
3408259b 8038 unsigned int block_end, rosize, len;
76d99061 8039
012093f6
MC		 8040#define BNX2_VPD_NVRAM_OFFSET 0x300
8041#define BNX2_VPD_LEN 128
76d99061
MC		 8042#define BNX2_MAX_VER_SLEN 30
8043
0df79c86 8044 data = kmalloc(BNX2_VPD_LEN, GFP_KERNEL);
76d99061
MC		 8045 if (!data)
8046 return;
8047
0df79c86 8048 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data, BNX2_VPD_LEN);
76d99061
MC		 8049 if (rc)
8050 goto vpd_done;
8051
0df79c86
HK		 8052 for (i = 0; i < BNX2_VPD_LEN; i += 4)
8053 swab32s((u32 *)&data[i]);
76d99061 8054
3408259b
DM		 8055 i = pci_vpd_find_tag(data, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
8056 if (i < 0)
8057 goto vpd_done;
8058
8059 rosize = pci_vpd_lrdt_size(&data[i]);
8060 i += PCI_VPD_LRDT_TAG_SIZE;
8061 block_end = i + rosize;
8062
8063 if (block_end > BNX2_VPD_LEN)
8064 goto vpd_done;
8065
8066 j = pci_vpd_find_info_keyword(data, i, rosize,
8067 PCI_VPD_RO_KEYWORD_MFR_ID);
df25bc38
MC		 8068 if (j < 0)
8069 goto vpd_done;
76d99061 8070
3408259b
DM		 8071 len = pci_vpd_info_field_size(&data[j]);
8072
8073 j += PCI_VPD_INFO_FLD_HDR_SIZE;
8074 if (j + len > block_end || len != 4 ||
8075 memcmp(&data[j], "1028", 4))
df25bc38 8076 goto vpd_done;
4067a854 8077
3408259b
DM		 8078 j = pci_vpd_find_info_keyword(data, i, rosize,
8079 PCI_VPD_RO_KEYWORD_VENDOR0);
df25bc38
MC		 8080 if (j < 0)
8081 goto vpd_done;
4067a854 8082
3408259b
DM		 8083 len = pci_vpd_info_field_size(&data[j]);
8084
8085 j += PCI_VPD_INFO_FLD_HDR_SIZE;
8086 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
76d99061 8087 goto vpd_done;
df25bc38
MC		 8088
8089 memcpy(bp->fw_version, &data[j], len);
8090 bp->fw_version[len] = ' ';
76d99061
MC		 8091
8092vpd_done:
8093 kfree(data);
8094}
8095
cfd95a63 8096static int
b6016b76
MC		 8097bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
8098{
8099 struct bnx2 *bp;
58fc2ea4 8100 int rc, i, j;
b6016b76 8101 u32 reg;
40453c83 8102 u64 dma_mask, persist_dma_mask;
cd709aa9 8103 int err;
b6016b76 8104
b6016b76 8105 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 8106 bp = netdev_priv(dev);
b6016b76
MC		 8107
8108 bp->flags = 0;
8109 bp->phy_flags = 0;
8110
354fcd77
MC		 8111 bp->temp_stats_blk =
8112 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
8113
b8aac410 8114 if (!bp->temp_stats_blk) {
354fcd77
MC		 8115 rc = -ENOMEM;
8116 goto err_out;
8117 }
8118
b6016b76
MC		 8119 /* enable device (incl. PCI PM wakeup), and bus-mastering */
8120 rc = pci_enable_device(pdev);
8121 if (rc) {
3a9c6a49 8122 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
b6016b76
MC		 8123 goto err_out;
8124 }
8125
8126 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 8127 dev_err(&pdev->dev,
3a9c6a49 8128 "Cannot find PCI device base address, aborting\n");
b6016b76
MC		 8129 rc = -ENODEV;
8130 goto err_out_disable;
8131 }
8132
8133 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
8134 if (rc) {
3a9c6a49 8135 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
b6016b76
MC		 8136 goto err_out_disable;
8137 }
8138
8139 pci_set_master(pdev);
8140
85768271 8141 bp->pm_cap = pdev->pm_cap;
b6016b76 8142 if (bp->pm_cap == 0) {
9b91cf9d 8143 dev_err(&pdev->dev,
3a9c6a49 8144 "Cannot find power management capability, aborting\n");
b6016b76
MC		 8145 rc = -EIO;
8146 goto err_out_release;
8147 }
8148
b6016b76
MC		 8149 bp->dev = dev;
8150 bp->pdev = pdev;
8151
8152 spin_lock_init(&bp->phy_lock);
1b8227c4 8153 spin_lock_init(&bp->indirect_lock);
c5a88950
MC		 8154#ifdef BCM_CNIC
8155 mutex_init(&bp->cnic_lock);
8156#endif
c4028958 8157 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76 8158
c0357e97
FR		 8159 bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +
8160 TX_MAX_TSS_RINGS + 1));
b6016b76 8161 if (!bp->regview) {
3a9c6a49 8162 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
b6016b76
MC		 8163 rc = -ENOMEM;
8164 goto err_out_release;
8165 }
8166
8167 /* Configure byte swap and enable write to the reg_window registers.
8168 * Rely on CPU to do target byte swapping on big endian systems
8169 * The chip's target access swapping will not swap all accesses
8170 */
e503e066
MC		 8171 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,
8172 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
8173 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
b6016b76 8174
e503e066 8175 bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);
b6016b76 8176
4ce45e02 8177 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
e82760e7
JM		 8178 if (!pci_is_pcie(pdev)) {
8179 dev_err(&pdev->dev, "Not PCIE, aborting\n");
883e5151
MC		 8180 rc = -EIO;
8181 goto err_out_unmap;
8182 }
f86e82fb 8183 bp->flags |= BNX2_FLAG_PCIE;
4ce45e02 8184 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)
f86e82fb 8185 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
c239f279
MC		 8186
8187 /* AER (Advanced Error Reporting) hooks */
8188 err = pci_enable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8189 if (!err)
8190 bp->flags |= BNX2_FLAG_AER_ENABLED;
c239f279 8191
883e5151 8192 } else {
59b47d8a
MC		 8193 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
8194 if (bp->pcix_cap == 0) {
8195 dev_err(&pdev->dev,
3a9c6a49 8196 "Cannot find PCIX capability, aborting\n");
59b47d8a
MC		 8197 rc = -EIO;
8198 goto err_out_unmap;
8199 }
61d9e3fa 8200 bp->flags |= BNX2_FLAG_BROKEN_STATS;
59b47d8a
MC		 8201 }
8202
4ce45e02
MC		 8203 if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&
8204 BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) {
555a8428 8205 if (pdev->msix_cap)
f86e82fb 8206 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 8207 }
8208
4ce45e02
MC		 8209 if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 &&
8210 BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) {
555a8428 8211 if (pdev->msi_cap)
f86e82fb 8212 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 8213 }
8214
40453c83 8215 /* 5708 cannot support DMA addresses > 40-bit. */
4ce45e02 8216 if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
50cf156a 8217 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
40453c83 8218 else
6a35528a 8219 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
40453c83
MC		 8220
8221 /* Configure DMA attributes. */
8222 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
8223 dev->features |= NETIF_F_HIGHDMA;
8224 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
8225 if (rc) {
8226 dev_err(&pdev->dev,
3a9c6a49 8227 "pci_set_consistent_dma_mask failed, aborting\n");
40453c83
MC		 8228 goto err_out_unmap;
8229 }
284901a9 8230 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3a9c6a49 8231 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
40453c83
MC		 8232 goto err_out_unmap;
8233 }
8234
f86e82fb 8235 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 8236 bnx2_get_pci_speed(bp);
b6016b76
MC		 8237
8238 /* 5706A0 may falsely detect SERR and PERR. */
4ce45e02 8239 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
e503e066 8240 reg = BNX2_RD(bp, PCI_COMMAND);
b6016b76 8241 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
e503e066 8242 BNX2_WR(bp, PCI_COMMAND, reg);
4ce45e02 8243 } else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) &&
f86e82fb 8244 !(bp->flags & BNX2_FLAG_PCIX)) {
9b91cf9d 8245 dev_err(&pdev->dev,
3a9c6a49 8246 "5706 A1 can only be used in a PCIX bus, aborting\n");
28c66b6d 8247 rc = -EPERM;
b6016b76
MC		 8248 goto err_out_unmap;
8249 }
8250
8251 bnx2_init_nvram(bp);
8252
2726d6e1 8253 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d 8254
aefd90e4
MC		 8255 if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID)
8256 bp->func = 1;
8257
e3648b3d 8258 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b 8259 BNX2_SHM_HDR_SIGNATURE_SIG) {
aefd90e4 8260 u32 off = bp->func << 2;
24cb230b 8261
2726d6e1 8262 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 8263 } else
e3648b3d
MC		 8264 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8265
b6016b76
MC		 8266 /* Get the permanent MAC address. First we need to make sure the
8267 * firmware is actually running.
8268 */
2726d6e1 8269 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 8270
8271 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8272 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
3a9c6a49 8273 dev_err(&pdev->dev, "Firmware not running, aborting\n");
b6016b76
MC		 8274 rc = -ENODEV;
8275 goto err_out_unmap;
8276 }
8277
76d99061
MC		 8278 bnx2_read_vpd_fw_ver(bp);
8279
8280 j = strlen(bp->fw_version);
2726d6e1 8281 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
76d99061 8282 for (i = 0; i < 3 && j < 24; i++) {
58fc2ea4
MC		 8283 u8 num, k, skip0;
8284
76d99061
MC		 8285 if (i == 0) {
8286 bp->fw_version[j++] = 'b';
8287 bp->fw_version[j++] = 'c';
8288 bp->fw_version[j++] = ' ';
8289 }
58fc2ea4
MC		 8290 num = (u8) (reg >> (24 - (i * 8)));
8291 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8292 if (num >= k || !skip0 || k == 1) {
8293 bp->fw_version[j++] = (num / k) + '0';
8294 skip0 = 0;
8295 }
8296 }
8297 if (i != 2)
8298 bp->fw_version[j++] = '.';
8299 }
2726d6e1 8300 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 8301 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8302 bp->wol = 1;
8303
8304 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 8305 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 8306
8307 for (i = 0; i < 30; i++) {
2726d6e1 8308 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 8309 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8310 break;
8311 msleep(10);
8312 }
8313 }
2726d6e1 8314 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 8315 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8316 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8317 reg != BNX2_CONDITION_MFW_RUN_NONE) {
2726d6e1 8318 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4 8319
76d99061
MC		 8320 if (j < 32)
8321 bp->fw_version[j++] = ' ';
8322 for (i = 0; i < 3 && j < 28; i++) {
2726d6e1 8323 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
3aeb7d22 8324 reg = be32_to_cpu(reg);
58fc2ea4
MC		 8325 memcpy(&bp->fw_version[j], &reg, 4);
8326 j += 4;
8327 }
8328 }
b6016b76 8329
2726d6e1 8330 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 8331 bp->mac_addr[0] = (u8) (reg >> 8);
8332 bp->mac_addr[1] = (u8) reg;
8333
2726d6e1 8334 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 8335 bp->mac_addr[2] = (u8) (reg >> 24);
8336 bp->mac_addr[3] = (u8) (reg >> 16);
8337 bp->mac_addr[4] = (u8) (reg >> 8);
8338 bp->mac_addr[5] = (u8) reg;
8339
2bc4078e 8340 bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT;
932f3772 8341 bnx2_set_rx_ring_size(bp, 255);
b6016b76 8342
cf7474a6 8343 bp->tx_quick_cons_trip_int = 2;
b6016b76 8344 bp->tx_quick_cons_trip = 20;
cf7474a6 8345 bp->tx_ticks_int = 18;
b6016b76 8346 bp->tx_ticks = 80;
6aa20a22 8347
cf7474a6
MC		 8348 bp->rx_quick_cons_trip_int = 2;
8349 bp->rx_quick_cons_trip = 12;
b6016b76
MC		 8350 bp->rx_ticks_int = 18;
8351 bp->rx_ticks = 18;
8352
7ea6920e 8353 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76 8354
ac392abc 8355 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 8356
5b0c76ad
MC		 8357 bp->phy_addr = 1;
8358
8fae307c 8359 /* allocate stats_blk */
8360 rc = bnx2_alloc_stats_blk(dev);
8361 if (rc)
8362 goto err_out_unmap;
8363
b6016b76 8364 /* Disable WOL support if we are running on a SERDES chip. */
4ce45e02 8365 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
253c8b75 8366 bnx2_get_5709_media(bp);
4ce45e02 8367 else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT)
583c28e5 8368 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 8369
0d8a6571 8370 bp->phy_port = PORT_TP;
583c28e5 8371 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 8372 bp->phy_port = PORT_FIBRE;
2726d6e1 8373 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 8374 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 8375 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8376 bp->wol = 0;
8377 }
4ce45e02 8378 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) {
38ea3686
MC		 8379 /* Don't do parallel detect on this board because of
8380 * some board problems. The link will not go down
8381 * if we do parallel detect.
8382 */
8383 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8384 pdev->subsystem_device == 0x310c)
8385 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8386 } else {
5b0c76ad 8387 bp->phy_addr = 2;
5b0c76ad 8388 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 8389 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 8390 }
4ce45e02
MC		 8391 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 ||
8392 BNX2_CHIP(bp) == BNX2_CHIP_5708)
583c28e5 8393 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
4ce45e02
MC		 8394 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&
8395 (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax ||
8396 BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx))
583c28e5 8397 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 8398
7c62e83b
MC		 8399 bnx2_init_fw_cap(bp);
8400
4ce45e02
MC		 8401 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||
8402 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||
8403 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) ||
e503e066 8404 !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
f86e82fb 8405 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8406 bp->wol = 0;
8407 }
dda1e390 8408
6d5e85c7
MC		 8409 if (bp->flags & BNX2_FLAG_NO_WOL)
8410 device_set_wakeup_capable(&bp->pdev->dev, false);
8411 else
8412 device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
8413
4ce45e02 8414 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
b6016b76
MC		 8415 bp->tx_quick_cons_trip_int =
8416 bp->tx_quick_cons_trip;
8417 bp->tx_ticks_int = bp->tx_ticks;
8418 bp->rx_quick_cons_trip_int =
8419 bp->rx_quick_cons_trip;
8420 bp->rx_ticks_int = bp->rx_ticks;
8421 bp->comp_prod_trip_int = bp->comp_prod_trip;
8422 bp->com_ticks_int = bp->com_ticks;
8423 bp->cmd_ticks_int = bp->cmd_ticks;
8424 }
8425
f9317a40
MC		 8426 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8427 *
8428 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8429 * with byte enables disabled on the unused 32-bit word. This is legal
8430 * but causes problems on the AMD 8132 which will eventually stop
8431 * responding after a while.
8432 *
8433 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 8434 * prefers to locally disable MSI rather than globally disabling it.
f9317a40 8435 */
4ce45e02 8436 if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) {
f9317a40
MC		 8437 struct pci_dev *amd_8132 = NULL;
8438
8439 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8440 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8441 amd_8132))) {
f9317a40 8442
44c10138
AK		 8443 if (amd_8132->revision >= 0x10 &&
8444 amd_8132->revision <= 0x13) {
f9317a40
MC		 8445 disable_msi = 1;
8446 pci_dev_put(amd_8132);
8447 break;
8448 }
8449 }
8450 }
8451
deaf391b 8452 bnx2_set_default_link(bp);
b6016b76
MC		 8453 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8454
e99e88a9 8455 timer_setup(&bp->timer, bnx2_timer, 0);
ac392abc 8456 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
cd339a0e 8457
7625eb2f 8458#ifdef BCM_CNIC
41c2178a
MC		 8459 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
8460 bp->cnic_eth_dev.max_iscsi_conn =
8461 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
8462 BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT;
4bd9b0ff 8463 bp->cnic_probe = bnx2_cnic_probe;
7625eb2f 8464#endif
c239f279
MC		 8465 pci_save_state(pdev);
8466
b6016b76
MC		 8467 return 0;
8468
8469err_out_unmap:
4bb9ebc7 8470 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
c239f279 8471 pci_disable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8472 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8473 }
c239f279 8474
c0357e97
FR		 8475 pci_iounmap(pdev, bp->regview);
8476 bp->regview = NULL;
b6016b76
MC		 8477
8478err_out_release:
8479 pci_release_regions(pdev);
8480
8481err_out_disable:
8482 pci_disable_device(pdev);
b6016b76
MC		 8483
8484err_out:
3703ebe4 8485 kfree(bp->temp_stats_blk);
8486
b6016b76
MC		 8487 return rc;
8488}
8489
cfd95a63 8490static char *
883e5151
MC		 8491bnx2_bus_string(struct bnx2 *bp, char *str)
8492{
8493 char *s = str;
8494
f86e82fb 8495 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 8496 s += sprintf(s, "PCI Express");
8497 } else {
8498 s += sprintf(s, "PCI");
f86e82fb 8499 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 8500 s += sprintf(s, "-X");
f86e82fb 8501 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 8502 s += sprintf(s, " 32-bit");
8503 else
8504 s += sprintf(s, " 64-bit");
8505 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8506 }
8507 return str;
8508}
8509
f048fa9c
MC		 8510static void
8511bnx2_del_napi(struct bnx2 *bp)
8512{
8513 int i;
8514
8515 for (i = 0; i < bp->irq_nvecs; i++)
8516 netif_napi_del(&bp->bnx2_napi[i].napi);
8517}
8518
8519static void
35efa7c1
MC		 8520bnx2_init_napi(struct bnx2 *bp)
8521{
b4b36042 8522 int i;
35efa7c1 8523
4327ba43 8524 for (i = 0; i < bp->irq_nvecs; i++) {
35e9010b
MC		 8525 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8526 int (*poll)(struct napi_struct *, int);
8527
8528 if (i == 0)
8529 poll = bnx2_poll;
8530 else
f0ea2e63 8531 poll = bnx2_poll_msix;
35e9010b
MC		 8532
8533 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
b4b36042
MC		 8534 bnapi->bp = bp;
8535 }
35efa7c1
MC		 8536}
8537
0421eae6
SH		 8538static const struct net_device_ops bnx2_netdev_ops = {
8539 .ndo_open = bnx2_open,
8540 .ndo_start_xmit = bnx2_start_xmit,
8541 .ndo_stop = bnx2_close,
5d07bf26 8542 .ndo_get_stats64 = bnx2_get_stats64,
0421eae6 8543 .ndo_set_rx_mode = bnx2_set_rx_mode,
a7605370 8544 .ndo_eth_ioctl = bnx2_ioctl,
0421eae6
SH		 8545 .ndo_validate_addr = eth_validate_addr,
8546 .ndo_set_mac_address = bnx2_change_mac_addr,
8547 .ndo_change_mtu = bnx2_change_mtu,
8d7dfc2b 8548 .ndo_set_features = bnx2_set_features,
0421eae6 8549 .ndo_tx_timeout = bnx2_tx_timeout,
257ddbda 8550#ifdef CONFIG_NET_POLL_CONTROLLER
0421eae6
SH		 8551 .ndo_poll_controller = poll_bnx2,
8552#endif
8553};
8554
cfd95a63 8555static int
b6016b76
MC		 8556bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8557{
c0357e97 8558 struct net_device *dev;
b6016b76 8559 struct bnx2 *bp;
0795af57 8560 int rc;
883e5151 8561 char str[40];
b6016b76 8562
b6016b76 8563 /* dev zeroed in init_etherdev */
706bf240 8564 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
b6016b76
MC		 8565 if (!dev)
8566 return -ENOMEM;
8567
8568 rc = bnx2_init_board(pdev, dev);
c0357e97
FR		 8569 if (rc < 0)
8570 goto err_free;
b6016b76 8571
0421eae6 8572 dev->netdev_ops = &bnx2_netdev_ops;
b6016b76 8573 dev->watchdog_timeo = TX_TIMEOUT;
b6016b76 8574 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 8575
972ec0d4 8576 bp = netdev_priv(dev);
b6016b76 8577
1b2f922f
MC		 8578 pci_set_drvdata(pdev, dev);
8579
6df77862
BH		 8580 /*
8581 * In-flight DMA from 1st kernel could continue going in kdump kernel.
8582 * New io-page table has been created before bnx2 does reset at open stage.
8583 * We have to wait for the in-flight DMA to complete to avoid it look up
8584 * into the newly created io-page table.
8585 */
8586 if (is_kdump_kernel())
8587 bnx2_wait_dma_complete(bp);
3e1be7ad 8588
d458cdf7 8589 memcpy(dev->dev_addr, bp->mac_addr, ETH_ALEN);
1b2f922f 8590
8d7dfc2b
MM		 8591 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
8592 NETIF_F_TSO | NETIF_F_TSO_ECN |
8593 NETIF_F_RXHASH | NETIF_F_RXCSUM;
8594
4ce45e02 8595 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
8d7dfc2b
MM		 8596 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8597
8598 dev->vlan_features = dev->hw_features;
f646968f 8599 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8d7dfc2b 8600 dev->features |= dev->hw_features;
01789349 8601 dev->priv_flags |= IFF_UNICAST_FLT;
e1c6dcca
JW		 8602 dev->min_mtu = MIN_ETHERNET_PACKET_SIZE;
8603 dev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE;
8d7dfc2b 8604
26caa346
IV		 8605 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
8606 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8607
b6016b76 8608 if ((rc = register_netdev(dev))) {
9b91cf9d 8609 dev_err(&pdev->dev, "Cannot register net device\n");
57579f76 8610 goto error;
b6016b76
MC		 8611 }
8612
c0357e97
FR		 8613 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, "
8614 "node addr %pM\n", board_info[ent->driver_data].name,
4ce45e02
MC		 8615 ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8616 ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4),
c0357e97
FR		 8617 bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0),
8618 pdev->irq, dev->dev_addr);
b6016b76 8619
b6016b76 8620 return 0;
57579f76
MC		 8621
8622error:
fda4d85d 8623 pci_iounmap(pdev, bp->regview);
57579f76
MC		 8624 pci_release_regions(pdev);
8625 pci_disable_device(pdev);
c0357e97 8626err_free:
8fae307c 8627 bnx2_free_stats_blk(dev);
57579f76
MC		 8628 free_netdev(dev);
8629 return rc;
b6016b76
MC		 8630}
8631
cfd95a63 8632static void
b6016b76
MC		 8633bnx2_remove_one(struct pci_dev *pdev)
8634{
8635 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8636 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 8637
8638 unregister_netdev(dev);
8639
8333a46a 8640 del_timer_sync(&bp->timer);
cd634019 8641 cancel_work_sync(&bp->reset_task);
8333a46a 8642
c0357e97 8643 pci_iounmap(bp->pdev, bp->regview);
b6016b76 8644
8fae307c 8645 bnx2_free_stats_blk(dev);
354fcd77
MC		 8646 kfree(bp->temp_stats_blk);
8647
4bb9ebc7 8648 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
c239f279 8649 pci_disable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8650 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8651 }
cd709aa9 8652
7880b72e 8653 bnx2_release_firmware(bp);
8654
c239f279 8655 free_netdev(dev);
cd709aa9 8656
b6016b76
MC		 8657 pci_release_regions(pdev);
8658 pci_disable_device(pdev);
b6016b76
MC		 8659}
8660
77d149c4 8661#ifdef CONFIG_PM_SLEEP
b6016b76 8662static int
28fb4eb4 8663bnx2_suspend(struct device *device)
b6016b76 8664{
f521eaa9 8665 struct net_device *dev = dev_get_drvdata(device);
972ec0d4 8666 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8667
28fb4eb4
MC		 8668 if (netif_running(dev)) {
8669 cancel_work_sync(&bp->reset_task);
8670 bnx2_netif_stop(bp, true);
8671 netif_device_detach(dev);
8672 del_timer_sync(&bp->timer);
8673 bnx2_shutdown_chip(bp);
8674 __bnx2_free_irq(bp);
8675 bnx2_free_skbs(bp);
8676 }
8677 bnx2_setup_wol(bp);
b6016b76
MC		 8678 return 0;
8679}
8680
8681static int
28fb4eb4 8682bnx2_resume(struct device *device)
b6016b76 8683{
f521eaa9 8684 struct net_device *dev = dev_get_drvdata(device);
972ec0d4 8685 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 8686
8687 if (!netif_running(dev))
8688 return 0;
8689
829ca9a3 8690 bnx2_set_power_state(bp, PCI_D0);
b6016b76 8691 netif_device_attach(dev);
28fb4eb4 8692 bnx2_request_irq(bp);
9a120bc5 8693 bnx2_init_nic(bp, 1);
212f9934 8694 bnx2_netif_start(bp, true);
b6016b76
MC		 8695 return 0;
8696}
8697
28fb4eb4
MC		 8698static SIMPLE_DEV_PM_OPS(bnx2_pm_ops, bnx2_suspend, bnx2_resume);
8699#define BNX2_PM_OPS (&bnx2_pm_ops)
8700
8701#else
8702
8703#define BNX2_PM_OPS NULL
8704
8705#endif /* CONFIG_PM_SLEEP */
6ff2da49
WX		 8706/**
8707 * bnx2_io_error_detected - called when PCI error is detected
8708 * @pdev: Pointer to PCI device
8709 * @state: The current pci connection state
8710 *
8711 * This function is called after a PCI bus error affecting
8712 * this device has been detected.
8713 */
8714static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8715 pci_channel_state_t state)
8716{
8717 struct net_device *dev = pci_get_drvdata(pdev);
8718 struct bnx2 *bp = netdev_priv(dev);
8719
8720 rtnl_lock();
8721 netif_device_detach(dev);
8722
2ec3de26
DN		 8723 if (state == pci_channel_io_perm_failure) {
8724 rtnl_unlock();
8725 return PCI_ERS_RESULT_DISCONNECT;
8726 }
8727
6ff2da49 8728 if (netif_running(dev)) {
212f9934 8729 bnx2_netif_stop(bp, true);
6ff2da49
WX		 8730 del_timer_sync(&bp->timer);
8731 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8732 }
8733
8734 pci_disable_device(pdev);
8735 rtnl_unlock();
8736
8737 /* Request a slot slot reset. */
8738 return PCI_ERS_RESULT_NEED_RESET;
8739}
8740
8741/**
8742 * bnx2_io_slot_reset - called after the pci bus has been reset.
8743 * @pdev: Pointer to PCI device
8744 *
8745 * Restart the card from scratch, as if from a cold-boot.
8746 */
8747static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8748{
8749 struct net_device *dev = pci_get_drvdata(pdev);
8750 struct bnx2 *bp = netdev_priv(dev);
02481bc6
MC		 8751 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
8752 int err = 0;
6ff2da49
WX		 8753
8754 rtnl_lock();
8755 if (pci_enable_device(pdev)) {
8756 dev_err(&pdev->dev,
3a9c6a49 8757 "Cannot re-enable PCI device after reset\n");
cd709aa9
JF		 8758 } else {
8759 pci_set_master(pdev);
8760 pci_restore_state(pdev);
8761 pci_save_state(pdev);
8762
25bfb1dd 8763 if (netif_running(dev))
02481bc6 8764 err = bnx2_init_nic(bp, 1);
25bfb1dd 8765
02481bc6
MC		 8766 if (!err)
8767 result = PCI_ERS_RESULT_RECOVERED;
8768 }
8769
8770 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(dev)) {
8771 bnx2_napi_enable(bp);
8772 dev_close(dev);
6ff2da49 8773 }
cd709aa9 8774 rtnl_unlock();
6ff2da49 8775
4bb9ebc7 8776 if (!(bp->flags & BNX2_FLAG_AER_ENABLED))
c239f279
MC		 8777 return result;
8778
cd709aa9 8779 return result;
6ff2da49
WX		 8780}
8781
8782/**
8783 * bnx2_io_resume - called when traffic can start flowing again.
8784 * @pdev: Pointer to PCI device
8785 *
8786 * This callback is called when the error recovery driver tells us that
8787 * its OK to resume normal operation.
8788 */
8789static void bnx2_io_resume(struct pci_dev *pdev)
8790{
8791 struct net_device *dev = pci_get_drvdata(pdev);
8792 struct bnx2 *bp = netdev_priv(dev);
8793
8794 rtnl_lock();
8795 if (netif_running(dev))
212f9934 8796 bnx2_netif_start(bp, true);
6ff2da49
WX		 8797
8798 netif_device_attach(dev);
8799 rtnl_unlock();
8800}
8801
25bfb1dd
MC		 8802static void bnx2_shutdown(struct pci_dev *pdev)
8803{
8804 struct net_device *dev = pci_get_drvdata(pdev);
8805 struct bnx2 *bp;
8806
8807 if (!dev)
8808 return;
8809
8810 bp = netdev_priv(dev);
8811 if (!bp)
8812 return;
8813
8814 rtnl_lock();
8815 if (netif_running(dev))
8816 dev_close(bp->dev);
8817
8818 if (system_state == SYSTEM_POWER_OFF)
8819 bnx2_set_power_state(bp, PCI_D3hot);
8820
8821 rtnl_unlock();
8822}
8823
fda4d85d 8824static const struct pci_error_handlers bnx2_err_handler = {
6ff2da49
WX		 8825 .error_detected = bnx2_io_error_detected,
8826 .slot_reset = bnx2_io_slot_reset,
8827 .resume = bnx2_io_resume,
8828};
8829
b6016b76 8830static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 8831 .name = DRV_MODULE_NAME,
8832 .id_table = bnx2_pci_tbl,
8833 .probe = bnx2_init_one,
cfd95a63 8834 .remove = bnx2_remove_one,
28fb4eb4 8835 .driver.pm = BNX2_PM_OPS,
6ff2da49 8836 .err_handler = &bnx2_err_handler,
25bfb1dd 8837 .shutdown = bnx2_shutdown,
b6016b76
MC		 8838};
8839
5a4123f3 8840module_pci_driver(bnx2_pci_driver);
Ubuntu Jammy Linux kernel mirror