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Commit | Line | Data |
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b6016b76 MC |
1 | /* bnx2.c: Broadcom NX2 network driver. |
2 | * | |
dc187cb3 | 3 | * Copyright (c) 2004-2011 Broadcom Corporation |
b6016b76 MC |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Written by: Michael Chan (mchan@broadcom.com) | |
10 | */ | |
11 | ||
3a9c6a49 | 12 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
f2a4f052 MC |
13 | |
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | ||
555069da | 17 | #include <linux/stringify.h> |
f2a4f052 MC |
18 | #include <linux/kernel.h> |
19 | #include <linux/timer.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/vmalloc.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/netdevice.h> | |
28 | #include <linux/etherdevice.h> | |
29 | #include <linux/skbuff.h> | |
30 | #include <linux/dma-mapping.h> | |
1977f032 | 31 | #include <linux/bitops.h> |
f2a4f052 MC |
32 | #include <asm/io.h> |
33 | #include <asm/irq.h> | |
34 | #include <linux/delay.h> | |
35 | #include <asm/byteorder.h> | |
c86a31f4 | 36 | #include <asm/page.h> |
f2a4f052 MC |
37 | #include <linux/time.h> |
38 | #include <linux/ethtool.h> | |
39 | #include <linux/mii.h> | |
01789349 | 40 | #include <linux/if.h> |
f2a4f052 | 41 | #include <linux/if_vlan.h> |
f2a4f052 | 42 | #include <net/ip.h> |
de081fa5 | 43 | #include <net/tcp.h> |
f2a4f052 | 44 | #include <net/checksum.h> |
f2a4f052 MC |
45 | #include <linux/workqueue.h> |
46 | #include <linux/crc32.h> | |
47 | #include <linux/prefetch.h> | |
29b12174 | 48 | #include <linux/cache.h> |
57579f76 | 49 | #include <linux/firmware.h> |
706bf240 | 50 | #include <linux/log2.h> |
cd709aa9 | 51 | #include <linux/aer.h> |
f2a4f052 | 52 | |
4edd473f MC |
53 | #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) |
54 | #define BCM_CNIC 1 | |
55 | #include "cnic_if.h" | |
56 | #endif | |
b6016b76 MC |
57 | #include "bnx2.h" |
58 | #include "bnx2_fw.h" | |
b3448b0b | 59 | |
b6016b76 | 60 | #define DRV_MODULE_NAME "bnx2" |
d2e553bc MC |
61 | #define DRV_MODULE_VERSION "2.2.3" |
62 | #define DRV_MODULE_RELDATE "June 27, 2012" | |
c2c20ef4 | 63 | #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw" |
22fa159d | 64 | #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw" |
c2c20ef4 | 65 | #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw" |
22fa159d MC |
66 | #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw" |
67 | #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw" | |
b6016b76 MC |
68 | |
69 | #define RUN_AT(x) (jiffies + (x)) | |
70 | ||
71 | /* Time in jiffies before concluding the transmitter is hung. */ | |
72 | #define TX_TIMEOUT (5*HZ) | |
73 | ||
cfd95a63 | 74 | static char version[] = |
b6016b76 MC |
75 | "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
76 | ||
77 | MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); | |
453a9c6e | 78 | MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver"); |
b6016b76 MC |
79 | MODULE_LICENSE("GPL"); |
80 | MODULE_VERSION(DRV_MODULE_VERSION); | |
57579f76 MC |
81 | MODULE_FIRMWARE(FW_MIPS_FILE_06); |
82 | MODULE_FIRMWARE(FW_RV2P_FILE_06); | |
83 | MODULE_FIRMWARE(FW_MIPS_FILE_09); | |
84 | MODULE_FIRMWARE(FW_RV2P_FILE_09); | |
078b0735 | 85 | MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax); |
b6016b76 MC |
86 | |
87 | static int disable_msi = 0; | |
88 | ||
89 | module_param(disable_msi, int, 0); | |
90 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
91 | ||
92 | typedef enum { | |
93 | BCM5706 = 0, | |
94 | NC370T, | |
95 | NC370I, | |
96 | BCM5706S, | |
97 | NC370F, | |
5b0c76ad MC |
98 | BCM5708, |
99 | BCM5708S, | |
bac0dff6 | 100 | BCM5709, |
27a005b8 | 101 | BCM5709S, |
7bb0a04f | 102 | BCM5716, |
1caacecb | 103 | BCM5716S, |
b6016b76 MC |
104 | } board_t; |
105 | ||
106 | /* indexed by board_t, above */ | |
fefa8645 | 107 | static struct { |
b6016b76 | 108 | char *name; |
cfd95a63 | 109 | } board_info[] = { |
b6016b76 MC |
110 | { "Broadcom NetXtreme II BCM5706 1000Base-T" }, |
111 | { "HP NC370T Multifunction Gigabit Server Adapter" }, | |
112 | { "HP NC370i Multifunction Gigabit Server Adapter" }, | |
113 | { "Broadcom NetXtreme II BCM5706 1000Base-SX" }, | |
114 | { "HP NC370F Multifunction Gigabit Server Adapter" }, | |
5b0c76ad MC |
115 | { "Broadcom NetXtreme II BCM5708 1000Base-T" }, |
116 | { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, | |
bac0dff6 | 117 | { "Broadcom NetXtreme II BCM5709 1000Base-T" }, |
27a005b8 | 118 | { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, |
7bb0a04f | 119 | { "Broadcom NetXtreme II BCM5716 1000Base-T" }, |
1caacecb | 120 | { "Broadcom NetXtreme II BCM5716 1000Base-SX" }, |
b6016b76 MC |
121 | }; |
122 | ||
7bb0a04f | 123 | static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = { |
b6016b76 MC |
124 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, |
125 | PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T }, | |
126 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | |
127 | PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I }, | |
128 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | |
129 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 }, | |
5b0c76ad MC |
130 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708, |
131 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 }, | |
b6016b76 MC |
132 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, |
133 | PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F }, | |
134 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, | |
135 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S }, | |
5b0c76ad MC |
136 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S, |
137 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S }, | |
bac0dff6 MC |
138 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709, |
139 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 }, | |
27a005b8 MC |
140 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S, |
141 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S }, | |
7bb0a04f MC |
142 | { PCI_VENDOR_ID_BROADCOM, 0x163b, |
143 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 }, | |
1caacecb | 144 | { PCI_VENDOR_ID_BROADCOM, 0x163c, |
1f2435e5 | 145 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S }, |
b6016b76 MC |
146 | { 0, } |
147 | }; | |
148 | ||
0ced9d01 | 149 | static const struct flash_spec flash_table[] = |
b6016b76 | 150 | { |
e30372c9 MC |
151 | #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE) |
152 | #define NONBUFFERED_FLAGS (BNX2_NV_WREN) | |
b6016b76 | 153 | /* Slow EEPROM */ |
37137709 | 154 | {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, |
e30372c9 | 155 | BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, |
b6016b76 MC |
156 | SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, |
157 | "EEPROM - slow"}, | |
37137709 MC |
158 | /* Expansion entry 0001 */ |
159 | {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 160 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
161 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
162 | "Entry 0001"}, | |
b6016b76 MC |
163 | /* Saifun SA25F010 (non-buffered flash) */ |
164 | /* strap, cfg1, & write1 need updates */ | |
37137709 | 165 | {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, |
e30372c9 | 166 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
b6016b76 MC |
167 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, |
168 | "Non-buffered flash (128kB)"}, | |
169 | /* Saifun SA25F020 (non-buffered flash) */ | |
170 | /* strap, cfg1, & write1 need updates */ | |
37137709 | 171 | {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, |
e30372c9 | 172 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
b6016b76 MC |
173 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, |
174 | "Non-buffered flash (256kB)"}, | |
37137709 MC |
175 | /* Expansion entry 0100 */ |
176 | {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 177 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
178 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
179 | "Entry 0100"}, | |
180 | /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ | |
6aa20a22 | 181 | {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, |
e30372c9 | 182 | NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, |
37137709 MC |
183 | ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, |
184 | "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, | |
185 | /* Entry 0110: ST M45PE20 (non-buffered flash)*/ | |
186 | {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, | |
e30372c9 | 187 | NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, |
37137709 MC |
188 | ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, |
189 | "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, | |
190 | /* Saifun SA25F005 (non-buffered flash) */ | |
191 | /* strap, cfg1, & write1 need updates */ | |
192 | {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 193 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
194 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, |
195 | "Non-buffered flash (64kB)"}, | |
196 | /* Fast EEPROM */ | |
197 | {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, | |
e30372c9 | 198 | BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, |
37137709 MC |
199 | SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, |
200 | "EEPROM - fast"}, | |
201 | /* Expansion entry 1001 */ | |
202 | {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 203 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
204 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
205 | "Entry 1001"}, | |
206 | /* Expansion entry 1010 */ | |
207 | {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 208 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
209 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
210 | "Entry 1010"}, | |
211 | /* ATMEL AT45DB011B (buffered flash) */ | |
212 | {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, | |
e30372c9 | 213 | BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, |
37137709 MC |
214 | BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, |
215 | "Buffered flash (128kB)"}, | |
216 | /* Expansion entry 1100 */ | |
217 | {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 218 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
219 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
220 | "Entry 1100"}, | |
221 | /* Expansion entry 1101 */ | |
222 | {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, | |
e30372c9 | 223 | NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, |
37137709 MC |
224 | SAIFUN_FLASH_BYTE_ADDR_MASK, 0, |
225 | "Entry 1101"}, | |
226 | /* Ateml Expansion entry 1110 */ | |
227 | {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, | |
e30372c9 | 228 | BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, |
37137709 MC |
229 | BUFFERED_FLASH_BYTE_ADDR_MASK, 0, |
230 | "Entry 1110 (Atmel)"}, | |
231 | /* ATMEL AT45DB021B (buffered flash) */ | |
232 | {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, | |
e30372c9 | 233 | BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, |
37137709 MC |
234 | BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, |
235 | "Buffered flash (256kB)"}, | |
b6016b76 MC |
236 | }; |
237 | ||
0ced9d01 | 238 | static const struct flash_spec flash_5709 = { |
e30372c9 MC |
239 | .flags = BNX2_NV_BUFFERED, |
240 | .page_bits = BCM5709_FLASH_PAGE_BITS, | |
241 | .page_size = BCM5709_FLASH_PAGE_SIZE, | |
242 | .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, | |
243 | .total_size = BUFFERED_FLASH_TOTAL_SIZE*2, | |
244 | .name = "5709 Buffered flash (256kB)", | |
245 | }; | |
246 | ||
b6016b76 MC |
247 | MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); |
248 | ||
4327ba43 | 249 | static void bnx2_init_napi(struct bnx2 *bp); |
f048fa9c | 250 | static void bnx2_del_napi(struct bnx2 *bp); |
4327ba43 | 251 | |
35e9010b | 252 | static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr) |
e89bbf10 | 253 | { |
2f8af120 | 254 | u32 diff; |
e89bbf10 | 255 | |
11848b96 MC |
256 | /* Tell compiler to fetch tx_prod and tx_cons from memory. */ |
257 | barrier(); | |
faac9c4b MC |
258 | |
259 | /* The ring uses 256 indices for 255 entries, one of them | |
260 | * needs to be skipped. | |
261 | */ | |
35e9010b | 262 | diff = txr->tx_prod - txr->tx_cons; |
2bc4078e | 263 | if (unlikely(diff >= BNX2_TX_DESC_CNT)) { |
faac9c4b | 264 | diff &= 0xffff; |
2bc4078e MC |
265 | if (diff == BNX2_TX_DESC_CNT) |
266 | diff = BNX2_MAX_TX_DESC_CNT; | |
faac9c4b | 267 | } |
807540ba | 268 | return bp->tx_ring_size - diff; |
e89bbf10 MC |
269 | } |
270 | ||
b6016b76 MC |
271 | static u32 |
272 | bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) | |
273 | { | |
1b8227c4 MC |
274 | u32 val; |
275 | ||
276 | spin_lock_bh(&bp->indirect_lock); | |
e503e066 MC |
277 | BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); |
278 | val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW); | |
1b8227c4 MC |
279 | spin_unlock_bh(&bp->indirect_lock); |
280 | return val; | |
b6016b76 MC |
281 | } |
282 | ||
283 | static void | |
284 | bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) | |
285 | { | |
1b8227c4 | 286 | spin_lock_bh(&bp->indirect_lock); |
e503e066 MC |
287 | BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); |
288 | BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val); | |
1b8227c4 | 289 | spin_unlock_bh(&bp->indirect_lock); |
b6016b76 MC |
290 | } |
291 | ||
2726d6e1 MC |
292 | static void |
293 | bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val) | |
294 | { | |
295 | bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val); | |
296 | } | |
297 | ||
298 | static u32 | |
299 | bnx2_shmem_rd(struct bnx2 *bp, u32 offset) | |
300 | { | |
807540ba | 301 | return bnx2_reg_rd_ind(bp, bp->shmem_base + offset); |
2726d6e1 MC |
302 | } |
303 | ||
b6016b76 MC |
304 | static void |
305 | bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) | |
306 | { | |
307 | offset += cid_addr; | |
1b8227c4 | 308 | spin_lock_bh(&bp->indirect_lock); |
4ce45e02 | 309 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
59b47d8a MC |
310 | int i; |
311 | ||
e503e066 MC |
312 | BNX2_WR(bp, BNX2_CTX_CTX_DATA, val); |
313 | BNX2_WR(bp, BNX2_CTX_CTX_CTRL, | |
314 | offset | BNX2_CTX_CTX_CTRL_WRITE_REQ); | |
59b47d8a | 315 | for (i = 0; i < 5; i++) { |
e503e066 | 316 | val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL); |
59b47d8a MC |
317 | if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) |
318 | break; | |
319 | udelay(5); | |
320 | } | |
321 | } else { | |
e503e066 MC |
322 | BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset); |
323 | BNX2_WR(bp, BNX2_CTX_DATA, val); | |
59b47d8a | 324 | } |
1b8227c4 | 325 | spin_unlock_bh(&bp->indirect_lock); |
b6016b76 MC |
326 | } |
327 | ||
4edd473f MC |
328 | #ifdef BCM_CNIC |
329 | static int | |
330 | bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info) | |
331 | { | |
332 | struct bnx2 *bp = netdev_priv(dev); | |
333 | struct drv_ctl_io *io = &info->data.io; | |
334 | ||
335 | switch (info->cmd) { | |
336 | case DRV_CTL_IO_WR_CMD: | |
337 | bnx2_reg_wr_ind(bp, io->offset, io->data); | |
338 | break; | |
339 | case DRV_CTL_IO_RD_CMD: | |
340 | io->data = bnx2_reg_rd_ind(bp, io->offset); | |
341 | break; | |
342 | case DRV_CTL_CTX_WR_CMD: | |
343 | bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data); | |
344 | break; | |
345 | default: | |
346 | return -EINVAL; | |
347 | } | |
348 | return 0; | |
349 | } | |
350 | ||
351 | static void bnx2_setup_cnic_irq_info(struct bnx2 *bp) | |
352 | { | |
353 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
354 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; | |
355 | int sb_id; | |
356 | ||
357 | if (bp->flags & BNX2_FLAG_USING_MSIX) { | |
358 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
359 | bnapi->cnic_present = 0; | |
360 | sb_id = bp->irq_nvecs; | |
361 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
362 | } else { | |
363 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
364 | bnapi->cnic_tag = bnapi->last_status_idx; | |
365 | bnapi->cnic_present = 1; | |
366 | sb_id = 0; | |
367 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
368 | } | |
369 | ||
370 | cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector; | |
371 | cp->irq_arr[0].status_blk = (void *) | |
372 | ((unsigned long) bnapi->status_blk.msi + | |
373 | (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id)); | |
374 | cp->irq_arr[0].status_blk_num = sb_id; | |
375 | cp->num_irq = 1; | |
376 | } | |
377 | ||
378 | static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops, | |
379 | void *data) | |
380 | { | |
381 | struct bnx2 *bp = netdev_priv(dev); | |
382 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
383 | ||
384 | if (ops == NULL) | |
385 | return -EINVAL; | |
386 | ||
387 | if (cp->drv_state & CNIC_DRV_STATE_REGD) | |
388 | return -EBUSY; | |
389 | ||
41c2178a MC |
390 | if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN)) |
391 | return -ENODEV; | |
392 | ||
4edd473f MC |
393 | bp->cnic_data = data; |
394 | rcu_assign_pointer(bp->cnic_ops, ops); | |
395 | ||
396 | cp->num_irq = 0; | |
397 | cp->drv_state = CNIC_DRV_STATE_REGD; | |
398 | ||
399 | bnx2_setup_cnic_irq_info(bp); | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
404 | static int bnx2_unregister_cnic(struct net_device *dev) | |
405 | { | |
406 | struct bnx2 *bp = netdev_priv(dev); | |
407 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; | |
408 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
409 | ||
c5a88950 | 410 | mutex_lock(&bp->cnic_lock); |
4edd473f MC |
411 | cp->drv_state = 0; |
412 | bnapi->cnic_present = 0; | |
2cfa5a04 | 413 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
c5a88950 | 414 | mutex_unlock(&bp->cnic_lock); |
4edd473f MC |
415 | synchronize_rcu(); |
416 | return 0; | |
417 | } | |
418 | ||
61c2fc4b | 419 | static struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev) |
4edd473f MC |
420 | { |
421 | struct bnx2 *bp = netdev_priv(dev); | |
422 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
423 | ||
7625eb2f MC |
424 | if (!cp->max_iscsi_conn) |
425 | return NULL; | |
426 | ||
4edd473f MC |
427 | cp->drv_owner = THIS_MODULE; |
428 | cp->chip_id = bp->chip_id; | |
429 | cp->pdev = bp->pdev; | |
430 | cp->io_base = bp->regview; | |
431 | cp->drv_ctl = bnx2_drv_ctl; | |
432 | cp->drv_register_cnic = bnx2_register_cnic; | |
433 | cp->drv_unregister_cnic = bnx2_unregister_cnic; | |
434 | ||
435 | return cp; | |
436 | } | |
4edd473f MC |
437 | |
438 | static void | |
439 | bnx2_cnic_stop(struct bnx2 *bp) | |
440 | { | |
441 | struct cnic_ops *c_ops; | |
442 | struct cnic_ctl_info info; | |
443 | ||
c5a88950 | 444 | mutex_lock(&bp->cnic_lock); |
13707f9e ED |
445 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
446 | lockdep_is_held(&bp->cnic_lock)); | |
4edd473f MC |
447 | if (c_ops) { |
448 | info.cmd = CNIC_CTL_STOP_CMD; | |
449 | c_ops->cnic_ctl(bp->cnic_data, &info); | |
450 | } | |
c5a88950 | 451 | mutex_unlock(&bp->cnic_lock); |
4edd473f MC |
452 | } |
453 | ||
454 | static void | |
455 | bnx2_cnic_start(struct bnx2 *bp) | |
456 | { | |
457 | struct cnic_ops *c_ops; | |
458 | struct cnic_ctl_info info; | |
459 | ||
c5a88950 | 460 | mutex_lock(&bp->cnic_lock); |
13707f9e ED |
461 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
462 | lockdep_is_held(&bp->cnic_lock)); | |
4edd473f MC |
463 | if (c_ops) { |
464 | if (!(bp->flags & BNX2_FLAG_USING_MSIX)) { | |
465 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; | |
466 | ||
467 | bnapi->cnic_tag = bnapi->last_status_idx; | |
468 | } | |
469 | info.cmd = CNIC_CTL_START_CMD; | |
470 | c_ops->cnic_ctl(bp->cnic_data, &info); | |
471 | } | |
c5a88950 | 472 | mutex_unlock(&bp->cnic_lock); |
4edd473f MC |
473 | } |
474 | ||
475 | #else | |
476 | ||
477 | static void | |
478 | bnx2_cnic_stop(struct bnx2 *bp) | |
479 | { | |
480 | } | |
481 | ||
482 | static void | |
483 | bnx2_cnic_start(struct bnx2 *bp) | |
484 | { | |
485 | } | |
486 | ||
487 | #endif | |
488 | ||
b6016b76 MC |
489 | static int |
490 | bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) | |
491 | { | |
492 | u32 val1; | |
493 | int i, ret; | |
494 | ||
583c28e5 | 495 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
e503e066 | 496 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); |
b6016b76 MC |
497 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; |
498 | ||
e503e066 MC |
499 | BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); |
500 | BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); | |
b6016b76 MC |
501 | |
502 | udelay(40); | |
503 | } | |
504 | ||
505 | val1 = (bp->phy_addr << 21) | (reg << 16) | | |
506 | BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT | | |
507 | BNX2_EMAC_MDIO_COMM_START_BUSY; | |
e503e066 | 508 | BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1); |
b6016b76 MC |
509 | |
510 | for (i = 0; i < 50; i++) { | |
511 | udelay(10); | |
512 | ||
e503e066 | 513 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); |
b6016b76 MC |
514 | if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { |
515 | udelay(5); | |
516 | ||
e503e066 | 517 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); |
b6016b76 MC |
518 | val1 &= BNX2_EMAC_MDIO_COMM_DATA; |
519 | ||
520 | break; | |
521 | } | |
522 | } | |
523 | ||
524 | if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) { | |
525 | *val = 0x0; | |
526 | ret = -EBUSY; | |
527 | } | |
528 | else { | |
529 | *val = val1; | |
530 | ret = 0; | |
531 | } | |
532 | ||
583c28e5 | 533 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
e503e066 | 534 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); |
b6016b76 MC |
535 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; |
536 | ||
e503e066 MC |
537 | BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); |
538 | BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); | |
b6016b76 MC |
539 | |
540 | udelay(40); | |
541 | } | |
542 | ||
543 | return ret; | |
544 | } | |
545 | ||
546 | static int | |
547 | bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) | |
548 | { | |
549 | u32 val1; | |
550 | int i, ret; | |
551 | ||
583c28e5 | 552 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
e503e066 | 553 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); |
b6016b76 MC |
554 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; |
555 | ||
e503e066 MC |
556 | BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); |
557 | BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); | |
b6016b76 MC |
558 | |
559 | udelay(40); | |
560 | } | |
561 | ||
562 | val1 = (bp->phy_addr << 21) | (reg << 16) | val | | |
563 | BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | | |
564 | BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; | |
e503e066 | 565 | BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1); |
6aa20a22 | 566 | |
b6016b76 MC |
567 | for (i = 0; i < 50; i++) { |
568 | udelay(10); | |
569 | ||
e503e066 | 570 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); |
b6016b76 MC |
571 | if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { |
572 | udelay(5); | |
573 | break; | |
574 | } | |
575 | } | |
576 | ||
577 | if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) | |
578 | ret = -EBUSY; | |
579 | else | |
580 | ret = 0; | |
581 | ||
583c28e5 | 582 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
e503e066 | 583 | val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); |
b6016b76 MC |
584 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; |
585 | ||
e503e066 MC |
586 | BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); |
587 | BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); | |
b6016b76 MC |
588 | |
589 | udelay(40); | |
590 | } | |
591 | ||
592 | return ret; | |
593 | } | |
594 | ||
595 | static void | |
596 | bnx2_disable_int(struct bnx2 *bp) | |
597 | { | |
b4b36042 MC |
598 | int i; |
599 | struct bnx2_napi *bnapi; | |
600 | ||
601 | for (i = 0; i < bp->irq_nvecs; i++) { | |
602 | bnapi = &bp->bnx2_napi[i]; | |
e503e066 | 603 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
b4b36042 MC |
604 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); |
605 | } | |
e503e066 | 606 | BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); |
b6016b76 MC |
607 | } |
608 | ||
609 | static void | |
610 | bnx2_enable_int(struct bnx2 *bp) | |
611 | { | |
b4b36042 MC |
612 | int i; |
613 | struct bnx2_napi *bnapi; | |
35efa7c1 | 614 | |
b4b36042 MC |
615 | for (i = 0; i < bp->irq_nvecs; i++) { |
616 | bnapi = &bp->bnx2_napi[i]; | |
1269a8a6 | 617 | |
e503e066 MC |
618 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
619 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
620 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT | | |
621 | bnapi->last_status_idx); | |
b6016b76 | 622 | |
e503e066 MC |
623 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
624 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
625 | bnapi->last_status_idx); | |
b4b36042 | 626 | } |
e503e066 | 627 | BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); |
b6016b76 MC |
628 | } |
629 | ||
630 | static void | |
631 | bnx2_disable_int_sync(struct bnx2 *bp) | |
632 | { | |
b4b36042 MC |
633 | int i; |
634 | ||
b6016b76 | 635 | atomic_inc(&bp->intr_sem); |
3767546c MC |
636 | if (!netif_running(bp->dev)) |
637 | return; | |
638 | ||
b6016b76 | 639 | bnx2_disable_int(bp); |
b4b36042 MC |
640 | for (i = 0; i < bp->irq_nvecs; i++) |
641 | synchronize_irq(bp->irq_tbl[i].vector); | |
b6016b76 MC |
642 | } |
643 | ||
35efa7c1 MC |
644 | static void |
645 | bnx2_napi_disable(struct bnx2 *bp) | |
646 | { | |
b4b36042 MC |
647 | int i; |
648 | ||
649 | for (i = 0; i < bp->irq_nvecs; i++) | |
650 | napi_disable(&bp->bnx2_napi[i].napi); | |
35efa7c1 MC |
651 | } |
652 | ||
653 | static void | |
654 | bnx2_napi_enable(struct bnx2 *bp) | |
655 | { | |
b4b36042 MC |
656 | int i; |
657 | ||
658 | for (i = 0; i < bp->irq_nvecs; i++) | |
659 | napi_enable(&bp->bnx2_napi[i].napi); | |
35efa7c1 MC |
660 | } |
661 | ||
b6016b76 | 662 | static void |
212f9934 | 663 | bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic) |
b6016b76 | 664 | { |
212f9934 MC |
665 | if (stop_cnic) |
666 | bnx2_cnic_stop(bp); | |
b6016b76 | 667 | if (netif_running(bp->dev)) { |
35efa7c1 | 668 | bnx2_napi_disable(bp); |
b6016b76 | 669 | netif_tx_disable(bp->dev); |
b6016b76 | 670 | } |
b7466560 | 671 | bnx2_disable_int_sync(bp); |
a0ba6760 | 672 | netif_carrier_off(bp->dev); /* prevent tx timeout */ |
b6016b76 MC |
673 | } |
674 | ||
675 | static void | |
212f9934 | 676 | bnx2_netif_start(struct bnx2 *bp, bool start_cnic) |
b6016b76 MC |
677 | { |
678 | if (atomic_dec_and_test(&bp->intr_sem)) { | |
679 | if (netif_running(bp->dev)) { | |
706bf240 | 680 | netif_tx_wake_all_queues(bp->dev); |
a0ba6760 MC |
681 | spin_lock_bh(&bp->phy_lock); |
682 | if (bp->link_up) | |
683 | netif_carrier_on(bp->dev); | |
684 | spin_unlock_bh(&bp->phy_lock); | |
35efa7c1 | 685 | bnx2_napi_enable(bp); |
b6016b76 | 686 | bnx2_enable_int(bp); |
212f9934 MC |
687 | if (start_cnic) |
688 | bnx2_cnic_start(bp); | |
b6016b76 MC |
689 | } |
690 | } | |
691 | } | |
692 | ||
35e9010b MC |
693 | static void |
694 | bnx2_free_tx_mem(struct bnx2 *bp) | |
695 | { | |
696 | int i; | |
697 | ||
698 | for (i = 0; i < bp->num_tx_rings; i++) { | |
699 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
700 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; | |
701 | ||
702 | if (txr->tx_desc_ring) { | |
36227e88 SG |
703 | dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE, |
704 | txr->tx_desc_ring, | |
705 | txr->tx_desc_mapping); | |
35e9010b MC |
706 | txr->tx_desc_ring = NULL; |
707 | } | |
708 | kfree(txr->tx_buf_ring); | |
709 | txr->tx_buf_ring = NULL; | |
710 | } | |
711 | } | |
712 | ||
bb4f98ab MC |
713 | static void |
714 | bnx2_free_rx_mem(struct bnx2 *bp) | |
715 | { | |
716 | int i; | |
717 | ||
718 | for (i = 0; i < bp->num_rx_rings; i++) { | |
719 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
720 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
721 | int j; | |
722 | ||
723 | for (j = 0; j < bp->rx_max_ring; j++) { | |
724 | if (rxr->rx_desc_ring[j]) | |
36227e88 SG |
725 | dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, |
726 | rxr->rx_desc_ring[j], | |
727 | rxr->rx_desc_mapping[j]); | |
bb4f98ab MC |
728 | rxr->rx_desc_ring[j] = NULL; |
729 | } | |
25b0b999 | 730 | vfree(rxr->rx_buf_ring); |
bb4f98ab MC |
731 | rxr->rx_buf_ring = NULL; |
732 | ||
733 | for (j = 0; j < bp->rx_max_pg_ring; j++) { | |
734 | if (rxr->rx_pg_desc_ring[j]) | |
36227e88 SG |
735 | dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, |
736 | rxr->rx_pg_desc_ring[j], | |
737 | rxr->rx_pg_desc_mapping[j]); | |
3298a738 | 738 | rxr->rx_pg_desc_ring[j] = NULL; |
bb4f98ab | 739 | } |
25b0b999 | 740 | vfree(rxr->rx_pg_ring); |
bb4f98ab MC |
741 | rxr->rx_pg_ring = NULL; |
742 | } | |
743 | } | |
744 | ||
35e9010b MC |
745 | static int |
746 | bnx2_alloc_tx_mem(struct bnx2 *bp) | |
747 | { | |
748 | int i; | |
749 | ||
750 | for (i = 0; i < bp->num_tx_rings; i++) { | |
751 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
752 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; | |
753 | ||
754 | txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); | |
755 | if (txr->tx_buf_ring == NULL) | |
756 | return -ENOMEM; | |
757 | ||
758 | txr->tx_desc_ring = | |
36227e88 SG |
759 | dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE, |
760 | &txr->tx_desc_mapping, GFP_KERNEL); | |
35e9010b MC |
761 | if (txr->tx_desc_ring == NULL) |
762 | return -ENOMEM; | |
763 | } | |
764 | return 0; | |
765 | } | |
766 | ||
bb4f98ab MC |
767 | static int |
768 | bnx2_alloc_rx_mem(struct bnx2 *bp) | |
769 | { | |
770 | int i; | |
771 | ||
772 | for (i = 0; i < bp->num_rx_rings; i++) { | |
773 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
774 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
775 | int j; | |
776 | ||
777 | rxr->rx_buf_ring = | |
89bf67f1 | 778 | vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring); |
bb4f98ab MC |
779 | if (rxr->rx_buf_ring == NULL) |
780 | return -ENOMEM; | |
781 | ||
bb4f98ab MC |
782 | for (j = 0; j < bp->rx_max_ring; j++) { |
783 | rxr->rx_desc_ring[j] = | |
36227e88 SG |
784 | dma_alloc_coherent(&bp->pdev->dev, |
785 | RXBD_RING_SIZE, | |
786 | &rxr->rx_desc_mapping[j], | |
787 | GFP_KERNEL); | |
bb4f98ab MC |
788 | if (rxr->rx_desc_ring[j] == NULL) |
789 | return -ENOMEM; | |
790 | ||
791 | } | |
792 | ||
793 | if (bp->rx_pg_ring_size) { | |
89bf67f1 | 794 | rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE * |
bb4f98ab MC |
795 | bp->rx_max_pg_ring); |
796 | if (rxr->rx_pg_ring == NULL) | |
797 | return -ENOMEM; | |
798 | ||
bb4f98ab MC |
799 | } |
800 | ||
801 | for (j = 0; j < bp->rx_max_pg_ring; j++) { | |
802 | rxr->rx_pg_desc_ring[j] = | |
36227e88 SG |
803 | dma_alloc_coherent(&bp->pdev->dev, |
804 | RXBD_RING_SIZE, | |
805 | &rxr->rx_pg_desc_mapping[j], | |
806 | GFP_KERNEL); | |
bb4f98ab MC |
807 | if (rxr->rx_pg_desc_ring[j] == NULL) |
808 | return -ENOMEM; | |
809 | ||
810 | } | |
811 | } | |
812 | return 0; | |
813 | } | |
814 | ||
b6016b76 MC |
815 | static void |
816 | bnx2_free_mem(struct bnx2 *bp) | |
817 | { | |
13daffa2 | 818 | int i; |
43e80b89 | 819 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; |
13daffa2 | 820 | |
35e9010b | 821 | bnx2_free_tx_mem(bp); |
bb4f98ab | 822 | bnx2_free_rx_mem(bp); |
35e9010b | 823 | |
59b47d8a MC |
824 | for (i = 0; i < bp->ctx_pages; i++) { |
825 | if (bp->ctx_blk[i]) { | |
2bc4078e | 826 | dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE, |
36227e88 SG |
827 | bp->ctx_blk[i], |
828 | bp->ctx_blk_mapping[i]); | |
59b47d8a MC |
829 | bp->ctx_blk[i] = NULL; |
830 | } | |
831 | } | |
43e80b89 | 832 | if (bnapi->status_blk.msi) { |
36227e88 SG |
833 | dma_free_coherent(&bp->pdev->dev, bp->status_stats_size, |
834 | bnapi->status_blk.msi, | |
835 | bp->status_blk_mapping); | |
43e80b89 | 836 | bnapi->status_blk.msi = NULL; |
0f31f994 | 837 | bp->stats_blk = NULL; |
b6016b76 | 838 | } |
b6016b76 MC |
839 | } |
840 | ||
841 | static int | |
842 | bnx2_alloc_mem(struct bnx2 *bp) | |
843 | { | |
35e9010b | 844 | int i, status_blk_size, err; |
43e80b89 MC |
845 | struct bnx2_napi *bnapi; |
846 | void *status_blk; | |
b6016b76 | 847 | |
0f31f994 MC |
848 | /* Combine status and statistics blocks into one allocation. */ |
849 | status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); | |
f86e82fb | 850 | if (bp->flags & BNX2_FLAG_MSIX_CAP) |
b4b36042 MC |
851 | status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC * |
852 | BNX2_SBLK_MSIX_ALIGN_SIZE); | |
0f31f994 MC |
853 | bp->status_stats_size = status_blk_size + |
854 | sizeof(struct statistics_block); | |
855 | ||
36227e88 | 856 | status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size, |
1f9061d2 JP |
857 | &bp->status_blk_mapping, |
858 | GFP_KERNEL | __GFP_ZERO); | |
43e80b89 | 859 | if (status_blk == NULL) |
b6016b76 MC |
860 | goto alloc_mem_err; |
861 | ||
43e80b89 MC |
862 | bnapi = &bp->bnx2_napi[0]; |
863 | bnapi->status_blk.msi = status_blk; | |
864 | bnapi->hw_tx_cons_ptr = | |
865 | &bnapi->status_blk.msi->status_tx_quick_consumer_index0; | |
866 | bnapi->hw_rx_cons_ptr = | |
867 | &bnapi->status_blk.msi->status_rx_quick_consumer_index0; | |
f86e82fb | 868 | if (bp->flags & BNX2_FLAG_MSIX_CAP) { |
379b39a2 | 869 | for (i = 1; i < bp->irq_nvecs; i++) { |
43e80b89 MC |
870 | struct status_block_msix *sblk; |
871 | ||
872 | bnapi = &bp->bnx2_napi[i]; | |
b4b36042 | 873 | |
64699336 | 874 | sblk = (status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i); |
43e80b89 MC |
875 | bnapi->status_blk.msix = sblk; |
876 | bnapi->hw_tx_cons_ptr = | |
877 | &sblk->status_tx_quick_consumer_index; | |
878 | bnapi->hw_rx_cons_ptr = | |
879 | &sblk->status_rx_quick_consumer_index; | |
b4b36042 MC |
880 | bnapi->int_num = i << 24; |
881 | } | |
882 | } | |
35efa7c1 | 883 | |
43e80b89 | 884 | bp->stats_blk = status_blk + status_blk_size; |
b6016b76 | 885 | |
0f31f994 | 886 | bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; |
b6016b76 | 887 | |
4ce45e02 | 888 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
2bc4078e | 889 | bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE; |
59b47d8a MC |
890 | if (bp->ctx_pages == 0) |
891 | bp->ctx_pages = 1; | |
892 | for (i = 0; i < bp->ctx_pages; i++) { | |
36227e88 | 893 | bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev, |
2bc4078e | 894 | BNX2_PAGE_SIZE, |
36227e88 SG |
895 | &bp->ctx_blk_mapping[i], |
896 | GFP_KERNEL); | |
59b47d8a MC |
897 | if (bp->ctx_blk[i] == NULL) |
898 | goto alloc_mem_err; | |
899 | } | |
900 | } | |
35e9010b | 901 | |
bb4f98ab MC |
902 | err = bnx2_alloc_rx_mem(bp); |
903 | if (err) | |
904 | goto alloc_mem_err; | |
905 | ||
35e9010b MC |
906 | err = bnx2_alloc_tx_mem(bp); |
907 | if (err) | |
908 | goto alloc_mem_err; | |
909 | ||
b6016b76 MC |
910 | return 0; |
911 | ||
912 | alloc_mem_err: | |
913 | bnx2_free_mem(bp); | |
914 | return -ENOMEM; | |
915 | } | |
916 | ||
e3648b3d MC |
917 | static void |
918 | bnx2_report_fw_link(struct bnx2 *bp) | |
919 | { | |
920 | u32 fw_link_status = 0; | |
921 | ||
583c28e5 | 922 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
923 | return; |
924 | ||
e3648b3d MC |
925 | if (bp->link_up) { |
926 | u32 bmsr; | |
927 | ||
928 | switch (bp->line_speed) { | |
929 | case SPEED_10: | |
930 | if (bp->duplex == DUPLEX_HALF) | |
931 | fw_link_status = BNX2_LINK_STATUS_10HALF; | |
932 | else | |
933 | fw_link_status = BNX2_LINK_STATUS_10FULL; | |
934 | break; | |
935 | case SPEED_100: | |
936 | if (bp->duplex == DUPLEX_HALF) | |
937 | fw_link_status = BNX2_LINK_STATUS_100HALF; | |
938 | else | |
939 | fw_link_status = BNX2_LINK_STATUS_100FULL; | |
940 | break; | |
941 | case SPEED_1000: | |
942 | if (bp->duplex == DUPLEX_HALF) | |
943 | fw_link_status = BNX2_LINK_STATUS_1000HALF; | |
944 | else | |
945 | fw_link_status = BNX2_LINK_STATUS_1000FULL; | |
946 | break; | |
947 | case SPEED_2500: | |
948 | if (bp->duplex == DUPLEX_HALF) | |
949 | fw_link_status = BNX2_LINK_STATUS_2500HALF; | |
950 | else | |
951 | fw_link_status = BNX2_LINK_STATUS_2500FULL; | |
952 | break; | |
953 | } | |
954 | ||
955 | fw_link_status |= BNX2_LINK_STATUS_LINK_UP; | |
956 | ||
957 | if (bp->autoneg) { | |
958 | fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED; | |
959 | ||
ca58c3af MC |
960 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
961 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | |
e3648b3d MC |
962 | |
963 | if (!(bmsr & BMSR_ANEGCOMPLETE) || | |
583c28e5 | 964 | bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) |
e3648b3d MC |
965 | fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET; |
966 | else | |
967 | fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE; | |
968 | } | |
969 | } | |
970 | else | |
971 | fw_link_status = BNX2_LINK_STATUS_LINK_DOWN; | |
972 | ||
2726d6e1 | 973 | bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status); |
e3648b3d MC |
974 | } |
975 | ||
9b1084b8 MC |
976 | static char * |
977 | bnx2_xceiver_str(struct bnx2 *bp) | |
978 | { | |
807540ba | 979 | return (bp->phy_port == PORT_FIBRE) ? "SerDes" : |
583c28e5 | 980 | ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" : |
807540ba | 981 | "Copper"); |
9b1084b8 MC |
982 | } |
983 | ||
b6016b76 MC |
984 | static void |
985 | bnx2_report_link(struct bnx2 *bp) | |
986 | { | |
987 | if (bp->link_up) { | |
988 | netif_carrier_on(bp->dev); | |
3a9c6a49 JP |
989 | netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex", |
990 | bnx2_xceiver_str(bp), | |
991 | bp->line_speed, | |
992 | bp->duplex == DUPLEX_FULL ? "full" : "half"); | |
b6016b76 MC |
993 | |
994 | if (bp->flow_ctrl) { | |
995 | if (bp->flow_ctrl & FLOW_CTRL_RX) { | |
3a9c6a49 | 996 | pr_cont(", receive "); |
b6016b76 | 997 | if (bp->flow_ctrl & FLOW_CTRL_TX) |
3a9c6a49 | 998 | pr_cont("& transmit "); |
b6016b76 MC |
999 | } |
1000 | else { | |
3a9c6a49 | 1001 | pr_cont(", transmit "); |
b6016b76 | 1002 | } |
3a9c6a49 | 1003 | pr_cont("flow control ON"); |
b6016b76 | 1004 | } |
3a9c6a49 JP |
1005 | pr_cont("\n"); |
1006 | } else { | |
b6016b76 | 1007 | netif_carrier_off(bp->dev); |
3a9c6a49 JP |
1008 | netdev_err(bp->dev, "NIC %s Link is Down\n", |
1009 | bnx2_xceiver_str(bp)); | |
b6016b76 | 1010 | } |
e3648b3d MC |
1011 | |
1012 | bnx2_report_fw_link(bp); | |
b6016b76 MC |
1013 | } |
1014 | ||
1015 | static void | |
1016 | bnx2_resolve_flow_ctrl(struct bnx2 *bp) | |
1017 | { | |
1018 | u32 local_adv, remote_adv; | |
1019 | ||
1020 | bp->flow_ctrl = 0; | |
6aa20a22 | 1021 | if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != |
b6016b76 MC |
1022 | (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { |
1023 | ||
1024 | if (bp->duplex == DUPLEX_FULL) { | |
1025 | bp->flow_ctrl = bp->req_flow_ctrl; | |
1026 | } | |
1027 | return; | |
1028 | } | |
1029 | ||
1030 | if (bp->duplex != DUPLEX_FULL) { | |
1031 | return; | |
1032 | } | |
1033 | ||
583c28e5 | 1034 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
4ce45e02 | 1035 | (BNX2_CHIP(bp) == BNX2_CHIP_5708)) { |
5b0c76ad MC |
1036 | u32 val; |
1037 | ||
1038 | bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); | |
1039 | if (val & BCM5708S_1000X_STAT1_TX_PAUSE) | |
1040 | bp->flow_ctrl |= FLOW_CTRL_TX; | |
1041 | if (val & BCM5708S_1000X_STAT1_RX_PAUSE) | |
1042 | bp->flow_ctrl |= FLOW_CTRL_RX; | |
1043 | return; | |
1044 | } | |
1045 | ||
ca58c3af MC |
1046 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
1047 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | |
b6016b76 | 1048 | |
583c28e5 | 1049 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
b6016b76 MC |
1050 | u32 new_local_adv = 0; |
1051 | u32 new_remote_adv = 0; | |
1052 | ||
1053 | if (local_adv & ADVERTISE_1000XPAUSE) | |
1054 | new_local_adv |= ADVERTISE_PAUSE_CAP; | |
1055 | if (local_adv & ADVERTISE_1000XPSE_ASYM) | |
1056 | new_local_adv |= ADVERTISE_PAUSE_ASYM; | |
1057 | if (remote_adv & ADVERTISE_1000XPAUSE) | |
1058 | new_remote_adv |= ADVERTISE_PAUSE_CAP; | |
1059 | if (remote_adv & ADVERTISE_1000XPSE_ASYM) | |
1060 | new_remote_adv |= ADVERTISE_PAUSE_ASYM; | |
1061 | ||
1062 | local_adv = new_local_adv; | |
1063 | remote_adv = new_remote_adv; | |
1064 | } | |
1065 | ||
1066 | /* See Table 28B-3 of 802.3ab-1999 spec. */ | |
1067 | if (local_adv & ADVERTISE_PAUSE_CAP) { | |
1068 | if(local_adv & ADVERTISE_PAUSE_ASYM) { | |
1069 | if (remote_adv & ADVERTISE_PAUSE_CAP) { | |
1070 | bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1071 | } | |
1072 | else if (remote_adv & ADVERTISE_PAUSE_ASYM) { | |
1073 | bp->flow_ctrl = FLOW_CTRL_RX; | |
1074 | } | |
1075 | } | |
1076 | else { | |
1077 | if (remote_adv & ADVERTISE_PAUSE_CAP) { | |
1078 | bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
1079 | } | |
1080 | } | |
1081 | } | |
1082 | else if (local_adv & ADVERTISE_PAUSE_ASYM) { | |
1083 | if ((remote_adv & ADVERTISE_PAUSE_CAP) && | |
1084 | (remote_adv & ADVERTISE_PAUSE_ASYM)) { | |
1085 | ||
1086 | bp->flow_ctrl = FLOW_CTRL_TX; | |
1087 | } | |
1088 | } | |
1089 | } | |
1090 | ||
27a005b8 MC |
1091 | static int |
1092 | bnx2_5709s_linkup(struct bnx2 *bp) | |
1093 | { | |
1094 | u32 val, speed; | |
1095 | ||
1096 | bp->link_up = 1; | |
1097 | ||
1098 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); | |
1099 | bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val); | |
1100 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1101 | ||
1102 | if ((bp->autoneg & AUTONEG_SPEED) == 0) { | |
1103 | bp->line_speed = bp->req_line_speed; | |
1104 | bp->duplex = bp->req_duplex; | |
1105 | return 0; | |
1106 | } | |
1107 | speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK; | |
1108 | switch (speed) { | |
1109 | case MII_BNX2_GP_TOP_AN_SPEED_10: | |
1110 | bp->line_speed = SPEED_10; | |
1111 | break; | |
1112 | case MII_BNX2_GP_TOP_AN_SPEED_100: | |
1113 | bp->line_speed = SPEED_100; | |
1114 | break; | |
1115 | case MII_BNX2_GP_TOP_AN_SPEED_1G: | |
1116 | case MII_BNX2_GP_TOP_AN_SPEED_1GKV: | |
1117 | bp->line_speed = SPEED_1000; | |
1118 | break; | |
1119 | case MII_BNX2_GP_TOP_AN_SPEED_2_5G: | |
1120 | bp->line_speed = SPEED_2500; | |
1121 | break; | |
1122 | } | |
1123 | if (val & MII_BNX2_GP_TOP_AN_FD) | |
1124 | bp->duplex = DUPLEX_FULL; | |
1125 | else | |
1126 | bp->duplex = DUPLEX_HALF; | |
1127 | return 0; | |
1128 | } | |
1129 | ||
b6016b76 | 1130 | static int |
5b0c76ad MC |
1131 | bnx2_5708s_linkup(struct bnx2 *bp) |
1132 | { | |
1133 | u32 val; | |
1134 | ||
1135 | bp->link_up = 1; | |
1136 | bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); | |
1137 | switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) { | |
1138 | case BCM5708S_1000X_STAT1_SPEED_10: | |
1139 | bp->line_speed = SPEED_10; | |
1140 | break; | |
1141 | case BCM5708S_1000X_STAT1_SPEED_100: | |
1142 | bp->line_speed = SPEED_100; | |
1143 | break; | |
1144 | case BCM5708S_1000X_STAT1_SPEED_1G: | |
1145 | bp->line_speed = SPEED_1000; | |
1146 | break; | |
1147 | case BCM5708S_1000X_STAT1_SPEED_2G5: | |
1148 | bp->line_speed = SPEED_2500; | |
1149 | break; | |
1150 | } | |
1151 | if (val & BCM5708S_1000X_STAT1_FD) | |
1152 | bp->duplex = DUPLEX_FULL; | |
1153 | else | |
1154 | bp->duplex = DUPLEX_HALF; | |
1155 | ||
1156 | return 0; | |
1157 | } | |
1158 | ||
1159 | static int | |
1160 | bnx2_5706s_linkup(struct bnx2 *bp) | |
b6016b76 MC |
1161 | { |
1162 | u32 bmcr, local_adv, remote_adv, common; | |
1163 | ||
1164 | bp->link_up = 1; | |
1165 | bp->line_speed = SPEED_1000; | |
1166 | ||
ca58c3af | 1167 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 MC |
1168 | if (bmcr & BMCR_FULLDPLX) { |
1169 | bp->duplex = DUPLEX_FULL; | |
1170 | } | |
1171 | else { | |
1172 | bp->duplex = DUPLEX_HALF; | |
1173 | } | |
1174 | ||
1175 | if (!(bmcr & BMCR_ANENABLE)) { | |
1176 | return 0; | |
1177 | } | |
1178 | ||
ca58c3af MC |
1179 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
1180 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | |
b6016b76 MC |
1181 | |
1182 | common = local_adv & remote_adv; | |
1183 | if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { | |
1184 | ||
1185 | if (common & ADVERTISE_1000XFULL) { | |
1186 | bp->duplex = DUPLEX_FULL; | |
1187 | } | |
1188 | else { | |
1189 | bp->duplex = DUPLEX_HALF; | |
1190 | } | |
1191 | } | |
1192 | ||
1193 | return 0; | |
1194 | } | |
1195 | ||
1196 | static int | |
1197 | bnx2_copper_linkup(struct bnx2 *bp) | |
1198 | { | |
1199 | u32 bmcr; | |
1200 | ||
ca58c3af | 1201 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 MC |
1202 | if (bmcr & BMCR_ANENABLE) { |
1203 | u32 local_adv, remote_adv, common; | |
1204 | ||
1205 | bnx2_read_phy(bp, MII_CTRL1000, &local_adv); | |
1206 | bnx2_read_phy(bp, MII_STAT1000, &remote_adv); | |
1207 | ||
1208 | common = local_adv & (remote_adv >> 2); | |
1209 | if (common & ADVERTISE_1000FULL) { | |
1210 | bp->line_speed = SPEED_1000; | |
1211 | bp->duplex = DUPLEX_FULL; | |
1212 | } | |
1213 | else if (common & ADVERTISE_1000HALF) { | |
1214 | bp->line_speed = SPEED_1000; | |
1215 | bp->duplex = DUPLEX_HALF; | |
1216 | } | |
1217 | else { | |
ca58c3af MC |
1218 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
1219 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | |
b6016b76 MC |
1220 | |
1221 | common = local_adv & remote_adv; | |
1222 | if (common & ADVERTISE_100FULL) { | |
1223 | bp->line_speed = SPEED_100; | |
1224 | bp->duplex = DUPLEX_FULL; | |
1225 | } | |
1226 | else if (common & ADVERTISE_100HALF) { | |
1227 | bp->line_speed = SPEED_100; | |
1228 | bp->duplex = DUPLEX_HALF; | |
1229 | } | |
1230 | else if (common & ADVERTISE_10FULL) { | |
1231 | bp->line_speed = SPEED_10; | |
1232 | bp->duplex = DUPLEX_FULL; | |
1233 | } | |
1234 | else if (common & ADVERTISE_10HALF) { | |
1235 | bp->line_speed = SPEED_10; | |
1236 | bp->duplex = DUPLEX_HALF; | |
1237 | } | |
1238 | else { | |
1239 | bp->line_speed = 0; | |
1240 | bp->link_up = 0; | |
1241 | } | |
1242 | } | |
1243 | } | |
1244 | else { | |
1245 | if (bmcr & BMCR_SPEED100) { | |
1246 | bp->line_speed = SPEED_100; | |
1247 | } | |
1248 | else { | |
1249 | bp->line_speed = SPEED_10; | |
1250 | } | |
1251 | if (bmcr & BMCR_FULLDPLX) { | |
1252 | bp->duplex = DUPLEX_FULL; | |
1253 | } | |
1254 | else { | |
1255 | bp->duplex = DUPLEX_HALF; | |
1256 | } | |
1257 | } | |
1258 | ||
1259 | return 0; | |
1260 | } | |
1261 | ||
83e3fc89 | 1262 | static void |
bb4f98ab | 1263 | bnx2_init_rx_context(struct bnx2 *bp, u32 cid) |
83e3fc89 | 1264 | { |
bb4f98ab | 1265 | u32 val, rx_cid_addr = GET_CID_ADDR(cid); |
83e3fc89 MC |
1266 | |
1267 | val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; | |
1268 | val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; | |
1269 | val |= 0x02 << 8; | |
1270 | ||
22fa159d MC |
1271 | if (bp->flow_ctrl & FLOW_CTRL_TX) |
1272 | val |= BNX2_L2CTX_FLOW_CTRL_ENABLE; | |
83e3fc89 | 1273 | |
83e3fc89 MC |
1274 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); |
1275 | } | |
1276 | ||
bb4f98ab MC |
1277 | static void |
1278 | bnx2_init_all_rx_contexts(struct bnx2 *bp) | |
1279 | { | |
1280 | int i; | |
1281 | u32 cid; | |
1282 | ||
1283 | for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) { | |
1284 | if (i == 1) | |
1285 | cid = RX_RSS_CID; | |
1286 | bnx2_init_rx_context(bp, cid); | |
1287 | } | |
1288 | } | |
1289 | ||
344478db | 1290 | static void |
b6016b76 MC |
1291 | bnx2_set_mac_link(struct bnx2 *bp) |
1292 | { | |
1293 | u32 val; | |
1294 | ||
e503e066 | 1295 | BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); |
b6016b76 MC |
1296 | if (bp->link_up && (bp->line_speed == SPEED_1000) && |
1297 | (bp->duplex == DUPLEX_HALF)) { | |
e503e066 | 1298 | BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); |
b6016b76 MC |
1299 | } |
1300 | ||
1301 | /* Configure the EMAC mode register. */ | |
e503e066 | 1302 | val = BNX2_RD(bp, BNX2_EMAC_MODE); |
b6016b76 MC |
1303 | |
1304 | val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | | |
5b0c76ad | 1305 | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | |
59b47d8a | 1306 | BNX2_EMAC_MODE_25G_MODE); |
b6016b76 MC |
1307 | |
1308 | if (bp->link_up) { | |
5b0c76ad MC |
1309 | switch (bp->line_speed) { |
1310 | case SPEED_10: | |
4ce45e02 | 1311 | if (BNX2_CHIP(bp) != BNX2_CHIP_5706) { |
59b47d8a | 1312 | val |= BNX2_EMAC_MODE_PORT_MII_10M; |
5b0c76ad MC |
1313 | break; |
1314 | } | |
1315 | /* fall through */ | |
1316 | case SPEED_100: | |
1317 | val |= BNX2_EMAC_MODE_PORT_MII; | |
1318 | break; | |
1319 | case SPEED_2500: | |
59b47d8a | 1320 | val |= BNX2_EMAC_MODE_25G_MODE; |
5b0c76ad MC |
1321 | /* fall through */ |
1322 | case SPEED_1000: | |
1323 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
1324 | break; | |
1325 | } | |
b6016b76 MC |
1326 | } |
1327 | else { | |
1328 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
1329 | } | |
1330 | ||
1331 | /* Set the MAC to operate in the appropriate duplex mode. */ | |
1332 | if (bp->duplex == DUPLEX_HALF) | |
1333 | val |= BNX2_EMAC_MODE_HALF_DUPLEX; | |
e503e066 | 1334 | BNX2_WR(bp, BNX2_EMAC_MODE, val); |
b6016b76 MC |
1335 | |
1336 | /* Enable/disable rx PAUSE. */ | |
1337 | bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; | |
1338 | ||
1339 | if (bp->flow_ctrl & FLOW_CTRL_RX) | |
1340 | bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; | |
e503e066 | 1341 | BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); |
b6016b76 MC |
1342 | |
1343 | /* Enable/disable tx PAUSE. */ | |
e503e066 | 1344 | val = BNX2_RD(bp, BNX2_EMAC_TX_MODE); |
b6016b76 MC |
1345 | val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; |
1346 | ||
1347 | if (bp->flow_ctrl & FLOW_CTRL_TX) | |
1348 | val |= BNX2_EMAC_TX_MODE_FLOW_EN; | |
e503e066 | 1349 | BNX2_WR(bp, BNX2_EMAC_TX_MODE, val); |
b6016b76 MC |
1350 | |
1351 | /* Acknowledge the interrupt. */ | |
e503e066 | 1352 | BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); |
b6016b76 | 1353 | |
22fa159d | 1354 | bnx2_init_all_rx_contexts(bp); |
b6016b76 MC |
1355 | } |
1356 | ||
27a005b8 MC |
1357 | static void |
1358 | bnx2_enable_bmsr1(struct bnx2 *bp) | |
1359 | { | |
583c28e5 | 1360 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
4ce45e02 | 1361 | (BNX2_CHIP(bp) == BNX2_CHIP_5709)) |
27a005b8 MC |
1362 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1363 | MII_BNX2_BLK_ADDR_GP_STATUS); | |
1364 | } | |
1365 | ||
1366 | static void | |
1367 | bnx2_disable_bmsr1(struct bnx2 *bp) | |
1368 | { | |
583c28e5 | 1369 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
4ce45e02 | 1370 | (BNX2_CHIP(bp) == BNX2_CHIP_5709)) |
27a005b8 MC |
1371 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1372 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1373 | } | |
1374 | ||
605a9e20 MC |
1375 | static int |
1376 | bnx2_test_and_enable_2g5(struct bnx2 *bp) | |
1377 | { | |
1378 | u32 up1; | |
1379 | int ret = 1; | |
1380 | ||
583c28e5 | 1381 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
605a9e20 MC |
1382 | return 0; |
1383 | ||
1384 | if (bp->autoneg & AUTONEG_SPEED) | |
1385 | bp->advertising |= ADVERTISED_2500baseX_Full; | |
1386 | ||
4ce45e02 | 1387 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
27a005b8 MC |
1388 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); |
1389 | ||
605a9e20 MC |
1390 | bnx2_read_phy(bp, bp->mii_up1, &up1); |
1391 | if (!(up1 & BCM5708S_UP1_2G5)) { | |
1392 | up1 |= BCM5708S_UP1_2G5; | |
1393 | bnx2_write_phy(bp, bp->mii_up1, up1); | |
1394 | ret = 0; | |
1395 | } | |
1396 | ||
4ce45e02 | 1397 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
27a005b8 MC |
1398 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1399 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1400 | ||
605a9e20 MC |
1401 | return ret; |
1402 | } | |
1403 | ||
1404 | static int | |
1405 | bnx2_test_and_disable_2g5(struct bnx2 *bp) | |
1406 | { | |
1407 | u32 up1; | |
1408 | int ret = 0; | |
1409 | ||
583c28e5 | 1410 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
605a9e20 MC |
1411 | return 0; |
1412 | ||
4ce45e02 | 1413 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
27a005b8 MC |
1414 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); |
1415 | ||
605a9e20 MC |
1416 | bnx2_read_phy(bp, bp->mii_up1, &up1); |
1417 | if (up1 & BCM5708S_UP1_2G5) { | |
1418 | up1 &= ~BCM5708S_UP1_2G5; | |
1419 | bnx2_write_phy(bp, bp->mii_up1, up1); | |
1420 | ret = 1; | |
1421 | } | |
1422 | ||
4ce45e02 | 1423 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
27a005b8 MC |
1424 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1425 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
1426 | ||
605a9e20 MC |
1427 | return ret; |
1428 | } | |
1429 | ||
1430 | static void | |
1431 | bnx2_enable_forced_2g5(struct bnx2 *bp) | |
1432 | { | |
cbd6890c MC |
1433 | u32 uninitialized_var(bmcr); |
1434 | int err; | |
605a9e20 | 1435 | |
583c28e5 | 1436 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
605a9e20 MC |
1437 | return; |
1438 | ||
4ce45e02 | 1439 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
27a005b8 MC |
1440 | u32 val; |
1441 | ||
1442 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1443 | MII_BNX2_BLK_ADDR_SERDES_DIG); | |
cbd6890c MC |
1444 | if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { |
1445 | val &= ~MII_BNX2_SD_MISC1_FORCE_MSK; | |
1446 | val |= MII_BNX2_SD_MISC1_FORCE | | |
1447 | MII_BNX2_SD_MISC1_FORCE_2_5G; | |
1448 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); | |
1449 | } | |
27a005b8 MC |
1450 | |
1451 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1452 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
cbd6890c | 1453 | err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
27a005b8 | 1454 | |
4ce45e02 | 1455 | } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { |
cbd6890c MC |
1456 | err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1457 | if (!err) | |
1458 | bmcr |= BCM5708S_BMCR_FORCE_2500; | |
c7079857 ED |
1459 | } else { |
1460 | return; | |
605a9e20 MC |
1461 | } |
1462 | ||
cbd6890c MC |
1463 | if (err) |
1464 | return; | |
1465 | ||
605a9e20 MC |
1466 | if (bp->autoneg & AUTONEG_SPEED) { |
1467 | bmcr &= ~BMCR_ANENABLE; | |
1468 | if (bp->req_duplex == DUPLEX_FULL) | |
1469 | bmcr |= BMCR_FULLDPLX; | |
1470 | } | |
1471 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | |
1472 | } | |
1473 | ||
1474 | static void | |
1475 | bnx2_disable_forced_2g5(struct bnx2 *bp) | |
1476 | { | |
cbd6890c MC |
1477 | u32 uninitialized_var(bmcr); |
1478 | int err; | |
605a9e20 | 1479 | |
583c28e5 | 1480 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
605a9e20 MC |
1481 | return; |
1482 | ||
4ce45e02 | 1483 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
27a005b8 MC |
1484 | u32 val; |
1485 | ||
1486 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1487 | MII_BNX2_BLK_ADDR_SERDES_DIG); | |
cbd6890c MC |
1488 | if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { |
1489 | val &= ~MII_BNX2_SD_MISC1_FORCE; | |
1490 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); | |
1491 | } | |
27a005b8 MC |
1492 | |
1493 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | |
1494 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
cbd6890c | 1495 | err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
27a005b8 | 1496 | |
4ce45e02 | 1497 | } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { |
cbd6890c MC |
1498 | err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1499 | if (!err) | |
1500 | bmcr &= ~BCM5708S_BMCR_FORCE_2500; | |
c7079857 ED |
1501 | } else { |
1502 | return; | |
605a9e20 MC |
1503 | } |
1504 | ||
cbd6890c MC |
1505 | if (err) |
1506 | return; | |
1507 | ||
605a9e20 MC |
1508 | if (bp->autoneg & AUTONEG_SPEED) |
1509 | bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART; | |
1510 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | |
1511 | } | |
1512 | ||
b2fadeae MC |
1513 | static void |
1514 | bnx2_5706s_force_link_dn(struct bnx2 *bp, int start) | |
1515 | { | |
1516 | u32 val; | |
1517 | ||
1518 | bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL); | |
1519 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); | |
1520 | if (start) | |
1521 | bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); | |
1522 | else | |
1523 | bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); | |
1524 | } | |
1525 | ||
b6016b76 MC |
1526 | static int |
1527 | bnx2_set_link(struct bnx2 *bp) | |
1528 | { | |
1529 | u32 bmsr; | |
1530 | u8 link_up; | |
1531 | ||
80be4434 | 1532 | if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) { |
b6016b76 MC |
1533 | bp->link_up = 1; |
1534 | return 0; | |
1535 | } | |
1536 | ||
583c28e5 | 1537 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
1538 | return 0; |
1539 | ||
b6016b76 MC |
1540 | link_up = bp->link_up; |
1541 | ||
27a005b8 MC |
1542 | bnx2_enable_bmsr1(bp); |
1543 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
1544 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
1545 | bnx2_disable_bmsr1(bp); | |
b6016b76 | 1546 | |
583c28e5 | 1547 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
4ce45e02 | 1548 | (BNX2_CHIP(bp) == BNX2_CHIP_5706)) { |
a2724e25 | 1549 | u32 val, an_dbg; |
b6016b76 | 1550 | |
583c28e5 | 1551 | if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { |
b2fadeae | 1552 | bnx2_5706s_force_link_dn(bp, 0); |
583c28e5 | 1553 | bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; |
b2fadeae | 1554 | } |
e503e066 | 1555 | val = BNX2_RD(bp, BNX2_EMAC_STATUS); |
a2724e25 MC |
1556 | |
1557 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); | |
1558 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | |
1559 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | |
1560 | ||
1561 | if ((val & BNX2_EMAC_STATUS_LINK) && | |
1562 | !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC)) | |
b6016b76 MC |
1563 | bmsr |= BMSR_LSTATUS; |
1564 | else | |
1565 | bmsr &= ~BMSR_LSTATUS; | |
1566 | } | |
1567 | ||
1568 | if (bmsr & BMSR_LSTATUS) { | |
1569 | bp->link_up = 1; | |
1570 | ||
583c28e5 | 1571 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
4ce45e02 | 1572 | if (BNX2_CHIP(bp) == BNX2_CHIP_5706) |
5b0c76ad | 1573 | bnx2_5706s_linkup(bp); |
4ce45e02 | 1574 | else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) |
5b0c76ad | 1575 | bnx2_5708s_linkup(bp); |
4ce45e02 | 1576 | else if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
27a005b8 | 1577 | bnx2_5709s_linkup(bp); |
b6016b76 MC |
1578 | } |
1579 | else { | |
1580 | bnx2_copper_linkup(bp); | |
1581 | } | |
1582 | bnx2_resolve_flow_ctrl(bp); | |
1583 | } | |
1584 | else { | |
583c28e5 | 1585 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
605a9e20 MC |
1586 | (bp->autoneg & AUTONEG_SPEED)) |
1587 | bnx2_disable_forced_2g5(bp); | |
b6016b76 | 1588 | |
583c28e5 | 1589 | if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) { |
b2fadeae MC |
1590 | u32 bmcr; |
1591 | ||
1592 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | |
1593 | bmcr |= BMCR_ANENABLE; | |
1594 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | |
1595 | ||
583c28e5 | 1596 | bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; |
b2fadeae | 1597 | } |
b6016b76 MC |
1598 | bp->link_up = 0; |
1599 | } | |
1600 | ||
1601 | if (bp->link_up != link_up) { | |
1602 | bnx2_report_link(bp); | |
1603 | } | |
1604 | ||
1605 | bnx2_set_mac_link(bp); | |
1606 | ||
1607 | return 0; | |
1608 | } | |
1609 | ||
1610 | static int | |
1611 | bnx2_reset_phy(struct bnx2 *bp) | |
1612 | { | |
1613 | int i; | |
1614 | u32 reg; | |
1615 | ||
ca58c3af | 1616 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); |
b6016b76 MC |
1617 | |
1618 | #define PHY_RESET_MAX_WAIT 100 | |
1619 | for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { | |
1620 | udelay(10); | |
1621 | ||
ca58c3af | 1622 | bnx2_read_phy(bp, bp->mii_bmcr, ®); |
b6016b76 MC |
1623 | if (!(reg & BMCR_RESET)) { |
1624 | udelay(20); | |
1625 | break; | |
1626 | } | |
1627 | } | |
1628 | if (i == PHY_RESET_MAX_WAIT) { | |
1629 | return -EBUSY; | |
1630 | } | |
1631 | return 0; | |
1632 | } | |
1633 | ||
1634 | static u32 | |
1635 | bnx2_phy_get_pause_adv(struct bnx2 *bp) | |
1636 | { | |
1637 | u32 adv = 0; | |
1638 | ||
1639 | if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == | |
1640 | (FLOW_CTRL_RX | FLOW_CTRL_TX)) { | |
1641 | ||
583c28e5 | 1642 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
b6016b76 MC |
1643 | adv = ADVERTISE_1000XPAUSE; |
1644 | } | |
1645 | else { | |
1646 | adv = ADVERTISE_PAUSE_CAP; | |
1647 | } | |
1648 | } | |
1649 | else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { | |
583c28e5 | 1650 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
b6016b76 MC |
1651 | adv = ADVERTISE_1000XPSE_ASYM; |
1652 | } | |
1653 | else { | |
1654 | adv = ADVERTISE_PAUSE_ASYM; | |
1655 | } | |
1656 | } | |
1657 | else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { | |
583c28e5 | 1658 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
b6016b76 MC |
1659 | adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1660 | } | |
1661 | else { | |
1662 | adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
1663 | } | |
1664 | } | |
1665 | return adv; | |
1666 | } | |
1667 | ||
a2f13890 | 1668 | static int bnx2_fw_sync(struct bnx2 *, u32, int, int); |
0d8a6571 | 1669 | |
b6016b76 | 1670 | static int |
0d8a6571 | 1671 | bnx2_setup_remote_phy(struct bnx2 *bp, u8 port) |
52d07b1f HH |
1672 | __releases(&bp->phy_lock) |
1673 | __acquires(&bp->phy_lock) | |
0d8a6571 MC |
1674 | { |
1675 | u32 speed_arg = 0, pause_adv; | |
1676 | ||
1677 | pause_adv = bnx2_phy_get_pause_adv(bp); | |
1678 | ||
1679 | if (bp->autoneg & AUTONEG_SPEED) { | |
1680 | speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG; | |
1681 | if (bp->advertising & ADVERTISED_10baseT_Half) | |
1682 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF; | |
1683 | if (bp->advertising & ADVERTISED_10baseT_Full) | |
1684 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL; | |
1685 | if (bp->advertising & ADVERTISED_100baseT_Half) | |
1686 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF; | |
1687 | if (bp->advertising & ADVERTISED_100baseT_Full) | |
1688 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL; | |
1689 | if (bp->advertising & ADVERTISED_1000baseT_Full) | |
1690 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL; | |
1691 | if (bp->advertising & ADVERTISED_2500baseX_Full) | |
1692 | speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; | |
1693 | } else { | |
1694 | if (bp->req_line_speed == SPEED_2500) | |
1695 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; | |
1696 | else if (bp->req_line_speed == SPEED_1000) | |
1697 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL; | |
1698 | else if (bp->req_line_speed == SPEED_100) { | |
1699 | if (bp->req_duplex == DUPLEX_FULL) | |
1700 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL; | |
1701 | else | |
1702 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF; | |
1703 | } else if (bp->req_line_speed == SPEED_10) { | |
1704 | if (bp->req_duplex == DUPLEX_FULL) | |
1705 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL; | |
1706 | else | |
1707 | speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF; | |
1708 | } | |
1709 | } | |
1710 | ||
1711 | if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP)) | |
1712 | speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE; | |
c26736ec | 1713 | if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM)) |
0d8a6571 MC |
1714 | speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE; |
1715 | ||
1716 | if (port == PORT_TP) | |
1717 | speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE | | |
1718 | BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED; | |
1719 | ||
2726d6e1 | 1720 | bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg); |
0d8a6571 MC |
1721 | |
1722 | spin_unlock_bh(&bp->phy_lock); | |
a2f13890 | 1723 | bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0); |
0d8a6571 MC |
1724 | spin_lock_bh(&bp->phy_lock); |
1725 | ||
1726 | return 0; | |
1727 | } | |
1728 | ||
1729 | static int | |
1730 | bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port) | |
52d07b1f HH |
1731 | __releases(&bp->phy_lock) |
1732 | __acquires(&bp->phy_lock) | |
b6016b76 | 1733 | { |
605a9e20 | 1734 | u32 adv, bmcr; |
b6016b76 MC |
1735 | u32 new_adv = 0; |
1736 | ||
583c28e5 | 1737 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
807540ba | 1738 | return bnx2_setup_remote_phy(bp, port); |
0d8a6571 | 1739 | |
b6016b76 MC |
1740 | if (!(bp->autoneg & AUTONEG_SPEED)) { |
1741 | u32 new_bmcr; | |
5b0c76ad MC |
1742 | int force_link_down = 0; |
1743 | ||
605a9e20 MC |
1744 | if (bp->req_line_speed == SPEED_2500) { |
1745 | if (!bnx2_test_and_enable_2g5(bp)) | |
1746 | force_link_down = 1; | |
1747 | } else if (bp->req_line_speed == SPEED_1000) { | |
1748 | if (bnx2_test_and_disable_2g5(bp)) | |
1749 | force_link_down = 1; | |
1750 | } | |
ca58c3af | 1751 | bnx2_read_phy(bp, bp->mii_adv, &adv); |
80be4434 MC |
1752 | adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); |
1753 | ||
ca58c3af | 1754 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
605a9e20 | 1755 | new_bmcr = bmcr & ~BMCR_ANENABLE; |
80be4434 | 1756 | new_bmcr |= BMCR_SPEED1000; |
605a9e20 | 1757 | |
4ce45e02 | 1758 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
27a005b8 MC |
1759 | if (bp->req_line_speed == SPEED_2500) |
1760 | bnx2_enable_forced_2g5(bp); | |
1761 | else if (bp->req_line_speed == SPEED_1000) { | |
1762 | bnx2_disable_forced_2g5(bp); | |
1763 | new_bmcr &= ~0x2000; | |
1764 | } | |
1765 | ||
4ce45e02 | 1766 | } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { |
605a9e20 MC |
1767 | if (bp->req_line_speed == SPEED_2500) |
1768 | new_bmcr |= BCM5708S_BMCR_FORCE_2500; | |
1769 | else | |
1770 | new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500; | |
5b0c76ad MC |
1771 | } |
1772 | ||
b6016b76 | 1773 | if (bp->req_duplex == DUPLEX_FULL) { |
5b0c76ad | 1774 | adv |= ADVERTISE_1000XFULL; |
b6016b76 MC |
1775 | new_bmcr |= BMCR_FULLDPLX; |
1776 | } | |
1777 | else { | |
5b0c76ad | 1778 | adv |= ADVERTISE_1000XHALF; |
b6016b76 MC |
1779 | new_bmcr &= ~BMCR_FULLDPLX; |
1780 | } | |
5b0c76ad | 1781 | if ((new_bmcr != bmcr) || (force_link_down)) { |
b6016b76 MC |
1782 | /* Force a link down visible on the other side */ |
1783 | if (bp->link_up) { | |
ca58c3af | 1784 | bnx2_write_phy(bp, bp->mii_adv, adv & |
5b0c76ad MC |
1785 | ~(ADVERTISE_1000XFULL | |
1786 | ADVERTISE_1000XHALF)); | |
ca58c3af | 1787 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr | |
b6016b76 MC |
1788 | BMCR_ANRESTART | BMCR_ANENABLE); |
1789 | ||
1790 | bp->link_up = 0; | |
1791 | netif_carrier_off(bp->dev); | |
ca58c3af | 1792 | bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); |
80be4434 | 1793 | bnx2_report_link(bp); |
b6016b76 | 1794 | } |
ca58c3af MC |
1795 | bnx2_write_phy(bp, bp->mii_adv, adv); |
1796 | bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); | |
605a9e20 MC |
1797 | } else { |
1798 | bnx2_resolve_flow_ctrl(bp); | |
1799 | bnx2_set_mac_link(bp); | |
b6016b76 MC |
1800 | } |
1801 | return 0; | |
1802 | } | |
1803 | ||
605a9e20 | 1804 | bnx2_test_and_enable_2g5(bp); |
5b0c76ad | 1805 | |
b6016b76 MC |
1806 | if (bp->advertising & ADVERTISED_1000baseT_Full) |
1807 | new_adv |= ADVERTISE_1000XFULL; | |
1808 | ||
1809 | new_adv |= bnx2_phy_get_pause_adv(bp); | |
1810 | ||
ca58c3af MC |
1811 | bnx2_read_phy(bp, bp->mii_adv, &adv); |
1812 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | |
b6016b76 MC |
1813 | |
1814 | bp->serdes_an_pending = 0; | |
1815 | if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { | |
1816 | /* Force a link down visible on the other side */ | |
1817 | if (bp->link_up) { | |
ca58c3af | 1818 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
80be4434 MC |
1819 | spin_unlock_bh(&bp->phy_lock); |
1820 | msleep(20); | |
1821 | spin_lock_bh(&bp->phy_lock); | |
b6016b76 MC |
1822 | } |
1823 | ||
ca58c3af MC |
1824 | bnx2_write_phy(bp, bp->mii_adv, new_adv); |
1825 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | | |
b6016b76 | 1826 | BMCR_ANENABLE); |
f8dd064e MC |
1827 | /* Speed up link-up time when the link partner |
1828 | * does not autonegotiate which is very common | |
1829 | * in blade servers. Some blade servers use | |
1830 | * IPMI for kerboard input and it's important | |
1831 | * to minimize link disruptions. Autoneg. involves | |
1832 | * exchanging base pages plus 3 next pages and | |
1833 | * normally completes in about 120 msec. | |
1834 | */ | |
40105c0b | 1835 | bp->current_interval = BNX2_SERDES_AN_TIMEOUT; |
f8dd064e MC |
1836 | bp->serdes_an_pending = 1; |
1837 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
605a9e20 MC |
1838 | } else { |
1839 | bnx2_resolve_flow_ctrl(bp); | |
1840 | bnx2_set_mac_link(bp); | |
b6016b76 MC |
1841 | } |
1842 | ||
1843 | return 0; | |
1844 | } | |
1845 | ||
1846 | #define ETHTOOL_ALL_FIBRE_SPEED \ | |
583c28e5 | 1847 | (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \ |
deaf391b MC |
1848 | (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\ |
1849 | (ADVERTISED_1000baseT_Full) | |
b6016b76 MC |
1850 | |
1851 | #define ETHTOOL_ALL_COPPER_SPEED \ | |
1852 | (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ | |
1853 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ | |
1854 | ADVERTISED_1000baseT_Full) | |
1855 | ||
1856 | #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ | |
1857 | ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) | |
6aa20a22 | 1858 | |
b6016b76 MC |
1859 | #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) |
1860 | ||
0d8a6571 MC |
1861 | static void |
1862 | bnx2_set_default_remote_link(struct bnx2 *bp) | |
1863 | { | |
1864 | u32 link; | |
1865 | ||
1866 | if (bp->phy_port == PORT_TP) | |
2726d6e1 | 1867 | link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK); |
0d8a6571 | 1868 | else |
2726d6e1 | 1869 | link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK); |
0d8a6571 MC |
1870 | |
1871 | if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) { | |
1872 | bp->req_line_speed = 0; | |
1873 | bp->autoneg |= AUTONEG_SPEED; | |
1874 | bp->advertising = ADVERTISED_Autoneg; | |
1875 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) | |
1876 | bp->advertising |= ADVERTISED_10baseT_Half; | |
1877 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL) | |
1878 | bp->advertising |= ADVERTISED_10baseT_Full; | |
1879 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) | |
1880 | bp->advertising |= ADVERTISED_100baseT_Half; | |
1881 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL) | |
1882 | bp->advertising |= ADVERTISED_100baseT_Full; | |
1883 | if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) | |
1884 | bp->advertising |= ADVERTISED_1000baseT_Full; | |
1885 | if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) | |
1886 | bp->advertising |= ADVERTISED_2500baseX_Full; | |
1887 | } else { | |
1888 | bp->autoneg = 0; | |
1889 | bp->advertising = 0; | |
1890 | bp->req_duplex = DUPLEX_FULL; | |
1891 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10) { | |
1892 | bp->req_line_speed = SPEED_10; | |
1893 | if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) | |
1894 | bp->req_duplex = DUPLEX_HALF; | |
1895 | } | |
1896 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100) { | |
1897 | bp->req_line_speed = SPEED_100; | |
1898 | if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) | |
1899 | bp->req_duplex = DUPLEX_HALF; | |
1900 | } | |
1901 | if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) | |
1902 | bp->req_line_speed = SPEED_1000; | |
1903 | if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) | |
1904 | bp->req_line_speed = SPEED_2500; | |
1905 | } | |
1906 | } | |
1907 | ||
deaf391b MC |
1908 | static void |
1909 | bnx2_set_default_link(struct bnx2 *bp) | |
1910 | { | |
ab59859d HH |
1911 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
1912 | bnx2_set_default_remote_link(bp); | |
1913 | return; | |
1914 | } | |
0d8a6571 | 1915 | |
deaf391b MC |
1916 | bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; |
1917 | bp->req_line_speed = 0; | |
583c28e5 | 1918 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
deaf391b MC |
1919 | u32 reg; |
1920 | ||
1921 | bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; | |
1922 | ||
2726d6e1 | 1923 | reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG); |
deaf391b MC |
1924 | reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; |
1925 | if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { | |
1926 | bp->autoneg = 0; | |
1927 | bp->req_line_speed = bp->line_speed = SPEED_1000; | |
1928 | bp->req_duplex = DUPLEX_FULL; | |
1929 | } | |
1930 | } else | |
1931 | bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; | |
1932 | } | |
1933 | ||
df149d70 MC |
1934 | static void |
1935 | bnx2_send_heart_beat(struct bnx2 *bp) | |
1936 | { | |
1937 | u32 msg; | |
1938 | u32 addr; | |
1939 | ||
1940 | spin_lock(&bp->indirect_lock); | |
1941 | msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK); | |
1942 | addr = bp->shmem_base + BNX2_DRV_PULSE_MB; | |
e503e066 MC |
1943 | BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr); |
1944 | BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg); | |
df149d70 MC |
1945 | spin_unlock(&bp->indirect_lock); |
1946 | } | |
1947 | ||
0d8a6571 MC |
1948 | static void |
1949 | bnx2_remote_phy_event(struct bnx2 *bp) | |
1950 | { | |
1951 | u32 msg; | |
1952 | u8 link_up = bp->link_up; | |
1953 | u8 old_port; | |
1954 | ||
2726d6e1 | 1955 | msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); |
0d8a6571 | 1956 | |
df149d70 MC |
1957 | if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED) |
1958 | bnx2_send_heart_beat(bp); | |
1959 | ||
1960 | msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED; | |
1961 | ||
0d8a6571 MC |
1962 | if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN) |
1963 | bp->link_up = 0; | |
1964 | else { | |
1965 | u32 speed; | |
1966 | ||
1967 | bp->link_up = 1; | |
1968 | speed = msg & BNX2_LINK_STATUS_SPEED_MASK; | |
1969 | bp->duplex = DUPLEX_FULL; | |
1970 | switch (speed) { | |
1971 | case BNX2_LINK_STATUS_10HALF: | |
1972 | bp->duplex = DUPLEX_HALF; | |
7947c9ce | 1973 | /* fall through */ |
0d8a6571 MC |
1974 | case BNX2_LINK_STATUS_10FULL: |
1975 | bp->line_speed = SPEED_10; | |
1976 | break; | |
1977 | case BNX2_LINK_STATUS_100HALF: | |
1978 | bp->duplex = DUPLEX_HALF; | |
7947c9ce | 1979 | /* fall through */ |
0d8a6571 MC |
1980 | case BNX2_LINK_STATUS_100BASE_T4: |
1981 | case BNX2_LINK_STATUS_100FULL: | |
1982 | bp->line_speed = SPEED_100; | |
1983 | break; | |
1984 | case BNX2_LINK_STATUS_1000HALF: | |
1985 | bp->duplex = DUPLEX_HALF; | |
7947c9ce | 1986 | /* fall through */ |
0d8a6571 MC |
1987 | case BNX2_LINK_STATUS_1000FULL: |
1988 | bp->line_speed = SPEED_1000; | |
1989 | break; | |
1990 | case BNX2_LINK_STATUS_2500HALF: | |
1991 | bp->duplex = DUPLEX_HALF; | |
7947c9ce | 1992 | /* fall through */ |
0d8a6571 MC |
1993 | case BNX2_LINK_STATUS_2500FULL: |
1994 | bp->line_speed = SPEED_2500; | |
1995 | break; | |
1996 | default: | |
1997 | bp->line_speed = 0; | |
1998 | break; | |
1999 | } | |
2000 | ||
0d8a6571 MC |
2001 | bp->flow_ctrl = 0; |
2002 | if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != | |
2003 | (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { | |
2004 | if (bp->duplex == DUPLEX_FULL) | |
2005 | bp->flow_ctrl = bp->req_flow_ctrl; | |
2006 | } else { | |
2007 | if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED) | |
2008 | bp->flow_ctrl |= FLOW_CTRL_TX; | |
2009 | if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED) | |
2010 | bp->flow_ctrl |= FLOW_CTRL_RX; | |
2011 | } | |
2012 | ||
2013 | old_port = bp->phy_port; | |
2014 | if (msg & BNX2_LINK_STATUS_SERDES_LINK) | |
2015 | bp->phy_port = PORT_FIBRE; | |
2016 | else | |
2017 | bp->phy_port = PORT_TP; | |
2018 | ||
2019 | if (old_port != bp->phy_port) | |
2020 | bnx2_set_default_link(bp); | |
2021 | ||
0d8a6571 MC |
2022 | } |
2023 | if (bp->link_up != link_up) | |
2024 | bnx2_report_link(bp); | |
2025 | ||
2026 | bnx2_set_mac_link(bp); | |
2027 | } | |
2028 | ||
2029 | static int | |
2030 | bnx2_set_remote_link(struct bnx2 *bp) | |
2031 | { | |
2032 | u32 evt_code; | |
2033 | ||
2726d6e1 | 2034 | evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB); |
0d8a6571 MC |
2035 | switch (evt_code) { |
2036 | case BNX2_FW_EVT_CODE_LINK_EVENT: | |
2037 | bnx2_remote_phy_event(bp); | |
2038 | break; | |
2039 | case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT: | |
2040 | default: | |
df149d70 | 2041 | bnx2_send_heart_beat(bp); |
0d8a6571 MC |
2042 | break; |
2043 | } | |
2044 | return 0; | |
2045 | } | |
2046 | ||
b6016b76 MC |
2047 | static int |
2048 | bnx2_setup_copper_phy(struct bnx2 *bp) | |
52d07b1f HH |
2049 | __releases(&bp->phy_lock) |
2050 | __acquires(&bp->phy_lock) | |
b6016b76 MC |
2051 | { |
2052 | u32 bmcr; | |
2053 | u32 new_bmcr; | |
2054 | ||
ca58c3af | 2055 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 MC |
2056 | |
2057 | if (bp->autoneg & AUTONEG_SPEED) { | |
2058 | u32 adv_reg, adv1000_reg; | |
37f07023 MC |
2059 | u32 new_adv = 0; |
2060 | u32 new_adv1000 = 0; | |
b6016b76 | 2061 | |
ca58c3af | 2062 | bnx2_read_phy(bp, bp->mii_adv, &adv_reg); |
b6016b76 MC |
2063 | adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP | |
2064 | ADVERTISE_PAUSE_ASYM); | |
2065 | ||
2066 | bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg); | |
2067 | adv1000_reg &= PHY_ALL_1000_SPEED; | |
2068 | ||
37f07023 MC |
2069 | new_adv = ethtool_adv_to_mii_adv_t(bp->advertising); |
2070 | new_adv |= ADVERTISE_CSMA; | |
2071 | new_adv |= bnx2_phy_get_pause_adv(bp); | |
b6016b76 | 2072 | |
37f07023 | 2073 | new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising); |
28011cf1 | 2074 | |
37f07023 MC |
2075 | if ((adv1000_reg != new_adv1000) || |
2076 | (adv_reg != new_adv) || | |
b6016b76 MC |
2077 | ((bmcr & BMCR_ANENABLE) == 0)) { |
2078 | ||
37f07023 MC |
2079 | bnx2_write_phy(bp, bp->mii_adv, new_adv); |
2080 | bnx2_write_phy(bp, MII_CTRL1000, new_adv1000); | |
ca58c3af | 2081 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | |
b6016b76 MC |
2082 | BMCR_ANENABLE); |
2083 | } | |
2084 | else if (bp->link_up) { | |
2085 | /* Flow ctrl may have changed from auto to forced */ | |
2086 | /* or vice-versa. */ | |
2087 | ||
2088 | bnx2_resolve_flow_ctrl(bp); | |
2089 | bnx2_set_mac_link(bp); | |
2090 | } | |
2091 | return 0; | |
2092 | } | |
2093 | ||
2094 | new_bmcr = 0; | |
2095 | if (bp->req_line_speed == SPEED_100) { | |
2096 | new_bmcr |= BMCR_SPEED100; | |
2097 | } | |
2098 | if (bp->req_duplex == DUPLEX_FULL) { | |
2099 | new_bmcr |= BMCR_FULLDPLX; | |
2100 | } | |
2101 | if (new_bmcr != bmcr) { | |
2102 | u32 bmsr; | |
b6016b76 | 2103 | |
ca58c3af MC |
2104 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
2105 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | |
6aa20a22 | 2106 | |
b6016b76 MC |
2107 | if (bmsr & BMSR_LSTATUS) { |
2108 | /* Force link down */ | |
ca58c3af | 2109 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
a16dda0e MC |
2110 | spin_unlock_bh(&bp->phy_lock); |
2111 | msleep(50); | |
2112 | spin_lock_bh(&bp->phy_lock); | |
2113 | ||
ca58c3af MC |
2114 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
2115 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | |
b6016b76 MC |
2116 | } |
2117 | ||
ca58c3af | 2118 | bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); |
b6016b76 MC |
2119 | |
2120 | /* Normally, the new speed is setup after the link has | |
2121 | * gone down and up again. In some cases, link will not go | |
2122 | * down so we need to set up the new speed here. | |
2123 | */ | |
2124 | if (bmsr & BMSR_LSTATUS) { | |
2125 | bp->line_speed = bp->req_line_speed; | |
2126 | bp->duplex = bp->req_duplex; | |
2127 | bnx2_resolve_flow_ctrl(bp); | |
2128 | bnx2_set_mac_link(bp); | |
2129 | } | |
27a005b8 MC |
2130 | } else { |
2131 | bnx2_resolve_flow_ctrl(bp); | |
2132 | bnx2_set_mac_link(bp); | |
b6016b76 MC |
2133 | } |
2134 | return 0; | |
2135 | } | |
2136 | ||
2137 | static int | |
0d8a6571 | 2138 | bnx2_setup_phy(struct bnx2 *bp, u8 port) |
52d07b1f HH |
2139 | __releases(&bp->phy_lock) |
2140 | __acquires(&bp->phy_lock) | |
b6016b76 MC |
2141 | { |
2142 | if (bp->loopback == MAC_LOOPBACK) | |
2143 | return 0; | |
2144 | ||
583c28e5 | 2145 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
807540ba | 2146 | return bnx2_setup_serdes_phy(bp, port); |
b6016b76 MC |
2147 | } |
2148 | else { | |
807540ba | 2149 | return bnx2_setup_copper_phy(bp); |
b6016b76 MC |
2150 | } |
2151 | } | |
2152 | ||
27a005b8 | 2153 | static int |
9a120bc5 | 2154 | bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy) |
27a005b8 MC |
2155 | { |
2156 | u32 val; | |
2157 | ||
2158 | bp->mii_bmcr = MII_BMCR + 0x10; | |
2159 | bp->mii_bmsr = MII_BMSR + 0x10; | |
2160 | bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1; | |
2161 | bp->mii_adv = MII_ADVERTISE + 0x10; | |
2162 | bp->mii_lpa = MII_LPA + 0x10; | |
2163 | bp->mii_up1 = MII_BNX2_OVER1G_UP1; | |
2164 | ||
2165 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER); | |
2166 | bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); | |
2167 | ||
2168 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
9a120bc5 MC |
2169 | if (reset_phy) |
2170 | bnx2_reset_phy(bp); | |
27a005b8 MC |
2171 | |
2172 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); | |
2173 | ||
2174 | bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val); | |
2175 | val &= ~MII_BNX2_SD_1000XCTL1_AUTODET; | |
2176 | val |= MII_BNX2_SD_1000XCTL1_FIBER; | |
2177 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); | |
2178 | ||
2179 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); | |
2180 | bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val); | |
583c28e5 | 2181 | if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) |
27a005b8 MC |
2182 | val |= BCM5708S_UP1_2G5; |
2183 | else | |
2184 | val &= ~BCM5708S_UP1_2G5; | |
2185 | bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); | |
2186 | ||
2187 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG); | |
2188 | bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val); | |
2189 | val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM; | |
2190 | bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); | |
2191 | ||
2192 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0); | |
2193 | ||
2194 | val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN | | |
2195 | MII_BNX2_CL73_BAM_NP_AFT_BP_EN; | |
2196 | bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); | |
2197 | ||
2198 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | |
2199 | ||
2200 | return 0; | |
2201 | } | |
2202 | ||
b6016b76 | 2203 | static int |
9a120bc5 | 2204 | bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy) |
5b0c76ad MC |
2205 | { |
2206 | u32 val; | |
2207 | ||
9a120bc5 MC |
2208 | if (reset_phy) |
2209 | bnx2_reset_phy(bp); | |
27a005b8 MC |
2210 | |
2211 | bp->mii_up1 = BCM5708S_UP1; | |
2212 | ||
5b0c76ad MC |
2213 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); |
2214 | bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); | |
2215 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); | |
2216 | ||
2217 | bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val); | |
2218 | val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN; | |
2219 | bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); | |
2220 | ||
2221 | bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val); | |
2222 | val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN; | |
2223 | bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); | |
2224 | ||
583c28e5 | 2225 | if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) { |
5b0c76ad MC |
2226 | bnx2_read_phy(bp, BCM5708S_UP1, &val); |
2227 | val |= BCM5708S_UP1_2G5; | |
2228 | bnx2_write_phy(bp, BCM5708S_UP1, val); | |
2229 | } | |
2230 | ||
4ce45e02 MC |
2231 | if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) || |
2232 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) || | |
2233 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) { | |
5b0c76ad MC |
2234 | /* increase tx signal amplitude */ |
2235 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | |
2236 | BCM5708S_BLK_ADDR_TX_MISC); | |
2237 | bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val); | |
2238 | val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM; | |
2239 | bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); | |
2240 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); | |
2241 | } | |
2242 | ||
2726d6e1 | 2243 | val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) & |
5b0c76ad MC |
2244 | BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK; |
2245 | ||
2246 | if (val) { | |
2247 | u32 is_backplane; | |
2248 | ||
2726d6e1 | 2249 | is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); |
5b0c76ad MC |
2250 | if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) { |
2251 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | |
2252 | BCM5708S_BLK_ADDR_TX_MISC); | |
2253 | bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); | |
2254 | bnx2_write_phy(bp, BCM5708S_BLK_ADDR, | |
2255 | BCM5708S_BLK_ADDR_DIG); | |
2256 | } | |
2257 | } | |
2258 | return 0; | |
2259 | } | |
2260 | ||
2261 | static int | |
9a120bc5 | 2262 | bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy) |
b6016b76 | 2263 | { |
9a120bc5 MC |
2264 | if (reset_phy) |
2265 | bnx2_reset_phy(bp); | |
27a005b8 | 2266 | |
583c28e5 | 2267 | bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; |
b6016b76 | 2268 | |
4ce45e02 | 2269 | if (BNX2_CHIP(bp) == BNX2_CHIP_5706) |
e503e066 | 2270 | BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); |
b6016b76 MC |
2271 | |
2272 | if (bp->dev->mtu > 1500) { | |
2273 | u32 val; | |
2274 | ||
2275 | /* Set extended packet length bit */ | |
2276 | bnx2_write_phy(bp, 0x18, 0x7); | |
2277 | bnx2_read_phy(bp, 0x18, &val); | |
2278 | bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); | |
2279 | ||
2280 | bnx2_write_phy(bp, 0x1c, 0x6c00); | |
2281 | bnx2_read_phy(bp, 0x1c, &val); | |
2282 | bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); | |
2283 | } | |
2284 | else { | |
2285 | u32 val; | |
2286 | ||
2287 | bnx2_write_phy(bp, 0x18, 0x7); | |
2288 | bnx2_read_phy(bp, 0x18, &val); | |
2289 | bnx2_write_phy(bp, 0x18, val & ~0x4007); | |
2290 | ||
2291 | bnx2_write_phy(bp, 0x1c, 0x6c00); | |
2292 | bnx2_read_phy(bp, 0x1c, &val); | |
2293 | bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); | |
2294 | } | |
2295 | ||
2296 | return 0; | |
2297 | } | |
2298 | ||
2299 | static int | |
9a120bc5 | 2300 | bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy) |
b6016b76 | 2301 | { |
5b0c76ad MC |
2302 | u32 val; |
2303 | ||
9a120bc5 MC |
2304 | if (reset_phy) |
2305 | bnx2_reset_phy(bp); | |
27a005b8 | 2306 | |
583c28e5 | 2307 | if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) { |
b6016b76 MC |
2308 | bnx2_write_phy(bp, 0x18, 0x0c00); |
2309 | bnx2_write_phy(bp, 0x17, 0x000a); | |
2310 | bnx2_write_phy(bp, 0x15, 0x310b); | |
2311 | bnx2_write_phy(bp, 0x17, 0x201f); | |
2312 | bnx2_write_phy(bp, 0x15, 0x9506); | |
2313 | bnx2_write_phy(bp, 0x17, 0x401f); | |
2314 | bnx2_write_phy(bp, 0x15, 0x14e2); | |
2315 | bnx2_write_phy(bp, 0x18, 0x0400); | |
2316 | } | |
2317 | ||
583c28e5 | 2318 | if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) { |
b659f44e MC |
2319 | bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, |
2320 | MII_BNX2_DSP_EXPAND_REG | 0x8); | |
2321 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); | |
2322 | val &= ~(1 << 8); | |
2323 | bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); | |
2324 | } | |
2325 | ||
b6016b76 | 2326 | if (bp->dev->mtu > 1500) { |
b6016b76 MC |
2327 | /* Set extended packet length bit */ |
2328 | bnx2_write_phy(bp, 0x18, 0x7); | |
2329 | bnx2_read_phy(bp, 0x18, &val); | |
2330 | bnx2_write_phy(bp, 0x18, val | 0x4000); | |
2331 | ||
2332 | bnx2_read_phy(bp, 0x10, &val); | |
2333 | bnx2_write_phy(bp, 0x10, val | 0x1); | |
2334 | } | |
2335 | else { | |
b6016b76 MC |
2336 | bnx2_write_phy(bp, 0x18, 0x7); |
2337 | bnx2_read_phy(bp, 0x18, &val); | |
2338 | bnx2_write_phy(bp, 0x18, val & ~0x4007); | |
2339 | ||
2340 | bnx2_read_phy(bp, 0x10, &val); | |
2341 | bnx2_write_phy(bp, 0x10, val & ~0x1); | |
2342 | } | |
2343 | ||
5b0c76ad MC |
2344 | /* ethernet@wirespeed */ |
2345 | bnx2_write_phy(bp, 0x18, 0x7007); | |
2346 | bnx2_read_phy(bp, 0x18, &val); | |
2347 | bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4)); | |
b6016b76 MC |
2348 | return 0; |
2349 | } | |
2350 | ||
2351 | ||
2352 | static int | |
9a120bc5 | 2353 | bnx2_init_phy(struct bnx2 *bp, int reset_phy) |
52d07b1f HH |
2354 | __releases(&bp->phy_lock) |
2355 | __acquires(&bp->phy_lock) | |
b6016b76 MC |
2356 | { |
2357 | u32 val; | |
2358 | int rc = 0; | |
2359 | ||
583c28e5 MC |
2360 | bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK; |
2361 | bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY; | |
b6016b76 | 2362 | |
ca58c3af MC |
2363 | bp->mii_bmcr = MII_BMCR; |
2364 | bp->mii_bmsr = MII_BMSR; | |
27a005b8 | 2365 | bp->mii_bmsr1 = MII_BMSR; |
ca58c3af MC |
2366 | bp->mii_adv = MII_ADVERTISE; |
2367 | bp->mii_lpa = MII_LPA; | |
2368 | ||
e503e066 | 2369 | BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); |
b6016b76 | 2370 | |
583c28e5 | 2371 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
2372 | goto setup_phy; |
2373 | ||
b6016b76 MC |
2374 | bnx2_read_phy(bp, MII_PHYSID1, &val); |
2375 | bp->phy_id = val << 16; | |
2376 | bnx2_read_phy(bp, MII_PHYSID2, &val); | |
2377 | bp->phy_id |= val & 0xffff; | |
2378 | ||
583c28e5 | 2379 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
4ce45e02 | 2380 | if (BNX2_CHIP(bp) == BNX2_CHIP_5706) |
9a120bc5 | 2381 | rc = bnx2_init_5706s_phy(bp, reset_phy); |
4ce45e02 | 2382 | else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) |
9a120bc5 | 2383 | rc = bnx2_init_5708s_phy(bp, reset_phy); |
4ce45e02 | 2384 | else if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
9a120bc5 | 2385 | rc = bnx2_init_5709s_phy(bp, reset_phy); |
b6016b76 MC |
2386 | } |
2387 | else { | |
9a120bc5 | 2388 | rc = bnx2_init_copper_phy(bp, reset_phy); |
b6016b76 MC |
2389 | } |
2390 | ||
0d8a6571 MC |
2391 | setup_phy: |
2392 | if (!rc) | |
2393 | rc = bnx2_setup_phy(bp, bp->phy_port); | |
b6016b76 MC |
2394 | |
2395 | return rc; | |
2396 | } | |
2397 | ||
2398 | static int | |
2399 | bnx2_set_mac_loopback(struct bnx2 *bp) | |
2400 | { | |
2401 | u32 mac_mode; | |
2402 | ||
e503e066 | 2403 | mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE); |
b6016b76 MC |
2404 | mac_mode &= ~BNX2_EMAC_MODE_PORT; |
2405 | mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK; | |
e503e066 | 2406 | BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode); |
b6016b76 MC |
2407 | bp->link_up = 1; |
2408 | return 0; | |
2409 | } | |
2410 | ||
bc5a0690 MC |
2411 | static int bnx2_test_link(struct bnx2 *); |
2412 | ||
2413 | static int | |
2414 | bnx2_set_phy_loopback(struct bnx2 *bp) | |
2415 | { | |
2416 | u32 mac_mode; | |
2417 | int rc, i; | |
2418 | ||
2419 | spin_lock_bh(&bp->phy_lock); | |
ca58c3af | 2420 | rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | |
bc5a0690 MC |
2421 | BMCR_SPEED1000); |
2422 | spin_unlock_bh(&bp->phy_lock); | |
2423 | if (rc) | |
2424 | return rc; | |
2425 | ||
2426 | for (i = 0; i < 10; i++) { | |
2427 | if (bnx2_test_link(bp) == 0) | |
2428 | break; | |
80be4434 | 2429 | msleep(100); |
bc5a0690 MC |
2430 | } |
2431 | ||
e503e066 | 2432 | mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE); |
bc5a0690 MC |
2433 | mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | |
2434 | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | | |
59b47d8a | 2435 | BNX2_EMAC_MODE_25G_MODE); |
bc5a0690 MC |
2436 | |
2437 | mac_mode |= BNX2_EMAC_MODE_PORT_GMII; | |
e503e066 | 2438 | BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode); |
bc5a0690 MC |
2439 | bp->link_up = 1; |
2440 | return 0; | |
2441 | } | |
2442 | ||
ecdbf6e0 JH |
2443 | static void |
2444 | bnx2_dump_mcp_state(struct bnx2 *bp) | |
2445 | { | |
2446 | struct net_device *dev = bp->dev; | |
2447 | u32 mcp_p0, mcp_p1; | |
2448 | ||
2449 | netdev_err(dev, "<--- start MCP states dump --->\n"); | |
4ce45e02 | 2450 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
ecdbf6e0 JH |
2451 | mcp_p0 = BNX2_MCP_STATE_P0; |
2452 | mcp_p1 = BNX2_MCP_STATE_P1; | |
2453 | } else { | |
2454 | mcp_p0 = BNX2_MCP_STATE_P0_5708; | |
2455 | mcp_p1 = BNX2_MCP_STATE_P1_5708; | |
2456 | } | |
2457 | netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n", | |
2458 | bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1)); | |
2459 | netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n", | |
2460 | bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE), | |
2461 | bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE), | |
2462 | bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK)); | |
2463 | netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n", | |
2464 | bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER), | |
2465 | bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER), | |
2466 | bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION)); | |
2467 | netdev_err(dev, "DEBUG: shmem states:\n"); | |
2468 | netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]", | |
2469 | bnx2_shmem_rd(bp, BNX2_DRV_MB), | |
2470 | bnx2_shmem_rd(bp, BNX2_FW_MB), | |
2471 | bnx2_shmem_rd(bp, BNX2_LINK_STATUS)); | |
2472 | pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB)); | |
2473 | netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]", | |
2474 | bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE), | |
2475 | bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE)); | |
2476 | pr_cont(" condition[%08x]\n", | |
2477 | bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION)); | |
13e63517 | 2478 | DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE); |
ecdbf6e0 JH |
2479 | DP_SHMEM_LINE(bp, 0x3cc); |
2480 | DP_SHMEM_LINE(bp, 0x3dc); | |
2481 | DP_SHMEM_LINE(bp, 0x3ec); | |
2482 | netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc)); | |
2483 | netdev_err(dev, "<--- end MCP states dump --->\n"); | |
2484 | } | |
2485 | ||
b6016b76 | 2486 | static int |
a2f13890 | 2487 | bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent) |
b6016b76 MC |
2488 | { |
2489 | int i; | |
2490 | u32 val; | |
2491 | ||
b6016b76 MC |
2492 | bp->fw_wr_seq++; |
2493 | msg_data |= bp->fw_wr_seq; | |
2494 | ||
2726d6e1 | 2495 | bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); |
b6016b76 | 2496 | |
a2f13890 MC |
2497 | if (!ack) |
2498 | return 0; | |
2499 | ||
b6016b76 | 2500 | /* wait for an acknowledgement. */ |
40105c0b | 2501 | for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) { |
b090ae2b | 2502 | msleep(10); |
b6016b76 | 2503 | |
2726d6e1 | 2504 | val = bnx2_shmem_rd(bp, BNX2_FW_MB); |
b6016b76 MC |
2505 | |
2506 | if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) | |
2507 | break; | |
2508 | } | |
b090ae2b MC |
2509 | if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0) |
2510 | return 0; | |
b6016b76 MC |
2511 | |
2512 | /* If we timed out, inform the firmware that this is the case. */ | |
b090ae2b | 2513 | if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) { |
b6016b76 MC |
2514 | msg_data &= ~BNX2_DRV_MSG_CODE; |
2515 | msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; | |
2516 | ||
2726d6e1 | 2517 | bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); |
ecdbf6e0 JH |
2518 | if (!silent) { |
2519 | pr_err("fw sync timeout, reset code = %x\n", msg_data); | |
2520 | bnx2_dump_mcp_state(bp); | |
2521 | } | |
b6016b76 | 2522 | |
b6016b76 MC |
2523 | return -EBUSY; |
2524 | } | |
2525 | ||
b090ae2b MC |
2526 | if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK) |
2527 | return -EIO; | |
2528 | ||
b6016b76 MC |
2529 | return 0; |
2530 | } | |
2531 | ||
59b47d8a MC |
2532 | static int |
2533 | bnx2_init_5709_context(struct bnx2 *bp) | |
2534 | { | |
2535 | int i, ret = 0; | |
2536 | u32 val; | |
2537 | ||
2538 | val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12); | |
2bc4078e | 2539 | val |= (BNX2_PAGE_BITS - 8) << 16; |
e503e066 | 2540 | BNX2_WR(bp, BNX2_CTX_COMMAND, val); |
641bdcd5 | 2541 | for (i = 0; i < 10; i++) { |
e503e066 | 2542 | val = BNX2_RD(bp, BNX2_CTX_COMMAND); |
641bdcd5 MC |
2543 | if (!(val & BNX2_CTX_COMMAND_MEM_INIT)) |
2544 | break; | |
2545 | udelay(2); | |
2546 | } | |
2547 | if (val & BNX2_CTX_COMMAND_MEM_INIT) | |
2548 | return -EBUSY; | |
2549 | ||
59b47d8a MC |
2550 | for (i = 0; i < bp->ctx_pages; i++) { |
2551 | int j; | |
2552 | ||
352f7687 | 2553 | if (bp->ctx_blk[i]) |
2bc4078e | 2554 | memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE); |
352f7687 MC |
2555 | else |
2556 | return -ENOMEM; | |
2557 | ||
e503e066 MC |
2558 | BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0, |
2559 | (bp->ctx_blk_mapping[i] & 0xffffffff) | | |
2560 | BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID); | |
2561 | BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1, | |
2562 | (u64) bp->ctx_blk_mapping[i] >> 32); | |
2563 | BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i | | |
2564 | BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); | |
59b47d8a MC |
2565 | for (j = 0; j < 10; j++) { |
2566 | ||
e503e066 | 2567 | val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL); |
59b47d8a MC |
2568 | if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) |
2569 | break; | |
2570 | udelay(5); | |
2571 | } | |
2572 | if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) { | |
2573 | ret = -EBUSY; | |
2574 | break; | |
2575 | } | |
2576 | } | |
2577 | return ret; | |
2578 | } | |
2579 | ||
b6016b76 MC |
2580 | static void |
2581 | bnx2_init_context(struct bnx2 *bp) | |
2582 | { | |
2583 | u32 vcid; | |
2584 | ||
2585 | vcid = 96; | |
2586 | while (vcid) { | |
2587 | u32 vcid_addr, pcid_addr, offset; | |
7947b20e | 2588 | int i; |
b6016b76 MC |
2589 | |
2590 | vcid--; | |
2591 | ||
4ce45e02 | 2592 | if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { |
b6016b76 MC |
2593 | u32 new_vcid; |
2594 | ||
2595 | vcid_addr = GET_PCID_ADDR(vcid); | |
2596 | if (vcid & 0x8) { | |
2597 | new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7); | |
2598 | } | |
2599 | else { | |
2600 | new_vcid = vcid; | |
2601 | } | |
2602 | pcid_addr = GET_PCID_ADDR(new_vcid); | |
2603 | } | |
2604 | else { | |
2605 | vcid_addr = GET_CID_ADDR(vcid); | |
2606 | pcid_addr = vcid_addr; | |
2607 | } | |
2608 | ||
7947b20e MC |
2609 | for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) { |
2610 | vcid_addr += (i << PHY_CTX_SHIFT); | |
2611 | pcid_addr += (i << PHY_CTX_SHIFT); | |
b6016b76 | 2612 | |
e503e066 MC |
2613 | BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); |
2614 | BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); | |
b6016b76 | 2615 | |
7947b20e MC |
2616 | /* Zero out the context. */ |
2617 | for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) | |
62a8313c | 2618 | bnx2_ctx_wr(bp, vcid_addr, offset, 0); |
7947b20e | 2619 | } |
b6016b76 MC |
2620 | } |
2621 | } | |
2622 | ||
2623 | static int | |
2624 | bnx2_alloc_bad_rbuf(struct bnx2 *bp) | |
2625 | { | |
2626 | u16 *good_mbuf; | |
2627 | u32 good_mbuf_cnt; | |
2628 | u32 val; | |
2629 | ||
2630 | good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL); | |
e404decb | 2631 | if (good_mbuf == NULL) |
b6016b76 | 2632 | return -ENOMEM; |
b6016b76 | 2633 | |
e503e066 | 2634 | BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, |
b6016b76 MC |
2635 | BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); |
2636 | ||
2637 | good_mbuf_cnt = 0; | |
2638 | ||
2639 | /* Allocate a bunch of mbufs and save the good ones in an array. */ | |
2726d6e1 | 2640 | val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); |
b6016b76 | 2641 | while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { |
2726d6e1 MC |
2642 | bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND, |
2643 | BNX2_RBUF_COMMAND_ALLOC_REQ); | |
b6016b76 | 2644 | |
2726d6e1 | 2645 | val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC); |
b6016b76 MC |
2646 | |
2647 | val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; | |
2648 | ||
2649 | /* The addresses with Bit 9 set are bad memory blocks. */ | |
2650 | if (!(val & (1 << 9))) { | |
2651 | good_mbuf[good_mbuf_cnt] = (u16) val; | |
2652 | good_mbuf_cnt++; | |
2653 | } | |
2654 | ||
2726d6e1 | 2655 | val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); |
b6016b76 MC |
2656 | } |
2657 | ||
2658 | /* Free the good ones back to the mbuf pool thus discarding | |
2659 | * all the bad ones. */ | |
2660 | while (good_mbuf_cnt) { | |
2661 | good_mbuf_cnt--; | |
2662 | ||
2663 | val = good_mbuf[good_mbuf_cnt]; | |
2664 | val = (val << 9) | val | 1; | |
2665 | ||
2726d6e1 | 2666 | bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val); |
b6016b76 MC |
2667 | } |
2668 | kfree(good_mbuf); | |
2669 | return 0; | |
2670 | } | |
2671 | ||
2672 | static void | |
5fcaed01 | 2673 | bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos) |
b6016b76 MC |
2674 | { |
2675 | u32 val; | |
b6016b76 MC |
2676 | |
2677 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
2678 | ||
e503e066 | 2679 | BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val); |
b6016b76 | 2680 | |
6aa20a22 | 2681 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | |
b6016b76 MC |
2682 | (mac_addr[4] << 8) | mac_addr[5]; |
2683 | ||
e503e066 | 2684 | BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val); |
b6016b76 MC |
2685 | } |
2686 | ||
47bf4246 | 2687 | static inline int |
a2df00aa | 2688 | bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp) |
47bf4246 MC |
2689 | { |
2690 | dma_addr_t mapping; | |
2bc4078e MC |
2691 | struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; |
2692 | struct bnx2_rx_bd *rxbd = | |
2693 | &rxr->rx_pg_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; | |
a2df00aa | 2694 | struct page *page = alloc_page(gfp); |
47bf4246 MC |
2695 | |
2696 | if (!page) | |
2697 | return -ENOMEM; | |
36227e88 | 2698 | mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE, |
47bf4246 | 2699 | PCI_DMA_FROMDEVICE); |
36227e88 | 2700 | if (dma_mapping_error(&bp->pdev->dev, mapping)) { |
3d16af86 BL |
2701 | __free_page(page); |
2702 | return -EIO; | |
2703 | } | |
2704 | ||
47bf4246 | 2705 | rx_pg->page = page; |
1a4ccc2d | 2706 | dma_unmap_addr_set(rx_pg, mapping, mapping); |
47bf4246 MC |
2707 | rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; |
2708 | rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
2709 | return 0; | |
2710 | } | |
2711 | ||
2712 | static void | |
bb4f98ab | 2713 | bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index) |
47bf4246 | 2714 | { |
2bc4078e | 2715 | struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; |
47bf4246 MC |
2716 | struct page *page = rx_pg->page; |
2717 | ||
2718 | if (!page) | |
2719 | return; | |
2720 | ||
36227e88 SG |
2721 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping), |
2722 | PAGE_SIZE, PCI_DMA_FROMDEVICE); | |
47bf4246 MC |
2723 | |
2724 | __free_page(page); | |
2725 | rx_pg->page = NULL; | |
2726 | } | |
2727 | ||
b6016b76 | 2728 | static inline int |
dd2bc8e9 | 2729 | bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp) |
b6016b76 | 2730 | { |
dd2bc8e9 | 2731 | u8 *data; |
2bc4078e | 2732 | struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[index]; |
b6016b76 | 2733 | dma_addr_t mapping; |
2bc4078e MC |
2734 | struct bnx2_rx_bd *rxbd = |
2735 | &rxr->rx_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; | |
b6016b76 | 2736 | |
dd2bc8e9 ED |
2737 | data = kmalloc(bp->rx_buf_size, gfp); |
2738 | if (!data) | |
b6016b76 | 2739 | return -ENOMEM; |
b6016b76 | 2740 | |
dd2bc8e9 ED |
2741 | mapping = dma_map_single(&bp->pdev->dev, |
2742 | get_l2_fhdr(data), | |
2743 | bp->rx_buf_use_size, | |
36227e88 SG |
2744 | PCI_DMA_FROMDEVICE); |
2745 | if (dma_mapping_error(&bp->pdev->dev, mapping)) { | |
dd2bc8e9 | 2746 | kfree(data); |
3d16af86 BL |
2747 | return -EIO; |
2748 | } | |
b6016b76 | 2749 | |
dd2bc8e9 | 2750 | rx_buf->data = data; |
1a4ccc2d | 2751 | dma_unmap_addr_set(rx_buf, mapping, mapping); |
b6016b76 MC |
2752 | |
2753 | rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; | |
2754 | rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
2755 | ||
bb4f98ab | 2756 | rxr->rx_prod_bseq += bp->rx_buf_use_size; |
b6016b76 MC |
2757 | |
2758 | return 0; | |
2759 | } | |
2760 | ||
da3e4fbe | 2761 | static int |
35efa7c1 | 2762 | bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event) |
b6016b76 | 2763 | { |
43e80b89 | 2764 | struct status_block *sblk = bnapi->status_blk.msi; |
b6016b76 | 2765 | u32 new_link_state, old_link_state; |
da3e4fbe | 2766 | int is_set = 1; |
b6016b76 | 2767 | |
da3e4fbe MC |
2768 | new_link_state = sblk->status_attn_bits & event; |
2769 | old_link_state = sblk->status_attn_bits_ack & event; | |
b6016b76 | 2770 | if (new_link_state != old_link_state) { |
da3e4fbe | 2771 | if (new_link_state) |
e503e066 | 2772 | BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event); |
da3e4fbe | 2773 | else |
e503e066 | 2774 | BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event); |
da3e4fbe MC |
2775 | } else |
2776 | is_set = 0; | |
2777 | ||
2778 | return is_set; | |
2779 | } | |
2780 | ||
2781 | static void | |
35efa7c1 | 2782 | bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi) |
da3e4fbe | 2783 | { |
74ecc62d MC |
2784 | spin_lock(&bp->phy_lock); |
2785 | ||
2786 | if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) | |
b6016b76 | 2787 | bnx2_set_link(bp); |
35efa7c1 | 2788 | if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT)) |
0d8a6571 MC |
2789 | bnx2_set_remote_link(bp); |
2790 | ||
74ecc62d MC |
2791 | spin_unlock(&bp->phy_lock); |
2792 | ||
b6016b76 MC |
2793 | } |
2794 | ||
ead7270b | 2795 | static inline u16 |
35efa7c1 | 2796 | bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi) |
ead7270b MC |
2797 | { |
2798 | u16 cons; | |
2799 | ||
43e80b89 MC |
2800 | /* Tell compiler that status block fields can change. */ |
2801 | barrier(); | |
2802 | cons = *bnapi->hw_tx_cons_ptr; | |
581daf7e | 2803 | barrier(); |
2bc4078e | 2804 | if (unlikely((cons & BNX2_MAX_TX_DESC_CNT) == BNX2_MAX_TX_DESC_CNT)) |
ead7270b MC |
2805 | cons++; |
2806 | return cons; | |
2807 | } | |
2808 | ||
57851d84 MC |
2809 | static int |
2810 | bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) | |
b6016b76 | 2811 | { |
35e9010b | 2812 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; |
b6016b76 | 2813 | u16 hw_cons, sw_cons, sw_ring_cons; |
706bf240 | 2814 | int tx_pkt = 0, index; |
e9831909 | 2815 | unsigned int tx_bytes = 0; |
706bf240 BL |
2816 | struct netdev_queue *txq; |
2817 | ||
2818 | index = (bnapi - bp->bnx2_napi); | |
2819 | txq = netdev_get_tx_queue(bp->dev, index); | |
b6016b76 | 2820 | |
35efa7c1 | 2821 | hw_cons = bnx2_get_hw_tx_cons(bnapi); |
35e9010b | 2822 | sw_cons = txr->tx_cons; |
b6016b76 MC |
2823 | |
2824 | while (sw_cons != hw_cons) { | |
2bc4078e | 2825 | struct bnx2_sw_tx_bd *tx_buf; |
b6016b76 MC |
2826 | struct sk_buff *skb; |
2827 | int i, last; | |
2828 | ||
2bc4078e | 2829 | sw_ring_cons = BNX2_TX_RING_IDX(sw_cons); |
b6016b76 | 2830 | |
35e9010b | 2831 | tx_buf = &txr->tx_buf_ring[sw_ring_cons]; |
b6016b76 | 2832 | skb = tx_buf->skb; |
1d39ed56 | 2833 | |
d62fda08 ED |
2834 | /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */ |
2835 | prefetch(&skb->end); | |
2836 | ||
b6016b76 | 2837 | /* partial BD completions possible with TSO packets */ |
d62fda08 | 2838 | if (tx_buf->is_gso) { |
b6016b76 MC |
2839 | u16 last_idx, last_ring_idx; |
2840 | ||
d62fda08 ED |
2841 | last_idx = sw_cons + tx_buf->nr_frags + 1; |
2842 | last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1; | |
2bc4078e | 2843 | if (unlikely(last_ring_idx >= BNX2_MAX_TX_DESC_CNT)) { |
b6016b76 MC |
2844 | last_idx++; |
2845 | } | |
2846 | if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { | |
2847 | break; | |
2848 | } | |
2849 | } | |
1d39ed56 | 2850 | |
36227e88 | 2851 | dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), |
e95524a7 | 2852 | skb_headlen(skb), PCI_DMA_TODEVICE); |
b6016b76 MC |
2853 | |
2854 | tx_buf->skb = NULL; | |
d62fda08 | 2855 | last = tx_buf->nr_frags; |
b6016b76 MC |
2856 | |
2857 | for (i = 0; i < last; i++) { | |
2bc4078e | 2858 | struct bnx2_sw_tx_bd *tx_buf; |
e95524a7 | 2859 | |
2bc4078e MC |
2860 | sw_cons = BNX2_NEXT_TX_BD(sw_cons); |
2861 | ||
2862 | tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(sw_cons)]; | |
36227e88 | 2863 | dma_unmap_page(&bp->pdev->dev, |
2bc4078e | 2864 | dma_unmap_addr(tx_buf, mapping), |
9e903e08 | 2865 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
e95524a7 | 2866 | PCI_DMA_TODEVICE); |
b6016b76 MC |
2867 | } |
2868 | ||
2bc4078e | 2869 | sw_cons = BNX2_NEXT_TX_BD(sw_cons); |
b6016b76 | 2870 | |
e9831909 | 2871 | tx_bytes += skb->len; |
745720e5 | 2872 | dev_kfree_skb(skb); |
57851d84 MC |
2873 | tx_pkt++; |
2874 | if (tx_pkt == budget) | |
2875 | break; | |
b6016b76 | 2876 | |
d62fda08 ED |
2877 | if (hw_cons == sw_cons) |
2878 | hw_cons = bnx2_get_hw_tx_cons(bnapi); | |
b6016b76 MC |
2879 | } |
2880 | ||
e9831909 | 2881 | netdev_tx_completed_queue(txq, tx_pkt, tx_bytes); |
35e9010b MC |
2882 | txr->hw_tx_cons = hw_cons; |
2883 | txr->tx_cons = sw_cons; | |
706bf240 | 2884 | |
2f8af120 | 2885 | /* Need to make the tx_cons update visible to bnx2_start_xmit() |
706bf240 | 2886 | * before checking for netif_tx_queue_stopped(). Without the |
2f8af120 MC |
2887 | * memory barrier, there is a small possibility that bnx2_start_xmit() |
2888 | * will miss it and cause the queue to be stopped forever. | |
2889 | */ | |
2890 | smp_mb(); | |
b6016b76 | 2891 | |
706bf240 | 2892 | if (unlikely(netif_tx_queue_stopped(txq)) && |
35e9010b | 2893 | (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) { |
706bf240 BL |
2894 | __netif_tx_lock(txq, smp_processor_id()); |
2895 | if ((netif_tx_queue_stopped(txq)) && | |
35e9010b | 2896 | (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) |
706bf240 BL |
2897 | netif_tx_wake_queue(txq); |
2898 | __netif_tx_unlock(txq); | |
b6016b76 | 2899 | } |
706bf240 | 2900 | |
57851d84 | 2901 | return tx_pkt; |
b6016b76 MC |
2902 | } |
2903 | ||
1db82f2a | 2904 | static void |
bb4f98ab | 2905 | bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, |
a1f60190 | 2906 | struct sk_buff *skb, int count) |
1db82f2a | 2907 | { |
2bc4078e MC |
2908 | struct bnx2_sw_pg *cons_rx_pg, *prod_rx_pg; |
2909 | struct bnx2_rx_bd *cons_bd, *prod_bd; | |
1db82f2a | 2910 | int i; |
3d16af86 | 2911 | u16 hw_prod, prod; |
bb4f98ab | 2912 | u16 cons = rxr->rx_pg_cons; |
1db82f2a | 2913 | |
3d16af86 BL |
2914 | cons_rx_pg = &rxr->rx_pg_ring[cons]; |
2915 | ||
2916 | /* The caller was unable to allocate a new page to replace the | |
2917 | * last one in the frags array, so we need to recycle that page | |
2918 | * and then free the skb. | |
2919 | */ | |
2920 | if (skb) { | |
2921 | struct page *page; | |
2922 | struct skb_shared_info *shinfo; | |
2923 | ||
2924 | shinfo = skb_shinfo(skb); | |
2925 | shinfo->nr_frags--; | |
b7b6a688 IC |
2926 | page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]); |
2927 | __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL); | |
3d16af86 BL |
2928 | |
2929 | cons_rx_pg->page = page; | |
2930 | dev_kfree_skb(skb); | |
2931 | } | |
2932 | ||
2933 | hw_prod = rxr->rx_pg_prod; | |
2934 | ||
1db82f2a | 2935 | for (i = 0; i < count; i++) { |
2bc4078e | 2936 | prod = BNX2_RX_PG_RING_IDX(hw_prod); |
1db82f2a | 2937 | |
bb4f98ab MC |
2938 | prod_rx_pg = &rxr->rx_pg_ring[prod]; |
2939 | cons_rx_pg = &rxr->rx_pg_ring[cons]; | |
2bc4078e MC |
2940 | cons_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(cons)] |
2941 | [BNX2_RX_IDX(cons)]; | |
2942 | prod_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(prod)] | |
2943 | [BNX2_RX_IDX(prod)]; | |
1db82f2a | 2944 | |
1db82f2a MC |
2945 | if (prod != cons) { |
2946 | prod_rx_pg->page = cons_rx_pg->page; | |
2947 | cons_rx_pg->page = NULL; | |
1a4ccc2d FT |
2948 | dma_unmap_addr_set(prod_rx_pg, mapping, |
2949 | dma_unmap_addr(cons_rx_pg, mapping)); | |
1db82f2a MC |
2950 | |
2951 | prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; | |
2952 | prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; | |
2953 | ||
2954 | } | |
2bc4078e MC |
2955 | cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(cons)); |
2956 | hw_prod = BNX2_NEXT_RX_BD(hw_prod); | |
1db82f2a | 2957 | } |
bb4f98ab MC |
2958 | rxr->rx_pg_prod = hw_prod; |
2959 | rxr->rx_pg_cons = cons; | |
1db82f2a MC |
2960 | } |
2961 | ||
b6016b76 | 2962 | static inline void |
dd2bc8e9 ED |
2963 | bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, |
2964 | u8 *data, u16 cons, u16 prod) | |
b6016b76 | 2965 | { |
2bc4078e MC |
2966 | struct bnx2_sw_bd *cons_rx_buf, *prod_rx_buf; |
2967 | struct bnx2_rx_bd *cons_bd, *prod_bd; | |
236b6394 | 2968 | |
bb4f98ab MC |
2969 | cons_rx_buf = &rxr->rx_buf_ring[cons]; |
2970 | prod_rx_buf = &rxr->rx_buf_ring[prod]; | |
b6016b76 | 2971 | |
36227e88 | 2972 | dma_sync_single_for_device(&bp->pdev->dev, |
1a4ccc2d | 2973 | dma_unmap_addr(cons_rx_buf, mapping), |
601d3d18 | 2974 | BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE); |
b6016b76 | 2975 | |
bb4f98ab | 2976 | rxr->rx_prod_bseq += bp->rx_buf_use_size; |
b6016b76 | 2977 | |
dd2bc8e9 | 2978 | prod_rx_buf->data = data; |
b6016b76 | 2979 | |
236b6394 MC |
2980 | if (cons == prod) |
2981 | return; | |
b6016b76 | 2982 | |
1a4ccc2d FT |
2983 | dma_unmap_addr_set(prod_rx_buf, mapping, |
2984 | dma_unmap_addr(cons_rx_buf, mapping)); | |
236b6394 | 2985 | |
2bc4078e MC |
2986 | cons_bd = &rxr->rx_desc_ring[BNX2_RX_RING(cons)][BNX2_RX_IDX(cons)]; |
2987 | prod_bd = &rxr->rx_desc_ring[BNX2_RX_RING(prod)][BNX2_RX_IDX(prod)]; | |
236b6394 MC |
2988 | prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; |
2989 | prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; | |
b6016b76 MC |
2990 | } |
2991 | ||
dd2bc8e9 ED |
2992 | static struct sk_buff * |
2993 | bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data, | |
a1f60190 MC |
2994 | unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr, |
2995 | u32 ring_idx) | |
85833c62 MC |
2996 | { |
2997 | int err; | |
2998 | u16 prod = ring_idx & 0xffff; | |
dd2bc8e9 | 2999 | struct sk_buff *skb; |
85833c62 | 3000 | |
dd2bc8e9 | 3001 | err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); |
85833c62 | 3002 | if (unlikely(err)) { |
dd2bc8e9 ED |
3003 | bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod); |
3004 | error: | |
1db82f2a MC |
3005 | if (hdr_len) { |
3006 | unsigned int raw_len = len + 4; | |
3007 | int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT; | |
3008 | ||
bb4f98ab | 3009 | bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); |
1db82f2a | 3010 | } |
dd2bc8e9 | 3011 | return NULL; |
85833c62 MC |
3012 | } |
3013 | ||
36227e88 | 3014 | dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, |
85833c62 | 3015 | PCI_DMA_FROMDEVICE); |
d3836f21 | 3016 | skb = build_skb(data, 0); |
dd2bc8e9 ED |
3017 | if (!skb) { |
3018 | kfree(data); | |
3019 | goto error; | |
3020 | } | |
3021 | skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET); | |
1db82f2a MC |
3022 | if (hdr_len == 0) { |
3023 | skb_put(skb, len); | |
dd2bc8e9 | 3024 | return skb; |
1db82f2a MC |
3025 | } else { |
3026 | unsigned int i, frag_len, frag_size, pages; | |
2bc4078e | 3027 | struct bnx2_sw_pg *rx_pg; |
bb4f98ab MC |
3028 | u16 pg_cons = rxr->rx_pg_cons; |
3029 | u16 pg_prod = rxr->rx_pg_prod; | |
1db82f2a MC |
3030 | |
3031 | frag_size = len + 4 - hdr_len; | |
3032 | pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT; | |
3033 | skb_put(skb, hdr_len); | |
3034 | ||
3035 | for (i = 0; i < pages; i++) { | |
3d16af86 BL |
3036 | dma_addr_t mapping_old; |
3037 | ||
1db82f2a MC |
3038 | frag_len = min(frag_size, (unsigned int) PAGE_SIZE); |
3039 | if (unlikely(frag_len <= 4)) { | |
3040 | unsigned int tail = 4 - frag_len; | |
3041 | ||
bb4f98ab MC |
3042 | rxr->rx_pg_cons = pg_cons; |
3043 | rxr->rx_pg_prod = pg_prod; | |
3044 | bnx2_reuse_rx_skb_pages(bp, rxr, NULL, | |
a1f60190 | 3045 | pages - i); |
1db82f2a MC |
3046 | skb->len -= tail; |
3047 | if (i == 0) { | |
3048 | skb->tail -= tail; | |
3049 | } else { | |
3050 | skb_frag_t *frag = | |
3051 | &skb_shinfo(skb)->frags[i - 1]; | |
9e903e08 | 3052 | skb_frag_size_sub(frag, tail); |
1db82f2a | 3053 | skb->data_len -= tail; |
1db82f2a | 3054 | } |
dd2bc8e9 | 3055 | return skb; |
1db82f2a | 3056 | } |
bb4f98ab | 3057 | rx_pg = &rxr->rx_pg_ring[pg_cons]; |
1db82f2a | 3058 | |
3d16af86 BL |
3059 | /* Don't unmap yet. If we're unable to allocate a new |
3060 | * page, we need to recycle the page and the DMA addr. | |
3061 | */ | |
1a4ccc2d | 3062 | mapping_old = dma_unmap_addr(rx_pg, mapping); |
1db82f2a MC |
3063 | if (i == pages - 1) |
3064 | frag_len -= 4; | |
3065 | ||
3066 | skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); | |
3067 | rx_pg->page = NULL; | |
3068 | ||
bb4f98ab | 3069 | err = bnx2_alloc_rx_page(bp, rxr, |
2bc4078e | 3070 | BNX2_RX_PG_RING_IDX(pg_prod), |
a2df00aa | 3071 | GFP_ATOMIC); |
1db82f2a | 3072 | if (unlikely(err)) { |
bb4f98ab MC |
3073 | rxr->rx_pg_cons = pg_cons; |
3074 | rxr->rx_pg_prod = pg_prod; | |
3075 | bnx2_reuse_rx_skb_pages(bp, rxr, skb, | |
a1f60190 | 3076 | pages - i); |
dd2bc8e9 | 3077 | return NULL; |
1db82f2a MC |
3078 | } |
3079 | ||
36227e88 | 3080 | dma_unmap_page(&bp->pdev->dev, mapping_old, |
3d16af86 BL |
3081 | PAGE_SIZE, PCI_DMA_FROMDEVICE); |
3082 | ||
1db82f2a MC |
3083 | frag_size -= frag_len; |
3084 | skb->data_len += frag_len; | |
a1f4e8bc | 3085 | skb->truesize += PAGE_SIZE; |
1db82f2a MC |
3086 | skb->len += frag_len; |
3087 | ||
2bc4078e MC |
3088 | pg_prod = BNX2_NEXT_RX_BD(pg_prod); |
3089 | pg_cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(pg_cons)); | |
1db82f2a | 3090 | } |
bb4f98ab MC |
3091 | rxr->rx_pg_prod = pg_prod; |
3092 | rxr->rx_pg_cons = pg_cons; | |
1db82f2a | 3093 | } |
dd2bc8e9 | 3094 | return skb; |
85833c62 MC |
3095 | } |
3096 | ||
c09c2627 | 3097 | static inline u16 |
35efa7c1 | 3098 | bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi) |
c09c2627 | 3099 | { |
bb4f98ab MC |
3100 | u16 cons; |
3101 | ||
43e80b89 MC |
3102 | /* Tell compiler that status block fields can change. */ |
3103 | barrier(); | |
3104 | cons = *bnapi->hw_rx_cons_ptr; | |
581daf7e | 3105 | barrier(); |
2bc4078e | 3106 | if (unlikely((cons & BNX2_MAX_RX_DESC_CNT) == BNX2_MAX_RX_DESC_CNT)) |
c09c2627 MC |
3107 | cons++; |
3108 | return cons; | |
3109 | } | |
3110 | ||
b6016b76 | 3111 | static int |
35efa7c1 | 3112 | bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) |
b6016b76 | 3113 | { |
bb4f98ab | 3114 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; |
b6016b76 MC |
3115 | u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; |
3116 | struct l2_fhdr *rx_hdr; | |
1db82f2a | 3117 | int rx_pkt = 0, pg_ring_used = 0; |
b6016b76 | 3118 | |
35efa7c1 | 3119 | hw_cons = bnx2_get_hw_rx_cons(bnapi); |
bb4f98ab MC |
3120 | sw_cons = rxr->rx_cons; |
3121 | sw_prod = rxr->rx_prod; | |
b6016b76 MC |
3122 | |
3123 | /* Memory barrier necessary as speculative reads of the rx | |
3124 | * buffer can be ahead of the index in the status block | |
3125 | */ | |
3126 | rmb(); | |
3127 | while (sw_cons != hw_cons) { | |
1db82f2a | 3128 | unsigned int len, hdr_len; |
ade2bfe7 | 3129 | u32 status; |
2bc4078e | 3130 | struct bnx2_sw_bd *rx_buf, *next_rx_buf; |
b6016b76 | 3131 | struct sk_buff *skb; |
236b6394 | 3132 | dma_addr_t dma_addr; |
dd2bc8e9 | 3133 | u8 *data; |
2bc4078e | 3134 | u16 next_ring_idx; |
b6016b76 | 3135 | |
2bc4078e MC |
3136 | sw_ring_cons = BNX2_RX_RING_IDX(sw_cons); |
3137 | sw_ring_prod = BNX2_RX_RING_IDX(sw_prod); | |
b6016b76 | 3138 | |
bb4f98ab | 3139 | rx_buf = &rxr->rx_buf_ring[sw_ring_cons]; |
dd2bc8e9 ED |
3140 | data = rx_buf->data; |
3141 | rx_buf->data = NULL; | |
aabef8b2 | 3142 | |
dd2bc8e9 ED |
3143 | rx_hdr = get_l2_fhdr(data); |
3144 | prefetch(rx_hdr); | |
236b6394 | 3145 | |
1a4ccc2d | 3146 | dma_addr = dma_unmap_addr(rx_buf, mapping); |
236b6394 | 3147 | |
36227e88 | 3148 | dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr, |
601d3d18 BL |
3149 | BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, |
3150 | PCI_DMA_FROMDEVICE); | |
b6016b76 | 3151 | |
2bc4078e MC |
3152 | next_ring_idx = BNX2_RX_RING_IDX(BNX2_NEXT_RX_BD(sw_cons)); |
3153 | next_rx_buf = &rxr->rx_buf_ring[next_ring_idx]; | |
dd2bc8e9 ED |
3154 | prefetch(get_l2_fhdr(next_rx_buf->data)); |
3155 | ||
1db82f2a | 3156 | len = rx_hdr->l2_fhdr_pkt_len; |
990ec380 | 3157 | status = rx_hdr->l2_fhdr_status; |
b6016b76 | 3158 | |
1db82f2a MC |
3159 | hdr_len = 0; |
3160 | if (status & L2_FHDR_STATUS_SPLIT) { | |
3161 | hdr_len = rx_hdr->l2_fhdr_ip_xsum; | |
3162 | pg_ring_used = 1; | |
3163 | } else if (len > bp->rx_jumbo_thresh) { | |
3164 | hdr_len = bp->rx_jumbo_thresh; | |
3165 | pg_ring_used = 1; | |
3166 | } | |
3167 | ||
990ec380 MC |
3168 | if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC | |
3169 | L2_FHDR_ERRORS_PHY_DECODE | | |
3170 | L2_FHDR_ERRORS_ALIGNMENT | | |
3171 | L2_FHDR_ERRORS_TOO_SHORT | | |
3172 | L2_FHDR_ERRORS_GIANT_FRAME))) { | |
3173 | ||
dd2bc8e9 | 3174 | bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons, |
990ec380 MC |
3175 | sw_ring_prod); |
3176 | if (pg_ring_used) { | |
3177 | int pages; | |
3178 | ||
3179 | pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT; | |
3180 | ||
3181 | bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); | |
3182 | } | |
3183 | goto next_rx; | |
3184 | } | |
3185 | ||
1db82f2a | 3186 | len -= 4; |
b6016b76 | 3187 | |
5d5d0015 | 3188 | if (len <= bp->rx_copy_thresh) { |
dd2bc8e9 ED |
3189 | skb = netdev_alloc_skb(bp->dev, len + 6); |
3190 | if (skb == NULL) { | |
3191 | bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons, | |
85833c62 MC |
3192 | sw_ring_prod); |
3193 | goto next_rx; | |
3194 | } | |
b6016b76 MC |
3195 | |
3196 | /* aligned copy */ | |
dd2bc8e9 ED |
3197 | memcpy(skb->data, |
3198 | (u8 *)rx_hdr + BNX2_RX_OFFSET - 6, | |
3199 | len + 6); | |
3200 | skb_reserve(skb, 6); | |
3201 | skb_put(skb, len); | |
b6016b76 | 3202 | |
dd2bc8e9 | 3203 | bnx2_reuse_rx_data(bp, rxr, data, |
b6016b76 MC |
3204 | sw_ring_cons, sw_ring_prod); |
3205 | ||
dd2bc8e9 ED |
3206 | } else { |
3207 | skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr, | |
3208 | (sw_ring_cons << 16) | sw_ring_prod); | |
3209 | if (!skb) | |
3210 | goto next_rx; | |
3211 | } | |
f22828e8 | 3212 | if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && |
7d0fd211 | 3213 | !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) |
86a9bad3 | 3214 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rx_hdr->l2_fhdr_vlan_tag); |
f22828e8 | 3215 | |
b6016b76 MC |
3216 | skb->protocol = eth_type_trans(skb, bp->dev); |
3217 | ||
3218 | if ((len > (bp->dev->mtu + ETH_HLEN)) && | |
d1e100ba | 3219 | (ntohs(skb->protocol) != 0x8100)) { |
b6016b76 | 3220 | |
745720e5 | 3221 | dev_kfree_skb(skb); |
b6016b76 MC |
3222 | goto next_rx; |
3223 | ||
3224 | } | |
3225 | ||
bc8acf2c | 3226 | skb_checksum_none_assert(skb); |
8d7dfc2b | 3227 | if ((bp->dev->features & NETIF_F_RXCSUM) && |
b6016b76 MC |
3228 | (status & (L2_FHDR_STATUS_TCP_SEGMENT | |
3229 | L2_FHDR_STATUS_UDP_DATAGRAM))) { | |
3230 | ||
ade2bfe7 MC |
3231 | if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM | |
3232 | L2_FHDR_ERRORS_UDP_XSUM)) == 0)) | |
b6016b76 MC |
3233 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
3234 | } | |
fdc8541d MC |
3235 | if ((bp->dev->features & NETIF_F_RXHASH) && |
3236 | ((status & L2_FHDR_STATUS_USE_RXHASH) == | |
3237 | L2_FHDR_STATUS_USE_RXHASH)) | |
3238 | skb->rxhash = rx_hdr->l2_fhdr_hash; | |
b6016b76 | 3239 | |
0c8dfc83 | 3240 | skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]); |
7d0fd211 | 3241 | napi_gro_receive(&bnapi->napi, skb); |
b6016b76 MC |
3242 | rx_pkt++; |
3243 | ||
3244 | next_rx: | |
2bc4078e MC |
3245 | sw_cons = BNX2_NEXT_RX_BD(sw_cons); |
3246 | sw_prod = BNX2_NEXT_RX_BD(sw_prod); | |
b6016b76 MC |
3247 | |
3248 | if ((rx_pkt == budget)) | |
3249 | break; | |
f4e418f7 MC |
3250 | |
3251 | /* Refresh hw_cons to see if there is new work */ | |
3252 | if (sw_cons == hw_cons) { | |
35efa7c1 | 3253 | hw_cons = bnx2_get_hw_rx_cons(bnapi); |
f4e418f7 MC |
3254 | rmb(); |
3255 | } | |
b6016b76 | 3256 | } |
bb4f98ab MC |
3257 | rxr->rx_cons = sw_cons; |
3258 | rxr->rx_prod = sw_prod; | |
b6016b76 | 3259 | |
1db82f2a | 3260 | if (pg_ring_used) |
e503e066 | 3261 | BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); |
1db82f2a | 3262 | |
e503e066 | 3263 | BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod); |
b6016b76 | 3264 | |
e503e066 | 3265 | BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); |
b6016b76 MC |
3266 | |
3267 | mmiowb(); | |
3268 | ||
3269 | return rx_pkt; | |
3270 | ||
3271 | } | |
3272 | ||
3273 | /* MSI ISR - The only difference between this and the INTx ISR | |
3274 | * is that the MSI interrupt is always serviced. | |
3275 | */ | |
3276 | static irqreturn_t | |
7d12e780 | 3277 | bnx2_msi(int irq, void *dev_instance) |
b6016b76 | 3278 | { |
f0ea2e63 MC |
3279 | struct bnx2_napi *bnapi = dev_instance; |
3280 | struct bnx2 *bp = bnapi->bp; | |
b6016b76 | 3281 | |
43e80b89 | 3282 | prefetch(bnapi->status_blk.msi); |
e503e066 | 3283 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
b6016b76 MC |
3284 | BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | |
3285 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
3286 | ||
3287 | /* Return here if interrupt is disabled. */ | |
73eef4cd MC |
3288 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) |
3289 | return IRQ_HANDLED; | |
b6016b76 | 3290 | |
288379f0 | 3291 | napi_schedule(&bnapi->napi); |
b6016b76 | 3292 | |
73eef4cd | 3293 | return IRQ_HANDLED; |
b6016b76 MC |
3294 | } |
3295 | ||
8e6a72c4 MC |
3296 | static irqreturn_t |
3297 | bnx2_msi_1shot(int irq, void *dev_instance) | |
3298 | { | |
f0ea2e63 MC |
3299 | struct bnx2_napi *bnapi = dev_instance; |
3300 | struct bnx2 *bp = bnapi->bp; | |
8e6a72c4 | 3301 | |
43e80b89 | 3302 | prefetch(bnapi->status_blk.msi); |
8e6a72c4 MC |
3303 | |
3304 | /* Return here if interrupt is disabled. */ | |
3305 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) | |
3306 | return IRQ_HANDLED; | |
3307 | ||
288379f0 | 3308 | napi_schedule(&bnapi->napi); |
8e6a72c4 MC |
3309 | |
3310 | return IRQ_HANDLED; | |
3311 | } | |
3312 | ||
b6016b76 | 3313 | static irqreturn_t |
7d12e780 | 3314 | bnx2_interrupt(int irq, void *dev_instance) |
b6016b76 | 3315 | { |
f0ea2e63 MC |
3316 | struct bnx2_napi *bnapi = dev_instance; |
3317 | struct bnx2 *bp = bnapi->bp; | |
43e80b89 | 3318 | struct status_block *sblk = bnapi->status_blk.msi; |
b6016b76 MC |
3319 | |
3320 | /* When using INTx, it is possible for the interrupt to arrive | |
3321 | * at the CPU before the status block posted prior to the | |
3322 | * interrupt. Reading a register will flush the status block. | |
3323 | * When using MSI, the MSI message will always complete after | |
3324 | * the status block write. | |
3325 | */ | |
35efa7c1 | 3326 | if ((sblk->status_idx == bnapi->last_status_idx) && |
e503e066 | 3327 | (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) & |
b6016b76 | 3328 | BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) |
73eef4cd | 3329 | return IRQ_NONE; |
b6016b76 | 3330 | |
e503e066 | 3331 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
b6016b76 MC |
3332 | BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | |
3333 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | |
3334 | ||
b8a7ce7b MC |
3335 | /* Read back to deassert IRQ immediately to avoid too many |
3336 | * spurious interrupts. | |
3337 | */ | |
e503e066 | 3338 | BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); |
b8a7ce7b | 3339 | |
b6016b76 | 3340 | /* Return here if interrupt is shared and is disabled. */ |
73eef4cd MC |
3341 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) |
3342 | return IRQ_HANDLED; | |
b6016b76 | 3343 | |
288379f0 | 3344 | if (napi_schedule_prep(&bnapi->napi)) { |
35efa7c1 | 3345 | bnapi->last_status_idx = sblk->status_idx; |
288379f0 | 3346 | __napi_schedule(&bnapi->napi); |
b8a7ce7b | 3347 | } |
b6016b76 | 3348 | |
73eef4cd | 3349 | return IRQ_HANDLED; |
b6016b76 MC |
3350 | } |
3351 | ||
f4e418f7 | 3352 | static inline int |
43e80b89 | 3353 | bnx2_has_fast_work(struct bnx2_napi *bnapi) |
f4e418f7 | 3354 | { |
35e9010b | 3355 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; |
bb4f98ab | 3356 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; |
f4e418f7 | 3357 | |
bb4f98ab | 3358 | if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) || |
35e9010b | 3359 | (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)) |
f4e418f7 | 3360 | return 1; |
43e80b89 MC |
3361 | return 0; |
3362 | } | |
3363 | ||
3364 | #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \ | |
3365 | STATUS_ATTN_BITS_TIMER_ABORT) | |
3366 | ||
3367 | static inline int | |
3368 | bnx2_has_work(struct bnx2_napi *bnapi) | |
3369 | { | |
3370 | struct status_block *sblk = bnapi->status_blk.msi; | |
3371 | ||
3372 | if (bnx2_has_fast_work(bnapi)) | |
3373 | return 1; | |
f4e418f7 | 3374 | |
4edd473f MC |
3375 | #ifdef BCM_CNIC |
3376 | if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx)) | |
3377 | return 1; | |
3378 | #endif | |
3379 | ||
da3e4fbe MC |
3380 | if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != |
3381 | (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS)) | |
f4e418f7 MC |
3382 | return 1; |
3383 | ||
3384 | return 0; | |
3385 | } | |
3386 | ||
efba0180 MC |
3387 | static void |
3388 | bnx2_chk_missed_msi(struct bnx2 *bp) | |
3389 | { | |
3390 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; | |
3391 | u32 msi_ctrl; | |
3392 | ||
3393 | if (bnx2_has_work(bnapi)) { | |
e503e066 | 3394 | msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL); |
efba0180 MC |
3395 | if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE)) |
3396 | return; | |
3397 | ||
3398 | if (bnapi->last_status_idx == bp->idle_chk_status_idx) { | |
e503e066 MC |
3399 | BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl & |
3400 | ~BNX2_PCICFG_MSI_CONTROL_ENABLE); | |
3401 | BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl); | |
efba0180 MC |
3402 | bnx2_msi(bp->irq_tbl[0].vector, bnapi); |
3403 | } | |
3404 | } | |
3405 | ||
3406 | bp->idle_chk_status_idx = bnapi->last_status_idx; | |
3407 | } | |
3408 | ||
4edd473f MC |
3409 | #ifdef BCM_CNIC |
3410 | static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi) | |
3411 | { | |
3412 | struct cnic_ops *c_ops; | |
3413 | ||
3414 | if (!bnapi->cnic_present) | |
3415 | return; | |
3416 | ||
3417 | rcu_read_lock(); | |
3418 | c_ops = rcu_dereference(bp->cnic_ops); | |
3419 | if (c_ops) | |
3420 | bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data, | |
3421 | bnapi->status_blk.msi); | |
3422 | rcu_read_unlock(); | |
3423 | } | |
3424 | #endif | |
3425 | ||
43e80b89 | 3426 | static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi) |
b6016b76 | 3427 | { |
43e80b89 | 3428 | struct status_block *sblk = bnapi->status_blk.msi; |
da3e4fbe MC |
3429 | u32 status_attn_bits = sblk->status_attn_bits; |
3430 | u32 status_attn_bits_ack = sblk->status_attn_bits_ack; | |
b6016b76 | 3431 | |
da3e4fbe MC |
3432 | if ((status_attn_bits & STATUS_ATTN_EVENTS) != |
3433 | (status_attn_bits_ack & STATUS_ATTN_EVENTS)) { | |
b6016b76 | 3434 | |
35efa7c1 | 3435 | bnx2_phy_int(bp, bnapi); |
bf5295bb MC |
3436 | |
3437 | /* This is needed to take care of transient status | |
3438 | * during link changes. | |
3439 | */ | |
e503e066 MC |
3440 | BNX2_WR(bp, BNX2_HC_COMMAND, |
3441 | bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
3442 | BNX2_RD(bp, BNX2_HC_COMMAND); | |
b6016b76 | 3443 | } |
43e80b89 MC |
3444 | } |
3445 | ||
3446 | static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi, | |
3447 | int work_done, int budget) | |
3448 | { | |
3449 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; | |
3450 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
b6016b76 | 3451 | |
35e9010b | 3452 | if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons) |
57851d84 | 3453 | bnx2_tx_int(bp, bnapi, 0); |
b6016b76 | 3454 | |
bb4f98ab | 3455 | if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) |
35efa7c1 | 3456 | work_done += bnx2_rx_int(bp, bnapi, budget - work_done); |
6aa20a22 | 3457 | |
6f535763 DM |
3458 | return work_done; |
3459 | } | |
3460 | ||
f0ea2e63 MC |
3461 | static int bnx2_poll_msix(struct napi_struct *napi, int budget) |
3462 | { | |
3463 | struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); | |
3464 | struct bnx2 *bp = bnapi->bp; | |
3465 | int work_done = 0; | |
3466 | struct status_block_msix *sblk = bnapi->status_blk.msix; | |
3467 | ||
3468 | while (1) { | |
3469 | work_done = bnx2_poll_work(bp, bnapi, work_done, budget); | |
3470 | if (unlikely(work_done >= budget)) | |
3471 | break; | |
3472 | ||
3473 | bnapi->last_status_idx = sblk->status_idx; | |
3474 | /* status idx must be read before checking for more work. */ | |
3475 | rmb(); | |
3476 | if (likely(!bnx2_has_fast_work(bnapi))) { | |
3477 | ||
288379f0 | 3478 | napi_complete(napi); |
e503e066 MC |
3479 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | |
3480 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
3481 | bnapi->last_status_idx); | |
f0ea2e63 MC |
3482 | break; |
3483 | } | |
3484 | } | |
3485 | return work_done; | |
3486 | } | |
3487 | ||
6f535763 DM |
3488 | static int bnx2_poll(struct napi_struct *napi, int budget) |
3489 | { | |
35efa7c1 MC |
3490 | struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); |
3491 | struct bnx2 *bp = bnapi->bp; | |
6f535763 | 3492 | int work_done = 0; |
43e80b89 | 3493 | struct status_block *sblk = bnapi->status_blk.msi; |
6f535763 DM |
3494 | |
3495 | while (1) { | |
43e80b89 MC |
3496 | bnx2_poll_link(bp, bnapi); |
3497 | ||
35efa7c1 | 3498 | work_done = bnx2_poll_work(bp, bnapi, work_done, budget); |
f4e418f7 | 3499 | |
4edd473f MC |
3500 | #ifdef BCM_CNIC |
3501 | bnx2_poll_cnic(bp, bnapi); | |
3502 | #endif | |
3503 | ||
35efa7c1 | 3504 | /* bnapi->last_status_idx is used below to tell the hw how |
6dee6421 MC |
3505 | * much work has been processed, so we must read it before |
3506 | * checking for more work. | |
3507 | */ | |
35efa7c1 | 3508 | bnapi->last_status_idx = sblk->status_idx; |
efba0180 MC |
3509 | |
3510 | if (unlikely(work_done >= budget)) | |
3511 | break; | |
3512 | ||
6dee6421 | 3513 | rmb(); |
35efa7c1 | 3514 | if (likely(!bnx2_has_work(bnapi))) { |
288379f0 | 3515 | napi_complete(napi); |
f86e82fb | 3516 | if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { |
e503e066 MC |
3517 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
3518 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
3519 | bnapi->last_status_idx); | |
6dee6421 | 3520 | break; |
6f535763 | 3521 | } |
e503e066 MC |
3522 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, |
3523 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
3524 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT | | |
3525 | bnapi->last_status_idx); | |
3526 | ||
3527 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | |
3528 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | |
3529 | bnapi->last_status_idx); | |
6f535763 DM |
3530 | break; |
3531 | } | |
b6016b76 MC |
3532 | } |
3533 | ||
bea3348e | 3534 | return work_done; |
b6016b76 MC |
3535 | } |
3536 | ||
932ff279 | 3537 | /* Called with rtnl_lock from vlan functions and also netif_tx_lock |
b6016b76 MC |
3538 | * from set_multicast. |
3539 | */ | |
3540 | static void | |
3541 | bnx2_set_rx_mode(struct net_device *dev) | |
3542 | { | |
972ec0d4 | 3543 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 3544 | u32 rx_mode, sort_mode; |
ccffad25 | 3545 | struct netdev_hw_addr *ha; |
b6016b76 | 3546 | int i; |
b6016b76 | 3547 | |
9f52b564 MC |
3548 | if (!netif_running(dev)) |
3549 | return; | |
3550 | ||
c770a65c | 3551 | spin_lock_bh(&bp->phy_lock); |
b6016b76 MC |
3552 | |
3553 | rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | | |
3554 | BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); | |
3555 | sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; | |
f646968f | 3556 | if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
7d0fd211 | 3557 | (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) |
b6016b76 | 3558 | rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; |
b6016b76 MC |
3559 | if (dev->flags & IFF_PROMISC) { |
3560 | /* Promiscuous mode. */ | |
3561 | rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; | |
7510873d MC |
3562 | sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | |
3563 | BNX2_RPM_SORT_USER0_PROM_VLAN; | |
b6016b76 MC |
3564 | } |
3565 | else if (dev->flags & IFF_ALLMULTI) { | |
3566 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
e503e066 MC |
3567 | BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), |
3568 | 0xffffffff); | |
b6016b76 MC |
3569 | } |
3570 | sort_mode |= BNX2_RPM_SORT_USER0_MC_EN; | |
3571 | } | |
3572 | else { | |
3573 | /* Accept one or more multicast(s). */ | |
b6016b76 MC |
3574 | u32 mc_filter[NUM_MC_HASH_REGISTERS]; |
3575 | u32 regidx; | |
3576 | u32 bit; | |
3577 | u32 crc; | |
3578 | ||
3579 | memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS); | |
3580 | ||
22bedad3 JP |
3581 | netdev_for_each_mc_addr(ha, dev) { |
3582 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
b6016b76 MC |
3583 | bit = crc & 0xff; |
3584 | regidx = (bit & 0xe0) >> 5; | |
3585 | bit &= 0x1f; | |
3586 | mc_filter[regidx] |= (1 << bit); | |
3587 | } | |
3588 | ||
3589 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
e503e066 MC |
3590 | BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), |
3591 | mc_filter[i]); | |
b6016b76 MC |
3592 | } |
3593 | ||
3594 | sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN; | |
3595 | } | |
3596 | ||
32e7bfc4 | 3597 | if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) { |
5fcaed01 BL |
3598 | rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; |
3599 | sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | | |
3600 | BNX2_RPM_SORT_USER0_PROM_VLAN; | |
3601 | } else if (!(dev->flags & IFF_PROMISC)) { | |
5fcaed01 | 3602 | /* Add all entries into to the match filter list */ |
ccffad25 | 3603 | i = 0; |
32e7bfc4 | 3604 | netdev_for_each_uc_addr(ha, dev) { |
ccffad25 | 3605 | bnx2_set_mac_addr(bp, ha->addr, |
5fcaed01 BL |
3606 | i + BNX2_START_UNICAST_ADDRESS_INDEX); |
3607 | sort_mode |= (1 << | |
3608 | (i + BNX2_START_UNICAST_ADDRESS_INDEX)); | |
ccffad25 | 3609 | i++; |
5fcaed01 BL |
3610 | } |
3611 | ||
3612 | } | |
3613 | ||
b6016b76 MC |
3614 | if (rx_mode != bp->rx_mode) { |
3615 | bp->rx_mode = rx_mode; | |
e503e066 | 3616 | BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); |
b6016b76 MC |
3617 | } |
3618 | ||
e503e066 MC |
3619 | BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); |
3620 | BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode); | |
3621 | BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); | |
b6016b76 | 3622 | |
c770a65c | 3623 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
3624 | } |
3625 | ||
7880b72e | 3626 | static int |
57579f76 MC |
3627 | check_fw_section(const struct firmware *fw, |
3628 | const struct bnx2_fw_file_section *section, | |
3629 | u32 alignment, bool non_empty) | |
3630 | { | |
3631 | u32 offset = be32_to_cpu(section->offset); | |
3632 | u32 len = be32_to_cpu(section->len); | |
3633 | ||
3634 | if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3) | |
3635 | return -EINVAL; | |
3636 | if ((non_empty && len == 0) || len > fw->size - offset || | |
3637 | len & (alignment - 1)) | |
3638 | return -EINVAL; | |
3639 | return 0; | |
3640 | } | |
3641 | ||
7880b72e | 3642 | static int |
57579f76 MC |
3643 | check_mips_fw_entry(const struct firmware *fw, |
3644 | const struct bnx2_mips_fw_file_entry *entry) | |
3645 | { | |
3646 | if (check_fw_section(fw, &entry->text, 4, true) || | |
3647 | check_fw_section(fw, &entry->data, 4, false) || | |
3648 | check_fw_section(fw, &entry->rodata, 4, false)) | |
3649 | return -EINVAL; | |
3650 | return 0; | |
3651 | } | |
3652 | ||
7880b72e | 3653 | static void bnx2_release_firmware(struct bnx2 *bp) |
3654 | { | |
3655 | if (bp->rv2p_firmware) { | |
3656 | release_firmware(bp->mips_firmware); | |
3657 | release_firmware(bp->rv2p_firmware); | |
3658 | bp->rv2p_firmware = NULL; | |
3659 | } | |
3660 | } | |
3661 | ||
3662 | static int bnx2_request_uncached_firmware(struct bnx2 *bp) | |
b6016b76 | 3663 | { |
57579f76 | 3664 | const char *mips_fw_file, *rv2p_fw_file; |
5ee1c326 BB |
3665 | const struct bnx2_mips_fw_file *mips_fw; |
3666 | const struct bnx2_rv2p_fw_file *rv2p_fw; | |
57579f76 MC |
3667 | int rc; |
3668 | ||
4ce45e02 | 3669 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
57579f76 | 3670 | mips_fw_file = FW_MIPS_FILE_09; |
4ce45e02 MC |
3671 | if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) || |
3672 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1)) | |
078b0735 MC |
3673 | rv2p_fw_file = FW_RV2P_FILE_09_Ax; |
3674 | else | |
3675 | rv2p_fw_file = FW_RV2P_FILE_09; | |
57579f76 MC |
3676 | } else { |
3677 | mips_fw_file = FW_MIPS_FILE_06; | |
3678 | rv2p_fw_file = FW_RV2P_FILE_06; | |
3679 | } | |
3680 | ||
3681 | rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev); | |
3682 | if (rc) { | |
3a9c6a49 | 3683 | pr_err("Can't load firmware file \"%s\"\n", mips_fw_file); |
7880b72e | 3684 | goto out; |
57579f76 MC |
3685 | } |
3686 | ||
3687 | rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev); | |
3688 | if (rc) { | |
3a9c6a49 | 3689 | pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file); |
7880b72e | 3690 | goto err_release_mips_firmware; |
57579f76 | 3691 | } |
5ee1c326 BB |
3692 | mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; |
3693 | rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; | |
3694 | if (bp->mips_firmware->size < sizeof(*mips_fw) || | |
3695 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) || | |
3696 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) || | |
3697 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) || | |
3698 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) || | |
3699 | check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) { | |
3a9c6a49 | 3700 | pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file); |
7880b72e | 3701 | rc = -EINVAL; |
3702 | goto err_release_firmware; | |
57579f76 | 3703 | } |
5ee1c326 BB |
3704 | if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) || |
3705 | check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) || | |
3706 | check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) { | |
3a9c6a49 | 3707 | pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file); |
7880b72e | 3708 | rc = -EINVAL; |
3709 | goto err_release_firmware; | |
57579f76 | 3710 | } |
7880b72e | 3711 | out: |
3712 | return rc; | |
57579f76 | 3713 | |
7880b72e | 3714 | err_release_firmware: |
3715 | release_firmware(bp->rv2p_firmware); | |
3716 | bp->rv2p_firmware = NULL; | |
3717 | err_release_mips_firmware: | |
3718 | release_firmware(bp->mips_firmware); | |
3719 | goto out; | |
3720 | } | |
3721 | ||
3722 | static int bnx2_request_firmware(struct bnx2 *bp) | |
3723 | { | |
3724 | return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp); | |
57579f76 MC |
3725 | } |
3726 | ||
3727 | static u32 | |
3728 | rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code) | |
3729 | { | |
3730 | switch (idx) { | |
3731 | case RV2P_P1_FIXUP_PAGE_SIZE_IDX: | |
3732 | rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK; | |
3733 | rv2p_code |= RV2P_BD_PAGE_SIZE; | |
3734 | break; | |
3735 | } | |
3736 | return rv2p_code; | |
3737 | } | |
3738 | ||
3739 | static int | |
3740 | load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc, | |
3741 | const struct bnx2_rv2p_fw_file_entry *fw_entry) | |
3742 | { | |
3743 | u32 rv2p_code_len, file_offset; | |
3744 | __be32 *rv2p_code; | |
b6016b76 | 3745 | int i; |
57579f76 MC |
3746 | u32 val, cmd, addr; |
3747 | ||
3748 | rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len); | |
3749 | file_offset = be32_to_cpu(fw_entry->rv2p.offset); | |
3750 | ||
3751 | rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); | |
b6016b76 | 3752 | |
57579f76 MC |
3753 | if (rv2p_proc == RV2P_PROC1) { |
3754 | cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR; | |
3755 | addr = BNX2_RV2P_PROC1_ADDR_CMD; | |
3756 | } else { | |
3757 | cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR; | |
3758 | addr = BNX2_RV2P_PROC2_ADDR_CMD; | |
d25be1d3 | 3759 | } |
b6016b76 MC |
3760 | |
3761 | for (i = 0; i < rv2p_code_len; i += 8) { | |
e503e066 | 3762 | BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code)); |
b6016b76 | 3763 | rv2p_code++; |
e503e066 | 3764 | BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code)); |
b6016b76 MC |
3765 | rv2p_code++; |
3766 | ||
57579f76 | 3767 | val = (i / 8) | cmd; |
e503e066 | 3768 | BNX2_WR(bp, addr, val); |
57579f76 MC |
3769 | } |
3770 | ||
3771 | rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); | |
3772 | for (i = 0; i < 8; i++) { | |
3773 | u32 loc, code; | |
3774 | ||
3775 | loc = be32_to_cpu(fw_entry->fixup[i]); | |
3776 | if (loc && ((loc * 4) < rv2p_code_len)) { | |
3777 | code = be32_to_cpu(*(rv2p_code + loc - 1)); | |
e503e066 | 3778 | BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code); |
57579f76 MC |
3779 | code = be32_to_cpu(*(rv2p_code + loc)); |
3780 | code = rv2p_fw_fixup(rv2p_proc, i, loc, code); | |
e503e066 | 3781 | BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code); |
57579f76 MC |
3782 | |
3783 | val = (loc / 2) | cmd; | |
e503e066 | 3784 | BNX2_WR(bp, addr, val); |
b6016b76 MC |
3785 | } |
3786 | } | |
3787 | ||
3788 | /* Reset the processor, un-stall is done later. */ | |
3789 | if (rv2p_proc == RV2P_PROC1) { | |
e503e066 | 3790 | BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET); |
b6016b76 MC |
3791 | } |
3792 | else { | |
e503e066 | 3793 | BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); |
b6016b76 | 3794 | } |
57579f76 MC |
3795 | |
3796 | return 0; | |
b6016b76 MC |
3797 | } |
3798 | ||
af3ee519 | 3799 | static int |
57579f76 MC |
3800 | load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, |
3801 | const struct bnx2_mips_fw_file_entry *fw_entry) | |
b6016b76 | 3802 | { |
57579f76 MC |
3803 | u32 addr, len, file_offset; |
3804 | __be32 *data; | |
b6016b76 MC |
3805 | u32 offset; |
3806 | u32 val; | |
3807 | ||
3808 | /* Halt the CPU. */ | |
2726d6e1 | 3809 | val = bnx2_reg_rd_ind(bp, cpu_reg->mode); |
b6016b76 | 3810 | val |= cpu_reg->mode_value_halt; |
2726d6e1 MC |
3811 | bnx2_reg_wr_ind(bp, cpu_reg->mode, val); |
3812 | bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); | |
b6016b76 MC |
3813 | |
3814 | /* Load the Text area. */ | |
57579f76 MC |
3815 | addr = be32_to_cpu(fw_entry->text.addr); |
3816 | len = be32_to_cpu(fw_entry->text.len); | |
3817 | file_offset = be32_to_cpu(fw_entry->text.offset); | |
3818 | data = (__be32 *)(bp->mips_firmware->data + file_offset); | |
ea1f8d5c | 3819 | |
57579f76 MC |
3820 | offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); |
3821 | if (len) { | |
b6016b76 MC |
3822 | int j; |
3823 | ||
57579f76 MC |
3824 | for (j = 0; j < (len / 4); j++, offset += 4) |
3825 | bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); | |
b6016b76 MC |
3826 | } |
3827 | ||
57579f76 MC |
3828 | /* Load the Data area. */ |
3829 | addr = be32_to_cpu(fw_entry->data.addr); | |
3830 | len = be32_to_cpu(fw_entry->data.len); | |
3831 | file_offset = be32_to_cpu(fw_entry->data.offset); | |
3832 | data = (__be32 *)(bp->mips_firmware->data + file_offset); | |
b6016b76 | 3833 | |
57579f76 MC |
3834 | offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); |
3835 | if (len) { | |
b6016b76 MC |
3836 | int j; |
3837 | ||
57579f76 MC |
3838 | for (j = 0; j < (len / 4); j++, offset += 4) |
3839 | bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); | |
b6016b76 MC |
3840 | } |
3841 | ||
3842 | /* Load the Read-Only area. */ | |
57579f76 MC |
3843 | addr = be32_to_cpu(fw_entry->rodata.addr); |
3844 | len = be32_to_cpu(fw_entry->rodata.len); | |
3845 | file_offset = be32_to_cpu(fw_entry->rodata.offset); | |
3846 | data = (__be32 *)(bp->mips_firmware->data + file_offset); | |
3847 | ||
3848 | offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); | |
3849 | if (len) { | |
b6016b76 MC |
3850 | int j; |
3851 | ||
57579f76 MC |
3852 | for (j = 0; j < (len / 4); j++, offset += 4) |
3853 | bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); | |
b6016b76 MC |
3854 | } |
3855 | ||
3856 | /* Clear the pre-fetch instruction. */ | |
2726d6e1 | 3857 | bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); |
57579f76 MC |
3858 | |
3859 | val = be32_to_cpu(fw_entry->start_addr); | |
3860 | bnx2_reg_wr_ind(bp, cpu_reg->pc, val); | |
b6016b76 MC |
3861 | |
3862 | /* Start the CPU. */ | |
2726d6e1 | 3863 | val = bnx2_reg_rd_ind(bp, cpu_reg->mode); |
b6016b76 | 3864 | val &= ~cpu_reg->mode_value_halt; |
2726d6e1 MC |
3865 | bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); |
3866 | bnx2_reg_wr_ind(bp, cpu_reg->mode, val); | |
af3ee519 MC |
3867 | |
3868 | return 0; | |
b6016b76 MC |
3869 | } |
3870 | ||
fba9fe91 | 3871 | static int |
b6016b76 MC |
3872 | bnx2_init_cpus(struct bnx2 *bp) |
3873 | { | |
57579f76 MC |
3874 | const struct bnx2_mips_fw_file *mips_fw = |
3875 | (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; | |
3876 | const struct bnx2_rv2p_fw_file *rv2p_fw = | |
3877 | (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; | |
3878 | int rc; | |
b6016b76 MC |
3879 | |
3880 | /* Initialize the RV2P processor. */ | |
57579f76 MC |
3881 | load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1); |
3882 | load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2); | |
b6016b76 MC |
3883 | |
3884 | /* Initialize the RX Processor. */ | |
57579f76 | 3885 | rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp); |
fba9fe91 MC |
3886 | if (rc) |
3887 | goto init_cpu_err; | |
3888 | ||
b6016b76 | 3889 | /* Initialize the TX Processor. */ |
57579f76 | 3890 | rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp); |
fba9fe91 MC |
3891 | if (rc) |
3892 | goto init_cpu_err; | |
3893 | ||
b6016b76 | 3894 | /* Initialize the TX Patch-up Processor. */ |
57579f76 | 3895 | rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat); |
fba9fe91 MC |
3896 | if (rc) |
3897 | goto init_cpu_err; | |
3898 | ||
b6016b76 | 3899 | /* Initialize the Completion Processor. */ |
57579f76 | 3900 | rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com); |
fba9fe91 MC |
3901 | if (rc) |
3902 | goto init_cpu_err; | |
3903 | ||
d43584c8 | 3904 | /* Initialize the Command Processor. */ |
57579f76 | 3905 | rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp); |
b6016b76 | 3906 | |
fba9fe91 | 3907 | init_cpu_err: |
fba9fe91 | 3908 | return rc; |
b6016b76 MC |
3909 | } |
3910 | ||
3911 | static int | |
829ca9a3 | 3912 | bnx2_set_power_state(struct bnx2 *bp, pci_power_t state) |
b6016b76 | 3913 | { |
b6016b76 | 3914 | switch (state) { |
829ca9a3 | 3915 | case PCI_D0: { |
b6016b76 MC |
3916 | u32 val; |
3917 | ||
6d5e85c7 MC |
3918 | pci_enable_wake(bp->pdev, PCI_D0, false); |
3919 | pci_set_power_state(bp->pdev, PCI_D0); | |
b6016b76 | 3920 | |
e503e066 | 3921 | val = BNX2_RD(bp, BNX2_EMAC_MODE); |
b6016b76 MC |
3922 | val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; |
3923 | val &= ~BNX2_EMAC_MODE_MPKT; | |
e503e066 | 3924 | BNX2_WR(bp, BNX2_EMAC_MODE, val); |
b6016b76 | 3925 | |
e503e066 | 3926 | val = BNX2_RD(bp, BNX2_RPM_CONFIG); |
b6016b76 | 3927 | val &= ~BNX2_RPM_CONFIG_ACPI_ENA; |
e503e066 | 3928 | BNX2_WR(bp, BNX2_RPM_CONFIG, val); |
b6016b76 MC |
3929 | break; |
3930 | } | |
829ca9a3 | 3931 | case PCI_D3hot: { |
b6016b76 MC |
3932 | int i; |
3933 | u32 val, wol_msg; | |
3934 | ||
3935 | if (bp->wol) { | |
3936 | u32 advertising; | |
3937 | u8 autoneg; | |
3938 | ||
3939 | autoneg = bp->autoneg; | |
3940 | advertising = bp->advertising; | |
3941 | ||
239cd343 MC |
3942 | if (bp->phy_port == PORT_TP) { |
3943 | bp->autoneg = AUTONEG_SPEED; | |
3944 | bp->advertising = ADVERTISED_10baseT_Half | | |
3945 | ADVERTISED_10baseT_Full | | |
3946 | ADVERTISED_100baseT_Half | | |
3947 | ADVERTISED_100baseT_Full | | |
3948 | ADVERTISED_Autoneg; | |
3949 | } | |
b6016b76 | 3950 | |
239cd343 MC |
3951 | spin_lock_bh(&bp->phy_lock); |
3952 | bnx2_setup_phy(bp, bp->phy_port); | |
3953 | spin_unlock_bh(&bp->phy_lock); | |
b6016b76 MC |
3954 | |
3955 | bp->autoneg = autoneg; | |
3956 | bp->advertising = advertising; | |
3957 | ||
5fcaed01 | 3958 | bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); |
b6016b76 | 3959 | |
e503e066 | 3960 | val = BNX2_RD(bp, BNX2_EMAC_MODE); |
b6016b76 MC |
3961 | |
3962 | /* Enable port mode. */ | |
3963 | val &= ~BNX2_EMAC_MODE_PORT; | |
239cd343 | 3964 | val |= BNX2_EMAC_MODE_MPKT_RCVD | |
b6016b76 | 3965 | BNX2_EMAC_MODE_ACPI_RCVD | |
b6016b76 | 3966 | BNX2_EMAC_MODE_MPKT; |
239cd343 MC |
3967 | if (bp->phy_port == PORT_TP) |
3968 | val |= BNX2_EMAC_MODE_PORT_MII; | |
3969 | else { | |
3970 | val |= BNX2_EMAC_MODE_PORT_GMII; | |
3971 | if (bp->line_speed == SPEED_2500) | |
3972 | val |= BNX2_EMAC_MODE_25G_MODE; | |
3973 | } | |
b6016b76 | 3974 | |
e503e066 | 3975 | BNX2_WR(bp, BNX2_EMAC_MODE, val); |
b6016b76 MC |
3976 | |
3977 | /* receive all multicast */ | |
3978 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | |
e503e066 MC |
3979 | BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), |
3980 | 0xffffffff); | |
b6016b76 | 3981 | } |
e503e066 MC |
3982 | BNX2_WR(bp, BNX2_EMAC_RX_MODE, |
3983 | BNX2_EMAC_RX_MODE_SORT_MODE); | |
b6016b76 MC |
3984 | |
3985 | val = 1 | BNX2_RPM_SORT_USER0_BC_EN | | |
3986 | BNX2_RPM_SORT_USER0_MC_EN; | |
e503e066 MC |
3987 | BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); |
3988 | BNX2_WR(bp, BNX2_RPM_SORT_USER0, val); | |
3989 | BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | | |
3990 | BNX2_RPM_SORT_USER0_ENA); | |
b6016b76 MC |
3991 | |
3992 | /* Need to enable EMAC and RPM for WOL. */ | |
e503e066 MC |
3993 | BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, |
3994 | BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE | | |
3995 | BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE | | |
3996 | BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE); | |
b6016b76 | 3997 | |
e503e066 | 3998 | val = BNX2_RD(bp, BNX2_RPM_CONFIG); |
b6016b76 | 3999 | val &= ~BNX2_RPM_CONFIG_ACPI_ENA; |
e503e066 | 4000 | BNX2_WR(bp, BNX2_RPM_CONFIG, val); |
b6016b76 MC |
4001 | |
4002 | wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | |
4003 | } | |
4004 | else { | |
4005 | wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | |
4006 | } | |
4007 | ||
f86e82fb | 4008 | if (!(bp->flags & BNX2_FLAG_NO_WOL)) |
a2f13890 MC |
4009 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, |
4010 | 1, 0); | |
b6016b76 | 4011 | |
6d5e85c7 | 4012 | pci_wake_from_d3(bp->pdev, bp->wol); |
4ce45e02 MC |
4013 | if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || |
4014 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) { | |
b6016b76 MC |
4015 | |
4016 | if (bp->wol) | |
6d5e85c7 MC |
4017 | pci_set_power_state(bp->pdev, PCI_D3hot); |
4018 | } else { | |
4019 | pci_set_power_state(bp->pdev, PCI_D3hot); | |
b6016b76 | 4020 | } |
b6016b76 MC |
4021 | |
4022 | /* No more memory access after this point until | |
4023 | * device is brought back to D0. | |
4024 | */ | |
b6016b76 MC |
4025 | break; |
4026 | } | |
4027 | default: | |
4028 | return -EINVAL; | |
4029 | } | |
4030 | return 0; | |
4031 | } | |
4032 | ||
4033 | static int | |
4034 | bnx2_acquire_nvram_lock(struct bnx2 *bp) | |
4035 | { | |
4036 | u32 val; | |
4037 | int j; | |
4038 | ||
4039 | /* Request access to the flash interface. */ | |
e503e066 | 4040 | BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2); |
b6016b76 | 4041 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { |
e503e066 | 4042 | val = BNX2_RD(bp, BNX2_NVM_SW_ARB); |
b6016b76 MC |
4043 | if (val & BNX2_NVM_SW_ARB_ARB_ARB2) |
4044 | break; | |
4045 | ||
4046 | udelay(5); | |
4047 | } | |
4048 | ||
4049 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4050 | return -EBUSY; | |
4051 | ||
4052 | return 0; | |
4053 | } | |
4054 | ||
4055 | static int | |
4056 | bnx2_release_nvram_lock(struct bnx2 *bp) | |
4057 | { | |
4058 | int j; | |
4059 | u32 val; | |
4060 | ||
4061 | /* Relinquish nvram interface. */ | |
e503e066 | 4062 | BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2); |
b6016b76 MC |
4063 | |
4064 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
e503e066 | 4065 | val = BNX2_RD(bp, BNX2_NVM_SW_ARB); |
b6016b76 MC |
4066 | if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2)) |
4067 | break; | |
4068 | ||
4069 | udelay(5); | |
4070 | } | |
4071 | ||
4072 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4073 | return -EBUSY; | |
4074 | ||
4075 | return 0; | |
4076 | } | |
4077 | ||
4078 | ||
4079 | static int | |
4080 | bnx2_enable_nvram_write(struct bnx2 *bp) | |
4081 | { | |
4082 | u32 val; | |
4083 | ||
e503e066 MC |
4084 | val = BNX2_RD(bp, BNX2_MISC_CFG); |
4085 | BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI); | |
b6016b76 | 4086 | |
e30372c9 | 4087 | if (bp->flash_info->flags & BNX2_NV_WREN) { |
b6016b76 MC |
4088 | int j; |
4089 | ||
e503e066 MC |
4090 | BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); |
4091 | BNX2_WR(bp, BNX2_NVM_COMMAND, | |
4092 | BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT); | |
b6016b76 MC |
4093 | |
4094 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4095 | udelay(5); | |
4096 | ||
e503e066 | 4097 | val = BNX2_RD(bp, BNX2_NVM_COMMAND); |
b6016b76 MC |
4098 | if (val & BNX2_NVM_COMMAND_DONE) |
4099 | break; | |
4100 | } | |
4101 | ||
4102 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4103 | return -EBUSY; | |
4104 | } | |
4105 | return 0; | |
4106 | } | |
4107 | ||
4108 | static void | |
4109 | bnx2_disable_nvram_write(struct bnx2 *bp) | |
4110 | { | |
4111 | u32 val; | |
4112 | ||
e503e066 MC |
4113 | val = BNX2_RD(bp, BNX2_MISC_CFG); |
4114 | BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN); | |
b6016b76 MC |
4115 | } |
4116 | ||
4117 | ||
4118 | static void | |
4119 | bnx2_enable_nvram_access(struct bnx2 *bp) | |
4120 | { | |
4121 | u32 val; | |
4122 | ||
e503e066 | 4123 | val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); |
b6016b76 | 4124 | /* Enable both bits, even on read. */ |
e503e066 MC |
4125 | BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE, |
4126 | val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); | |
b6016b76 MC |
4127 | } |
4128 | ||
4129 | static void | |
4130 | bnx2_disable_nvram_access(struct bnx2 *bp) | |
4131 | { | |
4132 | u32 val; | |
4133 | ||
e503e066 | 4134 | val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); |
b6016b76 | 4135 | /* Disable both bits, even after read. */ |
e503e066 | 4136 | BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE, |
b6016b76 MC |
4137 | val & ~(BNX2_NVM_ACCESS_ENABLE_EN | |
4138 | BNX2_NVM_ACCESS_ENABLE_WR_EN)); | |
4139 | } | |
4140 | ||
4141 | static int | |
4142 | bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset) | |
4143 | { | |
4144 | u32 cmd; | |
4145 | int j; | |
4146 | ||
e30372c9 | 4147 | if (bp->flash_info->flags & BNX2_NV_BUFFERED) |
b6016b76 MC |
4148 | /* Buffered flash, no erase needed */ |
4149 | return 0; | |
4150 | ||
4151 | /* Build an erase command */ | |
4152 | cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR | | |
4153 | BNX2_NVM_COMMAND_DOIT; | |
4154 | ||
4155 | /* Need to clear DONE bit separately. */ | |
e503e066 | 4156 | BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); |
b6016b76 MC |
4157 | |
4158 | /* Address of the NVRAM to read from. */ | |
e503e066 | 4159 | BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); |
b6016b76 MC |
4160 | |
4161 | /* Issue an erase command. */ | |
e503e066 | 4162 | BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); |
b6016b76 MC |
4163 | |
4164 | /* Wait for completion. */ | |
4165 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4166 | u32 val; | |
4167 | ||
4168 | udelay(5); | |
4169 | ||
e503e066 | 4170 | val = BNX2_RD(bp, BNX2_NVM_COMMAND); |
b6016b76 MC |
4171 | if (val & BNX2_NVM_COMMAND_DONE) |
4172 | break; | |
4173 | } | |
4174 | ||
4175 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4176 | return -EBUSY; | |
4177 | ||
4178 | return 0; | |
4179 | } | |
4180 | ||
4181 | static int | |
4182 | bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) | |
4183 | { | |
4184 | u32 cmd; | |
4185 | int j; | |
4186 | ||
4187 | /* Build the command word. */ | |
4188 | cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags; | |
4189 | ||
e30372c9 MC |
4190 | /* Calculate an offset of a buffered flash, not needed for 5709. */ |
4191 | if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { | |
b6016b76 MC |
4192 | offset = ((offset / bp->flash_info->page_size) << |
4193 | bp->flash_info->page_bits) + | |
4194 | (offset % bp->flash_info->page_size); | |
4195 | } | |
4196 | ||
4197 | /* Need to clear DONE bit separately. */ | |
e503e066 | 4198 | BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); |
b6016b76 MC |
4199 | |
4200 | /* Address of the NVRAM to read from. */ | |
e503e066 | 4201 | BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); |
b6016b76 MC |
4202 | |
4203 | /* Issue a read command. */ | |
e503e066 | 4204 | BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); |
b6016b76 MC |
4205 | |
4206 | /* Wait for completion. */ | |
4207 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4208 | u32 val; | |
4209 | ||
4210 | udelay(5); | |
4211 | ||
e503e066 | 4212 | val = BNX2_RD(bp, BNX2_NVM_COMMAND); |
b6016b76 | 4213 | if (val & BNX2_NVM_COMMAND_DONE) { |
e503e066 | 4214 | __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ)); |
b491edd5 | 4215 | memcpy(ret_val, &v, 4); |
b6016b76 MC |
4216 | break; |
4217 | } | |
4218 | } | |
4219 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4220 | return -EBUSY; | |
4221 | ||
4222 | return 0; | |
4223 | } | |
4224 | ||
4225 | ||
4226 | static int | |
4227 | bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) | |
4228 | { | |
b491edd5 AV |
4229 | u32 cmd; |
4230 | __be32 val32; | |
b6016b76 MC |
4231 | int j; |
4232 | ||
4233 | /* Build the command word. */ | |
4234 | cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags; | |
4235 | ||
e30372c9 MC |
4236 | /* Calculate an offset of a buffered flash, not needed for 5709. */ |
4237 | if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { | |
b6016b76 MC |
4238 | offset = ((offset / bp->flash_info->page_size) << |
4239 | bp->flash_info->page_bits) + | |
4240 | (offset % bp->flash_info->page_size); | |
4241 | } | |
4242 | ||
4243 | /* Need to clear DONE bit separately. */ | |
e503e066 | 4244 | BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); |
b6016b76 MC |
4245 | |
4246 | memcpy(&val32, val, 4); | |
b6016b76 MC |
4247 | |
4248 | /* Write the data. */ | |
e503e066 | 4249 | BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32)); |
b6016b76 MC |
4250 | |
4251 | /* Address of the NVRAM to write to. */ | |
e503e066 | 4252 | BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); |
b6016b76 MC |
4253 | |
4254 | /* Issue the write command. */ | |
e503e066 | 4255 | BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); |
b6016b76 MC |
4256 | |
4257 | /* Wait for completion. */ | |
4258 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | |
4259 | udelay(5); | |
4260 | ||
e503e066 | 4261 | if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE) |
b6016b76 MC |
4262 | break; |
4263 | } | |
4264 | if (j >= NVRAM_TIMEOUT_COUNT) | |
4265 | return -EBUSY; | |
4266 | ||
4267 | return 0; | |
4268 | } | |
4269 | ||
4270 | static int | |
4271 | bnx2_init_nvram(struct bnx2 *bp) | |
4272 | { | |
4273 | u32 val; | |
e30372c9 | 4274 | int j, entry_count, rc = 0; |
0ced9d01 | 4275 | const struct flash_spec *flash; |
b6016b76 | 4276 | |
4ce45e02 | 4277 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
e30372c9 MC |
4278 | bp->flash_info = &flash_5709; |
4279 | goto get_flash_size; | |
4280 | } | |
4281 | ||
b6016b76 | 4282 | /* Determine the selected interface. */ |
e503e066 | 4283 | val = BNX2_RD(bp, BNX2_NVM_CFG1); |
b6016b76 | 4284 | |
ff8ac609 | 4285 | entry_count = ARRAY_SIZE(flash_table); |
b6016b76 | 4286 | |
b6016b76 MC |
4287 | if (val & 0x40000000) { |
4288 | ||
4289 | /* Flash interface has been reconfigured */ | |
4290 | for (j = 0, flash = &flash_table[0]; j < entry_count; | |
37137709 MC |
4291 | j++, flash++) { |
4292 | if ((val & FLASH_BACKUP_STRAP_MASK) == | |
4293 | (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { | |
b6016b76 MC |
4294 | bp->flash_info = flash; |
4295 | break; | |
4296 | } | |
4297 | } | |
4298 | } | |
4299 | else { | |
37137709 | 4300 | u32 mask; |
b6016b76 MC |
4301 | /* Not yet been reconfigured */ |
4302 | ||
37137709 MC |
4303 | if (val & (1 << 23)) |
4304 | mask = FLASH_BACKUP_STRAP_MASK; | |
4305 | else | |
4306 | mask = FLASH_STRAP_MASK; | |
4307 | ||
b6016b76 MC |
4308 | for (j = 0, flash = &flash_table[0]; j < entry_count; |
4309 | j++, flash++) { | |
4310 | ||
37137709 | 4311 | if ((val & mask) == (flash->strapping & mask)) { |
b6016b76 MC |
4312 | bp->flash_info = flash; |
4313 | ||
4314 | /* Request access to the flash interface. */ | |
4315 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
4316 | return rc; | |
4317 | ||
4318 | /* Enable access to flash interface */ | |
4319 | bnx2_enable_nvram_access(bp); | |
4320 | ||
4321 | /* Reconfigure the flash interface */ | |
e503e066 MC |
4322 | BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1); |
4323 | BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2); | |
4324 | BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3); | |
4325 | BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1); | |
b6016b76 MC |
4326 | |
4327 | /* Disable access to flash interface */ | |
4328 | bnx2_disable_nvram_access(bp); | |
4329 | bnx2_release_nvram_lock(bp); | |
4330 | ||
4331 | break; | |
4332 | } | |
4333 | } | |
4334 | } /* if (val & 0x40000000) */ | |
4335 | ||
4336 | if (j == entry_count) { | |
4337 | bp->flash_info = NULL; | |
3a9c6a49 | 4338 | pr_alert("Unknown flash/EEPROM type\n"); |
1122db71 | 4339 | return -ENODEV; |
b6016b76 MC |
4340 | } |
4341 | ||
e30372c9 | 4342 | get_flash_size: |
2726d6e1 | 4343 | val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2); |
1122db71 MC |
4344 | val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK; |
4345 | if (val) | |
4346 | bp->flash_size = val; | |
4347 | else | |
4348 | bp->flash_size = bp->flash_info->total_size; | |
4349 | ||
b6016b76 MC |
4350 | return rc; |
4351 | } | |
4352 | ||
4353 | static int | |
4354 | bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf, | |
4355 | int buf_size) | |
4356 | { | |
4357 | int rc = 0; | |
4358 | u32 cmd_flags, offset32, len32, extra; | |
4359 | ||
4360 | if (buf_size == 0) | |
4361 | return 0; | |
4362 | ||
4363 | /* Request access to the flash interface. */ | |
4364 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
4365 | return rc; | |
4366 | ||
4367 | /* Enable access to flash interface */ | |
4368 | bnx2_enable_nvram_access(bp); | |
4369 | ||
4370 | len32 = buf_size; | |
4371 | offset32 = offset; | |
4372 | extra = 0; | |
4373 | ||
4374 | cmd_flags = 0; | |
4375 | ||
4376 | if (offset32 & 3) { | |
4377 | u8 buf[4]; | |
4378 | u32 pre_len; | |
4379 | ||
4380 | offset32 &= ~3; | |
4381 | pre_len = 4 - (offset & 3); | |
4382 | ||
4383 | if (pre_len >= len32) { | |
4384 | pre_len = len32; | |
4385 | cmd_flags = BNX2_NVM_COMMAND_FIRST | | |
4386 | BNX2_NVM_COMMAND_LAST; | |
4387 | } | |
4388 | else { | |
4389 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
4390 | } | |
4391 | ||
4392 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
4393 | ||
4394 | if (rc) | |
4395 | return rc; | |
4396 | ||
4397 | memcpy(ret_buf, buf + (offset & 3), pre_len); | |
4398 | ||
4399 | offset32 += 4; | |
4400 | ret_buf += pre_len; | |
4401 | len32 -= pre_len; | |
4402 | } | |
4403 | if (len32 & 3) { | |
4404 | extra = 4 - (len32 & 3); | |
4405 | len32 = (len32 + 4) & ~3; | |
4406 | } | |
4407 | ||
4408 | if (len32 == 4) { | |
4409 | u8 buf[4]; | |
4410 | ||
4411 | if (cmd_flags) | |
4412 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
4413 | else | |
4414 | cmd_flags = BNX2_NVM_COMMAND_FIRST | | |
4415 | BNX2_NVM_COMMAND_LAST; | |
4416 | ||
4417 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
4418 | ||
4419 | memcpy(ret_buf, buf, 4 - extra); | |
4420 | } | |
4421 | else if (len32 > 0) { | |
4422 | u8 buf[4]; | |
4423 | ||
4424 | /* Read the first word. */ | |
4425 | if (cmd_flags) | |
4426 | cmd_flags = 0; | |
4427 | else | |
4428 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
4429 | ||
4430 | rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags); | |
4431 | ||
4432 | /* Advance to the next dword. */ | |
4433 | offset32 += 4; | |
4434 | ret_buf += 4; | |
4435 | len32 -= 4; | |
4436 | ||
4437 | while (len32 > 4 && rc == 0) { | |
4438 | rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0); | |
4439 | ||
4440 | /* Advance to the next dword. */ | |
4441 | offset32 += 4; | |
4442 | ret_buf += 4; | |
4443 | len32 -= 4; | |
4444 | } | |
4445 | ||
4446 | if (rc) | |
4447 | return rc; | |
4448 | ||
4449 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
4450 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | |
4451 | ||
4452 | memcpy(ret_buf, buf, 4 - extra); | |
4453 | } | |
4454 | ||
4455 | /* Disable access to flash interface */ | |
4456 | bnx2_disable_nvram_access(bp); | |
4457 | ||
4458 | bnx2_release_nvram_lock(bp); | |
4459 | ||
4460 | return rc; | |
4461 | } | |
4462 | ||
4463 | static int | |
4464 | bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, | |
4465 | int buf_size) | |
4466 | { | |
4467 | u32 written, offset32, len32; | |
e6be763f | 4468 | u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL; |
b6016b76 MC |
4469 | int rc = 0; |
4470 | int align_start, align_end; | |
4471 | ||
4472 | buf = data_buf; | |
4473 | offset32 = offset; | |
4474 | len32 = buf_size; | |
4475 | align_start = align_end = 0; | |
4476 | ||
4477 | if ((align_start = (offset32 & 3))) { | |
4478 | offset32 &= ~3; | |
c873879c MC |
4479 | len32 += align_start; |
4480 | if (len32 < 4) | |
4481 | len32 = 4; | |
b6016b76 MC |
4482 | if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) |
4483 | return rc; | |
4484 | } | |
4485 | ||
4486 | if (len32 & 3) { | |
c873879c MC |
4487 | align_end = 4 - (len32 & 3); |
4488 | len32 += align_end; | |
4489 | if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4))) | |
4490 | return rc; | |
b6016b76 MC |
4491 | } |
4492 | ||
4493 | if (align_start || align_end) { | |
e6be763f MC |
4494 | align_buf = kmalloc(len32, GFP_KERNEL); |
4495 | if (align_buf == NULL) | |
b6016b76 MC |
4496 | return -ENOMEM; |
4497 | if (align_start) { | |
e6be763f | 4498 | memcpy(align_buf, start, 4); |
b6016b76 MC |
4499 | } |
4500 | if (align_end) { | |
e6be763f | 4501 | memcpy(align_buf + len32 - 4, end, 4); |
b6016b76 | 4502 | } |
e6be763f MC |
4503 | memcpy(align_buf + align_start, data_buf, buf_size); |
4504 | buf = align_buf; | |
b6016b76 MC |
4505 | } |
4506 | ||
e30372c9 | 4507 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
ae181bc4 MC |
4508 | flash_buffer = kmalloc(264, GFP_KERNEL); |
4509 | if (flash_buffer == NULL) { | |
4510 | rc = -ENOMEM; | |
4511 | goto nvram_write_end; | |
4512 | } | |
4513 | } | |
4514 | ||
b6016b76 MC |
4515 | written = 0; |
4516 | while ((written < len32) && (rc == 0)) { | |
4517 | u32 page_start, page_end, data_start, data_end; | |
4518 | u32 addr, cmd_flags; | |
4519 | int i; | |
b6016b76 MC |
4520 | |
4521 | /* Find the page_start addr */ | |
4522 | page_start = offset32 + written; | |
4523 | page_start -= (page_start % bp->flash_info->page_size); | |
4524 | /* Find the page_end addr */ | |
4525 | page_end = page_start + bp->flash_info->page_size; | |
4526 | /* Find the data_start addr */ | |
4527 | data_start = (written == 0) ? offset32 : page_start; | |
4528 | /* Find the data_end addr */ | |
6aa20a22 | 4529 | data_end = (page_end > offset32 + len32) ? |
b6016b76 MC |
4530 | (offset32 + len32) : page_end; |
4531 | ||
4532 | /* Request access to the flash interface. */ | |
4533 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | |
4534 | goto nvram_write_end; | |
4535 | ||
4536 | /* Enable access to flash interface */ | |
4537 | bnx2_enable_nvram_access(bp); | |
4538 | ||
4539 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | |
e30372c9 | 4540 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
b6016b76 MC |
4541 | int j; |
4542 | ||
4543 | /* Read the whole page into the buffer | |
4544 | * (non-buffer flash only) */ | |
4545 | for (j = 0; j < bp->flash_info->page_size; j += 4) { | |
4546 | if (j == (bp->flash_info->page_size - 4)) { | |
4547 | cmd_flags |= BNX2_NVM_COMMAND_LAST; | |
4548 | } | |
4549 | rc = bnx2_nvram_read_dword(bp, | |
6aa20a22 JG |
4550 | page_start + j, |
4551 | &flash_buffer[j], | |
b6016b76 MC |
4552 | cmd_flags); |
4553 | ||
4554 | if (rc) | |
4555 | goto nvram_write_end; | |
4556 | ||
4557 | cmd_flags = 0; | |
4558 | } | |
4559 | } | |
4560 | ||
4561 | /* Enable writes to flash interface (unlock write-protect) */ | |
4562 | if ((rc = bnx2_enable_nvram_write(bp)) != 0) | |
4563 | goto nvram_write_end; | |
4564 | ||
b6016b76 MC |
4565 | /* Loop to write back the buffer data from page_start to |
4566 | * data_start */ | |
4567 | i = 0; | |
e30372c9 | 4568 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
c873879c MC |
4569 | /* Erase the page */ |
4570 | if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) | |
4571 | goto nvram_write_end; | |
4572 | ||
4573 | /* Re-enable the write again for the actual write */ | |
4574 | bnx2_enable_nvram_write(bp); | |
4575 | ||
b6016b76 MC |
4576 | for (addr = page_start; addr < data_start; |
4577 | addr += 4, i += 4) { | |
6aa20a22 | 4578 | |
b6016b76 MC |
4579 | rc = bnx2_nvram_write_dword(bp, addr, |
4580 | &flash_buffer[i], cmd_flags); | |
4581 | ||
4582 | if (rc != 0) | |
4583 | goto nvram_write_end; | |
4584 | ||
4585 | cmd_flags = 0; | |
4586 | } | |
4587 | } | |
4588 | ||
4589 | /* Loop to write the new data from data_start to data_end */ | |
bae25761 | 4590 | for (addr = data_start; addr < data_end; addr += 4, i += 4) { |
b6016b76 | 4591 | if ((addr == page_end - 4) || |
e30372c9 | 4592 | ((bp->flash_info->flags & BNX2_NV_BUFFERED) && |
b6016b76 MC |
4593 | (addr == data_end - 4))) { |
4594 | ||
4595 | cmd_flags |= BNX2_NVM_COMMAND_LAST; | |
4596 | } | |
4597 | rc = bnx2_nvram_write_dword(bp, addr, buf, | |
4598 | cmd_flags); | |
4599 | ||
4600 | if (rc != 0) | |
4601 | goto nvram_write_end; | |
4602 | ||
4603 | cmd_flags = 0; | |
4604 | buf += 4; | |
4605 | } | |
4606 | ||
4607 | /* Loop to write back the buffer data from data_end | |
4608 | * to page_end */ | |
e30372c9 | 4609 | if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { |
b6016b76 MC |
4610 | for (addr = data_end; addr < page_end; |
4611 | addr += 4, i += 4) { | |
6aa20a22 | 4612 | |
b6016b76 MC |
4613 | if (addr == page_end-4) { |
4614 | cmd_flags = BNX2_NVM_COMMAND_LAST; | |
4615 | } | |
4616 | rc = bnx2_nvram_write_dword(bp, addr, | |
4617 | &flash_buffer[i], cmd_flags); | |
4618 | ||
4619 | if (rc != 0) | |
4620 | goto nvram_write_end; | |
4621 | ||
4622 | cmd_flags = 0; | |
4623 | } | |
4624 | } | |
4625 | ||
4626 | /* Disable writes to flash interface (lock write-protect) */ | |
4627 | bnx2_disable_nvram_write(bp); | |
4628 | ||
4629 | /* Disable access to flash interface */ | |
4630 | bnx2_disable_nvram_access(bp); | |
4631 | bnx2_release_nvram_lock(bp); | |
4632 | ||
4633 | /* Increment written */ | |
4634 | written += data_end - data_start; | |
4635 | } | |
4636 | ||
4637 | nvram_write_end: | |
e6be763f MC |
4638 | kfree(flash_buffer); |
4639 | kfree(align_buf); | |
b6016b76 MC |
4640 | return rc; |
4641 | } | |
4642 | ||
0d8a6571 | 4643 | static void |
7c62e83b | 4644 | bnx2_init_fw_cap(struct bnx2 *bp) |
0d8a6571 | 4645 | { |
7c62e83b | 4646 | u32 val, sig = 0; |
0d8a6571 | 4647 | |
583c28e5 | 4648 | bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP; |
7c62e83b MC |
4649 | bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN; |
4650 | ||
4651 | if (!(bp->flags & BNX2_FLAG_ASF_ENABLE)) | |
4652 | bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; | |
0d8a6571 | 4653 | |
2726d6e1 | 4654 | val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB); |
0d8a6571 MC |
4655 | if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE) |
4656 | return; | |
4657 | ||
7c62e83b MC |
4658 | if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) { |
4659 | bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; | |
4660 | sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN; | |
4661 | } | |
4662 | ||
4663 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && | |
4664 | (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) { | |
4665 | u32 link; | |
4666 | ||
583c28e5 | 4667 | bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; |
0d8a6571 | 4668 | |
7c62e83b MC |
4669 | link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); |
4670 | if (link & BNX2_LINK_STATUS_SERDES_LINK) | |
0d8a6571 MC |
4671 | bp->phy_port = PORT_FIBRE; |
4672 | else | |
4673 | bp->phy_port = PORT_TP; | |
489310a4 | 4674 | |
7c62e83b MC |
4675 | sig |= BNX2_DRV_ACK_CAP_SIGNATURE | |
4676 | BNX2_FW_CAP_REMOTE_PHY_CAPABLE; | |
0d8a6571 | 4677 | } |
7c62e83b MC |
4678 | |
4679 | if (netif_running(bp->dev) && sig) | |
4680 | bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig); | |
0d8a6571 MC |
4681 | } |
4682 | ||
b4b36042 MC |
4683 | static void |
4684 | bnx2_setup_msix_tbl(struct bnx2 *bp) | |
4685 | { | |
e503e066 | 4686 | BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN); |
b4b36042 | 4687 | |
e503e066 MC |
4688 | BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR); |
4689 | BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR); | |
b4b36042 MC |
4690 | } |
4691 | ||
b6016b76 MC |
4692 | static int |
4693 | bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) | |
4694 | { | |
4695 | u32 val; | |
4696 | int i, rc = 0; | |
489310a4 | 4697 | u8 old_port; |
b6016b76 MC |
4698 | |
4699 | /* Wait for the current PCI transaction to complete before | |
4700 | * issuing a reset. */ | |
4ce45e02 MC |
4701 | if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) || |
4702 | (BNX2_CHIP(bp) == BNX2_CHIP_5708)) { | |
e503e066 MC |
4703 | BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, |
4704 | BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | | |
4705 | BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | | |
4706 | BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | | |
4707 | BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); | |
4708 | val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); | |
a5dac108 EW |
4709 | udelay(5); |
4710 | } else { /* 5709 */ | |
e503e066 | 4711 | val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); |
a5dac108 | 4712 | val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; |
e503e066 MC |
4713 | BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); |
4714 | val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); | |
a5dac108 EW |
4715 | |
4716 | for (i = 0; i < 100; i++) { | |
4717 | msleep(1); | |
e503e066 | 4718 | val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL); |
a5dac108 EW |
4719 | if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND)) |
4720 | break; | |
4721 | } | |
4722 | } | |
b6016b76 | 4723 | |
b090ae2b | 4724 | /* Wait for the firmware to tell us it is ok to issue a reset. */ |
a2f13890 | 4725 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1); |
b090ae2b | 4726 | |
b6016b76 MC |
4727 | /* Deposit a driver reset signature so the firmware knows that |
4728 | * this is a soft reset. */ | |
2726d6e1 MC |
4729 | bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE, |
4730 | BNX2_DRV_RESET_SIGNATURE_MAGIC); | |
b6016b76 | 4731 | |
b6016b76 MC |
4732 | /* Do a dummy read to force the chip to complete all current transaction |
4733 | * before we issue a reset. */ | |
e503e066 | 4734 | val = BNX2_RD(bp, BNX2_MISC_ID); |
b6016b76 | 4735 | |
4ce45e02 | 4736 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
e503e066 MC |
4737 | BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); |
4738 | BNX2_RD(bp, BNX2_MISC_COMMAND); | |
234754d5 | 4739 | udelay(5); |
b6016b76 | 4740 | |
234754d5 MC |
4741 | val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | |
4742 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; | |
b6016b76 | 4743 | |
e503e066 | 4744 | BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); |
b6016b76 | 4745 | |
234754d5 MC |
4746 | } else { |
4747 | val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
4748 | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | | |
4749 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; | |
4750 | ||
4751 | /* Chip reset. */ | |
e503e066 | 4752 | BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); |
234754d5 | 4753 | |
594a9dfa MC |
4754 | /* Reading back any register after chip reset will hang the |
4755 | * bus on 5706 A0 and A1. The msleep below provides plenty | |
4756 | * of margin for write posting. | |
4757 | */ | |
4ce45e02 MC |
4758 | if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || |
4759 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) | |
8e545881 | 4760 | msleep(20); |
b6016b76 | 4761 | |
234754d5 MC |
4762 | /* Reset takes approximate 30 usec */ |
4763 | for (i = 0; i < 10; i++) { | |
e503e066 | 4764 | val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG); |
234754d5 MC |
4765 | if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | |
4766 | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) | |
4767 | break; | |
4768 | udelay(10); | |
4769 | } | |
4770 | ||
4771 | if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | |
4772 | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { | |
3a9c6a49 | 4773 | pr_err("Chip reset did not complete\n"); |
234754d5 MC |
4774 | return -EBUSY; |
4775 | } | |
b6016b76 MC |
4776 | } |
4777 | ||
4778 | /* Make sure byte swapping is properly configured. */ | |
e503e066 | 4779 | val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0); |
b6016b76 | 4780 | if (val != 0x01020304) { |
3a9c6a49 | 4781 | pr_err("Chip not in correct endian mode\n"); |
b6016b76 MC |
4782 | return -ENODEV; |
4783 | } | |
4784 | ||
b6016b76 | 4785 | /* Wait for the firmware to finish its initialization. */ |
a2f13890 | 4786 | rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0); |
b090ae2b MC |
4787 | if (rc) |
4788 | return rc; | |
b6016b76 | 4789 | |
0d8a6571 | 4790 | spin_lock_bh(&bp->phy_lock); |
489310a4 | 4791 | old_port = bp->phy_port; |
7c62e83b | 4792 | bnx2_init_fw_cap(bp); |
583c28e5 MC |
4793 | if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) && |
4794 | old_port != bp->phy_port) | |
0d8a6571 MC |
4795 | bnx2_set_default_remote_link(bp); |
4796 | spin_unlock_bh(&bp->phy_lock); | |
4797 | ||
4ce45e02 | 4798 | if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { |
b6016b76 MC |
4799 | /* Adjust the voltage regular to two steps lower. The default |
4800 | * of this register is 0x0000000e. */ | |
e503e066 | 4801 | BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); |
b6016b76 MC |
4802 | |
4803 | /* Remove bad rbuf memory from the free pool. */ | |
4804 | rc = bnx2_alloc_bad_rbuf(bp); | |
4805 | } | |
4806 | ||
c441b8d2 | 4807 | if (bp->flags & BNX2_FLAG_USING_MSIX) { |
b4b36042 | 4808 | bnx2_setup_msix_tbl(bp); |
c441b8d2 | 4809 | /* Prevent MSIX table reads and write from timing out */ |
e503e066 | 4810 | BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL, |
c441b8d2 MC |
4811 | BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN); |
4812 | } | |
b4b36042 | 4813 | |
b6016b76 MC |
4814 | return rc; |
4815 | } | |
4816 | ||
4817 | static int | |
4818 | bnx2_init_chip(struct bnx2 *bp) | |
4819 | { | |
d8026d93 | 4820 | u32 val, mtu; |
b4b36042 | 4821 | int rc, i; |
b6016b76 MC |
4822 | |
4823 | /* Make sure the interrupt is not active. */ | |
e503e066 | 4824 | BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); |
b6016b76 MC |
4825 | |
4826 | val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | | |
4827 | BNX2_DMA_CONFIG_DATA_WORD_SWAP | | |
4828 | #ifdef __BIG_ENDIAN | |
6aa20a22 | 4829 | BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | |
b6016b76 | 4830 | #endif |
6aa20a22 | 4831 | BNX2_DMA_CONFIG_CNTL_WORD_SWAP | |
b6016b76 MC |
4832 | DMA_READ_CHANS << 12 | |
4833 | DMA_WRITE_CHANS << 16; | |
4834 | ||
4835 | val |= (0x2 << 20) | (1 << 11); | |
4836 | ||
f86e82fb | 4837 | if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133)) |
b6016b76 MC |
4838 | val |= (1 << 23); |
4839 | ||
4ce45e02 MC |
4840 | if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) && |
4841 | (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) && | |
4842 | !(bp->flags & BNX2_FLAG_PCIX)) | |
b6016b76 MC |
4843 | val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; |
4844 | ||
e503e066 | 4845 | BNX2_WR(bp, BNX2_DMA_CONFIG, val); |
b6016b76 | 4846 | |
4ce45e02 | 4847 | if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { |
e503e066 | 4848 | val = BNX2_RD(bp, BNX2_TDMA_CONFIG); |
b6016b76 | 4849 | val |= BNX2_TDMA_CONFIG_ONE_DMA; |
e503e066 | 4850 | BNX2_WR(bp, BNX2_TDMA_CONFIG, val); |
b6016b76 MC |
4851 | } |
4852 | ||
f86e82fb | 4853 | if (bp->flags & BNX2_FLAG_PCIX) { |
b6016b76 MC |
4854 | u16 val16; |
4855 | ||
4856 | pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, | |
4857 | &val16); | |
4858 | pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, | |
4859 | val16 & ~PCI_X_CMD_ERO); | |
4860 | } | |
4861 | ||
e503e066 MC |
4862 | BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, |
4863 | BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | | |
4864 | BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | | |
4865 | BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); | |
b6016b76 MC |
4866 | |
4867 | /* Initialize context mapping and zero out the quick contexts. The | |
4868 | * context block must have already been enabled. */ | |
4ce45e02 | 4869 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
641bdcd5 MC |
4870 | rc = bnx2_init_5709_context(bp); |
4871 | if (rc) | |
4872 | return rc; | |
4873 | } else | |
59b47d8a | 4874 | bnx2_init_context(bp); |
b6016b76 | 4875 | |
fba9fe91 MC |
4876 | if ((rc = bnx2_init_cpus(bp)) != 0) |
4877 | return rc; | |
4878 | ||
b6016b76 MC |
4879 | bnx2_init_nvram(bp); |
4880 | ||
5fcaed01 | 4881 | bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); |
b6016b76 | 4882 | |
e503e066 | 4883 | val = BNX2_RD(bp, BNX2_MQ_CONFIG); |
b6016b76 MC |
4884 | val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; |
4885 | val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; | |
4ce45e02 | 4886 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
4edd473f | 4887 | val |= BNX2_MQ_CONFIG_BIN_MQ_MODE; |
4ce45e02 | 4888 | if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax) |
4edd473f MC |
4889 | val |= BNX2_MQ_CONFIG_HALT_DIS; |
4890 | } | |
68c9f75a | 4891 | |
e503e066 | 4892 | BNX2_WR(bp, BNX2_MQ_CONFIG, val); |
b6016b76 MC |
4893 | |
4894 | val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); | |
e503e066 MC |
4895 | BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); |
4896 | BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val); | |
b6016b76 | 4897 | |
2bc4078e | 4898 | val = (BNX2_PAGE_BITS - 8) << 24; |
e503e066 | 4899 | BNX2_WR(bp, BNX2_RV2P_CONFIG, val); |
b6016b76 MC |
4900 | |
4901 | /* Configure page size. */ | |
e503e066 | 4902 | val = BNX2_RD(bp, BNX2_TBDR_CONFIG); |
b6016b76 | 4903 | val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; |
2bc4078e | 4904 | val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40; |
e503e066 | 4905 | BNX2_WR(bp, BNX2_TBDR_CONFIG, val); |
b6016b76 MC |
4906 | |
4907 | val = bp->mac_addr[0] + | |
4908 | (bp->mac_addr[1] << 8) + | |
4909 | (bp->mac_addr[2] << 16) + | |
4910 | bp->mac_addr[3] + | |
4911 | (bp->mac_addr[4] << 8) + | |
4912 | (bp->mac_addr[5] << 16); | |
e503e066 | 4913 | BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); |
b6016b76 MC |
4914 | |
4915 | /* Program the MTU. Also include 4 bytes for CRC32. */ | |
d8026d93 MC |
4916 | mtu = bp->dev->mtu; |
4917 | val = mtu + ETH_HLEN + ETH_FCS_LEN; | |
b6016b76 MC |
4918 | if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) |
4919 | val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; | |
e503e066 | 4920 | BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); |
b6016b76 | 4921 | |
d8026d93 MC |
4922 | if (mtu < 1500) |
4923 | mtu = 1500; | |
4924 | ||
4925 | bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu)); | |
4926 | bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu)); | |
4927 | bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu)); | |
4928 | ||
155d5561 | 4929 | memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size); |
b4b36042 MC |
4930 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) |
4931 | bp->bnx2_napi[i].last_status_idx = 0; | |
4932 | ||
efba0180 MC |
4933 | bp->idle_chk_status_idx = 0xffff; |
4934 | ||
b6016b76 MC |
4935 | bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE; |
4936 | ||
4937 | /* Set up how to generate a link change interrupt. */ | |
e503e066 | 4938 | BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); |
b6016b76 | 4939 | |
e503e066 MC |
4940 | BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L, |
4941 | (u64) bp->status_blk_mapping & 0xffffffff); | |
4942 | BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); | |
b6016b76 | 4943 | |
e503e066 MC |
4944 | BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L, |
4945 | (u64) bp->stats_blk_mapping & 0xffffffff); | |
4946 | BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H, | |
4947 | (u64) bp->stats_blk_mapping >> 32); | |
b6016b76 | 4948 | |
e503e066 MC |
4949 | BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, |
4950 | (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); | |
b6016b76 | 4951 | |
e503e066 MC |
4952 | BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, |
4953 | (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); | |
b6016b76 | 4954 | |
e503e066 MC |
4955 | BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP, |
4956 | (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); | |
b6016b76 | 4957 | |
e503e066 | 4958 | BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); |
b6016b76 | 4959 | |
e503e066 | 4960 | BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); |
b6016b76 | 4961 | |
e503e066 MC |
4962 | BNX2_WR(bp, BNX2_HC_COM_TICKS, |
4963 | (bp->com_ticks_int << 16) | bp->com_ticks); | |
b6016b76 | 4964 | |
e503e066 MC |
4965 | BNX2_WR(bp, BNX2_HC_CMD_TICKS, |
4966 | (bp->cmd_ticks_int << 16) | bp->cmd_ticks); | |
b6016b76 | 4967 | |
61d9e3fa | 4968 | if (bp->flags & BNX2_FLAG_BROKEN_STATS) |
e503e066 | 4969 | BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0); |
02537b06 | 4970 | else |
e503e066 MC |
4971 | BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); |
4972 | BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ | |
b6016b76 | 4973 | |
4ce45e02 | 4974 | if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) |
8e6a72c4 | 4975 | val = BNX2_HC_CONFIG_COLLECT_STATS; |
b6016b76 | 4976 | else { |
8e6a72c4 MC |
4977 | val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE | |
4978 | BNX2_HC_CONFIG_COLLECT_STATS; | |
b6016b76 MC |
4979 | } |
4980 | ||
efde73a3 | 4981 | if (bp->flags & BNX2_FLAG_USING_MSIX) { |
e503e066 MC |
4982 | BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, |
4983 | BNX2_HC_MSIX_BIT_VECTOR_VAL); | |
c76c0475 | 4984 | |
5e9ad9e1 MC |
4985 | val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; |
4986 | } | |
4987 | ||
4988 | if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) | |
cf7474a6 | 4989 | val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM; |
5e9ad9e1 | 4990 | |
e503e066 | 4991 | BNX2_WR(bp, BNX2_HC_CONFIG, val); |
5e9ad9e1 | 4992 | |
22fa159d MC |
4993 | if (bp->rx_ticks < 25) |
4994 | bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1); | |
4995 | else | |
4996 | bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0); | |
4997 | ||
5e9ad9e1 MC |
4998 | for (i = 1; i < bp->irq_nvecs; i++) { |
4999 | u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) + | |
5000 | BNX2_HC_SB_CONFIG_1; | |
5001 | ||
e503e066 | 5002 | BNX2_WR(bp, base, |
c76c0475 | 5003 | BNX2_HC_SB_CONFIG_1_TX_TMR_MODE | |
5e9ad9e1 | 5004 | BNX2_HC_SB_CONFIG_1_RX_TMR_MODE | |
c76c0475 MC |
5005 | BNX2_HC_SB_CONFIG_1_ONE_SHOT); |
5006 | ||
e503e066 | 5007 | BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF, |
c76c0475 MC |
5008 | (bp->tx_quick_cons_trip_int << 16) | |
5009 | bp->tx_quick_cons_trip); | |
5010 | ||
e503e066 | 5011 | BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF, |
c76c0475 MC |
5012 | (bp->tx_ticks_int << 16) | bp->tx_ticks); |
5013 | ||
e503e066 MC |
5014 | BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF, |
5015 | (bp->rx_quick_cons_trip_int << 16) | | |
5e9ad9e1 | 5016 | bp->rx_quick_cons_trip); |
8e6a72c4 | 5017 | |
e503e066 | 5018 | BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF, |
5e9ad9e1 MC |
5019 | (bp->rx_ticks_int << 16) | bp->rx_ticks); |
5020 | } | |
8e6a72c4 | 5021 | |
b6016b76 | 5022 | /* Clear internal stats counters. */ |
e503e066 | 5023 | BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); |
b6016b76 | 5024 | |
e503e066 | 5025 | BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS); |
b6016b76 MC |
5026 | |
5027 | /* Initialize the receive filter. */ | |
5028 | bnx2_set_rx_mode(bp->dev); | |
5029 | ||
4ce45e02 | 5030 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
e503e066 | 5031 | val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); |
0aa38df7 | 5032 | val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; |
e503e066 | 5033 | BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); |
0aa38df7 | 5034 | } |
b090ae2b | 5035 | rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, |
a2f13890 | 5036 | 1, 0); |
b6016b76 | 5037 | |
e503e066 MC |
5038 | BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT); |
5039 | BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS); | |
b6016b76 MC |
5040 | |
5041 | udelay(20); | |
5042 | ||
e503e066 | 5043 | bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND); |
bf5295bb | 5044 | |
b090ae2b | 5045 | return rc; |
b6016b76 MC |
5046 | } |
5047 | ||
c76c0475 MC |
5048 | static void |
5049 | bnx2_clear_ring_states(struct bnx2 *bp) | |
5050 | { | |
5051 | struct bnx2_napi *bnapi; | |
35e9010b | 5052 | struct bnx2_tx_ring_info *txr; |
bb4f98ab | 5053 | struct bnx2_rx_ring_info *rxr; |
c76c0475 MC |
5054 | int i; |
5055 | ||
5056 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { | |
5057 | bnapi = &bp->bnx2_napi[i]; | |
35e9010b | 5058 | txr = &bnapi->tx_ring; |
bb4f98ab | 5059 | rxr = &bnapi->rx_ring; |
c76c0475 | 5060 | |
35e9010b MC |
5061 | txr->tx_cons = 0; |
5062 | txr->hw_tx_cons = 0; | |
bb4f98ab MC |
5063 | rxr->rx_prod_bseq = 0; |
5064 | rxr->rx_prod = 0; | |
5065 | rxr->rx_cons = 0; | |
5066 | rxr->rx_pg_prod = 0; | |
5067 | rxr->rx_pg_cons = 0; | |
c76c0475 MC |
5068 | } |
5069 | } | |
5070 | ||
59b47d8a | 5071 | static void |
35e9010b | 5072 | bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr) |
59b47d8a MC |
5073 | { |
5074 | u32 val, offset0, offset1, offset2, offset3; | |
62a8313c | 5075 | u32 cid_addr = GET_CID_ADDR(cid); |
59b47d8a | 5076 | |
4ce45e02 | 5077 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
59b47d8a MC |
5078 | offset0 = BNX2_L2CTX_TYPE_XI; |
5079 | offset1 = BNX2_L2CTX_CMD_TYPE_XI; | |
5080 | offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI; | |
5081 | offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI; | |
5082 | } else { | |
5083 | offset0 = BNX2_L2CTX_TYPE; | |
5084 | offset1 = BNX2_L2CTX_CMD_TYPE; | |
5085 | offset2 = BNX2_L2CTX_TBDR_BHADDR_HI; | |
5086 | offset3 = BNX2_L2CTX_TBDR_BHADDR_LO; | |
5087 | } | |
5088 | val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; | |
62a8313c | 5089 | bnx2_ctx_wr(bp, cid_addr, offset0, val); |
59b47d8a MC |
5090 | |
5091 | val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); | |
62a8313c | 5092 | bnx2_ctx_wr(bp, cid_addr, offset1, val); |
59b47d8a | 5093 | |
35e9010b | 5094 | val = (u64) txr->tx_desc_mapping >> 32; |
62a8313c | 5095 | bnx2_ctx_wr(bp, cid_addr, offset2, val); |
59b47d8a | 5096 | |
35e9010b | 5097 | val = (u64) txr->tx_desc_mapping & 0xffffffff; |
62a8313c | 5098 | bnx2_ctx_wr(bp, cid_addr, offset3, val); |
59b47d8a | 5099 | } |
b6016b76 MC |
5100 | |
5101 | static void | |
35e9010b | 5102 | bnx2_init_tx_ring(struct bnx2 *bp, int ring_num) |
b6016b76 | 5103 | { |
2bc4078e | 5104 | struct bnx2_tx_bd *txbd; |
c76c0475 MC |
5105 | u32 cid = TX_CID; |
5106 | struct bnx2_napi *bnapi; | |
35e9010b | 5107 | struct bnx2_tx_ring_info *txr; |
c76c0475 | 5108 | |
35e9010b MC |
5109 | bnapi = &bp->bnx2_napi[ring_num]; |
5110 | txr = &bnapi->tx_ring; | |
5111 | ||
5112 | if (ring_num == 0) | |
5113 | cid = TX_CID; | |
5114 | else | |
5115 | cid = TX_TSS_CID + ring_num - 1; | |
b6016b76 | 5116 | |
2f8af120 MC |
5117 | bp->tx_wake_thresh = bp->tx_ring_size / 2; |
5118 | ||
2bc4078e | 5119 | txbd = &txr->tx_desc_ring[BNX2_MAX_TX_DESC_CNT]; |
6aa20a22 | 5120 | |
35e9010b MC |
5121 | txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32; |
5122 | txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff; | |
b6016b76 | 5123 | |
35e9010b MC |
5124 | txr->tx_prod = 0; |
5125 | txr->tx_prod_bseq = 0; | |
6aa20a22 | 5126 | |
35e9010b MC |
5127 | txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; |
5128 | txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; | |
b6016b76 | 5129 | |
35e9010b | 5130 | bnx2_init_tx_context(bp, cid, txr); |
b6016b76 MC |
5131 | } |
5132 | ||
5133 | static void | |
2bc4078e MC |
5134 | bnx2_init_rxbd_rings(struct bnx2_rx_bd *rx_ring[], dma_addr_t dma[], |
5135 | u32 buf_size, int num_rings) | |
b6016b76 | 5136 | { |
b6016b76 | 5137 | int i; |
2bc4078e | 5138 | struct bnx2_rx_bd *rxbd; |
6aa20a22 | 5139 | |
5d5d0015 | 5140 | for (i = 0; i < num_rings; i++) { |
13daffa2 | 5141 | int j; |
b6016b76 | 5142 | |
5d5d0015 | 5143 | rxbd = &rx_ring[i][0]; |
2bc4078e | 5144 | for (j = 0; j < BNX2_MAX_RX_DESC_CNT; j++, rxbd++) { |
5d5d0015 | 5145 | rxbd->rx_bd_len = buf_size; |
13daffa2 MC |
5146 | rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; |
5147 | } | |
5d5d0015 | 5148 | if (i == (num_rings - 1)) |
13daffa2 MC |
5149 | j = 0; |
5150 | else | |
5151 | j = i + 1; | |
5d5d0015 MC |
5152 | rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32; |
5153 | rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff; | |
13daffa2 | 5154 | } |
5d5d0015 MC |
5155 | } |
5156 | ||
5157 | static void | |
bb4f98ab | 5158 | bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) |
5d5d0015 MC |
5159 | { |
5160 | int i; | |
5161 | u16 prod, ring_prod; | |
bb4f98ab MC |
5162 | u32 cid, rx_cid_addr, val; |
5163 | struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num]; | |
5164 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
5165 | ||
5166 | if (ring_num == 0) | |
5167 | cid = RX_CID; | |
5168 | else | |
5169 | cid = RX_RSS_CID + ring_num - 1; | |
5170 | ||
5171 | rx_cid_addr = GET_CID_ADDR(cid); | |
5d5d0015 | 5172 | |
bb4f98ab | 5173 | bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping, |
5d5d0015 MC |
5174 | bp->rx_buf_use_size, bp->rx_max_ring); |
5175 | ||
bb4f98ab | 5176 | bnx2_init_rx_context(bp, cid); |
83e3fc89 | 5177 | |
4ce45e02 | 5178 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
e503e066 MC |
5179 | val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5); |
5180 | BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM); | |
83e3fc89 MC |
5181 | } |
5182 | ||
62a8313c | 5183 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); |
47bf4246 | 5184 | if (bp->rx_pg_ring_size) { |
bb4f98ab MC |
5185 | bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring, |
5186 | rxr->rx_pg_desc_mapping, | |
47bf4246 MC |
5187 | PAGE_SIZE, bp->rx_max_pg_ring); |
5188 | val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; | |
62a8313c MC |
5189 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); |
5190 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, | |
5e9ad9e1 | 5191 | BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num); |
47bf4246 | 5192 | |
bb4f98ab | 5193 | val = (u64) rxr->rx_pg_desc_mapping[0] >> 32; |
62a8313c | 5194 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); |
47bf4246 | 5195 | |
bb4f98ab | 5196 | val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; |
62a8313c | 5197 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); |
47bf4246 | 5198 | |
4ce45e02 | 5199 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
e503e066 | 5200 | BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); |
47bf4246 | 5201 | } |
b6016b76 | 5202 | |
bb4f98ab | 5203 | val = (u64) rxr->rx_desc_mapping[0] >> 32; |
62a8313c | 5204 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); |
b6016b76 | 5205 | |
bb4f98ab | 5206 | val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff; |
62a8313c | 5207 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); |
b6016b76 | 5208 | |
bb4f98ab | 5209 | ring_prod = prod = rxr->rx_pg_prod; |
47bf4246 | 5210 | for (i = 0; i < bp->rx_pg_ring_size; i++) { |
a2df00aa | 5211 | if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) { |
3a9c6a49 JP |
5212 | netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n", |
5213 | ring_num, i, bp->rx_pg_ring_size); | |
47bf4246 | 5214 | break; |
b929e53c | 5215 | } |
2bc4078e MC |
5216 | prod = BNX2_NEXT_RX_BD(prod); |
5217 | ring_prod = BNX2_RX_PG_RING_IDX(prod); | |
47bf4246 | 5218 | } |
bb4f98ab | 5219 | rxr->rx_pg_prod = prod; |
47bf4246 | 5220 | |
bb4f98ab | 5221 | ring_prod = prod = rxr->rx_prod; |
236b6394 | 5222 | for (i = 0; i < bp->rx_ring_size; i++) { |
dd2bc8e9 | 5223 | if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) { |
3a9c6a49 JP |
5224 | netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n", |
5225 | ring_num, i, bp->rx_ring_size); | |
b6016b76 | 5226 | break; |
b929e53c | 5227 | } |
2bc4078e MC |
5228 | prod = BNX2_NEXT_RX_BD(prod); |
5229 | ring_prod = BNX2_RX_RING_IDX(prod); | |
b6016b76 | 5230 | } |
bb4f98ab | 5231 | rxr->rx_prod = prod; |
b6016b76 | 5232 | |
bb4f98ab MC |
5233 | rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX; |
5234 | rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ; | |
5235 | rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX; | |
b6016b76 | 5236 | |
e503e066 MC |
5237 | BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); |
5238 | BNX2_WR16(bp, rxr->rx_bidx_addr, prod); | |
bb4f98ab | 5239 | |
e503e066 | 5240 | BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); |
b6016b76 MC |
5241 | } |
5242 | ||
35e9010b MC |
5243 | static void |
5244 | bnx2_init_all_rings(struct bnx2 *bp) | |
5245 | { | |
5246 | int i; | |
5e9ad9e1 | 5247 | u32 val; |
35e9010b MC |
5248 | |
5249 | bnx2_clear_ring_states(bp); | |
5250 | ||
e503e066 | 5251 | BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0); |
35e9010b MC |
5252 | for (i = 0; i < bp->num_tx_rings; i++) |
5253 | bnx2_init_tx_ring(bp, i); | |
5254 | ||
5255 | if (bp->num_tx_rings > 1) | |
e503e066 MC |
5256 | BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) | |
5257 | (TX_TSS_CID << 7)); | |
35e9010b | 5258 | |
e503e066 | 5259 | BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0); |
5e9ad9e1 MC |
5260 | bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0); |
5261 | ||
bb4f98ab MC |
5262 | for (i = 0; i < bp->num_rx_rings; i++) |
5263 | bnx2_init_rx_ring(bp, i); | |
5e9ad9e1 MC |
5264 | |
5265 | if (bp->num_rx_rings > 1) { | |
22fa159d | 5266 | u32 tbl_32 = 0; |
5e9ad9e1 MC |
5267 | |
5268 | for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) { | |
22fa159d MC |
5269 | int shift = (i % 8) << 2; |
5270 | ||
5271 | tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift; | |
5272 | if ((i % 8) == 7) { | |
e503e066 MC |
5273 | BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32); |
5274 | BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) | | |
22fa159d MC |
5275 | BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK | |
5276 | BNX2_RLUP_RSS_COMMAND_WRITE | | |
5277 | BNX2_RLUP_RSS_COMMAND_HASH_MASK); | |
5278 | tbl_32 = 0; | |
5279 | } | |
5e9ad9e1 MC |
5280 | } |
5281 | ||
5282 | val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI | | |
5283 | BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI; | |
5284 | ||
e503e066 | 5285 | BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val); |
5e9ad9e1 MC |
5286 | |
5287 | } | |
35e9010b MC |
5288 | } |
5289 | ||
5d5d0015 | 5290 | static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size) |
13daffa2 | 5291 | { |
5d5d0015 | 5292 | u32 max, num_rings = 1; |
13daffa2 | 5293 | |
2bc4078e MC |
5294 | while (ring_size > BNX2_MAX_RX_DESC_CNT) { |
5295 | ring_size -= BNX2_MAX_RX_DESC_CNT; | |
13daffa2 MC |
5296 | num_rings++; |
5297 | } | |
5298 | /* round to next power of 2 */ | |
5d5d0015 | 5299 | max = max_size; |
13daffa2 MC |
5300 | while ((max & num_rings) == 0) |
5301 | max >>= 1; | |
5302 | ||
5303 | if (num_rings != max) | |
5304 | max <<= 1; | |
5305 | ||
5d5d0015 MC |
5306 | return max; |
5307 | } | |
5308 | ||
5309 | static void | |
5310 | bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) | |
5311 | { | |
84eaa187 | 5312 | u32 rx_size, rx_space, jumbo_size; |
5d5d0015 MC |
5313 | |
5314 | /* 8 for CRC and VLAN */ | |
d89cb6af | 5315 | rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8; |
5d5d0015 | 5316 | |
84eaa187 | 5317 | rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD + |
dd2bc8e9 | 5318 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
84eaa187 | 5319 | |
601d3d18 | 5320 | bp->rx_copy_thresh = BNX2_RX_COPY_THRESH; |
47bf4246 MC |
5321 | bp->rx_pg_ring_size = 0; |
5322 | bp->rx_max_pg_ring = 0; | |
5323 | bp->rx_max_pg_ring_idx = 0; | |
f86e82fb | 5324 | if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) { |
84eaa187 MC |
5325 | int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; |
5326 | ||
5327 | jumbo_size = size * pages; | |
2bc4078e MC |
5328 | if (jumbo_size > BNX2_MAX_TOTAL_RX_PG_DESC_CNT) |
5329 | jumbo_size = BNX2_MAX_TOTAL_RX_PG_DESC_CNT; | |
84eaa187 MC |
5330 | |
5331 | bp->rx_pg_ring_size = jumbo_size; | |
5332 | bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size, | |
2bc4078e MC |
5333 | BNX2_MAX_RX_PG_RINGS); |
5334 | bp->rx_max_pg_ring_idx = | |
5335 | (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1; | |
601d3d18 | 5336 | rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET; |
84eaa187 MC |
5337 | bp->rx_copy_thresh = 0; |
5338 | } | |
5d5d0015 MC |
5339 | |
5340 | bp->rx_buf_use_size = rx_size; | |
dd2bc8e9 ED |
5341 | /* hw alignment + build_skb() overhead*/ |
5342 | bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) + | |
5343 | NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
d89cb6af | 5344 | bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET; |
5d5d0015 | 5345 | bp->rx_ring_size = size; |
2bc4078e MC |
5346 | bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS); |
5347 | bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1; | |
13daffa2 MC |
5348 | } |
5349 | ||
b6016b76 MC |
5350 | static void |
5351 | bnx2_free_tx_skbs(struct bnx2 *bp) | |
5352 | { | |
5353 | int i; | |
5354 | ||
35e9010b MC |
5355 | for (i = 0; i < bp->num_tx_rings; i++) { |
5356 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
5357 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; | |
5358 | int j; | |
b6016b76 | 5359 | |
35e9010b | 5360 | if (txr->tx_buf_ring == NULL) |
b6016b76 | 5361 | continue; |
b6016b76 | 5362 | |
2bc4078e MC |
5363 | for (j = 0; j < BNX2_TX_DESC_CNT; ) { |
5364 | struct bnx2_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; | |
35e9010b | 5365 | struct sk_buff *skb = tx_buf->skb; |
e95524a7 | 5366 | int k, last; |
35e9010b MC |
5367 | |
5368 | if (skb == NULL) { | |
2bc4078e | 5369 | j = BNX2_NEXT_TX_BD(j); |
35e9010b MC |
5370 | continue; |
5371 | } | |
5372 | ||
36227e88 | 5373 | dma_unmap_single(&bp->pdev->dev, |
1a4ccc2d | 5374 | dma_unmap_addr(tx_buf, mapping), |
e95524a7 AD |
5375 | skb_headlen(skb), |
5376 | PCI_DMA_TODEVICE); | |
b6016b76 | 5377 | |
35e9010b | 5378 | tx_buf->skb = NULL; |
b6016b76 | 5379 | |
e95524a7 | 5380 | last = tx_buf->nr_frags; |
2bc4078e MC |
5381 | j = BNX2_NEXT_TX_BD(j); |
5382 | for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) { | |
5383 | tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(j)]; | |
36227e88 | 5384 | dma_unmap_page(&bp->pdev->dev, |
1a4ccc2d | 5385 | dma_unmap_addr(tx_buf, mapping), |
9e903e08 | 5386 | skb_frag_size(&skb_shinfo(skb)->frags[k]), |
e95524a7 AD |
5387 | PCI_DMA_TODEVICE); |
5388 | } | |
35e9010b | 5389 | dev_kfree_skb(skb); |
b6016b76 | 5390 | } |
e9831909 | 5391 | netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); |
b6016b76 | 5392 | } |
b6016b76 MC |
5393 | } |
5394 | ||
5395 | static void | |
5396 | bnx2_free_rx_skbs(struct bnx2 *bp) | |
5397 | { | |
5398 | int i; | |
5399 | ||
bb4f98ab MC |
5400 | for (i = 0; i < bp->num_rx_rings; i++) { |
5401 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; | |
5402 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; | |
5403 | int j; | |
b6016b76 | 5404 | |
bb4f98ab MC |
5405 | if (rxr->rx_buf_ring == NULL) |
5406 | return; | |
b6016b76 | 5407 | |
bb4f98ab | 5408 | for (j = 0; j < bp->rx_max_ring_idx; j++) { |
2bc4078e | 5409 | struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[j]; |
dd2bc8e9 | 5410 | u8 *data = rx_buf->data; |
b6016b76 | 5411 | |
dd2bc8e9 | 5412 | if (data == NULL) |
bb4f98ab | 5413 | continue; |
b6016b76 | 5414 | |
36227e88 | 5415 | dma_unmap_single(&bp->pdev->dev, |
1a4ccc2d | 5416 | dma_unmap_addr(rx_buf, mapping), |
bb4f98ab MC |
5417 | bp->rx_buf_use_size, |
5418 | PCI_DMA_FROMDEVICE); | |
b6016b76 | 5419 | |
dd2bc8e9 | 5420 | rx_buf->data = NULL; |
bb4f98ab | 5421 | |
dd2bc8e9 | 5422 | kfree(data); |
bb4f98ab MC |
5423 | } |
5424 | for (j = 0; j < bp->rx_max_pg_ring_idx; j++) | |
5425 | bnx2_free_rx_page(bp, rxr, j); | |
b6016b76 MC |
5426 | } |
5427 | } | |
5428 | ||
5429 | static void | |
5430 | bnx2_free_skbs(struct bnx2 *bp) | |
5431 | { | |
5432 | bnx2_free_tx_skbs(bp); | |
5433 | bnx2_free_rx_skbs(bp); | |
5434 | } | |
5435 | ||
5436 | static int | |
5437 | bnx2_reset_nic(struct bnx2 *bp, u32 reset_code) | |
5438 | { | |
5439 | int rc; | |
5440 | ||
5441 | rc = bnx2_reset_chip(bp, reset_code); | |
5442 | bnx2_free_skbs(bp); | |
5443 | if (rc) | |
5444 | return rc; | |
5445 | ||
fba9fe91 MC |
5446 | if ((rc = bnx2_init_chip(bp)) != 0) |
5447 | return rc; | |
5448 | ||
35e9010b | 5449 | bnx2_init_all_rings(bp); |
b6016b76 MC |
5450 | return 0; |
5451 | } | |
5452 | ||
5453 | static int | |
9a120bc5 | 5454 | bnx2_init_nic(struct bnx2 *bp, int reset_phy) |
b6016b76 MC |
5455 | { |
5456 | int rc; | |
5457 | ||
5458 | if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) | |
5459 | return rc; | |
5460 | ||
80be4434 | 5461 | spin_lock_bh(&bp->phy_lock); |
9a120bc5 | 5462 | bnx2_init_phy(bp, reset_phy); |
b6016b76 | 5463 | bnx2_set_link(bp); |
543a827d MC |
5464 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
5465 | bnx2_remote_phy_event(bp); | |
0d8a6571 | 5466 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
5467 | return 0; |
5468 | } | |
5469 | ||
74bf4ba3 MC |
5470 | static int |
5471 | bnx2_shutdown_chip(struct bnx2 *bp) | |
5472 | { | |
5473 | u32 reset_code; | |
5474 | ||
5475 | if (bp->flags & BNX2_FLAG_NO_WOL) | |
5476 | reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; | |
5477 | else if (bp->wol) | |
5478 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | |
5479 | else | |
5480 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | |
5481 | ||
5482 | return bnx2_reset_chip(bp, reset_code); | |
5483 | } | |
5484 | ||
b6016b76 MC |
5485 | static int |
5486 | bnx2_test_registers(struct bnx2 *bp) | |
5487 | { | |
5488 | int ret; | |
5bae30c9 | 5489 | int i, is_5709; |
f71e1309 | 5490 | static const struct { |
b6016b76 MC |
5491 | u16 offset; |
5492 | u16 flags; | |
5bae30c9 | 5493 | #define BNX2_FL_NOT_5709 1 |
b6016b76 MC |
5494 | u32 rw_mask; |
5495 | u32 ro_mask; | |
5496 | } reg_tbl[] = { | |
5497 | { 0x006c, 0, 0x00000000, 0x0000003f }, | |
5498 | { 0x0090, 0, 0xffffffff, 0x00000000 }, | |
5499 | { 0x0094, 0, 0x00000000, 0x00000000 }, | |
5500 | ||
5bae30c9 MC |
5501 | { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 }, |
5502 | { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5503 | { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5504 | { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff }, | |
5505 | { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 }, | |
5506 | { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, | |
5507 | { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff }, | |
5508 | { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5509 | { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5510 | ||
5511 | { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5512 | { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, | |
5513 | { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
5514 | { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
5515 | { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
5516 | { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, | |
5517 | ||
5518 | { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, | |
5519 | { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 }, | |
5520 | { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 }, | |
b6016b76 MC |
5521 | |
5522 | { 0x1000, 0, 0x00000000, 0x00000001 }, | |
15b169cc | 5523 | { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 }, |
b6016b76 MC |
5524 | |
5525 | { 0x1408, 0, 0x01c00800, 0x00000000 }, | |
5526 | { 0x149c, 0, 0x8000ffff, 0x00000000 }, | |
5527 | { 0x14a8, 0, 0x00000000, 0x000001ff }, | |
5b0c76ad | 5528 | { 0x14ac, 0, 0x0fffffff, 0x10000000 }, |
b6016b76 MC |
5529 | { 0x14b0, 0, 0x00000002, 0x00000001 }, |
5530 | { 0x14b8, 0, 0x00000000, 0x00000000 }, | |
5531 | { 0x14c0, 0, 0x00000000, 0x00000009 }, | |
5532 | { 0x14c4, 0, 0x00003fff, 0x00000000 }, | |
5533 | { 0x14cc, 0, 0x00000000, 0x00000001 }, | |
5534 | { 0x14d0, 0, 0xffffffff, 0x00000000 }, | |
b6016b76 MC |
5535 | |
5536 | { 0x1800, 0, 0x00000000, 0x00000001 }, | |
5537 | { 0x1804, 0, 0x00000000, 0x00000003 }, | |
b6016b76 MC |
5538 | |
5539 | { 0x2800, 0, 0x00000000, 0x00000001 }, | |
5540 | { 0x2804, 0, 0x00000000, 0x00003f01 }, | |
5541 | { 0x2808, 0, 0x0f3f3f03, 0x00000000 }, | |
5542 | { 0x2810, 0, 0xffff0000, 0x00000000 }, | |
5543 | { 0x2814, 0, 0xffff0000, 0x00000000 }, | |
5544 | { 0x2818, 0, 0xffff0000, 0x00000000 }, | |
5545 | { 0x281c, 0, 0xffff0000, 0x00000000 }, | |
5546 | { 0x2834, 0, 0xffffffff, 0x00000000 }, | |
5547 | { 0x2840, 0, 0x00000000, 0xffffffff }, | |
5548 | { 0x2844, 0, 0x00000000, 0xffffffff }, | |
5549 | { 0x2848, 0, 0xffffffff, 0x00000000 }, | |
5550 | { 0x284c, 0, 0xf800f800, 0x07ff07ff }, | |
5551 | ||
5552 | { 0x2c00, 0, 0x00000000, 0x00000011 }, | |
5553 | { 0x2c04, 0, 0x00000000, 0x00030007 }, | |
5554 | ||
b6016b76 MC |
5555 | { 0x3c00, 0, 0x00000000, 0x00000001 }, |
5556 | { 0x3c04, 0, 0x00000000, 0x00070000 }, | |
5557 | { 0x3c08, 0, 0x00007f71, 0x07f00000 }, | |
5558 | { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 }, | |
5559 | { 0x3c10, 0, 0xffffffff, 0x00000000 }, | |
5560 | { 0x3c14, 0, 0x00000000, 0xffffffff }, | |
5561 | { 0x3c18, 0, 0x00000000, 0xffffffff }, | |
5562 | { 0x3c1c, 0, 0xfffff000, 0x00000000 }, | |
5563 | { 0x3c20, 0, 0xffffff00, 0x00000000 }, | |
b6016b76 MC |
5564 | |
5565 | { 0x5004, 0, 0x00000000, 0x0000007f }, | |
5566 | { 0x5008, 0, 0x0f0007ff, 0x00000000 }, | |
b6016b76 | 5567 | |
b6016b76 MC |
5568 | { 0x5c00, 0, 0x00000000, 0x00000001 }, |
5569 | { 0x5c04, 0, 0x00000000, 0x0003000f }, | |
5570 | { 0x5c08, 0, 0x00000003, 0x00000000 }, | |
5571 | { 0x5c0c, 0, 0x0000fff8, 0x00000000 }, | |
5572 | { 0x5c10, 0, 0x00000000, 0xffffffff }, | |
5573 | { 0x5c80, 0, 0x00000000, 0x0f7113f1 }, | |
5574 | { 0x5c84, 0, 0x00000000, 0x0000f333 }, | |
5575 | { 0x5c88, 0, 0x00000000, 0x00077373 }, | |
5576 | { 0x5c8c, 0, 0x00000000, 0x0007f737 }, | |
5577 | ||
5578 | { 0x6808, 0, 0x0000ff7f, 0x00000000 }, | |
5579 | { 0x680c, 0, 0xffffffff, 0x00000000 }, | |
5580 | { 0x6810, 0, 0xffffffff, 0x00000000 }, | |
5581 | { 0x6814, 0, 0xffffffff, 0x00000000 }, | |
5582 | { 0x6818, 0, 0xffffffff, 0x00000000 }, | |
5583 | { 0x681c, 0, 0xffffffff, 0x00000000 }, | |
5584 | { 0x6820, 0, 0x00ff00ff, 0x00000000 }, | |
5585 | { 0x6824, 0, 0x00ff00ff, 0x00000000 }, | |
5586 | { 0x6828, 0, 0x00ff00ff, 0x00000000 }, | |
5587 | { 0x682c, 0, 0x03ff03ff, 0x00000000 }, | |
5588 | { 0x6830, 0, 0x03ff03ff, 0x00000000 }, | |
5589 | { 0x6834, 0, 0x03ff03ff, 0x00000000 }, | |
5590 | { 0x6838, 0, 0x03ff03ff, 0x00000000 }, | |
5591 | { 0x683c, 0, 0x0000ffff, 0x00000000 }, | |
5592 | { 0x6840, 0, 0x00000ff0, 0x00000000 }, | |
5593 | { 0x6844, 0, 0x00ffff00, 0x00000000 }, | |
5594 | { 0x684c, 0, 0xffffffff, 0x00000000 }, | |
5595 | { 0x6850, 0, 0x7f7f7f7f, 0x00000000 }, | |
5596 | { 0x6854, 0, 0x7f7f7f7f, 0x00000000 }, | |
5597 | { 0x6858, 0, 0x7f7f7f7f, 0x00000000 }, | |
5598 | { 0x685c, 0, 0x7f7f7f7f, 0x00000000 }, | |
5599 | { 0x6908, 0, 0x00000000, 0x0001ff0f }, | |
5600 | { 0x690c, 0, 0x00000000, 0x0ffe00f0 }, | |
5601 | ||
5602 | { 0xffff, 0, 0x00000000, 0x00000000 }, | |
5603 | }; | |
5604 | ||
5605 | ret = 0; | |
5bae30c9 | 5606 | is_5709 = 0; |
4ce45e02 | 5607 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
5bae30c9 MC |
5608 | is_5709 = 1; |
5609 | ||
b6016b76 MC |
5610 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { |
5611 | u32 offset, rw_mask, ro_mask, save_val, val; | |
5bae30c9 MC |
5612 | u16 flags = reg_tbl[i].flags; |
5613 | ||
5614 | if (is_5709 && (flags & BNX2_FL_NOT_5709)) | |
5615 | continue; | |
b6016b76 MC |
5616 | |
5617 | offset = (u32) reg_tbl[i].offset; | |
5618 | rw_mask = reg_tbl[i].rw_mask; | |
5619 | ro_mask = reg_tbl[i].ro_mask; | |
5620 | ||
14ab9b86 | 5621 | save_val = readl(bp->regview + offset); |
b6016b76 | 5622 | |
14ab9b86 | 5623 | writel(0, bp->regview + offset); |
b6016b76 | 5624 | |
14ab9b86 | 5625 | val = readl(bp->regview + offset); |
b6016b76 MC |
5626 | if ((val & rw_mask) != 0) { |
5627 | goto reg_test_err; | |
5628 | } | |
5629 | ||
5630 | if ((val & ro_mask) != (save_val & ro_mask)) { | |
5631 | goto reg_test_err; | |
5632 | } | |
5633 | ||
14ab9b86 | 5634 | writel(0xffffffff, bp->regview + offset); |
b6016b76 | 5635 | |
14ab9b86 | 5636 | val = readl(bp->regview + offset); |
b6016b76 MC |
5637 | if ((val & rw_mask) != rw_mask) { |
5638 | goto reg_test_err; | |
5639 | } | |
5640 | ||
5641 | if ((val & ro_mask) != (save_val & ro_mask)) { | |
5642 | goto reg_test_err; | |
5643 | } | |
5644 | ||
14ab9b86 | 5645 | writel(save_val, bp->regview + offset); |
b6016b76 MC |
5646 | continue; |
5647 | ||
5648 | reg_test_err: | |
14ab9b86 | 5649 | writel(save_val, bp->regview + offset); |
b6016b76 MC |
5650 | ret = -ENODEV; |
5651 | break; | |
5652 | } | |
5653 | return ret; | |
5654 | } | |
5655 | ||
5656 | static int | |
5657 | bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size) | |
5658 | { | |
f71e1309 | 5659 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, |
b6016b76 MC |
5660 | 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; |
5661 | int i; | |
5662 | ||
5663 | for (i = 0; i < sizeof(test_pattern) / 4; i++) { | |
5664 | u32 offset; | |
5665 | ||
5666 | for (offset = 0; offset < size; offset += 4) { | |
5667 | ||
2726d6e1 | 5668 | bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]); |
b6016b76 | 5669 | |
2726d6e1 | 5670 | if (bnx2_reg_rd_ind(bp, start + offset) != |
b6016b76 MC |
5671 | test_pattern[i]) { |
5672 | return -ENODEV; | |
5673 | } | |
5674 | } | |
5675 | } | |
5676 | return 0; | |
5677 | } | |
5678 | ||
5679 | static int | |
5680 | bnx2_test_memory(struct bnx2 *bp) | |
5681 | { | |
5682 | int ret = 0; | |
5683 | int i; | |
5bae30c9 | 5684 | static struct mem_entry { |
b6016b76 MC |
5685 | u32 offset; |
5686 | u32 len; | |
5bae30c9 | 5687 | } mem_tbl_5706[] = { |
b6016b76 | 5688 | { 0x60000, 0x4000 }, |
5b0c76ad | 5689 | { 0xa0000, 0x3000 }, |
b6016b76 MC |
5690 | { 0xe0000, 0x4000 }, |
5691 | { 0x120000, 0x4000 }, | |
5692 | { 0x1a0000, 0x4000 }, | |
5693 | { 0x160000, 0x4000 }, | |
5694 | { 0xffffffff, 0 }, | |
5bae30c9 MC |
5695 | }, |
5696 | mem_tbl_5709[] = { | |
5697 | { 0x60000, 0x4000 }, | |
5698 | { 0xa0000, 0x3000 }, | |
5699 | { 0xe0000, 0x4000 }, | |
5700 | { 0x120000, 0x4000 }, | |
5701 | { 0x1a0000, 0x4000 }, | |
5702 | { 0xffffffff, 0 }, | |
b6016b76 | 5703 | }; |
5bae30c9 MC |
5704 | struct mem_entry *mem_tbl; |
5705 | ||
4ce45e02 | 5706 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
5bae30c9 MC |
5707 | mem_tbl = mem_tbl_5709; |
5708 | else | |
5709 | mem_tbl = mem_tbl_5706; | |
b6016b76 MC |
5710 | |
5711 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
5712 | if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset, | |
5713 | mem_tbl[i].len)) != 0) { | |
5714 | return ret; | |
5715 | } | |
5716 | } | |
6aa20a22 | 5717 | |
b6016b76 MC |
5718 | return ret; |
5719 | } | |
5720 | ||
bc5a0690 MC |
5721 | #define BNX2_MAC_LOOPBACK 0 |
5722 | #define BNX2_PHY_LOOPBACK 1 | |
5723 | ||
b6016b76 | 5724 | static int |
bc5a0690 | 5725 | bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) |
b6016b76 MC |
5726 | { |
5727 | unsigned int pkt_size, num_pkts, i; | |
dd2bc8e9 ED |
5728 | struct sk_buff *skb; |
5729 | u8 *data; | |
b6016b76 | 5730 | unsigned char *packet; |
bc5a0690 | 5731 | u16 rx_start_idx, rx_idx; |
b6016b76 | 5732 | dma_addr_t map; |
2bc4078e MC |
5733 | struct bnx2_tx_bd *txbd; |
5734 | struct bnx2_sw_bd *rx_buf; | |
b6016b76 MC |
5735 | struct l2_fhdr *rx_hdr; |
5736 | int ret = -ENODEV; | |
c76c0475 | 5737 | struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; |
35e9010b | 5738 | struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; |
bb4f98ab | 5739 | struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; |
c76c0475 MC |
5740 | |
5741 | tx_napi = bnapi; | |
b6016b76 | 5742 | |
35e9010b | 5743 | txr = &tx_napi->tx_ring; |
bb4f98ab | 5744 | rxr = &bnapi->rx_ring; |
bc5a0690 MC |
5745 | if (loopback_mode == BNX2_MAC_LOOPBACK) { |
5746 | bp->loopback = MAC_LOOPBACK; | |
5747 | bnx2_set_mac_loopback(bp); | |
5748 | } | |
5749 | else if (loopback_mode == BNX2_PHY_LOOPBACK) { | |
583c28e5 | 5750 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
489310a4 MC |
5751 | return 0; |
5752 | ||
80be4434 | 5753 | bp->loopback = PHY_LOOPBACK; |
bc5a0690 MC |
5754 | bnx2_set_phy_loopback(bp); |
5755 | } | |
5756 | else | |
5757 | return -EINVAL; | |
b6016b76 | 5758 | |
84eaa187 | 5759 | pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4); |
932f3772 | 5760 | skb = netdev_alloc_skb(bp->dev, pkt_size); |
b6cbc3b6 JL |
5761 | if (!skb) |
5762 | return -ENOMEM; | |
b6016b76 | 5763 | packet = skb_put(skb, pkt_size); |
6634292b | 5764 | memcpy(packet, bp->dev->dev_addr, 6); |
b6016b76 MC |
5765 | memset(packet + 6, 0x0, 8); |
5766 | for (i = 14; i < pkt_size; i++) | |
5767 | packet[i] = (unsigned char) (i & 0xff); | |
5768 | ||
36227e88 SG |
5769 | map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, |
5770 | PCI_DMA_TODEVICE); | |
5771 | if (dma_mapping_error(&bp->pdev->dev, map)) { | |
3d16af86 BL |
5772 | dev_kfree_skb(skb); |
5773 | return -EIO; | |
5774 | } | |
b6016b76 | 5775 | |
e503e066 MC |
5776 | BNX2_WR(bp, BNX2_HC_COMMAND, |
5777 | bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
bf5295bb | 5778 | |
e503e066 | 5779 | BNX2_RD(bp, BNX2_HC_COMMAND); |
b6016b76 MC |
5780 | |
5781 | udelay(5); | |
35efa7c1 | 5782 | rx_start_idx = bnx2_get_hw_rx_cons(bnapi); |
b6016b76 | 5783 | |
b6016b76 MC |
5784 | num_pkts = 0; |
5785 | ||
2bc4078e | 5786 | txbd = &txr->tx_desc_ring[BNX2_TX_RING_IDX(txr->tx_prod)]; |
b6016b76 MC |
5787 | |
5788 | txbd->tx_bd_haddr_hi = (u64) map >> 32; | |
5789 | txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; | |
5790 | txbd->tx_bd_mss_nbytes = pkt_size; | |
5791 | txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; | |
5792 | ||
5793 | num_pkts++; | |
2bc4078e | 5794 | txr->tx_prod = BNX2_NEXT_TX_BD(txr->tx_prod); |
35e9010b | 5795 | txr->tx_prod_bseq += pkt_size; |
b6016b76 | 5796 | |
e503e066 MC |
5797 | BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod); |
5798 | BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); | |
b6016b76 MC |
5799 | |
5800 | udelay(100); | |
5801 | ||
e503e066 MC |
5802 | BNX2_WR(bp, BNX2_HC_COMMAND, |
5803 | bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | |
bf5295bb | 5804 | |
e503e066 | 5805 | BNX2_RD(bp, BNX2_HC_COMMAND); |
b6016b76 MC |
5806 | |
5807 | udelay(5); | |
5808 | ||
36227e88 | 5809 | dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE); |
745720e5 | 5810 | dev_kfree_skb(skb); |
b6016b76 | 5811 | |
35e9010b | 5812 | if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod) |
b6016b76 | 5813 | goto loopback_test_done; |
b6016b76 | 5814 | |
35efa7c1 | 5815 | rx_idx = bnx2_get_hw_rx_cons(bnapi); |
b6016b76 MC |
5816 | if (rx_idx != rx_start_idx + num_pkts) { |
5817 | goto loopback_test_done; | |
5818 | } | |
5819 | ||
bb4f98ab | 5820 | rx_buf = &rxr->rx_buf_ring[rx_start_idx]; |
dd2bc8e9 | 5821 | data = rx_buf->data; |
b6016b76 | 5822 | |
dd2bc8e9 ED |
5823 | rx_hdr = get_l2_fhdr(data); |
5824 | data = (u8 *)rx_hdr + BNX2_RX_OFFSET; | |
b6016b76 | 5825 | |
36227e88 | 5826 | dma_sync_single_for_cpu(&bp->pdev->dev, |
1a4ccc2d | 5827 | dma_unmap_addr(rx_buf, mapping), |
dd2bc8e9 | 5828 | bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); |
b6016b76 | 5829 | |
ade2bfe7 | 5830 | if (rx_hdr->l2_fhdr_status & |
b6016b76 MC |
5831 | (L2_FHDR_ERRORS_BAD_CRC | |
5832 | L2_FHDR_ERRORS_PHY_DECODE | | |
5833 | L2_FHDR_ERRORS_ALIGNMENT | | |
5834 | L2_FHDR_ERRORS_TOO_SHORT | | |
5835 | L2_FHDR_ERRORS_GIANT_FRAME)) { | |
5836 | ||
5837 | goto loopback_test_done; | |
5838 | } | |
5839 | ||
5840 | if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) { | |
5841 | goto loopback_test_done; | |
5842 | } | |
5843 | ||
5844 | for (i = 14; i < pkt_size; i++) { | |
dd2bc8e9 | 5845 | if (*(data + i) != (unsigned char) (i & 0xff)) { |
b6016b76 MC |
5846 | goto loopback_test_done; |
5847 | } | |
5848 | } | |
5849 | ||
5850 | ret = 0; | |
5851 | ||
5852 | loopback_test_done: | |
5853 | bp->loopback = 0; | |
5854 | return ret; | |
5855 | } | |
5856 | ||
bc5a0690 MC |
5857 | #define BNX2_MAC_LOOPBACK_FAILED 1 |
5858 | #define BNX2_PHY_LOOPBACK_FAILED 2 | |
5859 | #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \ | |
5860 | BNX2_PHY_LOOPBACK_FAILED) | |
5861 | ||
5862 | static int | |
5863 | bnx2_test_loopback(struct bnx2 *bp) | |
5864 | { | |
5865 | int rc = 0; | |
5866 | ||
5867 | if (!netif_running(bp->dev)) | |
5868 | return BNX2_LOOPBACK_FAILED; | |
5869 | ||
5870 | bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); | |
5871 | spin_lock_bh(&bp->phy_lock); | |
9a120bc5 | 5872 | bnx2_init_phy(bp, 1); |
bc5a0690 MC |
5873 | spin_unlock_bh(&bp->phy_lock); |
5874 | if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK)) | |
5875 | rc |= BNX2_MAC_LOOPBACK_FAILED; | |
5876 | if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK)) | |
5877 | rc |= BNX2_PHY_LOOPBACK_FAILED; | |
5878 | return rc; | |
5879 | } | |
5880 | ||
b6016b76 MC |
5881 | #define NVRAM_SIZE 0x200 |
5882 | #define CRC32_RESIDUAL 0xdebb20e3 | |
5883 | ||
5884 | static int | |
5885 | bnx2_test_nvram(struct bnx2 *bp) | |
5886 | { | |
b491edd5 | 5887 | __be32 buf[NVRAM_SIZE / 4]; |
b6016b76 MC |
5888 | u8 *data = (u8 *) buf; |
5889 | int rc = 0; | |
5890 | u32 magic, csum; | |
5891 | ||
5892 | if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0) | |
5893 | goto test_nvram_done; | |
5894 | ||
5895 | magic = be32_to_cpu(buf[0]); | |
5896 | if (magic != 0x669955aa) { | |
5897 | rc = -ENODEV; | |
5898 | goto test_nvram_done; | |
5899 | } | |
5900 | ||
5901 | if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0) | |
5902 | goto test_nvram_done; | |
5903 | ||
5904 | csum = ether_crc_le(0x100, data); | |
5905 | if (csum != CRC32_RESIDUAL) { | |
5906 | rc = -ENODEV; | |
5907 | goto test_nvram_done; | |
5908 | } | |
5909 | ||
5910 | csum = ether_crc_le(0x100, data + 0x100); | |
5911 | if (csum != CRC32_RESIDUAL) { | |
5912 | rc = -ENODEV; | |
5913 | } | |
5914 | ||
5915 | test_nvram_done: | |
5916 | return rc; | |
5917 | } | |
5918 | ||
5919 | static int | |
5920 | bnx2_test_link(struct bnx2 *bp) | |
5921 | { | |
5922 | u32 bmsr; | |
5923 | ||
9f52b564 MC |
5924 | if (!netif_running(bp->dev)) |
5925 | return -ENODEV; | |
5926 | ||
583c28e5 | 5927 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
489310a4 MC |
5928 | if (bp->link_up) |
5929 | return 0; | |
5930 | return -ENODEV; | |
5931 | } | |
c770a65c | 5932 | spin_lock_bh(&bp->phy_lock); |
27a005b8 MC |
5933 | bnx2_enable_bmsr1(bp); |
5934 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
5935 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | |
5936 | bnx2_disable_bmsr1(bp); | |
c770a65c | 5937 | spin_unlock_bh(&bp->phy_lock); |
6aa20a22 | 5938 | |
b6016b76 MC |
5939 | if (bmsr & BMSR_LSTATUS) { |
5940 | return 0; | |
5941 | } | |
5942 | return -ENODEV; | |
5943 | } | |
5944 | ||
5945 | static int | |
5946 | bnx2_test_intr(struct bnx2 *bp) | |
5947 | { | |
5948 | int i; | |
b6016b76 MC |
5949 | u16 status_idx; |
5950 | ||
5951 | if (!netif_running(bp->dev)) | |
5952 | return -ENODEV; | |
5953 | ||
e503e066 | 5954 | status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; |
b6016b76 MC |
5955 | |
5956 | /* This register is not touched during run-time. */ | |
e503e066 MC |
5957 | BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); |
5958 | BNX2_RD(bp, BNX2_HC_COMMAND); | |
b6016b76 MC |
5959 | |
5960 | for (i = 0; i < 10; i++) { | |
e503e066 | 5961 | if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != |
b6016b76 MC |
5962 | status_idx) { |
5963 | ||
5964 | break; | |
5965 | } | |
5966 | ||
5967 | msleep_interruptible(10); | |
5968 | } | |
5969 | if (i < 10) | |
5970 | return 0; | |
5971 | ||
5972 | return -ENODEV; | |
5973 | } | |
5974 | ||
38ea3686 | 5975 | /* Determining link for parallel detection. */ |
b2fadeae MC |
5976 | static int |
5977 | bnx2_5706_serdes_has_link(struct bnx2 *bp) | |
5978 | { | |
5979 | u32 mode_ctl, an_dbg, exp; | |
5980 | ||
38ea3686 MC |
5981 | if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL) |
5982 | return 0; | |
5983 | ||
b2fadeae MC |
5984 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL); |
5985 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl); | |
5986 | ||
5987 | if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET)) | |
5988 | return 0; | |
5989 | ||
5990 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); | |
5991 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | |
5992 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); | |
5993 | ||
f3014c0c | 5994 | if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID)) |
b2fadeae MC |
5995 | return 0; |
5996 | ||
5997 | bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1); | |
5998 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp); | |
5999 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp); | |
6000 | ||
6001 | if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */ | |
6002 | return 0; | |
6003 | ||
6004 | return 1; | |
6005 | } | |
6006 | ||
b6016b76 | 6007 | static void |
48b01e2d | 6008 | bnx2_5706_serdes_timer(struct bnx2 *bp) |
b6016b76 | 6009 | { |
b2fadeae MC |
6010 | int check_link = 1; |
6011 | ||
48b01e2d | 6012 | spin_lock(&bp->phy_lock); |
b2fadeae | 6013 | if (bp->serdes_an_pending) { |
48b01e2d | 6014 | bp->serdes_an_pending--; |
b2fadeae MC |
6015 | check_link = 0; |
6016 | } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { | |
48b01e2d | 6017 | u32 bmcr; |
b6016b76 | 6018 | |
ac392abc | 6019 | bp->current_interval = BNX2_TIMER_INTERVAL; |
cd339a0e | 6020 | |
ca58c3af | 6021 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 | 6022 | |
48b01e2d | 6023 | if (bmcr & BMCR_ANENABLE) { |
b2fadeae | 6024 | if (bnx2_5706_serdes_has_link(bp)) { |
48b01e2d MC |
6025 | bmcr &= ~BMCR_ANENABLE; |
6026 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
ca58c3af | 6027 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); |
583c28e5 | 6028 | bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT; |
48b01e2d | 6029 | } |
b6016b76 | 6030 | } |
48b01e2d MC |
6031 | } |
6032 | else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && | |
583c28e5 | 6033 | (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) { |
48b01e2d | 6034 | u32 phy2; |
b6016b76 | 6035 | |
48b01e2d MC |
6036 | bnx2_write_phy(bp, 0x17, 0x0f01); |
6037 | bnx2_read_phy(bp, 0x15, &phy2); | |
6038 | if (phy2 & 0x20) { | |
6039 | u32 bmcr; | |
cd339a0e | 6040 | |
ca58c3af | 6041 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
48b01e2d | 6042 | bmcr |= BMCR_ANENABLE; |
ca58c3af | 6043 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); |
b6016b76 | 6044 | |
583c28e5 | 6045 | bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; |
48b01e2d MC |
6046 | } |
6047 | } else | |
ac392abc | 6048 | bp->current_interval = BNX2_TIMER_INTERVAL; |
b6016b76 | 6049 | |
a2724e25 | 6050 | if (check_link) { |
b2fadeae MC |
6051 | u32 val; |
6052 | ||
6053 | bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); | |
6054 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); | |
6055 | bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); | |
6056 | ||
a2724e25 MC |
6057 | if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) { |
6058 | if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) { | |
6059 | bnx2_5706s_force_link_dn(bp, 1); | |
6060 | bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN; | |
6061 | } else | |
6062 | bnx2_set_link(bp); | |
6063 | } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC)) | |
6064 | bnx2_set_link(bp); | |
b2fadeae | 6065 | } |
48b01e2d MC |
6066 | spin_unlock(&bp->phy_lock); |
6067 | } | |
b6016b76 | 6068 | |
f8dd064e MC |
6069 | static void |
6070 | bnx2_5708_serdes_timer(struct bnx2 *bp) | |
6071 | { | |
583c28e5 | 6072 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
0d8a6571 MC |
6073 | return; |
6074 | ||
583c28e5 | 6075 | if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) { |
f8dd064e MC |
6076 | bp->serdes_an_pending = 0; |
6077 | return; | |
6078 | } | |
b6016b76 | 6079 | |
f8dd064e MC |
6080 | spin_lock(&bp->phy_lock); |
6081 | if (bp->serdes_an_pending) | |
6082 | bp->serdes_an_pending--; | |
6083 | else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { | |
6084 | u32 bmcr; | |
b6016b76 | 6085 | |
ca58c3af | 6086 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
f8dd064e | 6087 | if (bmcr & BMCR_ANENABLE) { |
605a9e20 | 6088 | bnx2_enable_forced_2g5(bp); |
40105c0b | 6089 | bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT; |
f8dd064e | 6090 | } else { |
605a9e20 | 6091 | bnx2_disable_forced_2g5(bp); |
f8dd064e | 6092 | bp->serdes_an_pending = 2; |
ac392abc | 6093 | bp->current_interval = BNX2_TIMER_INTERVAL; |
b6016b76 | 6094 | } |
b6016b76 | 6095 | |
f8dd064e | 6096 | } else |
ac392abc | 6097 | bp->current_interval = BNX2_TIMER_INTERVAL; |
b6016b76 | 6098 | |
f8dd064e MC |
6099 | spin_unlock(&bp->phy_lock); |
6100 | } | |
6101 | ||
48b01e2d MC |
6102 | static void |
6103 | bnx2_timer(unsigned long data) | |
6104 | { | |
6105 | struct bnx2 *bp = (struct bnx2 *) data; | |
b6016b76 | 6106 | |
48b01e2d MC |
6107 | if (!netif_running(bp->dev)) |
6108 | return; | |
b6016b76 | 6109 | |
48b01e2d MC |
6110 | if (atomic_read(&bp->intr_sem) != 0) |
6111 | goto bnx2_restart_timer; | |
b6016b76 | 6112 | |
efba0180 MC |
6113 | if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) == |
6114 | BNX2_FLAG_USING_MSI) | |
6115 | bnx2_chk_missed_msi(bp); | |
6116 | ||
df149d70 | 6117 | bnx2_send_heart_beat(bp); |
b6016b76 | 6118 | |
2726d6e1 MC |
6119 | bp->stats_blk->stat_FwRxDrop = |
6120 | bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT); | |
b6016b76 | 6121 | |
02537b06 | 6122 | /* workaround occasional corrupted counters */ |
61d9e3fa | 6123 | if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks) |
e503e066 MC |
6124 | BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | |
6125 | BNX2_HC_COMMAND_STATS_NOW); | |
02537b06 | 6126 | |
583c28e5 | 6127 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
4ce45e02 | 6128 | if (BNX2_CHIP(bp) == BNX2_CHIP_5706) |
f8dd064e | 6129 | bnx2_5706_serdes_timer(bp); |
27a005b8 | 6130 | else |
f8dd064e | 6131 | bnx2_5708_serdes_timer(bp); |
b6016b76 MC |
6132 | } |
6133 | ||
6134 | bnx2_restart_timer: | |
cd339a0e | 6135 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
b6016b76 MC |
6136 | } |
6137 | ||
8e6a72c4 MC |
6138 | static int |
6139 | bnx2_request_irq(struct bnx2 *bp) | |
6140 | { | |
6d866ffc | 6141 | unsigned long flags; |
b4b36042 MC |
6142 | struct bnx2_irq *irq; |
6143 | int rc = 0, i; | |
8e6a72c4 | 6144 | |
f86e82fb | 6145 | if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX) |
6d866ffc MC |
6146 | flags = 0; |
6147 | else | |
6148 | flags = IRQF_SHARED; | |
b4b36042 MC |
6149 | |
6150 | for (i = 0; i < bp->irq_nvecs; i++) { | |
6151 | irq = &bp->irq_tbl[i]; | |
c76c0475 | 6152 | rc = request_irq(irq->vector, irq->handler, flags, irq->name, |
f0ea2e63 | 6153 | &bp->bnx2_napi[i]); |
b4b36042 MC |
6154 | if (rc) |
6155 | break; | |
6156 | irq->requested = 1; | |
6157 | } | |
8e6a72c4 MC |
6158 | return rc; |
6159 | } | |
6160 | ||
6161 | static void | |
a29ba9d2 | 6162 | __bnx2_free_irq(struct bnx2 *bp) |
8e6a72c4 | 6163 | { |
b4b36042 MC |
6164 | struct bnx2_irq *irq; |
6165 | int i; | |
8e6a72c4 | 6166 | |
b4b36042 MC |
6167 | for (i = 0; i < bp->irq_nvecs; i++) { |
6168 | irq = &bp->irq_tbl[i]; | |
6169 | if (irq->requested) | |
f0ea2e63 | 6170 | free_irq(irq->vector, &bp->bnx2_napi[i]); |
b4b36042 | 6171 | irq->requested = 0; |
6d866ffc | 6172 | } |
a29ba9d2 MC |
6173 | } |
6174 | ||
6175 | static void | |
6176 | bnx2_free_irq(struct bnx2 *bp) | |
6177 | { | |
6178 | ||
6179 | __bnx2_free_irq(bp); | |
f86e82fb | 6180 | if (bp->flags & BNX2_FLAG_USING_MSI) |
b4b36042 | 6181 | pci_disable_msi(bp->pdev); |
f86e82fb | 6182 | else if (bp->flags & BNX2_FLAG_USING_MSIX) |
b4b36042 MC |
6183 | pci_disable_msix(bp->pdev); |
6184 | ||
f86e82fb | 6185 | bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI); |
b4b36042 MC |
6186 | } |
6187 | ||
6188 | static void | |
5e9ad9e1 | 6189 | bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) |
b4b36042 | 6190 | { |
379b39a2 | 6191 | int i, total_vecs, rc; |
57851d84 | 6192 | struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC]; |
4e1d0de9 MC |
6193 | struct net_device *dev = bp->dev; |
6194 | const int len = sizeof(bp->irq_tbl[0].name); | |
57851d84 | 6195 | |
b4b36042 | 6196 | bnx2_setup_msix_tbl(bp); |
e503e066 MC |
6197 | BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); |
6198 | BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE); | |
6199 | BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE); | |
57851d84 | 6200 | |
e2eb8e38 BL |
6201 | /* Need to flush the previous three writes to ensure MSI-X |
6202 | * is setup properly */ | |
e503e066 | 6203 | BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL); |
e2eb8e38 | 6204 | |
57851d84 MC |
6205 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { |
6206 | msix_ent[i].entry = i; | |
6207 | msix_ent[i].vector = 0; | |
6208 | } | |
6209 | ||
379b39a2 MC |
6210 | total_vecs = msix_vecs; |
6211 | #ifdef BCM_CNIC | |
6212 | total_vecs++; | |
6213 | #endif | |
6214 | rc = -ENOSPC; | |
6215 | while (total_vecs >= BNX2_MIN_MSIX_VEC) { | |
6216 | rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs); | |
6217 | if (rc <= 0) | |
6218 | break; | |
6219 | if (rc > 0) | |
6220 | total_vecs = rc; | |
6221 | } | |
6222 | ||
57851d84 MC |
6223 | if (rc != 0) |
6224 | return; | |
6225 | ||
379b39a2 MC |
6226 | msix_vecs = total_vecs; |
6227 | #ifdef BCM_CNIC | |
6228 | msix_vecs--; | |
6229 | #endif | |
5e9ad9e1 | 6230 | bp->irq_nvecs = msix_vecs; |
f86e82fb | 6231 | bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; |
379b39a2 | 6232 | for (i = 0; i < total_vecs; i++) { |
57851d84 | 6233 | bp->irq_tbl[i].vector = msix_ent[i].vector; |
69010313 MC |
6234 | snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); |
6235 | bp->irq_tbl[i].handler = bnx2_msi_1shot; | |
6236 | } | |
6d866ffc MC |
6237 | } |
6238 | ||
657d92fe | 6239 | static int |
6d866ffc MC |
6240 | bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) |
6241 | { | |
0a742128 | 6242 | int cpus = netif_get_num_default_rss_queues(); |
b033281f MC |
6243 | int msix_vecs; |
6244 | ||
6245 | if (!bp->num_req_rx_rings) | |
6246 | msix_vecs = max(cpus + 1, bp->num_req_tx_rings); | |
6247 | else if (!bp->num_req_tx_rings) | |
6248 | msix_vecs = max(cpus, bp->num_req_rx_rings); | |
6249 | else | |
6250 | msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings); | |
6251 | ||
6252 | msix_vecs = min(msix_vecs, RX_MAX_RINGS); | |
5e9ad9e1 | 6253 | |
6d866ffc MC |
6254 | bp->irq_tbl[0].handler = bnx2_interrupt; |
6255 | strcpy(bp->irq_tbl[0].name, bp->dev->name); | |
b4b36042 MC |
6256 | bp->irq_nvecs = 1; |
6257 | bp->irq_tbl[0].vector = bp->pdev->irq; | |
6258 | ||
3d5f3a7b | 6259 | if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi) |
5e9ad9e1 | 6260 | bnx2_enable_msix(bp, msix_vecs); |
6d866ffc | 6261 | |
f86e82fb DM |
6262 | if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi && |
6263 | !(bp->flags & BNX2_FLAG_USING_MSIX)) { | |
6d866ffc | 6264 | if (pci_enable_msi(bp->pdev) == 0) { |
f86e82fb | 6265 | bp->flags |= BNX2_FLAG_USING_MSI; |
4ce45e02 | 6266 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
f86e82fb | 6267 | bp->flags |= BNX2_FLAG_ONE_SHOT_MSI; |
6d866ffc MC |
6268 | bp->irq_tbl[0].handler = bnx2_msi_1shot; |
6269 | } else | |
6270 | bp->irq_tbl[0].handler = bnx2_msi; | |
b4b36042 MC |
6271 | |
6272 | bp->irq_tbl[0].vector = bp->pdev->irq; | |
6d866ffc MC |
6273 | } |
6274 | } | |
706bf240 | 6275 | |
b033281f MC |
6276 | if (!bp->num_req_tx_rings) |
6277 | bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs); | |
6278 | else | |
6279 | bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings); | |
6280 | ||
6281 | if (!bp->num_req_rx_rings) | |
6282 | bp->num_rx_rings = bp->irq_nvecs; | |
6283 | else | |
6284 | bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings); | |
6285 | ||
657d92fe | 6286 | netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings); |
706bf240 | 6287 | |
657d92fe | 6288 | return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings); |
8e6a72c4 MC |
6289 | } |
6290 | ||
b6016b76 MC |
6291 | /* Called with rtnl_lock */ |
6292 | static int | |
6293 | bnx2_open(struct net_device *dev) | |
6294 | { | |
972ec0d4 | 6295 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6296 | int rc; |
6297 | ||
7880b72e | 6298 | rc = bnx2_request_firmware(bp); |
6299 | if (rc < 0) | |
6300 | goto out; | |
6301 | ||
1b2f922f MC |
6302 | netif_carrier_off(dev); |
6303 | ||
829ca9a3 | 6304 | bnx2_set_power_state(bp, PCI_D0); |
b6016b76 MC |
6305 | bnx2_disable_int(bp); |
6306 | ||
657d92fe BH |
6307 | rc = bnx2_setup_int_mode(bp, disable_msi); |
6308 | if (rc) | |
6309 | goto open_err; | |
4327ba43 | 6310 | bnx2_init_napi(bp); |
35e9010b | 6311 | bnx2_napi_enable(bp); |
b6016b76 | 6312 | rc = bnx2_alloc_mem(bp); |
2739a8bb MC |
6313 | if (rc) |
6314 | goto open_err; | |
b6016b76 | 6315 | |
8e6a72c4 | 6316 | rc = bnx2_request_irq(bp); |
2739a8bb MC |
6317 | if (rc) |
6318 | goto open_err; | |
b6016b76 | 6319 | |
9a120bc5 | 6320 | rc = bnx2_init_nic(bp, 1); |
2739a8bb MC |
6321 | if (rc) |
6322 | goto open_err; | |
6aa20a22 | 6323 | |
cd339a0e | 6324 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
b6016b76 MC |
6325 | |
6326 | atomic_set(&bp->intr_sem, 0); | |
6327 | ||
354fcd77 MC |
6328 | memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block)); |
6329 | ||
b6016b76 MC |
6330 | bnx2_enable_int(bp); |
6331 | ||
f86e82fb | 6332 | if (bp->flags & BNX2_FLAG_USING_MSI) { |
b6016b76 MC |
6333 | /* Test MSI to make sure it is working |
6334 | * If MSI test fails, go back to INTx mode | |
6335 | */ | |
6336 | if (bnx2_test_intr(bp) != 0) { | |
3a9c6a49 | 6337 | netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n"); |
b6016b76 MC |
6338 | |
6339 | bnx2_disable_int(bp); | |
8e6a72c4 | 6340 | bnx2_free_irq(bp); |
b6016b76 | 6341 | |
6d866ffc MC |
6342 | bnx2_setup_int_mode(bp, 1); |
6343 | ||
9a120bc5 | 6344 | rc = bnx2_init_nic(bp, 0); |
b6016b76 | 6345 | |
8e6a72c4 MC |
6346 | if (!rc) |
6347 | rc = bnx2_request_irq(bp); | |
6348 | ||
b6016b76 | 6349 | if (rc) { |
b6016b76 | 6350 | del_timer_sync(&bp->timer); |
2739a8bb | 6351 | goto open_err; |
b6016b76 MC |
6352 | } |
6353 | bnx2_enable_int(bp); | |
6354 | } | |
6355 | } | |
f86e82fb | 6356 | if (bp->flags & BNX2_FLAG_USING_MSI) |
3a9c6a49 | 6357 | netdev_info(dev, "using MSI\n"); |
f86e82fb | 6358 | else if (bp->flags & BNX2_FLAG_USING_MSIX) |
3a9c6a49 | 6359 | netdev_info(dev, "using MSIX\n"); |
b6016b76 | 6360 | |
706bf240 | 6361 | netif_tx_start_all_queues(dev); |
7880b72e | 6362 | out: |
6363 | return rc; | |
2739a8bb MC |
6364 | |
6365 | open_err: | |
6366 | bnx2_napi_disable(bp); | |
6367 | bnx2_free_skbs(bp); | |
6368 | bnx2_free_irq(bp); | |
6369 | bnx2_free_mem(bp); | |
f048fa9c | 6370 | bnx2_del_napi(bp); |
7880b72e | 6371 | bnx2_release_firmware(bp); |
6372 | goto out; | |
b6016b76 MC |
6373 | } |
6374 | ||
6375 | static void | |
c4028958 | 6376 | bnx2_reset_task(struct work_struct *work) |
b6016b76 | 6377 | { |
c4028958 | 6378 | struct bnx2 *bp = container_of(work, struct bnx2, reset_task); |
cd634019 | 6379 | int rc; |
efdfad32 | 6380 | u16 pcicmd; |
b6016b76 | 6381 | |
51bf6bb4 MC |
6382 | rtnl_lock(); |
6383 | if (!netif_running(bp->dev)) { | |
6384 | rtnl_unlock(); | |
afdc08b9 | 6385 | return; |
51bf6bb4 | 6386 | } |
afdc08b9 | 6387 | |
212f9934 | 6388 | bnx2_netif_stop(bp, true); |
b6016b76 | 6389 | |
efdfad32 MC |
6390 | pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd); |
6391 | if (!(pcicmd & PCI_COMMAND_MEMORY)) { | |
6392 | /* in case PCI block has reset */ | |
6393 | pci_restore_state(bp->pdev); | |
6394 | pci_save_state(bp->pdev); | |
6395 | } | |
cd634019 MC |
6396 | rc = bnx2_init_nic(bp, 1); |
6397 | if (rc) { | |
6398 | netdev_err(bp->dev, "failed to reset NIC, closing\n"); | |
6399 | bnx2_napi_enable(bp); | |
6400 | dev_close(bp->dev); | |
6401 | rtnl_unlock(); | |
6402 | return; | |
6403 | } | |
b6016b76 MC |
6404 | |
6405 | atomic_set(&bp->intr_sem, 1); | |
212f9934 | 6406 | bnx2_netif_start(bp, true); |
51bf6bb4 | 6407 | rtnl_unlock(); |
b6016b76 MC |
6408 | } |
6409 | ||
555069da MC |
6410 | #define BNX2_FTQ_ENTRY(ftq) { __stringify(ftq##FTQ_CTL), BNX2_##ftq##FTQ_CTL } |
6411 | ||
6412 | static void | |
6413 | bnx2_dump_ftq(struct bnx2 *bp) | |
6414 | { | |
6415 | int i; | |
6416 | u32 reg, bdidx, cid, valid; | |
6417 | struct net_device *dev = bp->dev; | |
6418 | static const struct ftq_reg { | |
6419 | char *name; | |
6420 | u32 off; | |
6421 | } ftq_arr[] = { | |
6422 | BNX2_FTQ_ENTRY(RV2P_P), | |
6423 | BNX2_FTQ_ENTRY(RV2P_T), | |
6424 | BNX2_FTQ_ENTRY(RV2P_M), | |
6425 | BNX2_FTQ_ENTRY(TBDR_), | |
6426 | BNX2_FTQ_ENTRY(TDMA_), | |
6427 | BNX2_FTQ_ENTRY(TXP_), | |
6428 | BNX2_FTQ_ENTRY(TXP_), | |
6429 | BNX2_FTQ_ENTRY(TPAT_), | |
6430 | BNX2_FTQ_ENTRY(RXP_C), | |
6431 | BNX2_FTQ_ENTRY(RXP_), | |
6432 | BNX2_FTQ_ENTRY(COM_COMXQ_), | |
6433 | BNX2_FTQ_ENTRY(COM_COMTQ_), | |
6434 | BNX2_FTQ_ENTRY(COM_COMQ_), | |
6435 | BNX2_FTQ_ENTRY(CP_CPQ_), | |
6436 | }; | |
6437 | ||
6438 | netdev_err(dev, "<--- start FTQ dump --->\n"); | |
6439 | for (i = 0; i < ARRAY_SIZE(ftq_arr); i++) | |
6440 | netdev_err(dev, "%s %08x\n", ftq_arr[i].name, | |
6441 | bnx2_reg_rd_ind(bp, ftq_arr[i].off)); | |
6442 | ||
6443 | netdev_err(dev, "CPU states:\n"); | |
6444 | for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000) | |
6445 | netdev_err(dev, "%06x mode %x state %x evt_mask %x pc %x pc %x instr %x\n", | |
6446 | reg, bnx2_reg_rd_ind(bp, reg), | |
6447 | bnx2_reg_rd_ind(bp, reg + 4), | |
6448 | bnx2_reg_rd_ind(bp, reg + 8), | |
6449 | bnx2_reg_rd_ind(bp, reg + 0x1c), | |
6450 | bnx2_reg_rd_ind(bp, reg + 0x1c), | |
6451 | bnx2_reg_rd_ind(bp, reg + 0x20)); | |
6452 | ||
6453 | netdev_err(dev, "<--- end FTQ dump --->\n"); | |
6454 | netdev_err(dev, "<--- start TBDC dump --->\n"); | |
6455 | netdev_err(dev, "TBDC free cnt: %ld\n", | |
e503e066 | 6456 | BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT); |
555069da MC |
6457 | netdev_err(dev, "LINE CID BIDX CMD VALIDS\n"); |
6458 | for (i = 0; i < 0x20; i++) { | |
6459 | int j = 0; | |
6460 | ||
e503e066 MC |
6461 | BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i); |
6462 | BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE, | |
6463 | BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ); | |
6464 | BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB); | |
6465 | while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) & | |
555069da MC |
6466 | BNX2_TBDC_COMMAND_CMD_REG_ARB) && j < 100) |
6467 | j++; | |
6468 | ||
e503e066 MC |
6469 | cid = BNX2_RD(bp, BNX2_TBDC_CID); |
6470 | bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX); | |
6471 | valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE); | |
555069da MC |
6472 | netdev_err(dev, "%02x %06x %04lx %02x [%x]\n", |
6473 | i, cid, bdidx & BNX2_TBDC_BDIDX_BDIDX, | |
6474 | bdidx >> 24, (valid >> 8) & 0x0ff); | |
6475 | } | |
6476 | netdev_err(dev, "<--- end TBDC dump --->\n"); | |
6477 | } | |
6478 | ||
20175c57 MC |
6479 | static void |
6480 | bnx2_dump_state(struct bnx2 *bp) | |
6481 | { | |
6482 | struct net_device *dev = bp->dev; | |
ecdbf6e0 | 6483 | u32 val1, val2; |
5804a8fb MC |
6484 | |
6485 | pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1); | |
6486 | netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n", | |
6487 | atomic_read(&bp->intr_sem), val1); | |
6488 | pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1); | |
6489 | pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2); | |
6490 | netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2); | |
b98eba52 | 6491 | netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n", |
e503e066 MC |
6492 | BNX2_RD(bp, BNX2_EMAC_TX_STATUS), |
6493 | BNX2_RD(bp, BNX2_EMAC_RX_STATUS)); | |
b98eba52 | 6494 | netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n", |
e503e066 | 6495 | BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL)); |
3a9c6a49 | 6496 | netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n", |
e503e066 | 6497 | BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS)); |
20175c57 | 6498 | if (bp->flags & BNX2_FLAG_USING_MSIX) |
3a9c6a49 | 6499 | netdev_err(dev, "DEBUG: PBA[%08x]\n", |
e503e066 | 6500 | BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE)); |
20175c57 MC |
6501 | } |
6502 | ||
b6016b76 MC |
6503 | static void |
6504 | bnx2_tx_timeout(struct net_device *dev) | |
6505 | { | |
972ec0d4 | 6506 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6507 | |
555069da | 6508 | bnx2_dump_ftq(bp); |
20175c57 | 6509 | bnx2_dump_state(bp); |
ecdbf6e0 | 6510 | bnx2_dump_mcp_state(bp); |
20175c57 | 6511 | |
b6016b76 MC |
6512 | /* This allows the netif to be shutdown gracefully before resetting */ |
6513 | schedule_work(&bp->reset_task); | |
6514 | } | |
6515 | ||
932ff279 | 6516 | /* Called with netif_tx_lock. |
2f8af120 MC |
6517 | * bnx2_tx_int() runs without netif_tx_lock unless it needs to call |
6518 | * netif_wake_queue(). | |
b6016b76 | 6519 | */ |
61357325 | 6520 | static netdev_tx_t |
b6016b76 MC |
6521 | bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) |
6522 | { | |
972ec0d4 | 6523 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6524 | dma_addr_t mapping; |
2bc4078e MC |
6525 | struct bnx2_tx_bd *txbd; |
6526 | struct bnx2_sw_tx_bd *tx_buf; | |
b6016b76 MC |
6527 | u32 len, vlan_tag_flags, last_frag, mss; |
6528 | u16 prod, ring_prod; | |
6529 | int i; | |
706bf240 BL |
6530 | struct bnx2_napi *bnapi; |
6531 | struct bnx2_tx_ring_info *txr; | |
6532 | struct netdev_queue *txq; | |
6533 | ||
6534 | /* Determine which tx ring we will be placed on */ | |
6535 | i = skb_get_queue_mapping(skb); | |
6536 | bnapi = &bp->bnx2_napi[i]; | |
6537 | txr = &bnapi->tx_ring; | |
6538 | txq = netdev_get_tx_queue(dev, i); | |
b6016b76 | 6539 | |
35e9010b | 6540 | if (unlikely(bnx2_tx_avail(bp, txr) < |
a550c99b | 6541 | (skb_shinfo(skb)->nr_frags + 1))) { |
706bf240 | 6542 | netif_tx_stop_queue(txq); |
3a9c6a49 | 6543 | netdev_err(dev, "BUG! Tx ring full when queue awake!\n"); |
b6016b76 MC |
6544 | |
6545 | return NETDEV_TX_BUSY; | |
6546 | } | |
6547 | len = skb_headlen(skb); | |
35e9010b | 6548 | prod = txr->tx_prod; |
2bc4078e | 6549 | ring_prod = BNX2_TX_RING_IDX(prod); |
b6016b76 MC |
6550 | |
6551 | vlan_tag_flags = 0; | |
84fa7933 | 6552 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
b6016b76 MC |
6553 | vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; |
6554 | } | |
6555 | ||
eab6d18d | 6556 | if (vlan_tx_tag_present(skb)) { |
b6016b76 MC |
6557 | vlan_tag_flags |= |
6558 | (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); | |
6559 | } | |
7d0fd211 | 6560 | |
fde82055 | 6561 | if ((mss = skb_shinfo(skb)->gso_size)) { |
a1efb4b6 | 6562 | u32 tcp_opt_len; |
eddc9ec5 | 6563 | struct iphdr *iph; |
b6016b76 | 6564 | |
b6016b76 MC |
6565 | vlan_tag_flags |= TX_BD_FLAGS_SW_LSO; |
6566 | ||
4666f87a MC |
6567 | tcp_opt_len = tcp_optlen(skb); |
6568 | ||
6569 | if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { | |
6570 | u32 tcp_off = skb_transport_offset(skb) - | |
6571 | sizeof(struct ipv6hdr) - ETH_HLEN; | |
ab6a5bb6 | 6572 | |
4666f87a MC |
6573 | vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) | |
6574 | TX_BD_FLAGS_SW_FLAGS; | |
6575 | if (likely(tcp_off == 0)) | |
6576 | vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK; | |
6577 | else { | |
6578 | tcp_off >>= 3; | |
6579 | vlan_tag_flags |= ((tcp_off & 0x3) << | |
6580 | TX_BD_FLAGS_TCP6_OFF0_SHL) | | |
6581 | ((tcp_off & 0x10) << | |
6582 | TX_BD_FLAGS_TCP6_OFF4_SHL); | |
6583 | mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL; | |
6584 | } | |
6585 | } else { | |
4666f87a | 6586 | iph = ip_hdr(skb); |
4666f87a MC |
6587 | if (tcp_opt_len || (iph->ihl > 5)) { |
6588 | vlan_tag_flags |= ((iph->ihl - 5) + | |
6589 | (tcp_opt_len >> 2)) << 8; | |
6590 | } | |
b6016b76 | 6591 | } |
4666f87a | 6592 | } else |
b6016b76 | 6593 | mss = 0; |
b6016b76 | 6594 | |
36227e88 SG |
6595 | mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE); |
6596 | if (dma_mapping_error(&bp->pdev->dev, mapping)) { | |
3d16af86 BL |
6597 | dev_kfree_skb(skb); |
6598 | return NETDEV_TX_OK; | |
6599 | } | |
6600 | ||
35e9010b | 6601 | tx_buf = &txr->tx_buf_ring[ring_prod]; |
b6016b76 | 6602 | tx_buf->skb = skb; |
1a4ccc2d | 6603 | dma_unmap_addr_set(tx_buf, mapping, mapping); |
b6016b76 | 6604 | |
35e9010b | 6605 | txbd = &txr->tx_desc_ring[ring_prod]; |
b6016b76 MC |
6606 | |
6607 | txbd->tx_bd_haddr_hi = (u64) mapping >> 32; | |
6608 | txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
6609 | txbd->tx_bd_mss_nbytes = len | (mss << 16); | |
6610 | txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START; | |
6611 | ||
6612 | last_frag = skb_shinfo(skb)->nr_frags; | |
d62fda08 ED |
6613 | tx_buf->nr_frags = last_frag; |
6614 | tx_buf->is_gso = skb_is_gso(skb); | |
b6016b76 MC |
6615 | |
6616 | for (i = 0; i < last_frag; i++) { | |
9e903e08 | 6617 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
b6016b76 | 6618 | |
2bc4078e MC |
6619 | prod = BNX2_NEXT_TX_BD(prod); |
6620 | ring_prod = BNX2_TX_RING_IDX(prod); | |
35e9010b | 6621 | txbd = &txr->tx_desc_ring[ring_prod]; |
b6016b76 | 6622 | |
9e903e08 | 6623 | len = skb_frag_size(frag); |
b7b6a688 | 6624 | mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len, |
5d6bcdfe | 6625 | DMA_TO_DEVICE); |
36227e88 | 6626 | if (dma_mapping_error(&bp->pdev->dev, mapping)) |
e95524a7 | 6627 | goto dma_error; |
1a4ccc2d | 6628 | dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping, |
e95524a7 | 6629 | mapping); |
b6016b76 MC |
6630 | |
6631 | txbd->tx_bd_haddr_hi = (u64) mapping >> 32; | |
6632 | txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; | |
6633 | txbd->tx_bd_mss_nbytes = len | (mss << 16); | |
6634 | txbd->tx_bd_vlan_tag_flags = vlan_tag_flags; | |
6635 | ||
6636 | } | |
6637 | txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; | |
6638 | ||
94bf91ba VZ |
6639 | /* Sync BD data before updating TX mailbox */ |
6640 | wmb(); | |
6641 | ||
e9831909 ED |
6642 | netdev_tx_sent_queue(txq, skb->len); |
6643 | ||
2bc4078e | 6644 | prod = BNX2_NEXT_TX_BD(prod); |
35e9010b | 6645 | txr->tx_prod_bseq += skb->len; |
b6016b76 | 6646 | |
e503e066 MC |
6647 | BNX2_WR16(bp, txr->tx_bidx_addr, prod); |
6648 | BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); | |
b6016b76 MC |
6649 | |
6650 | mmiowb(); | |
6651 | ||
35e9010b | 6652 | txr->tx_prod = prod; |
b6016b76 | 6653 | |
35e9010b | 6654 | if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) { |
706bf240 | 6655 | netif_tx_stop_queue(txq); |
11848b96 MC |
6656 | |
6657 | /* netif_tx_stop_queue() must be done before checking | |
6658 | * tx index in bnx2_tx_avail() below, because in | |
6659 | * bnx2_tx_int(), we update tx index before checking for | |
6660 | * netif_tx_queue_stopped(). | |
6661 | */ | |
6662 | smp_mb(); | |
35e9010b | 6663 | if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh) |
706bf240 | 6664 | netif_tx_wake_queue(txq); |
b6016b76 MC |
6665 | } |
6666 | ||
e95524a7 AD |
6667 | return NETDEV_TX_OK; |
6668 | dma_error: | |
6669 | /* save value of frag that failed */ | |
6670 | last_frag = i; | |
6671 | ||
6672 | /* start back at beginning and unmap skb */ | |
6673 | prod = txr->tx_prod; | |
2bc4078e | 6674 | ring_prod = BNX2_TX_RING_IDX(prod); |
e95524a7 AD |
6675 | tx_buf = &txr->tx_buf_ring[ring_prod]; |
6676 | tx_buf->skb = NULL; | |
36227e88 | 6677 | dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), |
e95524a7 AD |
6678 | skb_headlen(skb), PCI_DMA_TODEVICE); |
6679 | ||
6680 | /* unmap remaining mapped pages */ | |
6681 | for (i = 0; i < last_frag; i++) { | |
2bc4078e MC |
6682 | prod = BNX2_NEXT_TX_BD(prod); |
6683 | ring_prod = BNX2_TX_RING_IDX(prod); | |
e95524a7 | 6684 | tx_buf = &txr->tx_buf_ring[ring_prod]; |
36227e88 | 6685 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), |
9e903e08 | 6686 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
e95524a7 AD |
6687 | PCI_DMA_TODEVICE); |
6688 | } | |
6689 | ||
6690 | dev_kfree_skb(skb); | |
b6016b76 MC |
6691 | return NETDEV_TX_OK; |
6692 | } | |
6693 | ||
6694 | /* Called with rtnl_lock */ | |
6695 | static int | |
6696 | bnx2_close(struct net_device *dev) | |
6697 | { | |
972ec0d4 | 6698 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6699 | |
bea3348e | 6700 | bnx2_disable_int_sync(bp); |
35efa7c1 | 6701 | bnx2_napi_disable(bp); |
d2e553bc | 6702 | netif_tx_disable(dev); |
b6016b76 | 6703 | del_timer_sync(&bp->timer); |
74bf4ba3 | 6704 | bnx2_shutdown_chip(bp); |
8e6a72c4 | 6705 | bnx2_free_irq(bp); |
b6016b76 MC |
6706 | bnx2_free_skbs(bp); |
6707 | bnx2_free_mem(bp); | |
f048fa9c | 6708 | bnx2_del_napi(bp); |
b6016b76 MC |
6709 | bp->link_up = 0; |
6710 | netif_carrier_off(bp->dev); | |
829ca9a3 | 6711 | bnx2_set_power_state(bp, PCI_D3hot); |
b6016b76 MC |
6712 | return 0; |
6713 | } | |
6714 | ||
354fcd77 MC |
6715 | static void |
6716 | bnx2_save_stats(struct bnx2 *bp) | |
6717 | { | |
6718 | u32 *hw_stats = (u32 *) bp->stats_blk; | |
6719 | u32 *temp_stats = (u32 *) bp->temp_stats_blk; | |
6720 | int i; | |
6721 | ||
6722 | /* The 1st 10 counters are 64-bit counters */ | |
6723 | for (i = 0; i < 20; i += 2) { | |
6724 | u32 hi; | |
6725 | u64 lo; | |
6726 | ||
c9885fe5 PR |
6727 | hi = temp_stats[i] + hw_stats[i]; |
6728 | lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1]; | |
354fcd77 MC |
6729 | if (lo > 0xffffffff) |
6730 | hi++; | |
c9885fe5 PR |
6731 | temp_stats[i] = hi; |
6732 | temp_stats[i + 1] = lo & 0xffffffff; | |
354fcd77 MC |
6733 | } |
6734 | ||
6735 | for ( ; i < sizeof(struct statistics_block) / 4; i++) | |
c9885fe5 | 6736 | temp_stats[i] += hw_stats[i]; |
354fcd77 MC |
6737 | } |
6738 | ||
5d07bf26 ED |
6739 | #define GET_64BIT_NET_STATS64(ctr) \ |
6740 | (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo)) | |
b6016b76 | 6741 | |
a4743058 | 6742 | #define GET_64BIT_NET_STATS(ctr) \ |
354fcd77 MC |
6743 | GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \ |
6744 | GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr) | |
b6016b76 | 6745 | |
a4743058 | 6746 | #define GET_32BIT_NET_STATS(ctr) \ |
354fcd77 MC |
6747 | (unsigned long) (bp->stats_blk->ctr + \ |
6748 | bp->temp_stats_blk->ctr) | |
a4743058 | 6749 | |
5d07bf26 ED |
6750 | static struct rtnl_link_stats64 * |
6751 | bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats) | |
b6016b76 | 6752 | { |
972ec0d4 | 6753 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6754 | |
5d07bf26 | 6755 | if (bp->stats_blk == NULL) |
b6016b76 | 6756 | return net_stats; |
5d07bf26 | 6757 | |
b6016b76 | 6758 | net_stats->rx_packets = |
a4743058 MC |
6759 | GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) + |
6760 | GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) + | |
6761 | GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts); | |
b6016b76 MC |
6762 | |
6763 | net_stats->tx_packets = | |
a4743058 MC |
6764 | GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) + |
6765 | GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) + | |
6766 | GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts); | |
b6016b76 MC |
6767 | |
6768 | net_stats->rx_bytes = | |
a4743058 | 6769 | GET_64BIT_NET_STATS(stat_IfHCInOctets); |
b6016b76 MC |
6770 | |
6771 | net_stats->tx_bytes = | |
a4743058 | 6772 | GET_64BIT_NET_STATS(stat_IfHCOutOctets); |
b6016b76 | 6773 | |
6aa20a22 | 6774 | net_stats->multicast = |
6fdae995 | 6775 | GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts); |
b6016b76 | 6776 | |
6aa20a22 | 6777 | net_stats->collisions = |
a4743058 | 6778 | GET_32BIT_NET_STATS(stat_EtherStatsCollisions); |
b6016b76 | 6779 | |
6aa20a22 | 6780 | net_stats->rx_length_errors = |
a4743058 MC |
6781 | GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) + |
6782 | GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts); | |
b6016b76 | 6783 | |
6aa20a22 | 6784 | net_stats->rx_over_errors = |
a4743058 MC |
6785 | GET_32BIT_NET_STATS(stat_IfInFTQDiscards) + |
6786 | GET_32BIT_NET_STATS(stat_IfInMBUFDiscards); | |
b6016b76 | 6787 | |
6aa20a22 | 6788 | net_stats->rx_frame_errors = |
a4743058 | 6789 | GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors); |
b6016b76 | 6790 | |
6aa20a22 | 6791 | net_stats->rx_crc_errors = |
a4743058 | 6792 | GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors); |
b6016b76 MC |
6793 | |
6794 | net_stats->rx_errors = net_stats->rx_length_errors + | |
6795 | net_stats->rx_over_errors + net_stats->rx_frame_errors + | |
6796 | net_stats->rx_crc_errors; | |
6797 | ||
6798 | net_stats->tx_aborted_errors = | |
a4743058 MC |
6799 | GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) + |
6800 | GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions); | |
b6016b76 | 6801 | |
4ce45e02 MC |
6802 | if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) || |
6803 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0)) | |
b6016b76 MC |
6804 | net_stats->tx_carrier_errors = 0; |
6805 | else { | |
6806 | net_stats->tx_carrier_errors = | |
a4743058 | 6807 | GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors); |
b6016b76 MC |
6808 | } |
6809 | ||
6810 | net_stats->tx_errors = | |
a4743058 | 6811 | GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) + |
b6016b76 MC |
6812 | net_stats->tx_aborted_errors + |
6813 | net_stats->tx_carrier_errors; | |
6814 | ||
cea94db9 | 6815 | net_stats->rx_missed_errors = |
a4743058 MC |
6816 | GET_32BIT_NET_STATS(stat_IfInFTQDiscards) + |
6817 | GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) + | |
6818 | GET_32BIT_NET_STATS(stat_FwRxDrop); | |
cea94db9 | 6819 | |
b6016b76 MC |
6820 | return net_stats; |
6821 | } | |
6822 | ||
6823 | /* All ethtool functions called with rtnl_lock */ | |
6824 | ||
6825 | static int | |
6826 | bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
6827 | { | |
972ec0d4 | 6828 | struct bnx2 *bp = netdev_priv(dev); |
7b6b8347 | 6829 | int support_serdes = 0, support_copper = 0; |
b6016b76 MC |
6830 | |
6831 | cmd->supported = SUPPORTED_Autoneg; | |
583c28e5 | 6832 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
7b6b8347 MC |
6833 | support_serdes = 1; |
6834 | support_copper = 1; | |
6835 | } else if (bp->phy_port == PORT_FIBRE) | |
6836 | support_serdes = 1; | |
6837 | else | |
6838 | support_copper = 1; | |
6839 | ||
6840 | if (support_serdes) { | |
b6016b76 MC |
6841 | cmd->supported |= SUPPORTED_1000baseT_Full | |
6842 | SUPPORTED_FIBRE; | |
583c28e5 | 6843 | if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) |
605a9e20 | 6844 | cmd->supported |= SUPPORTED_2500baseX_Full; |
b6016b76 | 6845 | |
b6016b76 | 6846 | } |
7b6b8347 | 6847 | if (support_copper) { |
b6016b76 MC |
6848 | cmd->supported |= SUPPORTED_10baseT_Half | |
6849 | SUPPORTED_10baseT_Full | | |
6850 | SUPPORTED_100baseT_Half | | |
6851 | SUPPORTED_100baseT_Full | | |
6852 | SUPPORTED_1000baseT_Full | | |
6853 | SUPPORTED_TP; | |
6854 | ||
b6016b76 MC |
6855 | } |
6856 | ||
7b6b8347 MC |
6857 | spin_lock_bh(&bp->phy_lock); |
6858 | cmd->port = bp->phy_port; | |
b6016b76 MC |
6859 | cmd->advertising = bp->advertising; |
6860 | ||
6861 | if (bp->autoneg & AUTONEG_SPEED) { | |
6862 | cmd->autoneg = AUTONEG_ENABLE; | |
70739497 | 6863 | } else { |
b6016b76 MC |
6864 | cmd->autoneg = AUTONEG_DISABLE; |
6865 | } | |
6866 | ||
6867 | if (netif_carrier_ok(dev)) { | |
70739497 | 6868 | ethtool_cmd_speed_set(cmd, bp->line_speed); |
b6016b76 MC |
6869 | cmd->duplex = bp->duplex; |
6870 | } | |
6871 | else { | |
70739497 | 6872 | ethtool_cmd_speed_set(cmd, -1); |
b6016b76 MC |
6873 | cmd->duplex = -1; |
6874 | } | |
7b6b8347 | 6875 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
6876 | |
6877 | cmd->transceiver = XCVR_INTERNAL; | |
6878 | cmd->phy_address = bp->phy_addr; | |
6879 | ||
6880 | return 0; | |
6881 | } | |
6aa20a22 | 6882 | |
b6016b76 MC |
6883 | static int |
6884 | bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
6885 | { | |
972ec0d4 | 6886 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
6887 | u8 autoneg = bp->autoneg; |
6888 | u8 req_duplex = bp->req_duplex; | |
6889 | u16 req_line_speed = bp->req_line_speed; | |
6890 | u32 advertising = bp->advertising; | |
7b6b8347 MC |
6891 | int err = -EINVAL; |
6892 | ||
6893 | spin_lock_bh(&bp->phy_lock); | |
6894 | ||
6895 | if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE) | |
6896 | goto err_out_unlock; | |
6897 | ||
583c28e5 MC |
6898 | if (cmd->port != bp->phy_port && |
6899 | !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)) | |
7b6b8347 | 6900 | goto err_out_unlock; |
b6016b76 | 6901 | |
d6b14486 MC |
6902 | /* If device is down, we can store the settings only if the user |
6903 | * is setting the currently active port. | |
6904 | */ | |
6905 | if (!netif_running(dev) && cmd->port != bp->phy_port) | |
6906 | goto err_out_unlock; | |
6907 | ||
b6016b76 MC |
6908 | if (cmd->autoneg == AUTONEG_ENABLE) { |
6909 | autoneg |= AUTONEG_SPEED; | |
6910 | ||
beb499af MC |
6911 | advertising = cmd->advertising; |
6912 | if (cmd->port == PORT_TP) { | |
6913 | advertising &= ETHTOOL_ALL_COPPER_SPEED; | |
6914 | if (!advertising) | |
b6016b76 | 6915 | advertising = ETHTOOL_ALL_COPPER_SPEED; |
beb499af MC |
6916 | } else { |
6917 | advertising &= ETHTOOL_ALL_FIBRE_SPEED; | |
6918 | if (!advertising) | |
6919 | advertising = ETHTOOL_ALL_FIBRE_SPEED; | |
b6016b76 MC |
6920 | } |
6921 | advertising |= ADVERTISED_Autoneg; | |
6922 | } | |
6923 | else { | |
25db0338 | 6924 | u32 speed = ethtool_cmd_speed(cmd); |
7b6b8347 | 6925 | if (cmd->port == PORT_FIBRE) { |
25db0338 DD |
6926 | if ((speed != SPEED_1000 && |
6927 | speed != SPEED_2500) || | |
80be4434 | 6928 | (cmd->duplex != DUPLEX_FULL)) |
7b6b8347 | 6929 | goto err_out_unlock; |
80be4434 | 6930 | |
25db0338 | 6931 | if (speed == SPEED_2500 && |
583c28e5 | 6932 | !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
7b6b8347 | 6933 | goto err_out_unlock; |
25db0338 | 6934 | } else if (speed == SPEED_1000 || speed == SPEED_2500) |
7b6b8347 MC |
6935 | goto err_out_unlock; |
6936 | ||
b6016b76 | 6937 | autoneg &= ~AUTONEG_SPEED; |
25db0338 | 6938 | req_line_speed = speed; |
b6016b76 MC |
6939 | req_duplex = cmd->duplex; |
6940 | advertising = 0; | |
6941 | } | |
6942 | ||
6943 | bp->autoneg = autoneg; | |
6944 | bp->advertising = advertising; | |
6945 | bp->req_line_speed = req_line_speed; | |
6946 | bp->req_duplex = req_duplex; | |
6947 | ||
d6b14486 MC |
6948 | err = 0; |
6949 | /* If device is down, the new settings will be picked up when it is | |
6950 | * brought up. | |
6951 | */ | |
6952 | if (netif_running(dev)) | |
6953 | err = bnx2_setup_phy(bp, cmd->port); | |
b6016b76 | 6954 | |
7b6b8347 | 6955 | err_out_unlock: |
c770a65c | 6956 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 | 6957 | |
7b6b8347 | 6958 | return err; |
b6016b76 MC |
6959 | } |
6960 | ||
6961 | static void | |
6962 | bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
6963 | { | |
972ec0d4 | 6964 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 6965 | |
68aad78c RJ |
6966 | strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); |
6967 | strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); | |
6968 | strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); | |
6969 | strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version)); | |
b6016b76 MC |
6970 | } |
6971 | ||
244ac4f4 MC |
6972 | #define BNX2_REGDUMP_LEN (32 * 1024) |
6973 | ||
6974 | static int | |
6975 | bnx2_get_regs_len(struct net_device *dev) | |
6976 | { | |
6977 | return BNX2_REGDUMP_LEN; | |
6978 | } | |
6979 | ||
6980 | static void | |
6981 | bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p) | |
6982 | { | |
6983 | u32 *p = _p, i, offset; | |
6984 | u8 *orig_p = _p; | |
6985 | struct bnx2 *bp = netdev_priv(dev); | |
b6bc7650 JP |
6986 | static const u32 reg_boundaries[] = { |
6987 | 0x0000, 0x0098, 0x0400, 0x045c, | |
6988 | 0x0800, 0x0880, 0x0c00, 0x0c10, | |
6989 | 0x0c30, 0x0d08, 0x1000, 0x101c, | |
6990 | 0x1040, 0x1048, 0x1080, 0x10a4, | |
6991 | 0x1400, 0x1490, 0x1498, 0x14f0, | |
6992 | 0x1500, 0x155c, 0x1580, 0x15dc, | |
6993 | 0x1600, 0x1658, 0x1680, 0x16d8, | |
6994 | 0x1800, 0x1820, 0x1840, 0x1854, | |
6995 | 0x1880, 0x1894, 0x1900, 0x1984, | |
6996 | 0x1c00, 0x1c0c, 0x1c40, 0x1c54, | |
6997 | 0x1c80, 0x1c94, 0x1d00, 0x1d84, | |
6998 | 0x2000, 0x2030, 0x23c0, 0x2400, | |
6999 | 0x2800, 0x2820, 0x2830, 0x2850, | |
7000 | 0x2b40, 0x2c10, 0x2fc0, 0x3058, | |
7001 | 0x3c00, 0x3c94, 0x4000, 0x4010, | |
7002 | 0x4080, 0x4090, 0x43c0, 0x4458, | |
7003 | 0x4c00, 0x4c18, 0x4c40, 0x4c54, | |
7004 | 0x4fc0, 0x5010, 0x53c0, 0x5444, | |
7005 | 0x5c00, 0x5c18, 0x5c80, 0x5c90, | |
7006 | 0x5fc0, 0x6000, 0x6400, 0x6428, | |
7007 | 0x6800, 0x6848, 0x684c, 0x6860, | |
7008 | 0x6888, 0x6910, 0x8000 | |
7009 | }; | |
244ac4f4 MC |
7010 | |
7011 | regs->version = 0; | |
7012 | ||
7013 | memset(p, 0, BNX2_REGDUMP_LEN); | |
7014 | ||
7015 | if (!netif_running(bp->dev)) | |
7016 | return; | |
7017 | ||
7018 | i = 0; | |
7019 | offset = reg_boundaries[0]; | |
7020 | p += offset; | |
7021 | while (offset < BNX2_REGDUMP_LEN) { | |
e503e066 | 7022 | *p++ = BNX2_RD(bp, offset); |
244ac4f4 MC |
7023 | offset += 4; |
7024 | if (offset == reg_boundaries[i + 1]) { | |
7025 | offset = reg_boundaries[i + 2]; | |
7026 | p = (u32 *) (orig_p + offset); | |
7027 | i += 2; | |
7028 | } | |
7029 | } | |
7030 | } | |
7031 | ||
b6016b76 MC |
7032 | static void |
7033 | bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
7034 | { | |
972ec0d4 | 7035 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7036 | |
f86e82fb | 7037 | if (bp->flags & BNX2_FLAG_NO_WOL) { |
b6016b76 MC |
7038 | wol->supported = 0; |
7039 | wol->wolopts = 0; | |
7040 | } | |
7041 | else { | |
7042 | wol->supported = WAKE_MAGIC; | |
7043 | if (bp->wol) | |
7044 | wol->wolopts = WAKE_MAGIC; | |
7045 | else | |
7046 | wol->wolopts = 0; | |
7047 | } | |
7048 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
7049 | } | |
7050 | ||
7051 | static int | |
7052 | bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
7053 | { | |
972ec0d4 | 7054 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7055 | |
7056 | if (wol->wolopts & ~WAKE_MAGIC) | |
7057 | return -EINVAL; | |
7058 | ||
7059 | if (wol->wolopts & WAKE_MAGIC) { | |
f86e82fb | 7060 | if (bp->flags & BNX2_FLAG_NO_WOL) |
b6016b76 MC |
7061 | return -EINVAL; |
7062 | ||
7063 | bp->wol = 1; | |
7064 | } | |
7065 | else { | |
7066 | bp->wol = 0; | |
7067 | } | |
6d5e85c7 MC |
7068 | |
7069 | device_set_wakeup_enable(&bp->pdev->dev, bp->wol); | |
7070 | ||
b6016b76 MC |
7071 | return 0; |
7072 | } | |
7073 | ||
7074 | static int | |
7075 | bnx2_nway_reset(struct net_device *dev) | |
7076 | { | |
972ec0d4 | 7077 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7078 | u32 bmcr; |
7079 | ||
9f52b564 MC |
7080 | if (!netif_running(dev)) |
7081 | return -EAGAIN; | |
7082 | ||
b6016b76 MC |
7083 | if (!(bp->autoneg & AUTONEG_SPEED)) { |
7084 | return -EINVAL; | |
7085 | } | |
7086 | ||
c770a65c | 7087 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 7088 | |
583c28e5 | 7089 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
7b6b8347 MC |
7090 | int rc; |
7091 | ||
7092 | rc = bnx2_setup_remote_phy(bp, bp->phy_port); | |
7093 | spin_unlock_bh(&bp->phy_lock); | |
7094 | return rc; | |
7095 | } | |
7096 | ||
b6016b76 | 7097 | /* Force a link down visible on the other side */ |
583c28e5 | 7098 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
ca58c3af | 7099 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
c770a65c | 7100 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
7101 | |
7102 | msleep(20); | |
7103 | ||
c770a65c | 7104 | spin_lock_bh(&bp->phy_lock); |
f8dd064e | 7105 | |
40105c0b | 7106 | bp->current_interval = BNX2_SERDES_AN_TIMEOUT; |
f8dd064e MC |
7107 | bp->serdes_an_pending = 1; |
7108 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
b6016b76 MC |
7109 | } |
7110 | ||
ca58c3af | 7111 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
b6016b76 | 7112 | bmcr &= ~BMCR_LOOPBACK; |
ca58c3af | 7113 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); |
b6016b76 | 7114 | |
c770a65c | 7115 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
7116 | |
7117 | return 0; | |
7118 | } | |
7119 | ||
7959ea25 ON |
7120 | static u32 |
7121 | bnx2_get_link(struct net_device *dev) | |
7122 | { | |
7123 | struct bnx2 *bp = netdev_priv(dev); | |
7124 | ||
7125 | return bp->link_up; | |
7126 | } | |
7127 | ||
b6016b76 MC |
7128 | static int |
7129 | bnx2_get_eeprom_len(struct net_device *dev) | |
7130 | { | |
972ec0d4 | 7131 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7132 | |
1122db71 | 7133 | if (bp->flash_info == NULL) |
b6016b76 MC |
7134 | return 0; |
7135 | ||
1122db71 | 7136 | return (int) bp->flash_size; |
b6016b76 MC |
7137 | } |
7138 | ||
7139 | static int | |
7140 | bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
7141 | u8 *eebuf) | |
7142 | { | |
972ec0d4 | 7143 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7144 | int rc; |
7145 | ||
9f52b564 MC |
7146 | if (!netif_running(dev)) |
7147 | return -EAGAIN; | |
7148 | ||
1064e944 | 7149 | /* parameters already validated in ethtool_get_eeprom */ |
b6016b76 MC |
7150 | |
7151 | rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); | |
7152 | ||
7153 | return rc; | |
7154 | } | |
7155 | ||
7156 | static int | |
7157 | bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
7158 | u8 *eebuf) | |
7159 | { | |
972ec0d4 | 7160 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7161 | int rc; |
7162 | ||
9f52b564 MC |
7163 | if (!netif_running(dev)) |
7164 | return -EAGAIN; | |
7165 | ||
1064e944 | 7166 | /* parameters already validated in ethtool_set_eeprom */ |
b6016b76 MC |
7167 | |
7168 | rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); | |
7169 | ||
7170 | return rc; | |
7171 | } | |
7172 | ||
7173 | static int | |
7174 | bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) | |
7175 | { | |
972ec0d4 | 7176 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7177 | |
7178 | memset(coal, 0, sizeof(struct ethtool_coalesce)); | |
7179 | ||
7180 | coal->rx_coalesce_usecs = bp->rx_ticks; | |
7181 | coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip; | |
7182 | coal->rx_coalesce_usecs_irq = bp->rx_ticks_int; | |
7183 | coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int; | |
7184 | ||
7185 | coal->tx_coalesce_usecs = bp->tx_ticks; | |
7186 | coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip; | |
7187 | coal->tx_coalesce_usecs_irq = bp->tx_ticks_int; | |
7188 | coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int; | |
7189 | ||
7190 | coal->stats_block_coalesce_usecs = bp->stats_ticks; | |
7191 | ||
7192 | return 0; | |
7193 | } | |
7194 | ||
7195 | static int | |
7196 | bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) | |
7197 | { | |
972ec0d4 | 7198 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7199 | |
7200 | bp->rx_ticks = (u16) coal->rx_coalesce_usecs; | |
7201 | if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; | |
7202 | ||
6aa20a22 | 7203 | bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; |
b6016b76 MC |
7204 | if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; |
7205 | ||
7206 | bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; | |
7207 | if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; | |
7208 | ||
7209 | bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq; | |
7210 | if (bp->rx_quick_cons_trip_int > 0xff) | |
7211 | bp->rx_quick_cons_trip_int = 0xff; | |
7212 | ||
7213 | bp->tx_ticks = (u16) coal->tx_coalesce_usecs; | |
7214 | if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; | |
7215 | ||
7216 | bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames; | |
7217 | if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; | |
7218 | ||
7219 | bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq; | |
7220 | if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; | |
7221 | ||
7222 | bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq; | |
7223 | if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = | |
7224 | 0xff; | |
7225 | ||
7226 | bp->stats_ticks = coal->stats_block_coalesce_usecs; | |
61d9e3fa | 7227 | if (bp->flags & BNX2_FLAG_BROKEN_STATS) { |
02537b06 MC |
7228 | if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC) |
7229 | bp->stats_ticks = USEC_PER_SEC; | |
7230 | } | |
7ea6920e MC |
7231 | if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS) |
7232 | bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS; | |
7233 | bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS; | |
b6016b76 MC |
7234 | |
7235 | if (netif_running(bp->dev)) { | |
212f9934 | 7236 | bnx2_netif_stop(bp, true); |
9a120bc5 | 7237 | bnx2_init_nic(bp, 0); |
212f9934 | 7238 | bnx2_netif_start(bp, true); |
b6016b76 MC |
7239 | } |
7240 | ||
7241 | return 0; | |
7242 | } | |
7243 | ||
7244 | static void | |
7245 | bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
7246 | { | |
972ec0d4 | 7247 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7248 | |
2bc4078e MC |
7249 | ering->rx_max_pending = BNX2_MAX_TOTAL_RX_DESC_CNT; |
7250 | ering->rx_jumbo_max_pending = BNX2_MAX_TOTAL_RX_PG_DESC_CNT; | |
b6016b76 MC |
7251 | |
7252 | ering->rx_pending = bp->rx_ring_size; | |
47bf4246 | 7253 | ering->rx_jumbo_pending = bp->rx_pg_ring_size; |
b6016b76 | 7254 | |
2bc4078e | 7255 | ering->tx_max_pending = BNX2_MAX_TX_DESC_CNT; |
b6016b76 MC |
7256 | ering->tx_pending = bp->tx_ring_size; |
7257 | } | |
7258 | ||
7259 | static int | |
b033281f | 7260 | bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq) |
b6016b76 | 7261 | { |
13daffa2 | 7262 | if (netif_running(bp->dev)) { |
354fcd77 MC |
7263 | /* Reset will erase chipset stats; save them */ |
7264 | bnx2_save_stats(bp); | |
7265 | ||
212f9934 | 7266 | bnx2_netif_stop(bp, true); |
13daffa2 | 7267 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); |
b033281f MC |
7268 | if (reset_irq) { |
7269 | bnx2_free_irq(bp); | |
7270 | bnx2_del_napi(bp); | |
7271 | } else { | |
7272 | __bnx2_free_irq(bp); | |
7273 | } | |
13daffa2 MC |
7274 | bnx2_free_skbs(bp); |
7275 | bnx2_free_mem(bp); | |
7276 | } | |
7277 | ||
5d5d0015 MC |
7278 | bnx2_set_rx_ring_size(bp, rx); |
7279 | bp->tx_ring_size = tx; | |
b6016b76 MC |
7280 | |
7281 | if (netif_running(bp->dev)) { | |
b033281f MC |
7282 | int rc = 0; |
7283 | ||
7284 | if (reset_irq) { | |
7285 | rc = bnx2_setup_int_mode(bp, disable_msi); | |
7286 | bnx2_init_napi(bp); | |
7287 | } | |
7288 | ||
7289 | if (!rc) | |
7290 | rc = bnx2_alloc_mem(bp); | |
13daffa2 | 7291 | |
a29ba9d2 MC |
7292 | if (!rc) |
7293 | rc = bnx2_request_irq(bp); | |
7294 | ||
6fefb65e MC |
7295 | if (!rc) |
7296 | rc = bnx2_init_nic(bp, 0); | |
7297 | ||
7298 | if (rc) { | |
7299 | bnx2_napi_enable(bp); | |
7300 | dev_close(bp->dev); | |
13daffa2 | 7301 | return rc; |
6fefb65e | 7302 | } |
e9f26c49 MC |
7303 | #ifdef BCM_CNIC |
7304 | mutex_lock(&bp->cnic_lock); | |
7305 | /* Let cnic know about the new status block. */ | |
7306 | if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD) | |
7307 | bnx2_setup_cnic_irq_info(bp); | |
7308 | mutex_unlock(&bp->cnic_lock); | |
7309 | #endif | |
212f9934 | 7310 | bnx2_netif_start(bp, true); |
b6016b76 | 7311 | } |
b6016b76 MC |
7312 | return 0; |
7313 | } | |
7314 | ||
5d5d0015 MC |
7315 | static int |
7316 | bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
7317 | { | |
7318 | struct bnx2 *bp = netdev_priv(dev); | |
7319 | int rc; | |
7320 | ||
2bc4078e MC |
7321 | if ((ering->rx_pending > BNX2_MAX_TOTAL_RX_DESC_CNT) || |
7322 | (ering->tx_pending > BNX2_MAX_TX_DESC_CNT) || | |
5d5d0015 MC |
7323 | (ering->tx_pending <= MAX_SKB_FRAGS)) { |
7324 | ||
7325 | return -EINVAL; | |
7326 | } | |
b033281f MC |
7327 | rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending, |
7328 | false); | |
5d5d0015 MC |
7329 | return rc; |
7330 | } | |
7331 | ||
b6016b76 MC |
7332 | static void |
7333 | bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
7334 | { | |
972ec0d4 | 7335 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7336 | |
7337 | epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); | |
7338 | epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); | |
7339 | epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); | |
7340 | } | |
7341 | ||
7342 | static int | |
7343 | bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | |
7344 | { | |
972ec0d4 | 7345 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7346 | |
7347 | bp->req_flow_ctrl = 0; | |
7348 | if (epause->rx_pause) | |
7349 | bp->req_flow_ctrl |= FLOW_CTRL_RX; | |
7350 | if (epause->tx_pause) | |
7351 | bp->req_flow_ctrl |= FLOW_CTRL_TX; | |
7352 | ||
7353 | if (epause->autoneg) { | |
7354 | bp->autoneg |= AUTONEG_FLOW_CTRL; | |
7355 | } | |
7356 | else { | |
7357 | bp->autoneg &= ~AUTONEG_FLOW_CTRL; | |
7358 | } | |
7359 | ||
9f52b564 MC |
7360 | if (netif_running(dev)) { |
7361 | spin_lock_bh(&bp->phy_lock); | |
7362 | bnx2_setup_phy(bp, bp->phy_port); | |
7363 | spin_unlock_bh(&bp->phy_lock); | |
7364 | } | |
b6016b76 MC |
7365 | |
7366 | return 0; | |
7367 | } | |
7368 | ||
14ab9b86 | 7369 | static struct { |
b6016b76 | 7370 | char string[ETH_GSTRING_LEN]; |
790dab2f | 7371 | } bnx2_stats_str_arr[] = { |
b6016b76 MC |
7372 | { "rx_bytes" }, |
7373 | { "rx_error_bytes" }, | |
7374 | { "tx_bytes" }, | |
7375 | { "tx_error_bytes" }, | |
7376 | { "rx_ucast_packets" }, | |
7377 | { "rx_mcast_packets" }, | |
7378 | { "rx_bcast_packets" }, | |
7379 | { "tx_ucast_packets" }, | |
7380 | { "tx_mcast_packets" }, | |
7381 | { "tx_bcast_packets" }, | |
7382 | { "tx_mac_errors" }, | |
7383 | { "tx_carrier_errors" }, | |
7384 | { "rx_crc_errors" }, | |
7385 | { "rx_align_errors" }, | |
7386 | { "tx_single_collisions" }, | |
7387 | { "tx_multi_collisions" }, | |
7388 | { "tx_deferred" }, | |
7389 | { "tx_excess_collisions" }, | |
7390 | { "tx_late_collisions" }, | |
7391 | { "tx_total_collisions" }, | |
7392 | { "rx_fragments" }, | |
7393 | { "rx_jabbers" }, | |
7394 | { "rx_undersize_packets" }, | |
7395 | { "rx_oversize_packets" }, | |
7396 | { "rx_64_byte_packets" }, | |
7397 | { "rx_65_to_127_byte_packets" }, | |
7398 | { "rx_128_to_255_byte_packets" }, | |
7399 | { "rx_256_to_511_byte_packets" }, | |
7400 | { "rx_512_to_1023_byte_packets" }, | |
7401 | { "rx_1024_to_1522_byte_packets" }, | |
7402 | { "rx_1523_to_9022_byte_packets" }, | |
7403 | { "tx_64_byte_packets" }, | |
7404 | { "tx_65_to_127_byte_packets" }, | |
7405 | { "tx_128_to_255_byte_packets" }, | |
7406 | { "tx_256_to_511_byte_packets" }, | |
7407 | { "tx_512_to_1023_byte_packets" }, | |
7408 | { "tx_1024_to_1522_byte_packets" }, | |
7409 | { "tx_1523_to_9022_byte_packets" }, | |
7410 | { "rx_xon_frames" }, | |
7411 | { "rx_xoff_frames" }, | |
7412 | { "tx_xon_frames" }, | |
7413 | { "tx_xoff_frames" }, | |
7414 | { "rx_mac_ctrl_frames" }, | |
7415 | { "rx_filtered_packets" }, | |
790dab2f | 7416 | { "rx_ftq_discards" }, |
b6016b76 | 7417 | { "rx_discards" }, |
cea94db9 | 7418 | { "rx_fw_discards" }, |
b6016b76 MC |
7419 | }; |
7420 | ||
0db83cd8 | 7421 | #define BNX2_NUM_STATS ARRAY_SIZE(bnx2_stats_str_arr) |
790dab2f | 7422 | |
b6016b76 MC |
7423 | #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4) |
7424 | ||
f71e1309 | 7425 | static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = { |
b6016b76 MC |
7426 | STATS_OFFSET32(stat_IfHCInOctets_hi), |
7427 | STATS_OFFSET32(stat_IfHCInBadOctets_hi), | |
7428 | STATS_OFFSET32(stat_IfHCOutOctets_hi), | |
7429 | STATS_OFFSET32(stat_IfHCOutBadOctets_hi), | |
7430 | STATS_OFFSET32(stat_IfHCInUcastPkts_hi), | |
7431 | STATS_OFFSET32(stat_IfHCInMulticastPkts_hi), | |
7432 | STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi), | |
7433 | STATS_OFFSET32(stat_IfHCOutUcastPkts_hi), | |
7434 | STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi), | |
7435 | STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi), | |
7436 | STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors), | |
6aa20a22 JG |
7437 | STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), |
7438 | STATS_OFFSET32(stat_Dot3StatsFCSErrors), | |
7439 | STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), | |
7440 | STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), | |
7441 | STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), | |
7442 | STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), | |
7443 | STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), | |
7444 | STATS_OFFSET32(stat_Dot3StatsLateCollisions), | |
7445 | STATS_OFFSET32(stat_EtherStatsCollisions), | |
7446 | STATS_OFFSET32(stat_EtherStatsFragments), | |
7447 | STATS_OFFSET32(stat_EtherStatsJabbers), | |
7448 | STATS_OFFSET32(stat_EtherStatsUndersizePkts), | |
7449 | STATS_OFFSET32(stat_EtherStatsOverrsizePkts), | |
7450 | STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), | |
7451 | STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), | |
7452 | STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), | |
7453 | STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), | |
7454 | STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), | |
7455 | STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), | |
7456 | STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), | |
7457 | STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), | |
7458 | STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), | |
7459 | STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), | |
7460 | STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), | |
7461 | STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), | |
7462 | STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), | |
7463 | STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), | |
7464 | STATS_OFFSET32(stat_XonPauseFramesReceived), | |
7465 | STATS_OFFSET32(stat_XoffPauseFramesReceived), | |
7466 | STATS_OFFSET32(stat_OutXonSent), | |
7467 | STATS_OFFSET32(stat_OutXoffSent), | |
7468 | STATS_OFFSET32(stat_MacControlFramesReceived), | |
7469 | STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), | |
790dab2f | 7470 | STATS_OFFSET32(stat_IfInFTQDiscards), |
6aa20a22 | 7471 | STATS_OFFSET32(stat_IfInMBUFDiscards), |
cea94db9 | 7472 | STATS_OFFSET32(stat_FwRxDrop), |
b6016b76 MC |
7473 | }; |
7474 | ||
7475 | /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are | |
7476 | * skipped because of errata. | |
6aa20a22 | 7477 | */ |
14ab9b86 | 7478 | static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = { |
b6016b76 MC |
7479 | 8,0,8,8,8,8,8,8,8,8, |
7480 | 4,0,4,4,4,4,4,4,4,4, | |
7481 | 4,4,4,4,4,4,4,4,4,4, | |
7482 | 4,4,4,4,4,4,4,4,4,4, | |
790dab2f | 7483 | 4,4,4,4,4,4,4, |
b6016b76 MC |
7484 | }; |
7485 | ||
5b0c76ad MC |
7486 | static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = { |
7487 | 8,0,8,8,8,8,8,8,8,8, | |
7488 | 4,4,4,4,4,4,4,4,4,4, | |
7489 | 4,4,4,4,4,4,4,4,4,4, | |
7490 | 4,4,4,4,4,4,4,4,4,4, | |
790dab2f | 7491 | 4,4,4,4,4,4,4, |
5b0c76ad MC |
7492 | }; |
7493 | ||
b6016b76 MC |
7494 | #define BNX2_NUM_TESTS 6 |
7495 | ||
14ab9b86 | 7496 | static struct { |
b6016b76 MC |
7497 | char string[ETH_GSTRING_LEN]; |
7498 | } bnx2_tests_str_arr[BNX2_NUM_TESTS] = { | |
7499 | { "register_test (offline)" }, | |
7500 | { "memory_test (offline)" }, | |
7501 | { "loopback_test (offline)" }, | |
7502 | { "nvram_test (online)" }, | |
7503 | { "interrupt_test (online)" }, | |
7504 | { "link_test (online)" }, | |
7505 | }; | |
7506 | ||
7507 | static int | |
b9f2c044 | 7508 | bnx2_get_sset_count(struct net_device *dev, int sset) |
b6016b76 | 7509 | { |
b9f2c044 JG |
7510 | switch (sset) { |
7511 | case ETH_SS_TEST: | |
7512 | return BNX2_NUM_TESTS; | |
7513 | case ETH_SS_STATS: | |
7514 | return BNX2_NUM_STATS; | |
7515 | default: | |
7516 | return -EOPNOTSUPP; | |
7517 | } | |
b6016b76 MC |
7518 | } |
7519 | ||
7520 | static void | |
7521 | bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) | |
7522 | { | |
972ec0d4 | 7523 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7524 | |
9f52b564 MC |
7525 | bnx2_set_power_state(bp, PCI_D0); |
7526 | ||
b6016b76 MC |
7527 | memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); |
7528 | if (etest->flags & ETH_TEST_FL_OFFLINE) { | |
80be4434 MC |
7529 | int i; |
7530 | ||
212f9934 | 7531 | bnx2_netif_stop(bp, true); |
b6016b76 MC |
7532 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG); |
7533 | bnx2_free_skbs(bp); | |
7534 | ||
7535 | if (bnx2_test_registers(bp) != 0) { | |
7536 | buf[0] = 1; | |
7537 | etest->flags |= ETH_TEST_FL_FAILED; | |
7538 | } | |
7539 | if (bnx2_test_memory(bp) != 0) { | |
7540 | buf[1] = 1; | |
7541 | etest->flags |= ETH_TEST_FL_FAILED; | |
7542 | } | |
bc5a0690 | 7543 | if ((buf[2] = bnx2_test_loopback(bp)) != 0) |
b6016b76 | 7544 | etest->flags |= ETH_TEST_FL_FAILED; |
b6016b76 | 7545 | |
9f52b564 MC |
7546 | if (!netif_running(bp->dev)) |
7547 | bnx2_shutdown_chip(bp); | |
b6016b76 | 7548 | else { |
9a120bc5 | 7549 | bnx2_init_nic(bp, 1); |
212f9934 | 7550 | bnx2_netif_start(bp, true); |
b6016b76 MC |
7551 | } |
7552 | ||
7553 | /* wait for link up */ | |
80be4434 MC |
7554 | for (i = 0; i < 7; i++) { |
7555 | if (bp->link_up) | |
7556 | break; | |
7557 | msleep_interruptible(1000); | |
7558 | } | |
b6016b76 MC |
7559 | } |
7560 | ||
7561 | if (bnx2_test_nvram(bp) != 0) { | |
7562 | buf[3] = 1; | |
7563 | etest->flags |= ETH_TEST_FL_FAILED; | |
7564 | } | |
7565 | if (bnx2_test_intr(bp) != 0) { | |
7566 | buf[4] = 1; | |
7567 | etest->flags |= ETH_TEST_FL_FAILED; | |
7568 | } | |
7569 | ||
7570 | if (bnx2_test_link(bp) != 0) { | |
7571 | buf[5] = 1; | |
7572 | etest->flags |= ETH_TEST_FL_FAILED; | |
7573 | ||
7574 | } | |
9f52b564 MC |
7575 | if (!netif_running(bp->dev)) |
7576 | bnx2_set_power_state(bp, PCI_D3hot); | |
b6016b76 MC |
7577 | } |
7578 | ||
7579 | static void | |
7580 | bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf) | |
7581 | { | |
7582 | switch (stringset) { | |
7583 | case ETH_SS_STATS: | |
7584 | memcpy(buf, bnx2_stats_str_arr, | |
7585 | sizeof(bnx2_stats_str_arr)); | |
7586 | break; | |
7587 | case ETH_SS_TEST: | |
7588 | memcpy(buf, bnx2_tests_str_arr, | |
7589 | sizeof(bnx2_tests_str_arr)); | |
7590 | break; | |
7591 | } | |
7592 | } | |
7593 | ||
b6016b76 MC |
7594 | static void |
7595 | bnx2_get_ethtool_stats(struct net_device *dev, | |
7596 | struct ethtool_stats *stats, u64 *buf) | |
7597 | { | |
972ec0d4 | 7598 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7599 | int i; |
7600 | u32 *hw_stats = (u32 *) bp->stats_blk; | |
354fcd77 | 7601 | u32 *temp_stats = (u32 *) bp->temp_stats_blk; |
14ab9b86 | 7602 | u8 *stats_len_arr = NULL; |
b6016b76 MC |
7603 | |
7604 | if (hw_stats == NULL) { | |
7605 | memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS); | |
7606 | return; | |
7607 | } | |
7608 | ||
4ce45e02 MC |
7609 | if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || |
7610 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) || | |
7611 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) || | |
7612 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0)) | |
b6016b76 | 7613 | stats_len_arr = bnx2_5706_stats_len_arr; |
5b0c76ad MC |
7614 | else |
7615 | stats_len_arr = bnx2_5708_stats_len_arr; | |
b6016b76 MC |
7616 | |
7617 | for (i = 0; i < BNX2_NUM_STATS; i++) { | |
354fcd77 MC |
7618 | unsigned long offset; |
7619 | ||
b6016b76 MC |
7620 | if (stats_len_arr[i] == 0) { |
7621 | /* skip this counter */ | |
7622 | buf[i] = 0; | |
7623 | continue; | |
7624 | } | |
354fcd77 MC |
7625 | |
7626 | offset = bnx2_stats_offset_arr[i]; | |
b6016b76 MC |
7627 | if (stats_len_arr[i] == 4) { |
7628 | /* 4-byte counter */ | |
354fcd77 MC |
7629 | buf[i] = (u64) *(hw_stats + offset) + |
7630 | *(temp_stats + offset); | |
b6016b76 MC |
7631 | continue; |
7632 | } | |
7633 | /* 8-byte counter */ | |
354fcd77 MC |
7634 | buf[i] = (((u64) *(hw_stats + offset)) << 32) + |
7635 | *(hw_stats + offset + 1) + | |
7636 | (((u64) *(temp_stats + offset)) << 32) + | |
7637 | *(temp_stats + offset + 1); | |
b6016b76 MC |
7638 | } |
7639 | } | |
7640 | ||
7641 | static int | |
2e17e1aa | 7642 | bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state) |
b6016b76 | 7643 | { |
972ec0d4 | 7644 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7645 | |
2e17e1aa | 7646 | switch (state) { |
7647 | case ETHTOOL_ID_ACTIVE: | |
7648 | bnx2_set_power_state(bp, PCI_D0); | |
9f52b564 | 7649 | |
e503e066 MC |
7650 | bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG); |
7651 | BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC); | |
fce55922 | 7652 | return 1; /* cycle on/off once per second */ |
b6016b76 | 7653 | |
2e17e1aa | 7654 | case ETHTOOL_ID_ON: |
e503e066 MC |
7655 | BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE | |
7656 | BNX2_EMAC_LED_1000MB_OVERRIDE | | |
7657 | BNX2_EMAC_LED_100MB_OVERRIDE | | |
7658 | BNX2_EMAC_LED_10MB_OVERRIDE | | |
7659 | BNX2_EMAC_LED_TRAFFIC_OVERRIDE | | |
7660 | BNX2_EMAC_LED_TRAFFIC); | |
2e17e1aa | 7661 | break; |
b6016b76 | 7662 | |
2e17e1aa | 7663 | case ETHTOOL_ID_OFF: |
e503e066 | 7664 | BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE); |
2e17e1aa | 7665 | break; |
9f52b564 | 7666 | |
2e17e1aa | 7667 | case ETHTOOL_ID_INACTIVE: |
e503e066 MC |
7668 | BNX2_WR(bp, BNX2_EMAC_LED, 0); |
7669 | BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save); | |
2e17e1aa | 7670 | |
7671 | if (!netif_running(dev)) | |
7672 | bnx2_set_power_state(bp, PCI_D3hot); | |
7673 | break; | |
7674 | } | |
9f52b564 | 7675 | |
b6016b76 MC |
7676 | return 0; |
7677 | } | |
7678 | ||
c8f44aff MM |
7679 | static netdev_features_t |
7680 | bnx2_fix_features(struct net_device *dev, netdev_features_t features) | |
4666f87a MC |
7681 | { |
7682 | struct bnx2 *bp = netdev_priv(dev); | |
7683 | ||
8d7dfc2b | 7684 | if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) |
f646968f | 7685 | features |= NETIF_F_HW_VLAN_CTAG_RX; |
8d7dfc2b MM |
7686 | |
7687 | return features; | |
4666f87a MC |
7688 | } |
7689 | ||
fdc8541d | 7690 | static int |
c8f44aff | 7691 | bnx2_set_features(struct net_device *dev, netdev_features_t features) |
fdc8541d | 7692 | { |
7d0fd211 | 7693 | struct bnx2 *bp = netdev_priv(dev); |
7d0fd211 | 7694 | |
7c810477 | 7695 | /* TSO with VLAN tag won't work with current firmware */ |
f646968f | 7696 | if (features & NETIF_F_HW_VLAN_CTAG_TX) |
8d7dfc2b MM |
7697 | dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO); |
7698 | else | |
7699 | dev->vlan_features &= ~NETIF_F_ALL_TSO; | |
7d0fd211 | 7700 | |
f646968f | 7701 | if ((!!(features & NETIF_F_HW_VLAN_CTAG_RX) != |
7d0fd211 JG |
7702 | !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) && |
7703 | netif_running(dev)) { | |
7704 | bnx2_netif_stop(bp, false); | |
8d7dfc2b | 7705 | dev->features = features; |
7d0fd211 JG |
7706 | bnx2_set_rx_mode(dev); |
7707 | bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1); | |
7708 | bnx2_netif_start(bp, false); | |
8d7dfc2b | 7709 | return 1; |
7d0fd211 JG |
7710 | } |
7711 | ||
7712 | return 0; | |
fdc8541d MC |
7713 | } |
7714 | ||
b033281f MC |
7715 | static void bnx2_get_channels(struct net_device *dev, |
7716 | struct ethtool_channels *channels) | |
7717 | { | |
7718 | struct bnx2 *bp = netdev_priv(dev); | |
7719 | u32 max_rx_rings = 1; | |
7720 | u32 max_tx_rings = 1; | |
7721 | ||
7722 | if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) { | |
7723 | max_rx_rings = RX_MAX_RINGS; | |
7724 | max_tx_rings = TX_MAX_RINGS; | |
7725 | } | |
7726 | ||
7727 | channels->max_rx = max_rx_rings; | |
7728 | channels->max_tx = max_tx_rings; | |
7729 | channels->max_other = 0; | |
7730 | channels->max_combined = 0; | |
7731 | channels->rx_count = bp->num_rx_rings; | |
7732 | channels->tx_count = bp->num_tx_rings; | |
7733 | channels->other_count = 0; | |
7734 | channels->combined_count = 0; | |
7735 | } | |
7736 | ||
7737 | static int bnx2_set_channels(struct net_device *dev, | |
7738 | struct ethtool_channels *channels) | |
7739 | { | |
7740 | struct bnx2 *bp = netdev_priv(dev); | |
7741 | u32 max_rx_rings = 1; | |
7742 | u32 max_tx_rings = 1; | |
7743 | int rc = 0; | |
7744 | ||
7745 | if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) { | |
7746 | max_rx_rings = RX_MAX_RINGS; | |
7747 | max_tx_rings = TX_MAX_RINGS; | |
7748 | } | |
7749 | if (channels->rx_count > max_rx_rings || | |
7750 | channels->tx_count > max_tx_rings) | |
7751 | return -EINVAL; | |
7752 | ||
7753 | bp->num_req_rx_rings = channels->rx_count; | |
7754 | bp->num_req_tx_rings = channels->tx_count; | |
7755 | ||
7756 | if (netif_running(dev)) | |
7757 | rc = bnx2_change_ring_size(bp, bp->rx_ring_size, | |
7758 | bp->tx_ring_size, true); | |
7759 | ||
7760 | return rc; | |
7761 | } | |
7762 | ||
7282d491 | 7763 | static const struct ethtool_ops bnx2_ethtool_ops = { |
b6016b76 MC |
7764 | .get_settings = bnx2_get_settings, |
7765 | .set_settings = bnx2_set_settings, | |
7766 | .get_drvinfo = bnx2_get_drvinfo, | |
244ac4f4 MC |
7767 | .get_regs_len = bnx2_get_regs_len, |
7768 | .get_regs = bnx2_get_regs, | |
b6016b76 MC |
7769 | .get_wol = bnx2_get_wol, |
7770 | .set_wol = bnx2_set_wol, | |
7771 | .nway_reset = bnx2_nway_reset, | |
7959ea25 | 7772 | .get_link = bnx2_get_link, |
b6016b76 MC |
7773 | .get_eeprom_len = bnx2_get_eeprom_len, |
7774 | .get_eeprom = bnx2_get_eeprom, | |
7775 | .set_eeprom = bnx2_set_eeprom, | |
7776 | .get_coalesce = bnx2_get_coalesce, | |
7777 | .set_coalesce = bnx2_set_coalesce, | |
7778 | .get_ringparam = bnx2_get_ringparam, | |
7779 | .set_ringparam = bnx2_set_ringparam, | |
7780 | .get_pauseparam = bnx2_get_pauseparam, | |
7781 | .set_pauseparam = bnx2_set_pauseparam, | |
b6016b76 MC |
7782 | .self_test = bnx2_self_test, |
7783 | .get_strings = bnx2_get_strings, | |
2e17e1aa | 7784 | .set_phys_id = bnx2_set_phys_id, |
b6016b76 | 7785 | .get_ethtool_stats = bnx2_get_ethtool_stats, |
b9f2c044 | 7786 | .get_sset_count = bnx2_get_sset_count, |
b033281f MC |
7787 | .get_channels = bnx2_get_channels, |
7788 | .set_channels = bnx2_set_channels, | |
b6016b76 MC |
7789 | }; |
7790 | ||
7791 | /* Called with rtnl_lock */ | |
7792 | static int | |
7793 | bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
7794 | { | |
14ab9b86 | 7795 | struct mii_ioctl_data *data = if_mii(ifr); |
972ec0d4 | 7796 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7797 | int err; |
7798 | ||
7799 | switch(cmd) { | |
7800 | case SIOCGMIIPHY: | |
7801 | data->phy_id = bp->phy_addr; | |
7802 | ||
7803 | /* fallthru */ | |
7804 | case SIOCGMIIREG: { | |
7805 | u32 mii_regval; | |
7806 | ||
583c28e5 | 7807 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
7b6b8347 MC |
7808 | return -EOPNOTSUPP; |
7809 | ||
dad3e452 MC |
7810 | if (!netif_running(dev)) |
7811 | return -EAGAIN; | |
7812 | ||
c770a65c | 7813 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 7814 | err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); |
c770a65c | 7815 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
7816 | |
7817 | data->val_out = mii_regval; | |
7818 | ||
7819 | return err; | |
7820 | } | |
7821 | ||
7822 | case SIOCSMIIREG: | |
583c28e5 | 7823 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
7b6b8347 MC |
7824 | return -EOPNOTSUPP; |
7825 | ||
dad3e452 MC |
7826 | if (!netif_running(dev)) |
7827 | return -EAGAIN; | |
7828 | ||
c770a65c | 7829 | spin_lock_bh(&bp->phy_lock); |
b6016b76 | 7830 | err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); |
c770a65c | 7831 | spin_unlock_bh(&bp->phy_lock); |
b6016b76 MC |
7832 | |
7833 | return err; | |
7834 | ||
7835 | default: | |
7836 | /* do nothing */ | |
7837 | break; | |
7838 | } | |
7839 | return -EOPNOTSUPP; | |
7840 | } | |
7841 | ||
7842 | /* Called with rtnl_lock */ | |
7843 | static int | |
7844 | bnx2_change_mac_addr(struct net_device *dev, void *p) | |
7845 | { | |
7846 | struct sockaddr *addr = p; | |
972ec0d4 | 7847 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 7848 | |
73eef4cd | 7849 | if (!is_valid_ether_addr(addr->sa_data)) |
504f9b5a | 7850 | return -EADDRNOTAVAIL; |
73eef4cd | 7851 | |
b6016b76 MC |
7852 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7853 | if (netif_running(dev)) | |
5fcaed01 | 7854 | bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); |
b6016b76 MC |
7855 | |
7856 | return 0; | |
7857 | } | |
7858 | ||
7859 | /* Called with rtnl_lock */ | |
7860 | static int | |
7861 | bnx2_change_mtu(struct net_device *dev, int new_mtu) | |
7862 | { | |
972ec0d4 | 7863 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
7864 | |
7865 | if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) || | |
7866 | ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE)) | |
7867 | return -EINVAL; | |
7868 | ||
7869 | dev->mtu = new_mtu; | |
b033281f MC |
7870 | return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size, |
7871 | false); | |
b6016b76 MC |
7872 | } |
7873 | ||
257ddbda | 7874 | #ifdef CONFIG_NET_POLL_CONTROLLER |
b6016b76 MC |
7875 | static void |
7876 | poll_bnx2(struct net_device *dev) | |
7877 | { | |
972ec0d4 | 7878 | struct bnx2 *bp = netdev_priv(dev); |
b2af2c1d | 7879 | int i; |
b6016b76 | 7880 | |
b2af2c1d | 7881 | for (i = 0; i < bp->irq_nvecs; i++) { |
1bf1e347 MC |
7882 | struct bnx2_irq *irq = &bp->irq_tbl[i]; |
7883 | ||
7884 | disable_irq(irq->vector); | |
7885 | irq->handler(irq->vector, &bp->bnx2_napi[i]); | |
7886 | enable_irq(irq->vector); | |
b2af2c1d | 7887 | } |
b6016b76 MC |
7888 | } |
7889 | #endif | |
7890 | ||
cfd95a63 | 7891 | static void |
253c8b75 MC |
7892 | bnx2_get_5709_media(struct bnx2 *bp) |
7893 | { | |
e503e066 | 7894 | u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); |
253c8b75 MC |
7895 | u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID; |
7896 | u32 strap; | |
7897 | ||
7898 | if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) | |
7899 | return; | |
7900 | else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { | |
583c28e5 | 7901 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
253c8b75 MC |
7902 | return; |
7903 | } | |
7904 | ||
7905 | if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) | |
7906 | strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; | |
7907 | else | |
7908 | strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; | |
7909 | ||
aefd90e4 | 7910 | if (bp->func == 0) { |
253c8b75 MC |
7911 | switch (strap) { |
7912 | case 0x4: | |
7913 | case 0x5: | |
7914 | case 0x6: | |
583c28e5 | 7915 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
253c8b75 MC |
7916 | return; |
7917 | } | |
7918 | } else { | |
7919 | switch (strap) { | |
7920 | case 0x1: | |
7921 | case 0x2: | |
7922 | case 0x4: | |
583c28e5 | 7923 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
253c8b75 MC |
7924 | return; |
7925 | } | |
7926 | } | |
7927 | } | |
7928 | ||
cfd95a63 | 7929 | static void |
883e5151 MC |
7930 | bnx2_get_pci_speed(struct bnx2 *bp) |
7931 | { | |
7932 | u32 reg; | |
7933 | ||
e503e066 | 7934 | reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS); |
883e5151 MC |
7935 | if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { |
7936 | u32 clkreg; | |
7937 | ||
f86e82fb | 7938 | bp->flags |= BNX2_FLAG_PCIX; |
883e5151 | 7939 | |
e503e066 | 7940 | clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); |
883e5151 MC |
7941 | |
7942 | clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; | |
7943 | switch (clkreg) { | |
7944 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: | |
7945 | bp->bus_speed_mhz = 133; | |
7946 | break; | |
7947 | ||
7948 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: | |
7949 | bp->bus_speed_mhz = 100; | |
7950 | break; | |
7951 | ||
7952 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: | |
7953 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: | |
7954 | bp->bus_speed_mhz = 66; | |
7955 | break; | |
7956 | ||
7957 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: | |
7958 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: | |
7959 | bp->bus_speed_mhz = 50; | |
7960 | break; | |
7961 | ||
7962 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: | |
7963 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: | |
7964 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: | |
7965 | bp->bus_speed_mhz = 33; | |
7966 | break; | |
7967 | } | |
7968 | } | |
7969 | else { | |
7970 | if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) | |
7971 | bp->bus_speed_mhz = 66; | |
7972 | else | |
7973 | bp->bus_speed_mhz = 33; | |
7974 | } | |
7975 | ||
7976 | if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) | |
f86e82fb | 7977 | bp->flags |= BNX2_FLAG_PCI_32BIT; |
883e5151 MC |
7978 | |
7979 | } | |
7980 | ||
cfd95a63 | 7981 | static void |
76d99061 MC |
7982 | bnx2_read_vpd_fw_ver(struct bnx2 *bp) |
7983 | { | |
df25bc38 | 7984 | int rc, i, j; |
76d99061 | 7985 | u8 *data; |
df25bc38 | 7986 | unsigned int block_end, rosize, len; |
76d99061 | 7987 | |
012093f6 MC |
7988 | #define BNX2_VPD_NVRAM_OFFSET 0x300 |
7989 | #define BNX2_VPD_LEN 128 | |
76d99061 MC |
7990 | #define BNX2_MAX_VER_SLEN 30 |
7991 | ||
7992 | data = kmalloc(256, GFP_KERNEL); | |
7993 | if (!data) | |
7994 | return; | |
7995 | ||
012093f6 MC |
7996 | rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN, |
7997 | BNX2_VPD_LEN); | |
76d99061 MC |
7998 | if (rc) |
7999 | goto vpd_done; | |
8000 | ||
012093f6 MC |
8001 | for (i = 0; i < BNX2_VPD_LEN; i += 4) { |
8002 | data[i] = data[i + BNX2_VPD_LEN + 3]; | |
8003 | data[i + 1] = data[i + BNX2_VPD_LEN + 2]; | |
8004 | data[i + 2] = data[i + BNX2_VPD_LEN + 1]; | |
8005 | data[i + 3] = data[i + BNX2_VPD_LEN]; | |
76d99061 MC |
8006 | } |
8007 | ||
df25bc38 MC |
8008 | i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA); |
8009 | if (i < 0) | |
8010 | goto vpd_done; | |
76d99061 | 8011 | |
df25bc38 MC |
8012 | rosize = pci_vpd_lrdt_size(&data[i]); |
8013 | i += PCI_VPD_LRDT_TAG_SIZE; | |
8014 | block_end = i + rosize; | |
76d99061 | 8015 | |
df25bc38 MC |
8016 | if (block_end > BNX2_VPD_LEN) |
8017 | goto vpd_done; | |
76d99061 | 8018 | |
df25bc38 MC |
8019 | j = pci_vpd_find_info_keyword(data, i, rosize, |
8020 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
8021 | if (j < 0) | |
8022 | goto vpd_done; | |
76d99061 | 8023 | |
df25bc38 | 8024 | len = pci_vpd_info_field_size(&data[j]); |
76d99061 | 8025 | |
df25bc38 MC |
8026 | j += PCI_VPD_INFO_FLD_HDR_SIZE; |
8027 | if (j + len > block_end || len != 4 || | |
8028 | memcmp(&data[j], "1028", 4)) | |
8029 | goto vpd_done; | |
4067a854 | 8030 | |
df25bc38 MC |
8031 | j = pci_vpd_find_info_keyword(data, i, rosize, |
8032 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
8033 | if (j < 0) | |
8034 | goto vpd_done; | |
4067a854 | 8035 | |
df25bc38 | 8036 | len = pci_vpd_info_field_size(&data[j]); |
4067a854 | 8037 | |
df25bc38 MC |
8038 | j += PCI_VPD_INFO_FLD_HDR_SIZE; |
8039 | if (j + len > block_end || len > BNX2_MAX_VER_SLEN) | |
76d99061 | 8040 | goto vpd_done; |
df25bc38 MC |
8041 | |
8042 | memcpy(bp->fw_version, &data[j], len); | |
8043 | bp->fw_version[len] = ' '; | |
76d99061 MC |
8044 | |
8045 | vpd_done: | |
8046 | kfree(data); | |
8047 | } | |
8048 | ||
cfd95a63 | 8049 | static int |
b6016b76 MC |
8050 | bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) |
8051 | { | |
8052 | struct bnx2 *bp; | |
58fc2ea4 | 8053 | int rc, i, j; |
b6016b76 | 8054 | u32 reg; |
40453c83 | 8055 | u64 dma_mask, persist_dma_mask; |
cd709aa9 | 8056 | int err; |
b6016b76 | 8057 | |
b6016b76 | 8058 | SET_NETDEV_DEV(dev, &pdev->dev); |
972ec0d4 | 8059 | bp = netdev_priv(dev); |
b6016b76 MC |
8060 | |
8061 | bp->flags = 0; | |
8062 | bp->phy_flags = 0; | |
8063 | ||
354fcd77 MC |
8064 | bp->temp_stats_blk = |
8065 | kzalloc(sizeof(struct statistics_block), GFP_KERNEL); | |
8066 | ||
8067 | if (bp->temp_stats_blk == NULL) { | |
8068 | rc = -ENOMEM; | |
8069 | goto err_out; | |
8070 | } | |
8071 | ||
b6016b76 MC |
8072 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ |
8073 | rc = pci_enable_device(pdev); | |
8074 | if (rc) { | |
3a9c6a49 | 8075 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
b6016b76 MC |
8076 | goto err_out; |
8077 | } | |
8078 | ||
8079 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
9b91cf9d | 8080 | dev_err(&pdev->dev, |
3a9c6a49 | 8081 | "Cannot find PCI device base address, aborting\n"); |
b6016b76 MC |
8082 | rc = -ENODEV; |
8083 | goto err_out_disable; | |
8084 | } | |
8085 | ||
8086 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
8087 | if (rc) { | |
3a9c6a49 | 8088 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
b6016b76 MC |
8089 | goto err_out_disable; |
8090 | } | |
8091 | ||
8092 | pci_set_master(pdev); | |
8093 | ||
85768271 | 8094 | bp->pm_cap = pdev->pm_cap; |
b6016b76 | 8095 | if (bp->pm_cap == 0) { |
9b91cf9d | 8096 | dev_err(&pdev->dev, |
3a9c6a49 | 8097 | "Cannot find power management capability, aborting\n"); |
b6016b76 MC |
8098 | rc = -EIO; |
8099 | goto err_out_release; | |
8100 | } | |
8101 | ||
b6016b76 MC |
8102 | bp->dev = dev; |
8103 | bp->pdev = pdev; | |
8104 | ||
8105 | spin_lock_init(&bp->phy_lock); | |
1b8227c4 | 8106 | spin_lock_init(&bp->indirect_lock); |
c5a88950 MC |
8107 | #ifdef BCM_CNIC |
8108 | mutex_init(&bp->cnic_lock); | |
8109 | #endif | |
c4028958 | 8110 | INIT_WORK(&bp->reset_task, bnx2_reset_task); |
b6016b76 | 8111 | |
c0357e97 FR |
8112 | bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID + |
8113 | TX_MAX_TSS_RINGS + 1)); | |
b6016b76 | 8114 | if (!bp->regview) { |
3a9c6a49 | 8115 | dev_err(&pdev->dev, "Cannot map register space, aborting\n"); |
b6016b76 MC |
8116 | rc = -ENOMEM; |
8117 | goto err_out_release; | |
8118 | } | |
8119 | ||
be7ff1af MC |
8120 | bnx2_set_power_state(bp, PCI_D0); |
8121 | ||
b6016b76 MC |
8122 | /* Configure byte swap and enable write to the reg_window registers. |
8123 | * Rely on CPU to do target byte swapping on big endian systems | |
8124 | * The chip's target access swapping will not swap all accesses | |
8125 | */ | |
e503e066 MC |
8126 | BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, |
8127 | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | | |
8128 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); | |
b6016b76 | 8129 | |
e503e066 | 8130 | bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID); |
b6016b76 | 8131 | |
4ce45e02 | 8132 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { |
e82760e7 JM |
8133 | if (!pci_is_pcie(pdev)) { |
8134 | dev_err(&pdev->dev, "Not PCIE, aborting\n"); | |
883e5151 MC |
8135 | rc = -EIO; |
8136 | goto err_out_unmap; | |
8137 | } | |
f86e82fb | 8138 | bp->flags |= BNX2_FLAG_PCIE; |
4ce45e02 | 8139 | if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax) |
f86e82fb | 8140 | bp->flags |= BNX2_FLAG_JUMBO_BROKEN; |
c239f279 MC |
8141 | |
8142 | /* AER (Advanced Error Reporting) hooks */ | |
8143 | err = pci_enable_pcie_error_reporting(pdev); | |
4bb9ebc7 MC |
8144 | if (!err) |
8145 | bp->flags |= BNX2_FLAG_AER_ENABLED; | |
c239f279 | 8146 | |
883e5151 | 8147 | } else { |
59b47d8a MC |
8148 | bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); |
8149 | if (bp->pcix_cap == 0) { | |
8150 | dev_err(&pdev->dev, | |
3a9c6a49 | 8151 | "Cannot find PCIX capability, aborting\n"); |
59b47d8a MC |
8152 | rc = -EIO; |
8153 | goto err_out_unmap; | |
8154 | } | |
61d9e3fa | 8155 | bp->flags |= BNX2_FLAG_BROKEN_STATS; |
59b47d8a MC |
8156 | } |
8157 | ||
4ce45e02 MC |
8158 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709 && |
8159 | BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) { | |
b4b36042 | 8160 | if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) |
f86e82fb | 8161 | bp->flags |= BNX2_FLAG_MSIX_CAP; |
b4b36042 MC |
8162 | } |
8163 | ||
4ce45e02 MC |
8164 | if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 && |
8165 | BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) { | |
8e6a72c4 | 8166 | if (pci_find_capability(pdev, PCI_CAP_ID_MSI)) |
f86e82fb | 8167 | bp->flags |= BNX2_FLAG_MSI_CAP; |
8e6a72c4 MC |
8168 | } |
8169 | ||
40453c83 | 8170 | /* 5708 cannot support DMA addresses > 40-bit. */ |
4ce45e02 | 8171 | if (BNX2_CHIP(bp) == BNX2_CHIP_5708) |
50cf156a | 8172 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
40453c83 | 8173 | else |
6a35528a | 8174 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
40453c83 MC |
8175 | |
8176 | /* Configure DMA attributes. */ | |
8177 | if (pci_set_dma_mask(pdev, dma_mask) == 0) { | |
8178 | dev->features |= NETIF_F_HIGHDMA; | |
8179 | rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask); | |
8180 | if (rc) { | |
8181 | dev_err(&pdev->dev, | |
3a9c6a49 | 8182 | "pci_set_consistent_dma_mask failed, aborting\n"); |
40453c83 MC |
8183 | goto err_out_unmap; |
8184 | } | |
284901a9 | 8185 | } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) { |
3a9c6a49 | 8186 | dev_err(&pdev->dev, "System does not support DMA, aborting\n"); |
40453c83 MC |
8187 | goto err_out_unmap; |
8188 | } | |
8189 | ||
f86e82fb | 8190 | if (!(bp->flags & BNX2_FLAG_PCIE)) |
883e5151 | 8191 | bnx2_get_pci_speed(bp); |
b6016b76 MC |
8192 | |
8193 | /* 5706A0 may falsely detect SERR and PERR. */ | |
4ce45e02 | 8194 | if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { |
e503e066 | 8195 | reg = BNX2_RD(bp, PCI_COMMAND); |
b6016b76 | 8196 | reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); |
e503e066 | 8197 | BNX2_WR(bp, PCI_COMMAND, reg); |
4ce45e02 | 8198 | } else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) && |
f86e82fb | 8199 | !(bp->flags & BNX2_FLAG_PCIX)) { |
b6016b76 | 8200 | |
9b91cf9d | 8201 | dev_err(&pdev->dev, |
3a9c6a49 | 8202 | "5706 A1 can only be used in a PCIX bus, aborting\n"); |
b6016b76 MC |
8203 | goto err_out_unmap; |
8204 | } | |
8205 | ||
8206 | bnx2_init_nvram(bp); | |
8207 | ||
2726d6e1 | 8208 | reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE); |
e3648b3d | 8209 | |
aefd90e4 MC |
8210 | if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID) |
8211 | bp->func = 1; | |
8212 | ||
e3648b3d | 8213 | if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == |
24cb230b | 8214 | BNX2_SHM_HDR_SIGNATURE_SIG) { |
aefd90e4 | 8215 | u32 off = bp->func << 2; |
24cb230b | 8216 | |
2726d6e1 | 8217 | bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off); |
24cb230b | 8218 | } else |
e3648b3d MC |
8219 | bp->shmem_base = HOST_VIEW_SHMEM_BASE; |
8220 | ||
b6016b76 MC |
8221 | /* Get the permanent MAC address. First we need to make sure the |
8222 | * firmware is actually running. | |
8223 | */ | |
2726d6e1 | 8224 | reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE); |
b6016b76 MC |
8225 | |
8226 | if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != | |
8227 | BNX2_DEV_INFO_SIGNATURE_MAGIC) { | |
3a9c6a49 | 8228 | dev_err(&pdev->dev, "Firmware not running, aborting\n"); |
b6016b76 MC |
8229 | rc = -ENODEV; |
8230 | goto err_out_unmap; | |
8231 | } | |
8232 | ||
76d99061 MC |
8233 | bnx2_read_vpd_fw_ver(bp); |
8234 | ||
8235 | j = strlen(bp->fw_version); | |
2726d6e1 | 8236 | reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV); |
76d99061 | 8237 | for (i = 0; i < 3 && j < 24; i++) { |
58fc2ea4 MC |
8238 | u8 num, k, skip0; |
8239 | ||
76d99061 MC |
8240 | if (i == 0) { |
8241 | bp->fw_version[j++] = 'b'; | |
8242 | bp->fw_version[j++] = 'c'; | |
8243 | bp->fw_version[j++] = ' '; | |
8244 | } | |
58fc2ea4 MC |
8245 | num = (u8) (reg >> (24 - (i * 8))); |
8246 | for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { | |
8247 | if (num >= k || !skip0 || k == 1) { | |
8248 | bp->fw_version[j++] = (num / k) + '0'; | |
8249 | skip0 = 0; | |
8250 | } | |
8251 | } | |
8252 | if (i != 2) | |
8253 | bp->fw_version[j++] = '.'; | |
8254 | } | |
2726d6e1 | 8255 | reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE); |
846f5c62 MC |
8256 | if (reg & BNX2_PORT_FEATURE_WOL_ENABLED) |
8257 | bp->wol = 1; | |
8258 | ||
8259 | if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) { | |
f86e82fb | 8260 | bp->flags |= BNX2_FLAG_ASF_ENABLE; |
c2d3db8c MC |
8261 | |
8262 | for (i = 0; i < 30; i++) { | |
2726d6e1 | 8263 | reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); |
c2d3db8c MC |
8264 | if (reg & BNX2_CONDITION_MFW_RUN_MASK) |
8265 | break; | |
8266 | msleep(10); | |
8267 | } | |
8268 | } | |
2726d6e1 | 8269 | reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); |
58fc2ea4 MC |
8270 | reg &= BNX2_CONDITION_MFW_RUN_MASK; |
8271 | if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN && | |
8272 | reg != BNX2_CONDITION_MFW_RUN_NONE) { | |
2726d6e1 | 8273 | u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR); |
58fc2ea4 | 8274 | |
76d99061 MC |
8275 | if (j < 32) |
8276 | bp->fw_version[j++] = ' '; | |
8277 | for (i = 0; i < 3 && j < 28; i++) { | |
2726d6e1 | 8278 | reg = bnx2_reg_rd_ind(bp, addr + i * 4); |
3aeb7d22 | 8279 | reg = be32_to_cpu(reg); |
58fc2ea4 MC |
8280 | memcpy(&bp->fw_version[j], ®, 4); |
8281 | j += 4; | |
8282 | } | |
8283 | } | |
b6016b76 | 8284 | |
2726d6e1 | 8285 | reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER); |
b6016b76 MC |
8286 | bp->mac_addr[0] = (u8) (reg >> 8); |
8287 | bp->mac_addr[1] = (u8) reg; | |
8288 | ||
2726d6e1 | 8289 | reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER); |
b6016b76 MC |
8290 | bp->mac_addr[2] = (u8) (reg >> 24); |
8291 | bp->mac_addr[3] = (u8) (reg >> 16); | |
8292 | bp->mac_addr[4] = (u8) (reg >> 8); | |
8293 | bp->mac_addr[5] = (u8) reg; | |
8294 | ||
2bc4078e | 8295 | bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT; |
932f3772 | 8296 | bnx2_set_rx_ring_size(bp, 255); |
b6016b76 | 8297 | |
cf7474a6 | 8298 | bp->tx_quick_cons_trip_int = 2; |
b6016b76 | 8299 | bp->tx_quick_cons_trip = 20; |
cf7474a6 | 8300 | bp->tx_ticks_int = 18; |
b6016b76 | 8301 | bp->tx_ticks = 80; |
6aa20a22 | 8302 | |
cf7474a6 MC |
8303 | bp->rx_quick_cons_trip_int = 2; |
8304 | bp->rx_quick_cons_trip = 12; | |
b6016b76 MC |
8305 | bp->rx_ticks_int = 18; |
8306 | bp->rx_ticks = 18; | |
8307 | ||
7ea6920e | 8308 | bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS; |
b6016b76 | 8309 | |
ac392abc | 8310 | bp->current_interval = BNX2_TIMER_INTERVAL; |
b6016b76 | 8311 | |
5b0c76ad MC |
8312 | bp->phy_addr = 1; |
8313 | ||
b6016b76 | 8314 | /* Disable WOL support if we are running on a SERDES chip. */ |
4ce45e02 | 8315 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
253c8b75 | 8316 | bnx2_get_5709_media(bp); |
4ce45e02 | 8317 | else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT) |
583c28e5 | 8318 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
bac0dff6 | 8319 | |
0d8a6571 | 8320 | bp->phy_port = PORT_TP; |
583c28e5 | 8321 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
0d8a6571 | 8322 | bp->phy_port = PORT_FIBRE; |
2726d6e1 | 8323 | reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); |
846f5c62 | 8324 | if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) { |
f86e82fb | 8325 | bp->flags |= BNX2_FLAG_NO_WOL; |
846f5c62 MC |
8326 | bp->wol = 0; |
8327 | } | |
4ce45e02 | 8328 | if (BNX2_CHIP(bp) == BNX2_CHIP_5706) { |
38ea3686 MC |
8329 | /* Don't do parallel detect on this board because of |
8330 | * some board problems. The link will not go down | |
8331 | * if we do parallel detect. | |
8332 | */ | |
8333 | if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP && | |
8334 | pdev->subsystem_device == 0x310c) | |
8335 | bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL; | |
8336 | } else { | |
5b0c76ad | 8337 | bp->phy_addr = 2; |
5b0c76ad | 8338 | if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) |
583c28e5 | 8339 | bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; |
5b0c76ad | 8340 | } |
4ce45e02 MC |
8341 | } else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 || |
8342 | BNX2_CHIP(bp) == BNX2_CHIP_5708) | |
583c28e5 | 8343 | bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX; |
4ce45e02 MC |
8344 | else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 && |
8345 | (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax || | |
8346 | BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx)) | |
583c28e5 | 8347 | bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC; |
b6016b76 | 8348 | |
7c62e83b MC |
8349 | bnx2_init_fw_cap(bp); |
8350 | ||
4ce45e02 MC |
8351 | if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) || |
8352 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) || | |
8353 | (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) || | |
e503e066 | 8354 | !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) { |
f86e82fb | 8355 | bp->flags |= BNX2_FLAG_NO_WOL; |
846f5c62 MC |
8356 | bp->wol = 0; |
8357 | } | |
dda1e390 | 8358 | |
6d5e85c7 MC |
8359 | if (bp->flags & BNX2_FLAG_NO_WOL) |
8360 | device_set_wakeup_capable(&bp->pdev->dev, false); | |
8361 | else | |
8362 | device_set_wakeup_enable(&bp->pdev->dev, bp->wol); | |
8363 | ||
4ce45e02 | 8364 | if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { |
b6016b76 MC |
8365 | bp->tx_quick_cons_trip_int = |
8366 | bp->tx_quick_cons_trip; | |
8367 | bp->tx_ticks_int = bp->tx_ticks; | |
8368 | bp->rx_quick_cons_trip_int = | |
8369 | bp->rx_quick_cons_trip; | |
8370 | bp->rx_ticks_int = bp->rx_ticks; | |
8371 | bp->comp_prod_trip_int = bp->comp_prod_trip; | |
8372 | bp->com_ticks_int = bp->com_ticks; | |
8373 | bp->cmd_ticks_int = bp->cmd_ticks; | |
8374 | } | |
8375 | ||
f9317a40 MC |
8376 | /* Disable MSI on 5706 if AMD 8132 bridge is found. |
8377 | * | |
8378 | * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes | |
8379 | * with byte enables disabled on the unused 32-bit word. This is legal | |
8380 | * but causes problems on the AMD 8132 which will eventually stop | |
8381 | * responding after a while. | |
8382 | * | |
8383 | * AMD believes this incompatibility is unique to the 5706, and | |
88187dfa | 8384 | * prefers to locally disable MSI rather than globally disabling it. |
f9317a40 | 8385 | */ |
4ce45e02 | 8386 | if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) { |
f9317a40 MC |
8387 | struct pci_dev *amd_8132 = NULL; |
8388 | ||
8389 | while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD, | |
8390 | PCI_DEVICE_ID_AMD_8132_BRIDGE, | |
8391 | amd_8132))) { | |
f9317a40 | 8392 | |
44c10138 AK |
8393 | if (amd_8132->revision >= 0x10 && |
8394 | amd_8132->revision <= 0x13) { | |
f9317a40 MC |
8395 | disable_msi = 1; |
8396 | pci_dev_put(amd_8132); | |
8397 | break; | |
8398 | } | |
8399 | } | |
8400 | } | |
8401 | ||
deaf391b | 8402 | bnx2_set_default_link(bp); |
b6016b76 MC |
8403 | bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; |
8404 | ||
cd339a0e | 8405 | init_timer(&bp->timer); |
ac392abc | 8406 | bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL); |
cd339a0e MC |
8407 | bp->timer.data = (unsigned long) bp; |
8408 | bp->timer.function = bnx2_timer; | |
8409 | ||
7625eb2f | 8410 | #ifdef BCM_CNIC |
41c2178a MC |
8411 | if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN) |
8412 | bp->cnic_eth_dev.max_iscsi_conn = | |
8413 | (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) & | |
8414 | BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT; | |
4bd9b0ff | 8415 | bp->cnic_probe = bnx2_cnic_probe; |
7625eb2f | 8416 | #endif |
c239f279 MC |
8417 | pci_save_state(pdev); |
8418 | ||
b6016b76 MC |
8419 | return 0; |
8420 | ||
8421 | err_out_unmap: | |
4bb9ebc7 | 8422 | if (bp->flags & BNX2_FLAG_AER_ENABLED) { |
c239f279 | 8423 | pci_disable_pcie_error_reporting(pdev); |
4bb9ebc7 MC |
8424 | bp->flags &= ~BNX2_FLAG_AER_ENABLED; |
8425 | } | |
c239f279 | 8426 | |
c0357e97 FR |
8427 | pci_iounmap(pdev, bp->regview); |
8428 | bp->regview = NULL; | |
b6016b76 MC |
8429 | |
8430 | err_out_release: | |
8431 | pci_release_regions(pdev); | |
8432 | ||
8433 | err_out_disable: | |
8434 | pci_disable_device(pdev); | |
8435 | pci_set_drvdata(pdev, NULL); | |
8436 | ||
8437 | err_out: | |
8438 | return rc; | |
8439 | } | |
8440 | ||
cfd95a63 | 8441 | static char * |
883e5151 MC |
8442 | bnx2_bus_string(struct bnx2 *bp, char *str) |
8443 | { | |
8444 | char *s = str; | |
8445 | ||
f86e82fb | 8446 | if (bp->flags & BNX2_FLAG_PCIE) { |
883e5151 MC |
8447 | s += sprintf(s, "PCI Express"); |
8448 | } else { | |
8449 | s += sprintf(s, "PCI"); | |
f86e82fb | 8450 | if (bp->flags & BNX2_FLAG_PCIX) |
883e5151 | 8451 | s += sprintf(s, "-X"); |
f86e82fb | 8452 | if (bp->flags & BNX2_FLAG_PCI_32BIT) |
883e5151 MC |
8453 | s += sprintf(s, " 32-bit"); |
8454 | else | |
8455 | s += sprintf(s, " 64-bit"); | |
8456 | s += sprintf(s, " %dMHz", bp->bus_speed_mhz); | |
8457 | } | |
8458 | return str; | |
8459 | } | |
8460 | ||
f048fa9c MC |
8461 | static void |
8462 | bnx2_del_napi(struct bnx2 *bp) | |
8463 | { | |
8464 | int i; | |
8465 | ||
8466 | for (i = 0; i < bp->irq_nvecs; i++) | |
8467 | netif_napi_del(&bp->bnx2_napi[i].napi); | |
8468 | } | |
8469 | ||
8470 | static void | |
35efa7c1 MC |
8471 | bnx2_init_napi(struct bnx2 *bp) |
8472 | { | |
b4b36042 | 8473 | int i; |
35efa7c1 | 8474 | |
4327ba43 | 8475 | for (i = 0; i < bp->irq_nvecs; i++) { |
35e9010b MC |
8476 | struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; |
8477 | int (*poll)(struct napi_struct *, int); | |
8478 | ||
8479 | if (i == 0) | |
8480 | poll = bnx2_poll; | |
8481 | else | |
f0ea2e63 | 8482 | poll = bnx2_poll_msix; |
35e9010b MC |
8483 | |
8484 | netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64); | |
b4b36042 MC |
8485 | bnapi->bp = bp; |
8486 | } | |
35efa7c1 MC |
8487 | } |
8488 | ||
0421eae6 SH |
8489 | static const struct net_device_ops bnx2_netdev_ops = { |
8490 | .ndo_open = bnx2_open, | |
8491 | .ndo_start_xmit = bnx2_start_xmit, | |
8492 | .ndo_stop = bnx2_close, | |
5d07bf26 | 8493 | .ndo_get_stats64 = bnx2_get_stats64, |
0421eae6 SH |
8494 | .ndo_set_rx_mode = bnx2_set_rx_mode, |
8495 | .ndo_do_ioctl = bnx2_ioctl, | |
8496 | .ndo_validate_addr = eth_validate_addr, | |
8497 | .ndo_set_mac_address = bnx2_change_mac_addr, | |
8498 | .ndo_change_mtu = bnx2_change_mtu, | |
8d7dfc2b MM |
8499 | .ndo_fix_features = bnx2_fix_features, |
8500 | .ndo_set_features = bnx2_set_features, | |
0421eae6 | 8501 | .ndo_tx_timeout = bnx2_tx_timeout, |
257ddbda | 8502 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0421eae6 SH |
8503 | .ndo_poll_controller = poll_bnx2, |
8504 | #endif | |
8505 | }; | |
8506 | ||
cfd95a63 | 8507 | static int |
b6016b76 MC |
8508 | bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
8509 | { | |
8510 | static int version_printed = 0; | |
c0357e97 | 8511 | struct net_device *dev; |
b6016b76 | 8512 | struct bnx2 *bp; |
0795af57 | 8513 | int rc; |
883e5151 | 8514 | char str[40]; |
b6016b76 MC |
8515 | |
8516 | if (version_printed++ == 0) | |
3a9c6a49 | 8517 | pr_info("%s", version); |
b6016b76 MC |
8518 | |
8519 | /* dev zeroed in init_etherdev */ | |
706bf240 | 8520 | dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS); |
b6016b76 MC |
8521 | if (!dev) |
8522 | return -ENOMEM; | |
8523 | ||
8524 | rc = bnx2_init_board(pdev, dev); | |
c0357e97 FR |
8525 | if (rc < 0) |
8526 | goto err_free; | |
b6016b76 | 8527 | |
0421eae6 | 8528 | dev->netdev_ops = &bnx2_netdev_ops; |
b6016b76 | 8529 | dev->watchdog_timeo = TX_TIMEOUT; |
b6016b76 | 8530 | dev->ethtool_ops = &bnx2_ethtool_ops; |
b6016b76 | 8531 | |
972ec0d4 | 8532 | bp = netdev_priv(dev); |
b6016b76 | 8533 | |
1b2f922f MC |
8534 | pci_set_drvdata(pdev, dev); |
8535 | ||
8536 | memcpy(dev->dev_addr, bp->mac_addr, 6); | |
1b2f922f | 8537 | |
8d7dfc2b MM |
8538 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
8539 | NETIF_F_TSO | NETIF_F_TSO_ECN | | |
8540 | NETIF_F_RXHASH | NETIF_F_RXCSUM; | |
8541 | ||
4ce45e02 | 8542 | if (BNX2_CHIP(bp) == BNX2_CHIP_5709) |
8d7dfc2b MM |
8543 | dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; |
8544 | ||
8545 | dev->vlan_features = dev->hw_features; | |
f646968f | 8546 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
8d7dfc2b | 8547 | dev->features |= dev->hw_features; |
01789349 | 8548 | dev->priv_flags |= IFF_UNICAST_FLT; |
8d7dfc2b | 8549 | |
b6016b76 | 8550 | if ((rc = register_netdev(dev))) { |
9b91cf9d | 8551 | dev_err(&pdev->dev, "Cannot register net device\n"); |
57579f76 | 8552 | goto error; |
b6016b76 MC |
8553 | } |
8554 | ||
c0357e97 FR |
8555 | netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, " |
8556 | "node addr %pM\n", board_info[ent->driver_data].name, | |
4ce45e02 MC |
8557 | ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A', |
8558 | ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4), | |
c0357e97 FR |
8559 | bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0), |
8560 | pdev->irq, dev->dev_addr); | |
b6016b76 | 8561 | |
b6016b76 | 8562 | return 0; |
57579f76 MC |
8563 | |
8564 | error: | |
fda4d85d | 8565 | pci_iounmap(pdev, bp->regview); |
57579f76 MC |
8566 | pci_release_regions(pdev); |
8567 | pci_disable_device(pdev); | |
8568 | pci_set_drvdata(pdev, NULL); | |
c0357e97 | 8569 | err_free: |
57579f76 MC |
8570 | free_netdev(dev); |
8571 | return rc; | |
b6016b76 MC |
8572 | } |
8573 | ||
cfd95a63 | 8574 | static void |
b6016b76 MC |
8575 | bnx2_remove_one(struct pci_dev *pdev) |
8576 | { | |
8577 | struct net_device *dev = pci_get_drvdata(pdev); | |
972ec0d4 | 8578 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 MC |
8579 | |
8580 | unregister_netdev(dev); | |
8581 | ||
8333a46a | 8582 | del_timer_sync(&bp->timer); |
cd634019 | 8583 | cancel_work_sync(&bp->reset_task); |
8333a46a | 8584 | |
c0357e97 | 8585 | pci_iounmap(bp->pdev, bp->regview); |
b6016b76 | 8586 | |
354fcd77 MC |
8587 | kfree(bp->temp_stats_blk); |
8588 | ||
4bb9ebc7 | 8589 | if (bp->flags & BNX2_FLAG_AER_ENABLED) { |
c239f279 | 8590 | pci_disable_pcie_error_reporting(pdev); |
4bb9ebc7 MC |
8591 | bp->flags &= ~BNX2_FLAG_AER_ENABLED; |
8592 | } | |
cd709aa9 | 8593 | |
7880b72e | 8594 | bnx2_release_firmware(bp); |
8595 | ||
c239f279 | 8596 | free_netdev(dev); |
cd709aa9 | 8597 | |
b6016b76 MC |
8598 | pci_release_regions(pdev); |
8599 | pci_disable_device(pdev); | |
8600 | pci_set_drvdata(pdev, NULL); | |
8601 | } | |
8602 | ||
8603 | static int | |
829ca9a3 | 8604 | bnx2_suspend(struct pci_dev *pdev, pm_message_t state) |
b6016b76 MC |
8605 | { |
8606 | struct net_device *dev = pci_get_drvdata(pdev); | |
972ec0d4 | 8607 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 8608 | |
6caebb02 MC |
8609 | /* PCI register 4 needs to be saved whether netif_running() or not. |
8610 | * MSI address and data need to be saved if using MSI and | |
8611 | * netif_running(). | |
8612 | */ | |
8613 | pci_save_state(pdev); | |
b6016b76 MC |
8614 | if (!netif_running(dev)) |
8615 | return 0; | |
8616 | ||
23f333a2 | 8617 | cancel_work_sync(&bp->reset_task); |
212f9934 | 8618 | bnx2_netif_stop(bp, true); |
b6016b76 MC |
8619 | netif_device_detach(dev); |
8620 | del_timer_sync(&bp->timer); | |
74bf4ba3 | 8621 | bnx2_shutdown_chip(bp); |
b6016b76 | 8622 | bnx2_free_skbs(bp); |
829ca9a3 | 8623 | bnx2_set_power_state(bp, pci_choose_state(pdev, state)); |
b6016b76 MC |
8624 | return 0; |
8625 | } | |
8626 | ||
8627 | static int | |
8628 | bnx2_resume(struct pci_dev *pdev) | |
8629 | { | |
8630 | struct net_device *dev = pci_get_drvdata(pdev); | |
972ec0d4 | 8631 | struct bnx2 *bp = netdev_priv(dev); |
b6016b76 | 8632 | |
6caebb02 | 8633 | pci_restore_state(pdev); |
b6016b76 MC |
8634 | if (!netif_running(dev)) |
8635 | return 0; | |
8636 | ||
829ca9a3 | 8637 | bnx2_set_power_state(bp, PCI_D0); |
b6016b76 | 8638 | netif_device_attach(dev); |
9a120bc5 | 8639 | bnx2_init_nic(bp, 1); |
212f9934 | 8640 | bnx2_netif_start(bp, true); |
b6016b76 MC |
8641 | return 0; |
8642 | } | |
8643 | ||
6ff2da49 WX |
8644 | /** |
8645 | * bnx2_io_error_detected - called when PCI error is detected | |
8646 | * @pdev: Pointer to PCI device | |
8647 | * @state: The current pci connection state | |
8648 | * | |
8649 | * This function is called after a PCI bus error affecting | |
8650 | * this device has been detected. | |
8651 | */ | |
8652 | static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev, | |
8653 | pci_channel_state_t state) | |
8654 | { | |
8655 | struct net_device *dev = pci_get_drvdata(pdev); | |
8656 | struct bnx2 *bp = netdev_priv(dev); | |
8657 | ||
8658 | rtnl_lock(); | |
8659 | netif_device_detach(dev); | |
8660 | ||
2ec3de26 DN |
8661 | if (state == pci_channel_io_perm_failure) { |
8662 | rtnl_unlock(); | |
8663 | return PCI_ERS_RESULT_DISCONNECT; | |
8664 | } | |
8665 | ||
6ff2da49 | 8666 | if (netif_running(dev)) { |
212f9934 | 8667 | bnx2_netif_stop(bp, true); |
6ff2da49 WX |
8668 | del_timer_sync(&bp->timer); |
8669 | bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); | |
8670 | } | |
8671 | ||
8672 | pci_disable_device(pdev); | |
8673 | rtnl_unlock(); | |
8674 | ||
8675 | /* Request a slot slot reset. */ | |
8676 | return PCI_ERS_RESULT_NEED_RESET; | |
8677 | } | |
8678 | ||
8679 | /** | |
8680 | * bnx2_io_slot_reset - called after the pci bus has been reset. | |
8681 | * @pdev: Pointer to PCI device | |
8682 | * | |
8683 | * Restart the card from scratch, as if from a cold-boot. | |
8684 | */ | |
8685 | static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev) | |
8686 | { | |
8687 | struct net_device *dev = pci_get_drvdata(pdev); | |
8688 | struct bnx2 *bp = netdev_priv(dev); | |
02481bc6 MC |
8689 | pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; |
8690 | int err = 0; | |
6ff2da49 WX |
8691 | |
8692 | rtnl_lock(); | |
8693 | if (pci_enable_device(pdev)) { | |
8694 | dev_err(&pdev->dev, | |
3a9c6a49 | 8695 | "Cannot re-enable PCI device after reset\n"); |
cd709aa9 JF |
8696 | } else { |
8697 | pci_set_master(pdev); | |
8698 | pci_restore_state(pdev); | |
8699 | pci_save_state(pdev); | |
8700 | ||
8701 | if (netif_running(dev)) { | |
8702 | bnx2_set_power_state(bp, PCI_D0); | |
02481bc6 | 8703 | err = bnx2_init_nic(bp, 1); |
cd709aa9 | 8704 | } |
02481bc6 MC |
8705 | if (!err) |
8706 | result = PCI_ERS_RESULT_RECOVERED; | |
8707 | } | |
8708 | ||
8709 | if (result != PCI_ERS_RESULT_RECOVERED && netif_running(dev)) { | |
8710 | bnx2_napi_enable(bp); | |
8711 | dev_close(dev); | |
6ff2da49 | 8712 | } |
cd709aa9 | 8713 | rtnl_unlock(); |
6ff2da49 | 8714 | |
4bb9ebc7 | 8715 | if (!(bp->flags & BNX2_FLAG_AER_ENABLED)) |
c239f279 MC |
8716 | return result; |
8717 | ||
cd709aa9 JF |
8718 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
8719 | if (err) { | |
8720 | dev_err(&pdev->dev, | |
8721 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", | |
8722 | err); /* non-fatal, continue */ | |
6ff2da49 WX |
8723 | } |
8724 | ||
cd709aa9 | 8725 | return result; |
6ff2da49 WX |
8726 | } |
8727 | ||
8728 | /** | |
8729 | * bnx2_io_resume - called when traffic can start flowing again. | |
8730 | * @pdev: Pointer to PCI device | |
8731 | * | |
8732 | * This callback is called when the error recovery driver tells us that | |
8733 | * its OK to resume normal operation. | |
8734 | */ | |
8735 | static void bnx2_io_resume(struct pci_dev *pdev) | |
8736 | { | |
8737 | struct net_device *dev = pci_get_drvdata(pdev); | |
8738 | struct bnx2 *bp = netdev_priv(dev); | |
8739 | ||
8740 | rtnl_lock(); | |
8741 | if (netif_running(dev)) | |
212f9934 | 8742 | bnx2_netif_start(bp, true); |
6ff2da49 WX |
8743 | |
8744 | netif_device_attach(dev); | |
8745 | rtnl_unlock(); | |
8746 | } | |
8747 | ||
fda4d85d | 8748 | static const struct pci_error_handlers bnx2_err_handler = { |
6ff2da49 WX |
8749 | .error_detected = bnx2_io_error_detected, |
8750 | .slot_reset = bnx2_io_slot_reset, | |
8751 | .resume = bnx2_io_resume, | |
8752 | }; | |
8753 | ||
b6016b76 | 8754 | static struct pci_driver bnx2_pci_driver = { |
14ab9b86 PH |
8755 | .name = DRV_MODULE_NAME, |
8756 | .id_table = bnx2_pci_tbl, | |
8757 | .probe = bnx2_init_one, | |
cfd95a63 | 8758 | .remove = bnx2_remove_one, |
14ab9b86 PH |
8759 | .suspend = bnx2_suspend, |
8760 | .resume = bnx2_resume, | |
6ff2da49 | 8761 | .err_handler = &bnx2_err_handler, |
b6016b76 MC |
8762 | }; |
8763 | ||
5a4123f3 | 8764 | module_pci_driver(bnx2_pci_driver); |