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netprio_cgroup: Fix build break
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
dc187cb3 3 * Copyright (c) 2004-2011 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
3a9c6a49 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
f2a4f052
MC		 13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16
17#include <linux/kernel.h>
18#include <linux/timer.h>
19#include <linux/errno.h>
20#include <linux/ioport.h>
21#include <linux/slab.h>
22#include <linux/vmalloc.h>
23#include <linux/interrupt.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28#include <linux/skbuff.h>
29#include <linux/dma-mapping.h>
1977f032 30#include <linux/bitops.h>
f2a4f052
MC		 31#include <asm/io.h>
32#include <asm/irq.h>
33#include <linux/delay.h>
34#include <asm/byteorder.h>
c86a31f4 35#include <asm/page.h>
f2a4f052
MC		 36#include <linux/time.h>
37#include <linux/ethtool.h>
38#include <linux/mii.h>
01789349 39#include <linux/if.h>
f2a4f052 40#include <linux/if_vlan.h>
f2a4f052 41#include <net/ip.h>
de081fa5 42#include <net/tcp.h>
f2a4f052 43#include <net/checksum.h>
f2a4f052
MC		 44#include <linux/workqueue.h>
45#include <linux/crc32.h>
46#include <linux/prefetch.h>
29b12174 47#include <linux/cache.h>
57579f76 48#include <linux/firmware.h>
706bf240 49#include <linux/log2.h>
cd709aa9 50#include <linux/aer.h>
f2a4f052 51
4edd473f
MC		 52#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
53#define BCM_CNIC 1
54#include "cnic_if.h"
55#endif
b6016b76
MC		 56#include "bnx2.h"
57#include "bnx2_fw.h"
b3448b0b 58
b6016b76 59#define DRV_MODULE_NAME "bnx2"
3aeb7d22
MC		 60#define DRV_MODULE_VERSION "2.1.11"
61#define DRV_MODULE_RELDATE "July 20, 2011"
0268102d 62#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.1.fw"
22fa159d 63#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
dc187cb3 64#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1a.fw"
22fa159d
MC		 65#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
66#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
b6016b76
MC		 67
68#define RUN_AT(x) (jiffies + (x))
69
70/* Time in jiffies before concluding the transmitter is hung. */
71#define TX_TIMEOUT (5*HZ)
72
fefa8645 73static char version[] __devinitdata =
b6016b76
MC		 74 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
75
76MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
453a9c6e 77MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
b6016b76
MC		 78MODULE_LICENSE("GPL");
79MODULE_VERSION(DRV_MODULE_VERSION);
57579f76
MC		 80MODULE_FIRMWARE(FW_MIPS_FILE_06);
81MODULE_FIRMWARE(FW_RV2P_FILE_06);
82MODULE_FIRMWARE(FW_MIPS_FILE_09);
83MODULE_FIRMWARE(FW_RV2P_FILE_09);
078b0735 84MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
b6016b76
MC		 85
86static int disable_msi = 0;
87
88module_param(disable_msi, int, 0);
89MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
90
91typedef enum {
92 BCM5706 = 0,
93 NC370T,
94 NC370I,
95 BCM5706S,
96 NC370F,
5b0c76ad
MC		 97 BCM5708,
98 BCM5708S,
bac0dff6 99 BCM5709,
27a005b8 100 BCM5709S,
7bb0a04f 101 BCM5716,
1caacecb 102 BCM5716S,
b6016b76
MC		 103} board_t;
104
105/* indexed by board_t, above */
fefa8645 106static struct {
b6016b76
MC		 107 char *name;
108} board_info[] __devinitdata = {
109 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
110 { "HP NC370T Multifunction Gigabit Server Adapter" },
111 { "HP NC370i Multifunction Gigabit Server Adapter" },
112 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
113 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 114 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
115 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 116 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 117 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
7bb0a04f 118 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
1caacecb 119 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
b6016b76
MC		 120 };
121
7bb0a04f 122static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
b6016b76
MC		 123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
124 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
126 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
132 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
133 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 135 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 137 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 139 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
7bb0a04f
MC		 141 { PCI_VENDOR_ID_BROADCOM, 0x163b,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
1caacecb 143 { PCI_VENDOR_ID_BROADCOM, 0x163c,
1f2435e5 144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
b6016b76
MC		 145 { 0, }
146};
147
0ced9d01 148static const struct flash_spec flash_table[] =
b6016b76 149{
e30372c9
MC		 150#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
151#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 152 /* Slow EEPROM */
37137709 153 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 154 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 155 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
156 "EEPROM - slow"},
37137709
MC		 157 /* Expansion entry 0001 */
158 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 159 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 160 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
161 "Entry 0001"},
b6016b76
MC		 162 /* Saifun SA25F010 (non-buffered flash) */
163 /* strap, cfg1, & write1 need updates */
37137709 164 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 165 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 166 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
167 "Non-buffered flash (128kB)"},
168 /* Saifun SA25F020 (non-buffered flash) */
169 /* strap, cfg1, & write1 need updates */
37137709 170 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 171 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 172 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
173 "Non-buffered flash (256kB)"},
37137709
MC		 174 /* Expansion entry 0100 */
175 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
178 "Entry 0100"},
179 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 180 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 181 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 182 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
183 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
184 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
185 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 186 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 187 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
188 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
189 /* Saifun SA25F005 (non-buffered flash) */
190 /* strap, cfg1, & write1 need updates */
191 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 192 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 193 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
194 "Non-buffered flash (64kB)"},
195 /* Fast EEPROM */
196 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 197 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 198 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
199 "EEPROM - fast"},
200 /* Expansion entry 1001 */
201 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 202 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 203 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
204 "Entry 1001"},
205 /* Expansion entry 1010 */
206 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 208 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
209 "Entry 1010"},
210 /* ATMEL AT45DB011B (buffered flash) */
211 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 212 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 213 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
214 "Buffered flash (128kB)"},
215 /* Expansion entry 1100 */
216 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 217 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 218 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
219 "Entry 1100"},
220 /* Expansion entry 1101 */
221 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 222 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 223 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
224 "Entry 1101"},
225 /* Ateml Expansion entry 1110 */
226 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 227 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 228 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
229 "Entry 1110 (Atmel)"},
230 /* ATMEL AT45DB021B (buffered flash) */
231 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 232 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 233 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
234 "Buffered flash (256kB)"},
b6016b76
MC		 235};
236
0ced9d01 237static const struct flash_spec flash_5709 = {
e30372c9
MC		 238 .flags = BNX2_NV_BUFFERED,
239 .page_bits = BCM5709_FLASH_PAGE_BITS,
240 .page_size = BCM5709_FLASH_PAGE_SIZE,
241 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
242 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
243 .name = "5709 Buffered flash (256kB)",
244};
245
b6016b76
MC		 246MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
247
4327ba43 248static void bnx2_init_napi(struct bnx2 *bp);
f048fa9c 249static void bnx2_del_napi(struct bnx2 *bp);
4327ba43 250
35e9010b 251static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
e89bbf10 252{
2f8af120 253 u32 diff;
e89bbf10 254
11848b96
MC		 255 /* Tell compiler to fetch tx_prod and tx_cons from memory. */
256 barrier();
faac9c4b
MC		 257
258 /* The ring uses 256 indices for 255 entries, one of them
259 * needs to be skipped.
260 */
35e9010b 261 diff = txr->tx_prod - txr->tx_cons;
faac9c4b
MC		 262 if (unlikely(diff >= TX_DESC_CNT)) {
263 diff &= 0xffff;
264 if (diff == TX_DESC_CNT)
265 diff = MAX_TX_DESC_CNT;
266 }
807540ba 267 return bp->tx_ring_size - diff;
e89bbf10
MC		 268}
269
b6016b76
MC		 270static u32
271bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
272{
1b8227c4
MC		 273 u32 val;
274
275 spin_lock_bh(&bp->indirect_lock);
b6016b76 276 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 277 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
278 spin_unlock_bh(&bp->indirect_lock);
279 return val;
b6016b76
MC		 280}
281
282static void
283bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
284{
1b8227c4 285 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 288 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 289}
290
2726d6e1
MC		 291static void
292bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
293{
294 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
295}
296
297static u32
298bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
299{
807540ba 300 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
2726d6e1
MC		 301}
302
b6016b76
MC		 303static void
304bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
305{
306 offset += cid_addr;
1b8227c4 307 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 308 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
309 int i;
310
311 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
312 REG_WR(bp, BNX2_CTX_CTX_CTRL,
313 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
314 for (i = 0; i < 5; i++) {
59b47d8a
MC		 315 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
316 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
317 break;
318 udelay(5);
319 }
320 } else {
321 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
322 REG_WR(bp, BNX2_CTX_DATA, val);
323 }
1b8227c4 324 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 325}
326
4edd473f
MC		 327#ifdef BCM_CNIC
328static int
329bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
330{
331 struct bnx2 *bp = netdev_priv(dev);
332 struct drv_ctl_io *io = &info->data.io;
333
334 switch (info->cmd) {
335 case DRV_CTL_IO_WR_CMD:
336 bnx2_reg_wr_ind(bp, io->offset, io->data);
337 break;
338 case DRV_CTL_IO_RD_CMD:
339 io->data = bnx2_reg_rd_ind(bp, io->offset);
340 break;
341 case DRV_CTL_CTX_WR_CMD:
342 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
343 break;
344 default:
345 return -EINVAL;
346 }
347 return 0;
348}
349
350static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
351{
352 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
353 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
354 int sb_id;
355
356 if (bp->flags & BNX2_FLAG_USING_MSIX) {
357 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
358 bnapi->cnic_present = 0;
359 sb_id = bp->irq_nvecs;
360 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
361 } else {
362 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
363 bnapi->cnic_tag = bnapi->last_status_idx;
364 bnapi->cnic_present = 1;
365 sb_id = 0;
366 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
367 }
368
369 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
370 cp->irq_arr[0].status_blk = (void *)
371 ((unsigned long) bnapi->status_blk.msi +
372 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
373 cp->irq_arr[0].status_blk_num = sb_id;
374 cp->num_irq = 1;
375}
376
377static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
378 void *data)
379{
380 struct bnx2 *bp = netdev_priv(dev);
381 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
382
383 if (ops == NULL)
384 return -EINVAL;
385
386 if (cp->drv_state & CNIC_DRV_STATE_REGD)
387 return -EBUSY;
388
41c2178a
MC		 389 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))
390 return -ENODEV;
391
4edd473f
MC		 392 bp->cnic_data = data;
393 rcu_assign_pointer(bp->cnic_ops, ops);
394
395 cp->num_irq = 0;
396 cp->drv_state = CNIC_DRV_STATE_REGD;
397
398 bnx2_setup_cnic_irq_info(bp);
399
400 return 0;
401}
402
403static int bnx2_unregister_cnic(struct net_device *dev)
404{
405 struct bnx2 *bp = netdev_priv(dev);
406 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
407 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
408
c5a88950 409 mutex_lock(&bp->cnic_lock);
4edd473f
MC		 410 cp->drv_state = 0;
411 bnapi->cnic_present = 0;
412 rcu_assign_pointer(bp->cnic_ops, NULL);
c5a88950 413 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 414 synchronize_rcu();
415 return 0;
416}
417
418struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
419{
420 struct bnx2 *bp = netdev_priv(dev);
421 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
422
7625eb2f
MC		 423 if (!cp->max_iscsi_conn)
424 return NULL;
425
4edd473f
MC		 426 cp->drv_owner = THIS_MODULE;
427 cp->chip_id = bp->chip_id;
428 cp->pdev = bp->pdev;
429 cp->io_base = bp->regview;
430 cp->drv_ctl = bnx2_drv_ctl;
431 cp->drv_register_cnic = bnx2_register_cnic;
432 cp->drv_unregister_cnic = bnx2_unregister_cnic;
433
434 return cp;
435}
436EXPORT_SYMBOL(bnx2_cnic_probe);
437
438static void
439bnx2_cnic_stop(struct bnx2 *bp)
440{
441 struct cnic_ops *c_ops;
442 struct cnic_ctl_info info;
443
c5a88950 444 mutex_lock(&bp->cnic_lock);
13707f9e
ED		 445 c_ops = rcu_dereference_protected(bp->cnic_ops,
446 lockdep_is_held(&bp->cnic_lock));
4edd473f
MC		 447 if (c_ops) {
448 info.cmd = CNIC_CTL_STOP_CMD;
449 c_ops->cnic_ctl(bp->cnic_data, &info);
450 }
c5a88950 451 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 452}
453
454static void
455bnx2_cnic_start(struct bnx2 *bp)
456{
457 struct cnic_ops *c_ops;
458 struct cnic_ctl_info info;
459
c5a88950 460 mutex_lock(&bp->cnic_lock);
13707f9e
ED		 461 c_ops = rcu_dereference_protected(bp->cnic_ops,
462 lockdep_is_held(&bp->cnic_lock));
4edd473f
MC		 463 if (c_ops) {
464 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
465 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
466
467 bnapi->cnic_tag = bnapi->last_status_idx;
468 }
469 info.cmd = CNIC_CTL_START_CMD;
470 c_ops->cnic_ctl(bp->cnic_data, &info);
471 }
c5a88950 472 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 473}
474
475#else
476
477static void
478bnx2_cnic_stop(struct bnx2 *bp)
479{
480}
481
482static void
483bnx2_cnic_start(struct bnx2 *bp)
484{
485}
486
487#endif
488
b6016b76
MC		 489static int
490bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
491{
492 u32 val1;
493 int i, ret;
494
583c28e5 495 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 496 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
497 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
498
499 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
500 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
501
502 udelay(40);
503 }
504
505 val1 = (bp->phy_addr << 21) | (reg << 16) |
506 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
507 BNX2_EMAC_MDIO_COMM_START_BUSY;
508 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
509
510 for (i = 0; i < 50; i++) {
511 udelay(10);
512
513 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
514 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
515 udelay(5);
516
517 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
518 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
519
520 break;
521 }
522 }
523
524 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
525 *val = 0x0;
526 ret = -EBUSY;
527 }
528 else {
529 *val = val1;
530 ret = 0;
531 }
532
583c28e5 533 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 534 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
535 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
536
537 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
538 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
539
540 udelay(40);
541 }
542
543 return ret;
544}
545
546static int
547bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
548{
549 u32 val1;
550 int i, ret;
551
583c28e5 552 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 553 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
554 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
555
556 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
557 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
558
559 udelay(40);
560 }
561
562 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
563 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
564 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
565 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 566
b6016b76
MC		 567 for (i = 0; i < 50; i++) {
568 udelay(10);
569
570 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
571 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
572 udelay(5);
573 break;
574 }
575 }
576
577 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
578 ret = -EBUSY;
579 else
580 ret = 0;
581
583c28e5 582 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 583 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
584 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
585
586 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
587 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
588
589 udelay(40);
590 }
591
592 return ret;
593}
594
595static void
596bnx2_disable_int(struct bnx2 *bp)
597{
b4b36042
MC		 598 int i;
599 struct bnx2_napi *bnapi;
600
601 for (i = 0; i < bp->irq_nvecs; i++) {
602 bnapi = &bp->bnx2_napi[i];
603 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
604 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
605 }
b6016b76
MC		 606 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
607}
608
609static void
610bnx2_enable_int(struct bnx2 *bp)
611{
b4b36042
MC		 612 int i;
613 struct bnx2_napi *bnapi;
35efa7c1 614
b4b36042
MC		 615 for (i = 0; i < bp->irq_nvecs; i++) {
616 bnapi = &bp->bnx2_napi[i];
1269a8a6 617
b4b36042
MC		 618 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
619 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
620 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
621 bnapi->last_status_idx);
b6016b76 622
b4b36042
MC		 623 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
624 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
625 bnapi->last_status_idx);
626 }
bf5295bb 627 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 628}
629
630static void
631bnx2_disable_int_sync(struct bnx2 *bp)
632{
b4b36042
MC		 633 int i;
634
b6016b76 635 atomic_inc(&bp->intr_sem);
3767546c
MC		 636 if (!netif_running(bp->dev))
637 return;
638
b6016b76 639 bnx2_disable_int(bp);
b4b36042
MC		 640 for (i = 0; i < bp->irq_nvecs; i++)
641 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 642}
643
35efa7c1
MC		 644static void
645bnx2_napi_disable(struct bnx2 *bp)
646{
b4b36042
MC		 647 int i;
648
649 for (i = 0; i < bp->irq_nvecs; i++)
650 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 651}
652
653static void
654bnx2_napi_enable(struct bnx2 *bp)
655{
b4b36042
MC		 656 int i;
657
658 for (i = 0; i < bp->irq_nvecs; i++)
659 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 660}
661
b6016b76 662static void
212f9934 663bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
b6016b76 664{
212f9934
MC		 665 if (stop_cnic)
666 bnx2_cnic_stop(bp);
b6016b76 667 if (netif_running(bp->dev)) {
35efa7c1 668 bnx2_napi_disable(bp);
b6016b76 669 netif_tx_disable(bp->dev);
b6016b76 670 }
b7466560 671 bnx2_disable_int_sync(bp);
a0ba6760 672 netif_carrier_off(bp->dev); /* prevent tx timeout */
b6016b76
MC		 673}
674
675static void
212f9934 676bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
b6016b76
MC		 677{
678 if (atomic_dec_and_test(&bp->intr_sem)) {
679 if (netif_running(bp->dev)) {
706bf240 680 netif_tx_wake_all_queues(bp->dev);
a0ba6760
MC		 681 spin_lock_bh(&bp->phy_lock);
682 if (bp->link_up)
683 netif_carrier_on(bp->dev);
684 spin_unlock_bh(&bp->phy_lock);
35efa7c1 685 bnx2_napi_enable(bp);
b6016b76 686 bnx2_enable_int(bp);
212f9934
MC		 687 if (start_cnic)
688 bnx2_cnic_start(bp);
b6016b76
MC		 689 }
690 }
691}
692
35e9010b
MC		 693static void
694bnx2_free_tx_mem(struct bnx2 *bp)
695{
696 int i;
697
698 for (i = 0; i < bp->num_tx_rings; i++) {
699 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
700 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
701
702 if (txr->tx_desc_ring) {
36227e88
SG		 703 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
704 txr->tx_desc_ring,
705 txr->tx_desc_mapping);
35e9010b
MC		 706 txr->tx_desc_ring = NULL;
707 }
708 kfree(txr->tx_buf_ring);
709 txr->tx_buf_ring = NULL;
710 }
711}
712
bb4f98ab
MC		 713static void
714bnx2_free_rx_mem(struct bnx2 *bp)
715{
716 int i;
717
718 for (i = 0; i < bp->num_rx_rings; i++) {
719 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
720 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
721 int j;
722
723 for (j = 0; j < bp->rx_max_ring; j++) {
724 if (rxr->rx_desc_ring[j])
36227e88
SG		 725 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
726 rxr->rx_desc_ring[j],
727 rxr->rx_desc_mapping[j]);
bb4f98ab
MC		 728 rxr->rx_desc_ring[j] = NULL;
729 }
25b0b999 730 vfree(rxr->rx_buf_ring);
bb4f98ab
MC		 731 rxr->rx_buf_ring = NULL;
732
733 for (j = 0; j < bp->rx_max_pg_ring; j++) {
734 if (rxr->rx_pg_desc_ring[j])
36227e88
SG		 735 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
736 rxr->rx_pg_desc_ring[j],
737 rxr->rx_pg_desc_mapping[j]);
3298a738 738 rxr->rx_pg_desc_ring[j] = NULL;
bb4f98ab 739 }
25b0b999 740 vfree(rxr->rx_pg_ring);
bb4f98ab
MC		 741 rxr->rx_pg_ring = NULL;
742 }
743}
744
35e9010b
MC		 745static int
746bnx2_alloc_tx_mem(struct bnx2 *bp)
747{
748 int i;
749
750 for (i = 0; i < bp->num_tx_rings; i++) {
751 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
752 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
753
754 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
755 if (txr->tx_buf_ring == NULL)
756 return -ENOMEM;
757
758 txr->tx_desc_ring =
36227e88
SG		 759 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
760 &txr->tx_desc_mapping, GFP_KERNEL);
35e9010b
MC		 761 if (txr->tx_desc_ring == NULL)
762 return -ENOMEM;
763 }
764 return 0;
765}
766
bb4f98ab
MC		 767static int
768bnx2_alloc_rx_mem(struct bnx2 *bp)
769{
770 int i;
771
772 for (i = 0; i < bp->num_rx_rings; i++) {
773 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
774 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
775 int j;
776
777 rxr->rx_buf_ring =
89bf67f1 778 vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
bb4f98ab
MC		 779 if (rxr->rx_buf_ring == NULL)
780 return -ENOMEM;
781
bb4f98ab
MC		 782 for (j = 0; j < bp->rx_max_ring; j++) {
783 rxr->rx_desc_ring[j] =
36227e88
SG		 784 dma_alloc_coherent(&bp->pdev->dev,
785 RXBD_RING_SIZE,
786 &rxr->rx_desc_mapping[j],
787 GFP_KERNEL);
bb4f98ab
MC		 788 if (rxr->rx_desc_ring[j] == NULL)
789 return -ENOMEM;
790
791 }
792
793 if (bp->rx_pg_ring_size) {
89bf67f1 794 rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE *
bb4f98ab
MC		 795 bp->rx_max_pg_ring);
796 if (rxr->rx_pg_ring == NULL)
797 return -ENOMEM;
798
bb4f98ab
MC		 799 }
800
801 for (j = 0; j < bp->rx_max_pg_ring; j++) {
802 rxr->rx_pg_desc_ring[j] =
36227e88
SG		 803 dma_alloc_coherent(&bp->pdev->dev,
804 RXBD_RING_SIZE,
805 &rxr->rx_pg_desc_mapping[j],
806 GFP_KERNEL);
bb4f98ab
MC		 807 if (rxr->rx_pg_desc_ring[j] == NULL)
808 return -ENOMEM;
809
810 }
811 }
812 return 0;
813}
814
b6016b76
MC		 815static void
816bnx2_free_mem(struct bnx2 *bp)
817{
13daffa2 818 int i;
43e80b89 819 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
13daffa2 820
35e9010b 821 bnx2_free_tx_mem(bp);
bb4f98ab 822 bnx2_free_rx_mem(bp);
35e9010b 823
59b47d8a
MC		 824 for (i = 0; i < bp->ctx_pages; i++) {
825 if (bp->ctx_blk[i]) {
36227e88
SG		 826 dma_free_coherent(&bp->pdev->dev, BCM_PAGE_SIZE,
827 bp->ctx_blk[i],
828 bp->ctx_blk_mapping[i]);
59b47d8a
MC		 829 bp->ctx_blk[i] = NULL;
830 }
831 }
43e80b89 832 if (bnapi->status_blk.msi) {
36227e88
SG		 833 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
834 bnapi->status_blk.msi,
835 bp->status_blk_mapping);
43e80b89 836 bnapi->status_blk.msi = NULL;
0f31f994 837 bp->stats_blk = NULL;
b6016b76 838 }
b6016b76
MC		 839}
840
841static int
842bnx2_alloc_mem(struct bnx2 *bp)
843{
35e9010b 844 int i, status_blk_size, err;
43e80b89
MC		 845 struct bnx2_napi *bnapi;
846 void *status_blk;
b6016b76 847
0f31f994
MC		 848 /* Combine status and statistics blocks into one allocation. */
849 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 850 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 851 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
852 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 853 bp->status_stats_size = status_blk_size +
854 sizeof(struct statistics_block);
855
36227e88
SG		 856 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
857 &bp->status_blk_mapping, GFP_KERNEL);
43e80b89 858 if (status_blk == NULL)
b6016b76
MC		 859 goto alloc_mem_err;
860
43e80b89 861 memset(status_blk, 0, bp->status_stats_size);
b6016b76 862
43e80b89
MC		 863 bnapi = &bp->bnx2_napi[0];
864 bnapi->status_blk.msi = status_blk;
865 bnapi->hw_tx_cons_ptr =
866 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
867 bnapi->hw_rx_cons_ptr =
868 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
f86e82fb 869 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
379b39a2 870 for (i = 1; i < bp->irq_nvecs; i++) {
43e80b89
MC		 871 struct status_block_msix *sblk;
872
873 bnapi = &bp->bnx2_napi[i];
b4b36042 874
43e80b89
MC		 875 sblk = (void *) (status_blk +
876 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
877 bnapi->status_blk.msix = sblk;
878 bnapi->hw_tx_cons_ptr =
879 &sblk->status_tx_quick_consumer_index;
880 bnapi->hw_rx_cons_ptr =
881 &sblk->status_rx_quick_consumer_index;
b4b36042
MC		 882 bnapi->int_num = i << 24;
883 }
884 }
35efa7c1 885
43e80b89 886 bp->stats_blk = status_blk + status_blk_size;
b6016b76 887
0f31f994 888 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 889
59b47d8a
MC		 890 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
891 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
892 if (bp->ctx_pages == 0)
893 bp->ctx_pages = 1;
894 for (i = 0; i < bp->ctx_pages; i++) {
36227e88 895 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
59b47d8a 896 BCM_PAGE_SIZE,
36227e88
SG		 897 &bp->ctx_blk_mapping[i],
898 GFP_KERNEL);
59b47d8a
MC		 899 if (bp->ctx_blk[i] == NULL)
900 goto alloc_mem_err;
901 }
902 }
35e9010b 903
bb4f98ab
MC		 904 err = bnx2_alloc_rx_mem(bp);
905 if (err)
906 goto alloc_mem_err;
907
35e9010b
MC		 908 err = bnx2_alloc_tx_mem(bp);
909 if (err)
910 goto alloc_mem_err;
911
b6016b76
MC		 912 return 0;
913
914alloc_mem_err:
915 bnx2_free_mem(bp);
916 return -ENOMEM;
917}
918
e3648b3d
MC		 919static void
920bnx2_report_fw_link(struct bnx2 *bp)
921{
922 u32 fw_link_status = 0;
923
583c28e5 924 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 925 return;
926
e3648b3d
MC		 927 if (bp->link_up) {
928 u32 bmsr;
929
930 switch (bp->line_speed) {
931 case SPEED_10:
932 if (bp->duplex == DUPLEX_HALF)
933 fw_link_status = BNX2_LINK_STATUS_10HALF;
934 else
935 fw_link_status = BNX2_LINK_STATUS_10FULL;
936 break;
937 case SPEED_100:
938 if (bp->duplex == DUPLEX_HALF)
939 fw_link_status = BNX2_LINK_STATUS_100HALF;
940 else
941 fw_link_status = BNX2_LINK_STATUS_100FULL;
942 break;
943 case SPEED_1000:
944 if (bp->duplex == DUPLEX_HALF)
945 fw_link_status = BNX2_LINK_STATUS_1000HALF;
946 else
947 fw_link_status = BNX2_LINK_STATUS_1000FULL;
948 break;
949 case SPEED_2500:
950 if (bp->duplex == DUPLEX_HALF)
951 fw_link_status = BNX2_LINK_STATUS_2500HALF;
952 else
953 fw_link_status = BNX2_LINK_STATUS_2500FULL;
954 break;
955 }
956
957 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
958
959 if (bp->autoneg) {
960 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
961
ca58c3af
MC		 962 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
963 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 964
965 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 966 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 967 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
968 else
969 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
970 }
971 }
972 else
973 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
974
2726d6e1 975 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 976}
977
9b1084b8
MC		 978static char *
979bnx2_xceiver_str(struct bnx2 *bp)
980{
807540ba 981 return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 982 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
807540ba 983 "Copper");
9b1084b8
MC		 984}
985
b6016b76
MC		 986static void
987bnx2_report_link(struct bnx2 *bp)
988{
989 if (bp->link_up) {
990 netif_carrier_on(bp->dev);
3a9c6a49
JP		 991 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
992 bnx2_xceiver_str(bp),
993 bp->line_speed,
994 bp->duplex == DUPLEX_FULL ? "full" : "half");
b6016b76
MC		 995
996 if (bp->flow_ctrl) {
997 if (bp->flow_ctrl & FLOW_CTRL_RX) {
3a9c6a49 998 pr_cont(", receive ");
b6016b76 999 if (bp->flow_ctrl & FLOW_CTRL_TX)
3a9c6a49 1000 pr_cont("& transmit ");
b6016b76
MC		 1001 }
1002 else {
3a9c6a49 1003 pr_cont(", transmit ");
b6016b76 1004 }
3a9c6a49 1005 pr_cont("flow control ON");
b6016b76 1006 }
3a9c6a49
JP		 1007 pr_cont("\n");
1008 } else {
b6016b76 1009 netif_carrier_off(bp->dev);
3a9c6a49
JP		 1010 netdev_err(bp->dev, "NIC %s Link is Down\n",
1011 bnx2_xceiver_str(bp));
b6016b76 1012 }
e3648b3d
MC		 1013
1014 bnx2_report_fw_link(bp);
b6016b76
MC		 1015}
1016
1017static void
1018bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1019{
1020 u32 local_adv, remote_adv;
1021
1022 bp->flow_ctrl = 0;
6aa20a22 1023 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 1024 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1025
1026 if (bp->duplex == DUPLEX_FULL) {
1027 bp->flow_ctrl = bp->req_flow_ctrl;
1028 }
1029 return;
1030 }
1031
1032 if (bp->duplex != DUPLEX_FULL) {
1033 return;
1034 }
1035
583c28e5 1036 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 1037 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1038 u32 val;
1039
1040 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1041 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1042 bp->flow_ctrl |= FLOW_CTRL_TX;
1043 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1044 bp->flow_ctrl |= FLOW_CTRL_RX;
1045 return;
1046 }
1047
ca58c3af
MC		 1048 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1049 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 1050
583c28e5 1051 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1052 u32 new_local_adv = 0;
1053 u32 new_remote_adv = 0;
1054
1055 if (local_adv & ADVERTISE_1000XPAUSE)
1056 new_local_adv |= ADVERTISE_PAUSE_CAP;
1057 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1058 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1059 if (remote_adv & ADVERTISE_1000XPAUSE)
1060 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1061 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1062 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1063
1064 local_adv = new_local_adv;
1065 remote_adv = new_remote_adv;
1066 }
1067
1068 /* See Table 28B-3 of 802.3ab-1999 spec. */
1069 if (local_adv & ADVERTISE_PAUSE_CAP) {
1070 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1071 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1072 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1073 }
1074 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1075 bp->flow_ctrl = FLOW_CTRL_RX;
1076 }
1077 }
1078 else {
1079 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1080 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1081 }
1082 }
1083 }
1084 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1085 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1086 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1087
1088 bp->flow_ctrl = FLOW_CTRL_TX;
1089 }
1090 }
1091}
1092
27a005b8
MC		 1093static int
1094bnx2_5709s_linkup(struct bnx2 *bp)
1095{
1096 u32 val, speed;
1097
1098 bp->link_up = 1;
1099
1100 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1101 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1102 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1103
1104 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1105 bp->line_speed = bp->req_line_speed;
1106 bp->duplex = bp->req_duplex;
1107 return 0;
1108 }
1109 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1110 switch (speed) {
1111 case MII_BNX2_GP_TOP_AN_SPEED_10:
1112 bp->line_speed = SPEED_10;
1113 break;
1114 case MII_BNX2_GP_TOP_AN_SPEED_100:
1115 bp->line_speed = SPEED_100;
1116 break;
1117 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1118 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1119 bp->line_speed = SPEED_1000;
1120 break;
1121 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1122 bp->line_speed = SPEED_2500;
1123 break;
1124 }
1125 if (val & MII_BNX2_GP_TOP_AN_FD)
1126 bp->duplex = DUPLEX_FULL;
1127 else
1128 bp->duplex = DUPLEX_HALF;
1129 return 0;
1130}
1131
b6016b76 1132static int
5b0c76ad
MC		 1133bnx2_5708s_linkup(struct bnx2 *bp)
1134{
1135 u32 val;
1136
1137 bp->link_up = 1;
1138 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1139 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1140 case BCM5708S_1000X_STAT1_SPEED_10:
1141 bp->line_speed = SPEED_10;
1142 break;
1143 case BCM5708S_1000X_STAT1_SPEED_100:
1144 bp->line_speed = SPEED_100;
1145 break;
1146 case BCM5708S_1000X_STAT1_SPEED_1G:
1147 bp->line_speed = SPEED_1000;
1148 break;
1149 case BCM5708S_1000X_STAT1_SPEED_2G5:
1150 bp->line_speed = SPEED_2500;
1151 break;
1152 }
1153 if (val & BCM5708S_1000X_STAT1_FD)
1154 bp->duplex = DUPLEX_FULL;
1155 else
1156 bp->duplex = DUPLEX_HALF;
1157
1158 return 0;
1159}
1160
1161static int
1162bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 1163{
1164 u32 bmcr, local_adv, remote_adv, common;
1165
1166 bp->link_up = 1;
1167 bp->line_speed = SPEED_1000;
1168
ca58c3af 1169 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1170 if (bmcr & BMCR_FULLDPLX) {
1171 bp->duplex = DUPLEX_FULL;
1172 }
1173 else {
1174 bp->duplex = DUPLEX_HALF;
1175 }
1176
1177 if (!(bmcr & BMCR_ANENABLE)) {
1178 return 0;
1179 }
1180
ca58c3af
MC		 1181 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1182 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1183
1184 common = local_adv & remote_adv;
1185 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1186
1187 if (common & ADVERTISE_1000XFULL) {
1188 bp->duplex = DUPLEX_FULL;
1189 }
1190 else {
1191 bp->duplex = DUPLEX_HALF;
1192 }
1193 }
1194
1195 return 0;
1196}
1197
1198static int
1199bnx2_copper_linkup(struct bnx2 *bp)
1200{
1201 u32 bmcr;
1202
ca58c3af 1203 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1204 if (bmcr & BMCR_ANENABLE) {
1205 u32 local_adv, remote_adv, common;
1206
1207 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1208 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1209
1210 common = local_adv & (remote_adv >> 2);
1211 if (common & ADVERTISE_1000FULL) {
1212 bp->line_speed = SPEED_1000;
1213 bp->duplex = DUPLEX_FULL;
1214 }
1215 else if (common & ADVERTISE_1000HALF) {
1216 bp->line_speed = SPEED_1000;
1217 bp->duplex = DUPLEX_HALF;
1218 }
1219 else {
ca58c3af
MC		 1220 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1221 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1222
1223 common = local_adv & remote_adv;
1224 if (common & ADVERTISE_100FULL) {
1225 bp->line_speed = SPEED_100;
1226 bp->duplex = DUPLEX_FULL;
1227 }
1228 else if (common & ADVERTISE_100HALF) {
1229 bp->line_speed = SPEED_100;
1230 bp->duplex = DUPLEX_HALF;
1231 }
1232 else if (common & ADVERTISE_10FULL) {
1233 bp->line_speed = SPEED_10;
1234 bp->duplex = DUPLEX_FULL;
1235 }
1236 else if (common & ADVERTISE_10HALF) {
1237 bp->line_speed = SPEED_10;
1238 bp->duplex = DUPLEX_HALF;
1239 }
1240 else {
1241 bp->line_speed = 0;
1242 bp->link_up = 0;
1243 }
1244 }
1245 }
1246 else {
1247 if (bmcr & BMCR_SPEED100) {
1248 bp->line_speed = SPEED_100;
1249 }
1250 else {
1251 bp->line_speed = SPEED_10;
1252 }
1253 if (bmcr & BMCR_FULLDPLX) {
1254 bp->duplex = DUPLEX_FULL;
1255 }
1256 else {
1257 bp->duplex = DUPLEX_HALF;
1258 }
1259 }
1260
1261 return 0;
1262}
1263
83e3fc89 1264static void
bb4f98ab 1265bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
83e3fc89 1266{
bb4f98ab 1267 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
83e3fc89
MC		 1268
1269 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1270 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1271 val |= 0x02 << 8;
1272
22fa159d
MC		 1273 if (bp->flow_ctrl & FLOW_CTRL_TX)
1274 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
83e3fc89 1275
83e3fc89
MC		 1276 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1277}
1278
bb4f98ab
MC		 1279static void
1280bnx2_init_all_rx_contexts(struct bnx2 *bp)
1281{
1282 int i;
1283 u32 cid;
1284
1285 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1286 if (i == 1)
1287 cid = RX_RSS_CID;
1288 bnx2_init_rx_context(bp, cid);
1289 }
1290}
1291
344478db 1292static void
b6016b76
MC		 1293bnx2_set_mac_link(struct bnx2 *bp)
1294{
1295 u32 val;
1296
1297 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1298 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1299 (bp->duplex == DUPLEX_HALF)) {
1300 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1301 }
1302
1303 /* Configure the EMAC mode register. */
1304 val = REG_RD(bp, BNX2_EMAC_MODE);
1305
1306 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1307 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1308 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1309
1310 if (bp->link_up) {
5b0c76ad
MC		 1311 switch (bp->line_speed) {
1312 case SPEED_10:
59b47d8a
MC		 1313 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1314 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1315 break;
1316 }
1317 /* fall through */
1318 case SPEED_100:
1319 val |= BNX2_EMAC_MODE_PORT_MII;
1320 break;
1321 case SPEED_2500:
59b47d8a 1322 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1323 /* fall through */
1324 case SPEED_1000:
1325 val |= BNX2_EMAC_MODE_PORT_GMII;
1326 break;
1327 }
b6016b76
MC		 1328 }
1329 else {
1330 val |= BNX2_EMAC_MODE_PORT_GMII;
1331 }
1332
1333 /* Set the MAC to operate in the appropriate duplex mode. */
1334 if (bp->duplex == DUPLEX_HALF)
1335 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1336 REG_WR(bp, BNX2_EMAC_MODE, val);
1337
1338 /* Enable/disable rx PAUSE. */
1339 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1340
1341 if (bp->flow_ctrl & FLOW_CTRL_RX)
1342 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1343 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1344
1345 /* Enable/disable tx PAUSE. */
1346 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1347 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1348
1349 if (bp->flow_ctrl & FLOW_CTRL_TX)
1350 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1351 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1352
1353 /* Acknowledge the interrupt. */
1354 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1355
22fa159d 1356 bnx2_init_all_rx_contexts(bp);
b6016b76
MC		 1357}
1358
27a005b8
MC		 1359static void
1360bnx2_enable_bmsr1(struct bnx2 *bp)
1361{
583c28e5 1362 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1363 (CHIP_NUM(bp) == CHIP_NUM_5709))
1364 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1365 MII_BNX2_BLK_ADDR_GP_STATUS);
1366}
1367
1368static void
1369bnx2_disable_bmsr1(struct bnx2 *bp)
1370{
583c28e5 1371 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1372 (CHIP_NUM(bp) == CHIP_NUM_5709))
1373 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1374 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1375}
1376
605a9e20
MC		 1377static int
1378bnx2_test_and_enable_2g5(struct bnx2 *bp)
1379{
1380 u32 up1;
1381 int ret = 1;
1382
583c28e5 1383 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1384 return 0;
1385
1386 if (bp->autoneg & AUTONEG_SPEED)
1387 bp->advertising |= ADVERTISED_2500baseX_Full;
1388
27a005b8
MC		 1389 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1390 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1391
605a9e20
MC		 1392 bnx2_read_phy(bp, bp->mii_up1, &up1);
1393 if (!(up1 & BCM5708S_UP1_2G5)) {
1394 up1 |= BCM5708S_UP1_2G5;
1395 bnx2_write_phy(bp, bp->mii_up1, up1);
1396 ret = 0;
1397 }
1398
27a005b8
MC		 1399 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1400 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1401 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1402
605a9e20
MC		 1403 return ret;
1404}
1405
1406static int
1407bnx2_test_and_disable_2g5(struct bnx2 *bp)
1408{
1409 u32 up1;
1410 int ret = 0;
1411
583c28e5 1412 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1413 return 0;
1414
27a005b8
MC		 1415 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1416 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1417
605a9e20
MC		 1418 bnx2_read_phy(bp, bp->mii_up1, &up1);
1419 if (up1 & BCM5708S_UP1_2G5) {
1420 up1 &= ~BCM5708S_UP1_2G5;
1421 bnx2_write_phy(bp, bp->mii_up1, up1);
1422 ret = 1;
1423 }
1424
27a005b8
MC		 1425 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1426 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1427 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1428
605a9e20
MC		 1429 return ret;
1430}
1431
1432static void
1433bnx2_enable_forced_2g5(struct bnx2 *bp)
1434{
cbd6890c
MC		 1435 u32 uninitialized_var(bmcr);
1436 int err;
605a9e20 1437
583c28e5 1438 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1439 return;
1440
27a005b8
MC		 1441 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1442 u32 val;
1443
1444 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1445 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1446 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1447 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1448 val |= MII_BNX2_SD_MISC1_FORCE |
1449 MII_BNX2_SD_MISC1_FORCE_2_5G;
1450 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1451 }
27a005b8
MC		 1452
1453 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1454 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1455 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1456
1457 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1458 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1459 if (!err)
1460 bmcr |= BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1461 } else {
1462 return;
605a9e20
MC		 1463 }
1464
cbd6890c
MC		 1465 if (err)
1466 return;
1467
605a9e20
MC		 1468 if (bp->autoneg & AUTONEG_SPEED) {
1469 bmcr &= ~BMCR_ANENABLE;
1470 if (bp->req_duplex == DUPLEX_FULL)
1471 bmcr |= BMCR_FULLDPLX;
1472 }
1473 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1474}
1475
1476static void
1477bnx2_disable_forced_2g5(struct bnx2 *bp)
1478{
cbd6890c
MC		 1479 u32 uninitialized_var(bmcr);
1480 int err;
605a9e20 1481
583c28e5 1482 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1483 return;
1484
27a005b8
MC		 1485 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1486 u32 val;
1487
1488 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1489 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1490 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1491 val &= ~MII_BNX2_SD_MISC1_FORCE;
1492 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1493 }
27a005b8
MC		 1494
1495 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1496 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1497 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1498
1499 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1500 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1501 if (!err)
1502 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1503 } else {
1504 return;
605a9e20
MC		 1505 }
1506
cbd6890c
MC		 1507 if (err)
1508 return;
1509
605a9e20
MC		 1510 if (bp->autoneg & AUTONEG_SPEED)
1511 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1512 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1513}
1514
b2fadeae
MC		 1515static void
1516bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1517{
1518 u32 val;
1519
1520 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1521 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1522 if (start)
1523 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1524 else
1525 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1526}
1527
b6016b76
MC		 1528static int
1529bnx2_set_link(struct bnx2 *bp)
1530{
1531 u32 bmsr;
1532 u8 link_up;
1533
80be4434 1534 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1535 bp->link_up = 1;
1536 return 0;
1537 }
1538
583c28e5 1539 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1540 return 0;
1541
b6016b76
MC		 1542 link_up = bp->link_up;
1543
27a005b8
MC		 1544 bnx2_enable_bmsr1(bp);
1545 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1546 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1547 bnx2_disable_bmsr1(bp);
b6016b76 1548
583c28e5 1549 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1550 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1551 u32 val, an_dbg;
b6016b76 1552
583c28e5 1553 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1554 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1555 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1556 }
b6016b76 1557 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1558
1559 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1560 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1561 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1562
1563 if ((val & BNX2_EMAC_STATUS_LINK) &&
1564 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1565 bmsr |= BMSR_LSTATUS;
1566 else
1567 bmsr &= ~BMSR_LSTATUS;
1568 }
1569
1570 if (bmsr & BMSR_LSTATUS) {
1571 bp->link_up = 1;
1572
583c28e5 1573 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1574 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1575 bnx2_5706s_linkup(bp);
1576 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1577 bnx2_5708s_linkup(bp);
27a005b8
MC		 1578 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1579 bnx2_5709s_linkup(bp);
b6016b76
MC		 1580 }
1581 else {
1582 bnx2_copper_linkup(bp);
1583 }
1584 bnx2_resolve_flow_ctrl(bp);
1585 }
1586 else {
583c28e5 1587 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1588 (bp->autoneg & AUTONEG_SPEED))
1589 bnx2_disable_forced_2g5(bp);
b6016b76 1590
583c28e5 1591 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1592 u32 bmcr;
1593
1594 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1595 bmcr |= BMCR_ANENABLE;
1596 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1597
583c28e5 1598 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1599 }
b6016b76
MC		 1600 bp->link_up = 0;
1601 }
1602
1603 if (bp->link_up != link_up) {
1604 bnx2_report_link(bp);
1605 }
1606
1607 bnx2_set_mac_link(bp);
1608
1609 return 0;
1610}
1611
1612static int
1613bnx2_reset_phy(struct bnx2 *bp)
1614{
1615 int i;
1616 u32 reg;
1617
ca58c3af 1618 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1619
1620#define PHY_RESET_MAX_WAIT 100
1621 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1622 udelay(10);
1623
ca58c3af 1624 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1625 if (!(reg & BMCR_RESET)) {
1626 udelay(20);
1627 break;
1628 }
1629 }
1630 if (i == PHY_RESET_MAX_WAIT) {
1631 return -EBUSY;
1632 }
1633 return 0;
1634}
1635
1636static u32
1637bnx2_phy_get_pause_adv(struct bnx2 *bp)
1638{
1639 u32 adv = 0;
1640
1641 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1642 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1643
583c28e5 1644 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1645 adv = ADVERTISE_1000XPAUSE;
1646 }
1647 else {
1648 adv = ADVERTISE_PAUSE_CAP;
1649 }
1650 }
1651 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1652 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1653 adv = ADVERTISE_1000XPSE_ASYM;
1654 }
1655 else {
1656 adv = ADVERTISE_PAUSE_ASYM;
1657 }
1658 }
1659 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1660 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1661 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1662 }
1663 else {
1664 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1665 }
1666 }
1667 return adv;
1668}
1669
a2f13890 1670static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
0d8a6571 1671
b6016b76 1672static int
0d8a6571 1673bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1674__releases(&bp->phy_lock)
1675__acquires(&bp->phy_lock)
0d8a6571
MC		 1676{
1677 u32 speed_arg = 0, pause_adv;
1678
1679 pause_adv = bnx2_phy_get_pause_adv(bp);
1680
1681 if (bp->autoneg & AUTONEG_SPEED) {
1682 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1683 if (bp->advertising & ADVERTISED_10baseT_Half)
1684 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1685 if (bp->advertising & ADVERTISED_10baseT_Full)
1686 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1687 if (bp->advertising & ADVERTISED_100baseT_Half)
1688 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1689 if (bp->advertising & ADVERTISED_100baseT_Full)
1690 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1691 if (bp->advertising & ADVERTISED_1000baseT_Full)
1692 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1693 if (bp->advertising & ADVERTISED_2500baseX_Full)
1694 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1695 } else {
1696 if (bp->req_line_speed == SPEED_2500)
1697 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1698 else if (bp->req_line_speed == SPEED_1000)
1699 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1700 else if (bp->req_line_speed == SPEED_100) {
1701 if (bp->req_duplex == DUPLEX_FULL)
1702 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1703 else
1704 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1705 } else if (bp->req_line_speed == SPEED_10) {
1706 if (bp->req_duplex == DUPLEX_FULL)
1707 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1708 else
1709 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1710 }
1711 }
1712
1713 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1714 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1715 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1716 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1717
1718 if (port == PORT_TP)
1719 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1720 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1721
2726d6e1 1722 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1723
1724 spin_unlock_bh(&bp->phy_lock);
a2f13890 1725 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
0d8a6571
MC		 1726 spin_lock_bh(&bp->phy_lock);
1727
1728 return 0;
1729}
1730
1731static int
1732bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1733__releases(&bp->phy_lock)
1734__acquires(&bp->phy_lock)
b6016b76 1735{
605a9e20 1736 u32 adv, bmcr;
b6016b76
MC		 1737 u32 new_adv = 0;
1738
583c28e5 1739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
807540ba 1740 return bnx2_setup_remote_phy(bp, port);
0d8a6571 1741
b6016b76
MC		 1742 if (!(bp->autoneg & AUTONEG_SPEED)) {
1743 u32 new_bmcr;
5b0c76ad
MC		 1744 int force_link_down = 0;
1745
605a9e20
MC		 1746 if (bp->req_line_speed == SPEED_2500) {
1747 if (!bnx2_test_and_enable_2g5(bp))
1748 force_link_down = 1;
1749 } else if (bp->req_line_speed == SPEED_1000) {
1750 if (bnx2_test_and_disable_2g5(bp))
1751 force_link_down = 1;
1752 }
ca58c3af 1753 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1754 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1755
ca58c3af 1756 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1757 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1758 new_bmcr |= BMCR_SPEED1000;
605a9e20 1759
27a005b8
MC		 1760 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1761 if (bp->req_line_speed == SPEED_2500)
1762 bnx2_enable_forced_2g5(bp);
1763 else if (bp->req_line_speed == SPEED_1000) {
1764 bnx2_disable_forced_2g5(bp);
1765 new_bmcr &= ~0x2000;
1766 }
1767
1768 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1769 if (bp->req_line_speed == SPEED_2500)
1770 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1771 else
1772 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1773 }
1774
b6016b76 1775 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1776 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1777 new_bmcr |= BMCR_FULLDPLX;
1778 }
1779 else {
5b0c76ad 1780 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1781 new_bmcr &= ~BMCR_FULLDPLX;
1782 }
5b0c76ad 1783 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1784 /* Force a link down visible on the other side */
1785 if (bp->link_up) {
ca58c3af 1786 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1787 ~(ADVERTISE_1000XFULL |
1788 ADVERTISE_1000XHALF));
ca58c3af 1789 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1790 BMCR_ANRESTART | BMCR_ANENABLE);
1791
1792 bp->link_up = 0;
1793 netif_carrier_off(bp->dev);
ca58c3af 1794 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1795 bnx2_report_link(bp);
b6016b76 1796 }
ca58c3af
MC		 1797 bnx2_write_phy(bp, bp->mii_adv, adv);
1798 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1799 } else {
1800 bnx2_resolve_flow_ctrl(bp);
1801 bnx2_set_mac_link(bp);
b6016b76
MC		 1802 }
1803 return 0;
1804 }
1805
605a9e20 1806 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1807
b6016b76
MC		 1808 if (bp->advertising & ADVERTISED_1000baseT_Full)
1809 new_adv |= ADVERTISE_1000XFULL;
1810
1811 new_adv |= bnx2_phy_get_pause_adv(bp);
1812
ca58c3af
MC		 1813 bnx2_read_phy(bp, bp->mii_adv, &adv);
1814 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1815
1816 bp->serdes_an_pending = 0;
1817 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1818 /* Force a link down visible on the other side */
1819 if (bp->link_up) {
ca58c3af 1820 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1821 spin_unlock_bh(&bp->phy_lock);
1822 msleep(20);
1823 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1824 }
1825
ca58c3af
MC		 1826 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1827 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1828 BMCR_ANENABLE);
f8dd064e
MC		 1829 /* Speed up link-up time when the link partner
1830 * does not autonegotiate which is very common
1831 * in blade servers. Some blade servers use
1832 * IPMI for kerboard input and it's important
1833 * to minimize link disruptions. Autoneg. involves
1834 * exchanging base pages plus 3 next pages and
1835 * normally completes in about 120 msec.
1836 */
40105c0b 1837 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 1838 bp->serdes_an_pending = 1;
1839 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1840 } else {
1841 bnx2_resolve_flow_ctrl(bp);
1842 bnx2_set_mac_link(bp);
b6016b76
MC		 1843 }
1844
1845 return 0;
1846}
1847
1848#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1849 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1850 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1851 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1852
1853#define ETHTOOL_ALL_COPPER_SPEED \
1854 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1855 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1856 ADVERTISED_1000baseT_Full)
1857
1858#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1859 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1860
b6016b76
MC		 1861#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1862
0d8a6571
MC		 1863static void
1864bnx2_set_default_remote_link(struct bnx2 *bp)
1865{
1866 u32 link;
1867
1868 if (bp->phy_port == PORT_TP)
2726d6e1 1869 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1870 else
2726d6e1 1871 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1872
1873 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1874 bp->req_line_speed = 0;
1875 bp->autoneg |= AUTONEG_SPEED;
1876 bp->advertising = ADVERTISED_Autoneg;
1877 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1878 bp->advertising |= ADVERTISED_10baseT_Half;
1879 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1880 bp->advertising |= ADVERTISED_10baseT_Full;
1881 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1882 bp->advertising |= ADVERTISED_100baseT_Half;
1883 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1884 bp->advertising |= ADVERTISED_100baseT_Full;
1885 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1886 bp->advertising |= ADVERTISED_1000baseT_Full;
1887 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1888 bp->advertising |= ADVERTISED_2500baseX_Full;
1889 } else {
1890 bp->autoneg = 0;
1891 bp->advertising = 0;
1892 bp->req_duplex = DUPLEX_FULL;
1893 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1894 bp->req_line_speed = SPEED_10;
1895 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1896 bp->req_duplex = DUPLEX_HALF;
1897 }
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1899 bp->req_line_speed = SPEED_100;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1901 bp->req_duplex = DUPLEX_HALF;
1902 }
1903 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1904 bp->req_line_speed = SPEED_1000;
1905 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1906 bp->req_line_speed = SPEED_2500;
1907 }
1908}
1909
deaf391b
MC		 1910static void
1911bnx2_set_default_link(struct bnx2 *bp)
1912{
ab59859d
HH		 1913 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1914 bnx2_set_default_remote_link(bp);
1915 return;
1916 }
0d8a6571 1917
deaf391b
MC		 1918 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1919 bp->req_line_speed = 0;
583c28e5 1920 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1921 u32 reg;
1922
1923 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1924
2726d6e1 1925 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1926 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1927 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1928 bp->autoneg = 0;
1929 bp->req_line_speed = bp->line_speed = SPEED_1000;
1930 bp->req_duplex = DUPLEX_FULL;
1931 }
1932 } else
1933 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1934}
1935
df149d70
MC		 1936static void
1937bnx2_send_heart_beat(struct bnx2 *bp)
1938{
1939 u32 msg;
1940 u32 addr;
1941
1942 spin_lock(&bp->indirect_lock);
1943 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1944 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1945 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1946 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1947 spin_unlock(&bp->indirect_lock);
1948}
1949
0d8a6571
MC		 1950static void
1951bnx2_remote_phy_event(struct bnx2 *bp)
1952{
1953 u32 msg;
1954 u8 link_up = bp->link_up;
1955 u8 old_port;
1956
2726d6e1 1957 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1958
df149d70
MC		 1959 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1960 bnx2_send_heart_beat(bp);
1961
1962 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1963
0d8a6571
MC		 1964 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1965 bp->link_up = 0;
1966 else {
1967 u32 speed;
1968
1969 bp->link_up = 1;
1970 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1971 bp->duplex = DUPLEX_FULL;
1972 switch (speed) {
1973 case BNX2_LINK_STATUS_10HALF:
1974 bp->duplex = DUPLEX_HALF;
1975 case BNX2_LINK_STATUS_10FULL:
1976 bp->line_speed = SPEED_10;
1977 break;
1978 case BNX2_LINK_STATUS_100HALF:
1979 bp->duplex = DUPLEX_HALF;
1980 case BNX2_LINK_STATUS_100BASE_T4:
1981 case BNX2_LINK_STATUS_100FULL:
1982 bp->line_speed = SPEED_100;
1983 break;
1984 case BNX2_LINK_STATUS_1000HALF:
1985 bp->duplex = DUPLEX_HALF;
1986 case BNX2_LINK_STATUS_1000FULL:
1987 bp->line_speed = SPEED_1000;
1988 break;
1989 case BNX2_LINK_STATUS_2500HALF:
1990 bp->duplex = DUPLEX_HALF;
1991 case BNX2_LINK_STATUS_2500FULL:
1992 bp->line_speed = SPEED_2500;
1993 break;
1994 default:
1995 bp->line_speed = 0;
1996 break;
1997 }
1998
0d8a6571
MC		 1999 bp->flow_ctrl = 0;
2000 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2001 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2002 if (bp->duplex == DUPLEX_FULL)
2003 bp->flow_ctrl = bp->req_flow_ctrl;
2004 } else {
2005 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2006 bp->flow_ctrl |= FLOW_CTRL_TX;
2007 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2008 bp->flow_ctrl |= FLOW_CTRL_RX;
2009 }
2010
2011 old_port = bp->phy_port;
2012 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2013 bp->phy_port = PORT_FIBRE;
2014 else
2015 bp->phy_port = PORT_TP;
2016
2017 if (old_port != bp->phy_port)
2018 bnx2_set_default_link(bp);
2019
0d8a6571
MC		 2020 }
2021 if (bp->link_up != link_up)
2022 bnx2_report_link(bp);
2023
2024 bnx2_set_mac_link(bp);
2025}
2026
2027static int
2028bnx2_set_remote_link(struct bnx2 *bp)
2029{
2030 u32 evt_code;
2031
2726d6e1 2032 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 2033 switch (evt_code) {
2034 case BNX2_FW_EVT_CODE_LINK_EVENT:
2035 bnx2_remote_phy_event(bp);
2036 break;
2037 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2038 default:
df149d70 2039 bnx2_send_heart_beat(bp);
0d8a6571
MC		 2040 break;
2041 }
2042 return 0;
2043}
2044
b6016b76
MC		 2045static int
2046bnx2_setup_copper_phy(struct bnx2 *bp)
52d07b1f
HH		 2047__releases(&bp->phy_lock)
2048__acquires(&bp->phy_lock)
b6016b76
MC		 2049{
2050 u32 bmcr;
2051 u32 new_bmcr;
2052
ca58c3af 2053 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 2054
2055 if (bp->autoneg & AUTONEG_SPEED) {
2056 u32 adv_reg, adv1000_reg;
37f07023
MC		 2057 u32 new_adv = 0;
2058 u32 new_adv1000 = 0;
b6016b76 2059
ca58c3af 2060 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 2061 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2062 ADVERTISE_PAUSE_ASYM);
2063
2064 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2065 adv1000_reg &= PHY_ALL_1000_SPEED;
2066
37f07023
MC		 2067 new_adv = ethtool_adv_to_mii_adv_t(bp->advertising);
2068 new_adv |= ADVERTISE_CSMA;
2069 new_adv |= bnx2_phy_get_pause_adv(bp);
b6016b76 2070
37f07023 2071 new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);
28011cf1 2072
37f07023
MC		 2073 if ((adv1000_reg != new_adv1000) ||
2074 (adv_reg != new_adv) ||
b6016b76
MC		 2075 ((bmcr & BMCR_ANENABLE) == 0)) {
2076
37f07023
MC		 2077 bnx2_write_phy(bp, bp->mii_adv, new_adv);
2078 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);
ca58c3af 2079 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 2080 BMCR_ANENABLE);
2081 }
2082 else if (bp->link_up) {
2083 /* Flow ctrl may have changed from auto to forced */
2084 /* or vice-versa. */
2085
2086 bnx2_resolve_flow_ctrl(bp);
2087 bnx2_set_mac_link(bp);
2088 }
2089 return 0;
2090 }
2091
2092 new_bmcr = 0;
2093 if (bp->req_line_speed == SPEED_100) {
2094 new_bmcr |= BMCR_SPEED100;
2095 }
2096 if (bp->req_duplex == DUPLEX_FULL) {
2097 new_bmcr |= BMCR_FULLDPLX;
2098 }
2099 if (new_bmcr != bmcr) {
2100 u32 bmsr;
b6016b76 2101
ca58c3af
MC		 2102 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2103 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 2104
b6016b76
MC		 2105 if (bmsr & BMSR_LSTATUS) {
2106 /* Force link down */
ca58c3af 2107 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 2108 spin_unlock_bh(&bp->phy_lock);
2109 msleep(50);
2110 spin_lock_bh(&bp->phy_lock);
2111
ca58c3af
MC		 2112 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2113 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 2114 }
2115
ca58c3af 2116 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 2117
2118 /* Normally, the new speed is setup after the link has
2119 * gone down and up again. In some cases, link will not go
2120 * down so we need to set up the new speed here.
2121 */
2122 if (bmsr & BMSR_LSTATUS) {
2123 bp->line_speed = bp->req_line_speed;
2124 bp->duplex = bp->req_duplex;
2125 bnx2_resolve_flow_ctrl(bp);
2126 bnx2_set_mac_link(bp);
2127 }
27a005b8
MC		 2128 } else {
2129 bnx2_resolve_flow_ctrl(bp);
2130 bnx2_set_mac_link(bp);
b6016b76
MC		 2131 }
2132 return 0;
2133}
2134
2135static int
0d8a6571 2136bnx2_setup_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 2137__releases(&bp->phy_lock)
2138__acquires(&bp->phy_lock)
b6016b76
MC		 2139{
2140 if (bp->loopback == MAC_LOOPBACK)
2141 return 0;
2142
583c28e5 2143 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
807540ba 2144 return bnx2_setup_serdes_phy(bp, port);
b6016b76
MC		 2145 }
2146 else {
807540ba 2147 return bnx2_setup_copper_phy(bp);
b6016b76
MC		 2148 }
2149}
2150
27a005b8 2151static int
9a120bc5 2152bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 2153{
2154 u32 val;
2155
2156 bp->mii_bmcr = MII_BMCR + 0x10;
2157 bp->mii_bmsr = MII_BMSR + 0x10;
2158 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2159 bp->mii_adv = MII_ADVERTISE + 0x10;
2160 bp->mii_lpa = MII_LPA + 0x10;
2161 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2162
2163 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2164 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2165
2166 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 2167 if (reset_phy)
2168 bnx2_reset_phy(bp);
27a005b8
MC		 2169
2170 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2171
2172 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2173 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2174 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2175 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2176
2177 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2178 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 2179 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 2180 val |= BCM5708S_UP1_2G5;
2181 else
2182 val &= ~BCM5708S_UP1_2G5;
2183 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2184
2185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2186 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2187 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2188 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2189
2190 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2191
2192 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2193 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2194 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2195
2196 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2197
2198 return 0;
2199}
2200
b6016b76 2201static int
9a120bc5 2202bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 2203{
2204 u32 val;
2205
9a120bc5
MC		 2206 if (reset_phy)
2207 bnx2_reset_phy(bp);
27a005b8
MC		 2208
2209 bp->mii_up1 = BCM5708S_UP1;
2210
5b0c76ad
MC		 2211 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2212 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2213 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2214
2215 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2216 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2217 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2218
2219 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2220 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2221 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2222
583c28e5 2223 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 2224 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2225 val |= BCM5708S_UP1_2G5;
2226 bnx2_write_phy(bp, BCM5708S_UP1, val);
2227 }
2228
2229 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 2230 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2231 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 2232 /* increase tx signal amplitude */
2233 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2234 BCM5708S_BLK_ADDR_TX_MISC);
2235 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2236 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2237 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2238 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2239 }
2240
2726d6e1 2241 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 2242 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2243
2244 if (val) {
2245 u32 is_backplane;
2246
2726d6e1 2247 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 2248 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2249 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2250 BCM5708S_BLK_ADDR_TX_MISC);
2251 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2252 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2253 BCM5708S_BLK_ADDR_DIG);
2254 }
2255 }
2256 return 0;
2257}
2258
2259static int
9a120bc5 2260bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2261{
9a120bc5
MC		 2262 if (reset_phy)
2263 bnx2_reset_phy(bp);
27a005b8 2264
583c28e5 2265 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 2266
59b47d8a
MC		 2267 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2268 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 2269
2270 if (bp->dev->mtu > 1500) {
2271 u32 val;
2272
2273 /* Set extended packet length bit */
2274 bnx2_write_phy(bp, 0x18, 0x7);
2275 bnx2_read_phy(bp, 0x18, &val);
2276 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2277
2278 bnx2_write_phy(bp, 0x1c, 0x6c00);
2279 bnx2_read_phy(bp, 0x1c, &val);
2280 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2281 }
2282 else {
2283 u32 val;
2284
2285 bnx2_write_phy(bp, 0x18, 0x7);
2286 bnx2_read_phy(bp, 0x18, &val);
2287 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2288
2289 bnx2_write_phy(bp, 0x1c, 0x6c00);
2290 bnx2_read_phy(bp, 0x1c, &val);
2291 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2292 }
2293
2294 return 0;
2295}
2296
2297static int
9a120bc5 2298bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2299{
5b0c76ad
MC		 2300 u32 val;
2301
9a120bc5
MC		 2302 if (reset_phy)
2303 bnx2_reset_phy(bp);
27a005b8 2304
583c28e5 2305 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2306 bnx2_write_phy(bp, 0x18, 0x0c00);
2307 bnx2_write_phy(bp, 0x17, 0x000a);
2308 bnx2_write_phy(bp, 0x15, 0x310b);
2309 bnx2_write_phy(bp, 0x17, 0x201f);
2310 bnx2_write_phy(bp, 0x15, 0x9506);
2311 bnx2_write_phy(bp, 0x17, 0x401f);
2312 bnx2_write_phy(bp, 0x15, 0x14e2);
2313 bnx2_write_phy(bp, 0x18, 0x0400);
2314 }
2315
583c28e5 2316 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2317 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2318 MII_BNX2_DSP_EXPAND_REG | 0x8);
2319 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2320 val &= ~(1 << 8);
2321 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2322 }
2323
b6016b76 2324 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2325 /* Set extended packet length bit */
2326 bnx2_write_phy(bp, 0x18, 0x7);
2327 bnx2_read_phy(bp, 0x18, &val);
2328 bnx2_write_phy(bp, 0x18, val | 0x4000);
2329
2330 bnx2_read_phy(bp, 0x10, &val);
2331 bnx2_write_phy(bp, 0x10, val | 0x1);
2332 }
2333 else {
b6016b76
MC		 2334 bnx2_write_phy(bp, 0x18, 0x7);
2335 bnx2_read_phy(bp, 0x18, &val);
2336 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2337
2338 bnx2_read_phy(bp, 0x10, &val);
2339 bnx2_write_phy(bp, 0x10, val & ~0x1);
2340 }
2341
5b0c76ad
MC		 2342 /* ethernet@wirespeed */
2343 bnx2_write_phy(bp, 0x18, 0x7007);
2344 bnx2_read_phy(bp, 0x18, &val);
2345 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2346 return 0;
2347}
2348
2349
2350static int
9a120bc5 2351bnx2_init_phy(struct bnx2 *bp, int reset_phy)
52d07b1f
HH		 2352__releases(&bp->phy_lock)
2353__acquires(&bp->phy_lock)
b6016b76
MC		 2354{
2355 u32 val;
2356 int rc = 0;
2357
583c28e5
MC		 2358 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2359 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2360
ca58c3af
MC		 2361 bp->mii_bmcr = MII_BMCR;
2362 bp->mii_bmsr = MII_BMSR;
27a005b8 2363 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2364 bp->mii_adv = MII_ADVERTISE;
2365 bp->mii_lpa = MII_LPA;
2366
b6016b76
MC		 2367 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2368
583c28e5 2369 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2370 goto setup_phy;
2371
b6016b76
MC		 2372 bnx2_read_phy(bp, MII_PHYSID1, &val);
2373 bp->phy_id = val << 16;
2374 bnx2_read_phy(bp, MII_PHYSID2, &val);
2375 bp->phy_id |= val & 0xffff;
2376
583c28e5 2377 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad 2378 if (CHIP_NUM(bp) == CHIP_NUM_5706)
9a120bc5 2379 rc = bnx2_init_5706s_phy(bp, reset_phy);
5b0c76ad 2380 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
9a120bc5 2381 rc = bnx2_init_5708s_phy(bp, reset_phy);
27a005b8 2382 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
9a120bc5 2383 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2384 }
2385 else {
9a120bc5 2386 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2387 }
2388
0d8a6571
MC		 2389setup_phy:
2390 if (!rc)
2391 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2392
2393 return rc;
2394}
2395
2396static int
2397bnx2_set_mac_loopback(struct bnx2 *bp)
2398{
2399 u32 mac_mode;
2400
2401 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2402 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2403 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2404 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2405 bp->link_up = 1;
2406 return 0;
2407}
2408
bc5a0690
MC		 2409static int bnx2_test_link(struct bnx2 *);
2410
2411static int
2412bnx2_set_phy_loopback(struct bnx2 *bp)
2413{
2414 u32 mac_mode;
2415 int rc, i;
2416
2417 spin_lock_bh(&bp->phy_lock);
ca58c3af 2418 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2419 BMCR_SPEED1000);
2420 spin_unlock_bh(&bp->phy_lock);
2421 if (rc)
2422 return rc;
2423
2424 for (i = 0; i < 10; i++) {
2425 if (bnx2_test_link(bp) == 0)
2426 break;
80be4434 2427 msleep(100);
bc5a0690
MC		 2428 }
2429
2430 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2431 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2432 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2433 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2434
2435 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2436 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2437 bp->link_up = 1;
2438 return 0;
2439}
2440
ecdbf6e0
JH		 2441static void
2442bnx2_dump_mcp_state(struct bnx2 *bp)
2443{
2444 struct net_device *dev = bp->dev;
2445 u32 mcp_p0, mcp_p1;
2446
2447 netdev_err(dev, "<--- start MCP states dump --->\n");
2448 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
2449 mcp_p0 = BNX2_MCP_STATE_P0;
2450 mcp_p1 = BNX2_MCP_STATE_P1;
2451 } else {
2452 mcp_p0 = BNX2_MCP_STATE_P0_5708;
2453 mcp_p1 = BNX2_MCP_STATE_P1_5708;
2454 }
2455 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
2456 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
2457 netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n",
2458 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),
2459 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),
2460 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));
2461 netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n",
2462 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2463 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2464 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));
2465 netdev_err(dev, "DEBUG: shmem states:\n");
2466 netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]",
2467 bnx2_shmem_rd(bp, BNX2_DRV_MB),
2468 bnx2_shmem_rd(bp, BNX2_FW_MB),
2469 bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
2470 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
2471 netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]",
2472 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
2473 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
2474 pr_cont(" condition[%08x]\n",
2475 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
2476 DP_SHMEM_LINE(bp, 0x3cc);
2477 DP_SHMEM_LINE(bp, 0x3dc);
2478 DP_SHMEM_LINE(bp, 0x3ec);
2479 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
2480 netdev_err(dev, "<--- end MCP states dump --->\n");
2481}
2482
b6016b76 2483static int
a2f13890 2484bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
b6016b76
MC		 2485{
2486 int i;
2487 u32 val;
2488
b6016b76
MC		 2489 bp->fw_wr_seq++;
2490 msg_data |= bp->fw_wr_seq;
2491
2726d6e1 2492 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2493
a2f13890
MC		 2494 if (!ack)
2495 return 0;
2496
b6016b76 2497 /* wait for an acknowledgement. */
40105c0b 2498 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
b090ae2b 2499 msleep(10);
b6016b76 2500
2726d6e1 2501 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2502
2503 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2504 break;
2505 }
b090ae2b
MC		 2506 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2507 return 0;
b6016b76
MC		 2508
2509 /* If we timed out, inform the firmware that this is the case. */
b090ae2b 2510 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
b6016b76
MC		 2511 msg_data &= ~BNX2_DRV_MSG_CODE;
2512 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2513
2726d6e1 2514 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
ecdbf6e0
JH		 2515 if (!silent) {
2516 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2517 bnx2_dump_mcp_state(bp);
2518 }
b6016b76 2519
b6016b76
MC		 2520 return -EBUSY;
2521 }
2522
b090ae2b
MC		 2523 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2524 return -EIO;
2525
b6016b76
MC		 2526 return 0;
2527}
2528
59b47d8a
MC		 2529static int
2530bnx2_init_5709_context(struct bnx2 *bp)
2531{
2532 int i, ret = 0;
2533 u32 val;
2534
2535 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2536 val |= (BCM_PAGE_BITS - 8) << 16;
2537 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2538 for (i = 0; i < 10; i++) {
2539 val = REG_RD(bp, BNX2_CTX_COMMAND);
2540 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2541 break;
2542 udelay(2);
2543 }
2544 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2545 return -EBUSY;
2546
59b47d8a
MC		 2547 for (i = 0; i < bp->ctx_pages; i++) {
2548 int j;
2549
352f7687
MC		 2550 if (bp->ctx_blk[i])
2551 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2552 else
2553 return -ENOMEM;
2554
59b47d8a
MC		 2555 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2556 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2557 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2558 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2559 (u64) bp->ctx_blk_mapping[i] >> 32);
2560 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2561 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2562 for (j = 0; j < 10; j++) {
2563
2564 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2565 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2566 break;
2567 udelay(5);
2568 }
2569 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2570 ret = -EBUSY;
2571 break;
2572 }
2573 }
2574 return ret;
2575}
2576
b6016b76
MC		 2577static void
2578bnx2_init_context(struct bnx2 *bp)
2579{
2580 u32 vcid;
2581
2582 vcid = 96;
2583 while (vcid) {
2584 u32 vcid_addr, pcid_addr, offset;
7947b20e 2585 int i;
b6016b76
MC		 2586
2587 vcid--;
2588
2589 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2590 u32 new_vcid;
2591
2592 vcid_addr = GET_PCID_ADDR(vcid);
2593 if (vcid & 0x8) {
2594 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2595 }
2596 else {
2597 new_vcid = vcid;
2598 }
2599 pcid_addr = GET_PCID_ADDR(new_vcid);
2600 }
2601 else {
2602 vcid_addr = GET_CID_ADDR(vcid);
2603 pcid_addr = vcid_addr;
2604 }
2605
7947b20e
MC		 2606 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2607 vcid_addr += (i << PHY_CTX_SHIFT);
2608 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2609
5d5d0015 2610 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2611 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2612
7947b20e
MC		 2613 /* Zero out the context. */
2614 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2615 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2616 }
b6016b76
MC		 2617 }
2618}
2619
2620static int
2621bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2622{
2623 u16 *good_mbuf;
2624 u32 good_mbuf_cnt;
2625 u32 val;
2626
2627 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2628 if (good_mbuf == NULL) {
3a9c6a49 2629 pr_err("Failed to allocate memory in %s\n", __func__);
b6016b76
MC		 2630 return -ENOMEM;
2631 }
2632
2633 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2634 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2635
2636 good_mbuf_cnt = 0;
2637
2638 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2639 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2640 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2641 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2642 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2643
2726d6e1 2644 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2645
2646 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2647
2648 /* The addresses with Bit 9 set are bad memory blocks. */
2649 if (!(val & (1 << 9))) {
2650 good_mbuf[good_mbuf_cnt] = (u16) val;
2651 good_mbuf_cnt++;
2652 }
2653
2726d6e1 2654 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2655 }
2656
2657 /* Free the good ones back to the mbuf pool thus discarding
2658 * all the bad ones. */
2659 while (good_mbuf_cnt) {
2660 good_mbuf_cnt--;
2661
2662 val = good_mbuf[good_mbuf_cnt];
2663 val = (val << 9) | val | 1;
2664
2726d6e1 2665 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2666 }
2667 kfree(good_mbuf);
2668 return 0;
2669}
2670
2671static void
5fcaed01 2672bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
b6016b76
MC		 2673{
2674 u32 val;
b6016b76
MC		 2675
2676 val = (mac_addr[0] << 8) | mac_addr[1];
2677
5fcaed01 2678 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
b6016b76 2679
6aa20a22 2680 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2681 (mac_addr[4] << 8) | mac_addr[5];
2682
5fcaed01 2683 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
b6016b76
MC		 2684}
2685
47bf4246 2686static inline int
a2df00aa 2687bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
47bf4246
MC		 2688{
2689 dma_addr_t mapping;
bb4f98ab 2690 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246 2691 struct rx_bd *rxbd =
bb4f98ab 2692 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
a2df00aa 2693 struct page *page = alloc_page(gfp);
47bf4246
MC		 2694
2695 if (!page)
2696 return -ENOMEM;
36227e88 2697 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
47bf4246 2698 PCI_DMA_FROMDEVICE);
36227e88 2699 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 2700 __free_page(page);
2701 return -EIO;
2702 }
2703
47bf4246 2704 rx_pg->page = page;
1a4ccc2d 2705 dma_unmap_addr_set(rx_pg, mapping, mapping);
47bf4246
MC		 2706 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2707 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2708 return 0;
2709}
2710
2711static void
bb4f98ab 2712bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246 2713{
bb4f98ab 2714 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246
MC		 2715 struct page *page = rx_pg->page;
2716
2717 if (!page)
2718 return;
2719
36227e88
SG		 2720 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2721 PAGE_SIZE, PCI_DMA_FROMDEVICE);
47bf4246
MC		 2722
2723 __free_page(page);
2724 rx_pg->page = NULL;
2725}
2726
b6016b76 2727static inline int
dd2bc8e9 2728bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
b6016b76 2729{
dd2bc8e9 2730 u8 *data;
bb4f98ab 2731 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
b6016b76 2732 dma_addr_t mapping;
bb4f98ab 2733 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76 2734
dd2bc8e9
ED		 2735 data = kmalloc(bp->rx_buf_size, gfp);
2736 if (!data)
b6016b76 2737 return -ENOMEM;
b6016b76 2738
dd2bc8e9
ED		 2739 mapping = dma_map_single(&bp->pdev->dev,
2740 get_l2_fhdr(data),
2741 bp->rx_buf_use_size,
36227e88
SG		 2742 PCI_DMA_FROMDEVICE);
2743 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
dd2bc8e9 2744 kfree(data);
3d16af86
BL		 2745 return -EIO;
2746 }
b6016b76 2747
dd2bc8e9 2748 rx_buf->data = data;
1a4ccc2d 2749 dma_unmap_addr_set(rx_buf, mapping, mapping);
b6016b76
MC		 2750
2751 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2752 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2753
bb4f98ab 2754 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2755
2756 return 0;
2757}
2758
da3e4fbe 2759static int
35efa7c1 2760bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2761{
43e80b89 2762 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76 2763 u32 new_link_state, old_link_state;
da3e4fbe 2764 int is_set = 1;
b6016b76 2765
da3e4fbe
MC		 2766 new_link_state = sblk->status_attn_bits & event;
2767 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2768 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2769 if (new_link_state)
2770 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2771 else
2772 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2773 } else
2774 is_set = 0;
2775
2776 return is_set;
2777}
2778
2779static void
35efa7c1 2780bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2781{
74ecc62d
MC		 2782 spin_lock(&bp->phy_lock);
2783
2784 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2785 bnx2_set_link(bp);
35efa7c1 2786 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2787 bnx2_set_remote_link(bp);
2788
74ecc62d
MC		 2789 spin_unlock(&bp->phy_lock);
2790
b6016b76
MC		 2791}
2792
ead7270b 2793static inline u16
35efa7c1 2794bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2795{
2796 u16 cons;
2797
43e80b89
MC		 2798 /* Tell compiler that status block fields can change. */
2799 barrier();
2800 cons = *bnapi->hw_tx_cons_ptr;
581daf7e 2801 barrier();
ead7270b
MC		 2802 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2803 cons++;
2804 return cons;
2805}
2806
57851d84
MC		 2807static int
2808bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2809{
35e9010b 2810 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
b6016b76 2811 u16 hw_cons, sw_cons, sw_ring_cons;
706bf240
BL		 2812 int tx_pkt = 0, index;
2813 struct netdev_queue *txq;
2814
2815 index = (bnapi - bp->bnx2_napi);
2816 txq = netdev_get_tx_queue(bp->dev, index);
b6016b76 2817
35efa7c1 2818 hw_cons = bnx2_get_hw_tx_cons(bnapi);
35e9010b 2819 sw_cons = txr->tx_cons;
b6016b76
MC		 2820
2821 while (sw_cons != hw_cons) {
3d16af86 2822 struct sw_tx_bd *tx_buf;
b6016b76
MC		 2823 struct sk_buff *skb;
2824 int i, last;
2825
2826 sw_ring_cons = TX_RING_IDX(sw_cons);
2827
35e9010b 2828 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
b6016b76 2829 skb = tx_buf->skb;
1d39ed56 2830
d62fda08
ED		 2831 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2832 prefetch(&skb->end);
2833
b6016b76 2834 /* partial BD completions possible with TSO packets */
d62fda08 2835 if (tx_buf->is_gso) {
b6016b76
MC		 2836 u16 last_idx, last_ring_idx;
2837
d62fda08
ED		 2838 last_idx = sw_cons + tx_buf->nr_frags + 1;
2839 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
b6016b76
MC		 2840 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2841 last_idx++;
2842 }
2843 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2844 break;
2845 }
2846 }
1d39ed56 2847
36227e88 2848 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7 2849 skb_headlen(skb), PCI_DMA_TODEVICE);
b6016b76
MC		 2850
2851 tx_buf->skb = NULL;
d62fda08 2852 last = tx_buf->nr_frags;
b6016b76
MC		 2853
2854 for (i = 0; i < last; i++) {
2855 sw_cons = NEXT_TX_BD(sw_cons);
e95524a7 2856
36227e88 2857 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 2858 dma_unmap_addr(
e95524a7
AD		 2859 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2860 mapping),
9e903e08 2861 skb_frag_size(&skb_shinfo(skb)->frags[i]),
e95524a7 2862 PCI_DMA_TODEVICE);
b6016b76
MC		 2863 }
2864
2865 sw_cons = NEXT_TX_BD(sw_cons);
2866
745720e5 2867 dev_kfree_skb(skb);
57851d84
MC		 2868 tx_pkt++;
2869 if (tx_pkt == budget)
2870 break;
b6016b76 2871
d62fda08
ED		 2872 if (hw_cons == sw_cons)
2873 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2874 }
2875
35e9010b
MC		 2876 txr->hw_tx_cons = hw_cons;
2877 txr->tx_cons = sw_cons;
706bf240 2878
2f8af120 2879 /* Need to make the tx_cons update visible to bnx2_start_xmit()
706bf240 2880 * before checking for netif_tx_queue_stopped(). Without the
2f8af120
MC		 2881 * memory barrier, there is a small possibility that bnx2_start_xmit()
2882 * will miss it and cause the queue to be stopped forever.
2883 */
2884 smp_mb();
b6016b76 2885
706bf240 2886 if (unlikely(netif_tx_queue_stopped(txq)) &&
35e9010b 2887 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
706bf240
BL		 2888 __netif_tx_lock(txq, smp_processor_id());
2889 if ((netif_tx_queue_stopped(txq)) &&
35e9010b 2890 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
706bf240
BL		 2891 netif_tx_wake_queue(txq);
2892 __netif_tx_unlock(txq);
b6016b76 2893 }
706bf240 2894
57851d84 2895 return tx_pkt;
b6016b76
MC		 2896}
2897
1db82f2a 2898static void
bb4f98ab 2899bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
a1f60190 2900 struct sk_buff *skb, int count)
1db82f2a
MC		 2901{
2902 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2903 struct rx_bd *cons_bd, *prod_bd;
1db82f2a 2904 int i;
3d16af86 2905 u16 hw_prod, prod;
bb4f98ab 2906 u16 cons = rxr->rx_pg_cons;
1db82f2a 2907
3d16af86
BL		 2908 cons_rx_pg = &rxr->rx_pg_ring[cons];
2909
2910 /* The caller was unable to allocate a new page to replace the
2911 * last one in the frags array, so we need to recycle that page
2912 * and then free the skb.
2913 */
2914 if (skb) {
2915 struct page *page;
2916 struct skb_shared_info *shinfo;
2917
2918 shinfo = skb_shinfo(skb);
2919 shinfo->nr_frags--;
b7b6a688
IC		 2920 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]);
2921 __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL);
3d16af86
BL		 2922
2923 cons_rx_pg->page = page;
2924 dev_kfree_skb(skb);
2925 }
2926
2927 hw_prod = rxr->rx_pg_prod;
2928
1db82f2a
MC		 2929 for (i = 0; i < count; i++) {
2930 prod = RX_PG_RING_IDX(hw_prod);
2931
bb4f98ab
MC		 2932 prod_rx_pg = &rxr->rx_pg_ring[prod];
2933 cons_rx_pg = &rxr->rx_pg_ring[cons];
2934 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2935 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1db82f2a 2936
1db82f2a
MC		 2937 if (prod != cons) {
2938 prod_rx_pg->page = cons_rx_pg->page;
2939 cons_rx_pg->page = NULL;
1a4ccc2d
FT		 2940 dma_unmap_addr_set(prod_rx_pg, mapping,
2941 dma_unmap_addr(cons_rx_pg, mapping));
1db82f2a
MC		 2942
2943 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2944 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2945
2946 }
2947 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2948 hw_prod = NEXT_RX_BD(hw_prod);
2949 }
bb4f98ab
MC		 2950 rxr->rx_pg_prod = hw_prod;
2951 rxr->rx_pg_cons = cons;
1db82f2a
MC		 2952}
2953
b6016b76 2954static inline void
dd2bc8e9
ED		 2955bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2956 u8 *data, u16 cons, u16 prod)
b6016b76 2957{
236b6394
MC		 2958 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2959 struct rx_bd *cons_bd, *prod_bd;
2960
bb4f98ab
MC		 2961 cons_rx_buf = &rxr->rx_buf_ring[cons];
2962 prod_rx_buf = &rxr->rx_buf_ring[prod];
b6016b76 2963
36227e88 2964 dma_sync_single_for_device(&bp->pdev->dev,
1a4ccc2d 2965 dma_unmap_addr(cons_rx_buf, mapping),
601d3d18 2966 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 2967
bb4f98ab 2968 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2969
dd2bc8e9 2970 prod_rx_buf->data = data;
b6016b76 2971
236b6394
MC		 2972 if (cons == prod)
2973 return;
b6016b76 2974
1a4ccc2d
FT		 2975 dma_unmap_addr_set(prod_rx_buf, mapping,
2976 dma_unmap_addr(cons_rx_buf, mapping));
236b6394 2977
bb4f98ab
MC		 2978 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2979 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2980 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2981 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2982}
2983
dd2bc8e9
ED		 2984static struct sk_buff *
2985bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,
a1f60190
MC		 2986 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2987 u32 ring_idx)
85833c62
MC		 2988{
2989 int err;
2990 u16 prod = ring_idx & 0xffff;
dd2bc8e9 2991 struct sk_buff *skb;
85833c62 2992
dd2bc8e9 2993 err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
85833c62 2994 if (unlikely(err)) {
dd2bc8e9
ED		 2995 bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);
2996error:
1db82f2a
MC		 2997 if (hdr_len) {
2998 unsigned int raw_len = len + 4;
2999 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
3000
bb4f98ab 3001 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
1db82f2a 3002 }
dd2bc8e9 3003 return NULL;
85833c62
MC		 3004 }
3005
36227e88 3006 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
85833c62 3007 PCI_DMA_FROMDEVICE);
dd2bc8e9
ED		 3008 skb = build_skb(data);
3009 if (!skb) {
3010 kfree(data);
3011 goto error;
3012 }
3013 skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET);
1db82f2a
MC		 3014 if (hdr_len == 0) {
3015 skb_put(skb, len);
dd2bc8e9 3016 return skb;
1db82f2a
MC		 3017 } else {
3018 unsigned int i, frag_len, frag_size, pages;
3019 struct sw_pg *rx_pg;
bb4f98ab
MC		 3020 u16 pg_cons = rxr->rx_pg_cons;
3021 u16 pg_prod = rxr->rx_pg_prod;
1db82f2a
MC		 3022
3023 frag_size = len + 4 - hdr_len;
3024 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3025 skb_put(skb, hdr_len);
3026
3027 for (i = 0; i < pages; i++) {
3d16af86
BL		 3028 dma_addr_t mapping_old;
3029
1db82f2a
MC		 3030 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3031 if (unlikely(frag_len <= 4)) {
3032 unsigned int tail = 4 - frag_len;
3033
bb4f98ab
MC		 3034 rxr->rx_pg_cons = pg_cons;
3035 rxr->rx_pg_prod = pg_prod;
3036 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
a1f60190 3037 pages - i);
1db82f2a
MC		 3038 skb->len -= tail;
3039 if (i == 0) {
3040 skb->tail -= tail;
3041 } else {
3042 skb_frag_t *frag =
3043 &skb_shinfo(skb)->frags[i - 1];
9e903e08 3044 skb_frag_size_sub(frag, tail);
1db82f2a 3045 skb->data_len -= tail;
1db82f2a 3046 }
dd2bc8e9 3047 return skb;
1db82f2a 3048 }
bb4f98ab 3049 rx_pg = &rxr->rx_pg_ring[pg_cons];
1db82f2a 3050
3d16af86
BL		 3051 /* Don't unmap yet. If we're unable to allocate a new
3052 * page, we need to recycle the page and the DMA addr.
3053 */
1a4ccc2d 3054 mapping_old = dma_unmap_addr(rx_pg, mapping);
1db82f2a
MC		 3055 if (i == pages - 1)
3056 frag_len -= 4;
3057
3058 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3059 rx_pg->page = NULL;
3060
bb4f98ab 3061 err = bnx2_alloc_rx_page(bp, rxr,
a2df00aa
SG		 3062 RX_PG_RING_IDX(pg_prod),
3063 GFP_ATOMIC);
1db82f2a 3064 if (unlikely(err)) {
bb4f98ab
MC		 3065 rxr->rx_pg_cons = pg_cons;
3066 rxr->rx_pg_prod = pg_prod;
3067 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
a1f60190 3068 pages - i);
dd2bc8e9 3069 return NULL;
1db82f2a
MC		 3070 }
3071
36227e88 3072 dma_unmap_page(&bp->pdev->dev, mapping_old,
3d16af86
BL		 3073 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3074
1db82f2a
MC		 3075 frag_size -= frag_len;
3076 skb->data_len += frag_len;
a1f4e8bc 3077 skb->truesize += PAGE_SIZE;
1db82f2a
MC		 3078 skb->len += frag_len;
3079
3080 pg_prod = NEXT_RX_BD(pg_prod);
3081 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3082 }
bb4f98ab
MC		 3083 rxr->rx_pg_prod = pg_prod;
3084 rxr->rx_pg_cons = pg_cons;
1db82f2a 3085 }
dd2bc8e9 3086 return skb;
85833c62
MC		 3087}
3088
c09c2627 3089static inline u16
35efa7c1 3090bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 3091{
bb4f98ab
MC		 3092 u16 cons;
3093
43e80b89
MC		 3094 /* Tell compiler that status block fields can change. */
3095 barrier();
3096 cons = *bnapi->hw_rx_cons_ptr;
581daf7e 3097 barrier();
c09c2627
MC		 3098 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3099 cons++;
3100 return cons;
3101}
3102
b6016b76 3103static int
35efa7c1 3104bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 3105{
bb4f98ab 3106 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76
MC		 3107 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3108 struct l2_fhdr *rx_hdr;
1db82f2a 3109 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 3110
35efa7c1 3111 hw_cons = bnx2_get_hw_rx_cons(bnapi);
bb4f98ab
MC		 3112 sw_cons = rxr->rx_cons;
3113 sw_prod = rxr->rx_prod;
b6016b76
MC		 3114
3115 /* Memory barrier necessary as speculative reads of the rx
3116 * buffer can be ahead of the index in the status block
3117 */
3118 rmb();
3119 while (sw_cons != hw_cons) {
1db82f2a 3120 unsigned int len, hdr_len;
ade2bfe7 3121 u32 status;
a33fa66b 3122 struct sw_bd *rx_buf, *next_rx_buf;
b6016b76 3123 struct sk_buff *skb;
236b6394 3124 dma_addr_t dma_addr;
dd2bc8e9 3125 u8 *data;
b6016b76
MC		 3126
3127 sw_ring_cons = RX_RING_IDX(sw_cons);
3128 sw_ring_prod = RX_RING_IDX(sw_prod);
3129
bb4f98ab 3130 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
dd2bc8e9
ED		 3131 data = rx_buf->data;
3132 rx_buf->data = NULL;
aabef8b2 3133
dd2bc8e9
ED		 3134 rx_hdr = get_l2_fhdr(data);
3135 prefetch(rx_hdr);
236b6394 3136
1a4ccc2d 3137 dma_addr = dma_unmap_addr(rx_buf, mapping);
236b6394 3138
36227e88 3139 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
601d3d18
BL		 3140 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3141 PCI_DMA_FROMDEVICE);
b6016b76 3142
dd2bc8e9
ED		 3143 next_rx_buf =
3144 &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3145 prefetch(get_l2_fhdr(next_rx_buf->data));
3146
1db82f2a 3147 len = rx_hdr->l2_fhdr_pkt_len;
990ec380 3148 status = rx_hdr->l2_fhdr_status;
b6016b76 3149
1db82f2a
MC		 3150 hdr_len = 0;
3151 if (status & L2_FHDR_STATUS_SPLIT) {
3152 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3153 pg_ring_used = 1;
3154 } else if (len > bp->rx_jumbo_thresh) {
3155 hdr_len = bp->rx_jumbo_thresh;
3156 pg_ring_used = 1;
3157 }
3158
990ec380
MC		 3159 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3160 L2_FHDR_ERRORS_PHY_DECODE |
3161 L2_FHDR_ERRORS_ALIGNMENT |
3162 L2_FHDR_ERRORS_TOO_SHORT |
3163 L2_FHDR_ERRORS_GIANT_FRAME))) {
3164
dd2bc8e9 3165 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
990ec380
MC		 3166 sw_ring_prod);
3167 if (pg_ring_used) {
3168 int pages;
3169
3170 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3171
3172 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3173 }
3174 goto next_rx;
3175 }
3176
1db82f2a 3177 len -= 4;
b6016b76 3178
5d5d0015 3179 if (len <= bp->rx_copy_thresh) {
dd2bc8e9
ED		 3180 skb = netdev_alloc_skb(bp->dev, len + 6);
3181 if (skb == NULL) {
3182 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
85833c62
MC		 3183 sw_ring_prod);
3184 goto next_rx;
3185 }
b6016b76
MC		 3186
3187 /* aligned copy */
dd2bc8e9
ED		 3188 memcpy(skb->data,
3189 (u8 *)rx_hdr + BNX2_RX_OFFSET - 6,
3190 len + 6);
3191 skb_reserve(skb, 6);
3192 skb_put(skb, len);
b6016b76 3193
dd2bc8e9 3194 bnx2_reuse_rx_data(bp, rxr, data,
b6016b76
MC		 3195 sw_ring_cons, sw_ring_prod);
3196
dd2bc8e9
ED		 3197 } else {
3198 skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,
3199 (sw_ring_cons << 16) | sw_ring_prod);
3200 if (!skb)
3201 goto next_rx;
3202 }
f22828e8 3203 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
7d0fd211
JG		 3204 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
3205 __vlan_hwaccel_put_tag(skb, rx_hdr->l2_fhdr_vlan_tag);
f22828e8 3206
b6016b76
MC		 3207 skb->protocol = eth_type_trans(skb, bp->dev);
3208
3209 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 3210 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 3211
745720e5 3212 dev_kfree_skb(skb);
b6016b76
MC		 3213 goto next_rx;
3214
3215 }
3216
bc8acf2c 3217 skb_checksum_none_assert(skb);
8d7dfc2b 3218 if ((bp->dev->features & NETIF_F_RXCSUM) &&
b6016b76
MC		 3219 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3220 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3221
ade2bfe7
MC		 3222 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3223 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 3224 skb->ip_summed = CHECKSUM_UNNECESSARY;
3225 }
fdc8541d
MC		 3226 if ((bp->dev->features & NETIF_F_RXHASH) &&
3227 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3228 L2_FHDR_STATUS_USE_RXHASH))
3229 skb->rxhash = rx_hdr->l2_fhdr_hash;
b6016b76 3230
0c8dfc83 3231 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
7d0fd211 3232 napi_gro_receive(&bnapi->napi, skb);
b6016b76
MC		 3233 rx_pkt++;
3234
3235next_rx:
b6016b76
MC		 3236 sw_cons = NEXT_RX_BD(sw_cons);
3237 sw_prod = NEXT_RX_BD(sw_prod);
3238
3239 if ((rx_pkt == budget))
3240 break;
f4e418f7
MC		 3241
3242 /* Refresh hw_cons to see if there is new work */
3243 if (sw_cons == hw_cons) {
35efa7c1 3244 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 3245 rmb();
3246 }
b6016b76 3247 }
bb4f98ab
MC		 3248 rxr->rx_cons = sw_cons;
3249 rxr->rx_prod = sw_prod;
b6016b76 3250
1db82f2a 3251 if (pg_ring_used)
bb4f98ab 3252 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
1db82f2a 3253
bb4f98ab 3254 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
b6016b76 3255
bb4f98ab 3256 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 3257
3258 mmiowb();
3259
3260 return rx_pkt;
3261
3262}
3263
3264/* MSI ISR - The only difference between this and the INTx ISR
3265 * is that the MSI interrupt is always serviced.
3266 */
3267static irqreturn_t
7d12e780 3268bnx2_msi(int irq, void *dev_instance)
b6016b76 3269{
f0ea2e63
MC		 3270 struct bnx2_napi *bnapi = dev_instance;
3271 struct bnx2 *bp = bnapi->bp;
b6016b76 3272
43e80b89 3273 prefetch(bnapi->status_blk.msi);
b6016b76
MC		 3274 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3275 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3276 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3277
3278 /* Return here if interrupt is disabled. */
73eef4cd
MC		 3279 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3280 return IRQ_HANDLED;
b6016b76 3281
288379f0 3282 napi_schedule(&bnapi->napi);
b6016b76 3283
73eef4cd 3284 return IRQ_HANDLED;
b6016b76
MC		 3285}
3286
8e6a72c4
MC		 3287static irqreturn_t
3288bnx2_msi_1shot(int irq, void *dev_instance)
3289{
f0ea2e63
MC		 3290 struct bnx2_napi *bnapi = dev_instance;
3291 struct bnx2 *bp = bnapi->bp;
8e6a72c4 3292
43e80b89 3293 prefetch(bnapi->status_blk.msi);
8e6a72c4
MC		 3294
3295 /* Return here if interrupt is disabled. */
3296 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3297 return IRQ_HANDLED;
3298
288379f0 3299 napi_schedule(&bnapi->napi);
8e6a72c4
MC		 3300
3301 return IRQ_HANDLED;
3302}
3303
b6016b76 3304static irqreturn_t
7d12e780 3305bnx2_interrupt(int irq, void *dev_instance)
b6016b76 3306{
f0ea2e63
MC		 3307 struct bnx2_napi *bnapi = dev_instance;
3308 struct bnx2 *bp = bnapi->bp;
43e80b89 3309 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76
MC		 3310
3311 /* When using INTx, it is possible for the interrupt to arrive
3312 * at the CPU before the status block posted prior to the
3313 * interrupt. Reading a register will flush the status block.
3314 * When using MSI, the MSI message will always complete after
3315 * the status block write.
3316 */
35efa7c1 3317 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 3318 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3319 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 3320 return IRQ_NONE;
b6016b76
MC		 3321
3322 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3323 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3324 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3325
b8a7ce7b
MC		 3326 /* Read back to deassert IRQ immediately to avoid too many
3327 * spurious interrupts.
3328 */
3329 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3330
b6016b76 3331 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 3332 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3333 return IRQ_HANDLED;
b6016b76 3334
288379f0 3335 if (napi_schedule_prep(&bnapi->napi)) {
35efa7c1 3336 bnapi->last_status_idx = sblk->status_idx;
288379f0 3337 __napi_schedule(&bnapi->napi);
b8a7ce7b 3338 }
b6016b76 3339
73eef4cd 3340 return IRQ_HANDLED;
b6016b76
MC		 3341}
3342
f4e418f7 3343static inline int
43e80b89 3344bnx2_has_fast_work(struct bnx2_napi *bnapi)
f4e418f7 3345{
35e9010b 3346 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 3347 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
f4e418f7 3348
bb4f98ab 3349 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
35e9010b 3350 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
f4e418f7 3351 return 1;
43e80b89
MC		 3352 return 0;
3353}
3354
3355#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3356 STATUS_ATTN_BITS_TIMER_ABORT)
3357
3358static inline int
3359bnx2_has_work(struct bnx2_napi *bnapi)
3360{
3361 struct status_block *sblk = bnapi->status_blk.msi;
3362
3363 if (bnx2_has_fast_work(bnapi))
3364 return 1;
f4e418f7 3365
4edd473f
MC		 3366#ifdef BCM_CNIC
3367 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3368 return 1;
3369#endif
3370
da3e4fbe
MC		 3371 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3372 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3373 return 1;
3374
3375 return 0;
3376}
3377
efba0180
MC		 3378static void
3379bnx2_chk_missed_msi(struct bnx2 *bp)
3380{
3381 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3382 u32 msi_ctrl;
3383
3384 if (bnx2_has_work(bnapi)) {
3385 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3386 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3387 return;
3388
3389 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3390 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3391 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3392 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3393 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3394 }
3395 }
3396
3397 bp->idle_chk_status_idx = bnapi->last_status_idx;
3398}
3399
4edd473f
MC		 3400#ifdef BCM_CNIC
3401static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3402{
3403 struct cnic_ops *c_ops;
3404
3405 if (!bnapi->cnic_present)
3406 return;
3407
3408 rcu_read_lock();
3409 c_ops = rcu_dereference(bp->cnic_ops);
3410 if (c_ops)
3411 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3412 bnapi->status_blk.msi);
3413 rcu_read_unlock();
3414}
3415#endif
3416
43e80b89 3417static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
b6016b76 3418{
43e80b89 3419 struct status_block *sblk = bnapi->status_blk.msi;
da3e4fbe
MC		 3420 u32 status_attn_bits = sblk->status_attn_bits;
3421 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3422
da3e4fbe
MC		 3423 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3424 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3425
35efa7c1 3426 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3427
3428 /* This is needed to take care of transient status
3429 * during link changes.
3430 */
3431 REG_WR(bp, BNX2_HC_COMMAND,
3432 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3433 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76 3434 }
43e80b89
MC		 3435}
3436
3437static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3438 int work_done, int budget)
3439{
3440 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3441 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76 3442
35e9010b 3443 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
57851d84 3444 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3445
bb4f98ab 3446 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
35efa7c1 3447 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3448
6f535763
DM		 3449 return work_done;
3450}
3451
f0ea2e63
MC		 3452static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3453{
3454 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3455 struct bnx2 *bp = bnapi->bp;
3456 int work_done = 0;
3457 struct status_block_msix *sblk = bnapi->status_blk.msix;
3458
3459 while (1) {
3460 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3461 if (unlikely(work_done >= budget))
3462 break;
3463
3464 bnapi->last_status_idx = sblk->status_idx;
3465 /* status idx must be read before checking for more work. */
3466 rmb();
3467 if (likely(!bnx2_has_fast_work(bnapi))) {
3468
288379f0 3469 napi_complete(napi);
f0ea2e63
MC		 3470 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3471 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3472 bnapi->last_status_idx);
3473 break;
3474 }
3475 }
3476 return work_done;
3477}
3478
6f535763
DM		 3479static int bnx2_poll(struct napi_struct *napi, int budget)
3480{
35efa7c1
MC		 3481 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3482 struct bnx2 *bp = bnapi->bp;
6f535763 3483 int work_done = 0;
43e80b89 3484 struct status_block *sblk = bnapi->status_blk.msi;
6f535763
DM		 3485
3486 while (1) {
43e80b89
MC		 3487 bnx2_poll_link(bp, bnapi);
3488
35efa7c1 3489 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3490
4edd473f
MC		 3491#ifdef BCM_CNIC
3492 bnx2_poll_cnic(bp, bnapi);
3493#endif
3494
35efa7c1 3495 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3496 * much work has been processed, so we must read it before
3497 * checking for more work.
3498 */
35efa7c1 3499 bnapi->last_status_idx = sblk->status_idx;
efba0180
MC		 3500
3501 if (unlikely(work_done >= budget))
3502 break;
3503
6dee6421 3504 rmb();
35efa7c1 3505 if (likely(!bnx2_has_work(bnapi))) {
288379f0 3506 napi_complete(napi);
f86e82fb 3507 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3508 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3509 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3510 bnapi->last_status_idx);
6dee6421 3511 break;
6f535763 3512 }
1269a8a6
MC		 3513 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3514 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3515 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3516 bnapi->last_status_idx);
1269a8a6 3517
6f535763
DM		 3518 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3519 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3520 bnapi->last_status_idx);
6f535763
DM		 3521 break;
3522 }
b6016b76
MC		 3523 }
3524
bea3348e 3525 return work_done;
b6016b76
MC		 3526}
3527
932ff279 3528/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3529 * from set_multicast.
3530 */
3531static void
3532bnx2_set_rx_mode(struct net_device *dev)
3533{
972ec0d4 3534 struct bnx2 *bp = netdev_priv(dev);
b6016b76 3535 u32 rx_mode, sort_mode;
ccffad25 3536 struct netdev_hw_addr *ha;
b6016b76 3537 int i;
b6016b76 3538
9f52b564
MC		 3539 if (!netif_running(dev))
3540 return;
3541
c770a65c 3542 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3543
3544 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3545 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3546 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
7d0fd211
JG		 3547 if (!(dev->features & NETIF_F_HW_VLAN_RX) &&
3548 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
b6016b76 3549 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3550 if (dev->flags & IFF_PROMISC) {
3551 /* Promiscuous mode. */
3552 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3553 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3554 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3555 }
3556 else if (dev->flags & IFF_ALLMULTI) {
3557 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3558 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3559 0xffffffff);
3560 }
3561 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3562 }
3563 else {
3564 /* Accept one or more multicast(s). */
b6016b76
MC		 3565 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3566 u32 regidx;
3567 u32 bit;
3568 u32 crc;
3569
3570 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3571
22bedad3
JP		 3572 netdev_for_each_mc_addr(ha, dev) {
3573 crc = ether_crc_le(ETH_ALEN, ha->addr);
b6016b76
MC		 3574 bit = crc & 0xff;
3575 regidx = (bit & 0xe0) >> 5;
3576 bit &= 0x1f;
3577 mc_filter[regidx] |= (1 << bit);
3578 }
3579
3580 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3581 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3582 mc_filter[i]);
3583 }
3584
3585 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3586 }
3587
32e7bfc4 3588 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
5fcaed01
BL		 3589 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3590 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3591 BNX2_RPM_SORT_USER0_PROM_VLAN;
3592 } else if (!(dev->flags & IFF_PROMISC)) {
5fcaed01 3593 /* Add all entries into to the match filter list */
ccffad25 3594 i = 0;
32e7bfc4 3595 netdev_for_each_uc_addr(ha, dev) {
ccffad25 3596 bnx2_set_mac_addr(bp, ha->addr,
5fcaed01
BL		 3597 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3598 sort_mode |= (1 <<
3599 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
ccffad25 3600 i++;
5fcaed01
BL		 3601 }
3602
3603 }
3604
b6016b76
MC		 3605 if (rx_mode != bp->rx_mode) {
3606 bp->rx_mode = rx_mode;
3607 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3608 }
3609
3610 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3611 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3612 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3613
c770a65c 3614 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3615}
3616
7880b72e 3617static int
57579f76
MC		 3618check_fw_section(const struct firmware *fw,
3619 const struct bnx2_fw_file_section *section,
3620 u32 alignment, bool non_empty)
3621{
3622 u32 offset = be32_to_cpu(section->offset);
3623 u32 len = be32_to_cpu(section->len);
3624
3625 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3626 return -EINVAL;
3627 if ((non_empty && len == 0) || len > fw->size - offset ||
3628 len & (alignment - 1))
3629 return -EINVAL;
3630 return 0;
3631}
3632
7880b72e 3633static int
57579f76
MC		 3634check_mips_fw_entry(const struct firmware *fw,
3635 const struct bnx2_mips_fw_file_entry *entry)
3636{
3637 if (check_fw_section(fw, &entry->text, 4, true) ||
3638 check_fw_section(fw, &entry->data, 4, false) ||
3639 check_fw_section(fw, &entry->rodata, 4, false))
3640 return -EINVAL;
3641 return 0;
3642}
3643
7880b72e 3644static void bnx2_release_firmware(struct bnx2 *bp)
3645{
3646 if (bp->rv2p_firmware) {
3647 release_firmware(bp->mips_firmware);
3648 release_firmware(bp->rv2p_firmware);
3649 bp->rv2p_firmware = NULL;
3650 }
3651}
3652
3653static int bnx2_request_uncached_firmware(struct bnx2 *bp)
b6016b76 3654{
57579f76 3655 const char *mips_fw_file, *rv2p_fw_file;
5ee1c326
BB		 3656 const struct bnx2_mips_fw_file *mips_fw;
3657 const struct bnx2_rv2p_fw_file *rv2p_fw;
57579f76
MC		 3658 int rc;
3659
3660 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3661 mips_fw_file = FW_MIPS_FILE_09;
078b0735
MC		 3662 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3663 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3664 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3665 else
3666 rv2p_fw_file = FW_RV2P_FILE_09;
57579f76
MC		 3667 } else {
3668 mips_fw_file = FW_MIPS_FILE_06;
3669 rv2p_fw_file = FW_RV2P_FILE_06;
3670 }
3671
3672 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3673 if (rc) {
3a9c6a49 3674 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
7880b72e 3675 goto out;
57579f76
MC		 3676 }
3677
3678 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3679 if (rc) {
3a9c6a49 3680 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
7880b72e 3681 goto err_release_mips_firmware;
57579f76 3682 }
5ee1c326
BB		 3683 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3684 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3685 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3686 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3687 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3688 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3689 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3690 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3a9c6a49 3691 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
7880b72e 3692 rc = -EINVAL;
3693 goto err_release_firmware;
57579f76 3694 }
5ee1c326
BB		 3695 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3696 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3697 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3a9c6a49 3698 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
7880b72e 3699 rc = -EINVAL;
3700 goto err_release_firmware;
57579f76 3701 }
7880b72e 3702out:
3703 return rc;
57579f76 3704
7880b72e 3705err_release_firmware:
3706 release_firmware(bp->rv2p_firmware);
3707 bp->rv2p_firmware = NULL;
3708err_release_mips_firmware:
3709 release_firmware(bp->mips_firmware);
3710 goto out;
3711}
3712
3713static int bnx2_request_firmware(struct bnx2 *bp)
3714{
3715 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);
57579f76
MC		 3716}
3717
3718static u32
3719rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3720{
3721 switch (idx) {
3722 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3723 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3724 rv2p_code |= RV2P_BD_PAGE_SIZE;
3725 break;
3726 }
3727 return rv2p_code;
3728}
3729
3730static int
3731load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3732 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3733{
3734 u32 rv2p_code_len, file_offset;
3735 __be32 *rv2p_code;
b6016b76 3736 int i;
57579f76
MC		 3737 u32 val, cmd, addr;
3738
3739 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3740 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3741
3742 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
b6016b76 3743
57579f76
MC		 3744 if (rv2p_proc == RV2P_PROC1) {
3745 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3746 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3747 } else {
3748 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3749 addr = BNX2_RV2P_PROC2_ADDR_CMD;
d25be1d3 3750 }
b6016b76
MC		 3751
3752 for (i = 0; i < rv2p_code_len; i += 8) {
57579f76 3753 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
b6016b76 3754 rv2p_code++;
57579f76 3755 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
b6016b76
MC		 3756 rv2p_code++;
3757
57579f76
MC		 3758 val = (i / 8) | cmd;
3759 REG_WR(bp, addr, val);
3760 }
3761
3762 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3763 for (i = 0; i < 8; i++) {
3764 u32 loc, code;
3765
3766 loc = be32_to_cpu(fw_entry->fixup[i]);
3767 if (loc && ((loc * 4) < rv2p_code_len)) {
3768 code = be32_to_cpu(*(rv2p_code + loc - 1));
3769 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3770 code = be32_to_cpu(*(rv2p_code + loc));
3771 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3772 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3773
3774 val = (loc / 2) | cmd;
3775 REG_WR(bp, addr, val);
b6016b76
MC		 3776 }
3777 }
3778
3779 /* Reset the processor, un-stall is done later. */
3780 if (rv2p_proc == RV2P_PROC1) {
3781 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3782 }
3783 else {
3784 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3785 }
57579f76
MC		 3786
3787 return 0;
b6016b76
MC		 3788}
3789
af3ee519 3790static int
57579f76
MC		 3791load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3792 const struct bnx2_mips_fw_file_entry *fw_entry)
b6016b76 3793{
57579f76
MC		 3794 u32 addr, len, file_offset;
3795 __be32 *data;
b6016b76
MC		 3796 u32 offset;
3797 u32 val;
3798
3799 /* Halt the CPU. */
2726d6e1 3800 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3801 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3802 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3803 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3804
3805 /* Load the Text area. */
57579f76
MC		 3806 addr = be32_to_cpu(fw_entry->text.addr);
3807 len = be32_to_cpu(fw_entry->text.len);
3808 file_offset = be32_to_cpu(fw_entry->text.offset);
3809 data = (__be32 *)(bp->mips_firmware->data + file_offset);
ea1f8d5c 3810
57579f76
MC		 3811 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3812 if (len) {
b6016b76
MC		 3813 int j;
3814
57579f76
MC		 3815 for (j = 0; j < (len / 4); j++, offset += 4)
3816 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3817 }
3818
57579f76
MC		 3819 /* Load the Data area. */
3820 addr = be32_to_cpu(fw_entry->data.addr);
3821 len = be32_to_cpu(fw_entry->data.len);
3822 file_offset = be32_to_cpu(fw_entry->data.offset);
3823 data = (__be32 *)(bp->mips_firmware->data + file_offset);
b6016b76 3824
57579f76
MC		 3825 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3826 if (len) {
b6016b76
MC		 3827 int j;
3828
57579f76
MC		 3829 for (j = 0; j < (len / 4); j++, offset += 4)
3830 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3831 }
3832
3833 /* Load the Read-Only area. */
57579f76
MC		 3834 addr = be32_to_cpu(fw_entry->rodata.addr);
3835 len = be32_to_cpu(fw_entry->rodata.len);
3836 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3837 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3838
3839 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3840 if (len) {
b6016b76
MC		 3841 int j;
3842
57579f76
MC		 3843 for (j = 0; j < (len / 4); j++, offset += 4)
3844 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3845 }
3846
3847 /* Clear the pre-fetch instruction. */
2726d6e1 3848 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
57579f76
MC		 3849
3850 val = be32_to_cpu(fw_entry->start_addr);
3851 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
b6016b76
MC		 3852
3853 /* Start the CPU. */
2726d6e1 3854 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3855 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3856 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3857 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3858
3859 return 0;
b6016b76
MC		 3860}
3861
fba9fe91 3862static int
b6016b76
MC		 3863bnx2_init_cpus(struct bnx2 *bp)
3864{
57579f76
MC		 3865 const struct bnx2_mips_fw_file *mips_fw =
3866 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3867 const struct bnx2_rv2p_fw_file *rv2p_fw =
3868 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3869 int rc;
b6016b76
MC		 3870
3871 /* Initialize the RV2P processor. */
57579f76
MC		 3872 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3873 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
b6016b76
MC		 3874
3875 /* Initialize the RX Processor. */
57579f76 3876 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
fba9fe91
MC		 3877 if (rc)
3878 goto init_cpu_err;
3879
b6016b76 3880 /* Initialize the TX Processor. */
57579f76 3881 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
fba9fe91
MC		 3882 if (rc)
3883 goto init_cpu_err;
3884
b6016b76 3885 /* Initialize the TX Patch-up Processor. */
57579f76 3886 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
fba9fe91
MC		 3887 if (rc)
3888 goto init_cpu_err;
3889
b6016b76 3890 /* Initialize the Completion Processor. */
57579f76 3891 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
fba9fe91
MC		 3892 if (rc)
3893 goto init_cpu_err;
3894
d43584c8 3895 /* Initialize the Command Processor. */
57579f76 3896 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
b6016b76 3897
fba9fe91 3898init_cpu_err:
fba9fe91 3899 return rc;
b6016b76
MC		 3900}
3901
3902static int
829ca9a3 3903bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3904{
3905 u16 pmcsr;
3906
3907 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3908
3909 switch (state) {
829ca9a3 3910 case PCI_D0: {
b6016b76
MC		 3911 u32 val;
3912
3913 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3914 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3915 PCI_PM_CTRL_PME_STATUS);
3916
3917 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3918 /* delay required during transition out of D3hot */
3919 msleep(20);
3920
3921 val = REG_RD(bp, BNX2_EMAC_MODE);
3922 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3923 val &= ~BNX2_EMAC_MODE_MPKT;
3924 REG_WR(bp, BNX2_EMAC_MODE, val);
3925
3926 val = REG_RD(bp, BNX2_RPM_CONFIG);
3927 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3928 REG_WR(bp, BNX2_RPM_CONFIG, val);
3929 break;
3930 }
829ca9a3 3931 case PCI_D3hot: {
b6016b76
MC		 3932 int i;
3933 u32 val, wol_msg;
3934
3935 if (bp->wol) {
3936 u32 advertising;
3937 u8 autoneg;
3938
3939 autoneg = bp->autoneg;
3940 advertising = bp->advertising;
3941
239cd343
MC		 3942 if (bp->phy_port == PORT_TP) {
3943 bp->autoneg = AUTONEG_SPEED;
3944 bp->advertising = ADVERTISED_10baseT_Half |
3945 ADVERTISED_10baseT_Full |
3946 ADVERTISED_100baseT_Half |
3947 ADVERTISED_100baseT_Full |
3948 ADVERTISED_Autoneg;
3949 }
b6016b76 3950
239cd343
MC		 3951 spin_lock_bh(&bp->phy_lock);
3952 bnx2_setup_phy(bp, bp->phy_port);
3953 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3954
3955 bp->autoneg = autoneg;
3956 bp->advertising = advertising;
3957
5fcaed01 3958 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 3959
3960 val = REG_RD(bp, BNX2_EMAC_MODE);
3961
3962 /* Enable port mode. */
3963 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3964 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3965 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3966 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3967 if (bp->phy_port == PORT_TP)
3968 val |= BNX2_EMAC_MODE_PORT_MII;
3969 else {
3970 val |= BNX2_EMAC_MODE_PORT_GMII;
3971 if (bp->line_speed == SPEED_2500)
3972 val |= BNX2_EMAC_MODE_25G_MODE;
3973 }
b6016b76
MC		 3974
3975 REG_WR(bp, BNX2_EMAC_MODE, val);
3976
3977 /* receive all multicast */
3978 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3979 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3980 0xffffffff);
3981 }
3982 REG_WR(bp, BNX2_EMAC_RX_MODE,
3983 BNX2_EMAC_RX_MODE_SORT_MODE);
3984
3985 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3986 BNX2_RPM_SORT_USER0_MC_EN;
3987 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3988 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3989 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3990 BNX2_RPM_SORT_USER0_ENA);
3991
3992 /* Need to enable EMAC and RPM for WOL. */
3993 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3994 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3995 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3996 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3997
3998 val = REG_RD(bp, BNX2_RPM_CONFIG);
3999 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
4000 REG_WR(bp, BNX2_RPM_CONFIG, val);
4001
4002 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4003 }
4004 else {
4005 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4006 }
4007
f86e82fb 4008 if (!(bp->flags & BNX2_FLAG_NO_WOL))
a2f13890
MC		 4009 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
4010 1, 0);
b6016b76
MC		 4011
4012 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4013 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4014 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
4015
4016 if (bp->wol)
4017 pmcsr |= 3;
4018 }
4019 else {
4020 pmcsr |= 3;
4021 }
4022 if (bp->wol) {
4023 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
4024 }
4025 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
4026 pmcsr);
4027
4028 /* No more memory access after this point until
4029 * device is brought back to D0.
4030 */
4031 udelay(50);
4032 break;
4033 }
4034 default:
4035 return -EINVAL;
4036 }
4037 return 0;
4038}
4039
4040static int
4041bnx2_acquire_nvram_lock(struct bnx2 *bp)
4042{
4043 u32 val;
4044 int j;
4045
4046 /* Request access to the flash interface. */
4047 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4048 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4049 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4050 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4051 break;
4052
4053 udelay(5);
4054 }
4055
4056 if (j >= NVRAM_TIMEOUT_COUNT)
4057 return -EBUSY;
4058
4059 return 0;
4060}
4061
4062static int
4063bnx2_release_nvram_lock(struct bnx2 *bp)
4064{
4065 int j;
4066 u32 val;
4067
4068 /* Relinquish nvram interface. */
4069 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4070
4071 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4072 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4073 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4074 break;
4075
4076 udelay(5);
4077 }
4078
4079 if (j >= NVRAM_TIMEOUT_COUNT)
4080 return -EBUSY;
4081
4082 return 0;
4083}
4084
4085
4086static int
4087bnx2_enable_nvram_write(struct bnx2 *bp)
4088{
4089 u32 val;
4090
4091 val = REG_RD(bp, BNX2_MISC_CFG);
4092 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4093
e30372c9 4094 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 4095 int j;
4096
4097 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4098 REG_WR(bp, BNX2_NVM_COMMAND,
4099 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4100
4101 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4102 udelay(5);
4103
4104 val = REG_RD(bp, BNX2_NVM_COMMAND);
4105 if (val & BNX2_NVM_COMMAND_DONE)
4106 break;
4107 }
4108
4109 if (j >= NVRAM_TIMEOUT_COUNT)
4110 return -EBUSY;
4111 }
4112 return 0;
4113}
4114
4115static void
4116bnx2_disable_nvram_write(struct bnx2 *bp)
4117{
4118 u32 val;
4119
4120 val = REG_RD(bp, BNX2_MISC_CFG);
4121 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4122}
4123
4124
4125static void
4126bnx2_enable_nvram_access(struct bnx2 *bp)
4127{
4128 u32 val;
4129
4130 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4131 /* Enable both bits, even on read. */
6aa20a22 4132 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4133 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4134}
4135
4136static void
4137bnx2_disable_nvram_access(struct bnx2 *bp)
4138{
4139 u32 val;
4140
4141 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4142 /* Disable both bits, even after read. */
6aa20a22 4143 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4144 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4145 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4146}
4147
4148static int
4149bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4150{
4151 u32 cmd;
4152 int j;
4153
e30372c9 4154 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 4155 /* Buffered flash, no erase needed */
4156 return 0;
4157
4158 /* Build an erase command */
4159 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4160 BNX2_NVM_COMMAND_DOIT;
4161
4162 /* Need to clear DONE bit separately. */
4163 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4164
4165 /* Address of the NVRAM to read from. */
4166 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4167
4168 /* Issue an erase command. */
4169 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4170
4171 /* Wait for completion. */
4172 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4173 u32 val;
4174
4175 udelay(5);
4176
4177 val = REG_RD(bp, BNX2_NVM_COMMAND);
4178 if (val & BNX2_NVM_COMMAND_DONE)
4179 break;
4180 }
4181
4182 if (j >= NVRAM_TIMEOUT_COUNT)
4183 return -EBUSY;
4184
4185 return 0;
4186}
4187
4188static int
4189bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4190{
4191 u32 cmd;
4192 int j;
4193
4194 /* Build the command word. */
4195 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4196
e30372c9
MC		 4197 /* Calculate an offset of a buffered flash, not needed for 5709. */
4198 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4199 offset = ((offset / bp->flash_info->page_size) <<
4200 bp->flash_info->page_bits) +
4201 (offset % bp->flash_info->page_size);
4202 }
4203
4204 /* Need to clear DONE bit separately. */
4205 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4206
4207 /* Address of the NVRAM to read from. */
4208 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4209
4210 /* Issue a read command. */
4211 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4212
4213 /* Wait for completion. */
4214 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4215 u32 val;
4216
4217 udelay(5);
4218
4219 val = REG_RD(bp, BNX2_NVM_COMMAND);
4220 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 4221 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4222 memcpy(ret_val, &v, 4);
b6016b76
MC		 4223 break;
4224 }
4225 }
4226 if (j >= NVRAM_TIMEOUT_COUNT)
4227 return -EBUSY;
4228
4229 return 0;
4230}
4231
4232
4233static int
4234bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4235{
b491edd5
AV		 4236 u32 cmd;
4237 __be32 val32;
b6016b76
MC		 4238 int j;
4239
4240 /* Build the command word. */
4241 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4242
e30372c9
MC		 4243 /* Calculate an offset of a buffered flash, not needed for 5709. */
4244 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4245 offset = ((offset / bp->flash_info->page_size) <<
4246 bp->flash_info->page_bits) +
4247 (offset % bp->flash_info->page_size);
4248 }
4249
4250 /* Need to clear DONE bit separately. */
4251 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4252
4253 memcpy(&val32, val, 4);
b6016b76
MC		 4254
4255 /* Write the data. */
b491edd5 4256 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 4257
4258 /* Address of the NVRAM to write to. */
4259 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4260
4261 /* Issue the write command. */
4262 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4263
4264 /* Wait for completion. */
4265 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4266 udelay(5);
4267
4268 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4269 break;
4270 }
4271 if (j >= NVRAM_TIMEOUT_COUNT)
4272 return -EBUSY;
4273
4274 return 0;
4275}
4276
4277static int
4278bnx2_init_nvram(struct bnx2 *bp)
4279{
4280 u32 val;
e30372c9 4281 int j, entry_count, rc = 0;
0ced9d01 4282 const struct flash_spec *flash;
b6016b76 4283
e30372c9
MC		 4284 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4285 bp->flash_info = &flash_5709;
4286 goto get_flash_size;
4287 }
4288
b6016b76
MC		 4289 /* Determine the selected interface. */
4290 val = REG_RD(bp, BNX2_NVM_CFG1);
4291
ff8ac609 4292 entry_count = ARRAY_SIZE(flash_table);
b6016b76 4293
b6016b76
MC		 4294 if (val & 0x40000000) {
4295
4296 /* Flash interface has been reconfigured */
4297 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 4298 j++, flash++) {
4299 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4300 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 4301 bp->flash_info = flash;
4302 break;
4303 }
4304 }
4305 }
4306 else {
37137709 4307 u32 mask;
b6016b76
MC		 4308 /* Not yet been reconfigured */
4309
37137709
MC		 4310 if (val & (1 << 23))
4311 mask = FLASH_BACKUP_STRAP_MASK;
4312 else
4313 mask = FLASH_STRAP_MASK;
4314
b6016b76
MC		 4315 for (j = 0, flash = &flash_table[0]; j < entry_count;
4316 j++, flash++) {
4317
37137709 4318 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 4319 bp->flash_info = flash;
4320
4321 /* Request access to the flash interface. */
4322 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4323 return rc;
4324
4325 /* Enable access to flash interface */
4326 bnx2_enable_nvram_access(bp);
4327
4328 /* Reconfigure the flash interface */
4329 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4330 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4331 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4332 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4333
4334 /* Disable access to flash interface */
4335 bnx2_disable_nvram_access(bp);
4336 bnx2_release_nvram_lock(bp);
4337
4338 break;
4339 }
4340 }
4341 } /* if (val & 0x40000000) */
4342
4343 if (j == entry_count) {
4344 bp->flash_info = NULL;
3a9c6a49 4345 pr_alert("Unknown flash/EEPROM type\n");
1122db71 4346 return -ENODEV;
b6016b76
MC		 4347 }
4348
e30372c9 4349get_flash_size:
2726d6e1 4350 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 4351 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4352 if (val)
4353 bp->flash_size = val;
4354 else
4355 bp->flash_size = bp->flash_info->total_size;
4356
b6016b76
MC		 4357 return rc;
4358}
4359
4360static int
4361bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4362 int buf_size)
4363{
4364 int rc = 0;
4365 u32 cmd_flags, offset32, len32, extra;
4366
4367 if (buf_size == 0)
4368 return 0;
4369
4370 /* Request access to the flash interface. */
4371 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4372 return rc;
4373
4374 /* Enable access to flash interface */
4375 bnx2_enable_nvram_access(bp);
4376
4377 len32 = buf_size;
4378 offset32 = offset;
4379 extra = 0;
4380
4381 cmd_flags = 0;
4382
4383 if (offset32 & 3) {
4384 u8 buf[4];
4385 u32 pre_len;
4386
4387 offset32 &= ~3;
4388 pre_len = 4 - (offset & 3);
4389
4390 if (pre_len >= len32) {
4391 pre_len = len32;
4392 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4393 BNX2_NVM_COMMAND_LAST;
4394 }
4395 else {
4396 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4397 }
4398
4399 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4400
4401 if (rc)
4402 return rc;
4403
4404 memcpy(ret_buf, buf + (offset & 3), pre_len);
4405
4406 offset32 += 4;
4407 ret_buf += pre_len;
4408 len32 -= pre_len;
4409 }
4410 if (len32 & 3) {
4411 extra = 4 - (len32 & 3);
4412 len32 = (len32 + 4) & ~3;
4413 }
4414
4415 if (len32 == 4) {
4416 u8 buf[4];
4417
4418 if (cmd_flags)
4419 cmd_flags = BNX2_NVM_COMMAND_LAST;
4420 else
4421 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4422 BNX2_NVM_COMMAND_LAST;
4423
4424 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4425
4426 memcpy(ret_buf, buf, 4 - extra);
4427 }
4428 else if (len32 > 0) {
4429 u8 buf[4];
4430
4431 /* Read the first word. */
4432 if (cmd_flags)
4433 cmd_flags = 0;
4434 else
4435 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4436
4437 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4438
4439 /* Advance to the next dword. */
4440 offset32 += 4;
4441 ret_buf += 4;
4442 len32 -= 4;
4443
4444 while (len32 > 4 && rc == 0) {
4445 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4446
4447 /* Advance to the next dword. */
4448 offset32 += 4;
4449 ret_buf += 4;
4450 len32 -= 4;
4451 }
4452
4453 if (rc)
4454 return rc;
4455
4456 cmd_flags = BNX2_NVM_COMMAND_LAST;
4457 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4458
4459 memcpy(ret_buf, buf, 4 - extra);
4460 }
4461
4462 /* Disable access to flash interface */
4463 bnx2_disable_nvram_access(bp);
4464
4465 bnx2_release_nvram_lock(bp);
4466
4467 return rc;
4468}
4469
4470static int
4471bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4472 int buf_size)
4473{
4474 u32 written, offset32, len32;
e6be763f 4475 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4476 int rc = 0;
4477 int align_start, align_end;
4478
4479 buf = data_buf;
4480 offset32 = offset;
4481 len32 = buf_size;
4482 align_start = align_end = 0;
4483
4484 if ((align_start = (offset32 & 3))) {
4485 offset32 &= ~3;
c873879c
MC		 4486 len32 += align_start;
4487 if (len32 < 4)
4488 len32 = 4;
b6016b76
MC		 4489 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4490 return rc;
4491 }
4492
4493 if (len32 & 3) {
c873879c
MC		 4494 align_end = 4 - (len32 & 3);
4495 len32 += align_end;
4496 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4497 return rc;
b6016b76
MC		 4498 }
4499
4500 if (align_start || align_end) {
e6be763f
MC		 4501 align_buf = kmalloc(len32, GFP_KERNEL);
4502 if (align_buf == NULL)
b6016b76
MC		 4503 return -ENOMEM;
4504 if (align_start) {
e6be763f 4505 memcpy(align_buf, start, 4);
b6016b76
MC		 4506 }
4507 if (align_end) {
e6be763f 4508 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4509 }
e6be763f
MC		 4510 memcpy(align_buf + align_start, data_buf, buf_size);
4511 buf = align_buf;
b6016b76
MC		 4512 }
4513
e30372c9 4514 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4515 flash_buffer = kmalloc(264, GFP_KERNEL);
4516 if (flash_buffer == NULL) {
4517 rc = -ENOMEM;
4518 goto nvram_write_end;
4519 }
4520 }
4521
b6016b76
MC		 4522 written = 0;
4523 while ((written < len32) && (rc == 0)) {
4524 u32 page_start, page_end, data_start, data_end;
4525 u32 addr, cmd_flags;
4526 int i;
b6016b76
MC		 4527
4528 /* Find the page_start addr */
4529 page_start = offset32 + written;
4530 page_start -= (page_start % bp->flash_info->page_size);
4531 /* Find the page_end addr */
4532 page_end = page_start + bp->flash_info->page_size;
4533 /* Find the data_start addr */
4534 data_start = (written == 0) ? offset32 : page_start;
4535 /* Find the data_end addr */
6aa20a22 4536 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4537 (offset32 + len32) : page_end;
4538
4539 /* Request access to the flash interface. */
4540 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4541 goto nvram_write_end;
4542
4543 /* Enable access to flash interface */
4544 bnx2_enable_nvram_access(bp);
4545
4546 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4547 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4548 int j;
4549
4550 /* Read the whole page into the buffer
4551 * (non-buffer flash only) */
4552 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4553 if (j == (bp->flash_info->page_size - 4)) {
4554 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4555 }
4556 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4557 page_start + j,
4558 &flash_buffer[j],
b6016b76
MC		 4559 cmd_flags);
4560
4561 if (rc)
4562 goto nvram_write_end;
4563
4564 cmd_flags = 0;
4565 }
4566 }
4567
4568 /* Enable writes to flash interface (unlock write-protect) */
4569 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4570 goto nvram_write_end;
4571
b6016b76
MC		 4572 /* Loop to write back the buffer data from page_start to
4573 * data_start */
4574 i = 0;
e30372c9 4575 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4576 /* Erase the page */
4577 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4578 goto nvram_write_end;
4579
4580 /* Re-enable the write again for the actual write */
4581 bnx2_enable_nvram_write(bp);
4582
b6016b76
MC		 4583 for (addr = page_start; addr < data_start;
4584 addr += 4, i += 4) {
6aa20a22 4585
b6016b76
MC		 4586 rc = bnx2_nvram_write_dword(bp, addr,
4587 &flash_buffer[i], cmd_flags);
4588
4589 if (rc != 0)
4590 goto nvram_write_end;
4591
4592 cmd_flags = 0;
4593 }
4594 }
4595
4596 /* Loop to write the new data from data_start to data_end */
bae25761 4597 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4598 if ((addr == page_end - 4) ||
e30372c9 4599 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4600 (addr == data_end - 4))) {
4601
4602 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4603 }
4604 rc = bnx2_nvram_write_dword(bp, addr, buf,
4605 cmd_flags);
4606
4607 if (rc != 0)
4608 goto nvram_write_end;
4609
4610 cmd_flags = 0;
4611 buf += 4;
4612 }
4613
4614 /* Loop to write back the buffer data from data_end
4615 * to page_end */
e30372c9 4616 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4617 for (addr = data_end; addr < page_end;
4618 addr += 4, i += 4) {
6aa20a22 4619
b6016b76
MC		 4620 if (addr == page_end-4) {
4621 cmd_flags = BNX2_NVM_COMMAND_LAST;
4622 }
4623 rc = bnx2_nvram_write_dword(bp, addr,
4624 &flash_buffer[i], cmd_flags);
4625
4626 if (rc != 0)
4627 goto nvram_write_end;
4628
4629 cmd_flags = 0;
4630 }
4631 }
4632
4633 /* Disable writes to flash interface (lock write-protect) */
4634 bnx2_disable_nvram_write(bp);
4635
4636 /* Disable access to flash interface */
4637 bnx2_disable_nvram_access(bp);
4638 bnx2_release_nvram_lock(bp);
4639
4640 /* Increment written */
4641 written += data_end - data_start;
4642 }
4643
4644nvram_write_end:
e6be763f
MC		 4645 kfree(flash_buffer);
4646 kfree(align_buf);
b6016b76
MC		 4647 return rc;
4648}
4649
0d8a6571 4650static void
7c62e83b 4651bnx2_init_fw_cap(struct bnx2 *bp)
0d8a6571 4652{
7c62e83b 4653 u32 val, sig = 0;
0d8a6571 4654
583c28e5 4655 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
7c62e83b
MC		 4656 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4657
4658 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4659 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
0d8a6571 4660
2726d6e1 4661 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4662 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4663 return;
4664
7c62e83b
MC		 4665 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4666 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4667 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4668 }
4669
4670 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4671 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4672 u32 link;
4673
583c28e5 4674 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4675
7c62e83b
MC		 4676 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4677 if (link & BNX2_LINK_STATUS_SERDES_LINK)
0d8a6571
MC		 4678 bp->phy_port = PORT_FIBRE;
4679 else
4680 bp->phy_port = PORT_TP;
489310a4 4681
7c62e83b
MC		 4682 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4683 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
0d8a6571 4684 }
7c62e83b
MC		 4685
4686 if (netif_running(bp->dev) && sig)
4687 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
0d8a6571
MC		 4688}
4689
b4b36042
MC		 4690static void
4691bnx2_setup_msix_tbl(struct bnx2 *bp)
4692{
4693 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4694
4695 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4696 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4697}
4698
b6016b76
MC		 4699static int
4700bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4701{
4702 u32 val;
4703 int i, rc = 0;
489310a4 4704 u8 old_port;
b6016b76
MC		 4705
4706 /* Wait for the current PCI transaction to complete before
4707 * issuing a reset. */
a5dac108
EW		 4708 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4709 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
4710 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4711 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4712 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4713 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4714 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4715 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4716 udelay(5);
4717 } else { /* 5709 */
4718 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4719 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4720 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4721 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4722
4723 for (i = 0; i < 100; i++) {
4724 msleep(1);
4725 val = REG_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4726 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4727 break;
4728 }
4729 }
b6016b76 4730
b090ae2b 4731 /* Wait for the firmware to tell us it is ok to issue a reset. */
a2f13890 4732 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
b090ae2b 4733
b6016b76
MC		 4734 /* Deposit a driver reset signature so the firmware knows that
4735 * this is a soft reset. */
2726d6e1
MC		 4736 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4737 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4738
b6016b76
MC		 4739 /* Do a dummy read to force the chip to complete all current transaction
4740 * before we issue a reset. */
4741 val = REG_RD(bp, BNX2_MISC_ID);
4742
234754d5
MC		 4743 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4744 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4745 REG_RD(bp, BNX2_MISC_COMMAND);
4746 udelay(5);
b6016b76 4747
234754d5
MC		 4748 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4749 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4750
be7ff1af 4751 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4752
234754d5
MC		 4753 } else {
4754 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4755 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4756 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4757
4758 /* Chip reset. */
4759 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4760
594a9dfa
MC		 4761 /* Reading back any register after chip reset will hang the
4762 * bus on 5706 A0 and A1. The msleep below provides plenty
4763 * of margin for write posting.
4764 */
234754d5 4765 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4766 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4767 msleep(20);
b6016b76 4768
234754d5
MC		 4769 /* Reset takes approximate 30 usec */
4770 for (i = 0; i < 10; i++) {
4771 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4772 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4773 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4774 break;
4775 udelay(10);
4776 }
4777
4778 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4779 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3a9c6a49 4780 pr_err("Chip reset did not complete\n");
234754d5
MC		 4781 return -EBUSY;
4782 }
b6016b76
MC		 4783 }
4784
4785 /* Make sure byte swapping is properly configured. */
4786 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4787 if (val != 0x01020304) {
3a9c6a49 4788 pr_err("Chip not in correct endian mode\n");
b6016b76
MC		 4789 return -ENODEV;
4790 }
4791
b6016b76 4792 /* Wait for the firmware to finish its initialization. */
a2f13890 4793 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
b090ae2b
MC		 4794 if (rc)
4795 return rc;
b6016b76 4796
0d8a6571 4797 spin_lock_bh(&bp->phy_lock);
489310a4 4798 old_port = bp->phy_port;
7c62e83b 4799 bnx2_init_fw_cap(bp);
583c28e5
MC		 4800 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4801 old_port != bp->phy_port)
0d8a6571
MC		 4802 bnx2_set_default_remote_link(bp);
4803 spin_unlock_bh(&bp->phy_lock);
4804
b6016b76
MC		 4805 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4806 /* Adjust the voltage regular to two steps lower. The default
4807 * of this register is 0x0000000e. */
4808 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4809
4810 /* Remove bad rbuf memory from the free pool. */
4811 rc = bnx2_alloc_bad_rbuf(bp);
4812 }
4813
c441b8d2 4814 if (bp->flags & BNX2_FLAG_USING_MSIX) {
b4b36042 4815 bnx2_setup_msix_tbl(bp);
c441b8d2
MC		 4816 /* Prevent MSIX table reads and write from timing out */
4817 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4818 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4819 }
b4b36042 4820
b6016b76
MC		 4821 return rc;
4822}
4823
4824static int
4825bnx2_init_chip(struct bnx2 *bp)
4826{
d8026d93 4827 u32 val, mtu;
b4b36042 4828 int rc, i;
b6016b76
MC		 4829
4830 /* Make sure the interrupt is not active. */
4831 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4832
4833 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4834 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4835#ifdef __BIG_ENDIAN
6aa20a22 4836 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4837#endif
6aa20a22 4838 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4839 DMA_READ_CHANS << 12 |
4840 DMA_WRITE_CHANS << 16;
4841
4842 val |= (0x2 << 20) | (1 << 11);
4843
f86e82fb 4844 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4845 val |= (1 << 23);
4846
4847 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4848 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4849 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4850
4851 REG_WR(bp, BNX2_DMA_CONFIG, val);
4852
4853 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4854 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4855 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4856 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4857 }
4858
f86e82fb 4859 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4860 u16 val16;
4861
4862 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4863 &val16);
4864 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4865 val16 & ~PCI_X_CMD_ERO);
4866 }
4867
4868 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4869 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4870 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4871 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4872
4873 /* Initialize context mapping and zero out the quick contexts. The
4874 * context block must have already been enabled. */
641bdcd5
MC		 4875 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4876 rc = bnx2_init_5709_context(bp);
4877 if (rc)
4878 return rc;
4879 } else
59b47d8a 4880 bnx2_init_context(bp);
b6016b76 4881
fba9fe91
MC		 4882 if ((rc = bnx2_init_cpus(bp)) != 0)
4883 return rc;
4884
b6016b76
MC		 4885 bnx2_init_nvram(bp);
4886
5fcaed01 4887 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 4888
4889 val = REG_RD(bp, BNX2_MQ_CONFIG);
4890 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4891 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4edd473f
MC		 4892 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4893 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4894 if (CHIP_REV(bp) == CHIP_REV_Ax)
4895 val |= BNX2_MQ_CONFIG_HALT_DIS;
4896 }
68c9f75a 4897
b6016b76
MC		 4898 REG_WR(bp, BNX2_MQ_CONFIG, val);
4899
4900 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4901 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4902 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4903
4904 val = (BCM_PAGE_BITS - 8) << 24;
4905 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4906
4907 /* Configure page size. */
4908 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4909 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4910 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4911 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4912
4913 val = bp->mac_addr[0] +
4914 (bp->mac_addr[1] << 8) +
4915 (bp->mac_addr[2] << 16) +
4916 bp->mac_addr[3] +
4917 (bp->mac_addr[4] << 8) +
4918 (bp->mac_addr[5] << 16);
4919 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4920
4921 /* Program the MTU. Also include 4 bytes for CRC32. */
d8026d93
MC		 4922 mtu = bp->dev->mtu;
4923 val = mtu + ETH_HLEN + ETH_FCS_LEN;
b6016b76
MC		 4924 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4925 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4926 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4927
d8026d93
MC		 4928 if (mtu < 1500)
4929 mtu = 1500;
4930
4931 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4932 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4933 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4934
155d5561 4935 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
b4b36042
MC		 4936 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4937 bp->bnx2_napi[i].last_status_idx = 0;
4938
efba0180
MC		 4939 bp->idle_chk_status_idx = 0xffff;
4940
b6016b76
MC		 4941 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4942
4943 /* Set up how to generate a link change interrupt. */
4944 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4945
4946 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4947 (u64) bp->status_blk_mapping & 0xffffffff);
4948 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4949
4950 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4951 (u64) bp->stats_blk_mapping & 0xffffffff);
4952 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4953 (u64) bp->stats_blk_mapping >> 32);
4954
6aa20a22 4955 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4956 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4957
4958 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4959 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4960
4961 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4962 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4963
4964 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4965
4966 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4967
4968 REG_WR(bp, BNX2_HC_COM_TICKS,
4969 (bp->com_ticks_int << 16) | bp->com_ticks);
4970
4971 REG_WR(bp, BNX2_HC_CMD_TICKS,
4972 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4973
61d9e3fa 4974 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
02537b06
MC		 4975 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4976 else
7ea6920e 4977 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4978 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4979
4980 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4981 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4982 else {
8e6a72c4
MC		 4983 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4984 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4985 }
4986
efde73a3 4987 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4988 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4989 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4990
5e9ad9e1
MC		 4991 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4992 }
4993
4994 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
cf7474a6 4995 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5e9ad9e1
MC		 4996
4997 REG_WR(bp, BNX2_HC_CONFIG, val);
4998
22fa159d
MC		 4999 if (bp->rx_ticks < 25)
5000 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
5001 else
5002 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
5003
5e9ad9e1
MC		 5004 for (i = 1; i < bp->irq_nvecs; i++) {
5005 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
5006 BNX2_HC_SB_CONFIG_1;
5007
6f743ca0 5008 REG_WR(bp, base,
c76c0475 5009 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5e9ad9e1 5010 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
c76c0475
MC		 5011 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
5012
6f743ca0 5013 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 5014 (bp->tx_quick_cons_trip_int << 16) |
5015 bp->tx_quick_cons_trip);
5016
6f743ca0 5017 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 5018 (bp->tx_ticks_int << 16) | bp->tx_ticks);
5019
5e9ad9e1
MC		 5020 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5021 (bp->rx_quick_cons_trip_int << 16) |
5022 bp->rx_quick_cons_trip);
8e6a72c4 5023
5e9ad9e1
MC		 5024 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
5025 (bp->rx_ticks_int << 16) | bp->rx_ticks);
5026 }
8e6a72c4 5027
b6016b76
MC		 5028 /* Clear internal stats counters. */
5029 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
5030
da3e4fbe 5031 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 5032
5033 /* Initialize the receive filter. */
5034 bnx2_set_rx_mode(bp->dev);
5035
0aa38df7
MC		 5036 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5037 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5038 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5039 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5040 }
b090ae2b 5041 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
a2f13890 5042 1, 0);
b6016b76 5043
df149d70 5044 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 5045 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5046
5047 udelay(20);
5048
bf5295bb
MC		 5049 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5050
b090ae2b 5051 return rc;
b6016b76
MC		 5052}
5053
c76c0475
MC		 5054static void
5055bnx2_clear_ring_states(struct bnx2 *bp)
5056{
5057 struct bnx2_napi *bnapi;
35e9010b 5058 struct bnx2_tx_ring_info *txr;
bb4f98ab 5059 struct bnx2_rx_ring_info *rxr;
c76c0475
MC		 5060 int i;
5061
5062 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5063 bnapi = &bp->bnx2_napi[i];
35e9010b 5064 txr = &bnapi->tx_ring;
bb4f98ab 5065 rxr = &bnapi->rx_ring;
c76c0475 5066
35e9010b
MC		 5067 txr->tx_cons = 0;
5068 txr->hw_tx_cons = 0;
bb4f98ab
MC		 5069 rxr->rx_prod_bseq = 0;
5070 rxr->rx_prod = 0;
5071 rxr->rx_cons = 0;
5072 rxr->rx_pg_prod = 0;
5073 rxr->rx_pg_cons = 0;
c76c0475
MC		 5074 }
5075}
5076
59b47d8a 5077static void
35e9010b 5078bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
59b47d8a
MC		 5079{
5080 u32 val, offset0, offset1, offset2, offset3;
62a8313c 5081 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 5082
5083 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5084 offset0 = BNX2_L2CTX_TYPE_XI;
5085 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5086 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5087 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5088 } else {
5089 offset0 = BNX2_L2CTX_TYPE;
5090 offset1 = BNX2_L2CTX_CMD_TYPE;
5091 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5092 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5093 }
5094 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 5095 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 5096
5097 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 5098 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a 5099
35e9010b 5100 val = (u64) txr->tx_desc_mapping >> 32;
62a8313c 5101 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a 5102
35e9010b 5103 val = (u64) txr->tx_desc_mapping & 0xffffffff;
62a8313c 5104 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 5105}
b6016b76
MC		 5106
5107static void
35e9010b 5108bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
b6016b76
MC		 5109{
5110 struct tx_bd *txbd;
c76c0475
MC		 5111 u32 cid = TX_CID;
5112 struct bnx2_napi *bnapi;
35e9010b 5113 struct bnx2_tx_ring_info *txr;
c76c0475 5114
35e9010b
MC		 5115 bnapi = &bp->bnx2_napi[ring_num];
5116 txr = &bnapi->tx_ring;
5117
5118 if (ring_num == 0)
5119 cid = TX_CID;
5120 else
5121 cid = TX_TSS_CID + ring_num - 1;
b6016b76 5122
2f8af120
MC		 5123 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5124
35e9010b 5125 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 5126
35e9010b
MC		 5127 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5128 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
b6016b76 5129
35e9010b
MC		 5130 txr->tx_prod = 0;
5131 txr->tx_prod_bseq = 0;
6aa20a22 5132
35e9010b
MC		 5133 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5134 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 5135
35e9010b 5136 bnx2_init_tx_context(bp, cid, txr);
b6016b76
MC		 5137}
5138
5139static void
5d5d0015
MC		 5140bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5141 int num_rings)
b6016b76 5142{
b6016b76 5143 int i;
5d5d0015 5144 struct rx_bd *rxbd;
6aa20a22 5145
5d5d0015 5146 for (i = 0; i < num_rings; i++) {
13daffa2 5147 int j;
b6016b76 5148
5d5d0015 5149 rxbd = &rx_ring[i][0];
13daffa2 5150 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 5151 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 5152 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5153 }
5d5d0015 5154 if (i == (num_rings - 1))
13daffa2
MC		 5155 j = 0;
5156 else
5157 j = i + 1;
5d5d0015
MC		 5158 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5159 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 5160 }
5d5d0015
MC		 5161}
5162
5163static void
bb4f98ab 5164bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5d5d0015
MC		 5165{
5166 int i;
5167 u16 prod, ring_prod;
bb4f98ab
MC		 5168 u32 cid, rx_cid_addr, val;
5169 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5170 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5171
5172 if (ring_num == 0)
5173 cid = RX_CID;
5174 else
5175 cid = RX_RSS_CID + ring_num - 1;
5176
5177 rx_cid_addr = GET_CID_ADDR(cid);
5d5d0015 5178
bb4f98ab 5179 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5d5d0015
MC		 5180 bp->rx_buf_use_size, bp->rx_max_ring);
5181
bb4f98ab 5182 bnx2_init_rx_context(bp, cid);
83e3fc89
MC		 5183
5184 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5185 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5186 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5187 }
5188
62a8313c 5189 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246 5190 if (bp->rx_pg_ring_size) {
bb4f98ab
MC		 5191 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5192 rxr->rx_pg_desc_mapping,
47bf4246
MC		 5193 PAGE_SIZE, bp->rx_max_pg_ring);
5194 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 5195 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5196 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5e9ad9e1 5197 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
47bf4246 5198
bb4f98ab 5199 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
62a8313c 5200 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246 5201
bb4f98ab 5202 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 5203 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 5204
5205 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5206 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5207 }
b6016b76 5208
bb4f98ab 5209 val = (u64) rxr->rx_desc_mapping[0] >> 32;
62a8313c 5210 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 5211
bb4f98ab 5212 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
62a8313c 5213 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 5214
bb4f98ab 5215 ring_prod = prod = rxr->rx_pg_prod;
47bf4246 5216 for (i = 0; i < bp->rx_pg_ring_size; i++) {
a2df00aa 5217 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5218 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5219 ring_num, i, bp->rx_pg_ring_size);
47bf4246 5220 break;
b929e53c 5221 }
47bf4246
MC		 5222 prod = NEXT_RX_BD(prod);
5223 ring_prod = RX_PG_RING_IDX(prod);
5224 }
bb4f98ab 5225 rxr->rx_pg_prod = prod;
47bf4246 5226
bb4f98ab 5227 ring_prod = prod = rxr->rx_prod;
236b6394 5228 for (i = 0; i < bp->rx_ring_size; i++) {
dd2bc8e9 5229 if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5230 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5231 ring_num, i, bp->rx_ring_size);
b6016b76 5232 break;
b929e53c 5233 }
b6016b76
MC		 5234 prod = NEXT_RX_BD(prod);
5235 ring_prod = RX_RING_IDX(prod);
5236 }
bb4f98ab 5237 rxr->rx_prod = prod;
b6016b76 5238
bb4f98ab
MC		 5239 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5240 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5241 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
b6016b76 5242
bb4f98ab
MC		 5243 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5244 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5245
5246 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 5247}
5248
35e9010b
MC		 5249static void
5250bnx2_init_all_rings(struct bnx2 *bp)
5251{
5252 int i;
5e9ad9e1 5253 u32 val;
35e9010b
MC		 5254
5255 bnx2_clear_ring_states(bp);
5256
5257 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5258 for (i = 0; i < bp->num_tx_rings; i++)
5259 bnx2_init_tx_ring(bp, i);
5260
5261 if (bp->num_tx_rings > 1)
5262 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5263 (TX_TSS_CID << 7));
5264
5e9ad9e1
MC		 5265 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5266 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5267
bb4f98ab
MC		 5268 for (i = 0; i < bp->num_rx_rings; i++)
5269 bnx2_init_rx_ring(bp, i);
5e9ad9e1
MC		 5270
5271 if (bp->num_rx_rings > 1) {
22fa159d 5272 u32 tbl_32 = 0;
5e9ad9e1
MC		 5273
5274 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
22fa159d
MC		 5275 int shift = (i % 8) << 2;
5276
5277 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
5278 if ((i % 8) == 7) {
5279 REG_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5280 REG_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
5281 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
5282 BNX2_RLUP_RSS_COMMAND_WRITE |
5283 BNX2_RLUP_RSS_COMMAND_HASH_MASK);
5284 tbl_32 = 0;
5285 }
5e9ad9e1
MC		 5286 }
5287
5288 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5289 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5290
5291 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5292
5293 }
35e9010b
MC		 5294}
5295
5d5d0015 5296static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 5297{
5d5d0015 5298 u32 max, num_rings = 1;
13daffa2 5299
5d5d0015
MC		 5300 while (ring_size > MAX_RX_DESC_CNT) {
5301 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 5302 num_rings++;
5303 }
5304 /* round to next power of 2 */
5d5d0015 5305 max = max_size;
13daffa2
MC		 5306 while ((max & num_rings) == 0)
5307 max >>= 1;
5308
5309 if (num_rings != max)
5310 max <<= 1;
5311
5d5d0015
MC		 5312 return max;
5313}
5314
5315static void
5316bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5317{
84eaa187 5318 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 5319
5320 /* 8 for CRC and VLAN */
d89cb6af 5321 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 5322
84eaa187 5323 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
dd2bc8e9 5324 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
84eaa187 5325
601d3d18 5326 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 5327 bp->rx_pg_ring_size = 0;
5328 bp->rx_max_pg_ring = 0;
5329 bp->rx_max_pg_ring_idx = 0;
f86e82fb 5330 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 5331 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5332
5333 jumbo_size = size * pages;
5334 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5335 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5336
5337 bp->rx_pg_ring_size = jumbo_size;
5338 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5339 MAX_RX_PG_RINGS);
5340 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
601d3d18 5341 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 5342 bp->rx_copy_thresh = 0;
5343 }
5d5d0015
MC		 5344
5345 bp->rx_buf_use_size = rx_size;
dd2bc8e9
ED		 5346 /* hw alignment + build_skb() overhead*/
5347 bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +
5348 NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
d89cb6af 5349 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015
MC		 5350 bp->rx_ring_size = size;
5351 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 5352 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5353}
5354
b6016b76
MC		 5355static void
5356bnx2_free_tx_skbs(struct bnx2 *bp)
5357{
5358 int i;
5359
35e9010b
MC		 5360 for (i = 0; i < bp->num_tx_rings; i++) {
5361 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5362 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5363 int j;
b6016b76 5364
35e9010b 5365 if (txr->tx_buf_ring == NULL)
b6016b76 5366 continue;
b6016b76 5367
35e9010b 5368 for (j = 0; j < TX_DESC_CNT; ) {
3d16af86 5369 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
35e9010b 5370 struct sk_buff *skb = tx_buf->skb;
e95524a7 5371 int k, last;
35e9010b
MC		 5372
5373 if (skb == NULL) {
5374 j++;
5375 continue;
5376 }
5377
36227e88 5378 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5379 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5380 skb_headlen(skb),
5381 PCI_DMA_TODEVICE);
b6016b76 5382
35e9010b 5383 tx_buf->skb = NULL;
b6016b76 5384
e95524a7
AD		 5385 last = tx_buf->nr_frags;
5386 j++;
5387 for (k = 0; k < last; k++, j++) {
5388 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
36227e88 5389 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 5390 dma_unmap_addr(tx_buf, mapping),
9e903e08 5391 skb_frag_size(&skb_shinfo(skb)->frags[k]),
e95524a7
AD		 5392 PCI_DMA_TODEVICE);
5393 }
35e9010b 5394 dev_kfree_skb(skb);
b6016b76 5395 }
b6016b76 5396 }
b6016b76
MC		 5397}
5398
5399static void
5400bnx2_free_rx_skbs(struct bnx2 *bp)
5401{
5402 int i;
5403
bb4f98ab
MC		 5404 for (i = 0; i < bp->num_rx_rings; i++) {
5405 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5406 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5407 int j;
b6016b76 5408
bb4f98ab
MC		 5409 if (rxr->rx_buf_ring == NULL)
5410 return;
b6016b76 5411
bb4f98ab
MC		 5412 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5413 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
dd2bc8e9 5414 u8 *data = rx_buf->data;
b6016b76 5415
dd2bc8e9 5416 if (data == NULL)
bb4f98ab 5417 continue;
b6016b76 5418
36227e88 5419 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5420 dma_unmap_addr(rx_buf, mapping),
bb4f98ab
MC		 5421 bp->rx_buf_use_size,
5422 PCI_DMA_FROMDEVICE);
b6016b76 5423
dd2bc8e9 5424 rx_buf->data = NULL;
bb4f98ab 5425
dd2bc8e9 5426 kfree(data);
bb4f98ab
MC		 5427 }
5428 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5429 bnx2_free_rx_page(bp, rxr, j);
b6016b76
MC		 5430 }
5431}
5432
5433static void
5434bnx2_free_skbs(struct bnx2 *bp)
5435{
5436 bnx2_free_tx_skbs(bp);
5437 bnx2_free_rx_skbs(bp);
5438}
5439
5440static int
5441bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5442{
5443 int rc;
5444
5445 rc = bnx2_reset_chip(bp, reset_code);
5446 bnx2_free_skbs(bp);
5447 if (rc)
5448 return rc;
5449
fba9fe91
MC		 5450 if ((rc = bnx2_init_chip(bp)) != 0)
5451 return rc;
5452
35e9010b 5453 bnx2_init_all_rings(bp);
b6016b76
MC		 5454 return 0;
5455}
5456
5457static int
9a120bc5 5458bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 5459{
5460 int rc;
5461
5462 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5463 return rc;
5464
80be4434 5465 spin_lock_bh(&bp->phy_lock);
9a120bc5 5466 bnx2_init_phy(bp, reset_phy);
b6016b76 5467 bnx2_set_link(bp);
543a827d
MC		 5468 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5469 bnx2_remote_phy_event(bp);
0d8a6571 5470 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5471 return 0;
5472}
5473
74bf4ba3
MC		 5474static int
5475bnx2_shutdown_chip(struct bnx2 *bp)
5476{
5477 u32 reset_code;
5478
5479 if (bp->flags & BNX2_FLAG_NO_WOL)
5480 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5481 else if (bp->wol)
5482 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5483 else
5484 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5485
5486 return bnx2_reset_chip(bp, reset_code);
5487}
5488
b6016b76
MC		 5489static int
5490bnx2_test_registers(struct bnx2 *bp)
5491{
5492 int ret;
5bae30c9 5493 int i, is_5709;
f71e1309 5494 static const struct {
b6016b76
MC		 5495 u16 offset;
5496 u16 flags;
5bae30c9 5497#define BNX2_FL_NOT_5709 1
b6016b76
MC		 5498 u32 rw_mask;
5499 u32 ro_mask;
5500 } reg_tbl[] = {
5501 { 0x006c, 0, 0x00000000, 0x0000003f },
5502 { 0x0090, 0, 0xffffffff, 0x00000000 },
5503 { 0x0094, 0, 0x00000000, 0x00000000 },
5504
5bae30c9
MC		 5505 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5506 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5507 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5508 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5509 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5510 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5511 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5512 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5513 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5514
5515 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5516 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5517 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5518 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5519 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5520 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5521
5522 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5523 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5524 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 5525
5526 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 5527 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 5528
5529 { 0x1408, 0, 0x01c00800, 0x00000000 },
5530 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5531 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 5532 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 5533 { 0x14b0, 0, 0x00000002, 0x00000001 },
5534 { 0x14b8, 0, 0x00000000, 0x00000000 },
5535 { 0x14c0, 0, 0x00000000, 0x00000009 },
5536 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5537 { 0x14cc, 0, 0x00000000, 0x00000001 },
5538 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 5539
5540 { 0x1800, 0, 0x00000000, 0x00000001 },
5541 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 5542
5543 { 0x2800, 0, 0x00000000, 0x00000001 },
5544 { 0x2804, 0, 0x00000000, 0x00003f01 },
5545 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5546 { 0x2810, 0, 0xffff0000, 0x00000000 },
5547 { 0x2814, 0, 0xffff0000, 0x00000000 },
5548 { 0x2818, 0, 0xffff0000, 0x00000000 },
5549 { 0x281c, 0, 0xffff0000, 0x00000000 },
5550 { 0x2834, 0, 0xffffffff, 0x00000000 },
5551 { 0x2840, 0, 0x00000000, 0xffffffff },
5552 { 0x2844, 0, 0x00000000, 0xffffffff },
5553 { 0x2848, 0, 0xffffffff, 0x00000000 },
5554 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5555
5556 { 0x2c00, 0, 0x00000000, 0x00000011 },
5557 { 0x2c04, 0, 0x00000000, 0x00030007 },
5558
b6016b76
MC		 5559 { 0x3c00, 0, 0x00000000, 0x00000001 },
5560 { 0x3c04, 0, 0x00000000, 0x00070000 },
5561 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5562 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5563 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5564 { 0x3c14, 0, 0x00000000, 0xffffffff },
5565 { 0x3c18, 0, 0x00000000, 0xffffffff },
5566 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5567 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 5568
5569 { 0x5004, 0, 0x00000000, 0x0000007f },
5570 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 5571
b6016b76
MC		 5572 { 0x5c00, 0, 0x00000000, 0x00000001 },
5573 { 0x5c04, 0, 0x00000000, 0x0003000f },
5574 { 0x5c08, 0, 0x00000003, 0x00000000 },
5575 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5576 { 0x5c10, 0, 0x00000000, 0xffffffff },
5577 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5578 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5579 { 0x5c88, 0, 0x00000000, 0x00077373 },
5580 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5581
5582 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5583 { 0x680c, 0, 0xffffffff, 0x00000000 },
5584 { 0x6810, 0, 0xffffffff, 0x00000000 },
5585 { 0x6814, 0, 0xffffffff, 0x00000000 },
5586 { 0x6818, 0, 0xffffffff, 0x00000000 },
5587 { 0x681c, 0, 0xffffffff, 0x00000000 },
5588 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5589 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5590 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5591 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5592 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5593 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5594 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5595 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5596 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5597 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5598 { 0x684c, 0, 0xffffffff, 0x00000000 },
5599 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5600 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5601 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5602 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5603 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5604 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5605
5606 { 0xffff, 0, 0x00000000, 0x00000000 },
5607 };
5608
5609 ret = 0;
5bae30c9
MC		 5610 is_5709 = 0;
5611 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5612 is_5709 = 1;
5613
b6016b76
MC		 5614 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5615 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5616 u16 flags = reg_tbl[i].flags;
5617
5618 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5619 continue;
b6016b76
MC		 5620
5621 offset = (u32) reg_tbl[i].offset;
5622 rw_mask = reg_tbl[i].rw_mask;
5623 ro_mask = reg_tbl[i].ro_mask;
5624
14ab9b86 5625 save_val = readl(bp->regview + offset);
b6016b76 5626
14ab9b86 5627 writel(0, bp->regview + offset);
b6016b76 5628
14ab9b86 5629 val = readl(bp->regview + offset);
b6016b76
MC		 5630 if ((val & rw_mask) != 0) {
5631 goto reg_test_err;
5632 }
5633
5634 if ((val & ro_mask) != (save_val & ro_mask)) {
5635 goto reg_test_err;
5636 }
5637
14ab9b86 5638 writel(0xffffffff, bp->regview + offset);
b6016b76 5639
14ab9b86 5640 val = readl(bp->regview + offset);
b6016b76
MC		 5641 if ((val & rw_mask) != rw_mask) {
5642 goto reg_test_err;
5643 }
5644
5645 if ((val & ro_mask) != (save_val & ro_mask)) {
5646 goto reg_test_err;
5647 }
5648
14ab9b86 5649 writel(save_val, bp->regview + offset);
b6016b76
MC		 5650 continue;
5651
5652reg_test_err:
14ab9b86 5653 writel(save_val, bp->regview + offset);
b6016b76
MC		 5654 ret = -ENODEV;
5655 break;
5656 }
5657 return ret;
5658}
5659
5660static int
5661bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5662{
f71e1309 5663 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5664 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5665 int i;
5666
5667 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5668 u32 offset;
5669
5670 for (offset = 0; offset < size; offset += 4) {
5671
2726d6e1 5672 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5673
2726d6e1 5674 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5675 test_pattern[i]) {
5676 return -ENODEV;
5677 }
5678 }
5679 }
5680 return 0;
5681}
5682
5683static int
5684bnx2_test_memory(struct bnx2 *bp)
5685{
5686 int ret = 0;
5687 int i;
5bae30c9 5688 static struct mem_entry {
b6016b76
MC		 5689 u32 offset;
5690 u32 len;
5bae30c9 5691 } mem_tbl_5706[] = {
b6016b76 5692 { 0x60000, 0x4000 },
5b0c76ad 5693 { 0xa0000, 0x3000 },
b6016b76
MC		 5694 { 0xe0000, 0x4000 },
5695 { 0x120000, 0x4000 },
5696 { 0x1a0000, 0x4000 },
5697 { 0x160000, 0x4000 },
5698 { 0xffffffff, 0 },
5bae30c9
MC		 5699 },
5700 mem_tbl_5709[] = {
5701 { 0x60000, 0x4000 },
5702 { 0xa0000, 0x3000 },
5703 { 0xe0000, 0x4000 },
5704 { 0x120000, 0x4000 },
5705 { 0x1a0000, 0x4000 },
5706 { 0xffffffff, 0 },
b6016b76 5707 };
5bae30c9
MC		 5708 struct mem_entry *mem_tbl;
5709
5710 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5711 mem_tbl = mem_tbl_5709;
5712 else
5713 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5714
5715 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5716 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5717 mem_tbl[i].len)) != 0) {
5718 return ret;
5719 }
5720 }
6aa20a22 5721
b6016b76
MC		 5722 return ret;
5723}
5724
bc5a0690
MC		 5725#define BNX2_MAC_LOOPBACK 0
5726#define BNX2_PHY_LOOPBACK 1
5727
b6016b76 5728static int
bc5a0690 5729bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5730{
5731 unsigned int pkt_size, num_pkts, i;
dd2bc8e9
ED		 5732 struct sk_buff *skb;
5733 u8 *data;
b6016b76 5734 unsigned char *packet;
bc5a0690 5735 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5736 dma_addr_t map;
5737 struct tx_bd *txbd;
5738 struct sw_bd *rx_buf;
5739 struct l2_fhdr *rx_hdr;
5740 int ret = -ENODEV;
c76c0475 5741 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
35e9010b 5742 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 5743 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
c76c0475
MC		 5744
5745 tx_napi = bnapi;
b6016b76 5746
35e9010b 5747 txr = &tx_napi->tx_ring;
bb4f98ab 5748 rxr = &bnapi->rx_ring;
bc5a0690
MC		 5749 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5750 bp->loopback = MAC_LOOPBACK;
5751 bnx2_set_mac_loopback(bp);
5752 }
5753 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5754 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5755 return 0;
5756
80be4434 5757 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5758 bnx2_set_phy_loopback(bp);
5759 }
5760 else
5761 return -EINVAL;
b6016b76 5762
84eaa187 5763 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5764 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5765 if (!skb)
5766 return -ENOMEM;
b6016b76 5767 packet = skb_put(skb, pkt_size);
6634292b 5768 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5769 memset(packet + 6, 0x0, 8);
5770 for (i = 14; i < pkt_size; i++)
5771 packet[i] = (unsigned char) (i & 0xff);
5772
36227e88
SG		 5773 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5774 PCI_DMA_TODEVICE);
5775 if (dma_mapping_error(&bp->pdev->dev, map)) {
3d16af86
BL		 5776 dev_kfree_skb(skb);
5777 return -EIO;
5778 }
b6016b76 5779
bf5295bb
MC		 5780 REG_WR(bp, BNX2_HC_COMMAND,
5781 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5782
b6016b76
MC		 5783 REG_RD(bp, BNX2_HC_COMMAND);
5784
5785 udelay(5);
35efa7c1 5786 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5787
b6016b76
MC		 5788 num_pkts = 0;
5789
35e9010b 5790 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
b6016b76
MC		 5791
5792 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5793 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5794 txbd->tx_bd_mss_nbytes = pkt_size;
5795 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5796
5797 num_pkts++;
35e9010b
MC		 5798 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5799 txr->tx_prod_bseq += pkt_size;
b6016b76 5800
35e9010b
MC		 5801 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5802 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 5803
5804 udelay(100);
5805
bf5295bb
MC		 5806 REG_WR(bp, BNX2_HC_COMMAND,
5807 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5808
b6016b76
MC		 5809 REG_RD(bp, BNX2_HC_COMMAND);
5810
5811 udelay(5);
5812
36227e88 5813 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5814 dev_kfree_skb(skb);
b6016b76 5815
35e9010b 5816 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
b6016b76 5817 goto loopback_test_done;
b6016b76 5818
35efa7c1 5819 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5820 if (rx_idx != rx_start_idx + num_pkts) {
5821 goto loopback_test_done;
5822 }
5823
bb4f98ab 5824 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
dd2bc8e9 5825 data = rx_buf->data;
b6016b76 5826
dd2bc8e9
ED		 5827 rx_hdr = get_l2_fhdr(data);
5828 data = (u8 *)rx_hdr + BNX2_RX_OFFSET;
b6016b76 5829
36227e88 5830 dma_sync_single_for_cpu(&bp->pdev->dev,
1a4ccc2d 5831 dma_unmap_addr(rx_buf, mapping),
dd2bc8e9 5832 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
b6016b76 5833
ade2bfe7 5834 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5835 (L2_FHDR_ERRORS_BAD_CRC |
5836 L2_FHDR_ERRORS_PHY_DECODE |
5837 L2_FHDR_ERRORS_ALIGNMENT |
5838 L2_FHDR_ERRORS_TOO_SHORT |
5839 L2_FHDR_ERRORS_GIANT_FRAME)) {
5840
5841 goto loopback_test_done;
5842 }
5843
5844 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5845 goto loopback_test_done;
5846 }
5847
5848 for (i = 14; i < pkt_size; i++) {
dd2bc8e9 5849 if (*(data + i) != (unsigned char) (i & 0xff)) {
b6016b76
MC		 5850 goto loopback_test_done;
5851 }
5852 }
5853
5854 ret = 0;
5855
5856loopback_test_done:
5857 bp->loopback = 0;
5858 return ret;
5859}
5860
bc5a0690
MC		 5861#define BNX2_MAC_LOOPBACK_FAILED 1
5862#define BNX2_PHY_LOOPBACK_FAILED 2
5863#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5864 BNX2_PHY_LOOPBACK_FAILED)
5865
5866static int
5867bnx2_test_loopback(struct bnx2 *bp)
5868{
5869 int rc = 0;
5870
5871 if (!netif_running(bp->dev))
5872 return BNX2_LOOPBACK_FAILED;
5873
5874 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5875 spin_lock_bh(&bp->phy_lock);
9a120bc5 5876 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5877 spin_unlock_bh(&bp->phy_lock);
5878 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5879 rc |= BNX2_MAC_LOOPBACK_FAILED;
5880 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5881 rc |= BNX2_PHY_LOOPBACK_FAILED;
5882 return rc;
5883}
5884
b6016b76
MC		 5885#define NVRAM_SIZE 0x200
5886#define CRC32_RESIDUAL 0xdebb20e3
5887
5888static int
5889bnx2_test_nvram(struct bnx2 *bp)
5890{
b491edd5 5891 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5892 u8 *data = (u8 *) buf;
5893 int rc = 0;
5894 u32 magic, csum;
5895
5896 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5897 goto test_nvram_done;
5898
5899 magic = be32_to_cpu(buf[0]);
5900 if (magic != 0x669955aa) {
5901 rc = -ENODEV;
5902 goto test_nvram_done;
5903 }
5904
5905 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5906 goto test_nvram_done;
5907
5908 csum = ether_crc_le(0x100, data);
5909 if (csum != CRC32_RESIDUAL) {
5910 rc = -ENODEV;
5911 goto test_nvram_done;
5912 }
5913
5914 csum = ether_crc_le(0x100, data + 0x100);
5915 if (csum != CRC32_RESIDUAL) {
5916 rc = -ENODEV;
5917 }
5918
5919test_nvram_done:
5920 return rc;
5921}
5922
5923static int
5924bnx2_test_link(struct bnx2 *bp)
5925{
5926 u32 bmsr;
5927
9f52b564
MC		 5928 if (!netif_running(bp->dev))
5929 return -ENODEV;
5930
583c28e5 5931 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5932 if (bp->link_up)
5933 return 0;
5934 return -ENODEV;
5935 }
c770a65c 5936 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5937 bnx2_enable_bmsr1(bp);
5938 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5939 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5940 bnx2_disable_bmsr1(bp);
c770a65c 5941 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5942
b6016b76
MC		 5943 if (bmsr & BMSR_LSTATUS) {
5944 return 0;
5945 }
5946 return -ENODEV;
5947}
5948
5949static int
5950bnx2_test_intr(struct bnx2 *bp)
5951{
5952 int i;
b6016b76
MC		 5953 u16 status_idx;
5954
5955 if (!netif_running(bp->dev))
5956 return -ENODEV;
5957
5958 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5959
5960 /* This register is not touched during run-time. */
bf5295bb 5961 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5962 REG_RD(bp, BNX2_HC_COMMAND);
5963
5964 for (i = 0; i < 10; i++) {
5965 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5966 status_idx) {
5967
5968 break;
5969 }
5970
5971 msleep_interruptible(10);
5972 }
5973 if (i < 10)
5974 return 0;
5975
5976 return -ENODEV;
5977}
5978
38ea3686 5979/* Determining link for parallel detection. */
b2fadeae
MC		 5980static int
5981bnx2_5706_serdes_has_link(struct bnx2 *bp)
5982{
5983 u32 mode_ctl, an_dbg, exp;
5984
38ea3686
MC		 5985 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5986 return 0;
5987
b2fadeae
MC		 5988 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5989 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5990
5991 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5992 return 0;
5993
5994 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5995 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5996 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5997
f3014c0c 5998 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 5999 return 0;
6000
6001 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
6002 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6003 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6004
6005 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
6006 return 0;
6007
6008 return 1;
6009}
6010
b6016b76 6011static void
48b01e2d 6012bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 6013{
b2fadeae
MC		 6014 int check_link = 1;
6015
48b01e2d 6016 spin_lock(&bp->phy_lock);
b2fadeae 6017 if (bp->serdes_an_pending) {
48b01e2d 6018 bp->serdes_an_pending--;
b2fadeae
MC		 6019 check_link = 0;
6020 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 6021 u32 bmcr;
b6016b76 6022
ac392abc 6023 bp->current_interval = BNX2_TIMER_INTERVAL;
cd339a0e 6024
ca58c3af 6025 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6026
48b01e2d 6027 if (bmcr & BMCR_ANENABLE) {
b2fadeae 6028 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 6029 bmcr &= ~BMCR_ANENABLE;
6030 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 6031 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 6032 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 6033 }
b6016b76 6034 }
48b01e2d
MC		 6035 }
6036 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 6037 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 6038 u32 phy2;
b6016b76 6039
48b01e2d
MC		 6040 bnx2_write_phy(bp, 0x17, 0x0f01);
6041 bnx2_read_phy(bp, 0x15, &phy2);
6042 if (phy2 & 0x20) {
6043 u32 bmcr;
cd339a0e 6044
ca58c3af 6045 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 6046 bmcr |= BMCR_ANENABLE;
ca58c3af 6047 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 6048
583c28e5 6049 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 6050 }
6051 } else
ac392abc 6052 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6053
a2724e25 6054 if (check_link) {
b2fadeae
MC		 6055 u32 val;
6056
6057 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6058 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6059 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6060
a2724e25
MC		 6061 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6062 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6063 bnx2_5706s_force_link_dn(bp, 1);
6064 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6065 } else
6066 bnx2_set_link(bp);
6067 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6068 bnx2_set_link(bp);
b2fadeae 6069 }
48b01e2d
MC		 6070 spin_unlock(&bp->phy_lock);
6071}
b6016b76 6072
f8dd064e
MC		 6073static void
6074bnx2_5708_serdes_timer(struct bnx2 *bp)
6075{
583c28e5 6076 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 6077 return;
6078
583c28e5 6079 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 6080 bp->serdes_an_pending = 0;
6081 return;
6082 }
b6016b76 6083
f8dd064e
MC		 6084 spin_lock(&bp->phy_lock);
6085 if (bp->serdes_an_pending)
6086 bp->serdes_an_pending--;
6087 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6088 u32 bmcr;
b6016b76 6089
ca58c3af 6090 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 6091 if (bmcr & BMCR_ANENABLE) {
605a9e20 6092 bnx2_enable_forced_2g5(bp);
40105c0b 6093 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
f8dd064e 6094 } else {
605a9e20 6095 bnx2_disable_forced_2g5(bp);
f8dd064e 6096 bp->serdes_an_pending = 2;
ac392abc 6097 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6098 }
b6016b76 6099
f8dd064e 6100 } else
ac392abc 6101 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6102
f8dd064e
MC		 6103 spin_unlock(&bp->phy_lock);
6104}
6105
48b01e2d
MC		 6106static void
6107bnx2_timer(unsigned long data)
6108{
6109 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 6110
48b01e2d
MC		 6111 if (!netif_running(bp->dev))
6112 return;
b6016b76 6113
48b01e2d
MC		 6114 if (atomic_read(&bp->intr_sem) != 0)
6115 goto bnx2_restart_timer;
b6016b76 6116
efba0180
MC		 6117 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6118 BNX2_FLAG_USING_MSI)
6119 bnx2_chk_missed_msi(bp);
6120
df149d70 6121 bnx2_send_heart_beat(bp);
b6016b76 6122
2726d6e1
MC		 6123 bp->stats_blk->stat_FwRxDrop =
6124 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 6125
02537b06 6126 /* workaround occasional corrupted counters */
61d9e3fa 6127 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
02537b06
MC		 6128 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6129 BNX2_HC_COMMAND_STATS_NOW);
6130
583c28e5 6131 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 6132 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6133 bnx2_5706_serdes_timer(bp);
27a005b8 6134 else
f8dd064e 6135 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 6136 }
6137
6138bnx2_restart_timer:
cd339a0e 6139 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6140}
6141
8e6a72c4
MC		 6142static int
6143bnx2_request_irq(struct bnx2 *bp)
6144{
6d866ffc 6145 unsigned long flags;
b4b36042
MC		 6146 struct bnx2_irq *irq;
6147 int rc = 0, i;
8e6a72c4 6148
f86e82fb 6149 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 6150 flags = 0;
6151 else
6152 flags = IRQF_SHARED;
b4b36042
MC		 6153
6154 for (i = 0; i < bp->irq_nvecs; i++) {
6155 irq = &bp->irq_tbl[i];
c76c0475 6156 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
f0ea2e63 6157 &bp->bnx2_napi[i]);
b4b36042
MC		 6158 if (rc)
6159 break;
6160 irq->requested = 1;
6161 }
8e6a72c4
MC		 6162 return rc;
6163}
6164
6165static void
a29ba9d2 6166__bnx2_free_irq(struct bnx2 *bp)
8e6a72c4 6167{
b4b36042
MC		 6168 struct bnx2_irq *irq;
6169 int i;
8e6a72c4 6170
b4b36042
MC		 6171 for (i = 0; i < bp->irq_nvecs; i++) {
6172 irq = &bp->irq_tbl[i];
6173 if (irq->requested)
f0ea2e63 6174 free_irq(irq->vector, &bp->bnx2_napi[i]);
b4b36042 6175 irq->requested = 0;
6d866ffc 6176 }
a29ba9d2
MC		 6177}
6178
6179static void
6180bnx2_free_irq(struct bnx2 *bp)
6181{
6182
6183 __bnx2_free_irq(bp);
f86e82fb 6184 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 6185 pci_disable_msi(bp->pdev);
f86e82fb 6186 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 6187 pci_disable_msix(bp->pdev);
6188
f86e82fb 6189 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 6190}
6191
6192static void
5e9ad9e1 6193bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
b4b36042 6194{
379b39a2 6195 int i, total_vecs, rc;
57851d84 6196 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
4e1d0de9
MC		 6197 struct net_device *dev = bp->dev;
6198 const int len = sizeof(bp->irq_tbl[0].name);
57851d84 6199
b4b36042
MC		 6200 bnx2_setup_msix_tbl(bp);
6201 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6202 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6203 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84 6204
e2eb8e38
BL		 6205 /* Need to flush the previous three writes to ensure MSI-X
6206 * is setup properly */
6207 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6208
57851d84
MC		 6209 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6210 msix_ent[i].entry = i;
6211 msix_ent[i].vector = 0;
6212 }
6213
379b39a2
MC		 6214 total_vecs = msix_vecs;
6215#ifdef BCM_CNIC
6216 total_vecs++;
6217#endif
6218 rc = -ENOSPC;
6219 while (total_vecs >= BNX2_MIN_MSIX_VEC) {
6220 rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
6221 if (rc <= 0)
6222 break;
6223 if (rc > 0)
6224 total_vecs = rc;
6225 }
6226
57851d84
MC		 6227 if (rc != 0)
6228 return;
6229
379b39a2
MC		 6230 msix_vecs = total_vecs;
6231#ifdef BCM_CNIC
6232 msix_vecs--;
6233#endif
5e9ad9e1 6234 bp->irq_nvecs = msix_vecs;
f86e82fb 6235 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
379b39a2 6236 for (i = 0; i < total_vecs; i++) {
57851d84 6237 bp->irq_tbl[i].vector = msix_ent[i].vector;
69010313
MC		 6238 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6239 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6240 }
6d866ffc
MC		 6241}
6242
657d92fe 6243static int
6d866ffc
MC		 6244bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6245{
5e9ad9e1 6246 int cpus = num_online_cpus();
706bf240 6247 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5e9ad9e1 6248
6d866ffc
MC		 6249 bp->irq_tbl[0].handler = bnx2_interrupt;
6250 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 6251 bp->irq_nvecs = 1;
6252 bp->irq_tbl[0].vector = bp->pdev->irq;
6253
3d5f3a7b 6254 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5e9ad9e1 6255 bnx2_enable_msix(bp, msix_vecs);
6d866ffc 6256
f86e82fb
DM		 6257 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6258 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 6259 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 6260 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 6261 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 6262 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 6263 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6264 } else
6265 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 6266
6267 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 6268 }
6269 }
706bf240
BL		 6270
6271 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
657d92fe 6272 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
706bf240 6273
5e9ad9e1 6274 bp->num_rx_rings = bp->irq_nvecs;
657d92fe 6275 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
8e6a72c4
MC		 6276}
6277
b6016b76
MC		 6278/* Called with rtnl_lock */
6279static int
6280bnx2_open(struct net_device *dev)
6281{
972ec0d4 6282 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6283 int rc;
6284
7880b72e 6285 rc = bnx2_request_firmware(bp);
6286 if (rc < 0)
6287 goto out;
6288
1b2f922f
MC		 6289 netif_carrier_off(dev);
6290
829ca9a3 6291 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 6292 bnx2_disable_int(bp);
6293
657d92fe
BH		 6294 rc = bnx2_setup_int_mode(bp, disable_msi);
6295 if (rc)
6296 goto open_err;
4327ba43 6297 bnx2_init_napi(bp);
35e9010b 6298 bnx2_napi_enable(bp);
b6016b76 6299 rc = bnx2_alloc_mem(bp);
2739a8bb
MC		 6300 if (rc)
6301 goto open_err;
b6016b76 6302
8e6a72c4 6303 rc = bnx2_request_irq(bp);
2739a8bb
MC		 6304 if (rc)
6305 goto open_err;
b6016b76 6306
9a120bc5 6307 rc = bnx2_init_nic(bp, 1);
2739a8bb
MC		 6308 if (rc)
6309 goto open_err;
6aa20a22 6310
cd339a0e 6311 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6312
6313 atomic_set(&bp->intr_sem, 0);
6314
354fcd77
MC		 6315 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6316
b6016b76
MC		 6317 bnx2_enable_int(bp);
6318
f86e82fb 6319 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 6320 /* Test MSI to make sure it is working
6321 * If MSI test fails, go back to INTx mode
6322 */
6323 if (bnx2_test_intr(bp) != 0) {
3a9c6a49 6324 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
b6016b76
MC		 6325
6326 bnx2_disable_int(bp);
8e6a72c4 6327 bnx2_free_irq(bp);
b6016b76 6328
6d866ffc
MC		 6329 bnx2_setup_int_mode(bp, 1);
6330
9a120bc5 6331 rc = bnx2_init_nic(bp, 0);
b6016b76 6332
8e6a72c4
MC		 6333 if (!rc)
6334 rc = bnx2_request_irq(bp);
6335
b6016b76 6336 if (rc) {
b6016b76 6337 del_timer_sync(&bp->timer);
2739a8bb 6338 goto open_err;
b6016b76
MC		 6339 }
6340 bnx2_enable_int(bp);
6341 }
6342 }
f86e82fb 6343 if (bp->flags & BNX2_FLAG_USING_MSI)
3a9c6a49 6344 netdev_info(dev, "using MSI\n");
f86e82fb 6345 else if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49 6346 netdev_info(dev, "using MSIX\n");
b6016b76 6347
706bf240 6348 netif_tx_start_all_queues(dev);
7880b72e 6349out:
6350 return rc;
2739a8bb
MC		 6351
6352open_err:
6353 bnx2_napi_disable(bp);
6354 bnx2_free_skbs(bp);
6355 bnx2_free_irq(bp);
6356 bnx2_free_mem(bp);
f048fa9c 6357 bnx2_del_napi(bp);
7880b72e 6358 bnx2_release_firmware(bp);
6359 goto out;
b6016b76
MC		 6360}
6361
6362static void
c4028958 6363bnx2_reset_task(struct work_struct *work)
b6016b76 6364{
c4028958 6365 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
cd634019 6366 int rc;
b6016b76 6367
51bf6bb4
MC		 6368 rtnl_lock();
6369 if (!netif_running(bp->dev)) {
6370 rtnl_unlock();
afdc08b9 6371 return;
51bf6bb4 6372 }
afdc08b9 6373
212f9934 6374 bnx2_netif_stop(bp, true);
b6016b76 6375
cd634019
MC		 6376 rc = bnx2_init_nic(bp, 1);
6377 if (rc) {
6378 netdev_err(bp->dev, "failed to reset NIC, closing\n");
6379 bnx2_napi_enable(bp);
6380 dev_close(bp->dev);
6381 rtnl_unlock();
6382 return;
6383 }
b6016b76
MC		 6384
6385 atomic_set(&bp->intr_sem, 1);
212f9934 6386 bnx2_netif_start(bp, true);
51bf6bb4 6387 rtnl_unlock();
b6016b76
MC		 6388}
6389
20175c57
MC		 6390static void
6391bnx2_dump_state(struct bnx2 *bp)
6392{
6393 struct net_device *dev = bp->dev;
ecdbf6e0 6394 u32 val1, val2;
5804a8fb
MC		 6395
6396 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6397 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6398 atomic_read(&bp->intr_sem), val1);
6399 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6400 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6401 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
b98eba52 6402 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
3a9c6a49 6403 REG_RD(bp, BNX2_EMAC_TX_STATUS),
b98eba52
EW		 6404 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6405 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
3a9c6a49 6406 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
3a9c6a49
JP		 6407 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6408 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
20175c57 6409 if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49
JP		 6410 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6411 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
20175c57
MC		 6412}
6413
b6016b76
MC		 6414static void
6415bnx2_tx_timeout(struct net_device *dev)
6416{
972ec0d4 6417 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6418
20175c57 6419 bnx2_dump_state(bp);
ecdbf6e0 6420 bnx2_dump_mcp_state(bp);
20175c57 6421
b6016b76
MC		 6422 /* This allows the netif to be shutdown gracefully before resetting */
6423 schedule_work(&bp->reset_task);
6424}
6425
932ff279 6426/* Called with netif_tx_lock.
2f8af120
MC		 6427 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6428 * netif_wake_queue().
b6016b76 6429 */
61357325 6430static netdev_tx_t
b6016b76
MC		 6431bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6432{
972ec0d4 6433 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6434 dma_addr_t mapping;
6435 struct tx_bd *txbd;
3d16af86 6436 struct sw_tx_bd *tx_buf;
b6016b76
MC		 6437 u32 len, vlan_tag_flags, last_frag, mss;
6438 u16 prod, ring_prod;
6439 int i;
706bf240
BL		 6440 struct bnx2_napi *bnapi;
6441 struct bnx2_tx_ring_info *txr;
6442 struct netdev_queue *txq;
6443
6444 /* Determine which tx ring we will be placed on */
6445 i = skb_get_queue_mapping(skb);
6446 bnapi = &bp->bnx2_napi[i];
6447 txr = &bnapi->tx_ring;
6448 txq = netdev_get_tx_queue(dev, i);
b6016b76 6449
35e9010b 6450 if (unlikely(bnx2_tx_avail(bp, txr) <
a550c99b 6451 (skb_shinfo(skb)->nr_frags + 1))) {
706bf240 6452 netif_tx_stop_queue(txq);
3a9c6a49 6453 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
b6016b76
MC		 6454
6455 return NETDEV_TX_BUSY;
6456 }
6457 len = skb_headlen(skb);
35e9010b 6458 prod = txr->tx_prod;
b6016b76
MC		 6459 ring_prod = TX_RING_IDX(prod);
6460
6461 vlan_tag_flags = 0;
84fa7933 6462 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 6463 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6464 }
6465
eab6d18d 6466 if (vlan_tx_tag_present(skb)) {
b6016b76
MC		 6467 vlan_tag_flags |=
6468 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6469 }
7d0fd211 6470
fde82055 6471 if ((mss = skb_shinfo(skb)->gso_size)) {
a1efb4b6 6472 u32 tcp_opt_len;
eddc9ec5 6473 struct iphdr *iph;
b6016b76 6474
b6016b76
MC		 6475 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6476
4666f87a
MC		 6477 tcp_opt_len = tcp_optlen(skb);
6478
6479 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6480 u32 tcp_off = skb_transport_offset(skb) -
6481 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 6482
4666f87a
MC		 6483 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6484 TX_BD_FLAGS_SW_FLAGS;
6485 if (likely(tcp_off == 0))
6486 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6487 else {
6488 tcp_off >>= 3;
6489 vlan_tag_flags |= ((tcp_off & 0x3) <<
6490 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6491 ((tcp_off & 0x10) <<
6492 TX_BD_FLAGS_TCP6_OFF4_SHL);
6493 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6494 }
6495 } else {
4666f87a 6496 iph = ip_hdr(skb);
4666f87a
MC		 6497 if (tcp_opt_len || (iph->ihl > 5)) {
6498 vlan_tag_flags |= ((iph->ihl - 5) +
6499 (tcp_opt_len >> 2)) << 8;
6500 }
b6016b76 6501 }
4666f87a 6502 } else
b6016b76 6503 mss = 0;
b6016b76 6504
36227e88
SG		 6505 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
6506 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 6507 dev_kfree_skb(skb);
6508 return NETDEV_TX_OK;
6509 }
6510
35e9010b 6511 tx_buf = &txr->tx_buf_ring[ring_prod];
b6016b76 6512 tx_buf->skb = skb;
1a4ccc2d 6513 dma_unmap_addr_set(tx_buf, mapping, mapping);
b6016b76 6514
35e9010b 6515 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6516
6517 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6518 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6519 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6520 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6521
6522 last_frag = skb_shinfo(skb)->nr_frags;
d62fda08
ED		 6523 tx_buf->nr_frags = last_frag;
6524 tx_buf->is_gso = skb_is_gso(skb);
b6016b76
MC		 6525
6526 for (i = 0; i < last_frag; i++) {
9e903e08 6527 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
b6016b76
MC		 6528
6529 prod = NEXT_TX_BD(prod);
6530 ring_prod = TX_RING_IDX(prod);
35e9010b 6531 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76 6532
9e903e08 6533 len = skb_frag_size(frag);
b7b6a688 6534 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,
5d6bcdfe 6535 DMA_TO_DEVICE);
36227e88 6536 if (dma_mapping_error(&bp->pdev->dev, mapping))
e95524a7 6537 goto dma_error;
1a4ccc2d 6538 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
e95524a7 6539 mapping);
b6016b76
MC		 6540
6541 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6542 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6543 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6544 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6545
6546 }
6547 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6548
6549 prod = NEXT_TX_BD(prod);
35e9010b 6550 txr->tx_prod_bseq += skb->len;
b6016b76 6551
35e9010b
MC		 6552 REG_WR16(bp, txr->tx_bidx_addr, prod);
6553 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 6554
6555 mmiowb();
6556
35e9010b 6557 txr->tx_prod = prod;
b6016b76 6558
35e9010b 6559 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
706bf240 6560 netif_tx_stop_queue(txq);
11848b96
MC		 6561
6562 /* netif_tx_stop_queue() must be done before checking
6563 * tx index in bnx2_tx_avail() below, because in
6564 * bnx2_tx_int(), we update tx index before checking for
6565 * netif_tx_queue_stopped().
6566 */
6567 smp_mb();
35e9010b 6568 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
706bf240 6569 netif_tx_wake_queue(txq);
b6016b76
MC		 6570 }
6571
e95524a7
AD		 6572 return NETDEV_TX_OK;
6573dma_error:
6574 /* save value of frag that failed */
6575 last_frag = i;
6576
6577 /* start back at beginning and unmap skb */
6578 prod = txr->tx_prod;
6579 ring_prod = TX_RING_IDX(prod);
6580 tx_buf = &txr->tx_buf_ring[ring_prod];
6581 tx_buf->skb = NULL;
36227e88 6582 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6583 skb_headlen(skb), PCI_DMA_TODEVICE);
6584
6585 /* unmap remaining mapped pages */
6586 for (i = 0; i < last_frag; i++) {
6587 prod = NEXT_TX_BD(prod);
6588 ring_prod = TX_RING_IDX(prod);
6589 tx_buf = &txr->tx_buf_ring[ring_prod];
36227e88 6590 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
9e903e08 6591 skb_frag_size(&skb_shinfo(skb)->frags[i]),
e95524a7
AD		 6592 PCI_DMA_TODEVICE);
6593 }
6594
6595 dev_kfree_skb(skb);
b6016b76
MC		 6596 return NETDEV_TX_OK;
6597}
6598
6599/* Called with rtnl_lock */
6600static int
6601bnx2_close(struct net_device *dev)
6602{
972ec0d4 6603 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6604
bea3348e 6605 bnx2_disable_int_sync(bp);
35efa7c1 6606 bnx2_napi_disable(bp);
b6016b76 6607 del_timer_sync(&bp->timer);
74bf4ba3 6608 bnx2_shutdown_chip(bp);
8e6a72c4 6609 bnx2_free_irq(bp);
b6016b76
MC		 6610 bnx2_free_skbs(bp);
6611 bnx2_free_mem(bp);
f048fa9c 6612 bnx2_del_napi(bp);
b6016b76
MC		 6613 bp->link_up = 0;
6614 netif_carrier_off(bp->dev);
829ca9a3 6615 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 6616 return 0;
6617}
6618
354fcd77
MC		 6619static void
6620bnx2_save_stats(struct bnx2 *bp)
6621{
6622 u32 *hw_stats = (u32 *) bp->stats_blk;
6623 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6624 int i;
6625
6626 /* The 1st 10 counters are 64-bit counters */
6627 for (i = 0; i < 20; i += 2) {
6628 u32 hi;
6629 u64 lo;
6630
c9885fe5
PR		 6631 hi = temp_stats[i] + hw_stats[i];
6632 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
354fcd77
MC		 6633 if (lo > 0xffffffff)
6634 hi++;
c9885fe5
PR		 6635 temp_stats[i] = hi;
6636 temp_stats[i + 1] = lo & 0xffffffff;
354fcd77
MC		 6637 }
6638
6639 for ( ; i < sizeof(struct statistics_block) / 4; i++)
c9885fe5 6640 temp_stats[i] += hw_stats[i];
354fcd77
MC		 6641}
6642
5d07bf26
ED		 6643#define GET_64BIT_NET_STATS64(ctr) \
6644 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
b6016b76 6645
a4743058 6646#define GET_64BIT_NET_STATS(ctr) \
354fcd77
MC		 6647 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6648 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
b6016b76 6649
a4743058 6650#define GET_32BIT_NET_STATS(ctr) \
354fcd77
MC		 6651 (unsigned long) (bp->stats_blk->ctr + \
6652 bp->temp_stats_blk->ctr)
a4743058 6653
5d07bf26
ED		 6654static struct rtnl_link_stats64 *
6655bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
b6016b76 6656{
972ec0d4 6657 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6658
5d07bf26 6659 if (bp->stats_blk == NULL)
b6016b76 6660 return net_stats;
5d07bf26 6661
b6016b76 6662 net_stats->rx_packets =
a4743058
MC		 6663 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6664 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6665 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
b6016b76
MC		 6666
6667 net_stats->tx_packets =
a4743058
MC		 6668 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6669 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6670 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
b6016b76
MC		 6671
6672 net_stats->rx_bytes =
a4743058 6673 GET_64BIT_NET_STATS(stat_IfHCInOctets);
b6016b76
MC		 6674
6675 net_stats->tx_bytes =
a4743058 6676 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
b6016b76 6677
6aa20a22 6678 net_stats->multicast =
6fdae995 6679 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
b6016b76 6680
6aa20a22 6681 net_stats->collisions =
a4743058 6682 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
b6016b76 6683
6aa20a22 6684 net_stats->rx_length_errors =
a4743058
MC		 6685 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6686 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
b6016b76 6687
6aa20a22 6688 net_stats->rx_over_errors =
a4743058
MC		 6689 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6690 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
b6016b76 6691
6aa20a22 6692 net_stats->rx_frame_errors =
a4743058 6693 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
b6016b76 6694
6aa20a22 6695 net_stats->rx_crc_errors =
a4743058 6696 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
b6016b76
MC		 6697
6698 net_stats->rx_errors = net_stats->rx_length_errors +
6699 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6700 net_stats->rx_crc_errors;
6701
6702 net_stats->tx_aborted_errors =
a4743058
MC		 6703 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6704 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
b6016b76 6705
5b0c76ad
MC		 6706 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6707 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 6708 net_stats->tx_carrier_errors = 0;
6709 else {
6710 net_stats->tx_carrier_errors =
a4743058 6711 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
b6016b76
MC		 6712 }
6713
6714 net_stats->tx_errors =
a4743058 6715 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
b6016b76
MC		 6716 net_stats->tx_aborted_errors +
6717 net_stats->tx_carrier_errors;
6718
cea94db9 6719 net_stats->rx_missed_errors =
a4743058
MC		 6720 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6721 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6722 GET_32BIT_NET_STATS(stat_FwRxDrop);
cea94db9 6723
b6016b76
MC		 6724 return net_stats;
6725}
6726
6727/* All ethtool functions called with rtnl_lock */
6728
6729static int
6730bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6731{
972ec0d4 6732 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6733 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6734
6735 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6736 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6737 support_serdes = 1;
6738 support_copper = 1;
6739 } else if (bp->phy_port == PORT_FIBRE)
6740 support_serdes = 1;
6741 else
6742 support_copper = 1;
6743
6744 if (support_serdes) {
b6016b76
MC		 6745 cmd->supported |= SUPPORTED_1000baseT_Full |
6746 SUPPORTED_FIBRE;
583c28e5 6747 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6748 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6749
b6016b76 6750 }
7b6b8347 6751 if (support_copper) {
b6016b76
MC		 6752 cmd->supported |= SUPPORTED_10baseT_Half |
6753 SUPPORTED_10baseT_Full |
6754 SUPPORTED_100baseT_Half |
6755 SUPPORTED_100baseT_Full |
6756 SUPPORTED_1000baseT_Full |
6757 SUPPORTED_TP;
6758
b6016b76
MC		 6759 }
6760
7b6b8347
MC		 6761 spin_lock_bh(&bp->phy_lock);
6762 cmd->port = bp->phy_port;
b6016b76
MC		 6763 cmd->advertising = bp->advertising;
6764
6765 if (bp->autoneg & AUTONEG_SPEED) {
6766 cmd->autoneg = AUTONEG_ENABLE;
70739497 6767 } else {
b6016b76
MC		 6768 cmd->autoneg = AUTONEG_DISABLE;
6769 }
6770
6771 if (netif_carrier_ok(dev)) {
70739497 6772 ethtool_cmd_speed_set(cmd, bp->line_speed);
b6016b76
MC		 6773 cmd->duplex = bp->duplex;
6774 }
6775 else {
70739497 6776 ethtool_cmd_speed_set(cmd, -1);
b6016b76
MC		 6777 cmd->duplex = -1;
6778 }
7b6b8347 6779 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6780
6781 cmd->transceiver = XCVR_INTERNAL;
6782 cmd->phy_address = bp->phy_addr;
6783
6784 return 0;
6785}
6aa20a22 6786
b6016b76
MC		 6787static int
6788bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6789{
972ec0d4 6790 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6791 u8 autoneg = bp->autoneg;
6792 u8 req_duplex = bp->req_duplex;
6793 u16 req_line_speed = bp->req_line_speed;
6794 u32 advertising = bp->advertising;
7b6b8347
MC		 6795 int err = -EINVAL;
6796
6797 spin_lock_bh(&bp->phy_lock);
6798
6799 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6800 goto err_out_unlock;
6801
583c28e5
MC		 6802 if (cmd->port != bp->phy_port &&
6803 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6804 goto err_out_unlock;
b6016b76 6805
d6b14486
MC		 6806 /* If device is down, we can store the settings only if the user
6807 * is setting the currently active port.
6808 */
6809 if (!netif_running(dev) && cmd->port != bp->phy_port)
6810 goto err_out_unlock;
6811
b6016b76
MC		 6812 if (cmd->autoneg == AUTONEG_ENABLE) {
6813 autoneg |= AUTONEG_SPEED;
6814
beb499af
MC		 6815 advertising = cmd->advertising;
6816 if (cmd->port == PORT_TP) {
6817 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6818 if (!advertising)
b6016b76 6819 advertising = ETHTOOL_ALL_COPPER_SPEED;
beb499af
MC		 6820 } else {
6821 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6822 if (!advertising)
6823 advertising = ETHTOOL_ALL_FIBRE_SPEED;
b6016b76
MC		 6824 }
6825 advertising |= ADVERTISED_Autoneg;
6826 }
6827 else {
25db0338 6828 u32 speed = ethtool_cmd_speed(cmd);
7b6b8347 6829 if (cmd->port == PORT_FIBRE) {
25db0338
DD		 6830 if ((speed != SPEED_1000 &&
6831 speed != SPEED_2500) ||
80be4434 6832 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6833 goto err_out_unlock;
80be4434 6834
25db0338 6835 if (speed == SPEED_2500 &&
583c28e5 6836 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6837 goto err_out_unlock;
25db0338 6838 } else if (speed == SPEED_1000 || speed == SPEED_2500)
7b6b8347
MC		 6839 goto err_out_unlock;
6840
b6016b76 6841 autoneg &= ~AUTONEG_SPEED;
25db0338 6842 req_line_speed = speed;
b6016b76
MC		 6843 req_duplex = cmd->duplex;
6844 advertising = 0;
6845 }
6846
6847 bp->autoneg = autoneg;
6848 bp->advertising = advertising;
6849 bp->req_line_speed = req_line_speed;
6850 bp->req_duplex = req_duplex;
6851
d6b14486
MC		 6852 err = 0;
6853 /* If device is down, the new settings will be picked up when it is
6854 * brought up.
6855 */
6856 if (netif_running(dev))
6857 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6858
7b6b8347 6859err_out_unlock:
c770a65c 6860 spin_unlock_bh(&bp->phy_lock);
b6016b76 6861
7b6b8347 6862 return err;
b6016b76
MC		 6863}
6864
6865static void
6866bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6867{
972ec0d4 6868 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6869
68aad78c
RJ		 6870 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
6871 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
6872 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
6873 strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));
b6016b76
MC		 6874}
6875
244ac4f4
MC		 6876#define BNX2_REGDUMP_LEN (32 * 1024)
6877
6878static int
6879bnx2_get_regs_len(struct net_device *dev)
6880{
6881 return BNX2_REGDUMP_LEN;
6882}
6883
6884static void
6885bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6886{
6887 u32 *p = _p, i, offset;
6888 u8 *orig_p = _p;
6889 struct bnx2 *bp = netdev_priv(dev);
b6bc7650
JP		 6890 static const u32 reg_boundaries[] = {
6891 0x0000, 0x0098, 0x0400, 0x045c,
6892 0x0800, 0x0880, 0x0c00, 0x0c10,
6893 0x0c30, 0x0d08, 0x1000, 0x101c,
6894 0x1040, 0x1048, 0x1080, 0x10a4,
6895 0x1400, 0x1490, 0x1498, 0x14f0,
6896 0x1500, 0x155c, 0x1580, 0x15dc,
6897 0x1600, 0x1658, 0x1680, 0x16d8,
6898 0x1800, 0x1820, 0x1840, 0x1854,
6899 0x1880, 0x1894, 0x1900, 0x1984,
6900 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6901 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6902 0x2000, 0x2030, 0x23c0, 0x2400,
6903 0x2800, 0x2820, 0x2830, 0x2850,
6904 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6905 0x3c00, 0x3c94, 0x4000, 0x4010,
6906 0x4080, 0x4090, 0x43c0, 0x4458,
6907 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6908 0x4fc0, 0x5010, 0x53c0, 0x5444,
6909 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6910 0x5fc0, 0x6000, 0x6400, 0x6428,
6911 0x6800, 0x6848, 0x684c, 0x6860,
6912 0x6888, 0x6910, 0x8000
6913 };
244ac4f4
MC		 6914
6915 regs->version = 0;
6916
6917 memset(p, 0, BNX2_REGDUMP_LEN);
6918
6919 if (!netif_running(bp->dev))
6920 return;
6921
6922 i = 0;
6923 offset = reg_boundaries[0];
6924 p += offset;
6925 while (offset < BNX2_REGDUMP_LEN) {
6926 *p++ = REG_RD(bp, offset);
6927 offset += 4;
6928 if (offset == reg_boundaries[i + 1]) {
6929 offset = reg_boundaries[i + 2];
6930 p = (u32 *) (orig_p + offset);
6931 i += 2;
6932 }
6933 }
6934}
6935
b6016b76
MC		 6936static void
6937bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6938{
972ec0d4 6939 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6940
f86e82fb 6941 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6942 wol->supported = 0;
6943 wol->wolopts = 0;
6944 }
6945 else {
6946 wol->supported = WAKE_MAGIC;
6947 if (bp->wol)
6948 wol->wolopts = WAKE_MAGIC;
6949 else
6950 wol->wolopts = 0;
6951 }
6952 memset(&wol->sopass, 0, sizeof(wol->sopass));
6953}
6954
6955static int
6956bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6957{
972ec0d4 6958 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6959
6960 if (wol->wolopts & ~WAKE_MAGIC)
6961 return -EINVAL;
6962
6963 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6964 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6965 return -EINVAL;
6966
6967 bp->wol = 1;
6968 }
6969 else {
6970 bp->wol = 0;
6971 }
6972 return 0;
6973}
6974
6975static int
6976bnx2_nway_reset(struct net_device *dev)
6977{
972ec0d4 6978 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6979 u32 bmcr;
6980
9f52b564
MC		 6981 if (!netif_running(dev))
6982 return -EAGAIN;
6983
b6016b76
MC		 6984 if (!(bp->autoneg & AUTONEG_SPEED)) {
6985 return -EINVAL;
6986 }
6987
c770a65c 6988 spin_lock_bh(&bp->phy_lock);
b6016b76 6989
583c28e5 6990 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6991 int rc;
6992
6993 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6994 spin_unlock_bh(&bp->phy_lock);
6995 return rc;
6996 }
6997
b6016b76 6998 /* Force a link down visible on the other side */
583c28e5 6999 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 7000 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 7001 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7002
7003 msleep(20);
7004
c770a65c 7005 spin_lock_bh(&bp->phy_lock);
f8dd064e 7006
40105c0b 7007 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 7008 bp->serdes_an_pending = 1;
7009 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 7010 }
7011
ca58c3af 7012 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 7013 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 7014 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 7015
c770a65c 7016 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7017
7018 return 0;
7019}
7020
7959ea25
ON		 7021static u32
7022bnx2_get_link(struct net_device *dev)
7023{
7024 struct bnx2 *bp = netdev_priv(dev);
7025
7026 return bp->link_up;
7027}
7028
b6016b76
MC		 7029static int
7030bnx2_get_eeprom_len(struct net_device *dev)
7031{
972ec0d4 7032 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7033
1122db71 7034 if (bp->flash_info == NULL)
b6016b76
MC		 7035 return 0;
7036
1122db71 7037 return (int) bp->flash_size;
b6016b76
MC		 7038}
7039
7040static int
7041bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7042 u8 *eebuf)
7043{
972ec0d4 7044 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7045 int rc;
7046
9f52b564
MC		 7047 if (!netif_running(dev))
7048 return -EAGAIN;
7049
1064e944 7050 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 7051
7052 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7053
7054 return rc;
7055}
7056
7057static int
7058bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7059 u8 *eebuf)
7060{
972ec0d4 7061 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7062 int rc;
7063
9f52b564
MC		 7064 if (!netif_running(dev))
7065 return -EAGAIN;
7066
1064e944 7067 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 7068
7069 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7070
7071 return rc;
7072}
7073
7074static int
7075bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7076{
972ec0d4 7077 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7078
7079 memset(coal, 0, sizeof(struct ethtool_coalesce));
7080
7081 coal->rx_coalesce_usecs = bp->rx_ticks;
7082 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7083 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7084 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7085
7086 coal->tx_coalesce_usecs = bp->tx_ticks;
7087 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7088 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7089 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7090
7091 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7092
7093 return 0;
7094}
7095
7096static int
7097bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7098{
972ec0d4 7099 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7100
7101 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7102 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7103
6aa20a22 7104 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 7105 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7106
7107 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7108 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7109
7110 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7111 if (bp->rx_quick_cons_trip_int > 0xff)
7112 bp->rx_quick_cons_trip_int = 0xff;
7113
7114 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7115 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7116
7117 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7118 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7119
7120 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7121 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7122
7123 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7124 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7125 0xff;
7126
7127 bp->stats_ticks = coal->stats_block_coalesce_usecs;
61d9e3fa 7128 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
02537b06
MC		 7129 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7130 bp->stats_ticks = USEC_PER_SEC;
7131 }
7ea6920e
MC		 7132 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7133 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7134 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7135
7136 if (netif_running(bp->dev)) {
212f9934 7137 bnx2_netif_stop(bp, true);
9a120bc5 7138 bnx2_init_nic(bp, 0);
212f9934 7139 bnx2_netif_start(bp, true);
b6016b76
MC		 7140 }
7141
7142 return 0;
7143}
7144
7145static void
7146bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7147{
972ec0d4 7148 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7149
13daffa2 7150 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
47bf4246 7151 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 7152
7153 ering->rx_pending = bp->rx_ring_size;
47bf4246 7154 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 7155
7156 ering->tx_max_pending = MAX_TX_DESC_CNT;
7157 ering->tx_pending = bp->tx_ring_size;
7158}
7159
7160static int
5d5d0015 7161bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 7162{
13daffa2 7163 if (netif_running(bp->dev)) {
354fcd77
MC		 7164 /* Reset will erase chipset stats; save them */
7165 bnx2_save_stats(bp);
7166
212f9934 7167 bnx2_netif_stop(bp, true);
13daffa2 7168 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
a29ba9d2 7169 __bnx2_free_irq(bp);
13daffa2
MC		 7170 bnx2_free_skbs(bp);
7171 bnx2_free_mem(bp);
7172 }
7173
5d5d0015
MC		 7174 bnx2_set_rx_ring_size(bp, rx);
7175 bp->tx_ring_size = tx;
b6016b76
MC		 7176
7177 if (netif_running(bp->dev)) {
13daffa2
MC		 7178 int rc;
7179
7180 rc = bnx2_alloc_mem(bp);
a29ba9d2
MC		 7181 if (!rc)
7182 rc = bnx2_request_irq(bp);
7183
6fefb65e
MC		 7184 if (!rc)
7185 rc = bnx2_init_nic(bp, 0);
7186
7187 if (rc) {
7188 bnx2_napi_enable(bp);
7189 dev_close(bp->dev);
13daffa2 7190 return rc;
6fefb65e 7191 }
e9f26c49
MC		 7192#ifdef BCM_CNIC
7193 mutex_lock(&bp->cnic_lock);
7194 /* Let cnic know about the new status block. */
7195 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7196 bnx2_setup_cnic_irq_info(bp);
7197 mutex_unlock(&bp->cnic_lock);
7198#endif
212f9934 7199 bnx2_netif_start(bp, true);
b6016b76 7200 }
b6016b76
MC		 7201 return 0;
7202}
7203
5d5d0015
MC		 7204static int
7205bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7206{
7207 struct bnx2 *bp = netdev_priv(dev);
7208 int rc;
7209
7210 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7211 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7212 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7213
7214 return -EINVAL;
7215 }
7216 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7217 return rc;
7218}
7219
b6016b76
MC		 7220static void
7221bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7222{
972ec0d4 7223 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7224
7225 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7226 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7227 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7228}
7229
7230static int
7231bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7232{
972ec0d4 7233 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7234
7235 bp->req_flow_ctrl = 0;
7236 if (epause->rx_pause)
7237 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7238 if (epause->tx_pause)
7239 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7240
7241 if (epause->autoneg) {
7242 bp->autoneg |= AUTONEG_FLOW_CTRL;
7243 }
7244 else {
7245 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7246 }
7247
9f52b564
MC		 7248 if (netif_running(dev)) {
7249 spin_lock_bh(&bp->phy_lock);
7250 bnx2_setup_phy(bp, bp->phy_port);
7251 spin_unlock_bh(&bp->phy_lock);
7252 }
b6016b76
MC		 7253
7254 return 0;
7255}
7256
14ab9b86 7257static struct {
b6016b76 7258 char string[ETH_GSTRING_LEN];
790dab2f 7259} bnx2_stats_str_arr[] = {
b6016b76
MC		 7260 { "rx_bytes" },
7261 { "rx_error_bytes" },
7262 { "tx_bytes" },
7263 { "tx_error_bytes" },
7264 { "rx_ucast_packets" },
7265 { "rx_mcast_packets" },
7266 { "rx_bcast_packets" },
7267 { "tx_ucast_packets" },
7268 { "tx_mcast_packets" },
7269 { "tx_bcast_packets" },
7270 { "tx_mac_errors" },
7271 { "tx_carrier_errors" },
7272 { "rx_crc_errors" },
7273 { "rx_align_errors" },
7274 { "tx_single_collisions" },
7275 { "tx_multi_collisions" },
7276 { "tx_deferred" },
7277 { "tx_excess_collisions" },
7278 { "tx_late_collisions" },
7279 { "tx_total_collisions" },
7280 { "rx_fragments" },
7281 { "rx_jabbers" },
7282 { "rx_undersize_packets" },
7283 { "rx_oversize_packets" },
7284 { "rx_64_byte_packets" },
7285 { "rx_65_to_127_byte_packets" },
7286 { "rx_128_to_255_byte_packets" },
7287 { "rx_256_to_511_byte_packets" },
7288 { "rx_512_to_1023_byte_packets" },
7289 { "rx_1024_to_1522_byte_packets" },
7290 { "rx_1523_to_9022_byte_packets" },
7291 { "tx_64_byte_packets" },
7292 { "tx_65_to_127_byte_packets" },
7293 { "tx_128_to_255_byte_packets" },
7294 { "tx_256_to_511_byte_packets" },
7295 { "tx_512_to_1023_byte_packets" },
7296 { "tx_1024_to_1522_byte_packets" },
7297 { "tx_1523_to_9022_byte_packets" },
7298 { "rx_xon_frames" },
7299 { "rx_xoff_frames" },
7300 { "tx_xon_frames" },
7301 { "tx_xoff_frames" },
7302 { "rx_mac_ctrl_frames" },
7303 { "rx_filtered_packets" },
790dab2f 7304 { "rx_ftq_discards" },
b6016b76 7305 { "rx_discards" },
cea94db9 7306 { "rx_fw_discards" },
b6016b76
MC		 7307};
7308
790dab2f
MC		 7309#define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7310 sizeof(bnx2_stats_str_arr[0]))
7311
b6016b76
MC		 7312#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7313
f71e1309 7314static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7315 STATS_OFFSET32(stat_IfHCInOctets_hi),
7316 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7317 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7318 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7319 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7320 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7321 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7322 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7323 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7324 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7325 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 7326 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7327 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7328 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7329 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7330 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7331 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7332 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7333 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7334 STATS_OFFSET32(stat_EtherStatsCollisions),
7335 STATS_OFFSET32(stat_EtherStatsFragments),
7336 STATS_OFFSET32(stat_EtherStatsJabbers),
7337 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7338 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7339 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7340 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7341 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7342 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7343 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7344 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7345 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7346 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7347 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7348 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7349 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7350 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7351 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7352 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7353 STATS_OFFSET32(stat_XonPauseFramesReceived),
7354 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7355 STATS_OFFSET32(stat_OutXonSent),
7356 STATS_OFFSET32(stat_OutXoffSent),
7357 STATS_OFFSET32(stat_MacControlFramesReceived),
7358 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
790dab2f 7359 STATS_OFFSET32(stat_IfInFTQDiscards),
6aa20a22 7360 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 7361 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 7362};
7363
7364/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7365 * skipped because of errata.
6aa20a22 7366 */
14ab9b86 7367static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7368 8,0,8,8,8,8,8,8,8,8,
7369 4,0,4,4,4,4,4,4,4,4,
7370 4,4,4,4,4,4,4,4,4,4,
7371 4,4,4,4,4,4,4,4,4,4,
790dab2f 7372 4,4,4,4,4,4,4,
b6016b76
MC		 7373};
7374
5b0c76ad
MC		 7375static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7376 8,0,8,8,8,8,8,8,8,8,
7377 4,4,4,4,4,4,4,4,4,4,
7378 4,4,4,4,4,4,4,4,4,4,
7379 4,4,4,4,4,4,4,4,4,4,
790dab2f 7380 4,4,4,4,4,4,4,
5b0c76ad
MC		 7381};
7382
b6016b76
MC		 7383#define BNX2_NUM_TESTS 6
7384
14ab9b86 7385static struct {
b6016b76
MC		 7386 char string[ETH_GSTRING_LEN];
7387} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7388 { "register_test (offline)" },
7389 { "memory_test (offline)" },
7390 { "loopback_test (offline)" },
7391 { "nvram_test (online)" },
7392 { "interrupt_test (online)" },
7393 { "link_test (online)" },
7394};
7395
7396static int
b9f2c044 7397bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 7398{
b9f2c044
JG		 7399 switch (sset) {
7400 case ETH_SS_TEST:
7401 return BNX2_NUM_TESTS;
7402 case ETH_SS_STATS:
7403 return BNX2_NUM_STATS;
7404 default:
7405 return -EOPNOTSUPP;
7406 }
b6016b76
MC		 7407}
7408
7409static void
7410bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7411{
972ec0d4 7412 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7413
9f52b564
MC		 7414 bnx2_set_power_state(bp, PCI_D0);
7415
b6016b76
MC		 7416 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7417 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 7418 int i;
7419
212f9934 7420 bnx2_netif_stop(bp, true);
b6016b76
MC		 7421 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7422 bnx2_free_skbs(bp);
7423
7424 if (bnx2_test_registers(bp) != 0) {
7425 buf[0] = 1;
7426 etest->flags |= ETH_TEST_FL_FAILED;
7427 }
7428 if (bnx2_test_memory(bp) != 0) {
7429 buf[1] = 1;
7430 etest->flags |= ETH_TEST_FL_FAILED;
7431 }
bc5a0690 7432 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 7433 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76 7434
9f52b564
MC		 7435 if (!netif_running(bp->dev))
7436 bnx2_shutdown_chip(bp);
b6016b76 7437 else {
9a120bc5 7438 bnx2_init_nic(bp, 1);
212f9934 7439 bnx2_netif_start(bp, true);
b6016b76
MC		 7440 }
7441
7442 /* wait for link up */
80be4434
MC		 7443 for (i = 0; i < 7; i++) {
7444 if (bp->link_up)
7445 break;
7446 msleep_interruptible(1000);
7447 }
b6016b76
MC		 7448 }
7449
7450 if (bnx2_test_nvram(bp) != 0) {
7451 buf[3] = 1;
7452 etest->flags |= ETH_TEST_FL_FAILED;
7453 }
7454 if (bnx2_test_intr(bp) != 0) {
7455 buf[4] = 1;
7456 etest->flags |= ETH_TEST_FL_FAILED;
7457 }
7458
7459 if (bnx2_test_link(bp) != 0) {
7460 buf[5] = 1;
7461 etest->flags |= ETH_TEST_FL_FAILED;
7462
7463 }
9f52b564
MC		 7464 if (!netif_running(bp->dev))
7465 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 7466}
7467
7468static void
7469bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7470{
7471 switch (stringset) {
7472 case ETH_SS_STATS:
7473 memcpy(buf, bnx2_stats_str_arr,
7474 sizeof(bnx2_stats_str_arr));
7475 break;
7476 case ETH_SS_TEST:
7477 memcpy(buf, bnx2_tests_str_arr,
7478 sizeof(bnx2_tests_str_arr));
7479 break;
7480 }
7481}
7482
b6016b76
MC		 7483static void
7484bnx2_get_ethtool_stats(struct net_device *dev,
7485 struct ethtool_stats *stats, u64 *buf)
7486{
972ec0d4 7487 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7488 int i;
7489 u32 *hw_stats = (u32 *) bp->stats_blk;
354fcd77 7490 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
14ab9b86 7491 u8 *stats_len_arr = NULL;
b6016b76
MC		 7492
7493 if (hw_stats == NULL) {
7494 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7495 return;
7496 }
7497
5b0c76ad
MC		 7498 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7499 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7500 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7501 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 7502 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 7503 else
7504 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 7505
7506 for (i = 0; i < BNX2_NUM_STATS; i++) {
354fcd77
MC		 7507 unsigned long offset;
7508
b6016b76
MC		 7509 if (stats_len_arr[i] == 0) {
7510 /* skip this counter */
7511 buf[i] = 0;
7512 continue;
7513 }
354fcd77
MC		 7514
7515 offset = bnx2_stats_offset_arr[i];
b6016b76
MC		 7516 if (stats_len_arr[i] == 4) {
7517 /* 4-byte counter */
354fcd77
MC		 7518 buf[i] = (u64) *(hw_stats + offset) +
7519 *(temp_stats + offset);
b6016b76
MC		 7520 continue;
7521 }
7522 /* 8-byte counter */
354fcd77
MC		 7523 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7524 *(hw_stats + offset + 1) +
7525 (((u64) *(temp_stats + offset)) << 32) +
7526 *(temp_stats + offset + 1);
b6016b76
MC		 7527 }
7528}
7529
7530static int
2e17e1aa 7531bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state)
b6016b76 7532{
972ec0d4 7533 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7534
2e17e1aa 7535 switch (state) {
7536 case ETHTOOL_ID_ACTIVE:
7537 bnx2_set_power_state(bp, PCI_D0);
9f52b564 7538
2e17e1aa 7539 bp->leds_save = REG_RD(bp, BNX2_MISC_CFG);
7540 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
fce55922 7541 return 1; /* cycle on/off once per second */
b6016b76 7542
2e17e1aa 7543 case ETHTOOL_ID_ON:
7544 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7545 BNX2_EMAC_LED_1000MB_OVERRIDE |
7546 BNX2_EMAC_LED_100MB_OVERRIDE |
7547 BNX2_EMAC_LED_10MB_OVERRIDE |
7548 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7549 BNX2_EMAC_LED_TRAFFIC);
7550 break;
b6016b76 7551
2e17e1aa 7552 case ETHTOOL_ID_OFF:
7553 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7554 break;
9f52b564 7555
2e17e1aa 7556 case ETHTOOL_ID_INACTIVE:
7557 REG_WR(bp, BNX2_EMAC_LED, 0);
7558 REG_WR(bp, BNX2_MISC_CFG, bp->leds_save);
7559
7560 if (!netif_running(dev))
7561 bnx2_set_power_state(bp, PCI_D3hot);
7562 break;
7563 }
9f52b564 7564
b6016b76
MC		 7565 return 0;
7566}
7567
c8f44aff
MM		 7568static netdev_features_t
7569bnx2_fix_features(struct net_device *dev, netdev_features_t features)
4666f87a
MC		 7570{
7571 struct bnx2 *bp = netdev_priv(dev);
7572
8d7dfc2b
MM		 7573 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
7574 features |= NETIF_F_HW_VLAN_RX;
7575
7576 return features;
4666f87a
MC		 7577}
7578
fdc8541d 7579static int
c8f44aff 7580bnx2_set_features(struct net_device *dev, netdev_features_t features)
fdc8541d 7581{
7d0fd211 7582 struct bnx2 *bp = netdev_priv(dev);
7d0fd211 7583
7c810477 7584 /* TSO with VLAN tag won't work with current firmware */
8d7dfc2b
MM		 7585 if (features & NETIF_F_HW_VLAN_TX)
7586 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO);
7587 else
7588 dev->vlan_features &= ~NETIF_F_ALL_TSO;
7d0fd211 7589
8d7dfc2b 7590 if ((!!(features & NETIF_F_HW_VLAN_RX) !=
7d0fd211
JG		 7591 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
7592 netif_running(dev)) {
7593 bnx2_netif_stop(bp, false);
8d7dfc2b 7594 dev->features = features;
7d0fd211
JG		 7595 bnx2_set_rx_mode(dev);
7596 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
7597 bnx2_netif_start(bp, false);
8d7dfc2b 7598 return 1;
7d0fd211
JG		 7599 }
7600
7601 return 0;
fdc8541d
MC		 7602}
7603
7282d491 7604static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 7605 .get_settings = bnx2_get_settings,
7606 .set_settings = bnx2_set_settings,
7607 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 7608 .get_regs_len = bnx2_get_regs_len,
7609 .get_regs = bnx2_get_regs,
b6016b76
MC		 7610 .get_wol = bnx2_get_wol,
7611 .set_wol = bnx2_set_wol,
7612 .nway_reset = bnx2_nway_reset,
7959ea25 7613 .get_link = bnx2_get_link,
b6016b76
MC		 7614 .get_eeprom_len = bnx2_get_eeprom_len,
7615 .get_eeprom = bnx2_get_eeprom,
7616 .set_eeprom = bnx2_set_eeprom,
7617 .get_coalesce = bnx2_get_coalesce,
7618 .set_coalesce = bnx2_set_coalesce,
7619 .get_ringparam = bnx2_get_ringparam,
7620 .set_ringparam = bnx2_set_ringparam,
7621 .get_pauseparam = bnx2_get_pauseparam,
7622 .set_pauseparam = bnx2_set_pauseparam,
b6016b76
MC		 7623 .self_test = bnx2_self_test,
7624 .get_strings = bnx2_get_strings,
2e17e1aa 7625 .set_phys_id = bnx2_set_phys_id,
b6016b76 7626 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 7627 .get_sset_count = bnx2_get_sset_count,
b6016b76
MC		 7628};
7629
7630/* Called with rtnl_lock */
7631static int
7632bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7633{
14ab9b86 7634 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 7635 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7636 int err;
7637
7638 switch(cmd) {
7639 case SIOCGMIIPHY:
7640 data->phy_id = bp->phy_addr;
7641
7642 /* fallthru */
7643 case SIOCGMIIREG: {
7644 u32 mii_regval;
7645
583c28e5 7646 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7647 return -EOPNOTSUPP;
7648
dad3e452
MC		 7649 if (!netif_running(dev))
7650 return -EAGAIN;
7651
c770a65c 7652 spin_lock_bh(&bp->phy_lock);
b6016b76 7653 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 7654 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7655
7656 data->val_out = mii_regval;
7657
7658 return err;
7659 }
7660
7661 case SIOCSMIIREG:
583c28e5 7662 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7663 return -EOPNOTSUPP;
7664
dad3e452
MC		 7665 if (!netif_running(dev))
7666 return -EAGAIN;
7667
c770a65c 7668 spin_lock_bh(&bp->phy_lock);
b6016b76 7669 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 7670 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7671
7672 return err;
7673
7674 default:
7675 /* do nothing */
7676 break;
7677 }
7678 return -EOPNOTSUPP;
7679}
7680
7681/* Called with rtnl_lock */
7682static int
7683bnx2_change_mac_addr(struct net_device *dev, void *p)
7684{
7685 struct sockaddr *addr = p;
972ec0d4 7686 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7687
73eef4cd
MC		 7688 if (!is_valid_ether_addr(addr->sa_data))
7689 return -EINVAL;
7690
b6016b76
MC		 7691 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7692 if (netif_running(dev))
5fcaed01 7693 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 7694
7695 return 0;
7696}
7697
7698/* Called with rtnl_lock */
7699static int
7700bnx2_change_mtu(struct net_device *dev, int new_mtu)
7701{
972ec0d4 7702 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7703
7704 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7705 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7706 return -EINVAL;
7707
7708 dev->mtu = new_mtu;
807540ba 7709 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size);
b6016b76
MC		 7710}
7711
257ddbda 7712#ifdef CONFIG_NET_POLL_CONTROLLER
b6016b76
MC		 7713static void
7714poll_bnx2(struct net_device *dev)
7715{
972ec0d4 7716 struct bnx2 *bp = netdev_priv(dev);
b2af2c1d 7717 int i;
b6016b76 7718
b2af2c1d 7719 for (i = 0; i < bp->irq_nvecs; i++) {
1bf1e347
MC		 7720 struct bnx2_irq *irq = &bp->irq_tbl[i];
7721
7722 disable_irq(irq->vector);
7723 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7724 enable_irq(irq->vector);
b2af2c1d 7725 }
b6016b76
MC		 7726}
7727#endif
7728
253c8b75
MC		 7729static void __devinit
7730bnx2_get_5709_media(struct bnx2 *bp)
7731{
7732 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7733 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7734 u32 strap;
7735
7736 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7737 return;
7738 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7739 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7740 return;
7741 }
7742
7743 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7744 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7745 else
7746 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7747
7748 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7749 switch (strap) {
7750 case 0x4:
7751 case 0x5:
7752 case 0x6:
583c28e5 7753 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7754 return;
7755 }
7756 } else {
7757 switch (strap) {
7758 case 0x1:
7759 case 0x2:
7760 case 0x4:
583c28e5 7761 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7762 return;
7763 }
7764 }
7765}
7766
883e5151
MC		 7767static void __devinit
7768bnx2_get_pci_speed(struct bnx2 *bp)
7769{
7770 u32 reg;
7771
7772 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7773 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7774 u32 clkreg;
7775
f86e82fb 7776 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 7777
7778 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7779
7780 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7781 switch (clkreg) {
7782 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7783 bp->bus_speed_mhz = 133;
7784 break;
7785
7786 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7787 bp->bus_speed_mhz = 100;
7788 break;
7789
7790 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7791 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7792 bp->bus_speed_mhz = 66;
7793 break;
7794
7795 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7796 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7797 bp->bus_speed_mhz = 50;
7798 break;
7799
7800 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7801 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7802 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7803 bp->bus_speed_mhz = 33;
7804 break;
7805 }
7806 }
7807 else {
7808 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7809 bp->bus_speed_mhz = 66;
7810 else
7811 bp->bus_speed_mhz = 33;
7812 }
7813
7814 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7815 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7816
7817}
7818
76d99061
MC		 7819static void __devinit
7820bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7821{
df25bc38 7822 int rc, i, j;
76d99061 7823 u8 *data;
df25bc38 7824 unsigned int block_end, rosize, len;
76d99061 7825
012093f6
MC		 7826#define BNX2_VPD_NVRAM_OFFSET 0x300
7827#define BNX2_VPD_LEN 128
76d99061
MC		 7828#define BNX2_MAX_VER_SLEN 30
7829
7830 data = kmalloc(256, GFP_KERNEL);
7831 if (!data)
7832 return;
7833
012093f6
MC		 7834 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7835 BNX2_VPD_LEN);
76d99061
MC		 7836 if (rc)
7837 goto vpd_done;
7838
012093f6
MC		 7839 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7840 data[i] = data[i + BNX2_VPD_LEN + 3];
7841 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7842 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7843 data[i + 3] = data[i + BNX2_VPD_LEN];
76d99061
MC		 7844 }
7845
df25bc38
MC		 7846 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7847 if (i < 0)
7848 goto vpd_done;
76d99061 7849
df25bc38
MC		 7850 rosize = pci_vpd_lrdt_size(&data[i]);
7851 i += PCI_VPD_LRDT_TAG_SIZE;
7852 block_end = i + rosize;
76d99061 7853
df25bc38
MC		 7854 if (block_end > BNX2_VPD_LEN)
7855 goto vpd_done;
76d99061 7856
df25bc38
MC		 7857 j = pci_vpd_find_info_keyword(data, i, rosize,
7858 PCI_VPD_RO_KEYWORD_MFR_ID);
7859 if (j < 0)
7860 goto vpd_done;
76d99061 7861
df25bc38 7862 len = pci_vpd_info_field_size(&data[j]);
76d99061 7863
df25bc38
MC		 7864 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7865 if (j + len > block_end || len != 4 ||
7866 memcmp(&data[j], "1028", 4))
7867 goto vpd_done;
4067a854 7868
df25bc38
MC		 7869 j = pci_vpd_find_info_keyword(data, i, rosize,
7870 PCI_VPD_RO_KEYWORD_VENDOR0);
7871 if (j < 0)
7872 goto vpd_done;
4067a854 7873
df25bc38 7874 len = pci_vpd_info_field_size(&data[j]);
4067a854 7875
df25bc38
MC		 7876 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7877 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
76d99061 7878 goto vpd_done;
df25bc38
MC		 7879
7880 memcpy(bp->fw_version, &data[j], len);
7881 bp->fw_version[len] = ' ';
76d99061
MC		 7882
7883vpd_done:
7884 kfree(data);
7885}
7886
b6016b76
MC		 7887static int __devinit
7888bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7889{
7890 struct bnx2 *bp;
7891 unsigned long mem_len;
58fc2ea4 7892 int rc, i, j;
b6016b76 7893 u32 reg;
40453c83 7894 u64 dma_mask, persist_dma_mask;
cd709aa9 7895 int err;
b6016b76 7896
b6016b76 7897 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7898 bp = netdev_priv(dev);
b6016b76
MC		 7899
7900 bp->flags = 0;
7901 bp->phy_flags = 0;
7902
354fcd77
MC		 7903 bp->temp_stats_blk =
7904 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7905
7906 if (bp->temp_stats_blk == NULL) {
7907 rc = -ENOMEM;
7908 goto err_out;
7909 }
7910
b6016b76
MC		 7911 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7912 rc = pci_enable_device(pdev);
7913 if (rc) {
3a9c6a49 7914 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
b6016b76
MC		 7915 goto err_out;
7916 }
7917
7918 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7919 dev_err(&pdev->dev,
3a9c6a49 7920 "Cannot find PCI device base address, aborting\n");
b6016b76
MC		 7921 rc = -ENODEV;
7922 goto err_out_disable;
7923 }
7924
7925 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7926 if (rc) {
3a9c6a49 7927 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
b6016b76
MC		 7928 goto err_out_disable;
7929 }
7930
7931 pci_set_master(pdev);
7932
7933 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7934 if (bp->pm_cap == 0) {
9b91cf9d 7935 dev_err(&pdev->dev,
3a9c6a49 7936 "Cannot find power management capability, aborting\n");
b6016b76
MC		 7937 rc = -EIO;
7938 goto err_out_release;
7939 }
7940
b6016b76
MC		 7941 bp->dev = dev;
7942 bp->pdev = pdev;
7943
7944 spin_lock_init(&bp->phy_lock);
1b8227c4 7945 spin_lock_init(&bp->indirect_lock);
c5a88950
MC		 7946#ifdef BCM_CNIC
7947 mutex_init(&bp->cnic_lock);
7948#endif
c4028958 7949 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7950
7951 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
4edd473f 7952 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
b6016b76
MC		 7953 dev->mem_end = dev->mem_start + mem_len;
7954 dev->irq = pdev->irq;
7955
7956 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7957
7958 if (!bp->regview) {
3a9c6a49 7959 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
b6016b76
MC		 7960 rc = -ENOMEM;
7961 goto err_out_release;
7962 }
7963
be7ff1af
MC		 7964 bnx2_set_power_state(bp, PCI_D0);
7965
b6016b76
MC		 7966 /* Configure byte swap and enable write to the reg_window registers.
7967 * Rely on CPU to do target byte swapping on big endian systems
7968 * The chip's target access swapping will not swap all accesses
7969 */
be7ff1af
MC		 7970 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG,
7971 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7972 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
b6016b76
MC		 7973
7974 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7975
883e5151 7976 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
e82760e7
JM		 7977 if (!pci_is_pcie(pdev)) {
7978 dev_err(&pdev->dev, "Not PCIE, aborting\n");
883e5151
MC		 7979 rc = -EIO;
7980 goto err_out_unmap;
7981 }
f86e82fb 7982 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7983 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7984 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
c239f279
MC		 7985
7986 /* AER (Advanced Error Reporting) hooks */
7987 err = pci_enable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 7988 if (!err)
7989 bp->flags |= BNX2_FLAG_AER_ENABLED;
c239f279 7990
883e5151 7991 } else {
59b47d8a
MC		 7992 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7993 if (bp->pcix_cap == 0) {
7994 dev_err(&pdev->dev,
3a9c6a49 7995 "Cannot find PCIX capability, aborting\n");
59b47d8a
MC		 7996 rc = -EIO;
7997 goto err_out_unmap;
7998 }
61d9e3fa 7999 bp->flags |= BNX2_FLAG_BROKEN_STATS;
59b47d8a
MC		 8000 }
8001
b4b36042
MC		 8002 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
8003 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 8004 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 8005 }
8006
8e6a72c4
MC		 8007 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
8008 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 8009 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 8010 }
8011
40453c83
MC		 8012 /* 5708 cannot support DMA addresses > 40-bit. */
8013 if (CHIP_NUM(bp) == CHIP_NUM_5708)
50cf156a 8014 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
40453c83 8015 else
6a35528a 8016 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
40453c83
MC		 8017
8018 /* Configure DMA attributes. */
8019 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
8020 dev->features |= NETIF_F_HIGHDMA;
8021 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
8022 if (rc) {
8023 dev_err(&pdev->dev,
3a9c6a49 8024 "pci_set_consistent_dma_mask failed, aborting\n");
40453c83
MC		 8025 goto err_out_unmap;
8026 }
284901a9 8027 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3a9c6a49 8028 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
40453c83
MC		 8029 goto err_out_unmap;
8030 }
8031
f86e82fb 8032 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 8033 bnx2_get_pci_speed(bp);
b6016b76
MC		 8034
8035 /* 5706A0 may falsely detect SERR and PERR. */
8036 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8037 reg = REG_RD(bp, PCI_COMMAND);
8038 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
8039 REG_WR(bp, PCI_COMMAND, reg);
8040 }
8041 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 8042 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 8043
9b91cf9d 8044 dev_err(&pdev->dev,
3a9c6a49 8045 "5706 A1 can only be used in a PCIX bus, aborting\n");
b6016b76
MC		 8046 goto err_out_unmap;
8047 }
8048
8049 bnx2_init_nvram(bp);
8050
2726d6e1 8051 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 8052
8053 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 8054 BNX2_SHM_HDR_SIGNATURE_SIG) {
8055 u32 off = PCI_FUNC(pdev->devfn) << 2;
8056
2726d6e1 8057 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 8058 } else
e3648b3d
MC		 8059 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8060
b6016b76
MC		 8061 /* Get the permanent MAC address. First we need to make sure the
8062 * firmware is actually running.
8063 */
2726d6e1 8064 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 8065
8066 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8067 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
3a9c6a49 8068 dev_err(&pdev->dev, "Firmware not running, aborting\n");
b6016b76
MC		 8069 rc = -ENODEV;
8070 goto err_out_unmap;
8071 }
8072
76d99061
MC		 8073 bnx2_read_vpd_fw_ver(bp);
8074
8075 j = strlen(bp->fw_version);
2726d6e1 8076 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
76d99061 8077 for (i = 0; i < 3 && j < 24; i++) {
58fc2ea4
MC		 8078 u8 num, k, skip0;
8079
76d99061
MC		 8080 if (i == 0) {
8081 bp->fw_version[j++] = 'b';
8082 bp->fw_version[j++] = 'c';
8083 bp->fw_version[j++] = ' ';
8084 }
58fc2ea4
MC		 8085 num = (u8) (reg >> (24 - (i * 8)));
8086 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8087 if (num >= k || !skip0 || k == 1) {
8088 bp->fw_version[j++] = (num / k) + '0';
8089 skip0 = 0;
8090 }
8091 }
8092 if (i != 2)
8093 bp->fw_version[j++] = '.';
8094 }
2726d6e1 8095 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 8096 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8097 bp->wol = 1;
8098
8099 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 8100 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 8101
8102 for (i = 0; i < 30; i++) {
2726d6e1 8103 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 8104 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8105 break;
8106 msleep(10);
8107 }
8108 }
2726d6e1 8109 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 8110 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8111 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8112 reg != BNX2_CONDITION_MFW_RUN_NONE) {
2726d6e1 8113 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4 8114
76d99061
MC		 8115 if (j < 32)
8116 bp->fw_version[j++] = ' ';
8117 for (i = 0; i < 3 && j < 28; i++) {
2726d6e1 8118 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
3aeb7d22 8119 reg = be32_to_cpu(reg);
58fc2ea4
MC		 8120 memcpy(&bp->fw_version[j], &reg, 4);
8121 j += 4;
8122 }
8123 }
b6016b76 8124
2726d6e1 8125 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 8126 bp->mac_addr[0] = (u8) (reg >> 8);
8127 bp->mac_addr[1] = (u8) reg;
8128
2726d6e1 8129 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 8130 bp->mac_addr[2] = (u8) (reg >> 24);
8131 bp->mac_addr[3] = (u8) (reg >> 16);
8132 bp->mac_addr[4] = (u8) (reg >> 8);
8133 bp->mac_addr[5] = (u8) reg;
8134
8135 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 8136 bnx2_set_rx_ring_size(bp, 255);
b6016b76 8137
cf7474a6 8138 bp->tx_quick_cons_trip_int = 2;
b6016b76 8139 bp->tx_quick_cons_trip = 20;
cf7474a6 8140 bp->tx_ticks_int = 18;
b6016b76 8141 bp->tx_ticks = 80;
6aa20a22 8142
cf7474a6
MC		 8143 bp->rx_quick_cons_trip_int = 2;
8144 bp->rx_quick_cons_trip = 12;
b6016b76
MC		 8145 bp->rx_ticks_int = 18;
8146 bp->rx_ticks = 18;
8147
7ea6920e 8148 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76 8149
ac392abc 8150 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 8151
5b0c76ad
MC		 8152 bp->phy_addr = 1;
8153
b6016b76 8154 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 8155 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8156 bnx2_get_5709_media(bp);
8157 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 8158 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 8159
0d8a6571 8160 bp->phy_port = PORT_TP;
583c28e5 8161 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 8162 bp->phy_port = PORT_FIBRE;
2726d6e1 8163 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 8164 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 8165 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8166 bp->wol = 0;
8167 }
38ea3686
MC		 8168 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8169 /* Don't do parallel detect on this board because of
8170 * some board problems. The link will not go down
8171 * if we do parallel detect.
8172 */
8173 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8174 pdev->subsystem_device == 0x310c)
8175 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8176 } else {
5b0c76ad 8177 bp->phy_addr = 2;
5b0c76ad 8178 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 8179 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 8180 }
261dd5ca
MC		 8181 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8182 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 8183 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 8184 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8185 (CHIP_REV(bp) == CHIP_REV_Ax ||
8186 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 8187 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 8188
7c62e83b
MC		 8189 bnx2_init_fw_cap(bp);
8190
16088272
MC		 8191 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8192 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
5ec6d7bf
MC		 8193 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8194 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
f86e82fb 8195 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8196 bp->wol = 0;
8197 }
dda1e390 8198
b6016b76
MC		 8199 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8200 bp->tx_quick_cons_trip_int =
8201 bp->tx_quick_cons_trip;
8202 bp->tx_ticks_int = bp->tx_ticks;
8203 bp->rx_quick_cons_trip_int =
8204 bp->rx_quick_cons_trip;
8205 bp->rx_ticks_int = bp->rx_ticks;
8206 bp->comp_prod_trip_int = bp->comp_prod_trip;
8207 bp->com_ticks_int = bp->com_ticks;
8208 bp->cmd_ticks_int = bp->cmd_ticks;
8209 }
8210
f9317a40
MC		 8211 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8212 *
8213 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8214 * with byte enables disabled on the unused 32-bit word. This is legal
8215 * but causes problems on the AMD 8132 which will eventually stop
8216 * responding after a while.
8217 *
8218 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 8219 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 8220 */
8221 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8222 struct pci_dev *amd_8132 = NULL;
8223
8224 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8225 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8226 amd_8132))) {
f9317a40 8227
44c10138
AK		 8228 if (amd_8132->revision >= 0x10 &&
8229 amd_8132->revision <= 0x13) {
f9317a40
MC		 8230 disable_msi = 1;
8231 pci_dev_put(amd_8132);
8232 break;
8233 }
8234 }
8235 }
8236
deaf391b 8237 bnx2_set_default_link(bp);
b6016b76
MC		 8238 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8239
cd339a0e 8240 init_timer(&bp->timer);
ac392abc 8241 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
cd339a0e
MC		 8242 bp->timer.data = (unsigned long) bp;
8243 bp->timer.function = bnx2_timer;
8244
7625eb2f 8245#ifdef BCM_CNIC
41c2178a
MC		 8246 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
8247 bp->cnic_eth_dev.max_iscsi_conn =
8248 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
8249 BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT;
7625eb2f 8250#endif
c239f279
MC		 8251 pci_save_state(pdev);
8252
b6016b76
MC		 8253 return 0;
8254
8255err_out_unmap:
4bb9ebc7 8256 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
c239f279 8257 pci_disable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8258 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8259 }
c239f279 8260
b6016b76
MC		 8261 if (bp->regview) {
8262 iounmap(bp->regview);
73eef4cd 8263 bp->regview = NULL;
b6016b76
MC		 8264 }
8265
8266err_out_release:
8267 pci_release_regions(pdev);
8268
8269err_out_disable:
8270 pci_disable_device(pdev);
8271 pci_set_drvdata(pdev, NULL);
8272
8273err_out:
8274 return rc;
8275}
8276
883e5151
MC		 8277static char * __devinit
8278bnx2_bus_string(struct bnx2 *bp, char *str)
8279{
8280 char *s = str;
8281
f86e82fb 8282 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 8283 s += sprintf(s, "PCI Express");
8284 } else {
8285 s += sprintf(s, "PCI");
f86e82fb 8286 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 8287 s += sprintf(s, "-X");
f86e82fb 8288 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 8289 s += sprintf(s, " 32-bit");
8290 else
8291 s += sprintf(s, " 64-bit");
8292 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8293 }
8294 return str;
8295}
8296
f048fa9c
MC		 8297static void
8298bnx2_del_napi(struct bnx2 *bp)
8299{
8300 int i;
8301
8302 for (i = 0; i < bp->irq_nvecs; i++)
8303 netif_napi_del(&bp->bnx2_napi[i].napi);
8304}
8305
8306static void
35efa7c1
MC		 8307bnx2_init_napi(struct bnx2 *bp)
8308{
b4b36042 8309 int i;
35efa7c1 8310
4327ba43 8311 for (i = 0; i < bp->irq_nvecs; i++) {
35e9010b
MC		 8312 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8313 int (*poll)(struct napi_struct *, int);
8314
8315 if (i == 0)
8316 poll = bnx2_poll;
8317 else
f0ea2e63 8318 poll = bnx2_poll_msix;
35e9010b
MC		 8319
8320 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
b4b36042
MC		 8321 bnapi->bp = bp;
8322 }
35efa7c1
MC		 8323}
8324
0421eae6
SH		 8325static const struct net_device_ops bnx2_netdev_ops = {
8326 .ndo_open = bnx2_open,
8327 .ndo_start_xmit = bnx2_start_xmit,
8328 .ndo_stop = bnx2_close,
5d07bf26 8329 .ndo_get_stats64 = bnx2_get_stats64,
0421eae6
SH		 8330 .ndo_set_rx_mode = bnx2_set_rx_mode,
8331 .ndo_do_ioctl = bnx2_ioctl,
8332 .ndo_validate_addr = eth_validate_addr,
8333 .ndo_set_mac_address = bnx2_change_mac_addr,
8334 .ndo_change_mtu = bnx2_change_mtu,
8d7dfc2b
MM		 8335 .ndo_fix_features = bnx2_fix_features,
8336 .ndo_set_features = bnx2_set_features,
0421eae6 8337 .ndo_tx_timeout = bnx2_tx_timeout,
257ddbda 8338#ifdef CONFIG_NET_POLL_CONTROLLER
0421eae6
SH		 8339 .ndo_poll_controller = poll_bnx2,
8340#endif
8341};
8342
b6016b76
MC		 8343static int __devinit
8344bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8345{
8346 static int version_printed = 0;
8347 struct net_device *dev = NULL;
8348 struct bnx2 *bp;
0795af57 8349 int rc;
883e5151 8350 char str[40];
b6016b76
MC		 8351
8352 if (version_printed++ == 0)
3a9c6a49 8353 pr_info("%s", version);
b6016b76
MC		 8354
8355 /* dev zeroed in init_etherdev */
706bf240 8356 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
b6016b76
MC		 8357
8358 if (!dev)
8359 return -ENOMEM;
8360
8361 rc = bnx2_init_board(pdev, dev);
8362 if (rc < 0) {
8363 free_netdev(dev);
8364 return rc;
8365 }
8366
0421eae6 8367 dev->netdev_ops = &bnx2_netdev_ops;
b6016b76 8368 dev->watchdog_timeo = TX_TIMEOUT;
b6016b76 8369 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 8370
972ec0d4 8371 bp = netdev_priv(dev);
b6016b76 8372
1b2f922f
MC		 8373 pci_set_drvdata(pdev, dev);
8374
8375 memcpy(dev->dev_addr, bp->mac_addr, 6);
8376 memcpy(dev->perm_addr, bp->mac_addr, 6);
1b2f922f 8377
8d7dfc2b
MM		 8378 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
8379 NETIF_F_TSO | NETIF_F_TSO_ECN |
8380 NETIF_F_RXHASH | NETIF_F_RXCSUM;
8381
8382 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8383 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8384
8385 dev->vlan_features = dev->hw_features;
8386 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8387 dev->features |= dev->hw_features;
01789349 8388 dev->priv_flags |= IFF_UNICAST_FLT;
8d7dfc2b 8389
b6016b76 8390 if ((rc = register_netdev(dev))) {
9b91cf9d 8391 dev_err(&pdev->dev, "Cannot register net device\n");
57579f76 8392 goto error;
b6016b76
MC		 8393 }
8394
3a9c6a49
JP		 8395 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8396 board_info[ent->driver_data].name,
8397 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8398 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8399 bnx2_bus_string(bp, str),
8400 dev->base_addr,
8401 bp->pdev->irq, dev->dev_addr);
b6016b76 8402
b6016b76 8403 return 0;
57579f76
MC		 8404
8405error:
57579f76
MC		 8406 if (bp->regview)
8407 iounmap(bp->regview);
8408 pci_release_regions(pdev);
8409 pci_disable_device(pdev);
8410 pci_set_drvdata(pdev, NULL);
8411 free_netdev(dev);
8412 return rc;
b6016b76
MC		 8413}
8414
8415static void __devexit
8416bnx2_remove_one(struct pci_dev *pdev)
8417{
8418 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8419 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 8420
8421 unregister_netdev(dev);
8422
8333a46a 8423 del_timer_sync(&bp->timer);
cd634019 8424 cancel_work_sync(&bp->reset_task);
8333a46a 8425
b6016b76
MC		 8426 if (bp->regview)
8427 iounmap(bp->regview);
8428
354fcd77
MC		 8429 kfree(bp->temp_stats_blk);
8430
4bb9ebc7 8431 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
c239f279 8432 pci_disable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8433 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8434 }
cd709aa9 8435
7880b72e 8436 bnx2_release_firmware(bp);
8437
c239f279 8438 free_netdev(dev);
cd709aa9 8439
b6016b76
MC		 8440 pci_release_regions(pdev);
8441 pci_disable_device(pdev);
8442 pci_set_drvdata(pdev, NULL);
8443}
8444
8445static int
829ca9a3 8446bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 8447{
8448 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8449 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8450
6caebb02
MC		 8451 /* PCI register 4 needs to be saved whether netif_running() or not.
8452 * MSI address and data need to be saved if using MSI and
8453 * netif_running().
8454 */
8455 pci_save_state(pdev);
b6016b76
MC		 8456 if (!netif_running(dev))
8457 return 0;
8458
23f333a2 8459 cancel_work_sync(&bp->reset_task);
212f9934 8460 bnx2_netif_stop(bp, true);
b6016b76
MC		 8461 netif_device_detach(dev);
8462 del_timer_sync(&bp->timer);
74bf4ba3 8463 bnx2_shutdown_chip(bp);
b6016b76 8464 bnx2_free_skbs(bp);
829ca9a3 8465 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 8466 return 0;
8467}
8468
8469static int
8470bnx2_resume(struct pci_dev *pdev)
8471{
8472 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8473 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8474
6caebb02 8475 pci_restore_state(pdev);
b6016b76
MC		 8476 if (!netif_running(dev))
8477 return 0;
8478
829ca9a3 8479 bnx2_set_power_state(bp, PCI_D0);
b6016b76 8480 netif_device_attach(dev);
9a120bc5 8481 bnx2_init_nic(bp, 1);
212f9934 8482 bnx2_netif_start(bp, true);
b6016b76
MC		 8483 return 0;
8484}
8485
6ff2da49
WX		 8486/**
8487 * bnx2_io_error_detected - called when PCI error is detected
8488 * @pdev: Pointer to PCI device
8489 * @state: The current pci connection state
8490 *
8491 * This function is called after a PCI bus error affecting
8492 * this device has been detected.
8493 */
8494static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8495 pci_channel_state_t state)
8496{
8497 struct net_device *dev = pci_get_drvdata(pdev);
8498 struct bnx2 *bp = netdev_priv(dev);
8499
8500 rtnl_lock();
8501 netif_device_detach(dev);
8502
2ec3de26
DN		 8503 if (state == pci_channel_io_perm_failure) {
8504 rtnl_unlock();
8505 return PCI_ERS_RESULT_DISCONNECT;
8506 }
8507
6ff2da49 8508 if (netif_running(dev)) {
212f9934 8509 bnx2_netif_stop(bp, true);
6ff2da49
WX		 8510 del_timer_sync(&bp->timer);
8511 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8512 }
8513
8514 pci_disable_device(pdev);
8515 rtnl_unlock();
8516
8517 /* Request a slot slot reset. */
8518 return PCI_ERS_RESULT_NEED_RESET;
8519}
8520
8521/**
8522 * bnx2_io_slot_reset - called after the pci bus has been reset.
8523 * @pdev: Pointer to PCI device
8524 *
8525 * Restart the card from scratch, as if from a cold-boot.
8526 */
8527static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8528{
8529 struct net_device *dev = pci_get_drvdata(pdev);
8530 struct bnx2 *bp = netdev_priv(dev);
cd709aa9
JF		 8531 pci_ers_result_t result;
8532 int err;
6ff2da49
WX		 8533
8534 rtnl_lock();
8535 if (pci_enable_device(pdev)) {
8536 dev_err(&pdev->dev,
3a9c6a49 8537 "Cannot re-enable PCI device after reset\n");
cd709aa9
JF		 8538 result = PCI_ERS_RESULT_DISCONNECT;
8539 } else {
8540 pci_set_master(pdev);
8541 pci_restore_state(pdev);
8542 pci_save_state(pdev);
8543
8544 if (netif_running(dev)) {
8545 bnx2_set_power_state(bp, PCI_D0);
8546 bnx2_init_nic(bp, 1);
8547 }
8548 result = PCI_ERS_RESULT_RECOVERED;
6ff2da49 8549 }
cd709aa9 8550 rtnl_unlock();
6ff2da49 8551
4bb9ebc7 8552 if (!(bp->flags & BNX2_FLAG_AER_ENABLED))
c239f279
MC		 8553 return result;
8554
cd709aa9
JF		 8555 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8556 if (err) {
8557 dev_err(&pdev->dev,
8558 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8559 err); /* non-fatal, continue */
6ff2da49
WX		 8560 }
8561
cd709aa9 8562 return result;
6ff2da49
WX		 8563}
8564
8565/**
8566 * bnx2_io_resume - called when traffic can start flowing again.
8567 * @pdev: Pointer to PCI device
8568 *
8569 * This callback is called when the error recovery driver tells us that
8570 * its OK to resume normal operation.
8571 */
8572static void bnx2_io_resume(struct pci_dev *pdev)
8573{
8574 struct net_device *dev = pci_get_drvdata(pdev);
8575 struct bnx2 *bp = netdev_priv(dev);
8576
8577 rtnl_lock();
8578 if (netif_running(dev))
212f9934 8579 bnx2_netif_start(bp, true);
6ff2da49
WX		 8580
8581 netif_device_attach(dev);
8582 rtnl_unlock();
8583}
8584
8585static struct pci_error_handlers bnx2_err_handler = {
8586 .error_detected = bnx2_io_error_detected,
8587 .slot_reset = bnx2_io_slot_reset,
8588 .resume = bnx2_io_resume,
8589};
8590
b6016b76 8591static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 8592 .name = DRV_MODULE_NAME,
8593 .id_table = bnx2_pci_tbl,
8594 .probe = bnx2_init_one,
8595 .remove = __devexit_p(bnx2_remove_one),
8596 .suspend = bnx2_suspend,
8597 .resume = bnx2_resume,
6ff2da49 8598 .err_handler = &bnx2_err_handler,
b6016b76
MC		 8599};
8600
8601static int __init bnx2_init(void)
8602{
29917620 8603 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 8604}
8605
8606static void __exit bnx2_cleanup(void)
8607{
8608 pci_unregister_driver(&bnx2_pci_driver);
8609}
8610
8611module_init(bnx2_init);
8612module_exit(bnx2_cleanup);
8613
8614
8615
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