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Repair wrong named definition aligned_u64
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
dc187cb3 3 * Copyright (c) 2004-2011 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
3a9c6a49 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
f2a4f052
MC		 13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16
17#include <linux/kernel.h>
18#include <linux/timer.h>
19#include <linux/errno.h>
20#include <linux/ioport.h>
21#include <linux/slab.h>
22#include <linux/vmalloc.h>
23#include <linux/interrupt.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28#include <linux/skbuff.h>
29#include <linux/dma-mapping.h>
1977f032 30#include <linux/bitops.h>
f2a4f052
MC		 31#include <asm/io.h>
32#include <asm/irq.h>
33#include <linux/delay.h>
34#include <asm/byteorder.h>
c86a31f4 35#include <asm/page.h>
f2a4f052
MC		 36#include <linux/time.h>
37#include <linux/ethtool.h>
38#include <linux/mii.h>
01789349 39#include <linux/if.h>
f2a4f052 40#include <linux/if_vlan.h>
f2a4f052 41#include <net/ip.h>
de081fa5 42#include <net/tcp.h>
f2a4f052 43#include <net/checksum.h>
f2a4f052
MC		 44#include <linux/workqueue.h>
45#include <linux/crc32.h>
46#include <linux/prefetch.h>
29b12174 47#include <linux/cache.h>
57579f76 48#include <linux/firmware.h>
706bf240 49#include <linux/log2.h>
cd709aa9 50#include <linux/aer.h>
f2a4f052 51
4edd473f
MC		 52#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
53#define BCM_CNIC 1
54#include "cnic_if.h"
55#endif
b6016b76
MC		 56#include "bnx2.h"
57#include "bnx2_fw.h"
b3448b0b 58
b6016b76 59#define DRV_MODULE_NAME "bnx2"
3aeb7d22
MC		 60#define DRV_MODULE_VERSION "2.1.11"
61#define DRV_MODULE_RELDATE "July 20, 2011"
0268102d 62#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.1.fw"
22fa159d 63#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
dc187cb3 64#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1a.fw"
22fa159d
MC		 65#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
66#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
b6016b76
MC		 67
68#define RUN_AT(x) (jiffies + (x))
69
70/* Time in jiffies before concluding the transmitter is hung. */
71#define TX_TIMEOUT (5*HZ)
72
fefa8645 73static char version[] __devinitdata =
b6016b76
MC		 74 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
75
76MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
453a9c6e 77MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
b6016b76
MC		 78MODULE_LICENSE("GPL");
79MODULE_VERSION(DRV_MODULE_VERSION);
57579f76
MC		 80MODULE_FIRMWARE(FW_MIPS_FILE_06);
81MODULE_FIRMWARE(FW_RV2P_FILE_06);
82MODULE_FIRMWARE(FW_MIPS_FILE_09);
83MODULE_FIRMWARE(FW_RV2P_FILE_09);
078b0735 84MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
b6016b76
MC		 85
86static int disable_msi = 0;
87
88module_param(disable_msi, int, 0);
89MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
90
91typedef enum {
92 BCM5706 = 0,
93 NC370T,
94 NC370I,
95 BCM5706S,
96 NC370F,
5b0c76ad
MC		 97 BCM5708,
98 BCM5708S,
bac0dff6 99 BCM5709,
27a005b8 100 BCM5709S,
7bb0a04f 101 BCM5716,
1caacecb 102 BCM5716S,
b6016b76
MC		 103} board_t;
104
105/* indexed by board_t, above */
fefa8645 106static struct {
b6016b76
MC		 107 char *name;
108} board_info[] __devinitdata = {
109 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
110 { "HP NC370T Multifunction Gigabit Server Adapter" },
111 { "HP NC370i Multifunction Gigabit Server Adapter" },
112 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
113 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 114 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
115 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 116 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 117 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
7bb0a04f 118 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
1caacecb 119 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
b6016b76
MC		 120 };
121
7bb0a04f 122static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
b6016b76
MC		 123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
124 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
126 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
132 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
133 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 135 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 137 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 139 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
7bb0a04f
MC		 141 { PCI_VENDOR_ID_BROADCOM, 0x163b,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
1caacecb 143 { PCI_VENDOR_ID_BROADCOM, 0x163c,
1f2435e5 144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
b6016b76
MC		 145 { 0, }
146};
147
0ced9d01 148static const struct flash_spec flash_table[] =
b6016b76 149{
e30372c9
MC		 150#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
151#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 152 /* Slow EEPROM */
37137709 153 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 154 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 155 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
156 "EEPROM - slow"},
37137709
MC		 157 /* Expansion entry 0001 */
158 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 159 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 160 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
161 "Entry 0001"},
b6016b76
MC		 162 /* Saifun SA25F010 (non-buffered flash) */
163 /* strap, cfg1, & write1 need updates */
37137709 164 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 165 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 166 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
167 "Non-buffered flash (128kB)"},
168 /* Saifun SA25F020 (non-buffered flash) */
169 /* strap, cfg1, & write1 need updates */
37137709 170 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 171 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 172 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
173 "Non-buffered flash (256kB)"},
37137709
MC		 174 /* Expansion entry 0100 */
175 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
178 "Entry 0100"},
179 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 180 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 181 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 182 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
183 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
184 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
185 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 186 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 187 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
188 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
189 /* Saifun SA25F005 (non-buffered flash) */
190 /* strap, cfg1, & write1 need updates */
191 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 192 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 193 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
194 "Non-buffered flash (64kB)"},
195 /* Fast EEPROM */
196 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 197 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 198 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
199 "EEPROM - fast"},
200 /* Expansion entry 1001 */
201 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 202 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 203 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
204 "Entry 1001"},
205 /* Expansion entry 1010 */
206 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 208 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
209 "Entry 1010"},
210 /* ATMEL AT45DB011B (buffered flash) */
211 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 212 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 213 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
214 "Buffered flash (128kB)"},
215 /* Expansion entry 1100 */
216 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 217 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 218 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
219 "Entry 1100"},
220 /* Expansion entry 1101 */
221 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 222 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 223 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
224 "Entry 1101"},
225 /* Ateml Expansion entry 1110 */
226 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 227 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 228 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
229 "Entry 1110 (Atmel)"},
230 /* ATMEL AT45DB021B (buffered flash) */
231 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 232 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 233 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
234 "Buffered flash (256kB)"},
b6016b76
MC		 235};
236
0ced9d01 237static const struct flash_spec flash_5709 = {
e30372c9
MC		 238 .flags = BNX2_NV_BUFFERED,
239 .page_bits = BCM5709_FLASH_PAGE_BITS,
240 .page_size = BCM5709_FLASH_PAGE_SIZE,
241 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
242 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
243 .name = "5709 Buffered flash (256kB)",
244};
245
b6016b76
MC		 246MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
247
4327ba43 248static void bnx2_init_napi(struct bnx2 *bp);
f048fa9c 249static void bnx2_del_napi(struct bnx2 *bp);
4327ba43 250
35e9010b 251static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
e89bbf10 252{
2f8af120 253 u32 diff;
e89bbf10 254
11848b96
MC		 255 /* Tell compiler to fetch tx_prod and tx_cons from memory. */
256 barrier();
faac9c4b
MC		 257
258 /* The ring uses 256 indices for 255 entries, one of them
259 * needs to be skipped.
260 */
35e9010b 261 diff = txr->tx_prod - txr->tx_cons;
faac9c4b
MC		 262 if (unlikely(diff >= TX_DESC_CNT)) {
263 diff &= 0xffff;
264 if (diff == TX_DESC_CNT)
265 diff = MAX_TX_DESC_CNT;
266 }
807540ba 267 return bp->tx_ring_size - diff;
e89bbf10
MC		 268}
269
b6016b76
MC		 270static u32
271bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
272{
1b8227c4
MC		 273 u32 val;
274
275 spin_lock_bh(&bp->indirect_lock);
b6016b76 276 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 277 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
278 spin_unlock_bh(&bp->indirect_lock);
279 return val;
b6016b76
MC		 280}
281
282static void
283bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
284{
1b8227c4 285 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 288 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 289}
290
2726d6e1
MC		 291static void
292bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
293{
294 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
295}
296
297static u32
298bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
299{
807540ba 300 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
2726d6e1
MC		 301}
302
b6016b76
MC		 303static void
304bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
305{
306 offset += cid_addr;
1b8227c4 307 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 308 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
309 int i;
310
311 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
312 REG_WR(bp, BNX2_CTX_CTX_CTRL,
313 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
314 for (i = 0; i < 5; i++) {
59b47d8a
MC		 315 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
316 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
317 break;
318 udelay(5);
319 }
320 } else {
321 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
322 REG_WR(bp, BNX2_CTX_DATA, val);
323 }
1b8227c4 324 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 325}
326
4edd473f
MC		 327#ifdef BCM_CNIC
328static int
329bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
330{
331 struct bnx2 *bp = netdev_priv(dev);
332 struct drv_ctl_io *io = &info->data.io;
333
334 switch (info->cmd) {
335 case DRV_CTL_IO_WR_CMD:
336 bnx2_reg_wr_ind(bp, io->offset, io->data);
337 break;
338 case DRV_CTL_IO_RD_CMD:
339 io->data = bnx2_reg_rd_ind(bp, io->offset);
340 break;
341 case DRV_CTL_CTX_WR_CMD:
342 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
343 break;
344 default:
345 return -EINVAL;
346 }
347 return 0;
348}
349
350static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
351{
352 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
353 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
354 int sb_id;
355
356 if (bp->flags & BNX2_FLAG_USING_MSIX) {
357 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
358 bnapi->cnic_present = 0;
359 sb_id = bp->irq_nvecs;
360 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
361 } else {
362 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
363 bnapi->cnic_tag = bnapi->last_status_idx;
364 bnapi->cnic_present = 1;
365 sb_id = 0;
366 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
367 }
368
369 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
370 cp->irq_arr[0].status_blk = (void *)
371 ((unsigned long) bnapi->status_blk.msi +
372 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
373 cp->irq_arr[0].status_blk_num = sb_id;
374 cp->num_irq = 1;
375}
376
377static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
378 void *data)
379{
380 struct bnx2 *bp = netdev_priv(dev);
381 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
382
383 if (ops == NULL)
384 return -EINVAL;
385
386 if (cp->drv_state & CNIC_DRV_STATE_REGD)
387 return -EBUSY;
388
41c2178a
MC		 389 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))
390 return -ENODEV;
391
4edd473f
MC		 392 bp->cnic_data = data;
393 rcu_assign_pointer(bp->cnic_ops, ops);
394
395 cp->num_irq = 0;
396 cp->drv_state = CNIC_DRV_STATE_REGD;
397
398 bnx2_setup_cnic_irq_info(bp);
399
400 return 0;
401}
402
403static int bnx2_unregister_cnic(struct net_device *dev)
404{
405 struct bnx2 *bp = netdev_priv(dev);
406 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
407 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
408
c5a88950 409 mutex_lock(&bp->cnic_lock);
4edd473f
MC		 410 cp->drv_state = 0;
411 bnapi->cnic_present = 0;
412 rcu_assign_pointer(bp->cnic_ops, NULL);
c5a88950 413 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 414 synchronize_rcu();
415 return 0;
416}
417
418struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
419{
420 struct bnx2 *bp = netdev_priv(dev);
421 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
422
7625eb2f
MC		 423 if (!cp->max_iscsi_conn)
424 return NULL;
425
4edd473f
MC		 426 cp->drv_owner = THIS_MODULE;
427 cp->chip_id = bp->chip_id;
428 cp->pdev = bp->pdev;
429 cp->io_base = bp->regview;
430 cp->drv_ctl = bnx2_drv_ctl;
431 cp->drv_register_cnic = bnx2_register_cnic;
432 cp->drv_unregister_cnic = bnx2_unregister_cnic;
433
434 return cp;
435}
436EXPORT_SYMBOL(bnx2_cnic_probe);
437
438static void
439bnx2_cnic_stop(struct bnx2 *bp)
440{
441 struct cnic_ops *c_ops;
442 struct cnic_ctl_info info;
443
c5a88950 444 mutex_lock(&bp->cnic_lock);
13707f9e
ED		 445 c_ops = rcu_dereference_protected(bp->cnic_ops,
446 lockdep_is_held(&bp->cnic_lock));
4edd473f
MC		 447 if (c_ops) {
448 info.cmd = CNIC_CTL_STOP_CMD;
449 c_ops->cnic_ctl(bp->cnic_data, &info);
450 }
c5a88950 451 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 452}
453
454static void
455bnx2_cnic_start(struct bnx2 *bp)
456{
457 struct cnic_ops *c_ops;
458 struct cnic_ctl_info info;
459
c5a88950 460 mutex_lock(&bp->cnic_lock);
13707f9e
ED		 461 c_ops = rcu_dereference_protected(bp->cnic_ops,
462 lockdep_is_held(&bp->cnic_lock));
4edd473f
MC		 463 if (c_ops) {
464 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
465 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
466
467 bnapi->cnic_tag = bnapi->last_status_idx;
468 }
469 info.cmd = CNIC_CTL_START_CMD;
470 c_ops->cnic_ctl(bp->cnic_data, &info);
471 }
c5a88950 472 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 473}
474
475#else
476
477static void
478bnx2_cnic_stop(struct bnx2 *bp)
479{
480}
481
482static void
483bnx2_cnic_start(struct bnx2 *bp)
484{
485}
486
487#endif
488
b6016b76
MC		 489static int
490bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
491{
492 u32 val1;
493 int i, ret;
494
583c28e5 495 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 496 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
497 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
498
499 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
500 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
501
502 udelay(40);
503 }
504
505 val1 = (bp->phy_addr << 21) | (reg << 16) |
506 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
507 BNX2_EMAC_MDIO_COMM_START_BUSY;
508 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
509
510 for (i = 0; i < 50; i++) {
511 udelay(10);
512
513 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
514 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
515 udelay(5);
516
517 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
518 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
519
520 break;
521 }
522 }
523
524 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
525 *val = 0x0;
526 ret = -EBUSY;
527 }
528 else {
529 *val = val1;
530 ret = 0;
531 }
532
583c28e5 533 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 534 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
535 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
536
537 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
538 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
539
540 udelay(40);
541 }
542
543 return ret;
544}
545
546static int
547bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
548{
549 u32 val1;
550 int i, ret;
551
583c28e5 552 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 553 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
554 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
555
556 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
557 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
558
559 udelay(40);
560 }
561
562 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
563 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
564 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
565 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 566
b6016b76
MC		 567 for (i = 0; i < 50; i++) {
568 udelay(10);
569
570 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
571 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
572 udelay(5);
573 break;
574 }
575 }
576
577 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
578 ret = -EBUSY;
579 else
580 ret = 0;
581
583c28e5 582 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 583 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
584 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
585
586 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
587 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
588
589 udelay(40);
590 }
591
592 return ret;
593}
594
595static void
596bnx2_disable_int(struct bnx2 *bp)
597{
b4b36042
MC		 598 int i;
599 struct bnx2_napi *bnapi;
600
601 for (i = 0; i < bp->irq_nvecs; i++) {
602 bnapi = &bp->bnx2_napi[i];
603 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
604 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
605 }
b6016b76
MC		 606 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
607}
608
609static void
610bnx2_enable_int(struct bnx2 *bp)
611{
b4b36042
MC		 612 int i;
613 struct bnx2_napi *bnapi;
35efa7c1 614
b4b36042
MC		 615 for (i = 0; i < bp->irq_nvecs; i++) {
616 bnapi = &bp->bnx2_napi[i];
1269a8a6 617
b4b36042
MC		 618 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
619 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
620 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
621 bnapi->last_status_idx);
b6016b76 622
b4b36042
MC		 623 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
624 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
625 bnapi->last_status_idx);
626 }
bf5295bb 627 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 628}
629
630static void
631bnx2_disable_int_sync(struct bnx2 *bp)
632{
b4b36042
MC		 633 int i;
634
b6016b76 635 atomic_inc(&bp->intr_sem);
3767546c
MC		 636 if (!netif_running(bp->dev))
637 return;
638
b6016b76 639 bnx2_disable_int(bp);
b4b36042
MC		 640 for (i = 0; i < bp->irq_nvecs; i++)
641 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 642}
643
35efa7c1
MC		 644static void
645bnx2_napi_disable(struct bnx2 *bp)
646{
b4b36042
MC		 647 int i;
648
649 for (i = 0; i < bp->irq_nvecs; i++)
650 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 651}
652
653static void
654bnx2_napi_enable(struct bnx2 *bp)
655{
b4b36042
MC		 656 int i;
657
658 for (i = 0; i < bp->irq_nvecs; i++)
659 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 660}
661
b6016b76 662static void
212f9934 663bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
b6016b76 664{
212f9934
MC		 665 if (stop_cnic)
666 bnx2_cnic_stop(bp);
b6016b76 667 if (netif_running(bp->dev)) {
35efa7c1 668 bnx2_napi_disable(bp);
b6016b76 669 netif_tx_disable(bp->dev);
b6016b76 670 }
b7466560 671 bnx2_disable_int_sync(bp);
a0ba6760 672 netif_carrier_off(bp->dev); /* prevent tx timeout */
b6016b76
MC		 673}
674
675static void
212f9934 676bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
b6016b76
MC		 677{
678 if (atomic_dec_and_test(&bp->intr_sem)) {
679 if (netif_running(bp->dev)) {
706bf240 680 netif_tx_wake_all_queues(bp->dev);
a0ba6760
MC		 681 spin_lock_bh(&bp->phy_lock);
682 if (bp->link_up)
683 netif_carrier_on(bp->dev);
684 spin_unlock_bh(&bp->phy_lock);
35efa7c1 685 bnx2_napi_enable(bp);
b6016b76 686 bnx2_enable_int(bp);
212f9934
MC		 687 if (start_cnic)
688 bnx2_cnic_start(bp);
b6016b76
MC		 689 }
690 }
691}
692
35e9010b
MC		 693static void
694bnx2_free_tx_mem(struct bnx2 *bp)
695{
696 int i;
697
698 for (i = 0; i < bp->num_tx_rings; i++) {
699 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
700 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
701
702 if (txr->tx_desc_ring) {
36227e88
SG		 703 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
704 txr->tx_desc_ring,
705 txr->tx_desc_mapping);
35e9010b
MC		 706 txr->tx_desc_ring = NULL;
707 }
708 kfree(txr->tx_buf_ring);
709 txr->tx_buf_ring = NULL;
710 }
711}
712
bb4f98ab
MC		 713static void
714bnx2_free_rx_mem(struct bnx2 *bp)
715{
716 int i;
717
718 for (i = 0; i < bp->num_rx_rings; i++) {
719 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
720 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
721 int j;
722
723 for (j = 0; j < bp->rx_max_ring; j++) {
724 if (rxr->rx_desc_ring[j])
36227e88
SG		 725 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
726 rxr->rx_desc_ring[j],
727 rxr->rx_desc_mapping[j]);
bb4f98ab
MC		 728 rxr->rx_desc_ring[j] = NULL;
729 }
25b0b999 730 vfree(rxr->rx_buf_ring);
bb4f98ab
MC		 731 rxr->rx_buf_ring = NULL;
732
733 for (j = 0; j < bp->rx_max_pg_ring; j++) {
734 if (rxr->rx_pg_desc_ring[j])
36227e88
SG		 735 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
736 rxr->rx_pg_desc_ring[j],
737 rxr->rx_pg_desc_mapping[j]);
3298a738 738 rxr->rx_pg_desc_ring[j] = NULL;
bb4f98ab 739 }
25b0b999 740 vfree(rxr->rx_pg_ring);
bb4f98ab
MC		 741 rxr->rx_pg_ring = NULL;
742 }
743}
744
35e9010b
MC		 745static int
746bnx2_alloc_tx_mem(struct bnx2 *bp)
747{
748 int i;
749
750 for (i = 0; i < bp->num_tx_rings; i++) {
751 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
752 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
753
754 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
755 if (txr->tx_buf_ring == NULL)
756 return -ENOMEM;
757
758 txr->tx_desc_ring =
36227e88
SG		 759 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
760 &txr->tx_desc_mapping, GFP_KERNEL);
35e9010b
MC		 761 if (txr->tx_desc_ring == NULL)
762 return -ENOMEM;
763 }
764 return 0;
765}
766
bb4f98ab
MC		 767static int
768bnx2_alloc_rx_mem(struct bnx2 *bp)
769{
770 int i;
771
772 for (i = 0; i < bp->num_rx_rings; i++) {
773 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
774 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
775 int j;
776
777 rxr->rx_buf_ring =
89bf67f1 778 vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
bb4f98ab
MC		 779 if (rxr->rx_buf_ring == NULL)
780 return -ENOMEM;
781
bb4f98ab
MC		 782 for (j = 0; j < bp->rx_max_ring; j++) {
783 rxr->rx_desc_ring[j] =
36227e88
SG		 784 dma_alloc_coherent(&bp->pdev->dev,
785 RXBD_RING_SIZE,
786 &rxr->rx_desc_mapping[j],
787 GFP_KERNEL);
bb4f98ab
MC		 788 if (rxr->rx_desc_ring[j] == NULL)
789 return -ENOMEM;
790
791 }
792
793 if (bp->rx_pg_ring_size) {
89bf67f1 794 rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE *
bb4f98ab
MC		 795 bp->rx_max_pg_ring);
796 if (rxr->rx_pg_ring == NULL)
797 return -ENOMEM;
798
bb4f98ab
MC		 799 }
800
801 for (j = 0; j < bp->rx_max_pg_ring; j++) {
802 rxr->rx_pg_desc_ring[j] =
36227e88
SG		 803 dma_alloc_coherent(&bp->pdev->dev,
804 RXBD_RING_SIZE,
805 &rxr->rx_pg_desc_mapping[j],
806 GFP_KERNEL);
bb4f98ab
MC		 807 if (rxr->rx_pg_desc_ring[j] == NULL)
808 return -ENOMEM;
809
810 }
811 }
812 return 0;
813}
814
b6016b76
MC		 815static void
816bnx2_free_mem(struct bnx2 *bp)
817{
13daffa2 818 int i;
43e80b89 819 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
13daffa2 820
35e9010b 821 bnx2_free_tx_mem(bp);
bb4f98ab 822 bnx2_free_rx_mem(bp);
35e9010b 823
59b47d8a
MC		 824 for (i = 0; i < bp->ctx_pages; i++) {
825 if (bp->ctx_blk[i]) {
36227e88
SG		 826 dma_free_coherent(&bp->pdev->dev, BCM_PAGE_SIZE,
827 bp->ctx_blk[i],
828 bp->ctx_blk_mapping[i]);
59b47d8a
MC		 829 bp->ctx_blk[i] = NULL;
830 }
831 }
43e80b89 832 if (bnapi->status_blk.msi) {
36227e88
SG		 833 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
834 bnapi->status_blk.msi,
835 bp->status_blk_mapping);
43e80b89 836 bnapi->status_blk.msi = NULL;
0f31f994 837 bp->stats_blk = NULL;
b6016b76 838 }
b6016b76
MC		 839}
840
841static int
842bnx2_alloc_mem(struct bnx2 *bp)
843{
35e9010b 844 int i, status_blk_size, err;
43e80b89
MC		 845 struct bnx2_napi *bnapi;
846 void *status_blk;
b6016b76 847
0f31f994
MC		 848 /* Combine status and statistics blocks into one allocation. */
849 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 850 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 851 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
852 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 853 bp->status_stats_size = status_blk_size +
854 sizeof(struct statistics_block);
855
36227e88
SG		 856 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
857 &bp->status_blk_mapping, GFP_KERNEL);
43e80b89 858 if (status_blk == NULL)
b6016b76
MC		 859 goto alloc_mem_err;
860
43e80b89 861 memset(status_blk, 0, bp->status_stats_size);
b6016b76 862
43e80b89
MC		 863 bnapi = &bp->bnx2_napi[0];
864 bnapi->status_blk.msi = status_blk;
865 bnapi->hw_tx_cons_ptr =
866 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
867 bnapi->hw_rx_cons_ptr =
868 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
f86e82fb 869 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
379b39a2 870 for (i = 1; i < bp->irq_nvecs; i++) {
43e80b89
MC		 871 struct status_block_msix *sblk;
872
873 bnapi = &bp->bnx2_napi[i];
b4b36042 874
43e80b89
MC		 875 sblk = (void *) (status_blk +
876 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
877 bnapi->status_blk.msix = sblk;
878 bnapi->hw_tx_cons_ptr =
879 &sblk->status_tx_quick_consumer_index;
880 bnapi->hw_rx_cons_ptr =
881 &sblk->status_rx_quick_consumer_index;
b4b36042
MC		 882 bnapi->int_num = i << 24;
883 }
884 }
35efa7c1 885
43e80b89 886 bp->stats_blk = status_blk + status_blk_size;
b6016b76 887
0f31f994 888 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 889
59b47d8a
MC		 890 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
891 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
892 if (bp->ctx_pages == 0)
893 bp->ctx_pages = 1;
894 for (i = 0; i < bp->ctx_pages; i++) {
36227e88 895 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
59b47d8a 896 BCM_PAGE_SIZE,
36227e88
SG		 897 &bp->ctx_blk_mapping[i],
898 GFP_KERNEL);
59b47d8a
MC		 899 if (bp->ctx_blk[i] == NULL)
900 goto alloc_mem_err;
901 }
902 }
35e9010b 903
bb4f98ab
MC		 904 err = bnx2_alloc_rx_mem(bp);
905 if (err)
906 goto alloc_mem_err;
907
35e9010b
MC		 908 err = bnx2_alloc_tx_mem(bp);
909 if (err)
910 goto alloc_mem_err;
911
b6016b76
MC		 912 return 0;
913
914alloc_mem_err:
915 bnx2_free_mem(bp);
916 return -ENOMEM;
917}
918
e3648b3d
MC		 919static void
920bnx2_report_fw_link(struct bnx2 *bp)
921{
922 u32 fw_link_status = 0;
923
583c28e5 924 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 925 return;
926
e3648b3d
MC		 927 if (bp->link_up) {
928 u32 bmsr;
929
930 switch (bp->line_speed) {
931 case SPEED_10:
932 if (bp->duplex == DUPLEX_HALF)
933 fw_link_status = BNX2_LINK_STATUS_10HALF;
934 else
935 fw_link_status = BNX2_LINK_STATUS_10FULL;
936 break;
937 case SPEED_100:
938 if (bp->duplex == DUPLEX_HALF)
939 fw_link_status = BNX2_LINK_STATUS_100HALF;
940 else
941 fw_link_status = BNX2_LINK_STATUS_100FULL;
942 break;
943 case SPEED_1000:
944 if (bp->duplex == DUPLEX_HALF)
945 fw_link_status = BNX2_LINK_STATUS_1000HALF;
946 else
947 fw_link_status = BNX2_LINK_STATUS_1000FULL;
948 break;
949 case SPEED_2500:
950 if (bp->duplex == DUPLEX_HALF)
951 fw_link_status = BNX2_LINK_STATUS_2500HALF;
952 else
953 fw_link_status = BNX2_LINK_STATUS_2500FULL;
954 break;
955 }
956
957 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
958
959 if (bp->autoneg) {
960 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
961
ca58c3af
MC		 962 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
963 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 964
965 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 966 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 967 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
968 else
969 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
970 }
971 }
972 else
973 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
974
2726d6e1 975 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 976}
977
9b1084b8
MC		 978static char *
979bnx2_xceiver_str(struct bnx2 *bp)
980{
807540ba 981 return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 982 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
807540ba 983 "Copper");
9b1084b8
MC		 984}
985
b6016b76
MC		 986static void
987bnx2_report_link(struct bnx2 *bp)
988{
989 if (bp->link_up) {
990 netif_carrier_on(bp->dev);
3a9c6a49
JP		 991 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
992 bnx2_xceiver_str(bp),
993 bp->line_speed,
994 bp->duplex == DUPLEX_FULL ? "full" : "half");
b6016b76
MC		 995
996 if (bp->flow_ctrl) {
997 if (bp->flow_ctrl & FLOW_CTRL_RX) {
3a9c6a49 998 pr_cont(", receive ");
b6016b76 999 if (bp->flow_ctrl & FLOW_CTRL_TX)
3a9c6a49 1000 pr_cont("& transmit ");
b6016b76
MC		 1001 }
1002 else {
3a9c6a49 1003 pr_cont(", transmit ");
b6016b76 1004 }
3a9c6a49 1005 pr_cont("flow control ON");
b6016b76 1006 }
3a9c6a49
JP		 1007 pr_cont("\n");
1008 } else {
b6016b76 1009 netif_carrier_off(bp->dev);
3a9c6a49
JP		 1010 netdev_err(bp->dev, "NIC %s Link is Down\n",
1011 bnx2_xceiver_str(bp));
b6016b76 1012 }
e3648b3d
MC		 1013
1014 bnx2_report_fw_link(bp);
b6016b76
MC		 1015}
1016
1017static void
1018bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1019{
1020 u32 local_adv, remote_adv;
1021
1022 bp->flow_ctrl = 0;
6aa20a22 1023 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 1024 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1025
1026 if (bp->duplex == DUPLEX_FULL) {
1027 bp->flow_ctrl = bp->req_flow_ctrl;
1028 }
1029 return;
1030 }
1031
1032 if (bp->duplex != DUPLEX_FULL) {
1033 return;
1034 }
1035
583c28e5 1036 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 1037 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1038 u32 val;
1039
1040 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1041 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1042 bp->flow_ctrl |= FLOW_CTRL_TX;
1043 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1044 bp->flow_ctrl |= FLOW_CTRL_RX;
1045 return;
1046 }
1047
ca58c3af
MC		 1048 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1049 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 1050
583c28e5 1051 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1052 u32 new_local_adv = 0;
1053 u32 new_remote_adv = 0;
1054
1055 if (local_adv & ADVERTISE_1000XPAUSE)
1056 new_local_adv |= ADVERTISE_PAUSE_CAP;
1057 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1058 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1059 if (remote_adv & ADVERTISE_1000XPAUSE)
1060 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1061 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1062 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1063
1064 local_adv = new_local_adv;
1065 remote_adv = new_remote_adv;
1066 }
1067
1068 /* See Table 28B-3 of 802.3ab-1999 spec. */
1069 if (local_adv & ADVERTISE_PAUSE_CAP) {
1070 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1071 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1072 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1073 }
1074 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1075 bp->flow_ctrl = FLOW_CTRL_RX;
1076 }
1077 }
1078 else {
1079 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1080 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1081 }
1082 }
1083 }
1084 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1085 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1086 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1087
1088 bp->flow_ctrl = FLOW_CTRL_TX;
1089 }
1090 }
1091}
1092
27a005b8
MC		 1093static int
1094bnx2_5709s_linkup(struct bnx2 *bp)
1095{
1096 u32 val, speed;
1097
1098 bp->link_up = 1;
1099
1100 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1101 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1102 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1103
1104 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1105 bp->line_speed = bp->req_line_speed;
1106 bp->duplex = bp->req_duplex;
1107 return 0;
1108 }
1109 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1110 switch (speed) {
1111 case MII_BNX2_GP_TOP_AN_SPEED_10:
1112 bp->line_speed = SPEED_10;
1113 break;
1114 case MII_BNX2_GP_TOP_AN_SPEED_100:
1115 bp->line_speed = SPEED_100;
1116 break;
1117 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1118 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1119 bp->line_speed = SPEED_1000;
1120 break;
1121 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1122 bp->line_speed = SPEED_2500;
1123 break;
1124 }
1125 if (val & MII_BNX2_GP_TOP_AN_FD)
1126 bp->duplex = DUPLEX_FULL;
1127 else
1128 bp->duplex = DUPLEX_HALF;
1129 return 0;
1130}
1131
b6016b76 1132static int
5b0c76ad
MC		 1133bnx2_5708s_linkup(struct bnx2 *bp)
1134{
1135 u32 val;
1136
1137 bp->link_up = 1;
1138 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1139 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1140 case BCM5708S_1000X_STAT1_SPEED_10:
1141 bp->line_speed = SPEED_10;
1142 break;
1143 case BCM5708S_1000X_STAT1_SPEED_100:
1144 bp->line_speed = SPEED_100;
1145 break;
1146 case BCM5708S_1000X_STAT1_SPEED_1G:
1147 bp->line_speed = SPEED_1000;
1148 break;
1149 case BCM5708S_1000X_STAT1_SPEED_2G5:
1150 bp->line_speed = SPEED_2500;
1151 break;
1152 }
1153 if (val & BCM5708S_1000X_STAT1_FD)
1154 bp->duplex = DUPLEX_FULL;
1155 else
1156 bp->duplex = DUPLEX_HALF;
1157
1158 return 0;
1159}
1160
1161static int
1162bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 1163{
1164 u32 bmcr, local_adv, remote_adv, common;
1165
1166 bp->link_up = 1;
1167 bp->line_speed = SPEED_1000;
1168
ca58c3af 1169 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1170 if (bmcr & BMCR_FULLDPLX) {
1171 bp->duplex = DUPLEX_FULL;
1172 }
1173 else {
1174 bp->duplex = DUPLEX_HALF;
1175 }
1176
1177 if (!(bmcr & BMCR_ANENABLE)) {
1178 return 0;
1179 }
1180
ca58c3af
MC		 1181 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1182 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1183
1184 common = local_adv & remote_adv;
1185 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1186
1187 if (common & ADVERTISE_1000XFULL) {
1188 bp->duplex = DUPLEX_FULL;
1189 }
1190 else {
1191 bp->duplex = DUPLEX_HALF;
1192 }
1193 }
1194
1195 return 0;
1196}
1197
1198static int
1199bnx2_copper_linkup(struct bnx2 *bp)
1200{
1201 u32 bmcr;
1202
ca58c3af 1203 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1204 if (bmcr & BMCR_ANENABLE) {
1205 u32 local_adv, remote_adv, common;
1206
1207 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1208 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1209
1210 common = local_adv & (remote_adv >> 2);
1211 if (common & ADVERTISE_1000FULL) {
1212 bp->line_speed = SPEED_1000;
1213 bp->duplex = DUPLEX_FULL;
1214 }
1215 else if (common & ADVERTISE_1000HALF) {
1216 bp->line_speed = SPEED_1000;
1217 bp->duplex = DUPLEX_HALF;
1218 }
1219 else {
ca58c3af
MC		 1220 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1221 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1222
1223 common = local_adv & remote_adv;
1224 if (common & ADVERTISE_100FULL) {
1225 bp->line_speed = SPEED_100;
1226 bp->duplex = DUPLEX_FULL;
1227 }
1228 else if (common & ADVERTISE_100HALF) {
1229 bp->line_speed = SPEED_100;
1230 bp->duplex = DUPLEX_HALF;
1231 }
1232 else if (common & ADVERTISE_10FULL) {
1233 bp->line_speed = SPEED_10;
1234 bp->duplex = DUPLEX_FULL;
1235 }
1236 else if (common & ADVERTISE_10HALF) {
1237 bp->line_speed = SPEED_10;
1238 bp->duplex = DUPLEX_HALF;
1239 }
1240 else {
1241 bp->line_speed = 0;
1242 bp->link_up = 0;
1243 }
1244 }
1245 }
1246 else {
1247 if (bmcr & BMCR_SPEED100) {
1248 bp->line_speed = SPEED_100;
1249 }
1250 else {
1251 bp->line_speed = SPEED_10;
1252 }
1253 if (bmcr & BMCR_FULLDPLX) {
1254 bp->duplex = DUPLEX_FULL;
1255 }
1256 else {
1257 bp->duplex = DUPLEX_HALF;
1258 }
1259 }
1260
1261 return 0;
1262}
1263
83e3fc89 1264static void
bb4f98ab 1265bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
83e3fc89 1266{
bb4f98ab 1267 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
83e3fc89
MC		 1268
1269 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1270 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1271 val |= 0x02 << 8;
1272
22fa159d
MC		 1273 if (bp->flow_ctrl & FLOW_CTRL_TX)
1274 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
83e3fc89 1275
83e3fc89
MC		 1276 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1277}
1278
bb4f98ab
MC		 1279static void
1280bnx2_init_all_rx_contexts(struct bnx2 *bp)
1281{
1282 int i;
1283 u32 cid;
1284
1285 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1286 if (i == 1)
1287 cid = RX_RSS_CID;
1288 bnx2_init_rx_context(bp, cid);
1289 }
1290}
1291
344478db 1292static void
b6016b76
MC		 1293bnx2_set_mac_link(struct bnx2 *bp)
1294{
1295 u32 val;
1296
1297 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1298 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1299 (bp->duplex == DUPLEX_HALF)) {
1300 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1301 }
1302
1303 /* Configure the EMAC mode register. */
1304 val = REG_RD(bp, BNX2_EMAC_MODE);
1305
1306 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1307 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1308 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1309
1310 if (bp->link_up) {
5b0c76ad
MC		 1311 switch (bp->line_speed) {
1312 case SPEED_10:
59b47d8a
MC		 1313 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1314 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1315 break;
1316 }
1317 /* fall through */
1318 case SPEED_100:
1319 val |= BNX2_EMAC_MODE_PORT_MII;
1320 break;
1321 case SPEED_2500:
59b47d8a 1322 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1323 /* fall through */
1324 case SPEED_1000:
1325 val |= BNX2_EMAC_MODE_PORT_GMII;
1326 break;
1327 }
b6016b76
MC		 1328 }
1329 else {
1330 val |= BNX2_EMAC_MODE_PORT_GMII;
1331 }
1332
1333 /* Set the MAC to operate in the appropriate duplex mode. */
1334 if (bp->duplex == DUPLEX_HALF)
1335 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1336 REG_WR(bp, BNX2_EMAC_MODE, val);
1337
1338 /* Enable/disable rx PAUSE. */
1339 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1340
1341 if (bp->flow_ctrl & FLOW_CTRL_RX)
1342 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1343 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1344
1345 /* Enable/disable tx PAUSE. */
1346 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1347 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1348
1349 if (bp->flow_ctrl & FLOW_CTRL_TX)
1350 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1351 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1352
1353 /* Acknowledge the interrupt. */
1354 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1355
22fa159d 1356 bnx2_init_all_rx_contexts(bp);
b6016b76
MC		 1357}
1358
27a005b8
MC		 1359static void
1360bnx2_enable_bmsr1(struct bnx2 *bp)
1361{
583c28e5 1362 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1363 (CHIP_NUM(bp) == CHIP_NUM_5709))
1364 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1365 MII_BNX2_BLK_ADDR_GP_STATUS);
1366}
1367
1368static void
1369bnx2_disable_bmsr1(struct bnx2 *bp)
1370{
583c28e5 1371 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1372 (CHIP_NUM(bp) == CHIP_NUM_5709))
1373 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1374 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1375}
1376
605a9e20
MC		 1377static int
1378bnx2_test_and_enable_2g5(struct bnx2 *bp)
1379{
1380 u32 up1;
1381 int ret = 1;
1382
583c28e5 1383 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1384 return 0;
1385
1386 if (bp->autoneg & AUTONEG_SPEED)
1387 bp->advertising |= ADVERTISED_2500baseX_Full;
1388
27a005b8
MC		 1389 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1390 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1391
605a9e20
MC		 1392 bnx2_read_phy(bp, bp->mii_up1, &up1);
1393 if (!(up1 & BCM5708S_UP1_2G5)) {
1394 up1 |= BCM5708S_UP1_2G5;
1395 bnx2_write_phy(bp, bp->mii_up1, up1);
1396 ret = 0;
1397 }
1398
27a005b8
MC		 1399 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1400 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1401 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1402
605a9e20
MC		 1403 return ret;
1404}
1405
1406static int
1407bnx2_test_and_disable_2g5(struct bnx2 *bp)
1408{
1409 u32 up1;
1410 int ret = 0;
1411
583c28e5 1412 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1413 return 0;
1414
27a005b8
MC		 1415 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1416 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1417
605a9e20
MC		 1418 bnx2_read_phy(bp, bp->mii_up1, &up1);
1419 if (up1 & BCM5708S_UP1_2G5) {
1420 up1 &= ~BCM5708S_UP1_2G5;
1421 bnx2_write_phy(bp, bp->mii_up1, up1);
1422 ret = 1;
1423 }
1424
27a005b8
MC		 1425 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1426 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1427 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1428
605a9e20
MC		 1429 return ret;
1430}
1431
1432static void
1433bnx2_enable_forced_2g5(struct bnx2 *bp)
1434{
cbd6890c
MC		 1435 u32 uninitialized_var(bmcr);
1436 int err;
605a9e20 1437
583c28e5 1438 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1439 return;
1440
27a005b8
MC		 1441 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1442 u32 val;
1443
1444 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1445 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1446 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1447 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1448 val |= MII_BNX2_SD_MISC1_FORCE |
1449 MII_BNX2_SD_MISC1_FORCE_2_5G;
1450 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1451 }
27a005b8
MC		 1452
1453 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1454 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1455 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1456
1457 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1458 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1459 if (!err)
1460 bmcr |= BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1461 } else {
1462 return;
605a9e20
MC		 1463 }
1464
cbd6890c
MC		 1465 if (err)
1466 return;
1467
605a9e20
MC		 1468 if (bp->autoneg & AUTONEG_SPEED) {
1469 bmcr &= ~BMCR_ANENABLE;
1470 if (bp->req_duplex == DUPLEX_FULL)
1471 bmcr |= BMCR_FULLDPLX;
1472 }
1473 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1474}
1475
1476static void
1477bnx2_disable_forced_2g5(struct bnx2 *bp)
1478{
cbd6890c
MC		 1479 u32 uninitialized_var(bmcr);
1480 int err;
605a9e20 1481
583c28e5 1482 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1483 return;
1484
27a005b8
MC		 1485 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1486 u32 val;
1487
1488 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1489 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1490 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1491 val &= ~MII_BNX2_SD_MISC1_FORCE;
1492 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1493 }
27a005b8
MC		 1494
1495 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1496 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1497 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1498
1499 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1500 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1501 if (!err)
1502 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1503 } else {
1504 return;
605a9e20
MC		 1505 }
1506
cbd6890c
MC		 1507 if (err)
1508 return;
1509
605a9e20
MC		 1510 if (bp->autoneg & AUTONEG_SPEED)
1511 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1512 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1513}
1514
b2fadeae
MC		 1515static void
1516bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1517{
1518 u32 val;
1519
1520 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1521 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1522 if (start)
1523 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1524 else
1525 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1526}
1527
b6016b76
MC		 1528static int
1529bnx2_set_link(struct bnx2 *bp)
1530{
1531 u32 bmsr;
1532 u8 link_up;
1533
80be4434 1534 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1535 bp->link_up = 1;
1536 return 0;
1537 }
1538
583c28e5 1539 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1540 return 0;
1541
b6016b76
MC		 1542 link_up = bp->link_up;
1543
27a005b8
MC		 1544 bnx2_enable_bmsr1(bp);
1545 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1546 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1547 bnx2_disable_bmsr1(bp);
b6016b76 1548
583c28e5 1549 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1550 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1551 u32 val, an_dbg;
b6016b76 1552
583c28e5 1553 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1554 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1555 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1556 }
b6016b76 1557 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1558
1559 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1560 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1561 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1562
1563 if ((val & BNX2_EMAC_STATUS_LINK) &&
1564 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1565 bmsr |= BMSR_LSTATUS;
1566 else
1567 bmsr &= ~BMSR_LSTATUS;
1568 }
1569
1570 if (bmsr & BMSR_LSTATUS) {
1571 bp->link_up = 1;
1572
583c28e5 1573 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1574 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1575 bnx2_5706s_linkup(bp);
1576 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1577 bnx2_5708s_linkup(bp);
27a005b8
MC		 1578 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1579 bnx2_5709s_linkup(bp);
b6016b76
MC		 1580 }
1581 else {
1582 bnx2_copper_linkup(bp);
1583 }
1584 bnx2_resolve_flow_ctrl(bp);
1585 }
1586 else {
583c28e5 1587 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1588 (bp->autoneg & AUTONEG_SPEED))
1589 bnx2_disable_forced_2g5(bp);
b6016b76 1590
583c28e5 1591 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1592 u32 bmcr;
1593
1594 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1595 bmcr |= BMCR_ANENABLE;
1596 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1597
583c28e5 1598 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1599 }
b6016b76
MC		 1600 bp->link_up = 0;
1601 }
1602
1603 if (bp->link_up != link_up) {
1604 bnx2_report_link(bp);
1605 }
1606
1607 bnx2_set_mac_link(bp);
1608
1609 return 0;
1610}
1611
1612static int
1613bnx2_reset_phy(struct bnx2 *bp)
1614{
1615 int i;
1616 u32 reg;
1617
ca58c3af 1618 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1619
1620#define PHY_RESET_MAX_WAIT 100
1621 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1622 udelay(10);
1623
ca58c3af 1624 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1625 if (!(reg & BMCR_RESET)) {
1626 udelay(20);
1627 break;
1628 }
1629 }
1630 if (i == PHY_RESET_MAX_WAIT) {
1631 return -EBUSY;
1632 }
1633 return 0;
1634}
1635
1636static u32
1637bnx2_phy_get_pause_adv(struct bnx2 *bp)
1638{
1639 u32 adv = 0;
1640
1641 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1642 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1643
583c28e5 1644 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1645 adv = ADVERTISE_1000XPAUSE;
1646 }
1647 else {
1648 adv = ADVERTISE_PAUSE_CAP;
1649 }
1650 }
1651 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1652 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1653 adv = ADVERTISE_1000XPSE_ASYM;
1654 }
1655 else {
1656 adv = ADVERTISE_PAUSE_ASYM;
1657 }
1658 }
1659 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1660 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1661 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1662 }
1663 else {
1664 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1665 }
1666 }
1667 return adv;
1668}
1669
a2f13890 1670static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
0d8a6571 1671
b6016b76 1672static int
0d8a6571 1673bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1674__releases(&bp->phy_lock)
1675__acquires(&bp->phy_lock)
0d8a6571
MC		 1676{
1677 u32 speed_arg = 0, pause_adv;
1678
1679 pause_adv = bnx2_phy_get_pause_adv(bp);
1680
1681 if (bp->autoneg & AUTONEG_SPEED) {
1682 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1683 if (bp->advertising & ADVERTISED_10baseT_Half)
1684 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1685 if (bp->advertising & ADVERTISED_10baseT_Full)
1686 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1687 if (bp->advertising & ADVERTISED_100baseT_Half)
1688 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1689 if (bp->advertising & ADVERTISED_100baseT_Full)
1690 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1691 if (bp->advertising & ADVERTISED_1000baseT_Full)
1692 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1693 if (bp->advertising & ADVERTISED_2500baseX_Full)
1694 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1695 } else {
1696 if (bp->req_line_speed == SPEED_2500)
1697 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1698 else if (bp->req_line_speed == SPEED_1000)
1699 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1700 else if (bp->req_line_speed == SPEED_100) {
1701 if (bp->req_duplex == DUPLEX_FULL)
1702 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1703 else
1704 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1705 } else if (bp->req_line_speed == SPEED_10) {
1706 if (bp->req_duplex == DUPLEX_FULL)
1707 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1708 else
1709 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1710 }
1711 }
1712
1713 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1714 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1715 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1716 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1717
1718 if (port == PORT_TP)
1719 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1720 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1721
2726d6e1 1722 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1723
1724 spin_unlock_bh(&bp->phy_lock);
a2f13890 1725 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
0d8a6571
MC		 1726 spin_lock_bh(&bp->phy_lock);
1727
1728 return 0;
1729}
1730
1731static int
1732bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1733__releases(&bp->phy_lock)
1734__acquires(&bp->phy_lock)
b6016b76 1735{
605a9e20 1736 u32 adv, bmcr;
b6016b76
MC		 1737 u32 new_adv = 0;
1738
583c28e5 1739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
807540ba 1740 return bnx2_setup_remote_phy(bp, port);
0d8a6571 1741
b6016b76
MC		 1742 if (!(bp->autoneg & AUTONEG_SPEED)) {
1743 u32 new_bmcr;
5b0c76ad
MC		 1744 int force_link_down = 0;
1745
605a9e20
MC		 1746 if (bp->req_line_speed == SPEED_2500) {
1747 if (!bnx2_test_and_enable_2g5(bp))
1748 force_link_down = 1;
1749 } else if (bp->req_line_speed == SPEED_1000) {
1750 if (bnx2_test_and_disable_2g5(bp))
1751 force_link_down = 1;
1752 }
ca58c3af 1753 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1754 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1755
ca58c3af 1756 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1757 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1758 new_bmcr |= BMCR_SPEED1000;
605a9e20 1759
27a005b8
MC		 1760 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1761 if (bp->req_line_speed == SPEED_2500)
1762 bnx2_enable_forced_2g5(bp);
1763 else if (bp->req_line_speed == SPEED_1000) {
1764 bnx2_disable_forced_2g5(bp);
1765 new_bmcr &= ~0x2000;
1766 }
1767
1768 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1769 if (bp->req_line_speed == SPEED_2500)
1770 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1771 else
1772 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1773 }
1774
b6016b76 1775 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1776 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1777 new_bmcr |= BMCR_FULLDPLX;
1778 }
1779 else {
5b0c76ad 1780 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1781 new_bmcr &= ~BMCR_FULLDPLX;
1782 }
5b0c76ad 1783 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1784 /* Force a link down visible on the other side */
1785 if (bp->link_up) {
ca58c3af 1786 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1787 ~(ADVERTISE_1000XFULL |
1788 ADVERTISE_1000XHALF));
ca58c3af 1789 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1790 BMCR_ANRESTART | BMCR_ANENABLE);
1791
1792 bp->link_up = 0;
1793 netif_carrier_off(bp->dev);
ca58c3af 1794 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1795 bnx2_report_link(bp);
b6016b76 1796 }
ca58c3af
MC		 1797 bnx2_write_phy(bp, bp->mii_adv, adv);
1798 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1799 } else {
1800 bnx2_resolve_flow_ctrl(bp);
1801 bnx2_set_mac_link(bp);
b6016b76
MC		 1802 }
1803 return 0;
1804 }
1805
605a9e20 1806 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1807
b6016b76
MC		 1808 if (bp->advertising & ADVERTISED_1000baseT_Full)
1809 new_adv |= ADVERTISE_1000XFULL;
1810
1811 new_adv |= bnx2_phy_get_pause_adv(bp);
1812
ca58c3af
MC		 1813 bnx2_read_phy(bp, bp->mii_adv, &adv);
1814 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1815
1816 bp->serdes_an_pending = 0;
1817 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1818 /* Force a link down visible on the other side */
1819 if (bp->link_up) {
ca58c3af 1820 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1821 spin_unlock_bh(&bp->phy_lock);
1822 msleep(20);
1823 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1824 }
1825
ca58c3af
MC		 1826 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1827 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1828 BMCR_ANENABLE);
f8dd064e
MC		 1829 /* Speed up link-up time when the link partner
1830 * does not autonegotiate which is very common
1831 * in blade servers. Some blade servers use
1832 * IPMI for kerboard input and it's important
1833 * to minimize link disruptions. Autoneg. involves
1834 * exchanging base pages plus 3 next pages and
1835 * normally completes in about 120 msec.
1836 */
40105c0b 1837 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 1838 bp->serdes_an_pending = 1;
1839 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1840 } else {
1841 bnx2_resolve_flow_ctrl(bp);
1842 bnx2_set_mac_link(bp);
b6016b76
MC		 1843 }
1844
1845 return 0;
1846}
1847
1848#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1849 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1850 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1851 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1852
1853#define ETHTOOL_ALL_COPPER_SPEED \
1854 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1855 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1856 ADVERTISED_1000baseT_Full)
1857
1858#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1859 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1860
b6016b76
MC		 1861#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1862
0d8a6571
MC		 1863static void
1864bnx2_set_default_remote_link(struct bnx2 *bp)
1865{
1866 u32 link;
1867
1868 if (bp->phy_port == PORT_TP)
2726d6e1 1869 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1870 else
2726d6e1 1871 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1872
1873 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1874 bp->req_line_speed = 0;
1875 bp->autoneg |= AUTONEG_SPEED;
1876 bp->advertising = ADVERTISED_Autoneg;
1877 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1878 bp->advertising |= ADVERTISED_10baseT_Half;
1879 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1880 bp->advertising |= ADVERTISED_10baseT_Full;
1881 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1882 bp->advertising |= ADVERTISED_100baseT_Half;
1883 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1884 bp->advertising |= ADVERTISED_100baseT_Full;
1885 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1886 bp->advertising |= ADVERTISED_1000baseT_Full;
1887 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1888 bp->advertising |= ADVERTISED_2500baseX_Full;
1889 } else {
1890 bp->autoneg = 0;
1891 bp->advertising = 0;
1892 bp->req_duplex = DUPLEX_FULL;
1893 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1894 bp->req_line_speed = SPEED_10;
1895 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1896 bp->req_duplex = DUPLEX_HALF;
1897 }
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1899 bp->req_line_speed = SPEED_100;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1901 bp->req_duplex = DUPLEX_HALF;
1902 }
1903 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1904 bp->req_line_speed = SPEED_1000;
1905 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1906 bp->req_line_speed = SPEED_2500;
1907 }
1908}
1909
deaf391b
MC		 1910static void
1911bnx2_set_default_link(struct bnx2 *bp)
1912{
ab59859d
HH		 1913 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1914 bnx2_set_default_remote_link(bp);
1915 return;
1916 }
0d8a6571 1917
deaf391b
MC		 1918 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1919 bp->req_line_speed = 0;
583c28e5 1920 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1921 u32 reg;
1922
1923 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1924
2726d6e1 1925 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1926 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1927 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1928 bp->autoneg = 0;
1929 bp->req_line_speed = bp->line_speed = SPEED_1000;
1930 bp->req_duplex = DUPLEX_FULL;
1931 }
1932 } else
1933 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1934}
1935
df149d70
MC		 1936static void
1937bnx2_send_heart_beat(struct bnx2 *bp)
1938{
1939 u32 msg;
1940 u32 addr;
1941
1942 spin_lock(&bp->indirect_lock);
1943 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1944 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1945 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1946 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1947 spin_unlock(&bp->indirect_lock);
1948}
1949
0d8a6571
MC		 1950static void
1951bnx2_remote_phy_event(struct bnx2 *bp)
1952{
1953 u32 msg;
1954 u8 link_up = bp->link_up;
1955 u8 old_port;
1956
2726d6e1 1957 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1958
df149d70
MC		 1959 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1960 bnx2_send_heart_beat(bp);
1961
1962 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1963
0d8a6571
MC		 1964 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1965 bp->link_up = 0;
1966 else {
1967 u32 speed;
1968
1969 bp->link_up = 1;
1970 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1971 bp->duplex = DUPLEX_FULL;
1972 switch (speed) {
1973 case BNX2_LINK_STATUS_10HALF:
1974 bp->duplex = DUPLEX_HALF;
1975 case BNX2_LINK_STATUS_10FULL:
1976 bp->line_speed = SPEED_10;
1977 break;
1978 case BNX2_LINK_STATUS_100HALF:
1979 bp->duplex = DUPLEX_HALF;
1980 case BNX2_LINK_STATUS_100BASE_T4:
1981 case BNX2_LINK_STATUS_100FULL:
1982 bp->line_speed = SPEED_100;
1983 break;
1984 case BNX2_LINK_STATUS_1000HALF:
1985 bp->duplex = DUPLEX_HALF;
1986 case BNX2_LINK_STATUS_1000FULL:
1987 bp->line_speed = SPEED_1000;
1988 break;
1989 case BNX2_LINK_STATUS_2500HALF:
1990 bp->duplex = DUPLEX_HALF;
1991 case BNX2_LINK_STATUS_2500FULL:
1992 bp->line_speed = SPEED_2500;
1993 break;
1994 default:
1995 bp->line_speed = 0;
1996 break;
1997 }
1998
0d8a6571
MC		 1999 bp->flow_ctrl = 0;
2000 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2001 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2002 if (bp->duplex == DUPLEX_FULL)
2003 bp->flow_ctrl = bp->req_flow_ctrl;
2004 } else {
2005 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2006 bp->flow_ctrl |= FLOW_CTRL_TX;
2007 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2008 bp->flow_ctrl |= FLOW_CTRL_RX;
2009 }
2010
2011 old_port = bp->phy_port;
2012 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2013 bp->phy_port = PORT_FIBRE;
2014 else
2015 bp->phy_port = PORT_TP;
2016
2017 if (old_port != bp->phy_port)
2018 bnx2_set_default_link(bp);
2019
0d8a6571
MC		 2020 }
2021 if (bp->link_up != link_up)
2022 bnx2_report_link(bp);
2023
2024 bnx2_set_mac_link(bp);
2025}
2026
2027static int
2028bnx2_set_remote_link(struct bnx2 *bp)
2029{
2030 u32 evt_code;
2031
2726d6e1 2032 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 2033 switch (evt_code) {
2034 case BNX2_FW_EVT_CODE_LINK_EVENT:
2035 bnx2_remote_phy_event(bp);
2036 break;
2037 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2038 default:
df149d70 2039 bnx2_send_heart_beat(bp);
0d8a6571
MC		 2040 break;
2041 }
2042 return 0;
2043}
2044
b6016b76
MC		 2045static int
2046bnx2_setup_copper_phy(struct bnx2 *bp)
52d07b1f
HH		 2047__releases(&bp->phy_lock)
2048__acquires(&bp->phy_lock)
b6016b76
MC		 2049{
2050 u32 bmcr;
2051 u32 new_bmcr;
2052
ca58c3af 2053 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 2054
2055 if (bp->autoneg & AUTONEG_SPEED) {
2056 u32 adv_reg, adv1000_reg;
2057 u32 new_adv_reg = 0;
2058 u32 new_adv1000_reg = 0;
2059
ca58c3af 2060 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 2061 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2062 ADVERTISE_PAUSE_ASYM);
2063
2064 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2065 adv1000_reg &= PHY_ALL_1000_SPEED;
2066
2067 if (bp->advertising & ADVERTISED_10baseT_Half)
2068 new_adv_reg |= ADVERTISE_10HALF;
2069 if (bp->advertising & ADVERTISED_10baseT_Full)
2070 new_adv_reg |= ADVERTISE_10FULL;
2071 if (bp->advertising & ADVERTISED_100baseT_Half)
2072 new_adv_reg |= ADVERTISE_100HALF;
2073 if (bp->advertising & ADVERTISED_100baseT_Full)
2074 new_adv_reg |= ADVERTISE_100FULL;
2075 if (bp->advertising & ADVERTISED_1000baseT_Full)
2076 new_adv1000_reg |= ADVERTISE_1000FULL;
6aa20a22 2077
b6016b76
MC		 2078 new_adv_reg |= ADVERTISE_CSMA;
2079
2080 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2081
2082 if ((adv1000_reg != new_adv1000_reg) ||
2083 (adv_reg != new_adv_reg) ||
2084 ((bmcr & BMCR_ANENABLE) == 0)) {
2085
ca58c3af 2086 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
b6016b76 2087 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
ca58c3af 2088 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 2089 BMCR_ANENABLE);
2090 }
2091 else if (bp->link_up) {
2092 /* Flow ctrl may have changed from auto to forced */
2093 /* or vice-versa. */
2094
2095 bnx2_resolve_flow_ctrl(bp);
2096 bnx2_set_mac_link(bp);
2097 }
2098 return 0;
2099 }
2100
2101 new_bmcr = 0;
2102 if (bp->req_line_speed == SPEED_100) {
2103 new_bmcr |= BMCR_SPEED100;
2104 }
2105 if (bp->req_duplex == DUPLEX_FULL) {
2106 new_bmcr |= BMCR_FULLDPLX;
2107 }
2108 if (new_bmcr != bmcr) {
2109 u32 bmsr;
b6016b76 2110
ca58c3af
MC		 2111 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2112 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 2113
b6016b76
MC		 2114 if (bmsr & BMSR_LSTATUS) {
2115 /* Force link down */
ca58c3af 2116 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 2117 spin_unlock_bh(&bp->phy_lock);
2118 msleep(50);
2119 spin_lock_bh(&bp->phy_lock);
2120
ca58c3af
MC		 2121 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2122 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 2123 }
2124
ca58c3af 2125 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 2126
2127 /* Normally, the new speed is setup after the link has
2128 * gone down and up again. In some cases, link will not go
2129 * down so we need to set up the new speed here.
2130 */
2131 if (bmsr & BMSR_LSTATUS) {
2132 bp->line_speed = bp->req_line_speed;
2133 bp->duplex = bp->req_duplex;
2134 bnx2_resolve_flow_ctrl(bp);
2135 bnx2_set_mac_link(bp);
2136 }
27a005b8
MC		 2137 } else {
2138 bnx2_resolve_flow_ctrl(bp);
2139 bnx2_set_mac_link(bp);
b6016b76
MC		 2140 }
2141 return 0;
2142}
2143
2144static int
0d8a6571 2145bnx2_setup_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 2146__releases(&bp->phy_lock)
2147__acquires(&bp->phy_lock)
b6016b76
MC		 2148{
2149 if (bp->loopback == MAC_LOOPBACK)
2150 return 0;
2151
583c28e5 2152 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
807540ba 2153 return bnx2_setup_serdes_phy(bp, port);
b6016b76
MC		 2154 }
2155 else {
807540ba 2156 return bnx2_setup_copper_phy(bp);
b6016b76
MC		 2157 }
2158}
2159
27a005b8 2160static int
9a120bc5 2161bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 2162{
2163 u32 val;
2164
2165 bp->mii_bmcr = MII_BMCR + 0x10;
2166 bp->mii_bmsr = MII_BMSR + 0x10;
2167 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2168 bp->mii_adv = MII_ADVERTISE + 0x10;
2169 bp->mii_lpa = MII_LPA + 0x10;
2170 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2171
2172 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2173 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2174
2175 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 2176 if (reset_phy)
2177 bnx2_reset_phy(bp);
27a005b8
MC		 2178
2179 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2180
2181 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2182 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2183 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2184 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2185
2186 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2187 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 2188 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 2189 val |= BCM5708S_UP1_2G5;
2190 else
2191 val &= ~BCM5708S_UP1_2G5;
2192 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2193
2194 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2195 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2196 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2197 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2198
2199 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2200
2201 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2202 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2203 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2204
2205 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2206
2207 return 0;
2208}
2209
b6016b76 2210static int
9a120bc5 2211bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 2212{
2213 u32 val;
2214
9a120bc5
MC		 2215 if (reset_phy)
2216 bnx2_reset_phy(bp);
27a005b8
MC		 2217
2218 bp->mii_up1 = BCM5708S_UP1;
2219
5b0c76ad
MC		 2220 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2221 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2222 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2223
2224 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2225 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2226 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2227
2228 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2229 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2230 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2231
583c28e5 2232 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 2233 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2234 val |= BCM5708S_UP1_2G5;
2235 bnx2_write_phy(bp, BCM5708S_UP1, val);
2236 }
2237
2238 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 2239 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2240 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 2241 /* increase tx signal amplitude */
2242 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2243 BCM5708S_BLK_ADDR_TX_MISC);
2244 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2245 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2246 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2247 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2248 }
2249
2726d6e1 2250 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 2251 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2252
2253 if (val) {
2254 u32 is_backplane;
2255
2726d6e1 2256 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 2257 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2258 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2259 BCM5708S_BLK_ADDR_TX_MISC);
2260 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2261 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2262 BCM5708S_BLK_ADDR_DIG);
2263 }
2264 }
2265 return 0;
2266}
2267
2268static int
9a120bc5 2269bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2270{
9a120bc5
MC		 2271 if (reset_phy)
2272 bnx2_reset_phy(bp);
27a005b8 2273
583c28e5 2274 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 2275
59b47d8a
MC		 2276 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2277 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 2278
2279 if (bp->dev->mtu > 1500) {
2280 u32 val;
2281
2282 /* Set extended packet length bit */
2283 bnx2_write_phy(bp, 0x18, 0x7);
2284 bnx2_read_phy(bp, 0x18, &val);
2285 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2286
2287 bnx2_write_phy(bp, 0x1c, 0x6c00);
2288 bnx2_read_phy(bp, 0x1c, &val);
2289 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2290 }
2291 else {
2292 u32 val;
2293
2294 bnx2_write_phy(bp, 0x18, 0x7);
2295 bnx2_read_phy(bp, 0x18, &val);
2296 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2297
2298 bnx2_write_phy(bp, 0x1c, 0x6c00);
2299 bnx2_read_phy(bp, 0x1c, &val);
2300 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2301 }
2302
2303 return 0;
2304}
2305
2306static int
9a120bc5 2307bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2308{
5b0c76ad
MC		 2309 u32 val;
2310
9a120bc5
MC		 2311 if (reset_phy)
2312 bnx2_reset_phy(bp);
27a005b8 2313
583c28e5 2314 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2315 bnx2_write_phy(bp, 0x18, 0x0c00);
2316 bnx2_write_phy(bp, 0x17, 0x000a);
2317 bnx2_write_phy(bp, 0x15, 0x310b);
2318 bnx2_write_phy(bp, 0x17, 0x201f);
2319 bnx2_write_phy(bp, 0x15, 0x9506);
2320 bnx2_write_phy(bp, 0x17, 0x401f);
2321 bnx2_write_phy(bp, 0x15, 0x14e2);
2322 bnx2_write_phy(bp, 0x18, 0x0400);
2323 }
2324
583c28e5 2325 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2326 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2327 MII_BNX2_DSP_EXPAND_REG | 0x8);
2328 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2329 val &= ~(1 << 8);
2330 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2331 }
2332
b6016b76 2333 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2334 /* Set extended packet length bit */
2335 bnx2_write_phy(bp, 0x18, 0x7);
2336 bnx2_read_phy(bp, 0x18, &val);
2337 bnx2_write_phy(bp, 0x18, val | 0x4000);
2338
2339 bnx2_read_phy(bp, 0x10, &val);
2340 bnx2_write_phy(bp, 0x10, val | 0x1);
2341 }
2342 else {
b6016b76
MC		 2343 bnx2_write_phy(bp, 0x18, 0x7);
2344 bnx2_read_phy(bp, 0x18, &val);
2345 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2346
2347 bnx2_read_phy(bp, 0x10, &val);
2348 bnx2_write_phy(bp, 0x10, val & ~0x1);
2349 }
2350
5b0c76ad
MC		 2351 /* ethernet@wirespeed */
2352 bnx2_write_phy(bp, 0x18, 0x7007);
2353 bnx2_read_phy(bp, 0x18, &val);
2354 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2355 return 0;
2356}
2357
2358
2359static int
9a120bc5 2360bnx2_init_phy(struct bnx2 *bp, int reset_phy)
52d07b1f
HH		 2361__releases(&bp->phy_lock)
2362__acquires(&bp->phy_lock)
b6016b76
MC		 2363{
2364 u32 val;
2365 int rc = 0;
2366
583c28e5
MC		 2367 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2368 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2369
ca58c3af
MC		 2370 bp->mii_bmcr = MII_BMCR;
2371 bp->mii_bmsr = MII_BMSR;
27a005b8 2372 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2373 bp->mii_adv = MII_ADVERTISE;
2374 bp->mii_lpa = MII_LPA;
2375
b6016b76
MC		 2376 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2377
583c28e5 2378 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2379 goto setup_phy;
2380
b6016b76
MC		 2381 bnx2_read_phy(bp, MII_PHYSID1, &val);
2382 bp->phy_id = val << 16;
2383 bnx2_read_phy(bp, MII_PHYSID2, &val);
2384 bp->phy_id |= val & 0xffff;
2385
583c28e5 2386 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad 2387 if (CHIP_NUM(bp) == CHIP_NUM_5706)
9a120bc5 2388 rc = bnx2_init_5706s_phy(bp, reset_phy);
5b0c76ad 2389 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
9a120bc5 2390 rc = bnx2_init_5708s_phy(bp, reset_phy);
27a005b8 2391 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
9a120bc5 2392 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2393 }
2394 else {
9a120bc5 2395 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2396 }
2397
0d8a6571
MC		 2398setup_phy:
2399 if (!rc)
2400 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2401
2402 return rc;
2403}
2404
2405static int
2406bnx2_set_mac_loopback(struct bnx2 *bp)
2407{
2408 u32 mac_mode;
2409
2410 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2411 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2412 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2413 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2414 bp->link_up = 1;
2415 return 0;
2416}
2417
bc5a0690
MC		 2418static int bnx2_test_link(struct bnx2 *);
2419
2420static int
2421bnx2_set_phy_loopback(struct bnx2 *bp)
2422{
2423 u32 mac_mode;
2424 int rc, i;
2425
2426 spin_lock_bh(&bp->phy_lock);
ca58c3af 2427 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2428 BMCR_SPEED1000);
2429 spin_unlock_bh(&bp->phy_lock);
2430 if (rc)
2431 return rc;
2432
2433 for (i = 0; i < 10; i++) {
2434 if (bnx2_test_link(bp) == 0)
2435 break;
80be4434 2436 msleep(100);
bc5a0690
MC		 2437 }
2438
2439 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2440 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2441 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2442 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2443
2444 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2445 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2446 bp->link_up = 1;
2447 return 0;
2448}
2449
ecdbf6e0
JH		 2450static void
2451bnx2_dump_mcp_state(struct bnx2 *bp)
2452{
2453 struct net_device *dev = bp->dev;
2454 u32 mcp_p0, mcp_p1;
2455
2456 netdev_err(dev, "<--- start MCP states dump --->\n");
2457 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
2458 mcp_p0 = BNX2_MCP_STATE_P0;
2459 mcp_p1 = BNX2_MCP_STATE_P1;
2460 } else {
2461 mcp_p0 = BNX2_MCP_STATE_P0_5708;
2462 mcp_p1 = BNX2_MCP_STATE_P1_5708;
2463 }
2464 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
2465 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
2466 netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n",
2467 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),
2468 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),
2469 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));
2470 netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n",
2471 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2472 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2473 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));
2474 netdev_err(dev, "DEBUG: shmem states:\n");
2475 netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]",
2476 bnx2_shmem_rd(bp, BNX2_DRV_MB),
2477 bnx2_shmem_rd(bp, BNX2_FW_MB),
2478 bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
2479 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
2480 netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]",
2481 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
2482 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
2483 pr_cont(" condition[%08x]\n",
2484 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
2485 DP_SHMEM_LINE(bp, 0x3cc);
2486 DP_SHMEM_LINE(bp, 0x3dc);
2487 DP_SHMEM_LINE(bp, 0x3ec);
2488 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
2489 netdev_err(dev, "<--- end MCP states dump --->\n");
2490}
2491
b6016b76 2492static int
a2f13890 2493bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
b6016b76
MC		 2494{
2495 int i;
2496 u32 val;
2497
b6016b76
MC		 2498 bp->fw_wr_seq++;
2499 msg_data |= bp->fw_wr_seq;
2500
2726d6e1 2501 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2502
a2f13890
MC		 2503 if (!ack)
2504 return 0;
2505
b6016b76 2506 /* wait for an acknowledgement. */
40105c0b 2507 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
b090ae2b 2508 msleep(10);
b6016b76 2509
2726d6e1 2510 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2511
2512 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2513 break;
2514 }
b090ae2b
MC		 2515 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2516 return 0;
b6016b76
MC		 2517
2518 /* If we timed out, inform the firmware that this is the case. */
b090ae2b 2519 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
b6016b76
MC		 2520 msg_data &= ~BNX2_DRV_MSG_CODE;
2521 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2522
2726d6e1 2523 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
ecdbf6e0
JH		 2524 if (!silent) {
2525 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2526 bnx2_dump_mcp_state(bp);
2527 }
b6016b76 2528
b6016b76
MC		 2529 return -EBUSY;
2530 }
2531
b090ae2b
MC		 2532 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2533 return -EIO;
2534
b6016b76
MC		 2535 return 0;
2536}
2537
59b47d8a
MC		 2538static int
2539bnx2_init_5709_context(struct bnx2 *bp)
2540{
2541 int i, ret = 0;
2542 u32 val;
2543
2544 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2545 val |= (BCM_PAGE_BITS - 8) << 16;
2546 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2547 for (i = 0; i < 10; i++) {
2548 val = REG_RD(bp, BNX2_CTX_COMMAND);
2549 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2550 break;
2551 udelay(2);
2552 }
2553 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2554 return -EBUSY;
2555
59b47d8a
MC		 2556 for (i = 0; i < bp->ctx_pages; i++) {
2557 int j;
2558
352f7687
MC		 2559 if (bp->ctx_blk[i])
2560 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2561 else
2562 return -ENOMEM;
2563
59b47d8a
MC		 2564 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2565 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2566 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2567 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2568 (u64) bp->ctx_blk_mapping[i] >> 32);
2569 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2570 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2571 for (j = 0; j < 10; j++) {
2572
2573 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2574 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2575 break;
2576 udelay(5);
2577 }
2578 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2579 ret = -EBUSY;
2580 break;
2581 }
2582 }
2583 return ret;
2584}
2585
b6016b76
MC		 2586static void
2587bnx2_init_context(struct bnx2 *bp)
2588{
2589 u32 vcid;
2590
2591 vcid = 96;
2592 while (vcid) {
2593 u32 vcid_addr, pcid_addr, offset;
7947b20e 2594 int i;
b6016b76
MC		 2595
2596 vcid--;
2597
2598 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2599 u32 new_vcid;
2600
2601 vcid_addr = GET_PCID_ADDR(vcid);
2602 if (vcid & 0x8) {
2603 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2604 }
2605 else {
2606 new_vcid = vcid;
2607 }
2608 pcid_addr = GET_PCID_ADDR(new_vcid);
2609 }
2610 else {
2611 vcid_addr = GET_CID_ADDR(vcid);
2612 pcid_addr = vcid_addr;
2613 }
2614
7947b20e
MC		 2615 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2616 vcid_addr += (i << PHY_CTX_SHIFT);
2617 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2618
5d5d0015 2619 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2620 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2621
7947b20e
MC		 2622 /* Zero out the context. */
2623 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2624 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2625 }
b6016b76
MC		 2626 }
2627}
2628
2629static int
2630bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2631{
2632 u16 *good_mbuf;
2633 u32 good_mbuf_cnt;
2634 u32 val;
2635
2636 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2637 if (good_mbuf == NULL) {
3a9c6a49 2638 pr_err("Failed to allocate memory in %s\n", __func__);
b6016b76
MC		 2639 return -ENOMEM;
2640 }
2641
2642 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2643 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2644
2645 good_mbuf_cnt = 0;
2646
2647 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2648 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2649 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2650 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2651 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2652
2726d6e1 2653 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2654
2655 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2656
2657 /* The addresses with Bit 9 set are bad memory blocks. */
2658 if (!(val & (1 << 9))) {
2659 good_mbuf[good_mbuf_cnt] = (u16) val;
2660 good_mbuf_cnt++;
2661 }
2662
2726d6e1 2663 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2664 }
2665
2666 /* Free the good ones back to the mbuf pool thus discarding
2667 * all the bad ones. */
2668 while (good_mbuf_cnt) {
2669 good_mbuf_cnt--;
2670
2671 val = good_mbuf[good_mbuf_cnt];
2672 val = (val << 9) | val | 1;
2673
2726d6e1 2674 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2675 }
2676 kfree(good_mbuf);
2677 return 0;
2678}
2679
2680static void
5fcaed01 2681bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
b6016b76
MC		 2682{
2683 u32 val;
b6016b76
MC		 2684
2685 val = (mac_addr[0] << 8) | mac_addr[1];
2686
5fcaed01 2687 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
b6016b76 2688
6aa20a22 2689 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2690 (mac_addr[4] << 8) | mac_addr[5];
2691
5fcaed01 2692 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
b6016b76
MC		 2693}
2694
47bf4246 2695static inline int
a2df00aa 2696bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
47bf4246
MC		 2697{
2698 dma_addr_t mapping;
bb4f98ab 2699 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246 2700 struct rx_bd *rxbd =
bb4f98ab 2701 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
a2df00aa 2702 struct page *page = alloc_page(gfp);
47bf4246
MC		 2703
2704 if (!page)
2705 return -ENOMEM;
36227e88 2706 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
47bf4246 2707 PCI_DMA_FROMDEVICE);
36227e88 2708 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 2709 __free_page(page);
2710 return -EIO;
2711 }
2712
47bf4246 2713 rx_pg->page = page;
1a4ccc2d 2714 dma_unmap_addr_set(rx_pg, mapping, mapping);
47bf4246
MC		 2715 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2716 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2717 return 0;
2718}
2719
2720static void
bb4f98ab 2721bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246 2722{
bb4f98ab 2723 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246
MC		 2724 struct page *page = rx_pg->page;
2725
2726 if (!page)
2727 return;
2728
36227e88
SG		 2729 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2730 PAGE_SIZE, PCI_DMA_FROMDEVICE);
47bf4246
MC		 2731
2732 __free_page(page);
2733 rx_pg->page = NULL;
2734}
2735
b6016b76 2736static inline int
a2df00aa 2737bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
b6016b76
MC		 2738{
2739 struct sk_buff *skb;
bb4f98ab 2740 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
b6016b76 2741 dma_addr_t mapping;
bb4f98ab 2742 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 2743 unsigned long align;
2744
a2df00aa 2745 skb = __netdev_alloc_skb(bp->dev, bp->rx_buf_size, gfp);
b6016b76
MC		 2746 if (skb == NULL) {
2747 return -ENOMEM;
2748 }
2749
59b47d8a
MC		 2750 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2751 skb_reserve(skb, BNX2_RX_ALIGN - align);
b6016b76 2752
36227e88
SG		 2753 mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_use_size,
2754 PCI_DMA_FROMDEVICE);
2755 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 2756 dev_kfree_skb(skb);
2757 return -EIO;
2758 }
b6016b76
MC		 2759
2760 rx_buf->skb = skb;
a33fa66b 2761 rx_buf->desc = (struct l2_fhdr *) skb->data;
1a4ccc2d 2762 dma_unmap_addr_set(rx_buf, mapping, mapping);
b6016b76
MC		 2763
2764 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2765 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2766
bb4f98ab 2767 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2768
2769 return 0;
2770}
2771
da3e4fbe 2772static int
35efa7c1 2773bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2774{
43e80b89 2775 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76 2776 u32 new_link_state, old_link_state;
da3e4fbe 2777 int is_set = 1;
b6016b76 2778
da3e4fbe
MC		 2779 new_link_state = sblk->status_attn_bits & event;
2780 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2781 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2782 if (new_link_state)
2783 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2784 else
2785 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2786 } else
2787 is_set = 0;
2788
2789 return is_set;
2790}
2791
2792static void
35efa7c1 2793bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2794{
74ecc62d
MC		 2795 spin_lock(&bp->phy_lock);
2796
2797 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2798 bnx2_set_link(bp);
35efa7c1 2799 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2800 bnx2_set_remote_link(bp);
2801
74ecc62d
MC		 2802 spin_unlock(&bp->phy_lock);
2803
b6016b76
MC		 2804}
2805
ead7270b 2806static inline u16
35efa7c1 2807bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2808{
2809 u16 cons;
2810
43e80b89
MC		 2811 /* Tell compiler that status block fields can change. */
2812 barrier();
2813 cons = *bnapi->hw_tx_cons_ptr;
581daf7e 2814 barrier();
ead7270b
MC		 2815 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2816 cons++;
2817 return cons;
2818}
2819
57851d84
MC		 2820static int
2821bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2822{
35e9010b 2823 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
b6016b76 2824 u16 hw_cons, sw_cons, sw_ring_cons;
706bf240
BL		 2825 int tx_pkt = 0, index;
2826 struct netdev_queue *txq;
2827
2828 index = (bnapi - bp->bnx2_napi);
2829 txq = netdev_get_tx_queue(bp->dev, index);
b6016b76 2830
35efa7c1 2831 hw_cons = bnx2_get_hw_tx_cons(bnapi);
35e9010b 2832 sw_cons = txr->tx_cons;
b6016b76
MC		 2833
2834 while (sw_cons != hw_cons) {
3d16af86 2835 struct sw_tx_bd *tx_buf;
b6016b76
MC		 2836 struct sk_buff *skb;
2837 int i, last;
2838
2839 sw_ring_cons = TX_RING_IDX(sw_cons);
2840
35e9010b 2841 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
b6016b76 2842 skb = tx_buf->skb;
1d39ed56 2843
d62fda08
ED		 2844 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2845 prefetch(&skb->end);
2846
b6016b76 2847 /* partial BD completions possible with TSO packets */
d62fda08 2848 if (tx_buf->is_gso) {
b6016b76
MC		 2849 u16 last_idx, last_ring_idx;
2850
d62fda08
ED		 2851 last_idx = sw_cons + tx_buf->nr_frags + 1;
2852 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
b6016b76
MC		 2853 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2854 last_idx++;
2855 }
2856 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2857 break;
2858 }
2859 }
1d39ed56 2860
36227e88 2861 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7 2862 skb_headlen(skb), PCI_DMA_TODEVICE);
b6016b76
MC		 2863
2864 tx_buf->skb = NULL;
d62fda08 2865 last = tx_buf->nr_frags;
b6016b76
MC		 2866
2867 for (i = 0; i < last; i++) {
2868 sw_cons = NEXT_TX_BD(sw_cons);
e95524a7 2869
36227e88 2870 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 2871 dma_unmap_addr(
e95524a7
AD		 2872 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2873 mapping),
2874 skb_shinfo(skb)->frags[i].size,
2875 PCI_DMA_TODEVICE);
b6016b76
MC		 2876 }
2877
2878 sw_cons = NEXT_TX_BD(sw_cons);
2879
745720e5 2880 dev_kfree_skb(skb);
57851d84
MC		 2881 tx_pkt++;
2882 if (tx_pkt == budget)
2883 break;
b6016b76 2884
d62fda08
ED		 2885 if (hw_cons == sw_cons)
2886 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2887 }
2888
35e9010b
MC		 2889 txr->hw_tx_cons = hw_cons;
2890 txr->tx_cons = sw_cons;
706bf240 2891
2f8af120 2892 /* Need to make the tx_cons update visible to bnx2_start_xmit()
706bf240 2893 * before checking for netif_tx_queue_stopped(). Without the
2f8af120
MC		 2894 * memory barrier, there is a small possibility that bnx2_start_xmit()
2895 * will miss it and cause the queue to be stopped forever.
2896 */
2897 smp_mb();
b6016b76 2898
706bf240 2899 if (unlikely(netif_tx_queue_stopped(txq)) &&
35e9010b 2900 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
706bf240
BL		 2901 __netif_tx_lock(txq, smp_processor_id());
2902 if ((netif_tx_queue_stopped(txq)) &&
35e9010b 2903 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
706bf240
BL		 2904 netif_tx_wake_queue(txq);
2905 __netif_tx_unlock(txq);
b6016b76 2906 }
706bf240 2907
57851d84 2908 return tx_pkt;
b6016b76
MC		 2909}
2910
1db82f2a 2911static void
bb4f98ab 2912bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
a1f60190 2913 struct sk_buff *skb, int count)
1db82f2a
MC		 2914{
2915 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2916 struct rx_bd *cons_bd, *prod_bd;
1db82f2a 2917 int i;
3d16af86 2918 u16 hw_prod, prod;
bb4f98ab 2919 u16 cons = rxr->rx_pg_cons;
1db82f2a 2920
3d16af86
BL		 2921 cons_rx_pg = &rxr->rx_pg_ring[cons];
2922
2923 /* The caller was unable to allocate a new page to replace the
2924 * last one in the frags array, so we need to recycle that page
2925 * and then free the skb.
2926 */
2927 if (skb) {
2928 struct page *page;
2929 struct skb_shared_info *shinfo;
2930
2931 shinfo = skb_shinfo(skb);
2932 shinfo->nr_frags--;
b7b6a688
IC		 2933 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]);
2934 __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL);
3d16af86
BL		 2935
2936 cons_rx_pg->page = page;
2937 dev_kfree_skb(skb);
2938 }
2939
2940 hw_prod = rxr->rx_pg_prod;
2941
1db82f2a
MC		 2942 for (i = 0; i < count; i++) {
2943 prod = RX_PG_RING_IDX(hw_prod);
2944
bb4f98ab
MC		 2945 prod_rx_pg = &rxr->rx_pg_ring[prod];
2946 cons_rx_pg = &rxr->rx_pg_ring[cons];
2947 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2948 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1db82f2a 2949
1db82f2a
MC		 2950 if (prod != cons) {
2951 prod_rx_pg->page = cons_rx_pg->page;
2952 cons_rx_pg->page = NULL;
1a4ccc2d
FT		 2953 dma_unmap_addr_set(prod_rx_pg, mapping,
2954 dma_unmap_addr(cons_rx_pg, mapping));
1db82f2a
MC		 2955
2956 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2957 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2958
2959 }
2960 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2961 hw_prod = NEXT_RX_BD(hw_prod);
2962 }
bb4f98ab
MC		 2963 rxr->rx_pg_prod = hw_prod;
2964 rxr->rx_pg_cons = cons;
1db82f2a
MC		 2965}
2966
b6016b76 2967static inline void
bb4f98ab
MC		 2968bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2969 struct sk_buff *skb, u16 cons, u16 prod)
b6016b76 2970{
236b6394
MC		 2971 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2972 struct rx_bd *cons_bd, *prod_bd;
2973
bb4f98ab
MC		 2974 cons_rx_buf = &rxr->rx_buf_ring[cons];
2975 prod_rx_buf = &rxr->rx_buf_ring[prod];
b6016b76 2976
36227e88 2977 dma_sync_single_for_device(&bp->pdev->dev,
1a4ccc2d 2978 dma_unmap_addr(cons_rx_buf, mapping),
601d3d18 2979 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 2980
bb4f98ab 2981 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2982
236b6394 2983 prod_rx_buf->skb = skb;
a33fa66b 2984 prod_rx_buf->desc = (struct l2_fhdr *) skb->data;
b6016b76 2985
236b6394
MC		 2986 if (cons == prod)
2987 return;
b6016b76 2988
1a4ccc2d
FT		 2989 dma_unmap_addr_set(prod_rx_buf, mapping,
2990 dma_unmap_addr(cons_rx_buf, mapping));
236b6394 2991
bb4f98ab
MC		 2992 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2993 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2994 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2995 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2996}
2997
85833c62 2998static int
bb4f98ab 2999bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
a1f60190
MC		 3000 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
3001 u32 ring_idx)
85833c62
MC		 3002{
3003 int err;
3004 u16 prod = ring_idx & 0xffff;
3005
a2df00aa 3006 err = bnx2_alloc_rx_skb(bp, rxr, prod, GFP_ATOMIC);
85833c62 3007 if (unlikely(err)) {
bb4f98ab 3008 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
1db82f2a
MC		 3009 if (hdr_len) {
3010 unsigned int raw_len = len + 4;
3011 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
3012
bb4f98ab 3013 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
1db82f2a 3014 }
85833c62
MC		 3015 return err;
3016 }
3017
d89cb6af 3018 skb_reserve(skb, BNX2_RX_OFFSET);
36227e88 3019 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
85833c62
MC		 3020 PCI_DMA_FROMDEVICE);
3021
1db82f2a
MC		 3022 if (hdr_len == 0) {
3023 skb_put(skb, len);
3024 return 0;
3025 } else {
3026 unsigned int i, frag_len, frag_size, pages;
3027 struct sw_pg *rx_pg;
bb4f98ab
MC		 3028 u16 pg_cons = rxr->rx_pg_cons;
3029 u16 pg_prod = rxr->rx_pg_prod;
1db82f2a
MC		 3030
3031 frag_size = len + 4 - hdr_len;
3032 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3033 skb_put(skb, hdr_len);
3034
3035 for (i = 0; i < pages; i++) {
3d16af86
BL		 3036 dma_addr_t mapping_old;
3037
1db82f2a
MC		 3038 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3039 if (unlikely(frag_len <= 4)) {
3040 unsigned int tail = 4 - frag_len;
3041
bb4f98ab
MC		 3042 rxr->rx_pg_cons = pg_cons;
3043 rxr->rx_pg_prod = pg_prod;
3044 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
a1f60190 3045 pages - i);
1db82f2a
MC		 3046 skb->len -= tail;
3047 if (i == 0) {
3048 skb->tail -= tail;
3049 } else {
3050 skb_frag_t *frag =
3051 &skb_shinfo(skb)->frags[i - 1];
3052 frag->size -= tail;
3053 skb->data_len -= tail;
3054 skb->truesize -= tail;
3055 }
3056 return 0;
3057 }
bb4f98ab 3058 rx_pg = &rxr->rx_pg_ring[pg_cons];
1db82f2a 3059
3d16af86
BL		 3060 /* Don't unmap yet. If we're unable to allocate a new
3061 * page, we need to recycle the page and the DMA addr.
3062 */
1a4ccc2d 3063 mapping_old = dma_unmap_addr(rx_pg, mapping);
1db82f2a
MC		 3064 if (i == pages - 1)
3065 frag_len -= 4;
3066
3067 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3068 rx_pg->page = NULL;
3069
bb4f98ab 3070 err = bnx2_alloc_rx_page(bp, rxr,
a2df00aa
SG		 3071 RX_PG_RING_IDX(pg_prod),
3072 GFP_ATOMIC);
1db82f2a 3073 if (unlikely(err)) {
bb4f98ab
MC		 3074 rxr->rx_pg_cons = pg_cons;
3075 rxr->rx_pg_prod = pg_prod;
3076 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
a1f60190 3077 pages - i);
1db82f2a
MC		 3078 return err;
3079 }
3080
36227e88 3081 dma_unmap_page(&bp->pdev->dev, mapping_old,
3d16af86
BL		 3082 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3083
1db82f2a
MC		 3084 frag_size -= frag_len;
3085 skb->data_len += frag_len;
3086 skb->truesize += frag_len;
3087 skb->len += frag_len;
3088
3089 pg_prod = NEXT_RX_BD(pg_prod);
3090 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3091 }
bb4f98ab
MC		 3092 rxr->rx_pg_prod = pg_prod;
3093 rxr->rx_pg_cons = pg_cons;
1db82f2a 3094 }
85833c62
MC		 3095 return 0;
3096}
3097
c09c2627 3098static inline u16
35efa7c1 3099bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 3100{
bb4f98ab
MC		 3101 u16 cons;
3102
43e80b89
MC		 3103 /* Tell compiler that status block fields can change. */
3104 barrier();
3105 cons = *bnapi->hw_rx_cons_ptr;
581daf7e 3106 barrier();
c09c2627
MC		 3107 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3108 cons++;
3109 return cons;
3110}
3111
b6016b76 3112static int
35efa7c1 3113bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 3114{
bb4f98ab 3115 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76
MC		 3116 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3117 struct l2_fhdr *rx_hdr;
1db82f2a 3118 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 3119
35efa7c1 3120 hw_cons = bnx2_get_hw_rx_cons(bnapi);
bb4f98ab
MC		 3121 sw_cons = rxr->rx_cons;
3122 sw_prod = rxr->rx_prod;
b6016b76
MC		 3123
3124 /* Memory barrier necessary as speculative reads of the rx
3125 * buffer can be ahead of the index in the status block
3126 */
3127 rmb();
3128 while (sw_cons != hw_cons) {
1db82f2a 3129 unsigned int len, hdr_len;
ade2bfe7 3130 u32 status;
a33fa66b 3131 struct sw_bd *rx_buf, *next_rx_buf;
b6016b76 3132 struct sk_buff *skb;
236b6394 3133 dma_addr_t dma_addr;
b6016b76
MC		 3134
3135 sw_ring_cons = RX_RING_IDX(sw_cons);
3136 sw_ring_prod = RX_RING_IDX(sw_prod);
3137
bb4f98ab 3138 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
b6016b76 3139 skb = rx_buf->skb;
a33fa66b 3140 prefetchw(skb);
236b6394 3141
aabef8b2
FT		 3142 next_rx_buf =
3143 &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3144 prefetch(next_rx_buf->desc);
3145
236b6394
MC		 3146 rx_buf->skb = NULL;
3147
1a4ccc2d 3148 dma_addr = dma_unmap_addr(rx_buf, mapping);
236b6394 3149
36227e88 3150 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
601d3d18
BL		 3151 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3152 PCI_DMA_FROMDEVICE);
b6016b76 3153
a33fa66b 3154 rx_hdr = rx_buf->desc;
1db82f2a 3155 len = rx_hdr->l2_fhdr_pkt_len;
990ec380 3156 status = rx_hdr->l2_fhdr_status;
b6016b76 3157
1db82f2a
MC		 3158 hdr_len = 0;
3159 if (status & L2_FHDR_STATUS_SPLIT) {
3160 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3161 pg_ring_used = 1;
3162 } else if (len > bp->rx_jumbo_thresh) {
3163 hdr_len = bp->rx_jumbo_thresh;
3164 pg_ring_used = 1;
3165 }
3166
990ec380
MC		 3167 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3168 L2_FHDR_ERRORS_PHY_DECODE |
3169 L2_FHDR_ERRORS_ALIGNMENT |
3170 L2_FHDR_ERRORS_TOO_SHORT |
3171 L2_FHDR_ERRORS_GIANT_FRAME))) {
3172
3173 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3174 sw_ring_prod);
3175 if (pg_ring_used) {
3176 int pages;
3177
3178 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3179
3180 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3181 }
3182 goto next_rx;
3183 }
3184
1db82f2a 3185 len -= 4;
b6016b76 3186
5d5d0015 3187 if (len <= bp->rx_copy_thresh) {
b6016b76
MC		 3188 struct sk_buff *new_skb;
3189
f22828e8 3190 new_skb = netdev_alloc_skb(bp->dev, len + 6);
85833c62 3191 if (new_skb == NULL) {
bb4f98ab 3192 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
85833c62
MC		 3193 sw_ring_prod);
3194 goto next_rx;
3195 }
b6016b76
MC		 3196
3197 /* aligned copy */
d89cb6af 3198 skb_copy_from_linear_data_offset(skb,
f22828e8
MC		 3199 BNX2_RX_OFFSET - 6,
3200 new_skb->data, len + 6);
3201 skb_reserve(new_skb, 6);
b6016b76 3202 skb_put(new_skb, len);
b6016b76 3203
bb4f98ab 3204 bnx2_reuse_rx_skb(bp, rxr, skb,
b6016b76
MC		 3205 sw_ring_cons, sw_ring_prod);
3206
3207 skb = new_skb;
bb4f98ab 3208 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
a1f60190 3209 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
b6016b76 3210 goto next_rx;
b6016b76 3211
f22828e8 3212 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
7d0fd211
JG		 3213 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
3214 __vlan_hwaccel_put_tag(skb, rx_hdr->l2_fhdr_vlan_tag);
f22828e8 3215
b6016b76
MC		 3216 skb->protocol = eth_type_trans(skb, bp->dev);
3217
3218 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 3219 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 3220
745720e5 3221 dev_kfree_skb(skb);
b6016b76
MC		 3222 goto next_rx;
3223
3224 }
3225
bc8acf2c 3226 skb_checksum_none_assert(skb);
8d7dfc2b 3227 if ((bp->dev->features & NETIF_F_RXCSUM) &&
b6016b76
MC		 3228 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3229 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3230
ade2bfe7
MC		 3231 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3232 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 3233 skb->ip_summed = CHECKSUM_UNNECESSARY;
3234 }
fdc8541d
MC		 3235 if ((bp->dev->features & NETIF_F_RXHASH) &&
3236 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3237 L2_FHDR_STATUS_USE_RXHASH))
3238 skb->rxhash = rx_hdr->l2_fhdr_hash;
b6016b76 3239
0c8dfc83 3240 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
7d0fd211 3241 napi_gro_receive(&bnapi->napi, skb);
b6016b76
MC		 3242 rx_pkt++;
3243
3244next_rx:
b6016b76
MC		 3245 sw_cons = NEXT_RX_BD(sw_cons);
3246 sw_prod = NEXT_RX_BD(sw_prod);
3247
3248 if ((rx_pkt == budget))
3249 break;
f4e418f7
MC		 3250
3251 /* Refresh hw_cons to see if there is new work */
3252 if (sw_cons == hw_cons) {
35efa7c1 3253 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 3254 rmb();
3255 }
b6016b76 3256 }
bb4f98ab
MC		 3257 rxr->rx_cons = sw_cons;
3258 rxr->rx_prod = sw_prod;
b6016b76 3259
1db82f2a 3260 if (pg_ring_used)
bb4f98ab 3261 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
1db82f2a 3262
bb4f98ab 3263 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
b6016b76 3264
bb4f98ab 3265 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 3266
3267 mmiowb();
3268
3269 return rx_pkt;
3270
3271}
3272
3273/* MSI ISR - The only difference between this and the INTx ISR
3274 * is that the MSI interrupt is always serviced.
3275 */
3276static irqreturn_t
7d12e780 3277bnx2_msi(int irq, void *dev_instance)
b6016b76 3278{
f0ea2e63
MC		 3279 struct bnx2_napi *bnapi = dev_instance;
3280 struct bnx2 *bp = bnapi->bp;
b6016b76 3281
43e80b89 3282 prefetch(bnapi->status_blk.msi);
b6016b76
MC		 3283 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3284 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3285 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3286
3287 /* Return here if interrupt is disabled. */
73eef4cd
MC		 3288 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3289 return IRQ_HANDLED;
b6016b76 3290
288379f0 3291 napi_schedule(&bnapi->napi);
b6016b76 3292
73eef4cd 3293 return IRQ_HANDLED;
b6016b76
MC		 3294}
3295
8e6a72c4
MC		 3296static irqreturn_t
3297bnx2_msi_1shot(int irq, void *dev_instance)
3298{
f0ea2e63
MC		 3299 struct bnx2_napi *bnapi = dev_instance;
3300 struct bnx2 *bp = bnapi->bp;
8e6a72c4 3301
43e80b89 3302 prefetch(bnapi->status_blk.msi);
8e6a72c4
MC		 3303
3304 /* Return here if interrupt is disabled. */
3305 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3306 return IRQ_HANDLED;
3307
288379f0 3308 napi_schedule(&bnapi->napi);
8e6a72c4
MC		 3309
3310 return IRQ_HANDLED;
3311}
3312
b6016b76 3313static irqreturn_t
7d12e780 3314bnx2_interrupt(int irq, void *dev_instance)
b6016b76 3315{
f0ea2e63
MC		 3316 struct bnx2_napi *bnapi = dev_instance;
3317 struct bnx2 *bp = bnapi->bp;
43e80b89 3318 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76
MC		 3319
3320 /* When using INTx, it is possible for the interrupt to arrive
3321 * at the CPU before the status block posted prior to the
3322 * interrupt. Reading a register will flush the status block.
3323 * When using MSI, the MSI message will always complete after
3324 * the status block write.
3325 */
35efa7c1 3326 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 3327 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3328 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 3329 return IRQ_NONE;
b6016b76
MC		 3330
3331 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3332 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3333 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3334
b8a7ce7b
MC		 3335 /* Read back to deassert IRQ immediately to avoid too many
3336 * spurious interrupts.
3337 */
3338 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3339
b6016b76 3340 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 3341 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3342 return IRQ_HANDLED;
b6016b76 3343
288379f0 3344 if (napi_schedule_prep(&bnapi->napi)) {
35efa7c1 3345 bnapi->last_status_idx = sblk->status_idx;
288379f0 3346 __napi_schedule(&bnapi->napi);
b8a7ce7b 3347 }
b6016b76 3348
73eef4cd 3349 return IRQ_HANDLED;
b6016b76
MC		 3350}
3351
f4e418f7 3352static inline int
43e80b89 3353bnx2_has_fast_work(struct bnx2_napi *bnapi)
f4e418f7 3354{
35e9010b 3355 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 3356 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
f4e418f7 3357
bb4f98ab 3358 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
35e9010b 3359 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
f4e418f7 3360 return 1;
43e80b89
MC		 3361 return 0;
3362}
3363
3364#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3365 STATUS_ATTN_BITS_TIMER_ABORT)
3366
3367static inline int
3368bnx2_has_work(struct bnx2_napi *bnapi)
3369{
3370 struct status_block *sblk = bnapi->status_blk.msi;
3371
3372 if (bnx2_has_fast_work(bnapi))
3373 return 1;
f4e418f7 3374
4edd473f
MC		 3375#ifdef BCM_CNIC
3376 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3377 return 1;
3378#endif
3379
da3e4fbe
MC		 3380 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3381 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3382 return 1;
3383
3384 return 0;
3385}
3386
efba0180
MC		 3387static void
3388bnx2_chk_missed_msi(struct bnx2 *bp)
3389{
3390 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3391 u32 msi_ctrl;
3392
3393 if (bnx2_has_work(bnapi)) {
3394 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3395 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3396 return;
3397
3398 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3399 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3400 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3401 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3402 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3403 }
3404 }
3405
3406 bp->idle_chk_status_idx = bnapi->last_status_idx;
3407}
3408
4edd473f
MC		 3409#ifdef BCM_CNIC
3410static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3411{
3412 struct cnic_ops *c_ops;
3413
3414 if (!bnapi->cnic_present)
3415 return;
3416
3417 rcu_read_lock();
3418 c_ops = rcu_dereference(bp->cnic_ops);
3419 if (c_ops)
3420 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3421 bnapi->status_blk.msi);
3422 rcu_read_unlock();
3423}
3424#endif
3425
43e80b89 3426static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
b6016b76 3427{
43e80b89 3428 struct status_block *sblk = bnapi->status_blk.msi;
da3e4fbe
MC		 3429 u32 status_attn_bits = sblk->status_attn_bits;
3430 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3431
da3e4fbe
MC		 3432 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3433 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3434
35efa7c1 3435 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3436
3437 /* This is needed to take care of transient status
3438 * during link changes.
3439 */
3440 REG_WR(bp, BNX2_HC_COMMAND,
3441 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3442 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76 3443 }
43e80b89
MC		 3444}
3445
3446static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3447 int work_done, int budget)
3448{
3449 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3450 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76 3451
35e9010b 3452 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
57851d84 3453 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3454
bb4f98ab 3455 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
35efa7c1 3456 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3457
6f535763
DM		 3458 return work_done;
3459}
3460
f0ea2e63
MC		 3461static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3462{
3463 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3464 struct bnx2 *bp = bnapi->bp;
3465 int work_done = 0;
3466 struct status_block_msix *sblk = bnapi->status_blk.msix;
3467
3468 while (1) {
3469 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3470 if (unlikely(work_done >= budget))
3471 break;
3472
3473 bnapi->last_status_idx = sblk->status_idx;
3474 /* status idx must be read before checking for more work. */
3475 rmb();
3476 if (likely(!bnx2_has_fast_work(bnapi))) {
3477
288379f0 3478 napi_complete(napi);
f0ea2e63
MC		 3479 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3480 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3481 bnapi->last_status_idx);
3482 break;
3483 }
3484 }
3485 return work_done;
3486}
3487
6f535763
DM		 3488static int bnx2_poll(struct napi_struct *napi, int budget)
3489{
35efa7c1
MC		 3490 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3491 struct bnx2 *bp = bnapi->bp;
6f535763 3492 int work_done = 0;
43e80b89 3493 struct status_block *sblk = bnapi->status_blk.msi;
6f535763
DM		 3494
3495 while (1) {
43e80b89
MC		 3496 bnx2_poll_link(bp, bnapi);
3497
35efa7c1 3498 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3499
4edd473f
MC		 3500#ifdef BCM_CNIC
3501 bnx2_poll_cnic(bp, bnapi);
3502#endif
3503
35efa7c1 3504 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3505 * much work has been processed, so we must read it before
3506 * checking for more work.
3507 */
35efa7c1 3508 bnapi->last_status_idx = sblk->status_idx;
efba0180
MC		 3509
3510 if (unlikely(work_done >= budget))
3511 break;
3512
6dee6421 3513 rmb();
35efa7c1 3514 if (likely(!bnx2_has_work(bnapi))) {
288379f0 3515 napi_complete(napi);
f86e82fb 3516 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3517 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3518 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3519 bnapi->last_status_idx);
6dee6421 3520 break;
6f535763 3521 }
1269a8a6
MC		 3522 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3523 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3524 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3525 bnapi->last_status_idx);
1269a8a6 3526
6f535763
DM		 3527 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3528 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3529 bnapi->last_status_idx);
6f535763
DM		 3530 break;
3531 }
b6016b76
MC		 3532 }
3533
bea3348e 3534 return work_done;
b6016b76
MC		 3535}
3536
932ff279 3537/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3538 * from set_multicast.
3539 */
3540static void
3541bnx2_set_rx_mode(struct net_device *dev)
3542{
972ec0d4 3543 struct bnx2 *bp = netdev_priv(dev);
b6016b76 3544 u32 rx_mode, sort_mode;
ccffad25 3545 struct netdev_hw_addr *ha;
b6016b76 3546 int i;
b6016b76 3547
9f52b564
MC		 3548 if (!netif_running(dev))
3549 return;
3550
c770a65c 3551 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3552
3553 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3554 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3555 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
7d0fd211
JG		 3556 if (!(dev->features & NETIF_F_HW_VLAN_RX) &&
3557 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
b6016b76 3558 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3559 if (dev->flags & IFF_PROMISC) {
3560 /* Promiscuous mode. */
3561 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3562 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3563 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3564 }
3565 else if (dev->flags & IFF_ALLMULTI) {
3566 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3567 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3568 0xffffffff);
3569 }
3570 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3571 }
3572 else {
3573 /* Accept one or more multicast(s). */
b6016b76
MC		 3574 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3575 u32 regidx;
3576 u32 bit;
3577 u32 crc;
3578
3579 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3580
22bedad3
JP		 3581 netdev_for_each_mc_addr(ha, dev) {
3582 crc = ether_crc_le(ETH_ALEN, ha->addr);
b6016b76
MC		 3583 bit = crc & 0xff;
3584 regidx = (bit & 0xe0) >> 5;
3585 bit &= 0x1f;
3586 mc_filter[regidx] |= (1 << bit);
3587 }
3588
3589 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3590 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3591 mc_filter[i]);
3592 }
3593
3594 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3595 }
3596
32e7bfc4 3597 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
5fcaed01
BL		 3598 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3599 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3600 BNX2_RPM_SORT_USER0_PROM_VLAN;
3601 } else if (!(dev->flags & IFF_PROMISC)) {
5fcaed01 3602 /* Add all entries into to the match filter list */
ccffad25 3603 i = 0;
32e7bfc4 3604 netdev_for_each_uc_addr(ha, dev) {
ccffad25 3605 bnx2_set_mac_addr(bp, ha->addr,
5fcaed01
BL		 3606 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3607 sort_mode |= (1 <<
3608 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
ccffad25 3609 i++;
5fcaed01
BL		 3610 }
3611
3612 }
3613
b6016b76
MC		 3614 if (rx_mode != bp->rx_mode) {
3615 bp->rx_mode = rx_mode;
3616 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3617 }
3618
3619 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3620 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3621 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3622
c770a65c 3623 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3624}
3625
57579f76
MC		 3626static int __devinit
3627check_fw_section(const struct firmware *fw,
3628 const struct bnx2_fw_file_section *section,
3629 u32 alignment, bool non_empty)
3630{
3631 u32 offset = be32_to_cpu(section->offset);
3632 u32 len = be32_to_cpu(section->len);
3633
3634 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3635 return -EINVAL;
3636 if ((non_empty && len == 0) || len > fw->size - offset ||
3637 len & (alignment - 1))
3638 return -EINVAL;
3639 return 0;
3640}
3641
3642static int __devinit
3643check_mips_fw_entry(const struct firmware *fw,
3644 const struct bnx2_mips_fw_file_entry *entry)
3645{
3646 if (check_fw_section(fw, &entry->text, 4, true) ||
3647 check_fw_section(fw, &entry->data, 4, false) ||
3648 check_fw_section(fw, &entry->rodata, 4, false))
3649 return -EINVAL;
3650 return 0;
3651}
3652
3653static int __devinit
3654bnx2_request_firmware(struct bnx2 *bp)
b6016b76 3655{
57579f76 3656 const char *mips_fw_file, *rv2p_fw_file;
5ee1c326
BB		 3657 const struct bnx2_mips_fw_file *mips_fw;
3658 const struct bnx2_rv2p_fw_file *rv2p_fw;
57579f76
MC		 3659 int rc;
3660
3661 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3662 mips_fw_file = FW_MIPS_FILE_09;
078b0735
MC		 3663 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3664 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3665 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3666 else
3667 rv2p_fw_file = FW_RV2P_FILE_09;
57579f76
MC		 3668 } else {
3669 mips_fw_file = FW_MIPS_FILE_06;
3670 rv2p_fw_file = FW_RV2P_FILE_06;
3671 }
3672
3673 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3674 if (rc) {
3a9c6a49 3675 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
57579f76
MC		 3676 return rc;
3677 }
3678
3679 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3680 if (rc) {
3a9c6a49 3681 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
57579f76
MC		 3682 return rc;
3683 }
5ee1c326
BB		 3684 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3685 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3686 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3687 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3688 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3689 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3690 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3691 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3a9c6a49 3692 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
57579f76
MC		 3693 return -EINVAL;
3694 }
5ee1c326
BB		 3695 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3696 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3697 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3a9c6a49 3698 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
57579f76
MC		 3699 return -EINVAL;
3700 }
3701
3702 return 0;
3703}
3704
3705static u32
3706rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3707{
3708 switch (idx) {
3709 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3710 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3711 rv2p_code |= RV2P_BD_PAGE_SIZE;
3712 break;
3713 }
3714 return rv2p_code;
3715}
3716
3717static int
3718load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3719 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3720{
3721 u32 rv2p_code_len, file_offset;
3722 __be32 *rv2p_code;
b6016b76 3723 int i;
57579f76
MC		 3724 u32 val, cmd, addr;
3725
3726 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3727 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3728
3729 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
b6016b76 3730
57579f76
MC		 3731 if (rv2p_proc == RV2P_PROC1) {
3732 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3733 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3734 } else {
3735 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3736 addr = BNX2_RV2P_PROC2_ADDR_CMD;
d25be1d3 3737 }
b6016b76
MC		 3738
3739 for (i = 0; i < rv2p_code_len; i += 8) {
57579f76 3740 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
b6016b76 3741 rv2p_code++;
57579f76 3742 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
b6016b76
MC		 3743 rv2p_code++;
3744
57579f76
MC		 3745 val = (i / 8) | cmd;
3746 REG_WR(bp, addr, val);
3747 }
3748
3749 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3750 for (i = 0; i < 8; i++) {
3751 u32 loc, code;
3752
3753 loc = be32_to_cpu(fw_entry->fixup[i]);
3754 if (loc && ((loc * 4) < rv2p_code_len)) {
3755 code = be32_to_cpu(*(rv2p_code + loc - 1));
3756 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3757 code = be32_to_cpu(*(rv2p_code + loc));
3758 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3759 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3760
3761 val = (loc / 2) | cmd;
3762 REG_WR(bp, addr, val);
b6016b76
MC		 3763 }
3764 }
3765
3766 /* Reset the processor, un-stall is done later. */
3767 if (rv2p_proc == RV2P_PROC1) {
3768 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3769 }
3770 else {
3771 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3772 }
57579f76
MC		 3773
3774 return 0;
b6016b76
MC		 3775}
3776
af3ee519 3777static int
57579f76
MC		 3778load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3779 const struct bnx2_mips_fw_file_entry *fw_entry)
b6016b76 3780{
57579f76
MC		 3781 u32 addr, len, file_offset;
3782 __be32 *data;
b6016b76
MC		 3783 u32 offset;
3784 u32 val;
3785
3786 /* Halt the CPU. */
2726d6e1 3787 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3788 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3789 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3790 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3791
3792 /* Load the Text area. */
57579f76
MC		 3793 addr = be32_to_cpu(fw_entry->text.addr);
3794 len = be32_to_cpu(fw_entry->text.len);
3795 file_offset = be32_to_cpu(fw_entry->text.offset);
3796 data = (__be32 *)(bp->mips_firmware->data + file_offset);
ea1f8d5c 3797
57579f76
MC		 3798 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3799 if (len) {
b6016b76
MC		 3800 int j;
3801
57579f76
MC		 3802 for (j = 0; j < (len / 4); j++, offset += 4)
3803 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3804 }
3805
57579f76
MC		 3806 /* Load the Data area. */
3807 addr = be32_to_cpu(fw_entry->data.addr);
3808 len = be32_to_cpu(fw_entry->data.len);
3809 file_offset = be32_to_cpu(fw_entry->data.offset);
3810 data = (__be32 *)(bp->mips_firmware->data + file_offset);
b6016b76 3811
57579f76
MC		 3812 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3813 if (len) {
b6016b76
MC		 3814 int j;
3815
57579f76
MC		 3816 for (j = 0; j < (len / 4); j++, offset += 4)
3817 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3818 }
3819
3820 /* Load the Read-Only area. */
57579f76
MC		 3821 addr = be32_to_cpu(fw_entry->rodata.addr);
3822 len = be32_to_cpu(fw_entry->rodata.len);
3823 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3824 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3825
3826 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3827 if (len) {
b6016b76
MC		 3828 int j;
3829
57579f76
MC		 3830 for (j = 0; j < (len / 4); j++, offset += 4)
3831 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3832 }
3833
3834 /* Clear the pre-fetch instruction. */
2726d6e1 3835 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
57579f76
MC		 3836
3837 val = be32_to_cpu(fw_entry->start_addr);
3838 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
b6016b76
MC		 3839
3840 /* Start the CPU. */
2726d6e1 3841 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3842 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3843 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3844 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3845
3846 return 0;
b6016b76
MC		 3847}
3848
fba9fe91 3849static int
b6016b76
MC		 3850bnx2_init_cpus(struct bnx2 *bp)
3851{
57579f76
MC		 3852 const struct bnx2_mips_fw_file *mips_fw =
3853 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3854 const struct bnx2_rv2p_fw_file *rv2p_fw =
3855 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3856 int rc;
b6016b76
MC		 3857
3858 /* Initialize the RV2P processor. */
57579f76
MC		 3859 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3860 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
b6016b76
MC		 3861
3862 /* Initialize the RX Processor. */
57579f76 3863 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
fba9fe91
MC		 3864 if (rc)
3865 goto init_cpu_err;
3866
b6016b76 3867 /* Initialize the TX Processor. */
57579f76 3868 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
fba9fe91
MC		 3869 if (rc)
3870 goto init_cpu_err;
3871
b6016b76 3872 /* Initialize the TX Patch-up Processor. */
57579f76 3873 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
fba9fe91
MC		 3874 if (rc)
3875 goto init_cpu_err;
3876
b6016b76 3877 /* Initialize the Completion Processor. */
57579f76 3878 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
fba9fe91
MC		 3879 if (rc)
3880 goto init_cpu_err;
3881
d43584c8 3882 /* Initialize the Command Processor. */
57579f76 3883 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
b6016b76 3884
fba9fe91 3885init_cpu_err:
fba9fe91 3886 return rc;
b6016b76
MC		 3887}
3888
3889static int
829ca9a3 3890bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3891{
3892 u16 pmcsr;
3893
3894 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3895
3896 switch (state) {
829ca9a3 3897 case PCI_D0: {
b6016b76
MC		 3898 u32 val;
3899
3900 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3901 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3902 PCI_PM_CTRL_PME_STATUS);
3903
3904 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3905 /* delay required during transition out of D3hot */
3906 msleep(20);
3907
3908 val = REG_RD(bp, BNX2_EMAC_MODE);
3909 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3910 val &= ~BNX2_EMAC_MODE_MPKT;
3911 REG_WR(bp, BNX2_EMAC_MODE, val);
3912
3913 val = REG_RD(bp, BNX2_RPM_CONFIG);
3914 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3915 REG_WR(bp, BNX2_RPM_CONFIG, val);
3916 break;
3917 }
829ca9a3 3918 case PCI_D3hot: {
b6016b76
MC		 3919 int i;
3920 u32 val, wol_msg;
3921
3922 if (bp->wol) {
3923 u32 advertising;
3924 u8 autoneg;
3925
3926 autoneg = bp->autoneg;
3927 advertising = bp->advertising;
3928
239cd343
MC		 3929 if (bp->phy_port == PORT_TP) {
3930 bp->autoneg = AUTONEG_SPEED;
3931 bp->advertising = ADVERTISED_10baseT_Half |
3932 ADVERTISED_10baseT_Full |
3933 ADVERTISED_100baseT_Half |
3934 ADVERTISED_100baseT_Full |
3935 ADVERTISED_Autoneg;
3936 }
b6016b76 3937
239cd343
MC		 3938 spin_lock_bh(&bp->phy_lock);
3939 bnx2_setup_phy(bp, bp->phy_port);
3940 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3941
3942 bp->autoneg = autoneg;
3943 bp->advertising = advertising;
3944
5fcaed01 3945 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 3946
3947 val = REG_RD(bp, BNX2_EMAC_MODE);
3948
3949 /* Enable port mode. */
3950 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3951 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3952 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3953 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3954 if (bp->phy_port == PORT_TP)
3955 val |= BNX2_EMAC_MODE_PORT_MII;
3956 else {
3957 val |= BNX2_EMAC_MODE_PORT_GMII;
3958 if (bp->line_speed == SPEED_2500)
3959 val |= BNX2_EMAC_MODE_25G_MODE;
3960 }
b6016b76
MC		 3961
3962 REG_WR(bp, BNX2_EMAC_MODE, val);
3963
3964 /* receive all multicast */
3965 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3966 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3967 0xffffffff);
3968 }
3969 REG_WR(bp, BNX2_EMAC_RX_MODE,
3970 BNX2_EMAC_RX_MODE_SORT_MODE);
3971
3972 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3973 BNX2_RPM_SORT_USER0_MC_EN;
3974 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3975 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3976 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3977 BNX2_RPM_SORT_USER0_ENA);
3978
3979 /* Need to enable EMAC and RPM for WOL. */
3980 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3981 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3982 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3983 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3984
3985 val = REG_RD(bp, BNX2_RPM_CONFIG);
3986 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3987 REG_WR(bp, BNX2_RPM_CONFIG, val);
3988
3989 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3990 }
3991 else {
3992 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3993 }
3994
f86e82fb 3995 if (!(bp->flags & BNX2_FLAG_NO_WOL))
a2f13890
MC		 3996 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3997 1, 0);
b6016b76
MC		 3998
3999 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4000 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4001 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
4002
4003 if (bp->wol)
4004 pmcsr |= 3;
4005 }
4006 else {
4007 pmcsr |= 3;
4008 }
4009 if (bp->wol) {
4010 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
4011 }
4012 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
4013 pmcsr);
4014
4015 /* No more memory access after this point until
4016 * device is brought back to D0.
4017 */
4018 udelay(50);
4019 break;
4020 }
4021 default:
4022 return -EINVAL;
4023 }
4024 return 0;
4025}
4026
4027static int
4028bnx2_acquire_nvram_lock(struct bnx2 *bp)
4029{
4030 u32 val;
4031 int j;
4032
4033 /* Request access to the flash interface. */
4034 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4035 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4036 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4037 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4038 break;
4039
4040 udelay(5);
4041 }
4042
4043 if (j >= NVRAM_TIMEOUT_COUNT)
4044 return -EBUSY;
4045
4046 return 0;
4047}
4048
4049static int
4050bnx2_release_nvram_lock(struct bnx2 *bp)
4051{
4052 int j;
4053 u32 val;
4054
4055 /* Relinquish nvram interface. */
4056 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4057
4058 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4059 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4060 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4061 break;
4062
4063 udelay(5);
4064 }
4065
4066 if (j >= NVRAM_TIMEOUT_COUNT)
4067 return -EBUSY;
4068
4069 return 0;
4070}
4071
4072
4073static int
4074bnx2_enable_nvram_write(struct bnx2 *bp)
4075{
4076 u32 val;
4077
4078 val = REG_RD(bp, BNX2_MISC_CFG);
4079 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4080
e30372c9 4081 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 4082 int j;
4083
4084 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4085 REG_WR(bp, BNX2_NVM_COMMAND,
4086 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4087
4088 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4089 udelay(5);
4090
4091 val = REG_RD(bp, BNX2_NVM_COMMAND);
4092 if (val & BNX2_NVM_COMMAND_DONE)
4093 break;
4094 }
4095
4096 if (j >= NVRAM_TIMEOUT_COUNT)
4097 return -EBUSY;
4098 }
4099 return 0;
4100}
4101
4102static void
4103bnx2_disable_nvram_write(struct bnx2 *bp)
4104{
4105 u32 val;
4106
4107 val = REG_RD(bp, BNX2_MISC_CFG);
4108 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4109}
4110
4111
4112static void
4113bnx2_enable_nvram_access(struct bnx2 *bp)
4114{
4115 u32 val;
4116
4117 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4118 /* Enable both bits, even on read. */
6aa20a22 4119 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4120 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4121}
4122
4123static void
4124bnx2_disable_nvram_access(struct bnx2 *bp)
4125{
4126 u32 val;
4127
4128 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4129 /* Disable both bits, even after read. */
6aa20a22 4130 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4131 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4132 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4133}
4134
4135static int
4136bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4137{
4138 u32 cmd;
4139 int j;
4140
e30372c9 4141 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 4142 /* Buffered flash, no erase needed */
4143 return 0;
4144
4145 /* Build an erase command */
4146 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4147 BNX2_NVM_COMMAND_DOIT;
4148
4149 /* Need to clear DONE bit separately. */
4150 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4151
4152 /* Address of the NVRAM to read from. */
4153 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4154
4155 /* Issue an erase command. */
4156 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4157
4158 /* Wait for completion. */
4159 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4160 u32 val;
4161
4162 udelay(5);
4163
4164 val = REG_RD(bp, BNX2_NVM_COMMAND);
4165 if (val & BNX2_NVM_COMMAND_DONE)
4166 break;
4167 }
4168
4169 if (j >= NVRAM_TIMEOUT_COUNT)
4170 return -EBUSY;
4171
4172 return 0;
4173}
4174
4175static int
4176bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4177{
4178 u32 cmd;
4179 int j;
4180
4181 /* Build the command word. */
4182 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4183
e30372c9
MC		 4184 /* Calculate an offset of a buffered flash, not needed for 5709. */
4185 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4186 offset = ((offset / bp->flash_info->page_size) <<
4187 bp->flash_info->page_bits) +
4188 (offset % bp->flash_info->page_size);
4189 }
4190
4191 /* Need to clear DONE bit separately. */
4192 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4193
4194 /* Address of the NVRAM to read from. */
4195 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4196
4197 /* Issue a read command. */
4198 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4199
4200 /* Wait for completion. */
4201 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4202 u32 val;
4203
4204 udelay(5);
4205
4206 val = REG_RD(bp, BNX2_NVM_COMMAND);
4207 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 4208 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4209 memcpy(ret_val, &v, 4);
b6016b76
MC		 4210 break;
4211 }
4212 }
4213 if (j >= NVRAM_TIMEOUT_COUNT)
4214 return -EBUSY;
4215
4216 return 0;
4217}
4218
4219
4220static int
4221bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4222{
b491edd5
AV		 4223 u32 cmd;
4224 __be32 val32;
b6016b76
MC		 4225 int j;
4226
4227 /* Build the command word. */
4228 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4229
e30372c9
MC		 4230 /* Calculate an offset of a buffered flash, not needed for 5709. */
4231 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4232 offset = ((offset / bp->flash_info->page_size) <<
4233 bp->flash_info->page_bits) +
4234 (offset % bp->flash_info->page_size);
4235 }
4236
4237 /* Need to clear DONE bit separately. */
4238 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4239
4240 memcpy(&val32, val, 4);
b6016b76
MC		 4241
4242 /* Write the data. */
b491edd5 4243 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 4244
4245 /* Address of the NVRAM to write to. */
4246 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4247
4248 /* Issue the write command. */
4249 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4250
4251 /* Wait for completion. */
4252 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4253 udelay(5);
4254
4255 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4256 break;
4257 }
4258 if (j >= NVRAM_TIMEOUT_COUNT)
4259 return -EBUSY;
4260
4261 return 0;
4262}
4263
4264static int
4265bnx2_init_nvram(struct bnx2 *bp)
4266{
4267 u32 val;
e30372c9 4268 int j, entry_count, rc = 0;
0ced9d01 4269 const struct flash_spec *flash;
b6016b76 4270
e30372c9
MC		 4271 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4272 bp->flash_info = &flash_5709;
4273 goto get_flash_size;
4274 }
4275
b6016b76
MC		 4276 /* Determine the selected interface. */
4277 val = REG_RD(bp, BNX2_NVM_CFG1);
4278
ff8ac609 4279 entry_count = ARRAY_SIZE(flash_table);
b6016b76 4280
b6016b76
MC		 4281 if (val & 0x40000000) {
4282
4283 /* Flash interface has been reconfigured */
4284 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 4285 j++, flash++) {
4286 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4287 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 4288 bp->flash_info = flash;
4289 break;
4290 }
4291 }
4292 }
4293 else {
37137709 4294 u32 mask;
b6016b76
MC		 4295 /* Not yet been reconfigured */
4296
37137709
MC		 4297 if (val & (1 << 23))
4298 mask = FLASH_BACKUP_STRAP_MASK;
4299 else
4300 mask = FLASH_STRAP_MASK;
4301
b6016b76
MC		 4302 for (j = 0, flash = &flash_table[0]; j < entry_count;
4303 j++, flash++) {
4304
37137709 4305 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 4306 bp->flash_info = flash;
4307
4308 /* Request access to the flash interface. */
4309 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4310 return rc;
4311
4312 /* Enable access to flash interface */
4313 bnx2_enable_nvram_access(bp);
4314
4315 /* Reconfigure the flash interface */
4316 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4317 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4318 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4319 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4320
4321 /* Disable access to flash interface */
4322 bnx2_disable_nvram_access(bp);
4323 bnx2_release_nvram_lock(bp);
4324
4325 break;
4326 }
4327 }
4328 } /* if (val & 0x40000000) */
4329
4330 if (j == entry_count) {
4331 bp->flash_info = NULL;
3a9c6a49 4332 pr_alert("Unknown flash/EEPROM type\n");
1122db71 4333 return -ENODEV;
b6016b76
MC		 4334 }
4335
e30372c9 4336get_flash_size:
2726d6e1 4337 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 4338 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4339 if (val)
4340 bp->flash_size = val;
4341 else
4342 bp->flash_size = bp->flash_info->total_size;
4343
b6016b76
MC		 4344 return rc;
4345}
4346
4347static int
4348bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4349 int buf_size)
4350{
4351 int rc = 0;
4352 u32 cmd_flags, offset32, len32, extra;
4353
4354 if (buf_size == 0)
4355 return 0;
4356
4357 /* Request access to the flash interface. */
4358 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4359 return rc;
4360
4361 /* Enable access to flash interface */
4362 bnx2_enable_nvram_access(bp);
4363
4364 len32 = buf_size;
4365 offset32 = offset;
4366 extra = 0;
4367
4368 cmd_flags = 0;
4369
4370 if (offset32 & 3) {
4371 u8 buf[4];
4372 u32 pre_len;
4373
4374 offset32 &= ~3;
4375 pre_len = 4 - (offset & 3);
4376
4377 if (pre_len >= len32) {
4378 pre_len = len32;
4379 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4380 BNX2_NVM_COMMAND_LAST;
4381 }
4382 else {
4383 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4384 }
4385
4386 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4387
4388 if (rc)
4389 return rc;
4390
4391 memcpy(ret_buf, buf + (offset & 3), pre_len);
4392
4393 offset32 += 4;
4394 ret_buf += pre_len;
4395 len32 -= pre_len;
4396 }
4397 if (len32 & 3) {
4398 extra = 4 - (len32 & 3);
4399 len32 = (len32 + 4) & ~3;
4400 }
4401
4402 if (len32 == 4) {
4403 u8 buf[4];
4404
4405 if (cmd_flags)
4406 cmd_flags = BNX2_NVM_COMMAND_LAST;
4407 else
4408 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4409 BNX2_NVM_COMMAND_LAST;
4410
4411 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4412
4413 memcpy(ret_buf, buf, 4 - extra);
4414 }
4415 else if (len32 > 0) {
4416 u8 buf[4];
4417
4418 /* Read the first word. */
4419 if (cmd_flags)
4420 cmd_flags = 0;
4421 else
4422 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4423
4424 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4425
4426 /* Advance to the next dword. */
4427 offset32 += 4;
4428 ret_buf += 4;
4429 len32 -= 4;
4430
4431 while (len32 > 4 && rc == 0) {
4432 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4433
4434 /* Advance to the next dword. */
4435 offset32 += 4;
4436 ret_buf += 4;
4437 len32 -= 4;
4438 }
4439
4440 if (rc)
4441 return rc;
4442
4443 cmd_flags = BNX2_NVM_COMMAND_LAST;
4444 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4445
4446 memcpy(ret_buf, buf, 4 - extra);
4447 }
4448
4449 /* Disable access to flash interface */
4450 bnx2_disable_nvram_access(bp);
4451
4452 bnx2_release_nvram_lock(bp);
4453
4454 return rc;
4455}
4456
4457static int
4458bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4459 int buf_size)
4460{
4461 u32 written, offset32, len32;
e6be763f 4462 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4463 int rc = 0;
4464 int align_start, align_end;
4465
4466 buf = data_buf;
4467 offset32 = offset;
4468 len32 = buf_size;
4469 align_start = align_end = 0;
4470
4471 if ((align_start = (offset32 & 3))) {
4472 offset32 &= ~3;
c873879c
MC		 4473 len32 += align_start;
4474 if (len32 < 4)
4475 len32 = 4;
b6016b76
MC		 4476 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4477 return rc;
4478 }
4479
4480 if (len32 & 3) {
c873879c
MC		 4481 align_end = 4 - (len32 & 3);
4482 len32 += align_end;
4483 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4484 return rc;
b6016b76
MC		 4485 }
4486
4487 if (align_start || align_end) {
e6be763f
MC		 4488 align_buf = kmalloc(len32, GFP_KERNEL);
4489 if (align_buf == NULL)
b6016b76
MC		 4490 return -ENOMEM;
4491 if (align_start) {
e6be763f 4492 memcpy(align_buf, start, 4);
b6016b76
MC		 4493 }
4494 if (align_end) {
e6be763f 4495 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4496 }
e6be763f
MC		 4497 memcpy(align_buf + align_start, data_buf, buf_size);
4498 buf = align_buf;
b6016b76
MC		 4499 }
4500
e30372c9 4501 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4502 flash_buffer = kmalloc(264, GFP_KERNEL);
4503 if (flash_buffer == NULL) {
4504 rc = -ENOMEM;
4505 goto nvram_write_end;
4506 }
4507 }
4508
b6016b76
MC		 4509 written = 0;
4510 while ((written < len32) && (rc == 0)) {
4511 u32 page_start, page_end, data_start, data_end;
4512 u32 addr, cmd_flags;
4513 int i;
b6016b76
MC		 4514
4515 /* Find the page_start addr */
4516 page_start = offset32 + written;
4517 page_start -= (page_start % bp->flash_info->page_size);
4518 /* Find the page_end addr */
4519 page_end = page_start + bp->flash_info->page_size;
4520 /* Find the data_start addr */
4521 data_start = (written == 0) ? offset32 : page_start;
4522 /* Find the data_end addr */
6aa20a22 4523 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4524 (offset32 + len32) : page_end;
4525
4526 /* Request access to the flash interface. */
4527 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4528 goto nvram_write_end;
4529
4530 /* Enable access to flash interface */
4531 bnx2_enable_nvram_access(bp);
4532
4533 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4534 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4535 int j;
4536
4537 /* Read the whole page into the buffer
4538 * (non-buffer flash only) */
4539 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4540 if (j == (bp->flash_info->page_size - 4)) {
4541 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4542 }
4543 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4544 page_start + j,
4545 &flash_buffer[j],
b6016b76
MC		 4546 cmd_flags);
4547
4548 if (rc)
4549 goto nvram_write_end;
4550
4551 cmd_flags = 0;
4552 }
4553 }
4554
4555 /* Enable writes to flash interface (unlock write-protect) */
4556 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4557 goto nvram_write_end;
4558
b6016b76
MC		 4559 /* Loop to write back the buffer data from page_start to
4560 * data_start */
4561 i = 0;
e30372c9 4562 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4563 /* Erase the page */
4564 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4565 goto nvram_write_end;
4566
4567 /* Re-enable the write again for the actual write */
4568 bnx2_enable_nvram_write(bp);
4569
b6016b76
MC		 4570 for (addr = page_start; addr < data_start;
4571 addr += 4, i += 4) {
6aa20a22 4572
b6016b76
MC		 4573 rc = bnx2_nvram_write_dword(bp, addr,
4574 &flash_buffer[i], cmd_flags);
4575
4576 if (rc != 0)
4577 goto nvram_write_end;
4578
4579 cmd_flags = 0;
4580 }
4581 }
4582
4583 /* Loop to write the new data from data_start to data_end */
bae25761 4584 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4585 if ((addr == page_end - 4) ||
e30372c9 4586 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4587 (addr == data_end - 4))) {
4588
4589 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4590 }
4591 rc = bnx2_nvram_write_dword(bp, addr, buf,
4592 cmd_flags);
4593
4594 if (rc != 0)
4595 goto nvram_write_end;
4596
4597 cmd_flags = 0;
4598 buf += 4;
4599 }
4600
4601 /* Loop to write back the buffer data from data_end
4602 * to page_end */
e30372c9 4603 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4604 for (addr = data_end; addr < page_end;
4605 addr += 4, i += 4) {
6aa20a22 4606
b6016b76
MC		 4607 if (addr == page_end-4) {
4608 cmd_flags = BNX2_NVM_COMMAND_LAST;
4609 }
4610 rc = bnx2_nvram_write_dword(bp, addr,
4611 &flash_buffer[i], cmd_flags);
4612
4613 if (rc != 0)
4614 goto nvram_write_end;
4615
4616 cmd_flags = 0;
4617 }
4618 }
4619
4620 /* Disable writes to flash interface (lock write-protect) */
4621 bnx2_disable_nvram_write(bp);
4622
4623 /* Disable access to flash interface */
4624 bnx2_disable_nvram_access(bp);
4625 bnx2_release_nvram_lock(bp);
4626
4627 /* Increment written */
4628 written += data_end - data_start;
4629 }
4630
4631nvram_write_end:
e6be763f
MC		 4632 kfree(flash_buffer);
4633 kfree(align_buf);
b6016b76
MC		 4634 return rc;
4635}
4636
0d8a6571 4637static void
7c62e83b 4638bnx2_init_fw_cap(struct bnx2 *bp)
0d8a6571 4639{
7c62e83b 4640 u32 val, sig = 0;
0d8a6571 4641
583c28e5 4642 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
7c62e83b
MC		 4643 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4644
4645 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4646 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
0d8a6571 4647
2726d6e1 4648 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4649 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4650 return;
4651
7c62e83b
MC		 4652 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4653 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4654 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4655 }
4656
4657 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4658 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4659 u32 link;
4660
583c28e5 4661 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4662
7c62e83b
MC		 4663 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4664 if (link & BNX2_LINK_STATUS_SERDES_LINK)
0d8a6571
MC		 4665 bp->phy_port = PORT_FIBRE;
4666 else
4667 bp->phy_port = PORT_TP;
489310a4 4668
7c62e83b
MC		 4669 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4670 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
0d8a6571 4671 }
7c62e83b
MC		 4672
4673 if (netif_running(bp->dev) && sig)
4674 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
0d8a6571
MC		 4675}
4676
b4b36042
MC		 4677static void
4678bnx2_setup_msix_tbl(struct bnx2 *bp)
4679{
4680 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4681
4682 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4683 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4684}
4685
b6016b76
MC		 4686static int
4687bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4688{
4689 u32 val;
4690 int i, rc = 0;
489310a4 4691 u8 old_port;
b6016b76
MC		 4692
4693 /* Wait for the current PCI transaction to complete before
4694 * issuing a reset. */
a5dac108
EW		 4695 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4696 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
4697 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4698 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4699 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4700 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4701 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4702 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4703 udelay(5);
4704 } else { /* 5709 */
4705 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4706 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4707 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4708 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4709
4710 for (i = 0; i < 100; i++) {
4711 msleep(1);
4712 val = REG_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4713 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4714 break;
4715 }
4716 }
b6016b76 4717
b090ae2b 4718 /* Wait for the firmware to tell us it is ok to issue a reset. */
a2f13890 4719 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
b090ae2b 4720
b6016b76
MC		 4721 /* Deposit a driver reset signature so the firmware knows that
4722 * this is a soft reset. */
2726d6e1
MC		 4723 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4724 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4725
b6016b76
MC		 4726 /* Do a dummy read to force the chip to complete all current transaction
4727 * before we issue a reset. */
4728 val = REG_RD(bp, BNX2_MISC_ID);
4729
234754d5
MC		 4730 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4731 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4732 REG_RD(bp, BNX2_MISC_COMMAND);
4733 udelay(5);
b6016b76 4734
234754d5
MC		 4735 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4736 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4737
be7ff1af 4738 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4739
234754d5
MC		 4740 } else {
4741 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4742 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4743 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4744
4745 /* Chip reset. */
4746 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4747
594a9dfa
MC		 4748 /* Reading back any register after chip reset will hang the
4749 * bus on 5706 A0 and A1. The msleep below provides plenty
4750 * of margin for write posting.
4751 */
234754d5 4752 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4753 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4754 msleep(20);
b6016b76 4755
234754d5
MC		 4756 /* Reset takes approximate 30 usec */
4757 for (i = 0; i < 10; i++) {
4758 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4759 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4760 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4761 break;
4762 udelay(10);
4763 }
4764
4765 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4766 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3a9c6a49 4767 pr_err("Chip reset did not complete\n");
234754d5
MC		 4768 return -EBUSY;
4769 }
b6016b76
MC		 4770 }
4771
4772 /* Make sure byte swapping is properly configured. */
4773 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4774 if (val != 0x01020304) {
3a9c6a49 4775 pr_err("Chip not in correct endian mode\n");
b6016b76
MC		 4776 return -ENODEV;
4777 }
4778
b6016b76 4779 /* Wait for the firmware to finish its initialization. */
a2f13890 4780 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
b090ae2b
MC		 4781 if (rc)
4782 return rc;
b6016b76 4783
0d8a6571 4784 spin_lock_bh(&bp->phy_lock);
489310a4 4785 old_port = bp->phy_port;
7c62e83b 4786 bnx2_init_fw_cap(bp);
583c28e5
MC		 4787 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4788 old_port != bp->phy_port)
0d8a6571
MC		 4789 bnx2_set_default_remote_link(bp);
4790 spin_unlock_bh(&bp->phy_lock);
4791
b6016b76
MC		 4792 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4793 /* Adjust the voltage regular to two steps lower. The default
4794 * of this register is 0x0000000e. */
4795 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4796
4797 /* Remove bad rbuf memory from the free pool. */
4798 rc = bnx2_alloc_bad_rbuf(bp);
4799 }
4800
c441b8d2 4801 if (bp->flags & BNX2_FLAG_USING_MSIX) {
b4b36042 4802 bnx2_setup_msix_tbl(bp);
c441b8d2
MC		 4803 /* Prevent MSIX table reads and write from timing out */
4804 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4805 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4806 }
b4b36042 4807
b6016b76
MC		 4808 return rc;
4809}
4810
4811static int
4812bnx2_init_chip(struct bnx2 *bp)
4813{
d8026d93 4814 u32 val, mtu;
b4b36042 4815 int rc, i;
b6016b76
MC		 4816
4817 /* Make sure the interrupt is not active. */
4818 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4819
4820 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4821 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4822#ifdef __BIG_ENDIAN
6aa20a22 4823 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4824#endif
6aa20a22 4825 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4826 DMA_READ_CHANS << 12 |
4827 DMA_WRITE_CHANS << 16;
4828
4829 val |= (0x2 << 20) | (1 << 11);
4830
f86e82fb 4831 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4832 val |= (1 << 23);
4833
4834 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4835 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4836 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4837
4838 REG_WR(bp, BNX2_DMA_CONFIG, val);
4839
4840 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4841 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4842 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4843 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4844 }
4845
f86e82fb 4846 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4847 u16 val16;
4848
4849 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4850 &val16);
4851 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4852 val16 & ~PCI_X_CMD_ERO);
4853 }
4854
4855 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4856 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4857 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4858 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4859
4860 /* Initialize context mapping and zero out the quick contexts. The
4861 * context block must have already been enabled. */
641bdcd5
MC		 4862 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4863 rc = bnx2_init_5709_context(bp);
4864 if (rc)
4865 return rc;
4866 } else
59b47d8a 4867 bnx2_init_context(bp);
b6016b76 4868
fba9fe91
MC		 4869 if ((rc = bnx2_init_cpus(bp)) != 0)
4870 return rc;
4871
b6016b76
MC		 4872 bnx2_init_nvram(bp);
4873
5fcaed01 4874 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 4875
4876 val = REG_RD(bp, BNX2_MQ_CONFIG);
4877 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4878 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4edd473f
MC		 4879 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4880 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4881 if (CHIP_REV(bp) == CHIP_REV_Ax)
4882 val |= BNX2_MQ_CONFIG_HALT_DIS;
4883 }
68c9f75a 4884
b6016b76
MC		 4885 REG_WR(bp, BNX2_MQ_CONFIG, val);
4886
4887 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4888 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4889 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4890
4891 val = (BCM_PAGE_BITS - 8) << 24;
4892 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4893
4894 /* Configure page size. */
4895 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4896 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4897 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4898 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4899
4900 val = bp->mac_addr[0] +
4901 (bp->mac_addr[1] << 8) +
4902 (bp->mac_addr[2] << 16) +
4903 bp->mac_addr[3] +
4904 (bp->mac_addr[4] << 8) +
4905 (bp->mac_addr[5] << 16);
4906 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4907
4908 /* Program the MTU. Also include 4 bytes for CRC32. */
d8026d93
MC		 4909 mtu = bp->dev->mtu;
4910 val = mtu + ETH_HLEN + ETH_FCS_LEN;
b6016b76
MC		 4911 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4912 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4913 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4914
d8026d93
MC		 4915 if (mtu < 1500)
4916 mtu = 1500;
4917
4918 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4919 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4920 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4921
155d5561 4922 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
b4b36042
MC		 4923 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4924 bp->bnx2_napi[i].last_status_idx = 0;
4925
efba0180
MC		 4926 bp->idle_chk_status_idx = 0xffff;
4927
b6016b76
MC		 4928 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4929
4930 /* Set up how to generate a link change interrupt. */
4931 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4932
4933 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4934 (u64) bp->status_blk_mapping & 0xffffffff);
4935 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4936
4937 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4938 (u64) bp->stats_blk_mapping & 0xffffffff);
4939 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4940 (u64) bp->stats_blk_mapping >> 32);
4941
6aa20a22 4942 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4943 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4944
4945 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4946 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4947
4948 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4949 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4950
4951 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4952
4953 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4954
4955 REG_WR(bp, BNX2_HC_COM_TICKS,
4956 (bp->com_ticks_int << 16) | bp->com_ticks);
4957
4958 REG_WR(bp, BNX2_HC_CMD_TICKS,
4959 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4960
61d9e3fa 4961 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
02537b06
MC		 4962 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4963 else
7ea6920e 4964 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4965 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4966
4967 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4968 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4969 else {
8e6a72c4
MC		 4970 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4971 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4972 }
4973
efde73a3 4974 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4975 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4976 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4977
5e9ad9e1
MC		 4978 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4979 }
4980
4981 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
cf7474a6 4982 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5e9ad9e1
MC		 4983
4984 REG_WR(bp, BNX2_HC_CONFIG, val);
4985
22fa159d
MC		 4986 if (bp->rx_ticks < 25)
4987 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
4988 else
4989 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
4990
5e9ad9e1
MC		 4991 for (i = 1; i < bp->irq_nvecs; i++) {
4992 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4993 BNX2_HC_SB_CONFIG_1;
4994
6f743ca0 4995 REG_WR(bp, base,
c76c0475 4996 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5e9ad9e1 4997 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
c76c0475
MC		 4998 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4999
6f743ca0 5000 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 5001 (bp->tx_quick_cons_trip_int << 16) |
5002 bp->tx_quick_cons_trip);
5003
6f743ca0 5004 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 5005 (bp->tx_ticks_int << 16) | bp->tx_ticks);
5006
5e9ad9e1
MC		 5007 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5008 (bp->rx_quick_cons_trip_int << 16) |
5009 bp->rx_quick_cons_trip);
8e6a72c4 5010
5e9ad9e1
MC		 5011 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
5012 (bp->rx_ticks_int << 16) | bp->rx_ticks);
5013 }
8e6a72c4 5014
b6016b76
MC		 5015 /* Clear internal stats counters. */
5016 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
5017
da3e4fbe 5018 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 5019
5020 /* Initialize the receive filter. */
5021 bnx2_set_rx_mode(bp->dev);
5022
0aa38df7
MC		 5023 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5024 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5025 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5026 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5027 }
b090ae2b 5028 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
a2f13890 5029 1, 0);
b6016b76 5030
df149d70 5031 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 5032 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5033
5034 udelay(20);
5035
bf5295bb
MC		 5036 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5037
b090ae2b 5038 return rc;
b6016b76
MC		 5039}
5040
c76c0475
MC		 5041static void
5042bnx2_clear_ring_states(struct bnx2 *bp)
5043{
5044 struct bnx2_napi *bnapi;
35e9010b 5045 struct bnx2_tx_ring_info *txr;
bb4f98ab 5046 struct bnx2_rx_ring_info *rxr;
c76c0475
MC		 5047 int i;
5048
5049 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5050 bnapi = &bp->bnx2_napi[i];
35e9010b 5051 txr = &bnapi->tx_ring;
bb4f98ab 5052 rxr = &bnapi->rx_ring;
c76c0475 5053
35e9010b
MC		 5054 txr->tx_cons = 0;
5055 txr->hw_tx_cons = 0;
bb4f98ab
MC		 5056 rxr->rx_prod_bseq = 0;
5057 rxr->rx_prod = 0;
5058 rxr->rx_cons = 0;
5059 rxr->rx_pg_prod = 0;
5060 rxr->rx_pg_cons = 0;
c76c0475
MC		 5061 }
5062}
5063
59b47d8a 5064static void
35e9010b 5065bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
59b47d8a
MC		 5066{
5067 u32 val, offset0, offset1, offset2, offset3;
62a8313c 5068 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 5069
5070 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5071 offset0 = BNX2_L2CTX_TYPE_XI;
5072 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5073 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5074 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5075 } else {
5076 offset0 = BNX2_L2CTX_TYPE;
5077 offset1 = BNX2_L2CTX_CMD_TYPE;
5078 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5079 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5080 }
5081 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 5082 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 5083
5084 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 5085 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a 5086
35e9010b 5087 val = (u64) txr->tx_desc_mapping >> 32;
62a8313c 5088 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a 5089
35e9010b 5090 val = (u64) txr->tx_desc_mapping & 0xffffffff;
62a8313c 5091 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 5092}
b6016b76
MC		 5093
5094static void
35e9010b 5095bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
b6016b76
MC		 5096{
5097 struct tx_bd *txbd;
c76c0475
MC		 5098 u32 cid = TX_CID;
5099 struct bnx2_napi *bnapi;
35e9010b 5100 struct bnx2_tx_ring_info *txr;
c76c0475 5101
35e9010b
MC		 5102 bnapi = &bp->bnx2_napi[ring_num];
5103 txr = &bnapi->tx_ring;
5104
5105 if (ring_num == 0)
5106 cid = TX_CID;
5107 else
5108 cid = TX_TSS_CID + ring_num - 1;
b6016b76 5109
2f8af120
MC		 5110 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5111
35e9010b 5112 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 5113
35e9010b
MC		 5114 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5115 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
b6016b76 5116
35e9010b
MC		 5117 txr->tx_prod = 0;
5118 txr->tx_prod_bseq = 0;
6aa20a22 5119
35e9010b
MC		 5120 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5121 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 5122
35e9010b 5123 bnx2_init_tx_context(bp, cid, txr);
b6016b76
MC		 5124}
5125
5126static void
5d5d0015
MC		 5127bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5128 int num_rings)
b6016b76 5129{
b6016b76 5130 int i;
5d5d0015 5131 struct rx_bd *rxbd;
6aa20a22 5132
5d5d0015 5133 for (i = 0; i < num_rings; i++) {
13daffa2 5134 int j;
b6016b76 5135
5d5d0015 5136 rxbd = &rx_ring[i][0];
13daffa2 5137 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 5138 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 5139 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5140 }
5d5d0015 5141 if (i == (num_rings - 1))
13daffa2
MC		 5142 j = 0;
5143 else
5144 j = i + 1;
5d5d0015
MC		 5145 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5146 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 5147 }
5d5d0015
MC		 5148}
5149
5150static void
bb4f98ab 5151bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5d5d0015
MC		 5152{
5153 int i;
5154 u16 prod, ring_prod;
bb4f98ab
MC		 5155 u32 cid, rx_cid_addr, val;
5156 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5157 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5158
5159 if (ring_num == 0)
5160 cid = RX_CID;
5161 else
5162 cid = RX_RSS_CID + ring_num - 1;
5163
5164 rx_cid_addr = GET_CID_ADDR(cid);
5d5d0015 5165
bb4f98ab 5166 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5d5d0015
MC		 5167 bp->rx_buf_use_size, bp->rx_max_ring);
5168
bb4f98ab 5169 bnx2_init_rx_context(bp, cid);
83e3fc89
MC		 5170
5171 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5172 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5173 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5174 }
5175
62a8313c 5176 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246 5177 if (bp->rx_pg_ring_size) {
bb4f98ab
MC		 5178 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5179 rxr->rx_pg_desc_mapping,
47bf4246
MC		 5180 PAGE_SIZE, bp->rx_max_pg_ring);
5181 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 5182 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5183 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5e9ad9e1 5184 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
47bf4246 5185
bb4f98ab 5186 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
62a8313c 5187 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246 5188
bb4f98ab 5189 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 5190 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 5191
5192 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5193 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5194 }
b6016b76 5195
bb4f98ab 5196 val = (u64) rxr->rx_desc_mapping[0] >> 32;
62a8313c 5197 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 5198
bb4f98ab 5199 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
62a8313c 5200 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 5201
bb4f98ab 5202 ring_prod = prod = rxr->rx_pg_prod;
47bf4246 5203 for (i = 0; i < bp->rx_pg_ring_size; i++) {
a2df00aa 5204 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5205 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5206 ring_num, i, bp->rx_pg_ring_size);
47bf4246 5207 break;
b929e53c 5208 }
47bf4246
MC		 5209 prod = NEXT_RX_BD(prod);
5210 ring_prod = RX_PG_RING_IDX(prod);
5211 }
bb4f98ab 5212 rxr->rx_pg_prod = prod;
47bf4246 5213
bb4f98ab 5214 ring_prod = prod = rxr->rx_prod;
236b6394 5215 for (i = 0; i < bp->rx_ring_size; i++) {
a2df00aa 5216 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5217 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5218 ring_num, i, bp->rx_ring_size);
b6016b76 5219 break;
b929e53c 5220 }
b6016b76
MC		 5221 prod = NEXT_RX_BD(prod);
5222 ring_prod = RX_RING_IDX(prod);
5223 }
bb4f98ab 5224 rxr->rx_prod = prod;
b6016b76 5225
bb4f98ab
MC		 5226 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5227 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5228 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
b6016b76 5229
bb4f98ab
MC		 5230 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5231 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5232
5233 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 5234}
5235
35e9010b
MC		 5236static void
5237bnx2_init_all_rings(struct bnx2 *bp)
5238{
5239 int i;
5e9ad9e1 5240 u32 val;
35e9010b
MC		 5241
5242 bnx2_clear_ring_states(bp);
5243
5244 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5245 for (i = 0; i < bp->num_tx_rings; i++)
5246 bnx2_init_tx_ring(bp, i);
5247
5248 if (bp->num_tx_rings > 1)
5249 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5250 (TX_TSS_CID << 7));
5251
5e9ad9e1
MC		 5252 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5253 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5254
bb4f98ab
MC		 5255 for (i = 0; i < bp->num_rx_rings; i++)
5256 bnx2_init_rx_ring(bp, i);
5e9ad9e1
MC		 5257
5258 if (bp->num_rx_rings > 1) {
22fa159d 5259 u32 tbl_32 = 0;
5e9ad9e1
MC		 5260
5261 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
22fa159d
MC		 5262 int shift = (i % 8) << 2;
5263
5264 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
5265 if ((i % 8) == 7) {
5266 REG_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5267 REG_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
5268 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
5269 BNX2_RLUP_RSS_COMMAND_WRITE |
5270 BNX2_RLUP_RSS_COMMAND_HASH_MASK);
5271 tbl_32 = 0;
5272 }
5e9ad9e1
MC		 5273 }
5274
5275 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5276 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5277
5278 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5279
5280 }
35e9010b
MC		 5281}
5282
5d5d0015 5283static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 5284{
5d5d0015 5285 u32 max, num_rings = 1;
13daffa2 5286
5d5d0015
MC		 5287 while (ring_size > MAX_RX_DESC_CNT) {
5288 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 5289 num_rings++;
5290 }
5291 /* round to next power of 2 */
5d5d0015 5292 max = max_size;
13daffa2
MC		 5293 while ((max & num_rings) == 0)
5294 max >>= 1;
5295
5296 if (num_rings != max)
5297 max <<= 1;
5298
5d5d0015
MC		 5299 return max;
5300}
5301
5302static void
5303bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5304{
84eaa187 5305 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 5306
5307 /* 8 for CRC and VLAN */
d89cb6af 5308 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 5309
84eaa187
MC		 5310 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5311 sizeof(struct skb_shared_info);
5312
601d3d18 5313 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 5314 bp->rx_pg_ring_size = 0;
5315 bp->rx_max_pg_ring = 0;
5316 bp->rx_max_pg_ring_idx = 0;
f86e82fb 5317 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 5318 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5319
5320 jumbo_size = size * pages;
5321 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5322 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5323
5324 bp->rx_pg_ring_size = jumbo_size;
5325 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5326 MAX_RX_PG_RINGS);
5327 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
601d3d18 5328 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 5329 bp->rx_copy_thresh = 0;
5330 }
5d5d0015
MC		 5331
5332 bp->rx_buf_use_size = rx_size;
5333 /* hw alignment */
5334 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
d89cb6af 5335 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015
MC		 5336 bp->rx_ring_size = size;
5337 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 5338 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5339}
5340
b6016b76
MC		 5341static void
5342bnx2_free_tx_skbs(struct bnx2 *bp)
5343{
5344 int i;
5345
35e9010b
MC		 5346 for (i = 0; i < bp->num_tx_rings; i++) {
5347 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5348 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5349 int j;
b6016b76 5350
35e9010b 5351 if (txr->tx_buf_ring == NULL)
b6016b76 5352 continue;
b6016b76 5353
35e9010b 5354 for (j = 0; j < TX_DESC_CNT; ) {
3d16af86 5355 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
35e9010b 5356 struct sk_buff *skb = tx_buf->skb;
e95524a7 5357 int k, last;
35e9010b
MC		 5358
5359 if (skb == NULL) {
5360 j++;
5361 continue;
5362 }
5363
36227e88 5364 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5365 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5366 skb_headlen(skb),
5367 PCI_DMA_TODEVICE);
b6016b76 5368
35e9010b 5369 tx_buf->skb = NULL;
b6016b76 5370
e95524a7
AD		 5371 last = tx_buf->nr_frags;
5372 j++;
5373 for (k = 0; k < last; k++, j++) {
5374 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
36227e88 5375 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 5376 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5377 skb_shinfo(skb)->frags[k].size,
5378 PCI_DMA_TODEVICE);
5379 }
35e9010b 5380 dev_kfree_skb(skb);
b6016b76 5381 }
b6016b76 5382 }
b6016b76
MC		 5383}
5384
5385static void
5386bnx2_free_rx_skbs(struct bnx2 *bp)
5387{
5388 int i;
5389
bb4f98ab
MC		 5390 for (i = 0; i < bp->num_rx_rings; i++) {
5391 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5392 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5393 int j;
b6016b76 5394
bb4f98ab
MC		 5395 if (rxr->rx_buf_ring == NULL)
5396 return;
b6016b76 5397
bb4f98ab
MC		 5398 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5399 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5400 struct sk_buff *skb = rx_buf->skb;
b6016b76 5401
bb4f98ab
MC		 5402 if (skb == NULL)
5403 continue;
b6016b76 5404
36227e88 5405 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5406 dma_unmap_addr(rx_buf, mapping),
bb4f98ab
MC		 5407 bp->rx_buf_use_size,
5408 PCI_DMA_FROMDEVICE);
b6016b76 5409
bb4f98ab
MC		 5410 rx_buf->skb = NULL;
5411
5412 dev_kfree_skb(skb);
5413 }
5414 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5415 bnx2_free_rx_page(bp, rxr, j);
b6016b76
MC		 5416 }
5417}
5418
5419static void
5420bnx2_free_skbs(struct bnx2 *bp)
5421{
5422 bnx2_free_tx_skbs(bp);
5423 bnx2_free_rx_skbs(bp);
5424}
5425
5426static int
5427bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5428{
5429 int rc;
5430
5431 rc = bnx2_reset_chip(bp, reset_code);
5432 bnx2_free_skbs(bp);
5433 if (rc)
5434 return rc;
5435
fba9fe91
MC		 5436 if ((rc = bnx2_init_chip(bp)) != 0)
5437 return rc;
5438
35e9010b 5439 bnx2_init_all_rings(bp);
b6016b76
MC		 5440 return 0;
5441}
5442
5443static int
9a120bc5 5444bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 5445{
5446 int rc;
5447
5448 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5449 return rc;
5450
80be4434 5451 spin_lock_bh(&bp->phy_lock);
9a120bc5 5452 bnx2_init_phy(bp, reset_phy);
b6016b76 5453 bnx2_set_link(bp);
543a827d
MC		 5454 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5455 bnx2_remote_phy_event(bp);
0d8a6571 5456 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5457 return 0;
5458}
5459
74bf4ba3
MC		 5460static int
5461bnx2_shutdown_chip(struct bnx2 *bp)
5462{
5463 u32 reset_code;
5464
5465 if (bp->flags & BNX2_FLAG_NO_WOL)
5466 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5467 else if (bp->wol)
5468 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5469 else
5470 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5471
5472 return bnx2_reset_chip(bp, reset_code);
5473}
5474
b6016b76
MC		 5475static int
5476bnx2_test_registers(struct bnx2 *bp)
5477{
5478 int ret;
5bae30c9 5479 int i, is_5709;
f71e1309 5480 static const struct {
b6016b76
MC		 5481 u16 offset;
5482 u16 flags;
5bae30c9 5483#define BNX2_FL_NOT_5709 1
b6016b76
MC		 5484 u32 rw_mask;
5485 u32 ro_mask;
5486 } reg_tbl[] = {
5487 { 0x006c, 0, 0x00000000, 0x0000003f },
5488 { 0x0090, 0, 0xffffffff, 0x00000000 },
5489 { 0x0094, 0, 0x00000000, 0x00000000 },
5490
5bae30c9
MC		 5491 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5492 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5493 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5494 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5495 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5496 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5497 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5498 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5499 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5500
5501 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5502 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5503 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5504 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5505 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5506 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5507
5508 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5509 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5510 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 5511
5512 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 5513 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 5514
5515 { 0x1408, 0, 0x01c00800, 0x00000000 },
5516 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5517 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 5518 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 5519 { 0x14b0, 0, 0x00000002, 0x00000001 },
5520 { 0x14b8, 0, 0x00000000, 0x00000000 },
5521 { 0x14c0, 0, 0x00000000, 0x00000009 },
5522 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5523 { 0x14cc, 0, 0x00000000, 0x00000001 },
5524 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 5525
5526 { 0x1800, 0, 0x00000000, 0x00000001 },
5527 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 5528
5529 { 0x2800, 0, 0x00000000, 0x00000001 },
5530 { 0x2804, 0, 0x00000000, 0x00003f01 },
5531 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5532 { 0x2810, 0, 0xffff0000, 0x00000000 },
5533 { 0x2814, 0, 0xffff0000, 0x00000000 },
5534 { 0x2818, 0, 0xffff0000, 0x00000000 },
5535 { 0x281c, 0, 0xffff0000, 0x00000000 },
5536 { 0x2834, 0, 0xffffffff, 0x00000000 },
5537 { 0x2840, 0, 0x00000000, 0xffffffff },
5538 { 0x2844, 0, 0x00000000, 0xffffffff },
5539 { 0x2848, 0, 0xffffffff, 0x00000000 },
5540 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5541
5542 { 0x2c00, 0, 0x00000000, 0x00000011 },
5543 { 0x2c04, 0, 0x00000000, 0x00030007 },
5544
b6016b76
MC		 5545 { 0x3c00, 0, 0x00000000, 0x00000001 },
5546 { 0x3c04, 0, 0x00000000, 0x00070000 },
5547 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5548 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5549 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5550 { 0x3c14, 0, 0x00000000, 0xffffffff },
5551 { 0x3c18, 0, 0x00000000, 0xffffffff },
5552 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5553 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 5554
5555 { 0x5004, 0, 0x00000000, 0x0000007f },
5556 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 5557
b6016b76
MC		 5558 { 0x5c00, 0, 0x00000000, 0x00000001 },
5559 { 0x5c04, 0, 0x00000000, 0x0003000f },
5560 { 0x5c08, 0, 0x00000003, 0x00000000 },
5561 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5562 { 0x5c10, 0, 0x00000000, 0xffffffff },
5563 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5564 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5565 { 0x5c88, 0, 0x00000000, 0x00077373 },
5566 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5567
5568 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5569 { 0x680c, 0, 0xffffffff, 0x00000000 },
5570 { 0x6810, 0, 0xffffffff, 0x00000000 },
5571 { 0x6814, 0, 0xffffffff, 0x00000000 },
5572 { 0x6818, 0, 0xffffffff, 0x00000000 },
5573 { 0x681c, 0, 0xffffffff, 0x00000000 },
5574 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5575 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5576 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5577 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5578 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5579 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5580 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5581 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5582 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5583 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5584 { 0x684c, 0, 0xffffffff, 0x00000000 },
5585 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5586 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5587 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5588 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5589 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5590 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5591
5592 { 0xffff, 0, 0x00000000, 0x00000000 },
5593 };
5594
5595 ret = 0;
5bae30c9
MC		 5596 is_5709 = 0;
5597 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5598 is_5709 = 1;
5599
b6016b76
MC		 5600 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5601 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5602 u16 flags = reg_tbl[i].flags;
5603
5604 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5605 continue;
b6016b76
MC		 5606
5607 offset = (u32) reg_tbl[i].offset;
5608 rw_mask = reg_tbl[i].rw_mask;
5609 ro_mask = reg_tbl[i].ro_mask;
5610
14ab9b86 5611 save_val = readl(bp->regview + offset);
b6016b76 5612
14ab9b86 5613 writel(0, bp->regview + offset);
b6016b76 5614
14ab9b86 5615 val = readl(bp->regview + offset);
b6016b76
MC		 5616 if ((val & rw_mask) != 0) {
5617 goto reg_test_err;
5618 }
5619
5620 if ((val & ro_mask) != (save_val & ro_mask)) {
5621 goto reg_test_err;
5622 }
5623
14ab9b86 5624 writel(0xffffffff, bp->regview + offset);
b6016b76 5625
14ab9b86 5626 val = readl(bp->regview + offset);
b6016b76
MC		 5627 if ((val & rw_mask) != rw_mask) {
5628 goto reg_test_err;
5629 }
5630
5631 if ((val & ro_mask) != (save_val & ro_mask)) {
5632 goto reg_test_err;
5633 }
5634
14ab9b86 5635 writel(save_val, bp->regview + offset);
b6016b76
MC		 5636 continue;
5637
5638reg_test_err:
14ab9b86 5639 writel(save_val, bp->regview + offset);
b6016b76
MC		 5640 ret = -ENODEV;
5641 break;
5642 }
5643 return ret;
5644}
5645
5646static int
5647bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5648{
f71e1309 5649 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5650 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5651 int i;
5652
5653 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5654 u32 offset;
5655
5656 for (offset = 0; offset < size; offset += 4) {
5657
2726d6e1 5658 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5659
2726d6e1 5660 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5661 test_pattern[i]) {
5662 return -ENODEV;
5663 }
5664 }
5665 }
5666 return 0;
5667}
5668
5669static int
5670bnx2_test_memory(struct bnx2 *bp)
5671{
5672 int ret = 0;
5673 int i;
5bae30c9 5674 static struct mem_entry {
b6016b76
MC		 5675 u32 offset;
5676 u32 len;
5bae30c9 5677 } mem_tbl_5706[] = {
b6016b76 5678 { 0x60000, 0x4000 },
5b0c76ad 5679 { 0xa0000, 0x3000 },
b6016b76
MC		 5680 { 0xe0000, 0x4000 },
5681 { 0x120000, 0x4000 },
5682 { 0x1a0000, 0x4000 },
5683 { 0x160000, 0x4000 },
5684 { 0xffffffff, 0 },
5bae30c9
MC		 5685 },
5686 mem_tbl_5709[] = {
5687 { 0x60000, 0x4000 },
5688 { 0xa0000, 0x3000 },
5689 { 0xe0000, 0x4000 },
5690 { 0x120000, 0x4000 },
5691 { 0x1a0000, 0x4000 },
5692 { 0xffffffff, 0 },
b6016b76 5693 };
5bae30c9
MC		 5694 struct mem_entry *mem_tbl;
5695
5696 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5697 mem_tbl = mem_tbl_5709;
5698 else
5699 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5700
5701 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5702 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5703 mem_tbl[i].len)) != 0) {
5704 return ret;
5705 }
5706 }
6aa20a22 5707
b6016b76
MC		 5708 return ret;
5709}
5710
bc5a0690
MC		 5711#define BNX2_MAC_LOOPBACK 0
5712#define BNX2_PHY_LOOPBACK 1
5713
b6016b76 5714static int
bc5a0690 5715bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5716{
5717 unsigned int pkt_size, num_pkts, i;
5718 struct sk_buff *skb, *rx_skb;
5719 unsigned char *packet;
bc5a0690 5720 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5721 dma_addr_t map;
5722 struct tx_bd *txbd;
5723 struct sw_bd *rx_buf;
5724 struct l2_fhdr *rx_hdr;
5725 int ret = -ENODEV;
c76c0475 5726 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
35e9010b 5727 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 5728 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
c76c0475
MC		 5729
5730 tx_napi = bnapi;
b6016b76 5731
35e9010b 5732 txr = &tx_napi->tx_ring;
bb4f98ab 5733 rxr = &bnapi->rx_ring;
bc5a0690
MC		 5734 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5735 bp->loopback = MAC_LOOPBACK;
5736 bnx2_set_mac_loopback(bp);
5737 }
5738 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5740 return 0;
5741
80be4434 5742 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5743 bnx2_set_phy_loopback(bp);
5744 }
5745 else
5746 return -EINVAL;
b6016b76 5747
84eaa187 5748 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5749 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5750 if (!skb)
5751 return -ENOMEM;
b6016b76 5752 packet = skb_put(skb, pkt_size);
6634292b 5753 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5754 memset(packet + 6, 0x0, 8);
5755 for (i = 14; i < pkt_size; i++)
5756 packet[i] = (unsigned char) (i & 0xff);
5757
36227e88
SG		 5758 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5759 PCI_DMA_TODEVICE);
5760 if (dma_mapping_error(&bp->pdev->dev, map)) {
3d16af86
BL		 5761 dev_kfree_skb(skb);
5762 return -EIO;
5763 }
b6016b76 5764
bf5295bb
MC		 5765 REG_WR(bp, BNX2_HC_COMMAND,
5766 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5767
b6016b76
MC		 5768 REG_RD(bp, BNX2_HC_COMMAND);
5769
5770 udelay(5);
35efa7c1 5771 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5772
b6016b76
MC		 5773 num_pkts = 0;
5774
35e9010b 5775 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
b6016b76
MC		 5776
5777 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5778 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5779 txbd->tx_bd_mss_nbytes = pkt_size;
5780 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5781
5782 num_pkts++;
35e9010b
MC		 5783 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5784 txr->tx_prod_bseq += pkt_size;
b6016b76 5785
35e9010b
MC		 5786 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5787 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 5788
5789 udelay(100);
5790
bf5295bb
MC		 5791 REG_WR(bp, BNX2_HC_COMMAND,
5792 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5793
b6016b76
MC		 5794 REG_RD(bp, BNX2_HC_COMMAND);
5795
5796 udelay(5);
5797
36227e88 5798 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5799 dev_kfree_skb(skb);
b6016b76 5800
35e9010b 5801 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
b6016b76 5802 goto loopback_test_done;
b6016b76 5803
35efa7c1 5804 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5805 if (rx_idx != rx_start_idx + num_pkts) {
5806 goto loopback_test_done;
5807 }
5808
bb4f98ab 5809 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
b6016b76
MC		 5810 rx_skb = rx_buf->skb;
5811
a33fa66b 5812 rx_hdr = rx_buf->desc;
d89cb6af 5813 skb_reserve(rx_skb, BNX2_RX_OFFSET);
b6016b76 5814
36227e88 5815 dma_sync_single_for_cpu(&bp->pdev->dev,
1a4ccc2d 5816 dma_unmap_addr(rx_buf, mapping),
b6016b76
MC		 5817 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5818
ade2bfe7 5819 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5820 (L2_FHDR_ERRORS_BAD_CRC |
5821 L2_FHDR_ERRORS_PHY_DECODE |
5822 L2_FHDR_ERRORS_ALIGNMENT |
5823 L2_FHDR_ERRORS_TOO_SHORT |
5824 L2_FHDR_ERRORS_GIANT_FRAME)) {
5825
5826 goto loopback_test_done;
5827 }
5828
5829 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5830 goto loopback_test_done;
5831 }
5832
5833 for (i = 14; i < pkt_size; i++) {
5834 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5835 goto loopback_test_done;
5836 }
5837 }
5838
5839 ret = 0;
5840
5841loopback_test_done:
5842 bp->loopback = 0;
5843 return ret;
5844}
5845
bc5a0690
MC		 5846#define BNX2_MAC_LOOPBACK_FAILED 1
5847#define BNX2_PHY_LOOPBACK_FAILED 2
5848#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5849 BNX2_PHY_LOOPBACK_FAILED)
5850
5851static int
5852bnx2_test_loopback(struct bnx2 *bp)
5853{
5854 int rc = 0;
5855
5856 if (!netif_running(bp->dev))
5857 return BNX2_LOOPBACK_FAILED;
5858
5859 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5860 spin_lock_bh(&bp->phy_lock);
9a120bc5 5861 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5862 spin_unlock_bh(&bp->phy_lock);
5863 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5864 rc |= BNX2_MAC_LOOPBACK_FAILED;
5865 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5866 rc |= BNX2_PHY_LOOPBACK_FAILED;
5867 return rc;
5868}
5869
b6016b76
MC		 5870#define NVRAM_SIZE 0x200
5871#define CRC32_RESIDUAL 0xdebb20e3
5872
5873static int
5874bnx2_test_nvram(struct bnx2 *bp)
5875{
b491edd5 5876 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5877 u8 *data = (u8 *) buf;
5878 int rc = 0;
5879 u32 magic, csum;
5880
5881 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5882 goto test_nvram_done;
5883
5884 magic = be32_to_cpu(buf[0]);
5885 if (magic != 0x669955aa) {
5886 rc = -ENODEV;
5887 goto test_nvram_done;
5888 }
5889
5890 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5891 goto test_nvram_done;
5892
5893 csum = ether_crc_le(0x100, data);
5894 if (csum != CRC32_RESIDUAL) {
5895 rc = -ENODEV;
5896 goto test_nvram_done;
5897 }
5898
5899 csum = ether_crc_le(0x100, data + 0x100);
5900 if (csum != CRC32_RESIDUAL) {
5901 rc = -ENODEV;
5902 }
5903
5904test_nvram_done:
5905 return rc;
5906}
5907
5908static int
5909bnx2_test_link(struct bnx2 *bp)
5910{
5911 u32 bmsr;
5912
9f52b564
MC		 5913 if (!netif_running(bp->dev))
5914 return -ENODEV;
5915
583c28e5 5916 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5917 if (bp->link_up)
5918 return 0;
5919 return -ENODEV;
5920 }
c770a65c 5921 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5922 bnx2_enable_bmsr1(bp);
5923 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5924 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5925 bnx2_disable_bmsr1(bp);
c770a65c 5926 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5927
b6016b76
MC		 5928 if (bmsr & BMSR_LSTATUS) {
5929 return 0;
5930 }
5931 return -ENODEV;
5932}
5933
5934static int
5935bnx2_test_intr(struct bnx2 *bp)
5936{
5937 int i;
b6016b76
MC		 5938 u16 status_idx;
5939
5940 if (!netif_running(bp->dev))
5941 return -ENODEV;
5942
5943 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5944
5945 /* This register is not touched during run-time. */
bf5295bb 5946 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5947 REG_RD(bp, BNX2_HC_COMMAND);
5948
5949 for (i = 0; i < 10; i++) {
5950 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5951 status_idx) {
5952
5953 break;
5954 }
5955
5956 msleep_interruptible(10);
5957 }
5958 if (i < 10)
5959 return 0;
5960
5961 return -ENODEV;
5962}
5963
38ea3686 5964/* Determining link for parallel detection. */
b2fadeae
MC		 5965static int
5966bnx2_5706_serdes_has_link(struct bnx2 *bp)
5967{
5968 u32 mode_ctl, an_dbg, exp;
5969
38ea3686
MC		 5970 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5971 return 0;
5972
b2fadeae
MC		 5973 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5974 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5975
5976 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5977 return 0;
5978
5979 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5980 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5981 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5982
f3014c0c 5983 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 5984 return 0;
5985
5986 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5987 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5988 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5989
5990 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5991 return 0;
5992
5993 return 1;
5994}
5995
b6016b76 5996static void
48b01e2d 5997bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 5998{
b2fadeae
MC		 5999 int check_link = 1;
6000
48b01e2d 6001 spin_lock(&bp->phy_lock);
b2fadeae 6002 if (bp->serdes_an_pending) {
48b01e2d 6003 bp->serdes_an_pending--;
b2fadeae
MC		 6004 check_link = 0;
6005 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 6006 u32 bmcr;
b6016b76 6007
ac392abc 6008 bp->current_interval = BNX2_TIMER_INTERVAL;
cd339a0e 6009
ca58c3af 6010 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6011
48b01e2d 6012 if (bmcr & BMCR_ANENABLE) {
b2fadeae 6013 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 6014 bmcr &= ~BMCR_ANENABLE;
6015 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 6016 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 6017 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 6018 }
b6016b76 6019 }
48b01e2d
MC		 6020 }
6021 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 6022 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 6023 u32 phy2;
b6016b76 6024
48b01e2d
MC		 6025 bnx2_write_phy(bp, 0x17, 0x0f01);
6026 bnx2_read_phy(bp, 0x15, &phy2);
6027 if (phy2 & 0x20) {
6028 u32 bmcr;
cd339a0e 6029
ca58c3af 6030 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 6031 bmcr |= BMCR_ANENABLE;
ca58c3af 6032 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 6033
583c28e5 6034 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 6035 }
6036 } else
ac392abc 6037 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6038
a2724e25 6039 if (check_link) {
b2fadeae
MC		 6040 u32 val;
6041
6042 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6043 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6044 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6045
a2724e25
MC		 6046 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6047 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6048 bnx2_5706s_force_link_dn(bp, 1);
6049 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6050 } else
6051 bnx2_set_link(bp);
6052 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6053 bnx2_set_link(bp);
b2fadeae 6054 }
48b01e2d
MC		 6055 spin_unlock(&bp->phy_lock);
6056}
b6016b76 6057
f8dd064e
MC		 6058static void
6059bnx2_5708_serdes_timer(struct bnx2 *bp)
6060{
583c28e5 6061 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 6062 return;
6063
583c28e5 6064 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 6065 bp->serdes_an_pending = 0;
6066 return;
6067 }
b6016b76 6068
f8dd064e
MC		 6069 spin_lock(&bp->phy_lock);
6070 if (bp->serdes_an_pending)
6071 bp->serdes_an_pending--;
6072 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6073 u32 bmcr;
b6016b76 6074
ca58c3af 6075 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 6076 if (bmcr & BMCR_ANENABLE) {
605a9e20 6077 bnx2_enable_forced_2g5(bp);
40105c0b 6078 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
f8dd064e 6079 } else {
605a9e20 6080 bnx2_disable_forced_2g5(bp);
f8dd064e 6081 bp->serdes_an_pending = 2;
ac392abc 6082 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6083 }
b6016b76 6084
f8dd064e 6085 } else
ac392abc 6086 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6087
f8dd064e
MC		 6088 spin_unlock(&bp->phy_lock);
6089}
6090
48b01e2d
MC		 6091static void
6092bnx2_timer(unsigned long data)
6093{
6094 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 6095
48b01e2d
MC		 6096 if (!netif_running(bp->dev))
6097 return;
b6016b76 6098
48b01e2d
MC		 6099 if (atomic_read(&bp->intr_sem) != 0)
6100 goto bnx2_restart_timer;
b6016b76 6101
efba0180
MC		 6102 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6103 BNX2_FLAG_USING_MSI)
6104 bnx2_chk_missed_msi(bp);
6105
df149d70 6106 bnx2_send_heart_beat(bp);
b6016b76 6107
2726d6e1
MC		 6108 bp->stats_blk->stat_FwRxDrop =
6109 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 6110
02537b06 6111 /* workaround occasional corrupted counters */
61d9e3fa 6112 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
02537b06
MC		 6113 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6114 BNX2_HC_COMMAND_STATS_NOW);
6115
583c28e5 6116 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 6117 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6118 bnx2_5706_serdes_timer(bp);
27a005b8 6119 else
f8dd064e 6120 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 6121 }
6122
6123bnx2_restart_timer:
cd339a0e 6124 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6125}
6126
8e6a72c4
MC		 6127static int
6128bnx2_request_irq(struct bnx2 *bp)
6129{
6d866ffc 6130 unsigned long flags;
b4b36042
MC		 6131 struct bnx2_irq *irq;
6132 int rc = 0, i;
8e6a72c4 6133
f86e82fb 6134 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 6135 flags = 0;
6136 else
6137 flags = IRQF_SHARED;
b4b36042
MC		 6138
6139 for (i = 0; i < bp->irq_nvecs; i++) {
6140 irq = &bp->irq_tbl[i];
c76c0475 6141 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
f0ea2e63 6142 &bp->bnx2_napi[i]);
b4b36042
MC		 6143 if (rc)
6144 break;
6145 irq->requested = 1;
6146 }
8e6a72c4
MC		 6147 return rc;
6148}
6149
6150static void
a29ba9d2 6151__bnx2_free_irq(struct bnx2 *bp)
8e6a72c4 6152{
b4b36042
MC		 6153 struct bnx2_irq *irq;
6154 int i;
8e6a72c4 6155
b4b36042
MC		 6156 for (i = 0; i < bp->irq_nvecs; i++) {
6157 irq = &bp->irq_tbl[i];
6158 if (irq->requested)
f0ea2e63 6159 free_irq(irq->vector, &bp->bnx2_napi[i]);
b4b36042 6160 irq->requested = 0;
6d866ffc 6161 }
a29ba9d2
MC		 6162}
6163
6164static void
6165bnx2_free_irq(struct bnx2 *bp)
6166{
6167
6168 __bnx2_free_irq(bp);
f86e82fb 6169 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 6170 pci_disable_msi(bp->pdev);
f86e82fb 6171 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 6172 pci_disable_msix(bp->pdev);
6173
f86e82fb 6174 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 6175}
6176
6177static void
5e9ad9e1 6178bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
b4b36042 6179{
379b39a2 6180 int i, total_vecs, rc;
57851d84 6181 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
4e1d0de9
MC		 6182 struct net_device *dev = bp->dev;
6183 const int len = sizeof(bp->irq_tbl[0].name);
57851d84 6184
b4b36042
MC		 6185 bnx2_setup_msix_tbl(bp);
6186 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6187 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6188 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84 6189
e2eb8e38
BL		 6190 /* Need to flush the previous three writes to ensure MSI-X
6191 * is setup properly */
6192 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6193
57851d84
MC		 6194 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6195 msix_ent[i].entry = i;
6196 msix_ent[i].vector = 0;
6197 }
6198
379b39a2
MC		 6199 total_vecs = msix_vecs;
6200#ifdef BCM_CNIC
6201 total_vecs++;
6202#endif
6203 rc = -ENOSPC;
6204 while (total_vecs >= BNX2_MIN_MSIX_VEC) {
6205 rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
6206 if (rc <= 0)
6207 break;
6208 if (rc > 0)
6209 total_vecs = rc;
6210 }
6211
57851d84
MC		 6212 if (rc != 0)
6213 return;
6214
379b39a2
MC		 6215 msix_vecs = total_vecs;
6216#ifdef BCM_CNIC
6217 msix_vecs--;
6218#endif
5e9ad9e1 6219 bp->irq_nvecs = msix_vecs;
f86e82fb 6220 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
379b39a2 6221 for (i = 0; i < total_vecs; i++) {
57851d84 6222 bp->irq_tbl[i].vector = msix_ent[i].vector;
69010313
MC		 6223 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6224 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6225 }
6d866ffc
MC		 6226}
6227
657d92fe 6228static int
6d866ffc
MC		 6229bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6230{
5e9ad9e1 6231 int cpus = num_online_cpus();
706bf240 6232 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5e9ad9e1 6233
6d866ffc
MC		 6234 bp->irq_tbl[0].handler = bnx2_interrupt;
6235 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 6236 bp->irq_nvecs = 1;
6237 bp->irq_tbl[0].vector = bp->pdev->irq;
6238
3d5f3a7b 6239 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5e9ad9e1 6240 bnx2_enable_msix(bp, msix_vecs);
6d866ffc 6241
f86e82fb
DM		 6242 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6243 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 6244 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 6245 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 6246 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 6247 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 6248 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6249 } else
6250 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 6251
6252 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 6253 }
6254 }
706bf240
BL		 6255
6256 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
657d92fe 6257 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
706bf240 6258
5e9ad9e1 6259 bp->num_rx_rings = bp->irq_nvecs;
657d92fe 6260 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
8e6a72c4
MC		 6261}
6262
b6016b76
MC		 6263/* Called with rtnl_lock */
6264static int
6265bnx2_open(struct net_device *dev)
6266{
972ec0d4 6267 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6268 int rc;
6269
1b2f922f
MC		 6270 netif_carrier_off(dev);
6271
829ca9a3 6272 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 6273 bnx2_disable_int(bp);
6274
657d92fe
BH		 6275 rc = bnx2_setup_int_mode(bp, disable_msi);
6276 if (rc)
6277 goto open_err;
4327ba43 6278 bnx2_init_napi(bp);
35e9010b 6279 bnx2_napi_enable(bp);
b6016b76 6280 rc = bnx2_alloc_mem(bp);
2739a8bb
MC		 6281 if (rc)
6282 goto open_err;
b6016b76 6283
8e6a72c4 6284 rc = bnx2_request_irq(bp);
2739a8bb
MC		 6285 if (rc)
6286 goto open_err;
b6016b76 6287
9a120bc5 6288 rc = bnx2_init_nic(bp, 1);
2739a8bb
MC		 6289 if (rc)
6290 goto open_err;
6aa20a22 6291
cd339a0e 6292 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6293
6294 atomic_set(&bp->intr_sem, 0);
6295
354fcd77
MC		 6296 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6297
b6016b76
MC		 6298 bnx2_enable_int(bp);
6299
f86e82fb 6300 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 6301 /* Test MSI to make sure it is working
6302 * If MSI test fails, go back to INTx mode
6303 */
6304 if (bnx2_test_intr(bp) != 0) {
3a9c6a49 6305 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
b6016b76
MC		 6306
6307 bnx2_disable_int(bp);
8e6a72c4 6308 bnx2_free_irq(bp);
b6016b76 6309
6d866ffc
MC		 6310 bnx2_setup_int_mode(bp, 1);
6311
9a120bc5 6312 rc = bnx2_init_nic(bp, 0);
b6016b76 6313
8e6a72c4
MC		 6314 if (!rc)
6315 rc = bnx2_request_irq(bp);
6316
b6016b76 6317 if (rc) {
b6016b76 6318 del_timer_sync(&bp->timer);
2739a8bb 6319 goto open_err;
b6016b76
MC		 6320 }
6321 bnx2_enable_int(bp);
6322 }
6323 }
f86e82fb 6324 if (bp->flags & BNX2_FLAG_USING_MSI)
3a9c6a49 6325 netdev_info(dev, "using MSI\n");
f86e82fb 6326 else if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49 6327 netdev_info(dev, "using MSIX\n");
b6016b76 6328
706bf240 6329 netif_tx_start_all_queues(dev);
b6016b76
MC		 6330
6331 return 0;
2739a8bb
MC		 6332
6333open_err:
6334 bnx2_napi_disable(bp);
6335 bnx2_free_skbs(bp);
6336 bnx2_free_irq(bp);
6337 bnx2_free_mem(bp);
f048fa9c 6338 bnx2_del_napi(bp);
2739a8bb 6339 return rc;
b6016b76
MC		 6340}
6341
6342static void
c4028958 6343bnx2_reset_task(struct work_struct *work)
b6016b76 6344{
c4028958 6345 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
cd634019 6346 int rc;
b6016b76 6347
51bf6bb4
MC		 6348 rtnl_lock();
6349 if (!netif_running(bp->dev)) {
6350 rtnl_unlock();
afdc08b9 6351 return;
51bf6bb4 6352 }
afdc08b9 6353
212f9934 6354 bnx2_netif_stop(bp, true);
b6016b76 6355
cd634019
MC		 6356 rc = bnx2_init_nic(bp, 1);
6357 if (rc) {
6358 netdev_err(bp->dev, "failed to reset NIC, closing\n");
6359 bnx2_napi_enable(bp);
6360 dev_close(bp->dev);
6361 rtnl_unlock();
6362 return;
6363 }
b6016b76
MC		 6364
6365 atomic_set(&bp->intr_sem, 1);
212f9934 6366 bnx2_netif_start(bp, true);
51bf6bb4 6367 rtnl_unlock();
b6016b76
MC		 6368}
6369
20175c57
MC		 6370static void
6371bnx2_dump_state(struct bnx2 *bp)
6372{
6373 struct net_device *dev = bp->dev;
ecdbf6e0 6374 u32 val1, val2;
5804a8fb
MC		 6375
6376 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6377 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6378 atomic_read(&bp->intr_sem), val1);
6379 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6380 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6381 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
b98eba52 6382 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
3a9c6a49 6383 REG_RD(bp, BNX2_EMAC_TX_STATUS),
b98eba52
EW		 6384 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6385 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
3a9c6a49 6386 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
3a9c6a49
JP		 6387 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6388 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
20175c57 6389 if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49
JP		 6390 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6391 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
20175c57
MC		 6392}
6393
b6016b76
MC		 6394static void
6395bnx2_tx_timeout(struct net_device *dev)
6396{
972ec0d4 6397 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6398
20175c57 6399 bnx2_dump_state(bp);
ecdbf6e0 6400 bnx2_dump_mcp_state(bp);
20175c57 6401
b6016b76
MC		 6402 /* This allows the netif to be shutdown gracefully before resetting */
6403 schedule_work(&bp->reset_task);
6404}
6405
932ff279 6406/* Called with netif_tx_lock.
2f8af120
MC		 6407 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6408 * netif_wake_queue().
b6016b76 6409 */
61357325 6410static netdev_tx_t
b6016b76
MC		 6411bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6412{
972ec0d4 6413 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6414 dma_addr_t mapping;
6415 struct tx_bd *txbd;
3d16af86 6416 struct sw_tx_bd *tx_buf;
b6016b76
MC		 6417 u32 len, vlan_tag_flags, last_frag, mss;
6418 u16 prod, ring_prod;
6419 int i;
706bf240
BL		 6420 struct bnx2_napi *bnapi;
6421 struct bnx2_tx_ring_info *txr;
6422 struct netdev_queue *txq;
6423
6424 /* Determine which tx ring we will be placed on */
6425 i = skb_get_queue_mapping(skb);
6426 bnapi = &bp->bnx2_napi[i];
6427 txr = &bnapi->tx_ring;
6428 txq = netdev_get_tx_queue(dev, i);
b6016b76 6429
35e9010b 6430 if (unlikely(bnx2_tx_avail(bp, txr) <
a550c99b 6431 (skb_shinfo(skb)->nr_frags + 1))) {
706bf240 6432 netif_tx_stop_queue(txq);
3a9c6a49 6433 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
b6016b76
MC		 6434
6435 return NETDEV_TX_BUSY;
6436 }
6437 len = skb_headlen(skb);
35e9010b 6438 prod = txr->tx_prod;
b6016b76
MC		 6439 ring_prod = TX_RING_IDX(prod);
6440
6441 vlan_tag_flags = 0;
84fa7933 6442 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 6443 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6444 }
6445
eab6d18d 6446 if (vlan_tx_tag_present(skb)) {
b6016b76
MC		 6447 vlan_tag_flags |=
6448 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6449 }
7d0fd211 6450
fde82055 6451 if ((mss = skb_shinfo(skb)->gso_size)) {
a1efb4b6 6452 u32 tcp_opt_len;
eddc9ec5 6453 struct iphdr *iph;
b6016b76 6454
b6016b76
MC		 6455 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6456
4666f87a
MC		 6457 tcp_opt_len = tcp_optlen(skb);
6458
6459 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6460 u32 tcp_off = skb_transport_offset(skb) -
6461 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 6462
4666f87a
MC		 6463 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6464 TX_BD_FLAGS_SW_FLAGS;
6465 if (likely(tcp_off == 0))
6466 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6467 else {
6468 tcp_off >>= 3;
6469 vlan_tag_flags |= ((tcp_off & 0x3) <<
6470 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6471 ((tcp_off & 0x10) <<
6472 TX_BD_FLAGS_TCP6_OFF4_SHL);
6473 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6474 }
6475 } else {
4666f87a 6476 iph = ip_hdr(skb);
4666f87a
MC		 6477 if (tcp_opt_len || (iph->ihl > 5)) {
6478 vlan_tag_flags |= ((iph->ihl - 5) +
6479 (tcp_opt_len >> 2)) << 8;
6480 }
b6016b76 6481 }
4666f87a 6482 } else
b6016b76 6483 mss = 0;
b6016b76 6484
36227e88
SG		 6485 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
6486 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 6487 dev_kfree_skb(skb);
6488 return NETDEV_TX_OK;
6489 }
6490
35e9010b 6491 tx_buf = &txr->tx_buf_ring[ring_prod];
b6016b76 6492 tx_buf->skb = skb;
1a4ccc2d 6493 dma_unmap_addr_set(tx_buf, mapping, mapping);
b6016b76 6494
35e9010b 6495 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6496
6497 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6498 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6499 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6500 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6501
6502 last_frag = skb_shinfo(skb)->nr_frags;
d62fda08
ED		 6503 tx_buf->nr_frags = last_frag;
6504 tx_buf->is_gso = skb_is_gso(skb);
b6016b76
MC		 6505
6506 for (i = 0; i < last_frag; i++) {
6507 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6508
6509 prod = NEXT_TX_BD(prod);
6510 ring_prod = TX_RING_IDX(prod);
35e9010b 6511 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6512
6513 len = frag->size;
b7b6a688
IC		 6514 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,
6515 PCI_DMA_TODEVICE);
36227e88 6516 if (dma_mapping_error(&bp->pdev->dev, mapping))
e95524a7 6517 goto dma_error;
1a4ccc2d 6518 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
e95524a7 6519 mapping);
b6016b76
MC		 6520
6521 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6522 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6523 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6524 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6525
6526 }
6527 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6528
6529 prod = NEXT_TX_BD(prod);
35e9010b 6530 txr->tx_prod_bseq += skb->len;
b6016b76 6531
35e9010b
MC		 6532 REG_WR16(bp, txr->tx_bidx_addr, prod);
6533 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 6534
6535 mmiowb();
6536
35e9010b 6537 txr->tx_prod = prod;
b6016b76 6538
35e9010b 6539 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
706bf240 6540 netif_tx_stop_queue(txq);
11848b96
MC		 6541
6542 /* netif_tx_stop_queue() must be done before checking
6543 * tx index in bnx2_tx_avail() below, because in
6544 * bnx2_tx_int(), we update tx index before checking for
6545 * netif_tx_queue_stopped().
6546 */
6547 smp_mb();
35e9010b 6548 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
706bf240 6549 netif_tx_wake_queue(txq);
b6016b76
MC		 6550 }
6551
e95524a7
AD		 6552 return NETDEV_TX_OK;
6553dma_error:
6554 /* save value of frag that failed */
6555 last_frag = i;
6556
6557 /* start back at beginning and unmap skb */
6558 prod = txr->tx_prod;
6559 ring_prod = TX_RING_IDX(prod);
6560 tx_buf = &txr->tx_buf_ring[ring_prod];
6561 tx_buf->skb = NULL;
36227e88 6562 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6563 skb_headlen(skb), PCI_DMA_TODEVICE);
6564
6565 /* unmap remaining mapped pages */
6566 for (i = 0; i < last_frag; i++) {
6567 prod = NEXT_TX_BD(prod);
6568 ring_prod = TX_RING_IDX(prod);
6569 tx_buf = &txr->tx_buf_ring[ring_prod];
36227e88 6570 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6571 skb_shinfo(skb)->frags[i].size,
6572 PCI_DMA_TODEVICE);
6573 }
6574
6575 dev_kfree_skb(skb);
b6016b76
MC		 6576 return NETDEV_TX_OK;
6577}
6578
6579/* Called with rtnl_lock */
6580static int
6581bnx2_close(struct net_device *dev)
6582{
972ec0d4 6583 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6584
bea3348e 6585 bnx2_disable_int_sync(bp);
35efa7c1 6586 bnx2_napi_disable(bp);
b6016b76 6587 del_timer_sync(&bp->timer);
74bf4ba3 6588 bnx2_shutdown_chip(bp);
8e6a72c4 6589 bnx2_free_irq(bp);
b6016b76
MC		 6590 bnx2_free_skbs(bp);
6591 bnx2_free_mem(bp);
f048fa9c 6592 bnx2_del_napi(bp);
b6016b76
MC		 6593 bp->link_up = 0;
6594 netif_carrier_off(bp->dev);
829ca9a3 6595 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 6596 return 0;
6597}
6598
354fcd77
MC		 6599static void
6600bnx2_save_stats(struct bnx2 *bp)
6601{
6602 u32 *hw_stats = (u32 *) bp->stats_blk;
6603 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6604 int i;
6605
6606 /* The 1st 10 counters are 64-bit counters */
6607 for (i = 0; i < 20; i += 2) {
6608 u32 hi;
6609 u64 lo;
6610
c9885fe5
PR		 6611 hi = temp_stats[i] + hw_stats[i];
6612 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
354fcd77
MC		 6613 if (lo > 0xffffffff)
6614 hi++;
c9885fe5
PR		 6615 temp_stats[i] = hi;
6616 temp_stats[i + 1] = lo & 0xffffffff;
354fcd77
MC		 6617 }
6618
6619 for ( ; i < sizeof(struct statistics_block) / 4; i++)
c9885fe5 6620 temp_stats[i] += hw_stats[i];
354fcd77
MC		 6621}
6622
5d07bf26
ED		 6623#define GET_64BIT_NET_STATS64(ctr) \
6624 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
b6016b76 6625
a4743058 6626#define GET_64BIT_NET_STATS(ctr) \
354fcd77
MC		 6627 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6628 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
b6016b76 6629
a4743058 6630#define GET_32BIT_NET_STATS(ctr) \
354fcd77
MC		 6631 (unsigned long) (bp->stats_blk->ctr + \
6632 bp->temp_stats_blk->ctr)
a4743058 6633
5d07bf26
ED		 6634static struct rtnl_link_stats64 *
6635bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
b6016b76 6636{
972ec0d4 6637 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6638
5d07bf26 6639 if (bp->stats_blk == NULL)
b6016b76 6640 return net_stats;
5d07bf26 6641
b6016b76 6642 net_stats->rx_packets =
a4743058
MC		 6643 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6644 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6645 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
b6016b76
MC		 6646
6647 net_stats->tx_packets =
a4743058
MC		 6648 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6649 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6650 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
b6016b76
MC		 6651
6652 net_stats->rx_bytes =
a4743058 6653 GET_64BIT_NET_STATS(stat_IfHCInOctets);
b6016b76
MC		 6654
6655 net_stats->tx_bytes =
a4743058 6656 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
b6016b76 6657
6aa20a22 6658 net_stats->multicast =
6fdae995 6659 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
b6016b76 6660
6aa20a22 6661 net_stats->collisions =
a4743058 6662 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
b6016b76 6663
6aa20a22 6664 net_stats->rx_length_errors =
a4743058
MC		 6665 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6666 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
b6016b76 6667
6aa20a22 6668 net_stats->rx_over_errors =
a4743058
MC		 6669 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6670 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
b6016b76 6671
6aa20a22 6672 net_stats->rx_frame_errors =
a4743058 6673 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
b6016b76 6674
6aa20a22 6675 net_stats->rx_crc_errors =
a4743058 6676 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
b6016b76
MC		 6677
6678 net_stats->rx_errors = net_stats->rx_length_errors +
6679 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6680 net_stats->rx_crc_errors;
6681
6682 net_stats->tx_aborted_errors =
a4743058
MC		 6683 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6684 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
b6016b76 6685
5b0c76ad
MC		 6686 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6687 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 6688 net_stats->tx_carrier_errors = 0;
6689 else {
6690 net_stats->tx_carrier_errors =
a4743058 6691 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
b6016b76
MC		 6692 }
6693
6694 net_stats->tx_errors =
a4743058 6695 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
b6016b76
MC		 6696 net_stats->tx_aborted_errors +
6697 net_stats->tx_carrier_errors;
6698
cea94db9 6699 net_stats->rx_missed_errors =
a4743058
MC		 6700 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6701 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6702 GET_32BIT_NET_STATS(stat_FwRxDrop);
cea94db9 6703
b6016b76
MC		 6704 return net_stats;
6705}
6706
6707/* All ethtool functions called with rtnl_lock */
6708
6709static int
6710bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6711{
972ec0d4 6712 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6713 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6714
6715 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6716 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6717 support_serdes = 1;
6718 support_copper = 1;
6719 } else if (bp->phy_port == PORT_FIBRE)
6720 support_serdes = 1;
6721 else
6722 support_copper = 1;
6723
6724 if (support_serdes) {
b6016b76
MC		 6725 cmd->supported |= SUPPORTED_1000baseT_Full |
6726 SUPPORTED_FIBRE;
583c28e5 6727 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6728 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6729
b6016b76 6730 }
7b6b8347 6731 if (support_copper) {
b6016b76
MC		 6732 cmd->supported |= SUPPORTED_10baseT_Half |
6733 SUPPORTED_10baseT_Full |
6734 SUPPORTED_100baseT_Half |
6735 SUPPORTED_100baseT_Full |
6736 SUPPORTED_1000baseT_Full |
6737 SUPPORTED_TP;
6738
b6016b76
MC		 6739 }
6740
7b6b8347
MC		 6741 spin_lock_bh(&bp->phy_lock);
6742 cmd->port = bp->phy_port;
b6016b76
MC		 6743 cmd->advertising = bp->advertising;
6744
6745 if (bp->autoneg & AUTONEG_SPEED) {
6746 cmd->autoneg = AUTONEG_ENABLE;
70739497 6747 } else {
b6016b76
MC		 6748 cmd->autoneg = AUTONEG_DISABLE;
6749 }
6750
6751 if (netif_carrier_ok(dev)) {
70739497 6752 ethtool_cmd_speed_set(cmd, bp->line_speed);
b6016b76
MC		 6753 cmd->duplex = bp->duplex;
6754 }
6755 else {
70739497 6756 ethtool_cmd_speed_set(cmd, -1);
b6016b76
MC		 6757 cmd->duplex = -1;
6758 }
7b6b8347 6759 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6760
6761 cmd->transceiver = XCVR_INTERNAL;
6762 cmd->phy_address = bp->phy_addr;
6763
6764 return 0;
6765}
6aa20a22 6766
b6016b76
MC		 6767static int
6768bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6769{
972ec0d4 6770 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6771 u8 autoneg = bp->autoneg;
6772 u8 req_duplex = bp->req_duplex;
6773 u16 req_line_speed = bp->req_line_speed;
6774 u32 advertising = bp->advertising;
7b6b8347
MC		 6775 int err = -EINVAL;
6776
6777 spin_lock_bh(&bp->phy_lock);
6778
6779 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6780 goto err_out_unlock;
6781
583c28e5
MC		 6782 if (cmd->port != bp->phy_port &&
6783 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6784 goto err_out_unlock;
b6016b76 6785
d6b14486
MC		 6786 /* If device is down, we can store the settings only if the user
6787 * is setting the currently active port.
6788 */
6789 if (!netif_running(dev) && cmd->port != bp->phy_port)
6790 goto err_out_unlock;
6791
b6016b76
MC		 6792 if (cmd->autoneg == AUTONEG_ENABLE) {
6793 autoneg |= AUTONEG_SPEED;
6794
beb499af
MC		 6795 advertising = cmd->advertising;
6796 if (cmd->port == PORT_TP) {
6797 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6798 if (!advertising)
b6016b76 6799 advertising = ETHTOOL_ALL_COPPER_SPEED;
beb499af
MC		 6800 } else {
6801 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6802 if (!advertising)
6803 advertising = ETHTOOL_ALL_FIBRE_SPEED;
b6016b76
MC		 6804 }
6805 advertising |= ADVERTISED_Autoneg;
6806 }
6807 else {
25db0338 6808 u32 speed = ethtool_cmd_speed(cmd);
7b6b8347 6809 if (cmd->port == PORT_FIBRE) {
25db0338
DD		 6810 if ((speed != SPEED_1000 &&
6811 speed != SPEED_2500) ||
80be4434 6812 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6813 goto err_out_unlock;
80be4434 6814
25db0338 6815 if (speed == SPEED_2500 &&
583c28e5 6816 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6817 goto err_out_unlock;
25db0338 6818 } else if (speed == SPEED_1000 || speed == SPEED_2500)
7b6b8347
MC		 6819 goto err_out_unlock;
6820
b6016b76 6821 autoneg &= ~AUTONEG_SPEED;
25db0338 6822 req_line_speed = speed;
b6016b76
MC		 6823 req_duplex = cmd->duplex;
6824 advertising = 0;
6825 }
6826
6827 bp->autoneg = autoneg;
6828 bp->advertising = advertising;
6829 bp->req_line_speed = req_line_speed;
6830 bp->req_duplex = req_duplex;
6831
d6b14486
MC		 6832 err = 0;
6833 /* If device is down, the new settings will be picked up when it is
6834 * brought up.
6835 */
6836 if (netif_running(dev))
6837 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6838
7b6b8347 6839err_out_unlock:
c770a65c 6840 spin_unlock_bh(&bp->phy_lock);
b6016b76 6841
7b6b8347 6842 return err;
b6016b76
MC		 6843}
6844
6845static void
6846bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6847{
972ec0d4 6848 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6849
6850 strcpy(info->driver, DRV_MODULE_NAME);
6851 strcpy(info->version, DRV_MODULE_VERSION);
6852 strcpy(info->bus_info, pci_name(bp->pdev));
58fc2ea4 6853 strcpy(info->fw_version, bp->fw_version);
b6016b76
MC		 6854}
6855
244ac4f4
MC		 6856#define BNX2_REGDUMP_LEN (32 * 1024)
6857
6858static int
6859bnx2_get_regs_len(struct net_device *dev)
6860{
6861 return BNX2_REGDUMP_LEN;
6862}
6863
6864static void
6865bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6866{
6867 u32 *p = _p, i, offset;
6868 u8 *orig_p = _p;
6869 struct bnx2 *bp = netdev_priv(dev);
b6bc7650
JP		 6870 static const u32 reg_boundaries[] = {
6871 0x0000, 0x0098, 0x0400, 0x045c,
6872 0x0800, 0x0880, 0x0c00, 0x0c10,
6873 0x0c30, 0x0d08, 0x1000, 0x101c,
6874 0x1040, 0x1048, 0x1080, 0x10a4,
6875 0x1400, 0x1490, 0x1498, 0x14f0,
6876 0x1500, 0x155c, 0x1580, 0x15dc,
6877 0x1600, 0x1658, 0x1680, 0x16d8,
6878 0x1800, 0x1820, 0x1840, 0x1854,
6879 0x1880, 0x1894, 0x1900, 0x1984,
6880 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6881 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6882 0x2000, 0x2030, 0x23c0, 0x2400,
6883 0x2800, 0x2820, 0x2830, 0x2850,
6884 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6885 0x3c00, 0x3c94, 0x4000, 0x4010,
6886 0x4080, 0x4090, 0x43c0, 0x4458,
6887 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6888 0x4fc0, 0x5010, 0x53c0, 0x5444,
6889 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6890 0x5fc0, 0x6000, 0x6400, 0x6428,
6891 0x6800, 0x6848, 0x684c, 0x6860,
6892 0x6888, 0x6910, 0x8000
6893 };
244ac4f4
MC		 6894
6895 regs->version = 0;
6896
6897 memset(p, 0, BNX2_REGDUMP_LEN);
6898
6899 if (!netif_running(bp->dev))
6900 return;
6901
6902 i = 0;
6903 offset = reg_boundaries[0];
6904 p += offset;
6905 while (offset < BNX2_REGDUMP_LEN) {
6906 *p++ = REG_RD(bp, offset);
6907 offset += 4;
6908 if (offset == reg_boundaries[i + 1]) {
6909 offset = reg_boundaries[i + 2];
6910 p = (u32 *) (orig_p + offset);
6911 i += 2;
6912 }
6913 }
6914}
6915
b6016b76
MC		 6916static void
6917bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6918{
972ec0d4 6919 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6920
f86e82fb 6921 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6922 wol->supported = 0;
6923 wol->wolopts = 0;
6924 }
6925 else {
6926 wol->supported = WAKE_MAGIC;
6927 if (bp->wol)
6928 wol->wolopts = WAKE_MAGIC;
6929 else
6930 wol->wolopts = 0;
6931 }
6932 memset(&wol->sopass, 0, sizeof(wol->sopass));
6933}
6934
6935static int
6936bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6937{
972ec0d4 6938 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6939
6940 if (wol->wolopts & ~WAKE_MAGIC)
6941 return -EINVAL;
6942
6943 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6944 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6945 return -EINVAL;
6946
6947 bp->wol = 1;
6948 }
6949 else {
6950 bp->wol = 0;
6951 }
6952 return 0;
6953}
6954
6955static int
6956bnx2_nway_reset(struct net_device *dev)
6957{
972ec0d4 6958 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6959 u32 bmcr;
6960
9f52b564
MC		 6961 if (!netif_running(dev))
6962 return -EAGAIN;
6963
b6016b76
MC		 6964 if (!(bp->autoneg & AUTONEG_SPEED)) {
6965 return -EINVAL;
6966 }
6967
c770a65c 6968 spin_lock_bh(&bp->phy_lock);
b6016b76 6969
583c28e5 6970 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6971 int rc;
6972
6973 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6974 spin_unlock_bh(&bp->phy_lock);
6975 return rc;
6976 }
6977
b6016b76 6978 /* Force a link down visible on the other side */
583c28e5 6979 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 6980 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 6981 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6982
6983 msleep(20);
6984
c770a65c 6985 spin_lock_bh(&bp->phy_lock);
f8dd064e 6986
40105c0b 6987 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 6988 bp->serdes_an_pending = 1;
6989 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6990 }
6991
ca58c3af 6992 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6993 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 6994 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 6995
c770a65c 6996 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6997
6998 return 0;
6999}
7000
7959ea25
ON		 7001static u32
7002bnx2_get_link(struct net_device *dev)
7003{
7004 struct bnx2 *bp = netdev_priv(dev);
7005
7006 return bp->link_up;
7007}
7008
b6016b76
MC		 7009static int
7010bnx2_get_eeprom_len(struct net_device *dev)
7011{
972ec0d4 7012 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7013
1122db71 7014 if (bp->flash_info == NULL)
b6016b76
MC		 7015 return 0;
7016
1122db71 7017 return (int) bp->flash_size;
b6016b76
MC		 7018}
7019
7020static int
7021bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7022 u8 *eebuf)
7023{
972ec0d4 7024 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7025 int rc;
7026
9f52b564
MC		 7027 if (!netif_running(dev))
7028 return -EAGAIN;
7029
1064e944 7030 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 7031
7032 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7033
7034 return rc;
7035}
7036
7037static int
7038bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7039 u8 *eebuf)
7040{
972ec0d4 7041 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7042 int rc;
7043
9f52b564
MC		 7044 if (!netif_running(dev))
7045 return -EAGAIN;
7046
1064e944 7047 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 7048
7049 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7050
7051 return rc;
7052}
7053
7054static int
7055bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7056{
972ec0d4 7057 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7058
7059 memset(coal, 0, sizeof(struct ethtool_coalesce));
7060
7061 coal->rx_coalesce_usecs = bp->rx_ticks;
7062 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7063 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7064 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7065
7066 coal->tx_coalesce_usecs = bp->tx_ticks;
7067 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7068 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7069 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7070
7071 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7072
7073 return 0;
7074}
7075
7076static int
7077bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7078{
972ec0d4 7079 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7080
7081 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7082 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7083
6aa20a22 7084 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 7085 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7086
7087 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7088 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7089
7090 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7091 if (bp->rx_quick_cons_trip_int > 0xff)
7092 bp->rx_quick_cons_trip_int = 0xff;
7093
7094 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7095 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7096
7097 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7098 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7099
7100 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7101 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7102
7103 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7104 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7105 0xff;
7106
7107 bp->stats_ticks = coal->stats_block_coalesce_usecs;
61d9e3fa 7108 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
02537b06
MC		 7109 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7110 bp->stats_ticks = USEC_PER_SEC;
7111 }
7ea6920e
MC		 7112 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7113 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7114 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7115
7116 if (netif_running(bp->dev)) {
212f9934 7117 bnx2_netif_stop(bp, true);
9a120bc5 7118 bnx2_init_nic(bp, 0);
212f9934 7119 bnx2_netif_start(bp, true);
b6016b76
MC		 7120 }
7121
7122 return 0;
7123}
7124
7125static void
7126bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7127{
972ec0d4 7128 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7129
13daffa2 7130 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
b6016b76 7131 ering->rx_mini_max_pending = 0;
47bf4246 7132 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 7133
7134 ering->rx_pending = bp->rx_ring_size;
7135 ering->rx_mini_pending = 0;
47bf4246 7136 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 7137
7138 ering->tx_max_pending = MAX_TX_DESC_CNT;
7139 ering->tx_pending = bp->tx_ring_size;
7140}
7141
7142static int
5d5d0015 7143bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 7144{
13daffa2 7145 if (netif_running(bp->dev)) {
354fcd77
MC		 7146 /* Reset will erase chipset stats; save them */
7147 bnx2_save_stats(bp);
7148
212f9934 7149 bnx2_netif_stop(bp, true);
13daffa2 7150 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
a29ba9d2 7151 __bnx2_free_irq(bp);
13daffa2
MC		 7152 bnx2_free_skbs(bp);
7153 bnx2_free_mem(bp);
7154 }
7155
5d5d0015
MC		 7156 bnx2_set_rx_ring_size(bp, rx);
7157 bp->tx_ring_size = tx;
b6016b76
MC		 7158
7159 if (netif_running(bp->dev)) {
13daffa2
MC		 7160 int rc;
7161
7162 rc = bnx2_alloc_mem(bp);
a29ba9d2
MC		 7163 if (!rc)
7164 rc = bnx2_request_irq(bp);
7165
6fefb65e
MC		 7166 if (!rc)
7167 rc = bnx2_init_nic(bp, 0);
7168
7169 if (rc) {
7170 bnx2_napi_enable(bp);
7171 dev_close(bp->dev);
13daffa2 7172 return rc;
6fefb65e 7173 }
e9f26c49
MC		 7174#ifdef BCM_CNIC
7175 mutex_lock(&bp->cnic_lock);
7176 /* Let cnic know about the new status block. */
7177 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7178 bnx2_setup_cnic_irq_info(bp);
7179 mutex_unlock(&bp->cnic_lock);
7180#endif
212f9934 7181 bnx2_netif_start(bp, true);
b6016b76 7182 }
b6016b76
MC		 7183 return 0;
7184}
7185
5d5d0015
MC		 7186static int
7187bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7188{
7189 struct bnx2 *bp = netdev_priv(dev);
7190 int rc;
7191
7192 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7193 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7194 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7195
7196 return -EINVAL;
7197 }
7198 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7199 return rc;
7200}
7201
b6016b76
MC		 7202static void
7203bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7204{
972ec0d4 7205 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7206
7207 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7208 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7209 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7210}
7211
7212static int
7213bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7214{
972ec0d4 7215 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7216
7217 bp->req_flow_ctrl = 0;
7218 if (epause->rx_pause)
7219 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7220 if (epause->tx_pause)
7221 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7222
7223 if (epause->autoneg) {
7224 bp->autoneg |= AUTONEG_FLOW_CTRL;
7225 }
7226 else {
7227 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7228 }
7229
9f52b564
MC		 7230 if (netif_running(dev)) {
7231 spin_lock_bh(&bp->phy_lock);
7232 bnx2_setup_phy(bp, bp->phy_port);
7233 spin_unlock_bh(&bp->phy_lock);
7234 }
b6016b76
MC		 7235
7236 return 0;
7237}
7238
14ab9b86 7239static struct {
b6016b76 7240 char string[ETH_GSTRING_LEN];
790dab2f 7241} bnx2_stats_str_arr[] = {
b6016b76
MC		 7242 { "rx_bytes" },
7243 { "rx_error_bytes" },
7244 { "tx_bytes" },
7245 { "tx_error_bytes" },
7246 { "rx_ucast_packets" },
7247 { "rx_mcast_packets" },
7248 { "rx_bcast_packets" },
7249 { "tx_ucast_packets" },
7250 { "tx_mcast_packets" },
7251 { "tx_bcast_packets" },
7252 { "tx_mac_errors" },
7253 { "tx_carrier_errors" },
7254 { "rx_crc_errors" },
7255 { "rx_align_errors" },
7256 { "tx_single_collisions" },
7257 { "tx_multi_collisions" },
7258 { "tx_deferred" },
7259 { "tx_excess_collisions" },
7260 { "tx_late_collisions" },
7261 { "tx_total_collisions" },
7262 { "rx_fragments" },
7263 { "rx_jabbers" },
7264 { "rx_undersize_packets" },
7265 { "rx_oversize_packets" },
7266 { "rx_64_byte_packets" },
7267 { "rx_65_to_127_byte_packets" },
7268 { "rx_128_to_255_byte_packets" },
7269 { "rx_256_to_511_byte_packets" },
7270 { "rx_512_to_1023_byte_packets" },
7271 { "rx_1024_to_1522_byte_packets" },
7272 { "rx_1523_to_9022_byte_packets" },
7273 { "tx_64_byte_packets" },
7274 { "tx_65_to_127_byte_packets" },
7275 { "tx_128_to_255_byte_packets" },
7276 { "tx_256_to_511_byte_packets" },
7277 { "tx_512_to_1023_byte_packets" },
7278 { "tx_1024_to_1522_byte_packets" },
7279 { "tx_1523_to_9022_byte_packets" },
7280 { "rx_xon_frames" },
7281 { "rx_xoff_frames" },
7282 { "tx_xon_frames" },
7283 { "tx_xoff_frames" },
7284 { "rx_mac_ctrl_frames" },
7285 { "rx_filtered_packets" },
790dab2f 7286 { "rx_ftq_discards" },
b6016b76 7287 { "rx_discards" },
cea94db9 7288 { "rx_fw_discards" },
b6016b76
MC		 7289};
7290
790dab2f
MC		 7291#define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7292 sizeof(bnx2_stats_str_arr[0]))
7293
b6016b76
MC		 7294#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7295
f71e1309 7296static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7297 STATS_OFFSET32(stat_IfHCInOctets_hi),
7298 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7299 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7300 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7301 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7302 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7303 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7304 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7305 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7306 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7307 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 7308 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7309 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7310 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7311 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7312 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7313 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7314 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7315 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7316 STATS_OFFSET32(stat_EtherStatsCollisions),
7317 STATS_OFFSET32(stat_EtherStatsFragments),
7318 STATS_OFFSET32(stat_EtherStatsJabbers),
7319 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7320 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7321 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7322 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7323 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7324 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7325 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7326 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7327 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7328 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7329 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7330 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7331 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7332 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7333 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7334 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7335 STATS_OFFSET32(stat_XonPauseFramesReceived),
7336 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7337 STATS_OFFSET32(stat_OutXonSent),
7338 STATS_OFFSET32(stat_OutXoffSent),
7339 STATS_OFFSET32(stat_MacControlFramesReceived),
7340 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
790dab2f 7341 STATS_OFFSET32(stat_IfInFTQDiscards),
6aa20a22 7342 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 7343 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 7344};
7345
7346/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7347 * skipped because of errata.
6aa20a22 7348 */
14ab9b86 7349static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7350 8,0,8,8,8,8,8,8,8,8,
7351 4,0,4,4,4,4,4,4,4,4,
7352 4,4,4,4,4,4,4,4,4,4,
7353 4,4,4,4,4,4,4,4,4,4,
790dab2f 7354 4,4,4,4,4,4,4,
b6016b76
MC		 7355};
7356
5b0c76ad
MC		 7357static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7358 8,0,8,8,8,8,8,8,8,8,
7359 4,4,4,4,4,4,4,4,4,4,
7360 4,4,4,4,4,4,4,4,4,4,
7361 4,4,4,4,4,4,4,4,4,4,
790dab2f 7362 4,4,4,4,4,4,4,
5b0c76ad
MC		 7363};
7364
b6016b76
MC		 7365#define BNX2_NUM_TESTS 6
7366
14ab9b86 7367static struct {
b6016b76
MC		 7368 char string[ETH_GSTRING_LEN];
7369} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7370 { "register_test (offline)" },
7371 { "memory_test (offline)" },
7372 { "loopback_test (offline)" },
7373 { "nvram_test (online)" },
7374 { "interrupt_test (online)" },
7375 { "link_test (online)" },
7376};
7377
7378static int
b9f2c044 7379bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 7380{
b9f2c044
JG		 7381 switch (sset) {
7382 case ETH_SS_TEST:
7383 return BNX2_NUM_TESTS;
7384 case ETH_SS_STATS:
7385 return BNX2_NUM_STATS;
7386 default:
7387 return -EOPNOTSUPP;
7388 }
b6016b76
MC		 7389}
7390
7391static void
7392bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7393{
972ec0d4 7394 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7395
9f52b564
MC		 7396 bnx2_set_power_state(bp, PCI_D0);
7397
b6016b76
MC		 7398 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7399 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 7400 int i;
7401
212f9934 7402 bnx2_netif_stop(bp, true);
b6016b76
MC		 7403 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7404 bnx2_free_skbs(bp);
7405
7406 if (bnx2_test_registers(bp) != 0) {
7407 buf[0] = 1;
7408 etest->flags |= ETH_TEST_FL_FAILED;
7409 }
7410 if (bnx2_test_memory(bp) != 0) {
7411 buf[1] = 1;
7412 etest->flags |= ETH_TEST_FL_FAILED;
7413 }
bc5a0690 7414 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 7415 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76 7416
9f52b564
MC		 7417 if (!netif_running(bp->dev))
7418 bnx2_shutdown_chip(bp);
b6016b76 7419 else {
9a120bc5 7420 bnx2_init_nic(bp, 1);
212f9934 7421 bnx2_netif_start(bp, true);
b6016b76
MC		 7422 }
7423
7424 /* wait for link up */
80be4434
MC		 7425 for (i = 0; i < 7; i++) {
7426 if (bp->link_up)
7427 break;
7428 msleep_interruptible(1000);
7429 }
b6016b76
MC		 7430 }
7431
7432 if (bnx2_test_nvram(bp) != 0) {
7433 buf[3] = 1;
7434 etest->flags |= ETH_TEST_FL_FAILED;
7435 }
7436 if (bnx2_test_intr(bp) != 0) {
7437 buf[4] = 1;
7438 etest->flags |= ETH_TEST_FL_FAILED;
7439 }
7440
7441 if (bnx2_test_link(bp) != 0) {
7442 buf[5] = 1;
7443 etest->flags |= ETH_TEST_FL_FAILED;
7444
7445 }
9f52b564
MC		 7446 if (!netif_running(bp->dev))
7447 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 7448}
7449
7450static void
7451bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7452{
7453 switch (stringset) {
7454 case ETH_SS_STATS:
7455 memcpy(buf, bnx2_stats_str_arr,
7456 sizeof(bnx2_stats_str_arr));
7457 break;
7458 case ETH_SS_TEST:
7459 memcpy(buf, bnx2_tests_str_arr,
7460 sizeof(bnx2_tests_str_arr));
7461 break;
7462 }
7463}
7464
b6016b76
MC		 7465static void
7466bnx2_get_ethtool_stats(struct net_device *dev,
7467 struct ethtool_stats *stats, u64 *buf)
7468{
972ec0d4 7469 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7470 int i;
7471 u32 *hw_stats = (u32 *) bp->stats_blk;
354fcd77 7472 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
14ab9b86 7473 u8 *stats_len_arr = NULL;
b6016b76
MC		 7474
7475 if (hw_stats == NULL) {
7476 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7477 return;
7478 }
7479
5b0c76ad
MC		 7480 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7481 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7482 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7483 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 7484 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 7485 else
7486 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 7487
7488 for (i = 0; i < BNX2_NUM_STATS; i++) {
354fcd77
MC		 7489 unsigned long offset;
7490
b6016b76
MC		 7491 if (stats_len_arr[i] == 0) {
7492 /* skip this counter */
7493 buf[i] = 0;
7494 continue;
7495 }
354fcd77
MC		 7496
7497 offset = bnx2_stats_offset_arr[i];
b6016b76
MC		 7498 if (stats_len_arr[i] == 4) {
7499 /* 4-byte counter */
354fcd77
MC		 7500 buf[i] = (u64) *(hw_stats + offset) +
7501 *(temp_stats + offset);
b6016b76
MC		 7502 continue;
7503 }
7504 /* 8-byte counter */
354fcd77
MC		 7505 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7506 *(hw_stats + offset + 1) +
7507 (((u64) *(temp_stats + offset)) << 32) +
7508 *(temp_stats + offset + 1);
b6016b76
MC		 7509 }
7510}
7511
7512static int
2e17e1aa 7513bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state)
b6016b76 7514{
972ec0d4 7515 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7516
2e17e1aa 7517 switch (state) {
7518 case ETHTOOL_ID_ACTIVE:
7519 bnx2_set_power_state(bp, PCI_D0);
9f52b564 7520
2e17e1aa 7521 bp->leds_save = REG_RD(bp, BNX2_MISC_CFG);
7522 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
fce55922 7523 return 1; /* cycle on/off once per second */
b6016b76 7524
2e17e1aa 7525 case ETHTOOL_ID_ON:
7526 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7527 BNX2_EMAC_LED_1000MB_OVERRIDE |
7528 BNX2_EMAC_LED_100MB_OVERRIDE |
7529 BNX2_EMAC_LED_10MB_OVERRIDE |
7530 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7531 BNX2_EMAC_LED_TRAFFIC);
7532 break;
b6016b76 7533
2e17e1aa 7534 case ETHTOOL_ID_OFF:
7535 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7536 break;
9f52b564 7537
2e17e1aa 7538 case ETHTOOL_ID_INACTIVE:
7539 REG_WR(bp, BNX2_EMAC_LED, 0);
7540 REG_WR(bp, BNX2_MISC_CFG, bp->leds_save);
7541
7542 if (!netif_running(dev))
7543 bnx2_set_power_state(bp, PCI_D3hot);
7544 break;
7545 }
9f52b564 7546
b6016b76
MC		 7547 return 0;
7548}
7549
8d7dfc2b
MM		 7550static u32
7551bnx2_fix_features(struct net_device *dev, u32 features)
4666f87a
MC		 7552{
7553 struct bnx2 *bp = netdev_priv(dev);
7554
8d7dfc2b
MM		 7555 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
7556 features |= NETIF_F_HW_VLAN_RX;
7557
7558 return features;
4666f87a
MC		 7559}
7560
fdc8541d 7561static int
8d7dfc2b 7562bnx2_set_features(struct net_device *dev, u32 features)
fdc8541d 7563{
7d0fd211 7564 struct bnx2 *bp = netdev_priv(dev);
7d0fd211 7565
7c810477 7566 /* TSO with VLAN tag won't work with current firmware */
8d7dfc2b
MM		 7567 if (features & NETIF_F_HW_VLAN_TX)
7568 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO);
7569 else
7570 dev->vlan_features &= ~NETIF_F_ALL_TSO;
7d0fd211 7571
8d7dfc2b 7572 if ((!!(features & NETIF_F_HW_VLAN_RX) !=
7d0fd211
JG		 7573 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
7574 netif_running(dev)) {
7575 bnx2_netif_stop(bp, false);
8d7dfc2b 7576 dev->features = features;
7d0fd211
JG		 7577 bnx2_set_rx_mode(dev);
7578 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
7579 bnx2_netif_start(bp, false);
8d7dfc2b 7580 return 1;
7d0fd211
JG		 7581 }
7582
7583 return 0;
fdc8541d
MC		 7584}
7585
7282d491 7586static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 7587 .get_settings = bnx2_get_settings,
7588 .set_settings = bnx2_set_settings,
7589 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 7590 .get_regs_len = bnx2_get_regs_len,
7591 .get_regs = bnx2_get_regs,
b6016b76
MC		 7592 .get_wol = bnx2_get_wol,
7593 .set_wol = bnx2_set_wol,
7594 .nway_reset = bnx2_nway_reset,
7959ea25 7595 .get_link = bnx2_get_link,
b6016b76
MC		 7596 .get_eeprom_len = bnx2_get_eeprom_len,
7597 .get_eeprom = bnx2_get_eeprom,
7598 .set_eeprom = bnx2_set_eeprom,
7599 .get_coalesce = bnx2_get_coalesce,
7600 .set_coalesce = bnx2_set_coalesce,
7601 .get_ringparam = bnx2_get_ringparam,
7602 .set_ringparam = bnx2_set_ringparam,
7603 .get_pauseparam = bnx2_get_pauseparam,
7604 .set_pauseparam = bnx2_set_pauseparam,
b6016b76
MC		 7605 .self_test = bnx2_self_test,
7606 .get_strings = bnx2_get_strings,
2e17e1aa 7607 .set_phys_id = bnx2_set_phys_id,
b6016b76 7608 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 7609 .get_sset_count = bnx2_get_sset_count,
b6016b76
MC		 7610};
7611
7612/* Called with rtnl_lock */
7613static int
7614bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7615{
14ab9b86 7616 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 7617 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7618 int err;
7619
7620 switch(cmd) {
7621 case SIOCGMIIPHY:
7622 data->phy_id = bp->phy_addr;
7623
7624 /* fallthru */
7625 case SIOCGMIIREG: {
7626 u32 mii_regval;
7627
583c28e5 7628 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7629 return -EOPNOTSUPP;
7630
dad3e452
MC		 7631 if (!netif_running(dev))
7632 return -EAGAIN;
7633
c770a65c 7634 spin_lock_bh(&bp->phy_lock);
b6016b76 7635 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 7636 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7637
7638 data->val_out = mii_regval;
7639
7640 return err;
7641 }
7642
7643 case SIOCSMIIREG:
583c28e5 7644 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7645 return -EOPNOTSUPP;
7646
dad3e452
MC		 7647 if (!netif_running(dev))
7648 return -EAGAIN;
7649
c770a65c 7650 spin_lock_bh(&bp->phy_lock);
b6016b76 7651 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 7652 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7653
7654 return err;
7655
7656 default:
7657 /* do nothing */
7658 break;
7659 }
7660 return -EOPNOTSUPP;
7661}
7662
7663/* Called with rtnl_lock */
7664static int
7665bnx2_change_mac_addr(struct net_device *dev, void *p)
7666{
7667 struct sockaddr *addr = p;
972ec0d4 7668 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7669
73eef4cd
MC		 7670 if (!is_valid_ether_addr(addr->sa_data))
7671 return -EINVAL;
7672
b6016b76
MC		 7673 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7674 if (netif_running(dev))
5fcaed01 7675 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 7676
7677 return 0;
7678}
7679
7680/* Called with rtnl_lock */
7681static int
7682bnx2_change_mtu(struct net_device *dev, int new_mtu)
7683{
972ec0d4 7684 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7685
7686 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7687 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7688 return -EINVAL;
7689
7690 dev->mtu = new_mtu;
807540ba 7691 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size);
b6016b76
MC		 7692}
7693
257ddbda 7694#ifdef CONFIG_NET_POLL_CONTROLLER
b6016b76
MC		 7695static void
7696poll_bnx2(struct net_device *dev)
7697{
972ec0d4 7698 struct bnx2 *bp = netdev_priv(dev);
b2af2c1d 7699 int i;
b6016b76 7700
b2af2c1d 7701 for (i = 0; i < bp->irq_nvecs; i++) {
1bf1e347
MC		 7702 struct bnx2_irq *irq = &bp->irq_tbl[i];
7703
7704 disable_irq(irq->vector);
7705 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7706 enable_irq(irq->vector);
b2af2c1d 7707 }
b6016b76
MC		 7708}
7709#endif
7710
253c8b75
MC		 7711static void __devinit
7712bnx2_get_5709_media(struct bnx2 *bp)
7713{
7714 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7715 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7716 u32 strap;
7717
7718 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7719 return;
7720 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7721 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7722 return;
7723 }
7724
7725 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7726 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7727 else
7728 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7729
7730 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7731 switch (strap) {
7732 case 0x4:
7733 case 0x5:
7734 case 0x6:
583c28e5 7735 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7736 return;
7737 }
7738 } else {
7739 switch (strap) {
7740 case 0x1:
7741 case 0x2:
7742 case 0x4:
583c28e5 7743 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7744 return;
7745 }
7746 }
7747}
7748
883e5151
MC		 7749static void __devinit
7750bnx2_get_pci_speed(struct bnx2 *bp)
7751{
7752 u32 reg;
7753
7754 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7755 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7756 u32 clkreg;
7757
f86e82fb 7758 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 7759
7760 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7761
7762 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7763 switch (clkreg) {
7764 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7765 bp->bus_speed_mhz = 133;
7766 break;
7767
7768 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7769 bp->bus_speed_mhz = 100;
7770 break;
7771
7772 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7773 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7774 bp->bus_speed_mhz = 66;
7775 break;
7776
7777 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7778 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7779 bp->bus_speed_mhz = 50;
7780 break;
7781
7782 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7783 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7784 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7785 bp->bus_speed_mhz = 33;
7786 break;
7787 }
7788 }
7789 else {
7790 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7791 bp->bus_speed_mhz = 66;
7792 else
7793 bp->bus_speed_mhz = 33;
7794 }
7795
7796 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7797 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7798
7799}
7800
76d99061
MC		 7801static void __devinit
7802bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7803{
df25bc38 7804 int rc, i, j;
76d99061 7805 u8 *data;
df25bc38 7806 unsigned int block_end, rosize, len;
76d99061 7807
012093f6
MC		 7808#define BNX2_VPD_NVRAM_OFFSET 0x300
7809#define BNX2_VPD_LEN 128
76d99061
MC		 7810#define BNX2_MAX_VER_SLEN 30
7811
7812 data = kmalloc(256, GFP_KERNEL);
7813 if (!data)
7814 return;
7815
012093f6
MC		 7816 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7817 BNX2_VPD_LEN);
76d99061
MC		 7818 if (rc)
7819 goto vpd_done;
7820
012093f6
MC		 7821 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7822 data[i] = data[i + BNX2_VPD_LEN + 3];
7823 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7824 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7825 data[i + 3] = data[i + BNX2_VPD_LEN];
76d99061
MC		 7826 }
7827
df25bc38
MC		 7828 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7829 if (i < 0)
7830 goto vpd_done;
76d99061 7831
df25bc38
MC		 7832 rosize = pci_vpd_lrdt_size(&data[i]);
7833 i += PCI_VPD_LRDT_TAG_SIZE;
7834 block_end = i + rosize;
76d99061 7835
df25bc38
MC		 7836 if (block_end > BNX2_VPD_LEN)
7837 goto vpd_done;
76d99061 7838
df25bc38
MC		 7839 j = pci_vpd_find_info_keyword(data, i, rosize,
7840 PCI_VPD_RO_KEYWORD_MFR_ID);
7841 if (j < 0)
7842 goto vpd_done;
76d99061 7843
df25bc38 7844 len = pci_vpd_info_field_size(&data[j]);
76d99061 7845
df25bc38
MC		 7846 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7847 if (j + len > block_end || len != 4 ||
7848 memcmp(&data[j], "1028", 4))
7849 goto vpd_done;
4067a854 7850
df25bc38
MC		 7851 j = pci_vpd_find_info_keyword(data, i, rosize,
7852 PCI_VPD_RO_KEYWORD_VENDOR0);
7853 if (j < 0)
7854 goto vpd_done;
4067a854 7855
df25bc38 7856 len = pci_vpd_info_field_size(&data[j]);
4067a854 7857
df25bc38
MC		 7858 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7859 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
76d99061 7860 goto vpd_done;
df25bc38
MC		 7861
7862 memcpy(bp->fw_version, &data[j], len);
7863 bp->fw_version[len] = ' ';
76d99061
MC		 7864
7865vpd_done:
7866 kfree(data);
7867}
7868
b6016b76
MC		 7869static int __devinit
7870bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7871{
7872 struct bnx2 *bp;
7873 unsigned long mem_len;
58fc2ea4 7874 int rc, i, j;
b6016b76 7875 u32 reg;
40453c83 7876 u64 dma_mask, persist_dma_mask;
cd709aa9 7877 int err;
b6016b76 7878
b6016b76 7879 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7880 bp = netdev_priv(dev);
b6016b76
MC		 7881
7882 bp->flags = 0;
7883 bp->phy_flags = 0;
7884
354fcd77
MC		 7885 bp->temp_stats_blk =
7886 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7887
7888 if (bp->temp_stats_blk == NULL) {
7889 rc = -ENOMEM;
7890 goto err_out;
7891 }
7892
b6016b76
MC		 7893 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7894 rc = pci_enable_device(pdev);
7895 if (rc) {
3a9c6a49 7896 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
b6016b76
MC		 7897 goto err_out;
7898 }
7899
7900 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7901 dev_err(&pdev->dev,
3a9c6a49 7902 "Cannot find PCI device base address, aborting\n");
b6016b76
MC		 7903 rc = -ENODEV;
7904 goto err_out_disable;
7905 }
7906
7907 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7908 if (rc) {
3a9c6a49 7909 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
b6016b76
MC		 7910 goto err_out_disable;
7911 }
7912
7913 pci_set_master(pdev);
7914
7915 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7916 if (bp->pm_cap == 0) {
9b91cf9d 7917 dev_err(&pdev->dev,
3a9c6a49 7918 "Cannot find power management capability, aborting\n");
b6016b76
MC		 7919 rc = -EIO;
7920 goto err_out_release;
7921 }
7922
b6016b76
MC		 7923 bp->dev = dev;
7924 bp->pdev = pdev;
7925
7926 spin_lock_init(&bp->phy_lock);
1b8227c4 7927 spin_lock_init(&bp->indirect_lock);
c5a88950
MC		 7928#ifdef BCM_CNIC
7929 mutex_init(&bp->cnic_lock);
7930#endif
c4028958 7931 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7932
7933 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
4edd473f 7934 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
b6016b76
MC		 7935 dev->mem_end = dev->mem_start + mem_len;
7936 dev->irq = pdev->irq;
7937
7938 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7939
7940 if (!bp->regview) {
3a9c6a49 7941 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
b6016b76
MC		 7942 rc = -ENOMEM;
7943 goto err_out_release;
7944 }
7945
be7ff1af
MC		 7946 bnx2_set_power_state(bp, PCI_D0);
7947
b6016b76
MC		 7948 /* Configure byte swap and enable write to the reg_window registers.
7949 * Rely on CPU to do target byte swapping on big endian systems
7950 * The chip's target access swapping will not swap all accesses
7951 */
be7ff1af
MC		 7952 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG,
7953 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7954 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
b6016b76
MC		 7955
7956 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7957
883e5151 7958 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
e82760e7
JM		 7959 if (!pci_is_pcie(pdev)) {
7960 dev_err(&pdev->dev, "Not PCIE, aborting\n");
883e5151
MC		 7961 rc = -EIO;
7962 goto err_out_unmap;
7963 }
f86e82fb 7964 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7965 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7966 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
c239f279
MC		 7967
7968 /* AER (Advanced Error Reporting) hooks */
7969 err = pci_enable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 7970 if (!err)
7971 bp->flags |= BNX2_FLAG_AER_ENABLED;
c239f279 7972
883e5151 7973 } else {
59b47d8a
MC		 7974 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7975 if (bp->pcix_cap == 0) {
7976 dev_err(&pdev->dev,
3a9c6a49 7977 "Cannot find PCIX capability, aborting\n");
59b47d8a
MC		 7978 rc = -EIO;
7979 goto err_out_unmap;
7980 }
61d9e3fa 7981 bp->flags |= BNX2_FLAG_BROKEN_STATS;
59b47d8a
MC		 7982 }
7983
b4b36042
MC		 7984 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7985 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 7986 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 7987 }
7988
8e6a72c4
MC		 7989 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7990 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 7991 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 7992 }
7993
40453c83
MC		 7994 /* 5708 cannot support DMA addresses > 40-bit. */
7995 if (CHIP_NUM(bp) == CHIP_NUM_5708)
50cf156a 7996 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
40453c83 7997 else
6a35528a 7998 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
40453c83
MC		 7999
8000 /* Configure DMA attributes. */
8001 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
8002 dev->features |= NETIF_F_HIGHDMA;
8003 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
8004 if (rc) {
8005 dev_err(&pdev->dev,
3a9c6a49 8006 "pci_set_consistent_dma_mask failed, aborting\n");
40453c83
MC		 8007 goto err_out_unmap;
8008 }
284901a9 8009 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3a9c6a49 8010 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
40453c83
MC		 8011 goto err_out_unmap;
8012 }
8013
f86e82fb 8014 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 8015 bnx2_get_pci_speed(bp);
b6016b76
MC		 8016
8017 /* 5706A0 may falsely detect SERR and PERR. */
8018 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8019 reg = REG_RD(bp, PCI_COMMAND);
8020 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
8021 REG_WR(bp, PCI_COMMAND, reg);
8022 }
8023 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 8024 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 8025
9b91cf9d 8026 dev_err(&pdev->dev,
3a9c6a49 8027 "5706 A1 can only be used in a PCIX bus, aborting\n");
b6016b76
MC		 8028 goto err_out_unmap;
8029 }
8030
8031 bnx2_init_nvram(bp);
8032
2726d6e1 8033 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 8034
8035 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 8036 BNX2_SHM_HDR_SIGNATURE_SIG) {
8037 u32 off = PCI_FUNC(pdev->devfn) << 2;
8038
2726d6e1 8039 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 8040 } else
e3648b3d
MC		 8041 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8042
b6016b76
MC		 8043 /* Get the permanent MAC address. First we need to make sure the
8044 * firmware is actually running.
8045 */
2726d6e1 8046 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 8047
8048 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8049 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
3a9c6a49 8050 dev_err(&pdev->dev, "Firmware not running, aborting\n");
b6016b76
MC		 8051 rc = -ENODEV;
8052 goto err_out_unmap;
8053 }
8054
76d99061
MC		 8055 bnx2_read_vpd_fw_ver(bp);
8056
8057 j = strlen(bp->fw_version);
2726d6e1 8058 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
76d99061 8059 for (i = 0; i < 3 && j < 24; i++) {
58fc2ea4
MC		 8060 u8 num, k, skip0;
8061
76d99061
MC		 8062 if (i == 0) {
8063 bp->fw_version[j++] = 'b';
8064 bp->fw_version[j++] = 'c';
8065 bp->fw_version[j++] = ' ';
8066 }
58fc2ea4
MC		 8067 num = (u8) (reg >> (24 - (i * 8)));
8068 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8069 if (num >= k || !skip0 || k == 1) {
8070 bp->fw_version[j++] = (num / k) + '0';
8071 skip0 = 0;
8072 }
8073 }
8074 if (i != 2)
8075 bp->fw_version[j++] = '.';
8076 }
2726d6e1 8077 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 8078 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8079 bp->wol = 1;
8080
8081 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 8082 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 8083
8084 for (i = 0; i < 30; i++) {
2726d6e1 8085 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 8086 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8087 break;
8088 msleep(10);
8089 }
8090 }
2726d6e1 8091 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 8092 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8093 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8094 reg != BNX2_CONDITION_MFW_RUN_NONE) {
2726d6e1 8095 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4 8096
76d99061
MC		 8097 if (j < 32)
8098 bp->fw_version[j++] = ' ';
8099 for (i = 0; i < 3 && j < 28; i++) {
2726d6e1 8100 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
3aeb7d22 8101 reg = be32_to_cpu(reg);
58fc2ea4
MC		 8102 memcpy(&bp->fw_version[j], &reg, 4);
8103 j += 4;
8104 }
8105 }
b6016b76 8106
2726d6e1 8107 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 8108 bp->mac_addr[0] = (u8) (reg >> 8);
8109 bp->mac_addr[1] = (u8) reg;
8110
2726d6e1 8111 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 8112 bp->mac_addr[2] = (u8) (reg >> 24);
8113 bp->mac_addr[3] = (u8) (reg >> 16);
8114 bp->mac_addr[4] = (u8) (reg >> 8);
8115 bp->mac_addr[5] = (u8) reg;
8116
8117 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 8118 bnx2_set_rx_ring_size(bp, 255);
b6016b76 8119
cf7474a6 8120 bp->tx_quick_cons_trip_int = 2;
b6016b76 8121 bp->tx_quick_cons_trip = 20;
cf7474a6 8122 bp->tx_ticks_int = 18;
b6016b76 8123 bp->tx_ticks = 80;
6aa20a22 8124
cf7474a6
MC		 8125 bp->rx_quick_cons_trip_int = 2;
8126 bp->rx_quick_cons_trip = 12;
b6016b76
MC		 8127 bp->rx_ticks_int = 18;
8128 bp->rx_ticks = 18;
8129
7ea6920e 8130 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76 8131
ac392abc 8132 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 8133
5b0c76ad
MC		 8134 bp->phy_addr = 1;
8135
b6016b76 8136 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 8137 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8138 bnx2_get_5709_media(bp);
8139 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 8140 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 8141
0d8a6571 8142 bp->phy_port = PORT_TP;
583c28e5 8143 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 8144 bp->phy_port = PORT_FIBRE;
2726d6e1 8145 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 8146 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 8147 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8148 bp->wol = 0;
8149 }
38ea3686
MC		 8150 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8151 /* Don't do parallel detect on this board because of
8152 * some board problems. The link will not go down
8153 * if we do parallel detect.
8154 */
8155 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8156 pdev->subsystem_device == 0x310c)
8157 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8158 } else {
5b0c76ad 8159 bp->phy_addr = 2;
5b0c76ad 8160 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 8161 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 8162 }
261dd5ca
MC		 8163 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8164 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 8165 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 8166 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8167 (CHIP_REV(bp) == CHIP_REV_Ax ||
8168 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 8169 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 8170
7c62e83b
MC		 8171 bnx2_init_fw_cap(bp);
8172
16088272
MC		 8173 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8174 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
5ec6d7bf
MC		 8175 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8176 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
f86e82fb 8177 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8178 bp->wol = 0;
8179 }
dda1e390 8180
b6016b76
MC		 8181 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8182 bp->tx_quick_cons_trip_int =
8183 bp->tx_quick_cons_trip;
8184 bp->tx_ticks_int = bp->tx_ticks;
8185 bp->rx_quick_cons_trip_int =
8186 bp->rx_quick_cons_trip;
8187 bp->rx_ticks_int = bp->rx_ticks;
8188 bp->comp_prod_trip_int = bp->comp_prod_trip;
8189 bp->com_ticks_int = bp->com_ticks;
8190 bp->cmd_ticks_int = bp->cmd_ticks;
8191 }
8192
f9317a40
MC		 8193 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8194 *
8195 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8196 * with byte enables disabled on the unused 32-bit word. This is legal
8197 * but causes problems on the AMD 8132 which will eventually stop
8198 * responding after a while.
8199 *
8200 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 8201 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 8202 */
8203 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8204 struct pci_dev *amd_8132 = NULL;
8205
8206 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8207 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8208 amd_8132))) {
f9317a40 8209
44c10138
AK		 8210 if (amd_8132->revision >= 0x10 &&
8211 amd_8132->revision <= 0x13) {
f9317a40
MC		 8212 disable_msi = 1;
8213 pci_dev_put(amd_8132);
8214 break;
8215 }
8216 }
8217 }
8218
deaf391b 8219 bnx2_set_default_link(bp);
b6016b76
MC		 8220 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8221
cd339a0e 8222 init_timer(&bp->timer);
ac392abc 8223 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
cd339a0e
MC		 8224 bp->timer.data = (unsigned long) bp;
8225 bp->timer.function = bnx2_timer;
8226
7625eb2f 8227#ifdef BCM_CNIC
41c2178a
MC		 8228 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
8229 bp->cnic_eth_dev.max_iscsi_conn =
8230 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
8231 BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT;
7625eb2f 8232#endif
c239f279
MC		 8233 pci_save_state(pdev);
8234
b6016b76
MC		 8235 return 0;
8236
8237err_out_unmap:
4bb9ebc7 8238 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
c239f279 8239 pci_disable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8240 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8241 }
c239f279 8242
b6016b76
MC		 8243 if (bp->regview) {
8244 iounmap(bp->regview);
73eef4cd 8245 bp->regview = NULL;
b6016b76
MC		 8246 }
8247
8248err_out_release:
8249 pci_release_regions(pdev);
8250
8251err_out_disable:
8252 pci_disable_device(pdev);
8253 pci_set_drvdata(pdev, NULL);
8254
8255err_out:
8256 return rc;
8257}
8258
883e5151
MC		 8259static char * __devinit
8260bnx2_bus_string(struct bnx2 *bp, char *str)
8261{
8262 char *s = str;
8263
f86e82fb 8264 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 8265 s += sprintf(s, "PCI Express");
8266 } else {
8267 s += sprintf(s, "PCI");
f86e82fb 8268 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 8269 s += sprintf(s, "-X");
f86e82fb 8270 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 8271 s += sprintf(s, " 32-bit");
8272 else
8273 s += sprintf(s, " 64-bit");
8274 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8275 }
8276 return str;
8277}
8278
f048fa9c
MC		 8279static void
8280bnx2_del_napi(struct bnx2 *bp)
8281{
8282 int i;
8283
8284 for (i = 0; i < bp->irq_nvecs; i++)
8285 netif_napi_del(&bp->bnx2_napi[i].napi);
8286}
8287
8288static void
35efa7c1
MC		 8289bnx2_init_napi(struct bnx2 *bp)
8290{
b4b36042 8291 int i;
35efa7c1 8292
4327ba43 8293 for (i = 0; i < bp->irq_nvecs; i++) {
35e9010b
MC		 8294 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8295 int (*poll)(struct napi_struct *, int);
8296
8297 if (i == 0)
8298 poll = bnx2_poll;
8299 else
f0ea2e63 8300 poll = bnx2_poll_msix;
35e9010b
MC		 8301
8302 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
b4b36042
MC		 8303 bnapi->bp = bp;
8304 }
35efa7c1
MC		 8305}
8306
0421eae6
SH		 8307static const struct net_device_ops bnx2_netdev_ops = {
8308 .ndo_open = bnx2_open,
8309 .ndo_start_xmit = bnx2_start_xmit,
8310 .ndo_stop = bnx2_close,
5d07bf26 8311 .ndo_get_stats64 = bnx2_get_stats64,
0421eae6
SH		 8312 .ndo_set_rx_mode = bnx2_set_rx_mode,
8313 .ndo_do_ioctl = bnx2_ioctl,
8314 .ndo_validate_addr = eth_validate_addr,
8315 .ndo_set_mac_address = bnx2_change_mac_addr,
8316 .ndo_change_mtu = bnx2_change_mtu,
8d7dfc2b
MM		 8317 .ndo_fix_features = bnx2_fix_features,
8318 .ndo_set_features = bnx2_set_features,
0421eae6 8319 .ndo_tx_timeout = bnx2_tx_timeout,
257ddbda 8320#ifdef CONFIG_NET_POLL_CONTROLLER
0421eae6
SH		 8321 .ndo_poll_controller = poll_bnx2,
8322#endif
8323};
8324
b6016b76
MC		 8325static int __devinit
8326bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8327{
8328 static int version_printed = 0;
8329 struct net_device *dev = NULL;
8330 struct bnx2 *bp;
0795af57 8331 int rc;
883e5151 8332 char str[40];
b6016b76
MC		 8333
8334 if (version_printed++ == 0)
3a9c6a49 8335 pr_info("%s", version);
b6016b76
MC		 8336
8337 /* dev zeroed in init_etherdev */
706bf240 8338 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
b6016b76
MC		 8339
8340 if (!dev)
8341 return -ENOMEM;
8342
8343 rc = bnx2_init_board(pdev, dev);
8344 if (rc < 0) {
8345 free_netdev(dev);
8346 return rc;
8347 }
8348
0421eae6 8349 dev->netdev_ops = &bnx2_netdev_ops;
b6016b76 8350 dev->watchdog_timeo = TX_TIMEOUT;
b6016b76 8351 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 8352
972ec0d4 8353 bp = netdev_priv(dev);
b6016b76 8354
1b2f922f
MC		 8355 pci_set_drvdata(pdev, dev);
8356
57579f76
MC		 8357 rc = bnx2_request_firmware(bp);
8358 if (rc)
8359 goto error;
8360
1b2f922f
MC		 8361 memcpy(dev->dev_addr, bp->mac_addr, 6);
8362 memcpy(dev->perm_addr, bp->mac_addr, 6);
1b2f922f 8363
8d7dfc2b
MM		 8364 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
8365 NETIF_F_TSO | NETIF_F_TSO_ECN |
8366 NETIF_F_RXHASH | NETIF_F_RXCSUM;
8367
8368 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8369 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8370
8371 dev->vlan_features = dev->hw_features;
8372 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8373 dev->features |= dev->hw_features;
01789349 8374 dev->priv_flags |= IFF_UNICAST_FLT;
8d7dfc2b 8375
b6016b76 8376 if ((rc = register_netdev(dev))) {
9b91cf9d 8377 dev_err(&pdev->dev, "Cannot register net device\n");
57579f76 8378 goto error;
b6016b76
MC		 8379 }
8380
3a9c6a49
JP		 8381 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8382 board_info[ent->driver_data].name,
8383 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8384 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8385 bnx2_bus_string(bp, str),
8386 dev->base_addr,
8387 bp->pdev->irq, dev->dev_addr);
b6016b76 8388
b6016b76 8389 return 0;
57579f76
MC		 8390
8391error:
8392 if (bp->mips_firmware)
8393 release_firmware(bp->mips_firmware);
8394 if (bp->rv2p_firmware)
8395 release_firmware(bp->rv2p_firmware);
8396
8397 if (bp->regview)
8398 iounmap(bp->regview);
8399 pci_release_regions(pdev);
8400 pci_disable_device(pdev);
8401 pci_set_drvdata(pdev, NULL);
8402 free_netdev(dev);
8403 return rc;
b6016b76
MC		 8404}
8405
8406static void __devexit
8407bnx2_remove_one(struct pci_dev *pdev)
8408{
8409 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8410 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 8411
8412 unregister_netdev(dev);
8413
8333a46a 8414 del_timer_sync(&bp->timer);
cd634019 8415 cancel_work_sync(&bp->reset_task);
8333a46a 8416
57579f76
MC		 8417 if (bp->mips_firmware)
8418 release_firmware(bp->mips_firmware);
8419 if (bp->rv2p_firmware)
8420 release_firmware(bp->rv2p_firmware);
8421
b6016b76
MC		 8422 if (bp->regview)
8423 iounmap(bp->regview);
8424
354fcd77
MC		 8425 kfree(bp->temp_stats_blk);
8426
4bb9ebc7 8427 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
c239f279 8428 pci_disable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8429 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8430 }
cd709aa9 8431
c239f279 8432 free_netdev(dev);
cd709aa9 8433
b6016b76
MC		 8434 pci_release_regions(pdev);
8435 pci_disable_device(pdev);
8436 pci_set_drvdata(pdev, NULL);
8437}
8438
8439static int
829ca9a3 8440bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 8441{
8442 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8443 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8444
6caebb02
MC		 8445 /* PCI register 4 needs to be saved whether netif_running() or not.
8446 * MSI address and data need to be saved if using MSI and
8447 * netif_running().
8448 */
8449 pci_save_state(pdev);
b6016b76
MC		 8450 if (!netif_running(dev))
8451 return 0;
8452
23f333a2 8453 cancel_work_sync(&bp->reset_task);
212f9934 8454 bnx2_netif_stop(bp, true);
b6016b76
MC		 8455 netif_device_detach(dev);
8456 del_timer_sync(&bp->timer);
74bf4ba3 8457 bnx2_shutdown_chip(bp);
b6016b76 8458 bnx2_free_skbs(bp);
829ca9a3 8459 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 8460 return 0;
8461}
8462
8463static int
8464bnx2_resume(struct pci_dev *pdev)
8465{
8466 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8467 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8468
6caebb02 8469 pci_restore_state(pdev);
b6016b76
MC		 8470 if (!netif_running(dev))
8471 return 0;
8472
829ca9a3 8473 bnx2_set_power_state(bp, PCI_D0);
b6016b76 8474 netif_device_attach(dev);
9a120bc5 8475 bnx2_init_nic(bp, 1);
212f9934 8476 bnx2_netif_start(bp, true);
b6016b76
MC		 8477 return 0;
8478}
8479
6ff2da49
WX		 8480/**
8481 * bnx2_io_error_detected - called when PCI error is detected
8482 * @pdev: Pointer to PCI device
8483 * @state: The current pci connection state
8484 *
8485 * This function is called after a PCI bus error affecting
8486 * this device has been detected.
8487 */
8488static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8489 pci_channel_state_t state)
8490{
8491 struct net_device *dev = pci_get_drvdata(pdev);
8492 struct bnx2 *bp = netdev_priv(dev);
8493
8494 rtnl_lock();
8495 netif_device_detach(dev);
8496
2ec3de26
DN		 8497 if (state == pci_channel_io_perm_failure) {
8498 rtnl_unlock();
8499 return PCI_ERS_RESULT_DISCONNECT;
8500 }
8501
6ff2da49 8502 if (netif_running(dev)) {
212f9934 8503 bnx2_netif_stop(bp, true);
6ff2da49
WX		 8504 del_timer_sync(&bp->timer);
8505 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8506 }
8507
8508 pci_disable_device(pdev);
8509 rtnl_unlock();
8510
8511 /* Request a slot slot reset. */
8512 return PCI_ERS_RESULT_NEED_RESET;
8513}
8514
8515/**
8516 * bnx2_io_slot_reset - called after the pci bus has been reset.
8517 * @pdev: Pointer to PCI device
8518 *
8519 * Restart the card from scratch, as if from a cold-boot.
8520 */
8521static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8522{
8523 struct net_device *dev = pci_get_drvdata(pdev);
8524 struct bnx2 *bp = netdev_priv(dev);
cd709aa9
JF		 8525 pci_ers_result_t result;
8526 int err;
6ff2da49
WX		 8527
8528 rtnl_lock();
8529 if (pci_enable_device(pdev)) {
8530 dev_err(&pdev->dev,
3a9c6a49 8531 "Cannot re-enable PCI device after reset\n");
cd709aa9
JF		 8532 result = PCI_ERS_RESULT_DISCONNECT;
8533 } else {
8534 pci_set_master(pdev);
8535 pci_restore_state(pdev);
8536 pci_save_state(pdev);
8537
8538 if (netif_running(dev)) {
8539 bnx2_set_power_state(bp, PCI_D0);
8540 bnx2_init_nic(bp, 1);
8541 }
8542 result = PCI_ERS_RESULT_RECOVERED;
6ff2da49 8543 }
cd709aa9 8544 rtnl_unlock();
6ff2da49 8545
4bb9ebc7 8546 if (!(bp->flags & BNX2_FLAG_AER_ENABLED))
c239f279
MC		 8547 return result;
8548
cd709aa9
JF		 8549 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8550 if (err) {
8551 dev_err(&pdev->dev,
8552 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8553 err); /* non-fatal, continue */
6ff2da49
WX		 8554 }
8555
cd709aa9 8556 return result;
6ff2da49
WX		 8557}
8558
8559/**
8560 * bnx2_io_resume - called when traffic can start flowing again.
8561 * @pdev: Pointer to PCI device
8562 *
8563 * This callback is called when the error recovery driver tells us that
8564 * its OK to resume normal operation.
8565 */
8566static void bnx2_io_resume(struct pci_dev *pdev)
8567{
8568 struct net_device *dev = pci_get_drvdata(pdev);
8569 struct bnx2 *bp = netdev_priv(dev);
8570
8571 rtnl_lock();
8572 if (netif_running(dev))
212f9934 8573 bnx2_netif_start(bp, true);
6ff2da49
WX		 8574
8575 netif_device_attach(dev);
8576 rtnl_unlock();
8577}
8578
8579static struct pci_error_handlers bnx2_err_handler = {
8580 .error_detected = bnx2_io_error_detected,
8581 .slot_reset = bnx2_io_slot_reset,
8582 .resume = bnx2_io_resume,
8583};
8584
b6016b76 8585static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 8586 .name = DRV_MODULE_NAME,
8587 .id_table = bnx2_pci_tbl,
8588 .probe = bnx2_init_one,
8589 .remove = __devexit_p(bnx2_remove_one),
8590 .suspend = bnx2_suspend,
8591 .resume = bnx2_resume,
6ff2da49 8592 .err_handler = &bnx2_err_handler,
b6016b76
MC		 8593};
8594
8595static int __init bnx2_init(void)
8596{
29917620 8597 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 8598}
8599
8600static void __exit bnx2_cleanup(void)
8601{
8602 pci_unregister_driver(&bnx2_pci_driver);
8603}
8604
8605module_init(bnx2_init);
8606module_exit(bnx2_cleanup);
8607
8608
8609
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