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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
dc187cb3 3 * Copyright (c) 2004-2011 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
3a9c6a49 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
f2a4f052
MC		 13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16
17#include <linux/kernel.h>
18#include <linux/timer.h>
19#include <linux/errno.h>
20#include <linux/ioport.h>
21#include <linux/slab.h>
22#include <linux/vmalloc.h>
23#include <linux/interrupt.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28#include <linux/skbuff.h>
29#include <linux/dma-mapping.h>
1977f032 30#include <linux/bitops.h>
f2a4f052
MC		 31#include <asm/io.h>
32#include <asm/irq.h>
33#include <linux/delay.h>
34#include <asm/byteorder.h>
c86a31f4 35#include <asm/page.h>
f2a4f052
MC		 36#include <linux/time.h>
37#include <linux/ethtool.h>
38#include <linux/mii.h>
01789349 39#include <linux/if.h>
f2a4f052 40#include <linux/if_vlan.h>
f2a4f052 41#include <net/ip.h>
de081fa5 42#include <net/tcp.h>
f2a4f052 43#include <net/checksum.h>
f2a4f052
MC		 44#include <linux/workqueue.h>
45#include <linux/crc32.h>
46#include <linux/prefetch.h>
29b12174 47#include <linux/cache.h>
57579f76 48#include <linux/firmware.h>
706bf240 49#include <linux/log2.h>
cd709aa9 50#include <linux/aer.h>
f2a4f052 51
4edd473f
MC		 52#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
53#define BCM_CNIC 1
54#include "cnic_if.h"
55#endif
b6016b76
MC		 56#include "bnx2.h"
57#include "bnx2_fw.h"
b3448b0b 58
b6016b76 59#define DRV_MODULE_NAME "bnx2"
3aeb7d22
MC		 60#define DRV_MODULE_VERSION "2.1.11"
61#define DRV_MODULE_RELDATE "July 20, 2011"
0268102d 62#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.1.fw"
22fa159d 63#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
dc187cb3 64#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1a.fw"
22fa159d
MC		 65#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
66#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
b6016b76
MC		 67
68#define RUN_AT(x) (jiffies + (x))
69
70/* Time in jiffies before concluding the transmitter is hung. */
71#define TX_TIMEOUT (5*HZ)
72
fefa8645 73static char version[] __devinitdata =
b6016b76
MC		 74 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
75
76MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
453a9c6e 77MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
b6016b76
MC		 78MODULE_LICENSE("GPL");
79MODULE_VERSION(DRV_MODULE_VERSION);
57579f76
MC		 80MODULE_FIRMWARE(FW_MIPS_FILE_06);
81MODULE_FIRMWARE(FW_RV2P_FILE_06);
82MODULE_FIRMWARE(FW_MIPS_FILE_09);
83MODULE_FIRMWARE(FW_RV2P_FILE_09);
078b0735 84MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
b6016b76
MC		 85
86static int disable_msi = 0;
87
88module_param(disable_msi, int, 0);
89MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
90
91typedef enum {
92 BCM5706 = 0,
93 NC370T,
94 NC370I,
95 BCM5706S,
96 NC370F,
5b0c76ad
MC		 97 BCM5708,
98 BCM5708S,
bac0dff6 99 BCM5709,
27a005b8 100 BCM5709S,
7bb0a04f 101 BCM5716,
1caacecb 102 BCM5716S,
b6016b76
MC		 103} board_t;
104
105/* indexed by board_t, above */
fefa8645 106static struct {
b6016b76
MC		 107 char *name;
108} board_info[] __devinitdata = {
109 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
110 { "HP NC370T Multifunction Gigabit Server Adapter" },
111 { "HP NC370i Multifunction Gigabit Server Adapter" },
112 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
113 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 114 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
115 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 116 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 117 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
7bb0a04f 118 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
1caacecb 119 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
b6016b76
MC		 120 };
121
7bb0a04f 122static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
b6016b76
MC		 123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
124 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
126 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
132 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
133 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 135 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 137 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 139 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
7bb0a04f
MC		 141 { PCI_VENDOR_ID_BROADCOM, 0x163b,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
1caacecb 143 { PCI_VENDOR_ID_BROADCOM, 0x163c,
1f2435e5 144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
b6016b76
MC		 145 { 0, }
146};
147
0ced9d01 148static const struct flash_spec flash_table[] =
b6016b76 149{
e30372c9
MC		 150#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
151#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 152 /* Slow EEPROM */
37137709 153 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 154 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 155 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
156 "EEPROM - slow"},
37137709
MC		 157 /* Expansion entry 0001 */
158 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 159 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 160 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
161 "Entry 0001"},
b6016b76
MC		 162 /* Saifun SA25F010 (non-buffered flash) */
163 /* strap, cfg1, & write1 need updates */
37137709 164 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 165 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 166 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
167 "Non-buffered flash (128kB)"},
168 /* Saifun SA25F020 (non-buffered flash) */
169 /* strap, cfg1, & write1 need updates */
37137709 170 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 171 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 172 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
173 "Non-buffered flash (256kB)"},
37137709
MC		 174 /* Expansion entry 0100 */
175 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
178 "Entry 0100"},
179 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 180 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 181 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 182 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
183 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
184 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
185 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 186 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 187 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
188 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
189 /* Saifun SA25F005 (non-buffered flash) */
190 /* strap, cfg1, & write1 need updates */
191 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 192 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 193 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
194 "Non-buffered flash (64kB)"},
195 /* Fast EEPROM */
196 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 197 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 198 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
199 "EEPROM - fast"},
200 /* Expansion entry 1001 */
201 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 202 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 203 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
204 "Entry 1001"},
205 /* Expansion entry 1010 */
206 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 208 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
209 "Entry 1010"},
210 /* ATMEL AT45DB011B (buffered flash) */
211 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 212 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 213 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
214 "Buffered flash (128kB)"},
215 /* Expansion entry 1100 */
216 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 217 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 218 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
219 "Entry 1100"},
220 /* Expansion entry 1101 */
221 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 222 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 223 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
224 "Entry 1101"},
225 /* Ateml Expansion entry 1110 */
226 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 227 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 228 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
229 "Entry 1110 (Atmel)"},
230 /* ATMEL AT45DB021B (buffered flash) */
231 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 232 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 233 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
234 "Buffered flash (256kB)"},
b6016b76
MC		 235};
236
0ced9d01 237static const struct flash_spec flash_5709 = {
e30372c9
MC		 238 .flags = BNX2_NV_BUFFERED,
239 .page_bits = BCM5709_FLASH_PAGE_BITS,
240 .page_size = BCM5709_FLASH_PAGE_SIZE,
241 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
242 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
243 .name = "5709 Buffered flash (256kB)",
244};
245
b6016b76
MC		 246MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
247
4327ba43 248static void bnx2_init_napi(struct bnx2 *bp);
f048fa9c 249static void bnx2_del_napi(struct bnx2 *bp);
4327ba43 250
35e9010b 251static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
e89bbf10 252{
2f8af120 253 u32 diff;
e89bbf10 254
11848b96
MC		 255 /* Tell compiler to fetch tx_prod and tx_cons from memory. */
256 barrier();
faac9c4b
MC		 257
258 /* The ring uses 256 indices for 255 entries, one of them
259 * needs to be skipped.
260 */
35e9010b 261 diff = txr->tx_prod - txr->tx_cons;
faac9c4b
MC		 262 if (unlikely(diff >= TX_DESC_CNT)) {
263 diff &= 0xffff;
264 if (diff == TX_DESC_CNT)
265 diff = MAX_TX_DESC_CNT;
266 }
807540ba 267 return bp->tx_ring_size - diff;
e89bbf10
MC		 268}
269
b6016b76
MC		 270static u32
271bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
272{
1b8227c4
MC		 273 u32 val;
274
275 spin_lock_bh(&bp->indirect_lock);
b6016b76 276 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 277 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
278 spin_unlock_bh(&bp->indirect_lock);
279 return val;
b6016b76
MC		 280}
281
282static void
283bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
284{
1b8227c4 285 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 288 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 289}
290
2726d6e1
MC		 291static void
292bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
293{
294 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
295}
296
297static u32
298bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
299{
807540ba 300 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
2726d6e1
MC		 301}
302
b6016b76
MC		 303static void
304bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
305{
306 offset += cid_addr;
1b8227c4 307 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 308 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
309 int i;
310
311 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
312 REG_WR(bp, BNX2_CTX_CTX_CTRL,
313 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
314 for (i = 0; i < 5; i++) {
59b47d8a
MC		 315 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
316 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
317 break;
318 udelay(5);
319 }
320 } else {
321 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
322 REG_WR(bp, BNX2_CTX_DATA, val);
323 }
1b8227c4 324 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 325}
326
4edd473f
MC		 327#ifdef BCM_CNIC
328static int
329bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
330{
331 struct bnx2 *bp = netdev_priv(dev);
332 struct drv_ctl_io *io = &info->data.io;
333
334 switch (info->cmd) {
335 case DRV_CTL_IO_WR_CMD:
336 bnx2_reg_wr_ind(bp, io->offset, io->data);
337 break;
338 case DRV_CTL_IO_RD_CMD:
339 io->data = bnx2_reg_rd_ind(bp, io->offset);
340 break;
341 case DRV_CTL_CTX_WR_CMD:
342 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
343 break;
344 default:
345 return -EINVAL;
346 }
347 return 0;
348}
349
350static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
351{
352 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
353 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
354 int sb_id;
355
356 if (bp->flags & BNX2_FLAG_USING_MSIX) {
357 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
358 bnapi->cnic_present = 0;
359 sb_id = bp->irq_nvecs;
360 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
361 } else {
362 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
363 bnapi->cnic_tag = bnapi->last_status_idx;
364 bnapi->cnic_present = 1;
365 sb_id = 0;
366 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
367 }
368
369 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
370 cp->irq_arr[0].status_blk = (void *)
371 ((unsigned long) bnapi->status_blk.msi +
372 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
373 cp->irq_arr[0].status_blk_num = sb_id;
374 cp->num_irq = 1;
375}
376
377static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
378 void *data)
379{
380 struct bnx2 *bp = netdev_priv(dev);
381 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
382
383 if (ops == NULL)
384 return -EINVAL;
385
386 if (cp->drv_state & CNIC_DRV_STATE_REGD)
387 return -EBUSY;
388
41c2178a
MC		 389 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))
390 return -ENODEV;
391
4edd473f
MC		 392 bp->cnic_data = data;
393 rcu_assign_pointer(bp->cnic_ops, ops);
394
395 cp->num_irq = 0;
396 cp->drv_state = CNIC_DRV_STATE_REGD;
397
398 bnx2_setup_cnic_irq_info(bp);
399
400 return 0;
401}
402
403static int bnx2_unregister_cnic(struct net_device *dev)
404{
405 struct bnx2 *bp = netdev_priv(dev);
406 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
407 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
408
c5a88950 409 mutex_lock(&bp->cnic_lock);
4edd473f
MC		 410 cp->drv_state = 0;
411 bnapi->cnic_present = 0;
412 rcu_assign_pointer(bp->cnic_ops, NULL);
c5a88950 413 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 414 synchronize_rcu();
415 return 0;
416}
417
418struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
419{
420 struct bnx2 *bp = netdev_priv(dev);
421 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
422
7625eb2f
MC		 423 if (!cp->max_iscsi_conn)
424 return NULL;
425
4edd473f
MC		 426 cp->drv_owner = THIS_MODULE;
427 cp->chip_id = bp->chip_id;
428 cp->pdev = bp->pdev;
429 cp->io_base = bp->regview;
430 cp->drv_ctl = bnx2_drv_ctl;
431 cp->drv_register_cnic = bnx2_register_cnic;
432 cp->drv_unregister_cnic = bnx2_unregister_cnic;
433
434 return cp;
435}
436EXPORT_SYMBOL(bnx2_cnic_probe);
437
438static void
439bnx2_cnic_stop(struct bnx2 *bp)
440{
441 struct cnic_ops *c_ops;
442 struct cnic_ctl_info info;
443
c5a88950 444 mutex_lock(&bp->cnic_lock);
13707f9e
ED		 445 c_ops = rcu_dereference_protected(bp->cnic_ops,
446 lockdep_is_held(&bp->cnic_lock));
4edd473f
MC		 447 if (c_ops) {
448 info.cmd = CNIC_CTL_STOP_CMD;
449 c_ops->cnic_ctl(bp->cnic_data, &info);
450 }
c5a88950 451 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 452}
453
454static void
455bnx2_cnic_start(struct bnx2 *bp)
456{
457 struct cnic_ops *c_ops;
458 struct cnic_ctl_info info;
459
c5a88950 460 mutex_lock(&bp->cnic_lock);
13707f9e
ED		 461 c_ops = rcu_dereference_protected(bp->cnic_ops,
462 lockdep_is_held(&bp->cnic_lock));
4edd473f
MC		 463 if (c_ops) {
464 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
465 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
466
467 bnapi->cnic_tag = bnapi->last_status_idx;
468 }
469 info.cmd = CNIC_CTL_START_CMD;
470 c_ops->cnic_ctl(bp->cnic_data, &info);
471 }
c5a88950 472 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 473}
474
475#else
476
477static void
478bnx2_cnic_stop(struct bnx2 *bp)
479{
480}
481
482static void
483bnx2_cnic_start(struct bnx2 *bp)
484{
485}
486
487#endif
488
b6016b76
MC		 489static int
490bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
491{
492 u32 val1;
493 int i, ret;
494
583c28e5 495 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 496 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
497 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
498
499 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
500 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
501
502 udelay(40);
503 }
504
505 val1 = (bp->phy_addr << 21) | (reg << 16) |
506 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
507 BNX2_EMAC_MDIO_COMM_START_BUSY;
508 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
509
510 for (i = 0; i < 50; i++) {
511 udelay(10);
512
513 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
514 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
515 udelay(5);
516
517 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
518 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
519
520 break;
521 }
522 }
523
524 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
525 *val = 0x0;
526 ret = -EBUSY;
527 }
528 else {
529 *val = val1;
530 ret = 0;
531 }
532
583c28e5 533 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 534 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
535 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
536
537 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
538 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
539
540 udelay(40);
541 }
542
543 return ret;
544}
545
546static int
547bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
548{
549 u32 val1;
550 int i, ret;
551
583c28e5 552 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 553 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
554 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
555
556 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
557 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
558
559 udelay(40);
560 }
561
562 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
563 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
564 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
565 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 566
b6016b76
MC		 567 for (i = 0; i < 50; i++) {
568 udelay(10);
569
570 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
571 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
572 udelay(5);
573 break;
574 }
575 }
576
577 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
578 ret = -EBUSY;
579 else
580 ret = 0;
581
583c28e5 582 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 583 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
584 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
585
586 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
587 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
588
589 udelay(40);
590 }
591
592 return ret;
593}
594
595static void
596bnx2_disable_int(struct bnx2 *bp)
597{
b4b36042
MC		 598 int i;
599 struct bnx2_napi *bnapi;
600
601 for (i = 0; i < bp->irq_nvecs; i++) {
602 bnapi = &bp->bnx2_napi[i];
603 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
604 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
605 }
b6016b76
MC		 606 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
607}
608
609static void
610bnx2_enable_int(struct bnx2 *bp)
611{
b4b36042
MC		 612 int i;
613 struct bnx2_napi *bnapi;
35efa7c1 614
b4b36042
MC		 615 for (i = 0; i < bp->irq_nvecs; i++) {
616 bnapi = &bp->bnx2_napi[i];
1269a8a6 617
b4b36042
MC		 618 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
619 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
620 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
621 bnapi->last_status_idx);
b6016b76 622
b4b36042
MC		 623 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
624 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
625 bnapi->last_status_idx);
626 }
bf5295bb 627 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 628}
629
630static void
631bnx2_disable_int_sync(struct bnx2 *bp)
632{
b4b36042
MC		 633 int i;
634
b6016b76 635 atomic_inc(&bp->intr_sem);
3767546c
MC		 636 if (!netif_running(bp->dev))
637 return;
638
b6016b76 639 bnx2_disable_int(bp);
b4b36042
MC		 640 for (i = 0; i < bp->irq_nvecs; i++)
641 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 642}
643
35efa7c1
MC		 644static void
645bnx2_napi_disable(struct bnx2 *bp)
646{
b4b36042
MC		 647 int i;
648
649 for (i = 0; i < bp->irq_nvecs; i++)
650 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 651}
652
653static void
654bnx2_napi_enable(struct bnx2 *bp)
655{
b4b36042
MC		 656 int i;
657
658 for (i = 0; i < bp->irq_nvecs; i++)
659 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 660}
661
b6016b76 662static void
212f9934 663bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
b6016b76 664{
212f9934
MC		 665 if (stop_cnic)
666 bnx2_cnic_stop(bp);
b6016b76 667 if (netif_running(bp->dev)) {
35efa7c1 668 bnx2_napi_disable(bp);
b6016b76 669 netif_tx_disable(bp->dev);
b6016b76 670 }
b7466560 671 bnx2_disable_int_sync(bp);
a0ba6760 672 netif_carrier_off(bp->dev); /* prevent tx timeout */
b6016b76
MC		 673}
674
675static void
212f9934 676bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
b6016b76
MC		 677{
678 if (atomic_dec_and_test(&bp->intr_sem)) {
679 if (netif_running(bp->dev)) {
706bf240 680 netif_tx_wake_all_queues(bp->dev);
a0ba6760
MC		 681 spin_lock_bh(&bp->phy_lock);
682 if (bp->link_up)
683 netif_carrier_on(bp->dev);
684 spin_unlock_bh(&bp->phy_lock);
35efa7c1 685 bnx2_napi_enable(bp);
b6016b76 686 bnx2_enable_int(bp);
212f9934
MC		 687 if (start_cnic)
688 bnx2_cnic_start(bp);
b6016b76
MC		 689 }
690 }
691}
692
35e9010b
MC		 693static void
694bnx2_free_tx_mem(struct bnx2 *bp)
695{
696 int i;
697
698 for (i = 0; i < bp->num_tx_rings; i++) {
699 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
700 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
701
702 if (txr->tx_desc_ring) {
36227e88
SG		 703 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
704 txr->tx_desc_ring,
705 txr->tx_desc_mapping);
35e9010b
MC		 706 txr->tx_desc_ring = NULL;
707 }
708 kfree(txr->tx_buf_ring);
709 txr->tx_buf_ring = NULL;
710 }
711}
712
bb4f98ab
MC		 713static void
714bnx2_free_rx_mem(struct bnx2 *bp)
715{
716 int i;
717
718 for (i = 0; i < bp->num_rx_rings; i++) {
719 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
720 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
721 int j;
722
723 for (j = 0; j < bp->rx_max_ring; j++) {
724 if (rxr->rx_desc_ring[j])
36227e88
SG		 725 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
726 rxr->rx_desc_ring[j],
727 rxr->rx_desc_mapping[j]);
bb4f98ab
MC		 728 rxr->rx_desc_ring[j] = NULL;
729 }
25b0b999 730 vfree(rxr->rx_buf_ring);
bb4f98ab
MC		 731 rxr->rx_buf_ring = NULL;
732
733 for (j = 0; j < bp->rx_max_pg_ring; j++) {
734 if (rxr->rx_pg_desc_ring[j])
36227e88
SG		 735 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
736 rxr->rx_pg_desc_ring[j],
737 rxr->rx_pg_desc_mapping[j]);
3298a738 738 rxr->rx_pg_desc_ring[j] = NULL;
bb4f98ab 739 }
25b0b999 740 vfree(rxr->rx_pg_ring);
bb4f98ab
MC		 741 rxr->rx_pg_ring = NULL;
742 }
743}
744
35e9010b
MC		 745static int
746bnx2_alloc_tx_mem(struct bnx2 *bp)
747{
748 int i;
749
750 for (i = 0; i < bp->num_tx_rings; i++) {
751 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
752 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
753
754 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
755 if (txr->tx_buf_ring == NULL)
756 return -ENOMEM;
757
758 txr->tx_desc_ring =
36227e88
SG		 759 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
760 &txr->tx_desc_mapping, GFP_KERNEL);
35e9010b
MC		 761 if (txr->tx_desc_ring == NULL)
762 return -ENOMEM;
763 }
764 return 0;
765}
766
bb4f98ab
MC		 767static int
768bnx2_alloc_rx_mem(struct bnx2 *bp)
769{
770 int i;
771
772 for (i = 0; i < bp->num_rx_rings; i++) {
773 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
774 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
775 int j;
776
777 rxr->rx_buf_ring =
89bf67f1 778 vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
bb4f98ab
MC		 779 if (rxr->rx_buf_ring == NULL)
780 return -ENOMEM;
781
bb4f98ab
MC		 782 for (j = 0; j < bp->rx_max_ring; j++) {
783 rxr->rx_desc_ring[j] =
36227e88
SG		 784 dma_alloc_coherent(&bp->pdev->dev,
785 RXBD_RING_SIZE,
786 &rxr->rx_desc_mapping[j],
787 GFP_KERNEL);
bb4f98ab
MC		 788 if (rxr->rx_desc_ring[j] == NULL)
789 return -ENOMEM;
790
791 }
792
793 if (bp->rx_pg_ring_size) {
89bf67f1 794 rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE *
bb4f98ab
MC		 795 bp->rx_max_pg_ring);
796 if (rxr->rx_pg_ring == NULL)
797 return -ENOMEM;
798
bb4f98ab
MC		 799 }
800
801 for (j = 0; j < bp->rx_max_pg_ring; j++) {
802 rxr->rx_pg_desc_ring[j] =
36227e88
SG		 803 dma_alloc_coherent(&bp->pdev->dev,
804 RXBD_RING_SIZE,
805 &rxr->rx_pg_desc_mapping[j],
806 GFP_KERNEL);
bb4f98ab
MC		 807 if (rxr->rx_pg_desc_ring[j] == NULL)
808 return -ENOMEM;
809
810 }
811 }
812 return 0;
813}
814
b6016b76
MC		 815static void
816bnx2_free_mem(struct bnx2 *bp)
817{
13daffa2 818 int i;
43e80b89 819 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
13daffa2 820
35e9010b 821 bnx2_free_tx_mem(bp);
bb4f98ab 822 bnx2_free_rx_mem(bp);
35e9010b 823
59b47d8a
MC		 824 for (i = 0; i < bp->ctx_pages; i++) {
825 if (bp->ctx_blk[i]) {
36227e88
SG		 826 dma_free_coherent(&bp->pdev->dev, BCM_PAGE_SIZE,
827 bp->ctx_blk[i],
828 bp->ctx_blk_mapping[i]);
59b47d8a
MC		 829 bp->ctx_blk[i] = NULL;
830 }
831 }
43e80b89 832 if (bnapi->status_blk.msi) {
36227e88
SG		 833 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
834 bnapi->status_blk.msi,
835 bp->status_blk_mapping);
43e80b89 836 bnapi->status_blk.msi = NULL;
0f31f994 837 bp->stats_blk = NULL;
b6016b76 838 }
b6016b76
MC		 839}
840
841static int
842bnx2_alloc_mem(struct bnx2 *bp)
843{
35e9010b 844 int i, status_blk_size, err;
43e80b89
MC		 845 struct bnx2_napi *bnapi;
846 void *status_blk;
b6016b76 847
0f31f994
MC		 848 /* Combine status and statistics blocks into one allocation. */
849 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 850 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 851 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
852 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 853 bp->status_stats_size = status_blk_size +
854 sizeof(struct statistics_block);
855
36227e88
SG		 856 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
857 &bp->status_blk_mapping, GFP_KERNEL);
43e80b89 858 if (status_blk == NULL)
b6016b76
MC		 859 goto alloc_mem_err;
860
43e80b89 861 memset(status_blk, 0, bp->status_stats_size);
b6016b76 862
43e80b89
MC		 863 bnapi = &bp->bnx2_napi[0];
864 bnapi->status_blk.msi = status_blk;
865 bnapi->hw_tx_cons_ptr =
866 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
867 bnapi->hw_rx_cons_ptr =
868 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
f86e82fb 869 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
379b39a2 870 for (i = 1; i < bp->irq_nvecs; i++) {
43e80b89
MC		 871 struct status_block_msix *sblk;
872
873 bnapi = &bp->bnx2_napi[i];
b4b36042 874
43e80b89
MC		 875 sblk = (void *) (status_blk +
876 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
877 bnapi->status_blk.msix = sblk;
878 bnapi->hw_tx_cons_ptr =
879 &sblk->status_tx_quick_consumer_index;
880 bnapi->hw_rx_cons_ptr =
881 &sblk->status_rx_quick_consumer_index;
b4b36042
MC		 882 bnapi->int_num = i << 24;
883 }
884 }
35efa7c1 885
43e80b89 886 bp->stats_blk = status_blk + status_blk_size;
b6016b76 887
0f31f994 888 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 889
59b47d8a
MC		 890 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
891 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
892 if (bp->ctx_pages == 0)
893 bp->ctx_pages = 1;
894 for (i = 0; i < bp->ctx_pages; i++) {
36227e88 895 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
59b47d8a 896 BCM_PAGE_SIZE,
36227e88
SG		 897 &bp->ctx_blk_mapping[i],
898 GFP_KERNEL);
59b47d8a
MC		 899 if (bp->ctx_blk[i] == NULL)
900 goto alloc_mem_err;
901 }
902 }
35e9010b 903
bb4f98ab
MC		 904 err = bnx2_alloc_rx_mem(bp);
905 if (err)
906 goto alloc_mem_err;
907
35e9010b
MC		 908 err = bnx2_alloc_tx_mem(bp);
909 if (err)
910 goto alloc_mem_err;
911
b6016b76
MC		 912 return 0;
913
914alloc_mem_err:
915 bnx2_free_mem(bp);
916 return -ENOMEM;
917}
918
e3648b3d
MC		 919static void
920bnx2_report_fw_link(struct bnx2 *bp)
921{
922 u32 fw_link_status = 0;
923
583c28e5 924 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 925 return;
926
e3648b3d
MC		 927 if (bp->link_up) {
928 u32 bmsr;
929
930 switch (bp->line_speed) {
931 case SPEED_10:
932 if (bp->duplex == DUPLEX_HALF)
933 fw_link_status = BNX2_LINK_STATUS_10HALF;
934 else
935 fw_link_status = BNX2_LINK_STATUS_10FULL;
936 break;
937 case SPEED_100:
938 if (bp->duplex == DUPLEX_HALF)
939 fw_link_status = BNX2_LINK_STATUS_100HALF;
940 else
941 fw_link_status = BNX2_LINK_STATUS_100FULL;
942 break;
943 case SPEED_1000:
944 if (bp->duplex == DUPLEX_HALF)
945 fw_link_status = BNX2_LINK_STATUS_1000HALF;
946 else
947 fw_link_status = BNX2_LINK_STATUS_1000FULL;
948 break;
949 case SPEED_2500:
950 if (bp->duplex == DUPLEX_HALF)
951 fw_link_status = BNX2_LINK_STATUS_2500HALF;
952 else
953 fw_link_status = BNX2_LINK_STATUS_2500FULL;
954 break;
955 }
956
957 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
958
959 if (bp->autoneg) {
960 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
961
ca58c3af
MC		 962 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
963 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 964
965 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 966 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 967 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
968 else
969 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
970 }
971 }
972 else
973 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
974
2726d6e1 975 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 976}
977
9b1084b8
MC		 978static char *
979bnx2_xceiver_str(struct bnx2 *bp)
980{
807540ba 981 return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 982 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
807540ba 983 "Copper");
9b1084b8
MC		 984}
985
b6016b76
MC		 986static void
987bnx2_report_link(struct bnx2 *bp)
988{
989 if (bp->link_up) {
990 netif_carrier_on(bp->dev);
3a9c6a49
JP		 991 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
992 bnx2_xceiver_str(bp),
993 bp->line_speed,
994 bp->duplex == DUPLEX_FULL ? "full" : "half");
b6016b76
MC		 995
996 if (bp->flow_ctrl) {
997 if (bp->flow_ctrl & FLOW_CTRL_RX) {
3a9c6a49 998 pr_cont(", receive ");
b6016b76 999 if (bp->flow_ctrl & FLOW_CTRL_TX)
3a9c6a49 1000 pr_cont("& transmit ");
b6016b76
MC		 1001 }
1002 else {
3a9c6a49 1003 pr_cont(", transmit ");
b6016b76 1004 }
3a9c6a49 1005 pr_cont("flow control ON");
b6016b76 1006 }
3a9c6a49
JP		 1007 pr_cont("\n");
1008 } else {
b6016b76 1009 netif_carrier_off(bp->dev);
3a9c6a49
JP		 1010 netdev_err(bp->dev, "NIC %s Link is Down\n",
1011 bnx2_xceiver_str(bp));
b6016b76 1012 }
e3648b3d
MC		 1013
1014 bnx2_report_fw_link(bp);
b6016b76
MC		 1015}
1016
1017static void
1018bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1019{
1020 u32 local_adv, remote_adv;
1021
1022 bp->flow_ctrl = 0;
6aa20a22 1023 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 1024 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1025
1026 if (bp->duplex == DUPLEX_FULL) {
1027 bp->flow_ctrl = bp->req_flow_ctrl;
1028 }
1029 return;
1030 }
1031
1032 if (bp->duplex != DUPLEX_FULL) {
1033 return;
1034 }
1035
583c28e5 1036 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 1037 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1038 u32 val;
1039
1040 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1041 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1042 bp->flow_ctrl |= FLOW_CTRL_TX;
1043 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1044 bp->flow_ctrl |= FLOW_CTRL_RX;
1045 return;
1046 }
1047
ca58c3af
MC		 1048 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1049 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 1050
583c28e5 1051 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1052 u32 new_local_adv = 0;
1053 u32 new_remote_adv = 0;
1054
1055 if (local_adv & ADVERTISE_1000XPAUSE)
1056 new_local_adv |= ADVERTISE_PAUSE_CAP;
1057 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1058 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1059 if (remote_adv & ADVERTISE_1000XPAUSE)
1060 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1061 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1062 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1063
1064 local_adv = new_local_adv;
1065 remote_adv = new_remote_adv;
1066 }
1067
1068 /* See Table 28B-3 of 802.3ab-1999 spec. */
1069 if (local_adv & ADVERTISE_PAUSE_CAP) {
1070 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1071 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1072 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1073 }
1074 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1075 bp->flow_ctrl = FLOW_CTRL_RX;
1076 }
1077 }
1078 else {
1079 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1080 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1081 }
1082 }
1083 }
1084 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1085 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1086 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1087
1088 bp->flow_ctrl = FLOW_CTRL_TX;
1089 }
1090 }
1091}
1092
27a005b8
MC		 1093static int
1094bnx2_5709s_linkup(struct bnx2 *bp)
1095{
1096 u32 val, speed;
1097
1098 bp->link_up = 1;
1099
1100 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1101 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1102 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1103
1104 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1105 bp->line_speed = bp->req_line_speed;
1106 bp->duplex = bp->req_duplex;
1107 return 0;
1108 }
1109 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1110 switch (speed) {
1111 case MII_BNX2_GP_TOP_AN_SPEED_10:
1112 bp->line_speed = SPEED_10;
1113 break;
1114 case MII_BNX2_GP_TOP_AN_SPEED_100:
1115 bp->line_speed = SPEED_100;
1116 break;
1117 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1118 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1119 bp->line_speed = SPEED_1000;
1120 break;
1121 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1122 bp->line_speed = SPEED_2500;
1123 break;
1124 }
1125 if (val & MII_BNX2_GP_TOP_AN_FD)
1126 bp->duplex = DUPLEX_FULL;
1127 else
1128 bp->duplex = DUPLEX_HALF;
1129 return 0;
1130}
1131
b6016b76 1132static int
5b0c76ad
MC		 1133bnx2_5708s_linkup(struct bnx2 *bp)
1134{
1135 u32 val;
1136
1137 bp->link_up = 1;
1138 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1139 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1140 case BCM5708S_1000X_STAT1_SPEED_10:
1141 bp->line_speed = SPEED_10;
1142 break;
1143 case BCM5708S_1000X_STAT1_SPEED_100:
1144 bp->line_speed = SPEED_100;
1145 break;
1146 case BCM5708S_1000X_STAT1_SPEED_1G:
1147 bp->line_speed = SPEED_1000;
1148 break;
1149 case BCM5708S_1000X_STAT1_SPEED_2G5:
1150 bp->line_speed = SPEED_2500;
1151 break;
1152 }
1153 if (val & BCM5708S_1000X_STAT1_FD)
1154 bp->duplex = DUPLEX_FULL;
1155 else
1156 bp->duplex = DUPLEX_HALF;
1157
1158 return 0;
1159}
1160
1161static int
1162bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 1163{
1164 u32 bmcr, local_adv, remote_adv, common;
1165
1166 bp->link_up = 1;
1167 bp->line_speed = SPEED_1000;
1168
ca58c3af 1169 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1170 if (bmcr & BMCR_FULLDPLX) {
1171 bp->duplex = DUPLEX_FULL;
1172 }
1173 else {
1174 bp->duplex = DUPLEX_HALF;
1175 }
1176
1177 if (!(bmcr & BMCR_ANENABLE)) {
1178 return 0;
1179 }
1180
ca58c3af
MC		 1181 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1182 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1183
1184 common = local_adv & remote_adv;
1185 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1186
1187 if (common & ADVERTISE_1000XFULL) {
1188 bp->duplex = DUPLEX_FULL;
1189 }
1190 else {
1191 bp->duplex = DUPLEX_HALF;
1192 }
1193 }
1194
1195 return 0;
1196}
1197
1198static int
1199bnx2_copper_linkup(struct bnx2 *bp)
1200{
1201 u32 bmcr;
1202
ca58c3af 1203 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1204 if (bmcr & BMCR_ANENABLE) {
1205 u32 local_adv, remote_adv, common;
1206
1207 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1208 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1209
1210 common = local_adv & (remote_adv >> 2);
1211 if (common & ADVERTISE_1000FULL) {
1212 bp->line_speed = SPEED_1000;
1213 bp->duplex = DUPLEX_FULL;
1214 }
1215 else if (common & ADVERTISE_1000HALF) {
1216 bp->line_speed = SPEED_1000;
1217 bp->duplex = DUPLEX_HALF;
1218 }
1219 else {
ca58c3af
MC		 1220 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1221 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1222
1223 common = local_adv & remote_adv;
1224 if (common & ADVERTISE_100FULL) {
1225 bp->line_speed = SPEED_100;
1226 bp->duplex = DUPLEX_FULL;
1227 }
1228 else if (common & ADVERTISE_100HALF) {
1229 bp->line_speed = SPEED_100;
1230 bp->duplex = DUPLEX_HALF;
1231 }
1232 else if (common & ADVERTISE_10FULL) {
1233 bp->line_speed = SPEED_10;
1234 bp->duplex = DUPLEX_FULL;
1235 }
1236 else if (common & ADVERTISE_10HALF) {
1237 bp->line_speed = SPEED_10;
1238 bp->duplex = DUPLEX_HALF;
1239 }
1240 else {
1241 bp->line_speed = 0;
1242 bp->link_up = 0;
1243 }
1244 }
1245 }
1246 else {
1247 if (bmcr & BMCR_SPEED100) {
1248 bp->line_speed = SPEED_100;
1249 }
1250 else {
1251 bp->line_speed = SPEED_10;
1252 }
1253 if (bmcr & BMCR_FULLDPLX) {
1254 bp->duplex = DUPLEX_FULL;
1255 }
1256 else {
1257 bp->duplex = DUPLEX_HALF;
1258 }
1259 }
1260
1261 return 0;
1262}
1263
83e3fc89 1264static void
bb4f98ab 1265bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
83e3fc89 1266{
bb4f98ab 1267 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
83e3fc89
MC		 1268
1269 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1270 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1271 val |= 0x02 << 8;
1272
22fa159d
MC		 1273 if (bp->flow_ctrl & FLOW_CTRL_TX)
1274 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
83e3fc89 1275
83e3fc89
MC		 1276 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1277}
1278
bb4f98ab
MC		 1279static void
1280bnx2_init_all_rx_contexts(struct bnx2 *bp)
1281{
1282 int i;
1283 u32 cid;
1284
1285 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1286 if (i == 1)
1287 cid = RX_RSS_CID;
1288 bnx2_init_rx_context(bp, cid);
1289 }
1290}
1291
344478db 1292static void
b6016b76
MC		 1293bnx2_set_mac_link(struct bnx2 *bp)
1294{
1295 u32 val;
1296
1297 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1298 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1299 (bp->duplex == DUPLEX_HALF)) {
1300 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1301 }
1302
1303 /* Configure the EMAC mode register. */
1304 val = REG_RD(bp, BNX2_EMAC_MODE);
1305
1306 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1307 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1308 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1309
1310 if (bp->link_up) {
5b0c76ad
MC		 1311 switch (bp->line_speed) {
1312 case SPEED_10:
59b47d8a
MC		 1313 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1314 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1315 break;
1316 }
1317 /* fall through */
1318 case SPEED_100:
1319 val |= BNX2_EMAC_MODE_PORT_MII;
1320 break;
1321 case SPEED_2500:
59b47d8a 1322 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1323 /* fall through */
1324 case SPEED_1000:
1325 val |= BNX2_EMAC_MODE_PORT_GMII;
1326 break;
1327 }
b6016b76
MC		 1328 }
1329 else {
1330 val |= BNX2_EMAC_MODE_PORT_GMII;
1331 }
1332
1333 /* Set the MAC to operate in the appropriate duplex mode. */
1334 if (bp->duplex == DUPLEX_HALF)
1335 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1336 REG_WR(bp, BNX2_EMAC_MODE, val);
1337
1338 /* Enable/disable rx PAUSE. */
1339 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1340
1341 if (bp->flow_ctrl & FLOW_CTRL_RX)
1342 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1343 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1344
1345 /* Enable/disable tx PAUSE. */
1346 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1347 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1348
1349 if (bp->flow_ctrl & FLOW_CTRL_TX)
1350 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1351 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1352
1353 /* Acknowledge the interrupt. */
1354 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1355
22fa159d 1356 bnx2_init_all_rx_contexts(bp);
b6016b76
MC		 1357}
1358
27a005b8
MC		 1359static void
1360bnx2_enable_bmsr1(struct bnx2 *bp)
1361{
583c28e5 1362 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1363 (CHIP_NUM(bp) == CHIP_NUM_5709))
1364 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1365 MII_BNX2_BLK_ADDR_GP_STATUS);
1366}
1367
1368static void
1369bnx2_disable_bmsr1(struct bnx2 *bp)
1370{
583c28e5 1371 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1372 (CHIP_NUM(bp) == CHIP_NUM_5709))
1373 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1374 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1375}
1376
605a9e20
MC		 1377static int
1378bnx2_test_and_enable_2g5(struct bnx2 *bp)
1379{
1380 u32 up1;
1381 int ret = 1;
1382
583c28e5 1383 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1384 return 0;
1385
1386 if (bp->autoneg & AUTONEG_SPEED)
1387 bp->advertising |= ADVERTISED_2500baseX_Full;
1388
27a005b8
MC		 1389 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1390 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1391
605a9e20
MC		 1392 bnx2_read_phy(bp, bp->mii_up1, &up1);
1393 if (!(up1 & BCM5708S_UP1_2G5)) {
1394 up1 |= BCM5708S_UP1_2G5;
1395 bnx2_write_phy(bp, bp->mii_up1, up1);
1396 ret = 0;
1397 }
1398
27a005b8
MC		 1399 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1400 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1401 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1402
605a9e20
MC		 1403 return ret;
1404}
1405
1406static int
1407bnx2_test_and_disable_2g5(struct bnx2 *bp)
1408{
1409 u32 up1;
1410 int ret = 0;
1411
583c28e5 1412 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1413 return 0;
1414
27a005b8
MC		 1415 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1416 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1417
605a9e20
MC		 1418 bnx2_read_phy(bp, bp->mii_up1, &up1);
1419 if (up1 & BCM5708S_UP1_2G5) {
1420 up1 &= ~BCM5708S_UP1_2G5;
1421 bnx2_write_phy(bp, bp->mii_up1, up1);
1422 ret = 1;
1423 }
1424
27a005b8
MC		 1425 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1426 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1427 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1428
605a9e20
MC		 1429 return ret;
1430}
1431
1432static void
1433bnx2_enable_forced_2g5(struct bnx2 *bp)
1434{
cbd6890c
MC		 1435 u32 uninitialized_var(bmcr);
1436 int err;
605a9e20 1437
583c28e5 1438 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1439 return;
1440
27a005b8
MC		 1441 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1442 u32 val;
1443
1444 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1445 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1446 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1447 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1448 val |= MII_BNX2_SD_MISC1_FORCE |
1449 MII_BNX2_SD_MISC1_FORCE_2_5G;
1450 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1451 }
27a005b8
MC		 1452
1453 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1454 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1455 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1456
1457 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1458 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1459 if (!err)
1460 bmcr |= BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1461 } else {
1462 return;
605a9e20
MC		 1463 }
1464
cbd6890c
MC		 1465 if (err)
1466 return;
1467
605a9e20
MC		 1468 if (bp->autoneg & AUTONEG_SPEED) {
1469 bmcr &= ~BMCR_ANENABLE;
1470 if (bp->req_duplex == DUPLEX_FULL)
1471 bmcr |= BMCR_FULLDPLX;
1472 }
1473 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1474}
1475
1476static void
1477bnx2_disable_forced_2g5(struct bnx2 *bp)
1478{
cbd6890c
MC		 1479 u32 uninitialized_var(bmcr);
1480 int err;
605a9e20 1481
583c28e5 1482 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1483 return;
1484
27a005b8
MC		 1485 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1486 u32 val;
1487
1488 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1489 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1490 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1491 val &= ~MII_BNX2_SD_MISC1_FORCE;
1492 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1493 }
27a005b8
MC		 1494
1495 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1496 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1497 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1498
1499 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1500 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1501 if (!err)
1502 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1503 } else {
1504 return;
605a9e20
MC		 1505 }
1506
cbd6890c
MC		 1507 if (err)
1508 return;
1509
605a9e20
MC		 1510 if (bp->autoneg & AUTONEG_SPEED)
1511 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1512 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1513}
1514
b2fadeae
MC		 1515static void
1516bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1517{
1518 u32 val;
1519
1520 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1521 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1522 if (start)
1523 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1524 else
1525 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1526}
1527
b6016b76
MC		 1528static int
1529bnx2_set_link(struct bnx2 *bp)
1530{
1531 u32 bmsr;
1532 u8 link_up;
1533
80be4434 1534 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1535 bp->link_up = 1;
1536 return 0;
1537 }
1538
583c28e5 1539 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1540 return 0;
1541
b6016b76
MC		 1542 link_up = bp->link_up;
1543
27a005b8
MC		 1544 bnx2_enable_bmsr1(bp);
1545 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1546 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1547 bnx2_disable_bmsr1(bp);
b6016b76 1548
583c28e5 1549 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1550 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1551 u32 val, an_dbg;
b6016b76 1552
583c28e5 1553 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1554 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1555 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1556 }
b6016b76 1557 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1558
1559 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1560 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1561 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1562
1563 if ((val & BNX2_EMAC_STATUS_LINK) &&
1564 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1565 bmsr |= BMSR_LSTATUS;
1566 else
1567 bmsr &= ~BMSR_LSTATUS;
1568 }
1569
1570 if (bmsr & BMSR_LSTATUS) {
1571 bp->link_up = 1;
1572
583c28e5 1573 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1574 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1575 bnx2_5706s_linkup(bp);
1576 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1577 bnx2_5708s_linkup(bp);
27a005b8
MC		 1578 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1579 bnx2_5709s_linkup(bp);
b6016b76
MC		 1580 }
1581 else {
1582 bnx2_copper_linkup(bp);
1583 }
1584 bnx2_resolve_flow_ctrl(bp);
1585 }
1586 else {
583c28e5 1587 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1588 (bp->autoneg & AUTONEG_SPEED))
1589 bnx2_disable_forced_2g5(bp);
b6016b76 1590
583c28e5 1591 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1592 u32 bmcr;
1593
1594 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1595 bmcr |= BMCR_ANENABLE;
1596 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1597
583c28e5 1598 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1599 }
b6016b76
MC		 1600 bp->link_up = 0;
1601 }
1602
1603 if (bp->link_up != link_up) {
1604 bnx2_report_link(bp);
1605 }
1606
1607 bnx2_set_mac_link(bp);
1608
1609 return 0;
1610}
1611
1612static int
1613bnx2_reset_phy(struct bnx2 *bp)
1614{
1615 int i;
1616 u32 reg;
1617
ca58c3af 1618 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1619
1620#define PHY_RESET_MAX_WAIT 100
1621 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1622 udelay(10);
1623
ca58c3af 1624 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1625 if (!(reg & BMCR_RESET)) {
1626 udelay(20);
1627 break;
1628 }
1629 }
1630 if (i == PHY_RESET_MAX_WAIT) {
1631 return -EBUSY;
1632 }
1633 return 0;
1634}
1635
1636static u32
1637bnx2_phy_get_pause_adv(struct bnx2 *bp)
1638{
1639 u32 adv = 0;
1640
1641 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1642 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1643
583c28e5 1644 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1645 adv = ADVERTISE_1000XPAUSE;
1646 }
1647 else {
1648 adv = ADVERTISE_PAUSE_CAP;
1649 }
1650 }
1651 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1652 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1653 adv = ADVERTISE_1000XPSE_ASYM;
1654 }
1655 else {
1656 adv = ADVERTISE_PAUSE_ASYM;
1657 }
1658 }
1659 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1660 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1661 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1662 }
1663 else {
1664 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1665 }
1666 }
1667 return adv;
1668}
1669
a2f13890 1670static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
0d8a6571 1671
b6016b76 1672static int
0d8a6571 1673bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1674__releases(&bp->phy_lock)
1675__acquires(&bp->phy_lock)
0d8a6571
MC		 1676{
1677 u32 speed_arg = 0, pause_adv;
1678
1679 pause_adv = bnx2_phy_get_pause_adv(bp);
1680
1681 if (bp->autoneg & AUTONEG_SPEED) {
1682 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1683 if (bp->advertising & ADVERTISED_10baseT_Half)
1684 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1685 if (bp->advertising & ADVERTISED_10baseT_Full)
1686 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1687 if (bp->advertising & ADVERTISED_100baseT_Half)
1688 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1689 if (bp->advertising & ADVERTISED_100baseT_Full)
1690 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1691 if (bp->advertising & ADVERTISED_1000baseT_Full)
1692 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1693 if (bp->advertising & ADVERTISED_2500baseX_Full)
1694 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1695 } else {
1696 if (bp->req_line_speed == SPEED_2500)
1697 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1698 else if (bp->req_line_speed == SPEED_1000)
1699 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1700 else if (bp->req_line_speed == SPEED_100) {
1701 if (bp->req_duplex == DUPLEX_FULL)
1702 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1703 else
1704 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1705 } else if (bp->req_line_speed == SPEED_10) {
1706 if (bp->req_duplex == DUPLEX_FULL)
1707 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1708 else
1709 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1710 }
1711 }
1712
1713 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1714 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1715 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1716 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1717
1718 if (port == PORT_TP)
1719 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1720 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1721
2726d6e1 1722 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1723
1724 spin_unlock_bh(&bp->phy_lock);
a2f13890 1725 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
0d8a6571
MC		 1726 spin_lock_bh(&bp->phy_lock);
1727
1728 return 0;
1729}
1730
1731static int
1732bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1733__releases(&bp->phy_lock)
1734__acquires(&bp->phy_lock)
b6016b76 1735{
605a9e20 1736 u32 adv, bmcr;
b6016b76
MC		 1737 u32 new_adv = 0;
1738
583c28e5 1739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
807540ba 1740 return bnx2_setup_remote_phy(bp, port);
0d8a6571 1741
b6016b76
MC		 1742 if (!(bp->autoneg & AUTONEG_SPEED)) {
1743 u32 new_bmcr;
5b0c76ad
MC		 1744 int force_link_down = 0;
1745
605a9e20
MC		 1746 if (bp->req_line_speed == SPEED_2500) {
1747 if (!bnx2_test_and_enable_2g5(bp))
1748 force_link_down = 1;
1749 } else if (bp->req_line_speed == SPEED_1000) {
1750 if (bnx2_test_and_disable_2g5(bp))
1751 force_link_down = 1;
1752 }
ca58c3af 1753 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1754 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1755
ca58c3af 1756 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1757 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1758 new_bmcr |= BMCR_SPEED1000;
605a9e20 1759
27a005b8
MC		 1760 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1761 if (bp->req_line_speed == SPEED_2500)
1762 bnx2_enable_forced_2g5(bp);
1763 else if (bp->req_line_speed == SPEED_1000) {
1764 bnx2_disable_forced_2g5(bp);
1765 new_bmcr &= ~0x2000;
1766 }
1767
1768 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1769 if (bp->req_line_speed == SPEED_2500)
1770 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1771 else
1772 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1773 }
1774
b6016b76 1775 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1776 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1777 new_bmcr |= BMCR_FULLDPLX;
1778 }
1779 else {
5b0c76ad 1780 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1781 new_bmcr &= ~BMCR_FULLDPLX;
1782 }
5b0c76ad 1783 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1784 /* Force a link down visible on the other side */
1785 if (bp->link_up) {
ca58c3af 1786 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1787 ~(ADVERTISE_1000XFULL |
1788 ADVERTISE_1000XHALF));
ca58c3af 1789 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1790 BMCR_ANRESTART | BMCR_ANENABLE);
1791
1792 bp->link_up = 0;
1793 netif_carrier_off(bp->dev);
ca58c3af 1794 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1795 bnx2_report_link(bp);
b6016b76 1796 }
ca58c3af
MC		 1797 bnx2_write_phy(bp, bp->mii_adv, adv);
1798 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1799 } else {
1800 bnx2_resolve_flow_ctrl(bp);
1801 bnx2_set_mac_link(bp);
b6016b76
MC		 1802 }
1803 return 0;
1804 }
1805
605a9e20 1806 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1807
b6016b76
MC		 1808 if (bp->advertising & ADVERTISED_1000baseT_Full)
1809 new_adv |= ADVERTISE_1000XFULL;
1810
1811 new_adv |= bnx2_phy_get_pause_adv(bp);
1812
ca58c3af
MC		 1813 bnx2_read_phy(bp, bp->mii_adv, &adv);
1814 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1815
1816 bp->serdes_an_pending = 0;
1817 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1818 /* Force a link down visible on the other side */
1819 if (bp->link_up) {
ca58c3af 1820 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1821 spin_unlock_bh(&bp->phy_lock);
1822 msleep(20);
1823 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1824 }
1825
ca58c3af
MC		 1826 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1827 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1828 BMCR_ANENABLE);
f8dd064e
MC		 1829 /* Speed up link-up time when the link partner
1830 * does not autonegotiate which is very common
1831 * in blade servers. Some blade servers use
1832 * IPMI for kerboard input and it's important
1833 * to minimize link disruptions. Autoneg. involves
1834 * exchanging base pages plus 3 next pages and
1835 * normally completes in about 120 msec.
1836 */
40105c0b 1837 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 1838 bp->serdes_an_pending = 1;
1839 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1840 } else {
1841 bnx2_resolve_flow_ctrl(bp);
1842 bnx2_set_mac_link(bp);
b6016b76
MC		 1843 }
1844
1845 return 0;
1846}
1847
1848#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1849 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1850 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1851 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1852
1853#define ETHTOOL_ALL_COPPER_SPEED \
1854 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1855 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1856 ADVERTISED_1000baseT_Full)
1857
1858#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1859 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1860
b6016b76
MC		 1861#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1862
0d8a6571
MC		 1863static void
1864bnx2_set_default_remote_link(struct bnx2 *bp)
1865{
1866 u32 link;
1867
1868 if (bp->phy_port == PORT_TP)
2726d6e1 1869 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1870 else
2726d6e1 1871 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1872
1873 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1874 bp->req_line_speed = 0;
1875 bp->autoneg |= AUTONEG_SPEED;
1876 bp->advertising = ADVERTISED_Autoneg;
1877 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1878 bp->advertising |= ADVERTISED_10baseT_Half;
1879 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1880 bp->advertising |= ADVERTISED_10baseT_Full;
1881 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1882 bp->advertising |= ADVERTISED_100baseT_Half;
1883 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1884 bp->advertising |= ADVERTISED_100baseT_Full;
1885 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1886 bp->advertising |= ADVERTISED_1000baseT_Full;
1887 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1888 bp->advertising |= ADVERTISED_2500baseX_Full;
1889 } else {
1890 bp->autoneg = 0;
1891 bp->advertising = 0;
1892 bp->req_duplex = DUPLEX_FULL;
1893 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1894 bp->req_line_speed = SPEED_10;
1895 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1896 bp->req_duplex = DUPLEX_HALF;
1897 }
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1899 bp->req_line_speed = SPEED_100;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1901 bp->req_duplex = DUPLEX_HALF;
1902 }
1903 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1904 bp->req_line_speed = SPEED_1000;
1905 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1906 bp->req_line_speed = SPEED_2500;
1907 }
1908}
1909
deaf391b
MC		 1910static void
1911bnx2_set_default_link(struct bnx2 *bp)
1912{
ab59859d
HH		 1913 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1914 bnx2_set_default_remote_link(bp);
1915 return;
1916 }
0d8a6571 1917
deaf391b
MC		 1918 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1919 bp->req_line_speed = 0;
583c28e5 1920 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1921 u32 reg;
1922
1923 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1924
2726d6e1 1925 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1926 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1927 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1928 bp->autoneg = 0;
1929 bp->req_line_speed = bp->line_speed = SPEED_1000;
1930 bp->req_duplex = DUPLEX_FULL;
1931 }
1932 } else
1933 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1934}
1935
df149d70
MC		 1936static void
1937bnx2_send_heart_beat(struct bnx2 *bp)
1938{
1939 u32 msg;
1940 u32 addr;
1941
1942 spin_lock(&bp->indirect_lock);
1943 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1944 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1945 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1946 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1947 spin_unlock(&bp->indirect_lock);
1948}
1949
0d8a6571
MC		 1950static void
1951bnx2_remote_phy_event(struct bnx2 *bp)
1952{
1953 u32 msg;
1954 u8 link_up = bp->link_up;
1955 u8 old_port;
1956
2726d6e1 1957 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1958
df149d70
MC		 1959 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1960 bnx2_send_heart_beat(bp);
1961
1962 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1963
0d8a6571
MC		 1964 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1965 bp->link_up = 0;
1966 else {
1967 u32 speed;
1968
1969 bp->link_up = 1;
1970 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1971 bp->duplex = DUPLEX_FULL;
1972 switch (speed) {
1973 case BNX2_LINK_STATUS_10HALF:
1974 bp->duplex = DUPLEX_HALF;
1975 case BNX2_LINK_STATUS_10FULL:
1976 bp->line_speed = SPEED_10;
1977 break;
1978 case BNX2_LINK_STATUS_100HALF:
1979 bp->duplex = DUPLEX_HALF;
1980 case BNX2_LINK_STATUS_100BASE_T4:
1981 case BNX2_LINK_STATUS_100FULL:
1982 bp->line_speed = SPEED_100;
1983 break;
1984 case BNX2_LINK_STATUS_1000HALF:
1985 bp->duplex = DUPLEX_HALF;
1986 case BNX2_LINK_STATUS_1000FULL:
1987 bp->line_speed = SPEED_1000;
1988 break;
1989 case BNX2_LINK_STATUS_2500HALF:
1990 bp->duplex = DUPLEX_HALF;
1991 case BNX2_LINK_STATUS_2500FULL:
1992 bp->line_speed = SPEED_2500;
1993 break;
1994 default:
1995 bp->line_speed = 0;
1996 break;
1997 }
1998
0d8a6571
MC		 1999 bp->flow_ctrl = 0;
2000 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2001 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2002 if (bp->duplex == DUPLEX_FULL)
2003 bp->flow_ctrl = bp->req_flow_ctrl;
2004 } else {
2005 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2006 bp->flow_ctrl |= FLOW_CTRL_TX;
2007 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2008 bp->flow_ctrl |= FLOW_CTRL_RX;
2009 }
2010
2011 old_port = bp->phy_port;
2012 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2013 bp->phy_port = PORT_FIBRE;
2014 else
2015 bp->phy_port = PORT_TP;
2016
2017 if (old_port != bp->phy_port)
2018 bnx2_set_default_link(bp);
2019
0d8a6571
MC		 2020 }
2021 if (bp->link_up != link_up)
2022 bnx2_report_link(bp);
2023
2024 bnx2_set_mac_link(bp);
2025}
2026
2027static int
2028bnx2_set_remote_link(struct bnx2 *bp)
2029{
2030 u32 evt_code;
2031
2726d6e1 2032 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 2033 switch (evt_code) {
2034 case BNX2_FW_EVT_CODE_LINK_EVENT:
2035 bnx2_remote_phy_event(bp);
2036 break;
2037 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2038 default:
df149d70 2039 bnx2_send_heart_beat(bp);
0d8a6571
MC		 2040 break;
2041 }
2042 return 0;
2043}
2044
b6016b76
MC		 2045static int
2046bnx2_setup_copper_phy(struct bnx2 *bp)
52d07b1f
HH		 2047__releases(&bp->phy_lock)
2048__acquires(&bp->phy_lock)
b6016b76
MC		 2049{
2050 u32 bmcr;
2051 u32 new_bmcr;
2052
ca58c3af 2053 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 2054
2055 if (bp->autoneg & AUTONEG_SPEED) {
2056 u32 adv_reg, adv1000_reg;
2057 u32 new_adv_reg = 0;
2058 u32 new_adv1000_reg = 0;
2059
ca58c3af 2060 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 2061 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2062 ADVERTISE_PAUSE_ASYM);
2063
2064 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2065 adv1000_reg &= PHY_ALL_1000_SPEED;
2066
2067 if (bp->advertising & ADVERTISED_10baseT_Half)
2068 new_adv_reg |= ADVERTISE_10HALF;
2069 if (bp->advertising & ADVERTISED_10baseT_Full)
2070 new_adv_reg |= ADVERTISE_10FULL;
2071 if (bp->advertising & ADVERTISED_100baseT_Half)
2072 new_adv_reg |= ADVERTISE_100HALF;
2073 if (bp->advertising & ADVERTISED_100baseT_Full)
2074 new_adv_reg |= ADVERTISE_100FULL;
2075 if (bp->advertising & ADVERTISED_1000baseT_Full)
2076 new_adv1000_reg |= ADVERTISE_1000FULL;
6aa20a22 2077
b6016b76
MC		 2078 new_adv_reg |= ADVERTISE_CSMA;
2079
2080 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2081
2082 if ((adv1000_reg != new_adv1000_reg) ||
2083 (adv_reg != new_adv_reg) ||
2084 ((bmcr & BMCR_ANENABLE) == 0)) {
2085
ca58c3af 2086 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
b6016b76 2087 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
ca58c3af 2088 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 2089 BMCR_ANENABLE);
2090 }
2091 else if (bp->link_up) {
2092 /* Flow ctrl may have changed from auto to forced */
2093 /* or vice-versa. */
2094
2095 bnx2_resolve_flow_ctrl(bp);
2096 bnx2_set_mac_link(bp);
2097 }
2098 return 0;
2099 }
2100
2101 new_bmcr = 0;
2102 if (bp->req_line_speed == SPEED_100) {
2103 new_bmcr |= BMCR_SPEED100;
2104 }
2105 if (bp->req_duplex == DUPLEX_FULL) {
2106 new_bmcr |= BMCR_FULLDPLX;
2107 }
2108 if (new_bmcr != bmcr) {
2109 u32 bmsr;
b6016b76 2110
ca58c3af
MC		 2111 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2112 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 2113
b6016b76
MC		 2114 if (bmsr & BMSR_LSTATUS) {
2115 /* Force link down */
ca58c3af 2116 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 2117 spin_unlock_bh(&bp->phy_lock);
2118 msleep(50);
2119 spin_lock_bh(&bp->phy_lock);
2120
ca58c3af
MC		 2121 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2122 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 2123 }
2124
ca58c3af 2125 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 2126
2127 /* Normally, the new speed is setup after the link has
2128 * gone down and up again. In some cases, link will not go
2129 * down so we need to set up the new speed here.
2130 */
2131 if (bmsr & BMSR_LSTATUS) {
2132 bp->line_speed = bp->req_line_speed;
2133 bp->duplex = bp->req_duplex;
2134 bnx2_resolve_flow_ctrl(bp);
2135 bnx2_set_mac_link(bp);
2136 }
27a005b8
MC		 2137 } else {
2138 bnx2_resolve_flow_ctrl(bp);
2139 bnx2_set_mac_link(bp);
b6016b76
MC		 2140 }
2141 return 0;
2142}
2143
2144static int
0d8a6571 2145bnx2_setup_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 2146__releases(&bp->phy_lock)
2147__acquires(&bp->phy_lock)
b6016b76
MC		 2148{
2149 if (bp->loopback == MAC_LOOPBACK)
2150 return 0;
2151
583c28e5 2152 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
807540ba 2153 return bnx2_setup_serdes_phy(bp, port);
b6016b76
MC		 2154 }
2155 else {
807540ba 2156 return bnx2_setup_copper_phy(bp);
b6016b76
MC		 2157 }
2158}
2159
27a005b8 2160static int
9a120bc5 2161bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 2162{
2163 u32 val;
2164
2165 bp->mii_bmcr = MII_BMCR + 0x10;
2166 bp->mii_bmsr = MII_BMSR + 0x10;
2167 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2168 bp->mii_adv = MII_ADVERTISE + 0x10;
2169 bp->mii_lpa = MII_LPA + 0x10;
2170 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2171
2172 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2173 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2174
2175 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 2176 if (reset_phy)
2177 bnx2_reset_phy(bp);
27a005b8
MC		 2178
2179 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2180
2181 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2182 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2183 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2184 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2185
2186 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2187 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 2188 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 2189 val |= BCM5708S_UP1_2G5;
2190 else
2191 val &= ~BCM5708S_UP1_2G5;
2192 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2193
2194 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2195 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2196 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2197 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2198
2199 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2200
2201 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2202 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2203 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2204
2205 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2206
2207 return 0;
2208}
2209
b6016b76 2210static int
9a120bc5 2211bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 2212{
2213 u32 val;
2214
9a120bc5
MC		 2215 if (reset_phy)
2216 bnx2_reset_phy(bp);
27a005b8
MC		 2217
2218 bp->mii_up1 = BCM5708S_UP1;
2219
5b0c76ad
MC		 2220 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2221 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2222 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2223
2224 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2225 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2226 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2227
2228 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2229 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2230 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2231
583c28e5 2232 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 2233 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2234 val |= BCM5708S_UP1_2G5;
2235 bnx2_write_phy(bp, BCM5708S_UP1, val);
2236 }
2237
2238 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 2239 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2240 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 2241 /* increase tx signal amplitude */
2242 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2243 BCM5708S_BLK_ADDR_TX_MISC);
2244 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2245 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2246 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2247 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2248 }
2249
2726d6e1 2250 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 2251 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2252
2253 if (val) {
2254 u32 is_backplane;
2255
2726d6e1 2256 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 2257 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2258 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2259 BCM5708S_BLK_ADDR_TX_MISC);
2260 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2261 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2262 BCM5708S_BLK_ADDR_DIG);
2263 }
2264 }
2265 return 0;
2266}
2267
2268static int
9a120bc5 2269bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2270{
9a120bc5
MC		 2271 if (reset_phy)
2272 bnx2_reset_phy(bp);
27a005b8 2273
583c28e5 2274 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 2275
59b47d8a
MC		 2276 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2277 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 2278
2279 if (bp->dev->mtu > 1500) {
2280 u32 val;
2281
2282 /* Set extended packet length bit */
2283 bnx2_write_phy(bp, 0x18, 0x7);
2284 bnx2_read_phy(bp, 0x18, &val);
2285 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2286
2287 bnx2_write_phy(bp, 0x1c, 0x6c00);
2288 bnx2_read_phy(bp, 0x1c, &val);
2289 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2290 }
2291 else {
2292 u32 val;
2293
2294 bnx2_write_phy(bp, 0x18, 0x7);
2295 bnx2_read_phy(bp, 0x18, &val);
2296 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2297
2298 bnx2_write_phy(bp, 0x1c, 0x6c00);
2299 bnx2_read_phy(bp, 0x1c, &val);
2300 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2301 }
2302
2303 return 0;
2304}
2305
2306static int
9a120bc5 2307bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2308{
5b0c76ad
MC		 2309 u32 val;
2310
9a120bc5
MC		 2311 if (reset_phy)
2312 bnx2_reset_phy(bp);
27a005b8 2313
583c28e5 2314 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2315 bnx2_write_phy(bp, 0x18, 0x0c00);
2316 bnx2_write_phy(bp, 0x17, 0x000a);
2317 bnx2_write_phy(bp, 0x15, 0x310b);
2318 bnx2_write_phy(bp, 0x17, 0x201f);
2319 bnx2_write_phy(bp, 0x15, 0x9506);
2320 bnx2_write_phy(bp, 0x17, 0x401f);
2321 bnx2_write_phy(bp, 0x15, 0x14e2);
2322 bnx2_write_phy(bp, 0x18, 0x0400);
2323 }
2324
583c28e5 2325 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2326 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2327 MII_BNX2_DSP_EXPAND_REG | 0x8);
2328 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2329 val &= ~(1 << 8);
2330 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2331 }
2332
b6016b76 2333 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2334 /* Set extended packet length bit */
2335 bnx2_write_phy(bp, 0x18, 0x7);
2336 bnx2_read_phy(bp, 0x18, &val);
2337 bnx2_write_phy(bp, 0x18, val | 0x4000);
2338
2339 bnx2_read_phy(bp, 0x10, &val);
2340 bnx2_write_phy(bp, 0x10, val | 0x1);
2341 }
2342 else {
b6016b76
MC		 2343 bnx2_write_phy(bp, 0x18, 0x7);
2344 bnx2_read_phy(bp, 0x18, &val);
2345 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2346
2347 bnx2_read_phy(bp, 0x10, &val);
2348 bnx2_write_phy(bp, 0x10, val & ~0x1);
2349 }
2350
5b0c76ad
MC		 2351 /* ethernet@wirespeed */
2352 bnx2_write_phy(bp, 0x18, 0x7007);
2353 bnx2_read_phy(bp, 0x18, &val);
2354 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2355 return 0;
2356}
2357
2358
2359static int
9a120bc5 2360bnx2_init_phy(struct bnx2 *bp, int reset_phy)
52d07b1f
HH		 2361__releases(&bp->phy_lock)
2362__acquires(&bp->phy_lock)
b6016b76
MC		 2363{
2364 u32 val;
2365 int rc = 0;
2366
583c28e5
MC		 2367 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2368 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2369
ca58c3af
MC		 2370 bp->mii_bmcr = MII_BMCR;
2371 bp->mii_bmsr = MII_BMSR;
27a005b8 2372 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2373 bp->mii_adv = MII_ADVERTISE;
2374 bp->mii_lpa = MII_LPA;
2375
b6016b76
MC		 2376 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2377
583c28e5 2378 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2379 goto setup_phy;
2380
b6016b76
MC		 2381 bnx2_read_phy(bp, MII_PHYSID1, &val);
2382 bp->phy_id = val << 16;
2383 bnx2_read_phy(bp, MII_PHYSID2, &val);
2384 bp->phy_id |= val & 0xffff;
2385
583c28e5 2386 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad 2387 if (CHIP_NUM(bp) == CHIP_NUM_5706)
9a120bc5 2388 rc = bnx2_init_5706s_phy(bp, reset_phy);
5b0c76ad 2389 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
9a120bc5 2390 rc = bnx2_init_5708s_phy(bp, reset_phy);
27a005b8 2391 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
9a120bc5 2392 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2393 }
2394 else {
9a120bc5 2395 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2396 }
2397
0d8a6571
MC		 2398setup_phy:
2399 if (!rc)
2400 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2401
2402 return rc;
2403}
2404
2405static int
2406bnx2_set_mac_loopback(struct bnx2 *bp)
2407{
2408 u32 mac_mode;
2409
2410 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2411 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2412 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2413 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2414 bp->link_up = 1;
2415 return 0;
2416}
2417
bc5a0690
MC		 2418static int bnx2_test_link(struct bnx2 *);
2419
2420static int
2421bnx2_set_phy_loopback(struct bnx2 *bp)
2422{
2423 u32 mac_mode;
2424 int rc, i;
2425
2426 spin_lock_bh(&bp->phy_lock);
ca58c3af 2427 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2428 BMCR_SPEED1000);
2429 spin_unlock_bh(&bp->phy_lock);
2430 if (rc)
2431 return rc;
2432
2433 for (i = 0; i < 10; i++) {
2434 if (bnx2_test_link(bp) == 0)
2435 break;
80be4434 2436 msleep(100);
bc5a0690
MC		 2437 }
2438
2439 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2440 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2441 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2442 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2443
2444 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2445 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2446 bp->link_up = 1;
2447 return 0;
2448}
2449
ecdbf6e0
JH		 2450static void
2451bnx2_dump_mcp_state(struct bnx2 *bp)
2452{
2453 struct net_device *dev = bp->dev;
2454 u32 mcp_p0, mcp_p1;
2455
2456 netdev_err(dev, "<--- start MCP states dump --->\n");
2457 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
2458 mcp_p0 = BNX2_MCP_STATE_P0;
2459 mcp_p1 = BNX2_MCP_STATE_P1;
2460 } else {
2461 mcp_p0 = BNX2_MCP_STATE_P0_5708;
2462 mcp_p1 = BNX2_MCP_STATE_P1_5708;
2463 }
2464 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
2465 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
2466 netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n",
2467 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),
2468 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),
2469 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));
2470 netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n",
2471 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2472 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2473 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));
2474 netdev_err(dev, "DEBUG: shmem states:\n");
2475 netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]",
2476 bnx2_shmem_rd(bp, BNX2_DRV_MB),
2477 bnx2_shmem_rd(bp, BNX2_FW_MB),
2478 bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
2479 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
2480 netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]",
2481 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
2482 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
2483 pr_cont(" condition[%08x]\n",
2484 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
2485 DP_SHMEM_LINE(bp, 0x3cc);
2486 DP_SHMEM_LINE(bp, 0x3dc);
2487 DP_SHMEM_LINE(bp, 0x3ec);
2488 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
2489 netdev_err(dev, "<--- end MCP states dump --->\n");
2490}
2491
b6016b76 2492static int
a2f13890 2493bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
b6016b76
MC		 2494{
2495 int i;
2496 u32 val;
2497
b6016b76
MC		 2498 bp->fw_wr_seq++;
2499 msg_data |= bp->fw_wr_seq;
2500
2726d6e1 2501 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2502
a2f13890
MC		 2503 if (!ack)
2504 return 0;
2505
b6016b76 2506 /* wait for an acknowledgement. */
40105c0b 2507 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
b090ae2b 2508 msleep(10);
b6016b76 2509
2726d6e1 2510 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2511
2512 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2513 break;
2514 }
b090ae2b
MC		 2515 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2516 return 0;
b6016b76
MC		 2517
2518 /* If we timed out, inform the firmware that this is the case. */
b090ae2b 2519 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
b6016b76
MC		 2520 msg_data &= ~BNX2_DRV_MSG_CODE;
2521 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2522
2726d6e1 2523 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
ecdbf6e0
JH		 2524 if (!silent) {
2525 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2526 bnx2_dump_mcp_state(bp);
2527 }
b6016b76 2528
b6016b76
MC		 2529 return -EBUSY;
2530 }
2531
b090ae2b
MC		 2532 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2533 return -EIO;
2534
b6016b76
MC		 2535 return 0;
2536}
2537
59b47d8a
MC		 2538static int
2539bnx2_init_5709_context(struct bnx2 *bp)
2540{
2541 int i, ret = 0;
2542 u32 val;
2543
2544 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2545 val |= (BCM_PAGE_BITS - 8) << 16;
2546 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2547 for (i = 0; i < 10; i++) {
2548 val = REG_RD(bp, BNX2_CTX_COMMAND);
2549 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2550 break;
2551 udelay(2);
2552 }
2553 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2554 return -EBUSY;
2555
59b47d8a
MC		 2556 for (i = 0; i < bp->ctx_pages; i++) {
2557 int j;
2558
352f7687
MC		 2559 if (bp->ctx_blk[i])
2560 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2561 else
2562 return -ENOMEM;
2563
59b47d8a
MC		 2564 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2565 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2566 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2567 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2568 (u64) bp->ctx_blk_mapping[i] >> 32);
2569 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2570 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2571 for (j = 0; j < 10; j++) {
2572
2573 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2574 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2575 break;
2576 udelay(5);
2577 }
2578 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2579 ret = -EBUSY;
2580 break;
2581 }
2582 }
2583 return ret;
2584}
2585
b6016b76
MC		 2586static void
2587bnx2_init_context(struct bnx2 *bp)
2588{
2589 u32 vcid;
2590
2591 vcid = 96;
2592 while (vcid) {
2593 u32 vcid_addr, pcid_addr, offset;
7947b20e 2594 int i;
b6016b76
MC		 2595
2596 vcid--;
2597
2598 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2599 u32 new_vcid;
2600
2601 vcid_addr = GET_PCID_ADDR(vcid);
2602 if (vcid & 0x8) {
2603 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2604 }
2605 else {
2606 new_vcid = vcid;
2607 }
2608 pcid_addr = GET_PCID_ADDR(new_vcid);
2609 }
2610 else {
2611 vcid_addr = GET_CID_ADDR(vcid);
2612 pcid_addr = vcid_addr;
2613 }
2614
7947b20e
MC		 2615 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2616 vcid_addr += (i << PHY_CTX_SHIFT);
2617 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2618
5d5d0015 2619 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2620 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2621
7947b20e
MC		 2622 /* Zero out the context. */
2623 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2624 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2625 }
b6016b76
MC		 2626 }
2627}
2628
2629static int
2630bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2631{
2632 u16 *good_mbuf;
2633 u32 good_mbuf_cnt;
2634 u32 val;
2635
2636 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2637 if (good_mbuf == NULL) {
3a9c6a49 2638 pr_err("Failed to allocate memory in %s\n", __func__);
b6016b76
MC		 2639 return -ENOMEM;
2640 }
2641
2642 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2643 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2644
2645 good_mbuf_cnt = 0;
2646
2647 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2648 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2649 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2650 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2651 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2652
2726d6e1 2653 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2654
2655 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2656
2657 /* The addresses with Bit 9 set are bad memory blocks. */
2658 if (!(val & (1 << 9))) {
2659 good_mbuf[good_mbuf_cnt] = (u16) val;
2660 good_mbuf_cnt++;
2661 }
2662
2726d6e1 2663 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2664 }
2665
2666 /* Free the good ones back to the mbuf pool thus discarding
2667 * all the bad ones. */
2668 while (good_mbuf_cnt) {
2669 good_mbuf_cnt--;
2670
2671 val = good_mbuf[good_mbuf_cnt];
2672 val = (val << 9) | val | 1;
2673
2726d6e1 2674 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2675 }
2676 kfree(good_mbuf);
2677 return 0;
2678}
2679
2680static void
5fcaed01 2681bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
b6016b76
MC		 2682{
2683 u32 val;
b6016b76
MC		 2684
2685 val = (mac_addr[0] << 8) | mac_addr[1];
2686
5fcaed01 2687 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
b6016b76 2688
6aa20a22 2689 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2690 (mac_addr[4] << 8) | mac_addr[5];
2691
5fcaed01 2692 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
b6016b76
MC		 2693}
2694
47bf4246 2695static inline int
a2df00aa 2696bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
47bf4246
MC		 2697{
2698 dma_addr_t mapping;
bb4f98ab 2699 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246 2700 struct rx_bd *rxbd =
bb4f98ab 2701 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
a2df00aa 2702 struct page *page = alloc_page(gfp);
47bf4246
MC		 2703
2704 if (!page)
2705 return -ENOMEM;
36227e88 2706 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
47bf4246 2707 PCI_DMA_FROMDEVICE);
36227e88 2708 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 2709 __free_page(page);
2710 return -EIO;
2711 }
2712
47bf4246 2713 rx_pg->page = page;
1a4ccc2d 2714 dma_unmap_addr_set(rx_pg, mapping, mapping);
47bf4246
MC		 2715 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2716 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2717 return 0;
2718}
2719
2720static void
bb4f98ab 2721bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246 2722{
bb4f98ab 2723 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246
MC		 2724 struct page *page = rx_pg->page;
2725
2726 if (!page)
2727 return;
2728
36227e88
SG		 2729 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2730 PAGE_SIZE, PCI_DMA_FROMDEVICE);
47bf4246
MC		 2731
2732 __free_page(page);
2733 rx_pg->page = NULL;
2734}
2735
b6016b76 2736static inline int
a2df00aa 2737bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
b6016b76
MC		 2738{
2739 struct sk_buff *skb;
bb4f98ab 2740 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
b6016b76 2741 dma_addr_t mapping;
bb4f98ab 2742 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 2743 unsigned long align;
2744
a2df00aa 2745 skb = __netdev_alloc_skb(bp->dev, bp->rx_buf_size, gfp);
b6016b76
MC		 2746 if (skb == NULL) {
2747 return -ENOMEM;
2748 }
2749
59b47d8a
MC		 2750 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2751 skb_reserve(skb, BNX2_RX_ALIGN - align);
b6016b76 2752
36227e88
SG		 2753 mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_use_size,
2754 PCI_DMA_FROMDEVICE);
2755 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 2756 dev_kfree_skb(skb);
2757 return -EIO;
2758 }
b6016b76
MC		 2759
2760 rx_buf->skb = skb;
a33fa66b 2761 rx_buf->desc = (struct l2_fhdr *) skb->data;
1a4ccc2d 2762 dma_unmap_addr_set(rx_buf, mapping, mapping);
b6016b76
MC		 2763
2764 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2765 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2766
bb4f98ab 2767 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2768
2769 return 0;
2770}
2771
da3e4fbe 2772static int
35efa7c1 2773bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2774{
43e80b89 2775 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76 2776 u32 new_link_state, old_link_state;
da3e4fbe 2777 int is_set = 1;
b6016b76 2778
da3e4fbe
MC		 2779 new_link_state = sblk->status_attn_bits & event;
2780 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2781 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2782 if (new_link_state)
2783 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2784 else
2785 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2786 } else
2787 is_set = 0;
2788
2789 return is_set;
2790}
2791
2792static void
35efa7c1 2793bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2794{
74ecc62d
MC		 2795 spin_lock(&bp->phy_lock);
2796
2797 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2798 bnx2_set_link(bp);
35efa7c1 2799 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2800 bnx2_set_remote_link(bp);
2801
74ecc62d
MC		 2802 spin_unlock(&bp->phy_lock);
2803
b6016b76
MC		 2804}
2805
ead7270b 2806static inline u16
35efa7c1 2807bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2808{
2809 u16 cons;
2810
43e80b89
MC		 2811 /* Tell compiler that status block fields can change. */
2812 barrier();
2813 cons = *bnapi->hw_tx_cons_ptr;
581daf7e 2814 barrier();
ead7270b
MC		 2815 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2816 cons++;
2817 return cons;
2818}
2819
57851d84
MC		 2820static int
2821bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2822{
35e9010b 2823 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
b6016b76 2824 u16 hw_cons, sw_cons, sw_ring_cons;
706bf240
BL		 2825 int tx_pkt = 0, index;
2826 struct netdev_queue *txq;
2827
2828 index = (bnapi - bp->bnx2_napi);
2829 txq = netdev_get_tx_queue(bp->dev, index);
b6016b76 2830
35efa7c1 2831 hw_cons = bnx2_get_hw_tx_cons(bnapi);
35e9010b 2832 sw_cons = txr->tx_cons;
b6016b76
MC		 2833
2834 while (sw_cons != hw_cons) {
3d16af86 2835 struct sw_tx_bd *tx_buf;
b6016b76
MC		 2836 struct sk_buff *skb;
2837 int i, last;
2838
2839 sw_ring_cons = TX_RING_IDX(sw_cons);
2840
35e9010b 2841 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
b6016b76 2842 skb = tx_buf->skb;
1d39ed56 2843
d62fda08
ED		 2844 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2845 prefetch(&skb->end);
2846
b6016b76 2847 /* partial BD completions possible with TSO packets */
d62fda08 2848 if (tx_buf->is_gso) {
b6016b76
MC		 2849 u16 last_idx, last_ring_idx;
2850
d62fda08
ED		 2851 last_idx = sw_cons + tx_buf->nr_frags + 1;
2852 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
b6016b76
MC		 2853 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2854 last_idx++;
2855 }
2856 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2857 break;
2858 }
2859 }
1d39ed56 2860
36227e88 2861 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7 2862 skb_headlen(skb), PCI_DMA_TODEVICE);
b6016b76
MC		 2863
2864 tx_buf->skb = NULL;
d62fda08 2865 last = tx_buf->nr_frags;
b6016b76
MC		 2866
2867 for (i = 0; i < last; i++) {
2868 sw_cons = NEXT_TX_BD(sw_cons);
e95524a7 2869
36227e88 2870 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 2871 dma_unmap_addr(
e95524a7
AD		 2872 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2873 mapping),
2874 skb_shinfo(skb)->frags[i].size,
2875 PCI_DMA_TODEVICE);
b6016b76
MC		 2876 }
2877
2878 sw_cons = NEXT_TX_BD(sw_cons);
2879
745720e5 2880 dev_kfree_skb(skb);
57851d84
MC		 2881 tx_pkt++;
2882 if (tx_pkt == budget)
2883 break;
b6016b76 2884
d62fda08
ED		 2885 if (hw_cons == sw_cons)
2886 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2887 }
2888
35e9010b
MC		 2889 txr->hw_tx_cons = hw_cons;
2890 txr->tx_cons = sw_cons;
706bf240 2891
2f8af120 2892 /* Need to make the tx_cons update visible to bnx2_start_xmit()
706bf240 2893 * before checking for netif_tx_queue_stopped(). Without the
2f8af120
MC		 2894 * memory barrier, there is a small possibility that bnx2_start_xmit()
2895 * will miss it and cause the queue to be stopped forever.
2896 */
2897 smp_mb();
b6016b76 2898
706bf240 2899 if (unlikely(netif_tx_queue_stopped(txq)) &&
35e9010b 2900 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
706bf240
BL		 2901 __netif_tx_lock(txq, smp_processor_id());
2902 if ((netif_tx_queue_stopped(txq)) &&
35e9010b 2903 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
706bf240
BL		 2904 netif_tx_wake_queue(txq);
2905 __netif_tx_unlock(txq);
b6016b76 2906 }
706bf240 2907
57851d84 2908 return tx_pkt;
b6016b76
MC		 2909}
2910
1db82f2a 2911static void
bb4f98ab 2912bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
a1f60190 2913 struct sk_buff *skb, int count)
1db82f2a
MC		 2914{
2915 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2916 struct rx_bd *cons_bd, *prod_bd;
1db82f2a 2917 int i;
3d16af86 2918 u16 hw_prod, prod;
bb4f98ab 2919 u16 cons = rxr->rx_pg_cons;
1db82f2a 2920
3d16af86
BL		 2921 cons_rx_pg = &rxr->rx_pg_ring[cons];
2922
2923 /* The caller was unable to allocate a new page to replace the
2924 * last one in the frags array, so we need to recycle that page
2925 * and then free the skb.
2926 */
2927 if (skb) {
2928 struct page *page;
2929 struct skb_shared_info *shinfo;
2930
2931 shinfo = skb_shinfo(skb);
2932 shinfo->nr_frags--;
b7b6a688
IC		 2933 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]);
2934 __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL);
3d16af86
BL		 2935
2936 cons_rx_pg->page = page;
2937 dev_kfree_skb(skb);
2938 }
2939
2940 hw_prod = rxr->rx_pg_prod;
2941
1db82f2a
MC		 2942 for (i = 0; i < count; i++) {
2943 prod = RX_PG_RING_IDX(hw_prod);
2944
bb4f98ab
MC		 2945 prod_rx_pg = &rxr->rx_pg_ring[prod];
2946 cons_rx_pg = &rxr->rx_pg_ring[cons];
2947 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2948 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1db82f2a 2949
1db82f2a
MC		 2950 if (prod != cons) {
2951 prod_rx_pg->page = cons_rx_pg->page;
2952 cons_rx_pg->page = NULL;
1a4ccc2d
FT		 2953 dma_unmap_addr_set(prod_rx_pg, mapping,
2954 dma_unmap_addr(cons_rx_pg, mapping));
1db82f2a
MC		 2955
2956 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2957 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2958
2959 }
2960 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2961 hw_prod = NEXT_RX_BD(hw_prod);
2962 }
bb4f98ab
MC		 2963 rxr->rx_pg_prod = hw_prod;
2964 rxr->rx_pg_cons = cons;
1db82f2a
MC		 2965}
2966
b6016b76 2967static inline void
bb4f98ab
MC		 2968bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2969 struct sk_buff *skb, u16 cons, u16 prod)
b6016b76 2970{
236b6394
MC		 2971 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2972 struct rx_bd *cons_bd, *prod_bd;
2973
bb4f98ab
MC		 2974 cons_rx_buf = &rxr->rx_buf_ring[cons];
2975 prod_rx_buf = &rxr->rx_buf_ring[prod];
b6016b76 2976
36227e88 2977 dma_sync_single_for_device(&bp->pdev->dev,
1a4ccc2d 2978 dma_unmap_addr(cons_rx_buf, mapping),
601d3d18 2979 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 2980
bb4f98ab 2981 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2982
236b6394 2983 prod_rx_buf->skb = skb;
a33fa66b 2984 prod_rx_buf->desc = (struct l2_fhdr *) skb->data;
b6016b76 2985
236b6394
MC		 2986 if (cons == prod)
2987 return;
b6016b76 2988
1a4ccc2d
FT		 2989 dma_unmap_addr_set(prod_rx_buf, mapping,
2990 dma_unmap_addr(cons_rx_buf, mapping));
236b6394 2991
bb4f98ab
MC		 2992 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2993 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2994 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2995 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2996}
2997
85833c62 2998static int
bb4f98ab 2999bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
a1f60190
MC		 3000 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
3001 u32 ring_idx)
85833c62
MC		 3002{
3003 int err;
3004 u16 prod = ring_idx & 0xffff;
3005
a2df00aa 3006 err = bnx2_alloc_rx_skb(bp, rxr, prod, GFP_ATOMIC);
85833c62 3007 if (unlikely(err)) {
bb4f98ab 3008 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
1db82f2a
MC		 3009 if (hdr_len) {
3010 unsigned int raw_len = len + 4;
3011 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
3012
bb4f98ab 3013 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
1db82f2a 3014 }
85833c62
MC		 3015 return err;
3016 }
3017
d89cb6af 3018 skb_reserve(skb, BNX2_RX_OFFSET);
36227e88 3019 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
85833c62
MC		 3020 PCI_DMA_FROMDEVICE);
3021
1db82f2a
MC		 3022 if (hdr_len == 0) {
3023 skb_put(skb, len);
3024 return 0;
3025 } else {
3026 unsigned int i, frag_len, frag_size, pages;
3027 struct sw_pg *rx_pg;
bb4f98ab
MC		 3028 u16 pg_cons = rxr->rx_pg_cons;
3029 u16 pg_prod = rxr->rx_pg_prod;
1db82f2a
MC		 3030
3031 frag_size = len + 4 - hdr_len;
3032 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3033 skb_put(skb, hdr_len);
3034
3035 for (i = 0; i < pages; i++) {
3d16af86
BL		 3036 dma_addr_t mapping_old;
3037
1db82f2a
MC		 3038 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3039 if (unlikely(frag_len <= 4)) {
3040 unsigned int tail = 4 - frag_len;
3041
bb4f98ab
MC		 3042 rxr->rx_pg_cons = pg_cons;
3043 rxr->rx_pg_prod = pg_prod;
3044 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
a1f60190 3045 pages - i);
1db82f2a
MC		 3046 skb->len -= tail;
3047 if (i == 0) {
3048 skb->tail -= tail;
3049 } else {
3050 skb_frag_t *frag =
3051 &skb_shinfo(skb)->frags[i - 1];
3052 frag->size -= tail;
3053 skb->data_len -= tail;
1db82f2a
MC		 3054 }
3055 return 0;
3056 }
bb4f98ab 3057 rx_pg = &rxr->rx_pg_ring[pg_cons];
1db82f2a 3058
3d16af86
BL		 3059 /* Don't unmap yet. If we're unable to allocate a new
3060 * page, we need to recycle the page and the DMA addr.
3061 */
1a4ccc2d 3062 mapping_old = dma_unmap_addr(rx_pg, mapping);
1db82f2a
MC		 3063 if (i == pages - 1)
3064 frag_len -= 4;
3065
3066 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3067 rx_pg->page = NULL;
3068
bb4f98ab 3069 err = bnx2_alloc_rx_page(bp, rxr,
a2df00aa
SG		 3070 RX_PG_RING_IDX(pg_prod),
3071 GFP_ATOMIC);
1db82f2a 3072 if (unlikely(err)) {
bb4f98ab
MC		 3073 rxr->rx_pg_cons = pg_cons;
3074 rxr->rx_pg_prod = pg_prod;
3075 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
a1f60190 3076 pages - i);
1db82f2a
MC		 3077 return err;
3078 }
3079
36227e88 3080 dma_unmap_page(&bp->pdev->dev, mapping_old,
3d16af86
BL		 3081 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3082
1db82f2a
MC		 3083 frag_size -= frag_len;
3084 skb->data_len += frag_len;
a1f4e8bc 3085 skb->truesize += PAGE_SIZE;
1db82f2a
MC		 3086 skb->len += frag_len;
3087
3088 pg_prod = NEXT_RX_BD(pg_prod);
3089 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3090 }
bb4f98ab
MC		 3091 rxr->rx_pg_prod = pg_prod;
3092 rxr->rx_pg_cons = pg_cons;
1db82f2a 3093 }
85833c62
MC		 3094 return 0;
3095}
3096
c09c2627 3097static inline u16
35efa7c1 3098bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 3099{
bb4f98ab
MC		 3100 u16 cons;
3101
43e80b89
MC		 3102 /* Tell compiler that status block fields can change. */
3103 barrier();
3104 cons = *bnapi->hw_rx_cons_ptr;
581daf7e 3105 barrier();
c09c2627
MC		 3106 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3107 cons++;
3108 return cons;
3109}
3110
b6016b76 3111static int
35efa7c1 3112bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 3113{
bb4f98ab 3114 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76
MC		 3115 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3116 struct l2_fhdr *rx_hdr;
1db82f2a 3117 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 3118
35efa7c1 3119 hw_cons = bnx2_get_hw_rx_cons(bnapi);
bb4f98ab
MC		 3120 sw_cons = rxr->rx_cons;
3121 sw_prod = rxr->rx_prod;
b6016b76
MC		 3122
3123 /* Memory barrier necessary as speculative reads of the rx
3124 * buffer can be ahead of the index in the status block
3125 */
3126 rmb();
3127 while (sw_cons != hw_cons) {
1db82f2a 3128 unsigned int len, hdr_len;
ade2bfe7 3129 u32 status;
a33fa66b 3130 struct sw_bd *rx_buf, *next_rx_buf;
b6016b76 3131 struct sk_buff *skb;
236b6394 3132 dma_addr_t dma_addr;
b6016b76
MC		 3133
3134 sw_ring_cons = RX_RING_IDX(sw_cons);
3135 sw_ring_prod = RX_RING_IDX(sw_prod);
3136
bb4f98ab 3137 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
b6016b76 3138 skb = rx_buf->skb;
a33fa66b 3139 prefetchw(skb);
236b6394 3140
aabef8b2
FT		 3141 next_rx_buf =
3142 &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3143 prefetch(next_rx_buf->desc);
3144
236b6394
MC		 3145 rx_buf->skb = NULL;
3146
1a4ccc2d 3147 dma_addr = dma_unmap_addr(rx_buf, mapping);
236b6394 3148
36227e88 3149 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
601d3d18
BL		 3150 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3151 PCI_DMA_FROMDEVICE);
b6016b76 3152
a33fa66b 3153 rx_hdr = rx_buf->desc;
1db82f2a 3154 len = rx_hdr->l2_fhdr_pkt_len;
990ec380 3155 status = rx_hdr->l2_fhdr_status;
b6016b76 3156
1db82f2a
MC		 3157 hdr_len = 0;
3158 if (status & L2_FHDR_STATUS_SPLIT) {
3159 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3160 pg_ring_used = 1;
3161 } else if (len > bp->rx_jumbo_thresh) {
3162 hdr_len = bp->rx_jumbo_thresh;
3163 pg_ring_used = 1;
3164 }
3165
990ec380
MC		 3166 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3167 L2_FHDR_ERRORS_PHY_DECODE |
3168 L2_FHDR_ERRORS_ALIGNMENT |
3169 L2_FHDR_ERRORS_TOO_SHORT |
3170 L2_FHDR_ERRORS_GIANT_FRAME))) {
3171
3172 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3173 sw_ring_prod);
3174 if (pg_ring_used) {
3175 int pages;
3176
3177 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3178
3179 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3180 }
3181 goto next_rx;
3182 }
3183
1db82f2a 3184 len -= 4;
b6016b76 3185
5d5d0015 3186 if (len <= bp->rx_copy_thresh) {
b6016b76
MC		 3187 struct sk_buff *new_skb;
3188
f22828e8 3189 new_skb = netdev_alloc_skb(bp->dev, len + 6);
85833c62 3190 if (new_skb == NULL) {
bb4f98ab 3191 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
85833c62
MC		 3192 sw_ring_prod);
3193 goto next_rx;
3194 }
b6016b76
MC		 3195
3196 /* aligned copy */
d89cb6af 3197 skb_copy_from_linear_data_offset(skb,
f22828e8
MC		 3198 BNX2_RX_OFFSET - 6,
3199 new_skb->data, len + 6);
3200 skb_reserve(new_skb, 6);
b6016b76 3201 skb_put(new_skb, len);
b6016b76 3202
bb4f98ab 3203 bnx2_reuse_rx_skb(bp, rxr, skb,
b6016b76
MC		 3204 sw_ring_cons, sw_ring_prod);
3205
3206 skb = new_skb;
bb4f98ab 3207 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
a1f60190 3208 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
b6016b76 3209 goto next_rx;
b6016b76 3210
f22828e8 3211 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
7d0fd211
JG		 3212 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
3213 __vlan_hwaccel_put_tag(skb, rx_hdr->l2_fhdr_vlan_tag);
f22828e8 3214
b6016b76
MC		 3215 skb->protocol = eth_type_trans(skb, bp->dev);
3216
3217 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 3218 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 3219
745720e5 3220 dev_kfree_skb(skb);
b6016b76
MC		 3221 goto next_rx;
3222
3223 }
3224
bc8acf2c 3225 skb_checksum_none_assert(skb);
8d7dfc2b 3226 if ((bp->dev->features & NETIF_F_RXCSUM) &&
b6016b76
MC		 3227 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3228 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3229
ade2bfe7
MC		 3230 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3231 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 3232 skb->ip_summed = CHECKSUM_UNNECESSARY;
3233 }
fdc8541d
MC		 3234 if ((bp->dev->features & NETIF_F_RXHASH) &&
3235 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3236 L2_FHDR_STATUS_USE_RXHASH))
3237 skb->rxhash = rx_hdr->l2_fhdr_hash;
b6016b76 3238
0c8dfc83 3239 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
7d0fd211 3240 napi_gro_receive(&bnapi->napi, skb);
b6016b76
MC		 3241 rx_pkt++;
3242
3243next_rx:
b6016b76
MC		 3244 sw_cons = NEXT_RX_BD(sw_cons);
3245 sw_prod = NEXT_RX_BD(sw_prod);
3246
3247 if ((rx_pkt == budget))
3248 break;
f4e418f7
MC		 3249
3250 /* Refresh hw_cons to see if there is new work */
3251 if (sw_cons == hw_cons) {
35efa7c1 3252 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 3253 rmb();
3254 }
b6016b76 3255 }
bb4f98ab
MC		 3256 rxr->rx_cons = sw_cons;
3257 rxr->rx_prod = sw_prod;
b6016b76 3258
1db82f2a 3259 if (pg_ring_used)
bb4f98ab 3260 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
1db82f2a 3261
bb4f98ab 3262 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
b6016b76 3263
bb4f98ab 3264 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 3265
3266 mmiowb();
3267
3268 return rx_pkt;
3269
3270}
3271
3272/* MSI ISR - The only difference between this and the INTx ISR
3273 * is that the MSI interrupt is always serviced.
3274 */
3275static irqreturn_t
7d12e780 3276bnx2_msi(int irq, void *dev_instance)
b6016b76 3277{
f0ea2e63
MC		 3278 struct bnx2_napi *bnapi = dev_instance;
3279 struct bnx2 *bp = bnapi->bp;
b6016b76 3280
43e80b89 3281 prefetch(bnapi->status_blk.msi);
b6016b76
MC		 3282 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3283 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3284 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3285
3286 /* Return here if interrupt is disabled. */
73eef4cd
MC		 3287 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3288 return IRQ_HANDLED;
b6016b76 3289
288379f0 3290 napi_schedule(&bnapi->napi);
b6016b76 3291
73eef4cd 3292 return IRQ_HANDLED;
b6016b76
MC		 3293}
3294
8e6a72c4
MC		 3295static irqreturn_t
3296bnx2_msi_1shot(int irq, void *dev_instance)
3297{
f0ea2e63
MC		 3298 struct bnx2_napi *bnapi = dev_instance;
3299 struct bnx2 *bp = bnapi->bp;
8e6a72c4 3300
43e80b89 3301 prefetch(bnapi->status_blk.msi);
8e6a72c4
MC		 3302
3303 /* Return here if interrupt is disabled. */
3304 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3305 return IRQ_HANDLED;
3306
288379f0 3307 napi_schedule(&bnapi->napi);
8e6a72c4
MC		 3308
3309 return IRQ_HANDLED;
3310}
3311
b6016b76 3312static irqreturn_t
7d12e780 3313bnx2_interrupt(int irq, void *dev_instance)
b6016b76 3314{
f0ea2e63
MC		 3315 struct bnx2_napi *bnapi = dev_instance;
3316 struct bnx2 *bp = bnapi->bp;
43e80b89 3317 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76
MC		 3318
3319 /* When using INTx, it is possible for the interrupt to arrive
3320 * at the CPU before the status block posted prior to the
3321 * interrupt. Reading a register will flush the status block.
3322 * When using MSI, the MSI message will always complete after
3323 * the status block write.
3324 */
35efa7c1 3325 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 3326 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3327 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 3328 return IRQ_NONE;
b6016b76
MC		 3329
3330 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3331 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3332 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3333
b8a7ce7b
MC		 3334 /* Read back to deassert IRQ immediately to avoid too many
3335 * spurious interrupts.
3336 */
3337 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3338
b6016b76 3339 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 3340 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3341 return IRQ_HANDLED;
b6016b76 3342
288379f0 3343 if (napi_schedule_prep(&bnapi->napi)) {
35efa7c1 3344 bnapi->last_status_idx = sblk->status_idx;
288379f0 3345 __napi_schedule(&bnapi->napi);
b8a7ce7b 3346 }
b6016b76 3347
73eef4cd 3348 return IRQ_HANDLED;
b6016b76
MC		 3349}
3350
f4e418f7 3351static inline int
43e80b89 3352bnx2_has_fast_work(struct bnx2_napi *bnapi)
f4e418f7 3353{
35e9010b 3354 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 3355 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
f4e418f7 3356
bb4f98ab 3357 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
35e9010b 3358 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
f4e418f7 3359 return 1;
43e80b89
MC		 3360 return 0;
3361}
3362
3363#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3364 STATUS_ATTN_BITS_TIMER_ABORT)
3365
3366static inline int
3367bnx2_has_work(struct bnx2_napi *bnapi)
3368{
3369 struct status_block *sblk = bnapi->status_blk.msi;
3370
3371 if (bnx2_has_fast_work(bnapi))
3372 return 1;
f4e418f7 3373
4edd473f
MC		 3374#ifdef BCM_CNIC
3375 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3376 return 1;
3377#endif
3378
da3e4fbe
MC		 3379 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3380 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3381 return 1;
3382
3383 return 0;
3384}
3385
efba0180
MC		 3386static void
3387bnx2_chk_missed_msi(struct bnx2 *bp)
3388{
3389 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3390 u32 msi_ctrl;
3391
3392 if (bnx2_has_work(bnapi)) {
3393 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3394 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3395 return;
3396
3397 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3398 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3399 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3400 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3401 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3402 }
3403 }
3404
3405 bp->idle_chk_status_idx = bnapi->last_status_idx;
3406}
3407
4edd473f
MC		 3408#ifdef BCM_CNIC
3409static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3410{
3411 struct cnic_ops *c_ops;
3412
3413 if (!bnapi->cnic_present)
3414 return;
3415
3416 rcu_read_lock();
3417 c_ops = rcu_dereference(bp->cnic_ops);
3418 if (c_ops)
3419 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3420 bnapi->status_blk.msi);
3421 rcu_read_unlock();
3422}
3423#endif
3424
43e80b89 3425static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
b6016b76 3426{
43e80b89 3427 struct status_block *sblk = bnapi->status_blk.msi;
da3e4fbe
MC		 3428 u32 status_attn_bits = sblk->status_attn_bits;
3429 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3430
da3e4fbe
MC		 3431 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3432 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3433
35efa7c1 3434 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3435
3436 /* This is needed to take care of transient status
3437 * during link changes.
3438 */
3439 REG_WR(bp, BNX2_HC_COMMAND,
3440 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3441 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76 3442 }
43e80b89
MC		 3443}
3444
3445static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3446 int work_done, int budget)
3447{
3448 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3449 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76 3450
35e9010b 3451 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
57851d84 3452 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3453
bb4f98ab 3454 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
35efa7c1 3455 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3456
6f535763
DM		 3457 return work_done;
3458}
3459
f0ea2e63
MC		 3460static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3461{
3462 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3463 struct bnx2 *bp = bnapi->bp;
3464 int work_done = 0;
3465 struct status_block_msix *sblk = bnapi->status_blk.msix;
3466
3467 while (1) {
3468 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3469 if (unlikely(work_done >= budget))
3470 break;
3471
3472 bnapi->last_status_idx = sblk->status_idx;
3473 /* status idx must be read before checking for more work. */
3474 rmb();
3475 if (likely(!bnx2_has_fast_work(bnapi))) {
3476
288379f0 3477 napi_complete(napi);
f0ea2e63
MC		 3478 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3479 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3480 bnapi->last_status_idx);
3481 break;
3482 }
3483 }
3484 return work_done;
3485}
3486
6f535763
DM		 3487static int bnx2_poll(struct napi_struct *napi, int budget)
3488{
35efa7c1
MC		 3489 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3490 struct bnx2 *bp = bnapi->bp;
6f535763 3491 int work_done = 0;
43e80b89 3492 struct status_block *sblk = bnapi->status_blk.msi;
6f535763
DM		 3493
3494 while (1) {
43e80b89
MC		 3495 bnx2_poll_link(bp, bnapi);
3496
35efa7c1 3497 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3498
4edd473f
MC		 3499#ifdef BCM_CNIC
3500 bnx2_poll_cnic(bp, bnapi);
3501#endif
3502
35efa7c1 3503 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3504 * much work has been processed, so we must read it before
3505 * checking for more work.
3506 */
35efa7c1 3507 bnapi->last_status_idx = sblk->status_idx;
efba0180
MC		 3508
3509 if (unlikely(work_done >= budget))
3510 break;
3511
6dee6421 3512 rmb();
35efa7c1 3513 if (likely(!bnx2_has_work(bnapi))) {
288379f0 3514 napi_complete(napi);
f86e82fb 3515 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3516 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3517 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3518 bnapi->last_status_idx);
6dee6421 3519 break;
6f535763 3520 }
1269a8a6
MC		 3521 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3522 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3523 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3524 bnapi->last_status_idx);
1269a8a6 3525
6f535763
DM		 3526 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3527 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3528 bnapi->last_status_idx);
6f535763
DM		 3529 break;
3530 }
b6016b76
MC		 3531 }
3532
bea3348e 3533 return work_done;
b6016b76
MC		 3534}
3535
932ff279 3536/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3537 * from set_multicast.
3538 */
3539static void
3540bnx2_set_rx_mode(struct net_device *dev)
3541{
972ec0d4 3542 struct bnx2 *bp = netdev_priv(dev);
b6016b76 3543 u32 rx_mode, sort_mode;
ccffad25 3544 struct netdev_hw_addr *ha;
b6016b76 3545 int i;
b6016b76 3546
9f52b564
MC		 3547 if (!netif_running(dev))
3548 return;
3549
c770a65c 3550 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3551
3552 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3553 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3554 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
7d0fd211
JG		 3555 if (!(dev->features & NETIF_F_HW_VLAN_RX) &&
3556 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
b6016b76 3557 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3558 if (dev->flags & IFF_PROMISC) {
3559 /* Promiscuous mode. */
3560 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3561 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3562 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3563 }
3564 else if (dev->flags & IFF_ALLMULTI) {
3565 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3566 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3567 0xffffffff);
3568 }
3569 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3570 }
3571 else {
3572 /* Accept one or more multicast(s). */
b6016b76
MC		 3573 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3574 u32 regidx;
3575 u32 bit;
3576 u32 crc;
3577
3578 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3579
22bedad3
JP		 3580 netdev_for_each_mc_addr(ha, dev) {
3581 crc = ether_crc_le(ETH_ALEN, ha->addr);
b6016b76
MC		 3582 bit = crc & 0xff;
3583 regidx = (bit & 0xe0) >> 5;
3584 bit &= 0x1f;
3585 mc_filter[regidx] |= (1 << bit);
3586 }
3587
3588 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3589 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3590 mc_filter[i]);
3591 }
3592
3593 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3594 }
3595
32e7bfc4 3596 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
5fcaed01
BL		 3597 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3598 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3599 BNX2_RPM_SORT_USER0_PROM_VLAN;
3600 } else if (!(dev->flags & IFF_PROMISC)) {
5fcaed01 3601 /* Add all entries into to the match filter list */
ccffad25 3602 i = 0;
32e7bfc4 3603 netdev_for_each_uc_addr(ha, dev) {
ccffad25 3604 bnx2_set_mac_addr(bp, ha->addr,
5fcaed01
BL		 3605 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3606 sort_mode |= (1 <<
3607 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
ccffad25 3608 i++;
5fcaed01
BL		 3609 }
3610
3611 }
3612
b6016b76
MC		 3613 if (rx_mode != bp->rx_mode) {
3614 bp->rx_mode = rx_mode;
3615 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3616 }
3617
3618 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3619 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3620 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3621
c770a65c 3622 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3623}
3624
7880b72e 3625static int
57579f76
MC		 3626check_fw_section(const struct firmware *fw,
3627 const struct bnx2_fw_file_section *section,
3628 u32 alignment, bool non_empty)
3629{
3630 u32 offset = be32_to_cpu(section->offset);
3631 u32 len = be32_to_cpu(section->len);
3632
3633 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3634 return -EINVAL;
3635 if ((non_empty && len == 0) || len > fw->size - offset ||
3636 len & (alignment - 1))
3637 return -EINVAL;
3638 return 0;
3639}
3640
7880b72e 3641static int
57579f76
MC		 3642check_mips_fw_entry(const struct firmware *fw,
3643 const struct bnx2_mips_fw_file_entry *entry)
3644{
3645 if (check_fw_section(fw, &entry->text, 4, true) ||
3646 check_fw_section(fw, &entry->data, 4, false) ||
3647 check_fw_section(fw, &entry->rodata, 4, false))
3648 return -EINVAL;
3649 return 0;
3650}
3651
7880b72e 3652static void bnx2_release_firmware(struct bnx2 *bp)
3653{
3654 if (bp->rv2p_firmware) {
3655 release_firmware(bp->mips_firmware);
3656 release_firmware(bp->rv2p_firmware);
3657 bp->rv2p_firmware = NULL;
3658 }
3659}
3660
3661static int bnx2_request_uncached_firmware(struct bnx2 *bp)
b6016b76 3662{
57579f76 3663 const char *mips_fw_file, *rv2p_fw_file;
5ee1c326
BB		 3664 const struct bnx2_mips_fw_file *mips_fw;
3665 const struct bnx2_rv2p_fw_file *rv2p_fw;
57579f76
MC		 3666 int rc;
3667
3668 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3669 mips_fw_file = FW_MIPS_FILE_09;
078b0735
MC		 3670 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3671 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3672 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3673 else
3674 rv2p_fw_file = FW_RV2P_FILE_09;
57579f76
MC		 3675 } else {
3676 mips_fw_file = FW_MIPS_FILE_06;
3677 rv2p_fw_file = FW_RV2P_FILE_06;
3678 }
3679
3680 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3681 if (rc) {
3a9c6a49 3682 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
7880b72e 3683 goto out;
57579f76
MC		 3684 }
3685
3686 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3687 if (rc) {
3a9c6a49 3688 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
7880b72e 3689 goto err_release_mips_firmware;
57579f76 3690 }
5ee1c326
BB		 3691 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3692 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3693 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3694 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3695 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3696 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3697 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3698 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3a9c6a49 3699 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
7880b72e 3700 rc = -EINVAL;
3701 goto err_release_firmware;
57579f76 3702 }
5ee1c326
BB		 3703 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3704 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3705 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3a9c6a49 3706 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
7880b72e 3707 rc = -EINVAL;
3708 goto err_release_firmware;
57579f76 3709 }
7880b72e 3710out:
3711 return rc;
57579f76 3712
7880b72e 3713err_release_firmware:
3714 release_firmware(bp->rv2p_firmware);
3715 bp->rv2p_firmware = NULL;
3716err_release_mips_firmware:
3717 release_firmware(bp->mips_firmware);
3718 goto out;
3719}
3720
3721static int bnx2_request_firmware(struct bnx2 *bp)
3722{
3723 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);
57579f76
MC		 3724}
3725
3726static u32
3727rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3728{
3729 switch (idx) {
3730 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3731 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3732 rv2p_code |= RV2P_BD_PAGE_SIZE;
3733 break;
3734 }
3735 return rv2p_code;
3736}
3737
3738static int
3739load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3740 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3741{
3742 u32 rv2p_code_len, file_offset;
3743 __be32 *rv2p_code;
b6016b76 3744 int i;
57579f76
MC		 3745 u32 val, cmd, addr;
3746
3747 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3748 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3749
3750 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
b6016b76 3751
57579f76
MC		 3752 if (rv2p_proc == RV2P_PROC1) {
3753 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3754 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3755 } else {
3756 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3757 addr = BNX2_RV2P_PROC2_ADDR_CMD;
d25be1d3 3758 }
b6016b76
MC		 3759
3760 for (i = 0; i < rv2p_code_len; i += 8) {
57579f76 3761 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
b6016b76 3762 rv2p_code++;
57579f76 3763 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
b6016b76
MC		 3764 rv2p_code++;
3765
57579f76
MC		 3766 val = (i / 8) | cmd;
3767 REG_WR(bp, addr, val);
3768 }
3769
3770 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3771 for (i = 0; i < 8; i++) {
3772 u32 loc, code;
3773
3774 loc = be32_to_cpu(fw_entry->fixup[i]);
3775 if (loc && ((loc * 4) < rv2p_code_len)) {
3776 code = be32_to_cpu(*(rv2p_code + loc - 1));
3777 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3778 code = be32_to_cpu(*(rv2p_code + loc));
3779 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3780 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3781
3782 val = (loc / 2) | cmd;
3783 REG_WR(bp, addr, val);
b6016b76
MC		 3784 }
3785 }
3786
3787 /* Reset the processor, un-stall is done later. */
3788 if (rv2p_proc == RV2P_PROC1) {
3789 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3790 }
3791 else {
3792 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3793 }
57579f76
MC		 3794
3795 return 0;
b6016b76
MC		 3796}
3797
af3ee519 3798static int
57579f76
MC		 3799load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3800 const struct bnx2_mips_fw_file_entry *fw_entry)
b6016b76 3801{
57579f76
MC		 3802 u32 addr, len, file_offset;
3803 __be32 *data;
b6016b76
MC		 3804 u32 offset;
3805 u32 val;
3806
3807 /* Halt the CPU. */
2726d6e1 3808 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3809 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3810 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3811 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3812
3813 /* Load the Text area. */
57579f76
MC		 3814 addr = be32_to_cpu(fw_entry->text.addr);
3815 len = be32_to_cpu(fw_entry->text.len);
3816 file_offset = be32_to_cpu(fw_entry->text.offset);
3817 data = (__be32 *)(bp->mips_firmware->data + file_offset);
ea1f8d5c 3818
57579f76
MC		 3819 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3820 if (len) {
b6016b76
MC		 3821 int j;
3822
57579f76
MC		 3823 for (j = 0; j < (len / 4); j++, offset += 4)
3824 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3825 }
3826
57579f76
MC		 3827 /* Load the Data area. */
3828 addr = be32_to_cpu(fw_entry->data.addr);
3829 len = be32_to_cpu(fw_entry->data.len);
3830 file_offset = be32_to_cpu(fw_entry->data.offset);
3831 data = (__be32 *)(bp->mips_firmware->data + file_offset);
b6016b76 3832
57579f76
MC		 3833 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3834 if (len) {
b6016b76
MC		 3835 int j;
3836
57579f76
MC		 3837 for (j = 0; j < (len / 4); j++, offset += 4)
3838 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3839 }
3840
3841 /* Load the Read-Only area. */
57579f76
MC		 3842 addr = be32_to_cpu(fw_entry->rodata.addr);
3843 len = be32_to_cpu(fw_entry->rodata.len);
3844 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3845 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3846
3847 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3848 if (len) {
b6016b76
MC		 3849 int j;
3850
57579f76
MC		 3851 for (j = 0; j < (len / 4); j++, offset += 4)
3852 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3853 }
3854
3855 /* Clear the pre-fetch instruction. */
2726d6e1 3856 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
57579f76
MC		 3857
3858 val = be32_to_cpu(fw_entry->start_addr);
3859 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
b6016b76
MC		 3860
3861 /* Start the CPU. */
2726d6e1 3862 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3863 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3864 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3865 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3866
3867 return 0;
b6016b76
MC		 3868}
3869
fba9fe91 3870static int
b6016b76
MC		 3871bnx2_init_cpus(struct bnx2 *bp)
3872{
57579f76
MC		 3873 const struct bnx2_mips_fw_file *mips_fw =
3874 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3875 const struct bnx2_rv2p_fw_file *rv2p_fw =
3876 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3877 int rc;
b6016b76
MC		 3878
3879 /* Initialize the RV2P processor. */
57579f76
MC		 3880 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3881 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
b6016b76
MC		 3882
3883 /* Initialize the RX Processor. */
57579f76 3884 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
fba9fe91
MC		 3885 if (rc)
3886 goto init_cpu_err;
3887
b6016b76 3888 /* Initialize the TX Processor. */
57579f76 3889 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
fba9fe91
MC		 3890 if (rc)
3891 goto init_cpu_err;
3892
b6016b76 3893 /* Initialize the TX Patch-up Processor. */
57579f76 3894 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
fba9fe91
MC		 3895 if (rc)
3896 goto init_cpu_err;
3897
b6016b76 3898 /* Initialize the Completion Processor. */
57579f76 3899 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
fba9fe91
MC		 3900 if (rc)
3901 goto init_cpu_err;
3902
d43584c8 3903 /* Initialize the Command Processor. */
57579f76 3904 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
b6016b76 3905
fba9fe91 3906init_cpu_err:
fba9fe91 3907 return rc;
b6016b76
MC		 3908}
3909
3910static int
829ca9a3 3911bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3912{
3913 u16 pmcsr;
3914
3915 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3916
3917 switch (state) {
829ca9a3 3918 case PCI_D0: {
b6016b76
MC		 3919 u32 val;
3920
3921 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3922 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3923 PCI_PM_CTRL_PME_STATUS);
3924
3925 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3926 /* delay required during transition out of D3hot */
3927 msleep(20);
3928
3929 val = REG_RD(bp, BNX2_EMAC_MODE);
3930 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3931 val &= ~BNX2_EMAC_MODE_MPKT;
3932 REG_WR(bp, BNX2_EMAC_MODE, val);
3933
3934 val = REG_RD(bp, BNX2_RPM_CONFIG);
3935 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3936 REG_WR(bp, BNX2_RPM_CONFIG, val);
3937 break;
3938 }
829ca9a3 3939 case PCI_D3hot: {
b6016b76
MC		 3940 int i;
3941 u32 val, wol_msg;
3942
3943 if (bp->wol) {
3944 u32 advertising;
3945 u8 autoneg;
3946
3947 autoneg = bp->autoneg;
3948 advertising = bp->advertising;
3949
239cd343
MC		 3950 if (bp->phy_port == PORT_TP) {
3951 bp->autoneg = AUTONEG_SPEED;
3952 bp->advertising = ADVERTISED_10baseT_Half |
3953 ADVERTISED_10baseT_Full |
3954 ADVERTISED_100baseT_Half |
3955 ADVERTISED_100baseT_Full |
3956 ADVERTISED_Autoneg;
3957 }
b6016b76 3958
239cd343
MC		 3959 spin_lock_bh(&bp->phy_lock);
3960 bnx2_setup_phy(bp, bp->phy_port);
3961 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3962
3963 bp->autoneg = autoneg;
3964 bp->advertising = advertising;
3965
5fcaed01 3966 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 3967
3968 val = REG_RD(bp, BNX2_EMAC_MODE);
3969
3970 /* Enable port mode. */
3971 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3972 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3973 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3974 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3975 if (bp->phy_port == PORT_TP)
3976 val |= BNX2_EMAC_MODE_PORT_MII;
3977 else {
3978 val |= BNX2_EMAC_MODE_PORT_GMII;
3979 if (bp->line_speed == SPEED_2500)
3980 val |= BNX2_EMAC_MODE_25G_MODE;
3981 }
b6016b76
MC		 3982
3983 REG_WR(bp, BNX2_EMAC_MODE, val);
3984
3985 /* receive all multicast */
3986 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3987 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3988 0xffffffff);
3989 }
3990 REG_WR(bp, BNX2_EMAC_RX_MODE,
3991 BNX2_EMAC_RX_MODE_SORT_MODE);
3992
3993 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3994 BNX2_RPM_SORT_USER0_MC_EN;
3995 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3996 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3997 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3998 BNX2_RPM_SORT_USER0_ENA);
3999
4000 /* Need to enable EMAC and RPM for WOL. */
4001 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4002 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
4003 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
4004 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
4005
4006 val = REG_RD(bp, BNX2_RPM_CONFIG);
4007 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
4008 REG_WR(bp, BNX2_RPM_CONFIG, val);
4009
4010 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4011 }
4012 else {
4013 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4014 }
4015
f86e82fb 4016 if (!(bp->flags & BNX2_FLAG_NO_WOL))
a2f13890
MC		 4017 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
4018 1, 0);
b6016b76
MC		 4019
4020 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4021 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4022 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
4023
4024 if (bp->wol)
4025 pmcsr |= 3;
4026 }
4027 else {
4028 pmcsr |= 3;
4029 }
4030 if (bp->wol) {
4031 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
4032 }
4033 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
4034 pmcsr);
4035
4036 /* No more memory access after this point until
4037 * device is brought back to D0.
4038 */
4039 udelay(50);
4040 break;
4041 }
4042 default:
4043 return -EINVAL;
4044 }
4045 return 0;
4046}
4047
4048static int
4049bnx2_acquire_nvram_lock(struct bnx2 *bp)
4050{
4051 u32 val;
4052 int j;
4053
4054 /* Request access to the flash interface. */
4055 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4056 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4057 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4058 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4059 break;
4060
4061 udelay(5);
4062 }
4063
4064 if (j >= NVRAM_TIMEOUT_COUNT)
4065 return -EBUSY;
4066
4067 return 0;
4068}
4069
4070static int
4071bnx2_release_nvram_lock(struct bnx2 *bp)
4072{
4073 int j;
4074 u32 val;
4075
4076 /* Relinquish nvram interface. */
4077 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4078
4079 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4080 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4081 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4082 break;
4083
4084 udelay(5);
4085 }
4086
4087 if (j >= NVRAM_TIMEOUT_COUNT)
4088 return -EBUSY;
4089
4090 return 0;
4091}
4092
4093
4094static int
4095bnx2_enable_nvram_write(struct bnx2 *bp)
4096{
4097 u32 val;
4098
4099 val = REG_RD(bp, BNX2_MISC_CFG);
4100 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4101
e30372c9 4102 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 4103 int j;
4104
4105 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4106 REG_WR(bp, BNX2_NVM_COMMAND,
4107 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4108
4109 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4110 udelay(5);
4111
4112 val = REG_RD(bp, BNX2_NVM_COMMAND);
4113 if (val & BNX2_NVM_COMMAND_DONE)
4114 break;
4115 }
4116
4117 if (j >= NVRAM_TIMEOUT_COUNT)
4118 return -EBUSY;
4119 }
4120 return 0;
4121}
4122
4123static void
4124bnx2_disable_nvram_write(struct bnx2 *bp)
4125{
4126 u32 val;
4127
4128 val = REG_RD(bp, BNX2_MISC_CFG);
4129 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4130}
4131
4132
4133static void
4134bnx2_enable_nvram_access(struct bnx2 *bp)
4135{
4136 u32 val;
4137
4138 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4139 /* Enable both bits, even on read. */
6aa20a22 4140 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4141 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4142}
4143
4144static void
4145bnx2_disable_nvram_access(struct bnx2 *bp)
4146{
4147 u32 val;
4148
4149 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4150 /* Disable both bits, even after read. */
6aa20a22 4151 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4152 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4153 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4154}
4155
4156static int
4157bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4158{
4159 u32 cmd;
4160 int j;
4161
e30372c9 4162 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 4163 /* Buffered flash, no erase needed */
4164 return 0;
4165
4166 /* Build an erase command */
4167 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4168 BNX2_NVM_COMMAND_DOIT;
4169
4170 /* Need to clear DONE bit separately. */
4171 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4172
4173 /* Address of the NVRAM to read from. */
4174 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4175
4176 /* Issue an erase command. */
4177 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4178
4179 /* Wait for completion. */
4180 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4181 u32 val;
4182
4183 udelay(5);
4184
4185 val = REG_RD(bp, BNX2_NVM_COMMAND);
4186 if (val & BNX2_NVM_COMMAND_DONE)
4187 break;
4188 }
4189
4190 if (j >= NVRAM_TIMEOUT_COUNT)
4191 return -EBUSY;
4192
4193 return 0;
4194}
4195
4196static int
4197bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4198{
4199 u32 cmd;
4200 int j;
4201
4202 /* Build the command word. */
4203 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4204
e30372c9
MC		 4205 /* Calculate an offset of a buffered flash, not needed for 5709. */
4206 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4207 offset = ((offset / bp->flash_info->page_size) <<
4208 bp->flash_info->page_bits) +
4209 (offset % bp->flash_info->page_size);
4210 }
4211
4212 /* Need to clear DONE bit separately. */
4213 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4214
4215 /* Address of the NVRAM to read from. */
4216 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4217
4218 /* Issue a read command. */
4219 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4220
4221 /* Wait for completion. */
4222 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4223 u32 val;
4224
4225 udelay(5);
4226
4227 val = REG_RD(bp, BNX2_NVM_COMMAND);
4228 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 4229 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4230 memcpy(ret_val, &v, 4);
b6016b76
MC		 4231 break;
4232 }
4233 }
4234 if (j >= NVRAM_TIMEOUT_COUNT)
4235 return -EBUSY;
4236
4237 return 0;
4238}
4239
4240
4241static int
4242bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4243{
b491edd5
AV		 4244 u32 cmd;
4245 __be32 val32;
b6016b76
MC		 4246 int j;
4247
4248 /* Build the command word. */
4249 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4250
e30372c9
MC		 4251 /* Calculate an offset of a buffered flash, not needed for 5709. */
4252 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4253 offset = ((offset / bp->flash_info->page_size) <<
4254 bp->flash_info->page_bits) +
4255 (offset % bp->flash_info->page_size);
4256 }
4257
4258 /* Need to clear DONE bit separately. */
4259 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4260
4261 memcpy(&val32, val, 4);
b6016b76
MC		 4262
4263 /* Write the data. */
b491edd5 4264 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 4265
4266 /* Address of the NVRAM to write to. */
4267 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4268
4269 /* Issue the write command. */
4270 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4271
4272 /* Wait for completion. */
4273 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4274 udelay(5);
4275
4276 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4277 break;
4278 }
4279 if (j >= NVRAM_TIMEOUT_COUNT)
4280 return -EBUSY;
4281
4282 return 0;
4283}
4284
4285static int
4286bnx2_init_nvram(struct bnx2 *bp)
4287{
4288 u32 val;
e30372c9 4289 int j, entry_count, rc = 0;
0ced9d01 4290 const struct flash_spec *flash;
b6016b76 4291
e30372c9
MC		 4292 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4293 bp->flash_info = &flash_5709;
4294 goto get_flash_size;
4295 }
4296
b6016b76
MC		 4297 /* Determine the selected interface. */
4298 val = REG_RD(bp, BNX2_NVM_CFG1);
4299
ff8ac609 4300 entry_count = ARRAY_SIZE(flash_table);
b6016b76 4301
b6016b76
MC		 4302 if (val & 0x40000000) {
4303
4304 /* Flash interface has been reconfigured */
4305 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 4306 j++, flash++) {
4307 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4308 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 4309 bp->flash_info = flash;
4310 break;
4311 }
4312 }
4313 }
4314 else {
37137709 4315 u32 mask;
b6016b76
MC		 4316 /* Not yet been reconfigured */
4317
37137709
MC		 4318 if (val & (1 << 23))
4319 mask = FLASH_BACKUP_STRAP_MASK;
4320 else
4321 mask = FLASH_STRAP_MASK;
4322
b6016b76
MC		 4323 for (j = 0, flash = &flash_table[0]; j < entry_count;
4324 j++, flash++) {
4325
37137709 4326 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 4327 bp->flash_info = flash;
4328
4329 /* Request access to the flash interface. */
4330 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4331 return rc;
4332
4333 /* Enable access to flash interface */
4334 bnx2_enable_nvram_access(bp);
4335
4336 /* Reconfigure the flash interface */
4337 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4338 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4339 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4340 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4341
4342 /* Disable access to flash interface */
4343 bnx2_disable_nvram_access(bp);
4344 bnx2_release_nvram_lock(bp);
4345
4346 break;
4347 }
4348 }
4349 } /* if (val & 0x40000000) */
4350
4351 if (j == entry_count) {
4352 bp->flash_info = NULL;
3a9c6a49 4353 pr_alert("Unknown flash/EEPROM type\n");
1122db71 4354 return -ENODEV;
b6016b76
MC		 4355 }
4356
e30372c9 4357get_flash_size:
2726d6e1 4358 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 4359 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4360 if (val)
4361 bp->flash_size = val;
4362 else
4363 bp->flash_size = bp->flash_info->total_size;
4364
b6016b76
MC		 4365 return rc;
4366}
4367
4368static int
4369bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4370 int buf_size)
4371{
4372 int rc = 0;
4373 u32 cmd_flags, offset32, len32, extra;
4374
4375 if (buf_size == 0)
4376 return 0;
4377
4378 /* Request access to the flash interface. */
4379 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4380 return rc;
4381
4382 /* Enable access to flash interface */
4383 bnx2_enable_nvram_access(bp);
4384
4385 len32 = buf_size;
4386 offset32 = offset;
4387 extra = 0;
4388
4389 cmd_flags = 0;
4390
4391 if (offset32 & 3) {
4392 u8 buf[4];
4393 u32 pre_len;
4394
4395 offset32 &= ~3;
4396 pre_len = 4 - (offset & 3);
4397
4398 if (pre_len >= len32) {
4399 pre_len = len32;
4400 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4401 BNX2_NVM_COMMAND_LAST;
4402 }
4403 else {
4404 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4405 }
4406
4407 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4408
4409 if (rc)
4410 return rc;
4411
4412 memcpy(ret_buf, buf + (offset & 3), pre_len);
4413
4414 offset32 += 4;
4415 ret_buf += pre_len;
4416 len32 -= pre_len;
4417 }
4418 if (len32 & 3) {
4419 extra = 4 - (len32 & 3);
4420 len32 = (len32 + 4) & ~3;
4421 }
4422
4423 if (len32 == 4) {
4424 u8 buf[4];
4425
4426 if (cmd_flags)
4427 cmd_flags = BNX2_NVM_COMMAND_LAST;
4428 else
4429 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4430 BNX2_NVM_COMMAND_LAST;
4431
4432 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4433
4434 memcpy(ret_buf, buf, 4 - extra);
4435 }
4436 else if (len32 > 0) {
4437 u8 buf[4];
4438
4439 /* Read the first word. */
4440 if (cmd_flags)
4441 cmd_flags = 0;
4442 else
4443 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4444
4445 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4446
4447 /* Advance to the next dword. */
4448 offset32 += 4;
4449 ret_buf += 4;
4450 len32 -= 4;
4451
4452 while (len32 > 4 && rc == 0) {
4453 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4454
4455 /* Advance to the next dword. */
4456 offset32 += 4;
4457 ret_buf += 4;
4458 len32 -= 4;
4459 }
4460
4461 if (rc)
4462 return rc;
4463
4464 cmd_flags = BNX2_NVM_COMMAND_LAST;
4465 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4466
4467 memcpy(ret_buf, buf, 4 - extra);
4468 }
4469
4470 /* Disable access to flash interface */
4471 bnx2_disable_nvram_access(bp);
4472
4473 bnx2_release_nvram_lock(bp);
4474
4475 return rc;
4476}
4477
4478static int
4479bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4480 int buf_size)
4481{
4482 u32 written, offset32, len32;
e6be763f 4483 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4484 int rc = 0;
4485 int align_start, align_end;
4486
4487 buf = data_buf;
4488 offset32 = offset;
4489 len32 = buf_size;
4490 align_start = align_end = 0;
4491
4492 if ((align_start = (offset32 & 3))) {
4493 offset32 &= ~3;
c873879c
MC		 4494 len32 += align_start;
4495 if (len32 < 4)
4496 len32 = 4;
b6016b76
MC		 4497 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4498 return rc;
4499 }
4500
4501 if (len32 & 3) {
c873879c
MC		 4502 align_end = 4 - (len32 & 3);
4503 len32 += align_end;
4504 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4505 return rc;
b6016b76
MC		 4506 }
4507
4508 if (align_start || align_end) {
e6be763f
MC		 4509 align_buf = kmalloc(len32, GFP_KERNEL);
4510 if (align_buf == NULL)
b6016b76
MC		 4511 return -ENOMEM;
4512 if (align_start) {
e6be763f 4513 memcpy(align_buf, start, 4);
b6016b76
MC		 4514 }
4515 if (align_end) {
e6be763f 4516 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4517 }
e6be763f
MC		 4518 memcpy(align_buf + align_start, data_buf, buf_size);
4519 buf = align_buf;
b6016b76
MC		 4520 }
4521
e30372c9 4522 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4523 flash_buffer = kmalloc(264, GFP_KERNEL);
4524 if (flash_buffer == NULL) {
4525 rc = -ENOMEM;
4526 goto nvram_write_end;
4527 }
4528 }
4529
b6016b76
MC		 4530 written = 0;
4531 while ((written < len32) && (rc == 0)) {
4532 u32 page_start, page_end, data_start, data_end;
4533 u32 addr, cmd_flags;
4534 int i;
b6016b76
MC		 4535
4536 /* Find the page_start addr */
4537 page_start = offset32 + written;
4538 page_start -= (page_start % bp->flash_info->page_size);
4539 /* Find the page_end addr */
4540 page_end = page_start + bp->flash_info->page_size;
4541 /* Find the data_start addr */
4542 data_start = (written == 0) ? offset32 : page_start;
4543 /* Find the data_end addr */
6aa20a22 4544 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4545 (offset32 + len32) : page_end;
4546
4547 /* Request access to the flash interface. */
4548 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4549 goto nvram_write_end;
4550
4551 /* Enable access to flash interface */
4552 bnx2_enable_nvram_access(bp);
4553
4554 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4555 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4556 int j;
4557
4558 /* Read the whole page into the buffer
4559 * (non-buffer flash only) */
4560 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4561 if (j == (bp->flash_info->page_size - 4)) {
4562 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4563 }
4564 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4565 page_start + j,
4566 &flash_buffer[j],
b6016b76
MC		 4567 cmd_flags);
4568
4569 if (rc)
4570 goto nvram_write_end;
4571
4572 cmd_flags = 0;
4573 }
4574 }
4575
4576 /* Enable writes to flash interface (unlock write-protect) */
4577 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4578 goto nvram_write_end;
4579
b6016b76
MC		 4580 /* Loop to write back the buffer data from page_start to
4581 * data_start */
4582 i = 0;
e30372c9 4583 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4584 /* Erase the page */
4585 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4586 goto nvram_write_end;
4587
4588 /* Re-enable the write again for the actual write */
4589 bnx2_enable_nvram_write(bp);
4590
b6016b76
MC		 4591 for (addr = page_start; addr < data_start;
4592 addr += 4, i += 4) {
6aa20a22 4593
b6016b76
MC		 4594 rc = bnx2_nvram_write_dword(bp, addr,
4595 &flash_buffer[i], cmd_flags);
4596
4597 if (rc != 0)
4598 goto nvram_write_end;
4599
4600 cmd_flags = 0;
4601 }
4602 }
4603
4604 /* Loop to write the new data from data_start to data_end */
bae25761 4605 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4606 if ((addr == page_end - 4) ||
e30372c9 4607 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4608 (addr == data_end - 4))) {
4609
4610 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4611 }
4612 rc = bnx2_nvram_write_dword(bp, addr, buf,
4613 cmd_flags);
4614
4615 if (rc != 0)
4616 goto nvram_write_end;
4617
4618 cmd_flags = 0;
4619 buf += 4;
4620 }
4621
4622 /* Loop to write back the buffer data from data_end
4623 * to page_end */
e30372c9 4624 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4625 for (addr = data_end; addr < page_end;
4626 addr += 4, i += 4) {
6aa20a22 4627
b6016b76
MC		 4628 if (addr == page_end-4) {
4629 cmd_flags = BNX2_NVM_COMMAND_LAST;
4630 }
4631 rc = bnx2_nvram_write_dword(bp, addr,
4632 &flash_buffer[i], cmd_flags);
4633
4634 if (rc != 0)
4635 goto nvram_write_end;
4636
4637 cmd_flags = 0;
4638 }
4639 }
4640
4641 /* Disable writes to flash interface (lock write-protect) */
4642 bnx2_disable_nvram_write(bp);
4643
4644 /* Disable access to flash interface */
4645 bnx2_disable_nvram_access(bp);
4646 bnx2_release_nvram_lock(bp);
4647
4648 /* Increment written */
4649 written += data_end - data_start;
4650 }
4651
4652nvram_write_end:
e6be763f
MC		 4653 kfree(flash_buffer);
4654 kfree(align_buf);
b6016b76
MC		 4655 return rc;
4656}
4657
0d8a6571 4658static void
7c62e83b 4659bnx2_init_fw_cap(struct bnx2 *bp)
0d8a6571 4660{
7c62e83b 4661 u32 val, sig = 0;
0d8a6571 4662
583c28e5 4663 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
7c62e83b
MC		 4664 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4665
4666 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4667 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
0d8a6571 4668
2726d6e1 4669 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4670 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4671 return;
4672
7c62e83b
MC		 4673 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4674 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4675 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4676 }
4677
4678 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4679 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4680 u32 link;
4681
583c28e5 4682 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4683
7c62e83b
MC		 4684 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4685 if (link & BNX2_LINK_STATUS_SERDES_LINK)
0d8a6571
MC		 4686 bp->phy_port = PORT_FIBRE;
4687 else
4688 bp->phy_port = PORT_TP;
489310a4 4689
7c62e83b
MC		 4690 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4691 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
0d8a6571 4692 }
7c62e83b
MC		 4693
4694 if (netif_running(bp->dev) && sig)
4695 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
0d8a6571
MC		 4696}
4697
b4b36042
MC		 4698static void
4699bnx2_setup_msix_tbl(struct bnx2 *bp)
4700{
4701 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4702
4703 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4704 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4705}
4706
b6016b76
MC		 4707static int
4708bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4709{
4710 u32 val;
4711 int i, rc = 0;
489310a4 4712 u8 old_port;
b6016b76
MC		 4713
4714 /* Wait for the current PCI transaction to complete before
4715 * issuing a reset. */
a5dac108
EW		 4716 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4717 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
4718 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4719 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4720 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4721 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4722 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4723 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4724 udelay(5);
4725 } else { /* 5709 */
4726 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4727 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4728 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4729 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4730
4731 for (i = 0; i < 100; i++) {
4732 msleep(1);
4733 val = REG_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4734 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4735 break;
4736 }
4737 }
b6016b76 4738
b090ae2b 4739 /* Wait for the firmware to tell us it is ok to issue a reset. */
a2f13890 4740 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
b090ae2b 4741
b6016b76
MC		 4742 /* Deposit a driver reset signature so the firmware knows that
4743 * this is a soft reset. */
2726d6e1
MC		 4744 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4745 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4746
b6016b76
MC		 4747 /* Do a dummy read to force the chip to complete all current transaction
4748 * before we issue a reset. */
4749 val = REG_RD(bp, BNX2_MISC_ID);
4750
234754d5
MC		 4751 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4752 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4753 REG_RD(bp, BNX2_MISC_COMMAND);
4754 udelay(5);
b6016b76 4755
234754d5
MC		 4756 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4757 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4758
be7ff1af 4759 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4760
234754d5
MC		 4761 } else {
4762 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4763 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4764 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4765
4766 /* Chip reset. */
4767 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4768
594a9dfa
MC		 4769 /* Reading back any register after chip reset will hang the
4770 * bus on 5706 A0 and A1. The msleep below provides plenty
4771 * of margin for write posting.
4772 */
234754d5 4773 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4774 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4775 msleep(20);
b6016b76 4776
234754d5
MC		 4777 /* Reset takes approximate 30 usec */
4778 for (i = 0; i < 10; i++) {
4779 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4780 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4781 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4782 break;
4783 udelay(10);
4784 }
4785
4786 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4787 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3a9c6a49 4788 pr_err("Chip reset did not complete\n");
234754d5
MC		 4789 return -EBUSY;
4790 }
b6016b76
MC		 4791 }
4792
4793 /* Make sure byte swapping is properly configured. */
4794 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4795 if (val != 0x01020304) {
3a9c6a49 4796 pr_err("Chip not in correct endian mode\n");
b6016b76
MC		 4797 return -ENODEV;
4798 }
4799
b6016b76 4800 /* Wait for the firmware to finish its initialization. */
a2f13890 4801 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
b090ae2b
MC		 4802 if (rc)
4803 return rc;
b6016b76 4804
0d8a6571 4805 spin_lock_bh(&bp->phy_lock);
489310a4 4806 old_port = bp->phy_port;
7c62e83b 4807 bnx2_init_fw_cap(bp);
583c28e5
MC		 4808 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4809 old_port != bp->phy_port)
0d8a6571
MC		 4810 bnx2_set_default_remote_link(bp);
4811 spin_unlock_bh(&bp->phy_lock);
4812
b6016b76
MC		 4813 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4814 /* Adjust the voltage regular to two steps lower. The default
4815 * of this register is 0x0000000e. */
4816 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4817
4818 /* Remove bad rbuf memory from the free pool. */
4819 rc = bnx2_alloc_bad_rbuf(bp);
4820 }
4821
c441b8d2 4822 if (bp->flags & BNX2_FLAG_USING_MSIX) {
b4b36042 4823 bnx2_setup_msix_tbl(bp);
c441b8d2
MC		 4824 /* Prevent MSIX table reads and write from timing out */
4825 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4826 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4827 }
b4b36042 4828
b6016b76
MC		 4829 return rc;
4830}
4831
4832static int
4833bnx2_init_chip(struct bnx2 *bp)
4834{
d8026d93 4835 u32 val, mtu;
b4b36042 4836 int rc, i;
b6016b76
MC		 4837
4838 /* Make sure the interrupt is not active. */
4839 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4840
4841 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4842 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4843#ifdef __BIG_ENDIAN
6aa20a22 4844 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4845#endif
6aa20a22 4846 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4847 DMA_READ_CHANS << 12 |
4848 DMA_WRITE_CHANS << 16;
4849
4850 val |= (0x2 << 20) | (1 << 11);
4851
f86e82fb 4852 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4853 val |= (1 << 23);
4854
4855 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4856 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4857 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4858
4859 REG_WR(bp, BNX2_DMA_CONFIG, val);
4860
4861 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4862 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4863 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4864 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4865 }
4866
f86e82fb 4867 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4868 u16 val16;
4869
4870 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4871 &val16);
4872 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4873 val16 & ~PCI_X_CMD_ERO);
4874 }
4875
4876 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4877 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4878 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4879 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4880
4881 /* Initialize context mapping and zero out the quick contexts. The
4882 * context block must have already been enabled. */
641bdcd5
MC		 4883 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4884 rc = bnx2_init_5709_context(bp);
4885 if (rc)
4886 return rc;
4887 } else
59b47d8a 4888 bnx2_init_context(bp);
b6016b76 4889
fba9fe91
MC		 4890 if ((rc = bnx2_init_cpus(bp)) != 0)
4891 return rc;
4892
b6016b76
MC		 4893 bnx2_init_nvram(bp);
4894
5fcaed01 4895 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 4896
4897 val = REG_RD(bp, BNX2_MQ_CONFIG);
4898 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4899 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4edd473f
MC		 4900 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4901 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4902 if (CHIP_REV(bp) == CHIP_REV_Ax)
4903 val |= BNX2_MQ_CONFIG_HALT_DIS;
4904 }
68c9f75a 4905
b6016b76
MC		 4906 REG_WR(bp, BNX2_MQ_CONFIG, val);
4907
4908 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4909 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4910 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4911
4912 val = (BCM_PAGE_BITS - 8) << 24;
4913 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4914
4915 /* Configure page size. */
4916 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4917 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4918 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4919 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4920
4921 val = bp->mac_addr[0] +
4922 (bp->mac_addr[1] << 8) +
4923 (bp->mac_addr[2] << 16) +
4924 bp->mac_addr[3] +
4925 (bp->mac_addr[4] << 8) +
4926 (bp->mac_addr[5] << 16);
4927 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4928
4929 /* Program the MTU. Also include 4 bytes for CRC32. */
d8026d93
MC		 4930 mtu = bp->dev->mtu;
4931 val = mtu + ETH_HLEN + ETH_FCS_LEN;
b6016b76
MC		 4932 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4933 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4934 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4935
d8026d93
MC		 4936 if (mtu < 1500)
4937 mtu = 1500;
4938
4939 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4940 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4941 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4942
155d5561 4943 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
b4b36042
MC		 4944 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4945 bp->bnx2_napi[i].last_status_idx = 0;
4946
efba0180
MC		 4947 bp->idle_chk_status_idx = 0xffff;
4948
b6016b76
MC		 4949 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4950
4951 /* Set up how to generate a link change interrupt. */
4952 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4953
4954 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4955 (u64) bp->status_blk_mapping & 0xffffffff);
4956 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4957
4958 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4959 (u64) bp->stats_blk_mapping & 0xffffffff);
4960 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4961 (u64) bp->stats_blk_mapping >> 32);
4962
6aa20a22 4963 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4964 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4965
4966 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4967 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4968
4969 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4970 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4971
4972 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4973
4974 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4975
4976 REG_WR(bp, BNX2_HC_COM_TICKS,
4977 (bp->com_ticks_int << 16) | bp->com_ticks);
4978
4979 REG_WR(bp, BNX2_HC_CMD_TICKS,
4980 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4981
61d9e3fa 4982 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
02537b06
MC		 4983 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4984 else
7ea6920e 4985 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4986 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4987
4988 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4989 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4990 else {
8e6a72c4
MC		 4991 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4992 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4993 }
4994
efde73a3 4995 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4996 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4997 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4998
5e9ad9e1
MC		 4999 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
5000 }
5001
5002 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
cf7474a6 5003 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5e9ad9e1
MC		 5004
5005 REG_WR(bp, BNX2_HC_CONFIG, val);
5006
22fa159d
MC		 5007 if (bp->rx_ticks < 25)
5008 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
5009 else
5010 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
5011
5e9ad9e1
MC		 5012 for (i = 1; i < bp->irq_nvecs; i++) {
5013 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
5014 BNX2_HC_SB_CONFIG_1;
5015
6f743ca0 5016 REG_WR(bp, base,
c76c0475 5017 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5e9ad9e1 5018 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
c76c0475
MC		 5019 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
5020
6f743ca0 5021 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 5022 (bp->tx_quick_cons_trip_int << 16) |
5023 bp->tx_quick_cons_trip);
5024
6f743ca0 5025 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 5026 (bp->tx_ticks_int << 16) | bp->tx_ticks);
5027
5e9ad9e1
MC		 5028 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5029 (bp->rx_quick_cons_trip_int << 16) |
5030 bp->rx_quick_cons_trip);
8e6a72c4 5031
5e9ad9e1
MC		 5032 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
5033 (bp->rx_ticks_int << 16) | bp->rx_ticks);
5034 }
8e6a72c4 5035
b6016b76
MC		 5036 /* Clear internal stats counters. */
5037 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
5038
da3e4fbe 5039 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 5040
5041 /* Initialize the receive filter. */
5042 bnx2_set_rx_mode(bp->dev);
5043
0aa38df7
MC		 5044 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5045 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5046 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5047 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5048 }
b090ae2b 5049 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
a2f13890 5050 1, 0);
b6016b76 5051
df149d70 5052 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 5053 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5054
5055 udelay(20);
5056
bf5295bb
MC		 5057 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5058
b090ae2b 5059 return rc;
b6016b76
MC		 5060}
5061
c76c0475
MC		 5062static void
5063bnx2_clear_ring_states(struct bnx2 *bp)
5064{
5065 struct bnx2_napi *bnapi;
35e9010b 5066 struct bnx2_tx_ring_info *txr;
bb4f98ab 5067 struct bnx2_rx_ring_info *rxr;
c76c0475
MC		 5068 int i;
5069
5070 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5071 bnapi = &bp->bnx2_napi[i];
35e9010b 5072 txr = &bnapi->tx_ring;
bb4f98ab 5073 rxr = &bnapi->rx_ring;
c76c0475 5074
35e9010b
MC		 5075 txr->tx_cons = 0;
5076 txr->hw_tx_cons = 0;
bb4f98ab
MC		 5077 rxr->rx_prod_bseq = 0;
5078 rxr->rx_prod = 0;
5079 rxr->rx_cons = 0;
5080 rxr->rx_pg_prod = 0;
5081 rxr->rx_pg_cons = 0;
c76c0475
MC		 5082 }
5083}
5084
59b47d8a 5085static void
35e9010b 5086bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
59b47d8a
MC		 5087{
5088 u32 val, offset0, offset1, offset2, offset3;
62a8313c 5089 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 5090
5091 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5092 offset0 = BNX2_L2CTX_TYPE_XI;
5093 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5094 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5095 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5096 } else {
5097 offset0 = BNX2_L2CTX_TYPE;
5098 offset1 = BNX2_L2CTX_CMD_TYPE;
5099 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5100 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5101 }
5102 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 5103 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 5104
5105 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 5106 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a 5107
35e9010b 5108 val = (u64) txr->tx_desc_mapping >> 32;
62a8313c 5109 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a 5110
35e9010b 5111 val = (u64) txr->tx_desc_mapping & 0xffffffff;
62a8313c 5112 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 5113}
b6016b76
MC		 5114
5115static void
35e9010b 5116bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
b6016b76
MC		 5117{
5118 struct tx_bd *txbd;
c76c0475
MC		 5119 u32 cid = TX_CID;
5120 struct bnx2_napi *bnapi;
35e9010b 5121 struct bnx2_tx_ring_info *txr;
c76c0475 5122
35e9010b
MC		 5123 bnapi = &bp->bnx2_napi[ring_num];
5124 txr = &bnapi->tx_ring;
5125
5126 if (ring_num == 0)
5127 cid = TX_CID;
5128 else
5129 cid = TX_TSS_CID + ring_num - 1;
b6016b76 5130
2f8af120
MC		 5131 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5132
35e9010b 5133 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 5134
35e9010b
MC		 5135 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5136 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
b6016b76 5137
35e9010b
MC		 5138 txr->tx_prod = 0;
5139 txr->tx_prod_bseq = 0;
6aa20a22 5140
35e9010b
MC		 5141 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5142 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 5143
35e9010b 5144 bnx2_init_tx_context(bp, cid, txr);
b6016b76
MC		 5145}
5146
5147static void
5d5d0015
MC		 5148bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5149 int num_rings)
b6016b76 5150{
b6016b76 5151 int i;
5d5d0015 5152 struct rx_bd *rxbd;
6aa20a22 5153
5d5d0015 5154 for (i = 0; i < num_rings; i++) {
13daffa2 5155 int j;
b6016b76 5156
5d5d0015 5157 rxbd = &rx_ring[i][0];
13daffa2 5158 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 5159 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 5160 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5161 }
5d5d0015 5162 if (i == (num_rings - 1))
13daffa2
MC		 5163 j = 0;
5164 else
5165 j = i + 1;
5d5d0015
MC		 5166 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5167 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 5168 }
5d5d0015
MC		 5169}
5170
5171static void
bb4f98ab 5172bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5d5d0015
MC		 5173{
5174 int i;
5175 u16 prod, ring_prod;
bb4f98ab
MC		 5176 u32 cid, rx_cid_addr, val;
5177 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5178 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5179
5180 if (ring_num == 0)
5181 cid = RX_CID;
5182 else
5183 cid = RX_RSS_CID + ring_num - 1;
5184
5185 rx_cid_addr = GET_CID_ADDR(cid);
5d5d0015 5186
bb4f98ab 5187 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5d5d0015
MC		 5188 bp->rx_buf_use_size, bp->rx_max_ring);
5189
bb4f98ab 5190 bnx2_init_rx_context(bp, cid);
83e3fc89
MC		 5191
5192 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5193 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5194 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5195 }
5196
62a8313c 5197 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246 5198 if (bp->rx_pg_ring_size) {
bb4f98ab
MC		 5199 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5200 rxr->rx_pg_desc_mapping,
47bf4246
MC		 5201 PAGE_SIZE, bp->rx_max_pg_ring);
5202 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 5203 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5204 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5e9ad9e1 5205 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
47bf4246 5206
bb4f98ab 5207 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
62a8313c 5208 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246 5209
bb4f98ab 5210 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 5211 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 5212
5213 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5214 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5215 }
b6016b76 5216
bb4f98ab 5217 val = (u64) rxr->rx_desc_mapping[0] >> 32;
62a8313c 5218 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 5219
bb4f98ab 5220 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
62a8313c 5221 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 5222
bb4f98ab 5223 ring_prod = prod = rxr->rx_pg_prod;
47bf4246 5224 for (i = 0; i < bp->rx_pg_ring_size; i++) {
a2df00aa 5225 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5226 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5227 ring_num, i, bp->rx_pg_ring_size);
47bf4246 5228 break;
b929e53c 5229 }
47bf4246
MC		 5230 prod = NEXT_RX_BD(prod);
5231 ring_prod = RX_PG_RING_IDX(prod);
5232 }
bb4f98ab 5233 rxr->rx_pg_prod = prod;
47bf4246 5234
bb4f98ab 5235 ring_prod = prod = rxr->rx_prod;
236b6394 5236 for (i = 0; i < bp->rx_ring_size; i++) {
a2df00aa 5237 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5238 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5239 ring_num, i, bp->rx_ring_size);
b6016b76 5240 break;
b929e53c 5241 }
b6016b76
MC		 5242 prod = NEXT_RX_BD(prod);
5243 ring_prod = RX_RING_IDX(prod);
5244 }
bb4f98ab 5245 rxr->rx_prod = prod;
b6016b76 5246
bb4f98ab
MC		 5247 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5248 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5249 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
b6016b76 5250
bb4f98ab
MC		 5251 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5252 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5253
5254 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 5255}
5256
35e9010b
MC		 5257static void
5258bnx2_init_all_rings(struct bnx2 *bp)
5259{
5260 int i;
5e9ad9e1 5261 u32 val;
35e9010b
MC		 5262
5263 bnx2_clear_ring_states(bp);
5264
5265 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5266 for (i = 0; i < bp->num_tx_rings; i++)
5267 bnx2_init_tx_ring(bp, i);
5268
5269 if (bp->num_tx_rings > 1)
5270 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5271 (TX_TSS_CID << 7));
5272
5e9ad9e1
MC		 5273 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5274 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5275
bb4f98ab
MC		 5276 for (i = 0; i < bp->num_rx_rings; i++)
5277 bnx2_init_rx_ring(bp, i);
5e9ad9e1
MC		 5278
5279 if (bp->num_rx_rings > 1) {
22fa159d 5280 u32 tbl_32 = 0;
5e9ad9e1
MC		 5281
5282 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
22fa159d
MC		 5283 int shift = (i % 8) << 2;
5284
5285 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
5286 if ((i % 8) == 7) {
5287 REG_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5288 REG_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
5289 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
5290 BNX2_RLUP_RSS_COMMAND_WRITE |
5291 BNX2_RLUP_RSS_COMMAND_HASH_MASK);
5292 tbl_32 = 0;
5293 }
5e9ad9e1
MC		 5294 }
5295
5296 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5297 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5298
5299 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5300
5301 }
35e9010b
MC		 5302}
5303
5d5d0015 5304static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 5305{
5d5d0015 5306 u32 max, num_rings = 1;
13daffa2 5307
5d5d0015
MC		 5308 while (ring_size > MAX_RX_DESC_CNT) {
5309 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 5310 num_rings++;
5311 }
5312 /* round to next power of 2 */
5d5d0015 5313 max = max_size;
13daffa2
MC		 5314 while ((max & num_rings) == 0)
5315 max >>= 1;
5316
5317 if (num_rings != max)
5318 max <<= 1;
5319
5d5d0015
MC		 5320 return max;
5321}
5322
5323static void
5324bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5325{
84eaa187 5326 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 5327
5328 /* 8 for CRC and VLAN */
d89cb6af 5329 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 5330
84eaa187
MC		 5331 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5332 sizeof(struct skb_shared_info);
5333
601d3d18 5334 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 5335 bp->rx_pg_ring_size = 0;
5336 bp->rx_max_pg_ring = 0;
5337 bp->rx_max_pg_ring_idx = 0;
f86e82fb 5338 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 5339 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5340
5341 jumbo_size = size * pages;
5342 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5343 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5344
5345 bp->rx_pg_ring_size = jumbo_size;
5346 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5347 MAX_RX_PG_RINGS);
5348 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
601d3d18 5349 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 5350 bp->rx_copy_thresh = 0;
5351 }
5d5d0015
MC		 5352
5353 bp->rx_buf_use_size = rx_size;
5354 /* hw alignment */
5355 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
d89cb6af 5356 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015
MC		 5357 bp->rx_ring_size = size;
5358 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 5359 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5360}
5361
b6016b76
MC		 5362static void
5363bnx2_free_tx_skbs(struct bnx2 *bp)
5364{
5365 int i;
5366
35e9010b
MC		 5367 for (i = 0; i < bp->num_tx_rings; i++) {
5368 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5369 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5370 int j;
b6016b76 5371
35e9010b 5372 if (txr->tx_buf_ring == NULL)
b6016b76 5373 continue;
b6016b76 5374
35e9010b 5375 for (j = 0; j < TX_DESC_CNT; ) {
3d16af86 5376 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
35e9010b 5377 struct sk_buff *skb = tx_buf->skb;
e95524a7 5378 int k, last;
35e9010b
MC		 5379
5380 if (skb == NULL) {
5381 j++;
5382 continue;
5383 }
5384
36227e88 5385 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5386 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5387 skb_headlen(skb),
5388 PCI_DMA_TODEVICE);
b6016b76 5389
35e9010b 5390 tx_buf->skb = NULL;
b6016b76 5391
e95524a7
AD		 5392 last = tx_buf->nr_frags;
5393 j++;
5394 for (k = 0; k < last; k++, j++) {
5395 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
36227e88 5396 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 5397 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5398 skb_shinfo(skb)->frags[k].size,
5399 PCI_DMA_TODEVICE);
5400 }
35e9010b 5401 dev_kfree_skb(skb);
b6016b76 5402 }
b6016b76 5403 }
b6016b76
MC		 5404}
5405
5406static void
5407bnx2_free_rx_skbs(struct bnx2 *bp)
5408{
5409 int i;
5410
bb4f98ab
MC		 5411 for (i = 0; i < bp->num_rx_rings; i++) {
5412 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5413 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5414 int j;
b6016b76 5415
bb4f98ab
MC		 5416 if (rxr->rx_buf_ring == NULL)
5417 return;
b6016b76 5418
bb4f98ab
MC		 5419 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5420 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5421 struct sk_buff *skb = rx_buf->skb;
b6016b76 5422
bb4f98ab
MC		 5423 if (skb == NULL)
5424 continue;
b6016b76 5425
36227e88 5426 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5427 dma_unmap_addr(rx_buf, mapping),
bb4f98ab
MC		 5428 bp->rx_buf_use_size,
5429 PCI_DMA_FROMDEVICE);
b6016b76 5430
bb4f98ab
MC		 5431 rx_buf->skb = NULL;
5432
5433 dev_kfree_skb(skb);
5434 }
5435 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5436 bnx2_free_rx_page(bp, rxr, j);
b6016b76
MC		 5437 }
5438}
5439
5440static void
5441bnx2_free_skbs(struct bnx2 *bp)
5442{
5443 bnx2_free_tx_skbs(bp);
5444 bnx2_free_rx_skbs(bp);
5445}
5446
5447static int
5448bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5449{
5450 int rc;
5451
5452 rc = bnx2_reset_chip(bp, reset_code);
5453 bnx2_free_skbs(bp);
5454 if (rc)
5455 return rc;
5456
fba9fe91
MC		 5457 if ((rc = bnx2_init_chip(bp)) != 0)
5458 return rc;
5459
35e9010b 5460 bnx2_init_all_rings(bp);
b6016b76
MC		 5461 return 0;
5462}
5463
5464static int
9a120bc5 5465bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 5466{
5467 int rc;
5468
5469 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5470 return rc;
5471
80be4434 5472 spin_lock_bh(&bp->phy_lock);
9a120bc5 5473 bnx2_init_phy(bp, reset_phy);
b6016b76 5474 bnx2_set_link(bp);
543a827d
MC		 5475 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5476 bnx2_remote_phy_event(bp);
0d8a6571 5477 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5478 return 0;
5479}
5480
74bf4ba3
MC		 5481static int
5482bnx2_shutdown_chip(struct bnx2 *bp)
5483{
5484 u32 reset_code;
5485
5486 if (bp->flags & BNX2_FLAG_NO_WOL)
5487 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5488 else if (bp->wol)
5489 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5490 else
5491 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5492
5493 return bnx2_reset_chip(bp, reset_code);
5494}
5495
b6016b76
MC		 5496static int
5497bnx2_test_registers(struct bnx2 *bp)
5498{
5499 int ret;
5bae30c9 5500 int i, is_5709;
f71e1309 5501 static const struct {
b6016b76
MC		 5502 u16 offset;
5503 u16 flags;
5bae30c9 5504#define BNX2_FL_NOT_5709 1
b6016b76
MC		 5505 u32 rw_mask;
5506 u32 ro_mask;
5507 } reg_tbl[] = {
5508 { 0x006c, 0, 0x00000000, 0x0000003f },
5509 { 0x0090, 0, 0xffffffff, 0x00000000 },
5510 { 0x0094, 0, 0x00000000, 0x00000000 },
5511
5bae30c9
MC		 5512 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5513 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5514 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5515 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5516 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5517 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5518 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5519 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5520 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5521
5522 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5523 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5524 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5525 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5526 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5527 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5528
5529 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5530 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5531 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 5532
5533 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 5534 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 5535
5536 { 0x1408, 0, 0x01c00800, 0x00000000 },
5537 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5538 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 5539 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 5540 { 0x14b0, 0, 0x00000002, 0x00000001 },
5541 { 0x14b8, 0, 0x00000000, 0x00000000 },
5542 { 0x14c0, 0, 0x00000000, 0x00000009 },
5543 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5544 { 0x14cc, 0, 0x00000000, 0x00000001 },
5545 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 5546
5547 { 0x1800, 0, 0x00000000, 0x00000001 },
5548 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 5549
5550 { 0x2800, 0, 0x00000000, 0x00000001 },
5551 { 0x2804, 0, 0x00000000, 0x00003f01 },
5552 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5553 { 0x2810, 0, 0xffff0000, 0x00000000 },
5554 { 0x2814, 0, 0xffff0000, 0x00000000 },
5555 { 0x2818, 0, 0xffff0000, 0x00000000 },
5556 { 0x281c, 0, 0xffff0000, 0x00000000 },
5557 { 0x2834, 0, 0xffffffff, 0x00000000 },
5558 { 0x2840, 0, 0x00000000, 0xffffffff },
5559 { 0x2844, 0, 0x00000000, 0xffffffff },
5560 { 0x2848, 0, 0xffffffff, 0x00000000 },
5561 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5562
5563 { 0x2c00, 0, 0x00000000, 0x00000011 },
5564 { 0x2c04, 0, 0x00000000, 0x00030007 },
5565
b6016b76
MC		 5566 { 0x3c00, 0, 0x00000000, 0x00000001 },
5567 { 0x3c04, 0, 0x00000000, 0x00070000 },
5568 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5569 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5570 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5571 { 0x3c14, 0, 0x00000000, 0xffffffff },
5572 { 0x3c18, 0, 0x00000000, 0xffffffff },
5573 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5574 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 5575
5576 { 0x5004, 0, 0x00000000, 0x0000007f },
5577 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 5578
b6016b76
MC		 5579 { 0x5c00, 0, 0x00000000, 0x00000001 },
5580 { 0x5c04, 0, 0x00000000, 0x0003000f },
5581 { 0x5c08, 0, 0x00000003, 0x00000000 },
5582 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5583 { 0x5c10, 0, 0x00000000, 0xffffffff },
5584 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5585 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5586 { 0x5c88, 0, 0x00000000, 0x00077373 },
5587 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5588
5589 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5590 { 0x680c, 0, 0xffffffff, 0x00000000 },
5591 { 0x6810, 0, 0xffffffff, 0x00000000 },
5592 { 0x6814, 0, 0xffffffff, 0x00000000 },
5593 { 0x6818, 0, 0xffffffff, 0x00000000 },
5594 { 0x681c, 0, 0xffffffff, 0x00000000 },
5595 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5596 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5597 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5598 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5599 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5600 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5601 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5602 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5603 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5604 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5605 { 0x684c, 0, 0xffffffff, 0x00000000 },
5606 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5607 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5608 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5609 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5610 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5611 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5612
5613 { 0xffff, 0, 0x00000000, 0x00000000 },
5614 };
5615
5616 ret = 0;
5bae30c9
MC		 5617 is_5709 = 0;
5618 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5619 is_5709 = 1;
5620
b6016b76
MC		 5621 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5622 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5623 u16 flags = reg_tbl[i].flags;
5624
5625 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5626 continue;
b6016b76
MC		 5627
5628 offset = (u32) reg_tbl[i].offset;
5629 rw_mask = reg_tbl[i].rw_mask;
5630 ro_mask = reg_tbl[i].ro_mask;
5631
14ab9b86 5632 save_val = readl(bp->regview + offset);
b6016b76 5633
14ab9b86 5634 writel(0, bp->regview + offset);
b6016b76 5635
14ab9b86 5636 val = readl(bp->regview + offset);
b6016b76
MC		 5637 if ((val & rw_mask) != 0) {
5638 goto reg_test_err;
5639 }
5640
5641 if ((val & ro_mask) != (save_val & ro_mask)) {
5642 goto reg_test_err;
5643 }
5644
14ab9b86 5645 writel(0xffffffff, bp->regview + offset);
b6016b76 5646
14ab9b86 5647 val = readl(bp->regview + offset);
b6016b76
MC		 5648 if ((val & rw_mask) != rw_mask) {
5649 goto reg_test_err;
5650 }
5651
5652 if ((val & ro_mask) != (save_val & ro_mask)) {
5653 goto reg_test_err;
5654 }
5655
14ab9b86 5656 writel(save_val, bp->regview + offset);
b6016b76
MC		 5657 continue;
5658
5659reg_test_err:
14ab9b86 5660 writel(save_val, bp->regview + offset);
b6016b76
MC		 5661 ret = -ENODEV;
5662 break;
5663 }
5664 return ret;
5665}
5666
5667static int
5668bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5669{
f71e1309 5670 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5671 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5672 int i;
5673
5674 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5675 u32 offset;
5676
5677 for (offset = 0; offset < size; offset += 4) {
5678
2726d6e1 5679 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5680
2726d6e1 5681 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5682 test_pattern[i]) {
5683 return -ENODEV;
5684 }
5685 }
5686 }
5687 return 0;
5688}
5689
5690static int
5691bnx2_test_memory(struct bnx2 *bp)
5692{
5693 int ret = 0;
5694 int i;
5bae30c9 5695 static struct mem_entry {
b6016b76
MC		 5696 u32 offset;
5697 u32 len;
5bae30c9 5698 } mem_tbl_5706[] = {
b6016b76 5699 { 0x60000, 0x4000 },
5b0c76ad 5700 { 0xa0000, 0x3000 },
b6016b76
MC		 5701 { 0xe0000, 0x4000 },
5702 { 0x120000, 0x4000 },
5703 { 0x1a0000, 0x4000 },
5704 { 0x160000, 0x4000 },
5705 { 0xffffffff, 0 },
5bae30c9
MC		 5706 },
5707 mem_tbl_5709[] = {
5708 { 0x60000, 0x4000 },
5709 { 0xa0000, 0x3000 },
5710 { 0xe0000, 0x4000 },
5711 { 0x120000, 0x4000 },
5712 { 0x1a0000, 0x4000 },
5713 { 0xffffffff, 0 },
b6016b76 5714 };
5bae30c9
MC		 5715 struct mem_entry *mem_tbl;
5716
5717 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5718 mem_tbl = mem_tbl_5709;
5719 else
5720 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5721
5722 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5723 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5724 mem_tbl[i].len)) != 0) {
5725 return ret;
5726 }
5727 }
6aa20a22 5728
b6016b76
MC		 5729 return ret;
5730}
5731
bc5a0690
MC		 5732#define BNX2_MAC_LOOPBACK 0
5733#define BNX2_PHY_LOOPBACK 1
5734
b6016b76 5735static int
bc5a0690 5736bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5737{
5738 unsigned int pkt_size, num_pkts, i;
5739 struct sk_buff *skb, *rx_skb;
5740 unsigned char *packet;
bc5a0690 5741 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5742 dma_addr_t map;
5743 struct tx_bd *txbd;
5744 struct sw_bd *rx_buf;
5745 struct l2_fhdr *rx_hdr;
5746 int ret = -ENODEV;
c76c0475 5747 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
35e9010b 5748 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 5749 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
c76c0475
MC		 5750
5751 tx_napi = bnapi;
b6016b76 5752
35e9010b 5753 txr = &tx_napi->tx_ring;
bb4f98ab 5754 rxr = &bnapi->rx_ring;
bc5a0690
MC		 5755 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5756 bp->loopback = MAC_LOOPBACK;
5757 bnx2_set_mac_loopback(bp);
5758 }
5759 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5760 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5761 return 0;
5762
80be4434 5763 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5764 bnx2_set_phy_loopback(bp);
5765 }
5766 else
5767 return -EINVAL;
b6016b76 5768
84eaa187 5769 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5770 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5771 if (!skb)
5772 return -ENOMEM;
b6016b76 5773 packet = skb_put(skb, pkt_size);
6634292b 5774 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5775 memset(packet + 6, 0x0, 8);
5776 for (i = 14; i < pkt_size; i++)
5777 packet[i] = (unsigned char) (i & 0xff);
5778
36227e88
SG		 5779 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5780 PCI_DMA_TODEVICE);
5781 if (dma_mapping_error(&bp->pdev->dev, map)) {
3d16af86
BL		 5782 dev_kfree_skb(skb);
5783 return -EIO;
5784 }
b6016b76 5785
bf5295bb
MC		 5786 REG_WR(bp, BNX2_HC_COMMAND,
5787 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5788
b6016b76
MC		 5789 REG_RD(bp, BNX2_HC_COMMAND);
5790
5791 udelay(5);
35efa7c1 5792 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5793
b6016b76
MC		 5794 num_pkts = 0;
5795
35e9010b 5796 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
b6016b76
MC		 5797
5798 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5799 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5800 txbd->tx_bd_mss_nbytes = pkt_size;
5801 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5802
5803 num_pkts++;
35e9010b
MC		 5804 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5805 txr->tx_prod_bseq += pkt_size;
b6016b76 5806
35e9010b
MC		 5807 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5808 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 5809
5810 udelay(100);
5811
bf5295bb
MC		 5812 REG_WR(bp, BNX2_HC_COMMAND,
5813 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5814
b6016b76
MC		 5815 REG_RD(bp, BNX2_HC_COMMAND);
5816
5817 udelay(5);
5818
36227e88 5819 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5820 dev_kfree_skb(skb);
b6016b76 5821
35e9010b 5822 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
b6016b76 5823 goto loopback_test_done;
b6016b76 5824
35efa7c1 5825 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5826 if (rx_idx != rx_start_idx + num_pkts) {
5827 goto loopback_test_done;
5828 }
5829
bb4f98ab 5830 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
b6016b76
MC		 5831 rx_skb = rx_buf->skb;
5832
a33fa66b 5833 rx_hdr = rx_buf->desc;
d89cb6af 5834 skb_reserve(rx_skb, BNX2_RX_OFFSET);
b6016b76 5835
36227e88 5836 dma_sync_single_for_cpu(&bp->pdev->dev,
1a4ccc2d 5837 dma_unmap_addr(rx_buf, mapping),
b6016b76
MC		 5838 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5839
ade2bfe7 5840 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5841 (L2_FHDR_ERRORS_BAD_CRC |
5842 L2_FHDR_ERRORS_PHY_DECODE |
5843 L2_FHDR_ERRORS_ALIGNMENT |
5844 L2_FHDR_ERRORS_TOO_SHORT |
5845 L2_FHDR_ERRORS_GIANT_FRAME)) {
5846
5847 goto loopback_test_done;
5848 }
5849
5850 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5851 goto loopback_test_done;
5852 }
5853
5854 for (i = 14; i < pkt_size; i++) {
5855 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5856 goto loopback_test_done;
5857 }
5858 }
5859
5860 ret = 0;
5861
5862loopback_test_done:
5863 bp->loopback = 0;
5864 return ret;
5865}
5866
bc5a0690
MC		 5867#define BNX2_MAC_LOOPBACK_FAILED 1
5868#define BNX2_PHY_LOOPBACK_FAILED 2
5869#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5870 BNX2_PHY_LOOPBACK_FAILED)
5871
5872static int
5873bnx2_test_loopback(struct bnx2 *bp)
5874{
5875 int rc = 0;
5876
5877 if (!netif_running(bp->dev))
5878 return BNX2_LOOPBACK_FAILED;
5879
5880 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5881 spin_lock_bh(&bp->phy_lock);
9a120bc5 5882 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5883 spin_unlock_bh(&bp->phy_lock);
5884 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5885 rc |= BNX2_MAC_LOOPBACK_FAILED;
5886 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5887 rc |= BNX2_PHY_LOOPBACK_FAILED;
5888 return rc;
5889}
5890
b6016b76
MC		 5891#define NVRAM_SIZE 0x200
5892#define CRC32_RESIDUAL 0xdebb20e3
5893
5894static int
5895bnx2_test_nvram(struct bnx2 *bp)
5896{
b491edd5 5897 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5898 u8 *data = (u8 *) buf;
5899 int rc = 0;
5900 u32 magic, csum;
5901
5902 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5903 goto test_nvram_done;
5904
5905 magic = be32_to_cpu(buf[0]);
5906 if (magic != 0x669955aa) {
5907 rc = -ENODEV;
5908 goto test_nvram_done;
5909 }
5910
5911 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5912 goto test_nvram_done;
5913
5914 csum = ether_crc_le(0x100, data);
5915 if (csum != CRC32_RESIDUAL) {
5916 rc = -ENODEV;
5917 goto test_nvram_done;
5918 }
5919
5920 csum = ether_crc_le(0x100, data + 0x100);
5921 if (csum != CRC32_RESIDUAL) {
5922 rc = -ENODEV;
5923 }
5924
5925test_nvram_done:
5926 return rc;
5927}
5928
5929static int
5930bnx2_test_link(struct bnx2 *bp)
5931{
5932 u32 bmsr;
5933
9f52b564
MC		 5934 if (!netif_running(bp->dev))
5935 return -ENODEV;
5936
583c28e5 5937 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5938 if (bp->link_up)
5939 return 0;
5940 return -ENODEV;
5941 }
c770a65c 5942 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5943 bnx2_enable_bmsr1(bp);
5944 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5945 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5946 bnx2_disable_bmsr1(bp);
c770a65c 5947 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5948
b6016b76
MC		 5949 if (bmsr & BMSR_LSTATUS) {
5950 return 0;
5951 }
5952 return -ENODEV;
5953}
5954
5955static int
5956bnx2_test_intr(struct bnx2 *bp)
5957{
5958 int i;
b6016b76
MC		 5959 u16 status_idx;
5960
5961 if (!netif_running(bp->dev))
5962 return -ENODEV;
5963
5964 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5965
5966 /* This register is not touched during run-time. */
bf5295bb 5967 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5968 REG_RD(bp, BNX2_HC_COMMAND);
5969
5970 for (i = 0; i < 10; i++) {
5971 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5972 status_idx) {
5973
5974 break;
5975 }
5976
5977 msleep_interruptible(10);
5978 }
5979 if (i < 10)
5980 return 0;
5981
5982 return -ENODEV;
5983}
5984
38ea3686 5985/* Determining link for parallel detection. */
b2fadeae
MC		 5986static int
5987bnx2_5706_serdes_has_link(struct bnx2 *bp)
5988{
5989 u32 mode_ctl, an_dbg, exp;
5990
38ea3686
MC		 5991 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5992 return 0;
5993
b2fadeae
MC		 5994 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5995 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5996
5997 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5998 return 0;
5999
6000 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6001 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
6002 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
6003
f3014c0c 6004 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 6005 return 0;
6006
6007 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
6008 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6009 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6010
6011 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
6012 return 0;
6013
6014 return 1;
6015}
6016
b6016b76 6017static void
48b01e2d 6018bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 6019{
b2fadeae
MC		 6020 int check_link = 1;
6021
48b01e2d 6022 spin_lock(&bp->phy_lock);
b2fadeae 6023 if (bp->serdes_an_pending) {
48b01e2d 6024 bp->serdes_an_pending--;
b2fadeae
MC		 6025 check_link = 0;
6026 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 6027 u32 bmcr;
b6016b76 6028
ac392abc 6029 bp->current_interval = BNX2_TIMER_INTERVAL;
cd339a0e 6030
ca58c3af 6031 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6032
48b01e2d 6033 if (bmcr & BMCR_ANENABLE) {
b2fadeae 6034 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 6035 bmcr &= ~BMCR_ANENABLE;
6036 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 6037 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 6038 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 6039 }
b6016b76 6040 }
48b01e2d
MC		 6041 }
6042 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 6043 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 6044 u32 phy2;
b6016b76 6045
48b01e2d
MC		 6046 bnx2_write_phy(bp, 0x17, 0x0f01);
6047 bnx2_read_phy(bp, 0x15, &phy2);
6048 if (phy2 & 0x20) {
6049 u32 bmcr;
cd339a0e 6050
ca58c3af 6051 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 6052 bmcr |= BMCR_ANENABLE;
ca58c3af 6053 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 6054
583c28e5 6055 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 6056 }
6057 } else
ac392abc 6058 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6059
a2724e25 6060 if (check_link) {
b2fadeae
MC		 6061 u32 val;
6062
6063 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6064 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6065 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6066
a2724e25
MC		 6067 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6068 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6069 bnx2_5706s_force_link_dn(bp, 1);
6070 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6071 } else
6072 bnx2_set_link(bp);
6073 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6074 bnx2_set_link(bp);
b2fadeae 6075 }
48b01e2d
MC		 6076 spin_unlock(&bp->phy_lock);
6077}
b6016b76 6078
f8dd064e
MC		 6079static void
6080bnx2_5708_serdes_timer(struct bnx2 *bp)
6081{
583c28e5 6082 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 6083 return;
6084
583c28e5 6085 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 6086 bp->serdes_an_pending = 0;
6087 return;
6088 }
b6016b76 6089
f8dd064e
MC		 6090 spin_lock(&bp->phy_lock);
6091 if (bp->serdes_an_pending)
6092 bp->serdes_an_pending--;
6093 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6094 u32 bmcr;
b6016b76 6095
ca58c3af 6096 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 6097 if (bmcr & BMCR_ANENABLE) {
605a9e20 6098 bnx2_enable_forced_2g5(bp);
40105c0b 6099 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
f8dd064e 6100 } else {
605a9e20 6101 bnx2_disable_forced_2g5(bp);
f8dd064e 6102 bp->serdes_an_pending = 2;
ac392abc 6103 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6104 }
b6016b76 6105
f8dd064e 6106 } else
ac392abc 6107 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6108
f8dd064e
MC		 6109 spin_unlock(&bp->phy_lock);
6110}
6111
48b01e2d
MC		 6112static void
6113bnx2_timer(unsigned long data)
6114{
6115 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 6116
48b01e2d
MC		 6117 if (!netif_running(bp->dev))
6118 return;
b6016b76 6119
48b01e2d
MC		 6120 if (atomic_read(&bp->intr_sem) != 0)
6121 goto bnx2_restart_timer;
b6016b76 6122
efba0180
MC		 6123 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6124 BNX2_FLAG_USING_MSI)
6125 bnx2_chk_missed_msi(bp);
6126
df149d70 6127 bnx2_send_heart_beat(bp);
b6016b76 6128
2726d6e1
MC		 6129 bp->stats_blk->stat_FwRxDrop =
6130 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 6131
02537b06 6132 /* workaround occasional corrupted counters */
61d9e3fa 6133 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
02537b06
MC		 6134 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6135 BNX2_HC_COMMAND_STATS_NOW);
6136
583c28e5 6137 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 6138 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6139 bnx2_5706_serdes_timer(bp);
27a005b8 6140 else
f8dd064e 6141 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 6142 }
6143
6144bnx2_restart_timer:
cd339a0e 6145 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6146}
6147
8e6a72c4
MC		 6148static int
6149bnx2_request_irq(struct bnx2 *bp)
6150{
6d866ffc 6151 unsigned long flags;
b4b36042
MC		 6152 struct bnx2_irq *irq;
6153 int rc = 0, i;
8e6a72c4 6154
f86e82fb 6155 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 6156 flags = 0;
6157 else
6158 flags = IRQF_SHARED;
b4b36042
MC		 6159
6160 for (i = 0; i < bp->irq_nvecs; i++) {
6161 irq = &bp->irq_tbl[i];
c76c0475 6162 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
f0ea2e63 6163 &bp->bnx2_napi[i]);
b4b36042
MC		 6164 if (rc)
6165 break;
6166 irq->requested = 1;
6167 }
8e6a72c4
MC		 6168 return rc;
6169}
6170
6171static void
a29ba9d2 6172__bnx2_free_irq(struct bnx2 *bp)
8e6a72c4 6173{
b4b36042
MC		 6174 struct bnx2_irq *irq;
6175 int i;
8e6a72c4 6176
b4b36042
MC		 6177 for (i = 0; i < bp->irq_nvecs; i++) {
6178 irq = &bp->irq_tbl[i];
6179 if (irq->requested)
f0ea2e63 6180 free_irq(irq->vector, &bp->bnx2_napi[i]);
b4b36042 6181 irq->requested = 0;
6d866ffc 6182 }
a29ba9d2
MC		 6183}
6184
6185static void
6186bnx2_free_irq(struct bnx2 *bp)
6187{
6188
6189 __bnx2_free_irq(bp);
f86e82fb 6190 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 6191 pci_disable_msi(bp->pdev);
f86e82fb 6192 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 6193 pci_disable_msix(bp->pdev);
6194
f86e82fb 6195 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 6196}
6197
6198static void
5e9ad9e1 6199bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
b4b36042 6200{
379b39a2 6201 int i, total_vecs, rc;
57851d84 6202 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
4e1d0de9
MC		 6203 struct net_device *dev = bp->dev;
6204 const int len = sizeof(bp->irq_tbl[0].name);
57851d84 6205
b4b36042
MC		 6206 bnx2_setup_msix_tbl(bp);
6207 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6208 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6209 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84 6210
e2eb8e38
BL		 6211 /* Need to flush the previous three writes to ensure MSI-X
6212 * is setup properly */
6213 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6214
57851d84
MC		 6215 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6216 msix_ent[i].entry = i;
6217 msix_ent[i].vector = 0;
6218 }
6219
379b39a2
MC		 6220 total_vecs = msix_vecs;
6221#ifdef BCM_CNIC
6222 total_vecs++;
6223#endif
6224 rc = -ENOSPC;
6225 while (total_vecs >= BNX2_MIN_MSIX_VEC) {
6226 rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
6227 if (rc <= 0)
6228 break;
6229 if (rc > 0)
6230 total_vecs = rc;
6231 }
6232
57851d84
MC		 6233 if (rc != 0)
6234 return;
6235
379b39a2
MC		 6236 msix_vecs = total_vecs;
6237#ifdef BCM_CNIC
6238 msix_vecs--;
6239#endif
5e9ad9e1 6240 bp->irq_nvecs = msix_vecs;
f86e82fb 6241 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
379b39a2 6242 for (i = 0; i < total_vecs; i++) {
57851d84 6243 bp->irq_tbl[i].vector = msix_ent[i].vector;
69010313
MC		 6244 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6245 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6246 }
6d866ffc
MC		 6247}
6248
657d92fe 6249static int
6d866ffc
MC		 6250bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6251{
5e9ad9e1 6252 int cpus = num_online_cpus();
706bf240 6253 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5e9ad9e1 6254
6d866ffc
MC		 6255 bp->irq_tbl[0].handler = bnx2_interrupt;
6256 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 6257 bp->irq_nvecs = 1;
6258 bp->irq_tbl[0].vector = bp->pdev->irq;
6259
3d5f3a7b 6260 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5e9ad9e1 6261 bnx2_enable_msix(bp, msix_vecs);
6d866ffc 6262
f86e82fb
DM		 6263 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6264 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 6265 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 6266 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 6267 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 6268 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 6269 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6270 } else
6271 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 6272
6273 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 6274 }
6275 }
706bf240
BL		 6276
6277 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
657d92fe 6278 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
706bf240 6279
5e9ad9e1 6280 bp->num_rx_rings = bp->irq_nvecs;
657d92fe 6281 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
8e6a72c4
MC		 6282}
6283
b6016b76
MC		 6284/* Called with rtnl_lock */
6285static int
6286bnx2_open(struct net_device *dev)
6287{
972ec0d4 6288 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6289 int rc;
6290
7880b72e 6291 rc = bnx2_request_firmware(bp);
6292 if (rc < 0)
6293 goto out;
6294
1b2f922f
MC		 6295 netif_carrier_off(dev);
6296
829ca9a3 6297 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 6298 bnx2_disable_int(bp);
6299
657d92fe
BH		 6300 rc = bnx2_setup_int_mode(bp, disable_msi);
6301 if (rc)
6302 goto open_err;
4327ba43 6303 bnx2_init_napi(bp);
35e9010b 6304 bnx2_napi_enable(bp);
b6016b76 6305 rc = bnx2_alloc_mem(bp);
2739a8bb
MC		 6306 if (rc)
6307 goto open_err;
b6016b76 6308
8e6a72c4 6309 rc = bnx2_request_irq(bp);
2739a8bb
MC		 6310 if (rc)
6311 goto open_err;
b6016b76 6312
9a120bc5 6313 rc = bnx2_init_nic(bp, 1);
2739a8bb
MC		 6314 if (rc)
6315 goto open_err;
6aa20a22 6316
cd339a0e 6317 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6318
6319 atomic_set(&bp->intr_sem, 0);
6320
354fcd77
MC		 6321 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6322
b6016b76
MC		 6323 bnx2_enable_int(bp);
6324
f86e82fb 6325 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 6326 /* Test MSI to make sure it is working
6327 * If MSI test fails, go back to INTx mode
6328 */
6329 if (bnx2_test_intr(bp) != 0) {
3a9c6a49 6330 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
b6016b76
MC		 6331
6332 bnx2_disable_int(bp);
8e6a72c4 6333 bnx2_free_irq(bp);
b6016b76 6334
6d866ffc
MC		 6335 bnx2_setup_int_mode(bp, 1);
6336
9a120bc5 6337 rc = bnx2_init_nic(bp, 0);
b6016b76 6338
8e6a72c4
MC		 6339 if (!rc)
6340 rc = bnx2_request_irq(bp);
6341
b6016b76 6342 if (rc) {
b6016b76 6343 del_timer_sync(&bp->timer);
2739a8bb 6344 goto open_err;
b6016b76
MC		 6345 }
6346 bnx2_enable_int(bp);
6347 }
6348 }
f86e82fb 6349 if (bp->flags & BNX2_FLAG_USING_MSI)
3a9c6a49 6350 netdev_info(dev, "using MSI\n");
f86e82fb 6351 else if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49 6352 netdev_info(dev, "using MSIX\n");
b6016b76 6353
706bf240 6354 netif_tx_start_all_queues(dev);
7880b72e 6355out:
6356 return rc;
2739a8bb
MC		 6357
6358open_err:
6359 bnx2_napi_disable(bp);
6360 bnx2_free_skbs(bp);
6361 bnx2_free_irq(bp);
6362 bnx2_free_mem(bp);
f048fa9c 6363 bnx2_del_napi(bp);
7880b72e 6364 bnx2_release_firmware(bp);
6365 goto out;
b6016b76
MC		 6366}
6367
6368static void
c4028958 6369bnx2_reset_task(struct work_struct *work)
b6016b76 6370{
c4028958 6371 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
cd634019 6372 int rc;
b6016b76 6373
51bf6bb4
MC		 6374 rtnl_lock();
6375 if (!netif_running(bp->dev)) {
6376 rtnl_unlock();
afdc08b9 6377 return;
51bf6bb4 6378 }
afdc08b9 6379
212f9934 6380 bnx2_netif_stop(bp, true);
b6016b76 6381
cd634019
MC		 6382 rc = bnx2_init_nic(bp, 1);
6383 if (rc) {
6384 netdev_err(bp->dev, "failed to reset NIC, closing\n");
6385 bnx2_napi_enable(bp);
6386 dev_close(bp->dev);
6387 rtnl_unlock();
6388 return;
6389 }
b6016b76
MC		 6390
6391 atomic_set(&bp->intr_sem, 1);
212f9934 6392 bnx2_netif_start(bp, true);
51bf6bb4 6393 rtnl_unlock();
b6016b76
MC		 6394}
6395
20175c57
MC		 6396static void
6397bnx2_dump_state(struct bnx2 *bp)
6398{
6399 struct net_device *dev = bp->dev;
ecdbf6e0 6400 u32 val1, val2;
5804a8fb
MC		 6401
6402 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6403 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6404 atomic_read(&bp->intr_sem), val1);
6405 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6406 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6407 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
b98eba52 6408 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
3a9c6a49 6409 REG_RD(bp, BNX2_EMAC_TX_STATUS),
b98eba52
EW		 6410 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6411 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
3a9c6a49 6412 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
3a9c6a49
JP		 6413 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6414 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
20175c57 6415 if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49
JP		 6416 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6417 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
20175c57
MC		 6418}
6419
b6016b76
MC		 6420static void
6421bnx2_tx_timeout(struct net_device *dev)
6422{
972ec0d4 6423 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6424
20175c57 6425 bnx2_dump_state(bp);
ecdbf6e0 6426 bnx2_dump_mcp_state(bp);
20175c57 6427
b6016b76
MC		 6428 /* This allows the netif to be shutdown gracefully before resetting */
6429 schedule_work(&bp->reset_task);
6430}
6431
932ff279 6432/* Called with netif_tx_lock.
2f8af120
MC		 6433 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6434 * netif_wake_queue().
b6016b76 6435 */
61357325 6436static netdev_tx_t
b6016b76
MC		 6437bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6438{
972ec0d4 6439 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6440 dma_addr_t mapping;
6441 struct tx_bd *txbd;
3d16af86 6442 struct sw_tx_bd *tx_buf;
b6016b76
MC		 6443 u32 len, vlan_tag_flags, last_frag, mss;
6444 u16 prod, ring_prod;
6445 int i;
706bf240
BL		 6446 struct bnx2_napi *bnapi;
6447 struct bnx2_tx_ring_info *txr;
6448 struct netdev_queue *txq;
6449
6450 /* Determine which tx ring we will be placed on */
6451 i = skb_get_queue_mapping(skb);
6452 bnapi = &bp->bnx2_napi[i];
6453 txr = &bnapi->tx_ring;
6454 txq = netdev_get_tx_queue(dev, i);
b6016b76 6455
35e9010b 6456 if (unlikely(bnx2_tx_avail(bp, txr) <
a550c99b 6457 (skb_shinfo(skb)->nr_frags + 1))) {
706bf240 6458 netif_tx_stop_queue(txq);
3a9c6a49 6459 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
b6016b76
MC		 6460
6461 return NETDEV_TX_BUSY;
6462 }
6463 len = skb_headlen(skb);
35e9010b 6464 prod = txr->tx_prod;
b6016b76
MC		 6465 ring_prod = TX_RING_IDX(prod);
6466
6467 vlan_tag_flags = 0;
84fa7933 6468 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 6469 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6470 }
6471
eab6d18d 6472 if (vlan_tx_tag_present(skb)) {
b6016b76
MC		 6473 vlan_tag_flags |=
6474 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6475 }
7d0fd211 6476
fde82055 6477 if ((mss = skb_shinfo(skb)->gso_size)) {
a1efb4b6 6478 u32 tcp_opt_len;
eddc9ec5 6479 struct iphdr *iph;
b6016b76 6480
b6016b76
MC		 6481 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6482
4666f87a
MC		 6483 tcp_opt_len = tcp_optlen(skb);
6484
6485 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6486 u32 tcp_off = skb_transport_offset(skb) -
6487 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 6488
4666f87a
MC		 6489 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6490 TX_BD_FLAGS_SW_FLAGS;
6491 if (likely(tcp_off == 0))
6492 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6493 else {
6494 tcp_off >>= 3;
6495 vlan_tag_flags |= ((tcp_off & 0x3) <<
6496 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6497 ((tcp_off & 0x10) <<
6498 TX_BD_FLAGS_TCP6_OFF4_SHL);
6499 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6500 }
6501 } else {
4666f87a 6502 iph = ip_hdr(skb);
4666f87a
MC		 6503 if (tcp_opt_len || (iph->ihl > 5)) {
6504 vlan_tag_flags |= ((iph->ihl - 5) +
6505 (tcp_opt_len >> 2)) << 8;
6506 }
b6016b76 6507 }
4666f87a 6508 } else
b6016b76 6509 mss = 0;
b6016b76 6510
36227e88
SG		 6511 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
6512 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 6513 dev_kfree_skb(skb);
6514 return NETDEV_TX_OK;
6515 }
6516
35e9010b 6517 tx_buf = &txr->tx_buf_ring[ring_prod];
b6016b76 6518 tx_buf->skb = skb;
1a4ccc2d 6519 dma_unmap_addr_set(tx_buf, mapping, mapping);
b6016b76 6520
35e9010b 6521 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6522
6523 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6524 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6525 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6526 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6527
6528 last_frag = skb_shinfo(skb)->nr_frags;
d62fda08
ED		 6529 tx_buf->nr_frags = last_frag;
6530 tx_buf->is_gso = skb_is_gso(skb);
b6016b76
MC		 6531
6532 for (i = 0; i < last_frag; i++) {
6533 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6534
6535 prod = NEXT_TX_BD(prod);
6536 ring_prod = TX_RING_IDX(prod);
35e9010b 6537 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6538
6539 len = frag->size;
b7b6a688 6540 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,
5d6bcdfe 6541 DMA_TO_DEVICE);
36227e88 6542 if (dma_mapping_error(&bp->pdev->dev, mapping))
e95524a7 6543 goto dma_error;
1a4ccc2d 6544 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
e95524a7 6545 mapping);
b6016b76
MC		 6546
6547 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6548 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6549 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6550 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6551
6552 }
6553 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6554
6555 prod = NEXT_TX_BD(prod);
35e9010b 6556 txr->tx_prod_bseq += skb->len;
b6016b76 6557
35e9010b
MC		 6558 REG_WR16(bp, txr->tx_bidx_addr, prod);
6559 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 6560
6561 mmiowb();
6562
35e9010b 6563 txr->tx_prod = prod;
b6016b76 6564
35e9010b 6565 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
706bf240 6566 netif_tx_stop_queue(txq);
11848b96
MC		 6567
6568 /* netif_tx_stop_queue() must be done before checking
6569 * tx index in bnx2_tx_avail() below, because in
6570 * bnx2_tx_int(), we update tx index before checking for
6571 * netif_tx_queue_stopped().
6572 */
6573 smp_mb();
35e9010b 6574 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
706bf240 6575 netif_tx_wake_queue(txq);
b6016b76
MC		 6576 }
6577
e95524a7
AD		 6578 return NETDEV_TX_OK;
6579dma_error:
6580 /* save value of frag that failed */
6581 last_frag = i;
6582
6583 /* start back at beginning and unmap skb */
6584 prod = txr->tx_prod;
6585 ring_prod = TX_RING_IDX(prod);
6586 tx_buf = &txr->tx_buf_ring[ring_prod];
6587 tx_buf->skb = NULL;
36227e88 6588 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6589 skb_headlen(skb), PCI_DMA_TODEVICE);
6590
6591 /* unmap remaining mapped pages */
6592 for (i = 0; i < last_frag; i++) {
6593 prod = NEXT_TX_BD(prod);
6594 ring_prod = TX_RING_IDX(prod);
6595 tx_buf = &txr->tx_buf_ring[ring_prod];
36227e88 6596 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6597 skb_shinfo(skb)->frags[i].size,
6598 PCI_DMA_TODEVICE);
6599 }
6600
6601 dev_kfree_skb(skb);
b6016b76
MC		 6602 return NETDEV_TX_OK;
6603}
6604
6605/* Called with rtnl_lock */
6606static int
6607bnx2_close(struct net_device *dev)
6608{
972ec0d4 6609 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6610
bea3348e 6611 bnx2_disable_int_sync(bp);
35efa7c1 6612 bnx2_napi_disable(bp);
b6016b76 6613 del_timer_sync(&bp->timer);
74bf4ba3 6614 bnx2_shutdown_chip(bp);
8e6a72c4 6615 bnx2_free_irq(bp);
b6016b76
MC		 6616 bnx2_free_skbs(bp);
6617 bnx2_free_mem(bp);
f048fa9c 6618 bnx2_del_napi(bp);
b6016b76
MC		 6619 bp->link_up = 0;
6620 netif_carrier_off(bp->dev);
829ca9a3 6621 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 6622 return 0;
6623}
6624
354fcd77
MC		 6625static void
6626bnx2_save_stats(struct bnx2 *bp)
6627{
6628 u32 *hw_stats = (u32 *) bp->stats_blk;
6629 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6630 int i;
6631
6632 /* The 1st 10 counters are 64-bit counters */
6633 for (i = 0; i < 20; i += 2) {
6634 u32 hi;
6635 u64 lo;
6636
c9885fe5
PR		 6637 hi = temp_stats[i] + hw_stats[i];
6638 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
354fcd77
MC		 6639 if (lo > 0xffffffff)
6640 hi++;
c9885fe5
PR		 6641 temp_stats[i] = hi;
6642 temp_stats[i + 1] = lo & 0xffffffff;
354fcd77
MC		 6643 }
6644
6645 for ( ; i < sizeof(struct statistics_block) / 4; i++)
c9885fe5 6646 temp_stats[i] += hw_stats[i];
354fcd77
MC		 6647}
6648
5d07bf26
ED		 6649#define GET_64BIT_NET_STATS64(ctr) \
6650 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
b6016b76 6651
a4743058 6652#define GET_64BIT_NET_STATS(ctr) \
354fcd77
MC		 6653 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6654 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
b6016b76 6655
a4743058 6656#define GET_32BIT_NET_STATS(ctr) \
354fcd77
MC		 6657 (unsigned long) (bp->stats_blk->ctr + \
6658 bp->temp_stats_blk->ctr)
a4743058 6659
5d07bf26
ED		 6660static struct rtnl_link_stats64 *
6661bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
b6016b76 6662{
972ec0d4 6663 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6664
5d07bf26 6665 if (bp->stats_blk == NULL)
b6016b76 6666 return net_stats;
5d07bf26 6667
b6016b76 6668 net_stats->rx_packets =
a4743058
MC		 6669 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6670 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6671 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
b6016b76
MC		 6672
6673 net_stats->tx_packets =
a4743058
MC		 6674 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6675 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6676 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
b6016b76
MC		 6677
6678 net_stats->rx_bytes =
a4743058 6679 GET_64BIT_NET_STATS(stat_IfHCInOctets);
b6016b76
MC		 6680
6681 net_stats->tx_bytes =
a4743058 6682 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
b6016b76 6683
6aa20a22 6684 net_stats->multicast =
6fdae995 6685 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
b6016b76 6686
6aa20a22 6687 net_stats->collisions =
a4743058 6688 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
b6016b76 6689
6aa20a22 6690 net_stats->rx_length_errors =
a4743058
MC		 6691 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6692 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
b6016b76 6693
6aa20a22 6694 net_stats->rx_over_errors =
a4743058
MC		 6695 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6696 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
b6016b76 6697
6aa20a22 6698 net_stats->rx_frame_errors =
a4743058 6699 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
b6016b76 6700
6aa20a22 6701 net_stats->rx_crc_errors =
a4743058 6702 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
b6016b76
MC		 6703
6704 net_stats->rx_errors = net_stats->rx_length_errors +
6705 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6706 net_stats->rx_crc_errors;
6707
6708 net_stats->tx_aborted_errors =
a4743058
MC		 6709 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6710 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
b6016b76 6711
5b0c76ad
MC		 6712 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6713 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 6714 net_stats->tx_carrier_errors = 0;
6715 else {
6716 net_stats->tx_carrier_errors =
a4743058 6717 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
b6016b76
MC		 6718 }
6719
6720 net_stats->tx_errors =
a4743058 6721 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
b6016b76
MC		 6722 net_stats->tx_aborted_errors +
6723 net_stats->tx_carrier_errors;
6724
cea94db9 6725 net_stats->rx_missed_errors =
a4743058
MC		 6726 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6727 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6728 GET_32BIT_NET_STATS(stat_FwRxDrop);
cea94db9 6729
b6016b76
MC		 6730 return net_stats;
6731}
6732
6733/* All ethtool functions called with rtnl_lock */
6734
6735static int
6736bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6737{
972ec0d4 6738 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6739 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6740
6741 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6742 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6743 support_serdes = 1;
6744 support_copper = 1;
6745 } else if (bp->phy_port == PORT_FIBRE)
6746 support_serdes = 1;
6747 else
6748 support_copper = 1;
6749
6750 if (support_serdes) {
b6016b76
MC		 6751 cmd->supported |= SUPPORTED_1000baseT_Full |
6752 SUPPORTED_FIBRE;
583c28e5 6753 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6754 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6755
b6016b76 6756 }
7b6b8347 6757 if (support_copper) {
b6016b76
MC		 6758 cmd->supported |= SUPPORTED_10baseT_Half |
6759 SUPPORTED_10baseT_Full |
6760 SUPPORTED_100baseT_Half |
6761 SUPPORTED_100baseT_Full |
6762 SUPPORTED_1000baseT_Full |
6763 SUPPORTED_TP;
6764
b6016b76
MC		 6765 }
6766
7b6b8347
MC		 6767 spin_lock_bh(&bp->phy_lock);
6768 cmd->port = bp->phy_port;
b6016b76
MC		 6769 cmd->advertising = bp->advertising;
6770
6771 if (bp->autoneg & AUTONEG_SPEED) {
6772 cmd->autoneg = AUTONEG_ENABLE;
70739497 6773 } else {
b6016b76
MC		 6774 cmd->autoneg = AUTONEG_DISABLE;
6775 }
6776
6777 if (netif_carrier_ok(dev)) {
70739497 6778 ethtool_cmd_speed_set(cmd, bp->line_speed);
b6016b76
MC		 6779 cmd->duplex = bp->duplex;
6780 }
6781 else {
70739497 6782 ethtool_cmd_speed_set(cmd, -1);
b6016b76
MC		 6783 cmd->duplex = -1;
6784 }
7b6b8347 6785 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6786
6787 cmd->transceiver = XCVR_INTERNAL;
6788 cmd->phy_address = bp->phy_addr;
6789
6790 return 0;
6791}
6aa20a22 6792
b6016b76
MC		 6793static int
6794bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6795{
972ec0d4 6796 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6797 u8 autoneg = bp->autoneg;
6798 u8 req_duplex = bp->req_duplex;
6799 u16 req_line_speed = bp->req_line_speed;
6800 u32 advertising = bp->advertising;
7b6b8347
MC		 6801 int err = -EINVAL;
6802
6803 spin_lock_bh(&bp->phy_lock);
6804
6805 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6806 goto err_out_unlock;
6807
583c28e5
MC		 6808 if (cmd->port != bp->phy_port &&
6809 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6810 goto err_out_unlock;
b6016b76 6811
d6b14486
MC		 6812 /* If device is down, we can store the settings only if the user
6813 * is setting the currently active port.
6814 */
6815 if (!netif_running(dev) && cmd->port != bp->phy_port)
6816 goto err_out_unlock;
6817
b6016b76
MC		 6818 if (cmd->autoneg == AUTONEG_ENABLE) {
6819 autoneg |= AUTONEG_SPEED;
6820
beb499af
MC		 6821 advertising = cmd->advertising;
6822 if (cmd->port == PORT_TP) {
6823 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6824 if (!advertising)
b6016b76 6825 advertising = ETHTOOL_ALL_COPPER_SPEED;
beb499af
MC		 6826 } else {
6827 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6828 if (!advertising)
6829 advertising = ETHTOOL_ALL_FIBRE_SPEED;
b6016b76
MC		 6830 }
6831 advertising |= ADVERTISED_Autoneg;
6832 }
6833 else {
25db0338 6834 u32 speed = ethtool_cmd_speed(cmd);
7b6b8347 6835 if (cmd->port == PORT_FIBRE) {
25db0338
DD		 6836 if ((speed != SPEED_1000 &&
6837 speed != SPEED_2500) ||
80be4434 6838 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6839 goto err_out_unlock;
80be4434 6840
25db0338 6841 if (speed == SPEED_2500 &&
583c28e5 6842 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6843 goto err_out_unlock;
25db0338 6844 } else if (speed == SPEED_1000 || speed == SPEED_2500)
7b6b8347
MC		 6845 goto err_out_unlock;
6846
b6016b76 6847 autoneg &= ~AUTONEG_SPEED;
25db0338 6848 req_line_speed = speed;
b6016b76
MC		 6849 req_duplex = cmd->duplex;
6850 advertising = 0;
6851 }
6852
6853 bp->autoneg = autoneg;
6854 bp->advertising = advertising;
6855 bp->req_line_speed = req_line_speed;
6856 bp->req_duplex = req_duplex;
6857
d6b14486
MC		 6858 err = 0;
6859 /* If device is down, the new settings will be picked up when it is
6860 * brought up.
6861 */
6862 if (netif_running(dev))
6863 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6864
7b6b8347 6865err_out_unlock:
c770a65c 6866 spin_unlock_bh(&bp->phy_lock);
b6016b76 6867
7b6b8347 6868 return err;
b6016b76
MC		 6869}
6870
6871static void
6872bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6873{
972ec0d4 6874 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6875
6876 strcpy(info->driver, DRV_MODULE_NAME);
6877 strcpy(info->version, DRV_MODULE_VERSION);
6878 strcpy(info->bus_info, pci_name(bp->pdev));
58fc2ea4 6879 strcpy(info->fw_version, bp->fw_version);
b6016b76
MC		 6880}
6881
244ac4f4
MC		 6882#define BNX2_REGDUMP_LEN (32 * 1024)
6883
6884static int
6885bnx2_get_regs_len(struct net_device *dev)
6886{
6887 return BNX2_REGDUMP_LEN;
6888}
6889
6890static void
6891bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6892{
6893 u32 *p = _p, i, offset;
6894 u8 *orig_p = _p;
6895 struct bnx2 *bp = netdev_priv(dev);
b6bc7650
JP		 6896 static const u32 reg_boundaries[] = {
6897 0x0000, 0x0098, 0x0400, 0x045c,
6898 0x0800, 0x0880, 0x0c00, 0x0c10,
6899 0x0c30, 0x0d08, 0x1000, 0x101c,
6900 0x1040, 0x1048, 0x1080, 0x10a4,
6901 0x1400, 0x1490, 0x1498, 0x14f0,
6902 0x1500, 0x155c, 0x1580, 0x15dc,
6903 0x1600, 0x1658, 0x1680, 0x16d8,
6904 0x1800, 0x1820, 0x1840, 0x1854,
6905 0x1880, 0x1894, 0x1900, 0x1984,
6906 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6907 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6908 0x2000, 0x2030, 0x23c0, 0x2400,
6909 0x2800, 0x2820, 0x2830, 0x2850,
6910 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6911 0x3c00, 0x3c94, 0x4000, 0x4010,
6912 0x4080, 0x4090, 0x43c0, 0x4458,
6913 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6914 0x4fc0, 0x5010, 0x53c0, 0x5444,
6915 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6916 0x5fc0, 0x6000, 0x6400, 0x6428,
6917 0x6800, 0x6848, 0x684c, 0x6860,
6918 0x6888, 0x6910, 0x8000
6919 };
244ac4f4
MC		 6920
6921 regs->version = 0;
6922
6923 memset(p, 0, BNX2_REGDUMP_LEN);
6924
6925 if (!netif_running(bp->dev))
6926 return;
6927
6928 i = 0;
6929 offset = reg_boundaries[0];
6930 p += offset;
6931 while (offset < BNX2_REGDUMP_LEN) {
6932 *p++ = REG_RD(bp, offset);
6933 offset += 4;
6934 if (offset == reg_boundaries[i + 1]) {
6935 offset = reg_boundaries[i + 2];
6936 p = (u32 *) (orig_p + offset);
6937 i += 2;
6938 }
6939 }
6940}
6941
b6016b76
MC		 6942static void
6943bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6944{
972ec0d4 6945 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6946
f86e82fb 6947 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6948 wol->supported = 0;
6949 wol->wolopts = 0;
6950 }
6951 else {
6952 wol->supported = WAKE_MAGIC;
6953 if (bp->wol)
6954 wol->wolopts = WAKE_MAGIC;
6955 else
6956 wol->wolopts = 0;
6957 }
6958 memset(&wol->sopass, 0, sizeof(wol->sopass));
6959}
6960
6961static int
6962bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6963{
972ec0d4 6964 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6965
6966 if (wol->wolopts & ~WAKE_MAGIC)
6967 return -EINVAL;
6968
6969 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6970 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6971 return -EINVAL;
6972
6973 bp->wol = 1;
6974 }
6975 else {
6976 bp->wol = 0;
6977 }
6978 return 0;
6979}
6980
6981static int
6982bnx2_nway_reset(struct net_device *dev)
6983{
972ec0d4 6984 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6985 u32 bmcr;
6986
9f52b564
MC		 6987 if (!netif_running(dev))
6988 return -EAGAIN;
6989
b6016b76
MC		 6990 if (!(bp->autoneg & AUTONEG_SPEED)) {
6991 return -EINVAL;
6992 }
6993
c770a65c 6994 spin_lock_bh(&bp->phy_lock);
b6016b76 6995
583c28e5 6996 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6997 int rc;
6998
6999 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
7000 spin_unlock_bh(&bp->phy_lock);
7001 return rc;
7002 }
7003
b6016b76 7004 /* Force a link down visible on the other side */
583c28e5 7005 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 7006 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 7007 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7008
7009 msleep(20);
7010
c770a65c 7011 spin_lock_bh(&bp->phy_lock);
f8dd064e 7012
40105c0b 7013 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 7014 bp->serdes_an_pending = 1;
7015 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 7016 }
7017
ca58c3af 7018 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 7019 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 7020 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 7021
c770a65c 7022 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7023
7024 return 0;
7025}
7026
7959ea25
ON		 7027static u32
7028bnx2_get_link(struct net_device *dev)
7029{
7030 struct bnx2 *bp = netdev_priv(dev);
7031
7032 return bp->link_up;
7033}
7034
b6016b76
MC		 7035static int
7036bnx2_get_eeprom_len(struct net_device *dev)
7037{
972ec0d4 7038 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7039
1122db71 7040 if (bp->flash_info == NULL)
b6016b76
MC		 7041 return 0;
7042
1122db71 7043 return (int) bp->flash_size;
b6016b76
MC		 7044}
7045
7046static int
7047bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7048 u8 *eebuf)
7049{
972ec0d4 7050 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7051 int rc;
7052
9f52b564
MC		 7053 if (!netif_running(dev))
7054 return -EAGAIN;
7055
1064e944 7056 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 7057
7058 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7059
7060 return rc;
7061}
7062
7063static int
7064bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7065 u8 *eebuf)
7066{
972ec0d4 7067 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7068 int rc;
7069
9f52b564
MC		 7070 if (!netif_running(dev))
7071 return -EAGAIN;
7072
1064e944 7073 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 7074
7075 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7076
7077 return rc;
7078}
7079
7080static int
7081bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7082{
972ec0d4 7083 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7084
7085 memset(coal, 0, sizeof(struct ethtool_coalesce));
7086
7087 coal->rx_coalesce_usecs = bp->rx_ticks;
7088 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7089 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7090 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7091
7092 coal->tx_coalesce_usecs = bp->tx_ticks;
7093 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7094 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7095 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7096
7097 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7098
7099 return 0;
7100}
7101
7102static int
7103bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7104{
972ec0d4 7105 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7106
7107 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7108 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7109
6aa20a22 7110 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 7111 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7112
7113 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7114 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7115
7116 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7117 if (bp->rx_quick_cons_trip_int > 0xff)
7118 bp->rx_quick_cons_trip_int = 0xff;
7119
7120 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7121 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7122
7123 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7124 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7125
7126 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7127 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7128
7129 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7130 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7131 0xff;
7132
7133 bp->stats_ticks = coal->stats_block_coalesce_usecs;
61d9e3fa 7134 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
02537b06
MC		 7135 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7136 bp->stats_ticks = USEC_PER_SEC;
7137 }
7ea6920e
MC		 7138 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7139 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7140 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7141
7142 if (netif_running(bp->dev)) {
212f9934 7143 bnx2_netif_stop(bp, true);
9a120bc5 7144 bnx2_init_nic(bp, 0);
212f9934 7145 bnx2_netif_start(bp, true);
b6016b76
MC		 7146 }
7147
7148 return 0;
7149}
7150
7151static void
7152bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7153{
972ec0d4 7154 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7155
13daffa2 7156 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
47bf4246 7157 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 7158
7159 ering->rx_pending = bp->rx_ring_size;
47bf4246 7160 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 7161
7162 ering->tx_max_pending = MAX_TX_DESC_CNT;
7163 ering->tx_pending = bp->tx_ring_size;
7164}
7165
7166static int
5d5d0015 7167bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 7168{
13daffa2 7169 if (netif_running(bp->dev)) {
354fcd77
MC		 7170 /* Reset will erase chipset stats; save them */
7171 bnx2_save_stats(bp);
7172
212f9934 7173 bnx2_netif_stop(bp, true);
13daffa2 7174 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
a29ba9d2 7175 __bnx2_free_irq(bp);
13daffa2
MC		 7176 bnx2_free_skbs(bp);
7177 bnx2_free_mem(bp);
7178 }
7179
5d5d0015
MC		 7180 bnx2_set_rx_ring_size(bp, rx);
7181 bp->tx_ring_size = tx;
b6016b76
MC		 7182
7183 if (netif_running(bp->dev)) {
13daffa2
MC		 7184 int rc;
7185
7186 rc = bnx2_alloc_mem(bp);
a29ba9d2
MC		 7187 if (!rc)
7188 rc = bnx2_request_irq(bp);
7189
6fefb65e
MC		 7190 if (!rc)
7191 rc = bnx2_init_nic(bp, 0);
7192
7193 if (rc) {
7194 bnx2_napi_enable(bp);
7195 dev_close(bp->dev);
13daffa2 7196 return rc;
6fefb65e 7197 }
e9f26c49
MC		 7198#ifdef BCM_CNIC
7199 mutex_lock(&bp->cnic_lock);
7200 /* Let cnic know about the new status block. */
7201 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7202 bnx2_setup_cnic_irq_info(bp);
7203 mutex_unlock(&bp->cnic_lock);
7204#endif
212f9934 7205 bnx2_netif_start(bp, true);
b6016b76 7206 }
b6016b76
MC		 7207 return 0;
7208}
7209
5d5d0015
MC		 7210static int
7211bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7212{
7213 struct bnx2 *bp = netdev_priv(dev);
7214 int rc;
7215
7216 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7217 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7218 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7219
7220 return -EINVAL;
7221 }
7222 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7223 return rc;
7224}
7225
b6016b76
MC		 7226static void
7227bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7228{
972ec0d4 7229 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7230
7231 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7232 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7233 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7234}
7235
7236static int
7237bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7238{
972ec0d4 7239 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7240
7241 bp->req_flow_ctrl = 0;
7242 if (epause->rx_pause)
7243 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7244 if (epause->tx_pause)
7245 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7246
7247 if (epause->autoneg) {
7248 bp->autoneg |= AUTONEG_FLOW_CTRL;
7249 }
7250 else {
7251 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7252 }
7253
9f52b564
MC		 7254 if (netif_running(dev)) {
7255 spin_lock_bh(&bp->phy_lock);
7256 bnx2_setup_phy(bp, bp->phy_port);
7257 spin_unlock_bh(&bp->phy_lock);
7258 }
b6016b76
MC		 7259
7260 return 0;
7261}
7262
14ab9b86 7263static struct {
b6016b76 7264 char string[ETH_GSTRING_LEN];
790dab2f 7265} bnx2_stats_str_arr[] = {
b6016b76
MC		 7266 { "rx_bytes" },
7267 { "rx_error_bytes" },
7268 { "tx_bytes" },
7269 { "tx_error_bytes" },
7270 { "rx_ucast_packets" },
7271 { "rx_mcast_packets" },
7272 { "rx_bcast_packets" },
7273 { "tx_ucast_packets" },
7274 { "tx_mcast_packets" },
7275 { "tx_bcast_packets" },
7276 { "tx_mac_errors" },
7277 { "tx_carrier_errors" },
7278 { "rx_crc_errors" },
7279 { "rx_align_errors" },
7280 { "tx_single_collisions" },
7281 { "tx_multi_collisions" },
7282 { "tx_deferred" },
7283 { "tx_excess_collisions" },
7284 { "tx_late_collisions" },
7285 { "tx_total_collisions" },
7286 { "rx_fragments" },
7287 { "rx_jabbers" },
7288 { "rx_undersize_packets" },
7289 { "rx_oversize_packets" },
7290 { "rx_64_byte_packets" },
7291 { "rx_65_to_127_byte_packets" },
7292 { "rx_128_to_255_byte_packets" },
7293 { "rx_256_to_511_byte_packets" },
7294 { "rx_512_to_1023_byte_packets" },
7295 { "rx_1024_to_1522_byte_packets" },
7296 { "rx_1523_to_9022_byte_packets" },
7297 { "tx_64_byte_packets" },
7298 { "tx_65_to_127_byte_packets" },
7299 { "tx_128_to_255_byte_packets" },
7300 { "tx_256_to_511_byte_packets" },
7301 { "tx_512_to_1023_byte_packets" },
7302 { "tx_1024_to_1522_byte_packets" },
7303 { "tx_1523_to_9022_byte_packets" },
7304 { "rx_xon_frames" },
7305 { "rx_xoff_frames" },
7306 { "tx_xon_frames" },
7307 { "tx_xoff_frames" },
7308 { "rx_mac_ctrl_frames" },
7309 { "rx_filtered_packets" },
790dab2f 7310 { "rx_ftq_discards" },
b6016b76 7311 { "rx_discards" },
cea94db9 7312 { "rx_fw_discards" },
b6016b76
MC		 7313};
7314
790dab2f
MC		 7315#define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7316 sizeof(bnx2_stats_str_arr[0]))
7317
b6016b76
MC		 7318#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7319
f71e1309 7320static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7321 STATS_OFFSET32(stat_IfHCInOctets_hi),
7322 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7323 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7324 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7325 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7326 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7327 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7328 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7329 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7330 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7331 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 7332 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7333 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7334 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7335 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7336 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7337 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7338 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7339 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7340 STATS_OFFSET32(stat_EtherStatsCollisions),
7341 STATS_OFFSET32(stat_EtherStatsFragments),
7342 STATS_OFFSET32(stat_EtherStatsJabbers),
7343 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7344 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7345 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7346 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7347 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7348 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7349 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7350 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7351 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7352 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7353 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7354 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7355 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7356 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7357 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7358 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7359 STATS_OFFSET32(stat_XonPauseFramesReceived),
7360 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7361 STATS_OFFSET32(stat_OutXonSent),
7362 STATS_OFFSET32(stat_OutXoffSent),
7363 STATS_OFFSET32(stat_MacControlFramesReceived),
7364 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
790dab2f 7365 STATS_OFFSET32(stat_IfInFTQDiscards),
6aa20a22 7366 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 7367 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 7368};
7369
7370/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7371 * skipped because of errata.
6aa20a22 7372 */
14ab9b86 7373static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7374 8,0,8,8,8,8,8,8,8,8,
7375 4,0,4,4,4,4,4,4,4,4,
7376 4,4,4,4,4,4,4,4,4,4,
7377 4,4,4,4,4,4,4,4,4,4,
790dab2f 7378 4,4,4,4,4,4,4,
b6016b76
MC		 7379};
7380
5b0c76ad
MC		 7381static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7382 8,0,8,8,8,8,8,8,8,8,
7383 4,4,4,4,4,4,4,4,4,4,
7384 4,4,4,4,4,4,4,4,4,4,
7385 4,4,4,4,4,4,4,4,4,4,
790dab2f 7386 4,4,4,4,4,4,4,
5b0c76ad
MC		 7387};
7388
b6016b76
MC		 7389#define BNX2_NUM_TESTS 6
7390
14ab9b86 7391static struct {
b6016b76
MC		 7392 char string[ETH_GSTRING_LEN];
7393} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7394 { "register_test (offline)" },
7395 { "memory_test (offline)" },
7396 { "loopback_test (offline)" },
7397 { "nvram_test (online)" },
7398 { "interrupt_test (online)" },
7399 { "link_test (online)" },
7400};
7401
7402static int
b9f2c044 7403bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 7404{
b9f2c044
JG		 7405 switch (sset) {
7406 case ETH_SS_TEST:
7407 return BNX2_NUM_TESTS;
7408 case ETH_SS_STATS:
7409 return BNX2_NUM_STATS;
7410 default:
7411 return -EOPNOTSUPP;
7412 }
b6016b76
MC		 7413}
7414
7415static void
7416bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7417{
972ec0d4 7418 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7419
9f52b564
MC		 7420 bnx2_set_power_state(bp, PCI_D0);
7421
b6016b76
MC		 7422 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7423 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 7424 int i;
7425
212f9934 7426 bnx2_netif_stop(bp, true);
b6016b76
MC		 7427 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7428 bnx2_free_skbs(bp);
7429
7430 if (bnx2_test_registers(bp) != 0) {
7431 buf[0] = 1;
7432 etest->flags |= ETH_TEST_FL_FAILED;
7433 }
7434 if (bnx2_test_memory(bp) != 0) {
7435 buf[1] = 1;
7436 etest->flags |= ETH_TEST_FL_FAILED;
7437 }
bc5a0690 7438 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 7439 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76 7440
9f52b564
MC		 7441 if (!netif_running(bp->dev))
7442 bnx2_shutdown_chip(bp);
b6016b76 7443 else {
9a120bc5 7444 bnx2_init_nic(bp, 1);
212f9934 7445 bnx2_netif_start(bp, true);
b6016b76
MC		 7446 }
7447
7448 /* wait for link up */
80be4434
MC		 7449 for (i = 0; i < 7; i++) {
7450 if (bp->link_up)
7451 break;
7452 msleep_interruptible(1000);
7453 }
b6016b76
MC		 7454 }
7455
7456 if (bnx2_test_nvram(bp) != 0) {
7457 buf[3] = 1;
7458 etest->flags |= ETH_TEST_FL_FAILED;
7459 }
7460 if (bnx2_test_intr(bp) != 0) {
7461 buf[4] = 1;
7462 etest->flags |= ETH_TEST_FL_FAILED;
7463 }
7464
7465 if (bnx2_test_link(bp) != 0) {
7466 buf[5] = 1;
7467 etest->flags |= ETH_TEST_FL_FAILED;
7468
7469 }
9f52b564
MC		 7470 if (!netif_running(bp->dev))
7471 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 7472}
7473
7474static void
7475bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7476{
7477 switch (stringset) {
7478 case ETH_SS_STATS:
7479 memcpy(buf, bnx2_stats_str_arr,
7480 sizeof(bnx2_stats_str_arr));
7481 break;
7482 case ETH_SS_TEST:
7483 memcpy(buf, bnx2_tests_str_arr,
7484 sizeof(bnx2_tests_str_arr));
7485 break;
7486 }
7487}
7488
b6016b76
MC		 7489static void
7490bnx2_get_ethtool_stats(struct net_device *dev,
7491 struct ethtool_stats *stats, u64 *buf)
7492{
972ec0d4 7493 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7494 int i;
7495 u32 *hw_stats = (u32 *) bp->stats_blk;
354fcd77 7496 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
14ab9b86 7497 u8 *stats_len_arr = NULL;
b6016b76
MC		 7498
7499 if (hw_stats == NULL) {
7500 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7501 return;
7502 }
7503
5b0c76ad
MC		 7504 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7505 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7506 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7507 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 7508 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 7509 else
7510 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 7511
7512 for (i = 0; i < BNX2_NUM_STATS; i++) {
354fcd77
MC		 7513 unsigned long offset;
7514
b6016b76
MC		 7515 if (stats_len_arr[i] == 0) {
7516 /* skip this counter */
7517 buf[i] = 0;
7518 continue;
7519 }
354fcd77
MC		 7520
7521 offset = bnx2_stats_offset_arr[i];
b6016b76
MC		 7522 if (stats_len_arr[i] == 4) {
7523 /* 4-byte counter */
354fcd77
MC		 7524 buf[i] = (u64) *(hw_stats + offset) +
7525 *(temp_stats + offset);
b6016b76
MC		 7526 continue;
7527 }
7528 /* 8-byte counter */
354fcd77
MC		 7529 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7530 *(hw_stats + offset + 1) +
7531 (((u64) *(temp_stats + offset)) << 32) +
7532 *(temp_stats + offset + 1);
b6016b76
MC		 7533 }
7534}
7535
7536static int
2e17e1aa 7537bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state)
b6016b76 7538{
972ec0d4 7539 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7540
2e17e1aa 7541 switch (state) {
7542 case ETHTOOL_ID_ACTIVE:
7543 bnx2_set_power_state(bp, PCI_D0);
9f52b564 7544
2e17e1aa 7545 bp->leds_save = REG_RD(bp, BNX2_MISC_CFG);
7546 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
fce55922 7547 return 1; /* cycle on/off once per second */
b6016b76 7548
2e17e1aa 7549 case ETHTOOL_ID_ON:
7550 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7551 BNX2_EMAC_LED_1000MB_OVERRIDE |
7552 BNX2_EMAC_LED_100MB_OVERRIDE |
7553 BNX2_EMAC_LED_10MB_OVERRIDE |
7554 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7555 BNX2_EMAC_LED_TRAFFIC);
7556 break;
b6016b76 7557
2e17e1aa 7558 case ETHTOOL_ID_OFF:
7559 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7560 break;
9f52b564 7561
2e17e1aa 7562 case ETHTOOL_ID_INACTIVE:
7563 REG_WR(bp, BNX2_EMAC_LED, 0);
7564 REG_WR(bp, BNX2_MISC_CFG, bp->leds_save);
7565
7566 if (!netif_running(dev))
7567 bnx2_set_power_state(bp, PCI_D3hot);
7568 break;
7569 }
9f52b564 7570
b6016b76
MC		 7571 return 0;
7572}
7573
8d7dfc2b
MM		 7574static u32
7575bnx2_fix_features(struct net_device *dev, u32 features)
4666f87a
MC		 7576{
7577 struct bnx2 *bp = netdev_priv(dev);
7578
8d7dfc2b
MM		 7579 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
7580 features |= NETIF_F_HW_VLAN_RX;
7581
7582 return features;
4666f87a
MC		 7583}
7584
fdc8541d 7585static int
8d7dfc2b 7586bnx2_set_features(struct net_device *dev, u32 features)
fdc8541d 7587{
7d0fd211 7588 struct bnx2 *bp = netdev_priv(dev);
7d0fd211 7589
7c810477 7590 /* TSO with VLAN tag won't work with current firmware */
8d7dfc2b
MM		 7591 if (features & NETIF_F_HW_VLAN_TX)
7592 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO);
7593 else
7594 dev->vlan_features &= ~NETIF_F_ALL_TSO;
7d0fd211 7595
8d7dfc2b 7596 if ((!!(features & NETIF_F_HW_VLAN_RX) !=
7d0fd211
JG		 7597 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
7598 netif_running(dev)) {
7599 bnx2_netif_stop(bp, false);
8d7dfc2b 7600 dev->features = features;
7d0fd211
JG		 7601 bnx2_set_rx_mode(dev);
7602 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
7603 bnx2_netif_start(bp, false);
8d7dfc2b 7604 return 1;
7d0fd211
JG		 7605 }
7606
7607 return 0;
fdc8541d
MC		 7608}
7609
7282d491 7610static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 7611 .get_settings = bnx2_get_settings,
7612 .set_settings = bnx2_set_settings,
7613 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 7614 .get_regs_len = bnx2_get_regs_len,
7615 .get_regs = bnx2_get_regs,
b6016b76
MC		 7616 .get_wol = bnx2_get_wol,
7617 .set_wol = bnx2_set_wol,
7618 .nway_reset = bnx2_nway_reset,
7959ea25 7619 .get_link = bnx2_get_link,
b6016b76
MC		 7620 .get_eeprom_len = bnx2_get_eeprom_len,
7621 .get_eeprom = bnx2_get_eeprom,
7622 .set_eeprom = bnx2_set_eeprom,
7623 .get_coalesce = bnx2_get_coalesce,
7624 .set_coalesce = bnx2_set_coalesce,
7625 .get_ringparam = bnx2_get_ringparam,
7626 .set_ringparam = bnx2_set_ringparam,
7627 .get_pauseparam = bnx2_get_pauseparam,
7628 .set_pauseparam = bnx2_set_pauseparam,
b6016b76
MC		 7629 .self_test = bnx2_self_test,
7630 .get_strings = bnx2_get_strings,
2e17e1aa 7631 .set_phys_id = bnx2_set_phys_id,
b6016b76 7632 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 7633 .get_sset_count = bnx2_get_sset_count,
b6016b76
MC		 7634};
7635
7636/* Called with rtnl_lock */
7637static int
7638bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7639{
14ab9b86 7640 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 7641 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7642 int err;
7643
7644 switch(cmd) {
7645 case SIOCGMIIPHY:
7646 data->phy_id = bp->phy_addr;
7647
7648 /* fallthru */
7649 case SIOCGMIIREG: {
7650 u32 mii_regval;
7651
583c28e5 7652 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7653 return -EOPNOTSUPP;
7654
dad3e452
MC		 7655 if (!netif_running(dev))
7656 return -EAGAIN;
7657
c770a65c 7658 spin_lock_bh(&bp->phy_lock);
b6016b76 7659 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 7660 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7661
7662 data->val_out = mii_regval;
7663
7664 return err;
7665 }
7666
7667 case SIOCSMIIREG:
583c28e5 7668 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7669 return -EOPNOTSUPP;
7670
dad3e452
MC		 7671 if (!netif_running(dev))
7672 return -EAGAIN;
7673
c770a65c 7674 spin_lock_bh(&bp->phy_lock);
b6016b76 7675 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 7676 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7677
7678 return err;
7679
7680 default:
7681 /* do nothing */
7682 break;
7683 }
7684 return -EOPNOTSUPP;
7685}
7686
7687/* Called with rtnl_lock */
7688static int
7689bnx2_change_mac_addr(struct net_device *dev, void *p)
7690{
7691 struct sockaddr *addr = p;
972ec0d4 7692 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7693
73eef4cd
MC		 7694 if (!is_valid_ether_addr(addr->sa_data))
7695 return -EINVAL;
7696
b6016b76
MC		 7697 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7698 if (netif_running(dev))
5fcaed01 7699 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 7700
7701 return 0;
7702}
7703
7704/* Called with rtnl_lock */
7705static int
7706bnx2_change_mtu(struct net_device *dev, int new_mtu)
7707{
972ec0d4 7708 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7709
7710 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7711 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7712 return -EINVAL;
7713
7714 dev->mtu = new_mtu;
807540ba 7715 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size);
b6016b76
MC		 7716}
7717
257ddbda 7718#ifdef CONFIG_NET_POLL_CONTROLLER
b6016b76
MC		 7719static void
7720poll_bnx2(struct net_device *dev)
7721{
972ec0d4 7722 struct bnx2 *bp = netdev_priv(dev);
b2af2c1d 7723 int i;
b6016b76 7724
b2af2c1d 7725 for (i = 0; i < bp->irq_nvecs; i++) {
1bf1e347
MC		 7726 struct bnx2_irq *irq = &bp->irq_tbl[i];
7727
7728 disable_irq(irq->vector);
7729 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7730 enable_irq(irq->vector);
b2af2c1d 7731 }
b6016b76
MC		 7732}
7733#endif
7734
253c8b75
MC		 7735static void __devinit
7736bnx2_get_5709_media(struct bnx2 *bp)
7737{
7738 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7739 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7740 u32 strap;
7741
7742 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7743 return;
7744 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7745 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7746 return;
7747 }
7748
7749 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7750 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7751 else
7752 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7753
7754 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7755 switch (strap) {
7756 case 0x4:
7757 case 0x5:
7758 case 0x6:
583c28e5 7759 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7760 return;
7761 }
7762 } else {
7763 switch (strap) {
7764 case 0x1:
7765 case 0x2:
7766 case 0x4:
583c28e5 7767 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7768 return;
7769 }
7770 }
7771}
7772
883e5151
MC		 7773static void __devinit
7774bnx2_get_pci_speed(struct bnx2 *bp)
7775{
7776 u32 reg;
7777
7778 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7779 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7780 u32 clkreg;
7781
f86e82fb 7782 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 7783
7784 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7785
7786 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7787 switch (clkreg) {
7788 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7789 bp->bus_speed_mhz = 133;
7790 break;
7791
7792 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7793 bp->bus_speed_mhz = 100;
7794 break;
7795
7796 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7797 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7798 bp->bus_speed_mhz = 66;
7799 break;
7800
7801 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7802 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7803 bp->bus_speed_mhz = 50;
7804 break;
7805
7806 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7807 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7808 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7809 bp->bus_speed_mhz = 33;
7810 break;
7811 }
7812 }
7813 else {
7814 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7815 bp->bus_speed_mhz = 66;
7816 else
7817 bp->bus_speed_mhz = 33;
7818 }
7819
7820 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7821 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7822
7823}
7824
76d99061
MC		 7825static void __devinit
7826bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7827{
df25bc38 7828 int rc, i, j;
76d99061 7829 u8 *data;
df25bc38 7830 unsigned int block_end, rosize, len;
76d99061 7831
012093f6
MC		 7832#define BNX2_VPD_NVRAM_OFFSET 0x300
7833#define BNX2_VPD_LEN 128
76d99061
MC		 7834#define BNX2_MAX_VER_SLEN 30
7835
7836 data = kmalloc(256, GFP_KERNEL);
7837 if (!data)
7838 return;
7839
012093f6
MC		 7840 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7841 BNX2_VPD_LEN);
76d99061
MC		 7842 if (rc)
7843 goto vpd_done;
7844
012093f6
MC		 7845 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7846 data[i] = data[i + BNX2_VPD_LEN + 3];
7847 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7848 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7849 data[i + 3] = data[i + BNX2_VPD_LEN];
76d99061
MC		 7850 }
7851
df25bc38
MC		 7852 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7853 if (i < 0)
7854 goto vpd_done;
76d99061 7855
df25bc38
MC		 7856 rosize = pci_vpd_lrdt_size(&data[i]);
7857 i += PCI_VPD_LRDT_TAG_SIZE;
7858 block_end = i + rosize;
76d99061 7859
df25bc38
MC		 7860 if (block_end > BNX2_VPD_LEN)
7861 goto vpd_done;
76d99061 7862
df25bc38
MC		 7863 j = pci_vpd_find_info_keyword(data, i, rosize,
7864 PCI_VPD_RO_KEYWORD_MFR_ID);
7865 if (j < 0)
7866 goto vpd_done;
76d99061 7867
df25bc38 7868 len = pci_vpd_info_field_size(&data[j]);
76d99061 7869
df25bc38
MC		 7870 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7871 if (j + len > block_end || len != 4 ||
7872 memcmp(&data[j], "1028", 4))
7873 goto vpd_done;
4067a854 7874
df25bc38
MC		 7875 j = pci_vpd_find_info_keyword(data, i, rosize,
7876 PCI_VPD_RO_KEYWORD_VENDOR0);
7877 if (j < 0)
7878 goto vpd_done;
4067a854 7879
df25bc38 7880 len = pci_vpd_info_field_size(&data[j]);
4067a854 7881
df25bc38
MC		 7882 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7883 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
76d99061 7884 goto vpd_done;
df25bc38
MC		 7885
7886 memcpy(bp->fw_version, &data[j], len);
7887 bp->fw_version[len] = ' ';
76d99061
MC		 7888
7889vpd_done:
7890 kfree(data);
7891}
7892
b6016b76
MC		 7893static int __devinit
7894bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7895{
7896 struct bnx2 *bp;
7897 unsigned long mem_len;
58fc2ea4 7898 int rc, i, j;
b6016b76 7899 u32 reg;
40453c83 7900 u64 dma_mask, persist_dma_mask;
cd709aa9 7901 int err;
b6016b76 7902
b6016b76 7903 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7904 bp = netdev_priv(dev);
b6016b76
MC		 7905
7906 bp->flags = 0;
7907 bp->phy_flags = 0;
7908
354fcd77
MC		 7909 bp->temp_stats_blk =
7910 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7911
7912 if (bp->temp_stats_blk == NULL) {
7913 rc = -ENOMEM;
7914 goto err_out;
7915 }
7916
b6016b76
MC		 7917 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7918 rc = pci_enable_device(pdev);
7919 if (rc) {
3a9c6a49 7920 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
b6016b76
MC		 7921 goto err_out;
7922 }
7923
7924 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7925 dev_err(&pdev->dev,
3a9c6a49 7926 "Cannot find PCI device base address, aborting\n");
b6016b76
MC		 7927 rc = -ENODEV;
7928 goto err_out_disable;
7929 }
7930
7931 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7932 if (rc) {
3a9c6a49 7933 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
b6016b76
MC		 7934 goto err_out_disable;
7935 }
7936
7937 pci_set_master(pdev);
7938
7939 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7940 if (bp->pm_cap == 0) {
9b91cf9d 7941 dev_err(&pdev->dev,
3a9c6a49 7942 "Cannot find power management capability, aborting\n");
b6016b76
MC		 7943 rc = -EIO;
7944 goto err_out_release;
7945 }
7946
b6016b76
MC		 7947 bp->dev = dev;
7948 bp->pdev = pdev;
7949
7950 spin_lock_init(&bp->phy_lock);
1b8227c4 7951 spin_lock_init(&bp->indirect_lock);
c5a88950
MC		 7952#ifdef BCM_CNIC
7953 mutex_init(&bp->cnic_lock);
7954#endif
c4028958 7955 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7956
7957 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
4edd473f 7958 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
b6016b76
MC		 7959 dev->mem_end = dev->mem_start + mem_len;
7960 dev->irq = pdev->irq;
7961
7962 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7963
7964 if (!bp->regview) {
3a9c6a49 7965 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
b6016b76
MC		 7966 rc = -ENOMEM;
7967 goto err_out_release;
7968 }
7969
be7ff1af
MC		 7970 bnx2_set_power_state(bp, PCI_D0);
7971
b6016b76
MC		 7972 /* Configure byte swap and enable write to the reg_window registers.
7973 * Rely on CPU to do target byte swapping on big endian systems
7974 * The chip's target access swapping will not swap all accesses
7975 */
be7ff1af
MC		 7976 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG,
7977 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7978 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
b6016b76
MC		 7979
7980 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7981
883e5151 7982 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
e82760e7
JM		 7983 if (!pci_is_pcie(pdev)) {
7984 dev_err(&pdev->dev, "Not PCIE, aborting\n");
883e5151
MC		 7985 rc = -EIO;
7986 goto err_out_unmap;
7987 }
f86e82fb 7988 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7989 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7990 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
c239f279
MC		 7991
7992 /* AER (Advanced Error Reporting) hooks */
7993 err = pci_enable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 7994 if (!err)
7995 bp->flags |= BNX2_FLAG_AER_ENABLED;
c239f279 7996
883e5151 7997 } else {
59b47d8a
MC		 7998 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7999 if (bp->pcix_cap == 0) {
8000 dev_err(&pdev->dev,
3a9c6a49 8001 "Cannot find PCIX capability, aborting\n");
59b47d8a
MC		 8002 rc = -EIO;
8003 goto err_out_unmap;
8004 }
61d9e3fa 8005 bp->flags |= BNX2_FLAG_BROKEN_STATS;
59b47d8a
MC		 8006 }
8007
b4b36042
MC		 8008 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
8009 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 8010 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 8011 }
8012
8e6a72c4
MC		 8013 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
8014 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 8015 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 8016 }
8017
40453c83
MC		 8018 /* 5708 cannot support DMA addresses > 40-bit. */
8019 if (CHIP_NUM(bp) == CHIP_NUM_5708)
50cf156a 8020 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
40453c83 8021 else
6a35528a 8022 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
40453c83
MC		 8023
8024 /* Configure DMA attributes. */
8025 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
8026 dev->features |= NETIF_F_HIGHDMA;
8027 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
8028 if (rc) {
8029 dev_err(&pdev->dev,
3a9c6a49 8030 "pci_set_consistent_dma_mask failed, aborting\n");
40453c83
MC		 8031 goto err_out_unmap;
8032 }
284901a9 8033 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3a9c6a49 8034 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
40453c83
MC		 8035 goto err_out_unmap;
8036 }
8037
f86e82fb 8038 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 8039 bnx2_get_pci_speed(bp);
b6016b76
MC		 8040
8041 /* 5706A0 may falsely detect SERR and PERR. */
8042 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8043 reg = REG_RD(bp, PCI_COMMAND);
8044 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
8045 REG_WR(bp, PCI_COMMAND, reg);
8046 }
8047 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 8048 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 8049
9b91cf9d 8050 dev_err(&pdev->dev,
3a9c6a49 8051 "5706 A1 can only be used in a PCIX bus, aborting\n");
b6016b76
MC		 8052 goto err_out_unmap;
8053 }
8054
8055 bnx2_init_nvram(bp);
8056
2726d6e1 8057 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 8058
8059 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 8060 BNX2_SHM_HDR_SIGNATURE_SIG) {
8061 u32 off = PCI_FUNC(pdev->devfn) << 2;
8062
2726d6e1 8063 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 8064 } else
e3648b3d
MC		 8065 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8066
b6016b76
MC		 8067 /* Get the permanent MAC address. First we need to make sure the
8068 * firmware is actually running.
8069 */
2726d6e1 8070 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 8071
8072 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8073 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
3a9c6a49 8074 dev_err(&pdev->dev, "Firmware not running, aborting\n");
b6016b76
MC		 8075 rc = -ENODEV;
8076 goto err_out_unmap;
8077 }
8078
76d99061
MC		 8079 bnx2_read_vpd_fw_ver(bp);
8080
8081 j = strlen(bp->fw_version);
2726d6e1 8082 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
76d99061 8083 for (i = 0; i < 3 && j < 24; i++) {
58fc2ea4
MC		 8084 u8 num, k, skip0;
8085
76d99061
MC		 8086 if (i == 0) {
8087 bp->fw_version[j++] = 'b';
8088 bp->fw_version[j++] = 'c';
8089 bp->fw_version[j++] = ' ';
8090 }
58fc2ea4
MC		 8091 num = (u8) (reg >> (24 - (i * 8)));
8092 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8093 if (num >= k || !skip0 || k == 1) {
8094 bp->fw_version[j++] = (num / k) + '0';
8095 skip0 = 0;
8096 }
8097 }
8098 if (i != 2)
8099 bp->fw_version[j++] = '.';
8100 }
2726d6e1 8101 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 8102 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8103 bp->wol = 1;
8104
8105 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 8106 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 8107
8108 for (i = 0; i < 30; i++) {
2726d6e1 8109 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 8110 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8111 break;
8112 msleep(10);
8113 }
8114 }
2726d6e1 8115 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 8116 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8117 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8118 reg != BNX2_CONDITION_MFW_RUN_NONE) {
2726d6e1 8119 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4 8120
76d99061
MC		 8121 if (j < 32)
8122 bp->fw_version[j++] = ' ';
8123 for (i = 0; i < 3 && j < 28; i++) {
2726d6e1 8124 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
3aeb7d22 8125 reg = be32_to_cpu(reg);
58fc2ea4
MC		 8126 memcpy(&bp->fw_version[j], &reg, 4);
8127 j += 4;
8128 }
8129 }
b6016b76 8130
2726d6e1 8131 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 8132 bp->mac_addr[0] = (u8) (reg >> 8);
8133 bp->mac_addr[1] = (u8) reg;
8134
2726d6e1 8135 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 8136 bp->mac_addr[2] = (u8) (reg >> 24);
8137 bp->mac_addr[3] = (u8) (reg >> 16);
8138 bp->mac_addr[4] = (u8) (reg >> 8);
8139 bp->mac_addr[5] = (u8) reg;
8140
8141 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 8142 bnx2_set_rx_ring_size(bp, 255);
b6016b76 8143
cf7474a6 8144 bp->tx_quick_cons_trip_int = 2;
b6016b76 8145 bp->tx_quick_cons_trip = 20;
cf7474a6 8146 bp->tx_ticks_int = 18;
b6016b76 8147 bp->tx_ticks = 80;
6aa20a22 8148
cf7474a6
MC		 8149 bp->rx_quick_cons_trip_int = 2;
8150 bp->rx_quick_cons_trip = 12;
b6016b76
MC		 8151 bp->rx_ticks_int = 18;
8152 bp->rx_ticks = 18;
8153
7ea6920e 8154 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76 8155
ac392abc 8156 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 8157
5b0c76ad
MC		 8158 bp->phy_addr = 1;
8159
b6016b76 8160 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 8161 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8162 bnx2_get_5709_media(bp);
8163 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 8164 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 8165
0d8a6571 8166 bp->phy_port = PORT_TP;
583c28e5 8167 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 8168 bp->phy_port = PORT_FIBRE;
2726d6e1 8169 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 8170 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 8171 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8172 bp->wol = 0;
8173 }
38ea3686
MC		 8174 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8175 /* Don't do parallel detect on this board because of
8176 * some board problems. The link will not go down
8177 * if we do parallel detect.
8178 */
8179 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8180 pdev->subsystem_device == 0x310c)
8181 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8182 } else {
5b0c76ad 8183 bp->phy_addr = 2;
5b0c76ad 8184 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 8185 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 8186 }
261dd5ca
MC		 8187 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8188 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 8189 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 8190 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8191 (CHIP_REV(bp) == CHIP_REV_Ax ||
8192 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 8193 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 8194
7c62e83b
MC		 8195 bnx2_init_fw_cap(bp);
8196
16088272
MC		 8197 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8198 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
5ec6d7bf
MC		 8199 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8200 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
f86e82fb 8201 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8202 bp->wol = 0;
8203 }
dda1e390 8204
b6016b76
MC		 8205 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8206 bp->tx_quick_cons_trip_int =
8207 bp->tx_quick_cons_trip;
8208 bp->tx_ticks_int = bp->tx_ticks;
8209 bp->rx_quick_cons_trip_int =
8210 bp->rx_quick_cons_trip;
8211 bp->rx_ticks_int = bp->rx_ticks;
8212 bp->comp_prod_trip_int = bp->comp_prod_trip;
8213 bp->com_ticks_int = bp->com_ticks;
8214 bp->cmd_ticks_int = bp->cmd_ticks;
8215 }
8216
f9317a40
MC		 8217 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8218 *
8219 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8220 * with byte enables disabled on the unused 32-bit word. This is legal
8221 * but causes problems on the AMD 8132 which will eventually stop
8222 * responding after a while.
8223 *
8224 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 8225 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 8226 */
8227 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8228 struct pci_dev *amd_8132 = NULL;
8229
8230 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8231 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8232 amd_8132))) {
f9317a40 8233
44c10138
AK		 8234 if (amd_8132->revision >= 0x10 &&
8235 amd_8132->revision <= 0x13) {
f9317a40
MC		 8236 disable_msi = 1;
8237 pci_dev_put(amd_8132);
8238 break;
8239 }
8240 }
8241 }
8242
deaf391b 8243 bnx2_set_default_link(bp);
b6016b76
MC		 8244 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8245
cd339a0e 8246 init_timer(&bp->timer);
ac392abc 8247 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
cd339a0e
MC		 8248 bp->timer.data = (unsigned long) bp;
8249 bp->timer.function = bnx2_timer;
8250
7625eb2f 8251#ifdef BCM_CNIC
41c2178a
MC		 8252 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
8253 bp->cnic_eth_dev.max_iscsi_conn =
8254 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
8255 BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT;
7625eb2f 8256#endif
c239f279
MC		 8257 pci_save_state(pdev);
8258
b6016b76
MC		 8259 return 0;
8260
8261err_out_unmap:
4bb9ebc7 8262 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
c239f279 8263 pci_disable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8264 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8265 }
c239f279 8266
b6016b76
MC		 8267 if (bp->regview) {
8268 iounmap(bp->regview);
73eef4cd 8269 bp->regview = NULL;
b6016b76
MC		 8270 }
8271
8272err_out_release:
8273 pci_release_regions(pdev);
8274
8275err_out_disable:
8276 pci_disable_device(pdev);
8277 pci_set_drvdata(pdev, NULL);
8278
8279err_out:
8280 return rc;
8281}
8282
883e5151
MC		 8283static char * __devinit
8284bnx2_bus_string(struct bnx2 *bp, char *str)
8285{
8286 char *s = str;
8287
f86e82fb 8288 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 8289 s += sprintf(s, "PCI Express");
8290 } else {
8291 s += sprintf(s, "PCI");
f86e82fb 8292 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 8293 s += sprintf(s, "-X");
f86e82fb 8294 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 8295 s += sprintf(s, " 32-bit");
8296 else
8297 s += sprintf(s, " 64-bit");
8298 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8299 }
8300 return str;
8301}
8302
f048fa9c
MC		 8303static void
8304bnx2_del_napi(struct bnx2 *bp)
8305{
8306 int i;
8307
8308 for (i = 0; i < bp->irq_nvecs; i++)
8309 netif_napi_del(&bp->bnx2_napi[i].napi);
8310}
8311
8312static void
35efa7c1
MC		 8313bnx2_init_napi(struct bnx2 *bp)
8314{
b4b36042 8315 int i;
35efa7c1 8316
4327ba43 8317 for (i = 0; i < bp->irq_nvecs; i++) {
35e9010b
MC		 8318 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8319 int (*poll)(struct napi_struct *, int);
8320
8321 if (i == 0)
8322 poll = bnx2_poll;
8323 else
f0ea2e63 8324 poll = bnx2_poll_msix;
35e9010b
MC		 8325
8326 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
b4b36042
MC		 8327 bnapi->bp = bp;
8328 }
35efa7c1
MC		 8329}
8330
0421eae6
SH		 8331static const struct net_device_ops bnx2_netdev_ops = {
8332 .ndo_open = bnx2_open,
8333 .ndo_start_xmit = bnx2_start_xmit,
8334 .ndo_stop = bnx2_close,
5d07bf26 8335 .ndo_get_stats64 = bnx2_get_stats64,
0421eae6
SH		 8336 .ndo_set_rx_mode = bnx2_set_rx_mode,
8337 .ndo_do_ioctl = bnx2_ioctl,
8338 .ndo_validate_addr = eth_validate_addr,
8339 .ndo_set_mac_address = bnx2_change_mac_addr,
8340 .ndo_change_mtu = bnx2_change_mtu,
8d7dfc2b
MM		 8341 .ndo_fix_features = bnx2_fix_features,
8342 .ndo_set_features = bnx2_set_features,
0421eae6 8343 .ndo_tx_timeout = bnx2_tx_timeout,
257ddbda 8344#ifdef CONFIG_NET_POLL_CONTROLLER
0421eae6
SH		 8345 .ndo_poll_controller = poll_bnx2,
8346#endif
8347};
8348
b6016b76
MC		 8349static int __devinit
8350bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8351{
8352 static int version_printed = 0;
8353 struct net_device *dev = NULL;
8354 struct bnx2 *bp;
0795af57 8355 int rc;
883e5151 8356 char str[40];
b6016b76
MC		 8357
8358 if (version_printed++ == 0)
3a9c6a49 8359 pr_info("%s", version);
b6016b76
MC		 8360
8361 /* dev zeroed in init_etherdev */
706bf240 8362 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
b6016b76
MC		 8363
8364 if (!dev)
8365 return -ENOMEM;
8366
8367 rc = bnx2_init_board(pdev, dev);
8368 if (rc < 0) {
8369 free_netdev(dev);
8370 return rc;
8371 }
8372
0421eae6 8373 dev->netdev_ops = &bnx2_netdev_ops;
b6016b76 8374 dev->watchdog_timeo = TX_TIMEOUT;
b6016b76 8375 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 8376
972ec0d4 8377 bp = netdev_priv(dev);
b6016b76 8378
1b2f922f
MC		 8379 pci_set_drvdata(pdev, dev);
8380
8381 memcpy(dev->dev_addr, bp->mac_addr, 6);
8382 memcpy(dev->perm_addr, bp->mac_addr, 6);
1b2f922f 8383
8d7dfc2b
MM		 8384 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
8385 NETIF_F_TSO | NETIF_F_TSO_ECN |
8386 NETIF_F_RXHASH | NETIF_F_RXCSUM;
8387
8388 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8389 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8390
8391 dev->vlan_features = dev->hw_features;
8392 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8393 dev->features |= dev->hw_features;
01789349 8394 dev->priv_flags |= IFF_UNICAST_FLT;
8d7dfc2b 8395
b6016b76 8396 if ((rc = register_netdev(dev))) {
9b91cf9d 8397 dev_err(&pdev->dev, "Cannot register net device\n");
57579f76 8398 goto error;
b6016b76
MC		 8399 }
8400
3a9c6a49
JP		 8401 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8402 board_info[ent->driver_data].name,
8403 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8404 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8405 bnx2_bus_string(bp, str),
8406 dev->base_addr,
8407 bp->pdev->irq, dev->dev_addr);
b6016b76 8408
b6016b76 8409 return 0;
57579f76
MC		 8410
8411error:
57579f76
MC		 8412 if (bp->regview)
8413 iounmap(bp->regview);
8414 pci_release_regions(pdev);
8415 pci_disable_device(pdev);
8416 pci_set_drvdata(pdev, NULL);
8417 free_netdev(dev);
8418 return rc;
b6016b76
MC		 8419}
8420
8421static void __devexit
8422bnx2_remove_one(struct pci_dev *pdev)
8423{
8424 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8425 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 8426
8427 unregister_netdev(dev);
8428
8333a46a 8429 del_timer_sync(&bp->timer);
cd634019 8430 cancel_work_sync(&bp->reset_task);
8333a46a 8431
b6016b76
MC		 8432 if (bp->regview)
8433 iounmap(bp->regview);
8434
354fcd77
MC		 8435 kfree(bp->temp_stats_blk);
8436
4bb9ebc7 8437 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
c239f279 8438 pci_disable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8439 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8440 }
cd709aa9 8441
7880b72e 8442 bnx2_release_firmware(bp);
8443
c239f279 8444 free_netdev(dev);
cd709aa9 8445
b6016b76
MC		 8446 pci_release_regions(pdev);
8447 pci_disable_device(pdev);
8448 pci_set_drvdata(pdev, NULL);
8449}
8450
8451static int
829ca9a3 8452bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 8453{
8454 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8455 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8456
6caebb02
MC		 8457 /* PCI register 4 needs to be saved whether netif_running() or not.
8458 * MSI address and data need to be saved if using MSI and
8459 * netif_running().
8460 */
8461 pci_save_state(pdev);
b6016b76
MC		 8462 if (!netif_running(dev))
8463 return 0;
8464
23f333a2 8465 cancel_work_sync(&bp->reset_task);
212f9934 8466 bnx2_netif_stop(bp, true);
b6016b76
MC		 8467 netif_device_detach(dev);
8468 del_timer_sync(&bp->timer);
74bf4ba3 8469 bnx2_shutdown_chip(bp);
b6016b76 8470 bnx2_free_skbs(bp);
829ca9a3 8471 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 8472 return 0;
8473}
8474
8475static int
8476bnx2_resume(struct pci_dev *pdev)
8477{
8478 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8479 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8480
6caebb02 8481 pci_restore_state(pdev);
b6016b76
MC		 8482 if (!netif_running(dev))
8483 return 0;
8484
829ca9a3 8485 bnx2_set_power_state(bp, PCI_D0);
b6016b76 8486 netif_device_attach(dev);
9a120bc5 8487 bnx2_init_nic(bp, 1);
212f9934 8488 bnx2_netif_start(bp, true);
b6016b76
MC		 8489 return 0;
8490}
8491
6ff2da49
WX		 8492/**
8493 * bnx2_io_error_detected - called when PCI error is detected
8494 * @pdev: Pointer to PCI device
8495 * @state: The current pci connection state
8496 *
8497 * This function is called after a PCI bus error affecting
8498 * this device has been detected.
8499 */
8500static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8501 pci_channel_state_t state)
8502{
8503 struct net_device *dev = pci_get_drvdata(pdev);
8504 struct bnx2 *bp = netdev_priv(dev);
8505
8506 rtnl_lock();
8507 netif_device_detach(dev);
8508
2ec3de26
DN		 8509 if (state == pci_channel_io_perm_failure) {
8510 rtnl_unlock();
8511 return PCI_ERS_RESULT_DISCONNECT;
8512 }
8513
6ff2da49 8514 if (netif_running(dev)) {
212f9934 8515 bnx2_netif_stop(bp, true);
6ff2da49
WX		 8516 del_timer_sync(&bp->timer);
8517 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8518 }
8519
8520 pci_disable_device(pdev);
8521 rtnl_unlock();
8522
8523 /* Request a slot slot reset. */
8524 return PCI_ERS_RESULT_NEED_RESET;
8525}
8526
8527/**
8528 * bnx2_io_slot_reset - called after the pci bus has been reset.
8529 * @pdev: Pointer to PCI device
8530 *
8531 * Restart the card from scratch, as if from a cold-boot.
8532 */
8533static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8534{
8535 struct net_device *dev = pci_get_drvdata(pdev);
8536 struct bnx2 *bp = netdev_priv(dev);
cd709aa9
JF		 8537 pci_ers_result_t result;
8538 int err;
6ff2da49
WX		 8539
8540 rtnl_lock();
8541 if (pci_enable_device(pdev)) {
8542 dev_err(&pdev->dev,
3a9c6a49 8543 "Cannot re-enable PCI device after reset\n");
cd709aa9
JF		 8544 result = PCI_ERS_RESULT_DISCONNECT;
8545 } else {
8546 pci_set_master(pdev);
8547 pci_restore_state(pdev);
8548 pci_save_state(pdev);
8549
8550 if (netif_running(dev)) {
8551 bnx2_set_power_state(bp, PCI_D0);
8552 bnx2_init_nic(bp, 1);
8553 }
8554 result = PCI_ERS_RESULT_RECOVERED;
6ff2da49 8555 }
cd709aa9 8556 rtnl_unlock();
6ff2da49 8557
4bb9ebc7 8558 if (!(bp->flags & BNX2_FLAG_AER_ENABLED))
c239f279
MC		 8559 return result;
8560
cd709aa9
JF		 8561 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8562 if (err) {
8563 dev_err(&pdev->dev,
8564 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8565 err); /* non-fatal, continue */
6ff2da49
WX		 8566 }
8567
cd709aa9 8568 return result;
6ff2da49
WX		 8569}
8570
8571/**
8572 * bnx2_io_resume - called when traffic can start flowing again.
8573 * @pdev: Pointer to PCI device
8574 *
8575 * This callback is called when the error recovery driver tells us that
8576 * its OK to resume normal operation.
8577 */
8578static void bnx2_io_resume(struct pci_dev *pdev)
8579{
8580 struct net_device *dev = pci_get_drvdata(pdev);
8581 struct bnx2 *bp = netdev_priv(dev);
8582
8583 rtnl_lock();
8584 if (netif_running(dev))
212f9934 8585 bnx2_netif_start(bp, true);
6ff2da49
WX		 8586
8587 netif_device_attach(dev);
8588 rtnl_unlock();
8589}
8590
8591static struct pci_error_handlers bnx2_err_handler = {
8592 .error_detected = bnx2_io_error_detected,
8593 .slot_reset = bnx2_io_slot_reset,
8594 .resume = bnx2_io_resume,
8595};
8596
b6016b76 8597static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 8598 .name = DRV_MODULE_NAME,
8599 .id_table = bnx2_pci_tbl,
8600 .probe = bnx2_init_one,
8601 .remove = __devexit_p(bnx2_remove_one),
8602 .suspend = bnx2_suspend,
8603 .resume = bnx2_resume,
6ff2da49 8604 .err_handler = &bnx2_err_handler,
b6016b76
MC		 8605};
8606
8607static int __init bnx2_init(void)
8608{
29917620 8609 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 8610}
8611
8612static void __exit bnx2_cleanup(void)
8613{
8614 pci_unregister_driver(&bnx2_pci_driver);
8615}
8616
8617module_init(bnx2_init);
8618module_exit(bnx2_cleanup);
8619
8620
8621
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