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4ad79e13 | 1 | /* bnx2x_cmn.c: QLogic Everest network driver. |
9f6c9258 | 2 | * |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
4ad79e13 YM |
4 | * Copyright (c) 2014 QLogic Corporation |
5 | * All rights reserved | |
9f6c9258 DK |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
08f6dd89 | 11 | * Maintained by: Ariel Elior <ariel.elior@qlogic.com> |
9f6c9258 DK |
12 | * Written by: Eliezer Tamir |
13 | * Based on code from Michael Chan's bnx2 driver | |
14 | * UDP CSUM errata workaround by Arik Gendelman | |
15 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
16 | * Statistics and Link management by Yitchak Gertner | |
17 | * | |
18 | */ | |
19 | ||
f1deab50 JP |
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
21 | ||
9f6c9258 | 22 | #include <linux/etherdevice.h> |
9bcc0893 | 23 | #include <linux/if_vlan.h> |
a6b7a407 | 24 | #include <linux/interrupt.h> |
9f6c9258 | 25 | #include <linux/ip.h> |
c9931896 | 26 | #include <linux/crash_dump.h> |
9969085e | 27 | #include <net/tcp.h> |
f2e0899f | 28 | #include <net/ipv6.h> |
7f3e01fe | 29 | #include <net/ip6_checksum.h> |
076bb0c8 | 30 | #include <net/busy_poll.h> |
c0cba59e | 31 | #include <linux/prefetch.h> |
9f6c9258 | 32 | #include "bnx2x_cmn.h" |
523224a3 | 33 | #include "bnx2x_init.h" |
042181f5 | 34 | #include "bnx2x_sp.h" |
9f6c9258 | 35 | |
a8f47eb7 | 36 | static void bnx2x_free_fp_mem_cnic(struct bnx2x *bp); |
37 | static int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp); | |
38 | static int bnx2x_alloc_fp_mem(struct bnx2x *bp); | |
39 | static int bnx2x_poll(struct napi_struct *napi, int budget); | |
40 | ||
41 | static void bnx2x_add_all_napi_cnic(struct bnx2x *bp) | |
42 | { | |
43 | int i; | |
44 | ||
45 | /* Add NAPI objects */ | |
46 | for_each_rx_queue_cnic(bp, i) { | |
47 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), | |
48 | bnx2x_poll, NAPI_POLL_WEIGHT); | |
a8f47eb7 | 49 | } |
50 | } | |
51 | ||
52 | static void bnx2x_add_all_napi(struct bnx2x *bp) | |
53 | { | |
54 | int i; | |
55 | ||
56 | /* Add NAPI objects */ | |
57 | for_each_eth_queue(bp, i) { | |
58 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), | |
59 | bnx2x_poll, NAPI_POLL_WEIGHT); | |
a8f47eb7 | 60 | } |
61 | } | |
62 | ||
63 | static int bnx2x_calc_num_queues(struct bnx2x *bp) | |
64 | { | |
7d0445d6 | 65 | int nq = bnx2x_num_queues ? : netif_get_num_default_rss_queues(); |
ff2ad307 MS |
66 | |
67 | /* Reduce memory usage in kdump environment by using only one queue */ | |
c9931896 | 68 | if (is_kdump_kernel()) |
ff2ad307 MS |
69 | nq = 1; |
70 | ||
7d0445d6 MS |
71 | nq = clamp(nq, 1, BNX2X_MAX_QUEUES(bp)); |
72 | return nq; | |
a8f47eb7 | 73 | } |
74 | ||
b3b83c3f DK |
75 | /** |
76 | * bnx2x_move_fp - move content of the fastpath structure. | |
77 | * | |
78 | * @bp: driver handle | |
79 | * @from: source FP index | |
80 | * @to: destination FP index | |
81 | * | |
82 | * Makes sure the contents of the bp->fp[to].napi is kept | |
72754080 AE |
83 | * intact. This is done by first copying the napi struct from |
84 | * the target to the source, and then mem copying the entire | |
65565884 MS |
85 | * source onto the target. Update txdata pointers and related |
86 | * content. | |
b3b83c3f DK |
87 | */ |
88 | static inline void bnx2x_move_fp(struct bnx2x *bp, int from, int to) | |
89 | { | |
90 | struct bnx2x_fastpath *from_fp = &bp->fp[from]; | |
91 | struct bnx2x_fastpath *to_fp = &bp->fp[to]; | |
15192a8c BW |
92 | struct bnx2x_sp_objs *from_sp_objs = &bp->sp_objs[from]; |
93 | struct bnx2x_sp_objs *to_sp_objs = &bp->sp_objs[to]; | |
94 | struct bnx2x_fp_stats *from_fp_stats = &bp->fp_stats[from]; | |
95 | struct bnx2x_fp_stats *to_fp_stats = &bp->fp_stats[to]; | |
65565884 MS |
96 | int old_max_eth_txqs, new_max_eth_txqs; |
97 | int old_txdata_index = 0, new_txdata_index = 0; | |
34d5626a | 98 | struct bnx2x_agg_info *old_tpa_info = to_fp->tpa_info; |
72754080 AE |
99 | |
100 | /* Copy the NAPI object as it has been already initialized */ | |
101 | from_fp->napi = to_fp->napi; | |
102 | ||
b3b83c3f DK |
103 | /* Move bnx2x_fastpath contents */ |
104 | memcpy(to_fp, from_fp, sizeof(*to_fp)); | |
105 | to_fp->index = to; | |
65565884 | 106 | |
34d5626a YM |
107 | /* Retain the tpa_info of the original `to' version as we don't want |
108 | * 2 FPs to contain the same tpa_info pointer. | |
109 | */ | |
110 | to_fp->tpa_info = old_tpa_info; | |
111 | ||
15192a8c BW |
112 | /* move sp_objs contents as well, as their indices match fp ones */ |
113 | memcpy(to_sp_objs, from_sp_objs, sizeof(*to_sp_objs)); | |
114 | ||
115 | /* move fp_stats contents as well, as their indices match fp ones */ | |
116 | memcpy(to_fp_stats, from_fp_stats, sizeof(*to_fp_stats)); | |
117 | ||
65565884 MS |
118 | /* Update txdata pointers in fp and move txdata content accordingly: |
119 | * Each fp consumes 'max_cos' txdata structures, so the index should be | |
120 | * decremented by max_cos x delta. | |
121 | */ | |
122 | ||
123 | old_max_eth_txqs = BNX2X_NUM_ETH_QUEUES(bp) * (bp)->max_cos; | |
124 | new_max_eth_txqs = (BNX2X_NUM_ETH_QUEUES(bp) - from + to) * | |
125 | (bp)->max_cos; | |
126 | if (from == FCOE_IDX(bp)) { | |
127 | old_txdata_index = old_max_eth_txqs + FCOE_TXQ_IDX_OFFSET; | |
128 | new_txdata_index = new_max_eth_txqs + FCOE_TXQ_IDX_OFFSET; | |
129 | } | |
130 | ||
4864a16a YM |
131 | memcpy(&bp->bnx2x_txq[new_txdata_index], |
132 | &bp->bnx2x_txq[old_txdata_index], | |
65565884 MS |
133 | sizeof(struct bnx2x_fp_txdata)); |
134 | to_fp->txdata_ptr[0] = &bp->bnx2x_txq[new_txdata_index]; | |
b3b83c3f DK |
135 | } |
136 | ||
8ca5e17e AE |
137 | /** |
138 | * bnx2x_fill_fw_str - Fill buffer with FW version string. | |
139 | * | |
140 | * @bp: driver handle | |
141 | * @buf: character buffer to fill with the fw name | |
142 | * @buf_len: length of the above buffer | |
143 | * | |
144 | */ | |
145 | void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len) | |
146 | { | |
147 | if (IS_PF(bp)) { | |
148 | u8 phy_fw_ver[PHY_FW_VER_LEN]; | |
149 | ||
150 | phy_fw_ver[0] = '\0'; | |
151 | bnx2x_get_ext_phy_fw_version(&bp->link_params, | |
152 | phy_fw_ver, PHY_FW_VER_LEN); | |
153 | strlcpy(buf, bp->fw_ver, buf_len); | |
154 | snprintf(buf + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver), | |
155 | "bc %d.%d.%d%s%s", | |
156 | (bp->common.bc_ver & 0xff0000) >> 16, | |
157 | (bp->common.bc_ver & 0xff00) >> 8, | |
158 | (bp->common.bc_ver & 0xff), | |
159 | ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver); | |
160 | } else { | |
6411280a | 161 | bnx2x_vf_fill_fw_str(bp, buf, buf_len); |
8ca5e17e AE |
162 | } |
163 | } | |
164 | ||
4864a16a YM |
165 | /** |
166 | * bnx2x_shrink_eth_fp - guarantees fastpath structures stay intact | |
167 | * | |
168 | * @bp: driver handle | |
169 | * @delta: number of eth queues which were not allocated | |
170 | */ | |
171 | static void bnx2x_shrink_eth_fp(struct bnx2x *bp, int delta) | |
172 | { | |
173 | int i, cos, old_eth_num = BNX2X_NUM_ETH_QUEUES(bp); | |
174 | ||
175 | /* Queue pointer cannot be re-set on an fp-basis, as moving pointer | |
16a5fd92 | 176 | * backward along the array could cause memory to be overridden |
4864a16a YM |
177 | */ |
178 | for (cos = 1; cos < bp->max_cos; cos++) { | |
179 | for (i = 0; i < old_eth_num - delta; i++) { | |
180 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
181 | int new_idx = cos * (old_eth_num - delta) + i; | |
182 | ||
183 | memcpy(&bp->bnx2x_txq[new_idx], fp->txdata_ptr[cos], | |
184 | sizeof(struct bnx2x_fp_txdata)); | |
185 | fp->txdata_ptr[cos] = &bp->bnx2x_txq[new_idx]; | |
186 | } | |
187 | } | |
188 | } | |
189 | ||
a8f47eb7 | 190 | int bnx2x_load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */ |
619c5cb6 | 191 | |
9f6c9258 DK |
192 | /* free skb in the packet ring at pos idx |
193 | * return idx of last bd freed | |
194 | */ | |
6383c0b3 | 195 | static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata, |
2df1a70a TH |
196 | u16 idx, unsigned int *pkts_compl, |
197 | unsigned int *bytes_compl) | |
9f6c9258 | 198 | { |
6383c0b3 | 199 | struct sw_tx_bd *tx_buf = &txdata->tx_buf_ring[idx]; |
9f6c9258 DK |
200 | struct eth_tx_start_bd *tx_start_bd; |
201 | struct eth_tx_bd *tx_data_bd; | |
202 | struct sk_buff *skb = tx_buf->skb; | |
203 | u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons; | |
204 | int nbd; | |
95e92fd4 | 205 | u16 split_bd_len = 0; |
9f6c9258 DK |
206 | |
207 | /* prefetch skb end pointer to speedup dev_kfree_skb() */ | |
208 | prefetch(&skb->end); | |
209 | ||
51c1a580 | 210 | DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d buff @(%p)->skb %p\n", |
6383c0b3 | 211 | txdata->txq_index, idx, tx_buf, skb); |
9f6c9258 | 212 | |
6383c0b3 | 213 | tx_start_bd = &txdata->tx_desc_ring[bd_idx].start_bd; |
9f6c9258 DK |
214 | |
215 | nbd = le16_to_cpu(tx_start_bd->nbd) - 1; | |
216 | #ifdef BNX2X_STOP_ON_ERROR | |
217 | if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) { | |
218 | BNX2X_ERR("BAD nbd!\n"); | |
219 | bnx2x_panic(); | |
220 | } | |
221 | #endif | |
222 | new_cons = nbd + tx_buf->first_bd; | |
223 | ||
224 | /* Get the next bd */ | |
225 | bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); | |
226 | ||
227 | /* Skip a parse bd... */ | |
228 | --nbd; | |
229 | bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); | |
230 | ||
fe26566d DK |
231 | if (tx_buf->flags & BNX2X_HAS_SECOND_PBD) { |
232 | /* Skip second parse bd... */ | |
233 | --nbd; | |
234 | bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); | |
235 | } | |
236 | ||
95e92fd4 | 237 | /* TSO headers+data bds share a common mapping. See bnx2x_tx_split() */ |
9f6c9258 | 238 | if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) { |
95e92fd4 MS |
239 | tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd; |
240 | split_bd_len = BD_UNMAP_LEN(tx_data_bd); | |
9f6c9258 DK |
241 | --nbd; |
242 | bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); | |
243 | } | |
244 | ||
95e92fd4 MS |
245 | /* unmap first bd */ |
246 | dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd), | |
247 | BD_UNMAP_LEN(tx_start_bd) + split_bd_len, | |
248 | DMA_TO_DEVICE); | |
249 | ||
9f6c9258 DK |
250 | /* now free frags */ |
251 | while (nbd > 0) { | |
252 | ||
6383c0b3 | 253 | tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd; |
9f6c9258 DK |
254 | dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd), |
255 | BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE); | |
256 | if (--nbd) | |
257 | bd_idx = TX_BD(NEXT_TX_IDX(bd_idx)); | |
258 | } | |
259 | ||
260 | /* release skb */ | |
261 | WARN_ON(!skb); | |
d8290ae5 | 262 | if (likely(skb)) { |
2df1a70a TH |
263 | (*pkts_compl)++; |
264 | (*bytes_compl) += skb->len; | |
e1615903 | 265 | dev_kfree_skb_any(skb); |
2df1a70a | 266 | } |
d8290ae5 | 267 | |
9f6c9258 DK |
268 | tx_buf->first_bd = 0; |
269 | tx_buf->skb = NULL; | |
270 | ||
271 | return new_cons; | |
272 | } | |
273 | ||
6383c0b3 | 274 | int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata) |
9f6c9258 | 275 | { |
9f6c9258 | 276 | struct netdev_queue *txq; |
6383c0b3 | 277 | u16 hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons; |
2df1a70a | 278 | unsigned int pkts_compl = 0, bytes_compl = 0; |
9f6c9258 DK |
279 | |
280 | #ifdef BNX2X_STOP_ON_ERROR | |
281 | if (unlikely(bp->panic)) | |
282 | return -1; | |
283 | #endif | |
284 | ||
6383c0b3 AE |
285 | txq = netdev_get_tx_queue(bp->dev, txdata->txq_index); |
286 | hw_cons = le16_to_cpu(*txdata->tx_cons_sb); | |
287 | sw_cons = txdata->tx_pkt_cons; | |
9f6c9258 | 288 | |
9c41c73c BK |
289 | /* Ensure subsequent loads occur after hw_cons */ |
290 | smp_rmb(); | |
291 | ||
9f6c9258 DK |
292 | while (sw_cons != hw_cons) { |
293 | u16 pkt_cons; | |
294 | ||
295 | pkt_cons = TX_BD(sw_cons); | |
296 | ||
51c1a580 MS |
297 | DP(NETIF_MSG_TX_DONE, |
298 | "queue[%d]: hw_cons %u sw_cons %u pkt_cons %u\n", | |
6383c0b3 | 299 | txdata->txq_index, hw_cons, sw_cons, pkt_cons); |
9f6c9258 | 300 | |
2df1a70a | 301 | bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons, |
2de67439 | 302 | &pkts_compl, &bytes_compl); |
2df1a70a | 303 | |
9f6c9258 DK |
304 | sw_cons++; |
305 | } | |
306 | ||
2df1a70a TH |
307 | netdev_tx_completed_queue(txq, pkts_compl, bytes_compl); |
308 | ||
6383c0b3 AE |
309 | txdata->tx_pkt_cons = sw_cons; |
310 | txdata->tx_bd_cons = bd_cons; | |
9f6c9258 DK |
311 | |
312 | /* Need to make the tx_bd_cons update visible to start_xmit() | |
313 | * before checking for netif_tx_queue_stopped(). Without the | |
314 | * memory barrier, there is a small possibility that | |
315 | * start_xmit() will miss it and cause the queue to be stopped | |
316 | * forever. | |
619c5cb6 VZ |
317 | * On the other hand we need an rmb() here to ensure the proper |
318 | * ordering of bit testing in the following | |
319 | * netif_tx_queue_stopped(txq) call. | |
9f6c9258 DK |
320 | */ |
321 | smp_mb(); | |
322 | ||
9f6c9258 | 323 | if (unlikely(netif_tx_queue_stopped(txq))) { |
16a5fd92 | 324 | /* Taking tx_lock() is needed to prevent re-enabling the queue |
9f6c9258 DK |
325 | * while it's empty. This could have happen if rx_action() gets |
326 | * suspended in bnx2x_tx_int() after the condition before | |
327 | * netif_tx_wake_queue(), while tx_action (bnx2x_start_xmit()): | |
328 | * | |
329 | * stops the queue->sees fresh tx_bd_cons->releases the queue-> | |
330 | * sends some packets consuming the whole queue again-> | |
331 | * stops the queue | |
332 | */ | |
333 | ||
334 | __netif_tx_lock(txq, smp_processor_id()); | |
335 | ||
336 | if ((netif_tx_queue_stopped(txq)) && | |
337 | (bp->state == BNX2X_STATE_OPEN) && | |
7df2dc6b | 338 | (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT)) |
9f6c9258 DK |
339 | netif_tx_wake_queue(txq); |
340 | ||
341 | __netif_tx_unlock(txq); | |
342 | } | |
343 | return 0; | |
344 | } | |
345 | ||
346 | static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp, | |
347 | u16 idx) | |
348 | { | |
349 | u16 last_max = fp->last_max_sge; | |
350 | ||
351 | if (SUB_S16(idx, last_max) > 0) | |
352 | fp->last_max_sge = idx; | |
353 | } | |
354 | ||
621b4d66 DK |
355 | static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp, |
356 | u16 sge_len, | |
357 | struct eth_end_agg_rx_cqe *cqe) | |
9f6c9258 DK |
358 | { |
359 | struct bnx2x *bp = fp->bp; | |
9f6c9258 DK |
360 | u16 last_max, last_elem, first_elem; |
361 | u16 delta = 0; | |
362 | u16 i; | |
363 | ||
364 | if (!sge_len) | |
365 | return; | |
366 | ||
367 | /* First mark all used pages */ | |
368 | for (i = 0; i < sge_len; i++) | |
619c5cb6 | 369 | BIT_VEC64_CLEAR_BIT(fp->sge_mask, |
621b4d66 | 370 | RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[i]))); |
9f6c9258 DK |
371 | |
372 | DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n", | |
621b4d66 | 373 | sge_len - 1, le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1])); |
9f6c9258 DK |
374 | |
375 | /* Here we assume that the last SGE index is the biggest */ | |
376 | prefetch((void *)(fp->sge_mask)); | |
523224a3 | 377 | bnx2x_update_last_max_sge(fp, |
621b4d66 | 378 | le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1])); |
9f6c9258 DK |
379 | |
380 | last_max = RX_SGE(fp->last_max_sge); | |
619c5cb6 VZ |
381 | last_elem = last_max >> BIT_VEC64_ELEM_SHIFT; |
382 | first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT; | |
9f6c9258 DK |
383 | |
384 | /* If ring is not full */ | |
385 | if (last_elem + 1 != first_elem) | |
386 | last_elem++; | |
387 | ||
388 | /* Now update the prod */ | |
389 | for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) { | |
390 | if (likely(fp->sge_mask[i])) | |
391 | break; | |
392 | ||
619c5cb6 VZ |
393 | fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK; |
394 | delta += BIT_VEC64_ELEM_SZ; | |
9f6c9258 DK |
395 | } |
396 | ||
397 | if (delta > 0) { | |
398 | fp->rx_sge_prod += delta; | |
399 | /* clear page-end entries */ | |
400 | bnx2x_clear_sge_mask_next_elems(fp); | |
401 | } | |
402 | ||
403 | DP(NETIF_MSG_RX_STATUS, | |
404 | "fp->last_max_sge = %d fp->rx_sge_prod = %d\n", | |
405 | fp->last_max_sge, fp->rx_sge_prod); | |
406 | } | |
407 | ||
2de67439 | 408 | /* Get Toeplitz hash value in the skb using the value from the |
e52fcb24 ED |
409 | * CQE (calculated by HW). |
410 | */ | |
411 | static u32 bnx2x_get_rxhash(const struct bnx2x *bp, | |
a334b5fb | 412 | const struct eth_fast_path_rx_cqe *cqe, |
5495ab75 | 413 | enum pkt_hash_types *rxhash_type) |
e52fcb24 | 414 | { |
2de67439 | 415 | /* Get Toeplitz hash from CQE */ |
e52fcb24 | 416 | if ((bp->dev->features & NETIF_F_RXHASH) && |
a334b5fb ED |
417 | (cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG)) { |
418 | enum eth_rss_hash_type htype; | |
419 | ||
420 | htype = cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE; | |
5495ab75 TH |
421 | *rxhash_type = ((htype == TCP_IPV4_HASH_TYPE) || |
422 | (htype == TCP_IPV6_HASH_TYPE)) ? | |
423 | PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3; | |
424 | ||
e52fcb24 | 425 | return le32_to_cpu(cqe->rss_hash_result); |
a334b5fb | 426 | } |
5495ab75 | 427 | *rxhash_type = PKT_HASH_TYPE_NONE; |
e52fcb24 ED |
428 | return 0; |
429 | } | |
430 | ||
9f6c9258 | 431 | static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue, |
e52fcb24 | 432 | u16 cons, u16 prod, |
619c5cb6 | 433 | struct eth_fast_path_rx_cqe *cqe) |
9f6c9258 DK |
434 | { |
435 | struct bnx2x *bp = fp->bp; | |
436 | struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; | |
437 | struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; | |
438 | struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; | |
439 | dma_addr_t mapping; | |
619c5cb6 VZ |
440 | struct bnx2x_agg_info *tpa_info = &fp->tpa_info[queue]; |
441 | struct sw_rx_bd *first_buf = &tpa_info->first_buf; | |
9f6c9258 | 442 | |
619c5cb6 VZ |
443 | /* print error if current state != stop */ |
444 | if (tpa_info->tpa_state != BNX2X_TPA_STOP) | |
9f6c9258 DK |
445 | BNX2X_ERR("start of bin not in stop [%d]\n", queue); |
446 | ||
e52fcb24 | 447 | /* Try to map an empty data buffer from the aggregation info */ |
619c5cb6 | 448 | mapping = dma_map_single(&bp->pdev->dev, |
e52fcb24 | 449 | first_buf->data + NET_SKB_PAD, |
619c5cb6 VZ |
450 | fp->rx_buf_size, DMA_FROM_DEVICE); |
451 | /* | |
452 | * ...if it fails - move the skb from the consumer to the producer | |
453 | * and set the current aggregation state as ERROR to drop it | |
454 | * when TPA_STOP arrives. | |
455 | */ | |
456 | ||
457 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
458 | /* Move the BD from the consumer to the producer */ | |
e52fcb24 | 459 | bnx2x_reuse_rx_data(fp, cons, prod); |
619c5cb6 VZ |
460 | tpa_info->tpa_state = BNX2X_TPA_ERROR; |
461 | return; | |
462 | } | |
9f6c9258 | 463 | |
e52fcb24 ED |
464 | /* move empty data from pool to prod */ |
465 | prod_rx_buf->data = first_buf->data; | |
619c5cb6 | 466 | dma_unmap_addr_set(prod_rx_buf, mapping, mapping); |
e52fcb24 | 467 | /* point prod_bd to new data */ |
9f6c9258 DK |
468 | prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); |
469 | prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
470 | ||
619c5cb6 VZ |
471 | /* move partial skb from cons to pool (don't unmap yet) */ |
472 | *first_buf = *cons_rx_buf; | |
473 | ||
474 | /* mark bin state as START */ | |
475 | tpa_info->parsing_flags = | |
476 | le16_to_cpu(cqe->pars_flags.flags); | |
477 | tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag); | |
478 | tpa_info->tpa_state = BNX2X_TPA_START; | |
479 | tpa_info->len_on_bd = le16_to_cpu(cqe->len_on_bd); | |
480 | tpa_info->placement_offset = cqe->placement_offset; | |
5495ab75 | 481 | tpa_info->rxhash = bnx2x_get_rxhash(bp, cqe, &tpa_info->rxhash_type); |
621b4d66 DK |
482 | if (fp->mode == TPA_MODE_GRO) { |
483 | u16 gro_size = le16_to_cpu(cqe->pkt_len_or_gro_seg_len); | |
924d75ab | 484 | tpa_info->full_page = SGE_PAGES / gro_size * gro_size; |
621b4d66 DK |
485 | tpa_info->gro_size = gro_size; |
486 | } | |
619c5cb6 | 487 | |
9f6c9258 DK |
488 | #ifdef BNX2X_STOP_ON_ERROR |
489 | fp->tpa_queue_used |= (1 << queue); | |
9f6c9258 | 490 | DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n", |
9f6c9258 DK |
491 | fp->tpa_queue_used); |
492 | #endif | |
493 | } | |
494 | ||
e4e3c02a VZ |
495 | /* Timestamp option length allowed for TPA aggregation: |
496 | * | |
497 | * nop nop kind length echo val | |
498 | */ | |
499 | #define TPA_TSTAMP_OPT_LEN 12 | |
500 | /** | |
cbf1de72 | 501 | * bnx2x_set_gro_params - compute GRO values |
e4e3c02a | 502 | * |
cbf1de72 | 503 | * @skb: packet skb |
e8920674 DK |
504 | * @parsing_flags: parsing flags from the START CQE |
505 | * @len_on_bd: total length of the first packet for the | |
506 | * aggregation. | |
cbf1de72 | 507 | * @pkt_len: length of all segments |
e8920674 DK |
508 | * |
509 | * Approximate value of the MSS for this aggregation calculated using | |
510 | * the first packet of it. | |
2de67439 | 511 | * Compute number of aggregated segments, and gso_type. |
e4e3c02a | 512 | */ |
cbf1de72 | 513 | static void bnx2x_set_gro_params(struct sk_buff *skb, u16 parsing_flags, |
ab5777d7 YM |
514 | u16 len_on_bd, unsigned int pkt_len, |
515 | u16 num_of_coalesced_segs) | |
e4e3c02a | 516 | { |
cbf1de72 | 517 | /* TPA aggregation won't have either IP options or TCP options |
619c5cb6 | 518 | * other than timestamp or IPv6 extension headers. |
e4e3c02a | 519 | */ |
619c5cb6 VZ |
520 | u16 hdrs_len = ETH_HLEN + sizeof(struct tcphdr); |
521 | ||
522 | if (GET_FLAG(parsing_flags, PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == | |
cbf1de72 | 523 | PRS_FLAG_OVERETH_IPV6) { |
619c5cb6 | 524 | hdrs_len += sizeof(struct ipv6hdr); |
cbf1de72 YM |
525 | skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; |
526 | } else { | |
619c5cb6 | 527 | hdrs_len += sizeof(struct iphdr); |
cbf1de72 YM |
528 | skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; |
529 | } | |
e4e3c02a VZ |
530 | |
531 | /* Check if there was a TCP timestamp, if there is it's will | |
532 | * always be 12 bytes length: nop nop kind length echo val. | |
533 | * | |
534 | * Otherwise FW would close the aggregation. | |
535 | */ | |
536 | if (parsing_flags & PARSING_FLAGS_TIME_STAMP_EXIST_FLAG) | |
537 | hdrs_len += TPA_TSTAMP_OPT_LEN; | |
538 | ||
cbf1de72 YM |
539 | skb_shinfo(skb)->gso_size = len_on_bd - hdrs_len; |
540 | ||
541 | /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count | |
542 | * to skb_shinfo(skb)->gso_segs | |
543 | */ | |
ab5777d7 | 544 | NAPI_GRO_CB(skb)->count = num_of_coalesced_segs; |
e4e3c02a VZ |
545 | } |
546 | ||
996dedba MS |
547 | static int bnx2x_alloc_rx_sge(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
548 | u16 index, gfp_t gfp_mask) | |
1191cb83 | 549 | { |
1191cb83 ED |
550 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; |
551 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
4cace675 | 552 | struct bnx2x_alloc_pool *pool = &fp->page_pool; |
1191cb83 ED |
553 | dma_addr_t mapping; |
554 | ||
b9032741 | 555 | if (!pool->page) { |
4cace675 | 556 | pool->page = alloc_pages(gfp_mask, PAGES_PER_SGE_SHIFT); |
5c9ffde4 | 557 | if (unlikely(!pool->page)) |
4cace675 | 558 | return -ENOMEM; |
4cace675 | 559 | |
4cace675 | 560 | pool->offset = 0; |
1191cb83 ED |
561 | } |
562 | ||
8031612d MS |
563 | mapping = dma_map_page(&bp->pdev->dev, pool->page, |
564 | pool->offset, SGE_PAGE_SIZE, DMA_FROM_DEVICE); | |
565 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
566 | BNX2X_ERR("Can't map sge\n"); | |
567 | return -ENOMEM; | |
568 | } | |
569 | ||
4cace675 GKB |
570 | sw_buf->page = pool->page; |
571 | sw_buf->offset = pool->offset; | |
572 | ||
1191cb83 ED |
573 | dma_unmap_addr_set(sw_buf, mapping, mapping); |
574 | ||
575 | sge->addr_hi = cpu_to_le32(U64_HI(mapping)); | |
576 | sge->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
577 | ||
4cace675 | 578 | pool->offset += SGE_PAGE_SIZE; |
b9032741 ED |
579 | if (PAGE_SIZE - pool->offset >= SGE_PAGE_SIZE) |
580 | get_page(pool->page); | |
581 | else | |
582 | pool->page = NULL; | |
1191cb83 ED |
583 | return 0; |
584 | } | |
585 | ||
9f6c9258 | 586 | static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
621b4d66 DK |
587 | struct bnx2x_agg_info *tpa_info, |
588 | u16 pages, | |
589 | struct sk_buff *skb, | |
619c5cb6 VZ |
590 | struct eth_end_agg_rx_cqe *cqe, |
591 | u16 cqe_idx) | |
9f6c9258 DK |
592 | { |
593 | struct sw_rx_page *rx_pg, old_rx_pg; | |
621b4d66 DK |
594 | u32 i, frag_len, frag_size; |
595 | int err, j, frag_id = 0; | |
619c5cb6 | 596 | u16 len_on_bd = tpa_info->len_on_bd; |
621b4d66 | 597 | u16 full_page = 0, gro_size = 0; |
9f6c9258 | 598 | |
619c5cb6 | 599 | frag_size = le16_to_cpu(cqe->pkt_len) - len_on_bd; |
621b4d66 DK |
600 | |
601 | if (fp->mode == TPA_MODE_GRO) { | |
602 | gro_size = tpa_info->gro_size; | |
603 | full_page = tpa_info->full_page; | |
604 | } | |
9f6c9258 DK |
605 | |
606 | /* This is needed in order to enable forwarding support */ | |
cbf1de72 YM |
607 | if (frag_size) |
608 | bnx2x_set_gro_params(skb, tpa_info->parsing_flags, len_on_bd, | |
ab5777d7 YM |
609 | le16_to_cpu(cqe->pkt_len), |
610 | le16_to_cpu(cqe->num_of_coalesced_segs)); | |
621b4d66 | 611 | |
9f6c9258 | 612 | #ifdef BNX2X_STOP_ON_ERROR |
924d75ab | 613 | if (pages > min_t(u32, 8, MAX_SKB_FRAGS) * SGE_PAGES) { |
9f6c9258 DK |
614 | BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n", |
615 | pages, cqe_idx); | |
619c5cb6 | 616 | BNX2X_ERR("cqe->pkt_len = %d\n", cqe->pkt_len); |
9f6c9258 DK |
617 | bnx2x_panic(); |
618 | return -EINVAL; | |
619 | } | |
620 | #endif | |
621 | ||
622 | /* Run through the SGL and compose the fragmented skb */ | |
623 | for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) { | |
619c5cb6 | 624 | u16 sge_idx = RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[j])); |
9f6c9258 DK |
625 | |
626 | /* FW gives the indices of the SGE as if the ring is an array | |
627 | (meaning that "next" element will consume 2 indices) */ | |
621b4d66 DK |
628 | if (fp->mode == TPA_MODE_GRO) |
629 | frag_len = min_t(u32, frag_size, (u32)full_page); | |
630 | else /* LRO */ | |
924d75ab | 631 | frag_len = min_t(u32, frag_size, (u32)SGE_PAGES); |
621b4d66 | 632 | |
9f6c9258 DK |
633 | rx_pg = &fp->rx_page_ring[sge_idx]; |
634 | old_rx_pg = *rx_pg; | |
635 | ||
636 | /* If we fail to allocate a substitute page, we simply stop | |
637 | where we are and drop the whole packet */ | |
996dedba | 638 | err = bnx2x_alloc_rx_sge(bp, fp, sge_idx, GFP_ATOMIC); |
9f6c9258 | 639 | if (unlikely(err)) { |
15192a8c | 640 | bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++; |
9f6c9258 DK |
641 | return err; |
642 | } | |
643 | ||
8031612d MS |
644 | dma_unmap_page(&bp->pdev->dev, |
645 | dma_unmap_addr(&old_rx_pg, mapping), | |
646 | SGE_PAGE_SIZE, DMA_FROM_DEVICE); | |
9f6c9258 | 647 | /* Add one frag and update the appropriate fields in the skb */ |
621b4d66 | 648 | if (fp->mode == TPA_MODE_LRO) |
4cace675 GKB |
649 | skb_fill_page_desc(skb, j, old_rx_pg.page, |
650 | old_rx_pg.offset, frag_len); | |
621b4d66 DK |
651 | else { /* GRO */ |
652 | int rem; | |
653 | int offset = 0; | |
654 | for (rem = frag_len; rem > 0; rem -= gro_size) { | |
655 | int len = rem > gro_size ? gro_size : rem; | |
656 | skb_fill_page_desc(skb, frag_id++, | |
4cace675 GKB |
657 | old_rx_pg.page, |
658 | old_rx_pg.offset + offset, | |
659 | len); | |
621b4d66 DK |
660 | if (offset) |
661 | get_page(old_rx_pg.page); | |
662 | offset += len; | |
663 | } | |
664 | } | |
9f6c9258 DK |
665 | |
666 | skb->data_len += frag_len; | |
924d75ab | 667 | skb->truesize += SGE_PAGES; |
9f6c9258 DK |
668 | skb->len += frag_len; |
669 | ||
670 | frag_size -= frag_len; | |
671 | } | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
d46d132c ED |
676 | static void bnx2x_frag_free(const struct bnx2x_fastpath *fp, void *data) |
677 | { | |
678 | if (fp->rx_frag_size) | |
e51423d9 | 679 | skb_free_frag(data); |
d46d132c ED |
680 | else |
681 | kfree(data); | |
682 | } | |
683 | ||
996dedba | 684 | static void *bnx2x_frag_alloc(const struct bnx2x_fastpath *fp, gfp_t gfp_mask) |
d46d132c | 685 | { |
996dedba MS |
686 | if (fp->rx_frag_size) { |
687 | /* GFP_KERNEL allocations are used only during initialization */ | |
d0164adc | 688 | if (unlikely(gfpflags_allow_blocking(gfp_mask))) |
996dedba MS |
689 | return (void *)__get_free_page(gfp_mask); |
690 | ||
d46d132c | 691 | return netdev_alloc_frag(fp->rx_frag_size); |
996dedba | 692 | } |
d46d132c | 693 | |
996dedba | 694 | return kmalloc(fp->rx_buf_size + NET_SKB_PAD, gfp_mask); |
d46d132c ED |
695 | } |
696 | ||
9969085e YM |
697 | #ifdef CONFIG_INET |
698 | static void bnx2x_gro_ip_csum(struct bnx2x *bp, struct sk_buff *skb) | |
699 | { | |
700 | const struct iphdr *iph = ip_hdr(skb); | |
701 | struct tcphdr *th; | |
702 | ||
703 | skb_set_transport_header(skb, sizeof(struct iphdr)); | |
704 | th = tcp_hdr(skb); | |
705 | ||
706 | th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb), | |
707 | iph->saddr, iph->daddr, 0); | |
708 | } | |
709 | ||
710 | static void bnx2x_gro_ipv6_csum(struct bnx2x *bp, struct sk_buff *skb) | |
711 | { | |
712 | struct ipv6hdr *iph = ipv6_hdr(skb); | |
713 | struct tcphdr *th; | |
714 | ||
715 | skb_set_transport_header(skb, sizeof(struct ipv6hdr)); | |
716 | th = tcp_hdr(skb); | |
717 | ||
718 | th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb), | |
719 | &iph->saddr, &iph->daddr, 0); | |
720 | } | |
2c2d06d5 YM |
721 | |
722 | static void bnx2x_gro_csum(struct bnx2x *bp, struct sk_buff *skb, | |
723 | void (*gro_func)(struct bnx2x*, struct sk_buff*)) | |
724 | { | |
0e24c0ad | 725 | skb_reset_network_header(skb); |
2c2d06d5 YM |
726 | gro_func(bp, skb); |
727 | tcp_gro_complete(skb); | |
728 | } | |
9969085e YM |
729 | #endif |
730 | ||
731 | static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
732 | struct sk_buff *skb) | |
733 | { | |
734 | #ifdef CONFIG_INET | |
cbf1de72 | 735 | if (skb_shinfo(skb)->gso_size) { |
9969085e YM |
736 | switch (be16_to_cpu(skb->protocol)) { |
737 | case ETH_P_IP: | |
2c2d06d5 | 738 | bnx2x_gro_csum(bp, skb, bnx2x_gro_ip_csum); |
9969085e YM |
739 | break; |
740 | case ETH_P_IPV6: | |
2c2d06d5 | 741 | bnx2x_gro_csum(bp, skb, bnx2x_gro_ipv6_csum); |
9969085e YM |
742 | break; |
743 | default: | |
9adab1b0 | 744 | WARN_ONCE(1, "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n", |
9969085e YM |
745 | be16_to_cpu(skb->protocol)); |
746 | } | |
9969085e YM |
747 | } |
748 | #endif | |
60e66fee | 749 | skb_record_rx_queue(skb, fp->rx_queue); |
9969085e YM |
750 | napi_gro_receive(&fp->napi, skb); |
751 | } | |
752 | ||
1191cb83 ED |
753 | static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
754 | struct bnx2x_agg_info *tpa_info, | |
755 | u16 pages, | |
756 | struct eth_end_agg_rx_cqe *cqe, | |
757 | u16 cqe_idx) | |
9f6c9258 | 758 | { |
619c5cb6 | 759 | struct sw_rx_bd *rx_buf = &tpa_info->first_buf; |
621b4d66 | 760 | u8 pad = tpa_info->placement_offset; |
619c5cb6 | 761 | u16 len = tpa_info->len_on_bd; |
e52fcb24 | 762 | struct sk_buff *skb = NULL; |
621b4d66 | 763 | u8 *new_data, *data = rx_buf->data; |
619c5cb6 VZ |
764 | u8 old_tpa_state = tpa_info->tpa_state; |
765 | ||
766 | tpa_info->tpa_state = BNX2X_TPA_STOP; | |
767 | ||
768 | /* If we there was an error during the handling of the TPA_START - | |
769 | * drop this aggregation. | |
770 | */ | |
771 | if (old_tpa_state == BNX2X_TPA_ERROR) | |
772 | goto drop; | |
773 | ||
e52fcb24 | 774 | /* Try to allocate the new data */ |
996dedba | 775 | new_data = bnx2x_frag_alloc(fp, GFP_ATOMIC); |
9f6c9258 DK |
776 | /* Unmap skb in the pool anyway, as we are going to change |
777 | pool entry status to BNX2X_TPA_STOP even if new skb allocation | |
778 | fails. */ | |
779 | dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(rx_buf, mapping), | |
a8c94b91 | 780 | fp->rx_buf_size, DMA_FROM_DEVICE); |
e52fcb24 | 781 | if (likely(new_data)) |
d46d132c | 782 | skb = build_skb(data, fp->rx_frag_size); |
9f6c9258 | 783 | |
e52fcb24 | 784 | if (likely(skb)) { |
9f6c9258 | 785 | #ifdef BNX2X_STOP_ON_ERROR |
a8c94b91 | 786 | if (pad + len > fp->rx_buf_size) { |
51c1a580 | 787 | BNX2X_ERR("skb_put is about to fail... pad %d len %d rx_buf_size %d\n", |
a8c94b91 | 788 | pad, len, fp->rx_buf_size); |
9f6c9258 DK |
789 | bnx2x_panic(); |
790 | return; | |
791 | } | |
792 | #endif | |
793 | ||
e52fcb24 | 794 | skb_reserve(skb, pad + NET_SKB_PAD); |
9f6c9258 | 795 | skb_put(skb, len); |
5495ab75 | 796 | skb_set_hash(skb, tpa_info->rxhash, tpa_info->rxhash_type); |
9f6c9258 DK |
797 | |
798 | skb->protocol = eth_type_trans(skb, bp->dev); | |
799 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
800 | ||
621b4d66 DK |
801 | if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages, |
802 | skb, cqe, cqe_idx)) { | |
619c5cb6 | 803 | if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN) |
86a9bad3 | 804 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tpa_info->vlan_tag); |
9969085e | 805 | bnx2x_gro_receive(bp, fp, skb); |
9f6c9258 | 806 | } else { |
51c1a580 MS |
807 | DP(NETIF_MSG_RX_STATUS, |
808 | "Failed to allocate new pages - dropping packet!\n"); | |
40955532 | 809 | dev_kfree_skb_any(skb); |
9f6c9258 DK |
810 | } |
811 | ||
e52fcb24 ED |
812 | /* put new data in bin */ |
813 | rx_buf->data = new_data; | |
9f6c9258 | 814 | |
619c5cb6 | 815 | return; |
9f6c9258 | 816 | } |
07b0f009 ED |
817 | if (new_data) |
818 | bnx2x_frag_free(fp, new_data); | |
619c5cb6 VZ |
819 | drop: |
820 | /* drop the packet and keep the buffer in the bin */ | |
821 | DP(NETIF_MSG_RX_STATUS, | |
822 | "Failed to allocate or map a new skb - dropping packet!\n"); | |
15192a8c | 823 | bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed++; |
9f6c9258 DK |
824 | } |
825 | ||
996dedba MS |
826 | static int bnx2x_alloc_rx_data(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
827 | u16 index, gfp_t gfp_mask) | |
1191cb83 ED |
828 | { |
829 | u8 *data; | |
830 | struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index]; | |
831 | struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index]; | |
832 | dma_addr_t mapping; | |
833 | ||
996dedba | 834 | data = bnx2x_frag_alloc(fp, gfp_mask); |
1191cb83 ED |
835 | if (unlikely(data == NULL)) |
836 | return -ENOMEM; | |
837 | ||
838 | mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD, | |
839 | fp->rx_buf_size, | |
840 | DMA_FROM_DEVICE); | |
841 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
d46d132c | 842 | bnx2x_frag_free(fp, data); |
1191cb83 ED |
843 | BNX2X_ERR("Can't map rx data\n"); |
844 | return -ENOMEM; | |
845 | } | |
846 | ||
847 | rx_buf->data = data; | |
848 | dma_unmap_addr_set(rx_buf, mapping, mapping); | |
849 | ||
850 | rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); | |
851 | rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
852 | ||
853 | return 0; | |
854 | } | |
855 | ||
15192a8c BW |
856 | static |
857 | void bnx2x_csum_validate(struct sk_buff *skb, union eth_rx_cqe *cqe, | |
858 | struct bnx2x_fastpath *fp, | |
859 | struct bnx2x_eth_q_stats *qstats) | |
d6cb3e41 | 860 | { |
e488921f MS |
861 | /* Do nothing if no L4 csum validation was done. |
862 | * We do not check whether IP csum was validated. For IPv4 we assume | |
863 | * that if the card got as far as validating the L4 csum, it also | |
864 | * validated the IP csum. IPv6 has no IP csum. | |
865 | */ | |
d6cb3e41 | 866 | if (cqe->fast_path_cqe.status_flags & |
e488921f | 867 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) |
d6cb3e41 ED |
868 | return; |
869 | ||
e488921f | 870 | /* If L4 validation was done, check if an error was found. */ |
d6cb3e41 ED |
871 | |
872 | if (cqe->fast_path_cqe.type_error_flags & | |
873 | (ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | | |
874 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) | |
15192a8c | 875 | qstats->hw_csum_err++; |
d6cb3e41 ED |
876 | else |
877 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
878 | } | |
9f6c9258 | 879 | |
a8f47eb7 | 880 | static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget) |
9f6c9258 DK |
881 | { |
882 | struct bnx2x *bp = fp->bp; | |
883 | u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons; | |
75b29459 | 884 | u16 sw_comp_cons, sw_comp_prod; |
9f6c9258 | 885 | int rx_pkt = 0; |
75b29459 DK |
886 | union eth_rx_cqe *cqe; |
887 | struct eth_fast_path_rx_cqe *cqe_fp; | |
9f6c9258 DK |
888 | |
889 | #ifdef BNX2X_STOP_ON_ERROR | |
890 | if (unlikely(bp->panic)) | |
891 | return 0; | |
892 | #endif | |
b3529744 EB |
893 | if (budget <= 0) |
894 | return rx_pkt; | |
9f6c9258 | 895 | |
9f6c9258 DK |
896 | bd_cons = fp->rx_bd_cons; |
897 | bd_prod = fp->rx_bd_prod; | |
898 | bd_prod_fw = bd_prod; | |
899 | sw_comp_cons = fp->rx_comp_cons; | |
900 | sw_comp_prod = fp->rx_comp_prod; | |
901 | ||
75b29459 DK |
902 | comp_ring_cons = RCQ_BD(sw_comp_cons); |
903 | cqe = &fp->rx_comp_ring[comp_ring_cons]; | |
904 | cqe_fp = &cqe->fast_path_cqe; | |
9f6c9258 DK |
905 | |
906 | DP(NETIF_MSG_RX_STATUS, | |
75b29459 | 907 | "queue[%d]: sw_comp_cons %u\n", fp->index, sw_comp_cons); |
9f6c9258 | 908 | |
75b29459 | 909 | while (BNX2X_IS_CQE_COMPLETED(cqe_fp)) { |
9f6c9258 DK |
910 | struct sw_rx_bd *rx_buf = NULL; |
911 | struct sk_buff *skb; | |
9f6c9258 | 912 | u8 cqe_fp_flags; |
619c5cb6 | 913 | enum eth_rx_cqe_type cqe_fp_type; |
621b4d66 | 914 | u16 len, pad, queue; |
e52fcb24 | 915 | u8 *data; |
bd5cef03 | 916 | u32 rxhash; |
5495ab75 | 917 | enum pkt_hash_types rxhash_type; |
9f6c9258 | 918 | |
619c5cb6 VZ |
919 | #ifdef BNX2X_STOP_ON_ERROR |
920 | if (unlikely(bp->panic)) | |
921 | return 0; | |
922 | #endif | |
923 | ||
9f6c9258 DK |
924 | bd_prod = RX_BD(bd_prod); |
925 | bd_cons = RX_BD(bd_cons); | |
926 | ||
9aaae044 | 927 | /* A rmb() is required to ensure that the CQE is not read |
928 | * before it is written by the adapter DMA. PCI ordering | |
929 | * rules will make sure the other fields are written before | |
930 | * the marker at the end of struct eth_fast_path_rx_cqe | |
931 | * but without rmb() a weakly ordered processor can process | |
932 | * stale data. Without the barrier TPA state-machine might | |
933 | * enter inconsistent state and kernel stack might be | |
934 | * provided with incorrect packet description - these lead | |
935 | * to various kernel crashed. | |
936 | */ | |
937 | rmb(); | |
938 | ||
619c5cb6 VZ |
939 | cqe_fp_flags = cqe_fp->type_error_flags; |
940 | cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; | |
9f6c9258 | 941 | |
51c1a580 MS |
942 | DP(NETIF_MSG_RX_STATUS, |
943 | "CQE type %x err %x status %x queue %x vlan %x len %u\n", | |
944 | CQE_TYPE(cqe_fp_flags), | |
619c5cb6 VZ |
945 | cqe_fp_flags, cqe_fp->status_flags, |
946 | le32_to_cpu(cqe_fp->rss_hash_result), | |
621b4d66 DK |
947 | le16_to_cpu(cqe_fp->vlan_tag), |
948 | le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len)); | |
9f6c9258 DK |
949 | |
950 | /* is this a slowpath msg? */ | |
619c5cb6 | 951 | if (unlikely(CQE_TYPE_SLOW(cqe_fp_type))) { |
9f6c9258 DK |
952 | bnx2x_sp_event(fp, cqe); |
953 | goto next_cqe; | |
e52fcb24 | 954 | } |
621b4d66 | 955 | |
e52fcb24 ED |
956 | rx_buf = &fp->rx_buf_ring[bd_cons]; |
957 | data = rx_buf->data; | |
9f6c9258 | 958 | |
e52fcb24 | 959 | if (!CQE_TYPE_FAST(cqe_fp_type)) { |
621b4d66 DK |
960 | struct bnx2x_agg_info *tpa_info; |
961 | u16 frag_size, pages; | |
619c5cb6 | 962 | #ifdef BNX2X_STOP_ON_ERROR |
e52fcb24 | 963 | /* sanity check */ |
7e6b4d44 | 964 | if (fp->mode == TPA_MODE_DISABLED && |
e52fcb24 ED |
965 | (CQE_TYPE_START(cqe_fp_type) || |
966 | CQE_TYPE_STOP(cqe_fp_type))) | |
7e6b4d44 | 967 | BNX2X_ERR("START/STOP packet while TPA disabled, type %x\n", |
e52fcb24 | 968 | CQE_TYPE(cqe_fp_type)); |
619c5cb6 | 969 | #endif |
9f6c9258 | 970 | |
e52fcb24 ED |
971 | if (CQE_TYPE_START(cqe_fp_type)) { |
972 | u16 queue = cqe_fp->queue_index; | |
973 | DP(NETIF_MSG_RX_STATUS, | |
974 | "calling tpa_start on queue %d\n", | |
975 | queue); | |
9f6c9258 | 976 | |
e52fcb24 ED |
977 | bnx2x_tpa_start(fp, queue, |
978 | bd_cons, bd_prod, | |
979 | cqe_fp); | |
621b4d66 | 980 | |
e52fcb24 | 981 | goto next_rx; |
621b4d66 DK |
982 | } |
983 | queue = cqe->end_agg_cqe.queue_index; | |
984 | tpa_info = &fp->tpa_info[queue]; | |
985 | DP(NETIF_MSG_RX_STATUS, | |
986 | "calling tpa_stop on queue %d\n", | |
987 | queue); | |
988 | ||
989 | frag_size = le16_to_cpu(cqe->end_agg_cqe.pkt_len) - | |
990 | tpa_info->len_on_bd; | |
991 | ||
992 | if (fp->mode == TPA_MODE_GRO) | |
993 | pages = (frag_size + tpa_info->full_page - 1) / | |
994 | tpa_info->full_page; | |
995 | else | |
996 | pages = SGE_PAGE_ALIGN(frag_size) >> | |
997 | SGE_PAGE_SHIFT; | |
998 | ||
999 | bnx2x_tpa_stop(bp, fp, tpa_info, pages, | |
1000 | &cqe->end_agg_cqe, comp_ring_cons); | |
9f6c9258 | 1001 | #ifdef BNX2X_STOP_ON_ERROR |
621b4d66 DK |
1002 | if (bp->panic) |
1003 | return 0; | |
9f6c9258 DK |
1004 | #endif |
1005 | ||
621b4d66 DK |
1006 | bnx2x_update_sge_prod(fp, pages, &cqe->end_agg_cqe); |
1007 | goto next_cqe; | |
e52fcb24 ED |
1008 | } |
1009 | /* non TPA */ | |
621b4d66 | 1010 | len = le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len); |
e52fcb24 ED |
1011 | pad = cqe_fp->placement_offset; |
1012 | dma_sync_single_for_cpu(&bp->pdev->dev, | |
9f6c9258 | 1013 | dma_unmap_addr(rx_buf, mapping), |
e52fcb24 ED |
1014 | pad + RX_COPY_THRESH, |
1015 | DMA_FROM_DEVICE); | |
1016 | pad += NET_SKB_PAD; | |
1017 | prefetch(data + pad); /* speedup eth_type_trans() */ | |
1018 | /* is this an error packet? */ | |
1019 | if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) { | |
51c1a580 | 1020 | DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS, |
e52fcb24 ED |
1021 | "ERROR flags %x rx packet %u\n", |
1022 | cqe_fp_flags, sw_comp_cons); | |
15192a8c | 1023 | bnx2x_fp_qstats(bp, fp)->rx_err_discard_pkt++; |
e52fcb24 ED |
1024 | goto reuse_rx; |
1025 | } | |
9f6c9258 | 1026 | |
e52fcb24 ED |
1027 | /* Since we don't have a jumbo ring |
1028 | * copy small packets if mtu > 1500 | |
1029 | */ | |
1030 | if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) && | |
1031 | (len <= RX_COPY_THRESH)) { | |
45abfb10 | 1032 | skb = napi_alloc_skb(&fp->napi, len); |
e52fcb24 | 1033 | if (skb == NULL) { |
51c1a580 | 1034 | DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS, |
e52fcb24 | 1035 | "ERROR packet dropped because of alloc failure\n"); |
15192a8c | 1036 | bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++; |
9f6c9258 DK |
1037 | goto reuse_rx; |
1038 | } | |
e52fcb24 ED |
1039 | memcpy(skb->data, data + pad, len); |
1040 | bnx2x_reuse_rx_data(fp, bd_cons, bd_prod); | |
1041 | } else { | |
996dedba MS |
1042 | if (likely(bnx2x_alloc_rx_data(bp, fp, bd_prod, |
1043 | GFP_ATOMIC) == 0)) { | |
9f6c9258 | 1044 | dma_unmap_single(&bp->pdev->dev, |
e52fcb24 | 1045 | dma_unmap_addr(rx_buf, mapping), |
a8c94b91 | 1046 | fp->rx_buf_size, |
9f6c9258 | 1047 | DMA_FROM_DEVICE); |
d46d132c | 1048 | skb = build_skb(data, fp->rx_frag_size); |
e52fcb24 | 1049 | if (unlikely(!skb)) { |
d46d132c | 1050 | bnx2x_frag_free(fp, data); |
15192a8c BW |
1051 | bnx2x_fp_qstats(bp, fp)-> |
1052 | rx_skb_alloc_failed++; | |
e52fcb24 ED |
1053 | goto next_rx; |
1054 | } | |
9f6c9258 | 1055 | skb_reserve(skb, pad); |
9f6c9258 | 1056 | } else { |
51c1a580 MS |
1057 | DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS, |
1058 | "ERROR packet dropped because of alloc failure\n"); | |
15192a8c | 1059 | bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++; |
9f6c9258 | 1060 | reuse_rx: |
e52fcb24 | 1061 | bnx2x_reuse_rx_data(fp, bd_cons, bd_prod); |
9f6c9258 DK |
1062 | goto next_rx; |
1063 | } | |
036d2df9 | 1064 | } |
9f6c9258 | 1065 | |
036d2df9 DK |
1066 | skb_put(skb, len); |
1067 | skb->protocol = eth_type_trans(skb, bp->dev); | |
9f6c9258 | 1068 | |
036d2df9 | 1069 | /* Set Toeplitz hash for a none-LRO skb */ |
5495ab75 TH |
1070 | rxhash = bnx2x_get_rxhash(bp, cqe_fp, &rxhash_type); |
1071 | skb_set_hash(skb, rxhash, rxhash_type); | |
9f6c9258 | 1072 | |
036d2df9 | 1073 | skb_checksum_none_assert(skb); |
f85582f8 | 1074 | |
d6cb3e41 | 1075 | if (bp->dev->features & NETIF_F_RXCSUM) |
15192a8c BW |
1076 | bnx2x_csum_validate(skb, cqe, fp, |
1077 | bnx2x_fp_qstats(bp, fp)); | |
9f6c9258 | 1078 | |
f233cafe | 1079 | skb_record_rx_queue(skb, fp->rx_queue); |
9f6c9258 | 1080 | |
eeed018c | 1081 | /* Check if this packet was timestamped */ |
56daf66d | 1082 | if (unlikely(cqe->fast_path_cqe.type_error_flags & |
eeed018c MK |
1083 | (1 << ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT))) |
1084 | bnx2x_set_rx_ts(bp, skb); | |
1085 | ||
619c5cb6 VZ |
1086 | if (le16_to_cpu(cqe_fp->pars_flags.flags) & |
1087 | PARSING_FLAGS_VLAN) | |
86a9bad3 | 1088 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), |
619c5cb6 | 1089 | le16_to_cpu(cqe_fp->vlan_tag)); |
9f6c9258 | 1090 | |
b59768c6 | 1091 | napi_gro_receive(&fp->napi, skb); |
9f6c9258 | 1092 | next_rx: |
e52fcb24 | 1093 | rx_buf->data = NULL; |
9f6c9258 DK |
1094 | |
1095 | bd_cons = NEXT_RX_IDX(bd_cons); | |
1096 | bd_prod = NEXT_RX_IDX(bd_prod); | |
1097 | bd_prod_fw = NEXT_RX_IDX(bd_prod_fw); | |
1098 | rx_pkt++; | |
1099 | next_cqe: | |
1100 | sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod); | |
1101 | sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons); | |
1102 | ||
75b29459 DK |
1103 | /* mark CQE as free */ |
1104 | BNX2X_SEED_CQE(cqe_fp); | |
1105 | ||
9f6c9258 DK |
1106 | if (rx_pkt == budget) |
1107 | break; | |
75b29459 DK |
1108 | |
1109 | comp_ring_cons = RCQ_BD(sw_comp_cons); | |
1110 | cqe = &fp->rx_comp_ring[comp_ring_cons]; | |
1111 | cqe_fp = &cqe->fast_path_cqe; | |
9f6c9258 DK |
1112 | } /* while */ |
1113 | ||
1114 | fp->rx_bd_cons = bd_cons; | |
1115 | fp->rx_bd_prod = bd_prod_fw; | |
1116 | fp->rx_comp_cons = sw_comp_cons; | |
1117 | fp->rx_comp_prod = sw_comp_prod; | |
1118 | ||
1119 | /* Update producers */ | |
1120 | bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod, | |
1121 | fp->rx_sge_prod); | |
1122 | ||
9f6c9258 DK |
1123 | return rx_pkt; |
1124 | } | |
1125 | ||
1126 | static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie) | |
1127 | { | |
1128 | struct bnx2x_fastpath *fp = fp_cookie; | |
1129 | struct bnx2x *bp = fp->bp; | |
6383c0b3 | 1130 | u8 cos; |
9f6c9258 | 1131 | |
51c1a580 MS |
1132 | DP(NETIF_MSG_INTR, |
1133 | "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n", | |
523224a3 | 1134 | fp->index, fp->fw_sb_id, fp->igu_sb_id); |
ecf01c22 | 1135 | |
523224a3 | 1136 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); |
9f6c9258 DK |
1137 | |
1138 | #ifdef BNX2X_STOP_ON_ERROR | |
1139 | if (unlikely(bp->panic)) | |
1140 | return IRQ_HANDLED; | |
1141 | #endif | |
1142 | ||
1143 | /* Handle Rx and Tx according to MSI-X vector */ | |
6383c0b3 | 1144 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 1145 | prefetch(fp->txdata_ptr[cos]->tx_cons_sb); |
6383c0b3 | 1146 | |
523224a3 | 1147 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
f5fbf115 | 1148 | napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi)); |
9f6c9258 DK |
1149 | |
1150 | return IRQ_HANDLED; | |
1151 | } | |
1152 | ||
9f6c9258 DK |
1153 | /* HW Lock for shared dual port PHYs */ |
1154 | void bnx2x_acquire_phy_lock(struct bnx2x *bp) | |
1155 | { | |
1156 | mutex_lock(&bp->port.phy_mutex); | |
1157 | ||
8203c4b6 | 1158 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO); |
9f6c9258 DK |
1159 | } |
1160 | ||
1161 | void bnx2x_release_phy_lock(struct bnx2x *bp) | |
1162 | { | |
8203c4b6 | 1163 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO); |
9f6c9258 DK |
1164 | |
1165 | mutex_unlock(&bp->port.phy_mutex); | |
1166 | } | |
1167 | ||
0793f83f DK |
1168 | /* calculates MF speed according to current linespeed and MF configuration */ |
1169 | u16 bnx2x_get_mf_speed(struct bnx2x *bp) | |
1170 | { | |
1171 | u16 line_speed = bp->link_vars.line_speed; | |
1172 | if (IS_MF(bp)) { | |
faa6fcbb DK |
1173 | u16 maxCfg = bnx2x_extract_max_cfg(bp, |
1174 | bp->mf_config[BP_VN(bp)]); | |
1175 | ||
1176 | /* Calculate the current MAX line speed limit for the MF | |
1177 | * devices | |
0793f83f | 1178 | */ |
da3cc2da | 1179 | if (IS_MF_PERCENT_BW(bp)) |
faa6fcbb DK |
1180 | line_speed = (line_speed * maxCfg) / 100; |
1181 | else { /* SD mode */ | |
0793f83f DK |
1182 | u16 vn_max_rate = maxCfg * 100; |
1183 | ||
1184 | if (vn_max_rate < line_speed) | |
1185 | line_speed = vn_max_rate; | |
faa6fcbb | 1186 | } |
0793f83f DK |
1187 | } |
1188 | ||
1189 | return line_speed; | |
1190 | } | |
1191 | ||
2ae17f66 VZ |
1192 | /** |
1193 | * bnx2x_fill_report_data - fill link report data to report | |
1194 | * | |
1195 | * @bp: driver handle | |
1196 | * @data: link state to update | |
1197 | * | |
1198 | * It uses a none-atomic bit operations because is called under the mutex. | |
1199 | */ | |
1191cb83 ED |
1200 | static void bnx2x_fill_report_data(struct bnx2x *bp, |
1201 | struct bnx2x_link_report_data *data) | |
2ae17f66 | 1202 | { |
2ae17f66 VZ |
1203 | memset(data, 0, sizeof(*data)); |
1204 | ||
6495d15a DK |
1205 | if (IS_PF(bp)) { |
1206 | /* Fill the report data: effective line speed */ | |
1207 | data->line_speed = bnx2x_get_mf_speed(bp); | |
1208 | ||
1209 | /* Link is down */ | |
1210 | if (!bp->link_vars.link_up || (bp->flags & MF_FUNC_DIS)) | |
1211 | __set_bit(BNX2X_LINK_REPORT_LINK_DOWN, | |
1212 | &data->link_report_flags); | |
1213 | ||
1214 | if (!BNX2X_NUM_ETH_QUEUES(bp)) | |
1215 | __set_bit(BNX2X_LINK_REPORT_LINK_DOWN, | |
1216 | &data->link_report_flags); | |
1217 | ||
1218 | /* Full DUPLEX */ | |
1219 | if (bp->link_vars.duplex == DUPLEX_FULL) | |
1220 | __set_bit(BNX2X_LINK_REPORT_FD, | |
1221 | &data->link_report_flags); | |
1222 | ||
1223 | /* Rx Flow Control is ON */ | |
1224 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) | |
1225 | __set_bit(BNX2X_LINK_REPORT_RX_FC_ON, | |
1226 | &data->link_report_flags); | |
1227 | ||
1228 | /* Tx Flow Control is ON */ | |
1229 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
1230 | __set_bit(BNX2X_LINK_REPORT_TX_FC_ON, | |
1231 | &data->link_report_flags); | |
1232 | } else { /* VF */ | |
1233 | *data = bp->vf_link_vars; | |
1234 | } | |
2ae17f66 VZ |
1235 | } |
1236 | ||
1237 | /** | |
1238 | * bnx2x_link_report - report link status to OS. | |
1239 | * | |
1240 | * @bp: driver handle | |
1241 | * | |
1242 | * Calls the __bnx2x_link_report() under the same locking scheme | |
1243 | * as a link/PHY state managing code to ensure a consistent link | |
1244 | * reporting. | |
1245 | */ | |
1246 | ||
9f6c9258 DK |
1247 | void bnx2x_link_report(struct bnx2x *bp) |
1248 | { | |
2ae17f66 VZ |
1249 | bnx2x_acquire_phy_lock(bp); |
1250 | __bnx2x_link_report(bp); | |
1251 | bnx2x_release_phy_lock(bp); | |
1252 | } | |
9f6c9258 | 1253 | |
2ae17f66 VZ |
1254 | /** |
1255 | * __bnx2x_link_report - report link status to OS. | |
1256 | * | |
1257 | * @bp: driver handle | |
1258 | * | |
16a5fd92 | 1259 | * None atomic implementation. |
2ae17f66 VZ |
1260 | * Should be called under the phy_lock. |
1261 | */ | |
1262 | void __bnx2x_link_report(struct bnx2x *bp) | |
1263 | { | |
1264 | struct bnx2x_link_report_data cur_data; | |
9f6c9258 | 1265 | |
6a9f0ecb SRK |
1266 | if (bp->force_link_down) { |
1267 | bp->link_vars.link_up = 0; | |
1268 | return; | |
1269 | } | |
1270 | ||
2ae17f66 | 1271 | /* reread mf_cfg */ |
ad5afc89 | 1272 | if (IS_PF(bp) && !CHIP_IS_E1(bp)) |
2ae17f66 VZ |
1273 | bnx2x_read_mf_cfg(bp); |
1274 | ||
1275 | /* Read the current link report info */ | |
1276 | bnx2x_fill_report_data(bp, &cur_data); | |
1277 | ||
1278 | /* Don't report link down or exactly the same link status twice */ | |
1279 | if (!memcmp(&cur_data, &bp->last_reported_link, sizeof(cur_data)) || | |
1280 | (test_bit(BNX2X_LINK_REPORT_LINK_DOWN, | |
1281 | &bp->last_reported_link.link_report_flags) && | |
1282 | test_bit(BNX2X_LINK_REPORT_LINK_DOWN, | |
1283 | &cur_data.link_report_flags))) | |
1284 | return; | |
1285 | ||
1286 | bp->link_cnt++; | |
9f6c9258 | 1287 | |
2ae17f66 VZ |
1288 | /* We are going to report a new link parameters now - |
1289 | * remember the current data for the next time. | |
1290 | */ | |
1291 | memcpy(&bp->last_reported_link, &cur_data, sizeof(cur_data)); | |
9f6c9258 | 1292 | |
6495d15a DK |
1293 | /* propagate status to VFs */ |
1294 | if (IS_PF(bp)) | |
1295 | bnx2x_iov_link_update(bp); | |
1296 | ||
2ae17f66 VZ |
1297 | if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN, |
1298 | &cur_data.link_report_flags)) { | |
1299 | netif_carrier_off(bp->dev); | |
1300 | netdev_err(bp->dev, "NIC Link is Down\n"); | |
1301 | return; | |
1302 | } else { | |
94f05b0f JP |
1303 | const char *duplex; |
1304 | const char *flow; | |
1305 | ||
2ae17f66 | 1306 | netif_carrier_on(bp->dev); |
9f6c9258 | 1307 | |
2ae17f66 VZ |
1308 | if (test_and_clear_bit(BNX2X_LINK_REPORT_FD, |
1309 | &cur_data.link_report_flags)) | |
94f05b0f | 1310 | duplex = "full"; |
9f6c9258 | 1311 | else |
94f05b0f | 1312 | duplex = "half"; |
9f6c9258 | 1313 | |
2ae17f66 VZ |
1314 | /* Handle the FC at the end so that only these flags would be |
1315 | * possibly set. This way we may easily check if there is no FC | |
1316 | * enabled. | |
1317 | */ | |
1318 | if (cur_data.link_report_flags) { | |
1319 | if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON, | |
1320 | &cur_data.link_report_flags)) { | |
2ae17f66 VZ |
1321 | if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON, |
1322 | &cur_data.link_report_flags)) | |
94f05b0f JP |
1323 | flow = "ON - receive & transmit"; |
1324 | else | |
1325 | flow = "ON - receive"; | |
9f6c9258 | 1326 | } else { |
94f05b0f | 1327 | flow = "ON - transmit"; |
9f6c9258 | 1328 | } |
94f05b0f JP |
1329 | } else { |
1330 | flow = "none"; | |
9f6c9258 | 1331 | } |
94f05b0f JP |
1332 | netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n", |
1333 | cur_data.line_speed, duplex, flow); | |
9f6c9258 DK |
1334 | } |
1335 | } | |
1336 | ||
1191cb83 ED |
1337 | static void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp) |
1338 | { | |
1339 | int i; | |
1340 | ||
1341 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { | |
1342 | struct eth_rx_sge *sge; | |
1343 | ||
1344 | sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2]; | |
1345 | sge->addr_hi = | |
1346 | cpu_to_le32(U64_HI(fp->rx_sge_mapping + | |
1347 | BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); | |
1348 | ||
1349 | sge->addr_lo = | |
1350 | cpu_to_le32(U64_LO(fp->rx_sge_mapping + | |
1351 | BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); | |
1352 | } | |
1353 | } | |
1354 | ||
1355 | static void bnx2x_free_tpa_pool(struct bnx2x *bp, | |
1356 | struct bnx2x_fastpath *fp, int last) | |
1357 | { | |
1358 | int i; | |
1359 | ||
1360 | for (i = 0; i < last; i++) { | |
1361 | struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i]; | |
1362 | struct sw_rx_bd *first_buf = &tpa_info->first_buf; | |
1363 | u8 *data = first_buf->data; | |
1364 | ||
1365 | if (data == NULL) { | |
1366 | DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i); | |
1367 | continue; | |
1368 | } | |
1369 | if (tpa_info->tpa_state == BNX2X_TPA_START) | |
1370 | dma_unmap_single(&bp->pdev->dev, | |
1371 | dma_unmap_addr(first_buf, mapping), | |
1372 | fp->rx_buf_size, DMA_FROM_DEVICE); | |
d46d132c | 1373 | bnx2x_frag_free(fp, data); |
1191cb83 ED |
1374 | first_buf->data = NULL; |
1375 | } | |
1376 | } | |
1377 | ||
55c11941 MS |
1378 | void bnx2x_init_rx_rings_cnic(struct bnx2x *bp) |
1379 | { | |
1380 | int j; | |
1381 | ||
1382 | for_each_rx_queue_cnic(bp, j) { | |
1383 | struct bnx2x_fastpath *fp = &bp->fp[j]; | |
1384 | ||
1385 | fp->rx_bd_cons = 0; | |
1386 | ||
1387 | /* Activate BD ring */ | |
1388 | /* Warning! | |
1389 | * this will generate an interrupt (to the TSTORM) | |
1390 | * must only be done after chip is initialized | |
1391 | */ | |
1392 | bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod, | |
1393 | fp->rx_sge_prod); | |
1394 | } | |
1395 | } | |
1396 | ||
9f6c9258 DK |
1397 | void bnx2x_init_rx_rings(struct bnx2x *bp) |
1398 | { | |
1399 | int func = BP_FUNC(bp); | |
523224a3 | 1400 | u16 ring_prod; |
9f6c9258 | 1401 | int i, j; |
25141580 | 1402 | |
b3b83c3f | 1403 | /* Allocate TPA resources */ |
55c11941 | 1404 | for_each_eth_queue(bp, j) { |
523224a3 | 1405 | struct bnx2x_fastpath *fp = &bp->fp[j]; |
9f6c9258 | 1406 | |
a8c94b91 VZ |
1407 | DP(NETIF_MSG_IFUP, |
1408 | "mtu %d rx_buf_size %d\n", bp->dev->mtu, fp->rx_buf_size); | |
1409 | ||
7e6b4d44 | 1410 | if (fp->mode != TPA_MODE_DISABLED) { |
16a5fd92 | 1411 | /* Fill the per-aggregation pool */ |
dfacf138 | 1412 | for (i = 0; i < MAX_AGG_QS(bp); i++) { |
619c5cb6 VZ |
1413 | struct bnx2x_agg_info *tpa_info = |
1414 | &fp->tpa_info[i]; | |
1415 | struct sw_rx_bd *first_buf = | |
1416 | &tpa_info->first_buf; | |
1417 | ||
996dedba MS |
1418 | first_buf->data = |
1419 | bnx2x_frag_alloc(fp, GFP_KERNEL); | |
e52fcb24 | 1420 | if (!first_buf->data) { |
51c1a580 MS |
1421 | BNX2X_ERR("Failed to allocate TPA skb pool for queue[%d] - disabling TPA on this queue!\n", |
1422 | j); | |
9f6c9258 | 1423 | bnx2x_free_tpa_pool(bp, fp, i); |
7e6b4d44 | 1424 | fp->mode = TPA_MODE_DISABLED; |
9f6c9258 DK |
1425 | break; |
1426 | } | |
619c5cb6 VZ |
1427 | dma_unmap_addr_set(first_buf, mapping, 0); |
1428 | tpa_info->tpa_state = BNX2X_TPA_STOP; | |
9f6c9258 | 1429 | } |
523224a3 DK |
1430 | |
1431 | /* "next page" elements initialization */ | |
1432 | bnx2x_set_next_page_sgl(fp); | |
1433 | ||
1434 | /* set SGEs bit mask */ | |
1435 | bnx2x_init_sge_ring_bit_mask(fp); | |
1436 | ||
1437 | /* Allocate SGEs and initialize the ring elements */ | |
1438 | for (i = 0, ring_prod = 0; | |
1439 | i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) { | |
1440 | ||
996dedba MS |
1441 | if (bnx2x_alloc_rx_sge(bp, fp, ring_prod, |
1442 | GFP_KERNEL) < 0) { | |
51c1a580 MS |
1443 | BNX2X_ERR("was only able to allocate %d rx sges\n", |
1444 | i); | |
1445 | BNX2X_ERR("disabling TPA for queue[%d]\n", | |
1446 | j); | |
523224a3 | 1447 | /* Cleanup already allocated elements */ |
619c5cb6 VZ |
1448 | bnx2x_free_rx_sge_range(bp, fp, |
1449 | ring_prod); | |
1450 | bnx2x_free_tpa_pool(bp, fp, | |
dfacf138 | 1451 | MAX_AGG_QS(bp)); |
7e6b4d44 | 1452 | fp->mode = TPA_MODE_DISABLED; |
523224a3 DK |
1453 | ring_prod = 0; |
1454 | break; | |
1455 | } | |
1456 | ring_prod = NEXT_SGE_IDX(ring_prod); | |
1457 | } | |
1458 | ||
1459 | fp->rx_sge_prod = ring_prod; | |
9f6c9258 DK |
1460 | } |
1461 | } | |
1462 | ||
55c11941 | 1463 | for_each_eth_queue(bp, j) { |
9f6c9258 DK |
1464 | struct bnx2x_fastpath *fp = &bp->fp[j]; |
1465 | ||
1466 | fp->rx_bd_cons = 0; | |
9f6c9258 | 1467 | |
b3b83c3f DK |
1468 | /* Activate BD ring */ |
1469 | /* Warning! | |
1470 | * this will generate an interrupt (to the TSTORM) | |
1471 | * must only be done after chip is initialized | |
1472 | */ | |
1473 | bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod, | |
1474 | fp->rx_sge_prod); | |
9f6c9258 | 1475 | |
9f6c9258 DK |
1476 | if (j != 0) |
1477 | continue; | |
1478 | ||
619c5cb6 | 1479 | if (CHIP_IS_E1(bp)) { |
f2e0899f DK |
1480 | REG_WR(bp, BAR_USTRORM_INTMEM + |
1481 | USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func), | |
1482 | U64_LO(fp->rx_comp_mapping)); | |
1483 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
1484 | USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4, | |
1485 | U64_HI(fp->rx_comp_mapping)); | |
1486 | } | |
9f6c9258 DK |
1487 | } |
1488 | } | |
f85582f8 | 1489 | |
55c11941 | 1490 | static void bnx2x_free_tx_skbs_queue(struct bnx2x_fastpath *fp) |
9f6c9258 | 1491 | { |
6383c0b3 | 1492 | u8 cos; |
55c11941 | 1493 | struct bnx2x *bp = fp->bp; |
9f6c9258 | 1494 | |
55c11941 MS |
1495 | for_each_cos_in_tx_queue(fp, cos) { |
1496 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; | |
1497 | unsigned pkts_compl = 0, bytes_compl = 0; | |
9f6c9258 | 1498 | |
55c11941 MS |
1499 | u16 sw_prod = txdata->tx_pkt_prod; |
1500 | u16 sw_cons = txdata->tx_pkt_cons; | |
9f6c9258 | 1501 | |
55c11941 MS |
1502 | while (sw_cons != sw_prod) { |
1503 | bnx2x_free_tx_pkt(bp, txdata, TX_BD(sw_cons), | |
1504 | &pkts_compl, &bytes_compl); | |
1505 | sw_cons++; | |
9f6c9258 | 1506 | } |
55c11941 MS |
1507 | |
1508 | netdev_tx_reset_queue( | |
1509 | netdev_get_tx_queue(bp->dev, | |
1510 | txdata->txq_index)); | |
1511 | } | |
1512 | } | |
1513 | ||
1514 | static void bnx2x_free_tx_skbs_cnic(struct bnx2x *bp) | |
1515 | { | |
1516 | int i; | |
1517 | ||
1518 | for_each_tx_queue_cnic(bp, i) { | |
1519 | bnx2x_free_tx_skbs_queue(&bp->fp[i]); | |
1520 | } | |
1521 | } | |
1522 | ||
1523 | static void bnx2x_free_tx_skbs(struct bnx2x *bp) | |
1524 | { | |
1525 | int i; | |
1526 | ||
1527 | for_each_eth_queue(bp, i) { | |
1528 | bnx2x_free_tx_skbs_queue(&bp->fp[i]); | |
9f6c9258 DK |
1529 | } |
1530 | } | |
1531 | ||
b3b83c3f DK |
1532 | static void bnx2x_free_rx_bds(struct bnx2x_fastpath *fp) |
1533 | { | |
1534 | struct bnx2x *bp = fp->bp; | |
1535 | int i; | |
1536 | ||
1537 | /* ring wasn't allocated */ | |
1538 | if (fp->rx_buf_ring == NULL) | |
1539 | return; | |
1540 | ||
1541 | for (i = 0; i < NUM_RX_BD; i++) { | |
1542 | struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i]; | |
e52fcb24 | 1543 | u8 *data = rx_buf->data; |
b3b83c3f | 1544 | |
e52fcb24 | 1545 | if (data == NULL) |
b3b83c3f | 1546 | continue; |
b3b83c3f DK |
1547 | dma_unmap_single(&bp->pdev->dev, |
1548 | dma_unmap_addr(rx_buf, mapping), | |
1549 | fp->rx_buf_size, DMA_FROM_DEVICE); | |
1550 | ||
e52fcb24 | 1551 | rx_buf->data = NULL; |
d46d132c | 1552 | bnx2x_frag_free(fp, data); |
b3b83c3f DK |
1553 | } |
1554 | } | |
1555 | ||
55c11941 MS |
1556 | static void bnx2x_free_rx_skbs_cnic(struct bnx2x *bp) |
1557 | { | |
1558 | int j; | |
1559 | ||
1560 | for_each_rx_queue_cnic(bp, j) { | |
1561 | bnx2x_free_rx_bds(&bp->fp[j]); | |
1562 | } | |
1563 | } | |
1564 | ||
9f6c9258 DK |
1565 | static void bnx2x_free_rx_skbs(struct bnx2x *bp) |
1566 | { | |
b3b83c3f | 1567 | int j; |
9f6c9258 | 1568 | |
55c11941 | 1569 | for_each_eth_queue(bp, j) { |
9f6c9258 DK |
1570 | struct bnx2x_fastpath *fp = &bp->fp[j]; |
1571 | ||
b3b83c3f | 1572 | bnx2x_free_rx_bds(fp); |
9f6c9258 | 1573 | |
7e6b4d44 | 1574 | if (fp->mode != TPA_MODE_DISABLED) |
dfacf138 | 1575 | bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp)); |
9f6c9258 DK |
1576 | } |
1577 | } | |
1578 | ||
a8f47eb7 | 1579 | static void bnx2x_free_skbs_cnic(struct bnx2x *bp) |
55c11941 MS |
1580 | { |
1581 | bnx2x_free_tx_skbs_cnic(bp); | |
1582 | bnx2x_free_rx_skbs_cnic(bp); | |
1583 | } | |
1584 | ||
9f6c9258 DK |
1585 | void bnx2x_free_skbs(struct bnx2x *bp) |
1586 | { | |
1587 | bnx2x_free_tx_skbs(bp); | |
1588 | bnx2x_free_rx_skbs(bp); | |
1589 | } | |
1590 | ||
e3835b99 DK |
1591 | void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value) |
1592 | { | |
1593 | /* load old values */ | |
1594 | u32 mf_cfg = bp->mf_config[BP_VN(bp)]; | |
1595 | ||
1596 | if (value != bnx2x_extract_max_cfg(bp, mf_cfg)) { | |
1597 | /* leave all but MAX value */ | |
1598 | mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK; | |
1599 | ||
1600 | /* set new MAX value */ | |
1601 | mf_cfg |= (value << FUNC_MF_CFG_MAX_BW_SHIFT) | |
1602 | & FUNC_MF_CFG_MAX_BW_MASK; | |
1603 | ||
1604 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, mf_cfg); | |
1605 | } | |
1606 | } | |
1607 | ||
ca92429f DK |
1608 | /** |
1609 | * bnx2x_free_msix_irqs - free previously requested MSI-X IRQ vectors | |
1610 | * | |
1611 | * @bp: driver handle | |
1612 | * @nvecs: number of vectors to be released | |
1613 | */ | |
1614 | static void bnx2x_free_msix_irqs(struct bnx2x *bp, int nvecs) | |
9f6c9258 | 1615 | { |
ca92429f | 1616 | int i, offset = 0; |
9f6c9258 | 1617 | |
ca92429f DK |
1618 | if (nvecs == offset) |
1619 | return; | |
ad5afc89 AE |
1620 | |
1621 | /* VFs don't have a default SB */ | |
1622 | if (IS_PF(bp)) { | |
1623 | free_irq(bp->msix_table[offset].vector, bp->dev); | |
1624 | DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n", | |
1625 | bp->msix_table[offset].vector); | |
1626 | offset++; | |
1627 | } | |
55c11941 MS |
1628 | |
1629 | if (CNIC_SUPPORT(bp)) { | |
1630 | if (nvecs == offset) | |
1631 | return; | |
1632 | offset++; | |
1633 | } | |
ca92429f | 1634 | |
ec6ba945 | 1635 | for_each_eth_queue(bp, i) { |
ca92429f DK |
1636 | if (nvecs == offset) |
1637 | return; | |
51c1a580 MS |
1638 | DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq\n", |
1639 | i, bp->msix_table[offset].vector); | |
9f6c9258 | 1640 | |
ca92429f | 1641 | free_irq(bp->msix_table[offset++].vector, &bp->fp[i]); |
9f6c9258 DK |
1642 | } |
1643 | } | |
1644 | ||
d6214d7a | 1645 | void bnx2x_free_irq(struct bnx2x *bp) |
9f6c9258 | 1646 | { |
30a5de77 | 1647 | if (bp->flags & USING_MSIX_FLAG && |
ad5afc89 AE |
1648 | !(bp->flags & USING_SINGLE_MSIX_FLAG)) { |
1649 | int nvecs = BNX2X_NUM_ETH_QUEUES(bp) + CNIC_SUPPORT(bp); | |
1650 | ||
1651 | /* vfs don't have a default status block */ | |
1652 | if (IS_PF(bp)) | |
1653 | nvecs++; | |
1654 | ||
1655 | bnx2x_free_msix_irqs(bp, nvecs); | |
1656 | } else { | |
30a5de77 | 1657 | free_irq(bp->dev->irq, bp->dev); |
ad5afc89 | 1658 | } |
9f6c9258 DK |
1659 | } |
1660 | ||
0e8d2ec5 | 1661 | int bnx2x_enable_msix(struct bnx2x *bp) |
9f6c9258 | 1662 | { |
1ab4434c | 1663 | int msix_vec = 0, i, rc; |
9f6c9258 | 1664 | |
1ab4434c AE |
1665 | /* VFs don't have a default status block */ |
1666 | if (IS_PF(bp)) { | |
1667 | bp->msix_table[msix_vec].entry = msix_vec; | |
1668 | BNX2X_DEV_INFO("msix_table[0].entry = %d (slowpath)\n", | |
1669 | bp->msix_table[0].entry); | |
1670 | msix_vec++; | |
1671 | } | |
9f6c9258 | 1672 | |
55c11941 MS |
1673 | /* Cnic requires an msix vector for itself */ |
1674 | if (CNIC_SUPPORT(bp)) { | |
1675 | bp->msix_table[msix_vec].entry = msix_vec; | |
1676 | BNX2X_DEV_INFO("msix_table[%d].entry = %d (CNIC)\n", | |
1677 | msix_vec, bp->msix_table[msix_vec].entry); | |
1678 | msix_vec++; | |
1679 | } | |
1680 | ||
6383c0b3 | 1681 | /* We need separate vectors for ETH queues only (not FCoE) */ |
ec6ba945 | 1682 | for_each_eth_queue(bp, i) { |
d6214d7a | 1683 | bp->msix_table[msix_vec].entry = msix_vec; |
51c1a580 MS |
1684 | BNX2X_DEV_INFO("msix_table[%d].entry = %d (fastpath #%u)\n", |
1685 | msix_vec, msix_vec, i); | |
d6214d7a | 1686 | msix_vec++; |
9f6c9258 DK |
1687 | } |
1688 | ||
1ab4434c AE |
1689 | DP(BNX2X_MSG_SP, "about to request enable msix with %d vectors\n", |
1690 | msix_vec); | |
d6214d7a | 1691 | |
a5444b17 AG |
1692 | rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0], |
1693 | BNX2X_MIN_MSIX_VEC_CNT(bp), msix_vec); | |
9f6c9258 DK |
1694 | /* |
1695 | * reconfigure number of tx/rx queues according to available | |
1696 | * MSI-X vectors | |
1697 | */ | |
a5444b17 | 1698 | if (rc == -ENOSPC) { |
30a5de77 | 1699 | /* Get by with single vector */ |
a5444b17 AG |
1700 | rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0], 1, 1); |
1701 | if (rc < 0) { | |
30a5de77 DK |
1702 | BNX2X_DEV_INFO("Single MSI-X is not attainable rc %d\n", |
1703 | rc); | |
1704 | goto no_msix; | |
1705 | } | |
1706 | ||
1707 | BNX2X_DEV_INFO("Using single MSI-X vector\n"); | |
1708 | bp->flags |= USING_SINGLE_MSIX_FLAG; | |
1709 | ||
55c11941 MS |
1710 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
1711 | bp->num_ethernet_queues = 1; | |
1712 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; | |
30a5de77 | 1713 | } else if (rc < 0) { |
a5444b17 | 1714 | BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc); |
30a5de77 | 1715 | goto no_msix; |
a5444b17 AG |
1716 | } else if (rc < msix_vec) { |
1717 | /* how less vectors we will have? */ | |
1718 | int diff = msix_vec - rc; | |
1719 | ||
1720 | BNX2X_DEV_INFO("Trying to use less MSI-X vectors: %d\n", rc); | |
1721 | ||
1722 | /* | |
1723 | * decrease number of queues by number of unallocated entries | |
1724 | */ | |
1725 | bp->num_ethernet_queues -= diff; | |
1726 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; | |
1727 | ||
1728 | BNX2X_DEV_INFO("New queue configuration set: %d\n", | |
1729 | bp->num_queues); | |
9f6c9258 DK |
1730 | } |
1731 | ||
1732 | bp->flags |= USING_MSIX_FLAG; | |
1733 | ||
1734 | return 0; | |
30a5de77 DK |
1735 | |
1736 | no_msix: | |
1737 | /* fall to INTx if not enough memory */ | |
1738 | if (rc == -ENOMEM) | |
1739 | bp->flags |= DISABLE_MSI_FLAG; | |
1740 | ||
1741 | return rc; | |
9f6c9258 DK |
1742 | } |
1743 | ||
1744 | static int bnx2x_req_msix_irqs(struct bnx2x *bp) | |
1745 | { | |
ca92429f | 1746 | int i, rc, offset = 0; |
9f6c9258 | 1747 | |
ad5afc89 AE |
1748 | /* no default status block for vf */ |
1749 | if (IS_PF(bp)) { | |
1750 | rc = request_irq(bp->msix_table[offset++].vector, | |
1751 | bnx2x_msix_sp_int, 0, | |
1752 | bp->dev->name, bp->dev); | |
1753 | if (rc) { | |
1754 | BNX2X_ERR("request sp irq failed\n"); | |
1755 | return -EBUSY; | |
1756 | } | |
9f6c9258 DK |
1757 | } |
1758 | ||
55c11941 MS |
1759 | if (CNIC_SUPPORT(bp)) |
1760 | offset++; | |
1761 | ||
ec6ba945 | 1762 | for_each_eth_queue(bp, i) { |
9f6c9258 DK |
1763 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
1764 | snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", | |
1765 | bp->dev->name, i); | |
1766 | ||
d6214d7a | 1767 | rc = request_irq(bp->msix_table[offset].vector, |
9f6c9258 DK |
1768 | bnx2x_msix_fp_int, 0, fp->name, fp); |
1769 | if (rc) { | |
ca92429f DK |
1770 | BNX2X_ERR("request fp #%d irq (%d) failed rc %d\n", i, |
1771 | bp->msix_table[offset].vector, rc); | |
1772 | bnx2x_free_msix_irqs(bp, offset); | |
9f6c9258 DK |
1773 | return -EBUSY; |
1774 | } | |
1775 | ||
d6214d7a | 1776 | offset++; |
9f6c9258 DK |
1777 | } |
1778 | ||
ec6ba945 | 1779 | i = BNX2X_NUM_ETH_QUEUES(bp); |
ad5afc89 AE |
1780 | if (IS_PF(bp)) { |
1781 | offset = 1 + CNIC_SUPPORT(bp); | |
1782 | netdev_info(bp->dev, | |
1783 | "using MSI-X IRQs: sp %d fp[%d] %d ... fp[%d] %d\n", | |
1784 | bp->msix_table[0].vector, | |
1785 | 0, bp->msix_table[offset].vector, | |
1786 | i - 1, bp->msix_table[offset + i - 1].vector); | |
1787 | } else { | |
1788 | offset = CNIC_SUPPORT(bp); | |
1789 | netdev_info(bp->dev, | |
1790 | "using MSI-X IRQs: fp[%d] %d ... fp[%d] %d\n", | |
1791 | 0, bp->msix_table[offset].vector, | |
1792 | i - 1, bp->msix_table[offset + i - 1].vector); | |
1793 | } | |
9f6c9258 DK |
1794 | return 0; |
1795 | } | |
1796 | ||
d6214d7a | 1797 | int bnx2x_enable_msi(struct bnx2x *bp) |
9f6c9258 DK |
1798 | { |
1799 | int rc; | |
1800 | ||
1801 | rc = pci_enable_msi(bp->pdev); | |
1802 | if (rc) { | |
51c1a580 | 1803 | BNX2X_DEV_INFO("MSI is not attainable\n"); |
9f6c9258 DK |
1804 | return -1; |
1805 | } | |
1806 | bp->flags |= USING_MSI_FLAG; | |
1807 | ||
1808 | return 0; | |
1809 | } | |
1810 | ||
1811 | static int bnx2x_req_irq(struct bnx2x *bp) | |
1812 | { | |
1813 | unsigned long flags; | |
30a5de77 | 1814 | unsigned int irq; |
9f6c9258 | 1815 | |
30a5de77 | 1816 | if (bp->flags & (USING_MSI_FLAG | USING_MSIX_FLAG)) |
9f6c9258 DK |
1817 | flags = 0; |
1818 | else | |
1819 | flags = IRQF_SHARED; | |
1820 | ||
30a5de77 DK |
1821 | if (bp->flags & USING_MSIX_FLAG) |
1822 | irq = bp->msix_table[0].vector; | |
1823 | else | |
1824 | irq = bp->pdev->irq; | |
1825 | ||
1826 | return request_irq(irq, bnx2x_interrupt, flags, bp->dev->name, bp->dev); | |
9f6c9258 DK |
1827 | } |
1828 | ||
c957d09f | 1829 | static int bnx2x_setup_irqs(struct bnx2x *bp) |
619c5cb6 VZ |
1830 | { |
1831 | int rc = 0; | |
30a5de77 DK |
1832 | if (bp->flags & USING_MSIX_FLAG && |
1833 | !(bp->flags & USING_SINGLE_MSIX_FLAG)) { | |
619c5cb6 VZ |
1834 | rc = bnx2x_req_msix_irqs(bp); |
1835 | if (rc) | |
1836 | return rc; | |
1837 | } else { | |
619c5cb6 VZ |
1838 | rc = bnx2x_req_irq(bp); |
1839 | if (rc) { | |
1840 | BNX2X_ERR("IRQ request failed rc %d, aborting\n", rc); | |
1841 | return rc; | |
1842 | } | |
1843 | if (bp->flags & USING_MSI_FLAG) { | |
1844 | bp->dev->irq = bp->pdev->irq; | |
30a5de77 DK |
1845 | netdev_info(bp->dev, "using MSI IRQ %d\n", |
1846 | bp->dev->irq); | |
1847 | } | |
1848 | if (bp->flags & USING_MSIX_FLAG) { | |
1849 | bp->dev->irq = bp->msix_table[0].vector; | |
1850 | netdev_info(bp->dev, "using MSIX IRQ %d\n", | |
1851 | bp->dev->irq); | |
619c5cb6 VZ |
1852 | } |
1853 | } | |
1854 | ||
1855 | return 0; | |
1856 | } | |
1857 | ||
55c11941 MS |
1858 | static void bnx2x_napi_enable_cnic(struct bnx2x *bp) |
1859 | { | |
1860 | int i; | |
1861 | ||
8f20aa57 | 1862 | for_each_rx_queue_cnic(bp, i) { |
55c11941 | 1863 | napi_enable(&bnx2x_fp(bp, i, napi)); |
8f20aa57 | 1864 | } |
55c11941 MS |
1865 | } |
1866 | ||
1191cb83 | 1867 | static void bnx2x_napi_enable(struct bnx2x *bp) |
9f6c9258 DK |
1868 | { |
1869 | int i; | |
1870 | ||
8f20aa57 | 1871 | for_each_eth_queue(bp, i) { |
9f6c9258 | 1872 | napi_enable(&bnx2x_fp(bp, i, napi)); |
8f20aa57 | 1873 | } |
9f6c9258 DK |
1874 | } |
1875 | ||
55c11941 MS |
1876 | static void bnx2x_napi_disable_cnic(struct bnx2x *bp) |
1877 | { | |
1878 | int i; | |
1879 | ||
8f20aa57 | 1880 | for_each_rx_queue_cnic(bp, i) { |
55c11941 | 1881 | napi_disable(&bnx2x_fp(bp, i, napi)); |
8f20aa57 | 1882 | } |
55c11941 MS |
1883 | } |
1884 | ||
1191cb83 | 1885 | static void bnx2x_napi_disable(struct bnx2x *bp) |
9f6c9258 DK |
1886 | { |
1887 | int i; | |
1888 | ||
8f20aa57 | 1889 | for_each_eth_queue(bp, i) { |
9f6c9258 | 1890 | napi_disable(&bnx2x_fp(bp, i, napi)); |
8f20aa57 | 1891 | } |
9f6c9258 DK |
1892 | } |
1893 | ||
1894 | void bnx2x_netif_start(struct bnx2x *bp) | |
1895 | { | |
4b7ed897 DK |
1896 | if (netif_running(bp->dev)) { |
1897 | bnx2x_napi_enable(bp); | |
55c11941 MS |
1898 | if (CNIC_LOADED(bp)) |
1899 | bnx2x_napi_enable_cnic(bp); | |
4b7ed897 DK |
1900 | bnx2x_int_enable(bp); |
1901 | if (bp->state == BNX2X_STATE_OPEN) | |
1902 | netif_tx_wake_all_queues(bp->dev); | |
9f6c9258 DK |
1903 | } |
1904 | } | |
1905 | ||
1906 | void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw) | |
1907 | { | |
1908 | bnx2x_int_disable_sync(bp, disable_hw); | |
1909 | bnx2x_napi_disable(bp); | |
55c11941 MS |
1910 | if (CNIC_LOADED(bp)) |
1911 | bnx2x_napi_disable_cnic(bp); | |
9f6c9258 | 1912 | } |
9f6c9258 | 1913 | |
f663dd9a | 1914 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 1915 | void *accel_priv, select_queue_fallback_t fallback) |
8307fa3e | 1916 | { |
8307fa3e | 1917 | struct bnx2x *bp = netdev_priv(dev); |
cdb9d6ae | 1918 | |
55c11941 | 1919 | if (CNIC_LOADED(bp) && !NO_FCOE(bp)) { |
8307fa3e VZ |
1920 | struct ethhdr *hdr = (struct ethhdr *)skb->data; |
1921 | u16 ether_type = ntohs(hdr->h_proto); | |
1922 | ||
1923 | /* Skip VLAN tag if present */ | |
1924 | if (ether_type == ETH_P_8021Q) { | |
1925 | struct vlan_ethhdr *vhdr = | |
1926 | (struct vlan_ethhdr *)skb->data; | |
1927 | ||
1928 | ether_type = ntohs(vhdr->h_vlan_encapsulated_proto); | |
1929 | } | |
1930 | ||
1931 | /* If ethertype is FCoE or FIP - use FCoE ring */ | |
1932 | if ((ether_type == ETH_P_FCOE) || (ether_type == ETH_P_FIP)) | |
6383c0b3 | 1933 | return bnx2x_fcoe_tx(bp, txq_index); |
8307fa3e | 1934 | } |
55c11941 | 1935 | |
cdb9d6ae | 1936 | /* select a non-FCoE queue */ |
04bb36f3 | 1937 | return fallback(dev, skb) % (BNX2X_NUM_ETH_QUEUES(bp)); |
8307fa3e VZ |
1938 | } |
1939 | ||
d6214d7a DK |
1940 | void bnx2x_set_num_queues(struct bnx2x *bp) |
1941 | { | |
96305234 | 1942 | /* RSS queues */ |
55c11941 | 1943 | bp->num_ethernet_queues = bnx2x_calc_num_queues(bp); |
ec6ba945 | 1944 | |
a3348722 | 1945 | /* override in STORAGE SD modes */ |
2e98ffc2 | 1946 | if (IS_MF_STORAGE_ONLY(bp)) |
55c11941 MS |
1947 | bp->num_ethernet_queues = 1; |
1948 | ||
ec6ba945 | 1949 | /* Add special queues */ |
55c11941 MS |
1950 | bp->num_cnic_queues = CNIC_SUPPORT(bp); /* For FCOE */ |
1951 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; | |
65565884 MS |
1952 | |
1953 | BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); | |
ec6ba945 VZ |
1954 | } |
1955 | ||
cdb9d6ae VZ |
1956 | /** |
1957 | * bnx2x_set_real_num_queues - configure netdev->real_num_[tx,rx]_queues | |
1958 | * | |
1959 | * @bp: Driver handle | |
1960 | * | |
1961 | * We currently support for at most 16 Tx queues for each CoS thus we will | |
1962 | * allocate a multiple of 16 for ETH L2 rings according to the value of the | |
1963 | * bp->max_cos. | |
1964 | * | |
1965 | * If there is an FCoE L2 queue the appropriate Tx queue will have the next | |
1966 | * index after all ETH L2 indices. | |
1967 | * | |
1968 | * If the actual number of Tx queues (for each CoS) is less than 16 then there | |
1969 | * will be the holes at the end of each group of 16 ETh L2 indices (0..15, | |
16a5fd92 | 1970 | * 16..31,...) with indices that are not coupled with any real Tx queue. |
cdb9d6ae VZ |
1971 | * |
1972 | * The proper configuration of skb->queue_mapping is handled by | |
1973 | * bnx2x_select_queue() and __skb_tx_hash(). | |
1974 | * | |
1975 | * bnx2x_setup_tc() takes care of the proper TC mappings so that __skb_tx_hash() | |
1976 | * will return a proper Tx index if TC is enabled (netdev->num_tc > 0). | |
1977 | */ | |
55c11941 | 1978 | static int bnx2x_set_real_num_queues(struct bnx2x *bp, int include_cnic) |
ec6ba945 | 1979 | { |
6383c0b3 | 1980 | int rc, tx, rx; |
ec6ba945 | 1981 | |
65565884 | 1982 | tx = BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos; |
55c11941 | 1983 | rx = BNX2X_NUM_ETH_QUEUES(bp); |
ec6ba945 | 1984 | |
6383c0b3 | 1985 | /* account for fcoe queue */ |
55c11941 MS |
1986 | if (include_cnic && !NO_FCOE(bp)) { |
1987 | rx++; | |
1988 | tx++; | |
6383c0b3 | 1989 | } |
6383c0b3 AE |
1990 | |
1991 | rc = netif_set_real_num_tx_queues(bp->dev, tx); | |
1992 | if (rc) { | |
1993 | BNX2X_ERR("Failed to set real number of Tx queues: %d\n", rc); | |
1994 | return rc; | |
1995 | } | |
1996 | rc = netif_set_real_num_rx_queues(bp->dev, rx); | |
1997 | if (rc) { | |
1998 | BNX2X_ERR("Failed to set real number of Rx queues: %d\n", rc); | |
1999 | return rc; | |
2000 | } | |
2001 | ||
51c1a580 | 2002 | DP(NETIF_MSG_IFUP, "Setting real num queues to (tx, rx) (%d, %d)\n", |
6383c0b3 AE |
2003 | tx, rx); |
2004 | ||
ec6ba945 VZ |
2005 | return rc; |
2006 | } | |
2007 | ||
1191cb83 | 2008 | static void bnx2x_set_rx_buf_size(struct bnx2x *bp) |
a8c94b91 VZ |
2009 | { |
2010 | int i; | |
2011 | ||
2012 | for_each_queue(bp, i) { | |
2013 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
e52fcb24 | 2014 | u32 mtu; |
a8c94b91 VZ |
2015 | |
2016 | /* Always use a mini-jumbo MTU for the FCoE L2 ring */ | |
2017 | if (IS_FCOE_IDX(i)) | |
2018 | /* | |
2019 | * Although there are no IP frames expected to arrive to | |
2020 | * this ring we still want to add an | |
2021 | * IP_HEADER_ALIGNMENT_PADDING to prevent a buffer | |
2022 | * overrun attack. | |
2023 | */ | |
e52fcb24 | 2024 | mtu = BNX2X_FCOE_MINI_JUMBO_MTU; |
a8c94b91 | 2025 | else |
e52fcb24 ED |
2026 | mtu = bp->dev->mtu; |
2027 | fp->rx_buf_size = BNX2X_FW_RX_ALIGN_START + | |
2028 | IP_HEADER_ALIGNMENT_PADDING + | |
e1c6dcca | 2029 | ETH_OVERHEAD + |
e52fcb24 ED |
2030 | mtu + |
2031 | BNX2X_FW_RX_ALIGN_END; | |
9b70de6d | 2032 | fp->rx_buf_size = SKB_DATA_ALIGN(fp->rx_buf_size); |
16a5fd92 | 2033 | /* Note : rx_buf_size doesn't take into account NET_SKB_PAD */ |
d46d132c ED |
2034 | if (fp->rx_buf_size + NET_SKB_PAD <= PAGE_SIZE) |
2035 | fp->rx_frag_size = fp->rx_buf_size + NET_SKB_PAD; | |
2036 | else | |
2037 | fp->rx_frag_size = 0; | |
a8c94b91 VZ |
2038 | } |
2039 | } | |
2040 | ||
60cad4e6 | 2041 | static int bnx2x_init_rss(struct bnx2x *bp) |
619c5cb6 VZ |
2042 | { |
2043 | int i; | |
619c5cb6 VZ |
2044 | u8 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp); |
2045 | ||
16a5fd92 | 2046 | /* Prepare the initial contents for the indirection table if RSS is |
619c5cb6 VZ |
2047 | * enabled |
2048 | */ | |
5d317c6a MS |
2049 | for (i = 0; i < sizeof(bp->rss_conf_obj.ind_table); i++) |
2050 | bp->rss_conf_obj.ind_table[i] = | |
96305234 DK |
2051 | bp->fp->cl_id + |
2052 | ethtool_rxfh_indir_default(i, num_eth_queues); | |
619c5cb6 VZ |
2053 | |
2054 | /* | |
2055 | * For 57710 and 57711 SEARCHER configuration (rss_keys) is | |
2056 | * per-port, so if explicit configuration is needed , do it only | |
2057 | * for a PMF. | |
2058 | * | |
2059 | * For 57712 and newer on the other hand it's a per-function | |
2060 | * configuration. | |
2061 | */ | |
5d317c6a | 2062 | return bnx2x_config_rss_eth(bp, bp->port.pmf || !CHIP_IS_E1x(bp)); |
619c5cb6 VZ |
2063 | } |
2064 | ||
60cad4e6 AE |
2065 | int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, |
2066 | bool config_hash, bool enable) | |
619c5cb6 | 2067 | { |
3b603066 | 2068 | struct bnx2x_config_rss_params params = {NULL}; |
619c5cb6 VZ |
2069 | |
2070 | /* Although RSS is meaningless when there is a single HW queue we | |
2071 | * still need it enabled in order to have HW Rx hash generated. | |
2072 | * | |
2073 | * if (!is_eth_multi(bp)) | |
2074 | * bp->multi_mode = ETH_RSS_MODE_DISABLED; | |
2075 | */ | |
2076 | ||
96305234 | 2077 | params.rss_obj = rss_obj; |
619c5cb6 VZ |
2078 | |
2079 | __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); | |
2080 | ||
60cad4e6 AE |
2081 | if (enable) { |
2082 | __set_bit(BNX2X_RSS_MODE_REGULAR, ¶ms.rss_flags); | |
2083 | ||
2084 | /* RSS configuration */ | |
2085 | __set_bit(BNX2X_RSS_IPV4, ¶ms.rss_flags); | |
2086 | __set_bit(BNX2X_RSS_IPV4_TCP, ¶ms.rss_flags); | |
2087 | __set_bit(BNX2X_RSS_IPV6, ¶ms.rss_flags); | |
2088 | __set_bit(BNX2X_RSS_IPV6_TCP, ¶ms.rss_flags); | |
2089 | if (rss_obj->udp_rss_v4) | |
2090 | __set_bit(BNX2X_RSS_IPV4_UDP, ¶ms.rss_flags); | |
2091 | if (rss_obj->udp_rss_v6) | |
2092 | __set_bit(BNX2X_RSS_IPV6_UDP, ¶ms.rss_flags); | |
e42780b6 | 2093 | |
28311f8e YM |
2094 | if (!CHIP_IS_E1x(bp)) { |
2095 | /* valid only for TUNN_MODE_VXLAN tunnel mode */ | |
2096 | __set_bit(BNX2X_RSS_IPV4_VXLAN, ¶ms.rss_flags); | |
2097 | __set_bit(BNX2X_RSS_IPV6_VXLAN, ¶ms.rss_flags); | |
2098 | ||
e42780b6 | 2099 | /* valid only for TUNN_MODE_GRE tunnel mode */ |
28311f8e YM |
2100 | __set_bit(BNX2X_RSS_TUNN_INNER_HDRS, ¶ms.rss_flags); |
2101 | } | |
60cad4e6 AE |
2102 | } else { |
2103 | __set_bit(BNX2X_RSS_MODE_DISABLED, ¶ms.rss_flags); | |
2104 | } | |
619c5cb6 | 2105 | |
96305234 DK |
2106 | /* Hash bits */ |
2107 | params.rss_result_mask = MULTI_MASK; | |
619c5cb6 | 2108 | |
5d317c6a | 2109 | memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table)); |
619c5cb6 | 2110 | |
96305234 DK |
2111 | if (config_hash) { |
2112 | /* RSS keys */ | |
e3ec69ca | 2113 | netdev_rss_key_fill(params.rss_key, T_ETH_RSS_KEY * 4); |
96305234 | 2114 | __set_bit(BNX2X_RSS_SET_SRCH, ¶ms.rss_flags); |
619c5cb6 VZ |
2115 | } |
2116 | ||
60cad4e6 AE |
2117 | if (IS_PF(bp)) |
2118 | return bnx2x_config_rss(bp, ¶ms); | |
2119 | else | |
2120 | return bnx2x_vfpf_config_rss(bp, ¶ms); | |
619c5cb6 VZ |
2121 | } |
2122 | ||
1191cb83 | 2123 | static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code) |
619c5cb6 | 2124 | { |
3b603066 | 2125 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 VZ |
2126 | |
2127 | /* Prepare parameters for function state transitions */ | |
2128 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
2129 | ||
2130 | func_params.f_obj = &bp->func_obj; | |
2131 | func_params.cmd = BNX2X_F_CMD_HW_INIT; | |
2132 | ||
2133 | func_params.params.hw_init.load_phase = load_code; | |
2134 | ||
2135 | return bnx2x_func_state_change(bp, &func_params); | |
2136 | } | |
2137 | ||
2138 | /* | |
2139 | * Cleans the object that have internal lists without sending | |
16a5fd92 | 2140 | * ramrods. Should be run when interrupts are disabled. |
619c5cb6 | 2141 | */ |
7fa6f340 | 2142 | void bnx2x_squeeze_objects(struct bnx2x *bp) |
619c5cb6 VZ |
2143 | { |
2144 | int rc; | |
2145 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
3b603066 | 2146 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
15192a8c | 2147 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; |
619c5cb6 VZ |
2148 | |
2149 | /***************** Cleanup MACs' object first *************************/ | |
2150 | ||
2151 | /* Wait for completion of requested */ | |
2152 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
2153 | /* Perform a dry cleanup */ | |
2154 | __set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags); | |
2155 | ||
2156 | /* Clean ETH primary MAC */ | |
2157 | __set_bit(BNX2X_ETH_MAC, &vlan_mac_flags); | |
15192a8c | 2158 | rc = mac_obj->delete_all(bp, &bp->sp_objs->mac_obj, &vlan_mac_flags, |
619c5cb6 VZ |
2159 | &ramrod_flags); |
2160 | if (rc != 0) | |
2161 | BNX2X_ERR("Failed to clean ETH MACs: %d\n", rc); | |
2162 | ||
2163 | /* Cleanup UC list */ | |
2164 | vlan_mac_flags = 0; | |
2165 | __set_bit(BNX2X_UC_LIST_MAC, &vlan_mac_flags); | |
2166 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, | |
2167 | &ramrod_flags); | |
2168 | if (rc != 0) | |
2169 | BNX2X_ERR("Failed to clean UC list MACs: %d\n", rc); | |
2170 | ||
2171 | /***************** Now clean mcast object *****************************/ | |
2172 | rparam.mcast_obj = &bp->mcast_obj; | |
2173 | __set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags); | |
2174 | ||
8b09be5f YM |
2175 | /* Add a DEL command... - Since we're doing a driver cleanup only, |
2176 | * we take a lock surrounding both the initial send and the CONTs, | |
2177 | * as we don't want a true completion to disrupt us in the middle. | |
2178 | */ | |
2179 | netif_addr_lock_bh(bp->dev); | |
619c5cb6 VZ |
2180 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); |
2181 | if (rc < 0) | |
51c1a580 MS |
2182 | BNX2X_ERR("Failed to add a new DEL command to a multi-cast object: %d\n", |
2183 | rc); | |
619c5cb6 VZ |
2184 | |
2185 | /* ...and wait until all pending commands are cleared */ | |
2186 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
2187 | while (rc != 0) { | |
2188 | if (rc < 0) { | |
2189 | BNX2X_ERR("Failed to clean multi-cast object: %d\n", | |
2190 | rc); | |
8b09be5f | 2191 | netif_addr_unlock_bh(bp->dev); |
619c5cb6 VZ |
2192 | return; |
2193 | } | |
2194 | ||
2195 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
2196 | } | |
8b09be5f | 2197 | netif_addr_unlock_bh(bp->dev); |
619c5cb6 VZ |
2198 | } |
2199 | ||
2200 | #ifndef BNX2X_STOP_ON_ERROR | |
2201 | #define LOAD_ERROR_EXIT(bp, label) \ | |
2202 | do { \ | |
2203 | (bp)->state = BNX2X_STATE_ERROR; \ | |
2204 | goto label; \ | |
2205 | } while (0) | |
55c11941 MS |
2206 | |
2207 | #define LOAD_ERROR_EXIT_CNIC(bp, label) \ | |
2208 | do { \ | |
2209 | bp->cnic_loaded = false; \ | |
2210 | goto label; \ | |
2211 | } while (0) | |
2212 | #else /*BNX2X_STOP_ON_ERROR*/ | |
619c5cb6 VZ |
2213 | #define LOAD_ERROR_EXIT(bp, label) \ |
2214 | do { \ | |
2215 | (bp)->state = BNX2X_STATE_ERROR; \ | |
2216 | (bp)->panic = 1; \ | |
2217 | return -EBUSY; \ | |
2218 | } while (0) | |
55c11941 MS |
2219 | #define LOAD_ERROR_EXIT_CNIC(bp, label) \ |
2220 | do { \ | |
2221 | bp->cnic_loaded = false; \ | |
2222 | (bp)->panic = 1; \ | |
2223 | return -EBUSY; \ | |
2224 | } while (0) | |
2225 | #endif /*BNX2X_STOP_ON_ERROR*/ | |
619c5cb6 | 2226 | |
ad5afc89 AE |
2227 | static void bnx2x_free_fw_stats_mem(struct bnx2x *bp) |
2228 | { | |
2229 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, | |
2230 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
2231 | return; | |
2232 | } | |
2233 | ||
2234 | static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) | |
452427b0 | 2235 | { |
8db573ba | 2236 | int num_groups, vf_headroom = 0; |
ad5afc89 | 2237 | int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; |
452427b0 | 2238 | |
ad5afc89 AE |
2239 | /* number of queues for statistics is number of eth queues + FCoE */ |
2240 | u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; | |
452427b0 | 2241 | |
ad5afc89 AE |
2242 | /* Total number of FW statistics requests = |
2243 | * 1 for port stats + 1 for PF stats + potential 2 for FCoE (fcoe proper | |
2244 | * and fcoe l2 queue) stats + num of queues (which includes another 1 | |
2245 | * for fcoe l2 queue if applicable) | |
2246 | */ | |
2247 | bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; | |
452427b0 | 2248 | |
8db573ba AE |
2249 | /* vf stats appear in the request list, but their data is allocated by |
2250 | * the VFs themselves. We don't include them in the bp->fw_stats_num as | |
2251 | * it is used to determine where to place the vf stats queries in the | |
2252 | * request struct | |
2253 | */ | |
2254 | if (IS_SRIOV(bp)) | |
6411280a | 2255 | vf_headroom = bnx2x_vf_headroom(bp); |
8db573ba | 2256 | |
ad5afc89 AE |
2257 | /* Request is built from stats_query_header and an array of |
2258 | * stats_query_cmd_group each of which contains | |
2259 | * STATS_QUERY_CMD_COUNT rules. The real number or requests is | |
2260 | * configured in the stats_query_header. | |
2261 | */ | |
2262 | num_groups = | |
8db573ba AE |
2263 | (((bp->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT) + |
2264 | (((bp->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT) ? | |
ad5afc89 AE |
2265 | 1 : 0)); |
2266 | ||
8db573ba AE |
2267 | DP(BNX2X_MSG_SP, "stats fw_stats_num %d, vf headroom %d, num_groups %d\n", |
2268 | bp->fw_stats_num, vf_headroom, num_groups); | |
ad5afc89 AE |
2269 | bp->fw_stats_req_sz = sizeof(struct stats_query_header) + |
2270 | num_groups * sizeof(struct stats_query_cmd_group); | |
2271 | ||
2272 | /* Data for statistics requests + stats_counter | |
2273 | * stats_counter holds per-STORM counters that are incremented | |
2274 | * when STORM has finished with the current request. | |
2275 | * memory for FCoE offloaded statistics are counted anyway, | |
2276 | * even if they will not be sent. | |
2277 | * VF stats are not accounted for here as the data of VF stats is stored | |
2278 | * in memory allocated by the VF, not here. | |
2279 | */ | |
2280 | bp->fw_stats_data_sz = sizeof(struct per_port_stats) + | |
2281 | sizeof(struct per_pf_stats) + | |
2282 | sizeof(struct fcoe_statistics_params) + | |
2283 | sizeof(struct per_queue_stats) * num_queue_stats + | |
2284 | sizeof(struct stats_counter); | |
2285 | ||
cd2b0389 JP |
2286 | bp->fw_stats = BNX2X_PCI_ALLOC(&bp->fw_stats_mapping, |
2287 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
2288 | if (!bp->fw_stats) | |
2289 | goto alloc_mem_err; | |
ad5afc89 AE |
2290 | |
2291 | /* Set shortcuts */ | |
2292 | bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; | |
2293 | bp->fw_stats_req_mapping = bp->fw_stats_mapping; | |
2294 | bp->fw_stats_data = (struct bnx2x_fw_stats_data *) | |
2295 | ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); | |
2296 | bp->fw_stats_data_mapping = bp->fw_stats_mapping + | |
2297 | bp->fw_stats_req_sz; | |
2298 | ||
6bf07b8e | 2299 | DP(BNX2X_MSG_SP, "statistics request base address set to %x %x\n", |
ad5afc89 AE |
2300 | U64_HI(bp->fw_stats_req_mapping), |
2301 | U64_LO(bp->fw_stats_req_mapping)); | |
6bf07b8e | 2302 | DP(BNX2X_MSG_SP, "statistics data base address set to %x %x\n", |
ad5afc89 AE |
2303 | U64_HI(bp->fw_stats_data_mapping), |
2304 | U64_LO(bp->fw_stats_data_mapping)); | |
2305 | return 0; | |
2306 | ||
2307 | alloc_mem_err: | |
2308 | bnx2x_free_fw_stats_mem(bp); | |
2309 | BNX2X_ERR("Can't allocate FW stats memory\n"); | |
2310 | return -ENOMEM; | |
2311 | } | |
2312 | ||
2313 | /* send load request to mcp and analyze response */ | |
2314 | static int bnx2x_nic_load_request(struct bnx2x *bp, u32 *load_code) | |
2315 | { | |
178135c1 DK |
2316 | u32 param; |
2317 | ||
ad5afc89 AE |
2318 | /* init fw_seq */ |
2319 | bp->fw_seq = | |
2320 | (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
2321 | DRV_MSG_SEQ_NUMBER_MASK); | |
2322 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
2323 | ||
2324 | /* Get current FW pulse sequence */ | |
2325 | bp->fw_drv_pulse_wr_seq = | |
2326 | (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb) & | |
2327 | DRV_PULSE_SEQ_MASK); | |
2328 | BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); | |
2329 | ||
178135c1 DK |
2330 | param = DRV_MSG_CODE_LOAD_REQ_WITH_LFA; |
2331 | ||
2332 | if (IS_MF_SD(bp) && bnx2x_port_after_undi(bp)) | |
2333 | param |= DRV_MSG_CODE_LOAD_REQ_FORCE_LFA; | |
2334 | ||
ad5afc89 | 2335 | /* load request */ |
178135c1 | 2336 | (*load_code) = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, param); |
ad5afc89 AE |
2337 | |
2338 | /* if mcp fails to respond we must abort */ | |
2339 | if (!(*load_code)) { | |
2340 | BNX2X_ERR("MCP response failure, aborting\n"); | |
2341 | return -EBUSY; | |
2342 | } | |
2343 | ||
2344 | /* If mcp refused (e.g. other port is in diagnostic mode) we | |
2345 | * must abort | |
2346 | */ | |
2347 | if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) { | |
2348 | BNX2X_ERR("MCP refused load request, aborting\n"); | |
2349 | return -EBUSY; | |
2350 | } | |
2351 | return 0; | |
2352 | } | |
2353 | ||
2354 | /* check whether another PF has already loaded FW to chip. In | |
2355 | * virtualized environments a pf from another VM may have already | |
2356 | * initialized the device including loading FW | |
2357 | */ | |
91ebb929 | 2358 | int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err) |
ad5afc89 AE |
2359 | { |
2360 | /* is another pf loaded on this engine? */ | |
2361 | if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP && | |
2362 | load_code != FW_MSG_CODE_DRV_LOAD_COMMON) { | |
2363 | /* build my FW version dword */ | |
2364 | u32 my_fw = (BCM_5710_FW_MAJOR_VERSION) + | |
2365 | (BCM_5710_FW_MINOR_VERSION << 8) + | |
2366 | (BCM_5710_FW_REVISION_VERSION << 16) + | |
2367 | (BCM_5710_FW_ENGINEERING_VERSION << 24); | |
2368 | ||
2369 | /* read loaded FW from chip */ | |
2370 | u32 loaded_fw = REG_RD(bp, XSEM_REG_PRAM); | |
2371 | ||
2372 | DP(BNX2X_MSG_SP, "loaded fw %x, my fw %x\n", | |
2373 | loaded_fw, my_fw); | |
2374 | ||
2375 | /* abort nic load if version mismatch */ | |
2376 | if (my_fw != loaded_fw) { | |
91ebb929 YM |
2377 | if (print_err) |
2378 | BNX2X_ERR("bnx2x with FW %x was already loaded which mismatches my %x FW. Aborting\n", | |
2379 | loaded_fw, my_fw); | |
2380 | else | |
2381 | BNX2X_DEV_INFO("bnx2x with FW %x was already loaded which mismatches my %x FW, possibly due to MF UNDI\n", | |
2382 | loaded_fw, my_fw); | |
ad5afc89 AE |
2383 | return -EBUSY; |
2384 | } | |
2385 | } | |
2386 | return 0; | |
2387 | } | |
2388 | ||
2389 | /* returns the "mcp load_code" according to global load_count array */ | |
2390 | static int bnx2x_nic_load_no_mcp(struct bnx2x *bp, int port) | |
2391 | { | |
2392 | int path = BP_PATH(bp); | |
2393 | ||
2394 | DP(NETIF_MSG_IFUP, "NO MCP - load counts[%d] %d, %d, %d\n", | |
a8f47eb7 | 2395 | path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], |
2396 | bnx2x_load_count[path][2]); | |
2397 | bnx2x_load_count[path][0]++; | |
2398 | bnx2x_load_count[path][1 + port]++; | |
ad5afc89 | 2399 | DP(NETIF_MSG_IFUP, "NO MCP - new load counts[%d] %d, %d, %d\n", |
a8f47eb7 | 2400 | path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], |
2401 | bnx2x_load_count[path][2]); | |
2402 | if (bnx2x_load_count[path][0] == 1) | |
ad5afc89 | 2403 | return FW_MSG_CODE_DRV_LOAD_COMMON; |
a8f47eb7 | 2404 | else if (bnx2x_load_count[path][1 + port] == 1) |
ad5afc89 AE |
2405 | return FW_MSG_CODE_DRV_LOAD_PORT; |
2406 | else | |
2407 | return FW_MSG_CODE_DRV_LOAD_FUNCTION; | |
2408 | } | |
2409 | ||
2410 | /* mark PMF if applicable */ | |
2411 | static void bnx2x_nic_load_pmf(struct bnx2x *bp, u32 load_code) | |
2412 | { | |
2413 | if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) || | |
2414 | (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) || | |
2415 | (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) { | |
2416 | bp->port.pmf = 1; | |
2417 | /* We need the barrier to ensure the ordering between the | |
2418 | * writing to bp->port.pmf here and reading it from the | |
2419 | * bnx2x_periodic_task(). | |
2420 | */ | |
2421 | smp_mb(); | |
2422 | } else { | |
2423 | bp->port.pmf = 0; | |
452427b0 YM |
2424 | } |
2425 | ||
ad5afc89 AE |
2426 | DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); |
2427 | } | |
2428 | ||
2429 | static void bnx2x_nic_load_afex_dcc(struct bnx2x *bp, int load_code) | |
2430 | { | |
2431 | if (((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) || | |
2432 | (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP)) && | |
2433 | (bp->common.shmem2_base)) { | |
2434 | if (SHMEM2_HAS(bp, dcc_support)) | |
2435 | SHMEM2_WR(bp, dcc_support, | |
2436 | (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV | | |
2437 | SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV)); | |
2438 | if (SHMEM2_HAS(bp, afex_driver_support)) | |
2439 | SHMEM2_WR(bp, afex_driver_support, | |
2440 | SHMEM_AFEX_SUPPORTED_VERSION_ONE); | |
2441 | } | |
2442 | ||
2443 | /* Set AFEX default VLAN tag to an invalid value */ | |
2444 | bp->afex_def_vlan_tag = -1; | |
452427b0 YM |
2445 | } |
2446 | ||
1191cb83 ED |
2447 | /** |
2448 | * bnx2x_bz_fp - zero content of the fastpath structure. | |
2449 | * | |
2450 | * @bp: driver handle | |
2451 | * @index: fastpath index to be zeroed | |
2452 | * | |
2453 | * Makes sure the contents of the bp->fp[index].napi is kept | |
2454 | * intact. | |
2455 | */ | |
2456 | static void bnx2x_bz_fp(struct bnx2x *bp, int index) | |
2457 | { | |
2458 | struct bnx2x_fastpath *fp = &bp->fp[index]; | |
65565884 | 2459 | int cos; |
1191cb83 | 2460 | struct napi_struct orig_napi = fp->napi; |
15192a8c | 2461 | struct bnx2x_agg_info *orig_tpa_info = fp->tpa_info; |
d76a6111 | 2462 | |
1191cb83 | 2463 | /* bzero bnx2x_fastpath contents */ |
c3146eb6 DK |
2464 | if (fp->tpa_info) |
2465 | memset(fp->tpa_info, 0, ETH_MAX_AGGREGATION_QUEUES_E1H_E2 * | |
2466 | sizeof(struct bnx2x_agg_info)); | |
2467 | memset(fp, 0, sizeof(*fp)); | |
1191cb83 ED |
2468 | |
2469 | /* Restore the NAPI object as it has been already initialized */ | |
2470 | fp->napi = orig_napi; | |
15192a8c | 2471 | fp->tpa_info = orig_tpa_info; |
1191cb83 ED |
2472 | fp->bp = bp; |
2473 | fp->index = index; | |
2474 | if (IS_ETH_FP(fp)) | |
2475 | fp->max_cos = bp->max_cos; | |
2476 | else | |
2477 | /* Special queues support only one CoS */ | |
2478 | fp->max_cos = 1; | |
2479 | ||
65565884 | 2480 | /* Init txdata pointers */ |
65565884 MS |
2481 | if (IS_FCOE_FP(fp)) |
2482 | fp->txdata_ptr[0] = &bp->bnx2x_txq[FCOE_TXQ_IDX(bp)]; | |
65565884 MS |
2483 | if (IS_ETH_FP(fp)) |
2484 | for_each_cos_in_tx_queue(fp, cos) | |
2485 | fp->txdata_ptr[cos] = &bp->bnx2x_txq[cos * | |
2486 | BNX2X_NUM_ETH_QUEUES(bp) + index]; | |
2487 | ||
16a5fd92 | 2488 | /* set the tpa flag for each queue. The tpa flag determines the queue |
1191cb83 ED |
2489 | * minimal size so it must be set prior to queue memory allocation |
2490 | */ | |
f8dcb5e3 | 2491 | if (bp->dev->features & NETIF_F_LRO) |
1191cb83 | 2492 | fp->mode = TPA_MODE_LRO; |
f8dcb5e3 | 2493 | else if (bp->dev->features & NETIF_F_GRO && |
7e6b4d44 | 2494 | bnx2x_mtu_allows_gro(bp->dev->mtu)) |
1191cb83 | 2495 | fp->mode = TPA_MODE_GRO; |
7e6b4d44 MS |
2496 | else |
2497 | fp->mode = TPA_MODE_DISABLED; | |
1191cb83 | 2498 | |
22a8f237 MS |
2499 | /* We don't want TPA if it's disabled in bp |
2500 | * or if this is an FCoE L2 ring. | |
2501 | */ | |
2502 | if (bp->disable_tpa || IS_FCOE_FP(fp)) | |
7e6b4d44 | 2503 | fp->mode = TPA_MODE_DISABLED; |
55c11941 MS |
2504 | } |
2505 | ||
230d00eb YM |
2506 | void bnx2x_set_os_driver_state(struct bnx2x *bp, u32 state) |
2507 | { | |
2508 | u32 cur; | |
2509 | ||
2510 | if (!IS_MF_BD(bp) || !SHMEM2_HAS(bp, os_driver_state) || IS_VF(bp)) | |
2511 | return; | |
2512 | ||
2513 | cur = SHMEM2_RD(bp, os_driver_state[BP_FW_MB_IDX(bp)]); | |
2514 | DP(NETIF_MSG_IFUP, "Driver state %08x-->%08x\n", | |
2515 | cur, state); | |
2516 | ||
2517 | SHMEM2_WR(bp, os_driver_state[BP_FW_MB_IDX(bp)], state); | |
2518 | } | |
2519 | ||
55c11941 MS |
2520 | int bnx2x_load_cnic(struct bnx2x *bp) |
2521 | { | |
2522 | int i, rc, port = BP_PORT(bp); | |
2523 | ||
2524 | DP(NETIF_MSG_IFUP, "Starting CNIC-related load\n"); | |
2525 | ||
2526 | mutex_init(&bp->cnic_mutex); | |
2527 | ||
ad5afc89 AE |
2528 | if (IS_PF(bp)) { |
2529 | rc = bnx2x_alloc_mem_cnic(bp); | |
2530 | if (rc) { | |
2531 | BNX2X_ERR("Unable to allocate bp memory for cnic\n"); | |
2532 | LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0); | |
2533 | } | |
55c11941 MS |
2534 | } |
2535 | ||
2536 | rc = bnx2x_alloc_fp_mem_cnic(bp); | |
2537 | if (rc) { | |
2538 | BNX2X_ERR("Unable to allocate memory for cnic fps\n"); | |
2539 | LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0); | |
2540 | } | |
2541 | ||
2542 | /* Update the number of queues with the cnic queues */ | |
2543 | rc = bnx2x_set_real_num_queues(bp, 1); | |
2544 | if (rc) { | |
2545 | BNX2X_ERR("Unable to set real_num_queues including cnic\n"); | |
2546 | LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0); | |
2547 | } | |
2548 | ||
2549 | /* Add all CNIC NAPI objects */ | |
2550 | bnx2x_add_all_napi_cnic(bp); | |
2551 | DP(NETIF_MSG_IFUP, "cnic napi added\n"); | |
2552 | bnx2x_napi_enable_cnic(bp); | |
2553 | ||
2554 | rc = bnx2x_init_hw_func_cnic(bp); | |
2555 | if (rc) | |
2556 | LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic1); | |
2557 | ||
2558 | bnx2x_nic_init_cnic(bp); | |
2559 | ||
ad5afc89 AE |
2560 | if (IS_PF(bp)) { |
2561 | /* Enable Timer scan */ | |
2562 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1); | |
2563 | ||
2564 | /* setup cnic queues */ | |
2565 | for_each_cnic_queue(bp, i) { | |
2566 | rc = bnx2x_setup_queue(bp, &bp->fp[i], 0); | |
2567 | if (rc) { | |
2568 | BNX2X_ERR("Queue setup failed\n"); | |
2569 | LOAD_ERROR_EXIT(bp, load_error_cnic2); | |
2570 | } | |
55c11941 MS |
2571 | } |
2572 | } | |
2573 | ||
2574 | /* Initialize Rx filter. */ | |
8b09be5f | 2575 | bnx2x_set_rx_mode_inner(bp); |
55c11941 MS |
2576 | |
2577 | /* re-read iscsi info */ | |
2578 | bnx2x_get_iscsi_info(bp); | |
2579 | bnx2x_setup_cnic_irq_info(bp); | |
2580 | bnx2x_setup_cnic_info(bp); | |
2581 | bp->cnic_loaded = true; | |
2582 | if (bp->state == BNX2X_STATE_OPEN) | |
2583 | bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD); | |
2584 | ||
55c11941 MS |
2585 | DP(NETIF_MSG_IFUP, "Ending successfully CNIC-related load\n"); |
2586 | ||
2587 | return 0; | |
2588 | ||
2589 | #ifndef BNX2X_STOP_ON_ERROR | |
2590 | load_error_cnic2: | |
2591 | /* Disable Timer scan */ | |
2592 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
2593 | ||
2594 | load_error_cnic1: | |
2595 | bnx2x_napi_disable_cnic(bp); | |
2596 | /* Update the number of queues without the cnic queues */ | |
d9d81862 | 2597 | if (bnx2x_set_real_num_queues(bp, 0)) |
55c11941 MS |
2598 | BNX2X_ERR("Unable to set real_num_queues not including cnic\n"); |
2599 | load_error_cnic0: | |
2600 | BNX2X_ERR("CNIC-related load failed\n"); | |
2601 | bnx2x_free_fp_mem_cnic(bp); | |
2602 | bnx2x_free_mem_cnic(bp); | |
2603 | return rc; | |
2604 | #endif /* ! BNX2X_STOP_ON_ERROR */ | |
1191cb83 ED |
2605 | } |
2606 | ||
9f6c9258 DK |
2607 | /* must be called with rtnl_lock */ |
2608 | int bnx2x_nic_load(struct bnx2x *bp, int load_mode) | |
2609 | { | |
619c5cb6 | 2610 | int port = BP_PORT(bp); |
ad5afc89 | 2611 | int i, rc = 0, load_code = 0; |
9f6c9258 | 2612 | |
55c11941 MS |
2613 | DP(NETIF_MSG_IFUP, "Starting NIC load\n"); |
2614 | DP(NETIF_MSG_IFUP, | |
2615 | "CNIC is %s\n", CNIC_ENABLED(bp) ? "enabled" : "disabled"); | |
2616 | ||
9f6c9258 | 2617 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
2618 | if (unlikely(bp->panic)) { |
2619 | BNX2X_ERR("Can't load NIC when there is panic\n"); | |
9f6c9258 | 2620 | return -EPERM; |
51c1a580 | 2621 | } |
9f6c9258 DK |
2622 | #endif |
2623 | ||
2624 | bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD; | |
2625 | ||
16a5fd92 | 2626 | /* zero the structure w/o any lock, before SP handler is initialized */ |
2ae17f66 VZ |
2627 | memset(&bp->last_reported_link, 0, sizeof(bp->last_reported_link)); |
2628 | __set_bit(BNX2X_LINK_REPORT_LINK_DOWN, | |
2629 | &bp->last_reported_link.link_report_flags); | |
2ae17f66 | 2630 | |
ad5afc89 AE |
2631 | if (IS_PF(bp)) |
2632 | /* must be called before memory allocation and HW init */ | |
2633 | bnx2x_ilt_set_info(bp); | |
523224a3 | 2634 | |
6383c0b3 AE |
2635 | /* |
2636 | * Zero fastpath structures preserving invariants like napi, which are | |
2637 | * allocated only once, fp index, max_cos, bp pointer. | |
7e6b4d44 | 2638 | * Also set fp->mode and txdata_ptr. |
b3b83c3f | 2639 | */ |
51c1a580 | 2640 | DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues); |
b3b83c3f DK |
2641 | for_each_queue(bp, i) |
2642 | bnx2x_bz_fp(bp, i); | |
55c11941 MS |
2643 | memset(bp->bnx2x_txq, 0, (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS + |
2644 | bp->num_cnic_queues) * | |
2645 | sizeof(struct bnx2x_fp_txdata)); | |
b3b83c3f | 2646 | |
55c11941 | 2647 | bp->fcoe_init = false; |
6383c0b3 | 2648 | |
a8c94b91 VZ |
2649 | /* Set the receive queues buffer size */ |
2650 | bnx2x_set_rx_buf_size(bp); | |
2651 | ||
ad5afc89 AE |
2652 | if (IS_PF(bp)) { |
2653 | rc = bnx2x_alloc_mem(bp); | |
2654 | if (rc) { | |
2655 | BNX2X_ERR("Unable to allocate bp memory\n"); | |
2656 | return rc; | |
2657 | } | |
2658 | } | |
2659 | ||
ad5afc89 AE |
2660 | /* need to be done after alloc mem, since it's self adjusting to amount |
2661 | * of memory available for RSS queues | |
2662 | */ | |
2663 | rc = bnx2x_alloc_fp_mem(bp); | |
2664 | if (rc) { | |
2665 | BNX2X_ERR("Unable to allocate memory for fps\n"); | |
2666 | LOAD_ERROR_EXIT(bp, load_error0); | |
2667 | } | |
d6214d7a | 2668 | |
e3ed4eae DK |
2669 | /* Allocated memory for FW statistics */ |
2670 | if (bnx2x_alloc_fw_stats_mem(bp)) | |
2671 | LOAD_ERROR_EXIT(bp, load_error0); | |
2672 | ||
8d9ac297 AE |
2673 | /* request pf to initialize status blocks */ |
2674 | if (IS_VF(bp)) { | |
2675 | rc = bnx2x_vfpf_init(bp); | |
2676 | if (rc) | |
2677 | LOAD_ERROR_EXIT(bp, load_error0); | |
2678 | } | |
2679 | ||
b3b83c3f DK |
2680 | /* As long as bnx2x_alloc_mem() may possibly update |
2681 | * bp->num_queues, bnx2x_set_real_num_queues() should always | |
55c11941 | 2682 | * come after it. At this stage cnic queues are not counted. |
b3b83c3f | 2683 | */ |
55c11941 | 2684 | rc = bnx2x_set_real_num_queues(bp, 0); |
d6214d7a | 2685 | if (rc) { |
ec6ba945 | 2686 | BNX2X_ERR("Unable to set real_num_queues\n"); |
619c5cb6 | 2687 | LOAD_ERROR_EXIT(bp, load_error0); |
9f6c9258 DK |
2688 | } |
2689 | ||
6383c0b3 | 2690 | /* configure multi cos mappings in kernel. |
16a5fd92 YM |
2691 | * this configuration may be overridden by a multi class queue |
2692 | * discipline or by a dcbx negotiation result. | |
6383c0b3 AE |
2693 | */ |
2694 | bnx2x_setup_tc(bp->dev, bp->max_cos); | |
2695 | ||
26614ba5 MS |
2696 | /* Add all NAPI objects */ |
2697 | bnx2x_add_all_napi(bp); | |
55c11941 | 2698 | DP(NETIF_MSG_IFUP, "napi added\n"); |
9f6c9258 DK |
2699 | bnx2x_napi_enable(bp); |
2700 | ||
ad5afc89 AE |
2701 | if (IS_PF(bp)) { |
2702 | /* set pf load just before approaching the MCP */ | |
2703 | bnx2x_set_pf_load(bp); | |
2704 | ||
2705 | /* if mcp exists send load request and analyze response */ | |
2706 | if (!BP_NOMCP(bp)) { | |
2707 | /* attempt to load pf */ | |
2708 | rc = bnx2x_nic_load_request(bp, &load_code); | |
2709 | if (rc) | |
2710 | LOAD_ERROR_EXIT(bp, load_error1); | |
2711 | ||
2712 | /* what did mcp say? */ | |
91ebb929 | 2713 | rc = bnx2x_compare_fw_ver(bp, load_code, true); |
ad5afc89 AE |
2714 | if (rc) { |
2715 | bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
d1e2d966 AE |
2716 | LOAD_ERROR_EXIT(bp, load_error2); |
2717 | } | |
ad5afc89 AE |
2718 | } else { |
2719 | load_code = bnx2x_nic_load_no_mcp(bp, port); | |
d1e2d966 | 2720 | } |
9f6c9258 | 2721 | |
ad5afc89 AE |
2722 | /* mark pmf if applicable */ |
2723 | bnx2x_nic_load_pmf(bp, load_code); | |
9f6c9258 | 2724 | |
ad5afc89 AE |
2725 | /* Init Function state controlling object */ |
2726 | bnx2x__init_func_obj(bp); | |
6383c0b3 | 2727 | |
ad5afc89 AE |
2728 | /* Initialize HW */ |
2729 | rc = bnx2x_init_hw(bp, load_code); | |
2730 | if (rc) { | |
2731 | BNX2X_ERR("HW init failed, aborting\n"); | |
2732 | bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
2733 | LOAD_ERROR_EXIT(bp, load_error2); | |
2734 | } | |
9f6c9258 DK |
2735 | } |
2736 | ||
ecf01c22 YM |
2737 | bnx2x_pre_irq_nic_init(bp); |
2738 | ||
d6214d7a DK |
2739 | /* Connect to IRQs */ |
2740 | rc = bnx2x_setup_irqs(bp); | |
523224a3 | 2741 | if (rc) { |
ad5afc89 AE |
2742 | BNX2X_ERR("setup irqs failed\n"); |
2743 | if (IS_PF(bp)) | |
2744 | bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
619c5cb6 | 2745 | LOAD_ERROR_EXIT(bp, load_error2); |
523224a3 DK |
2746 | } |
2747 | ||
619c5cb6 | 2748 | /* Init per-function objects */ |
ad5afc89 | 2749 | if (IS_PF(bp)) { |
ecf01c22 YM |
2750 | /* Setup NIC internals and enable interrupts */ |
2751 | bnx2x_post_irq_nic_init(bp, load_code); | |
2752 | ||
ad5afc89 | 2753 | bnx2x_init_bp_objs(bp); |
b56e9670 | 2754 | bnx2x_iov_nic_init(bp); |
a3348722 | 2755 | |
ad5afc89 AE |
2756 | /* Set AFEX default VLAN tag to an invalid value */ |
2757 | bp->afex_def_vlan_tag = -1; | |
2758 | bnx2x_nic_load_afex_dcc(bp, load_code); | |
2759 | bp->state = BNX2X_STATE_OPENING_WAIT4_PORT; | |
2760 | rc = bnx2x_func_start(bp); | |
2761 | if (rc) { | |
2762 | BNX2X_ERR("Function start failed!\n"); | |
2763 | bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
9f6c9258 | 2764 | |
619c5cb6 | 2765 | LOAD_ERROR_EXIT(bp, load_error3); |
9f6c9258 | 2766 | } |
9f6c9258 | 2767 | |
ad5afc89 AE |
2768 | /* Send LOAD_DONE command to MCP */ |
2769 | if (!BP_NOMCP(bp)) { | |
2770 | load_code = bnx2x_fw_command(bp, | |
2771 | DRV_MSG_CODE_LOAD_DONE, 0); | |
2772 | if (!load_code) { | |
2773 | BNX2X_ERR("MCP response failure, aborting\n"); | |
2774 | rc = -EBUSY; | |
2775 | LOAD_ERROR_EXIT(bp, load_error3); | |
2776 | } | |
2777 | } | |
9f6c9258 | 2778 | |
0c14e5ce AE |
2779 | /* initialize FW coalescing state machines in RAM */ |
2780 | bnx2x_update_coalesce(bp); | |
60cad4e6 | 2781 | } |
0c14e5ce | 2782 | |
60cad4e6 AE |
2783 | /* setup the leading queue */ |
2784 | rc = bnx2x_setup_leading(bp); | |
2785 | if (rc) { | |
2786 | BNX2X_ERR("Setup leading failed!\n"); | |
2787 | LOAD_ERROR_EXIT(bp, load_error3); | |
2788 | } | |
ad5afc89 | 2789 | |
60cad4e6 AE |
2790 | /* set up the rest of the queues */ |
2791 | for_each_nondefault_eth_queue(bp, i) { | |
2792 | if (IS_PF(bp)) | |
2793 | rc = bnx2x_setup_queue(bp, &bp->fp[i], false); | |
2794 | else /* VF */ | |
2795 | rc = bnx2x_vfpf_setup_q(bp, &bp->fp[i], false); | |
ad5afc89 | 2796 | if (rc) { |
60cad4e6 | 2797 | BNX2X_ERR("Queue %d setup failed\n", i); |
ad5afc89 AE |
2798 | LOAD_ERROR_EXIT(bp, load_error3); |
2799 | } | |
60cad4e6 | 2800 | } |
8d9ac297 | 2801 | |
60cad4e6 AE |
2802 | /* setup rss */ |
2803 | rc = bnx2x_init_rss(bp); | |
2804 | if (rc) { | |
2805 | BNX2X_ERR("PF RSS init failed\n"); | |
2806 | LOAD_ERROR_EXIT(bp, load_error3); | |
51c1a580 | 2807 | } |
619c5cb6 | 2808 | |
523224a3 DK |
2809 | /* Now when Clients are configured we are ready to work */ |
2810 | bp->state = BNX2X_STATE_OPEN; | |
2811 | ||
619c5cb6 | 2812 | /* Configure a ucast MAC */ |
ad5afc89 AE |
2813 | if (IS_PF(bp)) |
2814 | rc = bnx2x_set_eth_mac(bp, true); | |
8d9ac297 | 2815 | else /* vf */ |
f8f4f61a DK |
2816 | rc = bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, bp->fp->index, |
2817 | true); | |
51c1a580 MS |
2818 | if (rc) { |
2819 | BNX2X_ERR("Setting Ethernet MAC failed\n"); | |
55c11941 | 2820 | LOAD_ERROR_EXIT(bp, load_error3); |
51c1a580 | 2821 | } |
6e30dd4e | 2822 | |
ad5afc89 | 2823 | if (IS_PF(bp) && bp->pending_max) { |
e3835b99 DK |
2824 | bnx2x_update_max_mf_config(bp, bp->pending_max); |
2825 | bp->pending_max = 0; | |
2826 | } | |
2827 | ||
6a9f0ecb | 2828 | bp->force_link_down = false; |
ad5afc89 AE |
2829 | if (bp->port.pmf) { |
2830 | rc = bnx2x_initial_phy_init(bp, load_mode); | |
2831 | if (rc) | |
2832 | LOAD_ERROR_EXIT(bp, load_error3); | |
2833 | } | |
c63da990 | 2834 | bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_BOOT_FROM_SAN; |
9f6c9258 | 2835 | |
619c5cb6 VZ |
2836 | /* Start fast path */ |
2837 | ||
05cc5a39 YM |
2838 | /* Re-configure vlan filters */ |
2839 | rc = bnx2x_vlan_reconfigure_vid(bp); | |
2840 | if (rc) | |
2841 | LOAD_ERROR_EXIT(bp, load_error3); | |
2842 | ||
619c5cb6 | 2843 | /* Initialize Rx filter. */ |
8b09be5f | 2844 | bnx2x_set_rx_mode_inner(bp); |
6e30dd4e | 2845 | |
eeed018c MK |
2846 | if (bp->flags & PTP_SUPPORTED) { |
2847 | bnx2x_init_ptp(bp); | |
2848 | bnx2x_configure_ptp_filters(bp); | |
2849 | } | |
2850 | /* Start Tx */ | |
9f6c9258 DK |
2851 | switch (load_mode) { |
2852 | case LOAD_NORMAL: | |
16a5fd92 | 2853 | /* Tx queue should be only re-enabled */ |
523224a3 | 2854 | netif_tx_wake_all_queues(bp->dev); |
9f6c9258 DK |
2855 | break; |
2856 | ||
2857 | case LOAD_OPEN: | |
2858 | netif_tx_start_all_queues(bp->dev); | |
4e857c58 | 2859 | smp_mb__after_atomic(); |
9f6c9258 DK |
2860 | break; |
2861 | ||
2862 | case LOAD_DIAG: | |
8970b2e4 | 2863 | case LOAD_LOOPBACK_EXT: |
9f6c9258 DK |
2864 | bp->state = BNX2X_STATE_DIAG; |
2865 | break; | |
2866 | ||
2867 | default: | |
2868 | break; | |
2869 | } | |
2870 | ||
00253a8c | 2871 | if (bp->port.pmf) |
4c704899 | 2872 | bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_PORT_MASK, 0); |
00253a8c | 2873 | else |
9f6c9258 DK |
2874 | bnx2x__link_status_update(bp); |
2875 | ||
2876 | /* start the timer */ | |
2877 | mod_timer(&bp->timer, jiffies + bp->current_interval); | |
2878 | ||
55c11941 MS |
2879 | if (CNIC_ENABLED(bp)) |
2880 | bnx2x_load_cnic(bp); | |
9f6c9258 | 2881 | |
42f8277f YM |
2882 | if (IS_PF(bp)) |
2883 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); | |
2884 | ||
ad5afc89 AE |
2885 | if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { |
2886 | /* mark driver is loaded in shmem2 */ | |
9ce392d4 YM |
2887 | u32 val; |
2888 | val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]); | |
230d00eb YM |
2889 | val &= ~DRV_FLAGS_MTU_MASK; |
2890 | val |= (bp->dev->mtu << DRV_FLAGS_MTU_SHIFT); | |
9ce392d4 YM |
2891 | SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], |
2892 | val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED | | |
2893 | DRV_FLAGS_CAPABILITIES_LOADED_L2); | |
2894 | } | |
2895 | ||
619c5cb6 | 2896 | /* Wait for all pending SP commands to complete */ |
ad5afc89 | 2897 | if (IS_PF(bp) && !bnx2x_wait_sp_comp(bp, ~0x0UL)) { |
619c5cb6 | 2898 | BNX2X_ERR("Timeout waiting for SP elements to complete\n"); |
5d07d868 | 2899 | bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); |
619c5cb6 VZ |
2900 | return -EBUSY; |
2901 | } | |
6891dd25 | 2902 | |
c48f350f YM |
2903 | /* Update driver data for On-Chip MFW dump. */ |
2904 | if (IS_PF(bp)) | |
2905 | bnx2x_update_mfw_dump(bp); | |
2906 | ||
9876879f BW |
2907 | /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */ |
2908 | if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG)) | |
2909 | bnx2x_dcbx_init(bp, false); | |
2910 | ||
230d00eb YM |
2911 | if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) |
2912 | bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_ACTIVE); | |
2913 | ||
55c11941 MS |
2914 | DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n"); |
2915 | ||
9f6c9258 DK |
2916 | return 0; |
2917 | ||
619c5cb6 | 2918 | #ifndef BNX2X_STOP_ON_ERROR |
9f6c9258 | 2919 | load_error3: |
ad5afc89 AE |
2920 | if (IS_PF(bp)) { |
2921 | bnx2x_int_disable_sync(bp, 1); | |
d6214d7a | 2922 | |
ad5afc89 AE |
2923 | /* Clean queueable objects */ |
2924 | bnx2x_squeeze_objects(bp); | |
2925 | } | |
619c5cb6 | 2926 | |
9f6c9258 DK |
2927 | /* Free SKBs, SGEs, TPA pool and driver internals */ |
2928 | bnx2x_free_skbs(bp); | |
ec6ba945 | 2929 | for_each_rx_queue(bp, i) |
9f6c9258 | 2930 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); |
d6214d7a | 2931 | |
9f6c9258 | 2932 | /* Release IRQs */ |
d6214d7a DK |
2933 | bnx2x_free_irq(bp); |
2934 | load_error2: | |
ad5afc89 | 2935 | if (IS_PF(bp) && !BP_NOMCP(bp)) { |
d6214d7a DK |
2936 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); |
2937 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
2938 | } | |
2939 | ||
2940 | bp->port.pmf = 0; | |
9f6c9258 DK |
2941 | load_error1: |
2942 | bnx2x_napi_disable(bp); | |
722c6f58 | 2943 | bnx2x_del_all_napi(bp); |
ad5afc89 | 2944 | |
889b9af3 | 2945 | /* clear pf_load status, as it was already set */ |
ad5afc89 AE |
2946 | if (IS_PF(bp)) |
2947 | bnx2x_clear_pf_load(bp); | |
d6214d7a | 2948 | load_error0: |
ad5afc89 | 2949 | bnx2x_free_fw_stats_mem(bp); |
e3ed4eae | 2950 | bnx2x_free_fp_mem(bp); |
9f6c9258 DK |
2951 | bnx2x_free_mem(bp); |
2952 | ||
2953 | return rc; | |
619c5cb6 | 2954 | #endif /* ! BNX2X_STOP_ON_ERROR */ |
9f6c9258 DK |
2955 | } |
2956 | ||
7fa6f340 | 2957 | int bnx2x_drain_tx_queues(struct bnx2x *bp) |
ad5afc89 AE |
2958 | { |
2959 | u8 rc = 0, cos, i; | |
2960 | ||
2961 | /* Wait until tx fastpath tasks complete */ | |
2962 | for_each_tx_queue(bp, i) { | |
2963 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
2964 | ||
2965 | for_each_cos_in_tx_queue(fp, cos) | |
2966 | rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); | |
2967 | if (rc) | |
2968 | return rc; | |
2969 | } | |
2970 | return 0; | |
2971 | } | |
2972 | ||
9f6c9258 | 2973 | /* must be called with rtnl_lock */ |
5d07d868 | 2974 | int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link) |
9f6c9258 DK |
2975 | { |
2976 | int i; | |
c9ee9206 VZ |
2977 | bool global = false; |
2978 | ||
55c11941 MS |
2979 | DP(NETIF_MSG_IFUP, "Starting NIC unload\n"); |
2980 | ||
230d00eb YM |
2981 | if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) |
2982 | bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED); | |
2983 | ||
9ce392d4 | 2984 | /* mark driver is unloaded in shmem2 */ |
ad5afc89 | 2985 | if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { |
9ce392d4 YM |
2986 | u32 val; |
2987 | val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]); | |
2988 | SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], | |
2989 | val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); | |
2990 | } | |
2991 | ||
80bfe5cc | 2992 | if (IS_PF(bp) && bp->recovery_state != BNX2X_RECOVERY_DONE && |
ad5afc89 AE |
2993 | (bp->state == BNX2X_STATE_CLOSED || |
2994 | bp->state == BNX2X_STATE_ERROR)) { | |
c9ee9206 VZ |
2995 | /* We can get here if the driver has been unloaded |
2996 | * during parity error recovery and is either waiting for a | |
2997 | * leader to complete or for other functions to unload and | |
2998 | * then ifdown has been issued. In this case we want to | |
2999 | * unload and let other functions to complete a recovery | |
3000 | * process. | |
3001 | */ | |
9f6c9258 DK |
3002 | bp->recovery_state = BNX2X_RECOVERY_DONE; |
3003 | bp->is_leader = 0; | |
c9ee9206 VZ |
3004 | bnx2x_release_leader_lock(bp); |
3005 | smp_mb(); | |
3006 | ||
51c1a580 MS |
3007 | DP(NETIF_MSG_IFDOWN, "Releasing a leadership...\n"); |
3008 | BNX2X_ERR("Can't unload in closed or error state\n"); | |
9f6c9258 DK |
3009 | return -EINVAL; |
3010 | } | |
3011 | ||
80bfe5cc | 3012 | /* Nothing to do during unload if previous bnx2x_nic_load() |
16a5fd92 | 3013 | * have not completed successfully - all resources are released. |
80bfe5cc YM |
3014 | * |
3015 | * we can get here only after unsuccessful ndo_* callback, during which | |
3016 | * dev->IFF_UP flag is still on. | |
3017 | */ | |
3018 | if (bp->state == BNX2X_STATE_CLOSED || bp->state == BNX2X_STATE_ERROR) | |
3019 | return 0; | |
3020 | ||
3021 | /* It's important to set the bp->state to the value different from | |
87b7ba3d VZ |
3022 | * BNX2X_STATE_OPEN and only then stop the Tx. Otherwise bnx2x_tx_int() |
3023 | * may restart the Tx from the NAPI context (see bnx2x_tx_int()). | |
3024 | */ | |
3025 | bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; | |
3026 | smp_mb(); | |
3027 | ||
78c3bcc5 AE |
3028 | /* indicate to VFs that the PF is going down */ |
3029 | bnx2x_iov_channel_down(bp); | |
3030 | ||
55c11941 MS |
3031 | if (CNIC_LOADED(bp)) |
3032 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
3033 | ||
9505ee37 VZ |
3034 | /* Stop Tx */ |
3035 | bnx2x_tx_disable(bp); | |
65565884 | 3036 | netdev_reset_tc(bp->dev); |
9505ee37 | 3037 | |
9f6c9258 | 3038 | bp->rx_mode = BNX2X_RX_MODE_NONE; |
9f6c9258 | 3039 | |
9f6c9258 | 3040 | del_timer_sync(&bp->timer); |
f85582f8 | 3041 | |
f7084059 | 3042 | if (IS_PF(bp) && !BP_NOMCP(bp)) { |
ad5afc89 AE |
3043 | /* Set ALWAYS_ALIVE bit in shmem */ |
3044 | bp->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE; | |
3045 | bnx2x_drv_pulse(bp); | |
3046 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
3047 | bnx2x_save_statistics(bp); | |
3048 | } | |
9f6c9258 | 3049 | |
d78a1f08 YM |
3050 | /* wait till consumers catch up with producers in all queues. |
3051 | * If we're recovering, FW can't write to host so no reason | |
3052 | * to wait for the queues to complete all Tx. | |
3053 | */ | |
3054 | if (unload_mode != UNLOAD_RECOVERY) | |
3055 | bnx2x_drain_tx_queues(bp); | |
9f6c9258 | 3056 | |
9b176b6b AE |
3057 | /* if VF indicate to PF this function is going down (PF will delete sp |
3058 | * elements and clear initializations | |
3059 | */ | |
c99ec777 MC |
3060 | if (IS_VF(bp)) { |
3061 | bnx2x_clear_vlan_info(bp); | |
9b176b6b | 3062 | bnx2x_vfpf_close_vf(bp); |
c99ec777 | 3063 | } else if (unload_mode != UNLOAD_RECOVERY) { |
9b176b6b | 3064 | /* if this is a normal/close unload need to clean up chip*/ |
5d07d868 | 3065 | bnx2x_chip_cleanup(bp, unload_mode, keep_link); |
c99ec777 | 3066 | } else { |
c9ee9206 VZ |
3067 | /* Send the UNLOAD_REQUEST to the MCP */ |
3068 | bnx2x_send_unload_req(bp, unload_mode); | |
3069 | ||
16a5fd92 | 3070 | /* Prevent transactions to host from the functions on the |
c9ee9206 | 3071 | * engine that doesn't reset global blocks in case of global |
16a5fd92 | 3072 | * attention once global blocks are reset and gates are opened |
c9ee9206 VZ |
3073 | * (the engine which leader will perform the recovery |
3074 | * last). | |
3075 | */ | |
3076 | if (!CHIP_IS_E1x(bp)) | |
3077 | bnx2x_pf_disable(bp); | |
3078 | ||
3079 | /* Disable HW interrupts, NAPI */ | |
523224a3 | 3080 | bnx2x_netif_stop(bp, 1); |
26614ba5 MS |
3081 | /* Delete all NAPI objects */ |
3082 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
3083 | if (CNIC_LOADED(bp)) |
3084 | bnx2x_del_all_napi_cnic(bp); | |
523224a3 | 3085 | /* Release IRQs */ |
d6214d7a | 3086 | bnx2x_free_irq(bp); |
c9ee9206 VZ |
3087 | |
3088 | /* Report UNLOAD_DONE to MCP */ | |
5d07d868 | 3089 | bnx2x_send_unload_done(bp, false); |
523224a3 | 3090 | } |
9f6c9258 | 3091 | |
619c5cb6 | 3092 | /* |
16a5fd92 | 3093 | * At this stage no more interrupts will arrive so we may safely clean |
619c5cb6 VZ |
3094 | * the queueable objects here in case they failed to get cleaned so far. |
3095 | */ | |
ad5afc89 AE |
3096 | if (IS_PF(bp)) |
3097 | bnx2x_squeeze_objects(bp); | |
619c5cb6 | 3098 | |
79616895 VZ |
3099 | /* There should be no more pending SP commands at this stage */ |
3100 | bp->sp_state = 0; | |
3101 | ||
9f6c9258 DK |
3102 | bp->port.pmf = 0; |
3103 | ||
a0d307b2 DK |
3104 | /* clear pending work in rtnl task */ |
3105 | bp->sp_rtnl_state = 0; | |
3106 | smp_mb(); | |
3107 | ||
9f6c9258 DK |
3108 | /* Free SKBs, SGEs, TPA pool and driver internals */ |
3109 | bnx2x_free_skbs(bp); | |
55c11941 MS |
3110 | if (CNIC_LOADED(bp)) |
3111 | bnx2x_free_skbs_cnic(bp); | |
ec6ba945 | 3112 | for_each_rx_queue(bp, i) |
9f6c9258 | 3113 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); |
d6214d7a | 3114 | |
ad5afc89 AE |
3115 | bnx2x_free_fp_mem(bp); |
3116 | if (CNIC_LOADED(bp)) | |
55c11941 | 3117 | bnx2x_free_fp_mem_cnic(bp); |
9f6c9258 | 3118 | |
ad5afc89 | 3119 | if (IS_PF(bp)) { |
ad5afc89 AE |
3120 | if (CNIC_LOADED(bp)) |
3121 | bnx2x_free_mem_cnic(bp); | |
3122 | } | |
b4cddbd6 AE |
3123 | bnx2x_free_mem(bp); |
3124 | ||
9f6c9258 | 3125 | bp->state = BNX2X_STATE_CLOSED; |
55c11941 | 3126 | bp->cnic_loaded = false; |
9f6c9258 | 3127 | |
42f8277f | 3128 | /* Clear driver version indication in shmem */ |
f7084059 | 3129 | if (IS_PF(bp) && !BP_NOMCP(bp)) |
42f8277f YM |
3130 | bnx2x_update_mng_version(bp); |
3131 | ||
c9ee9206 VZ |
3132 | /* Check if there are pending parity attentions. If there are - set |
3133 | * RECOVERY_IN_PROGRESS. | |
3134 | */ | |
ad5afc89 | 3135 | if (IS_PF(bp) && bnx2x_chk_parity_attn(bp, &global, false)) { |
c9ee9206 VZ |
3136 | bnx2x_set_reset_in_progress(bp); |
3137 | ||
3138 | /* Set RESET_IS_GLOBAL if needed */ | |
3139 | if (global) | |
3140 | bnx2x_set_reset_global(bp); | |
3141 | } | |
3142 | ||
9f6c9258 DK |
3143 | /* The last driver must disable a "close the gate" if there is no |
3144 | * parity attention or "process kill" pending. | |
3145 | */ | |
ad5afc89 AE |
3146 | if (IS_PF(bp) && |
3147 | !bnx2x_clear_pf_load(bp) && | |
3148 | bnx2x_reset_is_done(bp, BP_PATH(bp))) | |
9f6c9258 DK |
3149 | bnx2x_disable_close_the_gate(bp); |
3150 | ||
55c11941 MS |
3151 | DP(NETIF_MSG_IFUP, "Ending NIC unload\n"); |
3152 | ||
9f6c9258 DK |
3153 | return 0; |
3154 | } | |
f85582f8 | 3155 | |
9f6c9258 DK |
3156 | int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state) |
3157 | { | |
3158 | u16 pmcsr; | |
3159 | ||
adf5f6a1 | 3160 | /* If there is no power capability, silently succeed */ |
29ed74c3 | 3161 | if (!bp->pdev->pm_cap) { |
51c1a580 | 3162 | BNX2X_DEV_INFO("No power capability. Breaking.\n"); |
adf5f6a1 DK |
3163 | return 0; |
3164 | } | |
3165 | ||
29ed74c3 | 3166 | pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL, &pmcsr); |
9f6c9258 DK |
3167 | |
3168 | switch (state) { | |
3169 | case PCI_D0: | |
29ed74c3 | 3170 | pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL, |
9f6c9258 DK |
3171 | ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) | |
3172 | PCI_PM_CTRL_PME_STATUS)); | |
3173 | ||
3174 | if (pmcsr & PCI_PM_CTRL_STATE_MASK) | |
3175 | /* delay required during transition out of D3hot */ | |
3176 | msleep(20); | |
3177 | break; | |
3178 | ||
3179 | case PCI_D3hot: | |
3180 | /* If there are other clients above don't | |
3181 | shut down the power */ | |
3182 | if (atomic_read(&bp->pdev->enable_cnt) != 1) | |
3183 | return 0; | |
3184 | /* Don't shut down the power for emulation and FPGA */ | |
3185 | if (CHIP_REV_IS_SLOW(bp)) | |
3186 | return 0; | |
3187 | ||
3188 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
3189 | pmcsr |= 3; | |
3190 | ||
3191 | if (bp->wol) | |
3192 | pmcsr |= PCI_PM_CTRL_PME_ENABLE; | |
3193 | ||
29ed74c3 | 3194 | pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL, |
9f6c9258 DK |
3195 | pmcsr); |
3196 | ||
3197 | /* No more memory access after this point until | |
3198 | * device is brought back to D0. | |
3199 | */ | |
3200 | break; | |
3201 | ||
3202 | default: | |
51c1a580 | 3203 | dev_err(&bp->pdev->dev, "Can't support state = %d\n", state); |
9f6c9258 DK |
3204 | return -EINVAL; |
3205 | } | |
3206 | return 0; | |
3207 | } | |
3208 | ||
9f6c9258 DK |
3209 | /* |
3210 | * net_device service functions | |
3211 | */ | |
a8f47eb7 | 3212 | static int bnx2x_poll(struct napi_struct *napi, int budget) |
9f6c9258 | 3213 | { |
9f6c9258 DK |
3214 | struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath, |
3215 | napi); | |
3216 | struct bnx2x *bp = fp->bp; | |
4d6acb62 ED |
3217 | int rx_work_done; |
3218 | u8 cos; | |
9f6c9258 | 3219 | |
9f6c9258 | 3220 | #ifdef BNX2X_STOP_ON_ERROR |
4d6acb62 ED |
3221 | if (unlikely(bp->panic)) { |
3222 | napi_complete(napi); | |
3223 | return 0; | |
3224 | } | |
9f6c9258 | 3225 | #endif |
4d6acb62 ED |
3226 | for_each_cos_in_tx_queue(fp, cos) |
3227 | if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) | |
3228 | bnx2x_tx_int(bp, fp->txdata_ptr[cos]); | |
9f6c9258 | 3229 | |
4d6acb62 | 3230 | rx_work_done = (bnx2x_has_rx_work(fp)) ? bnx2x_rx_int(fp, budget) : 0; |
55c11941 | 3231 | |
4d6acb62 ED |
3232 | if (rx_work_done < budget) { |
3233 | /* No need to update SB for FCoE L2 ring as long as | |
3234 | * it's connected to the default SB and the SB | |
3235 | * has been updated when NAPI was scheduled. | |
3236 | */ | |
3237 | if (IS_FCOE_FP(fp)) { | |
6ad20165 | 3238 | napi_complete_done(napi, rx_work_done); |
4d6acb62 | 3239 | } else { |
9f6c9258 | 3240 | bnx2x_update_fpsb_idx(fp); |
f85582f8 DK |
3241 | /* bnx2x_has_rx_work() reads the status block, |
3242 | * thus we need to ensure that status block indices | |
3243 | * have been actually read (bnx2x_update_fpsb_idx) | |
3244 | * prior to this check (bnx2x_has_rx_work) so that | |
3245 | * we won't write the "newer" value of the status block | |
3246 | * to IGU (if there was a DMA right after | |
3247 | * bnx2x_has_rx_work and if there is no rmb, the memory | |
3248 | * reading (bnx2x_update_fpsb_idx) may be postponed | |
3249 | * to right before bnx2x_ack_sb). In this case there | |
3250 | * will never be another interrupt until there is | |
3251 | * another update of the status block, while there | |
3252 | * is still unhandled work. | |
3253 | */ | |
9f6c9258 DK |
3254 | rmb(); |
3255 | ||
3256 | if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { | |
80f1c21c ED |
3257 | if (napi_complete_done(napi, rx_work_done)) { |
3258 | /* Re-enable interrupts */ | |
3259 | DP(NETIF_MSG_RX_STATUS, | |
3260 | "Update index to %d\n", fp->fp_hc_idx); | |
3261 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, | |
3262 | le16_to_cpu(fp->fp_hc_idx), | |
3263 | IGU_INT_ENABLE, 1); | |
3264 | } | |
4d6acb62 ED |
3265 | } else { |
3266 | rx_work_done = budget; | |
9f6c9258 DK |
3267 | } |
3268 | } | |
3269 | } | |
3270 | ||
4d6acb62 | 3271 | return rx_work_done; |
9f6c9258 DK |
3272 | } |
3273 | ||
9f6c9258 DK |
3274 | /* we split the first BD into headers and data BDs |
3275 | * to ease the pain of our fellow microcode engineers | |
3276 | * we use one mapping for both BDs | |
9f6c9258 | 3277 | */ |
91226790 DK |
3278 | static u16 bnx2x_tx_split(struct bnx2x *bp, |
3279 | struct bnx2x_fp_txdata *txdata, | |
3280 | struct sw_tx_bd *tx_buf, | |
3281 | struct eth_tx_start_bd **tx_bd, u16 hlen, | |
3282 | u16 bd_prod) | |
9f6c9258 DK |
3283 | { |
3284 | struct eth_tx_start_bd *h_tx_bd = *tx_bd; | |
3285 | struct eth_tx_bd *d_tx_bd; | |
3286 | dma_addr_t mapping; | |
3287 | int old_len = le16_to_cpu(h_tx_bd->nbytes); | |
3288 | ||
3289 | /* first fix first BD */ | |
9f6c9258 DK |
3290 | h_tx_bd->nbytes = cpu_to_le16(hlen); |
3291 | ||
91226790 DK |
3292 | DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d (%x:%x)\n", |
3293 | h_tx_bd->nbytes, h_tx_bd->addr_hi, h_tx_bd->addr_lo); | |
9f6c9258 DK |
3294 | |
3295 | /* now get a new data BD | |
3296 | * (after the pbd) and fill it */ | |
3297 | bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); | |
6383c0b3 | 3298 | d_tx_bd = &txdata->tx_desc_ring[bd_prod].reg_bd; |
9f6c9258 DK |
3299 | |
3300 | mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi), | |
3301 | le32_to_cpu(h_tx_bd->addr_lo)) + hlen; | |
3302 | ||
3303 | d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); | |
3304 | d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
3305 | d_tx_bd->nbytes = cpu_to_le16(old_len - hlen); | |
3306 | ||
3307 | /* this marks the BD as one that has no individual mapping */ | |
3308 | tx_buf->flags |= BNX2X_TSO_SPLIT_BD; | |
3309 | ||
3310 | DP(NETIF_MSG_TX_QUEUED, | |
3311 | "TSO split data size is %d (%x:%x)\n", | |
3312 | d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo); | |
3313 | ||
3314 | /* update tx_bd */ | |
3315 | *tx_bd = (struct eth_tx_start_bd *)d_tx_bd; | |
3316 | ||
3317 | return bd_prod; | |
3318 | } | |
3319 | ||
86564c3f YM |
3320 | #define bswab32(b32) ((__force __le32) swab32((__force __u32) (b32))) |
3321 | #define bswab16(b16) ((__force __le16) swab16((__force __u16) (b16))) | |
91226790 | 3322 | static __le16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix) |
9f6c9258 | 3323 | { |
86564c3f YM |
3324 | __sum16 tsum = (__force __sum16) csum; |
3325 | ||
9f6c9258 | 3326 | if (fix > 0) |
86564c3f YM |
3327 | tsum = ~csum_fold(csum_sub((__force __wsum) csum, |
3328 | csum_partial(t_header - fix, fix, 0))); | |
9f6c9258 DK |
3329 | |
3330 | else if (fix < 0) | |
86564c3f YM |
3331 | tsum = ~csum_fold(csum_add((__force __wsum) csum, |
3332 | csum_partial(t_header, -fix, 0))); | |
9f6c9258 | 3333 | |
e2593fcd | 3334 | return bswab16(tsum); |
9f6c9258 DK |
3335 | } |
3336 | ||
91226790 | 3337 | static u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb) |
9f6c9258 DK |
3338 | { |
3339 | u32 rc; | |
a848ade4 DK |
3340 | __u8 prot = 0; |
3341 | __be16 protocol; | |
9f6c9258 DK |
3342 | |
3343 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
a848ade4 | 3344 | return XMIT_PLAIN; |
9f6c9258 | 3345 | |
a848ade4 DK |
3346 | protocol = vlan_get_protocol(skb); |
3347 | if (protocol == htons(ETH_P_IPV6)) { | |
3348 | rc = XMIT_CSUM_V6; | |
3349 | prot = ipv6_hdr(skb)->nexthdr; | |
3350 | } else { | |
3351 | rc = XMIT_CSUM_V4; | |
3352 | prot = ip_hdr(skb)->protocol; | |
3353 | } | |
9f6c9258 | 3354 | |
a848ade4 DK |
3355 | if (!CHIP_IS_E1x(bp) && skb->encapsulation) { |
3356 | if (inner_ip_hdr(skb)->version == 6) { | |
3357 | rc |= XMIT_CSUM_ENC_V6; | |
3358 | if (inner_ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
3359 | rc |= XMIT_CSUM_TCP; | |
9f6c9258 | 3360 | } else { |
a848ade4 DK |
3361 | rc |= XMIT_CSUM_ENC_V4; |
3362 | if (inner_ip_hdr(skb)->protocol == IPPROTO_TCP) | |
9f6c9258 DK |
3363 | rc |= XMIT_CSUM_TCP; |
3364 | } | |
3365 | } | |
a848ade4 DK |
3366 | if (prot == IPPROTO_TCP) |
3367 | rc |= XMIT_CSUM_TCP; | |
9f6c9258 | 3368 | |
36a8f39e ED |
3369 | if (skb_is_gso(skb)) { |
3370 | if (skb_is_gso_v6(skb)) { | |
3371 | rc |= (XMIT_GSO_V6 | XMIT_CSUM_TCP); | |
3372 | if (rc & XMIT_CSUM_ENC) | |
3373 | rc |= XMIT_GSO_ENC_V6; | |
3374 | } else { | |
3375 | rc |= (XMIT_GSO_V4 | XMIT_CSUM_TCP); | |
3376 | if (rc & XMIT_CSUM_ENC) | |
3377 | rc |= XMIT_GSO_ENC_V4; | |
3378 | } | |
a848ade4 | 3379 | } |
9f6c9258 DK |
3380 | |
3381 | return rc; | |
3382 | } | |
3383 | ||
ea2465af YM |
3384 | /* VXLAN: 4 = 1 (for linear data BD) + 3 (2 for PBD and last BD) */ |
3385 | #define BNX2X_NUM_VXLAN_TSO_WIN_SUB_BDS 4 | |
3386 | ||
3387 | /* Regular: 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */ | |
3388 | #define BNX2X_NUM_TSO_WIN_SUB_BDS 3 | |
3389 | ||
3390 | #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - BDS_PER_TX_PKT) | |
9f6c9258 DK |
3391 | /* check if packet requires linearization (packet is too fragmented) |
3392 | no need to check fragmentation if page size > 8K (there will be no | |
3393 | violation to FW restrictions) */ | |
3394 | static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb, | |
3395 | u32 xmit_type) | |
3396 | { | |
ea2465af YM |
3397 | int first_bd_sz = 0, num_tso_win_sub = BNX2X_NUM_TSO_WIN_SUB_BDS; |
3398 | int to_copy = 0, hlen = 0; | |
9f6c9258 | 3399 | |
ea2465af YM |
3400 | if (xmit_type & XMIT_GSO_ENC) |
3401 | num_tso_win_sub = BNX2X_NUM_VXLAN_TSO_WIN_SUB_BDS; | |
9f6c9258 | 3402 | |
ea2465af | 3403 | if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - num_tso_win_sub)) { |
9f6c9258 DK |
3404 | if (xmit_type & XMIT_GSO) { |
3405 | unsigned short lso_mss = skb_shinfo(skb)->gso_size; | |
ea2465af | 3406 | int wnd_size = MAX_FETCH_BD - num_tso_win_sub; |
9f6c9258 DK |
3407 | /* Number of windows to check */ |
3408 | int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size; | |
3409 | int wnd_idx = 0; | |
3410 | int frag_idx = 0; | |
3411 | u32 wnd_sum = 0; | |
3412 | ||
3413 | /* Headers length */ | |
592b9b8d YM |
3414 | if (xmit_type & XMIT_GSO_ENC) |
3415 | hlen = (int)(skb_inner_transport_header(skb) - | |
3416 | skb->data) + | |
3417 | inner_tcp_hdrlen(skb); | |
3418 | else | |
3419 | hlen = (int)(skb_transport_header(skb) - | |
3420 | skb->data) + tcp_hdrlen(skb); | |
9f6c9258 DK |
3421 | |
3422 | /* Amount of data (w/o headers) on linear part of SKB*/ | |
3423 | first_bd_sz = skb_headlen(skb) - hlen; | |
3424 | ||
3425 | wnd_sum = first_bd_sz; | |
3426 | ||
3427 | /* Calculate the first sum - it's special */ | |
3428 | for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++) | |
3429 | wnd_sum += | |
9e903e08 | 3430 | skb_frag_size(&skb_shinfo(skb)->frags[frag_idx]); |
9f6c9258 DK |
3431 | |
3432 | /* If there was data on linear skb data - check it */ | |
3433 | if (first_bd_sz > 0) { | |
3434 | if (unlikely(wnd_sum < lso_mss)) { | |
3435 | to_copy = 1; | |
3436 | goto exit_lbl; | |
3437 | } | |
3438 | ||
3439 | wnd_sum -= first_bd_sz; | |
3440 | } | |
3441 | ||
3442 | /* Others are easier: run through the frag list and | |
3443 | check all windows */ | |
3444 | for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) { | |
3445 | wnd_sum += | |
9e903e08 | 3446 | skb_frag_size(&skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1]); |
9f6c9258 DK |
3447 | |
3448 | if (unlikely(wnd_sum < lso_mss)) { | |
3449 | to_copy = 1; | |
3450 | break; | |
3451 | } | |
3452 | wnd_sum -= | |
9e903e08 | 3453 | skb_frag_size(&skb_shinfo(skb)->frags[wnd_idx]); |
9f6c9258 DK |
3454 | } |
3455 | } else { | |
3456 | /* in non-LSO too fragmented packet should always | |
3457 | be linearized */ | |
3458 | to_copy = 1; | |
3459 | } | |
3460 | } | |
3461 | ||
3462 | exit_lbl: | |
3463 | if (unlikely(to_copy)) | |
3464 | DP(NETIF_MSG_TX_QUEUED, | |
51c1a580 | 3465 | "Linearization IS REQUIRED for %s packet. num_frags %d hlen %d first_bd_sz %d\n", |
9f6c9258 DK |
3466 | (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO", |
3467 | skb_shinfo(skb)->nr_frags, hlen, first_bd_sz); | |
3468 | ||
3469 | return to_copy; | |
3470 | } | |
3471 | #endif | |
3472 | ||
f2e0899f | 3473 | /** |
e8920674 | 3474 | * bnx2x_set_pbd_gso - update PBD in GSO case. |
f2e0899f | 3475 | * |
e8920674 DK |
3476 | * @skb: packet skb |
3477 | * @pbd: parse BD | |
3478 | * @xmit_type: xmit flags | |
f2e0899f | 3479 | */ |
91226790 DK |
3480 | static void bnx2x_set_pbd_gso(struct sk_buff *skb, |
3481 | struct eth_tx_parse_bd_e1x *pbd, | |
3482 | u32 xmit_type) | |
f2e0899f DK |
3483 | { |
3484 | pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size); | |
86564c3f | 3485 | pbd->tcp_send_seq = bswab32(tcp_hdr(skb)->seq); |
91226790 | 3486 | pbd->tcp_flags = pbd_tcp_flags(tcp_hdr(skb)); |
f2e0899f DK |
3487 | |
3488 | if (xmit_type & XMIT_GSO_V4) { | |
86564c3f | 3489 | pbd->ip_id = bswab16(ip_hdr(skb)->id); |
f2e0899f | 3490 | pbd->tcp_pseudo_csum = |
86564c3f YM |
3491 | bswab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr, |
3492 | ip_hdr(skb)->daddr, | |
3493 | 0, IPPROTO_TCP, 0)); | |
057cf65e | 3494 | } else { |
f2e0899f | 3495 | pbd->tcp_pseudo_csum = |
86564c3f YM |
3496 | bswab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, |
3497 | &ipv6_hdr(skb)->daddr, | |
3498 | 0, IPPROTO_TCP, 0)); | |
057cf65e | 3499 | } |
f2e0899f | 3500 | |
86564c3f YM |
3501 | pbd->global_data |= |
3502 | cpu_to_le16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN); | |
f2e0899f | 3503 | } |
f85582f8 | 3504 | |
a848ade4 DK |
3505 | /** |
3506 | * bnx2x_set_pbd_csum_enc - update PBD with checksum and return header length | |
3507 | * | |
3508 | * @bp: driver handle | |
3509 | * @skb: packet skb | |
3510 | * @parsing_data: data to be updated | |
3511 | * @xmit_type: xmit flags | |
3512 | * | |
3513 | * 57712/578xx related, when skb has encapsulation | |
3514 | */ | |
3515 | static u8 bnx2x_set_pbd_csum_enc(struct bnx2x *bp, struct sk_buff *skb, | |
3516 | u32 *parsing_data, u32 xmit_type) | |
3517 | { | |
3518 | *parsing_data |= | |
3519 | ((((u8 *)skb_inner_transport_header(skb) - skb->data) >> 1) << | |
3520 | ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) & | |
3521 | ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W; | |
3522 | ||
3523 | if (xmit_type & XMIT_CSUM_TCP) { | |
3524 | *parsing_data |= ((inner_tcp_hdrlen(skb) / 4) << | |
3525 | ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) & | |
3526 | ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW; | |
3527 | ||
3528 | return skb_inner_transport_header(skb) + | |
3529 | inner_tcp_hdrlen(skb) - skb->data; | |
3530 | } | |
3531 | ||
3532 | /* We support checksum offload for TCP and UDP only. | |
3533 | * No need to pass the UDP header length - it's a constant. | |
3534 | */ | |
3535 | return skb_inner_transport_header(skb) + | |
3536 | sizeof(struct udphdr) - skb->data; | |
3537 | } | |
3538 | ||
f2e0899f | 3539 | /** |
e8920674 | 3540 | * bnx2x_set_pbd_csum_e2 - update PBD with checksum and return header length |
f2e0899f | 3541 | * |
e8920674 DK |
3542 | * @bp: driver handle |
3543 | * @skb: packet skb | |
3544 | * @parsing_data: data to be updated | |
3545 | * @xmit_type: xmit flags | |
f2e0899f | 3546 | * |
91226790 | 3547 | * 57712/578xx related |
f2e0899f | 3548 | */ |
91226790 DK |
3549 | static u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb, |
3550 | u32 *parsing_data, u32 xmit_type) | |
f2e0899f | 3551 | { |
e39aece7 | 3552 | *parsing_data |= |
2de67439 | 3553 | ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) << |
91226790 DK |
3554 | ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) & |
3555 | ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W; | |
f2e0899f | 3556 | |
e39aece7 VZ |
3557 | if (xmit_type & XMIT_CSUM_TCP) { |
3558 | *parsing_data |= ((tcp_hdrlen(skb) / 4) << | |
3559 | ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) & | |
3560 | ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW; | |
f2e0899f | 3561 | |
e39aece7 | 3562 | return skb_transport_header(skb) + tcp_hdrlen(skb) - skb->data; |
924d75ab YM |
3563 | } |
3564 | /* We support checksum offload for TCP and UDP only. | |
3565 | * No need to pass the UDP header length - it's a constant. | |
3566 | */ | |
3567 | return skb_transport_header(skb) + sizeof(struct udphdr) - skb->data; | |
f2e0899f DK |
3568 | } |
3569 | ||
a848ade4 | 3570 | /* set FW indication according to inner or outer protocols if tunneled */ |
91226790 DK |
3571 | static void bnx2x_set_sbd_csum(struct bnx2x *bp, struct sk_buff *skb, |
3572 | struct eth_tx_start_bd *tx_start_bd, | |
3573 | u32 xmit_type) | |
93ef5c02 | 3574 | { |
93ef5c02 DK |
3575 | tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM; |
3576 | ||
a848ade4 | 3577 | if (xmit_type & (XMIT_CSUM_ENC_V6 | XMIT_CSUM_V6)) |
91226790 | 3578 | tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IPV6; |
93ef5c02 DK |
3579 | |
3580 | if (!(xmit_type & XMIT_CSUM_TCP)) | |
3581 | tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IS_UDP; | |
93ef5c02 DK |
3582 | } |
3583 | ||
f2e0899f | 3584 | /** |
e8920674 | 3585 | * bnx2x_set_pbd_csum - update PBD with checksum and return header length |
f2e0899f | 3586 | * |
e8920674 DK |
3587 | * @bp: driver handle |
3588 | * @skb: packet skb | |
3589 | * @pbd: parse BD to be updated | |
3590 | * @xmit_type: xmit flags | |
f2e0899f | 3591 | */ |
91226790 DK |
3592 | static u8 bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb, |
3593 | struct eth_tx_parse_bd_e1x *pbd, | |
3594 | u32 xmit_type) | |
f2e0899f | 3595 | { |
e39aece7 | 3596 | u8 hlen = (skb_network_header(skb) - skb->data) >> 1; |
f2e0899f DK |
3597 | |
3598 | /* for now NS flag is not used in Linux */ | |
3599 | pbd->global_data = | |
86564c3f YM |
3600 | cpu_to_le16(hlen | |
3601 | ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) << | |
3602 | ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT)); | |
f2e0899f DK |
3603 | |
3604 | pbd->ip_hlen_w = (skb_transport_header(skb) - | |
e39aece7 | 3605 | skb_network_header(skb)) >> 1; |
f2e0899f | 3606 | |
e39aece7 VZ |
3607 | hlen += pbd->ip_hlen_w; |
3608 | ||
3609 | /* We support checksum offload for TCP and UDP only */ | |
3610 | if (xmit_type & XMIT_CSUM_TCP) | |
3611 | hlen += tcp_hdrlen(skb) / 2; | |
3612 | else | |
3613 | hlen += sizeof(struct udphdr) / 2; | |
f2e0899f DK |
3614 | |
3615 | pbd->total_hlen_w = cpu_to_le16(hlen); | |
3616 | hlen = hlen*2; | |
3617 | ||
3618 | if (xmit_type & XMIT_CSUM_TCP) { | |
86564c3f | 3619 | pbd->tcp_pseudo_csum = bswab16(tcp_hdr(skb)->check); |
f2e0899f DK |
3620 | |
3621 | } else { | |
3622 | s8 fix = SKB_CS_OFF(skb); /* signed! */ | |
3623 | ||
3624 | DP(NETIF_MSG_TX_QUEUED, | |
3625 | "hlen %d fix %d csum before fix %x\n", | |
3626 | le16_to_cpu(pbd->total_hlen_w), fix, SKB_CS(skb)); | |
3627 | ||
3628 | /* HW bug: fixup the CSUM */ | |
3629 | pbd->tcp_pseudo_csum = | |
3630 | bnx2x_csum_fix(skb_transport_header(skb), | |
3631 | SKB_CS(skb), fix); | |
3632 | ||
3633 | DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n", | |
3634 | pbd->tcp_pseudo_csum); | |
3635 | } | |
3636 | ||
3637 | return hlen; | |
3638 | } | |
f85582f8 | 3639 | |
a848ade4 DK |
3640 | static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb, |
3641 | struct eth_tx_parse_bd_e2 *pbd_e2, | |
3642 | struct eth_tx_parse_2nd_bd *pbd2, | |
3643 | u16 *global_data, | |
3644 | u32 xmit_type) | |
3645 | { | |
e287a75c | 3646 | u16 hlen_w = 0; |
a848ade4 | 3647 | u8 outerip_off, outerip_len = 0; |
e768fb29 | 3648 | |
e287a75c DK |
3649 | /* from outer IP to transport */ |
3650 | hlen_w = (skb_inner_transport_header(skb) - | |
3651 | skb_network_header(skb)) >> 1; | |
a848ade4 DK |
3652 | |
3653 | /* transport len */ | |
e768fb29 | 3654 | hlen_w += inner_tcp_hdrlen(skb) >> 1; |
a848ade4 | 3655 | |
e287a75c | 3656 | pbd2->fw_ip_hdr_to_payload_w = hlen_w; |
a848ade4 | 3657 | |
e768fb29 DK |
3658 | /* outer IP header info */ |
3659 | if (xmit_type & XMIT_CSUM_V4) { | |
e287a75c | 3660 | struct iphdr *iph = ip_hdr(skb); |
1b4fc0e2 DK |
3661 | u32 csum = (__force u32)(~iph->check) - |
3662 | (__force u32)iph->tot_len - | |
3663 | (__force u32)iph->frag_off; | |
c957d09f | 3664 | |
e42780b6 DK |
3665 | outerip_len = iph->ihl << 1; |
3666 | ||
a848ade4 | 3667 | pbd2->fw_ip_csum_wo_len_flags_frag = |
c957d09f | 3668 | bswab16(csum_fold((__force __wsum)csum)); |
a848ade4 DK |
3669 | } else { |
3670 | pbd2->fw_ip_hdr_to_payload_w = | |
e287a75c | 3671 | hlen_w - ((sizeof(struct ipv6hdr)) >> 1); |
e42780b6 | 3672 | pbd_e2->data.tunnel_data.flags |= |
28311f8e | 3673 | ETH_TUNNEL_DATA_IPV6_OUTER; |
a848ade4 DK |
3674 | } |
3675 | ||
3676 | pbd2->tcp_send_seq = bswab32(inner_tcp_hdr(skb)->seq); | |
3677 | ||
3678 | pbd2->tcp_flags = pbd_tcp_flags(inner_tcp_hdr(skb)); | |
3679 | ||
e42780b6 DK |
3680 | /* inner IP header info */ |
3681 | if (xmit_type & XMIT_CSUM_ENC_V4) { | |
e287a75c | 3682 | pbd2->hw_ip_id = bswab16(inner_ip_hdr(skb)->id); |
a848ade4 DK |
3683 | |
3684 | pbd_e2->data.tunnel_data.pseudo_csum = | |
3685 | bswab16(~csum_tcpudp_magic( | |
3686 | inner_ip_hdr(skb)->saddr, | |
3687 | inner_ip_hdr(skb)->daddr, | |
3688 | 0, IPPROTO_TCP, 0)); | |
a848ade4 DK |
3689 | } else { |
3690 | pbd_e2->data.tunnel_data.pseudo_csum = | |
3691 | bswab16(~csum_ipv6_magic( | |
3692 | &inner_ipv6_hdr(skb)->saddr, | |
3693 | &inner_ipv6_hdr(skb)->daddr, | |
3694 | 0, IPPROTO_TCP, 0)); | |
3695 | } | |
3696 | ||
3697 | outerip_off = (skb_network_header(skb) - skb->data) >> 1; | |
3698 | ||
3699 | *global_data |= | |
3700 | outerip_off | | |
a848ade4 DK |
3701 | (outerip_len << |
3702 | ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT) | | |
3703 | ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) << | |
3704 | ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT); | |
65bc0cfe DK |
3705 | |
3706 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { | |
3707 | SET_FLAG(*global_data, ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST, 1); | |
3708 | pbd2->tunnel_udp_hdr_start_w = skb_transport_offset(skb) >> 1; | |
3709 | } | |
a848ade4 DK |
3710 | } |
3711 | ||
e42780b6 DK |
3712 | static inline void bnx2x_set_ipv6_ext_e2(struct sk_buff *skb, u32 *parsing_data, |
3713 | u32 xmit_type) | |
3714 | { | |
3715 | struct ipv6hdr *ipv6; | |
3716 | ||
3717 | if (!(xmit_type & (XMIT_GSO_ENC_V6 | XMIT_GSO_V6))) | |
3718 | return; | |
3719 | ||
3720 | if (xmit_type & XMIT_GSO_ENC_V6) | |
3721 | ipv6 = inner_ipv6_hdr(skb); | |
3722 | else /* XMIT_GSO_V6 */ | |
3723 | ipv6 = ipv6_hdr(skb); | |
3724 | ||
3725 | if (ipv6->nexthdr == NEXTHDR_IPV6) | |
3726 | *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR; | |
3727 | } | |
3728 | ||
9f6c9258 DK |
3729 | /* called with netif_tx_lock |
3730 | * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call | |
3731 | * netif_wake_queue() | |
3732 | */ | |
3733 | netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
3734 | { | |
3735 | struct bnx2x *bp = netdev_priv(dev); | |
6383c0b3 | 3736 | |
9f6c9258 | 3737 | struct netdev_queue *txq; |
6383c0b3 | 3738 | struct bnx2x_fp_txdata *txdata; |
9f6c9258 | 3739 | struct sw_tx_bd *tx_buf; |
619c5cb6 | 3740 | struct eth_tx_start_bd *tx_start_bd, *first_bd; |
9f6c9258 | 3741 | struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL; |
523224a3 | 3742 | struct eth_tx_parse_bd_e1x *pbd_e1x = NULL; |
f2e0899f | 3743 | struct eth_tx_parse_bd_e2 *pbd_e2 = NULL; |
a848ade4 | 3744 | struct eth_tx_parse_2nd_bd *pbd2 = NULL; |
2297a2da | 3745 | u32 pbd_e2_parsing_data = 0; |
9f6c9258 | 3746 | u16 pkt_prod, bd_prod; |
65565884 | 3747 | int nbd, txq_index; |
9f6c9258 DK |
3748 | dma_addr_t mapping; |
3749 | u32 xmit_type = bnx2x_xmit_type(bp, skb); | |
3750 | int i; | |
3751 | u8 hlen = 0; | |
3752 | __le16 pkt_size = 0; | |
3753 | struct ethhdr *eth; | |
3754 | u8 mac_type = UNICAST_ADDRESS; | |
3755 | ||
3756 | #ifdef BNX2X_STOP_ON_ERROR | |
3757 | if (unlikely(bp->panic)) | |
3758 | return NETDEV_TX_BUSY; | |
3759 | #endif | |
3760 | ||
6383c0b3 AE |
3761 | txq_index = skb_get_queue_mapping(skb); |
3762 | txq = netdev_get_tx_queue(dev, txq_index); | |
3763 | ||
55c11941 | 3764 | BUG_ON(txq_index >= MAX_ETH_TXQ_IDX(bp) + (CNIC_LOADED(bp) ? 1 : 0)); |
6383c0b3 | 3765 | |
65565884 | 3766 | txdata = &bp->bnx2x_txq[txq_index]; |
6383c0b3 AE |
3767 | |
3768 | /* enable this debug print to view the transmission queue being used | |
51c1a580 | 3769 | DP(NETIF_MSG_TX_QUEUED, "indices: txq %d, fp %d, txdata %d\n", |
6383c0b3 | 3770 | txq_index, fp_index, txdata_index); */ |
9f6c9258 | 3771 | |
16a5fd92 | 3772 | /* enable this debug print to view the transmission details |
51c1a580 MS |
3773 | DP(NETIF_MSG_TX_QUEUED, |
3774 | "transmitting packet cid %d fp index %d txdata_index %d tx_data ptr %p fp pointer %p\n", | |
6383c0b3 | 3775 | txdata->cid, fp_index, txdata_index, txdata, fp); */ |
9f6c9258 | 3776 | |
6383c0b3 | 3777 | if (unlikely(bnx2x_tx_avail(bp, txdata) < |
7df2dc6b DK |
3778 | skb_shinfo(skb)->nr_frags + |
3779 | BDS_PER_TX_PKT + | |
3780 | NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))) { | |
2384d6aa | 3781 | /* Handle special storage cases separately */ |
c96bdc0c DK |
3782 | if (txdata->tx_ring_size == 0) { |
3783 | struct bnx2x_eth_q_stats *q_stats = | |
3784 | bnx2x_fp_qstats(bp, txdata->parent_fp); | |
3785 | q_stats->driver_filtered_tx_pkt++; | |
3786 | dev_kfree_skb(skb); | |
3787 | return NETDEV_TX_OK; | |
3788 | } | |
2de67439 YM |
3789 | bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++; |
3790 | netif_tx_stop_queue(txq); | |
c96bdc0c | 3791 | BNX2X_ERR("BUG! Tx ring full when queue awake!\n"); |
2384d6aa | 3792 | |
9f6c9258 DK |
3793 | return NETDEV_TX_BUSY; |
3794 | } | |
3795 | ||
51c1a580 | 3796 | DP(NETIF_MSG_TX_QUEUED, |
04c46736 | 3797 | "queue[%d]: SKB: summed %x protocol %x protocol(%x,%x) gso type %x xmit_type %x len %d\n", |
6383c0b3 | 3798 | txq_index, skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr, |
04c46736 YM |
3799 | ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type, |
3800 | skb->len); | |
9f6c9258 DK |
3801 | |
3802 | eth = (struct ethhdr *)skb->data; | |
3803 | ||
3804 | /* set flag according to packet type (UNICAST_ADDRESS is default)*/ | |
3805 | if (unlikely(is_multicast_ether_addr(eth->h_dest))) { | |
3806 | if (is_broadcast_ether_addr(eth->h_dest)) | |
3807 | mac_type = BROADCAST_ADDRESS; | |
3808 | else | |
3809 | mac_type = MULTICAST_ADDRESS; | |
3810 | } | |
3811 | ||
91226790 | 3812 | #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - BDS_PER_TX_PKT) |
9f6c9258 DK |
3813 | /* First, check if we need to linearize the skb (due to FW |
3814 | restrictions). No need to check fragmentation if page size > 8K | |
3815 | (there will be no violation to FW restrictions) */ | |
3816 | if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) { | |
3817 | /* Statistics of linearization */ | |
3818 | bp->lin_cnt++; | |
3819 | if (skb_linearize(skb) != 0) { | |
51c1a580 MS |
3820 | DP(NETIF_MSG_TX_QUEUED, |
3821 | "SKB linearization failed - silently dropping this SKB\n"); | |
9f6c9258 DK |
3822 | dev_kfree_skb_any(skb); |
3823 | return NETDEV_TX_OK; | |
3824 | } | |
3825 | } | |
3826 | #endif | |
619c5cb6 VZ |
3827 | /* Map skb linear data for DMA */ |
3828 | mapping = dma_map_single(&bp->pdev->dev, skb->data, | |
3829 | skb_headlen(skb), DMA_TO_DEVICE); | |
3830 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
51c1a580 MS |
3831 | DP(NETIF_MSG_TX_QUEUED, |
3832 | "SKB mapping failed - silently dropping this SKB\n"); | |
619c5cb6 VZ |
3833 | dev_kfree_skb_any(skb); |
3834 | return NETDEV_TX_OK; | |
3835 | } | |
9f6c9258 DK |
3836 | /* |
3837 | Please read carefully. First we use one BD which we mark as start, | |
3838 | then we have a parsing info BD (used for TSO or xsum), | |
3839 | and only then we have the rest of the TSO BDs. | |
3840 | (don't forget to mark the last one as last, | |
3841 | and to unmap only AFTER you write to the BD ...) | |
3842 | And above all, all pdb sizes are in words - NOT DWORDS! | |
3843 | */ | |
3844 | ||
619c5cb6 VZ |
3845 | /* get current pkt produced now - advance it just before sending packet |
3846 | * since mapping of pages may fail and cause packet to be dropped | |
3847 | */ | |
6383c0b3 AE |
3848 | pkt_prod = txdata->tx_pkt_prod; |
3849 | bd_prod = TX_BD(txdata->tx_bd_prod); | |
9f6c9258 | 3850 | |
619c5cb6 VZ |
3851 | /* get a tx_buf and first BD |
3852 | * tx_start_bd may be changed during SPLIT, | |
3853 | * but first_bd will always stay first | |
3854 | */ | |
6383c0b3 AE |
3855 | tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; |
3856 | tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; | |
619c5cb6 | 3857 | first_bd = tx_start_bd; |
9f6c9258 DK |
3858 | |
3859 | tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; | |
f85582f8 | 3860 | |
eeed018c MK |
3861 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { |
3862 | if (!(bp->flags & TX_TIMESTAMPING_EN)) { | |
8e3020b2 | 3863 | bp->eth_stats.ptp_skip_tx_ts++; |
eeed018c MK |
3864 | BNX2X_ERR("Tx timestamping was not enabled, this packet will not be timestamped\n"); |
3865 | } else if (bp->ptp_tx_skb) { | |
8e3020b2 GP |
3866 | bp->eth_stats.ptp_skip_tx_ts++; |
3867 | netdev_err_once(bp->dev, | |
3868 | "Device supports only a single outstanding packet to timestamp, this packet won't be timestamped\n"); | |
eeed018c MK |
3869 | } else { |
3870 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
3871 | /* schedule check for Tx timestamp */ | |
3872 | bp->ptp_tx_skb = skb_get(skb); | |
3873 | bp->ptp_tx_start = jiffies; | |
3874 | schedule_work(&bp->ptp_task); | |
3875 | } | |
3876 | } | |
3877 | ||
91226790 DK |
3878 | /* header nbd: indirectly zero other flags! */ |
3879 | tx_start_bd->general_data = 1 << ETH_TX_START_BD_HDR_NBDS_SHIFT; | |
9f6c9258 DK |
3880 | |
3881 | /* remember the first BD of the packet */ | |
6383c0b3 | 3882 | tx_buf->first_bd = txdata->tx_bd_prod; |
9f6c9258 DK |
3883 | tx_buf->skb = skb; |
3884 | tx_buf->flags = 0; | |
3885 | ||
3886 | DP(NETIF_MSG_TX_QUEUED, | |
3887 | "sending pkt %u @%p next_idx %u bd %u @%p\n", | |
6383c0b3 | 3888 | pkt_prod, tx_buf, txdata->tx_pkt_prod, bd_prod, tx_start_bd); |
9f6c9258 | 3889 | |
df8a39de | 3890 | if (skb_vlan_tag_present(skb)) { |
523224a3 | 3891 | tx_start_bd->vlan_or_ethertype = |
df8a39de | 3892 | cpu_to_le16(skb_vlan_tag_get(skb)); |
523224a3 DK |
3893 | tx_start_bd->bd_flags.as_bitfield |= |
3894 | (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT); | |
dc1ba591 AE |
3895 | } else { |
3896 | /* when transmitting in a vf, start bd must hold the ethertype | |
3897 | * for fw to enforce it | |
3898 | */ | |
92f85f05 | 3899 | u16 vlan_tci = 0; |
ea36475a | 3900 | #ifndef BNX2X_STOP_ON_ERROR |
92f85f05 | 3901 | if (IS_VF(bp)) { |
ea36475a | 3902 | #endif |
92f85f05 MY |
3903 | /* Still need to consider inband vlan for enforced */ |
3904 | if (__vlan_get_tag(skb, &vlan_tci)) { | |
3905 | tx_start_bd->vlan_or_ethertype = | |
3906 | cpu_to_le16(ntohs(eth->h_proto)); | |
3907 | } else { | |
3908 | tx_start_bd->bd_flags.as_bitfield |= | |
3909 | (X_ETH_INBAND_VLAN << | |
3910 | ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT); | |
3911 | tx_start_bd->vlan_or_ethertype = | |
3912 | cpu_to_le16(vlan_tci); | |
3913 | } | |
ea36475a | 3914 | #ifndef BNX2X_STOP_ON_ERROR |
92f85f05 | 3915 | } else { |
dc1ba591 AE |
3916 | /* used by FW for packet accounting */ |
3917 | tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); | |
92f85f05 | 3918 | } |
ea36475a | 3919 | #endif |
dc1ba591 | 3920 | } |
9f6c9258 | 3921 | |
91226790 DK |
3922 | nbd = 2; /* start_bd + pbd + frags (updated when pages are mapped) */ |
3923 | ||
9f6c9258 DK |
3924 | /* turn on parsing and get a BD */ |
3925 | bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); | |
9f6c9258 | 3926 | |
93ef5c02 DK |
3927 | if (xmit_type & XMIT_CSUM) |
3928 | bnx2x_set_sbd_csum(bp, skb, tx_start_bd, xmit_type); | |
9f6c9258 | 3929 | |
619c5cb6 | 3930 | if (!CHIP_IS_E1x(bp)) { |
6383c0b3 | 3931 | pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2; |
f2e0899f | 3932 | memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); |
a848ade4 DK |
3933 | |
3934 | if (xmit_type & XMIT_CSUM_ENC) { | |
3935 | u16 global_data = 0; | |
3936 | ||
3937 | /* Set PBD in enc checksum offload case */ | |
3938 | hlen = bnx2x_set_pbd_csum_enc(bp, skb, | |
3939 | &pbd_e2_parsing_data, | |
3940 | xmit_type); | |
3941 | ||
3942 | /* turn on 2nd parsing and get a BD */ | |
3943 | bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); | |
3944 | ||
3945 | pbd2 = &txdata->tx_desc_ring[bd_prod].parse_2nd_bd; | |
3946 | ||
3947 | memset(pbd2, 0, sizeof(*pbd2)); | |
3948 | ||
3949 | pbd_e2->data.tunnel_data.ip_hdr_start_inner_w = | |
3950 | (skb_inner_network_header(skb) - | |
3951 | skb->data) >> 1; | |
3952 | ||
3953 | if (xmit_type & XMIT_GSO_ENC) | |
3954 | bnx2x_update_pbds_gso_enc(skb, pbd_e2, pbd2, | |
3955 | &global_data, | |
3956 | xmit_type); | |
3957 | ||
3958 | pbd2->global_data = cpu_to_le16(global_data); | |
3959 | ||
3960 | /* add addition parse BD indication to start BD */ | |
3961 | SET_FLAG(tx_start_bd->general_data, | |
3962 | ETH_TX_START_BD_PARSE_NBDS, 1); | |
3963 | /* set encapsulation flag in start BD */ | |
3964 | SET_FLAG(tx_start_bd->general_data, | |
3965 | ETH_TX_START_BD_TUNNEL_EXIST, 1); | |
fe26566d DK |
3966 | |
3967 | tx_buf->flags |= BNX2X_HAS_SECOND_PBD; | |
3968 | ||
a848ade4 DK |
3969 | nbd++; |
3970 | } else if (xmit_type & XMIT_CSUM) { | |
91226790 | 3971 | /* Set PBD in checksum offload case w/o encapsulation */ |
2297a2da VZ |
3972 | hlen = bnx2x_set_pbd_csum_e2(bp, skb, |
3973 | &pbd_e2_parsing_data, | |
3974 | xmit_type); | |
a848ade4 | 3975 | } |
dc1ba591 | 3976 | |
e42780b6 | 3977 | bnx2x_set_ipv6_ext_e2(skb, &pbd_e2_parsing_data, xmit_type); |
babe723d YM |
3978 | /* Add the macs to the parsing BD if this is a vf or if |
3979 | * Tx Switching is enabled. | |
3980 | */ | |
91226790 DK |
3981 | if (IS_VF(bp)) { |
3982 | /* override GRE parameters in BD */ | |
3983 | bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.src_hi, | |
3984 | &pbd_e2->data.mac_addr.src_mid, | |
3985 | &pbd_e2->data.mac_addr.src_lo, | |
619c5cb6 | 3986 | eth->h_source); |
91226790 | 3987 | |
babe723d YM |
3988 | bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.dst_hi, |
3989 | &pbd_e2->data.mac_addr.dst_mid, | |
3990 | &pbd_e2->data.mac_addr.dst_lo, | |
3991 | eth->h_dest); | |
ea36475a YM |
3992 | } else { |
3993 | if (bp->flags & TX_SWITCHING) | |
3994 | bnx2x_set_fw_mac_addr( | |
3995 | &pbd_e2->data.mac_addr.dst_hi, | |
3996 | &pbd_e2->data.mac_addr.dst_mid, | |
3997 | &pbd_e2->data.mac_addr.dst_lo, | |
3998 | eth->h_dest); | |
3999 | #ifdef BNX2X_STOP_ON_ERROR | |
4000 | /* Enforce security is always set in Stop on Error - | |
4001 | * source mac should be present in the parsing BD | |
4002 | */ | |
4003 | bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.src_hi, | |
4004 | &pbd_e2->data.mac_addr.src_mid, | |
4005 | &pbd_e2->data.mac_addr.src_lo, | |
4006 | eth->h_source); | |
4007 | #endif | |
619c5cb6 | 4008 | } |
96bed4b9 YM |
4009 | |
4010 | SET_FLAG(pbd_e2_parsing_data, | |
4011 | ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, mac_type); | |
f2e0899f | 4012 | } else { |
96bed4b9 | 4013 | u16 global_data = 0; |
6383c0b3 | 4014 | pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; |
f2e0899f DK |
4015 | memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); |
4016 | /* Set PBD in checksum offload case */ | |
4017 | if (xmit_type & XMIT_CSUM) | |
4018 | hlen = bnx2x_set_pbd_csum(bp, skb, pbd_e1x, xmit_type); | |
9f6c9258 | 4019 | |
96bed4b9 YM |
4020 | SET_FLAG(global_data, |
4021 | ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type); | |
4022 | pbd_e1x->global_data |= cpu_to_le16(global_data); | |
9f6c9258 DK |
4023 | } |
4024 | ||
f85582f8 | 4025 | /* Setup the data pointer of the first BD of the packet */ |
9f6c9258 DK |
4026 | tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); |
4027 | tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
9f6c9258 DK |
4028 | tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); |
4029 | pkt_size = tx_start_bd->nbytes; | |
4030 | ||
51c1a580 | 4031 | DP(NETIF_MSG_TX_QUEUED, |
91226790 | 4032 | "first bd @%p addr (%x:%x) nbytes %d flags %x vlan %x\n", |
9f6c9258 | 4033 | tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo, |
91226790 | 4034 | le16_to_cpu(tx_start_bd->nbytes), |
523224a3 DK |
4035 | tx_start_bd->bd_flags.as_bitfield, |
4036 | le16_to_cpu(tx_start_bd->vlan_or_ethertype)); | |
9f6c9258 DK |
4037 | |
4038 | if (xmit_type & XMIT_GSO) { | |
4039 | ||
4040 | DP(NETIF_MSG_TX_QUEUED, | |
4041 | "TSO packet len %d hlen %d total len %d tso size %d\n", | |
4042 | skb->len, hlen, skb_headlen(skb), | |
4043 | skb_shinfo(skb)->gso_size); | |
4044 | ||
4045 | tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO; | |
4046 | ||
91226790 DK |
4047 | if (unlikely(skb_headlen(skb) > hlen)) { |
4048 | nbd++; | |
6383c0b3 AE |
4049 | bd_prod = bnx2x_tx_split(bp, txdata, tx_buf, |
4050 | &tx_start_bd, hlen, | |
91226790 DK |
4051 | bd_prod); |
4052 | } | |
619c5cb6 | 4053 | if (!CHIP_IS_E1x(bp)) |
e42780b6 DK |
4054 | pbd_e2_parsing_data |= |
4055 | (skb_shinfo(skb)->gso_size << | |
4056 | ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) & | |
4057 | ETH_TX_PARSE_BD_E2_LSO_MSS; | |
f2e0899f | 4058 | else |
e42780b6 | 4059 | bnx2x_set_pbd_gso(skb, pbd_e1x, xmit_type); |
9f6c9258 | 4060 | } |
2297a2da VZ |
4061 | |
4062 | /* Set the PBD's parsing_data field if not zero | |
4063 | * (for the chips newer than 57711). | |
4064 | */ | |
4065 | if (pbd_e2_parsing_data) | |
4066 | pbd_e2->parsing_data = cpu_to_le32(pbd_e2_parsing_data); | |
4067 | ||
9f6c9258 DK |
4068 | tx_data_bd = (struct eth_tx_bd *)tx_start_bd; |
4069 | ||
f85582f8 | 4070 | /* Handle fragmented skb */ |
9f6c9258 DK |
4071 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
4072 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
4073 | ||
9e903e08 ED |
4074 | mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, |
4075 | skb_frag_size(frag), DMA_TO_DEVICE); | |
619c5cb6 | 4076 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { |
2df1a70a | 4077 | unsigned int pkts_compl = 0, bytes_compl = 0; |
619c5cb6 | 4078 | |
51c1a580 MS |
4079 | DP(NETIF_MSG_TX_QUEUED, |
4080 | "Unable to map page - dropping packet...\n"); | |
619c5cb6 VZ |
4081 | |
4082 | /* we need unmap all buffers already mapped | |
4083 | * for this SKB; | |
4084 | * first_bd->nbd need to be properly updated | |
4085 | * before call to bnx2x_free_tx_pkt | |
4086 | */ | |
4087 | first_bd->nbd = cpu_to_le16(nbd); | |
6383c0b3 | 4088 | bnx2x_free_tx_pkt(bp, txdata, |
2df1a70a TH |
4089 | TX_BD(txdata->tx_pkt_prod), |
4090 | &pkts_compl, &bytes_compl); | |
619c5cb6 VZ |
4091 | return NETDEV_TX_OK; |
4092 | } | |
4093 | ||
9f6c9258 | 4094 | bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); |
6383c0b3 | 4095 | tx_data_bd = &txdata->tx_desc_ring[bd_prod].reg_bd; |
9f6c9258 | 4096 | if (total_pkt_bd == NULL) |
6383c0b3 | 4097 | total_pkt_bd = &txdata->tx_desc_ring[bd_prod].reg_bd; |
9f6c9258 | 4098 | |
9f6c9258 DK |
4099 | tx_data_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); |
4100 | tx_data_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
9e903e08 ED |
4101 | tx_data_bd->nbytes = cpu_to_le16(skb_frag_size(frag)); |
4102 | le16_add_cpu(&pkt_size, skb_frag_size(frag)); | |
619c5cb6 | 4103 | nbd++; |
9f6c9258 DK |
4104 | |
4105 | DP(NETIF_MSG_TX_QUEUED, | |
4106 | "frag %d bd @%p addr (%x:%x) nbytes %d\n", | |
4107 | i, tx_data_bd, tx_data_bd->addr_hi, tx_data_bd->addr_lo, | |
4108 | le16_to_cpu(tx_data_bd->nbytes)); | |
4109 | } | |
4110 | ||
4111 | DP(NETIF_MSG_TX_QUEUED, "last bd @%p\n", tx_data_bd); | |
4112 | ||
619c5cb6 VZ |
4113 | /* update with actual num BDs */ |
4114 | first_bd->nbd = cpu_to_le16(nbd); | |
4115 | ||
9f6c9258 DK |
4116 | bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); |
4117 | ||
4118 | /* now send a tx doorbell, counting the next BD | |
4119 | * if the packet contains or ends with it | |
4120 | */ | |
4121 | if (TX_BD_POFF(bd_prod) < nbd) | |
4122 | nbd++; | |
4123 | ||
619c5cb6 VZ |
4124 | /* total_pkt_bytes should be set on the first data BD if |
4125 | * it's not an LSO packet and there is more than one | |
4126 | * data BD. In this case pkt_size is limited by an MTU value. | |
4127 | * However we prefer to set it for an LSO packet (while we don't | |
4128 | * have to) in order to save some CPU cycles in a none-LSO | |
4129 | * case, when we much more care about them. | |
4130 | */ | |
9f6c9258 DK |
4131 | if (total_pkt_bd != NULL) |
4132 | total_pkt_bd->total_pkt_bytes = pkt_size; | |
4133 | ||
523224a3 | 4134 | if (pbd_e1x) |
9f6c9258 | 4135 | DP(NETIF_MSG_TX_QUEUED, |
51c1a580 | 4136 | "PBD (E1X) @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u tcp_flags %x xsum %x seq %u hlen %u\n", |
523224a3 DK |
4137 | pbd_e1x, pbd_e1x->global_data, pbd_e1x->ip_hlen_w, |
4138 | pbd_e1x->ip_id, pbd_e1x->lso_mss, pbd_e1x->tcp_flags, | |
4139 | pbd_e1x->tcp_pseudo_csum, pbd_e1x->tcp_send_seq, | |
4140 | le16_to_cpu(pbd_e1x->total_hlen_w)); | |
f2e0899f DK |
4141 | if (pbd_e2) |
4142 | DP(NETIF_MSG_TX_QUEUED, | |
4143 | "PBD (E2) @%p dst %x %x %x src %x %x %x parsing_data %x\n", | |
91226790 DK |
4144 | pbd_e2, |
4145 | pbd_e2->data.mac_addr.dst_hi, | |
4146 | pbd_e2->data.mac_addr.dst_mid, | |
4147 | pbd_e2->data.mac_addr.dst_lo, | |
4148 | pbd_e2->data.mac_addr.src_hi, | |
4149 | pbd_e2->data.mac_addr.src_mid, | |
4150 | pbd_e2->data.mac_addr.src_lo, | |
f2e0899f | 4151 | pbd_e2->parsing_data); |
9f6c9258 DK |
4152 | DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod); |
4153 | ||
2df1a70a TH |
4154 | netdev_tx_sent_queue(txq, skb->len); |
4155 | ||
8373c57d WB |
4156 | skb_tx_timestamp(skb); |
4157 | ||
6383c0b3 | 4158 | txdata->tx_pkt_prod++; |
9f6c9258 DK |
4159 | /* |
4160 | * Make sure that the BD data is updated before updating the producer | |
4161 | * since FW might read the BD right after the producer is updated. | |
4162 | * This is only applicable for weak-ordered memory model archs such | |
4163 | * as IA-64. The following barrier is also mandatory since FW will | |
4164 | * assumes packets must have BDs. | |
4165 | */ | |
4166 | wmb(); | |
4167 | ||
6383c0b3 | 4168 | txdata->tx_db.data.prod += nbd; |
9f6c9258 | 4169 | barrier(); |
f85582f8 | 4170 | |
6383c0b3 | 4171 | DOORBELL(bp, txdata->cid, txdata->tx_db.raw); |
9f6c9258 DK |
4172 | |
4173 | mmiowb(); | |
4174 | ||
6383c0b3 | 4175 | txdata->tx_bd_prod += nbd; |
9f6c9258 | 4176 | |
7df2dc6b | 4177 | if (unlikely(bnx2x_tx_avail(bp, txdata) < MAX_DESC_PER_TX_PKT)) { |
9f6c9258 DK |
4178 | netif_tx_stop_queue(txq); |
4179 | ||
4180 | /* paired memory barrier is in bnx2x_tx_int(), we have to keep | |
4181 | * ordering of set_bit() in netif_tx_stop_queue() and read of | |
4182 | * fp->bd_tx_cons */ | |
4183 | smp_mb(); | |
4184 | ||
15192a8c | 4185 | bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++; |
7df2dc6b | 4186 | if (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT) |
9f6c9258 DK |
4187 | netif_tx_wake_queue(txq); |
4188 | } | |
6383c0b3 | 4189 | txdata->tx_pkt++; |
9f6c9258 DK |
4190 | |
4191 | return NETDEV_TX_OK; | |
4192 | } | |
f85582f8 | 4193 | |
230d00eb YM |
4194 | void bnx2x_get_c2s_mapping(struct bnx2x *bp, u8 *c2s_map, u8 *c2s_default) |
4195 | { | |
4196 | int mfw_vn = BP_FW_MB_IDX(bp); | |
4197 | u32 tmp; | |
4198 | ||
4199 | /* If the shmem shouldn't affect configuration, reflect */ | |
4200 | if (!IS_MF_BD(bp)) { | |
4201 | int i; | |
4202 | ||
4203 | for (i = 0; i < BNX2X_MAX_PRIORITY; i++) | |
4204 | c2s_map[i] = i; | |
4205 | *c2s_default = 0; | |
4206 | ||
4207 | return; | |
4208 | } | |
4209 | ||
4210 | tmp = SHMEM2_RD(bp, c2s_pcp_map_lower[mfw_vn]); | |
4211 | tmp = (__force u32)be32_to_cpu((__force __be32)tmp); | |
4212 | c2s_map[0] = tmp & 0xff; | |
4213 | c2s_map[1] = (tmp >> 8) & 0xff; | |
4214 | c2s_map[2] = (tmp >> 16) & 0xff; | |
4215 | c2s_map[3] = (tmp >> 24) & 0xff; | |
4216 | ||
4217 | tmp = SHMEM2_RD(bp, c2s_pcp_map_upper[mfw_vn]); | |
4218 | tmp = (__force u32)be32_to_cpu((__force __be32)tmp); | |
4219 | c2s_map[4] = tmp & 0xff; | |
4220 | c2s_map[5] = (tmp >> 8) & 0xff; | |
4221 | c2s_map[6] = (tmp >> 16) & 0xff; | |
4222 | c2s_map[7] = (tmp >> 24) & 0xff; | |
4223 | ||
4224 | tmp = SHMEM2_RD(bp, c2s_pcp_map_default[mfw_vn]); | |
4225 | tmp = (__force u32)be32_to_cpu((__force __be32)tmp); | |
4226 | *c2s_default = (tmp >> (8 * mfw_vn)) & 0xff; | |
4227 | } | |
4228 | ||
6383c0b3 AE |
4229 | /** |
4230 | * bnx2x_setup_tc - routine to configure net_device for multi tc | |
4231 | * | |
4232 | * @netdev: net device to configure | |
4233 | * @tc: number of traffic classes to enable | |
4234 | * | |
4235 | * callback connected to the ndo_setup_tc function pointer | |
4236 | */ | |
4237 | int bnx2x_setup_tc(struct net_device *dev, u8 num_tc) | |
4238 | { | |
6383c0b3 | 4239 | struct bnx2x *bp = netdev_priv(dev); |
230d00eb YM |
4240 | u8 c2s_map[BNX2X_MAX_PRIORITY], c2s_def; |
4241 | int cos, prio, count, offset; | |
6383c0b3 AE |
4242 | |
4243 | /* setup tc must be called under rtnl lock */ | |
4244 | ASSERT_RTNL(); | |
4245 | ||
16a5fd92 | 4246 | /* no traffic classes requested. Aborting */ |
6383c0b3 AE |
4247 | if (!num_tc) { |
4248 | netdev_reset_tc(dev); | |
4249 | return 0; | |
4250 | } | |
4251 | ||
4252 | /* requested to support too many traffic classes */ | |
4253 | if (num_tc > bp->max_cos) { | |
6bf07b8e | 4254 | BNX2X_ERR("support for too many traffic classes requested: %d. Max supported is %d\n", |
51c1a580 | 4255 | num_tc, bp->max_cos); |
6383c0b3 AE |
4256 | return -EINVAL; |
4257 | } | |
4258 | ||
4259 | /* declare amount of supported traffic classes */ | |
4260 | if (netdev_set_num_tc(dev, num_tc)) { | |
51c1a580 | 4261 | BNX2X_ERR("failed to declare %d traffic classes\n", num_tc); |
6383c0b3 AE |
4262 | return -EINVAL; |
4263 | } | |
4264 | ||
230d00eb YM |
4265 | bnx2x_get_c2s_mapping(bp, c2s_map, &c2s_def); |
4266 | ||
6383c0b3 AE |
4267 | /* configure priority to traffic class mapping */ |
4268 | for (prio = 0; prio < BNX2X_MAX_PRIORITY; prio++) { | |
230d00eb YM |
4269 | int outer_prio = c2s_map[prio]; |
4270 | ||
4271 | netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[outer_prio]); | |
51c1a580 MS |
4272 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
4273 | "mapping priority %d to tc %d\n", | |
230d00eb | 4274 | outer_prio, bp->prio_to_cos[outer_prio]); |
6383c0b3 AE |
4275 | } |
4276 | ||
16a5fd92 | 4277 | /* Use this configuration to differentiate tc0 from other COSes |
6383c0b3 AE |
4278 | This can be used for ets or pfc, and save the effort of setting |
4279 | up a multio class queue disc or negotiating DCBX with a switch | |
4280 | netdev_set_prio_tc_map(dev, 0, 0); | |
94f05b0f | 4281 | DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", 0, 0); |
6383c0b3 AE |
4282 | for (prio = 1; prio < 16; prio++) { |
4283 | netdev_set_prio_tc_map(dev, prio, 1); | |
94f05b0f | 4284 | DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", prio, 1); |
6383c0b3 AE |
4285 | } */ |
4286 | ||
4287 | /* configure traffic class to transmission queue mapping */ | |
4288 | for (cos = 0; cos < bp->max_cos; cos++) { | |
4289 | count = BNX2X_NUM_ETH_QUEUES(bp); | |
65565884 | 4290 | offset = cos * BNX2X_NUM_NON_CNIC_QUEUES(bp); |
6383c0b3 | 4291 | netdev_set_tc_queue(dev, cos, count, offset); |
51c1a580 MS |
4292 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
4293 | "mapping tc %d to offset %d count %d\n", | |
6383c0b3 AE |
4294 | cos, offset, count); |
4295 | } | |
4296 | ||
4297 | return 0; | |
4298 | } | |
4299 | ||
2572ac53 | 4300 | int __bnx2x_setup_tc(struct net_device *dev, enum tc_setup_type type, |
de4784ca | 4301 | void *type_data) |
e4c6734e | 4302 | { |
de4784ca JP |
4303 | struct tc_mqprio_qopt *mqprio = type_data; |
4304 | ||
575ed7d3 | 4305 | if (type != TC_SETUP_QDISC_MQPRIO) |
38cf0426 | 4306 | return -EOPNOTSUPP; |
56f36acd | 4307 | |
de4784ca | 4308 | mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; |
56f36acd | 4309 | |
de4784ca | 4310 | return bnx2x_setup_tc(dev, mqprio->num_tc); |
e4c6734e JF |
4311 | } |
4312 | ||
9f6c9258 DK |
4313 | /* called with rtnl_lock */ |
4314 | int bnx2x_change_mac_addr(struct net_device *dev, void *p) | |
4315 | { | |
4316 | struct sockaddr *addr = p; | |
4317 | struct bnx2x *bp = netdev_priv(dev); | |
619c5cb6 | 4318 | int rc = 0; |
9f6c9258 | 4319 | |
2e98ffc2 | 4320 | if (!is_valid_ether_addr(addr->sa_data)) { |
51c1a580 | 4321 | BNX2X_ERR("Requested MAC address is not valid\n"); |
614c76df | 4322 | return -EINVAL; |
51c1a580 | 4323 | } |
614c76df | 4324 | |
2e98ffc2 DK |
4325 | if (IS_MF_STORAGE_ONLY(bp)) { |
4326 | BNX2X_ERR("Can't change address on STORAGE ONLY function\n"); | |
9f6c9258 | 4327 | return -EINVAL; |
51c1a580 | 4328 | } |
9f6c9258 | 4329 | |
619c5cb6 VZ |
4330 | if (netif_running(dev)) { |
4331 | rc = bnx2x_set_eth_mac(bp, false); | |
4332 | if (rc) | |
4333 | return rc; | |
4334 | } | |
4335 | ||
9f6c9258 | 4336 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
619c5cb6 | 4337 | |
523224a3 | 4338 | if (netif_running(dev)) |
619c5cb6 | 4339 | rc = bnx2x_set_eth_mac(bp, true); |
9f6c9258 | 4340 | |
230d00eb YM |
4341 | if (IS_PF(bp) && SHMEM2_HAS(bp, curr_cfg)) |
4342 | SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS); | |
4343 | ||
619c5cb6 | 4344 | return rc; |
9f6c9258 DK |
4345 | } |
4346 | ||
b3b83c3f DK |
4347 | static void bnx2x_free_fp_mem_at(struct bnx2x *bp, int fp_index) |
4348 | { | |
4349 | union host_hc_status_block *sb = &bnx2x_fp(bp, fp_index, status_blk); | |
4350 | struct bnx2x_fastpath *fp = &bp->fp[fp_index]; | |
6383c0b3 | 4351 | u8 cos; |
b3b83c3f DK |
4352 | |
4353 | /* Common */ | |
55c11941 | 4354 | |
b3b83c3f DK |
4355 | if (IS_FCOE_IDX(fp_index)) { |
4356 | memset(sb, 0, sizeof(union host_hc_status_block)); | |
4357 | fp->status_blk_mapping = 0; | |
b3b83c3f | 4358 | } else { |
b3b83c3f | 4359 | /* status blocks */ |
619c5cb6 | 4360 | if (!CHIP_IS_E1x(bp)) |
b3b83c3f DK |
4361 | BNX2X_PCI_FREE(sb->e2_sb, |
4362 | bnx2x_fp(bp, fp_index, | |
4363 | status_blk_mapping), | |
4364 | sizeof(struct host_hc_status_block_e2)); | |
4365 | else | |
4366 | BNX2X_PCI_FREE(sb->e1x_sb, | |
4367 | bnx2x_fp(bp, fp_index, | |
4368 | status_blk_mapping), | |
4369 | sizeof(struct host_hc_status_block_e1x)); | |
b3b83c3f | 4370 | } |
55c11941 | 4371 | |
b3b83c3f DK |
4372 | /* Rx */ |
4373 | if (!skip_rx_queue(bp, fp_index)) { | |
4374 | bnx2x_free_rx_bds(fp); | |
4375 | ||
4376 | /* fastpath rx rings: rx_buf rx_desc rx_comp */ | |
4377 | BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_buf_ring)); | |
4378 | BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_desc_ring), | |
4379 | bnx2x_fp(bp, fp_index, rx_desc_mapping), | |
4380 | sizeof(struct eth_rx_bd) * NUM_RX_BD); | |
4381 | ||
4382 | BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_comp_ring), | |
4383 | bnx2x_fp(bp, fp_index, rx_comp_mapping), | |
4384 | sizeof(struct eth_fast_path_rx_cqe) * | |
4385 | NUM_RCQ_BD); | |
4386 | ||
4387 | /* SGE ring */ | |
4388 | BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_page_ring)); | |
4389 | BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_sge_ring), | |
4390 | bnx2x_fp(bp, fp_index, rx_sge_mapping), | |
4391 | BCM_PAGE_SIZE * NUM_RX_SGE_PAGES); | |
4392 | } | |
4393 | ||
4394 | /* Tx */ | |
4395 | if (!skip_tx_queue(bp, fp_index)) { | |
4396 | /* fastpath tx rings: tx_buf tx_desc */ | |
6383c0b3 | 4397 | for_each_cos_in_tx_queue(fp, cos) { |
65565884 | 4398 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
6383c0b3 | 4399 | |
51c1a580 | 4400 | DP(NETIF_MSG_IFDOWN, |
94f05b0f | 4401 | "freeing tx memory of fp %d cos %d cid %d\n", |
6383c0b3 AE |
4402 | fp_index, cos, txdata->cid); |
4403 | ||
4404 | BNX2X_FREE(txdata->tx_buf_ring); | |
4405 | BNX2X_PCI_FREE(txdata->tx_desc_ring, | |
4406 | txdata->tx_desc_mapping, | |
4407 | sizeof(union eth_tx_bd_types) * NUM_TX_BD); | |
4408 | } | |
b3b83c3f DK |
4409 | } |
4410 | /* end of fastpath */ | |
4411 | } | |
4412 | ||
a8f47eb7 | 4413 | static void bnx2x_free_fp_mem_cnic(struct bnx2x *bp) |
55c11941 MS |
4414 | { |
4415 | int i; | |
4416 | for_each_cnic_queue(bp, i) | |
4417 | bnx2x_free_fp_mem_at(bp, i); | |
4418 | } | |
4419 | ||
b3b83c3f DK |
4420 | void bnx2x_free_fp_mem(struct bnx2x *bp) |
4421 | { | |
4422 | int i; | |
55c11941 | 4423 | for_each_eth_queue(bp, i) |
b3b83c3f DK |
4424 | bnx2x_free_fp_mem_at(bp, i); |
4425 | } | |
4426 | ||
1191cb83 | 4427 | static void set_sb_shortcuts(struct bnx2x *bp, int index) |
b3b83c3f DK |
4428 | { |
4429 | union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk); | |
619c5cb6 | 4430 | if (!CHIP_IS_E1x(bp)) { |
b3b83c3f DK |
4431 | bnx2x_fp(bp, index, sb_index_values) = |
4432 | (__le16 *)status_blk.e2_sb->sb.index_values; | |
4433 | bnx2x_fp(bp, index, sb_running_index) = | |
4434 | (__le16 *)status_blk.e2_sb->sb.running_index; | |
4435 | } else { | |
4436 | bnx2x_fp(bp, index, sb_index_values) = | |
4437 | (__le16 *)status_blk.e1x_sb->sb.index_values; | |
4438 | bnx2x_fp(bp, index, sb_running_index) = | |
4439 | (__le16 *)status_blk.e1x_sb->sb.running_index; | |
4440 | } | |
4441 | } | |
4442 | ||
1191cb83 ED |
4443 | /* Returns the number of actually allocated BDs */ |
4444 | static int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp, | |
4445 | int rx_ring_size) | |
4446 | { | |
4447 | struct bnx2x *bp = fp->bp; | |
4448 | u16 ring_prod, cqe_ring_prod; | |
4449 | int i, failure_cnt = 0; | |
4450 | ||
4451 | fp->rx_comp_cons = 0; | |
4452 | cqe_ring_prod = ring_prod = 0; | |
4453 | ||
4454 | /* This routine is called only during fo init so | |
4455 | * fp->eth_q_stats.rx_skb_alloc_failed = 0 | |
4456 | */ | |
4457 | for (i = 0; i < rx_ring_size; i++) { | |
996dedba | 4458 | if (bnx2x_alloc_rx_data(bp, fp, ring_prod, GFP_KERNEL) < 0) { |
1191cb83 ED |
4459 | failure_cnt++; |
4460 | continue; | |
4461 | } | |
4462 | ring_prod = NEXT_RX_IDX(ring_prod); | |
4463 | cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod); | |
4464 | WARN_ON(ring_prod <= (i - failure_cnt)); | |
4465 | } | |
4466 | ||
4467 | if (failure_cnt) | |
4468 | BNX2X_ERR("was only able to allocate %d rx skbs on queue[%d]\n", | |
4469 | i - failure_cnt, fp->index); | |
4470 | ||
4471 | fp->rx_bd_prod = ring_prod; | |
4472 | /* Limit the CQE producer by the CQE ring size */ | |
4473 | fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT, | |
4474 | cqe_ring_prod); | |
1191cb83 | 4475 | |
15192a8c | 4476 | bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed += failure_cnt; |
1191cb83 ED |
4477 | |
4478 | return i - failure_cnt; | |
4479 | } | |
4480 | ||
4481 | static void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp) | |
4482 | { | |
4483 | int i; | |
4484 | ||
4485 | for (i = 1; i <= NUM_RCQ_RINGS; i++) { | |
4486 | struct eth_rx_cqe_next_page *nextpg; | |
4487 | ||
4488 | nextpg = (struct eth_rx_cqe_next_page *) | |
4489 | &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1]; | |
4490 | nextpg->addr_hi = | |
4491 | cpu_to_le32(U64_HI(fp->rx_comp_mapping + | |
4492 | BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); | |
4493 | nextpg->addr_lo = | |
4494 | cpu_to_le32(U64_LO(fp->rx_comp_mapping + | |
4495 | BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); | |
4496 | } | |
4497 | } | |
4498 | ||
b3b83c3f DK |
4499 | static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index) |
4500 | { | |
4501 | union host_hc_status_block *sb; | |
4502 | struct bnx2x_fastpath *fp = &bp->fp[index]; | |
4503 | int ring_size = 0; | |
6383c0b3 | 4504 | u8 cos; |
c2188952 | 4505 | int rx_ring_size = 0; |
b3b83c3f | 4506 | |
2e98ffc2 | 4507 | if (!bp->rx_ring_size && IS_MF_STORAGE_ONLY(bp)) { |
614c76df DK |
4508 | rx_ring_size = MIN_RX_SIZE_NONTPA; |
4509 | bp->rx_ring_size = rx_ring_size; | |
55c11941 | 4510 | } else if (!bp->rx_ring_size) { |
c2188952 VZ |
4511 | rx_ring_size = MAX_RX_AVAIL/BNX2X_NUM_RX_QUEUES(bp); |
4512 | ||
065f8b92 YM |
4513 | if (CHIP_IS_E3(bp)) { |
4514 | u32 cfg = SHMEM_RD(bp, | |
4515 | dev_info.port_hw_config[BP_PORT(bp)]. | |
4516 | default_cfg); | |
4517 | ||
4518 | /* Decrease ring size for 1G functions */ | |
4519 | if ((cfg & PORT_HW_CFG_NET_SERDES_IF_MASK) == | |
4520 | PORT_HW_CFG_NET_SERDES_IF_SGMII) | |
4521 | rx_ring_size /= 10; | |
4522 | } | |
d760fc37 | 4523 | |
c2188952 VZ |
4524 | /* allocate at least number of buffers required by FW */ |
4525 | rx_ring_size = max_t(int, bp->disable_tpa ? MIN_RX_SIZE_NONTPA : | |
4526 | MIN_RX_SIZE_TPA, rx_ring_size); | |
4527 | ||
4528 | bp->rx_ring_size = rx_ring_size; | |
614c76df | 4529 | } else /* if rx_ring_size specified - use it */ |
c2188952 | 4530 | rx_ring_size = bp->rx_ring_size; |
b3b83c3f | 4531 | |
04c46736 YM |
4532 | DP(BNX2X_MSG_SP, "calculated rx_ring_size %d\n", rx_ring_size); |
4533 | ||
b3b83c3f DK |
4534 | /* Common */ |
4535 | sb = &bnx2x_fp(bp, index, status_blk); | |
55c11941 | 4536 | |
b3b83c3f | 4537 | if (!IS_FCOE_IDX(index)) { |
b3b83c3f | 4538 | /* status blocks */ |
cd2b0389 JP |
4539 | if (!CHIP_IS_E1x(bp)) { |
4540 | sb->e2_sb = BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, status_blk_mapping), | |
4541 | sizeof(struct host_hc_status_block_e2)); | |
4542 | if (!sb->e2_sb) | |
4543 | goto alloc_mem_err; | |
4544 | } else { | |
4545 | sb->e1x_sb = BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, status_blk_mapping), | |
4546 | sizeof(struct host_hc_status_block_e1x)); | |
4547 | if (!sb->e1x_sb) | |
4548 | goto alloc_mem_err; | |
4549 | } | |
b3b83c3f | 4550 | } |
8eef2af1 DK |
4551 | |
4552 | /* FCoE Queue uses Default SB and doesn't ACK the SB, thus no need to | |
4553 | * set shortcuts for it. | |
4554 | */ | |
4555 | if (!IS_FCOE_IDX(index)) | |
4556 | set_sb_shortcuts(bp, index); | |
b3b83c3f DK |
4557 | |
4558 | /* Tx */ | |
4559 | if (!skip_tx_queue(bp, index)) { | |
4560 | /* fastpath tx rings: tx_buf tx_desc */ | |
6383c0b3 | 4561 | for_each_cos_in_tx_queue(fp, cos) { |
65565884 | 4562 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
6383c0b3 | 4563 | |
51c1a580 MS |
4564 | DP(NETIF_MSG_IFUP, |
4565 | "allocating tx memory of fp %d cos %d\n", | |
6383c0b3 AE |
4566 | index, cos); |
4567 | ||
cd2b0389 JP |
4568 | txdata->tx_buf_ring = kcalloc(NUM_TX_BD, |
4569 | sizeof(struct sw_tx_bd), | |
4570 | GFP_KERNEL); | |
4571 | if (!txdata->tx_buf_ring) | |
4572 | goto alloc_mem_err; | |
4573 | txdata->tx_desc_ring = BNX2X_PCI_ALLOC(&txdata->tx_desc_mapping, | |
4574 | sizeof(union eth_tx_bd_types) * NUM_TX_BD); | |
4575 | if (!txdata->tx_desc_ring) | |
4576 | goto alloc_mem_err; | |
6383c0b3 | 4577 | } |
b3b83c3f DK |
4578 | } |
4579 | ||
4580 | /* Rx */ | |
4581 | if (!skip_rx_queue(bp, index)) { | |
4582 | /* fastpath rx rings: rx_buf rx_desc rx_comp */ | |
cd2b0389 JP |
4583 | bnx2x_fp(bp, index, rx_buf_ring) = |
4584 | kcalloc(NUM_RX_BD, sizeof(struct sw_rx_bd), GFP_KERNEL); | |
4585 | if (!bnx2x_fp(bp, index, rx_buf_ring)) | |
4586 | goto alloc_mem_err; | |
4587 | bnx2x_fp(bp, index, rx_desc_ring) = | |
4588 | BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, rx_desc_mapping), | |
4589 | sizeof(struct eth_rx_bd) * NUM_RX_BD); | |
4590 | if (!bnx2x_fp(bp, index, rx_desc_ring)) | |
4591 | goto alloc_mem_err; | |
b3b83c3f | 4592 | |
75b29459 | 4593 | /* Seed all CQEs by 1s */ |
cd2b0389 JP |
4594 | bnx2x_fp(bp, index, rx_comp_ring) = |
4595 | BNX2X_PCI_FALLOC(&bnx2x_fp(bp, index, rx_comp_mapping), | |
4596 | sizeof(struct eth_fast_path_rx_cqe) * NUM_RCQ_BD); | |
4597 | if (!bnx2x_fp(bp, index, rx_comp_ring)) | |
4598 | goto alloc_mem_err; | |
b3b83c3f DK |
4599 | |
4600 | /* SGE ring */ | |
cd2b0389 JP |
4601 | bnx2x_fp(bp, index, rx_page_ring) = |
4602 | kcalloc(NUM_RX_SGE, sizeof(struct sw_rx_page), | |
4603 | GFP_KERNEL); | |
4604 | if (!bnx2x_fp(bp, index, rx_page_ring)) | |
4605 | goto alloc_mem_err; | |
4606 | bnx2x_fp(bp, index, rx_sge_ring) = | |
4607 | BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, rx_sge_mapping), | |
4608 | BCM_PAGE_SIZE * NUM_RX_SGE_PAGES); | |
4609 | if (!bnx2x_fp(bp, index, rx_sge_ring)) | |
4610 | goto alloc_mem_err; | |
b3b83c3f DK |
4611 | /* RX BD ring */ |
4612 | bnx2x_set_next_page_rx_bd(fp); | |
4613 | ||
4614 | /* CQ ring */ | |
4615 | bnx2x_set_next_page_rx_cq(fp); | |
4616 | ||
4617 | /* BDs */ | |
4618 | ring_size = bnx2x_alloc_rx_bds(fp, rx_ring_size); | |
4619 | if (ring_size < rx_ring_size) | |
4620 | goto alloc_mem_err; | |
4621 | } | |
4622 | ||
4623 | return 0; | |
4624 | ||
4625 | /* handles low memory cases */ | |
4626 | alloc_mem_err: | |
4627 | BNX2X_ERR("Unable to allocate full memory for queue %d (size %d)\n", | |
4628 | index, ring_size); | |
4629 | /* FW will drop all packets if queue is not big enough, | |
4630 | * In these cases we disable the queue | |
6383c0b3 | 4631 | * Min size is different for OOO, TPA and non-TPA queues |
b3b83c3f | 4632 | */ |
7e6b4d44 | 4633 | if (ring_size < (fp->mode == TPA_MODE_DISABLED ? |
eb722d7a | 4634 | MIN_RX_SIZE_NONTPA : MIN_RX_SIZE_TPA)) { |
b3b83c3f DK |
4635 | /* release memory allocated for this queue */ |
4636 | bnx2x_free_fp_mem_at(bp, index); | |
4637 | return -ENOMEM; | |
4638 | } | |
4639 | return 0; | |
4640 | } | |
4641 | ||
a8f47eb7 | 4642 | static int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp) |
55c11941 MS |
4643 | { |
4644 | if (!NO_FCOE(bp)) | |
4645 | /* FCoE */ | |
4646 | if (bnx2x_alloc_fp_mem_at(bp, FCOE_IDX(bp))) | |
4647 | /* we will fail load process instead of mark | |
4648 | * NO_FCOE_FLAG | |
4649 | */ | |
4650 | return -ENOMEM; | |
4651 | ||
4652 | return 0; | |
4653 | } | |
4654 | ||
a8f47eb7 | 4655 | static int bnx2x_alloc_fp_mem(struct bnx2x *bp) |
b3b83c3f DK |
4656 | { |
4657 | int i; | |
4658 | ||
55c11941 MS |
4659 | /* 1. Allocate FP for leading - fatal if error |
4660 | * 2. Allocate RSS - fix number of queues if error | |
b3b83c3f DK |
4661 | */ |
4662 | ||
4663 | /* leading */ | |
4664 | if (bnx2x_alloc_fp_mem_at(bp, 0)) | |
4665 | return -ENOMEM; | |
6383c0b3 | 4666 | |
b3b83c3f DK |
4667 | /* RSS */ |
4668 | for_each_nondefault_eth_queue(bp, i) | |
4669 | if (bnx2x_alloc_fp_mem_at(bp, i)) | |
4670 | break; | |
4671 | ||
4672 | /* handle memory failures */ | |
4673 | if (i != BNX2X_NUM_ETH_QUEUES(bp)) { | |
4674 | int delta = BNX2X_NUM_ETH_QUEUES(bp) - i; | |
4675 | ||
4676 | WARN_ON(delta < 0); | |
4864a16a | 4677 | bnx2x_shrink_eth_fp(bp, delta); |
55c11941 MS |
4678 | if (CNIC_SUPPORT(bp)) |
4679 | /* move non eth FPs next to last eth FP | |
4680 | * must be done in that order | |
4681 | * FCOE_IDX < FWD_IDX < OOO_IDX | |
4682 | */ | |
b3b83c3f | 4683 | |
55c11941 MS |
4684 | /* move FCoE fp even NO_FCOE_FLAG is on */ |
4685 | bnx2x_move_fp(bp, FCOE_IDX(bp), FCOE_IDX(bp) - delta); | |
4686 | bp->num_ethernet_queues -= delta; | |
4687 | bp->num_queues = bp->num_ethernet_queues + | |
4688 | bp->num_cnic_queues; | |
b3b83c3f DK |
4689 | BNX2X_ERR("Adjusted num of queues from %d to %d\n", |
4690 | bp->num_queues + delta, bp->num_queues); | |
4691 | } | |
4692 | ||
4693 | return 0; | |
4694 | } | |
d6214d7a | 4695 | |
523224a3 DK |
4696 | void bnx2x_free_mem_bp(struct bnx2x *bp) |
4697 | { | |
c3146eb6 DK |
4698 | int i; |
4699 | ||
4700 | for (i = 0; i < bp->fp_array_size; i++) | |
4701 | kfree(bp->fp[i].tpa_info); | |
523224a3 | 4702 | kfree(bp->fp); |
15192a8c BW |
4703 | kfree(bp->sp_objs); |
4704 | kfree(bp->fp_stats); | |
65565884 | 4705 | kfree(bp->bnx2x_txq); |
523224a3 DK |
4706 | kfree(bp->msix_table); |
4707 | kfree(bp->ilt); | |
4708 | } | |
4709 | ||
0329aba1 | 4710 | int bnx2x_alloc_mem_bp(struct bnx2x *bp) |
523224a3 DK |
4711 | { |
4712 | struct bnx2x_fastpath *fp; | |
4713 | struct msix_entry *tbl; | |
4714 | struct bnx2x_ilt *ilt; | |
6383c0b3 | 4715 | int msix_table_size = 0; |
55c11941 | 4716 | int fp_array_size, txq_array_size; |
15192a8c | 4717 | int i; |
6383c0b3 AE |
4718 | |
4719 | /* | |
4720 | * The biggest MSI-X table we might need is as a maximum number of fast | |
2de67439 | 4721 | * path IGU SBs plus default SB (for PF only). |
6383c0b3 | 4722 | */ |
1ab4434c AE |
4723 | msix_table_size = bp->igu_sb_cnt; |
4724 | if (IS_PF(bp)) | |
4725 | msix_table_size++; | |
4726 | BNX2X_DEV_INFO("msix_table_size %d\n", msix_table_size); | |
523224a3 | 4727 | |
6383c0b3 | 4728 | /* fp array: RSS plus CNIC related L2 queues */ |
55c11941 | 4729 | fp_array_size = BNX2X_MAX_RSS_COUNT(bp) + CNIC_SUPPORT(bp); |
c3146eb6 DK |
4730 | bp->fp_array_size = fp_array_size; |
4731 | BNX2X_DEV_INFO("fp_array_size %d\n", bp->fp_array_size); | |
15192a8c | 4732 | |
c3146eb6 | 4733 | fp = kcalloc(bp->fp_array_size, sizeof(*fp), GFP_KERNEL); |
523224a3 DK |
4734 | if (!fp) |
4735 | goto alloc_err; | |
c3146eb6 | 4736 | for (i = 0; i < bp->fp_array_size; i++) { |
15192a8c BW |
4737 | fp[i].tpa_info = |
4738 | kcalloc(ETH_MAX_AGGREGATION_QUEUES_E1H_E2, | |
4739 | sizeof(struct bnx2x_agg_info), GFP_KERNEL); | |
4740 | if (!(fp[i].tpa_info)) | |
4741 | goto alloc_err; | |
4742 | } | |
4743 | ||
523224a3 DK |
4744 | bp->fp = fp; |
4745 | ||
15192a8c | 4746 | /* allocate sp objs */ |
c3146eb6 | 4747 | bp->sp_objs = kcalloc(bp->fp_array_size, sizeof(struct bnx2x_sp_objs), |
15192a8c BW |
4748 | GFP_KERNEL); |
4749 | if (!bp->sp_objs) | |
4750 | goto alloc_err; | |
4751 | ||
4752 | /* allocate fp_stats */ | |
c3146eb6 | 4753 | bp->fp_stats = kcalloc(bp->fp_array_size, sizeof(struct bnx2x_fp_stats), |
15192a8c BW |
4754 | GFP_KERNEL); |
4755 | if (!bp->fp_stats) | |
4756 | goto alloc_err; | |
4757 | ||
65565884 | 4758 | /* Allocate memory for the transmission queues array */ |
55c11941 MS |
4759 | txq_array_size = |
4760 | BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS + CNIC_SUPPORT(bp); | |
4761 | BNX2X_DEV_INFO("txq_array_size %d", txq_array_size); | |
4762 | ||
4763 | bp->bnx2x_txq = kcalloc(txq_array_size, sizeof(struct bnx2x_fp_txdata), | |
4764 | GFP_KERNEL); | |
65565884 MS |
4765 | if (!bp->bnx2x_txq) |
4766 | goto alloc_err; | |
4767 | ||
523224a3 | 4768 | /* msix table */ |
01e23742 | 4769 | tbl = kcalloc(msix_table_size, sizeof(*tbl), GFP_KERNEL); |
523224a3 DK |
4770 | if (!tbl) |
4771 | goto alloc_err; | |
4772 | bp->msix_table = tbl; | |
4773 | ||
4774 | /* ilt */ | |
4775 | ilt = kzalloc(sizeof(*ilt), GFP_KERNEL); | |
4776 | if (!ilt) | |
4777 | goto alloc_err; | |
4778 | bp->ilt = ilt; | |
4779 | ||
4780 | return 0; | |
4781 | alloc_err: | |
4782 | bnx2x_free_mem_bp(bp); | |
4783 | return -ENOMEM; | |
523224a3 DK |
4784 | } |
4785 | ||
a9fccec7 | 4786 | int bnx2x_reload_if_running(struct net_device *dev) |
66371c44 MM |
4787 | { |
4788 | struct bnx2x *bp = netdev_priv(dev); | |
4789 | ||
4790 | if (unlikely(!netif_running(dev))) | |
4791 | return 0; | |
4792 | ||
5d07d868 | 4793 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); |
66371c44 MM |
4794 | return bnx2x_nic_load(bp, LOAD_NORMAL); |
4795 | } | |
4796 | ||
1ac9e428 YR |
4797 | int bnx2x_get_cur_phy_idx(struct bnx2x *bp) |
4798 | { | |
4799 | u32 sel_phy_idx = 0; | |
4800 | if (bp->link_params.num_phys <= 1) | |
4801 | return INT_PHY; | |
4802 | ||
4803 | if (bp->link_vars.link_up) { | |
4804 | sel_phy_idx = EXT_PHY1; | |
4805 | /* In case link is SERDES, check if the EXT_PHY2 is the one */ | |
4806 | if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) && | |
4807 | (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE)) | |
4808 | sel_phy_idx = EXT_PHY2; | |
4809 | } else { | |
4810 | ||
4811 | switch (bnx2x_phy_selection(&bp->link_params)) { | |
4812 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
4813 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
4814 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
4815 | sel_phy_idx = EXT_PHY1; | |
4816 | break; | |
4817 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
4818 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
4819 | sel_phy_idx = EXT_PHY2; | |
4820 | break; | |
4821 | } | |
4822 | } | |
4823 | ||
4824 | return sel_phy_idx; | |
1ac9e428 YR |
4825 | } |
4826 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp) | |
4827 | { | |
4828 | u32 sel_phy_idx = bnx2x_get_cur_phy_idx(bp); | |
4829 | /* | |
2de67439 | 4830 | * The selected activated PHY is always after swapping (in case PHY |
1ac9e428 YR |
4831 | * swapping is enabled). So when swapping is enabled, we need to reverse |
4832 | * the configuration | |
4833 | */ | |
4834 | ||
4835 | if (bp->link_params.multi_phy_config & | |
4836 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
4837 | if (sel_phy_idx == EXT_PHY1) | |
4838 | sel_phy_idx = EXT_PHY2; | |
4839 | else if (sel_phy_idx == EXT_PHY2) | |
4840 | sel_phy_idx = EXT_PHY1; | |
4841 | } | |
4842 | return LINK_CONFIG_IDX(sel_phy_idx); | |
4843 | } | |
4844 | ||
55c11941 | 4845 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
4846 | int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type) |
4847 | { | |
4848 | struct bnx2x *bp = netdev_priv(dev); | |
4849 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
4850 | ||
4851 | switch (type) { | |
4852 | case NETDEV_FCOE_WWNN: | |
4853 | *wwn = HILO_U64(cp->fcoe_wwn_node_name_hi, | |
4854 | cp->fcoe_wwn_node_name_lo); | |
4855 | break; | |
4856 | case NETDEV_FCOE_WWPN: | |
4857 | *wwn = HILO_U64(cp->fcoe_wwn_port_name_hi, | |
4858 | cp->fcoe_wwn_port_name_lo); | |
4859 | break; | |
4860 | default: | |
51c1a580 | 4861 | BNX2X_ERR("Wrong WWN type requested - %d\n", type); |
bf61ee14 VZ |
4862 | return -EINVAL; |
4863 | } | |
4864 | ||
4865 | return 0; | |
4866 | } | |
4867 | #endif | |
4868 | ||
9f6c9258 DK |
4869 | /* called with rtnl_lock */ |
4870 | int bnx2x_change_mtu(struct net_device *dev, int new_mtu) | |
4871 | { | |
4872 | struct bnx2x *bp = netdev_priv(dev); | |
9f6c9258 | 4873 | |
0650c0b8 YM |
4874 | if (pci_num_vf(bp->pdev)) { |
4875 | DP(BNX2X_MSG_IOV, "VFs are enabled, can not change MTU\n"); | |
4876 | return -EPERM; | |
4877 | } | |
4878 | ||
9f6c9258 | 4879 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 4880 | BNX2X_ERR("Can't perform change MTU during parity recovery\n"); |
9f6c9258 DK |
4881 | return -EAGAIN; |
4882 | } | |
4883 | ||
9f6c9258 DK |
4884 | /* This does not race with packet allocation |
4885 | * because the actual alloc size is | |
4886 | * only updated as part of load | |
4887 | */ | |
4888 | dev->mtu = new_mtu; | |
4889 | ||
230d00eb YM |
4890 | if (IS_PF(bp) && SHMEM2_HAS(bp, curr_cfg)) |
4891 | SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS); | |
4892 | ||
66371c44 MM |
4893 | return bnx2x_reload_if_running(dev); |
4894 | } | |
4895 | ||
c8f44aff | 4896 | netdev_features_t bnx2x_fix_features(struct net_device *dev, |
621b4d66 | 4897 | netdev_features_t features) |
66371c44 MM |
4898 | { |
4899 | struct bnx2x *bp = netdev_priv(dev); | |
4900 | ||
909d9faa YM |
4901 | if (pci_num_vf(bp->pdev)) { |
4902 | netdev_features_t changed = dev->features ^ features; | |
4903 | ||
4904 | /* Revert the requested changes in features if they | |
4905 | * would require internal reload of PF in bnx2x_set_features(). | |
4906 | */ | |
4907 | if (!(features & NETIF_F_RXCSUM) && !bp->disable_tpa) { | |
4908 | features &= ~NETIF_F_RXCSUM; | |
4909 | features |= dev->features & NETIF_F_RXCSUM; | |
4910 | } | |
4911 | ||
4912 | if (changed & NETIF_F_LOOPBACK) { | |
4913 | features &= ~NETIF_F_LOOPBACK; | |
4914 | features |= dev->features & NETIF_F_LOOPBACK; | |
4915 | } | |
4916 | } | |
4917 | ||
66371c44 | 4918 | /* TPA requires Rx CSUM offloading */ |
aebf6244 | 4919 | if (!(features & NETIF_F_RXCSUM)) { |
66371c44 | 4920 | features &= ~NETIF_F_LRO; |
621b4d66 DK |
4921 | features &= ~NETIF_F_GRO; |
4922 | } | |
66371c44 MM |
4923 | |
4924 | return features; | |
4925 | } | |
4926 | ||
c8f44aff | 4927 | int bnx2x_set_features(struct net_device *dev, netdev_features_t features) |
66371c44 MM |
4928 | { |
4929 | struct bnx2x *bp = netdev_priv(dev); | |
f8dcb5e3 | 4930 | netdev_features_t changes = features ^ dev->features; |
538dd2e3 | 4931 | bool bnx2x_reload = false; |
f8dcb5e3 | 4932 | int rc; |
621b4d66 | 4933 | |
909d9faa YM |
4934 | /* VFs or non SRIOV PFs should be able to change loopback feature */ |
4935 | if (!pci_num_vf(bp->pdev)) { | |
4936 | if (features & NETIF_F_LOOPBACK) { | |
4937 | if (bp->link_params.loopback_mode != LOOPBACK_BMAC) { | |
4938 | bp->link_params.loopback_mode = LOOPBACK_BMAC; | |
4939 | bnx2x_reload = true; | |
4940 | } | |
4941 | } else { | |
4942 | if (bp->link_params.loopback_mode != LOOPBACK_NONE) { | |
4943 | bp->link_params.loopback_mode = LOOPBACK_NONE; | |
4944 | bnx2x_reload = true; | |
4945 | } | |
538dd2e3 MB |
4946 | } |
4947 | } | |
4948 | ||
16a5fd92 | 4949 | /* if GRO is changed while LRO is enabled, don't force a reload */ |
f8dcb5e3 MS |
4950 | if ((changes & NETIF_F_GRO) && (features & NETIF_F_LRO)) |
4951 | changes &= ~NETIF_F_GRO; | |
8802f579 | 4952 | |
aebf6244 | 4953 | /* if GRO is changed while HW TPA is off, don't force a reload */ |
f8dcb5e3 MS |
4954 | if ((changes & NETIF_F_GRO) && bp->disable_tpa) |
4955 | changes &= ~NETIF_F_GRO; | |
aebf6244 | 4956 | |
8802f579 | 4957 | if (changes) |
538dd2e3 | 4958 | bnx2x_reload = true; |
8802f579 | 4959 | |
538dd2e3 | 4960 | if (bnx2x_reload) { |
f8dcb5e3 MS |
4961 | if (bp->recovery_state == BNX2X_RECOVERY_DONE) { |
4962 | dev->features = features; | |
4963 | rc = bnx2x_reload_if_running(dev); | |
4964 | return rc ? rc : 1; | |
4965 | } | |
66371c44 | 4966 | /* else: bnx2x_nic_load() will be called at end of recovery */ |
9f6c9258 DK |
4967 | } |
4968 | ||
66371c44 | 4969 | return 0; |
9f6c9258 DK |
4970 | } |
4971 | ||
4972 | void bnx2x_tx_timeout(struct net_device *dev) | |
4973 | { | |
4974 | struct bnx2x *bp = netdev_priv(dev); | |
4975 | ||
4976 | #ifdef BNX2X_STOP_ON_ERROR | |
4977 | if (!bp->panic) | |
4978 | bnx2x_panic(); | |
4979 | #endif | |
7be08a72 | 4980 | |
9f6c9258 | 4981 | /* This allows the netif to be shutdown gracefully before resetting */ |
230bb0f3 | 4982 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_TX_TIMEOUT, 0); |
9f6c9258 DK |
4983 | } |
4984 | ||
9f6c9258 DK |
4985 | int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state) |
4986 | { | |
4987 | struct net_device *dev = pci_get_drvdata(pdev); | |
4988 | struct bnx2x *bp; | |
4989 | ||
4990 | if (!dev) { | |
4991 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); | |
4992 | return -ENODEV; | |
4993 | } | |
4994 | bp = netdev_priv(dev); | |
4995 | ||
4996 | rtnl_lock(); | |
4997 | ||
4998 | pci_save_state(pdev); | |
4999 | ||
5000 | if (!netif_running(dev)) { | |
5001 | rtnl_unlock(); | |
5002 | return 0; | |
5003 | } | |
5004 | ||
5005 | netif_device_detach(dev); | |
5006 | ||
5d07d868 | 5007 | bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); |
9f6c9258 DK |
5008 | |
5009 | bnx2x_set_power_state(bp, pci_choose_state(pdev, state)); | |
5010 | ||
5011 | rtnl_unlock(); | |
5012 | ||
5013 | return 0; | |
5014 | } | |
5015 | ||
5016 | int bnx2x_resume(struct pci_dev *pdev) | |
5017 | { | |
5018 | struct net_device *dev = pci_get_drvdata(pdev); | |
5019 | struct bnx2x *bp; | |
5020 | int rc; | |
5021 | ||
5022 | if (!dev) { | |
5023 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); | |
5024 | return -ENODEV; | |
5025 | } | |
5026 | bp = netdev_priv(dev); | |
5027 | ||
5028 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { | |
51c1a580 | 5029 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
9f6c9258 DK |
5030 | return -EAGAIN; |
5031 | } | |
5032 | ||
5033 | rtnl_lock(); | |
5034 | ||
5035 | pci_restore_state(pdev); | |
5036 | ||
5037 | if (!netif_running(dev)) { | |
5038 | rtnl_unlock(); | |
5039 | return 0; | |
5040 | } | |
5041 | ||
5042 | bnx2x_set_power_state(bp, PCI_D0); | |
5043 | netif_device_attach(dev); | |
5044 | ||
5045 | rc = bnx2x_nic_load(bp, LOAD_OPEN); | |
5046 | ||
5047 | rtnl_unlock(); | |
5048 | ||
5049 | return rc; | |
5050 | } | |
619c5cb6 | 5051 | |
619c5cb6 VZ |
5052 | void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, |
5053 | u32 cid) | |
5054 | { | |
b9871bcf AE |
5055 | if (!cxt) { |
5056 | BNX2X_ERR("bad context pointer %p\n", cxt); | |
5057 | return; | |
5058 | } | |
5059 | ||
619c5cb6 VZ |
5060 | /* ustorm cxt validation */ |
5061 | cxt->ustorm_ag_context.cdu_usage = | |
5062 | CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid), | |
5063 | CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE); | |
5064 | /* xcontext validation */ | |
5065 | cxt->xstorm_ag_context.cdu_reserved = | |
5066 | CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid), | |
5067 | CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE); | |
5068 | } | |
5069 | ||
1191cb83 ED |
5070 | static void storm_memset_hc_timeout(struct bnx2x *bp, u8 port, |
5071 | u8 fw_sb_id, u8 sb_index, | |
5072 | u8 ticks) | |
619c5cb6 | 5073 | { |
619c5cb6 VZ |
5074 | u32 addr = BAR_CSTRORM_INTMEM + |
5075 | CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index); | |
5076 | REG_WR8(bp, addr, ticks); | |
51c1a580 MS |
5077 | DP(NETIF_MSG_IFUP, |
5078 | "port %x fw_sb_id %d sb_index %d ticks %d\n", | |
5079 | port, fw_sb_id, sb_index, ticks); | |
619c5cb6 VZ |
5080 | } |
5081 | ||
1191cb83 ED |
5082 | static void storm_memset_hc_disable(struct bnx2x *bp, u8 port, |
5083 | u16 fw_sb_id, u8 sb_index, | |
5084 | u8 disable) | |
619c5cb6 VZ |
5085 | { |
5086 | u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT); | |
5087 | u32 addr = BAR_CSTRORM_INTMEM + | |
5088 | CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index); | |
0c14e5ce | 5089 | u8 flags = REG_RD8(bp, addr); |
619c5cb6 VZ |
5090 | /* clear and set */ |
5091 | flags &= ~HC_INDEX_DATA_HC_ENABLED; | |
5092 | flags |= enable_flag; | |
0c14e5ce | 5093 | REG_WR8(bp, addr, flags); |
51c1a580 MS |
5094 | DP(NETIF_MSG_IFUP, |
5095 | "port %x fw_sb_id %d sb_index %d disable %d\n", | |
5096 | port, fw_sb_id, sb_index, disable); | |
619c5cb6 VZ |
5097 | } |
5098 | ||
5099 | void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, | |
5100 | u8 sb_index, u8 disable, u16 usec) | |
5101 | { | |
5102 | int port = BP_PORT(bp); | |
5103 | u8 ticks = usec / BNX2X_BTR; | |
5104 | ||
5105 | storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks); | |
5106 | ||
5107 | disable = disable ? 1 : (usec ? 0 : 1); | |
5108 | storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable); | |
5109 | } | |
230bb0f3 YM |
5110 | |
5111 | void bnx2x_schedule_sp_rtnl(struct bnx2x *bp, enum sp_rtnl_flag flag, | |
5112 | u32 verbose) | |
5113 | { | |
4e857c58 | 5114 | smp_mb__before_atomic(); |
230bb0f3 | 5115 | set_bit(flag, &bp->sp_rtnl_state); |
4e857c58 | 5116 | smp_mb__after_atomic(); |
230bb0f3 YM |
5117 | DP((BNX2X_MSG_SP | verbose), "Scheduling sp_rtnl task [Flag: %d]\n", |
5118 | flag); | |
5119 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
5120 | } |