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9f6c9258 DK |
1 | /* bnx2x_cmn.h: Broadcom Everest network driver. |
2 | * | |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
9f6c9258 DK |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
17 | #ifndef BNX2X_CMN_H | |
18 | #define BNX2X_CMN_H | |
19 | ||
20 | #include <linux/types.h> | |
619c5cb6 | 21 | #include <linux/pci.h> |
9f6c9258 | 22 | #include <linux/netdevice.h> |
614c76df | 23 | #include <linux/etherdevice.h> |
9f6c9258 | 24 | |
9f6c9258 | 25 | #include "bnx2x.h" |
6411280a | 26 | #include "bnx2x_sriov.h" |
9f6c9258 | 27 | |
619c5cb6 | 28 | /* This is used as a replacement for an MCP if it's not present */ |
a8f47eb7 | 29 | extern int bnx2x_load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ |
30 | extern int bnx2x_num_queues; | |
9f6c9258 | 31 | |
b3b83c3f DK |
32 | /************************ Macros ********************************/ |
33 | #define BNX2X_PCI_FREE(x, y, size) \ | |
34 | do { \ | |
35 | if (x) { \ | |
36 | dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ | |
37 | x = NULL; \ | |
38 | y = 0; \ | |
39 | } \ | |
40 | } while (0) | |
41 | ||
42 | #define BNX2X_FREE(x) \ | |
43 | do { \ | |
44 | if (x) { \ | |
45 | kfree((void *)x); \ | |
46 | x = NULL; \ | |
47 | } \ | |
48 | } while (0) | |
49 | ||
6bf07b8e YM |
50 | #define BNX2X_PCI_ALLOC(x, y, size) \ |
51 | do { \ | |
ede23fa8 | 52 | x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ |
6bf07b8e YM |
53 | if (x == NULL) \ |
54 | goto alloc_mem_err; \ | |
55 | DP(NETIF_MSG_HW, "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \ | |
56 | (unsigned long long)(*y), x); \ | |
57 | } while (0) | |
b3b83c3f | 58 | |
75b29459 DK |
59 | #define BNX2X_PCI_FALLOC(x, y, size) \ |
60 | do { \ | |
61 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ | |
62 | if (x == NULL) \ | |
63 | goto alloc_mem_err; \ | |
64 | memset((void *)x, 0xFFFFFFFF, size); \ | |
65 | DP(NETIF_MSG_HW, "BNX2X_PCI_FALLOC: Physical %Lx Virtual %p\n",\ | |
66 | (unsigned long long)(*y), x); \ | |
67 | } while (0) | |
68 | ||
b3b83c3f DK |
69 | #define BNX2X_ALLOC(x, size) \ |
70 | do { \ | |
71 | x = kzalloc(size, GFP_KERNEL); \ | |
72 | if (x == NULL) \ | |
73 | goto alloc_mem_err; \ | |
74 | } while (0) | |
75 | ||
9f6c9258 DK |
76 | /*********************** Interfaces **************************** |
77 | * Functions that need to be implemented by each driver version | |
78 | */ | |
619c5cb6 VZ |
79 | /* Init */ |
80 | ||
81 | /** | |
82 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
83 | * | |
84 | * @bp: driver handle | |
85 | * @unload_mode: requested function's unload mode | |
86 | * | |
87 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
88 | */ | |
89 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); | |
90 | ||
91 | /** | |
92 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
93 | * | |
94 | * @bp: driver handle | |
5d07d868 | 95 | * @keep_link: true iff link should be kept up |
619c5cb6 | 96 | */ |
5d07d868 | 97 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link); |
619c5cb6 VZ |
98 | |
99 | /** | |
96305234 | 100 | * bnx2x_config_rss_pf - configure RSS parameters in a PF. |
619c5cb6 VZ |
101 | * |
102 | * @bp: driver handle | |
49ce9c2c | 103 | * @rss_obj: RSS object to use |
619c5cb6 VZ |
104 | * @ind_table: indirection table to configure |
105 | * @config_hash: re-configure RSS hash keys configuration | |
60cad4e6 | 106 | * @enable: enabled or disabled configuration |
619c5cb6 | 107 | */ |
60cad4e6 AE |
108 | int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, |
109 | bool config_hash, bool enable); | |
619c5cb6 VZ |
110 | |
111 | /** | |
112 | * bnx2x__init_func_obj - init function object | |
113 | * | |
114 | * @bp: driver handle | |
115 | * | |
116 | * Initializes the Function Object with the appropriate | |
117 | * parameters which include a function slow path driver | |
118 | * interface. | |
119 | */ | |
120 | void bnx2x__init_func_obj(struct bnx2x *bp); | |
121 | ||
122 | /** | |
123 | * bnx2x_setup_queue - setup eth queue. | |
124 | * | |
125 | * @bp: driver handle | |
126 | * @fp: pointer to the fastpath structure | |
127 | * @leading: boolean | |
128 | * | |
129 | */ | |
130 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
131 | bool leading); | |
132 | ||
133 | /** | |
134 | * bnx2x_setup_leading - bring up a leading eth queue. | |
135 | * | |
136 | * @bp: driver handle | |
137 | */ | |
138 | int bnx2x_setup_leading(struct bnx2x *bp); | |
139 | ||
140 | /** | |
141 | * bnx2x_fw_command - send the MCP a request | |
142 | * | |
143 | * @bp: driver handle | |
144 | * @command: request | |
145 | * @param: request's parameter | |
146 | * | |
147 | * block until there is a reply | |
148 | */ | |
149 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); | |
9f6c9258 DK |
150 | |
151 | /** | |
e8920674 | 152 | * bnx2x_initial_phy_init - initialize link parameters structure variables. |
9f6c9258 | 153 | * |
e8920674 DK |
154 | * @bp: driver handle |
155 | * @load_mode: current mode | |
9f6c9258 | 156 | */ |
cd1dfce2 | 157 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); |
9f6c9258 DK |
158 | |
159 | /** | |
e8920674 | 160 | * bnx2x_link_set - configure hw according to link parameters structure. |
9f6c9258 | 161 | * |
e8920674 | 162 | * @bp: driver handle |
9f6c9258 DK |
163 | */ |
164 | void bnx2x_link_set(struct bnx2x *bp); | |
165 | ||
5d07d868 YM |
166 | /** |
167 | * bnx2x_force_link_reset - Forces link reset, and put the PHY | |
168 | * in reset as well. | |
169 | * | |
170 | * @bp: driver handle | |
171 | */ | |
172 | void bnx2x_force_link_reset(struct bnx2x *bp); | |
173 | ||
9f6c9258 | 174 | /** |
e8920674 | 175 | * bnx2x_link_test - query link status. |
9f6c9258 | 176 | * |
e8920674 DK |
177 | * @bp: driver handle |
178 | * @is_serdes: bool | |
9f6c9258 | 179 | * |
e8920674 | 180 | * Returns 0 if link is UP. |
9f6c9258 | 181 | */ |
a22f0788 | 182 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); |
9f6c9258 | 183 | |
619c5cb6 VZ |
184 | /** |
185 | * bnx2x_drv_pulse - write driver pulse to shmem | |
186 | * | |
187 | * @bp: driver handle | |
188 | * | |
189 | * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox | |
190 | * in the shmem. | |
191 | */ | |
192 | void bnx2x_drv_pulse(struct bnx2x *bp); | |
193 | ||
194 | /** | |
195 | * bnx2x_igu_ack_sb - update IGU with current SB value | |
196 | * | |
197 | * @bp: driver handle | |
198 | * @igu_sb_id: SB id | |
199 | * @segment: SB segment | |
200 | * @index: SB index | |
201 | * @op: SB operation | |
202 | * @update: is HW update required | |
203 | */ | |
204 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, | |
205 | u16 index, u8 op, u8 update); | |
206 | ||
c9ee9206 VZ |
207 | /* Disable transactions from chip to host */ |
208 | void bnx2x_pf_disable(struct bnx2x *bp); | |
07ba6af4 | 209 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); |
c9ee9206 | 210 | |
9f6c9258 | 211 | /** |
e8920674 | 212 | * bnx2x__link_status_update - handles link status change. |
9f6c9258 | 213 | * |
e8920674 | 214 | * @bp: driver handle |
9f6c9258 DK |
215 | */ |
216 | void bnx2x__link_status_update(struct bnx2x *bp); | |
217 | ||
f85582f8 | 218 | /** |
e8920674 | 219 | * bnx2x_link_report - report link status to upper layer. |
f85582f8 | 220 | * |
e8920674 | 221 | * @bp: driver handle |
f85582f8 DK |
222 | */ |
223 | void bnx2x_link_report(struct bnx2x *bp); | |
224 | ||
2ae17f66 VZ |
225 | /* None-atomic version of bnx2x_link_report() */ |
226 | void __bnx2x_link_report(struct bnx2x *bp); | |
227 | ||
0793f83f | 228 | /** |
e8920674 | 229 | * bnx2x_get_mf_speed - calculate MF speed. |
0793f83f | 230 | * |
e8920674 | 231 | * @bp: driver handle |
0793f83f | 232 | * |
e8920674 | 233 | * Takes into account current linespeed and MF configuration. |
0793f83f DK |
234 | */ |
235 | u16 bnx2x_get_mf_speed(struct bnx2x *bp); | |
236 | ||
9f6c9258 | 237 | /** |
e8920674 | 238 | * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler |
9f6c9258 | 239 | * |
e8920674 DK |
240 | * @irq: irq number |
241 | * @dev_instance: private instance | |
9f6c9258 DK |
242 | */ |
243 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); | |
244 | ||
245 | /** | |
e8920674 | 246 | * bnx2x_interrupt - non MSI-X interrupt handler |
9f6c9258 | 247 | * |
e8920674 DK |
248 | * @irq: irq number |
249 | * @dev_instance: private instance | |
9f6c9258 DK |
250 | */ |
251 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); | |
9f6c9258 DK |
252 | |
253 | /** | |
e8920674 | 254 | * bnx2x_cnic_notify - send command to cnic driver |
9f6c9258 | 255 | * |
e8920674 DK |
256 | * @bp: driver handle |
257 | * @cmd: command | |
9f6c9258 DK |
258 | */ |
259 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); | |
260 | ||
261 | /** | |
e8920674 | 262 | * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information |
9f6c9258 | 263 | * |
e8920674 | 264 | * @bp: driver handle |
9f6c9258 DK |
265 | */ |
266 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); | |
37ae41a9 MS |
267 | |
268 | /** | |
269 | * bnx2x_setup_cnic_info - provides cnic with updated info | |
270 | * | |
271 | * @bp: driver handle | |
272 | */ | |
273 | void bnx2x_setup_cnic_info(struct bnx2x *bp); | |
274 | ||
9f6c9258 | 275 | /** |
e8920674 | 276 | * bnx2x_int_enable - enable HW interrupts. |
9f6c9258 | 277 | * |
e8920674 | 278 | * @bp: driver handle |
9f6c9258 DK |
279 | */ |
280 | void bnx2x_int_enable(struct bnx2x *bp); | |
281 | ||
282 | /** | |
e8920674 DK |
283 | * bnx2x_int_disable_sync - disable interrupts. |
284 | * | |
285 | * @bp: driver handle | |
286 | * @disable_hw: true, disable HW interrupts. | |
9f6c9258 | 287 | * |
e8920674 DK |
288 | * This function ensures that there are no |
289 | * ISRs or SP DPCs (sp_task) are running after it returns. | |
9f6c9258 DK |
290 | */ |
291 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); | |
292 | ||
9f6c9258 | 293 | /** |
55c11941 | 294 | * bnx2x_nic_init_cnic - init driver internals for cnic. |
e8920674 DK |
295 | * |
296 | * @bp: driver handle | |
297 | * @load_code: COMMON, PORT or FUNCTION | |
298 | * | |
299 | * Initializes: | |
9f6c9258 DK |
300 | * - rings |
301 | * - status blocks | |
302 | * - etc. | |
9f6c9258 | 303 | */ |
55c11941 | 304 | void bnx2x_nic_init_cnic(struct bnx2x *bp); |
9f6c9258 | 305 | |
55c11941 | 306 | /** |
ecf01c22 | 307 | * bnx2x_preirq_nic_init - init driver internals. |
55c11941 MS |
308 | * |
309 | * @bp: driver handle | |
310 | * | |
311 | * Initializes: | |
ecf01c22 YM |
312 | * - fastpath object |
313 | * - fastpath rings | |
314 | * etc. | |
315 | */ | |
316 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp); | |
317 | ||
318 | /** | |
319 | * bnx2x_postirq_nic_init - init driver internals. | |
320 | * | |
321 | * @bp: driver handle | |
322 | * @load_code: COMMON, PORT or FUNCTION | |
323 | * | |
324 | * Initializes: | |
55c11941 | 325 | * - status blocks |
ecf01c22 | 326 | * - slowpath rings |
55c11941 MS |
327 | * - etc. |
328 | */ | |
ecf01c22 | 329 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code); |
55c11941 MS |
330 | /** |
331 | * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. | |
332 | * | |
333 | * @bp: driver handle | |
334 | */ | |
335 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp); | |
9f6c9258 | 336 | /** |
e8920674 | 337 | * bnx2x_alloc_mem - allocate driver's memory. |
9f6c9258 | 338 | * |
e8920674 | 339 | * @bp: driver handle |
9f6c9258 DK |
340 | */ |
341 | int bnx2x_alloc_mem(struct bnx2x *bp); | |
342 | ||
55c11941 MS |
343 | /** |
344 | * bnx2x_free_mem_cnic - release driver's memory for cnic. | |
345 | * | |
346 | * @bp: driver handle | |
347 | */ | |
348 | void bnx2x_free_mem_cnic(struct bnx2x *bp); | |
9f6c9258 | 349 | /** |
e8920674 | 350 | * bnx2x_free_mem - release driver's memory. |
9f6c9258 | 351 | * |
e8920674 | 352 | * @bp: driver handle |
9f6c9258 DK |
353 | */ |
354 | void bnx2x_free_mem(struct bnx2x *bp); | |
355 | ||
9f6c9258 | 356 | /** |
e8920674 | 357 | * bnx2x_set_num_queues - set number of queues according to mode. |
9f6c9258 | 358 | * |
e8920674 | 359 | * @bp: driver handle |
9f6c9258 | 360 | */ |
d6214d7a | 361 | void bnx2x_set_num_queues(struct bnx2x *bp); |
9f6c9258 DK |
362 | |
363 | /** | |
e8920674 DK |
364 | * bnx2x_chip_cleanup - cleanup chip internals. |
365 | * | |
366 | * @bp: driver handle | |
367 | * @unload_mode: COMMON, PORT, FUNCTION | |
5d07d868 | 368 | * @keep_link: true iff link should be kept up. |
e8920674 | 369 | * |
9f6c9258 | 370 | * - Cleanup MAC configuration. |
e8920674 | 371 | * - Closes clients. |
9f6c9258 | 372 | * - etc. |
9f6c9258 | 373 | */ |
5d07d868 | 374 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link); |
9f6c9258 DK |
375 | |
376 | /** | |
e8920674 | 377 | * bnx2x_acquire_hw_lock - acquire HW lock. |
9f6c9258 | 378 | * |
e8920674 DK |
379 | * @bp: driver handle |
380 | * @resource: resource bit which was locked | |
9f6c9258 DK |
381 | */ |
382 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); | |
383 | ||
384 | /** | |
e8920674 | 385 | * bnx2x_release_hw_lock - release HW lock. |
9f6c9258 | 386 | * |
e8920674 DK |
387 | * @bp: driver handle |
388 | * @resource: resource bit which was locked | |
9f6c9258 DK |
389 | */ |
390 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); | |
391 | ||
c9ee9206 VZ |
392 | /** |
393 | * bnx2x_release_leader_lock - release recovery leader lock | |
394 | * | |
395 | * @bp: driver handle | |
396 | */ | |
397 | int bnx2x_release_leader_lock(struct bnx2x *bp); | |
398 | ||
9f6c9258 | 399 | /** |
e8920674 DK |
400 | * bnx2x_set_eth_mac - configure eth MAC address in the HW |
401 | * | |
402 | * @bp: driver handle | |
403 | * @set: set or clear | |
9f6c9258 | 404 | * |
e8920674 | 405 | * Configures according to the value in netdev->dev_addr. |
9f6c9258 | 406 | */ |
619c5cb6 | 407 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); |
9f6c9258 | 408 | |
ec6ba945 | 409 | /** |
619c5cb6 | 410 | * bnx2x_set_rx_mode - set MAC filtering configurations. |
ec6ba945 | 411 | * |
619c5cb6 | 412 | * @dev: netdevice |
ec6ba945 | 413 | * |
619c5cb6 VZ |
414 | * called with netif_tx_lock from dev_mcast.c |
415 | * If bp->state is OPEN, should be called with | |
416 | * netif_addr_lock_bh() | |
ec6ba945 | 417 | */ |
8b09be5f | 418 | void bnx2x_set_rx_mode_inner(struct bnx2x *bp); |
ec6ba945 | 419 | |
9f6c9258 | 420 | /* Parity errors related */ |
889b9af3 AE |
421 | void bnx2x_set_pf_load(struct bnx2x *bp); |
422 | bool bnx2x_clear_pf_load(struct bnx2x *bp); | |
c9ee9206 VZ |
423 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); |
424 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); | |
425 | void bnx2x_set_reset_in_progress(struct bnx2x *bp); | |
426 | void bnx2x_set_reset_global(struct bnx2x *bp); | |
9f6c9258 | 427 | void bnx2x_disable_close_the_gate(struct bnx2x *bp); |
55c11941 | 428 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp); |
9f6c9258 | 429 | |
9f6c9258 | 430 | /** |
e8920674 | 431 | * bnx2x_sp_event - handle ramrods completion. |
9f6c9258 | 432 | * |
e8920674 DK |
433 | * @fp: fastpath handle for the event |
434 | * @rr_cqe: eth_rx_cqe | |
9f6c9258 | 435 | */ |
f85582f8 | 436 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); |
9f6c9258 | 437 | |
523224a3 | 438 | /** |
e8920674 | 439 | * bnx2x_ilt_set_info - prepare ILT configurations. |
523224a3 | 440 | * |
e8920674 | 441 | * @bp: driver handle |
523224a3 DK |
442 | */ |
443 | void bnx2x_ilt_set_info(struct bnx2x *bp); | |
9f6c9258 | 444 | |
55c11941 MS |
445 | /** |
446 | * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC | |
447 | * and TM. | |
448 | * | |
449 | * @bp: driver handle | |
450 | */ | |
451 | void bnx2x_ilt_set_info_cnic(struct bnx2x *bp); | |
452 | ||
e4901dde | 453 | /** |
e8920674 | 454 | * bnx2x_dcbx_init - initialize dcbx protocol. |
e4901dde | 455 | * |
e8920674 | 456 | * @bp: driver handle |
e4901dde | 457 | */ |
9876879f | 458 | void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); |
e4901dde | 459 | |
f85582f8 | 460 | /** |
e8920674 | 461 | * bnx2x_set_power_state - set power state to the requested value. |
f85582f8 | 462 | * |
e8920674 DK |
463 | * @bp: driver handle |
464 | * @state: required state D0 or D3hot | |
f85582f8 | 465 | * |
e8920674 | 466 | * Currently only D0 and D3hot are supported. |
f85582f8 DK |
467 | */ |
468 | int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); | |
469 | ||
e3835b99 | 470 | /** |
e8920674 | 471 | * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. |
e3835b99 | 472 | * |
e8920674 DK |
473 | * @bp: driver handle |
474 | * @value: new value | |
e3835b99 DK |
475 | */ |
476 | void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); | |
619c5cb6 | 477 | /* Error handling */ |
7a25cc73 DK |
478 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); |
479 | ||
f85582f8 | 480 | /* dev_close main block */ |
5d07d868 | 481 | int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link); |
f85582f8 DK |
482 | |
483 | /* dev_open main block */ | |
484 | int bnx2x_nic_load(struct bnx2x *bp, int load_mode); | |
485 | ||
486 | /* hard_xmit callback */ | |
487 | netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
488 | ||
6383c0b3 AE |
489 | /* setup_tc callback */ |
490 | int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); | |
491 | ||
3ec9f9ca AE |
492 | int bnx2x_get_vf_config(struct net_device *dev, int vf, |
493 | struct ifla_vf_info *ivi); | |
abc5a021 | 494 | int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac); |
3ec9f9ca | 495 | int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos); |
abc5a021 | 496 | |
8307fa3e | 497 | /* select_queue callback */ |
f663dd9a | 498 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 499 | void *accel_priv, select_queue_fallback_t fallback); |
8307fa3e | 500 | |
dc1ba591 AE |
501 | static inline void bnx2x_update_rx_prod(struct bnx2x *bp, |
502 | struct bnx2x_fastpath *fp, | |
503 | u16 bd_prod, u16 rx_comp_prod, | |
504 | u16 rx_sge_prod) | |
505 | { | |
506 | struct ustorm_eth_rx_producers rx_prods = {0}; | |
507 | u32 i; | |
508 | ||
509 | /* Update producers */ | |
510 | rx_prods.bd_prod = bd_prod; | |
511 | rx_prods.cqe_prod = rx_comp_prod; | |
512 | rx_prods.sge_prod = rx_sge_prod; | |
513 | ||
514 | /* Make sure that the BD and SGE data is updated before updating the | |
515 | * producers since FW might read the BD/SGE right after the producer | |
516 | * is updated. | |
517 | * This is only applicable for weak-ordered memory model archs such | |
518 | * as IA-64. The following barrier is also mandatory since FW will | |
519 | * assumes BDs must have buffers. | |
520 | */ | |
521 | wmb(); | |
522 | ||
523 | for (i = 0; i < sizeof(rx_prods)/4; i++) | |
524 | REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, | |
525 | ((u32 *)&rx_prods)[i]); | |
526 | ||
527 | mmiowb(); /* keep prod updates ordered */ | |
528 | ||
529 | DP(NETIF_MSG_RX_STATUS, | |
530 | "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", | |
531 | fp->index, bd_prod, rx_comp_prod, rx_sge_prod); | |
532 | } | |
533 | ||
a9fccec7 DK |
534 | /* reload helper */ |
535 | int bnx2x_reload_if_running(struct net_device *dev); | |
536 | ||
f85582f8 DK |
537 | int bnx2x_change_mac_addr(struct net_device *dev, void *p); |
538 | ||
f85582f8 | 539 | /* NAPI poll Tx part */ |
6383c0b3 | 540 | int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); |
f85582f8 DK |
541 | |
542 | /* suspend/resume callbacks */ | |
543 | int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); | |
544 | int bnx2x_resume(struct pci_dev *pdev); | |
545 | ||
546 | /* Release IRQ vectors */ | |
547 | void bnx2x_free_irq(struct bnx2x *bp); | |
548 | ||
b3b83c3f | 549 | void bnx2x_free_fp_mem(struct bnx2x *bp); |
f85582f8 | 550 | void bnx2x_init_rx_rings(struct bnx2x *bp); |
55c11941 | 551 | void bnx2x_init_rx_rings_cnic(struct bnx2x *bp); |
f85582f8 DK |
552 | void bnx2x_free_skbs(struct bnx2x *bp); |
553 | void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); | |
554 | void bnx2x_netif_start(struct bnx2x *bp); | |
55c11941 | 555 | int bnx2x_load_cnic(struct bnx2x *bp); |
f85582f8 | 556 | |
d6214d7a | 557 | /** |
e8920674 | 558 | * bnx2x_enable_msix - set msix configuration. |
d6214d7a | 559 | * |
e8920674 | 560 | * @bp: driver handle |
d6214d7a | 561 | * |
e8920674 DK |
562 | * fills msix_table, requests vectors, updates num_queues |
563 | * according to number of available vectors. | |
d6214d7a | 564 | */ |
0e8d2ec5 | 565 | int bnx2x_enable_msix(struct bnx2x *bp); |
d6214d7a DK |
566 | |
567 | /** | |
e8920674 | 568 | * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly |
d6214d7a | 569 | * |
e8920674 | 570 | * @bp: driver handle |
d6214d7a DK |
571 | */ |
572 | int bnx2x_enable_msi(struct bnx2x *bp); | |
573 | ||
8f20aa57 DK |
574 | /** |
575 | * bnx2x_low_latency_recv - LL callback | |
576 | * | |
577 | * @napi: napi structure | |
578 | */ | |
579 | int bnx2x_low_latency_recv(struct napi_struct *napi); | |
580 | ||
f85582f8 | 581 | /** |
e8920674 | 582 | * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure |
f85582f8 | 583 | * |
e8920674 | 584 | * @bp: driver handle |
f85582f8 | 585 | */ |
0329aba1 | 586 | int bnx2x_alloc_mem_bp(struct bnx2x *bp); |
e8920674 DK |
587 | |
588 | /** | |
589 | * bnx2x_free_mem_bp - release memories outsize main driver structure | |
590 | * | |
591 | * @bp: driver handle | |
592 | */ | |
f85582f8 DK |
593 | void bnx2x_free_mem_bp(struct bnx2x *bp); |
594 | ||
595 | /** | |
e8920674 | 596 | * bnx2x_change_mtu - change mtu netdev callback |
f85582f8 | 597 | * |
e8920674 DK |
598 | * @dev: net device |
599 | * @new_mtu: requested mtu | |
f85582f8 | 600 | * |
f85582f8 DK |
601 | */ |
602 | int bnx2x_change_mtu(struct net_device *dev, int new_mtu); | |
603 | ||
55c11941 | 604 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
605 | /** |
606 | * bnx2x_fcoe_get_wwn - return the requested WWN value for this port | |
607 | * | |
608 | * @dev: net_device | |
609 | * @wwn: output buffer | |
610 | * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) | |
611 | * | |
612 | */ | |
613 | int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); | |
614 | #endif | |
621b4d66 | 615 | |
c8f44aff | 616 | netdev_features_t bnx2x_fix_features(struct net_device *dev, |
621b4d66 | 617 | netdev_features_t features); |
c8f44aff | 618 | int bnx2x_set_features(struct net_device *dev, netdev_features_t features); |
66371c44 | 619 | |
f85582f8 | 620 | /** |
e8920674 | 621 | * bnx2x_tx_timeout - tx timeout netdev callback |
f85582f8 | 622 | * |
e8920674 | 623 | * @dev: net device |
f85582f8 DK |
624 | */ |
625 | void bnx2x_tx_timeout(struct net_device *dev); | |
626 | ||
619c5cb6 VZ |
627 | /*********************** Inlines **********************************/ |
628 | /*********************** Fast path ********************************/ | |
9f6c9258 DK |
629 | static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) |
630 | { | |
9f6c9258 | 631 | barrier(); /* status block is written to by the chip */ |
523224a3 | 632 | fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; |
9f6c9258 DK |
633 | } |
634 | ||
f2e0899f DK |
635 | static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, |
636 | u8 segment, u16 index, u8 op, | |
637 | u8 update, u32 igu_addr) | |
638 | { | |
639 | struct igu_regular cmd_data = {0}; | |
640 | ||
641 | cmd_data.sb_id_and_flags = | |
642 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
643 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
644 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
645 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
646 | ||
51c1a580 | 647 | DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", |
f2e0899f DK |
648 | cmd_data.sb_id_and_flags, igu_addr); |
649 | REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); | |
650 | ||
651 | /* Make sure that ACK is written */ | |
652 | mmiowb(); | |
653 | barrier(); | |
654 | } | |
655 | ||
f2e0899f DK |
656 | static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, |
657 | u8 storm, u16 index, u8 op, u8 update) | |
9f6c9258 DK |
658 | { |
659 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
660 | COMMAND_REG_INT_ACK); | |
661 | struct igu_ack_register igu_ack; | |
662 | ||
663 | igu_ack.status_block_index = index; | |
664 | igu_ack.sb_id_and_flags = | |
665 | ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | | |
666 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
667 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
668 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
669 | ||
9f6c9258 DK |
670 | REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); |
671 | ||
672 | /* Make sure that ACK is written */ | |
673 | mmiowb(); | |
674 | barrier(); | |
675 | } | |
f2e0899f | 676 | |
f2e0899f DK |
677 | static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, |
678 | u16 index, u8 op, u8 update) | |
679 | { | |
680 | if (bp->common.int_block == INT_BLOCK_HC) | |
681 | bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); | |
682 | else { | |
683 | u8 segment; | |
684 | ||
685 | if (CHIP_INT_MODE_IS_BC(bp)) | |
686 | segment = storm; | |
687 | else if (igu_sb_id != bp->igu_dsb_id) | |
688 | segment = IGU_SEG_ACCESS_DEF; | |
689 | else if (storm == ATTENTION_ID) | |
690 | segment = IGU_SEG_ACCESS_ATTN; | |
691 | else | |
692 | segment = IGU_SEG_ACCESS_DEF; | |
693 | bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); | |
694 | } | |
695 | } | |
696 | ||
697 | static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) | |
9f6c9258 DK |
698 | { |
699 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
700 | COMMAND_REG_SIMD_MASK); | |
701 | u32 result = REG_RD(bp, hc_addr); | |
702 | ||
f2e0899f | 703 | barrier(); |
9f6c9258 DK |
704 | return result; |
705 | } | |
706 | ||
f2e0899f DK |
707 | static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) |
708 | { | |
709 | u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); | |
710 | u32 result = REG_RD(bp, igu_addr); | |
711 | ||
51c1a580 | 712 | DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", |
f2e0899f DK |
713 | result, igu_addr); |
714 | ||
715 | barrier(); | |
716 | return result; | |
717 | } | |
718 | ||
719 | static inline u16 bnx2x_ack_int(struct bnx2x *bp) | |
720 | { | |
721 | barrier(); | |
722 | if (bp->common.int_block == INT_BLOCK_HC) | |
723 | return bnx2x_hc_ack_int(bp); | |
724 | else | |
725 | return bnx2x_igu_ack_int(bp); | |
726 | } | |
727 | ||
6383c0b3 | 728 | static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
729 | { |
730 | /* Tell compiler that consumer and producer can change */ | |
731 | barrier(); | |
6383c0b3 | 732 | return txdata->tx_pkt_prod != txdata->tx_pkt_cons; |
9f6c9258 DK |
733 | } |
734 | ||
6383c0b3 AE |
735 | static inline u16 bnx2x_tx_avail(struct bnx2x *bp, |
736 | struct bnx2x_fp_txdata *txdata) | |
9f6c9258 DK |
737 | { |
738 | s16 used; | |
739 | u16 prod; | |
740 | u16 cons; | |
741 | ||
6383c0b3 AE |
742 | prod = txdata->tx_bd_prod; |
743 | cons = txdata->tx_bd_cons; | |
9f6c9258 | 744 | |
7b5342d9 | 745 | used = SUB_S16(prod, cons); |
9f6c9258 DK |
746 | |
747 | #ifdef BNX2X_STOP_ON_ERROR | |
748 | WARN_ON(used < 0); | |
7b5342d9 YM |
749 | WARN_ON(used > txdata->tx_ring_size); |
750 | WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); | |
9f6c9258 DK |
751 | #endif |
752 | ||
7b5342d9 | 753 | return (s16)(txdata->tx_ring_size) - used; |
9f6c9258 DK |
754 | } |
755 | ||
6383c0b3 | 756 | static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
757 | { |
758 | u16 hw_cons; | |
759 | ||
760 | /* Tell compiler that status block fields can change */ | |
761 | barrier(); | |
6383c0b3 AE |
762 | hw_cons = le16_to_cpu(*txdata->tx_cons_sb); |
763 | return hw_cons != txdata->tx_pkt_cons; | |
764 | } | |
765 | ||
766 | static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) | |
767 | { | |
768 | u8 cos; | |
769 | for_each_cos_in_tx_queue(fp, cos) | |
65565884 | 770 | if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) |
6383c0b3 AE |
771 | return true; |
772 | return false; | |
9f6c9258 DK |
773 | } |
774 | ||
75b29459 DK |
775 | #define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0) |
776 | #define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF) | |
523224a3 DK |
777 | static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) |
778 | { | |
75b29459 DK |
779 | u16 cons; |
780 | union eth_rx_cqe *cqe; | |
781 | struct eth_fast_path_rx_cqe *cqe_fp; | |
523224a3 | 782 | |
75b29459 DK |
783 | cons = RCQ_BD(fp->rx_comp_cons); |
784 | cqe = &fp->rx_comp_ring[cons]; | |
785 | cqe_fp = &cqe->fast_path_cqe; | |
786 | return BNX2X_IS_CQE_COMPLETED(cqe_fp); | |
523224a3 | 787 | } |
f85582f8 | 788 | |
f2e0899f | 789 | /** |
619c5cb6 | 790 | * bnx2x_tx_disable - disables tx from stack point of view |
f2e0899f | 791 | * |
e8920674 | 792 | * @bp: driver handle |
f2e0899f DK |
793 | */ |
794 | static inline void bnx2x_tx_disable(struct bnx2x *bp) | |
795 | { | |
796 | netif_tx_disable(bp->dev); | |
797 | netif_carrier_off(bp->dev); | |
798 | } | |
799 | ||
9f6c9258 DK |
800 | static inline void bnx2x_free_rx_sge(struct bnx2x *bp, |
801 | struct bnx2x_fastpath *fp, u16 index) | |
802 | { | |
803 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
804 | struct page *page = sw_buf->page; | |
805 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
806 | ||
807 | /* Skip "next page" elements */ | |
808 | if (!page) | |
809 | return; | |
810 | ||
811 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), | |
924d75ab | 812 | SGE_PAGES, DMA_FROM_DEVICE); |
9f6c9258 DK |
813 | __free_pages(page, PAGES_PER_SGE_SHIFT); |
814 | ||
815 | sw_buf->page = NULL; | |
816 | sge->addr_hi = 0; | |
817 | sge->addr_lo = 0; | |
818 | } | |
819 | ||
55c11941 MS |
820 | static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) |
821 | { | |
822 | int i; | |
823 | ||
8f20aa57 DK |
824 | for_each_rx_queue_cnic(bp, i) { |
825 | napi_hash_del(&bnx2x_fp(bp, i, napi)); | |
55c11941 | 826 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
8f20aa57 | 827 | } |
55c11941 MS |
828 | } |
829 | ||
d6214d7a DK |
830 | static inline void bnx2x_del_all_napi(struct bnx2x *bp) |
831 | { | |
832 | int i; | |
833 | ||
8f20aa57 DK |
834 | for_each_eth_queue(bp, i) { |
835 | napi_hash_del(&bnx2x_fp(bp, i, napi)); | |
d6214d7a | 836 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
8f20aa57 | 837 | } |
d6214d7a | 838 | } |
523224a3 | 839 | |
1ab4434c | 840 | int bnx2x_set_int_mode(struct bnx2x *bp); |
0e8d2ec5 | 841 | |
d6214d7a DK |
842 | static inline void bnx2x_disable_msi(struct bnx2x *bp) |
843 | { | |
844 | if (bp->flags & USING_MSIX_FLAG) { | |
845 | pci_disable_msix(bp->pdev); | |
30a5de77 | 846 | bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); |
d6214d7a DK |
847 | } else if (bp->flags & USING_MSI_FLAG) { |
848 | pci_disable_msi(bp->pdev); | |
849 | bp->flags &= ~USING_MSI_FLAG; | |
850 | } | |
851 | } | |
852 | ||
523224a3 | 853 | static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) |
9f6c9258 | 854 | { |
523224a3 | 855 | int i, j; |
9f6c9258 | 856 | |
523224a3 DK |
857 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { |
858 | int idx = RX_SGE_CNT * i - 1; | |
859 | ||
860 | for (j = 0; j < 2; j++) { | |
619c5cb6 | 861 | BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); |
523224a3 DK |
862 | idx--; |
863 | } | |
864 | } | |
865 | } | |
866 | ||
867 | static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) | |
868 | { | |
869 | /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ | |
b3637827 | 870 | memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); |
523224a3 DK |
871 | |
872 | /* Clear the two last indices in the page to 1: | |
873 | these are the indices that correspond to the "next" element, | |
874 | hence will never be indicated and should be removed from | |
875 | the calculations. */ | |
876 | bnx2x_clear_sge_mask_next_elems(fp); | |
9f6c9258 DK |
877 | } |
878 | ||
e52fcb24 | 879 | /* note that we are not allocating a new buffer, |
9f6c9258 DK |
880 | * we are just moving one from cons to prod |
881 | * we are not creating a new mapping, | |
882 | * so there is no need to check for dma_mapping_error(). | |
883 | */ | |
e52fcb24 | 884 | static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, |
749a8503 | 885 | u16 cons, u16 prod) |
9f6c9258 | 886 | { |
9f6c9258 DK |
887 | struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; |
888 | struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; | |
889 | struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; | |
890 | struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; | |
891 | ||
9f6c9258 DK |
892 | dma_unmap_addr_set(prod_rx_buf, mapping, |
893 | dma_unmap_addr(cons_rx_buf, mapping)); | |
e52fcb24 | 894 | prod_rx_buf->data = cons_rx_buf->data; |
9f6c9258 DK |
895 | *prod_bd = *cons_bd; |
896 | } | |
f85582f8 | 897 | |
619c5cb6 VZ |
898 | /************************* Init ******************************************/ |
899 | ||
b475d78f YM |
900 | /* returns func by VN for current port */ |
901 | static inline int func_by_vn(struct bnx2x *bp, int vn) | |
902 | { | |
903 | return 2 * vn + BP_PORT(bp); | |
904 | } | |
905 | ||
5d317c6a | 906 | static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) |
96305234 | 907 | { |
60cad4e6 | 908 | return bnx2x_rss(bp, &bp->rss_conf_obj, config_hash, true); |
96305234 DK |
909 | } |
910 | ||
619c5cb6 VZ |
911 | /** |
912 | * bnx2x_func_start - init function | |
913 | * | |
914 | * @bp: driver handle | |
915 | * | |
916 | * Must be called before sending CLIENT_SETUP for the first client. | |
917 | */ | |
918 | static inline int bnx2x_func_start(struct bnx2x *bp) | |
919 | { | |
3b603066 | 920 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 VZ |
921 | struct bnx2x_func_start_params *start_params = |
922 | &func_params.params.start; | |
923 | ||
924 | /* Prepare parameters for function state transitions */ | |
925 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
926 | ||
927 | func_params.f_obj = &bp->func_obj; | |
928 | func_params.cmd = BNX2X_F_CMD_START; | |
929 | ||
930 | /* Function parameters */ | |
931 | start_params->mf_mode = bp->mf_mode; | |
932 | start_params->sd_vlan_tag = bp->mf_ov; | |
8d7b0278 AE |
933 | |
934 | if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) | |
6383c0b3 | 935 | start_params->network_cos_mode = STATIC_COS; |
8d7b0278 AE |
936 | else /* CHIP_IS_E1X */ |
937 | start_params->network_cos_mode = FW_WRR; | |
619c5cb6 | 938 | |
e8c37aff | 939 | start_params->gre_tunnel_mode = L2GRE_TUNNEL; |
1bc277f7 DK |
940 | start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS; |
941 | ||
619c5cb6 VZ |
942 | return bnx2x_func_state_change(bp, &func_params); |
943 | } | |
944 | ||
619c5cb6 VZ |
945 | /** |
946 | * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format | |
947 | * | |
948 | * @fw_hi: pointer to upper part | |
949 | * @fw_mid: pointer to middle part | |
950 | * @fw_lo: pointer to lower part | |
951 | * @mac: pointer to MAC address | |
952 | */ | |
86564c3f YM |
953 | static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, |
954 | __le16 *fw_lo, u8 *mac) | |
619c5cb6 VZ |
955 | { |
956 | ((u8 *)fw_hi)[0] = mac[1]; | |
957 | ((u8 *)fw_hi)[1] = mac[0]; | |
958 | ((u8 *)fw_mid)[0] = mac[3]; | |
959 | ((u8 *)fw_mid)[1] = mac[2]; | |
960 | ((u8 *)fw_lo)[0] = mac[5]; | |
961 | ((u8 *)fw_lo)[1] = mac[4]; | |
962 | } | |
963 | ||
523224a3 DK |
964 | static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, |
965 | struct bnx2x_fastpath *fp, int last) | |
9f6c9258 | 966 | { |
523224a3 | 967 | int i; |
9f6c9258 | 968 | |
b3b83c3f DK |
969 | if (fp->disable_tpa) |
970 | return; | |
971 | ||
523224a3 DK |
972 | for (i = 0; i < last; i++) |
973 | bnx2x_free_rx_sge(bp, fp, i); | |
9f6c9258 DK |
974 | } |
975 | ||
523224a3 | 976 | static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) |
9f6c9258 | 977 | { |
523224a3 | 978 | int i; |
9f6c9258 | 979 | |
523224a3 DK |
980 | for (i = 1; i <= NUM_RX_RINGS; i++) { |
981 | struct eth_rx_bd *rx_bd; | |
982 | ||
983 | rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; | |
984 | rx_bd->addr_hi = | |
985 | cpu_to_le32(U64_HI(fp->rx_desc_mapping + | |
986 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
987 | rx_bd->addr_lo = | |
988 | cpu_to_le32(U64_LO(fp->rx_desc_mapping + | |
989 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
990 | } | |
9f6c9258 DK |
991 | } |
992 | ||
619c5cb6 VZ |
993 | /* Statistics ID are global per chip/path, while Client IDs for E1x are per |
994 | * port. | |
995 | */ | |
996 | static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) | |
997 | { | |
de5c3741 YM |
998 | struct bnx2x *bp = fp->bp; |
999 | if (!CHIP_IS_E1x(bp)) { | |
de5c3741 YM |
1000 | /* there are special statistics counters for FCoE 136..140 */ |
1001 | if (IS_FCOE_FP(fp)) | |
1002 | return bp->cnic_base_cl_id + (bp->pf_num >> 1); | |
619c5cb6 | 1003 | return fp->cl_id; |
de5c3741 YM |
1004 | } |
1005 | return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; | |
619c5cb6 VZ |
1006 | } |
1007 | ||
1008 | static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, | |
1009 | bnx2x_obj_type obj_type) | |
1010 | { | |
1011 | struct bnx2x *bp = fp->bp; | |
1012 | ||
1013 | /* Configure classification DBs */ | |
15192a8c BW |
1014 | bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, |
1015 | fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), | |
619c5cb6 VZ |
1016 | bnx2x_sp_mapping(bp, mac_rdata), |
1017 | BNX2X_FILTER_MAC_PENDING, | |
1018 | &bp->sp_state, obj_type, | |
1019 | &bp->macs_pool); | |
1020 | } | |
1021 | ||
1022 | /** | |
1023 | * bnx2x_get_path_func_num - get number of active functions | |
1024 | * | |
1025 | * @bp: driver handle | |
1026 | * | |
1027 | * Calculates the number of active (not hidden) functions on the | |
1028 | * current path. | |
1029 | */ | |
1030 | static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) | |
1031 | { | |
1032 | u8 func_num = 0, i; | |
1033 | ||
1034 | /* 57710 has only one function per-port */ | |
1035 | if (CHIP_IS_E1(bp)) | |
1036 | return 1; | |
1037 | ||
1038 | /* Calculate a number of functions enabled on the current | |
1039 | * PATH/PORT. | |
1040 | */ | |
1041 | if (CHIP_REV_IS_SLOW(bp)) { | |
1042 | if (IS_MF(bp)) | |
1043 | func_num = 4; | |
1044 | else | |
1045 | func_num = 2; | |
1046 | } else { | |
1047 | for (i = 0; i < E1H_FUNC_MAX / 2; i++) { | |
1048 | u32 func_config = | |
1049 | MF_CFG_RD(bp, | |
1050 | func_mf_config[BP_PORT(bp) + 2 * i]. | |
1051 | config); | |
1052 | func_num += | |
1053 | ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | WARN_ON(!func_num); | |
1058 | ||
1059 | return func_num; | |
1060 | } | |
1061 | ||
1062 | static inline void bnx2x_init_bp_objs(struct bnx2x *bp) | |
1063 | { | |
1064 | /* RX_MODE controlling object */ | |
1065 | bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); | |
1066 | ||
1067 | /* multicast configuration controlling object */ | |
1068 | bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, | |
1069 | BP_FUNC(bp), BP_FUNC(bp), | |
1070 | bnx2x_sp(bp, mcast_rdata), | |
1071 | bnx2x_sp_mapping(bp, mcast_rdata), | |
1072 | BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, | |
1073 | BNX2X_OBJ_TYPE_RX); | |
1074 | ||
1075 | /* Setup CAM credit pools */ | |
1076 | bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), | |
1077 | bnx2x_get_path_func_num(bp)); | |
1078 | ||
b56e9670 AE |
1079 | bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1, |
1080 | bnx2x_get_path_func_num(bp)); | |
1081 | ||
619c5cb6 VZ |
1082 | /* RSS configuration object */ |
1083 | bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, | |
1084 | bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), | |
1085 | bnx2x_sp(bp, rss_rdata), | |
1086 | bnx2x_sp_mapping(bp, rss_rdata), | |
1087 | BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, | |
1088 | BNX2X_OBJ_TYPE_RX); | |
1089 | } | |
1090 | ||
1091 | static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) | |
1092 | { | |
1093 | if (CHIP_IS_E1x(fp->bp)) | |
1094 | return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; | |
1095 | else | |
1096 | return fp->cl_id; | |
1097 | } | |
1098 | ||
6383c0b3 | 1099 | static inline void bnx2x_init_txdata(struct bnx2x *bp, |
65565884 MS |
1100 | struct bnx2x_fp_txdata *txdata, u32 cid, |
1101 | int txq_index, __le16 *tx_cons_sb, | |
1102 | struct bnx2x_fastpath *fp) | |
6383c0b3 AE |
1103 | { |
1104 | txdata->cid = cid; | |
1105 | txdata->txq_index = txq_index; | |
1106 | txdata->tx_cons_sb = tx_cons_sb; | |
65565884 | 1107 | txdata->parent_fp = fp; |
7b5342d9 | 1108 | txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; |
6383c0b3 | 1109 | |
51c1a580 | 1110 | DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", |
6383c0b3 AE |
1111 | txdata->cid, txdata->txq_index); |
1112 | } | |
619c5cb6 | 1113 | |
619c5cb6 VZ |
1114 | static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) |
1115 | { | |
1116 | return bp->cnic_base_cl_id + cl_idx + | |
134d0f97 | 1117 | (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; |
619c5cb6 VZ |
1118 | } |
1119 | ||
1120 | static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) | |
1121 | { | |
619c5cb6 VZ |
1122 | /* the 'first' id is allocated for the cnic */ |
1123 | return bp->base_fw_ndsb; | |
1124 | } | |
1125 | ||
1126 | static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) | |
1127 | { | |
1128 | return bp->igu_base_sb; | |
1129 | } | |
1130 | ||
619c5cb6 | 1131 | static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, |
6383c0b3 | 1132 | struct bnx2x_fp_txdata *txdata) |
619c5cb6 VZ |
1133 | { |
1134 | int cnt = 1000; | |
1135 | ||
6383c0b3 | 1136 | while (bnx2x_has_tx_work_unload(txdata)) { |
619c5cb6 | 1137 | if (!cnt) { |
51c1a580 | 1138 | BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", |
6383c0b3 AE |
1139 | txdata->txq_index, txdata->tx_pkt_prod, |
1140 | txdata->tx_pkt_cons); | |
619c5cb6 VZ |
1141 | #ifdef BNX2X_STOP_ON_ERROR |
1142 | bnx2x_panic(); | |
1143 | return -EBUSY; | |
1144 | #else | |
1145 | break; | |
1146 | #endif | |
1147 | } | |
1148 | cnt--; | |
0926d499 | 1149 | usleep_range(1000, 2000); |
619c5cb6 VZ |
1150 | } |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | ||
1ac9e428 YR |
1155 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
1156 | ||
523224a3 DK |
1157 | static inline void __storm_memset_struct(struct bnx2x *bp, |
1158 | u32 addr, size_t size, u32 *data) | |
1159 | { | |
1160 | int i; | |
1161 | for (i = 0; i < size/4; i++) | |
1162 | REG_WR(bp, addr + (i * 4), data[i]); | |
1163 | } | |
1164 | ||
619c5cb6 VZ |
1165 | /** |
1166 | * bnx2x_wait_sp_comp - wait for the outstanding SP commands. | |
1167 | * | |
1168 | * @bp: driver handle | |
1169 | * @mask: bits that need to be cleared | |
1170 | */ | |
1171 | static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) | |
1172 | { | |
1173 | int tout = 5000; /* Wait for 5 secs tops */ | |
1174 | ||
1175 | while (tout--) { | |
1176 | smp_mb(); | |
1177 | netif_addr_lock_bh(bp->dev); | |
1178 | if (!(bp->sp_state & mask)) { | |
1179 | netif_addr_unlock_bh(bp->dev); | |
1180 | return true; | |
1181 | } | |
1182 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1183 | |
0926d499 | 1184 | usleep_range(1000, 2000); |
619c5cb6 VZ |
1185 | } |
1186 | ||
1187 | smp_mb(); | |
1188 | ||
1189 | netif_addr_lock_bh(bp->dev); | |
1190 | if (bp->sp_state & mask) { | |
51c1a580 MS |
1191 | BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", |
1192 | bp->sp_state, mask); | |
619c5cb6 VZ |
1193 | netif_addr_unlock_bh(bp->dev); |
1194 | return false; | |
1195 | } | |
1196 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1197 | |
619c5cb6 | 1198 | return true; |
523224a3 | 1199 | } |
f85582f8 | 1200 | |
619c5cb6 VZ |
1201 | /** |
1202 | * bnx2x_set_ctx_validation - set CDU context validation values | |
1203 | * | |
1204 | * @bp: driver handle | |
1205 | * @cxt: context of the connection on the host memory | |
1206 | * @cid: SW CID of the connection to be configured | |
1207 | */ | |
1208 | void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, | |
1209 | u32 cid); | |
1210 | ||
1211 | void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, | |
1212 | u8 sb_index, u8 disable, u16 usec); | |
9f6c9258 DK |
1213 | void bnx2x_acquire_phy_lock(struct bnx2x *bp); |
1214 | void bnx2x_release_phy_lock(struct bnx2x *bp); | |
1215 | ||
faa6fcbb | 1216 | /** |
e8920674 | 1217 | * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. |
faa6fcbb | 1218 | * |
e8920674 DK |
1219 | * @bp: driver handle |
1220 | * @mf_cfg: MF configuration | |
faa6fcbb | 1221 | * |
faa6fcbb DK |
1222 | */ |
1223 | static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) | |
1224 | { | |
1225 | u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> | |
1226 | FUNC_MF_CFG_MAX_BW_SHIFT; | |
1227 | if (!max_cfg) { | |
51c1a580 | 1228 | DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, |
96b0accb | 1229 | "Max BW configured to 0 - using 100 instead\n"); |
faa6fcbb DK |
1230 | max_cfg = 100; |
1231 | } | |
1232 | return max_cfg; | |
1233 | } | |
1234 | ||
621b4d66 DK |
1235 | /* checks if HW supports GRO for given MTU */ |
1236 | static inline bool bnx2x_mtu_allows_gro(int mtu) | |
1237 | { | |
1238 | /* gro frags per page */ | |
1239 | int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); | |
1240 | ||
1241 | /* | |
16a5fd92 YM |
1242 | * 1. Number of frags should not grow above MAX_SKB_FRAGS |
1243 | * 2. Frag must fit the page | |
621b4d66 DK |
1244 | */ |
1245 | return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; | |
1246 | } | |
55c11941 | 1247 | |
b306f5ed DK |
1248 | /** |
1249 | * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. | |
1250 | * | |
1251 | * @bp: driver handle | |
1252 | * | |
1253 | */ | |
1254 | void bnx2x_get_iscsi_info(struct bnx2x *bp); | |
00253a8c DK |
1255 | |
1256 | /** | |
1257 | * bnx2x_link_sync_notify - send notification to other functions. | |
1258 | * | |
1259 | * @bp: driver handle | |
1260 | * | |
1261 | */ | |
1262 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) | |
1263 | { | |
1264 | int func; | |
1265 | int vn; | |
1266 | ||
1267 | /* Set the attention towards other drivers on the same port */ | |
1268 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
1269 | if (vn == BP_VN(bp)) | |
1270 | continue; | |
1271 | ||
1272 | func = func_by_vn(bp, vn); | |
1273 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + | |
1274 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); | |
1275 | } | |
1276 | } | |
1277 | ||
1278 | /** | |
1279 | * bnx2x_update_drv_flags - update flags in shmem | |
1280 | * | |
1281 | * @bp: driver handle | |
1282 | * @flags: flags to update | |
1283 | * @set: set or clear | |
1284 | * | |
1285 | */ | |
1286 | static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) | |
1287 | { | |
1288 | if (SHMEM2_HAS(bp, drv_flags)) { | |
1289 | u32 drv_flags; | |
f16da43b | 1290 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1291 | drv_flags = SHMEM2_RD(bp, drv_flags); |
1292 | ||
1293 | if (set) | |
1294 | SET_FLAGS(drv_flags, flags); | |
1295 | else | |
1296 | RESET_FLAGS(drv_flags, flags); | |
1297 | ||
1298 | SHMEM2_WR(bp, drv_flags, drv_flags); | |
51c1a580 | 1299 | DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); |
f16da43b | 1300 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1301 | } |
1302 | } | |
1303 | ||
614c76df DK |
1304 | static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) |
1305 | { | |
55c11941 MS |
1306 | if (is_valid_ether_addr(addr) || |
1307 | (is_zero_ether_addr(addr) && | |
1308 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)))) | |
614c76df | 1309 | return true; |
55c11941 | 1310 | |
614c76df DK |
1311 | return false; |
1312 | } | |
1313 | ||
8ca5e17e | 1314 | /** |
2de67439 | 1315 | * bnx2x_fill_fw_str - Fill buffer with FW version string |
8ca5e17e AE |
1316 | * |
1317 | * @bp: driver handle | |
1318 | * @buf: character buffer to fill with the fw name | |
1319 | * @buf_len: length of the above buffer | |
1320 | * | |
1321 | */ | |
1322 | void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len); | |
7fa6f340 YM |
1323 | |
1324 | int bnx2x_drain_tx_queues(struct bnx2x *bp); | |
1325 | void bnx2x_squeeze_objects(struct bnx2x *bp); | |
1326 | ||
9f6c9258 | 1327 | #endif /* BNX2X_CMN_H */ |