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4ad79e13 | 1 | /* bnx2x_cmn.h: QLogic Everest network driver. |
9f6c9258 | 2 | * |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
4ad79e13 YM |
4 | * Copyright (c) 2014 QLogic Corporation |
5 | * All rights reserved | |
9f6c9258 DK |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
08f6dd89 | 11 | * Maintained by: Ariel Elior <ariel.elior@qlogic.com> |
9f6c9258 DK |
12 | * Written by: Eliezer Tamir |
13 | * Based on code from Michael Chan's bnx2 driver | |
14 | * UDP CSUM errata workaround by Arik Gendelman | |
15 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
16 | * Statistics and Link management by Yitchak Gertner | |
17 | * | |
18 | */ | |
19 | #ifndef BNX2X_CMN_H | |
20 | #define BNX2X_CMN_H | |
21 | ||
22 | #include <linux/types.h> | |
619c5cb6 | 23 | #include <linux/pci.h> |
9f6c9258 | 24 | #include <linux/netdevice.h> |
614c76df | 25 | #include <linux/etherdevice.h> |
df1efc2d | 26 | #include <linux/irq.h> |
9f6c9258 | 27 | |
9f6c9258 | 28 | #include "bnx2x.h" |
6411280a | 29 | #include "bnx2x_sriov.h" |
9f6c9258 | 30 | |
619c5cb6 | 31 | /* This is used as a replacement for an MCP if it's not present */ |
a8f47eb7 | 32 | extern int bnx2x_load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ |
33 | extern int bnx2x_num_queues; | |
9f6c9258 | 34 | |
b3b83c3f DK |
35 | /************************ Macros ********************************/ |
36 | #define BNX2X_PCI_FREE(x, y, size) \ | |
37 | do { \ | |
38 | if (x) { \ | |
39 | dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ | |
40 | x = NULL; \ | |
41 | y = 0; \ | |
42 | } \ | |
43 | } while (0) | |
44 | ||
45 | #define BNX2X_FREE(x) \ | |
46 | do { \ | |
47 | if (x) { \ | |
48 | kfree((void *)x); \ | |
49 | x = NULL; \ | |
50 | } \ | |
51 | } while (0) | |
52 | ||
cd2b0389 JP |
53 | #define BNX2X_PCI_ALLOC(y, size) \ |
54 | ({ \ | |
55 | void *x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ | |
56 | if (x) \ | |
57 | DP(NETIF_MSG_HW, \ | |
58 | "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \ | |
59 | (unsigned long long)(*y), x); \ | |
60 | x; \ | |
61 | }) | |
62 | #define BNX2X_PCI_FALLOC(y, size) \ | |
63 | ({ \ | |
64 | void *x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ | |
65 | if (x) { \ | |
66 | memset(x, 0xff, size); \ | |
67 | DP(NETIF_MSG_HW, \ | |
68 | "BNX2X_PCI_FALLOC: Physical %Lx Virtual %p\n", \ | |
69 | (unsigned long long)(*y), x); \ | |
70 | } \ | |
71 | x; \ | |
72 | }) | |
b3b83c3f | 73 | |
9f6c9258 DK |
74 | /*********************** Interfaces **************************** |
75 | * Functions that need to be implemented by each driver version | |
76 | */ | |
619c5cb6 VZ |
77 | /* Init */ |
78 | ||
79 | /** | |
80 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
81 | * | |
82 | * @bp: driver handle | |
83 | * @unload_mode: requested function's unload mode | |
84 | * | |
85 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
86 | */ | |
87 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); | |
88 | ||
89 | /** | |
90 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
91 | * | |
92 | * @bp: driver handle | |
5d07d868 | 93 | * @keep_link: true iff link should be kept up |
619c5cb6 | 94 | */ |
5d07d868 | 95 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link); |
619c5cb6 VZ |
96 | |
97 | /** | |
96305234 | 98 | * bnx2x_config_rss_pf - configure RSS parameters in a PF. |
619c5cb6 VZ |
99 | * |
100 | * @bp: driver handle | |
49ce9c2c | 101 | * @rss_obj: RSS object to use |
619c5cb6 VZ |
102 | * @ind_table: indirection table to configure |
103 | * @config_hash: re-configure RSS hash keys configuration | |
60cad4e6 | 104 | * @enable: enabled or disabled configuration |
619c5cb6 | 105 | */ |
60cad4e6 AE |
106 | int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, |
107 | bool config_hash, bool enable); | |
619c5cb6 VZ |
108 | |
109 | /** | |
110 | * bnx2x__init_func_obj - init function object | |
111 | * | |
112 | * @bp: driver handle | |
113 | * | |
114 | * Initializes the Function Object with the appropriate | |
115 | * parameters which include a function slow path driver | |
116 | * interface. | |
117 | */ | |
118 | void bnx2x__init_func_obj(struct bnx2x *bp); | |
119 | ||
120 | /** | |
121 | * bnx2x_setup_queue - setup eth queue. | |
122 | * | |
123 | * @bp: driver handle | |
124 | * @fp: pointer to the fastpath structure | |
125 | * @leading: boolean | |
126 | * | |
127 | */ | |
128 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
129 | bool leading); | |
130 | ||
131 | /** | |
132 | * bnx2x_setup_leading - bring up a leading eth queue. | |
133 | * | |
134 | * @bp: driver handle | |
135 | */ | |
136 | int bnx2x_setup_leading(struct bnx2x *bp); | |
137 | ||
138 | /** | |
139 | * bnx2x_fw_command - send the MCP a request | |
140 | * | |
141 | * @bp: driver handle | |
142 | * @command: request | |
143 | * @param: request's parameter | |
144 | * | |
145 | * block until there is a reply | |
146 | */ | |
147 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); | |
9f6c9258 DK |
148 | |
149 | /** | |
e8920674 | 150 | * bnx2x_initial_phy_init - initialize link parameters structure variables. |
9f6c9258 | 151 | * |
e8920674 DK |
152 | * @bp: driver handle |
153 | * @load_mode: current mode | |
9f6c9258 | 154 | */ |
cd1dfce2 | 155 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); |
9f6c9258 DK |
156 | |
157 | /** | |
e8920674 | 158 | * bnx2x_link_set - configure hw according to link parameters structure. |
9f6c9258 | 159 | * |
e8920674 | 160 | * @bp: driver handle |
9f6c9258 DK |
161 | */ |
162 | void bnx2x_link_set(struct bnx2x *bp); | |
163 | ||
5d07d868 YM |
164 | /** |
165 | * bnx2x_force_link_reset - Forces link reset, and put the PHY | |
166 | * in reset as well. | |
167 | * | |
168 | * @bp: driver handle | |
169 | */ | |
170 | void bnx2x_force_link_reset(struct bnx2x *bp); | |
171 | ||
9f6c9258 | 172 | /** |
e8920674 | 173 | * bnx2x_link_test - query link status. |
9f6c9258 | 174 | * |
e8920674 DK |
175 | * @bp: driver handle |
176 | * @is_serdes: bool | |
9f6c9258 | 177 | * |
e8920674 | 178 | * Returns 0 if link is UP. |
9f6c9258 | 179 | */ |
a22f0788 | 180 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); |
9f6c9258 | 181 | |
619c5cb6 VZ |
182 | /** |
183 | * bnx2x_drv_pulse - write driver pulse to shmem | |
184 | * | |
185 | * @bp: driver handle | |
186 | * | |
187 | * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox | |
188 | * in the shmem. | |
189 | */ | |
190 | void bnx2x_drv_pulse(struct bnx2x *bp); | |
191 | ||
192 | /** | |
193 | * bnx2x_igu_ack_sb - update IGU with current SB value | |
194 | * | |
195 | * @bp: driver handle | |
196 | * @igu_sb_id: SB id | |
197 | * @segment: SB segment | |
198 | * @index: SB index | |
199 | * @op: SB operation | |
200 | * @update: is HW update required | |
201 | */ | |
202 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, | |
203 | u16 index, u8 op, u8 update); | |
204 | ||
c9ee9206 VZ |
205 | /* Disable transactions from chip to host */ |
206 | void bnx2x_pf_disable(struct bnx2x *bp); | |
07ba6af4 | 207 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); |
c9ee9206 | 208 | |
9f6c9258 | 209 | /** |
e8920674 | 210 | * bnx2x__link_status_update - handles link status change. |
9f6c9258 | 211 | * |
e8920674 | 212 | * @bp: driver handle |
9f6c9258 DK |
213 | */ |
214 | void bnx2x__link_status_update(struct bnx2x *bp); | |
215 | ||
f85582f8 | 216 | /** |
e8920674 | 217 | * bnx2x_link_report - report link status to upper layer. |
f85582f8 | 218 | * |
e8920674 | 219 | * @bp: driver handle |
f85582f8 DK |
220 | */ |
221 | void bnx2x_link_report(struct bnx2x *bp); | |
222 | ||
2ae17f66 VZ |
223 | /* None-atomic version of bnx2x_link_report() */ |
224 | void __bnx2x_link_report(struct bnx2x *bp); | |
225 | ||
0793f83f | 226 | /** |
e8920674 | 227 | * bnx2x_get_mf_speed - calculate MF speed. |
0793f83f | 228 | * |
e8920674 | 229 | * @bp: driver handle |
0793f83f | 230 | * |
e8920674 | 231 | * Takes into account current linespeed and MF configuration. |
0793f83f DK |
232 | */ |
233 | u16 bnx2x_get_mf_speed(struct bnx2x *bp); | |
234 | ||
9f6c9258 | 235 | /** |
e8920674 | 236 | * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler |
9f6c9258 | 237 | * |
e8920674 DK |
238 | * @irq: irq number |
239 | * @dev_instance: private instance | |
9f6c9258 DK |
240 | */ |
241 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); | |
242 | ||
243 | /** | |
e8920674 | 244 | * bnx2x_interrupt - non MSI-X interrupt handler |
9f6c9258 | 245 | * |
e8920674 DK |
246 | * @irq: irq number |
247 | * @dev_instance: private instance | |
9f6c9258 DK |
248 | */ |
249 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); | |
9f6c9258 DK |
250 | |
251 | /** | |
e8920674 | 252 | * bnx2x_cnic_notify - send command to cnic driver |
9f6c9258 | 253 | * |
e8920674 DK |
254 | * @bp: driver handle |
255 | * @cmd: command | |
9f6c9258 DK |
256 | */ |
257 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); | |
258 | ||
259 | /** | |
e8920674 | 260 | * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information |
9f6c9258 | 261 | * |
e8920674 | 262 | * @bp: driver handle |
9f6c9258 DK |
263 | */ |
264 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); | |
37ae41a9 MS |
265 | |
266 | /** | |
267 | * bnx2x_setup_cnic_info - provides cnic with updated info | |
268 | * | |
269 | * @bp: driver handle | |
270 | */ | |
271 | void bnx2x_setup_cnic_info(struct bnx2x *bp); | |
272 | ||
9f6c9258 | 273 | /** |
e8920674 | 274 | * bnx2x_int_enable - enable HW interrupts. |
9f6c9258 | 275 | * |
e8920674 | 276 | * @bp: driver handle |
9f6c9258 DK |
277 | */ |
278 | void bnx2x_int_enable(struct bnx2x *bp); | |
279 | ||
280 | /** | |
e8920674 DK |
281 | * bnx2x_int_disable_sync - disable interrupts. |
282 | * | |
283 | * @bp: driver handle | |
284 | * @disable_hw: true, disable HW interrupts. | |
9f6c9258 | 285 | * |
e8920674 DK |
286 | * This function ensures that there are no |
287 | * ISRs or SP DPCs (sp_task) are running after it returns. | |
9f6c9258 DK |
288 | */ |
289 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); | |
290 | ||
9f6c9258 | 291 | /** |
55c11941 | 292 | * bnx2x_nic_init_cnic - init driver internals for cnic. |
e8920674 DK |
293 | * |
294 | * @bp: driver handle | |
295 | * @load_code: COMMON, PORT or FUNCTION | |
296 | * | |
297 | * Initializes: | |
9f6c9258 DK |
298 | * - rings |
299 | * - status blocks | |
300 | * - etc. | |
9f6c9258 | 301 | */ |
55c11941 | 302 | void bnx2x_nic_init_cnic(struct bnx2x *bp); |
9f6c9258 | 303 | |
55c11941 | 304 | /** |
ecf01c22 | 305 | * bnx2x_preirq_nic_init - init driver internals. |
55c11941 MS |
306 | * |
307 | * @bp: driver handle | |
308 | * | |
309 | * Initializes: | |
ecf01c22 YM |
310 | * - fastpath object |
311 | * - fastpath rings | |
312 | * etc. | |
313 | */ | |
314 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp); | |
315 | ||
316 | /** | |
317 | * bnx2x_postirq_nic_init - init driver internals. | |
318 | * | |
319 | * @bp: driver handle | |
320 | * @load_code: COMMON, PORT or FUNCTION | |
321 | * | |
322 | * Initializes: | |
55c11941 | 323 | * - status blocks |
ecf01c22 | 324 | * - slowpath rings |
55c11941 MS |
325 | * - etc. |
326 | */ | |
ecf01c22 | 327 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code); |
55c11941 MS |
328 | /** |
329 | * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. | |
330 | * | |
331 | * @bp: driver handle | |
332 | */ | |
333 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp); | |
9f6c9258 | 334 | /** |
e8920674 | 335 | * bnx2x_alloc_mem - allocate driver's memory. |
9f6c9258 | 336 | * |
e8920674 | 337 | * @bp: driver handle |
9f6c9258 DK |
338 | */ |
339 | int bnx2x_alloc_mem(struct bnx2x *bp); | |
340 | ||
55c11941 MS |
341 | /** |
342 | * bnx2x_free_mem_cnic - release driver's memory for cnic. | |
343 | * | |
344 | * @bp: driver handle | |
345 | */ | |
346 | void bnx2x_free_mem_cnic(struct bnx2x *bp); | |
9f6c9258 | 347 | /** |
e8920674 | 348 | * bnx2x_free_mem - release driver's memory. |
9f6c9258 | 349 | * |
e8920674 | 350 | * @bp: driver handle |
9f6c9258 DK |
351 | */ |
352 | void bnx2x_free_mem(struct bnx2x *bp); | |
353 | ||
9f6c9258 | 354 | /** |
e8920674 | 355 | * bnx2x_set_num_queues - set number of queues according to mode. |
9f6c9258 | 356 | * |
e8920674 | 357 | * @bp: driver handle |
9f6c9258 | 358 | */ |
d6214d7a | 359 | void bnx2x_set_num_queues(struct bnx2x *bp); |
9f6c9258 DK |
360 | |
361 | /** | |
e8920674 DK |
362 | * bnx2x_chip_cleanup - cleanup chip internals. |
363 | * | |
364 | * @bp: driver handle | |
365 | * @unload_mode: COMMON, PORT, FUNCTION | |
5d07d868 | 366 | * @keep_link: true iff link should be kept up. |
e8920674 | 367 | * |
9f6c9258 | 368 | * - Cleanup MAC configuration. |
e8920674 | 369 | * - Closes clients. |
9f6c9258 | 370 | * - etc. |
9f6c9258 | 371 | */ |
5d07d868 | 372 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link); |
9f6c9258 DK |
373 | |
374 | /** | |
e8920674 | 375 | * bnx2x_acquire_hw_lock - acquire HW lock. |
9f6c9258 | 376 | * |
e8920674 DK |
377 | * @bp: driver handle |
378 | * @resource: resource bit which was locked | |
9f6c9258 DK |
379 | */ |
380 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); | |
381 | ||
382 | /** | |
e8920674 | 383 | * bnx2x_release_hw_lock - release HW lock. |
9f6c9258 | 384 | * |
e8920674 DK |
385 | * @bp: driver handle |
386 | * @resource: resource bit which was locked | |
9f6c9258 DK |
387 | */ |
388 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); | |
389 | ||
c9ee9206 VZ |
390 | /** |
391 | * bnx2x_release_leader_lock - release recovery leader lock | |
392 | * | |
393 | * @bp: driver handle | |
394 | */ | |
395 | int bnx2x_release_leader_lock(struct bnx2x *bp); | |
396 | ||
9f6c9258 | 397 | /** |
e8920674 DK |
398 | * bnx2x_set_eth_mac - configure eth MAC address in the HW |
399 | * | |
400 | * @bp: driver handle | |
401 | * @set: set or clear | |
9f6c9258 | 402 | * |
e8920674 | 403 | * Configures according to the value in netdev->dev_addr. |
9f6c9258 | 404 | */ |
619c5cb6 | 405 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); |
9f6c9258 | 406 | |
ec6ba945 | 407 | /** |
619c5cb6 | 408 | * bnx2x_set_rx_mode - set MAC filtering configurations. |
ec6ba945 | 409 | * |
619c5cb6 | 410 | * @dev: netdevice |
ec6ba945 | 411 | * |
619c5cb6 VZ |
412 | * called with netif_tx_lock from dev_mcast.c |
413 | * If bp->state is OPEN, should be called with | |
414 | * netif_addr_lock_bh() | |
ec6ba945 | 415 | */ |
8b09be5f | 416 | void bnx2x_set_rx_mode_inner(struct bnx2x *bp); |
ec6ba945 | 417 | |
9f6c9258 | 418 | /* Parity errors related */ |
889b9af3 AE |
419 | void bnx2x_set_pf_load(struct bnx2x *bp); |
420 | bool bnx2x_clear_pf_load(struct bnx2x *bp); | |
c9ee9206 VZ |
421 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); |
422 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); | |
423 | void bnx2x_set_reset_in_progress(struct bnx2x *bp); | |
424 | void bnx2x_set_reset_global(struct bnx2x *bp); | |
9f6c9258 | 425 | void bnx2x_disable_close_the_gate(struct bnx2x *bp); |
55c11941 | 426 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp); |
9f6c9258 | 427 | |
9f6c9258 | 428 | /** |
e8920674 | 429 | * bnx2x_sp_event - handle ramrods completion. |
9f6c9258 | 430 | * |
e8920674 DK |
431 | * @fp: fastpath handle for the event |
432 | * @rr_cqe: eth_rx_cqe | |
9f6c9258 | 433 | */ |
f85582f8 | 434 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); |
9f6c9258 | 435 | |
523224a3 | 436 | /** |
e8920674 | 437 | * bnx2x_ilt_set_info - prepare ILT configurations. |
523224a3 | 438 | * |
e8920674 | 439 | * @bp: driver handle |
523224a3 DK |
440 | */ |
441 | void bnx2x_ilt_set_info(struct bnx2x *bp); | |
9f6c9258 | 442 | |
55c11941 MS |
443 | /** |
444 | * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC | |
445 | * and TM. | |
446 | * | |
447 | * @bp: driver handle | |
448 | */ | |
449 | void bnx2x_ilt_set_info_cnic(struct bnx2x *bp); | |
450 | ||
e4901dde | 451 | /** |
e8920674 | 452 | * bnx2x_dcbx_init - initialize dcbx protocol. |
e4901dde | 453 | * |
e8920674 | 454 | * @bp: driver handle |
e4901dde | 455 | */ |
9876879f | 456 | void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); |
e4901dde | 457 | |
f85582f8 | 458 | /** |
e8920674 | 459 | * bnx2x_set_power_state - set power state to the requested value. |
f85582f8 | 460 | * |
e8920674 DK |
461 | * @bp: driver handle |
462 | * @state: required state D0 or D3hot | |
f85582f8 | 463 | * |
e8920674 | 464 | * Currently only D0 and D3hot are supported. |
f85582f8 DK |
465 | */ |
466 | int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); | |
467 | ||
e3835b99 | 468 | /** |
e8920674 | 469 | * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. |
e3835b99 | 470 | * |
e8920674 DK |
471 | * @bp: driver handle |
472 | * @value: new value | |
e3835b99 DK |
473 | */ |
474 | void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); | |
619c5cb6 | 475 | /* Error handling */ |
7a25cc73 DK |
476 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); |
477 | ||
f85582f8 | 478 | /* dev_close main block */ |
5d07d868 | 479 | int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link); |
f85582f8 DK |
480 | |
481 | /* dev_open main block */ | |
482 | int bnx2x_nic_load(struct bnx2x *bp, int load_mode); | |
483 | ||
484 | /* hard_xmit callback */ | |
485 | netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
486 | ||
6383c0b3 AE |
487 | /* setup_tc callback */ |
488 | int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); | |
16e5cc64 JF |
489 | int __bnx2x_setup_tc(struct net_device *dev, u32 handle, __be16 proto, |
490 | struct tc_to_netdev *tc); | |
6383c0b3 | 491 | |
3ec9f9ca AE |
492 | int bnx2x_get_vf_config(struct net_device *dev, int vf, |
493 | struct ifla_vf_info *ivi); | |
abc5a021 | 494 | int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac); |
79aab093 MS |
495 | int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, |
496 | __be16 vlan_proto); | |
abc5a021 | 497 | |
8307fa3e | 498 | /* select_queue callback */ |
f663dd9a | 499 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 500 | void *accel_priv, select_queue_fallback_t fallback); |
8307fa3e | 501 | |
dc1ba591 AE |
502 | static inline void bnx2x_update_rx_prod(struct bnx2x *bp, |
503 | struct bnx2x_fastpath *fp, | |
504 | u16 bd_prod, u16 rx_comp_prod, | |
505 | u16 rx_sge_prod) | |
506 | { | |
507 | struct ustorm_eth_rx_producers rx_prods = {0}; | |
508 | u32 i; | |
509 | ||
510 | /* Update producers */ | |
511 | rx_prods.bd_prod = bd_prod; | |
512 | rx_prods.cqe_prod = rx_comp_prod; | |
513 | rx_prods.sge_prod = rx_sge_prod; | |
514 | ||
515 | /* Make sure that the BD and SGE data is updated before updating the | |
516 | * producers since FW might read the BD/SGE right after the producer | |
517 | * is updated. | |
518 | * This is only applicable for weak-ordered memory model archs such | |
519 | * as IA-64. The following barrier is also mandatory since FW will | |
520 | * assumes BDs must have buffers. | |
521 | */ | |
522 | wmb(); | |
523 | ||
524 | for (i = 0; i < sizeof(rx_prods)/4; i++) | |
525 | REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, | |
526 | ((u32 *)&rx_prods)[i]); | |
527 | ||
528 | mmiowb(); /* keep prod updates ordered */ | |
529 | ||
530 | DP(NETIF_MSG_RX_STATUS, | |
531 | "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", | |
532 | fp->index, bd_prod, rx_comp_prod, rx_sge_prod); | |
533 | } | |
534 | ||
a9fccec7 DK |
535 | /* reload helper */ |
536 | int bnx2x_reload_if_running(struct net_device *dev); | |
537 | ||
f85582f8 DK |
538 | int bnx2x_change_mac_addr(struct net_device *dev, void *p); |
539 | ||
f85582f8 | 540 | /* NAPI poll Tx part */ |
6383c0b3 | 541 | int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); |
f85582f8 DK |
542 | |
543 | /* suspend/resume callbacks */ | |
544 | int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); | |
545 | int bnx2x_resume(struct pci_dev *pdev); | |
546 | ||
547 | /* Release IRQ vectors */ | |
548 | void bnx2x_free_irq(struct bnx2x *bp); | |
549 | ||
b3b83c3f | 550 | void bnx2x_free_fp_mem(struct bnx2x *bp); |
f85582f8 | 551 | void bnx2x_init_rx_rings(struct bnx2x *bp); |
55c11941 | 552 | void bnx2x_init_rx_rings_cnic(struct bnx2x *bp); |
f85582f8 DK |
553 | void bnx2x_free_skbs(struct bnx2x *bp); |
554 | void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); | |
555 | void bnx2x_netif_start(struct bnx2x *bp); | |
55c11941 | 556 | int bnx2x_load_cnic(struct bnx2x *bp); |
f85582f8 | 557 | |
d6214d7a | 558 | /** |
e8920674 | 559 | * bnx2x_enable_msix - set msix configuration. |
d6214d7a | 560 | * |
e8920674 | 561 | * @bp: driver handle |
d6214d7a | 562 | * |
e8920674 DK |
563 | * fills msix_table, requests vectors, updates num_queues |
564 | * according to number of available vectors. | |
d6214d7a | 565 | */ |
0e8d2ec5 | 566 | int bnx2x_enable_msix(struct bnx2x *bp); |
d6214d7a DK |
567 | |
568 | /** | |
e8920674 | 569 | * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly |
d6214d7a | 570 | * |
e8920674 | 571 | * @bp: driver handle |
d6214d7a DK |
572 | */ |
573 | int bnx2x_enable_msi(struct bnx2x *bp); | |
574 | ||
f85582f8 | 575 | /** |
e8920674 | 576 | * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure |
f85582f8 | 577 | * |
e8920674 | 578 | * @bp: driver handle |
f85582f8 | 579 | */ |
0329aba1 | 580 | int bnx2x_alloc_mem_bp(struct bnx2x *bp); |
e8920674 DK |
581 | |
582 | /** | |
583 | * bnx2x_free_mem_bp - release memories outsize main driver structure | |
584 | * | |
585 | * @bp: driver handle | |
586 | */ | |
f85582f8 DK |
587 | void bnx2x_free_mem_bp(struct bnx2x *bp); |
588 | ||
589 | /** | |
e8920674 | 590 | * bnx2x_change_mtu - change mtu netdev callback |
f85582f8 | 591 | * |
e8920674 DK |
592 | * @dev: net device |
593 | * @new_mtu: requested mtu | |
f85582f8 | 594 | * |
f85582f8 DK |
595 | */ |
596 | int bnx2x_change_mtu(struct net_device *dev, int new_mtu); | |
597 | ||
55c11941 | 598 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
599 | /** |
600 | * bnx2x_fcoe_get_wwn - return the requested WWN value for this port | |
601 | * | |
602 | * @dev: net_device | |
603 | * @wwn: output buffer | |
604 | * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) | |
605 | * | |
606 | */ | |
607 | int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); | |
608 | #endif | |
621b4d66 | 609 | |
c8f44aff | 610 | netdev_features_t bnx2x_fix_features(struct net_device *dev, |
621b4d66 | 611 | netdev_features_t features); |
c8f44aff | 612 | int bnx2x_set_features(struct net_device *dev, netdev_features_t features); |
66371c44 | 613 | |
f85582f8 | 614 | /** |
e8920674 | 615 | * bnx2x_tx_timeout - tx timeout netdev callback |
f85582f8 | 616 | * |
e8920674 | 617 | * @dev: net device |
f85582f8 DK |
618 | */ |
619 | void bnx2x_tx_timeout(struct net_device *dev); | |
620 | ||
230d00eb YM |
621 | /** bnx2x_get_c2s_mapping - read inner-to-outer vlan configuration |
622 | * c2s_map should have BNX2X_MAX_PRIORITY entries. | |
623 | * @bp: driver handle | |
624 | * @c2s_map: should have BNX2X_MAX_PRIORITY entries for mapping | |
625 | * @c2s_default: entry for non-tagged configuration | |
626 | */ | |
627 | void bnx2x_get_c2s_mapping(struct bnx2x *bp, u8 *c2s_map, u8 *c2s_default); | |
628 | ||
619c5cb6 VZ |
629 | /*********************** Inlines **********************************/ |
630 | /*********************** Fast path ********************************/ | |
9f6c9258 DK |
631 | static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) |
632 | { | |
9f6c9258 | 633 | barrier(); /* status block is written to by the chip */ |
523224a3 | 634 | fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; |
9f6c9258 DK |
635 | } |
636 | ||
f2e0899f DK |
637 | static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, |
638 | u8 segment, u16 index, u8 op, | |
639 | u8 update, u32 igu_addr) | |
640 | { | |
641 | struct igu_regular cmd_data = {0}; | |
642 | ||
643 | cmd_data.sb_id_and_flags = | |
644 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
645 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
646 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
647 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
648 | ||
51c1a580 | 649 | DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", |
f2e0899f DK |
650 | cmd_data.sb_id_and_flags, igu_addr); |
651 | REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); | |
652 | ||
653 | /* Make sure that ACK is written */ | |
654 | mmiowb(); | |
655 | barrier(); | |
656 | } | |
657 | ||
f2e0899f DK |
658 | static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, |
659 | u8 storm, u16 index, u8 op, u8 update) | |
9f6c9258 DK |
660 | { |
661 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
662 | COMMAND_REG_INT_ACK); | |
663 | struct igu_ack_register igu_ack; | |
664 | ||
665 | igu_ack.status_block_index = index; | |
666 | igu_ack.sb_id_and_flags = | |
667 | ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | | |
668 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
669 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
670 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
671 | ||
9f6c9258 DK |
672 | REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); |
673 | ||
674 | /* Make sure that ACK is written */ | |
675 | mmiowb(); | |
676 | barrier(); | |
677 | } | |
f2e0899f | 678 | |
f2e0899f DK |
679 | static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, |
680 | u16 index, u8 op, u8 update) | |
681 | { | |
682 | if (bp->common.int_block == INT_BLOCK_HC) | |
683 | bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); | |
684 | else { | |
685 | u8 segment; | |
686 | ||
687 | if (CHIP_INT_MODE_IS_BC(bp)) | |
688 | segment = storm; | |
689 | else if (igu_sb_id != bp->igu_dsb_id) | |
690 | segment = IGU_SEG_ACCESS_DEF; | |
691 | else if (storm == ATTENTION_ID) | |
692 | segment = IGU_SEG_ACCESS_ATTN; | |
693 | else | |
694 | segment = IGU_SEG_ACCESS_DEF; | |
695 | bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); | |
696 | } | |
697 | } | |
698 | ||
699 | static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) | |
9f6c9258 DK |
700 | { |
701 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
702 | COMMAND_REG_SIMD_MASK); | |
703 | u32 result = REG_RD(bp, hc_addr); | |
704 | ||
f2e0899f | 705 | barrier(); |
9f6c9258 DK |
706 | return result; |
707 | } | |
708 | ||
f2e0899f DK |
709 | static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) |
710 | { | |
711 | u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); | |
712 | u32 result = REG_RD(bp, igu_addr); | |
713 | ||
51c1a580 | 714 | DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", |
f2e0899f DK |
715 | result, igu_addr); |
716 | ||
717 | barrier(); | |
718 | return result; | |
719 | } | |
720 | ||
721 | static inline u16 bnx2x_ack_int(struct bnx2x *bp) | |
722 | { | |
723 | barrier(); | |
724 | if (bp->common.int_block == INT_BLOCK_HC) | |
725 | return bnx2x_hc_ack_int(bp); | |
726 | else | |
727 | return bnx2x_igu_ack_int(bp); | |
728 | } | |
729 | ||
6383c0b3 | 730 | static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
731 | { |
732 | /* Tell compiler that consumer and producer can change */ | |
733 | barrier(); | |
6383c0b3 | 734 | return txdata->tx_pkt_prod != txdata->tx_pkt_cons; |
9f6c9258 DK |
735 | } |
736 | ||
6383c0b3 AE |
737 | static inline u16 bnx2x_tx_avail(struct bnx2x *bp, |
738 | struct bnx2x_fp_txdata *txdata) | |
9f6c9258 DK |
739 | { |
740 | s16 used; | |
741 | u16 prod; | |
742 | u16 cons; | |
743 | ||
6383c0b3 AE |
744 | prod = txdata->tx_bd_prod; |
745 | cons = txdata->tx_bd_cons; | |
9f6c9258 | 746 | |
7b5342d9 | 747 | used = SUB_S16(prod, cons); |
9f6c9258 DK |
748 | |
749 | #ifdef BNX2X_STOP_ON_ERROR | |
750 | WARN_ON(used < 0); | |
7b5342d9 YM |
751 | WARN_ON(used > txdata->tx_ring_size); |
752 | WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); | |
9f6c9258 DK |
753 | #endif |
754 | ||
7b5342d9 | 755 | return (s16)(txdata->tx_ring_size) - used; |
9f6c9258 DK |
756 | } |
757 | ||
6383c0b3 | 758 | static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
759 | { |
760 | u16 hw_cons; | |
761 | ||
762 | /* Tell compiler that status block fields can change */ | |
763 | barrier(); | |
6383c0b3 AE |
764 | hw_cons = le16_to_cpu(*txdata->tx_cons_sb); |
765 | return hw_cons != txdata->tx_pkt_cons; | |
766 | } | |
767 | ||
768 | static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) | |
769 | { | |
770 | u8 cos; | |
771 | for_each_cos_in_tx_queue(fp, cos) | |
65565884 | 772 | if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) |
6383c0b3 AE |
773 | return true; |
774 | return false; | |
9f6c9258 DK |
775 | } |
776 | ||
75b29459 DK |
777 | #define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0) |
778 | #define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF) | |
523224a3 DK |
779 | static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) |
780 | { | |
75b29459 DK |
781 | u16 cons; |
782 | union eth_rx_cqe *cqe; | |
783 | struct eth_fast_path_rx_cqe *cqe_fp; | |
523224a3 | 784 | |
75b29459 DK |
785 | cons = RCQ_BD(fp->rx_comp_cons); |
786 | cqe = &fp->rx_comp_ring[cons]; | |
787 | cqe_fp = &cqe->fast_path_cqe; | |
788 | return BNX2X_IS_CQE_COMPLETED(cqe_fp); | |
523224a3 | 789 | } |
f85582f8 | 790 | |
f2e0899f | 791 | /** |
619c5cb6 | 792 | * bnx2x_tx_disable - disables tx from stack point of view |
f2e0899f | 793 | * |
e8920674 | 794 | * @bp: driver handle |
f2e0899f DK |
795 | */ |
796 | static inline void bnx2x_tx_disable(struct bnx2x *bp) | |
797 | { | |
798 | netif_tx_disable(bp->dev); | |
799 | netif_carrier_off(bp->dev); | |
800 | } | |
801 | ||
9f6c9258 DK |
802 | static inline void bnx2x_free_rx_sge(struct bnx2x *bp, |
803 | struct bnx2x_fastpath *fp, u16 index) | |
804 | { | |
805 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
806 | struct page *page = sw_buf->page; | |
807 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
808 | ||
809 | /* Skip "next page" elements */ | |
810 | if (!page) | |
811 | return; | |
812 | ||
4cace675 GKB |
813 | /* Since many fragments can share the same page, make sure to |
814 | * only unmap and free the page once. | |
815 | */ | |
8031612d MS |
816 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), |
817 | SGE_PAGE_SIZE, DMA_FROM_DEVICE); | |
4cace675 GKB |
818 | |
819 | put_page(page); | |
9f6c9258 DK |
820 | |
821 | sw_buf->page = NULL; | |
822 | sge->addr_hi = 0; | |
823 | sge->addr_lo = 0; | |
824 | } | |
825 | ||
55c11941 MS |
826 | static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) |
827 | { | |
828 | int i; | |
829 | ||
8f20aa57 DK |
830 | for_each_rx_queue_cnic(bp, i) { |
831 | napi_hash_del(&bnx2x_fp(bp, i, napi)); | |
55c11941 | 832 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
8f20aa57 | 833 | } |
55c11941 MS |
834 | } |
835 | ||
d6214d7a DK |
836 | static inline void bnx2x_del_all_napi(struct bnx2x *bp) |
837 | { | |
838 | int i; | |
839 | ||
8f20aa57 DK |
840 | for_each_eth_queue(bp, i) { |
841 | napi_hash_del(&bnx2x_fp(bp, i, napi)); | |
d6214d7a | 842 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
8f20aa57 | 843 | } |
d6214d7a | 844 | } |
523224a3 | 845 | |
1ab4434c | 846 | int bnx2x_set_int_mode(struct bnx2x *bp); |
0e8d2ec5 | 847 | |
d6214d7a DK |
848 | static inline void bnx2x_disable_msi(struct bnx2x *bp) |
849 | { | |
850 | if (bp->flags & USING_MSIX_FLAG) { | |
851 | pci_disable_msix(bp->pdev); | |
30a5de77 | 852 | bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); |
d6214d7a DK |
853 | } else if (bp->flags & USING_MSI_FLAG) { |
854 | pci_disable_msi(bp->pdev); | |
855 | bp->flags &= ~USING_MSI_FLAG; | |
856 | } | |
857 | } | |
858 | ||
523224a3 | 859 | static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) |
9f6c9258 | 860 | { |
523224a3 | 861 | int i, j; |
9f6c9258 | 862 | |
523224a3 DK |
863 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { |
864 | int idx = RX_SGE_CNT * i - 1; | |
865 | ||
866 | for (j = 0; j < 2; j++) { | |
619c5cb6 | 867 | BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); |
523224a3 DK |
868 | idx--; |
869 | } | |
870 | } | |
871 | } | |
872 | ||
873 | static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) | |
874 | { | |
875 | /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ | |
b3637827 | 876 | memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); |
523224a3 DK |
877 | |
878 | /* Clear the two last indices in the page to 1: | |
879 | these are the indices that correspond to the "next" element, | |
880 | hence will never be indicated and should be removed from | |
881 | the calculations. */ | |
882 | bnx2x_clear_sge_mask_next_elems(fp); | |
9f6c9258 DK |
883 | } |
884 | ||
e52fcb24 | 885 | /* note that we are not allocating a new buffer, |
9f6c9258 DK |
886 | * we are just moving one from cons to prod |
887 | * we are not creating a new mapping, | |
888 | * so there is no need to check for dma_mapping_error(). | |
889 | */ | |
e52fcb24 | 890 | static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, |
749a8503 | 891 | u16 cons, u16 prod) |
9f6c9258 | 892 | { |
9f6c9258 DK |
893 | struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; |
894 | struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; | |
895 | struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; | |
896 | struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; | |
897 | ||
9f6c9258 DK |
898 | dma_unmap_addr_set(prod_rx_buf, mapping, |
899 | dma_unmap_addr(cons_rx_buf, mapping)); | |
e52fcb24 | 900 | prod_rx_buf->data = cons_rx_buf->data; |
9f6c9258 DK |
901 | *prod_bd = *cons_bd; |
902 | } | |
f85582f8 | 903 | |
619c5cb6 VZ |
904 | /************************* Init ******************************************/ |
905 | ||
b475d78f YM |
906 | /* returns func by VN for current port */ |
907 | static inline int func_by_vn(struct bnx2x *bp, int vn) | |
908 | { | |
909 | return 2 * vn + BP_PORT(bp); | |
910 | } | |
911 | ||
5d317c6a | 912 | static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) |
96305234 | 913 | { |
60cad4e6 | 914 | return bnx2x_rss(bp, &bp->rss_conf_obj, config_hash, true); |
96305234 DK |
915 | } |
916 | ||
619c5cb6 VZ |
917 | /** |
918 | * bnx2x_func_start - init function | |
919 | * | |
920 | * @bp: driver handle | |
921 | * | |
922 | * Must be called before sending CLIENT_SETUP for the first client. | |
923 | */ | |
924 | static inline int bnx2x_func_start(struct bnx2x *bp) | |
925 | { | |
3b603066 | 926 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 VZ |
927 | struct bnx2x_func_start_params *start_params = |
928 | &func_params.params.start; | |
883ce97d | 929 | u16 port; |
619c5cb6 VZ |
930 | |
931 | /* Prepare parameters for function state transitions */ | |
932 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
933 | ||
934 | func_params.f_obj = &bp->func_obj; | |
935 | func_params.cmd = BNX2X_F_CMD_START; | |
936 | ||
937 | /* Function parameters */ | |
938 | start_params->mf_mode = bp->mf_mode; | |
939 | start_params->sd_vlan_tag = bp->mf_ov; | |
8d7b0278 | 940 | |
230d00eb YM |
941 | /* Configure Ethertype for BD mode */ |
942 | if (IS_MF_BD(bp)) { | |
943 | DP(NETIF_MSG_IFUP, "Configuring ethertype 0x88a8 for BD\n"); | |
944 | start_params->sd_vlan_eth_type = ETH_P_8021AD; | |
945 | REG_WR(bp, PRS_REG_VLAN_TYPE_0, ETH_P_8021AD); | |
946 | REG_WR(bp, PBF_REG_VLAN_TYPE_0, ETH_P_8021AD); | |
947 | REG_WR(bp, NIG_REG_LLH_E1HOV_TYPE_1, ETH_P_8021AD); | |
948 | ||
949 | bnx2x_get_c2s_mapping(bp, start_params->c2s_pri, | |
950 | &start_params->c2s_pri_default); | |
951 | start_params->c2s_pri_valid = 1; | |
952 | ||
953 | DP(NETIF_MSG_IFUP, | |
954 | "Inner-to-Outer priority: %02x %02x %02x %02x %02x %02x %02x %02x [Default %02x]\n", | |
955 | start_params->c2s_pri[0], start_params->c2s_pri[1], | |
956 | start_params->c2s_pri[2], start_params->c2s_pri[3], | |
957 | start_params->c2s_pri[4], start_params->c2s_pri[5], | |
958 | start_params->c2s_pri[6], start_params->c2s_pri[7], | |
959 | start_params->c2s_pri_default); | |
960 | } | |
961 | ||
8d7b0278 | 962 | if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) |
6383c0b3 | 963 | start_params->network_cos_mode = STATIC_COS; |
8d7b0278 AE |
964 | else /* CHIP_IS_E1X */ |
965 | start_params->network_cos_mode = FW_WRR; | |
883ce97d YM |
966 | if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) { |
967 | port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].dst_port; | |
968 | start_params->vxlan_dst_port = port; | |
969 | } | |
970 | if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) { | |
971 | port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].dst_port; | |
972 | start_params->geneve_dst_port = port; | |
973 | } | |
f34fa14c | 974 | |
28311f8e | 975 | start_params->inner_rss = 1; |
1bc277f7 | 976 | |
7609647e YM |
977 | if (IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { |
978 | start_params->class_fail_ethtype = ETH_P_FIP; | |
979 | start_params->class_fail = 1; | |
980 | start_params->no_added_tags = 1; | |
981 | } | |
982 | ||
619c5cb6 VZ |
983 | return bnx2x_func_state_change(bp, &func_params); |
984 | } | |
985 | ||
619c5cb6 VZ |
986 | /** |
987 | * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format | |
988 | * | |
989 | * @fw_hi: pointer to upper part | |
990 | * @fw_mid: pointer to middle part | |
991 | * @fw_lo: pointer to lower part | |
992 | * @mac: pointer to MAC address | |
993 | */ | |
86564c3f YM |
994 | static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, |
995 | __le16 *fw_lo, u8 *mac) | |
619c5cb6 VZ |
996 | { |
997 | ((u8 *)fw_hi)[0] = mac[1]; | |
998 | ((u8 *)fw_hi)[1] = mac[0]; | |
999 | ((u8 *)fw_mid)[0] = mac[3]; | |
1000 | ((u8 *)fw_mid)[1] = mac[2]; | |
1001 | ((u8 *)fw_lo)[0] = mac[5]; | |
1002 | ((u8 *)fw_lo)[1] = mac[4]; | |
1003 | } | |
1004 | ||
4cace675 GKB |
1005 | static inline void bnx2x_free_rx_mem_pool(struct bnx2x *bp, |
1006 | struct bnx2x_alloc_pool *pool) | |
1007 | { | |
1008 | if (!pool->page) | |
1009 | return; | |
1010 | ||
4cace675 GKB |
1011 | put_page(pool->page); |
1012 | ||
1013 | pool->page = NULL; | |
1014 | } | |
1015 | ||
523224a3 DK |
1016 | static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, |
1017 | struct bnx2x_fastpath *fp, int last) | |
9f6c9258 | 1018 | { |
523224a3 | 1019 | int i; |
9f6c9258 | 1020 | |
7e6b4d44 | 1021 | if (fp->mode == TPA_MODE_DISABLED) |
b3b83c3f DK |
1022 | return; |
1023 | ||
523224a3 DK |
1024 | for (i = 0; i < last; i++) |
1025 | bnx2x_free_rx_sge(bp, fp, i); | |
4cace675 GKB |
1026 | |
1027 | bnx2x_free_rx_mem_pool(bp, &fp->page_pool); | |
9f6c9258 DK |
1028 | } |
1029 | ||
523224a3 | 1030 | static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) |
9f6c9258 | 1031 | { |
523224a3 | 1032 | int i; |
9f6c9258 | 1033 | |
523224a3 DK |
1034 | for (i = 1; i <= NUM_RX_RINGS; i++) { |
1035 | struct eth_rx_bd *rx_bd; | |
1036 | ||
1037 | rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; | |
1038 | rx_bd->addr_hi = | |
1039 | cpu_to_le32(U64_HI(fp->rx_desc_mapping + | |
1040 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
1041 | rx_bd->addr_lo = | |
1042 | cpu_to_le32(U64_LO(fp->rx_desc_mapping + | |
1043 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
1044 | } | |
9f6c9258 DK |
1045 | } |
1046 | ||
619c5cb6 VZ |
1047 | /* Statistics ID are global per chip/path, while Client IDs for E1x are per |
1048 | * port. | |
1049 | */ | |
1050 | static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) | |
1051 | { | |
de5c3741 YM |
1052 | struct bnx2x *bp = fp->bp; |
1053 | if (!CHIP_IS_E1x(bp)) { | |
de5c3741 YM |
1054 | /* there are special statistics counters for FCoE 136..140 */ |
1055 | if (IS_FCOE_FP(fp)) | |
1056 | return bp->cnic_base_cl_id + (bp->pf_num >> 1); | |
619c5cb6 | 1057 | return fp->cl_id; |
de5c3741 YM |
1058 | } |
1059 | return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; | |
619c5cb6 VZ |
1060 | } |
1061 | ||
1062 | static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, | |
1063 | bnx2x_obj_type obj_type) | |
1064 | { | |
1065 | struct bnx2x *bp = fp->bp; | |
1066 | ||
1067 | /* Configure classification DBs */ | |
15192a8c BW |
1068 | bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, |
1069 | fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), | |
619c5cb6 VZ |
1070 | bnx2x_sp_mapping(bp, mac_rdata), |
1071 | BNX2X_FILTER_MAC_PENDING, | |
1072 | &bp->sp_state, obj_type, | |
1073 | &bp->macs_pool); | |
05cc5a39 YM |
1074 | |
1075 | if (!CHIP_IS_E1x(bp)) | |
1076 | bnx2x_init_vlan_obj(bp, &bnx2x_sp_obj(bp, fp).vlan_obj, | |
1077 | fp->cl_id, fp->cid, BP_FUNC(bp), | |
1078 | bnx2x_sp(bp, vlan_rdata), | |
1079 | bnx2x_sp_mapping(bp, vlan_rdata), | |
1080 | BNX2X_FILTER_VLAN_PENDING, | |
1081 | &bp->sp_state, obj_type, | |
1082 | &bp->vlans_pool); | |
619c5cb6 VZ |
1083 | } |
1084 | ||
1085 | /** | |
1086 | * bnx2x_get_path_func_num - get number of active functions | |
1087 | * | |
1088 | * @bp: driver handle | |
1089 | * | |
1090 | * Calculates the number of active (not hidden) functions on the | |
1091 | * current path. | |
1092 | */ | |
1093 | static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) | |
1094 | { | |
1095 | u8 func_num = 0, i; | |
1096 | ||
1097 | /* 57710 has only one function per-port */ | |
1098 | if (CHIP_IS_E1(bp)) | |
1099 | return 1; | |
1100 | ||
1101 | /* Calculate a number of functions enabled on the current | |
1102 | * PATH/PORT. | |
1103 | */ | |
1104 | if (CHIP_REV_IS_SLOW(bp)) { | |
1105 | if (IS_MF(bp)) | |
1106 | func_num = 4; | |
1107 | else | |
1108 | func_num = 2; | |
1109 | } else { | |
1110 | for (i = 0; i < E1H_FUNC_MAX / 2; i++) { | |
1111 | u32 func_config = | |
1112 | MF_CFG_RD(bp, | |
1113 | func_mf_config[BP_PORT(bp) + 2 * i]. | |
1114 | config); | |
1115 | func_num += | |
1116 | ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); | |
1117 | } | |
1118 | } | |
1119 | ||
1120 | WARN_ON(!func_num); | |
1121 | ||
1122 | return func_num; | |
1123 | } | |
1124 | ||
1125 | static inline void bnx2x_init_bp_objs(struct bnx2x *bp) | |
1126 | { | |
1127 | /* RX_MODE controlling object */ | |
1128 | bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); | |
1129 | ||
1130 | /* multicast configuration controlling object */ | |
1131 | bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, | |
1132 | BP_FUNC(bp), BP_FUNC(bp), | |
1133 | bnx2x_sp(bp, mcast_rdata), | |
1134 | bnx2x_sp_mapping(bp, mcast_rdata), | |
1135 | BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, | |
1136 | BNX2X_OBJ_TYPE_RX); | |
1137 | ||
1138 | /* Setup CAM credit pools */ | |
1139 | bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), | |
1140 | bnx2x_get_path_func_num(bp)); | |
1141 | ||
05cc5a39 | 1142 | bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_FUNC(bp), |
b56e9670 AE |
1143 | bnx2x_get_path_func_num(bp)); |
1144 | ||
619c5cb6 VZ |
1145 | /* RSS configuration object */ |
1146 | bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, | |
1147 | bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), | |
1148 | bnx2x_sp(bp, rss_rdata), | |
1149 | bnx2x_sp_mapping(bp, rss_rdata), | |
1150 | BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, | |
1151 | BNX2X_OBJ_TYPE_RX); | |
05cc5a39 YM |
1152 | |
1153 | bp->vlan_credit = PF_VLAN_CREDIT_E2(bp, bnx2x_get_path_func_num(bp)); | |
619c5cb6 VZ |
1154 | } |
1155 | ||
1156 | static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) | |
1157 | { | |
1158 | if (CHIP_IS_E1x(fp->bp)) | |
1159 | return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; | |
1160 | else | |
1161 | return fp->cl_id; | |
1162 | } | |
1163 | ||
6383c0b3 | 1164 | static inline void bnx2x_init_txdata(struct bnx2x *bp, |
65565884 MS |
1165 | struct bnx2x_fp_txdata *txdata, u32 cid, |
1166 | int txq_index, __le16 *tx_cons_sb, | |
1167 | struct bnx2x_fastpath *fp) | |
6383c0b3 AE |
1168 | { |
1169 | txdata->cid = cid; | |
1170 | txdata->txq_index = txq_index; | |
1171 | txdata->tx_cons_sb = tx_cons_sb; | |
65565884 | 1172 | txdata->parent_fp = fp; |
7b5342d9 | 1173 | txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; |
6383c0b3 | 1174 | |
51c1a580 | 1175 | DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", |
6383c0b3 AE |
1176 | txdata->cid, txdata->txq_index); |
1177 | } | |
619c5cb6 | 1178 | |
619c5cb6 VZ |
1179 | static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) |
1180 | { | |
1181 | return bp->cnic_base_cl_id + cl_idx + | |
134d0f97 | 1182 | (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; |
619c5cb6 VZ |
1183 | } |
1184 | ||
1185 | static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) | |
1186 | { | |
619c5cb6 VZ |
1187 | /* the 'first' id is allocated for the cnic */ |
1188 | return bp->base_fw_ndsb; | |
1189 | } | |
1190 | ||
1191 | static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) | |
1192 | { | |
1193 | return bp->igu_base_sb; | |
1194 | } | |
1195 | ||
619c5cb6 | 1196 | static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, |
6383c0b3 | 1197 | struct bnx2x_fp_txdata *txdata) |
619c5cb6 VZ |
1198 | { |
1199 | int cnt = 1000; | |
1200 | ||
6383c0b3 | 1201 | while (bnx2x_has_tx_work_unload(txdata)) { |
619c5cb6 | 1202 | if (!cnt) { |
51c1a580 | 1203 | BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", |
6383c0b3 AE |
1204 | txdata->txq_index, txdata->tx_pkt_prod, |
1205 | txdata->tx_pkt_cons); | |
619c5cb6 VZ |
1206 | #ifdef BNX2X_STOP_ON_ERROR |
1207 | bnx2x_panic(); | |
1208 | return -EBUSY; | |
1209 | #else | |
1210 | break; | |
1211 | #endif | |
1212 | } | |
1213 | cnt--; | |
0926d499 | 1214 | usleep_range(1000, 2000); |
619c5cb6 VZ |
1215 | } |
1216 | ||
1217 | return 0; | |
1218 | } | |
1219 | ||
1ac9e428 YR |
1220 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
1221 | ||
523224a3 DK |
1222 | static inline void __storm_memset_struct(struct bnx2x *bp, |
1223 | u32 addr, size_t size, u32 *data) | |
1224 | { | |
1225 | int i; | |
1226 | for (i = 0; i < size/4; i++) | |
1227 | REG_WR(bp, addr + (i * 4), data[i]); | |
1228 | } | |
1229 | ||
619c5cb6 VZ |
1230 | /** |
1231 | * bnx2x_wait_sp_comp - wait for the outstanding SP commands. | |
1232 | * | |
1233 | * @bp: driver handle | |
1234 | * @mask: bits that need to be cleared | |
1235 | */ | |
1236 | static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) | |
1237 | { | |
1238 | int tout = 5000; /* Wait for 5 secs tops */ | |
1239 | ||
1240 | while (tout--) { | |
1241 | smp_mb(); | |
1242 | netif_addr_lock_bh(bp->dev); | |
1243 | if (!(bp->sp_state & mask)) { | |
1244 | netif_addr_unlock_bh(bp->dev); | |
1245 | return true; | |
1246 | } | |
1247 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1248 | |
0926d499 | 1249 | usleep_range(1000, 2000); |
619c5cb6 VZ |
1250 | } |
1251 | ||
1252 | smp_mb(); | |
1253 | ||
1254 | netif_addr_lock_bh(bp->dev); | |
1255 | if (bp->sp_state & mask) { | |
51c1a580 MS |
1256 | BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", |
1257 | bp->sp_state, mask); | |
619c5cb6 VZ |
1258 | netif_addr_unlock_bh(bp->dev); |
1259 | return false; | |
1260 | } | |
1261 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1262 | |
619c5cb6 | 1263 | return true; |
523224a3 | 1264 | } |
f85582f8 | 1265 | |
619c5cb6 VZ |
1266 | /** |
1267 | * bnx2x_set_ctx_validation - set CDU context validation values | |
1268 | * | |
1269 | * @bp: driver handle | |
1270 | * @cxt: context of the connection on the host memory | |
1271 | * @cid: SW CID of the connection to be configured | |
1272 | */ | |
1273 | void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, | |
1274 | u32 cid); | |
1275 | ||
1276 | void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, | |
1277 | u8 sb_index, u8 disable, u16 usec); | |
9f6c9258 DK |
1278 | void bnx2x_acquire_phy_lock(struct bnx2x *bp); |
1279 | void bnx2x_release_phy_lock(struct bnx2x *bp); | |
1280 | ||
faa6fcbb | 1281 | /** |
e8920674 | 1282 | * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. |
faa6fcbb | 1283 | * |
e8920674 DK |
1284 | * @bp: driver handle |
1285 | * @mf_cfg: MF configuration | |
faa6fcbb | 1286 | * |
faa6fcbb DK |
1287 | */ |
1288 | static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) | |
1289 | { | |
1290 | u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> | |
1291 | FUNC_MF_CFG_MAX_BW_SHIFT; | |
1292 | if (!max_cfg) { | |
51c1a580 | 1293 | DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, |
96b0accb | 1294 | "Max BW configured to 0 - using 100 instead\n"); |
faa6fcbb DK |
1295 | max_cfg = 100; |
1296 | } | |
1297 | return max_cfg; | |
1298 | } | |
1299 | ||
621b4d66 DK |
1300 | /* checks if HW supports GRO for given MTU */ |
1301 | static inline bool bnx2x_mtu_allows_gro(int mtu) | |
1302 | { | |
1303 | /* gro frags per page */ | |
1304 | int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); | |
1305 | ||
1306 | /* | |
16a5fd92 YM |
1307 | * 1. Number of frags should not grow above MAX_SKB_FRAGS |
1308 | * 2. Frag must fit the page | |
621b4d66 DK |
1309 | */ |
1310 | return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; | |
1311 | } | |
55c11941 | 1312 | |
b306f5ed DK |
1313 | /** |
1314 | * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. | |
1315 | * | |
1316 | * @bp: driver handle | |
1317 | * | |
1318 | */ | |
1319 | void bnx2x_get_iscsi_info(struct bnx2x *bp); | |
00253a8c DK |
1320 | |
1321 | /** | |
1322 | * bnx2x_link_sync_notify - send notification to other functions. | |
1323 | * | |
1324 | * @bp: driver handle | |
1325 | * | |
1326 | */ | |
1327 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) | |
1328 | { | |
1329 | int func; | |
1330 | int vn; | |
1331 | ||
1332 | /* Set the attention towards other drivers on the same port */ | |
1333 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
1334 | if (vn == BP_VN(bp)) | |
1335 | continue; | |
1336 | ||
1337 | func = func_by_vn(bp, vn); | |
1338 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + | |
1339 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); | |
1340 | } | |
1341 | } | |
1342 | ||
1343 | /** | |
1344 | * bnx2x_update_drv_flags - update flags in shmem | |
1345 | * | |
1346 | * @bp: driver handle | |
1347 | * @flags: flags to update | |
1348 | * @set: set or clear | |
1349 | * | |
1350 | */ | |
1351 | static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) | |
1352 | { | |
1353 | if (SHMEM2_HAS(bp, drv_flags)) { | |
1354 | u32 drv_flags; | |
f16da43b | 1355 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1356 | drv_flags = SHMEM2_RD(bp, drv_flags); |
1357 | ||
1358 | if (set) | |
1359 | SET_FLAGS(drv_flags, flags); | |
1360 | else | |
1361 | RESET_FLAGS(drv_flags, flags); | |
1362 | ||
1363 | SHMEM2_WR(bp, drv_flags, drv_flags); | |
51c1a580 | 1364 | DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); |
f16da43b | 1365 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1366 | } |
1367 | } | |
1368 | ||
55c11941 | 1369 | |
614c76df | 1370 | |
8ca5e17e | 1371 | /** |
2de67439 | 1372 | * bnx2x_fill_fw_str - Fill buffer with FW version string |
8ca5e17e AE |
1373 | * |
1374 | * @bp: driver handle | |
1375 | * @buf: character buffer to fill with the fw name | |
1376 | * @buf_len: length of the above buffer | |
1377 | * | |
1378 | */ | |
1379 | void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len); | |
7fa6f340 YM |
1380 | |
1381 | int bnx2x_drain_tx_queues(struct bnx2x *bp); | |
1382 | void bnx2x_squeeze_objects(struct bnx2x *bp); | |
1383 | ||
230bb0f3 YM |
1384 | void bnx2x_schedule_sp_rtnl(struct bnx2x*, enum sp_rtnl_flag, |
1385 | u32 verbose); | |
1386 | ||
230d00eb YM |
1387 | /** |
1388 | * bnx2x_set_os_driver_state - write driver state for management FW usage | |
1389 | * | |
1390 | * @bp: driver handle | |
1391 | * @state: OS_DRIVER_STATE_* value reflecting current driver state | |
1392 | */ | |
1393 | void bnx2x_set_os_driver_state(struct bnx2x *bp, u32 state); | |
97ac4ef7 YM |
1394 | |
1395 | /** | |
1396 | * bnx2x_nvram_read - reads data from nvram [might sleep] | |
1397 | * | |
1398 | * @bp: driver handle | |
1399 | * @offset: byte offset in nvram | |
1400 | * @ret_buf: pointer to buffer where data is to be stored | |
1401 | * @buf_size: Length of 'ret_buf' in bytes | |
1402 | */ | |
1403 | int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, | |
1404 | int buf_size); | |
1405 | ||
9f6c9258 | 1406 | #endif /* BNX2X_CMN_H */ |