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de0c62db DK |
1 | /* bnx2x_ethtool.c: Broadcom Everest network driver. |
2 | * | |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
de0c62db DK |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
f1deab50 JP |
17 | |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
19 | ||
de0c62db DK |
20 | #include <linux/ethtool.h> |
21 | #include <linux/netdevice.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/sched.h> | |
24 | #include <linux/crc32.h> | |
de0c62db DK |
25 | #include "bnx2x.h" |
26 | #include "bnx2x_cmn.h" | |
27 | #include "bnx2x_dump.h" | |
4a33bc03 | 28 | #include "bnx2x_init.h" |
de0c62db | 29 | |
ec6ba945 VZ |
30 | /* Note: in the format strings below %s is replaced by the queue-name which is |
31 | * either its index or 'fcoe' for the fcoe queue. Make sure the format string | |
32 | * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 | |
33 | */ | |
34 | #define MAX_QUEUE_NAME_LEN 4 | |
35 | static const struct { | |
36 | long offset; | |
37 | int size; | |
38 | char string[ETH_GSTRING_LEN]; | |
39 | } bnx2x_q_stats_arr[] = { | |
40 | /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, | |
ec6ba945 VZ |
41 | { Q_STATS_OFFSET32(total_unicast_packets_received_hi), |
42 | 8, "[%s]: rx_ucast_packets" }, | |
43 | { Q_STATS_OFFSET32(total_multicast_packets_received_hi), | |
44 | 8, "[%s]: rx_mcast_packets" }, | |
45 | { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), | |
46 | 8, "[%s]: rx_bcast_packets" }, | |
47 | { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, | |
48 | { Q_STATS_OFFSET32(rx_err_discard_pkt), | |
49 | 4, "[%s]: rx_phy_ip_err_discards"}, | |
50 | { Q_STATS_OFFSET32(rx_skb_alloc_failed), | |
51 | 4, "[%s]: rx_skb_alloc_discard" }, | |
52 | { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, | |
53 | ||
619c5cb6 VZ |
54 | { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, |
55 | /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), | |
ec6ba945 VZ |
56 | 8, "[%s]: tx_ucast_packets" }, |
57 | { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), | |
58 | 8, "[%s]: tx_mcast_packets" }, | |
59 | { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), | |
619c5cb6 VZ |
60 | 8, "[%s]: tx_bcast_packets" }, |
61 | { Q_STATS_OFFSET32(total_tpa_aggregations_hi), | |
62 | 8, "[%s]: tpa_aggregations" }, | |
63 | { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), | |
64 | 8, "[%s]: tpa_aggregated_frames"}, | |
c96bdc0c DK |
65 | { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, |
66 | { Q_STATS_OFFSET32(driver_filtered_tx_pkt), | |
67 | 4, "[%s]: driver_filtered_tx_pkt" } | |
ec6ba945 VZ |
68 | }; |
69 | ||
70 | #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) | |
71 | ||
72 | static const struct { | |
73 | long offset; | |
74 | int size; | |
75 | u32 flags; | |
76 | #define STATS_FLAGS_PORT 1 | |
77 | #define STATS_FLAGS_FUNC 2 | |
78 | #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) | |
79 | char string[ETH_GSTRING_LEN]; | |
80 | } bnx2x_stats_arr[] = { | |
81 | /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), | |
82 | 8, STATS_FLAGS_BOTH, "rx_bytes" }, | |
83 | { STATS_OFFSET32(error_bytes_received_hi), | |
84 | 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, | |
85 | { STATS_OFFSET32(total_unicast_packets_received_hi), | |
86 | 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, | |
87 | { STATS_OFFSET32(total_multicast_packets_received_hi), | |
88 | 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, | |
89 | { STATS_OFFSET32(total_broadcast_packets_received_hi), | |
90 | 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, | |
91 | { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), | |
92 | 8, STATS_FLAGS_PORT, "rx_crc_errors" }, | |
93 | { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), | |
94 | 8, STATS_FLAGS_PORT, "rx_align_errors" }, | |
95 | { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), | |
96 | 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, | |
97 | { STATS_OFFSET32(etherstatsoverrsizepkts_hi), | |
98 | 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, | |
99 | /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), | |
100 | 8, STATS_FLAGS_PORT, "rx_fragments" }, | |
101 | { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), | |
102 | 8, STATS_FLAGS_PORT, "rx_jabbers" }, | |
103 | { STATS_OFFSET32(no_buff_discard_hi), | |
104 | 8, STATS_FLAGS_BOTH, "rx_discards" }, | |
105 | { STATS_OFFSET32(mac_filter_discard), | |
106 | 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, | |
619c5cb6 VZ |
107 | { STATS_OFFSET32(mf_tag_discard), |
108 | 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, | |
0e898dd7 BW |
109 | { STATS_OFFSET32(pfc_frames_received_hi), |
110 | 8, STATS_FLAGS_PORT, "pfc_frames_received" }, | |
111 | { STATS_OFFSET32(pfc_frames_sent_hi), | |
112 | 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, | |
ec6ba945 VZ |
113 | { STATS_OFFSET32(brb_drop_hi), |
114 | 8, STATS_FLAGS_PORT, "rx_brb_discard" }, | |
115 | { STATS_OFFSET32(brb_truncate_hi), | |
116 | 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, | |
117 | { STATS_OFFSET32(pause_frames_received_hi), | |
118 | 8, STATS_FLAGS_PORT, "rx_pause_frames" }, | |
119 | { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), | |
120 | 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, | |
121 | { STATS_OFFSET32(nig_timer_max), | |
122 | 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, | |
123 | /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), | |
124 | 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, | |
125 | { STATS_OFFSET32(rx_skb_alloc_failed), | |
126 | 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, | |
127 | { STATS_OFFSET32(hw_csum_err), | |
128 | 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, | |
129 | ||
130 | { STATS_OFFSET32(total_bytes_transmitted_hi), | |
131 | 8, STATS_FLAGS_BOTH, "tx_bytes" }, | |
132 | { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), | |
133 | 8, STATS_FLAGS_PORT, "tx_error_bytes" }, | |
134 | { STATS_OFFSET32(total_unicast_packets_transmitted_hi), | |
135 | 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, | |
136 | { STATS_OFFSET32(total_multicast_packets_transmitted_hi), | |
137 | 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, | |
138 | { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), | |
139 | 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, | |
140 | { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), | |
141 | 8, STATS_FLAGS_PORT, "tx_mac_errors" }, | |
142 | { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), | |
143 | 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, | |
144 | /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), | |
145 | 8, STATS_FLAGS_PORT, "tx_single_collisions" }, | |
146 | { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), | |
147 | 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, | |
148 | { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), | |
149 | 8, STATS_FLAGS_PORT, "tx_deferred" }, | |
150 | { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), | |
151 | 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, | |
152 | { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), | |
153 | 8, STATS_FLAGS_PORT, "tx_late_collisions" }, | |
154 | { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), | |
155 | 8, STATS_FLAGS_PORT, "tx_total_collisions" }, | |
156 | { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), | |
157 | 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, | |
158 | { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), | |
159 | 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, | |
160 | { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), | |
161 | 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, | |
162 | { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), | |
163 | 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, | |
164 | /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), | |
165 | 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, | |
166 | { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), | |
167 | 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, | |
168 | { STATS_OFFSET32(etherstatspktsover1522octets_hi), | |
169 | 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, | |
170 | { STATS_OFFSET32(pause_frames_sent_hi), | |
619c5cb6 VZ |
171 | 8, STATS_FLAGS_PORT, "tx_pause_frames" }, |
172 | { STATS_OFFSET32(total_tpa_aggregations_hi), | |
173 | 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, | |
174 | { STATS_OFFSET32(total_tpa_aggregated_frames_hi), | |
175 | 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, | |
176 | { STATS_OFFSET32(total_tpa_bytes_hi), | |
7a752993 AE |
177 | 8, STATS_FLAGS_FUNC, "tpa_bytes"}, |
178 | { STATS_OFFSET32(recoverable_error), | |
179 | 4, STATS_FLAGS_FUNC, "recoverable_errors" }, | |
180 | { STATS_OFFSET32(unrecoverable_error), | |
181 | 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, | |
c96bdc0c DK |
182 | { STATS_OFFSET32(driver_filtered_tx_pkt), |
183 | 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, | |
e9939c80 YM |
184 | { STATS_OFFSET32(eee_tx_lpi), |
185 | 4, STATS_FLAGS_PORT, "Tx LPI entry count"} | |
ec6ba945 VZ |
186 | }; |
187 | ||
188 | #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) | |
07ba6af4 | 189 | |
1ac9e428 YR |
190 | static int bnx2x_get_port_type(struct bnx2x *bp) |
191 | { | |
192 | int port_type; | |
193 | u32 phy_idx = bnx2x_get_cur_phy_idx(bp); | |
194 | switch (bp->link_params.phy[phy_idx].media_type) { | |
dbef807e YM |
195 | case ETH_PHY_SFPP_10G_FIBER: |
196 | case ETH_PHY_SFP_1G_FIBER: | |
1ac9e428 YR |
197 | case ETH_PHY_XFP_FIBER: |
198 | case ETH_PHY_KR: | |
199 | case ETH_PHY_CX4: | |
200 | port_type = PORT_FIBRE; | |
201 | break; | |
202 | case ETH_PHY_DA_TWINAX: | |
203 | port_type = PORT_DA; | |
204 | break; | |
205 | case ETH_PHY_BASE_T: | |
206 | port_type = PORT_TP; | |
207 | break; | |
208 | case ETH_PHY_NOT_PRESENT: | |
209 | port_type = PORT_NONE; | |
210 | break; | |
211 | case ETH_PHY_UNSPECIFIED: | |
212 | default: | |
213 | port_type = PORT_OTHER; | |
214 | break; | |
215 | } | |
216 | return port_type; | |
217 | } | |
ec6ba945 | 218 | |
de0c62db DK |
219 | static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
220 | { | |
221 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 | 222 | int cfg_idx = bnx2x_get_link_cfg_idx(bp); |
b3337e4c | 223 | |
a22f0788 YR |
224 | /* Dual Media boards present all available port types */ |
225 | cmd->supported = bp->port.supported[cfg_idx] | | |
226 | (bp->port.supported[cfg_idx ^ 1] & | |
227 | (SUPPORTED_TP | SUPPORTED_FIBRE)); | |
228 | cmd->advertising = bp->port.advertising[cfg_idx]; | |
dbef807e YM |
229 | if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type == |
230 | ETH_PHY_SFP_1G_FIBER) { | |
231 | cmd->supported &= ~(SUPPORTED_10000baseT_Full); | |
232 | cmd->advertising &= ~(ADVERTISED_10000baseT_Full); | |
233 | } | |
de0c62db | 234 | |
59694f00 YM |
235 | if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && |
236 | !(bp->flags & MF_FUNC_DIS)) { | |
2de67439 | 237 | cmd->duplex = bp->link_vars.duplex; |
38298461 YM |
238 | |
239 | if (IS_MF(bp) && !BP_NOMCP(bp)) | |
240 | ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); | |
59694f00 YM |
241 | else |
242 | ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); | |
de0c62db | 243 | } else { |
38298461 YM |
244 | cmd->duplex = DUPLEX_UNKNOWN; |
245 | ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); | |
de0c62db | 246 | } |
f2e0899f | 247 | |
1ac9e428 | 248 | cmd->port = bnx2x_get_port_type(bp); |
a22f0788 | 249 | |
de0c62db DK |
250 | cmd->phy_address = bp->mdio.prtad; |
251 | cmd->transceiver = XCVR_INTERNAL; | |
252 | ||
a22f0788 | 253 | if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) |
de0c62db DK |
254 | cmd->autoneg = AUTONEG_ENABLE; |
255 | else | |
256 | cmd->autoneg = AUTONEG_DISABLE; | |
257 | ||
9e7e8399 MY |
258 | /* Publish LP advertised speeds and FC */ |
259 | if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
260 | u32 status = bp->link_vars.link_status; | |
261 | ||
262 | cmd->lp_advertising |= ADVERTISED_Autoneg; | |
263 | if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) | |
264 | cmd->lp_advertising |= ADVERTISED_Pause; | |
265 | if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) | |
266 | cmd->lp_advertising |= ADVERTISED_Asym_Pause; | |
267 | ||
268 | if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) | |
269 | cmd->lp_advertising |= ADVERTISED_10baseT_Half; | |
270 | if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) | |
271 | cmd->lp_advertising |= ADVERTISED_10baseT_Full; | |
272 | if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) | |
273 | cmd->lp_advertising |= ADVERTISED_100baseT_Half; | |
274 | if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) | |
275 | cmd->lp_advertising |= ADVERTISED_100baseT_Full; | |
276 | if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) | |
277 | cmd->lp_advertising |= ADVERTISED_1000baseT_Half; | |
278 | if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) | |
279 | cmd->lp_advertising |= ADVERTISED_1000baseT_Full; | |
280 | if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) | |
281 | cmd->lp_advertising |= ADVERTISED_2500baseX_Full; | |
282 | if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) | |
283 | cmd->lp_advertising |= ADVERTISED_10000baseT_Full; | |
be94bea7 YR |
284 | if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) |
285 | cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full; | |
9e7e8399 MY |
286 | } |
287 | ||
de0c62db DK |
288 | cmd->maxtxpkt = 0; |
289 | cmd->maxrxpkt = 0; | |
290 | ||
51c1a580 | 291 | DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" |
f1deab50 JP |
292 | " supported 0x%x advertising 0x%x speed %u\n" |
293 | " duplex %d port %d phy_address %d transceiver %d\n" | |
294 | " autoneg %d maxtxpkt %d maxrxpkt %d\n", | |
b3337e4c DD |
295 | cmd->cmd, cmd->supported, cmd->advertising, |
296 | ethtool_cmd_speed(cmd), | |
de0c62db DK |
297 | cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, |
298 | cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
304 | { | |
305 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 | 306 | u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; |
dbef807e | 307 | u32 speed, phy_idx; |
de0c62db | 308 | |
0793f83f | 309 | if (IS_MF_SD(bp)) |
de0c62db DK |
310 | return 0; |
311 | ||
51c1a580 | 312 | DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" |
b3337e4c | 313 | " supported 0x%x advertising 0x%x speed %u\n" |
0793f83f DK |
314 | " duplex %d port %d phy_address %d transceiver %d\n" |
315 | " autoneg %d maxtxpkt %d maxrxpkt %d\n", | |
b3337e4c DD |
316 | cmd->cmd, cmd->supported, cmd->advertising, |
317 | ethtool_cmd_speed(cmd), | |
de0c62db DK |
318 | cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, |
319 | cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); | |
320 | ||
b3337e4c | 321 | speed = ethtool_cmd_speed(cmd); |
0793f83f | 322 | |
16a5fd92 | 323 | /* If received a request for an unknown duplex, assume full*/ |
38298461 YM |
324 | if (cmd->duplex == DUPLEX_UNKNOWN) |
325 | cmd->duplex = DUPLEX_FULL; | |
326 | ||
0793f83f | 327 | if (IS_MF_SI(bp)) { |
e3835b99 | 328 | u32 part; |
0793f83f DK |
329 | u32 line_speed = bp->link_vars.line_speed; |
330 | ||
331 | /* use 10G if no link detected */ | |
332 | if (!line_speed) | |
333 | line_speed = 10000; | |
334 | ||
335 | if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { | |
51c1a580 MS |
336 | DP(BNX2X_MSG_ETHTOOL, |
337 | "To set speed BC %X or higher is required, please upgrade BC\n", | |
338 | REQ_BC_VER_4_SET_MF_BW); | |
0793f83f DK |
339 | return -EINVAL; |
340 | } | |
e3835b99 | 341 | |
faa6fcbb | 342 | part = (speed * 100) / line_speed; |
e3835b99 | 343 | |
faa6fcbb | 344 | if (line_speed < speed || !part) { |
51c1a580 MS |
345 | DP(BNX2X_MSG_ETHTOOL, |
346 | "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); | |
0793f83f DK |
347 | return -EINVAL; |
348 | } | |
0793f83f | 349 | |
e3835b99 DK |
350 | if (bp->state != BNX2X_STATE_OPEN) |
351 | /* store value for following "load" */ | |
352 | bp->pending_max = part; | |
353 | else | |
354 | bnx2x_update_max_mf_config(bp, part); | |
0793f83f | 355 | |
0793f83f DK |
356 | return 0; |
357 | } | |
358 | ||
a22f0788 YR |
359 | cfg_idx = bnx2x_get_link_cfg_idx(bp); |
360 | old_multi_phy_config = bp->link_params.multi_phy_config; | |
33f9e6f5 YR |
361 | if (cmd->port != bnx2x_get_port_type(bp)) { |
362 | switch (cmd->port) { | |
363 | case PORT_TP: | |
364 | if (!(bp->port.supported[0] & SUPPORTED_TP || | |
365 | bp->port.supported[1] & SUPPORTED_TP)) { | |
366 | DP(BNX2X_MSG_ETHTOOL, | |
367 | "Unsupported port type\n"); | |
368 | return -EINVAL; | |
369 | } | |
370 | bp->link_params.multi_phy_config &= | |
371 | ~PORT_HW_CFG_PHY_SELECTION_MASK; | |
372 | if (bp->link_params.multi_phy_config & | |
373 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) | |
374 | bp->link_params.multi_phy_config |= | |
375 | PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
376 | else | |
377 | bp->link_params.multi_phy_config |= | |
378 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
379 | break; | |
380 | case PORT_FIBRE: | |
381 | case PORT_DA: | |
382 | if (!(bp->port.supported[0] & SUPPORTED_FIBRE || | |
383 | bp->port.supported[1] & SUPPORTED_FIBRE)) { | |
384 | DP(BNX2X_MSG_ETHTOOL, | |
385 | "Unsupported port type\n"); | |
386 | return -EINVAL; | |
387 | } | |
388 | bp->link_params.multi_phy_config &= | |
389 | ~PORT_HW_CFG_PHY_SELECTION_MASK; | |
390 | if (bp->link_params.multi_phy_config & | |
391 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) | |
392 | bp->link_params.multi_phy_config |= | |
393 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
394 | else | |
395 | bp->link_params.multi_phy_config |= | |
396 | PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
397 | break; | |
398 | default: | |
51c1a580 | 399 | DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); |
a22f0788 YR |
400 | return -EINVAL; |
401 | } | |
a22f0788 | 402 | } |
2de67439 | 403 | /* Save new config in case command complete successfully */ |
a22f0788 YR |
404 | new_multi_phy_config = bp->link_params.multi_phy_config; |
405 | /* Get the new cfg_idx */ | |
406 | cfg_idx = bnx2x_get_link_cfg_idx(bp); | |
407 | /* Restore old config in case command failed */ | |
408 | bp->link_params.multi_phy_config = old_multi_phy_config; | |
51c1a580 | 409 | DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); |
a22f0788 | 410 | |
de0c62db | 411 | if (cmd->autoneg == AUTONEG_ENABLE) { |
75318327 YR |
412 | u32 an_supported_speed = bp->port.supported[cfg_idx]; |
413 | if (bp->link_params.phy[EXT_PHY1].type == | |
414 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
415 | an_supported_speed |= (SUPPORTED_100baseT_Half | | |
416 | SUPPORTED_100baseT_Full); | |
a22f0788 | 417 | if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { |
51c1a580 | 418 | DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); |
de0c62db DK |
419 | return -EINVAL; |
420 | } | |
421 | ||
422 | /* advertise the requested speed and duplex if supported */ | |
75318327 | 423 | if (cmd->advertising & ~an_supported_speed) { |
51c1a580 MS |
424 | DP(BNX2X_MSG_ETHTOOL, |
425 | "Advertisement parameters are not supported\n"); | |
8d661637 YR |
426 | return -EINVAL; |
427 | } | |
de0c62db | 428 | |
a22f0788 | 429 | bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; |
8d661637 YR |
430 | bp->link_params.req_duplex[cfg_idx] = cmd->duplex; |
431 | bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | | |
de0c62db | 432 | cmd->advertising); |
8d661637 YR |
433 | if (cmd->advertising) { |
434 | ||
435 | bp->link_params.speed_cap_mask[cfg_idx] = 0; | |
436 | if (cmd->advertising & ADVERTISED_10baseT_Half) { | |
437 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
438 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; | |
439 | } | |
440 | if (cmd->advertising & ADVERTISED_10baseT_Full) | |
441 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
442 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; | |
de0c62db | 443 | |
8d661637 YR |
444 | if (cmd->advertising & ADVERTISED_100baseT_Full) |
445 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
446 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; | |
447 | ||
448 | if (cmd->advertising & ADVERTISED_100baseT_Half) { | |
449 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
450 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; | |
451 | } | |
452 | if (cmd->advertising & ADVERTISED_1000baseT_Half) { | |
453 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
454 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; | |
455 | } | |
456 | if (cmd->advertising & (ADVERTISED_1000baseT_Full | | |
457 | ADVERTISED_1000baseKX_Full)) | |
458 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
459 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; | |
460 | ||
461 | if (cmd->advertising & (ADVERTISED_10000baseT_Full | | |
462 | ADVERTISED_10000baseKX4_Full | | |
463 | ADVERTISED_10000baseKR_Full)) | |
464 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
465 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; | |
be94bea7 YR |
466 | |
467 | if (cmd->advertising & ADVERTISED_20000baseKR2_Full) | |
468 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
469 | PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; | |
8d661637 | 470 | } |
de0c62db DK |
471 | } else { /* forced speed */ |
472 | /* advertise the requested speed and duplex if supported */ | |
a22f0788 | 473 | switch (speed) { |
de0c62db DK |
474 | case SPEED_10: |
475 | if (cmd->duplex == DUPLEX_FULL) { | |
a22f0788 | 476 | if (!(bp->port.supported[cfg_idx] & |
de0c62db | 477 | SUPPORTED_10baseT_Full)) { |
51c1a580 | 478 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
479 | "10M full not supported\n"); |
480 | return -EINVAL; | |
481 | } | |
482 | ||
483 | advertising = (ADVERTISED_10baseT_Full | | |
484 | ADVERTISED_TP); | |
485 | } else { | |
a22f0788 | 486 | if (!(bp->port.supported[cfg_idx] & |
de0c62db | 487 | SUPPORTED_10baseT_Half)) { |
51c1a580 | 488 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
489 | "10M half not supported\n"); |
490 | return -EINVAL; | |
491 | } | |
492 | ||
493 | advertising = (ADVERTISED_10baseT_Half | | |
494 | ADVERTISED_TP); | |
495 | } | |
496 | break; | |
497 | ||
498 | case SPEED_100: | |
499 | if (cmd->duplex == DUPLEX_FULL) { | |
a22f0788 | 500 | if (!(bp->port.supported[cfg_idx] & |
de0c62db | 501 | SUPPORTED_100baseT_Full)) { |
51c1a580 | 502 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
503 | "100M full not supported\n"); |
504 | return -EINVAL; | |
505 | } | |
506 | ||
507 | advertising = (ADVERTISED_100baseT_Full | | |
508 | ADVERTISED_TP); | |
509 | } else { | |
a22f0788 | 510 | if (!(bp->port.supported[cfg_idx] & |
de0c62db | 511 | SUPPORTED_100baseT_Half)) { |
51c1a580 | 512 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
513 | "100M half not supported\n"); |
514 | return -EINVAL; | |
515 | } | |
516 | ||
517 | advertising = (ADVERTISED_100baseT_Half | | |
518 | ADVERTISED_TP); | |
519 | } | |
520 | break; | |
521 | ||
522 | case SPEED_1000: | |
523 | if (cmd->duplex != DUPLEX_FULL) { | |
51c1a580 MS |
524 | DP(BNX2X_MSG_ETHTOOL, |
525 | "1G half not supported\n"); | |
de0c62db DK |
526 | return -EINVAL; |
527 | } | |
528 | ||
a22f0788 YR |
529 | if (!(bp->port.supported[cfg_idx] & |
530 | SUPPORTED_1000baseT_Full)) { | |
51c1a580 MS |
531 | DP(BNX2X_MSG_ETHTOOL, |
532 | "1G full not supported\n"); | |
de0c62db DK |
533 | return -EINVAL; |
534 | } | |
535 | ||
536 | advertising = (ADVERTISED_1000baseT_Full | | |
537 | ADVERTISED_TP); | |
538 | break; | |
539 | ||
540 | case SPEED_2500: | |
541 | if (cmd->duplex != DUPLEX_FULL) { | |
51c1a580 | 542 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
543 | "2.5G half not supported\n"); |
544 | return -EINVAL; | |
545 | } | |
546 | ||
a22f0788 YR |
547 | if (!(bp->port.supported[cfg_idx] |
548 | & SUPPORTED_2500baseX_Full)) { | |
51c1a580 | 549 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
550 | "2.5G full not supported\n"); |
551 | return -EINVAL; | |
552 | } | |
553 | ||
554 | advertising = (ADVERTISED_2500baseX_Full | | |
555 | ADVERTISED_TP); | |
556 | break; | |
557 | ||
558 | case SPEED_10000: | |
559 | if (cmd->duplex != DUPLEX_FULL) { | |
51c1a580 MS |
560 | DP(BNX2X_MSG_ETHTOOL, |
561 | "10G half not supported\n"); | |
de0c62db DK |
562 | return -EINVAL; |
563 | } | |
dbef807e | 564 | phy_idx = bnx2x_get_cur_phy_idx(bp); |
a22f0788 | 565 | if (!(bp->port.supported[cfg_idx] |
dbef807e YM |
566 | & SUPPORTED_10000baseT_Full) || |
567 | (bp->link_params.phy[phy_idx].media_type == | |
568 | ETH_PHY_SFP_1G_FIBER)) { | |
51c1a580 MS |
569 | DP(BNX2X_MSG_ETHTOOL, |
570 | "10G full not supported\n"); | |
de0c62db DK |
571 | return -EINVAL; |
572 | } | |
573 | ||
574 | advertising = (ADVERTISED_10000baseT_Full | | |
575 | ADVERTISED_FIBRE); | |
576 | break; | |
577 | ||
578 | default: | |
51c1a580 | 579 | DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); |
de0c62db DK |
580 | return -EINVAL; |
581 | } | |
582 | ||
a22f0788 YR |
583 | bp->link_params.req_line_speed[cfg_idx] = speed; |
584 | bp->link_params.req_duplex[cfg_idx] = cmd->duplex; | |
585 | bp->port.advertising[cfg_idx] = advertising; | |
de0c62db DK |
586 | } |
587 | ||
51c1a580 | 588 | DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" |
f1deab50 | 589 | " req_duplex %d advertising 0x%x\n", |
a22f0788 YR |
590 | bp->link_params.req_line_speed[cfg_idx], |
591 | bp->link_params.req_duplex[cfg_idx], | |
592 | bp->port.advertising[cfg_idx]); | |
de0c62db | 593 | |
a22f0788 YR |
594 | /* Set new config */ |
595 | bp->link_params.multi_phy_config = new_multi_phy_config; | |
de0c62db DK |
596 | if (netif_running(dev)) { |
597 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
598 | bnx2x_link_set(bp); | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
07ba6af4 MS |
604 | #define DUMP_ALL_PRESETS 0x1FFF |
605 | #define DUMP_MAX_PRESETS 13 | |
0fea29c1 | 606 | |
07ba6af4 | 607 | static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) |
0fea29c1 VZ |
608 | { |
609 | if (CHIP_IS_E1(bp)) | |
07ba6af4 | 610 | return dump_num_registers[0][preset-1]; |
0fea29c1 | 611 | else if (CHIP_IS_E1H(bp)) |
07ba6af4 | 612 | return dump_num_registers[1][preset-1]; |
0fea29c1 | 613 | else if (CHIP_IS_E2(bp)) |
07ba6af4 | 614 | return dump_num_registers[2][preset-1]; |
0fea29c1 | 615 | else if (CHIP_IS_E3A0(bp)) |
07ba6af4 | 616 | return dump_num_registers[3][preset-1]; |
0fea29c1 | 617 | else if (CHIP_IS_E3B0(bp)) |
07ba6af4 | 618 | return dump_num_registers[4][preset-1]; |
0fea29c1 | 619 | else |
07ba6af4 MS |
620 | return 0; |
621 | } | |
622 | ||
623 | static int __bnx2x_get_regs_len(struct bnx2x *bp) | |
624 | { | |
625 | u32 preset_idx; | |
626 | int regdump_len = 0; | |
627 | ||
628 | /* Calculate the total preset regs length */ | |
629 | for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) | |
630 | regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); | |
631 | ||
632 | return regdump_len; | |
633 | } | |
634 | ||
635 | static int bnx2x_get_regs_len(struct net_device *dev) | |
636 | { | |
637 | struct bnx2x *bp = netdev_priv(dev); | |
638 | int regdump_len = 0; | |
639 | ||
75543741 YM |
640 | if (IS_VF(bp)) |
641 | return 0; | |
642 | ||
07ba6af4 MS |
643 | regdump_len = __bnx2x_get_regs_len(bp); |
644 | regdump_len *= 4; | |
645 | regdump_len += sizeof(struct dump_header); | |
646 | ||
647 | return regdump_len; | |
0fea29c1 VZ |
648 | } |
649 | ||
07ba6af4 MS |
650 | #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) |
651 | #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) | |
652 | #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) | |
653 | #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) | |
654 | #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) | |
655 | ||
656 | #define IS_REG_IN_PRESET(presets, idx) \ | |
657 | ((presets & (1 << (idx-1))) == (1 << (idx-1))) | |
658 | ||
0fea29c1 | 659 | /******* Paged registers info selectors ********/ |
1191cb83 | 660 | static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) |
0fea29c1 VZ |
661 | { |
662 | if (CHIP_IS_E2(bp)) | |
663 | return page_vals_e2; | |
664 | else if (CHIP_IS_E3(bp)) | |
665 | return page_vals_e3; | |
666 | else | |
667 | return NULL; | |
668 | } | |
669 | ||
1191cb83 | 670 | static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) |
0fea29c1 VZ |
671 | { |
672 | if (CHIP_IS_E2(bp)) | |
673 | return PAGE_MODE_VALUES_E2; | |
674 | else if (CHIP_IS_E3(bp)) | |
675 | return PAGE_MODE_VALUES_E3; | |
676 | else | |
677 | return 0; | |
678 | } | |
679 | ||
1191cb83 | 680 | static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) |
0fea29c1 VZ |
681 | { |
682 | if (CHIP_IS_E2(bp)) | |
683 | return page_write_regs_e2; | |
684 | else if (CHIP_IS_E3(bp)) | |
685 | return page_write_regs_e3; | |
686 | else | |
687 | return NULL; | |
688 | } | |
689 | ||
1191cb83 | 690 | static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) |
0fea29c1 VZ |
691 | { |
692 | if (CHIP_IS_E2(bp)) | |
693 | return PAGE_WRITE_REGS_E2; | |
694 | else if (CHIP_IS_E3(bp)) | |
695 | return PAGE_WRITE_REGS_E3; | |
696 | else | |
697 | return 0; | |
698 | } | |
699 | ||
1191cb83 | 700 | static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) |
0fea29c1 VZ |
701 | { |
702 | if (CHIP_IS_E2(bp)) | |
703 | return page_read_regs_e2; | |
704 | else if (CHIP_IS_E3(bp)) | |
705 | return page_read_regs_e3; | |
706 | else | |
707 | return NULL; | |
708 | } | |
709 | ||
1191cb83 | 710 | static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) |
0fea29c1 VZ |
711 | { |
712 | if (CHIP_IS_E2(bp)) | |
713 | return PAGE_READ_REGS_E2; | |
714 | else if (CHIP_IS_E3(bp)) | |
715 | return PAGE_READ_REGS_E3; | |
716 | else | |
717 | return 0; | |
718 | } | |
719 | ||
07ba6af4 MS |
720 | static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, |
721 | const struct reg_addr *reg_info) | |
0fea29c1 | 722 | { |
07ba6af4 MS |
723 | if (CHIP_IS_E1(bp)) |
724 | return IS_E1_REG(reg_info->chips); | |
725 | else if (CHIP_IS_E1H(bp)) | |
726 | return IS_E1H_REG(reg_info->chips); | |
727 | else if (CHIP_IS_E2(bp)) | |
728 | return IS_E2_REG(reg_info->chips); | |
729 | else if (CHIP_IS_E3A0(bp)) | |
730 | return IS_E3A0_REG(reg_info->chips); | |
731 | else if (CHIP_IS_E3B0(bp)) | |
732 | return IS_E3B0_REG(reg_info->chips); | |
733 | else | |
734 | return false; | |
0fea29c1 | 735 | } |
de0c62db | 736 | |
07ba6af4 MS |
737 | static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, |
738 | const struct wreg_addr *wreg_info) | |
739 | { | |
740 | if (CHIP_IS_E1(bp)) | |
741 | return IS_E1_REG(wreg_info->chips); | |
742 | else if (CHIP_IS_E1H(bp)) | |
743 | return IS_E1H_REG(wreg_info->chips); | |
744 | else if (CHIP_IS_E2(bp)) | |
745 | return IS_E2_REG(wreg_info->chips); | |
746 | else if (CHIP_IS_E3A0(bp)) | |
747 | return IS_E3A0_REG(wreg_info->chips); | |
748 | else if (CHIP_IS_E3B0(bp)) | |
749 | return IS_E3B0_REG(wreg_info->chips); | |
750 | else | |
751 | return false; | |
de0c62db DK |
752 | } |
753 | ||
0fea29c1 VZ |
754 | /** |
755 | * bnx2x_read_pages_regs - read "paged" registers | |
756 | * | |
757 | * @bp device handle | |
758 | * @p output buffer | |
759 | * | |
2de67439 YM |
760 | * Reads "paged" memories: memories that may only be read by first writing to a |
761 | * specific address ("write address") and then reading from a specific address | |
762 | * ("read address"). There may be more than one write address per "page" and | |
763 | * more than one read address per write address. | |
0fea29c1 | 764 | */ |
07ba6af4 | 765 | static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) |
f2e0899f DK |
766 | { |
767 | u32 i, j, k, n; | |
07ba6af4 | 768 | |
0fea29c1 VZ |
769 | /* addresses of the paged registers */ |
770 | const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); | |
771 | /* number of paged registers */ | |
772 | int num_pages = __bnx2x_get_page_reg_num(bp); | |
773 | /* write addresses */ | |
774 | const u32 *write_addr = __bnx2x_get_page_write_ar(bp); | |
775 | /* number of write addresses */ | |
776 | int write_num = __bnx2x_get_page_write_num(bp); | |
777 | /* read addresses info */ | |
778 | const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); | |
779 | /* number of read addresses */ | |
780 | int read_num = __bnx2x_get_page_read_num(bp); | |
07ba6af4 | 781 | u32 addr, size; |
0fea29c1 VZ |
782 | |
783 | for (i = 0; i < num_pages; i++) { | |
784 | for (j = 0; j < write_num; j++) { | |
785 | REG_WR(bp, write_addr[j], page_addr[i]); | |
07ba6af4 MS |
786 | |
787 | for (k = 0; k < read_num; k++) { | |
788 | if (IS_REG_IN_PRESET(read_addr[k].presets, | |
789 | preset)) { | |
790 | size = read_addr[k].size; | |
791 | for (n = 0; n < size; n++) { | |
792 | addr = read_addr[k].addr + n*4; | |
793 | *p++ = REG_RD(bp, addr); | |
794 | } | |
795 | } | |
796 | } | |
f2e0899f DK |
797 | } |
798 | } | |
799 | } | |
800 | ||
07ba6af4 | 801 | static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) |
0fea29c1 | 802 | { |
07ba6af4 MS |
803 | u32 i, j, addr; |
804 | const struct wreg_addr *wreg_addr_p = NULL; | |
805 | ||
806 | if (CHIP_IS_E1(bp)) | |
807 | wreg_addr_p = &wreg_addr_e1; | |
808 | else if (CHIP_IS_E1H(bp)) | |
809 | wreg_addr_p = &wreg_addr_e1h; | |
810 | else if (CHIP_IS_E2(bp)) | |
811 | wreg_addr_p = &wreg_addr_e2; | |
812 | else if (CHIP_IS_E3A0(bp)) | |
813 | wreg_addr_p = &wreg_addr_e3; | |
814 | else if (CHIP_IS_E3B0(bp)) | |
815 | wreg_addr_p = &wreg_addr_e3b0; | |
816 | ||
817 | /* Read the idle_chk registers */ | |
818 | for (i = 0; i < IDLE_REGS_COUNT; i++) { | |
819 | if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && | |
820 | IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { | |
821 | for (j = 0; j < idle_reg_addrs[i].size; j++) | |
822 | *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); | |
823 | } | |
824 | } | |
0fea29c1 VZ |
825 | |
826 | /* Read the regular registers */ | |
07ba6af4 MS |
827 | for (i = 0; i < REGS_COUNT; i++) { |
828 | if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && | |
829 | IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { | |
0fea29c1 VZ |
830 | for (j = 0; j < reg_addrs[i].size; j++) |
831 | *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); | |
07ba6af4 MS |
832 | } |
833 | } | |
834 | ||
835 | /* Read the CAM registers */ | |
836 | if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && | |
837 | IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { | |
838 | for (i = 0; i < wreg_addr_p->size; i++) { | |
839 | *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); | |
840 | ||
841 | /* In case of wreg_addr register, read additional | |
842 | registers from read_regs array | |
843 | */ | |
844 | for (j = 0; j < wreg_addr_p->read_regs_count; j++) { | |
845 | addr = *(wreg_addr_p->read_regs); | |
846 | *p++ = REG_RD(bp, addr + j*4); | |
847 | } | |
848 | } | |
849 | } | |
850 | ||
851 | /* Paged registers are supported in E2 & E3 only */ | |
852 | if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { | |
16a5fd92 | 853 | /* Read "paged" registers */ |
07ba6af4 MS |
854 | bnx2x_read_pages_regs(bp, p, preset); |
855 | } | |
856 | ||
857 | return 0; | |
858 | } | |
859 | ||
860 | static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) | |
861 | { | |
862 | u32 preset_idx; | |
0fea29c1 | 863 | |
07ba6af4 MS |
864 | /* Read all registers, by reading all preset registers */ |
865 | for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { | |
866 | /* Skip presets with IOR */ | |
867 | if ((preset_idx == 2) || | |
868 | (preset_idx == 5) || | |
869 | (preset_idx == 8) || | |
870 | (preset_idx == 11)) | |
871 | continue; | |
872 | __bnx2x_get_preset_regs(bp, p, preset_idx); | |
873 | p += __bnx2x_get_preset_regs_len(bp, preset_idx); | |
874 | } | |
0fea29c1 VZ |
875 | } |
876 | ||
de0c62db DK |
877 | static void bnx2x_get_regs(struct net_device *dev, |
878 | struct ethtool_regs *regs, void *_p) | |
879 | { | |
0fea29c1 | 880 | u32 *p = _p; |
de0c62db | 881 | struct bnx2x *bp = netdev_priv(dev); |
07ba6af4 | 882 | struct dump_header dump_hdr = {0}; |
de0c62db | 883 | |
07ba6af4 | 884 | regs->version = 2; |
de0c62db DK |
885 | memset(p, 0, regs->len); |
886 | ||
887 | if (!netif_running(bp->dev)) | |
888 | return; | |
889 | ||
4a33bc03 VZ |
890 | /* Disable parity attentions as long as following dump may |
891 | * cause false alarms by reading never written registers. We | |
892 | * will re-enable parity attentions right after the dump. | |
893 | */ | |
07ba6af4 | 894 | |
4a33bc03 VZ |
895 | bnx2x_disable_blocks_parity(bp); |
896 | ||
07ba6af4 MS |
897 | dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; |
898 | dump_hdr.preset = DUMP_ALL_PRESETS; | |
899 | dump_hdr.version = BNX2X_DUMP_VERSION; | |
900 | ||
901 | /* dump_meta_data presents OR of CHIP and PATH. */ | |
902 | if (CHIP_IS_E1(bp)) { | |
903 | dump_hdr.dump_meta_data = DUMP_CHIP_E1; | |
904 | } else if (CHIP_IS_E1H(bp)) { | |
905 | dump_hdr.dump_meta_data = DUMP_CHIP_E1H; | |
906 | } else if (CHIP_IS_E2(bp)) { | |
907 | dump_hdr.dump_meta_data = DUMP_CHIP_E2 | | |
908 | (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); | |
909 | } else if (CHIP_IS_E3A0(bp)) { | |
910 | dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | | |
911 | (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); | |
912 | } else if (CHIP_IS_E3B0(bp)) { | |
913 | dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | | |
914 | (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); | |
915 | } | |
916 | ||
917 | memcpy(p, &dump_hdr, sizeof(struct dump_header)); | |
918 | p += dump_hdr.header_size + 1; | |
de0c62db | 919 | |
0fea29c1 VZ |
920 | /* Actually read the registers */ |
921 | __bnx2x_get_regs(bp, p); | |
922 | ||
4293b9f5 | 923 | /* Re-enable parity attentions */ |
07ba6af4 MS |
924 | bnx2x_clear_blocks_parity(bp); |
925 | bnx2x_enable_blocks_parity(bp); | |
07ba6af4 MS |
926 | } |
927 | ||
928 | static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) | |
929 | { | |
930 | struct bnx2x *bp = netdev_priv(dev); | |
931 | int regdump_len = 0; | |
932 | ||
933 | regdump_len = __bnx2x_get_preset_regs_len(bp, preset); | |
934 | regdump_len *= 4; | |
935 | regdump_len += sizeof(struct dump_header); | |
936 | ||
937 | return regdump_len; | |
938 | } | |
939 | ||
940 | static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) | |
941 | { | |
942 | struct bnx2x *bp = netdev_priv(dev); | |
943 | ||
944 | /* Use the ethtool_dump "flag" field as the dump preset index */ | |
5bb680d6 MS |
945 | if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) |
946 | return -EINVAL; | |
947 | ||
07ba6af4 MS |
948 | bp->dump_preset_idx = val->flag; |
949 | return 0; | |
950 | } | |
951 | ||
952 | static int bnx2x_get_dump_flag(struct net_device *dev, | |
953 | struct ethtool_dump *dump) | |
954 | { | |
955 | struct bnx2x *bp = netdev_priv(dev); | |
956 | ||
8cc2d927 MS |
957 | dump->version = BNX2X_DUMP_VERSION; |
958 | dump->flag = bp->dump_preset_idx; | |
07ba6af4 MS |
959 | /* Calculate the requested preset idx length */ |
960 | dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); | |
961 | DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", | |
962 | bp->dump_preset_idx, dump->len); | |
07ba6af4 MS |
963 | return 0; |
964 | } | |
965 | ||
966 | static int bnx2x_get_dump_data(struct net_device *dev, | |
967 | struct ethtool_dump *dump, | |
968 | void *buffer) | |
969 | { | |
970 | u32 *p = buffer; | |
971 | struct bnx2x *bp = netdev_priv(dev); | |
972 | struct dump_header dump_hdr = {0}; | |
973 | ||
07ba6af4 MS |
974 | /* Disable parity attentions as long as following dump may |
975 | * cause false alarms by reading never written registers. We | |
976 | * will re-enable parity attentions right after the dump. | |
977 | */ | |
978 | ||
07ba6af4 MS |
979 | bnx2x_disable_blocks_parity(bp); |
980 | ||
07ba6af4 MS |
981 | dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; |
982 | dump_hdr.preset = bp->dump_preset_idx; | |
983 | dump_hdr.version = BNX2X_DUMP_VERSION; | |
984 | ||
985 | DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); | |
986 | ||
987 | /* dump_meta_data presents OR of CHIP and PATH. */ | |
988 | if (CHIP_IS_E1(bp)) { | |
989 | dump_hdr.dump_meta_data = DUMP_CHIP_E1; | |
990 | } else if (CHIP_IS_E1H(bp)) { | |
991 | dump_hdr.dump_meta_data = DUMP_CHIP_E1H; | |
992 | } else if (CHIP_IS_E2(bp)) { | |
993 | dump_hdr.dump_meta_data = DUMP_CHIP_E2 | | |
994 | (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); | |
995 | } else if (CHIP_IS_E3A0(bp)) { | |
996 | dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | | |
997 | (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); | |
998 | } else if (CHIP_IS_E3B0(bp)) { | |
999 | dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | | |
1000 | (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); | |
1001 | } | |
1002 | ||
1003 | memcpy(p, &dump_hdr, sizeof(struct dump_header)); | |
1004 | p += dump_hdr.header_size + 1; | |
1005 | ||
1006 | /* Actually read the registers */ | |
1007 | __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); | |
1008 | ||
4293b9f5 | 1009 | /* Re-enable parity attentions */ |
07ba6af4 MS |
1010 | bnx2x_clear_blocks_parity(bp); |
1011 | bnx2x_enable_blocks_parity(bp); | |
1012 | ||
07ba6af4 | 1013 | return 0; |
de0c62db DK |
1014 | } |
1015 | ||
de0c62db DK |
1016 | static void bnx2x_get_drvinfo(struct net_device *dev, |
1017 | struct ethtool_drvinfo *info) | |
1018 | { | |
1019 | struct bnx2x *bp = netdev_priv(dev); | |
de0c62db | 1020 | |
68aad78c RJ |
1021 | strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); |
1022 | strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); | |
de0c62db | 1023 | |
8ca5e17e AE |
1024 | bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version)); |
1025 | ||
68aad78c | 1026 | strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); |
de0c62db | 1027 | info->n_stats = BNX2X_NUM_STATS; |
cf2c1df6 | 1028 | info->testinfo_len = BNX2X_NUM_TESTS(bp); |
de0c62db DK |
1029 | info->eedump_len = bp->common.flash_size; |
1030 | info->regdump_len = bnx2x_get_regs_len(dev); | |
1031 | } | |
1032 | ||
1033 | static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1034 | { | |
1035 | struct bnx2x *bp = netdev_priv(dev); | |
1036 | ||
1037 | if (bp->flags & NO_WOL_FLAG) { | |
1038 | wol->supported = 0; | |
1039 | wol->wolopts = 0; | |
1040 | } else { | |
1041 | wol->supported = WAKE_MAGIC; | |
1042 | if (bp->wol) | |
1043 | wol->wolopts = WAKE_MAGIC; | |
1044 | else | |
1045 | wol->wolopts = 0; | |
1046 | } | |
1047 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
1048 | } | |
1049 | ||
1050 | static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1051 | { | |
1052 | struct bnx2x *bp = netdev_priv(dev); | |
1053 | ||
51c1a580 | 1054 | if (wol->wolopts & ~WAKE_MAGIC) { |
2de67439 | 1055 | DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); |
de0c62db | 1056 | return -EINVAL; |
51c1a580 | 1057 | } |
de0c62db DK |
1058 | |
1059 | if (wol->wolopts & WAKE_MAGIC) { | |
51c1a580 | 1060 | if (bp->flags & NO_WOL_FLAG) { |
2de67439 | 1061 | DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); |
de0c62db | 1062 | return -EINVAL; |
51c1a580 | 1063 | } |
de0c62db DK |
1064 | bp->wol = 1; |
1065 | } else | |
1066 | bp->wol = 0; | |
1067 | ||
1068 | return 0; | |
1069 | } | |
1070 | ||
1071 | static u32 bnx2x_get_msglevel(struct net_device *dev) | |
1072 | { | |
1073 | struct bnx2x *bp = netdev_priv(dev); | |
1074 | ||
1075 | return bp->msg_enable; | |
1076 | } | |
1077 | ||
1078 | static void bnx2x_set_msglevel(struct net_device *dev, u32 level) | |
1079 | { | |
1080 | struct bnx2x *bp = netdev_priv(dev); | |
1081 | ||
7a25cc73 DK |
1082 | if (capable(CAP_NET_ADMIN)) { |
1083 | /* dump MCP trace */ | |
ad5afc89 | 1084 | if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) |
7a25cc73 | 1085 | bnx2x_fw_dump_lvl(bp, KERN_INFO); |
de0c62db | 1086 | bp->msg_enable = level; |
7a25cc73 | 1087 | } |
de0c62db DK |
1088 | } |
1089 | ||
1090 | static int bnx2x_nway_reset(struct net_device *dev) | |
1091 | { | |
1092 | struct bnx2x *bp = netdev_priv(dev); | |
1093 | ||
1094 | if (!bp->port.pmf) | |
1095 | return 0; | |
1096 | ||
1097 | if (netif_running(dev)) { | |
1098 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
5d07d868 | 1099 | bnx2x_force_link_reset(bp); |
de0c62db DK |
1100 | bnx2x_link_set(bp); |
1101 | } | |
1102 | ||
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | static u32 bnx2x_get_link(struct net_device *dev) | |
1107 | { | |
1108 | struct bnx2x *bp = netdev_priv(dev); | |
1109 | ||
f2e0899f | 1110 | if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) |
de0c62db DK |
1111 | return 0; |
1112 | ||
1113 | return bp->link_vars.link_up; | |
1114 | } | |
1115 | ||
1116 | static int bnx2x_get_eeprom_len(struct net_device *dev) | |
1117 | { | |
1118 | struct bnx2x *bp = netdev_priv(dev); | |
1119 | ||
1120 | return bp->common.flash_size; | |
1121 | } | |
1122 | ||
16a5fd92 YM |
1123 | /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, |
1124 | * had we done things the other way around, if two pfs from the same port would | |
f16da43b AE |
1125 | * attempt to access nvram at the same time, we could run into a scenario such |
1126 | * as: | |
1127 | * pf A takes the port lock. | |
1128 | * pf B succeeds in taking the same lock since they are from the same port. | |
1129 | * pf A takes the per pf misc lock. Performs eeprom access. | |
1130 | * pf A finishes. Unlocks the per pf misc lock. | |
1131 | * Pf B takes the lock and proceeds to perform it's own access. | |
1132 | * pf A unlocks the per port lock, while pf B is still working (!). | |
1133 | * mcp takes the per port lock and corrupts pf B's access (and/or has it's own | |
2de67439 | 1134 | * access corrupted by pf B) |
f16da43b | 1135 | */ |
de0c62db DK |
1136 | static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) |
1137 | { | |
1138 | int port = BP_PORT(bp); | |
1139 | int count, i; | |
f16da43b AE |
1140 | u32 val; |
1141 | ||
1142 | /* acquire HW lock: protect against other PFs in PF Direct Assignment */ | |
1143 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); | |
de0c62db DK |
1144 | |
1145 | /* adjust timeout for emulation/FPGA */ | |
754a2f52 | 1146 | count = BNX2X_NVRAM_TIMEOUT_COUNT; |
de0c62db DK |
1147 | if (CHIP_REV_IS_SLOW(bp)) |
1148 | count *= 100; | |
1149 | ||
1150 | /* request access to nvram interface */ | |
1151 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
1152 | (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); | |
1153 | ||
1154 | for (i = 0; i < count*10; i++) { | |
1155 | val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); | |
1156 | if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) | |
1157 | break; | |
1158 | ||
1159 | udelay(5); | |
1160 | } | |
1161 | ||
1162 | if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { | |
51c1a580 MS |
1163 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
1164 | "cannot get access to nvram interface\n"); | |
de0c62db DK |
1165 | return -EBUSY; |
1166 | } | |
1167 | ||
1168 | return 0; | |
1169 | } | |
1170 | ||
1171 | static int bnx2x_release_nvram_lock(struct bnx2x *bp) | |
1172 | { | |
1173 | int port = BP_PORT(bp); | |
1174 | int count, i; | |
f16da43b | 1175 | u32 val; |
de0c62db DK |
1176 | |
1177 | /* adjust timeout for emulation/FPGA */ | |
754a2f52 | 1178 | count = BNX2X_NVRAM_TIMEOUT_COUNT; |
de0c62db DK |
1179 | if (CHIP_REV_IS_SLOW(bp)) |
1180 | count *= 100; | |
1181 | ||
1182 | /* relinquish nvram interface */ | |
1183 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
1184 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); | |
1185 | ||
1186 | for (i = 0; i < count*10; i++) { | |
1187 | val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); | |
1188 | if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) | |
1189 | break; | |
1190 | ||
1191 | udelay(5); | |
1192 | } | |
1193 | ||
1194 | if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { | |
51c1a580 MS |
1195 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
1196 | "cannot free access to nvram interface\n"); | |
de0c62db DK |
1197 | return -EBUSY; |
1198 | } | |
1199 | ||
f16da43b AE |
1200 | /* release HW lock: protect against other PFs in PF Direct Assignment */ |
1201 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); | |
de0c62db DK |
1202 | return 0; |
1203 | } | |
1204 | ||
1205 | static void bnx2x_enable_nvram_access(struct bnx2x *bp) | |
1206 | { | |
1207 | u32 val; | |
1208 | ||
1209 | val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); | |
1210 | ||
1211 | /* enable both bits, even on read */ | |
1212 | REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, | |
1213 | (val | MCPR_NVM_ACCESS_ENABLE_EN | | |
1214 | MCPR_NVM_ACCESS_ENABLE_WR_EN)); | |
1215 | } | |
1216 | ||
1217 | static void bnx2x_disable_nvram_access(struct bnx2x *bp) | |
1218 | { | |
1219 | u32 val; | |
1220 | ||
1221 | val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); | |
1222 | ||
1223 | /* disable both bits, even after read */ | |
1224 | REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, | |
1225 | (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | | |
1226 | MCPR_NVM_ACCESS_ENABLE_WR_EN))); | |
1227 | } | |
1228 | ||
1229 | static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, | |
1230 | u32 cmd_flags) | |
1231 | { | |
1232 | int count, i, rc; | |
1233 | u32 val; | |
1234 | ||
1235 | /* build the command word */ | |
1236 | cmd_flags |= MCPR_NVM_COMMAND_DOIT; | |
1237 | ||
1238 | /* need to clear DONE bit separately */ | |
1239 | REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); | |
1240 | ||
1241 | /* address of the NVRAM to read from */ | |
1242 | REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, | |
1243 | (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); | |
1244 | ||
1245 | /* issue a read command */ | |
1246 | REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); | |
1247 | ||
1248 | /* adjust timeout for emulation/FPGA */ | |
754a2f52 | 1249 | count = BNX2X_NVRAM_TIMEOUT_COUNT; |
de0c62db DK |
1250 | if (CHIP_REV_IS_SLOW(bp)) |
1251 | count *= 100; | |
1252 | ||
1253 | /* wait for completion */ | |
1254 | *ret_val = 0; | |
1255 | rc = -EBUSY; | |
1256 | for (i = 0; i < count; i++) { | |
1257 | udelay(5); | |
1258 | val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); | |
1259 | ||
1260 | if (val & MCPR_NVM_COMMAND_DONE) { | |
1261 | val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); | |
1262 | /* we read nvram data in cpu order | |
1263 | * but ethtool sees it as an array of bytes | |
07ba6af4 MS |
1264 | * converting to big-endian will do the work |
1265 | */ | |
de0c62db DK |
1266 | *ret_val = cpu_to_be32(val); |
1267 | rc = 0; | |
1268 | break; | |
1269 | } | |
1270 | } | |
51c1a580 MS |
1271 | if (rc == -EBUSY) |
1272 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
1273 | "nvram read timeout expired\n"); | |
de0c62db DK |
1274 | return rc; |
1275 | } | |
1276 | ||
1277 | static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, | |
1278 | int buf_size) | |
1279 | { | |
1280 | int rc; | |
1281 | u32 cmd_flags; | |
1282 | __be32 val; | |
1283 | ||
1284 | if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { | |
51c1a580 | 1285 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
de0c62db DK |
1286 | "Invalid parameter: offset 0x%x buf_size 0x%x\n", |
1287 | offset, buf_size); | |
1288 | return -EINVAL; | |
1289 | } | |
1290 | ||
1291 | if (offset + buf_size > bp->common.flash_size) { | |
51c1a580 MS |
1292 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
1293 | "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", | |
de0c62db DK |
1294 | offset, buf_size, bp->common.flash_size); |
1295 | return -EINVAL; | |
1296 | } | |
1297 | ||
1298 | /* request access to nvram interface */ | |
1299 | rc = bnx2x_acquire_nvram_lock(bp); | |
1300 | if (rc) | |
1301 | return rc; | |
1302 | ||
1303 | /* enable access to nvram interface */ | |
1304 | bnx2x_enable_nvram_access(bp); | |
1305 | ||
1306 | /* read the first word(s) */ | |
1307 | cmd_flags = MCPR_NVM_COMMAND_FIRST; | |
1308 | while ((buf_size > sizeof(u32)) && (rc == 0)) { | |
1309 | rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); | |
1310 | memcpy(ret_buf, &val, 4); | |
1311 | ||
1312 | /* advance to the next dword */ | |
1313 | offset += sizeof(u32); | |
1314 | ret_buf += sizeof(u32); | |
1315 | buf_size -= sizeof(u32); | |
1316 | cmd_flags = 0; | |
1317 | } | |
1318 | ||
1319 | if (rc == 0) { | |
1320 | cmd_flags |= MCPR_NVM_COMMAND_LAST; | |
1321 | rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); | |
1322 | memcpy(ret_buf, &val, 4); | |
1323 | } | |
1324 | ||
1325 | /* disable access to nvram interface */ | |
1326 | bnx2x_disable_nvram_access(bp); | |
1327 | bnx2x_release_nvram_lock(bp); | |
1328 | ||
1329 | return rc; | |
1330 | } | |
1331 | ||
85640952 DK |
1332 | static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, |
1333 | int buf_size) | |
1334 | { | |
1335 | int rc; | |
1336 | ||
1337 | rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); | |
1338 | ||
1339 | if (!rc) { | |
1340 | __be32 *be = (__be32 *)buf; | |
1341 | ||
1342 | while ((buf_size -= 4) >= 0) | |
1343 | *buf++ = be32_to_cpu(*be++); | |
1344 | } | |
1345 | ||
1346 | return rc; | |
1347 | } | |
1348 | ||
3fb43eb2 YM |
1349 | static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) |
1350 | { | |
1351 | int rc = 1; | |
1352 | u16 pm = 0; | |
1353 | struct net_device *dev = pci_get_drvdata(bp->pdev); | |
1354 | ||
29ed74c3 | 1355 | if (bp->pdev->pm_cap) |
3fb43eb2 | 1356 | rc = pci_read_config_word(bp->pdev, |
29ed74c3 | 1357 | bp->pdev->pm_cap + PCI_PM_CTRL, &pm); |
3fb43eb2 | 1358 | |
829a5071 | 1359 | if ((rc && !netif_running(dev)) || |
c957d09f | 1360 | (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) |
3fb43eb2 YM |
1361 | return false; |
1362 | ||
1363 | return true; | |
1364 | } | |
1365 | ||
de0c62db DK |
1366 | static int bnx2x_get_eeprom(struct net_device *dev, |
1367 | struct ethtool_eeprom *eeprom, u8 *eebuf) | |
1368 | { | |
1369 | struct bnx2x *bp = netdev_priv(dev); | |
de0c62db | 1370 | |
3fb43eb2 | 1371 | if (!bnx2x_is_nvm_accessible(bp)) { |
51c1a580 MS |
1372 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
1373 | "cannot access eeprom when the interface is down\n"); | |
de0c62db | 1374 | return -EAGAIN; |
51c1a580 | 1375 | } |
de0c62db | 1376 | |
51c1a580 | 1377 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" |
f1deab50 | 1378 | " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", |
de0c62db DK |
1379 | eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, |
1380 | eeprom->len, eeprom->len); | |
1381 | ||
1382 | /* parameters already validated in ethtool_get_eeprom */ | |
1383 | ||
f1691dc6 | 1384 | return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); |
de0c62db DK |
1385 | } |
1386 | ||
24ea818e YM |
1387 | static int bnx2x_get_module_eeprom(struct net_device *dev, |
1388 | struct ethtool_eeprom *ee, | |
1389 | u8 *data) | |
1390 | { | |
1391 | struct bnx2x *bp = netdev_priv(dev); | |
669d6996 | 1392 | int rc = -EINVAL, phy_idx; |
24ea818e | 1393 | u8 *user_data = data; |
669d6996 | 1394 | unsigned int start_addr = ee->offset, xfer_size = 0; |
24ea818e | 1395 | |
3fb43eb2 | 1396 | if (!bnx2x_is_nvm_accessible(bp)) { |
24ea818e YM |
1397 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
1398 | "cannot access eeprom when the interface is down\n"); | |
1399 | return -EAGAIN; | |
1400 | } | |
1401 | ||
1402 | phy_idx = bnx2x_get_cur_phy_idx(bp); | |
669d6996 YR |
1403 | |
1404 | /* Read A0 section */ | |
1405 | if (start_addr < ETH_MODULE_SFF_8079_LEN) { | |
1406 | /* Limit transfer size to the A0 section boundary */ | |
1407 | if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) | |
1408 | xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; | |
1409 | else | |
1410 | xfer_size = ee->len; | |
1411 | bnx2x_acquire_phy_lock(bp); | |
24ea818e YM |
1412 | rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], |
1413 | &bp->link_params, | |
669d6996 YR |
1414 | I2C_DEV_ADDR_A0, |
1415 | start_addr, | |
24ea818e YM |
1416 | xfer_size, |
1417 | user_data); | |
669d6996 YR |
1418 | bnx2x_release_phy_lock(bp); |
1419 | if (rc) { | |
1420 | DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); | |
1421 | ||
1422 | return -EINVAL; | |
1423 | } | |
24ea818e | 1424 | user_data += xfer_size; |
669d6996 | 1425 | start_addr += xfer_size; |
24ea818e YM |
1426 | } |
1427 | ||
669d6996 YR |
1428 | /* Read A2 section */ |
1429 | if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && | |
1430 | (start_addr < ETH_MODULE_SFF_8472_LEN)) { | |
1431 | xfer_size = ee->len - xfer_size; | |
1432 | /* Limit transfer size to the A2 section boundary */ | |
1433 | if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) | |
1434 | xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; | |
1435 | start_addr -= ETH_MODULE_SFF_8079_LEN; | |
1436 | bnx2x_acquire_phy_lock(bp); | |
1437 | rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], | |
1438 | &bp->link_params, | |
1439 | I2C_DEV_ADDR_A2, | |
1440 | start_addr, | |
1441 | xfer_size, | |
1442 | user_data); | |
1443 | bnx2x_release_phy_lock(bp); | |
1444 | if (rc) { | |
1445 | DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); | |
1446 | return -EINVAL; | |
1447 | } | |
1448 | } | |
24ea818e YM |
1449 | return rc; |
1450 | } | |
1451 | ||
1452 | static int bnx2x_get_module_info(struct net_device *dev, | |
1453 | struct ethtool_modinfo *modinfo) | |
1454 | { | |
1455 | struct bnx2x *bp = netdev_priv(dev); | |
669d6996 YR |
1456 | int phy_idx, rc; |
1457 | u8 sff8472_comp, diag_type; | |
1458 | ||
3fb43eb2 | 1459 | if (!bnx2x_is_nvm_accessible(bp)) { |
669d6996 | 1460 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
24ea818e YM |
1461 | "cannot access eeprom when the interface is down\n"); |
1462 | return -EAGAIN; | |
1463 | } | |
24ea818e | 1464 | phy_idx = bnx2x_get_cur_phy_idx(bp); |
669d6996 YR |
1465 | bnx2x_acquire_phy_lock(bp); |
1466 | rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], | |
1467 | &bp->link_params, | |
1468 | I2C_DEV_ADDR_A0, | |
1469 | SFP_EEPROM_SFF_8472_COMP_ADDR, | |
1470 | SFP_EEPROM_SFF_8472_COMP_SIZE, | |
1471 | &sff8472_comp); | |
1472 | bnx2x_release_phy_lock(bp); | |
1473 | if (rc) { | |
1474 | DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); | |
1475 | return -EINVAL; | |
1476 | } | |
1477 | ||
1478 | bnx2x_acquire_phy_lock(bp); | |
1479 | rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], | |
1480 | &bp->link_params, | |
1481 | I2C_DEV_ADDR_A0, | |
1482 | SFP_EEPROM_DIAG_TYPE_ADDR, | |
1483 | SFP_EEPROM_DIAG_TYPE_SIZE, | |
1484 | &diag_type); | |
1485 | bnx2x_release_phy_lock(bp); | |
1486 | if (rc) { | |
1487 | DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); | |
1488 | return -EINVAL; | |
1489 | } | |
1490 | ||
1491 | if (!sff8472_comp || | |
1492 | (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { | |
24ea818e YM |
1493 | modinfo->type = ETH_MODULE_SFF_8079; |
1494 | modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; | |
669d6996 YR |
1495 | } else { |
1496 | modinfo->type = ETH_MODULE_SFF_8472; | |
1497 | modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; | |
24ea818e | 1498 | } |
669d6996 | 1499 | return 0; |
24ea818e YM |
1500 | } |
1501 | ||
de0c62db DK |
1502 | static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, |
1503 | u32 cmd_flags) | |
1504 | { | |
1505 | int count, i, rc; | |
1506 | ||
1507 | /* build the command word */ | |
1508 | cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; | |
1509 | ||
1510 | /* need to clear DONE bit separately */ | |
1511 | REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); | |
1512 | ||
1513 | /* write the data */ | |
1514 | REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); | |
1515 | ||
1516 | /* address of the NVRAM to write to */ | |
1517 | REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, | |
1518 | (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); | |
1519 | ||
1520 | /* issue the write command */ | |
1521 | REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); | |
1522 | ||
1523 | /* adjust timeout for emulation/FPGA */ | |
754a2f52 | 1524 | count = BNX2X_NVRAM_TIMEOUT_COUNT; |
de0c62db DK |
1525 | if (CHIP_REV_IS_SLOW(bp)) |
1526 | count *= 100; | |
1527 | ||
1528 | /* wait for completion */ | |
1529 | rc = -EBUSY; | |
1530 | for (i = 0; i < count; i++) { | |
1531 | udelay(5); | |
1532 | val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); | |
1533 | if (val & MCPR_NVM_COMMAND_DONE) { | |
1534 | rc = 0; | |
1535 | break; | |
1536 | } | |
1537 | } | |
1538 | ||
51c1a580 MS |
1539 | if (rc == -EBUSY) |
1540 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
1541 | "nvram write timeout expired\n"); | |
de0c62db DK |
1542 | return rc; |
1543 | } | |
1544 | ||
1545 | #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) | |
1546 | ||
1547 | static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, | |
1548 | int buf_size) | |
1549 | { | |
1550 | int rc; | |
30c20b67 DK |
1551 | u32 cmd_flags, align_offset, val; |
1552 | __be32 val_be; | |
de0c62db DK |
1553 | |
1554 | if (offset + buf_size > bp->common.flash_size) { | |
51c1a580 MS |
1555 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
1556 | "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", | |
de0c62db DK |
1557 | offset, buf_size, bp->common.flash_size); |
1558 | return -EINVAL; | |
1559 | } | |
1560 | ||
1561 | /* request access to nvram interface */ | |
1562 | rc = bnx2x_acquire_nvram_lock(bp); | |
1563 | if (rc) | |
1564 | return rc; | |
1565 | ||
1566 | /* enable access to nvram interface */ | |
1567 | bnx2x_enable_nvram_access(bp); | |
1568 | ||
1569 | cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); | |
1570 | align_offset = (offset & ~0x03); | |
30c20b67 | 1571 | rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); |
de0c62db DK |
1572 | |
1573 | if (rc == 0) { | |
de0c62db | 1574 | /* nvram data is returned as an array of bytes |
07ba6af4 MS |
1575 | * convert it back to cpu order |
1576 | */ | |
30c20b67 DK |
1577 | val = be32_to_cpu(val_be); |
1578 | ||
c957d09f YM |
1579 | val &= ~le32_to_cpu((__force __le32) |
1580 | (0xff << BYTE_OFFSET(offset))); | |
1581 | val |= le32_to_cpu((__force __le32) | |
1582 | (*data_buf << BYTE_OFFSET(offset))); | |
de0c62db DK |
1583 | |
1584 | rc = bnx2x_nvram_write_dword(bp, align_offset, val, | |
1585 | cmd_flags); | |
1586 | } | |
1587 | ||
1588 | /* disable access to nvram interface */ | |
1589 | bnx2x_disable_nvram_access(bp); | |
1590 | bnx2x_release_nvram_lock(bp); | |
1591 | ||
1592 | return rc; | |
1593 | } | |
1594 | ||
1595 | static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, | |
1596 | int buf_size) | |
1597 | { | |
1598 | int rc; | |
1599 | u32 cmd_flags; | |
1600 | u32 val; | |
1601 | u32 written_so_far; | |
1602 | ||
1603 | if (buf_size == 1) /* ethtool */ | |
1604 | return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); | |
1605 | ||
1606 | if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { | |
51c1a580 | 1607 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
de0c62db DK |
1608 | "Invalid parameter: offset 0x%x buf_size 0x%x\n", |
1609 | offset, buf_size); | |
1610 | return -EINVAL; | |
1611 | } | |
1612 | ||
1613 | if (offset + buf_size > bp->common.flash_size) { | |
51c1a580 MS |
1614 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
1615 | "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", | |
de0c62db DK |
1616 | offset, buf_size, bp->common.flash_size); |
1617 | return -EINVAL; | |
1618 | } | |
1619 | ||
1620 | /* request access to nvram interface */ | |
1621 | rc = bnx2x_acquire_nvram_lock(bp); | |
1622 | if (rc) | |
1623 | return rc; | |
1624 | ||
1625 | /* enable access to nvram interface */ | |
1626 | bnx2x_enable_nvram_access(bp); | |
1627 | ||
1628 | written_so_far = 0; | |
1629 | cmd_flags = MCPR_NVM_COMMAND_FIRST; | |
1630 | while ((written_so_far < buf_size) && (rc == 0)) { | |
1631 | if (written_so_far == (buf_size - sizeof(u32))) | |
1632 | cmd_flags |= MCPR_NVM_COMMAND_LAST; | |
754a2f52 | 1633 | else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) |
de0c62db | 1634 | cmd_flags |= MCPR_NVM_COMMAND_LAST; |
754a2f52 | 1635 | else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) |
de0c62db DK |
1636 | cmd_flags |= MCPR_NVM_COMMAND_FIRST; |
1637 | ||
1638 | memcpy(&val, data_buf, 4); | |
1639 | ||
68bf5a10 YM |
1640 | /* Notice unlike bnx2x_nvram_read_dword() this will not |
1641 | * change val using be32_to_cpu(), which causes data to flip | |
1642 | * if the eeprom is read and then written back. This is due | |
1643 | * to tools utilizing this functionality that would break | |
1644 | * if this would be resolved. | |
1645 | */ | |
de0c62db DK |
1646 | rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); |
1647 | ||
1648 | /* advance to the next dword */ | |
1649 | offset += sizeof(u32); | |
1650 | data_buf += sizeof(u32); | |
1651 | written_so_far += sizeof(u32); | |
1652 | cmd_flags = 0; | |
1653 | } | |
1654 | ||
1655 | /* disable access to nvram interface */ | |
1656 | bnx2x_disable_nvram_access(bp); | |
1657 | bnx2x_release_nvram_lock(bp); | |
1658 | ||
1659 | return rc; | |
1660 | } | |
1661 | ||
1662 | static int bnx2x_set_eeprom(struct net_device *dev, | |
1663 | struct ethtool_eeprom *eeprom, u8 *eebuf) | |
1664 | { | |
1665 | struct bnx2x *bp = netdev_priv(dev); | |
1666 | int port = BP_PORT(bp); | |
1667 | int rc = 0; | |
e10bc84d | 1668 | u32 ext_phy_config; |
3fb43eb2 YM |
1669 | |
1670 | if (!bnx2x_is_nvm_accessible(bp)) { | |
51c1a580 MS |
1671 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
1672 | "cannot access eeprom when the interface is down\n"); | |
de0c62db | 1673 | return -EAGAIN; |
51c1a580 | 1674 | } |
de0c62db | 1675 | |
51c1a580 | 1676 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" |
f1deab50 | 1677 | " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", |
de0c62db DK |
1678 | eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, |
1679 | eeprom->len, eeprom->len); | |
1680 | ||
1681 | /* parameters already validated in ethtool_set_eeprom */ | |
1682 | ||
1683 | /* PHY eeprom can be accessed only by the PMF */ | |
1684 | if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && | |
51c1a580 MS |
1685 | !bp->port.pmf) { |
1686 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
1687 | "wrong magic or interface is not pmf\n"); | |
de0c62db | 1688 | return -EINVAL; |
51c1a580 | 1689 | } |
de0c62db | 1690 | |
e10bc84d YR |
1691 | ext_phy_config = |
1692 | SHMEM_RD(bp, | |
1693 | dev_info.port_hw_config[port].external_phy_config); | |
1694 | ||
de0c62db DK |
1695 | if (eeprom->magic == 0x50485950) { |
1696 | /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ | |
1697 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
1698 | ||
1699 | bnx2x_acquire_phy_lock(bp); | |
1700 | rc |= bnx2x_link_reset(&bp->link_params, | |
1701 | &bp->link_vars, 0); | |
e10bc84d | 1702 | if (XGXS_EXT_PHY_TYPE(ext_phy_config) == |
de0c62db DK |
1703 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) |
1704 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
1705 | MISC_REGISTERS_GPIO_HIGH, port); | |
1706 | bnx2x_release_phy_lock(bp); | |
1707 | bnx2x_link_report(bp); | |
1708 | ||
1709 | } else if (eeprom->magic == 0x50485952) { | |
1710 | /* 'PHYR' (0x50485952): re-init link after FW upgrade */ | |
1711 | if (bp->state == BNX2X_STATE_OPEN) { | |
1712 | bnx2x_acquire_phy_lock(bp); | |
1713 | rc |= bnx2x_link_reset(&bp->link_params, | |
1714 | &bp->link_vars, 1); | |
1715 | ||
1716 | rc |= bnx2x_phy_init(&bp->link_params, | |
1717 | &bp->link_vars); | |
1718 | bnx2x_release_phy_lock(bp); | |
1719 | bnx2x_calc_fc_adv(bp); | |
1720 | } | |
1721 | } else if (eeprom->magic == 0x53985943) { | |
1722 | /* 'PHYC' (0x53985943): PHY FW upgrade completed */ | |
e10bc84d | 1723 | if (XGXS_EXT_PHY_TYPE(ext_phy_config) == |
de0c62db | 1724 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { |
de0c62db DK |
1725 | |
1726 | /* DSP Remove Download Mode */ | |
1727 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
1728 | MISC_REGISTERS_GPIO_LOW, port); | |
1729 | ||
1730 | bnx2x_acquire_phy_lock(bp); | |
1731 | ||
e10bc84d YR |
1732 | bnx2x_sfx7101_sp_sw_reset(bp, |
1733 | &bp->link_params.phy[EXT_PHY1]); | |
de0c62db DK |
1734 | |
1735 | /* wait 0.5 sec to allow it to run */ | |
1736 | msleep(500); | |
1737 | bnx2x_ext_phy_hw_reset(bp, port); | |
1738 | msleep(500); | |
1739 | bnx2x_release_phy_lock(bp); | |
1740 | } | |
1741 | } else | |
1742 | rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); | |
1743 | ||
1744 | return rc; | |
1745 | } | |
f85582f8 | 1746 | |
de0c62db DK |
1747 | static int bnx2x_get_coalesce(struct net_device *dev, |
1748 | struct ethtool_coalesce *coal) | |
1749 | { | |
1750 | struct bnx2x *bp = netdev_priv(dev); | |
1751 | ||
1752 | memset(coal, 0, sizeof(struct ethtool_coalesce)); | |
1753 | ||
1754 | coal->rx_coalesce_usecs = bp->rx_ticks; | |
1755 | coal->tx_coalesce_usecs = bp->tx_ticks; | |
1756 | ||
1757 | return 0; | |
1758 | } | |
1759 | ||
1760 | static int bnx2x_set_coalesce(struct net_device *dev, | |
1761 | struct ethtool_coalesce *coal) | |
1762 | { | |
1763 | struct bnx2x *bp = netdev_priv(dev); | |
1764 | ||
1765 | bp->rx_ticks = (u16)coal->rx_coalesce_usecs; | |
1766 | if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) | |
1767 | bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; | |
1768 | ||
1769 | bp->tx_ticks = (u16)coal->tx_coalesce_usecs; | |
1770 | if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) | |
1771 | bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; | |
1772 | ||
1773 | if (netif_running(dev)) | |
1774 | bnx2x_update_coalesce(bp); | |
1775 | ||
1776 | return 0; | |
1777 | } | |
1778 | ||
1779 | static void bnx2x_get_ringparam(struct net_device *dev, | |
1780 | struct ethtool_ringparam *ering) | |
1781 | { | |
1782 | struct bnx2x *bp = netdev_priv(dev); | |
1783 | ||
1784 | ering->rx_max_pending = MAX_RX_AVAIL; | |
de0c62db | 1785 | |
25141580 DK |
1786 | if (bp->rx_ring_size) |
1787 | ering->rx_pending = bp->rx_ring_size; | |
1788 | else | |
c2188952 | 1789 | ering->rx_pending = MAX_RX_AVAIL; |
25141580 | 1790 | |
a3348722 | 1791 | ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; |
de0c62db DK |
1792 | ering->tx_pending = bp->tx_ring_size; |
1793 | } | |
1794 | ||
1795 | static int bnx2x_set_ringparam(struct net_device *dev, | |
1796 | struct ethtool_ringparam *ering) | |
1797 | { | |
1798 | struct bnx2x *bp = netdev_priv(dev); | |
de0c62db | 1799 | |
04c46736 YM |
1800 | DP(BNX2X_MSG_ETHTOOL, |
1801 | "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", | |
1802 | ering->rx_pending, ering->tx_pending); | |
1803 | ||
de0c62db | 1804 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 MS |
1805 | DP(BNX2X_MSG_ETHTOOL, |
1806 | "Handling parity error recovery. Try again later\n"); | |
de0c62db DK |
1807 | return -EAGAIN; |
1808 | } | |
1809 | ||
1810 | if ((ering->rx_pending > MAX_RX_AVAIL) || | |
b3b83c3f DK |
1811 | (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : |
1812 | MIN_RX_SIZE_TPA)) || | |
a3348722 | 1813 | (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) || |
51c1a580 MS |
1814 | (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { |
1815 | DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); | |
de0c62db | 1816 | return -EINVAL; |
51c1a580 | 1817 | } |
de0c62db DK |
1818 | |
1819 | bp->rx_ring_size = ering->rx_pending; | |
1820 | bp->tx_ring_size = ering->tx_pending; | |
1821 | ||
a9fccec7 | 1822 | return bnx2x_reload_if_running(dev); |
de0c62db DK |
1823 | } |
1824 | ||
1825 | static void bnx2x_get_pauseparam(struct net_device *dev, | |
1826 | struct ethtool_pauseparam *epause) | |
1827 | { | |
1828 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 | 1829 | int cfg_idx = bnx2x_get_link_cfg_idx(bp); |
9e7e8399 MY |
1830 | int cfg_reg; |
1831 | ||
a22f0788 YR |
1832 | epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == |
1833 | BNX2X_FLOW_CTRL_AUTO); | |
de0c62db | 1834 | |
9e7e8399 | 1835 | if (!epause->autoneg) |
241fb5d2 | 1836 | cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; |
9e7e8399 MY |
1837 | else |
1838 | cfg_reg = bp->link_params.req_fc_auto_adv; | |
1839 | ||
1840 | epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == | |
de0c62db | 1841 | BNX2X_FLOW_CTRL_RX); |
9e7e8399 | 1842 | epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == |
de0c62db DK |
1843 | BNX2X_FLOW_CTRL_TX); |
1844 | ||
51c1a580 | 1845 | DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" |
f1deab50 | 1846 | " autoneg %d rx_pause %d tx_pause %d\n", |
de0c62db DK |
1847 | epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); |
1848 | } | |
1849 | ||
1850 | static int bnx2x_set_pauseparam(struct net_device *dev, | |
1851 | struct ethtool_pauseparam *epause) | |
1852 | { | |
1853 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 | 1854 | u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
fb3bff17 | 1855 | if (IS_MF(bp)) |
de0c62db DK |
1856 | return 0; |
1857 | ||
51c1a580 | 1858 | DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" |
f1deab50 | 1859 | " autoneg %d rx_pause %d tx_pause %d\n", |
de0c62db DK |
1860 | epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); |
1861 | ||
a22f0788 | 1862 | bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; |
de0c62db DK |
1863 | |
1864 | if (epause->rx_pause) | |
a22f0788 | 1865 | bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; |
de0c62db DK |
1866 | |
1867 | if (epause->tx_pause) | |
a22f0788 | 1868 | bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; |
de0c62db | 1869 | |
a22f0788 YR |
1870 | if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) |
1871 | bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; | |
de0c62db DK |
1872 | |
1873 | if (epause->autoneg) { | |
a22f0788 | 1874 | if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { |
51c1a580 | 1875 | DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); |
de0c62db DK |
1876 | return -EINVAL; |
1877 | } | |
1878 | ||
a22f0788 YR |
1879 | if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { |
1880 | bp->link_params.req_flow_ctrl[cfg_idx] = | |
1881 | BNX2X_FLOW_CTRL_AUTO; | |
1882 | } | |
ba35a0fd | 1883 | bp->link_params.req_fc_auto_adv = 0; |
5cd75f0c YR |
1884 | if (epause->rx_pause) |
1885 | bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; | |
1886 | ||
1887 | if (epause->tx_pause) | |
1888 | bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; | |
ba35a0fd YR |
1889 | |
1890 | if (!bp->link_params.req_fc_auto_adv) | |
1891 | bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; | |
de0c62db DK |
1892 | } |
1893 | ||
51c1a580 | 1894 | DP(BNX2X_MSG_ETHTOOL, |
a22f0788 | 1895 | "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); |
de0c62db DK |
1896 | |
1897 | if (netif_running(dev)) { | |
1898 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
1899 | bnx2x_link_set(bp); | |
1900 | } | |
1901 | ||
1902 | return 0; | |
1903 | } | |
1904 | ||
5889335c | 1905 | static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { |
cf2c1df6 MS |
1906 | "register_test (offline) ", |
1907 | "memory_test (offline) ", | |
1908 | "int_loopback_test (offline)", | |
1909 | "ext_loopback_test (offline)", | |
1910 | "nvram_test (online) ", | |
1911 | "interrupt_test (online) ", | |
1912 | "link_test (online) " | |
de0c62db DK |
1913 | }; |
1914 | ||
3521b419 YM |
1915 | enum { |
1916 | BNX2X_PRI_FLAG_ISCSI, | |
1917 | BNX2X_PRI_FLAG_FCOE, | |
1918 | BNX2X_PRI_FLAG_STORAGE, | |
1919 | BNX2X_PRI_FLAG_LEN, | |
1920 | }; | |
1921 | ||
1922 | static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { | |
1923 | "iSCSI offload support", | |
1924 | "FCoE offload support", | |
1925 | "Storage only interface" | |
1926 | }; | |
1927 | ||
e9939c80 YM |
1928 | static u32 bnx2x_eee_to_adv(u32 eee_adv) |
1929 | { | |
1930 | u32 modes = 0; | |
1931 | ||
1932 | if (eee_adv & SHMEM_EEE_100M_ADV) | |
1933 | modes |= ADVERTISED_100baseT_Full; | |
1934 | if (eee_adv & SHMEM_EEE_1G_ADV) | |
1935 | modes |= ADVERTISED_1000baseT_Full; | |
1936 | if (eee_adv & SHMEM_EEE_10G_ADV) | |
1937 | modes |= ADVERTISED_10000baseT_Full; | |
1938 | ||
1939 | return modes; | |
1940 | } | |
1941 | ||
1942 | static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) | |
1943 | { | |
1944 | u32 eee_adv = 0; | |
1945 | if (modes & ADVERTISED_100baseT_Full) | |
1946 | eee_adv |= SHMEM_EEE_100M_ADV; | |
1947 | if (modes & ADVERTISED_1000baseT_Full) | |
1948 | eee_adv |= SHMEM_EEE_1G_ADV; | |
1949 | if (modes & ADVERTISED_10000baseT_Full) | |
1950 | eee_adv |= SHMEM_EEE_10G_ADV; | |
1951 | ||
1952 | return eee_adv << shift; | |
1953 | } | |
1954 | ||
1955 | static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) | |
1956 | { | |
1957 | struct bnx2x *bp = netdev_priv(dev); | |
1958 | u32 eee_cfg; | |
1959 | ||
1960 | if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { | |
1961 | DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); | |
1962 | return -EOPNOTSUPP; | |
1963 | } | |
1964 | ||
08e9acc2 | 1965 | eee_cfg = bp->link_vars.eee_status; |
e9939c80 YM |
1966 | |
1967 | edata->supported = | |
1968 | bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> | |
1969 | SHMEM_EEE_SUPPORTED_SHIFT); | |
1970 | ||
1971 | edata->advertised = | |
1972 | bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> | |
1973 | SHMEM_EEE_ADV_STATUS_SHIFT); | |
1974 | edata->lp_advertised = | |
1975 | bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> | |
1976 | SHMEM_EEE_LP_ADV_STATUS_SHIFT); | |
1977 | ||
1978 | /* SHMEM value is in 16u units --> Convert to 1u units. */ | |
1979 | edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; | |
1980 | ||
1981 | edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; | |
1982 | edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; | |
1983 | edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; | |
1984 | ||
1985 | return 0; | |
1986 | } | |
1987 | ||
1988 | static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) | |
1989 | { | |
1990 | struct bnx2x *bp = netdev_priv(dev); | |
1991 | u32 eee_cfg; | |
1992 | u32 advertised; | |
1993 | ||
1994 | if (IS_MF(bp)) | |
1995 | return 0; | |
1996 | ||
1997 | if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { | |
1998 | DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); | |
1999 | return -EOPNOTSUPP; | |
2000 | } | |
2001 | ||
08e9acc2 | 2002 | eee_cfg = bp->link_vars.eee_status; |
e9939c80 YM |
2003 | |
2004 | if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { | |
2005 | DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); | |
2006 | return -EOPNOTSUPP; | |
2007 | } | |
2008 | ||
2009 | advertised = bnx2x_adv_to_eee(edata->advertised, | |
2010 | SHMEM_EEE_ADV_STATUS_SHIFT); | |
2011 | if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { | |
2012 | DP(BNX2X_MSG_ETHTOOL, | |
efc7ce03 | 2013 | "Direct manipulation of EEE advertisement is not supported\n"); |
e9939c80 YM |
2014 | return -EINVAL; |
2015 | } | |
2016 | ||
2017 | if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { | |
2018 | DP(BNX2X_MSG_ETHTOOL, | |
2019 | "Maximal Tx Lpi timer supported is %x(u)\n", | |
2020 | EEE_MODE_TIMER_MASK); | |
2021 | return -EINVAL; | |
2022 | } | |
2023 | if (edata->tx_lpi_enabled && | |
2024 | (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { | |
2025 | DP(BNX2X_MSG_ETHTOOL, | |
2026 | "Minimal Tx Lpi timer supported is %d(u)\n", | |
2027 | EEE_MODE_NVRAM_AGGRESSIVE_TIME); | |
2028 | return -EINVAL; | |
2029 | } | |
2030 | ||
2031 | /* All is well; Apply changes*/ | |
2032 | if (edata->eee_enabled) | |
2033 | bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; | |
2034 | else | |
2035 | bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; | |
2036 | ||
2037 | if (edata->tx_lpi_enabled) | |
2038 | bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; | |
2039 | else | |
2040 | bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; | |
2041 | ||
2042 | bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; | |
2043 | bp->link_params.eee_mode |= (edata->tx_lpi_timer & | |
2044 | EEE_MODE_TIMER_MASK) | | |
2045 | EEE_MODE_OVERRIDE_NVRAM | | |
2046 | EEE_MODE_OUTPUT_TIME; | |
2047 | ||
16a5fd92 | 2048 | /* Restart link to propagate changes */ |
e9939c80 YM |
2049 | if (netif_running(dev)) { |
2050 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
5d07d868 | 2051 | bnx2x_force_link_reset(bp); |
e9939c80 YM |
2052 | bnx2x_link_set(bp); |
2053 | } | |
2054 | ||
2055 | return 0; | |
2056 | } | |
2057 | ||
619c5cb6 VZ |
2058 | enum { |
2059 | BNX2X_CHIP_E1_OFST = 0, | |
2060 | BNX2X_CHIP_E1H_OFST, | |
2061 | BNX2X_CHIP_E2_OFST, | |
2062 | BNX2X_CHIP_E3_OFST, | |
2063 | BNX2X_CHIP_E3B0_OFST, | |
2064 | BNX2X_CHIP_MAX_OFST | |
2065 | }; | |
2066 | ||
2067 | #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) | |
2068 | #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) | |
2069 | #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) | |
2070 | #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) | |
2071 | #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) | |
2072 | ||
2073 | #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) | |
2074 | #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) | |
2075 | ||
de0c62db DK |
2076 | static int bnx2x_test_registers(struct bnx2x *bp) |
2077 | { | |
2078 | int idx, i, rc = -ENODEV; | |
619c5cb6 | 2079 | u32 wr_val = 0, hw; |
de0c62db DK |
2080 | int port = BP_PORT(bp); |
2081 | static const struct { | |
619c5cb6 | 2082 | u32 hw; |
de0c62db DK |
2083 | u32 offset0; |
2084 | u32 offset1; | |
2085 | u32 mask; | |
2086 | } reg_tbl[] = { | |
619c5cb6 VZ |
2087 | /* 0 */ { BNX2X_CHIP_MASK_ALL, |
2088 | BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, | |
2089 | { BNX2X_CHIP_MASK_ALL, | |
2090 | DORQ_REG_DB_ADDR0, 4, 0xffffffff }, | |
2091 | { BNX2X_CHIP_MASK_E1X, | |
2092 | HC_REG_AGG_INT_0, 4, 0x000003ff }, | |
2093 | { BNX2X_CHIP_MASK_ALL, | |
2094 | PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, | |
2095 | { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, | |
2096 | PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, | |
2097 | { BNX2X_CHIP_MASK_E3B0, | |
2098 | PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, | |
2099 | { BNX2X_CHIP_MASK_ALL, | |
2100 | PRS_REG_CID_PORT_0, 4, 0x00ffffff }, | |
2101 | { BNX2X_CHIP_MASK_ALL, | |
2102 | PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, | |
2103 | { BNX2X_CHIP_MASK_ALL, | |
2104 | PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, | |
2105 | { BNX2X_CHIP_MASK_ALL, | |
2106 | PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, | |
2107 | /* 10 */ { BNX2X_CHIP_MASK_ALL, | |
2108 | PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, | |
2109 | { BNX2X_CHIP_MASK_ALL, | |
2110 | PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, | |
2111 | { BNX2X_CHIP_MASK_ALL, | |
2112 | QM_REG_CONNNUM_0, 4, 0x000fffff }, | |
2113 | { BNX2X_CHIP_MASK_ALL, | |
2114 | TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, | |
2115 | { BNX2X_CHIP_MASK_ALL, | |
2116 | SRC_REG_KEYRSS0_0, 40, 0xffffffff }, | |
2117 | { BNX2X_CHIP_MASK_ALL, | |
2118 | SRC_REG_KEYRSS0_7, 40, 0xffffffff }, | |
2119 | { BNX2X_CHIP_MASK_ALL, | |
2120 | XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, | |
2121 | { BNX2X_CHIP_MASK_ALL, | |
2122 | XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, | |
2123 | { BNX2X_CHIP_MASK_ALL, | |
2124 | XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, | |
2125 | { BNX2X_CHIP_MASK_ALL, | |
2126 | NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, | |
2127 | /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, | |
2128 | NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, | |
2129 | { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, | |
2130 | NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, | |
2131 | { BNX2X_CHIP_MASK_ALL, | |
2132 | NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, | |
2133 | { BNX2X_CHIP_MASK_ALL, | |
2134 | NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, | |
2135 | { BNX2X_CHIP_MASK_ALL, | |
2136 | NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, | |
2137 | { BNX2X_CHIP_MASK_ALL, | |
2138 | NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, | |
2139 | { BNX2X_CHIP_MASK_ALL, | |
2140 | NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, | |
2141 | { BNX2X_CHIP_MASK_ALL, | |
2142 | NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, | |
2143 | { BNX2X_CHIP_MASK_ALL, | |
2144 | NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, | |
2145 | { BNX2X_CHIP_MASK_ALL, | |
2146 | NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, | |
2147 | /* 30 */ { BNX2X_CHIP_MASK_ALL, | |
2148 | NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, | |
2149 | { BNX2X_CHIP_MASK_ALL, | |
2150 | NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, | |
2151 | { BNX2X_CHIP_MASK_ALL, | |
2152 | NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, | |
2153 | { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, | |
2154 | NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, | |
2155 | { BNX2X_CHIP_MASK_ALL, | |
2156 | NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, | |
2157 | { BNX2X_CHIP_MASK_ALL, | |
2158 | NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, | |
2159 | { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, | |
2160 | NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, | |
2161 | { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, | |
2162 | NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, | |
2163 | ||
2164 | { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } | |
de0c62db DK |
2165 | }; |
2166 | ||
3fb43eb2 | 2167 | if (!bnx2x_is_nvm_accessible(bp)) { |
51c1a580 MS |
2168 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
2169 | "cannot access eeprom when the interface is down\n"); | |
de0c62db | 2170 | return rc; |
51c1a580 | 2171 | } |
de0c62db | 2172 | |
619c5cb6 VZ |
2173 | if (CHIP_IS_E1(bp)) |
2174 | hw = BNX2X_CHIP_MASK_E1; | |
2175 | else if (CHIP_IS_E1H(bp)) | |
2176 | hw = BNX2X_CHIP_MASK_E1H; | |
2177 | else if (CHIP_IS_E2(bp)) | |
2178 | hw = BNX2X_CHIP_MASK_E2; | |
2179 | else if (CHIP_IS_E3B0(bp)) | |
2180 | hw = BNX2X_CHIP_MASK_E3B0; | |
2181 | else /* e3 A0 */ | |
2182 | hw = BNX2X_CHIP_MASK_E3; | |
2183 | ||
de0c62db | 2184 | /* Repeat the test twice: |
07ba6af4 MS |
2185 | * First by writing 0x00000000, second by writing 0xffffffff |
2186 | */ | |
de0c62db DK |
2187 | for (idx = 0; idx < 2; idx++) { |
2188 | ||
2189 | switch (idx) { | |
2190 | case 0: | |
2191 | wr_val = 0; | |
2192 | break; | |
2193 | case 1: | |
2194 | wr_val = 0xffffffff; | |
2195 | break; | |
2196 | } | |
2197 | ||
2198 | for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { | |
2199 | u32 offset, mask, save_val, val; | |
619c5cb6 | 2200 | if (!(hw & reg_tbl[i].hw)) |
f2e0899f | 2201 | continue; |
de0c62db DK |
2202 | |
2203 | offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; | |
2204 | mask = reg_tbl[i].mask; | |
2205 | ||
2206 | save_val = REG_RD(bp, offset); | |
2207 | ||
ec6ba945 | 2208 | REG_WR(bp, offset, wr_val & mask); |
f85582f8 | 2209 | |
de0c62db DK |
2210 | val = REG_RD(bp, offset); |
2211 | ||
2212 | /* Restore the original register's value */ | |
2213 | REG_WR(bp, offset, save_val); | |
2214 | ||
2215 | /* verify value is as expected */ | |
2216 | if ((val & mask) != (wr_val & mask)) { | |
51c1a580 | 2217 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
2218 | "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", |
2219 | offset, val, wr_val, mask); | |
2220 | goto test_reg_exit; | |
2221 | } | |
2222 | } | |
2223 | } | |
2224 | ||
2225 | rc = 0; | |
2226 | ||
2227 | test_reg_exit: | |
2228 | return rc; | |
2229 | } | |
2230 | ||
2231 | static int bnx2x_test_memory(struct bnx2x *bp) | |
2232 | { | |
2233 | int i, j, rc = -ENODEV; | |
619c5cb6 | 2234 | u32 val, index; |
de0c62db DK |
2235 | static const struct { |
2236 | u32 offset; | |
2237 | int size; | |
2238 | } mem_tbl[] = { | |
2239 | { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, | |
2240 | { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, | |
2241 | { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, | |
2242 | { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, | |
2243 | { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, | |
2244 | { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, | |
2245 | { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, | |
2246 | ||
2247 | { 0xffffffff, 0 } | |
2248 | }; | |
619c5cb6 | 2249 | |
de0c62db DK |
2250 | static const struct { |
2251 | char *name; | |
2252 | u32 offset; | |
619c5cb6 | 2253 | u32 hw_mask[BNX2X_CHIP_MAX_OFST]; |
de0c62db | 2254 | } prty_tbl[] = { |
619c5cb6 VZ |
2255 | { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, |
2256 | {0x3ffc0, 0, 0, 0} }, | |
2257 | { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, | |
2258 | {0x2, 0x2, 0, 0} }, | |
2259 | { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, | |
2260 | {0, 0, 0, 0} }, | |
2261 | { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, | |
2262 | {0x3ffc0, 0, 0, 0} }, | |
2263 | { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, | |
2264 | {0x3ffc0, 0, 0, 0} }, | |
2265 | { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, | |
2266 | {0x3ffc1, 0, 0, 0} }, | |
2267 | ||
2268 | { NULL, 0xffffffff, {0, 0, 0, 0} } | |
de0c62db DK |
2269 | }; |
2270 | ||
3fb43eb2 | 2271 | if (!bnx2x_is_nvm_accessible(bp)) { |
51c1a580 MS |
2272 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
2273 | "cannot access eeprom when the interface is down\n"); | |
de0c62db | 2274 | return rc; |
51c1a580 | 2275 | } |
de0c62db | 2276 | |
619c5cb6 VZ |
2277 | if (CHIP_IS_E1(bp)) |
2278 | index = BNX2X_CHIP_E1_OFST; | |
2279 | else if (CHIP_IS_E1H(bp)) | |
2280 | index = BNX2X_CHIP_E1H_OFST; | |
2281 | else if (CHIP_IS_E2(bp)) | |
2282 | index = BNX2X_CHIP_E2_OFST; | |
2283 | else /* e3 */ | |
2284 | index = BNX2X_CHIP_E3_OFST; | |
2285 | ||
f2e0899f DK |
2286 | /* pre-Check the parity status */ |
2287 | for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { | |
2288 | val = REG_RD(bp, prty_tbl[i].offset); | |
619c5cb6 | 2289 | if (val & ~(prty_tbl[i].hw_mask[index])) { |
51c1a580 | 2290 | DP(BNX2X_MSG_ETHTOOL, |
f2e0899f DK |
2291 | "%s is 0x%x\n", prty_tbl[i].name, val); |
2292 | goto test_mem_exit; | |
2293 | } | |
2294 | } | |
2295 | ||
de0c62db DK |
2296 | /* Go through all the memories */ |
2297 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) | |
2298 | for (j = 0; j < mem_tbl[i].size; j++) | |
2299 | REG_RD(bp, mem_tbl[i].offset + j*4); | |
2300 | ||
2301 | /* Check the parity status */ | |
2302 | for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { | |
2303 | val = REG_RD(bp, prty_tbl[i].offset); | |
619c5cb6 | 2304 | if (val & ~(prty_tbl[i].hw_mask[index])) { |
51c1a580 | 2305 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
2306 | "%s is 0x%x\n", prty_tbl[i].name, val); |
2307 | goto test_mem_exit; | |
2308 | } | |
2309 | } | |
2310 | ||
2311 | rc = 0; | |
2312 | ||
2313 | test_mem_exit: | |
2314 | return rc; | |
2315 | } | |
2316 | ||
a22f0788 | 2317 | static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) |
de0c62db | 2318 | { |
f2e0899f | 2319 | int cnt = 1400; |
de0c62db | 2320 | |
619c5cb6 | 2321 | if (link_up) { |
a22f0788 | 2322 | while (bnx2x_link_test(bp, is_serdes) && cnt--) |
619c5cb6 VZ |
2323 | msleep(20); |
2324 | ||
2325 | if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) | |
51c1a580 | 2326 | DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); |
8970b2e4 MS |
2327 | |
2328 | cnt = 1400; | |
2329 | while (!bp->link_vars.link_up && cnt--) | |
2330 | msleep(20); | |
2331 | ||
2332 | if (cnt <= 0 && !bp->link_vars.link_up) | |
2333 | DP(BNX2X_MSG_ETHTOOL, | |
2334 | "Timeout waiting for link init\n"); | |
619c5cb6 | 2335 | } |
de0c62db DK |
2336 | } |
2337 | ||
619c5cb6 | 2338 | static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) |
de0c62db DK |
2339 | { |
2340 | unsigned int pkt_size, num_pkts, i; | |
2341 | struct sk_buff *skb; | |
2342 | unsigned char *packet; | |
2343 | struct bnx2x_fastpath *fp_rx = &bp->fp[0]; | |
2344 | struct bnx2x_fastpath *fp_tx = &bp->fp[0]; | |
65565884 | 2345 | struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; |
de0c62db DK |
2346 | u16 tx_start_idx, tx_idx; |
2347 | u16 rx_start_idx, rx_idx; | |
b0700b1e | 2348 | u16 pkt_prod, bd_prod; |
de0c62db DK |
2349 | struct sw_tx_bd *tx_buf; |
2350 | struct eth_tx_start_bd *tx_start_bd; | |
de0c62db DK |
2351 | dma_addr_t mapping; |
2352 | union eth_rx_cqe *cqe; | |
619c5cb6 | 2353 | u8 cqe_fp_flags, cqe_fp_type; |
de0c62db DK |
2354 | struct sw_rx_bd *rx_buf; |
2355 | u16 len; | |
2356 | int rc = -ENODEV; | |
e52fcb24 | 2357 | u8 *data; |
8970b2e4 MS |
2358 | struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, |
2359 | txdata->txq_index); | |
de0c62db DK |
2360 | |
2361 | /* check the loopback mode */ | |
2362 | switch (loopback_mode) { | |
2363 | case BNX2X_PHY_LOOPBACK: | |
8970b2e4 MS |
2364 | if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { |
2365 | DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); | |
de0c62db | 2366 | return -EINVAL; |
8970b2e4 | 2367 | } |
de0c62db DK |
2368 | break; |
2369 | case BNX2X_MAC_LOOPBACK: | |
32911333 YR |
2370 | if (CHIP_IS_E3(bp)) { |
2371 | int cfg_idx = bnx2x_get_link_cfg_idx(bp); | |
2372 | if (bp->port.supported[cfg_idx] & | |
2373 | (SUPPORTED_10000baseT_Full | | |
2374 | SUPPORTED_20000baseMLD2_Full | | |
2375 | SUPPORTED_20000baseKR2_Full)) | |
2376 | bp->link_params.loopback_mode = LOOPBACK_XMAC; | |
2377 | else | |
2378 | bp->link_params.loopback_mode = LOOPBACK_UMAC; | |
2379 | } else | |
2380 | bp->link_params.loopback_mode = LOOPBACK_BMAC; | |
2381 | ||
de0c62db DK |
2382 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
2383 | break; | |
8970b2e4 MS |
2384 | case BNX2X_EXT_LOOPBACK: |
2385 | if (bp->link_params.loopback_mode != LOOPBACK_EXT) { | |
2386 | DP(BNX2X_MSG_ETHTOOL, | |
2387 | "Can't configure external loopback\n"); | |
2388 | return -EINVAL; | |
2389 | } | |
2390 | break; | |
de0c62db | 2391 | default: |
51c1a580 | 2392 | DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); |
de0c62db DK |
2393 | return -EINVAL; |
2394 | } | |
2395 | ||
2396 | /* prepare the loopback packet */ | |
2397 | pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? | |
2398 | bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); | |
a8c94b91 | 2399 | skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); |
de0c62db | 2400 | if (!skb) { |
51c1a580 | 2401 | DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); |
de0c62db DK |
2402 | rc = -ENOMEM; |
2403 | goto test_loopback_exit; | |
2404 | } | |
2405 | packet = skb_put(skb, pkt_size); | |
2406 | memcpy(packet, bp->dev->dev_addr, ETH_ALEN); | |
2407 | memset(packet + ETH_ALEN, 0, ETH_ALEN); | |
2408 | memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); | |
2409 | for (i = ETH_HLEN; i < pkt_size; i++) | |
2410 | packet[i] = (unsigned char) (i & 0xff); | |
619c5cb6 VZ |
2411 | mapping = dma_map_single(&bp->pdev->dev, skb->data, |
2412 | skb_headlen(skb), DMA_TO_DEVICE); | |
2413 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
2414 | rc = -ENOMEM; | |
2415 | dev_kfree_skb(skb); | |
51c1a580 | 2416 | DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); |
619c5cb6 VZ |
2417 | goto test_loopback_exit; |
2418 | } | |
de0c62db DK |
2419 | |
2420 | /* send the loopback packet */ | |
2421 | num_pkts = 0; | |
6383c0b3 | 2422 | tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); |
de0c62db DK |
2423 | rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); |
2424 | ||
73dbb5e1 DK |
2425 | netdev_tx_sent_queue(txq, skb->len); |
2426 | ||
6383c0b3 AE |
2427 | pkt_prod = txdata->tx_pkt_prod++; |
2428 | tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; | |
2429 | tx_buf->first_bd = txdata->tx_bd_prod; | |
de0c62db DK |
2430 | tx_buf->skb = skb; |
2431 | tx_buf->flags = 0; | |
2432 | ||
6383c0b3 AE |
2433 | bd_prod = TX_BD(txdata->tx_bd_prod); |
2434 | tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; | |
de0c62db DK |
2435 | tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); |
2436 | tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
2437 | tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ | |
2438 | tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); | |
523224a3 | 2439 | tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); |
de0c62db | 2440 | tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; |
523224a3 DK |
2441 | SET_FLAG(tx_start_bd->general_data, |
2442 | ETH_TX_START_BD_HDR_NBDS, | |
2443 | 1); | |
96bed4b9 YM |
2444 | SET_FLAG(tx_start_bd->general_data, |
2445 | ETH_TX_START_BD_PARSE_NBDS, | |
2446 | 0); | |
de0c62db DK |
2447 | |
2448 | /* turn on parsing and get a BD */ | |
2449 | bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); | |
f85582f8 | 2450 | |
96bed4b9 YM |
2451 | if (CHIP_IS_E1x(bp)) { |
2452 | u16 global_data = 0; | |
2453 | struct eth_tx_parse_bd_e1x *pbd_e1x = | |
2454 | &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; | |
2455 | memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); | |
2456 | SET_FLAG(global_data, | |
2457 | ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); | |
2458 | pbd_e1x->global_data = cpu_to_le16(global_data); | |
2459 | } else { | |
2460 | u32 parsing_data = 0; | |
2461 | struct eth_tx_parse_bd_e2 *pbd_e2 = | |
2462 | &txdata->tx_desc_ring[bd_prod].parse_bd_e2; | |
2463 | memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); | |
2464 | SET_FLAG(parsing_data, | |
2465 | ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); | |
2466 | pbd_e2->parsing_data = cpu_to_le32(parsing_data); | |
2467 | } | |
de0c62db DK |
2468 | wmb(); |
2469 | ||
6383c0b3 | 2470 | txdata->tx_db.data.prod += 2; |
de0c62db | 2471 | barrier(); |
6383c0b3 | 2472 | DOORBELL(bp, txdata->cid, txdata->tx_db.raw); |
de0c62db DK |
2473 | |
2474 | mmiowb(); | |
619c5cb6 | 2475 | barrier(); |
de0c62db DK |
2476 | |
2477 | num_pkts++; | |
6383c0b3 | 2478 | txdata->tx_bd_prod += 2; /* start + pbd */ |
de0c62db DK |
2479 | |
2480 | udelay(100); | |
2481 | ||
6383c0b3 | 2482 | tx_idx = le16_to_cpu(*txdata->tx_cons_sb); |
de0c62db DK |
2483 | if (tx_idx != tx_start_idx + num_pkts) |
2484 | goto test_loopback_exit; | |
2485 | ||
f2e0899f DK |
2486 | /* Unlike HC IGU won't generate an interrupt for status block |
2487 | * updates that have been performed while interrupts were | |
2488 | * disabled. | |
2489 | */ | |
e1210d12 ED |
2490 | if (bp->common.int_block == INT_BLOCK_IGU) { |
2491 | /* Disable local BHes to prevent a dead-lock situation between | |
2492 | * sch_direct_xmit() and bnx2x_run_loopback() (calling | |
2493 | * bnx2x_tx_int()), as both are taking netif_tx_lock(). | |
2494 | */ | |
2495 | local_bh_disable(); | |
6383c0b3 | 2496 | bnx2x_tx_int(bp, txdata); |
e1210d12 ED |
2497 | local_bh_enable(); |
2498 | } | |
f2e0899f | 2499 | |
de0c62db DK |
2500 | rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); |
2501 | if (rx_idx != rx_start_idx + num_pkts) | |
2502 | goto test_loopback_exit; | |
2503 | ||
b0700b1e | 2504 | cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; |
de0c62db | 2505 | cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; |
619c5cb6 VZ |
2506 | cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; |
2507 | if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) | |
de0c62db DK |
2508 | goto test_loopback_rx_exit; |
2509 | ||
621b4d66 | 2510 | len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); |
de0c62db DK |
2511 | if (len != pkt_size) |
2512 | goto test_loopback_rx_exit; | |
2513 | ||
2514 | rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; | |
9924cafc | 2515 | dma_sync_single_for_cpu(&bp->pdev->dev, |
619c5cb6 VZ |
2516 | dma_unmap_addr(rx_buf, mapping), |
2517 | fp_rx->rx_buf_size, DMA_FROM_DEVICE); | |
e52fcb24 | 2518 | data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; |
de0c62db | 2519 | for (i = ETH_HLEN; i < pkt_size; i++) |
e52fcb24 | 2520 | if (*(data + i) != (unsigned char) (i & 0xff)) |
de0c62db DK |
2521 | goto test_loopback_rx_exit; |
2522 | ||
2523 | rc = 0; | |
2524 | ||
2525 | test_loopback_rx_exit: | |
2526 | ||
2527 | fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); | |
2528 | fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); | |
2529 | fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); | |
2530 | fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); | |
2531 | ||
2532 | /* Update producers */ | |
2533 | bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, | |
2534 | fp_rx->rx_sge_prod); | |
2535 | ||
2536 | test_loopback_exit: | |
2537 | bp->link_params.loopback_mode = LOOPBACK_NONE; | |
2538 | ||
2539 | return rc; | |
2540 | } | |
2541 | ||
619c5cb6 | 2542 | static int bnx2x_test_loopback(struct bnx2x *bp) |
de0c62db DK |
2543 | { |
2544 | int rc = 0, res; | |
2545 | ||
2546 | if (BP_NOMCP(bp)) | |
2547 | return rc; | |
2548 | ||
2549 | if (!netif_running(bp->dev)) | |
2550 | return BNX2X_LOOPBACK_FAILED; | |
2551 | ||
2552 | bnx2x_netif_stop(bp, 1); | |
2553 | bnx2x_acquire_phy_lock(bp); | |
2554 | ||
619c5cb6 | 2555 | res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); |
de0c62db | 2556 | if (res) { |
51c1a580 | 2557 | DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); |
de0c62db DK |
2558 | rc |= BNX2X_PHY_LOOPBACK_FAILED; |
2559 | } | |
2560 | ||
619c5cb6 | 2561 | res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); |
de0c62db | 2562 | if (res) { |
51c1a580 | 2563 | DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); |
de0c62db DK |
2564 | rc |= BNX2X_MAC_LOOPBACK_FAILED; |
2565 | } | |
2566 | ||
2567 | bnx2x_release_phy_lock(bp); | |
2568 | bnx2x_netif_start(bp); | |
2569 | ||
2570 | return rc; | |
2571 | } | |
2572 | ||
8970b2e4 MS |
2573 | static int bnx2x_test_ext_loopback(struct bnx2x *bp) |
2574 | { | |
2575 | int rc; | |
2576 | u8 is_serdes = | |
2577 | (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; | |
2578 | ||
2579 | if (BP_NOMCP(bp)) | |
2580 | return -ENODEV; | |
2581 | ||
2582 | if (!netif_running(bp->dev)) | |
2583 | return BNX2X_EXT_LOOPBACK_FAILED; | |
2584 | ||
5d07d868 | 2585 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); |
8970b2e4 MS |
2586 | rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); |
2587 | if (rc) { | |
2588 | DP(BNX2X_MSG_ETHTOOL, | |
2589 | "Can't perform self-test, nic_load (for external lb) failed\n"); | |
2590 | return -ENODEV; | |
2591 | } | |
2592 | bnx2x_wait_for_link(bp, 1, is_serdes); | |
2593 | ||
2594 | bnx2x_netif_stop(bp, 1); | |
2595 | ||
2596 | rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); | |
2597 | if (rc) | |
2598 | DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); | |
2599 | ||
2600 | bnx2x_netif_start(bp); | |
2601 | ||
2602 | return rc; | |
2603 | } | |
2604 | ||
edb944d2 DK |
2605 | struct code_entry { |
2606 | u32 sram_start_addr; | |
2607 | u32 code_attribute; | |
2608 | #define CODE_IMAGE_TYPE_MASK 0xf0800003 | |
2609 | #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 | |
2610 | #define CODE_IMAGE_LENGTH_MASK 0x007ffffc | |
2611 | #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 | |
2612 | u32 nvm_start_addr; | |
2613 | }; | |
2614 | ||
2615 | #define CODE_ENTRY_MAX 16 | |
2616 | #define CODE_ENTRY_EXTENDED_DIR_IDX 15 | |
2617 | #define MAX_IMAGES_IN_EXTENDED_DIR 64 | |
2618 | #define NVRAM_DIR_OFFSET 0x14 | |
2619 | ||
2620 | #define EXTENDED_DIR_EXISTS(code) \ | |
2621 | ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ | |
2622 | (code & CODE_IMAGE_LENGTH_MASK) != 0) | |
2623 | ||
de0c62db | 2624 | #define CRC32_RESIDUAL 0xdebb20e3 |
edb944d2 DK |
2625 | #define CRC_BUFF_SIZE 256 |
2626 | ||
2627 | static int bnx2x_nvram_crc(struct bnx2x *bp, | |
2628 | int offset, | |
2629 | int size, | |
2630 | u8 *buff) | |
2631 | { | |
2632 | u32 crc = ~0; | |
2633 | int rc = 0, done = 0; | |
2634 | ||
2635 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
2636 | "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); | |
2637 | ||
2638 | while (done < size) { | |
2639 | int count = min_t(int, size - done, CRC_BUFF_SIZE); | |
2640 | ||
2641 | rc = bnx2x_nvram_read(bp, offset + done, buff, count); | |
2642 | ||
2643 | if (rc) | |
2644 | return rc; | |
2645 | ||
2646 | crc = crc32_le(crc, buff, count); | |
2647 | done += count; | |
2648 | } | |
2649 | ||
2650 | if (crc != CRC32_RESIDUAL) | |
2651 | rc = -EINVAL; | |
2652 | ||
2653 | return rc; | |
2654 | } | |
2655 | ||
2656 | static int bnx2x_test_nvram_dir(struct bnx2x *bp, | |
2657 | struct code_entry *entry, | |
2658 | u8 *buff) | |
2659 | { | |
2660 | size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; | |
2661 | u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; | |
2662 | int rc; | |
2663 | ||
2664 | /* Zero-length images and AFEX profiles do not have CRC */ | |
2665 | if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) | |
2666 | return 0; | |
2667 | ||
2668 | rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); | |
2669 | if (rc) | |
2670 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
2671 | "image %x has failed crc test (rc %d)\n", type, rc); | |
2672 | ||
2673 | return rc; | |
2674 | } | |
2675 | ||
2676 | static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) | |
2677 | { | |
2678 | int rc; | |
2679 | struct code_entry entry; | |
2680 | ||
2681 | rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); | |
2682 | if (rc) | |
2683 | return rc; | |
2684 | ||
2685 | return bnx2x_test_nvram_dir(bp, &entry, buff); | |
2686 | } | |
2687 | ||
2688 | static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) | |
2689 | { | |
2690 | u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; | |
2691 | struct code_entry entry; | |
2692 | int i; | |
2693 | ||
2694 | rc = bnx2x_nvram_read32(bp, | |
2695 | dir_offset + | |
2696 | sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, | |
2697 | (u32 *)&entry, sizeof(entry)); | |
2698 | if (rc) | |
2699 | return rc; | |
2700 | ||
2701 | if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) | |
2702 | return 0; | |
2703 | ||
2704 | rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, | |
2705 | &cnt, sizeof(u32)); | |
2706 | if (rc) | |
2707 | return rc; | |
2708 | ||
2709 | dir_offset = entry.nvm_start_addr + 8; | |
2710 | ||
2711 | for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { | |
2712 | rc = bnx2x_test_dir_entry(bp, dir_offset + | |
2713 | sizeof(struct code_entry) * i, | |
2714 | buff); | |
2715 | if (rc) | |
2716 | return rc; | |
2717 | } | |
2718 | ||
2719 | return 0; | |
2720 | } | |
2721 | ||
2722 | static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) | |
2723 | { | |
2724 | u32 rc, dir_offset = NVRAM_DIR_OFFSET; | |
2725 | int i; | |
2726 | ||
2727 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); | |
2728 | ||
2729 | for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { | |
2730 | rc = bnx2x_test_dir_entry(bp, dir_offset + | |
2731 | sizeof(struct code_entry) * i, | |
2732 | buff); | |
2733 | if (rc) | |
2734 | return rc; | |
2735 | } | |
2736 | ||
2737 | return bnx2x_test_nvram_ext_dirs(bp, buff); | |
2738 | } | |
2739 | ||
2740 | struct crc_pair { | |
2741 | int offset; | |
2742 | int size; | |
2743 | }; | |
2744 | ||
2745 | static int bnx2x_test_nvram_tbl(struct bnx2x *bp, | |
2746 | const struct crc_pair *nvram_tbl, u8 *buf) | |
2747 | { | |
2748 | int i; | |
2749 | ||
2750 | for (i = 0; nvram_tbl[i].size; i++) { | |
2751 | int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, | |
2752 | nvram_tbl[i].size, buf); | |
2753 | if (rc) { | |
2754 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
2755 | "nvram_tbl[%d] has failed crc test (rc %d)\n", | |
2756 | i, rc); | |
2757 | return rc; | |
2758 | } | |
2759 | } | |
2760 | ||
2761 | return 0; | |
2762 | } | |
de0c62db DK |
2763 | |
2764 | static int bnx2x_test_nvram(struct bnx2x *bp) | |
2765 | { | |
edb944d2 | 2766 | const struct crc_pair nvram_tbl[] = { |
de0c62db DK |
2767 | { 0, 0x14 }, /* bootstrap */ |
2768 | { 0x14, 0xec }, /* dir */ | |
2769 | { 0x100, 0x350 }, /* manuf_info */ | |
2770 | { 0x450, 0xf0 }, /* feature_info */ | |
2771 | { 0x640, 0x64 }, /* upgrade_key_info */ | |
de0c62db | 2772 | { 0x708, 0x70 }, /* manuf_key_info */ |
de0c62db DK |
2773 | { 0, 0 } |
2774 | }; | |
edb944d2 DK |
2775 | const struct crc_pair nvram_tbl2[] = { |
2776 | { 0x7e8, 0x350 }, /* manuf_info2 */ | |
2777 | { 0xb38, 0xf0 }, /* feature_info */ | |
2778 | { 0, 0 } | |
2779 | }; | |
2780 | ||
85640952 | 2781 | u8 *buf; |
edb944d2 DK |
2782 | int rc; |
2783 | u32 magic; | |
de0c62db DK |
2784 | |
2785 | if (BP_NOMCP(bp)) | |
2786 | return 0; | |
2787 | ||
edb944d2 | 2788 | buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); |
afa13b4b | 2789 | if (!buf) { |
51c1a580 | 2790 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); |
afa13b4b MY |
2791 | rc = -ENOMEM; |
2792 | goto test_nvram_exit; | |
2793 | } | |
afa13b4b | 2794 | |
85640952 | 2795 | rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); |
de0c62db | 2796 | if (rc) { |
51c1a580 MS |
2797 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
2798 | "magic value read (rc %d)\n", rc); | |
de0c62db DK |
2799 | goto test_nvram_exit; |
2800 | } | |
2801 | ||
de0c62db | 2802 | if (magic != 0x669955aa) { |
51c1a580 MS |
2803 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
2804 | "wrong magic value (0x%08x)\n", magic); | |
de0c62db DK |
2805 | rc = -ENODEV; |
2806 | goto test_nvram_exit; | |
2807 | } | |
2808 | ||
edb944d2 DK |
2809 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); |
2810 | rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); | |
2811 | if (rc) | |
2812 | goto test_nvram_exit; | |
de0c62db | 2813 | |
edb944d2 DK |
2814 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { |
2815 | u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & | |
2816 | SHARED_HW_CFG_HIDE_PORT1; | |
de0c62db | 2817 | |
edb944d2 | 2818 | if (!hide) { |
51c1a580 | 2819 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
edb944d2 DK |
2820 | "Port 1 CRC test-set\n"); |
2821 | rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); | |
2822 | if (rc) | |
2823 | goto test_nvram_exit; | |
de0c62db DK |
2824 | } |
2825 | } | |
2826 | ||
edb944d2 DK |
2827 | rc = bnx2x_test_nvram_dirs(bp, buf); |
2828 | ||
de0c62db | 2829 | test_nvram_exit: |
afa13b4b | 2830 | kfree(buf); |
de0c62db DK |
2831 | return rc; |
2832 | } | |
2833 | ||
619c5cb6 | 2834 | /* Send an EMPTY ramrod on the first queue */ |
de0c62db DK |
2835 | static int bnx2x_test_intr(struct bnx2x *bp) |
2836 | { | |
3b603066 | 2837 | struct bnx2x_queue_state_params params = {NULL}; |
de0c62db | 2838 | |
51c1a580 MS |
2839 | if (!netif_running(bp->dev)) { |
2840 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
2841 | "cannot access eeprom when the interface is down\n"); | |
de0c62db | 2842 | return -ENODEV; |
51c1a580 | 2843 | } |
de0c62db | 2844 | |
15192a8c | 2845 | params.q_obj = &bp->sp_objs->q_obj; |
619c5cb6 | 2846 | params.cmd = BNX2X_Q_CMD_EMPTY; |
de0c62db | 2847 | |
619c5cb6 VZ |
2848 | __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); |
2849 | ||
2850 | return bnx2x_queue_state_change(bp, ¶ms); | |
de0c62db DK |
2851 | } |
2852 | ||
2853 | static void bnx2x_self_test(struct net_device *dev, | |
2854 | struct ethtool_test *etest, u64 *buf) | |
2855 | { | |
2856 | struct bnx2x *bp = netdev_priv(dev); | |
a336ca7c YR |
2857 | u8 is_serdes, link_up; |
2858 | int rc, cnt = 0; | |
cf2c1df6 | 2859 | |
de0c62db | 2860 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 MS |
2861 | netdev_err(bp->dev, |
2862 | "Handling parity error recovery. Try again later\n"); | |
de0c62db DK |
2863 | etest->flags |= ETH_TEST_FL_FAILED; |
2864 | return; | |
2865 | } | |
2de67439 | 2866 | |
8970b2e4 MS |
2867 | DP(BNX2X_MSG_ETHTOOL, |
2868 | "Self-test command parameters: offline = %d, external_lb = %d\n", | |
2869 | (etest->flags & ETH_TEST_FL_OFFLINE), | |
2870 | (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); | |
de0c62db | 2871 | |
cf2c1df6 | 2872 | memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); |
de0c62db | 2873 | |
bd8e012b YM |
2874 | if (bnx2x_test_nvram(bp) != 0) { |
2875 | if (!IS_MF(bp)) | |
2876 | buf[4] = 1; | |
2877 | else | |
2878 | buf[0] = 1; | |
2879 | etest->flags |= ETH_TEST_FL_FAILED; | |
2880 | } | |
2881 | ||
cf2c1df6 | 2882 | if (!netif_running(dev)) { |
bd8e012b | 2883 | DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); |
de0c62db | 2884 | return; |
cf2c1df6 | 2885 | } |
de0c62db | 2886 | |
a22f0788 | 2887 | is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; |
a336ca7c | 2888 | link_up = bp->link_vars.link_up; |
cf2c1df6 MS |
2889 | /* offline tests are not supported in MF mode */ |
2890 | if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { | |
de0c62db DK |
2891 | int port = BP_PORT(bp); |
2892 | u32 val; | |
de0c62db DK |
2893 | |
2894 | /* save current value of input enable for TX port IF */ | |
2895 | val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); | |
2896 | /* disable input for TX port IF */ | |
2897 | REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); | |
2898 | ||
5d07d868 | 2899 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); |
cf2c1df6 MS |
2900 | rc = bnx2x_nic_load(bp, LOAD_DIAG); |
2901 | if (rc) { | |
2902 | etest->flags |= ETH_TEST_FL_FAILED; | |
2903 | DP(BNX2X_MSG_ETHTOOL, | |
2904 | "Can't perform self-test, nic_load (for offline) failed\n"); | |
2905 | return; | |
2906 | } | |
2907 | ||
de0c62db | 2908 | /* wait until link state is restored */ |
619c5cb6 | 2909 | bnx2x_wait_for_link(bp, 1, is_serdes); |
de0c62db DK |
2910 | |
2911 | if (bnx2x_test_registers(bp) != 0) { | |
2912 | buf[0] = 1; | |
2913 | etest->flags |= ETH_TEST_FL_FAILED; | |
2914 | } | |
2915 | if (bnx2x_test_memory(bp) != 0) { | |
2916 | buf[1] = 1; | |
2917 | etest->flags |= ETH_TEST_FL_FAILED; | |
2918 | } | |
f85582f8 | 2919 | |
8970b2e4 | 2920 | buf[2] = bnx2x_test_loopback(bp); /* internal LB */ |
de0c62db DK |
2921 | if (buf[2] != 0) |
2922 | etest->flags |= ETH_TEST_FL_FAILED; | |
2923 | ||
8970b2e4 MS |
2924 | if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { |
2925 | buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ | |
2926 | if (buf[3] != 0) | |
2927 | etest->flags |= ETH_TEST_FL_FAILED; | |
2928 | etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; | |
2929 | } | |
2930 | ||
5d07d868 | 2931 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); |
de0c62db DK |
2932 | |
2933 | /* restore input for TX port IF */ | |
2934 | REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); | |
cf2c1df6 MS |
2935 | rc = bnx2x_nic_load(bp, LOAD_NORMAL); |
2936 | if (rc) { | |
2937 | etest->flags |= ETH_TEST_FL_FAILED; | |
2938 | DP(BNX2X_MSG_ETHTOOL, | |
2939 | "Can't perform self-test, nic_load (for online) failed\n"); | |
2940 | return; | |
2941 | } | |
de0c62db | 2942 | /* wait until link state is restored */ |
a22f0788 | 2943 | bnx2x_wait_for_link(bp, link_up, is_serdes); |
de0c62db | 2944 | } |
bd8e012b | 2945 | |
de0c62db | 2946 | if (bnx2x_test_intr(bp) != 0) { |
cf2c1df6 MS |
2947 | if (!IS_MF(bp)) |
2948 | buf[5] = 1; | |
2949 | else | |
2950 | buf[1] = 1; | |
de0c62db DK |
2951 | etest->flags |= ETH_TEST_FL_FAILED; |
2952 | } | |
633ac363 | 2953 | |
a336ca7c YR |
2954 | if (link_up) { |
2955 | cnt = 100; | |
2956 | while (bnx2x_link_test(bp, is_serdes) && --cnt) | |
2957 | msleep(20); | |
2958 | } | |
2959 | ||
2960 | if (!cnt) { | |
cf2c1df6 MS |
2961 | if (!IS_MF(bp)) |
2962 | buf[6] = 1; | |
2963 | else | |
2964 | buf[2] = 1; | |
633ac363 DK |
2965 | etest->flags |= ETH_TEST_FL_FAILED; |
2966 | } | |
de0c62db DK |
2967 | } |
2968 | ||
de0c62db DK |
2969 | #define IS_PORT_STAT(i) \ |
2970 | ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) | |
2971 | #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) | |
d8361051 YM |
2972 | #define HIDE_PORT_STAT(bp) \ |
2973 | ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \ | |
2974 | IS_VF(bp)) | |
de0c62db | 2975 | |
619c5cb6 VZ |
2976 | /* ethtool statistics are displayed for all regular ethernet queues and the |
2977 | * fcoe L2 queue if not disabled | |
2978 | */ | |
1191cb83 | 2979 | static int bnx2x_num_stat_queues(struct bnx2x *bp) |
619c5cb6 VZ |
2980 | { |
2981 | return BNX2X_NUM_ETH_QUEUES(bp); | |
2982 | } | |
2983 | ||
de0c62db DK |
2984 | static int bnx2x_get_sset_count(struct net_device *dev, int stringset) |
2985 | { | |
2986 | struct bnx2x *bp = netdev_priv(dev); | |
3521b419 | 2987 | int i, num_strings = 0; |
de0c62db DK |
2988 | |
2989 | switch (stringset) { | |
2990 | case ETH_SS_STATS: | |
2991 | if (is_multi(bp)) { | |
3521b419 YM |
2992 | num_strings = bnx2x_num_stat_queues(bp) * |
2993 | BNX2X_NUM_Q_STATS; | |
d5e83632 | 2994 | } else |
3521b419 | 2995 | num_strings = 0; |
d8361051 | 2996 | if (HIDE_PORT_STAT(bp)) { |
d5e83632 YM |
2997 | for (i = 0; i < BNX2X_NUM_STATS; i++) |
2998 | if (IS_FUNC_STAT(i)) | |
3521b419 | 2999 | num_strings++; |
d5e83632 | 3000 | } else |
3521b419 | 3001 | num_strings += BNX2X_NUM_STATS; |
d5e83632 | 3002 | |
3521b419 | 3003 | return num_strings; |
de0c62db DK |
3004 | |
3005 | case ETH_SS_TEST: | |
cf2c1df6 | 3006 | return BNX2X_NUM_TESTS(bp); |
de0c62db | 3007 | |
3521b419 YM |
3008 | case ETH_SS_PRIV_FLAGS: |
3009 | return BNX2X_PRI_FLAG_LEN; | |
3010 | ||
de0c62db DK |
3011 | default: |
3012 | return -EINVAL; | |
3013 | } | |
3014 | } | |
3015 | ||
3521b419 YM |
3016 | static u32 bnx2x_get_private_flags(struct net_device *dev) |
3017 | { | |
3018 | struct bnx2x *bp = netdev_priv(dev); | |
3019 | u32 flags = 0; | |
3020 | ||
3021 | flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; | |
3022 | flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; | |
3023 | flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; | |
3024 | ||
3025 | return flags; | |
3026 | } | |
3027 | ||
de0c62db DK |
3028 | static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
3029 | { | |
3030 | struct bnx2x *bp = netdev_priv(dev); | |
5889335c | 3031 | int i, j, k, start; |
ec6ba945 | 3032 | char queue_name[MAX_QUEUE_NAME_LEN+1]; |
de0c62db DK |
3033 | |
3034 | switch (stringset) { | |
3035 | case ETH_SS_STATS: | |
d5e83632 | 3036 | k = 0; |
de0c62db | 3037 | if (is_multi(bp)) { |
619c5cb6 | 3038 | for_each_eth_queue(bp, i) { |
ec6ba945 | 3039 | memset(queue_name, 0, sizeof(queue_name)); |
619c5cb6 | 3040 | sprintf(queue_name, "%d", i); |
de0c62db | 3041 | for (j = 0; j < BNX2X_NUM_Q_STATS; j++) |
ec6ba945 VZ |
3042 | snprintf(buf + (k + j)*ETH_GSTRING_LEN, |
3043 | ETH_GSTRING_LEN, | |
3044 | bnx2x_q_stats_arr[j].string, | |
3045 | queue_name); | |
de0c62db DK |
3046 | k += BNX2X_NUM_Q_STATS; |
3047 | } | |
de0c62db | 3048 | } |
d5e83632 | 3049 | |
d5e83632 | 3050 | for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { |
d8361051 | 3051 | if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) |
d5e83632 YM |
3052 | continue; |
3053 | strcpy(buf + (k + j)*ETH_GSTRING_LEN, | |
3054 | bnx2x_stats_arr[i].string); | |
3055 | j++; | |
3056 | } | |
3057 | ||
de0c62db DK |
3058 | break; |
3059 | ||
3060 | case ETH_SS_TEST: | |
cf2c1df6 MS |
3061 | /* First 4 tests cannot be done in MF mode */ |
3062 | if (!IS_MF(bp)) | |
3063 | start = 0; | |
3064 | else | |
3065 | start = 4; | |
5889335c MS |
3066 | memcpy(buf, bnx2x_tests_str_arr + start, |
3067 | ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); | |
3521b419 YM |
3068 | break; |
3069 | ||
3070 | case ETH_SS_PRIV_FLAGS: | |
3071 | memcpy(buf, bnx2x_private_arr, | |
3072 | ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); | |
3073 | break; | |
de0c62db DK |
3074 | } |
3075 | } | |
3076 | ||
3077 | static void bnx2x_get_ethtool_stats(struct net_device *dev, | |
3078 | struct ethtool_stats *stats, u64 *buf) | |
3079 | { | |
3080 | struct bnx2x *bp = netdev_priv(dev); | |
3081 | u32 *hw_stats, *offset; | |
d5e83632 | 3082 | int i, j, k = 0; |
de0c62db DK |
3083 | |
3084 | if (is_multi(bp)) { | |
619c5cb6 | 3085 | for_each_eth_queue(bp, i) { |
15192a8c | 3086 | hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; |
de0c62db DK |
3087 | for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { |
3088 | if (bnx2x_q_stats_arr[j].size == 0) { | |
3089 | /* skip this counter */ | |
3090 | buf[k + j] = 0; | |
3091 | continue; | |
3092 | } | |
3093 | offset = (hw_stats + | |
3094 | bnx2x_q_stats_arr[j].offset); | |
3095 | if (bnx2x_q_stats_arr[j].size == 4) { | |
3096 | /* 4-byte counter */ | |
3097 | buf[k + j] = (u64) *offset; | |
3098 | continue; | |
3099 | } | |
3100 | /* 8-byte counter */ | |
3101 | buf[k + j] = HILO_U64(*offset, *(offset + 1)); | |
3102 | } | |
3103 | k += BNX2X_NUM_Q_STATS; | |
3104 | } | |
d5e83632 YM |
3105 | } |
3106 | ||
3107 | hw_stats = (u32 *)&bp->eth_stats; | |
3108 | for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { | |
d8361051 | 3109 | if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) |
d5e83632 YM |
3110 | continue; |
3111 | if (bnx2x_stats_arr[i].size == 0) { | |
3112 | /* skip this counter */ | |
3113 | buf[k + j] = 0; | |
3114 | j++; | |
3115 | continue; | |
de0c62db | 3116 | } |
d5e83632 YM |
3117 | offset = (hw_stats + bnx2x_stats_arr[i].offset); |
3118 | if (bnx2x_stats_arr[i].size == 4) { | |
3119 | /* 4-byte counter */ | |
3120 | buf[k + j] = (u64) *offset; | |
de0c62db | 3121 | j++; |
d5e83632 | 3122 | continue; |
de0c62db | 3123 | } |
d5e83632 YM |
3124 | /* 8-byte counter */ |
3125 | buf[k + j] = HILO_U64(*offset, *(offset + 1)); | |
3126 | j++; | |
de0c62db DK |
3127 | } |
3128 | } | |
3129 | ||
32d36134 | 3130 | static int bnx2x_set_phys_id(struct net_device *dev, |
3131 | enum ethtool_phys_id_state state) | |
de0c62db DK |
3132 | { |
3133 | struct bnx2x *bp = netdev_priv(dev); | |
de0c62db | 3134 | |
3fb43eb2 | 3135 | if (!bnx2x_is_nvm_accessible(bp)) { |
51c1a580 MS |
3136 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
3137 | "cannot access eeprom when the interface is down\n"); | |
32d36134 | 3138 | return -EAGAIN; |
51c1a580 | 3139 | } |
de0c62db | 3140 | |
32d36134 | 3141 | switch (state) { |
3142 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 3143 | return 1; /* cycle on/off once per second */ |
de0c62db | 3144 | |
32d36134 | 3145 | case ETHTOOL_ID_ON: |
8203c4b6 | 3146 | bnx2x_acquire_phy_lock(bp); |
32d36134 | 3147 | bnx2x_set_led(&bp->link_params, &bp->link_vars, |
e1943424 | 3148 | LED_MODE_ON, SPEED_1000); |
8203c4b6 | 3149 | bnx2x_release_phy_lock(bp); |
32d36134 | 3150 | break; |
de0c62db | 3151 | |
32d36134 | 3152 | case ETHTOOL_ID_OFF: |
8203c4b6 | 3153 | bnx2x_acquire_phy_lock(bp); |
32d36134 | 3154 | bnx2x_set_led(&bp->link_params, &bp->link_vars, |
e1943424 | 3155 | LED_MODE_FRONT_PANEL_OFF, 0); |
8203c4b6 | 3156 | bnx2x_release_phy_lock(bp); |
32d36134 | 3157 | break; |
3158 | ||
3159 | case ETHTOOL_ID_INACTIVE: | |
8203c4b6 | 3160 | bnx2x_acquire_phy_lock(bp); |
e1943424 DM |
3161 | bnx2x_set_led(&bp->link_params, &bp->link_vars, |
3162 | LED_MODE_OPER, | |
3163 | bp->link_vars.line_speed); | |
8203c4b6 | 3164 | bnx2x_release_phy_lock(bp); |
32d36134 | 3165 | } |
de0c62db DK |
3166 | |
3167 | return 0; | |
3168 | } | |
3169 | ||
5d317c6a MS |
3170 | static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) |
3171 | { | |
5d317c6a MS |
3172 | switch (info->flow_type) { |
3173 | case TCP_V4_FLOW: | |
3174 | case TCP_V6_FLOW: | |
3175 | info->data = RXH_IP_SRC | RXH_IP_DST | | |
3176 | RXH_L4_B_0_1 | RXH_L4_B_2_3; | |
3177 | break; | |
3178 | case UDP_V4_FLOW: | |
3179 | if (bp->rss_conf_obj.udp_rss_v4) | |
3180 | info->data = RXH_IP_SRC | RXH_IP_DST | | |
3181 | RXH_L4_B_0_1 | RXH_L4_B_2_3; | |
3182 | else | |
3183 | info->data = RXH_IP_SRC | RXH_IP_DST; | |
3184 | break; | |
3185 | case UDP_V6_FLOW: | |
3186 | if (bp->rss_conf_obj.udp_rss_v6) | |
3187 | info->data = RXH_IP_SRC | RXH_IP_DST | | |
3188 | RXH_L4_B_0_1 | RXH_L4_B_2_3; | |
3189 | else | |
3190 | info->data = RXH_IP_SRC | RXH_IP_DST; | |
3191 | break; | |
3192 | case IPV4_FLOW: | |
3193 | case IPV6_FLOW: | |
3194 | info->data = RXH_IP_SRC | RXH_IP_DST; | |
3195 | break; | |
3196 | default: | |
3197 | info->data = 0; | |
3198 | break; | |
3199 | } | |
3200 | ||
3201 | return 0; | |
3202 | } | |
3203 | ||
ab532cf3 | 3204 | static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, |
815c7db5 | 3205 | u32 *rules __always_unused) |
ab532cf3 TH |
3206 | { |
3207 | struct bnx2x *bp = netdev_priv(dev); | |
3208 | ||
3209 | switch (info->cmd) { | |
3210 | case ETHTOOL_GRXRINGS: | |
3211 | info->data = BNX2X_NUM_ETH_QUEUES(bp); | |
3212 | return 0; | |
5d317c6a MS |
3213 | case ETHTOOL_GRXFH: |
3214 | return bnx2x_get_rss_flags(bp, info); | |
3215 | default: | |
3216 | DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); | |
3217 | return -EOPNOTSUPP; | |
3218 | } | |
3219 | } | |
3220 | ||
3221 | static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) | |
3222 | { | |
3223 | int udp_rss_requested; | |
3224 | ||
3225 | DP(BNX2X_MSG_ETHTOOL, | |
3226 | "Set rss flags command parameters: flow type = %d, data = %llu\n", | |
3227 | info->flow_type, info->data); | |
3228 | ||
3229 | switch (info->flow_type) { | |
3230 | case TCP_V4_FLOW: | |
3231 | case TCP_V6_FLOW: | |
3232 | /* For TCP only 4-tupple hash is supported */ | |
3233 | if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | | |
3234 | RXH_L4_B_0_1 | RXH_L4_B_2_3)) { | |
3235 | DP(BNX2X_MSG_ETHTOOL, | |
3236 | "Command parameters not supported\n"); | |
3237 | return -EINVAL; | |
5d317c6a | 3238 | } |
2de67439 | 3239 | return 0; |
5d317c6a MS |
3240 | |
3241 | case UDP_V4_FLOW: | |
3242 | case UDP_V6_FLOW: | |
3243 | /* For UDP either 2-tupple hash or 4-tupple hash is supported */ | |
3244 | if (info->data == (RXH_IP_SRC | RXH_IP_DST | | |
2de67439 | 3245 | RXH_L4_B_0_1 | RXH_L4_B_2_3)) |
5d317c6a MS |
3246 | udp_rss_requested = 1; |
3247 | else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) | |
3248 | udp_rss_requested = 0; | |
3249 | else | |
3250 | return -EINVAL; | |
3251 | if ((info->flow_type == UDP_V4_FLOW) && | |
3252 | (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { | |
3253 | bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; | |
3254 | DP(BNX2X_MSG_ETHTOOL, | |
3255 | "rss re-configured, UDP 4-tupple %s\n", | |
3256 | udp_rss_requested ? "enabled" : "disabled"); | |
60cad4e6 | 3257 | return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); |
5d317c6a MS |
3258 | } else if ((info->flow_type == UDP_V6_FLOW) && |
3259 | (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { | |
3260 | bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; | |
5d317c6a MS |
3261 | DP(BNX2X_MSG_ETHTOOL, |
3262 | "rss re-configured, UDP 4-tupple %s\n", | |
3263 | udp_rss_requested ? "enabled" : "disabled"); | |
60cad4e6 | 3264 | return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); |
5d317c6a | 3265 | } |
924d75ab YM |
3266 | return 0; |
3267 | ||
5d317c6a MS |
3268 | case IPV4_FLOW: |
3269 | case IPV6_FLOW: | |
3270 | /* For IP only 2-tupple hash is supported */ | |
3271 | if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { | |
3272 | DP(BNX2X_MSG_ETHTOOL, | |
3273 | "Command parameters not supported\n"); | |
3274 | return -EINVAL; | |
5d317c6a | 3275 | } |
924d75ab YM |
3276 | return 0; |
3277 | ||
5d317c6a MS |
3278 | case SCTP_V4_FLOW: |
3279 | case AH_ESP_V4_FLOW: | |
3280 | case AH_V4_FLOW: | |
3281 | case ESP_V4_FLOW: | |
3282 | case SCTP_V6_FLOW: | |
3283 | case AH_ESP_V6_FLOW: | |
3284 | case AH_V6_FLOW: | |
3285 | case ESP_V6_FLOW: | |
3286 | case IP_USER_FLOW: | |
3287 | case ETHER_FLOW: | |
3288 | /* RSS is not supported for these protocols */ | |
3289 | if (info->data) { | |
3290 | DP(BNX2X_MSG_ETHTOOL, | |
3291 | "Command parameters not supported\n"); | |
3292 | return -EINVAL; | |
5d317c6a | 3293 | } |
924d75ab YM |
3294 | return 0; |
3295 | ||
5d317c6a MS |
3296 | default: |
3297 | return -EINVAL; | |
3298 | } | |
3299 | } | |
3300 | ||
3301 | static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) | |
3302 | { | |
3303 | struct bnx2x *bp = netdev_priv(dev); | |
ab532cf3 | 3304 | |
5d317c6a MS |
3305 | switch (info->cmd) { |
3306 | case ETHTOOL_SRXFH: | |
3307 | return bnx2x_set_rss_flags(bp, info); | |
ab532cf3 | 3308 | default: |
51c1a580 | 3309 | DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); |
ab532cf3 TH |
3310 | return -EOPNOTSUPP; |
3311 | } | |
3312 | } | |
3313 | ||
7850f63f BH |
3314 | static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) |
3315 | { | |
96305234 | 3316 | return T_ETH_INDIRECTION_TABLE_SIZE; |
7850f63f BH |
3317 | } |
3318 | ||
3319 | static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir) | |
ab532cf3 TH |
3320 | { |
3321 | struct bnx2x *bp = netdev_priv(dev); | |
619c5cb6 VZ |
3322 | u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; |
3323 | size_t i; | |
ab532cf3 | 3324 | |
619c5cb6 VZ |
3325 | /* Get the current configuration of the RSS indirection table */ |
3326 | bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); | |
3327 | ||
3328 | /* | |
3329 | * We can't use a memcpy() as an internal storage of an | |
3330 | * indirection table is a u8 array while indir->ring_index | |
3331 | * points to an array of u32. | |
3332 | * | |
3333 | * Indirection table contains the FW Client IDs, so we need to | |
3334 | * align the returned table to the Client ID of the leading RSS | |
3335 | * queue. | |
3336 | */ | |
7850f63f BH |
3337 | for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) |
3338 | indir[i] = ind_table[i] - bp->fp->cl_id; | |
619c5cb6 | 3339 | |
ab532cf3 TH |
3340 | return 0; |
3341 | } | |
3342 | ||
7850f63f | 3343 | static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir) |
ab532cf3 TH |
3344 | { |
3345 | struct bnx2x *bp = netdev_priv(dev); | |
3346 | size_t i; | |
619c5cb6 VZ |
3347 | |
3348 | for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { | |
619c5cb6 VZ |
3349 | /* |
3350 | * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy() | |
3351 | * as an internal storage of an indirection table is a u8 array | |
3352 | * while indir->ring_index points to an array of u32. | |
3353 | * | |
3354 | * Indirection table contains the FW Client IDs, so we need to | |
3355 | * align the received table to the Client ID of the leading RSS | |
3356 | * queue | |
3357 | */ | |
5d317c6a | 3358 | bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; |
619c5cb6 | 3359 | } |
ab532cf3 | 3360 | |
5d317c6a | 3361 | return bnx2x_config_rss_eth(bp, false); |
ab532cf3 TH |
3362 | } |
3363 | ||
0e8d2ec5 MS |
3364 | /** |
3365 | * bnx2x_get_channels - gets the number of RSS queues. | |
3366 | * | |
3367 | * @dev: net device | |
3368 | * @channels: returns the number of max / current queues | |
3369 | */ | |
3370 | static void bnx2x_get_channels(struct net_device *dev, | |
3371 | struct ethtool_channels *channels) | |
3372 | { | |
3373 | struct bnx2x *bp = netdev_priv(dev); | |
3374 | ||
3375 | channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); | |
3376 | channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); | |
3377 | } | |
3378 | ||
3379 | /** | |
3380 | * bnx2x_change_num_queues - change the number of RSS queues. | |
3381 | * | |
3382 | * @bp: bnx2x private structure | |
3383 | * | |
3384 | * Re-configure interrupt mode to get the new number of MSI-X | |
3385 | * vectors and re-add NAPI objects. | |
3386 | */ | |
3387 | static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) | |
3388 | { | |
0e8d2ec5 | 3389 | bnx2x_disable_msi(bp); |
55c11941 MS |
3390 | bp->num_ethernet_queues = num_rss; |
3391 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; | |
3392 | BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); | |
0e8d2ec5 | 3393 | bnx2x_set_int_mode(bp); |
0e8d2ec5 MS |
3394 | } |
3395 | ||
3396 | /** | |
3397 | * bnx2x_set_channels - sets the number of RSS queues. | |
3398 | * | |
3399 | * @dev: net device | |
3400 | * @channels: includes the number of queues requested | |
3401 | */ | |
3402 | static int bnx2x_set_channels(struct net_device *dev, | |
3403 | struct ethtool_channels *channels) | |
3404 | { | |
3405 | struct bnx2x *bp = netdev_priv(dev); | |
3406 | ||
0e8d2ec5 MS |
3407 | DP(BNX2X_MSG_ETHTOOL, |
3408 | "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", | |
3409 | channels->rx_count, channels->tx_count, channels->other_count, | |
3410 | channels->combined_count); | |
3411 | ||
3412 | /* We don't support separate rx / tx channels. | |
3413 | * We don't allow setting 'other' channels. | |
3414 | */ | |
3415 | if (channels->rx_count || channels->tx_count || channels->other_count | |
3416 | || (channels->combined_count == 0) || | |
3417 | (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { | |
3418 | DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); | |
3419 | return -EINVAL; | |
3420 | } | |
3421 | ||
3422 | /* Check if there was a change in the active parameters */ | |
3423 | if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { | |
3424 | DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); | |
3425 | return 0; | |
3426 | } | |
3427 | ||
3428 | /* Set the requested number of queues in bp context. | |
3429 | * Note that the actual number of queues created during load may be | |
3430 | * less than requested if memory is low. | |
3431 | */ | |
3432 | if (unlikely(!netif_running(dev))) { | |
3433 | bnx2x_change_num_queues(bp, channels->combined_count); | |
3434 | return 0; | |
3435 | } | |
5d07d868 | 3436 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); |
0e8d2ec5 MS |
3437 | bnx2x_change_num_queues(bp, channels->combined_count); |
3438 | return bnx2x_nic_load(bp, LOAD_NORMAL); | |
3439 | } | |
3440 | ||
de0c62db DK |
3441 | static const struct ethtool_ops bnx2x_ethtool_ops = { |
3442 | .get_settings = bnx2x_get_settings, | |
3443 | .set_settings = bnx2x_set_settings, | |
3444 | .get_drvinfo = bnx2x_get_drvinfo, | |
3445 | .get_regs_len = bnx2x_get_regs_len, | |
3446 | .get_regs = bnx2x_get_regs, | |
07ba6af4 MS |
3447 | .get_dump_flag = bnx2x_get_dump_flag, |
3448 | .get_dump_data = bnx2x_get_dump_data, | |
3449 | .set_dump = bnx2x_set_dump, | |
de0c62db DK |
3450 | .get_wol = bnx2x_get_wol, |
3451 | .set_wol = bnx2x_set_wol, | |
3452 | .get_msglevel = bnx2x_get_msglevel, | |
3453 | .set_msglevel = bnx2x_set_msglevel, | |
3454 | .nway_reset = bnx2x_nway_reset, | |
3455 | .get_link = bnx2x_get_link, | |
3456 | .get_eeprom_len = bnx2x_get_eeprom_len, | |
3457 | .get_eeprom = bnx2x_get_eeprom, | |
3458 | .set_eeprom = bnx2x_set_eeprom, | |
3459 | .get_coalesce = bnx2x_get_coalesce, | |
3460 | .set_coalesce = bnx2x_set_coalesce, | |
3461 | .get_ringparam = bnx2x_get_ringparam, | |
3462 | .set_ringparam = bnx2x_set_ringparam, | |
3463 | .get_pauseparam = bnx2x_get_pauseparam, | |
3464 | .set_pauseparam = bnx2x_set_pauseparam, | |
de0c62db DK |
3465 | .self_test = bnx2x_self_test, |
3466 | .get_sset_count = bnx2x_get_sset_count, | |
3521b419 | 3467 | .get_priv_flags = bnx2x_get_private_flags, |
de0c62db | 3468 | .get_strings = bnx2x_get_strings, |
32d36134 | 3469 | .set_phys_id = bnx2x_set_phys_id, |
de0c62db | 3470 | .get_ethtool_stats = bnx2x_get_ethtool_stats, |
ab532cf3 | 3471 | .get_rxnfc = bnx2x_get_rxnfc, |
5d317c6a | 3472 | .set_rxnfc = bnx2x_set_rxnfc, |
7850f63f | 3473 | .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, |
ab532cf3 TH |
3474 | .get_rxfh_indir = bnx2x_get_rxfh_indir, |
3475 | .set_rxfh_indir = bnx2x_set_rxfh_indir, | |
0e8d2ec5 MS |
3476 | .get_channels = bnx2x_get_channels, |
3477 | .set_channels = bnx2x_set_channels, | |
24ea818e YM |
3478 | .get_module_info = bnx2x_get_module_info, |
3479 | .get_module_eeprom = bnx2x_get_module_eeprom, | |
e9939c80 YM |
3480 | .get_eee = bnx2x_get_eee, |
3481 | .set_eee = bnx2x_set_eee, | |
be53ce1e | 3482 | .get_ts_info = ethtool_op_get_ts_info, |
de0c62db DK |
3483 | }; |
3484 | ||
005a07ba AE |
3485 | static const struct ethtool_ops bnx2x_vf_ethtool_ops = { |
3486 | .get_settings = bnx2x_get_settings, | |
3487 | .set_settings = bnx2x_set_settings, | |
3488 | .get_drvinfo = bnx2x_get_drvinfo, | |
3489 | .get_msglevel = bnx2x_get_msglevel, | |
3490 | .set_msglevel = bnx2x_set_msglevel, | |
3491 | .get_link = bnx2x_get_link, | |
3492 | .get_coalesce = bnx2x_get_coalesce, | |
3493 | .get_ringparam = bnx2x_get_ringparam, | |
3494 | .set_ringparam = bnx2x_set_ringparam, | |
3495 | .get_sset_count = bnx2x_get_sset_count, | |
3496 | .get_strings = bnx2x_get_strings, | |
3497 | .get_ethtool_stats = bnx2x_get_ethtool_stats, | |
3498 | .get_rxnfc = bnx2x_get_rxnfc, | |
3499 | .set_rxnfc = bnx2x_set_rxnfc, | |
3500 | .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, | |
3501 | .get_rxfh_indir = bnx2x_get_rxfh_indir, | |
3502 | .set_rxfh_indir = bnx2x_set_rxfh_indir, | |
3503 | .get_channels = bnx2x_get_channels, | |
3504 | .set_channels = bnx2x_set_channels, | |
3505 | }; | |
3506 | ||
3507 | void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) | |
de0c62db | 3508 | { |
005a07ba AE |
3509 | if (IS_PF(bp)) |
3510 | SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); | |
3511 | else /* vf */ | |
3512 | SET_ETHTOOL_OPS(netdev, &bnx2x_vf_ethtool_ops); | |
de0c62db | 3513 | } |