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bnx2x: Semantic renovation
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
de0c62db
DK		 25#include "bnx2x.h"
26#include "bnx2x_cmn.h"
27#include "bnx2x_dump.h"
4a33bc03 28#include "bnx2x_init.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
c96bdc0c
DK		 65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
67 4, "[%s]: driver_filtered_tx_pkt" }
ec6ba945
VZ		 68};
69
70#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
71
72static const struct {
73 long offset;
74 int size;
75 u32 flags;
76#define STATS_FLAGS_PORT 1
77#define STATS_FLAGS_FUNC 2
78#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
79 char string[ETH_GSTRING_LEN];
80} bnx2x_stats_arr[] = {
81/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_bytes" },
83 { STATS_OFFSET32(error_bytes_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
85 { STATS_OFFSET32(total_unicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
87 { STATS_OFFSET32(total_multicast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
89 { STATS_OFFSET32(total_broadcast_packets_received_hi),
90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
92 8, STATS_FLAGS_PORT, "rx_crc_errors" },
93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
94 8, STATS_FLAGS_PORT, "rx_align_errors" },
95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
98 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
99/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
100 8, STATS_FLAGS_PORT, "rx_fragments" },
101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
102 8, STATS_FLAGS_PORT, "rx_jabbers" },
103 { STATS_OFFSET32(no_buff_discard_hi),
104 8, STATS_FLAGS_BOTH, "rx_discards" },
105 { STATS_OFFSET32(mac_filter_discard),
106 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 107 { STATS_OFFSET32(mf_tag_discard),
108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 109 { STATS_OFFSET32(pfc_frames_received_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_received" },
111 { STATS_OFFSET32(pfc_frames_sent_hi),
112 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 113 { STATS_OFFSET32(brb_drop_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_discard" },
115 { STATS_OFFSET32(brb_truncate_hi),
116 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
117 { STATS_OFFSET32(pause_frames_received_hi),
118 8, STATS_FLAGS_PORT, "rx_pause_frames" },
119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
121 { STATS_OFFSET32(nig_timer_max),
122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
123/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
125 { STATS_OFFSET32(rx_skb_alloc_failed),
126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
127 { STATS_OFFSET32(hw_csum_err),
128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
129
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, STATS_FLAGS_PORT, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, STATS_FLAGS_PORT, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
144/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, STATS_FLAGS_PORT, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, STATS_FLAGS_PORT, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
164/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 171 8, STATS_FLAGS_PORT, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 177 8, STATS_FLAGS_FUNC, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, STATS_FLAGS_FUNC, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
c96bdc0c
DK		 182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
e9939c80
YM		 184 { STATS_OFFSET32(eee_tx_lpi),
185 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
ec6ba945
VZ		 186};
187
188#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
07ba6af4 189
1ac9e428
YR		 190static int bnx2x_get_port_type(struct bnx2x *bp)
191{
192 int port_type;
193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 switch (bp->link_params.phy[phy_idx].media_type) {
dbef807e
YM		 195 case ETH_PHY_SFPP_10G_FIBER:
196 case ETH_PHY_SFP_1G_FIBER:
1ac9e428
YR		 197 case ETH_PHY_XFP_FIBER:
198 case ETH_PHY_KR:
199 case ETH_PHY_CX4:
200 port_type = PORT_FIBRE;
201 break;
202 case ETH_PHY_DA_TWINAX:
203 port_type = PORT_DA;
204 break;
205 case ETH_PHY_BASE_T:
206 port_type = PORT_TP;
207 break;
208 case ETH_PHY_NOT_PRESENT:
209 port_type = PORT_NONE;
210 break;
211 case ETH_PHY_UNSPECIFIED:
212 default:
213 port_type = PORT_OTHER;
214 break;
215 }
216 return port_type;
217}
ec6ba945 218
de0c62db
DK		 219static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
220{
221 struct bnx2x *bp = netdev_priv(dev);
a22f0788 222 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 223
a22f0788
YR		 224 /* Dual Media boards present all available port types */
225 cmd->supported = bp->port.supported[cfg_idx] |
226 (bp->port.supported[cfg_idx ^ 1] &
227 (SUPPORTED_TP | SUPPORTED_FIBRE));
228 cmd->advertising = bp->port.advertising[cfg_idx];
dbef807e
YM		 229 if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
230 ETH_PHY_SFP_1G_FIBER) {
231 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
232 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
233 }
de0c62db 234
59694f00
YM		 235 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
236 !(bp->flags & MF_FUNC_DIS)) {
2de67439 237 cmd->duplex = bp->link_vars.duplex;
38298461
YM		 238
239 if (IS_MF(bp) && !BP_NOMCP(bp))
240 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
59694f00
YM		 241 else
242 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
de0c62db 243 } else {
38298461
YM		 244 cmd->duplex = DUPLEX_UNKNOWN;
245 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
de0c62db 246 }
f2e0899f 247
1ac9e428 248 cmd->port = bnx2x_get_port_type(bp);
a22f0788 249
de0c62db
DK		 250 cmd->phy_address = bp->mdio.prtad;
251 cmd->transceiver = XCVR_INTERNAL;
252
a22f0788 253 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 254 cmd->autoneg = AUTONEG_ENABLE;
255 else
256 cmd->autoneg = AUTONEG_DISABLE;
257
9e7e8399
MY		 258 /* Publish LP advertised speeds and FC */
259 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
260 u32 status = bp->link_vars.link_status;
261
262 cmd->lp_advertising |= ADVERTISED_Autoneg;
263 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
264 cmd->lp_advertising |= ADVERTISED_Pause;
265 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
266 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
267
268 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
269 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
270 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
271 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
272 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
273 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
274 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
275 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
276 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
277 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
278 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
279 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
280 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
281 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
282 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
283 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
284 }
285
de0c62db
DK		 286 cmd->maxtxpkt = 0;
287 cmd->maxrxpkt = 0;
288
51c1a580 289 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 290 " supported 0x%x advertising 0x%x speed %u\n"
291 " duplex %d port %d phy_address %d transceiver %d\n"
292 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 293 cmd->cmd, cmd->supported, cmd->advertising,
294 ethtool_cmd_speed(cmd),
de0c62db
DK		 295 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
296 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
297
298 return 0;
299}
300
301static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
302{
303 struct bnx2x *bp = netdev_priv(dev);
a22f0788 304 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
dbef807e 305 u32 speed, phy_idx;
de0c62db 306
0793f83f 307 if (IS_MF_SD(bp))
de0c62db
DK		 308 return 0;
309
51c1a580 310 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
b3337e4c 311 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 312 " duplex %d port %d phy_address %d transceiver %d\n"
313 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 314 cmd->cmd, cmd->supported, cmd->advertising,
315 ethtool_cmd_speed(cmd),
de0c62db
DK		 316 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
317 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
318
b3337e4c 319 speed = ethtool_cmd_speed(cmd);
0793f83f 320
38298461
YM		 321 /* If recieved a request for an unknown duplex, assume full*/
322 if (cmd->duplex == DUPLEX_UNKNOWN)
323 cmd->duplex = DUPLEX_FULL;
324
0793f83f 325 if (IS_MF_SI(bp)) {
e3835b99 326 u32 part;
0793f83f
DK		 327 u32 line_speed = bp->link_vars.line_speed;
328
329 /* use 10G if no link detected */
330 if (!line_speed)
331 line_speed = 10000;
332
333 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
51c1a580
MS		 334 DP(BNX2X_MSG_ETHTOOL,
335 "To set speed BC %X or higher is required, please upgrade BC\n",
336 REQ_BC_VER_4_SET_MF_BW);
0793f83f
DK		 337 return -EINVAL;
338 }
e3835b99 339
faa6fcbb 340 part = (speed * 100) / line_speed;
e3835b99 341
faa6fcbb 342 if (line_speed < speed || !part) {
51c1a580
MS		 343 DP(BNX2X_MSG_ETHTOOL,
344 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
0793f83f
DK		 345 return -EINVAL;
346 }
0793f83f 347
e3835b99
DK		 348 if (bp->state != BNX2X_STATE_OPEN)
349 /* store value for following "load" */
350 bp->pending_max = part;
351 else
352 bnx2x_update_max_mf_config(bp, part);
0793f83f 353
0793f83f
DK		 354 return 0;
355 }
356
a22f0788
YR		 357 cfg_idx = bnx2x_get_link_cfg_idx(bp);
358 old_multi_phy_config = bp->link_params.multi_phy_config;
359 switch (cmd->port) {
360 case PORT_TP:
361 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
362 break; /* no port change */
363
364 if (!(bp->port.supported[0] & SUPPORTED_TP ||
365 bp->port.supported[1] & SUPPORTED_TP)) {
51c1a580 366 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 367 return -EINVAL;
368 }
369 bp->link_params.multi_phy_config &=
370 ~PORT_HW_CFG_PHY_SELECTION_MASK;
371 if (bp->link_params.multi_phy_config &
372 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
373 bp->link_params.multi_phy_config |=
374 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
375 else
376 bp->link_params.multi_phy_config |=
377 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
378 break;
379 case PORT_FIBRE:
bfdb5823 380 case PORT_DA:
a22f0788
YR		 381 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
382 break; /* no port change */
383
384 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
385 bp->port.supported[1] & SUPPORTED_FIBRE)) {
51c1a580 386 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 387 return -EINVAL;
388 }
389 bp->link_params.multi_phy_config &=
390 ~PORT_HW_CFG_PHY_SELECTION_MASK;
391 if (bp->link_params.multi_phy_config &
392 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
393 bp->link_params.multi_phy_config |=
394 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
395 else
396 bp->link_params.multi_phy_config |=
397 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
398 break;
399 default:
51c1a580 400 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 401 return -EINVAL;
402 }
2de67439 403 /* Save new config in case command complete successfully */
a22f0788
YR		 404 new_multi_phy_config = bp->link_params.multi_phy_config;
405 /* Get the new cfg_idx */
406 cfg_idx = bnx2x_get_link_cfg_idx(bp);
407 /* Restore old config in case command failed */
408 bp->link_params.multi_phy_config = old_multi_phy_config;
51c1a580 409 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
a22f0788 410
de0c62db 411 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 412 u32 an_supported_speed = bp->port.supported[cfg_idx];
413 if (bp->link_params.phy[EXT_PHY1].type ==
414 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
415 an_supported_speed |= (SUPPORTED_100baseT_Half |
416 SUPPORTED_100baseT_Full);
a22f0788 417 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 418 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
de0c62db
DK		 419 return -EINVAL;
420 }
421
422 /* advertise the requested speed and duplex if supported */
75318327 423 if (cmd->advertising & ~an_supported_speed) {
51c1a580
MS		 424 DP(BNX2X_MSG_ETHTOOL,
425 "Advertisement parameters are not supported\n");
8d661637
YR		 426 return -EINVAL;
427 }
de0c62db 428
a22f0788 429 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 430 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
431 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 432 cmd->advertising);
8d661637
YR		 433 if (cmd->advertising) {
434
435 bp->link_params.speed_cap_mask[cfg_idx] = 0;
436 if (cmd->advertising & ADVERTISED_10baseT_Half) {
437 bp->link_params.speed_cap_mask[cfg_idx] |=
438 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
439 }
440 if (cmd->advertising & ADVERTISED_10baseT_Full)
441 bp->link_params.speed_cap_mask[cfg_idx] |=
442 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 443
8d661637
YR		 444 if (cmd->advertising & ADVERTISED_100baseT_Full)
445 bp->link_params.speed_cap_mask[cfg_idx] |=
446 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
447
448 if (cmd->advertising & ADVERTISED_100baseT_Half) {
449 bp->link_params.speed_cap_mask[cfg_idx] |=
450 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
451 }
452 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
453 bp->link_params.speed_cap_mask[cfg_idx] |=
454 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
455 }
456 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
457 ADVERTISED_1000baseKX_Full))
458 bp->link_params.speed_cap_mask[cfg_idx] |=
459 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
460
461 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
462 ADVERTISED_10000baseKX4_Full |
463 ADVERTISED_10000baseKR_Full))
464 bp->link_params.speed_cap_mask[cfg_idx] |=
465 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
466 }
de0c62db
DK		 467 } else { /* forced speed */
468 /* advertise the requested speed and duplex if supported */
a22f0788 469 switch (speed) {
de0c62db
DK		 470 case SPEED_10:
471 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 472 if (!(bp->port.supported[cfg_idx] &
de0c62db 473 SUPPORTED_10baseT_Full)) {
51c1a580 474 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 475 "10M full not supported\n");
476 return -EINVAL;
477 }
478
479 advertising = (ADVERTISED_10baseT_Full |
480 ADVERTISED_TP);
481 } else {
a22f0788 482 if (!(bp->port.supported[cfg_idx] &
de0c62db 483 SUPPORTED_10baseT_Half)) {
51c1a580 484 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 485 "10M half not supported\n");
486 return -EINVAL;
487 }
488
489 advertising = (ADVERTISED_10baseT_Half |
490 ADVERTISED_TP);
491 }
492 break;
493
494 case SPEED_100:
495 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 496 if (!(bp->port.supported[cfg_idx] &
de0c62db 497 SUPPORTED_100baseT_Full)) {
51c1a580 498 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 499 "100M full not supported\n");
500 return -EINVAL;
501 }
502
503 advertising = (ADVERTISED_100baseT_Full |
504 ADVERTISED_TP);
505 } else {
a22f0788 506 if (!(bp->port.supported[cfg_idx] &
de0c62db 507 SUPPORTED_100baseT_Half)) {
51c1a580 508 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 509 "100M half not supported\n");
510 return -EINVAL;
511 }
512
513 advertising = (ADVERTISED_100baseT_Half |
514 ADVERTISED_TP);
515 }
516 break;
517
518 case SPEED_1000:
519 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 520 DP(BNX2X_MSG_ETHTOOL,
521 "1G half not supported\n");
de0c62db
DK		 522 return -EINVAL;
523 }
524
a22f0788
YR		 525 if (!(bp->port.supported[cfg_idx] &
526 SUPPORTED_1000baseT_Full)) {
51c1a580
MS		 527 DP(BNX2X_MSG_ETHTOOL,
528 "1G full not supported\n");
de0c62db
DK		 529 return -EINVAL;
530 }
531
532 advertising = (ADVERTISED_1000baseT_Full |
533 ADVERTISED_TP);
534 break;
535
536 case SPEED_2500:
537 if (cmd->duplex != DUPLEX_FULL) {
51c1a580 538 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 539 "2.5G half not supported\n");
540 return -EINVAL;
541 }
542
a22f0788
YR		 543 if (!(bp->port.supported[cfg_idx]
544 & SUPPORTED_2500baseX_Full)) {
51c1a580 545 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 546 "2.5G full not supported\n");
547 return -EINVAL;
548 }
549
550 advertising = (ADVERTISED_2500baseX_Full |
551 ADVERTISED_TP);
552 break;
553
554 case SPEED_10000:
555 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 556 DP(BNX2X_MSG_ETHTOOL,
557 "10G half not supported\n");
de0c62db
DK		 558 return -EINVAL;
559 }
dbef807e 560 phy_idx = bnx2x_get_cur_phy_idx(bp);
a22f0788 561 if (!(bp->port.supported[cfg_idx]
dbef807e
YM		 562 & SUPPORTED_10000baseT_Full) ||
563 (bp->link_params.phy[phy_idx].media_type ==
564 ETH_PHY_SFP_1G_FIBER)) {
51c1a580
MS		 565 DP(BNX2X_MSG_ETHTOOL,
566 "10G full not supported\n");
de0c62db
DK		 567 return -EINVAL;
568 }
569
570 advertising = (ADVERTISED_10000baseT_Full |
571 ADVERTISED_FIBRE);
572 break;
573
574 default:
51c1a580 575 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
de0c62db
DK		 576 return -EINVAL;
577 }
578
a22f0788
YR		 579 bp->link_params.req_line_speed[cfg_idx] = speed;
580 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
581 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 582 }
583
51c1a580 584 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
f1deab50 585 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 586 bp->link_params.req_line_speed[cfg_idx],
587 bp->link_params.req_duplex[cfg_idx],
588 bp->port.advertising[cfg_idx]);
de0c62db 589
a22f0788
YR		 590 /* Set new config */
591 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 592 if (netif_running(dev)) {
593 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
594 bnx2x_link_set(bp);
595 }
596
597 return 0;
598}
599
07ba6af4
MS		 600#define DUMP_ALL_PRESETS 0x1FFF
601#define DUMP_MAX_PRESETS 13
0fea29c1 602
07ba6af4 603static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
0fea29c1
VZ		 604{
605 if (CHIP_IS_E1(bp))
07ba6af4 606 return dump_num_registers[0][preset-1];
0fea29c1 607 else if (CHIP_IS_E1H(bp))
07ba6af4 608 return dump_num_registers[1][preset-1];
0fea29c1 609 else if (CHIP_IS_E2(bp))
07ba6af4 610 return dump_num_registers[2][preset-1];
0fea29c1 611 else if (CHIP_IS_E3A0(bp))
07ba6af4 612 return dump_num_registers[3][preset-1];
0fea29c1 613 else if (CHIP_IS_E3B0(bp))
07ba6af4 614 return dump_num_registers[4][preset-1];
0fea29c1 615 else
07ba6af4
MS		 616 return 0;
617}
618
619static int __bnx2x_get_regs_len(struct bnx2x *bp)
620{
621 u32 preset_idx;
622 int regdump_len = 0;
623
624 /* Calculate the total preset regs length */
625 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
626 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
627
628 return regdump_len;
629}
630
631static int bnx2x_get_regs_len(struct net_device *dev)
632{
633 struct bnx2x *bp = netdev_priv(dev);
634 int regdump_len = 0;
635
636 regdump_len = __bnx2x_get_regs_len(bp);
637 regdump_len *= 4;
638 regdump_len += sizeof(struct dump_header);
639
640 return regdump_len;
0fea29c1
VZ		 641}
642
07ba6af4
MS		 643#define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
644#define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
645#define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
646#define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
647#define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
648
649#define IS_REG_IN_PRESET(presets, idx) \
650 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
651
0fea29c1 652/******* Paged registers info selectors ********/
1191cb83 653static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
0fea29c1
VZ		 654{
655 if (CHIP_IS_E2(bp))
656 return page_vals_e2;
657 else if (CHIP_IS_E3(bp))
658 return page_vals_e3;
659 else
660 return NULL;
661}
662
1191cb83 663static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
0fea29c1
VZ		 664{
665 if (CHIP_IS_E2(bp))
666 return PAGE_MODE_VALUES_E2;
667 else if (CHIP_IS_E3(bp))
668 return PAGE_MODE_VALUES_E3;
669 else
670 return 0;
671}
672
1191cb83 673static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
0fea29c1
VZ		 674{
675 if (CHIP_IS_E2(bp))
676 return page_write_regs_e2;
677 else if (CHIP_IS_E3(bp))
678 return page_write_regs_e3;
679 else
680 return NULL;
681}
682
1191cb83 683static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
0fea29c1
VZ		 684{
685 if (CHIP_IS_E2(bp))
686 return PAGE_WRITE_REGS_E2;
687 else if (CHIP_IS_E3(bp))
688 return PAGE_WRITE_REGS_E3;
689 else
690 return 0;
691}
692
1191cb83 693static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
0fea29c1
VZ		 694{
695 if (CHIP_IS_E2(bp))
696 return page_read_regs_e2;
697 else if (CHIP_IS_E3(bp))
698 return page_read_regs_e3;
699 else
700 return NULL;
701}
702
1191cb83 703static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
0fea29c1
VZ		 704{
705 if (CHIP_IS_E2(bp))
706 return PAGE_READ_REGS_E2;
707 else if (CHIP_IS_E3(bp))
708 return PAGE_READ_REGS_E3;
709 else
710 return 0;
711}
712
07ba6af4
MS		 713static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
714 const struct reg_addr *reg_info)
0fea29c1 715{
07ba6af4
MS		 716 if (CHIP_IS_E1(bp))
717 return IS_E1_REG(reg_info->chips);
718 else if (CHIP_IS_E1H(bp))
719 return IS_E1H_REG(reg_info->chips);
720 else if (CHIP_IS_E2(bp))
721 return IS_E2_REG(reg_info->chips);
722 else if (CHIP_IS_E3A0(bp))
723 return IS_E3A0_REG(reg_info->chips);
724 else if (CHIP_IS_E3B0(bp))
725 return IS_E3B0_REG(reg_info->chips);
726 else
727 return false;
0fea29c1 728}
de0c62db 729
de0c62db 730
07ba6af4
MS		 731static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
732 const struct wreg_addr *wreg_info)
733{
734 if (CHIP_IS_E1(bp))
735 return IS_E1_REG(wreg_info->chips);
736 else if (CHIP_IS_E1H(bp))
737 return IS_E1H_REG(wreg_info->chips);
738 else if (CHIP_IS_E2(bp))
739 return IS_E2_REG(wreg_info->chips);
740 else if (CHIP_IS_E3A0(bp))
741 return IS_E3A0_REG(wreg_info->chips);
742 else if (CHIP_IS_E3B0(bp))
743 return IS_E3B0_REG(wreg_info->chips);
744 else
745 return false;
de0c62db
DK		 746}
747
0fea29c1
VZ		 748/**
749 * bnx2x_read_pages_regs - read "paged" registers
750 *
751 * @bp device handle
752 * @p output buffer
753 *
2de67439
YM		 754 * Reads "paged" memories: memories that may only be read by first writing to a
755 * specific address ("write address") and then reading from a specific address
756 * ("read address"). There may be more than one write address per "page" and
757 * more than one read address per write address.
0fea29c1 758 */
07ba6af4 759static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
f2e0899f
DK		 760{
761 u32 i, j, k, n;
07ba6af4 762
0fea29c1
VZ		 763 /* addresses of the paged registers */
764 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
765 /* number of paged registers */
766 int num_pages = __bnx2x_get_page_reg_num(bp);
767 /* write addresses */
768 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
769 /* number of write addresses */
770 int write_num = __bnx2x_get_page_write_num(bp);
771 /* read addresses info */
772 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
773 /* number of read addresses */
774 int read_num = __bnx2x_get_page_read_num(bp);
07ba6af4 775 u32 addr, size;
0fea29c1
VZ		 776
777 for (i = 0; i < num_pages; i++) {
778 for (j = 0; j < write_num; j++) {
779 REG_WR(bp, write_addr[j], page_addr[i]);
07ba6af4
MS		 780
781 for (k = 0; k < read_num; k++) {
782 if (IS_REG_IN_PRESET(read_addr[k].presets,
783 preset)) {
784 size = read_addr[k].size;
785 for (n = 0; n < size; n++) {
786 addr = read_addr[k].addr + n*4;
787 *p++ = REG_RD(bp, addr);
788 }
789 }
790 }
f2e0899f
DK		 791 }
792 }
793}
794
07ba6af4 795static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
0fea29c1 796{
07ba6af4
MS		 797 u32 i, j, addr;
798 const struct wreg_addr *wreg_addr_p = NULL;
799
800 if (CHIP_IS_E1(bp))
801 wreg_addr_p = &wreg_addr_e1;
802 else if (CHIP_IS_E1H(bp))
803 wreg_addr_p = &wreg_addr_e1h;
804 else if (CHIP_IS_E2(bp))
805 wreg_addr_p = &wreg_addr_e2;
806 else if (CHIP_IS_E3A0(bp))
807 wreg_addr_p = &wreg_addr_e3;
808 else if (CHIP_IS_E3B0(bp))
809 wreg_addr_p = &wreg_addr_e3b0;
810
811 /* Read the idle_chk registers */
812 for (i = 0; i < IDLE_REGS_COUNT; i++) {
813 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
814 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
815 for (j = 0; j < idle_reg_addrs[i].size; j++)
816 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
817 }
818 }
0fea29c1
VZ		 819
820 /* Read the regular registers */
07ba6af4
MS		 821 for (i = 0; i < REGS_COUNT; i++) {
822 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
823 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
0fea29c1
VZ		 824 for (j = 0; j < reg_addrs[i].size; j++)
825 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
07ba6af4
MS		 826 }
827 }
828
829 /* Read the CAM registers */
830 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
831 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
832 for (i = 0; i < wreg_addr_p->size; i++) {
833 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
834
835 /* In case of wreg_addr register, read additional
836 registers from read_regs array
837 */
838 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
839 addr = *(wreg_addr_p->read_regs);
840 *p++ = REG_RD(bp, addr + j*4);
841 }
842 }
843 }
844
845 /* Paged registers are supported in E2 & E3 only */
846 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
847 /* Read "paged" registes */
848 bnx2x_read_pages_regs(bp, p, preset);
849 }
850
851 return 0;
852}
853
854static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
855{
856 u32 preset_idx;
0fea29c1 857
07ba6af4
MS		 858 /* Read all registers, by reading all preset registers */
859 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
860 /* Skip presets with IOR */
861 if ((preset_idx == 2) ||
862 (preset_idx == 5) ||
863 (preset_idx == 8) ||
864 (preset_idx == 11))
865 continue;
866 __bnx2x_get_preset_regs(bp, p, preset_idx);
867 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
868 }
0fea29c1
VZ		 869}
870
de0c62db
DK		 871static void bnx2x_get_regs(struct net_device *dev,
872 struct ethtool_regs *regs, void *_p)
873{
0fea29c1 874 u32 *p = _p;
de0c62db 875 struct bnx2x *bp = netdev_priv(dev);
07ba6af4 876 struct dump_header dump_hdr = {0};
de0c62db 877
07ba6af4 878 regs->version = 2;
de0c62db
DK		 879 memset(p, 0, regs->len);
880
881 if (!netif_running(bp->dev))
882 return;
883
4a33bc03
VZ		 884 /* Disable parity attentions as long as following dump may
885 * cause false alarms by reading never written registers. We
886 * will re-enable parity attentions right after the dump.
887 */
07ba6af4
MS		 888
889 /* Disable parity on path 0 */
890 bnx2x_pretend_func(bp, 0);
4a33bc03
VZ		 891 bnx2x_disable_blocks_parity(bp);
892
07ba6af4
MS		 893 /* Disable parity on path 1 */
894 bnx2x_pretend_func(bp, 1);
895 bnx2x_disable_blocks_parity(bp);
f2e0899f 896
07ba6af4
MS		 897 /* Return to current function */
898 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
de0c62db 899
07ba6af4
MS		 900 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
901 dump_hdr.preset = DUMP_ALL_PRESETS;
902 dump_hdr.version = BNX2X_DUMP_VERSION;
903
904 /* dump_meta_data presents OR of CHIP and PATH. */
905 if (CHIP_IS_E1(bp)) {
906 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
907 } else if (CHIP_IS_E1H(bp)) {
908 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
909 } else if (CHIP_IS_E2(bp)) {
910 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
911 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
912 } else if (CHIP_IS_E3A0(bp)) {
913 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
914 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
915 } else if (CHIP_IS_E3B0(bp)) {
916 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
917 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
918 }
919
920 memcpy(p, &dump_hdr, sizeof(struct dump_header));
921 p += dump_hdr.header_size + 1;
de0c62db 922
0fea29c1
VZ		 923 /* Actually read the registers */
924 __bnx2x_get_regs(bp, p);
925
07ba6af4
MS		 926 /* Re-enable parity attentions on path 0 */
927 bnx2x_pretend_func(bp, 0);
928 bnx2x_clear_blocks_parity(bp);
929 bnx2x_enable_blocks_parity(bp);
930
931 /* Re-enable parity attentions on path 1 */
932 bnx2x_pretend_func(bp, 1);
4a33bc03 933 bnx2x_clear_blocks_parity(bp);
c9ee9206 934 bnx2x_enable_blocks_parity(bp);
07ba6af4
MS		 935
936 /* Return to current function */
937 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
938}
939
940static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
941{
942 struct bnx2x *bp = netdev_priv(dev);
943 int regdump_len = 0;
944
945 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
946 regdump_len *= 4;
947 regdump_len += sizeof(struct dump_header);
948
949 return regdump_len;
950}
951
952static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
953{
954 struct bnx2x *bp = netdev_priv(dev);
955
956 /* Use the ethtool_dump "flag" field as the dump preset index */
957 bp->dump_preset_idx = val->flag;
958 return 0;
959}
960
961static int bnx2x_get_dump_flag(struct net_device *dev,
962 struct ethtool_dump *dump)
963{
964 struct bnx2x *bp = netdev_priv(dev);
965
966 /* Calculate the requested preset idx length */
967 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
968 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
969 bp->dump_preset_idx, dump->len);
970
971 dump->flag = ETHTOOL_GET_DUMP_DATA;
972 return 0;
973}
974
975static int bnx2x_get_dump_data(struct net_device *dev,
976 struct ethtool_dump *dump,
977 void *buffer)
978{
979 u32 *p = buffer;
980 struct bnx2x *bp = netdev_priv(dev);
981 struct dump_header dump_hdr = {0};
982
983 memset(p, 0, dump->len);
984
985 /* Disable parity attentions as long as following dump may
986 * cause false alarms by reading never written registers. We
987 * will re-enable parity attentions right after the dump.
988 */
989
990 /* Disable parity on path 0 */
991 bnx2x_pretend_func(bp, 0);
992 bnx2x_disable_blocks_parity(bp);
993
994 /* Disable parity on path 1 */
995 bnx2x_pretend_func(bp, 1);
996 bnx2x_disable_blocks_parity(bp);
997
998 /* Return to current function */
999 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1000
1001 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1002 dump_hdr.preset = bp->dump_preset_idx;
1003 dump_hdr.version = BNX2X_DUMP_VERSION;
1004
1005 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1006
1007 /* dump_meta_data presents OR of CHIP and PATH. */
1008 if (CHIP_IS_E1(bp)) {
1009 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1010 } else if (CHIP_IS_E1H(bp)) {
1011 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1012 } else if (CHIP_IS_E2(bp)) {
1013 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1014 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1015 } else if (CHIP_IS_E3A0(bp)) {
1016 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1017 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1018 } else if (CHIP_IS_E3B0(bp)) {
1019 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1020 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1021 }
1022
1023 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1024 p += dump_hdr.header_size + 1;
1025
1026 /* Actually read the registers */
1027 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1028
1029 /* Re-enable parity attentions on path 0 */
1030 bnx2x_pretend_func(bp, 0);
1031 bnx2x_clear_blocks_parity(bp);
1032 bnx2x_enable_blocks_parity(bp);
1033
1034 /* Re-enable parity attentions on path 1 */
1035 bnx2x_pretend_func(bp, 1);
1036 bnx2x_clear_blocks_parity(bp);
1037 bnx2x_enable_blocks_parity(bp);
1038
1039 /* Return to current function */
1040 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1041
1042 return 0;
de0c62db
DK		 1043}
1044
de0c62db
DK		 1045static void bnx2x_get_drvinfo(struct net_device *dev,
1046 struct ethtool_drvinfo *info)
1047{
1048 struct bnx2x *bp = netdev_priv(dev);
de0c62db 1049
68aad78c
RJ		 1050 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1051 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db 1052
8ca5e17e
AE		 1053 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1054
68aad78c 1055 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db 1056 info->n_stats = BNX2X_NUM_STATS;
cf2c1df6 1057 info->testinfo_len = BNX2X_NUM_TESTS(bp);
de0c62db
DK		 1058 info->eedump_len = bp->common.flash_size;
1059 info->regdump_len = bnx2x_get_regs_len(dev);
1060}
1061
1062static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1063{
1064 struct bnx2x *bp = netdev_priv(dev);
1065
1066 if (bp->flags & NO_WOL_FLAG) {
1067 wol->supported = 0;
1068 wol->wolopts = 0;
1069 } else {
1070 wol->supported = WAKE_MAGIC;
1071 if (bp->wol)
1072 wol->wolopts = WAKE_MAGIC;
1073 else
1074 wol->wolopts = 0;
1075 }
1076 memset(&wol->sopass, 0, sizeof(wol->sopass));
1077}
1078
1079static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1080{
1081 struct bnx2x *bp = netdev_priv(dev);
1082
51c1a580 1083 if (wol->wolopts & ~WAKE_MAGIC) {
2de67439 1084 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
de0c62db 1085 return -EINVAL;
51c1a580 1086 }
de0c62db
DK		 1087
1088 if (wol->wolopts & WAKE_MAGIC) {
51c1a580 1089 if (bp->flags & NO_WOL_FLAG) {
2de67439 1090 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
de0c62db 1091 return -EINVAL;
51c1a580 1092 }
de0c62db
DK		 1093 bp->wol = 1;
1094 } else
1095 bp->wol = 0;
1096
1097 return 0;
1098}
1099
1100static u32 bnx2x_get_msglevel(struct net_device *dev)
1101{
1102 struct bnx2x *bp = netdev_priv(dev);
1103
1104 return bp->msg_enable;
1105}
1106
1107static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1108{
1109 struct bnx2x *bp = netdev_priv(dev);
1110
7a25cc73
DK		 1111 if (capable(CAP_NET_ADMIN)) {
1112 /* dump MCP trace */
ad5afc89 1113 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
7a25cc73 1114 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 1115 bp->msg_enable = level;
7a25cc73 1116 }
de0c62db
DK		 1117}
1118
1119static int bnx2x_nway_reset(struct net_device *dev)
1120{
1121 struct bnx2x *bp = netdev_priv(dev);
1122
1123 if (!bp->port.pmf)
1124 return 0;
1125
1126 if (netif_running(dev)) {
1127 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 1128 bnx2x_force_link_reset(bp);
de0c62db
DK		 1129 bnx2x_link_set(bp);
1130 }
1131
1132 return 0;
1133}
1134
1135static u32 bnx2x_get_link(struct net_device *dev)
1136{
1137 struct bnx2x *bp = netdev_priv(dev);
1138
f2e0899f 1139 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 1140 return 0;
1141
1142 return bp->link_vars.link_up;
1143}
1144
1145static int bnx2x_get_eeprom_len(struct net_device *dev)
1146{
1147 struct bnx2x *bp = netdev_priv(dev);
1148
1149 return bp->common.flash_size;
1150}
1151
f16da43b
AE		 1152/* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
1153 * we done things the other way around, if two pfs from the same port would
1154 * attempt to access nvram at the same time, we could run into a scenario such
1155 * as:
1156 * pf A takes the port lock.
1157 * pf B succeeds in taking the same lock since they are from the same port.
1158 * pf A takes the per pf misc lock. Performs eeprom access.
1159 * pf A finishes. Unlocks the per pf misc lock.
1160 * Pf B takes the lock and proceeds to perform it's own access.
1161 * pf A unlocks the per port lock, while pf B is still working (!).
1162 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
2de67439 1163 * access corrupted by pf B)
f16da43b 1164 */
de0c62db
DK		 1165static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1166{
1167 int port = BP_PORT(bp);
1168 int count, i;
f16da43b
AE		 1169 u32 val;
1170
1171 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1172 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1173
1174 /* adjust timeout for emulation/FPGA */
754a2f52 1175 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1176 if (CHIP_REV_IS_SLOW(bp))
1177 count *= 100;
1178
1179 /* request access to nvram interface */
1180 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1181 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1182
1183 for (i = 0; i < count*10; i++) {
1184 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1185 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1186 break;
1187
1188 udelay(5);
1189 }
1190
1191 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
51c1a580
MS		 1192 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1193 "cannot get access to nvram interface\n");
de0c62db
DK		 1194 return -EBUSY;
1195 }
1196
1197 return 0;
1198}
1199
1200static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1201{
1202 int port = BP_PORT(bp);
1203 int count, i;
f16da43b 1204 u32 val;
de0c62db
DK		 1205
1206 /* adjust timeout for emulation/FPGA */
754a2f52 1207 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1208 if (CHIP_REV_IS_SLOW(bp))
1209 count *= 100;
1210
1211 /* relinquish nvram interface */
1212 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1213 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1214
1215 for (i = 0; i < count*10; i++) {
1216 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1217 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1218 break;
1219
1220 udelay(5);
1221 }
1222
1223 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
51c1a580
MS		 1224 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1225 "cannot free access to nvram interface\n");
de0c62db
DK		 1226 return -EBUSY;
1227 }
1228
f16da43b
AE		 1229 /* release HW lock: protect against other PFs in PF Direct Assignment */
1230 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1231 return 0;
1232}
1233
1234static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1235{
1236 u32 val;
1237
1238 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1239
1240 /* enable both bits, even on read */
1241 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1242 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1243 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1244}
1245
1246static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1247{
1248 u32 val;
1249
1250 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1251
1252 /* disable both bits, even after read */
1253 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1254 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1255 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1256}
1257
1258static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1259 u32 cmd_flags)
1260{
1261 int count, i, rc;
1262 u32 val;
1263
1264 /* build the command word */
1265 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1266
1267 /* need to clear DONE bit separately */
1268 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1269
1270 /* address of the NVRAM to read from */
1271 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1272 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1273
1274 /* issue a read command */
1275 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1276
1277 /* adjust timeout for emulation/FPGA */
754a2f52 1278 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1279 if (CHIP_REV_IS_SLOW(bp))
1280 count *= 100;
1281
1282 /* wait for completion */
1283 *ret_val = 0;
1284 rc = -EBUSY;
1285 for (i = 0; i < count; i++) {
1286 udelay(5);
1287 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1288
1289 if (val & MCPR_NVM_COMMAND_DONE) {
1290 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1291 /* we read nvram data in cpu order
1292 * but ethtool sees it as an array of bytes
07ba6af4
MS		 1293 * converting to big-endian will do the work
1294 */
de0c62db
DK		 1295 *ret_val = cpu_to_be32(val);
1296 rc = 0;
1297 break;
1298 }
1299 }
51c1a580
MS		 1300 if (rc == -EBUSY)
1301 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1302 "nvram read timeout expired\n");
de0c62db
DK		 1303 return rc;
1304}
1305
1306static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1307 int buf_size)
1308{
1309 int rc;
1310 u32 cmd_flags;
1311 __be32 val;
1312
1313 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1314 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1315 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1316 offset, buf_size);
1317 return -EINVAL;
1318 }
1319
1320 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1321 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1322 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1323 offset, buf_size, bp->common.flash_size);
1324 return -EINVAL;
1325 }
1326
1327 /* request access to nvram interface */
1328 rc = bnx2x_acquire_nvram_lock(bp);
1329 if (rc)
1330 return rc;
1331
1332 /* enable access to nvram interface */
1333 bnx2x_enable_nvram_access(bp);
1334
1335 /* read the first word(s) */
1336 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1337 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1338 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1339 memcpy(ret_buf, &val, 4);
1340
1341 /* advance to the next dword */
1342 offset += sizeof(u32);
1343 ret_buf += sizeof(u32);
1344 buf_size -= sizeof(u32);
1345 cmd_flags = 0;
1346 }
1347
1348 if (rc == 0) {
1349 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1350 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1351 memcpy(ret_buf, &val, 4);
1352 }
1353
1354 /* disable access to nvram interface */
1355 bnx2x_disable_nvram_access(bp);
1356 bnx2x_release_nvram_lock(bp);
1357
1358 return rc;
1359}
1360
1361static int bnx2x_get_eeprom(struct net_device *dev,
1362 struct ethtool_eeprom *eeprom, u8 *eebuf)
1363{
1364 struct bnx2x *bp = netdev_priv(dev);
1365 int rc;
1366
51c1a580
MS		 1367 if (!netif_running(dev)) {
1368 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1369 "cannot access eeprom when the interface is down\n");
de0c62db 1370 return -EAGAIN;
51c1a580 1371 }
de0c62db 1372
51c1a580 1373 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1374 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1375 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1376 eeprom->len, eeprom->len);
1377
1378 /* parameters already validated in ethtool_get_eeprom */
1379
1380 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1381
1382 return rc;
1383}
1384
24ea818e
YM		 1385static int bnx2x_get_module_eeprom(struct net_device *dev,
1386 struct ethtool_eeprom *ee,
1387 u8 *data)
1388{
1389 struct bnx2x *bp = netdev_priv(dev);
1390 int rc = 0, phy_idx;
1391 u8 *user_data = data;
1392 int remaining_len = ee->len, xfer_size;
1393 unsigned int page_off = ee->offset;
1394
1395 if (!netif_running(dev)) {
1396 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1397 "cannot access eeprom when the interface is down\n");
1398 return -EAGAIN;
1399 }
1400
1401 phy_idx = bnx2x_get_cur_phy_idx(bp);
1402 bnx2x_acquire_phy_lock(bp);
1403 while (!rc && remaining_len > 0) {
1404 xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ?
1405 SFP_EEPROM_PAGE_SIZE : remaining_len;
1406 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1407 &bp->link_params,
1408 page_off,
1409 xfer_size,
1410 user_data);
1411 remaining_len -= xfer_size;
1412 user_data += xfer_size;
1413 page_off += xfer_size;
1414 }
1415
1416 bnx2x_release_phy_lock(bp);
1417 return rc;
1418}
1419
1420static int bnx2x_get_module_info(struct net_device *dev,
1421 struct ethtool_modinfo *modinfo)
1422{
1423 struct bnx2x *bp = netdev_priv(dev);
1424 int phy_idx;
1425 if (!netif_running(dev)) {
1426 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1427 "cannot access eeprom when the interface is down\n");
1428 return -EAGAIN;
1429 }
1430
1431 phy_idx = bnx2x_get_cur_phy_idx(bp);
1432 switch (bp->link_params.phy[phy_idx].media_type) {
1433 case ETH_PHY_SFPP_10G_FIBER:
1434 case ETH_PHY_SFP_1G_FIBER:
1435 case ETH_PHY_DA_TWINAX:
1436 modinfo->type = ETH_MODULE_SFF_8079;
1437 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1438 return 0;
1439 default:
1440 return -EOPNOTSUPP;
1441 }
1442}
1443
de0c62db
DK		 1444static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1445 u32 cmd_flags)
1446{
1447 int count, i, rc;
1448
1449 /* build the command word */
1450 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1451
1452 /* need to clear DONE bit separately */
1453 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1454
1455 /* write the data */
1456 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1457
1458 /* address of the NVRAM to write to */
1459 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1460 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1461
1462 /* issue the write command */
1463 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1464
1465 /* adjust timeout for emulation/FPGA */
754a2f52 1466 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1467 if (CHIP_REV_IS_SLOW(bp))
1468 count *= 100;
1469
1470 /* wait for completion */
1471 rc = -EBUSY;
1472 for (i = 0; i < count; i++) {
1473 udelay(5);
1474 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1475 if (val & MCPR_NVM_COMMAND_DONE) {
1476 rc = 0;
1477 break;
1478 }
1479 }
1480
51c1a580
MS		 1481 if (rc == -EBUSY)
1482 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1483 "nvram write timeout expired\n");
de0c62db
DK		 1484 return rc;
1485}
1486
1487#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1488
1489static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1490 int buf_size)
1491{
1492 int rc;
1493 u32 cmd_flags;
1494 u32 align_offset;
1495 __be32 val;
1496
1497 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1498 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1499 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1500 offset, buf_size, bp->common.flash_size);
1501 return -EINVAL;
1502 }
1503
1504 /* request access to nvram interface */
1505 rc = bnx2x_acquire_nvram_lock(bp);
1506 if (rc)
1507 return rc;
1508
1509 /* enable access to nvram interface */
1510 bnx2x_enable_nvram_access(bp);
1511
1512 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1513 align_offset = (offset & ~0x03);
1514 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1515
1516 if (rc == 0) {
1517 val &= ~(0xff << BYTE_OFFSET(offset));
1518 val |= (*data_buf << BYTE_OFFSET(offset));
1519
1520 /* nvram data is returned as an array of bytes
07ba6af4
MS		 1521 * convert it back to cpu order
1522 */
de0c62db
DK		 1523 val = be32_to_cpu(val);
1524
1525 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1526 cmd_flags);
1527 }
1528
1529 /* disable access to nvram interface */
1530 bnx2x_disable_nvram_access(bp);
1531 bnx2x_release_nvram_lock(bp);
1532
1533 return rc;
1534}
1535
1536static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1537 int buf_size)
1538{
1539 int rc;
1540 u32 cmd_flags;
1541 u32 val;
1542 u32 written_so_far;
1543
1544 if (buf_size == 1) /* ethtool */
1545 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1546
1547 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1548 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1549 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1550 offset, buf_size);
1551 return -EINVAL;
1552 }
1553
1554 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1555 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1556 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1557 offset, buf_size, bp->common.flash_size);
1558 return -EINVAL;
1559 }
1560
1561 /* request access to nvram interface */
1562 rc = bnx2x_acquire_nvram_lock(bp);
1563 if (rc)
1564 return rc;
1565
1566 /* enable access to nvram interface */
1567 bnx2x_enable_nvram_access(bp);
1568
1569 written_so_far = 0;
1570 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1571 while ((written_so_far < buf_size) && (rc == 0)) {
1572 if (written_so_far == (buf_size - sizeof(u32)))
1573 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1574 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1575 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1576 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1577 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1578
1579 memcpy(&val, data_buf, 4);
1580
1581 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1582
1583 /* advance to the next dword */
1584 offset += sizeof(u32);
1585 data_buf += sizeof(u32);
1586 written_so_far += sizeof(u32);
1587 cmd_flags = 0;
1588 }
1589
1590 /* disable access to nvram interface */
1591 bnx2x_disable_nvram_access(bp);
1592 bnx2x_release_nvram_lock(bp);
1593
1594 return rc;
1595}
1596
1597static int bnx2x_set_eeprom(struct net_device *dev,
1598 struct ethtool_eeprom *eeprom, u8 *eebuf)
1599{
1600 struct bnx2x *bp = netdev_priv(dev);
1601 int port = BP_PORT(bp);
1602 int rc = 0;
e10bc84d 1603 u32 ext_phy_config;
51c1a580
MS		 1604 if (!netif_running(dev)) {
1605 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1606 "cannot access eeprom when the interface is down\n");
de0c62db 1607 return -EAGAIN;
51c1a580 1608 }
de0c62db 1609
51c1a580 1610 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1611 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1612 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1613 eeprom->len, eeprom->len);
1614
1615 /* parameters already validated in ethtool_set_eeprom */
1616
1617 /* PHY eeprom can be accessed only by the PMF */
1618 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
51c1a580
MS		 1619 !bp->port.pmf) {
1620 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1621 "wrong magic or interface is not pmf\n");
de0c62db 1622 return -EINVAL;
51c1a580 1623 }
de0c62db 1624
e10bc84d
YR		 1625 ext_phy_config =
1626 SHMEM_RD(bp,
1627 dev_info.port_hw_config[port].external_phy_config);
1628
de0c62db
DK		 1629 if (eeprom->magic == 0x50485950) {
1630 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1631 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1632
1633 bnx2x_acquire_phy_lock(bp);
1634 rc |= bnx2x_link_reset(&bp->link_params,
1635 &bp->link_vars, 0);
e10bc84d 1636 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1637 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1638 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1639 MISC_REGISTERS_GPIO_HIGH, port);
1640 bnx2x_release_phy_lock(bp);
1641 bnx2x_link_report(bp);
1642
1643 } else if (eeprom->magic == 0x50485952) {
1644 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1645 if (bp->state == BNX2X_STATE_OPEN) {
1646 bnx2x_acquire_phy_lock(bp);
1647 rc |= bnx2x_link_reset(&bp->link_params,
1648 &bp->link_vars, 1);
1649
1650 rc |= bnx2x_phy_init(&bp->link_params,
1651 &bp->link_vars);
1652 bnx2x_release_phy_lock(bp);
1653 bnx2x_calc_fc_adv(bp);
1654 }
1655 } else if (eeprom->magic == 0x53985943) {
1656 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1657 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1658 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1659
1660 /* DSP Remove Download Mode */
1661 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1662 MISC_REGISTERS_GPIO_LOW, port);
1663
1664 bnx2x_acquire_phy_lock(bp);
1665
e10bc84d
YR		 1666 bnx2x_sfx7101_sp_sw_reset(bp,
1667 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1668
1669 /* wait 0.5 sec to allow it to run */
1670 msleep(500);
1671 bnx2x_ext_phy_hw_reset(bp, port);
1672 msleep(500);
1673 bnx2x_release_phy_lock(bp);
1674 }
1675 } else
1676 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1677
1678 return rc;
1679}
f85582f8 1680
de0c62db
DK		 1681static int bnx2x_get_coalesce(struct net_device *dev,
1682 struct ethtool_coalesce *coal)
1683{
1684 struct bnx2x *bp = netdev_priv(dev);
1685
1686 memset(coal, 0, sizeof(struct ethtool_coalesce));
1687
1688 coal->rx_coalesce_usecs = bp->rx_ticks;
1689 coal->tx_coalesce_usecs = bp->tx_ticks;
1690
1691 return 0;
1692}
1693
1694static int bnx2x_set_coalesce(struct net_device *dev,
1695 struct ethtool_coalesce *coal)
1696{
1697 struct bnx2x *bp = netdev_priv(dev);
1698
1699 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1700 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1701 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1702
1703 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1704 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1705 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1706
1707 if (netif_running(dev))
1708 bnx2x_update_coalesce(bp);
1709
1710 return 0;
1711}
1712
1713static void bnx2x_get_ringparam(struct net_device *dev,
1714 struct ethtool_ringparam *ering)
1715{
1716 struct bnx2x *bp = netdev_priv(dev);
1717
1718 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1719
25141580
DK		 1720 if (bp->rx_ring_size)
1721 ering->rx_pending = bp->rx_ring_size;
1722 else
c2188952 1723 ering->rx_pending = MAX_RX_AVAIL;
25141580 1724
a3348722 1725 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
de0c62db
DK		 1726 ering->tx_pending = bp->tx_ring_size;
1727}
1728
1729static int bnx2x_set_ringparam(struct net_device *dev,
1730 struct ethtool_ringparam *ering)
1731{
1732 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 1733
1734 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 1735 DP(BNX2X_MSG_ETHTOOL,
1736 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 1737 return -EAGAIN;
1738 }
1739
1740 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1741 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1742 MIN_RX_SIZE_TPA)) ||
a3348722 1743 (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
51c1a580
MS		 1744 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1745 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db 1746 return -EINVAL;
51c1a580 1747 }
de0c62db
DK		 1748
1749 bp->rx_ring_size = ering->rx_pending;
1750 bp->tx_ring_size = ering->tx_pending;
1751
a9fccec7 1752 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1753}
1754
1755static void bnx2x_get_pauseparam(struct net_device *dev,
1756 struct ethtool_pauseparam *epause)
1757{
1758 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1759 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1760 int cfg_reg;
1761
a22f0788
YR		 1762 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1763 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1764
9e7e8399 1765 if (!epause->autoneg)
241fb5d2 1766 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
9e7e8399
MY		 1767 else
1768 cfg_reg = bp->link_params.req_fc_auto_adv;
1769
1770 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1771 BNX2X_FLOW_CTRL_RX);
9e7e8399 1772 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1773 BNX2X_FLOW_CTRL_TX);
1774
51c1a580 1775 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1776 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1777 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1778}
1779
1780static int bnx2x_set_pauseparam(struct net_device *dev,
1781 struct ethtool_pauseparam *epause)
1782{
1783 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1784 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1785 if (IS_MF(bp))
de0c62db
DK		 1786 return 0;
1787
51c1a580 1788 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1789 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1790 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1791
a22f0788 1792 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1793
1794 if (epause->rx_pause)
a22f0788 1795 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1796
1797 if (epause->tx_pause)
a22f0788 1798 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1799
a22f0788
YR		 1800 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1801 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1802
1803 if (epause->autoneg) {
a22f0788 1804 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 1805 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
de0c62db
DK		 1806 return -EINVAL;
1807 }
1808
a22f0788
YR		 1809 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1810 bp->link_params.req_flow_ctrl[cfg_idx] =
1811 BNX2X_FLOW_CTRL_AUTO;
1812 }
5cd75f0c
YR		 1813 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE;
1814 if (epause->rx_pause)
1815 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1816
1817 if (epause->tx_pause)
1818 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
de0c62db
DK		 1819 }
1820
51c1a580 1821 DP(BNX2X_MSG_ETHTOOL,
a22f0788 1822 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1823
1824 if (netif_running(dev)) {
1825 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1826 bnx2x_link_set(bp);
1827 }
1828
1829 return 0;
1830}
1831
5889335c 1832static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
cf2c1df6
MS		 1833 "register_test (offline) ",
1834 "memory_test (offline) ",
1835 "int_loopback_test (offline)",
1836 "ext_loopback_test (offline)",
1837 "nvram_test (online) ",
1838 "interrupt_test (online) ",
1839 "link_test (online) "
de0c62db
DK		 1840};
1841
e9939c80
YM		 1842static u32 bnx2x_eee_to_adv(u32 eee_adv)
1843{
1844 u32 modes = 0;
1845
1846 if (eee_adv & SHMEM_EEE_100M_ADV)
1847 modes |= ADVERTISED_100baseT_Full;
1848 if (eee_adv & SHMEM_EEE_1G_ADV)
1849 modes |= ADVERTISED_1000baseT_Full;
1850 if (eee_adv & SHMEM_EEE_10G_ADV)
1851 modes |= ADVERTISED_10000baseT_Full;
1852
1853 return modes;
1854}
1855
1856static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1857{
1858 u32 eee_adv = 0;
1859 if (modes & ADVERTISED_100baseT_Full)
1860 eee_adv |= SHMEM_EEE_100M_ADV;
1861 if (modes & ADVERTISED_1000baseT_Full)
1862 eee_adv |= SHMEM_EEE_1G_ADV;
1863 if (modes & ADVERTISED_10000baseT_Full)
1864 eee_adv |= SHMEM_EEE_10G_ADV;
1865
1866 return eee_adv << shift;
1867}
1868
1869static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1870{
1871 struct bnx2x *bp = netdev_priv(dev);
1872 u32 eee_cfg;
1873
1874 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1875 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1876 return -EOPNOTSUPP;
1877 }
1878
08e9acc2 1879 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 1880
1881 edata->supported =
1882 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1883 SHMEM_EEE_SUPPORTED_SHIFT);
1884
1885 edata->advertised =
1886 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1887 SHMEM_EEE_ADV_STATUS_SHIFT);
1888 edata->lp_advertised =
1889 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1890 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1891
1892 /* SHMEM value is in 16u units --> Convert to 1u units. */
1893 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1894
1895 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
1896 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
1897 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1898
1899 return 0;
1900}
1901
1902static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1903{
1904 struct bnx2x *bp = netdev_priv(dev);
1905 u32 eee_cfg;
1906 u32 advertised;
1907
1908 if (IS_MF(bp))
1909 return 0;
1910
1911 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1912 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1913 return -EOPNOTSUPP;
1914 }
1915
08e9acc2 1916 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 1917
1918 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1919 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1920 return -EOPNOTSUPP;
1921 }
1922
1923 advertised = bnx2x_adv_to_eee(edata->advertised,
1924 SHMEM_EEE_ADV_STATUS_SHIFT);
1925 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1926 DP(BNX2X_MSG_ETHTOOL,
efc7ce03 1927 "Direct manipulation of EEE advertisement is not supported\n");
e9939c80
YM		 1928 return -EINVAL;
1929 }
1930
1931 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1932 DP(BNX2X_MSG_ETHTOOL,
1933 "Maximal Tx Lpi timer supported is %x(u)\n",
1934 EEE_MODE_TIMER_MASK);
1935 return -EINVAL;
1936 }
1937 if (edata->tx_lpi_enabled &&
1938 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1939 DP(BNX2X_MSG_ETHTOOL,
1940 "Minimal Tx Lpi timer supported is %d(u)\n",
1941 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1942 return -EINVAL;
1943 }
1944
1945 /* All is well; Apply changes*/
1946 if (edata->eee_enabled)
1947 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1948 else
1949 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1950
1951 if (edata->tx_lpi_enabled)
1952 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1953 else
1954 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1955
1956 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1957 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1958 EEE_MODE_TIMER_MASK) |
1959 EEE_MODE_OVERRIDE_NVRAM |
1960 EEE_MODE_OUTPUT_TIME;
1961
1962 /* Restart link to propogate changes */
1963 if (netif_running(dev)) {
1964 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 1965 bnx2x_force_link_reset(bp);
e9939c80
YM		 1966 bnx2x_link_set(bp);
1967 }
1968
1969 return 0;
1970}
1971
619c5cb6
VZ		 1972enum {
1973 BNX2X_CHIP_E1_OFST = 0,
1974 BNX2X_CHIP_E1H_OFST,
1975 BNX2X_CHIP_E2_OFST,
1976 BNX2X_CHIP_E3_OFST,
1977 BNX2X_CHIP_E3B0_OFST,
1978 BNX2X_CHIP_MAX_OFST
1979};
1980
1981#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1982#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1983#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1984#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1985#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1986
1987#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1988#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1989
de0c62db
DK		 1990static int bnx2x_test_registers(struct bnx2x *bp)
1991{
1992 int idx, i, rc = -ENODEV;
619c5cb6 1993 u32 wr_val = 0, hw;
de0c62db
DK		 1994 int port = BP_PORT(bp);
1995 static const struct {
619c5cb6 1996 u32 hw;
de0c62db
DK		 1997 u32 offset0;
1998 u32 offset1;
1999 u32 mask;
2000 } reg_tbl[] = {
619c5cb6
VZ		 2001/* 0 */ { BNX2X_CHIP_MASK_ALL,
2002 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2003 { BNX2X_CHIP_MASK_ALL,
2004 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2005 { BNX2X_CHIP_MASK_E1X,
2006 HC_REG_AGG_INT_0, 4, 0x000003ff },
2007 { BNX2X_CHIP_MASK_ALL,
2008 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2009 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2010 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2011 { BNX2X_CHIP_MASK_E3B0,
2012 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2013 { BNX2X_CHIP_MASK_ALL,
2014 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2015 { BNX2X_CHIP_MASK_ALL,
2016 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2017 { BNX2X_CHIP_MASK_ALL,
2018 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2019 { BNX2X_CHIP_MASK_ALL,
2020 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2021/* 10 */ { BNX2X_CHIP_MASK_ALL,
2022 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2023 { BNX2X_CHIP_MASK_ALL,
2024 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2025 { BNX2X_CHIP_MASK_ALL,
2026 QM_REG_CONNNUM_0, 4, 0x000fffff },
2027 { BNX2X_CHIP_MASK_ALL,
2028 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2029 { BNX2X_CHIP_MASK_ALL,
2030 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2031 { BNX2X_CHIP_MASK_ALL,
2032 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2033 { BNX2X_CHIP_MASK_ALL,
2034 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2035 { BNX2X_CHIP_MASK_ALL,
2036 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2037 { BNX2X_CHIP_MASK_ALL,
2038 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2039 { BNX2X_CHIP_MASK_ALL,
2040 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2041/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2042 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2043 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2044 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2045 { BNX2X_CHIP_MASK_ALL,
2046 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2047 { BNX2X_CHIP_MASK_ALL,
2048 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2049 { BNX2X_CHIP_MASK_ALL,
2050 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2051 { BNX2X_CHIP_MASK_ALL,
2052 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2053 { BNX2X_CHIP_MASK_ALL,
2054 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2055 { BNX2X_CHIP_MASK_ALL,
2056 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2057 { BNX2X_CHIP_MASK_ALL,
2058 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2059 { BNX2X_CHIP_MASK_ALL,
2060 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2061/* 30 */ { BNX2X_CHIP_MASK_ALL,
2062 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2063 { BNX2X_CHIP_MASK_ALL,
2064 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2065 { BNX2X_CHIP_MASK_ALL,
2066 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2067 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2068 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2069 { BNX2X_CHIP_MASK_ALL,
2070 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2071 { BNX2X_CHIP_MASK_ALL,
2072 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2073 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2074 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2075 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2076 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2077
2078 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 2079 };
2080
51c1a580
MS		 2081 if (!netif_running(bp->dev)) {
2082 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2083 "cannot access eeprom when the interface is down\n");
de0c62db 2084 return rc;
51c1a580 2085 }
de0c62db 2086
619c5cb6
VZ		 2087 if (CHIP_IS_E1(bp))
2088 hw = BNX2X_CHIP_MASK_E1;
2089 else if (CHIP_IS_E1H(bp))
2090 hw = BNX2X_CHIP_MASK_E1H;
2091 else if (CHIP_IS_E2(bp))
2092 hw = BNX2X_CHIP_MASK_E2;
2093 else if (CHIP_IS_E3B0(bp))
2094 hw = BNX2X_CHIP_MASK_E3B0;
2095 else /* e3 A0 */
2096 hw = BNX2X_CHIP_MASK_E3;
2097
de0c62db 2098 /* Repeat the test twice:
07ba6af4
MS		 2099 * First by writing 0x00000000, second by writing 0xffffffff
2100 */
de0c62db
DK		 2101 for (idx = 0; idx < 2; idx++) {
2102
2103 switch (idx) {
2104 case 0:
2105 wr_val = 0;
2106 break;
2107 case 1:
2108 wr_val = 0xffffffff;
2109 break;
2110 }
2111
2112 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2113 u32 offset, mask, save_val, val;
619c5cb6 2114 if (!(hw & reg_tbl[i].hw))
f2e0899f 2115 continue;
de0c62db
DK		 2116
2117 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2118 mask = reg_tbl[i].mask;
2119
2120 save_val = REG_RD(bp, offset);
2121
ec6ba945 2122 REG_WR(bp, offset, wr_val & mask);
f85582f8 2123
de0c62db
DK		 2124 val = REG_RD(bp, offset);
2125
2126 /* Restore the original register's value */
2127 REG_WR(bp, offset, save_val);
2128
2129 /* verify value is as expected */
2130 if ((val & mask) != (wr_val & mask)) {
51c1a580 2131 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 2132 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2133 offset, val, wr_val, mask);
2134 goto test_reg_exit;
2135 }
2136 }
2137 }
2138
2139 rc = 0;
2140
2141test_reg_exit:
2142 return rc;
2143}
2144
2145static int bnx2x_test_memory(struct bnx2x *bp)
2146{
2147 int i, j, rc = -ENODEV;
619c5cb6 2148 u32 val, index;
de0c62db
DK		 2149 static const struct {
2150 u32 offset;
2151 int size;
2152 } mem_tbl[] = {
2153 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2154 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2155 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2156 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2157 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2158 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2159 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2160
2161 { 0xffffffff, 0 }
2162 };
619c5cb6 2163
de0c62db
DK		 2164 static const struct {
2165 char *name;
2166 u32 offset;
619c5cb6 2167 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 2168 } prty_tbl[] = {
619c5cb6
VZ		 2169 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2170 {0x3ffc0, 0, 0, 0} },
2171 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2172 {0x2, 0x2, 0, 0} },
2173 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2174 {0, 0, 0, 0} },
2175 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2176 {0x3ffc0, 0, 0, 0} },
2177 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2178 {0x3ffc0, 0, 0, 0} },
2179 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2180 {0x3ffc1, 0, 0, 0} },
2181
2182 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 2183 };
2184
51c1a580
MS		 2185 if (!netif_running(bp->dev)) {
2186 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2187 "cannot access eeprom when the interface is down\n");
de0c62db 2188 return rc;
51c1a580 2189 }
de0c62db 2190
619c5cb6
VZ		 2191 if (CHIP_IS_E1(bp))
2192 index = BNX2X_CHIP_E1_OFST;
2193 else if (CHIP_IS_E1H(bp))
2194 index = BNX2X_CHIP_E1H_OFST;
2195 else if (CHIP_IS_E2(bp))
2196 index = BNX2X_CHIP_E2_OFST;
2197 else /* e3 */
2198 index = BNX2X_CHIP_E3_OFST;
2199
f2e0899f
DK		 2200 /* pre-Check the parity status */
2201 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2202 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 2203 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 2204 DP(BNX2X_MSG_ETHTOOL,
f2e0899f
DK		 2205 "%s is 0x%x\n", prty_tbl[i].name, val);
2206 goto test_mem_exit;
2207 }
2208 }
2209
de0c62db
DK		 2210 /* Go through all the memories */
2211 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2212 for (j = 0; j < mem_tbl[i].size; j++)
2213 REG_RD(bp, mem_tbl[i].offset + j*4);
2214
2215 /* Check the parity status */
2216 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2217 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 2218 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 2219 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 2220 "%s is 0x%x\n", prty_tbl[i].name, val);
2221 goto test_mem_exit;
2222 }
2223 }
2224
2225 rc = 0;
2226
2227test_mem_exit:
2228 return rc;
2229}
2230
a22f0788 2231static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 2232{
f2e0899f 2233 int cnt = 1400;
de0c62db 2234
619c5cb6 2235 if (link_up) {
a22f0788 2236 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 2237 msleep(20);
2238
2239 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
51c1a580 2240 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
8970b2e4
MS		 2241
2242 cnt = 1400;
2243 while (!bp->link_vars.link_up && cnt--)
2244 msleep(20);
2245
2246 if (cnt <= 0 && !bp->link_vars.link_up)
2247 DP(BNX2X_MSG_ETHTOOL,
2248 "Timeout waiting for link init\n");
619c5cb6 2249 }
de0c62db
DK		 2250}
2251
619c5cb6 2252static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 2253{
2254 unsigned int pkt_size, num_pkts, i;
2255 struct sk_buff *skb;
2256 unsigned char *packet;
2257 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2258 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
65565884 2259 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
de0c62db
DK		 2260 u16 tx_start_idx, tx_idx;
2261 u16 rx_start_idx, rx_idx;
b0700b1e 2262 u16 pkt_prod, bd_prod;
de0c62db
DK		 2263 struct sw_tx_bd *tx_buf;
2264 struct eth_tx_start_bd *tx_start_bd;
de0c62db
DK		 2265 dma_addr_t mapping;
2266 union eth_rx_cqe *cqe;
619c5cb6 2267 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 2268 struct sw_rx_bd *rx_buf;
2269 u16 len;
2270 int rc = -ENODEV;
e52fcb24 2271 u8 *data;
8970b2e4
MS		 2272 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2273 txdata->txq_index);
de0c62db
DK		 2274
2275 /* check the loopback mode */
2276 switch (loopback_mode) {
2277 case BNX2X_PHY_LOOPBACK:
8970b2e4
MS		 2278 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2279 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
de0c62db 2280 return -EINVAL;
8970b2e4 2281 }
de0c62db
DK		 2282 break;
2283 case BNX2X_MAC_LOOPBACK:
32911333
YR		 2284 if (CHIP_IS_E3(bp)) {
2285 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2286 if (bp->port.supported[cfg_idx] &
2287 (SUPPORTED_10000baseT_Full |
2288 SUPPORTED_20000baseMLD2_Full |
2289 SUPPORTED_20000baseKR2_Full))
2290 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2291 else
2292 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2293 } else
2294 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2295
de0c62db
DK		 2296 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2297 break;
8970b2e4
MS		 2298 case BNX2X_EXT_LOOPBACK:
2299 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2300 DP(BNX2X_MSG_ETHTOOL,
2301 "Can't configure external loopback\n");
2302 return -EINVAL;
2303 }
2304 break;
de0c62db 2305 default:
51c1a580 2306 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db
DK		 2307 return -EINVAL;
2308 }
2309
2310 /* prepare the loopback packet */
2311 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2312 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 2313 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db 2314 if (!skb) {
51c1a580 2315 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
de0c62db
DK		 2316 rc = -ENOMEM;
2317 goto test_loopback_exit;
2318 }
2319 packet = skb_put(skb, pkt_size);
2320 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2321 memset(packet + ETH_ALEN, 0, ETH_ALEN);
2322 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2323 for (i = ETH_HLEN; i < pkt_size; i++)
2324 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 2325 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2326 skb_headlen(skb), DMA_TO_DEVICE);
2327 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2328 rc = -ENOMEM;
2329 dev_kfree_skb(skb);
51c1a580 2330 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
619c5cb6
VZ		 2331 goto test_loopback_exit;
2332 }
de0c62db
DK		 2333
2334 /* send the loopback packet */
2335 num_pkts = 0;
6383c0b3 2336 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2337 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2338
73dbb5e1
DK		 2339 netdev_tx_sent_queue(txq, skb->len);
2340
6383c0b3
AE		 2341 pkt_prod = txdata->tx_pkt_prod++;
2342 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2343 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 2344 tx_buf->skb = skb;
2345 tx_buf->flags = 0;
2346
6383c0b3
AE		 2347 bd_prod = TX_BD(txdata->tx_bd_prod);
2348 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 2349 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2350 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2351 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2352 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 2353 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 2354 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 2355 SET_FLAG(tx_start_bd->general_data,
2356 ETH_TX_START_BD_HDR_NBDS,
2357 1);
96bed4b9
YM		 2358 SET_FLAG(tx_start_bd->general_data,
2359 ETH_TX_START_BD_PARSE_NBDS,
2360 0);
de0c62db
DK		 2361
2362 /* turn on parsing and get a BD */
2363 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 2364
96bed4b9
YM		 2365 if (CHIP_IS_E1x(bp)) {
2366 u16 global_data = 0;
2367 struct eth_tx_parse_bd_e1x *pbd_e1x =
2368 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2369 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2370 SET_FLAG(global_data,
2371 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2372 pbd_e1x->global_data = cpu_to_le16(global_data);
2373 } else {
2374 u32 parsing_data = 0;
2375 struct eth_tx_parse_bd_e2 *pbd_e2 =
2376 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2377 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2378 SET_FLAG(parsing_data,
2379 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2380 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2381 }
de0c62db
DK		 2382 wmb();
2383
6383c0b3 2384 txdata->tx_db.data.prod += 2;
de0c62db 2385 barrier();
6383c0b3 2386 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 2387
2388 mmiowb();
619c5cb6 2389 barrier();
de0c62db
DK		 2390
2391 num_pkts++;
6383c0b3 2392 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 2393
2394 udelay(100);
2395
6383c0b3 2396 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2397 if (tx_idx != tx_start_idx + num_pkts)
2398 goto test_loopback_exit;
2399
f2e0899f
DK		 2400 /* Unlike HC IGU won't generate an interrupt for status block
2401 * updates that have been performed while interrupts were
2402 * disabled.
2403 */
e1210d12
ED		 2404 if (bp->common.int_block == INT_BLOCK_IGU) {
2405 /* Disable local BHes to prevent a dead-lock situation between
2406 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2407 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2408 */
2409 local_bh_disable();
6383c0b3 2410 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 2411 local_bh_enable();
2412 }
f2e0899f 2413
de0c62db
DK		 2414 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2415 if (rx_idx != rx_start_idx + num_pkts)
2416 goto test_loopback_exit;
2417
b0700b1e 2418 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 2419 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 2420 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2421 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 2422 goto test_loopback_rx_exit;
2423
621b4d66 2424 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
de0c62db
DK		 2425 if (len != pkt_size)
2426 goto test_loopback_rx_exit;
2427
2428 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 2429 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 2430 dma_unmap_addr(rx_buf, mapping),
2431 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 2432 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 2433 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 2434 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 2435 goto test_loopback_rx_exit;
2436
2437 rc = 0;
2438
2439test_loopback_rx_exit:
2440
2441 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2442 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2443 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2444 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2445
2446 /* Update producers */
2447 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2448 fp_rx->rx_sge_prod);
2449
2450test_loopback_exit:
2451 bp->link_params.loopback_mode = LOOPBACK_NONE;
2452
2453 return rc;
2454}
2455
619c5cb6 2456static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 2457{
2458 int rc = 0, res;
2459
2460 if (BP_NOMCP(bp))
2461 return rc;
2462
2463 if (!netif_running(bp->dev))
2464 return BNX2X_LOOPBACK_FAILED;
2465
2466 bnx2x_netif_stop(bp, 1);
2467 bnx2x_acquire_phy_lock(bp);
2468
619c5cb6 2469 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db 2470 if (res) {
51c1a580 2471 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
de0c62db
DK		 2472 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2473 }
2474
619c5cb6 2475 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db 2476 if (res) {
51c1a580 2477 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
de0c62db
DK		 2478 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2479 }
2480
2481 bnx2x_release_phy_lock(bp);
2482 bnx2x_netif_start(bp);
2483
2484 return rc;
2485}
2486
8970b2e4
MS		 2487static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2488{
2489 int rc;
2490 u8 is_serdes =
2491 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2492
2493 if (BP_NOMCP(bp))
2494 return -ENODEV;
2495
2496 if (!netif_running(bp->dev))
2497 return BNX2X_EXT_LOOPBACK_FAILED;
2498
5d07d868 2499 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
8970b2e4
MS		 2500 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2501 if (rc) {
2502 DP(BNX2X_MSG_ETHTOOL,
2503 "Can't perform self-test, nic_load (for external lb) failed\n");
2504 return -ENODEV;
2505 }
2506 bnx2x_wait_for_link(bp, 1, is_serdes);
2507
2508 bnx2x_netif_stop(bp, 1);
2509
2510 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2511 if (rc)
2512 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2513
2514 bnx2x_netif_start(bp);
2515
2516 return rc;
2517}
2518
de0c62db
DK		 2519#define CRC32_RESIDUAL 0xdebb20e3
2520
2521static int bnx2x_test_nvram(struct bnx2x *bp)
2522{
2523 static const struct {
2524 int offset;
2525 int size;
2526 } nvram_tbl[] = {
2527 { 0, 0x14 }, /* bootstrap */
2528 { 0x14, 0xec }, /* dir */
2529 { 0x100, 0x350 }, /* manuf_info */
2530 { 0x450, 0xf0 }, /* feature_info */
2531 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2532 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2533 { 0, 0 }
2534 };
afa13b4b
MY		 2535 __be32 *buf;
2536 u8 *data;
de0c62db
DK		 2537 int i, rc;
2538 u32 magic, crc;
2539
2540 if (BP_NOMCP(bp))
2541 return 0;
2542
afa13b4b
MY		 2543 buf = kmalloc(0x350, GFP_KERNEL);
2544 if (!buf) {
51c1a580 2545 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
afa13b4b
MY		 2546 rc = -ENOMEM;
2547 goto test_nvram_exit;
2548 }
2549 data = (u8 *)buf;
2550
de0c62db
DK		 2551 rc = bnx2x_nvram_read(bp, 0, data, 4);
2552 if (rc) {
51c1a580
MS		 2553 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2554 "magic value read (rc %d)\n", rc);
de0c62db
DK		 2555 goto test_nvram_exit;
2556 }
2557
2558 magic = be32_to_cpu(buf[0]);
2559 if (magic != 0x669955aa) {
51c1a580
MS		 2560 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2561 "wrong magic value (0x%08x)\n", magic);
de0c62db
DK		 2562 rc = -ENODEV;
2563 goto test_nvram_exit;
2564 }
2565
2566 for (i = 0; nvram_tbl[i].size; i++) {
2567
2568 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2569 nvram_tbl[i].size);
2570 if (rc) {
51c1a580 2571 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 2572 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2573 goto test_nvram_exit;
2574 }
2575
2576 crc = ether_crc_le(nvram_tbl[i].size, data);
2577 if (crc != CRC32_RESIDUAL) {
51c1a580
MS		 2578 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2579 "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
de0c62db
DK		 2580 rc = -ENODEV;
2581 goto test_nvram_exit;
2582 }
2583 }
2584
2585test_nvram_exit:
afa13b4b 2586 kfree(buf);
de0c62db
DK		 2587 return rc;
2588}
2589
619c5cb6 2590/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2591static int bnx2x_test_intr(struct bnx2x *bp)
2592{
3b603066 2593 struct bnx2x_queue_state_params params = {NULL};
de0c62db 2594
51c1a580
MS		 2595 if (!netif_running(bp->dev)) {
2596 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2597 "cannot access eeprom when the interface is down\n");
de0c62db 2598 return -ENODEV;
51c1a580 2599 }
de0c62db 2600
15192a8c 2601 params.q_obj = &bp->sp_objs->q_obj;
619c5cb6 2602 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2603
619c5cb6
VZ		 2604 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2605
2606 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2607}
2608
2609static void bnx2x_self_test(struct net_device *dev,
2610 struct ethtool_test *etest, u64 *buf)
2611{
2612 struct bnx2x *bp = netdev_priv(dev);
a336ca7c
YR		 2613 u8 is_serdes, link_up;
2614 int rc, cnt = 0;
cf2c1df6 2615
de0c62db 2616 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 2617 netdev_err(bp->dev,
2618 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 2619 etest->flags |= ETH_TEST_FL_FAILED;
2620 return;
2621 }
2de67439 2622
8970b2e4
MS		 2623 DP(BNX2X_MSG_ETHTOOL,
2624 "Self-test command parameters: offline = %d, external_lb = %d\n",
2625 (etest->flags & ETH_TEST_FL_OFFLINE),
2626 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
de0c62db 2627
cf2c1df6 2628 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
de0c62db 2629
cf2c1df6
MS		 2630 if (!netif_running(dev)) {
2631 DP(BNX2X_MSG_ETHTOOL,
2632 "Can't perform self-test when interface is down\n");
de0c62db 2633 return;
cf2c1df6 2634 }
de0c62db 2635
a22f0788 2636 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
a336ca7c 2637 link_up = bp->link_vars.link_up;
cf2c1df6
MS		 2638 /* offline tests are not supported in MF mode */
2639 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
de0c62db
DK		 2640 int port = BP_PORT(bp);
2641 u32 val;
de0c62db
DK		 2642
2643 /* save current value of input enable for TX port IF */
2644 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2645 /* disable input for TX port IF */
2646 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2647
5d07d868 2648 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
cf2c1df6
MS		 2649 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2650 if (rc) {
2651 etest->flags |= ETH_TEST_FL_FAILED;
2652 DP(BNX2X_MSG_ETHTOOL,
2653 "Can't perform self-test, nic_load (for offline) failed\n");
2654 return;
2655 }
2656
de0c62db 2657 /* wait until link state is restored */
619c5cb6 2658 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2659
2660 if (bnx2x_test_registers(bp) != 0) {
2661 buf[0] = 1;
2662 etest->flags |= ETH_TEST_FL_FAILED;
2663 }
2664 if (bnx2x_test_memory(bp) != 0) {
2665 buf[1] = 1;
2666 etest->flags |= ETH_TEST_FL_FAILED;
2667 }
f85582f8 2668
8970b2e4 2669 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
de0c62db
DK		 2670 if (buf[2] != 0)
2671 etest->flags |= ETH_TEST_FL_FAILED;
2672
8970b2e4
MS		 2673 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2674 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2675 if (buf[3] != 0)
2676 etest->flags |= ETH_TEST_FL_FAILED;
2677 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2678 }
2679
5d07d868 2680 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
de0c62db
DK		 2681
2682 /* restore input for TX port IF */
2683 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
cf2c1df6
MS		 2684 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2685 if (rc) {
2686 etest->flags |= ETH_TEST_FL_FAILED;
2687 DP(BNX2X_MSG_ETHTOOL,
2688 "Can't perform self-test, nic_load (for online) failed\n");
2689 return;
2690 }
de0c62db 2691 /* wait until link state is restored */
a22f0788 2692 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2693 }
2694 if (bnx2x_test_nvram(bp) != 0) {
cf2c1df6
MS		 2695 if (!IS_MF(bp))
2696 buf[4] = 1;
2697 else
2698 buf[0] = 1;
de0c62db
DK		 2699 etest->flags |= ETH_TEST_FL_FAILED;
2700 }
2701 if (bnx2x_test_intr(bp) != 0) {
cf2c1df6
MS		 2702 if (!IS_MF(bp))
2703 buf[5] = 1;
2704 else
2705 buf[1] = 1;
de0c62db
DK		 2706 etest->flags |= ETH_TEST_FL_FAILED;
2707 }
633ac363 2708
a336ca7c
YR		 2709 if (link_up) {
2710 cnt = 100;
2711 while (bnx2x_link_test(bp, is_serdes) && --cnt)
2712 msleep(20);
2713 }
2714
2715 if (!cnt) {
cf2c1df6
MS		 2716 if (!IS_MF(bp))
2717 buf[6] = 1;
2718 else
2719 buf[2] = 1;
633ac363
DK		 2720 etest->flags |= ETH_TEST_FL_FAILED;
2721 }
de0c62db
DK		 2722}
2723
de0c62db
DK		 2724#define IS_PORT_STAT(i) \
2725 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2726#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2727#define IS_MF_MODE_STAT(bp) \
2728 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2729
619c5cb6
VZ		 2730/* ethtool statistics are displayed for all regular ethernet queues and the
2731 * fcoe L2 queue if not disabled
2732 */
1191cb83 2733static int bnx2x_num_stat_queues(struct bnx2x *bp)
619c5cb6
VZ		 2734{
2735 return BNX2X_NUM_ETH_QUEUES(bp);
2736}
2737
de0c62db
DK		 2738static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2739{
2740 struct bnx2x *bp = netdev_priv(dev);
2741 int i, num_stats;
2742
2743 switch (stringset) {
2744 case ETH_SS_STATS:
2745 if (is_multi(bp)) {
619c5cb6 2746 num_stats = bnx2x_num_stat_queues(bp) *
d5e83632
YM		 2747 BNX2X_NUM_Q_STATS;
2748 } else
2749 num_stats = 0;
2750 if (IS_MF_MODE_STAT(bp)) {
2751 for (i = 0; i < BNX2X_NUM_STATS; i++)
2752 if (IS_FUNC_STAT(i))
2753 num_stats++;
2754 } else
2755 num_stats += BNX2X_NUM_STATS;
2756
de0c62db
DK		 2757 return num_stats;
2758
2759 case ETH_SS_TEST:
cf2c1df6 2760 return BNX2X_NUM_TESTS(bp);
de0c62db
DK		 2761
2762 default:
2763 return -EINVAL;
2764 }
2765}
2766
2767static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2768{
2769 struct bnx2x *bp = netdev_priv(dev);
5889335c 2770 int i, j, k, start;
ec6ba945 2771 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2772
2773 switch (stringset) {
2774 case ETH_SS_STATS:
d5e83632 2775 k = 0;
de0c62db 2776 if (is_multi(bp)) {
619c5cb6 2777 for_each_eth_queue(bp, i) {
ec6ba945 2778 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2779 sprintf(queue_name, "%d", i);
de0c62db 2780 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2781 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2782 ETH_GSTRING_LEN,
2783 bnx2x_q_stats_arr[j].string,
2784 queue_name);
de0c62db
DK		 2785 k += BNX2X_NUM_Q_STATS;
2786 }
de0c62db 2787 }
d5e83632
YM		 2788
2789
2790 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2791 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2792 continue;
2793 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2794 bnx2x_stats_arr[i].string);
2795 j++;
2796 }
2797
de0c62db
DK		 2798 break;
2799
2800 case ETH_SS_TEST:
cf2c1df6
MS		 2801 /* First 4 tests cannot be done in MF mode */
2802 if (!IS_MF(bp))
2803 start = 0;
2804 else
2805 start = 4;
5889335c
MS		 2806 memcpy(buf, bnx2x_tests_str_arr + start,
2807 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
de0c62db
DK		 2808 }
2809}
2810
2811static void bnx2x_get_ethtool_stats(struct net_device *dev,
2812 struct ethtool_stats *stats, u64 *buf)
2813{
2814 struct bnx2x *bp = netdev_priv(dev);
2815 u32 *hw_stats, *offset;
d5e83632 2816 int i, j, k = 0;
de0c62db
DK		 2817
2818 if (is_multi(bp)) {
619c5cb6 2819 for_each_eth_queue(bp, i) {
15192a8c 2820 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
de0c62db
DK		 2821 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2822 if (bnx2x_q_stats_arr[j].size == 0) {
2823 /* skip this counter */
2824 buf[k + j] = 0;
2825 continue;
2826 }
2827 offset = (hw_stats +
2828 bnx2x_q_stats_arr[j].offset);
2829 if (bnx2x_q_stats_arr[j].size == 4) {
2830 /* 4-byte counter */
2831 buf[k + j] = (u64) *offset;
2832 continue;
2833 }
2834 /* 8-byte counter */
2835 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2836 }
2837 k += BNX2X_NUM_Q_STATS;
2838 }
d5e83632
YM		 2839 }
2840
2841 hw_stats = (u32 *)&bp->eth_stats;
2842 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2843 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2844 continue;
2845 if (bnx2x_stats_arr[i].size == 0) {
2846 /* skip this counter */
2847 buf[k + j] = 0;
2848 j++;
2849 continue;
de0c62db 2850 }
d5e83632
YM		 2851 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2852 if (bnx2x_stats_arr[i].size == 4) {
2853 /* 4-byte counter */
2854 buf[k + j] = (u64) *offset;
de0c62db 2855 j++;
d5e83632 2856 continue;
de0c62db 2857 }
d5e83632
YM		 2858 /* 8-byte counter */
2859 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2860 j++;
de0c62db
DK		 2861 }
2862}
2863
32d36134 2864static int bnx2x_set_phys_id(struct net_device *dev,
2865 enum ethtool_phys_id_state state)
de0c62db
DK		 2866{
2867 struct bnx2x *bp = netdev_priv(dev);
de0c62db 2868
51c1a580
MS		 2869 if (!netif_running(dev)) {
2870 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2871 "cannot access eeprom when the interface is down\n");
32d36134 2872 return -EAGAIN;
51c1a580 2873 }
de0c62db 2874
51c1a580
MS		 2875 if (!bp->port.pmf) {
2876 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
32d36134 2877 return -EOPNOTSUPP;
51c1a580 2878 }
de0c62db 2879
32d36134 2880 switch (state) {
2881 case ETHTOOL_ID_ACTIVE:
fce55922 2882 return 1; /* cycle on/off once per second */
de0c62db 2883
32d36134 2884 case ETHTOOL_ID_ON:
8203c4b6 2885 bnx2x_acquire_phy_lock(bp);
32d36134 2886 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2887 LED_MODE_ON, SPEED_1000);
8203c4b6 2888 bnx2x_release_phy_lock(bp);
32d36134 2889 break;
de0c62db 2890
32d36134 2891 case ETHTOOL_ID_OFF:
8203c4b6 2892 bnx2x_acquire_phy_lock(bp);
32d36134 2893 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2894 LED_MODE_FRONT_PANEL_OFF, 0);
8203c4b6 2895 bnx2x_release_phy_lock(bp);
32d36134 2896 break;
2897
2898 case ETHTOOL_ID_INACTIVE:
8203c4b6 2899 bnx2x_acquire_phy_lock(bp);
e1943424
DM		 2900 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2901 LED_MODE_OPER,
2902 bp->link_vars.line_speed);
8203c4b6 2903 bnx2x_release_phy_lock(bp);
32d36134 2904 }
de0c62db
DK		 2905
2906 return 0;
2907}
2908
5d317c6a
MS		 2909static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2910{
2911
2912 switch (info->flow_type) {
2913 case TCP_V4_FLOW:
2914 case TCP_V6_FLOW:
2915 info->data = RXH_IP_SRC | RXH_IP_DST |
2916 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2917 break;
2918 case UDP_V4_FLOW:
2919 if (bp->rss_conf_obj.udp_rss_v4)
2920 info->data = RXH_IP_SRC | RXH_IP_DST |
2921 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2922 else
2923 info->data = RXH_IP_SRC | RXH_IP_DST;
2924 break;
2925 case UDP_V6_FLOW:
2926 if (bp->rss_conf_obj.udp_rss_v6)
2927 info->data = RXH_IP_SRC | RXH_IP_DST |
2928 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2929 else
2930 info->data = RXH_IP_SRC | RXH_IP_DST;
2931 break;
2932 case IPV4_FLOW:
2933 case IPV6_FLOW:
2934 info->data = RXH_IP_SRC | RXH_IP_DST;
2935 break;
2936 default:
2937 info->data = 0;
2938 break;
2939 }
2940
2941 return 0;
2942}
2943
ab532cf3 2944static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2945 u32 *rules __always_unused)
ab532cf3
TH		 2946{
2947 struct bnx2x *bp = netdev_priv(dev);
2948
2949 switch (info->cmd) {
2950 case ETHTOOL_GRXRINGS:
2951 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2952 return 0;
5d317c6a
MS		 2953 case ETHTOOL_GRXFH:
2954 return bnx2x_get_rss_flags(bp, info);
2955 default:
2956 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2957 return -EOPNOTSUPP;
2958 }
2959}
2960
2961static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2962{
2963 int udp_rss_requested;
2964
2965 DP(BNX2X_MSG_ETHTOOL,
2966 "Set rss flags command parameters: flow type = %d, data = %llu\n",
2967 info->flow_type, info->data);
2968
2969 switch (info->flow_type) {
2970 case TCP_V4_FLOW:
2971 case TCP_V6_FLOW:
2972 /* For TCP only 4-tupple hash is supported */
2973 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
2974 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2975 DP(BNX2X_MSG_ETHTOOL,
2976 "Command parameters not supported\n");
2977 return -EINVAL;
5d317c6a 2978 }
2de67439 2979 return 0;
5d317c6a
MS		 2980
2981 case UDP_V4_FLOW:
2982 case UDP_V6_FLOW:
2983 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
2984 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2de67439 2985 RXH_L4_B_0_1 | RXH_L4_B_2_3))
5d317c6a
MS		 2986 udp_rss_requested = 1;
2987 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
2988 udp_rss_requested = 0;
2989 else
2990 return -EINVAL;
2991 if ((info->flow_type == UDP_V4_FLOW) &&
2992 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
2993 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
2994 DP(BNX2X_MSG_ETHTOOL,
2995 "rss re-configured, UDP 4-tupple %s\n",
2996 udp_rss_requested ? "enabled" : "disabled");
2997 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2998 } else if ((info->flow_type == UDP_V6_FLOW) &&
2999 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3000 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
5d317c6a
MS		 3001 DP(BNX2X_MSG_ETHTOOL,
3002 "rss re-configured, UDP 4-tupple %s\n",
3003 udp_rss_requested ? "enabled" : "disabled");
337da3e3 3004 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
5d317c6a
MS		 3005 } else {
3006 return 0;
3007 }
3008 case IPV4_FLOW:
3009 case IPV6_FLOW:
3010 /* For IP only 2-tupple hash is supported */
3011 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3012 DP(BNX2X_MSG_ETHTOOL,
3013 "Command parameters not supported\n");
3014 return -EINVAL;
3015 } else {
3016 return 0;
3017 }
3018 case SCTP_V4_FLOW:
3019 case AH_ESP_V4_FLOW:
3020 case AH_V4_FLOW:
3021 case ESP_V4_FLOW:
3022 case SCTP_V6_FLOW:
3023 case AH_ESP_V6_FLOW:
3024 case AH_V6_FLOW:
3025 case ESP_V6_FLOW:
3026 case IP_USER_FLOW:
3027 case ETHER_FLOW:
3028 /* RSS is not supported for these protocols */
3029 if (info->data) {
3030 DP(BNX2X_MSG_ETHTOOL,
3031 "Command parameters not supported\n");
3032 return -EINVAL;
3033 } else {
3034 return 0;
3035 }
3036 default:
3037 return -EINVAL;
3038 }
3039}
3040
3041static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3042{
3043 struct bnx2x *bp = netdev_priv(dev);
ab532cf3 3044
5d317c6a
MS		 3045 switch (info->cmd) {
3046 case ETHTOOL_SRXFH:
3047 return bnx2x_set_rss_flags(bp, info);
ab532cf3 3048 default:
51c1a580 3049 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
ab532cf3
TH		 3050 return -EOPNOTSUPP;
3051 }
3052}
3053
7850f63f
BH		 3054static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3055{
96305234 3056 return T_ETH_INDIRECTION_TABLE_SIZE;
7850f63f
BH		 3057}
3058
3059static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
ab532cf3
TH		 3060{
3061 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 3062 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3063 size_t i;
ab532cf3 3064
619c5cb6
VZ		 3065 /* Get the current configuration of the RSS indirection table */
3066 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3067
3068 /*
3069 * We can't use a memcpy() as an internal storage of an
3070 * indirection table is a u8 array while indir->ring_index
3071 * points to an array of u32.
3072 *
3073 * Indirection table contains the FW Client IDs, so we need to
3074 * align the returned table to the Client ID of the leading RSS
3075 * queue.
3076 */
7850f63f
BH		 3077 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3078 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 3079
ab532cf3
TH		 3080 return 0;
3081}
3082
7850f63f 3083static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
ab532cf3
TH		 3084{
3085 struct bnx2x *bp = netdev_priv(dev);
3086 size_t i;
619c5cb6
VZ		 3087
3088 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6
VZ		 3089 /*
3090 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
3091 * as an internal storage of an indirection table is a u8 array
3092 * while indir->ring_index points to an array of u32.
3093 *
3094 * Indirection table contains the FW Client IDs, so we need to
3095 * align the received table to the Client ID of the leading RSS
3096 * queue
3097 */
5d317c6a 3098 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 3099 }
ab532cf3 3100
5d317c6a 3101 return bnx2x_config_rss_eth(bp, false);
ab532cf3
TH		 3102}
3103
0e8d2ec5
MS		 3104/**
3105 * bnx2x_get_channels - gets the number of RSS queues.
3106 *
3107 * @dev: net device
3108 * @channels: returns the number of max / current queues
3109 */
3110static void bnx2x_get_channels(struct net_device *dev,
3111 struct ethtool_channels *channels)
3112{
3113 struct bnx2x *bp = netdev_priv(dev);
3114
3115 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3116 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3117}
3118
3119/**
3120 * bnx2x_change_num_queues - change the number of RSS queues.
3121 *
3122 * @bp: bnx2x private structure
3123 *
3124 * Re-configure interrupt mode to get the new number of MSI-X
3125 * vectors and re-add NAPI objects.
3126 */
3127static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3128{
0e8d2ec5 3129 bnx2x_disable_msi(bp);
55c11941
MS		 3130 bp->num_ethernet_queues = num_rss;
3131 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3132 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
0e8d2ec5 3133 bnx2x_set_int_mode(bp);
0e8d2ec5
MS		 3134}
3135
3136/**
3137 * bnx2x_set_channels - sets the number of RSS queues.
3138 *
3139 * @dev: net device
3140 * @channels: includes the number of queues requested
3141 */
3142static int bnx2x_set_channels(struct net_device *dev,
3143 struct ethtool_channels *channels)
3144{
3145 struct bnx2x *bp = netdev_priv(dev);
3146
3147
3148 DP(BNX2X_MSG_ETHTOOL,
3149 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3150 channels->rx_count, channels->tx_count, channels->other_count,
3151 channels->combined_count);
3152
3153 /* We don't support separate rx / tx channels.
3154 * We don't allow setting 'other' channels.
3155 */
3156 if (channels->rx_count || channels->tx_count || channels->other_count
3157 || (channels->combined_count == 0) ||
3158 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3159 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3160 return -EINVAL;
3161 }
3162
3163 /* Check if there was a change in the active parameters */
3164 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3165 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3166 return 0;
3167 }
3168
3169 /* Set the requested number of queues in bp context.
3170 * Note that the actual number of queues created during load may be
3171 * less than requested if memory is low.
3172 */
3173 if (unlikely(!netif_running(dev))) {
3174 bnx2x_change_num_queues(bp, channels->combined_count);
3175 return 0;
3176 }
5d07d868 3177 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
0e8d2ec5
MS		 3178 bnx2x_change_num_queues(bp, channels->combined_count);
3179 return bnx2x_nic_load(bp, LOAD_NORMAL);
3180}
3181
de0c62db
DK		 3182static const struct ethtool_ops bnx2x_ethtool_ops = {
3183 .get_settings = bnx2x_get_settings,
3184 .set_settings = bnx2x_set_settings,
3185 .get_drvinfo = bnx2x_get_drvinfo,
3186 .get_regs_len = bnx2x_get_regs_len,
3187 .get_regs = bnx2x_get_regs,
07ba6af4
MS		 3188 .get_dump_flag = bnx2x_get_dump_flag,
3189 .get_dump_data = bnx2x_get_dump_data,
3190 .set_dump = bnx2x_set_dump,
de0c62db
DK		 3191 .get_wol = bnx2x_get_wol,
3192 .set_wol = bnx2x_set_wol,
3193 .get_msglevel = bnx2x_get_msglevel,
3194 .set_msglevel = bnx2x_set_msglevel,
3195 .nway_reset = bnx2x_nway_reset,
3196 .get_link = bnx2x_get_link,
3197 .get_eeprom_len = bnx2x_get_eeprom_len,
3198 .get_eeprom = bnx2x_get_eeprom,
3199 .set_eeprom = bnx2x_set_eeprom,
3200 .get_coalesce = bnx2x_get_coalesce,
3201 .set_coalesce = bnx2x_set_coalesce,
3202 .get_ringparam = bnx2x_get_ringparam,
3203 .set_ringparam = bnx2x_set_ringparam,
3204 .get_pauseparam = bnx2x_get_pauseparam,
3205 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 3206 .self_test = bnx2x_self_test,
3207 .get_sset_count = bnx2x_get_sset_count,
3208 .get_strings = bnx2x_get_strings,
32d36134 3209 .set_phys_id = bnx2x_set_phys_id,
de0c62db 3210 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 3211 .get_rxnfc = bnx2x_get_rxnfc,
5d317c6a 3212 .set_rxnfc = bnx2x_set_rxnfc,
7850f63f 3213 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
ab532cf3
TH		 3214 .get_rxfh_indir = bnx2x_get_rxfh_indir,
3215 .set_rxfh_indir = bnx2x_set_rxfh_indir,
0e8d2ec5
MS		 3216 .get_channels = bnx2x_get_channels,
3217 .set_channels = bnx2x_set_channels,
24ea818e
YM		 3218 .get_module_info = bnx2x_get_module_info,
3219 .get_module_eeprom = bnx2x_get_module_eeprom,
e9939c80
YM		 3220 .get_eee = bnx2x_get_eee,
3221 .set_eee = bnx2x_set_eee,
be53ce1e 3222 .get_ts_info = ethtool_op_get_ts_info,
de0c62db
DK		 3223};
3224
3225void bnx2x_set_ethtool_ops(struct net_device *netdev)
3226{
3227 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
3228}
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