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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
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de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
25
26
27#include "bnx2x.h"
28#include "bnx2x_cmn.h"
29#include "bnx2x_dump.h"
4a33bc03 30#include "bnx2x_init.h"
042181f5 31#include "bnx2x_sp.h"
de0c62db 32
ec6ba945
VZ		 33/* Note: in the format strings below %s is replaced by the queue-name which is
34 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
35 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
36 */
37#define MAX_QUEUE_NAME_LEN 4
38static const struct {
39 long offset;
40 int size;
41 char string[ETH_GSTRING_LEN];
42} bnx2x_q_stats_arr[] = {
43/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 44 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
45 8, "[%s]: rx_ucast_packets" },
46 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
47 8, "[%s]: rx_mcast_packets" },
48 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
49 8, "[%s]: rx_bcast_packets" },
50 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
51 { Q_STATS_OFFSET32(rx_err_discard_pkt),
52 4, "[%s]: rx_phy_ip_err_discards"},
53 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
54 4, "[%s]: rx_skb_alloc_discard" },
55 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
56
619c5cb6
VZ		 57 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
58/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 59 8, "[%s]: tx_ucast_packets" },
60 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
61 8, "[%s]: tx_mcast_packets" },
62 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 63 8, "[%s]: tx_bcast_packets" },
64 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
65 8, "[%s]: tpa_aggregations" },
66 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
67 8, "[%s]: tpa_aggregated_frames"},
68 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
ec6ba945
VZ		 69};
70
71#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
72
73static const struct {
74 long offset;
75 int size;
76 u32 flags;
77#define STATS_FLAGS_PORT 1
78#define STATS_FLAGS_FUNC 2
79#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
80 char string[ETH_GSTRING_LEN];
81} bnx2x_stats_arr[] = {
82/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
83 8, STATS_FLAGS_BOTH, "rx_bytes" },
84 { STATS_OFFSET32(error_bytes_received_hi),
85 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
86 { STATS_OFFSET32(total_unicast_packets_received_hi),
87 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
88 { STATS_OFFSET32(total_multicast_packets_received_hi),
89 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
90 { STATS_OFFSET32(total_broadcast_packets_received_hi),
91 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
92 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
93 8, STATS_FLAGS_PORT, "rx_crc_errors" },
94 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
95 8, STATS_FLAGS_PORT, "rx_align_errors" },
96 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
97 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
98 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
99 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
100/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
101 8, STATS_FLAGS_PORT, "rx_fragments" },
102 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
103 8, STATS_FLAGS_PORT, "rx_jabbers" },
104 { STATS_OFFSET32(no_buff_discard_hi),
105 8, STATS_FLAGS_BOTH, "rx_discards" },
106 { STATS_OFFSET32(mac_filter_discard),
107 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 108 { STATS_OFFSET32(mf_tag_discard),
109 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
ec6ba945
VZ		 110 { STATS_OFFSET32(brb_drop_hi),
111 8, STATS_FLAGS_PORT, "rx_brb_discard" },
112 { STATS_OFFSET32(brb_truncate_hi),
113 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
114 { STATS_OFFSET32(pause_frames_received_hi),
115 8, STATS_FLAGS_PORT, "rx_pause_frames" },
116 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
117 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
118 { STATS_OFFSET32(nig_timer_max),
119 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
120/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
121 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
122 { STATS_OFFSET32(rx_skb_alloc_failed),
123 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
124 { STATS_OFFSET32(hw_csum_err),
125 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
126
127 { STATS_OFFSET32(total_bytes_transmitted_hi),
128 8, STATS_FLAGS_BOTH, "tx_bytes" },
129 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
130 8, STATS_FLAGS_PORT, "tx_error_bytes" },
131 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
132 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
133 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
134 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
135 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
136 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
137 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
138 8, STATS_FLAGS_PORT, "tx_mac_errors" },
139 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
140 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
141/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
142 8, STATS_FLAGS_PORT, "tx_single_collisions" },
143 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
144 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
145 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
146 8, STATS_FLAGS_PORT, "tx_deferred" },
147 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
148 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
149 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
150 8, STATS_FLAGS_PORT, "tx_late_collisions" },
151 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
152 8, STATS_FLAGS_PORT, "tx_total_collisions" },
153 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
154 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
155 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
156 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
157 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
158 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
159 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
160 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
161/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
162 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
163 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
164 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
165 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
166 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
167 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 168 8, STATS_FLAGS_PORT, "tx_pause_frames" },
169 { STATS_OFFSET32(total_tpa_aggregations_hi),
170 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
171 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
172 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
173 { STATS_OFFSET32(total_tpa_bytes_hi),
174 8, STATS_FLAGS_FUNC, "tpa_bytes"}
ec6ba945
VZ		 175};
176
177#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
1ac9e428
YR		 178static int bnx2x_get_port_type(struct bnx2x *bp)
179{
180 int port_type;
181 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
182 switch (bp->link_params.phy[phy_idx].media_type) {
183 case ETH_PHY_SFP_FIBER:
184 case ETH_PHY_XFP_FIBER:
185 case ETH_PHY_KR:
186 case ETH_PHY_CX4:
187 port_type = PORT_FIBRE;
188 break;
189 case ETH_PHY_DA_TWINAX:
190 port_type = PORT_DA;
191 break;
192 case ETH_PHY_BASE_T:
193 port_type = PORT_TP;
194 break;
195 case ETH_PHY_NOT_PRESENT:
196 port_type = PORT_NONE;
197 break;
198 case ETH_PHY_UNSPECIFIED:
199 default:
200 port_type = PORT_OTHER;
201 break;
202 }
203 return port_type;
204}
ec6ba945 205
de0c62db
DK		 206static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
207{
208 struct bnx2x *bp = netdev_priv(dev);
a22f0788 209 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 210
a22f0788
YR		 211 /* Dual Media boards present all available port types */
212 cmd->supported = bp->port.supported[cfg_idx] |
213 (bp->port.supported[cfg_idx ^ 1] &
214 (SUPPORTED_TP | SUPPORTED_FIBRE));
215 cmd->advertising = bp->port.advertising[cfg_idx];
de0c62db
DK		 216
217 if ((bp->state == BNX2X_STATE_OPEN) &&
218 !(bp->flags & MF_FUNC_DIS) &&
219 (bp->link_vars.link_up)) {
b3337e4c 220 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
de0c62db 221 cmd->duplex = bp->link_vars.duplex;
de0c62db 222 } else {
b3337e4c
DD		 223 ethtool_cmd_speed_set(
224 cmd, bp->link_params.req_line_speed[cfg_idx]);
a22f0788 225 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
de0c62db 226 }
f2e0899f 227
0793f83f 228 if (IS_MF(bp))
b3337e4c 229 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
de0c62db 230
1ac9e428 231 cmd->port = bnx2x_get_port_type(bp);
a22f0788 232
de0c62db
DK		 233 cmd->phy_address = bp->mdio.prtad;
234 cmd->transceiver = XCVR_INTERNAL;
235
a22f0788 236 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 237 cmd->autoneg = AUTONEG_ENABLE;
238 else
239 cmd->autoneg = AUTONEG_DISABLE;
240
241 cmd->maxtxpkt = 0;
242 cmd->maxrxpkt = 0;
243
244 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 245 " supported 0x%x advertising 0x%x speed %u\n"
246 " duplex %d port %d phy_address %d transceiver %d\n"
247 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 248 cmd->cmd, cmd->supported, cmd->advertising,
249 ethtool_cmd_speed(cmd),
de0c62db
DK		 250 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
251 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
252
253 return 0;
254}
255
256static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
257{
258 struct bnx2x *bp = netdev_priv(dev);
a22f0788 259 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
0793f83f 260 u32 speed;
de0c62db 261
0793f83f 262 if (IS_MF_SD(bp))
de0c62db
DK		 263 return 0;
264
265 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
b3337e4c 266 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 267 " duplex %d port %d phy_address %d transceiver %d\n"
268 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 269 cmd->cmd, cmd->supported, cmd->advertising,
270 ethtool_cmd_speed(cmd),
de0c62db
DK		 271 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
272 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
273
b3337e4c 274 speed = ethtool_cmd_speed(cmd);
0793f83f
DK		 275
276 if (IS_MF_SI(bp)) {
e3835b99 277 u32 part;
0793f83f
DK		 278 u32 line_speed = bp->link_vars.line_speed;
279
280 /* use 10G if no link detected */
281 if (!line_speed)
282 line_speed = 10000;
283
284 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
285 BNX2X_DEV_INFO("To set speed BC %X or higher "
286 "is required, please upgrade BC\n",
287 REQ_BC_VER_4_SET_MF_BW);
288 return -EINVAL;
289 }
e3835b99 290
faa6fcbb 291 part = (speed * 100) / line_speed;
e3835b99 292
faa6fcbb
DK		 293 if (line_speed < speed || !part) {
294 BNX2X_DEV_INFO("Speed setting should be in a range "
295 "from 1%% to 100%% "
296 "of actual line speed\n");
0793f83f
DK		 297 return -EINVAL;
298 }
0793f83f 299
e3835b99
DK		 300 if (bp->state != BNX2X_STATE_OPEN)
301 /* store value for following "load" */
302 bp->pending_max = part;
303 else
304 bnx2x_update_max_mf_config(bp, part);
0793f83f 305
0793f83f
DK		 306 return 0;
307 }
308
a22f0788
YR		 309 cfg_idx = bnx2x_get_link_cfg_idx(bp);
310 old_multi_phy_config = bp->link_params.multi_phy_config;
311 switch (cmd->port) {
312 case PORT_TP:
313 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
314 break; /* no port change */
315
316 if (!(bp->port.supported[0] & SUPPORTED_TP ||
317 bp->port.supported[1] & SUPPORTED_TP)) {
318 DP(NETIF_MSG_LINK, "Unsupported port type\n");
319 return -EINVAL;
320 }
321 bp->link_params.multi_phy_config &=
322 ~PORT_HW_CFG_PHY_SELECTION_MASK;
323 if (bp->link_params.multi_phy_config &
324 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
325 bp->link_params.multi_phy_config |=
326 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
327 else
328 bp->link_params.multi_phy_config |=
329 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
330 break;
331 case PORT_FIBRE:
bfdb5823 332 case PORT_DA:
a22f0788
YR		 333 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
334 break; /* no port change */
335
336 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
337 bp->port.supported[1] & SUPPORTED_FIBRE)) {
338 DP(NETIF_MSG_LINK, "Unsupported port type\n");
339 return -EINVAL;
340 }
341 bp->link_params.multi_phy_config &=
342 ~PORT_HW_CFG_PHY_SELECTION_MASK;
343 if (bp->link_params.multi_phy_config &
344 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
345 bp->link_params.multi_phy_config |=
346 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
347 else
348 bp->link_params.multi_phy_config |=
349 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
350 break;
351 default:
352 DP(NETIF_MSG_LINK, "Unsupported port type\n");
353 return -EINVAL;
354 }
2f751a80 355 /* Save new config in case command complete successully */
a22f0788
YR		 356 new_multi_phy_config = bp->link_params.multi_phy_config;
357 /* Get the new cfg_idx */
358 cfg_idx = bnx2x_get_link_cfg_idx(bp);
359 /* Restore old config in case command failed */
360 bp->link_params.multi_phy_config = old_multi_phy_config;
361 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
362
de0c62db 363 if (cmd->autoneg == AUTONEG_ENABLE) {
a22f0788 364 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 365 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
366 return -EINVAL;
367 }
368
369 /* advertise the requested speed and duplex if supported */
8d661637
YR		 370 if (cmd->advertising & ~(bp->port.supported[cfg_idx])) {
371 DP(NETIF_MSG_LINK, "Advertisement parameters "
372 "are not supported\n");
373 return -EINVAL;
374 }
de0c62db 375
a22f0788 376 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 377 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
378 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 379 cmd->advertising);
8d661637
YR		 380 if (cmd->advertising) {
381
382 bp->link_params.speed_cap_mask[cfg_idx] = 0;
383 if (cmd->advertising & ADVERTISED_10baseT_Half) {
384 bp->link_params.speed_cap_mask[cfg_idx] |=
385 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
386 }
387 if (cmd->advertising & ADVERTISED_10baseT_Full)
388 bp->link_params.speed_cap_mask[cfg_idx] |=
389 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 390
8d661637
YR		 391 if (cmd->advertising & ADVERTISED_100baseT_Full)
392 bp->link_params.speed_cap_mask[cfg_idx] |=
393 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
394
395 if (cmd->advertising & ADVERTISED_100baseT_Half) {
396 bp->link_params.speed_cap_mask[cfg_idx] |=
397 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
398 }
399 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
400 bp->link_params.speed_cap_mask[cfg_idx] |=
401 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
402 }
403 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
404 ADVERTISED_1000baseKX_Full))
405 bp->link_params.speed_cap_mask[cfg_idx] |=
406 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
407
408 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
409 ADVERTISED_10000baseKX4_Full |
410 ADVERTISED_10000baseKR_Full))
411 bp->link_params.speed_cap_mask[cfg_idx] |=
412 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
413 }
de0c62db
DK		 414 } else { /* forced speed */
415 /* advertise the requested speed and duplex if supported */
a22f0788 416 switch (speed) {
de0c62db
DK		 417 case SPEED_10:
418 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 419 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 420 SUPPORTED_10baseT_Full)) {
421 DP(NETIF_MSG_LINK,
422 "10M full not supported\n");
423 return -EINVAL;
424 }
425
426 advertising = (ADVERTISED_10baseT_Full |
427 ADVERTISED_TP);
428 } else {
a22f0788 429 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 430 SUPPORTED_10baseT_Half)) {
431 DP(NETIF_MSG_LINK,
432 "10M half not supported\n");
433 return -EINVAL;
434 }
435
436 advertising = (ADVERTISED_10baseT_Half |
437 ADVERTISED_TP);
438 }
439 break;
440
441 case SPEED_100:
442 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 443 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 444 SUPPORTED_100baseT_Full)) {
445 DP(NETIF_MSG_LINK,
446 "100M full not supported\n");
447 return -EINVAL;
448 }
449
450 advertising = (ADVERTISED_100baseT_Full |
451 ADVERTISED_TP);
452 } else {
a22f0788 453 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 454 SUPPORTED_100baseT_Half)) {
455 DP(NETIF_MSG_LINK,
456 "100M half not supported\n");
457 return -EINVAL;
458 }
459
460 advertising = (ADVERTISED_100baseT_Half |
461 ADVERTISED_TP);
462 }
463 break;
464
465 case SPEED_1000:
466 if (cmd->duplex != DUPLEX_FULL) {
467 DP(NETIF_MSG_LINK, "1G half not supported\n");
468 return -EINVAL;
469 }
470
a22f0788
YR		 471 if (!(bp->port.supported[cfg_idx] &
472 SUPPORTED_1000baseT_Full)) {
de0c62db
DK		 473 DP(NETIF_MSG_LINK, "1G full not supported\n");
474 return -EINVAL;
475 }
476
477 advertising = (ADVERTISED_1000baseT_Full |
478 ADVERTISED_TP);
479 break;
480
481 case SPEED_2500:
482 if (cmd->duplex != DUPLEX_FULL) {
483 DP(NETIF_MSG_LINK,
484 "2.5G half not supported\n");
485 return -EINVAL;
486 }
487
a22f0788
YR		 488 if (!(bp->port.supported[cfg_idx]
489 & SUPPORTED_2500baseX_Full)) {
de0c62db
DK		 490 DP(NETIF_MSG_LINK,
491 "2.5G full not supported\n");
492 return -EINVAL;
493 }
494
495 advertising = (ADVERTISED_2500baseX_Full |
496 ADVERTISED_TP);
497 break;
498
499 case SPEED_10000:
500 if (cmd->duplex != DUPLEX_FULL) {
501 DP(NETIF_MSG_LINK, "10G half not supported\n");
502 return -EINVAL;
503 }
504
a22f0788
YR		 505 if (!(bp->port.supported[cfg_idx]
506 & SUPPORTED_10000baseT_Full)) {
de0c62db
DK		 507 DP(NETIF_MSG_LINK, "10G full not supported\n");
508 return -EINVAL;
509 }
510
511 advertising = (ADVERTISED_10000baseT_Full |
512 ADVERTISED_FIBRE);
513 break;
514
515 default:
b3337e4c 516 DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
de0c62db
DK		 517 return -EINVAL;
518 }
519
a22f0788
YR		 520 bp->link_params.req_line_speed[cfg_idx] = speed;
521 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
522 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 523 }
524
525 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
f1deab50 526 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 527 bp->link_params.req_line_speed[cfg_idx],
528 bp->link_params.req_duplex[cfg_idx],
529 bp->port.advertising[cfg_idx]);
de0c62db 530
a22f0788
YR		 531 /* Set new config */
532 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 533 if (netif_running(dev)) {
534 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
535 bnx2x_link_set(bp);
536 }
537
538 return 0;
539}
540
541#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
542#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 543#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
0fea29c1
VZ		 544#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
545#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
546
547static inline bool bnx2x_is_reg_online(struct bnx2x *bp,
548 const struct reg_addr *reg_info)
549{
550 if (CHIP_IS_E1(bp))
551 return IS_E1_ONLINE(reg_info->info);
552 else if (CHIP_IS_E1H(bp))
553 return IS_E1H_ONLINE(reg_info->info);
554 else if (CHIP_IS_E2(bp))
555 return IS_E2_ONLINE(reg_info->info);
556 else if (CHIP_IS_E3A0(bp))
557 return IS_E3_ONLINE(reg_info->info);
558 else if (CHIP_IS_E3B0(bp))
559 return IS_E3B0_ONLINE(reg_info->info);
560 else
561 return false;
562}
563
564/******* Paged registers info selectors ********/
565static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
566{
567 if (CHIP_IS_E2(bp))
568 return page_vals_e2;
569 else if (CHIP_IS_E3(bp))
570 return page_vals_e3;
571 else
572 return NULL;
573}
574
575static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
576{
577 if (CHIP_IS_E2(bp))
578 return PAGE_MODE_VALUES_E2;
579 else if (CHIP_IS_E3(bp))
580 return PAGE_MODE_VALUES_E3;
581 else
582 return 0;
583}
584
585static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
586{
587 if (CHIP_IS_E2(bp))
588 return page_write_regs_e2;
589 else if (CHIP_IS_E3(bp))
590 return page_write_regs_e3;
591 else
592 return NULL;
593}
594
595static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
596{
597 if (CHIP_IS_E2(bp))
598 return PAGE_WRITE_REGS_E2;
599 else if (CHIP_IS_E3(bp))
600 return PAGE_WRITE_REGS_E3;
601 else
602 return 0;
603}
604
605static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
606{
607 if (CHIP_IS_E2(bp))
608 return page_read_regs_e2;
609 else if (CHIP_IS_E3(bp))
610 return page_read_regs_e3;
611 else
612 return NULL;
613}
614
615static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
616{
617 if (CHIP_IS_E2(bp))
618 return PAGE_READ_REGS_E2;
619 else if (CHIP_IS_E3(bp))
620 return PAGE_READ_REGS_E3;
621 else
622 return 0;
623}
624
625static inline int __bnx2x_get_regs_len(struct bnx2x *bp)
626{
627 int num_pages = __bnx2x_get_page_reg_num(bp);
628 int page_write_num = __bnx2x_get_page_write_num(bp);
629 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
630 int page_read_num = __bnx2x_get_page_read_num(bp);
631 int regdump_len = 0;
632 int i, j, k;
633
634 for (i = 0; i < REGS_COUNT; i++)
635 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
636 regdump_len += reg_addrs[i].size;
637
638 for (i = 0; i < num_pages; i++)
639 for (j = 0; j < page_write_num; j++)
640 for (k = 0; k < page_read_num; k++)
641 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
642 regdump_len += page_read_addr[k].size;
643
644 return regdump_len;
645}
de0c62db
DK		 646
647static int bnx2x_get_regs_len(struct net_device *dev)
648{
649 struct bnx2x *bp = netdev_priv(dev);
650 int regdump_len = 0;
de0c62db 651
0fea29c1 652 regdump_len = __bnx2x_get_regs_len(bp);
de0c62db
DK		 653 regdump_len *= 4;
654 regdump_len += sizeof(struct dump_hdr);
655
656 return regdump_len;
657}
658
0fea29c1
VZ		 659/**
660 * bnx2x_read_pages_regs - read "paged" registers
661 *
662 * @bp device handle
663 * @p output buffer
664 *
665 * Reads "paged" memories: memories that may only be read by first writing to a
666 * specific address ("write address") and then reading from a specific address
667 * ("read address"). There may be more than one write address per "page" and
668 * more than one read address per write address.
669 */
670static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
f2e0899f
DK		 671{
672 u32 i, j, k, n;
0fea29c1
VZ		 673 /* addresses of the paged registers */
674 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
675 /* number of paged registers */
676 int num_pages = __bnx2x_get_page_reg_num(bp);
677 /* write addresses */
678 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
679 /* number of write addresses */
680 int write_num = __bnx2x_get_page_write_num(bp);
681 /* read addresses info */
682 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
683 /* number of read addresses */
684 int read_num = __bnx2x_get_page_read_num(bp);
685
686 for (i = 0; i < num_pages; i++) {
687 for (j = 0; j < write_num; j++) {
688 REG_WR(bp, write_addr[j], page_addr[i]);
689 for (k = 0; k < read_num; k++)
690 if (bnx2x_is_reg_online(bp, &read_addr[k]))
f2e0899f 691 for (n = 0; n <
0fea29c1 692 read_addr[k].size; n++)
f2e0899f 693 *p++ = REG_RD(bp,
0fea29c1 694 read_addr[k].addr + n*4);
f2e0899f
DK		 695 }
696 }
697}
698
0fea29c1
VZ		 699static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
700{
701 u32 i, j;
702
703 /* Read the regular registers */
704 for (i = 0; i < REGS_COUNT; i++)
705 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
706 for (j = 0; j < reg_addrs[i].size; j++)
707 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
708
709 /* Read "paged" registes */
710 bnx2x_read_pages_regs(bp, p);
711}
712
de0c62db
DK		 713static void bnx2x_get_regs(struct net_device *dev,
714 struct ethtool_regs *regs, void *_p)
715{
0fea29c1 716 u32 *p = _p;
de0c62db
DK		 717 struct bnx2x *bp = netdev_priv(dev);
718 struct dump_hdr dump_hdr = {0};
719
720 regs->version = 0;
721 memset(p, 0, regs->len);
722
723 if (!netif_running(bp->dev))
724 return;
725
4a33bc03
VZ		 726 /* Disable parity attentions as long as following dump may
727 * cause false alarms by reading never written registers. We
728 * will re-enable parity attentions right after the dump.
729 */
730 bnx2x_disable_blocks_parity(bp);
731
de0c62db
DK		 732 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
733 dump_hdr.dump_sign = dump_sign_all;
734 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
735 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
736 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
737 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 738
739 if (CHIP_IS_E1(bp))
740 dump_hdr.info = RI_E1_ONLINE;
741 else if (CHIP_IS_E1H(bp))
742 dump_hdr.info = RI_E1H_ONLINE;
619c5cb6 743 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 744 dump_hdr.info = RI_E2_ONLINE |
745 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 746
747 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
748 p += dump_hdr.hdr_size + 1;
749
0fea29c1
VZ		 750 /* Actually read the registers */
751 __bnx2x_get_regs(bp, p);
752
4a33bc03
VZ		 753 /* Re-enable parity attentions */
754 bnx2x_clear_blocks_parity(bp);
c9ee9206 755 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 756}
757
de0c62db
DK		 758static void bnx2x_get_drvinfo(struct net_device *dev,
759 struct ethtool_drvinfo *info)
760{
761 struct bnx2x *bp = netdev_priv(dev);
762 u8 phy_fw_ver[PHY_FW_VER_LEN];
763
68aad78c
RJ		 764 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
765 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db
DK		 766
767 phy_fw_ver[0] = '\0';
768 if (bp->port.pmf) {
769 bnx2x_acquire_phy_lock(bp);
770 bnx2x_get_ext_phy_fw_version(&bp->link_params,
771 (bp->state != BNX2X_STATE_CLOSED),
772 phy_fw_ver, PHY_FW_VER_LEN);
773 bnx2x_release_phy_lock(bp);
774 }
775
68aad78c 776 strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
de0c62db
DK		 777 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
778 "bc %d.%d.%d%s%s",
779 (bp->common.bc_ver & 0xff0000) >> 16,
780 (bp->common.bc_ver & 0xff00) >> 8,
781 (bp->common.bc_ver & 0xff),
782 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
68aad78c 783 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db
DK		 784 info->n_stats = BNX2X_NUM_STATS;
785 info->testinfo_len = BNX2X_NUM_TESTS;
786 info->eedump_len = bp->common.flash_size;
787 info->regdump_len = bnx2x_get_regs_len(dev);
788}
789
790static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
791{
792 struct bnx2x *bp = netdev_priv(dev);
793
794 if (bp->flags & NO_WOL_FLAG) {
795 wol->supported = 0;
796 wol->wolopts = 0;
797 } else {
798 wol->supported = WAKE_MAGIC;
799 if (bp->wol)
800 wol->wolopts = WAKE_MAGIC;
801 else
802 wol->wolopts = 0;
803 }
804 memset(&wol->sopass, 0, sizeof(wol->sopass));
805}
806
807static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
808{
809 struct bnx2x *bp = netdev_priv(dev);
810
811 if (wol->wolopts & ~WAKE_MAGIC)
812 return -EINVAL;
813
814 if (wol->wolopts & WAKE_MAGIC) {
815 if (bp->flags & NO_WOL_FLAG)
816 return -EINVAL;
817
818 bp->wol = 1;
819 } else
820 bp->wol = 0;
821
822 return 0;
823}
824
825static u32 bnx2x_get_msglevel(struct net_device *dev)
826{
827 struct bnx2x *bp = netdev_priv(dev);
828
829 return bp->msg_enable;
830}
831
832static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
833{
834 struct bnx2x *bp = netdev_priv(dev);
835
7a25cc73
DK		 836 if (capable(CAP_NET_ADMIN)) {
837 /* dump MCP trace */
838 if (level & BNX2X_MSG_MCP)
839 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 840 bp->msg_enable = level;
7a25cc73 841 }
de0c62db
DK		 842}
843
844static int bnx2x_nway_reset(struct net_device *dev)
845{
846 struct bnx2x *bp = netdev_priv(dev);
847
848 if (!bp->port.pmf)
849 return 0;
850
851 if (netif_running(dev)) {
852 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
853 bnx2x_link_set(bp);
854 }
855
856 return 0;
857}
858
859static u32 bnx2x_get_link(struct net_device *dev)
860{
861 struct bnx2x *bp = netdev_priv(dev);
862
f2e0899f 863 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 864 return 0;
865
866 return bp->link_vars.link_up;
867}
868
869static int bnx2x_get_eeprom_len(struct net_device *dev)
870{
871 struct bnx2x *bp = netdev_priv(dev);
872
873 return bp->common.flash_size;
874}
875
876static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
877{
878 int port = BP_PORT(bp);
879 int count, i;
880 u32 val = 0;
881
882 /* adjust timeout for emulation/FPGA */
754a2f52 883 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 884 if (CHIP_REV_IS_SLOW(bp))
885 count *= 100;
886
887 /* request access to nvram interface */
888 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
889 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
890
891 for (i = 0; i < count*10; i++) {
892 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
893 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
894 break;
895
896 udelay(5);
897 }
898
899 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
900 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
901 return -EBUSY;
902 }
903
904 return 0;
905}
906
907static int bnx2x_release_nvram_lock(struct bnx2x *bp)
908{
909 int port = BP_PORT(bp);
910 int count, i;
911 u32 val = 0;
912
913 /* adjust timeout for emulation/FPGA */
754a2f52 914 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 915 if (CHIP_REV_IS_SLOW(bp))
916 count *= 100;
917
918 /* relinquish nvram interface */
919 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
920 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
921
922 for (i = 0; i < count*10; i++) {
923 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
924 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
925 break;
926
927 udelay(5);
928 }
929
930 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
931 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
932 return -EBUSY;
933 }
934
935 return 0;
936}
937
938static void bnx2x_enable_nvram_access(struct bnx2x *bp)
939{
940 u32 val;
941
942 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
943
944 /* enable both bits, even on read */
945 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
946 (val | MCPR_NVM_ACCESS_ENABLE_EN |
947 MCPR_NVM_ACCESS_ENABLE_WR_EN));
948}
949
950static void bnx2x_disable_nvram_access(struct bnx2x *bp)
951{
952 u32 val;
953
954 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
955
956 /* disable both bits, even after read */
957 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
958 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
959 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
960}
961
962static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
963 u32 cmd_flags)
964{
965 int count, i, rc;
966 u32 val;
967
968 /* build the command word */
969 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
970
971 /* need to clear DONE bit separately */
972 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
973
974 /* address of the NVRAM to read from */
975 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
976 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
977
978 /* issue a read command */
979 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
980
981 /* adjust timeout for emulation/FPGA */
754a2f52 982 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 983 if (CHIP_REV_IS_SLOW(bp))
984 count *= 100;
985
986 /* wait for completion */
987 *ret_val = 0;
988 rc = -EBUSY;
989 for (i = 0; i < count; i++) {
990 udelay(5);
991 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
992
993 if (val & MCPR_NVM_COMMAND_DONE) {
994 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
995 /* we read nvram data in cpu order
996 * but ethtool sees it as an array of bytes
997 * converting to big-endian will do the work */
998 *ret_val = cpu_to_be32(val);
999 rc = 0;
1000 break;
1001 }
1002 }
1003
1004 return rc;
1005}
1006
1007static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1008 int buf_size)
1009{
1010 int rc;
1011 u32 cmd_flags;
1012 __be32 val;
1013
1014 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1015 DP(BNX2X_MSG_NVM,
1016 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1017 offset, buf_size);
1018 return -EINVAL;
1019 }
1020
1021 if (offset + buf_size > bp->common.flash_size) {
1022 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1023 " buf_size (0x%x) > flash_size (0x%x)\n",
1024 offset, buf_size, bp->common.flash_size);
1025 return -EINVAL;
1026 }
1027
1028 /* request access to nvram interface */
1029 rc = bnx2x_acquire_nvram_lock(bp);
1030 if (rc)
1031 return rc;
1032
1033 /* enable access to nvram interface */
1034 bnx2x_enable_nvram_access(bp);
1035
1036 /* read the first word(s) */
1037 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1038 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1039 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1040 memcpy(ret_buf, &val, 4);
1041
1042 /* advance to the next dword */
1043 offset += sizeof(u32);
1044 ret_buf += sizeof(u32);
1045 buf_size -= sizeof(u32);
1046 cmd_flags = 0;
1047 }
1048
1049 if (rc == 0) {
1050 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1051 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1052 memcpy(ret_buf, &val, 4);
1053 }
1054
1055 /* disable access to nvram interface */
1056 bnx2x_disable_nvram_access(bp);
1057 bnx2x_release_nvram_lock(bp);
1058
1059 return rc;
1060}
1061
1062static int bnx2x_get_eeprom(struct net_device *dev,
1063 struct ethtool_eeprom *eeprom, u8 *eebuf)
1064{
1065 struct bnx2x *bp = netdev_priv(dev);
1066 int rc;
1067
1068 if (!netif_running(dev))
1069 return -EAGAIN;
1070
1071 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1072 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1073 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1074 eeprom->len, eeprom->len);
1075
1076 /* parameters already validated in ethtool_get_eeprom */
1077
1078 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1079
1080 return rc;
1081}
1082
1083static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1084 u32 cmd_flags)
1085{
1086 int count, i, rc;
1087
1088 /* build the command word */
1089 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1090
1091 /* need to clear DONE bit separately */
1092 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1093
1094 /* write the data */
1095 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1096
1097 /* address of the NVRAM to write to */
1098 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1099 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1100
1101 /* issue the write command */
1102 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1103
1104 /* adjust timeout for emulation/FPGA */
754a2f52 1105 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1106 if (CHIP_REV_IS_SLOW(bp))
1107 count *= 100;
1108
1109 /* wait for completion */
1110 rc = -EBUSY;
1111 for (i = 0; i < count; i++) {
1112 udelay(5);
1113 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1114 if (val & MCPR_NVM_COMMAND_DONE) {
1115 rc = 0;
1116 break;
1117 }
1118 }
1119
1120 return rc;
1121}
1122
1123#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1124
1125static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1126 int buf_size)
1127{
1128 int rc;
1129 u32 cmd_flags;
1130 u32 align_offset;
1131 __be32 val;
1132
1133 if (offset + buf_size > bp->common.flash_size) {
1134 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1135 " buf_size (0x%x) > flash_size (0x%x)\n",
1136 offset, buf_size, bp->common.flash_size);
1137 return -EINVAL;
1138 }
1139
1140 /* request access to nvram interface */
1141 rc = bnx2x_acquire_nvram_lock(bp);
1142 if (rc)
1143 return rc;
1144
1145 /* enable access to nvram interface */
1146 bnx2x_enable_nvram_access(bp);
1147
1148 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1149 align_offset = (offset & ~0x03);
1150 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1151
1152 if (rc == 0) {
1153 val &= ~(0xff << BYTE_OFFSET(offset));
1154 val |= (*data_buf << BYTE_OFFSET(offset));
1155
1156 /* nvram data is returned as an array of bytes
1157 * convert it back to cpu order */
1158 val = be32_to_cpu(val);
1159
1160 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1161 cmd_flags);
1162 }
1163
1164 /* disable access to nvram interface */
1165 bnx2x_disable_nvram_access(bp);
1166 bnx2x_release_nvram_lock(bp);
1167
1168 return rc;
1169}
1170
1171static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1172 int buf_size)
1173{
1174 int rc;
1175 u32 cmd_flags;
1176 u32 val;
1177 u32 written_so_far;
1178
1179 if (buf_size == 1) /* ethtool */
1180 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1181
1182 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1183 DP(BNX2X_MSG_NVM,
1184 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1185 offset, buf_size);
1186 return -EINVAL;
1187 }
1188
1189 if (offset + buf_size > bp->common.flash_size) {
1190 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1191 " buf_size (0x%x) > flash_size (0x%x)\n",
1192 offset, buf_size, bp->common.flash_size);
1193 return -EINVAL;
1194 }
1195
1196 /* request access to nvram interface */
1197 rc = bnx2x_acquire_nvram_lock(bp);
1198 if (rc)
1199 return rc;
1200
1201 /* enable access to nvram interface */
1202 bnx2x_enable_nvram_access(bp);
1203
1204 written_so_far = 0;
1205 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1206 while ((written_so_far < buf_size) && (rc == 0)) {
1207 if (written_so_far == (buf_size - sizeof(u32)))
1208 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1209 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1210 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1211 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1212 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1213
1214 memcpy(&val, data_buf, 4);
1215
1216 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1217
1218 /* advance to the next dword */
1219 offset += sizeof(u32);
1220 data_buf += sizeof(u32);
1221 written_so_far += sizeof(u32);
1222 cmd_flags = 0;
1223 }
1224
1225 /* disable access to nvram interface */
1226 bnx2x_disable_nvram_access(bp);
1227 bnx2x_release_nvram_lock(bp);
1228
1229 return rc;
1230}
1231
1232static int bnx2x_set_eeprom(struct net_device *dev,
1233 struct ethtool_eeprom *eeprom, u8 *eebuf)
1234{
1235 struct bnx2x *bp = netdev_priv(dev);
1236 int port = BP_PORT(bp);
1237 int rc = 0;
e10bc84d 1238 u32 ext_phy_config;
de0c62db
DK		 1239 if (!netif_running(dev))
1240 return -EAGAIN;
1241
1242 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1243 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1244 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1245 eeprom->len, eeprom->len);
1246
1247 /* parameters already validated in ethtool_set_eeprom */
1248
1249 /* PHY eeprom can be accessed only by the PMF */
1250 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1251 !bp->port.pmf)
1252 return -EINVAL;
1253
e10bc84d
YR		 1254 ext_phy_config =
1255 SHMEM_RD(bp,
1256 dev_info.port_hw_config[port].external_phy_config);
1257
de0c62db
DK		 1258 if (eeprom->magic == 0x50485950) {
1259 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1260 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1261
1262 bnx2x_acquire_phy_lock(bp);
1263 rc |= bnx2x_link_reset(&bp->link_params,
1264 &bp->link_vars, 0);
e10bc84d 1265 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1266 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1267 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1268 MISC_REGISTERS_GPIO_HIGH, port);
1269 bnx2x_release_phy_lock(bp);
1270 bnx2x_link_report(bp);
1271
1272 } else if (eeprom->magic == 0x50485952) {
1273 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1274 if (bp->state == BNX2X_STATE_OPEN) {
1275 bnx2x_acquire_phy_lock(bp);
1276 rc |= bnx2x_link_reset(&bp->link_params,
1277 &bp->link_vars, 1);
1278
1279 rc |= bnx2x_phy_init(&bp->link_params,
1280 &bp->link_vars);
1281 bnx2x_release_phy_lock(bp);
1282 bnx2x_calc_fc_adv(bp);
1283 }
1284 } else if (eeprom->magic == 0x53985943) {
1285 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1286 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1287 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1288
1289 /* DSP Remove Download Mode */
1290 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1291 MISC_REGISTERS_GPIO_LOW, port);
1292
1293 bnx2x_acquire_phy_lock(bp);
1294
e10bc84d
YR		 1295 bnx2x_sfx7101_sp_sw_reset(bp,
1296 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1297
1298 /* wait 0.5 sec to allow it to run */
1299 msleep(500);
1300 bnx2x_ext_phy_hw_reset(bp, port);
1301 msleep(500);
1302 bnx2x_release_phy_lock(bp);
1303 }
1304 } else
1305 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1306
1307 return rc;
1308}
f85582f8 1309
de0c62db
DK		 1310static int bnx2x_get_coalesce(struct net_device *dev,
1311 struct ethtool_coalesce *coal)
1312{
1313 struct bnx2x *bp = netdev_priv(dev);
1314
1315 memset(coal, 0, sizeof(struct ethtool_coalesce));
1316
1317 coal->rx_coalesce_usecs = bp->rx_ticks;
1318 coal->tx_coalesce_usecs = bp->tx_ticks;
1319
1320 return 0;
1321}
1322
1323static int bnx2x_set_coalesce(struct net_device *dev,
1324 struct ethtool_coalesce *coal)
1325{
1326 struct bnx2x *bp = netdev_priv(dev);
1327
1328 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1329 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1330 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1331
1332 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1333 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1334 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1335
1336 if (netif_running(dev))
1337 bnx2x_update_coalesce(bp);
1338
1339 return 0;
1340}
1341
1342static void bnx2x_get_ringparam(struct net_device *dev,
1343 struct ethtool_ringparam *ering)
1344{
1345 struct bnx2x *bp = netdev_priv(dev);
1346
1347 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1348
25141580
DK		 1349 if (bp->rx_ring_size)
1350 ering->rx_pending = bp->rx_ring_size;
1351 else
c2188952 1352 ering->rx_pending = MAX_RX_AVAIL;
25141580 1353
de0c62db
DK		 1354 ering->tx_max_pending = MAX_TX_AVAIL;
1355 ering->tx_pending = bp->tx_ring_size;
1356}
1357
1358static int bnx2x_set_ringparam(struct net_device *dev,
1359 struct ethtool_ringparam *ering)
1360{
1361 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 1362
1363 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
f1deab50 1364 pr_err("Handling parity error recovery. Try again later\n");
de0c62db
DK		 1365 return -EAGAIN;
1366 }
1367
1368 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1369 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1370 MIN_RX_SIZE_TPA)) ||
de0c62db
DK		 1371 (ering->tx_pending > MAX_TX_AVAIL) ||
1372 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1373 return -EINVAL;
1374
1375 bp->rx_ring_size = ering->rx_pending;
1376 bp->tx_ring_size = ering->tx_pending;
1377
a9fccec7 1378 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1379}
1380
1381static void bnx2x_get_pauseparam(struct net_device *dev,
1382 struct ethtool_pauseparam *epause)
1383{
1384 struct bnx2x *bp = netdev_priv(dev);
a22f0788
YR		 1385 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1386 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1387 BNX2X_FLOW_CTRL_AUTO);
de0c62db
DK		 1388
1389 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1390 BNX2X_FLOW_CTRL_RX);
1391 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1392 BNX2X_FLOW_CTRL_TX);
1393
1394 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
f1deab50 1395 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1396 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1397}
1398
1399static int bnx2x_set_pauseparam(struct net_device *dev,
1400 struct ethtool_pauseparam *epause)
1401{
1402 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1403 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1404 if (IS_MF(bp))
de0c62db
DK		 1405 return 0;
1406
1407 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
f1deab50 1408 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1409 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1410
a22f0788 1411 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1412
1413 if (epause->rx_pause)
a22f0788 1414 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1415
1416 if (epause->tx_pause)
a22f0788 1417 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1418
a22f0788
YR		 1419 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1420 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1421
1422 if (epause->autoneg) {
a22f0788 1423 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 1424 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1425 return -EINVAL;
1426 }
1427
a22f0788
YR		 1428 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1429 bp->link_params.req_flow_ctrl[cfg_idx] =
1430 BNX2X_FLOW_CTRL_AUTO;
1431 }
de0c62db
DK		 1432 }
1433
1434 DP(NETIF_MSG_LINK,
a22f0788 1435 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1436
1437 if (netif_running(dev)) {
1438 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1439 bnx2x_link_set(bp);
1440 }
1441
1442 return 0;
1443}
1444
de0c62db
DK		 1445static const struct {
1446 char string[ETH_GSTRING_LEN];
1447} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1448 { "register_test (offline)" },
1449 { "memory_test (offline)" },
1450 { "loopback_test (offline)" },
1451 { "nvram_test (online)" },
1452 { "interrupt_test (online)" },
1453 { "link_test (online)" },
1454 { "idle check (online)" }
1455};
1456
619c5cb6
VZ		 1457enum {
1458 BNX2X_CHIP_E1_OFST = 0,
1459 BNX2X_CHIP_E1H_OFST,
1460 BNX2X_CHIP_E2_OFST,
1461 BNX2X_CHIP_E3_OFST,
1462 BNX2X_CHIP_E3B0_OFST,
1463 BNX2X_CHIP_MAX_OFST
1464};
1465
1466#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1467#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1468#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1469#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1470#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1471
1472#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1473#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1474
de0c62db
DK		 1475static int bnx2x_test_registers(struct bnx2x *bp)
1476{
1477 int idx, i, rc = -ENODEV;
619c5cb6 1478 u32 wr_val = 0, hw;
de0c62db
DK		 1479 int port = BP_PORT(bp);
1480 static const struct {
619c5cb6 1481 u32 hw;
de0c62db
DK		 1482 u32 offset0;
1483 u32 offset1;
1484 u32 mask;
1485 } reg_tbl[] = {
619c5cb6
VZ		 1486/* 0 */ { BNX2X_CHIP_MASK_ALL,
1487 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1488 { BNX2X_CHIP_MASK_ALL,
1489 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1490 { BNX2X_CHIP_MASK_E1X,
1491 HC_REG_AGG_INT_0, 4, 0x000003ff },
1492 { BNX2X_CHIP_MASK_ALL,
1493 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1494 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1495 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1496 { BNX2X_CHIP_MASK_E3B0,
1497 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1498 { BNX2X_CHIP_MASK_ALL,
1499 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1500 { BNX2X_CHIP_MASK_ALL,
1501 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1502 { BNX2X_CHIP_MASK_ALL,
1503 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1504 { BNX2X_CHIP_MASK_ALL,
1505 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1506/* 10 */ { BNX2X_CHIP_MASK_ALL,
1507 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1508 { BNX2X_CHIP_MASK_ALL,
1509 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1510 { BNX2X_CHIP_MASK_ALL,
1511 QM_REG_CONNNUM_0, 4, 0x000fffff },
1512 { BNX2X_CHIP_MASK_ALL,
1513 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1514 { BNX2X_CHIP_MASK_ALL,
1515 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1516 { BNX2X_CHIP_MASK_ALL,
1517 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1518 { BNX2X_CHIP_MASK_ALL,
1519 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1520 { BNX2X_CHIP_MASK_ALL,
1521 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1522 { BNX2X_CHIP_MASK_ALL,
1523 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1524 { BNX2X_CHIP_MASK_ALL,
1525 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1526/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1527 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1528 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1529 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1530 { BNX2X_CHIP_MASK_ALL,
1531 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1532 { BNX2X_CHIP_MASK_ALL,
1533 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1534 { BNX2X_CHIP_MASK_ALL,
1535 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1536 { BNX2X_CHIP_MASK_ALL,
1537 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1538 { BNX2X_CHIP_MASK_ALL,
1539 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1540 { BNX2X_CHIP_MASK_ALL,
1541 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1542 { BNX2X_CHIP_MASK_ALL,
1543 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1544 { BNX2X_CHIP_MASK_ALL,
1545 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1546/* 30 */ { BNX2X_CHIP_MASK_ALL,
1547 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1548 { BNX2X_CHIP_MASK_ALL,
1549 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1550 { BNX2X_CHIP_MASK_ALL,
1551 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1552 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1553 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1554 { BNX2X_CHIP_MASK_ALL,
1555 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1556 { BNX2X_CHIP_MASK_ALL,
1557 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1558 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1559 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1560 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1561 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1562
1563 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 1564 };
1565
1566 if (!netif_running(bp->dev))
1567 return rc;
1568
619c5cb6
VZ		 1569 if (CHIP_IS_E1(bp))
1570 hw = BNX2X_CHIP_MASK_E1;
1571 else if (CHIP_IS_E1H(bp))
1572 hw = BNX2X_CHIP_MASK_E1H;
1573 else if (CHIP_IS_E2(bp))
1574 hw = BNX2X_CHIP_MASK_E2;
1575 else if (CHIP_IS_E3B0(bp))
1576 hw = BNX2X_CHIP_MASK_E3B0;
1577 else /* e3 A0 */
1578 hw = BNX2X_CHIP_MASK_E3;
1579
de0c62db
DK		 1580 /* Repeat the test twice:
1581 First by writing 0x00000000, second by writing 0xffffffff */
1582 for (idx = 0; idx < 2; idx++) {
1583
1584 switch (idx) {
1585 case 0:
1586 wr_val = 0;
1587 break;
1588 case 1:
1589 wr_val = 0xffffffff;
1590 break;
1591 }
1592
1593 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1594 u32 offset, mask, save_val, val;
619c5cb6 1595 if (!(hw & reg_tbl[i].hw))
f2e0899f 1596 continue;
de0c62db
DK		 1597
1598 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1599 mask = reg_tbl[i].mask;
1600
1601 save_val = REG_RD(bp, offset);
1602
ec6ba945 1603 REG_WR(bp, offset, wr_val & mask);
f85582f8 1604
de0c62db
DK		 1605 val = REG_RD(bp, offset);
1606
1607 /* Restore the original register's value */
1608 REG_WR(bp, offset, save_val);
1609
1610 /* verify value is as expected */
1611 if ((val & mask) != (wr_val & mask)) {
619c5cb6 1612 DP(NETIF_MSG_HW,
de0c62db
DK		 1613 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1614 offset, val, wr_val, mask);
1615 goto test_reg_exit;
1616 }
1617 }
1618 }
1619
1620 rc = 0;
1621
1622test_reg_exit:
1623 return rc;
1624}
1625
1626static int bnx2x_test_memory(struct bnx2x *bp)
1627{
1628 int i, j, rc = -ENODEV;
619c5cb6 1629 u32 val, index;
de0c62db
DK		 1630 static const struct {
1631 u32 offset;
1632 int size;
1633 } mem_tbl[] = {
1634 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1635 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1636 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1637 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1638 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1639 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1640 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1641
1642 { 0xffffffff, 0 }
1643 };
619c5cb6 1644
de0c62db
DK		 1645 static const struct {
1646 char *name;
1647 u32 offset;
619c5cb6 1648 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 1649 } prty_tbl[] = {
619c5cb6
VZ		 1650 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1651 {0x3ffc0, 0, 0, 0} },
1652 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1653 {0x2, 0x2, 0, 0} },
1654 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1655 {0, 0, 0, 0} },
1656 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1657 {0x3ffc0, 0, 0, 0} },
1658 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1659 {0x3ffc0, 0, 0, 0} },
1660 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1661 {0x3ffc1, 0, 0, 0} },
1662
1663 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 1664 };
1665
1666 if (!netif_running(bp->dev))
1667 return rc;
1668
619c5cb6
VZ		 1669 if (CHIP_IS_E1(bp))
1670 index = BNX2X_CHIP_E1_OFST;
1671 else if (CHIP_IS_E1H(bp))
1672 index = BNX2X_CHIP_E1H_OFST;
1673 else if (CHIP_IS_E2(bp))
1674 index = BNX2X_CHIP_E2_OFST;
1675 else /* e3 */
1676 index = BNX2X_CHIP_E3_OFST;
1677
f2e0899f
DK		 1678 /* pre-Check the parity status */
1679 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1680 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1681 if (val & ~(prty_tbl[i].hw_mask[index])) {
f2e0899f
DK		 1682 DP(NETIF_MSG_HW,
1683 "%s is 0x%x\n", prty_tbl[i].name, val);
1684 goto test_mem_exit;
1685 }
1686 }
1687
de0c62db
DK		 1688 /* Go through all the memories */
1689 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1690 for (j = 0; j < mem_tbl[i].size; j++)
1691 REG_RD(bp, mem_tbl[i].offset + j*4);
1692
1693 /* Check the parity status */
1694 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1695 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1696 if (val & ~(prty_tbl[i].hw_mask[index])) {
de0c62db
DK		 1697 DP(NETIF_MSG_HW,
1698 "%s is 0x%x\n", prty_tbl[i].name, val);
1699 goto test_mem_exit;
1700 }
1701 }
1702
1703 rc = 0;
1704
1705test_mem_exit:
1706 return rc;
1707}
1708
a22f0788 1709static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 1710{
f2e0899f 1711 int cnt = 1400;
de0c62db 1712
619c5cb6 1713 if (link_up) {
a22f0788 1714 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 1715 msleep(20);
1716
1717 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
1718 DP(NETIF_MSG_LINK, "Timeout waiting for link up\n");
1719 }
de0c62db
DK		 1720}
1721
619c5cb6 1722static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 1723{
1724 unsigned int pkt_size, num_pkts, i;
1725 struct sk_buff *skb;
1726 unsigned char *packet;
1727 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1728 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
6383c0b3 1729 struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
de0c62db
DK		 1730 u16 tx_start_idx, tx_idx;
1731 u16 rx_start_idx, rx_idx;
619c5cb6 1732 u16 pkt_prod, bd_prod, rx_comp_cons;
de0c62db
DK		 1733 struct sw_tx_bd *tx_buf;
1734 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 1735 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1736 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 1737 dma_addr_t mapping;
1738 union eth_rx_cqe *cqe;
619c5cb6 1739 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 1740 struct sw_rx_bd *rx_buf;
1741 u16 len;
1742 int rc = -ENODEV;
e52fcb24 1743 u8 *data;
de0c62db
DK		 1744
1745 /* check the loopback mode */
1746 switch (loopback_mode) {
1747 case BNX2X_PHY_LOOPBACK:
de6eae1f 1748 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
de0c62db
DK		 1749 return -EINVAL;
1750 break;
1751 case BNX2X_MAC_LOOPBACK:
32911333
YR		 1752 if (CHIP_IS_E3(bp)) {
1753 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1754 if (bp->port.supported[cfg_idx] &
1755 (SUPPORTED_10000baseT_Full |
1756 SUPPORTED_20000baseMLD2_Full |
1757 SUPPORTED_20000baseKR2_Full))
1758 bp->link_params.loopback_mode = LOOPBACK_XMAC;
1759 else
1760 bp->link_params.loopback_mode = LOOPBACK_UMAC;
1761 } else
1762 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1763
de0c62db
DK		 1764 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1765 break;
1766 default:
1767 return -EINVAL;
1768 }
1769
1770 /* prepare the loopback packet */
1771 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1772 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 1773 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db
DK		 1774 if (!skb) {
1775 rc = -ENOMEM;
1776 goto test_loopback_exit;
1777 }
1778 packet = skb_put(skb, pkt_size);
1779 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1780 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1781 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1782 for (i = ETH_HLEN; i < pkt_size; i++)
1783 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 1784 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1785 skb_headlen(skb), DMA_TO_DEVICE);
1786 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1787 rc = -ENOMEM;
1788 dev_kfree_skb(skb);
1789 BNX2X_ERR("Unable to map SKB\n");
1790 goto test_loopback_exit;
1791 }
de0c62db
DK		 1792
1793 /* send the loopback packet */
1794 num_pkts = 0;
6383c0b3 1795 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 1796 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1797
6383c0b3
AE		 1798 pkt_prod = txdata->tx_pkt_prod++;
1799 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
1800 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 1801 tx_buf->skb = skb;
1802 tx_buf->flags = 0;
1803
6383c0b3
AE		 1804 bd_prod = TX_BD(txdata->tx_bd_prod);
1805 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 1806 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1807 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1808 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1809 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 1810 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 1811 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 1812 SET_FLAG(tx_start_bd->general_data,
1813 ETH_TX_START_BD_ETH_ADDR_TYPE,
1814 UNICAST_ADDRESS);
1815 SET_FLAG(tx_start_bd->general_data,
1816 ETH_TX_START_BD_HDR_NBDS,
1817 1);
de0c62db
DK		 1818
1819 /* turn on parsing and get a BD */
1820 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 1821
6383c0b3
AE		 1822 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
1823 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 1824
f2e0899f 1825 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 1826 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 1827
1828 wmb();
1829
6383c0b3 1830 txdata->tx_db.data.prod += 2;
de0c62db 1831 barrier();
6383c0b3 1832 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 1833
1834 mmiowb();
619c5cb6 1835 barrier();
de0c62db
DK		 1836
1837 num_pkts++;
6383c0b3 1838 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 1839
1840 udelay(100);
1841
6383c0b3 1842 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 1843 if (tx_idx != tx_start_idx + num_pkts)
1844 goto test_loopback_exit;
1845
f2e0899f
DK		 1846 /* Unlike HC IGU won't generate an interrupt for status block
1847 * updates that have been performed while interrupts were
1848 * disabled.
1849 */
e1210d12
ED		 1850 if (bp->common.int_block == INT_BLOCK_IGU) {
1851 /* Disable local BHes to prevent a dead-lock situation between
1852 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1853 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1854 */
1855 local_bh_disable();
6383c0b3 1856 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 1857 local_bh_enable();
1858 }
f2e0899f 1859
de0c62db
DK		 1860 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1861 if (rx_idx != rx_start_idx + num_pkts)
1862 goto test_loopback_exit;
1863
619c5cb6
VZ		 1864 rx_comp_cons = le16_to_cpu(fp_rx->rx_comp_cons);
1865 cqe = &fp_rx->rx_comp_ring[RCQ_BD(rx_comp_cons)];
de0c62db 1866 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 1867 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1868 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 1869 goto test_loopback_rx_exit;
1870
1871 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1872 if (len != pkt_size)
1873 goto test_loopback_rx_exit;
1874
1875 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 1876 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 1877 dma_unmap_addr(rx_buf, mapping),
1878 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 1879 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 1880 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 1881 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 1882 goto test_loopback_rx_exit;
1883
1884 rc = 0;
1885
1886test_loopback_rx_exit:
1887
1888 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1889 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1890 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1891 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1892
1893 /* Update producers */
1894 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1895 fp_rx->rx_sge_prod);
1896
1897test_loopback_exit:
1898 bp->link_params.loopback_mode = LOOPBACK_NONE;
1899
1900 return rc;
1901}
1902
619c5cb6 1903static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 1904{
1905 int rc = 0, res;
1906
1907 if (BP_NOMCP(bp))
1908 return rc;
1909
1910 if (!netif_running(bp->dev))
1911 return BNX2X_LOOPBACK_FAILED;
1912
1913 bnx2x_netif_stop(bp, 1);
1914 bnx2x_acquire_phy_lock(bp);
1915
619c5cb6 1916 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db
DK		 1917 if (res) {
1918 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1919 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1920 }
1921
619c5cb6 1922 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db
DK		 1923 if (res) {
1924 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1925 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1926 }
1927
1928 bnx2x_release_phy_lock(bp);
1929 bnx2x_netif_start(bp);
1930
1931 return rc;
1932}
1933
1934#define CRC32_RESIDUAL 0xdebb20e3
1935
1936static int bnx2x_test_nvram(struct bnx2x *bp)
1937{
1938 static const struct {
1939 int offset;
1940 int size;
1941 } nvram_tbl[] = {
1942 { 0, 0x14 }, /* bootstrap */
1943 { 0x14, 0xec }, /* dir */
1944 { 0x100, 0x350 }, /* manuf_info */
1945 { 0x450, 0xf0 }, /* feature_info */
1946 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 1947 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 1948 { 0, 0 }
1949 };
1950 __be32 buf[0x350 / 4];
1951 u8 *data = (u8 *)buf;
1952 int i, rc;
1953 u32 magic, crc;
1954
1955 if (BP_NOMCP(bp))
1956 return 0;
1957
1958 rc = bnx2x_nvram_read(bp, 0, data, 4);
1959 if (rc) {
1960 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1961 goto test_nvram_exit;
1962 }
1963
1964 magic = be32_to_cpu(buf[0]);
1965 if (magic != 0x669955aa) {
1966 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1967 rc = -ENODEV;
1968 goto test_nvram_exit;
1969 }
1970
1971 for (i = 0; nvram_tbl[i].size; i++) {
1972
1973 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1974 nvram_tbl[i].size);
1975 if (rc) {
1976 DP(NETIF_MSG_PROBE,
1977 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1978 goto test_nvram_exit;
1979 }
1980
1981 crc = ether_crc_le(nvram_tbl[i].size, data);
1982 if (crc != CRC32_RESIDUAL) {
1983 DP(NETIF_MSG_PROBE,
1984 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1985 rc = -ENODEV;
1986 goto test_nvram_exit;
1987 }
1988 }
1989
1990test_nvram_exit:
1991 return rc;
1992}
1993
619c5cb6 1994/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 1995static int bnx2x_test_intr(struct bnx2x *bp)
1996{
619c5cb6 1997 struct bnx2x_queue_state_params params = {0};
de0c62db
DK		 1998
1999 if (!netif_running(bp->dev))
2000 return -ENODEV;
2001
619c5cb6
VZ		 2002 params.q_obj = &bp->fp->q_obj;
2003 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2004
619c5cb6
VZ		 2005 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2006
2007 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2008}
2009
2010static void bnx2x_self_test(struct net_device *dev,
2011 struct ethtool_test *etest, u64 *buf)
2012{
2013 struct bnx2x *bp = netdev_priv(dev);
a22f0788 2014 u8 is_serdes;
de0c62db 2015 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
f1deab50 2016 pr_err("Handling parity error recovery. Try again later\n");
de0c62db
DK		 2017 etest->flags |= ETH_TEST_FL_FAILED;
2018 return;
2019 }
2020
2021 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
2022
2023 if (!netif_running(dev))
2024 return;
2025
2026 /* offline tests are not supported in MF mode */
fb3bff17 2027 if (IS_MF(bp))
de0c62db 2028 etest->flags &= ~ETH_TEST_FL_OFFLINE;
a22f0788 2029 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db
DK		 2030
2031 if (etest->flags & ETH_TEST_FL_OFFLINE) {
2032 int port = BP_PORT(bp);
2033 u32 val;
2034 u8 link_up;
2035
2036 /* save current value of input enable for TX port IF */
2037 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2038 /* disable input for TX port IF */
2039 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2040
a22f0788
YR		 2041 link_up = bp->link_vars.link_up;
2042
de0c62db
DK		 2043 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2044 bnx2x_nic_load(bp, LOAD_DIAG);
2045 /* wait until link state is restored */
619c5cb6 2046 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2047
2048 if (bnx2x_test_registers(bp) != 0) {
2049 buf[0] = 1;
2050 etest->flags |= ETH_TEST_FL_FAILED;
2051 }
2052 if (bnx2x_test_memory(bp) != 0) {
2053 buf[1] = 1;
2054 etest->flags |= ETH_TEST_FL_FAILED;
2055 }
f85582f8 2056
619c5cb6 2057 buf[2] = bnx2x_test_loopback(bp);
de0c62db
DK		 2058 if (buf[2] != 0)
2059 etest->flags |= ETH_TEST_FL_FAILED;
2060
2061 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2062
2063 /* restore input for TX port IF */
2064 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2065
2066 bnx2x_nic_load(bp, LOAD_NORMAL);
2067 /* wait until link state is restored */
a22f0788 2068 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2069 }
2070 if (bnx2x_test_nvram(bp) != 0) {
2071 buf[3] = 1;
2072 etest->flags |= ETH_TEST_FL_FAILED;
2073 }
2074 if (bnx2x_test_intr(bp) != 0) {
2075 buf[4] = 1;
2076 etest->flags |= ETH_TEST_FL_FAILED;
2077 }
633ac363
DK		 2078
2079 if (bnx2x_link_test(bp, is_serdes) != 0) {
2080 buf[5] = 1;
2081 etest->flags |= ETH_TEST_FL_FAILED;
2082 }
de0c62db
DK		 2083
2084#ifdef BNX2X_EXTRA_DEBUG
2085 bnx2x_panic_dump(bp);
2086#endif
2087}
2088
de0c62db
DK		 2089#define IS_PORT_STAT(i) \
2090 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2091#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2092#define IS_MF_MODE_STAT(bp) \
2093 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2094
619c5cb6
VZ		 2095/* ethtool statistics are displayed for all regular ethernet queues and the
2096 * fcoe L2 queue if not disabled
2097 */
2098static inline int bnx2x_num_stat_queues(struct bnx2x *bp)
2099{
2100 return BNX2X_NUM_ETH_QUEUES(bp);
2101}
2102
de0c62db
DK		 2103static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2104{
2105 struct bnx2x *bp = netdev_priv(dev);
2106 int i, num_stats;
2107
2108 switch (stringset) {
2109 case ETH_SS_STATS:
2110 if (is_multi(bp)) {
619c5cb6 2111 num_stats = bnx2x_num_stat_queues(bp) *
ec6ba945 2112 BNX2X_NUM_Q_STATS;
fb3bff17 2113 if (!IS_MF_MODE_STAT(bp))
de0c62db
DK		 2114 num_stats += BNX2X_NUM_STATS;
2115 } else {
fb3bff17 2116 if (IS_MF_MODE_STAT(bp)) {
de0c62db
DK		 2117 num_stats = 0;
2118 for (i = 0; i < BNX2X_NUM_STATS; i++)
2119 if (IS_FUNC_STAT(i))
2120 num_stats++;
2121 } else
2122 num_stats = BNX2X_NUM_STATS;
2123 }
2124 return num_stats;
2125
2126 case ETH_SS_TEST:
2127 return BNX2X_NUM_TESTS;
2128
2129 default:
2130 return -EINVAL;
2131 }
2132}
2133
2134static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2135{
2136 struct bnx2x *bp = netdev_priv(dev);
2137 int i, j, k;
ec6ba945 2138 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2139
2140 switch (stringset) {
2141 case ETH_SS_STATS:
2142 if (is_multi(bp)) {
2143 k = 0;
619c5cb6 2144 for_each_eth_queue(bp, i) {
ec6ba945 2145 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2146 sprintf(queue_name, "%d", i);
de0c62db 2147 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2148 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2149 ETH_GSTRING_LEN,
2150 bnx2x_q_stats_arr[j].string,
2151 queue_name);
de0c62db
DK		 2152 k += BNX2X_NUM_Q_STATS;
2153 }
fb3bff17 2154 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 2155 break;
2156 for (j = 0; j < BNX2X_NUM_STATS; j++)
2157 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2158 bnx2x_stats_arr[j].string);
2159 } else {
2160 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 2161 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 2162 continue;
2163 strcpy(buf + j*ETH_GSTRING_LEN,
2164 bnx2x_stats_arr[i].string);
2165 j++;
2166 }
2167 }
2168 break;
2169
2170 case ETH_SS_TEST:
2171 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2172 break;
2173 }
2174}
2175
2176static void bnx2x_get_ethtool_stats(struct net_device *dev,
2177 struct ethtool_stats *stats, u64 *buf)
2178{
2179 struct bnx2x *bp = netdev_priv(dev);
2180 u32 *hw_stats, *offset;
2181 int i, j, k;
2182
2183 if (is_multi(bp)) {
2184 k = 0;
619c5cb6 2185 for_each_eth_queue(bp, i) {
de0c62db
DK		 2186 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2187 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2188 if (bnx2x_q_stats_arr[j].size == 0) {
2189 /* skip this counter */
2190 buf[k + j] = 0;
2191 continue;
2192 }
2193 offset = (hw_stats +
2194 bnx2x_q_stats_arr[j].offset);
2195 if (bnx2x_q_stats_arr[j].size == 4) {
2196 /* 4-byte counter */
2197 buf[k + j] = (u64) *offset;
2198 continue;
2199 }
2200 /* 8-byte counter */
2201 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2202 }
2203 k += BNX2X_NUM_Q_STATS;
2204 }
fb3bff17 2205 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 2206 return;
2207 hw_stats = (u32 *)&bp->eth_stats;
2208 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2209 if (bnx2x_stats_arr[j].size == 0) {
2210 /* skip this counter */
2211 buf[k + j] = 0;
2212 continue;
2213 }
2214 offset = (hw_stats + bnx2x_stats_arr[j].offset);
2215 if (bnx2x_stats_arr[j].size == 4) {
2216 /* 4-byte counter */
2217 buf[k + j] = (u64) *offset;
2218 continue;
2219 }
2220 /* 8-byte counter */
2221 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2222 }
2223 } else {
2224 hw_stats = (u32 *)&bp->eth_stats;
2225 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 2226 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 2227 continue;
2228 if (bnx2x_stats_arr[i].size == 0) {
2229 /* skip this counter */
2230 buf[j] = 0;
2231 j++;
2232 continue;
2233 }
2234 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2235 if (bnx2x_stats_arr[i].size == 4) {
2236 /* 4-byte counter */
2237 buf[j] = (u64) *offset;
2238 j++;
2239 continue;
2240 }
2241 /* 8-byte counter */
2242 buf[j] = HILO_U64(*offset, *(offset + 1));
2243 j++;
2244 }
2245 }
2246}
2247
32d36134 2248static int bnx2x_set_phys_id(struct net_device *dev,
2249 enum ethtool_phys_id_state state)
de0c62db
DK		 2250{
2251 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 2252
2253 if (!netif_running(dev))
32d36134 2254 return -EAGAIN;
de0c62db
DK		 2255
2256 if (!bp->port.pmf)
32d36134 2257 return -EOPNOTSUPP;
de0c62db 2258
32d36134 2259 switch (state) {
2260 case ETHTOOL_ID_ACTIVE:
fce55922 2261 return 1; /* cycle on/off once per second */
de0c62db 2262
32d36134 2263 case ETHTOOL_ID_ON:
2264 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2265 LED_MODE_ON, SPEED_1000);
32d36134 2266 break;
de0c62db 2267
32d36134 2268 case ETHTOOL_ID_OFF:
2269 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2270 LED_MODE_FRONT_PANEL_OFF, 0);
de0c62db 2271
32d36134 2272 break;
2273
2274 case ETHTOOL_ID_INACTIVE:
e1943424
DM		 2275 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2276 LED_MODE_OPER,
2277 bp->link_vars.line_speed);
32d36134 2278 }
de0c62db
DK		 2279
2280 return 0;
2281}
2282
ab532cf3 2283static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2284 u32 *rules __always_unused)
ab532cf3
TH		 2285{
2286 struct bnx2x *bp = netdev_priv(dev);
2287
2288 switch (info->cmd) {
2289 case ETHTOOL_GRXRINGS:
2290 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2291 return 0;
2292
2293 default:
2294 return -EOPNOTSUPP;
2295 }
2296}
2297
2298static int bnx2x_get_rxfh_indir(struct net_device *dev,
2299 struct ethtool_rxfh_indir *indir)
2300{
2301 struct bnx2x *bp = netdev_priv(dev);
2302 size_t copy_size =
619c5cb6
VZ		 2303 min_t(size_t, indir->size, T_ETH_INDIRECTION_TABLE_SIZE);
2304 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2305 size_t i;
ab532cf3
TH		 2306
2307 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2308 return -EOPNOTSUPP;
2309
619c5cb6
VZ		 2310 /* Get the current configuration of the RSS indirection table */
2311 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2312
2313 /*
2314 * We can't use a memcpy() as an internal storage of an
2315 * indirection table is a u8 array while indir->ring_index
2316 * points to an array of u32.
2317 *
2318 * Indirection table contains the FW Client IDs, so we need to
2319 * align the returned table to the Client ID of the leading RSS
2320 * queue.
2321 */
2322 for (i = 0; i < copy_size; i++)
2323 indir->ring_index[i] = ind_table[i] - bp->fp->cl_id;
2324
2325 indir->size = T_ETH_INDIRECTION_TABLE_SIZE;
2326
ab532cf3
TH		 2327 return 0;
2328}
2329
2330static int bnx2x_set_rxfh_indir(struct net_device *dev,
2331 const struct ethtool_rxfh_indir *indir)
2332{
2333 struct bnx2x *bp = netdev_priv(dev);
2334 size_t i;
619c5cb6
VZ		 2335 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2336 u32 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
ab532cf3
TH		 2337
2338 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2339 return -EOPNOTSUPP;
2340
619c5cb6
VZ		 2341 /* validate the size */
2342 if (indir->size != T_ETH_INDIRECTION_TABLE_SIZE)
ab532cf3 2343 return -EINVAL;
619c5cb6
VZ		 2344
2345 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2346 /* validate the indices */
2347 if (indir->ring_index[i] >= num_eth_queues)
ab532cf3 2348 return -EINVAL;
619c5cb6
VZ		 2349 /*
2350 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2351 * as an internal storage of an indirection table is a u8 array
2352 * while indir->ring_index points to an array of u32.
2353 *
2354 * Indirection table contains the FW Client IDs, so we need to
2355 * align the received table to the Client ID of the leading RSS
2356 * queue
2357 */
2358 ind_table[i] = indir->ring_index[i] + bp->fp->cl_id;
2359 }
ab532cf3 2360
619c5cb6 2361 return bnx2x_config_rss_pf(bp, ind_table, false);
ab532cf3
TH		 2362}
2363
de0c62db
DK		 2364static const struct ethtool_ops bnx2x_ethtool_ops = {
2365 .get_settings = bnx2x_get_settings,
2366 .set_settings = bnx2x_set_settings,
2367 .get_drvinfo = bnx2x_get_drvinfo,
2368 .get_regs_len = bnx2x_get_regs_len,
2369 .get_regs = bnx2x_get_regs,
2370 .get_wol = bnx2x_get_wol,
2371 .set_wol = bnx2x_set_wol,
2372 .get_msglevel = bnx2x_get_msglevel,
2373 .set_msglevel = bnx2x_set_msglevel,
2374 .nway_reset = bnx2x_nway_reset,
2375 .get_link = bnx2x_get_link,
2376 .get_eeprom_len = bnx2x_get_eeprom_len,
2377 .get_eeprom = bnx2x_get_eeprom,
2378 .set_eeprom = bnx2x_set_eeprom,
2379 .get_coalesce = bnx2x_get_coalesce,
2380 .set_coalesce = bnx2x_set_coalesce,
2381 .get_ringparam = bnx2x_get_ringparam,
2382 .set_ringparam = bnx2x_set_ringparam,
2383 .get_pauseparam = bnx2x_get_pauseparam,
2384 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 2385 .self_test = bnx2x_self_test,
2386 .get_sset_count = bnx2x_get_sset_count,
2387 .get_strings = bnx2x_get_strings,
32d36134 2388 .set_phys_id = bnx2x_set_phys_id,
de0c62db 2389 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3
TH		 2390 .get_rxnfc = bnx2x_get_rxnfc,
2391 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2392 .set_rxfh_indir = bnx2x_set_rxfh_indir,
de0c62db
DK		 2393};
2394
2395void bnx2x_set_ethtool_ops(struct net_device *netdev)
2396{
2397 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2398}
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