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bnx2x: Added nvram personalities support
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
85b26ea1 3 * Copyright (c) 2007-2012 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
de0c62db
DK		 25#include "bnx2x.h"
26#include "bnx2x_cmn.h"
27#include "bnx2x_dump.h"
4a33bc03 28#include "bnx2x_init.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
c96bdc0c
DK		 65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
67 4, "[%s]: driver_filtered_tx_pkt" }
ec6ba945
VZ		 68};
69
70#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
71
72static const struct {
73 long offset;
74 int size;
75 u32 flags;
76#define STATS_FLAGS_PORT 1
77#define STATS_FLAGS_FUNC 2
78#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
79 char string[ETH_GSTRING_LEN];
80} bnx2x_stats_arr[] = {
81/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_bytes" },
83 { STATS_OFFSET32(error_bytes_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
85 { STATS_OFFSET32(total_unicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
87 { STATS_OFFSET32(total_multicast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
89 { STATS_OFFSET32(total_broadcast_packets_received_hi),
90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
92 8, STATS_FLAGS_PORT, "rx_crc_errors" },
93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
94 8, STATS_FLAGS_PORT, "rx_align_errors" },
95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
98 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
99/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
100 8, STATS_FLAGS_PORT, "rx_fragments" },
101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
102 8, STATS_FLAGS_PORT, "rx_jabbers" },
103 { STATS_OFFSET32(no_buff_discard_hi),
104 8, STATS_FLAGS_BOTH, "rx_discards" },
105 { STATS_OFFSET32(mac_filter_discard),
106 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 107 { STATS_OFFSET32(mf_tag_discard),
108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 109 { STATS_OFFSET32(pfc_frames_received_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_received" },
111 { STATS_OFFSET32(pfc_frames_sent_hi),
112 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 113 { STATS_OFFSET32(brb_drop_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_discard" },
115 { STATS_OFFSET32(brb_truncate_hi),
116 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
117 { STATS_OFFSET32(pause_frames_received_hi),
118 8, STATS_FLAGS_PORT, "rx_pause_frames" },
119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
121 { STATS_OFFSET32(nig_timer_max),
122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
123/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
125 { STATS_OFFSET32(rx_skb_alloc_failed),
126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
127 { STATS_OFFSET32(hw_csum_err),
128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
129
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, STATS_FLAGS_PORT, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, STATS_FLAGS_PORT, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
144/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, STATS_FLAGS_PORT, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, STATS_FLAGS_PORT, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
164/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 171 8, STATS_FLAGS_PORT, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 177 8, STATS_FLAGS_FUNC, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, STATS_FLAGS_FUNC, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
c96bdc0c
DK		 182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
e9939c80
YM		 184 { STATS_OFFSET32(eee_tx_lpi),
185 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
ec6ba945
VZ		 186};
187
188#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
1ac9e428
YR		 189static int bnx2x_get_port_type(struct bnx2x *bp)
190{
191 int port_type;
192 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
193 switch (bp->link_params.phy[phy_idx].media_type) {
dbef807e
YM		 194 case ETH_PHY_SFPP_10G_FIBER:
195 case ETH_PHY_SFP_1G_FIBER:
1ac9e428
YR		 196 case ETH_PHY_XFP_FIBER:
197 case ETH_PHY_KR:
198 case ETH_PHY_CX4:
199 port_type = PORT_FIBRE;
200 break;
201 case ETH_PHY_DA_TWINAX:
202 port_type = PORT_DA;
203 break;
204 case ETH_PHY_BASE_T:
205 port_type = PORT_TP;
206 break;
207 case ETH_PHY_NOT_PRESENT:
208 port_type = PORT_NONE;
209 break;
210 case ETH_PHY_UNSPECIFIED:
211 default:
212 port_type = PORT_OTHER;
213 break;
214 }
215 return port_type;
216}
ec6ba945 217
de0c62db
DK		 218static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
219{
220 struct bnx2x *bp = netdev_priv(dev);
a22f0788 221 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 222
a22f0788
YR		 223 /* Dual Media boards present all available port types */
224 cmd->supported = bp->port.supported[cfg_idx] |
225 (bp->port.supported[cfg_idx ^ 1] &
226 (SUPPORTED_TP | SUPPORTED_FIBRE));
227 cmd->advertising = bp->port.advertising[cfg_idx];
dbef807e
YM		 228 if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
229 ETH_PHY_SFP_1G_FIBER) {
230 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
231 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
232 }
de0c62db 233
59694f00
YM		 234 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
235 !(bp->flags & MF_FUNC_DIS)) {
38298461 236 cmd->duplex = bp->link_vars.duplex;
38298461
YM		 237
238 if (IS_MF(bp) && !BP_NOMCP(bp))
239 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
59694f00
YM		 240 else
241 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
de0c62db 242 } else {
38298461
YM		 243 cmd->duplex = DUPLEX_UNKNOWN;
244 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
de0c62db 245 }
f2e0899f 246
1ac9e428 247 cmd->port = bnx2x_get_port_type(bp);
a22f0788 248
de0c62db
DK		 249 cmd->phy_address = bp->mdio.prtad;
250 cmd->transceiver = XCVR_INTERNAL;
251
a22f0788 252 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 253 cmd->autoneg = AUTONEG_ENABLE;
254 else
255 cmd->autoneg = AUTONEG_DISABLE;
256
9e7e8399
MY		 257 /* Publish LP advertised speeds and FC */
258 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
259 u32 status = bp->link_vars.link_status;
260
261 cmd->lp_advertising |= ADVERTISED_Autoneg;
262 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
263 cmd->lp_advertising |= ADVERTISED_Pause;
264 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
265 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
266
267 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
268 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
269 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
270 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
271 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
272 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
273 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
274 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
275 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
276 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
277 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
278 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
279 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
280 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
281 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
282 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
283 }
284
de0c62db
DK		 285 cmd->maxtxpkt = 0;
286 cmd->maxrxpkt = 0;
287
51c1a580 288 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 289 " supported 0x%x advertising 0x%x speed %u\n"
290 " duplex %d port %d phy_address %d transceiver %d\n"
291 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 292 cmd->cmd, cmd->supported, cmd->advertising,
293 ethtool_cmd_speed(cmd),
de0c62db
DK		 294 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
295 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
296
297 return 0;
298}
299
300static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
301{
302 struct bnx2x *bp = netdev_priv(dev);
a22f0788 303 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
dbef807e 304 u32 speed, phy_idx;
de0c62db 305
0793f83f 306 if (IS_MF_SD(bp))
de0c62db
DK		 307 return 0;
308
51c1a580 309 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
b3337e4c 310 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 311 " duplex %d port %d phy_address %d transceiver %d\n"
312 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 313 cmd->cmd, cmd->supported, cmd->advertising,
314 ethtool_cmd_speed(cmd),
de0c62db
DK		 315 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
316 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
317
b3337e4c 318 speed = ethtool_cmd_speed(cmd);
0793f83f 319
38298461
YM		 320 /* If recieved a request for an unknown duplex, assume full*/
321 if (cmd->duplex == DUPLEX_UNKNOWN)
322 cmd->duplex = DUPLEX_FULL;
323
0793f83f 324 if (IS_MF_SI(bp)) {
e3835b99 325 u32 part;
0793f83f
DK		 326 u32 line_speed = bp->link_vars.line_speed;
327
328 /* use 10G if no link detected */
329 if (!line_speed)
330 line_speed = 10000;
331
332 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
51c1a580
MS		 333 DP(BNX2X_MSG_ETHTOOL,
334 "To set speed BC %X or higher is required, please upgrade BC\n",
335 REQ_BC_VER_4_SET_MF_BW);
0793f83f
DK		 336 return -EINVAL;
337 }
e3835b99 338
faa6fcbb 339 part = (speed * 100) / line_speed;
e3835b99 340
faa6fcbb 341 if (line_speed < speed || !part) {
51c1a580
MS		 342 DP(BNX2X_MSG_ETHTOOL,
343 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
0793f83f
DK		 344 return -EINVAL;
345 }
0793f83f 346
e3835b99
DK		 347 if (bp->state != BNX2X_STATE_OPEN)
348 /* store value for following "load" */
349 bp->pending_max = part;
350 else
351 bnx2x_update_max_mf_config(bp, part);
0793f83f 352
0793f83f
DK		 353 return 0;
354 }
355
a22f0788
YR		 356 cfg_idx = bnx2x_get_link_cfg_idx(bp);
357 old_multi_phy_config = bp->link_params.multi_phy_config;
358 switch (cmd->port) {
359 case PORT_TP:
360 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
361 break; /* no port change */
362
363 if (!(bp->port.supported[0] & SUPPORTED_TP ||
364 bp->port.supported[1] & SUPPORTED_TP)) {
51c1a580 365 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 366 return -EINVAL;
367 }
368 bp->link_params.multi_phy_config &=
369 ~PORT_HW_CFG_PHY_SELECTION_MASK;
370 if (bp->link_params.multi_phy_config &
371 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
372 bp->link_params.multi_phy_config |=
373 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
374 else
375 bp->link_params.multi_phy_config |=
376 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
377 break;
378 case PORT_FIBRE:
bfdb5823 379 case PORT_DA:
a22f0788
YR		 380 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
381 break; /* no port change */
382
383 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
384 bp->port.supported[1] & SUPPORTED_FIBRE)) {
51c1a580 385 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 386 return -EINVAL;
387 }
388 bp->link_params.multi_phy_config &=
389 ~PORT_HW_CFG_PHY_SELECTION_MASK;
390 if (bp->link_params.multi_phy_config &
391 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
392 bp->link_params.multi_phy_config |=
393 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
394 else
395 bp->link_params.multi_phy_config |=
396 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
397 break;
398 default:
51c1a580 399 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 400 return -EINVAL;
401 }
2f751a80 402 /* Save new config in case command complete successully */
a22f0788
YR		 403 new_multi_phy_config = bp->link_params.multi_phy_config;
404 /* Get the new cfg_idx */
405 cfg_idx = bnx2x_get_link_cfg_idx(bp);
406 /* Restore old config in case command failed */
407 bp->link_params.multi_phy_config = old_multi_phy_config;
51c1a580 408 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
a22f0788 409
de0c62db 410 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 411 u32 an_supported_speed = bp->port.supported[cfg_idx];
412 if (bp->link_params.phy[EXT_PHY1].type ==
413 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
414 an_supported_speed |= (SUPPORTED_100baseT_Half |
415 SUPPORTED_100baseT_Full);
a22f0788 416 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 417 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
de0c62db
DK		 418 return -EINVAL;
419 }
420
421 /* advertise the requested speed and duplex if supported */
75318327 422 if (cmd->advertising & ~an_supported_speed) {
51c1a580
MS		 423 DP(BNX2X_MSG_ETHTOOL,
424 "Advertisement parameters are not supported\n");
8d661637
YR		 425 return -EINVAL;
426 }
de0c62db 427
a22f0788 428 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 429 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
430 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 431 cmd->advertising);
8d661637
YR		 432 if (cmd->advertising) {
433
434 bp->link_params.speed_cap_mask[cfg_idx] = 0;
435 if (cmd->advertising & ADVERTISED_10baseT_Half) {
436 bp->link_params.speed_cap_mask[cfg_idx] |=
437 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
438 }
439 if (cmd->advertising & ADVERTISED_10baseT_Full)
440 bp->link_params.speed_cap_mask[cfg_idx] |=
441 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 442
8d661637
YR		 443 if (cmd->advertising & ADVERTISED_100baseT_Full)
444 bp->link_params.speed_cap_mask[cfg_idx] |=
445 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
446
447 if (cmd->advertising & ADVERTISED_100baseT_Half) {
448 bp->link_params.speed_cap_mask[cfg_idx] |=
449 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
450 }
451 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
452 bp->link_params.speed_cap_mask[cfg_idx] |=
453 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
454 }
455 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
456 ADVERTISED_1000baseKX_Full))
457 bp->link_params.speed_cap_mask[cfg_idx] |=
458 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
459
460 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
461 ADVERTISED_10000baseKX4_Full |
462 ADVERTISED_10000baseKR_Full))
463 bp->link_params.speed_cap_mask[cfg_idx] |=
464 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
465 }
de0c62db
DK		 466 } else { /* forced speed */
467 /* advertise the requested speed and duplex if supported */
a22f0788 468 switch (speed) {
de0c62db
DK		 469 case SPEED_10:
470 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 471 if (!(bp->port.supported[cfg_idx] &
de0c62db 472 SUPPORTED_10baseT_Full)) {
51c1a580 473 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 474 "10M full not supported\n");
475 return -EINVAL;
476 }
477
478 advertising = (ADVERTISED_10baseT_Full |
479 ADVERTISED_TP);
480 } else {
a22f0788 481 if (!(bp->port.supported[cfg_idx] &
de0c62db 482 SUPPORTED_10baseT_Half)) {
51c1a580 483 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 484 "10M half not supported\n");
485 return -EINVAL;
486 }
487
488 advertising = (ADVERTISED_10baseT_Half |
489 ADVERTISED_TP);
490 }
491 break;
492
493 case SPEED_100:
494 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 495 if (!(bp->port.supported[cfg_idx] &
de0c62db 496 SUPPORTED_100baseT_Full)) {
51c1a580 497 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 498 "100M full not supported\n");
499 return -EINVAL;
500 }
501
502 advertising = (ADVERTISED_100baseT_Full |
503 ADVERTISED_TP);
504 } else {
a22f0788 505 if (!(bp->port.supported[cfg_idx] &
de0c62db 506 SUPPORTED_100baseT_Half)) {
51c1a580 507 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 508 "100M half not supported\n");
509 return -EINVAL;
510 }
511
512 advertising = (ADVERTISED_100baseT_Half |
513 ADVERTISED_TP);
514 }
515 break;
516
517 case SPEED_1000:
518 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 519 DP(BNX2X_MSG_ETHTOOL,
520 "1G half not supported\n");
de0c62db
DK		 521 return -EINVAL;
522 }
523
a22f0788
YR		 524 if (!(bp->port.supported[cfg_idx] &
525 SUPPORTED_1000baseT_Full)) {
51c1a580
MS		 526 DP(BNX2X_MSG_ETHTOOL,
527 "1G full not supported\n");
de0c62db
DK		 528 return -EINVAL;
529 }
530
531 advertising = (ADVERTISED_1000baseT_Full |
532 ADVERTISED_TP);
533 break;
534
535 case SPEED_2500:
536 if (cmd->duplex != DUPLEX_FULL) {
51c1a580 537 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 538 "2.5G half not supported\n");
539 return -EINVAL;
540 }
541
a22f0788
YR		 542 if (!(bp->port.supported[cfg_idx]
543 & SUPPORTED_2500baseX_Full)) {
51c1a580 544 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 545 "2.5G full not supported\n");
546 return -EINVAL;
547 }
548
549 advertising = (ADVERTISED_2500baseX_Full |
550 ADVERTISED_TP);
551 break;
552
553 case SPEED_10000:
554 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 555 DP(BNX2X_MSG_ETHTOOL,
556 "10G half not supported\n");
de0c62db
DK		 557 return -EINVAL;
558 }
dbef807e 559 phy_idx = bnx2x_get_cur_phy_idx(bp);
a22f0788 560 if (!(bp->port.supported[cfg_idx]
dbef807e
YM		 561 & SUPPORTED_10000baseT_Full) ||
562 (bp->link_params.phy[phy_idx].media_type ==
563 ETH_PHY_SFP_1G_FIBER)) {
51c1a580
MS		 564 DP(BNX2X_MSG_ETHTOOL,
565 "10G full not supported\n");
de0c62db
DK		 566 return -EINVAL;
567 }
568
569 advertising = (ADVERTISED_10000baseT_Full |
570 ADVERTISED_FIBRE);
571 break;
572
573 default:
51c1a580 574 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
de0c62db
DK		 575 return -EINVAL;
576 }
577
a22f0788
YR		 578 bp->link_params.req_line_speed[cfg_idx] = speed;
579 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
580 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 581 }
582
51c1a580 583 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
f1deab50 584 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 585 bp->link_params.req_line_speed[cfg_idx],
586 bp->link_params.req_duplex[cfg_idx],
587 bp->port.advertising[cfg_idx]);
de0c62db 588
a22f0788
YR		 589 /* Set new config */
590 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 591 if (netif_running(dev)) {
592 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
593 bnx2x_link_set(bp);
594 }
595
596 return 0;
597}
598
599#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
600#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 601#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
0fea29c1
VZ		 602#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
603#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
604
1191cb83
ED		 605static bool bnx2x_is_reg_online(struct bnx2x *bp,
606 const struct reg_addr *reg_info)
0fea29c1
VZ		 607{
608 if (CHIP_IS_E1(bp))
609 return IS_E1_ONLINE(reg_info->info);
610 else if (CHIP_IS_E1H(bp))
611 return IS_E1H_ONLINE(reg_info->info);
612 else if (CHIP_IS_E2(bp))
613 return IS_E2_ONLINE(reg_info->info);
614 else if (CHIP_IS_E3A0(bp))
615 return IS_E3_ONLINE(reg_info->info);
616 else if (CHIP_IS_E3B0(bp))
617 return IS_E3B0_ONLINE(reg_info->info);
618 else
619 return false;
620}
621
622/******* Paged registers info selectors ********/
1191cb83 623static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
0fea29c1
VZ		 624{
625 if (CHIP_IS_E2(bp))
626 return page_vals_e2;
627 else if (CHIP_IS_E3(bp))
628 return page_vals_e3;
629 else
630 return NULL;
631}
632
1191cb83 633static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
0fea29c1
VZ		 634{
635 if (CHIP_IS_E2(bp))
636 return PAGE_MODE_VALUES_E2;
637 else if (CHIP_IS_E3(bp))
638 return PAGE_MODE_VALUES_E3;
639 else
640 return 0;
641}
642
1191cb83 643static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
0fea29c1
VZ		 644{
645 if (CHIP_IS_E2(bp))
646 return page_write_regs_e2;
647 else if (CHIP_IS_E3(bp))
648 return page_write_regs_e3;
649 else
650 return NULL;
651}
652
1191cb83 653static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
0fea29c1
VZ		 654{
655 if (CHIP_IS_E2(bp))
656 return PAGE_WRITE_REGS_E2;
657 else if (CHIP_IS_E3(bp))
658 return PAGE_WRITE_REGS_E3;
659 else
660 return 0;
661}
662
1191cb83 663static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
0fea29c1
VZ		 664{
665 if (CHIP_IS_E2(bp))
666 return page_read_regs_e2;
667 else if (CHIP_IS_E3(bp))
668 return page_read_regs_e3;
669 else
670 return NULL;
671}
672
1191cb83 673static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
0fea29c1
VZ		 674{
675 if (CHIP_IS_E2(bp))
676 return PAGE_READ_REGS_E2;
677 else if (CHIP_IS_E3(bp))
678 return PAGE_READ_REGS_E3;
679 else
680 return 0;
681}
682
1191cb83 683static int __bnx2x_get_regs_len(struct bnx2x *bp)
0fea29c1
VZ		 684{
685 int num_pages = __bnx2x_get_page_reg_num(bp);
686 int page_write_num = __bnx2x_get_page_write_num(bp);
687 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
688 int page_read_num = __bnx2x_get_page_read_num(bp);
689 int regdump_len = 0;
690 int i, j, k;
691
692 for (i = 0; i < REGS_COUNT; i++)
693 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
694 regdump_len += reg_addrs[i].size;
695
696 for (i = 0; i < num_pages; i++)
697 for (j = 0; j < page_write_num; j++)
698 for (k = 0; k < page_read_num; k++)
699 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
700 regdump_len += page_read_addr[k].size;
701
702 return regdump_len;
703}
de0c62db
DK		 704
705static int bnx2x_get_regs_len(struct net_device *dev)
706{
707 struct bnx2x *bp = netdev_priv(dev);
708 int regdump_len = 0;
de0c62db 709
0fea29c1 710 regdump_len = __bnx2x_get_regs_len(bp);
de0c62db
DK		 711 regdump_len *= 4;
712 regdump_len += sizeof(struct dump_hdr);
713
714 return regdump_len;
715}
716
0fea29c1
VZ		 717/**
718 * bnx2x_read_pages_regs - read "paged" registers
719 *
720 * @bp device handle
721 * @p output buffer
722 *
723 * Reads "paged" memories: memories that may only be read by first writing to a
724 * specific address ("write address") and then reading from a specific address
725 * ("read address"). There may be more than one write address per "page" and
726 * more than one read address per write address.
727 */
1191cb83 728static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
f2e0899f
DK		 729{
730 u32 i, j, k, n;
0fea29c1
VZ		 731 /* addresses of the paged registers */
732 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
733 /* number of paged registers */
734 int num_pages = __bnx2x_get_page_reg_num(bp);
735 /* write addresses */
736 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
737 /* number of write addresses */
738 int write_num = __bnx2x_get_page_write_num(bp);
739 /* read addresses info */
740 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
741 /* number of read addresses */
742 int read_num = __bnx2x_get_page_read_num(bp);
743
744 for (i = 0; i < num_pages; i++) {
745 for (j = 0; j < write_num; j++) {
746 REG_WR(bp, write_addr[j], page_addr[i]);
747 for (k = 0; k < read_num; k++)
748 if (bnx2x_is_reg_online(bp, &read_addr[k]))
f2e0899f 749 for (n = 0; n <
0fea29c1 750 read_addr[k].size; n++)
f2e0899f 751 *p++ = REG_RD(bp,
0fea29c1 752 read_addr[k].addr + n*4);
f2e0899f
DK		 753 }
754 }
755}
756
1191cb83 757static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
0fea29c1
VZ		 758{
759 u32 i, j;
760
761 /* Read the regular registers */
762 for (i = 0; i < REGS_COUNT; i++)
763 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
764 for (j = 0; j < reg_addrs[i].size; j++)
765 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
766
767 /* Read "paged" registes */
768 bnx2x_read_pages_regs(bp, p);
769}
770
de0c62db
DK		 771static void bnx2x_get_regs(struct net_device *dev,
772 struct ethtool_regs *regs, void *_p)
773{
0fea29c1 774 u32 *p = _p;
de0c62db
DK		 775 struct bnx2x *bp = netdev_priv(dev);
776 struct dump_hdr dump_hdr = {0};
777
2ace9510 778 regs->version = 1;
de0c62db
DK		 779 memset(p, 0, regs->len);
780
781 if (!netif_running(bp->dev))
782 return;
783
4a33bc03
VZ		 784 /* Disable parity attentions as long as following dump may
785 * cause false alarms by reading never written registers. We
786 * will re-enable parity attentions right after the dump.
787 */
788 bnx2x_disable_blocks_parity(bp);
789
de0c62db
DK		 790 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
791 dump_hdr.dump_sign = dump_sign_all;
792 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
793 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
794 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
795 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 796
797 if (CHIP_IS_E1(bp))
798 dump_hdr.info = RI_E1_ONLINE;
799 else if (CHIP_IS_E1H(bp))
800 dump_hdr.info = RI_E1H_ONLINE;
619c5cb6 801 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 802 dump_hdr.info = RI_E2_ONLINE |
803 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 804
805 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
806 p += dump_hdr.hdr_size + 1;
807
0fea29c1
VZ		 808 /* Actually read the registers */
809 __bnx2x_get_regs(bp, p);
810
4a33bc03
VZ		 811 /* Re-enable parity attentions */
812 bnx2x_clear_blocks_parity(bp);
c9ee9206 813 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 814}
815
de0c62db
DK		 816static void bnx2x_get_drvinfo(struct net_device *dev,
817 struct ethtool_drvinfo *info)
818{
819 struct bnx2x *bp = netdev_priv(dev);
de0c62db 820
68aad78c
RJ		 821 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
822 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db 823
8ca5e17e
AE		 824 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
825
68aad78c 826 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db 827 info->n_stats = BNX2X_NUM_STATS;
cf2c1df6 828 info->testinfo_len = BNX2X_NUM_TESTS(bp);
de0c62db
DK		 829 info->eedump_len = bp->common.flash_size;
830 info->regdump_len = bnx2x_get_regs_len(dev);
831}
832
833static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
834{
835 struct bnx2x *bp = netdev_priv(dev);
836
837 if (bp->flags & NO_WOL_FLAG) {
838 wol->supported = 0;
839 wol->wolopts = 0;
840 } else {
841 wol->supported = WAKE_MAGIC;
842 if (bp->wol)
843 wol->wolopts = WAKE_MAGIC;
844 else
845 wol->wolopts = 0;
846 }
847 memset(&wol->sopass, 0, sizeof(wol->sopass));
848}
849
850static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
851{
852 struct bnx2x *bp = netdev_priv(dev);
853
51c1a580
MS		 854 if (wol->wolopts & ~WAKE_MAGIC) {
855 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 856 return -EINVAL;
51c1a580 857 }
de0c62db
DK		 858
859 if (wol->wolopts & WAKE_MAGIC) {
51c1a580
MS		 860 if (bp->flags & NO_WOL_FLAG) {
861 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 862 return -EINVAL;
51c1a580 863 }
de0c62db
DK		 864 bp->wol = 1;
865 } else
866 bp->wol = 0;
867
868 return 0;
869}
870
871static u32 bnx2x_get_msglevel(struct net_device *dev)
872{
873 struct bnx2x *bp = netdev_priv(dev);
874
875 return bp->msg_enable;
876}
877
878static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
879{
880 struct bnx2x *bp = netdev_priv(dev);
881
7a25cc73
DK		 882 if (capable(CAP_NET_ADMIN)) {
883 /* dump MCP trace */
ad5afc89 884 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
7a25cc73 885 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 886 bp->msg_enable = level;
7a25cc73 887 }
de0c62db
DK		 888}
889
890static int bnx2x_nway_reset(struct net_device *dev)
891{
892 struct bnx2x *bp = netdev_priv(dev);
893
894 if (!bp->port.pmf)
895 return 0;
896
897 if (netif_running(dev)) {
898 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 899 bnx2x_force_link_reset(bp);
de0c62db
DK		 900 bnx2x_link_set(bp);
901 }
902
903 return 0;
904}
905
906static u32 bnx2x_get_link(struct net_device *dev)
907{
908 struct bnx2x *bp = netdev_priv(dev);
909
f2e0899f 910 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 911 return 0;
912
913 return bp->link_vars.link_up;
914}
915
916static int bnx2x_get_eeprom_len(struct net_device *dev)
917{
918 struct bnx2x *bp = netdev_priv(dev);
919
920 return bp->common.flash_size;
921}
922
f16da43b
AE		 923/* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
924 * we done things the other way around, if two pfs from the same port would
925 * attempt to access nvram at the same time, we could run into a scenario such
926 * as:
927 * pf A takes the port lock.
928 * pf B succeeds in taking the same lock since they are from the same port.
929 * pf A takes the per pf misc lock. Performs eeprom access.
930 * pf A finishes. Unlocks the per pf misc lock.
931 * Pf B takes the lock and proceeds to perform it's own access.
932 * pf A unlocks the per port lock, while pf B is still working (!).
933 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
934 * acess corrupted by pf B).*
935 */
de0c62db
DK		 936static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
937{
938 int port = BP_PORT(bp);
939 int count, i;
f16da43b
AE		 940 u32 val;
941
942 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
943 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 944
945 /* adjust timeout for emulation/FPGA */
754a2f52 946 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 947 if (CHIP_REV_IS_SLOW(bp))
948 count *= 100;
949
950 /* request access to nvram interface */
951 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
952 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
953
954 for (i = 0; i < count*10; i++) {
955 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
956 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
957 break;
958
959 udelay(5);
960 }
961
962 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
51c1a580
MS		 963 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
964 "cannot get access to nvram interface\n");
de0c62db
DK		 965 return -EBUSY;
966 }
967
968 return 0;
969}
970
971static int bnx2x_release_nvram_lock(struct bnx2x *bp)
972{
973 int port = BP_PORT(bp);
974 int count, i;
f16da43b 975 u32 val;
de0c62db
DK		 976
977 /* adjust timeout for emulation/FPGA */
754a2f52 978 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 979 if (CHIP_REV_IS_SLOW(bp))
980 count *= 100;
981
982 /* relinquish nvram interface */
983 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
984 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
985
986 for (i = 0; i < count*10; i++) {
987 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
988 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
989 break;
990
991 udelay(5);
992 }
993
994 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
51c1a580
MS		 995 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
996 "cannot free access to nvram interface\n");
de0c62db
DK		 997 return -EBUSY;
998 }
999
f16da43b
AE		 1000 /* release HW lock: protect against other PFs in PF Direct Assignment */
1001 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1002 return 0;
1003}
1004
1005static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1006{
1007 u32 val;
1008
1009 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1010
1011 /* enable both bits, even on read */
1012 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1013 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1014 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1015}
1016
1017static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1018{
1019 u32 val;
1020
1021 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1022
1023 /* disable both bits, even after read */
1024 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1025 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1026 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1027}
1028
1029static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1030 u32 cmd_flags)
1031{
1032 int count, i, rc;
1033 u32 val;
1034
1035 /* build the command word */
1036 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1037
1038 /* need to clear DONE bit separately */
1039 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1040
1041 /* address of the NVRAM to read from */
1042 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1043 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1044
1045 /* issue a read command */
1046 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1047
1048 /* adjust timeout for emulation/FPGA */
754a2f52 1049 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1050 if (CHIP_REV_IS_SLOW(bp))
1051 count *= 100;
1052
1053 /* wait for completion */
1054 *ret_val = 0;
1055 rc = -EBUSY;
1056 for (i = 0; i < count; i++) {
1057 udelay(5);
1058 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1059
1060 if (val & MCPR_NVM_COMMAND_DONE) {
1061 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1062 /* we read nvram data in cpu order
1063 * but ethtool sees it as an array of bytes
1064 * converting to big-endian will do the work */
1065 *ret_val = cpu_to_be32(val);
1066 rc = 0;
1067 break;
1068 }
1069 }
51c1a580
MS		 1070 if (rc == -EBUSY)
1071 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1072 "nvram read timeout expired\n");
de0c62db
DK		 1073 return rc;
1074}
1075
1076static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1077 int buf_size)
1078{
1079 int rc;
1080 u32 cmd_flags;
1081 __be32 val;
1082
1083 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1084 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1085 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1086 offset, buf_size);
1087 return -EINVAL;
1088 }
1089
1090 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1091 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1092 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1093 offset, buf_size, bp->common.flash_size);
1094 return -EINVAL;
1095 }
1096
1097 /* request access to nvram interface */
1098 rc = bnx2x_acquire_nvram_lock(bp);
1099 if (rc)
1100 return rc;
1101
1102 /* enable access to nvram interface */
1103 bnx2x_enable_nvram_access(bp);
1104
1105 /* read the first word(s) */
1106 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1107 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1108 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1109 memcpy(ret_buf, &val, 4);
1110
1111 /* advance to the next dword */
1112 offset += sizeof(u32);
1113 ret_buf += sizeof(u32);
1114 buf_size -= sizeof(u32);
1115 cmd_flags = 0;
1116 }
1117
1118 if (rc == 0) {
1119 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1120 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1121 memcpy(ret_buf, &val, 4);
1122 }
1123
1124 /* disable access to nvram interface */
1125 bnx2x_disable_nvram_access(bp);
1126 bnx2x_release_nvram_lock(bp);
1127
1128 return rc;
1129}
1130
1131static int bnx2x_get_eeprom(struct net_device *dev,
1132 struct ethtool_eeprom *eeprom, u8 *eebuf)
1133{
1134 struct bnx2x *bp = netdev_priv(dev);
1135 int rc;
1136
51c1a580
MS		 1137 if (!netif_running(dev)) {
1138 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1139 "cannot access eeprom when the interface is down\n");
de0c62db 1140 return -EAGAIN;
51c1a580 1141 }
de0c62db 1142
51c1a580 1143 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1144 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1145 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1146 eeprom->len, eeprom->len);
1147
1148 /* parameters already validated in ethtool_get_eeprom */
1149
1150 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1151
1152 return rc;
1153}
1154
24ea818e
YM		 1155static int bnx2x_get_module_eeprom(struct net_device *dev,
1156 struct ethtool_eeprom *ee,
1157 u8 *data)
1158{
1159 struct bnx2x *bp = netdev_priv(dev);
1160 int rc = 0, phy_idx;
1161 u8 *user_data = data;
1162 int remaining_len = ee->len, xfer_size;
1163 unsigned int page_off = ee->offset;
1164
1165 if (!netif_running(dev)) {
1166 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1167 "cannot access eeprom when the interface is down\n");
1168 return -EAGAIN;
1169 }
1170
1171 phy_idx = bnx2x_get_cur_phy_idx(bp);
1172 bnx2x_acquire_phy_lock(bp);
1173 while (!rc && remaining_len > 0) {
1174 xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ?
1175 SFP_EEPROM_PAGE_SIZE : remaining_len;
1176 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1177 &bp->link_params,
1178 page_off,
1179 xfer_size,
1180 user_data);
1181 remaining_len -= xfer_size;
1182 user_data += xfer_size;
1183 page_off += xfer_size;
1184 }
1185
1186 bnx2x_release_phy_lock(bp);
1187 return rc;
1188}
1189
1190static int bnx2x_get_module_info(struct net_device *dev,
1191 struct ethtool_modinfo *modinfo)
1192{
1193 struct bnx2x *bp = netdev_priv(dev);
1194 int phy_idx;
1195 if (!netif_running(dev)) {
1196 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1197 "cannot access eeprom when the interface is down\n");
1198 return -EAGAIN;
1199 }
1200
1201 phy_idx = bnx2x_get_cur_phy_idx(bp);
1202 switch (bp->link_params.phy[phy_idx].media_type) {
1203 case ETH_PHY_SFPP_10G_FIBER:
1204 case ETH_PHY_SFP_1G_FIBER:
1205 case ETH_PHY_DA_TWINAX:
1206 modinfo->type = ETH_MODULE_SFF_8079;
1207 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1208 return 0;
1209 default:
1210 return -EOPNOTSUPP;
1211 }
1212}
1213
de0c62db
DK		 1214static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1215 u32 cmd_flags)
1216{
1217 int count, i, rc;
1218
1219 /* build the command word */
1220 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1221
1222 /* need to clear DONE bit separately */
1223 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1224
1225 /* write the data */
1226 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1227
1228 /* address of the NVRAM to write to */
1229 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1230 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1231
1232 /* issue the write command */
1233 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1234
1235 /* adjust timeout for emulation/FPGA */
754a2f52 1236 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1237 if (CHIP_REV_IS_SLOW(bp))
1238 count *= 100;
1239
1240 /* wait for completion */
1241 rc = -EBUSY;
1242 for (i = 0; i < count; i++) {
1243 udelay(5);
1244 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1245 if (val & MCPR_NVM_COMMAND_DONE) {
1246 rc = 0;
1247 break;
1248 }
1249 }
1250
51c1a580
MS		 1251 if (rc == -EBUSY)
1252 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1253 "nvram write timeout expired\n");
de0c62db
DK		 1254 return rc;
1255}
1256
1257#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1258
1259static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1260 int buf_size)
1261{
1262 int rc;
1263 u32 cmd_flags;
1264 u32 align_offset;
1265 __be32 val;
1266
1267 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1268 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1269 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1270 offset, buf_size, bp->common.flash_size);
1271 return -EINVAL;
1272 }
1273
1274 /* request access to nvram interface */
1275 rc = bnx2x_acquire_nvram_lock(bp);
1276 if (rc)
1277 return rc;
1278
1279 /* enable access to nvram interface */
1280 bnx2x_enable_nvram_access(bp);
1281
1282 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1283 align_offset = (offset & ~0x03);
1284 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1285
1286 if (rc == 0) {
1287 val &= ~(0xff << BYTE_OFFSET(offset));
1288 val |= (*data_buf << BYTE_OFFSET(offset));
1289
1290 /* nvram data is returned as an array of bytes
1291 * convert it back to cpu order */
1292 val = be32_to_cpu(val);
1293
1294 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1295 cmd_flags);
1296 }
1297
1298 /* disable access to nvram interface */
1299 bnx2x_disable_nvram_access(bp);
1300 bnx2x_release_nvram_lock(bp);
1301
1302 return rc;
1303}
1304
1305static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1306 int buf_size)
1307{
1308 int rc;
1309 u32 cmd_flags;
1310 u32 val;
1311 u32 written_so_far;
1312
1313 if (buf_size == 1) /* ethtool */
1314 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1315
1316 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1317 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1318 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1319 offset, buf_size);
1320 return -EINVAL;
1321 }
1322
1323 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1324 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1325 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1326 offset, buf_size, bp->common.flash_size);
1327 return -EINVAL;
1328 }
1329
1330 /* request access to nvram interface */
1331 rc = bnx2x_acquire_nvram_lock(bp);
1332 if (rc)
1333 return rc;
1334
1335 /* enable access to nvram interface */
1336 bnx2x_enable_nvram_access(bp);
1337
1338 written_so_far = 0;
1339 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1340 while ((written_so_far < buf_size) && (rc == 0)) {
1341 if (written_so_far == (buf_size - sizeof(u32)))
1342 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1343 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1344 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1345 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1346 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1347
1348 memcpy(&val, data_buf, 4);
1349
1350 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1351
1352 /* advance to the next dword */
1353 offset += sizeof(u32);
1354 data_buf += sizeof(u32);
1355 written_so_far += sizeof(u32);
1356 cmd_flags = 0;
1357 }
1358
1359 /* disable access to nvram interface */
1360 bnx2x_disable_nvram_access(bp);
1361 bnx2x_release_nvram_lock(bp);
1362
1363 return rc;
1364}
1365
1366static int bnx2x_set_eeprom(struct net_device *dev,
1367 struct ethtool_eeprom *eeprom, u8 *eebuf)
1368{
1369 struct bnx2x *bp = netdev_priv(dev);
1370 int port = BP_PORT(bp);
1371 int rc = 0;
e10bc84d 1372 u32 ext_phy_config;
51c1a580
MS		 1373 if (!netif_running(dev)) {
1374 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1375 "cannot access eeprom when the interface is down\n");
de0c62db 1376 return -EAGAIN;
51c1a580 1377 }
de0c62db 1378
51c1a580 1379 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1380 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1381 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1382 eeprom->len, eeprom->len);
1383
1384 /* parameters already validated in ethtool_set_eeprom */
1385
1386 /* PHY eeprom can be accessed only by the PMF */
1387 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
51c1a580
MS		 1388 !bp->port.pmf) {
1389 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1390 "wrong magic or interface is not pmf\n");
de0c62db 1391 return -EINVAL;
51c1a580 1392 }
de0c62db 1393
e10bc84d
YR		 1394 ext_phy_config =
1395 SHMEM_RD(bp,
1396 dev_info.port_hw_config[port].external_phy_config);
1397
de0c62db
DK		 1398 if (eeprom->magic == 0x50485950) {
1399 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1400 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1401
1402 bnx2x_acquire_phy_lock(bp);
1403 rc |= bnx2x_link_reset(&bp->link_params,
1404 &bp->link_vars, 0);
e10bc84d 1405 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1406 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1407 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1408 MISC_REGISTERS_GPIO_HIGH, port);
1409 bnx2x_release_phy_lock(bp);
1410 bnx2x_link_report(bp);
1411
1412 } else if (eeprom->magic == 0x50485952) {
1413 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1414 if (bp->state == BNX2X_STATE_OPEN) {
1415 bnx2x_acquire_phy_lock(bp);
1416 rc |= bnx2x_link_reset(&bp->link_params,
1417 &bp->link_vars, 1);
1418
1419 rc |= bnx2x_phy_init(&bp->link_params,
1420 &bp->link_vars);
1421 bnx2x_release_phy_lock(bp);
1422 bnx2x_calc_fc_adv(bp);
1423 }
1424 } else if (eeprom->magic == 0x53985943) {
1425 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1426 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1427 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1428
1429 /* DSP Remove Download Mode */
1430 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1431 MISC_REGISTERS_GPIO_LOW, port);
1432
1433 bnx2x_acquire_phy_lock(bp);
1434
e10bc84d
YR		 1435 bnx2x_sfx7101_sp_sw_reset(bp,
1436 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1437
1438 /* wait 0.5 sec to allow it to run */
1439 msleep(500);
1440 bnx2x_ext_phy_hw_reset(bp, port);
1441 msleep(500);
1442 bnx2x_release_phy_lock(bp);
1443 }
1444 } else
1445 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1446
1447 return rc;
1448}
f85582f8 1449
de0c62db
DK		 1450static int bnx2x_get_coalesce(struct net_device *dev,
1451 struct ethtool_coalesce *coal)
1452{
1453 struct bnx2x *bp = netdev_priv(dev);
1454
1455 memset(coal, 0, sizeof(struct ethtool_coalesce));
1456
1457 coal->rx_coalesce_usecs = bp->rx_ticks;
1458 coal->tx_coalesce_usecs = bp->tx_ticks;
1459
1460 return 0;
1461}
1462
1463static int bnx2x_set_coalesce(struct net_device *dev,
1464 struct ethtool_coalesce *coal)
1465{
1466 struct bnx2x *bp = netdev_priv(dev);
1467
1468 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1469 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1470 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1471
1472 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1473 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1474 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1475
1476 if (netif_running(dev))
1477 bnx2x_update_coalesce(bp);
1478
1479 return 0;
1480}
1481
1482static void bnx2x_get_ringparam(struct net_device *dev,
1483 struct ethtool_ringparam *ering)
1484{
1485 struct bnx2x *bp = netdev_priv(dev);
1486
1487 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1488
25141580
DK		 1489 if (bp->rx_ring_size)
1490 ering->rx_pending = bp->rx_ring_size;
1491 else
c2188952 1492 ering->rx_pending = MAX_RX_AVAIL;
25141580 1493
a3348722 1494 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
de0c62db
DK		 1495 ering->tx_pending = bp->tx_ring_size;
1496}
1497
1498static int bnx2x_set_ringparam(struct net_device *dev,
1499 struct ethtool_ringparam *ering)
1500{
1501 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 1502
1503 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 1504 DP(BNX2X_MSG_ETHTOOL,
1505 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 1506 return -EAGAIN;
1507 }
1508
1509 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1510 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1511 MIN_RX_SIZE_TPA)) ||
a3348722 1512 (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
51c1a580
MS		 1513 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1514 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db 1515 return -EINVAL;
51c1a580 1516 }
de0c62db
DK		 1517
1518 bp->rx_ring_size = ering->rx_pending;
1519 bp->tx_ring_size = ering->tx_pending;
1520
a9fccec7 1521 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1522}
1523
1524static void bnx2x_get_pauseparam(struct net_device *dev,
1525 struct ethtool_pauseparam *epause)
1526{
1527 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1528 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1529 int cfg_reg;
1530
a22f0788
YR		 1531 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1532 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1533
9e7e8399 1534 if (!epause->autoneg)
241fb5d2 1535 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
9e7e8399
MY		 1536 else
1537 cfg_reg = bp->link_params.req_fc_auto_adv;
1538
1539 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1540 BNX2X_FLOW_CTRL_RX);
9e7e8399 1541 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1542 BNX2X_FLOW_CTRL_TX);
1543
51c1a580 1544 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1545 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1546 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1547}
1548
1549static int bnx2x_set_pauseparam(struct net_device *dev,
1550 struct ethtool_pauseparam *epause)
1551{
1552 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1553 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1554 if (IS_MF(bp))
de0c62db
DK		 1555 return 0;
1556
51c1a580 1557 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1558 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1559 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1560
a22f0788 1561 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1562
1563 if (epause->rx_pause)
a22f0788 1564 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1565
1566 if (epause->tx_pause)
a22f0788 1567 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1568
a22f0788
YR		 1569 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1570 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1571
1572 if (epause->autoneg) {
a22f0788 1573 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 1574 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
de0c62db
DK		 1575 return -EINVAL;
1576 }
1577
a22f0788
YR		 1578 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1579 bp->link_params.req_flow_ctrl[cfg_idx] =
1580 BNX2X_FLOW_CTRL_AUTO;
1581 }
5cd75f0c
YR		 1582 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE;
1583 if (epause->rx_pause)
1584 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1585
1586 if (epause->tx_pause)
1587 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
de0c62db
DK		 1588 }
1589
51c1a580 1590 DP(BNX2X_MSG_ETHTOOL,
a22f0788 1591 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1592
1593 if (netif_running(dev)) {
1594 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1595 bnx2x_link_set(bp);
1596 }
1597
1598 return 0;
1599}
1600
5889335c 1601static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
cf2c1df6
MS		 1602 "register_test (offline) ",
1603 "memory_test (offline) ",
1604 "int_loopback_test (offline)",
1605 "ext_loopback_test (offline)",
1606 "nvram_test (online) ",
1607 "interrupt_test (online) ",
1608 "link_test (online) "
de0c62db
DK		 1609};
1610
e9939c80
YM		 1611static u32 bnx2x_eee_to_adv(u32 eee_adv)
1612{
1613 u32 modes = 0;
1614
1615 if (eee_adv & SHMEM_EEE_100M_ADV)
1616 modes |= ADVERTISED_100baseT_Full;
1617 if (eee_adv & SHMEM_EEE_1G_ADV)
1618 modes |= ADVERTISED_1000baseT_Full;
1619 if (eee_adv & SHMEM_EEE_10G_ADV)
1620 modes |= ADVERTISED_10000baseT_Full;
1621
1622 return modes;
1623}
1624
1625static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1626{
1627 u32 eee_adv = 0;
1628 if (modes & ADVERTISED_100baseT_Full)
1629 eee_adv |= SHMEM_EEE_100M_ADV;
1630 if (modes & ADVERTISED_1000baseT_Full)
1631 eee_adv |= SHMEM_EEE_1G_ADV;
1632 if (modes & ADVERTISED_10000baseT_Full)
1633 eee_adv |= SHMEM_EEE_10G_ADV;
1634
1635 return eee_adv << shift;
1636}
1637
1638static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1639{
1640 struct bnx2x *bp = netdev_priv(dev);
1641 u32 eee_cfg;
1642
1643 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1644 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1645 return -EOPNOTSUPP;
1646 }
1647
08e9acc2 1648 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 1649
1650 edata->supported =
1651 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1652 SHMEM_EEE_SUPPORTED_SHIFT);
1653
1654 edata->advertised =
1655 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1656 SHMEM_EEE_ADV_STATUS_SHIFT);
1657 edata->lp_advertised =
1658 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1659 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1660
1661 /* SHMEM value is in 16u units --> Convert to 1u units. */
1662 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1663
1664 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
1665 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
1666 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1667
1668 return 0;
1669}
1670
1671static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1672{
1673 struct bnx2x *bp = netdev_priv(dev);
1674 u32 eee_cfg;
1675 u32 advertised;
1676
1677 if (IS_MF(bp))
1678 return 0;
1679
1680 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1681 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1682 return -EOPNOTSUPP;
1683 }
1684
08e9acc2 1685 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 1686
1687 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1688 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1689 return -EOPNOTSUPP;
1690 }
1691
1692 advertised = bnx2x_adv_to_eee(edata->advertised,
1693 SHMEM_EEE_ADV_STATUS_SHIFT);
1694 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1695 DP(BNX2X_MSG_ETHTOOL,
efc7ce03 1696 "Direct manipulation of EEE advertisement is not supported\n");
e9939c80
YM		 1697 return -EINVAL;
1698 }
1699
1700 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1701 DP(BNX2X_MSG_ETHTOOL,
1702 "Maximal Tx Lpi timer supported is %x(u)\n",
1703 EEE_MODE_TIMER_MASK);
1704 return -EINVAL;
1705 }
1706 if (edata->tx_lpi_enabled &&
1707 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1708 DP(BNX2X_MSG_ETHTOOL,
1709 "Minimal Tx Lpi timer supported is %d(u)\n",
1710 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1711 return -EINVAL;
1712 }
1713
1714 /* All is well; Apply changes*/
1715 if (edata->eee_enabled)
1716 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1717 else
1718 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1719
1720 if (edata->tx_lpi_enabled)
1721 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1722 else
1723 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1724
1725 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1726 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1727 EEE_MODE_TIMER_MASK) |
1728 EEE_MODE_OVERRIDE_NVRAM |
1729 EEE_MODE_OUTPUT_TIME;
1730
1731 /* Restart link to propogate changes */
1732 if (netif_running(dev)) {
1733 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 1734 bnx2x_force_link_reset(bp);
e9939c80
YM		 1735 bnx2x_link_set(bp);
1736 }
1737
1738 return 0;
1739}
1740
1741
619c5cb6
VZ		 1742enum {
1743 BNX2X_CHIP_E1_OFST = 0,
1744 BNX2X_CHIP_E1H_OFST,
1745 BNX2X_CHIP_E2_OFST,
1746 BNX2X_CHIP_E3_OFST,
1747 BNX2X_CHIP_E3B0_OFST,
1748 BNX2X_CHIP_MAX_OFST
1749};
1750
1751#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1752#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1753#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1754#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1755#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1756
1757#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1758#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1759
de0c62db
DK		 1760static int bnx2x_test_registers(struct bnx2x *bp)
1761{
1762 int idx, i, rc = -ENODEV;
619c5cb6 1763 u32 wr_val = 0, hw;
de0c62db
DK		 1764 int port = BP_PORT(bp);
1765 static const struct {
619c5cb6 1766 u32 hw;
de0c62db
DK		 1767 u32 offset0;
1768 u32 offset1;
1769 u32 mask;
1770 } reg_tbl[] = {
619c5cb6
VZ		 1771/* 0 */ { BNX2X_CHIP_MASK_ALL,
1772 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1773 { BNX2X_CHIP_MASK_ALL,
1774 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1775 { BNX2X_CHIP_MASK_E1X,
1776 HC_REG_AGG_INT_0, 4, 0x000003ff },
1777 { BNX2X_CHIP_MASK_ALL,
1778 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1779 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1780 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1781 { BNX2X_CHIP_MASK_E3B0,
1782 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1783 { BNX2X_CHIP_MASK_ALL,
1784 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1785 { BNX2X_CHIP_MASK_ALL,
1786 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1787 { BNX2X_CHIP_MASK_ALL,
1788 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1789 { BNX2X_CHIP_MASK_ALL,
1790 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1791/* 10 */ { BNX2X_CHIP_MASK_ALL,
1792 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1793 { BNX2X_CHIP_MASK_ALL,
1794 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1795 { BNX2X_CHIP_MASK_ALL,
1796 QM_REG_CONNNUM_0, 4, 0x000fffff },
1797 { BNX2X_CHIP_MASK_ALL,
1798 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1799 { BNX2X_CHIP_MASK_ALL,
1800 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1801 { BNX2X_CHIP_MASK_ALL,
1802 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1803 { BNX2X_CHIP_MASK_ALL,
1804 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1805 { BNX2X_CHIP_MASK_ALL,
1806 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1807 { BNX2X_CHIP_MASK_ALL,
1808 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1809 { BNX2X_CHIP_MASK_ALL,
1810 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1811/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1812 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1813 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1814 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1815 { BNX2X_CHIP_MASK_ALL,
1816 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1817 { BNX2X_CHIP_MASK_ALL,
1818 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1819 { BNX2X_CHIP_MASK_ALL,
1820 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1821 { BNX2X_CHIP_MASK_ALL,
1822 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1823 { BNX2X_CHIP_MASK_ALL,
1824 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1825 { BNX2X_CHIP_MASK_ALL,
1826 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1827 { BNX2X_CHIP_MASK_ALL,
1828 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1829 { BNX2X_CHIP_MASK_ALL,
1830 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1831/* 30 */ { BNX2X_CHIP_MASK_ALL,
1832 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1833 { BNX2X_CHIP_MASK_ALL,
1834 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1835 { BNX2X_CHIP_MASK_ALL,
1836 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1837 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1838 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1839 { BNX2X_CHIP_MASK_ALL,
1840 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1841 { BNX2X_CHIP_MASK_ALL,
1842 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1843 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1844 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1845 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1846 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1847
1848 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 1849 };
1850
51c1a580
MS		 1851 if (!netif_running(bp->dev)) {
1852 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1853 "cannot access eeprom when the interface is down\n");
de0c62db 1854 return rc;
51c1a580 1855 }
de0c62db 1856
619c5cb6
VZ		 1857 if (CHIP_IS_E1(bp))
1858 hw = BNX2X_CHIP_MASK_E1;
1859 else if (CHIP_IS_E1H(bp))
1860 hw = BNX2X_CHIP_MASK_E1H;
1861 else if (CHIP_IS_E2(bp))
1862 hw = BNX2X_CHIP_MASK_E2;
1863 else if (CHIP_IS_E3B0(bp))
1864 hw = BNX2X_CHIP_MASK_E3B0;
1865 else /* e3 A0 */
1866 hw = BNX2X_CHIP_MASK_E3;
1867
de0c62db
DK		 1868 /* Repeat the test twice:
1869 First by writing 0x00000000, second by writing 0xffffffff */
1870 for (idx = 0; idx < 2; idx++) {
1871
1872 switch (idx) {
1873 case 0:
1874 wr_val = 0;
1875 break;
1876 case 1:
1877 wr_val = 0xffffffff;
1878 break;
1879 }
1880
1881 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1882 u32 offset, mask, save_val, val;
619c5cb6 1883 if (!(hw & reg_tbl[i].hw))
f2e0899f 1884 continue;
de0c62db
DK		 1885
1886 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1887 mask = reg_tbl[i].mask;
1888
1889 save_val = REG_RD(bp, offset);
1890
ec6ba945 1891 REG_WR(bp, offset, wr_val & mask);
f85582f8 1892
de0c62db
DK		 1893 val = REG_RD(bp, offset);
1894
1895 /* Restore the original register's value */
1896 REG_WR(bp, offset, save_val);
1897
1898 /* verify value is as expected */
1899 if ((val & mask) != (wr_val & mask)) {
51c1a580 1900 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1901 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1902 offset, val, wr_val, mask);
1903 goto test_reg_exit;
1904 }
1905 }
1906 }
1907
1908 rc = 0;
1909
1910test_reg_exit:
1911 return rc;
1912}
1913
1914static int bnx2x_test_memory(struct bnx2x *bp)
1915{
1916 int i, j, rc = -ENODEV;
619c5cb6 1917 u32 val, index;
de0c62db
DK		 1918 static const struct {
1919 u32 offset;
1920 int size;
1921 } mem_tbl[] = {
1922 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1923 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1924 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1925 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1926 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1927 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1928 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1929
1930 { 0xffffffff, 0 }
1931 };
619c5cb6 1932
de0c62db
DK		 1933 static const struct {
1934 char *name;
1935 u32 offset;
619c5cb6 1936 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 1937 } prty_tbl[] = {
619c5cb6
VZ		 1938 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1939 {0x3ffc0, 0, 0, 0} },
1940 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1941 {0x2, 0x2, 0, 0} },
1942 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1943 {0, 0, 0, 0} },
1944 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1945 {0x3ffc0, 0, 0, 0} },
1946 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1947 {0x3ffc0, 0, 0, 0} },
1948 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1949 {0x3ffc1, 0, 0, 0} },
1950
1951 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 1952 };
1953
51c1a580
MS		 1954 if (!netif_running(bp->dev)) {
1955 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1956 "cannot access eeprom when the interface is down\n");
de0c62db 1957 return rc;
51c1a580 1958 }
de0c62db 1959
619c5cb6
VZ		 1960 if (CHIP_IS_E1(bp))
1961 index = BNX2X_CHIP_E1_OFST;
1962 else if (CHIP_IS_E1H(bp))
1963 index = BNX2X_CHIP_E1H_OFST;
1964 else if (CHIP_IS_E2(bp))
1965 index = BNX2X_CHIP_E2_OFST;
1966 else /* e3 */
1967 index = BNX2X_CHIP_E3_OFST;
1968
f2e0899f
DK		 1969 /* pre-Check the parity status */
1970 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1971 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1972 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1973 DP(BNX2X_MSG_ETHTOOL,
f2e0899f
DK		 1974 "%s is 0x%x\n", prty_tbl[i].name, val);
1975 goto test_mem_exit;
1976 }
1977 }
1978
de0c62db
DK		 1979 /* Go through all the memories */
1980 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1981 for (j = 0; j < mem_tbl[i].size; j++)
1982 REG_RD(bp, mem_tbl[i].offset + j*4);
1983
1984 /* Check the parity status */
1985 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1986 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1987 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1988 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1989 "%s is 0x%x\n", prty_tbl[i].name, val);
1990 goto test_mem_exit;
1991 }
1992 }
1993
1994 rc = 0;
1995
1996test_mem_exit:
1997 return rc;
1998}
1999
a22f0788 2000static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 2001{
f2e0899f 2002 int cnt = 1400;
de0c62db 2003
619c5cb6 2004 if (link_up) {
a22f0788 2005 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 2006 msleep(20);
2007
2008 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
51c1a580 2009 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
8970b2e4
MS		 2010
2011 cnt = 1400;
2012 while (!bp->link_vars.link_up && cnt--)
2013 msleep(20);
2014
2015 if (cnt <= 0 && !bp->link_vars.link_up)
2016 DP(BNX2X_MSG_ETHTOOL,
2017 "Timeout waiting for link init\n");
619c5cb6 2018 }
de0c62db
DK		 2019}
2020
619c5cb6 2021static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 2022{
2023 unsigned int pkt_size, num_pkts, i;
2024 struct sk_buff *skb;
2025 unsigned char *packet;
2026 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2027 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
65565884 2028 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
de0c62db
DK		 2029 u16 tx_start_idx, tx_idx;
2030 u16 rx_start_idx, rx_idx;
b0700b1e 2031 u16 pkt_prod, bd_prod;
de0c62db
DK		 2032 struct sw_tx_bd *tx_buf;
2033 struct eth_tx_start_bd *tx_start_bd;
de0c62db
DK		 2034 dma_addr_t mapping;
2035 union eth_rx_cqe *cqe;
619c5cb6 2036 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 2037 struct sw_rx_bd *rx_buf;
2038 u16 len;
2039 int rc = -ENODEV;
e52fcb24 2040 u8 *data;
8970b2e4
MS		 2041 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2042 txdata->txq_index);
de0c62db
DK		 2043
2044 /* check the loopback mode */
2045 switch (loopback_mode) {
2046 case BNX2X_PHY_LOOPBACK:
8970b2e4
MS		 2047 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2048 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
de0c62db 2049 return -EINVAL;
8970b2e4 2050 }
de0c62db
DK		 2051 break;
2052 case BNX2X_MAC_LOOPBACK:
32911333
YR		 2053 if (CHIP_IS_E3(bp)) {
2054 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2055 if (bp->port.supported[cfg_idx] &
2056 (SUPPORTED_10000baseT_Full |
2057 SUPPORTED_20000baseMLD2_Full |
2058 SUPPORTED_20000baseKR2_Full))
2059 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2060 else
2061 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2062 } else
2063 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2064
de0c62db
DK		 2065 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2066 break;
8970b2e4
MS		 2067 case BNX2X_EXT_LOOPBACK:
2068 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2069 DP(BNX2X_MSG_ETHTOOL,
2070 "Can't configure external loopback\n");
2071 return -EINVAL;
2072 }
2073 break;
de0c62db 2074 default:
51c1a580 2075 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db
DK		 2076 return -EINVAL;
2077 }
2078
2079 /* prepare the loopback packet */
2080 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2081 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 2082 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db 2083 if (!skb) {
51c1a580 2084 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
de0c62db
DK		 2085 rc = -ENOMEM;
2086 goto test_loopback_exit;
2087 }
2088 packet = skb_put(skb, pkt_size);
2089 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2090 memset(packet + ETH_ALEN, 0, ETH_ALEN);
2091 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2092 for (i = ETH_HLEN; i < pkt_size; i++)
2093 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 2094 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2095 skb_headlen(skb), DMA_TO_DEVICE);
2096 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2097 rc = -ENOMEM;
2098 dev_kfree_skb(skb);
51c1a580 2099 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
619c5cb6
VZ		 2100 goto test_loopback_exit;
2101 }
de0c62db
DK		 2102
2103 /* send the loopback packet */
2104 num_pkts = 0;
6383c0b3 2105 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2106 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2107
73dbb5e1
DK		 2108 netdev_tx_sent_queue(txq, skb->len);
2109
6383c0b3
AE		 2110 pkt_prod = txdata->tx_pkt_prod++;
2111 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2112 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 2113 tx_buf->skb = skb;
2114 tx_buf->flags = 0;
2115
6383c0b3
AE		 2116 bd_prod = TX_BD(txdata->tx_bd_prod);
2117 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 2118 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2119 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2120 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2121 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 2122 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 2123 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 2124 SET_FLAG(tx_start_bd->general_data,
2125 ETH_TX_START_BD_HDR_NBDS,
2126 1);
96bed4b9
YM		 2127 SET_FLAG(tx_start_bd->general_data,
2128 ETH_TX_START_BD_PARSE_NBDS,
2129 0);
de0c62db
DK		 2130
2131 /* turn on parsing and get a BD */
2132 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 2133
96bed4b9
YM		 2134 if (CHIP_IS_E1x(bp)) {
2135 u16 global_data = 0;
2136 struct eth_tx_parse_bd_e1x *pbd_e1x =
2137 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2138 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2139 SET_FLAG(global_data,
2140 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2141 pbd_e1x->global_data = cpu_to_le16(global_data);
2142 } else {
2143 u32 parsing_data = 0;
2144 struct eth_tx_parse_bd_e2 *pbd_e2 =
2145 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2146 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2147 SET_FLAG(parsing_data,
2148 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2149 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2150 }
de0c62db
DK		 2151 wmb();
2152
6383c0b3 2153 txdata->tx_db.data.prod += 2;
de0c62db 2154 barrier();
6383c0b3 2155 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 2156
2157 mmiowb();
619c5cb6 2158 barrier();
de0c62db
DK		 2159
2160 num_pkts++;
6383c0b3 2161 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 2162
2163 udelay(100);
2164
6383c0b3 2165 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2166 if (tx_idx != tx_start_idx + num_pkts)
2167 goto test_loopback_exit;
2168
f2e0899f
DK		 2169 /* Unlike HC IGU won't generate an interrupt for status block
2170 * updates that have been performed while interrupts were
2171 * disabled.
2172 */
e1210d12
ED		 2173 if (bp->common.int_block == INT_BLOCK_IGU) {
2174 /* Disable local BHes to prevent a dead-lock situation between
2175 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2176 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2177 */
2178 local_bh_disable();
6383c0b3 2179 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 2180 local_bh_enable();
2181 }
f2e0899f 2182
de0c62db
DK		 2183 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2184 if (rx_idx != rx_start_idx + num_pkts)
2185 goto test_loopback_exit;
2186
b0700b1e 2187 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 2188 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 2189 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2190 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 2191 goto test_loopback_rx_exit;
2192
621b4d66 2193 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
de0c62db
DK		 2194 if (len != pkt_size)
2195 goto test_loopback_rx_exit;
2196
2197 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 2198 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 2199 dma_unmap_addr(rx_buf, mapping),
2200 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 2201 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 2202 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 2203 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 2204 goto test_loopback_rx_exit;
2205
2206 rc = 0;
2207
2208test_loopback_rx_exit:
2209
2210 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2211 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2212 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2213 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2214
2215 /* Update producers */
2216 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2217 fp_rx->rx_sge_prod);
2218
2219test_loopback_exit:
2220 bp->link_params.loopback_mode = LOOPBACK_NONE;
2221
2222 return rc;
2223}
2224
619c5cb6 2225static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 2226{
2227 int rc = 0, res;
2228
2229 if (BP_NOMCP(bp))
2230 return rc;
2231
2232 if (!netif_running(bp->dev))
2233 return BNX2X_LOOPBACK_FAILED;
2234
2235 bnx2x_netif_stop(bp, 1);
2236 bnx2x_acquire_phy_lock(bp);
2237
619c5cb6 2238 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db 2239 if (res) {
51c1a580 2240 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
de0c62db
DK		 2241 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2242 }
2243
619c5cb6 2244 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db 2245 if (res) {
51c1a580 2246 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
de0c62db
DK		 2247 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2248 }
2249
2250 bnx2x_release_phy_lock(bp);
2251 bnx2x_netif_start(bp);
2252
2253 return rc;
2254}
2255
8970b2e4
MS		 2256static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2257{
2258 int rc;
2259 u8 is_serdes =
2260 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2261
2262 if (BP_NOMCP(bp))
2263 return -ENODEV;
2264
2265 if (!netif_running(bp->dev))
2266 return BNX2X_EXT_LOOPBACK_FAILED;
2267
5d07d868 2268 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
8970b2e4
MS		 2269 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2270 if (rc) {
2271 DP(BNX2X_MSG_ETHTOOL,
2272 "Can't perform self-test, nic_load (for external lb) failed\n");
2273 return -ENODEV;
2274 }
2275 bnx2x_wait_for_link(bp, 1, is_serdes);
2276
2277 bnx2x_netif_stop(bp, 1);
2278
2279 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2280 if (rc)
2281 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2282
2283 bnx2x_netif_start(bp);
2284
2285 return rc;
2286}
2287
de0c62db
DK		 2288#define CRC32_RESIDUAL 0xdebb20e3
2289
2290static int bnx2x_test_nvram(struct bnx2x *bp)
2291{
2292 static const struct {
2293 int offset;
2294 int size;
2295 } nvram_tbl[] = {
2296 { 0, 0x14 }, /* bootstrap */
2297 { 0x14, 0xec }, /* dir */
2298 { 0x100, 0x350 }, /* manuf_info */
2299 { 0x450, 0xf0 }, /* feature_info */
2300 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2301 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2302 { 0, 0 }
2303 };
afa13b4b
MY		 2304 __be32 *buf;
2305 u8 *data;
de0c62db
DK		 2306 int i, rc;
2307 u32 magic, crc;
2308
2309 if (BP_NOMCP(bp))
2310 return 0;
2311
afa13b4b
MY		 2312 buf = kmalloc(0x350, GFP_KERNEL);
2313 if (!buf) {
51c1a580 2314 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
afa13b4b
MY		 2315 rc = -ENOMEM;
2316 goto test_nvram_exit;
2317 }
2318 data = (u8 *)buf;
2319
de0c62db
DK		 2320 rc = bnx2x_nvram_read(bp, 0, data, 4);
2321 if (rc) {
51c1a580
MS		 2322 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2323 "magic value read (rc %d)\n", rc);
de0c62db
DK		 2324 goto test_nvram_exit;
2325 }
2326
2327 magic = be32_to_cpu(buf[0]);
2328 if (magic != 0x669955aa) {
51c1a580
MS		 2329 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2330 "wrong magic value (0x%08x)\n", magic);
de0c62db
DK		 2331 rc = -ENODEV;
2332 goto test_nvram_exit;
2333 }
2334
2335 for (i = 0; nvram_tbl[i].size; i++) {
2336
2337 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2338 nvram_tbl[i].size);
2339 if (rc) {
51c1a580 2340 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 2341 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2342 goto test_nvram_exit;
2343 }
2344
2345 crc = ether_crc_le(nvram_tbl[i].size, data);
2346 if (crc != CRC32_RESIDUAL) {
51c1a580
MS		 2347 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2348 "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
de0c62db
DK		 2349 rc = -ENODEV;
2350 goto test_nvram_exit;
2351 }
2352 }
2353
2354test_nvram_exit:
afa13b4b 2355 kfree(buf);
de0c62db
DK		 2356 return rc;
2357}
2358
619c5cb6 2359/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2360static int bnx2x_test_intr(struct bnx2x *bp)
2361{
3b603066 2362 struct bnx2x_queue_state_params params = {NULL};
de0c62db 2363
51c1a580
MS		 2364 if (!netif_running(bp->dev)) {
2365 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2366 "cannot access eeprom when the interface is down\n");
de0c62db 2367 return -ENODEV;
51c1a580 2368 }
de0c62db 2369
15192a8c 2370 params.q_obj = &bp->sp_objs->q_obj;
619c5cb6 2371 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2372
619c5cb6
VZ		 2373 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2374
2375 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2376}
2377
2378static void bnx2x_self_test(struct net_device *dev,
2379 struct ethtool_test *etest, u64 *buf)
2380{
2381 struct bnx2x *bp = netdev_priv(dev);
a336ca7c
YR		 2382 u8 is_serdes, link_up;
2383 int rc, cnt = 0;
cf2c1df6 2384
de0c62db 2385 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 2386 netdev_err(bp->dev,
2387 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 2388 etest->flags |= ETH_TEST_FL_FAILED;
2389 return;
2390 }
8970b2e4
MS		 2391 DP(BNX2X_MSG_ETHTOOL,
2392 "Self-test command parameters: offline = %d, external_lb = %d\n",
2393 (etest->flags & ETH_TEST_FL_OFFLINE),
2394 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
de0c62db 2395
cf2c1df6 2396 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
de0c62db 2397
cf2c1df6
MS		 2398 if (!netif_running(dev)) {
2399 DP(BNX2X_MSG_ETHTOOL,
2400 "Can't perform self-test when interface is down\n");
de0c62db 2401 return;
cf2c1df6 2402 }
de0c62db 2403
a22f0788 2404 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
a336ca7c 2405 link_up = bp->link_vars.link_up;
cf2c1df6
MS		 2406 /* offline tests are not supported in MF mode */
2407 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
de0c62db
DK		 2408 int port = BP_PORT(bp);
2409 u32 val;
de0c62db
DK		 2410
2411 /* save current value of input enable for TX port IF */
2412 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2413 /* disable input for TX port IF */
2414 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2415
5d07d868 2416 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
cf2c1df6
MS		 2417 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2418 if (rc) {
2419 etest->flags |= ETH_TEST_FL_FAILED;
2420 DP(BNX2X_MSG_ETHTOOL,
2421 "Can't perform self-test, nic_load (for offline) failed\n");
2422 return;
2423 }
2424
de0c62db 2425 /* wait until link state is restored */
619c5cb6 2426 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2427
2428 if (bnx2x_test_registers(bp) != 0) {
2429 buf[0] = 1;
2430 etest->flags |= ETH_TEST_FL_FAILED;
2431 }
2432 if (bnx2x_test_memory(bp) != 0) {
2433 buf[1] = 1;
2434 etest->flags |= ETH_TEST_FL_FAILED;
2435 }
f85582f8 2436
8970b2e4 2437 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
de0c62db
DK		 2438 if (buf[2] != 0)
2439 etest->flags |= ETH_TEST_FL_FAILED;
2440
8970b2e4
MS		 2441 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2442 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2443 if (buf[3] != 0)
2444 etest->flags |= ETH_TEST_FL_FAILED;
2445 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2446 }
2447
5d07d868 2448 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
de0c62db
DK		 2449
2450 /* restore input for TX port IF */
2451 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
cf2c1df6
MS		 2452 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2453 if (rc) {
2454 etest->flags |= ETH_TEST_FL_FAILED;
2455 DP(BNX2X_MSG_ETHTOOL,
2456 "Can't perform self-test, nic_load (for online) failed\n");
2457 return;
2458 }
de0c62db 2459 /* wait until link state is restored */
a22f0788 2460 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2461 }
2462 if (bnx2x_test_nvram(bp) != 0) {
cf2c1df6
MS		 2463 if (!IS_MF(bp))
2464 buf[4] = 1;
2465 else
2466 buf[0] = 1;
de0c62db
DK		 2467 etest->flags |= ETH_TEST_FL_FAILED;
2468 }
2469 if (bnx2x_test_intr(bp) != 0) {
cf2c1df6
MS		 2470 if (!IS_MF(bp))
2471 buf[5] = 1;
2472 else
2473 buf[1] = 1;
de0c62db
DK		 2474 etest->flags |= ETH_TEST_FL_FAILED;
2475 }
633ac363 2476
a336ca7c
YR		 2477 if (link_up) {
2478 cnt = 100;
2479 while (bnx2x_link_test(bp, is_serdes) && --cnt)
2480 msleep(20);
2481 }
2482
2483 if (!cnt) {
cf2c1df6
MS		 2484 if (!IS_MF(bp))
2485 buf[6] = 1;
2486 else
2487 buf[2] = 1;
633ac363
DK		 2488 etest->flags |= ETH_TEST_FL_FAILED;
2489 }
de0c62db
DK		 2490
2491#ifdef BNX2X_EXTRA_DEBUG
2492 bnx2x_panic_dump(bp);
2493#endif
2494}
2495
de0c62db
DK		 2496#define IS_PORT_STAT(i) \
2497 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2498#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2499#define IS_MF_MODE_STAT(bp) \
2500 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2501
619c5cb6
VZ		 2502/* ethtool statistics are displayed for all regular ethernet queues and the
2503 * fcoe L2 queue if not disabled
2504 */
1191cb83 2505static int bnx2x_num_stat_queues(struct bnx2x *bp)
619c5cb6
VZ		 2506{
2507 return BNX2X_NUM_ETH_QUEUES(bp);
2508}
2509
de0c62db
DK		 2510static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2511{
2512 struct bnx2x *bp = netdev_priv(dev);
2513 int i, num_stats;
2514
2515 switch (stringset) {
2516 case ETH_SS_STATS:
2517 if (is_multi(bp)) {
619c5cb6 2518 num_stats = bnx2x_num_stat_queues(bp) *
d5e83632
YM		 2519 BNX2X_NUM_Q_STATS;
2520 } else
2521 num_stats = 0;
2522 if (IS_MF_MODE_STAT(bp)) {
2523 for (i = 0; i < BNX2X_NUM_STATS; i++)
2524 if (IS_FUNC_STAT(i))
2525 num_stats++;
2526 } else
2527 num_stats += BNX2X_NUM_STATS;
2528
de0c62db
DK		 2529 return num_stats;
2530
2531 case ETH_SS_TEST:
cf2c1df6 2532 return BNX2X_NUM_TESTS(bp);
de0c62db
DK		 2533
2534 default:
2535 return -EINVAL;
2536 }
2537}
2538
2539static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2540{
2541 struct bnx2x *bp = netdev_priv(dev);
5889335c 2542 int i, j, k, start;
ec6ba945 2543 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2544
2545 switch (stringset) {
2546 case ETH_SS_STATS:
d5e83632 2547 k = 0;
de0c62db 2548 if (is_multi(bp)) {
619c5cb6 2549 for_each_eth_queue(bp, i) {
ec6ba945 2550 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2551 sprintf(queue_name, "%d", i);
de0c62db 2552 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2553 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2554 ETH_GSTRING_LEN,
2555 bnx2x_q_stats_arr[j].string,
2556 queue_name);
de0c62db
DK		 2557 k += BNX2X_NUM_Q_STATS;
2558 }
de0c62db 2559 }
d5e83632
YM		 2560
2561
2562 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2563 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2564 continue;
2565 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2566 bnx2x_stats_arr[i].string);
2567 j++;
2568 }
2569
de0c62db
DK		 2570 break;
2571
2572 case ETH_SS_TEST:
cf2c1df6
MS		 2573 /* First 4 tests cannot be done in MF mode */
2574 if (!IS_MF(bp))
2575 start = 0;
2576 else
2577 start = 4;
5889335c
MS		 2578 memcpy(buf, bnx2x_tests_str_arr + start,
2579 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
de0c62db
DK		 2580 }
2581}
2582
2583static void bnx2x_get_ethtool_stats(struct net_device *dev,
2584 struct ethtool_stats *stats, u64 *buf)
2585{
2586 struct bnx2x *bp = netdev_priv(dev);
2587 u32 *hw_stats, *offset;
d5e83632 2588 int i, j, k = 0;
de0c62db
DK		 2589
2590 if (is_multi(bp)) {
619c5cb6 2591 for_each_eth_queue(bp, i) {
15192a8c 2592 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
de0c62db
DK		 2593 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2594 if (bnx2x_q_stats_arr[j].size == 0) {
2595 /* skip this counter */
2596 buf[k + j] = 0;
2597 continue;
2598 }
2599 offset = (hw_stats +
2600 bnx2x_q_stats_arr[j].offset);
2601 if (bnx2x_q_stats_arr[j].size == 4) {
2602 /* 4-byte counter */
2603 buf[k + j] = (u64) *offset;
2604 continue;
2605 }
2606 /* 8-byte counter */
2607 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2608 }
2609 k += BNX2X_NUM_Q_STATS;
2610 }
d5e83632
YM		 2611 }
2612
2613 hw_stats = (u32 *)&bp->eth_stats;
2614 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2615 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2616 continue;
2617 if (bnx2x_stats_arr[i].size == 0) {
2618 /* skip this counter */
2619 buf[k + j] = 0;
2620 j++;
2621 continue;
de0c62db 2622 }
d5e83632
YM		 2623 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2624 if (bnx2x_stats_arr[i].size == 4) {
2625 /* 4-byte counter */
2626 buf[k + j] = (u64) *offset;
de0c62db 2627 j++;
d5e83632 2628 continue;
de0c62db 2629 }
d5e83632
YM		 2630 /* 8-byte counter */
2631 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2632 j++;
de0c62db
DK		 2633 }
2634}
2635
32d36134 2636static int bnx2x_set_phys_id(struct net_device *dev,
2637 enum ethtool_phys_id_state state)
de0c62db
DK		 2638{
2639 struct bnx2x *bp = netdev_priv(dev);
de0c62db 2640
51c1a580
MS		 2641 if (!netif_running(dev)) {
2642 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2643 "cannot access eeprom when the interface is down\n");
32d36134 2644 return -EAGAIN;
51c1a580 2645 }
de0c62db 2646
51c1a580
MS		 2647 if (!bp->port.pmf) {
2648 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
32d36134 2649 return -EOPNOTSUPP;
51c1a580 2650 }
de0c62db 2651
32d36134 2652 switch (state) {
2653 case ETHTOOL_ID_ACTIVE:
fce55922 2654 return 1; /* cycle on/off once per second */
de0c62db 2655
32d36134 2656 case ETHTOOL_ID_ON:
8203c4b6 2657 bnx2x_acquire_phy_lock(bp);
32d36134 2658 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2659 LED_MODE_ON, SPEED_1000);
8203c4b6 2660 bnx2x_release_phy_lock(bp);
32d36134 2661 break;
de0c62db 2662
32d36134 2663 case ETHTOOL_ID_OFF:
8203c4b6 2664 bnx2x_acquire_phy_lock(bp);
32d36134 2665 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2666 LED_MODE_FRONT_PANEL_OFF, 0);
8203c4b6 2667 bnx2x_release_phy_lock(bp);
32d36134 2668 break;
2669
2670 case ETHTOOL_ID_INACTIVE:
8203c4b6 2671 bnx2x_acquire_phy_lock(bp);
e1943424
DM		 2672 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2673 LED_MODE_OPER,
2674 bp->link_vars.line_speed);
8203c4b6 2675 bnx2x_release_phy_lock(bp);
32d36134 2676 }
de0c62db
DK		 2677
2678 return 0;
2679}
2680
5d317c6a
MS		 2681static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2682{
2683
2684 switch (info->flow_type) {
2685 case TCP_V4_FLOW:
2686 case TCP_V6_FLOW:
2687 info->data = RXH_IP_SRC | RXH_IP_DST |
2688 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2689 break;
2690 case UDP_V4_FLOW:
2691 if (bp->rss_conf_obj.udp_rss_v4)
2692 info->data = RXH_IP_SRC | RXH_IP_DST |
2693 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2694 else
2695 info->data = RXH_IP_SRC | RXH_IP_DST;
2696 break;
2697 case UDP_V6_FLOW:
2698 if (bp->rss_conf_obj.udp_rss_v6)
2699 info->data = RXH_IP_SRC | RXH_IP_DST |
2700 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2701 else
2702 info->data = RXH_IP_SRC | RXH_IP_DST;
2703 break;
2704 case IPV4_FLOW:
2705 case IPV6_FLOW:
2706 info->data = RXH_IP_SRC | RXH_IP_DST;
2707 break;
2708 default:
2709 info->data = 0;
2710 break;
2711 }
2712
2713 return 0;
2714}
2715
ab532cf3 2716static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2717 u32 *rules __always_unused)
ab532cf3
TH		 2718{
2719 struct bnx2x *bp = netdev_priv(dev);
2720
2721 switch (info->cmd) {
2722 case ETHTOOL_GRXRINGS:
2723 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2724 return 0;
5d317c6a
MS		 2725 case ETHTOOL_GRXFH:
2726 return bnx2x_get_rss_flags(bp, info);
2727 default:
2728 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2729 return -EOPNOTSUPP;
2730 }
2731}
2732
2733static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2734{
2735 int udp_rss_requested;
2736
2737 DP(BNX2X_MSG_ETHTOOL,
2738 "Set rss flags command parameters: flow type = %d, data = %llu\n",
2739 info->flow_type, info->data);
2740
2741 switch (info->flow_type) {
2742 case TCP_V4_FLOW:
2743 case TCP_V6_FLOW:
2744 /* For TCP only 4-tupple hash is supported */
2745 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
2746 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2747 DP(BNX2X_MSG_ETHTOOL,
2748 "Command parameters not supported\n");
2749 return -EINVAL;
2750 } else {
2751 return 0;
2752 }
2753
2754 case UDP_V4_FLOW:
2755 case UDP_V6_FLOW:
2756 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
2757 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2758 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2759 udp_rss_requested = 1;
2760 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
2761 udp_rss_requested = 0;
2762 else
2763 return -EINVAL;
2764 if ((info->flow_type == UDP_V4_FLOW) &&
2765 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
2766 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
2767 DP(BNX2X_MSG_ETHTOOL,
2768 "rss re-configured, UDP 4-tupple %s\n",
2769 udp_rss_requested ? "enabled" : "disabled");
2770 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2771 } else if ((info->flow_type == UDP_V6_FLOW) &&
2772 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
2773 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
5d317c6a
MS		 2774 DP(BNX2X_MSG_ETHTOOL,
2775 "rss re-configured, UDP 4-tupple %s\n",
2776 udp_rss_requested ? "enabled" : "disabled");
337da3e3 2777 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
5d317c6a
MS		 2778 } else {
2779 return 0;
2780 }
2781 case IPV4_FLOW:
2782 case IPV6_FLOW:
2783 /* For IP only 2-tupple hash is supported */
2784 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
2785 DP(BNX2X_MSG_ETHTOOL,
2786 "Command parameters not supported\n");
2787 return -EINVAL;
2788 } else {
2789 return 0;
2790 }
2791 case SCTP_V4_FLOW:
2792 case AH_ESP_V4_FLOW:
2793 case AH_V4_FLOW:
2794 case ESP_V4_FLOW:
2795 case SCTP_V6_FLOW:
2796 case AH_ESP_V6_FLOW:
2797 case AH_V6_FLOW:
2798 case ESP_V6_FLOW:
2799 case IP_USER_FLOW:
2800 case ETHER_FLOW:
2801 /* RSS is not supported for these protocols */
2802 if (info->data) {
2803 DP(BNX2X_MSG_ETHTOOL,
2804 "Command parameters not supported\n");
2805 return -EINVAL;
2806 } else {
2807 return 0;
2808 }
2809 default:
2810 return -EINVAL;
2811 }
2812}
2813
2814static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
2815{
2816 struct bnx2x *bp = netdev_priv(dev);
ab532cf3 2817
5d317c6a
MS		 2818 switch (info->cmd) {
2819 case ETHTOOL_SRXFH:
2820 return bnx2x_set_rss_flags(bp, info);
ab532cf3 2821 default:
51c1a580 2822 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
ab532cf3
TH		 2823 return -EOPNOTSUPP;
2824 }
2825}
2826
7850f63f
BH		 2827static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2828{
96305234 2829 return T_ETH_INDIRECTION_TABLE_SIZE;
7850f63f
BH		 2830}
2831
2832static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
ab532cf3
TH		 2833{
2834 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 2835 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2836 size_t i;
ab532cf3 2837
619c5cb6
VZ		 2838 /* Get the current configuration of the RSS indirection table */
2839 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2840
2841 /*
2842 * We can't use a memcpy() as an internal storage of an
2843 * indirection table is a u8 array while indir->ring_index
2844 * points to an array of u32.
2845 *
2846 * Indirection table contains the FW Client IDs, so we need to
2847 * align the returned table to the Client ID of the leading RSS
2848 * queue.
2849 */
7850f63f
BH		 2850 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2851 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 2852
ab532cf3
TH		 2853 return 0;
2854}
2855
7850f63f 2856static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
ab532cf3
TH		 2857{
2858 struct bnx2x *bp = netdev_priv(dev);
2859 size_t i;
619c5cb6
VZ		 2860
2861 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6
VZ		 2862 /*
2863 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2864 * as an internal storage of an indirection table is a u8 array
2865 * while indir->ring_index points to an array of u32.
2866 *
2867 * Indirection table contains the FW Client IDs, so we need to
2868 * align the received table to the Client ID of the leading RSS
2869 * queue
2870 */
5d317c6a 2871 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 2872 }
ab532cf3 2873
5d317c6a 2874 return bnx2x_config_rss_eth(bp, false);
ab532cf3
TH		 2875}
2876
0e8d2ec5
MS		 2877/**
2878 * bnx2x_get_channels - gets the number of RSS queues.
2879 *
2880 * @dev: net device
2881 * @channels: returns the number of max / current queues
2882 */
2883static void bnx2x_get_channels(struct net_device *dev,
2884 struct ethtool_channels *channels)
2885{
2886 struct bnx2x *bp = netdev_priv(dev);
2887
2888 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
2889 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
2890}
2891
2892/**
2893 * bnx2x_change_num_queues - change the number of RSS queues.
2894 *
2895 * @bp: bnx2x private structure
2896 *
2897 * Re-configure interrupt mode to get the new number of MSI-X
2898 * vectors and re-add NAPI objects.
2899 */
2900static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
2901{
0e8d2ec5 2902 bnx2x_disable_msi(bp);
55c11941
MS		 2903 bp->num_ethernet_queues = num_rss;
2904 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
2905 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
0e8d2ec5 2906 bnx2x_set_int_mode(bp);
0e8d2ec5
MS		 2907}
2908
2909/**
2910 * bnx2x_set_channels - sets the number of RSS queues.
2911 *
2912 * @dev: net device
2913 * @channels: includes the number of queues requested
2914 */
2915static int bnx2x_set_channels(struct net_device *dev,
2916 struct ethtool_channels *channels)
2917{
2918 struct bnx2x *bp = netdev_priv(dev);
2919
2920
2921 DP(BNX2X_MSG_ETHTOOL,
2922 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
2923 channels->rx_count, channels->tx_count, channels->other_count,
2924 channels->combined_count);
2925
2926 /* We don't support separate rx / tx channels.
2927 * We don't allow setting 'other' channels.
2928 */
2929 if (channels->rx_count || channels->tx_count || channels->other_count
2930 || (channels->combined_count == 0) ||
2931 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
2932 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
2933 return -EINVAL;
2934 }
2935
2936 /* Check if there was a change in the active parameters */
2937 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
2938 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
2939 return 0;
2940 }
2941
2942 /* Set the requested number of queues in bp context.
2943 * Note that the actual number of queues created during load may be
2944 * less than requested if memory is low.
2945 */
2946 if (unlikely(!netif_running(dev))) {
2947 bnx2x_change_num_queues(bp, channels->combined_count);
2948 return 0;
2949 }
5d07d868 2950 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
0e8d2ec5
MS		 2951 bnx2x_change_num_queues(bp, channels->combined_count);
2952 return bnx2x_nic_load(bp, LOAD_NORMAL);
2953}
2954
de0c62db
DK		 2955static const struct ethtool_ops bnx2x_ethtool_ops = {
2956 .get_settings = bnx2x_get_settings,
2957 .set_settings = bnx2x_set_settings,
2958 .get_drvinfo = bnx2x_get_drvinfo,
2959 .get_regs_len = bnx2x_get_regs_len,
2960 .get_regs = bnx2x_get_regs,
2961 .get_wol = bnx2x_get_wol,
2962 .set_wol = bnx2x_set_wol,
2963 .get_msglevel = bnx2x_get_msglevel,
2964 .set_msglevel = bnx2x_set_msglevel,
2965 .nway_reset = bnx2x_nway_reset,
2966 .get_link = bnx2x_get_link,
2967 .get_eeprom_len = bnx2x_get_eeprom_len,
2968 .get_eeprom = bnx2x_get_eeprom,
2969 .set_eeprom = bnx2x_set_eeprom,
2970 .get_coalesce = bnx2x_get_coalesce,
2971 .set_coalesce = bnx2x_set_coalesce,
2972 .get_ringparam = bnx2x_get_ringparam,
2973 .set_ringparam = bnx2x_set_ringparam,
2974 .get_pauseparam = bnx2x_get_pauseparam,
2975 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 2976 .self_test = bnx2x_self_test,
2977 .get_sset_count = bnx2x_get_sset_count,
2978 .get_strings = bnx2x_get_strings,
32d36134 2979 .set_phys_id = bnx2x_set_phys_id,
de0c62db 2980 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 2981 .get_rxnfc = bnx2x_get_rxnfc,
5d317c6a 2982 .set_rxnfc = bnx2x_set_rxnfc,
7850f63f 2983 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
ab532cf3
TH		 2984 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2985 .set_rxfh_indir = bnx2x_set_rxfh_indir,
0e8d2ec5
MS		 2986 .get_channels = bnx2x_get_channels,
2987 .set_channels = bnx2x_set_channels,
24ea818e
YM		 2988 .get_module_info = bnx2x_get_module_info,
2989 .get_module_eeprom = bnx2x_get_module_eeprom,
e9939c80
YM		 2990 .get_eee = bnx2x_get_eee,
2991 .set_eee = bnx2x_set_eee,
be53ce1e 2992 .get_ts_info = ethtool_op_get_ts_info,
de0c62db
DK		 2993};
2994
2995void bnx2x_set_ethtool_ops(struct net_device *netdev)
2996{
2997 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2998}
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