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bnx2x: Add support for external LB
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
85b26ea1 3 * Copyright (c) 2007-2012 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
de0c62db
DK		 25#include "bnx2x.h"
26#include "bnx2x_cmn.h"
27#include "bnx2x_dump.h"
4a33bc03 28#include "bnx2x_init.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
ec6ba945
VZ		 66};
67
68#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
69
70static const struct {
71 long offset;
72 int size;
73 u32 flags;
74#define STATS_FLAGS_PORT 1
75#define STATS_FLAGS_FUNC 2
76#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
77 char string[ETH_GSTRING_LEN];
78} bnx2x_stats_arr[] = {
79/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_bytes" },
81 { STATS_OFFSET32(error_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
83 { STATS_OFFSET32(total_unicast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
85 { STATS_OFFSET32(total_multicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
87 { STATS_OFFSET32(total_broadcast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
89 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
90 8, STATS_FLAGS_PORT, "rx_crc_errors" },
91 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
92 8, STATS_FLAGS_PORT, "rx_align_errors" },
93 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
94 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
95 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
97/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
98 8, STATS_FLAGS_PORT, "rx_fragments" },
99 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
100 8, STATS_FLAGS_PORT, "rx_jabbers" },
101 { STATS_OFFSET32(no_buff_discard_hi),
102 8, STATS_FLAGS_BOTH, "rx_discards" },
103 { STATS_OFFSET32(mac_filter_discard),
104 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 105 { STATS_OFFSET32(mf_tag_discard),
106 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 107 { STATS_OFFSET32(pfc_frames_received_hi),
108 8, STATS_FLAGS_PORT, "pfc_frames_received" },
109 { STATS_OFFSET32(pfc_frames_sent_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 111 { STATS_OFFSET32(brb_drop_hi),
112 8, STATS_FLAGS_PORT, "rx_brb_discard" },
113 { STATS_OFFSET32(brb_truncate_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
115 { STATS_OFFSET32(pause_frames_received_hi),
116 8, STATS_FLAGS_PORT, "rx_pause_frames" },
117 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
118 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
119 { STATS_OFFSET32(nig_timer_max),
120 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
121/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
122 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
123 { STATS_OFFSET32(rx_skb_alloc_failed),
124 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
125 { STATS_OFFSET32(hw_csum_err),
126 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
127
128 { STATS_OFFSET32(total_bytes_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_bytes" },
130 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
131 8, STATS_FLAGS_PORT, "tx_error_bytes" },
132 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
133 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
134 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
136 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
138 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
139 8, STATS_FLAGS_PORT, "tx_mac_errors" },
140 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
141 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
142/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
143 8, STATS_FLAGS_PORT, "tx_single_collisions" },
144 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
147 8, STATS_FLAGS_PORT, "tx_deferred" },
148 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
149 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
150 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_late_collisions" },
152 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_total_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
155 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
157 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
159 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
161 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
162/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
163 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
164 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
165 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
166 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
168 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 169 8, STATS_FLAGS_PORT, "tx_pause_frames" },
170 { STATS_OFFSET32(total_tpa_aggregations_hi),
171 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
172 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
174 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 175 8, STATS_FLAGS_FUNC, "tpa_bytes"},
176 { STATS_OFFSET32(recoverable_error),
177 4, STATS_FLAGS_FUNC, "recoverable_errors" },
178 { STATS_OFFSET32(unrecoverable_error),
179 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
e9939c80
YM		 180 { STATS_OFFSET32(eee_tx_lpi),
181 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
ec6ba945
VZ		 182};
183
184#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
1ac9e428
YR		 185static int bnx2x_get_port_type(struct bnx2x *bp)
186{
187 int port_type;
188 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
189 switch (bp->link_params.phy[phy_idx].media_type) {
190 case ETH_PHY_SFP_FIBER:
191 case ETH_PHY_XFP_FIBER:
192 case ETH_PHY_KR:
193 case ETH_PHY_CX4:
194 port_type = PORT_FIBRE;
195 break;
196 case ETH_PHY_DA_TWINAX:
197 port_type = PORT_DA;
198 break;
199 case ETH_PHY_BASE_T:
200 port_type = PORT_TP;
201 break;
202 case ETH_PHY_NOT_PRESENT:
203 port_type = PORT_NONE;
204 break;
205 case ETH_PHY_UNSPECIFIED:
206 default:
207 port_type = PORT_OTHER;
208 break;
209 }
210 return port_type;
211}
ec6ba945 212
de0c62db
DK		 213static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
214{
215 struct bnx2x *bp = netdev_priv(dev);
a22f0788 216 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 217
a22f0788
YR		 218 /* Dual Media boards present all available port types */
219 cmd->supported = bp->port.supported[cfg_idx] |
220 (bp->port.supported[cfg_idx ^ 1] &
221 (SUPPORTED_TP | SUPPORTED_FIBRE));
222 cmd->advertising = bp->port.advertising[cfg_idx];
de0c62db 223
38298461
YM		 224 if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) {
225 if (!(bp->flags & MF_FUNC_DIS)) {
226 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
227 cmd->duplex = bp->link_vars.duplex;
228 } else {
229 ethtool_cmd_speed_set(
230 cmd, bp->link_params.req_line_speed[cfg_idx]);
231 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
232 }
233
234 if (IS_MF(bp) && !BP_NOMCP(bp))
235 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
de0c62db 236 } else {
38298461
YM		 237 cmd->duplex = DUPLEX_UNKNOWN;
238 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
de0c62db 239 }
f2e0899f 240
1ac9e428 241 cmd->port = bnx2x_get_port_type(bp);
a22f0788 242
de0c62db
DK		 243 cmd->phy_address = bp->mdio.prtad;
244 cmd->transceiver = XCVR_INTERNAL;
245
a22f0788 246 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 247 cmd->autoneg = AUTONEG_ENABLE;
248 else
249 cmd->autoneg = AUTONEG_DISABLE;
250
9e7e8399
MY		 251 /* Publish LP advertised speeds and FC */
252 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
253 u32 status = bp->link_vars.link_status;
254
255 cmd->lp_advertising |= ADVERTISED_Autoneg;
256 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
257 cmd->lp_advertising |= ADVERTISED_Pause;
258 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
259 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
260
261 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
262 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
263 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
264 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
265 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
266 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
267 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
268 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
269 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
270 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
271 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
272 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
273 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
274 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
275 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
276 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
277 }
278
de0c62db
DK		 279 cmd->maxtxpkt = 0;
280 cmd->maxrxpkt = 0;
281
51c1a580 282 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 283 " supported 0x%x advertising 0x%x speed %u\n"
284 " duplex %d port %d phy_address %d transceiver %d\n"
285 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 286 cmd->cmd, cmd->supported, cmd->advertising,
287 ethtool_cmd_speed(cmd),
de0c62db
DK		 288 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
289 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
290
291 return 0;
292}
293
294static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
295{
296 struct bnx2x *bp = netdev_priv(dev);
a22f0788 297 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
0793f83f 298 u32 speed;
de0c62db 299
0793f83f 300 if (IS_MF_SD(bp))
de0c62db
DK		 301 return 0;
302
51c1a580 303 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
b3337e4c 304 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 305 " duplex %d port %d phy_address %d transceiver %d\n"
306 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 307 cmd->cmd, cmd->supported, cmd->advertising,
308 ethtool_cmd_speed(cmd),
de0c62db
DK		 309 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
310 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
311
b3337e4c 312 speed = ethtool_cmd_speed(cmd);
0793f83f 313
38298461
YM		 314 /* If recieved a request for an unknown duplex, assume full*/
315 if (cmd->duplex == DUPLEX_UNKNOWN)
316 cmd->duplex = DUPLEX_FULL;
317
0793f83f 318 if (IS_MF_SI(bp)) {
e3835b99 319 u32 part;
0793f83f
DK		 320 u32 line_speed = bp->link_vars.line_speed;
321
322 /* use 10G if no link detected */
323 if (!line_speed)
324 line_speed = 10000;
325
326 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
51c1a580
MS		 327 DP(BNX2X_MSG_ETHTOOL,
328 "To set speed BC %X or higher is required, please upgrade BC\n",
329 REQ_BC_VER_4_SET_MF_BW);
0793f83f
DK		 330 return -EINVAL;
331 }
e3835b99 332
faa6fcbb 333 part = (speed * 100) / line_speed;
e3835b99 334
faa6fcbb 335 if (line_speed < speed || !part) {
51c1a580
MS		 336 DP(BNX2X_MSG_ETHTOOL,
337 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
0793f83f
DK		 338 return -EINVAL;
339 }
0793f83f 340
e3835b99
DK		 341 if (bp->state != BNX2X_STATE_OPEN)
342 /* store value for following "load" */
343 bp->pending_max = part;
344 else
345 bnx2x_update_max_mf_config(bp, part);
0793f83f 346
0793f83f
DK		 347 return 0;
348 }
349
a22f0788
YR		 350 cfg_idx = bnx2x_get_link_cfg_idx(bp);
351 old_multi_phy_config = bp->link_params.multi_phy_config;
352 switch (cmd->port) {
353 case PORT_TP:
354 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
355 break; /* no port change */
356
357 if (!(bp->port.supported[0] & SUPPORTED_TP ||
358 bp->port.supported[1] & SUPPORTED_TP)) {
51c1a580 359 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 360 return -EINVAL;
361 }
362 bp->link_params.multi_phy_config &=
363 ~PORT_HW_CFG_PHY_SELECTION_MASK;
364 if (bp->link_params.multi_phy_config &
365 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
366 bp->link_params.multi_phy_config |=
367 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
368 else
369 bp->link_params.multi_phy_config |=
370 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
371 break;
372 case PORT_FIBRE:
bfdb5823 373 case PORT_DA:
a22f0788
YR		 374 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
375 break; /* no port change */
376
377 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
378 bp->port.supported[1] & SUPPORTED_FIBRE)) {
51c1a580 379 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 380 return -EINVAL;
381 }
382 bp->link_params.multi_phy_config &=
383 ~PORT_HW_CFG_PHY_SELECTION_MASK;
384 if (bp->link_params.multi_phy_config &
385 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
386 bp->link_params.multi_phy_config |=
387 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
388 else
389 bp->link_params.multi_phy_config |=
390 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
391 break;
392 default:
51c1a580 393 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 394 return -EINVAL;
395 }
2f751a80 396 /* Save new config in case command complete successully */
a22f0788
YR		 397 new_multi_phy_config = bp->link_params.multi_phy_config;
398 /* Get the new cfg_idx */
399 cfg_idx = bnx2x_get_link_cfg_idx(bp);
400 /* Restore old config in case command failed */
401 bp->link_params.multi_phy_config = old_multi_phy_config;
51c1a580 402 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
a22f0788 403
de0c62db 404 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 405 u32 an_supported_speed = bp->port.supported[cfg_idx];
406 if (bp->link_params.phy[EXT_PHY1].type ==
407 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
408 an_supported_speed |= (SUPPORTED_100baseT_Half |
409 SUPPORTED_100baseT_Full);
a22f0788 410 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 411 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
de0c62db
DK		 412 return -EINVAL;
413 }
414
415 /* advertise the requested speed and duplex if supported */
75318327 416 if (cmd->advertising & ~an_supported_speed) {
51c1a580
MS		 417 DP(BNX2X_MSG_ETHTOOL,
418 "Advertisement parameters are not supported\n");
8d661637
YR		 419 return -EINVAL;
420 }
de0c62db 421
a22f0788 422 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 423 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
424 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 425 cmd->advertising);
8d661637
YR		 426 if (cmd->advertising) {
427
428 bp->link_params.speed_cap_mask[cfg_idx] = 0;
429 if (cmd->advertising & ADVERTISED_10baseT_Half) {
430 bp->link_params.speed_cap_mask[cfg_idx] |=
431 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
432 }
433 if (cmd->advertising & ADVERTISED_10baseT_Full)
434 bp->link_params.speed_cap_mask[cfg_idx] |=
435 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 436
8d661637
YR		 437 if (cmd->advertising & ADVERTISED_100baseT_Full)
438 bp->link_params.speed_cap_mask[cfg_idx] |=
439 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
440
441 if (cmd->advertising & ADVERTISED_100baseT_Half) {
442 bp->link_params.speed_cap_mask[cfg_idx] |=
443 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
444 }
445 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
446 bp->link_params.speed_cap_mask[cfg_idx] |=
447 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
448 }
449 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
450 ADVERTISED_1000baseKX_Full))
451 bp->link_params.speed_cap_mask[cfg_idx] |=
452 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
453
454 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
455 ADVERTISED_10000baseKX4_Full |
456 ADVERTISED_10000baseKR_Full))
457 bp->link_params.speed_cap_mask[cfg_idx] |=
458 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
459 }
de0c62db
DK		 460 } else { /* forced speed */
461 /* advertise the requested speed and duplex if supported */
a22f0788 462 switch (speed) {
de0c62db
DK		 463 case SPEED_10:
464 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 465 if (!(bp->port.supported[cfg_idx] &
de0c62db 466 SUPPORTED_10baseT_Full)) {
51c1a580 467 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 468 "10M full not supported\n");
469 return -EINVAL;
470 }
471
472 advertising = (ADVERTISED_10baseT_Full |
473 ADVERTISED_TP);
474 } else {
a22f0788 475 if (!(bp->port.supported[cfg_idx] &
de0c62db 476 SUPPORTED_10baseT_Half)) {
51c1a580 477 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 478 "10M half not supported\n");
479 return -EINVAL;
480 }
481
482 advertising = (ADVERTISED_10baseT_Half |
483 ADVERTISED_TP);
484 }
485 break;
486
487 case SPEED_100:
488 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 489 if (!(bp->port.supported[cfg_idx] &
de0c62db 490 SUPPORTED_100baseT_Full)) {
51c1a580 491 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 492 "100M full not supported\n");
493 return -EINVAL;
494 }
495
496 advertising = (ADVERTISED_100baseT_Full |
497 ADVERTISED_TP);
498 } else {
a22f0788 499 if (!(bp->port.supported[cfg_idx] &
de0c62db 500 SUPPORTED_100baseT_Half)) {
51c1a580 501 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 502 "100M half not supported\n");
503 return -EINVAL;
504 }
505
506 advertising = (ADVERTISED_100baseT_Half |
507 ADVERTISED_TP);
508 }
509 break;
510
511 case SPEED_1000:
512 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 513 DP(BNX2X_MSG_ETHTOOL,
514 "1G half not supported\n");
de0c62db
DK		 515 return -EINVAL;
516 }
517
a22f0788
YR		 518 if (!(bp->port.supported[cfg_idx] &
519 SUPPORTED_1000baseT_Full)) {
51c1a580
MS		 520 DP(BNX2X_MSG_ETHTOOL,
521 "1G full not supported\n");
de0c62db
DK		 522 return -EINVAL;
523 }
524
525 advertising = (ADVERTISED_1000baseT_Full |
526 ADVERTISED_TP);
527 break;
528
529 case SPEED_2500:
530 if (cmd->duplex != DUPLEX_FULL) {
51c1a580 531 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 532 "2.5G half not supported\n");
533 return -EINVAL;
534 }
535
a22f0788
YR		 536 if (!(bp->port.supported[cfg_idx]
537 & SUPPORTED_2500baseX_Full)) {
51c1a580 538 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 539 "2.5G full not supported\n");
540 return -EINVAL;
541 }
542
543 advertising = (ADVERTISED_2500baseX_Full |
544 ADVERTISED_TP);
545 break;
546
547 case SPEED_10000:
548 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 549 DP(BNX2X_MSG_ETHTOOL,
550 "10G half not supported\n");
de0c62db
DK		 551 return -EINVAL;
552 }
553
a22f0788
YR		 554 if (!(bp->port.supported[cfg_idx]
555 & SUPPORTED_10000baseT_Full)) {
51c1a580
MS		 556 DP(BNX2X_MSG_ETHTOOL,
557 "10G full not supported\n");
de0c62db
DK		 558 return -EINVAL;
559 }
560
561 advertising = (ADVERTISED_10000baseT_Full |
562 ADVERTISED_FIBRE);
563 break;
564
565 default:
51c1a580 566 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
de0c62db
DK		 567 return -EINVAL;
568 }
569
a22f0788
YR		 570 bp->link_params.req_line_speed[cfg_idx] = speed;
571 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
572 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 573 }
574
51c1a580 575 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
f1deab50 576 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 577 bp->link_params.req_line_speed[cfg_idx],
578 bp->link_params.req_duplex[cfg_idx],
579 bp->port.advertising[cfg_idx]);
de0c62db 580
a22f0788
YR		 581 /* Set new config */
582 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 583 if (netif_running(dev)) {
584 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
585 bnx2x_link_set(bp);
586 }
587
588 return 0;
589}
590
591#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
592#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 593#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
0fea29c1
VZ		 594#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
595#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
596
1191cb83
ED		 597static bool bnx2x_is_reg_online(struct bnx2x *bp,
598 const struct reg_addr *reg_info)
0fea29c1
VZ		 599{
600 if (CHIP_IS_E1(bp))
601 return IS_E1_ONLINE(reg_info->info);
602 else if (CHIP_IS_E1H(bp))
603 return IS_E1H_ONLINE(reg_info->info);
604 else if (CHIP_IS_E2(bp))
605 return IS_E2_ONLINE(reg_info->info);
606 else if (CHIP_IS_E3A0(bp))
607 return IS_E3_ONLINE(reg_info->info);
608 else if (CHIP_IS_E3B0(bp))
609 return IS_E3B0_ONLINE(reg_info->info);
610 else
611 return false;
612}
613
614/******* Paged registers info selectors ********/
1191cb83 615static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
0fea29c1
VZ		 616{
617 if (CHIP_IS_E2(bp))
618 return page_vals_e2;
619 else if (CHIP_IS_E3(bp))
620 return page_vals_e3;
621 else
622 return NULL;
623}
624
1191cb83 625static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
0fea29c1
VZ		 626{
627 if (CHIP_IS_E2(bp))
628 return PAGE_MODE_VALUES_E2;
629 else if (CHIP_IS_E3(bp))
630 return PAGE_MODE_VALUES_E3;
631 else
632 return 0;
633}
634
1191cb83 635static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
0fea29c1
VZ		 636{
637 if (CHIP_IS_E2(bp))
638 return page_write_regs_e2;
639 else if (CHIP_IS_E3(bp))
640 return page_write_regs_e3;
641 else
642 return NULL;
643}
644
1191cb83 645static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
0fea29c1
VZ		 646{
647 if (CHIP_IS_E2(bp))
648 return PAGE_WRITE_REGS_E2;
649 else if (CHIP_IS_E3(bp))
650 return PAGE_WRITE_REGS_E3;
651 else
652 return 0;
653}
654
1191cb83 655static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
0fea29c1
VZ		 656{
657 if (CHIP_IS_E2(bp))
658 return page_read_regs_e2;
659 else if (CHIP_IS_E3(bp))
660 return page_read_regs_e3;
661 else
662 return NULL;
663}
664
1191cb83 665static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
0fea29c1
VZ		 666{
667 if (CHIP_IS_E2(bp))
668 return PAGE_READ_REGS_E2;
669 else if (CHIP_IS_E3(bp))
670 return PAGE_READ_REGS_E3;
671 else
672 return 0;
673}
674
1191cb83 675static int __bnx2x_get_regs_len(struct bnx2x *bp)
0fea29c1
VZ		 676{
677 int num_pages = __bnx2x_get_page_reg_num(bp);
678 int page_write_num = __bnx2x_get_page_write_num(bp);
679 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
680 int page_read_num = __bnx2x_get_page_read_num(bp);
681 int regdump_len = 0;
682 int i, j, k;
683
684 for (i = 0; i < REGS_COUNT; i++)
685 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
686 regdump_len += reg_addrs[i].size;
687
688 for (i = 0; i < num_pages; i++)
689 for (j = 0; j < page_write_num; j++)
690 for (k = 0; k < page_read_num; k++)
691 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
692 regdump_len += page_read_addr[k].size;
693
694 return regdump_len;
695}
de0c62db
DK		 696
697static int bnx2x_get_regs_len(struct net_device *dev)
698{
699 struct bnx2x *bp = netdev_priv(dev);
700 int regdump_len = 0;
de0c62db 701
0fea29c1 702 regdump_len = __bnx2x_get_regs_len(bp);
de0c62db
DK		 703 regdump_len *= 4;
704 regdump_len += sizeof(struct dump_hdr);
705
706 return regdump_len;
707}
708
0fea29c1
VZ		 709/**
710 * bnx2x_read_pages_regs - read "paged" registers
711 *
712 * @bp device handle
713 * @p output buffer
714 *
715 * Reads "paged" memories: memories that may only be read by first writing to a
716 * specific address ("write address") and then reading from a specific address
717 * ("read address"). There may be more than one write address per "page" and
718 * more than one read address per write address.
719 */
1191cb83 720static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
f2e0899f
DK		 721{
722 u32 i, j, k, n;
0fea29c1
VZ		 723 /* addresses of the paged registers */
724 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
725 /* number of paged registers */
726 int num_pages = __bnx2x_get_page_reg_num(bp);
727 /* write addresses */
728 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
729 /* number of write addresses */
730 int write_num = __bnx2x_get_page_write_num(bp);
731 /* read addresses info */
732 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
733 /* number of read addresses */
734 int read_num = __bnx2x_get_page_read_num(bp);
735
736 for (i = 0; i < num_pages; i++) {
737 for (j = 0; j < write_num; j++) {
738 REG_WR(bp, write_addr[j], page_addr[i]);
739 for (k = 0; k < read_num; k++)
740 if (bnx2x_is_reg_online(bp, &read_addr[k]))
f2e0899f 741 for (n = 0; n <
0fea29c1 742 read_addr[k].size; n++)
f2e0899f 743 *p++ = REG_RD(bp,
0fea29c1 744 read_addr[k].addr + n*4);
f2e0899f
DK		 745 }
746 }
747}
748
1191cb83 749static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
0fea29c1
VZ		 750{
751 u32 i, j;
752
753 /* Read the regular registers */
754 for (i = 0; i < REGS_COUNT; i++)
755 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
756 for (j = 0; j < reg_addrs[i].size; j++)
757 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
758
759 /* Read "paged" registes */
760 bnx2x_read_pages_regs(bp, p);
761}
762
de0c62db
DK		 763static void bnx2x_get_regs(struct net_device *dev,
764 struct ethtool_regs *regs, void *_p)
765{
0fea29c1 766 u32 *p = _p;
de0c62db
DK		 767 struct bnx2x *bp = netdev_priv(dev);
768 struct dump_hdr dump_hdr = {0};
769
770 regs->version = 0;
771 memset(p, 0, regs->len);
772
773 if (!netif_running(bp->dev))
774 return;
775
4a33bc03
VZ		 776 /* Disable parity attentions as long as following dump may
777 * cause false alarms by reading never written registers. We
778 * will re-enable parity attentions right after the dump.
779 */
780 bnx2x_disable_blocks_parity(bp);
781
de0c62db
DK		 782 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
783 dump_hdr.dump_sign = dump_sign_all;
784 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
785 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
786 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
787 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 788
789 if (CHIP_IS_E1(bp))
790 dump_hdr.info = RI_E1_ONLINE;
791 else if (CHIP_IS_E1H(bp))
792 dump_hdr.info = RI_E1H_ONLINE;
619c5cb6 793 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 794 dump_hdr.info = RI_E2_ONLINE |
795 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 796
797 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
798 p += dump_hdr.hdr_size + 1;
799
0fea29c1
VZ		 800 /* Actually read the registers */
801 __bnx2x_get_regs(bp, p);
802
4a33bc03
VZ		 803 /* Re-enable parity attentions */
804 bnx2x_clear_blocks_parity(bp);
c9ee9206 805 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 806}
807
de0c62db
DK		 808static void bnx2x_get_drvinfo(struct net_device *dev,
809 struct ethtool_drvinfo *info)
810{
811 struct bnx2x *bp = netdev_priv(dev);
812 u8 phy_fw_ver[PHY_FW_VER_LEN];
813
68aad78c
RJ		 814 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
815 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db
DK		 816
817 phy_fw_ver[0] = '\0';
a1e785e0
MY		 818 bnx2x_get_ext_phy_fw_version(&bp->link_params,
819 phy_fw_ver, PHY_FW_VER_LEN);
68aad78c 820 strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
de0c62db
DK		 821 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
822 "bc %d.%d.%d%s%s",
823 (bp->common.bc_ver & 0xff0000) >> 16,
824 (bp->common.bc_ver & 0xff00) >> 8,
825 (bp->common.bc_ver & 0xff),
826 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
68aad78c 827 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db
DK		 828 info->n_stats = BNX2X_NUM_STATS;
829 info->testinfo_len = BNX2X_NUM_TESTS;
830 info->eedump_len = bp->common.flash_size;
831 info->regdump_len = bnx2x_get_regs_len(dev);
832}
833
834static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
835{
836 struct bnx2x *bp = netdev_priv(dev);
837
838 if (bp->flags & NO_WOL_FLAG) {
839 wol->supported = 0;
840 wol->wolopts = 0;
841 } else {
842 wol->supported = WAKE_MAGIC;
843 if (bp->wol)
844 wol->wolopts = WAKE_MAGIC;
845 else
846 wol->wolopts = 0;
847 }
848 memset(&wol->sopass, 0, sizeof(wol->sopass));
849}
850
851static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
852{
853 struct bnx2x *bp = netdev_priv(dev);
854
51c1a580
MS		 855 if (wol->wolopts & ~WAKE_MAGIC) {
856 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 857 return -EINVAL;
51c1a580 858 }
de0c62db
DK		 859
860 if (wol->wolopts & WAKE_MAGIC) {
51c1a580
MS		 861 if (bp->flags & NO_WOL_FLAG) {
862 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 863 return -EINVAL;
51c1a580 864 }
de0c62db
DK		 865 bp->wol = 1;
866 } else
867 bp->wol = 0;
868
869 return 0;
870}
871
872static u32 bnx2x_get_msglevel(struct net_device *dev)
873{
874 struct bnx2x *bp = netdev_priv(dev);
875
876 return bp->msg_enable;
877}
878
879static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
880{
881 struct bnx2x *bp = netdev_priv(dev);
882
7a25cc73
DK		 883 if (capable(CAP_NET_ADMIN)) {
884 /* dump MCP trace */
885 if (level & BNX2X_MSG_MCP)
886 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 887 bp->msg_enable = level;
7a25cc73 888 }
de0c62db
DK		 889}
890
891static int bnx2x_nway_reset(struct net_device *dev)
892{
893 struct bnx2x *bp = netdev_priv(dev);
894
895 if (!bp->port.pmf)
896 return 0;
897
898 if (netif_running(dev)) {
899 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
900 bnx2x_link_set(bp);
901 }
902
903 return 0;
904}
905
906static u32 bnx2x_get_link(struct net_device *dev)
907{
908 struct bnx2x *bp = netdev_priv(dev);
909
f2e0899f 910 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 911 return 0;
912
913 return bp->link_vars.link_up;
914}
915
916static int bnx2x_get_eeprom_len(struct net_device *dev)
917{
918 struct bnx2x *bp = netdev_priv(dev);
919
920 return bp->common.flash_size;
921}
922
f16da43b
AE		 923/* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
924 * we done things the other way around, if two pfs from the same port would
925 * attempt to access nvram at the same time, we could run into a scenario such
926 * as:
927 * pf A takes the port lock.
928 * pf B succeeds in taking the same lock since they are from the same port.
929 * pf A takes the per pf misc lock. Performs eeprom access.
930 * pf A finishes. Unlocks the per pf misc lock.
931 * Pf B takes the lock and proceeds to perform it's own access.
932 * pf A unlocks the per port lock, while pf B is still working (!).
933 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
934 * acess corrupted by pf B).*
935 */
de0c62db
DK		 936static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
937{
938 int port = BP_PORT(bp);
939 int count, i;
f16da43b
AE		 940 u32 val;
941
942 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
943 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 944
945 /* adjust timeout for emulation/FPGA */
754a2f52 946 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 947 if (CHIP_REV_IS_SLOW(bp))
948 count *= 100;
949
950 /* request access to nvram interface */
951 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
952 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
953
954 for (i = 0; i < count*10; i++) {
955 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
956 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
957 break;
958
959 udelay(5);
960 }
961
962 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
51c1a580
MS		 963 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
964 "cannot get access to nvram interface\n");
de0c62db
DK		 965 return -EBUSY;
966 }
967
968 return 0;
969}
970
971static int bnx2x_release_nvram_lock(struct bnx2x *bp)
972{
973 int port = BP_PORT(bp);
974 int count, i;
f16da43b 975 u32 val;
de0c62db
DK		 976
977 /* adjust timeout for emulation/FPGA */
754a2f52 978 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 979 if (CHIP_REV_IS_SLOW(bp))
980 count *= 100;
981
982 /* relinquish nvram interface */
983 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
984 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
985
986 for (i = 0; i < count*10; i++) {
987 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
988 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
989 break;
990
991 udelay(5);
992 }
993
994 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
51c1a580
MS		 995 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
996 "cannot free access to nvram interface\n");
de0c62db
DK		 997 return -EBUSY;
998 }
999
f16da43b
AE		 1000 /* release HW lock: protect against other PFs in PF Direct Assignment */
1001 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1002 return 0;
1003}
1004
1005static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1006{
1007 u32 val;
1008
1009 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1010
1011 /* enable both bits, even on read */
1012 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1013 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1014 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1015}
1016
1017static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1018{
1019 u32 val;
1020
1021 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1022
1023 /* disable both bits, even after read */
1024 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1025 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1026 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1027}
1028
1029static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1030 u32 cmd_flags)
1031{
1032 int count, i, rc;
1033 u32 val;
1034
1035 /* build the command word */
1036 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1037
1038 /* need to clear DONE bit separately */
1039 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1040
1041 /* address of the NVRAM to read from */
1042 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1043 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1044
1045 /* issue a read command */
1046 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1047
1048 /* adjust timeout for emulation/FPGA */
754a2f52 1049 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1050 if (CHIP_REV_IS_SLOW(bp))
1051 count *= 100;
1052
1053 /* wait for completion */
1054 *ret_val = 0;
1055 rc = -EBUSY;
1056 for (i = 0; i < count; i++) {
1057 udelay(5);
1058 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1059
1060 if (val & MCPR_NVM_COMMAND_DONE) {
1061 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1062 /* we read nvram data in cpu order
1063 * but ethtool sees it as an array of bytes
1064 * converting to big-endian will do the work */
1065 *ret_val = cpu_to_be32(val);
1066 rc = 0;
1067 break;
1068 }
1069 }
51c1a580
MS		 1070 if (rc == -EBUSY)
1071 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1072 "nvram read timeout expired\n");
de0c62db
DK		 1073 return rc;
1074}
1075
1076static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1077 int buf_size)
1078{
1079 int rc;
1080 u32 cmd_flags;
1081 __be32 val;
1082
1083 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1084 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1085 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1086 offset, buf_size);
1087 return -EINVAL;
1088 }
1089
1090 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1091 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1092 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1093 offset, buf_size, bp->common.flash_size);
1094 return -EINVAL;
1095 }
1096
1097 /* request access to nvram interface */
1098 rc = bnx2x_acquire_nvram_lock(bp);
1099 if (rc)
1100 return rc;
1101
1102 /* enable access to nvram interface */
1103 bnx2x_enable_nvram_access(bp);
1104
1105 /* read the first word(s) */
1106 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1107 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1108 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1109 memcpy(ret_buf, &val, 4);
1110
1111 /* advance to the next dword */
1112 offset += sizeof(u32);
1113 ret_buf += sizeof(u32);
1114 buf_size -= sizeof(u32);
1115 cmd_flags = 0;
1116 }
1117
1118 if (rc == 0) {
1119 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1120 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1121 memcpy(ret_buf, &val, 4);
1122 }
1123
1124 /* disable access to nvram interface */
1125 bnx2x_disable_nvram_access(bp);
1126 bnx2x_release_nvram_lock(bp);
1127
1128 return rc;
1129}
1130
1131static int bnx2x_get_eeprom(struct net_device *dev,
1132 struct ethtool_eeprom *eeprom, u8 *eebuf)
1133{
1134 struct bnx2x *bp = netdev_priv(dev);
1135 int rc;
1136
51c1a580
MS		 1137 if (!netif_running(dev)) {
1138 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1139 "cannot access eeprom when the interface is down\n");
de0c62db 1140 return -EAGAIN;
51c1a580 1141 }
de0c62db 1142
51c1a580 1143 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1144 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1145 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1146 eeprom->len, eeprom->len);
1147
1148 /* parameters already validated in ethtool_get_eeprom */
1149
1150 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1151
1152 return rc;
1153}
1154
1155static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1156 u32 cmd_flags)
1157{
1158 int count, i, rc;
1159
1160 /* build the command word */
1161 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1162
1163 /* need to clear DONE bit separately */
1164 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1165
1166 /* write the data */
1167 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1168
1169 /* address of the NVRAM to write to */
1170 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1171 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1172
1173 /* issue the write command */
1174 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1175
1176 /* adjust timeout for emulation/FPGA */
754a2f52 1177 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1178 if (CHIP_REV_IS_SLOW(bp))
1179 count *= 100;
1180
1181 /* wait for completion */
1182 rc = -EBUSY;
1183 for (i = 0; i < count; i++) {
1184 udelay(5);
1185 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1186 if (val & MCPR_NVM_COMMAND_DONE) {
1187 rc = 0;
1188 break;
1189 }
1190 }
1191
51c1a580
MS		 1192 if (rc == -EBUSY)
1193 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1194 "nvram write timeout expired\n");
de0c62db
DK		 1195 return rc;
1196}
1197
1198#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1199
1200static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1201 int buf_size)
1202{
1203 int rc;
1204 u32 cmd_flags;
1205 u32 align_offset;
1206 __be32 val;
1207
1208 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1209 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1210 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1211 offset, buf_size, bp->common.flash_size);
1212 return -EINVAL;
1213 }
1214
1215 /* request access to nvram interface */
1216 rc = bnx2x_acquire_nvram_lock(bp);
1217 if (rc)
1218 return rc;
1219
1220 /* enable access to nvram interface */
1221 bnx2x_enable_nvram_access(bp);
1222
1223 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1224 align_offset = (offset & ~0x03);
1225 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1226
1227 if (rc == 0) {
1228 val &= ~(0xff << BYTE_OFFSET(offset));
1229 val |= (*data_buf << BYTE_OFFSET(offset));
1230
1231 /* nvram data is returned as an array of bytes
1232 * convert it back to cpu order */
1233 val = be32_to_cpu(val);
1234
1235 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1236 cmd_flags);
1237 }
1238
1239 /* disable access to nvram interface */
1240 bnx2x_disable_nvram_access(bp);
1241 bnx2x_release_nvram_lock(bp);
1242
1243 return rc;
1244}
1245
1246static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1247 int buf_size)
1248{
1249 int rc;
1250 u32 cmd_flags;
1251 u32 val;
1252 u32 written_so_far;
1253
1254 if (buf_size == 1) /* ethtool */
1255 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1256
1257 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1258 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1259 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1260 offset, buf_size);
1261 return -EINVAL;
1262 }
1263
1264 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1265 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1266 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1267 offset, buf_size, bp->common.flash_size);
1268 return -EINVAL;
1269 }
1270
1271 /* request access to nvram interface */
1272 rc = bnx2x_acquire_nvram_lock(bp);
1273 if (rc)
1274 return rc;
1275
1276 /* enable access to nvram interface */
1277 bnx2x_enable_nvram_access(bp);
1278
1279 written_so_far = 0;
1280 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1281 while ((written_so_far < buf_size) && (rc == 0)) {
1282 if (written_so_far == (buf_size - sizeof(u32)))
1283 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1284 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1285 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1286 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1287 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1288
1289 memcpy(&val, data_buf, 4);
1290
1291 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1292
1293 /* advance to the next dword */
1294 offset += sizeof(u32);
1295 data_buf += sizeof(u32);
1296 written_so_far += sizeof(u32);
1297 cmd_flags = 0;
1298 }
1299
1300 /* disable access to nvram interface */
1301 bnx2x_disable_nvram_access(bp);
1302 bnx2x_release_nvram_lock(bp);
1303
1304 return rc;
1305}
1306
1307static int bnx2x_set_eeprom(struct net_device *dev,
1308 struct ethtool_eeprom *eeprom, u8 *eebuf)
1309{
1310 struct bnx2x *bp = netdev_priv(dev);
1311 int port = BP_PORT(bp);
1312 int rc = 0;
e10bc84d 1313 u32 ext_phy_config;
51c1a580
MS		 1314 if (!netif_running(dev)) {
1315 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1316 "cannot access eeprom when the interface is down\n");
de0c62db 1317 return -EAGAIN;
51c1a580 1318 }
de0c62db 1319
51c1a580 1320 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1321 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1322 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1323 eeprom->len, eeprom->len);
1324
1325 /* parameters already validated in ethtool_set_eeprom */
1326
1327 /* PHY eeprom can be accessed only by the PMF */
1328 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
51c1a580
MS		 1329 !bp->port.pmf) {
1330 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1331 "wrong magic or interface is not pmf\n");
de0c62db 1332 return -EINVAL;
51c1a580 1333 }
de0c62db 1334
e10bc84d
YR		 1335 ext_phy_config =
1336 SHMEM_RD(bp,
1337 dev_info.port_hw_config[port].external_phy_config);
1338
de0c62db
DK		 1339 if (eeprom->magic == 0x50485950) {
1340 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1341 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1342
1343 bnx2x_acquire_phy_lock(bp);
1344 rc |= bnx2x_link_reset(&bp->link_params,
1345 &bp->link_vars, 0);
e10bc84d 1346 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1347 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1348 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1349 MISC_REGISTERS_GPIO_HIGH, port);
1350 bnx2x_release_phy_lock(bp);
1351 bnx2x_link_report(bp);
1352
1353 } else if (eeprom->magic == 0x50485952) {
1354 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1355 if (bp->state == BNX2X_STATE_OPEN) {
1356 bnx2x_acquire_phy_lock(bp);
1357 rc |= bnx2x_link_reset(&bp->link_params,
1358 &bp->link_vars, 1);
1359
1360 rc |= bnx2x_phy_init(&bp->link_params,
1361 &bp->link_vars);
1362 bnx2x_release_phy_lock(bp);
1363 bnx2x_calc_fc_adv(bp);
1364 }
1365 } else if (eeprom->magic == 0x53985943) {
1366 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1367 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1368 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1369
1370 /* DSP Remove Download Mode */
1371 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1372 MISC_REGISTERS_GPIO_LOW, port);
1373
1374 bnx2x_acquire_phy_lock(bp);
1375
e10bc84d
YR		 1376 bnx2x_sfx7101_sp_sw_reset(bp,
1377 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1378
1379 /* wait 0.5 sec to allow it to run */
1380 msleep(500);
1381 bnx2x_ext_phy_hw_reset(bp, port);
1382 msleep(500);
1383 bnx2x_release_phy_lock(bp);
1384 }
1385 } else
1386 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1387
1388 return rc;
1389}
f85582f8 1390
de0c62db
DK		 1391static int bnx2x_get_coalesce(struct net_device *dev,
1392 struct ethtool_coalesce *coal)
1393{
1394 struct bnx2x *bp = netdev_priv(dev);
1395
1396 memset(coal, 0, sizeof(struct ethtool_coalesce));
1397
1398 coal->rx_coalesce_usecs = bp->rx_ticks;
1399 coal->tx_coalesce_usecs = bp->tx_ticks;
1400
1401 return 0;
1402}
1403
1404static int bnx2x_set_coalesce(struct net_device *dev,
1405 struct ethtool_coalesce *coal)
1406{
1407 struct bnx2x *bp = netdev_priv(dev);
1408
1409 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1410 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1411 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1412
1413 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1414 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1415 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1416
1417 if (netif_running(dev))
1418 bnx2x_update_coalesce(bp);
1419
1420 return 0;
1421}
1422
1423static void bnx2x_get_ringparam(struct net_device *dev,
1424 struct ethtool_ringparam *ering)
1425{
1426 struct bnx2x *bp = netdev_priv(dev);
1427
1428 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1429
25141580
DK		 1430 if (bp->rx_ring_size)
1431 ering->rx_pending = bp->rx_ring_size;
1432 else
c2188952 1433 ering->rx_pending = MAX_RX_AVAIL;
25141580 1434
a3348722 1435 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
de0c62db
DK		 1436 ering->tx_pending = bp->tx_ring_size;
1437}
1438
1439static int bnx2x_set_ringparam(struct net_device *dev,
1440 struct ethtool_ringparam *ering)
1441{
1442 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 1443
1444 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 1445 DP(BNX2X_MSG_ETHTOOL,
1446 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 1447 return -EAGAIN;
1448 }
1449
1450 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1451 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1452 MIN_RX_SIZE_TPA)) ||
a3348722 1453 (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
51c1a580
MS		 1454 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1455 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db 1456 return -EINVAL;
51c1a580 1457 }
de0c62db
DK		 1458
1459 bp->rx_ring_size = ering->rx_pending;
1460 bp->tx_ring_size = ering->tx_pending;
1461
a9fccec7 1462 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1463}
1464
1465static void bnx2x_get_pauseparam(struct net_device *dev,
1466 struct ethtool_pauseparam *epause)
1467{
1468 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1469 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1470 int cfg_reg;
1471
a22f0788
YR		 1472 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1473 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1474
9e7e8399 1475 if (!epause->autoneg)
241fb5d2 1476 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
9e7e8399
MY		 1477 else
1478 cfg_reg = bp->link_params.req_fc_auto_adv;
1479
1480 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1481 BNX2X_FLOW_CTRL_RX);
9e7e8399 1482 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1483 BNX2X_FLOW_CTRL_TX);
1484
51c1a580 1485 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1486 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1487 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1488}
1489
1490static int bnx2x_set_pauseparam(struct net_device *dev,
1491 struct ethtool_pauseparam *epause)
1492{
1493 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1494 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1495 if (IS_MF(bp))
de0c62db
DK		 1496 return 0;
1497
51c1a580 1498 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1499 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1500 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1501
a22f0788 1502 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1503
1504 if (epause->rx_pause)
a22f0788 1505 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1506
1507 if (epause->tx_pause)
a22f0788 1508 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1509
a22f0788
YR		 1510 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1511 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1512
1513 if (epause->autoneg) {
a22f0788 1514 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 1515 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
de0c62db
DK		 1516 return -EINVAL;
1517 }
1518
a22f0788
YR		 1519 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1520 bp->link_params.req_flow_ctrl[cfg_idx] =
1521 BNX2X_FLOW_CTRL_AUTO;
1522 }
de0c62db
DK		 1523 }
1524
51c1a580 1525 DP(BNX2X_MSG_ETHTOOL,
a22f0788 1526 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1527
1528 if (netif_running(dev)) {
1529 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1530 bnx2x_link_set(bp);
1531 }
1532
1533 return 0;
1534}
1535
de0c62db
DK		 1536static const struct {
1537 char string[ETH_GSTRING_LEN];
1538} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1539 { "register_test (offline)" },
1540 { "memory_test (offline)" },
8970b2e4
MS		 1541 { "int_loopback_test (offline)" },
1542 { "ext_loopback_test (offline)" },
de0c62db
DK		 1543 { "nvram_test (online)" },
1544 { "interrupt_test (online)" },
1545 { "link_test (online)" },
1546 { "idle check (online)" }
1547};
1548
e9939c80
YM		 1549static u32 bnx2x_eee_to_adv(u32 eee_adv)
1550{
1551 u32 modes = 0;
1552
1553 if (eee_adv & SHMEM_EEE_100M_ADV)
1554 modes |= ADVERTISED_100baseT_Full;
1555 if (eee_adv & SHMEM_EEE_1G_ADV)
1556 modes |= ADVERTISED_1000baseT_Full;
1557 if (eee_adv & SHMEM_EEE_10G_ADV)
1558 modes |= ADVERTISED_10000baseT_Full;
1559
1560 return modes;
1561}
1562
1563static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1564{
1565 u32 eee_adv = 0;
1566 if (modes & ADVERTISED_100baseT_Full)
1567 eee_adv |= SHMEM_EEE_100M_ADV;
1568 if (modes & ADVERTISED_1000baseT_Full)
1569 eee_adv |= SHMEM_EEE_1G_ADV;
1570 if (modes & ADVERTISED_10000baseT_Full)
1571 eee_adv |= SHMEM_EEE_10G_ADV;
1572
1573 return eee_adv << shift;
1574}
1575
1576static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1577{
1578 struct bnx2x *bp = netdev_priv(dev);
1579 u32 eee_cfg;
1580
1581 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1582 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1583 return -EOPNOTSUPP;
1584 }
1585
1586 eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
1587
1588 edata->supported =
1589 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1590 SHMEM_EEE_SUPPORTED_SHIFT);
1591
1592 edata->advertised =
1593 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1594 SHMEM_EEE_ADV_STATUS_SHIFT);
1595 edata->lp_advertised =
1596 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1597 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1598
1599 /* SHMEM value is in 16u units --> Convert to 1u units. */
1600 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1601
1602 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
1603 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
1604 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1605
1606 return 0;
1607}
1608
1609static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1610{
1611 struct bnx2x *bp = netdev_priv(dev);
1612 u32 eee_cfg;
1613 u32 advertised;
1614
1615 if (IS_MF(bp))
1616 return 0;
1617
1618 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1619 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1620 return -EOPNOTSUPP;
1621 }
1622
1623 eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
1624
1625 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1626 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1627 return -EOPNOTSUPP;
1628 }
1629
1630 advertised = bnx2x_adv_to_eee(edata->advertised,
1631 SHMEM_EEE_ADV_STATUS_SHIFT);
1632 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1633 DP(BNX2X_MSG_ETHTOOL,
1634 "Direct manipulation of EEE advertisment is not supported\n");
1635 return -EINVAL;
1636 }
1637
1638 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1639 DP(BNX2X_MSG_ETHTOOL,
1640 "Maximal Tx Lpi timer supported is %x(u)\n",
1641 EEE_MODE_TIMER_MASK);
1642 return -EINVAL;
1643 }
1644 if (edata->tx_lpi_enabled &&
1645 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1646 DP(BNX2X_MSG_ETHTOOL,
1647 "Minimal Tx Lpi timer supported is %d(u)\n",
1648 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1649 return -EINVAL;
1650 }
1651
1652 /* All is well; Apply changes*/
1653 if (edata->eee_enabled)
1654 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1655 else
1656 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1657
1658 if (edata->tx_lpi_enabled)
1659 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1660 else
1661 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1662
1663 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1664 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1665 EEE_MODE_TIMER_MASK) |
1666 EEE_MODE_OVERRIDE_NVRAM |
1667 EEE_MODE_OUTPUT_TIME;
1668
1669 /* Restart link to propogate changes */
1670 if (netif_running(dev)) {
1671 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1672 bnx2x_link_set(bp);
1673 }
1674
1675 return 0;
1676}
1677
1678
619c5cb6
VZ		 1679enum {
1680 BNX2X_CHIP_E1_OFST = 0,
1681 BNX2X_CHIP_E1H_OFST,
1682 BNX2X_CHIP_E2_OFST,
1683 BNX2X_CHIP_E3_OFST,
1684 BNX2X_CHIP_E3B0_OFST,
1685 BNX2X_CHIP_MAX_OFST
1686};
1687
1688#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1689#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1690#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1691#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1692#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1693
1694#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1695#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1696
de0c62db
DK		 1697static int bnx2x_test_registers(struct bnx2x *bp)
1698{
1699 int idx, i, rc = -ENODEV;
619c5cb6 1700 u32 wr_val = 0, hw;
de0c62db
DK		 1701 int port = BP_PORT(bp);
1702 static const struct {
619c5cb6 1703 u32 hw;
de0c62db
DK		 1704 u32 offset0;
1705 u32 offset1;
1706 u32 mask;
1707 } reg_tbl[] = {
619c5cb6
VZ		 1708/* 0 */ { BNX2X_CHIP_MASK_ALL,
1709 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1710 { BNX2X_CHIP_MASK_ALL,
1711 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1712 { BNX2X_CHIP_MASK_E1X,
1713 HC_REG_AGG_INT_0, 4, 0x000003ff },
1714 { BNX2X_CHIP_MASK_ALL,
1715 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1716 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1717 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1718 { BNX2X_CHIP_MASK_E3B0,
1719 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1720 { BNX2X_CHIP_MASK_ALL,
1721 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1722 { BNX2X_CHIP_MASK_ALL,
1723 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1724 { BNX2X_CHIP_MASK_ALL,
1725 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1726 { BNX2X_CHIP_MASK_ALL,
1727 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1728/* 10 */ { BNX2X_CHIP_MASK_ALL,
1729 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1730 { BNX2X_CHIP_MASK_ALL,
1731 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1732 { BNX2X_CHIP_MASK_ALL,
1733 QM_REG_CONNNUM_0, 4, 0x000fffff },
1734 { BNX2X_CHIP_MASK_ALL,
1735 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1736 { BNX2X_CHIP_MASK_ALL,
1737 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1738 { BNX2X_CHIP_MASK_ALL,
1739 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1740 { BNX2X_CHIP_MASK_ALL,
1741 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1742 { BNX2X_CHIP_MASK_ALL,
1743 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1744 { BNX2X_CHIP_MASK_ALL,
1745 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1746 { BNX2X_CHIP_MASK_ALL,
1747 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1748/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1749 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1750 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1751 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1752 { BNX2X_CHIP_MASK_ALL,
1753 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1754 { BNX2X_CHIP_MASK_ALL,
1755 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1756 { BNX2X_CHIP_MASK_ALL,
1757 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1758 { BNX2X_CHIP_MASK_ALL,
1759 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1760 { BNX2X_CHIP_MASK_ALL,
1761 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1762 { BNX2X_CHIP_MASK_ALL,
1763 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1764 { BNX2X_CHIP_MASK_ALL,
1765 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1766 { BNX2X_CHIP_MASK_ALL,
1767 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1768/* 30 */ { BNX2X_CHIP_MASK_ALL,
1769 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1770 { BNX2X_CHIP_MASK_ALL,
1771 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1772 { BNX2X_CHIP_MASK_ALL,
1773 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1774 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1775 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1776 { BNX2X_CHIP_MASK_ALL,
1777 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1778 { BNX2X_CHIP_MASK_ALL,
1779 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1780 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1781 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1782 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1783 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1784
1785 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 1786 };
1787
51c1a580
MS		 1788 if (!netif_running(bp->dev)) {
1789 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1790 "cannot access eeprom when the interface is down\n");
de0c62db 1791 return rc;
51c1a580 1792 }
de0c62db 1793
619c5cb6
VZ		 1794 if (CHIP_IS_E1(bp))
1795 hw = BNX2X_CHIP_MASK_E1;
1796 else if (CHIP_IS_E1H(bp))
1797 hw = BNX2X_CHIP_MASK_E1H;
1798 else if (CHIP_IS_E2(bp))
1799 hw = BNX2X_CHIP_MASK_E2;
1800 else if (CHIP_IS_E3B0(bp))
1801 hw = BNX2X_CHIP_MASK_E3B0;
1802 else /* e3 A0 */
1803 hw = BNX2X_CHIP_MASK_E3;
1804
de0c62db
DK		 1805 /* Repeat the test twice:
1806 First by writing 0x00000000, second by writing 0xffffffff */
1807 for (idx = 0; idx < 2; idx++) {
1808
1809 switch (idx) {
1810 case 0:
1811 wr_val = 0;
1812 break;
1813 case 1:
1814 wr_val = 0xffffffff;
1815 break;
1816 }
1817
1818 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1819 u32 offset, mask, save_val, val;
619c5cb6 1820 if (!(hw & reg_tbl[i].hw))
f2e0899f 1821 continue;
de0c62db
DK		 1822
1823 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1824 mask = reg_tbl[i].mask;
1825
1826 save_val = REG_RD(bp, offset);
1827
ec6ba945 1828 REG_WR(bp, offset, wr_val & mask);
f85582f8 1829
de0c62db
DK		 1830 val = REG_RD(bp, offset);
1831
1832 /* Restore the original register's value */
1833 REG_WR(bp, offset, save_val);
1834
1835 /* verify value is as expected */
1836 if ((val & mask) != (wr_val & mask)) {
51c1a580 1837 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1838 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1839 offset, val, wr_val, mask);
1840 goto test_reg_exit;
1841 }
1842 }
1843 }
1844
1845 rc = 0;
1846
1847test_reg_exit:
1848 return rc;
1849}
1850
1851static int bnx2x_test_memory(struct bnx2x *bp)
1852{
1853 int i, j, rc = -ENODEV;
619c5cb6 1854 u32 val, index;
de0c62db
DK		 1855 static const struct {
1856 u32 offset;
1857 int size;
1858 } mem_tbl[] = {
1859 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1860 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1861 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1862 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1863 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1864 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1865 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1866
1867 { 0xffffffff, 0 }
1868 };
619c5cb6 1869
de0c62db
DK		 1870 static const struct {
1871 char *name;
1872 u32 offset;
619c5cb6 1873 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 1874 } prty_tbl[] = {
619c5cb6
VZ		 1875 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1876 {0x3ffc0, 0, 0, 0} },
1877 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1878 {0x2, 0x2, 0, 0} },
1879 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1880 {0, 0, 0, 0} },
1881 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1882 {0x3ffc0, 0, 0, 0} },
1883 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1884 {0x3ffc0, 0, 0, 0} },
1885 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1886 {0x3ffc1, 0, 0, 0} },
1887
1888 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 1889 };
1890
51c1a580
MS		 1891 if (!netif_running(bp->dev)) {
1892 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1893 "cannot access eeprom when the interface is down\n");
de0c62db 1894 return rc;
51c1a580 1895 }
de0c62db 1896
619c5cb6
VZ		 1897 if (CHIP_IS_E1(bp))
1898 index = BNX2X_CHIP_E1_OFST;
1899 else if (CHIP_IS_E1H(bp))
1900 index = BNX2X_CHIP_E1H_OFST;
1901 else if (CHIP_IS_E2(bp))
1902 index = BNX2X_CHIP_E2_OFST;
1903 else /* e3 */
1904 index = BNX2X_CHIP_E3_OFST;
1905
f2e0899f
DK		 1906 /* pre-Check the parity status */
1907 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1908 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1909 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1910 DP(BNX2X_MSG_ETHTOOL,
f2e0899f
DK		 1911 "%s is 0x%x\n", prty_tbl[i].name, val);
1912 goto test_mem_exit;
1913 }
1914 }
1915
de0c62db
DK		 1916 /* Go through all the memories */
1917 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1918 for (j = 0; j < mem_tbl[i].size; j++)
1919 REG_RD(bp, mem_tbl[i].offset + j*4);
1920
1921 /* Check the parity status */
1922 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1923 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1924 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1925 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1926 "%s is 0x%x\n", prty_tbl[i].name, val);
1927 goto test_mem_exit;
1928 }
1929 }
1930
1931 rc = 0;
1932
1933test_mem_exit:
1934 return rc;
1935}
1936
a22f0788 1937static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 1938{
f2e0899f 1939 int cnt = 1400;
de0c62db 1940
619c5cb6 1941 if (link_up) {
a22f0788 1942 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 1943 msleep(20);
1944
1945 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
51c1a580 1946 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
8970b2e4
MS		 1947
1948 cnt = 1400;
1949 while (!bp->link_vars.link_up && cnt--)
1950 msleep(20);
1951
1952 if (cnt <= 0 && !bp->link_vars.link_up)
1953 DP(BNX2X_MSG_ETHTOOL,
1954 "Timeout waiting for link init\n");
619c5cb6 1955 }
de0c62db
DK		 1956}
1957
619c5cb6 1958static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 1959{
1960 unsigned int pkt_size, num_pkts, i;
1961 struct sk_buff *skb;
1962 unsigned char *packet;
1963 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1964 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
6383c0b3 1965 struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
de0c62db
DK		 1966 u16 tx_start_idx, tx_idx;
1967 u16 rx_start_idx, rx_idx;
b0700b1e 1968 u16 pkt_prod, bd_prod;
de0c62db
DK		 1969 struct sw_tx_bd *tx_buf;
1970 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 1971 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1972 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 1973 dma_addr_t mapping;
1974 union eth_rx_cqe *cqe;
619c5cb6 1975 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 1976 struct sw_rx_bd *rx_buf;
1977 u16 len;
1978 int rc = -ENODEV;
e52fcb24 1979 u8 *data;
8970b2e4
MS		 1980 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
1981 txdata->txq_index);
de0c62db
DK		 1982
1983 /* check the loopback mode */
1984 switch (loopback_mode) {
1985 case BNX2X_PHY_LOOPBACK:
8970b2e4
MS		 1986 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
1987 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
de0c62db 1988 return -EINVAL;
8970b2e4 1989 }
de0c62db
DK		 1990 break;
1991 case BNX2X_MAC_LOOPBACK:
32911333
YR		 1992 if (CHIP_IS_E3(bp)) {
1993 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1994 if (bp->port.supported[cfg_idx] &
1995 (SUPPORTED_10000baseT_Full |
1996 SUPPORTED_20000baseMLD2_Full |
1997 SUPPORTED_20000baseKR2_Full))
1998 bp->link_params.loopback_mode = LOOPBACK_XMAC;
1999 else
2000 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2001 } else
2002 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2003
de0c62db
DK		 2004 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2005 break;
8970b2e4
MS		 2006 case BNX2X_EXT_LOOPBACK:
2007 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2008 DP(BNX2X_MSG_ETHTOOL,
2009 "Can't configure external loopback\n");
2010 return -EINVAL;
2011 }
2012 break;
de0c62db 2013 default:
51c1a580 2014 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db
DK		 2015 return -EINVAL;
2016 }
2017
2018 /* prepare the loopback packet */
2019 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2020 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 2021 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db 2022 if (!skb) {
51c1a580 2023 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
de0c62db
DK		 2024 rc = -ENOMEM;
2025 goto test_loopback_exit;
2026 }
2027 packet = skb_put(skb, pkt_size);
2028 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2029 memset(packet + ETH_ALEN, 0, ETH_ALEN);
2030 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2031 for (i = ETH_HLEN; i < pkt_size; i++)
2032 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 2033 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2034 skb_headlen(skb), DMA_TO_DEVICE);
2035 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2036 rc = -ENOMEM;
2037 dev_kfree_skb(skb);
51c1a580 2038 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
619c5cb6
VZ		 2039 goto test_loopback_exit;
2040 }
de0c62db
DK		 2041
2042 /* send the loopback packet */
2043 num_pkts = 0;
6383c0b3 2044 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2045 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2046
73dbb5e1
DK		 2047 netdev_tx_sent_queue(txq, skb->len);
2048
6383c0b3
AE		 2049 pkt_prod = txdata->tx_pkt_prod++;
2050 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2051 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 2052 tx_buf->skb = skb;
2053 tx_buf->flags = 0;
2054
6383c0b3
AE		 2055 bd_prod = TX_BD(txdata->tx_bd_prod);
2056 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 2057 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2058 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2059 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2060 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 2061 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 2062 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 2063 SET_FLAG(tx_start_bd->general_data,
2064 ETH_TX_START_BD_ETH_ADDR_TYPE,
2065 UNICAST_ADDRESS);
2066 SET_FLAG(tx_start_bd->general_data,
2067 ETH_TX_START_BD_HDR_NBDS,
2068 1);
de0c62db
DK		 2069
2070 /* turn on parsing and get a BD */
2071 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 2072
6383c0b3
AE		 2073 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2074 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 2075
f2e0899f 2076 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 2077 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 2078
2079 wmb();
2080
6383c0b3 2081 txdata->tx_db.data.prod += 2;
de0c62db 2082 barrier();
6383c0b3 2083 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 2084
2085 mmiowb();
619c5cb6 2086 barrier();
de0c62db
DK		 2087
2088 num_pkts++;
6383c0b3 2089 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 2090
2091 udelay(100);
2092
6383c0b3 2093 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2094 if (tx_idx != tx_start_idx + num_pkts)
2095 goto test_loopback_exit;
2096
f2e0899f
DK		 2097 /* Unlike HC IGU won't generate an interrupt for status block
2098 * updates that have been performed while interrupts were
2099 * disabled.
2100 */
e1210d12
ED		 2101 if (bp->common.int_block == INT_BLOCK_IGU) {
2102 /* Disable local BHes to prevent a dead-lock situation between
2103 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2104 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2105 */
2106 local_bh_disable();
6383c0b3 2107 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 2108 local_bh_enable();
2109 }
f2e0899f 2110
de0c62db
DK		 2111 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2112 if (rx_idx != rx_start_idx + num_pkts)
2113 goto test_loopback_exit;
2114
b0700b1e 2115 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 2116 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 2117 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2118 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 2119 goto test_loopback_rx_exit;
2120
621b4d66 2121 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
de0c62db
DK		 2122 if (len != pkt_size)
2123 goto test_loopback_rx_exit;
2124
2125 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 2126 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 2127 dma_unmap_addr(rx_buf, mapping),
2128 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 2129 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 2130 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 2131 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 2132 goto test_loopback_rx_exit;
2133
2134 rc = 0;
2135
2136test_loopback_rx_exit:
2137
2138 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2139 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2140 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2141 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2142
2143 /* Update producers */
2144 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2145 fp_rx->rx_sge_prod);
2146
2147test_loopback_exit:
2148 bp->link_params.loopback_mode = LOOPBACK_NONE;
2149
2150 return rc;
2151}
2152
619c5cb6 2153static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 2154{
2155 int rc = 0, res;
2156
2157 if (BP_NOMCP(bp))
2158 return rc;
2159
2160 if (!netif_running(bp->dev))
2161 return BNX2X_LOOPBACK_FAILED;
2162
2163 bnx2x_netif_stop(bp, 1);
2164 bnx2x_acquire_phy_lock(bp);
2165
619c5cb6 2166 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db 2167 if (res) {
51c1a580 2168 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
de0c62db
DK		 2169 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2170 }
2171
619c5cb6 2172 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db 2173 if (res) {
51c1a580 2174 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
de0c62db
DK		 2175 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2176 }
2177
2178 bnx2x_release_phy_lock(bp);
2179 bnx2x_netif_start(bp);
2180
2181 return rc;
2182}
2183
8970b2e4
MS		 2184static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2185{
2186 int rc;
2187 u8 is_serdes =
2188 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2189
2190 if (BP_NOMCP(bp))
2191 return -ENODEV;
2192
2193 if (!netif_running(bp->dev))
2194 return BNX2X_EXT_LOOPBACK_FAILED;
2195
2196 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2197 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2198 if (rc) {
2199 DP(BNX2X_MSG_ETHTOOL,
2200 "Can't perform self-test, nic_load (for external lb) failed\n");
2201 return -ENODEV;
2202 }
2203 bnx2x_wait_for_link(bp, 1, is_serdes);
2204
2205 bnx2x_netif_stop(bp, 1);
2206
2207 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2208 if (rc)
2209 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2210
2211 bnx2x_netif_start(bp);
2212
2213 return rc;
2214}
2215
de0c62db
DK		 2216#define CRC32_RESIDUAL 0xdebb20e3
2217
2218static int bnx2x_test_nvram(struct bnx2x *bp)
2219{
2220 static const struct {
2221 int offset;
2222 int size;
2223 } nvram_tbl[] = {
2224 { 0, 0x14 }, /* bootstrap */
2225 { 0x14, 0xec }, /* dir */
2226 { 0x100, 0x350 }, /* manuf_info */
2227 { 0x450, 0xf0 }, /* feature_info */
2228 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2229 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2230 { 0, 0 }
2231 };
afa13b4b
MY		 2232 __be32 *buf;
2233 u8 *data;
de0c62db
DK		 2234 int i, rc;
2235 u32 magic, crc;
2236
2237 if (BP_NOMCP(bp))
2238 return 0;
2239
afa13b4b
MY		 2240 buf = kmalloc(0x350, GFP_KERNEL);
2241 if (!buf) {
51c1a580 2242 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
afa13b4b
MY		 2243 rc = -ENOMEM;
2244 goto test_nvram_exit;
2245 }
2246 data = (u8 *)buf;
2247
de0c62db
DK		 2248 rc = bnx2x_nvram_read(bp, 0, data, 4);
2249 if (rc) {
51c1a580
MS		 2250 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2251 "magic value read (rc %d)\n", rc);
de0c62db
DK		 2252 goto test_nvram_exit;
2253 }
2254
2255 magic = be32_to_cpu(buf[0]);
2256 if (magic != 0x669955aa) {
51c1a580
MS		 2257 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2258 "wrong magic value (0x%08x)\n", magic);
de0c62db
DK		 2259 rc = -ENODEV;
2260 goto test_nvram_exit;
2261 }
2262
2263 for (i = 0; nvram_tbl[i].size; i++) {
2264
2265 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2266 nvram_tbl[i].size);
2267 if (rc) {
51c1a580 2268 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 2269 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2270 goto test_nvram_exit;
2271 }
2272
2273 crc = ether_crc_le(nvram_tbl[i].size, data);
2274 if (crc != CRC32_RESIDUAL) {
51c1a580
MS		 2275 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2276 "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
de0c62db
DK		 2277 rc = -ENODEV;
2278 goto test_nvram_exit;
2279 }
2280 }
2281
2282test_nvram_exit:
afa13b4b 2283 kfree(buf);
de0c62db
DK		 2284 return rc;
2285}
2286
619c5cb6 2287/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2288static int bnx2x_test_intr(struct bnx2x *bp)
2289{
3b603066 2290 struct bnx2x_queue_state_params params = {NULL};
de0c62db 2291
51c1a580
MS		 2292 if (!netif_running(bp->dev)) {
2293 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2294 "cannot access eeprom when the interface is down\n");
de0c62db 2295 return -ENODEV;
51c1a580 2296 }
de0c62db 2297
619c5cb6
VZ		 2298 params.q_obj = &bp->fp->q_obj;
2299 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2300
619c5cb6
VZ		 2301 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2302
2303 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2304}
2305
2306static void bnx2x_self_test(struct net_device *dev,
2307 struct ethtool_test *etest, u64 *buf)
2308{
2309 struct bnx2x *bp = netdev_priv(dev);
a22f0788 2310 u8 is_serdes;
de0c62db 2311 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 2312 netdev_err(bp->dev,
2313 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 2314 etest->flags |= ETH_TEST_FL_FAILED;
2315 return;
2316 }
8970b2e4
MS		 2317 DP(BNX2X_MSG_ETHTOOL,
2318 "Self-test command parameters: offline = %d, external_lb = %d\n",
2319 (etest->flags & ETH_TEST_FL_OFFLINE),
2320 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
de0c62db
DK		 2321
2322 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
2323
2324 if (!netif_running(dev))
2325 return;
2326
2327 /* offline tests are not supported in MF mode */
fb3bff17 2328 if (IS_MF(bp))
de0c62db 2329 etest->flags &= ~ETH_TEST_FL_OFFLINE;
a22f0788 2330 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db
DK		 2331
2332 if (etest->flags & ETH_TEST_FL_OFFLINE) {
2333 int port = BP_PORT(bp);
2334 u32 val;
2335 u8 link_up;
2336
2337 /* save current value of input enable for TX port IF */
2338 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2339 /* disable input for TX port IF */
2340 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2341
a22f0788
YR		 2342 link_up = bp->link_vars.link_up;
2343
de0c62db
DK		 2344 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2345 bnx2x_nic_load(bp, LOAD_DIAG);
2346 /* wait until link state is restored */
619c5cb6 2347 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2348
2349 if (bnx2x_test_registers(bp) != 0) {
2350 buf[0] = 1;
2351 etest->flags |= ETH_TEST_FL_FAILED;
2352 }
2353 if (bnx2x_test_memory(bp) != 0) {
2354 buf[1] = 1;
2355 etest->flags |= ETH_TEST_FL_FAILED;
2356 }
f85582f8 2357
8970b2e4 2358 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
de0c62db
DK		 2359 if (buf[2] != 0)
2360 etest->flags |= ETH_TEST_FL_FAILED;
2361
8970b2e4
MS		 2362 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2363 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2364 if (buf[3] != 0)
2365 etest->flags |= ETH_TEST_FL_FAILED;
2366 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2367 }
2368
de0c62db
DK		 2369 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2370
2371 /* restore input for TX port IF */
2372 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2373
2374 bnx2x_nic_load(bp, LOAD_NORMAL);
2375 /* wait until link state is restored */
a22f0788 2376 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2377 }
2378 if (bnx2x_test_nvram(bp) != 0) {
8970b2e4 2379 buf[4] = 1;
de0c62db
DK		 2380 etest->flags |= ETH_TEST_FL_FAILED;
2381 }
2382 if (bnx2x_test_intr(bp) != 0) {
8970b2e4 2383 buf[5] = 1;
de0c62db
DK		 2384 etest->flags |= ETH_TEST_FL_FAILED;
2385 }
633ac363
DK		 2386
2387 if (bnx2x_link_test(bp, is_serdes) != 0) {
8970b2e4 2388 buf[6] = 1;
633ac363
DK		 2389 etest->flags |= ETH_TEST_FL_FAILED;
2390 }
de0c62db
DK		 2391
2392#ifdef BNX2X_EXTRA_DEBUG
2393 bnx2x_panic_dump(bp);
2394#endif
2395}
2396
de0c62db
DK		 2397#define IS_PORT_STAT(i) \
2398 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2399#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2400#define IS_MF_MODE_STAT(bp) \
2401 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2402
619c5cb6
VZ		 2403/* ethtool statistics are displayed for all regular ethernet queues and the
2404 * fcoe L2 queue if not disabled
2405 */
1191cb83 2406static int bnx2x_num_stat_queues(struct bnx2x *bp)
619c5cb6
VZ		 2407{
2408 return BNX2X_NUM_ETH_QUEUES(bp);
2409}
2410
de0c62db
DK		 2411static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2412{
2413 struct bnx2x *bp = netdev_priv(dev);
2414 int i, num_stats;
2415
2416 switch (stringset) {
2417 case ETH_SS_STATS:
2418 if (is_multi(bp)) {
619c5cb6 2419 num_stats = bnx2x_num_stat_queues(bp) *
d5e83632
YM		 2420 BNX2X_NUM_Q_STATS;
2421 } else
2422 num_stats = 0;
2423 if (IS_MF_MODE_STAT(bp)) {
2424 for (i = 0; i < BNX2X_NUM_STATS; i++)
2425 if (IS_FUNC_STAT(i))
2426 num_stats++;
2427 } else
2428 num_stats += BNX2X_NUM_STATS;
2429
de0c62db
DK		 2430 return num_stats;
2431
2432 case ETH_SS_TEST:
2433 return BNX2X_NUM_TESTS;
2434
2435 default:
2436 return -EINVAL;
2437 }
2438}
2439
2440static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2441{
2442 struct bnx2x *bp = netdev_priv(dev);
2443 int i, j, k;
ec6ba945 2444 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2445
2446 switch (stringset) {
2447 case ETH_SS_STATS:
d5e83632 2448 k = 0;
de0c62db 2449 if (is_multi(bp)) {
619c5cb6 2450 for_each_eth_queue(bp, i) {
ec6ba945 2451 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2452 sprintf(queue_name, "%d", i);
de0c62db 2453 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2454 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2455 ETH_GSTRING_LEN,
2456 bnx2x_q_stats_arr[j].string,
2457 queue_name);
de0c62db
DK		 2458 k += BNX2X_NUM_Q_STATS;
2459 }
de0c62db 2460 }
d5e83632
YM		 2461
2462
2463 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2464 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2465 continue;
2466 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2467 bnx2x_stats_arr[i].string);
2468 j++;
2469 }
2470
de0c62db
DK		 2471 break;
2472
2473 case ETH_SS_TEST:
2474 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2475 break;
2476 }
2477}
2478
2479static void bnx2x_get_ethtool_stats(struct net_device *dev,
2480 struct ethtool_stats *stats, u64 *buf)
2481{
2482 struct bnx2x *bp = netdev_priv(dev);
2483 u32 *hw_stats, *offset;
d5e83632 2484 int i, j, k = 0;
de0c62db
DK		 2485
2486 if (is_multi(bp)) {
619c5cb6 2487 for_each_eth_queue(bp, i) {
de0c62db
DK		 2488 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2489 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2490 if (bnx2x_q_stats_arr[j].size == 0) {
2491 /* skip this counter */
2492 buf[k + j] = 0;
2493 continue;
2494 }
2495 offset = (hw_stats +
2496 bnx2x_q_stats_arr[j].offset);
2497 if (bnx2x_q_stats_arr[j].size == 4) {
2498 /* 4-byte counter */
2499 buf[k + j] = (u64) *offset;
2500 continue;
2501 }
2502 /* 8-byte counter */
2503 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2504 }
2505 k += BNX2X_NUM_Q_STATS;
2506 }
d5e83632
YM		 2507 }
2508
2509 hw_stats = (u32 *)&bp->eth_stats;
2510 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2511 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2512 continue;
2513 if (bnx2x_stats_arr[i].size == 0) {
2514 /* skip this counter */
2515 buf[k + j] = 0;
2516 j++;
2517 continue;
de0c62db 2518 }
d5e83632
YM		 2519 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2520 if (bnx2x_stats_arr[i].size == 4) {
2521 /* 4-byte counter */
2522 buf[k + j] = (u64) *offset;
de0c62db 2523 j++;
d5e83632 2524 continue;
de0c62db 2525 }
d5e83632
YM		 2526 /* 8-byte counter */
2527 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2528 j++;
de0c62db
DK		 2529 }
2530}
2531
32d36134 2532static int bnx2x_set_phys_id(struct net_device *dev,
2533 enum ethtool_phys_id_state state)
de0c62db
DK		 2534{
2535 struct bnx2x *bp = netdev_priv(dev);
de0c62db 2536
51c1a580
MS		 2537 if (!netif_running(dev)) {
2538 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2539 "cannot access eeprom when the interface is down\n");
32d36134 2540 return -EAGAIN;
51c1a580 2541 }
de0c62db 2542
51c1a580
MS		 2543 if (!bp->port.pmf) {
2544 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
32d36134 2545 return -EOPNOTSUPP;
51c1a580 2546 }
de0c62db 2547
32d36134 2548 switch (state) {
2549 case ETHTOOL_ID_ACTIVE:
fce55922 2550 return 1; /* cycle on/off once per second */
de0c62db 2551
32d36134 2552 case ETHTOOL_ID_ON:
2553 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2554 LED_MODE_ON, SPEED_1000);
32d36134 2555 break;
de0c62db 2556
32d36134 2557 case ETHTOOL_ID_OFF:
2558 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2559 LED_MODE_FRONT_PANEL_OFF, 0);
de0c62db 2560
32d36134 2561 break;
2562
2563 case ETHTOOL_ID_INACTIVE:
e1943424
DM		 2564 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2565 LED_MODE_OPER,
2566 bp->link_vars.line_speed);
32d36134 2567 }
de0c62db
DK		 2568
2569 return 0;
2570}
2571
ab532cf3 2572static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2573 u32 *rules __always_unused)
ab532cf3
TH		 2574{
2575 struct bnx2x *bp = netdev_priv(dev);
2576
2577 switch (info->cmd) {
2578 case ETHTOOL_GRXRINGS:
2579 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2580 return 0;
2581
2582 default:
51c1a580 2583 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
ab532cf3
TH		 2584 return -EOPNOTSUPP;
2585 }
2586}
2587
7850f63f
BH		 2588static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2589{
96305234 2590 return T_ETH_INDIRECTION_TABLE_SIZE;
7850f63f
BH		 2591}
2592
2593static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
ab532cf3
TH		 2594{
2595 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 2596 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2597 size_t i;
ab532cf3 2598
619c5cb6
VZ		 2599 /* Get the current configuration of the RSS indirection table */
2600 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2601
2602 /*
2603 * We can't use a memcpy() as an internal storage of an
2604 * indirection table is a u8 array while indir->ring_index
2605 * points to an array of u32.
2606 *
2607 * Indirection table contains the FW Client IDs, so we need to
2608 * align the returned table to the Client ID of the leading RSS
2609 * queue.
2610 */
7850f63f
BH		 2611 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2612 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 2613
ab532cf3
TH		 2614 return 0;
2615}
2616
7850f63f 2617static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
ab532cf3
TH		 2618{
2619 struct bnx2x *bp = netdev_priv(dev);
2620 size_t i;
619c5cb6 2621 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
619c5cb6
VZ		 2622
2623 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6
VZ		 2624 /*
2625 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2626 * as an internal storage of an indirection table is a u8 array
2627 * while indir->ring_index points to an array of u32.
2628 *
2629 * Indirection table contains the FW Client IDs, so we need to
2630 * align the received table to the Client ID of the leading RSS
2631 * queue
2632 */
7850f63f 2633 ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 2634 }
ab532cf3 2635
96305234 2636 return bnx2x_config_rss_eth(bp, ind_table, false);
ab532cf3
TH		 2637}
2638
de0c62db
DK		 2639static const struct ethtool_ops bnx2x_ethtool_ops = {
2640 .get_settings = bnx2x_get_settings,
2641 .set_settings = bnx2x_set_settings,
2642 .get_drvinfo = bnx2x_get_drvinfo,
2643 .get_regs_len = bnx2x_get_regs_len,
2644 .get_regs = bnx2x_get_regs,
2645 .get_wol = bnx2x_get_wol,
2646 .set_wol = bnx2x_set_wol,
2647 .get_msglevel = bnx2x_get_msglevel,
2648 .set_msglevel = bnx2x_set_msglevel,
2649 .nway_reset = bnx2x_nway_reset,
2650 .get_link = bnx2x_get_link,
2651 .get_eeprom_len = bnx2x_get_eeprom_len,
2652 .get_eeprom = bnx2x_get_eeprom,
2653 .set_eeprom = bnx2x_set_eeprom,
2654 .get_coalesce = bnx2x_get_coalesce,
2655 .set_coalesce = bnx2x_set_coalesce,
2656 .get_ringparam = bnx2x_get_ringparam,
2657 .set_ringparam = bnx2x_set_ringparam,
2658 .get_pauseparam = bnx2x_get_pauseparam,
2659 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 2660 .self_test = bnx2x_self_test,
2661 .get_sset_count = bnx2x_get_sset_count,
2662 .get_strings = bnx2x_get_strings,
32d36134 2663 .set_phys_id = bnx2x_set_phys_id,
de0c62db 2664 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 2665 .get_rxnfc = bnx2x_get_rxnfc,
7850f63f 2666 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
ab532cf3
TH		 2667 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2668 .set_rxfh_indir = bnx2x_set_rxfh_indir,
e9939c80
YM		 2669 .get_eee = bnx2x_get_eee,
2670 .set_eee = bnx2x_set_eee,
de0c62db
DK		 2671};
2672
2673void bnx2x_set_ethtool_ops(struct net_device *netdev)
2674{
2675 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2676}
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