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bnx2x: Fix statistics gathering on link change
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
08f6dd89 9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
de0c62db
DK		 10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
de0c62db
DK		 25#include "bnx2x.h"
26#include "bnx2x_cmn.h"
27#include "bnx2x_dump.h"
4a33bc03 28#include "bnx2x_init.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
c96bdc0c
DK		 65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
67 4, "[%s]: driver_filtered_tx_pkt" }
ec6ba945
VZ		 68};
69
70#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
71
72static const struct {
73 long offset;
74 int size;
75 u32 flags;
76#define STATS_FLAGS_PORT 1
77#define STATS_FLAGS_FUNC 2
78#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
79 char string[ETH_GSTRING_LEN];
80} bnx2x_stats_arr[] = {
81/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_bytes" },
83 { STATS_OFFSET32(error_bytes_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
85 { STATS_OFFSET32(total_unicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
87 { STATS_OFFSET32(total_multicast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
89 { STATS_OFFSET32(total_broadcast_packets_received_hi),
90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
92 8, STATS_FLAGS_PORT, "rx_crc_errors" },
93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
94 8, STATS_FLAGS_PORT, "rx_align_errors" },
95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
98 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
99/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
100 8, STATS_FLAGS_PORT, "rx_fragments" },
101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
102 8, STATS_FLAGS_PORT, "rx_jabbers" },
103 { STATS_OFFSET32(no_buff_discard_hi),
104 8, STATS_FLAGS_BOTH, "rx_discards" },
105 { STATS_OFFSET32(mac_filter_discard),
106 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 107 { STATS_OFFSET32(mf_tag_discard),
108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 109 { STATS_OFFSET32(pfc_frames_received_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_received" },
111 { STATS_OFFSET32(pfc_frames_sent_hi),
112 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 113 { STATS_OFFSET32(brb_drop_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_discard" },
115 { STATS_OFFSET32(brb_truncate_hi),
116 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
117 { STATS_OFFSET32(pause_frames_received_hi),
118 8, STATS_FLAGS_PORT, "rx_pause_frames" },
119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
121 { STATS_OFFSET32(nig_timer_max),
122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
123/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
125 { STATS_OFFSET32(rx_skb_alloc_failed),
126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
127 { STATS_OFFSET32(hw_csum_err),
128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
129
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, STATS_FLAGS_PORT, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, STATS_FLAGS_PORT, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
144/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, STATS_FLAGS_PORT, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, STATS_FLAGS_PORT, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
164/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 171 8, STATS_FLAGS_PORT, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 177 8, STATS_FLAGS_FUNC, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, STATS_FLAGS_FUNC, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
c96bdc0c
DK		 182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
e9939c80
YM		 184 { STATS_OFFSET32(eee_tx_lpi),
185 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
ec6ba945
VZ		 186};
187
188#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
07ba6af4 189
1ac9e428
YR		 190static int bnx2x_get_port_type(struct bnx2x *bp)
191{
192 int port_type;
193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 switch (bp->link_params.phy[phy_idx].media_type) {
dbef807e
YM		 195 case ETH_PHY_SFPP_10G_FIBER:
196 case ETH_PHY_SFP_1G_FIBER:
1ac9e428
YR		 197 case ETH_PHY_XFP_FIBER:
198 case ETH_PHY_KR:
199 case ETH_PHY_CX4:
200 port_type = PORT_FIBRE;
201 break;
202 case ETH_PHY_DA_TWINAX:
203 port_type = PORT_DA;
204 break;
205 case ETH_PHY_BASE_T:
206 port_type = PORT_TP;
207 break;
208 case ETH_PHY_NOT_PRESENT:
209 port_type = PORT_NONE;
210 break;
211 case ETH_PHY_UNSPECIFIED:
212 default:
213 port_type = PORT_OTHER;
214 break;
215 }
216 return port_type;
217}
ec6ba945 218
6495d15a
DK		 219static int bnx2x_get_vf_settings(struct net_device *dev,
220 struct ethtool_cmd *cmd)
221{
222 struct bnx2x *bp = netdev_priv(dev);
223
224 if (bp->state == BNX2X_STATE_OPEN) {
225 if (test_bit(BNX2X_LINK_REPORT_FD,
226 &bp->vf_link_vars.link_report_flags))
227 cmd->duplex = DUPLEX_FULL;
228 else
229 cmd->duplex = DUPLEX_HALF;
230
231 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed);
232 } else {
233 cmd->duplex = DUPLEX_UNKNOWN;
234 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
235 }
236
237 cmd->port = PORT_OTHER;
238 cmd->phy_address = 0;
239 cmd->transceiver = XCVR_INTERNAL;
240 cmd->autoneg = AUTONEG_DISABLE;
241 cmd->maxtxpkt = 0;
242 cmd->maxrxpkt = 0;
243
244 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
245 " supported 0x%x advertising 0x%x speed %u\n"
246 " duplex %d port %d phy_address %d transceiver %d\n"
247 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
248 cmd->cmd, cmd->supported, cmd->advertising,
249 ethtool_cmd_speed(cmd),
250 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
251 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
252
253 return 0;
254}
255
de0c62db
DK		 256static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
257{
258 struct bnx2x *bp = netdev_priv(dev);
a22f0788 259 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
5d67c1c5 260 u32 media_type;
b3337e4c 261
a22f0788
YR		 262 /* Dual Media boards present all available port types */
263 cmd->supported = bp->port.supported[cfg_idx] |
264 (bp->port.supported[cfg_idx ^ 1] &
265 (SUPPORTED_TP | SUPPORTED_FIBRE));
266 cmd->advertising = bp->port.advertising[cfg_idx];
5d67c1c5
YM		 267 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
268 if (media_type == ETH_PHY_SFP_1G_FIBER) {
dbef807e
YM		 269 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
270 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
271 }
de0c62db 272
59694f00
YM		 273 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
274 !(bp->flags & MF_FUNC_DIS)) {
2de67439 275 cmd->duplex = bp->link_vars.duplex;
38298461
YM		 276
277 if (IS_MF(bp) && !BP_NOMCP(bp))
278 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
59694f00
YM		 279 else
280 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
de0c62db 281 } else {
38298461
YM		 282 cmd->duplex = DUPLEX_UNKNOWN;
283 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
de0c62db 284 }
f2e0899f 285
1ac9e428 286 cmd->port = bnx2x_get_port_type(bp);
a22f0788 287
de0c62db
DK		 288 cmd->phy_address = bp->mdio.prtad;
289 cmd->transceiver = XCVR_INTERNAL;
290
a22f0788 291 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 292 cmd->autoneg = AUTONEG_ENABLE;
293 else
294 cmd->autoneg = AUTONEG_DISABLE;
295
9e7e8399
MY		 296 /* Publish LP advertised speeds and FC */
297 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
298 u32 status = bp->link_vars.link_status;
299
300 cmd->lp_advertising |= ADVERTISED_Autoneg;
301 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
302 cmd->lp_advertising |= ADVERTISED_Pause;
303 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
304 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
305
306 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
307 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
308 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
309 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
310 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
311 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
312 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
313 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
314 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
315 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
5d67c1c5
YM		 316 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
317 if (media_type == ETH_PHY_KR) {
318 cmd->lp_advertising |=
319 ADVERTISED_1000baseKX_Full;
320 } else {
321 cmd->lp_advertising |=
322 ADVERTISED_1000baseT_Full;
323 }
324 }
9e7e8399
MY		 325 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
326 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
5d67c1c5
YM		 327 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
328 if (media_type == ETH_PHY_KR) {
329 cmd->lp_advertising |=
330 ADVERTISED_10000baseKR_Full;
331 } else {
332 cmd->lp_advertising |=
333 ADVERTISED_10000baseT_Full;
334 }
335 }
be94bea7
YR		 336 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
337 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
9e7e8399
MY		 338 }
339
de0c62db
DK		 340 cmd->maxtxpkt = 0;
341 cmd->maxrxpkt = 0;
342
51c1a580 343 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 344 " supported 0x%x advertising 0x%x speed %u\n"
345 " duplex %d port %d phy_address %d transceiver %d\n"
346 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 347 cmd->cmd, cmd->supported, cmd->advertising,
348 ethtool_cmd_speed(cmd),
de0c62db
DK		 349 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
350 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
351
352 return 0;
353}
354
355static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
356{
357 struct bnx2x *bp = netdev_priv(dev);
a22f0788 358 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
dbef807e 359 u32 speed, phy_idx;
de0c62db 360
0793f83f 361 if (IS_MF_SD(bp))
de0c62db
DK		 362 return 0;
363
51c1a580 364 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
b3337e4c 365 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 366 " duplex %d port %d phy_address %d transceiver %d\n"
367 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 368 cmd->cmd, cmd->supported, cmd->advertising,
369 ethtool_cmd_speed(cmd),
de0c62db
DK		 370 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
371 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
372
b3337e4c 373 speed = ethtool_cmd_speed(cmd);
0793f83f 374
16a5fd92 375 /* If received a request for an unknown duplex, assume full*/
38298461
YM		 376 if (cmd->duplex == DUPLEX_UNKNOWN)
377 cmd->duplex = DUPLEX_FULL;
378
0793f83f 379 if (IS_MF_SI(bp)) {
e3835b99 380 u32 part;
0793f83f
DK		 381 u32 line_speed = bp->link_vars.line_speed;
382
383 /* use 10G if no link detected */
384 if (!line_speed)
385 line_speed = 10000;
386
387 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
51c1a580
MS		 388 DP(BNX2X_MSG_ETHTOOL,
389 "To set speed BC %X or higher is required, please upgrade BC\n",
390 REQ_BC_VER_4_SET_MF_BW);
0793f83f
DK		 391 return -EINVAL;
392 }
e3835b99 393
faa6fcbb 394 part = (speed * 100) / line_speed;
e3835b99 395
faa6fcbb 396 if (line_speed < speed || !part) {
51c1a580
MS		 397 DP(BNX2X_MSG_ETHTOOL,
398 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
0793f83f
DK		 399 return -EINVAL;
400 }
0793f83f 401
e3835b99
DK		 402 if (bp->state != BNX2X_STATE_OPEN)
403 /* store value for following "load" */
404 bp->pending_max = part;
405 else
406 bnx2x_update_max_mf_config(bp, part);
0793f83f 407
0793f83f
DK		 408 return 0;
409 }
410
a22f0788
YR		 411 cfg_idx = bnx2x_get_link_cfg_idx(bp);
412 old_multi_phy_config = bp->link_params.multi_phy_config;
33f9e6f5
YR		 413 if (cmd->port != bnx2x_get_port_type(bp)) {
414 switch (cmd->port) {
415 case PORT_TP:
416 if (!(bp->port.supported[0] & SUPPORTED_TP ||
417 bp->port.supported[1] & SUPPORTED_TP)) {
418 DP(BNX2X_MSG_ETHTOOL,
419 "Unsupported port type\n");
420 return -EINVAL;
421 }
422 bp->link_params.multi_phy_config &=
423 ~PORT_HW_CFG_PHY_SELECTION_MASK;
424 if (bp->link_params.multi_phy_config &
425 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
426 bp->link_params.multi_phy_config |=
427 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
428 else
429 bp->link_params.multi_phy_config |=
430 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
431 break;
432 case PORT_FIBRE:
433 case PORT_DA:
042d7654 434 case PORT_NONE:
33f9e6f5
YR		 435 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
436 bp->port.supported[1] & SUPPORTED_FIBRE)) {
437 DP(BNX2X_MSG_ETHTOOL,
438 "Unsupported port type\n");
439 return -EINVAL;
440 }
441 bp->link_params.multi_phy_config &=
442 ~PORT_HW_CFG_PHY_SELECTION_MASK;
443 if (bp->link_params.multi_phy_config &
444 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
445 bp->link_params.multi_phy_config |=
446 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
447 else
448 bp->link_params.multi_phy_config |=
449 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
450 break;
451 default:
51c1a580 452 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 453 return -EINVAL;
454 }
a22f0788 455 }
2de67439 456 /* Save new config in case command complete successfully */
a22f0788
YR		 457 new_multi_phy_config = bp->link_params.multi_phy_config;
458 /* Get the new cfg_idx */
459 cfg_idx = bnx2x_get_link_cfg_idx(bp);
460 /* Restore old config in case command failed */
461 bp->link_params.multi_phy_config = old_multi_phy_config;
51c1a580 462 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
a22f0788 463
de0c62db 464 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 465 u32 an_supported_speed = bp->port.supported[cfg_idx];
466 if (bp->link_params.phy[EXT_PHY1].type ==
467 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
468 an_supported_speed |= (SUPPORTED_100baseT_Half |
469 SUPPORTED_100baseT_Full);
a22f0788 470 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 471 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
de0c62db
DK		 472 return -EINVAL;
473 }
474
475 /* advertise the requested speed and duplex if supported */
75318327 476 if (cmd->advertising & ~an_supported_speed) {
51c1a580
MS		 477 DP(BNX2X_MSG_ETHTOOL,
478 "Advertisement parameters are not supported\n");
8d661637
YR		 479 return -EINVAL;
480 }
de0c62db 481
a22f0788 482 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 483 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
484 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 485 cmd->advertising);
8d661637
YR		 486 if (cmd->advertising) {
487
488 bp->link_params.speed_cap_mask[cfg_idx] = 0;
489 if (cmd->advertising & ADVERTISED_10baseT_Half) {
490 bp->link_params.speed_cap_mask[cfg_idx] |=
491 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
492 }
493 if (cmd->advertising & ADVERTISED_10baseT_Full)
494 bp->link_params.speed_cap_mask[cfg_idx] |=
495 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 496
8d661637
YR		 497 if (cmd->advertising & ADVERTISED_100baseT_Full)
498 bp->link_params.speed_cap_mask[cfg_idx] |=
499 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
500
501 if (cmd->advertising & ADVERTISED_100baseT_Half) {
502 bp->link_params.speed_cap_mask[cfg_idx] |=
503 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
504 }
505 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
506 bp->link_params.speed_cap_mask[cfg_idx] |=
507 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
508 }
509 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
510 ADVERTISED_1000baseKX_Full))
511 bp->link_params.speed_cap_mask[cfg_idx] |=
512 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
513
514 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
515 ADVERTISED_10000baseKX4_Full |
516 ADVERTISED_10000baseKR_Full))
517 bp->link_params.speed_cap_mask[cfg_idx] |=
518 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
be94bea7
YR		 519
520 if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
521 bp->link_params.speed_cap_mask[cfg_idx] |=
522 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
8d661637 523 }
de0c62db
DK		 524 } else { /* forced speed */
525 /* advertise the requested speed and duplex if supported */
a22f0788 526 switch (speed) {
de0c62db
DK		 527 case SPEED_10:
528 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 529 if (!(bp->port.supported[cfg_idx] &
de0c62db 530 SUPPORTED_10baseT_Full)) {
51c1a580 531 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 532 "10M full not supported\n");
533 return -EINVAL;
534 }
535
536 advertising = (ADVERTISED_10baseT_Full |
537 ADVERTISED_TP);
538 } else {
a22f0788 539 if (!(bp->port.supported[cfg_idx] &
de0c62db 540 SUPPORTED_10baseT_Half)) {
51c1a580 541 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 542 "10M half not supported\n");
543 return -EINVAL;
544 }
545
546 advertising = (ADVERTISED_10baseT_Half |
547 ADVERTISED_TP);
548 }
549 break;
550
551 case SPEED_100:
552 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 553 if (!(bp->port.supported[cfg_idx] &
de0c62db 554 SUPPORTED_100baseT_Full)) {
51c1a580 555 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 556 "100M full not supported\n");
557 return -EINVAL;
558 }
559
560 advertising = (ADVERTISED_100baseT_Full |
561 ADVERTISED_TP);
562 } else {
a22f0788 563 if (!(bp->port.supported[cfg_idx] &
de0c62db 564 SUPPORTED_100baseT_Half)) {
51c1a580 565 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 566 "100M half not supported\n");
567 return -EINVAL;
568 }
569
570 advertising = (ADVERTISED_100baseT_Half |
571 ADVERTISED_TP);
572 }
573 break;
574
575 case SPEED_1000:
576 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 577 DP(BNX2X_MSG_ETHTOOL,
578 "1G half not supported\n");
de0c62db
DK		 579 return -EINVAL;
580 }
581
5d67c1c5
YM		 582 if (bp->port.supported[cfg_idx] &
583 SUPPORTED_1000baseT_Full) {
584 advertising = (ADVERTISED_1000baseT_Full |
585 ADVERTISED_TP);
586
587 } else if (bp->port.supported[cfg_idx] &
588 SUPPORTED_1000baseKX_Full) {
589 advertising = ADVERTISED_1000baseKX_Full;
590 } else {
51c1a580
MS		 591 DP(BNX2X_MSG_ETHTOOL,
592 "1G full not supported\n");
de0c62db
DK		 593 return -EINVAL;
594 }
595
de0c62db
DK		 596 break;
597
598 case SPEED_2500:
599 if (cmd->duplex != DUPLEX_FULL) {
51c1a580 600 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 601 "2.5G half not supported\n");
602 return -EINVAL;
603 }
604
a22f0788
YR		 605 if (!(bp->port.supported[cfg_idx]
606 & SUPPORTED_2500baseX_Full)) {
51c1a580 607 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 608 "2.5G full not supported\n");
609 return -EINVAL;
610 }
611
612 advertising = (ADVERTISED_2500baseX_Full |
613 ADVERTISED_TP);
614 break;
615
616 case SPEED_10000:
617 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 618 DP(BNX2X_MSG_ETHTOOL,
619 "10G half not supported\n");
de0c62db
DK		 620 return -EINVAL;
621 }
dbef807e 622 phy_idx = bnx2x_get_cur_phy_idx(bp);
5d67c1c5
YM		 623 if ((bp->port.supported[cfg_idx] &
624 SUPPORTED_10000baseT_Full) &&
625 (bp->link_params.phy[phy_idx].media_type !=
dbef807e 626 ETH_PHY_SFP_1G_FIBER)) {
5d67c1c5
YM		 627 advertising = (ADVERTISED_10000baseT_Full |
628 ADVERTISED_FIBRE);
629 } else if (bp->port.supported[cfg_idx] &
630 SUPPORTED_10000baseKR_Full) {
631 advertising = (ADVERTISED_10000baseKR_Full |
632 ADVERTISED_FIBRE);
633 } else {
51c1a580
MS		 634 DP(BNX2X_MSG_ETHTOOL,
635 "10G full not supported\n");
de0c62db
DK		 636 return -EINVAL;
637 }
638
de0c62db
DK		 639 break;
640
641 default:
51c1a580 642 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
de0c62db
DK		 643 return -EINVAL;
644 }
645
a22f0788
YR		 646 bp->link_params.req_line_speed[cfg_idx] = speed;
647 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
648 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 649 }
650
51c1a580 651 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
f1deab50 652 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 653 bp->link_params.req_line_speed[cfg_idx],
654 bp->link_params.req_duplex[cfg_idx],
655 bp->port.advertising[cfg_idx]);
de0c62db 656
a22f0788
YR		 657 /* Set new config */
658 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 659 if (netif_running(dev)) {
660 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
dc6a20aa 661 bnx2x_force_link_reset(bp);
de0c62db
DK		 662 bnx2x_link_set(bp);
663 }
664
665 return 0;
666}
667
07ba6af4
MS		 668#define DUMP_ALL_PRESETS 0x1FFF
669#define DUMP_MAX_PRESETS 13
0fea29c1 670
07ba6af4 671static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
0fea29c1
VZ		 672{
673 if (CHIP_IS_E1(bp))
07ba6af4 674 return dump_num_registers[0][preset-1];
0fea29c1 675 else if (CHIP_IS_E1H(bp))
07ba6af4 676 return dump_num_registers[1][preset-1];
0fea29c1 677 else if (CHIP_IS_E2(bp))
07ba6af4 678 return dump_num_registers[2][preset-1];
0fea29c1 679 else if (CHIP_IS_E3A0(bp))
07ba6af4 680 return dump_num_registers[3][preset-1];
0fea29c1 681 else if (CHIP_IS_E3B0(bp))
07ba6af4 682 return dump_num_registers[4][preset-1];
0fea29c1 683 else
07ba6af4
MS		 684 return 0;
685}
686
687static int __bnx2x_get_regs_len(struct bnx2x *bp)
688{
689 u32 preset_idx;
690 int regdump_len = 0;
691
692 /* Calculate the total preset regs length */
693 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
694 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
695
696 return regdump_len;
697}
698
699static int bnx2x_get_regs_len(struct net_device *dev)
700{
701 struct bnx2x *bp = netdev_priv(dev);
702 int regdump_len = 0;
703
75543741
YM		 704 if (IS_VF(bp))
705 return 0;
706
07ba6af4
MS		 707 regdump_len = __bnx2x_get_regs_len(bp);
708 regdump_len *= 4;
709 regdump_len += sizeof(struct dump_header);
710
711 return regdump_len;
0fea29c1
VZ		 712}
713
07ba6af4
MS		 714#define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
715#define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
716#define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
717#define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
718#define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
719
720#define IS_REG_IN_PRESET(presets, idx) \
721 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
722
0fea29c1 723/******* Paged registers info selectors ********/
1191cb83 724static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
0fea29c1
VZ		 725{
726 if (CHIP_IS_E2(bp))
727 return page_vals_e2;
728 else if (CHIP_IS_E3(bp))
729 return page_vals_e3;
730 else
731 return NULL;
732}
733
1191cb83 734static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
0fea29c1
VZ		 735{
736 if (CHIP_IS_E2(bp))
737 return PAGE_MODE_VALUES_E2;
738 else if (CHIP_IS_E3(bp))
739 return PAGE_MODE_VALUES_E3;
740 else
741 return 0;
742}
743
1191cb83 744static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
0fea29c1
VZ		 745{
746 if (CHIP_IS_E2(bp))
747 return page_write_regs_e2;
748 else if (CHIP_IS_E3(bp))
749 return page_write_regs_e3;
750 else
751 return NULL;
752}
753
1191cb83 754static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
0fea29c1
VZ		 755{
756 if (CHIP_IS_E2(bp))
757 return PAGE_WRITE_REGS_E2;
758 else if (CHIP_IS_E3(bp))
759 return PAGE_WRITE_REGS_E3;
760 else
761 return 0;
762}
763
1191cb83 764static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
0fea29c1
VZ		 765{
766 if (CHIP_IS_E2(bp))
767 return page_read_regs_e2;
768 else if (CHIP_IS_E3(bp))
769 return page_read_regs_e3;
770 else
771 return NULL;
772}
773
1191cb83 774static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
0fea29c1
VZ		 775{
776 if (CHIP_IS_E2(bp))
777 return PAGE_READ_REGS_E2;
778 else if (CHIP_IS_E3(bp))
779 return PAGE_READ_REGS_E3;
780 else
781 return 0;
782}
783
07ba6af4
MS		 784static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
785 const struct reg_addr *reg_info)
0fea29c1 786{
07ba6af4
MS		 787 if (CHIP_IS_E1(bp))
788 return IS_E1_REG(reg_info->chips);
789 else if (CHIP_IS_E1H(bp))
790 return IS_E1H_REG(reg_info->chips);
791 else if (CHIP_IS_E2(bp))
792 return IS_E2_REG(reg_info->chips);
793 else if (CHIP_IS_E3A0(bp))
794 return IS_E3A0_REG(reg_info->chips);
795 else if (CHIP_IS_E3B0(bp))
796 return IS_E3B0_REG(reg_info->chips);
797 else
798 return false;
0fea29c1 799}
de0c62db 800
07ba6af4
MS		 801static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
802 const struct wreg_addr *wreg_info)
803{
804 if (CHIP_IS_E1(bp))
805 return IS_E1_REG(wreg_info->chips);
806 else if (CHIP_IS_E1H(bp))
807 return IS_E1H_REG(wreg_info->chips);
808 else if (CHIP_IS_E2(bp))
809 return IS_E2_REG(wreg_info->chips);
810 else if (CHIP_IS_E3A0(bp))
811 return IS_E3A0_REG(wreg_info->chips);
812 else if (CHIP_IS_E3B0(bp))
813 return IS_E3B0_REG(wreg_info->chips);
814 else
815 return false;
de0c62db
DK		 816}
817
0fea29c1
VZ		 818/**
819 * bnx2x_read_pages_regs - read "paged" registers
820 *
821 * @bp device handle
822 * @p output buffer
823 *
2de67439
YM		 824 * Reads "paged" memories: memories that may only be read by first writing to a
825 * specific address ("write address") and then reading from a specific address
826 * ("read address"). There may be more than one write address per "page" and
827 * more than one read address per write address.
0fea29c1 828 */
07ba6af4 829static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
f2e0899f
DK		 830{
831 u32 i, j, k, n;
07ba6af4 832
0fea29c1
VZ		 833 /* addresses of the paged registers */
834 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
835 /* number of paged registers */
836 int num_pages = __bnx2x_get_page_reg_num(bp);
837 /* write addresses */
838 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
839 /* number of write addresses */
840 int write_num = __bnx2x_get_page_write_num(bp);
841 /* read addresses info */
842 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
843 /* number of read addresses */
844 int read_num = __bnx2x_get_page_read_num(bp);
07ba6af4 845 u32 addr, size;
0fea29c1
VZ		 846
847 for (i = 0; i < num_pages; i++) {
848 for (j = 0; j < write_num; j++) {
849 REG_WR(bp, write_addr[j], page_addr[i]);
07ba6af4
MS		 850
851 for (k = 0; k < read_num; k++) {
852 if (IS_REG_IN_PRESET(read_addr[k].presets,
853 preset)) {
854 size = read_addr[k].size;
855 for (n = 0; n < size; n++) {
856 addr = read_addr[k].addr + n*4;
857 *p++ = REG_RD(bp, addr);
858 }
859 }
860 }
f2e0899f
DK		 861 }
862 }
863}
864
07ba6af4 865static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
0fea29c1 866{
07ba6af4
MS		 867 u32 i, j, addr;
868 const struct wreg_addr *wreg_addr_p = NULL;
869
870 if (CHIP_IS_E1(bp))
871 wreg_addr_p = &wreg_addr_e1;
872 else if (CHIP_IS_E1H(bp))
873 wreg_addr_p = &wreg_addr_e1h;
874 else if (CHIP_IS_E2(bp))
875 wreg_addr_p = &wreg_addr_e2;
876 else if (CHIP_IS_E3A0(bp))
877 wreg_addr_p = &wreg_addr_e3;
878 else if (CHIP_IS_E3B0(bp))
879 wreg_addr_p = &wreg_addr_e3b0;
880
881 /* Read the idle_chk registers */
882 for (i = 0; i < IDLE_REGS_COUNT; i++) {
883 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
884 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
885 for (j = 0; j < idle_reg_addrs[i].size; j++)
886 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
887 }
888 }
0fea29c1
VZ		 889
890 /* Read the regular registers */
07ba6af4
MS		 891 for (i = 0; i < REGS_COUNT; i++) {
892 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
893 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
0fea29c1
VZ		 894 for (j = 0; j < reg_addrs[i].size; j++)
895 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
07ba6af4
MS		 896 }
897 }
898
899 /* Read the CAM registers */
900 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
901 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
902 for (i = 0; i < wreg_addr_p->size; i++) {
903 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
904
905 /* In case of wreg_addr register, read additional
906 registers from read_regs array
907 */
908 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
909 addr = *(wreg_addr_p->read_regs);
910 *p++ = REG_RD(bp, addr + j*4);
911 }
912 }
913 }
914
915 /* Paged registers are supported in E2 & E3 only */
916 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
16a5fd92 917 /* Read "paged" registers */
07ba6af4
MS		 918 bnx2x_read_pages_regs(bp, p, preset);
919 }
920
921 return 0;
922}
923
924static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
925{
926 u32 preset_idx;
0fea29c1 927
07ba6af4
MS		 928 /* Read all registers, by reading all preset registers */
929 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
930 /* Skip presets with IOR */
931 if ((preset_idx == 2) ||
932 (preset_idx == 5) ||
933 (preset_idx == 8) ||
934 (preset_idx == 11))
935 continue;
936 __bnx2x_get_preset_regs(bp, p, preset_idx);
937 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
938 }
0fea29c1
VZ		 939}
940
de0c62db
DK		 941static void bnx2x_get_regs(struct net_device *dev,
942 struct ethtool_regs *regs, void *_p)
943{
0fea29c1 944 u32 *p = _p;
de0c62db 945 struct bnx2x *bp = netdev_priv(dev);
07ba6af4 946 struct dump_header dump_hdr = {0};
de0c62db 947
07ba6af4 948 regs->version = 2;
de0c62db
DK		 949 memset(p, 0, regs->len);
950
951 if (!netif_running(bp->dev))
952 return;
953
4a33bc03
VZ		 954 /* Disable parity attentions as long as following dump may
955 * cause false alarms by reading never written registers. We
956 * will re-enable parity attentions right after the dump.
957 */
07ba6af4 958
4a33bc03
VZ		 959 bnx2x_disable_blocks_parity(bp);
960
07ba6af4
MS		 961 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
962 dump_hdr.preset = DUMP_ALL_PRESETS;
963 dump_hdr.version = BNX2X_DUMP_VERSION;
964
965 /* dump_meta_data presents OR of CHIP and PATH. */
966 if (CHIP_IS_E1(bp)) {
967 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
968 } else if (CHIP_IS_E1H(bp)) {
969 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
970 } else if (CHIP_IS_E2(bp)) {
971 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
972 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
973 } else if (CHIP_IS_E3A0(bp)) {
974 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
975 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
976 } else if (CHIP_IS_E3B0(bp)) {
977 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
978 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
979 }
980
981 memcpy(p, &dump_hdr, sizeof(struct dump_header));
982 p += dump_hdr.header_size + 1;
de0c62db 983
0fea29c1
VZ		 984 /* Actually read the registers */
985 __bnx2x_get_regs(bp, p);
986
4293b9f5 987 /* Re-enable parity attentions */
07ba6af4
MS		 988 bnx2x_clear_blocks_parity(bp);
989 bnx2x_enable_blocks_parity(bp);
07ba6af4
MS		 990}
991
992static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
993{
994 struct bnx2x *bp = netdev_priv(dev);
995 int regdump_len = 0;
996
997 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
998 regdump_len *= 4;
999 regdump_len += sizeof(struct dump_header);
1000
1001 return regdump_len;
1002}
1003
1004static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1005{
1006 struct bnx2x *bp = netdev_priv(dev);
1007
1008 /* Use the ethtool_dump "flag" field as the dump preset index */
5bb680d6
MS		 1009 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1010 return -EINVAL;
1011
07ba6af4
MS		 1012 bp->dump_preset_idx = val->flag;
1013 return 0;
1014}
1015
1016static int bnx2x_get_dump_flag(struct net_device *dev,
1017 struct ethtool_dump *dump)
1018{
1019 struct bnx2x *bp = netdev_priv(dev);
1020
8cc2d927
MS		 1021 dump->version = BNX2X_DUMP_VERSION;
1022 dump->flag = bp->dump_preset_idx;
07ba6af4
MS		 1023 /* Calculate the requested preset idx length */
1024 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1025 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1026 bp->dump_preset_idx, dump->len);
07ba6af4
MS		 1027 return 0;
1028}
1029
1030static int bnx2x_get_dump_data(struct net_device *dev,
1031 struct ethtool_dump *dump,
1032 void *buffer)
1033{
1034 u32 *p = buffer;
1035 struct bnx2x *bp = netdev_priv(dev);
1036 struct dump_header dump_hdr = {0};
1037
07ba6af4
MS		 1038 /* Disable parity attentions as long as following dump may
1039 * cause false alarms by reading never written registers. We
1040 * will re-enable parity attentions right after the dump.
1041 */
1042
07ba6af4
MS		 1043 bnx2x_disable_blocks_parity(bp);
1044
07ba6af4
MS		 1045 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1046 dump_hdr.preset = bp->dump_preset_idx;
1047 dump_hdr.version = BNX2X_DUMP_VERSION;
1048
1049 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1050
1051 /* dump_meta_data presents OR of CHIP and PATH. */
1052 if (CHIP_IS_E1(bp)) {
1053 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1054 } else if (CHIP_IS_E1H(bp)) {
1055 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1056 } else if (CHIP_IS_E2(bp)) {
1057 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1058 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1059 } else if (CHIP_IS_E3A0(bp)) {
1060 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1061 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1062 } else if (CHIP_IS_E3B0(bp)) {
1063 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1064 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1065 }
1066
1067 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1068 p += dump_hdr.header_size + 1;
1069
1070 /* Actually read the registers */
1071 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1072
4293b9f5 1073 /* Re-enable parity attentions */
07ba6af4
MS		 1074 bnx2x_clear_blocks_parity(bp);
1075 bnx2x_enable_blocks_parity(bp);
1076
07ba6af4 1077 return 0;
de0c62db
DK		 1078}
1079
de0c62db
DK		 1080static void bnx2x_get_drvinfo(struct net_device *dev,
1081 struct ethtool_drvinfo *info)
1082{
1083 struct bnx2x *bp = netdev_priv(dev);
de0c62db 1084
68aad78c
RJ		 1085 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1086 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db 1087
8ca5e17e
AE		 1088 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1089
68aad78c 1090 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db 1091 info->n_stats = BNX2X_NUM_STATS;
cf2c1df6 1092 info->testinfo_len = BNX2X_NUM_TESTS(bp);
de0c62db
DK		 1093 info->eedump_len = bp->common.flash_size;
1094 info->regdump_len = bnx2x_get_regs_len(dev);
1095}
1096
1097static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1098{
1099 struct bnx2x *bp = netdev_priv(dev);
1100
1101 if (bp->flags & NO_WOL_FLAG) {
1102 wol->supported = 0;
1103 wol->wolopts = 0;
1104 } else {
1105 wol->supported = WAKE_MAGIC;
1106 if (bp->wol)
1107 wol->wolopts = WAKE_MAGIC;
1108 else
1109 wol->wolopts = 0;
1110 }
1111 memset(&wol->sopass, 0, sizeof(wol->sopass));
1112}
1113
1114static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1115{
1116 struct bnx2x *bp = netdev_priv(dev);
1117
51c1a580 1118 if (wol->wolopts & ~WAKE_MAGIC) {
2de67439 1119 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
de0c62db 1120 return -EINVAL;
51c1a580 1121 }
de0c62db
DK		 1122
1123 if (wol->wolopts & WAKE_MAGIC) {
51c1a580 1124 if (bp->flags & NO_WOL_FLAG) {
2de67439 1125 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
de0c62db 1126 return -EINVAL;
51c1a580 1127 }
de0c62db
DK		 1128 bp->wol = 1;
1129 } else
1130 bp->wol = 0;
1131
1132 return 0;
1133}
1134
1135static u32 bnx2x_get_msglevel(struct net_device *dev)
1136{
1137 struct bnx2x *bp = netdev_priv(dev);
1138
1139 return bp->msg_enable;
1140}
1141
1142static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1143{
1144 struct bnx2x *bp = netdev_priv(dev);
1145
7a25cc73
DK		 1146 if (capable(CAP_NET_ADMIN)) {
1147 /* dump MCP trace */
ad5afc89 1148 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
7a25cc73 1149 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 1150 bp->msg_enable = level;
7a25cc73 1151 }
de0c62db
DK		 1152}
1153
1154static int bnx2x_nway_reset(struct net_device *dev)
1155{
1156 struct bnx2x *bp = netdev_priv(dev);
1157
1158 if (!bp->port.pmf)
1159 return 0;
1160
1161 if (netif_running(dev)) {
1162 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 1163 bnx2x_force_link_reset(bp);
de0c62db
DK		 1164 bnx2x_link_set(bp);
1165 }
1166
1167 return 0;
1168}
1169
1170static u32 bnx2x_get_link(struct net_device *dev)
1171{
1172 struct bnx2x *bp = netdev_priv(dev);
1173
f2e0899f 1174 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 1175 return 0;
1176
6495d15a
DK		 1177 if (IS_VF(bp))
1178 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1179 &bp->vf_link_vars.link_report_flags);
1180
de0c62db
DK		 1181 return bp->link_vars.link_up;
1182}
1183
1184static int bnx2x_get_eeprom_len(struct net_device *dev)
1185{
1186 struct bnx2x *bp = netdev_priv(dev);
1187
1188 return bp->common.flash_size;
1189}
1190
16a5fd92
YM		 1191/* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1192 * had we done things the other way around, if two pfs from the same port would
f16da43b
AE		 1193 * attempt to access nvram at the same time, we could run into a scenario such
1194 * as:
1195 * pf A takes the port lock.
1196 * pf B succeeds in taking the same lock since they are from the same port.
1197 * pf A takes the per pf misc lock. Performs eeprom access.
1198 * pf A finishes. Unlocks the per pf misc lock.
1199 * Pf B takes the lock and proceeds to perform it's own access.
1200 * pf A unlocks the per port lock, while pf B is still working (!).
1201 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
2de67439 1202 * access corrupted by pf B)
f16da43b 1203 */
de0c62db
DK		 1204static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1205{
1206 int port = BP_PORT(bp);
1207 int count, i;
f16da43b
AE		 1208 u32 val;
1209
1210 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1211 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1212
1213 /* adjust timeout for emulation/FPGA */
754a2f52 1214 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1215 if (CHIP_REV_IS_SLOW(bp))
1216 count *= 100;
1217
1218 /* request access to nvram interface */
1219 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1220 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1221
1222 for (i = 0; i < count*10; i++) {
1223 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1224 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1225 break;
1226
1227 udelay(5);
1228 }
1229
1230 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
51c1a580
MS		 1231 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1232 "cannot get access to nvram interface\n");
de0c62db
DK		 1233 return -EBUSY;
1234 }
1235
1236 return 0;
1237}
1238
1239static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1240{
1241 int port = BP_PORT(bp);
1242 int count, i;
f16da43b 1243 u32 val;
de0c62db
DK		 1244
1245 /* adjust timeout for emulation/FPGA */
754a2f52 1246 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1247 if (CHIP_REV_IS_SLOW(bp))
1248 count *= 100;
1249
1250 /* relinquish nvram interface */
1251 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1252 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1253
1254 for (i = 0; i < count*10; i++) {
1255 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1256 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1257 break;
1258
1259 udelay(5);
1260 }
1261
1262 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
51c1a580
MS		 1263 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1264 "cannot free access to nvram interface\n");
de0c62db
DK		 1265 return -EBUSY;
1266 }
1267
f16da43b
AE		 1268 /* release HW lock: protect against other PFs in PF Direct Assignment */
1269 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1270 return 0;
1271}
1272
1273static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1274{
1275 u32 val;
1276
1277 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1278
1279 /* enable both bits, even on read */
1280 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1281 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1282 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1283}
1284
1285static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1286{
1287 u32 val;
1288
1289 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1290
1291 /* disable both bits, even after read */
1292 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1293 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1294 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1295}
1296
1297static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1298 u32 cmd_flags)
1299{
1300 int count, i, rc;
1301 u32 val;
1302
1303 /* build the command word */
1304 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1305
1306 /* need to clear DONE bit separately */
1307 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1308
1309 /* address of the NVRAM to read from */
1310 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1311 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1312
1313 /* issue a read command */
1314 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1315
1316 /* adjust timeout for emulation/FPGA */
754a2f52 1317 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1318 if (CHIP_REV_IS_SLOW(bp))
1319 count *= 100;
1320
1321 /* wait for completion */
1322 *ret_val = 0;
1323 rc = -EBUSY;
1324 for (i = 0; i < count; i++) {
1325 udelay(5);
1326 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1327
1328 if (val & MCPR_NVM_COMMAND_DONE) {
1329 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1330 /* we read nvram data in cpu order
1331 * but ethtool sees it as an array of bytes
07ba6af4
MS		 1332 * converting to big-endian will do the work
1333 */
de0c62db
DK		 1334 *ret_val = cpu_to_be32(val);
1335 rc = 0;
1336 break;
1337 }
1338 }
51c1a580
MS		 1339 if (rc == -EBUSY)
1340 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1341 "nvram read timeout expired\n");
de0c62db
DK		 1342 return rc;
1343}
1344
1345static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1346 int buf_size)
1347{
1348 int rc;
1349 u32 cmd_flags;
1350 __be32 val;
1351
1352 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1353 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1354 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1355 offset, buf_size);
1356 return -EINVAL;
1357 }
1358
1359 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1360 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1361 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1362 offset, buf_size, bp->common.flash_size);
1363 return -EINVAL;
1364 }
1365
1366 /* request access to nvram interface */
1367 rc = bnx2x_acquire_nvram_lock(bp);
1368 if (rc)
1369 return rc;
1370
1371 /* enable access to nvram interface */
1372 bnx2x_enable_nvram_access(bp);
1373
1374 /* read the first word(s) */
1375 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1376 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1377 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1378 memcpy(ret_buf, &val, 4);
1379
1380 /* advance to the next dword */
1381 offset += sizeof(u32);
1382 ret_buf += sizeof(u32);
1383 buf_size -= sizeof(u32);
1384 cmd_flags = 0;
1385 }
1386
1387 if (rc == 0) {
1388 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1389 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1390 memcpy(ret_buf, &val, 4);
1391 }
1392
1393 /* disable access to nvram interface */
1394 bnx2x_disable_nvram_access(bp);
1395 bnx2x_release_nvram_lock(bp);
1396
1397 return rc;
1398}
1399
85640952
DK		 1400static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1401 int buf_size)
1402{
1403 int rc;
1404
1405 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1406
1407 if (!rc) {
1408 __be32 *be = (__be32 *)buf;
1409
1410 while ((buf_size -= 4) >= 0)
1411 *buf++ = be32_to_cpu(*be++);
1412 }
1413
1414 return rc;
1415}
1416
3fb43eb2
YM		 1417static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1418{
1419 int rc = 1;
1420 u16 pm = 0;
1421 struct net_device *dev = pci_get_drvdata(bp->pdev);
1422
29ed74c3 1423 if (bp->pdev->pm_cap)
3fb43eb2 1424 rc = pci_read_config_word(bp->pdev,
29ed74c3 1425 bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
3fb43eb2 1426
829a5071 1427 if ((rc && !netif_running(dev)) ||
c957d09f 1428 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
3fb43eb2
YM		 1429 return false;
1430
1431 return true;
1432}
1433
de0c62db
DK		 1434static int bnx2x_get_eeprom(struct net_device *dev,
1435 struct ethtool_eeprom *eeprom, u8 *eebuf)
1436{
1437 struct bnx2x *bp = netdev_priv(dev);
de0c62db 1438
3fb43eb2 1439 if (!bnx2x_is_nvm_accessible(bp)) {
51c1a580
MS		 1440 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1441 "cannot access eeprom when the interface is down\n");
de0c62db 1442 return -EAGAIN;
51c1a580 1443 }
de0c62db 1444
51c1a580 1445 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1446 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1447 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1448 eeprom->len, eeprom->len);
1449
1450 /* parameters already validated in ethtool_get_eeprom */
1451
f1691dc6 1452 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
de0c62db
DK		 1453}
1454
24ea818e
YM		 1455static int bnx2x_get_module_eeprom(struct net_device *dev,
1456 struct ethtool_eeprom *ee,
1457 u8 *data)
1458{
1459 struct bnx2x *bp = netdev_priv(dev);
669d6996 1460 int rc = -EINVAL, phy_idx;
24ea818e 1461 u8 *user_data = data;
669d6996 1462 unsigned int start_addr = ee->offset, xfer_size = 0;
24ea818e 1463
3fb43eb2 1464 if (!bnx2x_is_nvm_accessible(bp)) {
24ea818e
YM		 1465 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1466 "cannot access eeprom when the interface is down\n");
1467 return -EAGAIN;
1468 }
1469
1470 phy_idx = bnx2x_get_cur_phy_idx(bp);
669d6996
YR		 1471
1472 /* Read A0 section */
1473 if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1474 /* Limit transfer size to the A0 section boundary */
1475 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1476 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1477 else
1478 xfer_size = ee->len;
1479 bnx2x_acquire_phy_lock(bp);
24ea818e
YM		 1480 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1481 &bp->link_params,
669d6996
YR		 1482 I2C_DEV_ADDR_A0,
1483 start_addr,
24ea818e
YM		 1484 xfer_size,
1485 user_data);
669d6996
YR		 1486 bnx2x_release_phy_lock(bp);
1487 if (rc) {
1488 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1489
1490 return -EINVAL;
1491 }
24ea818e 1492 user_data += xfer_size;
669d6996 1493 start_addr += xfer_size;
24ea818e
YM		 1494 }
1495
669d6996
YR		 1496 /* Read A2 section */
1497 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1498 (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1499 xfer_size = ee->len - xfer_size;
1500 /* Limit transfer size to the A2 section boundary */
1501 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1502 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1503 start_addr -= ETH_MODULE_SFF_8079_LEN;
1504 bnx2x_acquire_phy_lock(bp);
1505 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1506 &bp->link_params,
1507 I2C_DEV_ADDR_A2,
1508 start_addr,
1509 xfer_size,
1510 user_data);
1511 bnx2x_release_phy_lock(bp);
1512 if (rc) {
1513 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1514 return -EINVAL;
1515 }
1516 }
24ea818e
YM		 1517 return rc;
1518}
1519
1520static int bnx2x_get_module_info(struct net_device *dev,
1521 struct ethtool_modinfo *modinfo)
1522{
1523 struct bnx2x *bp = netdev_priv(dev);
669d6996
YR		 1524 int phy_idx, rc;
1525 u8 sff8472_comp, diag_type;
1526
3fb43eb2 1527 if (!bnx2x_is_nvm_accessible(bp)) {
669d6996 1528 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
24ea818e
YM		 1529 "cannot access eeprom when the interface is down\n");
1530 return -EAGAIN;
1531 }
24ea818e 1532 phy_idx = bnx2x_get_cur_phy_idx(bp);
669d6996
YR		 1533 bnx2x_acquire_phy_lock(bp);
1534 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1535 &bp->link_params,
1536 I2C_DEV_ADDR_A0,
1537 SFP_EEPROM_SFF_8472_COMP_ADDR,
1538 SFP_EEPROM_SFF_8472_COMP_SIZE,
1539 &sff8472_comp);
1540 bnx2x_release_phy_lock(bp);
1541 if (rc) {
1542 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1543 return -EINVAL;
1544 }
1545
1546 bnx2x_acquire_phy_lock(bp);
1547 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1548 &bp->link_params,
1549 I2C_DEV_ADDR_A0,
1550 SFP_EEPROM_DIAG_TYPE_ADDR,
1551 SFP_EEPROM_DIAG_TYPE_SIZE,
1552 &diag_type);
1553 bnx2x_release_phy_lock(bp);
1554 if (rc) {
1555 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1556 return -EINVAL;
1557 }
1558
1559 if (!sff8472_comp ||
1560 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
24ea818e
YM		 1561 modinfo->type = ETH_MODULE_SFF_8079;
1562 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
669d6996
YR		 1563 } else {
1564 modinfo->type = ETH_MODULE_SFF_8472;
1565 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
24ea818e 1566 }
669d6996 1567 return 0;
24ea818e
YM		 1568}
1569
de0c62db
DK		 1570static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1571 u32 cmd_flags)
1572{
1573 int count, i, rc;
1574
1575 /* build the command word */
1576 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1577
1578 /* need to clear DONE bit separately */
1579 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1580
1581 /* write the data */
1582 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1583
1584 /* address of the NVRAM to write to */
1585 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1586 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1587
1588 /* issue the write command */
1589 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1590
1591 /* adjust timeout for emulation/FPGA */
754a2f52 1592 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1593 if (CHIP_REV_IS_SLOW(bp))
1594 count *= 100;
1595
1596 /* wait for completion */
1597 rc = -EBUSY;
1598 for (i = 0; i < count; i++) {
1599 udelay(5);
1600 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1601 if (val & MCPR_NVM_COMMAND_DONE) {
1602 rc = 0;
1603 break;
1604 }
1605 }
1606
51c1a580
MS		 1607 if (rc == -EBUSY)
1608 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1609 "nvram write timeout expired\n");
de0c62db
DK		 1610 return rc;
1611}
1612
1613#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1614
1615static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1616 int buf_size)
1617{
1618 int rc;
30c20b67
DK		 1619 u32 cmd_flags, align_offset, val;
1620 __be32 val_be;
de0c62db
DK		 1621
1622 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1623 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1624 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1625 offset, buf_size, bp->common.flash_size);
1626 return -EINVAL;
1627 }
1628
1629 /* request access to nvram interface */
1630 rc = bnx2x_acquire_nvram_lock(bp);
1631 if (rc)
1632 return rc;
1633
1634 /* enable access to nvram interface */
1635 bnx2x_enable_nvram_access(bp);
1636
1637 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1638 align_offset = (offset & ~0x03);
30c20b67 1639 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
de0c62db
DK		 1640
1641 if (rc == 0) {
de0c62db 1642 /* nvram data is returned as an array of bytes
07ba6af4
MS		 1643 * convert it back to cpu order
1644 */
30c20b67
DK		 1645 val = be32_to_cpu(val_be);
1646
c957d09f
YM		 1647 val &= ~le32_to_cpu((__force __le32)
1648 (0xff << BYTE_OFFSET(offset)));
1649 val |= le32_to_cpu((__force __le32)
1650 (*data_buf << BYTE_OFFSET(offset)));
de0c62db
DK		 1651
1652 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1653 cmd_flags);
1654 }
1655
1656 /* disable access to nvram interface */
1657 bnx2x_disable_nvram_access(bp);
1658 bnx2x_release_nvram_lock(bp);
1659
1660 return rc;
1661}
1662
1663static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1664 int buf_size)
1665{
1666 int rc;
1667 u32 cmd_flags;
1668 u32 val;
1669 u32 written_so_far;
1670
1671 if (buf_size == 1) /* ethtool */
1672 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1673
1674 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1675 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1676 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1677 offset, buf_size);
1678 return -EINVAL;
1679 }
1680
1681 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1682 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1683 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1684 offset, buf_size, bp->common.flash_size);
1685 return -EINVAL;
1686 }
1687
1688 /* request access to nvram interface */
1689 rc = bnx2x_acquire_nvram_lock(bp);
1690 if (rc)
1691 return rc;
1692
1693 /* enable access to nvram interface */
1694 bnx2x_enable_nvram_access(bp);
1695
1696 written_so_far = 0;
1697 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1698 while ((written_so_far < buf_size) && (rc == 0)) {
1699 if (written_so_far == (buf_size - sizeof(u32)))
1700 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1701 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1702 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1703 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1704 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1705
1706 memcpy(&val, data_buf, 4);
1707
68bf5a10
YM		 1708 /* Notice unlike bnx2x_nvram_read_dword() this will not
1709 * change val using be32_to_cpu(), which causes data to flip
1710 * if the eeprom is read and then written back. This is due
1711 * to tools utilizing this functionality that would break
1712 * if this would be resolved.
1713 */
de0c62db
DK		 1714 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1715
1716 /* advance to the next dword */
1717 offset += sizeof(u32);
1718 data_buf += sizeof(u32);
1719 written_so_far += sizeof(u32);
1720 cmd_flags = 0;
1721 }
1722
1723 /* disable access to nvram interface */
1724 bnx2x_disable_nvram_access(bp);
1725 bnx2x_release_nvram_lock(bp);
1726
1727 return rc;
1728}
1729
1730static int bnx2x_set_eeprom(struct net_device *dev,
1731 struct ethtool_eeprom *eeprom, u8 *eebuf)
1732{
1733 struct bnx2x *bp = netdev_priv(dev);
1734 int port = BP_PORT(bp);
1735 int rc = 0;
e10bc84d 1736 u32 ext_phy_config;
3fb43eb2
YM		 1737
1738 if (!bnx2x_is_nvm_accessible(bp)) {
51c1a580
MS		 1739 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1740 "cannot access eeprom when the interface is down\n");
de0c62db 1741 return -EAGAIN;
51c1a580 1742 }
de0c62db 1743
51c1a580 1744 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1745 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1746 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1747 eeprom->len, eeprom->len);
1748
1749 /* parameters already validated in ethtool_set_eeprom */
1750
1751 /* PHY eeprom can be accessed only by the PMF */
1752 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
51c1a580
MS		 1753 !bp->port.pmf) {
1754 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1755 "wrong magic or interface is not pmf\n");
de0c62db 1756 return -EINVAL;
51c1a580 1757 }
de0c62db 1758
e10bc84d
YR		 1759 ext_phy_config =
1760 SHMEM_RD(bp,
1761 dev_info.port_hw_config[port].external_phy_config);
1762
de0c62db
DK		 1763 if (eeprom->magic == 0x50485950) {
1764 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1765 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1766
1767 bnx2x_acquire_phy_lock(bp);
1768 rc |= bnx2x_link_reset(&bp->link_params,
1769 &bp->link_vars, 0);
e10bc84d 1770 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1771 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1772 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1773 MISC_REGISTERS_GPIO_HIGH, port);
1774 bnx2x_release_phy_lock(bp);
1775 bnx2x_link_report(bp);
1776
1777 } else if (eeprom->magic == 0x50485952) {
1778 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1779 if (bp->state == BNX2X_STATE_OPEN) {
1780 bnx2x_acquire_phy_lock(bp);
1781 rc |= bnx2x_link_reset(&bp->link_params,
1782 &bp->link_vars, 1);
1783
1784 rc |= bnx2x_phy_init(&bp->link_params,
1785 &bp->link_vars);
1786 bnx2x_release_phy_lock(bp);
1787 bnx2x_calc_fc_adv(bp);
1788 }
1789 } else if (eeprom->magic == 0x53985943) {
1790 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1791 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1792 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1793
1794 /* DSP Remove Download Mode */
1795 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1796 MISC_REGISTERS_GPIO_LOW, port);
1797
1798 bnx2x_acquire_phy_lock(bp);
1799
e10bc84d
YR		 1800 bnx2x_sfx7101_sp_sw_reset(bp,
1801 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1802
1803 /* wait 0.5 sec to allow it to run */
1804 msleep(500);
1805 bnx2x_ext_phy_hw_reset(bp, port);
1806 msleep(500);
1807 bnx2x_release_phy_lock(bp);
1808 }
1809 } else
1810 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1811
1812 return rc;
1813}
f85582f8 1814
de0c62db
DK		 1815static int bnx2x_get_coalesce(struct net_device *dev,
1816 struct ethtool_coalesce *coal)
1817{
1818 struct bnx2x *bp = netdev_priv(dev);
1819
1820 memset(coal, 0, sizeof(struct ethtool_coalesce));
1821
1822 coal->rx_coalesce_usecs = bp->rx_ticks;
1823 coal->tx_coalesce_usecs = bp->tx_ticks;
1824
1825 return 0;
1826}
1827
1828static int bnx2x_set_coalesce(struct net_device *dev,
1829 struct ethtool_coalesce *coal)
1830{
1831 struct bnx2x *bp = netdev_priv(dev);
1832
1833 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1834 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1835 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1836
1837 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1838 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1839 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1840
1841 if (netif_running(dev))
1842 bnx2x_update_coalesce(bp);
1843
1844 return 0;
1845}
1846
1847static void bnx2x_get_ringparam(struct net_device *dev,
1848 struct ethtool_ringparam *ering)
1849{
1850 struct bnx2x *bp = netdev_priv(dev);
1851
1852 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1853
25141580
DK		 1854 if (bp->rx_ring_size)
1855 ering->rx_pending = bp->rx_ring_size;
1856 else
c2188952 1857 ering->rx_pending = MAX_RX_AVAIL;
25141580 1858
a3348722 1859 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
de0c62db
DK		 1860 ering->tx_pending = bp->tx_ring_size;
1861}
1862
1863static int bnx2x_set_ringparam(struct net_device *dev,
1864 struct ethtool_ringparam *ering)
1865{
1866 struct bnx2x *bp = netdev_priv(dev);
de0c62db 1867
04c46736
YM		 1868 DP(BNX2X_MSG_ETHTOOL,
1869 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1870 ering->rx_pending, ering->tx_pending);
1871
909d9faa
YM		 1872 if (pci_num_vf(bp->pdev)) {
1873 DP(BNX2X_MSG_IOV,
1874 "VFs are enabled, can not change ring parameters\n");
1875 return -EPERM;
1876 }
1877
de0c62db 1878 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 1879 DP(BNX2X_MSG_ETHTOOL,
1880 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 1881 return -EAGAIN;
1882 }
1883
1884 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1885 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1886 MIN_RX_SIZE_TPA)) ||
2e98ffc2 1887 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
51c1a580
MS		 1888 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1889 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db 1890 return -EINVAL;
51c1a580 1891 }
de0c62db
DK		 1892
1893 bp->rx_ring_size = ering->rx_pending;
1894 bp->tx_ring_size = ering->tx_pending;
1895
a9fccec7 1896 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1897}
1898
1899static void bnx2x_get_pauseparam(struct net_device *dev,
1900 struct ethtool_pauseparam *epause)
1901{
1902 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1903 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1904 int cfg_reg;
1905
a22f0788
YR		 1906 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1907 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1908
9e7e8399 1909 if (!epause->autoneg)
241fb5d2 1910 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
9e7e8399
MY		 1911 else
1912 cfg_reg = bp->link_params.req_fc_auto_adv;
1913
1914 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1915 BNX2X_FLOW_CTRL_RX);
9e7e8399 1916 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1917 BNX2X_FLOW_CTRL_TX);
1918
51c1a580 1919 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1920 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1921 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1922}
1923
1924static int bnx2x_set_pauseparam(struct net_device *dev,
1925 struct ethtool_pauseparam *epause)
1926{
1927 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1928 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1929 if (IS_MF(bp))
de0c62db
DK		 1930 return 0;
1931
51c1a580 1932 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1933 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1934 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1935
a22f0788 1936 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1937
1938 if (epause->rx_pause)
a22f0788 1939 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1940
1941 if (epause->tx_pause)
a22f0788 1942 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1943
a22f0788
YR		 1944 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1945 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1946
1947 if (epause->autoneg) {
a22f0788 1948 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 1949 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
de0c62db
DK		 1950 return -EINVAL;
1951 }
1952
a22f0788
YR		 1953 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1954 bp->link_params.req_flow_ctrl[cfg_idx] =
1955 BNX2X_FLOW_CTRL_AUTO;
1956 }
ba35a0fd 1957 bp->link_params.req_fc_auto_adv = 0;
5cd75f0c
YR		 1958 if (epause->rx_pause)
1959 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1960
1961 if (epause->tx_pause)
1962 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
ba35a0fd
YR		 1963
1964 if (!bp->link_params.req_fc_auto_adv)
1965 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1966 }
1967
51c1a580 1968 DP(BNX2X_MSG_ETHTOOL,
a22f0788 1969 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1970
1971 if (netif_running(dev)) {
1972 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
dc6a20aa 1973 bnx2x_force_link_reset(bp);
de0c62db
DK		 1974 bnx2x_link_set(bp);
1975 }
1976
1977 return 0;
1978}
1979
5889335c 1980static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
cf2c1df6
MS		 1981 "register_test (offline) ",
1982 "memory_test (offline) ",
1983 "int_loopback_test (offline)",
1984 "ext_loopback_test (offline)",
1985 "nvram_test (online) ",
1986 "interrupt_test (online) ",
1987 "link_test (online) "
de0c62db
DK		 1988};
1989
3521b419
YM		 1990enum {
1991 BNX2X_PRI_FLAG_ISCSI,
1992 BNX2X_PRI_FLAG_FCOE,
1993 BNX2X_PRI_FLAG_STORAGE,
1994 BNX2X_PRI_FLAG_LEN,
1995};
1996
1997static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
1998 "iSCSI offload support",
1999 "FCoE offload support",
2000 "Storage only interface"
2001};
2002
e9939c80
YM		 2003static u32 bnx2x_eee_to_adv(u32 eee_adv)
2004{
2005 u32 modes = 0;
2006
2007 if (eee_adv & SHMEM_EEE_100M_ADV)
2008 modes |= ADVERTISED_100baseT_Full;
2009 if (eee_adv & SHMEM_EEE_1G_ADV)
2010 modes |= ADVERTISED_1000baseT_Full;
2011 if (eee_adv & SHMEM_EEE_10G_ADV)
2012 modes |= ADVERTISED_10000baseT_Full;
2013
2014 return modes;
2015}
2016
2017static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2018{
2019 u32 eee_adv = 0;
2020 if (modes & ADVERTISED_100baseT_Full)
2021 eee_adv |= SHMEM_EEE_100M_ADV;
2022 if (modes & ADVERTISED_1000baseT_Full)
2023 eee_adv |= SHMEM_EEE_1G_ADV;
2024 if (modes & ADVERTISED_10000baseT_Full)
2025 eee_adv |= SHMEM_EEE_10G_ADV;
2026
2027 return eee_adv << shift;
2028}
2029
2030static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2031{
2032 struct bnx2x *bp = netdev_priv(dev);
2033 u32 eee_cfg;
2034
2035 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2036 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2037 return -EOPNOTSUPP;
2038 }
2039
08e9acc2 2040 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 2041
2042 edata->supported =
2043 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2044 SHMEM_EEE_SUPPORTED_SHIFT);
2045
2046 edata->advertised =
2047 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2048 SHMEM_EEE_ADV_STATUS_SHIFT);
2049 edata->lp_advertised =
2050 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2051 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2052
2053 /* SHMEM value is in 16u units --> Convert to 1u units. */
2054 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2055
2056 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
2057 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
2058 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2059
2060 return 0;
2061}
2062
2063static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2064{
2065 struct bnx2x *bp = netdev_priv(dev);
2066 u32 eee_cfg;
2067 u32 advertised;
2068
2069 if (IS_MF(bp))
2070 return 0;
2071
2072 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2073 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2074 return -EOPNOTSUPP;
2075 }
2076
08e9acc2 2077 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 2078
2079 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2080 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2081 return -EOPNOTSUPP;
2082 }
2083
2084 advertised = bnx2x_adv_to_eee(edata->advertised,
2085 SHMEM_EEE_ADV_STATUS_SHIFT);
2086 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2087 DP(BNX2X_MSG_ETHTOOL,
efc7ce03 2088 "Direct manipulation of EEE advertisement is not supported\n");
e9939c80
YM		 2089 return -EINVAL;
2090 }
2091
2092 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2093 DP(BNX2X_MSG_ETHTOOL,
2094 "Maximal Tx Lpi timer supported is %x(u)\n",
2095 EEE_MODE_TIMER_MASK);
2096 return -EINVAL;
2097 }
2098 if (edata->tx_lpi_enabled &&
2099 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2100 DP(BNX2X_MSG_ETHTOOL,
2101 "Minimal Tx Lpi timer supported is %d(u)\n",
2102 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2103 return -EINVAL;
2104 }
2105
2106 /* All is well; Apply changes*/
2107 if (edata->eee_enabled)
2108 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2109 else
2110 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2111
2112 if (edata->tx_lpi_enabled)
2113 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2114 else
2115 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2116
2117 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2118 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2119 EEE_MODE_TIMER_MASK) |
2120 EEE_MODE_OVERRIDE_NVRAM |
2121 EEE_MODE_OUTPUT_TIME;
2122
16a5fd92 2123 /* Restart link to propagate changes */
e9939c80
YM		 2124 if (netif_running(dev)) {
2125 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 2126 bnx2x_force_link_reset(bp);
e9939c80
YM		 2127 bnx2x_link_set(bp);
2128 }
2129
2130 return 0;
2131}
2132
619c5cb6
VZ		 2133enum {
2134 BNX2X_CHIP_E1_OFST = 0,
2135 BNX2X_CHIP_E1H_OFST,
2136 BNX2X_CHIP_E2_OFST,
2137 BNX2X_CHIP_E3_OFST,
2138 BNX2X_CHIP_E3B0_OFST,
2139 BNX2X_CHIP_MAX_OFST
2140};
2141
2142#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
2143#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
2144#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
2145#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
2146#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
2147
2148#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2149#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2150
de0c62db
DK		 2151static int bnx2x_test_registers(struct bnx2x *bp)
2152{
2153 int idx, i, rc = -ENODEV;
619c5cb6 2154 u32 wr_val = 0, hw;
de0c62db
DK		 2155 int port = BP_PORT(bp);
2156 static const struct {
619c5cb6 2157 u32 hw;
de0c62db
DK		 2158 u32 offset0;
2159 u32 offset1;
2160 u32 mask;
2161 } reg_tbl[] = {
619c5cb6
VZ		 2162/* 0 */ { BNX2X_CHIP_MASK_ALL,
2163 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2164 { BNX2X_CHIP_MASK_ALL,
2165 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2166 { BNX2X_CHIP_MASK_E1X,
2167 HC_REG_AGG_INT_0, 4, 0x000003ff },
2168 { BNX2X_CHIP_MASK_ALL,
2169 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2170 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2171 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2172 { BNX2X_CHIP_MASK_E3B0,
2173 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2174 { BNX2X_CHIP_MASK_ALL,
2175 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2176 { BNX2X_CHIP_MASK_ALL,
2177 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2178 { BNX2X_CHIP_MASK_ALL,
2179 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2180 { BNX2X_CHIP_MASK_ALL,
2181 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2182/* 10 */ { BNX2X_CHIP_MASK_ALL,
2183 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2184 { BNX2X_CHIP_MASK_ALL,
2185 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2186 { BNX2X_CHIP_MASK_ALL,
2187 QM_REG_CONNNUM_0, 4, 0x000fffff },
2188 { BNX2X_CHIP_MASK_ALL,
2189 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2190 { BNX2X_CHIP_MASK_ALL,
2191 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2192 { BNX2X_CHIP_MASK_ALL,
2193 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2194 { BNX2X_CHIP_MASK_ALL,
2195 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2196 { BNX2X_CHIP_MASK_ALL,
2197 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2198 { BNX2X_CHIP_MASK_ALL,
2199 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2200 { BNX2X_CHIP_MASK_ALL,
2201 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2202/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2203 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2204 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2205 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2206 { BNX2X_CHIP_MASK_ALL,
2207 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2208 { BNX2X_CHIP_MASK_ALL,
2209 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2210 { BNX2X_CHIP_MASK_ALL,
2211 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2212 { BNX2X_CHIP_MASK_ALL,
2213 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2214 { BNX2X_CHIP_MASK_ALL,
2215 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2216 { BNX2X_CHIP_MASK_ALL,
2217 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2218 { BNX2X_CHIP_MASK_ALL,
2219 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2220 { BNX2X_CHIP_MASK_ALL,
2221 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2222/* 30 */ { BNX2X_CHIP_MASK_ALL,
2223 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2224 { BNX2X_CHIP_MASK_ALL,
2225 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2226 { BNX2X_CHIP_MASK_ALL,
2227 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2228 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2229 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2230 { BNX2X_CHIP_MASK_ALL,
2231 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2232 { BNX2X_CHIP_MASK_ALL,
2233 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2234 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2235 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2236 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2237 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2238
2239 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 2240 };
2241
3fb43eb2 2242 if (!bnx2x_is_nvm_accessible(bp)) {
51c1a580
MS		 2243 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2244 "cannot access eeprom when the interface is down\n");
de0c62db 2245 return rc;
51c1a580 2246 }
de0c62db 2247
619c5cb6
VZ		 2248 if (CHIP_IS_E1(bp))
2249 hw = BNX2X_CHIP_MASK_E1;
2250 else if (CHIP_IS_E1H(bp))
2251 hw = BNX2X_CHIP_MASK_E1H;
2252 else if (CHIP_IS_E2(bp))
2253 hw = BNX2X_CHIP_MASK_E2;
2254 else if (CHIP_IS_E3B0(bp))
2255 hw = BNX2X_CHIP_MASK_E3B0;
2256 else /* e3 A0 */
2257 hw = BNX2X_CHIP_MASK_E3;
2258
de0c62db 2259 /* Repeat the test twice:
07ba6af4
MS		 2260 * First by writing 0x00000000, second by writing 0xffffffff
2261 */
de0c62db
DK		 2262 for (idx = 0; idx < 2; idx++) {
2263
2264 switch (idx) {
2265 case 0:
2266 wr_val = 0;
2267 break;
2268 case 1:
2269 wr_val = 0xffffffff;
2270 break;
2271 }
2272
2273 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2274 u32 offset, mask, save_val, val;
619c5cb6 2275 if (!(hw & reg_tbl[i].hw))
f2e0899f 2276 continue;
de0c62db
DK		 2277
2278 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2279 mask = reg_tbl[i].mask;
2280
2281 save_val = REG_RD(bp, offset);
2282
ec6ba945 2283 REG_WR(bp, offset, wr_val & mask);
f85582f8 2284
de0c62db
DK		 2285 val = REG_RD(bp, offset);
2286
2287 /* Restore the original register's value */
2288 REG_WR(bp, offset, save_val);
2289
2290 /* verify value is as expected */
2291 if ((val & mask) != (wr_val & mask)) {
51c1a580 2292 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 2293 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2294 offset, val, wr_val, mask);
2295 goto test_reg_exit;
2296 }
2297 }
2298 }
2299
2300 rc = 0;
2301
2302test_reg_exit:
2303 return rc;
2304}
2305
2306static int bnx2x_test_memory(struct bnx2x *bp)
2307{
2308 int i, j, rc = -ENODEV;
619c5cb6 2309 u32 val, index;
de0c62db
DK		 2310 static const struct {
2311 u32 offset;
2312 int size;
2313 } mem_tbl[] = {
2314 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2315 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2316 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2317 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2318 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2319 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2320 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2321
2322 { 0xffffffff, 0 }
2323 };
619c5cb6 2324
de0c62db
DK		 2325 static const struct {
2326 char *name;
2327 u32 offset;
619c5cb6 2328 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 2329 } prty_tbl[] = {
619c5cb6
VZ		 2330 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2331 {0x3ffc0, 0, 0, 0} },
2332 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2333 {0x2, 0x2, 0, 0} },
2334 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2335 {0, 0, 0, 0} },
2336 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2337 {0x3ffc0, 0, 0, 0} },
2338 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2339 {0x3ffc0, 0, 0, 0} },
2340 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2341 {0x3ffc1, 0, 0, 0} },
2342
2343 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 2344 };
2345
3fb43eb2 2346 if (!bnx2x_is_nvm_accessible(bp)) {
51c1a580
MS		 2347 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2348 "cannot access eeprom when the interface is down\n");
de0c62db 2349 return rc;
51c1a580 2350 }
de0c62db 2351
619c5cb6
VZ		 2352 if (CHIP_IS_E1(bp))
2353 index = BNX2X_CHIP_E1_OFST;
2354 else if (CHIP_IS_E1H(bp))
2355 index = BNX2X_CHIP_E1H_OFST;
2356 else if (CHIP_IS_E2(bp))
2357 index = BNX2X_CHIP_E2_OFST;
2358 else /* e3 */
2359 index = BNX2X_CHIP_E3_OFST;
2360
f2e0899f
DK		 2361 /* pre-Check the parity status */
2362 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2363 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 2364 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 2365 DP(BNX2X_MSG_ETHTOOL,
f2e0899f
DK		 2366 "%s is 0x%x\n", prty_tbl[i].name, val);
2367 goto test_mem_exit;
2368 }
2369 }
2370
de0c62db
DK		 2371 /* Go through all the memories */
2372 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2373 for (j = 0; j < mem_tbl[i].size; j++)
2374 REG_RD(bp, mem_tbl[i].offset + j*4);
2375
2376 /* Check the parity status */
2377 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2378 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 2379 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 2380 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 2381 "%s is 0x%x\n", prty_tbl[i].name, val);
2382 goto test_mem_exit;
2383 }
2384 }
2385
2386 rc = 0;
2387
2388test_mem_exit:
2389 return rc;
2390}
2391
a22f0788 2392static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 2393{
f2e0899f 2394 int cnt = 1400;
de0c62db 2395
619c5cb6 2396 if (link_up) {
a22f0788 2397 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 2398 msleep(20);
2399
2400 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
51c1a580 2401 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
8970b2e4
MS		 2402
2403 cnt = 1400;
2404 while (!bp->link_vars.link_up && cnt--)
2405 msleep(20);
2406
2407 if (cnt <= 0 && !bp->link_vars.link_up)
2408 DP(BNX2X_MSG_ETHTOOL,
2409 "Timeout waiting for link init\n");
619c5cb6 2410 }
de0c62db
DK		 2411}
2412
619c5cb6 2413static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 2414{
2415 unsigned int pkt_size, num_pkts, i;
2416 struct sk_buff *skb;
2417 unsigned char *packet;
2418 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2419 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
65565884 2420 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
de0c62db
DK		 2421 u16 tx_start_idx, tx_idx;
2422 u16 rx_start_idx, rx_idx;
b0700b1e 2423 u16 pkt_prod, bd_prod;
de0c62db
DK		 2424 struct sw_tx_bd *tx_buf;
2425 struct eth_tx_start_bd *tx_start_bd;
de0c62db
DK		 2426 dma_addr_t mapping;
2427 union eth_rx_cqe *cqe;
619c5cb6 2428 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 2429 struct sw_rx_bd *rx_buf;
2430 u16 len;
2431 int rc = -ENODEV;
e52fcb24 2432 u8 *data;
8970b2e4
MS		 2433 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2434 txdata->txq_index);
de0c62db
DK		 2435
2436 /* check the loopback mode */
2437 switch (loopback_mode) {
2438 case BNX2X_PHY_LOOPBACK:
8970b2e4
MS		 2439 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2440 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
de0c62db 2441 return -EINVAL;
8970b2e4 2442 }
de0c62db
DK		 2443 break;
2444 case BNX2X_MAC_LOOPBACK:
32911333
YR		 2445 if (CHIP_IS_E3(bp)) {
2446 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2447 if (bp->port.supported[cfg_idx] &
2448 (SUPPORTED_10000baseT_Full |
2449 SUPPORTED_20000baseMLD2_Full |
2450 SUPPORTED_20000baseKR2_Full))
2451 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2452 else
2453 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2454 } else
2455 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2456
de0c62db
DK		 2457 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2458 break;
8970b2e4
MS		 2459 case BNX2X_EXT_LOOPBACK:
2460 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2461 DP(BNX2X_MSG_ETHTOOL,
2462 "Can't configure external loopback\n");
2463 return -EINVAL;
2464 }
2465 break;
de0c62db 2466 default:
51c1a580 2467 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db
DK		 2468 return -EINVAL;
2469 }
2470
2471 /* prepare the loopback packet */
2472 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2473 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 2474 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db 2475 if (!skb) {
51c1a580 2476 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
de0c62db
DK		 2477 rc = -ENOMEM;
2478 goto test_loopback_exit;
2479 }
2480 packet = skb_put(skb, pkt_size);
2481 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
c7bf7169 2482 eth_zero_addr(packet + ETH_ALEN);
de0c62db
DK		 2483 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2484 for (i = ETH_HLEN; i < pkt_size; i++)
2485 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 2486 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2487 skb_headlen(skb), DMA_TO_DEVICE);
2488 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2489 rc = -ENOMEM;
2490 dev_kfree_skb(skb);
51c1a580 2491 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
619c5cb6
VZ		 2492 goto test_loopback_exit;
2493 }
de0c62db
DK		 2494
2495 /* send the loopback packet */
2496 num_pkts = 0;
6383c0b3 2497 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2498 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2499
73dbb5e1
DK		 2500 netdev_tx_sent_queue(txq, skb->len);
2501
6383c0b3
AE		 2502 pkt_prod = txdata->tx_pkt_prod++;
2503 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2504 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 2505 tx_buf->skb = skb;
2506 tx_buf->flags = 0;
2507
6383c0b3
AE		 2508 bd_prod = TX_BD(txdata->tx_bd_prod);
2509 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 2510 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2511 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2512 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2513 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 2514 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 2515 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 2516 SET_FLAG(tx_start_bd->general_data,
2517 ETH_TX_START_BD_HDR_NBDS,
2518 1);
96bed4b9
YM		 2519 SET_FLAG(tx_start_bd->general_data,
2520 ETH_TX_START_BD_PARSE_NBDS,
2521 0);
de0c62db
DK		 2522
2523 /* turn on parsing and get a BD */
2524 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 2525
96bed4b9
YM		 2526 if (CHIP_IS_E1x(bp)) {
2527 u16 global_data = 0;
2528 struct eth_tx_parse_bd_e1x *pbd_e1x =
2529 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2530 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2531 SET_FLAG(global_data,
2532 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2533 pbd_e1x->global_data = cpu_to_le16(global_data);
2534 } else {
2535 u32 parsing_data = 0;
2536 struct eth_tx_parse_bd_e2 *pbd_e2 =
2537 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2538 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2539 SET_FLAG(parsing_data,
2540 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2541 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2542 }
de0c62db
DK		 2543 wmb();
2544
6383c0b3 2545 txdata->tx_db.data.prod += 2;
de0c62db 2546 barrier();
6383c0b3 2547 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 2548
2549 mmiowb();
619c5cb6 2550 barrier();
de0c62db
DK		 2551
2552 num_pkts++;
6383c0b3 2553 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 2554
2555 udelay(100);
2556
6383c0b3 2557 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2558 if (tx_idx != tx_start_idx + num_pkts)
2559 goto test_loopback_exit;
2560
f2e0899f
DK		 2561 /* Unlike HC IGU won't generate an interrupt for status block
2562 * updates that have been performed while interrupts were
2563 * disabled.
2564 */
e1210d12
ED		 2565 if (bp->common.int_block == INT_BLOCK_IGU) {
2566 /* Disable local BHes to prevent a dead-lock situation between
2567 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2568 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2569 */
2570 local_bh_disable();
6383c0b3 2571 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 2572 local_bh_enable();
2573 }
f2e0899f 2574
de0c62db
DK		 2575 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2576 if (rx_idx != rx_start_idx + num_pkts)
2577 goto test_loopback_exit;
2578
b0700b1e 2579 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 2580 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 2581 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2582 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 2583 goto test_loopback_rx_exit;
2584
621b4d66 2585 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
de0c62db
DK		 2586 if (len != pkt_size)
2587 goto test_loopback_rx_exit;
2588
2589 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 2590 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 2591 dma_unmap_addr(rx_buf, mapping),
2592 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 2593 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 2594 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 2595 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 2596 goto test_loopback_rx_exit;
2597
2598 rc = 0;
2599
2600test_loopback_rx_exit:
2601
2602 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2603 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2604 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2605 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2606
2607 /* Update producers */
2608 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2609 fp_rx->rx_sge_prod);
2610
2611test_loopback_exit:
2612 bp->link_params.loopback_mode = LOOPBACK_NONE;
2613
2614 return rc;
2615}
2616
619c5cb6 2617static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 2618{
2619 int rc = 0, res;
2620
2621 if (BP_NOMCP(bp))
2622 return rc;
2623
2624 if (!netif_running(bp->dev))
2625 return BNX2X_LOOPBACK_FAILED;
2626
2627 bnx2x_netif_stop(bp, 1);
2628 bnx2x_acquire_phy_lock(bp);
2629
619c5cb6 2630 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db 2631 if (res) {
51c1a580 2632 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
de0c62db
DK		 2633 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2634 }
2635
619c5cb6 2636 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db 2637 if (res) {
51c1a580 2638 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
de0c62db
DK		 2639 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2640 }
2641
2642 bnx2x_release_phy_lock(bp);
2643 bnx2x_netif_start(bp);
2644
2645 return rc;
2646}
2647
8970b2e4
MS		 2648static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2649{
2650 int rc;
2651 u8 is_serdes =
2652 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2653
2654 if (BP_NOMCP(bp))
2655 return -ENODEV;
2656
2657 if (!netif_running(bp->dev))
2658 return BNX2X_EXT_LOOPBACK_FAILED;
2659
5d07d868 2660 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
8970b2e4
MS		 2661 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2662 if (rc) {
2663 DP(BNX2X_MSG_ETHTOOL,
2664 "Can't perform self-test, nic_load (for external lb) failed\n");
2665 return -ENODEV;
2666 }
2667 bnx2x_wait_for_link(bp, 1, is_serdes);
2668
2669 bnx2x_netif_stop(bp, 1);
2670
2671 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2672 if (rc)
2673 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2674
2675 bnx2x_netif_start(bp);
2676
2677 return rc;
2678}
2679
edb944d2
DK		 2680struct code_entry {
2681 u32 sram_start_addr;
2682 u32 code_attribute;
2683#define CODE_IMAGE_TYPE_MASK 0xf0800003
2684#define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003
2685#define CODE_IMAGE_LENGTH_MASK 0x007ffffc
2686#define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000
2687 u32 nvm_start_addr;
2688};
2689
2690#define CODE_ENTRY_MAX 16
2691#define CODE_ENTRY_EXTENDED_DIR_IDX 15
2692#define MAX_IMAGES_IN_EXTENDED_DIR 64
2693#define NVRAM_DIR_OFFSET 0x14
2694
2695#define EXTENDED_DIR_EXISTS(code) \
2696 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2697 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2698
de0c62db 2699#define CRC32_RESIDUAL 0xdebb20e3
edb944d2
DK		 2700#define CRC_BUFF_SIZE 256
2701
2702static int bnx2x_nvram_crc(struct bnx2x *bp,
2703 int offset,
2704 int size,
2705 u8 *buff)
2706{
2707 u32 crc = ~0;
2708 int rc = 0, done = 0;
2709
2710 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2711 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2712
2713 while (done < size) {
2714 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2715
2716 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2717
2718 if (rc)
2719 return rc;
2720
2721 crc = crc32_le(crc, buff, count);
2722 done += count;
2723 }
2724
2725 if (crc != CRC32_RESIDUAL)
2726 rc = -EINVAL;
2727
2728 return rc;
2729}
2730
2731static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2732 struct code_entry *entry,
2733 u8 *buff)
2734{
2735 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2736 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2737 int rc;
2738
2739 /* Zero-length images and AFEX profiles do not have CRC */
2740 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2741 return 0;
2742
2743 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2744 if (rc)
2745 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2746 "image %x has failed crc test (rc %d)\n", type, rc);
2747
2748 return rc;
2749}
2750
2751static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2752{
2753 int rc;
2754 struct code_entry entry;
2755
2756 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2757 if (rc)
2758 return rc;
2759
2760 return bnx2x_test_nvram_dir(bp, &entry, buff);
2761}
2762
2763static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2764{
2765 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2766 struct code_entry entry;
2767 int i;
2768
2769 rc = bnx2x_nvram_read32(bp,
2770 dir_offset +
2771 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2772 (u32 *)&entry, sizeof(entry));
2773 if (rc)
2774 return rc;
2775
2776 if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2777 return 0;
2778
2779 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2780 &cnt, sizeof(u32));
2781 if (rc)
2782 return rc;
2783
2784 dir_offset = entry.nvm_start_addr + 8;
2785
2786 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2787 rc = bnx2x_test_dir_entry(bp, dir_offset +
2788 sizeof(struct code_entry) * i,
2789 buff);
2790 if (rc)
2791 return rc;
2792 }
2793
2794 return 0;
2795}
2796
2797static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2798{
2799 u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2800 int i;
2801
2802 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2803
2804 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2805 rc = bnx2x_test_dir_entry(bp, dir_offset +
2806 sizeof(struct code_entry) * i,
2807 buff);
2808 if (rc)
2809 return rc;
2810 }
2811
2812 return bnx2x_test_nvram_ext_dirs(bp, buff);
2813}
2814
2815struct crc_pair {
2816 int offset;
2817 int size;
2818};
2819
2820static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2821 const struct crc_pair *nvram_tbl, u8 *buf)
2822{
2823 int i;
2824
2825 for (i = 0; nvram_tbl[i].size; i++) {
2826 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2827 nvram_tbl[i].size, buf);
2828 if (rc) {
2829 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2830 "nvram_tbl[%d] has failed crc test (rc %d)\n",
2831 i, rc);
2832 return rc;
2833 }
2834 }
2835
2836 return 0;
2837}
de0c62db
DK		 2838
2839static int bnx2x_test_nvram(struct bnx2x *bp)
2840{
edb944d2 2841 const struct crc_pair nvram_tbl[] = {
de0c62db
DK		 2842 { 0, 0x14 }, /* bootstrap */
2843 { 0x14, 0xec }, /* dir */
2844 { 0x100, 0x350 }, /* manuf_info */
2845 { 0x450, 0xf0 }, /* feature_info */
2846 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2847 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2848 { 0, 0 }
2849 };
edb944d2
DK		 2850 const struct crc_pair nvram_tbl2[] = {
2851 { 0x7e8, 0x350 }, /* manuf_info2 */
2852 { 0xb38, 0xf0 }, /* feature_info */
2853 { 0, 0 }
2854 };
2855
85640952 2856 u8 *buf;
edb944d2
DK		 2857 int rc;
2858 u32 magic;
de0c62db
DK		 2859
2860 if (BP_NOMCP(bp))
2861 return 0;
2862
edb944d2 2863 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
afa13b4b 2864 if (!buf) {
51c1a580 2865 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
afa13b4b
MY		 2866 rc = -ENOMEM;
2867 goto test_nvram_exit;
2868 }
afa13b4b 2869
85640952 2870 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
de0c62db 2871 if (rc) {
51c1a580
MS		 2872 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2873 "magic value read (rc %d)\n", rc);
de0c62db
DK		 2874 goto test_nvram_exit;
2875 }
2876
de0c62db 2877 if (magic != 0x669955aa) {
51c1a580
MS		 2878 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2879 "wrong magic value (0x%08x)\n", magic);
de0c62db
DK		 2880 rc = -ENODEV;
2881 goto test_nvram_exit;
2882 }
2883
edb944d2
DK		 2884 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2885 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2886 if (rc)
2887 goto test_nvram_exit;
de0c62db 2888
edb944d2
DK		 2889 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2890 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2891 SHARED_HW_CFG_HIDE_PORT1;
de0c62db 2892
edb944d2 2893 if (!hide) {
51c1a580 2894 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
edb944d2
DK		 2895 "Port 1 CRC test-set\n");
2896 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2897 if (rc)
2898 goto test_nvram_exit;
de0c62db
DK		 2899 }
2900 }
2901
edb944d2
DK		 2902 rc = bnx2x_test_nvram_dirs(bp, buf);
2903
de0c62db 2904test_nvram_exit:
afa13b4b 2905 kfree(buf);
de0c62db
DK		 2906 return rc;
2907}
2908
619c5cb6 2909/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2910static int bnx2x_test_intr(struct bnx2x *bp)
2911{
3b603066 2912 struct bnx2x_queue_state_params params = {NULL};
de0c62db 2913
51c1a580
MS		 2914 if (!netif_running(bp->dev)) {
2915 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2916 "cannot access eeprom when the interface is down\n");
de0c62db 2917 return -ENODEV;
51c1a580 2918 }
de0c62db 2919
15192a8c 2920 params.q_obj = &bp->sp_objs->q_obj;
619c5cb6 2921 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2922
619c5cb6
VZ		 2923 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2924
2925 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2926}
2927
2928static void bnx2x_self_test(struct net_device *dev,
2929 struct ethtool_test *etest, u64 *buf)
2930{
2931 struct bnx2x *bp = netdev_priv(dev);
a336ca7c
YR		 2932 u8 is_serdes, link_up;
2933 int rc, cnt = 0;
cf2c1df6 2934
909d9faa
YM		 2935 if (pci_num_vf(bp->pdev)) {
2936 DP(BNX2X_MSG_IOV,
2937 "VFs are enabled, can not perform self test\n");
2938 return;
2939 }
2940
de0c62db 2941 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 2942 netdev_err(bp->dev,
2943 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 2944 etest->flags |= ETH_TEST_FL_FAILED;
2945 return;
2946 }
2de67439 2947
8970b2e4
MS		 2948 DP(BNX2X_MSG_ETHTOOL,
2949 "Self-test command parameters: offline = %d, external_lb = %d\n",
2950 (etest->flags & ETH_TEST_FL_OFFLINE),
2951 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
de0c62db 2952
cf2c1df6 2953 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
de0c62db 2954
bd8e012b
YM		 2955 if (bnx2x_test_nvram(bp) != 0) {
2956 if (!IS_MF(bp))
2957 buf[4] = 1;
2958 else
2959 buf[0] = 1;
2960 etest->flags |= ETH_TEST_FL_FAILED;
2961 }
2962
cf2c1df6 2963 if (!netif_running(dev)) {
bd8e012b 2964 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
de0c62db 2965 return;
cf2c1df6 2966 }
de0c62db 2967
a22f0788 2968 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
a336ca7c 2969 link_up = bp->link_vars.link_up;
cf2c1df6
MS		 2970 /* offline tests are not supported in MF mode */
2971 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
de0c62db
DK		 2972 int port = BP_PORT(bp);
2973 u32 val;
de0c62db
DK		 2974
2975 /* save current value of input enable for TX port IF */
2976 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2977 /* disable input for TX port IF */
2978 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2979
5d07d868 2980 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
cf2c1df6
MS		 2981 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2982 if (rc) {
2983 etest->flags |= ETH_TEST_FL_FAILED;
2984 DP(BNX2X_MSG_ETHTOOL,
2985 "Can't perform self-test, nic_load (for offline) failed\n");
2986 return;
2987 }
2988
de0c62db 2989 /* wait until link state is restored */
619c5cb6 2990 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2991
2992 if (bnx2x_test_registers(bp) != 0) {
2993 buf[0] = 1;
2994 etest->flags |= ETH_TEST_FL_FAILED;
2995 }
2996 if (bnx2x_test_memory(bp) != 0) {
2997 buf[1] = 1;
2998 etest->flags |= ETH_TEST_FL_FAILED;
2999 }
f85582f8 3000
8970b2e4 3001 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
de0c62db
DK		 3002 if (buf[2] != 0)
3003 etest->flags |= ETH_TEST_FL_FAILED;
3004
8970b2e4
MS		 3005 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3006 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
3007 if (buf[3] != 0)
3008 etest->flags |= ETH_TEST_FL_FAILED;
3009 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3010 }
3011
5d07d868 3012 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
de0c62db
DK		 3013
3014 /* restore input for TX port IF */
3015 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
cf2c1df6
MS		 3016 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3017 if (rc) {
3018 etest->flags |= ETH_TEST_FL_FAILED;
3019 DP(BNX2X_MSG_ETHTOOL,
3020 "Can't perform self-test, nic_load (for online) failed\n");
3021 return;
3022 }
de0c62db 3023 /* wait until link state is restored */
a22f0788 3024 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db 3025 }
bd8e012b 3026
de0c62db 3027 if (bnx2x_test_intr(bp) != 0) {
cf2c1df6
MS		 3028 if (!IS_MF(bp))
3029 buf[5] = 1;
3030 else
3031 buf[1] = 1;
de0c62db
DK		 3032 etest->flags |= ETH_TEST_FL_FAILED;
3033 }
633ac363 3034
a336ca7c
YR		 3035 if (link_up) {
3036 cnt = 100;
3037 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3038 msleep(20);
3039 }
3040
3041 if (!cnt) {
cf2c1df6
MS		 3042 if (!IS_MF(bp))
3043 buf[6] = 1;
3044 else
3045 buf[2] = 1;
633ac363
DK		 3046 etest->flags |= ETH_TEST_FL_FAILED;
3047 }
de0c62db
DK		 3048}
3049
de0c62db
DK		 3050#define IS_PORT_STAT(i) \
3051 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
3052#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
d8361051
YM		 3053#define HIDE_PORT_STAT(bp) \
3054 ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \
3055 IS_VF(bp))
de0c62db 3056
619c5cb6
VZ		 3057/* ethtool statistics are displayed for all regular ethernet queues and the
3058 * fcoe L2 queue if not disabled
3059 */
1191cb83 3060static int bnx2x_num_stat_queues(struct bnx2x *bp)
619c5cb6
VZ		 3061{
3062 return BNX2X_NUM_ETH_QUEUES(bp);
3063}
3064
de0c62db
DK		 3065static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3066{
3067 struct bnx2x *bp = netdev_priv(dev);
3521b419 3068 int i, num_strings = 0;
de0c62db
DK		 3069
3070 switch (stringset) {
3071 case ETH_SS_STATS:
3072 if (is_multi(bp)) {
3521b419
YM		 3073 num_strings = bnx2x_num_stat_queues(bp) *
3074 BNX2X_NUM_Q_STATS;
d5e83632 3075 } else
3521b419 3076 num_strings = 0;
d8361051 3077 if (HIDE_PORT_STAT(bp)) {
d5e83632
YM		 3078 for (i = 0; i < BNX2X_NUM_STATS; i++)
3079 if (IS_FUNC_STAT(i))
3521b419 3080 num_strings++;
d5e83632 3081 } else
3521b419 3082 num_strings += BNX2X_NUM_STATS;
d5e83632 3083
3521b419 3084 return num_strings;
de0c62db
DK		 3085
3086 case ETH_SS_TEST:
cf2c1df6 3087 return BNX2X_NUM_TESTS(bp);
de0c62db 3088
3521b419
YM		 3089 case ETH_SS_PRIV_FLAGS:
3090 return BNX2X_PRI_FLAG_LEN;
3091
de0c62db
DK		 3092 default:
3093 return -EINVAL;
3094 }
3095}
3096
3521b419
YM		 3097static u32 bnx2x_get_private_flags(struct net_device *dev)
3098{
3099 struct bnx2x *bp = netdev_priv(dev);
3100 u32 flags = 0;
3101
3102 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3103 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3104 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3105
3106 return flags;
3107}
3108
de0c62db
DK		 3109static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3110{
3111 struct bnx2x *bp = netdev_priv(dev);
5889335c 3112 int i, j, k, start;
ec6ba945 3113 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 3114
3115 switch (stringset) {
3116 case ETH_SS_STATS:
d5e83632 3117 k = 0;
de0c62db 3118 if (is_multi(bp)) {
619c5cb6 3119 for_each_eth_queue(bp, i) {
ec6ba945 3120 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 3121 sprintf(queue_name, "%d", i);
de0c62db 3122 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 3123 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3124 ETH_GSTRING_LEN,
3125 bnx2x_q_stats_arr[j].string,
3126 queue_name);
de0c62db
DK		 3127 k += BNX2X_NUM_Q_STATS;
3128 }
de0c62db 3129 }
d5e83632 3130
d5e83632 3131 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
d8361051 3132 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
d5e83632
YM		 3133 continue;
3134 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3135 bnx2x_stats_arr[i].string);
3136 j++;
3137 }
3138
de0c62db
DK		 3139 break;
3140
3141 case ETH_SS_TEST:
cf2c1df6
MS		 3142 /* First 4 tests cannot be done in MF mode */
3143 if (!IS_MF(bp))
3144 start = 0;
3145 else
3146 start = 4;
5889335c
MS		 3147 memcpy(buf, bnx2x_tests_str_arr + start,
3148 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3521b419
YM		 3149 break;
3150
3151 case ETH_SS_PRIV_FLAGS:
3152 memcpy(buf, bnx2x_private_arr,
3153 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3154 break;
de0c62db
DK		 3155 }
3156}
3157
3158static void bnx2x_get_ethtool_stats(struct net_device *dev,
3159 struct ethtool_stats *stats, u64 *buf)
3160{
3161 struct bnx2x *bp = netdev_priv(dev);
3162 u32 *hw_stats, *offset;
d5e83632 3163 int i, j, k = 0;
de0c62db
DK		 3164
3165 if (is_multi(bp)) {
619c5cb6 3166 for_each_eth_queue(bp, i) {
15192a8c 3167 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
de0c62db
DK		 3168 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3169 if (bnx2x_q_stats_arr[j].size == 0) {
3170 /* skip this counter */
3171 buf[k + j] = 0;
3172 continue;
3173 }
3174 offset = (hw_stats +
3175 bnx2x_q_stats_arr[j].offset);
3176 if (bnx2x_q_stats_arr[j].size == 4) {
3177 /* 4-byte counter */
3178 buf[k + j] = (u64) *offset;
3179 continue;
3180 }
3181 /* 8-byte counter */
3182 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3183 }
3184 k += BNX2X_NUM_Q_STATS;
3185 }
d5e83632
YM		 3186 }
3187
3188 hw_stats = (u32 *)&bp->eth_stats;
3189 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
d8361051 3190 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
d5e83632
YM		 3191 continue;
3192 if (bnx2x_stats_arr[i].size == 0) {
3193 /* skip this counter */
3194 buf[k + j] = 0;
3195 j++;
3196 continue;
de0c62db 3197 }
d5e83632
YM		 3198 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3199 if (bnx2x_stats_arr[i].size == 4) {
3200 /* 4-byte counter */
3201 buf[k + j] = (u64) *offset;
de0c62db 3202 j++;
d5e83632 3203 continue;
de0c62db 3204 }
d5e83632
YM		 3205 /* 8-byte counter */
3206 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3207 j++;
de0c62db
DK		 3208 }
3209}
3210
32d36134 3211static int bnx2x_set_phys_id(struct net_device *dev,
3212 enum ethtool_phys_id_state state)
de0c62db
DK		 3213{
3214 struct bnx2x *bp = netdev_priv(dev);
de0c62db 3215
3fb43eb2 3216 if (!bnx2x_is_nvm_accessible(bp)) {
51c1a580
MS		 3217 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3218 "cannot access eeprom when the interface is down\n");
32d36134 3219 return -EAGAIN;
51c1a580 3220 }
de0c62db 3221
32d36134 3222 switch (state) {
3223 case ETHTOOL_ID_ACTIVE:
fce55922 3224 return 1; /* cycle on/off once per second */
de0c62db 3225
32d36134 3226 case ETHTOOL_ID_ON:
8203c4b6 3227 bnx2x_acquire_phy_lock(bp);
32d36134 3228 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 3229 LED_MODE_ON, SPEED_1000);
8203c4b6 3230 bnx2x_release_phy_lock(bp);
32d36134 3231 break;
de0c62db 3232
32d36134 3233 case ETHTOOL_ID_OFF:
8203c4b6 3234 bnx2x_acquire_phy_lock(bp);
32d36134 3235 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 3236 LED_MODE_FRONT_PANEL_OFF, 0);
8203c4b6 3237 bnx2x_release_phy_lock(bp);
32d36134 3238 break;
3239
3240 case ETHTOOL_ID_INACTIVE:
8203c4b6 3241 bnx2x_acquire_phy_lock(bp);
e1943424
DM		 3242 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3243 LED_MODE_OPER,
3244 bp->link_vars.line_speed);
8203c4b6 3245 bnx2x_release_phy_lock(bp);
32d36134 3246 }
de0c62db
DK		 3247
3248 return 0;
3249}
3250
5d317c6a
MS		 3251static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3252{
5d317c6a
MS		 3253 switch (info->flow_type) {
3254 case TCP_V4_FLOW:
3255 case TCP_V6_FLOW:
3256 info->data = RXH_IP_SRC | RXH_IP_DST |
3257 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3258 break;
3259 case UDP_V4_FLOW:
3260 if (bp->rss_conf_obj.udp_rss_v4)
3261 info->data = RXH_IP_SRC | RXH_IP_DST |
3262 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3263 else
3264 info->data = RXH_IP_SRC | RXH_IP_DST;
3265 break;
3266 case UDP_V6_FLOW:
3267 if (bp->rss_conf_obj.udp_rss_v6)
3268 info->data = RXH_IP_SRC | RXH_IP_DST |
3269 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3270 else
3271 info->data = RXH_IP_SRC | RXH_IP_DST;
3272 break;
3273 case IPV4_FLOW:
3274 case IPV6_FLOW:
3275 info->data = RXH_IP_SRC | RXH_IP_DST;
3276 break;
3277 default:
3278 info->data = 0;
3279 break;
3280 }
3281
3282 return 0;
3283}
3284
ab532cf3 3285static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 3286 u32 *rules __always_unused)
ab532cf3
TH		 3287{
3288 struct bnx2x *bp = netdev_priv(dev);
3289
3290 switch (info->cmd) {
3291 case ETHTOOL_GRXRINGS:
3292 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3293 return 0;
5d317c6a
MS		 3294 case ETHTOOL_GRXFH:
3295 return bnx2x_get_rss_flags(bp, info);
3296 default:
3297 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3298 return -EOPNOTSUPP;
3299 }
3300}
3301
3302static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3303{
3304 int udp_rss_requested;
3305
3306 DP(BNX2X_MSG_ETHTOOL,
3307 "Set rss flags command parameters: flow type = %d, data = %llu\n",
3308 info->flow_type, info->data);
3309
3310 switch (info->flow_type) {
3311 case TCP_V4_FLOW:
3312 case TCP_V6_FLOW:
3313 /* For TCP only 4-tupple hash is supported */
3314 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3315 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3316 DP(BNX2X_MSG_ETHTOOL,
3317 "Command parameters not supported\n");
3318 return -EINVAL;
5d317c6a 3319 }
2de67439 3320 return 0;
5d317c6a
MS		 3321
3322 case UDP_V4_FLOW:
3323 case UDP_V6_FLOW:
3324 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3325 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2de67439 3326 RXH_L4_B_0_1 | RXH_L4_B_2_3))
5d317c6a
MS		 3327 udp_rss_requested = 1;
3328 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3329 udp_rss_requested = 0;
3330 else
3331 return -EINVAL;
3332 if ((info->flow_type == UDP_V4_FLOW) &&
3333 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3334 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3335 DP(BNX2X_MSG_ETHTOOL,
3336 "rss re-configured, UDP 4-tupple %s\n",
3337 udp_rss_requested ? "enabled" : "disabled");
60cad4e6 3338 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
5d317c6a
MS		 3339 } else if ((info->flow_type == UDP_V6_FLOW) &&
3340 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3341 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
5d317c6a
MS		 3342 DP(BNX2X_MSG_ETHTOOL,
3343 "rss re-configured, UDP 4-tupple %s\n",
3344 udp_rss_requested ? "enabled" : "disabled");
60cad4e6 3345 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
5d317c6a 3346 }
924d75ab
YM		 3347 return 0;
3348
5d317c6a
MS		 3349 case IPV4_FLOW:
3350 case IPV6_FLOW:
3351 /* For IP only 2-tupple hash is supported */
3352 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3353 DP(BNX2X_MSG_ETHTOOL,
3354 "Command parameters not supported\n");
3355 return -EINVAL;
5d317c6a 3356 }
924d75ab
YM		 3357 return 0;
3358
5d317c6a
MS		 3359 case SCTP_V4_FLOW:
3360 case AH_ESP_V4_FLOW:
3361 case AH_V4_FLOW:
3362 case ESP_V4_FLOW:
3363 case SCTP_V6_FLOW:
3364 case AH_ESP_V6_FLOW:
3365 case AH_V6_FLOW:
3366 case ESP_V6_FLOW:
3367 case IP_USER_FLOW:
3368 case ETHER_FLOW:
3369 /* RSS is not supported for these protocols */
3370 if (info->data) {
3371 DP(BNX2X_MSG_ETHTOOL,
3372 "Command parameters not supported\n");
3373 return -EINVAL;
5d317c6a 3374 }
924d75ab
YM		 3375 return 0;
3376
5d317c6a
MS		 3377 default:
3378 return -EINVAL;
3379 }
3380}
3381
3382static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3383{
3384 struct bnx2x *bp = netdev_priv(dev);
ab532cf3 3385
5d317c6a
MS		 3386 switch (info->cmd) {
3387 case ETHTOOL_SRXFH:
3388 return bnx2x_set_rss_flags(bp, info);
ab532cf3 3389 default:
51c1a580 3390 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
ab532cf3
TH		 3391 return -EOPNOTSUPP;
3392 }
3393}
3394
7850f63f
BH		 3395static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3396{
96305234 3397 return T_ETH_INDIRECTION_TABLE_SIZE;
7850f63f
BH		 3398}
3399
892311f6
EP		 3400static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3401 u8 *hfunc)
ab532cf3
TH		 3402{
3403 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 3404 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3405 size_t i;
ab532cf3 3406
892311f6
EP		 3407 if (hfunc)
3408 *hfunc = ETH_RSS_HASH_TOP;
3409 if (!indir)
3410 return 0;
3411
619c5cb6
VZ		 3412 /* Get the current configuration of the RSS indirection table */
3413 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3414
3415 /*
3416 * We can't use a memcpy() as an internal storage of an
3417 * indirection table is a u8 array while indir->ring_index
3418 * points to an array of u32.
3419 *
3420 * Indirection table contains the FW Client IDs, so we need to
3421 * align the returned table to the Client ID of the leading RSS
3422 * queue.
3423 */
7850f63f
BH		 3424 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3425 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 3426
ab532cf3
TH		 3427 return 0;
3428}
3429
fe62d001 3430static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
892311f6 3431 const u8 *key, const u8 hfunc)
ab532cf3
TH		 3432{
3433 struct bnx2x *bp = netdev_priv(dev);
3434 size_t i;
619c5cb6 3435
892311f6
EP		 3436 /* We require at least one supported parameter to be changed and no
3437 * change in any of the unsupported parameters
3438 */
3439 if (key ||
3440 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3441 return -EOPNOTSUPP;
3442
3443 if (!indir)
3444 return 0;
3445
619c5cb6 3446 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6 3447 /*
fe62d001 3448 * The same as in bnx2x_get_rxfh: we can't use a memcpy()
619c5cb6
VZ		 3449 * as an internal storage of an indirection table is a u8 array
3450 * while indir->ring_index points to an array of u32.
3451 *
3452 * Indirection table contains the FW Client IDs, so we need to
3453 * align the received table to the Client ID of the leading RSS
3454 * queue
3455 */
5d317c6a 3456 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 3457 }
ab532cf3 3458
5d317c6a 3459 return bnx2x_config_rss_eth(bp, false);
ab532cf3
TH		 3460}
3461
0e8d2ec5
MS		 3462/**
3463 * bnx2x_get_channels - gets the number of RSS queues.
3464 *
3465 * @dev: net device
3466 * @channels: returns the number of max / current queues
3467 */
3468static void bnx2x_get_channels(struct net_device *dev,
3469 struct ethtool_channels *channels)
3470{
3471 struct bnx2x *bp = netdev_priv(dev);
3472
3473 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3474 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3475}
3476
3477/**
3478 * bnx2x_change_num_queues - change the number of RSS queues.
3479 *
3480 * @bp: bnx2x private structure
3481 *
3482 * Re-configure interrupt mode to get the new number of MSI-X
3483 * vectors and re-add NAPI objects.
3484 */
3485static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3486{
0e8d2ec5 3487 bnx2x_disable_msi(bp);
55c11941
MS		 3488 bp->num_ethernet_queues = num_rss;
3489 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3490 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
0e8d2ec5 3491 bnx2x_set_int_mode(bp);
0e8d2ec5
MS		 3492}
3493
3494/**
3495 * bnx2x_set_channels - sets the number of RSS queues.
3496 *
3497 * @dev: net device
3498 * @channels: includes the number of queues requested
3499 */
3500static int bnx2x_set_channels(struct net_device *dev,
3501 struct ethtool_channels *channels)
3502{
3503 struct bnx2x *bp = netdev_priv(dev);
3504
0e8d2ec5
MS		 3505 DP(BNX2X_MSG_ETHTOOL,
3506 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3507 channels->rx_count, channels->tx_count, channels->other_count,
3508 channels->combined_count);
3509
909d9faa
YM		 3510 if (pci_num_vf(bp->pdev)) {
3511 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3512 return -EPERM;
3513 }
3514
0e8d2ec5
MS		 3515 /* We don't support separate rx / tx channels.
3516 * We don't allow setting 'other' channels.
3517 */
3518 if (channels->rx_count || channels->tx_count || channels->other_count
3519 || (channels->combined_count == 0) ||
3520 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3521 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3522 return -EINVAL;
3523 }
3524
3525 /* Check if there was a change in the active parameters */
3526 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3527 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3528 return 0;
3529 }
3530
3531 /* Set the requested number of queues in bp context.
3532 * Note that the actual number of queues created during load may be
3533 * less than requested if memory is low.
3534 */
3535 if (unlikely(!netif_running(dev))) {
3536 bnx2x_change_num_queues(bp, channels->combined_count);
3537 return 0;
3538 }
5d07d868 3539 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
0e8d2ec5
MS		 3540 bnx2x_change_num_queues(bp, channels->combined_count);
3541 return bnx2x_nic_load(bp, LOAD_NORMAL);
3542}
3543
eeed018c
MK		 3544static int bnx2x_get_ts_info(struct net_device *dev,
3545 struct ethtool_ts_info *info)
3546{
3547 struct bnx2x *bp = netdev_priv(dev);
3548
3549 if (bp->flags & PTP_SUPPORTED) {
3550 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3551 SOF_TIMESTAMPING_RX_SOFTWARE |
3552 SOF_TIMESTAMPING_SOFTWARE |
3553 SOF_TIMESTAMPING_TX_HARDWARE |
3554 SOF_TIMESTAMPING_RX_HARDWARE |
3555 SOF_TIMESTAMPING_RAW_HARDWARE;
3556
3557 if (bp->ptp_clock)
3558 info->phc_index = ptp_clock_index(bp->ptp_clock);
3559 else
3560 info->phc_index = -1;
3561
3562 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3563 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3564 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
3565 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
3566 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3567 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
3568 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
3569 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3570 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
3571 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
3572 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
3573 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
3574 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
3575
3576 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3577
3578 return 0;
3579 }
3580
3581 return ethtool_op_get_ts_info(dev, info);
3582}
3583
de0c62db
DK		 3584static const struct ethtool_ops bnx2x_ethtool_ops = {
3585 .get_settings = bnx2x_get_settings,
3586 .set_settings = bnx2x_set_settings,
3587 .get_drvinfo = bnx2x_get_drvinfo,
3588 .get_regs_len = bnx2x_get_regs_len,
3589 .get_regs = bnx2x_get_regs,
07ba6af4
MS		 3590 .get_dump_flag = bnx2x_get_dump_flag,
3591 .get_dump_data = bnx2x_get_dump_data,
3592 .set_dump = bnx2x_set_dump,
de0c62db
DK		 3593 .get_wol = bnx2x_get_wol,
3594 .set_wol = bnx2x_set_wol,
3595 .get_msglevel = bnx2x_get_msglevel,
3596 .set_msglevel = bnx2x_set_msglevel,
3597 .nway_reset = bnx2x_nway_reset,
3598 .get_link = bnx2x_get_link,
3599 .get_eeprom_len = bnx2x_get_eeprom_len,
3600 .get_eeprom = bnx2x_get_eeprom,
3601 .set_eeprom = bnx2x_set_eeprom,
3602 .get_coalesce = bnx2x_get_coalesce,
3603 .set_coalesce = bnx2x_set_coalesce,
3604 .get_ringparam = bnx2x_get_ringparam,
3605 .set_ringparam = bnx2x_set_ringparam,
3606 .get_pauseparam = bnx2x_get_pauseparam,
3607 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 3608 .self_test = bnx2x_self_test,
3609 .get_sset_count = bnx2x_get_sset_count,
3521b419 3610 .get_priv_flags = bnx2x_get_private_flags,
de0c62db 3611 .get_strings = bnx2x_get_strings,
32d36134 3612 .set_phys_id = bnx2x_set_phys_id,
de0c62db 3613 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 3614 .get_rxnfc = bnx2x_get_rxnfc,
5d317c6a 3615 .set_rxnfc = bnx2x_set_rxnfc,
7850f63f 3616 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
fe62d001
BH		 3617 .get_rxfh = bnx2x_get_rxfh,
3618 .set_rxfh = bnx2x_set_rxfh,
0e8d2ec5
MS		 3619 .get_channels = bnx2x_get_channels,
3620 .set_channels = bnx2x_set_channels,
24ea818e
YM		 3621 .get_module_info = bnx2x_get_module_info,
3622 .get_module_eeprom = bnx2x_get_module_eeprom,
e9939c80
YM		 3623 .get_eee = bnx2x_get_eee,
3624 .set_eee = bnx2x_set_eee,
eeed018c 3625 .get_ts_info = bnx2x_get_ts_info,
de0c62db
DK		 3626};
3627
005a07ba 3628static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
6495d15a 3629 .get_settings = bnx2x_get_vf_settings,
005a07ba
AE		 3630 .get_drvinfo = bnx2x_get_drvinfo,
3631 .get_msglevel = bnx2x_get_msglevel,
3632 .set_msglevel = bnx2x_set_msglevel,
3633 .get_link = bnx2x_get_link,
3634 .get_coalesce = bnx2x_get_coalesce,
3635 .get_ringparam = bnx2x_get_ringparam,
3636 .set_ringparam = bnx2x_set_ringparam,
3637 .get_sset_count = bnx2x_get_sset_count,
3638 .get_strings = bnx2x_get_strings,
3639 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3640 .get_rxnfc = bnx2x_get_rxnfc,
3641 .set_rxnfc = bnx2x_set_rxnfc,
3642 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
fe62d001
BH		 3643 .get_rxfh = bnx2x_get_rxfh,
3644 .set_rxfh = bnx2x_set_rxfh,
005a07ba
AE		 3645 .get_channels = bnx2x_get_channels,
3646 .set_channels = bnx2x_set_channels,
3647};
3648
3649void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
de0c62db 3650{
7ad24ea4
WK		 3651 netdev->ethtool_ops = (IS_PF(bp)) ?
3652 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
de0c62db 3653}
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