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a2fbb9ea ET |
1 | /* bnx2x_hsi.h: Broadcom Everest network driver. |
2 | * | |
85b26ea1 | 3 | * Copyright (c) 2007-2012 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | */ | |
523224a3 DK |
9 | #ifndef BNX2X_HSI_H |
10 | #define BNX2X_HSI_H | |
11 | ||
12 | #include "bnx2x_fw_defs.h" | |
2e499d3c | 13 | #include "bnx2x_mfw_req.h" |
a2fbb9ea | 14 | |
619c5cb6 | 15 | #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e |
2ba45142 | 16 | |
e2513065 MC |
17 | struct license_key { |
18 | u32 reserved[6]; | |
19 | ||
2ba45142 VZ |
20 | u32 max_iscsi_conn; |
21 | #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF | |
22 | #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 | |
23 | #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 | |
24 | #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 | |
e2513065 | 25 | |
2ba45142 | 26 | u32 reserved_a; |
e2513065 | 27 | |
2ba45142 VZ |
28 | u32 max_fcoe_conn; |
29 | #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF | |
30 | #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 | |
31 | #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 | |
32 | #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 | |
33 | ||
34 | u32 reserved_b[4]; | |
35 | }; | |
a2fbb9ea | 36 | |
a2fbb9ea | 37 | /**************************************************************************** |
619c5cb6 | 38 | * Shared HW configuration * |
a2fbb9ea | 39 | ****************************************************************************/ |
619c5cb6 VZ |
40 | #define PIN_CFG_NA 0x00000000 |
41 | #define PIN_CFG_GPIO0_P0 0x00000001 | |
42 | #define PIN_CFG_GPIO1_P0 0x00000002 | |
43 | #define PIN_CFG_GPIO2_P0 0x00000003 | |
44 | #define PIN_CFG_GPIO3_P0 0x00000004 | |
45 | #define PIN_CFG_GPIO0_P1 0x00000005 | |
46 | #define PIN_CFG_GPIO1_P1 0x00000006 | |
47 | #define PIN_CFG_GPIO2_P1 0x00000007 | |
48 | #define PIN_CFG_GPIO3_P1 0x00000008 | |
49 | #define PIN_CFG_EPIO0 0x00000009 | |
50 | #define PIN_CFG_EPIO1 0x0000000a | |
51 | #define PIN_CFG_EPIO2 0x0000000b | |
52 | #define PIN_CFG_EPIO3 0x0000000c | |
53 | #define PIN_CFG_EPIO4 0x0000000d | |
54 | #define PIN_CFG_EPIO5 0x0000000e | |
55 | #define PIN_CFG_EPIO6 0x0000000f | |
56 | #define PIN_CFG_EPIO7 0x00000010 | |
57 | #define PIN_CFG_EPIO8 0x00000011 | |
58 | #define PIN_CFG_EPIO9 0x00000012 | |
59 | #define PIN_CFG_EPIO10 0x00000013 | |
60 | #define PIN_CFG_EPIO11 0x00000014 | |
61 | #define PIN_CFG_EPIO12 0x00000015 | |
62 | #define PIN_CFG_EPIO13 0x00000016 | |
63 | #define PIN_CFG_EPIO14 0x00000017 | |
64 | #define PIN_CFG_EPIO15 0x00000018 | |
65 | #define PIN_CFG_EPIO16 0x00000019 | |
66 | #define PIN_CFG_EPIO17 0x0000001a | |
67 | #define PIN_CFG_EPIO18 0x0000001b | |
68 | #define PIN_CFG_EPIO19 0x0000001c | |
69 | #define PIN_CFG_EPIO20 0x0000001d | |
70 | #define PIN_CFG_EPIO21 0x0000001e | |
71 | #define PIN_CFG_EPIO22 0x0000001f | |
72 | #define PIN_CFG_EPIO23 0x00000020 | |
73 | #define PIN_CFG_EPIO24 0x00000021 | |
74 | #define PIN_CFG_EPIO25 0x00000022 | |
75 | #define PIN_CFG_EPIO26 0x00000023 | |
76 | #define PIN_CFG_EPIO27 0x00000024 | |
77 | #define PIN_CFG_EPIO28 0x00000025 | |
78 | #define PIN_CFG_EPIO29 0x00000026 | |
79 | #define PIN_CFG_EPIO30 0x00000027 | |
80 | #define PIN_CFG_EPIO31 0x00000028 | |
81 | ||
82 | /* EPIO definition */ | |
83 | #define EPIO_CFG_NA 0x00000000 | |
84 | #define EPIO_CFG_EPIO0 0x00000001 | |
85 | #define EPIO_CFG_EPIO1 0x00000002 | |
86 | #define EPIO_CFG_EPIO2 0x00000003 | |
87 | #define EPIO_CFG_EPIO3 0x00000004 | |
88 | #define EPIO_CFG_EPIO4 0x00000005 | |
89 | #define EPIO_CFG_EPIO5 0x00000006 | |
90 | #define EPIO_CFG_EPIO6 0x00000007 | |
91 | #define EPIO_CFG_EPIO7 0x00000008 | |
92 | #define EPIO_CFG_EPIO8 0x00000009 | |
93 | #define EPIO_CFG_EPIO9 0x0000000a | |
94 | #define EPIO_CFG_EPIO10 0x0000000b | |
95 | #define EPIO_CFG_EPIO11 0x0000000c | |
96 | #define EPIO_CFG_EPIO12 0x0000000d | |
97 | #define EPIO_CFG_EPIO13 0x0000000e | |
98 | #define EPIO_CFG_EPIO14 0x0000000f | |
99 | #define EPIO_CFG_EPIO15 0x00000010 | |
100 | #define EPIO_CFG_EPIO16 0x00000011 | |
101 | #define EPIO_CFG_EPIO17 0x00000012 | |
102 | #define EPIO_CFG_EPIO18 0x00000013 | |
103 | #define EPIO_CFG_EPIO19 0x00000014 | |
104 | #define EPIO_CFG_EPIO20 0x00000015 | |
105 | #define EPIO_CFG_EPIO21 0x00000016 | |
106 | #define EPIO_CFG_EPIO22 0x00000017 | |
107 | #define EPIO_CFG_EPIO23 0x00000018 | |
108 | #define EPIO_CFG_EPIO24 0x00000019 | |
109 | #define EPIO_CFG_EPIO25 0x0000001a | |
110 | #define EPIO_CFG_EPIO26 0x0000001b | |
111 | #define EPIO_CFG_EPIO27 0x0000001c | |
112 | #define EPIO_CFG_EPIO28 0x0000001d | |
113 | #define EPIO_CFG_EPIO29 0x0000001e | |
114 | #define EPIO_CFG_EPIO30 0x0000001f | |
115 | #define EPIO_CFG_EPIO31 0x00000020 | |
116 | ||
117 | ||
118 | struct shared_hw_cfg { /* NVRAM Offset */ | |
a2fbb9ea | 119 | /* Up to 16 bytes of NULL-terminated string */ |
619c5cb6 VZ |
120 | u8 part_num[16]; /* 0x104 */ |
121 | ||
122 | u32 config; /* 0x114 */ | |
123 | #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 | |
124 | #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 | |
125 | #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 | |
126 | #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 | |
127 | #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 | |
a2fbb9ea | 128 | |
619c5cb6 | 129 | #define SHARED_HW_CFG_PORT_SWAP 0x00000004 |
a2fbb9ea | 130 | |
619c5cb6 | 131 | #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 |
a2fbb9ea | 132 | |
619c5cb6 VZ |
133 | #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 |
134 | #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 | |
a2fbb9ea | 135 | |
619c5cb6 VZ |
136 | #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 |
137 | #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 | |
a2fbb9ea ET |
138 | /* Whatever MFW found in NVM |
139 | (if multiple found, priority order is: NC-SI, UMP, IPMI) */ | |
619c5cb6 VZ |
140 | #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 |
141 | #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 | |
142 | #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 | |
143 | #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 | |
a2fbb9ea ET |
144 | /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI |
145 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
619c5cb6 | 146 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 |
a2fbb9ea ET |
147 | /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI |
148 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
619c5cb6 | 149 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 |
a2fbb9ea ET |
150 | /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP |
151 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
619c5cb6 VZ |
152 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 |
153 | ||
154 | #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 | |
155 | #define SHARED_HW_CFG_LED_MODE_SHIFT 16 | |
156 | #define SHARED_HW_CFG_LED_MAC1 0x00000000 | |
157 | #define SHARED_HW_CFG_LED_PHY1 0x00010000 | |
158 | #define SHARED_HW_CFG_LED_PHY2 0x00020000 | |
159 | #define SHARED_HW_CFG_LED_PHY3 0x00030000 | |
160 | #define SHARED_HW_CFG_LED_MAC2 0x00040000 | |
161 | #define SHARED_HW_CFG_LED_PHY4 0x00050000 | |
162 | #define SHARED_HW_CFG_LED_PHY5 0x00060000 | |
163 | #define SHARED_HW_CFG_LED_PHY6 0x00070000 | |
164 | #define SHARED_HW_CFG_LED_MAC3 0x00080000 | |
165 | #define SHARED_HW_CFG_LED_PHY7 0x00090000 | |
166 | #define SHARED_HW_CFG_LED_PHY9 0x000a0000 | |
167 | #define SHARED_HW_CFG_LED_PHY11 0x000b0000 | |
168 | #define SHARED_HW_CFG_LED_MAC4 0x000c0000 | |
169 | #define SHARED_HW_CFG_LED_PHY8 0x000d0000 | |
170 | #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 | |
171 | ||
172 | ||
173 | #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 | |
174 | #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 | |
175 | #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 | |
176 | #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 | |
177 | #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 | |
178 | #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 | |
179 | #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 | |
180 | #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 | |
181 | ||
182 | #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 | |
183 | #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 | |
184 | #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 | |
185 | ||
186 | #define SHARED_HW_CFG_ATC_MASK 0x80000000 | |
187 | #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 | |
188 | #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 | |
189 | ||
190 | u32 config2; /* 0x118 */ | |
a2fbb9ea | 191 | /* one time auto detect grace period (in sec) */ |
619c5cb6 VZ |
192 | #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff |
193 | #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 | |
a2fbb9ea | 194 | |
619c5cb6 VZ |
195 | #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 |
196 | #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 | |
a2fbb9ea ET |
197 | |
198 | /* The default value for the core clock is 250MHz and it is | |
199 | achieved by setting the clock change to 4 */ | |
619c5cb6 VZ |
200 | #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 |
201 | #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 | |
a2fbb9ea | 202 | |
619c5cb6 VZ |
203 | #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 |
204 | #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 | |
205 | #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 | |
a2fbb9ea | 206 | |
619c5cb6 | 207 | #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 |
a2fbb9ea | 208 | |
619c5cb6 VZ |
209 | #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 |
210 | #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 | |
211 | #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 | |
212 | ||
213 | /* Output low when PERST is asserted */ | |
214 | #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 | |
215 | #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 | |
216 | #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 | |
a2fbb9ea | 217 | |
619c5cb6 VZ |
218 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 |
219 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 | |
220 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 | |
221 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 | |
222 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 | |
223 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 | |
224 | ||
225 | /* The fan failure mechanism is usually related to the PHY type | |
226 | since the power consumption of the board is determined by the PHY. | |
227 | Currently, fan is required for most designs with SFX7101, BCM8727 | |
228 | and BCM8481. If a fan is not required for a board which uses one | |
229 | of those PHYs, this field should be set to "Disabled". If a fan is | |
230 | required for a different PHY type, this option should be set to | |
231 | "Enabled". The fan failure indication is expected on SPIO5 */ | |
232 | #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 | |
233 | #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 | |
234 | #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 | |
235 | #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 | |
236 | #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 | |
237 | ||
238 | /* ASPM Power Management support */ | |
239 | #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 | |
240 | #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 | |
241 | #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 | |
242 | #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 | |
243 | #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 | |
244 | #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 | |
245 | ||
246 | /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register | |
247 | tl_control_0 (register 0x2800) */ | |
248 | #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 | |
249 | #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 | |
250 | #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 | |
251 | ||
252 | #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 | |
253 | #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 | |
254 | #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 | |
255 | ||
256 | #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 | |
257 | #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 | |
258 | #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 | |
259 | ||
260 | /* Set the MDC/MDIO access for the first external phy */ | |
261 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 | |
262 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 | |
263 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 | |
264 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 | |
265 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 | |
266 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 | |
267 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 | |
268 | ||
269 | /* Set the MDC/MDIO access for the second external phy */ | |
270 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 | |
271 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 | |
272 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 | |
273 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 | |
274 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 | |
275 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 | |
276 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 | |
277 | ||
278 | ||
279 | u32 power_dissipated; /* 0x11c */ | |
280 | #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 | |
281 | #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 | |
282 | #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 | |
283 | #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 | |
284 | #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 | |
285 | #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 | |
286 | ||
287 | #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 | |
288 | #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 | |
289 | ||
290 | u32 ump_nc_si_config; /* 0x120 */ | |
291 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 | |
292 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 | |
293 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 | |
294 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 | |
295 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 | |
296 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 | |
297 | ||
298 | #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 | |
299 | #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 | |
300 | ||
301 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 | |
302 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 | |
303 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 | |
304 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 | |
305 | ||
306 | u32 board; /* 0x124 */ | |
307 | #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F | |
308 | #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 | |
309 | #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 | |
310 | #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 | |
311 | /* Use the PIN_CFG_XXX defines on top */ | |
312 | #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 | |
313 | #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 | |
314 | ||
315 | #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 | |
316 | #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 | |
317 | ||
318 | #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 | |
319 | #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 | |
320 | ||
321 | u32 wc_lane_config; /* 0x128 */ | |
322 | #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF | |
323 | #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 | |
324 | #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b | |
325 | #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 | |
326 | #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b | |
327 | #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 | |
328 | #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF | |
329 | #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 | |
330 | #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 | |
331 | #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 | |
332 | ||
333 | /* TX lane Polarity swap */ | |
334 | #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 | |
335 | #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 | |
336 | #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 | |
337 | #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 | |
338 | /* TX lane Polarity swap */ | |
339 | #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 | |
340 | #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 | |
341 | #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 | |
342 | #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 | |
343 | ||
344 | /* Selects the port layout of the board */ | |
345 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 | |
346 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 | |
347 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 | |
348 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 | |
349 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 | |
350 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 | |
351 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 | |
352 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 | |
a2fbb9ea ET |
353 | }; |
354 | ||
f1410647 | 355 | |
a2fbb9ea | 356 | /**************************************************************************** |
619c5cb6 | 357 | * Port HW configuration * |
a2fbb9ea | 358 | ****************************************************************************/ |
619c5cb6 | 359 | struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ |
a2fbb9ea | 360 | |
a2fbb9ea | 361 | u32 pci_id; |
619c5cb6 VZ |
362 | #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 |
363 | #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff | |
a2fbb9ea ET |
364 | |
365 | u32 pci_sub_id; | |
619c5cb6 VZ |
366 | #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 |
367 | #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff | |
a2fbb9ea ET |
368 | |
369 | u32 power_dissipated; | |
619c5cb6 VZ |
370 | #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff |
371 | #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 | |
372 | #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 | |
373 | #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 | |
374 | #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 | |
375 | #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 | |
376 | #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 | |
377 | #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 | |
a2fbb9ea ET |
378 | |
379 | u32 power_consumed; | |
619c5cb6 VZ |
380 | #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff |
381 | #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 | |
382 | #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 | |
383 | #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 | |
384 | #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 | |
385 | #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 | |
386 | #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 | |
387 | #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 | |
a2fbb9ea ET |
388 | |
389 | u32 mac_upper; | |
619c5cb6 VZ |
390 | #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff |
391 | #define PORT_HW_CFG_UPPERMAC_SHIFT 0 | |
a2fbb9ea ET |
392 | u32 mac_lower; |
393 | ||
394 | u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ | |
395 | u32 iscsi_mac_lower; | |
396 | ||
397 | u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ | |
398 | u32 rdma_mac_lower; | |
399 | ||
400 | u32 serdes_config; | |
619c5cb6 VZ |
401 | #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff |
402 | #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 | |
403 | ||
404 | #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 | |
405 | #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 | |
406 | ||
407 | ||
408 | /* Default values: 2P-64, 4P-32 */ | |
409 | u32 pf_config; /* 0x158 */ | |
410 | #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F | |
411 | #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 | |
412 | ||
413 | /* Default values: 17 */ | |
414 | #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 | |
415 | #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 | |
416 | ||
417 | #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 | |
418 | #define PORT_HW_CFG_FLR_ENABLED 0x00010000 | |
419 | ||
420 | u32 vf_config; /* 0x15C */ | |
421 | #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F | |
422 | #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 | |
423 | ||
424 | #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 | |
425 | #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 | |
426 | ||
427 | u32 mf_pci_id; /* 0x160 */ | |
428 | #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF | |
429 | #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 | |
430 | ||
431 | /* Controls the TX laser of the SFP+ module */ | |
432 | u32 sfp_ctrl; /* 0x164 */ | |
433 | #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF | |
434 | #define PORT_HW_CFG_TX_LASER_SHIFT 0 | |
435 | #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 | |
436 | #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 | |
437 | #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 | |
438 | #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 | |
439 | #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 | |
440 | ||
441 | /* Controls the fault module LED of the SFP+ */ | |
442 | #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 | |
443 | #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 | |
444 | #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 | |
445 | #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 | |
446 | #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 | |
447 | #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 | |
448 | #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 | |
449 | ||
450 | /* The output pin TX_DIS that controls the TX laser of the SFP+ | |
451 | module. Use the PIN_CFG_XXX defines on top */ | |
452 | u32 e3_sfp_ctrl; /* 0x168 */ | |
453 | #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF | |
454 | #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 | |
455 | ||
456 | /* The output pin for SFPP_TYPE which turns on the Fault module LED */ | |
457 | #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 | |
458 | #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 | |
459 | ||
460 | /* The input pin MOD_ABS that indicates whether SFP+ module is | |
461 | present or not. Use the PIN_CFG_XXX defines on top */ | |
462 | #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 | |
463 | #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 | |
464 | ||
465 | /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ | |
466 | module. Use the PIN_CFG_XXX defines on top */ | |
467 | #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 | |
468 | #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 | |
469 | ||
470 | /* | |
471 | * The input pin which signals module transmit fault. Use the | |
472 | * PIN_CFG_XXX defines on top | |
473 | */ | |
474 | u32 e3_cmn_pin_cfg; /* 0x16C */ | |
475 | #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF | |
476 | #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 | |
477 | ||
478 | /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on | |
479 | top */ | |
480 | #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 | |
481 | #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 | |
482 | ||
483 | /* | |
484 | * The output pin which powers down the PHY. Use the PIN_CFG_XXX | |
485 | * defines on top | |
486 | */ | |
487 | #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 | |
488 | #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 | |
489 | ||
490 | /* The output pin values BSC_SEL which selects the I2C for this port | |
491 | in the I2C Mux */ | |
492 | #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 | |
493 | #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 | |
494 | ||
a8db5b4c YR |
495 | |
496 | /* | |
619c5cb6 VZ |
497 | * The input pin I_FAULT which indicate over-current has occurred. |
498 | * Use the PIN_CFG_XXX defines on top | |
a8db5b4c | 499 | */ |
619c5cb6 VZ |
500 | u32 e3_cmn_pin_cfg1; /* 0x170 */ |
501 | #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF | |
502 | #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 | |
503 | u32 reserved0[7]; /* 0x174 */ | |
504 | ||
505 | u32 aeu_int_mask; /* 0x190 */ | |
506 | ||
507 | u32 media_type; /* 0x194 */ | |
508 | #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF | |
509 | #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 | |
510 | ||
511 | #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 | |
512 | #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 | |
513 | ||
514 | #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 | |
515 | #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 | |
516 | ||
517 | /* 4 times 16 bits for all 4 lanes. In case external PHY is present | |
518 | (not direct mode), those values will not take effect on the 4 XGXS | |
519 | lanes. For some external PHYs (such as 8706 and 8726) the values | |
520 | will be used to configure the external PHY in those cases, not | |
521 | all 4 values are needed. */ | |
522 | u16 xgxs_config_rx[4]; /* 0x198 */ | |
523 | u16 xgxs_config_tx[4]; /* 0x1A0 */ | |
524 | ||
525 | /* For storing FCOE mac on shared memory */ | |
526 | u32 fcoe_fip_mac_upper; | |
527 | #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff | |
528 | #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 | |
529 | u32 fcoe_fip_mac_lower; | |
530 | ||
531 | u32 fcoe_wwn_port_name_upper; | |
532 | u32 fcoe_wwn_port_name_lower; | |
533 | ||
534 | u32 fcoe_wwn_node_name_upper; | |
535 | u32 fcoe_wwn_node_name_lower; | |
536 | ||
0520e63a YR |
537 | u32 Reserved1[49]; /* 0x1C0 */ |
538 | ||
539 | /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), | |
540 | 84833 only */ | |
541 | u32 xgbt_phy_cfg; /* 0x284 */ | |
542 | #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF | |
543 | #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 | |
619c5cb6 VZ |
544 | |
545 | u32 default_cfg; /* 0x288 */ | |
546 | #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 | |
547 | #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 | |
548 | #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 | |
549 | #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 | |
550 | #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 | |
551 | #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 | |
552 | ||
553 | #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C | |
554 | #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 | |
555 | #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 | |
556 | #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 | |
557 | #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 | |
558 | #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c | |
559 | ||
560 | #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 | |
561 | #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 | |
562 | #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 | |
563 | #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 | |
564 | #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 | |
565 | #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 | |
566 | ||
567 | #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 | |
568 | #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 | |
569 | #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 | |
570 | #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 | |
571 | #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 | |
572 | #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 | |
573 | ||
574 | /* When KR link is required to be set to force which is not | |
575 | KR-compliant, this parameter determine what is the trigger for it. | |
576 | When GPIO is selected, low input will force the speed. Currently | |
577 | default speed is 1G. In the future, it may be widen to select the | |
578 | forced speed in with another parameter. Note when force-1G is | |
579 | enabled, it override option 56: Link Speed option. */ | |
580 | #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 | |
581 | #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 | |
582 | #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 | |
583 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 | |
584 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 | |
585 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 | |
586 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 | |
587 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 | |
588 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 | |
589 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 | |
590 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 | |
591 | #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 | |
592 | /* Enable to determine with which GPIO to reset the external phy */ | |
593 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 | |
594 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 | |
595 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 | |
596 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 | |
597 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 | |
598 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 | |
599 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 | |
600 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 | |
601 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 | |
602 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 | |
603 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 | |
604 | ||
121839be | 605 | /* Enable BAM on KR */ |
619c5cb6 VZ |
606 | #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 |
607 | #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 | |
608 | #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 | |
609 | #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 | |
121839be | 610 | |
1bef68e3 | 611 | /* Enable Common Mode Sense */ |
619c5cb6 VZ |
612 | #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 |
613 | #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 | |
614 | #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 | |
615 | #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 | |
616 | ||
619c5cb6 VZ |
617 | /* Determine the Serdes electrical interface */ |
618 | #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 | |
619 | #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 | |
620 | #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 | |
621 | #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 | |
622 | #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 | |
623 | #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 | |
624 | #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 | |
625 | #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 | |
626 | ||
1bef68e3 | 627 | |
a22f0788 | 628 | u32 speed_capability_mask2; /* 0x28C */ |
619c5cb6 VZ |
629 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF |
630 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 | |
631 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 | |
632 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 | |
633 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 | |
634 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 | |
635 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 | |
636 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 | |
637 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 | |
638 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 | |
639 | ||
640 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 | |
641 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 | |
642 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 | |
643 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 | |
644 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 | |
645 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 | |
646 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 | |
647 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 | |
648 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 | |
649 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 | |
650 | ||
651 | ||
652 | /* In the case where two media types (e.g. copper and fiber) are | |
653 | present and electrically active at the same time, PHY Selection | |
654 | will determine which of the two PHYs will be designated as the | |
655 | Active PHY and used for a connection to the network. */ | |
656 | u32 multi_phy_config; /* 0x290 */ | |
657 | #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 | |
658 | #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 | |
659 | #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 | |
660 | #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 | |
661 | #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 | |
662 | #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 | |
663 | #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 | |
664 | ||
665 | /* When enabled, all second phy nvram parameters will be swapped | |
666 | with the first phy parameters */ | |
667 | #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 | |
668 | #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 | |
669 | #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 | |
670 | #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 | |
671 | ||
672 | ||
673 | /* Address of the second external phy */ | |
674 | u32 external_phy_config2; /* 0x294 */ | |
675 | #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF | |
676 | #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 | |
677 | ||
678 | /* The second XGXS external PHY type */ | |
679 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 | |
680 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 | |
681 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 | |
682 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 | |
683 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 | |
684 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 | |
685 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 | |
686 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 | |
687 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 | |
688 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 | |
689 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 | |
690 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 | |
691 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 | |
692 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 | |
693 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 | |
694 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 | |
52c4d6c4 | 695 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 |
619c5cb6 | 696 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 |
3756a89f | 697 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 |
619c5cb6 VZ |
698 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 |
699 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 | |
700 | ||
701 | ||
702 | /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as | |
703 | 8706, 8726 and 8727) not all 4 values are needed. */ | |
704 | u16 xgxs_config2_rx[4]; /* 0x296 */ | |
705 | u16 xgxs_config2_tx[4]; /* 0x2A0 */ | |
a2fbb9ea ET |
706 | |
707 | u32 lane_config; | |
619c5cb6 VZ |
708 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff |
709 | #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 | |
710 | /* AN and forced */ | |
711 | #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b | |
712 | /* forced only */ | |
713 | #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 | |
714 | /* forced only */ | |
715 | #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 | |
716 | /* forced only */ | |
717 | #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 | |
718 | #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff | |
719 | #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 | |
720 | #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 | |
721 | #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 | |
722 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 | |
723 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 | |
724 | ||
725 | /* Indicate whether to swap the external phy polarity */ | |
726 | #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 | |
727 | #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 | |
728 | #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 | |
729 | ||
a2fbb9ea ET |
730 | |
731 | u32 external_phy_config; | |
619c5cb6 VZ |
732 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff |
733 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 | |
734 | ||
735 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 | |
736 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 | |
737 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 | |
738 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 | |
739 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 | |
740 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 | |
741 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 | |
742 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 | |
743 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 | |
744 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 | |
745 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 | |
746 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 | |
747 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 | |
748 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 | |
749 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 | |
750 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 | |
52c4d6c4 | 751 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 |
619c5cb6 | 752 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 |
3756a89f | 753 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 |
619c5cb6 VZ |
754 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 |
755 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 | |
756 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 | |
757 | ||
758 | #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 | |
759 | #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 | |
760 | ||
761 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 | |
762 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 | |
763 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 | |
764 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 | |
765 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 | |
766 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 | |
a2fbb9ea ET |
767 | |
768 | u32 speed_capability_mask; | |
619c5cb6 VZ |
769 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff |
770 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 | |
771 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 | |
772 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 | |
773 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 | |
774 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 | |
775 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 | |
776 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 | |
777 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 | |
778 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 | |
779 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 | |
780 | ||
781 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 | |
782 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 | |
783 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 | |
784 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 | |
785 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 | |
786 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 | |
787 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 | |
788 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 | |
789 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 | |
790 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 | |
791 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 | |
792 | ||
793 | /* A place to hold the original MAC address as a backup */ | |
794 | u32 backup_mac_upper; /* 0x2B4 */ | |
795 | u32 backup_mac_lower; /* 0x2B8 */ | |
a2fbb9ea ET |
796 | |
797 | }; | |
798 | ||
f1410647 | 799 | |
a2fbb9ea | 800 | /**************************************************************************** |
619c5cb6 | 801 | * Shared Feature configuration * |
a2fbb9ea | 802 | ****************************************************************************/ |
619c5cb6 VZ |
803 | struct shared_feat_cfg { /* NVRAM Offset */ |
804 | ||
805 | u32 config; /* 0x450 */ | |
806 | #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 | |
807 | ||
808 | /* Use NVRAM values instead of HW default values */ | |
809 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ | |
810 | 0x00000002 | |
811 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ | |
812 | 0x00000000 | |
813 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ | |
814 | 0x00000002 | |
815 | ||
816 | #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 | |
817 | #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 | |
818 | #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 | |
f1410647 | 819 | |
619c5cb6 VZ |
820 | #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 |
821 | #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 | |
589abe3a | 822 | |
619c5cb6 VZ |
823 | /* Override the OTP back to single function mode. When using GPIO, |
824 | high means only SF, 0 is according to CLP configuration */ | |
825 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 | |
826 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 | |
827 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 | |
828 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 | |
829 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 | |
830 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 | |
a3348722 | 831 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 |
589abe3a | 832 | |
619c5cb6 VZ |
833 | /* The interval in seconds between sending LLDP packets. Set to zero |
834 | to disable the feature */ | |
835 | #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 | |
836 | #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 | |
837 | ||
838 | /* The assigned device type ID for LLDP usage */ | |
839 | #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 | |
840 | #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 | |
a2fbb9ea ET |
841 | |
842 | }; | |
843 | ||
844 | ||
845 | /**************************************************************************** | |
619c5cb6 | 846 | * Port Feature configuration * |
a2fbb9ea | 847 | ****************************************************************************/ |
619c5cb6 | 848 | struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ |
f1410647 | 849 | |
a2fbb9ea | 850 | u32 config; |
619c5cb6 VZ |
851 | #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f |
852 | #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 | |
853 | #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 | |
854 | #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 | |
855 | #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 | |
856 | #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 | |
857 | #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 | |
858 | #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 | |
859 | #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 | |
860 | #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 | |
861 | #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 | |
862 | #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 | |
863 | #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a | |
864 | #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b | |
865 | #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c | |
866 | #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d | |
867 | #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e | |
868 | #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f | |
869 | #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 | |
870 | #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 | |
871 | #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 | |
872 | #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 | |
873 | #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 | |
874 | #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 | |
875 | #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 | |
876 | #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 | |
877 | #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 | |
878 | #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 | |
879 | #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 | |
880 | #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 | |
881 | #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 | |
882 | #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 | |
883 | #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 | |
884 | #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 | |
885 | #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 | |
886 | #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 | |
887 | ||
888 | #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 | |
889 | #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 | |
890 | #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 | |
891 | ||
619c5cb6 VZ |
892 | #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 |
893 | #define PORT_FEATURE_EN_SIZE_SHIFT 24 | |
894 | #define PORT_FEATURE_WOL_ENABLED 0x01000000 | |
895 | #define PORT_FEATURE_MBA_ENABLED 0x02000000 | |
896 | #define PORT_FEATURE_MFW_ENABLED 0x04000000 | |
897 | ||
898 | /* Advertise expansion ROM even if MBA is disabled */ | |
899 | #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 | |
900 | #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 | |
901 | #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 | |
902 | ||
903 | /* Check the optic vendor via i2c against a list of approved modules | |
904 | in a separate nvram image */ | |
905 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 | |
906 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 | |
907 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ | |
908 | 0x00000000 | |
909 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ | |
910 | 0x20000000 | |
911 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 | |
912 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 | |
589abe3a | 913 | |
a2fbb9ea ET |
914 | u32 wol_config; |
915 | /* Default is used when driver sets to "auto" mode */ | |
619c5cb6 VZ |
916 | #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 |
917 | #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 | |
918 | #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 | |
919 | #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 | |
920 | #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 | |
921 | #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 | |
922 | #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 | |
923 | #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 | |
924 | #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 | |
a2fbb9ea ET |
925 | |
926 | u32 mba_config; | |
619c5cb6 VZ |
927 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 |
928 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 | |
929 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 | |
930 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 | |
931 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 | |
932 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 | |
933 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 | |
934 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 | |
935 | ||
936 | #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 | |
937 | #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 | |
938 | ||
939 | #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 | |
940 | #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 | |
941 | #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 | |
942 | #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 | |
943 | #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 | |
944 | #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 | |
945 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 | |
946 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 | |
947 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 | |
948 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 | |
949 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 | |
950 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 | |
951 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 | |
952 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 | |
953 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 | |
954 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 | |
955 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 | |
956 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 | |
957 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 | |
958 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 | |
959 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 | |
960 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 | |
961 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 | |
962 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 | |
963 | #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 | |
964 | #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 | |
965 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 | |
966 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 | |
967 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 | |
968 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 | |
969 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 | |
970 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 | |
971 | #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 | |
972 | #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 | |
973 | #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 | |
974 | #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 | |
975 | #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 | |
976 | #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 | |
977 | #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 | |
978 | #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 | |
979 | #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 | |
980 | #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 | |
981 | #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 | |
a2fbb9ea | 982 | u32 bmc_config; |
619c5cb6 VZ |
983 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 |
984 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 | |
985 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 | |
a2fbb9ea ET |
986 | |
987 | u32 mba_vlan_cfg; | |
619c5cb6 VZ |
988 | #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff |
989 | #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 | |
990 | #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 | |
a2fbb9ea ET |
991 | |
992 | u32 resource_cfg; | |
619c5cb6 VZ |
993 | #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 |
994 | #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 | |
995 | #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 | |
996 | #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 | |
997 | #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 | |
a2fbb9ea ET |
998 | |
999 | u32 smbus_config; | |
619c5cb6 VZ |
1000 | #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe |
1001 | #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 | |
1002 | ||
1003 | u32 vf_config; | |
1004 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f | |
1005 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 | |
1006 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 | |
1007 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 | |
1008 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 | |
1009 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 | |
1010 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 | |
1011 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 | |
1012 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 | |
1013 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 | |
1014 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 | |
1015 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 | |
1016 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a | |
1017 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b | |
1018 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c | |
1019 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d | |
1020 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e | |
1021 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f | |
a2fbb9ea ET |
1022 | |
1023 | u32 link_config; /* Used as HW defaults for the driver */ | |
619c5cb6 VZ |
1024 | #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 |
1025 | #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 | |
1026 | /* (forced) low speed switch (< 10G) */ | |
1027 | #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 | |
1028 | /* (forced) high speed switch (>= 10G) */ | |
1029 | #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 | |
1030 | #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 | |
1031 | #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 | |
1032 | ||
1033 | #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 | |
1034 | #define PORT_FEATURE_LINK_SPEED_SHIFT 16 | |
1035 | #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 | |
1036 | #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 | |
1037 | #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 | |
1038 | #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 | |
1039 | #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 | |
1040 | #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 | |
1041 | #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 | |
1042 | #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 | |
1043 | #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 | |
1044 | ||
1045 | #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 | |
1046 | #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 | |
1047 | #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 | |
1048 | #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 | |
1049 | #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 | |
1050 | #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 | |
1051 | #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 | |
a2fbb9ea ET |
1052 | |
1053 | /* The default for MCP link configuration, | |
619c5cb6 | 1054 | uses the same defines as link_config */ |
a2fbb9ea | 1055 | u32 mfw_wol_link_cfg; |
619c5cb6 | 1056 | |
a22f0788 | 1057 | /* The default for the driver of the second external phy, |
619c5cb6 VZ |
1058 | uses the same defines as link_config */ |
1059 | u32 link_config2; /* 0x47C */ | |
a2fbb9ea | 1060 | |
a22f0788 | 1061 | /* The default for MCP of the second external phy, |
619c5cb6 VZ |
1062 | uses the same defines as link_config */ |
1063 | u32 mfw_wol_link_cfg2; /* 0x480 */ | |
a22f0788 | 1064 | |
a2fbb9ea | 1065 | |
c8c60d88 YM |
1066 | /* EEE power saving mode */ |
1067 | u32 eee_power_mode; /* 0x484 */ | |
1068 | #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF | |
1069 | #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 | |
1070 | #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 | |
1071 | #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 | |
1072 | #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 | |
1073 | #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 | |
1074 | ||
1075 | ||
1076 | u32 Reserved2[16]; /* 0x488 */ | |
a2fbb9ea ET |
1077 | }; |
1078 | ||
1079 | ||
34f80b04 | 1080 | /**************************************************************************** |
619c5cb6 | 1081 | * Device Information * |
34f80b04 | 1082 | ****************************************************************************/ |
619c5cb6 | 1083 | struct shm_dev_info { /* size */ |
f1410647 | 1084 | |
34f80b04 | 1085 | u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ |
f1410647 | 1086 | |
619c5cb6 | 1087 | struct shared_hw_cfg shared_hw_config; /* 40 */ |
f1410647 | 1088 | |
619c5cb6 | 1089 | struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ |
f1410647 | 1090 | |
619c5cb6 | 1091 | struct shared_feat_cfg shared_feature_config; /* 4 */ |
f1410647 | 1092 | |
619c5cb6 | 1093 | struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ |
f1410647 ET |
1094 | |
1095 | }; | |
1096 | ||
1097 | ||
619c5cb6 VZ |
1098 | #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) |
1099 | #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." | |
1100 | #endif | |
f1410647 | 1101 | |
619c5cb6 VZ |
1102 | #define FUNC_0 0 |
1103 | #define FUNC_1 1 | |
1104 | #define FUNC_2 2 | |
1105 | #define FUNC_3 3 | |
1106 | #define FUNC_4 4 | |
1107 | #define FUNC_5 5 | |
1108 | #define FUNC_6 6 | |
1109 | #define FUNC_7 7 | |
1110 | #define E1_FUNC_MAX 2 | |
1111 | #define E1H_FUNC_MAX 8 | |
1112 | #define E2_FUNC_MAX 4 /* per path */ | |
1113 | ||
1114 | #define VN_0 0 | |
1115 | #define VN_1 1 | |
1116 | #define VN_2 2 | |
1117 | #define VN_3 3 | |
1118 | #define E1VN_MAX 1 | |
1119 | #define E1HVN_MAX 4 | |
1120 | ||
1121 | #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ | |
f1410647 ET |
1122 | /* This value (in milliseconds) determines the frequency of the driver |
1123 | * issuing the PULSE message code. The firmware monitors this periodic | |
1124 | * pulse to determine when to switch to an OS-absent mode. */ | |
619c5cb6 | 1125 | #define DRV_PULSE_PERIOD_MS 250 |
f1410647 ET |
1126 | |
1127 | /* This value (in milliseconds) determines how long the driver should | |
1128 | * wait for an acknowledgement from the firmware before timing out. Once | |
1129 | * the firmware has timed out, the driver will assume there is no firmware | |
1130 | * running and there won't be any firmware-driver synchronization during a | |
1131 | * driver reset. */ | |
619c5cb6 | 1132 | #define FW_ACK_TIME_OUT_MS 5000 |
f1410647 | 1133 | |
619c5cb6 | 1134 | #define FW_ACK_POLL_TIME_MS 1 |
f1410647 | 1135 | |
619c5cb6 | 1136 | #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) |
f1410647 | 1137 | |
de128804 DK |
1138 | #define MFW_TRACE_SIGNATURE 0x54524342 |
1139 | ||
a2fbb9ea | 1140 | /**************************************************************************** |
619c5cb6 | 1141 | * Driver <-> FW Mailbox * |
a2fbb9ea | 1142 | ****************************************************************************/ |
f1410647 | 1143 | struct drv_port_mb { |
a2fbb9ea | 1144 | |
f1410647 ET |
1145 | u32 link_status; |
1146 | /* Driver should update this field on any link change event */ | |
a2fbb9ea | 1147 | |
d0b8a6f9 | 1148 | #define LINK_STATUS_NONE (0<<0) |
619c5cb6 VZ |
1149 | #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 |
1150 | #define LINK_STATUS_LINK_UP 0x00000001 | |
1151 | #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E | |
1152 | #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) | |
1153 | #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) | |
1154 | #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) | |
1155 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) | |
1156 | #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) | |
1157 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) | |
1158 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) | |
1159 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) | |
1160 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) | |
1161 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) | |
1162 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) | |
1163 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) | |
1164 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) | |
1165 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) | |
1166 | #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) | |
1167 | #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) | |
1168 | ||
1169 | #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 | |
1170 | #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 | |
1171 | ||
1172 | #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 | |
1173 | #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 | |
1174 | #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 | |
1175 | ||
1176 | #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 | |
1177 | #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 | |
1178 | #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 | |
1179 | #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 | |
1180 | #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 | |
1181 | #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 | |
1182 | #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 | |
1183 | ||
1184 | #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 | |
1185 | #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 | |
1186 | ||
1187 | #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 | |
1188 | #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 | |
1189 | ||
1190 | #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 | |
1191 | #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) | |
1192 | #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) | |
1193 | #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) | |
1194 | #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) | |
1195 | ||
1196 | #define LINK_STATUS_SERDES_LINK 0x00100000 | |
1197 | ||
1198 | #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 | |
1199 | #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 | |
1200 | #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 | |
1201 | #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 | |
f1410647 | 1202 | |
b8d6d082 YR |
1203 | #define LINK_STATUS_PFC_ENABLED 0x20000000 |
1204 | ||
de6f3377 | 1205 | #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 |
d0b8a6f9 | 1206 | #define LINK_STATUS_SFP_TX_FAULT 0x80000000 |
de6f3377 | 1207 | |
34f80b04 EG |
1208 | u32 port_stx; |
1209 | ||
de832a55 EG |
1210 | u32 stat_nig_timer; |
1211 | ||
a35da8db EG |
1212 | /* MCP firmware does not use this field */ |
1213 | u32 ext_phy_fw_version; | |
f1410647 ET |
1214 | |
1215 | }; | |
1216 | ||
1217 | ||
1218 | struct drv_func_mb { | |
1219 | ||
1220 | u32 drv_mb_header; | |
619c5cb6 VZ |
1221 | #define DRV_MSG_CODE_MASK 0xffff0000 |
1222 | #define DRV_MSG_CODE_LOAD_REQ 0x10000000 | |
1223 | #define DRV_MSG_CODE_LOAD_DONE 0x11000000 | |
1224 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 | |
1225 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 | |
1226 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 | |
1227 | #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 | |
1228 | #define DRV_MSG_CODE_DCC_OK 0x30000000 | |
1229 | #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 | |
1230 | #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 | |
1231 | #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 | |
1232 | #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 | |
1233 | #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 | |
1234 | #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 | |
1235 | #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 | |
1236 | #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 | |
4d295db0 | 1237 | /* |
619c5cb6 VZ |
1238 | * The optic module verification command requires bootcode |
1239 | * v5.0.6 or later, te specific optic module verification command | |
1240 | * requires bootcode v5.2.12 or later | |
4d295db0 | 1241 | */ |
619c5cb6 VZ |
1242 | #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 |
1243 | #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 | |
1244 | #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 | |
1245 | #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 | |
a3348722 BW |
1246 | #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 |
1247 | #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 | |
85242eea | 1248 | #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 |
0e898dd7 | 1249 | #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 |
2e499d3c | 1250 | #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 |
619c5cb6 VZ |
1251 | |
1252 | #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 | |
1253 | #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 | |
9876879f | 1254 | #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 |
619c5cb6 VZ |
1255 | |
1256 | #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 | |
a3348722 BW |
1257 | |
1258 | #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 | |
1259 | #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 | |
1260 | #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 | |
1261 | #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 | |
1262 | #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 | |
1263 | ||
1d187b34 BW |
1264 | #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 |
1265 | #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 | |
f1410647 | 1266 | |
c8c60d88 YM |
1267 | #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 |
1268 | ||
619c5cb6 VZ |
1269 | #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 |
1270 | #define REQ_BC_VER_4_SET_MF_BW 0x00060202 | |
1271 | #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 | |
34f80b04 | 1272 | |
619c5cb6 VZ |
1273 | #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 |
1274 | ||
452427b0 YM |
1275 | #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 |
1276 | #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 | |
1277 | ||
619c5cb6 VZ |
1278 | #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 |
1279 | #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 | |
1280 | #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 | |
1281 | #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 | |
1282 | ||
1283 | #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff | |
f1410647 ET |
1284 | |
1285 | u32 drv_mb_param; | |
619c5cb6 VZ |
1286 | #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 |
1287 | #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 | |
f1410647 | 1288 | |
5d07d868 YM |
1289 | #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 |
1290 | ||
1291 | #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a | |
f1410647 | 1292 | u32 fw_mb_header; |
619c5cb6 VZ |
1293 | #define FW_MSG_CODE_MASK 0xffff0000 |
1294 | #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 | |
1295 | #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 | |
1296 | #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 | |
1297 | /* Load common chip is supported from bc 6.0.0 */ | |
1298 | #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 | |
1299 | #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 | |
1300 | ||
1301 | #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 | |
1302 | #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 | |
1303 | #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 | |
1304 | #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 | |
1305 | #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 | |
1306 | #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 | |
1307 | #define FW_MSG_CODE_DCC_DONE 0x30100000 | |
1308 | #define FW_MSG_CODE_LLDP_DONE 0x40100000 | |
1309 | #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 | |
1310 | #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 | |
1311 | #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 | |
1312 | #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 | |
1313 | #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 | |
1314 | #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 | |
1315 | #define FW_MSG_CODE_NO_KEY 0x80f00000 | |
1316 | #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 | |
1317 | #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 | |
1318 | #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 | |
1319 | #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 | |
1320 | #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 | |
1321 | #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 | |
1322 | #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 | |
1323 | #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 | |
1324 | #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 | |
1325 | #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 | |
a3348722 BW |
1326 | #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 |
1327 | ||
1328 | #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 | |
1329 | #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 | |
1330 | #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 | |
1331 | #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 | |
1332 | #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 | |
1333 | ||
1d187b34 BW |
1334 | #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 |
1335 | #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 | |
619c5cb6 | 1336 | |
c8c60d88 YM |
1337 | #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 |
1338 | ||
619c5cb6 VZ |
1339 | #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 |
1340 | #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 | |
1341 | ||
1342 | #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 | |
1343 | ||
1344 | #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 | |
1345 | #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 | |
1346 | #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 | |
1347 | #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 | |
1348 | ||
1349 | #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff | |
f1410647 ET |
1350 | |
1351 | u32 fw_mb_param; | |
1352 | ||
1353 | u32 drv_pulse_mb; | |
619c5cb6 VZ |
1354 | #define DRV_PULSE_SEQ_MASK 0x00007fff |
1355 | #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 | |
1356 | /* | |
1357 | * The system time is in the format of | |
1358 | * (year-2001)*12*32 + month*32 + day. | |
1359 | */ | |
1360 | #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 | |
1361 | /* | |
1362 | * Indicate to the firmware not to go into the | |
f1410647 | 1363 | * OS-absent when it is not getting driver pulse. |
619c5cb6 VZ |
1364 | * This is used for debugging as well for PXE(MBA). |
1365 | */ | |
f1410647 ET |
1366 | |
1367 | u32 mcp_pulse_mb; | |
619c5cb6 VZ |
1368 | #define MCP_PULSE_SEQ_MASK 0x00007fff |
1369 | #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 | |
f1410647 ET |
1370 | /* Indicates to the driver not to assert due to lack |
1371 | * of MCP response */ | |
619c5cb6 VZ |
1372 | #define MCP_EVENT_MASK 0xffff0000 |
1373 | #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 | |
f1410647 ET |
1374 | |
1375 | u32 iscsi_boot_signature; | |
1376 | u32 iscsi_boot_block_offset; | |
1377 | ||
34f80b04 | 1378 | u32 drv_status; |
619c5cb6 VZ |
1379 | #define DRV_STATUS_PMF 0x00000001 |
1380 | #define DRV_STATUS_VF_DISABLED 0x00000002 | |
1381 | #define DRV_STATUS_SET_MF_BW 0x00000004 | |
1382 | #define DRV_STATUS_LINK_EVENT 0x00000008 | |
1383 | ||
1384 | #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 | |
1385 | #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 | |
1386 | #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 | |
1387 | #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 | |
1388 | #define DRV_STATUS_DCC_RESERVED1 0x00000800 | |
1389 | #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 | |
1390 | #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 | |
1391 | ||
1392 | #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 | |
1393 | #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 | |
a3348722 BW |
1394 | #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 |
1395 | #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 | |
1396 | #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 | |
1397 | #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 | |
1398 | #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 | |
1399 | ||
1d187b34 | 1400 | #define DRV_STATUS_DRV_INFO_REQ 0x04000000 |
2691d51d | 1401 | |
c8c60d88 YM |
1402 | #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 |
1403 | ||
34f80b04 | 1404 | u32 virt_mac_upper; |
619c5cb6 VZ |
1405 | #define VIRT_MAC_SIGN_MASK 0xffff0000 |
1406 | #define VIRT_MAC_SIGNATURE 0x564d0000 | |
34f80b04 | 1407 | u32 virt_mac_lower; |
a2fbb9ea ET |
1408 | |
1409 | }; | |
1410 | ||
1411 | ||
1412 | /**************************************************************************** | |
619c5cb6 | 1413 | * Management firmware state * |
a2fbb9ea | 1414 | ****************************************************************************/ |
f1410647 | 1415 | /* Allocate 440 bytes for management firmware */ |
619c5cb6 | 1416 | #define MGMTFW_STATE_WORD_SIZE 110 |
a2fbb9ea ET |
1417 | |
1418 | struct mgmtfw_state { | |
1419 | u32 opaque[MGMTFW_STATE_WORD_SIZE]; | |
1420 | }; | |
1421 | ||
1422 | ||
34f80b04 | 1423 | /**************************************************************************** |
619c5cb6 | 1424 | * Multi-Function configuration * |
34f80b04 EG |
1425 | ****************************************************************************/ |
1426 | struct shared_mf_cfg { | |
1427 | ||
1428 | u32 clp_mb; | |
619c5cb6 | 1429 | #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 |
34f80b04 | 1430 | /* set by CLP */ |
619c5cb6 | 1431 | #define SHARED_MF_CLP_EXIT 0x00000001 |
34f80b04 | 1432 | /* set by MCP */ |
619c5cb6 | 1433 | #define SHARED_MF_CLP_EXIT_DONE 0x00010000 |
34f80b04 EG |
1434 | |
1435 | }; | |
1436 | ||
1437 | struct port_mf_cfg { | |
1438 | ||
619c5cb6 VZ |
1439 | u32 dynamic_cfg; /* device control channel */ |
1440 | #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff | |
1441 | #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 | |
1442 | #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK | |
34f80b04 | 1443 | |
621b4d66 | 1444 | u32 reserved[1]; |
34f80b04 EG |
1445 | |
1446 | }; | |
1447 | ||
1448 | struct func_mf_cfg { | |
1449 | ||
1450 | u32 config; | |
1451 | /* E/R/I/D */ | |
1452 | /* function 0 of each port cannot be hidden */ | |
619c5cb6 | 1453 | #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 |
34f80b04 | 1454 | |
619c5cb6 VZ |
1455 | #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 |
1456 | #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 | |
1457 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 | |
1458 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 | |
1459 | #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 | |
1460 | #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ | |
1461 | FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA | |
34f80b04 | 1462 | |
619c5cb6 VZ |
1463 | #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 |
1464 | #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 | |
34f80b04 EG |
1465 | |
1466 | /* PRI */ | |
1467 | /* 0 - low priority, 3 - high priority */ | |
619c5cb6 VZ |
1468 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 |
1469 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 | |
1470 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 | |
34f80b04 EG |
1471 | |
1472 | /* MINBW, MAXBW */ | |
1473 | /* value range - 0..100, increments in 100Mbps */ | |
619c5cb6 VZ |
1474 | #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 |
1475 | #define FUNC_MF_CFG_MIN_BW_SHIFT 16 | |
1476 | #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 | |
1477 | #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 | |
1478 | #define FUNC_MF_CFG_MAX_BW_SHIFT 24 | |
1479 | #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 | |
1480 | ||
1481 | u32 mac_upper; /* MAC */ | |
1482 | #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff | |
1483 | #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 | |
1484 | #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK | |
34f80b04 | 1485 | u32 mac_lower; |
619c5cb6 | 1486 | #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff |
34f80b04 EG |
1487 | |
1488 | u32 e1hov_tag; /* VNI */ | |
619c5cb6 VZ |
1489 | #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff |
1490 | #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 | |
1491 | #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK | |
34f80b04 | 1492 | |
a3348722 BW |
1493 | /* afex default VLAN ID - 12 bits */ |
1494 | #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 | |
1495 | #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 | |
1496 | ||
1497 | u32 afex_config; | |
1498 | #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff | |
1499 | #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 | |
1500 | #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 | |
1501 | #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 | |
1502 | #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 | |
1503 | #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 | |
1504 | #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 | |
1505 | ||
1506 | u32 reserved; | |
1507 | }; | |
1508 | ||
1509 | enum mf_cfg_afex_vlan_mode { | |
1510 | FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, | |
1511 | FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, | |
1512 | FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE | |
34f80b04 EG |
1513 | }; |
1514 | ||
0793f83f DK |
1515 | /* This structure is not applicable and should not be accessed on 57711 */ |
1516 | struct func_ext_cfg { | |
1517 | u32 func_cfg; | |
619c5cb6 VZ |
1518 | #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF |
1519 | #define MACP_FUNC_CFG_FLAGS_SHIFT 0 | |
1520 | #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 | |
1521 | #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 | |
1522 | #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 | |
1523 | #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 | |
0793f83f DK |
1524 | |
1525 | u32 iscsi_mac_addr_upper; | |
1526 | u32 iscsi_mac_addr_lower; | |
1527 | ||
1528 | u32 fcoe_mac_addr_upper; | |
1529 | u32 fcoe_mac_addr_lower; | |
1530 | ||
1531 | u32 fcoe_wwn_port_name_upper; | |
1532 | u32 fcoe_wwn_port_name_lower; | |
1533 | ||
1534 | u32 fcoe_wwn_node_name_upper; | |
1535 | u32 fcoe_wwn_node_name_lower; | |
1536 | ||
1537 | u32 preserve_data; | |
619c5cb6 VZ |
1538 | #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) |
1539 | #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) | |
1540 | #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) | |
1541 | #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) | |
1542 | #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) | |
1543 | #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) | |
0793f83f DK |
1544 | }; |
1545 | ||
34f80b04 EG |
1546 | struct mf_cfg { |
1547 | ||
619c5cb6 | 1548 | struct shared_mf_cfg shared_mf_config; /* 0x4 */ |
621b4d66 DK |
1549 | /* 0x8*2*2=0x20 */ |
1550 | struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; | |
619c5cb6 VZ |
1551 | /* for all chips, there are 8 mf functions */ |
1552 | struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ | |
1553 | /* | |
1554 | * Extended configuration per function - this array does not exist and | |
1555 | * should not be accessed on 57711 | |
1556 | */ | |
1557 | struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ | |
1558 | }; /* 0x224 */ | |
34f80b04 | 1559 | |
a2fbb9ea | 1560 | /**************************************************************************** |
619c5cb6 | 1561 | * Shared Memory Region * |
a2fbb9ea | 1562 | ****************************************************************************/ |
619c5cb6 | 1563 | struct shmem_region { /* SharedMem Offset (size) */ |
f1410647 | 1564 | |
619c5cb6 VZ |
1565 | u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ |
1566 | #define SHR_MEM_FORMAT_REV_MASK 0xff000000 | |
1567 | #define SHR_MEM_FORMAT_REV_ID ('A'<<24) | |
f1410647 | 1568 | /* validity bits */ |
619c5cb6 VZ |
1569 | #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 |
1570 | #define SHR_MEM_VALIDITY_MB 0x00200000 | |
1571 | #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 | |
1572 | #define SHR_MEM_VALIDITY_RESERVED 0x00000007 | |
a2fbb9ea | 1573 | /* One licensing bit should be set */ |
619c5cb6 VZ |
1574 | #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 |
1575 | #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 | |
1576 | #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 | |
1577 | #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 | |
f1410647 | 1578 | /* Active MFW */ |
619c5cb6 VZ |
1579 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 |
1580 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 | |
1581 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 | |
1582 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 | |
1583 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 | |
1584 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 | |
a2fbb9ea | 1585 | |
619c5cb6 | 1586 | struct shm_dev_info dev_info; /* 0x8 (0x438) */ |
a2fbb9ea | 1587 | |
619c5cb6 | 1588 | struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ |
a2fbb9ea ET |
1589 | |
1590 | /* FW information (for internal FW use) */ | |
619c5cb6 VZ |
1591 | u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ |
1592 | struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ | |
f1410647 | 1593 | |
619c5cb6 VZ |
1594 | struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ |
1595 | ||
1596 | #ifdef BMAPI | |
1597 | /* This is a variable length array */ | |
1598 | /* the number of function depends on the chip type */ | |
1599 | struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ | |
1600 | #else | |
1601 | /* the number of function depends on the chip type */ | |
1602 | struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ | |
1603 | #endif /* BMAPI */ | |
523224a3 DK |
1604 | |
1605 | }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ | |
34f80b04 | 1606 | |
619c5cb6 VZ |
1607 | /**************************************************************************** |
1608 | * Shared Memory 2 Region * | |
1609 | ****************************************************************************/ | |
1610 | /* The fw_flr_ack is actually built in the following way: */ | |
1611 | /* 8 bit: PF ack */ | |
1612 | /* 64 bit: VF ack */ | |
1613 | /* 8 bit: ios_dis_ack */ | |
1614 | /* In order to maintain endianity in the mailbox hsi, we want to keep using */ | |
1615 | /* u32. The fw must have the VF right after the PF since this is how it */ | |
1616 | /* access arrays(it expects always the VF to reside after the PF, and that */ | |
1617 | /* makes the calculation much easier for it. ) */ | |
1618 | /* In order to answer both limitations, and keep the struct small, the code */ | |
1619 | /* will abuse the structure defined here to achieve the actual partition */ | |
1620 | /* above */ | |
1621 | /****************************************************************************/ | |
f2e0899f | 1622 | struct fw_flr_ack { |
619c5cb6 VZ |
1623 | u32 pf_ack; |
1624 | u32 vf_ack[1]; | |
1625 | u32 iov_dis_ack; | |
f2e0899f | 1626 | }; |
a2fbb9ea | 1627 | |
f2e0899f | 1628 | struct fw_flr_mb { |
619c5cb6 VZ |
1629 | u32 aggint; |
1630 | u32 opgen_addr; | |
1631 | struct fw_flr_ack ack; | |
f2e0899f | 1632 | }; |
a2fbb9ea | 1633 | |
c8c60d88 YM |
1634 | struct eee_remote_vals { |
1635 | u32 tx_tw; | |
1636 | u32 rx_tw; | |
1637 | }; | |
1638 | ||
e4901dde VZ |
1639 | /**** SUPPORT FOR SHMEM ARRRAYS *** |
1640 | * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to | |
1641 | * define arrays with storage types smaller then unsigned dwords. | |
1642 | * The macros below add generic support for SHMEM arrays with numeric elements | |
1643 | * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword | |
1644 | * array with individual bit-filed elements accessed using shifts and masks. | |
1645 | * | |
1646 | */ | |
1647 | ||
1648 | /* eb is the bitwidth of a single element */ | |
1649 | #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) | |
1650 | #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) | |
1651 | ||
1652 | /* the bit-position macro allows the used to flip the order of the arrays | |
1653 | * elements on a per byte or word boundary. | |
1654 | * | |
1655 | * example: an array with 8 entries each 4 bit wide. This array will fit into | |
1656 | * a single dword. The diagrmas below show the array order of the nibbles. | |
1657 | * | |
1658 | * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: | |
1659 | * | |
619c5cb6 VZ |
1660 | * | | | | |
1661 | * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | | |
1662 | * | | | | | |
e4901dde VZ |
1663 | * |
1664 | * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: | |
1665 | * | |
619c5cb6 VZ |
1666 | * | | | | |
1667 | * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | | |
1668 | * | | | | | |
e4901dde VZ |
1669 | * |
1670 | * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: | |
1671 | * | |
619c5cb6 VZ |
1672 | * | | | | |
1673 | * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | | |
1674 | * | | | | | |
e4901dde VZ |
1675 | */ |
1676 | #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ | |
1677 | ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ | |
1678 | (((i)%((fb)/(eb))) * (eb))) | |
1679 | ||
619c5cb6 | 1680 | #define SHMEM_ARRAY_GET(a, i, eb, fb) \ |
e4901dde VZ |
1681 | ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ |
1682 | SHMEM_ARRAY_MASK(eb)) | |
1683 | ||
619c5cb6 | 1684 | #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ |
e4901dde VZ |
1685 | do { \ |
1686 | a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ | |
619c5cb6 | 1687 | SHMEM_ARRAY_BITPOS(i, eb, fb)); \ |
e4901dde | 1688 | a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ |
619c5cb6 | 1689 | SHMEM_ARRAY_BITPOS(i, eb, fb)); \ |
e4901dde VZ |
1690 | } while (0) |
1691 | ||
1692 | ||
1693 | /****START OF DCBX STRUCTURES DECLARATIONS****/ | |
1694 | #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 | |
1695 | #define DCBX_PRI_PG_BITWIDTH 4 | |
1696 | #define DCBX_PRI_PG_FBITS 8 | |
1697 | #define DCBX_PRI_PG_GET(a, i) \ | |
1698 | SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) | |
1699 | #define DCBX_PRI_PG_SET(a, i, val) \ | |
1700 | SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) | |
1701 | #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 | |
1702 | #define DCBX_BW_PG_BITWIDTH 8 | |
1703 | #define DCBX_PG_BW_GET(a, i) \ | |
1704 | SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) | |
1705 | #define DCBX_PG_BW_SET(a, i, val) \ | |
1706 | SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) | |
1707 | #define DCBX_STRICT_PRI_PG 15 | |
1708 | #define DCBX_MAX_APP_PROTOCOL 16 | |
1709 | #define FCOE_APP_IDX 0 | |
1710 | #define ISCSI_APP_IDX 1 | |
1711 | #define PREDEFINED_APP_IDX_MAX 2 | |
1712 | ||
619c5cb6 VZ |
1713 | |
1714 | /* Big/Little endian have the same representation. */ | |
e4901dde | 1715 | struct dcbx_ets_feature { |
619c5cb6 VZ |
1716 | /* |
1717 | * For Admin MIB - is this feature supported by the | |
1718 | * driver | For Local MIB - should this feature be enabled. | |
1719 | */ | |
e4901dde VZ |
1720 | u32 enabled; |
1721 | u32 pg_bw_tbl[2]; | |
1722 | u32 pri_pg_tbl[1]; | |
1723 | }; | |
1724 | ||
619c5cb6 | 1725 | /* Driver structure in LE */ |
e4901dde VZ |
1726 | struct dcbx_pfc_feature { |
1727 | #ifdef __BIG_ENDIAN | |
1728 | u8 pri_en_bitmap; | |
619c5cb6 VZ |
1729 | #define DCBX_PFC_PRI_0 0x01 |
1730 | #define DCBX_PFC_PRI_1 0x02 | |
1731 | #define DCBX_PFC_PRI_2 0x04 | |
1732 | #define DCBX_PFC_PRI_3 0x08 | |
1733 | #define DCBX_PFC_PRI_4 0x10 | |
1734 | #define DCBX_PFC_PRI_5 0x20 | |
1735 | #define DCBX_PFC_PRI_6 0x40 | |
1736 | #define DCBX_PFC_PRI_7 0x80 | |
e4901dde VZ |
1737 | u8 pfc_caps; |
1738 | u8 reserved; | |
1739 | u8 enabled; | |
1740 | #elif defined(__LITTLE_ENDIAN) | |
1741 | u8 enabled; | |
1742 | u8 reserved; | |
1743 | u8 pfc_caps; | |
1744 | u8 pri_en_bitmap; | |
619c5cb6 VZ |
1745 | #define DCBX_PFC_PRI_0 0x01 |
1746 | #define DCBX_PFC_PRI_1 0x02 | |
1747 | #define DCBX_PFC_PRI_2 0x04 | |
1748 | #define DCBX_PFC_PRI_3 0x08 | |
1749 | #define DCBX_PFC_PRI_4 0x10 | |
1750 | #define DCBX_PFC_PRI_5 0x20 | |
1751 | #define DCBX_PFC_PRI_6 0x40 | |
1752 | #define DCBX_PFC_PRI_7 0x80 | |
e4901dde VZ |
1753 | #endif |
1754 | }; | |
1755 | ||
1756 | struct dcbx_app_priority_entry { | |
1757 | #ifdef __BIG_ENDIAN | |
619c5cb6 VZ |
1758 | u16 app_id; |
1759 | u8 pri_bitmap; | |
1760 | u8 appBitfield; | |
1761 | #define DCBX_APP_ENTRY_VALID 0x01 | |
1762 | #define DCBX_APP_ENTRY_SF_MASK 0x30 | |
1763 | #define DCBX_APP_ENTRY_SF_SHIFT 4 | |
1764 | #define DCBX_APP_SF_ETH_TYPE 0x10 | |
1765 | #define DCBX_APP_SF_PORT 0x20 | |
e4901dde VZ |
1766 | #elif defined(__LITTLE_ENDIAN) |
1767 | u8 appBitfield; | |
619c5cb6 VZ |
1768 | #define DCBX_APP_ENTRY_VALID 0x01 |
1769 | #define DCBX_APP_ENTRY_SF_MASK 0x30 | |
1770 | #define DCBX_APP_ENTRY_SF_SHIFT 4 | |
1771 | #define DCBX_APP_SF_ETH_TYPE 0x10 | |
1772 | #define DCBX_APP_SF_PORT 0x20 | |
1773 | u8 pri_bitmap; | |
1774 | u16 app_id; | |
e4901dde VZ |
1775 | #endif |
1776 | }; | |
1777 | ||
619c5cb6 VZ |
1778 | |
1779 | /* FW structure in BE */ | |
e4901dde VZ |
1780 | struct dcbx_app_priority_feature { |
1781 | #ifdef __BIG_ENDIAN | |
1782 | u8 reserved; | |
1783 | u8 default_pri; | |
1784 | u8 tc_supported; | |
1785 | u8 enabled; | |
1786 | #elif defined(__LITTLE_ENDIAN) | |
1787 | u8 enabled; | |
1788 | u8 tc_supported; | |
1789 | u8 default_pri; | |
1790 | u8 reserved; | |
1791 | #endif | |
1792 | struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; | |
1793 | }; | |
1794 | ||
619c5cb6 | 1795 | /* FW structure in BE */ |
e4901dde | 1796 | struct dcbx_features { |
619c5cb6 | 1797 | /* PG feature */ |
e4901dde | 1798 | struct dcbx_ets_feature ets; |
619c5cb6 | 1799 | /* PFC feature */ |
e4901dde | 1800 | struct dcbx_pfc_feature pfc; |
619c5cb6 | 1801 | /* APP feature */ |
e4901dde VZ |
1802 | struct dcbx_app_priority_feature app; |
1803 | }; | |
1804 | ||
619c5cb6 VZ |
1805 | /* LLDP protocol parameters */ |
1806 | /* FW structure in BE */ | |
e4901dde VZ |
1807 | struct lldp_params { |
1808 | #ifdef __BIG_ENDIAN | |
619c5cb6 VZ |
1809 | u8 msg_fast_tx_interval; |
1810 | u8 msg_tx_hold; | |
1811 | u8 msg_tx_interval; | |
1812 | u8 admin_status; | |
1813 | #define LLDP_TX_ONLY 0x01 | |
1814 | #define LLDP_RX_ONLY 0x02 | |
1815 | #define LLDP_TX_RX 0x03 | |
1816 | #define LLDP_DISABLED 0x04 | |
1817 | u8 reserved1; | |
1818 | u8 tx_fast; | |
1819 | u8 tx_crd_max; | |
1820 | u8 tx_crd; | |
e4901dde | 1821 | #elif defined(__LITTLE_ENDIAN) |
619c5cb6 VZ |
1822 | u8 admin_status; |
1823 | #define LLDP_TX_ONLY 0x01 | |
1824 | #define LLDP_RX_ONLY 0x02 | |
1825 | #define LLDP_TX_RX 0x03 | |
1826 | #define LLDP_DISABLED 0x04 | |
1827 | u8 msg_tx_interval; | |
1828 | u8 msg_tx_hold; | |
1829 | u8 msg_fast_tx_interval; | |
1830 | u8 tx_crd; | |
1831 | u8 tx_crd_max; | |
1832 | u8 tx_fast; | |
1833 | u8 reserved1; | |
e4901dde | 1834 | #endif |
619c5cb6 VZ |
1835 | #define REM_CHASSIS_ID_STAT_LEN 4 |
1836 | #define REM_PORT_ID_STAT_LEN 4 | |
1837 | /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ | |
e4901dde | 1838 | u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; |
619c5cb6 | 1839 | /* Holds remote Port ID TLV header, subtype and 9B of payload. */ |
e4901dde VZ |
1840 | u32 peer_port_id[REM_PORT_ID_STAT_LEN]; |
1841 | }; | |
1842 | ||
1843 | struct lldp_dcbx_stat { | |
619c5cb6 VZ |
1844 | #define LOCAL_CHASSIS_ID_STAT_LEN 2 |
1845 | #define LOCAL_PORT_ID_STAT_LEN 2 | |
1846 | /* Holds local Chassis ID 8B payload of constant subtype 4. */ | |
e4901dde | 1847 | u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; |
619c5cb6 | 1848 | /* Holds local Port ID 8B payload of constant subtype 3. */ |
e4901dde | 1849 | u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; |
619c5cb6 | 1850 | /* Number of DCBX frames transmitted. */ |
e4901dde | 1851 | u32 num_tx_dcbx_pkts; |
619c5cb6 | 1852 | /* Number of DCBX frames received. */ |
e4901dde VZ |
1853 | u32 num_rx_dcbx_pkts; |
1854 | }; | |
1855 | ||
619c5cb6 | 1856 | /* ADMIN MIB - DCBX local machine default configuration. */ |
e4901dde | 1857 | struct lldp_admin_mib { |
619c5cb6 VZ |
1858 | u32 ver_cfg_flags; |
1859 | #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 | |
1860 | #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 | |
1861 | #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 | |
1862 | #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 | |
1863 | #define DCBX_ETS_RECO_VALID 0x00000010 | |
1864 | #define DCBX_ETS_WILLING 0x00000020 | |
1865 | #define DCBX_PFC_WILLING 0x00000040 | |
1866 | #define DCBX_APP_WILLING 0x00000080 | |
1867 | #define DCBX_VERSION_CEE 0x00000100 | |
1868 | #define DCBX_VERSION_IEEE 0x00000200 | |
1869 | #define DCBX_DCBX_ENABLED 0x00000400 | |
1870 | #define DCBX_CEE_VERSION_MASK 0x0000f000 | |
1871 | #define DCBX_CEE_VERSION_SHIFT 12 | |
1872 | #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 | |
1873 | #define DCBX_CEE_MAX_VERSION_SHIFT 16 | |
1874 | struct dcbx_features features; | |
1875 | }; | |
1876 | ||
1877 | /* REMOTE MIB - remote machine DCBX configuration. */ | |
e4901dde VZ |
1878 | struct lldp_remote_mib { |
1879 | u32 prefix_seq_num; | |
1880 | u32 flags; | |
619c5cb6 VZ |
1881 | #define DCBX_ETS_TLV_RX 0x00000001 |
1882 | #define DCBX_PFC_TLV_RX 0x00000002 | |
1883 | #define DCBX_APP_TLV_RX 0x00000004 | |
1884 | #define DCBX_ETS_RX_ERROR 0x00000010 | |
1885 | #define DCBX_PFC_RX_ERROR 0x00000020 | |
1886 | #define DCBX_APP_RX_ERROR 0x00000040 | |
1887 | #define DCBX_ETS_REM_WILLING 0x00000100 | |
1888 | #define DCBX_PFC_REM_WILLING 0x00000200 | |
1889 | #define DCBX_APP_REM_WILLING 0x00000400 | |
1890 | #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 | |
1891 | #define DCBX_REMOTE_MIB_VALID 0x00002000 | |
e4901dde VZ |
1892 | struct dcbx_features features; |
1893 | u32 suffix_seq_num; | |
1894 | }; | |
1895 | ||
619c5cb6 | 1896 | /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ |
e4901dde VZ |
1897 | struct lldp_local_mib { |
1898 | u32 prefix_seq_num; | |
619c5cb6 | 1899 | /* Indicates if there is mismatch with negotiation results. */ |
e4901dde | 1900 | u32 error; |
619c5cb6 VZ |
1901 | #define DCBX_LOCAL_ETS_ERROR 0x00000001 |
1902 | #define DCBX_LOCAL_PFC_ERROR 0x00000002 | |
1903 | #define DCBX_LOCAL_APP_ERROR 0x00000004 | |
1904 | #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 | |
1905 | #define DCBX_LOCAL_APP_MISMATCH 0x00000020 | |
6debea87 | 1906 | #define DCBX_REMOTE_MIB_ERROR 0x00000040 |
910b2202 DK |
1907 | #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 |
1908 | #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 | |
1909 | #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 | |
e4901dde VZ |
1910 | struct dcbx_features features; |
1911 | u32 suffix_seq_num; | |
1912 | }; | |
1913 | /***END OF DCBX STRUCTURES DECLARATIONS***/ | |
a2fbb9ea | 1914 | |
d3a8f13b YR |
1915 | /***********************************************************/ |
1916 | /* Elink section */ | |
1917 | /***********************************************************/ | |
1918 | #define SHMEM_LINK_CONFIG_SIZE 2 | |
1919 | struct shmem_lfa { | |
1920 | u32 req_duplex; | |
1921 | #define REQ_DUPLEX_PHY0_MASK 0x0000ffff | |
1922 | #define REQ_DUPLEX_PHY0_SHIFT 0 | |
1923 | #define REQ_DUPLEX_PHY1_MASK 0xffff0000 | |
1924 | #define REQ_DUPLEX_PHY1_SHIFT 16 | |
1925 | u32 req_flow_ctrl; | |
1926 | #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff | |
1927 | #define REQ_FLOW_CTRL_PHY0_SHIFT 0 | |
1928 | #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 | |
1929 | #define REQ_FLOW_CTRL_PHY1_SHIFT 16 | |
1930 | u32 req_line_speed; /* Also determine AutoNeg */ | |
1931 | #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff | |
1932 | #define REQ_LINE_SPD_PHY0_SHIFT 0 | |
1933 | #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 | |
1934 | #define REQ_LINE_SPD_PHY1_SHIFT 16 | |
1935 | u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; | |
1936 | u32 additional_config; | |
1937 | #define REQ_FC_AUTO_ADV_MASK 0x0000ffff | |
1938 | #define REQ_FC_AUTO_ADV0_SHIFT 0 | |
1939 | #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 | |
1940 | u32 lfa_sts; | |
1941 | #define LFA_LINK_FLAP_REASON_OFFSET 0 | |
1942 | #define LFA_LINK_FLAP_REASON_MASK 0x000000ff | |
1943 | #define LFA_LINK_DOWN 0x1 | |
1944 | #define LFA_LOOPBACK_ENABLED 0x2 | |
1945 | #define LFA_DUPLEX_MISMATCH 0x3 | |
1946 | #define LFA_MFW_IS_TOO_OLD 0x4 | |
1947 | #define LFA_LINK_SPEED_MISMATCH 0x5 | |
1948 | #define LFA_FLOW_CTRL_MISMATCH 0x6 | |
1949 | #define LFA_SPEED_CAP_MISMATCH 0x7 | |
1950 | #define LFA_DCC_LFA_DISABLED 0x8 | |
1951 | #define LFA_EEE_MISMATCH 0x9 | |
1952 | ||
1953 | #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 | |
1954 | #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 | |
1955 | ||
1956 | #define LINK_FLAP_COUNT_OFFSET 16 | |
1957 | #define LINK_FLAP_COUNT_MASK 0x00ff0000 | |
1958 | ||
1959 | #define LFA_FLAGS_MASK 0xff000000 | |
1960 | #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) | |
1961 | }; | |
1962 | ||
619c5cb6 VZ |
1963 | struct ncsi_oem_fcoe_features { |
1964 | u32 fcoe_features1; | |
1965 | #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF | |
1966 | #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 | |
1967 | ||
1968 | #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 | |
1969 | #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 | |
1970 | ||
1971 | u32 fcoe_features2; | |
1972 | #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF | |
1973 | #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 | |
1974 | ||
1975 | #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 | |
1976 | #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 | |
1977 | ||
1978 | u32 fcoe_features3; | |
1979 | #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF | |
1980 | #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 | |
1981 | ||
1982 | #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 | |
1983 | #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 | |
1984 | ||
1985 | u32 fcoe_features4; | |
1986 | #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F | |
1987 | #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 | |
1988 | }; | |
1989 | ||
1990 | struct ncsi_oem_data { | |
1991 | u32 driver_version[4]; | |
1992 | struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; | |
1993 | }; | |
1994 | ||
2691d51d EG |
1995 | struct shmem2_region { |
1996 | ||
619c5cb6 VZ |
1997 | u32 size; /* 0x0000 */ |
1998 | ||
1999 | u32 dcc_support; /* 0x0004 */ | |
2000 | #define SHMEM_DCC_SUPPORT_NONE 0x00000000 | |
2001 | #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 | |
2002 | #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 | |
2003 | #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 | |
2004 | #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 | |
2005 | #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 | |
2006 | ||
2007 | u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ | |
a22f0788 YR |
2008 | /* |
2009 | * For backwards compatibility, if the mf_cfg_addr does not exist | |
2010 | * (the size filed is smaller than 0xc) the mf_cfg resides at the | |
2011 | * end of struct shmem_region | |
619c5cb6 VZ |
2012 | */ |
2013 | u32 mf_cfg_addr; /* 0x0010 */ | |
2014 | #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 | |
2015 | ||
2016 | struct fw_flr_mb flr_mb; /* 0x0014 */ | |
2017 | u32 dcbx_lldp_params_offset; /* 0x0028 */ | |
2018 | #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 | |
2019 | u32 dcbx_neg_res_offset; /* 0x002c */ | |
2020 | #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 | |
2021 | u32 dcbx_remote_mib_offset; /* 0x0030 */ | |
2022 | #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 | |
f2e0899f DK |
2023 | /* |
2024 | * The other shmemX_base_addr holds the other path's shmem address | |
2025 | * required for example in case of common phy init, or for path1 to know | |
2026 | * the address of mcp debug trace which is located in offset from shmem | |
2027 | * of path0 | |
a22f0788 | 2028 | */ |
619c5cb6 VZ |
2029 | u32 other_shmem_base_addr; /* 0x0034 */ |
2030 | u32 other_shmem2_base_addr; /* 0x0038 */ | |
2031 | /* | |
2032 | * mcp_vf_disabled is set by the MCP to indicate the driver about VFs | |
2033 | * which were disabled/flred | |
2034 | */ | |
2035 | u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ | |
2036 | ||
2037 | /* | |
2038 | * drv_ack_vf_disabled is set by the PF driver to ack handled disabled | |
2039 | * VFs | |
2040 | */ | |
2041 | u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ | |
2042 | ||
2043 | u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ | |
2044 | #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 | |
2045 | ||
2046 | /* | |
2047 | * edebug_driver_if field is used to transfer messages between edebug | |
2048 | * app to the driver through shmem2. | |
2049 | * | |
2050 | * message format: | |
2051 | * bits 0-2 - function number / instance of driver to perform request | |
2052 | * bits 3-5 - op code / is_ack? | |
2053 | * bits 6-63 - data | |
2054 | */ | |
2055 | u32 edebug_driver_if[2]; /* 0x0068 */ | |
2056 | #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 | |
2057 | #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 | |
2058 | #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 | |
2059 | ||
2060 | u32 nvm_retain_bitmap_addr; /* 0x0070 */ | |
2061 | ||
a3348722 BW |
2062 | /* afex support of that driver */ |
2063 | u32 afex_driver_support; /* 0x0074 */ | |
2064 | #define SHMEM_AFEX_VERSION_MASK 0x100f | |
2065 | #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 | |
2066 | #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 | |
619c5cb6 | 2067 | |
a3348722 BW |
2068 | /* driver receives addr in scratchpad to which it should respond */ |
2069 | u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX]; | |
619c5cb6 | 2070 | |
a3348722 BW |
2071 | /* generic params from MCP to driver (value depends on the msg sent |
2072 | * to driver | |
2073 | */ | |
2074 | u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ | |
2075 | u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ | |
619c5cb6 VZ |
2076 | |
2077 | u32 swim_base_addr; /* 0x0108 */ | |
2078 | u32 swim_funcs; | |
2079 | u32 swim_main_cb; | |
2080 | ||
a3348722 BW |
2081 | /* bitmap notifying which VIF profiles stored in nvram are enabled by |
2082 | * switch | |
2083 | */ | |
2084 | u32 afex_profiles_enabled[2]; | |
619c5cb6 VZ |
2085 | |
2086 | /* generic flags controlled by the driver */ | |
2087 | u32 drv_flags; | |
2088 | #define DRV_FLAGS_DCB_CONFIGURED 0x1 | |
2089 | ||
2090 | /* pointer to extended dev_info shared data copied from nvm image */ | |
2091 | u32 extended_dev_info_shared_addr; | |
2092 | u32 ncsi_oem_data_addr; | |
2093 | ||
1d187b34 BW |
2094 | u32 ocsd_host_addr; /* initialized by option ROM */ |
2095 | u32 ocbb_host_addr; /* initialized by option ROM */ | |
2096 | u32 ocsd_req_update_interval; /* initialized by option ROM */ | |
2097 | u32 temperature_in_half_celsius; | |
2098 | u32 glob_struct_in_host; | |
2099 | ||
2100 | u32 dcbx_neg_res_ext_offset; | |
2101 | #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 | |
2102 | ||
2103 | u32 drv_capabilities_flag[E2_FUNC_MAX]; | |
2104 | #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 | |
2105 | #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 | |
2106 | #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 | |
2107 | #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 | |
2108 | ||
2109 | u32 extended_dev_info_shared_cfg_size; | |
2110 | ||
2111 | u32 dcbx_en[PORT_MAX]; | |
2112 | ||
2113 | /* The offset points to the multi threaded meta structure */ | |
2114 | u32 multi_thread_data_offset; | |
2115 | ||
2116 | /* address of DMAable host address holding values from the drivers */ | |
2117 | u32 drv_info_host_addr_lo; | |
2118 | u32 drv_info_host_addr_hi; | |
2119 | ||
2120 | /* general values written by the MFW (such as current version) */ | |
2121 | u32 drv_info_control; | |
2122 | #define DRV_INFO_CONTROL_VER_MASK 0x000000ff | |
2123 | #define DRV_INFO_CONTROL_VER_SHIFT 0 | |
2124 | #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 | |
2125 | #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 | |
621b4d66 | 2126 | u32 ibft_host_addr; /* initialized by option ROM */ |
c8c60d88 YM |
2127 | struct eee_remote_vals eee_remote_vals[PORT_MAX]; |
2128 | u32 reserved[E2_FUNC_MAX]; | |
2129 | ||
2130 | ||
2131 | /* the status of EEE auto-negotiation | |
2132 | * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. | |
2133 | * bits 19:16 the supported modes for EEE. | |
2134 | * bits 23:20 the speeds advertised for EEE. | |
2135 | * bits 27:24 the speeds the Link partner advertised for EEE. | |
2136 | * The supported/adv. modes in bits 27:19 originate from the | |
2137 | * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). | |
2138 | * bit 28 when 1'b1 EEE was requested. | |
2139 | * bit 29 when 1'b1 tx lpi was requested. | |
2140 | * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff | |
2141 | * 30:29 are 2'b11. | |
2142 | * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as | |
2143 | * value. When 1'b1 those bits contains a value times 16 microseconds. | |
2144 | */ | |
2145 | u32 eee_status[PORT_MAX]; | |
2146 | #define SHMEM_EEE_TIMER_MASK 0x0000ffff | |
2147 | #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 | |
2148 | #define SHMEM_EEE_SUPPORTED_SHIFT 16 | |
2149 | #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 | |
2150 | #define SHMEM_EEE_100M_ADV (1<<0) | |
2151 | #define SHMEM_EEE_1G_ADV (1<<1) | |
2152 | #define SHMEM_EEE_10G_ADV (1<<2) | |
2153 | #define SHMEM_EEE_ADV_STATUS_SHIFT 20 | |
2154 | #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 | |
2155 | #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 | |
2156 | #define SHMEM_EEE_REQUESTED_BIT 0x10000000 | |
2157 | #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 | |
2158 | #define SHMEM_EEE_ACTIVE_BIT 0x40000000 | |
2159 | #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 | |
2160 | ||
2161 | u32 sizeof_port_stats; | |
2691d51d EG |
2162 | }; |
2163 | ||
2164 | ||
bb2a0f7a | 2165 | struct emac_stats { |
619c5cb6 VZ |
2166 | u32 rx_stat_ifhcinoctets; |
2167 | u32 rx_stat_ifhcinbadoctets; | |
2168 | u32 rx_stat_etherstatsfragments; | |
2169 | u32 rx_stat_ifhcinucastpkts; | |
2170 | u32 rx_stat_ifhcinmulticastpkts; | |
2171 | u32 rx_stat_ifhcinbroadcastpkts; | |
2172 | u32 rx_stat_dot3statsfcserrors; | |
2173 | u32 rx_stat_dot3statsalignmenterrors; | |
2174 | u32 rx_stat_dot3statscarriersenseerrors; | |
2175 | u32 rx_stat_xonpauseframesreceived; | |
2176 | u32 rx_stat_xoffpauseframesreceived; | |
2177 | u32 rx_stat_maccontrolframesreceived; | |
2178 | u32 rx_stat_xoffstateentered; | |
2179 | u32 rx_stat_dot3statsframestoolong; | |
2180 | u32 rx_stat_etherstatsjabbers; | |
2181 | u32 rx_stat_etherstatsundersizepkts; | |
2182 | u32 rx_stat_etherstatspkts64octets; | |
2183 | u32 rx_stat_etherstatspkts65octetsto127octets; | |
2184 | u32 rx_stat_etherstatspkts128octetsto255octets; | |
2185 | u32 rx_stat_etherstatspkts256octetsto511octets; | |
2186 | u32 rx_stat_etherstatspkts512octetsto1023octets; | |
2187 | u32 rx_stat_etherstatspkts1024octetsto1522octets; | |
2188 | u32 rx_stat_etherstatspktsover1522octets; | |
2189 | ||
2190 | u32 rx_stat_falsecarriererrors; | |
2191 | ||
2192 | u32 tx_stat_ifhcoutoctets; | |
2193 | u32 tx_stat_ifhcoutbadoctets; | |
2194 | u32 tx_stat_etherstatscollisions; | |
2195 | u32 tx_stat_outxonsent; | |
2196 | u32 tx_stat_outxoffsent; | |
2197 | u32 tx_stat_flowcontroldone; | |
2198 | u32 tx_stat_dot3statssinglecollisionframes; | |
2199 | u32 tx_stat_dot3statsmultiplecollisionframes; | |
2200 | u32 tx_stat_dot3statsdeferredtransmissions; | |
2201 | u32 tx_stat_dot3statsexcessivecollisions; | |
2202 | u32 tx_stat_dot3statslatecollisions; | |
2203 | u32 tx_stat_ifhcoutucastpkts; | |
2204 | u32 tx_stat_ifhcoutmulticastpkts; | |
2205 | u32 tx_stat_ifhcoutbroadcastpkts; | |
2206 | u32 tx_stat_etherstatspkts64octets; | |
2207 | u32 tx_stat_etherstatspkts65octetsto127octets; | |
2208 | u32 tx_stat_etherstatspkts128octetsto255octets; | |
2209 | u32 tx_stat_etherstatspkts256octetsto511octets; | |
2210 | u32 tx_stat_etherstatspkts512octetsto1023octets; | |
2211 | u32 tx_stat_etherstatspkts1024octetsto1522octets; | |
2212 | u32 tx_stat_etherstatspktsover1522octets; | |
2213 | u32 tx_stat_dot3statsinternalmactransmiterrors; | |
bb2a0f7a YG |
2214 | }; |
2215 | ||
2216 | ||
523224a3 | 2217 | struct bmac1_stats { |
619c5cb6 VZ |
2218 | u32 tx_stat_gtpkt_lo; |
2219 | u32 tx_stat_gtpkt_hi; | |
2220 | u32 tx_stat_gtxpf_lo; | |
2221 | u32 tx_stat_gtxpf_hi; | |
2222 | u32 tx_stat_gtfcs_lo; | |
2223 | u32 tx_stat_gtfcs_hi; | |
2224 | u32 tx_stat_gtmca_lo; | |
2225 | u32 tx_stat_gtmca_hi; | |
2226 | u32 tx_stat_gtbca_lo; | |
2227 | u32 tx_stat_gtbca_hi; | |
2228 | u32 tx_stat_gtfrg_lo; | |
2229 | u32 tx_stat_gtfrg_hi; | |
2230 | u32 tx_stat_gtovr_lo; | |
2231 | u32 tx_stat_gtovr_hi; | |
2232 | u32 tx_stat_gt64_lo; | |
2233 | u32 tx_stat_gt64_hi; | |
2234 | u32 tx_stat_gt127_lo; | |
2235 | u32 tx_stat_gt127_hi; | |
2236 | u32 tx_stat_gt255_lo; | |
2237 | u32 tx_stat_gt255_hi; | |
2238 | u32 tx_stat_gt511_lo; | |
2239 | u32 tx_stat_gt511_hi; | |
2240 | u32 tx_stat_gt1023_lo; | |
2241 | u32 tx_stat_gt1023_hi; | |
2242 | u32 tx_stat_gt1518_lo; | |
2243 | u32 tx_stat_gt1518_hi; | |
2244 | u32 tx_stat_gt2047_lo; | |
2245 | u32 tx_stat_gt2047_hi; | |
2246 | u32 tx_stat_gt4095_lo; | |
2247 | u32 tx_stat_gt4095_hi; | |
2248 | u32 tx_stat_gt9216_lo; | |
2249 | u32 tx_stat_gt9216_hi; | |
2250 | u32 tx_stat_gt16383_lo; | |
2251 | u32 tx_stat_gt16383_hi; | |
2252 | u32 tx_stat_gtmax_lo; | |
2253 | u32 tx_stat_gtmax_hi; | |
2254 | u32 tx_stat_gtufl_lo; | |
2255 | u32 tx_stat_gtufl_hi; | |
2256 | u32 tx_stat_gterr_lo; | |
2257 | u32 tx_stat_gterr_hi; | |
2258 | u32 tx_stat_gtbyt_lo; | |
2259 | u32 tx_stat_gtbyt_hi; | |
2260 | ||
2261 | u32 rx_stat_gr64_lo; | |
2262 | u32 rx_stat_gr64_hi; | |
2263 | u32 rx_stat_gr127_lo; | |
2264 | u32 rx_stat_gr127_hi; | |
2265 | u32 rx_stat_gr255_lo; | |
2266 | u32 rx_stat_gr255_hi; | |
2267 | u32 rx_stat_gr511_lo; | |
2268 | u32 rx_stat_gr511_hi; | |
2269 | u32 rx_stat_gr1023_lo; | |
2270 | u32 rx_stat_gr1023_hi; | |
2271 | u32 rx_stat_gr1518_lo; | |
2272 | u32 rx_stat_gr1518_hi; | |
2273 | u32 rx_stat_gr2047_lo; | |
2274 | u32 rx_stat_gr2047_hi; | |
2275 | u32 rx_stat_gr4095_lo; | |
2276 | u32 rx_stat_gr4095_hi; | |
2277 | u32 rx_stat_gr9216_lo; | |
2278 | u32 rx_stat_gr9216_hi; | |
2279 | u32 rx_stat_gr16383_lo; | |
2280 | u32 rx_stat_gr16383_hi; | |
2281 | u32 rx_stat_grmax_lo; | |
2282 | u32 rx_stat_grmax_hi; | |
2283 | u32 rx_stat_grpkt_lo; | |
2284 | u32 rx_stat_grpkt_hi; | |
2285 | u32 rx_stat_grfcs_lo; | |
2286 | u32 rx_stat_grfcs_hi; | |
2287 | u32 rx_stat_grmca_lo; | |
2288 | u32 rx_stat_grmca_hi; | |
2289 | u32 rx_stat_grbca_lo; | |
2290 | u32 rx_stat_grbca_hi; | |
2291 | u32 rx_stat_grxcf_lo; | |
2292 | u32 rx_stat_grxcf_hi; | |
2293 | u32 rx_stat_grxpf_lo; | |
2294 | u32 rx_stat_grxpf_hi; | |
2295 | u32 rx_stat_grxuo_lo; | |
2296 | u32 rx_stat_grxuo_hi; | |
2297 | u32 rx_stat_grjbr_lo; | |
2298 | u32 rx_stat_grjbr_hi; | |
2299 | u32 rx_stat_grovr_lo; | |
2300 | u32 rx_stat_grovr_hi; | |
2301 | u32 rx_stat_grflr_lo; | |
2302 | u32 rx_stat_grflr_hi; | |
2303 | u32 rx_stat_grmeg_lo; | |
2304 | u32 rx_stat_grmeg_hi; | |
2305 | u32 rx_stat_grmeb_lo; | |
2306 | u32 rx_stat_grmeb_hi; | |
2307 | u32 rx_stat_grbyt_lo; | |
2308 | u32 rx_stat_grbyt_hi; | |
2309 | u32 rx_stat_grund_lo; | |
2310 | u32 rx_stat_grund_hi; | |
2311 | u32 rx_stat_grfrg_lo; | |
2312 | u32 rx_stat_grfrg_hi; | |
2313 | u32 rx_stat_grerb_lo; | |
2314 | u32 rx_stat_grerb_hi; | |
2315 | u32 rx_stat_grfre_lo; | |
2316 | u32 rx_stat_grfre_hi; | |
2317 | u32 rx_stat_gripj_lo; | |
2318 | u32 rx_stat_gripj_hi; | |
bb2a0f7a YG |
2319 | }; |
2320 | ||
f2e0899f DK |
2321 | struct bmac2_stats { |
2322 | u32 tx_stat_gtpk_lo; /* gtpok */ | |
2323 | u32 tx_stat_gtpk_hi; /* gtpok */ | |
2324 | u32 tx_stat_gtxpf_lo; /* gtpf */ | |
2325 | u32 tx_stat_gtxpf_hi; /* gtpf */ | |
2326 | u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ | |
2327 | u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ | |
2328 | u32 tx_stat_gtfcs_lo; | |
2329 | u32 tx_stat_gtfcs_hi; | |
2330 | u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ | |
2331 | u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ | |
2332 | u32 tx_stat_gtmca_lo; | |
2333 | u32 tx_stat_gtmca_hi; | |
2334 | u32 tx_stat_gtbca_lo; | |
2335 | u32 tx_stat_gtbca_hi; | |
2336 | u32 tx_stat_gtovr_lo; | |
2337 | u32 tx_stat_gtovr_hi; | |
2338 | u32 tx_stat_gtfrg_lo; | |
2339 | u32 tx_stat_gtfrg_hi; | |
2340 | u32 tx_stat_gtpkt1_lo; /* gtpkt */ | |
2341 | u32 tx_stat_gtpkt1_hi; /* gtpkt */ | |
2342 | u32 tx_stat_gt64_lo; | |
2343 | u32 tx_stat_gt64_hi; | |
2344 | u32 tx_stat_gt127_lo; | |
2345 | u32 tx_stat_gt127_hi; | |
2346 | u32 tx_stat_gt255_lo; | |
2347 | u32 tx_stat_gt255_hi; | |
2348 | u32 tx_stat_gt511_lo; | |
2349 | u32 tx_stat_gt511_hi; | |
2350 | u32 tx_stat_gt1023_lo; | |
2351 | u32 tx_stat_gt1023_hi; | |
2352 | u32 tx_stat_gt1518_lo; | |
2353 | u32 tx_stat_gt1518_hi; | |
2354 | u32 tx_stat_gt2047_lo; | |
2355 | u32 tx_stat_gt2047_hi; | |
2356 | u32 tx_stat_gt4095_lo; | |
2357 | u32 tx_stat_gt4095_hi; | |
2358 | u32 tx_stat_gt9216_lo; | |
2359 | u32 tx_stat_gt9216_hi; | |
2360 | u32 tx_stat_gt16383_lo; | |
2361 | u32 tx_stat_gt16383_hi; | |
2362 | u32 tx_stat_gtmax_lo; | |
2363 | u32 tx_stat_gtmax_hi; | |
2364 | u32 tx_stat_gtufl_lo; | |
2365 | u32 tx_stat_gtufl_hi; | |
2366 | u32 tx_stat_gterr_lo; | |
2367 | u32 tx_stat_gterr_hi; | |
2368 | u32 tx_stat_gtbyt_lo; | |
2369 | u32 tx_stat_gtbyt_hi; | |
2370 | ||
2371 | u32 rx_stat_gr64_lo; | |
2372 | u32 rx_stat_gr64_hi; | |
2373 | u32 rx_stat_gr127_lo; | |
2374 | u32 rx_stat_gr127_hi; | |
2375 | u32 rx_stat_gr255_lo; | |
2376 | u32 rx_stat_gr255_hi; | |
2377 | u32 rx_stat_gr511_lo; | |
2378 | u32 rx_stat_gr511_hi; | |
2379 | u32 rx_stat_gr1023_lo; | |
2380 | u32 rx_stat_gr1023_hi; | |
2381 | u32 rx_stat_gr1518_lo; | |
2382 | u32 rx_stat_gr1518_hi; | |
2383 | u32 rx_stat_gr2047_lo; | |
2384 | u32 rx_stat_gr2047_hi; | |
2385 | u32 rx_stat_gr4095_lo; | |
2386 | u32 rx_stat_gr4095_hi; | |
2387 | u32 rx_stat_gr9216_lo; | |
2388 | u32 rx_stat_gr9216_hi; | |
2389 | u32 rx_stat_gr16383_lo; | |
2390 | u32 rx_stat_gr16383_hi; | |
2391 | u32 rx_stat_grmax_lo; | |
2392 | u32 rx_stat_grmax_hi; | |
2393 | u32 rx_stat_grpkt_lo; | |
2394 | u32 rx_stat_grpkt_hi; | |
2395 | u32 rx_stat_grfcs_lo; | |
2396 | u32 rx_stat_grfcs_hi; | |
2397 | u32 rx_stat_gruca_lo; | |
2398 | u32 rx_stat_gruca_hi; | |
2399 | u32 rx_stat_grmca_lo; | |
2400 | u32 rx_stat_grmca_hi; | |
2401 | u32 rx_stat_grbca_lo; | |
2402 | u32 rx_stat_grbca_hi; | |
2403 | u32 rx_stat_grxpf_lo; /* grpf */ | |
2404 | u32 rx_stat_grxpf_hi; /* grpf */ | |
2405 | u32 rx_stat_grpp_lo; | |
2406 | u32 rx_stat_grpp_hi; | |
2407 | u32 rx_stat_grxuo_lo; /* gruo */ | |
2408 | u32 rx_stat_grxuo_hi; /* gruo */ | |
2409 | u32 rx_stat_grjbr_lo; | |
2410 | u32 rx_stat_grjbr_hi; | |
2411 | u32 rx_stat_grovr_lo; | |
2412 | u32 rx_stat_grovr_hi; | |
2413 | u32 rx_stat_grxcf_lo; /* grcf */ | |
2414 | u32 rx_stat_grxcf_hi; /* grcf */ | |
2415 | u32 rx_stat_grflr_lo; | |
2416 | u32 rx_stat_grflr_hi; | |
2417 | u32 rx_stat_grpok_lo; | |
2418 | u32 rx_stat_grpok_hi; | |
2419 | u32 rx_stat_grmeg_lo; | |
2420 | u32 rx_stat_grmeg_hi; | |
2421 | u32 rx_stat_grmeb_lo; | |
2422 | u32 rx_stat_grmeb_hi; | |
2423 | u32 rx_stat_grbyt_lo; | |
2424 | u32 rx_stat_grbyt_hi; | |
2425 | u32 rx_stat_grund_lo; | |
2426 | u32 rx_stat_grund_hi; | |
2427 | u32 rx_stat_grfrg_lo; | |
2428 | u32 rx_stat_grfrg_hi; | |
2429 | u32 rx_stat_grerb_lo; /* grerrbyt */ | |
2430 | u32 rx_stat_grerb_hi; /* grerrbyt */ | |
2431 | u32 rx_stat_grfre_lo; /* grfrerr */ | |
2432 | u32 rx_stat_grfre_hi; /* grfrerr */ | |
2433 | u32 rx_stat_gripj_lo; | |
2434 | u32 rx_stat_gripj_hi; | |
2435 | }; | |
bb2a0f7a | 2436 | |
619c5cb6 VZ |
2437 | struct mstat_stats { |
2438 | struct { | |
2439 | /* OTE MSTAT on E3 has a bug where this register's contents are | |
2440 | * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp | |
2441 | */ | |
2442 | u32 tx_gtxpok_lo; | |
2443 | u32 tx_gtxpok_hi; | |
2444 | u32 tx_gtxpf_lo; | |
2445 | u32 tx_gtxpf_hi; | |
2446 | u32 tx_gtxpp_lo; | |
2447 | u32 tx_gtxpp_hi; | |
2448 | u32 tx_gtfcs_lo; | |
2449 | u32 tx_gtfcs_hi; | |
2450 | u32 tx_gtuca_lo; | |
2451 | u32 tx_gtuca_hi; | |
2452 | u32 tx_gtmca_lo; | |
2453 | u32 tx_gtmca_hi; | |
2454 | u32 tx_gtgca_lo; | |
2455 | u32 tx_gtgca_hi; | |
2456 | u32 tx_gtpkt_lo; | |
2457 | u32 tx_gtpkt_hi; | |
2458 | u32 tx_gt64_lo; | |
2459 | u32 tx_gt64_hi; | |
2460 | u32 tx_gt127_lo; | |
2461 | u32 tx_gt127_hi; | |
2462 | u32 tx_gt255_lo; | |
2463 | u32 tx_gt255_hi; | |
2464 | u32 tx_gt511_lo; | |
2465 | u32 tx_gt511_hi; | |
2466 | u32 tx_gt1023_lo; | |
2467 | u32 tx_gt1023_hi; | |
2468 | u32 tx_gt1518_lo; | |
2469 | u32 tx_gt1518_hi; | |
2470 | u32 tx_gt2047_lo; | |
2471 | u32 tx_gt2047_hi; | |
2472 | u32 tx_gt4095_lo; | |
2473 | u32 tx_gt4095_hi; | |
2474 | u32 tx_gt9216_lo; | |
2475 | u32 tx_gt9216_hi; | |
2476 | u32 tx_gt16383_lo; | |
2477 | u32 tx_gt16383_hi; | |
2478 | u32 tx_gtufl_lo; | |
2479 | u32 tx_gtufl_hi; | |
2480 | u32 tx_gterr_lo; | |
2481 | u32 tx_gterr_hi; | |
2482 | u32 tx_gtbyt_lo; | |
2483 | u32 tx_gtbyt_hi; | |
2484 | u32 tx_collisions_lo; | |
2485 | u32 tx_collisions_hi; | |
2486 | u32 tx_singlecollision_lo; | |
2487 | u32 tx_singlecollision_hi; | |
2488 | u32 tx_multiplecollisions_lo; | |
2489 | u32 tx_multiplecollisions_hi; | |
2490 | u32 tx_deferred_lo; | |
2491 | u32 tx_deferred_hi; | |
2492 | u32 tx_excessivecollisions_lo; | |
2493 | u32 tx_excessivecollisions_hi; | |
2494 | u32 tx_latecollisions_lo; | |
2495 | u32 tx_latecollisions_hi; | |
2496 | } stats_tx; | |
2497 | ||
2498 | struct { | |
2499 | u32 rx_gr64_lo; | |
2500 | u32 rx_gr64_hi; | |
2501 | u32 rx_gr127_lo; | |
2502 | u32 rx_gr127_hi; | |
2503 | u32 rx_gr255_lo; | |
2504 | u32 rx_gr255_hi; | |
2505 | u32 rx_gr511_lo; | |
2506 | u32 rx_gr511_hi; | |
2507 | u32 rx_gr1023_lo; | |
2508 | u32 rx_gr1023_hi; | |
2509 | u32 rx_gr1518_lo; | |
2510 | u32 rx_gr1518_hi; | |
2511 | u32 rx_gr2047_lo; | |
2512 | u32 rx_gr2047_hi; | |
2513 | u32 rx_gr4095_lo; | |
2514 | u32 rx_gr4095_hi; | |
2515 | u32 rx_gr9216_lo; | |
2516 | u32 rx_gr9216_hi; | |
2517 | u32 rx_gr16383_lo; | |
2518 | u32 rx_gr16383_hi; | |
2519 | u32 rx_grpkt_lo; | |
2520 | u32 rx_grpkt_hi; | |
2521 | u32 rx_grfcs_lo; | |
2522 | u32 rx_grfcs_hi; | |
2523 | u32 rx_gruca_lo; | |
2524 | u32 rx_gruca_hi; | |
2525 | u32 rx_grmca_lo; | |
2526 | u32 rx_grmca_hi; | |
2527 | u32 rx_grbca_lo; | |
2528 | u32 rx_grbca_hi; | |
2529 | u32 rx_grxpf_lo; | |
2530 | u32 rx_grxpf_hi; | |
2531 | u32 rx_grxpp_lo; | |
2532 | u32 rx_grxpp_hi; | |
2533 | u32 rx_grxuo_lo; | |
2534 | u32 rx_grxuo_hi; | |
2535 | u32 rx_grovr_lo; | |
2536 | u32 rx_grovr_hi; | |
2537 | u32 rx_grxcf_lo; | |
2538 | u32 rx_grxcf_hi; | |
2539 | u32 rx_grflr_lo; | |
2540 | u32 rx_grflr_hi; | |
2541 | u32 rx_grpok_lo; | |
2542 | u32 rx_grpok_hi; | |
2543 | u32 rx_grbyt_lo; | |
2544 | u32 rx_grbyt_hi; | |
2545 | u32 rx_grund_lo; | |
2546 | u32 rx_grund_hi; | |
2547 | u32 rx_grfrg_lo; | |
2548 | u32 rx_grfrg_hi; | |
2549 | u32 rx_grerb_lo; | |
2550 | u32 rx_grerb_hi; | |
2551 | u32 rx_grfre_lo; | |
2552 | u32 rx_grfre_hi; | |
2553 | ||
2554 | u32 rx_alignmenterrors_lo; | |
2555 | u32 rx_alignmenterrors_hi; | |
2556 | u32 rx_falsecarrier_lo; | |
2557 | u32 rx_falsecarrier_hi; | |
2558 | u32 rx_llfcmsgcnt_lo; | |
2559 | u32 rx_llfcmsgcnt_hi; | |
2560 | } stats_rx; | |
2561 | }; | |
2562 | ||
bb2a0f7a | 2563 | union mac_stats { |
619c5cb6 VZ |
2564 | struct emac_stats emac_stats; |
2565 | struct bmac1_stats bmac1_stats; | |
2566 | struct bmac2_stats bmac2_stats; | |
2567 | struct mstat_stats mstat_stats; | |
bb2a0f7a YG |
2568 | }; |
2569 | ||
2570 | ||
2571 | struct mac_stx { | |
619c5cb6 VZ |
2572 | /* in_bad_octets */ |
2573 | u32 rx_stat_ifhcinbadoctets_hi; | |
2574 | u32 rx_stat_ifhcinbadoctets_lo; | |
2575 | ||
2576 | /* out_bad_octets */ | |
2577 | u32 tx_stat_ifhcoutbadoctets_hi; | |
2578 | u32 tx_stat_ifhcoutbadoctets_lo; | |
2579 | ||
2580 | /* crc_receive_errors */ | |
2581 | u32 rx_stat_dot3statsfcserrors_hi; | |
2582 | u32 rx_stat_dot3statsfcserrors_lo; | |
2583 | /* alignment_errors */ | |
2584 | u32 rx_stat_dot3statsalignmenterrors_hi; | |
2585 | u32 rx_stat_dot3statsalignmenterrors_lo; | |
2586 | /* carrier_sense_errors */ | |
2587 | u32 rx_stat_dot3statscarriersenseerrors_hi; | |
2588 | u32 rx_stat_dot3statscarriersenseerrors_lo; | |
2589 | /* false_carrier_detections */ | |
2590 | u32 rx_stat_falsecarriererrors_hi; | |
2591 | u32 rx_stat_falsecarriererrors_lo; | |
2592 | ||
2593 | /* runt_packets_received */ | |
2594 | u32 rx_stat_etherstatsundersizepkts_hi; | |
2595 | u32 rx_stat_etherstatsundersizepkts_lo; | |
2596 | /* jabber_packets_received */ | |
2597 | u32 rx_stat_dot3statsframestoolong_hi; | |
2598 | u32 rx_stat_dot3statsframestoolong_lo; | |
2599 | ||
2600 | /* error_runt_packets_received */ | |
2601 | u32 rx_stat_etherstatsfragments_hi; | |
2602 | u32 rx_stat_etherstatsfragments_lo; | |
2603 | /* error_jabber_packets_received */ | |
2604 | u32 rx_stat_etherstatsjabbers_hi; | |
2605 | u32 rx_stat_etherstatsjabbers_lo; | |
2606 | ||
2607 | /* control_frames_received */ | |
2608 | u32 rx_stat_maccontrolframesreceived_hi; | |
2609 | u32 rx_stat_maccontrolframesreceived_lo; | |
2610 | u32 rx_stat_mac_xpf_hi; | |
2611 | u32 rx_stat_mac_xpf_lo; | |
2612 | u32 rx_stat_mac_xcf_hi; | |
2613 | u32 rx_stat_mac_xcf_lo; | |
2614 | ||
2615 | /* xoff_state_entered */ | |
2616 | u32 rx_stat_xoffstateentered_hi; | |
2617 | u32 rx_stat_xoffstateentered_lo; | |
2618 | /* pause_xon_frames_received */ | |
2619 | u32 rx_stat_xonpauseframesreceived_hi; | |
2620 | u32 rx_stat_xonpauseframesreceived_lo; | |
2621 | /* pause_xoff_frames_received */ | |
2622 | u32 rx_stat_xoffpauseframesreceived_hi; | |
2623 | u32 rx_stat_xoffpauseframesreceived_lo; | |
2624 | /* pause_xon_frames_transmitted */ | |
2625 | u32 tx_stat_outxonsent_hi; | |
2626 | u32 tx_stat_outxonsent_lo; | |
2627 | /* pause_xoff_frames_transmitted */ | |
2628 | u32 tx_stat_outxoffsent_hi; | |
2629 | u32 tx_stat_outxoffsent_lo; | |
2630 | /* flow_control_done */ | |
2631 | u32 tx_stat_flowcontroldone_hi; | |
2632 | u32 tx_stat_flowcontroldone_lo; | |
2633 | ||
2634 | /* ether_stats_collisions */ | |
2635 | u32 tx_stat_etherstatscollisions_hi; | |
2636 | u32 tx_stat_etherstatscollisions_lo; | |
2637 | /* single_collision_transmit_frames */ | |
2638 | u32 tx_stat_dot3statssinglecollisionframes_hi; | |
2639 | u32 tx_stat_dot3statssinglecollisionframes_lo; | |
2640 | /* multiple_collision_transmit_frames */ | |
2641 | u32 tx_stat_dot3statsmultiplecollisionframes_hi; | |
2642 | u32 tx_stat_dot3statsmultiplecollisionframes_lo; | |
2643 | /* deferred_transmissions */ | |
2644 | u32 tx_stat_dot3statsdeferredtransmissions_hi; | |
2645 | u32 tx_stat_dot3statsdeferredtransmissions_lo; | |
2646 | /* excessive_collision_frames */ | |
2647 | u32 tx_stat_dot3statsexcessivecollisions_hi; | |
2648 | u32 tx_stat_dot3statsexcessivecollisions_lo; | |
2649 | /* late_collision_frames */ | |
2650 | u32 tx_stat_dot3statslatecollisions_hi; | |
2651 | u32 tx_stat_dot3statslatecollisions_lo; | |
2652 | ||
2653 | /* frames_transmitted_64_bytes */ | |
2654 | u32 tx_stat_etherstatspkts64octets_hi; | |
2655 | u32 tx_stat_etherstatspkts64octets_lo; | |
2656 | /* frames_transmitted_65_127_bytes */ | |
2657 | u32 tx_stat_etherstatspkts65octetsto127octets_hi; | |
2658 | u32 tx_stat_etherstatspkts65octetsto127octets_lo; | |
2659 | /* frames_transmitted_128_255_bytes */ | |
2660 | u32 tx_stat_etherstatspkts128octetsto255octets_hi; | |
2661 | u32 tx_stat_etherstatspkts128octetsto255octets_lo; | |
2662 | /* frames_transmitted_256_511_bytes */ | |
2663 | u32 tx_stat_etherstatspkts256octetsto511octets_hi; | |
2664 | u32 tx_stat_etherstatspkts256octetsto511octets_lo; | |
2665 | /* frames_transmitted_512_1023_bytes */ | |
2666 | u32 tx_stat_etherstatspkts512octetsto1023octets_hi; | |
2667 | u32 tx_stat_etherstatspkts512octetsto1023octets_lo; | |
2668 | /* frames_transmitted_1024_1522_bytes */ | |
2669 | u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; | |
2670 | u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; | |
2671 | /* frames_transmitted_1523_9022_bytes */ | |
2672 | u32 tx_stat_etherstatspktsover1522octets_hi; | |
2673 | u32 tx_stat_etherstatspktsover1522octets_lo; | |
2674 | u32 tx_stat_mac_2047_hi; | |
2675 | u32 tx_stat_mac_2047_lo; | |
2676 | u32 tx_stat_mac_4095_hi; | |
2677 | u32 tx_stat_mac_4095_lo; | |
2678 | u32 tx_stat_mac_9216_hi; | |
2679 | u32 tx_stat_mac_9216_lo; | |
2680 | u32 tx_stat_mac_16383_hi; | |
2681 | u32 tx_stat_mac_16383_lo; | |
2682 | ||
2683 | /* internal_mac_transmit_errors */ | |
2684 | u32 tx_stat_dot3statsinternalmactransmiterrors_hi; | |
2685 | u32 tx_stat_dot3statsinternalmactransmiterrors_lo; | |
2686 | ||
2687 | /* if_out_discards */ | |
2688 | u32 tx_stat_mac_ufl_hi; | |
2689 | u32 tx_stat_mac_ufl_lo; | |
2690 | }; | |
2691 | ||
2692 | ||
2693 | #define MAC_STX_IDX_MAX 2 | |
bb2a0f7a YG |
2694 | |
2695 | struct host_port_stats { | |
0e898dd7 | 2696 | u32 host_port_stats_counter; |
bb2a0f7a | 2697 | |
619c5cb6 | 2698 | struct mac_stx mac_stx[MAC_STX_IDX_MAX]; |
bb2a0f7a | 2699 | |
619c5cb6 VZ |
2700 | u32 brb_drop_hi; |
2701 | u32 brb_drop_lo; | |
bb2a0f7a | 2702 | |
0e898dd7 BW |
2703 | u32 not_used; /* obsolete */ |
2704 | u32 pfc_frames_tx_hi; | |
2705 | u32 pfc_frames_tx_lo; | |
2706 | u32 pfc_frames_rx_hi; | |
2707 | u32 pfc_frames_rx_lo; | |
c8c60d88 YM |
2708 | |
2709 | u32 eee_lpi_count_hi; | |
2710 | u32 eee_lpi_count_lo; | |
bb2a0f7a YG |
2711 | }; |
2712 | ||
2713 | ||
2714 | struct host_func_stats { | |
619c5cb6 | 2715 | u32 host_func_stats_start; |
bb2a0f7a | 2716 | |
619c5cb6 VZ |
2717 | u32 total_bytes_received_hi; |
2718 | u32 total_bytes_received_lo; | |
bb2a0f7a | 2719 | |
619c5cb6 VZ |
2720 | u32 total_bytes_transmitted_hi; |
2721 | u32 total_bytes_transmitted_lo; | |
bb2a0f7a | 2722 | |
619c5cb6 VZ |
2723 | u32 total_unicast_packets_received_hi; |
2724 | u32 total_unicast_packets_received_lo; | |
bb2a0f7a | 2725 | |
619c5cb6 VZ |
2726 | u32 total_multicast_packets_received_hi; |
2727 | u32 total_multicast_packets_received_lo; | |
bb2a0f7a | 2728 | |
619c5cb6 VZ |
2729 | u32 total_broadcast_packets_received_hi; |
2730 | u32 total_broadcast_packets_received_lo; | |
bb2a0f7a | 2731 | |
619c5cb6 VZ |
2732 | u32 total_unicast_packets_transmitted_hi; |
2733 | u32 total_unicast_packets_transmitted_lo; | |
bb2a0f7a | 2734 | |
619c5cb6 VZ |
2735 | u32 total_multicast_packets_transmitted_hi; |
2736 | u32 total_multicast_packets_transmitted_lo; | |
bb2a0f7a | 2737 | |
619c5cb6 VZ |
2738 | u32 total_broadcast_packets_transmitted_hi; |
2739 | u32 total_broadcast_packets_transmitted_lo; | |
bb2a0f7a | 2740 | |
619c5cb6 VZ |
2741 | u32 valid_bytes_received_hi; |
2742 | u32 valid_bytes_received_lo; | |
bb2a0f7a | 2743 | |
619c5cb6 | 2744 | u32 host_func_stats_end; |
bb2a0f7a | 2745 | }; |
34f80b04 | 2746 | |
619c5cb6 VZ |
2747 | /* VIC definitions */ |
2748 | #define VICSTATST_UIF_INDEX 2 | |
34f80b04 | 2749 | |
a3348722 BW |
2750 | |
2751 | /* stats collected for afex. | |
2752 | * NOTE: structure is exactly as expected to be received by the switch. | |
2753 | * order must remain exactly as is unless protocol changes ! | |
2754 | */ | |
2755 | struct afex_stats { | |
2756 | u32 tx_unicast_frames_hi; | |
2757 | u32 tx_unicast_frames_lo; | |
2758 | u32 tx_unicast_bytes_hi; | |
2759 | u32 tx_unicast_bytes_lo; | |
2760 | u32 tx_multicast_frames_hi; | |
2761 | u32 tx_multicast_frames_lo; | |
2762 | u32 tx_multicast_bytes_hi; | |
2763 | u32 tx_multicast_bytes_lo; | |
2764 | u32 tx_broadcast_frames_hi; | |
2765 | u32 tx_broadcast_frames_lo; | |
2766 | u32 tx_broadcast_bytes_hi; | |
2767 | u32 tx_broadcast_bytes_lo; | |
2768 | u32 tx_frames_discarded_hi; | |
2769 | u32 tx_frames_discarded_lo; | |
2770 | u32 tx_frames_dropped_hi; | |
2771 | u32 tx_frames_dropped_lo; | |
2772 | ||
2773 | u32 rx_unicast_frames_hi; | |
2774 | u32 rx_unicast_frames_lo; | |
2775 | u32 rx_unicast_bytes_hi; | |
2776 | u32 rx_unicast_bytes_lo; | |
2777 | u32 rx_multicast_frames_hi; | |
2778 | u32 rx_multicast_frames_lo; | |
2779 | u32 rx_multicast_bytes_hi; | |
2780 | u32 rx_multicast_bytes_lo; | |
2781 | u32 rx_broadcast_frames_hi; | |
2782 | u32 rx_broadcast_frames_lo; | |
2783 | u32 rx_broadcast_bytes_hi; | |
2784 | u32 rx_broadcast_bytes_lo; | |
2785 | u32 rx_frames_discarded_hi; | |
2786 | u32 rx_frames_discarded_lo; | |
2787 | u32 rx_frames_dropped_hi; | |
2788 | u32 rx_frames_dropped_lo; | |
2789 | }; | |
2790 | ||
619c5cb6 | 2791 | #define BCM_5710_FW_MAJOR_VERSION 7 |
96bed4b9 YM |
2792 | #define BCM_5710_FW_MINOR_VERSION 8 |
2793 | #define BCM_5710_FW_REVISION_VERSION 2 | |
a3348722 | 2794 | #define BCM_5710_FW_ENGINEERING_VERSION 0 |
a2fbb9ea ET |
2795 | #define BCM_5710_FW_COMPILE_FLAGS 1 |
2796 | ||
2797 | ||
2798 | /* | |
2799 | * attention bits | |
2800 | */ | |
523224a3 | 2801 | struct atten_sp_status_block { |
4781bfad EG |
2802 | __le32 attn_bits; |
2803 | __le32 attn_bits_ack; | |
a2fbb9ea ET |
2804 | u8 status_block_id; |
2805 | u8 reserved0; | |
4781bfad EG |
2806 | __le16 attn_bits_index; |
2807 | __le32 reserved1; | |
a2fbb9ea ET |
2808 | }; |
2809 | ||
2810 | ||
2811 | /* | |
619c5cb6 | 2812 | * The eth aggregative context of Cstorm |
a2fbb9ea | 2813 | */ |
619c5cb6 VZ |
2814 | struct cstorm_eth_ag_context { |
2815 | u32 __reserved0[10]; | |
a2fbb9ea ET |
2816 | }; |
2817 | ||
619c5cb6 | 2818 | |
a2fbb9ea | 2819 | /* |
619c5cb6 | 2820 | * dmae command structure |
a2fbb9ea | 2821 | */ |
619c5cb6 VZ |
2822 | struct dmae_command { |
2823 | u32 opcode; | |
2824 | #define DMAE_COMMAND_SRC (0x1<<0) | |
2825 | #define DMAE_COMMAND_SRC_SHIFT 0 | |
2826 | #define DMAE_COMMAND_DST (0x3<<1) | |
2827 | #define DMAE_COMMAND_DST_SHIFT 1 | |
2828 | #define DMAE_COMMAND_C_DST (0x1<<3) | |
2829 | #define DMAE_COMMAND_C_DST_SHIFT 3 | |
2830 | #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) | |
2831 | #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 | |
2832 | #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) | |
2833 | #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 | |
2834 | #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) | |
2835 | #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 | |
2836 | #define DMAE_COMMAND_ENDIANITY (0x3<<9) | |
2837 | #define DMAE_COMMAND_ENDIANITY_SHIFT 9 | |
2838 | #define DMAE_COMMAND_PORT (0x1<<11) | |
2839 | #define DMAE_COMMAND_PORT_SHIFT 11 | |
2840 | #define DMAE_COMMAND_CRC_RESET (0x1<<12) | |
2841 | #define DMAE_COMMAND_CRC_RESET_SHIFT 12 | |
2842 | #define DMAE_COMMAND_SRC_RESET (0x1<<13) | |
2843 | #define DMAE_COMMAND_SRC_RESET_SHIFT 13 | |
2844 | #define DMAE_COMMAND_DST_RESET (0x1<<14) | |
2845 | #define DMAE_COMMAND_DST_RESET_SHIFT 14 | |
2846 | #define DMAE_COMMAND_E1HVN (0x3<<15) | |
2847 | #define DMAE_COMMAND_E1HVN_SHIFT 15 | |
2848 | #define DMAE_COMMAND_DST_VN (0x3<<17) | |
2849 | #define DMAE_COMMAND_DST_VN_SHIFT 17 | |
2850 | #define DMAE_COMMAND_C_FUNC (0x1<<19) | |
2851 | #define DMAE_COMMAND_C_FUNC_SHIFT 19 | |
2852 | #define DMAE_COMMAND_ERR_POLICY (0x3<<20) | |
2853 | #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 | |
2854 | #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) | |
2855 | #define DMAE_COMMAND_RESERVED0_SHIFT 22 | |
2856 | u32 src_addr_lo; | |
2857 | u32 src_addr_hi; | |
2858 | u32 dst_addr_lo; | |
2859 | u32 dst_addr_hi; | |
a2fbb9ea | 2860 | #if defined(__BIG_ENDIAN) |
619c5cb6 VZ |
2861 | u16 opcode_iov; |
2862 | #define DMAE_COMMAND_SRC_VFID (0x3F<<0) | |
2863 | #define DMAE_COMMAND_SRC_VFID_SHIFT 0 | |
2864 | #define DMAE_COMMAND_SRC_VFPF (0x1<<6) | |
2865 | #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 | |
2866 | #define DMAE_COMMAND_RESERVED1 (0x1<<7) | |
2867 | #define DMAE_COMMAND_RESERVED1_SHIFT 7 | |
2868 | #define DMAE_COMMAND_DST_VFID (0x3F<<8) | |
2869 | #define DMAE_COMMAND_DST_VFID_SHIFT 8 | |
2870 | #define DMAE_COMMAND_DST_VFPF (0x1<<14) | |
2871 | #define DMAE_COMMAND_DST_VFPF_SHIFT 14 | |
2872 | #define DMAE_COMMAND_RESERVED2 (0x1<<15) | |
2873 | #define DMAE_COMMAND_RESERVED2_SHIFT 15 | |
2874 | u16 len; | |
a2fbb9ea | 2875 | #elif defined(__LITTLE_ENDIAN) |
619c5cb6 VZ |
2876 | u16 len; |
2877 | u16 opcode_iov; | |
2878 | #define DMAE_COMMAND_SRC_VFID (0x3F<<0) | |
2879 | #define DMAE_COMMAND_SRC_VFID_SHIFT 0 | |
2880 | #define DMAE_COMMAND_SRC_VFPF (0x1<<6) | |
2881 | #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 | |
2882 | #define DMAE_COMMAND_RESERVED1 (0x1<<7) | |
2883 | #define DMAE_COMMAND_RESERVED1_SHIFT 7 | |
2884 | #define DMAE_COMMAND_DST_VFID (0x3F<<8) | |
2885 | #define DMAE_COMMAND_DST_VFID_SHIFT 8 | |
2886 | #define DMAE_COMMAND_DST_VFPF (0x1<<14) | |
2887 | #define DMAE_COMMAND_DST_VFPF_SHIFT 14 | |
2888 | #define DMAE_COMMAND_RESERVED2 (0x1<<15) | |
2889 | #define DMAE_COMMAND_RESERVED2_SHIFT 15 | |
a2fbb9ea | 2890 | #endif |
619c5cb6 VZ |
2891 | u32 comp_addr_lo; |
2892 | u32 comp_addr_hi; | |
2893 | u32 comp_val; | |
2894 | u32 crc32; | |
2895 | u32 crc32_c; | |
2896 | #if defined(__BIG_ENDIAN) | |
2897 | u16 crc16_c; | |
2898 | u16 crc16; | |
2899 | #elif defined(__LITTLE_ENDIAN) | |
2900 | u16 crc16; | |
2901 | u16 crc16_c; | |
2902 | #endif | |
2903 | #if defined(__BIG_ENDIAN) | |
2904 | u16 reserved3; | |
2905 | u16 crc_t10; | |
2906 | #elif defined(__LITTLE_ENDIAN) | |
2907 | u16 crc_t10; | |
2908 | u16 reserved3; | |
2909 | #endif | |
2910 | #if defined(__BIG_ENDIAN) | |
2911 | u16 xsum8; | |
2912 | u16 xsum16; | |
2913 | #elif defined(__LITTLE_ENDIAN) | |
2914 | u16 xsum16; | |
2915 | u16 xsum8; | |
2916 | #endif | |
2917 | }; | |
2918 | ||
2919 | ||
ca00392c | 2920 | /* |
619c5cb6 | 2921 | * common data for all protocols |
ca00392c | 2922 | */ |
619c5cb6 VZ |
2923 | struct doorbell_hdr { |
2924 | u8 header; | |
2925 | #define DOORBELL_HDR_RX (0x1<<0) | |
2926 | #define DOORBELL_HDR_RX_SHIFT 0 | |
2927 | #define DOORBELL_HDR_DB_TYPE (0x1<<1) | |
2928 | #define DOORBELL_HDR_DB_TYPE_SHIFT 1 | |
2929 | #define DOORBELL_HDR_DPM_SIZE (0x3<<2) | |
2930 | #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 | |
2931 | #define DOORBELL_HDR_CONN_TYPE (0xF<<4) | |
2932 | #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 | |
2933 | }; | |
2934 | ||
2935 | /* | |
2936 | * Ethernet doorbell | |
2937 | */ | |
2938 | struct eth_tx_doorbell { | |
ca00392c | 2939 | #if defined(__BIG_ENDIAN) |
619c5cb6 VZ |
2940 | u16 npackets; |
2941 | u8 params; | |
2942 | #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) | |
2943 | #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 | |
2944 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) | |
2945 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 | |
2946 | #define ETH_TX_DOORBELL_SPARE (0x1<<7) | |
2947 | #define ETH_TX_DOORBELL_SPARE_SHIFT 7 | |
2948 | struct doorbell_hdr hdr; | |
ca00392c | 2949 | #elif defined(__LITTLE_ENDIAN) |
619c5cb6 VZ |
2950 | struct doorbell_hdr hdr; |
2951 | u8 params; | |
2952 | #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) | |
2953 | #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 | |
2954 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) | |
2955 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 | |
2956 | #define ETH_TX_DOORBELL_SPARE (0x1<<7) | |
2957 | #define ETH_TX_DOORBELL_SPARE_SHIFT 7 | |
2958 | u16 npackets; | |
ca00392c EG |
2959 | #endif |
2960 | }; | |
2961 | ||
2962 | ||
a2fbb9ea | 2963 | /* |
523224a3 DK |
2964 | * 3 lines. status block |
2965 | */ | |
2966 | struct hc_status_block_e1x { | |
2967 | __le16 index_values[HC_SB_MAX_INDICES_E1X]; | |
2968 | __le16 running_index[HC_SB_MAX_SM]; | |
619c5cb6 | 2969 | __le32 rsrv[11]; |
523224a3 DK |
2970 | }; |
2971 | ||
2972 | /* | |
2973 | * host status block | |
2974 | */ | |
2975 | struct host_hc_status_block_e1x { | |
2976 | struct hc_status_block_e1x sb; | |
2977 | }; | |
2978 | ||
2979 | ||
2980 | /* | |
2981 | * 3 lines. status block | |
2982 | */ | |
2983 | struct hc_status_block_e2 { | |
2984 | __le16 index_values[HC_SB_MAX_INDICES_E2]; | |
2985 | __le16 running_index[HC_SB_MAX_SM]; | |
619c5cb6 | 2986 | __le32 reserved[11]; |
523224a3 DK |
2987 | }; |
2988 | ||
2989 | /* | |
2990 | * host status block | |
2991 | */ | |
2992 | struct host_hc_status_block_e2 { | |
2993 | struct hc_status_block_e2 sb; | |
2994 | }; | |
2995 | ||
2996 | ||
2997 | /* | |
2998 | * 5 lines. slow-path status block | |
2999 | */ | |
3000 | struct hc_sp_status_block { | |
3001 | __le16 index_values[HC_SP_SB_MAX_INDICES]; | |
3002 | __le16 running_index; | |
3003 | __le16 rsrv; | |
3004 | u32 rsrv1; | |
3005 | }; | |
3006 | ||
3007 | /* | |
3008 | * host status block | |
3009 | */ | |
3010 | struct host_sp_status_block { | |
3011 | struct atten_sp_status_block atten_status_block; | |
3012 | struct hc_sp_status_block sp_sb; | |
3013 | }; | |
3014 | ||
3015 | ||
3016 | /* | |
3017 | * IGU driver acknowledgment register | |
a2fbb9ea ET |
3018 | */ |
3019 | struct igu_ack_register { | |
3020 | #if defined(__BIG_ENDIAN) | |
3021 | u16 sb_id_and_flags; | |
3022 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) | |
3023 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 | |
3024 | #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) | |
3025 | #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 | |
3026 | #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) | |
3027 | #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 | |
3028 | #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) | |
3029 | #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 | |
3030 | #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) | |
3031 | #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 | |
3032 | u16 status_block_index; | |
3033 | #elif defined(__LITTLE_ENDIAN) | |
3034 | u16 status_block_index; | |
3035 | u16 sb_id_and_flags; | |
3036 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) | |
3037 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 | |
3038 | #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) | |
3039 | #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 | |
3040 | #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) | |
3041 | #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 | |
3042 | #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) | |
3043 | #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 | |
3044 | #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) | |
3045 | #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 | |
3046 | #endif | |
3047 | }; | |
3048 | ||
3049 | ||
ca00392c EG |
3050 | /* |
3051 | * IGU driver acknowledgement register | |
3052 | */ | |
3053 | struct igu_backward_compatible { | |
3054 | u32 sb_id_and_flags; | |
3055 | #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) | |
3056 | #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 | |
3057 | #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) | |
3058 | #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 | |
3059 | #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) | |
3060 | #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 | |
3061 | #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) | |
3062 | #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 | |
3063 | #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) | |
3064 | #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 | |
3065 | #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) | |
3066 | #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 | |
3067 | u32 reserved_2; | |
3068 | }; | |
3069 | ||
3070 | ||
3071 | /* | |
3072 | * IGU driver acknowledgement register | |
3073 | */ | |
3074 | struct igu_regular { | |
3075 | u32 sb_id_and_flags; | |
3076 | #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) | |
3077 | #define IGU_REGULAR_SB_INDEX_SHIFT 0 | |
3078 | #define IGU_REGULAR_RESERVED0 (0x1<<20) | |
3079 | #define IGU_REGULAR_RESERVED0_SHIFT 20 | |
3080 | #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) | |
3081 | #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 | |
3082 | #define IGU_REGULAR_BUPDATE (0x1<<24) | |
3083 | #define IGU_REGULAR_BUPDATE_SHIFT 24 | |
3084 | #define IGU_REGULAR_ENABLE_INT (0x3<<25) | |
3085 | #define IGU_REGULAR_ENABLE_INT_SHIFT 25 | |
3086 | #define IGU_REGULAR_RESERVED_1 (0x1<<27) | |
3087 | #define IGU_REGULAR_RESERVED_1_SHIFT 27 | |
3088 | #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) | |
3089 | #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 | |
3090 | #define IGU_REGULAR_CLEANUP_SET (0x1<<30) | |
3091 | #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 | |
3092 | #define IGU_REGULAR_BCLEANUP (0x1<<31) | |
3093 | #define IGU_REGULAR_BCLEANUP_SHIFT 31 | |
3094 | u32 reserved_2; | |
3095 | }; | |
3096 | ||
3097 | /* | |
3098 | * IGU driver acknowledgement register | |
3099 | */ | |
3100 | union igu_consprod_reg { | |
3101 | struct igu_regular regular; | |
3102 | struct igu_backward_compatible backward_compatible; | |
3103 | }; | |
3104 | ||
3105 | ||
619c5cb6 VZ |
3106 | /* |
3107 | * Igu control commands | |
3108 | */ | |
3109 | enum igu_ctrl_cmd { | |
3110 | IGU_CTRL_CMD_TYPE_RD, | |
3111 | IGU_CTRL_CMD_TYPE_WR, | |
3112 | MAX_IGU_CTRL_CMD | |
3113 | }; | |
3114 | ||
3115 | ||
f2e0899f DK |
3116 | /* |
3117 | * Control register for the IGU command register | |
3118 | */ | |
3119 | struct igu_ctrl_reg { | |
3120 | u32 ctrl_data; | |
3121 | #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) | |
3122 | #define IGU_CTRL_REG_ADDRESS_SHIFT 0 | |
3123 | #define IGU_CTRL_REG_FID (0x7F<<12) | |
3124 | #define IGU_CTRL_REG_FID_SHIFT 12 | |
3125 | #define IGU_CTRL_REG_RESERVED (0x1<<19) | |
3126 | #define IGU_CTRL_REG_RESERVED_SHIFT 19 | |
3127 | #define IGU_CTRL_REG_TYPE (0x1<<20) | |
3128 | #define IGU_CTRL_REG_TYPE_SHIFT 20 | |
3129 | #define IGU_CTRL_REG_UNUSED (0x7FF<<21) | |
3130 | #define IGU_CTRL_REG_UNUSED_SHIFT 21 | |
3131 | }; | |
3132 | ||
3133 | ||
619c5cb6 VZ |
3134 | /* |
3135 | * Igu interrupt command | |
3136 | */ | |
3137 | enum igu_int_cmd { | |
3138 | IGU_INT_ENABLE, | |
3139 | IGU_INT_DISABLE, | |
3140 | IGU_INT_NOP, | |
3141 | IGU_INT_NOP2, | |
3142 | MAX_IGU_INT_CMD | |
3143 | }; | |
3144 | ||
3145 | ||
3146 | /* | |
3147 | * Igu segments | |
3148 | */ | |
3149 | enum igu_seg_access { | |
3150 | IGU_SEG_ACCESS_NORM, | |
3151 | IGU_SEG_ACCESS_DEF, | |
3152 | IGU_SEG_ACCESS_ATTN, | |
3153 | MAX_IGU_SEG_ACCESS | |
3154 | }; | |
3155 | ||
3156 | ||
a2fbb9ea ET |
3157 | /* |
3158 | * Parser parsing flags field | |
3159 | */ | |
3160 | struct parsing_flags { | |
4781bfad | 3161 | __le16 flags; |
a2fbb9ea ET |
3162 | #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) |
3163 | #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 | |
34f80b04 EG |
3164 | #define PARSING_FLAGS_VLAN (0x1<<1) |
3165 | #define PARSING_FLAGS_VLAN_SHIFT 1 | |
3166 | #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) | |
3167 | #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 | |
a2fbb9ea ET |
3168 | #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) |
3169 | #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 | |
3170 | #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) | |
3171 | #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 | |
3172 | #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) | |
3173 | #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 | |
3174 | #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) | |
3175 | #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 | |
3176 | #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) | |
3177 | #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 | |
3178 | #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) | |
3179 | #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 | |
3180 | #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) | |
3181 | #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 | |
3182 | #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) | |
3183 | #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 | |
3184 | #define PARSING_FLAGS_LLC_SNAP (0x1<<13) | |
3185 | #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 | |
3186 | #define PARSING_FLAGS_RESERVED0 (0x3<<14) | |
3187 | #define PARSING_FLAGS_RESERVED0_SHIFT 14 | |
3188 | }; | |
3189 | ||
3190 | ||
619c5cb6 VZ |
3191 | /* |
3192 | * Parsing flags for TCP ACK type | |
3193 | */ | |
3194 | enum prs_flags_ack_type { | |
3195 | PRS_FLAG_PUREACK_PIGGY, | |
3196 | PRS_FLAG_PUREACK_PURE, | |
3197 | MAX_PRS_FLAGS_ACK_TYPE | |
34f80b04 EG |
3198 | }; |
3199 | ||
3200 | ||
a2fbb9ea | 3201 | /* |
619c5cb6 | 3202 | * Parsing flags for Ethernet address type |
a2fbb9ea | 3203 | */ |
619c5cb6 VZ |
3204 | enum prs_flags_eth_addr_type { |
3205 | PRS_FLAG_ETHTYPE_NON_UNICAST, | |
3206 | PRS_FLAG_ETHTYPE_UNICAST, | |
3207 | MAX_PRS_FLAGS_ETH_ADDR_TYPE | |
a2fbb9ea ET |
3208 | }; |
3209 | ||
3210 | ||
619c5cb6 VZ |
3211 | /* |
3212 | * Parsing flags for over-ethernet protocol | |
3213 | */ | |
3214 | enum prs_flags_over_eth { | |
3215 | PRS_FLAG_OVERETH_UNKNOWN, | |
3216 | PRS_FLAG_OVERETH_IPV4, | |
3217 | PRS_FLAG_OVERETH_IPV6, | |
3218 | PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, | |
3219 | MAX_PRS_FLAGS_OVER_ETH | |
3220 | }; | |
3221 | ||
3222 | ||
3223 | /* | |
3224 | * Parsing flags for over-IP protocol | |
3225 | */ | |
3226 | enum prs_flags_over_ip { | |
3227 | PRS_FLAG_OVERIP_UNKNOWN, | |
3228 | PRS_FLAG_OVERIP_TCP, | |
3229 | PRS_FLAG_OVERIP_UDP, | |
3230 | MAX_PRS_FLAGS_OVER_IP | |
a2fbb9ea ET |
3231 | }; |
3232 | ||
3233 | ||
3234 | /* | |
523224a3 | 3235 | * SDM operation gen command (generate aggregative interrupt) |
a2fbb9ea | 3236 | */ |
523224a3 DK |
3237 | struct sdm_op_gen { |
3238 | __le32 command; | |
3239 | #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) | |
3240 | #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 | |
3241 | #define SDM_OP_GEN_COMP_TYPE (0x7<<5) | |
3242 | #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 | |
3243 | #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) | |
3244 | #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 | |
3245 | #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) | |
3246 | #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 | |
3247 | #define SDM_OP_GEN_RESERVED (0x7FFF<<17) | |
3248 | #define SDM_OP_GEN_RESERVED_SHIFT 17 | |
34f80b04 EG |
3249 | }; |
3250 | ||
34f80b04 EG |
3251 | |
3252 | /* | |
619c5cb6 | 3253 | * Timers connection context |
34f80b04 | 3254 | */ |
619c5cb6 VZ |
3255 | struct timers_block_context { |
3256 | u32 __reserved_0; | |
3257 | u32 __reserved_1; | |
3258 | u32 __reserved_2; | |
3259 | u32 flags; | |
3260 | #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) | |
3261 | #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 | |
3262 | #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) | |
3263 | #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 | |
3264 | #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) | |
3265 | #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 | |
34f80b04 EG |
3266 | }; |
3267 | ||
523224a3 | 3268 | |
34f80b04 | 3269 | /* |
619c5cb6 | 3270 | * The eth aggregative context of Tstorm |
34f80b04 | 3271 | */ |
619c5cb6 VZ |
3272 | struct tstorm_eth_ag_context { |
3273 | u32 __reserved0[14]; | |
a2fbb9ea ET |
3274 | }; |
3275 | ||
619c5cb6 | 3276 | |
a2fbb9ea | 3277 | /* |
619c5cb6 | 3278 | * The eth aggregative context of Ustorm |
a2fbb9ea | 3279 | */ |
619c5cb6 VZ |
3280 | struct ustorm_eth_ag_context { |
3281 | u32 __reserved0; | |
3282 | #if defined(__BIG_ENDIAN) | |
3283 | u8 cdu_usage; | |
3284 | u8 __reserved2; | |
3285 | u16 __reserved1; | |
3286 | #elif defined(__LITTLE_ENDIAN) | |
3287 | u16 __reserved1; | |
3288 | u8 __reserved2; | |
3289 | u8 cdu_usage; | |
3290 | #endif | |
3291 | u32 __reserved3[6]; | |
a2fbb9ea ET |
3292 | }; |
3293 | ||
619c5cb6 | 3294 | |
a2fbb9ea ET |
3295 | /* |
3296 | * The eth aggregative context of Xstorm | |
3297 | */ | |
3298 | struct xstorm_eth_ag_context { | |
523224a3 | 3299 | u32 reserved0; |
a2fbb9ea ET |
3300 | #if defined(__BIG_ENDIAN) |
3301 | u8 cdu_reserved; | |
523224a3 DK |
3302 | u8 reserved2; |
3303 | u16 reserved1; | |
a2fbb9ea | 3304 | #elif defined(__LITTLE_ENDIAN) |
523224a3 DK |
3305 | u16 reserved1; |
3306 | u8 reserved2; | |
a2fbb9ea ET |
3307 | u8 cdu_reserved; |
3308 | #endif | |
523224a3 | 3309 | u32 reserved3[30]; |
a2fbb9ea ET |
3310 | }; |
3311 | ||
523224a3 | 3312 | |
a2fbb9ea | 3313 | /* |
619c5cb6 | 3314 | * doorbell message sent to the chip |
a2fbb9ea | 3315 | */ |
619c5cb6 VZ |
3316 | struct doorbell { |
3317 | #if defined(__BIG_ENDIAN) | |
3318 | u16 zero_fill2; | |
3319 | u8 zero_fill1; | |
3320 | struct doorbell_hdr header; | |
3321 | #elif defined(__LITTLE_ENDIAN) | |
3322 | struct doorbell_hdr header; | |
3323 | u8 zero_fill1; | |
3324 | u16 zero_fill2; | |
3325 | #endif | |
a2fbb9ea ET |
3326 | }; |
3327 | ||
523224a3 | 3328 | |
a2fbb9ea | 3329 | /* |
619c5cb6 | 3330 | * doorbell message sent to the chip |
a2fbb9ea | 3331 | */ |
619c5cb6 | 3332 | struct doorbell_set_prod { |
a2fbb9ea | 3333 | #if defined(__BIG_ENDIAN) |
619c5cb6 VZ |
3334 | u16 prod; |
3335 | u8 zero_fill1; | |
3336 | struct doorbell_hdr header; | |
a2fbb9ea | 3337 | #elif defined(__LITTLE_ENDIAN) |
619c5cb6 VZ |
3338 | struct doorbell_hdr header; |
3339 | u8 zero_fill1; | |
3340 | u16 prod; | |
a2fbb9ea | 3341 | #endif |
a2fbb9ea ET |
3342 | }; |
3343 | ||
619c5cb6 VZ |
3344 | |
3345 | struct regpair { | |
3346 | __le32 lo; | |
3347 | __le32 hi; | |
3348 | }; | |
3349 | ||
3350 | ||
a2fbb9ea | 3351 | /* |
619c5cb6 | 3352 | * Classify rule opcodes in E2/E3 |
a2fbb9ea | 3353 | */ |
619c5cb6 VZ |
3354 | enum classify_rule { |
3355 | CLASSIFY_RULE_OPCODE_MAC, | |
3356 | CLASSIFY_RULE_OPCODE_VLAN, | |
3357 | CLASSIFY_RULE_OPCODE_PAIR, | |
3358 | MAX_CLASSIFY_RULE | |
a2fbb9ea ET |
3359 | }; |
3360 | ||
619c5cb6 | 3361 | |
a2fbb9ea | 3362 | /* |
619c5cb6 | 3363 | * Classify rule types in E2/E3 |
a2fbb9ea | 3364 | */ |
619c5cb6 VZ |
3365 | enum classify_rule_action_type { |
3366 | CLASSIFY_RULE_REMOVE, | |
3367 | CLASSIFY_RULE_ADD, | |
3368 | MAX_CLASSIFY_RULE_ACTION_TYPE | |
a2fbb9ea ET |
3369 | }; |
3370 | ||
619c5cb6 | 3371 | |
a2fbb9ea | 3372 | /* |
619c5cb6 | 3373 | * client init ramrod data |
a2fbb9ea | 3374 | */ |
619c5cb6 VZ |
3375 | struct client_init_general_data { |
3376 | u8 client_id; | |
3377 | u8 statistics_counter_id; | |
3378 | u8 statistics_en_flg; | |
3379 | u8 is_fcoe_flg; | |
3380 | u8 activate_flg; | |
3381 | u8 sp_client_id; | |
3382 | __le16 mtu; | |
3383 | u8 statistics_zero_flg; | |
3384 | u8 func_id; | |
3385 | u8 cos; | |
3386 | u8 traffic_type; | |
3387 | u32 reserved0; | |
ca00392c EG |
3388 | }; |
3389 | ||
619c5cb6 | 3390 | |
ca00392c | 3391 | /* |
619c5cb6 | 3392 | * client init rx data |
ca00392c | 3393 | */ |
619c5cb6 VZ |
3394 | struct client_init_rx_data { |
3395 | u8 tpa_en; | |
3396 | #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) | |
3397 | #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 | |
3398 | #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) | |
3399 | #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 | |
621b4d66 DK |
3400 | #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) |
3401 | #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 | |
3402 | #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) | |
3403 | #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 | |
619c5cb6 VZ |
3404 | u8 vmqueue_mode_en_flg; |
3405 | u8 extra_data_over_sgl_en_flg; | |
3406 | u8 cache_line_alignment_log_size; | |
3407 | u8 enable_dynamic_hc; | |
3408 | u8 max_sges_for_packet; | |
3409 | u8 client_qzone_id; | |
3410 | u8 drop_ip_cs_err_flg; | |
3411 | u8 drop_tcp_cs_err_flg; | |
3412 | u8 drop_ttl0_flg; | |
3413 | u8 drop_udp_cs_err_flg; | |
3414 | u8 inner_vlan_removal_enable_flg; | |
3415 | u8 outer_vlan_removal_enable_flg; | |
3416 | u8 status_block_id; | |
3417 | u8 rx_sb_index_number; | |
621b4d66 | 3418 | u8 dont_verify_rings_pause_thr_flg; |
619c5cb6 VZ |
3419 | u8 max_tpa_queues; |
3420 | u8 silent_vlan_removal_flg; | |
3421 | __le16 max_bytes_on_bd; | |
3422 | __le16 sge_buff_size; | |
3423 | u8 approx_mcast_engine_id; | |
3424 | u8 rss_engine_id; | |
3425 | struct regpair bd_page_base; | |
3426 | struct regpair sge_page_base; | |
3427 | struct regpair cqe_page_base; | |
3428 | u8 is_leading_rss; | |
3429 | u8 is_approx_mcast; | |
3430 | __le16 max_agg_size; | |
3431 | __le16 state; | |
3432 | #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) | |
3433 | #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 | |
3434 | #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) | |
3435 | #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 | |
3436 | #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) | |
3437 | #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 | |
3438 | #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) | |
3439 | #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 | |
3440 | #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) | |
3441 | #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 | |
3442 | #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) | |
3443 | #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 | |
3444 | #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) | |
3445 | #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 | |
3446 | #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) | |
3447 | #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 | |
3448 | __le16 cqe_pause_thr_low; | |
3449 | __le16 cqe_pause_thr_high; | |
3450 | __le16 bd_pause_thr_low; | |
3451 | __le16 bd_pause_thr_high; | |
3452 | __le16 sge_pause_thr_low; | |
3453 | __le16 sge_pause_thr_high; | |
3454 | __le16 rx_cos_mask; | |
3455 | __le16 silent_vlan_value; | |
3456 | __le16 silent_vlan_mask; | |
3457 | __le32 reserved6[2]; | |
a2fbb9ea ET |
3458 | }; |
3459 | ||
3460 | /* | |
619c5cb6 | 3461 | * client init tx data |
a2fbb9ea | 3462 | */ |
619c5cb6 VZ |
3463 | struct client_init_tx_data { |
3464 | u8 enforce_security_flg; | |
3465 | u8 tx_status_block_id; | |
3466 | u8 tx_sb_index_number; | |
3467 | u8 tss_leading_client_id; | |
3468 | u8 tx_switching_flg; | |
3469 | u8 anti_spoofing_flg; | |
3470 | __le16 default_vlan; | |
3471 | struct regpair tx_bd_page_base; | |
3472 | __le16 state; | |
3473 | #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) | |
3474 | #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 | |
3475 | #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) | |
3476 | #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 | |
3477 | #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) | |
3478 | #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 | |
3479 | #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) | |
3480 | #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 | |
3481 | #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4) | |
3482 | #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4 | |
3483 | u8 default_vlan_flg; | |
a3348722 | 3484 | u8 force_default_pri_flg; |
619c5cb6 | 3485 | __le32 reserved3; |
a2fbb9ea ET |
3486 | }; |
3487 | ||
f2e0899f | 3488 | /* |
619c5cb6 | 3489 | * client init ramrod data |
f2e0899f | 3490 | */ |
619c5cb6 VZ |
3491 | struct client_init_ramrod_data { |
3492 | struct client_init_general_data general; | |
3493 | struct client_init_rx_data rx; | |
3494 | struct client_init_tx_data tx; | |
f2e0899f DK |
3495 | }; |
3496 | ||
619c5cb6 | 3497 | |
a2fbb9ea | 3498 | /* |
619c5cb6 | 3499 | * client update ramrod data |
a2fbb9ea | 3500 | */ |
619c5cb6 VZ |
3501 | struct client_update_ramrod_data { |
3502 | u8 client_id; | |
3503 | u8 func_id; | |
3504 | u8 inner_vlan_removal_enable_flg; | |
3505 | u8 inner_vlan_removal_change_flg; | |
3506 | u8 outer_vlan_removal_enable_flg; | |
3507 | u8 outer_vlan_removal_change_flg; | |
3508 | u8 anti_spoofing_enable_flg; | |
3509 | u8 anti_spoofing_change_flg; | |
3510 | u8 activate_flg; | |
3511 | u8 activate_change_flg; | |
3512 | __le16 default_vlan; | |
3513 | u8 default_vlan_enable_flg; | |
3514 | u8 default_vlan_change_flg; | |
3515 | __le16 silent_vlan_value; | |
3516 | __le16 silent_vlan_mask; | |
3517 | u8 silent_vlan_removal_flg; | |
3518 | u8 silent_vlan_change_flg; | |
3519 | __le32 echo; | |
a2fbb9ea ET |
3520 | }; |
3521 | ||
619c5cb6 | 3522 | |
a2fbb9ea | 3523 | /* |
619c5cb6 | 3524 | * The eth storm context of Cstorm |
a2fbb9ea | 3525 | */ |
619c5cb6 VZ |
3526 | struct cstorm_eth_st_context { |
3527 | u32 __reserved0[4]; | |
3528 | }; | |
3529 | ||
3530 | ||
3531 | struct double_regpair { | |
3532 | u32 regpair0_lo; | |
3533 | u32 regpair0_hi; | |
3534 | u32 regpair1_lo; | |
3535 | u32 regpair1_hi; | |
a2fbb9ea ET |
3536 | }; |
3537 | ||
523224a3 | 3538 | |
a2fbb9ea | 3539 | /* |
619c5cb6 | 3540 | * Ethernet address typesm used in ethernet tx BDs |
a2fbb9ea | 3541 | */ |
619c5cb6 VZ |
3542 | enum eth_addr_type { |
3543 | UNKNOWN_ADDRESS, | |
3544 | UNICAST_ADDRESS, | |
3545 | MULTICAST_ADDRESS, | |
3546 | BROADCAST_ADDRESS, | |
3547 | MAX_ETH_ADDR_TYPE | |
a2fbb9ea ET |
3548 | }; |
3549 | ||
619c5cb6 | 3550 | |
a2fbb9ea | 3551 | /* |
619c5cb6 | 3552 | * |
a2fbb9ea | 3553 | */ |
619c5cb6 VZ |
3554 | struct eth_classify_cmd_header { |
3555 | u8 cmd_general_data; | |
3556 | #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) | |
3557 | #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 | |
3558 | #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) | |
3559 | #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 | |
3560 | #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) | |
3561 | #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 | |
3562 | #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) | |
3563 | #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 | |
3564 | #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) | |
3565 | #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 | |
3566 | u8 func_id; | |
3567 | u8 client_id; | |
3568 | u8 reserved1; | |
a2fbb9ea ET |
3569 | }; |
3570 | ||
619c5cb6 | 3571 | |
a2fbb9ea | 3572 | /* |
619c5cb6 | 3573 | * header for eth classification config ramrod |
a2fbb9ea | 3574 | */ |
619c5cb6 VZ |
3575 | struct eth_classify_header { |
3576 | u8 rule_cnt; | |
3577 | u8 reserved0; | |
3578 | __le16 reserved1; | |
3579 | __le32 echo; | |
a2fbb9ea ET |
3580 | }; |
3581 | ||
3582 | ||
3583 | /* | |
619c5cb6 | 3584 | * Command for adding/removing a MAC classification rule |
a2fbb9ea | 3585 | */ |
619c5cb6 VZ |
3586 | struct eth_classify_mac_cmd { |
3587 | struct eth_classify_cmd_header header; | |
3588 | __le32 reserved0; | |
3589 | __le16 mac_lsb; | |
3590 | __le16 mac_mid; | |
3591 | __le16 mac_msb; | |
3592 | __le16 reserved1; | |
3593 | }; | |
3594 | ||
3595 | ||
3596 | /* | |
3597 | * Command for adding/removing a MAC-VLAN pair classification rule | |
3598 | */ | |
3599 | struct eth_classify_pair_cmd { | |
3600 | struct eth_classify_cmd_header header; | |
3601 | __le32 reserved0; | |
3602 | __le16 mac_lsb; | |
3603 | __le16 mac_mid; | |
3604 | __le16 mac_msb; | |
3605 | __le16 vlan; | |
3606 | }; | |
3607 | ||
3608 | ||
3609 | /* | |
3610 | * Command for adding/removing a VLAN classification rule | |
3611 | */ | |
3612 | struct eth_classify_vlan_cmd { | |
3613 | struct eth_classify_cmd_header header; | |
3614 | __le32 reserved0; | |
3615 | __le32 reserved1; | |
3616 | __le16 reserved2; | |
3617 | __le16 vlan; | |
a2fbb9ea ET |
3618 | }; |
3619 | ||
619c5cb6 VZ |
3620 | /* |
3621 | * union for eth classification rule | |
3622 | */ | |
3623 | union eth_classify_rule_cmd { | |
3624 | struct eth_classify_mac_cmd mac; | |
3625 | struct eth_classify_vlan_cmd vlan; | |
3626 | struct eth_classify_pair_cmd pair; | |
3627 | }; | |
a2fbb9ea ET |
3628 | |
3629 | /* | |
619c5cb6 | 3630 | * parameters for eth classification configuration ramrod |
a2fbb9ea | 3631 | */ |
619c5cb6 VZ |
3632 | struct eth_classify_rules_ramrod_data { |
3633 | struct eth_classify_header header; | |
3634 | union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; | |
a2fbb9ea ET |
3635 | }; |
3636 | ||
a2fbb9ea ET |
3637 | |
3638 | /* | |
619c5cb6 | 3639 | * The data contain client ID need to the ramrod |
a2fbb9ea | 3640 | */ |
619c5cb6 VZ |
3641 | struct eth_common_ramrod_data { |
3642 | __le32 client_id; | |
3643 | __le32 reserved1; | |
a2fbb9ea ET |
3644 | }; |
3645 | ||
3646 | ||
3647 | /* | |
619c5cb6 | 3648 | * The eth storm context of Ustorm |
a2fbb9ea | 3649 | */ |
619c5cb6 VZ |
3650 | struct ustorm_eth_st_context { |
3651 | u32 reserved0[52]; | |
523224a3 DK |
3652 | }; |
3653 | ||
3654 | /* | |
619c5cb6 | 3655 | * The eth storm context of Tstorm |
523224a3 | 3656 | */ |
619c5cb6 VZ |
3657 | struct tstorm_eth_st_context { |
3658 | u32 __reserved0[28]; | |
a2fbb9ea ET |
3659 | }; |
3660 | ||
3661 | /* | |
619c5cb6 | 3662 | * The eth storm context of Xstorm |
a2fbb9ea | 3663 | */ |
619c5cb6 VZ |
3664 | struct xstorm_eth_st_context { |
3665 | u32 reserved0[60]; | |
a2fbb9ea ET |
3666 | }; |
3667 | ||
3668 | /* | |
619c5cb6 | 3669 | * Ethernet connection context |
a2fbb9ea | 3670 | */ |
619c5cb6 VZ |
3671 | struct eth_context { |
3672 | struct ustorm_eth_st_context ustorm_st_context; | |
3673 | struct tstorm_eth_st_context tstorm_st_context; | |
3674 | struct xstorm_eth_ag_context xstorm_ag_context; | |
3675 | struct tstorm_eth_ag_context tstorm_ag_context; | |
3676 | struct cstorm_eth_ag_context cstorm_ag_context; | |
3677 | struct ustorm_eth_ag_context ustorm_ag_context; | |
3678 | struct timers_block_context timers_context; | |
3679 | struct xstorm_eth_st_context xstorm_st_context; | |
3680 | struct cstorm_eth_st_context cstorm_st_context; | |
a2fbb9ea ET |
3681 | }; |
3682 | ||
3683 | ||
3684 | /* | |
523224a3 | 3685 | * union for sgl and raw data. |
a2fbb9ea | 3686 | */ |
523224a3 DK |
3687 | union eth_sgl_or_raw_data { |
3688 | __le16 sgl[8]; | |
3689 | u32 raw_data[4]; | |
a2fbb9ea ET |
3690 | }; |
3691 | ||
619c5cb6 VZ |
3692 | /* |
3693 | * eth FP end aggregation CQE parameters struct | |
3694 | */ | |
3695 | struct eth_end_agg_rx_cqe { | |
3696 | u8 type_error_flags; | |
3697 | #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) | |
3698 | #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 | |
3699 | #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) | |
3700 | #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 | |
3701 | #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) | |
3702 | #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 | |
3703 | u8 reserved1; | |
3704 | u8 queue_index; | |
3705 | u8 reserved2; | |
3706 | __le32 timestamp_delta; | |
3707 | __le16 num_of_coalesced_segs; | |
3708 | __le16 pkt_len; | |
3709 | u8 pure_ack_count; | |
3710 | u8 reserved3; | |
3711 | __le16 reserved4; | |
3712 | union eth_sgl_or_raw_data sgl_or_raw_data; | |
3713 | __le32 reserved5[8]; | |
3714 | }; | |
3715 | ||
3716 | ||
a2fbb9ea ET |
3717 | /* |
3718 | * regular eth FP CQE parameters struct | |
3719 | */ | |
3720 | struct eth_fast_path_rx_cqe { | |
34f80b04 | 3721 | u8 type_error_flags; |
619c5cb6 | 3722 | #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) |
34f80b04 | 3723 | #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 |
619c5cb6 VZ |
3724 | #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) |
3725 | #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 | |
3726 | #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) | |
3727 | #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 | |
3728 | #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) | |
3729 | #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 | |
3730 | #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) | |
3731 | #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 | |
3732 | #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) | |
3733 | #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 | |
a2fbb9ea ET |
3734 | u8 status_flags; |
3735 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) | |
3736 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 | |
3737 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) | |
3738 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 | |
3739 | #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) | |
3740 | #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 | |
3741 | #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) | |
3742 | #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 | |
3743 | #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) | |
3744 | #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 | |
3745 | #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) | |
3746 | #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 | |
34f80b04 | 3747 | u8 queue_index; |
619c5cb6 | 3748 | u8 placement_offset; |
4781bfad EG |
3749 | __le32 rss_hash_result; |
3750 | __le16 vlan_tag; | |
621b4d66 | 3751 | __le16 pkt_len_or_gro_seg_len; |
4781bfad | 3752 | __le16 len_on_bd; |
a2fbb9ea | 3753 | struct parsing_flags pars_flags; |
523224a3 | 3754 | union eth_sgl_or_raw_data sgl_or_raw_data; |
619c5cb6 VZ |
3755 | __le32 reserved1[8]; |
3756 | }; | |
3757 | ||
3758 | ||
3759 | /* | |
3760 | * Command for setting classification flags for a client | |
3761 | */ | |
3762 | struct eth_filter_rules_cmd { | |
3763 | u8 cmd_general_data; | |
3764 | #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) | |
3765 | #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 | |
3766 | #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) | |
3767 | #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 | |
3768 | #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) | |
3769 | #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 | |
3770 | u8 func_id; | |
3771 | u8 client_id; | |
3772 | u8 reserved1; | |
3773 | __le16 state; | |
3774 | #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) | |
3775 | #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 | |
3776 | #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) | |
3777 | #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 | |
3778 | #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) | |
3779 | #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 | |
3780 | #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) | |
3781 | #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 | |
3782 | #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) | |
3783 | #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 | |
3784 | #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) | |
3785 | #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 | |
3786 | #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) | |
3787 | #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 | |
3788 | #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) | |
3789 | #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 | |
3790 | __le16 reserved3; | |
3791 | struct regpair reserved4; | |
3792 | }; | |
3793 | ||
3794 | ||
3795 | /* | |
3796 | * parameters for eth classification filters ramrod | |
3797 | */ | |
3798 | struct eth_filter_rules_ramrod_data { | |
3799 | struct eth_classify_header header; | |
3800 | struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; | |
3801 | }; | |
3802 | ||
3803 | ||
3804 | /* | |
3805 | * parameters for eth classification configuration ramrod | |
3806 | */ | |
3807 | struct eth_general_rules_ramrod_data { | |
3808 | struct eth_classify_header header; | |
3809 | union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; | |
a2fbb9ea ET |
3810 | }; |
3811 | ||
3812 | ||
3813 | /* | |
619c5cb6 | 3814 | * The data for Halt ramrod |
a2fbb9ea ET |
3815 | */ |
3816 | struct eth_halt_ramrod_data { | |
619c5cb6 VZ |
3817 | __le32 client_id; |
3818 | __le32 reserved0; | |
a2fbb9ea ET |
3819 | }; |
3820 | ||
619c5cb6 | 3821 | |
34f80b04 | 3822 | /* |
619c5cb6 | 3823 | * Command for setting multicast classification for a client |
34f80b04 | 3824 | */ |
619c5cb6 VZ |
3825 | struct eth_multicast_rules_cmd { |
3826 | u8 cmd_general_data; | |
3827 | #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) | |
3828 | #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 | |
3829 | #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) | |
3830 | #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 | |
3831 | #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) | |
3832 | #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 | |
3833 | #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) | |
3834 | #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 | |
3835 | u8 func_id; | |
3836 | u8 bin_id; | |
3837 | u8 engine_id; | |
3838 | __le32 reserved2; | |
3839 | struct regpair reserved3; | |
3840 | }; | |
3841 | ||
3842 | ||
3843 | /* | |
3844 | * parameters for multicast classification ramrod | |
3845 | */ | |
3846 | struct eth_multicast_rules_ramrod_data { | |
3847 | struct eth_classify_header header; | |
3848 | struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; | |
34f80b04 EG |
3849 | }; |
3850 | ||
3851 | ||
a2fbb9ea ET |
3852 | /* |
3853 | * Place holder for ramrods protocol specific data | |
3854 | */ | |
3855 | struct ramrod_data { | |
4781bfad EG |
3856 | __le32 data_lo; |
3857 | __le32 data_hi; | |
a2fbb9ea ET |
3858 | }; |
3859 | ||
3860 | /* | |
33471629 | 3861 | * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) |
a2fbb9ea ET |
3862 | */ |
3863 | union eth_ramrod_data { | |
3864 | struct ramrod_data general; | |
3865 | }; | |
3866 | ||
3867 | ||
619c5cb6 VZ |
3868 | /* |
3869 | * RSS toeplitz hash type, as reported in CQE | |
3870 | */ | |
3871 | enum eth_rss_hash_type { | |
3872 | DEFAULT_HASH_TYPE, | |
3873 | IPV4_HASH_TYPE, | |
3874 | TCP_IPV4_HASH_TYPE, | |
3875 | IPV6_HASH_TYPE, | |
3876 | TCP_IPV6_HASH_TYPE, | |
3877 | VLAN_PRI_HASH_TYPE, | |
3878 | E1HOV_PRI_HASH_TYPE, | |
3879 | DSCP_HASH_TYPE, | |
3880 | MAX_ETH_RSS_HASH_TYPE | |
3881 | }; | |
3882 | ||
3883 | ||
3884 | /* | |
3885 | * Ethernet RSS mode | |
3886 | */ | |
3887 | enum eth_rss_mode { | |
3888 | ETH_RSS_MODE_DISABLED, | |
3889 | ETH_RSS_MODE_REGULAR, | |
3890 | ETH_RSS_MODE_VLAN_PRI, | |
3891 | ETH_RSS_MODE_E1HOV_PRI, | |
3892 | ETH_RSS_MODE_IP_DSCP, | |
3893 | MAX_ETH_RSS_MODE | |
3894 | }; | |
3895 | ||
3896 | ||
3897 | /* | |
3898 | * parameters for RSS update ramrod (E2) | |
3899 | */ | |
3900 | struct eth_rss_update_ramrod_data { | |
3901 | u8 rss_engine_id; | |
3902 | u8 capabilities; | |
3903 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) | |
3904 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 | |
3905 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) | |
3906 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 | |
3907 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) | |
3908 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 | |
3909 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) | |
3910 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 | |
3911 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) | |
3912 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 | |
3913 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) | |
3914 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 | |
96bed4b9 YM |
3915 | #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) |
3916 | #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 | |
619c5cb6 VZ |
3917 | u8 rss_result_mask; |
3918 | u8 rss_mode; | |
3919 | __le32 __reserved2; | |
3920 | u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; | |
3921 | __le32 rss_key[T_ETH_RSS_KEY]; | |
3922 | __le32 echo; | |
3923 | __le32 reserved3; | |
3924 | }; | |
3925 | ||
3926 | ||
3927 | /* | |
3928 | * The eth Rx Buffer Descriptor | |
3929 | */ | |
3930 | struct eth_rx_bd { | |
3931 | __le32 addr_lo; | |
3932 | __le32 addr_hi; | |
3933 | }; | |
3934 | ||
3935 | ||
a2fbb9ea ET |
3936 | /* |
3937 | * Eth Rx Cqe structure- general structure for ramrods | |
3938 | */ | |
3939 | struct common_ramrod_eth_rx_cqe { | |
34f80b04 | 3940 | u8 ramrod_type; |
619c5cb6 | 3941 | #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) |
34f80b04 | 3942 | #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 |
619c5cb6 VZ |
3943 | #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) |
3944 | #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 | |
3945 | #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) | |
3946 | #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 | |
8d9c5f34 | 3947 | u8 conn_type; |
4781bfad EG |
3948 | __le16 reserved1; |
3949 | __le32 conn_and_cmd_data; | |
a2fbb9ea ET |
3950 | #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) |
3951 | #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 | |
3952 | #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) | |
3953 | #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 | |
3954 | struct ramrod_data protocol_data; | |
619c5cb6 VZ |
3955 | __le32 echo; |
3956 | __le32 reserved2[11]; | |
3957 | }; | |
3958 | ||
3959 | /* | |
3960 | * Rx Last CQE in page (in ETH) | |
3961 | */ | |
3962 | struct eth_rx_cqe_next_page { | |
3963 | __le32 addr_lo; | |
3964 | __le32 addr_hi; | |
3965 | __le32 reserved[14]; | |
3966 | }; | |
3967 | ||
3968 | /* | |
3969 | * union for all eth rx cqe types (fix their sizes) | |
3970 | */ | |
3971 | union eth_rx_cqe { | |
3972 | struct eth_fast_path_rx_cqe fast_path_cqe; | |
3973 | struct common_ramrod_eth_rx_cqe ramrod_cqe; | |
3974 | struct eth_rx_cqe_next_page next_page_cqe; | |
3975 | struct eth_end_agg_rx_cqe end_agg_cqe; | |
3976 | }; | |
3977 | ||
3978 | ||
3979 | /* | |
3980 | * Values for RX ETH CQE type field | |
3981 | */ | |
3982 | enum eth_rx_cqe_type { | |
3983 | RX_ETH_CQE_TYPE_ETH_FASTPATH, | |
3984 | RX_ETH_CQE_TYPE_ETH_RAMROD, | |
3985 | RX_ETH_CQE_TYPE_ETH_START_AGG, | |
3986 | RX_ETH_CQE_TYPE_ETH_STOP_AGG, | |
3987 | MAX_ETH_RX_CQE_TYPE | |
3988 | }; | |
3989 | ||
3990 | ||
3991 | /* | |
3992 | * Type of SGL/Raw field in ETH RX fast path CQE | |
3993 | */ | |
3994 | enum eth_rx_fp_sel { | |
3995 | ETH_FP_CQE_REGULAR, | |
3996 | ETH_FP_CQE_RAW, | |
3997 | MAX_ETH_RX_FP_SEL | |
3998 | }; | |
3999 | ||
4000 | ||
4001 | /* | |
4002 | * The eth Rx SGE Descriptor | |
4003 | */ | |
4004 | struct eth_rx_sge { | |
4005 | __le32 addr_lo; | |
4006 | __le32 addr_hi; | |
4007 | }; | |
4008 | ||
4009 | ||
4010 | /* | |
4011 | * common data for all protocols | |
4012 | */ | |
4013 | struct spe_hdr { | |
4014 | __le32 conn_and_cmd_data; | |
4015 | #define SPE_HDR_CID (0xFFFFFF<<0) | |
4016 | #define SPE_HDR_CID_SHIFT 0 | |
4017 | #define SPE_HDR_CMD_ID (0xFF<<24) | |
4018 | #define SPE_HDR_CMD_ID_SHIFT 24 | |
4019 | __le16 type; | |
4020 | #define SPE_HDR_CONN_TYPE (0xFF<<0) | |
4021 | #define SPE_HDR_CONN_TYPE_SHIFT 0 | |
4022 | #define SPE_HDR_FUNCTION_ID (0xFF<<8) | |
4023 | #define SPE_HDR_FUNCTION_ID_SHIFT 8 | |
4024 | __le16 reserved1; | |
4025 | }; | |
4026 | ||
4027 | /* | |
4028 | * specific data for ethernet slow path element | |
4029 | */ | |
4030 | union eth_specific_data { | |
4031 | u8 protocol_data[8]; | |
4032 | struct regpair client_update_ramrod_data; | |
4033 | struct regpair client_init_ramrod_init_data; | |
4034 | struct eth_halt_ramrod_data halt_ramrod_data; | |
4035 | struct regpair update_data_addr; | |
4036 | struct eth_common_ramrod_data common_ramrod_data; | |
4037 | struct regpair classify_cfg_addr; | |
4038 | struct regpair filter_cfg_addr; | |
4039 | struct regpair mcast_cfg_addr; | |
4040 | }; | |
4041 | ||
4042 | /* | |
4043 | * Ethernet slow path element | |
4044 | */ | |
4045 | struct eth_spe { | |
4046 | struct spe_hdr hdr; | |
4047 | union eth_specific_data data; | |
4048 | }; | |
4049 | ||
4050 | ||
4051 | /* | |
4052 | * Ethernet command ID for slow path elements | |
4053 | */ | |
4054 | enum eth_spqe_cmd_id { | |
4055 | RAMROD_CMD_ID_ETH_UNUSED, | |
4056 | RAMROD_CMD_ID_ETH_CLIENT_SETUP, | |
4057 | RAMROD_CMD_ID_ETH_HALT, | |
4058 | RAMROD_CMD_ID_ETH_FORWARD_SETUP, | |
4059 | RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, | |
4060 | RAMROD_CMD_ID_ETH_CLIENT_UPDATE, | |
4061 | RAMROD_CMD_ID_ETH_EMPTY, | |
4062 | RAMROD_CMD_ID_ETH_TERMINATE, | |
4063 | RAMROD_CMD_ID_ETH_TPA_UPDATE, | |
4064 | RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, | |
4065 | RAMROD_CMD_ID_ETH_FILTER_RULES, | |
4066 | RAMROD_CMD_ID_ETH_MULTICAST_RULES, | |
4067 | RAMROD_CMD_ID_ETH_RSS_UPDATE, | |
4068 | RAMROD_CMD_ID_ETH_SET_MAC, | |
4069 | MAX_ETH_SPQE_CMD_ID | |
4070 | }; | |
4071 | ||
4072 | ||
4073 | /* | |
4074 | * eth tpa update command | |
4075 | */ | |
4076 | enum eth_tpa_update_command { | |
4077 | TPA_UPDATE_NONE_COMMAND, | |
4078 | TPA_UPDATE_ENABLE_COMMAND, | |
4079 | TPA_UPDATE_DISABLE_COMMAND, | |
4080 | MAX_ETH_TPA_UPDATE_COMMAND | |
4081 | }; | |
4082 | ||
4083 | ||
4084 | /* | |
4085 | * Tx regular BD structure | |
4086 | */ | |
4087 | struct eth_tx_bd { | |
4088 | __le32 addr_lo; | |
4089 | __le32 addr_hi; | |
4090 | __le16 total_pkt_bytes; | |
4091 | __le16 nbytes; | |
4092 | u8 reserved[4]; | |
4093 | }; | |
4094 | ||
4095 | ||
4096 | /* | |
4097 | * structure for easy accessibility to assembler | |
4098 | */ | |
4099 | struct eth_tx_bd_flags { | |
4100 | u8 as_bitfield; | |
4101 | #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) | |
4102 | #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 | |
4103 | #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) | |
4104 | #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 | |
4105 | #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) | |
4106 | #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 | |
4107 | #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) | |
4108 | #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 | |
4109 | #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) | |
4110 | #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 | |
4111 | #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) | |
4112 | #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 | |
4113 | #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) | |
4114 | #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 | |
a2fbb9ea ET |
4115 | }; |
4116 | ||
4117 | /* | |
619c5cb6 | 4118 | * The eth Tx Buffer Descriptor |
a2fbb9ea | 4119 | */ |
619c5cb6 | 4120 | struct eth_tx_start_bd { |
4781bfad EG |
4121 | __le32 addr_lo; |
4122 | __le32 addr_hi; | |
619c5cb6 VZ |
4123 | __le16 nbd; |
4124 | __le16 nbytes; | |
4125 | __le16 vlan_or_ethertype; | |
4126 | struct eth_tx_bd_flags bd_flags; | |
4127 | u8 general_data; | |
4128 | #define ETH_TX_START_BD_HDR_NBDS (0xF<<0) | |
4129 | #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 | |
4130 | #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) | |
4131 | #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 | |
96bed4b9 YM |
4132 | #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) |
4133 | #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 | |
4134 | #define ETH_TX_START_BD_RESREVED (0x1<<7) | |
4135 | #define ETH_TX_START_BD_RESREVED_SHIFT 7 | |
a2fbb9ea ET |
4136 | }; |
4137 | ||
4138 | /* | |
619c5cb6 | 4139 | * Tx parsing BD structure for ETH E1/E1h |
a2fbb9ea | 4140 | */ |
619c5cb6 | 4141 | struct eth_tx_parse_bd_e1x { |
96bed4b9 | 4142 | __le16 global_data; |
619c5cb6 VZ |
4143 | #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) |
4144 | #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 | |
96bed4b9 YM |
4145 | #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) |
4146 | #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 | |
4147 | #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) | |
4148 | #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 | |
4149 | #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) | |
4150 | #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 | |
4151 | #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) | |
4152 | #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 | |
4153 | #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) | |
4154 | #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 | |
619c5cb6 VZ |
4155 | u8 tcp_flags; |
4156 | #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) | |
4157 | #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 | |
4158 | #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) | |
4159 | #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 | |
4160 | #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) | |
4161 | #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 | |
4162 | #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) | |
4163 | #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 | |
4164 | #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) | |
4165 | #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 | |
4166 | #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) | |
4167 | #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 | |
4168 | #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) | |
4169 | #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 | |
4170 | #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) | |
4171 | #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 | |
4172 | u8 ip_hlen_w; | |
619c5cb6 VZ |
4173 | __le16 total_hlen_w; |
4174 | __le16 tcp_pseudo_csum; | |
4175 | __le16 lso_mss; | |
4176 | __le16 ip_id; | |
4177 | __le32 tcp_send_seq; | |
a2fbb9ea ET |
4178 | }; |
4179 | ||
a2fbb9ea | 4180 | /* |
619c5cb6 | 4181 | * Tx parsing BD structure for ETH E2 |
a2fbb9ea | 4182 | */ |
619c5cb6 VZ |
4183 | struct eth_tx_parse_bd_e2 { |
4184 | __le16 dst_mac_addr_lo; | |
4185 | __le16 dst_mac_addr_mid; | |
4186 | __le16 dst_mac_addr_hi; | |
4187 | __le16 src_mac_addr_lo; | |
4188 | __le16 src_mac_addr_mid; | |
4189 | __le16 src_mac_addr_hi; | |
4190 | __le32 parsing_data; | |
96bed4b9 | 4191 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x7FF<<0) |
619c5cb6 | 4192 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0 |
96bed4b9 YM |
4193 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) |
4194 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 | |
4195 | #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) | |
4196 | #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 | |
4197 | #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) | |
4198 | #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 | |
4199 | #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) | |
4200 | #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 | |
a2fbb9ea ET |
4201 | }; |
4202 | ||
a2fbb9ea | 4203 | /* |
619c5cb6 | 4204 | * The last BD in the BD memory will hold a pointer to the next BD memory |
a2fbb9ea | 4205 | */ |
619c5cb6 VZ |
4206 | struct eth_tx_next_bd { |
4207 | __le32 addr_lo; | |
4208 | __le32 addr_hi; | |
4209 | u8 reserved[8]; | |
a2fbb9ea ET |
4210 | }; |
4211 | ||
4212 | /* | |
619c5cb6 | 4213 | * union for 4 Bd types |
a2fbb9ea | 4214 | */ |
619c5cb6 VZ |
4215 | union eth_tx_bd_types { |
4216 | struct eth_tx_start_bd start_bd; | |
4217 | struct eth_tx_bd reg_bd; | |
4218 | struct eth_tx_parse_bd_e1x parse_bd_e1x; | |
4219 | struct eth_tx_parse_bd_e2 parse_bd_e2; | |
4220 | struct eth_tx_next_bd next_bd; | |
a2fbb9ea ET |
4221 | }; |
4222 | ||
a2fbb9ea | 4223 | /* |
ca00392c | 4224 | * array of 13 bds as appears in the eth xstorm context |
a2fbb9ea | 4225 | */ |
ca00392c EG |
4226 | struct eth_tx_bds_array { |
4227 | union eth_tx_bd_types bds[13]; | |
a2fbb9ea ET |
4228 | }; |
4229 | ||
4230 | ||
4231 | /* | |
619c5cb6 | 4232 | * VLAN mode on TX BDs |
a2fbb9ea | 4233 | */ |
619c5cb6 VZ |
4234 | enum eth_tx_vlan_type { |
4235 | X_ETH_NO_VLAN, | |
4236 | X_ETH_OUTBAND_VLAN, | |
4237 | X_ETH_INBAND_VLAN, | |
4238 | X_ETH_FW_ADDED_VLAN, | |
4239 | MAX_ETH_TX_VLAN_TYPE | |
a2fbb9ea ET |
4240 | }; |
4241 | ||
ca00392c | 4242 | |
a2fbb9ea | 4243 | /* |
619c5cb6 | 4244 | * Ethernet VLAN filtering mode in E1x |
a2fbb9ea | 4245 | */ |
619c5cb6 VZ |
4246 | enum eth_vlan_filter_mode { |
4247 | ETH_VLAN_FILTER_ANY_VLAN, | |
4248 | ETH_VLAN_FILTER_SPECIFIC_VLAN, | |
4249 | ETH_VLAN_FILTER_CLASSIFY, | |
4250 | MAX_ETH_VLAN_FILTER_MODE | |
a2fbb9ea ET |
4251 | }; |
4252 | ||
4253 | ||
4254 | /* | |
4255 | * MAC filtering configuration command header | |
4256 | */ | |
4257 | struct mac_configuration_hdr { | |
8d9c5f34 | 4258 | u8 length; |
a2fbb9ea | 4259 | u8 offset; |
619c5cb6 VZ |
4260 | __le16 client_id; |
4261 | __le32 echo; | |
a2fbb9ea ET |
4262 | }; |
4263 | ||
4264 | /* | |
4265 | * MAC address in list for ramrod | |
4266 | */ | |
523224a3 | 4267 | struct mac_configuration_entry { |
4781bfad EG |
4268 | __le16 lsb_mac_addr; |
4269 | __le16 middle_mac_addr; | |
4270 | __le16 msb_mac_addr; | |
523224a3 DK |
4271 | __le16 vlan_id; |
4272 | u8 pf_id; | |
a2fbb9ea | 4273 | u8 flags; |
523224a3 DK |
4274 | #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) |
4275 | #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 | |
4276 | #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) | |
4277 | #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 | |
4278 | #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) | |
4279 | #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 | |
4280 | #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) | |
4281 | #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 | |
4282 | #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) | |
4283 | #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 | |
4284 | #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) | |
4285 | #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 | |
619c5cb6 VZ |
4286 | __le16 reserved0; |
4287 | __le32 clients_bit_vector; | |
a2fbb9ea ET |
4288 | }; |
4289 | ||
4290 | /* | |
523224a3 | 4291 | * MAC filtering configuration command |
a2fbb9ea ET |
4292 | */ |
4293 | struct mac_configuration_cmd { | |
4294 | struct mac_configuration_hdr hdr; | |
4295 | struct mac_configuration_entry config_table[64]; | |
4296 | }; | |
4297 | ||
4298 | ||
619c5cb6 VZ |
4299 | /* |
4300 | * Set-MAC command type (in E1x) | |
4301 | */ | |
4302 | enum set_mac_action_type { | |
4303 | T_ETH_MAC_COMMAND_INVALIDATE, | |
4304 | T_ETH_MAC_COMMAND_SET, | |
4305 | MAX_SET_MAC_ACTION_TYPE | |
4306 | }; | |
4307 | ||
4308 | ||
621b4d66 DK |
4309 | /* |
4310 | * Ethernet TPA Modes | |
4311 | */ | |
4312 | enum tpa_mode { | |
4313 | TPA_LRO, | |
4314 | TPA_GRO, | |
4315 | MAX_TPA_MODE}; | |
4316 | ||
4317 | ||
619c5cb6 VZ |
4318 | /* |
4319 | * tpa update ramrod data | |
4320 | */ | |
4321 | struct tpa_update_ramrod_data { | |
4322 | u8 update_ipv4; | |
4323 | u8 update_ipv6; | |
4324 | u8 client_id; | |
4325 | u8 max_tpa_queues; | |
4326 | u8 max_sges_for_packet; | |
4327 | u8 complete_on_both_clients; | |
621b4d66 DK |
4328 | u8 dont_verify_rings_pause_thr_flg; |
4329 | u8 tpa_mode; | |
619c5cb6 VZ |
4330 | __le16 sge_buff_size; |
4331 | __le16 max_agg_size; | |
4332 | __le32 sge_page_base_lo; | |
4333 | __le32 sge_page_base_hi; | |
4334 | __le16 sge_pause_thr_low; | |
4335 | __le16 sge_pause_thr_high; | |
4336 | }; | |
4337 | ||
4338 | ||
34f80b04 EG |
4339 | /* |
4340 | * approximate-match multicast filtering for E1H per function in Tstorm | |
4341 | */ | |
4342 | struct tstorm_eth_approximate_match_multicast_filtering { | |
4343 | u32 mcast_add_hash_bit_array[8]; | |
4344 | }; | |
4345 | ||
4346 | ||
619c5cb6 VZ |
4347 | /* |
4348 | * Common configuration parameters per function in Tstorm | |
4349 | */ | |
4350 | struct tstorm_eth_function_common_config { | |
4351 | __le16 config_flags; | |
4352 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) | |
4353 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 | |
4354 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) | |
4355 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 | |
4356 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) | |
4357 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 | |
4358 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) | |
4359 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 | |
4360 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) | |
4361 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 | |
4362 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) | |
4363 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 | |
4364 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) | |
4365 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 | |
4366 | u8 rss_result_mask; | |
4367 | u8 reserved1; | |
4368 | __le16 vlan_id[2]; | |
4369 | }; | |
4370 | ||
4371 | ||
a2fbb9ea ET |
4372 | /* |
4373 | * MAC filtering configuration parameters per port in Tstorm | |
4374 | */ | |
4375 | struct tstorm_eth_mac_filter_config { | |
619c5cb6 VZ |
4376 | __le32 ucast_drop_all; |
4377 | __le32 ucast_accept_all; | |
4378 | __le32 mcast_drop_all; | |
4379 | __le32 mcast_accept_all; | |
4380 | __le32 bcast_accept_all; | |
4381 | __le32 vlan_filter[2]; | |
4382 | __le32 unmatched_unicast; | |
a2fbb9ea ET |
4383 | }; |
4384 | ||
4385 | ||
8d9c5f34 | 4386 | /* |
619c5cb6 | 4387 | * tx only queue init ramrod data |
8d9c5f34 | 4388 | */ |
619c5cb6 VZ |
4389 | struct tx_queue_init_ramrod_data { |
4390 | struct client_init_general_data general; | |
4391 | struct client_init_tx_data tx; | |
8d9c5f34 EG |
4392 | }; |
4393 | ||
4394 | ||
34f80b04 EG |
4395 | /* |
4396 | * Three RX producers for ETH | |
4397 | */ | |
8d9c5f34 | 4398 | struct ustorm_eth_rx_producers { |
a2fbb9ea | 4399 | #if defined(__BIG_ENDIAN) |
34f80b04 EG |
4400 | u16 bd_prod; |
4401 | u16 cqe_prod; | |
a2fbb9ea | 4402 | #elif defined(__LITTLE_ENDIAN) |
34f80b04 EG |
4403 | u16 cqe_prod; |
4404 | u16 bd_prod; | |
a2fbb9ea | 4405 | #endif |
a2fbb9ea | 4406 | #if defined(__BIG_ENDIAN) |
34f80b04 EG |
4407 | u16 reserved; |
4408 | u16 sge_prod; | |
a2fbb9ea | 4409 | #elif defined(__LITTLE_ENDIAN) |
34f80b04 EG |
4410 | u16 sge_prod; |
4411 | u16 reserved; | |
a2fbb9ea | 4412 | #endif |
a2fbb9ea ET |
4413 | }; |
4414 | ||
a2fbb9ea | 4415 | |
523224a3 | 4416 | /* |
50f0a562 BW |
4417 | * FCoE RX statistics parameters section#0 |
4418 | */ | |
4419 | struct fcoe_rx_stat_params_section0 { | |
4420 | __le32 fcoe_rx_pkt_cnt; | |
4421 | __le32 fcoe_rx_byte_cnt; | |
4422 | }; | |
4423 | ||
4424 | ||
4425 | /* | |
4426 | * FCoE RX statistics parameters section#1 | |
4427 | */ | |
4428 | struct fcoe_rx_stat_params_section1 { | |
4429 | __le32 fcoe_ver_cnt; | |
4430 | __le32 fcoe_rx_drop_pkt_cnt; | |
4431 | }; | |
4432 | ||
4433 | ||
4434 | /* | |
4435 | * FCoE RX statistics parameters section#2 | |
523224a3 | 4436 | */ |
50f0a562 BW |
4437 | struct fcoe_rx_stat_params_section2 { |
4438 | __le32 fc_crc_cnt; | |
4439 | __le32 eofa_del_cnt; | |
4440 | __le32 miss_frame_cnt; | |
4441 | __le32 seq_timeout_cnt; | |
4442 | __le32 drop_seq_cnt; | |
4443 | __le32 fcoe_rx_drop_pkt_cnt; | |
4444 | __le32 fcp_rx_pkt_cnt; | |
4445 | __le32 reserved0; | |
4446 | }; | |
4447 | ||
4448 | ||
4449 | /* | |
4450 | * FCoE TX statistics parameters | |
4451 | */ | |
4452 | struct fcoe_tx_stat_params { | |
4453 | __le32 fcoe_tx_pkt_cnt; | |
4454 | __le32 fcoe_tx_byte_cnt; | |
4455 | __le32 fcp_tx_pkt_cnt; | |
4456 | __le32 reserved0; | |
4457 | }; | |
4458 | ||
4459 | /* | |
4460 | * FCoE statistics parameters | |
4461 | */ | |
4462 | struct fcoe_statistics_params { | |
4463 | struct fcoe_tx_stat_params tx_stat; | |
4464 | struct fcoe_rx_stat_params_section0 rx_stat0; | |
4465 | struct fcoe_rx_stat_params_section1 rx_stat1; | |
4466 | struct fcoe_rx_stat_params_section2 rx_stat2; | |
4467 | }; | |
4468 | ||
4469 | ||
a3348722 BW |
4470 | /* |
4471 | * The data afex vif list ramrod need | |
4472 | */ | |
4473 | struct afex_vif_list_ramrod_data { | |
4474 | u8 afex_vif_list_command; | |
4475 | u8 func_bit_map; | |
4476 | __le16 vif_list_index; | |
4477 | u8 func_to_clear; | |
4478 | u8 echo; | |
4479 | __le16 reserved1; | |
4480 | }; | |
4481 | ||
4482 | ||
50f0a562 BW |
4483 | /* |
4484 | * cfc delete event data | |
a3348722 | 4485 | */ |
523224a3 DK |
4486 | struct cfc_del_event_data { |
4487 | u32 cid; | |
619c5cb6 VZ |
4488 | u32 reserved0; |
4489 | u32 reserved1; | |
523224a3 DK |
4490 | }; |
4491 | ||
4492 | ||
34f80b04 EG |
4493 | /* |
4494 | * per-port SAFC demo variables | |
4495 | */ | |
4496 | struct cmng_flags_per_port { | |
8a1c38d1 EG |
4497 | u32 cmng_enables; |
4498 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) | |
4499 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 | |
4500 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) | |
4501 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 | |
619c5cb6 VZ |
4502 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) |
4503 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 | |
4504 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) | |
4505 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 | |
4506 | #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) | |
4507 | #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 | |
4508 | u32 __reserved1; | |
a2fbb9ea ET |
4509 | }; |
4510 | ||
34f80b04 EG |
4511 | |
4512 | /* | |
4513 | * per-port rate shaping variables | |
4514 | */ | |
4515 | struct rate_shaping_vars_per_port { | |
4516 | u32 rs_periodic_timeout; | |
4517 | u32 rs_threshold; | |
4518 | }; | |
4519 | ||
34f80b04 EG |
4520 | /* |
4521 | * per-port fairness variables | |
4522 | */ | |
4523 | struct fairness_vars_per_port { | |
4524 | u32 upper_bound; | |
4525 | u32 fair_threshold; | |
4526 | u32 fairness_timeout; | |
619c5cb6 | 4527 | u32 reserved0; |
34f80b04 EG |
4528 | }; |
4529 | ||
34f80b04 EG |
4530 | /* |
4531 | * per-port SAFC variables | |
4532 | */ | |
4533 | struct safc_struct_per_port { | |
4534 | #if defined(__BIG_ENDIAN) | |
8d9c5f34 EG |
4535 | u16 __reserved1; |
4536 | u8 __reserved0; | |
34f80b04 EG |
4537 | u8 safc_timeout_usec; |
4538 | #elif defined(__LITTLE_ENDIAN) | |
4539 | u8 safc_timeout_usec; | |
8d9c5f34 EG |
4540 | u8 __reserved0; |
4541 | u16 __reserved1; | |
34f80b04 | 4542 | #endif |
523224a3 | 4543 | u8 cos_to_traffic_types[MAX_COS_NUMBER]; |
8d9c5f34 | 4544 | u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; |
a2fbb9ea ET |
4545 | }; |
4546 | ||
34f80b04 EG |
4547 | /* |
4548 | * Per-port congestion management variables | |
4549 | */ | |
4550 | struct cmng_struct_per_port { | |
4551 | struct rate_shaping_vars_per_port rs_vars; | |
4552 | struct fairness_vars_per_port fair_vars; | |
4553 | struct safc_struct_per_port safc_vars; | |
4554 | struct cmng_flags_per_port flags; | |
a2fbb9ea ET |
4555 | }; |
4556 | ||
b475d78f YM |
4557 | /* |
4558 | * a single rate shaping counter. can be used as protocol or vnic counter | |
4559 | */ | |
4560 | struct rate_shaping_counter { | |
4561 | u32 quota; | |
4562 | #if defined(__BIG_ENDIAN) | |
4563 | u16 __reserved0; | |
4564 | u16 rate; | |
4565 | #elif defined(__LITTLE_ENDIAN) | |
4566 | u16 rate; | |
4567 | u16 __reserved0; | |
4568 | #endif | |
4569 | }; | |
4570 | ||
4571 | /* | |
4572 | * per-vnic rate shaping variables | |
4573 | */ | |
4574 | struct rate_shaping_vars_per_vn { | |
4575 | struct rate_shaping_counter vn_counter; | |
4576 | }; | |
4577 | ||
4578 | /* | |
4579 | * per-vnic fairness variables | |
4580 | */ | |
4581 | struct fairness_vars_per_vn { | |
4582 | u32 cos_credit_delta[MAX_COS_NUMBER]; | |
4583 | u32 vn_credit_delta; | |
4584 | u32 __reserved0; | |
4585 | }; | |
4586 | ||
4587 | /* | |
4588 | * cmng port init state | |
4589 | */ | |
4590 | struct cmng_vnic { | |
4591 | struct rate_shaping_vars_per_vn vnic_max_rate[4]; | |
4592 | struct fairness_vars_per_vn vnic_min_rate[4]; | |
4593 | }; | |
4594 | ||
4595 | /* | |
4596 | * cmng port init state | |
4597 | */ | |
4598 | struct cmng_init { | |
4599 | struct cmng_struct_per_port port; | |
4600 | struct cmng_vnic vnic; | |
4601 | }; | |
4602 | ||
4603 | ||
4604 | /* | |
4605 | * driver parameters for congestion management init, all rates are in Mbps | |
4606 | */ | |
4607 | struct cmng_init_input { | |
4608 | u32 port_rate; | |
4609 | u16 vnic_min_rate[4]; | |
4610 | u16 vnic_max_rate[4]; | |
4611 | u16 cos_min_rate[MAX_COS_NUMBER]; | |
4612 | u16 cos_to_pause_mask[MAX_COS_NUMBER]; | |
4613 | struct cmng_flags_per_port flags; | |
4614 | }; | |
4615 | ||
a2fbb9ea | 4616 | |
619c5cb6 VZ |
4617 | /* |
4618 | * Protocol-common command ID for slow path elements | |
4619 | */ | |
4620 | enum common_spqe_cmd_id { | |
4621 | RAMROD_CMD_ID_COMMON_UNUSED, | |
4622 | RAMROD_CMD_ID_COMMON_FUNCTION_START, | |
4623 | RAMROD_CMD_ID_COMMON_FUNCTION_STOP, | |
621b4d66 | 4624 | RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, |
619c5cb6 VZ |
4625 | RAMROD_CMD_ID_COMMON_CFC_DEL, |
4626 | RAMROD_CMD_ID_COMMON_CFC_DEL_WB, | |
4627 | RAMROD_CMD_ID_COMMON_STAT_QUERY, | |
4628 | RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, | |
4629 | RAMROD_CMD_ID_COMMON_START_TRAFFIC, | |
a3348722 | 4630 | RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, |
619c5cb6 VZ |
4631 | MAX_COMMON_SPQE_CMD_ID |
4632 | }; | |
4633 | ||
4634 | ||
4635 | /* | |
4636 | * Per-protocol connection types | |
4637 | */ | |
4638 | enum connection_type { | |
4639 | ETH_CONNECTION_TYPE, | |
4640 | TOE_CONNECTION_TYPE, | |
4641 | RDMA_CONNECTION_TYPE, | |
4642 | ISCSI_CONNECTION_TYPE, | |
4643 | FCOE_CONNECTION_TYPE, | |
4644 | RESERVED_CONNECTION_TYPE_0, | |
4645 | RESERVED_CONNECTION_TYPE_1, | |
4646 | RESERVED_CONNECTION_TYPE_2, | |
4647 | NONE_CONNECTION_TYPE, | |
4648 | MAX_CONNECTION_TYPE | |
4649 | }; | |
4650 | ||
4651 | ||
4652 | /* | |
4653 | * Cos modes | |
4654 | */ | |
4655 | enum cos_mode { | |
4656 | OVERRIDE_COS, | |
4657 | STATIC_COS, | |
4658 | FW_WRR, | |
4659 | MAX_COS_MODE | |
4660 | }; | |
4661 | ||
523224a3 DK |
4662 | |
4663 | /* | |
4664 | * Dynamic HC counters set by the driver | |
4665 | */ | |
4666 | struct hc_dynamic_drv_counter { | |
4667 | u32 val[HC_SB_MAX_DYNAMIC_INDICES]; | |
4668 | }; | |
4669 | ||
4670 | /* | |
4671 | * zone A per-queue data | |
4672 | */ | |
4673 | struct cstorm_queue_zone_data { | |
4674 | struct hc_dynamic_drv_counter hc_dyn_drv_cnt; | |
4675 | struct regpair reserved[2]; | |
4676 | }; | |
4677 | ||
619c5cb6 | 4678 | |
ca00392c | 4679 | /* |
619c5cb6 | 4680 | * Vf-PF channel data in cstorm ram (non-triggered zone) |
ca00392c | 4681 | */ |
619c5cb6 VZ |
4682 | struct vf_pf_channel_zone_data { |
4683 | u32 msg_addr_lo; | |
4684 | u32 msg_addr_hi; | |
ca00392c EG |
4685 | }; |
4686 | ||
a2fbb9ea | 4687 | /* |
619c5cb6 | 4688 | * zone for VF non-triggered data |
a2fbb9ea | 4689 | */ |
619c5cb6 VZ |
4690 | struct non_trigger_vf_zone { |
4691 | struct vf_pf_channel_zone_data vf_pf_channel; | |
a2fbb9ea ET |
4692 | }; |
4693 | ||
bb2a0f7a | 4694 | /* |
619c5cb6 | 4695 | * Vf-PF channel trigger zone in cstorm ram |
bb2a0f7a | 4696 | */ |
619c5cb6 VZ |
4697 | struct vf_pf_channel_zone_trigger { |
4698 | u8 addr_valid; | |
bb2a0f7a YG |
4699 | }; |
4700 | ||
bb2a0f7a | 4701 | /* |
619c5cb6 | 4702 | * zone that triggers the in-bound interrupt |
bb2a0f7a | 4703 | */ |
619c5cb6 VZ |
4704 | struct trigger_vf_zone { |
4705 | #if defined(__BIG_ENDIAN) | |
4706 | u16 reserved1; | |
4707 | u8 reserved0; | |
4708 | struct vf_pf_channel_zone_trigger vf_pf_channel; | |
4709 | #elif defined(__LITTLE_ENDIAN) | |
4710 | struct vf_pf_channel_zone_trigger vf_pf_channel; | |
4711 | u8 reserved0; | |
4712 | u16 reserved1; | |
4713 | #endif | |
4714 | u32 reserved2; | |
bb2a0f7a YG |
4715 | }; |
4716 | ||
a2fbb9ea | 4717 | /* |
619c5cb6 | 4718 | * zone B per-VF data |
a2fbb9ea | 4719 | */ |
619c5cb6 VZ |
4720 | struct cstorm_vf_zone_data { |
4721 | struct non_trigger_vf_zone non_trigger; | |
4722 | struct trigger_vf_zone trigger; | |
a2fbb9ea ET |
4723 | }; |
4724 | ||
619c5cb6 | 4725 | |
a2fbb9ea | 4726 | /* |
619c5cb6 | 4727 | * Dynamic host coalescing init parameters, per state machine |
a2fbb9ea | 4728 | */ |
619c5cb6 VZ |
4729 | struct dynamic_hc_sm_config { |
4730 | u32 threshold[3]; | |
4731 | u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; | |
4732 | u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; | |
4733 | u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; | |
4734 | u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; | |
4735 | u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; | |
a2fbb9ea ET |
4736 | }; |
4737 | ||
de832a55 | 4738 | /* |
619c5cb6 | 4739 | * Dynamic host coalescing init parameters |
de832a55 | 4740 | */ |
619c5cb6 VZ |
4741 | struct dynamic_hc_config { |
4742 | struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; | |
4743 | }; | |
4744 | ||
4745 | ||
4746 | struct e2_integ_data { | |
4747 | #if defined(__BIG_ENDIAN) | |
4748 | u8 flags; | |
4749 | #define E2_INTEG_DATA_TESTING_EN (0x1<<0) | |
4750 | #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 | |
4751 | #define E2_INTEG_DATA_LB_TX (0x1<<1) | |
4752 | #define E2_INTEG_DATA_LB_TX_SHIFT 1 | |
4753 | #define E2_INTEG_DATA_COS_TX (0x1<<2) | |
4754 | #define E2_INTEG_DATA_COS_TX_SHIFT 2 | |
4755 | #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) | |
4756 | #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 | |
4757 | #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) | |
4758 | #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 | |
4759 | #define E2_INTEG_DATA_RESERVED (0x7<<5) | |
4760 | #define E2_INTEG_DATA_RESERVED_SHIFT 5 | |
4761 | u8 cos; | |
4762 | u8 voq; | |
4763 | u8 pbf_queue; | |
4764 | #elif defined(__LITTLE_ENDIAN) | |
4765 | u8 pbf_queue; | |
4766 | u8 voq; | |
4767 | u8 cos; | |
4768 | u8 flags; | |
4769 | #define E2_INTEG_DATA_TESTING_EN (0x1<<0) | |
4770 | #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 | |
4771 | #define E2_INTEG_DATA_LB_TX (0x1<<1) | |
4772 | #define E2_INTEG_DATA_LB_TX_SHIFT 1 | |
4773 | #define E2_INTEG_DATA_COS_TX (0x1<<2) | |
4774 | #define E2_INTEG_DATA_COS_TX_SHIFT 2 | |
4775 | #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) | |
4776 | #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 | |
4777 | #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) | |
4778 | #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 | |
4779 | #define E2_INTEG_DATA_RESERVED (0x7<<5) | |
4780 | #define E2_INTEG_DATA_RESERVED_SHIFT 5 | |
4781 | #endif | |
4782 | #if defined(__BIG_ENDIAN) | |
4783 | u16 reserved3; | |
4784 | u8 reserved2; | |
4785 | u8 ramEn; | |
4786 | #elif defined(__LITTLE_ENDIAN) | |
4787 | u8 ramEn; | |
4788 | u8 reserved2; | |
4789 | u16 reserved3; | |
4790 | #endif | |
de832a55 EG |
4791 | }; |
4792 | ||
619c5cb6 | 4793 | |
de832a55 | 4794 | /* |
619c5cb6 | 4795 | * set mac event data |
de832a55 | 4796 | */ |
619c5cb6 VZ |
4797 | struct eth_event_data { |
4798 | u32 echo; | |
4799 | u32 reserved0; | |
4800 | u32 reserved1; | |
de832a55 EG |
4801 | }; |
4802 | ||
619c5cb6 | 4803 | |
a2fbb9ea | 4804 | /* |
619c5cb6 | 4805 | * pf-vf event data |
a2fbb9ea | 4806 | */ |
619c5cb6 VZ |
4807 | struct vf_pf_event_data { |
4808 | u8 vf_id; | |
4809 | u8 reserved0; | |
4810 | u16 reserved1; | |
4811 | u32 msg_addr_lo; | |
4812 | u32 msg_addr_hi; | |
a2fbb9ea ET |
4813 | }; |
4814 | ||
619c5cb6 VZ |
4815 | /* |
4816 | * VF FLR event data | |
4817 | */ | |
4818 | struct vf_flr_event_data { | |
4819 | u8 vf_id; | |
4820 | u8 reserved0; | |
4821 | u16 reserved1; | |
4822 | u32 reserved2; | |
4823 | u32 reserved3; | |
4824 | }; | |
a2fbb9ea | 4825 | |
523224a3 | 4826 | /* |
619c5cb6 | 4827 | * malicious VF event data |
523224a3 | 4828 | */ |
619c5cb6 VZ |
4829 | struct malicious_vf_event_data { |
4830 | u8 vf_id; | |
4831 | u8 reserved0; | |
4832 | u16 reserved1; | |
523224a3 | 4833 | u32 reserved2; |
619c5cb6 | 4834 | u32 reserved3; |
523224a3 DK |
4835 | }; |
4836 | ||
a3348722 BW |
4837 | /* |
4838 | * vif list event data | |
4839 | */ | |
4840 | struct vif_list_event_data { | |
4841 | u8 func_bit_map; | |
4842 | u8 echo; | |
4843 | __le16 reserved0; | |
4844 | __le32 reserved1; | |
4845 | __le32 reserved2; | |
4846 | }; | |
4847 | ||
523224a3 DK |
4848 | /* |
4849 | * union for all event ring message types | |
4850 | */ | |
4851 | union event_data { | |
619c5cb6 VZ |
4852 | struct vf_pf_event_data vf_pf_event; |
4853 | struct eth_event_data eth_event; | |
523224a3 | 4854 | struct cfc_del_event_data cfc_del_event; |
619c5cb6 VZ |
4855 | struct vf_flr_event_data vf_flr_event; |
4856 | struct malicious_vf_event_data malicious_vf_event; | |
a3348722 | 4857 | struct vif_list_event_data vif_list_event; |
523224a3 DK |
4858 | }; |
4859 | ||
4860 | ||
4861 | /* | |
4862 | * per PF event ring data | |
4863 | */ | |
4864 | struct event_ring_data { | |
4865 | struct regpair base_addr; | |
4866 | #if defined(__BIG_ENDIAN) | |
4867 | u8 index_id; | |
4868 | u8 sb_id; | |
4869 | u16 producer; | |
4870 | #elif defined(__LITTLE_ENDIAN) | |
4871 | u16 producer; | |
4872 | u8 sb_id; | |
4873 | u8 index_id; | |
4874 | #endif | |
4875 | u32 reserved0; | |
4876 | }; | |
4877 | ||
4878 | ||
4879 | /* | |
4880 | * event ring message element (each element is 128 bits) | |
4881 | */ | |
4882 | struct event_ring_msg { | |
4883 | u8 opcode; | |
619c5cb6 | 4884 | u8 error; |
523224a3 DK |
4885 | u16 reserved1; |
4886 | union event_data data; | |
4887 | }; | |
4888 | ||
4889 | /* | |
4890 | * event ring next page element (128 bits) | |
4891 | */ | |
4892 | struct event_ring_next { | |
4893 | struct regpair addr; | |
4894 | u32 reserved[2]; | |
4895 | }; | |
4896 | ||
4897 | /* | |
4898 | * union for event ring element types (each element is 128 bits) | |
4899 | */ | |
4900 | union event_ring_elem { | |
4901 | struct event_ring_msg message; | |
4902 | struct event_ring_next next_page; | |
4903 | }; | |
4904 | ||
4905 | ||
619c5cb6 VZ |
4906 | /* |
4907 | * Common event ring opcodes | |
4908 | */ | |
4909 | enum event_ring_opcode { | |
4910 | EVENT_RING_OPCODE_VF_PF_CHANNEL, | |
4911 | EVENT_RING_OPCODE_FUNCTION_START, | |
4912 | EVENT_RING_OPCODE_FUNCTION_STOP, | |
4913 | EVENT_RING_OPCODE_CFC_DEL, | |
4914 | EVENT_RING_OPCODE_CFC_DEL_WB, | |
4915 | EVENT_RING_OPCODE_STAT_QUERY, | |
4916 | EVENT_RING_OPCODE_STOP_TRAFFIC, | |
4917 | EVENT_RING_OPCODE_START_TRAFFIC, | |
4918 | EVENT_RING_OPCODE_VF_FLR, | |
4919 | EVENT_RING_OPCODE_MALICIOUS_VF, | |
4920 | EVENT_RING_OPCODE_FORWARD_SETUP, | |
4921 | EVENT_RING_OPCODE_RSS_UPDATE_RULES, | |
621b4d66 | 4922 | EVENT_RING_OPCODE_FUNCTION_UPDATE, |
a3348722 | 4923 | EVENT_RING_OPCODE_AFEX_VIF_LISTS, |
619c5cb6 VZ |
4924 | EVENT_RING_OPCODE_SET_MAC, |
4925 | EVENT_RING_OPCODE_CLASSIFICATION_RULES, | |
4926 | EVENT_RING_OPCODE_FILTERS_RULES, | |
4927 | EVENT_RING_OPCODE_MULTICAST_RULES, | |
4928 | MAX_EVENT_RING_OPCODE | |
4929 | }; | |
4930 | ||
4931 | ||
4932 | /* | |
4933 | * Modes for fairness algorithm | |
4934 | */ | |
4935 | enum fairness_mode { | |
4936 | FAIRNESS_COS_WRR_MODE, | |
4937 | FAIRNESS_COS_ETS_MODE, | |
4938 | MAX_FAIRNESS_MODE | |
4939 | }; | |
4940 | ||
4941 | ||
619c5cb6 VZ |
4942 | /* |
4943 | * Priority and cos | |
4944 | */ | |
4945 | struct priority_cos { | |
4946 | u8 priority; | |
4947 | u8 cos; | |
4948 | __le16 reserved1; | |
4949 | }; | |
4950 | ||
e4901dde VZ |
4951 | /* |
4952 | * The data for flow control configuration | |
4953 | */ | |
4954 | struct flow_control_configuration { | |
619c5cb6 | 4955 | struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; |
e4901dde VZ |
4956 | u8 dcb_enabled; |
4957 | u8 dcb_version; | |
619c5cb6 VZ |
4958 | u8 dont_add_pri_0_en; |
4959 | u8 reserved1; | |
4960 | __le32 reserved2; | |
4961 | }; | |
4962 | ||
4963 | ||
4964 | /* | |
4965 | * | |
4966 | */ | |
4967 | struct function_start_data { | |
96bed4b9 YM |
4968 | u8 function_mode; |
4969 | u8 reserved; | |
619c5cb6 | 4970 | __le16 sd_vlan_tag; |
a3348722 | 4971 | __le16 vif_id; |
619c5cb6 VZ |
4972 | u8 path_id; |
4973 | u8 network_cos_mode; | |
e4901dde VZ |
4974 | }; |
4975 | ||
4976 | ||
a3348722 BW |
4977 | struct function_update_data { |
4978 | u8 vif_id_change_flg; | |
4979 | u8 afex_default_vlan_change_flg; | |
4980 | u8 allowed_priorities_change_flg; | |
4981 | u8 network_cos_mode_change_flg; | |
4982 | __le16 vif_id; | |
4983 | __le16 afex_default_vlan; | |
4984 | u8 allowed_priorities; | |
4985 | u8 network_cos_mode; | |
4986 | u8 lb_mode_en; | |
4987 | u8 reserved0; | |
4988 | __le32 reserved1; | |
4989 | }; | |
4990 | ||
4991 | ||
a2fbb9ea ET |
4992 | /* |
4993 | * FW version stored in the Xstorm RAM | |
4994 | */ | |
4995 | struct fw_version { | |
4996 | #if defined(__BIG_ENDIAN) | |
8d9c5f34 EG |
4997 | u8 engineering; |
4998 | u8 revision; | |
4999 | u8 minor; | |
5000 | u8 major; | |
a2fbb9ea | 5001 | #elif defined(__LITTLE_ENDIAN) |
8d9c5f34 EG |
5002 | u8 major; |
5003 | u8 minor; | |
5004 | u8 revision; | |
5005 | u8 engineering; | |
a2fbb9ea ET |
5006 | #endif |
5007 | u32 flags; | |
5008 | #define FW_VERSION_OPTIMIZED (0x1<<0) | |
5009 | #define FW_VERSION_OPTIMIZED_SHIFT 0 | |
5010 | #define FW_VERSION_BIG_ENDIEN (0x1<<1) | |
5011 | #define FW_VERSION_BIG_ENDIEN_SHIFT 1 | |
34f80b04 EG |
5012 | #define FW_VERSION_CHIP_VERSION (0x3<<2) |
5013 | #define FW_VERSION_CHIP_VERSION_SHIFT 2 | |
5014 | #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) | |
5015 | #define __FW_VERSION_RESERVED_SHIFT 4 | |
a2fbb9ea ET |
5016 | }; |
5017 | ||
5018 | ||
523224a3 DK |
5019 | /* |
5020 | * Dynamic Host-Coalescing - Driver(host) counters | |
5021 | */ | |
5022 | struct hc_dynamic_sb_drv_counters { | |
5023 | u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; | |
5024 | }; | |
5025 | ||
5026 | ||
5027 | /* | |
5028 | * 2 bytes. configuration/state parameters for a single protocol index | |
5029 | */ | |
5030 | struct hc_index_data { | |
5031 | #if defined(__BIG_ENDIAN) | |
5032 | u8 flags; | |
5033 | #define HC_INDEX_DATA_SM_ID (0x1<<0) | |
5034 | #define HC_INDEX_DATA_SM_ID_SHIFT 0 | |
5035 | #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) | |
5036 | #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 | |
5037 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) | |
5038 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 | |
5039 | #define HC_INDEX_DATA_RESERVE (0x1F<<3) | |
5040 | #define HC_INDEX_DATA_RESERVE_SHIFT 3 | |
5041 | u8 timeout; | |
5042 | #elif defined(__LITTLE_ENDIAN) | |
5043 | u8 timeout; | |
5044 | u8 flags; | |
5045 | #define HC_INDEX_DATA_SM_ID (0x1<<0) | |
5046 | #define HC_INDEX_DATA_SM_ID_SHIFT 0 | |
5047 | #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) | |
5048 | #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 | |
5049 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) | |
5050 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 | |
5051 | #define HC_INDEX_DATA_RESERVE (0x1F<<3) | |
5052 | #define HC_INDEX_DATA_RESERVE_SHIFT 3 | |
5053 | #endif | |
5054 | }; | |
5055 | ||
5056 | ||
5057 | /* | |
5058 | * HC state-machine | |
5059 | */ | |
5060 | struct hc_status_block_sm { | |
5061 | #if defined(__BIG_ENDIAN) | |
5062 | u8 igu_seg_id; | |
5063 | u8 igu_sb_id; | |
5064 | u8 timer_value; | |
5065 | u8 __flags; | |
5066 | #elif defined(__LITTLE_ENDIAN) | |
5067 | u8 __flags; | |
5068 | u8 timer_value; | |
5069 | u8 igu_sb_id; | |
5070 | u8 igu_seg_id; | |
5071 | #endif | |
5072 | u32 time_to_expire; | |
5073 | }; | |
5074 | ||
5075 | /* | |
5076 | * hold PCI identification variables- used in various places in firmware | |
5077 | */ | |
5078 | struct pci_entity { | |
5079 | #if defined(__BIG_ENDIAN) | |
5080 | u8 vf_valid; | |
5081 | u8 vf_id; | |
5082 | u8 vnic_id; | |
5083 | u8 pf_id; | |
5084 | #elif defined(__LITTLE_ENDIAN) | |
5085 | u8 pf_id; | |
5086 | u8 vnic_id; | |
5087 | u8 vf_id; | |
5088 | u8 vf_valid; | |
5089 | #endif | |
5090 | }; | |
5091 | ||
5092 | /* | |
5093 | * The fast-path status block meta-data, common to all chips | |
5094 | */ | |
5095 | struct hc_sb_data { | |
5096 | struct regpair host_sb_addr; | |
5097 | struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; | |
5098 | struct pci_entity p_func; | |
5099 | #if defined(__BIG_ENDIAN) | |
5100 | u8 rsrv0; | |
619c5cb6 | 5101 | u8 state; |
523224a3 | 5102 | u8 dhc_qzone_id; |
523224a3 DK |
5103 | u8 same_igu_sb_1b; |
5104 | #elif defined(__LITTLE_ENDIAN) | |
5105 | u8 same_igu_sb_1b; | |
523224a3 | 5106 | u8 dhc_qzone_id; |
619c5cb6 | 5107 | u8 state; |
523224a3 DK |
5108 | u8 rsrv0; |
5109 | #endif | |
5110 | struct regpair rsrv1[2]; | |
5111 | }; | |
5112 | ||
5113 | ||
619c5cb6 VZ |
5114 | /* |
5115 | * Segment types for host coaslescing | |
5116 | */ | |
5117 | enum hc_segment { | |
5118 | HC_REGULAR_SEGMENT, | |
5119 | HC_DEFAULT_SEGMENT, | |
5120 | MAX_HC_SEGMENT | |
5121 | }; | |
5122 | ||
5123 | ||
523224a3 DK |
5124 | /* |
5125 | * The fast-path status block meta-data | |
5126 | */ | |
5127 | struct hc_sp_status_block_data { | |
5128 | struct regpair host_sb_addr; | |
5129 | #if defined(__BIG_ENDIAN) | |
619c5cb6 VZ |
5130 | u8 rsrv1; |
5131 | u8 state; | |
523224a3 DK |
5132 | u8 igu_seg_id; |
5133 | u8 igu_sb_id; | |
5134 | #elif defined(__LITTLE_ENDIAN) | |
5135 | u8 igu_sb_id; | |
5136 | u8 igu_seg_id; | |
619c5cb6 VZ |
5137 | u8 state; |
5138 | u8 rsrv1; | |
523224a3 DK |
5139 | #endif |
5140 | struct pci_entity p_func; | |
5141 | }; | |
5142 | ||
5143 | ||
5144 | /* | |
5145 | * The fast-path status block meta-data | |
5146 | */ | |
5147 | struct hc_status_block_data_e1x { | |
5148 | struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; | |
5149 | struct hc_sb_data common; | |
5150 | }; | |
5151 | ||
5152 | ||
5153 | /* | |
5154 | * The fast-path status block meta-data | |
5155 | */ | |
5156 | struct hc_status_block_data_e2 { | |
5157 | struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; | |
5158 | struct hc_sb_data common; | |
5159 | }; | |
5160 | ||
5161 | ||
619c5cb6 VZ |
5162 | /* |
5163 | * IGU block operartion modes (in Everest2) | |
5164 | */ | |
5165 | enum igu_mode { | |
5166 | HC_IGU_BC_MODE, | |
5167 | HC_IGU_NBC_MODE, | |
5168 | MAX_IGU_MODE | |
5169 | }; | |
5170 | ||
5171 | ||
5172 | /* | |
5173 | * IP versions | |
5174 | */ | |
5175 | enum ip_ver { | |
5176 | IP_V4, | |
5177 | IP_V6, | |
5178 | MAX_IP_VER | |
5179 | }; | |
5180 | ||
5181 | ||
5182 | /* | |
5183 | * Multi-function modes | |
5184 | */ | |
5185 | enum mf_mode { | |
5186 | SINGLE_FUNCTION, | |
5187 | MULTI_FUNCTION_SD, | |
5188 | MULTI_FUNCTION_SI, | |
a3348722 | 5189 | MULTI_FUNCTION_AFEX, |
619c5cb6 VZ |
5190 | MAX_MF_MODE |
5191 | }; | |
5192 | ||
5193 | /* | |
5194 | * Protocol-common statistics collected by the Tstorm (per pf) | |
5195 | */ | |
5196 | struct tstorm_per_pf_stats { | |
5197 | struct regpair rcv_error_bytes; | |
5198 | }; | |
5199 | ||
5200 | /* | |
5201 | * | |
5202 | */ | |
5203 | struct per_pf_stats { | |
5204 | struct tstorm_per_pf_stats tstorm_pf_statistics; | |
5205 | }; | |
5206 | ||
5207 | ||
5208 | /* | |
5209 | * Protocol-common statistics collected by the Tstorm (per port) | |
5210 | */ | |
5211 | struct tstorm_per_port_stats { | |
5212 | __le32 mac_discard; | |
5213 | __le32 mac_filter_discard; | |
5214 | __le32 brb_truncate_discard; | |
5215 | __le32 mf_tag_discard; | |
5216 | __le32 packet_drop; | |
5217 | __le32 reserved; | |
5218 | }; | |
5219 | ||
5220 | /* | |
5221 | * | |
5222 | */ | |
5223 | struct per_port_stats { | |
5224 | struct tstorm_per_port_stats tstorm_port_statistics; | |
5225 | }; | |
5226 | ||
5227 | ||
5228 | /* | |
5229 | * Protocol-common statistics collected by the Tstorm (per client) | |
5230 | */ | |
5231 | struct tstorm_per_queue_stats { | |
5232 | struct regpair rcv_ucast_bytes; | |
5233 | __le32 rcv_ucast_pkts; | |
5234 | __le32 checksum_discard; | |
5235 | struct regpair rcv_bcast_bytes; | |
5236 | __le32 rcv_bcast_pkts; | |
5237 | __le32 pkts_too_big_discard; | |
5238 | struct regpair rcv_mcast_bytes; | |
5239 | __le32 rcv_mcast_pkts; | |
5240 | __le32 ttl0_discard; | |
5241 | __le16 no_buff_discard; | |
5242 | __le16 reserved0; | |
5243 | __le32 reserved1; | |
5244 | }; | |
5245 | ||
5246 | /* | |
5247 | * Protocol-common statistics collected by the Ustorm (per client) | |
5248 | */ | |
5249 | struct ustorm_per_queue_stats { | |
5250 | struct regpair ucast_no_buff_bytes; | |
5251 | struct regpair mcast_no_buff_bytes; | |
5252 | struct regpair bcast_no_buff_bytes; | |
5253 | __le32 ucast_no_buff_pkts; | |
5254 | __le32 mcast_no_buff_pkts; | |
5255 | __le32 bcast_no_buff_pkts; | |
5256 | __le32 coalesced_pkts; | |
5257 | struct regpair coalesced_bytes; | |
5258 | __le32 coalesced_events; | |
5259 | __le32 coalesced_aborts; | |
5260 | }; | |
5261 | ||
5262 | /* | |
5263 | * Protocol-common statistics collected by the Xstorm (per client) | |
5264 | */ | |
5265 | struct xstorm_per_queue_stats { | |
5266 | struct regpair ucast_bytes_sent; | |
5267 | struct regpair mcast_bytes_sent; | |
5268 | struct regpair bcast_bytes_sent; | |
5269 | __le32 ucast_pkts_sent; | |
5270 | __le32 mcast_pkts_sent; | |
5271 | __le32 bcast_pkts_sent; | |
5272 | __le32 error_drop_pkts; | |
5273 | }; | |
5274 | ||
5275 | /* | |
5276 | * | |
5277 | */ | |
5278 | struct per_queue_stats { | |
5279 | struct tstorm_per_queue_stats tstorm_queue_statistics; | |
5280 | struct ustorm_per_queue_stats ustorm_queue_statistics; | |
5281 | struct xstorm_per_queue_stats xstorm_queue_statistics; | |
5282 | }; | |
5283 | ||
5284 | ||
a2fbb9ea ET |
5285 | /* |
5286 | * FW version stored in first line of pram | |
5287 | */ | |
5288 | struct pram_fw_version { | |
8d9c5f34 EG |
5289 | u8 major; |
5290 | u8 minor; | |
5291 | u8 revision; | |
5292 | u8 engineering; | |
a2fbb9ea ET |
5293 | u8 flags; |
5294 | #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) | |
5295 | #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 | |
5296 | #define PRAM_FW_VERSION_STORM_ID (0x3<<1) | |
5297 | #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 | |
5298 | #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) | |
5299 | #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 | |
34f80b04 EG |
5300 | #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) |
5301 | #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 | |
5302 | #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) | |
5303 | #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 | |
5304 | }; | |
5305 | ||
5306 | ||
523224a3 DK |
5307 | /* |
5308 | * Ethernet slow path element | |
5309 | */ | |
5310 | union protocol_common_specific_data { | |
5311 | u8 protocol_data[8]; | |
5312 | struct regpair phy_address; | |
5313 | struct regpair mac_config_addr; | |
a3348722 | 5314 | struct afex_vif_list_ramrod_data afex_vif_list_data; |
523224a3 DK |
5315 | }; |
5316 | ||
ca00392c EG |
5317 | /* |
5318 | * The send queue element | |
5319 | */ | |
5320 | struct protocol_common_spe { | |
5321 | struct spe_hdr hdr; | |
523224a3 | 5322 | union protocol_common_specific_data data; |
ca00392c EG |
5323 | }; |
5324 | ||
5325 | ||
a2fbb9ea ET |
5326 | /* |
5327 | * The send queue element | |
5328 | */ | |
5329 | struct slow_path_element { | |
5330 | struct spe_hdr hdr; | |
523224a3 | 5331 | struct regpair protocol_data; |
a2fbb9ea ET |
5332 | }; |
5333 | ||
5334 | ||
5335 | /* | |
619c5cb6 | 5336 | * Protocol-common statistics counter |
a2fbb9ea | 5337 | */ |
619c5cb6 VZ |
5338 | struct stats_counter { |
5339 | __le16 xstats_counter; | |
5340 | __le16 reserved0; | |
5341 | __le32 reserved1; | |
5342 | __le16 tstats_counter; | |
5343 | __le16 reserved2; | |
5344 | __le32 reserved3; | |
5345 | __le16 ustats_counter; | |
5346 | __le16 reserved4; | |
5347 | __le32 reserved5; | |
5348 | __le16 cstats_counter; | |
5349 | __le16 reserved6; | |
5350 | __le32 reserved7; | |
a2fbb9ea ET |
5351 | }; |
5352 | ||
5353 | ||
523224a3 | 5354 | /* |
619c5cb6 | 5355 | * |
523224a3 | 5356 | */ |
619c5cb6 VZ |
5357 | struct stats_query_entry { |
5358 | u8 kind; | |
5359 | u8 index; | |
5360 | __le16 funcID; | |
5361 | __le32 reserved; | |
5362 | struct regpair address; | |
523224a3 DK |
5363 | }; |
5364 | ||
5365 | /* | |
619c5cb6 | 5366 | * statistic command |
523224a3 | 5367 | */ |
619c5cb6 VZ |
5368 | struct stats_query_cmd_group { |
5369 | struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; | |
5370 | }; | |
5371 | ||
5372 | ||
5373 | /* | |
5374 | * statistic command header | |
5375 | */ | |
5376 | struct stats_query_header { | |
5377 | u8 cmd_num; | |
5378 | u8 reserved0; | |
5379 | __le16 drv_stats_counter; | |
5380 | __le32 reserved1; | |
5381 | struct regpair stats_counters_addrs; | |
5382 | }; | |
5383 | ||
5384 | ||
5385 | /* | |
5386 | * Types of statistcis query entry | |
5387 | */ | |
5388 | enum stats_query_type { | |
5389 | STATS_TYPE_QUEUE, | |
5390 | STATS_TYPE_PORT, | |
5391 | STATS_TYPE_PF, | |
5392 | STATS_TYPE_TOE, | |
5393 | STATS_TYPE_FCOE, | |
5394 | MAX_STATS_QUERY_TYPE | |
5395 | }; | |
5396 | ||
5397 | ||
5398 | /* | |
5399 | * Indicate of the function status block state | |
5400 | */ | |
5401 | enum status_block_state { | |
5402 | SB_DISABLED, | |
5403 | SB_ENABLED, | |
5404 | SB_CLEANED, | |
5405 | MAX_STATUS_BLOCK_STATE | |
5406 | }; | |
5407 | ||
5408 | ||
5409 | /* | |
5410 | * Storm IDs (including attentions for IGU related enums) | |
5411 | */ | |
5412 | enum storm_id { | |
5413 | USTORM_ID, | |
5414 | CSTORM_ID, | |
5415 | XSTORM_ID, | |
5416 | TSTORM_ID, | |
5417 | ATTENTION_ID, | |
5418 | MAX_STORM_ID | |
5419 | }; | |
5420 | ||
5421 | ||
5422 | /* | |
5423 | * Taffic types used in ETS and flow control algorithms | |
5424 | */ | |
5425 | enum traffic_type { | |
5426 | LLFC_TRAFFIC_TYPE_NW, | |
5427 | LLFC_TRAFFIC_TYPE_FCOE, | |
5428 | LLFC_TRAFFIC_TYPE_ISCSI, | |
5429 | MAX_TRAFFIC_TYPE | |
523224a3 DK |
5430 | }; |
5431 | ||
5432 | ||
5433 | /* | |
5434 | * zone A per-queue data | |
5435 | */ | |
5436 | struct tstorm_queue_zone_data { | |
5437 | struct regpair reserved[4]; | |
5438 | }; | |
5439 | ||
5440 | ||
5441 | /* | |
5442 | * zone B per-VF data | |
5443 | */ | |
5444 | struct tstorm_vf_zone_data { | |
5445 | struct regpair reserved; | |
5446 | }; | |
5447 | ||
5448 | ||
5449 | /* | |
5450 | * zone A per-queue data | |
5451 | */ | |
5452 | struct ustorm_queue_zone_data { | |
5453 | struct ustorm_eth_rx_producers eth_rx_producers; | |
5454 | struct regpair reserved[3]; | |
5455 | }; | |
5456 | ||
5457 | ||
5458 | /* | |
5459 | * zone B per-VF data | |
5460 | */ | |
5461 | struct ustorm_vf_zone_data { | |
5462 | struct regpair reserved; | |
5463 | }; | |
5464 | ||
5465 | ||
5466 | /* | |
5467 | * data per VF-PF channel | |
5468 | */ | |
5469 | struct vf_pf_channel_data { | |
5470 | #if defined(__BIG_ENDIAN) | |
5471 | u16 reserved0; | |
5472 | u8 valid; | |
5473 | u8 state; | |
5474 | #elif defined(__LITTLE_ENDIAN) | |
5475 | u8 state; | |
5476 | u8 valid; | |
5477 | u16 reserved0; | |
5478 | #endif | |
5479 | u32 reserved1; | |
5480 | }; | |
5481 | ||
5482 | ||
619c5cb6 VZ |
5483 | /* |
5484 | * State of VF-PF channel | |
5485 | */ | |
5486 | enum vf_pf_channel_state { | |
5487 | VF_PF_CHANNEL_STATE_READY, | |
5488 | VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, | |
5489 | MAX_VF_PF_CHANNEL_STATE | |
5490 | }; | |
5491 | ||
5492 | ||
a3348722 BW |
5493 | /* |
5494 | * vif_list_rule_kind | |
5495 | */ | |
5496 | enum vif_list_rule_kind { | |
5497 | VIF_LIST_RULE_SET, | |
5498 | VIF_LIST_RULE_GET, | |
5499 | VIF_LIST_RULE_CLEAR_ALL, | |
5500 | VIF_LIST_RULE_CLEAR_FUNC, | |
5501 | MAX_VIF_LIST_RULE_KIND | |
5502 | }; | |
5503 | ||
5504 | ||
523224a3 DK |
5505 | /* |
5506 | * zone A per-queue data | |
5507 | */ | |
5508 | struct xstorm_queue_zone_data { | |
5509 | struct regpair reserved[4]; | |
5510 | }; | |
5511 | ||
5512 | ||
5513 | /* | |
5514 | * zone B per-VF data | |
5515 | */ | |
5516 | struct xstorm_vf_zone_data { | |
5517 | struct regpair reserved; | |
5518 | }; | |
5519 | ||
5520 | #endif /* BNX2X_HSI_H */ |