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a2fbb9ea ET |
1 | /* bnx2x_hsi.h: Broadcom Everest network driver. |
2 | * | |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | */ | |
523224a3 DK |
9 | #ifndef BNX2X_HSI_H |
10 | #define BNX2X_HSI_H | |
11 | ||
12 | #include "bnx2x_fw_defs.h" | |
2e499d3c | 13 | #include "bnx2x_mfw_req.h" |
a2fbb9ea | 14 | |
619c5cb6 | 15 | #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e |
2ba45142 | 16 | |
e2513065 MC |
17 | struct license_key { |
18 | u32 reserved[6]; | |
19 | ||
2ba45142 VZ |
20 | u32 max_iscsi_conn; |
21 | #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF | |
22 | #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 | |
23 | #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 | |
24 | #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 | |
e2513065 | 25 | |
2ba45142 | 26 | u32 reserved_a; |
e2513065 | 27 | |
2ba45142 VZ |
28 | u32 max_fcoe_conn; |
29 | #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF | |
30 | #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 | |
31 | #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 | |
32 | #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 | |
33 | ||
34 | u32 reserved_b[4]; | |
35 | }; | |
a2fbb9ea | 36 | |
a2fbb9ea | 37 | /**************************************************************************** |
619c5cb6 | 38 | * Shared HW configuration * |
a2fbb9ea | 39 | ****************************************************************************/ |
619c5cb6 VZ |
40 | #define PIN_CFG_NA 0x00000000 |
41 | #define PIN_CFG_GPIO0_P0 0x00000001 | |
42 | #define PIN_CFG_GPIO1_P0 0x00000002 | |
43 | #define PIN_CFG_GPIO2_P0 0x00000003 | |
44 | #define PIN_CFG_GPIO3_P0 0x00000004 | |
45 | #define PIN_CFG_GPIO0_P1 0x00000005 | |
46 | #define PIN_CFG_GPIO1_P1 0x00000006 | |
47 | #define PIN_CFG_GPIO2_P1 0x00000007 | |
48 | #define PIN_CFG_GPIO3_P1 0x00000008 | |
49 | #define PIN_CFG_EPIO0 0x00000009 | |
50 | #define PIN_CFG_EPIO1 0x0000000a | |
51 | #define PIN_CFG_EPIO2 0x0000000b | |
52 | #define PIN_CFG_EPIO3 0x0000000c | |
53 | #define PIN_CFG_EPIO4 0x0000000d | |
54 | #define PIN_CFG_EPIO5 0x0000000e | |
55 | #define PIN_CFG_EPIO6 0x0000000f | |
56 | #define PIN_CFG_EPIO7 0x00000010 | |
57 | #define PIN_CFG_EPIO8 0x00000011 | |
58 | #define PIN_CFG_EPIO9 0x00000012 | |
59 | #define PIN_CFG_EPIO10 0x00000013 | |
60 | #define PIN_CFG_EPIO11 0x00000014 | |
61 | #define PIN_CFG_EPIO12 0x00000015 | |
62 | #define PIN_CFG_EPIO13 0x00000016 | |
63 | #define PIN_CFG_EPIO14 0x00000017 | |
64 | #define PIN_CFG_EPIO15 0x00000018 | |
65 | #define PIN_CFG_EPIO16 0x00000019 | |
66 | #define PIN_CFG_EPIO17 0x0000001a | |
67 | #define PIN_CFG_EPIO18 0x0000001b | |
68 | #define PIN_CFG_EPIO19 0x0000001c | |
69 | #define PIN_CFG_EPIO20 0x0000001d | |
70 | #define PIN_CFG_EPIO21 0x0000001e | |
71 | #define PIN_CFG_EPIO22 0x0000001f | |
72 | #define PIN_CFG_EPIO23 0x00000020 | |
73 | #define PIN_CFG_EPIO24 0x00000021 | |
74 | #define PIN_CFG_EPIO25 0x00000022 | |
75 | #define PIN_CFG_EPIO26 0x00000023 | |
76 | #define PIN_CFG_EPIO27 0x00000024 | |
77 | #define PIN_CFG_EPIO28 0x00000025 | |
78 | #define PIN_CFG_EPIO29 0x00000026 | |
79 | #define PIN_CFG_EPIO30 0x00000027 | |
80 | #define PIN_CFG_EPIO31 0x00000028 | |
81 | ||
82 | /* EPIO definition */ | |
83 | #define EPIO_CFG_NA 0x00000000 | |
84 | #define EPIO_CFG_EPIO0 0x00000001 | |
85 | #define EPIO_CFG_EPIO1 0x00000002 | |
86 | #define EPIO_CFG_EPIO2 0x00000003 | |
87 | #define EPIO_CFG_EPIO3 0x00000004 | |
88 | #define EPIO_CFG_EPIO4 0x00000005 | |
89 | #define EPIO_CFG_EPIO5 0x00000006 | |
90 | #define EPIO_CFG_EPIO6 0x00000007 | |
91 | #define EPIO_CFG_EPIO7 0x00000008 | |
92 | #define EPIO_CFG_EPIO8 0x00000009 | |
93 | #define EPIO_CFG_EPIO9 0x0000000a | |
94 | #define EPIO_CFG_EPIO10 0x0000000b | |
95 | #define EPIO_CFG_EPIO11 0x0000000c | |
96 | #define EPIO_CFG_EPIO12 0x0000000d | |
97 | #define EPIO_CFG_EPIO13 0x0000000e | |
98 | #define EPIO_CFG_EPIO14 0x0000000f | |
99 | #define EPIO_CFG_EPIO15 0x00000010 | |
100 | #define EPIO_CFG_EPIO16 0x00000011 | |
101 | #define EPIO_CFG_EPIO17 0x00000012 | |
102 | #define EPIO_CFG_EPIO18 0x00000013 | |
103 | #define EPIO_CFG_EPIO19 0x00000014 | |
104 | #define EPIO_CFG_EPIO20 0x00000015 | |
105 | #define EPIO_CFG_EPIO21 0x00000016 | |
106 | #define EPIO_CFG_EPIO22 0x00000017 | |
107 | #define EPIO_CFG_EPIO23 0x00000018 | |
108 | #define EPIO_CFG_EPIO24 0x00000019 | |
109 | #define EPIO_CFG_EPIO25 0x0000001a | |
110 | #define EPIO_CFG_EPIO26 0x0000001b | |
111 | #define EPIO_CFG_EPIO27 0x0000001c | |
112 | #define EPIO_CFG_EPIO28 0x0000001d | |
113 | #define EPIO_CFG_EPIO29 0x0000001e | |
114 | #define EPIO_CFG_EPIO30 0x0000001f | |
115 | #define EPIO_CFG_EPIO31 0x00000020 | |
116 | ||
91226790 DK |
117 | struct mac_addr { |
118 | u32 upper; | |
119 | u32 lower; | |
120 | }; | |
619c5cb6 VZ |
121 | |
122 | struct shared_hw_cfg { /* NVRAM Offset */ | |
a2fbb9ea | 123 | /* Up to 16 bytes of NULL-terminated string */ |
619c5cb6 VZ |
124 | u8 part_num[16]; /* 0x104 */ |
125 | ||
126 | u32 config; /* 0x114 */ | |
127 | #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 | |
128 | #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 | |
129 | #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 | |
130 | #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 | |
131 | #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 | |
a2fbb9ea | 132 | |
619c5cb6 | 133 | #define SHARED_HW_CFG_PORT_SWAP 0x00000004 |
a2fbb9ea | 134 | |
619c5cb6 | 135 | #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 |
a2fbb9ea | 136 | |
619c5cb6 VZ |
137 | #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 |
138 | #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 | |
a2fbb9ea | 139 | |
619c5cb6 VZ |
140 | #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 |
141 | #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 | |
a2fbb9ea ET |
142 | /* Whatever MFW found in NVM |
143 | (if multiple found, priority order is: NC-SI, UMP, IPMI) */ | |
619c5cb6 VZ |
144 | #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 |
145 | #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 | |
146 | #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 | |
147 | #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 | |
a2fbb9ea ET |
148 | /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI |
149 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
619c5cb6 | 150 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 |
a2fbb9ea ET |
151 | /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI |
152 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
619c5cb6 | 153 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 |
a2fbb9ea ET |
154 | /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP |
155 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
619c5cb6 VZ |
156 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 |
157 | ||
158 | #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 | |
159 | #define SHARED_HW_CFG_LED_MODE_SHIFT 16 | |
160 | #define SHARED_HW_CFG_LED_MAC1 0x00000000 | |
161 | #define SHARED_HW_CFG_LED_PHY1 0x00010000 | |
162 | #define SHARED_HW_CFG_LED_PHY2 0x00020000 | |
163 | #define SHARED_HW_CFG_LED_PHY3 0x00030000 | |
164 | #define SHARED_HW_CFG_LED_MAC2 0x00040000 | |
165 | #define SHARED_HW_CFG_LED_PHY4 0x00050000 | |
166 | #define SHARED_HW_CFG_LED_PHY5 0x00060000 | |
167 | #define SHARED_HW_CFG_LED_PHY6 0x00070000 | |
168 | #define SHARED_HW_CFG_LED_MAC3 0x00080000 | |
169 | #define SHARED_HW_CFG_LED_PHY7 0x00090000 | |
170 | #define SHARED_HW_CFG_LED_PHY9 0x000a0000 | |
171 | #define SHARED_HW_CFG_LED_PHY11 0x000b0000 | |
172 | #define SHARED_HW_CFG_LED_MAC4 0x000c0000 | |
173 | #define SHARED_HW_CFG_LED_PHY8 0x000d0000 | |
174 | #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 | |
7dc950ca | 175 | #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 |
619c5cb6 VZ |
176 | |
177 | ||
178 | #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 | |
179 | #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 | |
180 | #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 | |
181 | #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 | |
182 | #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 | |
183 | #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 | |
184 | #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 | |
185 | #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 | |
186 | ||
187 | #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 | |
188 | #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 | |
189 | #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 | |
190 | ||
191 | #define SHARED_HW_CFG_ATC_MASK 0x80000000 | |
192 | #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 | |
193 | #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 | |
194 | ||
195 | u32 config2; /* 0x118 */ | |
a2fbb9ea | 196 | /* one time auto detect grace period (in sec) */ |
619c5cb6 VZ |
197 | #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff |
198 | #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 | |
a2fbb9ea | 199 | |
619c5cb6 VZ |
200 | #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 |
201 | #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 | |
a2fbb9ea ET |
202 | |
203 | /* The default value for the core clock is 250MHz and it is | |
204 | achieved by setting the clock change to 4 */ | |
619c5cb6 VZ |
205 | #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 |
206 | #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 | |
a2fbb9ea | 207 | |
619c5cb6 VZ |
208 | #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 |
209 | #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 | |
210 | #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 | |
a2fbb9ea | 211 | |
619c5cb6 | 212 | #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 |
a2fbb9ea | 213 | |
619c5cb6 VZ |
214 | #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 |
215 | #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 | |
216 | #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 | |
217 | ||
218 | /* Output low when PERST is asserted */ | |
219 | #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 | |
220 | #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 | |
221 | #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 | |
a2fbb9ea | 222 | |
619c5cb6 VZ |
223 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 |
224 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 | |
225 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 | |
226 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 | |
227 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 | |
228 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 | |
229 | ||
230 | /* The fan failure mechanism is usually related to the PHY type | |
231 | since the power consumption of the board is determined by the PHY. | |
232 | Currently, fan is required for most designs with SFX7101, BCM8727 | |
233 | and BCM8481. If a fan is not required for a board which uses one | |
234 | of those PHYs, this field should be set to "Disabled". If a fan is | |
235 | required for a different PHY type, this option should be set to | |
236 | "Enabled". The fan failure indication is expected on SPIO5 */ | |
237 | #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 | |
238 | #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 | |
239 | #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 | |
240 | #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 | |
241 | #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 | |
242 | ||
243 | /* ASPM Power Management support */ | |
244 | #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 | |
245 | #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 | |
246 | #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 | |
247 | #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 | |
248 | #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 | |
249 | #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 | |
250 | ||
251 | /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register | |
252 | tl_control_0 (register 0x2800) */ | |
253 | #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 | |
254 | #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 | |
255 | #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 | |
256 | ||
257 | #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 | |
258 | #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 | |
259 | #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 | |
260 | ||
261 | #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 | |
262 | #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 | |
263 | #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 | |
264 | ||
265 | /* Set the MDC/MDIO access for the first external phy */ | |
266 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 | |
267 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 | |
268 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 | |
269 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 | |
270 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 | |
271 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 | |
272 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 | |
273 | ||
274 | /* Set the MDC/MDIO access for the second external phy */ | |
275 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 | |
276 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 | |
277 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 | |
278 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 | |
279 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 | |
280 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 | |
281 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 | |
282 | ||
283 | ||
284 | u32 power_dissipated; /* 0x11c */ | |
285 | #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 | |
286 | #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 | |
287 | #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 | |
288 | #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 | |
289 | #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 | |
290 | #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 | |
291 | ||
292 | #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 | |
293 | #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 | |
294 | ||
295 | u32 ump_nc_si_config; /* 0x120 */ | |
296 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 | |
297 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 | |
298 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 | |
299 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 | |
300 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 | |
301 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 | |
302 | ||
303 | #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 | |
304 | #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 | |
305 | ||
306 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 | |
307 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 | |
308 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 | |
309 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 | |
310 | ||
311 | u32 board; /* 0x124 */ | |
312 | #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F | |
313 | #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 | |
314 | #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 | |
315 | #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 | |
316 | /* Use the PIN_CFG_XXX defines on top */ | |
317 | #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 | |
318 | #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 | |
319 | ||
320 | #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 | |
321 | #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 | |
322 | ||
323 | #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 | |
324 | #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 | |
325 | ||
326 | u32 wc_lane_config; /* 0x128 */ | |
327 | #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF | |
328 | #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 | |
329 | #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b | |
330 | #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 | |
331 | #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b | |
332 | #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 | |
333 | #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF | |
334 | #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 | |
335 | #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 | |
336 | #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 | |
337 | ||
338 | /* TX lane Polarity swap */ | |
339 | #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 | |
340 | #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 | |
341 | #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 | |
342 | #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 | |
343 | /* TX lane Polarity swap */ | |
344 | #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 | |
345 | #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 | |
346 | #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 | |
347 | #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 | |
348 | ||
349 | /* Selects the port layout of the board */ | |
350 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 | |
351 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 | |
352 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 | |
353 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 | |
354 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 | |
355 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 | |
356 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 | |
357 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 | |
a2fbb9ea ET |
358 | }; |
359 | ||
f1410647 | 360 | |
a2fbb9ea | 361 | /**************************************************************************** |
619c5cb6 | 362 | * Port HW configuration * |
a2fbb9ea | 363 | ****************************************************************************/ |
619c5cb6 | 364 | struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ |
a2fbb9ea | 365 | |
a2fbb9ea | 366 | u32 pci_id; |
619c5cb6 VZ |
367 | #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 |
368 | #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff | |
a2fbb9ea ET |
369 | |
370 | u32 pci_sub_id; | |
619c5cb6 VZ |
371 | #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 |
372 | #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff | |
a2fbb9ea ET |
373 | |
374 | u32 power_dissipated; | |
619c5cb6 VZ |
375 | #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff |
376 | #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 | |
377 | #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 | |
378 | #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 | |
379 | #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 | |
380 | #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 | |
381 | #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 | |
382 | #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 | |
a2fbb9ea ET |
383 | |
384 | u32 power_consumed; | |
619c5cb6 VZ |
385 | #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff |
386 | #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 | |
387 | #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 | |
388 | #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 | |
389 | #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 | |
390 | #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 | |
391 | #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 | |
392 | #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 | |
a2fbb9ea ET |
393 | |
394 | u32 mac_upper; | |
619c5cb6 VZ |
395 | #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff |
396 | #define PORT_HW_CFG_UPPERMAC_SHIFT 0 | |
a2fbb9ea ET |
397 | u32 mac_lower; |
398 | ||
399 | u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ | |
400 | u32 iscsi_mac_lower; | |
401 | ||
402 | u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ | |
403 | u32 rdma_mac_lower; | |
404 | ||
405 | u32 serdes_config; | |
619c5cb6 VZ |
406 | #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff |
407 | #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 | |
408 | ||
409 | #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 | |
410 | #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 | |
411 | ||
412 | ||
413 | /* Default values: 2P-64, 4P-32 */ | |
414 | u32 pf_config; /* 0x158 */ | |
415 | #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F | |
416 | #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 | |
417 | ||
418 | /* Default values: 17 */ | |
419 | #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 | |
420 | #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 | |
421 | ||
422 | #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 | |
423 | #define PORT_HW_CFG_FLR_ENABLED 0x00010000 | |
424 | ||
425 | u32 vf_config; /* 0x15C */ | |
426 | #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F | |
427 | #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 | |
428 | ||
429 | #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 | |
430 | #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 | |
431 | ||
432 | u32 mf_pci_id; /* 0x160 */ | |
433 | #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF | |
434 | #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 | |
435 | ||
436 | /* Controls the TX laser of the SFP+ module */ | |
437 | u32 sfp_ctrl; /* 0x164 */ | |
438 | #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF | |
439 | #define PORT_HW_CFG_TX_LASER_SHIFT 0 | |
440 | #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 | |
441 | #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 | |
442 | #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 | |
443 | #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 | |
444 | #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 | |
445 | ||
446 | /* Controls the fault module LED of the SFP+ */ | |
447 | #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 | |
448 | #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 | |
449 | #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 | |
450 | #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 | |
451 | #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 | |
452 | #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 | |
453 | #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 | |
454 | ||
455 | /* The output pin TX_DIS that controls the TX laser of the SFP+ | |
456 | module. Use the PIN_CFG_XXX defines on top */ | |
457 | u32 e3_sfp_ctrl; /* 0x168 */ | |
458 | #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF | |
459 | #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 | |
460 | ||
461 | /* The output pin for SFPP_TYPE which turns on the Fault module LED */ | |
462 | #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 | |
463 | #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 | |
464 | ||
465 | /* The input pin MOD_ABS that indicates whether SFP+ module is | |
466 | present or not. Use the PIN_CFG_XXX defines on top */ | |
467 | #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 | |
468 | #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 | |
469 | ||
470 | /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ | |
471 | module. Use the PIN_CFG_XXX defines on top */ | |
472 | #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 | |
473 | #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 | |
474 | ||
475 | /* | |
476 | * The input pin which signals module transmit fault. Use the | |
477 | * PIN_CFG_XXX defines on top | |
478 | */ | |
479 | u32 e3_cmn_pin_cfg; /* 0x16C */ | |
480 | #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF | |
481 | #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 | |
482 | ||
483 | /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on | |
484 | top */ | |
485 | #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 | |
486 | #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 | |
487 | ||
488 | /* | |
489 | * The output pin which powers down the PHY. Use the PIN_CFG_XXX | |
490 | * defines on top | |
491 | */ | |
492 | #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 | |
493 | #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 | |
494 | ||
495 | /* The output pin values BSC_SEL which selects the I2C for this port | |
496 | in the I2C Mux */ | |
497 | #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 | |
498 | #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 | |
499 | ||
a8db5b4c YR |
500 | |
501 | /* | |
619c5cb6 VZ |
502 | * The input pin I_FAULT which indicate over-current has occurred. |
503 | * Use the PIN_CFG_XXX defines on top | |
a8db5b4c | 504 | */ |
619c5cb6 VZ |
505 | u32 e3_cmn_pin_cfg1; /* 0x170 */ |
506 | #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF | |
507 | #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 | |
7964211d YM |
508 | |
509 | /* pause on host ring */ | |
510 | u32 generic_features; /* 0x174 */ | |
511 | #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 | |
512 | #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 | |
513 | #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 | |
514 | #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 | |
515 | ||
e438c5d6 YR |
516 | /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 |
517 | * LOM recommended and tested value is 0xBEB2. Using a different | |
518 | * value means using a value not tested by BRCM | |
519 | */ | |
520 | u32 sfi_tap_values; /* 0x178 */ | |
521 | #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF | |
522 | #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 | |
523 | ||
524 | /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested | |
525 | * value is 0x2. LOM recommended and tested value is 0x2. Using a | |
526 | * different value means using a value not tested by BRCM | |
527 | */ | |
528 | #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 | |
529 | #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 | |
530 | ||
531 | u32 reserved0[5]; /* 0x17c */ | |
619c5cb6 VZ |
532 | |
533 | u32 aeu_int_mask; /* 0x190 */ | |
534 | ||
535 | u32 media_type; /* 0x194 */ | |
536 | #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF | |
537 | #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 | |
538 | ||
539 | #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 | |
540 | #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 | |
541 | ||
542 | #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 | |
543 | #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 | |
544 | ||
545 | /* 4 times 16 bits for all 4 lanes. In case external PHY is present | |
546 | (not direct mode), those values will not take effect on the 4 XGXS | |
547 | lanes. For some external PHYs (such as 8706 and 8726) the values | |
548 | will be used to configure the external PHY in those cases, not | |
549 | all 4 values are needed. */ | |
550 | u16 xgxs_config_rx[4]; /* 0x198 */ | |
551 | u16 xgxs_config_tx[4]; /* 0x1A0 */ | |
552 | ||
553 | /* For storing FCOE mac on shared memory */ | |
554 | u32 fcoe_fip_mac_upper; | |
555 | #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff | |
556 | #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 | |
557 | u32 fcoe_fip_mac_lower; | |
558 | ||
559 | u32 fcoe_wwn_port_name_upper; | |
560 | u32 fcoe_wwn_port_name_lower; | |
561 | ||
562 | u32 fcoe_wwn_node_name_upper; | |
563 | u32 fcoe_wwn_node_name_lower; | |
564 | ||
0520e63a YR |
565 | u32 Reserved1[49]; /* 0x1C0 */ |
566 | ||
567 | /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), | |
568 | 84833 only */ | |
569 | u32 xgbt_phy_cfg; /* 0x284 */ | |
570 | #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF | |
571 | #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 | |
619c5cb6 VZ |
572 | |
573 | u32 default_cfg; /* 0x288 */ | |
574 | #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 | |
575 | #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 | |
576 | #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 | |
577 | #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 | |
578 | #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 | |
579 | #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 | |
580 | ||
581 | #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C | |
582 | #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 | |
583 | #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 | |
584 | #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 | |
585 | #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 | |
586 | #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c | |
587 | ||
588 | #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 | |
589 | #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 | |
590 | #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 | |
591 | #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 | |
592 | #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 | |
593 | #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 | |
594 | ||
595 | #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 | |
596 | #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 | |
597 | #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 | |
598 | #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 | |
599 | #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 | |
600 | #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 | |
601 | ||
602 | /* When KR link is required to be set to force which is not | |
603 | KR-compliant, this parameter determine what is the trigger for it. | |
604 | When GPIO is selected, low input will force the speed. Currently | |
605 | default speed is 1G. In the future, it may be widen to select the | |
606 | forced speed in with another parameter. Note when force-1G is | |
607 | enabled, it override option 56: Link Speed option. */ | |
608 | #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 | |
609 | #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 | |
610 | #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 | |
611 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 | |
612 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 | |
613 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 | |
614 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 | |
615 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 | |
616 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 | |
617 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 | |
618 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 | |
619 | #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 | |
620 | /* Enable to determine with which GPIO to reset the external phy */ | |
621 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 | |
622 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 | |
623 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 | |
624 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 | |
625 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 | |
626 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 | |
627 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 | |
628 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 | |
629 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 | |
630 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 | |
631 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 | |
632 | ||
121839be | 633 | /* Enable BAM on KR */ |
619c5cb6 VZ |
634 | #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 |
635 | #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 | |
636 | #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 | |
637 | #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 | |
121839be | 638 | |
1bef68e3 | 639 | /* Enable Common Mode Sense */ |
619c5cb6 VZ |
640 | #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 |
641 | #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 | |
642 | #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 | |
643 | #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 | |
644 | ||
619c5cb6 VZ |
645 | /* Determine the Serdes electrical interface */ |
646 | #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 | |
647 | #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 | |
648 | #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 | |
649 | #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 | |
650 | #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 | |
651 | #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 | |
652 | #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 | |
653 | #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 | |
654 | ||
1bef68e3 | 655 | |
a22f0788 | 656 | u32 speed_capability_mask2; /* 0x28C */ |
619c5cb6 VZ |
657 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF |
658 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 | |
659 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 | |
660 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 | |
661 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 | |
662 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 | |
663 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 | |
664 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 | |
665 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 | |
666 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 | |
667 | ||
668 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 | |
669 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 | |
670 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 | |
671 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 | |
672 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 | |
673 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 | |
674 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 | |
675 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 | |
676 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 | |
677 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 | |
678 | ||
679 | ||
680 | /* In the case where two media types (e.g. copper and fiber) are | |
681 | present and electrically active at the same time, PHY Selection | |
682 | will determine which of the two PHYs will be designated as the | |
683 | Active PHY and used for a connection to the network. */ | |
684 | u32 multi_phy_config; /* 0x290 */ | |
685 | #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 | |
686 | #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 | |
687 | #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 | |
688 | #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 | |
689 | #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 | |
690 | #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 | |
691 | #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 | |
692 | ||
693 | /* When enabled, all second phy nvram parameters will be swapped | |
694 | with the first phy parameters */ | |
695 | #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 | |
696 | #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 | |
697 | #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 | |
698 | #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 | |
699 | ||
700 | ||
701 | /* Address of the second external phy */ | |
702 | u32 external_phy_config2; /* 0x294 */ | |
703 | #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF | |
704 | #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 | |
705 | ||
706 | /* The second XGXS external PHY type */ | |
707 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 | |
708 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 | |
709 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 | |
710 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 | |
711 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 | |
712 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 | |
713 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 | |
714 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 | |
715 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 | |
716 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 | |
717 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 | |
718 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 | |
719 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 | |
720 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 | |
721 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 | |
722 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 | |
52c4d6c4 | 723 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 |
619c5cb6 | 724 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 |
3756a89f | 725 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 |
0f6bb03d | 726 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 |
619c5cb6 VZ |
727 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 |
728 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 | |
729 | ||
730 | ||
731 | /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as | |
732 | 8706, 8726 and 8727) not all 4 values are needed. */ | |
733 | u16 xgxs_config2_rx[4]; /* 0x296 */ | |
734 | u16 xgxs_config2_tx[4]; /* 0x2A0 */ | |
a2fbb9ea ET |
735 | |
736 | u32 lane_config; | |
619c5cb6 VZ |
737 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff |
738 | #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 | |
739 | /* AN and forced */ | |
740 | #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b | |
741 | /* forced only */ | |
742 | #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 | |
743 | /* forced only */ | |
744 | #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 | |
745 | /* forced only */ | |
746 | #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 | |
747 | #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff | |
748 | #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 | |
749 | #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 | |
750 | #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 | |
751 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 | |
752 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 | |
753 | ||
754 | /* Indicate whether to swap the external phy polarity */ | |
755 | #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 | |
756 | #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 | |
757 | #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 | |
758 | ||
a2fbb9ea ET |
759 | |
760 | u32 external_phy_config; | |
619c5cb6 VZ |
761 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff |
762 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 | |
763 | ||
764 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 | |
765 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 | |
766 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 | |
767 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 | |
768 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 | |
769 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 | |
770 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 | |
771 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 | |
772 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 | |
773 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 | |
774 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 | |
775 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 | |
776 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 | |
777 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 | |
778 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 | |
779 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 | |
52c4d6c4 | 780 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 |
619c5cb6 | 781 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 |
3756a89f | 782 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 |
0f6bb03d | 783 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 |
619c5cb6 VZ |
784 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 |
785 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 | |
786 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 | |
787 | ||
788 | #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 | |
789 | #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 | |
790 | ||
791 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 | |
792 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 | |
793 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 | |
794 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 | |
795 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 | |
796 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 | |
a2fbb9ea ET |
797 | |
798 | u32 speed_capability_mask; | |
619c5cb6 VZ |
799 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff |
800 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 | |
801 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 | |
802 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 | |
803 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 | |
804 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 | |
805 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 | |
806 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 | |
807 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 | |
808 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 | |
809 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 | |
810 | ||
811 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 | |
812 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 | |
813 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 | |
814 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 | |
815 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 | |
816 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 | |
817 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 | |
818 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 | |
819 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 | |
820 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 | |
821 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 | |
822 | ||
823 | /* A place to hold the original MAC address as a backup */ | |
824 | u32 backup_mac_upper; /* 0x2B4 */ | |
825 | u32 backup_mac_lower; /* 0x2B8 */ | |
a2fbb9ea ET |
826 | |
827 | }; | |
828 | ||
f1410647 | 829 | |
a2fbb9ea | 830 | /**************************************************************************** |
619c5cb6 | 831 | * Shared Feature configuration * |
a2fbb9ea | 832 | ****************************************************************************/ |
619c5cb6 VZ |
833 | struct shared_feat_cfg { /* NVRAM Offset */ |
834 | ||
835 | u32 config; /* 0x450 */ | |
836 | #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 | |
837 | ||
838 | /* Use NVRAM values instead of HW default values */ | |
839 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ | |
840 | 0x00000002 | |
841 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ | |
842 | 0x00000000 | |
843 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ | |
844 | 0x00000002 | |
845 | ||
846 | #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 | |
847 | #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 | |
848 | #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 | |
f1410647 | 849 | |
619c5cb6 VZ |
850 | #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 |
851 | #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 | |
589abe3a | 852 | |
619c5cb6 VZ |
853 | /* Override the OTP back to single function mode. When using GPIO, |
854 | high means only SF, 0 is according to CLP configuration */ | |
855 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 | |
856 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 | |
857 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 | |
858 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 | |
859 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 | |
860 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 | |
a3348722 | 861 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 |
589abe3a | 862 | |
619c5cb6 VZ |
863 | /* The interval in seconds between sending LLDP packets. Set to zero |
864 | to disable the feature */ | |
865 | #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 | |
866 | #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 | |
867 | ||
868 | /* The assigned device type ID for LLDP usage */ | |
869 | #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 | |
870 | #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 | |
a2fbb9ea ET |
871 | |
872 | }; | |
873 | ||
874 | ||
875 | /**************************************************************************** | |
619c5cb6 | 876 | * Port Feature configuration * |
a2fbb9ea | 877 | ****************************************************************************/ |
619c5cb6 | 878 | struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ |
f1410647 | 879 | |
a2fbb9ea | 880 | u32 config; |
619c5cb6 VZ |
881 | #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f |
882 | #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 | |
883 | #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 | |
884 | #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 | |
885 | #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 | |
886 | #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 | |
887 | #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 | |
888 | #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 | |
889 | #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 | |
890 | #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 | |
891 | #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 | |
892 | #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 | |
893 | #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a | |
894 | #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b | |
895 | #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c | |
896 | #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d | |
897 | #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e | |
898 | #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f | |
899 | #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 | |
900 | #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 | |
901 | #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 | |
902 | #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 | |
903 | #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 | |
904 | #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 | |
905 | #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 | |
906 | #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 | |
907 | #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 | |
908 | #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 | |
909 | #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 | |
910 | #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 | |
911 | #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 | |
912 | #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 | |
913 | #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 | |
914 | #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 | |
915 | #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 | |
916 | #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 | |
917 | ||
918 | #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 | |
919 | #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 | |
920 | #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 | |
921 | ||
4ba7699b YM |
922 | #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 |
923 | #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 | |
924 | #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 | |
925 | ||
619c5cb6 VZ |
926 | #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 |
927 | #define PORT_FEATURE_EN_SIZE_SHIFT 24 | |
928 | #define PORT_FEATURE_WOL_ENABLED 0x01000000 | |
929 | #define PORT_FEATURE_MBA_ENABLED 0x02000000 | |
930 | #define PORT_FEATURE_MFW_ENABLED 0x04000000 | |
931 | ||
932 | /* Advertise expansion ROM even if MBA is disabled */ | |
933 | #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 | |
934 | #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 | |
935 | #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 | |
936 | ||
937 | /* Check the optic vendor via i2c against a list of approved modules | |
938 | in a separate nvram image */ | |
939 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 | |
940 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 | |
941 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ | |
942 | 0x00000000 | |
943 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ | |
944 | 0x20000000 | |
945 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 | |
946 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 | |
589abe3a | 947 | |
a2fbb9ea ET |
948 | u32 wol_config; |
949 | /* Default is used when driver sets to "auto" mode */ | |
619c5cb6 VZ |
950 | #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 |
951 | #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 | |
952 | #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 | |
953 | #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 | |
954 | #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 | |
955 | #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 | |
956 | #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 | |
957 | #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 | |
958 | #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 | |
a2fbb9ea ET |
959 | |
960 | u32 mba_config; | |
619c5cb6 VZ |
961 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 |
962 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 | |
963 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 | |
964 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 | |
965 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 | |
966 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 | |
967 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 | |
968 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 | |
969 | ||
970 | #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 | |
971 | #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 | |
972 | ||
973 | #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 | |
974 | #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 | |
975 | #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 | |
976 | #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 | |
977 | #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 | |
978 | #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 | |
979 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 | |
980 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 | |
981 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 | |
982 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 | |
983 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 | |
984 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 | |
985 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 | |
986 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 | |
987 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 | |
988 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 | |
989 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 | |
990 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 | |
991 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 | |
992 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 | |
993 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 | |
994 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 | |
995 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 | |
996 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 | |
997 | #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 | |
998 | #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 | |
999 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 | |
1000 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 | |
1001 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 | |
1002 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 | |
1003 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 | |
1004 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 | |
1005 | #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 | |
1006 | #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 | |
1007 | #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 | |
1008 | #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 | |
1009 | #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 | |
1010 | #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 | |
1011 | #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 | |
1012 | #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 | |
1013 | #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 | |
1014 | #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 | |
1015 | #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 | |
a2fbb9ea | 1016 | u32 bmc_config; |
619c5cb6 VZ |
1017 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 |
1018 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 | |
1019 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 | |
a2fbb9ea ET |
1020 | |
1021 | u32 mba_vlan_cfg; | |
619c5cb6 VZ |
1022 | #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff |
1023 | #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 | |
1024 | #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 | |
a2fbb9ea ET |
1025 | |
1026 | u32 resource_cfg; | |
619c5cb6 VZ |
1027 | #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 |
1028 | #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 | |
1029 | #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 | |
1030 | #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 | |
1031 | #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 | |
a2fbb9ea ET |
1032 | |
1033 | u32 smbus_config; | |
619c5cb6 VZ |
1034 | #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe |
1035 | #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 | |
1036 | ||
1037 | u32 vf_config; | |
1038 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f | |
1039 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 | |
1040 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 | |
1041 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 | |
1042 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 | |
1043 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 | |
1044 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 | |
1045 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 | |
1046 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 | |
1047 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 | |
1048 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 | |
1049 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 | |
1050 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a | |
1051 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b | |
1052 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c | |
1053 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d | |
1054 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e | |
1055 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f | |
a2fbb9ea ET |
1056 | |
1057 | u32 link_config; /* Used as HW defaults for the driver */ | |
619c5cb6 VZ |
1058 | #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 |
1059 | #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 | |
1060 | /* (forced) low speed switch (< 10G) */ | |
1061 | #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 | |
1062 | /* (forced) high speed switch (>= 10G) */ | |
1063 | #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 | |
1064 | #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 | |
1065 | #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 | |
1066 | ||
1067 | #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 | |
1068 | #define PORT_FEATURE_LINK_SPEED_SHIFT 16 | |
1069 | #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 | |
1070 | #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 | |
1071 | #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 | |
1072 | #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 | |
1073 | #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 | |
1074 | #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 | |
1075 | #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 | |
1076 | #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 | |
1077 | #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 | |
1078 | ||
1079 | #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 | |
1080 | #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 | |
1081 | #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 | |
1082 | #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 | |
1083 | #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 | |
1084 | #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 | |
1085 | #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 | |
a2fbb9ea ET |
1086 | |
1087 | /* The default for MCP link configuration, | |
619c5cb6 | 1088 | uses the same defines as link_config */ |
a2fbb9ea | 1089 | u32 mfw_wol_link_cfg; |
619c5cb6 | 1090 | |
a22f0788 | 1091 | /* The default for the driver of the second external phy, |
619c5cb6 VZ |
1092 | uses the same defines as link_config */ |
1093 | u32 link_config2; /* 0x47C */ | |
a2fbb9ea | 1094 | |
a22f0788 | 1095 | /* The default for MCP of the second external phy, |
619c5cb6 VZ |
1096 | uses the same defines as link_config */ |
1097 | u32 mfw_wol_link_cfg2; /* 0x480 */ | |
a22f0788 | 1098 | |
a2fbb9ea | 1099 | |
c8c60d88 YM |
1100 | /* EEE power saving mode */ |
1101 | u32 eee_power_mode; /* 0x484 */ | |
1102 | #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF | |
1103 | #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 | |
1104 | #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 | |
1105 | #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 | |
1106 | #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 | |
1107 | #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 | |
1108 | ||
1109 | ||
1110 | u32 Reserved2[16]; /* 0x488 */ | |
a2fbb9ea ET |
1111 | }; |
1112 | ||
1113 | ||
34f80b04 | 1114 | /**************************************************************************** |
619c5cb6 | 1115 | * Device Information * |
34f80b04 | 1116 | ****************************************************************************/ |
619c5cb6 | 1117 | struct shm_dev_info { /* size */ |
f1410647 | 1118 | |
34f80b04 | 1119 | u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ |
f1410647 | 1120 | |
619c5cb6 | 1121 | struct shared_hw_cfg shared_hw_config; /* 40 */ |
f1410647 | 1122 | |
619c5cb6 | 1123 | struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ |
f1410647 | 1124 | |
619c5cb6 | 1125 | struct shared_feat_cfg shared_feature_config; /* 4 */ |
f1410647 | 1126 | |
619c5cb6 | 1127 | struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ |
f1410647 ET |
1128 | |
1129 | }; | |
1130 | ||
1131 | ||
619c5cb6 VZ |
1132 | #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) |
1133 | #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." | |
1134 | #endif | |
f1410647 | 1135 | |
619c5cb6 VZ |
1136 | #define FUNC_0 0 |
1137 | #define FUNC_1 1 | |
1138 | #define FUNC_2 2 | |
1139 | #define FUNC_3 3 | |
1140 | #define FUNC_4 4 | |
1141 | #define FUNC_5 5 | |
1142 | #define FUNC_6 6 | |
1143 | #define FUNC_7 7 | |
1144 | #define E1_FUNC_MAX 2 | |
1145 | #define E1H_FUNC_MAX 8 | |
1146 | #define E2_FUNC_MAX 4 /* per path */ | |
1147 | ||
1148 | #define VN_0 0 | |
1149 | #define VN_1 1 | |
1150 | #define VN_2 2 | |
1151 | #define VN_3 3 | |
1152 | #define E1VN_MAX 1 | |
1153 | #define E1HVN_MAX 4 | |
1154 | ||
1155 | #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ | |
f1410647 ET |
1156 | /* This value (in milliseconds) determines the frequency of the driver |
1157 | * issuing the PULSE message code. The firmware monitors this periodic | |
1158 | * pulse to determine when to switch to an OS-absent mode. */ | |
619c5cb6 | 1159 | #define DRV_PULSE_PERIOD_MS 250 |
f1410647 ET |
1160 | |
1161 | /* This value (in milliseconds) determines how long the driver should | |
1162 | * wait for an acknowledgement from the firmware before timing out. Once | |
1163 | * the firmware has timed out, the driver will assume there is no firmware | |
1164 | * running and there won't be any firmware-driver synchronization during a | |
1165 | * driver reset. */ | |
619c5cb6 | 1166 | #define FW_ACK_TIME_OUT_MS 5000 |
f1410647 | 1167 | |
619c5cb6 | 1168 | #define FW_ACK_POLL_TIME_MS 1 |
f1410647 | 1169 | |
619c5cb6 | 1170 | #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) |
f1410647 | 1171 | |
de128804 DK |
1172 | #define MFW_TRACE_SIGNATURE 0x54524342 |
1173 | ||
a2fbb9ea | 1174 | /**************************************************************************** |
619c5cb6 | 1175 | * Driver <-> FW Mailbox * |
a2fbb9ea | 1176 | ****************************************************************************/ |
f1410647 | 1177 | struct drv_port_mb { |
a2fbb9ea | 1178 | |
f1410647 ET |
1179 | u32 link_status; |
1180 | /* Driver should update this field on any link change event */ | |
a2fbb9ea | 1181 | |
d0b8a6f9 | 1182 | #define LINK_STATUS_NONE (0<<0) |
619c5cb6 VZ |
1183 | #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 |
1184 | #define LINK_STATUS_LINK_UP 0x00000001 | |
1185 | #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E | |
1186 | #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) | |
1187 | #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) | |
1188 | #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) | |
1189 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) | |
1190 | #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) | |
1191 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) | |
1192 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) | |
1193 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) | |
1194 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) | |
1195 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) | |
1196 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) | |
1197 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) | |
1198 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) | |
1199 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) | |
1200 | #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) | |
1201 | #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) | |
1202 | ||
1203 | #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 | |
1204 | #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 | |
1205 | ||
1206 | #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 | |
1207 | #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 | |
1208 | #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 | |
1209 | ||
1210 | #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 | |
1211 | #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 | |
1212 | #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 | |
1213 | #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 | |
1214 | #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 | |
1215 | #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 | |
1216 | #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 | |
1217 | ||
1218 | #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 | |
1219 | #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 | |
1220 | ||
1221 | #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 | |
1222 | #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 | |
1223 | ||
1224 | #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 | |
1225 | #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) | |
1226 | #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) | |
1227 | #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) | |
1228 | #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) | |
1229 | ||
1230 | #define LINK_STATUS_SERDES_LINK 0x00100000 | |
1231 | ||
1232 | #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 | |
1233 | #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 | |
1234 | #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 | |
1235 | #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 | |
f1410647 | 1236 | |
b8d6d082 YR |
1237 | #define LINK_STATUS_PFC_ENABLED 0x20000000 |
1238 | ||
de6f3377 | 1239 | #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 |
d0b8a6f9 | 1240 | #define LINK_STATUS_SFP_TX_FAULT 0x80000000 |
de6f3377 | 1241 | |
34f80b04 EG |
1242 | u32 port_stx; |
1243 | ||
de832a55 EG |
1244 | u32 stat_nig_timer; |
1245 | ||
a35da8db EG |
1246 | /* MCP firmware does not use this field */ |
1247 | u32 ext_phy_fw_version; | |
f1410647 ET |
1248 | |
1249 | }; | |
1250 | ||
1251 | ||
1252 | struct drv_func_mb { | |
1253 | ||
1254 | u32 drv_mb_header; | |
619c5cb6 VZ |
1255 | #define DRV_MSG_CODE_MASK 0xffff0000 |
1256 | #define DRV_MSG_CODE_LOAD_REQ 0x10000000 | |
1257 | #define DRV_MSG_CODE_LOAD_DONE 0x11000000 | |
1258 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 | |
1259 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 | |
1260 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 | |
1261 | #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 | |
1262 | #define DRV_MSG_CODE_DCC_OK 0x30000000 | |
1263 | #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 | |
1264 | #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 | |
1265 | #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 | |
1266 | #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 | |
1267 | #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 | |
1268 | #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 | |
1269 | #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 | |
1270 | #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 | |
4d295db0 | 1271 | /* |
619c5cb6 VZ |
1272 | * The optic module verification command requires bootcode |
1273 | * v5.0.6 or later, te specific optic module verification command | |
1274 | * requires bootcode v5.2.12 or later | |
4d295db0 | 1275 | */ |
619c5cb6 VZ |
1276 | #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 |
1277 | #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 | |
1278 | #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 | |
1279 | #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 | |
a3348722 BW |
1280 | #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 |
1281 | #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 | |
85242eea | 1282 | #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 |
55386fe8 | 1283 | #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 |
0e898dd7 | 1284 | #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 |
2e499d3c | 1285 | #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 |
619c5cb6 VZ |
1286 | |
1287 | #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 | |
1288 | #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 | |
9876879f | 1289 | #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 |
619c5cb6 VZ |
1290 | |
1291 | #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 | |
a3348722 BW |
1292 | |
1293 | #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 | |
1294 | #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 | |
1295 | #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 | |
1296 | #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 | |
1297 | #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 | |
1298 | ||
1d187b34 BW |
1299 | #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 |
1300 | #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 | |
f1410647 | 1301 | |
c8c60d88 YM |
1302 | #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 |
1303 | ||
a6d3a5ba BW |
1304 | #define DRV_MSG_CODE_RMMOD 0xdb000000 |
1305 | #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f | |
1306 | ||
619c5cb6 VZ |
1307 | #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 |
1308 | #define REQ_BC_VER_4_SET_MF_BW 0x00060202 | |
1309 | #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 | |
34f80b04 | 1310 | |
619c5cb6 VZ |
1311 | #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 |
1312 | ||
452427b0 YM |
1313 | #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 |
1314 | #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 | |
1315 | ||
619c5cb6 VZ |
1316 | #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 |
1317 | #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 | |
1318 | #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 | |
1319 | #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 | |
1320 | ||
1321 | #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff | |
f1410647 ET |
1322 | |
1323 | u32 drv_mb_param; | |
619c5cb6 VZ |
1324 | #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 |
1325 | #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 | |
f1410647 | 1326 | |
5d07d868 YM |
1327 | #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 |
1328 | ||
1329 | #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a | |
178135c1 DK |
1330 | #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 |
1331 | ||
f1410647 | 1332 | u32 fw_mb_header; |
619c5cb6 VZ |
1333 | #define FW_MSG_CODE_MASK 0xffff0000 |
1334 | #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 | |
1335 | #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 | |
1336 | #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 | |
1337 | /* Load common chip is supported from bc 6.0.0 */ | |
1338 | #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 | |
1339 | #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 | |
1340 | ||
1341 | #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 | |
1342 | #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 | |
1343 | #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 | |
1344 | #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 | |
1345 | #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 | |
1346 | #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 | |
1347 | #define FW_MSG_CODE_DCC_DONE 0x30100000 | |
1348 | #define FW_MSG_CODE_LLDP_DONE 0x40100000 | |
1349 | #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 | |
1350 | #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 | |
1351 | #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 | |
1352 | #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 | |
1353 | #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 | |
1354 | #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 | |
1355 | #define FW_MSG_CODE_NO_KEY 0x80f00000 | |
1356 | #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 | |
1357 | #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 | |
1358 | #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 | |
1359 | #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 | |
1360 | #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 | |
1361 | #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 | |
1362 | #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 | |
1363 | #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 | |
1364 | #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 | |
1365 | #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 | |
a3348722 BW |
1366 | #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 |
1367 | ||
1368 | #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 | |
1369 | #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 | |
1370 | #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 | |
1371 | #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 | |
1372 | #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 | |
1373 | ||
1d187b34 BW |
1374 | #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 |
1375 | #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 | |
619c5cb6 | 1376 | |
c8c60d88 YM |
1377 | #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 |
1378 | ||
a6d3a5ba BW |
1379 | #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 |
1380 | ||
619c5cb6 VZ |
1381 | #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 |
1382 | #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 | |
1383 | ||
1384 | #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 | |
1385 | ||
1386 | #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 | |
1387 | #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 | |
1388 | #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 | |
1389 | #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 | |
1390 | ||
1391 | #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff | |
f1410647 ET |
1392 | |
1393 | u32 fw_mb_param; | |
1394 | ||
1395 | u32 drv_pulse_mb; | |
619c5cb6 VZ |
1396 | #define DRV_PULSE_SEQ_MASK 0x00007fff |
1397 | #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 | |
1398 | /* | |
1399 | * The system time is in the format of | |
1400 | * (year-2001)*12*32 + month*32 + day. | |
1401 | */ | |
1402 | #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 | |
1403 | /* | |
1404 | * Indicate to the firmware not to go into the | |
f1410647 | 1405 | * OS-absent when it is not getting driver pulse. |
619c5cb6 VZ |
1406 | * This is used for debugging as well for PXE(MBA). |
1407 | */ | |
f1410647 ET |
1408 | |
1409 | u32 mcp_pulse_mb; | |
619c5cb6 VZ |
1410 | #define MCP_PULSE_SEQ_MASK 0x00007fff |
1411 | #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 | |
f1410647 ET |
1412 | /* Indicates to the driver not to assert due to lack |
1413 | * of MCP response */ | |
619c5cb6 VZ |
1414 | #define MCP_EVENT_MASK 0xffff0000 |
1415 | #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 | |
f1410647 ET |
1416 | |
1417 | u32 iscsi_boot_signature; | |
1418 | u32 iscsi_boot_block_offset; | |
1419 | ||
34f80b04 | 1420 | u32 drv_status; |
619c5cb6 VZ |
1421 | #define DRV_STATUS_PMF 0x00000001 |
1422 | #define DRV_STATUS_VF_DISABLED 0x00000002 | |
1423 | #define DRV_STATUS_SET_MF_BW 0x00000004 | |
1424 | #define DRV_STATUS_LINK_EVENT 0x00000008 | |
1425 | ||
1426 | #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 | |
1427 | #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 | |
1428 | #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 | |
1429 | #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 | |
1430 | #define DRV_STATUS_DCC_RESERVED1 0x00000800 | |
1431 | #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 | |
1432 | #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 | |
1433 | ||
1434 | #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 | |
1435 | #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 | |
a3348722 BW |
1436 | #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 |
1437 | #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 | |
1438 | #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 | |
1439 | #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 | |
1440 | #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 | |
1441 | ||
1d187b34 | 1442 | #define DRV_STATUS_DRV_INFO_REQ 0x04000000 |
2691d51d | 1443 | |
c8c60d88 YM |
1444 | #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 |
1445 | ||
34f80b04 | 1446 | u32 virt_mac_upper; |
619c5cb6 VZ |
1447 | #define VIRT_MAC_SIGN_MASK 0xffff0000 |
1448 | #define VIRT_MAC_SIGNATURE 0x564d0000 | |
34f80b04 | 1449 | u32 virt_mac_lower; |
a2fbb9ea ET |
1450 | |
1451 | }; | |
1452 | ||
1453 | ||
1454 | /**************************************************************************** | |
619c5cb6 | 1455 | * Management firmware state * |
a2fbb9ea | 1456 | ****************************************************************************/ |
f1410647 | 1457 | /* Allocate 440 bytes for management firmware */ |
619c5cb6 | 1458 | #define MGMTFW_STATE_WORD_SIZE 110 |
a2fbb9ea ET |
1459 | |
1460 | struct mgmtfw_state { | |
1461 | u32 opaque[MGMTFW_STATE_WORD_SIZE]; | |
1462 | }; | |
1463 | ||
1464 | ||
34f80b04 | 1465 | /**************************************************************************** |
619c5cb6 | 1466 | * Multi-Function configuration * |
34f80b04 EG |
1467 | ****************************************************************************/ |
1468 | struct shared_mf_cfg { | |
1469 | ||
1470 | u32 clp_mb; | |
619c5cb6 | 1471 | #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 |
34f80b04 | 1472 | /* set by CLP */ |
619c5cb6 | 1473 | #define SHARED_MF_CLP_EXIT 0x00000001 |
34f80b04 | 1474 | /* set by MCP */ |
619c5cb6 | 1475 | #define SHARED_MF_CLP_EXIT_DONE 0x00010000 |
34f80b04 EG |
1476 | |
1477 | }; | |
1478 | ||
1479 | struct port_mf_cfg { | |
1480 | ||
619c5cb6 VZ |
1481 | u32 dynamic_cfg; /* device control channel */ |
1482 | #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff | |
1483 | #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 | |
1484 | #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK | |
34f80b04 | 1485 | |
621b4d66 | 1486 | u32 reserved[1]; |
34f80b04 EG |
1487 | |
1488 | }; | |
1489 | ||
1490 | struct func_mf_cfg { | |
1491 | ||
1492 | u32 config; | |
1493 | /* E/R/I/D */ | |
1494 | /* function 0 of each port cannot be hidden */ | |
619c5cb6 | 1495 | #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 |
34f80b04 | 1496 | |
619c5cb6 VZ |
1497 | #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 |
1498 | #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 | |
1499 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 | |
1500 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 | |
1501 | #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 | |
1502 | #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ | |
1503 | FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA | |
34f80b04 | 1504 | |
619c5cb6 VZ |
1505 | #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 |
1506 | #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 | |
34f80b04 EG |
1507 | |
1508 | /* PRI */ | |
1509 | /* 0 - low priority, 3 - high priority */ | |
619c5cb6 VZ |
1510 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 |
1511 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 | |
1512 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 | |
34f80b04 EG |
1513 | |
1514 | /* MINBW, MAXBW */ | |
1515 | /* value range - 0..100, increments in 100Mbps */ | |
619c5cb6 VZ |
1516 | #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 |
1517 | #define FUNC_MF_CFG_MIN_BW_SHIFT 16 | |
1518 | #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 | |
1519 | #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 | |
1520 | #define FUNC_MF_CFG_MAX_BW_SHIFT 24 | |
1521 | #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 | |
1522 | ||
1523 | u32 mac_upper; /* MAC */ | |
1524 | #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff | |
1525 | #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 | |
1526 | #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK | |
34f80b04 | 1527 | u32 mac_lower; |
619c5cb6 | 1528 | #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff |
34f80b04 EG |
1529 | |
1530 | u32 e1hov_tag; /* VNI */ | |
619c5cb6 VZ |
1531 | #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff |
1532 | #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 | |
1533 | #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK | |
34f80b04 | 1534 | |
a3348722 BW |
1535 | /* afex default VLAN ID - 12 bits */ |
1536 | #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 | |
1537 | #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 | |
1538 | ||
1539 | u32 afex_config; | |
1540 | #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff | |
1541 | #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 | |
1542 | #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 | |
1543 | #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 | |
1544 | #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 | |
1545 | #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 | |
1546 | #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 | |
1547 | ||
1548 | u32 reserved; | |
1549 | }; | |
1550 | ||
1551 | enum mf_cfg_afex_vlan_mode { | |
1552 | FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, | |
1553 | FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, | |
1554 | FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE | |
34f80b04 EG |
1555 | }; |
1556 | ||
0793f83f DK |
1557 | /* This structure is not applicable and should not be accessed on 57711 */ |
1558 | struct func_ext_cfg { | |
1559 | u32 func_cfg; | |
7964211d | 1560 | #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F |
619c5cb6 VZ |
1561 | #define MACP_FUNC_CFG_FLAGS_SHIFT 0 |
1562 | #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 | |
1563 | #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 | |
1564 | #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 | |
1565 | #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 | |
7964211d | 1566 | #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 |
0793f83f DK |
1567 | |
1568 | u32 iscsi_mac_addr_upper; | |
1569 | u32 iscsi_mac_addr_lower; | |
1570 | ||
1571 | u32 fcoe_mac_addr_upper; | |
1572 | u32 fcoe_mac_addr_lower; | |
1573 | ||
1574 | u32 fcoe_wwn_port_name_upper; | |
1575 | u32 fcoe_wwn_port_name_lower; | |
1576 | ||
1577 | u32 fcoe_wwn_node_name_upper; | |
1578 | u32 fcoe_wwn_node_name_lower; | |
1579 | ||
1580 | u32 preserve_data; | |
619c5cb6 VZ |
1581 | #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) |
1582 | #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) | |
1583 | #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) | |
1584 | #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) | |
1585 | #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) | |
1586 | #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) | |
0793f83f DK |
1587 | }; |
1588 | ||
34f80b04 EG |
1589 | struct mf_cfg { |
1590 | ||
619c5cb6 | 1591 | struct shared_mf_cfg shared_mf_config; /* 0x4 */ |
621b4d66 DK |
1592 | /* 0x8*2*2=0x20 */ |
1593 | struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; | |
619c5cb6 VZ |
1594 | /* for all chips, there are 8 mf functions */ |
1595 | struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ | |
1596 | /* | |
1597 | * Extended configuration per function - this array does not exist and | |
1598 | * should not be accessed on 57711 | |
1599 | */ | |
1600 | struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ | |
1601 | }; /* 0x224 */ | |
34f80b04 | 1602 | |
a2fbb9ea | 1603 | /**************************************************************************** |
619c5cb6 | 1604 | * Shared Memory Region * |
a2fbb9ea | 1605 | ****************************************************************************/ |
619c5cb6 | 1606 | struct shmem_region { /* SharedMem Offset (size) */ |
f1410647 | 1607 | |
619c5cb6 VZ |
1608 | u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ |
1609 | #define SHR_MEM_FORMAT_REV_MASK 0xff000000 | |
1610 | #define SHR_MEM_FORMAT_REV_ID ('A'<<24) | |
f1410647 | 1611 | /* validity bits */ |
619c5cb6 VZ |
1612 | #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 |
1613 | #define SHR_MEM_VALIDITY_MB 0x00200000 | |
1614 | #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 | |
1615 | #define SHR_MEM_VALIDITY_RESERVED 0x00000007 | |
a2fbb9ea | 1616 | /* One licensing bit should be set */ |
619c5cb6 VZ |
1617 | #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 |
1618 | #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 | |
1619 | #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 | |
1620 | #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 | |
f1410647 | 1621 | /* Active MFW */ |
619c5cb6 VZ |
1622 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 |
1623 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 | |
1624 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 | |
1625 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 | |
1626 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 | |
1627 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 | |
a2fbb9ea | 1628 | |
619c5cb6 | 1629 | struct shm_dev_info dev_info; /* 0x8 (0x438) */ |
a2fbb9ea | 1630 | |
619c5cb6 | 1631 | struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ |
a2fbb9ea ET |
1632 | |
1633 | /* FW information (for internal FW use) */ | |
619c5cb6 VZ |
1634 | u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ |
1635 | struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ | |
f1410647 | 1636 | |
619c5cb6 VZ |
1637 | struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ |
1638 | ||
1639 | #ifdef BMAPI | |
1640 | /* This is a variable length array */ | |
1641 | /* the number of function depends on the chip type */ | |
1642 | struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ | |
1643 | #else | |
1644 | /* the number of function depends on the chip type */ | |
1645 | struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ | |
1646 | #endif /* BMAPI */ | |
523224a3 DK |
1647 | |
1648 | }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ | |
34f80b04 | 1649 | |
619c5cb6 VZ |
1650 | /**************************************************************************** |
1651 | * Shared Memory 2 Region * | |
1652 | ****************************************************************************/ | |
1653 | /* The fw_flr_ack is actually built in the following way: */ | |
1654 | /* 8 bit: PF ack */ | |
1655 | /* 64 bit: VF ack */ | |
1656 | /* 8 bit: ios_dis_ack */ | |
1657 | /* In order to maintain endianity in the mailbox hsi, we want to keep using */ | |
1658 | /* u32. The fw must have the VF right after the PF since this is how it */ | |
1659 | /* access arrays(it expects always the VF to reside after the PF, and that */ | |
1660 | /* makes the calculation much easier for it. ) */ | |
1661 | /* In order to answer both limitations, and keep the struct small, the code */ | |
1662 | /* will abuse the structure defined here to achieve the actual partition */ | |
1663 | /* above */ | |
1664 | /****************************************************************************/ | |
f2e0899f | 1665 | struct fw_flr_ack { |
619c5cb6 VZ |
1666 | u32 pf_ack; |
1667 | u32 vf_ack[1]; | |
1668 | u32 iov_dis_ack; | |
f2e0899f | 1669 | }; |
a2fbb9ea | 1670 | |
f2e0899f | 1671 | struct fw_flr_mb { |
619c5cb6 VZ |
1672 | u32 aggint; |
1673 | u32 opgen_addr; | |
1674 | struct fw_flr_ack ack; | |
f2e0899f | 1675 | }; |
a2fbb9ea | 1676 | |
c8c60d88 YM |
1677 | struct eee_remote_vals { |
1678 | u32 tx_tw; | |
1679 | u32 rx_tw; | |
1680 | }; | |
1681 | ||
e4901dde VZ |
1682 | /**** SUPPORT FOR SHMEM ARRRAYS *** |
1683 | * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to | |
1684 | * define arrays with storage types smaller then unsigned dwords. | |
1685 | * The macros below add generic support for SHMEM arrays with numeric elements | |
1686 | * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword | |
1687 | * array with individual bit-filed elements accessed using shifts and masks. | |
1688 | * | |
1689 | */ | |
1690 | ||
1691 | /* eb is the bitwidth of a single element */ | |
1692 | #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) | |
1693 | #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) | |
1694 | ||
1695 | /* the bit-position macro allows the used to flip the order of the arrays | |
1696 | * elements on a per byte or word boundary. | |
1697 | * | |
1698 | * example: an array with 8 entries each 4 bit wide. This array will fit into | |
1699 | * a single dword. The diagrmas below show the array order of the nibbles. | |
1700 | * | |
1701 | * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: | |
1702 | * | |
619c5cb6 VZ |
1703 | * | | | | |
1704 | * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | | |
1705 | * | | | | | |
e4901dde VZ |
1706 | * |
1707 | * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: | |
1708 | * | |
619c5cb6 VZ |
1709 | * | | | | |
1710 | * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | | |
1711 | * | | | | | |
e4901dde VZ |
1712 | * |
1713 | * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: | |
1714 | * | |
619c5cb6 VZ |
1715 | * | | | | |
1716 | * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | | |
1717 | * | | | | | |
e4901dde VZ |
1718 | */ |
1719 | #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ | |
1720 | ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ | |
1721 | (((i)%((fb)/(eb))) * (eb))) | |
1722 | ||
619c5cb6 | 1723 | #define SHMEM_ARRAY_GET(a, i, eb, fb) \ |
e4901dde VZ |
1724 | ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ |
1725 | SHMEM_ARRAY_MASK(eb)) | |
1726 | ||
619c5cb6 | 1727 | #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ |
e4901dde VZ |
1728 | do { \ |
1729 | a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ | |
619c5cb6 | 1730 | SHMEM_ARRAY_BITPOS(i, eb, fb)); \ |
e4901dde | 1731 | a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ |
619c5cb6 | 1732 | SHMEM_ARRAY_BITPOS(i, eb, fb)); \ |
e4901dde VZ |
1733 | } while (0) |
1734 | ||
1735 | ||
1736 | /****START OF DCBX STRUCTURES DECLARATIONS****/ | |
1737 | #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 | |
1738 | #define DCBX_PRI_PG_BITWIDTH 4 | |
1739 | #define DCBX_PRI_PG_FBITS 8 | |
1740 | #define DCBX_PRI_PG_GET(a, i) \ | |
1741 | SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) | |
1742 | #define DCBX_PRI_PG_SET(a, i, val) \ | |
1743 | SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) | |
1744 | #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 | |
1745 | #define DCBX_BW_PG_BITWIDTH 8 | |
1746 | #define DCBX_PG_BW_GET(a, i) \ | |
1747 | SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) | |
1748 | #define DCBX_PG_BW_SET(a, i, val) \ | |
1749 | SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) | |
1750 | #define DCBX_STRICT_PRI_PG 15 | |
1751 | #define DCBX_MAX_APP_PROTOCOL 16 | |
1752 | #define FCOE_APP_IDX 0 | |
1753 | #define ISCSI_APP_IDX 1 | |
1754 | #define PREDEFINED_APP_IDX_MAX 2 | |
1755 | ||
619c5cb6 VZ |
1756 | |
1757 | /* Big/Little endian have the same representation. */ | |
e4901dde | 1758 | struct dcbx_ets_feature { |
619c5cb6 VZ |
1759 | /* |
1760 | * For Admin MIB - is this feature supported by the | |
1761 | * driver | For Local MIB - should this feature be enabled. | |
1762 | */ | |
e4901dde VZ |
1763 | u32 enabled; |
1764 | u32 pg_bw_tbl[2]; | |
1765 | u32 pri_pg_tbl[1]; | |
1766 | }; | |
1767 | ||
619c5cb6 | 1768 | /* Driver structure in LE */ |
e4901dde VZ |
1769 | struct dcbx_pfc_feature { |
1770 | #ifdef __BIG_ENDIAN | |
1771 | u8 pri_en_bitmap; | |
619c5cb6 VZ |
1772 | #define DCBX_PFC_PRI_0 0x01 |
1773 | #define DCBX_PFC_PRI_1 0x02 | |
1774 | #define DCBX_PFC_PRI_2 0x04 | |
1775 | #define DCBX_PFC_PRI_3 0x08 | |
1776 | #define DCBX_PFC_PRI_4 0x10 | |
1777 | #define DCBX_PFC_PRI_5 0x20 | |
1778 | #define DCBX_PFC_PRI_6 0x40 | |
1779 | #define DCBX_PFC_PRI_7 0x80 | |
e4901dde VZ |
1780 | u8 pfc_caps; |
1781 | u8 reserved; | |
1782 | u8 enabled; | |
1783 | #elif defined(__LITTLE_ENDIAN) | |
1784 | u8 enabled; | |
1785 | u8 reserved; | |
1786 | u8 pfc_caps; | |
1787 | u8 pri_en_bitmap; | |
619c5cb6 VZ |
1788 | #define DCBX_PFC_PRI_0 0x01 |
1789 | #define DCBX_PFC_PRI_1 0x02 | |
1790 | #define DCBX_PFC_PRI_2 0x04 | |
1791 | #define DCBX_PFC_PRI_3 0x08 | |
1792 | #define DCBX_PFC_PRI_4 0x10 | |
1793 | #define DCBX_PFC_PRI_5 0x20 | |
1794 | #define DCBX_PFC_PRI_6 0x40 | |
1795 | #define DCBX_PFC_PRI_7 0x80 | |
e4901dde VZ |
1796 | #endif |
1797 | }; | |
1798 | ||
1799 | struct dcbx_app_priority_entry { | |
1800 | #ifdef __BIG_ENDIAN | |
619c5cb6 VZ |
1801 | u16 app_id; |
1802 | u8 pri_bitmap; | |
1803 | u8 appBitfield; | |
1804 | #define DCBX_APP_ENTRY_VALID 0x01 | |
1805 | #define DCBX_APP_ENTRY_SF_MASK 0x30 | |
1806 | #define DCBX_APP_ENTRY_SF_SHIFT 4 | |
1807 | #define DCBX_APP_SF_ETH_TYPE 0x10 | |
1808 | #define DCBX_APP_SF_PORT 0x20 | |
e4901dde VZ |
1809 | #elif defined(__LITTLE_ENDIAN) |
1810 | u8 appBitfield; | |
619c5cb6 VZ |
1811 | #define DCBX_APP_ENTRY_VALID 0x01 |
1812 | #define DCBX_APP_ENTRY_SF_MASK 0x30 | |
1813 | #define DCBX_APP_ENTRY_SF_SHIFT 4 | |
1814 | #define DCBX_APP_SF_ETH_TYPE 0x10 | |
1815 | #define DCBX_APP_SF_PORT 0x20 | |
1816 | u8 pri_bitmap; | |
1817 | u16 app_id; | |
e4901dde VZ |
1818 | #endif |
1819 | }; | |
1820 | ||
619c5cb6 VZ |
1821 | |
1822 | /* FW structure in BE */ | |
e4901dde VZ |
1823 | struct dcbx_app_priority_feature { |
1824 | #ifdef __BIG_ENDIAN | |
1825 | u8 reserved; | |
1826 | u8 default_pri; | |
1827 | u8 tc_supported; | |
1828 | u8 enabled; | |
1829 | #elif defined(__LITTLE_ENDIAN) | |
1830 | u8 enabled; | |
1831 | u8 tc_supported; | |
1832 | u8 default_pri; | |
1833 | u8 reserved; | |
1834 | #endif | |
1835 | struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; | |
1836 | }; | |
1837 | ||
619c5cb6 | 1838 | /* FW structure in BE */ |
e4901dde | 1839 | struct dcbx_features { |
619c5cb6 | 1840 | /* PG feature */ |
e4901dde | 1841 | struct dcbx_ets_feature ets; |
619c5cb6 | 1842 | /* PFC feature */ |
e4901dde | 1843 | struct dcbx_pfc_feature pfc; |
619c5cb6 | 1844 | /* APP feature */ |
e4901dde VZ |
1845 | struct dcbx_app_priority_feature app; |
1846 | }; | |
1847 | ||
619c5cb6 VZ |
1848 | /* LLDP protocol parameters */ |
1849 | /* FW structure in BE */ | |
e4901dde VZ |
1850 | struct lldp_params { |
1851 | #ifdef __BIG_ENDIAN | |
619c5cb6 VZ |
1852 | u8 msg_fast_tx_interval; |
1853 | u8 msg_tx_hold; | |
1854 | u8 msg_tx_interval; | |
1855 | u8 admin_status; | |
1856 | #define LLDP_TX_ONLY 0x01 | |
1857 | #define LLDP_RX_ONLY 0x02 | |
1858 | #define LLDP_TX_RX 0x03 | |
1859 | #define LLDP_DISABLED 0x04 | |
1860 | u8 reserved1; | |
1861 | u8 tx_fast; | |
1862 | u8 tx_crd_max; | |
1863 | u8 tx_crd; | |
e4901dde | 1864 | #elif defined(__LITTLE_ENDIAN) |
619c5cb6 VZ |
1865 | u8 admin_status; |
1866 | #define LLDP_TX_ONLY 0x01 | |
1867 | #define LLDP_RX_ONLY 0x02 | |
1868 | #define LLDP_TX_RX 0x03 | |
1869 | #define LLDP_DISABLED 0x04 | |
1870 | u8 msg_tx_interval; | |
1871 | u8 msg_tx_hold; | |
1872 | u8 msg_fast_tx_interval; | |
1873 | u8 tx_crd; | |
1874 | u8 tx_crd_max; | |
1875 | u8 tx_fast; | |
1876 | u8 reserved1; | |
e4901dde | 1877 | #endif |
619c5cb6 VZ |
1878 | #define REM_CHASSIS_ID_STAT_LEN 4 |
1879 | #define REM_PORT_ID_STAT_LEN 4 | |
1880 | /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ | |
e4901dde | 1881 | u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; |
619c5cb6 | 1882 | /* Holds remote Port ID TLV header, subtype and 9B of payload. */ |
e4901dde VZ |
1883 | u32 peer_port_id[REM_PORT_ID_STAT_LEN]; |
1884 | }; | |
1885 | ||
1886 | struct lldp_dcbx_stat { | |
619c5cb6 VZ |
1887 | #define LOCAL_CHASSIS_ID_STAT_LEN 2 |
1888 | #define LOCAL_PORT_ID_STAT_LEN 2 | |
1889 | /* Holds local Chassis ID 8B payload of constant subtype 4. */ | |
e4901dde | 1890 | u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; |
619c5cb6 | 1891 | /* Holds local Port ID 8B payload of constant subtype 3. */ |
e4901dde | 1892 | u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; |
619c5cb6 | 1893 | /* Number of DCBX frames transmitted. */ |
e4901dde | 1894 | u32 num_tx_dcbx_pkts; |
619c5cb6 | 1895 | /* Number of DCBX frames received. */ |
e4901dde VZ |
1896 | u32 num_rx_dcbx_pkts; |
1897 | }; | |
1898 | ||
619c5cb6 | 1899 | /* ADMIN MIB - DCBX local machine default configuration. */ |
e4901dde | 1900 | struct lldp_admin_mib { |
619c5cb6 VZ |
1901 | u32 ver_cfg_flags; |
1902 | #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 | |
1903 | #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 | |
1904 | #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 | |
1905 | #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 | |
1906 | #define DCBX_ETS_RECO_VALID 0x00000010 | |
1907 | #define DCBX_ETS_WILLING 0x00000020 | |
1908 | #define DCBX_PFC_WILLING 0x00000040 | |
1909 | #define DCBX_APP_WILLING 0x00000080 | |
1910 | #define DCBX_VERSION_CEE 0x00000100 | |
1911 | #define DCBX_VERSION_IEEE 0x00000200 | |
1912 | #define DCBX_DCBX_ENABLED 0x00000400 | |
1913 | #define DCBX_CEE_VERSION_MASK 0x0000f000 | |
1914 | #define DCBX_CEE_VERSION_SHIFT 12 | |
1915 | #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 | |
1916 | #define DCBX_CEE_MAX_VERSION_SHIFT 16 | |
1917 | struct dcbx_features features; | |
1918 | }; | |
1919 | ||
1920 | /* REMOTE MIB - remote machine DCBX configuration. */ | |
e4901dde VZ |
1921 | struct lldp_remote_mib { |
1922 | u32 prefix_seq_num; | |
1923 | u32 flags; | |
619c5cb6 VZ |
1924 | #define DCBX_ETS_TLV_RX 0x00000001 |
1925 | #define DCBX_PFC_TLV_RX 0x00000002 | |
1926 | #define DCBX_APP_TLV_RX 0x00000004 | |
1927 | #define DCBX_ETS_RX_ERROR 0x00000010 | |
1928 | #define DCBX_PFC_RX_ERROR 0x00000020 | |
1929 | #define DCBX_APP_RX_ERROR 0x00000040 | |
1930 | #define DCBX_ETS_REM_WILLING 0x00000100 | |
1931 | #define DCBX_PFC_REM_WILLING 0x00000200 | |
1932 | #define DCBX_APP_REM_WILLING 0x00000400 | |
1933 | #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 | |
1934 | #define DCBX_REMOTE_MIB_VALID 0x00002000 | |
e4901dde VZ |
1935 | struct dcbx_features features; |
1936 | u32 suffix_seq_num; | |
1937 | }; | |
1938 | ||
619c5cb6 | 1939 | /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ |
e4901dde VZ |
1940 | struct lldp_local_mib { |
1941 | u32 prefix_seq_num; | |
619c5cb6 | 1942 | /* Indicates if there is mismatch with negotiation results. */ |
e4901dde | 1943 | u32 error; |
619c5cb6 VZ |
1944 | #define DCBX_LOCAL_ETS_ERROR 0x00000001 |
1945 | #define DCBX_LOCAL_PFC_ERROR 0x00000002 | |
1946 | #define DCBX_LOCAL_APP_ERROR 0x00000004 | |
1947 | #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 | |
1948 | #define DCBX_LOCAL_APP_MISMATCH 0x00000020 | |
6debea87 | 1949 | #define DCBX_REMOTE_MIB_ERROR 0x00000040 |
910b2202 DK |
1950 | #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 |
1951 | #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 | |
1952 | #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 | |
e4901dde VZ |
1953 | struct dcbx_features features; |
1954 | u32 suffix_seq_num; | |
1955 | }; | |
1956 | /***END OF DCBX STRUCTURES DECLARATIONS***/ | |
a2fbb9ea | 1957 | |
d3a8f13b YR |
1958 | /***********************************************************/ |
1959 | /* Elink section */ | |
1960 | /***********************************************************/ | |
1961 | #define SHMEM_LINK_CONFIG_SIZE 2 | |
1962 | struct shmem_lfa { | |
1963 | u32 req_duplex; | |
1964 | #define REQ_DUPLEX_PHY0_MASK 0x0000ffff | |
1965 | #define REQ_DUPLEX_PHY0_SHIFT 0 | |
1966 | #define REQ_DUPLEX_PHY1_MASK 0xffff0000 | |
1967 | #define REQ_DUPLEX_PHY1_SHIFT 16 | |
1968 | u32 req_flow_ctrl; | |
1969 | #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff | |
1970 | #define REQ_FLOW_CTRL_PHY0_SHIFT 0 | |
1971 | #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 | |
1972 | #define REQ_FLOW_CTRL_PHY1_SHIFT 16 | |
1973 | u32 req_line_speed; /* Also determine AutoNeg */ | |
1974 | #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff | |
1975 | #define REQ_LINE_SPD_PHY0_SHIFT 0 | |
1976 | #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 | |
1977 | #define REQ_LINE_SPD_PHY1_SHIFT 16 | |
1978 | u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; | |
1979 | u32 additional_config; | |
1980 | #define REQ_FC_AUTO_ADV_MASK 0x0000ffff | |
1981 | #define REQ_FC_AUTO_ADV0_SHIFT 0 | |
1982 | #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 | |
1983 | u32 lfa_sts; | |
1984 | #define LFA_LINK_FLAP_REASON_OFFSET 0 | |
1985 | #define LFA_LINK_FLAP_REASON_MASK 0x000000ff | |
1986 | #define LFA_LINK_DOWN 0x1 | |
1987 | #define LFA_LOOPBACK_ENABLED 0x2 | |
1988 | #define LFA_DUPLEX_MISMATCH 0x3 | |
1989 | #define LFA_MFW_IS_TOO_OLD 0x4 | |
1990 | #define LFA_LINK_SPEED_MISMATCH 0x5 | |
1991 | #define LFA_FLOW_CTRL_MISMATCH 0x6 | |
1992 | #define LFA_SPEED_CAP_MISMATCH 0x7 | |
1993 | #define LFA_DCC_LFA_DISABLED 0x8 | |
1994 | #define LFA_EEE_MISMATCH 0x9 | |
1995 | ||
1996 | #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 | |
1997 | #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 | |
1998 | ||
1999 | #define LINK_FLAP_COUNT_OFFSET 16 | |
2000 | #define LINK_FLAP_COUNT_MASK 0x00ff0000 | |
2001 | ||
2002 | #define LFA_FLAGS_MASK 0xff000000 | |
2003 | #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) | |
2004 | }; | |
2005 | ||
42f8277f YM |
2006 | /* Used to support NSCI get OS driver version |
2007 | * on driver load the version value will be set | |
2008 | * on driver unload driver value of 0x0 will be set. | |
2009 | */ | |
2010 | struct os_drv_ver { | |
2011 | #define DRV_VER_NOT_LOADED 0 | |
2012 | ||
2013 | /* personalties order is important */ | |
2014 | #define DRV_PERS_ETHERNET 0 | |
2015 | #define DRV_PERS_ISCSI 1 | |
2016 | #define DRV_PERS_FCOE 2 | |
2017 | ||
2018 | /* shmem2 struct is constant can't add more personalties here */ | |
2019 | #define MAX_DRV_PERS 3 | |
2020 | u32 versions[MAX_DRV_PERS]; | |
2021 | }; | |
2022 | ||
619c5cb6 VZ |
2023 | struct ncsi_oem_fcoe_features { |
2024 | u32 fcoe_features1; | |
2025 | #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF | |
2026 | #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 | |
2027 | ||
2028 | #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 | |
2029 | #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 | |
2030 | ||
2031 | u32 fcoe_features2; | |
2032 | #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF | |
2033 | #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 | |
2034 | ||
2035 | #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 | |
2036 | #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 | |
2037 | ||
2038 | u32 fcoe_features3; | |
2039 | #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF | |
2040 | #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 | |
2041 | ||
2042 | #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 | |
2043 | #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 | |
2044 | ||
2045 | u32 fcoe_features4; | |
2046 | #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F | |
2047 | #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 | |
2048 | }; | |
2049 | ||
2050 | struct ncsi_oem_data { | |
2051 | u32 driver_version[4]; | |
2052 | struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; | |
2053 | }; | |
2054 | ||
2691d51d EG |
2055 | struct shmem2_region { |
2056 | ||
619c5cb6 VZ |
2057 | u32 size; /* 0x0000 */ |
2058 | ||
2059 | u32 dcc_support; /* 0x0004 */ | |
2060 | #define SHMEM_DCC_SUPPORT_NONE 0x00000000 | |
2061 | #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 | |
2062 | #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 | |
2063 | #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 | |
2064 | #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 | |
2065 | #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 | |
2066 | ||
2067 | u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ | |
a22f0788 YR |
2068 | /* |
2069 | * For backwards compatibility, if the mf_cfg_addr does not exist | |
2070 | * (the size filed is smaller than 0xc) the mf_cfg resides at the | |
2071 | * end of struct shmem_region | |
619c5cb6 VZ |
2072 | */ |
2073 | u32 mf_cfg_addr; /* 0x0010 */ | |
2074 | #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 | |
2075 | ||
2076 | struct fw_flr_mb flr_mb; /* 0x0014 */ | |
2077 | u32 dcbx_lldp_params_offset; /* 0x0028 */ | |
2078 | #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 | |
2079 | u32 dcbx_neg_res_offset; /* 0x002c */ | |
2080 | #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 | |
2081 | u32 dcbx_remote_mib_offset; /* 0x0030 */ | |
2082 | #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 | |
f2e0899f DK |
2083 | /* |
2084 | * The other shmemX_base_addr holds the other path's shmem address | |
2085 | * required for example in case of common phy init, or for path1 to know | |
2086 | * the address of mcp debug trace which is located in offset from shmem | |
2087 | * of path0 | |
a22f0788 | 2088 | */ |
619c5cb6 VZ |
2089 | u32 other_shmem_base_addr; /* 0x0034 */ |
2090 | u32 other_shmem2_base_addr; /* 0x0038 */ | |
2091 | /* | |
2092 | * mcp_vf_disabled is set by the MCP to indicate the driver about VFs | |
2093 | * which were disabled/flred | |
2094 | */ | |
2095 | u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ | |
2096 | ||
2097 | /* | |
2098 | * drv_ack_vf_disabled is set by the PF driver to ack handled disabled | |
2099 | * VFs | |
2100 | */ | |
2101 | u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ | |
2102 | ||
2103 | u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ | |
2104 | #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 | |
2105 | ||
2106 | /* | |
2107 | * edebug_driver_if field is used to transfer messages between edebug | |
2108 | * app to the driver through shmem2. | |
2109 | * | |
2110 | * message format: | |
2111 | * bits 0-2 - function number / instance of driver to perform request | |
2112 | * bits 3-5 - op code / is_ack? | |
2113 | * bits 6-63 - data | |
2114 | */ | |
2115 | u32 edebug_driver_if[2]; /* 0x0068 */ | |
2116 | #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 | |
2117 | #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 | |
2118 | #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 | |
2119 | ||
2120 | u32 nvm_retain_bitmap_addr; /* 0x0070 */ | |
2121 | ||
a3348722 BW |
2122 | /* afex support of that driver */ |
2123 | u32 afex_driver_support; /* 0x0074 */ | |
2124 | #define SHMEM_AFEX_VERSION_MASK 0x100f | |
2125 | #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 | |
2126 | #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 | |
619c5cb6 | 2127 | |
a3348722 BW |
2128 | /* driver receives addr in scratchpad to which it should respond */ |
2129 | u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX]; | |
619c5cb6 | 2130 | |
a3348722 BW |
2131 | /* generic params from MCP to driver (value depends on the msg sent |
2132 | * to driver | |
2133 | */ | |
2134 | u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ | |
2135 | u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ | |
619c5cb6 VZ |
2136 | |
2137 | u32 swim_base_addr; /* 0x0108 */ | |
2138 | u32 swim_funcs; | |
2139 | u32 swim_main_cb; | |
2140 | ||
a3348722 BW |
2141 | /* bitmap notifying which VIF profiles stored in nvram are enabled by |
2142 | * switch | |
2143 | */ | |
2144 | u32 afex_profiles_enabled[2]; | |
619c5cb6 VZ |
2145 | |
2146 | /* generic flags controlled by the driver */ | |
2147 | u32 drv_flags; | |
4c704899 BW |
2148 | #define DRV_FLAGS_DCB_CONFIGURED 0x0 |
2149 | #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 | |
2150 | #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 | |
619c5cb6 | 2151 | |
4c704899 BW |
2152 | #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ |
2153 | (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ | |
2154 | (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) | |
619c5cb6 VZ |
2155 | /* pointer to extended dev_info shared data copied from nvm image */ |
2156 | u32 extended_dev_info_shared_addr; | |
2157 | u32 ncsi_oem_data_addr; | |
2158 | ||
1d187b34 BW |
2159 | u32 ocsd_host_addr; /* initialized by option ROM */ |
2160 | u32 ocbb_host_addr; /* initialized by option ROM */ | |
2161 | u32 ocsd_req_update_interval; /* initialized by option ROM */ | |
2162 | u32 temperature_in_half_celsius; | |
2163 | u32 glob_struct_in_host; | |
2164 | ||
2165 | u32 dcbx_neg_res_ext_offset; | |
2166 | #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 | |
2167 | ||
2168 | u32 drv_capabilities_flag[E2_FUNC_MAX]; | |
2169 | #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 | |
2170 | #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 | |
2171 | #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 | |
2172 | #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 | |
2173 | ||
2174 | u32 extended_dev_info_shared_cfg_size; | |
2175 | ||
2176 | u32 dcbx_en[PORT_MAX]; | |
2177 | ||
2178 | /* The offset points to the multi threaded meta structure */ | |
2179 | u32 multi_thread_data_offset; | |
2180 | ||
2181 | /* address of DMAable host address holding values from the drivers */ | |
2182 | u32 drv_info_host_addr_lo; | |
2183 | u32 drv_info_host_addr_hi; | |
2184 | ||
2185 | /* general values written by the MFW (such as current version) */ | |
2186 | u32 drv_info_control; | |
2187 | #define DRV_INFO_CONTROL_VER_MASK 0x000000ff | |
2188 | #define DRV_INFO_CONTROL_VER_SHIFT 0 | |
2189 | #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 | |
2190 | #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 | |
621b4d66 | 2191 | u32 ibft_host_addr; /* initialized by option ROM */ |
c8c60d88 YM |
2192 | struct eee_remote_vals eee_remote_vals[PORT_MAX]; |
2193 | u32 reserved[E2_FUNC_MAX]; | |
2194 | ||
2195 | ||
2196 | /* the status of EEE auto-negotiation | |
2197 | * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. | |
2198 | * bits 19:16 the supported modes for EEE. | |
2199 | * bits 23:20 the speeds advertised for EEE. | |
2200 | * bits 27:24 the speeds the Link partner advertised for EEE. | |
2201 | * The supported/adv. modes in bits 27:19 originate from the | |
2202 | * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). | |
2203 | * bit 28 when 1'b1 EEE was requested. | |
2204 | * bit 29 when 1'b1 tx lpi was requested. | |
2205 | * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff | |
2206 | * 30:29 are 2'b11. | |
2207 | * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as | |
2208 | * value. When 1'b1 those bits contains a value times 16 microseconds. | |
2209 | */ | |
2210 | u32 eee_status[PORT_MAX]; | |
2211 | #define SHMEM_EEE_TIMER_MASK 0x0000ffff | |
2212 | #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 | |
2213 | #define SHMEM_EEE_SUPPORTED_SHIFT 16 | |
2214 | #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 | |
2215 | #define SHMEM_EEE_100M_ADV (1<<0) | |
2216 | #define SHMEM_EEE_1G_ADV (1<<1) | |
2217 | #define SHMEM_EEE_10G_ADV (1<<2) | |
2218 | #define SHMEM_EEE_ADV_STATUS_SHIFT 20 | |
2219 | #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 | |
2220 | #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 | |
2221 | #define SHMEM_EEE_REQUESTED_BIT 0x10000000 | |
2222 | #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 | |
2223 | #define SHMEM_EEE_ACTIVE_BIT 0x40000000 | |
2224 | #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 | |
2225 | ||
2226 | u32 sizeof_port_stats; | |
b884d95b YR |
2227 | |
2228 | /* Link Flap Avoidance */ | |
2229 | u32 lfa_host_addr[PORT_MAX]; | |
2230 | u32 reserved1; | |
2231 | ||
2232 | u32 reserved2; /* Offset 0x148 */ | |
2233 | u32 reserved3; /* Offset 0x14C */ | |
2234 | u32 reserved4; /* Offset 0x150 */ | |
4e7b4997 | 2235 | u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */ |
6e9e5644 YR |
2236 | #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001 |
2237 | #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00 | |
2238 | #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8 | |
2239 | #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000 | |
2240 | #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000 | |
2241 | #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000 | |
42f8277f YM |
2242 | |
2243 | u32 reserved5[2]; | |
2244 | u32 reserved6[PORT_MAX]; | |
2245 | ||
2246 | /* driver version for each personality */ | |
2247 | struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */ | |
2248 | ||
2249 | /* Flag to the driver that PF's drv_info_host_addr buffer was read */ | |
2250 | u32 mfw_drv_indication; | |
2251 | ||
2252 | /* We use indication for each PF (0..3) */ | |
2253 | #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_)) | |
2691d51d EG |
2254 | }; |
2255 | ||
2256 | ||
bb2a0f7a | 2257 | struct emac_stats { |
619c5cb6 VZ |
2258 | u32 rx_stat_ifhcinoctets; |
2259 | u32 rx_stat_ifhcinbadoctets; | |
2260 | u32 rx_stat_etherstatsfragments; | |
2261 | u32 rx_stat_ifhcinucastpkts; | |
2262 | u32 rx_stat_ifhcinmulticastpkts; | |
2263 | u32 rx_stat_ifhcinbroadcastpkts; | |
2264 | u32 rx_stat_dot3statsfcserrors; | |
2265 | u32 rx_stat_dot3statsalignmenterrors; | |
2266 | u32 rx_stat_dot3statscarriersenseerrors; | |
2267 | u32 rx_stat_xonpauseframesreceived; | |
2268 | u32 rx_stat_xoffpauseframesreceived; | |
2269 | u32 rx_stat_maccontrolframesreceived; | |
2270 | u32 rx_stat_xoffstateentered; | |
2271 | u32 rx_stat_dot3statsframestoolong; | |
2272 | u32 rx_stat_etherstatsjabbers; | |
2273 | u32 rx_stat_etherstatsundersizepkts; | |
2274 | u32 rx_stat_etherstatspkts64octets; | |
2275 | u32 rx_stat_etherstatspkts65octetsto127octets; | |
2276 | u32 rx_stat_etherstatspkts128octetsto255octets; | |
2277 | u32 rx_stat_etherstatspkts256octetsto511octets; | |
2278 | u32 rx_stat_etherstatspkts512octetsto1023octets; | |
2279 | u32 rx_stat_etherstatspkts1024octetsto1522octets; | |
2280 | u32 rx_stat_etherstatspktsover1522octets; | |
2281 | ||
2282 | u32 rx_stat_falsecarriererrors; | |
2283 | ||
2284 | u32 tx_stat_ifhcoutoctets; | |
2285 | u32 tx_stat_ifhcoutbadoctets; | |
2286 | u32 tx_stat_etherstatscollisions; | |
2287 | u32 tx_stat_outxonsent; | |
2288 | u32 tx_stat_outxoffsent; | |
2289 | u32 tx_stat_flowcontroldone; | |
2290 | u32 tx_stat_dot3statssinglecollisionframes; | |
2291 | u32 tx_stat_dot3statsmultiplecollisionframes; | |
2292 | u32 tx_stat_dot3statsdeferredtransmissions; | |
2293 | u32 tx_stat_dot3statsexcessivecollisions; | |
2294 | u32 tx_stat_dot3statslatecollisions; | |
2295 | u32 tx_stat_ifhcoutucastpkts; | |
2296 | u32 tx_stat_ifhcoutmulticastpkts; | |
2297 | u32 tx_stat_ifhcoutbroadcastpkts; | |
2298 | u32 tx_stat_etherstatspkts64octets; | |
2299 | u32 tx_stat_etherstatspkts65octetsto127octets; | |
2300 | u32 tx_stat_etherstatspkts128octetsto255octets; | |
2301 | u32 tx_stat_etherstatspkts256octetsto511octets; | |
2302 | u32 tx_stat_etherstatspkts512octetsto1023octets; | |
2303 | u32 tx_stat_etherstatspkts1024octetsto1522octets; | |
2304 | u32 tx_stat_etherstatspktsover1522octets; | |
2305 | u32 tx_stat_dot3statsinternalmactransmiterrors; | |
bb2a0f7a YG |
2306 | }; |
2307 | ||
2308 | ||
523224a3 | 2309 | struct bmac1_stats { |
619c5cb6 VZ |
2310 | u32 tx_stat_gtpkt_lo; |
2311 | u32 tx_stat_gtpkt_hi; | |
2312 | u32 tx_stat_gtxpf_lo; | |
2313 | u32 tx_stat_gtxpf_hi; | |
2314 | u32 tx_stat_gtfcs_lo; | |
2315 | u32 tx_stat_gtfcs_hi; | |
2316 | u32 tx_stat_gtmca_lo; | |
2317 | u32 tx_stat_gtmca_hi; | |
2318 | u32 tx_stat_gtbca_lo; | |
2319 | u32 tx_stat_gtbca_hi; | |
2320 | u32 tx_stat_gtfrg_lo; | |
2321 | u32 tx_stat_gtfrg_hi; | |
2322 | u32 tx_stat_gtovr_lo; | |
2323 | u32 tx_stat_gtovr_hi; | |
2324 | u32 tx_stat_gt64_lo; | |
2325 | u32 tx_stat_gt64_hi; | |
2326 | u32 tx_stat_gt127_lo; | |
2327 | u32 tx_stat_gt127_hi; | |
2328 | u32 tx_stat_gt255_lo; | |
2329 | u32 tx_stat_gt255_hi; | |
2330 | u32 tx_stat_gt511_lo; | |
2331 | u32 tx_stat_gt511_hi; | |
2332 | u32 tx_stat_gt1023_lo; | |
2333 | u32 tx_stat_gt1023_hi; | |
2334 | u32 tx_stat_gt1518_lo; | |
2335 | u32 tx_stat_gt1518_hi; | |
2336 | u32 tx_stat_gt2047_lo; | |
2337 | u32 tx_stat_gt2047_hi; | |
2338 | u32 tx_stat_gt4095_lo; | |
2339 | u32 tx_stat_gt4095_hi; | |
2340 | u32 tx_stat_gt9216_lo; | |
2341 | u32 tx_stat_gt9216_hi; | |
2342 | u32 tx_stat_gt16383_lo; | |
2343 | u32 tx_stat_gt16383_hi; | |
2344 | u32 tx_stat_gtmax_lo; | |
2345 | u32 tx_stat_gtmax_hi; | |
2346 | u32 tx_stat_gtufl_lo; | |
2347 | u32 tx_stat_gtufl_hi; | |
2348 | u32 tx_stat_gterr_lo; | |
2349 | u32 tx_stat_gterr_hi; | |
2350 | u32 tx_stat_gtbyt_lo; | |
2351 | u32 tx_stat_gtbyt_hi; | |
2352 | ||
2353 | u32 rx_stat_gr64_lo; | |
2354 | u32 rx_stat_gr64_hi; | |
2355 | u32 rx_stat_gr127_lo; | |
2356 | u32 rx_stat_gr127_hi; | |
2357 | u32 rx_stat_gr255_lo; | |
2358 | u32 rx_stat_gr255_hi; | |
2359 | u32 rx_stat_gr511_lo; | |
2360 | u32 rx_stat_gr511_hi; | |
2361 | u32 rx_stat_gr1023_lo; | |
2362 | u32 rx_stat_gr1023_hi; | |
2363 | u32 rx_stat_gr1518_lo; | |
2364 | u32 rx_stat_gr1518_hi; | |
2365 | u32 rx_stat_gr2047_lo; | |
2366 | u32 rx_stat_gr2047_hi; | |
2367 | u32 rx_stat_gr4095_lo; | |
2368 | u32 rx_stat_gr4095_hi; | |
2369 | u32 rx_stat_gr9216_lo; | |
2370 | u32 rx_stat_gr9216_hi; | |
2371 | u32 rx_stat_gr16383_lo; | |
2372 | u32 rx_stat_gr16383_hi; | |
2373 | u32 rx_stat_grmax_lo; | |
2374 | u32 rx_stat_grmax_hi; | |
2375 | u32 rx_stat_grpkt_lo; | |
2376 | u32 rx_stat_grpkt_hi; | |
2377 | u32 rx_stat_grfcs_lo; | |
2378 | u32 rx_stat_grfcs_hi; | |
2379 | u32 rx_stat_grmca_lo; | |
2380 | u32 rx_stat_grmca_hi; | |
2381 | u32 rx_stat_grbca_lo; | |
2382 | u32 rx_stat_grbca_hi; | |
2383 | u32 rx_stat_grxcf_lo; | |
2384 | u32 rx_stat_grxcf_hi; | |
2385 | u32 rx_stat_grxpf_lo; | |
2386 | u32 rx_stat_grxpf_hi; | |
2387 | u32 rx_stat_grxuo_lo; | |
2388 | u32 rx_stat_grxuo_hi; | |
2389 | u32 rx_stat_grjbr_lo; | |
2390 | u32 rx_stat_grjbr_hi; | |
2391 | u32 rx_stat_grovr_lo; | |
2392 | u32 rx_stat_grovr_hi; | |
2393 | u32 rx_stat_grflr_lo; | |
2394 | u32 rx_stat_grflr_hi; | |
2395 | u32 rx_stat_grmeg_lo; | |
2396 | u32 rx_stat_grmeg_hi; | |
2397 | u32 rx_stat_grmeb_lo; | |
2398 | u32 rx_stat_grmeb_hi; | |
2399 | u32 rx_stat_grbyt_lo; | |
2400 | u32 rx_stat_grbyt_hi; | |
2401 | u32 rx_stat_grund_lo; | |
2402 | u32 rx_stat_grund_hi; | |
2403 | u32 rx_stat_grfrg_lo; | |
2404 | u32 rx_stat_grfrg_hi; | |
2405 | u32 rx_stat_grerb_lo; | |
2406 | u32 rx_stat_grerb_hi; | |
2407 | u32 rx_stat_grfre_lo; | |
2408 | u32 rx_stat_grfre_hi; | |
2409 | u32 rx_stat_gripj_lo; | |
2410 | u32 rx_stat_gripj_hi; | |
bb2a0f7a YG |
2411 | }; |
2412 | ||
f2e0899f DK |
2413 | struct bmac2_stats { |
2414 | u32 tx_stat_gtpk_lo; /* gtpok */ | |
2415 | u32 tx_stat_gtpk_hi; /* gtpok */ | |
2416 | u32 tx_stat_gtxpf_lo; /* gtpf */ | |
2417 | u32 tx_stat_gtxpf_hi; /* gtpf */ | |
2418 | u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ | |
2419 | u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ | |
2420 | u32 tx_stat_gtfcs_lo; | |
2421 | u32 tx_stat_gtfcs_hi; | |
2422 | u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ | |
2423 | u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ | |
2424 | u32 tx_stat_gtmca_lo; | |
2425 | u32 tx_stat_gtmca_hi; | |
2426 | u32 tx_stat_gtbca_lo; | |
2427 | u32 tx_stat_gtbca_hi; | |
2428 | u32 tx_stat_gtovr_lo; | |
2429 | u32 tx_stat_gtovr_hi; | |
2430 | u32 tx_stat_gtfrg_lo; | |
2431 | u32 tx_stat_gtfrg_hi; | |
2432 | u32 tx_stat_gtpkt1_lo; /* gtpkt */ | |
2433 | u32 tx_stat_gtpkt1_hi; /* gtpkt */ | |
2434 | u32 tx_stat_gt64_lo; | |
2435 | u32 tx_stat_gt64_hi; | |
2436 | u32 tx_stat_gt127_lo; | |
2437 | u32 tx_stat_gt127_hi; | |
2438 | u32 tx_stat_gt255_lo; | |
2439 | u32 tx_stat_gt255_hi; | |
2440 | u32 tx_stat_gt511_lo; | |
2441 | u32 tx_stat_gt511_hi; | |
2442 | u32 tx_stat_gt1023_lo; | |
2443 | u32 tx_stat_gt1023_hi; | |
2444 | u32 tx_stat_gt1518_lo; | |
2445 | u32 tx_stat_gt1518_hi; | |
2446 | u32 tx_stat_gt2047_lo; | |
2447 | u32 tx_stat_gt2047_hi; | |
2448 | u32 tx_stat_gt4095_lo; | |
2449 | u32 tx_stat_gt4095_hi; | |
2450 | u32 tx_stat_gt9216_lo; | |
2451 | u32 tx_stat_gt9216_hi; | |
2452 | u32 tx_stat_gt16383_lo; | |
2453 | u32 tx_stat_gt16383_hi; | |
2454 | u32 tx_stat_gtmax_lo; | |
2455 | u32 tx_stat_gtmax_hi; | |
2456 | u32 tx_stat_gtufl_lo; | |
2457 | u32 tx_stat_gtufl_hi; | |
2458 | u32 tx_stat_gterr_lo; | |
2459 | u32 tx_stat_gterr_hi; | |
2460 | u32 tx_stat_gtbyt_lo; | |
2461 | u32 tx_stat_gtbyt_hi; | |
2462 | ||
2463 | u32 rx_stat_gr64_lo; | |
2464 | u32 rx_stat_gr64_hi; | |
2465 | u32 rx_stat_gr127_lo; | |
2466 | u32 rx_stat_gr127_hi; | |
2467 | u32 rx_stat_gr255_lo; | |
2468 | u32 rx_stat_gr255_hi; | |
2469 | u32 rx_stat_gr511_lo; | |
2470 | u32 rx_stat_gr511_hi; | |
2471 | u32 rx_stat_gr1023_lo; | |
2472 | u32 rx_stat_gr1023_hi; | |
2473 | u32 rx_stat_gr1518_lo; | |
2474 | u32 rx_stat_gr1518_hi; | |
2475 | u32 rx_stat_gr2047_lo; | |
2476 | u32 rx_stat_gr2047_hi; | |
2477 | u32 rx_stat_gr4095_lo; | |
2478 | u32 rx_stat_gr4095_hi; | |
2479 | u32 rx_stat_gr9216_lo; | |
2480 | u32 rx_stat_gr9216_hi; | |
2481 | u32 rx_stat_gr16383_lo; | |
2482 | u32 rx_stat_gr16383_hi; | |
2483 | u32 rx_stat_grmax_lo; | |
2484 | u32 rx_stat_grmax_hi; | |
2485 | u32 rx_stat_grpkt_lo; | |
2486 | u32 rx_stat_grpkt_hi; | |
2487 | u32 rx_stat_grfcs_lo; | |
2488 | u32 rx_stat_grfcs_hi; | |
2489 | u32 rx_stat_gruca_lo; | |
2490 | u32 rx_stat_gruca_hi; | |
2491 | u32 rx_stat_grmca_lo; | |
2492 | u32 rx_stat_grmca_hi; | |
2493 | u32 rx_stat_grbca_lo; | |
2494 | u32 rx_stat_grbca_hi; | |
2495 | u32 rx_stat_grxpf_lo; /* grpf */ | |
2496 | u32 rx_stat_grxpf_hi; /* grpf */ | |
2497 | u32 rx_stat_grpp_lo; | |
2498 | u32 rx_stat_grpp_hi; | |
2499 | u32 rx_stat_grxuo_lo; /* gruo */ | |
2500 | u32 rx_stat_grxuo_hi; /* gruo */ | |
2501 | u32 rx_stat_grjbr_lo; | |
2502 | u32 rx_stat_grjbr_hi; | |
2503 | u32 rx_stat_grovr_lo; | |
2504 | u32 rx_stat_grovr_hi; | |
2505 | u32 rx_stat_grxcf_lo; /* grcf */ | |
2506 | u32 rx_stat_grxcf_hi; /* grcf */ | |
2507 | u32 rx_stat_grflr_lo; | |
2508 | u32 rx_stat_grflr_hi; | |
2509 | u32 rx_stat_grpok_lo; | |
2510 | u32 rx_stat_grpok_hi; | |
2511 | u32 rx_stat_grmeg_lo; | |
2512 | u32 rx_stat_grmeg_hi; | |
2513 | u32 rx_stat_grmeb_lo; | |
2514 | u32 rx_stat_grmeb_hi; | |
2515 | u32 rx_stat_grbyt_lo; | |
2516 | u32 rx_stat_grbyt_hi; | |
2517 | u32 rx_stat_grund_lo; | |
2518 | u32 rx_stat_grund_hi; | |
2519 | u32 rx_stat_grfrg_lo; | |
2520 | u32 rx_stat_grfrg_hi; | |
2521 | u32 rx_stat_grerb_lo; /* grerrbyt */ | |
2522 | u32 rx_stat_grerb_hi; /* grerrbyt */ | |
2523 | u32 rx_stat_grfre_lo; /* grfrerr */ | |
2524 | u32 rx_stat_grfre_hi; /* grfrerr */ | |
2525 | u32 rx_stat_gripj_lo; | |
2526 | u32 rx_stat_gripj_hi; | |
2527 | }; | |
bb2a0f7a | 2528 | |
619c5cb6 VZ |
2529 | struct mstat_stats { |
2530 | struct { | |
2531 | /* OTE MSTAT on E3 has a bug where this register's contents are | |
2532 | * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp | |
2533 | */ | |
2534 | u32 tx_gtxpok_lo; | |
2535 | u32 tx_gtxpok_hi; | |
2536 | u32 tx_gtxpf_lo; | |
2537 | u32 tx_gtxpf_hi; | |
2538 | u32 tx_gtxpp_lo; | |
2539 | u32 tx_gtxpp_hi; | |
2540 | u32 tx_gtfcs_lo; | |
2541 | u32 tx_gtfcs_hi; | |
2542 | u32 tx_gtuca_lo; | |
2543 | u32 tx_gtuca_hi; | |
2544 | u32 tx_gtmca_lo; | |
2545 | u32 tx_gtmca_hi; | |
2546 | u32 tx_gtgca_lo; | |
2547 | u32 tx_gtgca_hi; | |
2548 | u32 tx_gtpkt_lo; | |
2549 | u32 tx_gtpkt_hi; | |
2550 | u32 tx_gt64_lo; | |
2551 | u32 tx_gt64_hi; | |
2552 | u32 tx_gt127_lo; | |
2553 | u32 tx_gt127_hi; | |
2554 | u32 tx_gt255_lo; | |
2555 | u32 tx_gt255_hi; | |
2556 | u32 tx_gt511_lo; | |
2557 | u32 tx_gt511_hi; | |
2558 | u32 tx_gt1023_lo; | |
2559 | u32 tx_gt1023_hi; | |
2560 | u32 tx_gt1518_lo; | |
2561 | u32 tx_gt1518_hi; | |
2562 | u32 tx_gt2047_lo; | |
2563 | u32 tx_gt2047_hi; | |
2564 | u32 tx_gt4095_lo; | |
2565 | u32 tx_gt4095_hi; | |
2566 | u32 tx_gt9216_lo; | |
2567 | u32 tx_gt9216_hi; | |
2568 | u32 tx_gt16383_lo; | |
2569 | u32 tx_gt16383_hi; | |
2570 | u32 tx_gtufl_lo; | |
2571 | u32 tx_gtufl_hi; | |
2572 | u32 tx_gterr_lo; | |
2573 | u32 tx_gterr_hi; | |
2574 | u32 tx_gtbyt_lo; | |
2575 | u32 tx_gtbyt_hi; | |
2576 | u32 tx_collisions_lo; | |
2577 | u32 tx_collisions_hi; | |
2578 | u32 tx_singlecollision_lo; | |
2579 | u32 tx_singlecollision_hi; | |
2580 | u32 tx_multiplecollisions_lo; | |
2581 | u32 tx_multiplecollisions_hi; | |
2582 | u32 tx_deferred_lo; | |
2583 | u32 tx_deferred_hi; | |
2584 | u32 tx_excessivecollisions_lo; | |
2585 | u32 tx_excessivecollisions_hi; | |
2586 | u32 tx_latecollisions_lo; | |
2587 | u32 tx_latecollisions_hi; | |
2588 | } stats_tx; | |
2589 | ||
2590 | struct { | |
2591 | u32 rx_gr64_lo; | |
2592 | u32 rx_gr64_hi; | |
2593 | u32 rx_gr127_lo; | |
2594 | u32 rx_gr127_hi; | |
2595 | u32 rx_gr255_lo; | |
2596 | u32 rx_gr255_hi; | |
2597 | u32 rx_gr511_lo; | |
2598 | u32 rx_gr511_hi; | |
2599 | u32 rx_gr1023_lo; | |
2600 | u32 rx_gr1023_hi; | |
2601 | u32 rx_gr1518_lo; | |
2602 | u32 rx_gr1518_hi; | |
2603 | u32 rx_gr2047_lo; | |
2604 | u32 rx_gr2047_hi; | |
2605 | u32 rx_gr4095_lo; | |
2606 | u32 rx_gr4095_hi; | |
2607 | u32 rx_gr9216_lo; | |
2608 | u32 rx_gr9216_hi; | |
2609 | u32 rx_gr16383_lo; | |
2610 | u32 rx_gr16383_hi; | |
2611 | u32 rx_grpkt_lo; | |
2612 | u32 rx_grpkt_hi; | |
2613 | u32 rx_grfcs_lo; | |
2614 | u32 rx_grfcs_hi; | |
2615 | u32 rx_gruca_lo; | |
2616 | u32 rx_gruca_hi; | |
2617 | u32 rx_grmca_lo; | |
2618 | u32 rx_grmca_hi; | |
2619 | u32 rx_grbca_lo; | |
2620 | u32 rx_grbca_hi; | |
2621 | u32 rx_grxpf_lo; | |
2622 | u32 rx_grxpf_hi; | |
2623 | u32 rx_grxpp_lo; | |
2624 | u32 rx_grxpp_hi; | |
2625 | u32 rx_grxuo_lo; | |
2626 | u32 rx_grxuo_hi; | |
2627 | u32 rx_grovr_lo; | |
2628 | u32 rx_grovr_hi; | |
2629 | u32 rx_grxcf_lo; | |
2630 | u32 rx_grxcf_hi; | |
2631 | u32 rx_grflr_lo; | |
2632 | u32 rx_grflr_hi; | |
2633 | u32 rx_grpok_lo; | |
2634 | u32 rx_grpok_hi; | |
2635 | u32 rx_grbyt_lo; | |
2636 | u32 rx_grbyt_hi; | |
2637 | u32 rx_grund_lo; | |
2638 | u32 rx_grund_hi; | |
2639 | u32 rx_grfrg_lo; | |
2640 | u32 rx_grfrg_hi; | |
2641 | u32 rx_grerb_lo; | |
2642 | u32 rx_grerb_hi; | |
2643 | u32 rx_grfre_lo; | |
2644 | u32 rx_grfre_hi; | |
2645 | ||
2646 | u32 rx_alignmenterrors_lo; | |
2647 | u32 rx_alignmenterrors_hi; | |
2648 | u32 rx_falsecarrier_lo; | |
2649 | u32 rx_falsecarrier_hi; | |
2650 | u32 rx_llfcmsgcnt_lo; | |
2651 | u32 rx_llfcmsgcnt_hi; | |
2652 | } stats_rx; | |
2653 | }; | |
2654 | ||
bb2a0f7a | 2655 | union mac_stats { |
619c5cb6 VZ |
2656 | struct emac_stats emac_stats; |
2657 | struct bmac1_stats bmac1_stats; | |
2658 | struct bmac2_stats bmac2_stats; | |
2659 | struct mstat_stats mstat_stats; | |
bb2a0f7a YG |
2660 | }; |
2661 | ||
2662 | ||
2663 | struct mac_stx { | |
619c5cb6 VZ |
2664 | /* in_bad_octets */ |
2665 | u32 rx_stat_ifhcinbadoctets_hi; | |
2666 | u32 rx_stat_ifhcinbadoctets_lo; | |
2667 | ||
2668 | /* out_bad_octets */ | |
2669 | u32 tx_stat_ifhcoutbadoctets_hi; | |
2670 | u32 tx_stat_ifhcoutbadoctets_lo; | |
2671 | ||
2672 | /* crc_receive_errors */ | |
2673 | u32 rx_stat_dot3statsfcserrors_hi; | |
2674 | u32 rx_stat_dot3statsfcserrors_lo; | |
2675 | /* alignment_errors */ | |
2676 | u32 rx_stat_dot3statsalignmenterrors_hi; | |
2677 | u32 rx_stat_dot3statsalignmenterrors_lo; | |
2678 | /* carrier_sense_errors */ | |
2679 | u32 rx_stat_dot3statscarriersenseerrors_hi; | |
2680 | u32 rx_stat_dot3statscarriersenseerrors_lo; | |
2681 | /* false_carrier_detections */ | |
2682 | u32 rx_stat_falsecarriererrors_hi; | |
2683 | u32 rx_stat_falsecarriererrors_lo; | |
2684 | ||
2685 | /* runt_packets_received */ | |
2686 | u32 rx_stat_etherstatsundersizepkts_hi; | |
2687 | u32 rx_stat_etherstatsundersizepkts_lo; | |
2688 | /* jabber_packets_received */ | |
2689 | u32 rx_stat_dot3statsframestoolong_hi; | |
2690 | u32 rx_stat_dot3statsframestoolong_lo; | |
2691 | ||
2692 | /* error_runt_packets_received */ | |
2693 | u32 rx_stat_etherstatsfragments_hi; | |
2694 | u32 rx_stat_etherstatsfragments_lo; | |
2695 | /* error_jabber_packets_received */ | |
2696 | u32 rx_stat_etherstatsjabbers_hi; | |
2697 | u32 rx_stat_etherstatsjabbers_lo; | |
2698 | ||
2699 | /* control_frames_received */ | |
2700 | u32 rx_stat_maccontrolframesreceived_hi; | |
2701 | u32 rx_stat_maccontrolframesreceived_lo; | |
2702 | u32 rx_stat_mac_xpf_hi; | |
2703 | u32 rx_stat_mac_xpf_lo; | |
2704 | u32 rx_stat_mac_xcf_hi; | |
2705 | u32 rx_stat_mac_xcf_lo; | |
2706 | ||
2707 | /* xoff_state_entered */ | |
2708 | u32 rx_stat_xoffstateentered_hi; | |
2709 | u32 rx_stat_xoffstateentered_lo; | |
2710 | /* pause_xon_frames_received */ | |
2711 | u32 rx_stat_xonpauseframesreceived_hi; | |
2712 | u32 rx_stat_xonpauseframesreceived_lo; | |
2713 | /* pause_xoff_frames_received */ | |
2714 | u32 rx_stat_xoffpauseframesreceived_hi; | |
2715 | u32 rx_stat_xoffpauseframesreceived_lo; | |
2716 | /* pause_xon_frames_transmitted */ | |
2717 | u32 tx_stat_outxonsent_hi; | |
2718 | u32 tx_stat_outxonsent_lo; | |
2719 | /* pause_xoff_frames_transmitted */ | |
2720 | u32 tx_stat_outxoffsent_hi; | |
2721 | u32 tx_stat_outxoffsent_lo; | |
2722 | /* flow_control_done */ | |
2723 | u32 tx_stat_flowcontroldone_hi; | |
2724 | u32 tx_stat_flowcontroldone_lo; | |
2725 | ||
2726 | /* ether_stats_collisions */ | |
2727 | u32 tx_stat_etherstatscollisions_hi; | |
2728 | u32 tx_stat_etherstatscollisions_lo; | |
2729 | /* single_collision_transmit_frames */ | |
2730 | u32 tx_stat_dot3statssinglecollisionframes_hi; | |
2731 | u32 tx_stat_dot3statssinglecollisionframes_lo; | |
2732 | /* multiple_collision_transmit_frames */ | |
2733 | u32 tx_stat_dot3statsmultiplecollisionframes_hi; | |
2734 | u32 tx_stat_dot3statsmultiplecollisionframes_lo; | |
2735 | /* deferred_transmissions */ | |
2736 | u32 tx_stat_dot3statsdeferredtransmissions_hi; | |
2737 | u32 tx_stat_dot3statsdeferredtransmissions_lo; | |
2738 | /* excessive_collision_frames */ | |
2739 | u32 tx_stat_dot3statsexcessivecollisions_hi; | |
2740 | u32 tx_stat_dot3statsexcessivecollisions_lo; | |
2741 | /* late_collision_frames */ | |
2742 | u32 tx_stat_dot3statslatecollisions_hi; | |
2743 | u32 tx_stat_dot3statslatecollisions_lo; | |
2744 | ||
2745 | /* frames_transmitted_64_bytes */ | |
2746 | u32 tx_stat_etherstatspkts64octets_hi; | |
2747 | u32 tx_stat_etherstatspkts64octets_lo; | |
2748 | /* frames_transmitted_65_127_bytes */ | |
2749 | u32 tx_stat_etherstatspkts65octetsto127octets_hi; | |
2750 | u32 tx_stat_etherstatspkts65octetsto127octets_lo; | |
2751 | /* frames_transmitted_128_255_bytes */ | |
2752 | u32 tx_stat_etherstatspkts128octetsto255octets_hi; | |
2753 | u32 tx_stat_etherstatspkts128octetsto255octets_lo; | |
2754 | /* frames_transmitted_256_511_bytes */ | |
2755 | u32 tx_stat_etherstatspkts256octetsto511octets_hi; | |
2756 | u32 tx_stat_etherstatspkts256octetsto511octets_lo; | |
2757 | /* frames_transmitted_512_1023_bytes */ | |
2758 | u32 tx_stat_etherstatspkts512octetsto1023octets_hi; | |
2759 | u32 tx_stat_etherstatspkts512octetsto1023octets_lo; | |
2760 | /* frames_transmitted_1024_1522_bytes */ | |
2761 | u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; | |
2762 | u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; | |
2763 | /* frames_transmitted_1523_9022_bytes */ | |
2764 | u32 tx_stat_etherstatspktsover1522octets_hi; | |
2765 | u32 tx_stat_etherstatspktsover1522octets_lo; | |
2766 | u32 tx_stat_mac_2047_hi; | |
2767 | u32 tx_stat_mac_2047_lo; | |
2768 | u32 tx_stat_mac_4095_hi; | |
2769 | u32 tx_stat_mac_4095_lo; | |
2770 | u32 tx_stat_mac_9216_hi; | |
2771 | u32 tx_stat_mac_9216_lo; | |
2772 | u32 tx_stat_mac_16383_hi; | |
2773 | u32 tx_stat_mac_16383_lo; | |
2774 | ||
2775 | /* internal_mac_transmit_errors */ | |
2776 | u32 tx_stat_dot3statsinternalmactransmiterrors_hi; | |
2777 | u32 tx_stat_dot3statsinternalmactransmiterrors_lo; | |
2778 | ||
2779 | /* if_out_discards */ | |
2780 | u32 tx_stat_mac_ufl_hi; | |
2781 | u32 tx_stat_mac_ufl_lo; | |
2782 | }; | |
2783 | ||
2784 | ||
2785 | #define MAC_STX_IDX_MAX 2 | |
bb2a0f7a YG |
2786 | |
2787 | struct host_port_stats { | |
0e898dd7 | 2788 | u32 host_port_stats_counter; |
bb2a0f7a | 2789 | |
619c5cb6 | 2790 | struct mac_stx mac_stx[MAC_STX_IDX_MAX]; |
bb2a0f7a | 2791 | |
619c5cb6 VZ |
2792 | u32 brb_drop_hi; |
2793 | u32 brb_drop_lo; | |
bb2a0f7a | 2794 | |
0e898dd7 BW |
2795 | u32 not_used; /* obsolete */ |
2796 | u32 pfc_frames_tx_hi; | |
2797 | u32 pfc_frames_tx_lo; | |
2798 | u32 pfc_frames_rx_hi; | |
2799 | u32 pfc_frames_rx_lo; | |
c8c60d88 YM |
2800 | |
2801 | u32 eee_lpi_count_hi; | |
2802 | u32 eee_lpi_count_lo; | |
bb2a0f7a YG |
2803 | }; |
2804 | ||
2805 | ||
2806 | struct host_func_stats { | |
619c5cb6 | 2807 | u32 host_func_stats_start; |
bb2a0f7a | 2808 | |
619c5cb6 VZ |
2809 | u32 total_bytes_received_hi; |
2810 | u32 total_bytes_received_lo; | |
bb2a0f7a | 2811 | |
619c5cb6 VZ |
2812 | u32 total_bytes_transmitted_hi; |
2813 | u32 total_bytes_transmitted_lo; | |
bb2a0f7a | 2814 | |
619c5cb6 VZ |
2815 | u32 total_unicast_packets_received_hi; |
2816 | u32 total_unicast_packets_received_lo; | |
bb2a0f7a | 2817 | |
619c5cb6 VZ |
2818 | u32 total_multicast_packets_received_hi; |
2819 | u32 total_multicast_packets_received_lo; | |
bb2a0f7a | 2820 | |
619c5cb6 VZ |
2821 | u32 total_broadcast_packets_received_hi; |
2822 | u32 total_broadcast_packets_received_lo; | |
bb2a0f7a | 2823 | |
619c5cb6 VZ |
2824 | u32 total_unicast_packets_transmitted_hi; |
2825 | u32 total_unicast_packets_transmitted_lo; | |
bb2a0f7a | 2826 | |
619c5cb6 VZ |
2827 | u32 total_multicast_packets_transmitted_hi; |
2828 | u32 total_multicast_packets_transmitted_lo; | |
bb2a0f7a | 2829 | |
619c5cb6 VZ |
2830 | u32 total_broadcast_packets_transmitted_hi; |
2831 | u32 total_broadcast_packets_transmitted_lo; | |
bb2a0f7a | 2832 | |
619c5cb6 VZ |
2833 | u32 valid_bytes_received_hi; |
2834 | u32 valid_bytes_received_lo; | |
bb2a0f7a | 2835 | |
619c5cb6 | 2836 | u32 host_func_stats_end; |
bb2a0f7a | 2837 | }; |
34f80b04 | 2838 | |
619c5cb6 VZ |
2839 | /* VIC definitions */ |
2840 | #define VICSTATST_UIF_INDEX 2 | |
34f80b04 | 2841 | |
a3348722 BW |
2842 | |
2843 | /* stats collected for afex. | |
2844 | * NOTE: structure is exactly as expected to be received by the switch. | |
2845 | * order must remain exactly as is unless protocol changes ! | |
2846 | */ | |
2847 | struct afex_stats { | |
2848 | u32 tx_unicast_frames_hi; | |
2849 | u32 tx_unicast_frames_lo; | |
2850 | u32 tx_unicast_bytes_hi; | |
2851 | u32 tx_unicast_bytes_lo; | |
2852 | u32 tx_multicast_frames_hi; | |
2853 | u32 tx_multicast_frames_lo; | |
2854 | u32 tx_multicast_bytes_hi; | |
2855 | u32 tx_multicast_bytes_lo; | |
2856 | u32 tx_broadcast_frames_hi; | |
2857 | u32 tx_broadcast_frames_lo; | |
2858 | u32 tx_broadcast_bytes_hi; | |
2859 | u32 tx_broadcast_bytes_lo; | |
2860 | u32 tx_frames_discarded_hi; | |
2861 | u32 tx_frames_discarded_lo; | |
2862 | u32 tx_frames_dropped_hi; | |
2863 | u32 tx_frames_dropped_lo; | |
2864 | ||
2865 | u32 rx_unicast_frames_hi; | |
2866 | u32 rx_unicast_frames_lo; | |
2867 | u32 rx_unicast_bytes_hi; | |
2868 | u32 rx_unicast_bytes_lo; | |
2869 | u32 rx_multicast_frames_hi; | |
2870 | u32 rx_multicast_frames_lo; | |
2871 | u32 rx_multicast_bytes_hi; | |
2872 | u32 rx_multicast_bytes_lo; | |
2873 | u32 rx_broadcast_frames_hi; | |
2874 | u32 rx_broadcast_frames_lo; | |
2875 | u32 rx_broadcast_bytes_hi; | |
2876 | u32 rx_broadcast_bytes_lo; | |
2877 | u32 rx_frames_discarded_hi; | |
2878 | u32 rx_frames_discarded_lo; | |
2879 | u32 rx_frames_dropped_hi; | |
2880 | u32 rx_frames_dropped_lo; | |
2881 | }; | |
2882 | ||
619c5cb6 | 2883 | #define BCM_5710_FW_MAJOR_VERSION 7 |
96bed4b9 | 2884 | #define BCM_5710_FW_MINOR_VERSION 8 |
3156b8eb | 2885 | #define BCM_5710_FW_REVISION_VERSION 19 |
91226790 | 2886 | #define BCM_5710_FW_ENGINEERING_VERSION 0 |
a2fbb9ea ET |
2887 | #define BCM_5710_FW_COMPILE_FLAGS 1 |
2888 | ||
2889 | ||
2890 | /* | |
2891 | * attention bits | |
2892 | */ | |
523224a3 | 2893 | struct atten_sp_status_block { |
4781bfad EG |
2894 | __le32 attn_bits; |
2895 | __le32 attn_bits_ack; | |
a2fbb9ea ET |
2896 | u8 status_block_id; |
2897 | u8 reserved0; | |
4781bfad EG |
2898 | __le16 attn_bits_index; |
2899 | __le32 reserved1; | |
a2fbb9ea ET |
2900 | }; |
2901 | ||
2902 | ||
2903 | /* | |
619c5cb6 | 2904 | * The eth aggregative context of Cstorm |
a2fbb9ea | 2905 | */ |
619c5cb6 VZ |
2906 | struct cstorm_eth_ag_context { |
2907 | u32 __reserved0[10]; | |
a2fbb9ea ET |
2908 | }; |
2909 | ||
619c5cb6 | 2910 | |
a2fbb9ea | 2911 | /* |
619c5cb6 | 2912 | * dmae command structure |
a2fbb9ea | 2913 | */ |
619c5cb6 VZ |
2914 | struct dmae_command { |
2915 | u32 opcode; | |
2916 | #define DMAE_COMMAND_SRC (0x1<<0) | |
2917 | #define DMAE_COMMAND_SRC_SHIFT 0 | |
2918 | #define DMAE_COMMAND_DST (0x3<<1) | |
2919 | #define DMAE_COMMAND_DST_SHIFT 1 | |
2920 | #define DMAE_COMMAND_C_DST (0x1<<3) | |
2921 | #define DMAE_COMMAND_C_DST_SHIFT 3 | |
2922 | #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) | |
2923 | #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 | |
2924 | #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) | |
2925 | #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 | |
2926 | #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) | |
2927 | #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 | |
2928 | #define DMAE_COMMAND_ENDIANITY (0x3<<9) | |
2929 | #define DMAE_COMMAND_ENDIANITY_SHIFT 9 | |
2930 | #define DMAE_COMMAND_PORT (0x1<<11) | |
2931 | #define DMAE_COMMAND_PORT_SHIFT 11 | |
2932 | #define DMAE_COMMAND_CRC_RESET (0x1<<12) | |
2933 | #define DMAE_COMMAND_CRC_RESET_SHIFT 12 | |
2934 | #define DMAE_COMMAND_SRC_RESET (0x1<<13) | |
2935 | #define DMAE_COMMAND_SRC_RESET_SHIFT 13 | |
2936 | #define DMAE_COMMAND_DST_RESET (0x1<<14) | |
2937 | #define DMAE_COMMAND_DST_RESET_SHIFT 14 | |
2938 | #define DMAE_COMMAND_E1HVN (0x3<<15) | |
2939 | #define DMAE_COMMAND_E1HVN_SHIFT 15 | |
2940 | #define DMAE_COMMAND_DST_VN (0x3<<17) | |
2941 | #define DMAE_COMMAND_DST_VN_SHIFT 17 | |
2942 | #define DMAE_COMMAND_C_FUNC (0x1<<19) | |
2943 | #define DMAE_COMMAND_C_FUNC_SHIFT 19 | |
2944 | #define DMAE_COMMAND_ERR_POLICY (0x3<<20) | |
2945 | #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 | |
2946 | #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) | |
2947 | #define DMAE_COMMAND_RESERVED0_SHIFT 22 | |
2948 | u32 src_addr_lo; | |
2949 | u32 src_addr_hi; | |
2950 | u32 dst_addr_lo; | |
2951 | u32 dst_addr_hi; | |
a2fbb9ea | 2952 | #if defined(__BIG_ENDIAN) |
619c5cb6 VZ |
2953 | u16 opcode_iov; |
2954 | #define DMAE_COMMAND_SRC_VFID (0x3F<<0) | |
2955 | #define DMAE_COMMAND_SRC_VFID_SHIFT 0 | |
2956 | #define DMAE_COMMAND_SRC_VFPF (0x1<<6) | |
2957 | #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 | |
2958 | #define DMAE_COMMAND_RESERVED1 (0x1<<7) | |
2959 | #define DMAE_COMMAND_RESERVED1_SHIFT 7 | |
2960 | #define DMAE_COMMAND_DST_VFID (0x3F<<8) | |
2961 | #define DMAE_COMMAND_DST_VFID_SHIFT 8 | |
2962 | #define DMAE_COMMAND_DST_VFPF (0x1<<14) | |
2963 | #define DMAE_COMMAND_DST_VFPF_SHIFT 14 | |
2964 | #define DMAE_COMMAND_RESERVED2 (0x1<<15) | |
2965 | #define DMAE_COMMAND_RESERVED2_SHIFT 15 | |
2966 | u16 len; | |
a2fbb9ea | 2967 | #elif defined(__LITTLE_ENDIAN) |
619c5cb6 VZ |
2968 | u16 len; |
2969 | u16 opcode_iov; | |
2970 | #define DMAE_COMMAND_SRC_VFID (0x3F<<0) | |
2971 | #define DMAE_COMMAND_SRC_VFID_SHIFT 0 | |
2972 | #define DMAE_COMMAND_SRC_VFPF (0x1<<6) | |
2973 | #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 | |
2974 | #define DMAE_COMMAND_RESERVED1 (0x1<<7) | |
2975 | #define DMAE_COMMAND_RESERVED1_SHIFT 7 | |
2976 | #define DMAE_COMMAND_DST_VFID (0x3F<<8) | |
2977 | #define DMAE_COMMAND_DST_VFID_SHIFT 8 | |
2978 | #define DMAE_COMMAND_DST_VFPF (0x1<<14) | |
2979 | #define DMAE_COMMAND_DST_VFPF_SHIFT 14 | |
2980 | #define DMAE_COMMAND_RESERVED2 (0x1<<15) | |
2981 | #define DMAE_COMMAND_RESERVED2_SHIFT 15 | |
a2fbb9ea | 2982 | #endif |
619c5cb6 VZ |
2983 | u32 comp_addr_lo; |
2984 | u32 comp_addr_hi; | |
2985 | u32 comp_val; | |
2986 | u32 crc32; | |
2987 | u32 crc32_c; | |
2988 | #if defined(__BIG_ENDIAN) | |
2989 | u16 crc16_c; | |
2990 | u16 crc16; | |
2991 | #elif defined(__LITTLE_ENDIAN) | |
2992 | u16 crc16; | |
2993 | u16 crc16_c; | |
2994 | #endif | |
2995 | #if defined(__BIG_ENDIAN) | |
2996 | u16 reserved3; | |
2997 | u16 crc_t10; | |
2998 | #elif defined(__LITTLE_ENDIAN) | |
2999 | u16 crc_t10; | |
3000 | u16 reserved3; | |
3001 | #endif | |
3002 | #if defined(__BIG_ENDIAN) | |
3003 | u16 xsum8; | |
3004 | u16 xsum16; | |
3005 | #elif defined(__LITTLE_ENDIAN) | |
3006 | u16 xsum16; | |
3007 | u16 xsum8; | |
3008 | #endif | |
3009 | }; | |
3010 | ||
3011 | ||
ca00392c | 3012 | /* |
619c5cb6 | 3013 | * common data for all protocols |
ca00392c | 3014 | */ |
619c5cb6 VZ |
3015 | struct doorbell_hdr { |
3016 | u8 header; | |
3017 | #define DOORBELL_HDR_RX (0x1<<0) | |
3018 | #define DOORBELL_HDR_RX_SHIFT 0 | |
3019 | #define DOORBELL_HDR_DB_TYPE (0x1<<1) | |
3020 | #define DOORBELL_HDR_DB_TYPE_SHIFT 1 | |
3021 | #define DOORBELL_HDR_DPM_SIZE (0x3<<2) | |
3022 | #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 | |
3023 | #define DOORBELL_HDR_CONN_TYPE (0xF<<4) | |
3024 | #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 | |
3025 | }; | |
3026 | ||
3027 | /* | |
3028 | * Ethernet doorbell | |
3029 | */ | |
3030 | struct eth_tx_doorbell { | |
ca00392c | 3031 | #if defined(__BIG_ENDIAN) |
619c5cb6 VZ |
3032 | u16 npackets; |
3033 | u8 params; | |
3034 | #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) | |
3035 | #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 | |
3036 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) | |
3037 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 | |
3038 | #define ETH_TX_DOORBELL_SPARE (0x1<<7) | |
3039 | #define ETH_TX_DOORBELL_SPARE_SHIFT 7 | |
3040 | struct doorbell_hdr hdr; | |
ca00392c | 3041 | #elif defined(__LITTLE_ENDIAN) |
619c5cb6 VZ |
3042 | struct doorbell_hdr hdr; |
3043 | u8 params; | |
3044 | #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) | |
3045 | #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 | |
3046 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) | |
3047 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 | |
3048 | #define ETH_TX_DOORBELL_SPARE (0x1<<7) | |
3049 | #define ETH_TX_DOORBELL_SPARE_SHIFT 7 | |
3050 | u16 npackets; | |
ca00392c EG |
3051 | #endif |
3052 | }; | |
3053 | ||
3054 | ||
a2fbb9ea | 3055 | /* |
523224a3 DK |
3056 | * 3 lines. status block |
3057 | */ | |
3058 | struct hc_status_block_e1x { | |
3059 | __le16 index_values[HC_SB_MAX_INDICES_E1X]; | |
3060 | __le16 running_index[HC_SB_MAX_SM]; | |
619c5cb6 | 3061 | __le32 rsrv[11]; |
523224a3 DK |
3062 | }; |
3063 | ||
3064 | /* | |
3065 | * host status block | |
3066 | */ | |
3067 | struct host_hc_status_block_e1x { | |
3068 | struct hc_status_block_e1x sb; | |
3069 | }; | |
3070 | ||
3071 | ||
3072 | /* | |
3073 | * 3 lines. status block | |
3074 | */ | |
3075 | struct hc_status_block_e2 { | |
3076 | __le16 index_values[HC_SB_MAX_INDICES_E2]; | |
3077 | __le16 running_index[HC_SB_MAX_SM]; | |
619c5cb6 | 3078 | __le32 reserved[11]; |
523224a3 DK |
3079 | }; |
3080 | ||
3081 | /* | |
3082 | * host status block | |
3083 | */ | |
3084 | struct host_hc_status_block_e2 { | |
3085 | struct hc_status_block_e2 sb; | |
3086 | }; | |
3087 | ||
3088 | ||
3089 | /* | |
3090 | * 5 lines. slow-path status block | |
3091 | */ | |
3092 | struct hc_sp_status_block { | |
3093 | __le16 index_values[HC_SP_SB_MAX_INDICES]; | |
3094 | __le16 running_index; | |
3095 | __le16 rsrv; | |
3096 | u32 rsrv1; | |
3097 | }; | |
3098 | ||
3099 | /* | |
3100 | * host status block | |
3101 | */ | |
3102 | struct host_sp_status_block { | |
3103 | struct atten_sp_status_block atten_status_block; | |
3104 | struct hc_sp_status_block sp_sb; | |
3105 | }; | |
3106 | ||
3107 | ||
3108 | /* | |
3109 | * IGU driver acknowledgment register | |
a2fbb9ea ET |
3110 | */ |
3111 | struct igu_ack_register { | |
3112 | #if defined(__BIG_ENDIAN) | |
3113 | u16 sb_id_and_flags; | |
3114 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) | |
3115 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 | |
3116 | #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) | |
3117 | #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 | |
3118 | #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) | |
3119 | #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 | |
3120 | #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) | |
3121 | #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 | |
3122 | #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) | |
3123 | #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 | |
3124 | u16 status_block_index; | |
3125 | #elif defined(__LITTLE_ENDIAN) | |
3126 | u16 status_block_index; | |
3127 | u16 sb_id_and_flags; | |
3128 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) | |
3129 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 | |
3130 | #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) | |
3131 | #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 | |
3132 | #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) | |
3133 | #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 | |
3134 | #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) | |
3135 | #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 | |
3136 | #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) | |
3137 | #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 | |
3138 | #endif | |
3139 | }; | |
3140 | ||
3141 | ||
ca00392c EG |
3142 | /* |
3143 | * IGU driver acknowledgement register | |
3144 | */ | |
3145 | struct igu_backward_compatible { | |
3146 | u32 sb_id_and_flags; | |
3147 | #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) | |
3148 | #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 | |
3149 | #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) | |
3150 | #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 | |
3151 | #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) | |
3152 | #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 | |
3153 | #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) | |
3154 | #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 | |
3155 | #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) | |
3156 | #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 | |
3157 | #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) | |
3158 | #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 | |
3159 | u32 reserved_2; | |
3160 | }; | |
3161 | ||
3162 | ||
3163 | /* | |
3164 | * IGU driver acknowledgement register | |
3165 | */ | |
3166 | struct igu_regular { | |
3167 | u32 sb_id_and_flags; | |
3168 | #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) | |
3169 | #define IGU_REGULAR_SB_INDEX_SHIFT 0 | |
3170 | #define IGU_REGULAR_RESERVED0 (0x1<<20) | |
3171 | #define IGU_REGULAR_RESERVED0_SHIFT 20 | |
3172 | #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) | |
3173 | #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 | |
3174 | #define IGU_REGULAR_BUPDATE (0x1<<24) | |
3175 | #define IGU_REGULAR_BUPDATE_SHIFT 24 | |
3176 | #define IGU_REGULAR_ENABLE_INT (0x3<<25) | |
3177 | #define IGU_REGULAR_ENABLE_INT_SHIFT 25 | |
3178 | #define IGU_REGULAR_RESERVED_1 (0x1<<27) | |
3179 | #define IGU_REGULAR_RESERVED_1_SHIFT 27 | |
3180 | #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) | |
3181 | #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 | |
3182 | #define IGU_REGULAR_CLEANUP_SET (0x1<<30) | |
3183 | #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 | |
3184 | #define IGU_REGULAR_BCLEANUP (0x1<<31) | |
3185 | #define IGU_REGULAR_BCLEANUP_SHIFT 31 | |
3186 | u32 reserved_2; | |
3187 | }; | |
3188 | ||
3189 | /* | |
3190 | * IGU driver acknowledgement register | |
3191 | */ | |
3192 | union igu_consprod_reg { | |
3193 | struct igu_regular regular; | |
3194 | struct igu_backward_compatible backward_compatible; | |
3195 | }; | |
3196 | ||
3197 | ||
619c5cb6 VZ |
3198 | /* |
3199 | * Igu control commands | |
3200 | */ | |
3201 | enum igu_ctrl_cmd { | |
3202 | IGU_CTRL_CMD_TYPE_RD, | |
3203 | IGU_CTRL_CMD_TYPE_WR, | |
3204 | MAX_IGU_CTRL_CMD | |
3205 | }; | |
3206 | ||
3207 | ||
f2e0899f DK |
3208 | /* |
3209 | * Control register for the IGU command register | |
3210 | */ | |
3211 | struct igu_ctrl_reg { | |
3212 | u32 ctrl_data; | |
3213 | #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) | |
3214 | #define IGU_CTRL_REG_ADDRESS_SHIFT 0 | |
3215 | #define IGU_CTRL_REG_FID (0x7F<<12) | |
3216 | #define IGU_CTRL_REG_FID_SHIFT 12 | |
3217 | #define IGU_CTRL_REG_RESERVED (0x1<<19) | |
3218 | #define IGU_CTRL_REG_RESERVED_SHIFT 19 | |
3219 | #define IGU_CTRL_REG_TYPE (0x1<<20) | |
3220 | #define IGU_CTRL_REG_TYPE_SHIFT 20 | |
3221 | #define IGU_CTRL_REG_UNUSED (0x7FF<<21) | |
3222 | #define IGU_CTRL_REG_UNUSED_SHIFT 21 | |
3223 | }; | |
3224 | ||
3225 | ||
619c5cb6 VZ |
3226 | /* |
3227 | * Igu interrupt command | |
3228 | */ | |
3229 | enum igu_int_cmd { | |
3230 | IGU_INT_ENABLE, | |
3231 | IGU_INT_DISABLE, | |
3232 | IGU_INT_NOP, | |
3233 | IGU_INT_NOP2, | |
3234 | MAX_IGU_INT_CMD | |
3235 | }; | |
3236 | ||
3237 | ||
3238 | /* | |
3239 | * Igu segments | |
3240 | */ | |
3241 | enum igu_seg_access { | |
3242 | IGU_SEG_ACCESS_NORM, | |
3243 | IGU_SEG_ACCESS_DEF, | |
3244 | IGU_SEG_ACCESS_ATTN, | |
3245 | MAX_IGU_SEG_ACCESS | |
3246 | }; | |
3247 | ||
3248 | ||
a2fbb9ea ET |
3249 | /* |
3250 | * Parser parsing flags field | |
3251 | */ | |
3252 | struct parsing_flags { | |
4781bfad | 3253 | __le16 flags; |
a2fbb9ea ET |
3254 | #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) |
3255 | #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 | |
34f80b04 EG |
3256 | #define PARSING_FLAGS_VLAN (0x1<<1) |
3257 | #define PARSING_FLAGS_VLAN_SHIFT 1 | |
3258 | #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) | |
3259 | #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 | |
a2fbb9ea ET |
3260 | #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) |
3261 | #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 | |
3262 | #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) | |
3263 | #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 | |
3264 | #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) | |
3265 | #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 | |
3266 | #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) | |
3267 | #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 | |
3268 | #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) | |
3269 | #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 | |
3270 | #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) | |
3271 | #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 | |
3272 | #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) | |
3273 | #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 | |
3274 | #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) | |
3275 | #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 | |
3276 | #define PARSING_FLAGS_LLC_SNAP (0x1<<13) | |
3277 | #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 | |
3278 | #define PARSING_FLAGS_RESERVED0 (0x3<<14) | |
3279 | #define PARSING_FLAGS_RESERVED0_SHIFT 14 | |
3280 | }; | |
3281 | ||
3282 | ||
619c5cb6 VZ |
3283 | /* |
3284 | * Parsing flags for TCP ACK type | |
3285 | */ | |
3286 | enum prs_flags_ack_type { | |
3287 | PRS_FLAG_PUREACK_PIGGY, | |
3288 | PRS_FLAG_PUREACK_PURE, | |
3289 | MAX_PRS_FLAGS_ACK_TYPE | |
34f80b04 EG |
3290 | }; |
3291 | ||
3292 | ||
a2fbb9ea | 3293 | /* |
619c5cb6 | 3294 | * Parsing flags for Ethernet address type |
a2fbb9ea | 3295 | */ |
619c5cb6 VZ |
3296 | enum prs_flags_eth_addr_type { |
3297 | PRS_FLAG_ETHTYPE_NON_UNICAST, | |
3298 | PRS_FLAG_ETHTYPE_UNICAST, | |
3299 | MAX_PRS_FLAGS_ETH_ADDR_TYPE | |
a2fbb9ea ET |
3300 | }; |
3301 | ||
3302 | ||
619c5cb6 VZ |
3303 | /* |
3304 | * Parsing flags for over-ethernet protocol | |
3305 | */ | |
3306 | enum prs_flags_over_eth { | |
3307 | PRS_FLAG_OVERETH_UNKNOWN, | |
3308 | PRS_FLAG_OVERETH_IPV4, | |
3309 | PRS_FLAG_OVERETH_IPV6, | |
3310 | PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, | |
3311 | MAX_PRS_FLAGS_OVER_ETH | |
3312 | }; | |
3313 | ||
3314 | ||
3315 | /* | |
3316 | * Parsing flags for over-IP protocol | |
3317 | */ | |
3318 | enum prs_flags_over_ip { | |
3319 | PRS_FLAG_OVERIP_UNKNOWN, | |
3320 | PRS_FLAG_OVERIP_TCP, | |
3321 | PRS_FLAG_OVERIP_UDP, | |
3322 | MAX_PRS_FLAGS_OVER_IP | |
a2fbb9ea ET |
3323 | }; |
3324 | ||
3325 | ||
3326 | /* | |
523224a3 | 3327 | * SDM operation gen command (generate aggregative interrupt) |
a2fbb9ea | 3328 | */ |
523224a3 DK |
3329 | struct sdm_op_gen { |
3330 | __le32 command; | |
3331 | #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) | |
3332 | #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 | |
3333 | #define SDM_OP_GEN_COMP_TYPE (0x7<<5) | |
3334 | #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 | |
3335 | #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) | |
3336 | #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 | |
3337 | #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) | |
3338 | #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 | |
3339 | #define SDM_OP_GEN_RESERVED (0x7FFF<<17) | |
3340 | #define SDM_OP_GEN_RESERVED_SHIFT 17 | |
34f80b04 EG |
3341 | }; |
3342 | ||
34f80b04 EG |
3343 | |
3344 | /* | |
619c5cb6 | 3345 | * Timers connection context |
34f80b04 | 3346 | */ |
619c5cb6 VZ |
3347 | struct timers_block_context { |
3348 | u32 __reserved_0; | |
3349 | u32 __reserved_1; | |
3350 | u32 __reserved_2; | |
3351 | u32 flags; | |
3352 | #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) | |
3353 | #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 | |
3354 | #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) | |
3355 | #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 | |
3356 | #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) | |
3357 | #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 | |
34f80b04 EG |
3358 | }; |
3359 | ||
523224a3 | 3360 | |
34f80b04 | 3361 | /* |
619c5cb6 | 3362 | * The eth aggregative context of Tstorm |
34f80b04 | 3363 | */ |
619c5cb6 VZ |
3364 | struct tstorm_eth_ag_context { |
3365 | u32 __reserved0[14]; | |
a2fbb9ea ET |
3366 | }; |
3367 | ||
619c5cb6 | 3368 | |
a2fbb9ea | 3369 | /* |
619c5cb6 | 3370 | * The eth aggregative context of Ustorm |
a2fbb9ea | 3371 | */ |
619c5cb6 VZ |
3372 | struct ustorm_eth_ag_context { |
3373 | u32 __reserved0; | |
3374 | #if defined(__BIG_ENDIAN) | |
3375 | u8 cdu_usage; | |
3376 | u8 __reserved2; | |
3377 | u16 __reserved1; | |
3378 | #elif defined(__LITTLE_ENDIAN) | |
3379 | u16 __reserved1; | |
3380 | u8 __reserved2; | |
3381 | u8 cdu_usage; | |
3382 | #endif | |
3383 | u32 __reserved3[6]; | |
a2fbb9ea ET |
3384 | }; |
3385 | ||
619c5cb6 | 3386 | |
a2fbb9ea ET |
3387 | /* |
3388 | * The eth aggregative context of Xstorm | |
3389 | */ | |
3390 | struct xstorm_eth_ag_context { | |
523224a3 | 3391 | u32 reserved0; |
a2fbb9ea ET |
3392 | #if defined(__BIG_ENDIAN) |
3393 | u8 cdu_reserved; | |
523224a3 DK |
3394 | u8 reserved2; |
3395 | u16 reserved1; | |
a2fbb9ea | 3396 | #elif defined(__LITTLE_ENDIAN) |
523224a3 DK |
3397 | u16 reserved1; |
3398 | u8 reserved2; | |
a2fbb9ea ET |
3399 | u8 cdu_reserved; |
3400 | #endif | |
523224a3 | 3401 | u32 reserved3[30]; |
a2fbb9ea ET |
3402 | }; |
3403 | ||
523224a3 | 3404 | |
a2fbb9ea | 3405 | /* |
619c5cb6 | 3406 | * doorbell message sent to the chip |
a2fbb9ea | 3407 | */ |
619c5cb6 VZ |
3408 | struct doorbell { |
3409 | #if defined(__BIG_ENDIAN) | |
3410 | u16 zero_fill2; | |
3411 | u8 zero_fill1; | |
3412 | struct doorbell_hdr header; | |
3413 | #elif defined(__LITTLE_ENDIAN) | |
3414 | struct doorbell_hdr header; | |
3415 | u8 zero_fill1; | |
3416 | u16 zero_fill2; | |
3417 | #endif | |
a2fbb9ea ET |
3418 | }; |
3419 | ||
523224a3 | 3420 | |
a2fbb9ea | 3421 | /* |
619c5cb6 | 3422 | * doorbell message sent to the chip |
a2fbb9ea | 3423 | */ |
619c5cb6 | 3424 | struct doorbell_set_prod { |
a2fbb9ea | 3425 | #if defined(__BIG_ENDIAN) |
619c5cb6 VZ |
3426 | u16 prod; |
3427 | u8 zero_fill1; | |
3428 | struct doorbell_hdr header; | |
a2fbb9ea | 3429 | #elif defined(__LITTLE_ENDIAN) |
619c5cb6 VZ |
3430 | struct doorbell_hdr header; |
3431 | u8 zero_fill1; | |
3432 | u16 prod; | |
a2fbb9ea | 3433 | #endif |
a2fbb9ea ET |
3434 | }; |
3435 | ||
619c5cb6 VZ |
3436 | |
3437 | struct regpair { | |
3438 | __le32 lo; | |
3439 | __le32 hi; | |
3440 | }; | |
3441 | ||
86564c3f YM |
3442 | struct regpair_native { |
3443 | u32 lo; | |
3444 | u32 hi; | |
3445 | }; | |
619c5cb6 | 3446 | |
a2fbb9ea | 3447 | /* |
619c5cb6 | 3448 | * Classify rule opcodes in E2/E3 |
a2fbb9ea | 3449 | */ |
619c5cb6 VZ |
3450 | enum classify_rule { |
3451 | CLASSIFY_RULE_OPCODE_MAC, | |
3452 | CLASSIFY_RULE_OPCODE_VLAN, | |
3453 | CLASSIFY_RULE_OPCODE_PAIR, | |
3454 | MAX_CLASSIFY_RULE | |
a2fbb9ea ET |
3455 | }; |
3456 | ||
619c5cb6 | 3457 | |
a2fbb9ea | 3458 | /* |
619c5cb6 | 3459 | * Classify rule types in E2/E3 |
a2fbb9ea | 3460 | */ |
619c5cb6 VZ |
3461 | enum classify_rule_action_type { |
3462 | CLASSIFY_RULE_REMOVE, | |
3463 | CLASSIFY_RULE_ADD, | |
3464 | MAX_CLASSIFY_RULE_ACTION_TYPE | |
a2fbb9ea ET |
3465 | }; |
3466 | ||
619c5cb6 | 3467 | |
a2fbb9ea | 3468 | /* |
619c5cb6 | 3469 | * client init ramrod data |
a2fbb9ea | 3470 | */ |
619c5cb6 VZ |
3471 | struct client_init_general_data { |
3472 | u8 client_id; | |
3473 | u8 statistics_counter_id; | |
3474 | u8 statistics_en_flg; | |
3475 | u8 is_fcoe_flg; | |
3476 | u8 activate_flg; | |
3477 | u8 sp_client_id; | |
3478 | __le16 mtu; | |
3479 | u8 statistics_zero_flg; | |
3480 | u8 func_id; | |
3481 | u8 cos; | |
3482 | u8 traffic_type; | |
3483 | u32 reserved0; | |
ca00392c EG |
3484 | }; |
3485 | ||
619c5cb6 | 3486 | |
ca00392c | 3487 | /* |
619c5cb6 | 3488 | * client init rx data |
ca00392c | 3489 | */ |
619c5cb6 VZ |
3490 | struct client_init_rx_data { |
3491 | u8 tpa_en; | |
3492 | #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) | |
3493 | #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 | |
3494 | #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) | |
3495 | #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 | |
621b4d66 DK |
3496 | #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) |
3497 | #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 | |
3498 | #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) | |
3499 | #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 | |
619c5cb6 VZ |
3500 | u8 vmqueue_mode_en_flg; |
3501 | u8 extra_data_over_sgl_en_flg; | |
3502 | u8 cache_line_alignment_log_size; | |
3503 | u8 enable_dynamic_hc; | |
3504 | u8 max_sges_for_packet; | |
3505 | u8 client_qzone_id; | |
3506 | u8 drop_ip_cs_err_flg; | |
3507 | u8 drop_tcp_cs_err_flg; | |
3508 | u8 drop_ttl0_flg; | |
3509 | u8 drop_udp_cs_err_flg; | |
3510 | u8 inner_vlan_removal_enable_flg; | |
3511 | u8 outer_vlan_removal_enable_flg; | |
3512 | u8 status_block_id; | |
3513 | u8 rx_sb_index_number; | |
621b4d66 | 3514 | u8 dont_verify_rings_pause_thr_flg; |
619c5cb6 VZ |
3515 | u8 max_tpa_queues; |
3516 | u8 silent_vlan_removal_flg; | |
3517 | __le16 max_bytes_on_bd; | |
3518 | __le16 sge_buff_size; | |
3519 | u8 approx_mcast_engine_id; | |
3520 | u8 rss_engine_id; | |
3521 | struct regpair bd_page_base; | |
3522 | struct regpair sge_page_base; | |
3523 | struct regpair cqe_page_base; | |
3524 | u8 is_leading_rss; | |
3525 | u8 is_approx_mcast; | |
3526 | __le16 max_agg_size; | |
3527 | __le16 state; | |
3528 | #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) | |
3529 | #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 | |
3530 | #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) | |
3531 | #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 | |
3532 | #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) | |
3533 | #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 | |
3534 | #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) | |
3535 | #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 | |
3536 | #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) | |
3537 | #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 | |
3538 | #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) | |
3539 | #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 | |
3540 | #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) | |
3541 | #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 | |
3542 | #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) | |
3543 | #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 | |
3544 | __le16 cqe_pause_thr_low; | |
3545 | __le16 cqe_pause_thr_high; | |
3546 | __le16 bd_pause_thr_low; | |
3547 | __le16 bd_pause_thr_high; | |
3548 | __le16 sge_pause_thr_low; | |
3549 | __le16 sge_pause_thr_high; | |
3550 | __le16 rx_cos_mask; | |
3551 | __le16 silent_vlan_value; | |
3552 | __le16 silent_vlan_mask; | |
3553 | __le32 reserved6[2]; | |
a2fbb9ea ET |
3554 | }; |
3555 | ||
3556 | /* | |
619c5cb6 | 3557 | * client init tx data |
a2fbb9ea | 3558 | */ |
619c5cb6 VZ |
3559 | struct client_init_tx_data { |
3560 | u8 enforce_security_flg; | |
3561 | u8 tx_status_block_id; | |
3562 | u8 tx_sb_index_number; | |
3563 | u8 tss_leading_client_id; | |
3564 | u8 tx_switching_flg; | |
3565 | u8 anti_spoofing_flg; | |
3566 | __le16 default_vlan; | |
3567 | struct regpair tx_bd_page_base; | |
3568 | __le16 state; | |
3569 | #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) | |
3570 | #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 | |
3571 | #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) | |
3572 | #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 | |
3573 | #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) | |
3574 | #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 | |
3575 | #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) | |
3576 | #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 | |
91226790 DK |
3577 | #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) |
3578 | #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 | |
619c5cb6 | 3579 | u8 default_vlan_flg; |
a3348722 | 3580 | u8 force_default_pri_flg; |
91226790 DK |
3581 | u8 tunnel_lso_inc_ip_id; |
3582 | u8 refuse_outband_vlan_flg; | |
3583 | u8 tunnel_non_lso_pcsum_location; | |
3584 | u8 reserved1; | |
a2fbb9ea ET |
3585 | }; |
3586 | ||
f2e0899f | 3587 | /* |
619c5cb6 | 3588 | * client init ramrod data |
f2e0899f | 3589 | */ |
619c5cb6 VZ |
3590 | struct client_init_ramrod_data { |
3591 | struct client_init_general_data general; | |
3592 | struct client_init_rx_data rx; | |
3593 | struct client_init_tx_data tx; | |
f2e0899f DK |
3594 | }; |
3595 | ||
619c5cb6 | 3596 | |
a2fbb9ea | 3597 | /* |
619c5cb6 | 3598 | * client update ramrod data |
a2fbb9ea | 3599 | */ |
619c5cb6 VZ |
3600 | struct client_update_ramrod_data { |
3601 | u8 client_id; | |
3602 | u8 func_id; | |
3603 | u8 inner_vlan_removal_enable_flg; | |
3604 | u8 inner_vlan_removal_change_flg; | |
3605 | u8 outer_vlan_removal_enable_flg; | |
3606 | u8 outer_vlan_removal_change_flg; | |
3607 | u8 anti_spoofing_enable_flg; | |
3608 | u8 anti_spoofing_change_flg; | |
3609 | u8 activate_flg; | |
3610 | u8 activate_change_flg; | |
3611 | __le16 default_vlan; | |
3612 | u8 default_vlan_enable_flg; | |
3613 | u8 default_vlan_change_flg; | |
3614 | __le16 silent_vlan_value; | |
3615 | __le16 silent_vlan_mask; | |
3616 | u8 silent_vlan_removal_flg; | |
3617 | u8 silent_vlan_change_flg; | |
91226790 DK |
3618 | u8 refuse_outband_vlan_flg; |
3619 | u8 refuse_outband_vlan_change_flg; | |
3620 | u8 tx_switching_flg; | |
3621 | u8 tx_switching_change_flg; | |
3622 | __le32 reserved1; | |
619c5cb6 | 3623 | __le32 echo; |
a2fbb9ea ET |
3624 | }; |
3625 | ||
619c5cb6 | 3626 | |
a2fbb9ea | 3627 | /* |
619c5cb6 | 3628 | * The eth storm context of Cstorm |
a2fbb9ea | 3629 | */ |
619c5cb6 VZ |
3630 | struct cstorm_eth_st_context { |
3631 | u32 __reserved0[4]; | |
3632 | }; | |
3633 | ||
3634 | ||
3635 | struct double_regpair { | |
3636 | u32 regpair0_lo; | |
3637 | u32 regpair0_hi; | |
3638 | u32 regpair1_lo; | |
3639 | u32 regpair1_hi; | |
a2fbb9ea ET |
3640 | }; |
3641 | ||
523224a3 | 3642 | |
a2fbb9ea | 3643 | /* |
619c5cb6 | 3644 | * Ethernet address typesm used in ethernet tx BDs |
a2fbb9ea | 3645 | */ |
619c5cb6 VZ |
3646 | enum eth_addr_type { |
3647 | UNKNOWN_ADDRESS, | |
3648 | UNICAST_ADDRESS, | |
3649 | MULTICAST_ADDRESS, | |
3650 | BROADCAST_ADDRESS, | |
3651 | MAX_ETH_ADDR_TYPE | |
a2fbb9ea ET |
3652 | }; |
3653 | ||
619c5cb6 | 3654 | |
a2fbb9ea | 3655 | /* |
619c5cb6 | 3656 | * |
a2fbb9ea | 3657 | */ |
619c5cb6 VZ |
3658 | struct eth_classify_cmd_header { |
3659 | u8 cmd_general_data; | |
3660 | #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) | |
3661 | #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 | |
3662 | #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) | |
3663 | #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 | |
3664 | #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) | |
3665 | #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 | |
3666 | #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) | |
3667 | #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 | |
3668 | #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) | |
3669 | #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 | |
3670 | u8 func_id; | |
3671 | u8 client_id; | |
3672 | u8 reserved1; | |
a2fbb9ea ET |
3673 | }; |
3674 | ||
619c5cb6 | 3675 | |
a2fbb9ea | 3676 | /* |
619c5cb6 | 3677 | * header for eth classification config ramrod |
a2fbb9ea | 3678 | */ |
619c5cb6 VZ |
3679 | struct eth_classify_header { |
3680 | u8 rule_cnt; | |
3681 | u8 reserved0; | |
3682 | __le16 reserved1; | |
3683 | __le32 echo; | |
a2fbb9ea ET |
3684 | }; |
3685 | ||
3686 | ||
3687 | /* | |
619c5cb6 | 3688 | * Command for adding/removing a MAC classification rule |
a2fbb9ea | 3689 | */ |
619c5cb6 VZ |
3690 | struct eth_classify_mac_cmd { |
3691 | struct eth_classify_cmd_header header; | |
91226790 DK |
3692 | __le16 reserved0; |
3693 | __le16 inner_mac; | |
619c5cb6 VZ |
3694 | __le16 mac_lsb; |
3695 | __le16 mac_mid; | |
3696 | __le16 mac_msb; | |
3697 | __le16 reserved1; | |
3698 | }; | |
3699 | ||
3700 | ||
3701 | /* | |
3702 | * Command for adding/removing a MAC-VLAN pair classification rule | |
3703 | */ | |
3704 | struct eth_classify_pair_cmd { | |
3705 | struct eth_classify_cmd_header header; | |
91226790 DK |
3706 | __le16 reserved0; |
3707 | __le16 inner_mac; | |
619c5cb6 VZ |
3708 | __le16 mac_lsb; |
3709 | __le16 mac_mid; | |
3710 | __le16 mac_msb; | |
3711 | __le16 vlan; | |
3712 | }; | |
3713 | ||
3714 | ||
3715 | /* | |
3716 | * Command for adding/removing a VLAN classification rule | |
3717 | */ | |
3718 | struct eth_classify_vlan_cmd { | |
3719 | struct eth_classify_cmd_header header; | |
3720 | __le32 reserved0; | |
3721 | __le32 reserved1; | |
3722 | __le16 reserved2; | |
3723 | __le16 vlan; | |
a2fbb9ea ET |
3724 | }; |
3725 | ||
619c5cb6 VZ |
3726 | /* |
3727 | * union for eth classification rule | |
3728 | */ | |
3729 | union eth_classify_rule_cmd { | |
3730 | struct eth_classify_mac_cmd mac; | |
3731 | struct eth_classify_vlan_cmd vlan; | |
3732 | struct eth_classify_pair_cmd pair; | |
3733 | }; | |
a2fbb9ea ET |
3734 | |
3735 | /* | |
619c5cb6 | 3736 | * parameters for eth classification configuration ramrod |
a2fbb9ea | 3737 | */ |
619c5cb6 VZ |
3738 | struct eth_classify_rules_ramrod_data { |
3739 | struct eth_classify_header header; | |
3740 | union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; | |
a2fbb9ea ET |
3741 | }; |
3742 | ||
a2fbb9ea ET |
3743 | |
3744 | /* | |
619c5cb6 | 3745 | * The data contain client ID need to the ramrod |
a2fbb9ea | 3746 | */ |
619c5cb6 VZ |
3747 | struct eth_common_ramrod_data { |
3748 | __le32 client_id; | |
3749 | __le32 reserved1; | |
a2fbb9ea ET |
3750 | }; |
3751 | ||
3752 | ||
3753 | /* | |
619c5cb6 | 3754 | * The eth storm context of Ustorm |
a2fbb9ea | 3755 | */ |
619c5cb6 VZ |
3756 | struct ustorm_eth_st_context { |
3757 | u32 reserved0[52]; | |
523224a3 DK |
3758 | }; |
3759 | ||
3760 | /* | |
619c5cb6 | 3761 | * The eth storm context of Tstorm |
523224a3 | 3762 | */ |
619c5cb6 VZ |
3763 | struct tstorm_eth_st_context { |
3764 | u32 __reserved0[28]; | |
a2fbb9ea ET |
3765 | }; |
3766 | ||
3767 | /* | |
619c5cb6 | 3768 | * The eth storm context of Xstorm |
a2fbb9ea | 3769 | */ |
619c5cb6 VZ |
3770 | struct xstorm_eth_st_context { |
3771 | u32 reserved0[60]; | |
a2fbb9ea ET |
3772 | }; |
3773 | ||
3774 | /* | |
619c5cb6 | 3775 | * Ethernet connection context |
a2fbb9ea | 3776 | */ |
619c5cb6 VZ |
3777 | struct eth_context { |
3778 | struct ustorm_eth_st_context ustorm_st_context; | |
3779 | struct tstorm_eth_st_context tstorm_st_context; | |
3780 | struct xstorm_eth_ag_context xstorm_ag_context; | |
3781 | struct tstorm_eth_ag_context tstorm_ag_context; | |
3782 | struct cstorm_eth_ag_context cstorm_ag_context; | |
3783 | struct ustorm_eth_ag_context ustorm_ag_context; | |
3784 | struct timers_block_context timers_context; | |
3785 | struct xstorm_eth_st_context xstorm_st_context; | |
3786 | struct cstorm_eth_st_context cstorm_st_context; | |
a2fbb9ea ET |
3787 | }; |
3788 | ||
3789 | ||
3790 | /* | |
523224a3 | 3791 | * union for sgl and raw data. |
a2fbb9ea | 3792 | */ |
523224a3 DK |
3793 | union eth_sgl_or_raw_data { |
3794 | __le16 sgl[8]; | |
3795 | u32 raw_data[4]; | |
a2fbb9ea ET |
3796 | }; |
3797 | ||
619c5cb6 VZ |
3798 | /* |
3799 | * eth FP end aggregation CQE parameters struct | |
3800 | */ | |
3801 | struct eth_end_agg_rx_cqe { | |
3802 | u8 type_error_flags; | |
3803 | #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) | |
3804 | #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 | |
3805 | #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) | |
3806 | #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 | |
3807 | #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) | |
3808 | #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 | |
3809 | u8 reserved1; | |
3810 | u8 queue_index; | |
3811 | u8 reserved2; | |
3812 | __le32 timestamp_delta; | |
3813 | __le16 num_of_coalesced_segs; | |
3814 | __le16 pkt_len; | |
3815 | u8 pure_ack_count; | |
3816 | u8 reserved3; | |
3817 | __le16 reserved4; | |
3818 | union eth_sgl_or_raw_data sgl_or_raw_data; | |
3819 | __le32 reserved5[8]; | |
3820 | }; | |
3821 | ||
3822 | ||
a2fbb9ea ET |
3823 | /* |
3824 | * regular eth FP CQE parameters struct | |
3825 | */ | |
3826 | struct eth_fast_path_rx_cqe { | |
34f80b04 | 3827 | u8 type_error_flags; |
619c5cb6 | 3828 | #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) |
34f80b04 | 3829 | #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 |
619c5cb6 VZ |
3830 | #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) |
3831 | #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 | |
3832 | #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) | |
3833 | #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 | |
3834 | #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) | |
3835 | #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 | |
3836 | #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) | |
3837 | #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 | |
3838 | #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) | |
3839 | #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 | |
a2fbb9ea ET |
3840 | u8 status_flags; |
3841 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) | |
3842 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 | |
3843 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) | |
3844 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 | |
3845 | #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) | |
3846 | #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 | |
3847 | #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) | |
3848 | #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 | |
3849 | #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) | |
3850 | #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 | |
3851 | #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) | |
3852 | #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 | |
34f80b04 | 3853 | u8 queue_index; |
619c5cb6 | 3854 | u8 placement_offset; |
4781bfad EG |
3855 | __le32 rss_hash_result; |
3856 | __le16 vlan_tag; | |
621b4d66 | 3857 | __le16 pkt_len_or_gro_seg_len; |
4781bfad | 3858 | __le16 len_on_bd; |
a2fbb9ea | 3859 | struct parsing_flags pars_flags; |
523224a3 | 3860 | union eth_sgl_or_raw_data sgl_or_raw_data; |
75b29459 DK |
3861 | __le32 reserved1[7]; |
3862 | u32 marker; | |
619c5cb6 VZ |
3863 | }; |
3864 | ||
3865 | ||
3866 | /* | |
3867 | * Command for setting classification flags for a client | |
3868 | */ | |
3869 | struct eth_filter_rules_cmd { | |
3870 | u8 cmd_general_data; | |
3871 | #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) | |
3872 | #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 | |
3873 | #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) | |
3874 | #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 | |
3875 | #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) | |
3876 | #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 | |
3877 | u8 func_id; | |
3878 | u8 client_id; | |
3879 | u8 reserved1; | |
3880 | __le16 state; | |
3881 | #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) | |
3882 | #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 | |
3883 | #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) | |
3884 | #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 | |
3885 | #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) | |
3886 | #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 | |
3887 | #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) | |
3888 | #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 | |
3889 | #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) | |
3890 | #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 | |
3891 | #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) | |
3892 | #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 | |
3893 | #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) | |
3894 | #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 | |
3895 | #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) | |
3896 | #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 | |
3897 | __le16 reserved3; | |
3898 | struct regpair reserved4; | |
3899 | }; | |
3900 | ||
3901 | ||
3902 | /* | |
3903 | * parameters for eth classification filters ramrod | |
3904 | */ | |
3905 | struct eth_filter_rules_ramrod_data { | |
3906 | struct eth_classify_header header; | |
3907 | struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; | |
3908 | }; | |
3909 | ||
3910 | ||
3911 | /* | |
3912 | * parameters for eth classification configuration ramrod | |
3913 | */ | |
3914 | struct eth_general_rules_ramrod_data { | |
3915 | struct eth_classify_header header; | |
3916 | union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; | |
a2fbb9ea ET |
3917 | }; |
3918 | ||
3919 | ||
3920 | /* | |
619c5cb6 | 3921 | * The data for Halt ramrod |
a2fbb9ea ET |
3922 | */ |
3923 | struct eth_halt_ramrod_data { | |
619c5cb6 VZ |
3924 | __le32 client_id; |
3925 | __le32 reserved0; | |
a2fbb9ea ET |
3926 | }; |
3927 | ||
619c5cb6 | 3928 | |
34f80b04 | 3929 | /* |
91226790 DK |
3930 | * destination and source mac address. |
3931 | */ | |
3932 | struct eth_mac_addresses { | |
3933 | #if defined(__BIG_ENDIAN) | |
3934 | __le16 dst_mid; | |
3935 | __le16 dst_lo; | |
3936 | #elif defined(__LITTLE_ENDIAN) | |
3937 | __le16 dst_lo; | |
3938 | __le16 dst_mid; | |
3939 | #endif | |
3940 | #if defined(__BIG_ENDIAN) | |
3941 | __le16 src_lo; | |
3942 | __le16 dst_hi; | |
3943 | #elif defined(__LITTLE_ENDIAN) | |
3944 | __le16 dst_hi; | |
3945 | __le16 src_lo; | |
3946 | #endif | |
3947 | #if defined(__BIG_ENDIAN) | |
3948 | __le16 src_hi; | |
3949 | __le16 src_mid; | |
3950 | #elif defined(__LITTLE_ENDIAN) | |
3951 | __le16 src_mid; | |
3952 | __le16 src_hi; | |
3953 | #endif | |
3954 | }; | |
3955 | ||
3956 | /* tunneling related data */ | |
3957 | struct eth_tunnel_data { | |
3958 | #if defined(__BIG_ENDIAN) | |
3959 | __le16 dst_mid; | |
3960 | __le16 dst_lo; | |
3961 | #elif defined(__LITTLE_ENDIAN) | |
3962 | __le16 dst_lo; | |
3963 | __le16 dst_mid; | |
3964 | #endif | |
3965 | #if defined(__BIG_ENDIAN) | |
3966 | __le16 reserved0; | |
3967 | __le16 dst_hi; | |
3968 | #elif defined(__LITTLE_ENDIAN) | |
3969 | __le16 dst_hi; | |
3970 | __le16 reserved0; | |
3971 | #endif | |
3972 | #if defined(__BIG_ENDIAN) | |
3973 | u8 reserved1; | |
3974 | u8 ip_hdr_start_inner_w; | |
3975 | __le16 pseudo_csum; | |
3976 | #elif defined(__LITTLE_ENDIAN) | |
3977 | __le16 pseudo_csum; | |
3978 | u8 ip_hdr_start_inner_w; | |
3979 | u8 reserved1; | |
3980 | #endif | |
3981 | }; | |
3982 | ||
3983 | /* union for mac addresses and for tunneling data. | |
3984 | * considered as tunneling data only if (tunnel_exist == 1). | |
34f80b04 | 3985 | */ |
91226790 DK |
3986 | union eth_mac_addr_or_tunnel_data { |
3987 | struct eth_mac_addresses mac_addr; | |
3988 | struct eth_tunnel_data tunnel_data; | |
3989 | }; | |
3990 | ||
3991 | /*Command for setting multicast classification for a client */ | |
619c5cb6 VZ |
3992 | struct eth_multicast_rules_cmd { |
3993 | u8 cmd_general_data; | |
3994 | #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) | |
3995 | #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 | |
3996 | #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) | |
3997 | #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 | |
3998 | #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) | |
3999 | #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 | |
4000 | #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) | |
4001 | #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 | |
4002 | u8 func_id; | |
4003 | u8 bin_id; | |
4004 | u8 engine_id; | |
4005 | __le32 reserved2; | |
4006 | struct regpair reserved3; | |
4007 | }; | |
4008 | ||
619c5cb6 VZ |
4009 | /* |
4010 | * parameters for multicast classification ramrod | |
4011 | */ | |
4012 | struct eth_multicast_rules_ramrod_data { | |
4013 | struct eth_classify_header header; | |
4014 | struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; | |
34f80b04 EG |
4015 | }; |
4016 | ||
a2fbb9ea ET |
4017 | /* |
4018 | * Place holder for ramrods protocol specific data | |
4019 | */ | |
4020 | struct ramrod_data { | |
4781bfad EG |
4021 | __le32 data_lo; |
4022 | __le32 data_hi; | |
a2fbb9ea ET |
4023 | }; |
4024 | ||
4025 | /* | |
33471629 | 4026 | * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) |
a2fbb9ea ET |
4027 | */ |
4028 | union eth_ramrod_data { | |
4029 | struct ramrod_data general; | |
4030 | }; | |
4031 | ||
4032 | ||
619c5cb6 VZ |
4033 | /* |
4034 | * RSS toeplitz hash type, as reported in CQE | |
4035 | */ | |
4036 | enum eth_rss_hash_type { | |
4037 | DEFAULT_HASH_TYPE, | |
4038 | IPV4_HASH_TYPE, | |
4039 | TCP_IPV4_HASH_TYPE, | |
4040 | IPV6_HASH_TYPE, | |
4041 | TCP_IPV6_HASH_TYPE, | |
4042 | VLAN_PRI_HASH_TYPE, | |
4043 | E1HOV_PRI_HASH_TYPE, | |
4044 | DSCP_HASH_TYPE, | |
4045 | MAX_ETH_RSS_HASH_TYPE | |
4046 | }; | |
4047 | ||
4048 | ||
4049 | /* | |
4050 | * Ethernet RSS mode | |
4051 | */ | |
4052 | enum eth_rss_mode { | |
4053 | ETH_RSS_MODE_DISABLED, | |
4054 | ETH_RSS_MODE_REGULAR, | |
4055 | ETH_RSS_MODE_VLAN_PRI, | |
4056 | ETH_RSS_MODE_E1HOV_PRI, | |
4057 | ETH_RSS_MODE_IP_DSCP, | |
4058 | MAX_ETH_RSS_MODE | |
4059 | }; | |
4060 | ||
4061 | ||
4062 | /* | |
4063 | * parameters for RSS update ramrod (E2) | |
4064 | */ | |
4065 | struct eth_rss_update_ramrod_data { | |
4066 | u8 rss_engine_id; | |
4067 | u8 capabilities; | |
4068 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) | |
4069 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 | |
4070 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) | |
4071 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 | |
4072 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) | |
4073 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 | |
4074 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) | |
4075 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 | |
4076 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) | |
4077 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 | |
4078 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) | |
4079 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 | |
91226790 DK |
4080 | #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) |
4081 | #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6 | |
96bed4b9 YM |
4082 | #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) |
4083 | #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 | |
619c5cb6 VZ |
4084 | u8 rss_result_mask; |
4085 | u8 rss_mode; | |
91226790 DK |
4086 | __le16 udp_4tuple_dst_port_mask; |
4087 | __le16 udp_4tuple_dst_port_value; | |
619c5cb6 VZ |
4088 | u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; |
4089 | __le32 rss_key[T_ETH_RSS_KEY]; | |
4090 | __le32 echo; | |
4091 | __le32 reserved3; | |
4092 | }; | |
4093 | ||
4094 | ||
4095 | /* | |
4096 | * The eth Rx Buffer Descriptor | |
4097 | */ | |
4098 | struct eth_rx_bd { | |
4099 | __le32 addr_lo; | |
4100 | __le32 addr_hi; | |
4101 | }; | |
4102 | ||
4103 | ||
a2fbb9ea ET |
4104 | /* |
4105 | * Eth Rx Cqe structure- general structure for ramrods | |
4106 | */ | |
4107 | struct common_ramrod_eth_rx_cqe { | |
34f80b04 | 4108 | u8 ramrod_type; |
619c5cb6 | 4109 | #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) |
34f80b04 | 4110 | #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 |
619c5cb6 VZ |
4111 | #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) |
4112 | #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 | |
4113 | #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) | |
4114 | #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 | |
8d9c5f34 | 4115 | u8 conn_type; |
4781bfad EG |
4116 | __le16 reserved1; |
4117 | __le32 conn_and_cmd_data; | |
a2fbb9ea ET |
4118 | #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) |
4119 | #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 | |
4120 | #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) | |
4121 | #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 | |
4122 | struct ramrod_data protocol_data; | |
619c5cb6 VZ |
4123 | __le32 echo; |
4124 | __le32 reserved2[11]; | |
4125 | }; | |
4126 | ||
4127 | /* | |
4128 | * Rx Last CQE in page (in ETH) | |
4129 | */ | |
4130 | struct eth_rx_cqe_next_page { | |
4131 | __le32 addr_lo; | |
4132 | __le32 addr_hi; | |
4133 | __le32 reserved[14]; | |
4134 | }; | |
4135 | ||
4136 | /* | |
4137 | * union for all eth rx cqe types (fix their sizes) | |
4138 | */ | |
4139 | union eth_rx_cqe { | |
4140 | struct eth_fast_path_rx_cqe fast_path_cqe; | |
4141 | struct common_ramrod_eth_rx_cqe ramrod_cqe; | |
4142 | struct eth_rx_cqe_next_page next_page_cqe; | |
4143 | struct eth_end_agg_rx_cqe end_agg_cqe; | |
4144 | }; | |
4145 | ||
4146 | ||
4147 | /* | |
4148 | * Values for RX ETH CQE type field | |
4149 | */ | |
4150 | enum eth_rx_cqe_type { | |
4151 | RX_ETH_CQE_TYPE_ETH_FASTPATH, | |
4152 | RX_ETH_CQE_TYPE_ETH_RAMROD, | |
4153 | RX_ETH_CQE_TYPE_ETH_START_AGG, | |
4154 | RX_ETH_CQE_TYPE_ETH_STOP_AGG, | |
4155 | MAX_ETH_RX_CQE_TYPE | |
4156 | }; | |
4157 | ||
4158 | ||
4159 | /* | |
4160 | * Type of SGL/Raw field in ETH RX fast path CQE | |
4161 | */ | |
4162 | enum eth_rx_fp_sel { | |
4163 | ETH_FP_CQE_REGULAR, | |
4164 | ETH_FP_CQE_RAW, | |
4165 | MAX_ETH_RX_FP_SEL | |
4166 | }; | |
4167 | ||
4168 | ||
4169 | /* | |
4170 | * The eth Rx SGE Descriptor | |
4171 | */ | |
4172 | struct eth_rx_sge { | |
4173 | __le32 addr_lo; | |
4174 | __le32 addr_hi; | |
4175 | }; | |
4176 | ||
4177 | ||
4178 | /* | |
4179 | * common data for all protocols | |
4180 | */ | |
4181 | struct spe_hdr { | |
4182 | __le32 conn_and_cmd_data; | |
4183 | #define SPE_HDR_CID (0xFFFFFF<<0) | |
4184 | #define SPE_HDR_CID_SHIFT 0 | |
4185 | #define SPE_HDR_CMD_ID (0xFF<<24) | |
4186 | #define SPE_HDR_CMD_ID_SHIFT 24 | |
4187 | __le16 type; | |
4188 | #define SPE_HDR_CONN_TYPE (0xFF<<0) | |
4189 | #define SPE_HDR_CONN_TYPE_SHIFT 0 | |
4190 | #define SPE_HDR_FUNCTION_ID (0xFF<<8) | |
4191 | #define SPE_HDR_FUNCTION_ID_SHIFT 8 | |
4192 | __le16 reserved1; | |
4193 | }; | |
4194 | ||
4195 | /* | |
4196 | * specific data for ethernet slow path element | |
4197 | */ | |
4198 | union eth_specific_data { | |
4199 | u8 protocol_data[8]; | |
4200 | struct regpair client_update_ramrod_data; | |
4201 | struct regpair client_init_ramrod_init_data; | |
4202 | struct eth_halt_ramrod_data halt_ramrod_data; | |
4203 | struct regpair update_data_addr; | |
4204 | struct eth_common_ramrod_data common_ramrod_data; | |
4205 | struct regpair classify_cfg_addr; | |
4206 | struct regpair filter_cfg_addr; | |
4207 | struct regpair mcast_cfg_addr; | |
4208 | }; | |
4209 | ||
4210 | /* | |
4211 | * Ethernet slow path element | |
4212 | */ | |
4213 | struct eth_spe { | |
4214 | struct spe_hdr hdr; | |
4215 | union eth_specific_data data; | |
4216 | }; | |
4217 | ||
4218 | ||
4219 | /* | |
4220 | * Ethernet command ID for slow path elements | |
4221 | */ | |
4222 | enum eth_spqe_cmd_id { | |
4223 | RAMROD_CMD_ID_ETH_UNUSED, | |
4224 | RAMROD_CMD_ID_ETH_CLIENT_SETUP, | |
4225 | RAMROD_CMD_ID_ETH_HALT, | |
4226 | RAMROD_CMD_ID_ETH_FORWARD_SETUP, | |
4227 | RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, | |
4228 | RAMROD_CMD_ID_ETH_CLIENT_UPDATE, | |
4229 | RAMROD_CMD_ID_ETH_EMPTY, | |
4230 | RAMROD_CMD_ID_ETH_TERMINATE, | |
4231 | RAMROD_CMD_ID_ETH_TPA_UPDATE, | |
4232 | RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, | |
4233 | RAMROD_CMD_ID_ETH_FILTER_RULES, | |
4234 | RAMROD_CMD_ID_ETH_MULTICAST_RULES, | |
4235 | RAMROD_CMD_ID_ETH_RSS_UPDATE, | |
4236 | RAMROD_CMD_ID_ETH_SET_MAC, | |
4237 | MAX_ETH_SPQE_CMD_ID | |
4238 | }; | |
4239 | ||
4240 | ||
4241 | /* | |
4242 | * eth tpa update command | |
4243 | */ | |
4244 | enum eth_tpa_update_command { | |
4245 | TPA_UPDATE_NONE_COMMAND, | |
4246 | TPA_UPDATE_ENABLE_COMMAND, | |
4247 | TPA_UPDATE_DISABLE_COMMAND, | |
4248 | MAX_ETH_TPA_UPDATE_COMMAND | |
4249 | }; | |
4250 | ||
91226790 DK |
4251 | /* In case of LSO over IPv4 tunnel, whether to increment |
4252 | * IP ID on external IP header or internal IP header | |
4253 | */ | |
4254 | enum eth_tunnel_lso_inc_ip_id { | |
4255 | EXT_HEADER, | |
4256 | INT_HEADER, | |
4257 | MAX_ETH_TUNNEL_LSO_INC_IP_ID | |
4258 | }; | |
4259 | ||
4260 | /* In case tunnel exist and L4 checksum offload, | |
4261 | * the pseudo checksum location, on packet or on BD. | |
4262 | */ | |
4263 | enum eth_tunnel_non_lso_pcsum_location { | |
4264 | PCSUM_ON_PKT, | |
4265 | PCSUM_ON_BD, | |
4266 | MAX_ETH_TUNNEL_NON_LSO_PCSUM_LOCATION | |
4267 | }; | |
619c5cb6 VZ |
4268 | |
4269 | /* | |
4270 | * Tx regular BD structure | |
4271 | */ | |
4272 | struct eth_tx_bd { | |
4273 | __le32 addr_lo; | |
4274 | __le32 addr_hi; | |
4275 | __le16 total_pkt_bytes; | |
4276 | __le16 nbytes; | |
4277 | u8 reserved[4]; | |
4278 | }; | |
4279 | ||
4280 | ||
4281 | /* | |
4282 | * structure for easy accessibility to assembler | |
4283 | */ | |
4284 | struct eth_tx_bd_flags { | |
4285 | u8 as_bitfield; | |
4286 | #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) | |
4287 | #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 | |
4288 | #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) | |
4289 | #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 | |
4290 | #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) | |
4291 | #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 | |
4292 | #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) | |
4293 | #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 | |
4294 | #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) | |
4295 | #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 | |
4296 | #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) | |
4297 | #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 | |
4298 | #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) | |
4299 | #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 | |
a2fbb9ea ET |
4300 | }; |
4301 | ||
4302 | /* | |
619c5cb6 | 4303 | * The eth Tx Buffer Descriptor |
a2fbb9ea | 4304 | */ |
619c5cb6 | 4305 | struct eth_tx_start_bd { |
4781bfad EG |
4306 | __le32 addr_lo; |
4307 | __le32 addr_hi; | |
619c5cb6 VZ |
4308 | __le16 nbd; |
4309 | __le16 nbytes; | |
4310 | __le16 vlan_or_ethertype; | |
4311 | struct eth_tx_bd_flags bd_flags; | |
4312 | u8 general_data; | |
4313 | #define ETH_TX_START_BD_HDR_NBDS (0xF<<0) | |
4314 | #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 | |
4315 | #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) | |
4316 | #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 | |
96bed4b9 YM |
4317 | #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) |
4318 | #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 | |
91226790 DK |
4319 | #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) |
4320 | #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 | |
a2fbb9ea ET |
4321 | }; |
4322 | ||
4323 | /* | |
619c5cb6 | 4324 | * Tx parsing BD structure for ETH E1/E1h |
a2fbb9ea | 4325 | */ |
619c5cb6 | 4326 | struct eth_tx_parse_bd_e1x { |
96bed4b9 | 4327 | __le16 global_data; |
619c5cb6 VZ |
4328 | #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) |
4329 | #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 | |
96bed4b9 YM |
4330 | #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) |
4331 | #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 | |
4332 | #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) | |
4333 | #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 | |
4334 | #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) | |
4335 | #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 | |
4336 | #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) | |
4337 | #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 | |
4338 | #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) | |
4339 | #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 | |
619c5cb6 VZ |
4340 | u8 tcp_flags; |
4341 | #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) | |
4342 | #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 | |
4343 | #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) | |
4344 | #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 | |
4345 | #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) | |
4346 | #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 | |
4347 | #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) | |
4348 | #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 | |
4349 | #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) | |
4350 | #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 | |
4351 | #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) | |
4352 | #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 | |
4353 | #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) | |
4354 | #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 | |
4355 | #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) | |
4356 | #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 | |
4357 | u8 ip_hlen_w; | |
619c5cb6 VZ |
4358 | __le16 total_hlen_w; |
4359 | __le16 tcp_pseudo_csum; | |
4360 | __le16 lso_mss; | |
4361 | __le16 ip_id; | |
4362 | __le32 tcp_send_seq; | |
a2fbb9ea ET |
4363 | }; |
4364 | ||
a2fbb9ea | 4365 | /* |
619c5cb6 | 4366 | * Tx parsing BD structure for ETH E2 |
a2fbb9ea | 4367 | */ |
619c5cb6 | 4368 | struct eth_tx_parse_bd_e2 { |
91226790 | 4369 | union eth_mac_addr_or_tunnel_data data; |
619c5cb6 | 4370 | __le32 parsing_data; |
91226790 DK |
4371 | #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) |
4372 | #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 | |
96bed4b9 YM |
4373 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) |
4374 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 | |
4375 | #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) | |
4376 | #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 | |
4377 | #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) | |
4378 | #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 | |
4379 | #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) | |
4380 | #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 | |
a2fbb9ea ET |
4381 | }; |
4382 | ||
a2fbb9ea | 4383 | /* |
91226790 | 4384 | * Tx 2nd parsing BD structure for ETH packet |
a2fbb9ea | 4385 | */ |
91226790 DK |
4386 | struct eth_tx_parse_2nd_bd { |
4387 | __le16 global_data; | |
4388 | #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) | |
4389 | #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 | |
4390 | #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER (0x1<<4) | |
4391 | #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT 4 | |
4392 | #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) | |
4393 | #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 | |
4394 | #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) | |
4395 | #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 | |
4396 | #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) | |
4397 | #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 | |
4398 | #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) | |
4399 | #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 | |
4400 | #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x7<<13) | |
4401 | #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 13 | |
4402 | __le16 reserved1; | |
4403 | u8 tcp_flags; | |
4404 | #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) | |
4405 | #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 | |
4406 | #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) | |
4407 | #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 | |
4408 | #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) | |
4409 | #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 | |
4410 | #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) | |
4411 | #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 | |
4412 | #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) | |
4413 | #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 | |
4414 | #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) | |
4415 | #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 | |
4416 | #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) | |
4417 | #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 | |
4418 | #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) | |
4419 | #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 | |
4420 | u8 reserved2; | |
4421 | u8 tunnel_udp_hdr_start_w; | |
4422 | u8 fw_ip_hdr_to_payload_w; | |
4423 | __le16 fw_ip_csum_wo_len_flags_frag; | |
4424 | __le16 hw_ip_id; | |
4425 | __le32 tcp_send_seq; | |
4426 | }; | |
4427 | ||
4428 | /* The last BD in the BD memory will hold a pointer to the next BD memory */ | |
619c5cb6 VZ |
4429 | struct eth_tx_next_bd { |
4430 | __le32 addr_lo; | |
4431 | __le32 addr_hi; | |
4432 | u8 reserved[8]; | |
a2fbb9ea ET |
4433 | }; |
4434 | ||
4435 | /* | |
619c5cb6 | 4436 | * union for 4 Bd types |
a2fbb9ea | 4437 | */ |
619c5cb6 VZ |
4438 | union eth_tx_bd_types { |
4439 | struct eth_tx_start_bd start_bd; | |
4440 | struct eth_tx_bd reg_bd; | |
4441 | struct eth_tx_parse_bd_e1x parse_bd_e1x; | |
4442 | struct eth_tx_parse_bd_e2 parse_bd_e2; | |
91226790 | 4443 | struct eth_tx_parse_2nd_bd parse_2nd_bd; |
619c5cb6 | 4444 | struct eth_tx_next_bd next_bd; |
a2fbb9ea ET |
4445 | }; |
4446 | ||
a2fbb9ea | 4447 | /* |
ca00392c | 4448 | * array of 13 bds as appears in the eth xstorm context |
a2fbb9ea | 4449 | */ |
ca00392c EG |
4450 | struct eth_tx_bds_array { |
4451 | union eth_tx_bd_types bds[13]; | |
a2fbb9ea ET |
4452 | }; |
4453 | ||
4454 | ||
4455 | /* | |
619c5cb6 | 4456 | * VLAN mode on TX BDs |
a2fbb9ea | 4457 | */ |
619c5cb6 VZ |
4458 | enum eth_tx_vlan_type { |
4459 | X_ETH_NO_VLAN, | |
4460 | X_ETH_OUTBAND_VLAN, | |
4461 | X_ETH_INBAND_VLAN, | |
4462 | X_ETH_FW_ADDED_VLAN, | |
4463 | MAX_ETH_TX_VLAN_TYPE | |
a2fbb9ea ET |
4464 | }; |
4465 | ||
ca00392c | 4466 | |
a2fbb9ea | 4467 | /* |
619c5cb6 | 4468 | * Ethernet VLAN filtering mode in E1x |
a2fbb9ea | 4469 | */ |
619c5cb6 VZ |
4470 | enum eth_vlan_filter_mode { |
4471 | ETH_VLAN_FILTER_ANY_VLAN, | |
4472 | ETH_VLAN_FILTER_SPECIFIC_VLAN, | |
4473 | ETH_VLAN_FILTER_CLASSIFY, | |
4474 | MAX_ETH_VLAN_FILTER_MODE | |
a2fbb9ea ET |
4475 | }; |
4476 | ||
4477 | ||
4478 | /* | |
4479 | * MAC filtering configuration command header | |
4480 | */ | |
4481 | struct mac_configuration_hdr { | |
8d9c5f34 | 4482 | u8 length; |
a2fbb9ea | 4483 | u8 offset; |
619c5cb6 VZ |
4484 | __le16 client_id; |
4485 | __le32 echo; | |
a2fbb9ea ET |
4486 | }; |
4487 | ||
4488 | /* | |
4489 | * MAC address in list for ramrod | |
4490 | */ | |
523224a3 | 4491 | struct mac_configuration_entry { |
4781bfad EG |
4492 | __le16 lsb_mac_addr; |
4493 | __le16 middle_mac_addr; | |
4494 | __le16 msb_mac_addr; | |
523224a3 DK |
4495 | __le16 vlan_id; |
4496 | u8 pf_id; | |
a2fbb9ea | 4497 | u8 flags; |
523224a3 DK |
4498 | #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) |
4499 | #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 | |
4500 | #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) | |
4501 | #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 | |
4502 | #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) | |
4503 | #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 | |
4504 | #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) | |
4505 | #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 | |
4506 | #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) | |
4507 | #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 | |
4508 | #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) | |
4509 | #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 | |
619c5cb6 VZ |
4510 | __le16 reserved0; |
4511 | __le32 clients_bit_vector; | |
a2fbb9ea ET |
4512 | }; |
4513 | ||
4514 | /* | |
523224a3 | 4515 | * MAC filtering configuration command |
a2fbb9ea ET |
4516 | */ |
4517 | struct mac_configuration_cmd { | |
4518 | struct mac_configuration_hdr hdr; | |
4519 | struct mac_configuration_entry config_table[64]; | |
4520 | }; | |
4521 | ||
4522 | ||
619c5cb6 VZ |
4523 | /* |
4524 | * Set-MAC command type (in E1x) | |
4525 | */ | |
4526 | enum set_mac_action_type { | |
4527 | T_ETH_MAC_COMMAND_INVALIDATE, | |
4528 | T_ETH_MAC_COMMAND_SET, | |
4529 | MAX_SET_MAC_ACTION_TYPE | |
4530 | }; | |
4531 | ||
4532 | ||
621b4d66 DK |
4533 | /* |
4534 | * Ethernet TPA Modes | |
4535 | */ | |
4536 | enum tpa_mode { | |
4537 | TPA_LRO, | |
4538 | TPA_GRO, | |
4539 | MAX_TPA_MODE}; | |
4540 | ||
4541 | ||
619c5cb6 VZ |
4542 | /* |
4543 | * tpa update ramrod data | |
4544 | */ | |
4545 | struct tpa_update_ramrod_data { | |
4546 | u8 update_ipv4; | |
4547 | u8 update_ipv6; | |
4548 | u8 client_id; | |
4549 | u8 max_tpa_queues; | |
4550 | u8 max_sges_for_packet; | |
4551 | u8 complete_on_both_clients; | |
621b4d66 DK |
4552 | u8 dont_verify_rings_pause_thr_flg; |
4553 | u8 tpa_mode; | |
619c5cb6 VZ |
4554 | __le16 sge_buff_size; |
4555 | __le16 max_agg_size; | |
4556 | __le32 sge_page_base_lo; | |
4557 | __le32 sge_page_base_hi; | |
4558 | __le16 sge_pause_thr_low; | |
4559 | __le16 sge_pause_thr_high; | |
4560 | }; | |
4561 | ||
4562 | ||
34f80b04 EG |
4563 | /* |
4564 | * approximate-match multicast filtering for E1H per function in Tstorm | |
4565 | */ | |
4566 | struct tstorm_eth_approximate_match_multicast_filtering { | |
4567 | u32 mcast_add_hash_bit_array[8]; | |
4568 | }; | |
4569 | ||
4570 | ||
619c5cb6 VZ |
4571 | /* |
4572 | * Common configuration parameters per function in Tstorm | |
4573 | */ | |
4574 | struct tstorm_eth_function_common_config { | |
4575 | __le16 config_flags; | |
4576 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) | |
4577 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 | |
4578 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) | |
4579 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 | |
4580 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) | |
4581 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 | |
4582 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) | |
4583 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 | |
4584 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) | |
4585 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 | |
4586 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) | |
4587 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 | |
4588 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) | |
4589 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 | |
4590 | u8 rss_result_mask; | |
4591 | u8 reserved1; | |
4592 | __le16 vlan_id[2]; | |
4593 | }; | |
4594 | ||
4595 | ||
a2fbb9ea ET |
4596 | /* |
4597 | * MAC filtering configuration parameters per port in Tstorm | |
4598 | */ | |
4599 | struct tstorm_eth_mac_filter_config { | |
86564c3f YM |
4600 | u32 ucast_drop_all; |
4601 | u32 ucast_accept_all; | |
4602 | u32 mcast_drop_all; | |
4603 | u32 mcast_accept_all; | |
4604 | u32 bcast_accept_all; | |
4605 | u32 vlan_filter[2]; | |
4606 | u32 unmatched_unicast; | |
a2fbb9ea ET |
4607 | }; |
4608 | ||
4609 | ||
8d9c5f34 | 4610 | /* |
619c5cb6 | 4611 | * tx only queue init ramrod data |
8d9c5f34 | 4612 | */ |
619c5cb6 VZ |
4613 | struct tx_queue_init_ramrod_data { |
4614 | struct client_init_general_data general; | |
4615 | struct client_init_tx_data tx; | |
8d9c5f34 EG |
4616 | }; |
4617 | ||
4618 | ||
34f80b04 EG |
4619 | /* |
4620 | * Three RX producers for ETH | |
4621 | */ | |
8d9c5f34 | 4622 | struct ustorm_eth_rx_producers { |
a2fbb9ea | 4623 | #if defined(__BIG_ENDIAN) |
34f80b04 EG |
4624 | u16 bd_prod; |
4625 | u16 cqe_prod; | |
a2fbb9ea | 4626 | #elif defined(__LITTLE_ENDIAN) |
34f80b04 EG |
4627 | u16 cqe_prod; |
4628 | u16 bd_prod; | |
a2fbb9ea | 4629 | #endif |
a2fbb9ea | 4630 | #if defined(__BIG_ENDIAN) |
34f80b04 EG |
4631 | u16 reserved; |
4632 | u16 sge_prod; | |
a2fbb9ea | 4633 | #elif defined(__LITTLE_ENDIAN) |
34f80b04 EG |
4634 | u16 sge_prod; |
4635 | u16 reserved; | |
a2fbb9ea | 4636 | #endif |
a2fbb9ea ET |
4637 | }; |
4638 | ||
a2fbb9ea | 4639 | |
523224a3 | 4640 | /* |
50f0a562 BW |
4641 | * FCoE RX statistics parameters section#0 |
4642 | */ | |
4643 | struct fcoe_rx_stat_params_section0 { | |
4644 | __le32 fcoe_rx_pkt_cnt; | |
4645 | __le32 fcoe_rx_byte_cnt; | |
4646 | }; | |
4647 | ||
4648 | ||
4649 | /* | |
4650 | * FCoE RX statistics parameters section#1 | |
4651 | */ | |
4652 | struct fcoe_rx_stat_params_section1 { | |
4653 | __le32 fcoe_ver_cnt; | |
4654 | __le32 fcoe_rx_drop_pkt_cnt; | |
4655 | }; | |
4656 | ||
4657 | ||
4658 | /* | |
4659 | * FCoE RX statistics parameters section#2 | |
523224a3 | 4660 | */ |
50f0a562 BW |
4661 | struct fcoe_rx_stat_params_section2 { |
4662 | __le32 fc_crc_cnt; | |
4663 | __le32 eofa_del_cnt; | |
4664 | __le32 miss_frame_cnt; | |
4665 | __le32 seq_timeout_cnt; | |
4666 | __le32 drop_seq_cnt; | |
4667 | __le32 fcoe_rx_drop_pkt_cnt; | |
4668 | __le32 fcp_rx_pkt_cnt; | |
4669 | __le32 reserved0; | |
4670 | }; | |
4671 | ||
4672 | ||
4673 | /* | |
4674 | * FCoE TX statistics parameters | |
4675 | */ | |
4676 | struct fcoe_tx_stat_params { | |
4677 | __le32 fcoe_tx_pkt_cnt; | |
4678 | __le32 fcoe_tx_byte_cnt; | |
4679 | __le32 fcp_tx_pkt_cnt; | |
4680 | __le32 reserved0; | |
4681 | }; | |
4682 | ||
4683 | /* | |
4684 | * FCoE statistics parameters | |
4685 | */ | |
4686 | struct fcoe_statistics_params { | |
4687 | struct fcoe_tx_stat_params tx_stat; | |
4688 | struct fcoe_rx_stat_params_section0 rx_stat0; | |
4689 | struct fcoe_rx_stat_params_section1 rx_stat1; | |
4690 | struct fcoe_rx_stat_params_section2 rx_stat2; | |
4691 | }; | |
4692 | ||
4693 | ||
a3348722 BW |
4694 | /* |
4695 | * The data afex vif list ramrod need | |
4696 | */ | |
4697 | struct afex_vif_list_ramrod_data { | |
4698 | u8 afex_vif_list_command; | |
4699 | u8 func_bit_map; | |
4700 | __le16 vif_list_index; | |
4701 | u8 func_to_clear; | |
4702 | u8 echo; | |
4703 | __le16 reserved1; | |
4704 | }; | |
4705 | ||
4706 | ||
50f0a562 BW |
4707 | /* |
4708 | * cfc delete event data | |
a3348722 | 4709 | */ |
523224a3 DK |
4710 | struct cfc_del_event_data { |
4711 | u32 cid; | |
619c5cb6 VZ |
4712 | u32 reserved0; |
4713 | u32 reserved1; | |
523224a3 DK |
4714 | }; |
4715 | ||
4716 | ||
34f80b04 EG |
4717 | /* |
4718 | * per-port SAFC demo variables | |
4719 | */ | |
4720 | struct cmng_flags_per_port { | |
8a1c38d1 EG |
4721 | u32 cmng_enables; |
4722 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) | |
4723 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 | |
4724 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) | |
4725 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 | |
619c5cb6 VZ |
4726 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) |
4727 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 | |
4728 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) | |
4729 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 | |
4730 | #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) | |
4731 | #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 | |
4732 | u32 __reserved1; | |
a2fbb9ea ET |
4733 | }; |
4734 | ||
34f80b04 EG |
4735 | |
4736 | /* | |
4737 | * per-port rate shaping variables | |
4738 | */ | |
4739 | struct rate_shaping_vars_per_port { | |
4740 | u32 rs_periodic_timeout; | |
4741 | u32 rs_threshold; | |
4742 | }; | |
4743 | ||
34f80b04 EG |
4744 | /* |
4745 | * per-port fairness variables | |
4746 | */ | |
4747 | struct fairness_vars_per_port { | |
4748 | u32 upper_bound; | |
4749 | u32 fair_threshold; | |
4750 | u32 fairness_timeout; | |
619c5cb6 | 4751 | u32 reserved0; |
34f80b04 EG |
4752 | }; |
4753 | ||
34f80b04 EG |
4754 | /* |
4755 | * per-port SAFC variables | |
4756 | */ | |
4757 | struct safc_struct_per_port { | |
4758 | #if defined(__BIG_ENDIAN) | |
8d9c5f34 EG |
4759 | u16 __reserved1; |
4760 | u8 __reserved0; | |
34f80b04 EG |
4761 | u8 safc_timeout_usec; |
4762 | #elif defined(__LITTLE_ENDIAN) | |
4763 | u8 safc_timeout_usec; | |
8d9c5f34 EG |
4764 | u8 __reserved0; |
4765 | u16 __reserved1; | |
34f80b04 | 4766 | #endif |
523224a3 | 4767 | u8 cos_to_traffic_types[MAX_COS_NUMBER]; |
8d9c5f34 | 4768 | u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; |
a2fbb9ea ET |
4769 | }; |
4770 | ||
34f80b04 EG |
4771 | /* |
4772 | * Per-port congestion management variables | |
4773 | */ | |
4774 | struct cmng_struct_per_port { | |
4775 | struct rate_shaping_vars_per_port rs_vars; | |
4776 | struct fairness_vars_per_port fair_vars; | |
4777 | struct safc_struct_per_port safc_vars; | |
4778 | struct cmng_flags_per_port flags; | |
a2fbb9ea ET |
4779 | }; |
4780 | ||
b475d78f YM |
4781 | /* |
4782 | * a single rate shaping counter. can be used as protocol or vnic counter | |
4783 | */ | |
4784 | struct rate_shaping_counter { | |
4785 | u32 quota; | |
4786 | #if defined(__BIG_ENDIAN) | |
4787 | u16 __reserved0; | |
4788 | u16 rate; | |
4789 | #elif defined(__LITTLE_ENDIAN) | |
4790 | u16 rate; | |
4791 | u16 __reserved0; | |
4792 | #endif | |
4793 | }; | |
4794 | ||
4795 | /* | |
4796 | * per-vnic rate shaping variables | |
4797 | */ | |
4798 | struct rate_shaping_vars_per_vn { | |
4799 | struct rate_shaping_counter vn_counter; | |
4800 | }; | |
4801 | ||
4802 | /* | |
4803 | * per-vnic fairness variables | |
4804 | */ | |
4805 | struct fairness_vars_per_vn { | |
4806 | u32 cos_credit_delta[MAX_COS_NUMBER]; | |
4807 | u32 vn_credit_delta; | |
4808 | u32 __reserved0; | |
4809 | }; | |
4810 | ||
4811 | /* | |
4812 | * cmng port init state | |
4813 | */ | |
4814 | struct cmng_vnic { | |
4815 | struct rate_shaping_vars_per_vn vnic_max_rate[4]; | |
4816 | struct fairness_vars_per_vn vnic_min_rate[4]; | |
4817 | }; | |
4818 | ||
4819 | /* | |
4820 | * cmng port init state | |
4821 | */ | |
4822 | struct cmng_init { | |
4823 | struct cmng_struct_per_port port; | |
4824 | struct cmng_vnic vnic; | |
4825 | }; | |
4826 | ||
4827 | ||
4828 | /* | |
4829 | * driver parameters for congestion management init, all rates are in Mbps | |
4830 | */ | |
4831 | struct cmng_init_input { | |
4832 | u32 port_rate; | |
4833 | u16 vnic_min_rate[4]; | |
4834 | u16 vnic_max_rate[4]; | |
4835 | u16 cos_min_rate[MAX_COS_NUMBER]; | |
4836 | u16 cos_to_pause_mask[MAX_COS_NUMBER]; | |
4837 | struct cmng_flags_per_port flags; | |
4838 | }; | |
4839 | ||
a2fbb9ea | 4840 | |
619c5cb6 VZ |
4841 | /* |
4842 | * Protocol-common command ID for slow path elements | |
4843 | */ | |
4844 | enum common_spqe_cmd_id { | |
4845 | RAMROD_CMD_ID_COMMON_UNUSED, | |
4846 | RAMROD_CMD_ID_COMMON_FUNCTION_START, | |
4847 | RAMROD_CMD_ID_COMMON_FUNCTION_STOP, | |
621b4d66 | 4848 | RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, |
619c5cb6 VZ |
4849 | RAMROD_CMD_ID_COMMON_CFC_DEL, |
4850 | RAMROD_CMD_ID_COMMON_CFC_DEL_WB, | |
4851 | RAMROD_CMD_ID_COMMON_STAT_QUERY, | |
4852 | RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, | |
4853 | RAMROD_CMD_ID_COMMON_START_TRAFFIC, | |
a3348722 | 4854 | RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, |
91226790 | 4855 | RAMROD_CMD_ID_COMMON_SET_TIMESYNC, |
619c5cb6 VZ |
4856 | MAX_COMMON_SPQE_CMD_ID |
4857 | }; | |
4858 | ||
619c5cb6 VZ |
4859 | /* |
4860 | * Per-protocol connection types | |
4861 | */ | |
4862 | enum connection_type { | |
4863 | ETH_CONNECTION_TYPE, | |
4864 | TOE_CONNECTION_TYPE, | |
4865 | RDMA_CONNECTION_TYPE, | |
4866 | ISCSI_CONNECTION_TYPE, | |
4867 | FCOE_CONNECTION_TYPE, | |
4868 | RESERVED_CONNECTION_TYPE_0, | |
4869 | RESERVED_CONNECTION_TYPE_1, | |
4870 | RESERVED_CONNECTION_TYPE_2, | |
4871 | NONE_CONNECTION_TYPE, | |
4872 | MAX_CONNECTION_TYPE | |
4873 | }; | |
4874 | ||
4875 | ||
4876 | /* | |
4877 | * Cos modes | |
4878 | */ | |
4879 | enum cos_mode { | |
4880 | OVERRIDE_COS, | |
4881 | STATIC_COS, | |
4882 | FW_WRR, | |
4883 | MAX_COS_MODE | |
4884 | }; | |
4885 | ||
523224a3 DK |
4886 | |
4887 | /* | |
4888 | * Dynamic HC counters set by the driver | |
4889 | */ | |
4890 | struct hc_dynamic_drv_counter { | |
4891 | u32 val[HC_SB_MAX_DYNAMIC_INDICES]; | |
4892 | }; | |
4893 | ||
4894 | /* | |
4895 | * zone A per-queue data | |
4896 | */ | |
4897 | struct cstorm_queue_zone_data { | |
4898 | struct hc_dynamic_drv_counter hc_dyn_drv_cnt; | |
4899 | struct regpair reserved[2]; | |
4900 | }; | |
4901 | ||
619c5cb6 | 4902 | |
ca00392c | 4903 | /* |
619c5cb6 | 4904 | * Vf-PF channel data in cstorm ram (non-triggered zone) |
ca00392c | 4905 | */ |
619c5cb6 VZ |
4906 | struct vf_pf_channel_zone_data { |
4907 | u32 msg_addr_lo; | |
4908 | u32 msg_addr_hi; | |
ca00392c EG |
4909 | }; |
4910 | ||
a2fbb9ea | 4911 | /* |
619c5cb6 | 4912 | * zone for VF non-triggered data |
a2fbb9ea | 4913 | */ |
619c5cb6 VZ |
4914 | struct non_trigger_vf_zone { |
4915 | struct vf_pf_channel_zone_data vf_pf_channel; | |
a2fbb9ea ET |
4916 | }; |
4917 | ||
bb2a0f7a | 4918 | /* |
619c5cb6 | 4919 | * Vf-PF channel trigger zone in cstorm ram |
bb2a0f7a | 4920 | */ |
619c5cb6 VZ |
4921 | struct vf_pf_channel_zone_trigger { |
4922 | u8 addr_valid; | |
bb2a0f7a YG |
4923 | }; |
4924 | ||
bb2a0f7a | 4925 | /* |
619c5cb6 | 4926 | * zone that triggers the in-bound interrupt |
bb2a0f7a | 4927 | */ |
619c5cb6 VZ |
4928 | struct trigger_vf_zone { |
4929 | #if defined(__BIG_ENDIAN) | |
4930 | u16 reserved1; | |
4931 | u8 reserved0; | |
4932 | struct vf_pf_channel_zone_trigger vf_pf_channel; | |
4933 | #elif defined(__LITTLE_ENDIAN) | |
4934 | struct vf_pf_channel_zone_trigger vf_pf_channel; | |
4935 | u8 reserved0; | |
4936 | u16 reserved1; | |
4937 | #endif | |
4938 | u32 reserved2; | |
bb2a0f7a YG |
4939 | }; |
4940 | ||
a2fbb9ea | 4941 | /* |
619c5cb6 | 4942 | * zone B per-VF data |
a2fbb9ea | 4943 | */ |
619c5cb6 VZ |
4944 | struct cstorm_vf_zone_data { |
4945 | struct non_trigger_vf_zone non_trigger; | |
4946 | struct trigger_vf_zone trigger; | |
a2fbb9ea ET |
4947 | }; |
4948 | ||
619c5cb6 | 4949 | |
a2fbb9ea | 4950 | /* |
619c5cb6 | 4951 | * Dynamic host coalescing init parameters, per state machine |
a2fbb9ea | 4952 | */ |
619c5cb6 VZ |
4953 | struct dynamic_hc_sm_config { |
4954 | u32 threshold[3]; | |
4955 | u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; | |
4956 | u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; | |
4957 | u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; | |
4958 | u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; | |
4959 | u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; | |
a2fbb9ea ET |
4960 | }; |
4961 | ||
de832a55 | 4962 | /* |
619c5cb6 | 4963 | * Dynamic host coalescing init parameters |
de832a55 | 4964 | */ |
619c5cb6 VZ |
4965 | struct dynamic_hc_config { |
4966 | struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; | |
4967 | }; | |
4968 | ||
4969 | ||
4970 | struct e2_integ_data { | |
4971 | #if defined(__BIG_ENDIAN) | |
4972 | u8 flags; | |
4973 | #define E2_INTEG_DATA_TESTING_EN (0x1<<0) | |
4974 | #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 | |
4975 | #define E2_INTEG_DATA_LB_TX (0x1<<1) | |
4976 | #define E2_INTEG_DATA_LB_TX_SHIFT 1 | |
4977 | #define E2_INTEG_DATA_COS_TX (0x1<<2) | |
4978 | #define E2_INTEG_DATA_COS_TX_SHIFT 2 | |
4979 | #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) | |
4980 | #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 | |
4981 | #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) | |
4982 | #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 | |
4983 | #define E2_INTEG_DATA_RESERVED (0x7<<5) | |
4984 | #define E2_INTEG_DATA_RESERVED_SHIFT 5 | |
4985 | u8 cos; | |
4986 | u8 voq; | |
4987 | u8 pbf_queue; | |
4988 | #elif defined(__LITTLE_ENDIAN) | |
4989 | u8 pbf_queue; | |
4990 | u8 voq; | |
4991 | u8 cos; | |
4992 | u8 flags; | |
4993 | #define E2_INTEG_DATA_TESTING_EN (0x1<<0) | |
4994 | #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 | |
4995 | #define E2_INTEG_DATA_LB_TX (0x1<<1) | |
4996 | #define E2_INTEG_DATA_LB_TX_SHIFT 1 | |
4997 | #define E2_INTEG_DATA_COS_TX (0x1<<2) | |
4998 | #define E2_INTEG_DATA_COS_TX_SHIFT 2 | |
4999 | #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) | |
5000 | #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 | |
5001 | #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) | |
5002 | #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 | |
5003 | #define E2_INTEG_DATA_RESERVED (0x7<<5) | |
5004 | #define E2_INTEG_DATA_RESERVED_SHIFT 5 | |
5005 | #endif | |
5006 | #if defined(__BIG_ENDIAN) | |
5007 | u16 reserved3; | |
5008 | u8 reserved2; | |
5009 | u8 ramEn; | |
5010 | #elif defined(__LITTLE_ENDIAN) | |
5011 | u8 ramEn; | |
5012 | u8 reserved2; | |
5013 | u16 reserved3; | |
5014 | #endif | |
de832a55 EG |
5015 | }; |
5016 | ||
619c5cb6 | 5017 | |
de832a55 | 5018 | /* |
619c5cb6 | 5019 | * set mac event data |
de832a55 | 5020 | */ |
619c5cb6 VZ |
5021 | struct eth_event_data { |
5022 | u32 echo; | |
5023 | u32 reserved0; | |
5024 | u32 reserved1; | |
de832a55 EG |
5025 | }; |
5026 | ||
619c5cb6 | 5027 | |
a2fbb9ea | 5028 | /* |
619c5cb6 | 5029 | * pf-vf event data |
a2fbb9ea | 5030 | */ |
619c5cb6 VZ |
5031 | struct vf_pf_event_data { |
5032 | u8 vf_id; | |
5033 | u8 reserved0; | |
5034 | u16 reserved1; | |
5035 | u32 msg_addr_lo; | |
5036 | u32 msg_addr_hi; | |
a2fbb9ea ET |
5037 | }; |
5038 | ||
619c5cb6 VZ |
5039 | /* |
5040 | * VF FLR event data | |
5041 | */ | |
5042 | struct vf_flr_event_data { | |
5043 | u8 vf_id; | |
5044 | u8 reserved0; | |
5045 | u16 reserved1; | |
5046 | u32 reserved2; | |
5047 | u32 reserved3; | |
5048 | }; | |
a2fbb9ea | 5049 | |
523224a3 | 5050 | /* |
619c5cb6 | 5051 | * malicious VF event data |
523224a3 | 5052 | */ |
619c5cb6 VZ |
5053 | struct malicious_vf_event_data { |
5054 | u8 vf_id; | |
91226790 | 5055 | u8 err_id; |
619c5cb6 | 5056 | u16 reserved1; |
523224a3 | 5057 | u32 reserved2; |
619c5cb6 | 5058 | u32 reserved3; |
523224a3 DK |
5059 | }; |
5060 | ||
a3348722 BW |
5061 | /* |
5062 | * vif list event data | |
5063 | */ | |
5064 | struct vif_list_event_data { | |
5065 | u8 func_bit_map; | |
5066 | u8 echo; | |
5067 | __le16 reserved0; | |
5068 | __le32 reserved1; | |
5069 | __le32 reserved2; | |
5070 | }; | |
5071 | ||
babc6727 MS |
5072 | /* function update event data */ |
5073 | struct function_update_event_data { | |
5074 | u8 echo; | |
5075 | u8 reserved; | |
5076 | __le16 reserved0; | |
5077 | __le32 reserved1; | |
5078 | __le32 reserved2; | |
5079 | }; | |
5080 | ||
5081 | ||
5082 | /* union for all event ring message types */ | |
523224a3 | 5083 | union event_data { |
619c5cb6 VZ |
5084 | struct vf_pf_event_data vf_pf_event; |
5085 | struct eth_event_data eth_event; | |
523224a3 | 5086 | struct cfc_del_event_data cfc_del_event; |
619c5cb6 VZ |
5087 | struct vf_flr_event_data vf_flr_event; |
5088 | struct malicious_vf_event_data malicious_vf_event; | |
a3348722 | 5089 | struct vif_list_event_data vif_list_event; |
babc6727 | 5090 | struct function_update_event_data function_update_event; |
523224a3 DK |
5091 | }; |
5092 | ||
5093 | ||
5094 | /* | |
5095 | * per PF event ring data | |
5096 | */ | |
5097 | struct event_ring_data { | |
86564c3f | 5098 | struct regpair_native base_addr; |
523224a3 DK |
5099 | #if defined(__BIG_ENDIAN) |
5100 | u8 index_id; | |
5101 | u8 sb_id; | |
5102 | u16 producer; | |
5103 | #elif defined(__LITTLE_ENDIAN) | |
5104 | u16 producer; | |
5105 | u8 sb_id; | |
5106 | u8 index_id; | |
5107 | #endif | |
5108 | u32 reserved0; | |
5109 | }; | |
5110 | ||
5111 | ||
5112 | /* | |
5113 | * event ring message element (each element is 128 bits) | |
5114 | */ | |
5115 | struct event_ring_msg { | |
5116 | u8 opcode; | |
619c5cb6 | 5117 | u8 error; |
523224a3 DK |
5118 | u16 reserved1; |
5119 | union event_data data; | |
5120 | }; | |
5121 | ||
5122 | /* | |
5123 | * event ring next page element (128 bits) | |
5124 | */ | |
5125 | struct event_ring_next { | |
5126 | struct regpair addr; | |
5127 | u32 reserved[2]; | |
5128 | }; | |
5129 | ||
5130 | /* | |
5131 | * union for event ring element types (each element is 128 bits) | |
5132 | */ | |
5133 | union event_ring_elem { | |
5134 | struct event_ring_msg message; | |
5135 | struct event_ring_next next_page; | |
5136 | }; | |
5137 | ||
5138 | ||
619c5cb6 VZ |
5139 | /* |
5140 | * Common event ring opcodes | |
5141 | */ | |
5142 | enum event_ring_opcode { | |
5143 | EVENT_RING_OPCODE_VF_PF_CHANNEL, | |
5144 | EVENT_RING_OPCODE_FUNCTION_START, | |
5145 | EVENT_RING_OPCODE_FUNCTION_STOP, | |
5146 | EVENT_RING_OPCODE_CFC_DEL, | |
5147 | EVENT_RING_OPCODE_CFC_DEL_WB, | |
5148 | EVENT_RING_OPCODE_STAT_QUERY, | |
5149 | EVENT_RING_OPCODE_STOP_TRAFFIC, | |
5150 | EVENT_RING_OPCODE_START_TRAFFIC, | |
5151 | EVENT_RING_OPCODE_VF_FLR, | |
5152 | EVENT_RING_OPCODE_MALICIOUS_VF, | |
5153 | EVENT_RING_OPCODE_FORWARD_SETUP, | |
5154 | EVENT_RING_OPCODE_RSS_UPDATE_RULES, | |
621b4d66 | 5155 | EVENT_RING_OPCODE_FUNCTION_UPDATE, |
a3348722 | 5156 | EVENT_RING_OPCODE_AFEX_VIF_LISTS, |
619c5cb6 VZ |
5157 | EVENT_RING_OPCODE_SET_MAC, |
5158 | EVENT_RING_OPCODE_CLASSIFICATION_RULES, | |
5159 | EVENT_RING_OPCODE_FILTERS_RULES, | |
5160 | EVENT_RING_OPCODE_MULTICAST_RULES, | |
91226790 | 5161 | EVENT_RING_OPCODE_SET_TIMESYNC, |
619c5cb6 VZ |
5162 | MAX_EVENT_RING_OPCODE |
5163 | }; | |
5164 | ||
619c5cb6 VZ |
5165 | /* |
5166 | * Modes for fairness algorithm | |
5167 | */ | |
5168 | enum fairness_mode { | |
5169 | FAIRNESS_COS_WRR_MODE, | |
5170 | FAIRNESS_COS_ETS_MODE, | |
5171 | MAX_FAIRNESS_MODE | |
5172 | }; | |
5173 | ||
5174 | ||
619c5cb6 VZ |
5175 | /* |
5176 | * Priority and cos | |
5177 | */ | |
5178 | struct priority_cos { | |
5179 | u8 priority; | |
5180 | u8 cos; | |
5181 | __le16 reserved1; | |
5182 | }; | |
5183 | ||
e4901dde VZ |
5184 | /* |
5185 | * The data for flow control configuration | |
5186 | */ | |
5187 | struct flow_control_configuration { | |
619c5cb6 | 5188 | struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; |
e4901dde VZ |
5189 | u8 dcb_enabled; |
5190 | u8 dcb_version; | |
619c5cb6 VZ |
5191 | u8 dont_add_pri_0_en; |
5192 | u8 reserved1; | |
5193 | __le32 reserved2; | |
5194 | }; | |
5195 | ||
5196 | ||
5197 | /* | |
5198 | * | |
5199 | */ | |
5200 | struct function_start_data { | |
96bed4b9 | 5201 | u8 function_mode; |
91226790 | 5202 | u8 allow_npar_tx_switching; |
619c5cb6 | 5203 | __le16 sd_vlan_tag; |
a3348722 | 5204 | __le16 vif_id; |
619c5cb6 VZ |
5205 | u8 path_id; |
5206 | u8 network_cos_mode; | |
91226790 DK |
5207 | u8 dmae_cmd_id; |
5208 | u8 gre_tunnel_mode; | |
5209 | u8 gre_tunnel_rss; | |
5210 | u8 nvgre_clss_en; | |
5211 | __le16 reserved1[2]; | |
e4901dde VZ |
5212 | }; |
5213 | ||
a3348722 BW |
5214 | struct function_update_data { |
5215 | u8 vif_id_change_flg; | |
5216 | u8 afex_default_vlan_change_flg; | |
5217 | u8 allowed_priorities_change_flg; | |
5218 | u8 network_cos_mode_change_flg; | |
5219 | __le16 vif_id; | |
5220 | __le16 afex_default_vlan; | |
5221 | u8 allowed_priorities; | |
5222 | u8 network_cos_mode; | |
91226790 | 5223 | u8 lb_mode_en_change_flg; |
a3348722 | 5224 | u8 lb_mode_en; |
babc6727 MS |
5225 | u8 tx_switch_suspend_change_flg; |
5226 | u8 tx_switch_suspend; | |
5227 | u8 echo; | |
91226790 DK |
5228 | u8 reserved1; |
5229 | u8 update_gre_cfg_flg; | |
5230 | u8 gre_tunnel_mode; | |
5231 | u8 gre_tunnel_rss; | |
5232 | u8 nvgre_clss_en; | |
5233 | u32 reserved3; | |
a3348722 BW |
5234 | }; |
5235 | ||
a2fbb9ea ET |
5236 | /* |
5237 | * FW version stored in the Xstorm RAM | |
5238 | */ | |
5239 | struct fw_version { | |
5240 | #if defined(__BIG_ENDIAN) | |
8d9c5f34 EG |
5241 | u8 engineering; |
5242 | u8 revision; | |
5243 | u8 minor; | |
5244 | u8 major; | |
a2fbb9ea | 5245 | #elif defined(__LITTLE_ENDIAN) |
8d9c5f34 EG |
5246 | u8 major; |
5247 | u8 minor; | |
5248 | u8 revision; | |
5249 | u8 engineering; | |
a2fbb9ea ET |
5250 | #endif |
5251 | u32 flags; | |
5252 | #define FW_VERSION_OPTIMIZED (0x1<<0) | |
5253 | #define FW_VERSION_OPTIMIZED_SHIFT 0 | |
5254 | #define FW_VERSION_BIG_ENDIEN (0x1<<1) | |
5255 | #define FW_VERSION_BIG_ENDIEN_SHIFT 1 | |
34f80b04 EG |
5256 | #define FW_VERSION_CHIP_VERSION (0x3<<2) |
5257 | #define FW_VERSION_CHIP_VERSION_SHIFT 2 | |
5258 | #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) | |
5259 | #define __FW_VERSION_RESERVED_SHIFT 4 | |
a2fbb9ea ET |
5260 | }; |
5261 | ||
91226790 DK |
5262 | /* GRE RSS Mode */ |
5263 | enum gre_rss_mode { | |
5264 | GRE_OUTER_HEADERS_RSS, | |
5265 | GRE_INNER_HEADERS_RSS, | |
5266 | NVGRE_KEY_ENTROPY_RSS, | |
5267 | MAX_GRE_RSS_MODE | |
5268 | }; | |
5269 | ||
5270 | /* GRE Tunnel Mode */ | |
5271 | enum gre_tunnel_type { | |
5272 | NO_GRE_TUNNEL, | |
5273 | NVGRE_TUNNEL, | |
5274 | L2GRE_TUNNEL, | |
5275 | IPGRE_TUNNEL, | |
5276 | MAX_GRE_TUNNEL_TYPE | |
5277 | }; | |
a2fbb9ea | 5278 | |
523224a3 DK |
5279 | /* |
5280 | * Dynamic Host-Coalescing - Driver(host) counters | |
5281 | */ | |
5282 | struct hc_dynamic_sb_drv_counters { | |
5283 | u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; | |
5284 | }; | |
5285 | ||
5286 | ||
5287 | /* | |
5288 | * 2 bytes. configuration/state parameters for a single protocol index | |
5289 | */ | |
5290 | struct hc_index_data { | |
5291 | #if defined(__BIG_ENDIAN) | |
5292 | u8 flags; | |
5293 | #define HC_INDEX_DATA_SM_ID (0x1<<0) | |
5294 | #define HC_INDEX_DATA_SM_ID_SHIFT 0 | |
5295 | #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) | |
5296 | #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 | |
5297 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) | |
5298 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 | |
5299 | #define HC_INDEX_DATA_RESERVE (0x1F<<3) | |
5300 | #define HC_INDEX_DATA_RESERVE_SHIFT 3 | |
5301 | u8 timeout; | |
5302 | #elif defined(__LITTLE_ENDIAN) | |
5303 | u8 timeout; | |
5304 | u8 flags; | |
5305 | #define HC_INDEX_DATA_SM_ID (0x1<<0) | |
5306 | #define HC_INDEX_DATA_SM_ID_SHIFT 0 | |
5307 | #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) | |
5308 | #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 | |
5309 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) | |
5310 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 | |
5311 | #define HC_INDEX_DATA_RESERVE (0x1F<<3) | |
5312 | #define HC_INDEX_DATA_RESERVE_SHIFT 3 | |
5313 | #endif | |
5314 | }; | |
5315 | ||
5316 | ||
5317 | /* | |
5318 | * HC state-machine | |
5319 | */ | |
5320 | struct hc_status_block_sm { | |
5321 | #if defined(__BIG_ENDIAN) | |
5322 | u8 igu_seg_id; | |
5323 | u8 igu_sb_id; | |
5324 | u8 timer_value; | |
5325 | u8 __flags; | |
5326 | #elif defined(__LITTLE_ENDIAN) | |
5327 | u8 __flags; | |
5328 | u8 timer_value; | |
5329 | u8 igu_sb_id; | |
5330 | u8 igu_seg_id; | |
5331 | #endif | |
5332 | u32 time_to_expire; | |
5333 | }; | |
5334 | ||
5335 | /* | |
5336 | * hold PCI identification variables- used in various places in firmware | |
5337 | */ | |
5338 | struct pci_entity { | |
5339 | #if defined(__BIG_ENDIAN) | |
5340 | u8 vf_valid; | |
5341 | u8 vf_id; | |
5342 | u8 vnic_id; | |
5343 | u8 pf_id; | |
5344 | #elif defined(__LITTLE_ENDIAN) | |
5345 | u8 pf_id; | |
5346 | u8 vnic_id; | |
5347 | u8 vf_id; | |
5348 | u8 vf_valid; | |
5349 | #endif | |
5350 | }; | |
5351 | ||
5352 | /* | |
5353 | * The fast-path status block meta-data, common to all chips | |
5354 | */ | |
5355 | struct hc_sb_data { | |
86564c3f | 5356 | struct regpair_native host_sb_addr; |
523224a3 DK |
5357 | struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; |
5358 | struct pci_entity p_func; | |
5359 | #if defined(__BIG_ENDIAN) | |
5360 | u8 rsrv0; | |
619c5cb6 | 5361 | u8 state; |
523224a3 | 5362 | u8 dhc_qzone_id; |
523224a3 DK |
5363 | u8 same_igu_sb_1b; |
5364 | #elif defined(__LITTLE_ENDIAN) | |
5365 | u8 same_igu_sb_1b; | |
523224a3 | 5366 | u8 dhc_qzone_id; |
619c5cb6 | 5367 | u8 state; |
523224a3 DK |
5368 | u8 rsrv0; |
5369 | #endif | |
86564c3f | 5370 | struct regpair_native rsrv1[2]; |
523224a3 DK |
5371 | }; |
5372 | ||
5373 | ||
619c5cb6 VZ |
5374 | /* |
5375 | * Segment types for host coaslescing | |
5376 | */ | |
5377 | enum hc_segment { | |
5378 | HC_REGULAR_SEGMENT, | |
5379 | HC_DEFAULT_SEGMENT, | |
5380 | MAX_HC_SEGMENT | |
5381 | }; | |
5382 | ||
5383 | ||
523224a3 DK |
5384 | /* |
5385 | * The fast-path status block meta-data | |
5386 | */ | |
5387 | struct hc_sp_status_block_data { | |
86564c3f | 5388 | struct regpair_native host_sb_addr; |
523224a3 | 5389 | #if defined(__BIG_ENDIAN) |
619c5cb6 VZ |
5390 | u8 rsrv1; |
5391 | u8 state; | |
523224a3 DK |
5392 | u8 igu_seg_id; |
5393 | u8 igu_sb_id; | |
5394 | #elif defined(__LITTLE_ENDIAN) | |
5395 | u8 igu_sb_id; | |
5396 | u8 igu_seg_id; | |
619c5cb6 VZ |
5397 | u8 state; |
5398 | u8 rsrv1; | |
523224a3 DK |
5399 | #endif |
5400 | struct pci_entity p_func; | |
5401 | }; | |
5402 | ||
5403 | ||
5404 | /* | |
5405 | * The fast-path status block meta-data | |
5406 | */ | |
5407 | struct hc_status_block_data_e1x { | |
5408 | struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; | |
5409 | struct hc_sb_data common; | |
5410 | }; | |
5411 | ||
5412 | ||
5413 | /* | |
5414 | * The fast-path status block meta-data | |
5415 | */ | |
5416 | struct hc_status_block_data_e2 { | |
5417 | struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; | |
5418 | struct hc_sb_data common; | |
5419 | }; | |
5420 | ||
5421 | ||
619c5cb6 VZ |
5422 | /* |
5423 | * IGU block operartion modes (in Everest2) | |
5424 | */ | |
5425 | enum igu_mode { | |
5426 | HC_IGU_BC_MODE, | |
5427 | HC_IGU_NBC_MODE, | |
5428 | MAX_IGU_MODE | |
5429 | }; | |
5430 | ||
5431 | ||
5432 | /* | |
5433 | * IP versions | |
5434 | */ | |
5435 | enum ip_ver { | |
5436 | IP_V4, | |
5437 | IP_V6, | |
5438 | MAX_IP_VER | |
5439 | }; | |
5440 | ||
91226790 DK |
5441 | /* |
5442 | * Malicious VF error ID | |
5443 | */ | |
5444 | enum malicious_vf_error_id { | |
5445 | VF_PF_CHANNEL_NOT_READY, | |
5446 | ETH_ILLEGAL_BD_LENGTHS, | |
5447 | ETH_PACKET_TOO_SHORT, | |
5448 | ETH_PAYLOAD_TOO_BIG, | |
5449 | ETH_ILLEGAL_ETH_TYPE, | |
5450 | ETH_ILLEGAL_LSO_HDR_LEN, | |
5451 | ETH_TOO_MANY_BDS, | |
5452 | ETH_ZERO_HDR_NBDS, | |
5453 | ETH_START_BD_NOT_SET, | |
5454 | ETH_ILLEGAL_PARSE_NBDS, | |
5455 | ETH_IPV6_AND_CHECKSUM, | |
5456 | ETH_VLAN_FLG_INCORRECT, | |
5457 | ETH_ILLEGAL_LSO_MSS, | |
5458 | ETH_TUNNEL_NOT_SUPPORTED, | |
5459 | MAX_MALICIOUS_VF_ERROR_ID | |
5460 | }; | |
619c5cb6 VZ |
5461 | |
5462 | /* | |
5463 | * Multi-function modes | |
5464 | */ | |
5465 | enum mf_mode { | |
5466 | SINGLE_FUNCTION, | |
5467 | MULTI_FUNCTION_SD, | |
5468 | MULTI_FUNCTION_SI, | |
a3348722 | 5469 | MULTI_FUNCTION_AFEX, |
619c5cb6 VZ |
5470 | MAX_MF_MODE |
5471 | }; | |
5472 | ||
5473 | /* | |
5474 | * Protocol-common statistics collected by the Tstorm (per pf) | |
5475 | */ | |
5476 | struct tstorm_per_pf_stats { | |
5477 | struct regpair rcv_error_bytes; | |
5478 | }; | |
5479 | ||
5480 | /* | |
5481 | * | |
5482 | */ | |
5483 | struct per_pf_stats { | |
5484 | struct tstorm_per_pf_stats tstorm_pf_statistics; | |
5485 | }; | |
5486 | ||
5487 | ||
5488 | /* | |
5489 | * Protocol-common statistics collected by the Tstorm (per port) | |
5490 | */ | |
5491 | struct tstorm_per_port_stats { | |
5492 | __le32 mac_discard; | |
5493 | __le32 mac_filter_discard; | |
5494 | __le32 brb_truncate_discard; | |
5495 | __le32 mf_tag_discard; | |
5496 | __le32 packet_drop; | |
5497 | __le32 reserved; | |
5498 | }; | |
5499 | ||
5500 | /* | |
5501 | * | |
5502 | */ | |
5503 | struct per_port_stats { | |
5504 | struct tstorm_per_port_stats tstorm_port_statistics; | |
5505 | }; | |
5506 | ||
5507 | ||
5508 | /* | |
5509 | * Protocol-common statistics collected by the Tstorm (per client) | |
5510 | */ | |
5511 | struct tstorm_per_queue_stats { | |
5512 | struct regpair rcv_ucast_bytes; | |
5513 | __le32 rcv_ucast_pkts; | |
5514 | __le32 checksum_discard; | |
5515 | struct regpair rcv_bcast_bytes; | |
5516 | __le32 rcv_bcast_pkts; | |
5517 | __le32 pkts_too_big_discard; | |
5518 | struct regpair rcv_mcast_bytes; | |
5519 | __le32 rcv_mcast_pkts; | |
5520 | __le32 ttl0_discard; | |
5521 | __le16 no_buff_discard; | |
5522 | __le16 reserved0; | |
5523 | __le32 reserved1; | |
5524 | }; | |
5525 | ||
5526 | /* | |
5527 | * Protocol-common statistics collected by the Ustorm (per client) | |
5528 | */ | |
5529 | struct ustorm_per_queue_stats { | |
5530 | struct regpair ucast_no_buff_bytes; | |
5531 | struct regpair mcast_no_buff_bytes; | |
5532 | struct regpair bcast_no_buff_bytes; | |
5533 | __le32 ucast_no_buff_pkts; | |
5534 | __le32 mcast_no_buff_pkts; | |
5535 | __le32 bcast_no_buff_pkts; | |
5536 | __le32 coalesced_pkts; | |
5537 | struct regpair coalesced_bytes; | |
5538 | __le32 coalesced_events; | |
5539 | __le32 coalesced_aborts; | |
5540 | }; | |
5541 | ||
5542 | /* | |
5543 | * Protocol-common statistics collected by the Xstorm (per client) | |
5544 | */ | |
5545 | struct xstorm_per_queue_stats { | |
5546 | struct regpair ucast_bytes_sent; | |
5547 | struct regpair mcast_bytes_sent; | |
5548 | struct regpair bcast_bytes_sent; | |
5549 | __le32 ucast_pkts_sent; | |
5550 | __le32 mcast_pkts_sent; | |
5551 | __le32 bcast_pkts_sent; | |
5552 | __le32 error_drop_pkts; | |
5553 | }; | |
5554 | ||
5555 | /* | |
5556 | * | |
5557 | */ | |
5558 | struct per_queue_stats { | |
5559 | struct tstorm_per_queue_stats tstorm_queue_statistics; | |
5560 | struct ustorm_per_queue_stats ustorm_queue_statistics; | |
5561 | struct xstorm_per_queue_stats xstorm_queue_statistics; | |
5562 | }; | |
5563 | ||
5564 | ||
a2fbb9ea ET |
5565 | /* |
5566 | * FW version stored in first line of pram | |
5567 | */ | |
5568 | struct pram_fw_version { | |
8d9c5f34 EG |
5569 | u8 major; |
5570 | u8 minor; | |
5571 | u8 revision; | |
5572 | u8 engineering; | |
a2fbb9ea ET |
5573 | u8 flags; |
5574 | #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) | |
5575 | #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 | |
5576 | #define PRAM_FW_VERSION_STORM_ID (0x3<<1) | |
5577 | #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 | |
5578 | #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) | |
5579 | #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 | |
34f80b04 EG |
5580 | #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) |
5581 | #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 | |
5582 | #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) | |
5583 | #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 | |
5584 | }; | |
5585 | ||
5586 | ||
523224a3 DK |
5587 | /* |
5588 | * Ethernet slow path element | |
5589 | */ | |
5590 | union protocol_common_specific_data { | |
5591 | u8 protocol_data[8]; | |
5592 | struct regpair phy_address; | |
5593 | struct regpair mac_config_addr; | |
a3348722 | 5594 | struct afex_vif_list_ramrod_data afex_vif_list_data; |
523224a3 DK |
5595 | }; |
5596 | ||
ca00392c EG |
5597 | /* |
5598 | * The send queue element | |
5599 | */ | |
5600 | struct protocol_common_spe { | |
5601 | struct spe_hdr hdr; | |
523224a3 | 5602 | union protocol_common_specific_data data; |
ca00392c EG |
5603 | }; |
5604 | ||
a2fbb9ea ET |
5605 | /* |
5606 | * The send queue element | |
5607 | */ | |
5608 | struct slow_path_element { | |
5609 | struct spe_hdr hdr; | |
523224a3 | 5610 | struct regpair protocol_data; |
a2fbb9ea ET |
5611 | }; |
5612 | ||
5613 | ||
5614 | /* | |
619c5cb6 | 5615 | * Protocol-common statistics counter |
a2fbb9ea | 5616 | */ |
619c5cb6 VZ |
5617 | struct stats_counter { |
5618 | __le16 xstats_counter; | |
5619 | __le16 reserved0; | |
5620 | __le32 reserved1; | |
5621 | __le16 tstats_counter; | |
5622 | __le16 reserved2; | |
5623 | __le32 reserved3; | |
5624 | __le16 ustats_counter; | |
5625 | __le16 reserved4; | |
5626 | __le32 reserved5; | |
5627 | __le16 cstats_counter; | |
5628 | __le16 reserved6; | |
5629 | __le32 reserved7; | |
a2fbb9ea ET |
5630 | }; |
5631 | ||
5632 | ||
523224a3 | 5633 | /* |
619c5cb6 | 5634 | * |
523224a3 | 5635 | */ |
619c5cb6 VZ |
5636 | struct stats_query_entry { |
5637 | u8 kind; | |
5638 | u8 index; | |
5639 | __le16 funcID; | |
5640 | __le32 reserved; | |
5641 | struct regpair address; | |
523224a3 DK |
5642 | }; |
5643 | ||
5644 | /* | |
619c5cb6 | 5645 | * statistic command |
523224a3 | 5646 | */ |
619c5cb6 VZ |
5647 | struct stats_query_cmd_group { |
5648 | struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; | |
5649 | }; | |
5650 | ||
5651 | ||
5652 | /* | |
5653 | * statistic command header | |
5654 | */ | |
5655 | struct stats_query_header { | |
5656 | u8 cmd_num; | |
5657 | u8 reserved0; | |
5658 | __le16 drv_stats_counter; | |
5659 | __le32 reserved1; | |
5660 | struct regpair stats_counters_addrs; | |
5661 | }; | |
5662 | ||
5663 | ||
5664 | /* | |
5665 | * Types of statistcis query entry | |
5666 | */ | |
5667 | enum stats_query_type { | |
5668 | STATS_TYPE_QUEUE, | |
5669 | STATS_TYPE_PORT, | |
5670 | STATS_TYPE_PF, | |
5671 | STATS_TYPE_TOE, | |
5672 | STATS_TYPE_FCOE, | |
5673 | MAX_STATS_QUERY_TYPE | |
5674 | }; | |
5675 | ||
5676 | ||
5677 | /* | |
5678 | * Indicate of the function status block state | |
5679 | */ | |
5680 | enum status_block_state { | |
5681 | SB_DISABLED, | |
5682 | SB_ENABLED, | |
5683 | SB_CLEANED, | |
5684 | MAX_STATUS_BLOCK_STATE | |
5685 | }; | |
5686 | ||
5687 | ||
5688 | /* | |
5689 | * Storm IDs (including attentions for IGU related enums) | |
5690 | */ | |
5691 | enum storm_id { | |
5692 | USTORM_ID, | |
5693 | CSTORM_ID, | |
5694 | XSTORM_ID, | |
5695 | TSTORM_ID, | |
5696 | ATTENTION_ID, | |
5697 | MAX_STORM_ID | |
5698 | }; | |
5699 | ||
5700 | ||
5701 | /* | |
5702 | * Taffic types used in ETS and flow control algorithms | |
5703 | */ | |
5704 | enum traffic_type { | |
5705 | LLFC_TRAFFIC_TYPE_NW, | |
5706 | LLFC_TRAFFIC_TYPE_FCOE, | |
5707 | LLFC_TRAFFIC_TYPE_ISCSI, | |
5708 | MAX_TRAFFIC_TYPE | |
523224a3 DK |
5709 | }; |
5710 | ||
5711 | ||
5712 | /* | |
5713 | * zone A per-queue data | |
5714 | */ | |
5715 | struct tstorm_queue_zone_data { | |
5716 | struct regpair reserved[4]; | |
5717 | }; | |
5718 | ||
5719 | ||
5720 | /* | |
5721 | * zone B per-VF data | |
5722 | */ | |
5723 | struct tstorm_vf_zone_data { | |
5724 | struct regpair reserved; | |
5725 | }; | |
5726 | ||
5727 | ||
5728 | /* | |
5729 | * zone A per-queue data | |
5730 | */ | |
5731 | struct ustorm_queue_zone_data { | |
5732 | struct ustorm_eth_rx_producers eth_rx_producers; | |
5733 | struct regpair reserved[3]; | |
5734 | }; | |
5735 | ||
5736 | ||
5737 | /* | |
5738 | * zone B per-VF data | |
5739 | */ | |
5740 | struct ustorm_vf_zone_data { | |
5741 | struct regpair reserved; | |
5742 | }; | |
5743 | ||
5744 | ||
5745 | /* | |
5746 | * data per VF-PF channel | |
5747 | */ | |
5748 | struct vf_pf_channel_data { | |
5749 | #if defined(__BIG_ENDIAN) | |
5750 | u16 reserved0; | |
5751 | u8 valid; | |
5752 | u8 state; | |
5753 | #elif defined(__LITTLE_ENDIAN) | |
5754 | u8 state; | |
5755 | u8 valid; | |
5756 | u16 reserved0; | |
5757 | #endif | |
5758 | u32 reserved1; | |
5759 | }; | |
5760 | ||
5761 | ||
619c5cb6 VZ |
5762 | /* |
5763 | * State of VF-PF channel | |
5764 | */ | |
5765 | enum vf_pf_channel_state { | |
5766 | VF_PF_CHANNEL_STATE_READY, | |
5767 | VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, | |
5768 | MAX_VF_PF_CHANNEL_STATE | |
5769 | }; | |
5770 | ||
5771 | ||
a3348722 BW |
5772 | /* |
5773 | * vif_list_rule_kind | |
5774 | */ | |
5775 | enum vif_list_rule_kind { | |
5776 | VIF_LIST_RULE_SET, | |
5777 | VIF_LIST_RULE_GET, | |
5778 | VIF_LIST_RULE_CLEAR_ALL, | |
5779 | VIF_LIST_RULE_CLEAR_FUNC, | |
5780 | MAX_VIF_LIST_RULE_KIND | |
5781 | }; | |
5782 | ||
5783 | ||
523224a3 DK |
5784 | /* |
5785 | * zone A per-queue data | |
5786 | */ | |
5787 | struct xstorm_queue_zone_data { | |
5788 | struct regpair reserved[4]; | |
5789 | }; | |
5790 | ||
5791 | ||
5792 | /* | |
5793 | * zone B per-VF data | |
5794 | */ | |
5795 | struct xstorm_vf_zone_data { | |
5796 | struct regpair reserved; | |
5797 | }; | |
5798 | ||
5799 | #endif /* BNX2X_HSI_H */ |