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247fa82b | 1 | /* Copyright 2008-2013 Broadcom Corporation |
ea4e040a YR |
2 | * |
3 | * Unless you and Broadcom execute a separate written software license | |
4 | * agreement governing use of this software, this software is licensed to you | |
5 | * under the terms of the GNU General Public License version 2, available | |
6 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
7 | * | |
8 | * Notwithstanding the above, under no circumstances may you combine this | |
9 | * software in any way with any other Broadcom software provided under a | |
10 | * license other than the GPL, without Broadcom's express prior written | |
11 | * consent. | |
12 | * | |
13 | * Written by Yaniv Rosner | |
14 | * | |
15 | */ | |
16 | ||
7995c64e JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
ea4e040a YR |
19 | #include <linux/kernel.h> |
20 | #include <linux/errno.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ethtool.h> | |
25 | #include <linux/mutex.h> | |
ea4e040a | 26 | |
ea4e040a | 27 | #include "bnx2x.h" |
619c5cb6 VZ |
28 | #include "bnx2x_cmn.h" |
29 | ||
669d6996 YR |
30 | typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy, |
31 | struct link_params *params, | |
32 | u8 dev_addr, u16 addr, u8 byte_cnt, | |
33 | u8 *o_buf, u8); | |
ea4e040a | 34 | /********************************************************/ |
3196a88a | 35 | #define ETH_HLEN 14 |
cd88ccee YR |
36 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
37 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
ea4e040a YR |
38 | #define ETH_MIN_PACKET_SIZE 60 |
39 | #define ETH_MAX_PACKET_SIZE 1500 | |
40 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
41 | #define MDIO_ACCESS_TIMEOUT 1000 | |
3c9ada22 YR |
42 | #define WC_LANE_MAX 4 |
43 | #define I2C_SWITCH_WIDTH 2 | |
44 | #define I2C_BSC0 0 | |
45 | #define I2C_BSC1 1 | |
46 | #define I2C_WA_RETRY_CNT 3 | |
50a29845 | 47 | #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) |
3c9ada22 YR |
48 | #define MCPR_IMC_COMMAND_READ_OP 1 |
49 | #define MCPR_IMC_COMMAND_WRITE_OP 2 | |
ea4e040a | 50 | |
26ffaf36 YR |
51 | /* LED Blink rate that will achieve ~15.9Hz */ |
52 | #define LED_BLINK_RATE_VAL_E3 354 | |
53 | #define LED_BLINK_RATE_VAL_E1X_E2 480 | |
ea4e040a | 54 | /***********************************************************/ |
3196a88a | 55 | /* Shortcut definitions */ |
ea4e040a YR |
56 | /***********************************************************/ |
57 | ||
2f904460 EG |
58 | #define NIG_LATCH_BC_ENABLE_MI_INT 0 |
59 | ||
60 | #define NIG_STATUS_EMAC0_MI_INT \ | |
61 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT | |
ea4e040a YR |
62 | #define NIG_STATUS_XGXS0_LINK10G \ |
63 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G | |
64 | #define NIG_STATUS_XGXS0_LINK_STATUS \ | |
65 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS | |
66 | #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ | |
67 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE | |
68 | #define NIG_STATUS_SERDES0_LINK_STATUS \ | |
69 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS | |
70 | #define NIG_MASK_MI_INT \ | |
71 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT | |
72 | #define NIG_MASK_XGXS0_LINK10G \ | |
73 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G | |
74 | #define NIG_MASK_XGXS0_LINK_STATUS \ | |
75 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS | |
76 | #define NIG_MASK_SERDES0_LINK_STATUS \ | |
77 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS | |
78 | ||
79 | #define MDIO_AN_CL73_OR_37_COMPLETE \ | |
80 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ | |
81 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) | |
82 | ||
83 | #define XGXS_RESET_BITS \ | |
84 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ | |
85 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ | |
86 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ | |
87 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ | |
88 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) | |
89 | ||
90 | #define SERDES_RESET_BITS \ | |
91 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ | |
92 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ | |
93 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ | |
94 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) | |
95 | ||
96 | #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 | |
97 | #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 | |
cd88ccee | 98 | #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM |
3196a88a | 99 | #define AUTONEG_PARALLEL \ |
ea4e040a | 100 | SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION |
3196a88a | 101 | #define AUTONEG_SGMII_FIBER_AUTODET \ |
ea4e040a | 102 | SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT |
3196a88a | 103 | #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY |
ea4e040a YR |
104 | |
105 | #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ | |
106 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE | |
107 | #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ | |
108 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE | |
109 | #define GP_STATUS_SPEED_MASK \ | |
110 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK | |
111 | #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M | |
112 | #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M | |
113 | #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G | |
114 | #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G | |
115 | #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G | |
116 | #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G | |
117 | #define GP_STATUS_10G_HIG \ | |
118 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG | |
119 | #define GP_STATUS_10G_CX4 \ | |
120 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 | |
ea4e040a YR |
121 | #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX |
122 | #define GP_STATUS_10G_KX4 \ | |
123 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 | |
3c9ada22 YR |
124 | #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR |
125 | #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI | |
126 | #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS | |
127 | #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI | |
4e7b4997 | 128 | #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 |
cd88ccee YR |
129 | #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD |
130 | #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD | |
ea4e040a | 131 | #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD |
cd88ccee | 132 | #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 |
ea4e040a YR |
133 | #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD |
134 | #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD | |
135 | #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD | |
136 | #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD | |
137 | #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD | |
138 | #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD | |
139 | #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD | |
cd88ccee YR |
140 | #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD |
141 | #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD | |
3c9ada22 YR |
142 | #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD |
143 | #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD | |
6583e33b | 144 | |
4978140c YR |
145 | #define LINK_UPDATE_MASK \ |
146 | (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ | |
147 | LINK_STATUS_LINK_UP | \ | |
148 | LINK_STATUS_PHYSICAL_LINK_FLAG | \ | |
149 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ | |
150 | LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ | |
151 | LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ | |
152 | LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ | |
153 | LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ | |
154 | LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) | |
6583e33b | 155 | |
589abe3a | 156 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 |
cd88ccee | 157 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 |
589abe3a | 158 | #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 |
b807c748 | 159 | #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 |
589abe3a | 160 | |
4d295db0 EG |
161 | |
162 | #define SFP_EEPROM_COMP_CODE_ADDR 0x3 | |
163 | #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) | |
164 | #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) | |
165 | #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) | |
166 | ||
589abe3a EG |
167 | #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 |
168 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 | |
cd88ccee | 169 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 |
4d295db0 | 170 | |
cd88ccee | 171 | #define SFP_EEPROM_OPTIONS_ADDR 0x40 |
589abe3a | 172 | #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 |
cd88ccee | 173 | #define SFP_EEPROM_OPTIONS_SIZE 2 |
589abe3a | 174 | |
cd88ccee YR |
175 | #define EDC_MODE_LINEAR 0x0022 |
176 | #define EDC_MODE_LIMITING 0x0044 | |
177 | #define EDC_MODE_PASSIVE_DAC 0x0055 | |
869952e3 | 178 | #define EDC_MODE_ACTIVE_DAC 0x0066 |
4d295db0 | 179 | |
866cedae | 180 | /* ETS defines*/ |
9380bb9e YR |
181 | #define DCBX_INVALID_COS (0xFF) |
182 | ||
bcab15c5 VZ |
183 | #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) |
184 | #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) | |
9380bb9e YR |
185 | #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) |
186 | #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) | |
187 | #define ETS_E3B0_PBF_MIN_W_VAL (10000) | |
188 | ||
189 | #define MAX_PACKET_SIZE (9700) | |
a9077bfd | 190 | #define MAX_KR_LINK_RETRY 4 |
9380bb9e | 191 | |
ea4e040a YR |
192 | /**********************************************************/ |
193 | /* INTERFACE */ | |
194 | /**********************************************************/ | |
e10bc84d | 195 | |
cd2be89b | 196 | #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
e10bc84d | 197 | bnx2x_cl45_write(_bp, _phy, \ |
7aa0711f | 198 | (_phy)->def_md_devad, \ |
ea4e040a YR |
199 | (_bank + (_addr & 0xf)), \ |
200 | _val) | |
201 | ||
cd2be89b | 202 | #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
e10bc84d | 203 | bnx2x_cl45_read(_bp, _phy, \ |
7aa0711f | 204 | (_phy)->def_md_devad, \ |
ea4e040a YR |
205 | (_bank + (_addr & 0xf)), \ |
206 | _val) | |
207 | ||
ea4e040a YR |
208 | static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) |
209 | { | |
210 | u32 val = REG_RD(bp, reg); | |
211 | ||
212 | val |= bits; | |
213 | REG_WR(bp, reg, val); | |
214 | return val; | |
215 | } | |
216 | ||
217 | static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) | |
218 | { | |
219 | u32 val = REG_RD(bp, reg); | |
220 | ||
221 | val &= ~bits; | |
222 | REG_WR(bp, reg, val); | |
223 | return val; | |
224 | } | |
225 | ||
d3a8f13b YR |
226 | /* |
227 | * bnx2x_check_lfa - This function checks if link reinitialization is required, | |
228 | * or link flap can be avoided. | |
229 | * | |
230 | * @params: link parameters | |
231 | * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed | |
232 | * condition code. | |
233 | */ | |
234 | static int bnx2x_check_lfa(struct link_params *params) | |
235 | { | |
236 | u32 link_status, cfg_idx, lfa_mask, cfg_size; | |
237 | u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; | |
238 | u32 saved_val, req_val, eee_status; | |
239 | struct bnx2x *bp = params->bp; | |
240 | ||
241 | additional_config = | |
242 | REG_RD(bp, params->lfa_base + | |
243 | offsetof(struct shmem_lfa, additional_config)); | |
244 | ||
245 | /* NOTE: must be first condition checked - | |
246 | * to verify DCC bit is cleared in any case! | |
247 | */ | |
248 | if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { | |
249 | DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); | |
250 | REG_WR(bp, params->lfa_base + | |
251 | offsetof(struct shmem_lfa, additional_config), | |
252 | additional_config & ~NO_LFA_DUE_TO_DCC_MASK); | |
253 | return LFA_DCC_LFA_DISABLED; | |
254 | } | |
255 | ||
256 | /* Verify that link is up */ | |
257 | link_status = REG_RD(bp, params->shmem_base + | |
258 | offsetof(struct shmem_region, | |
259 | port_mb[params->port].link_status)); | |
260 | if (!(link_status & LINK_STATUS_LINK_UP)) | |
261 | return LFA_LINK_DOWN; | |
262 | ||
c63da990 BW |
263 | /* if loaded after BOOT from SAN, don't flap the link in any case and |
264 | * rely on link set by preboot driver | |
265 | */ | |
266 | if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN) | |
267 | return 0; | |
268 | ||
d3a8f13b YR |
269 | /* Verify that loopback mode is not set */ |
270 | if (params->loopback_mode) | |
271 | return LFA_LOOPBACK_ENABLED; | |
272 | ||
273 | /* Verify that MFW supports LFA */ | |
274 | if (!params->lfa_base) | |
275 | return LFA_MFW_IS_TOO_OLD; | |
276 | ||
277 | if (params->num_phys == 3) { | |
278 | cfg_size = 2; | |
279 | lfa_mask = 0xffffffff; | |
280 | } else { | |
281 | cfg_size = 1; | |
282 | lfa_mask = 0xffff; | |
283 | } | |
284 | ||
285 | /* Compare Duplex */ | |
286 | saved_val = REG_RD(bp, params->lfa_base + | |
287 | offsetof(struct shmem_lfa, req_duplex)); | |
288 | req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); | |
289 | if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { | |
290 | DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", | |
291 | (saved_val & lfa_mask), (req_val & lfa_mask)); | |
292 | return LFA_DUPLEX_MISMATCH; | |
293 | } | |
294 | /* Compare Flow Control */ | |
295 | saved_val = REG_RD(bp, params->lfa_base + | |
296 | offsetof(struct shmem_lfa, req_flow_ctrl)); | |
297 | req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); | |
298 | if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { | |
299 | DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", | |
300 | (saved_val & lfa_mask), (req_val & lfa_mask)); | |
301 | return LFA_FLOW_CTRL_MISMATCH; | |
302 | } | |
303 | /* Compare Link Speed */ | |
304 | saved_val = REG_RD(bp, params->lfa_base + | |
305 | offsetof(struct shmem_lfa, req_line_speed)); | |
306 | req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); | |
307 | if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { | |
308 | DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", | |
309 | (saved_val & lfa_mask), (req_val & lfa_mask)); | |
310 | return LFA_LINK_SPEED_MISMATCH; | |
311 | } | |
312 | ||
313 | for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { | |
314 | cur_speed_cap_mask = REG_RD(bp, params->lfa_base + | |
315 | offsetof(struct shmem_lfa, | |
316 | speed_cap_mask[cfg_idx])); | |
317 | ||
318 | if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { | |
319 | DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", | |
320 | cur_speed_cap_mask, | |
321 | params->speed_cap_mask[cfg_idx]); | |
322 | return LFA_SPEED_CAP_MISMATCH; | |
323 | } | |
324 | } | |
325 | ||
326 | cur_req_fc_auto_adv = | |
327 | REG_RD(bp, params->lfa_base + | |
328 | offsetof(struct shmem_lfa, additional_config)) & | |
329 | REQ_FC_AUTO_ADV_MASK; | |
330 | ||
331 | if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { | |
332 | DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", | |
333 | cur_req_fc_auto_adv, params->req_fc_auto_adv); | |
334 | return LFA_FLOW_CTRL_MISMATCH; | |
335 | } | |
336 | ||
337 | eee_status = REG_RD(bp, params->shmem2_base + | |
338 | offsetof(struct shmem2_region, | |
339 | eee_status[params->port])); | |
340 | ||
341 | if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ | |
342 | (params->eee_mode & EEE_MODE_ENABLE_LPI)) || | |
343 | ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ | |
344 | (params->eee_mode & EEE_MODE_ADV_LPI))) { | |
345 | DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, | |
346 | eee_status); | |
347 | return LFA_EEE_MISMATCH; | |
348 | } | |
349 | ||
350 | /* LFA conditions are met */ | |
351 | return 0; | |
352 | } | |
3c9ada22 YR |
353 | /******************************************************************/ |
354 | /* EPIO/GPIO section */ | |
355 | /******************************************************************/ | |
3deb8167 YR |
356 | static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) |
357 | { | |
358 | u32 epio_mask, gp_oenable; | |
359 | *en = 0; | |
360 | /* Sanity check */ | |
361 | if (epio_pin > 31) { | |
362 | DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); | |
363 | return; | |
364 | } | |
365 | ||
366 | epio_mask = 1 << epio_pin; | |
367 | /* Set this EPIO to output */ | |
368 | gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); | |
369 | REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); | |
370 | ||
371 | *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; | |
372 | } | |
3c9ada22 YR |
373 | static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) |
374 | { | |
375 | u32 epio_mask, gp_output, gp_oenable; | |
376 | ||
377 | /* Sanity check */ | |
378 | if (epio_pin > 31) { | |
379 | DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); | |
380 | return; | |
381 | } | |
382 | DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); | |
383 | epio_mask = 1 << epio_pin; | |
384 | /* Set this EPIO to output */ | |
385 | gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); | |
386 | if (en) | |
387 | gp_output |= epio_mask; | |
388 | else | |
389 | gp_output &= ~epio_mask; | |
390 | ||
391 | REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); | |
392 | ||
393 | /* Set the value for this EPIO */ | |
394 | gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); | |
395 | REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); | |
396 | } | |
397 | ||
398 | static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) | |
399 | { | |
400 | if (pin_cfg == PIN_CFG_NA) | |
401 | return; | |
402 | if (pin_cfg >= PIN_CFG_EPIO0) { | |
403 | bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); | |
404 | } else { | |
405 | u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; | |
406 | u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; | |
407 | bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); | |
408 | } | |
409 | } | |
410 | ||
3deb8167 YR |
411 | static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) |
412 | { | |
413 | if (pin_cfg == PIN_CFG_NA) | |
414 | return -EINVAL; | |
415 | if (pin_cfg >= PIN_CFG_EPIO0) { | |
416 | bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); | |
417 | } else { | |
418 | u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; | |
419 | u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; | |
420 | *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); | |
421 | } | |
422 | return 0; | |
423 | ||
424 | } | |
bcab15c5 VZ |
425 | /******************************************************************/ |
426 | /* ETS section */ | |
427 | /******************************************************************/ | |
6c3218c6 | 428 | static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) |
bcab15c5 VZ |
429 | { |
430 | /* ETS disabled configuration*/ | |
431 | struct bnx2x *bp = params->bp; | |
432 | ||
6c3218c6 | 433 | DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); |
bcab15c5 | 434 | |
8f73f0b9 | 435 | /* mapping between entry priority to client number (0,1,2 -debug and |
bcab15c5 VZ |
436 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) |
437 | * 3bits client num. | |
438 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
439 | * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 | |
440 | */ | |
441 | ||
442 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); | |
8f73f0b9 | 443 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
bcab15c5 VZ |
444 | * as strict. Bits 0,1,2 - debug and management entries, 3 - |
445 | * COS0 entry, 4 - COS1 entry. | |
446 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT | |
447 | * bit4 bit3 bit2 bit1 bit0 | |
448 | * MCP and debug are strict | |
449 | */ | |
450 | ||
451 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); | |
452 | /* defines which entries (clients) are subjected to WFQ arbitration */ | |
453 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); | |
8f73f0b9 | 454 | /* For strict priority entries defines the number of consecutive |
2cf7acf9 YR |
455 | * slots for the highest priority. |
456 | */ | |
bcab15c5 | 457 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); |
8f73f0b9 | 458 | /* mapping between the CREDIT_WEIGHT registers and actual client |
bcab15c5 VZ |
459 | * numbers |
460 | */ | |
461 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); | |
462 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); | |
463 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); | |
464 | ||
465 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); | |
466 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); | |
467 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); | |
468 | /* ETS mode disable */ | |
469 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); | |
8f73f0b9 | 470 | /* If ETS mode is enabled (there is no strict priority) defines a WFQ |
bcab15c5 VZ |
471 | * weight for COS0/COS1. |
472 | */ | |
473 | REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); | |
474 | REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); | |
475 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ | |
476 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); | |
477 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); | |
478 | /* Defines the number of consecutive slots for the strict priority */ | |
479 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); | |
480 | } | |
6c3218c6 YR |
481 | /****************************************************************************** |
482 | * Description: | |
483 | * Getting min_w_val will be set according to line speed . | |
484 | *. | |
485 | ******************************************************************************/ | |
486 | static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) | |
487 | { | |
488 | u32 min_w_val = 0; | |
489 | /* Calculate min_w_val.*/ | |
490 | if (vars->link_up) { | |
de0396f4 | 491 | if (vars->line_speed == SPEED_20000) |
6c3218c6 YR |
492 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; |
493 | else | |
494 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; | |
495 | } else | |
496 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; | |
8f73f0b9 YR |
497 | /* If the link isn't up (static configuration for example ) The |
498 | * link will be according to 20GBPS. | |
499 | */ | |
6c3218c6 YR |
500 | return min_w_val; |
501 | } | |
502 | /****************************************************************************** | |
503 | * Description: | |
504 | * Getting credit upper bound form min_w_val. | |
505 | *. | |
506 | ******************************************************************************/ | |
507 | static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) | |
508 | { | |
509 | const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), | |
510 | MAX_PACKET_SIZE); | |
511 | return credit_upper_bound; | |
512 | } | |
513 | /****************************************************************************** | |
514 | * Description: | |
515 | * Set credit upper bound for NIG. | |
516 | *. | |
517 | ******************************************************************************/ | |
518 | static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( | |
519 | const struct link_params *params, | |
520 | const u32 min_w_val) | |
521 | { | |
522 | struct bnx2x *bp = params->bp; | |
523 | const u8 port = params->port; | |
524 | const u32 credit_upper_bound = | |
525 | bnx2x_ets_get_credit_upper_bound(min_w_val); | |
526 | ||
527 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : | |
528 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); | |
529 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : | |
530 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); | |
531 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : | |
532 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); | |
533 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : | |
534 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); | |
535 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : | |
536 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); | |
537 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : | |
538 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); | |
539 | ||
de0396f4 | 540 | if (!port) { |
6c3218c6 YR |
541 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, |
542 | credit_upper_bound); | |
543 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, | |
544 | credit_upper_bound); | |
545 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, | |
546 | credit_upper_bound); | |
547 | } | |
548 | } | |
549 | /****************************************************************************** | |
550 | * Description: | |
551 | * Will return the NIG ETS registers to init values.Except | |
552 | * credit_upper_bound. | |
553 | * That isn't used in this configuration (No WFQ is enabled) and will be | |
554 | * configured acording to spec | |
555 | *. | |
556 | ******************************************************************************/ | |
557 | static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, | |
558 | const struct link_vars *vars) | |
559 | { | |
560 | struct bnx2x *bp = params->bp; | |
561 | const u8 port = params->port; | |
562 | const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); | |
8f73f0b9 | 563 | /* Mapping between entry priority to client number (0,1,2 -debug and |
6c3218c6 YR |
564 | * management clients, 3 - COS0 client, 4 - COS1, ... 8 - |
565 | * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by | |
566 | * reset value or init tool | |
567 | */ | |
568 | if (port) { | |
569 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); | |
570 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); | |
571 | } else { | |
572 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); | |
573 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); | |
574 | } | |
8f73f0b9 YR |
575 | /* For strict priority entries defines the number of consecutive |
576 | * slots for the highest priority. | |
577 | */ | |
6c3218c6 YR |
578 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : |
579 | NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); | |
8f73f0b9 | 580 | /* Mapping between the CREDIT_WEIGHT registers and actual client |
6c3218c6 YR |
581 | * numbers |
582 | */ | |
6c3218c6 YR |
583 | if (port) { |
584 | /*Port 1 has 6 COS*/ | |
585 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); | |
586 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); | |
587 | } else { | |
588 | /*Port 0 has 9 COS*/ | |
589 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, | |
590 | 0x43210876); | |
591 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); | |
592 | } | |
593 | ||
8f73f0b9 | 594 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
6c3218c6 YR |
595 | * as strict. Bits 0,1,2 - debug and management entries, 3 - |
596 | * COS0 entry, 4 - COS1 entry. | |
597 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT | |
598 | * bit4 bit3 bit2 bit1 bit0 | |
599 | * MCP and debug are strict | |
600 | */ | |
601 | if (port) | |
602 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); | |
603 | else | |
604 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); | |
605 | /* defines which entries (clients) are subjected to WFQ arbitration */ | |
606 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : | |
607 | NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); | |
608 | ||
8f73f0b9 YR |
609 | /* Please notice the register address are note continuous and a |
610 | * for here is note appropriate.In 2 port mode port0 only COS0-5 | |
611 | * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 | |
612 | * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT | |
613 | * are never used for WFQ | |
614 | */ | |
6c3218c6 YR |
615 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : |
616 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); | |
617 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : | |
618 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); | |
619 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : | |
620 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); | |
621 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : | |
622 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); | |
623 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : | |
624 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); | |
625 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : | |
626 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); | |
de0396f4 | 627 | if (!port) { |
6c3218c6 YR |
628 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); |
629 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); | |
630 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); | |
631 | } | |
632 | ||
633 | bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); | |
634 | } | |
635 | /****************************************************************************** | |
636 | * Description: | |
637 | * Set credit upper bound for PBF. | |
638 | *. | |
639 | ******************************************************************************/ | |
640 | static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( | |
641 | const struct link_params *params, | |
642 | const u32 min_w_val) | |
643 | { | |
644 | struct bnx2x *bp = params->bp; | |
645 | const u32 credit_upper_bound = | |
646 | bnx2x_ets_get_credit_upper_bound(min_w_val); | |
647 | const u8 port = params->port; | |
648 | u32 base_upper_bound = 0; | |
649 | u8 max_cos = 0; | |
650 | u8 i = 0; | |
8f73f0b9 YR |
651 | /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 |
652 | * port mode port1 has COS0-2 that can be used for WFQ. | |
653 | */ | |
de0396f4 | 654 | if (!port) { |
6c3218c6 YR |
655 | base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; |
656 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; | |
657 | } else { | |
658 | base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; | |
659 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; | |
660 | } | |
661 | ||
662 | for (i = 0; i < max_cos; i++) | |
663 | REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); | |
664 | } | |
665 | ||
666 | /****************************************************************************** | |
667 | * Description: | |
668 | * Will return the PBF ETS registers to init values.Except | |
669 | * credit_upper_bound. | |
670 | * That isn't used in this configuration (No WFQ is enabled) and will be | |
671 | * configured acording to spec | |
672 | *. | |
673 | ******************************************************************************/ | |
674 | static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) | |
675 | { | |
676 | struct bnx2x *bp = params->bp; | |
677 | const u8 port = params->port; | |
678 | const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; | |
679 | u8 i = 0; | |
680 | u32 base_weight = 0; | |
681 | u8 max_cos = 0; | |
682 | ||
8f73f0b9 | 683 | /* Mapping between entry priority to client number 0 - COS0 |
6c3218c6 YR |
684 | * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. |
685 | * TODO_ETS - Should be done by reset value or init tool | |
686 | */ | |
687 | if (port) | |
688 | /* 0x688 (|011|0 10|00 1|000) */ | |
689 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); | |
690 | else | |
691 | /* (10 1|100 |011|0 10|00 1|000) */ | |
692 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); | |
693 | ||
694 | /* TODO_ETS - Should be done by reset value or init tool */ | |
695 | if (port) | |
696 | /* 0x688 (|011|0 10|00 1|000)*/ | |
697 | REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); | |
698 | else | |
699 | /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ | |
700 | REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); | |
701 | ||
702 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : | |
703 | PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); | |
704 | ||
705 | ||
706 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : | |
707 | PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); | |
708 | ||
709 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : | |
710 | PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); | |
8f73f0b9 YR |
711 | /* In 2 port mode port0 has COS0-5 that can be used for WFQ. |
712 | * In 4 port mode port1 has COS0-2 that can be used for WFQ. | |
713 | */ | |
de0396f4 | 714 | if (!port) { |
6c3218c6 YR |
715 | base_weight = PBF_REG_COS0_WEIGHT_P0; |
716 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; | |
717 | } else { | |
718 | base_weight = PBF_REG_COS0_WEIGHT_P1; | |
719 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; | |
720 | } | |
721 | ||
722 | for (i = 0; i < max_cos; i++) | |
723 | REG_WR(bp, base_weight + (0x4 * i), 0); | |
724 | ||
725 | bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); | |
726 | } | |
727 | /****************************************************************************** | |
728 | * Description: | |
729 | * E3B0 disable will return basicly the values to init values. | |
730 | *. | |
731 | ******************************************************************************/ | |
732 | static int bnx2x_ets_e3b0_disabled(const struct link_params *params, | |
733 | const struct link_vars *vars) | |
734 | { | |
735 | struct bnx2x *bp = params->bp; | |
736 | ||
737 | if (!CHIP_IS_E3B0(bp)) { | |
94f05b0f JP |
738 | DP(NETIF_MSG_LINK, |
739 | "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); | |
6c3218c6 YR |
740 | return -EINVAL; |
741 | } | |
742 | ||
743 | bnx2x_ets_e3b0_nig_disabled(params, vars); | |
744 | ||
745 | bnx2x_ets_e3b0_pbf_disabled(params); | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
750 | /****************************************************************************** | |
751 | * Description: | |
752 | * Disable will return basicly the values to init values. | |
8f73f0b9 | 753 | * |
6c3218c6 YR |
754 | ******************************************************************************/ |
755 | int bnx2x_ets_disabled(struct link_params *params, | |
756 | struct link_vars *vars) | |
757 | { | |
758 | struct bnx2x *bp = params->bp; | |
759 | int bnx2x_status = 0; | |
760 | ||
761 | if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) | |
762 | bnx2x_ets_e2e3a0_disabled(params); | |
763 | else if (CHIP_IS_E3B0(bp)) | |
764 | bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); | |
765 | else { | |
766 | DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); | |
767 | return -EINVAL; | |
768 | } | |
769 | ||
770 | return bnx2x_status; | |
771 | } | |
772 | ||
773 | /****************************************************************************** | |
774 | * Description | |
775 | * Set the COS mappimg to SP and BW until this point all the COS are not | |
776 | * set as SP or BW. | |
777 | ******************************************************************************/ | |
778 | static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, | |
779 | const struct bnx2x_ets_params *ets_params, | |
780 | const u8 cos_sp_bitmap, | |
781 | const u8 cos_bw_bitmap) | |
782 | { | |
783 | struct bnx2x *bp = params->bp; | |
784 | const u8 port = params->port; | |
785 | const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); | |
786 | const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; | |
787 | const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; | |
788 | const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; | |
789 | ||
790 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : | |
791 | NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); | |
792 | ||
793 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : | |
794 | PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); | |
bcab15c5 | 795 | |
6c3218c6 YR |
796 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : |
797 | NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, | |
798 | nig_cli_subject2wfq_bitmap); | |
799 | ||
800 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : | |
801 | PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, | |
802 | pbf_cli_subject2wfq_bitmap); | |
803 | ||
804 | return 0; | |
805 | } | |
806 | ||
807 | /****************************************************************************** | |
808 | * Description: | |
809 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are | |
810 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. | |
811 | ******************************************************************************/ | |
812 | static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, | |
813 | const u8 cos_entry, | |
814 | const u32 min_w_val_nig, | |
815 | const u32 min_w_val_pbf, | |
816 | const u16 total_bw, | |
817 | const u8 bw, | |
818 | const u8 port) | |
819 | { | |
820 | u32 nig_reg_adress_crd_weight = 0; | |
821 | u32 pbf_reg_adress_crd_weight = 0; | |
c482e6c0 YR |
822 | /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ |
823 | const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; | |
824 | const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; | |
6c3218c6 YR |
825 | |
826 | switch (cos_entry) { | |
827 | case 0: | |
828 | nig_reg_adress_crd_weight = | |
829 | (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : | |
830 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; | |
831 | pbf_reg_adress_crd_weight = (port) ? | |
832 | PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; | |
833 | break; | |
834 | case 1: | |
835 | nig_reg_adress_crd_weight = (port) ? | |
836 | NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : | |
837 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; | |
838 | pbf_reg_adress_crd_weight = (port) ? | |
839 | PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; | |
840 | break; | |
841 | case 2: | |
842 | nig_reg_adress_crd_weight = (port) ? | |
843 | NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : | |
844 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; | |
845 | ||
846 | pbf_reg_adress_crd_weight = (port) ? | |
847 | PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; | |
848 | break; | |
849 | case 3: | |
850 | if (port) | |
851 | return -EINVAL; | |
852 | nig_reg_adress_crd_weight = | |
853 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; | |
854 | pbf_reg_adress_crd_weight = | |
855 | PBF_REG_COS3_WEIGHT_P0; | |
856 | break; | |
857 | case 4: | |
858 | if (port) | |
859 | return -EINVAL; | |
860 | nig_reg_adress_crd_weight = | |
861 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; | |
862 | pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; | |
863 | break; | |
864 | case 5: | |
865 | if (port) | |
866 | return -EINVAL; | |
867 | nig_reg_adress_crd_weight = | |
868 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; | |
869 | pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; | |
870 | break; | |
871 | } | |
872 | ||
873 | REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); | |
874 | ||
875 | REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); | |
876 | ||
877 | return 0; | |
878 | } | |
879 | /****************************************************************************** | |
880 | * Description: | |
881 | * Calculate the total BW.A value of 0 isn't legal. | |
8f73f0b9 | 882 | * |
6c3218c6 YR |
883 | ******************************************************************************/ |
884 | static int bnx2x_ets_e3b0_get_total_bw( | |
885 | const struct link_params *params, | |
870516e1 | 886 | struct bnx2x_ets_params *ets_params, |
6c3218c6 YR |
887 | u16 *total_bw) |
888 | { | |
889 | struct bnx2x *bp = params->bp; | |
890 | u8 cos_idx = 0; | |
870516e1 | 891 | u8 is_bw_cos_exist = 0; |
6c3218c6 YR |
892 | |
893 | *total_bw = 0 ; | |
894 | /* Calculate total BW requested */ | |
895 | for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { | |
de0396f4 | 896 | if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { |
870516e1 YR |
897 | is_bw_cos_exist = 1; |
898 | if (!ets_params->cos[cos_idx].params.bw_params.bw) { | |
899 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" | |
900 | "was set to 0\n"); | |
8f73f0b9 | 901 | /* This is to prevent a state when ramrods |
870516e1 | 902 | * can't be sent |
8f73f0b9 | 903 | */ |
870516e1 YR |
904 | ets_params->cos[cos_idx].params.bw_params.bw |
905 | = 1; | |
906 | } | |
c482e6c0 YR |
907 | *total_bw += |
908 | ets_params->cos[cos_idx].params.bw_params.bw; | |
6c3218c6 | 909 | } |
6c3218c6 YR |
910 | } |
911 | ||
c482e6c0 | 912 | /* Check total BW is valid */ |
de0396f4 YR |
913 | if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { |
914 | if (*total_bw == 0) { | |
94f05b0f | 915 | DP(NETIF_MSG_LINK, |
2f751a80 | 916 | "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); |
6c3218c6 YR |
917 | return -EINVAL; |
918 | } | |
94f05b0f | 919 | DP(NETIF_MSG_LINK, |
2f751a80 | 920 | "bnx2x_ets_E3B0_config total BW should be 100\n"); |
8f73f0b9 | 921 | /* We can handle a case whre the BW isn't 100 this can happen |
2f751a80 YR |
922 | * if the TC are joined. |
923 | */ | |
6c3218c6 YR |
924 | } |
925 | return 0; | |
926 | } | |
927 | ||
928 | /****************************************************************************** | |
929 | * Description: | |
930 | * Invalidate all the sp_pri_to_cos. | |
8f73f0b9 | 931 | * |
6c3218c6 YR |
932 | ******************************************************************************/ |
933 | static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) | |
934 | { | |
935 | u8 pri = 0; | |
936 | for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) | |
937 | sp_pri_to_cos[pri] = DCBX_INVALID_COS; | |
938 | } | |
939 | /****************************************************************************** | |
940 | * Description: | |
941 | * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers | |
942 | * according to sp_pri_to_cos. | |
8f73f0b9 | 943 | * |
6c3218c6 YR |
944 | ******************************************************************************/ |
945 | static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, | |
946 | u8 *sp_pri_to_cos, const u8 pri, | |
947 | const u8 cos_entry) | |
948 | { | |
949 | struct bnx2x *bp = params->bp; | |
950 | const u8 port = params->port; | |
951 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
952 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
953 | ||
7e5998aa DC |
954 | if (pri >= max_num_of_cos) { |
955 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " | |
956 | "parameter Illegal strict priority\n"); | |
957 | return -EINVAL; | |
958 | } | |
959 | ||
de0396f4 | 960 | if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { |
6c3218c6 | 961 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " |
94f05b0f | 962 | "parameter There can't be two COS's with " |
6c3218c6 YR |
963 | "the same strict pri\n"); |
964 | return -EINVAL; | |
965 | } | |
966 | ||
6c3218c6 YR |
967 | sp_pri_to_cos[pri] = cos_entry; |
968 | return 0; | |
969 | ||
970 | } | |
971 | ||
972 | /****************************************************************************** | |
973 | * Description: | |
974 | * Returns the correct value according to COS and priority in | |
975 | * the sp_pri_cli register. | |
8f73f0b9 | 976 | * |
6c3218c6 YR |
977 | ******************************************************************************/ |
978 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, | |
979 | const u8 pri_set, | |
980 | const u8 pri_offset, | |
981 | const u8 entry_size) | |
982 | { | |
983 | u64 pri_cli_nig = 0; | |
984 | pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * | |
985 | (pri_set + pri_offset)); | |
986 | ||
987 | return pri_cli_nig; | |
988 | } | |
989 | /****************************************************************************** | |
990 | * Description: | |
991 | * Returns the correct value according to COS and priority in the | |
992 | * sp_pri_cli register for NIG. | |
8f73f0b9 | 993 | * |
6c3218c6 YR |
994 | ******************************************************************************/ |
995 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) | |
996 | { | |
997 | /* MCP Dbg0 and dbg1 are always with higher strict pri*/ | |
998 | const u8 nig_cos_offset = 3; | |
999 | const u8 nig_pri_offset = 3; | |
1000 | ||
1001 | return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, | |
1002 | nig_pri_offset, 4); | |
1003 | ||
1004 | } | |
1005 | /****************************************************************************** | |
1006 | * Description: | |
1007 | * Returns the correct value according to COS and priority in the | |
1008 | * sp_pri_cli register for PBF. | |
8f73f0b9 | 1009 | * |
6c3218c6 YR |
1010 | ******************************************************************************/ |
1011 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) | |
1012 | { | |
1013 | const u8 pbf_cos_offset = 0; | |
1014 | const u8 pbf_pri_offset = 0; | |
1015 | ||
1016 | return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, | |
1017 | pbf_pri_offset, 3); | |
1018 | ||
1019 | } | |
1020 | ||
1021 | /****************************************************************************** | |
1022 | * Description: | |
1023 | * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers | |
1024 | * according to sp_pri_to_cos.(which COS has higher priority) | |
8f73f0b9 | 1025 | * |
6c3218c6 YR |
1026 | ******************************************************************************/ |
1027 | static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, | |
1028 | u8 *sp_pri_to_cos) | |
1029 | { | |
1030 | struct bnx2x *bp = params->bp; | |
1031 | u8 i = 0; | |
1032 | const u8 port = params->port; | |
1033 | /* MCP Dbg0 and dbg1 are always with higher strict pri*/ | |
1034 | u64 pri_cli_nig = 0x210; | |
1035 | u32 pri_cli_pbf = 0x0; | |
1036 | u8 pri_set = 0; | |
1037 | u8 pri_bitmask = 0; | |
1038 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
1039 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
1040 | ||
1041 | u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; | |
1042 | ||
1043 | /* Set all the strict priority first */ | |
1044 | for (i = 0; i < max_num_of_cos; i++) { | |
de0396f4 YR |
1045 | if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { |
1046 | if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { | |
6c3218c6 YR |
1047 | DP(NETIF_MSG_LINK, |
1048 | "bnx2x_ets_e3b0_sp_set_pri_cli_reg " | |
1049 | "invalid cos entry\n"); | |
1050 | return -EINVAL; | |
1051 | } | |
1052 | ||
1053 | pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( | |
1054 | sp_pri_to_cos[i], pri_set); | |
1055 | ||
1056 | pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( | |
1057 | sp_pri_to_cos[i], pri_set); | |
1058 | pri_bitmask = 1 << sp_pri_to_cos[i]; | |
1059 | /* COS is used remove it from bitmap.*/ | |
de0396f4 | 1060 | if (!(pri_bitmask & cos_bit_to_set)) { |
6c3218c6 YR |
1061 | DP(NETIF_MSG_LINK, |
1062 | "bnx2x_ets_e3b0_sp_set_pri_cli_reg " | |
1063 | "invalid There can't be two COS's with" | |
1064 | " the same strict pri\n"); | |
1065 | return -EINVAL; | |
1066 | } | |
1067 | cos_bit_to_set &= ~pri_bitmask; | |
1068 | pri_set++; | |
1069 | } | |
1070 | } | |
1071 | ||
1072 | /* Set all the Non strict priority i= COS*/ | |
1073 | for (i = 0; i < max_num_of_cos; i++) { | |
1074 | pri_bitmask = 1 << i; | |
1075 | /* Check if COS was already used for SP */ | |
1076 | if (pri_bitmask & cos_bit_to_set) { | |
1077 | /* COS wasn't used for SP */ | |
1078 | pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( | |
1079 | i, pri_set); | |
1080 | ||
1081 | pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( | |
1082 | i, pri_set); | |
1083 | /* COS is used remove it from bitmap.*/ | |
1084 | cos_bit_to_set &= ~pri_bitmask; | |
1085 | pri_set++; | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | if (pri_set != max_num_of_cos) { | |
1090 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " | |
1091 | "entries were set\n"); | |
1092 | return -EINVAL; | |
1093 | } | |
1094 | ||
1095 | if (port) { | |
1096 | /* Only 6 usable clients*/ | |
1097 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, | |
1098 | (u32)pri_cli_nig); | |
1099 | ||
1100 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); | |
1101 | } else { | |
1102 | /* Only 9 usable clients*/ | |
1103 | const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); | |
1104 | const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); | |
1105 | ||
1106 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, | |
1107 | pri_cli_nig_lsb); | |
1108 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, | |
1109 | pri_cli_nig_msb); | |
1110 | ||
1111 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); | |
1112 | } | |
1113 | return 0; | |
1114 | } | |
1115 | ||
1116 | /****************************************************************************** | |
1117 | * Description: | |
1118 | * Configure the COS to ETS according to BW and SP settings. | |
1119 | ******************************************************************************/ | |
1120 | int bnx2x_ets_e3b0_config(const struct link_params *params, | |
1121 | const struct link_vars *vars, | |
870516e1 | 1122 | struct bnx2x_ets_params *ets_params) |
6c3218c6 YR |
1123 | { |
1124 | struct bnx2x *bp = params->bp; | |
1125 | int bnx2x_status = 0; | |
1126 | const u8 port = params->port; | |
1127 | u16 total_bw = 0; | |
1128 | const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); | |
1129 | const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; | |
1130 | u8 cos_bw_bitmap = 0; | |
1131 | u8 cos_sp_bitmap = 0; | |
1132 | u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; | |
1133 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
1134 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
1135 | u8 cos_entry = 0; | |
1136 | ||
1137 | if (!CHIP_IS_E3B0(bp)) { | |
94f05b0f JP |
1138 | DP(NETIF_MSG_LINK, |
1139 | "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); | |
6c3218c6 YR |
1140 | return -EINVAL; |
1141 | } | |
1142 | ||
1143 | if ((ets_params->num_of_cos > max_num_of_cos)) { | |
1144 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " | |
1145 | "isn't supported\n"); | |
1146 | return -EINVAL; | |
1147 | } | |
1148 | ||
1149 | /* Prepare sp strict priority parameters*/ | |
1150 | bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); | |
1151 | ||
1152 | /* Prepare BW parameters*/ | |
1153 | bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, | |
1154 | &total_bw); | |
de0396f4 | 1155 | if (bnx2x_status) { |
94f05b0f JP |
1156 | DP(NETIF_MSG_LINK, |
1157 | "bnx2x_ets_E3B0_config get_total_bw failed\n"); | |
6c3218c6 YR |
1158 | return -EINVAL; |
1159 | } | |
1160 | ||
8f73f0b9 | 1161 | /* Upper bound is set according to current link speed (min_w_val |
2f751a80 | 1162 | * should be the same for upper bound and COS credit val). |
6c3218c6 YR |
1163 | */ |
1164 | bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); | |
1165 | bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); | |
1166 | ||
1167 | ||
1168 | for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { | |
1169 | if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { | |
1170 | cos_bw_bitmap |= (1 << cos_entry); | |
8f73f0b9 | 1171 | /* The function also sets the BW in HW(not the mappin |
6c3218c6 YR |
1172 | * yet) |
1173 | */ | |
1174 | bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( | |
1175 | bp, cos_entry, min_w_val_nig, min_w_val_pbf, | |
1176 | total_bw, | |
1177 | ets_params->cos[cos_entry].params.bw_params.bw, | |
1178 | port); | |
1179 | } else if (bnx2x_cos_state_strict == | |
1180 | ets_params->cos[cos_entry].state){ | |
1181 | cos_sp_bitmap |= (1 << cos_entry); | |
1182 | ||
1183 | bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( | |
1184 | params, | |
1185 | sp_pri_to_cos, | |
1186 | ets_params->cos[cos_entry].params.sp_params.pri, | |
1187 | cos_entry); | |
1188 | ||
1189 | } else { | |
94f05b0f JP |
1190 | DP(NETIF_MSG_LINK, |
1191 | "bnx2x_ets_e3b0_config cos state not valid\n"); | |
6c3218c6 YR |
1192 | return -EINVAL; |
1193 | } | |
de0396f4 | 1194 | if (bnx2x_status) { |
94f05b0f JP |
1195 | DP(NETIF_MSG_LINK, |
1196 | "bnx2x_ets_e3b0_config set cos bw failed\n"); | |
6c3218c6 YR |
1197 | return bnx2x_status; |
1198 | } | |
1199 | } | |
1200 | ||
1201 | /* Set SP register (which COS has higher priority) */ | |
1202 | bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, | |
1203 | sp_pri_to_cos); | |
1204 | ||
de0396f4 | 1205 | if (bnx2x_status) { |
94f05b0f JP |
1206 | DP(NETIF_MSG_LINK, |
1207 | "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); | |
6c3218c6 YR |
1208 | return bnx2x_status; |
1209 | } | |
1210 | ||
1211 | /* Set client mapping of BW and strict */ | |
1212 | bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, | |
1213 | cos_sp_bitmap, | |
1214 | cos_bw_bitmap); | |
1215 | ||
de0396f4 | 1216 | if (bnx2x_status) { |
6c3218c6 YR |
1217 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); |
1218 | return bnx2x_status; | |
1219 | } | |
1220 | return 0; | |
1221 | } | |
65a001ba | 1222 | static void bnx2x_ets_bw_limit_common(const struct link_params *params) |
bcab15c5 VZ |
1223 | { |
1224 | /* ETS disabled configuration */ | |
1225 | struct bnx2x *bp = params->bp; | |
1226 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); | |
8f73f0b9 | 1227 | /* Defines which entries (clients) are subjected to WFQ arbitration |
2cf7acf9 YR |
1228 | * COS0 0x8 |
1229 | * COS1 0x10 | |
1230 | */ | |
bcab15c5 | 1231 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); |
8f73f0b9 | 1232 | /* Mapping between the ARB_CREDIT_WEIGHT registers and actual |
2cf7acf9 YR |
1233 | * client numbers (WEIGHT_0 does not actually have to represent |
1234 | * client 0) | |
1235 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
1236 | * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 | |
1237 | */ | |
bcab15c5 VZ |
1238 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); |
1239 | ||
1240 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, | |
1241 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1242 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, | |
1243 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1244 | ||
1245 | /* ETS mode enabled*/ | |
1246 | REG_WR(bp, PBF_REG_ETS_ENABLED, 1); | |
1247 | ||
1248 | /* Defines the number of consecutive slots for the strict priority */ | |
1249 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); | |
8f73f0b9 | 1250 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
2cf7acf9 YR |
1251 | * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 |
1252 | * entry, 4 - COS1 entry. | |
1253 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT | |
1254 | * bit4 bit3 bit2 bit1 bit0 | |
1255 | * MCP and debug are strict | |
1256 | */ | |
bcab15c5 VZ |
1257 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); |
1258 | ||
1259 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ | |
1260 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, | |
1261 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1262 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, | |
1263 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1264 | } | |
1265 | ||
1266 | void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, | |
1267 | const u32 cos1_bw) | |
1268 | { | |
1269 | /* ETS disabled configuration*/ | |
1270 | struct bnx2x *bp = params->bp; | |
1271 | const u32 total_bw = cos0_bw + cos1_bw; | |
1272 | u32 cos0_credit_weight = 0; | |
1273 | u32 cos1_credit_weight = 0; | |
1274 | ||
1275 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); | |
1276 | ||
de0396f4 YR |
1277 | if ((!total_bw) || |
1278 | (!cos0_bw) || | |
1279 | (!cos1_bw)) { | |
cd88ccee | 1280 | DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); |
bcab15c5 VZ |
1281 | return; |
1282 | } | |
1283 | ||
1284 | cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ | |
1285 | total_bw; | |
1286 | cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ | |
1287 | total_bw; | |
1288 | ||
1289 | bnx2x_ets_bw_limit_common(params); | |
1290 | ||
1291 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); | |
1292 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); | |
1293 | ||
1294 | REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); | |
1295 | REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); | |
1296 | } | |
1297 | ||
fcf5b650 | 1298 | int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) |
bcab15c5 VZ |
1299 | { |
1300 | /* ETS disabled configuration*/ | |
1301 | struct bnx2x *bp = params->bp; | |
1302 | u32 val = 0; | |
1303 | ||
bcab15c5 | 1304 | DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); |
8f73f0b9 | 1305 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
bcab15c5 VZ |
1306 | * as strict. Bits 0,1,2 - debug and management entries, |
1307 | * 3 - COS0 entry, 4 - COS1 entry. | |
1308 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT | |
1309 | * bit4 bit3 bit2 bit1 bit0 | |
1310 | * MCP and debug are strict | |
1311 | */ | |
1312 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); | |
8f73f0b9 | 1313 | /* For strict priority entries defines the number of consecutive slots |
bcab15c5 VZ |
1314 | * for the highest priority. |
1315 | */ | |
1316 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); | |
1317 | /* ETS mode disable */ | |
1318 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); | |
1319 | /* Defines the number of consecutive slots for the strict priority */ | |
1320 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); | |
1321 | ||
1322 | /* Defines the number of consecutive slots for the strict priority */ | |
1323 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); | |
1324 | ||
8f73f0b9 | 1325 | /* Mapping between entry priority to client number (0,1,2 -debug and |
2cf7acf9 YR |
1326 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) |
1327 | * 3bits client num. | |
1328 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
1329 | * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 | |
1330 | * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 | |
1331 | */ | |
de0396f4 | 1332 | val = (!strict_cos) ? 0x2318 : 0x22E0; |
bcab15c5 VZ |
1333 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); |
1334 | ||
1335 | return 0; | |
1336 | } | |
c8c60d88 | 1337 | |
bcab15c5 | 1338 | /******************************************************************/ |
e8920674 | 1339 | /* PFC section */ |
bcab15c5 | 1340 | /******************************************************************/ |
9380bb9e YR |
1341 | static void bnx2x_update_pfc_xmac(struct link_params *params, |
1342 | struct link_vars *vars, | |
1343 | u8 is_lb) | |
1344 | { | |
1345 | struct bnx2x *bp = params->bp; | |
1346 | u32 xmac_base; | |
1347 | u32 pause_val, pfc0_val, pfc1_val; | |
1348 | ||
1349 | /* XMAC base adrr */ | |
1350 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1351 | ||
1352 | /* Initialize pause and pfc registers */ | |
1353 | pause_val = 0x18000; | |
1354 | pfc0_val = 0xFFFF8000; | |
1355 | pfc1_val = 0x2; | |
1356 | ||
1357 | /* No PFC support */ | |
1358 | if (!(params->feature_config_flags & | |
1359 | FEATURE_CONFIG_PFC_ENABLED)) { | |
1360 | ||
8f73f0b9 | 1361 | /* RX flow control - Process pause frame in receive direction |
9380bb9e YR |
1362 | */ |
1363 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) | |
1364 | pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; | |
1365 | ||
8f73f0b9 | 1366 | /* TX flow control - Send pause packet when buffer is full */ |
9380bb9e YR |
1367 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
1368 | pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; | |
1369 | } else {/* PFC support */ | |
1370 | pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | | |
1371 | XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | | |
1372 | XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | | |
27d9129f YR |
1373 | XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | |
1374 | XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; | |
1375 | /* Write pause and PFC registers */ | |
1376 | REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); | |
1377 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); | |
1378 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); | |
1379 | pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; | |
1380 | ||
9380bb9e YR |
1381 | } |
1382 | ||
1383 | /* Write pause and PFC registers */ | |
1384 | REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); | |
1385 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); | |
1386 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); | |
1387 | ||
9380bb9e | 1388 | |
b8d6d082 YR |
1389 | /* Set MAC address for source TX Pause/PFC frames */ |
1390 | REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, | |
1391 | ((params->mac_addr[2] << 24) | | |
1392 | (params->mac_addr[3] << 16) | | |
1393 | (params->mac_addr[4] << 8) | | |
1394 | (params->mac_addr[5]))); | |
1395 | REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, | |
1396 | ((params->mac_addr[0] << 8) | | |
1397 | (params->mac_addr[1]))); | |
9380bb9e | 1398 | |
b8d6d082 YR |
1399 | udelay(30); |
1400 | } | |
bcab15c5 | 1401 | |
bcab15c5 | 1402 | |
bcab15c5 VZ |
1403 | static void bnx2x_emac_get_pfc_stat(struct link_params *params, |
1404 | u32 pfc_frames_sent[2], | |
1405 | u32 pfc_frames_received[2]) | |
1406 | { | |
1407 | /* Read pfc statistic */ | |
1408 | struct bnx2x *bp = params->bp; | |
1409 | u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1410 | u32 val_xon = 0; | |
1411 | u32 val_xoff = 0; | |
1412 | ||
1413 | DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n"); | |
1414 | ||
1415 | /* PFC received frames */ | |
1416 | val_xoff = REG_RD(bp, emac_base + | |
1417 | EMAC_REG_RX_PFC_STATS_XOFF_RCVD); | |
1418 | val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; | |
1419 | val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); | |
1420 | val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; | |
1421 | ||
1422 | pfc_frames_received[0] = val_xon + val_xoff; | |
1423 | ||
1424 | /* PFC received sent */ | |
1425 | val_xoff = REG_RD(bp, emac_base + | |
1426 | EMAC_REG_RX_PFC_STATS_XOFF_SENT); | |
1427 | val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; | |
1428 | val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); | |
1429 | val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; | |
1430 | ||
1431 | pfc_frames_sent[0] = val_xon + val_xoff; | |
1432 | } | |
1433 | ||
b8d6d082 | 1434 | /* Read pfc statistic*/ |
bcab15c5 VZ |
1435 | void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars, |
1436 | u32 pfc_frames_sent[2], | |
1437 | u32 pfc_frames_received[2]) | |
1438 | { | |
1439 | /* Read pfc statistic */ | |
1440 | struct bnx2x *bp = params->bp; | |
b8d6d082 | 1441 | |
bcab15c5 VZ |
1442 | DP(NETIF_MSG_LINK, "pfc statistic\n"); |
1443 | ||
1444 | if (!vars->link_up) | |
1445 | return; | |
1446 | ||
de0396f4 | 1447 | if (vars->mac_type == MAC_TYPE_EMAC) { |
b8d6d082 | 1448 | DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n"); |
bcab15c5 VZ |
1449 | bnx2x_emac_get_pfc_stat(params, pfc_frames_sent, |
1450 | pfc_frames_received); | |
bcab15c5 VZ |
1451 | } |
1452 | } | |
1453 | /******************************************************************/ | |
1454 | /* MAC/PBF section */ | |
1455 | /******************************************************************/ | |
55386fe8 YR |
1456 | static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, |
1457 | u32 emac_base) | |
a198c142 | 1458 | { |
55386fe8 YR |
1459 | u32 new_mode, cur_mode; |
1460 | u32 clc_cnt; | |
8f73f0b9 | 1461 | /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz |
a198c142 YR |
1462 | * (a value of 49==0x31) and make sure that the AUTO poll is off |
1463 | */ | |
55386fe8 | 1464 | cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); |
a198c142 | 1465 | |
3c9ada22 | 1466 | if (USES_WARPCORE(bp)) |
55386fe8 | 1467 | clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; |
3c9ada22 | 1468 | else |
55386fe8 | 1469 | clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; |
a198c142 | 1470 | |
55386fe8 YR |
1471 | if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && |
1472 | (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) | |
1473 | return; | |
1474 | ||
1475 | new_mode = cur_mode & | |
1476 | ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); | |
1477 | new_mode |= clc_cnt; | |
1478 | new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); | |
a198c142 | 1479 | |
55386fe8 YR |
1480 | DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n", |
1481 | cur_mode, new_mode); | |
1482 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); | |
a198c142 YR |
1483 | udelay(40); |
1484 | } | |
55386fe8 YR |
1485 | |
1486 | static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp, | |
1487 | struct link_params *params) | |
1488 | { | |
1489 | u8 phy_index; | |
1490 | /* Set mdio clock per phy */ | |
1491 | for (phy_index = INT_PHY; phy_index < params->num_phys; | |
1492 | phy_index++) | |
1493 | bnx2x_set_mdio_clk(bp, params->chip_id, | |
1494 | params->phy[phy_index].mdio_ctrl); | |
1495 | } | |
1496 | ||
2f751a80 YR |
1497 | static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) |
1498 | { | |
1499 | u32 port4mode_ovwr_val; | |
1500 | /* Check 4-port override enabled */ | |
1501 | port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); | |
1502 | if (port4mode_ovwr_val & (1<<0)) { | |
1503 | /* Return 4-port mode override value */ | |
1504 | return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); | |
1505 | } | |
1506 | /* Return 4-port mode from input pin */ | |
1507 | return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
1508 | } | |
a198c142 | 1509 | |
ea4e040a | 1510 | static void bnx2x_emac_init(struct link_params *params, |
cd88ccee | 1511 | struct link_vars *vars) |
ea4e040a YR |
1512 | { |
1513 | /* reset and unreset the emac core */ | |
1514 | struct bnx2x *bp = params->bp; | |
1515 | u8 port = params->port; | |
1516 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1517 | u32 val; | |
1518 | u16 timeout; | |
1519 | ||
1520 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
cd88ccee | 1521 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
ea4e040a YR |
1522 | udelay(5); |
1523 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
cd88ccee | 1524 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
ea4e040a YR |
1525 | |
1526 | /* init emac - use read-modify-write */ | |
1527 | /* self clear reset */ | |
1528 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
3196a88a | 1529 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); |
ea4e040a YR |
1530 | |
1531 | timeout = 200; | |
3196a88a | 1532 | do { |
ea4e040a YR |
1533 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); |
1534 | DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); | |
1535 | if (!timeout) { | |
1536 | DP(NETIF_MSG_LINK, "EMAC timeout!\n"); | |
1537 | return; | |
1538 | } | |
1539 | timeout--; | |
3196a88a | 1540 | } while (val & EMAC_MODE_RESET); |
55386fe8 YR |
1541 | |
1542 | bnx2x_set_mdio_emac_per_phy(bp, params); | |
ea4e040a YR |
1543 | /* Set mac address */ |
1544 | val = ((params->mac_addr[0] << 8) | | |
1545 | params->mac_addr[1]); | |
3196a88a | 1546 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); |
ea4e040a YR |
1547 | |
1548 | val = ((params->mac_addr[2] << 24) | | |
1549 | (params->mac_addr[3] << 16) | | |
1550 | (params->mac_addr[4] << 8) | | |
1551 | params->mac_addr[5]); | |
3196a88a | 1552 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); |
ea4e040a YR |
1553 | } |
1554 | ||
9380bb9e YR |
1555 | static void bnx2x_set_xumac_nig(struct link_params *params, |
1556 | u16 tx_pause_en, | |
1557 | u8 enable) | |
1558 | { | |
1559 | struct bnx2x *bp = params->bp; | |
1560 | ||
1561 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, | |
1562 | enable); | |
1563 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, | |
1564 | enable); | |
1565 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : | |
1566 | NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); | |
1567 | } | |
1568 | ||
d3a8f13b | 1569 | static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en) |
ce7c0489 YR |
1570 | { |
1571 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
d3a8f13b | 1572 | u32 val; |
ce7c0489 YR |
1573 | struct bnx2x *bp = params->bp; |
1574 | if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & | |
1575 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) | |
1576 | return; | |
d3a8f13b YR |
1577 | val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); |
1578 | if (en) | |
1579 | val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | | |
1580 | UMAC_COMMAND_CONFIG_REG_RX_ENA); | |
1581 | else | |
1582 | val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | | |
1583 | UMAC_COMMAND_CONFIG_REG_RX_ENA); | |
ce7c0489 | 1584 | /* Disable RX and TX */ |
d3a8f13b | 1585 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
ce7c0489 YR |
1586 | } |
1587 | ||
9380bb9e YR |
1588 | static void bnx2x_umac_enable(struct link_params *params, |
1589 | struct link_vars *vars, u8 lb) | |
1590 | { | |
1591 | u32 val; | |
1592 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1593 | struct bnx2x *bp = params->bp; | |
1594 | /* Reset UMAC */ | |
1595 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1596 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); | |
d231023e | 1597 | usleep_range(1000, 2000); |
9380bb9e YR |
1598 | |
1599 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1600 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); | |
1601 | ||
1602 | DP(NETIF_MSG_LINK, "enabling UMAC\n"); | |
1603 | ||
9380bb9e YR |
1604 | /* This register opens the gate for the UMAC despite its name */ |
1605 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); | |
1606 | ||
1607 | val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | | |
1608 | UMAC_COMMAND_CONFIG_REG_PAD_EN | | |
1609 | UMAC_COMMAND_CONFIG_REG_SW_RESET | | |
1610 | UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; | |
1611 | switch (vars->line_speed) { | |
1612 | case SPEED_10: | |
1613 | val |= (0<<2); | |
1614 | break; | |
1615 | case SPEED_100: | |
1616 | val |= (1<<2); | |
1617 | break; | |
1618 | case SPEED_1000: | |
1619 | val |= (2<<2); | |
1620 | break; | |
1621 | case SPEED_2500: | |
1622 | val |= (3<<2); | |
1623 | break; | |
1624 | default: | |
1625 | DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", | |
1626 | vars->line_speed); | |
1627 | break; | |
1628 | } | |
9d5b36be YR |
1629 | if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) |
1630 | val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; | |
1631 | ||
1632 | if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
1633 | val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; | |
1634 | ||
e18c56b2 MY |
1635 | if (vars->duplex == DUPLEX_HALF) |
1636 | val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; | |
1637 | ||
9380bb9e YR |
1638 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
1639 | udelay(50); | |
1640 | ||
26964bb7 YM |
1641 | /* Configure UMAC for EEE */ |
1642 | if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { | |
1643 | DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); | |
1644 | REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, | |
1645 | UMAC_UMAC_EEE_CTRL_REG_EEE_EN); | |
1646 | REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); | |
1647 | } else { | |
1648 | REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); | |
1649 | } | |
1650 | ||
b8d6d082 YR |
1651 | /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ |
1652 | REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, | |
1653 | ((params->mac_addr[2] << 24) | | |
1654 | (params->mac_addr[3] << 16) | | |
1655 | (params->mac_addr[4] << 8) | | |
1656 | (params->mac_addr[5]))); | |
1657 | REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, | |
1658 | ((params->mac_addr[0] << 8) | | |
1659 | (params->mac_addr[1]))); | |
1660 | ||
9380bb9e YR |
1661 | /* Enable RX and TX */ |
1662 | val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; | |
1663 | val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | | |
3c9ada22 | 1664 | UMAC_COMMAND_CONFIG_REG_RX_ENA; |
9380bb9e YR |
1665 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
1666 | udelay(50); | |
1667 | ||
1668 | /* Remove SW Reset */ | |
1669 | val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; | |
1670 | ||
1671 | /* Check loopback mode */ | |
1672 | if (lb) | |
1673 | val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; | |
1674 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); | |
1675 | ||
8f73f0b9 | 1676 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame |
9380bb9e YR |
1677 | * length used by the MAC receive logic to check frames. |
1678 | */ | |
1679 | REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); | |
1680 | bnx2x_set_xumac_nig(params, | |
1681 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); | |
1682 | vars->mac_type = MAC_TYPE_UMAC; | |
1683 | ||
1684 | } | |
1685 | ||
9380bb9e | 1686 | /* Define the XMAC mode */ |
ce7c0489 | 1687 | static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) |
9380bb9e | 1688 | { |
ce7c0489 | 1689 | struct bnx2x *bp = params->bp; |
9380bb9e YR |
1690 | u32 is_port4mode = bnx2x_is_4_port_mode(bp); |
1691 | ||
8f73f0b9 | 1692 | /* In 4-port mode, need to set the mode only once, so if XMAC is |
2f751a80 YR |
1693 | * already out of reset, it means the mode has already been set, |
1694 | * and it must not* reset the XMAC again, since it controls both | |
1695 | * ports of the path | |
1696 | */ | |
9380bb9e | 1697 | |
4e7b4997 YR |
1698 | if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || |
1699 | (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || | |
1700 | (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) && | |
1701 | is_port4mode && | |
ce7c0489 | 1702 | (REG_RD(bp, MISC_REG_RESET_REG_2) & |
9380bb9e | 1703 | MISC_REGISTERS_RESET_REG_2_XMAC)) { |
94f05b0f JP |
1704 | DP(NETIF_MSG_LINK, |
1705 | "XMAC already out of reset in 4-port mode\n"); | |
9380bb9e YR |
1706 | return; |
1707 | } | |
1708 | ||
1709 | /* Hard reset */ | |
1710 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1711 | MISC_REGISTERS_RESET_REG_2_XMAC); | |
d231023e | 1712 | usleep_range(1000, 2000); |
9380bb9e YR |
1713 | |
1714 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1715 | MISC_REGISTERS_RESET_REG_2_XMAC); | |
1716 | if (is_port4mode) { | |
1717 | DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); | |
1718 | ||
8f73f0b9 | 1719 | /* Set the number of ports on the system side to up to 2 */ |
9380bb9e YR |
1720 | REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); |
1721 | ||
1722 | /* Set the number of ports on the Warp Core to 10G */ | |
1723 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); | |
1724 | } else { | |
8f73f0b9 | 1725 | /* Set the number of ports on the system side to 1 */ |
9380bb9e YR |
1726 | REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); |
1727 | if (max_speed == SPEED_10000) { | |
94f05b0f JP |
1728 | DP(NETIF_MSG_LINK, |
1729 | "Init XMAC to 10G x 1 port per path\n"); | |
9380bb9e YR |
1730 | /* Set the number of ports on the Warp Core to 10G */ |
1731 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); | |
1732 | } else { | |
94f05b0f JP |
1733 | DP(NETIF_MSG_LINK, |
1734 | "Init XMAC to 20G x 2 ports per path\n"); | |
9380bb9e YR |
1735 | /* Set the number of ports on the Warp Core to 20G */ |
1736 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); | |
1737 | } | |
1738 | } | |
1739 | /* Soft reset */ | |
1740 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1741 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); | |
d231023e | 1742 | usleep_range(1000, 2000); |
9380bb9e YR |
1743 | |
1744 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1745 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); | |
1746 | ||
1747 | } | |
1748 | ||
d3a8f13b | 1749 | static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en) |
9380bb9e YR |
1750 | { |
1751 | u8 port = params->port; | |
1752 | struct bnx2x *bp = params->bp; | |
b5077662 | 1753 | u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; |
d3a8f13b | 1754 | u32 val; |
9380bb9e YR |
1755 | |
1756 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
1757 | MISC_REGISTERS_RESET_REG_2_XMAC) { | |
8f73f0b9 | 1758 | /* Send an indication to change the state in the NIG back to XON |
b5077662 YR |
1759 | * Clearing this bit enables the next set of this bit to get |
1760 | * rising edge | |
1761 | */ | |
1762 | pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); | |
1763 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, | |
1764 | (pfc_ctrl & ~(1<<1))); | |
1765 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, | |
1766 | (pfc_ctrl | (1<<1))); | |
9380bb9e | 1767 | DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); |
d3a8f13b YR |
1768 | val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); |
1769 | if (en) | |
1770 | val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); | |
1771 | else | |
1772 | val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); | |
1773 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); | |
9380bb9e YR |
1774 | } |
1775 | } | |
1776 | ||
1777 | static int bnx2x_xmac_enable(struct link_params *params, | |
1778 | struct link_vars *vars, u8 lb) | |
1779 | { | |
1780 | u32 val, xmac_base; | |
1781 | struct bnx2x *bp = params->bp; | |
1782 | DP(NETIF_MSG_LINK, "enabling XMAC\n"); | |
1783 | ||
1784 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1785 | ||
ce7c0489 | 1786 | bnx2x_xmac_init(params, vars->line_speed); |
9380bb9e | 1787 | |
8f73f0b9 | 1788 | /* This register determines on which events the MAC will assert |
9380bb9e YR |
1789 | * error on the i/f to the NIG along w/ EOP. |
1790 | */ | |
1791 | ||
8f73f0b9 | 1792 | /* This register tells the NIG whether to send traffic to UMAC |
9380bb9e YR |
1793 | * or XMAC |
1794 | */ | |
1795 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); | |
1796 | ||
4e7b4997 YR |
1797 | /* When XMAC is in XLGMII mode, disable sending idles for fault |
1798 | * detection. | |
1799 | */ | |
1800 | if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { | |
1801 | REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, | |
1802 | (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | | |
1803 | XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); | |
1804 | REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); | |
1805 | REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, | |
1806 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | | |
1807 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); | |
1808 | } | |
9380bb9e YR |
1809 | /* Set Max packet size */ |
1810 | REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); | |
1811 | ||
1812 | /* CRC append for Tx packets */ | |
1813 | REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); | |
1814 | ||
1815 | /* update PFC */ | |
1816 | bnx2x_update_pfc_xmac(params, vars, 0); | |
1817 | ||
c8c60d88 YM |
1818 | if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { |
1819 | DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); | |
1820 | REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); | |
1821 | REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); | |
1822 | } else { | |
1823 | REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); | |
1824 | } | |
1825 | ||
9380bb9e YR |
1826 | /* Enable TX and RX */ |
1827 | val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; | |
1828 | ||
4e7b4997 YR |
1829 | /* Set MAC in XLGMII mode for dual-mode */ |
1830 | if ((vars->line_speed == SPEED_20000) && | |
1831 | (params->phy[INT_PHY].supported & | |
1832 | SUPPORTED_20000baseKR2_Full)) | |
1833 | val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; | |
1834 | ||
9380bb9e YR |
1835 | /* Check loopback mode */ |
1836 | if (lb) | |
4d7e25d6 | 1837 | val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; |
9380bb9e YR |
1838 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); |
1839 | bnx2x_set_xumac_nig(params, | |
1840 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); | |
1841 | ||
1842 | vars->mac_type = MAC_TYPE_XMAC; | |
1843 | ||
1844 | return 0; | |
1845 | } | |
2f751a80 | 1846 | |
fcf5b650 | 1847 | static int bnx2x_emac_enable(struct link_params *params, |
9045f6b4 | 1848 | struct link_vars *vars, u8 lb) |
ea4e040a YR |
1849 | { |
1850 | struct bnx2x *bp = params->bp; | |
1851 | u8 port = params->port; | |
1852 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1853 | u32 val; | |
1854 | ||
1855 | DP(NETIF_MSG_LINK, "enabling EMAC\n"); | |
1856 | ||
de6f3377 YR |
1857 | /* Disable BMAC */ |
1858 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1859 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
1860 | ||
ea4e040a YR |
1861 | /* enable emac and not bmac */ |
1862 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); | |
1863 | ||
ea4e040a YR |
1864 | /* ASIC */ |
1865 | if (vars->phy_flags & PHY_XGXS_FLAG) { | |
1866 | u32 ser_lane = ((params->lane_config & | |
cd88ccee YR |
1867 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
1868 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
ea4e040a YR |
1869 | |
1870 | DP(NETIF_MSG_LINK, "XGXS\n"); | |
1871 | /* select the master lanes (out of 0-3) */ | |
cd88ccee | 1872 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); |
ea4e040a | 1873 | /* select XGXS */ |
cd88ccee | 1874 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); |
ea4e040a YR |
1875 | |
1876 | } else { /* SerDes */ | |
1877 | DP(NETIF_MSG_LINK, "SerDes\n"); | |
1878 | /* select SerDes */ | |
cd88ccee | 1879 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); |
ea4e040a YR |
1880 | } |
1881 | ||
811a2f2d | 1882 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, |
cd88ccee | 1883 | EMAC_RX_MODE_RESET); |
811a2f2d | 1884 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, |
cd88ccee | 1885 | EMAC_TX_MODE_RESET); |
ea4e040a | 1886 | |
ea4e040a YR |
1887 | /* pause enable/disable */ |
1888 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, | |
1889 | EMAC_RX_MODE_FLOW_EN); | |
ea4e040a YR |
1890 | |
1891 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
bcab15c5 VZ |
1892 | (EMAC_TX_MODE_EXT_PAUSE_EN | |
1893 | EMAC_TX_MODE_FLOW_EN)); | |
1894 | if (!(params->feature_config_flags & | |
1895 | FEATURE_CONFIG_PFC_ENABLED)) { | |
1896 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) | |
1897 | bnx2x_bits_en(bp, emac_base + | |
1898 | EMAC_REG_EMAC_RX_MODE, | |
1899 | EMAC_RX_MODE_FLOW_EN); | |
1900 | ||
1901 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
1902 | bnx2x_bits_en(bp, emac_base + | |
1903 | EMAC_REG_EMAC_TX_MODE, | |
1904 | (EMAC_TX_MODE_EXT_PAUSE_EN | | |
1905 | EMAC_TX_MODE_FLOW_EN)); | |
1906 | } else | |
1907 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
1908 | EMAC_TX_MODE_FLOW_EN); | |
ea4e040a YR |
1909 | |
1910 | /* KEEP_VLAN_TAG, promiscuous */ | |
1911 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); | |
1912 | val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; | |
bcab15c5 | 1913 | |
8f73f0b9 | 1914 | /* Setting this bit causes MAC control frames (except for pause |
2cf7acf9 YR |
1915 | * frames) to be passed on for processing. This setting has no |
1916 | * affect on the operation of the pause frames. This bit effects | |
1917 | * all packets regardless of RX Parser packet sorting logic. | |
1918 | * Turn the PFC off to make sure we are in Xon state before | |
1919 | * enabling it. | |
1920 | */ | |
bcab15c5 VZ |
1921 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); |
1922 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { | |
1923 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); | |
1924 | /* Enable PFC again */ | |
1925 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, | |
1926 | EMAC_REG_RX_PFC_MODE_RX_EN | | |
1927 | EMAC_REG_RX_PFC_MODE_TX_EN | | |
1928 | EMAC_REG_RX_PFC_MODE_PRIORITIES); | |
1929 | ||
1930 | EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, | |
1931 | ((0x0101 << | |
1932 | EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | | |
1933 | (0x00ff << | |
1934 | EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); | |
1935 | val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; | |
1936 | } | |
3196a88a | 1937 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); |
ea4e040a YR |
1938 | |
1939 | /* Set Loopback */ | |
1940 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
1941 | if (lb) | |
1942 | val |= 0x810; | |
1943 | else | |
1944 | val &= ~0x810; | |
3196a88a | 1945 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); |
ea4e040a | 1946 | |
d231023e | 1947 | /* Enable emac */ |
6c55c3cd EG |
1948 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); |
1949 | ||
d231023e | 1950 | /* Enable emac for jumbo packets */ |
3196a88a | 1951 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, |
ea4e040a YR |
1952 | (EMAC_RX_MTU_SIZE_JUMBO_ENA | |
1953 | (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); | |
1954 | ||
d231023e | 1955 | /* Strip CRC */ |
ea4e040a YR |
1956 | REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); |
1957 | ||
d231023e | 1958 | /* Disable the NIG in/out to the bmac */ |
ea4e040a YR |
1959 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); |
1960 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
1961 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); | |
1962 | ||
d231023e | 1963 | /* Enable the NIG in/out to the emac */ |
ea4e040a YR |
1964 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); |
1965 | val = 0; | |
bcab15c5 VZ |
1966 | if ((params->feature_config_flags & |
1967 | FEATURE_CONFIG_PFC_ENABLED) || | |
1968 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
ea4e040a YR |
1969 | val = 1; |
1970 | ||
1971 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); | |
1972 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); | |
1973 | ||
02a23165 | 1974 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); |
ea4e040a YR |
1975 | |
1976 | vars->mac_type = MAC_TYPE_EMAC; | |
1977 | return 0; | |
1978 | } | |
1979 | ||
bcab15c5 VZ |
1980 | static void bnx2x_update_pfc_bmac1(struct link_params *params, |
1981 | struct link_vars *vars) | |
1982 | { | |
1983 | u32 wb_data[2]; | |
1984 | struct bnx2x *bp = params->bp; | |
1985 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
1986 | NIG_REG_INGRESS_BMAC0_MEM; | |
1987 | ||
1988 | u32 val = 0x14; | |
1989 | if ((!(params->feature_config_flags & | |
1990 | FEATURE_CONFIG_PFC_ENABLED)) && | |
1991 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
1992 | /* Enable BigMAC to react on received Pause packets */ | |
1993 | val |= (1<<5); | |
1994 | wb_data[0] = val; | |
1995 | wb_data[1] = 0; | |
1996 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); | |
1997 | ||
d231023e | 1998 | /* TX control */ |
bcab15c5 VZ |
1999 | val = 0xc0; |
2000 | if (!(params->feature_config_flags & | |
2001 | FEATURE_CONFIG_PFC_ENABLED) && | |
2002 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
2003 | val |= 0x800000; | |
2004 | wb_data[0] = val; | |
2005 | wb_data[1] = 0; | |
2006 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); | |
2007 | } | |
2008 | ||
2009 | static void bnx2x_update_pfc_bmac2(struct link_params *params, | |
2010 | struct link_vars *vars, | |
2011 | u8 is_lb) | |
f2e0899f | 2012 | { |
8f73f0b9 | 2013 | /* Set rx control: Strip CRC and enable BigMAC to relay |
f2e0899f DK |
2014 | * control packets to the system as well |
2015 | */ | |
2016 | u32 wb_data[2]; | |
2017 | struct bnx2x *bp = params->bp; | |
2018 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2019 | NIG_REG_INGRESS_BMAC0_MEM; | |
2020 | u32 val = 0x14; | |
ea4e040a | 2021 | |
bcab15c5 VZ |
2022 | if ((!(params->feature_config_flags & |
2023 | FEATURE_CONFIG_PFC_ENABLED)) && | |
2024 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
f2e0899f DK |
2025 | /* Enable BigMAC to react on received Pause packets */ |
2026 | val |= (1<<5); | |
2027 | wb_data[0] = val; | |
2028 | wb_data[1] = 0; | |
cd88ccee | 2029 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); |
f2e0899f | 2030 | udelay(30); |
ea4e040a | 2031 | |
f2e0899f DK |
2032 | /* Tx control */ |
2033 | val = 0xc0; | |
bcab15c5 VZ |
2034 | if (!(params->feature_config_flags & |
2035 | FEATURE_CONFIG_PFC_ENABLED) && | |
2036 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
f2e0899f DK |
2037 | val |= 0x800000; |
2038 | wb_data[0] = val; | |
2039 | wb_data[1] = 0; | |
bcab15c5 VZ |
2040 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); |
2041 | ||
2042 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { | |
2043 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); | |
2044 | /* Enable PFC RX & TX & STATS and set 8 COS */ | |
2045 | wb_data[0] = 0x0; | |
2046 | wb_data[0] |= (1<<0); /* RX */ | |
2047 | wb_data[0] |= (1<<1); /* TX */ | |
2048 | wb_data[0] |= (1<<2); /* Force initial Xon */ | |
2049 | wb_data[0] |= (1<<3); /* 8 cos */ | |
2050 | wb_data[0] |= (1<<5); /* STATS */ | |
2051 | wb_data[1] = 0; | |
2052 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, | |
2053 | wb_data, 2); | |
2054 | /* Clear the force Xon */ | |
2055 | wb_data[0] &= ~(1<<2); | |
2056 | } else { | |
2057 | DP(NETIF_MSG_LINK, "PFC is disabled\n"); | |
d231023e | 2058 | /* Disable PFC RX & TX & STATS and set 8 COS */ |
bcab15c5 VZ |
2059 | wb_data[0] = 0x8; |
2060 | wb_data[1] = 0; | |
2061 | } | |
2062 | ||
2063 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); | |
f2e0899f | 2064 | |
8f73f0b9 | 2065 | /* Set Time (based unit is 512 bit time) between automatic |
2cf7acf9 YR |
2066 | * re-sending of PP packets amd enable automatic re-send of |
2067 | * Per-Priroity Packet as long as pp_gen is asserted and | |
2068 | * pp_disable is low. | |
2069 | */ | |
f2e0899f | 2070 | val = 0x8000; |
bcab15c5 VZ |
2071 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
2072 | val |= (1<<16); /* enable automatic re-send */ | |
2073 | ||
f2e0899f DK |
2074 | wb_data[0] = val; |
2075 | wb_data[1] = 0; | |
2076 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, | |
cd88ccee | 2077 | wb_data, 2); |
f2e0899f DK |
2078 | |
2079 | /* mac control */ | |
2080 | val = 0x3; /* Enable RX and TX */ | |
2081 | if (is_lb) { | |
2082 | val |= 0x4; /* Local loopback */ | |
2083 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
2084 | } | |
bcab15c5 VZ |
2085 | /* When PFC enabled, Pass pause frames towards the NIG. */ |
2086 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
2087 | val |= ((1<<6)|(1<<5)); | |
f2e0899f DK |
2088 | |
2089 | wb_data[0] = val; | |
2090 | wb_data[1] = 0; | |
cd88ccee | 2091 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
f2e0899f DK |
2092 | } |
2093 | ||
619c5cb6 VZ |
2094 | /****************************************************************************** |
2095 | * Description: | |
2096 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are | |
2097 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. | |
2098 | ******************************************************************************/ | |
d231023e YM |
2099 | static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, |
2100 | u8 cos_entry, | |
2101 | u32 priority_mask, u8 port) | |
619c5cb6 VZ |
2102 | { |
2103 | u32 nig_reg_rx_priority_mask_add = 0; | |
2104 | ||
2105 | switch (cos_entry) { | |
2106 | case 0: | |
2107 | nig_reg_rx_priority_mask_add = (port) ? | |
2108 | NIG_REG_P1_RX_COS0_PRIORITY_MASK : | |
2109 | NIG_REG_P0_RX_COS0_PRIORITY_MASK; | |
2110 | break; | |
2111 | case 1: | |
2112 | nig_reg_rx_priority_mask_add = (port) ? | |
2113 | NIG_REG_P1_RX_COS1_PRIORITY_MASK : | |
2114 | NIG_REG_P0_RX_COS1_PRIORITY_MASK; | |
2115 | break; | |
2116 | case 2: | |
2117 | nig_reg_rx_priority_mask_add = (port) ? | |
2118 | NIG_REG_P1_RX_COS2_PRIORITY_MASK : | |
2119 | NIG_REG_P0_RX_COS2_PRIORITY_MASK; | |
2120 | break; | |
2121 | case 3: | |
2122 | if (port) | |
2123 | return -EINVAL; | |
2124 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; | |
2125 | break; | |
2126 | case 4: | |
2127 | if (port) | |
2128 | return -EINVAL; | |
2129 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; | |
2130 | break; | |
2131 | case 5: | |
2132 | if (port) | |
2133 | return -EINVAL; | |
2134 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; | |
2135 | break; | |
2136 | } | |
2137 | ||
2138 | REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); | |
2139 | ||
2140 | return 0; | |
2141 | } | |
b8d6d082 YR |
2142 | static void bnx2x_update_mng(struct link_params *params, u32 link_status) |
2143 | { | |
2144 | struct bnx2x *bp = params->bp; | |
2145 | ||
2146 | REG_WR(bp, params->shmem_base + | |
2147 | offsetof(struct shmem_region, | |
2148 | port_mb[params->port].link_status), link_status); | |
2149 | } | |
2150 | ||
4e7b4997 YR |
2151 | static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr) |
2152 | { | |
2153 | struct bnx2x *bp = params->bp; | |
2154 | ||
2155 | if (SHMEM2_HAS(bp, link_attr_sync)) | |
2156 | REG_WR(bp, params->shmem2_base + | |
2157 | offsetof(struct shmem2_region, | |
2158 | link_attr_sync[params->port]), link_attr); | |
2159 | } | |
2160 | ||
bcab15c5 VZ |
2161 | static void bnx2x_update_pfc_nig(struct link_params *params, |
2162 | struct link_vars *vars, | |
2163 | struct bnx2x_nig_brb_pfc_port_params *nig_params) | |
2164 | { | |
2165 | u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; | |
127302bb | 2166 | u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; |
bcab15c5 | 2167 | u32 pkt_priority_to_cos = 0; |
bcab15c5 | 2168 | struct bnx2x *bp = params->bp; |
9380bb9e YR |
2169 | u8 port = params->port; |
2170 | ||
bcab15c5 VZ |
2171 | int set_pfc = params->feature_config_flags & |
2172 | FEATURE_CONFIG_PFC_ENABLED; | |
2173 | DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); | |
2174 | ||
8f73f0b9 | 2175 | /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set |
bcab15c5 VZ |
2176 | * MAC control frames (that are not pause packets) |
2177 | * will be forwarded to the XCM. | |
2178 | */ | |
127302bb YR |
2179 | xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : |
2180 | NIG_REG_LLH0_XCM_MASK); | |
8f73f0b9 | 2181 | /* NIG params will override non PFC params, since it's possible to |
bcab15c5 VZ |
2182 | * do transition from PFC to SAFC |
2183 | */ | |
2184 | if (set_pfc) { | |
2185 | pause_enable = 0; | |
2186 | llfc_out_en = 0; | |
2187 | llfc_enable = 0; | |
9380bb9e YR |
2188 | if (CHIP_IS_E3(bp)) |
2189 | ppp_enable = 0; | |
2190 | else | |
503976e9 | 2191 | ppp_enable = 1; |
bcab15c5 VZ |
2192 | xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : |
2193 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
127302bb YR |
2194 | xcm_out_en = 0; |
2195 | hwpfc_enable = 1; | |
bcab15c5 VZ |
2196 | } else { |
2197 | if (nig_params) { | |
2198 | llfc_out_en = nig_params->llfc_out_en; | |
2199 | llfc_enable = nig_params->llfc_enable; | |
2200 | pause_enable = nig_params->pause_enable; | |
8f73f0b9 | 2201 | } else /* Default non PFC mode - PAUSE */ |
bcab15c5 VZ |
2202 | pause_enable = 1; |
2203 | ||
2204 | xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | |
2205 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
127302bb | 2206 | xcm_out_en = 1; |
bcab15c5 VZ |
2207 | } |
2208 | ||
9380bb9e YR |
2209 | if (CHIP_IS_E3(bp)) |
2210 | REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : | |
2211 | NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); | |
bcab15c5 VZ |
2212 | REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : |
2213 | NIG_REG_LLFC_OUT_EN_0, llfc_out_en); | |
2214 | REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : | |
2215 | NIG_REG_LLFC_ENABLE_0, llfc_enable); | |
2216 | REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : | |
2217 | NIG_REG_PAUSE_ENABLE_0, pause_enable); | |
2218 | ||
2219 | REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : | |
2220 | NIG_REG_PPP_ENABLE_0, ppp_enable); | |
2221 | ||
2222 | REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : | |
2223 | NIG_REG_LLH0_XCM_MASK, xcm_mask); | |
2224 | ||
127302bb YR |
2225 | REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : |
2226 | NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); | |
bcab15c5 | 2227 | |
d231023e | 2228 | /* Output enable for RX_XCM # IF */ |
127302bb YR |
2229 | REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : |
2230 | NIG_REG_XCM0_OUT_EN, xcm_out_en); | |
bcab15c5 VZ |
2231 | |
2232 | /* HW PFC TX enable */ | |
127302bb YR |
2233 | REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : |
2234 | NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); | |
bcab15c5 | 2235 | |
bcab15c5 | 2236 | if (nig_params) { |
619c5cb6 | 2237 | u8 i = 0; |
bcab15c5 VZ |
2238 | pkt_priority_to_cos = nig_params->pkt_priority_to_cos; |
2239 | ||
619c5cb6 VZ |
2240 | for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) |
2241 | bnx2x_pfc_nig_rx_priority_mask(bp, i, | |
2242 | nig_params->rx_cos_priority_mask[i], port); | |
bcab15c5 VZ |
2243 | |
2244 | REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : | |
2245 | NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, | |
2246 | nig_params->llfc_high_priority_classes); | |
2247 | ||
2248 | REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : | |
2249 | NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, | |
2250 | nig_params->llfc_low_priority_classes); | |
2251 | } | |
2252 | REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : | |
2253 | NIG_REG_P0_PKT_PRIORITY_TO_COS, | |
2254 | pkt_priority_to_cos); | |
2255 | } | |
2256 | ||
9380bb9e | 2257 | int bnx2x_update_pfc(struct link_params *params, |
bcab15c5 VZ |
2258 | struct link_vars *vars, |
2259 | struct bnx2x_nig_brb_pfc_port_params *pfc_params) | |
2260 | { | |
8f73f0b9 | 2261 | /* The PFC and pause are orthogonal to one another, meaning when |
bcab15c5 VZ |
2262 | * PFC is enabled, the pause are disabled, and when PFC is |
2263 | * disabled, pause are set according to the pause result. | |
2264 | */ | |
2265 | u32 val; | |
2266 | struct bnx2x *bp = params->bp; | |
9380bb9e YR |
2267 | int bnx2x_status = 0; |
2268 | u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); | |
b8d6d082 YR |
2269 | |
2270 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
2271 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
2272 | else | |
2273 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; | |
2274 | ||
2275 | bnx2x_update_mng(params, vars->link_status); | |
2276 | ||
d231023e | 2277 | /* Update NIG params */ |
bcab15c5 VZ |
2278 | bnx2x_update_pfc_nig(params, vars, pfc_params); |
2279 | ||
bcab15c5 | 2280 | if (!vars->link_up) |
9380bb9e | 2281 | return bnx2x_status; |
bcab15c5 VZ |
2282 | |
2283 | DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); | |
375944cb YR |
2284 | |
2285 | if (CHIP_IS_E3(bp)) { | |
2286 | if (vars->mac_type == MAC_TYPE_XMAC) | |
2287 | bnx2x_update_pfc_xmac(params, vars, 0); | |
2288 | } else { | |
9380bb9e YR |
2289 | val = REG_RD(bp, MISC_REG_RESET_REG_2); |
2290 | if ((val & | |
3c9ada22 | 2291 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) |
9380bb9e YR |
2292 | == 0) { |
2293 | DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); | |
2294 | bnx2x_emac_enable(params, vars, 0); | |
2295 | return bnx2x_status; | |
2296 | } | |
9380bb9e YR |
2297 | if (CHIP_IS_E2(bp)) |
2298 | bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); | |
2299 | else | |
2300 | bnx2x_update_pfc_bmac1(params, vars); | |
2301 | ||
2302 | val = 0; | |
2303 | if ((params->feature_config_flags & | |
2304 | FEATURE_CONFIG_PFC_ENABLED) || | |
2305 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
2306 | val = 1; | |
2307 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); | |
2308 | } | |
2309 | return bnx2x_status; | |
bcab15c5 | 2310 | } |
f2e0899f | 2311 | |
fcf5b650 YR |
2312 | static int bnx2x_bmac1_enable(struct link_params *params, |
2313 | struct link_vars *vars, | |
2314 | u8 is_lb) | |
ea4e040a YR |
2315 | { |
2316 | struct bnx2x *bp = params->bp; | |
2317 | u8 port = params->port; | |
2318 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2319 | NIG_REG_INGRESS_BMAC0_MEM; | |
2320 | u32 wb_data[2]; | |
2321 | u32 val; | |
2322 | ||
f2e0899f | 2323 | DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); |
ea4e040a YR |
2324 | |
2325 | /* XGXS control */ | |
2326 | wb_data[0] = 0x3c; | |
2327 | wb_data[1] = 0; | |
cd88ccee YR |
2328 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, |
2329 | wb_data, 2); | |
ea4e040a | 2330 | |
d231023e | 2331 | /* TX MAC SA */ |
ea4e040a YR |
2332 | wb_data[0] = ((params->mac_addr[2] << 24) | |
2333 | (params->mac_addr[3] << 16) | | |
2334 | (params->mac_addr[4] << 8) | | |
2335 | params->mac_addr[5]); | |
2336 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
2337 | params->mac_addr[1]); | |
cd88ccee | 2338 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); |
ea4e040a | 2339 | |
d231023e | 2340 | /* MAC control */ |
ea4e040a YR |
2341 | val = 0x3; |
2342 | if (is_lb) { | |
2343 | val |= 0x4; | |
2344 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
2345 | } | |
2346 | wb_data[0] = val; | |
2347 | wb_data[1] = 0; | |
cd88ccee | 2348 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); |
ea4e040a | 2349 | |
d231023e | 2350 | /* Set rx mtu */ |
ea4e040a YR |
2351 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2352 | wb_data[1] = 0; | |
cd88ccee | 2353 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); |
ea4e040a | 2354 | |
bcab15c5 | 2355 | bnx2x_update_pfc_bmac1(params, vars); |
ea4e040a | 2356 | |
d231023e | 2357 | /* Set tx mtu */ |
ea4e040a YR |
2358 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2359 | wb_data[1] = 0; | |
cd88ccee | 2360 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); |
ea4e040a | 2361 | |
d231023e | 2362 | /* Set cnt max size */ |
ea4e040a YR |
2363 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2364 | wb_data[1] = 0; | |
cd88ccee | 2365 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
ea4e040a | 2366 | |
d231023e | 2367 | /* Configure SAFC */ |
ea4e040a YR |
2368 | wb_data[0] = 0x1000200; |
2369 | wb_data[1] = 0; | |
2370 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, | |
2371 | wb_data, 2); | |
f2e0899f DK |
2372 | |
2373 | return 0; | |
2374 | } | |
2375 | ||
fcf5b650 YR |
2376 | static int bnx2x_bmac2_enable(struct link_params *params, |
2377 | struct link_vars *vars, | |
2378 | u8 is_lb) | |
f2e0899f DK |
2379 | { |
2380 | struct bnx2x *bp = params->bp; | |
2381 | u8 port = params->port; | |
2382 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2383 | NIG_REG_INGRESS_BMAC0_MEM; | |
2384 | u32 wb_data[2]; | |
2385 | ||
2386 | DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); | |
2387 | ||
2388 | wb_data[0] = 0; | |
2389 | wb_data[1] = 0; | |
cd88ccee | 2390 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
f2e0899f DK |
2391 | udelay(30); |
2392 | ||
2393 | /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ | |
2394 | wb_data[0] = 0x3c; | |
2395 | wb_data[1] = 0; | |
cd88ccee YR |
2396 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, |
2397 | wb_data, 2); | |
f2e0899f DK |
2398 | |
2399 | udelay(30); | |
2400 | ||
d231023e | 2401 | /* TX MAC SA */ |
f2e0899f DK |
2402 | wb_data[0] = ((params->mac_addr[2] << 24) | |
2403 | (params->mac_addr[3] << 16) | | |
2404 | (params->mac_addr[4] << 8) | | |
2405 | params->mac_addr[5]); | |
2406 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
2407 | params->mac_addr[1]); | |
2408 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, | |
cd88ccee | 2409 | wb_data, 2); |
f2e0899f DK |
2410 | |
2411 | udelay(30); | |
2412 | ||
2413 | /* Configure SAFC */ | |
2414 | wb_data[0] = 0x1000200; | |
2415 | wb_data[1] = 0; | |
2416 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, | |
cd88ccee | 2417 | wb_data, 2); |
f2e0899f DK |
2418 | udelay(30); |
2419 | ||
d231023e | 2420 | /* Set RX MTU */ |
f2e0899f DK |
2421 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2422 | wb_data[1] = 0; | |
cd88ccee | 2423 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); |
f2e0899f DK |
2424 | udelay(30); |
2425 | ||
d231023e | 2426 | /* Set TX MTU */ |
f2e0899f DK |
2427 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2428 | wb_data[1] = 0; | |
cd88ccee | 2429 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); |
f2e0899f | 2430 | udelay(30); |
d231023e | 2431 | /* Set cnt max size */ |
f2e0899f DK |
2432 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; |
2433 | wb_data[1] = 0; | |
cd88ccee | 2434 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
f2e0899f | 2435 | udelay(30); |
bcab15c5 | 2436 | bnx2x_update_pfc_bmac2(params, vars, is_lb); |
f2e0899f DK |
2437 | |
2438 | return 0; | |
2439 | } | |
2440 | ||
fcf5b650 YR |
2441 | static int bnx2x_bmac_enable(struct link_params *params, |
2442 | struct link_vars *vars, | |
d3a8f13b | 2443 | u8 is_lb, u8 reset_bmac) |
f2e0899f | 2444 | { |
fcf5b650 YR |
2445 | int rc = 0; |
2446 | u8 port = params->port; | |
f2e0899f DK |
2447 | struct bnx2x *bp = params->bp; |
2448 | u32 val; | |
d231023e | 2449 | /* Reset and unreset the BigMac */ |
d3a8f13b YR |
2450 | if (reset_bmac) { |
2451 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
2452 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
2453 | usleep_range(1000, 2000); | |
2454 | } | |
f2e0899f DK |
2455 | |
2456 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
cd88ccee | 2457 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
f2e0899f | 2458 | |
d231023e | 2459 | /* Enable access for bmac registers */ |
f2e0899f DK |
2460 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); |
2461 | ||
2462 | /* Enable BMAC according to BMAC type*/ | |
2463 | if (CHIP_IS_E2(bp)) | |
2464 | rc = bnx2x_bmac2_enable(params, vars, is_lb); | |
2465 | else | |
2466 | rc = bnx2x_bmac1_enable(params, vars, is_lb); | |
ea4e040a YR |
2467 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); |
2468 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); | |
2469 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); | |
2470 | val = 0; | |
bcab15c5 VZ |
2471 | if ((params->feature_config_flags & |
2472 | FEATURE_CONFIG_PFC_ENABLED) || | |
2473 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
ea4e040a YR |
2474 | val = 1; |
2475 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); | |
2476 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); | |
2477 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); | |
2478 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
2479 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); | |
2480 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); | |
2481 | ||
2482 | vars->mac_type = MAC_TYPE_BMAC; | |
f2e0899f | 2483 | return rc; |
ea4e040a YR |
2484 | } |
2485 | ||
d3a8f13b | 2486 | static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) |
ea4e040a YR |
2487 | { |
2488 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
cd88ccee | 2489 | NIG_REG_INGRESS_BMAC0_MEM; |
ea4e040a | 2490 | u32 wb_data[2]; |
3196a88a | 2491 | u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); |
ea4e040a | 2492 | |
d3a8f13b YR |
2493 | if (CHIP_IS_E2(bp)) |
2494 | bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; | |
2495 | else | |
2496 | bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; | |
ea4e040a YR |
2497 | /* Only if the bmac is out of reset */ |
2498 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
2499 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && | |
2500 | nig_bmac_enable) { | |
d3a8f13b YR |
2501 | /* Clear Rx Enable bit in BMAC_CONTROL register */ |
2502 | REG_RD_DMAE(bp, bmac_addr, wb_data, 2); | |
2503 | if (en) | |
2504 | wb_data[0] |= BMAC_CONTROL_RX_ENABLE; | |
2505 | else | |
f2e0899f | 2506 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
d3a8f13b | 2507 | REG_WR_DMAE(bp, bmac_addr, wb_data, 2); |
d231023e | 2508 | usleep_range(1000, 2000); |
ea4e040a YR |
2509 | } |
2510 | } | |
2511 | ||
fcf5b650 YR |
2512 | static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, |
2513 | u32 line_speed) | |
ea4e040a YR |
2514 | { |
2515 | struct bnx2x *bp = params->bp; | |
2516 | u8 port = params->port; | |
2517 | u32 init_crd, crd; | |
2518 | u32 count = 1000; | |
ea4e040a | 2519 | |
d231023e | 2520 | /* Disable port */ |
ea4e040a YR |
2521 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); |
2522 | ||
d231023e | 2523 | /* Wait for init credit */ |
ea4e040a YR |
2524 | init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); |
2525 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
2526 | DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); | |
2527 | ||
2528 | while ((init_crd != crd) && count) { | |
d231023e | 2529 | usleep_range(5000, 10000); |
ea4e040a YR |
2530 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); |
2531 | count--; | |
2532 | } | |
2533 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
2534 | if (init_crd != crd) { | |
2535 | DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", | |
2536 | init_crd, crd); | |
2537 | return -EINVAL; | |
2538 | } | |
2539 | ||
c0700f90 | 2540 | if (flow_ctrl & BNX2X_FLOW_CTRL_RX || |
8c99e7b0 YR |
2541 | line_speed == SPEED_10 || |
2542 | line_speed == SPEED_100 || | |
2543 | line_speed == SPEED_1000 || | |
2544 | line_speed == SPEED_2500) { | |
2545 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); | |
d231023e | 2546 | /* Update threshold */ |
ea4e040a | 2547 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); |
d231023e | 2548 | /* Update init credit */ |
cd88ccee | 2549 | init_crd = 778; /* (800-18-4) */ |
ea4e040a YR |
2550 | |
2551 | } else { | |
2552 | u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + | |
2553 | ETH_OVREHEAD)/16; | |
8c99e7b0 | 2554 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); |
d231023e | 2555 | /* Update threshold */ |
ea4e040a | 2556 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); |
d231023e | 2557 | /* Update init credit */ |
ea4e040a | 2558 | switch (line_speed) { |
ea4e040a YR |
2559 | case SPEED_10000: |
2560 | init_crd = thresh + 553 - 22; | |
2561 | break; | |
ea4e040a YR |
2562 | default: |
2563 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", | |
2564 | line_speed); | |
2565 | return -EINVAL; | |
ea4e040a YR |
2566 | } |
2567 | } | |
2568 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); | |
2569 | DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", | |
2570 | line_speed, init_crd); | |
2571 | ||
d231023e | 2572 | /* Probe the credit changes */ |
ea4e040a | 2573 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); |
d231023e | 2574 | usleep_range(5000, 10000); |
ea4e040a YR |
2575 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); |
2576 | ||
d231023e | 2577 | /* Enable port */ |
ea4e040a YR |
2578 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); |
2579 | return 0; | |
2580 | } | |
2581 | ||
e8920674 DK |
2582 | /** |
2583 | * bnx2x_get_emac_base - retrive emac base address | |
2cf7acf9 | 2584 | * |
e8920674 DK |
2585 | * @bp: driver handle |
2586 | * @mdc_mdio_access: access type | |
2587 | * @port: port id | |
2cf7acf9 YR |
2588 | * |
2589 | * This function selects the MDC/MDIO access (through emac0 or | |
2590 | * emac1) depend on the mdc_mdio_access, port, port swapped. Each | |
2591 | * phy has a default access mode, which could also be overridden | |
2592 | * by nvram configuration. This parameter, whether this is the | |
2593 | * default phy configuration, or the nvram overrun | |
2594 | * configuration, is passed here as mdc_mdio_access and selects | |
2595 | * the emac_base for the CL45 read/writes operations | |
2596 | */ | |
c18aa15d YR |
2597 | static u32 bnx2x_get_emac_base(struct bnx2x *bp, |
2598 | u32 mdc_mdio_access, u8 port) | |
ea4e040a | 2599 | { |
c18aa15d YR |
2600 | u32 emac_base = 0; |
2601 | switch (mdc_mdio_access) { | |
2602 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: | |
2603 | break; | |
2604 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: | |
2605 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) | |
2606 | emac_base = GRCBASE_EMAC1; | |
2607 | else | |
2608 | emac_base = GRCBASE_EMAC0; | |
2609 | break; | |
2610 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: | |
589abe3a EG |
2611 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) |
2612 | emac_base = GRCBASE_EMAC0; | |
2613 | else | |
2614 | emac_base = GRCBASE_EMAC1; | |
ea4e040a | 2615 | break; |
c18aa15d YR |
2616 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: |
2617 | emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
2618 | break; | |
2619 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: | |
6378c025 | 2620 | emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; |
ea4e040a YR |
2621 | break; |
2622 | default: | |
ea4e040a YR |
2623 | break; |
2624 | } | |
2625 | return emac_base; | |
2626 | ||
2627 | } | |
2628 | ||
6583e33b YR |
2629 | /******************************************************************/ |
2630 | /* CL22 access functions */ | |
2631 | /******************************************************************/ | |
2632 | static int bnx2x_cl22_write(struct bnx2x *bp, | |
2633 | struct bnx2x_phy *phy, | |
2634 | u16 reg, u16 val) | |
2635 | { | |
2636 | u32 tmp, mode; | |
2637 | u8 i; | |
2638 | int rc = 0; | |
2639 | /* Switch to CL22 */ | |
2640 | mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
2641 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, | |
2642 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); | |
2643 | ||
d231023e | 2644 | /* Address */ |
6583e33b YR |
2645 | tmp = ((phy->addr << 21) | (reg << 16) | val | |
2646 | EMAC_MDIO_COMM_COMMAND_WRITE_22 | | |
2647 | EMAC_MDIO_COMM_START_BUSY); | |
2648 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); | |
2649 | ||
2650 | for (i = 0; i < 50; i++) { | |
2651 | udelay(10); | |
2652 | ||
2653 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
2654 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
2655 | udelay(5); | |
2656 | break; | |
2657 | } | |
2658 | } | |
2659 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | |
2660 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
2661 | rc = -EFAULT; | |
2662 | } | |
2663 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); | |
2664 | return rc; | |
2665 | } | |
2666 | ||
2667 | static int bnx2x_cl22_read(struct bnx2x *bp, | |
2668 | struct bnx2x_phy *phy, | |
2669 | u16 reg, u16 *ret_val) | |
2670 | { | |
2671 | u32 val, mode; | |
2672 | u16 i; | |
2673 | int rc = 0; | |
2674 | ||
2675 | /* Switch to CL22 */ | |
2676 | mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
2677 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, | |
2678 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); | |
2679 | ||
d231023e | 2680 | /* Address */ |
6583e33b YR |
2681 | val = ((phy->addr << 21) | (reg << 16) | |
2682 | EMAC_MDIO_COMM_COMMAND_READ_22 | | |
2683 | EMAC_MDIO_COMM_START_BUSY); | |
2684 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); | |
2685 | ||
2686 | for (i = 0; i < 50; i++) { | |
2687 | udelay(10); | |
2688 | ||
2689 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
2690 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
2691 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); | |
2692 | udelay(5); | |
2693 | break; | |
2694 | } | |
2695 | } | |
2696 | if (val & EMAC_MDIO_COMM_START_BUSY) { | |
2697 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
2698 | ||
2699 | *ret_val = 0; | |
2700 | rc = -EFAULT; | |
2701 | } | |
2702 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); | |
2703 | return rc; | |
2704 | } | |
2705 | ||
2cf7acf9 YR |
2706 | /******************************************************************/ |
2707 | /* CL45 access functions */ | |
2708 | /******************************************************************/ | |
a198c142 YR |
2709 | static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, |
2710 | u8 devad, u16 reg, u16 *ret_val) | |
ea4e040a | 2711 | { |
a198c142 YR |
2712 | u32 val; |
2713 | u16 i; | |
fcf5b650 | 2714 | int rc = 0; |
55386fe8 YR |
2715 | u32 chip_id; |
2716 | if (phy->flags & FLAGS_MDC_MDIO_WA_G) { | |
2717 | chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | | |
2718 | ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); | |
2719 | bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); | |
2720 | } | |
2721 | ||
157fa283 YR |
2722 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
2723 | bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
2724 | EMAC_MDIO_STATUS_10MB); | |
d231023e | 2725 | /* Address */ |
a198c142 | 2726 | val = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
2727 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
2728 | EMAC_MDIO_COMM_START_BUSY); | |
a198c142 | 2729 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
2730 | |
2731 | for (i = 0; i < 50; i++) { | |
2732 | udelay(10); | |
2733 | ||
a198c142 YR |
2734 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
2735 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
ea4e040a YR |
2736 | udelay(5); |
2737 | break; | |
2738 | } | |
2739 | } | |
a198c142 YR |
2740 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
2741 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
6d870c39 | 2742 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
a198c142 | 2743 | *ret_val = 0; |
ea4e040a YR |
2744 | rc = -EFAULT; |
2745 | } else { | |
d231023e | 2746 | /* Data */ |
a198c142 YR |
2747 | val = ((phy->addr << 21) | (devad << 16) | |
2748 | EMAC_MDIO_COMM_COMMAND_READ_45 | | |
ea4e040a | 2749 | EMAC_MDIO_COMM_START_BUSY); |
a198c142 | 2750 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
2751 | |
2752 | for (i = 0; i < 50; i++) { | |
2753 | udelay(10); | |
2754 | ||
a198c142 | 2755 | val = REG_RD(bp, phy->mdio_ctrl + |
cd88ccee | 2756 | EMAC_REG_EMAC_MDIO_COMM); |
a198c142 YR |
2757 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
2758 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); | |
ea4e040a YR |
2759 | break; |
2760 | } | |
2761 | } | |
a198c142 YR |
2762 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
2763 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
6d870c39 | 2764 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
a198c142 | 2765 | *ret_val = 0; |
ea4e040a YR |
2766 | rc = -EFAULT; |
2767 | } | |
2768 | } | |
3c9ada22 YR |
2769 | /* Work around for E3 A0 */ |
2770 | if (phy->flags & FLAGS_MDC_MDIO_WA) { | |
2771 | phy->flags ^= FLAGS_DUMMY_READ; | |
2772 | if (phy->flags & FLAGS_DUMMY_READ) { | |
2773 | u16 temp_val; | |
2774 | bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); | |
2775 | } | |
2776 | } | |
ea4e040a | 2777 | |
157fa283 YR |
2778 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
2779 | bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
2780 | EMAC_MDIO_STATUS_10MB); | |
ea4e040a YR |
2781 | return rc; |
2782 | } | |
2783 | ||
a198c142 YR |
2784 | static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
2785 | u8 devad, u16 reg, u16 val) | |
ea4e040a | 2786 | { |
a198c142 YR |
2787 | u32 tmp; |
2788 | u8 i; | |
fcf5b650 | 2789 | int rc = 0; |
55386fe8 YR |
2790 | u32 chip_id; |
2791 | if (phy->flags & FLAGS_MDC_MDIO_WA_G) { | |
2792 | chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | | |
2793 | ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); | |
2794 | bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); | |
2795 | } | |
2796 | ||
157fa283 YR |
2797 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
2798 | bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
2799 | EMAC_MDIO_STATUS_10MB); | |
ea4e040a | 2800 | |
d231023e | 2801 | /* Address */ |
a198c142 | 2802 | tmp = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
2803 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
2804 | EMAC_MDIO_COMM_START_BUSY); | |
a198c142 | 2805 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
2806 | |
2807 | for (i = 0; i < 50; i++) { | |
2808 | udelay(10); | |
2809 | ||
a198c142 YR |
2810 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
2811 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
ea4e040a YR |
2812 | udelay(5); |
2813 | break; | |
2814 | } | |
2815 | } | |
a198c142 YR |
2816 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
2817 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
6d870c39 | 2818 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
ea4e040a | 2819 | rc = -EFAULT; |
ea4e040a | 2820 | } else { |
d231023e | 2821 | /* Data */ |
a198c142 YR |
2822 | tmp = ((phy->addr << 21) | (devad << 16) | val | |
2823 | EMAC_MDIO_COMM_COMMAND_WRITE_45 | | |
ea4e040a | 2824 | EMAC_MDIO_COMM_START_BUSY); |
a198c142 | 2825 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
2826 | |
2827 | for (i = 0; i < 50; i++) { | |
2828 | udelay(10); | |
2829 | ||
a198c142 | 2830 | tmp = REG_RD(bp, phy->mdio_ctrl + |
cd88ccee | 2831 | EMAC_REG_EMAC_MDIO_COMM); |
a198c142 YR |
2832 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
2833 | udelay(5); | |
ea4e040a YR |
2834 | break; |
2835 | } | |
2836 | } | |
a198c142 YR |
2837 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
2838 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
6d870c39 | 2839 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
ea4e040a YR |
2840 | rc = -EFAULT; |
2841 | } | |
2842 | } | |
3c9ada22 YR |
2843 | /* Work around for E3 A0 */ |
2844 | if (phy->flags & FLAGS_MDC_MDIO_WA) { | |
2845 | phy->flags ^= FLAGS_DUMMY_READ; | |
2846 | if (phy->flags & FLAGS_DUMMY_READ) { | |
2847 | u16 temp_val; | |
2848 | bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); | |
2849 | } | |
2850 | } | |
157fa283 YR |
2851 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
2852 | bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
2853 | EMAC_MDIO_STATUS_10MB); | |
3c9ada22 YR |
2854 | return rc; |
2855 | } | |
ec4010ec YM |
2856 | |
2857 | /******************************************************************/ | |
2858 | /* EEE section */ | |
2859 | /******************************************************************/ | |
2860 | static u8 bnx2x_eee_has_cap(struct link_params *params) | |
2861 | { | |
2862 | struct bnx2x *bp = params->bp; | |
2863 | ||
2864 | if (REG_RD(bp, params->shmem2_base) <= | |
2865 | offsetof(struct shmem2_region, eee_status[params->port])) | |
2866 | return 0; | |
2867 | ||
2868 | return 1; | |
2869 | } | |
2870 | ||
2871 | static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) | |
2872 | { | |
2873 | switch (nvram_mode) { | |
2874 | case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: | |
2875 | *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; | |
2876 | break; | |
2877 | case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: | |
2878 | *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; | |
2879 | break; | |
2880 | case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: | |
2881 | *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; | |
2882 | break; | |
2883 | default: | |
2884 | *idle_timer = 0; | |
2885 | break; | |
2886 | } | |
2887 | ||
2888 | return 0; | |
2889 | } | |
2890 | ||
2891 | static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) | |
2892 | { | |
2893 | switch (idle_timer) { | |
2894 | case EEE_MODE_NVRAM_BALANCED_TIME: | |
2895 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; | |
2896 | break; | |
2897 | case EEE_MODE_NVRAM_AGGRESSIVE_TIME: | |
2898 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; | |
2899 | break; | |
2900 | case EEE_MODE_NVRAM_LATENCY_TIME: | |
2901 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; | |
2902 | break; | |
2903 | default: | |
2904 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; | |
2905 | break; | |
2906 | } | |
2907 | ||
2908 | return 0; | |
2909 | } | |
2910 | ||
2911 | static u32 bnx2x_eee_calc_timer(struct link_params *params) | |
2912 | { | |
2913 | u32 eee_mode, eee_idle; | |
2914 | struct bnx2x *bp = params->bp; | |
2915 | ||
2916 | if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { | |
2917 | if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { | |
2918 | /* time value in eee_mode --> used directly*/ | |
2919 | eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; | |
2920 | } else { | |
2921 | /* hsi value in eee_mode --> time */ | |
2922 | if (bnx2x_eee_nvram_to_time(params->eee_mode & | |
2923 | EEE_MODE_NVRAM_MASK, | |
2924 | &eee_idle)) | |
2925 | return 0; | |
2926 | } | |
2927 | } else { | |
2928 | /* hsi values in nvram --> time*/ | |
2929 | eee_mode = ((REG_RD(bp, params->shmem_base + | |
2930 | offsetof(struct shmem_region, dev_info. | |
2931 | port_feature_config[params->port]. | |
2932 | eee_power_mode)) & | |
2933 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
2934 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
2935 | ||
2936 | if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) | |
2937 | return 0; | |
2938 | } | |
2939 | ||
2940 | return eee_idle; | |
2941 | } | |
2942 | ||
2943 | static int bnx2x_eee_set_timers(struct link_params *params, | |
2944 | struct link_vars *vars) | |
2945 | { | |
2946 | u32 eee_idle = 0, eee_mode; | |
2947 | struct bnx2x *bp = params->bp; | |
2948 | ||
2949 | eee_idle = bnx2x_eee_calc_timer(params); | |
2950 | ||
2951 | if (eee_idle) { | |
2952 | REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), | |
2953 | eee_idle); | |
2954 | } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && | |
2955 | (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && | |
2956 | (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { | |
2957 | DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); | |
2958 | return -EINVAL; | |
2959 | } | |
2960 | ||
2961 | vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); | |
2962 | if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { | |
2963 | /* eee_idle in 1u --> eee_status in 16u */ | |
2964 | eee_idle >>= 4; | |
2965 | vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | | |
2966 | SHMEM_EEE_TIME_OUTPUT_BIT; | |
2967 | } else { | |
2968 | if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) | |
2969 | return -EINVAL; | |
2970 | vars->eee_status |= eee_mode; | |
2971 | } | |
2972 | ||
2973 | return 0; | |
2974 | } | |
2975 | ||
2976 | static int bnx2x_eee_initial_config(struct link_params *params, | |
2977 | struct link_vars *vars, u8 mode) | |
2978 | { | |
2979 | vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; | |
2980 | ||
2981 | /* Propogate params' bits --> vars (for migration exposure) */ | |
2982 | if (params->eee_mode & EEE_MODE_ENABLE_LPI) | |
2983 | vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; | |
2984 | else | |
2985 | vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; | |
2986 | ||
2987 | if (params->eee_mode & EEE_MODE_ADV_LPI) | |
2988 | vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; | |
2989 | else | |
2990 | vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; | |
2991 | ||
2992 | return bnx2x_eee_set_timers(params, vars); | |
2993 | } | |
2994 | ||
2995 | static int bnx2x_eee_disable(struct bnx2x_phy *phy, | |
2996 | struct link_params *params, | |
2997 | struct link_vars *vars) | |
2998 | { | |
2999 | struct bnx2x *bp = params->bp; | |
3000 | ||
3001 | /* Make Certain LPI is disabled */ | |
3002 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); | |
3003 | ||
3004 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); | |
3005 | ||
3006 | vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; | |
3007 | ||
3008 | return 0; | |
3009 | } | |
3010 | ||
3011 | static int bnx2x_eee_advertise(struct bnx2x_phy *phy, | |
3012 | struct link_params *params, | |
3013 | struct link_vars *vars, u8 modes) | |
3014 | { | |
3015 | struct bnx2x *bp = params->bp; | |
3016 | u16 val = 0; | |
3017 | ||
3018 | /* Mask events preventing LPI generation */ | |
3019 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); | |
3020 | ||
3021 | if (modes & SHMEM_EEE_10G_ADV) { | |
3022 | DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); | |
3023 | val |= 0x8; | |
3024 | } | |
3025 | if (modes & SHMEM_EEE_1G_ADV) { | |
3026 | DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); | |
3027 | val |= 0x4; | |
3028 | } | |
3029 | ||
3030 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); | |
3031 | ||
3032 | vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; | |
3033 | vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); | |
3034 | ||
3035 | return 0; | |
3036 | } | |
3037 | ||
3038 | static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) | |
3039 | { | |
3040 | struct bnx2x *bp = params->bp; | |
3041 | ||
3042 | if (bnx2x_eee_has_cap(params)) | |
3043 | REG_WR(bp, params->shmem2_base + | |
3044 | offsetof(struct shmem2_region, | |
3045 | eee_status[params->port]), eee_status); | |
3046 | } | |
3047 | ||
3048 | static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, | |
3049 | struct link_params *params, | |
3050 | struct link_vars *vars) | |
3051 | { | |
3052 | struct bnx2x *bp = params->bp; | |
3053 | u16 adv = 0, lp = 0; | |
3054 | u32 lp_adv = 0; | |
3055 | u8 neg = 0; | |
3056 | ||
3057 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); | |
3058 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); | |
3059 | ||
3060 | if (lp & 0x2) { | |
3061 | lp_adv |= SHMEM_EEE_100M_ADV; | |
3062 | if (adv & 0x2) { | |
3063 | if (vars->line_speed == SPEED_100) | |
3064 | neg = 1; | |
3065 | DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); | |
3066 | } | |
3067 | } | |
3068 | if (lp & 0x14) { | |
3069 | lp_adv |= SHMEM_EEE_1G_ADV; | |
3070 | if (adv & 0x14) { | |
3071 | if (vars->line_speed == SPEED_1000) | |
3072 | neg = 1; | |
3073 | DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); | |
3074 | } | |
3075 | } | |
3076 | if (lp & 0x68) { | |
3077 | lp_adv |= SHMEM_EEE_10G_ADV; | |
3078 | if (adv & 0x68) { | |
3079 | if (vars->line_speed == SPEED_10000) | |
3080 | neg = 1; | |
3081 | DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); | |
3082 | } | |
3083 | } | |
3084 | ||
3085 | vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; | |
3086 | vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); | |
3087 | ||
3088 | if (neg) { | |
3089 | DP(NETIF_MSG_LINK, "EEE is active\n"); | |
3090 | vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; | |
3091 | } | |
3092 | ||
3093 | } | |
3094 | ||
3c9ada22 YR |
3095 | /******************************************************************/ |
3096 | /* BSC access functions from E3 */ | |
3097 | /******************************************************************/ | |
3098 | static void bnx2x_bsc_module_sel(struct link_params *params) | |
3099 | { | |
3100 | int idx; | |
3101 | u32 board_cfg, sfp_ctrl; | |
3102 | u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; | |
3103 | struct bnx2x *bp = params->bp; | |
3104 | u8 port = params->port; | |
3105 | /* Read I2C output PINs */ | |
3106 | board_cfg = REG_RD(bp, params->shmem_base + | |
3107 | offsetof(struct shmem_region, | |
3108 | dev_info.shared_hw_config.board)); | |
3109 | i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; | |
3110 | i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> | |
3111 | SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; | |
3112 | ||
3113 | /* Read I2C output value */ | |
3114 | sfp_ctrl = REG_RD(bp, params->shmem_base + | |
3115 | offsetof(struct shmem_region, | |
3116 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)); | |
3117 | i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; | |
3118 | i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; | |
3119 | DP(NETIF_MSG_LINK, "Setting BSC switch\n"); | |
3120 | for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) | |
3121 | bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); | |
3122 | } | |
3123 | ||
3124 | static int bnx2x_bsc_read(struct link_params *params, | |
d67710ff | 3125 | struct bnx2x *bp, |
3c9ada22 YR |
3126 | u8 sl_devid, |
3127 | u16 sl_addr, | |
3128 | u8 lc_addr, | |
3129 | u8 xfer_cnt, | |
3130 | u32 *data_array) | |
3131 | { | |
3132 | u32 val, i; | |
3133 | int rc = 0; | |
3c9ada22 | 3134 | |
3c9ada22 YR |
3135 | if (xfer_cnt > 16) { |
3136 | DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", | |
3137 | xfer_cnt); | |
3138 | return -EINVAL; | |
3139 | } | |
3140 | bnx2x_bsc_module_sel(params); | |
3141 | ||
3142 | xfer_cnt = 16 - lc_addr; | |
3143 | ||
d231023e | 3144 | /* Enable the engine */ |
3c9ada22 YR |
3145 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); |
3146 | val |= MCPR_IMC_COMMAND_ENABLE; | |
3147 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3148 | ||
d231023e | 3149 | /* Program slave device ID */ |
3c9ada22 YR |
3150 | val = (sl_devid << 16) | sl_addr; |
3151 | REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); | |
3152 | ||
d231023e | 3153 | /* Start xfer with 0 byte to update the address pointer ???*/ |
3c9ada22 YR |
3154 | val = (MCPR_IMC_COMMAND_ENABLE) | |
3155 | (MCPR_IMC_COMMAND_WRITE_OP << | |
3156 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | | |
3157 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); | |
3158 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3159 | ||
d231023e | 3160 | /* Poll for completion */ |
3c9ada22 YR |
3161 | i = 0; |
3162 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3163 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { | |
3164 | udelay(10); | |
3165 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3166 | if (i++ > 1000) { | |
3167 | DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", | |
3168 | i); | |
3169 | rc = -EFAULT; | |
3170 | break; | |
3171 | } | |
3172 | } | |
3173 | if (rc == -EFAULT) | |
3174 | return rc; | |
3175 | ||
d231023e | 3176 | /* Start xfer with read op */ |
3c9ada22 YR |
3177 | val = (MCPR_IMC_COMMAND_ENABLE) | |
3178 | (MCPR_IMC_COMMAND_READ_OP << | |
3179 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | | |
3180 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | | |
3181 | (xfer_cnt); | |
3182 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3183 | ||
d231023e | 3184 | /* Poll for completion */ |
3c9ada22 YR |
3185 | i = 0; |
3186 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3187 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { | |
3188 | udelay(10); | |
3189 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3190 | if (i++ > 1000) { | |
3191 | DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); | |
3192 | rc = -EFAULT; | |
3193 | break; | |
3194 | } | |
3195 | } | |
3196 | if (rc == -EFAULT) | |
3197 | return rc; | |
3198 | ||
3199 | for (i = (lc_addr >> 2); i < 4; i++) { | |
3200 | data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); | |
3201 | #ifdef __BIG_ENDIAN | |
3202 | data_array[i] = ((data_array[i] & 0x000000ff) << 24) | | |
3203 | ((data_array[i] & 0x0000ff00) << 8) | | |
3204 | ((data_array[i] & 0x00ff0000) >> 8) | | |
3205 | ((data_array[i] & 0xff000000) >> 24); | |
3206 | #endif | |
3207 | } | |
ea4e040a YR |
3208 | return rc; |
3209 | } | |
3210 | ||
3c9ada22 YR |
3211 | static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
3212 | u8 devad, u16 reg, u16 or_val) | |
3213 | { | |
3214 | u16 val; | |
3215 | bnx2x_cl45_read(bp, phy, devad, reg, &val); | |
3216 | bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); | |
3217 | } | |
3218 | ||
4e7b4997 YR |
3219 | static void bnx2x_cl45_read_and_write(struct bnx2x *bp, |
3220 | struct bnx2x_phy *phy, | |
3221 | u8 devad, u16 reg, u16 and_val) | |
3222 | { | |
3223 | u16 val; | |
3224 | bnx2x_cl45_read(bp, phy, devad, reg, &val); | |
3225 | bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); | |
3226 | } | |
3227 | ||
fcf5b650 YR |
3228 | int bnx2x_phy_read(struct link_params *params, u8 phy_addr, |
3229 | u8 devad, u16 reg, u16 *ret_val) | |
e10bc84d YR |
3230 | { |
3231 | u8 phy_index; | |
8f73f0b9 | 3232 | /* Probe for the phy according to the given phy_addr, and execute |
e10bc84d YR |
3233 | * the read request on it |
3234 | */ | |
3235 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
3236 | if (params->phy[phy_index].addr == phy_addr) { | |
3237 | return bnx2x_cl45_read(params->bp, | |
3238 | ¶ms->phy[phy_index], devad, | |
3239 | reg, ret_val); | |
3240 | } | |
3241 | } | |
3242 | return -EINVAL; | |
3243 | } | |
3244 | ||
fcf5b650 YR |
3245 | int bnx2x_phy_write(struct link_params *params, u8 phy_addr, |
3246 | u8 devad, u16 reg, u16 val) | |
e10bc84d YR |
3247 | { |
3248 | u8 phy_index; | |
8f73f0b9 | 3249 | /* Probe for the phy according to the given phy_addr, and execute |
e10bc84d YR |
3250 | * the write request on it |
3251 | */ | |
3252 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
3253 | if (params->phy[phy_index].addr == phy_addr) { | |
3254 | return bnx2x_cl45_write(params->bp, | |
3255 | ¶ms->phy[phy_index], devad, | |
3256 | reg, val); | |
3257 | } | |
3258 | } | |
3259 | return -EINVAL; | |
3260 | } | |
3c9ada22 YR |
3261 | static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, |
3262 | struct link_params *params) | |
3263 | { | |
3264 | u8 lane = 0; | |
3265 | struct bnx2x *bp = params->bp; | |
3266 | u32 path_swap, path_swap_ovr; | |
3267 | u8 path, port; | |
3268 | ||
3269 | path = BP_PATH(bp); | |
3270 | port = params->port; | |
3271 | ||
3272 | if (bnx2x_is_4_port_mode(bp)) { | |
3273 | u32 port_swap, port_swap_ovr; | |
3274 | ||
8f73f0b9 | 3275 | /* Figure out path swap value */ |
3c9ada22 YR |
3276 | path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); |
3277 | if (path_swap_ovr & 0x1) | |
3278 | path_swap = (path_swap_ovr & 0x2); | |
3279 | else | |
3280 | path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); | |
3281 | ||
3282 | if (path_swap) | |
3283 | path = path ^ 1; | |
3284 | ||
8f73f0b9 | 3285 | /* Figure out port swap value */ |
3c9ada22 YR |
3286 | port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); |
3287 | if (port_swap_ovr & 0x1) | |
3288 | port_swap = (port_swap_ovr & 0x2); | |
3289 | else | |
3290 | port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); | |
3291 | ||
3292 | if (port_swap) | |
3293 | port = port ^ 1; | |
3294 | ||
3295 | lane = (port<<1) + path; | |
d231023e | 3296 | } else { /* Two port mode - no port swap */ |
3c9ada22 | 3297 | |
8f73f0b9 | 3298 | /* Figure out path swap value */ |
3c9ada22 YR |
3299 | path_swap_ovr = |
3300 | REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); | |
3301 | if (path_swap_ovr & 0x1) { | |
3302 | path_swap = (path_swap_ovr & 0x2); | |
3303 | } else { | |
3304 | path_swap = | |
3305 | REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); | |
3306 | } | |
3307 | if (path_swap) | |
3308 | path = path ^ 1; | |
3309 | ||
3310 | lane = path << 1 ; | |
3311 | } | |
3312 | return lane; | |
3313 | } | |
e10bc84d | 3314 | |
ec146a6f YR |
3315 | static void bnx2x_set_aer_mmd(struct link_params *params, |
3316 | struct bnx2x_phy *phy) | |
ea4e040a | 3317 | { |
ea4e040a | 3318 | u32 ser_lane; |
f2e0899f DK |
3319 | u16 offset, aer_val; |
3320 | struct bnx2x *bp = params->bp; | |
ea4e040a YR |
3321 | ser_lane = ((params->lane_config & |
3322 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
3323 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
3324 | ||
ec146a6f YR |
3325 | offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? |
3326 | (phy->addr + ser_lane) : 0; | |
3327 | ||
3c9ada22 YR |
3328 | if (USES_WARPCORE(bp)) { |
3329 | aer_val = bnx2x_get_warpcore_lane(phy, params); | |
8f73f0b9 | 3330 | /* In Dual-lane mode, two lanes are joined together, |
3c9ada22 YR |
3331 | * so in order to configure them, the AER broadcast method is |
3332 | * used here. | |
3333 | * 0x200 is the broadcast address for lanes 0,1 | |
3334 | * 0x201 is the broadcast address for lanes 2,3 | |
3335 | */ | |
3336 | if (phy->flags & FLAGS_WC_DUAL_MODE) | |
3337 | aer_val = (aer_val >> 1) | 0x200; | |
3338 | } else if (CHIP_IS_E2(bp)) | |
82a0d475 | 3339 | aer_val = 0x3800 + offset - 1; |
f2e0899f DK |
3340 | else |
3341 | aer_val = 0x3800 + offset; | |
2f751a80 | 3342 | |
cd2be89b | 3343 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
cd88ccee | 3344 | MDIO_AER_BLOCK_AER_REG, aer_val); |
ec146a6f | 3345 | |
ea4e040a YR |
3346 | } |
3347 | ||
de6eae1f YR |
3348 | /******************************************************************/ |
3349 | /* Internal phy section */ | |
3350 | /******************************************************************/ | |
ea4e040a | 3351 | |
de6eae1f YR |
3352 | static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) |
3353 | { | |
3354 | u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
ea4e040a | 3355 | |
de6eae1f YR |
3356 | /* Set Clause 22 */ |
3357 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); | |
3358 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); | |
3359 | udelay(500); | |
3360 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); | |
3361 | udelay(500); | |
3362 | /* Set Clause 45 */ | |
3363 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); | |
ea4e040a YR |
3364 | } |
3365 | ||
de6eae1f | 3366 | static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) |
ea4e040a | 3367 | { |
de6eae1f | 3368 | u32 val; |
ea4e040a | 3369 | |
de6eae1f | 3370 | DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); |
ea4e040a | 3371 | |
de6eae1f | 3372 | val = SERDES_RESET_BITS << (port*16); |
c1b73990 | 3373 | |
d231023e | 3374 | /* Reset and unreset the SerDes/XGXS */ |
de6eae1f YR |
3375 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); |
3376 | udelay(500); | |
3377 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
ea4e040a | 3378 | |
de6eae1f | 3379 | bnx2x_set_serdes_access(bp, port); |
ea4e040a | 3380 | |
cd88ccee YR |
3381 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, |
3382 | DEFAULT_PHY_DEV_ADDR); | |
de6eae1f YR |
3383 | } |
3384 | ||
a75bb001 YR |
3385 | static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, |
3386 | struct link_params *params, | |
3387 | u32 action) | |
3388 | { | |
3389 | struct bnx2x *bp = params->bp; | |
3390 | switch (action) { | |
3391 | case PHY_INIT: | |
3392 | /* Set correct devad */ | |
3393 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); | |
3394 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, | |
3395 | phy->def_md_devad); | |
3396 | break; | |
3397 | } | |
3398 | } | |
3399 | ||
de6eae1f YR |
3400 | static void bnx2x_xgxs_deassert(struct link_params *params) |
3401 | { | |
3402 | struct bnx2x *bp = params->bp; | |
3403 | u8 port; | |
3404 | u32 val; | |
3405 | DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); | |
3406 | port = params->port; | |
3407 | ||
3408 | val = XGXS_RESET_BITS << (port*16); | |
3409 | ||
d231023e | 3410 | /* Reset and unreset the SerDes/XGXS */ |
de6eae1f YR |
3411 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); |
3412 | udelay(500); | |
3413 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
a75bb001 YR |
3414 | bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, |
3415 | PHY_INIT); | |
de6eae1f YR |
3416 | } |
3417 | ||
9045f6b4 YR |
3418 | static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, |
3419 | struct link_params *params, u16 *ieee_fc) | |
3420 | { | |
3421 | struct bnx2x *bp = params->bp; | |
3422 | *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; | |
8f73f0b9 | 3423 | /* Resolve pause mode and advertisement Please refer to Table |
9045f6b4 YR |
3424 | * 28B-3 of the 802.3ab-1999 spec |
3425 | */ | |
3426 | ||
3427 | switch (phy->req_flow_ctrl) { | |
3428 | case BNX2X_FLOW_CTRL_AUTO: | |
ba35a0fd YR |
3429 | switch (params->req_fc_auto_adv) { |
3430 | case BNX2X_FLOW_CTRL_BOTH: | |
9045f6b4 | 3431 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
ba35a0fd YR |
3432 | break; |
3433 | case BNX2X_FLOW_CTRL_RX: | |
3434 | case BNX2X_FLOW_CTRL_TX: | |
9045f6b4 | 3435 | *ieee_fc |= |
ba35a0fd YR |
3436 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
3437 | break; | |
3438 | default: | |
3439 | break; | |
3440 | } | |
9045f6b4 | 3441 | break; |
9045f6b4 YR |
3442 | case BNX2X_FLOW_CTRL_TX: |
3443 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
3444 | break; | |
3445 | ||
3446 | case BNX2X_FLOW_CTRL_RX: | |
3447 | case BNX2X_FLOW_CTRL_BOTH: | |
3448 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
3449 | break; | |
3450 | ||
3451 | case BNX2X_FLOW_CTRL_NONE: | |
3452 | default: | |
3453 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; | |
3454 | break; | |
3455 | } | |
3456 | DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); | |
3457 | } | |
3458 | ||
3459 | static void set_phy_vars(struct link_params *params, | |
3460 | struct link_vars *vars) | |
3461 | { | |
3462 | struct bnx2x *bp = params->bp; | |
3463 | u8 actual_phy_idx, phy_index, link_cfg_idx; | |
3464 | u8 phy_config_swapped = params->multi_phy_config & | |
3465 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
3466 | for (phy_index = INT_PHY; phy_index < params->num_phys; | |
3467 | phy_index++) { | |
3468 | link_cfg_idx = LINK_CONFIG_IDX(phy_index); | |
3469 | actual_phy_idx = phy_index; | |
3470 | if (phy_config_swapped) { | |
3471 | if (phy_index == EXT_PHY1) | |
3472 | actual_phy_idx = EXT_PHY2; | |
3473 | else if (phy_index == EXT_PHY2) | |
3474 | actual_phy_idx = EXT_PHY1; | |
3475 | } | |
3476 | params->phy[actual_phy_idx].req_flow_ctrl = | |
3477 | params->req_flow_ctrl[link_cfg_idx]; | |
3478 | ||
3479 | params->phy[actual_phy_idx].req_line_speed = | |
3480 | params->req_line_speed[link_cfg_idx]; | |
3481 | ||
3482 | params->phy[actual_phy_idx].speed_cap_mask = | |
3483 | params->speed_cap_mask[link_cfg_idx]; | |
a22f0788 | 3484 | |
9045f6b4 YR |
3485 | params->phy[actual_phy_idx].req_duplex = |
3486 | params->req_duplex[link_cfg_idx]; | |
3487 | ||
3488 | if (params->req_line_speed[link_cfg_idx] == | |
3489 | SPEED_AUTO_NEG) | |
3490 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
3491 | ||
3492 | DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," | |
3493 | " speed_cap_mask %x\n", | |
3494 | params->phy[actual_phy_idx].req_flow_ctrl, | |
3495 | params->phy[actual_phy_idx].req_line_speed, | |
3496 | params->phy[actual_phy_idx].speed_cap_mask); | |
3497 | } | |
3498 | } | |
3499 | ||
3500 | static void bnx2x_ext_phy_set_pause(struct link_params *params, | |
3501 | struct bnx2x_phy *phy, | |
3502 | struct link_vars *vars) | |
3503 | { | |
3504 | u16 val; | |
3505 | struct bnx2x *bp = params->bp; | |
d231023e | 3506 | /* Read modify write pause advertizing */ |
9045f6b4 YR |
3507 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); |
3508 | ||
3509 | val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; | |
3510 | ||
3511 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
3512 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
3513 | if ((vars->ieee_fc & | |
3514 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
3515 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
3516 | val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
3517 | } | |
3518 | if ((vars->ieee_fc & | |
3519 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
3520 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
3521 | val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
3522 | } | |
3523 | DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); | |
3524 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); | |
3525 | } | |
3526 | ||
3527 | static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) | |
3528 | { /* LD LP */ | |
3529 | switch (pause_result) { /* ASYM P ASYM P */ | |
3530 | case 0xb: /* 1 0 1 1 */ | |
3531 | vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; | |
3532 | break; | |
3533 | ||
3534 | case 0xe: /* 1 1 1 0 */ | |
3535 | vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; | |
3536 | break; | |
3537 | ||
3538 | case 0x5: /* 0 1 0 1 */ | |
3539 | case 0x7: /* 0 1 1 1 */ | |
3540 | case 0xd: /* 1 1 0 1 */ | |
3541 | case 0xf: /* 1 1 1 1 */ | |
3542 | vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; | |
3543 | break; | |
3544 | ||
3545 | default: | |
3546 | break; | |
3547 | } | |
3548 | if (pause_result & (1<<0)) | |
3549 | vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; | |
3550 | if (pause_result & (1<<1)) | |
3551 | vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; | |
8f73f0b9 | 3552 | |
9045f6b4 YR |
3553 | } |
3554 | ||
9e7e8399 MY |
3555 | static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, |
3556 | struct link_params *params, | |
3557 | struct link_vars *vars) | |
9045f6b4 | 3558 | { |
9045f6b4 YR |
3559 | u16 ld_pause; /* local */ |
3560 | u16 lp_pause; /* link partner */ | |
3561 | u16 pause_result; | |
9e7e8399 MY |
3562 | struct bnx2x *bp = params->bp; |
3563 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { | |
3564 | bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); | |
3565 | bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); | |
ca05f29c YR |
3566 | } else if (CHIP_IS_E3(bp) && |
3567 | SINGLE_MEDIA_DIRECT(params)) { | |
3568 | u8 lane = bnx2x_get_warpcore_lane(phy, params); | |
3569 | u16 gp_status, gp_mask; | |
3570 | bnx2x_cl45_read(bp, phy, | |
3571 | MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, | |
3572 | &gp_status); | |
3573 | gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | | |
3574 | MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << | |
3575 | lane; | |
3576 | if ((gp_status & gp_mask) == gp_mask) { | |
3577 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3578 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3579 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3580 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3581 | } else { | |
3582 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3583 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
3584 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3585 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
3586 | ld_pause = ((ld_pause & | |
3587 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
3588 | << 3); | |
3589 | lp_pause = ((lp_pause & | |
3590 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
3591 | << 3); | |
3592 | } | |
9e7e8399 MY |
3593 | } else { |
3594 | bnx2x_cl45_read(bp, phy, | |
3595 | MDIO_AN_DEVAD, | |
3596 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3597 | bnx2x_cl45_read(bp, phy, | |
3598 | MDIO_AN_DEVAD, | |
3599 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3600 | } | |
3601 | pause_result = (ld_pause & | |
3602 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; | |
3603 | pause_result |= (lp_pause & | |
3604 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; | |
3605 | DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); | |
3606 | bnx2x_pause_resolve(vars, pause_result); | |
9045f6b4 | 3607 | |
9e7e8399 | 3608 | } |
8f73f0b9 | 3609 | |
9e7e8399 MY |
3610 | static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, |
3611 | struct link_params *params, | |
3612 | struct link_vars *vars) | |
3613 | { | |
3614 | u8 ret = 0; | |
9045f6b4 | 3615 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
9e7e8399 MY |
3616 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { |
3617 | /* Update the advertised flow-controled of LD/LP in AN */ | |
3618 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
3619 | bnx2x_ext_phy_update_adv_fc(phy, params, vars); | |
3620 | /* But set the flow-control result as the requested one */ | |
9045f6b4 | 3621 | vars->flow_ctrl = phy->req_flow_ctrl; |
9e7e8399 | 3622 | } else if (phy->req_line_speed != SPEED_AUTO_NEG) |
9045f6b4 YR |
3623 | vars->flow_ctrl = params->req_fc_auto_adv; |
3624 | else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
3625 | ret = 1; | |
9e7e8399 | 3626 | bnx2x_ext_phy_update_adv_fc(phy, params, vars); |
9045f6b4 YR |
3627 | } |
3628 | return ret; | |
3629 | } | |
3c9ada22 YR |
3630 | /******************************************************************/ |
3631 | /* Warpcore section */ | |
3632 | /******************************************************************/ | |
3633 | /* The init_internal_warpcore should mirror the xgxs, | |
3634 | * i.e. reset the lane (if needed), set aer for the | |
3635 | * init configuration, and set/clear SGMII flag. Internal | |
3636 | * phy init is done purely in phy_init stage. | |
3637 | */ | |
e438c5d6 YR |
3638 | #define WC_TX_DRIVER(post2, idriver, ipre) \ |
3639 | ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ | |
3640 | (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ | |
3641 | (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) | |
3642 | ||
3643 | #define WC_TX_FIR(post, main, pre) \ | |
3644 | ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ | |
3645 | (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ | |
3646 | (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) | |
3647 | ||
4e7b4997 YR |
3648 | static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, |
3649 | struct link_params *params, | |
3650 | struct link_vars *vars) | |
3651 | { | |
3652 | struct bnx2x *bp = params->bp; | |
3653 | u16 i; | |
3654 | static struct bnx2x_reg_set reg_set[] = { | |
3655 | /* Step 1 - Program the TX/RX alignment markers */ | |
3656 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, | |
3657 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, | |
3658 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, | |
3659 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, | |
3660 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, | |
3661 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, | |
3662 | /* Step 2 - Configure the NP registers */ | |
3663 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, | |
3664 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, | |
3665 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, | |
3666 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, | |
3667 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, | |
3668 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, | |
3669 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, | |
3670 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, | |
3671 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} | |
3672 | }; | |
3673 | DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n"); | |
3674 | ||
3675 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
3676 | MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); | |
3677 | ||
b5a05550 | 3678 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
4e7b4997 YR |
3679 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
3680 | reg_set[i].val); | |
3681 | ||
3682 | /* Start KR2 work-around timer which handles BCM8073 link-parner */ | |
3683 | vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; | |
3684 | bnx2x_update_link_attr(params, vars->link_attr_sync); | |
3685 | } | |
ec4010ec | 3686 | |
4e4b14c9 YR |
3687 | static void bnx2x_disable_kr2(struct link_params *params, |
3688 | struct link_vars *vars, | |
3689 | struct bnx2x_phy *phy) | |
3690 | { | |
3691 | struct bnx2x *bp = params->bp; | |
3692 | int i; | |
3693 | static struct bnx2x_reg_set reg_set[] = { | |
3694 | /* Step 1 - Program the TX/RX alignment markers */ | |
3695 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, | |
3696 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, | |
3697 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, | |
3698 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, | |
3699 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, | |
3700 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, | |
3701 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, | |
3702 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, | |
3703 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, | |
3704 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, | |
3705 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, | |
3706 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, | |
3707 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, | |
3708 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, | |
3709 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} | |
3710 | }; | |
3711 | DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n"); | |
3712 | ||
3713 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) | |
3714 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, | |
3715 | reg_set[i].val); | |
3716 | vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; | |
3717 | bnx2x_update_link_attr(params, vars->link_attr_sync); | |
3718 | ||
3719 | vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT; | |
3720 | } | |
3721 | ||
ec4010ec YM |
3722 | static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, |
3723 | struct link_params *params) | |
3724 | { | |
3725 | struct bnx2x *bp = params->bp; | |
3726 | ||
3727 | DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); | |
3728 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3729 | MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); | |
3730 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
3731 | MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); | |
3732 | } | |
3733 | ||
4e7b4997 YR |
3734 | static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy, |
3735 | struct link_params *params) | |
3736 | { | |
3737 | /* Restart autoneg on the leading lane only */ | |
3738 | struct bnx2x *bp = params->bp; | |
3739 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
3740 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
3741 | MDIO_AER_BLOCK_AER_REG, lane); | |
3742 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3743 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); | |
3744 | ||
3745 | /* Restore AER */ | |
3746 | bnx2x_set_aer_mmd(params, phy); | |
3747 | } | |
3748 | ||
3c9ada22 YR |
3749 | static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, |
3750 | struct link_params *params, | |
3751 | struct link_vars *vars) { | |
cd1a26a3 | 3752 | u16 lane, i, cl72_ctrl, an_adv = 0; |
a351d497 YM |
3753 | struct bnx2x *bp = params->bp; |
3754 | static struct bnx2x_reg_set reg_set[] = { | |
3755 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, | |
a351d497 YM |
3756 | {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, |
3757 | {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, | |
3758 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, | |
3759 | /* Disable Autoneg: re-enable it after adv is done. */ | |
4e7b4997 YR |
3760 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, |
3761 | {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, | |
3762 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, | |
a351d497 | 3763 | }; |
3c9ada22 | 3764 | DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); |
6a51c0d1 | 3765 | /* Set to default registers that may be overriden by 10G force */ |
b5a05550 | 3766 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
a351d497 YM |
3767 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
3768 | reg_set[i].val); | |
a9077bfd | 3769 | |
b457bcb9 | 3770 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
503976e9 | 3771 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); |
4e7b4997 | 3772 | cl72_ctrl &= 0x08ff; |
b457bcb9 YR |
3773 | cl72_ctrl |= 0x3800; |
3774 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
503976e9 | 3775 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); |
b457bcb9 | 3776 | |
3c9ada22 YR |
3777 | /* Check adding advertisement for 1G KX */ |
3778 | if (((vars->line_speed == SPEED_AUTO_NEG) && | |
3779 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
3780 | (vars->line_speed == SPEED_1000)) { | |
05fcaeac | 3781 | u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; |
cd1a26a3 | 3782 | an_adv |= (1<<5); |
3c9ada22 YR |
3783 | |
3784 | /* Enable CL37 1G Parallel Detect */ | |
a351d497 | 3785 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); |
3c9ada22 YR |
3786 | DP(NETIF_MSG_LINK, "Advertize 1G\n"); |
3787 | } | |
3788 | if (((vars->line_speed == SPEED_AUTO_NEG) && | |
3789 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
3790 | (vars->line_speed == SPEED_10000)) { | |
3791 | /* Check adding advertisement for 10G KR */ | |
cd1a26a3 | 3792 | an_adv |= (1<<7); |
3c9ada22 | 3793 | /* Enable 10G Parallel Detect */ |
cd1a26a3 YR |
3794 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
3795 | MDIO_AER_BLOCK_AER_REG, 0); | |
3796 | ||
3c9ada22 | 3797 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
a351d497 | 3798 | MDIO_WC_REG_PAR_DET_10G_CTRL, 1); |
cd1a26a3 | 3799 | bnx2x_set_aer_mmd(params, phy); |
3c9ada22 YR |
3800 | DP(NETIF_MSG_LINK, "Advertize 10G\n"); |
3801 | } | |
3802 | ||
3803 | /* Set Transmit PMD settings */ | |
3804 | lane = bnx2x_get_warpcore_lane(phy, params); | |
3805 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
e438c5d6 YR |
3806 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, |
3807 | WC_TX_DRIVER(0x02, 0x06, 0x09)); | |
4e7b4997 YR |
3808 | /* Configure the next lane if dual mode */ |
3809 | if (phy->flags & FLAGS_WC_DUAL_MODE) | |
3810 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3811 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), | |
e438c5d6 | 3812 | WC_TX_DRIVER(0x02, 0x06, 0x09)); |
3c9ada22 YR |
3813 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
3814 | MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, | |
3815 | 0x03f0); | |
3816 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3817 | MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, | |
3818 | 0x03f0); | |
3c9ada22 YR |
3819 | |
3820 | /* Advertised speeds */ | |
3821 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
cd1a26a3 | 3822 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); |
3c9ada22 | 3823 | |
6b1f3900 YR |
3824 | /* Advertised and set FEC (Forward Error Correction) */ |
3825 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3826 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, | |
3827 | (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | | |
3828 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); | |
3829 | ||
a34bc969 YR |
3830 | /* Enable CL37 BAM */ |
3831 | if (REG_RD(bp, params->shmem_base + | |
3832 | offsetof(struct shmem_region, dev_info. | |
3833 | port_hw_config[params->port].default_cfg)) & | |
3834 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
a351d497 YM |
3835 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3836 | MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, | |
3837 | 1); | |
a34bc969 YR |
3838 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); |
3839 | } | |
3840 | ||
3c9ada22 YR |
3841 | /* Advertise pause */ |
3842 | bnx2x_ext_phy_set_pause(params, phy, vars); | |
b6a9c1ef | 3843 | vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; |
a351d497 YM |
3844 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3845 | MDIO_WC_REG_DIGITAL5_MISC7, 0x100); | |
a9077bfd YR |
3846 | |
3847 | /* Over 1G - AN local device user page 1 */ | |
3848 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3849 | MDIO_WC_REG_DIGITAL3_UP1, 0x1f); | |
3850 | ||
4e7b4997 YR |
3851 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
3852 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || | |
3853 | (phy->req_line_speed == SPEED_20000)) { | |
3854 | ||
3855 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
3856 | MDIO_AER_BLOCK_AER_REG, lane); | |
3857 | ||
3858 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
3859 | MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), | |
3860 | (1<<11)); | |
3861 | ||
3862 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3863 | MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); | |
3864 | bnx2x_set_aer_mmd(params, phy); | |
a9077bfd | 3865 | |
4e7b4997 | 3866 | bnx2x_warpcore_enable_AN_KR2(phy, params, vars); |
4e4b14c9 | 3867 | } else { |
b899e698 YR |
3868 | /* Enable Auto-Detect to support 1G over CL37 as well */ |
3869 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3870 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10); | |
3871 | ||
3872 | /* Force cl48 sync_status LOW to avoid getting stuck in CL73 | |
3873 | * parallel-detect loop when CL73 and CL37 are enabled. | |
3874 | */ | |
3875 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
3876 | MDIO_AER_BLOCK_AER_REG, 0); | |
3877 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3878 | MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI, 0x0800); | |
3879 | bnx2x_set_aer_mmd(params, phy); | |
3880 | ||
4e4b14c9 | 3881 | bnx2x_disable_kr2(params, vars, phy); |
4e7b4997 YR |
3882 | } |
3883 | ||
3884 | /* Enable Autoneg: only on the main lane */ | |
3885 | bnx2x_warpcore_restart_AN_KR(phy, params); | |
3c9ada22 YR |
3886 | } |
3887 | ||
3888 | static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, | |
3889 | struct link_params *params, | |
3890 | struct link_vars *vars) | |
3891 | { | |
3892 | struct bnx2x *bp = params->bp; | |
cd1a26a3 | 3893 | u16 val16, i, lane; |
a351d497 YM |
3894 | static struct bnx2x_reg_set reg_set[] = { |
3895 | /* Disable Autoneg */ | |
3896 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, | |
a351d497 YM |
3897 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, |
3898 | 0x3f00}, | |
3899 | {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, | |
3900 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, | |
3901 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, | |
3902 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, | |
a351d497 | 3903 | /* Leave cl72 training enable, needed for KR */ |
4e7b4997 | 3904 | {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} |
a351d497 YM |
3905 | }; |
3906 | ||
b5a05550 | 3907 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
a351d497 YM |
3908 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
3909 | reg_set[i].val); | |
3c9ada22 | 3910 | |
cd1a26a3 YR |
3911 | lane = bnx2x_get_warpcore_lane(phy, params); |
3912 | /* Global registers */ | |
3913 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
3914 | MDIO_AER_BLOCK_AER_REG, 0); | |
3915 | /* Disable CL36 PCS Tx */ | |
3916 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3917 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); | |
3918 | val16 &= ~(0x0011 << lane); | |
3919 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3920 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); | |
3c9ada22 | 3921 | |
cd1a26a3 YR |
3922 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
3923 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); | |
3924 | val16 |= (0x0303 << (lane << 1)); | |
3925 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3926 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); | |
3927 | /* Restore AER */ | |
3928 | bnx2x_set_aer_mmd(params, phy); | |
3c9ada22 YR |
3929 | /* Set speed via PMA/PMD register */ |
3930 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | |
3931 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); | |
3932 | ||
3933 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | |
3934 | MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); | |
3935 | ||
8f73f0b9 | 3936 | /* Enable encoded forced speed */ |
3c9ada22 YR |
3937 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
3938 | MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); | |
3939 | ||
3940 | /* Turn TX scramble payload only the 64/66 scrambler */ | |
3941 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3942 | MDIO_WC_REG_TX66_CONTROL, 0x9); | |
3943 | ||
3944 | /* Turn RX scramble payload only the 64/66 scrambler */ | |
3945 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
3946 | MDIO_WC_REG_RX66_CONTROL, 0xF9); | |
3947 | ||
d231023e | 3948 | /* Set and clear loopback to cause a reset to 64/66 decoder */ |
3c9ada22 YR |
3949 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
3950 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); | |
3951 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3952 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); | |
3953 | ||
3954 | } | |
3955 | ||
3956 | static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, | |
3957 | struct link_params *params, | |
3958 | u8 is_xfi) | |
3959 | { | |
3960 | struct bnx2x *bp = params->bp; | |
3961 | u16 misc1_val, tap_val, tx_driver_val, lane, val; | |
e438c5d6 YR |
3962 | u32 cfg_tap_val, tx_drv_brdct, tx_equal; |
3963 | ||
3c9ada22 | 3964 | /* Hold rxSeqStart */ |
a351d497 YM |
3965 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3966 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); | |
3c9ada22 YR |
3967 | |
3968 | /* Hold tx_fifo_reset */ | |
a351d497 YM |
3969 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3970 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); | |
3c9ada22 YR |
3971 | |
3972 | /* Disable CL73 AN */ | |
3973 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); | |
3974 | ||
3975 | /* Disable 100FX Enable and Auto-Detect */ | |
503976e9 YR |
3976 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
3977 | MDIO_WC_REG_FX100_CTRL1, 0xFFFA); | |
3c9ada22 YR |
3978 | |
3979 | /* Disable 100FX Idle detect */ | |
a351d497 YM |
3980 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3981 | MDIO_WC_REG_FX100_CTRL3, 0x0080); | |
3c9ada22 YR |
3982 | |
3983 | /* Set Block address to Remote PHY & Clear forced_speed[5] */ | |
503976e9 YR |
3984 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
3985 | MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); | |
3c9ada22 YR |
3986 | |
3987 | /* Turn off auto-detect & fiber mode */ | |
503976e9 YR |
3988 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
3989 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
3990 | 0xFFEE); | |
3c9ada22 YR |
3991 | |
3992 | /* Set filter_force_link, disable_false_link and parallel_detect */ | |
3993 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3994 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); | |
3995 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3996 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
3997 | ((val | 0x0006) & 0xFFFE)); | |
3998 | ||
3999 | /* Set XFI / SFI */ | |
4000 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4001 | MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); | |
4002 | ||
4003 | misc1_val &= ~(0x1f); | |
4004 | ||
4005 | if (is_xfi) { | |
4006 | misc1_val |= 0x5; | |
e438c5d6 YR |
4007 | tap_val = WC_TX_FIR(0x08, 0x37, 0x00); |
4008 | tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); | |
3c9ada22 | 4009 | } else { |
e438c5d6 YR |
4010 | cfg_tap_val = REG_RD(bp, params->shmem_base + |
4011 | offsetof(struct shmem_region, dev_info. | |
4012 | port_hw_config[params->port]. | |
4013 | sfi_tap_values)); | |
4014 | ||
4015 | tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; | |
4016 | ||
4017 | tx_drv_brdct = (cfg_tap_val & | |
4018 | PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> | |
4019 | PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; | |
4020 | ||
3c9ada22 | 4021 | misc1_val |= 0x9; |
e438c5d6 YR |
4022 | |
4023 | /* TAP values are controlled by nvram, if value there isn't 0 */ | |
4024 | if (tx_equal) | |
4025 | tap_val = (u16)tx_equal; | |
4026 | else | |
4027 | tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); | |
4028 | ||
4029 | if (tx_drv_brdct) | |
4030 | tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct, | |
4031 | 0x06); | |
4032 | else | |
4033 | tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); | |
3c9ada22 YR |
4034 | } |
4035 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4036 | MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); | |
4037 | ||
4038 | /* Set Transmit PMD settings */ | |
4039 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4040 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4041 | MDIO_WC_REG_TX_FIR_TAP, | |
4042 | tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); | |
4043 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4044 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | |
4045 | tx_driver_val); | |
4046 | ||
4047 | /* Enable fiber mode, enable and invert sig_det */ | |
a351d497 YM |
4048 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4049 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); | |
3c9ada22 YR |
4050 | |
4051 | /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ | |
a351d497 YM |
4052 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4053 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); | |
3c9ada22 | 4054 | |
ec4010ec | 4055 | bnx2x_warpcore_set_lpi_passthrough(phy, params); |
c8c60d88 | 4056 | |
3c9ada22 YR |
4057 | /* 10G XFI Full Duplex */ |
4058 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4059 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); | |
4060 | ||
4061 | /* Release tx_fifo_reset */ | |
503976e9 YR |
4062 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4063 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, | |
4064 | 0xFFFE); | |
3c9ada22 | 4065 | /* Release rxSeqStart */ |
503976e9 YR |
4066 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4067 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); | |
3c9ada22 YR |
4068 | } |
4069 | ||
4e7b4997 YR |
4070 | static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, |
4071 | struct link_params *params) | |
3c9ada22 | 4072 | { |
4e7b4997 YR |
4073 | u16 val; |
4074 | struct bnx2x *bp = params->bp; | |
4075 | /* Set global registers, so set AER lane to 0 */ | |
4076 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4077 | MDIO_AER_BLOCK_AER_REG, 0); | |
4078 | ||
4079 | /* Disable sequencer */ | |
4080 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, | |
4081 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); | |
4082 | ||
4083 | bnx2x_set_aer_mmd(params, phy); | |
4084 | ||
4085 | bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, | |
4086 | MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); | |
4087 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
4088 | MDIO_AN_REG_CTRL, 0); | |
4089 | /* Turn off CL73 */ | |
4090 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4091 | MDIO_WC_REG_CL73_USERB0_CTRL, &val); | |
4092 | val &= ~(1<<5); | |
4093 | val |= (1<<6); | |
4094 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4095 | MDIO_WC_REG_CL73_USERB0_CTRL, val); | |
4096 | ||
4097 | /* Set 20G KR2 force speed */ | |
4098 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
4099 | MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); | |
4100 | ||
4101 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
4102 | MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); | |
4103 | ||
4104 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4105 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); | |
4106 | val &= ~(3<<14); | |
4107 | val |= (1<<15); | |
4108 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4109 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); | |
4110 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4111 | MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); | |
4112 | ||
4113 | /* Enable sequencer (over lane 0) */ | |
4114 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4115 | MDIO_AER_BLOCK_AER_REG, 0); | |
4116 | ||
4117 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
4118 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); | |
4119 | ||
4120 | bnx2x_set_aer_mmd(params, phy); | |
3c9ada22 YR |
4121 | } |
4122 | ||
4123 | static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, | |
4124 | struct bnx2x_phy *phy, | |
4125 | u16 lane) | |
4126 | { | |
4127 | /* Rx0 anaRxControl1G */ | |
4128 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4129 | MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); | |
4130 | ||
4131 | /* Rx2 anaRxControl1G */ | |
4132 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4133 | MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); | |
4134 | ||
4135 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4136 | MDIO_WC_REG_RX66_SCW0, 0xE070); | |
4137 | ||
4138 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4139 | MDIO_WC_REG_RX66_SCW1, 0xC0D0); | |
4140 | ||
4141 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4142 | MDIO_WC_REG_RX66_SCW2, 0xA0B0); | |
4143 | ||
4144 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4145 | MDIO_WC_REG_RX66_SCW3, 0x8090); | |
4146 | ||
4147 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4148 | MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); | |
4149 | ||
4150 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4151 | MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); | |
4152 | ||
4153 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4154 | MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); | |
4155 | ||
4156 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4157 | MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); | |
4158 | ||
4159 | /* Serdes Digital Misc1 */ | |
4160 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4161 | MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); | |
4162 | ||
4163 | /* Serdes Digital4 Misc3 */ | |
4164 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4165 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); | |
4166 | ||
4167 | /* Set Transmit PMD settings */ | |
4168 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4169 | MDIO_WC_REG_TX_FIR_TAP, | |
e438c5d6 YR |
4170 | (WC_TX_FIR(0x12, 0x2d, 0x00) | |
4171 | MDIO_WC_REG_TX_FIR_TAP_ENABLE)); | |
3c9ada22 | 4172 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
e438c5d6 YR |
4173 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, |
4174 | WC_TX_DRIVER(0x02, 0x02, 0x02)); | |
3c9ada22 YR |
4175 | } |
4176 | ||
4177 | static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, | |
4178 | struct link_params *params, | |
521683da YR |
4179 | u8 fiber_mode, |
4180 | u8 always_autoneg) | |
3c9ada22 YR |
4181 | { |
4182 | struct bnx2x *bp = params->bp; | |
4183 | u16 val16, digctrl_kx1, digctrl_kx2; | |
3c9ada22 YR |
4184 | |
4185 | /* Clear XFI clock comp in non-10G single lane mode. */ | |
503976e9 YR |
4186 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4187 | MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); | |
3c9ada22 | 4188 | |
26964bb7 YM |
4189 | bnx2x_warpcore_set_lpi_passthrough(phy, params); |
4190 | ||
521683da | 4191 | if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { |
3c9ada22 | 4192 | /* SGMII Autoneg */ |
503976e9 YR |
4193 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4194 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, | |
4195 | 0x1000); | |
3c9ada22 YR |
4196 | DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); |
4197 | } else { | |
4198 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4199 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
521683da | 4200 | val16 &= 0xcebf; |
3c9ada22 YR |
4201 | switch (phy->req_line_speed) { |
4202 | case SPEED_10: | |
4203 | break; | |
4204 | case SPEED_100: | |
4205 | val16 |= 0x2000; | |
4206 | break; | |
4207 | case SPEED_1000: | |
4208 | val16 |= 0x0040; | |
4209 | break; | |
4210 | default: | |
94f05b0f JP |
4211 | DP(NETIF_MSG_LINK, |
4212 | "Speed not supported: 0x%x\n", phy->req_line_speed); | |
3c9ada22 YR |
4213 | return; |
4214 | } | |
4215 | ||
4216 | if (phy->req_duplex == DUPLEX_FULL) | |
4217 | val16 |= 0x0100; | |
4218 | ||
4219 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4220 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); | |
4221 | ||
4222 | DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", | |
4223 | phy->req_line_speed); | |
4224 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4225 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
4226 | DP(NETIF_MSG_LINK, " (readback) %x\n", val16); | |
4227 | } | |
4228 | ||
4229 | /* SGMII Slave mode and disable signal detect */ | |
4230 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4231 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); | |
4232 | if (fiber_mode) | |
4233 | digctrl_kx1 = 1; | |
4234 | else | |
4235 | digctrl_kx1 &= 0xff4a; | |
4236 | ||
4237 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4238 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4239 | digctrl_kx1); | |
4240 | ||
4241 | /* Turn off parallel detect */ | |
4242 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4243 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); | |
4244 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4245 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4246 | (digctrl_kx2 & ~(1<<2))); | |
4247 | ||
4248 | /* Re-enable parallel detect */ | |
4249 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4250 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4251 | (digctrl_kx2 | (1<<2))); | |
4252 | ||
4253 | /* Enable autodet */ | |
4254 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4255 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4256 | (digctrl_kx1 | 0x10)); | |
4257 | } | |
4258 | ||
4259 | static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, | |
4260 | struct bnx2x_phy *phy, | |
4261 | u8 reset) | |
4262 | { | |
4263 | u16 val; | |
4264 | /* Take lane out of reset after configuration is finished */ | |
4265 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4266 | MDIO_WC_REG_DIGITAL5_MISC6, &val); | |
4267 | if (reset) | |
4268 | val |= 0xC000; | |
4269 | else | |
4270 | val &= 0x3FFF; | |
4271 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4272 | MDIO_WC_REG_DIGITAL5_MISC6, val); | |
4273 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4274 | MDIO_WC_REG_DIGITAL5_MISC6, &val); | |
4275 | } | |
2f751a80 | 4276 | /* Clear SFI/XFI link settings registers */ |
3c9ada22 YR |
4277 | static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, |
4278 | struct link_params *params, | |
4279 | u16 lane) | |
4280 | { | |
4281 | struct bnx2x *bp = params->bp; | |
a351d497 YM |
4282 | u16 i; |
4283 | static struct bnx2x_reg_set wc_regs[] = { | |
4284 | {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, | |
4285 | {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, | |
4286 | {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, | |
4287 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, | |
4288 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4289 | 0x0195}, | |
4290 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4291 | 0x0007}, | |
4292 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, | |
4293 | 0x0002}, | |
4294 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, | |
4295 | {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, | |
4296 | {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, | |
4297 | {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} | |
4298 | }; | |
3c9ada22 | 4299 | /* Set XFI clock comp as default. */ |
a351d497 YM |
4300 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4301 | MDIO_WC_REG_RX66_CONTROL, (3<<13)); | |
4302 | ||
b5a05550 | 4303 | for (i = 0; i < ARRAY_SIZE(wc_regs); i++) |
a351d497 YM |
4304 | bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, |
4305 | wc_regs[i].val); | |
3c9ada22 | 4306 | |
3c9ada22 | 4307 | lane = bnx2x_get_warpcore_lane(phy, params); |
3c9ada22 YR |
4308 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
4309 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); | |
a351d497 | 4310 | |
3c9ada22 YR |
4311 | } |
4312 | ||
4313 | static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, | |
4314 | u32 chip_id, | |
4315 | u32 shmem_base, u8 port, | |
4316 | u8 *gpio_num, u8 *gpio_port) | |
4317 | { | |
4318 | u32 cfg_pin; | |
4319 | *gpio_num = 0; | |
4320 | *gpio_port = 0; | |
4321 | if (CHIP_IS_E3(bp)) { | |
4322 | cfg_pin = (REG_RD(bp, shmem_base + | |
4323 | offsetof(struct shmem_region, | |
4324 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
4325 | PORT_HW_CFG_E3_MOD_ABS_MASK) >> | |
4326 | PORT_HW_CFG_E3_MOD_ABS_SHIFT; | |
4327 | ||
8f73f0b9 | 4328 | /* Should not happen. This function called upon interrupt |
3c9ada22 YR |
4329 | * triggered by GPIO ( since EPIO can only generate interrupts |
4330 | * to MCP). | |
4331 | * So if this function was called and none of the GPIOs was set, | |
4332 | * it means the shit hit the fan. | |
4333 | */ | |
4334 | if ((cfg_pin < PIN_CFG_GPIO0_P0) || | |
4335 | (cfg_pin > PIN_CFG_GPIO3_P1)) { | |
94f05b0f | 4336 | DP(NETIF_MSG_LINK, |
503976e9 | 4337 | "No cfg pin %x for module detect indication\n", |
94f05b0f | 4338 | cfg_pin); |
3c9ada22 YR |
4339 | return -EINVAL; |
4340 | } | |
4341 | ||
4342 | *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; | |
4343 | *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; | |
4344 | } else { | |
4345 | *gpio_num = MISC_REGISTERS_GPIO_3; | |
4346 | *gpio_port = port; | |
4347 | } | |
503976e9 | 4348 | |
3c9ada22 YR |
4349 | return 0; |
4350 | } | |
4351 | ||
4352 | static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, | |
4353 | struct link_params *params) | |
4354 | { | |
4355 | struct bnx2x *bp = params->bp; | |
4356 | u8 gpio_num, gpio_port; | |
4357 | u32 gpio_val; | |
4358 | if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, | |
4359 | params->shmem_base, params->port, | |
4360 | &gpio_num, &gpio_port) != 0) | |
4361 | return 0; | |
4362 | gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); | |
4363 | ||
4364 | /* Call the handling function in case module is detected */ | |
4365 | if (gpio_val == 0) | |
4366 | return 1; | |
4367 | else | |
4368 | return 0; | |
4369 | } | |
a9077bfd | 4370 | static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, |
503976e9 | 4371 | struct link_params *params) |
a9077bfd YR |
4372 | { |
4373 | u16 gp2_status_reg0, lane; | |
4374 | struct bnx2x *bp = params->bp; | |
4375 | ||
4376 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4377 | ||
4378 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, | |
4379 | &gp2_status_reg0); | |
4380 | ||
4381 | return (gp2_status_reg0 >> (8+lane)) & 0x1; | |
4382 | } | |
4383 | ||
4384 | static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, | |
503976e9 YR |
4385 | struct link_params *params, |
4386 | struct link_vars *vars) | |
a9077bfd YR |
4387 | { |
4388 | struct bnx2x *bp = params->bp; | |
4389 | u32 serdes_net_if; | |
4390 | u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; | |
a9077bfd YR |
4391 | |
4392 | vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; | |
4393 | ||
4394 | if (!vars->turn_to_run_wc_rt) | |
4395 | return; | |
4396 | ||
a9077bfd | 4397 | if (vars->rx_tx_asic_rst) { |
b6a9c1ef | 4398 | u16 lane = bnx2x_get_warpcore_lane(phy, params); |
a9077bfd YR |
4399 | serdes_net_if = (REG_RD(bp, params->shmem_base + |
4400 | offsetof(struct shmem_region, dev_info. | |
4401 | port_hw_config[params->port].default_cfg)) & | |
4402 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
4403 | ||
4404 | switch (serdes_net_if) { | |
4405 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
4406 | /* Do we get link yet? */ | |
4407 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, | |
503976e9 | 4408 | &gp_status1); |
a9077bfd YR |
4409 | lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ |
4410 | /*10G KR*/ | |
4411 | lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; | |
4412 | ||
a9077bfd | 4413 | if (lnkup_kr || lnkup) { |
b6a9c1ef | 4414 | vars->rx_tx_asic_rst = 0; |
a9077bfd | 4415 | } else { |
8f73f0b9 | 4416 | /* Reset the lane to see if link comes up.*/ |
a9077bfd YR |
4417 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
4418 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
4419 | ||
d231023e | 4420 | /* Restart Autoneg */ |
a9077bfd YR |
4421 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
4422 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); | |
4423 | ||
4424 | vars->rx_tx_asic_rst--; | |
4425 | DP(NETIF_MSG_LINK, "0x%x retry left\n", | |
4426 | vars->rx_tx_asic_rst); | |
4427 | } | |
4428 | break; | |
4429 | ||
4430 | default: | |
4431 | break; | |
4432 | } | |
4433 | ||
4434 | } /*params->rx_tx_asic_rst*/ | |
4435 | ||
4436 | } | |
dbef807e YM |
4437 | static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, |
4438 | struct link_params *params) | |
4439 | { | |
4440 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
4441 | struct bnx2x *bp = params->bp; | |
4442 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
4443 | if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == | |
4444 | SPEED_10000) && | |
4445 | (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { | |
4446 | DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); | |
4447 | bnx2x_warpcore_set_10G_XFI(phy, params, 0); | |
4448 | } else { | |
4449 | DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); | |
4450 | bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); | |
4451 | } | |
4452 | } | |
4453 | ||
5a1fbf40 YR |
4454 | static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, |
4455 | struct bnx2x_phy *phy, | |
4456 | u8 tx_en) | |
4457 | { | |
4458 | struct bnx2x *bp = params->bp; | |
4459 | u32 cfg_pin; | |
4460 | u8 port = params->port; | |
4461 | ||
4462 | cfg_pin = REG_RD(bp, params->shmem_base + | |
4463 | offsetof(struct shmem_region, | |
4464 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
4465 | PORT_HW_CFG_E3_TX_LASER_MASK; | |
4466 | /* Set the !tx_en since this pin is DISABLE_TX_LASER */ | |
4467 | DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); | |
4468 | ||
4469 | /* For 20G, the expected pin to be used is 3 pins after the current */ | |
4470 | bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); | |
4471 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) | |
4472 | bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); | |
4473 | } | |
4474 | ||
3c9ada22 YR |
4475 | static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, |
4476 | struct link_params *params, | |
4477 | struct link_vars *vars) | |
4478 | { | |
4479 | struct bnx2x *bp = params->bp; | |
4480 | u32 serdes_net_if; | |
4481 | u8 fiber_mode; | |
4482 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
4483 | serdes_net_if = (REG_RD(bp, params->shmem_base + | |
4484 | offsetof(struct shmem_region, dev_info. | |
4485 | port_hw_config[params->port].default_cfg)) & | |
4486 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
4487 | DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " | |
4488 | "serdes_net_if = 0x%x\n", | |
4489 | vars->line_speed, serdes_net_if); | |
4490 | bnx2x_set_aer_mmd(params, phy); | |
d3a8f13b | 4491 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
3c9ada22 YR |
4492 | vars->phy_flags |= PHY_XGXS_FLAG; |
4493 | if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || | |
4494 | (phy->req_line_speed && | |
4495 | ((phy->req_line_speed == SPEED_100) || | |
4496 | (phy->req_line_speed == SPEED_10)))) { | |
4497 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4498 | DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); | |
4499 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
521683da | 4500 | bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); |
3c9ada22 YR |
4501 | } else { |
4502 | switch (serdes_net_if) { | |
4503 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
4504 | /* Enable KR Auto Neg */ | |
6a51c0d1 | 4505 | if (params->loopback_mode != LOOPBACK_EXT) |
3c9ada22 YR |
4506 | bnx2x_warpcore_enable_AN_KR(phy, params, vars); |
4507 | else { | |
4508 | DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); | |
4509 | bnx2x_warpcore_set_10G_KR(phy, params, vars); | |
4510 | } | |
4511 | break; | |
4512 | ||
4513 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | |
4514 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
4515 | if (vars->line_speed == SPEED_10000) { | |
4516 | DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); | |
4517 | bnx2x_warpcore_set_10G_XFI(phy, params, 1); | |
4518 | } else { | |
4519 | if (SINGLE_MEDIA_DIRECT(params)) { | |
4520 | DP(NETIF_MSG_LINK, "1G Fiber\n"); | |
4521 | fiber_mode = 1; | |
4522 | } else { | |
4523 | DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); | |
4524 | fiber_mode = 0; | |
4525 | } | |
4526 | bnx2x_warpcore_set_sgmii_speed(phy, | |
4527 | params, | |
521683da YR |
4528 | fiber_mode, |
4529 | 0); | |
3c9ada22 YR |
4530 | } |
4531 | ||
4532 | break; | |
4533 | ||
4534 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | |
5a1fbf40 YR |
4535 | /* Issue Module detection if module is plugged, or |
4536 | * enabled transmitter to avoid current leakage in case | |
4537 | * no module is connected | |
4538 | */ | |
0afbd74a YR |
4539 | if ((params->loopback_mode == LOOPBACK_NONE) || |
4540 | (params->loopback_mode == LOOPBACK_EXT)) { | |
4541 | if (bnx2x_is_sfp_module_plugged(phy, params)) | |
4542 | bnx2x_sfp_module_detection(phy, params); | |
4543 | else | |
4544 | bnx2x_sfp_e3_set_transmitter(params, | |
4545 | phy, 1); | |
4546 | } | |
dbef807e YM |
4547 | |
4548 | bnx2x_warpcore_config_sfi(phy, params); | |
3c9ada22 YR |
4549 | break; |
4550 | ||
4551 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: | |
4552 | if (vars->line_speed != SPEED_20000) { | |
4553 | DP(NETIF_MSG_LINK, "Speed not supported yet\n"); | |
4554 | return; | |
4555 | } | |
4556 | DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); | |
4557 | bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); | |
4558 | /* Issue Module detection */ | |
4559 | ||
4560 | bnx2x_sfp_module_detection(phy, params); | |
4561 | break; | |
3c9ada22 | 4562 | case PORT_HW_CFG_NET_SERDES_IF_KR2: |
4e7b4997 YR |
4563 | if (!params->loopback_mode) { |
4564 | bnx2x_warpcore_enable_AN_KR(phy, params, vars); | |
4565 | } else { | |
4566 | DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n"); | |
4567 | bnx2x_warpcore_set_20G_force_KR2(phy, params); | |
3c9ada22 | 4568 | } |
3c9ada22 | 4569 | break; |
3c9ada22 | 4570 | default: |
94f05b0f JP |
4571 | DP(NETIF_MSG_LINK, |
4572 | "Unsupported Serdes Net Interface 0x%x\n", | |
4573 | serdes_net_if); | |
3c9ada22 YR |
4574 | return; |
4575 | } | |
4576 | } | |
4577 | ||
4578 | /* Take lane out of reset after configuration is finished */ | |
4579 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
4580 | DP(NETIF_MSG_LINK, "Exit config init\n"); | |
4581 | } | |
4582 | ||
3c9ada22 YR |
4583 | static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, |
4584 | struct link_params *params) | |
4585 | { | |
4586 | struct bnx2x *bp = params->bp; | |
cd1a26a3 | 4587 | u16 val16, lane; |
3c9ada22 | 4588 | bnx2x_sfp_e3_set_transmitter(params, phy, 0); |
55386fe8 | 4589 | bnx2x_set_mdio_emac_per_phy(bp, params); |
3c9ada22 YR |
4590 | bnx2x_set_aer_mmd(params, phy); |
4591 | /* Global register */ | |
4592 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
4593 | ||
4594 | /* Clear loopback settings (if any) */ | |
4595 | /* 10G & 20G */ | |
503976e9 YR |
4596 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4597 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); | |
3c9ada22 | 4598 | |
503976e9 YR |
4599 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4600 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); | |
3c9ada22 YR |
4601 | |
4602 | /* Update those 1-copy registers */ | |
4603 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4604 | MDIO_AER_BLOCK_AER_REG, 0); | |
8f73f0b9 | 4605 | /* Enable 1G MDIO (1-copy) */ |
503976e9 YR |
4606 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4607 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4608 | ~0x10); | |
3c9ada22 | 4609 | |
503976e9 YR |
4610 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4611 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); | |
cd1a26a3 YR |
4612 | lane = bnx2x_get_warpcore_lane(phy, params); |
4613 | /* Disable CL36 PCS Tx */ | |
4614 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4615 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); | |
4616 | val16 |= (0x11 << lane); | |
4617 | if (phy->flags & FLAGS_WC_DUAL_MODE) | |
4618 | val16 |= (0x22 << lane); | |
4619 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4620 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); | |
4621 | ||
4622 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4623 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); | |
4624 | val16 &= ~(0x0303 << (lane << 1)); | |
4625 | val16 |= (0x0101 << (lane << 1)); | |
4626 | if (phy->flags & FLAGS_WC_DUAL_MODE) { | |
4627 | val16 &= ~(0x0c0c << (lane << 1)); | |
4628 | val16 |= (0x0404 << (lane << 1)); | |
4629 | } | |
4630 | ||
4631 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4632 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); | |
4633 | /* Restore AER */ | |
4634 | bnx2x_set_aer_mmd(params, phy); | |
4635 | ||
3c9ada22 YR |
4636 | } |
4637 | ||
4638 | static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, | |
4639 | struct link_params *params) | |
4640 | { | |
4641 | struct bnx2x *bp = params->bp; | |
4642 | u16 val16; | |
4643 | u32 lane; | |
4644 | DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", | |
4645 | params->loopback_mode, phy->req_line_speed); | |
4646 | ||
4e7b4997 YR |
4647 | if (phy->req_line_speed < SPEED_10000 || |
4648 | phy->supported & SUPPORTED_20000baseKR2_Full) { | |
4649 | /* 10/100/1000/20G-KR2 */ | |
3c9ada22 YR |
4650 | |
4651 | /* Update those 1-copy registers */ | |
4652 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4653 | MDIO_AER_BLOCK_AER_REG, 0); | |
4654 | /* Enable 1G MDIO (1-copy) */ | |
a351d497 YM |
4655 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4656 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4657 | 0x10); | |
3c9ada22 YR |
4658 | /* Set 1G loopback based on lane (1-copy) */ |
4659 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4660 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4661 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); | |
4e7b4997 YR |
4662 | val16 |= (1<<lane); |
4663 | if (phy->flags & FLAGS_WC_DUAL_MODE) | |
4664 | val16 |= (2<<lane); | |
3c9ada22 | 4665 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
503976e9 YR |
4666 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, |
4667 | val16); | |
3c9ada22 YR |
4668 | |
4669 | /* Switch back to 4-copy registers */ | |
4670 | bnx2x_set_aer_mmd(params, phy); | |
3c9ada22 | 4671 | } else { |
4e7b4997 | 4672 | /* 10G / 20G-DXGXS */ |
a351d497 YM |
4673 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4674 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, | |
4675 | 0x4000); | |
a351d497 YM |
4676 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4677 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); | |
3c9ada22 YR |
4678 | } |
4679 | } | |
4680 | ||
4681 | ||
d231023e YM |
4682 | |
4683 | static void bnx2x_sync_link(struct link_params *params, | |
4684 | struct link_vars *vars) | |
de6eae1f YR |
4685 | { |
4686 | struct bnx2x *bp = params->bp; | |
9380bb9e | 4687 | u8 link_10g_plus; |
de6f3377 YR |
4688 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) |
4689 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; | |
2f751a80 | 4690 | vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); |
de6eae1f YR |
4691 | if (vars->link_up) { |
4692 | DP(NETIF_MSG_LINK, "phy link up\n"); | |
4693 | ||
4694 | vars->phy_link_up = 1; | |
4695 | vars->duplex = DUPLEX_FULL; | |
4696 | switch (vars->link_status & | |
cd88ccee | 4697 | LINK_STATUS_SPEED_AND_DUPLEX_MASK) { |
8f73f0b9 YR |
4698 | case LINK_10THD: |
4699 | vars->duplex = DUPLEX_HALF; | |
4700 | /* Fall thru */ | |
4701 | case LINK_10TFD: | |
4702 | vars->line_speed = SPEED_10; | |
4703 | break; | |
de6eae1f | 4704 | |
8f73f0b9 YR |
4705 | case LINK_100TXHD: |
4706 | vars->duplex = DUPLEX_HALF; | |
4707 | /* Fall thru */ | |
4708 | case LINK_100T4: | |
4709 | case LINK_100TXFD: | |
4710 | vars->line_speed = SPEED_100; | |
4711 | break; | |
de6eae1f | 4712 | |
8f73f0b9 YR |
4713 | case LINK_1000THD: |
4714 | vars->duplex = DUPLEX_HALF; | |
4715 | /* Fall thru */ | |
4716 | case LINK_1000TFD: | |
4717 | vars->line_speed = SPEED_1000; | |
4718 | break; | |
de6eae1f | 4719 | |
8f73f0b9 YR |
4720 | case LINK_2500THD: |
4721 | vars->duplex = DUPLEX_HALF; | |
4722 | /* Fall thru */ | |
4723 | case LINK_2500TFD: | |
4724 | vars->line_speed = SPEED_2500; | |
4725 | break; | |
de6eae1f | 4726 | |
8f73f0b9 YR |
4727 | case LINK_10GTFD: |
4728 | vars->line_speed = SPEED_10000; | |
4729 | break; | |
4730 | case LINK_20GTFD: | |
4731 | vars->line_speed = SPEED_20000; | |
4732 | break; | |
4733 | default: | |
4734 | break; | |
de6eae1f | 4735 | } |
de6eae1f YR |
4736 | vars->flow_ctrl = 0; |
4737 | if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) | |
4738 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; | |
4739 | ||
4740 | if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) | |
4741 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; | |
4742 | ||
4743 | if (!vars->flow_ctrl) | |
4744 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
4745 | ||
4746 | if (vars->line_speed && | |
4747 | ((vars->line_speed == SPEED_10) || | |
4748 | (vars->line_speed == SPEED_100))) { | |
4749 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4750 | } else { | |
4751 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
4752 | } | |
3c9ada22 YR |
4753 | if (vars->line_speed && |
4754 | USES_WARPCORE(bp) && | |
4755 | (vars->line_speed == SPEED_1000)) | |
4756 | vars->phy_flags |= PHY_SGMII_FLAG; | |
d231023e | 4757 | /* Anything 10 and over uses the bmac */ |
9380bb9e YR |
4758 | link_10g_plus = (vars->line_speed >= SPEED_10000); |
4759 | ||
4760 | if (link_10g_plus) { | |
4761 | if (USES_WARPCORE(bp)) | |
4762 | vars->mac_type = MAC_TYPE_XMAC; | |
4763 | else | |
3c9ada22 | 4764 | vars->mac_type = MAC_TYPE_BMAC; |
9380bb9e YR |
4765 | } else { |
4766 | if (USES_WARPCORE(bp)) | |
4767 | vars->mac_type = MAC_TYPE_UMAC; | |
3c9ada22 YR |
4768 | else |
4769 | vars->mac_type = MAC_TYPE_EMAC; | |
9380bb9e | 4770 | } |
d231023e | 4771 | } else { /* Link down */ |
de6eae1f YR |
4772 | DP(NETIF_MSG_LINK, "phy link down\n"); |
4773 | ||
4774 | vars->phy_link_up = 0; | |
4775 | ||
4776 | vars->line_speed = 0; | |
4777 | vars->duplex = DUPLEX_FULL; | |
4778 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
4779 | ||
d231023e | 4780 | /* Indicate no mac active */ |
de6eae1f | 4781 | vars->mac_type = MAC_TYPE_NONE; |
de6f3377 YR |
4782 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) |
4783 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
d0b8a6f9 YM |
4784 | if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) |
4785 | vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; | |
de6eae1f | 4786 | } |
2f751a80 YR |
4787 | } |
4788 | ||
4789 | void bnx2x_link_status_update(struct link_params *params, | |
4790 | struct link_vars *vars) | |
4791 | { | |
4792 | struct bnx2x *bp = params->bp; | |
4793 | u8 port = params->port; | |
4794 | u32 sync_offset, media_types; | |
4795 | /* Update PHY configuration */ | |
4796 | set_phy_vars(params, vars); | |
de6eae1f | 4797 | |
2f751a80 YR |
4798 | vars->link_status = REG_RD(bp, params->shmem_base + |
4799 | offsetof(struct shmem_region, | |
4800 | port_mb[port].link_status)); | |
7614fe88 MB |
4801 | |
4802 | /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ | |
05fcaeac YR |
4803 | if (params->loopback_mode != LOOPBACK_NONE && |
4804 | params->loopback_mode != LOOPBACK_EXT) | |
7614fe88 MB |
4805 | vars->link_status |= LINK_STATUS_LINK_UP; |
4806 | ||
08e9acc2 YM |
4807 | if (bnx2x_eee_has_cap(params)) |
4808 | vars->eee_status = REG_RD(bp, params->shmem2_base + | |
4809 | offsetof(struct shmem2_region, | |
4810 | eee_status[params->port])); | |
2f751a80 YR |
4811 | |
4812 | vars->phy_flags = PHY_XGXS_FLAG; | |
4813 | bnx2x_sync_link(params, vars); | |
1ac9e428 YR |
4814 | /* Sync media type */ |
4815 | sync_offset = params->shmem_base + | |
4816 | offsetof(struct shmem_region, | |
4817 | dev_info.port_hw_config[port].media_type); | |
4818 | media_types = REG_RD(bp, sync_offset); | |
4819 | ||
4820 | params->phy[INT_PHY].media_type = | |
4821 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> | |
4822 | PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; | |
4823 | params->phy[EXT_PHY1].media_type = | |
4824 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> | |
4825 | PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; | |
4826 | params->phy[EXT_PHY2].media_type = | |
4827 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> | |
4828 | PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; | |
4829 | DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); | |
4830 | ||
020c7e3f YR |
4831 | /* Sync AEU offset */ |
4832 | sync_offset = params->shmem_base + | |
4833 | offsetof(struct shmem_region, | |
4834 | dev_info.port_hw_config[port].aeu_int_mask); | |
4835 | ||
4836 | vars->aeu_int_mask = REG_RD(bp, sync_offset); | |
4837 | ||
b8d6d082 YR |
4838 | /* Sync PFC status */ |
4839 | if (vars->link_status & LINK_STATUS_PFC_ENABLED) | |
4840 | params->feature_config_flags |= | |
4841 | FEATURE_CONFIG_PFC_ENABLED; | |
4842 | else | |
4843 | params->feature_config_flags &= | |
4844 | ~FEATURE_CONFIG_PFC_ENABLED; | |
4845 | ||
4e7b4997 YR |
4846 | if (SHMEM2_HAS(bp, link_attr_sync)) |
4847 | vars->link_attr_sync = SHMEM2_RD(bp, | |
4848 | link_attr_sync[params->port]); | |
4849 | ||
020c7e3f YR |
4850 | DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", |
4851 | vars->link_status, vars->phy_link_up, vars->aeu_int_mask); | |
de6eae1f YR |
4852 | DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", |
4853 | vars->line_speed, vars->duplex, vars->flow_ctrl); | |
4854 | } | |
4855 | ||
de6eae1f YR |
4856 | static void bnx2x_set_master_ln(struct link_params *params, |
4857 | struct bnx2x_phy *phy) | |
4858 | { | |
4859 | struct bnx2x *bp = params->bp; | |
4860 | u16 new_master_ln, ser_lane; | |
cd88ccee | 4861 | ser_lane = ((params->lane_config & |
de6eae1f | 4862 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
cd88ccee | 4863 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); |
de6eae1f | 4864 | |
d231023e | 4865 | /* Set the master_ln for AN */ |
cd2be89b | 4866 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4867 | MDIO_REG_BANK_XGXS_BLOCK2, |
4868 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
4869 | &new_master_ln); | |
de6eae1f | 4870 | |
cd2be89b | 4871 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4872 | MDIO_REG_BANK_XGXS_BLOCK2 , |
4873 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
4874 | (new_master_ln | ser_lane)); | |
de6eae1f YR |
4875 | } |
4876 | ||
fcf5b650 YR |
4877 | static int bnx2x_reset_unicore(struct link_params *params, |
4878 | struct bnx2x_phy *phy, | |
4879 | u8 set_serdes) | |
de6eae1f YR |
4880 | { |
4881 | struct bnx2x *bp = params->bp; | |
4882 | u16 mii_control; | |
4883 | u16 i; | |
cd2be89b | 4884 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4885 | MDIO_REG_BANK_COMBO_IEEE0, |
4886 | MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); | |
de6eae1f | 4887 | |
d231023e | 4888 | /* Reset the unicore */ |
cd2be89b | 4889 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4890 | MDIO_REG_BANK_COMBO_IEEE0, |
4891 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
4892 | (mii_control | | |
4893 | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); | |
de6eae1f YR |
4894 | if (set_serdes) |
4895 | bnx2x_set_serdes_access(bp, params->port); | |
4896 | ||
d231023e | 4897 | /* Wait for the reset to self clear */ |
de6eae1f YR |
4898 | for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { |
4899 | udelay(5); | |
4900 | ||
d231023e | 4901 | /* The reset erased the previous bank value */ |
cd2be89b | 4902 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4903 | MDIO_REG_BANK_COMBO_IEEE0, |
4904 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
4905 | &mii_control); | |
de6eae1f YR |
4906 | |
4907 | if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { | |
4908 | udelay(5); | |
4909 | return 0; | |
4910 | } | |
4911 | } | |
ea4e040a | 4912 | |
6d870c39 YR |
4913 | netdev_err(bp->dev, "Warning: PHY was not initialized," |
4914 | " Port %d\n", | |
4915 | params->port); | |
ea4e040a YR |
4916 | DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); |
4917 | return -EINVAL; | |
4918 | ||
4919 | } | |
4920 | ||
e10bc84d YR |
4921 | static void bnx2x_set_swap_lanes(struct link_params *params, |
4922 | struct bnx2x_phy *phy) | |
ea4e040a YR |
4923 | { |
4924 | struct bnx2x *bp = params->bp; | |
8f73f0b9 YR |
4925 | /* Each two bits represents a lane number: |
4926 | * No swap is 0123 => 0x1b no need to enable the swap | |
2cf7acf9 | 4927 | */ |
2f751a80 | 4928 | u16 rx_lane_swap, tx_lane_swap; |
ea4e040a | 4929 | |
ea4e040a | 4930 | rx_lane_swap = ((params->lane_config & |
cd88ccee YR |
4931 | PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> |
4932 | PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); | |
ea4e040a | 4933 | tx_lane_swap = ((params->lane_config & |
cd88ccee YR |
4934 | PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> |
4935 | PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); | |
ea4e040a YR |
4936 | |
4937 | if (rx_lane_swap != 0x1b) { | |
cd2be89b | 4938 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4939 | MDIO_REG_BANK_XGXS_BLOCK2, |
4940 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, | |
4941 | (rx_lane_swap | | |
4942 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | | |
4943 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); | |
ea4e040a | 4944 | } else { |
cd2be89b | 4945 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4946 | MDIO_REG_BANK_XGXS_BLOCK2, |
4947 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); | |
ea4e040a YR |
4948 | } |
4949 | ||
4950 | if (tx_lane_swap != 0x1b) { | |
cd2be89b | 4951 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4952 | MDIO_REG_BANK_XGXS_BLOCK2, |
4953 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, | |
4954 | (tx_lane_swap | | |
4955 | MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); | |
ea4e040a | 4956 | } else { |
cd2be89b | 4957 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4958 | MDIO_REG_BANK_XGXS_BLOCK2, |
4959 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); | |
ea4e040a YR |
4960 | } |
4961 | } | |
4962 | ||
e10bc84d YR |
4963 | static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, |
4964 | struct link_params *params) | |
ea4e040a YR |
4965 | { |
4966 | struct bnx2x *bp = params->bp; | |
4967 | u16 control2; | |
cd2be89b | 4968 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4969 | MDIO_REG_BANK_SERDES_DIGITAL, |
4970 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
4971 | &control2); | |
7aa0711f | 4972 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
18afb0a6 YR |
4973 | control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; |
4974 | else | |
4975 | control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; | |
7aa0711f YR |
4976 | DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", |
4977 | phy->speed_cap_mask, control2); | |
cd2be89b | 4978 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4979 | MDIO_REG_BANK_SERDES_DIGITAL, |
4980 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
4981 | control2); | |
ea4e040a | 4982 | |
e10bc84d | 4983 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && |
c18aa15d | 4984 | (phy->speed_cap_mask & |
18afb0a6 | 4985 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { |
ea4e040a YR |
4986 | DP(NETIF_MSG_LINK, "XGXS\n"); |
4987 | ||
cd2be89b | 4988 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4989 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
4990 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, | |
4991 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); | |
ea4e040a | 4992 | |
cd2be89b | 4993 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4994 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
4995 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
4996 | &control2); | |
ea4e040a YR |
4997 | |
4998 | ||
4999 | control2 |= | |
5000 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; | |
5001 | ||
cd2be89b | 5002 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5003 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
5004 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
5005 | control2); | |
ea4e040a YR |
5006 | |
5007 | /* Disable parallel detection of HiG */ | |
cd2be89b | 5008 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5009 | MDIO_REG_BANK_XGXS_BLOCK2, |
5010 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, | |
5011 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | | |
5012 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); | |
ea4e040a YR |
5013 | } |
5014 | } | |
5015 | ||
e10bc84d YR |
5016 | static void bnx2x_set_autoneg(struct bnx2x_phy *phy, |
5017 | struct link_params *params, | |
cd88ccee YR |
5018 | struct link_vars *vars, |
5019 | u8 enable_cl73) | |
ea4e040a YR |
5020 | { |
5021 | struct bnx2x *bp = params->bp; | |
5022 | u16 reg_val; | |
5023 | ||
5024 | /* CL37 Autoneg */ | |
cd2be89b | 5025 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5026 | MDIO_REG_BANK_COMBO_IEEE0, |
5027 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
ea4e040a YR |
5028 | |
5029 | /* CL37 Autoneg Enabled */ | |
8c99e7b0 | 5030 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
5031 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; |
5032 | else /* CL37 Autoneg Disabled */ | |
5033 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
5034 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); | |
5035 | ||
cd2be89b | 5036 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5037 | MDIO_REG_BANK_COMBO_IEEE0, |
5038 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
ea4e040a YR |
5039 | |
5040 | /* Enable/Disable Autodetection */ | |
5041 | ||
cd2be89b | 5042 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5043 | MDIO_REG_BANK_SERDES_DIGITAL, |
5044 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); | |
239d686d EG |
5045 | reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | |
5046 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); | |
5047 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; | |
8c99e7b0 | 5048 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
5049 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; |
5050 | else | |
5051 | reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; | |
5052 | ||
cd2be89b | 5053 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5054 | MDIO_REG_BANK_SERDES_DIGITAL, |
5055 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); | |
ea4e040a YR |
5056 | |
5057 | /* Enable TetonII and BAM autoneg */ | |
cd2be89b | 5058 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5059 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
5060 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
ea4e040a | 5061 | ®_val); |
8c99e7b0 | 5062 | if (vars->line_speed == SPEED_AUTO_NEG) { |
ea4e040a YR |
5063 | /* Enable BAM aneg Mode and TetonII aneg Mode */ |
5064 | reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
5065 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
5066 | } else { | |
5067 | /* TetonII and BAM Autoneg Disabled */ | |
5068 | reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
5069 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
5070 | } | |
cd2be89b | 5071 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5072 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
5073 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
5074 | reg_val); | |
ea4e040a | 5075 | |
239d686d EG |
5076 | if (enable_cl73) { |
5077 | /* Enable Cl73 FSM status bits */ | |
cd2be89b | 5078 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5079 | MDIO_REG_BANK_CL73_USERB0, |
5080 | MDIO_CL73_USERB0_CL73_UCTRL, | |
5081 | 0xe); | |
239d686d EG |
5082 | |
5083 | /* Enable BAM Station Manager*/ | |
cd2be89b | 5084 | CL22_WR_OVER_CL45(bp, phy, |
239d686d EG |
5085 | MDIO_REG_BANK_CL73_USERB0, |
5086 | MDIO_CL73_USERB0_CL73_BAM_CTRL1, | |
5087 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | | |
5088 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | | |
5089 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); | |
5090 | ||
7846e471 | 5091 | /* Advertise CL73 link speeds */ |
cd2be89b | 5092 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5093 | MDIO_REG_BANK_CL73_IEEEB1, |
5094 | MDIO_CL73_IEEEB1_AN_ADV2, | |
5095 | ®_val); | |
7aa0711f | 5096 | if (phy->speed_cap_mask & |
7846e471 YR |
5097 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
5098 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; | |
7aa0711f | 5099 | if (phy->speed_cap_mask & |
7846e471 YR |
5100 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
5101 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; | |
239d686d | 5102 | |
cd2be89b | 5103 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5104 | MDIO_REG_BANK_CL73_IEEEB1, |
5105 | MDIO_CL73_IEEEB1_AN_ADV2, | |
5106 | reg_val); | |
239d686d | 5107 | |
239d686d EG |
5108 | /* CL73 Autoneg Enabled */ |
5109 | reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; | |
5110 | ||
5111 | } else /* CL73 Autoneg Disabled */ | |
5112 | reg_val = 0; | |
ea4e040a | 5113 | |
cd2be89b | 5114 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5115 | MDIO_REG_BANK_CL73_IEEEB0, |
5116 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); | |
ea4e040a YR |
5117 | } |
5118 | ||
d231023e | 5119 | /* Program SerDes, forced speed */ |
e10bc84d YR |
5120 | static void bnx2x_program_serdes(struct bnx2x_phy *phy, |
5121 | struct link_params *params, | |
cd88ccee | 5122 | struct link_vars *vars) |
ea4e040a YR |
5123 | { |
5124 | struct bnx2x *bp = params->bp; | |
5125 | u16 reg_val; | |
5126 | ||
d231023e | 5127 | /* Program duplex, disable autoneg and sgmii*/ |
cd2be89b | 5128 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5129 | MDIO_REG_BANK_COMBO_IEEE0, |
5130 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
ea4e040a | 5131 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | |
57937203 EG |
5132 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
5133 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); | |
7aa0711f | 5134 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a | 5135 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; |
cd2be89b | 5136 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5137 | MDIO_REG_BANK_COMBO_IEEE0, |
5138 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
ea4e040a | 5139 | |
8f73f0b9 | 5140 | /* Program speed |
2cf7acf9 YR |
5141 | * - needed only if the speed is greater than 1G (2.5G or 10G) |
5142 | */ | |
cd2be89b | 5143 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5144 | MDIO_REG_BANK_SERDES_DIGITAL, |
5145 | MDIO_SERDES_DIGITAL_MISC1, ®_val); | |
d231023e | 5146 | /* Clearing the speed value before setting the right speed */ |
8c99e7b0 YR |
5147 | DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); |
5148 | ||
5149 | reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | | |
5150 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
5151 | ||
5152 | if (!((vars->line_speed == SPEED_1000) || | |
5153 | (vars->line_speed == SPEED_100) || | |
5154 | (vars->line_speed == SPEED_10))) { | |
5155 | ||
ea4e040a YR |
5156 | reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | |
5157 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
8c99e7b0 | 5158 | if (vars->line_speed == SPEED_10000) |
ea4e040a YR |
5159 | reg_val |= |
5160 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; | |
8c99e7b0 YR |
5161 | } |
5162 | ||
cd2be89b | 5163 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5164 | MDIO_REG_BANK_SERDES_DIGITAL, |
5165 | MDIO_SERDES_DIGITAL_MISC1, reg_val); | |
8c99e7b0 | 5166 | |
ea4e040a YR |
5167 | } |
5168 | ||
9045f6b4 YR |
5169 | static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, |
5170 | struct link_params *params) | |
ea4e040a YR |
5171 | { |
5172 | struct bnx2x *bp = params->bp; | |
5173 | u16 val = 0; | |
5174 | ||
d231023e | 5175 | /* Set extended capabilities */ |
7aa0711f | 5176 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) |
ea4e040a | 5177 | val |= MDIO_OVER_1G_UP1_2_5G; |
7aa0711f | 5178 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
ea4e040a | 5179 | val |= MDIO_OVER_1G_UP1_10G; |
cd2be89b | 5180 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5181 | MDIO_REG_BANK_OVER_1G, |
5182 | MDIO_OVER_1G_UP1, val); | |
ea4e040a | 5183 | |
cd2be89b | 5184 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5185 | MDIO_REG_BANK_OVER_1G, |
5186 | MDIO_OVER_1G_UP3, 0x400); | |
ea4e040a YR |
5187 | } |
5188 | ||
9045f6b4 YR |
5189 | static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, |
5190 | struct link_params *params, | |
5191 | u16 ieee_fc) | |
8c99e7b0 YR |
5192 | { |
5193 | struct bnx2x *bp = params->bp; | |
7846e471 | 5194 | u16 val; |
d231023e | 5195 | /* For AN, we are always publishing full duplex */ |
ea4e040a | 5196 | |
cd2be89b | 5197 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5198 | MDIO_REG_BANK_COMBO_IEEE0, |
5199 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); | |
cd2be89b | 5200 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5201 | MDIO_REG_BANK_CL73_IEEEB1, |
5202 | MDIO_CL73_IEEEB1_AN_ADV1, &val); | |
7846e471 YR |
5203 | val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; |
5204 | val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); | |
cd2be89b | 5205 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5206 | MDIO_REG_BANK_CL73_IEEEB1, |
5207 | MDIO_CL73_IEEEB1_AN_ADV1, val); | |
ea4e040a YR |
5208 | } |
5209 | ||
e10bc84d YR |
5210 | static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, |
5211 | struct link_params *params, | |
5212 | u8 enable_cl73) | |
ea4e040a YR |
5213 | { |
5214 | struct bnx2x *bp = params->bp; | |
3a36f2ef | 5215 | u16 mii_control; |
239d686d | 5216 | |
ea4e040a | 5217 | DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); |
3a36f2ef | 5218 | /* Enable and restart BAM/CL37 aneg */ |
ea4e040a | 5219 | |
239d686d | 5220 | if (enable_cl73) { |
cd2be89b | 5221 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5222 | MDIO_REG_BANK_CL73_IEEEB0, |
5223 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5224 | &mii_control); | |
239d686d | 5225 | |
cd2be89b | 5226 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5227 | MDIO_REG_BANK_CL73_IEEEB0, |
5228 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5229 | (mii_control | | |
5230 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | | |
5231 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); | |
239d686d EG |
5232 | } else { |
5233 | ||
cd2be89b | 5234 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5235 | MDIO_REG_BANK_COMBO_IEEE0, |
5236 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5237 | &mii_control); | |
239d686d EG |
5238 | DP(NETIF_MSG_LINK, |
5239 | "bnx2x_restart_autoneg mii_control before = 0x%x\n", | |
5240 | mii_control); | |
cd2be89b | 5241 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5242 | MDIO_REG_BANK_COMBO_IEEE0, |
5243 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5244 | (mii_control | | |
5245 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
5246 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); | |
239d686d | 5247 | } |
ea4e040a YR |
5248 | } |
5249 | ||
e10bc84d YR |
5250 | static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, |
5251 | struct link_params *params, | |
cd88ccee | 5252 | struct link_vars *vars) |
ea4e040a YR |
5253 | { |
5254 | struct bnx2x *bp = params->bp; | |
5255 | u16 control1; | |
5256 | ||
d231023e | 5257 | /* In SGMII mode, the unicore is always slave */ |
ea4e040a | 5258 | |
cd2be89b | 5259 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5260 | MDIO_REG_BANK_SERDES_DIGITAL, |
5261 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
5262 | &control1); | |
ea4e040a | 5263 | control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; |
d231023e | 5264 | /* Set sgmii mode (and not fiber) */ |
ea4e040a YR |
5265 | control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | |
5266 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | | |
5267 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); | |
cd2be89b | 5268 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5269 | MDIO_REG_BANK_SERDES_DIGITAL, |
5270 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
5271 | control1); | |
ea4e040a | 5272 | |
d231023e | 5273 | /* If forced speed */ |
8c99e7b0 | 5274 | if (!(vars->line_speed == SPEED_AUTO_NEG)) { |
d231023e | 5275 | /* Set speed, disable autoneg */ |
ea4e040a YR |
5276 | u16 mii_control; |
5277 | ||
cd2be89b | 5278 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5279 | MDIO_REG_BANK_COMBO_IEEE0, |
5280 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5281 | &mii_control); | |
ea4e040a YR |
5282 | mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
5283 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| | |
5284 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); | |
5285 | ||
8c99e7b0 | 5286 | switch (vars->line_speed) { |
ea4e040a YR |
5287 | case SPEED_100: |
5288 | mii_control |= | |
5289 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; | |
5290 | break; | |
5291 | case SPEED_1000: | |
5292 | mii_control |= | |
5293 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; | |
5294 | break; | |
5295 | case SPEED_10: | |
d231023e | 5296 | /* There is nothing to set for 10M */ |
ea4e040a YR |
5297 | break; |
5298 | default: | |
d231023e | 5299 | /* Invalid speed for SGMII */ |
8c99e7b0 YR |
5300 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
5301 | vars->line_speed); | |
ea4e040a YR |
5302 | break; |
5303 | } | |
5304 | ||
d231023e | 5305 | /* Setting the full duplex */ |
7aa0711f | 5306 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a YR |
5307 | mii_control |= |
5308 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; | |
cd2be89b | 5309 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5310 | MDIO_REG_BANK_COMBO_IEEE0, |
5311 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5312 | mii_control); | |
ea4e040a YR |
5313 | |
5314 | } else { /* AN mode */ | |
d231023e | 5315 | /* Enable and restart AN */ |
e10bc84d | 5316 | bnx2x_restart_autoneg(phy, params, 0); |
ea4e040a YR |
5317 | } |
5318 | } | |
5319 | ||
8f73f0b9 | 5320 | /* Link management |
ea4e040a | 5321 | */ |
fcf5b650 YR |
5322 | static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, |
5323 | struct link_params *params) | |
15ddd2d0 YR |
5324 | { |
5325 | struct bnx2x *bp = params->bp; | |
5326 | u16 pd_10g, status2_1000x; | |
7aa0711f YR |
5327 | if (phy->req_line_speed != SPEED_AUTO_NEG) |
5328 | return 0; | |
cd2be89b | 5329 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5330 | MDIO_REG_BANK_SERDES_DIGITAL, |
5331 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
5332 | &status2_1000x); | |
cd2be89b | 5333 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5334 | MDIO_REG_BANK_SERDES_DIGITAL, |
5335 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
5336 | &status2_1000x); | |
15ddd2d0 YR |
5337 | if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { |
5338 | DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", | |
5339 | params->port); | |
5340 | return 1; | |
5341 | } | |
5342 | ||
cd2be89b | 5343 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5344 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
5345 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, | |
5346 | &pd_10g); | |
15ddd2d0 YR |
5347 | |
5348 | if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { | |
5349 | DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", | |
5350 | params->port); | |
5351 | return 1; | |
5352 | } | |
5353 | return 0; | |
5354 | } | |
ea4e040a | 5355 | |
9e7e8399 MY |
5356 | static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, |
5357 | struct link_params *params, | |
5358 | struct link_vars *vars, | |
5359 | u32 gp_status) | |
5360 | { | |
5361 | u16 ld_pause; /* local driver */ | |
5362 | u16 lp_pause; /* link partner */ | |
5363 | u16 pause_result; | |
5364 | struct bnx2x *bp = params->bp; | |
5365 | if ((gp_status & | |
5366 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
5367 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == | |
5368 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
5369 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { | |
5370 | ||
5371 | CL22_RD_OVER_CL45(bp, phy, | |
5372 | MDIO_REG_BANK_CL73_IEEEB1, | |
5373 | MDIO_CL73_IEEEB1_AN_ADV1, | |
5374 | &ld_pause); | |
5375 | CL22_RD_OVER_CL45(bp, phy, | |
5376 | MDIO_REG_BANK_CL73_IEEEB1, | |
5377 | MDIO_CL73_IEEEB1_AN_LP_ADV1, | |
5378 | &lp_pause); | |
5379 | pause_result = (ld_pause & | |
5380 | MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; | |
5381 | pause_result |= (lp_pause & | |
5382 | MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; | |
5383 | DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); | |
5384 | } else { | |
5385 | CL22_RD_OVER_CL45(bp, phy, | |
5386 | MDIO_REG_BANK_COMBO_IEEE0, | |
5387 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, | |
5388 | &ld_pause); | |
5389 | CL22_RD_OVER_CL45(bp, phy, | |
5390 | MDIO_REG_BANK_COMBO_IEEE0, | |
5391 | MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, | |
5392 | &lp_pause); | |
5393 | pause_result = (ld_pause & | |
5394 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; | |
5395 | pause_result |= (lp_pause & | |
5396 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; | |
5397 | DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); | |
5398 | } | |
5399 | bnx2x_pause_resolve(vars, pause_result); | |
5400 | ||
5401 | } | |
5402 | ||
e10bc84d YR |
5403 | static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, |
5404 | struct link_params *params, | |
5405 | struct link_vars *vars, | |
5406 | u32 gp_status) | |
ea4e040a YR |
5407 | { |
5408 | struct bnx2x *bp = params->bp; | |
c0700f90 | 5409 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a | 5410 | |
d231023e | 5411 | /* Resolve from gp_status in case of AN complete and not sgmii */ |
9e7e8399 MY |
5412 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { |
5413 | /* Update the advertised flow-controled of LD/LP in AN */ | |
5414 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
5415 | bnx2x_update_adv_fc(phy, params, vars, gp_status); | |
5416 | /* But set the flow-control result as the requested one */ | |
7aa0711f | 5417 | vars->flow_ctrl = phy->req_flow_ctrl; |
9e7e8399 | 5418 | } else if (phy->req_line_speed != SPEED_AUTO_NEG) |
7aa0711f YR |
5419 | vars->flow_ctrl = params->req_fc_auto_adv; |
5420 | else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && | |
5421 | (!(vars->phy_flags & PHY_SGMII_FLAG))) { | |
e10bc84d | 5422 | if (bnx2x_direct_parallel_detect_used(phy, params)) { |
15ddd2d0 YR |
5423 | vars->flow_ctrl = params->req_fc_auto_adv; |
5424 | return; | |
5425 | } | |
9e7e8399 | 5426 | bnx2x_update_adv_fc(phy, params, vars, gp_status); |
ea4e040a YR |
5427 | } |
5428 | DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); | |
5429 | } | |
5430 | ||
e10bc84d YR |
5431 | static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, |
5432 | struct link_params *params) | |
239d686d EG |
5433 | { |
5434 | struct bnx2x *bp = params->bp; | |
9045f6b4 | 5435 | u16 rx_status, ustat_val, cl37_fsm_received; |
239d686d EG |
5436 | DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); |
5437 | /* Step 1: Make sure signal is detected */ | |
cd2be89b | 5438 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5439 | MDIO_REG_BANK_RX0, |
5440 | MDIO_RX0_RX_STATUS, | |
5441 | &rx_status); | |
239d686d EG |
5442 | if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != |
5443 | (MDIO_RX0_RX_STATUS_SIGDET)) { | |
5444 | DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." | |
5445 | "rx_status(0x80b0) = 0x%x\n", rx_status); | |
cd2be89b | 5446 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5447 | MDIO_REG_BANK_CL73_IEEEB0, |
5448 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5449 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); | |
239d686d EG |
5450 | return; |
5451 | } | |
5452 | /* Step 2: Check CL73 state machine */ | |
cd2be89b | 5453 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5454 | MDIO_REG_BANK_CL73_USERB0, |
5455 | MDIO_CL73_USERB0_CL73_USTAT1, | |
5456 | &ustat_val); | |
239d686d EG |
5457 | if ((ustat_val & |
5458 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
5459 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != | |
5460 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
5461 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { | |
5462 | DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " | |
5463 | "ustat_val(0x8371) = 0x%x\n", ustat_val); | |
5464 | return; | |
5465 | } | |
8f73f0b9 | 5466 | /* Step 3: Check CL37 Message Pages received to indicate LP |
2cf7acf9 YR |
5467 | * supports only CL37 |
5468 | */ | |
cd2be89b | 5469 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5470 | MDIO_REG_BANK_REMOTE_PHY, |
5471 | MDIO_REMOTE_PHY_MISC_RX_STATUS, | |
9045f6b4 YR |
5472 | &cl37_fsm_received); |
5473 | if ((cl37_fsm_received & | |
239d686d EG |
5474 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | |
5475 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != | |
5476 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | | |
5477 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { | |
5478 | DP(NETIF_MSG_LINK, "No CL37 FSM were received. " | |
5479 | "misc_rx_status(0x8330) = 0x%x\n", | |
9045f6b4 | 5480 | cl37_fsm_received); |
239d686d EG |
5481 | return; |
5482 | } | |
8f73f0b9 | 5483 | /* The combined cl37/cl73 fsm state information indicating that |
2cf7acf9 YR |
5484 | * we are connected to a device which does not support cl73, but |
5485 | * does support cl37 BAM. In this case we disable cl73 and | |
5486 | * restart cl37 auto-neg | |
5487 | */ | |
5488 | ||
239d686d | 5489 | /* Disable CL73 */ |
cd2be89b | 5490 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5491 | MDIO_REG_BANK_CL73_IEEEB0, |
5492 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5493 | 0); | |
239d686d | 5494 | /* Restart CL37 autoneg */ |
e10bc84d | 5495 | bnx2x_restart_autoneg(phy, params, 0); |
239d686d EG |
5496 | DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); |
5497 | } | |
7aa0711f YR |
5498 | |
5499 | static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, | |
5500 | struct link_params *params, | |
5501 | struct link_vars *vars, | |
5502 | u32 gp_status) | |
5503 | { | |
5504 | if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) | |
5505 | vars->link_status |= | |
5506 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5507 | ||
5508 | if (bnx2x_direct_parallel_detect_used(phy, params)) | |
5509 | vars->link_status |= | |
5510 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
5511 | } | |
3c9ada22 YR |
5512 | static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, |
5513 | struct link_params *params, | |
5514 | struct link_vars *vars, | |
5515 | u16 is_link_up, | |
5516 | u16 speed_mask, | |
5517 | u16 is_duplex) | |
ea4e040a YR |
5518 | { |
5519 | struct bnx2x *bp = params->bp; | |
7aa0711f YR |
5520 | if (phy->req_line_speed == SPEED_AUTO_NEG) |
5521 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
3c9ada22 YR |
5522 | if (is_link_up) { |
5523 | DP(NETIF_MSG_LINK, "phy link up\n"); | |
ea4e040a YR |
5524 | |
5525 | vars->phy_link_up = 1; | |
5526 | vars->link_status |= LINK_STATUS_LINK_UP; | |
5527 | ||
3c9ada22 | 5528 | switch (speed_mask) { |
ea4e040a | 5529 | case GP_STATUS_10M: |
3c9ada22 | 5530 | vars->line_speed = SPEED_10; |
430d172a | 5531 | if (is_duplex == DUPLEX_FULL) |
ea4e040a YR |
5532 | vars->link_status |= LINK_10TFD; |
5533 | else | |
5534 | vars->link_status |= LINK_10THD; | |
5535 | break; | |
5536 | ||
5537 | case GP_STATUS_100M: | |
3c9ada22 | 5538 | vars->line_speed = SPEED_100; |
430d172a | 5539 | if (is_duplex == DUPLEX_FULL) |
ea4e040a YR |
5540 | vars->link_status |= LINK_100TXFD; |
5541 | else | |
5542 | vars->link_status |= LINK_100TXHD; | |
5543 | break; | |
5544 | ||
5545 | case GP_STATUS_1G: | |
5546 | case GP_STATUS_1G_KX: | |
3c9ada22 | 5547 | vars->line_speed = SPEED_1000; |
430d172a | 5548 | if (is_duplex == DUPLEX_FULL) |
ea4e040a YR |
5549 | vars->link_status |= LINK_1000TFD; |
5550 | else | |
5551 | vars->link_status |= LINK_1000THD; | |
5552 | break; | |
5553 | ||
5554 | case GP_STATUS_2_5G: | |
3c9ada22 | 5555 | vars->line_speed = SPEED_2500; |
430d172a | 5556 | if (is_duplex == DUPLEX_FULL) |
ea4e040a YR |
5557 | vars->link_status |= LINK_2500TFD; |
5558 | else | |
5559 | vars->link_status |= LINK_2500THD; | |
5560 | break; | |
5561 | ||
5562 | case GP_STATUS_5G: | |
5563 | case GP_STATUS_6G: | |
5564 | DP(NETIF_MSG_LINK, | |
5565 | "link speed unsupported gp_status 0x%x\n", | |
3c9ada22 | 5566 | speed_mask); |
ea4e040a | 5567 | return -EINVAL; |
ab6ad5a4 | 5568 | |
ea4e040a YR |
5569 | case GP_STATUS_10G_KX4: |
5570 | case GP_STATUS_10G_HIG: | |
5571 | case GP_STATUS_10G_CX4: | |
3c9ada22 YR |
5572 | case GP_STATUS_10G_KR: |
5573 | case GP_STATUS_10G_SFI: | |
5574 | case GP_STATUS_10G_XFI: | |
5575 | vars->line_speed = SPEED_10000; | |
ea4e040a YR |
5576 | vars->link_status |= LINK_10GTFD; |
5577 | break; | |
3c9ada22 | 5578 | case GP_STATUS_20G_DXGXS: |
4e7b4997 | 5579 | case GP_STATUS_20G_KR2: |
3c9ada22 YR |
5580 | vars->line_speed = SPEED_20000; |
5581 | vars->link_status |= LINK_20GTFD; | |
5582 | break; | |
ea4e040a YR |
5583 | default: |
5584 | DP(NETIF_MSG_LINK, | |
5585 | "link speed unsupported gp_status 0x%x\n", | |
3c9ada22 | 5586 | speed_mask); |
ab6ad5a4 | 5587 | return -EINVAL; |
ea4e040a | 5588 | } |
ea4e040a YR |
5589 | } else { /* link_down */ |
5590 | DP(NETIF_MSG_LINK, "phy link down\n"); | |
5591 | ||
5592 | vars->phy_link_up = 0; | |
57963ed9 | 5593 | |
ea4e040a | 5594 | vars->duplex = DUPLEX_FULL; |
c0700f90 | 5595 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a | 5596 | vars->mac_type = MAC_TYPE_NONE; |
3c9ada22 YR |
5597 | } |
5598 | DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", | |
5599 | vars->phy_link_up, vars->line_speed); | |
5600 | return 0; | |
5601 | } | |
5602 | ||
5603 | static int bnx2x_link_settings_status(struct bnx2x_phy *phy, | |
5604 | struct link_params *params, | |
5605 | struct link_vars *vars) | |
5606 | { | |
3c9ada22 YR |
5607 | struct bnx2x *bp = params->bp; |
5608 | ||
5609 | u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; | |
5610 | int rc = 0; | |
5611 | ||
5612 | /* Read gp_status */ | |
5613 | CL22_RD_OVER_CL45(bp, phy, | |
5614 | MDIO_REG_BANK_GP_STATUS, | |
5615 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
5616 | &gp_status); | |
5617 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) | |
5618 | duplex = DUPLEX_FULL; | |
5619 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) | |
5620 | link_up = 1; | |
5621 | speed_mask = gp_status & GP_STATUS_SPEED_MASK; | |
5622 | DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", | |
5623 | gp_status, link_up, speed_mask); | |
5624 | rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, | |
5625 | duplex); | |
5626 | if (rc == -EINVAL) | |
5627 | return rc; | |
239d686d | 5628 | |
3c9ada22 YR |
5629 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { |
5630 | if (SINGLE_MEDIA_DIRECT(params)) { | |
430d172a | 5631 | vars->duplex = duplex; |
3c9ada22 YR |
5632 | bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); |
5633 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
5634 | bnx2x_xgxs_an_resolve(phy, params, vars, | |
5635 | gp_status); | |
5636 | } | |
d231023e | 5637 | } else { /* Link_down */ |
c18aa15d YR |
5638 | if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
5639 | SINGLE_MEDIA_DIRECT(params)) { | |
239d686d | 5640 | /* Check signal is detected */ |
c18aa15d | 5641 | bnx2x_check_fallback_to_cl37(phy, params); |
239d686d | 5642 | } |
ea4e040a YR |
5643 | } |
5644 | ||
9e7e8399 MY |
5645 | /* Read LP advertised speeds*/ |
5646 | if (SINGLE_MEDIA_DIRECT(params) && | |
5647 | (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { | |
5648 | u16 val; | |
5649 | ||
5650 | CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, | |
5651 | MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); | |
5652 | ||
5653 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) | |
5654 | vars->link_status |= | |
5655 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
5656 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | | |
5657 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) | |
5658 | vars->link_status |= | |
5659 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5660 | ||
5661 | CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, | |
5662 | MDIO_OVER_1G_LP_UP1, &val); | |
5663 | ||
5664 | if (val & MDIO_OVER_1G_UP1_2_5G) | |
5665 | vars->link_status |= | |
5666 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; | |
5667 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) | |
5668 | vars->link_status |= | |
5669 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5670 | } | |
5671 | ||
a22f0788 YR |
5672 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", |
5673 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
ea4e040a YR |
5674 | return rc; |
5675 | } | |
5676 | ||
3c9ada22 YR |
5677 | static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, |
5678 | struct link_params *params, | |
5679 | struct link_vars *vars) | |
5680 | { | |
3c9ada22 | 5681 | struct bnx2x *bp = params->bp; |
3c9ada22 YR |
5682 | u8 lane; |
5683 | u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; | |
5684 | int rc = 0; | |
5685 | lane = bnx2x_get_warpcore_lane(phy, params); | |
5686 | /* Read gp_status */ | |
4e7b4997 YR |
5687 | if ((params->loopback_mode) && |
5688 | (phy->flags & FLAGS_WC_DUAL_MODE)) { | |
5689 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5690 | MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); | |
5691 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5692 | MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); | |
5693 | link_up &= 0x1; | |
5694 | } else if ((phy->req_line_speed > SPEED_10000) && | |
5695 | (phy->supported & SUPPORTED_20000baseMLD2_Full)) { | |
3c9ada22 YR |
5696 | u16 temp_link_up; |
5697 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5698 | 1, &temp_link_up); | |
5699 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5700 | 1, &link_up); | |
5701 | DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", | |
5702 | temp_link_up, link_up); | |
5703 | link_up &= (1<<2); | |
5704 | if (link_up) | |
5705 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
5706 | } else { | |
5707 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4e7b4997 YR |
5708 | MDIO_WC_REG_GP2_STATUS_GP_2_1, |
5709 | &gp_status1); | |
3c9ada22 | 5710 | DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); |
4e7b4997 YR |
5711 | /* Check for either KR, 1G, or AN up. */ |
5712 | link_up = ((gp_status1 >> 8) | | |
5713 | (gp_status1 >> 12) | | |
5714 | (gp_status1)) & | |
5715 | (1 << lane); | |
5716 | if (phy->supported & SUPPORTED_20000baseKR2_Full) { | |
5717 | u16 an_link; | |
5718 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
5719 | MDIO_AN_REG_STATUS, &an_link); | |
5720 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
5721 | MDIO_AN_REG_STATUS, &an_link); | |
5722 | link_up |= (an_link & (1<<2)); | |
5723 | } | |
3c9ada22 YR |
5724 | if (link_up && SINGLE_MEDIA_DIRECT(params)) { |
5725 | u16 pd, gp_status4; | |
5726 | if (phy->req_line_speed == SPEED_AUTO_NEG) { | |
5727 | /* Check Autoneg complete */ | |
5728 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5729 | MDIO_WC_REG_GP2_STATUS_GP_2_4, | |
5730 | &gp_status4); | |
5731 | if (gp_status4 & ((1<<12)<<lane)) | |
5732 | vars->link_status |= | |
5733 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5734 | ||
5735 | /* Check parallel detect used */ | |
5736 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5737 | MDIO_WC_REG_PAR_DET_10G_STATUS, | |
5738 | &pd); | |
5739 | if (pd & (1<<15)) | |
5740 | vars->link_status |= | |
5741 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
5742 | } | |
5743 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
430d172a | 5744 | vars->duplex = duplex; |
3c9ada22 YR |
5745 | } |
5746 | } | |
5747 | ||
9e7e8399 MY |
5748 | if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && |
5749 | SINGLE_MEDIA_DIRECT(params)) { | |
5750 | u16 val; | |
5751 | ||
5752 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
5753 | MDIO_AN_REG_LP_AUTO_NEG2, &val); | |
5754 | ||
5755 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) | |
5756 | vars->link_status |= | |
5757 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
5758 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | | |
5759 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) | |
5760 | vars->link_status |= | |
5761 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5762 | ||
5763 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5764 | MDIO_WC_REG_DIGITAL3_LP_UP1, &val); | |
5765 | ||
5766 | if (val & MDIO_OVER_1G_UP1_2_5G) | |
5767 | vars->link_status |= | |
5768 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; | |
5769 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) | |
5770 | vars->link_status |= | |
5771 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5772 | ||
5773 | } | |
5774 | ||
5775 | ||
3c9ada22 YR |
5776 | if (lane < 2) { |
5777 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5778 | MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); | |
5779 | } else { | |
5780 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5781 | MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); | |
5782 | } | |
5783 | DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); | |
5784 | ||
5785 | if ((lane & 1) == 0) | |
5786 | gp_speed <<= 8; | |
5787 | gp_speed &= 0x3f00; | |
4e7b4997 | 5788 | link_up = !!link_up; |
3c9ada22 YR |
5789 | |
5790 | rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, | |
5791 | duplex); | |
5792 | ||
b6a9c1ef YR |
5793 | /* In case of KR link down, start up the recovering procedure */ |
5794 | if ((!link_up) && (phy->media_type == ETH_PHY_KR) && | |
5795 | (!(phy->flags & FLAGS_WC_DUAL_MODE))) | |
5796 | vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; | |
5797 | ||
3c9ada22 YR |
5798 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", |
5799 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
5800 | return rc; | |
5801 | } | |
ed8680a7 | 5802 | static void bnx2x_set_gmii_tx_driver(struct link_params *params) |
ea4e040a YR |
5803 | { |
5804 | struct bnx2x *bp = params->bp; | |
e10bc84d | 5805 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; |
ea4e040a YR |
5806 | u16 lp_up2; |
5807 | u16 tx_driver; | |
c2c8b03e | 5808 | u16 bank; |
ea4e040a | 5809 | |
d231023e | 5810 | /* Read precomp */ |
cd2be89b | 5811 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5812 | MDIO_REG_BANK_OVER_1G, |
5813 | MDIO_OVER_1G_LP_UP2, &lp_up2); | |
ea4e040a | 5814 | |
d231023e | 5815 | /* Bits [10:7] at lp_up2, positioned at [15:12] */ |
ea4e040a YR |
5816 | lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> |
5817 | MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << | |
5818 | MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); | |
5819 | ||
c2c8b03e EG |
5820 | if (lp_up2 == 0) |
5821 | return; | |
5822 | ||
5823 | for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; | |
5824 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { | |
cd2be89b | 5825 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5826 | bank, |
5827 | MDIO_TX0_TX_DRIVER, &tx_driver); | |
c2c8b03e | 5828 | |
d231023e | 5829 | /* Replace tx_driver bits [15:12] */ |
c2c8b03e EG |
5830 | if (lp_up2 != |
5831 | (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { | |
5832 | tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; | |
5833 | tx_driver |= lp_up2; | |
cd2be89b | 5834 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5835 | bank, |
5836 | MDIO_TX0_TX_DRIVER, tx_driver); | |
c2c8b03e | 5837 | } |
ea4e040a YR |
5838 | } |
5839 | } | |
5840 | ||
fcf5b650 YR |
5841 | static int bnx2x_emac_program(struct link_params *params, |
5842 | struct link_vars *vars) | |
ea4e040a YR |
5843 | { |
5844 | struct bnx2x *bp = params->bp; | |
5845 | u8 port = params->port; | |
5846 | u16 mode = 0; | |
5847 | ||
5848 | DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); | |
5849 | bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + | |
cd88ccee YR |
5850 | EMAC_REG_EMAC_MODE, |
5851 | (EMAC_MODE_25G_MODE | | |
5852 | EMAC_MODE_PORT_MII_10M | | |
5853 | EMAC_MODE_HALF_DUPLEX)); | |
b7737c9b | 5854 | switch (vars->line_speed) { |
ea4e040a YR |
5855 | case SPEED_10: |
5856 | mode |= EMAC_MODE_PORT_MII_10M; | |
5857 | break; | |
5858 | ||
5859 | case SPEED_100: | |
5860 | mode |= EMAC_MODE_PORT_MII; | |
5861 | break; | |
5862 | ||
5863 | case SPEED_1000: | |
5864 | mode |= EMAC_MODE_PORT_GMII; | |
5865 | break; | |
5866 | ||
5867 | case SPEED_2500: | |
5868 | mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); | |
5869 | break; | |
5870 | ||
5871 | default: | |
5872 | /* 10G not valid for EMAC */ | |
b7737c9b YR |
5873 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
5874 | vars->line_speed); | |
ea4e040a YR |
5875 | return -EINVAL; |
5876 | } | |
5877 | ||
b7737c9b | 5878 | if (vars->duplex == DUPLEX_HALF) |
ea4e040a YR |
5879 | mode |= EMAC_MODE_HALF_DUPLEX; |
5880 | bnx2x_bits_en(bp, | |
cd88ccee YR |
5881 | GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, |
5882 | mode); | |
ea4e040a | 5883 | |
7f02c4ad | 5884 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
ea4e040a YR |
5885 | return 0; |
5886 | } | |
5887 | ||
de6eae1f YR |
5888 | static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, |
5889 | struct link_params *params) | |
b7737c9b | 5890 | { |
de6eae1f YR |
5891 | |
5892 | u16 bank, i = 0; | |
5893 | struct bnx2x *bp = params->bp; | |
5894 | ||
5895 | for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; | |
5896 | bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { | |
cd2be89b | 5897 | CL22_WR_OVER_CL45(bp, phy, |
de6eae1f YR |
5898 | bank, |
5899 | MDIO_RX0_RX_EQ_BOOST, | |
5900 | phy->rx_preemphasis[i]); | |
5901 | } | |
5902 | ||
5903 | for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; | |
5904 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { | |
cd2be89b | 5905 | CL22_WR_OVER_CL45(bp, phy, |
de6eae1f YR |
5906 | bank, |
5907 | MDIO_TX0_TX_DRIVER, | |
5908 | phy->tx_preemphasis[i]); | |
5909 | } | |
5910 | } | |
5911 | ||
ec146a6f YR |
5912 | static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, |
5913 | struct link_params *params, | |
5914 | struct link_vars *vars) | |
de6eae1f YR |
5915 | { |
5916 | struct bnx2x *bp = params->bp; | |
5917 | u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || | |
5918 | (params->loopback_mode == LOOPBACK_XGXS)); | |
5919 | if (!(vars->phy_flags & PHY_SGMII_FLAG)) { | |
5920 | if (SINGLE_MEDIA_DIRECT(params) && | |
5921 | (params->feature_config_flags & | |
5922 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) | |
5923 | bnx2x_set_preemphasis(phy, params); | |
5924 | ||
d231023e | 5925 | /* Forced speed requested? */ |
de6eae1f YR |
5926 | if (vars->line_speed != SPEED_AUTO_NEG || |
5927 | (SINGLE_MEDIA_DIRECT(params) && | |
cd88ccee | 5928 | params->loopback_mode == LOOPBACK_EXT)) { |
de6eae1f YR |
5929 | DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); |
5930 | ||
d231023e | 5931 | /* Disable autoneg */ |
de6eae1f YR |
5932 | bnx2x_set_autoneg(phy, params, vars, 0); |
5933 | ||
d231023e | 5934 | /* Program speed and duplex */ |
de6eae1f YR |
5935 | bnx2x_program_serdes(phy, params, vars); |
5936 | ||
5937 | } else { /* AN_mode */ | |
5938 | DP(NETIF_MSG_LINK, "not SGMII, AN\n"); | |
5939 | ||
5940 | /* AN enabled */ | |
9045f6b4 | 5941 | bnx2x_set_brcm_cl37_advertisement(phy, params); |
de6eae1f | 5942 | |
d231023e | 5943 | /* Program duplex & pause advertisement (for aneg) */ |
9045f6b4 YR |
5944 | bnx2x_set_ieee_aneg_advertisement(phy, params, |
5945 | vars->ieee_fc); | |
de6eae1f | 5946 | |
d231023e | 5947 | /* Enable autoneg */ |
de6eae1f YR |
5948 | bnx2x_set_autoneg(phy, params, vars, enable_cl73); |
5949 | ||
d231023e | 5950 | /* Enable and restart AN */ |
de6eae1f YR |
5951 | bnx2x_restart_autoneg(phy, params, enable_cl73); |
5952 | } | |
5953 | ||
5954 | } else { /* SGMII mode */ | |
5955 | DP(NETIF_MSG_LINK, "SGMII\n"); | |
5956 | ||
5957 | bnx2x_initialize_sgmii_process(phy, params, vars); | |
5958 | } | |
5959 | } | |
5960 | ||
ec146a6f YR |
5961 | static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, |
5962 | struct link_params *params, | |
5963 | struct link_vars *vars) | |
b7737c9b | 5964 | { |
fcf5b650 | 5965 | int rc; |
ec146a6f | 5966 | vars->phy_flags |= PHY_XGXS_FLAG; |
b7737c9b YR |
5967 | if ((phy->req_line_speed && |
5968 | ((phy->req_line_speed == SPEED_100) || | |
5969 | (phy->req_line_speed == SPEED_10))) || | |
5970 | (!phy->req_line_speed && | |
5971 | (phy->speed_cap_mask >= | |
5972 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && | |
5973 | (phy->speed_cap_mask < | |
ec146a6f YR |
5974 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || |
5975 | (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) | |
b7737c9b YR |
5976 | vars->phy_flags |= PHY_SGMII_FLAG; |
5977 | else | |
5978 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
5979 | ||
5980 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
ec146a6f YR |
5981 | bnx2x_set_aer_mmd(params, phy); |
5982 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) | |
5983 | bnx2x_set_master_ln(params, phy); | |
b7737c9b YR |
5984 | |
5985 | rc = bnx2x_reset_unicore(params, phy, 0); | |
d231023e YM |
5986 | /* Reset the SerDes and wait for reset bit return low */ |
5987 | if (rc) | |
b7737c9b YR |
5988 | return rc; |
5989 | ||
ec146a6f | 5990 | bnx2x_set_aer_mmd(params, phy); |
d231023e | 5991 | /* Setting the masterLn_def again after the reset */ |
ec146a6f YR |
5992 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { |
5993 | bnx2x_set_master_ln(params, phy); | |
5994 | bnx2x_set_swap_lanes(params, phy); | |
5995 | } | |
b7737c9b YR |
5996 | |
5997 | return rc; | |
5998 | } | |
c18aa15d | 5999 | |
de6eae1f | 6000 | static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, |
6d870c39 YR |
6001 | struct bnx2x_phy *phy, |
6002 | struct link_params *params) | |
ea4e040a | 6003 | { |
de6eae1f | 6004 | u16 cnt, ctrl; |
25985edc | 6005 | /* Wait for soft reset to get cleared up to 1 sec */ |
de6eae1f | 6006 | for (cnt = 0; cnt < 1000; cnt++) { |
52c4d6c4 | 6007 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
6583e33b YR |
6008 | bnx2x_cl22_read(bp, phy, |
6009 | MDIO_PMA_REG_CTRL, &ctrl); | |
6010 | else | |
6011 | bnx2x_cl45_read(bp, phy, | |
6012 | MDIO_PMA_DEVAD, | |
6013 | MDIO_PMA_REG_CTRL, &ctrl); | |
de6eae1f YR |
6014 | if (!(ctrl & (1<<15))) |
6015 | break; | |
d231023e | 6016 | usleep_range(1000, 2000); |
de6eae1f | 6017 | } |
6d870c39 YR |
6018 | |
6019 | if (cnt == 1000) | |
6020 | netdev_err(bp->dev, "Warning: PHY was not initialized," | |
6021 | " Port %d\n", | |
6022 | params->port); | |
de6eae1f YR |
6023 | DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); |
6024 | return cnt; | |
ea4e040a YR |
6025 | } |
6026 | ||
de6eae1f | 6027 | static void bnx2x_link_int_enable(struct link_params *params) |
a35da8db | 6028 | { |
de6eae1f YR |
6029 | u8 port = params->port; |
6030 | u32 mask; | |
6031 | struct bnx2x *bp = params->bp; | |
c18aa15d | 6032 | |
2cf7acf9 | 6033 | /* Setting the status to report on link up for either XGXS or SerDes */ |
3c9ada22 YR |
6034 | if (CHIP_IS_E3(bp)) { |
6035 | mask = NIG_MASK_XGXS0_LINK_STATUS; | |
6036 | if (!(SINGLE_MEDIA_DIRECT(params))) | |
6037 | mask |= NIG_MASK_MI_INT; | |
6038 | } else if (params->switch_cfg == SWITCH_CFG_10G) { | |
de6eae1f YR |
6039 | mask = (NIG_MASK_XGXS0_LINK10G | |
6040 | NIG_MASK_XGXS0_LINK_STATUS); | |
6041 | DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); | |
6042 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
6043 | params->phy[INT_PHY].type != | |
6044 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { | |
6045 | mask |= NIG_MASK_MI_INT; | |
6046 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
6047 | } | |
6048 | ||
6049 | } else { /* SerDes */ | |
6050 | mask = NIG_MASK_SERDES0_LINK_STATUS; | |
6051 | DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); | |
6052 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
6053 | params->phy[INT_PHY].type != | |
6054 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { | |
6055 | mask |= NIG_MASK_MI_INT; | |
6056 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
6057 | } | |
6058 | } | |
6059 | bnx2x_bits_en(bp, | |
6060 | NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | |
6061 | mask); | |
6062 | ||
6063 | DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, | |
6064 | (params->switch_cfg == SWITCH_CFG_10G), | |
6065 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
6066 | DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", | |
6067 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
6068 | REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), | |
6069 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); | |
6070 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", | |
6071 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
6072 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
a35da8db EG |
6073 | } |
6074 | ||
a22f0788 YR |
6075 | static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, |
6076 | u8 exp_mi_int) | |
a35da8db | 6077 | { |
a22f0788 YR |
6078 | u32 latch_status = 0; |
6079 | ||
8f73f0b9 | 6080 | /* Disable the MI INT ( external phy int ) by writing 1 to the |
a22f0788 YR |
6081 | * status register. Link down indication is high-active-signal, |
6082 | * so in this case we need to write the status to clear the XOR | |
de6eae1f YR |
6083 | */ |
6084 | /* Read Latched signals */ | |
6085 | latch_status = REG_RD(bp, | |
a22f0788 YR |
6086 | NIG_REG_LATCH_STATUS_0 + port*8); |
6087 | DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); | |
de6eae1f | 6088 | /* Handle only those with latched-signal=up.*/ |
a22f0788 YR |
6089 | if (exp_mi_int) |
6090 | bnx2x_bits_en(bp, | |
6091 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
6092 | + port*4, | |
6093 | NIG_STATUS_EMAC0_MI_INT); | |
6094 | else | |
6095 | bnx2x_bits_dis(bp, | |
6096 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
6097 | + port*4, | |
6098 | NIG_STATUS_EMAC0_MI_INT); | |
6099 | ||
de6eae1f | 6100 | if (latch_status & 1) { |
a22f0788 | 6101 | |
de6eae1f YR |
6102 | /* For all latched-signal=up : Re-Arm Latch signals */ |
6103 | REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, | |
cd88ccee | 6104 | (latch_status & 0xfffe) | (latch_status & 1)); |
de6eae1f | 6105 | } |
a22f0788 | 6106 | /* For all latched-signal=up,Write original_signal to status */ |
a35da8db EG |
6107 | } |
6108 | ||
de6eae1f | 6109 | static void bnx2x_link_int_ack(struct link_params *params, |
3c9ada22 | 6110 | struct link_vars *vars, u8 is_10g_plus) |
b1607af5 | 6111 | { |
e10bc84d | 6112 | struct bnx2x *bp = params->bp; |
de6eae1f | 6113 | u8 port = params->port; |
3c9ada22 | 6114 | u32 mask; |
8f73f0b9 | 6115 | /* First reset all status we assume only one line will be |
2cf7acf9 YR |
6116 | * change at a time |
6117 | */ | |
de6eae1f | 6118 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
cd88ccee YR |
6119 | (NIG_STATUS_XGXS0_LINK10G | |
6120 | NIG_STATUS_XGXS0_LINK_STATUS | | |
6121 | NIG_STATUS_SERDES0_LINK_STATUS)); | |
de6eae1f | 6122 | if (vars->phy_link_up) { |
3c9ada22 YR |
6123 | if (USES_WARPCORE(bp)) |
6124 | mask = NIG_STATUS_XGXS0_LINK_STATUS; | |
6125 | else { | |
6126 | if (is_10g_plus) | |
6127 | mask = NIG_STATUS_XGXS0_LINK10G; | |
6128 | else if (params->switch_cfg == SWITCH_CFG_10G) { | |
8f73f0b9 | 6129 | /* Disable the link interrupt by writing 1 to |
3c9ada22 YR |
6130 | * the relevant lane in the status register |
6131 | */ | |
6132 | u32 ser_lane = | |
6133 | ((params->lane_config & | |
de6eae1f YR |
6134 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
6135 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
3c9ada22 YR |
6136 | mask = ((1 << ser_lane) << |
6137 | NIG_STATUS_XGXS0_LINK_STATUS_SIZE); | |
6138 | } else | |
6139 | mask = NIG_STATUS_SERDES0_LINK_STATUS; | |
de6eae1f | 6140 | } |
3c9ada22 YR |
6141 | DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", |
6142 | mask); | |
6143 | bnx2x_bits_en(bp, | |
6144 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | |
6145 | mask); | |
ea4e040a | 6146 | } |
ea4e040a | 6147 | } |
ea4e040a | 6148 | |
fcf5b650 | 6149 | static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) |
de6eae1f YR |
6150 | { |
6151 | u8 *str_ptr = str; | |
6152 | u32 mask = 0xf0000000; | |
6153 | u8 shift = 8*4; | |
6154 | u8 digit; | |
a22f0788 | 6155 | u8 remove_leading_zeros = 1; |
de6eae1f YR |
6156 | if (*len < 10) { |
6157 | /* Need more than 10chars for this format */ | |
6158 | *str_ptr = '\0'; | |
a22f0788 | 6159 | (*len)--; |
de6eae1f | 6160 | return -EINVAL; |
ea4e040a | 6161 | } |
de6eae1f | 6162 | while (shift > 0) { |
ea4e040a | 6163 | |
de6eae1f YR |
6164 | shift -= 4; |
6165 | digit = ((num & mask) >> shift); | |
a22f0788 YR |
6166 | if (digit == 0 && remove_leading_zeros) { |
6167 | mask = mask >> 4; | |
6168 | continue; | |
6169 | } else if (digit < 0xa) | |
de6eae1f YR |
6170 | *str_ptr = digit + '0'; |
6171 | else | |
6172 | *str_ptr = digit - 0xa + 'a'; | |
a22f0788 | 6173 | remove_leading_zeros = 0; |
de6eae1f | 6174 | str_ptr++; |
a22f0788 | 6175 | (*len)--; |
de6eae1f YR |
6176 | mask = mask >> 4; |
6177 | if (shift == 4*4) { | |
a22f0788 | 6178 | *str_ptr = '.'; |
de6eae1f | 6179 | str_ptr++; |
a22f0788 YR |
6180 | (*len)--; |
6181 | remove_leading_zeros = 1; | |
ea4e040a | 6182 | } |
ea4e040a | 6183 | } |
de6eae1f | 6184 | return 0; |
ea4e040a YR |
6185 | } |
6186 | ||
a22f0788 | 6187 | |
fcf5b650 | 6188 | static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
ea4e040a | 6189 | { |
de6eae1f YR |
6190 | str[0] = '\0'; |
6191 | (*len)--; | |
6192 | return 0; | |
6193 | } | |
ea4e040a | 6194 | |
a1e785e0 MY |
6195 | int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, |
6196 | u16 len) | |
de6eae1f YR |
6197 | { |
6198 | struct bnx2x *bp; | |
6199 | u32 spirom_ver = 0; | |
fcf5b650 | 6200 | int status = 0; |
de6eae1f | 6201 | u8 *ver_p = version; |
a22f0788 | 6202 | u16 remain_len = len; |
de6eae1f YR |
6203 | if (version == NULL || params == NULL) |
6204 | return -EINVAL; | |
6205 | bp = params->bp; | |
ea4e040a | 6206 | |
de6eae1f YR |
6207 | /* Extract first external phy*/ |
6208 | version[0] = '\0'; | |
6209 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); | |
ea4e040a | 6210 | |
a22f0788 | 6211 | if (params->phy[EXT_PHY1].format_fw_ver) { |
de6eae1f YR |
6212 | status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, |
6213 | ver_p, | |
a22f0788 YR |
6214 | &remain_len); |
6215 | ver_p += (len - remain_len); | |
6216 | } | |
6217 | if ((params->num_phys == MAX_PHYS) && | |
6218 | (params->phy[EXT_PHY2].ver_addr != 0)) { | |
cd88ccee | 6219 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); |
a22f0788 YR |
6220 | if (params->phy[EXT_PHY2].format_fw_ver) { |
6221 | *ver_p = '/'; | |
6222 | ver_p++; | |
6223 | remain_len--; | |
6224 | status |= params->phy[EXT_PHY2].format_fw_ver( | |
6225 | spirom_ver, | |
6226 | ver_p, | |
6227 | &remain_len); | |
6228 | ver_p = version + (len - remain_len); | |
6229 | } | |
6230 | } | |
6231 | *ver_p = '\0'; | |
de6eae1f | 6232 | return status; |
6bbca910 | 6233 | } |
ea4e040a | 6234 | |
de6eae1f YR |
6235 | static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, |
6236 | struct link_params *params) | |
589abe3a | 6237 | { |
de6eae1f | 6238 | u8 port = params->port; |
589abe3a | 6239 | struct bnx2x *bp = params->bp; |
589abe3a | 6240 | |
de6eae1f | 6241 | if (phy->req_line_speed != SPEED_1000) { |
3c9ada22 | 6242 | u32 md_devad = 0; |
589abe3a | 6243 | |
de6eae1f | 6244 | DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); |
589abe3a | 6245 | |
3c9ada22 | 6246 | if (!CHIP_IS_E3(bp)) { |
d231023e | 6247 | /* Change the uni_phy_addr in the nig */ |
3c9ada22 YR |
6248 | md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + |
6249 | port*0x18)); | |
cc1cb004 | 6250 | |
3c9ada22 YR |
6251 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
6252 | 0x5); | |
6253 | } | |
589abe3a | 6254 | |
de6eae1f | 6255 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
6256 | 5, |
6257 | (MDIO_REG_BANK_AER_BLOCK + | |
6258 | (MDIO_AER_BLOCK_AER_REG & 0xf)), | |
6259 | 0x2800); | |
589abe3a | 6260 | |
de6eae1f | 6261 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
6262 | 5, |
6263 | (MDIO_REG_BANK_CL73_IEEEB0 + | |
6264 | (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), | |
6265 | 0x6041); | |
de6eae1f | 6266 | msleep(200); |
d231023e | 6267 | /* Set aer mmd back */ |
ec146a6f | 6268 | bnx2x_set_aer_mmd(params, phy); |
589abe3a | 6269 | |
3c9ada22 | 6270 | if (!CHIP_IS_E3(bp)) { |
d231023e | 6271 | /* And md_devad */ |
3c9ada22 YR |
6272 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
6273 | md_devad); | |
6274 | } | |
de6eae1f YR |
6275 | } else { |
6276 | u16 mii_ctrl; | |
6277 | DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); | |
6278 | bnx2x_cl45_read(bp, phy, 5, | |
6279 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
6280 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
6281 | &mii_ctrl); | |
6282 | bnx2x_cl45_write(bp, phy, 5, | |
6283 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
6284 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
6285 | mii_ctrl | | |
6286 | MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); | |
6287 | } | |
589abe3a EG |
6288 | } |
6289 | ||
fcf5b650 YR |
6290 | int bnx2x_set_led(struct link_params *params, |
6291 | struct link_vars *vars, u8 mode, u32 speed) | |
4d295db0 | 6292 | { |
de6eae1f YR |
6293 | u8 port = params->port; |
6294 | u16 hw_led_mode = params->hw_led_mode; | |
fcf5b650 YR |
6295 | int rc = 0; |
6296 | u8 phy_idx; | |
de6eae1f YR |
6297 | u32 tmp; |
6298 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
589abe3a | 6299 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
6300 | DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); |
6301 | DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", | |
6302 | speed, hw_led_mode); | |
7f02c4ad YR |
6303 | /* In case */ |
6304 | for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { | |
6305 | if (params->phy[phy_idx].set_link_led) { | |
6306 | params->phy[phy_idx].set_link_led( | |
6307 | ¶ms->phy[phy_idx], params, mode); | |
6308 | } | |
6309 | } | |
6310 | ||
de6eae1f | 6311 | switch (mode) { |
7f02c4ad | 6312 | case LED_MODE_FRONT_PANEL_OFF: |
de6eae1f YR |
6313 | case LED_MODE_OFF: |
6314 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); | |
6315 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
cd88ccee | 6316 | SHARED_HW_CFG_LED_MAC1); |
589abe3a | 6317 | |
de6eae1f | 6318 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
001cea77 | 6319 | if (params->phy[EXT_PHY1].type == |
9379c9be YR |
6320 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
6321 | tmp &= ~(EMAC_LED_1000MB_OVERRIDE | | |
6322 | EMAC_LED_100MB_OVERRIDE | | |
6323 | EMAC_LED_10MB_OVERRIDE); | |
6324 | else | |
6325 | tmp |= EMAC_LED_OVERRIDE; | |
6326 | ||
6327 | EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); | |
de6eae1f | 6328 | break; |
589abe3a | 6329 | |
de6eae1f | 6330 | case LED_MODE_OPER: |
8f73f0b9 | 6331 | /* For all other phys, OPER mode is same as ON, so in case |
7f02c4ad | 6332 | * link is down, do nothing |
2cf7acf9 | 6333 | */ |
7f02c4ad YR |
6334 | if (!vars->link_up) |
6335 | break; | |
6336 | case LED_MODE_ON: | |
e4d78f12 YR |
6337 | if (((params->phy[EXT_PHY1].type == |
6338 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || | |
6339 | (params->phy[EXT_PHY1].type == | |
6340 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && | |
1f48353a | 6341 | CHIP_IS_E2(bp) && params->num_phys == 2) { |
8f73f0b9 | 6342 | /* This is a work-around for E2+8727 Configurations */ |
1f48353a YR |
6343 | if (mode == LED_MODE_ON || |
6344 | speed == SPEED_10000){ | |
6345 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); | |
6346 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
6347 | ||
6348 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); | |
6349 | EMAC_WR(bp, EMAC_REG_EMAC_LED, | |
6350 | (tmp | EMAC_LED_OVERRIDE)); | |
8f73f0b9 | 6351 | /* Return here without enabling traffic |
ab505dec | 6352 | * LED blink and setting rate in ON mode. |
793bd450 YR |
6353 | * In oper mode, enabling LED blink |
6354 | * and setting rate is needed. | |
6355 | */ | |
6356 | if (mode == LED_MODE_ON) | |
6357 | return rc; | |
1f48353a | 6358 | } |
793bd450 | 6359 | } else if (SINGLE_MEDIA_DIRECT(params)) { |
8f73f0b9 | 6360 | /* This is a work-around for HW issue found when link |
2cf7acf9 YR |
6361 | * is up in CL73 |
6362 | */ | |
ab505dec YR |
6363 | if ((!CHIP_IS_E3(bp)) || |
6364 | (CHIP_IS_E3(bp) && | |
6365 | mode == LED_MODE_ON)) | |
6366 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
6367 | ||
793bd450 YR |
6368 | if (CHIP_IS_E1x(bp) || |
6369 | CHIP_IS_E2(bp) || | |
6370 | (mode == LED_MODE_ON)) | |
6371 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); | |
6372 | else | |
6373 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
6374 | hw_led_mode); | |
001cea77 YR |
6375 | } else if ((params->phy[EXT_PHY1].type == |
6376 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && | |
9379c9be | 6377 | (mode == LED_MODE_ON)) { |
001cea77 YR |
6378 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); |
6379 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); | |
9379c9be YR |
6380 | EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | |
6381 | EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); | |
6382 | /* Break here; otherwise, it'll disable the | |
6383 | * intended override. | |
6384 | */ | |
6385 | break; | |
7dc950ca YR |
6386 | } else { |
6387 | u32 nig_led_mode = ((params->hw_led_mode << | |
6388 | SHARED_HW_CFG_LED_MODE_SHIFT) == | |
6389 | SHARED_HW_CFG_LED_EXTPHY2) ? | |
6390 | (SHARED_HW_CFG_LED_PHY1 >> | |
6391 | SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; | |
001cea77 | 6392 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, |
7dc950ca YR |
6393 | nig_led_mode); |
6394 | } | |
589abe3a | 6395 | |
cd88ccee | 6396 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); |
de6eae1f | 6397 | /* Set blinking rate to ~15.9Hz */ |
26ffaf36 YR |
6398 | if (CHIP_IS_E3(bp)) |
6399 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, | |
6400 | LED_BLINK_RATE_VAL_E3); | |
6401 | else | |
6402 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, | |
6403 | LED_BLINK_RATE_VAL_E1X_E2); | |
de6eae1f | 6404 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + |
cd88ccee | 6405 | port*4, 1); |
9379c9be YR |
6406 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
6407 | EMAC_WR(bp, EMAC_REG_EMAC_LED, | |
6408 | (tmp & (~EMAC_LED_OVERRIDE))); | |
589abe3a | 6409 | |
de6eae1f YR |
6410 | if (CHIP_IS_E1(bp) && |
6411 | ((speed == SPEED_2500) || | |
6412 | (speed == SPEED_1000) || | |
6413 | (speed == SPEED_100) || | |
6414 | (speed == SPEED_10))) { | |
8f73f0b9 | 6415 | /* For speeds less than 10G LED scheme is different */ |
de6eae1f | 6416 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 |
cd88ccee | 6417 | + port*4, 1); |
de6eae1f | 6418 | REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + |
cd88ccee | 6419 | port*4, 0); |
de6eae1f | 6420 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + |
cd88ccee | 6421 | port*4, 1); |
de6eae1f YR |
6422 | } |
6423 | break; | |
589abe3a | 6424 | |
de6eae1f YR |
6425 | default: |
6426 | rc = -EINVAL; | |
6427 | DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", | |
6428 | mode); | |
6429 | break; | |
589abe3a | 6430 | } |
de6eae1f | 6431 | return rc; |
589abe3a | 6432 | |
4d295db0 EG |
6433 | } |
6434 | ||
8f73f0b9 | 6435 | /* This function comes to reflect the actual link state read DIRECTLY from the |
a22f0788 YR |
6436 | * HW |
6437 | */ | |
fcf5b650 YR |
6438 | int bnx2x_test_link(struct link_params *params, struct link_vars *vars, |
6439 | u8 is_serdes) | |
4d295db0 EG |
6440 | { |
6441 | struct bnx2x *bp = params->bp; | |
de6eae1f | 6442 | u16 gp_status = 0, phy_index = 0; |
a22f0788 YR |
6443 | u8 ext_phy_link_up = 0, serdes_phy_type; |
6444 | struct link_vars temp_vars; | |
3c9ada22 YR |
6445 | struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; |
6446 | ||
6447 | if (CHIP_IS_E3(bp)) { | |
6448 | u16 link_up; | |
6449 | if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] | |
6450 | > SPEED_10000) { | |
6451 | /* Check 20G link */ | |
6452 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6453 | 1, &link_up); | |
6454 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6455 | 1, &link_up); | |
6456 | link_up &= (1<<2); | |
6457 | } else { | |
6458 | /* Check 10G link and below*/ | |
6459 | u8 lane = bnx2x_get_warpcore_lane(int_phy, params); | |
6460 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6461 | MDIO_WC_REG_GP2_STATUS_GP_2_1, | |
6462 | &gp_status); | |
6463 | gp_status = ((gp_status >> 8) & 0xf) | | |
6464 | ((gp_status >> 12) & 0xf); | |
6465 | link_up = gp_status & (1 << lane); | |
6466 | } | |
6467 | if (!link_up) | |
6468 | return -ESRCH; | |
6469 | } else { | |
6470 | CL22_RD_OVER_CL45(bp, int_phy, | |
cd88ccee YR |
6471 | MDIO_REG_BANK_GP_STATUS, |
6472 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
6473 | &gp_status); | |
d231023e | 6474 | /* Link is up only if both local phy and external phy are up */ |
a22f0788 YR |
6475 | if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) |
6476 | return -ESRCH; | |
3c9ada22 YR |
6477 | } |
6478 | /* In XGXS loopback mode, do not check external PHY */ | |
6479 | if (params->loopback_mode == LOOPBACK_XGXS) | |
6480 | return 0; | |
a22f0788 YR |
6481 | |
6482 | switch (params->num_phys) { | |
6483 | case 1: | |
6484 | /* No external PHY */ | |
6485 | return 0; | |
6486 | case 2: | |
6487 | ext_phy_link_up = params->phy[EXT_PHY1].read_status( | |
6488 | ¶ms->phy[EXT_PHY1], | |
6489 | params, &temp_vars); | |
6490 | break; | |
6491 | case 3: /* Dual Media */ | |
de6eae1f YR |
6492 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6493 | phy_index++) { | |
a22f0788 | 6494 | serdes_phy_type = ((params->phy[phy_index].media_type == |
dbef807e YM |
6495 | ETH_PHY_SFPP_10G_FIBER) || |
6496 | (params->phy[phy_index].media_type == | |
6497 | ETH_PHY_SFP_1G_FIBER) || | |
a22f0788 | 6498 | (params->phy[phy_index].media_type == |
1ac9e428 YR |
6499 | ETH_PHY_XFP_FIBER) || |
6500 | (params->phy[phy_index].media_type == | |
6501 | ETH_PHY_DA_TWINAX)); | |
a22f0788 YR |
6502 | |
6503 | if (is_serdes != serdes_phy_type) | |
6504 | continue; | |
6505 | if (params->phy[phy_index].read_status) { | |
6506 | ext_phy_link_up |= | |
de6eae1f YR |
6507 | params->phy[phy_index].read_status( |
6508 | ¶ms->phy[phy_index], | |
6509 | params, &temp_vars); | |
a22f0788 | 6510 | } |
de6eae1f | 6511 | } |
a22f0788 | 6512 | break; |
4d295db0 | 6513 | } |
a22f0788 YR |
6514 | if (ext_phy_link_up) |
6515 | return 0; | |
de6eae1f YR |
6516 | return -ESRCH; |
6517 | } | |
4d295db0 | 6518 | |
fcf5b650 YR |
6519 | static int bnx2x_link_initialize(struct link_params *params, |
6520 | struct link_vars *vars) | |
de6eae1f | 6521 | { |
fcf5b650 | 6522 | int rc = 0; |
de6eae1f YR |
6523 | u8 phy_index, non_ext_phy; |
6524 | struct bnx2x *bp = params->bp; | |
8f73f0b9 | 6525 | /* In case of external phy existence, the line speed would be the |
2cf7acf9 YR |
6526 | * line speed linked up by the external phy. In case it is direct |
6527 | * only, then the line_speed during initialization will be | |
6528 | * equal to the req_line_speed | |
6529 | */ | |
de6eae1f | 6530 | vars->line_speed = params->phy[INT_PHY].req_line_speed; |
4d295db0 | 6531 | |
8f73f0b9 | 6532 | /* Initialize the internal phy in case this is a direct board |
de6eae1f YR |
6533 | * (no external phys), or this board has external phy which requires |
6534 | * to first. | |
6535 | */ | |
3c9ada22 YR |
6536 | if (!USES_WARPCORE(bp)) |
6537 | bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); | |
de6eae1f YR |
6538 | /* init ext phy and enable link state int */ |
6539 | non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || | |
6540 | (params->loopback_mode == LOOPBACK_XGXS)); | |
4d295db0 | 6541 | |
de6eae1f YR |
6542 | if (non_ext_phy || |
6543 | (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || | |
6544 | (params->loopback_mode == LOOPBACK_EXT_PHY)) { | |
6545 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; | |
3c9ada22 YR |
6546 | if (vars->line_speed == SPEED_AUTO_NEG && |
6547 | (CHIP_IS_E1x(bp) || | |
937e5c3d | 6548 | CHIP_IS_E2(bp))) |
de6eae1f | 6549 | bnx2x_set_parallel_detection(phy, params); |
937e5c3d EG |
6550 | if (params->phy[INT_PHY].config_init) |
6551 | params->phy[INT_PHY].config_init(phy, params, vars); | |
4d295db0 EG |
6552 | } |
6553 | ||
0afbd74a YR |
6554 | /* Re-read this value in case it was changed inside config_init due to |
6555 | * limitations of optic module | |
6556 | */ | |
6557 | vars->line_speed = params->phy[INT_PHY].req_line_speed; | |
6558 | ||
de6eae1f | 6559 | /* Init external phy*/ |
fd36a2e6 YR |
6560 | if (non_ext_phy) { |
6561 | if (params->phy[INT_PHY].supported & | |
6562 | SUPPORTED_FIBRE) | |
6563 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6564 | } else { | |
de6eae1f YR |
6565 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6566 | phy_index++) { | |
8f73f0b9 | 6567 | /* No need to initialize second phy in case of first |
a22f0788 YR |
6568 | * phy only selection. In case of second phy, we do |
6569 | * need to initialize the first phy, since they are | |
6570 | * connected. | |
2cf7acf9 | 6571 | */ |
fd36a2e6 YR |
6572 | if (params->phy[phy_index].supported & |
6573 | SUPPORTED_FIBRE) | |
6574 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6575 | ||
a22f0788 YR |
6576 | if (phy_index == EXT_PHY2 && |
6577 | (bnx2x_phy_selection(params) == | |
6578 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { | |
94f05b0f JP |
6579 | DP(NETIF_MSG_LINK, |
6580 | "Not initializing second phy\n"); | |
a22f0788 YR |
6581 | continue; |
6582 | } | |
de6eae1f YR |
6583 | params->phy[phy_index].config_init( |
6584 | ¶ms->phy[phy_index], | |
6585 | params, vars); | |
6586 | } | |
fd36a2e6 | 6587 | } |
de6eae1f YR |
6588 | /* Reset the interrupt indication after phy was initialized */ |
6589 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + | |
6590 | params->port*4, | |
6591 | (NIG_STATUS_XGXS0_LINK10G | | |
6592 | NIG_STATUS_XGXS0_LINK_STATUS | | |
6593 | NIG_STATUS_SERDES0_LINK_STATUS | | |
6594 | NIG_MASK_MI_INT)); | |
6595 | return rc; | |
6596 | } | |
4d295db0 | 6597 | |
de6eae1f YR |
6598 | static void bnx2x_int_link_reset(struct bnx2x_phy *phy, |
6599 | struct link_params *params) | |
6600 | { | |
d231023e | 6601 | /* Reset the SerDes/XGXS */ |
cd88ccee YR |
6602 | REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, |
6603 | (0x1ff << (params->port*16))); | |
589abe3a EG |
6604 | } |
6605 | ||
de6eae1f YR |
6606 | static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, |
6607 | struct link_params *params) | |
4d295db0 | 6608 | { |
de6eae1f YR |
6609 | struct bnx2x *bp = params->bp; |
6610 | u8 gpio_port; | |
6611 | /* HW reset */ | |
f2e0899f DK |
6612 | if (CHIP_IS_E2(bp)) |
6613 | gpio_port = BP_PATH(bp); | |
6614 | else | |
6615 | gpio_port = params->port; | |
de6eae1f | 6616 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee YR |
6617 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
6618 | gpio_port); | |
de6eae1f | 6619 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee YR |
6620 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
6621 | gpio_port); | |
de6eae1f | 6622 | DP(NETIF_MSG_LINK, "reset external PHY\n"); |
4d295db0 | 6623 | } |
589abe3a | 6624 | |
fcf5b650 YR |
6625 | static int bnx2x_update_link_down(struct link_params *params, |
6626 | struct link_vars *vars) | |
589abe3a EG |
6627 | { |
6628 | struct bnx2x *bp = params->bp; | |
de6eae1f | 6629 | u8 port = params->port; |
589abe3a | 6630 | |
de6eae1f | 6631 | DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); |
7f02c4ad | 6632 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
3deb8167 | 6633 | vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; |
d231023e | 6634 | /* Indicate no mac active */ |
de6eae1f | 6635 | vars->mac_type = MAC_TYPE_NONE; |
ab6ad5a4 | 6636 | |
d231023e | 6637 | /* Update shared memory */ |
4978140c | 6638 | vars->link_status &= ~LINK_UPDATE_MASK; |
de6eae1f YR |
6639 | vars->line_speed = 0; |
6640 | bnx2x_update_mng(params, vars->link_status); | |
589abe3a | 6641 | |
d231023e | 6642 | /* Activate nig drain */ |
de6eae1f | 6643 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); |
4d295db0 | 6644 | |
d231023e | 6645 | /* Disable emac */ |
9380bb9e YR |
6646 | if (!CHIP_IS_E3(bp)) |
6647 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
de6eae1f | 6648 | |
d231023e YM |
6649 | usleep_range(10000, 20000); |
6650 | /* Reset BigMac/Xmac */ | |
9380bb9e | 6651 | if (CHIP_IS_E1x(bp) || |
d3a8f13b YR |
6652 | CHIP_IS_E2(bp)) |
6653 | bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); | |
6654 | ||
ce7c0489 | 6655 | if (CHIP_IS_E3(bp)) { |
d231023e | 6656 | /* Prevent LPI Generation by chip */ |
c8c60d88 YM |
6657 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), |
6658 | 0); | |
c8c60d88 YM |
6659 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), |
6660 | 0); | |
6661 | vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | | |
6662 | SHMEM_EEE_ACTIVE_BIT); | |
6663 | ||
6664 | bnx2x_update_mng_eee(params, vars->eee_status); | |
d3a8f13b YR |
6665 | bnx2x_set_xmac_rxtx(params, 0); |
6666 | bnx2x_set_umac_rxtx(params, 0); | |
ce7c0489 | 6667 | } |
9380bb9e | 6668 | |
589abe3a EG |
6669 | return 0; |
6670 | } | |
de6eae1f | 6671 | |
fcf5b650 YR |
6672 | static int bnx2x_update_link_up(struct link_params *params, |
6673 | struct link_vars *vars, | |
6674 | u8 link_10g) | |
589abe3a EG |
6675 | { |
6676 | struct bnx2x *bp = params->bp; | |
55098c5c | 6677 | u8 phy_idx, port = params->port; |
fcf5b650 | 6678 | int rc = 0; |
4d295db0 | 6679 | |
de6f3377 YR |
6680 | vars->link_status |= (LINK_STATUS_LINK_UP | |
6681 | LINK_STATUS_PHYSICAL_LINK_FLAG); | |
3deb8167 | 6682 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; |
7f02c4ad | 6683 | |
de6eae1f YR |
6684 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
6685 | vars->link_status |= | |
6686 | LINK_STATUS_TX_FLOW_CONTROL_ENABLED; | |
589abe3a | 6687 | |
de6eae1f YR |
6688 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
6689 | vars->link_status |= | |
6690 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED; | |
9380bb9e | 6691 | if (USES_WARPCORE(bp)) { |
3deb8167 YR |
6692 | if (link_10g) { |
6693 | if (bnx2x_xmac_enable(params, vars, 0) == | |
6694 | -ESRCH) { | |
6695 | DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); | |
6696 | vars->link_up = 0; | |
6697 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
6698 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
6699 | } | |
6700 | } else | |
9380bb9e | 6701 | bnx2x_umac_enable(params, vars, 0); |
7f02c4ad | 6702 | bnx2x_set_led(params, vars, |
9380bb9e | 6703 | LED_MODE_OPER, vars->line_speed); |
c8c60d88 YM |
6704 | |
6705 | if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && | |
6706 | (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { | |
6707 | DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); | |
6708 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + | |
6709 | (params->port << 2), 1); | |
6710 | REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); | |
6711 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + | |
6712 | (params->port << 2), 0xfc20); | |
6713 | } | |
9380bb9e YR |
6714 | } |
6715 | if ((CHIP_IS_E1x(bp) || | |
6716 | CHIP_IS_E2(bp))) { | |
6717 | if (link_10g) { | |
d3a8f13b | 6718 | if (bnx2x_bmac_enable(params, vars, 0, 1) == |
3deb8167 YR |
6719 | -ESRCH) { |
6720 | DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); | |
6721 | vars->link_up = 0; | |
6722 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
6723 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
6724 | } | |
cc1cb004 | 6725 | |
9380bb9e YR |
6726 | bnx2x_set_led(params, vars, |
6727 | LED_MODE_OPER, SPEED_10000); | |
6728 | } else { | |
6729 | rc = bnx2x_emac_program(params, vars); | |
6730 | bnx2x_emac_enable(params, vars, 0); | |
6731 | ||
6732 | /* AN complete? */ | |
6733 | if ((vars->link_status & | |
6734 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) | |
6735 | && (!(vars->phy_flags & PHY_SGMII_FLAG)) && | |
6736 | SINGLE_MEDIA_DIRECT(params)) | |
6737 | bnx2x_set_gmii_tx_driver(params); | |
6738 | } | |
de6eae1f | 6739 | } |
cc1cb004 | 6740 | |
de6eae1f | 6741 | /* PBF - link up */ |
9380bb9e | 6742 | if (CHIP_IS_E1x(bp)) |
f2e0899f DK |
6743 | rc |= bnx2x_pbf_update(params, vars->flow_ctrl, |
6744 | vars->line_speed); | |
589abe3a | 6745 | |
d231023e | 6746 | /* Disable drain */ |
de6eae1f | 6747 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); |
589abe3a | 6748 | |
d231023e | 6749 | /* Update shared memory */ |
de6eae1f | 6750 | bnx2x_update_mng(params, vars->link_status); |
c8c60d88 | 6751 | bnx2x_update_mng_eee(params, vars->eee_status); |
55098c5c YR |
6752 | /* Check remote fault */ |
6753 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { | |
6754 | if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { | |
6755 | bnx2x_check_half_open_conn(params, vars, 0); | |
6756 | break; | |
6757 | } | |
6758 | } | |
de6eae1f YR |
6759 | msleep(20); |
6760 | return rc; | |
589abe3a | 6761 | } |
8f73f0b9 | 6762 | /* The bnx2x_link_update function should be called upon link |
de6eae1f YR |
6763 | * interrupt. |
6764 | * Link is considered up as follows: | |
6765 | * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs | |
6766 | * to be up | |
6767 | * - SINGLE_MEDIA - The link between the 577xx and the external | |
6768 | * phy (XGXS) need to up as well as the external link of the | |
6769 | * phy (PHY_EXT1) | |
6770 | * - DUAL_MEDIA - The link between the 577xx and the first | |
6771 | * external phy needs to be up, and at least one of the 2 | |
6772 | * external phy link must be up. | |
6773 | */ | |
fcf5b650 | 6774 | int bnx2x_link_update(struct link_params *params, struct link_vars *vars) |
4d295db0 | 6775 | { |
de6eae1f YR |
6776 | struct bnx2x *bp = params->bp; |
6777 | struct link_vars phy_vars[MAX_PHYS]; | |
6778 | u8 port = params->port; | |
3c9ada22 | 6779 | u8 link_10g_plus, phy_index; |
fcf5b650 YR |
6780 | u8 ext_phy_link_up = 0, cur_link_up; |
6781 | int rc = 0; | |
de6eae1f YR |
6782 | u8 is_mi_int = 0; |
6783 | u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; | |
6784 | u8 active_external_phy = INT_PHY; | |
3deb8167 | 6785 | vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; |
4978140c | 6786 | vars->link_status &= ~LINK_UPDATE_MASK; |
de6eae1f YR |
6787 | for (phy_index = INT_PHY; phy_index < params->num_phys; |
6788 | phy_index++) { | |
6789 | phy_vars[phy_index].flow_ctrl = 0; | |
6790 | phy_vars[phy_index].link_status = 0; | |
6791 | phy_vars[phy_index].line_speed = 0; | |
6792 | phy_vars[phy_index].duplex = DUPLEX_FULL; | |
6793 | phy_vars[phy_index].phy_link_up = 0; | |
6794 | phy_vars[phy_index].link_up = 0; | |
c688fe2f | 6795 | phy_vars[phy_index].fault_detected = 0; |
c8c60d88 YM |
6796 | /* different consideration, since vars holds inner state */ |
6797 | phy_vars[phy_index].eee_status = vars->eee_status; | |
de6eae1f | 6798 | } |
4d295db0 | 6799 | |
3c9ada22 YR |
6800 | if (USES_WARPCORE(bp)) |
6801 | bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); | |
6802 | ||
de6eae1f YR |
6803 | DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", |
6804 | port, (vars->phy_flags & PHY_XGXS_FLAG), | |
6805 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
4d295db0 | 6806 | |
de6eae1f | 6807 | is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + |
cd88ccee | 6808 | port*0x18) > 0); |
de6eae1f YR |
6809 | DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", |
6810 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
6811 | is_mi_int, | |
cd88ccee | 6812 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); |
4d295db0 | 6813 | |
de6eae1f YR |
6814 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", |
6815 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
6816 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
4d295db0 | 6817 | |
d231023e | 6818 | /* Disable emac */ |
9380bb9e YR |
6819 | if (!CHIP_IS_E3(bp)) |
6820 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
4d295db0 | 6821 | |
8f73f0b9 | 6822 | /* Step 1: |
2cf7acf9 YR |
6823 | * Check external link change only for external phys, and apply |
6824 | * priority selection between them in case the link on both phys | |
9045f6b4 | 6825 | * is up. Note that instead of the common vars, a temporary |
2cf7acf9 YR |
6826 | * vars argument is used since each phy may have different link/ |
6827 | * speed/duplex result | |
6828 | */ | |
de6eae1f YR |
6829 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6830 | phy_index++) { | |
6831 | struct bnx2x_phy *phy = ¶ms->phy[phy_index]; | |
6832 | if (!phy->read_status) | |
6833 | continue; | |
6834 | /* Read link status and params of this ext phy */ | |
6835 | cur_link_up = phy->read_status(phy, params, | |
6836 | &phy_vars[phy_index]); | |
6837 | if (cur_link_up) { | |
6838 | DP(NETIF_MSG_LINK, "phy in index %d link is up\n", | |
6839 | phy_index); | |
6840 | } else { | |
6841 | DP(NETIF_MSG_LINK, "phy in index %d link is down\n", | |
6842 | phy_index); | |
6843 | continue; | |
6844 | } | |
e10bc84d | 6845 | |
de6eae1f YR |
6846 | if (!ext_phy_link_up) { |
6847 | ext_phy_link_up = 1; | |
6848 | active_external_phy = phy_index; | |
a22f0788 YR |
6849 | } else { |
6850 | switch (bnx2x_phy_selection(params)) { | |
6851 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
6852 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
8f73f0b9 | 6853 | /* In this option, the first PHY makes sure to pass the |
a22f0788 YR |
6854 | * traffic through itself only. |
6855 | * Its not clear how to reset the link on the second phy | |
2cf7acf9 | 6856 | */ |
a22f0788 YR |
6857 | active_external_phy = EXT_PHY1; |
6858 | break; | |
6859 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
8f73f0b9 | 6860 | /* In this option, the first PHY makes sure to pass the |
a22f0788 | 6861 | * traffic through the second PHY. |
2cf7acf9 | 6862 | */ |
a22f0788 YR |
6863 | active_external_phy = EXT_PHY2; |
6864 | break; | |
6865 | default: | |
8f73f0b9 | 6866 | /* Link indication on both PHYs with the following cases |
a22f0788 YR |
6867 | * is invalid: |
6868 | * - FIRST_PHY means that second phy wasn't initialized, | |
6869 | * hence its link is expected to be down | |
6870 | * - SECOND_PHY means that first phy should not be able | |
6871 | * to link up by itself (using configuration) | |
6872 | * - DEFAULT should be overriden during initialiazation | |
2cf7acf9 | 6873 | */ |
a22f0788 YR |
6874 | DP(NETIF_MSG_LINK, "Invalid link indication" |
6875 | "mpc=0x%x. DISABLING LINK !!!\n", | |
6876 | params->multi_phy_config); | |
6877 | ext_phy_link_up = 0; | |
6878 | break; | |
6879 | } | |
589abe3a | 6880 | } |
589abe3a | 6881 | } |
de6eae1f | 6882 | prev_line_speed = vars->line_speed; |
8f73f0b9 | 6883 | /* Step 2: |
2cf7acf9 YR |
6884 | * Read the status of the internal phy. In case of |
6885 | * DIRECT_SINGLE_MEDIA board, this link is the external link, | |
6886 | * otherwise this is the link between the 577xx and the first | |
6887 | * external phy | |
6888 | */ | |
de6eae1f YR |
6889 | if (params->phy[INT_PHY].read_status) |
6890 | params->phy[INT_PHY].read_status( | |
6891 | ¶ms->phy[INT_PHY], | |
6892 | params, vars); | |
8f73f0b9 | 6893 | /* The INT_PHY flow control reside in the vars. This include the |
de6eae1f YR |
6894 | * case where the speed or flow control are not set to AUTO. |
6895 | * Otherwise, the active external phy flow control result is set | |
6896 | * to the vars. The ext_phy_line_speed is needed to check if the | |
6897 | * speed is different between the internal phy and external phy. | |
6898 | * This case may be result of intermediate link speed change. | |
4d295db0 | 6899 | */ |
de6eae1f YR |
6900 | if (active_external_phy > INT_PHY) { |
6901 | vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; | |
8f73f0b9 | 6902 | /* Link speed is taken from the XGXS. AN and FC result from |
de6eae1f | 6903 | * the external phy. |
4d295db0 | 6904 | */ |
de6eae1f | 6905 | vars->link_status |= phy_vars[active_external_phy].link_status; |
a22f0788 | 6906 | |
8f73f0b9 | 6907 | /* if active_external_phy is first PHY and link is up - disable |
a22f0788 YR |
6908 | * disable TX on second external PHY |
6909 | */ | |
6910 | if (active_external_phy == EXT_PHY1) { | |
6911 | if (params->phy[EXT_PHY2].phy_specific_func) { | |
94f05b0f JP |
6912 | DP(NETIF_MSG_LINK, |
6913 | "Disabling TX on EXT_PHY2\n"); | |
a22f0788 YR |
6914 | params->phy[EXT_PHY2].phy_specific_func( |
6915 | ¶ms->phy[EXT_PHY2], | |
6916 | params, DISABLE_TX); | |
6917 | } | |
6918 | } | |
6919 | ||
de6eae1f YR |
6920 | ext_phy_line_speed = phy_vars[active_external_phy].line_speed; |
6921 | vars->duplex = phy_vars[active_external_phy].duplex; | |
6922 | if (params->phy[active_external_phy].supported & | |
6923 | SUPPORTED_FIBRE) | |
6924 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
fd36a2e6 YR |
6925 | else |
6926 | vars->link_status &= ~LINK_STATUS_SERDES_LINK; | |
c8c60d88 YM |
6927 | |
6928 | vars->eee_status = phy_vars[active_external_phy].eee_status; | |
6929 | ||
de6eae1f YR |
6930 | DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", |
6931 | active_external_phy); | |
6932 | } | |
a22f0788 YR |
6933 | |
6934 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
6935 | phy_index++) { | |
6936 | if (params->phy[phy_index].flags & | |
6937 | FLAGS_REARM_LATCH_SIGNAL) { | |
6938 | bnx2x_rearm_latch_signal(bp, port, | |
6939 | phy_index == | |
6940 | active_external_phy); | |
6941 | break; | |
6942 | } | |
6943 | } | |
de6eae1f YR |
6944 | DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," |
6945 | " ext_phy_line_speed = %d\n", vars->flow_ctrl, | |
6946 | vars->link_status, ext_phy_line_speed); | |
8f73f0b9 | 6947 | /* Upon link speed change set the NIG into drain mode. Comes to |
de6eae1f YR |
6948 | * deals with possible FIFO glitch due to clk change when speed |
6949 | * is decreased without link down indicator | |
6950 | */ | |
4d295db0 | 6951 | |
de6eae1f YR |
6952 | if (vars->phy_link_up) { |
6953 | if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && | |
6954 | (ext_phy_line_speed != vars->line_speed)) { | |
6955 | DP(NETIF_MSG_LINK, "Internal link speed %d is" | |
6956 | " different than the external" | |
6957 | " link speed %d\n", vars->line_speed, | |
6958 | ext_phy_line_speed); | |
6959 | vars->phy_link_up = 0; | |
6960 | } else if (prev_line_speed != vars->line_speed) { | |
cd88ccee YR |
6961 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, |
6962 | 0); | |
503976e9 | 6963 | usleep_range(1000, 2000); |
de6eae1f YR |
6964 | } |
6965 | } | |
e10bc84d | 6966 | |
d231023e | 6967 | /* Anything 10 and over uses the bmac */ |
3c9ada22 | 6968 | link_10g_plus = (vars->line_speed >= SPEED_10000); |
589abe3a | 6969 | |
3c9ada22 | 6970 | bnx2x_link_int_ack(params, vars, link_10g_plus); |
589abe3a | 6971 | |
8f73f0b9 | 6972 | /* In case external phy link is up, and internal link is down |
2cf7acf9 YR |
6973 | * (not initialized yet probably after link initialization, it |
6974 | * needs to be initialized. | |
6975 | * Note that after link down-up as result of cable plug, the xgxs | |
6976 | * link would probably become up again without the need | |
6977 | * initialize it | |
6978 | */ | |
de6eae1f YR |
6979 | if (!(SINGLE_MEDIA_DIRECT(params))) { |
6980 | DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," | |
6981 | " init_preceding = %d\n", ext_phy_link_up, | |
6982 | vars->phy_link_up, | |
6983 | params->phy[EXT_PHY1].flags & | |
6984 | FLAGS_INIT_XGXS_FIRST); | |
6985 | if (!(params->phy[EXT_PHY1].flags & | |
6986 | FLAGS_INIT_XGXS_FIRST) | |
6987 | && ext_phy_link_up && !vars->phy_link_up) { | |
6988 | vars->line_speed = ext_phy_line_speed; | |
6989 | if (vars->line_speed < SPEED_1000) | |
6990 | vars->phy_flags |= PHY_SGMII_FLAG; | |
6991 | else | |
6992 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
ec146a6f YR |
6993 | |
6994 | if (params->phy[INT_PHY].config_init) | |
6995 | params->phy[INT_PHY].config_init( | |
6996 | ¶ms->phy[INT_PHY], params, | |
de6eae1f | 6997 | vars); |
4d295db0 | 6998 | } |
589abe3a | 6999 | } |
8f73f0b9 | 7000 | /* Link is up only if both local phy and external phy (in case of |
9045f6b4 | 7001 | * non-direct board) are up and no fault detected on active PHY. |
4d295db0 | 7002 | */ |
de6eae1f YR |
7003 | vars->link_up = (vars->phy_link_up && |
7004 | (ext_phy_link_up || | |
c688fe2f YR |
7005 | SINGLE_MEDIA_DIRECT(params)) && |
7006 | (phy_vars[active_external_phy].fault_detected == 0)); | |
de6eae1f | 7007 | |
27d9129f YR |
7008 | /* Update the PFC configuration in case it was changed */ |
7009 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
7010 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
7011 | else | |
7012 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; | |
7013 | ||
de6eae1f | 7014 | if (vars->link_up) |
3c9ada22 | 7015 | rc = bnx2x_update_link_up(params, vars, link_10g_plus); |
4d295db0 | 7016 | else |
de6eae1f | 7017 | rc = bnx2x_update_link_down(params, vars); |
589abe3a | 7018 | |
a3348722 BW |
7019 | /* Update MCP link status was changed */ |
7020 | if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) | |
7021 | bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); | |
7022 | ||
4d295db0 | 7023 | return rc; |
589abe3a EG |
7024 | } |
7025 | ||
de6eae1f YR |
7026 | /*****************************************************************************/ |
7027 | /* External Phy section */ | |
7028 | /*****************************************************************************/ | |
7029 | void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) | |
7030 | { | |
7031 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 7032 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
503976e9 | 7033 | usleep_range(1000, 2000); |
de6eae1f | 7034 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 7035 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); |
de6eae1f | 7036 | } |
589abe3a | 7037 | |
de6eae1f YR |
7038 | static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, |
7039 | u32 spirom_ver, u32 ver_addr) | |
7040 | { | |
7041 | DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", | |
7042 | (u16)(spirom_ver>>16), (u16)spirom_ver, port); | |
4d295db0 | 7043 | |
de6eae1f YR |
7044 | if (ver_addr) |
7045 | REG_WR(bp, ver_addr, spirom_ver); | |
589abe3a EG |
7046 | } |
7047 | ||
de6eae1f YR |
7048 | static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, |
7049 | struct bnx2x_phy *phy, | |
7050 | u8 port) | |
6bbca910 | 7051 | { |
de6eae1f YR |
7052 | u16 fw_ver1, fw_ver2; |
7053 | ||
7054 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
cd88ccee | 7055 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); |
de6eae1f | 7056 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
cd88ccee | 7057 | MDIO_PMA_REG_ROM_VER2, &fw_ver2); |
de6eae1f YR |
7058 | bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), |
7059 | phy->ver_addr); | |
ea4e040a | 7060 | } |
ab6ad5a4 | 7061 | |
de6eae1f YR |
7062 | static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, |
7063 | struct bnx2x_phy *phy, | |
7064 | struct link_vars *vars) | |
7065 | { | |
7066 | u16 val; | |
7067 | bnx2x_cl45_read(bp, phy, | |
7068 | MDIO_AN_DEVAD, | |
7069 | MDIO_AN_REG_STATUS, &val); | |
7070 | bnx2x_cl45_read(bp, phy, | |
7071 | MDIO_AN_DEVAD, | |
7072 | MDIO_AN_REG_STATUS, &val); | |
7073 | if (val & (1<<5)) | |
7074 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
7075 | if ((val & (1<<0)) == 0) | |
7076 | vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; | |
7077 | } | |
7078 | ||
7079 | /******************************************************************/ | |
7080 | /* common BCM8073/BCM8727 PHY SECTION */ | |
7081 | /******************************************************************/ | |
7082 | static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, | |
7083 | struct link_params *params, | |
7084 | struct link_vars *vars) | |
7085 | { | |
7086 | struct bnx2x *bp = params->bp; | |
7087 | if (phy->req_line_speed == SPEED_10 || | |
7088 | phy->req_line_speed == SPEED_100) { | |
7089 | vars->flow_ctrl = phy->req_flow_ctrl; | |
7090 | return; | |
7091 | } | |
7092 | ||
7093 | if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && | |
7094 | (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { | |
7095 | u16 pause_result; | |
7096 | u16 ld_pause; /* local */ | |
7097 | u16 lp_pause; /* link partner */ | |
7098 | bnx2x_cl45_read(bp, phy, | |
7099 | MDIO_AN_DEVAD, | |
7100 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
7101 | ||
7102 | bnx2x_cl45_read(bp, phy, | |
7103 | MDIO_AN_DEVAD, | |
7104 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
7105 | pause_result = (ld_pause & | |
7106 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; | |
7107 | pause_result |= (lp_pause & | |
7108 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; | |
7109 | ||
7110 | bnx2x_pause_resolve(vars, pause_result); | |
7111 | DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", | |
7112 | pause_result); | |
7113 | } | |
7114 | } | |
fcf5b650 YR |
7115 | static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, |
7116 | struct bnx2x_phy *phy, | |
7117 | u8 port) | |
de6eae1f | 7118 | { |
5c99274b YR |
7119 | u32 count = 0; |
7120 | u16 fw_ver1, fw_msgout; | |
fcf5b650 | 7121 | int rc = 0; |
5c99274b | 7122 | |
de6eae1f YR |
7123 | /* Boot port from external ROM */ |
7124 | /* EDC grst */ | |
7125 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7126 | MDIO_PMA_DEVAD, |
7127 | MDIO_PMA_REG_GEN_CTRL, | |
7128 | 0x0001); | |
de6eae1f | 7129 | |
d231023e | 7130 | /* Ucode reboot and rst */ |
de6eae1f | 7131 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7132 | MDIO_PMA_DEVAD, |
7133 | MDIO_PMA_REG_GEN_CTRL, | |
7134 | 0x008c); | |
de6eae1f YR |
7135 | |
7136 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7137 | MDIO_PMA_DEVAD, |
7138 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
de6eae1f YR |
7139 | |
7140 | /* Reset internal microprocessor */ | |
7141 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7142 | MDIO_PMA_DEVAD, |
7143 | MDIO_PMA_REG_GEN_CTRL, | |
7144 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
de6eae1f YR |
7145 | |
7146 | /* Release srst bit */ | |
7147 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7148 | MDIO_PMA_DEVAD, |
7149 | MDIO_PMA_REG_GEN_CTRL, | |
7150 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
de6eae1f | 7151 | |
5c99274b YR |
7152 | /* Delay 100ms per the PHY specifications */ |
7153 | msleep(100); | |
7154 | ||
7155 | /* 8073 sometimes taking longer to download */ | |
7156 | do { | |
7157 | count++; | |
7158 | if (count > 300) { | |
7159 | DP(NETIF_MSG_LINK, | |
7160 | "bnx2x_8073_8727_external_rom_boot port %x:" | |
7161 | "Download failed. fw version = 0x%x\n", | |
7162 | port, fw_ver1); | |
7163 | rc = -EINVAL; | |
7164 | break; | |
7165 | } | |
7166 | ||
7167 | bnx2x_cl45_read(bp, phy, | |
7168 | MDIO_PMA_DEVAD, | |
7169 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); | |
7170 | bnx2x_cl45_read(bp, phy, | |
7171 | MDIO_PMA_DEVAD, | |
7172 | MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); | |
7173 | ||
503976e9 | 7174 | usleep_range(1000, 2000); |
5c99274b YR |
7175 | } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || |
7176 | ((fw_msgout & 0xff) != 0x03 && (phy->type == | |
7177 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); | |
de6eae1f YR |
7178 | |
7179 | /* Clear ser_boot_ctl bit */ | |
7180 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7181 | MDIO_PMA_DEVAD, |
7182 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
de6eae1f | 7183 | bnx2x_save_bcm_spirom_ver(bp, phy, port); |
5c99274b YR |
7184 | |
7185 | DP(NETIF_MSG_LINK, | |
7186 | "bnx2x_8073_8727_external_rom_boot port %x:" | |
7187 | "Download complete. fw version = 0x%x\n", | |
7188 | port, fw_ver1); | |
7189 | ||
7190 | return rc; | |
de6eae1f YR |
7191 | } |
7192 | ||
de6eae1f YR |
7193 | /******************************************************************/ |
7194 | /* BCM8073 PHY SECTION */ | |
7195 | /******************************************************************/ | |
fcf5b650 | 7196 | static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) |
de6eae1f YR |
7197 | { |
7198 | /* This is only required for 8073A1, version 102 only */ | |
7199 | u16 val; | |
7200 | ||
7201 | /* Read 8073 HW revision*/ | |
7202 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7203 | MDIO_PMA_DEVAD, |
7204 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
de6eae1f YR |
7205 | |
7206 | if (val != 1) { | |
7207 | /* No need to workaround in 8073 A1 */ | |
7208 | return 0; | |
7209 | } | |
7210 | ||
7211 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7212 | MDIO_PMA_DEVAD, |
7213 | MDIO_PMA_REG_ROM_VER2, &val); | |
de6eae1f YR |
7214 | |
7215 | /* SNR should be applied only for version 0x102 */ | |
7216 | if (val != 0x102) | |
7217 | return 0; | |
7218 | ||
7219 | return 1; | |
7220 | } | |
7221 | ||
fcf5b650 | 7222 | static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) |
de6eae1f YR |
7223 | { |
7224 | u16 val, cnt, cnt1 ; | |
7225 | ||
7226 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7227 | MDIO_PMA_DEVAD, |
7228 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
de6eae1f YR |
7229 | |
7230 | if (val > 0) { | |
7231 | /* No need to workaround in 8073 A1 */ | |
7232 | return 0; | |
7233 | } | |
7234 | /* XAUI workaround in 8073 A0: */ | |
7235 | ||
8f73f0b9 | 7236 | /* After loading the boot ROM and restarting Autoneg, poll |
2cf7acf9 YR |
7237 | * Dev1, Reg $C820: |
7238 | */ | |
de6eae1f YR |
7239 | |
7240 | for (cnt = 0; cnt < 1000; cnt++) { | |
7241 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7242 | MDIO_PMA_DEVAD, |
7243 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
7244 | &val); | |
8f73f0b9 | 7245 | /* If bit [14] = 0 or bit [13] = 0, continue on with |
2cf7acf9 YR |
7246 | * system initialization (XAUI work-around not required, as |
7247 | * these bits indicate 2.5G or 1G link up). | |
7248 | */ | |
de6eae1f YR |
7249 | if (!(val & (1<<14)) || !(val & (1<<13))) { |
7250 | DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); | |
7251 | return 0; | |
7252 | } else if (!(val & (1<<15))) { | |
2cf7acf9 | 7253 | DP(NETIF_MSG_LINK, "bit 15 went off\n"); |
8f73f0b9 | 7254 | /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's |
2cf7acf9 YR |
7255 | * MSB (bit15) goes to 1 (indicating that the XAUI |
7256 | * workaround has completed), then continue on with | |
7257 | * system initialization. | |
7258 | */ | |
de6eae1f YR |
7259 | for (cnt1 = 0; cnt1 < 1000; cnt1++) { |
7260 | bnx2x_cl45_read(bp, phy, | |
7261 | MDIO_PMA_DEVAD, | |
7262 | MDIO_PMA_REG_8073_XAUI_WA, &val); | |
7263 | if (val & (1<<15)) { | |
7264 | DP(NETIF_MSG_LINK, | |
7265 | "XAUI workaround has completed\n"); | |
7266 | return 0; | |
7267 | } | |
d231023e | 7268 | usleep_range(3000, 6000); |
de6eae1f YR |
7269 | } |
7270 | break; | |
7271 | } | |
d231023e | 7272 | usleep_range(3000, 6000); |
de6eae1f YR |
7273 | } |
7274 | DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); | |
7275 | return -EINVAL; | |
7276 | } | |
7277 | ||
7278 | static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) | |
7279 | { | |
7280 | /* Force KR or KX */ | |
7281 | bnx2x_cl45_write(bp, phy, | |
7282 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
7283 | bnx2x_cl45_write(bp, phy, | |
7284 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); | |
7285 | bnx2x_cl45_write(bp, phy, | |
7286 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); | |
7287 | bnx2x_cl45_write(bp, phy, | |
7288 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
7289 | } | |
7290 | ||
6bbca910 | 7291 | static void bnx2x_8073_set_pause_cl37(struct link_params *params, |
e10bc84d YR |
7292 | struct bnx2x_phy *phy, |
7293 | struct link_vars *vars) | |
ea4e040a | 7294 | { |
6bbca910 | 7295 | u16 cl37_val; |
e10bc84d YR |
7296 | struct bnx2x *bp = params->bp; |
7297 | bnx2x_cl45_read(bp, phy, | |
62b29a5d | 7298 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); |
6bbca910 YR |
7299 | |
7300 | cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
7301 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
e10bc84d | 7302 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
6bbca910 YR |
7303 | if ((vars->ieee_fc & |
7304 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == | |
7305 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { | |
7306 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; | |
7307 | } | |
7308 | if ((vars->ieee_fc & | |
7309 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
7310 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
7311 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
7312 | } | |
7313 | if ((vars->ieee_fc & | |
7314 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
7315 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
7316 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
7317 | } | |
7318 | DP(NETIF_MSG_LINK, | |
7319 | "Ext phy AN advertize cl37 0x%x\n", cl37_val); | |
7320 | ||
e10bc84d | 7321 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 7322 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); |
6bbca910 | 7323 | msleep(500); |
ea4e040a YR |
7324 | } |
7325 | ||
5c107fda YR |
7326 | static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, |
7327 | struct link_params *params, | |
7328 | u32 action) | |
7329 | { | |
7330 | struct bnx2x *bp = params->bp; | |
7331 | switch (action) { | |
7332 | case PHY_INIT: | |
7333 | /* Enable LASI */ | |
7334 | bnx2x_cl45_write(bp, phy, | |
7335 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); | |
7336 | bnx2x_cl45_write(bp, phy, | |
7337 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); | |
7338 | break; | |
7339 | } | |
7340 | } | |
7341 | ||
fcf5b650 YR |
7342 | static int bnx2x_8073_config_init(struct bnx2x_phy *phy, |
7343 | struct link_params *params, | |
7344 | struct link_vars *vars) | |
ea4e040a | 7345 | { |
e10bc84d | 7346 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
7347 | u16 val = 0, tmp1; |
7348 | u8 gpio_port; | |
7349 | DP(NETIF_MSG_LINK, "Init 8073\n"); | |
e10bc84d | 7350 | |
f2e0899f DK |
7351 | if (CHIP_IS_E2(bp)) |
7352 | gpio_port = BP_PATH(bp); | |
7353 | else | |
7354 | gpio_port = params->port; | |
de6eae1f YR |
7355 | /* Restore normal power mode*/ |
7356 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 7357 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
e10bc84d | 7358 | |
de6eae1f | 7359 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 7360 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
ea4e040a | 7361 | |
5c107fda | 7362 | bnx2x_8073_specific_func(phy, params, PHY_INIT); |
de6eae1f | 7363 | bnx2x_8073_set_pause_cl37(params, phy, vars); |
57963ed9 | 7364 | |
e10bc84d | 7365 | bnx2x_cl45_read(bp, phy, |
de6eae1f | 7366 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); |
2f904460 | 7367 | |
de6eae1f | 7368 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 7369 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); |
2f904460 | 7370 | |
de6eae1f | 7371 | DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); |
a1e4be39 | 7372 | |
74d7a119 YR |
7373 | /* Swap polarity if required - Must be done only in non-1G mode */ |
7374 | if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
7375 | /* Configure the 8073 to swap _P and _N of the KR lines */ | |
7376 | DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); | |
7377 | /* 10G Rx/Tx and 1G Tx signal polarity swap */ | |
7378 | bnx2x_cl45_read(bp, phy, | |
7379 | MDIO_PMA_DEVAD, | |
7380 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); | |
7381 | bnx2x_cl45_write(bp, phy, | |
7382 | MDIO_PMA_DEVAD, | |
7383 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, | |
7384 | (val | (3<<9))); | |
7385 | } | |
7386 | ||
7387 | ||
de6eae1f | 7388 | /* Enable CL37 BAM */ |
121839be YR |
7389 | if (REG_RD(bp, params->shmem_base + |
7390 | offsetof(struct shmem_region, dev_info. | |
7391 | port_hw_config[params->port].default_cfg)) & | |
7392 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
57963ed9 | 7393 | |
121839be YR |
7394 | bnx2x_cl45_read(bp, phy, |
7395 | MDIO_AN_DEVAD, | |
7396 | MDIO_AN_REG_8073_BAM, &val); | |
7397 | bnx2x_cl45_write(bp, phy, | |
7398 | MDIO_AN_DEVAD, | |
7399 | MDIO_AN_REG_8073_BAM, val | 1); | |
7400 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); | |
7401 | } | |
de6eae1f YR |
7402 | if (params->loopback_mode == LOOPBACK_EXT) { |
7403 | bnx2x_807x_force_10G(bp, phy); | |
7404 | DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); | |
7405 | return 0; | |
7406 | } else { | |
7407 | bnx2x_cl45_write(bp, phy, | |
7408 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); | |
7409 | } | |
7410 | if (phy->req_line_speed != SPEED_AUTO_NEG) { | |
7411 | if (phy->req_line_speed == SPEED_10000) { | |
7412 | val = (1<<7); | |
7413 | } else if (phy->req_line_speed == SPEED_2500) { | |
7414 | val = (1<<5); | |
8f73f0b9 | 7415 | /* Note that 2.5G works only when used with 1G |
25985edc | 7416 | * advertisement |
2cf7acf9 | 7417 | */ |
de6eae1f YR |
7418 | } else |
7419 | val = (1<<5); | |
7420 | } else { | |
7421 | val = 0; | |
7422 | if (phy->speed_cap_mask & | |
7423 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
7424 | val |= (1<<7); | |
57963ed9 | 7425 | |
25985edc | 7426 | /* Note that 2.5G works only when used with 1G advertisement */ |
de6eae1f YR |
7427 | if (phy->speed_cap_mask & |
7428 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | | |
7429 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) | |
7430 | val |= (1<<5); | |
7431 | DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); | |
7432 | } | |
57963ed9 | 7433 | |
de6eae1f YR |
7434 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); |
7435 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); | |
57963ed9 | 7436 | |
de6eae1f YR |
7437 | if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && |
7438 | (phy->req_line_speed == SPEED_AUTO_NEG)) || | |
7439 | (phy->req_line_speed == SPEED_2500)) { | |
7440 | u16 phy_ver; | |
7441 | /* Allow 2.5G for A1 and above */ | |
7442 | bnx2x_cl45_read(bp, phy, | |
7443 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, | |
7444 | &phy_ver); | |
7445 | DP(NETIF_MSG_LINK, "Add 2.5G\n"); | |
7446 | if (phy_ver > 0) | |
7447 | tmp1 |= 1; | |
7448 | else | |
7449 | tmp1 &= 0xfffe; | |
7450 | } else { | |
7451 | DP(NETIF_MSG_LINK, "Disable 2.5G\n"); | |
7452 | tmp1 &= 0xfffe; | |
7453 | } | |
57963ed9 | 7454 | |
de6eae1f YR |
7455 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); |
7456 | /* Add support for CL37 (passive mode) II */ | |
57963ed9 | 7457 | |
de6eae1f YR |
7458 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); |
7459 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, | |
7460 | (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? | |
7461 | 0x20 : 0x40))); | |
57963ed9 | 7462 | |
de6eae1f YR |
7463 | /* Add support for CL37 (passive mode) III */ |
7464 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
57963ed9 | 7465 | |
8f73f0b9 | 7466 | /* The SNR will improve about 2db by changing BW and FEE main |
2cf7acf9 YR |
7467 | * tap. Rest commands are executed after link is up |
7468 | * Change FFE main cursor to 5 in EDC register | |
7469 | */ | |
de6eae1f YR |
7470 | if (bnx2x_8073_is_snr_needed(bp, phy)) |
7471 | bnx2x_cl45_write(bp, phy, | |
7472 | MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, | |
7473 | 0xFB0C); | |
57963ed9 | 7474 | |
de6eae1f YR |
7475 | /* Enable FEC (Forware Error Correction) Request in the AN */ |
7476 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); | |
7477 | tmp1 |= (1<<15); | |
7478 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); | |
57963ed9 | 7479 | |
de6eae1f | 7480 | bnx2x_ext_phy_set_pause(params, phy, vars); |
57963ed9 | 7481 | |
de6eae1f YR |
7482 | /* Restart autoneg */ |
7483 | msleep(500); | |
7484 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
7485 | DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", | |
7486 | ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); | |
7487 | return 0; | |
b7737c9b | 7488 | } |
ea4e040a | 7489 | |
de6eae1f | 7490 | static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
7491 | struct link_params *params, |
7492 | struct link_vars *vars) | |
7493 | { | |
7494 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
7495 | u8 link_up = 0; |
7496 | u16 val1, val2; | |
7497 | u16 link_status = 0; | |
7498 | u16 an1000_status = 0; | |
a35da8db | 7499 | |
de6eae1f | 7500 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 7501 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
b7737c9b | 7502 | |
de6eae1f | 7503 | DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); |
ea4e040a | 7504 | |
d231023e | 7505 | /* Clear the interrupt LASI status register */ |
de6eae1f YR |
7506 | bnx2x_cl45_read(bp, phy, |
7507 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
7508 | bnx2x_cl45_read(bp, phy, | |
7509 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); | |
7510 | DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); | |
7511 | /* Clear MSG-OUT */ | |
7512 | bnx2x_cl45_read(bp, phy, | |
7513 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
7514 | ||
7515 | /* Check the LASI */ | |
7516 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 7517 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); |
de6eae1f YR |
7518 | |
7519 | DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); | |
7520 | ||
7521 | /* Check the link status */ | |
7522 | bnx2x_cl45_read(bp, phy, | |
7523 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
7524 | DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); | |
7525 | ||
7526 | bnx2x_cl45_read(bp, phy, | |
7527 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
7528 | bnx2x_cl45_read(bp, phy, | |
7529 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
7530 | link_up = ((val1 & 4) == 4); | |
7531 | DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); | |
7532 | ||
7533 | if (link_up && | |
7534 | ((phy->req_line_speed != SPEED_10000))) { | |
7535 | if (bnx2x_8073_xaui_wa(bp, phy) != 0) | |
7536 | return 0; | |
62b29a5d | 7537 | } |
de6eae1f YR |
7538 | bnx2x_cl45_read(bp, phy, |
7539 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
7540 | bnx2x_cl45_read(bp, phy, | |
7541 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
62b29a5d | 7542 | |
de6eae1f YR |
7543 | /* Check the link status on 1.1.2 */ |
7544 | bnx2x_cl45_read(bp, phy, | |
7545 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
7546 | bnx2x_cl45_read(bp, phy, | |
7547 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
7548 | DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," | |
7549 | "an_link_status=0x%x\n", val2, val1, an1000_status); | |
62b29a5d | 7550 | |
de6eae1f YR |
7551 | link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); |
7552 | if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { | |
8f73f0b9 | 7553 | /* The SNR will improve about 2dbby changing the BW and FEE main |
2cf7acf9 YR |
7554 | * tap. The 1st write to change FFE main tap is set before |
7555 | * restart AN. Change PLL Bandwidth in EDC register | |
7556 | */ | |
62b29a5d | 7557 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
7558 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, |
7559 | 0x26BC); | |
62b29a5d | 7560 | |
de6eae1f | 7561 | /* Change CDR Bandwidth in EDC register */ |
62b29a5d | 7562 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
7563 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, |
7564 | 0x0333); | |
7565 | } | |
7566 | bnx2x_cl45_read(bp, phy, | |
7567 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
7568 | &link_status); | |
62b29a5d | 7569 | |
de6eae1f YR |
7570 | /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ |
7571 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { | |
7572 | link_up = 1; | |
7573 | vars->line_speed = SPEED_10000; | |
7574 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", | |
7575 | params->port); | |
7576 | } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { | |
7577 | link_up = 1; | |
7578 | vars->line_speed = SPEED_2500; | |
7579 | DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", | |
7580 | params->port); | |
7581 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { | |
7582 | link_up = 1; | |
7583 | vars->line_speed = SPEED_1000; | |
7584 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
7585 | params->port); | |
7586 | } else { | |
7587 | link_up = 0; | |
7588 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
7589 | params->port); | |
62b29a5d | 7590 | } |
de6eae1f YR |
7591 | |
7592 | if (link_up) { | |
74d7a119 YR |
7593 | /* Swap polarity if required */ |
7594 | if (params->lane_config & | |
7595 | PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
7596 | /* Configure the 8073 to swap P and N of the KR lines */ | |
7597 | bnx2x_cl45_read(bp, phy, | |
7598 | MDIO_XS_DEVAD, | |
7599 | MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); | |
8f73f0b9 | 7600 | /* Set bit 3 to invert Rx in 1G mode and clear this bit |
2cf7acf9 YR |
7601 | * when it`s in 10G mode. |
7602 | */ | |
74d7a119 YR |
7603 | if (vars->line_speed == SPEED_1000) { |
7604 | DP(NETIF_MSG_LINK, "Swapping 1G polarity for" | |
7605 | "the 8073\n"); | |
7606 | val1 |= (1<<3); | |
7607 | } else | |
7608 | val1 &= ~(1<<3); | |
7609 | ||
7610 | bnx2x_cl45_write(bp, phy, | |
7611 | MDIO_XS_DEVAD, | |
7612 | MDIO_XS_REG_8073_RX_CTRL_PCIE, | |
7613 | val1); | |
7614 | } | |
de6eae1f YR |
7615 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); |
7616 | bnx2x_8073_resolve_fc(phy, params, vars); | |
791f18c0 | 7617 | vars->duplex = DUPLEX_FULL; |
de6eae1f | 7618 | } |
9e7e8399 MY |
7619 | |
7620 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
7621 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
7622 | MDIO_AN_REG_LP_AUTO_NEG2, &val1); | |
7623 | ||
7624 | if (val1 & (1<<5)) | |
7625 | vars->link_status |= | |
7626 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
7627 | if (val1 & (1<<7)) | |
7628 | vars->link_status |= | |
7629 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
7630 | } | |
7631 | ||
de6eae1f | 7632 | return link_up; |
b7737c9b YR |
7633 | } |
7634 | ||
de6eae1f YR |
7635 | static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, |
7636 | struct link_params *params) | |
7637 | { | |
7638 | struct bnx2x *bp = params->bp; | |
7639 | u8 gpio_port; | |
f2e0899f DK |
7640 | if (CHIP_IS_E2(bp)) |
7641 | gpio_port = BP_PATH(bp); | |
7642 | else | |
7643 | gpio_port = params->port; | |
de6eae1f YR |
7644 | DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", |
7645 | gpio_port); | |
7646 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee YR |
7647 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
7648 | gpio_port); | |
de6eae1f YR |
7649 | } |
7650 | ||
7651 | /******************************************************************/ | |
7652 | /* BCM8705 PHY SECTION */ | |
7653 | /******************************************************************/ | |
fcf5b650 YR |
7654 | static int bnx2x_8705_config_init(struct bnx2x_phy *phy, |
7655 | struct link_params *params, | |
7656 | struct link_vars *vars) | |
b7737c9b YR |
7657 | { |
7658 | struct bnx2x *bp = params->bp; | |
de6eae1f | 7659 | DP(NETIF_MSG_LINK, "init 8705\n"); |
b7737c9b YR |
7660 | /* Restore normal power mode*/ |
7661 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 7662 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
7663 | /* HW reset */ |
7664 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
7665 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
6d870c39 | 7666 | bnx2x_wait_reset_complete(bp, phy, params); |
b7737c9b | 7667 | |
de6eae1f YR |
7668 | bnx2x_cl45_write(bp, phy, |
7669 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); | |
7670 | bnx2x_cl45_write(bp, phy, | |
7671 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); | |
7672 | bnx2x_cl45_write(bp, phy, | |
7673 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); | |
7674 | bnx2x_cl45_write(bp, phy, | |
7675 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); | |
7676 | /* BCM8705 doesn't have microcode, hence the 0 */ | |
7677 | bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); | |
7678 | return 0; | |
7679 | } | |
4d295db0 | 7680 | |
de6eae1f YR |
7681 | static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, |
7682 | struct link_params *params, | |
7683 | struct link_vars *vars) | |
7684 | { | |
7685 | u8 link_up = 0; | |
7686 | u16 val1, rx_sd; | |
7687 | struct bnx2x *bp = params->bp; | |
7688 | DP(NETIF_MSG_LINK, "read status 8705\n"); | |
7689 | bnx2x_cl45_read(bp, phy, | |
7690 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
7691 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 7692 | |
de6eae1f YR |
7693 | bnx2x_cl45_read(bp, phy, |
7694 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
7695 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 7696 | |
de6eae1f YR |
7697 | bnx2x_cl45_read(bp, phy, |
7698 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); | |
c2c8b03e | 7699 | |
de6eae1f YR |
7700 | bnx2x_cl45_read(bp, phy, |
7701 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
7702 | bnx2x_cl45_read(bp, phy, | |
7703 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
c2c8b03e | 7704 | |
de6eae1f YR |
7705 | DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); |
7706 | link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); | |
7707 | if (link_up) { | |
7708 | vars->line_speed = SPEED_10000; | |
7709 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
62b29a5d | 7710 | } |
de6eae1f YR |
7711 | return link_up; |
7712 | } | |
d90d96ba | 7713 | |
de6eae1f YR |
7714 | /******************************************************************/ |
7715 | /* SFP+ module Section */ | |
7716 | /******************************************************************/ | |
85242eea YR |
7717 | static void bnx2x_set_disable_pmd_transmit(struct link_params *params, |
7718 | struct bnx2x_phy *phy, | |
7719 | u8 pmd_dis) | |
7720 | { | |
7721 | struct bnx2x *bp = params->bp; | |
8f73f0b9 | 7722 | /* Disable transmitter only for bootcodes which can enable it afterwards |
85242eea YR |
7723 | * (for D3 link) |
7724 | */ | |
7725 | if (pmd_dis) { | |
7726 | if (params->feature_config_flags & | |
7727 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) | |
7728 | DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); | |
7729 | else { | |
7730 | DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); | |
7731 | return; | |
7732 | } | |
7733 | } else | |
7734 | DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); | |
7735 | bnx2x_cl45_write(bp, phy, | |
7736 | MDIO_PMA_DEVAD, | |
7737 | MDIO_PMA_REG_TX_DISABLE, pmd_dis); | |
7738 | } | |
7739 | ||
a8db5b4c YR |
7740 | static u8 bnx2x_get_gpio_port(struct link_params *params) |
7741 | { | |
7742 | u8 gpio_port; | |
7743 | u32 swap_val, swap_override; | |
7744 | struct bnx2x *bp = params->bp; | |
7745 | if (CHIP_IS_E2(bp)) | |
7746 | gpio_port = BP_PATH(bp); | |
7747 | else | |
7748 | gpio_port = params->port; | |
7749 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
7750 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
7751 | return gpio_port ^ (swap_val && swap_override); | |
7752 | } | |
3c9ada22 YR |
7753 | |
7754 | static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, | |
7755 | struct bnx2x_phy *phy, | |
7756 | u8 tx_en) | |
de6eae1f YR |
7757 | { |
7758 | u16 val; | |
a8db5b4c YR |
7759 | u8 port = params->port; |
7760 | struct bnx2x *bp = params->bp; | |
7761 | u32 tx_en_mode; | |
d90d96ba | 7762 | |
de6eae1f | 7763 | /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ |
a8db5b4c YR |
7764 | tx_en_mode = REG_RD(bp, params->shmem_base + |
7765 | offsetof(struct shmem_region, | |
7766 | dev_info.port_hw_config[port].sfp_ctrl)) & | |
7767 | PORT_HW_CFG_TX_LASER_MASK; | |
7768 | DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " | |
7769 | "mode = %x\n", tx_en, port, tx_en_mode); | |
7770 | switch (tx_en_mode) { | |
7771 | case PORT_HW_CFG_TX_LASER_MDIO: | |
d90d96ba | 7772 | |
a8db5b4c YR |
7773 | bnx2x_cl45_read(bp, phy, |
7774 | MDIO_PMA_DEVAD, | |
7775 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
7776 | &val); | |
b7737c9b | 7777 | |
a8db5b4c YR |
7778 | if (tx_en) |
7779 | val &= ~(1<<15); | |
7780 | else | |
7781 | val |= (1<<15); | |
7782 | ||
7783 | bnx2x_cl45_write(bp, phy, | |
7784 | MDIO_PMA_DEVAD, | |
7785 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
7786 | val); | |
7787 | break; | |
7788 | case PORT_HW_CFG_TX_LASER_GPIO0: | |
7789 | case PORT_HW_CFG_TX_LASER_GPIO1: | |
7790 | case PORT_HW_CFG_TX_LASER_GPIO2: | |
7791 | case PORT_HW_CFG_TX_LASER_GPIO3: | |
7792 | { | |
7793 | u16 gpio_pin; | |
7794 | u8 gpio_port, gpio_mode; | |
7795 | if (tx_en) | |
7796 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; | |
7797 | else | |
7798 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; | |
7799 | ||
7800 | gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; | |
7801 | gpio_port = bnx2x_get_gpio_port(params); | |
7802 | bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); | |
7803 | break; | |
7804 | } | |
7805 | default: | |
7806 | DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); | |
7807 | break; | |
7808 | } | |
b7737c9b YR |
7809 | } |
7810 | ||
3c9ada22 YR |
7811 | static void bnx2x_sfp_set_transmitter(struct link_params *params, |
7812 | struct bnx2x_phy *phy, | |
7813 | u8 tx_en) | |
7814 | { | |
7815 | struct bnx2x *bp = params->bp; | |
7816 | DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); | |
7817 | if (CHIP_IS_E3(bp)) | |
7818 | bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); | |
7819 | else | |
7820 | bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); | |
7821 | } | |
7822 | ||
fcf5b650 YR |
7823 | static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7824 | struct link_params *params, | |
669d6996 YR |
7825 | u8 dev_addr, u16 addr, u8 byte_cnt, |
7826 | u8 *o_buf, u8 is_init) | |
b7737c9b YR |
7827 | { |
7828 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
7829 | u16 val = 0; |
7830 | u16 i; | |
24ea818e | 7831 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { |
94f05b0f JP |
7832 | DP(NETIF_MSG_LINK, |
7833 | "Reading from eeprom is limited to 0xf\n"); | |
de6eae1f YR |
7834 | return -EINVAL; |
7835 | } | |
7836 | /* Set the read command byte count */ | |
62b29a5d | 7837 | bnx2x_cl45_write(bp, phy, |
de6eae1f | 7838 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, |
669d6996 | 7839 | (byte_cnt | (dev_addr << 8))); |
ea4e040a | 7840 | |
de6eae1f YR |
7841 | /* Set the read command address */ |
7842 | bnx2x_cl45_write(bp, phy, | |
7843 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
cd88ccee | 7844 | addr); |
ea4e040a | 7845 | |
de6eae1f | 7846 | /* Activate read command */ |
62b29a5d | 7847 | bnx2x_cl45_write(bp, phy, |
de6eae1f | 7848 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, |
cd88ccee | 7849 | 0x2c0f); |
ea4e040a | 7850 | |
de6eae1f YR |
7851 | /* Wait up to 500us for command complete status */ |
7852 | for (i = 0; i < 100; i++) { | |
7853 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7854 | MDIO_PMA_DEVAD, |
7855 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7856 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7857 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
7858 | break; | |
7859 | udelay(5); | |
62b29a5d | 7860 | } |
62b29a5d | 7861 | |
de6eae1f YR |
7862 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
7863 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
7864 | DP(NETIF_MSG_LINK, | |
7865 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
7866 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
7867 | return -EINVAL; | |
62b29a5d | 7868 | } |
e10bc84d | 7869 | |
de6eae1f YR |
7870 | /* Read the buffer */ |
7871 | for (i = 0; i < byte_cnt; i++) { | |
62b29a5d | 7872 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
7873 | MDIO_PMA_DEVAD, |
7874 | MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); | |
de6eae1f | 7875 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); |
62b29a5d | 7876 | } |
6bbca910 | 7877 | |
de6eae1f YR |
7878 | for (i = 0; i < 100; i++) { |
7879 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7880 | MDIO_PMA_DEVAD, |
7881 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7882 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7883 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
6f38ad93 | 7884 | return 0; |
503976e9 | 7885 | usleep_range(1000, 2000); |
de6eae1f YR |
7886 | } |
7887 | return -EINVAL; | |
b7737c9b | 7888 | } |
4d295db0 | 7889 | |
50a29845 | 7890 | static void bnx2x_warpcore_power_module(struct link_params *params, |
50a29845 YM |
7891 | u8 power) |
7892 | { | |
7893 | u32 pin_cfg; | |
7894 | struct bnx2x *bp = params->bp; | |
7895 | ||
7896 | pin_cfg = (REG_RD(bp, params->shmem_base + | |
7897 | offsetof(struct shmem_region, | |
7898 | dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & | |
7899 | PORT_HW_CFG_E3_PWR_DIS_MASK) >> | |
7900 | PORT_HW_CFG_E3_PWR_DIS_SHIFT; | |
7901 | ||
7902 | if (pin_cfg == PIN_CFG_NA) | |
7903 | return; | |
7904 | DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", | |
7905 | power, pin_cfg); | |
7906 | /* Low ==> corresponding SFP+ module is powered | |
7907 | * high ==> the SFP+ module is powered down | |
7908 | */ | |
7909 | bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); | |
7910 | } | |
3c9ada22 YR |
7911 | static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7912 | struct link_params *params, | |
669d6996 | 7913 | u8 dev_addr, |
3c9ada22 | 7914 | u16 addr, u8 byte_cnt, |
e82041df | 7915 | u8 *o_buf, u8 is_init) |
3c9ada22 YR |
7916 | { |
7917 | int rc = 0; | |
7918 | u8 i, j = 0, cnt = 0; | |
7919 | u32 data_array[4]; | |
7920 | u16 addr32; | |
7921 | struct bnx2x *bp = params->bp; | |
24ea818e YM |
7922 | |
7923 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { | |
94f05b0f JP |
7924 | DP(NETIF_MSG_LINK, |
7925 | "Reading from eeprom is limited to 16 bytes\n"); | |
3c9ada22 YR |
7926 | return -EINVAL; |
7927 | } | |
7928 | ||
7929 | /* 4 byte aligned address */ | |
7930 | addr32 = addr & (~0x3); | |
7931 | do { | |
e82041df | 7932 | if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { |
5a1fbf40 | 7933 | bnx2x_warpcore_power_module(params, 0); |
50a29845 | 7934 | /* Note that 100us are not enough here */ |
e82041df | 7935 | usleep_range(1000, 2000); |
5a1fbf40 | 7936 | bnx2x_warpcore_power_module(params, 1); |
50a29845 | 7937 | } |
d67710ff | 7938 | rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt, |
3c9ada22 YR |
7939 | data_array); |
7940 | } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); | |
7941 | ||
7942 | if (rc == 0) { | |
7943 | for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { | |
7944 | o_buf[j] = *((u8 *)data_array + i); | |
7945 | j++; | |
7946 | } | |
7947 | } | |
7948 | ||
7949 | return rc; | |
7950 | } | |
7951 | ||
fcf5b650 YR |
7952 | static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7953 | struct link_params *params, | |
669d6996 YR |
7954 | u8 dev_addr, u16 addr, u8 byte_cnt, |
7955 | u8 *o_buf, u8 is_init) | |
b7737c9b | 7956 | { |
b7737c9b | 7957 | struct bnx2x *bp = params->bp; |
de6eae1f | 7958 | u16 val, i; |
ea4e040a | 7959 | |
24ea818e | 7960 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { |
94f05b0f JP |
7961 | DP(NETIF_MSG_LINK, |
7962 | "Reading from eeprom is limited to 0xf\n"); | |
de6eae1f YR |
7963 | return -EINVAL; |
7964 | } | |
4d295db0 | 7965 | |
669d6996 YR |
7966 | /* Set 2-wire transfer rate of SFP+ module EEPROM |
7967 | * to 100Khz since some DACs(direct attached cables) do | |
7968 | * not work at 400Khz. | |
7969 | */ | |
7970 | bnx2x_cl45_write(bp, phy, | |
7971 | MDIO_PMA_DEVAD, | |
7972 | MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, | |
7973 | ((dev_addr << 8) | 1)); | |
7974 | ||
de6eae1f YR |
7975 | /* Need to read from 1.8000 to clear it */ |
7976 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7977 | MDIO_PMA_DEVAD, |
7978 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
7979 | &val); | |
4d295db0 | 7980 | |
de6eae1f | 7981 | /* Set the read command byte count */ |
62b29a5d | 7982 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7983 | MDIO_PMA_DEVAD, |
7984 | MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, | |
7985 | ((byte_cnt < 2) ? 2 : byte_cnt)); | |
ea4e040a | 7986 | |
de6eae1f | 7987 | /* Set the read command address */ |
62b29a5d | 7988 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7989 | MDIO_PMA_DEVAD, |
7990 | MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
7991 | addr); | |
de6eae1f | 7992 | /* Set the destination address */ |
62b29a5d | 7993 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7994 | MDIO_PMA_DEVAD, |
7995 | 0x8004, | |
7996 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); | |
62b29a5d | 7997 | |
de6eae1f | 7998 | /* Activate read command */ |
62b29a5d | 7999 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8000 | MDIO_PMA_DEVAD, |
8001 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
8002 | 0x8002); | |
8f73f0b9 | 8003 | /* Wait appropriate time for two-wire command to finish before |
2cf7acf9 YR |
8004 | * polling the status register |
8005 | */ | |
503976e9 | 8006 | usleep_range(1000, 2000); |
4d295db0 | 8007 | |
de6eae1f YR |
8008 | /* Wait up to 500us for command complete status */ |
8009 | for (i = 0; i < 100; i++) { | |
62b29a5d | 8010 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8011 | MDIO_PMA_DEVAD, |
8012 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
8013 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
8014 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
8015 | break; | |
8016 | udelay(5); | |
62b29a5d | 8017 | } |
4d295db0 | 8018 | |
de6eae1f YR |
8019 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
8020 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
8021 | DP(NETIF_MSG_LINK, | |
8022 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
8023 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
65a001ba | 8024 | return -EFAULT; |
de6eae1f | 8025 | } |
62b29a5d | 8026 | |
de6eae1f YR |
8027 | /* Read the buffer */ |
8028 | for (i = 0; i < byte_cnt; i++) { | |
8029 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
8030 | MDIO_PMA_DEVAD, |
8031 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); | |
de6eae1f YR |
8032 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); |
8033 | } | |
4d295db0 | 8034 | |
de6eae1f YR |
8035 | for (i = 0; i < 100; i++) { |
8036 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
8037 | MDIO_PMA_DEVAD, |
8038 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
8039 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
8040 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
6f38ad93 | 8041 | return 0; |
503976e9 | 8042 | usleep_range(1000, 2000); |
62b29a5d YR |
8043 | } |
8044 | ||
de6eae1f | 8045 | return -EINVAL; |
b7737c9b | 8046 | } |
fcf5b650 | 8047 | int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
669d6996 YR |
8048 | struct link_params *params, u8 dev_addr, |
8049 | u16 addr, u16 byte_cnt, u8 *o_buf) | |
b7737c9b | 8050 | { |
669d6996 YR |
8051 | int rc = 0; |
8052 | struct bnx2x *bp = params->bp; | |
8053 | u8 xfer_size; | |
8054 | u8 *user_data = o_buf; | |
8055 | read_sfp_module_eeprom_func_p read_func; | |
8056 | ||
8057 | if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { | |
8058 | DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr); | |
8059 | return -EINVAL; | |
8060 | } | |
8061 | ||
e4d78f12 YR |
8062 | switch (phy->type) { |
8063 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
669d6996 YR |
8064 | read_func = bnx2x_8726_read_sfp_module_eeprom; |
8065 | break; | |
e4d78f12 YR |
8066 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
8067 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
669d6996 YR |
8068 | read_func = bnx2x_8727_read_sfp_module_eeprom; |
8069 | break; | |
3c9ada22 | 8070 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
669d6996 YR |
8071 | read_func = bnx2x_warpcore_read_sfp_module_eeprom; |
8072 | break; | |
8073 | default: | |
8074 | return -EOPNOTSUPP; | |
8075 | } | |
8076 | ||
8077 | while (!rc && (byte_cnt > 0)) { | |
8078 | xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ? | |
8079 | SFP_EEPROM_PAGE_SIZE : byte_cnt; | |
8080 | rc = read_func(phy, params, dev_addr, addr, xfer_size, | |
8081 | user_data, 0); | |
8082 | byte_cnt -= xfer_size; | |
8083 | user_data += xfer_size; | |
8084 | addr += xfer_size; | |
e4d78f12 YR |
8085 | } |
8086 | return rc; | |
b7737c9b YR |
8087 | } |
8088 | ||
fcf5b650 YR |
8089 | static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, |
8090 | struct link_params *params, | |
8091 | u16 *edc_mode) | |
b7737c9b YR |
8092 | { |
8093 | struct bnx2x *bp = params->bp; | |
1ac9e428 | 8094 | u32 sync_offset = 0, phy_idx, media_types; |
52160da7 | 8095 | u8 gport, val[2], check_limiting_mode = 0; |
de6eae1f | 8096 | *edc_mode = EDC_MODE_LIMITING; |
1ac9e428 | 8097 | phy->media_type = ETH_PHY_UNSPECIFIED; |
de6eae1f YR |
8098 | /* First check for copper cable */ |
8099 | if (bnx2x_read_sfp_module_eeprom(phy, | |
8100 | params, | |
669d6996 | 8101 | I2C_DEV_ADDR_A0, |
de6eae1f | 8102 | SFP_EEPROM_CON_TYPE_ADDR, |
dbef807e YM |
8103 | 2, |
8104 | (u8 *)val) != 0) { | |
de6eae1f YR |
8105 | DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); |
8106 | return -EINVAL; | |
8107 | } | |
a1e4be39 | 8108 | |
dbef807e | 8109 | switch (val[0]) { |
de6eae1f YR |
8110 | case SFP_EEPROM_CON_TYPE_VAL_COPPER: |
8111 | { | |
8112 | u8 copper_module_type; | |
1ac9e428 | 8113 | phy->media_type = ETH_PHY_DA_TWINAX; |
8f73f0b9 | 8114 | /* Check if its active cable (includes SFP+ module) |
2cf7acf9 YR |
8115 | * of passive cable |
8116 | */ | |
de6eae1f YR |
8117 | if (bnx2x_read_sfp_module_eeprom(phy, |
8118 | params, | |
669d6996 | 8119 | I2C_DEV_ADDR_A0, |
de6eae1f YR |
8120 | SFP_EEPROM_FC_TX_TECH_ADDR, |
8121 | 1, | |
9045f6b4 | 8122 | &copper_module_type) != 0) { |
de6eae1f YR |
8123 | DP(NETIF_MSG_LINK, |
8124 | "Failed to read copper-cable-type" | |
8125 | " from SFP+ EEPROM\n"); | |
8126 | return -EINVAL; | |
8127 | } | |
4f60dab1 | 8128 | |
de6eae1f YR |
8129 | if (copper_module_type & |
8130 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { | |
8131 | DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); | |
869952e3 YR |
8132 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
8133 | *edc_mode = EDC_MODE_ACTIVE_DAC; | |
8134 | else | |
8135 | check_limiting_mode = 1; | |
e803d33a YR |
8136 | } else { |
8137 | *edc_mode = EDC_MODE_PASSIVE_DAC; | |
8138 | /* Even in case PASSIVE_DAC indication is not set, | |
8139 | * treat it as a passive DAC cable, since some cables | |
8140 | * don't have this indication. | |
8141 | */ | |
8142 | if (copper_module_type & | |
8143 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { | |
94f05b0f JP |
8144 | DP(NETIF_MSG_LINK, |
8145 | "Passive Copper cable detected\n"); | |
e803d33a YR |
8146 | } else { |
8147 | DP(NETIF_MSG_LINK, | |
8148 | "Unknown copper-cable-type\n"); | |
8149 | } | |
de6eae1f YR |
8150 | } |
8151 | break; | |
62b29a5d | 8152 | } |
de6eae1f | 8153 | case SFP_EEPROM_CON_TYPE_VAL_LC: |
b807c748 | 8154 | case SFP_EEPROM_CON_TYPE_VAL_RJ45: |
de6eae1f | 8155 | check_limiting_mode = 1; |
dbef807e YM |
8156 | if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK | |
8157 | SFP_EEPROM_COMP_CODE_LR_MASK | | |
8158 | SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { | |
b807c748 | 8159 | DP(NETIF_MSG_LINK, "1G SFP module detected\n"); |
52160da7 | 8160 | gport = params->port; |
dbef807e | 8161 | phy->media_type = ETH_PHY_SFP_1G_FIBER; |
b807c748 YR |
8162 | if (phy->req_line_speed != SPEED_1000) { |
8163 | phy->req_line_speed = SPEED_1000; | |
8164 | if (!CHIP_IS_E1x(bp)) { | |
8165 | gport = BP_PATH(bp) + | |
8166 | (params->port << 1); | |
8167 | } | |
8168 | netdev_err(bp->dev, | |
8169 | "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n", | |
8170 | gport); | |
8171 | } | |
dbef807e YM |
8172 | } else { |
8173 | int idx, cfg_idx = 0; | |
8174 | DP(NETIF_MSG_LINK, "10G Optic module detected\n"); | |
8175 | for (idx = INT_PHY; idx < MAX_PHYS; idx++) { | |
8176 | if (params->phy[idx].type == phy->type) { | |
8177 | cfg_idx = LINK_CONFIG_IDX(idx); | |
8178 | break; | |
8179 | } | |
8180 | } | |
8181 | phy->media_type = ETH_PHY_SFPP_10G_FIBER; | |
8182 | phy->req_line_speed = params->req_line_speed[cfg_idx]; | |
8183 | } | |
de6eae1f YR |
8184 | break; |
8185 | default: | |
8186 | DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", | |
dbef807e | 8187 | val[0]); |
de6eae1f | 8188 | return -EINVAL; |
62b29a5d | 8189 | } |
1ac9e428 YR |
8190 | sync_offset = params->shmem_base + |
8191 | offsetof(struct shmem_region, | |
8192 | dev_info.port_hw_config[params->port].media_type); | |
8193 | media_types = REG_RD(bp, sync_offset); | |
8194 | /* Update media type for non-PMF sync */ | |
8195 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { | |
8196 | if (&(params->phy[phy_idx]) == phy) { | |
8197 | media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << | |
8198 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); | |
8199 | media_types |= ((phy->media_type & | |
8200 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << | |
8201 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); | |
8202 | break; | |
8203 | } | |
8204 | } | |
8205 | REG_WR(bp, sync_offset, media_types); | |
de6eae1f YR |
8206 | if (check_limiting_mode) { |
8207 | u8 options[SFP_EEPROM_OPTIONS_SIZE]; | |
8208 | if (bnx2x_read_sfp_module_eeprom(phy, | |
8209 | params, | |
669d6996 | 8210 | I2C_DEV_ADDR_A0, |
de6eae1f YR |
8211 | SFP_EEPROM_OPTIONS_ADDR, |
8212 | SFP_EEPROM_OPTIONS_SIZE, | |
8213 | options) != 0) { | |
94f05b0f JP |
8214 | DP(NETIF_MSG_LINK, |
8215 | "Failed to read Option field from module EEPROM\n"); | |
de6eae1f YR |
8216 | return -EINVAL; |
8217 | } | |
8218 | if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) | |
8219 | *edc_mode = EDC_MODE_LINEAR; | |
8220 | else | |
8221 | *edc_mode = EDC_MODE_LIMITING; | |
62b29a5d | 8222 | } |
de6eae1f | 8223 | DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); |
62b29a5d | 8224 | return 0; |
b7737c9b | 8225 | } |
8f73f0b9 | 8226 | /* This function read the relevant field from the module (SFP+), and verify it |
2cf7acf9 YR |
8227 | * is compliant with this board |
8228 | */ | |
fcf5b650 YR |
8229 | static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, |
8230 | struct link_params *params) | |
b7737c9b YR |
8231 | { |
8232 | struct bnx2x *bp = params->bp; | |
a22f0788 YR |
8233 | u32 val, cmd; |
8234 | u32 fw_resp, fw_cmd_param; | |
de6eae1f YR |
8235 | char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; |
8236 | char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; | |
a22f0788 | 8237 | phy->flags &= ~FLAGS_SFP_NOT_APPROVED; |
de6eae1f YR |
8238 | val = REG_RD(bp, params->shmem_base + |
8239 | offsetof(struct shmem_region, dev_info. | |
8240 | port_feature_config[params->port].config)); | |
8241 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8242 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { | |
8243 | DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); | |
8244 | return 0; | |
8245 | } | |
ea4e040a | 8246 | |
a22f0788 YR |
8247 | if (params->feature_config_flags & |
8248 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { | |
8249 | /* Use specific phy request */ | |
8250 | cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; | |
8251 | } else if (params->feature_config_flags & | |
8252 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { | |
8253 | /* Use first phy request only in case of non-dual media*/ | |
8254 | if (DUAL_MEDIA(params)) { | |
94f05b0f JP |
8255 | DP(NETIF_MSG_LINK, |
8256 | "FW does not support OPT MDL verification\n"); | |
a22f0788 YR |
8257 | return -EINVAL; |
8258 | } | |
8259 | cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; | |
8260 | } else { | |
8261 | /* No support in OPT MDL detection */ | |
94f05b0f JP |
8262 | DP(NETIF_MSG_LINK, |
8263 | "FW does not support OPT MDL verification\n"); | |
de6eae1f YR |
8264 | return -EINVAL; |
8265 | } | |
523224a3 | 8266 | |
a22f0788 YR |
8267 | fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); |
8268 | fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); | |
de6eae1f YR |
8269 | if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { |
8270 | DP(NETIF_MSG_LINK, "Approved module\n"); | |
8271 | return 0; | |
8272 | } | |
b7737c9b | 8273 | |
d231023e | 8274 | /* Format the warning message */ |
de6eae1f YR |
8275 | if (bnx2x_read_sfp_module_eeprom(phy, |
8276 | params, | |
669d6996 | 8277 | I2C_DEV_ADDR_A0, |
cd88ccee YR |
8278 | SFP_EEPROM_VENDOR_NAME_ADDR, |
8279 | SFP_EEPROM_VENDOR_NAME_SIZE, | |
8280 | (u8 *)vendor_name)) | |
de6eae1f YR |
8281 | vendor_name[0] = '\0'; |
8282 | else | |
8283 | vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; | |
8284 | if (bnx2x_read_sfp_module_eeprom(phy, | |
8285 | params, | |
669d6996 | 8286 | I2C_DEV_ADDR_A0, |
cd88ccee YR |
8287 | SFP_EEPROM_PART_NO_ADDR, |
8288 | SFP_EEPROM_PART_NO_SIZE, | |
8289 | (u8 *)vendor_pn)) | |
de6eae1f YR |
8290 | vendor_pn[0] = '\0'; |
8291 | else | |
8292 | vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; | |
8293 | ||
6d870c39 YR |
8294 | netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," |
8295 | " Port %d from %s part number %s\n", | |
8296 | params->port, vendor_name, vendor_pn); | |
59a2e53b YR |
8297 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != |
8298 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) | |
8299 | phy->flags |= FLAGS_SFP_NOT_APPROVED; | |
de6eae1f | 8300 | return -EINVAL; |
b7737c9b | 8301 | } |
7aa0711f | 8302 | |
fcf5b650 YR |
8303 | static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, |
8304 | struct link_params *params) | |
7aa0711f | 8305 | |
4d295db0 | 8306 | { |
de6eae1f | 8307 | u8 val; |
e82041df | 8308 | int rc; |
4d295db0 | 8309 | struct bnx2x *bp = params->bp; |
de6eae1f | 8310 | u16 timeout; |
8f73f0b9 | 8311 | /* Initialization time after hot-plug may take up to 300ms for |
2cf7acf9 YR |
8312 | * some phys type ( e.g. JDSU ) |
8313 | */ | |
8314 | ||
de6eae1f | 8315 | for (timeout = 0; timeout < 60; timeout++) { |
e82041df | 8316 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
669d6996 YR |
8317 | rc = bnx2x_warpcore_read_sfp_module_eeprom( |
8318 | phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, | |
8319 | 1); | |
e82041df | 8320 | else |
669d6996 YR |
8321 | rc = bnx2x_read_sfp_module_eeprom(phy, params, |
8322 | I2C_DEV_ADDR_A0, | |
8323 | 1, 1, &val); | |
e82041df | 8324 | if (rc == 0) { |
94f05b0f JP |
8325 | DP(NETIF_MSG_LINK, |
8326 | "SFP+ module initialization took %d ms\n", | |
8327 | timeout * 5); | |
de6eae1f YR |
8328 | return 0; |
8329 | } | |
d231023e | 8330 | usleep_range(5000, 10000); |
de6eae1f | 8331 | } |
669d6996 YR |
8332 | rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0, |
8333 | 1, 1, &val); | |
e82041df | 8334 | return rc; |
de6eae1f | 8335 | } |
4d295db0 | 8336 | |
de6eae1f YR |
8337 | static void bnx2x_8727_power_module(struct bnx2x *bp, |
8338 | struct bnx2x_phy *phy, | |
8339 | u8 is_power_up) { | |
8340 | /* Make sure GPIOs are not using for LED mode */ | |
8341 | u16 val; | |
8f73f0b9 | 8342 | /* In the GPIO register, bit 4 is use to determine if the GPIOs are |
de6eae1f YR |
8343 | * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for |
8344 | * output | |
3c9ada22 YR |
8345 | * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 |
8346 | * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 | |
de6eae1f YR |
8347 | * where the 1st bit is the over-current(only input), and 2nd bit is |
8348 | * for power( only output ) | |
2cf7acf9 | 8349 | * |
de6eae1f YR |
8350 | * In case of NOC feature is disabled and power is up, set GPIO control |
8351 | * as input to enable listening of over-current indication | |
8352 | */ | |
8353 | if (phy->flags & FLAGS_NOC) | |
8354 | return; | |
27d02432 | 8355 | if (is_power_up) |
de6eae1f YR |
8356 | val = (1<<4); |
8357 | else | |
8f73f0b9 | 8358 | /* Set GPIO control to OUTPUT, and set the power bit |
de6eae1f YR |
8359 | * to according to the is_power_up |
8360 | */ | |
27d02432 | 8361 | val = (1<<1); |
4d295db0 | 8362 | |
de6eae1f YR |
8363 | bnx2x_cl45_write(bp, phy, |
8364 | MDIO_PMA_DEVAD, | |
8365 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
8366 | val); | |
8367 | } | |
4d295db0 | 8368 | |
fcf5b650 YR |
8369 | static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, |
8370 | struct bnx2x_phy *phy, | |
8371 | u16 edc_mode) | |
de6eae1f YR |
8372 | { |
8373 | u16 cur_limiting_mode; | |
4d295db0 | 8374 | |
de6eae1f | 8375 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8376 | MDIO_PMA_DEVAD, |
8377 | MDIO_PMA_REG_ROM_VER2, | |
8378 | &cur_limiting_mode); | |
de6eae1f YR |
8379 | DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", |
8380 | cur_limiting_mode); | |
8381 | ||
8382 | if (edc_mode == EDC_MODE_LIMITING) { | |
cd88ccee | 8383 | DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); |
e10bc84d | 8384 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 8385 | MDIO_PMA_DEVAD, |
de6eae1f YR |
8386 | MDIO_PMA_REG_ROM_VER2, |
8387 | EDC_MODE_LIMITING); | |
8388 | } else { /* LRM mode ( default )*/ | |
4d295db0 | 8389 | |
de6eae1f | 8390 | DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); |
4d295db0 | 8391 | |
8f73f0b9 | 8392 | /* Changing to LRM mode takes quite few seconds. So do it only |
2cf7acf9 YR |
8393 | * if current mode is limiting (default is LRM) |
8394 | */ | |
de6eae1f YR |
8395 | if (cur_limiting_mode != EDC_MODE_LIMITING) |
8396 | return 0; | |
4d295db0 | 8397 | |
de6eae1f | 8398 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8399 | MDIO_PMA_DEVAD, |
8400 | MDIO_PMA_REG_LRM_MODE, | |
8401 | 0); | |
de6eae1f | 8402 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8403 | MDIO_PMA_DEVAD, |
8404 | MDIO_PMA_REG_ROM_VER2, | |
8405 | 0x128); | |
de6eae1f | 8406 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8407 | MDIO_PMA_DEVAD, |
8408 | MDIO_PMA_REG_MISC_CTRL0, | |
8409 | 0x4008); | |
de6eae1f | 8410 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8411 | MDIO_PMA_DEVAD, |
8412 | MDIO_PMA_REG_LRM_MODE, | |
8413 | 0xaaaa); | |
4d295db0 | 8414 | } |
de6eae1f | 8415 | return 0; |
4d295db0 EG |
8416 | } |
8417 | ||
fcf5b650 YR |
8418 | static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, |
8419 | struct bnx2x_phy *phy, | |
8420 | u16 edc_mode) | |
ea4e040a | 8421 | { |
de6eae1f YR |
8422 | u16 phy_identifier; |
8423 | u16 rom_ver2_val; | |
62b29a5d | 8424 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8425 | MDIO_PMA_DEVAD, |
8426 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8427 | &phy_identifier); | |
ea4e040a | 8428 | |
de6eae1f | 8429 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8430 | MDIO_PMA_DEVAD, |
8431 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8432 | (phy_identifier & ~(1<<9))); | |
ea4e040a | 8433 | |
62b29a5d | 8434 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8435 | MDIO_PMA_DEVAD, |
8436 | MDIO_PMA_REG_ROM_VER2, | |
8437 | &rom_ver2_val); | |
de6eae1f YR |
8438 | /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ |
8439 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
8440 | MDIO_PMA_DEVAD, |
8441 | MDIO_PMA_REG_ROM_VER2, | |
8442 | (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); | |
4d295db0 | 8443 | |
de6eae1f | 8444 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8445 | MDIO_PMA_DEVAD, |
8446 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8447 | (phy_identifier | (1<<9))); | |
4d295db0 | 8448 | |
de6eae1f | 8449 | return 0; |
b7737c9b | 8450 | } |
ea4e040a | 8451 | |
a22f0788 YR |
8452 | static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, |
8453 | struct link_params *params, | |
8454 | u32 action) | |
8455 | { | |
8456 | struct bnx2x *bp = params->bp; | |
5c107fda | 8457 | u16 val; |
a22f0788 YR |
8458 | switch (action) { |
8459 | case DISABLE_TX: | |
a8db5b4c | 8460 | bnx2x_sfp_set_transmitter(params, phy, 0); |
a22f0788 YR |
8461 | break; |
8462 | case ENABLE_TX: | |
8463 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) | |
a8db5b4c | 8464 | bnx2x_sfp_set_transmitter(params, phy, 1); |
a22f0788 | 8465 | break; |
5c107fda YR |
8466 | case PHY_INIT: |
8467 | bnx2x_cl45_write(bp, phy, | |
8468 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, | |
8469 | (1<<2) | (1<<5)); | |
8470 | bnx2x_cl45_write(bp, phy, | |
8471 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, | |
8472 | 0); | |
8473 | bnx2x_cl45_write(bp, phy, | |
8474 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); | |
8475 | /* Make MOD_ABS give interrupt on change */ | |
8476 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
8477 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
8478 | &val); | |
8479 | val |= (1<<12); | |
8480 | if (phy->flags & FLAGS_NOC) | |
8481 | val |= (3<<5); | |
8482 | /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 | |
8483 | * status which reflect SFP+ module over-current | |
8484 | */ | |
8485 | if (!(phy->flags & FLAGS_NOC)) | |
8486 | val &= 0xff8f; /* Reset bits 4-6 */ | |
8487 | bnx2x_cl45_write(bp, phy, | |
8488 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
8489 | val); | |
5c107fda | 8490 | break; |
a22f0788 YR |
8491 | default: |
8492 | DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", | |
8493 | action); | |
8494 | return; | |
8495 | } | |
8496 | } | |
8497 | ||
3c9ada22 | 8498 | static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, |
a8db5b4c YR |
8499 | u8 gpio_mode) |
8500 | { | |
8501 | struct bnx2x *bp = params->bp; | |
8502 | ||
8503 | u32 fault_led_gpio = REG_RD(bp, params->shmem_base + | |
8504 | offsetof(struct shmem_region, | |
8505 | dev_info.port_hw_config[params->port].sfp_ctrl)) & | |
8506 | PORT_HW_CFG_FAULT_MODULE_LED_MASK; | |
8507 | switch (fault_led_gpio) { | |
8508 | case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: | |
8509 | return; | |
8510 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: | |
8511 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: | |
8512 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: | |
8513 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: | |
8514 | { | |
8515 | u8 gpio_port = bnx2x_get_gpio_port(params); | |
8516 | u16 gpio_pin = fault_led_gpio - | |
8517 | PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; | |
8518 | DP(NETIF_MSG_LINK, "Set fault module-detected led " | |
8519 | "pin %x port %x mode %x\n", | |
8520 | gpio_pin, gpio_port, gpio_mode); | |
8521 | bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); | |
8522 | } | |
8523 | break; | |
8524 | default: | |
8525 | DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", | |
8526 | fault_led_gpio); | |
8527 | } | |
8528 | } | |
8529 | ||
3c9ada22 YR |
8530 | static void bnx2x_set_e3_module_fault_led(struct link_params *params, |
8531 | u8 gpio_mode) | |
8532 | { | |
8533 | u32 pin_cfg; | |
8534 | u8 port = params->port; | |
8535 | struct bnx2x *bp = params->bp; | |
8536 | pin_cfg = (REG_RD(bp, params->shmem_base + | |
8537 | offsetof(struct shmem_region, | |
8538 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
8539 | PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> | |
8540 | PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; | |
8541 | DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", | |
8542 | gpio_mode, pin_cfg); | |
8543 | bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); | |
8544 | } | |
8545 | ||
8546 | static void bnx2x_set_sfp_module_fault_led(struct link_params *params, | |
8547 | u8 gpio_mode) | |
8548 | { | |
8549 | struct bnx2x *bp = params->bp; | |
8550 | DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); | |
8551 | if (CHIP_IS_E3(bp)) { | |
8f73f0b9 | 8552 | /* Low ==> if SFP+ module is supported otherwise |
3c9ada22 YR |
8553 | * High ==> if SFP+ module is not on the approved vendor list |
8554 | */ | |
8555 | bnx2x_set_e3_module_fault_led(params, gpio_mode); | |
8556 | } else | |
8557 | bnx2x_set_e1e2_module_fault_led(params, gpio_mode); | |
8558 | } | |
8559 | ||
985848f8 YR |
8560 | static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, |
8561 | struct link_params *params) | |
8562 | { | |
b76070b4 | 8563 | struct bnx2x *bp = params->bp; |
5a1fbf40 | 8564 | bnx2x_warpcore_power_module(params, 0); |
b76070b4 YR |
8565 | /* Put Warpcore in low power mode */ |
8566 | REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); | |
8567 | ||
8568 | /* Put LCPLL in low power mode */ | |
8569 | REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); | |
8570 | REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); | |
8571 | REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); | |
985848f8 YR |
8572 | } |
8573 | ||
e4d78f12 YR |
8574 | static void bnx2x_power_sfp_module(struct link_params *params, |
8575 | struct bnx2x_phy *phy, | |
8576 | u8 power) | |
8577 | { | |
8578 | struct bnx2x *bp = params->bp; | |
8579 | DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); | |
8580 | ||
8581 | switch (phy->type) { | |
8582 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
8583 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
8584 | bnx2x_8727_power_module(params->bp, phy, power); | |
8585 | break; | |
3c9ada22 | 8586 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
5a1fbf40 | 8587 | bnx2x_warpcore_power_module(params, power); |
3c9ada22 YR |
8588 | break; |
8589 | default: | |
8590 | break; | |
8591 | } | |
8592 | } | |
8593 | static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, | |
8594 | struct bnx2x_phy *phy, | |
8595 | u16 edc_mode) | |
8596 | { | |
8597 | u16 val = 0; | |
8598 | u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; | |
8599 | struct bnx2x *bp = params->bp; | |
8600 | ||
8601 | u8 lane = bnx2x_get_warpcore_lane(phy, params); | |
8602 | /* This is a global register which controls all lanes */ | |
8603 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
8604 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); | |
8605 | val &= ~(0xf << (lane << 2)); | |
8606 | ||
8607 | switch (edc_mode) { | |
8608 | case EDC_MODE_LINEAR: | |
8609 | case EDC_MODE_LIMITING: | |
8610 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; | |
8611 | break; | |
8612 | case EDC_MODE_PASSIVE_DAC: | |
869952e3 | 8613 | case EDC_MODE_ACTIVE_DAC: |
3c9ada22 YR |
8614 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; |
8615 | break; | |
e4d78f12 YR |
8616 | default: |
8617 | break; | |
8618 | } | |
3c9ada22 YR |
8619 | |
8620 | val |= (mode << (lane << 2)); | |
8621 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
8622 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); | |
8623 | /* A must read */ | |
8624 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
8625 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); | |
8626 | ||
19af03a3 YR |
8627 | /* Restart microcode to re-read the new mode */ |
8628 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
8629 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
3c9ada22 | 8630 | |
e4d78f12 YR |
8631 | } |
8632 | ||
8633 | static void bnx2x_set_limiting_mode(struct link_params *params, | |
8634 | struct bnx2x_phy *phy, | |
8635 | u16 edc_mode) | |
8636 | { | |
8637 | switch (phy->type) { | |
8638 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
8639 | bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); | |
8640 | break; | |
8641 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
8642 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
8643 | bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); | |
8644 | break; | |
3c9ada22 YR |
8645 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
8646 | bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); | |
8647 | break; | |
e4d78f12 YR |
8648 | } |
8649 | } | |
8650 | ||
fcf5b650 YR |
8651 | int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, |
8652 | struct link_params *params) | |
b7737c9b | 8653 | { |
b7737c9b | 8654 | struct bnx2x *bp = params->bp; |
de6eae1f | 8655 | u16 edc_mode; |
fcf5b650 | 8656 | int rc = 0; |
ea4e040a | 8657 | |
de6eae1f YR |
8658 | u32 val = REG_RD(bp, params->shmem_base + |
8659 | offsetof(struct shmem_region, dev_info. | |
8660 | port_feature_config[params->port].config)); | |
5a1fbf40 YR |
8661 | /* Enabled transmitter by default */ |
8662 | bnx2x_sfp_set_transmitter(params, phy, 1); | |
de6eae1f YR |
8663 | DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", |
8664 | params->port); | |
e4d78f12 YR |
8665 | /* Power up module */ |
8666 | bnx2x_power_sfp_module(params, phy, 1); | |
de6eae1f YR |
8667 | if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { |
8668 | DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); | |
8669 | return -EINVAL; | |
cd88ccee | 8670 | } else if (bnx2x_verify_sfp_module(phy, params) != 0) { |
d231023e | 8671 | /* Check SFP+ module compatibility */ |
de6eae1f YR |
8672 | DP(NETIF_MSG_LINK, "Module verification failed!!\n"); |
8673 | rc = -EINVAL; | |
8674 | /* Turn on fault module-detected led */ | |
a8db5b4c YR |
8675 | bnx2x_set_sfp_module_fault_led(params, |
8676 | MISC_REGISTERS_GPIO_HIGH); | |
8677 | ||
e4d78f12 YR |
8678 | /* Check if need to power down the SFP+ module */ |
8679 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8680 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { | |
de6eae1f | 8681 | DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); |
e4d78f12 | 8682 | bnx2x_power_sfp_module(params, phy, 0); |
de6eae1f YR |
8683 | return rc; |
8684 | } | |
8685 | } else { | |
8686 | /* Turn off fault module-detected led */ | |
a8db5b4c | 8687 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); |
62b29a5d | 8688 | } |
b7737c9b | 8689 | |
8f73f0b9 | 8690 | /* Check and set limiting mode / LRM mode on 8726. On 8727 it |
2cf7acf9 YR |
8691 | * is done automatically |
8692 | */ | |
e4d78f12 YR |
8693 | bnx2x_set_limiting_mode(params, phy, edc_mode); |
8694 | ||
5a1fbf40 YR |
8695 | /* Disable transmit for this module if the module is not approved, and |
8696 | * laser needs to be disabled. | |
de6eae1f | 8697 | */ |
5a1fbf40 YR |
8698 | if ((rc) && |
8699 | ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8700 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) | |
a8db5b4c | 8701 | bnx2x_sfp_set_transmitter(params, phy, 0); |
b7737c9b | 8702 | |
de6eae1f YR |
8703 | return rc; |
8704 | } | |
8705 | ||
8706 | void bnx2x_handle_module_detect_int(struct link_params *params) | |
b7737c9b YR |
8707 | { |
8708 | struct bnx2x *bp = params->bp; | |
3c9ada22 | 8709 | struct bnx2x_phy *phy; |
de6eae1f | 8710 | u32 gpio_val; |
3c9ada22 | 8711 | u8 gpio_num, gpio_port; |
5a1fbf40 | 8712 | if (CHIP_IS_E3(bp)) { |
3c9ada22 | 8713 | phy = ¶ms->phy[INT_PHY]; |
5a1fbf40 YR |
8714 | /* Always enable TX laser,will be disabled in case of fault */ |
8715 | bnx2x_sfp_set_transmitter(params, phy, 1); | |
8716 | } else { | |
3c9ada22 | 8717 | phy = ¶ms->phy[EXT_PHY1]; |
5a1fbf40 | 8718 | } |
3c9ada22 YR |
8719 | if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, |
8720 | params->port, &gpio_num, &gpio_port) == | |
8721 | -EINVAL) { | |
8722 | DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); | |
8723 | return; | |
8724 | } | |
4d295db0 | 8725 | |
de6eae1f | 8726 | /* Set valid module led off */ |
a8db5b4c | 8727 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); |
4d295db0 | 8728 | |
2cf7acf9 | 8729 | /* Get current gpio val reflecting module plugged in / out*/ |
3c9ada22 | 8730 | gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); |
62b29a5d | 8731 | |
de6eae1f YR |
8732 | /* Call the handling function in case module is detected */ |
8733 | if (gpio_val == 0) { | |
55386fe8 | 8734 | bnx2x_set_mdio_emac_per_phy(bp, params); |
dbef807e YM |
8735 | bnx2x_set_aer_mmd(params, phy); |
8736 | ||
e4d78f12 | 8737 | bnx2x_power_sfp_module(params, phy, 1); |
3c9ada22 | 8738 | bnx2x_set_gpio_int(bp, gpio_num, |
de6eae1f | 8739 | MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, |
3c9ada22 | 8740 | gpio_port); |
dbef807e | 8741 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { |
de6eae1f | 8742 | bnx2x_sfp_module_detection(phy, params); |
dbef807e YM |
8743 | if (CHIP_IS_E3(bp)) { |
8744 | u16 rx_tx_in_reset; | |
8745 | /* In case WC is out of reset, reconfigure the | |
8746 | * link speed while taking into account 1G | |
8747 | * module limitation. | |
8748 | */ | |
8749 | bnx2x_cl45_read(bp, phy, | |
8750 | MDIO_WC_DEVAD, | |
8751 | MDIO_WC_REG_DIGITAL5_MISC6, | |
8752 | &rx_tx_in_reset); | |
d9169323 YR |
8753 | if ((!rx_tx_in_reset) && |
8754 | (params->link_flags & | |
8755 | PHY_INITIALIZED)) { | |
dbef807e YM |
8756 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
8757 | bnx2x_warpcore_config_sfi(phy, params); | |
8758 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
8759 | } | |
8760 | } | |
8761 | } else { | |
de6eae1f | 8762 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); |
dbef807e | 8763 | } |
de6eae1f | 8764 | } else { |
3c9ada22 | 8765 | bnx2x_set_gpio_int(bp, gpio_num, |
de6eae1f | 8766 | MISC_REGISTERS_GPIO_INT_OUTPUT_SET, |
3c9ada22 | 8767 | gpio_port); |
8f73f0b9 | 8768 | /* Module was plugged out. |
2cf7acf9 YR |
8769 | * Disable transmit for this module |
8770 | */ | |
1ac9e428 | 8771 | phy->media_type = ETH_PHY_NOT_PRESENT; |
62b29a5d | 8772 | } |
de6eae1f | 8773 | } |
62b29a5d | 8774 | |
c688fe2f YR |
8775 | /******************************************************************/ |
8776 | /* Used by 8706 and 8727 */ | |
8777 | /******************************************************************/ | |
8778 | static void bnx2x_sfp_mask_fault(struct bnx2x *bp, | |
8779 | struct bnx2x_phy *phy, | |
8780 | u16 alarm_status_offset, | |
8781 | u16 alarm_ctrl_offset) | |
8782 | { | |
8783 | u16 alarm_status, val; | |
8784 | bnx2x_cl45_read(bp, phy, | |
8785 | MDIO_PMA_DEVAD, alarm_status_offset, | |
8786 | &alarm_status); | |
8787 | bnx2x_cl45_read(bp, phy, | |
8788 | MDIO_PMA_DEVAD, alarm_status_offset, | |
8789 | &alarm_status); | |
8790 | /* Mask or enable the fault event. */ | |
8791 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); | |
8792 | if (alarm_status & (1<<0)) | |
8793 | val &= ~(1<<0); | |
8794 | else | |
8795 | val |= (1<<0); | |
8796 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); | |
8797 | } | |
de6eae1f YR |
8798 | /******************************************************************/ |
8799 | /* common BCM8706/BCM8726 PHY SECTION */ | |
8800 | /******************************************************************/ | |
8801 | static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, | |
8802 | struct link_params *params, | |
8803 | struct link_vars *vars) | |
8804 | { | |
8805 | u8 link_up = 0; | |
8806 | u16 val1, val2, rx_sd, pcs_status; | |
8807 | struct bnx2x *bp = params->bp; | |
8808 | DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); | |
8809 | /* Clear RX Alarm*/ | |
62b29a5d | 8810 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8811 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); |
c688fe2f | 8812 | |
60d2fe03 YR |
8813 | bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, |
8814 | MDIO_PMA_LASI_TXCTRL); | |
c688fe2f | 8815 | |
d231023e | 8816 | /* Clear LASI indication*/ |
de6eae1f | 8817 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8818 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f | 8819 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8820 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); |
de6eae1f | 8821 | DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); |
62b29a5d YR |
8822 | |
8823 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
8824 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); |
8825 | bnx2x_cl45_read(bp, phy, | |
8826 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); | |
8827 | bnx2x_cl45_read(bp, phy, | |
8828 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
8829 | bnx2x_cl45_read(bp, phy, | |
8830 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
62b29a5d | 8831 | |
de6eae1f YR |
8832 | DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" |
8833 | " link_status 0x%x\n", rx_sd, pcs_status, val2); | |
8f73f0b9 | 8834 | /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status |
2cf7acf9 | 8835 | * are set, or if the autoneg bit 1 is set |
de6eae1f YR |
8836 | */ |
8837 | link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); | |
8838 | if (link_up) { | |
8839 | if (val2 & (1<<1)) | |
8840 | vars->line_speed = SPEED_1000; | |
8841 | else | |
8842 | vars->line_speed = SPEED_10000; | |
62b29a5d | 8843 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
791f18c0 | 8844 | vars->duplex = DUPLEX_FULL; |
de6eae1f | 8845 | } |
c688fe2f YR |
8846 | |
8847 | /* Capture 10G link fault. Read twice to clear stale value. */ | |
8848 | if (vars->line_speed == SPEED_10000) { | |
8849 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 8850 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f | 8851 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
60d2fe03 | 8852 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
8853 | if (val1 & (1<<0)) |
8854 | vars->fault_detected = 1; | |
8855 | } | |
8856 | ||
62b29a5d | 8857 | return link_up; |
b7737c9b | 8858 | } |
62b29a5d | 8859 | |
de6eae1f YR |
8860 | /******************************************************************/ |
8861 | /* BCM8706 PHY SECTION */ | |
8862 | /******************************************************************/ | |
8863 | static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, | |
b7737c9b YR |
8864 | struct link_params *params, |
8865 | struct link_vars *vars) | |
8866 | { | |
a8db5b4c YR |
8867 | u32 tx_en_mode; |
8868 | u16 cnt, val, tmp1; | |
b7737c9b | 8869 | struct bnx2x *bp = params->bp; |
3deb8167 | 8870 | |
de6eae1f | 8871 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee | 8872 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
8873 | /* HW reset */ |
8874 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
8875 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
6d870c39 | 8876 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 8877 | |
de6eae1f YR |
8878 | /* Wait until fw is loaded */ |
8879 | for (cnt = 0; cnt < 100; cnt++) { | |
8880 | bnx2x_cl45_read(bp, phy, | |
8881 | MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); | |
8882 | if (val) | |
8883 | break; | |
d231023e | 8884 | usleep_range(10000, 20000); |
de6eae1f YR |
8885 | } |
8886 | DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); | |
8887 | if ((params->feature_config_flags & | |
8888 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
8889 | u8 i; | |
8890 | u16 reg; | |
8891 | for (i = 0; i < 4; i++) { | |
8892 | reg = MDIO_XS_8706_REG_BANK_RX0 + | |
8893 | i*(MDIO_XS_8706_REG_BANK_RX1 - | |
8894 | MDIO_XS_8706_REG_BANK_RX0); | |
8895 | bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); | |
8896 | /* Clear first 3 bits of the control */ | |
8897 | val &= ~0x7; | |
8898 | /* Set control bits according to configuration */ | |
8899 | val |= (phy->rx_preemphasis[i] & 0x7); | |
8900 | DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" | |
8901 | " reg 0x%x <-- val 0x%x\n", reg, val); | |
8902 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); | |
8903 | } | |
8904 | } | |
8905 | /* Force speed */ | |
8906 | if (phy->req_line_speed == SPEED_10000) { | |
8907 | DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); | |
ea4e040a | 8908 | |
de6eae1f YR |
8909 | bnx2x_cl45_write(bp, phy, |
8910 | MDIO_PMA_DEVAD, | |
8911 | MDIO_PMA_REG_DIGITAL_CTRL, 0x400); | |
8912 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8913 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, |
c688fe2f YR |
8914 | 0); |
8915 | /* Arm LASI for link and Tx fault. */ | |
8916 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8917 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); |
de6eae1f | 8918 | } else { |
25985edc | 8919 | /* Force 1Gbps using autoneg with 1G advertisement */ |
6bbca910 | 8920 | |
de6eae1f YR |
8921 | /* Allow CL37 through CL73 */ |
8922 | DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); | |
8923 | bnx2x_cl45_write(bp, phy, | |
8924 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
6bbca910 | 8925 | |
25985edc | 8926 | /* Enable Full-Duplex advertisement on CL37 */ |
de6eae1f YR |
8927 | bnx2x_cl45_write(bp, phy, |
8928 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); | |
8929 | /* Enable CL37 AN */ | |
8930 | bnx2x_cl45_write(bp, phy, | |
8931 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
8932 | /* 1G support */ | |
8933 | bnx2x_cl45_write(bp, phy, | |
8934 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); | |
6bbca910 | 8935 | |
de6eae1f YR |
8936 | /* Enable clause 73 AN */ |
8937 | bnx2x_cl45_write(bp, phy, | |
8938 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
8939 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8940 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
8941 | 0x0400); |
8942 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8943 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, |
de6eae1f YR |
8944 | 0x0004); |
8945 | } | |
8946 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
a8db5b4c | 8947 | |
8f73f0b9 | 8948 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low |
a8db5b4c YR |
8949 | * power mode, if TX Laser is disabled |
8950 | */ | |
8951 | ||
8952 | tx_en_mode = REG_RD(bp, params->shmem_base + | |
8953 | offsetof(struct shmem_region, | |
8954 | dev_info.port_hw_config[params->port].sfp_ctrl)) | |
8955 | & PORT_HW_CFG_TX_LASER_MASK; | |
8956 | ||
8957 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { | |
8958 | DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); | |
8959 | bnx2x_cl45_read(bp, phy, | |
8960 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); | |
8961 | tmp1 |= 0x1; | |
8962 | bnx2x_cl45_write(bp, phy, | |
8963 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); | |
8964 | } | |
8965 | ||
de6eae1f YR |
8966 | return 0; |
8967 | } | |
ea4e040a | 8968 | |
fcf5b650 YR |
8969 | static int bnx2x_8706_read_status(struct bnx2x_phy *phy, |
8970 | struct link_params *params, | |
8971 | struct link_vars *vars) | |
de6eae1f YR |
8972 | { |
8973 | return bnx2x_8706_8726_read_status(phy, params, vars); | |
8974 | } | |
6bbca910 | 8975 | |
de6eae1f YR |
8976 | /******************************************************************/ |
8977 | /* BCM8726 PHY SECTION */ | |
8978 | /******************************************************************/ | |
8979 | static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, | |
8980 | struct link_params *params) | |
8981 | { | |
8982 | struct bnx2x *bp = params->bp; | |
8983 | DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); | |
8984 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); | |
8985 | } | |
62b29a5d | 8986 | |
de6eae1f YR |
8987 | static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, |
8988 | struct link_params *params) | |
8989 | { | |
8990 | struct bnx2x *bp = params->bp; | |
8991 | /* Need to wait 100ms after reset */ | |
8992 | msleep(100); | |
62b29a5d | 8993 | |
de6eae1f YR |
8994 | /* Micro controller re-boot */ |
8995 | bnx2x_cl45_write(bp, phy, | |
8996 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); | |
62b29a5d | 8997 | |
de6eae1f YR |
8998 | /* Set soft reset */ |
8999 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
9000 | MDIO_PMA_DEVAD, |
9001 | MDIO_PMA_REG_GEN_CTRL, | |
9002 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
62b29a5d | 9003 | |
de6eae1f | 9004 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
9005 | MDIO_PMA_DEVAD, |
9006 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
6bbca910 | 9007 | |
de6eae1f | 9008 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
9009 | MDIO_PMA_DEVAD, |
9010 | MDIO_PMA_REG_GEN_CTRL, | |
9011 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
de6eae1f | 9012 | |
d231023e | 9013 | /* Wait for 150ms for microcode load */ |
de6eae1f YR |
9014 | msleep(150); |
9015 | ||
9016 | /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ | |
9017 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
9018 | MDIO_PMA_DEVAD, |
9019 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
de6eae1f YR |
9020 | |
9021 | msleep(200); | |
9022 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
b7737c9b YR |
9023 | } |
9024 | ||
de6eae1f | 9025 | static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
9026 | struct link_params *params, |
9027 | struct link_vars *vars) | |
9028 | { | |
9029 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
9030 | u16 val1; |
9031 | u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); | |
62b29a5d YR |
9032 | if (link_up) { |
9033 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
9034 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, |
9035 | &val1); | |
9036 | if (val1 & (1<<15)) { | |
9037 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); | |
9038 | link_up = 0; | |
9039 | vars->line_speed = 0; | |
9040 | } | |
62b29a5d YR |
9041 | } |
9042 | return link_up; | |
b7737c9b YR |
9043 | } |
9044 | ||
de6eae1f | 9045 | |
fcf5b650 YR |
9046 | static int bnx2x_8726_config_init(struct bnx2x_phy *phy, |
9047 | struct link_params *params, | |
9048 | struct link_vars *vars) | |
b7737c9b YR |
9049 | { |
9050 | struct bnx2x *bp = params->bp; | |
de6eae1f | 9051 | DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); |
62b29a5d | 9052 | |
de6eae1f | 9053 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
6d870c39 | 9054 | bnx2x_wait_reset_complete(bp, phy, params); |
62b29a5d | 9055 | |
de6eae1f | 9056 | bnx2x_8726_external_rom_boot(phy, params); |
62b29a5d | 9057 | |
8f73f0b9 | 9058 | /* Need to call module detected on initialization since the module |
2cf7acf9 YR |
9059 | * detection triggered by actual module insertion might occur before |
9060 | * driver is loaded, and when driver is loaded, it reset all | |
9061 | * registers, including the transmitter | |
9062 | */ | |
de6eae1f | 9063 | bnx2x_sfp_module_detection(phy, params); |
62b29a5d | 9064 | |
de6eae1f YR |
9065 | if (phy->req_line_speed == SPEED_1000) { |
9066 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
9067 | bnx2x_cl45_write(bp, phy, | |
9068 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
9069 | bnx2x_cl45_write(bp, phy, | |
9070 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
9071 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 9072 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); |
de6eae1f | 9073 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 9074 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
9075 | 0x400); |
9076 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && | |
9077 | (phy->speed_cap_mask & | |
9078 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && | |
9079 | ((phy->speed_cap_mask & | |
9080 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
9081 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
9082 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
9083 | /* Set Flow control */ | |
9084 | bnx2x_ext_phy_set_pause(params, phy, vars); | |
9085 | bnx2x_cl45_write(bp, phy, | |
9086 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); | |
9087 | bnx2x_cl45_write(bp, phy, | |
9088 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
9089 | bnx2x_cl45_write(bp, phy, | |
9090 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); | |
9091 | bnx2x_cl45_write(bp, phy, | |
9092 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
9093 | bnx2x_cl45_write(bp, phy, | |
9094 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
8f73f0b9 | 9095 | /* Enable RX-ALARM control to receive interrupt for 1G speed |
2cf7acf9 YR |
9096 | * change |
9097 | */ | |
de6eae1f | 9098 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 9099 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); |
de6eae1f | 9100 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 9101 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f | 9102 | 0x400); |
62b29a5d | 9103 | |
de6eae1f YR |
9104 | } else { /* Default 10G. Set only LASI control */ |
9105 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 9106 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); |
7aa0711f YR |
9107 | } |
9108 | ||
de6eae1f YR |
9109 | /* Set TX PreEmphasis if needed */ |
9110 | if ((params->feature_config_flags & | |
9111 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
94f05b0f JP |
9112 | DP(NETIF_MSG_LINK, |
9113 | "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", | |
de6eae1f YR |
9114 | phy->tx_preemphasis[0], |
9115 | phy->tx_preemphasis[1]); | |
9116 | bnx2x_cl45_write(bp, phy, | |
9117 | MDIO_PMA_DEVAD, | |
9118 | MDIO_PMA_REG_8726_TX_CTRL1, | |
9119 | phy->tx_preemphasis[0]); | |
c18aa15d | 9120 | |
de6eae1f YR |
9121 | bnx2x_cl45_write(bp, phy, |
9122 | MDIO_PMA_DEVAD, | |
9123 | MDIO_PMA_REG_8726_TX_CTRL2, | |
9124 | phy->tx_preemphasis[1]); | |
9125 | } | |
ab6ad5a4 | 9126 | |
de6eae1f | 9127 | return 0; |
ab6ad5a4 | 9128 | |
ea4e040a YR |
9129 | } |
9130 | ||
de6eae1f YR |
9131 | static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, |
9132 | struct link_params *params) | |
2f904460 | 9133 | { |
de6eae1f YR |
9134 | struct bnx2x *bp = params->bp; |
9135 | DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); | |
9136 | /* Set serial boot control for external load */ | |
9137 | bnx2x_cl45_write(bp, phy, | |
9138 | MDIO_PMA_DEVAD, | |
9139 | MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
9140 | } | |
9141 | ||
9142 | /******************************************************************/ | |
9143 | /* BCM8727 PHY SECTION */ | |
9144 | /******************************************************************/ | |
7f02c4ad YR |
9145 | |
9146 | static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, | |
9147 | struct link_params *params, u8 mode) | |
9148 | { | |
9149 | struct bnx2x *bp = params->bp; | |
9150 | u16 led_mode_bitmask = 0; | |
9151 | u16 gpio_pins_bitmask = 0; | |
9152 | u16 val; | |
9153 | /* Only NOC flavor requires to set the LED specifically */ | |
9154 | if (!(phy->flags & FLAGS_NOC)) | |
9155 | return; | |
9156 | switch (mode) { | |
9157 | case LED_MODE_FRONT_PANEL_OFF: | |
9158 | case LED_MODE_OFF: | |
9159 | led_mode_bitmask = 0; | |
9160 | gpio_pins_bitmask = 0x03; | |
9161 | break; | |
9162 | case LED_MODE_ON: | |
9163 | led_mode_bitmask = 0; | |
9164 | gpio_pins_bitmask = 0x02; | |
9165 | break; | |
9166 | case LED_MODE_OPER: | |
9167 | led_mode_bitmask = 0x60; | |
9168 | gpio_pins_bitmask = 0x11; | |
9169 | break; | |
9170 | } | |
9171 | bnx2x_cl45_read(bp, phy, | |
9172 | MDIO_PMA_DEVAD, | |
9173 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
9174 | &val); | |
9175 | val &= 0xff8f; | |
9176 | val |= led_mode_bitmask; | |
9177 | bnx2x_cl45_write(bp, phy, | |
9178 | MDIO_PMA_DEVAD, | |
9179 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
9180 | val); | |
9181 | bnx2x_cl45_read(bp, phy, | |
9182 | MDIO_PMA_DEVAD, | |
9183 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
9184 | &val); | |
9185 | val &= 0xffe0; | |
9186 | val |= gpio_pins_bitmask; | |
9187 | bnx2x_cl45_write(bp, phy, | |
9188 | MDIO_PMA_DEVAD, | |
9189 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
9190 | val); | |
9191 | } | |
de6eae1f YR |
9192 | static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, |
9193 | struct link_params *params) { | |
9194 | u32 swap_val, swap_override; | |
9195 | u8 port; | |
8f73f0b9 | 9196 | /* The PHY reset is controlled by GPIO 1. Fake the port number |
de6eae1f | 9197 | * to cancel the swap done in set_gpio() |
2f904460 | 9198 | */ |
de6eae1f YR |
9199 | struct bnx2x *bp = params->bp; |
9200 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
9201 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
9202 | port = (swap_val && swap_override) ^ 1; | |
9203 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 9204 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
2f904460 | 9205 | } |
e10bc84d | 9206 | |
dbef807e YM |
9207 | static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, |
9208 | struct link_params *params) | |
9209 | { | |
9210 | struct bnx2x *bp = params->bp; | |
9211 | u16 tmp1, val; | |
9212 | /* Set option 1G speed */ | |
9213 | if ((phy->req_line_speed == SPEED_1000) || | |
9214 | (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { | |
9215 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
9216 | bnx2x_cl45_write(bp, phy, | |
9217 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
9218 | bnx2x_cl45_write(bp, phy, | |
9219 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
9220 | bnx2x_cl45_read(bp, phy, | |
9221 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); | |
9222 | DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); | |
9223 | /* Power down the XAUI until link is up in case of dual-media | |
9224 | * and 1G | |
9225 | */ | |
9226 | if (DUAL_MEDIA(params)) { | |
9227 | bnx2x_cl45_read(bp, phy, | |
9228 | MDIO_PMA_DEVAD, | |
9229 | MDIO_PMA_REG_8727_PCS_GP, &val); | |
9230 | val |= (3<<10); | |
9231 | bnx2x_cl45_write(bp, phy, | |
9232 | MDIO_PMA_DEVAD, | |
9233 | MDIO_PMA_REG_8727_PCS_GP, val); | |
9234 | } | |
9235 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && | |
9236 | ((phy->speed_cap_mask & | |
9237 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && | |
9238 | ((phy->speed_cap_mask & | |
9239 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
9240 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
9241 | ||
9242 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
9243 | bnx2x_cl45_write(bp, phy, | |
9244 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); | |
9245 | bnx2x_cl45_write(bp, phy, | |
9246 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); | |
9247 | } else { | |
9248 | /* Since the 8727 has only single reset pin, need to set the 10G | |
9249 | * registers although it is default | |
9250 | */ | |
9251 | bnx2x_cl45_write(bp, phy, | |
9252 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, | |
9253 | 0x0020); | |
9254 | bnx2x_cl45_write(bp, phy, | |
9255 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); | |
9256 | bnx2x_cl45_write(bp, phy, | |
9257 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
9258 | bnx2x_cl45_write(bp, phy, | |
9259 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, | |
9260 | 0x0008); | |
9261 | } | |
9262 | } | |
9263 | ||
fcf5b650 YR |
9264 | static int bnx2x_8727_config_init(struct bnx2x_phy *phy, |
9265 | struct link_params *params, | |
9266 | struct link_vars *vars) | |
ea4e040a | 9267 | { |
a8db5b4c | 9268 | u32 tx_en_mode; |
5c107fda | 9269 | u16 tmp1, mod_abs, tmp2; |
ea4e040a | 9270 | struct bnx2x *bp = params->bp; |
de6eae1f | 9271 | /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ |
ea4e040a | 9272 | |
6d870c39 | 9273 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 9274 | |
de6eae1f | 9275 | DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); |
ea4e040a | 9276 | |
5c107fda | 9277 | bnx2x_8727_specific_func(phy, params, PHY_INIT); |
8f73f0b9 | 9278 | /* Initially configure MOD_ABS to interrupt when module is |
2cf7acf9 YR |
9279 | * presence( bit 8) |
9280 | */ | |
de6eae1f YR |
9281 | bnx2x_cl45_read(bp, phy, |
9282 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
8f73f0b9 | 9283 | /* Set EDC off by setting OPTXLOS signal input to low (bit 9). |
2cf7acf9 YR |
9284 | * When the EDC is off it locks onto a reference clock and avoids |
9285 | * becoming 'lost' | |
9286 | */ | |
7f02c4ad YR |
9287 | mod_abs &= ~(1<<8); |
9288 | if (!(phy->flags & FLAGS_NOC)) | |
9289 | mod_abs &= ~(1<<9); | |
de6eae1f YR |
9290 | bnx2x_cl45_write(bp, phy, |
9291 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9292 | |
85242eea YR |
9293 | /* Enable/Disable PHY transmitter output */ |
9294 | bnx2x_set_disable_pmd_transmit(params, phy, 0); | |
9295 | ||
de6eae1f YR |
9296 | bnx2x_8727_power_module(bp, phy, 1); |
9297 | ||
9298 | bnx2x_cl45_read(bp, phy, | |
9299 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); | |
9300 | ||
9301 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 9302 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); |
de6eae1f | 9303 | |
dbef807e | 9304 | bnx2x_8727_config_speed(phy, params); |
5c107fda | 9305 | |
b7737c9b | 9306 | |
de6eae1f YR |
9307 | /* Set TX PreEmphasis if needed */ |
9308 | if ((params->feature_config_flags & | |
9309 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
9310 | DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", | |
9311 | phy->tx_preemphasis[0], | |
9312 | phy->tx_preemphasis[1]); | |
9313 | bnx2x_cl45_write(bp, phy, | |
9314 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, | |
9315 | phy->tx_preemphasis[0]); | |
ea4e040a | 9316 | |
de6eae1f YR |
9317 | bnx2x_cl45_write(bp, phy, |
9318 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, | |
9319 | phy->tx_preemphasis[1]); | |
9320 | } | |
ea4e040a | 9321 | |
8f73f0b9 | 9322 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low |
a8db5b4c YR |
9323 | * power mode, if TX Laser is disabled |
9324 | */ | |
9325 | tx_en_mode = REG_RD(bp, params->shmem_base + | |
9326 | offsetof(struct shmem_region, | |
9327 | dev_info.port_hw_config[params->port].sfp_ctrl)) | |
9328 | & PORT_HW_CFG_TX_LASER_MASK; | |
9329 | ||
9330 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { | |
9331 | ||
9332 | DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); | |
9333 | bnx2x_cl45_read(bp, phy, | |
9334 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); | |
9335 | tmp2 |= 0x1000; | |
9336 | tmp2 &= 0xFFEF; | |
9337 | bnx2x_cl45_write(bp, phy, | |
9338 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); | |
59a2e53b YR |
9339 | bnx2x_cl45_read(bp, phy, |
9340 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, | |
9341 | &tmp2); | |
9342 | bnx2x_cl45_write(bp, phy, | |
9343 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, | |
9344 | (tmp2 & 0x7fff)); | |
a8db5b4c YR |
9345 | } |
9346 | ||
de6eae1f | 9347 | return 0; |
ea4e040a YR |
9348 | } |
9349 | ||
de6eae1f YR |
9350 | static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, |
9351 | struct link_params *params) | |
ea4e040a | 9352 | { |
ea4e040a | 9353 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
9354 | u16 mod_abs, rx_alarm_status; |
9355 | u32 val = REG_RD(bp, params->shmem_base + | |
9356 | offsetof(struct shmem_region, dev_info. | |
9357 | port_feature_config[params->port]. | |
9358 | config)); | |
9359 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
9360 | MDIO_PMA_DEVAD, |
9361 | MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
de6eae1f | 9362 | if (mod_abs & (1<<8)) { |
ea4e040a | 9363 | |
de6eae1f | 9364 | /* Module is absent */ |
94f05b0f JP |
9365 | DP(NETIF_MSG_LINK, |
9366 | "MOD_ABS indication show module is absent\n"); | |
1ac9e428 | 9367 | phy->media_type = ETH_PHY_NOT_PRESENT; |
8f73f0b9 | 9368 | /* 1. Set mod_abs to detect next module |
2cf7acf9 YR |
9369 | * presence event |
9370 | * 2. Set EDC off by setting OPTXLOS signal input to low | |
9371 | * (bit 9). | |
9372 | * When the EDC is off it locks onto a reference clock and | |
9373 | * avoids becoming 'lost'. | |
9374 | */ | |
7f02c4ad YR |
9375 | mod_abs &= ~(1<<8); |
9376 | if (!(phy->flags & FLAGS_NOC)) | |
9377 | mod_abs &= ~(1<<9); | |
de6eae1f | 9378 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
9379 | MDIO_PMA_DEVAD, |
9380 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9381 | |
8f73f0b9 | 9382 | /* Clear RX alarm since it stays up as long as |
2cf7acf9 YR |
9383 | * the mod_abs wasn't changed |
9384 | */ | |
de6eae1f | 9385 | bnx2x_cl45_read(bp, phy, |
cd88ccee | 9386 | MDIO_PMA_DEVAD, |
60d2fe03 | 9387 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
ea4e040a | 9388 | |
de6eae1f YR |
9389 | } else { |
9390 | /* Module is present */ | |
94f05b0f JP |
9391 | DP(NETIF_MSG_LINK, |
9392 | "MOD_ABS indication show module is present\n"); | |
8f73f0b9 | 9393 | /* First disable transmitter, and if the module is ok, the |
2cf7acf9 YR |
9394 | * module_detection will enable it |
9395 | * 1. Set mod_abs to detect next module absent event ( bit 8) | |
9396 | * 2. Restore the default polarity of the OPRXLOS signal and | |
9397 | * this signal will then correctly indicate the presence or | |
9398 | * absence of the Rx signal. (bit 9) | |
9399 | */ | |
7f02c4ad YR |
9400 | mod_abs |= (1<<8); |
9401 | if (!(phy->flags & FLAGS_NOC)) | |
9402 | mod_abs |= (1<<9); | |
e10bc84d | 9403 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
9404 | MDIO_PMA_DEVAD, |
9405 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9406 | |
8f73f0b9 | 9407 | /* Clear RX alarm since it stays up as long as the mod_abs |
2cf7acf9 YR |
9408 | * wasn't changed. This is need to be done before calling the |
9409 | * module detection, otherwise it will clear* the link update | |
9410 | * alarm | |
9411 | */ | |
de6eae1f YR |
9412 | bnx2x_cl45_read(bp, phy, |
9413 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9414 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
ea4e040a | 9415 | |
ea4e040a | 9416 | |
de6eae1f YR |
9417 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
9418 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
a8db5b4c | 9419 | bnx2x_sfp_set_transmitter(params, phy, 0); |
de6eae1f YR |
9420 | |
9421 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) | |
9422 | bnx2x_sfp_module_detection(phy, params); | |
9423 | else | |
9424 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); | |
dbef807e YM |
9425 | |
9426 | /* Reconfigure link speed based on module type limitations */ | |
9427 | bnx2x_8727_config_speed(phy, params); | |
ea4e040a | 9428 | } |
de6eae1f YR |
9429 | |
9430 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", | |
2cf7acf9 YR |
9431 | rx_alarm_status); |
9432 | /* No need to check link status in case of module plugged in/out */ | |
ea4e040a YR |
9433 | } |
9434 | ||
de6eae1f YR |
9435 | static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, |
9436 | struct link_params *params, | |
9437 | struct link_vars *vars) | |
9438 | ||
ea4e040a YR |
9439 | { |
9440 | struct bnx2x *bp = params->bp; | |
27d02432 | 9441 | u8 link_up = 0, oc_port = params->port; |
de6eae1f | 9442 | u16 link_status = 0; |
a22f0788 YR |
9443 | u16 rx_alarm_status, lasi_ctrl, val1; |
9444 | ||
9445 | /* If PHY is not initialized, do not check link status */ | |
9446 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 9447 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, |
a22f0788 YR |
9448 | &lasi_ctrl); |
9449 | if (!lasi_ctrl) | |
9450 | return 0; | |
9451 | ||
9045f6b4 | 9452 | /* Check the LASI on Rx */ |
de6eae1f | 9453 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 9454 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, |
de6eae1f YR |
9455 | &rx_alarm_status); |
9456 | vars->line_speed = 0; | |
9457 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); | |
9458 | ||
60d2fe03 YR |
9459 | bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, |
9460 | MDIO_PMA_LASI_TXCTRL); | |
c688fe2f | 9461 | |
de6eae1f | 9462 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 9463 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f YR |
9464 | |
9465 | DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); | |
9466 | ||
9467 | /* Clear MSG-OUT */ | |
9468 | bnx2x_cl45_read(bp, phy, | |
9469 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
9470 | ||
8f73f0b9 | 9471 | /* If a module is present and there is need to check |
de6eae1f YR |
9472 | * for over current |
9473 | */ | |
9474 | if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { | |
9475 | /* Check over-current using 8727 GPIO0 input*/ | |
9476 | bnx2x_cl45_read(bp, phy, | |
9477 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, | |
9478 | &val1); | |
9479 | ||
9480 | if ((val1 & (1<<8)) == 0) { | |
27d02432 YR |
9481 | if (!CHIP_IS_E1x(bp)) |
9482 | oc_port = BP_PATH(bp) + (params->port << 1); | |
94f05b0f JP |
9483 | DP(NETIF_MSG_LINK, |
9484 | "8727 Power fault has been detected on port %d\n", | |
9485 | oc_port); | |
2f751a80 YR |
9486 | netdev_err(bp->dev, "Error: Power fault on Port %d has " |
9487 | "been detected and the power to " | |
9488 | "that SFP+ module has been removed " | |
9489 | "to prevent failure of the card. " | |
9490 | "Please remove the SFP+ module and " | |
9491 | "restart the system to clear this " | |
9492 | "error.\n", | |
27d02432 | 9493 | oc_port); |
2cf7acf9 | 9494 | /* Disable all RX_ALARMs except for mod_abs */ |
de6eae1f YR |
9495 | bnx2x_cl45_write(bp, phy, |
9496 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9497 | MDIO_PMA_LASI_RXCTRL, (1<<5)); |
de6eae1f YR |
9498 | |
9499 | bnx2x_cl45_read(bp, phy, | |
9500 | MDIO_PMA_DEVAD, | |
9501 | MDIO_PMA_REG_PHY_IDENTIFIER, &val1); | |
9502 | /* Wait for module_absent_event */ | |
9503 | val1 |= (1<<8); | |
9504 | bnx2x_cl45_write(bp, phy, | |
9505 | MDIO_PMA_DEVAD, | |
9506 | MDIO_PMA_REG_PHY_IDENTIFIER, val1); | |
9507 | /* Clear RX alarm */ | |
9508 | bnx2x_cl45_read(bp, phy, | |
9509 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9510 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
5a1fbf40 | 9511 | bnx2x_8727_power_module(params->bp, phy, 0); |
de6eae1f YR |
9512 | return 0; |
9513 | } | |
9514 | } /* Over current check */ | |
9515 | ||
9516 | /* When module absent bit is set, check module */ | |
9517 | if (rx_alarm_status & (1<<5)) { | |
9518 | bnx2x_8727_handle_mod_abs(phy, params); | |
9519 | /* Enable all mod_abs and link detection bits */ | |
9520 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 9521 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
9522 | ((1<<5) | (1<<2))); |
9523 | } | |
59a2e53b YR |
9524 | |
9525 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { | |
9526 | DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); | |
9527 | bnx2x_sfp_set_transmitter(params, phy, 1); | |
9528 | } else { | |
de6eae1f YR |
9529 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); |
9530 | return 0; | |
9531 | } | |
9532 | ||
9533 | bnx2x_cl45_read(bp, phy, | |
9534 | MDIO_PMA_DEVAD, | |
9535 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); | |
9536 | ||
8f73f0b9 | 9537 | /* Bits 0..2 --> speed detected, |
2cf7acf9 YR |
9538 | * Bits 13..15--> link is down |
9539 | */ | |
de6eae1f YR |
9540 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { |
9541 | link_up = 1; | |
9542 | vars->line_speed = SPEED_10000; | |
2cf7acf9 YR |
9543 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", |
9544 | params->port); | |
de6eae1f YR |
9545 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { |
9546 | link_up = 1; | |
9547 | vars->line_speed = SPEED_1000; | |
9548 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
9549 | params->port); | |
9550 | } else { | |
9551 | link_up = 0; | |
9552 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
9553 | params->port); | |
9554 | } | |
c688fe2f YR |
9555 | |
9556 | /* Capture 10G link fault. */ | |
9557 | if (vars->line_speed == SPEED_10000) { | |
9558 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 9559 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
9560 | |
9561 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 9562 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
9563 | |
9564 | if (val1 & (1<<0)) { | |
9565 | vars->fault_detected = 1; | |
9566 | } | |
9567 | } | |
9568 | ||
791f18c0 | 9569 | if (link_up) { |
de6eae1f | 9570 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
791f18c0 YR |
9571 | vars->duplex = DUPLEX_FULL; |
9572 | DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); | |
9573 | } | |
a22f0788 YR |
9574 | |
9575 | if ((DUAL_MEDIA(params)) && | |
9576 | (phy->req_line_speed == SPEED_1000)) { | |
9577 | bnx2x_cl45_read(bp, phy, | |
9578 | MDIO_PMA_DEVAD, | |
9579 | MDIO_PMA_REG_8727_PCS_GP, &val1); | |
8f73f0b9 | 9580 | /* In case of dual-media board and 1G, power up the XAUI side, |
a22f0788 YR |
9581 | * otherwise power it down. For 10G it is done automatically |
9582 | */ | |
9583 | if (link_up) | |
9584 | val1 &= ~(3<<10); | |
9585 | else | |
9586 | val1 |= (3<<10); | |
9587 | bnx2x_cl45_write(bp, phy, | |
9588 | MDIO_PMA_DEVAD, | |
9589 | MDIO_PMA_REG_8727_PCS_GP, val1); | |
9590 | } | |
de6eae1f | 9591 | return link_up; |
b7737c9b | 9592 | } |
ea4e040a | 9593 | |
de6eae1f YR |
9594 | static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, |
9595 | struct link_params *params) | |
b7737c9b YR |
9596 | { |
9597 | struct bnx2x *bp = params->bp; | |
85242eea YR |
9598 | |
9599 | /* Enable/Disable PHY transmitter output */ | |
9600 | bnx2x_set_disable_pmd_transmit(params, phy, 1); | |
9601 | ||
de6eae1f | 9602 | /* Disable Transmitter */ |
a8db5b4c | 9603 | bnx2x_sfp_set_transmitter(params, phy, 0); |
a22f0788 | 9604 | /* Clear LASI */ |
60d2fe03 | 9605 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); |
a22f0788 | 9606 | |
ea4e040a | 9607 | } |
c18aa15d | 9608 | |
de6eae1f YR |
9609 | /******************************************************************/ |
9610 | /* BCM8481/BCM84823/BCM84833 PHY SECTION */ | |
9611 | /******************************************************************/ | |
9612 | static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |
11b2ec6b YR |
9613 | struct bnx2x *bp, |
9614 | u8 port) | |
ea4e040a | 9615 | { |
503976e9 YR |
9616 | u16 val, fw_ver2, cnt, i; |
9617 | static struct bnx2x_reg_set reg_set[] = { | |
9618 | {MDIO_PMA_DEVAD, 0xA819, 0x0014}, | |
9619 | {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, | |
9620 | {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, | |
9621 | {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, | |
9622 | {MDIO_PMA_DEVAD, 0xA817, 0x0009} | |
9623 | }; | |
9624 | u16 fw_ver1; | |
ea4e040a | 9625 | |
0f6bb03d YR |
9626 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
9627 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { | |
11b2ec6b | 9628 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); |
8267bbb0 | 9629 | bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, |
11b2ec6b YR |
9630 | phy->ver_addr); |
9631 | } else { | |
9632 | /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ | |
9633 | /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ | |
05fcaeac | 9634 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
503976e9 YR |
9635 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, |
9636 | reg_set[i].reg, reg_set[i].val); | |
11b2ec6b YR |
9637 | |
9638 | for (cnt = 0; cnt < 100; cnt++) { | |
9639 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
9640 | if (val & 1) | |
9641 | break; | |
9642 | udelay(5); | |
9643 | } | |
9644 | if (cnt == 100) { | |
9645 | DP(NETIF_MSG_LINK, "Unable to read 848xx " | |
9646 | "phy fw version(1)\n"); | |
9647 | bnx2x_save_spirom_version(bp, port, 0, | |
9648 | phy->ver_addr); | |
9649 | return; | |
9650 | } | |
c87bca1e | 9651 | |
ea4e040a | 9652 | |
11b2ec6b YR |
9653 | /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ |
9654 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); | |
9655 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
9656 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); | |
9657 | for (cnt = 0; cnt < 100; cnt++) { | |
9658 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
9659 | if (val & 1) | |
9660 | break; | |
9661 | udelay(5); | |
9662 | } | |
9663 | if (cnt == 100) { | |
9664 | DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " | |
9665 | "version(2)\n"); | |
9666 | bnx2x_save_spirom_version(bp, port, 0, | |
9667 | phy->ver_addr); | |
9668 | return; | |
9669 | } | |
ea4e040a | 9670 | |
11b2ec6b YR |
9671 | /* lower 16 bits of the register SPI_FW_STATUS */ |
9672 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); | |
9673 | /* upper 16 bits of register SPI_FW_STATUS */ | |
9674 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); | |
ea4e040a | 9675 | |
11b2ec6b | 9676 | bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, |
de6eae1f | 9677 | phy->ver_addr); |
ea4e040a YR |
9678 | } |
9679 | ||
de6eae1f | 9680 | } |
de6eae1f YR |
9681 | static void bnx2x_848xx_set_led(struct bnx2x *bp, |
9682 | struct bnx2x_phy *phy) | |
ea4e040a | 9683 | { |
503976e9 YR |
9684 | u16 val, offset, i; |
9685 | static struct bnx2x_reg_set reg_set[] = { | |
9686 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, | |
9687 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, | |
9688 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, | |
9689 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, | |
9690 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, | |
9691 | MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, | |
9692 | {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} | |
9693 | }; | |
de6eae1f YR |
9694 | /* PHYC_CTL_LED_CTL */ |
9695 | bnx2x_cl45_read(bp, phy, | |
9696 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9697 | MDIO_PMA_REG_8481_LINK_SIGNAL, &val); |
de6eae1f YR |
9698 | val &= 0xFE00; |
9699 | val |= 0x0092; | |
345b5d52 | 9700 | |
de6eae1f YR |
9701 | bnx2x_cl45_write(bp, phy, |
9702 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9703 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); |
ea4e040a | 9704 | |
b5a05550 | 9705 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
503976e9 YR |
9706 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
9707 | reg_set[i].val); | |
f25b3c8b | 9708 | |
0f6bb03d YR |
9709 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
9710 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) | |
521683da YR |
9711 | offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; |
9712 | else | |
9713 | offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; | |
9714 | ||
503976e9 YR |
9715 | /* stretch_en for LED3*/ |
9716 | bnx2x_cl45_read_or_write(bp, phy, | |
9717 | MDIO_PMA_DEVAD, offset, | |
9718 | MDIO_PMA_REG_84823_LED3_STRETCH_EN); | |
ea4e040a YR |
9719 | } |
9720 | ||
5c107fda YR |
9721 | static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, |
9722 | struct link_params *params, | |
9723 | u32 action) | |
9724 | { | |
9725 | struct bnx2x *bp = params->bp; | |
9726 | switch (action) { | |
9727 | case PHY_INIT: | |
0f6bb03d YR |
9728 | if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
9729 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { | |
5c107fda YR |
9730 | /* Save spirom version */ |
9731 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); | |
9732 | } | |
9733 | /* This phy uses the NIG latch mechanism since link indication | |
9734 | * arrives through its LED4 and not via its LASI signal, so we | |
9735 | * get steady signal instead of clear on read | |
9736 | */ | |
9737 | bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, | |
9738 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
9739 | ||
9740 | bnx2x_848xx_set_led(bp, phy); | |
9741 | break; | |
9742 | } | |
9743 | } | |
9744 | ||
fcf5b650 YR |
9745 | static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, |
9746 | struct link_params *params, | |
9747 | struct link_vars *vars) | |
ea4e040a | 9748 | { |
c18aa15d | 9749 | struct bnx2x *bp = params->bp; |
503976e9 | 9750 | u16 autoneg_val, an_1000_val, an_10_100_val; |
bac27bd9 | 9751 | |
5c107fda | 9752 | bnx2x_848xx_specific_func(phy, params, PHY_INIT); |
de6eae1f YR |
9753 | bnx2x_cl45_write(bp, phy, |
9754 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); | |
ea4e040a | 9755 | |
de6eae1f YR |
9756 | /* set 1000 speed advertisement */ |
9757 | bnx2x_cl45_read(bp, phy, | |
9758 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
9759 | &an_1000_val); | |
57963ed9 | 9760 | |
de6eae1f YR |
9761 | bnx2x_ext_phy_set_pause(params, phy, vars); |
9762 | bnx2x_cl45_read(bp, phy, | |
9763 | MDIO_AN_DEVAD, | |
9764 | MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
9765 | &an_10_100_val); | |
9766 | bnx2x_cl45_read(bp, phy, | |
9767 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
9768 | &autoneg_val); | |
9769 | /* Disable forced speed */ | |
9770 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); | |
9771 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); | |
ea4e040a | 9772 | |
de6eae1f YR |
9773 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
9774 | (phy->speed_cap_mask & | |
9775 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
9776 | (phy->req_line_speed == SPEED_1000)) { | |
9777 | an_1000_val |= (1<<8); | |
9778 | autoneg_val |= (1<<9 | 1<<12); | |
9779 | if (phy->req_duplex == DUPLEX_FULL) | |
9780 | an_1000_val |= (1<<9); | |
9781 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); | |
9782 | } else | |
9783 | an_1000_val &= ~((1<<8) | (1<<9)); | |
ea4e040a | 9784 | |
de6eae1f YR |
9785 | bnx2x_cl45_write(bp, phy, |
9786 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
9787 | an_1000_val); | |
ea4e040a | 9788 | |
343f7dc4 YR |
9789 | /* Set 10/100 speed advertisement */ |
9790 | if (phy->req_line_speed == SPEED_AUTO_NEG) { | |
9791 | if (phy->speed_cap_mask & | |
9792 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { | |
9793 | /* Enable autoneg and restart autoneg for legacy speeds | |
9794 | */ | |
9795 | autoneg_val |= (1<<9 | 1<<12); | |
de6eae1f | 9796 | an_10_100_val |= (1<<8); |
343f7dc4 YR |
9797 | DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); |
9798 | } | |
9799 | ||
9800 | if (phy->speed_cap_mask & | |
9801 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { | |
9802 | /* Enable autoneg and restart autoneg for legacy speeds | |
9803 | */ | |
9804 | autoneg_val |= (1<<9 | 1<<12); | |
9805 | an_10_100_val |= (1<<7); | |
9806 | DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); | |
9807 | } | |
9808 | ||
9809 | if ((phy->speed_cap_mask & | |
9810 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && | |
9811 | (phy->supported & SUPPORTED_10baseT_Full)) { | |
de6eae1f | 9812 | an_10_100_val |= (1<<6); |
343f7dc4 YR |
9813 | autoneg_val |= (1<<9 | 1<<12); |
9814 | DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); | |
9815 | } | |
9816 | ||
9817 | if ((phy->speed_cap_mask & | |
9818 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && | |
9819 | (phy->supported & SUPPORTED_10baseT_Half)) { | |
9820 | an_10_100_val |= (1<<5); | |
9821 | autoneg_val |= (1<<9 | 1<<12); | |
9822 | DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); | |
9823 | } | |
de6eae1f | 9824 | } |
b7737c9b | 9825 | |
de6eae1f | 9826 | /* Only 10/100 are allowed to work in FORCE mode */ |
0520e63a YR |
9827 | if ((phy->req_line_speed == SPEED_100) && |
9828 | (phy->supported & | |
9829 | (SUPPORTED_100baseT_Half | | |
9830 | SUPPORTED_100baseT_Full))) { | |
de6eae1f YR |
9831 | autoneg_val |= (1<<13); |
9832 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
9833 | bnx2x_cl45_write(bp, phy, | |
9834 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
9835 | (1<<15 | 1<<9 | 7<<0)); | |
521683da YR |
9836 | /* The PHY needs this set even for forced link. */ |
9837 | an_10_100_val |= (1<<8) | (1<<7); | |
de6eae1f YR |
9838 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); |
9839 | } | |
0520e63a YR |
9840 | if ((phy->req_line_speed == SPEED_10) && |
9841 | (phy->supported & | |
9842 | (SUPPORTED_10baseT_Half | | |
9843 | SUPPORTED_10baseT_Full))) { | |
de6eae1f YR |
9844 | /* Enabled AUTO-MDIX when autoneg is disabled */ |
9845 | bnx2x_cl45_write(bp, phy, | |
9846 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
9847 | (1<<15 | 1<<9 | 7<<0)); | |
9848 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); | |
9849 | } | |
b7737c9b | 9850 | |
de6eae1f YR |
9851 | bnx2x_cl45_write(bp, phy, |
9852 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
9853 | an_10_100_val); | |
b7737c9b | 9854 | |
de6eae1f YR |
9855 | if (phy->req_duplex == DUPLEX_FULL) |
9856 | autoneg_val |= (1<<8); | |
b7737c9b | 9857 | |
0f6bb03d YR |
9858 | /* Always write this if this is not 84833/4. |
9859 | * For 84833/4, write it only when it's a forced speed. | |
fd38f73e | 9860 | */ |
0f6bb03d YR |
9861 | if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
9862 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || | |
503976e9 | 9863 | ((autoneg_val & (1<<12)) == 0)) |
fd38f73e | 9864 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
9865 | MDIO_AN_DEVAD, |
9866 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); | |
b7737c9b | 9867 | |
de6eae1f YR |
9868 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
9869 | (phy->speed_cap_mask & | |
9870 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
9871 | (phy->req_line_speed == SPEED_10000)) { | |
9045f6b4 YR |
9872 | DP(NETIF_MSG_LINK, "Advertising 10G\n"); |
9873 | /* Restart autoneg for 10G*/ | |
de6eae1f | 9874 | |
503976e9 YR |
9875 | bnx2x_cl45_read_or_write( |
9876 | bp, phy, | |
9877 | MDIO_AN_DEVAD, | |
9878 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9879 | 0x1000); | |
521683da YR |
9880 | bnx2x_cl45_write(bp, phy, |
9881 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, | |
9882 | 0x3200); | |
fd38f73e | 9883 | } else |
de6eae1f YR |
9884 | bnx2x_cl45_write(bp, phy, |
9885 | MDIO_AN_DEVAD, | |
9886 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9887 | 1); | |
fd38f73e | 9888 | |
de6eae1f | 9889 | return 0; |
b7737c9b YR |
9890 | } |
9891 | ||
fcf5b650 YR |
9892 | static int bnx2x_8481_config_init(struct bnx2x_phy *phy, |
9893 | struct link_params *params, | |
9894 | struct link_vars *vars) | |
ea4e040a YR |
9895 | { |
9896 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
9897 | /* Restore normal power mode*/ |
9898 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 9899 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
b7737c9b | 9900 | |
de6eae1f YR |
9901 | /* HW reset */ |
9902 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
6d870c39 | 9903 | bnx2x_wait_reset_complete(bp, phy, params); |
ab6ad5a4 | 9904 | |
de6eae1f YR |
9905 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
9906 | return bnx2x_848xx_cmn_config_init(phy, params, vars); | |
9907 | } | |
ea4e040a | 9908 | |
521683da YR |
9909 | #define PHY84833_CMDHDLR_WAIT 300 |
9910 | #define PHY84833_CMDHDLR_MAX_ARGS 5 | |
9911 | static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, | |
503976e9 YR |
9912 | struct link_params *params, u16 fw_cmd, |
9913 | u16 cmd_args[], int argc) | |
bac27bd9 | 9914 | { |
c8c60d88 | 9915 | int idx; |
bac27bd9 | 9916 | u16 val; |
bac27bd9 | 9917 | struct bnx2x *bp = params->bp; |
bac27bd9 YR |
9918 | /* Write CMD_OPEN_OVERRIDE to STATUS reg */ |
9919 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
521683da YR |
9920 | MDIO_84833_CMD_HDLR_STATUS, |
9921 | PHY84833_STATUS_CMD_OPEN_OVERRIDE); | |
9922 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { | |
bac27bd9 | 9923 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9924 | MDIO_84833_CMD_HDLR_STATUS, &val); |
9925 | if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) | |
bac27bd9 | 9926 | break; |
503976e9 | 9927 | usleep_range(1000, 2000); |
bac27bd9 | 9928 | } |
521683da YR |
9929 | if (idx >= PHY84833_CMDHDLR_WAIT) { |
9930 | DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); | |
bac27bd9 YR |
9931 | return -EINVAL; |
9932 | } | |
9933 | ||
521683da | 9934 | /* Prepare argument(s) and issue command */ |
c8c60d88 | 9935 | for (idx = 0; idx < argc; idx++) { |
521683da YR |
9936 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
9937 | MDIO_84833_CMD_HDLR_DATA1 + idx, | |
9938 | cmd_args[idx]); | |
9939 | } | |
bac27bd9 | 9940 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9941 | MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); |
9942 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { | |
bac27bd9 | 9943 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9944 | MDIO_84833_CMD_HDLR_STATUS, &val); |
9945 | if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || | |
9946 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) | |
bac27bd9 | 9947 | break; |
503976e9 | 9948 | usleep_range(1000, 2000); |
bac27bd9 | 9949 | } |
521683da YR |
9950 | if ((idx >= PHY84833_CMDHDLR_WAIT) || |
9951 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { | |
9952 | DP(NETIF_MSG_LINK, "FW cmd failed.\n"); | |
bac27bd9 YR |
9953 | return -EINVAL; |
9954 | } | |
521683da | 9955 | /* Gather returning data */ |
c8c60d88 | 9956 | for (idx = 0; idx < argc; idx++) { |
521683da YR |
9957 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
9958 | MDIO_84833_CMD_HDLR_DATA1 + idx, | |
9959 | &cmd_args[idx]); | |
9960 | } | |
bac27bd9 | 9961 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9962 | MDIO_84833_CMD_HDLR_STATUS, |
9963 | PHY84833_STATUS_CMD_CLEAR_COMPLETE); | |
bac27bd9 YR |
9964 | return 0; |
9965 | } | |
9966 | ||
521683da YR |
9967 | static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, |
9968 | struct link_params *params, | |
9969 | struct link_vars *vars) | |
9970 | { | |
9971 | u32 pair_swap; | |
9972 | u16 data[PHY84833_CMDHDLR_MAX_ARGS]; | |
9973 | int status; | |
9974 | struct bnx2x *bp = params->bp; | |
9975 | ||
9976 | /* Check for configuration. */ | |
9977 | pair_swap = REG_RD(bp, params->shmem_base + | |
9978 | offsetof(struct shmem_region, | |
9979 | dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & | |
9980 | PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; | |
9981 | ||
9982 | if (pair_swap == 0) | |
9983 | return 0; | |
9984 | ||
9985 | /* Only the second argument is used for this command */ | |
9986 | data[1] = (u16)pair_swap; | |
9987 | ||
9988 | status = bnx2x_84833_cmd_hdlr(phy, params, | |
c8c60d88 | 9989 | PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); |
521683da YR |
9990 | if (status == 0) |
9991 | DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); | |
9992 | ||
9993 | return status; | |
9994 | } | |
9995 | ||
985848f8 YR |
9996 | static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, |
9997 | u32 shmem_base_path[], | |
9998 | u32 chip_id) | |
0d40f0d4 YR |
9999 | { |
10000 | u32 reset_pin[2]; | |
10001 | u32 idx; | |
10002 | u8 reset_gpios; | |
10003 | if (CHIP_IS_E3(bp)) { | |
10004 | /* Assume that these will be GPIOs, not EPIOs. */ | |
10005 | for (idx = 0; idx < 2; idx++) { | |
10006 | /* Map config param to register bit. */ | |
10007 | reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + | |
10008 | offsetof(struct shmem_region, | |
10009 | dev_info.port_hw_config[0].e3_cmn_pin_cfg)); | |
10010 | reset_pin[idx] = (reset_pin[idx] & | |
10011 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10012 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10013 | reset_pin[idx] -= PIN_CFG_GPIO0_P0; | |
10014 | reset_pin[idx] = (1 << reset_pin[idx]); | |
10015 | } | |
10016 | reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); | |
10017 | } else { | |
10018 | /* E2, look from diff place of shmem. */ | |
10019 | for (idx = 0; idx < 2; idx++) { | |
10020 | reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + | |
10021 | offsetof(struct shmem_region, | |
10022 | dev_info.port_hw_config[0].default_cfg)); | |
10023 | reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; | |
10024 | reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; | |
10025 | reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; | |
10026 | reset_pin[idx] = (1 << reset_pin[idx]); | |
10027 | } | |
10028 | reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); | |
10029 | } | |
10030 | ||
985848f8 YR |
10031 | return reset_gpios; |
10032 | } | |
10033 | ||
10034 | static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, | |
10035 | struct link_params *params) | |
10036 | { | |
10037 | struct bnx2x *bp = params->bp; | |
10038 | u8 reset_gpios; | |
10039 | u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + | |
10040 | offsetof(struct shmem2_region, | |
10041 | other_shmem_base_addr)); | |
10042 | ||
10043 | u32 shmem_base_path[2]; | |
99bf7f34 YR |
10044 | |
10045 | /* Work around for 84833 LED failure inside RESET status */ | |
10046 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
10047 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
10048 | MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); | |
10049 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
10050 | MDIO_AN_REG_8481_1G_100T_EXT_CTRL, | |
10051 | MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); | |
10052 | ||
985848f8 YR |
10053 | shmem_base_path[0] = params->shmem_base; |
10054 | shmem_base_path[1] = other_shmem_base_addr; | |
10055 | ||
10056 | reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, | |
10057 | params->chip_id); | |
10058 | ||
10059 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); | |
10060 | udelay(10); | |
10061 | DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", | |
10062 | reset_gpios); | |
10063 | ||
10064 | return 0; | |
10065 | } | |
10066 | ||
c8c60d88 YM |
10067 | static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, |
10068 | struct link_params *params, | |
10069 | struct link_vars *vars) | |
10070 | { | |
10071 | int rc; | |
10072 | struct bnx2x *bp = params->bp; | |
10073 | u16 cmd_args = 0; | |
10074 | ||
10075 | DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); | |
10076 | ||
c8c60d88 YM |
10077 | /* Prevent Phy from working in EEE and advertising it */ |
10078 | rc = bnx2x_84833_cmd_hdlr(phy, params, | |
10079 | PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); | |
d231023e | 10080 | if (rc) { |
c8c60d88 YM |
10081 | DP(NETIF_MSG_LINK, "EEE disable failed.\n"); |
10082 | return rc; | |
10083 | } | |
10084 | ||
ec4010ec | 10085 | return bnx2x_eee_disable(phy, params, vars); |
c8c60d88 YM |
10086 | } |
10087 | ||
10088 | static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, | |
10089 | struct link_params *params, | |
10090 | struct link_vars *vars) | |
10091 | { | |
10092 | int rc; | |
10093 | struct bnx2x *bp = params->bp; | |
10094 | u16 cmd_args = 1; | |
10095 | ||
c8c60d88 YM |
10096 | rc = bnx2x_84833_cmd_hdlr(phy, params, |
10097 | PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); | |
d231023e | 10098 | if (rc) { |
c8c60d88 YM |
10099 | DP(NETIF_MSG_LINK, "EEE enable failed.\n"); |
10100 | return rc; | |
10101 | } | |
10102 | ||
ec4010ec | 10103 | return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); |
c8c60d88 YM |
10104 | } |
10105 | ||
a89a1d4a | 10106 | #define PHY84833_CONSTANT_LATENCY 1193 |
fcf5b650 YR |
10107 | static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, |
10108 | struct link_params *params, | |
10109 | struct link_vars *vars) | |
de6eae1f YR |
10110 | { |
10111 | struct bnx2x *bp = params->bp; | |
6a71bbe0 | 10112 | u8 port, initialize = 1; |
bac27bd9 | 10113 | u16 val; |
503976e9 | 10114 | u32 actual_phy_selection; |
521683da | 10115 | u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; |
fcf5b650 | 10116 | int rc = 0; |
7f02c4ad | 10117 | |
503976e9 | 10118 | usleep_range(1000, 2000); |
bac27bd9 | 10119 | |
5481388b | 10120 | if (!(CHIP_IS_E1x(bp))) |
6a71bbe0 YR |
10121 | port = BP_PATH(bp); |
10122 | else | |
10123 | port = params->port; | |
bac27bd9 YR |
10124 | |
10125 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
10126 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
10127 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, | |
10128 | port); | |
10129 | } else { | |
985848f8 | 10130 | /* MDIO reset */ |
bac27bd9 YR |
10131 | bnx2x_cl45_write(bp, phy, |
10132 | MDIO_PMA_DEVAD, | |
10133 | MDIO_PMA_REG_CTRL, 0x8000); | |
521683da YR |
10134 | } |
10135 | ||
10136 | bnx2x_wait_reset_complete(bp, phy, params); | |
10137 | ||
10138 | /* Wait for GPHY to come out of reset */ | |
10139 | msleep(50); | |
0f6bb03d YR |
10140 | if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
10141 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { | |
8f73f0b9 | 10142 | /* BCM84823 requires that XGXS links up first @ 10G for normal |
521683da YR |
10143 | * behavior. |
10144 | */ | |
10145 | u16 temp; | |
10146 | temp = vars->line_speed; | |
10147 | vars->line_speed = SPEED_10000; | |
10148 | bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); | |
10149 | bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); | |
10150 | vars->line_speed = temp; | |
10151 | } | |
a22f0788 YR |
10152 | |
10153 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, | |
bac27bd9 | 10154 | MDIO_CTL_REG_84823_MEDIA, &val); |
a22f0788 YR |
10155 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | |
10156 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK | | |
10157 | MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | | |
10158 | MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | | |
10159 | MDIO_CTL_REG_84823_MEDIA_FIBER_1G); | |
0d40f0d4 YR |
10160 | |
10161 | if (CHIP_IS_E3(bp)) { | |
10162 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | | |
10163 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK); | |
10164 | } else { | |
10165 | val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | | |
10166 | MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); | |
10167 | } | |
a22f0788 YR |
10168 | |
10169 | actual_phy_selection = bnx2x_phy_selection(params); | |
10170 | ||
10171 | switch (actual_phy_selection) { | |
10172 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
25985edc | 10173 | /* Do nothing. Essentially this is like the priority copper */ |
a22f0788 YR |
10174 | break; |
10175 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
10176 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; | |
10177 | break; | |
10178 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
10179 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; | |
10180 | break; | |
10181 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
10182 | /* Do nothing here. The first PHY won't be initialized at all */ | |
10183 | break; | |
10184 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
10185 | val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; | |
10186 | initialize = 0; | |
10187 | break; | |
10188 | } | |
10189 | if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) | |
10190 | val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; | |
10191 | ||
10192 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
bac27bd9 | 10193 | MDIO_CTL_REG_84823_MEDIA, val); |
a22f0788 YR |
10194 | DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", |
10195 | params->multi_phy_config, val); | |
10196 | ||
0f6bb03d YR |
10197 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
10198 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { | |
11b2ec6b | 10199 | bnx2x_84833_pair_swap_cfg(phy, params, vars); |
a89a1d4a | 10200 | |
096b9527 YR |
10201 | /* Keep AutogrEEEn disabled. */ |
10202 | cmd_args[0] = 0x0; | |
11b2ec6b YR |
10203 | cmd_args[1] = 0x0; |
10204 | cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; | |
10205 | cmd_args[3] = PHY84833_CONSTANT_LATENCY; | |
10206 | rc = bnx2x_84833_cmd_hdlr(phy, params, | |
c8c60d88 YM |
10207 | PHY84833_CMD_SET_EEE_MODE, cmd_args, |
10208 | PHY84833_CMDHDLR_MAX_ARGS); | |
d231023e | 10209 | if (rc) |
11b2ec6b YR |
10210 | DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); |
10211 | } | |
a22f0788 YR |
10212 | if (initialize) |
10213 | rc = bnx2x_848xx_cmn_config_init(phy, params, vars); | |
10214 | else | |
11b2ec6b | 10215 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); |
a89a1d4a YR |
10216 | /* 84833 PHY has a better feature and doesn't need to support this. */ |
10217 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
503976e9 | 10218 | u32 cms_enable = REG_RD(bp, params->shmem_base + |
1bef68e3 YR |
10219 | offsetof(struct shmem_region, |
10220 | dev_info.port_hw_config[params->port].default_cfg)) & | |
10221 | PORT_HW_CFG_ENABLE_CMS_MASK; | |
10222 | ||
a89a1d4a YR |
10223 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
10224 | MDIO_CTL_REG_84823_USER_CTRL_REG, &val); | |
10225 | if (cms_enable) | |
10226 | val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; | |
10227 | else | |
10228 | val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; | |
10229 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
10230 | MDIO_CTL_REG_84823_USER_CTRL_REG, val); | |
10231 | } | |
1bef68e3 | 10232 | |
c8c60d88 YM |
10233 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
10234 | MDIO_84833_TOP_CFG_FW_REV, &val); | |
10235 | ||
10236 | /* Configure EEE support */ | |
f6b6eb69 YM |
10237 | if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && |
10238 | (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && | |
10239 | bnx2x_eee_has_cap(params)) { | |
ec4010ec | 10240 | rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); |
d231023e | 10241 | if (rc) { |
c8c60d88 YM |
10242 | DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); |
10243 | bnx2x_8483x_disable_eee(phy, params, vars); | |
10244 | return rc; | |
10245 | } | |
10246 | ||
fd5dfca7 | 10247 | if ((phy->req_duplex == DUPLEX_FULL) && |
c8c60d88 YM |
10248 | (params->eee_mode & EEE_MODE_ADV_LPI) && |
10249 | (bnx2x_eee_calc_timer(params) || | |
10250 | !(params->eee_mode & EEE_MODE_ENABLE_LPI))) | |
10251 | rc = bnx2x_8483x_enable_eee(phy, params, vars); | |
10252 | else | |
10253 | rc = bnx2x_8483x_disable_eee(phy, params, vars); | |
d231023e | 10254 | if (rc) { |
efc7ce03 | 10255 | DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n"); |
c8c60d88 YM |
10256 | return rc; |
10257 | } | |
10258 | } else { | |
c8c60d88 YM |
10259 | vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; |
10260 | } | |
10261 | ||
0f6bb03d YR |
10262 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
10263 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { | |
11b2ec6b | 10264 | /* Bring PHY out of super isolate mode as the final step. */ |
503976e9 YR |
10265 | bnx2x_cl45_read_and_write(bp, phy, |
10266 | MDIO_CTL_DEVAD, | |
10267 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, | |
10268 | (u16)~MDIO_84833_SUPER_ISOLATE); | |
11b2ec6b | 10269 | } |
a22f0788 | 10270 | return rc; |
de6eae1f | 10271 | } |
ea4e040a | 10272 | |
de6eae1f | 10273 | static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, |
cd88ccee YR |
10274 | struct link_params *params, |
10275 | struct link_vars *vars) | |
de6eae1f YR |
10276 | { |
10277 | struct bnx2x *bp = params->bp; | |
bac27bd9 | 10278 | u16 val, val1, val2; |
de6eae1f | 10279 | u8 link_up = 0; |
ea4e040a | 10280 | |
c87bca1e | 10281 | |
de6eae1f YR |
10282 | /* Check 10G-BaseT link status */ |
10283 | /* Check PMD signal ok */ | |
10284 | bnx2x_cl45_read(bp, phy, | |
10285 | MDIO_AN_DEVAD, 0xFFFA, &val1); | |
10286 | bnx2x_cl45_read(bp, phy, | |
bac27bd9 | 10287 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, |
de6eae1f YR |
10288 | &val2); |
10289 | DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); | |
ea4e040a | 10290 | |
de6eae1f YR |
10291 | /* Check link 10G */ |
10292 | if (val2 & (1<<11)) { | |
ea4e040a | 10293 | vars->line_speed = SPEED_10000; |
791f18c0 | 10294 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
10295 | link_up = 1; |
10296 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
10297 | } else { /* Check Legacy speed link */ | |
10298 | u16 legacy_status, legacy_speed; | |
ea4e040a | 10299 | |
de6eae1f YR |
10300 | /* Enable expansion register 0x42 (Operation mode status) */ |
10301 | bnx2x_cl45_write(bp, phy, | |
10302 | MDIO_AN_DEVAD, | |
10303 | MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); | |
ea4e040a | 10304 | |
de6eae1f YR |
10305 | /* Get legacy speed operation status */ |
10306 | bnx2x_cl45_read(bp, phy, | |
10307 | MDIO_AN_DEVAD, | |
10308 | MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, | |
10309 | &legacy_status); | |
ea4e040a | 10310 | |
94f05b0f JP |
10311 | DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", |
10312 | legacy_status); | |
de6eae1f | 10313 | link_up = ((legacy_status & (1<<11)) == (1<<11)); |
14400901 YM |
10314 | legacy_speed = (legacy_status & (3<<9)); |
10315 | if (legacy_speed == (0<<9)) | |
10316 | vars->line_speed = SPEED_10; | |
10317 | else if (legacy_speed == (1<<9)) | |
10318 | vars->line_speed = SPEED_100; | |
10319 | else if (legacy_speed == (2<<9)) | |
10320 | vars->line_speed = SPEED_1000; | |
10321 | else { /* Should not happen: Treat as link down */ | |
10322 | vars->line_speed = 0; | |
10323 | link_up = 0; | |
10324 | } | |
ea4e040a | 10325 | |
14400901 | 10326 | if (link_up) { |
de6eae1f YR |
10327 | if (legacy_status & (1<<8)) |
10328 | vars->duplex = DUPLEX_FULL; | |
10329 | else | |
10330 | vars->duplex = DUPLEX_HALF; | |
ea4e040a | 10331 | |
94f05b0f JP |
10332 | DP(NETIF_MSG_LINK, |
10333 | "Link is up in %dMbps, is_duplex_full= %d\n", | |
10334 | vars->line_speed, | |
10335 | (vars->duplex == DUPLEX_FULL)); | |
de6eae1f YR |
10336 | /* Check legacy speed AN resolution */ |
10337 | bnx2x_cl45_read(bp, phy, | |
10338 | MDIO_AN_DEVAD, | |
10339 | MDIO_AN_REG_8481_LEGACY_MII_STATUS, | |
10340 | &val); | |
10341 | if (val & (1<<5)) | |
10342 | vars->link_status |= | |
10343 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
10344 | bnx2x_cl45_read(bp, phy, | |
10345 | MDIO_AN_DEVAD, | |
10346 | MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, | |
10347 | &val); | |
10348 | if ((val & (1<<0)) == 0) | |
10349 | vars->link_status |= | |
10350 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
ea4e040a | 10351 | } |
ea4e040a | 10352 | } |
de6eae1f | 10353 | if (link_up) { |
d231023e | 10354 | DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", |
de6eae1f YR |
10355 | vars->line_speed); |
10356 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
9e7e8399 MY |
10357 | |
10358 | /* Read LP advertised speeds */ | |
10359 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10360 | MDIO_AN_REG_CL37_FC_LP, &val); | |
10361 | if (val & (1<<5)) | |
10362 | vars->link_status |= | |
10363 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; | |
10364 | if (val & (1<<6)) | |
10365 | vars->link_status |= | |
10366 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; | |
10367 | if (val & (1<<7)) | |
10368 | vars->link_status |= | |
10369 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; | |
10370 | if (val & (1<<8)) | |
10371 | vars->link_status |= | |
10372 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; | |
10373 | if (val & (1<<9)) | |
10374 | vars->link_status |= | |
10375 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; | |
10376 | ||
10377 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10378 | MDIO_AN_REG_1000T_STATUS, &val); | |
10379 | ||
10380 | if (val & (1<<10)) | |
10381 | vars->link_status |= | |
10382 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; | |
10383 | if (val & (1<<11)) | |
10384 | vars->link_status |= | |
10385 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
10386 | ||
10387 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10388 | MDIO_AN_REG_MASTER_STATUS, &val); | |
10389 | ||
10390 | if (val & (1<<11)) | |
10391 | vars->link_status |= | |
10392 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
c8c60d88 YM |
10393 | |
10394 | /* Determine if EEE was negotiated */ | |
31b958d7 YR |
10395 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
10396 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) | |
ec4010ec | 10397 | bnx2x_eee_an_resolve(phy, params, vars); |
de6eae1f | 10398 | } |
589abe3a | 10399 | |
de6eae1f | 10400 | return link_up; |
b7737c9b YR |
10401 | } |
10402 | ||
fcf5b650 | 10403 | static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) |
b7737c9b | 10404 | { |
fcf5b650 | 10405 | int status = 0; |
de6eae1f YR |
10406 | u32 spirom_ver; |
10407 | spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); | |
10408 | status = bnx2x_format_ver(spirom_ver, str, len); | |
10409 | return status; | |
b7737c9b | 10410 | } |
de6eae1f YR |
10411 | |
10412 | static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, | |
10413 | struct link_params *params) | |
b7737c9b | 10414 | { |
de6eae1f | 10415 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 10416 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); |
de6eae1f | 10417 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 10418 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); |
b7737c9b | 10419 | } |
de6eae1f | 10420 | |
b7737c9b YR |
10421 | static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, |
10422 | struct link_params *params) | |
10423 | { | |
10424 | bnx2x_cl45_write(params->bp, phy, | |
10425 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
10426 | bnx2x_cl45_write(params->bp, phy, | |
10427 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); | |
10428 | } | |
10429 | ||
10430 | static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, | |
10431 | struct link_params *params) | |
10432 | { | |
10433 | struct bnx2x *bp = params->bp; | |
6a71bbe0 | 10434 | u8 port; |
0d40f0d4 | 10435 | u16 val16; |
bac27bd9 | 10436 | |
f93fb016 | 10437 | if (!(CHIP_IS_E1x(bp))) |
6a71bbe0 YR |
10438 | port = BP_PATH(bp); |
10439 | else | |
10440 | port = params->port; | |
bac27bd9 YR |
10441 | |
10442 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
10443 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
10444 | MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
10445 | port); | |
10446 | } else { | |
0d40f0d4 YR |
10447 | bnx2x_cl45_read(bp, phy, |
10448 | MDIO_CTL_DEVAD, | |
11b2ec6b YR |
10449 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); |
10450 | val16 |= MDIO_84833_SUPER_ISOLATE; | |
fd38f73e | 10451 | bnx2x_cl45_write(bp, phy, |
11b2ec6b YR |
10452 | MDIO_CTL_DEVAD, |
10453 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); | |
bac27bd9 | 10454 | } |
b7737c9b YR |
10455 | } |
10456 | ||
7f02c4ad YR |
10457 | static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, |
10458 | struct link_params *params, u8 mode) | |
10459 | { | |
10460 | struct bnx2x *bp = params->bp; | |
10461 | u16 val; | |
bac27bd9 YR |
10462 | u8 port; |
10463 | ||
f93fb016 | 10464 | if (!(CHIP_IS_E1x(bp))) |
bac27bd9 YR |
10465 | port = BP_PATH(bp); |
10466 | else | |
10467 | port = params->port; | |
7f02c4ad YR |
10468 | |
10469 | switch (mode) { | |
10470 | case LED_MODE_OFF: | |
10471 | ||
bac27bd9 | 10472 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); |
7f02c4ad YR |
10473 | |
10474 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10475 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10476 | ||
10477 | /* Set LED masks */ | |
10478 | bnx2x_cl45_write(bp, phy, | |
10479 | MDIO_PMA_DEVAD, | |
10480 | MDIO_PMA_REG_8481_LED1_MASK, | |
10481 | 0x0); | |
10482 | ||
10483 | bnx2x_cl45_write(bp, phy, | |
10484 | MDIO_PMA_DEVAD, | |
10485 | MDIO_PMA_REG_8481_LED2_MASK, | |
10486 | 0x0); | |
10487 | ||
10488 | bnx2x_cl45_write(bp, phy, | |
10489 | MDIO_PMA_DEVAD, | |
10490 | MDIO_PMA_REG_8481_LED3_MASK, | |
10491 | 0x0); | |
10492 | ||
10493 | bnx2x_cl45_write(bp, phy, | |
10494 | MDIO_PMA_DEVAD, | |
10495 | MDIO_PMA_REG_8481_LED5_MASK, | |
10496 | 0x0); | |
10497 | ||
10498 | } else { | |
10499 | bnx2x_cl45_write(bp, phy, | |
10500 | MDIO_PMA_DEVAD, | |
10501 | MDIO_PMA_REG_8481_LED1_MASK, | |
10502 | 0x0); | |
10503 | } | |
10504 | break; | |
10505 | case LED_MODE_FRONT_PANEL_OFF: | |
10506 | ||
10507 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", | |
bac27bd9 | 10508 | port); |
7f02c4ad YR |
10509 | |
10510 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10511 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10512 | ||
10513 | /* Set LED masks */ | |
10514 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10515 | MDIO_PMA_DEVAD, |
10516 | MDIO_PMA_REG_8481_LED1_MASK, | |
10517 | 0x0); | |
7f02c4ad YR |
10518 | |
10519 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10520 | MDIO_PMA_DEVAD, |
10521 | MDIO_PMA_REG_8481_LED2_MASK, | |
10522 | 0x0); | |
7f02c4ad YR |
10523 | |
10524 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10525 | MDIO_PMA_DEVAD, |
10526 | MDIO_PMA_REG_8481_LED3_MASK, | |
10527 | 0x0); | |
7f02c4ad YR |
10528 | |
10529 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10530 | MDIO_PMA_DEVAD, |
10531 | MDIO_PMA_REG_8481_LED5_MASK, | |
10532 | 0x20); | |
7f02c4ad YR |
10533 | |
10534 | } else { | |
10535 | bnx2x_cl45_write(bp, phy, | |
10536 | MDIO_PMA_DEVAD, | |
10537 | MDIO_PMA_REG_8481_LED1_MASK, | |
10538 | 0x0); | |
8ce76845 YR |
10539 | if (phy->type == |
10540 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { | |
10541 | /* Disable MI_INT interrupt before setting LED4 | |
10542 | * source to constant off. | |
10543 | */ | |
10544 | if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + | |
10545 | params->port*4) & | |
10546 | NIG_MASK_MI_INT) { | |
10547 | params->link_flags |= | |
10548 | LINK_FLAGS_INT_DISABLED; | |
10549 | ||
10550 | bnx2x_bits_dis( | |
10551 | bp, | |
10552 | NIG_REG_MASK_INTERRUPT_PORT0 + | |
10553 | params->port*4, | |
10554 | NIG_MASK_MI_INT); | |
10555 | } | |
10556 | bnx2x_cl45_write(bp, phy, | |
10557 | MDIO_PMA_DEVAD, | |
10558 | MDIO_PMA_REG_8481_SIGNAL_MASK, | |
10559 | 0x0); | |
10560 | } | |
7f02c4ad YR |
10561 | } |
10562 | break; | |
10563 | case LED_MODE_ON: | |
10564 | ||
bac27bd9 | 10565 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); |
7f02c4ad YR |
10566 | |
10567 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10568 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10569 | /* Set control reg */ | |
10570 | bnx2x_cl45_read(bp, phy, | |
10571 | MDIO_PMA_DEVAD, | |
10572 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10573 | &val); | |
10574 | val &= 0x8000; | |
10575 | val |= 0x2492; | |
10576 | ||
10577 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10578 | MDIO_PMA_DEVAD, |
10579 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10580 | val); | |
7f02c4ad YR |
10581 | |
10582 | /* Set LED masks */ | |
10583 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10584 | MDIO_PMA_DEVAD, |
10585 | MDIO_PMA_REG_8481_LED1_MASK, | |
10586 | 0x0); | |
7f02c4ad YR |
10587 | |
10588 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10589 | MDIO_PMA_DEVAD, |
10590 | MDIO_PMA_REG_8481_LED2_MASK, | |
10591 | 0x20); | |
7f02c4ad YR |
10592 | |
10593 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10594 | MDIO_PMA_DEVAD, |
10595 | MDIO_PMA_REG_8481_LED3_MASK, | |
10596 | 0x20); | |
7f02c4ad YR |
10597 | |
10598 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10599 | MDIO_PMA_DEVAD, |
10600 | MDIO_PMA_REG_8481_LED5_MASK, | |
10601 | 0x0); | |
7f02c4ad YR |
10602 | } else { |
10603 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10604 | MDIO_PMA_DEVAD, |
10605 | MDIO_PMA_REG_8481_LED1_MASK, | |
10606 | 0x20); | |
8ce76845 YR |
10607 | if (phy->type == |
10608 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { | |
10609 | /* Disable MI_INT interrupt before setting LED4 | |
10610 | * source to constant on. | |
10611 | */ | |
10612 | if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + | |
10613 | params->port*4) & | |
10614 | NIG_MASK_MI_INT) { | |
10615 | params->link_flags |= | |
10616 | LINK_FLAGS_INT_DISABLED; | |
10617 | ||
10618 | bnx2x_bits_dis( | |
10619 | bp, | |
10620 | NIG_REG_MASK_INTERRUPT_PORT0 + | |
10621 | params->port*4, | |
10622 | NIG_MASK_MI_INT); | |
10623 | } | |
10624 | bnx2x_cl45_write(bp, phy, | |
10625 | MDIO_PMA_DEVAD, | |
10626 | MDIO_PMA_REG_8481_SIGNAL_MASK, | |
10627 | 0x20); | |
10628 | } | |
7f02c4ad YR |
10629 | } |
10630 | break; | |
10631 | ||
10632 | case LED_MODE_OPER: | |
10633 | ||
bac27bd9 | 10634 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); |
7f02c4ad YR |
10635 | |
10636 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10637 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10638 | ||
10639 | /* Set control reg */ | |
10640 | bnx2x_cl45_read(bp, phy, | |
10641 | MDIO_PMA_DEVAD, | |
10642 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10643 | &val); | |
10644 | ||
10645 | if (!((val & | |
cd88ccee YR |
10646 | MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) |
10647 | >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { | |
2cf7acf9 | 10648 | DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); |
7f02c4ad YR |
10649 | bnx2x_cl45_write(bp, phy, |
10650 | MDIO_PMA_DEVAD, | |
10651 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10652 | 0xa492); | |
10653 | } | |
10654 | ||
10655 | /* Set LED masks */ | |
10656 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10657 | MDIO_PMA_DEVAD, |
10658 | MDIO_PMA_REG_8481_LED1_MASK, | |
10659 | 0x10); | |
7f02c4ad YR |
10660 | |
10661 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10662 | MDIO_PMA_DEVAD, |
10663 | MDIO_PMA_REG_8481_LED2_MASK, | |
10664 | 0x80); | |
7f02c4ad YR |
10665 | |
10666 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10667 | MDIO_PMA_DEVAD, |
10668 | MDIO_PMA_REG_8481_LED3_MASK, | |
10669 | 0x98); | |
7f02c4ad YR |
10670 | |
10671 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10672 | MDIO_PMA_DEVAD, |
10673 | MDIO_PMA_REG_8481_LED5_MASK, | |
10674 | 0x40); | |
7f02c4ad YR |
10675 | |
10676 | } else { | |
7dc950ca YR |
10677 | /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED |
10678 | * sources are all wired through LED1, rather than only | |
10679 | * 10G in other modes. | |
10680 | */ | |
10681 | val = ((params->hw_led_mode << | |
10682 | SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10683 | SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; | |
10684 | ||
7f02c4ad YR |
10685 | bnx2x_cl45_write(bp, phy, |
10686 | MDIO_PMA_DEVAD, | |
10687 | MDIO_PMA_REG_8481_LED1_MASK, | |
7dc950ca | 10688 | val); |
53eda06d YR |
10689 | |
10690 | /* Tell LED3 to blink on source */ | |
10691 | bnx2x_cl45_read(bp, phy, | |
10692 | MDIO_PMA_DEVAD, | |
10693 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10694 | &val); | |
10695 | val &= ~(7<<6); | |
10696 | val |= (1<<6); /* A83B[8:6]= 1 */ | |
10697 | bnx2x_cl45_write(bp, phy, | |
10698 | MDIO_PMA_DEVAD, | |
10699 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10700 | val); | |
8ce76845 YR |
10701 | if (phy->type == |
10702 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { | |
10703 | /* Restore LED4 source to external link, | |
10704 | * and re-enable interrupts. | |
10705 | */ | |
10706 | bnx2x_cl45_write(bp, phy, | |
10707 | MDIO_PMA_DEVAD, | |
10708 | MDIO_PMA_REG_8481_SIGNAL_MASK, | |
10709 | 0x40); | |
10710 | if (params->link_flags & | |
10711 | LINK_FLAGS_INT_DISABLED) { | |
10712 | bnx2x_link_int_enable(params); | |
10713 | params->link_flags &= | |
10714 | ~LINK_FLAGS_INT_DISABLED; | |
10715 | } | |
10716 | } | |
7f02c4ad YR |
10717 | } |
10718 | break; | |
10719 | } | |
0d40f0d4 | 10720 | |
8f73f0b9 | 10721 | /* This is a workaround for E3+84833 until autoneg |
0d40f0d4 YR |
10722 | * restart is fixed in f/w |
10723 | */ | |
10724 | if (CHIP_IS_E3(bp)) { | |
10725 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
10726 | MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); | |
10727 | } | |
7f02c4ad | 10728 | } |
0d40f0d4 | 10729 | |
6583e33b | 10730 | /******************************************************************/ |
52c4d6c4 | 10731 | /* 54618SE PHY SECTION */ |
6583e33b | 10732 | /******************************************************************/ |
5c107fda YR |
10733 | static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, |
10734 | struct link_params *params, | |
10735 | u32 action) | |
10736 | { | |
10737 | struct bnx2x *bp = params->bp; | |
10738 | u16 temp; | |
10739 | switch (action) { | |
10740 | case PHY_INIT: | |
10741 | /* Configure LED4: set to INTR (0x6). */ | |
10742 | /* Accessing shadow register 0xe. */ | |
10743 | bnx2x_cl22_write(bp, phy, | |
10744 | MDIO_REG_GPHY_SHADOW, | |
10745 | MDIO_REG_GPHY_SHADOW_LED_SEL2); | |
10746 | bnx2x_cl22_read(bp, phy, | |
10747 | MDIO_REG_GPHY_SHADOW, | |
10748 | &temp); | |
10749 | temp &= ~(0xf << 4); | |
10750 | temp |= (0x6 << 4); | |
10751 | bnx2x_cl22_write(bp, phy, | |
10752 | MDIO_REG_GPHY_SHADOW, | |
10753 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10754 | /* Configure INTR based on link status change. */ | |
10755 | bnx2x_cl22_write(bp, phy, | |
10756 | MDIO_REG_INTR_MASK, | |
10757 | ~MDIO_REG_INTR_MASK_LINK_STATUS); | |
10758 | break; | |
10759 | } | |
10760 | } | |
10761 | ||
52c4d6c4 | 10762 | static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, |
6583e33b YR |
10763 | struct link_params *params, |
10764 | struct link_vars *vars) | |
10765 | { | |
10766 | struct bnx2x *bp = params->bp; | |
10767 | u8 port; | |
10768 | u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; | |
10769 | u32 cfg_pin; | |
10770 | ||
52c4d6c4 | 10771 | DP(NETIF_MSG_LINK, "54618SE cfg init\n"); |
d231023e | 10772 | usleep_range(1000, 2000); |
6583e33b | 10773 | |
8f73f0b9 | 10774 | /* This works with E3 only, no need to check the chip |
2f751a80 YR |
10775 | * before determining the port. |
10776 | */ | |
6583e33b YR |
10777 | port = params->port; |
10778 | ||
10779 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
10780 | offsetof(struct shmem_region, | |
10781 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
10782 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10783 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10784 | ||
10785 | /* Drive pin high to bring the GPHY out of reset. */ | |
10786 | bnx2x_set_cfg_pin(bp, cfg_pin, 1); | |
10787 | ||
10788 | /* wait for GPHY to reset */ | |
10789 | msleep(50); | |
10790 | ||
10791 | /* reset phy */ | |
10792 | bnx2x_cl22_write(bp, phy, | |
10793 | MDIO_PMA_REG_CTRL, 0x8000); | |
10794 | bnx2x_wait_reset_complete(bp, phy, params); | |
10795 | ||
8f73f0b9 | 10796 | /* Wait for GPHY to reset */ |
6583e33b YR |
10797 | msleep(50); |
10798 | ||
6583e33b | 10799 | |
5c107fda | 10800 | bnx2x_54618se_specific_func(phy, params, PHY_INIT); |
6583e33b YR |
10801 | /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ |
10802 | bnx2x_cl22_write(bp, phy, | |
10803 | MDIO_REG_GPHY_SHADOW, | |
10804 | MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); | |
10805 | bnx2x_cl22_read(bp, phy, | |
10806 | MDIO_REG_GPHY_SHADOW, | |
10807 | &temp); | |
10808 | temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; | |
10809 | bnx2x_cl22_write(bp, phy, | |
10810 | MDIO_REG_GPHY_SHADOW, | |
10811 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10812 | ||
10813 | /* Set up fc */ | |
10814 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
10815 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
10816 | fc_val = 0; | |
10817 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
10818 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) | |
10819 | fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
10820 | ||
10821 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
10822 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
10823 | fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
10824 | ||
d231023e | 10825 | /* Read all advertisement */ |
6583e33b YR |
10826 | bnx2x_cl22_read(bp, phy, |
10827 | 0x09, | |
10828 | &an_1000_val); | |
10829 | ||
10830 | bnx2x_cl22_read(bp, phy, | |
10831 | 0x04, | |
10832 | &an_10_100_val); | |
10833 | ||
10834 | bnx2x_cl22_read(bp, phy, | |
10835 | MDIO_PMA_REG_CTRL, | |
10836 | &autoneg_val); | |
10837 | ||
10838 | /* Disable forced speed */ | |
10839 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); | |
10840 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | | |
10841 | (1<<11)); | |
10842 | ||
10843 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
a429ec23 YR |
10844 | (phy->speed_cap_mask & |
10845 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
10846 | (phy->req_line_speed == SPEED_1000)) { | |
6583e33b YR |
10847 | an_1000_val |= (1<<8); |
10848 | autoneg_val |= (1<<9 | 1<<12); | |
10849 | if (phy->req_duplex == DUPLEX_FULL) | |
10850 | an_1000_val |= (1<<9); | |
10851 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); | |
10852 | } else | |
10853 | an_1000_val &= ~((1<<8) | (1<<9)); | |
10854 | ||
10855 | bnx2x_cl22_write(bp, phy, | |
10856 | 0x09, | |
10857 | an_1000_val); | |
10858 | bnx2x_cl22_read(bp, phy, | |
10859 | 0x09, | |
10860 | &an_1000_val); | |
10861 | ||
a429ec23 YR |
10862 | /* Advertise 10/100 link speed */ |
10863 | if (phy->req_line_speed == SPEED_AUTO_NEG) { | |
10864 | if (phy->speed_cap_mask & | |
10865 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { | |
10866 | an_10_100_val |= (1<<5); | |
10867 | autoneg_val |= (1<<9 | 1<<12); | |
10868 | DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); | |
10869 | } | |
10870 | if (phy->speed_cap_mask & | |
10871 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) { | |
6583e33b | 10872 | an_10_100_val |= (1<<6); |
a429ec23 YR |
10873 | autoneg_val |= (1<<9 | 1<<12); |
10874 | DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); | |
10875 | } | |
10876 | if (phy->speed_cap_mask & | |
10877 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { | |
10878 | an_10_100_val |= (1<<7); | |
10879 | autoneg_val |= (1<<9 | 1<<12); | |
10880 | DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); | |
10881 | } | |
10882 | if (phy->speed_cap_mask & | |
10883 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { | |
10884 | an_10_100_val |= (1<<8); | |
10885 | autoneg_val |= (1<<9 | 1<<12); | |
10886 | DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); | |
10887 | } | |
6583e33b YR |
10888 | } |
10889 | ||
10890 | /* Only 10/100 are allowed to work in FORCE mode */ | |
10891 | if (phy->req_line_speed == SPEED_100) { | |
10892 | autoneg_val |= (1<<13); | |
10893 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
10894 | bnx2x_cl22_write(bp, phy, | |
10895 | 0x18, | |
10896 | (1<<15 | 1<<9 | 7<<0)); | |
10897 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); | |
10898 | } | |
10899 | if (phy->req_line_speed == SPEED_10) { | |
10900 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
10901 | bnx2x_cl22_write(bp, phy, | |
10902 | 0x18, | |
10903 | (1<<15 | 1<<9 | 7<<0)); | |
10904 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); | |
10905 | } | |
10906 | ||
26964bb7 YM |
10907 | if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { |
10908 | int rc; | |
10909 | ||
10910 | bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, | |
10911 | MDIO_REG_GPHY_EXP_ACCESS_TOP | | |
10912 | MDIO_REG_GPHY_EXP_TOP_2K_BUF); | |
10913 | bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); | |
10914 | temp &= 0xfffe; | |
10915 | bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); | |
10916 | ||
10917 | rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); | |
10918 | if (rc) { | |
10919 | DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); | |
10920 | bnx2x_eee_disable(phy, params, vars); | |
10921 | } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && | |
10922 | (phy->req_duplex == DUPLEX_FULL) && | |
10923 | (bnx2x_eee_calc_timer(params) || | |
10924 | !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { | |
10925 | /* Need to advertise EEE only when requested, | |
10926 | * and either no LPI assertion was requested, | |
10927 | * or it was requested and a valid timer was set. | |
10928 | * Also notice full duplex is required for EEE. | |
10929 | */ | |
10930 | bnx2x_eee_advertise(phy, params, vars, | |
10931 | SHMEM_EEE_1G_ADV); | |
a89a1d4a | 10932 | } else { |
26964bb7 YM |
10933 | DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); |
10934 | bnx2x_eee_disable(phy, params, vars); | |
10935 | } | |
10936 | } else { | |
10937 | vars->eee_status &= ~SHMEM_EEE_1G_ADV << | |
10938 | SHMEM_EEE_SUPPORTED_SHIFT; | |
10939 | ||
10940 | if (phy->flags & FLAGS_EEE) { | |
10941 | /* Handle legacy auto-grEEEn */ | |
10942 | if (params->feature_config_flags & | |
10943 | FEATURE_CONFIG_AUTOGREEEN_ENABLED) { | |
10944 | temp = 6; | |
10945 | DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); | |
10946 | } else { | |
10947 | temp = 0; | |
10948 | DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); | |
10949 | } | |
10950 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
10951 | MDIO_AN_REG_EEE_ADV, temp); | |
a89a1d4a | 10952 | } |
a89a1d4a YR |
10953 | } |
10954 | ||
6583e33b YR |
10955 | bnx2x_cl22_write(bp, phy, |
10956 | 0x04, | |
10957 | an_10_100_val | fc_val); | |
10958 | ||
10959 | if (phy->req_duplex == DUPLEX_FULL) | |
10960 | autoneg_val |= (1<<8); | |
10961 | ||
10962 | bnx2x_cl22_write(bp, phy, | |
10963 | MDIO_PMA_REG_CTRL, autoneg_val); | |
10964 | ||
10965 | return 0; | |
10966 | } | |
10967 | ||
1d125bd5 YR |
10968 | |
10969 | static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, | |
10970 | struct link_params *params, u8 mode) | |
10971 | { | |
10972 | struct bnx2x *bp = params->bp; | |
10973 | u16 temp; | |
10974 | ||
10975 | bnx2x_cl22_write(bp, phy, | |
10976 | MDIO_REG_GPHY_SHADOW, | |
10977 | MDIO_REG_GPHY_SHADOW_LED_SEL1); | |
10978 | bnx2x_cl22_read(bp, phy, | |
10979 | MDIO_REG_GPHY_SHADOW, | |
10980 | &temp); | |
10981 | temp &= 0xff00; | |
10982 | ||
10983 | DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); | |
10984 | switch (mode) { | |
10985 | case LED_MODE_FRONT_PANEL_OFF: | |
10986 | case LED_MODE_OFF: | |
10987 | temp |= 0x00ee; | |
10988 | break; | |
10989 | case LED_MODE_OPER: | |
10990 | temp |= 0x0001; | |
10991 | break; | |
10992 | case LED_MODE_ON: | |
10993 | temp |= 0x00ff; | |
10994 | break; | |
10995 | default: | |
10996 | break; | |
10997 | } | |
10998 | bnx2x_cl22_write(bp, phy, | |
10999 | MDIO_REG_GPHY_SHADOW, | |
11000 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
11001 | return; | |
11002 | } | |
11003 | ||
11004 | ||
52c4d6c4 YR |
11005 | static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, |
11006 | struct link_params *params) | |
6583e33b YR |
11007 | { |
11008 | struct bnx2x *bp = params->bp; | |
11009 | u32 cfg_pin; | |
11010 | u8 port; | |
11011 | ||
8f73f0b9 | 11012 | /* In case of no EPIO routed to reset the GPHY, put it |
d2059a06 YR |
11013 | * in low power mode. |
11014 | */ | |
11015 | bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); | |
8f73f0b9 | 11016 | /* This works with E3 only, no need to check the chip |
d2059a06 YR |
11017 | * before determining the port. |
11018 | */ | |
6583e33b YR |
11019 | port = params->port; |
11020 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
11021 | offsetof(struct shmem_region, | |
11022 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
11023 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
11024 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
11025 | ||
11026 | /* Drive pin low to put GPHY in reset. */ | |
11027 | bnx2x_set_cfg_pin(bp, cfg_pin, 0); | |
11028 | } | |
11029 | ||
52c4d6c4 YR |
11030 | static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, |
11031 | struct link_params *params, | |
11032 | struct link_vars *vars) | |
6583e33b YR |
11033 | { |
11034 | struct bnx2x *bp = params->bp; | |
11035 | u16 val; | |
11036 | u8 link_up = 0; | |
11037 | u16 legacy_status, legacy_speed; | |
11038 | ||
11039 | /* Get speed operation status */ | |
11040 | bnx2x_cl22_read(bp, phy, | |
a351d497 | 11041 | MDIO_REG_GPHY_AUX_STATUS, |
6583e33b | 11042 | &legacy_status); |
52c4d6c4 | 11043 | DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); |
6583e33b YR |
11044 | |
11045 | /* Read status to clear the PHY interrupt. */ | |
11046 | bnx2x_cl22_read(bp, phy, | |
11047 | MDIO_REG_INTR_STATUS, | |
11048 | &val); | |
11049 | ||
11050 | link_up = ((legacy_status & (1<<2)) == (1<<2)); | |
11051 | ||
11052 | if (link_up) { | |
11053 | legacy_speed = (legacy_status & (7<<8)); | |
11054 | if (legacy_speed == (7<<8)) { | |
11055 | vars->line_speed = SPEED_1000; | |
11056 | vars->duplex = DUPLEX_FULL; | |
11057 | } else if (legacy_speed == (6<<8)) { | |
11058 | vars->line_speed = SPEED_1000; | |
11059 | vars->duplex = DUPLEX_HALF; | |
11060 | } else if (legacy_speed == (5<<8)) { | |
11061 | vars->line_speed = SPEED_100; | |
11062 | vars->duplex = DUPLEX_FULL; | |
11063 | } | |
11064 | /* Omitting 100Base-T4 for now */ | |
11065 | else if (legacy_speed == (3<<8)) { | |
11066 | vars->line_speed = SPEED_100; | |
11067 | vars->duplex = DUPLEX_HALF; | |
11068 | } else if (legacy_speed == (2<<8)) { | |
11069 | vars->line_speed = SPEED_10; | |
11070 | vars->duplex = DUPLEX_FULL; | |
11071 | } else if (legacy_speed == (1<<8)) { | |
11072 | vars->line_speed = SPEED_10; | |
11073 | vars->duplex = DUPLEX_HALF; | |
11074 | } else /* Should not happen */ | |
11075 | vars->line_speed = 0; | |
11076 | ||
94f05b0f JP |
11077 | DP(NETIF_MSG_LINK, |
11078 | "Link is up in %dMbps, is_duplex_full= %d\n", | |
11079 | vars->line_speed, | |
11080 | (vars->duplex == DUPLEX_FULL)); | |
6583e33b YR |
11081 | |
11082 | /* Check legacy speed AN resolution */ | |
11083 | bnx2x_cl22_read(bp, phy, | |
11084 | 0x01, | |
11085 | &val); | |
11086 | if (val & (1<<5)) | |
11087 | vars->link_status |= | |
11088 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
11089 | bnx2x_cl22_read(bp, phy, | |
11090 | 0x06, | |
11091 | &val); | |
11092 | if ((val & (1<<0)) == 0) | |
11093 | vars->link_status |= | |
11094 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
11095 | ||
52c4d6c4 | 11096 | DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", |
6583e33b | 11097 | vars->line_speed); |
52c4d6c4 | 11098 | |
6583e33b | 11099 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
9e7e8399 MY |
11100 | |
11101 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
8f73f0b9 | 11102 | /* Report LP advertised speeds */ |
9e7e8399 MY |
11103 | bnx2x_cl22_read(bp, phy, 0x5, &val); |
11104 | ||
11105 | if (val & (1<<5)) | |
11106 | vars->link_status |= | |
11107 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; | |
11108 | if (val & (1<<6)) | |
11109 | vars->link_status |= | |
11110 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; | |
11111 | if (val & (1<<7)) | |
11112 | vars->link_status |= | |
11113 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; | |
11114 | if (val & (1<<8)) | |
11115 | vars->link_status |= | |
11116 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; | |
11117 | if (val & (1<<9)) | |
11118 | vars->link_status |= | |
11119 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; | |
11120 | ||
11121 | bnx2x_cl22_read(bp, phy, 0xa, &val); | |
11122 | if (val & (1<<10)) | |
11123 | vars->link_status |= | |
11124 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; | |
11125 | if (val & (1<<11)) | |
11126 | vars->link_status |= | |
11127 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
26964bb7 YM |
11128 | |
11129 | if ((phy->flags & FLAGS_EEE) && | |
11130 | bnx2x_eee_has_cap(params)) | |
11131 | bnx2x_eee_an_resolve(phy, params, vars); | |
9e7e8399 | 11132 | } |
6583e33b YR |
11133 | } |
11134 | return link_up; | |
11135 | } | |
11136 | ||
52c4d6c4 YR |
11137 | static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, |
11138 | struct link_params *params) | |
6583e33b YR |
11139 | { |
11140 | struct bnx2x *bp = params->bp; | |
11141 | u16 val; | |
11142 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
11143 | ||
52c4d6c4 | 11144 | DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); |
6583e33b YR |
11145 | |
11146 | /* Enable master/slave manual mmode and set to master */ | |
11147 | /* mii write 9 [bits set 11 12] */ | |
11148 | bnx2x_cl22_write(bp, phy, 0x09, 3<<11); | |
11149 | ||
11150 | /* forced 1G and disable autoneg */ | |
11151 | /* set val [mii read 0] */ | |
11152 | /* set val [expr $val & [bits clear 6 12 13]] */ | |
11153 | /* set val [expr $val | [bits set 6 8]] */ | |
11154 | /* mii write 0 $val */ | |
11155 | bnx2x_cl22_read(bp, phy, 0x00, &val); | |
11156 | val &= ~((1<<6) | (1<<12) | (1<<13)); | |
11157 | val |= (1<<6) | (1<<8); | |
11158 | bnx2x_cl22_write(bp, phy, 0x00, val); | |
11159 | ||
11160 | /* Set external loopback and Tx using 6dB coding */ | |
11161 | /* mii write 0x18 7 */ | |
11162 | /* set val [mii read 0x18] */ | |
11163 | /* mii write 0x18 [expr $val | [bits set 10 15]] */ | |
11164 | bnx2x_cl22_write(bp, phy, 0x18, 7); | |
11165 | bnx2x_cl22_read(bp, phy, 0x18, &val); | |
11166 | bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); | |
11167 | ||
11168 | /* This register opens the gate for the UMAC despite its name */ | |
11169 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); | |
11170 | ||
8f73f0b9 | 11171 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame |
6583e33b YR |
11172 | * length used by the MAC receive logic to check frames. |
11173 | */ | |
11174 | REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); | |
11175 | } | |
11176 | ||
de6eae1f YR |
11177 | /******************************************************************/ |
11178 | /* SFX7101 PHY SECTION */ | |
11179 | /******************************************************************/ | |
11180 | static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, | |
11181 | struct link_params *params) | |
b7737c9b YR |
11182 | { |
11183 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
11184 | /* SFX7101_XGXS_TEST1 */ |
11185 | bnx2x_cl45_write(bp, phy, | |
11186 | MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); | |
589abe3a EG |
11187 | } |
11188 | ||
fcf5b650 YR |
11189 | static int bnx2x_7101_config_init(struct bnx2x_phy *phy, |
11190 | struct link_params *params, | |
11191 | struct link_vars *vars) | |
ea4e040a | 11192 | { |
de6eae1f | 11193 | u16 fw_ver1, fw_ver2, val; |
ea4e040a | 11194 | struct bnx2x *bp = params->bp; |
de6eae1f | 11195 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); |
ea4e040a | 11196 | |
de6eae1f YR |
11197 | /* Restore normal power mode*/ |
11198 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 11199 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
11200 | /* HW reset */ |
11201 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
6d870c39 | 11202 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 11203 | |
de6eae1f | 11204 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 11205 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); |
de6eae1f YR |
11206 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); |
11207 | bnx2x_cl45_write(bp, phy, | |
11208 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); | |
ea4e040a | 11209 | |
de6eae1f YR |
11210 | bnx2x_ext_phy_set_pause(params, phy, vars); |
11211 | /* Restart autoneg */ | |
11212 | bnx2x_cl45_read(bp, phy, | |
11213 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); | |
11214 | val |= 0x200; | |
11215 | bnx2x_cl45_write(bp, phy, | |
11216 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); | |
ea4e040a | 11217 | |
de6eae1f YR |
11218 | /* Save spirom version */ |
11219 | bnx2x_cl45_read(bp, phy, | |
11220 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); | |
ea4e040a | 11221 | |
de6eae1f YR |
11222 | bnx2x_cl45_read(bp, phy, |
11223 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); | |
11224 | bnx2x_save_spirom_version(bp, params->port, | |
11225 | (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); | |
11226 | return 0; | |
11227 | } | |
ea4e040a | 11228 | |
de6eae1f YR |
11229 | static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, |
11230 | struct link_params *params, | |
11231 | struct link_vars *vars) | |
57963ed9 YR |
11232 | { |
11233 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
11234 | u8 link_up; |
11235 | u16 val1, val2; | |
11236 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 11237 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); |
de6eae1f | 11238 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 11239 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f YR |
11240 | DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", |
11241 | val2, val1); | |
11242 | bnx2x_cl45_read(bp, phy, | |
11243 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
11244 | bnx2x_cl45_read(bp, phy, | |
11245 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
11246 | DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", | |
11247 | val2, val1); | |
11248 | link_up = ((val1 & 4) == 4); | |
d231023e | 11249 | /* If link is up print the AN outcome of the SFX7101 PHY */ |
de6eae1f YR |
11250 | if (link_up) { |
11251 | bnx2x_cl45_read(bp, phy, | |
11252 | MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, | |
11253 | &val2); | |
11254 | vars->line_speed = SPEED_10000; | |
791f18c0 | 11255 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
11256 | DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", |
11257 | val2, (val2 & (1<<14))); | |
11258 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
11259 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
9e7e8399 | 11260 | |
d231023e | 11261 | /* Read LP advertised speeds */ |
9e7e8399 MY |
11262 | if (val2 & (1<<11)) |
11263 | vars->link_status |= | |
11264 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
de6eae1f YR |
11265 | } |
11266 | return link_up; | |
11267 | } | |
6c55c3cd | 11268 | |
fcf5b650 | 11269 | static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
de6eae1f YR |
11270 | { |
11271 | if (*len < 5) | |
11272 | return -EINVAL; | |
11273 | str[0] = (spirom_ver & 0xFF); | |
11274 | str[1] = (spirom_ver & 0xFF00) >> 8; | |
11275 | str[2] = (spirom_ver & 0xFF0000) >> 16; | |
11276 | str[3] = (spirom_ver & 0xFF000000) >> 24; | |
11277 | str[4] = '\0'; | |
11278 | *len -= 5; | |
57963ed9 YR |
11279 | return 0; |
11280 | } | |
11281 | ||
de6eae1f | 11282 | void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) |
57963ed9 | 11283 | { |
de6eae1f | 11284 | u16 val, cnt; |
7aa0711f | 11285 | |
de6eae1f | 11286 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
11287 | MDIO_PMA_DEVAD, |
11288 | MDIO_PMA_REG_7101_RESET, &val); | |
57963ed9 | 11289 | |
de6eae1f YR |
11290 | for (cnt = 0; cnt < 10; cnt++) { |
11291 | msleep(50); | |
11292 | /* Writes a self-clearing reset */ | |
11293 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
11294 | MDIO_PMA_DEVAD, |
11295 | MDIO_PMA_REG_7101_RESET, | |
11296 | (val | (1<<15))); | |
de6eae1f YR |
11297 | /* Wait for clear */ |
11298 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
11299 | MDIO_PMA_DEVAD, |
11300 | MDIO_PMA_REG_7101_RESET, &val); | |
0c786f02 | 11301 | |
de6eae1f YR |
11302 | if ((val & (1<<15)) == 0) |
11303 | break; | |
57963ed9 | 11304 | } |
57963ed9 | 11305 | } |
ea4e040a | 11306 | |
de6eae1f YR |
11307 | static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, |
11308 | struct link_params *params) { | |
11309 | /* Low power mode is controlled by GPIO 2 */ | |
11310 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 11311 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
de6eae1f YR |
11312 | /* The PHY reset is controlled by GPIO 1 */ |
11313 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 11314 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
de6eae1f | 11315 | } |
ea4e040a | 11316 | |
7f02c4ad YR |
11317 | static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, |
11318 | struct link_params *params, u8 mode) | |
11319 | { | |
11320 | u16 val = 0; | |
11321 | struct bnx2x *bp = params->bp; | |
11322 | switch (mode) { | |
11323 | case LED_MODE_FRONT_PANEL_OFF: | |
11324 | case LED_MODE_OFF: | |
11325 | val = 2; | |
11326 | break; | |
11327 | case LED_MODE_ON: | |
11328 | val = 1; | |
11329 | break; | |
11330 | case LED_MODE_OPER: | |
11331 | val = 0; | |
11332 | break; | |
11333 | } | |
11334 | bnx2x_cl45_write(bp, phy, | |
11335 | MDIO_PMA_DEVAD, | |
11336 | MDIO_PMA_REG_7107_LINK_LED_CNTL, | |
11337 | val); | |
11338 | } | |
11339 | ||
de6eae1f YR |
11340 | /******************************************************************/ |
11341 | /* STATIC PHY DECLARATION */ | |
11342 | /******************************************************************/ | |
ea4e040a | 11343 | |
503976e9 | 11344 | static const struct bnx2x_phy phy_null = { |
de6eae1f YR |
11345 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, |
11346 | .addr = 0, | |
de6eae1f | 11347 | .def_md_devad = 0, |
9045f6b4 | 11348 | .flags = FLAGS_INIT_XGXS_FIRST, |
de6eae1f YR |
11349 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11350 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11351 | .mdio_ctrl = 0, | |
11352 | .supported = 0, | |
11353 | .media_type = ETH_PHY_NOT_PRESENT, | |
11354 | .ver_addr = 0, | |
cd88ccee YR |
11355 | .req_flow_ctrl = 0, |
11356 | .req_line_speed = 0, | |
11357 | .speed_cap_mask = 0, | |
de6eae1f YR |
11358 | .req_duplex = 0, |
11359 | .rsrv = 0, | |
11360 | .config_init = (config_init_t)NULL, | |
11361 | .read_status = (read_status_t)NULL, | |
11362 | .link_reset = (link_reset_t)NULL, | |
11363 | .config_loopback = (config_loopback_t)NULL, | |
11364 | .format_fw_ver = (format_fw_ver_t)NULL, | |
11365 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11366 | .set_link_led = (set_link_led_t)NULL, |
11367 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 11368 | }; |
ea4e040a | 11369 | |
503976e9 | 11370 | static const struct bnx2x_phy phy_serdes = { |
de6eae1f YR |
11371 | .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, |
11372 | .addr = 0xff, | |
de6eae1f | 11373 | .def_md_devad = 0, |
9045f6b4 | 11374 | .flags = 0, |
de6eae1f YR |
11375 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11376 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11377 | .mdio_ctrl = 0, | |
11378 | .supported = (SUPPORTED_10baseT_Half | | |
11379 | SUPPORTED_10baseT_Full | | |
11380 | SUPPORTED_100baseT_Half | | |
11381 | SUPPORTED_100baseT_Full | | |
11382 | SUPPORTED_1000baseT_Full | | |
11383 | SUPPORTED_2500baseX_Full | | |
11384 | SUPPORTED_TP | | |
11385 | SUPPORTED_Autoneg | | |
11386 | SUPPORTED_Pause | | |
11387 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11388 | .media_type = ETH_PHY_BASE_T, |
de6eae1f YR |
11389 | .ver_addr = 0, |
11390 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11391 | .req_line_speed = 0, |
11392 | .speed_cap_mask = 0, | |
de6eae1f YR |
11393 | .req_duplex = 0, |
11394 | .rsrv = 0, | |
ec146a6f | 11395 | .config_init = (config_init_t)bnx2x_xgxs_config_init, |
de6eae1f YR |
11396 | .read_status = (read_status_t)bnx2x_link_settings_status, |
11397 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
11398 | .config_loopback = (config_loopback_t)NULL, | |
11399 | .format_fw_ver = (format_fw_ver_t)NULL, | |
11400 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11401 | .set_link_led = (set_link_led_t)NULL, |
11402 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 11403 | }; |
b7737c9b | 11404 | |
503976e9 | 11405 | static const struct bnx2x_phy phy_xgxs = { |
b7737c9b YR |
11406 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, |
11407 | .addr = 0xff, | |
b7737c9b | 11408 | .def_md_devad = 0, |
9045f6b4 | 11409 | .flags = 0, |
b7737c9b YR |
11410 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11411 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11412 | .mdio_ctrl = 0, | |
11413 | .supported = (SUPPORTED_10baseT_Half | | |
11414 | SUPPORTED_10baseT_Full | | |
11415 | SUPPORTED_100baseT_Half | | |
11416 | SUPPORTED_100baseT_Full | | |
11417 | SUPPORTED_1000baseT_Full | | |
11418 | SUPPORTED_2500baseX_Full | | |
11419 | SUPPORTED_10000baseT_Full | | |
11420 | SUPPORTED_FIBRE | | |
11421 | SUPPORTED_Autoneg | | |
11422 | SUPPORTED_Pause | | |
11423 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11424 | .media_type = ETH_PHY_CX4, |
b7737c9b YR |
11425 | .ver_addr = 0, |
11426 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11427 | .req_line_speed = 0, |
11428 | .speed_cap_mask = 0, | |
b7737c9b YR |
11429 | .req_duplex = 0, |
11430 | .rsrv = 0, | |
ec146a6f | 11431 | .config_init = (config_init_t)bnx2x_xgxs_config_init, |
b7737c9b YR |
11432 | .read_status = (read_status_t)bnx2x_link_settings_status, |
11433 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
11434 | .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, | |
11435 | .format_fw_ver = (format_fw_ver_t)NULL, | |
11436 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 | 11437 | .set_link_led = (set_link_led_t)NULL, |
a75bb001 | 11438 | .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func |
b7737c9b | 11439 | }; |
503976e9 | 11440 | static const struct bnx2x_phy phy_warpcore = { |
3c9ada22 YR |
11441 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, |
11442 | .addr = 0xff, | |
11443 | .def_md_devad = 0, | |
8203c4b6 | 11444 | .flags = FLAGS_TX_ERROR_CHECK, |
3c9ada22 YR |
11445 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11446 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11447 | .mdio_ctrl = 0, | |
11448 | .supported = (SUPPORTED_10baseT_Half | | |
8f73f0b9 YR |
11449 | SUPPORTED_10baseT_Full | |
11450 | SUPPORTED_100baseT_Half | | |
11451 | SUPPORTED_100baseT_Full | | |
11452 | SUPPORTED_1000baseT_Full | | |
11453 | SUPPORTED_10000baseT_Full | | |
11454 | SUPPORTED_20000baseKR2_Full | | |
11455 | SUPPORTED_20000baseMLD2_Full | | |
11456 | SUPPORTED_FIBRE | | |
11457 | SUPPORTED_Autoneg | | |
11458 | SUPPORTED_Pause | | |
11459 | SUPPORTED_Asym_Pause), | |
3c9ada22 YR |
11460 | .media_type = ETH_PHY_UNSPECIFIED, |
11461 | .ver_addr = 0, | |
11462 | .req_flow_ctrl = 0, | |
11463 | .req_line_speed = 0, | |
11464 | .speed_cap_mask = 0, | |
11465 | /* req_duplex = */0, | |
11466 | /* rsrv = */0, | |
11467 | .config_init = (config_init_t)bnx2x_warpcore_config_init, | |
11468 | .read_status = (read_status_t)bnx2x_warpcore_read_status, | |
11469 | .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, | |
11470 | .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, | |
11471 | .format_fw_ver = (format_fw_ver_t)NULL, | |
985848f8 | 11472 | .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, |
3c9ada22 YR |
11473 | .set_link_led = (set_link_led_t)NULL, |
11474 | .phy_specific_func = (phy_specific_func_t)NULL | |
11475 | }; | |
11476 | ||
b7737c9b | 11477 | |
503976e9 | 11478 | static const struct bnx2x_phy phy_7101 = { |
b7737c9b YR |
11479 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, |
11480 | .addr = 0xff, | |
b7737c9b | 11481 | .def_md_devad = 0, |
9045f6b4 | 11482 | .flags = FLAGS_FAN_FAILURE_DET_REQ, |
b7737c9b YR |
11483 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11484 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11485 | .mdio_ctrl = 0, | |
11486 | .supported = (SUPPORTED_10000baseT_Full | | |
11487 | SUPPORTED_TP | | |
11488 | SUPPORTED_Autoneg | | |
11489 | SUPPORTED_Pause | | |
11490 | SUPPORTED_Asym_Pause), | |
11491 | .media_type = ETH_PHY_BASE_T, | |
11492 | .ver_addr = 0, | |
11493 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11494 | .req_line_speed = 0, |
11495 | .speed_cap_mask = 0, | |
b7737c9b YR |
11496 | .req_duplex = 0, |
11497 | .rsrv = 0, | |
11498 | .config_init = (config_init_t)bnx2x_7101_config_init, | |
11499 | .read_status = (read_status_t)bnx2x_7101_read_status, | |
11500 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11501 | .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, | |
11502 | .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, | |
11503 | .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, | |
7f02c4ad | 11504 | .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, |
a22f0788 | 11505 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b | 11506 | }; |
503976e9 | 11507 | static const struct bnx2x_phy phy_8073 = { |
b7737c9b YR |
11508 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, |
11509 | .addr = 0xff, | |
b7737c9b | 11510 | .def_md_devad = 0, |
8203c4b6 | 11511 | .flags = 0, |
b7737c9b YR |
11512 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11513 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11514 | .mdio_ctrl = 0, | |
11515 | .supported = (SUPPORTED_10000baseT_Full | | |
11516 | SUPPORTED_2500baseX_Full | | |
11517 | SUPPORTED_1000baseT_Full | | |
11518 | SUPPORTED_FIBRE | | |
11519 | SUPPORTED_Autoneg | | |
11520 | SUPPORTED_Pause | | |
11521 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11522 | .media_type = ETH_PHY_KR, |
b7737c9b | 11523 | .ver_addr = 0, |
cd88ccee YR |
11524 | .req_flow_ctrl = 0, |
11525 | .req_line_speed = 0, | |
11526 | .speed_cap_mask = 0, | |
b7737c9b YR |
11527 | .req_duplex = 0, |
11528 | .rsrv = 0, | |
62b29a5d | 11529 | .config_init = (config_init_t)bnx2x_8073_config_init, |
b7737c9b YR |
11530 | .read_status = (read_status_t)bnx2x_8073_read_status, |
11531 | .link_reset = (link_reset_t)bnx2x_8073_link_reset, | |
11532 | .config_loopback = (config_loopback_t)NULL, | |
11533 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11534 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 | 11535 | .set_link_led = (set_link_led_t)NULL, |
5c107fda | 11536 | .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func |
b7737c9b | 11537 | }; |
503976e9 | 11538 | static const struct bnx2x_phy phy_8705 = { |
b7737c9b YR |
11539 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, |
11540 | .addr = 0xff, | |
b7737c9b | 11541 | .def_md_devad = 0, |
9045f6b4 | 11542 | .flags = FLAGS_INIT_XGXS_FIRST, |
b7737c9b YR |
11543 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11544 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11545 | .mdio_ctrl = 0, | |
11546 | .supported = (SUPPORTED_10000baseT_Full | | |
11547 | SUPPORTED_FIBRE | | |
11548 | SUPPORTED_Pause | | |
11549 | SUPPORTED_Asym_Pause), | |
11550 | .media_type = ETH_PHY_XFP_FIBER, | |
11551 | .ver_addr = 0, | |
11552 | .req_flow_ctrl = 0, | |
11553 | .req_line_speed = 0, | |
11554 | .speed_cap_mask = 0, | |
11555 | .req_duplex = 0, | |
11556 | .rsrv = 0, | |
11557 | .config_init = (config_init_t)bnx2x_8705_config_init, | |
11558 | .read_status = (read_status_t)bnx2x_8705_read_status, | |
11559 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11560 | .config_loopback = (config_loopback_t)NULL, | |
11561 | .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, | |
11562 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11563 | .set_link_led = (set_link_led_t)NULL, |
11564 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b | 11565 | }; |
503976e9 | 11566 | static const struct bnx2x_phy phy_8706 = { |
b7737c9b YR |
11567 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, |
11568 | .addr = 0xff, | |
b7737c9b | 11569 | .def_md_devad = 0, |
05822420 | 11570 | .flags = FLAGS_INIT_XGXS_FIRST, |
b7737c9b YR |
11571 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11572 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11573 | .mdio_ctrl = 0, | |
11574 | .supported = (SUPPORTED_10000baseT_Full | | |
11575 | SUPPORTED_1000baseT_Full | | |
11576 | SUPPORTED_FIBRE | | |
11577 | SUPPORTED_Pause | | |
11578 | SUPPORTED_Asym_Pause), | |
dbef807e | 11579 | .media_type = ETH_PHY_SFPP_10G_FIBER, |
b7737c9b YR |
11580 | .ver_addr = 0, |
11581 | .req_flow_ctrl = 0, | |
11582 | .req_line_speed = 0, | |
11583 | .speed_cap_mask = 0, | |
11584 | .req_duplex = 0, | |
11585 | .rsrv = 0, | |
11586 | .config_init = (config_init_t)bnx2x_8706_config_init, | |
11587 | .read_status = (read_status_t)bnx2x_8706_read_status, | |
11588 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11589 | .config_loopback = (config_loopback_t)NULL, | |
11590 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11591 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11592 | .set_link_led = (set_link_led_t)NULL, |
11593 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11594 | }; |
11595 | ||
503976e9 | 11596 | static const struct bnx2x_phy phy_8726 = { |
b7737c9b YR |
11597 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, |
11598 | .addr = 0xff, | |
9045f6b4 | 11599 | .def_md_devad = 0, |
8203c4b6 | 11600 | .flags = (FLAGS_INIT_XGXS_FIRST | |
55098c5c | 11601 | FLAGS_TX_ERROR_CHECK), |
b7737c9b YR |
11602 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11603 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11604 | .mdio_ctrl = 0, | |
11605 | .supported = (SUPPORTED_10000baseT_Full | | |
11606 | SUPPORTED_1000baseT_Full | | |
11607 | SUPPORTED_Autoneg | | |
11608 | SUPPORTED_FIBRE | | |
11609 | SUPPORTED_Pause | | |
11610 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11611 | .media_type = ETH_PHY_NOT_PRESENT, |
b7737c9b YR |
11612 | .ver_addr = 0, |
11613 | .req_flow_ctrl = 0, | |
11614 | .req_line_speed = 0, | |
11615 | .speed_cap_mask = 0, | |
11616 | .req_duplex = 0, | |
11617 | .rsrv = 0, | |
11618 | .config_init = (config_init_t)bnx2x_8726_config_init, | |
11619 | .read_status = (read_status_t)bnx2x_8726_read_status, | |
11620 | .link_reset = (link_reset_t)bnx2x_8726_link_reset, | |
11621 | .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, | |
11622 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11623 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11624 | .set_link_led = (set_link_led_t)NULL, |
11625 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11626 | }; |
11627 | ||
503976e9 | 11628 | static const struct bnx2x_phy phy_8727 = { |
b7737c9b YR |
11629 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, |
11630 | .addr = 0xff, | |
b7737c9b | 11631 | .def_md_devad = 0, |
55098c5c YR |
11632 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11633 | FLAGS_TX_ERROR_CHECK), | |
b7737c9b YR |
11634 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11635 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11636 | .mdio_ctrl = 0, | |
11637 | .supported = (SUPPORTED_10000baseT_Full | | |
11638 | SUPPORTED_1000baseT_Full | | |
b7737c9b YR |
11639 | SUPPORTED_FIBRE | |
11640 | SUPPORTED_Pause | | |
11641 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11642 | .media_type = ETH_PHY_NOT_PRESENT, |
b7737c9b YR |
11643 | .ver_addr = 0, |
11644 | .req_flow_ctrl = 0, | |
11645 | .req_line_speed = 0, | |
11646 | .speed_cap_mask = 0, | |
11647 | .req_duplex = 0, | |
11648 | .rsrv = 0, | |
11649 | .config_init = (config_init_t)bnx2x_8727_config_init, | |
11650 | .read_status = (read_status_t)bnx2x_8727_read_status, | |
11651 | .link_reset = (link_reset_t)bnx2x_8727_link_reset, | |
11652 | .config_loopback = (config_loopback_t)NULL, | |
11653 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11654 | .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, | |
7f02c4ad | 11655 | .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, |
a22f0788 | 11656 | .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func |
b7737c9b | 11657 | }; |
503976e9 | 11658 | static const struct bnx2x_phy phy_8481 = { |
b7737c9b YR |
11659 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, |
11660 | .addr = 0xff, | |
9045f6b4 | 11661 | .def_md_devad = 0, |
a22f0788 YR |
11662 | .flags = FLAGS_FAN_FAILURE_DET_REQ | |
11663 | FLAGS_REARM_LATCH_SIGNAL, | |
b7737c9b YR |
11664 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11665 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11666 | .mdio_ctrl = 0, | |
11667 | .supported = (SUPPORTED_10baseT_Half | | |
11668 | SUPPORTED_10baseT_Full | | |
11669 | SUPPORTED_100baseT_Half | | |
11670 | SUPPORTED_100baseT_Full | | |
11671 | SUPPORTED_1000baseT_Full | | |
11672 | SUPPORTED_10000baseT_Full | | |
11673 | SUPPORTED_TP | | |
11674 | SUPPORTED_Autoneg | | |
11675 | SUPPORTED_Pause | | |
11676 | SUPPORTED_Asym_Pause), | |
11677 | .media_type = ETH_PHY_BASE_T, | |
11678 | .ver_addr = 0, | |
11679 | .req_flow_ctrl = 0, | |
11680 | .req_line_speed = 0, | |
11681 | .speed_cap_mask = 0, | |
11682 | .req_duplex = 0, | |
11683 | .rsrv = 0, | |
11684 | .config_init = (config_init_t)bnx2x_8481_config_init, | |
11685 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11686 | .link_reset = (link_reset_t)bnx2x_8481_link_reset, | |
11687 | .config_loopback = (config_loopback_t)NULL, | |
11688 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
11689 | .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, | |
7f02c4ad | 11690 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
a22f0788 | 11691 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b YR |
11692 | }; |
11693 | ||
503976e9 | 11694 | static const struct bnx2x_phy phy_84823 = { |
de6eae1f YR |
11695 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, |
11696 | .addr = 0xff, | |
9045f6b4 | 11697 | .def_md_devad = 0, |
55098c5c YR |
11698 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11699 | FLAGS_REARM_LATCH_SIGNAL | | |
11700 | FLAGS_TX_ERROR_CHECK), | |
de6eae1f YR |
11701 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11702 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11703 | .mdio_ctrl = 0, | |
11704 | .supported = (SUPPORTED_10baseT_Half | | |
11705 | SUPPORTED_10baseT_Full | | |
11706 | SUPPORTED_100baseT_Half | | |
11707 | SUPPORTED_100baseT_Full | | |
11708 | SUPPORTED_1000baseT_Full | | |
11709 | SUPPORTED_10000baseT_Full | | |
11710 | SUPPORTED_TP | | |
11711 | SUPPORTED_Autoneg | | |
11712 | SUPPORTED_Pause | | |
11713 | SUPPORTED_Asym_Pause), | |
11714 | .media_type = ETH_PHY_BASE_T, | |
11715 | .ver_addr = 0, | |
11716 | .req_flow_ctrl = 0, | |
11717 | .req_line_speed = 0, | |
11718 | .speed_cap_mask = 0, | |
11719 | .req_duplex = 0, | |
11720 | .rsrv = 0, | |
11721 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
11722 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11723 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
11724 | .config_loopback = (config_loopback_t)NULL, | |
11725 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
11726 | .hw_reset = (hw_reset_t)NULL, | |
7f02c4ad | 11727 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
5c107fda | 11728 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func |
de6eae1f YR |
11729 | }; |
11730 | ||
503976e9 | 11731 | static const struct bnx2x_phy phy_84833 = { |
c87bca1e YR |
11732 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, |
11733 | .addr = 0xff, | |
9045f6b4 | 11734 | .def_md_devad = 0, |
55098c5c YR |
11735 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11736 | FLAGS_REARM_LATCH_SIGNAL | | |
f6b6eb69 | 11737 | FLAGS_TX_ERROR_CHECK), |
c87bca1e YR |
11738 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11739 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11740 | .mdio_ctrl = 0, | |
0520e63a | 11741 | .supported = (SUPPORTED_100baseT_Half | |
c87bca1e YR |
11742 | SUPPORTED_100baseT_Full | |
11743 | SUPPORTED_1000baseT_Full | | |
11744 | SUPPORTED_10000baseT_Full | | |
11745 | SUPPORTED_TP | | |
11746 | SUPPORTED_Autoneg | | |
11747 | SUPPORTED_Pause | | |
11748 | SUPPORTED_Asym_Pause), | |
11749 | .media_type = ETH_PHY_BASE_T, | |
11750 | .ver_addr = 0, | |
11751 | .req_flow_ctrl = 0, | |
11752 | .req_line_speed = 0, | |
11753 | .speed_cap_mask = 0, | |
11754 | .req_duplex = 0, | |
11755 | .rsrv = 0, | |
11756 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
11757 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11758 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
11759 | .config_loopback = (config_loopback_t)NULL, | |
11760 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
985848f8 | 11761 | .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, |
c87bca1e | 11762 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
5c107fda | 11763 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func |
c87bca1e YR |
11764 | }; |
11765 | ||
0f6bb03d YR |
11766 | static const struct bnx2x_phy phy_84834 = { |
11767 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, | |
11768 | .addr = 0xff, | |
11769 | .def_md_devad = 0, | |
11770 | .flags = FLAGS_FAN_FAILURE_DET_REQ | | |
11771 | FLAGS_REARM_LATCH_SIGNAL, | |
11772 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11773 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11774 | .mdio_ctrl = 0, | |
11775 | .supported = (SUPPORTED_100baseT_Half | | |
11776 | SUPPORTED_100baseT_Full | | |
11777 | SUPPORTED_1000baseT_Full | | |
11778 | SUPPORTED_10000baseT_Full | | |
11779 | SUPPORTED_TP | | |
11780 | SUPPORTED_Autoneg | | |
11781 | SUPPORTED_Pause | | |
11782 | SUPPORTED_Asym_Pause), | |
11783 | .media_type = ETH_PHY_BASE_T, | |
11784 | .ver_addr = 0, | |
11785 | .req_flow_ctrl = 0, | |
11786 | .req_line_speed = 0, | |
11787 | .speed_cap_mask = 0, | |
11788 | .req_duplex = 0, | |
11789 | .rsrv = 0, | |
11790 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
11791 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11792 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
11793 | .config_loopback = (config_loopback_t)NULL, | |
11794 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
11795 | .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, | |
11796 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, | |
11797 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func | |
11798 | }; | |
11799 | ||
503976e9 | 11800 | static const struct bnx2x_phy phy_54618se = { |
52c4d6c4 | 11801 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, |
6583e33b YR |
11802 | .addr = 0xff, |
11803 | .def_md_devad = 0, | |
11804 | .flags = FLAGS_INIT_XGXS_FIRST, | |
11805 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11806 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11807 | .mdio_ctrl = 0, | |
11808 | .supported = (SUPPORTED_10baseT_Half | | |
11809 | SUPPORTED_10baseT_Full | | |
11810 | SUPPORTED_100baseT_Half | | |
11811 | SUPPORTED_100baseT_Full | | |
11812 | SUPPORTED_1000baseT_Full | | |
11813 | SUPPORTED_TP | | |
11814 | SUPPORTED_Autoneg | | |
11815 | SUPPORTED_Pause | | |
11816 | SUPPORTED_Asym_Pause), | |
11817 | .media_type = ETH_PHY_BASE_T, | |
11818 | .ver_addr = 0, | |
11819 | .req_flow_ctrl = 0, | |
11820 | .req_line_speed = 0, | |
11821 | .speed_cap_mask = 0, | |
11822 | /* req_duplex = */0, | |
11823 | /* rsrv = */0, | |
52c4d6c4 YR |
11824 | .config_init = (config_init_t)bnx2x_54618se_config_init, |
11825 | .read_status = (read_status_t)bnx2x_54618se_read_status, | |
11826 | .link_reset = (link_reset_t)bnx2x_54618se_link_reset, | |
11827 | .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, | |
6583e33b YR |
11828 | .format_fw_ver = (format_fw_ver_t)NULL, |
11829 | .hw_reset = (hw_reset_t)NULL, | |
1d125bd5 | 11830 | .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, |
5c107fda | 11831 | .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func |
6583e33b | 11832 | }; |
de6eae1f YR |
11833 | /*****************************************************************/ |
11834 | /* */ | |
11835 | /* Populate the phy according. Main function: bnx2x_populate_phy */ | |
11836 | /* */ | |
11837 | /*****************************************************************/ | |
11838 | ||
11839 | static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, | |
11840 | struct bnx2x_phy *phy, u8 port, | |
11841 | u8 phy_index) | |
11842 | { | |
11843 | /* Get the 4 lanes xgxs config rx and tx */ | |
11844 | u32 rx = 0, tx = 0, i; | |
11845 | for (i = 0; i < 2; i++) { | |
8f73f0b9 YR |
11846 | /* INT_PHY and EXT_PHY1 share the same value location in |
11847 | * the shmem. When num_phys is greater than 1, than this value | |
de6eae1f YR |
11848 | * applies only to EXT_PHY1 |
11849 | */ | |
a22f0788 YR |
11850 | if (phy_index == INT_PHY || phy_index == EXT_PHY1) { |
11851 | rx = REG_RD(bp, shmem_base + | |
11852 | offsetof(struct shmem_region, | |
cd88ccee | 11853 | dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); |
a22f0788 YR |
11854 | |
11855 | tx = REG_RD(bp, shmem_base + | |
11856 | offsetof(struct shmem_region, | |
cd88ccee | 11857 | dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); |
a22f0788 YR |
11858 | } else { |
11859 | rx = REG_RD(bp, shmem_base + | |
11860 | offsetof(struct shmem_region, | |
cd88ccee | 11861 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
de6eae1f | 11862 | |
a22f0788 YR |
11863 | tx = REG_RD(bp, shmem_base + |
11864 | offsetof(struct shmem_region, | |
cd88ccee | 11865 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
a22f0788 | 11866 | } |
de6eae1f YR |
11867 | |
11868 | phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); | |
11869 | phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); | |
11870 | ||
11871 | phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); | |
11872 | phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); | |
11873 | } | |
11874 | } | |
11875 | ||
11876 | static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, | |
11877 | u8 phy_index, u8 port) | |
11878 | { | |
11879 | u32 ext_phy_config = 0; | |
11880 | switch (phy_index) { | |
11881 | case EXT_PHY1: | |
11882 | ext_phy_config = REG_RD(bp, shmem_base + | |
11883 | offsetof(struct shmem_region, | |
11884 | dev_info.port_hw_config[port].external_phy_config)); | |
11885 | break; | |
a22f0788 YR |
11886 | case EXT_PHY2: |
11887 | ext_phy_config = REG_RD(bp, shmem_base + | |
11888 | offsetof(struct shmem_region, | |
11889 | dev_info.port_hw_config[port].external_phy_config2)); | |
11890 | break; | |
de6eae1f YR |
11891 | default: |
11892 | DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); | |
11893 | return -EINVAL; | |
11894 | } | |
11895 | ||
11896 | return ext_phy_config; | |
11897 | } | |
fcf5b650 YR |
11898 | static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, |
11899 | struct bnx2x_phy *phy) | |
de6eae1f YR |
11900 | { |
11901 | u32 phy_addr; | |
11902 | u32 chip_id; | |
11903 | u32 switch_cfg = (REG_RD(bp, shmem_base + | |
11904 | offsetof(struct shmem_region, | |
11905 | dev_info.port_feature_config[port].link_config)) & | |
11906 | PORT_FEATURE_CONNECTED_SWITCH_MASK); | |
ec15b898 YR |
11907 | chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | |
11908 | ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); | |
11909 | ||
3c9ada22 YR |
11910 | DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); |
11911 | if (USES_WARPCORE(bp)) { | |
11912 | u32 serdes_net_if; | |
de6eae1f | 11913 | phy_addr = REG_RD(bp, |
3c9ada22 YR |
11914 | MISC_REG_WC0_CTRL_PHY_ADDR); |
11915 | *phy = phy_warpcore; | |
11916 | if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) | |
11917 | phy->flags |= FLAGS_4_PORT_MODE; | |
11918 | else | |
11919 | phy->flags &= ~FLAGS_4_PORT_MODE; | |
11920 | /* Check Dual mode */ | |
11921 | serdes_net_if = (REG_RD(bp, shmem_base + | |
11922 | offsetof(struct shmem_region, dev_info. | |
11923 | port_hw_config[port].default_cfg)) & | |
11924 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
8f73f0b9 | 11925 | /* Set the appropriate supported and flags indications per |
3c9ada22 YR |
11926 | * interface type of the chip |
11927 | */ | |
11928 | switch (serdes_net_if) { | |
11929 | case PORT_HW_CFG_NET_SERDES_IF_SGMII: | |
11930 | phy->supported &= (SUPPORTED_10baseT_Half | | |
11931 | SUPPORTED_10baseT_Full | | |
11932 | SUPPORTED_100baseT_Half | | |
11933 | SUPPORTED_100baseT_Full | | |
11934 | SUPPORTED_1000baseT_Full | | |
11935 | SUPPORTED_FIBRE | | |
11936 | SUPPORTED_Autoneg | | |
11937 | SUPPORTED_Pause | | |
11938 | SUPPORTED_Asym_Pause); | |
11939 | phy->media_type = ETH_PHY_BASE_T; | |
11940 | break; | |
11941 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | |
03c31488 YR |
11942 | phy->supported &= (SUPPORTED_1000baseT_Full | |
11943 | SUPPORTED_10000baseT_Full | | |
11944 | SUPPORTED_FIBRE | | |
11945 | SUPPORTED_Pause | | |
11946 | SUPPORTED_Asym_Pause); | |
3c9ada22 YR |
11947 | phy->media_type = ETH_PHY_XFP_FIBER; |
11948 | break; | |
11949 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | |
11950 | phy->supported &= (SUPPORTED_1000baseT_Full | | |
11951 | SUPPORTED_10000baseT_Full | | |
11952 | SUPPORTED_FIBRE | | |
11953 | SUPPORTED_Pause | | |
11954 | SUPPORTED_Asym_Pause); | |
dbef807e | 11955 | phy->media_type = ETH_PHY_SFPP_10G_FIBER; |
3c9ada22 YR |
11956 | break; |
11957 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
11958 | phy->media_type = ETH_PHY_KR; | |
11959 | phy->supported &= (SUPPORTED_1000baseT_Full | | |
11960 | SUPPORTED_10000baseT_Full | | |
11961 | SUPPORTED_FIBRE | | |
11962 | SUPPORTED_Autoneg | | |
11963 | SUPPORTED_Pause | | |
11964 | SUPPORTED_Asym_Pause); | |
11965 | break; | |
11966 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: | |
11967 | phy->media_type = ETH_PHY_KR; | |
11968 | phy->flags |= FLAGS_WC_DUAL_MODE; | |
11969 | phy->supported &= (SUPPORTED_20000baseMLD2_Full | | |
11970 | SUPPORTED_FIBRE | | |
11971 | SUPPORTED_Pause | | |
11972 | SUPPORTED_Asym_Pause); | |
11973 | break; | |
11974 | case PORT_HW_CFG_NET_SERDES_IF_KR2: | |
11975 | phy->media_type = ETH_PHY_KR; | |
11976 | phy->flags |= FLAGS_WC_DUAL_MODE; | |
11977 | phy->supported &= (SUPPORTED_20000baseKR2_Full | | |
be94bea7 YR |
11978 | SUPPORTED_10000baseT_Full | |
11979 | SUPPORTED_1000baseT_Full | | |
4e7b4997 | 11980 | SUPPORTED_Autoneg | |
3c9ada22 YR |
11981 | SUPPORTED_FIBRE | |
11982 | SUPPORTED_Pause | | |
11983 | SUPPORTED_Asym_Pause); | |
4e7b4997 | 11984 | phy->flags &= ~FLAGS_TX_ERROR_CHECK; |
3c9ada22 YR |
11985 | break; |
11986 | default: | |
11987 | DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", | |
11988 | serdes_net_if); | |
11989 | break; | |
11990 | } | |
11991 | ||
8f73f0b9 | 11992 | /* Enable MDC/MDIO work-around for E3 A0 since free running MDC |
3c9ada22 YR |
11993 | * was not set as expected. For B0, ECO will be enabled so there |
11994 | * won't be an issue there | |
11995 | */ | |
11996 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
11997 | phy->flags |= FLAGS_MDC_MDIO_WA; | |
157fa283 YR |
11998 | else |
11999 | phy->flags |= FLAGS_MDC_MDIO_WA_B0; | |
3c9ada22 YR |
12000 | } else { |
12001 | switch (switch_cfg) { | |
12002 | case SWITCH_CFG_1G: | |
12003 | phy_addr = REG_RD(bp, | |
12004 | NIG_REG_SERDES0_CTRL_PHY_ADDR + | |
12005 | port * 0x10); | |
12006 | *phy = phy_serdes; | |
12007 | break; | |
12008 | case SWITCH_CFG_10G: | |
12009 | phy_addr = REG_RD(bp, | |
12010 | NIG_REG_XGXS0_CTRL_PHY_ADDR + | |
12011 | port * 0x18); | |
12012 | *phy = phy_xgxs; | |
12013 | break; | |
12014 | default: | |
12015 | DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); | |
12016 | return -EINVAL; | |
12017 | } | |
de6eae1f YR |
12018 | } |
12019 | phy->addr = (u8)phy_addr; | |
12020 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, | |
12021 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, | |
12022 | port); | |
f2e0899f DK |
12023 | if (CHIP_IS_E2(bp)) |
12024 | phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; | |
12025 | else | |
12026 | phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; | |
de6eae1f YR |
12027 | |
12028 | DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", | |
12029 | port, phy->addr, phy->mdio_ctrl); | |
12030 | ||
12031 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); | |
12032 | return 0; | |
12033 | } | |
12034 | ||
fcf5b650 YR |
12035 | static int bnx2x_populate_ext_phy(struct bnx2x *bp, |
12036 | u8 phy_index, | |
12037 | u32 shmem_base, | |
12038 | u32 shmem2_base, | |
12039 | u8 port, | |
12040 | struct bnx2x_phy *phy) | |
de6eae1f YR |
12041 | { |
12042 | u32 ext_phy_config, phy_type, config2; | |
12043 | u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; | |
12044 | ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, | |
12045 | phy_index, port); | |
12046 | phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
12047 | /* Select the phy type */ | |
12048 | switch (phy_type) { | |
12049 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
12050 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; | |
12051 | *phy = phy_8073; | |
12052 | break; | |
12053 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | |
12054 | *phy = phy_8705; | |
12055 | break; | |
12056 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | |
12057 | *phy = phy_8706; | |
12058 | break; | |
12059 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
12060 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
12061 | *phy = phy_8726; | |
12062 | break; | |
12063 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
12064 | /* BCM8727_NOC => BCM8727 no over current */ | |
12065 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
12066 | *phy = phy_8727; | |
12067 | phy->flags |= FLAGS_NOC; | |
12068 | break; | |
e4d78f12 | 12069 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
de6eae1f YR |
12070 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
12071 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
12072 | *phy = phy_8727; | |
12073 | break; | |
12074 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: | |
12075 | *phy = phy_8481; | |
12076 | break; | |
12077 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | |
12078 | *phy = phy_84823; | |
12079 | break; | |
c87bca1e YR |
12080 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
12081 | *phy = phy_84833; | |
12082 | break; | |
0f6bb03d YR |
12083 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: |
12084 | *phy = phy_84834; | |
12085 | break; | |
3756a89f | 12086 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: |
52c4d6c4 YR |
12087 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: |
12088 | *phy = phy_54618se; | |
26964bb7 YM |
12089 | if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
12090 | phy->flags |= FLAGS_EEE; | |
6583e33b | 12091 | break; |
de6eae1f YR |
12092 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: |
12093 | *phy = phy_7101; | |
12094 | break; | |
12095 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: | |
12096 | *phy = phy_null; | |
12097 | return -EINVAL; | |
12098 | default: | |
12099 | *phy = phy_null; | |
6db5193b YR |
12100 | /* In case external PHY wasn't found */ |
12101 | if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && | |
12102 | (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
12103 | return -EINVAL; | |
de6eae1f YR |
12104 | return 0; |
12105 | } | |
12106 | ||
12107 | phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); | |
12108 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); | |
12109 | ||
8f73f0b9 | 12110 | /* The shmem address of the phy version is located on different |
2cf7acf9 YR |
12111 | * structures. In case this structure is too old, do not set |
12112 | * the address | |
12113 | */ | |
de6eae1f YR |
12114 | config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, |
12115 | dev_info.shared_hw_config.config2)); | |
a22f0788 YR |
12116 | if (phy_index == EXT_PHY1) { |
12117 | phy->ver_addr = shmem_base + offsetof(struct shmem_region, | |
12118 | port_mb[port].ext_phy_fw_version); | |
de6eae1f | 12119 | |
cd88ccee YR |
12120 | /* Check specific mdc mdio settings */ |
12121 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) | |
12122 | mdc_mdio_access = config2 & | |
12123 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; | |
a22f0788 YR |
12124 | } else { |
12125 | u32 size = REG_RD(bp, shmem2_base); | |
de6eae1f | 12126 | |
a22f0788 YR |
12127 | if (size > |
12128 | offsetof(struct shmem2_region, ext_phy_fw_version2)) { | |
12129 | phy->ver_addr = shmem2_base + | |
12130 | offsetof(struct shmem2_region, | |
12131 | ext_phy_fw_version2[port]); | |
12132 | } | |
12133 | /* Check specific mdc mdio settings */ | |
12134 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) | |
12135 | mdc_mdio_access = (config2 & | |
12136 | SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> | |
12137 | (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - | |
12138 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); | |
12139 | } | |
de6eae1f YR |
12140 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); |
12141 | ||
0f6bb03d YR |
12142 | if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
12143 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && | |
75318327 | 12144 | (phy->ver_addr)) { |
0f6bb03d | 12145 | /* Remove 100Mb link supported for BCM84833/4 when phy fw |
75318327 YR |
12146 | * version lower than or equal to 1.39 |
12147 | */ | |
12148 | u32 raw_ver = REG_RD(bp, phy->ver_addr); | |
12149 | if (((raw_ver & 0x7F) <= 39) && | |
12150 | (((raw_ver & 0xF80) >> 7) <= 1)) | |
12151 | phy->supported &= ~(SUPPORTED_100baseT_Half | | |
12152 | SUPPORTED_100baseT_Full); | |
12153 | } | |
12154 | ||
de6eae1f YR |
12155 | DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", |
12156 | phy_type, port, phy_index); | |
12157 | DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", | |
12158 | phy->addr, phy->mdio_ctrl); | |
12159 | return 0; | |
12160 | } | |
12161 | ||
fcf5b650 YR |
12162 | static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, |
12163 | u32 shmem2_base, u8 port, struct bnx2x_phy *phy) | |
de6eae1f | 12164 | { |
fcf5b650 | 12165 | int status = 0; |
de6eae1f YR |
12166 | phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; |
12167 | if (phy_index == INT_PHY) | |
12168 | return bnx2x_populate_int_phy(bp, shmem_base, port, phy); | |
a22f0788 | 12169 | status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
12170 | port, phy); |
12171 | return status; | |
12172 | } | |
12173 | ||
12174 | static void bnx2x_phy_def_cfg(struct link_params *params, | |
12175 | struct bnx2x_phy *phy, | |
a22f0788 | 12176 | u8 phy_index) |
de6eae1f YR |
12177 | { |
12178 | struct bnx2x *bp = params->bp; | |
12179 | u32 link_config; | |
12180 | /* Populate the default phy configuration for MF mode */ | |
a22f0788 YR |
12181 | if (phy_index == EXT_PHY2) { |
12182 | link_config = REG_RD(bp, params->shmem_base + | |
cd88ccee | 12183 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
12184 | port_feature_config[params->port].link_config2)); |
12185 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
12186 | offsetof(struct shmem_region, |
12187 | dev_info. | |
a22f0788 YR |
12188 | port_hw_config[params->port].speed_capability_mask2)); |
12189 | } else { | |
12190 | link_config = REG_RD(bp, params->shmem_base + | |
cd88ccee | 12191 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
12192 | port_feature_config[params->port].link_config)); |
12193 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
12194 | offsetof(struct shmem_region, |
12195 | dev_info. | |
12196 | port_hw_config[params->port].speed_capability_mask)); | |
a22f0788 | 12197 | } |
94f05b0f JP |
12198 | DP(NETIF_MSG_LINK, |
12199 | "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", | |
12200 | phy_index, link_config, phy->speed_cap_mask); | |
de6eae1f YR |
12201 | |
12202 | phy->req_duplex = DUPLEX_FULL; | |
12203 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
12204 | case PORT_FEATURE_LINK_SPEED_10M_HALF: | |
12205 | phy->req_duplex = DUPLEX_HALF; | |
12206 | case PORT_FEATURE_LINK_SPEED_10M_FULL: | |
12207 | phy->req_line_speed = SPEED_10; | |
12208 | break; | |
12209 | case PORT_FEATURE_LINK_SPEED_100M_HALF: | |
12210 | phy->req_duplex = DUPLEX_HALF; | |
12211 | case PORT_FEATURE_LINK_SPEED_100M_FULL: | |
12212 | phy->req_line_speed = SPEED_100; | |
12213 | break; | |
12214 | case PORT_FEATURE_LINK_SPEED_1G: | |
12215 | phy->req_line_speed = SPEED_1000; | |
12216 | break; | |
12217 | case PORT_FEATURE_LINK_SPEED_2_5G: | |
12218 | phy->req_line_speed = SPEED_2500; | |
12219 | break; | |
12220 | case PORT_FEATURE_LINK_SPEED_10G_CX4: | |
12221 | phy->req_line_speed = SPEED_10000; | |
12222 | break; | |
12223 | default: | |
12224 | phy->req_line_speed = SPEED_AUTO_NEG; | |
12225 | break; | |
12226 | } | |
12227 | ||
12228 | switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { | |
12229 | case PORT_FEATURE_FLOW_CONTROL_AUTO: | |
12230 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; | |
12231 | break; | |
12232 | case PORT_FEATURE_FLOW_CONTROL_TX: | |
12233 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; | |
12234 | break; | |
12235 | case PORT_FEATURE_FLOW_CONTROL_RX: | |
12236 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; | |
12237 | break; | |
12238 | case PORT_FEATURE_FLOW_CONTROL_BOTH: | |
12239 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; | |
12240 | break; | |
12241 | default: | |
12242 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12243 | break; | |
12244 | } | |
12245 | } | |
12246 | ||
a22f0788 YR |
12247 | u32 bnx2x_phy_selection(struct link_params *params) |
12248 | { | |
12249 | u32 phy_config_swapped, prio_cfg; | |
12250 | u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; | |
12251 | ||
12252 | phy_config_swapped = params->multi_phy_config & | |
12253 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
12254 | ||
12255 | prio_cfg = params->multi_phy_config & | |
12256 | PORT_HW_CFG_PHY_SELECTION_MASK; | |
12257 | ||
12258 | if (phy_config_swapped) { | |
12259 | switch (prio_cfg) { | |
12260 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
12261 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; | |
12262 | break; | |
12263 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
12264 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; | |
12265 | break; | |
12266 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
12267 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
12268 | break; | |
12269 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
12270 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
12271 | break; | |
12272 | } | |
12273 | } else | |
12274 | return_cfg = prio_cfg; | |
12275 | ||
12276 | return return_cfg; | |
12277 | } | |
12278 | ||
fcf5b650 | 12279 | int bnx2x_phy_probe(struct link_params *params) |
de6eae1f | 12280 | { |
2f751a80 | 12281 | u8 phy_index, actual_phy_idx; |
1ac9e428 | 12282 | u32 phy_config_swapped, sync_offset, media_types; |
de6eae1f YR |
12283 | struct bnx2x *bp = params->bp; |
12284 | struct bnx2x_phy *phy; | |
12285 | params->num_phys = 0; | |
12286 | DP(NETIF_MSG_LINK, "Begin phy probe\n"); | |
a22f0788 YR |
12287 | phy_config_swapped = params->multi_phy_config & |
12288 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
de6eae1f YR |
12289 | |
12290 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
12291 | phy_index++) { | |
de6eae1f | 12292 | actual_phy_idx = phy_index; |
a22f0788 YR |
12293 | if (phy_config_swapped) { |
12294 | if (phy_index == EXT_PHY1) | |
12295 | actual_phy_idx = EXT_PHY2; | |
12296 | else if (phy_index == EXT_PHY2) | |
12297 | actual_phy_idx = EXT_PHY1; | |
12298 | } | |
12299 | DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," | |
12300 | " actual_phy_idx %x\n", phy_config_swapped, | |
12301 | phy_index, actual_phy_idx); | |
de6eae1f YR |
12302 | phy = ¶ms->phy[actual_phy_idx]; |
12303 | if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, | |
a22f0788 | 12304 | params->shmem2_base, params->port, |
de6eae1f YR |
12305 | phy) != 0) { |
12306 | params->num_phys = 0; | |
12307 | DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", | |
12308 | phy_index); | |
12309 | for (phy_index = INT_PHY; | |
12310 | phy_index < MAX_PHYS; | |
12311 | phy_index++) | |
12312 | *phy = phy_null; | |
12313 | return -EINVAL; | |
12314 | } | |
12315 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) | |
12316 | break; | |
12317 | ||
55098c5c YR |
12318 | if (params->feature_config_flags & |
12319 | FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) | |
12320 | phy->flags &= ~FLAGS_TX_ERROR_CHECK; | |
12321 | ||
55386fe8 YR |
12322 | if (!(params->feature_config_flags & |
12323 | FEATURE_CONFIG_MT_SUPPORT)) | |
12324 | phy->flags |= FLAGS_MDC_MDIO_WA_G; | |
12325 | ||
1ac9e428 YR |
12326 | sync_offset = params->shmem_base + |
12327 | offsetof(struct shmem_region, | |
12328 | dev_info.port_hw_config[params->port].media_type); | |
12329 | media_types = REG_RD(bp, sync_offset); | |
12330 | ||
8f73f0b9 | 12331 | /* Update media type for non-PMF sync only for the first time |
1ac9e428 YR |
12332 | * In case the media type changes afterwards, it will be updated |
12333 | * using the update_status function | |
12334 | */ | |
12335 | if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << | |
12336 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
12337 | actual_phy_idx))) == 0) { | |
12338 | media_types |= ((phy->media_type & | |
12339 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << | |
12340 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
12341 | actual_phy_idx)); | |
12342 | } | |
12343 | REG_WR(bp, sync_offset, media_types); | |
12344 | ||
a22f0788 | 12345 | bnx2x_phy_def_cfg(params, phy, phy_index); |
de6eae1f YR |
12346 | params->num_phys++; |
12347 | } | |
12348 | ||
12349 | DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); | |
12350 | return 0; | |
12351 | } | |
12352 | ||
910cc727 MS |
12353 | static void bnx2x_init_bmac_loopback(struct link_params *params, |
12354 | struct link_vars *vars) | |
de6eae1f YR |
12355 | { |
12356 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
12357 | vars->link_up = 1; |
12358 | vars->line_speed = SPEED_10000; | |
12359 | vars->duplex = DUPLEX_FULL; | |
12360 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12361 | vars->mac_type = MAC_TYPE_BMAC; | |
b7737c9b | 12362 | |
de6eae1f | 12363 | vars->phy_flags = PHY_XGXS_FLAG; |
b7737c9b | 12364 | |
de6eae1f | 12365 | bnx2x_xgxs_deassert(params); |
b7737c9b | 12366 | |
05fcaeac | 12367 | /* Set bmac loopback */ |
d3a8f13b | 12368 | bnx2x_bmac_enable(params, vars, 1, 1); |
b7737c9b | 12369 | |
cd88ccee | 12370 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
9045f6b4 | 12371 | } |
b7737c9b | 12372 | |
910cc727 MS |
12373 | static void bnx2x_init_emac_loopback(struct link_params *params, |
12374 | struct link_vars *vars) | |
9045f6b4 YR |
12375 | { |
12376 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
12377 | vars->link_up = 1; |
12378 | vars->line_speed = SPEED_1000; | |
12379 | vars->duplex = DUPLEX_FULL; | |
12380 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12381 | vars->mac_type = MAC_TYPE_EMAC; | |
b7737c9b | 12382 | |
de6eae1f | 12383 | vars->phy_flags = PHY_XGXS_FLAG; |
e10bc84d | 12384 | |
de6eae1f | 12385 | bnx2x_xgxs_deassert(params); |
05fcaeac | 12386 | /* Set bmac loopback */ |
de6eae1f YR |
12387 | bnx2x_emac_enable(params, vars, 1); |
12388 | bnx2x_emac_program(params, vars); | |
cd88ccee | 12389 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
9045f6b4 | 12390 | } |
b7737c9b | 12391 | |
910cc727 MS |
12392 | static void bnx2x_init_xmac_loopback(struct link_params *params, |
12393 | struct link_vars *vars) | |
9380bb9e YR |
12394 | { |
12395 | struct bnx2x *bp = params->bp; | |
12396 | vars->link_up = 1; | |
12397 | if (!params->req_line_speed[0]) | |
12398 | vars->line_speed = SPEED_10000; | |
12399 | else | |
12400 | vars->line_speed = params->req_line_speed[0]; | |
12401 | vars->duplex = DUPLEX_FULL; | |
12402 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12403 | vars->mac_type = MAC_TYPE_XMAC; | |
12404 | vars->phy_flags = PHY_XGXS_FLAG; | |
8f73f0b9 | 12405 | /* Set WC to loopback mode since link is required to provide clock |
9380bb9e YR |
12406 | * to the XMAC in 20G mode |
12407 | */ | |
afad009a YR |
12408 | bnx2x_set_aer_mmd(params, ¶ms->phy[0]); |
12409 | bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); | |
12410 | params->phy[INT_PHY].config_loopback( | |
3c9ada22 YR |
12411 | ¶ms->phy[INT_PHY], |
12412 | params); | |
afad009a | 12413 | |
9380bb9e YR |
12414 | bnx2x_xmac_enable(params, vars, 1); |
12415 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
12416 | } | |
12417 | ||
910cc727 MS |
12418 | static void bnx2x_init_umac_loopback(struct link_params *params, |
12419 | struct link_vars *vars) | |
9380bb9e YR |
12420 | { |
12421 | struct bnx2x *bp = params->bp; | |
12422 | vars->link_up = 1; | |
12423 | vars->line_speed = SPEED_1000; | |
12424 | vars->duplex = DUPLEX_FULL; | |
12425 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12426 | vars->mac_type = MAC_TYPE_UMAC; | |
12427 | vars->phy_flags = PHY_XGXS_FLAG; | |
12428 | bnx2x_umac_enable(params, vars, 1); | |
12429 | ||
12430 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
12431 | } | |
12432 | ||
910cc727 MS |
12433 | static void bnx2x_init_xgxs_loopback(struct link_params *params, |
12434 | struct link_vars *vars) | |
9045f6b4 YR |
12435 | { |
12436 | struct bnx2x *bp = params->bp; | |
4e7b4997 | 12437 | struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; |
503976e9 YR |
12438 | vars->link_up = 1; |
12439 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12440 | vars->duplex = DUPLEX_FULL; | |
9045f6b4 | 12441 | if (params->req_line_speed[0] == SPEED_1000) |
503976e9 | 12442 | vars->line_speed = SPEED_1000; |
4e7b4997 YR |
12443 | else if ((params->req_line_speed[0] == SPEED_20000) || |
12444 | (int_phy->flags & FLAGS_WC_DUAL_MODE)) | |
12445 | vars->line_speed = SPEED_20000; | |
9045f6b4 | 12446 | else |
4e7b4997 | 12447 | vars->line_speed = SPEED_10000; |
62b29a5d | 12448 | |
9380bb9e YR |
12449 | if (!USES_WARPCORE(bp)) |
12450 | bnx2x_xgxs_deassert(params); | |
9045f6b4 YR |
12451 | bnx2x_link_initialize(params, vars); |
12452 | ||
12453 | if (params->req_line_speed[0] == SPEED_1000) { | |
9380bb9e YR |
12454 | if (USES_WARPCORE(bp)) |
12455 | bnx2x_umac_enable(params, vars, 0); | |
12456 | else { | |
12457 | bnx2x_emac_program(params, vars); | |
12458 | bnx2x_emac_enable(params, vars, 0); | |
12459 | } | |
12460 | } else { | |
12461 | if (USES_WARPCORE(bp)) | |
12462 | bnx2x_xmac_enable(params, vars, 0); | |
12463 | else | |
d3a8f13b | 12464 | bnx2x_bmac_enable(params, vars, 0, 1); |
9380bb9e | 12465 | } |
9045f6b4 | 12466 | |
503976e9 YR |
12467 | if (params->loopback_mode == LOOPBACK_XGXS) { |
12468 | /* Set 10G XGXS loopback */ | |
12469 | int_phy->config_loopback(int_phy, params); | |
12470 | } else { | |
12471 | /* Set external phy loopback */ | |
12472 | u8 phy_index; | |
12473 | for (phy_index = EXT_PHY1; | |
12474 | phy_index < params->num_phys; phy_index++) | |
12475 | if (params->phy[phy_index].config_loopback) | |
12476 | params->phy[phy_index].config_loopback( | |
12477 | ¶ms->phy[phy_index], | |
12478 | params); | |
12479 | } | |
12480 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
de6eae1f | 12481 | |
9045f6b4 YR |
12482 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
12483 | } | |
12484 | ||
55c11941 | 12485 | void bnx2x_set_rx_filter(struct link_params *params, u8 en) |
d3a8f13b YR |
12486 | { |
12487 | struct bnx2x *bp = params->bp; | |
12488 | u8 val = en * 0x1F; | |
12489 | ||
503976e9 | 12490 | /* Open / close the gate between the NIG and the BRB */ |
d3a8f13b YR |
12491 | if (!CHIP_IS_E1x(bp)) |
12492 | val |= en * 0x20; | |
12493 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); | |
12494 | ||
12495 | if (!CHIP_IS_E1(bp)) { | |
12496 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, | |
12497 | en*0x3); | |
12498 | } | |
12499 | ||
12500 | REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
12501 | NIG_REG_LLH0_BRB1_NOT_MCP), en); | |
12502 | } | |
12503 | static int bnx2x_avoid_link_flap(struct link_params *params, | |
12504 | struct link_vars *vars) | |
12505 | { | |
12506 | u32 phy_idx; | |
12507 | u32 dont_clear_stat, lfa_sts; | |
12508 | struct bnx2x *bp = params->bp; | |
12509 | ||
12510 | /* Sync the link parameters */ | |
12511 | bnx2x_link_status_update(params, vars); | |
12512 | ||
12513 | /* | |
12514 | * The module verification was already done by previous link owner, | |
12515 | * so this call is meant only to get warning message | |
12516 | */ | |
12517 | ||
12518 | for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) { | |
12519 | struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; | |
12520 | if (phy->phy_specific_func) { | |
12521 | DP(NETIF_MSG_LINK, "Calling PHY specific func\n"); | |
12522 | phy->phy_specific_func(phy, params, PHY_INIT); | |
12523 | } | |
12524 | if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || | |
12525 | (phy->media_type == ETH_PHY_SFP_1G_FIBER) || | |
12526 | (phy->media_type == ETH_PHY_DA_TWINAX)) | |
12527 | bnx2x_verify_sfp_module(phy, params); | |
12528 | } | |
12529 | lfa_sts = REG_RD(bp, params->lfa_base + | |
12530 | offsetof(struct shmem_lfa, | |
12531 | lfa_sts)); | |
12532 | ||
12533 | dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; | |
12534 | ||
12535 | /* Re-enable the NIG/MAC */ | |
12536 | if (CHIP_IS_E3(bp)) { | |
12537 | if (!dont_clear_stat) { | |
12538 | REG_WR(bp, GRCBASE_MISC + | |
12539 | MISC_REGISTERS_RESET_REG_2_CLEAR, | |
12540 | (MISC_REGISTERS_RESET_REG_2_MSTAT0 << | |
12541 | params->port)); | |
12542 | REG_WR(bp, GRCBASE_MISC + | |
12543 | MISC_REGISTERS_RESET_REG_2_SET, | |
12544 | (MISC_REGISTERS_RESET_REG_2_MSTAT0 << | |
12545 | params->port)); | |
12546 | } | |
12547 | if (vars->line_speed < SPEED_10000) | |
12548 | bnx2x_umac_enable(params, vars, 0); | |
12549 | else | |
12550 | bnx2x_xmac_enable(params, vars, 0); | |
12551 | } else { | |
12552 | if (vars->line_speed < SPEED_10000) | |
12553 | bnx2x_emac_enable(params, vars, 0); | |
12554 | else | |
12555 | bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat); | |
12556 | } | |
12557 | ||
12558 | /* Increment LFA count */ | |
12559 | lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | | |
12560 | (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> | |
12561 | LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) | |
12562 | << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); | |
12563 | /* Clear link flap reason */ | |
12564 | lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; | |
12565 | ||
12566 | REG_WR(bp, params->lfa_base + | |
12567 | offsetof(struct shmem_lfa, lfa_sts), lfa_sts); | |
12568 | ||
12569 | /* Disable NIG DRAIN */ | |
12570 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
12571 | ||
12572 | /* Enable interrupts */ | |
12573 | bnx2x_link_int_enable(params); | |
12574 | return 0; | |
12575 | } | |
12576 | ||
12577 | static void bnx2x_cannot_avoid_link_flap(struct link_params *params, | |
12578 | struct link_vars *vars, | |
12579 | int lfa_status) | |
12580 | { | |
12581 | u32 lfa_sts, cfg_idx, tmp_val; | |
12582 | struct bnx2x *bp = params->bp; | |
12583 | ||
12584 | bnx2x_link_reset(params, vars, 1); | |
12585 | ||
12586 | if (!params->lfa_base) | |
12587 | return; | |
12588 | /* Store the new link parameters */ | |
12589 | REG_WR(bp, params->lfa_base + | |
12590 | offsetof(struct shmem_lfa, req_duplex), | |
12591 | params->req_duplex[0] | (params->req_duplex[1] << 16)); | |
12592 | ||
12593 | REG_WR(bp, params->lfa_base + | |
12594 | offsetof(struct shmem_lfa, req_flow_ctrl), | |
12595 | params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); | |
12596 | ||
12597 | REG_WR(bp, params->lfa_base + | |
12598 | offsetof(struct shmem_lfa, req_line_speed), | |
12599 | params->req_line_speed[0] | (params->req_line_speed[1] << 16)); | |
12600 | ||
12601 | for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { | |
12602 | REG_WR(bp, params->lfa_base + | |
12603 | offsetof(struct shmem_lfa, | |
12604 | speed_cap_mask[cfg_idx]), | |
12605 | params->speed_cap_mask[cfg_idx]); | |
12606 | } | |
12607 | ||
12608 | tmp_val = REG_RD(bp, params->lfa_base + | |
12609 | offsetof(struct shmem_lfa, additional_config)); | |
12610 | tmp_val &= ~REQ_FC_AUTO_ADV_MASK; | |
12611 | tmp_val |= params->req_fc_auto_adv; | |
12612 | ||
12613 | REG_WR(bp, params->lfa_base + | |
12614 | offsetof(struct shmem_lfa, additional_config), tmp_val); | |
12615 | ||
12616 | lfa_sts = REG_RD(bp, params->lfa_base + | |
12617 | offsetof(struct shmem_lfa, lfa_sts)); | |
12618 | ||
12619 | /* Clear the "Don't Clear Statistics" bit, and set reason */ | |
12620 | lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; | |
12621 | ||
12622 | /* Set link flap reason */ | |
12623 | lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; | |
12624 | lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << | |
12625 | LFA_LINK_FLAP_REASON_OFFSET); | |
12626 | ||
12627 | /* Increment link flap counter */ | |
12628 | lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | | |
12629 | (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> | |
12630 | LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) | |
12631 | << LINK_FLAP_COUNT_OFFSET)); | |
12632 | REG_WR(bp, params->lfa_base + | |
12633 | offsetof(struct shmem_lfa, lfa_sts), lfa_sts); | |
12634 | /* Proceed with regular link initialization */ | |
12635 | } | |
12636 | ||
9045f6b4 YR |
12637 | int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) |
12638 | { | |
d3a8f13b | 12639 | int lfa_status; |
9045f6b4 YR |
12640 | struct bnx2x *bp = params->bp; |
12641 | DP(NETIF_MSG_LINK, "Phy Initialization started\n"); | |
12642 | DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", | |
12643 | params->req_line_speed[0], params->req_flow_ctrl[0]); | |
12644 | DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", | |
12645 | params->req_line_speed[1], params->req_flow_ctrl[1]); | |
05fcaeac | 12646 | DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); |
9045f6b4 YR |
12647 | vars->link_status = 0; |
12648 | vars->phy_link_up = 0; | |
12649 | vars->link_up = 0; | |
12650 | vars->line_speed = 0; | |
12651 | vars->duplex = DUPLEX_FULL; | |
12652 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12653 | vars->mac_type = MAC_TYPE_NONE; | |
12654 | vars->phy_flags = 0; | |
5f3347e6 | 12655 | vars->check_kr2_recovery_cnt = 0; |
d9169323 | 12656 | params->link_flags = PHY_INITIALIZED; |
d3a8f13b YR |
12657 | /* Driver opens NIG-BRB filters */ |
12658 | bnx2x_set_rx_filter(params, 1); | |
12659 | /* Check if link flap can be avoided */ | |
12660 | lfa_status = bnx2x_check_lfa(params); | |
12661 | ||
12662 | if (lfa_status == 0) { | |
12663 | DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n"); | |
12664 | return bnx2x_avoid_link_flap(params, vars); | |
12665 | } | |
12666 | ||
12667 | DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", | |
12668 | lfa_status); | |
12669 | bnx2x_cannot_avoid_link_flap(params, vars, lfa_status); | |
9045f6b4 | 12670 | |
d231023e | 12671 | /* Disable attentions */ |
9045f6b4 YR |
12672 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, |
12673 | (NIG_MASK_XGXS0_LINK_STATUS | | |
12674 | NIG_MASK_XGXS0_LINK10G | | |
12675 | NIG_MASK_SERDES0_LINK_STATUS | | |
12676 | NIG_MASK_MI_INT)); | |
12677 | ||
12678 | bnx2x_emac_init(params, vars); | |
12679 | ||
27d9129f YR |
12680 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
12681 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
12682 | ||
9045f6b4 YR |
12683 | if (params->num_phys == 0) { |
12684 | DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); | |
12685 | return -EINVAL; | |
12686 | } | |
12687 | set_phy_vars(params, vars); | |
12688 | ||
12689 | DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); | |
12690 | switch (params->loopback_mode) { | |
12691 | case LOOPBACK_BMAC: | |
12692 | bnx2x_init_bmac_loopback(params, vars); | |
12693 | break; | |
12694 | case LOOPBACK_EMAC: | |
12695 | bnx2x_init_emac_loopback(params, vars); | |
12696 | break; | |
9380bb9e YR |
12697 | case LOOPBACK_XMAC: |
12698 | bnx2x_init_xmac_loopback(params, vars); | |
12699 | break; | |
12700 | case LOOPBACK_UMAC: | |
12701 | bnx2x_init_umac_loopback(params, vars); | |
12702 | break; | |
9045f6b4 YR |
12703 | case LOOPBACK_XGXS: |
12704 | case LOOPBACK_EXT_PHY: | |
12705 | bnx2x_init_xgxs_loopback(params, vars); | |
12706 | break; | |
12707 | default: | |
9380bb9e YR |
12708 | if (!CHIP_IS_E3(bp)) { |
12709 | if (params->switch_cfg == SWITCH_CFG_10G) | |
12710 | bnx2x_xgxs_deassert(params); | |
12711 | else | |
12712 | bnx2x_serdes_deassert(bp, params->port); | |
12713 | } | |
de6eae1f YR |
12714 | bnx2x_link_initialize(params, vars); |
12715 | msleep(30); | |
12716 | bnx2x_link_int_enable(params); | |
9045f6b4 | 12717 | break; |
de6eae1f | 12718 | } |
55098c5c | 12719 | bnx2x_update_mng(params, vars->link_status); |
c8c60d88 YM |
12720 | |
12721 | bnx2x_update_mng_eee(params, vars->eee_status); | |
e10bc84d YR |
12722 | return 0; |
12723 | } | |
fcf5b650 YR |
12724 | |
12725 | int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, | |
12726 | u8 reset_ext_phy) | |
b7737c9b YR |
12727 | { |
12728 | struct bnx2x *bp = params->bp; | |
cf1d972c | 12729 | u8 phy_index, port = params->port, clear_latch_ind = 0; |
de6eae1f | 12730 | DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); |
d231023e | 12731 | /* Disable attentions */ |
de6eae1f YR |
12732 | vars->link_status = 0; |
12733 | bnx2x_update_mng(params, vars->link_status); | |
c8c60d88 YM |
12734 | vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | |
12735 | SHMEM_EEE_ACTIVE_BIT); | |
12736 | bnx2x_update_mng_eee(params, vars->eee_status); | |
de6eae1f | 12737 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, |
cd88ccee YR |
12738 | (NIG_MASK_XGXS0_LINK_STATUS | |
12739 | NIG_MASK_XGXS0_LINK10G | | |
12740 | NIG_MASK_SERDES0_LINK_STATUS | | |
12741 | NIG_MASK_MI_INT)); | |
b7737c9b | 12742 | |
d231023e | 12743 | /* Activate nig drain */ |
de6eae1f | 12744 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); |
b7737c9b | 12745 | |
d231023e | 12746 | /* Disable nig egress interface */ |
9380bb9e YR |
12747 | if (!CHIP_IS_E3(bp)) { |
12748 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); | |
12749 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); | |
12750 | } | |
b7737c9b | 12751 | |
d3a8f13b YR |
12752 | if (!CHIP_IS_E3(bp)) { |
12753 | bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); | |
12754 | } else { | |
12755 | bnx2x_set_xmac_rxtx(params, 0); | |
12756 | bnx2x_set_umac_rxtx(params, 0); | |
12757 | } | |
d231023e | 12758 | /* Disable emac */ |
9380bb9e YR |
12759 | if (!CHIP_IS_E3(bp)) |
12760 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
b7737c9b | 12761 | |
d231023e | 12762 | usleep_range(10000, 20000); |
25985edc | 12763 | /* The PHY reset is controlled by GPIO 1 |
de6eae1f YR |
12764 | * Hold it as vars low |
12765 | */ | |
d231023e | 12766 | /* Clear link led */ |
55386fe8 | 12767 | bnx2x_set_mdio_emac_per_phy(bp, params); |
7f02c4ad YR |
12768 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
12769 | ||
de6eae1f YR |
12770 | if (reset_ext_phy) { |
12771 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
12772 | phy_index++) { | |
28f4881c YR |
12773 | if (params->phy[phy_index].link_reset) { |
12774 | bnx2x_set_aer_mmd(params, | |
12775 | ¶ms->phy[phy_index]); | |
de6eae1f YR |
12776 | params->phy[phy_index].link_reset( |
12777 | ¶ms->phy[phy_index], | |
12778 | params); | |
28f4881c | 12779 | } |
cf1d972c YR |
12780 | if (params->phy[phy_index].flags & |
12781 | FLAGS_REARM_LATCH_SIGNAL) | |
12782 | clear_latch_ind = 1; | |
b7737c9b | 12783 | } |
b7737c9b YR |
12784 | } |
12785 | ||
cf1d972c YR |
12786 | if (clear_latch_ind) { |
12787 | /* Clear latching indication */ | |
12788 | bnx2x_rearm_latch_signal(bp, port, 0); | |
12789 | bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, | |
12790 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
12791 | } | |
de6eae1f YR |
12792 | if (params->phy[INT_PHY].link_reset) |
12793 | params->phy[INT_PHY].link_reset( | |
12794 | ¶ms->phy[INT_PHY], params); | |
b7737c9b | 12795 | |
d231023e | 12796 | /* Disable nig ingress interface */ |
9380bb9e | 12797 | if (!CHIP_IS_E3(bp)) { |
d231023e | 12798 | /* Reset BigMac */ |
ce7c0489 YR |
12799 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
12800 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
9380bb9e YR |
12801 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); |
12802 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); | |
ce7c0489 YR |
12803 | } else { |
12804 | u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
12805 | bnx2x_set_xumac_nig(params, 0, 0); | |
12806 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
12807 | MISC_REGISTERS_RESET_REG_2_XMAC) | |
12808 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, | |
12809 | XMAC_CTRL_REG_SOFT_RESET); | |
9380bb9e | 12810 | } |
de6eae1f | 12811 | vars->link_up = 0; |
3c9ada22 | 12812 | vars->phy_flags = 0; |
b7737c9b YR |
12813 | return 0; |
12814 | } | |
d3a8f13b YR |
12815 | int bnx2x_lfa_reset(struct link_params *params, |
12816 | struct link_vars *vars) | |
12817 | { | |
12818 | struct bnx2x *bp = params->bp; | |
12819 | vars->link_up = 0; | |
12820 | vars->phy_flags = 0; | |
d9169323 | 12821 | params->link_flags &= ~PHY_INITIALIZED; |
d3a8f13b YR |
12822 | if (!params->lfa_base) |
12823 | return bnx2x_link_reset(params, vars, 1); | |
12824 | /* | |
12825 | * Activate NIG drain so that during this time the device won't send | |
12826 | * anything while it is unable to response. | |
12827 | */ | |
12828 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); | |
12829 | ||
12830 | /* | |
12831 | * Close gracefully the gate from BMAC to NIG such that no half packets | |
12832 | * are passed. | |
12833 | */ | |
12834 | if (!CHIP_IS_E3(bp)) | |
12835 | bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); | |
12836 | ||
12837 | if (CHIP_IS_E3(bp)) { | |
12838 | bnx2x_set_xmac_rxtx(params, 0); | |
12839 | bnx2x_set_umac_rxtx(params, 0); | |
12840 | } | |
12841 | /* Wait 10ms for the pipe to clean up*/ | |
12842 | usleep_range(10000, 20000); | |
12843 | ||
12844 | /* Clean the NIG-BRB using the network filters in a way that will | |
12845 | * not cut a packet in the middle. | |
12846 | */ | |
12847 | bnx2x_set_rx_filter(params, 0); | |
12848 | ||
12849 | /* | |
12850 | * Re-open the gate between the BMAC and the NIG, after verifying the | |
12851 | * gate to the BRB is closed, otherwise packets may arrive to the | |
12852 | * firmware before driver had initialized it. The target is to achieve | |
12853 | * minimum management protocol down time. | |
12854 | */ | |
12855 | if (!CHIP_IS_E3(bp)) | |
12856 | bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); | |
12857 | ||
12858 | if (CHIP_IS_E3(bp)) { | |
12859 | bnx2x_set_xmac_rxtx(params, 1); | |
12860 | bnx2x_set_umac_rxtx(params, 1); | |
12861 | } | |
12862 | /* Disable NIG drain */ | |
12863 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
12864 | return 0; | |
12865 | } | |
b7737c9b | 12866 | |
de6eae1f YR |
12867 | /****************************************************************************/ |
12868 | /* Common function */ | |
12869 | /****************************************************************************/ | |
fcf5b650 YR |
12870 | static int bnx2x_8073_common_init_phy(struct bnx2x *bp, |
12871 | u32 shmem_base_path[], | |
12872 | u32 shmem2_base_path[], u8 phy_index, | |
12873 | u32 chip_id) | |
6bbca910 | 12874 | { |
e10bc84d YR |
12875 | struct bnx2x_phy phy[PORT_MAX]; |
12876 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
6bbca910 | 12877 | u16 val; |
c8e64df4 | 12878 | s8 port = 0; |
f2e0899f | 12879 | s8 port_of_path = 0; |
c8e64df4 YR |
12880 | u32 swap_val, swap_override; |
12881 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
12882 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
12883 | port ^= (swap_val && swap_override); | |
12884 | bnx2x_ext_phy_hw_reset(bp, port); | |
6bbca910 YR |
12885 | /* PART1 - Reset both phys */ |
12886 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f2e0899f DK |
12887 | u32 shmem_base, shmem2_base; |
12888 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 12889 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
12890 | shmem_base = shmem_base_path[0]; |
12891 | shmem2_base = shmem2_base_path[0]; | |
12892 | port_of_path = port; | |
3c9ada22 YR |
12893 | } else { |
12894 | shmem_base = shmem_base_path[port]; | |
12895 | shmem2_base = shmem2_base_path[port]; | |
12896 | port_of_path = 0; | |
f2e0899f DK |
12897 | } |
12898 | ||
6bbca910 | 12899 | /* Extract the ext phy address for the port */ |
a22f0788 | 12900 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 12901 | port_of_path, &phy[port]) != |
e10bc84d YR |
12902 | 0) { |
12903 | DP(NETIF_MSG_LINK, "populate_phy failed\n"); | |
12904 | return -EINVAL; | |
12905 | } | |
d231023e | 12906 | /* Disable attentions */ |
6a71bbe0 YR |
12907 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
12908 | port_of_path*4, | |
cd88ccee YR |
12909 | (NIG_MASK_XGXS0_LINK_STATUS | |
12910 | NIG_MASK_XGXS0_LINK10G | | |
12911 | NIG_MASK_SERDES0_LINK_STATUS | | |
12912 | NIG_MASK_MI_INT)); | |
6bbca910 | 12913 | |
6bbca910 | 12914 | /* Need to take the phy out of low power mode in order |
8f73f0b9 YR |
12915 | * to write to access its registers |
12916 | */ | |
6bbca910 | 12917 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee YR |
12918 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
12919 | port); | |
6bbca910 YR |
12920 | |
12921 | /* Reset the phy */ | |
e10bc84d | 12922 | bnx2x_cl45_write(bp, &phy[port], |
cd88ccee YR |
12923 | MDIO_PMA_DEVAD, |
12924 | MDIO_PMA_REG_CTRL, | |
12925 | 1<<15); | |
6bbca910 YR |
12926 | } |
12927 | ||
12928 | /* Add delay of 150ms after reset */ | |
12929 | msleep(150); | |
12930 | ||
e10bc84d YR |
12931 | if (phy[PORT_0].addr & 0x1) { |
12932 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
12933 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
12934 | } else { | |
12935 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
12936 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
12937 | } | |
12938 | ||
6bbca910 YR |
12939 | /* PART2 - Download firmware to both phys */ |
12940 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
3c9ada22 | 12941 | if (CHIP_IS_E1x(bp)) |
f2e0899f | 12942 | port_of_path = port; |
3c9ada22 YR |
12943 | else |
12944 | port_of_path = 0; | |
6bbca910 | 12945 | |
f2e0899f DK |
12946 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
12947 | phy_blk[port]->addr); | |
5c99274b YR |
12948 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
12949 | port_of_path)) | |
6bbca910 | 12950 | return -EINVAL; |
6bbca910 YR |
12951 | |
12952 | /* Only set bit 10 = 1 (Tx power down) */ | |
e10bc84d | 12953 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12954 | MDIO_PMA_DEVAD, |
12955 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
6bbca910 YR |
12956 | |
12957 | /* Phase1 of TX_POWER_DOWN reset */ | |
e10bc84d | 12958 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12959 | MDIO_PMA_DEVAD, |
12960 | MDIO_PMA_REG_TX_POWER_DOWN, | |
12961 | (val | 1<<10)); | |
6bbca910 YR |
12962 | } |
12963 | ||
8f73f0b9 | 12964 | /* Toggle Transmitter: Power down and then up with 600ms delay |
2cf7acf9 YR |
12965 | * between |
12966 | */ | |
6bbca910 YR |
12967 | msleep(600); |
12968 | ||
12969 | /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ | |
12970 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f5372251 | 12971 | /* Phase2 of POWER_DOWN_RESET */ |
6bbca910 | 12972 | /* Release bit 10 (Release Tx power down) */ |
e10bc84d | 12973 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12974 | MDIO_PMA_DEVAD, |
12975 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
6bbca910 | 12976 | |
e10bc84d | 12977 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12978 | MDIO_PMA_DEVAD, |
12979 | MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); | |
d231023e | 12980 | usleep_range(15000, 30000); |
6bbca910 YR |
12981 | |
12982 | /* Read modify write the SPI-ROM version select register */ | |
e10bc84d | 12983 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12984 | MDIO_PMA_DEVAD, |
12985 | MDIO_PMA_REG_EDC_FFE_MAIN, &val); | |
e10bc84d | 12986 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12987 | MDIO_PMA_DEVAD, |
12988 | MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); | |
6bbca910 YR |
12989 | |
12990 | /* set GPIO2 back to LOW */ | |
12991 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 12992 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
6bbca910 YR |
12993 | } |
12994 | return 0; | |
6bbca910 | 12995 | } |
fcf5b650 YR |
12996 | static int bnx2x_8726_common_init_phy(struct bnx2x *bp, |
12997 | u32 shmem_base_path[], | |
12998 | u32 shmem2_base_path[], u8 phy_index, | |
12999 | u32 chip_id) | |
de6eae1f YR |
13000 | { |
13001 | u32 val; | |
13002 | s8 port; | |
13003 | struct bnx2x_phy phy; | |
13004 | /* Use port1 because of the static port-swap */ | |
13005 | /* Enable the module detection interrupt */ | |
13006 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); | |
13007 | val |= ((1<<MISC_REGISTERS_GPIO_3)| | |
13008 | (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); | |
13009 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); | |
13010 | ||
650154bf | 13011 | bnx2x_ext_phy_hw_reset(bp, 0); |
d231023e | 13012 | usleep_range(5000, 10000); |
de6eae1f | 13013 | for (port = 0; port < PORT_MAX; port++) { |
f2e0899f DK |
13014 | u32 shmem_base, shmem2_base; |
13015 | ||
13016 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 13017 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
13018 | shmem_base = shmem_base_path[0]; |
13019 | shmem2_base = shmem2_base_path[0]; | |
3c9ada22 YR |
13020 | } else { |
13021 | shmem_base = shmem_base_path[port]; | |
13022 | shmem2_base = shmem2_base_path[port]; | |
f2e0899f | 13023 | } |
de6eae1f | 13024 | /* Extract the ext phy address for the port */ |
a22f0788 | 13025 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
13026 | port, &phy) != |
13027 | 0) { | |
13028 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13029 | return -EINVAL; | |
13030 | } | |
13031 | ||
13032 | /* Reset phy*/ | |
13033 | bnx2x_cl45_write(bp, &phy, | |
13034 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
13035 | ||
13036 | ||
13037 | /* Set fault module detected LED on */ | |
13038 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
cd88ccee YR |
13039 | MISC_REGISTERS_GPIO_HIGH, |
13040 | port); | |
de6eae1f YR |
13041 | } |
13042 | ||
13043 | return 0; | |
13044 | } | |
a8db5b4c YR |
13045 | static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, |
13046 | u8 *io_gpio, u8 *io_port) | |
13047 | { | |
13048 | ||
13049 | u32 phy_gpio_reset = REG_RD(bp, shmem_base + | |
13050 | offsetof(struct shmem_region, | |
13051 | dev_info.port_hw_config[PORT_0].default_cfg)); | |
13052 | switch (phy_gpio_reset) { | |
13053 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: | |
13054 | *io_gpio = 0; | |
13055 | *io_port = 0; | |
13056 | break; | |
13057 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: | |
13058 | *io_gpio = 1; | |
13059 | *io_port = 0; | |
13060 | break; | |
13061 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: | |
13062 | *io_gpio = 2; | |
13063 | *io_port = 0; | |
13064 | break; | |
13065 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: | |
13066 | *io_gpio = 3; | |
13067 | *io_port = 0; | |
13068 | break; | |
13069 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: | |
13070 | *io_gpio = 0; | |
13071 | *io_port = 1; | |
13072 | break; | |
13073 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: | |
13074 | *io_gpio = 1; | |
13075 | *io_port = 1; | |
13076 | break; | |
13077 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: | |
13078 | *io_gpio = 2; | |
13079 | *io_port = 1; | |
13080 | break; | |
13081 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: | |
13082 | *io_gpio = 3; | |
13083 | *io_port = 1; | |
13084 | break; | |
13085 | default: | |
13086 | /* Don't override the io_gpio and io_port */ | |
13087 | break; | |
13088 | } | |
13089 | } | |
fcf5b650 YR |
13090 | |
13091 | static int bnx2x_8727_common_init_phy(struct bnx2x *bp, | |
13092 | u32 shmem_base_path[], | |
13093 | u32 shmem2_base_path[], u8 phy_index, | |
13094 | u32 chip_id) | |
4d295db0 | 13095 | { |
a8db5b4c | 13096 | s8 port, reset_gpio; |
4d295db0 | 13097 | u32 swap_val, swap_override; |
e10bc84d YR |
13098 | struct bnx2x_phy phy[PORT_MAX]; |
13099 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
f2e0899f | 13100 | s8 port_of_path; |
cd88ccee YR |
13101 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); |
13102 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
4d295db0 | 13103 | |
a8db5b4c | 13104 | reset_gpio = MISC_REGISTERS_GPIO_1; |
a22f0788 | 13105 | port = 1; |
4d295db0 | 13106 | |
8f73f0b9 | 13107 | /* Retrieve the reset gpio/port which control the reset. |
a8db5b4c YR |
13108 | * Default is GPIO1, PORT1 |
13109 | */ | |
13110 | bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], | |
13111 | (u8 *)&reset_gpio, (u8 *)&port); | |
a22f0788 YR |
13112 | |
13113 | /* Calculate the port based on port swap */ | |
13114 | port ^= (swap_val && swap_override); | |
13115 | ||
a8db5b4c YR |
13116 | /* Initiate PHY reset*/ |
13117 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
13118 | port); | |
503976e9 | 13119 | usleep_range(1000, 2000); |
a8db5b4c YR |
13120 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
13121 | port); | |
13122 | ||
d231023e | 13123 | usleep_range(5000, 10000); |
bc7f0a05 | 13124 | |
4d295db0 | 13125 | /* PART1 - Reset both phys */ |
a22f0788 | 13126 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
f2e0899f DK |
13127 | u32 shmem_base, shmem2_base; |
13128 | ||
13129 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 13130 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
13131 | shmem_base = shmem_base_path[0]; |
13132 | shmem2_base = shmem2_base_path[0]; | |
13133 | port_of_path = port; | |
3c9ada22 YR |
13134 | } else { |
13135 | shmem_base = shmem_base_path[port]; | |
13136 | shmem2_base = shmem2_base_path[port]; | |
13137 | port_of_path = 0; | |
f2e0899f DK |
13138 | } |
13139 | ||
4d295db0 | 13140 | /* Extract the ext phy address for the port */ |
a22f0788 | 13141 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 13142 | port_of_path, &phy[port]) != |
e10bc84d YR |
13143 | 0) { |
13144 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13145 | return -EINVAL; | |
13146 | } | |
4d295db0 | 13147 | /* disable attentions */ |
f2e0899f DK |
13148 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
13149 | port_of_path*4, | |
13150 | (NIG_MASK_XGXS0_LINK_STATUS | | |
13151 | NIG_MASK_XGXS0_LINK10G | | |
13152 | NIG_MASK_SERDES0_LINK_STATUS | | |
13153 | NIG_MASK_MI_INT)); | |
4d295db0 | 13154 | |
4d295db0 EG |
13155 | |
13156 | /* Reset the phy */ | |
e10bc84d | 13157 | bnx2x_cl45_write(bp, &phy[port], |
cd88ccee | 13158 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
4d295db0 EG |
13159 | } |
13160 | ||
13161 | /* Add delay of 150ms after reset */ | |
13162 | msleep(150); | |
e10bc84d YR |
13163 | if (phy[PORT_0].addr & 0x1) { |
13164 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
13165 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
13166 | } else { | |
13167 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
13168 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
13169 | } | |
4d295db0 | 13170 | /* PART2 - Download firmware to both phys */ |
e10bc84d | 13171 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
3c9ada22 | 13172 | if (CHIP_IS_E1x(bp)) |
f2e0899f | 13173 | port_of_path = port; |
3c9ada22 YR |
13174 | else |
13175 | port_of_path = 0; | |
f2e0899f DK |
13176 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
13177 | phy_blk[port]->addr); | |
5c99274b YR |
13178 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
13179 | port_of_path)) | |
4d295db0 | 13180 | return -EINVAL; |
85242eea YR |
13181 | /* Disable PHY transmitter output */ |
13182 | bnx2x_cl45_write(bp, phy_blk[port], | |
13183 | MDIO_PMA_DEVAD, | |
13184 | MDIO_PMA_REG_TX_DISABLE, 1); | |
4d295db0 | 13185 | |
5c99274b | 13186 | } |
4d295db0 EG |
13187 | return 0; |
13188 | } | |
13189 | ||
521683da YR |
13190 | static int bnx2x_84833_common_init_phy(struct bnx2x *bp, |
13191 | u32 shmem_base_path[], | |
13192 | u32 shmem2_base_path[], | |
13193 | u8 phy_index, | |
13194 | u32 chip_id) | |
13195 | { | |
13196 | u8 reset_gpios; | |
521683da YR |
13197 | reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); |
13198 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); | |
13199 | udelay(10); | |
13200 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); | |
13201 | DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", | |
13202 | reset_gpios); | |
11b2ec6b YR |
13203 | return 0; |
13204 | } | |
521683da | 13205 | |
fcf5b650 YR |
13206 | static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], |
13207 | u32 shmem2_base_path[], u8 phy_index, | |
13208 | u32 ext_phy_type, u32 chip_id) | |
6bbca910 | 13209 | { |
fcf5b650 | 13210 | int rc = 0; |
6bbca910 YR |
13211 | |
13212 | switch (ext_phy_type) { | |
13213 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
f2e0899f DK |
13214 | rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, |
13215 | shmem2_base_path, | |
13216 | phy_index, chip_id); | |
6bbca910 | 13217 | break; |
e4d78f12 | 13218 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
4d295db0 EG |
13219 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
13220 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
f2e0899f DK |
13221 | rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, |
13222 | shmem2_base_path, | |
13223 | phy_index, chip_id); | |
4d295db0 EG |
13224 | break; |
13225 | ||
589abe3a | 13226 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
8f73f0b9 | 13227 | /* GPIO1 affects both ports, so there's need to pull |
2cf7acf9 YR |
13228 | * it for single port alone |
13229 | */ | |
f2e0899f DK |
13230 | rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, |
13231 | shmem2_base_path, | |
13232 | phy_index, chip_id); | |
a22f0788 | 13233 | break; |
0d40f0d4 | 13234 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
0f6bb03d | 13235 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: |
8f73f0b9 | 13236 | /* GPIO3's are linked, and so both need to be toggled |
0d40f0d4 YR |
13237 | * to obtain required 2us pulse. |
13238 | */ | |
521683da YR |
13239 | rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, |
13240 | shmem2_base_path, | |
13241 | phy_index, chip_id); | |
0d40f0d4 | 13242 | break; |
a22f0788 YR |
13243 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: |
13244 | rc = -EINVAL; | |
4f60dab1 | 13245 | break; |
6bbca910 YR |
13246 | default: |
13247 | DP(NETIF_MSG_LINK, | |
2cf7acf9 YR |
13248 | "ext_phy 0x%x common init not required\n", |
13249 | ext_phy_type); | |
6bbca910 YR |
13250 | break; |
13251 | } | |
13252 | ||
d231023e | 13253 | if (rc) |
6d870c39 YR |
13254 | netdev_err(bp->dev, "Warning: PHY was not initialized," |
13255 | " Port %d\n", | |
13256 | 0); | |
6bbca910 YR |
13257 | return rc; |
13258 | } | |
13259 | ||
fcf5b650 YR |
13260 | int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], |
13261 | u32 shmem2_base_path[], u32 chip_id) | |
a22f0788 | 13262 | { |
fcf5b650 | 13263 | int rc = 0; |
3c9ada22 YR |
13264 | u32 phy_ver, val; |
13265 | u8 phy_index = 0; | |
a22f0788 | 13266 | u32 ext_phy_type, ext_phy_config; |
55386fe8 YR |
13267 | |
13268 | bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0); | |
13269 | bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1); | |
a22f0788 | 13270 | DP(NETIF_MSG_LINK, "Begin common phy init\n"); |
3c9ada22 YR |
13271 | if (CHIP_IS_E3(bp)) { |
13272 | /* Enable EPIO */ | |
13273 | val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); | |
13274 | REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); | |
13275 | } | |
b21a3424 YR |
13276 | /* Check if common init was already done */ |
13277 | phy_ver = REG_RD(bp, shmem_base_path[0] + | |
13278 | offsetof(struct shmem_region, | |
13279 | port_mb[PORT_0].ext_phy_fw_version)); | |
13280 | if (phy_ver) { | |
13281 | DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", | |
13282 | phy_ver); | |
13283 | return 0; | |
13284 | } | |
13285 | ||
a22f0788 YR |
13286 | /* Read the ext_phy_type for arbitrary port(0) */ |
13287 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
13288 | phy_index++) { | |
13289 | ext_phy_config = bnx2x_get_ext_phy_config(bp, | |
f2e0899f | 13290 | shmem_base_path[0], |
a22f0788 YR |
13291 | phy_index, 0); |
13292 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
f2e0899f DK |
13293 | rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, |
13294 | shmem2_base_path, | |
13295 | phy_index, ext_phy_type, | |
13296 | chip_id); | |
a22f0788 YR |
13297 | } |
13298 | return rc; | |
13299 | } | |
d90d96ba | 13300 | |
3deb8167 YR |
13301 | static void bnx2x_check_over_curr(struct link_params *params, |
13302 | struct link_vars *vars) | |
13303 | { | |
13304 | struct bnx2x *bp = params->bp; | |
13305 | u32 cfg_pin; | |
13306 | u8 port = params->port; | |
13307 | u32 pin_val; | |
13308 | ||
13309 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
13310 | offsetof(struct shmem_region, | |
13311 | dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & | |
13312 | PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> | |
13313 | PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; | |
13314 | ||
13315 | /* Ignore check if no external input PIN available */ | |
13316 | if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) | |
13317 | return; | |
13318 | ||
13319 | if (!pin_val) { | |
13320 | if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { | |
13321 | netdev_err(bp->dev, "Error: Power fault on Port %d has" | |
13322 | " been detected and the power to " | |
13323 | "that SFP+ module has been removed" | |
13324 | " to prevent failure of the card." | |
13325 | " Please remove the SFP+ module and" | |
13326 | " restart the system to clear this" | |
13327 | " error.\n", | |
13328 | params->port); | |
13329 | vars->phy_flags |= PHY_OVER_CURRENT_FLAG; | |
5a1fbf40 | 13330 | bnx2x_warpcore_power_module(params, 0); |
3deb8167 YR |
13331 | } |
13332 | } else | |
13333 | vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; | |
13334 | } | |
13335 | ||
d0b8a6f9 YM |
13336 | /* Returns 0 if no change occured since last check; 1 otherwise. */ |
13337 | static u8 bnx2x_analyze_link_error(struct link_params *params, | |
13338 | struct link_vars *vars, u32 status, | |
13339 | u32 phy_flag, u32 link_flag, u8 notify) | |
3deb8167 YR |
13340 | { |
13341 | struct bnx2x *bp = params->bp; | |
13342 | /* Compare new value with previous value */ | |
13343 | u8 led_mode; | |
d0b8a6f9 | 13344 | u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; |
3deb8167 | 13345 | |
d0b8a6f9 YM |
13346 | if ((status ^ old_status) == 0) |
13347 | return 0; | |
3deb8167 YR |
13348 | |
13349 | /* If values differ */ | |
d0b8a6f9 YM |
13350 | switch (phy_flag) { |
13351 | case PHY_HALF_OPEN_CONN_FLAG: | |
13352 | DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); | |
13353 | break; | |
13354 | case PHY_SFP_TX_FAULT_FLAG: | |
13355 | DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); | |
13356 | break; | |
13357 | default: | |
efc7ce03 | 13358 | DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n"); |
d0b8a6f9 YM |
13359 | } |
13360 | DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, | |
13361 | old_status, status); | |
3deb8167 | 13362 | |
ad1d9ef3 YR |
13363 | /* Do not touch the link in case physical link down */ |
13364 | if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) | |
13365 | return 1; | |
13366 | ||
8f73f0b9 | 13367 | /* a. Update shmem->link_status accordingly |
3deb8167 YR |
13368 | * b. Update link_vars->link_up |
13369 | */ | |
d0b8a6f9 | 13370 | if (status) { |
3deb8167 | 13371 | vars->link_status &= ~LINK_STATUS_LINK_UP; |
d0b8a6f9 | 13372 | vars->link_status |= link_flag; |
3deb8167 | 13373 | vars->link_up = 0; |
d0b8a6f9 | 13374 | vars->phy_flags |= phy_flag; |
55098c5c YR |
13375 | |
13376 | /* activate nig drain */ | |
13377 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); | |
8f73f0b9 | 13378 | /* Set LED mode to off since the PHY doesn't know about these |
3deb8167 YR |
13379 | * errors |
13380 | */ | |
13381 | led_mode = LED_MODE_OFF; | |
13382 | } else { | |
13383 | vars->link_status |= LINK_STATUS_LINK_UP; | |
d0b8a6f9 | 13384 | vars->link_status &= ~link_flag; |
3deb8167 | 13385 | vars->link_up = 1; |
d0b8a6f9 | 13386 | vars->phy_flags &= ~phy_flag; |
3deb8167 | 13387 | led_mode = LED_MODE_OPER; |
55098c5c YR |
13388 | |
13389 | /* Clear nig drain */ | |
13390 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
3deb8167 | 13391 | } |
55098c5c | 13392 | bnx2x_sync_link(params, vars); |
3deb8167 YR |
13393 | /* Update the LED according to the link state */ |
13394 | bnx2x_set_led(params, vars, led_mode, SPEED_10000); | |
13395 | ||
13396 | /* Update link status in the shared memory */ | |
13397 | bnx2x_update_mng(params, vars->link_status); | |
13398 | ||
13399 | /* C. Trigger General Attention */ | |
13400 | vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; | |
55098c5c YR |
13401 | if (notify) |
13402 | bnx2x_notify_link_changed(bp); | |
d0b8a6f9 YM |
13403 | |
13404 | return 1; | |
3deb8167 YR |
13405 | } |
13406 | ||
de6f3377 YR |
13407 | /****************************************************************************** |
13408 | * Description: | |
13409 | * This function checks for half opened connection change indication. | |
13410 | * When such change occurs, it calls the bnx2x_analyze_link_error | |
13411 | * to check if Remote Fault is set or cleared. Reception of remote fault | |
13412 | * status message in the MAC indicates that the peer's MAC has detected | |
13413 | * a fault, for example, due to break in the TX side of fiber. | |
13414 | * | |
13415 | ******************************************************************************/ | |
55098c5c YR |
13416 | int bnx2x_check_half_open_conn(struct link_params *params, |
13417 | struct link_vars *vars, | |
13418 | u8 notify) | |
3deb8167 YR |
13419 | { |
13420 | struct bnx2x *bp = params->bp; | |
13421 | u32 lss_status = 0; | |
13422 | u32 mac_base; | |
13423 | /* In case link status is physically up @ 10G do */ | |
55098c5c YR |
13424 | if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || |
13425 | (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) | |
13426 | return 0; | |
3deb8167 | 13427 | |
de6f3377 | 13428 | if (CHIP_IS_E3(bp) && |
3deb8167 | 13429 | (REG_RD(bp, MISC_REG_RESET_REG_2) & |
de6f3377 YR |
13430 | (MISC_REGISTERS_RESET_REG_2_XMAC))) { |
13431 | /* Check E3 XMAC */ | |
8f73f0b9 | 13432 | /* Note that link speed cannot be queried here, since it may be |
de6f3377 YR |
13433 | * zero while link is down. In case UMAC is active, LSS will |
13434 | * simply not be set | |
13435 | */ | |
13436 | mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
13437 | ||
13438 | /* Clear stick bits (Requires rising edge) */ | |
13439 | REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); | |
13440 | REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, | |
13441 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | | |
13442 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); | |
13443 | if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) | |
13444 | lss_status = 1; | |
13445 | ||
d0b8a6f9 YM |
13446 | bnx2x_analyze_link_error(params, vars, lss_status, |
13447 | PHY_HALF_OPEN_CONN_FLAG, | |
13448 | LINK_STATUS_NONE, notify); | |
de6f3377 YR |
13449 | } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & |
13450 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { | |
3deb8167 YR |
13451 | /* Check E1X / E2 BMAC */ |
13452 | u32 lss_status_reg; | |
13453 | u32 wb_data[2]; | |
13454 | mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
13455 | NIG_REG_INGRESS_BMAC0_MEM; | |
13456 | /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ | |
13457 | if (CHIP_IS_E2(bp)) | |
13458 | lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; | |
13459 | else | |
13460 | lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; | |
13461 | ||
13462 | REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); | |
13463 | lss_status = (wb_data[0] > 0); | |
13464 | ||
d0b8a6f9 YM |
13465 | bnx2x_analyze_link_error(params, vars, lss_status, |
13466 | PHY_HALF_OPEN_CONN_FLAG, | |
13467 | LINK_STATUS_NONE, notify); | |
3deb8167 | 13468 | } |
55098c5c | 13469 | return 0; |
3deb8167 | 13470 | } |
d0b8a6f9 YM |
13471 | static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, |
13472 | struct link_params *params, | |
13473 | struct link_vars *vars) | |
13474 | { | |
13475 | struct bnx2x *bp = params->bp; | |
13476 | u32 cfg_pin, value = 0; | |
13477 | u8 led_change, port = params->port; | |
3deb8167 | 13478 | |
d0b8a6f9 YM |
13479 | /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ |
13480 | cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, | |
13481 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
13482 | PORT_HW_CFG_E3_TX_FAULT_MASK) >> | |
13483 | PORT_HW_CFG_E3_TX_FAULT_SHIFT; | |
13484 | ||
13485 | if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { | |
13486 | DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); | |
13487 | return; | |
13488 | } | |
13489 | ||
13490 | led_change = bnx2x_analyze_link_error(params, vars, value, | |
13491 | PHY_SFP_TX_FAULT_FLAG, | |
13492 | LINK_STATUS_SFP_TX_FAULT, 1); | |
13493 | ||
13494 | if (led_change) { | |
13495 | /* Change TX_Fault led, set link status for further syncs */ | |
13496 | u8 led_mode; | |
13497 | ||
13498 | if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { | |
13499 | led_mode = MISC_REGISTERS_GPIO_HIGH; | |
13500 | vars->link_status |= LINK_STATUS_SFP_TX_FAULT; | |
13501 | } else { | |
13502 | led_mode = MISC_REGISTERS_GPIO_LOW; | |
13503 | vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; | |
13504 | } | |
13505 | ||
13506 | /* If module is unapproved, led should be on regardless */ | |
13507 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { | |
13508 | DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", | |
13509 | led_mode); | |
13510 | bnx2x_set_e3_module_fault_led(params, led_mode); | |
13511 | } | |
13512 | } | |
13513 | } | |
4e7b4997 YR |
13514 | static void bnx2x_kr2_recovery(struct link_params *params, |
13515 | struct link_vars *vars, | |
13516 | struct bnx2x_phy *phy) | |
13517 | { | |
13518 | struct bnx2x *bp = params->bp; | |
13519 | DP(NETIF_MSG_LINK, "KR2 recovery\n"); | |
13520 | bnx2x_warpcore_enable_AN_KR2(phy, params, vars); | |
13521 | bnx2x_warpcore_restart_AN_KR(phy, params); | |
13522 | } | |
13523 | ||
13524 | static void bnx2x_check_kr2_wa(struct link_params *params, | |
13525 | struct link_vars *vars, | |
13526 | struct bnx2x_phy *phy) | |
13527 | { | |
13528 | struct bnx2x *bp = params->bp; | |
13529 | u16 base_page, next_page, not_kr2_device, lane; | |
cb28ea3b | 13530 | int sigdet; |
4e7b4997 | 13531 | |
5f3347e6 | 13532 | /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery |
05fcaeac YR |
13533 | * Since some switches tend to reinit the AN process and clear the |
13534 | * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled | |
5f3347e6 YR |
13535 | * and recovered many times |
13536 | */ | |
13537 | if (vars->check_kr2_recovery_cnt > 0) { | |
13538 | vars->check_kr2_recovery_cnt--; | |
13539 | return; | |
13540 | } | |
cb28ea3b YR |
13541 | |
13542 | sigdet = bnx2x_warpcore_get_sigdet(phy, params); | |
13543 | if (!sigdet) { | |
13544 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { | |
13545 | bnx2x_kr2_recovery(params, vars, phy); | |
13546 | DP(NETIF_MSG_LINK, "No sigdet\n"); | |
13547 | } | |
13548 | return; | |
13549 | } | |
13550 | ||
4e7b4997 YR |
13551 | lane = bnx2x_get_warpcore_lane(phy, params); |
13552 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
13553 | MDIO_AER_BLOCK_AER_REG, lane); | |
13554 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
13555 | MDIO_AN_REG_LP_AUTO_NEG, &base_page); | |
13556 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
13557 | MDIO_AN_REG_LP_AUTO_NEG2, &next_page); | |
13558 | bnx2x_set_aer_mmd(params, phy); | |
13559 | ||
13560 | /* CL73 has not begun yet */ | |
13561 | if (base_page == 0) { | |
05fcaeac | 13562 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { |
4e7b4997 | 13563 | bnx2x_kr2_recovery(params, vars, phy); |
05fcaeac YR |
13564 | DP(NETIF_MSG_LINK, "No BP\n"); |
13565 | } | |
4e7b4997 YR |
13566 | return; |
13567 | } | |
13568 | ||
13569 | /* In case NP bit is not set in the BasePage, or it is set, | |
13570 | * but only KX is advertised, declare this link partner as non-KR2 | |
13571 | * device. | |
13572 | */ | |
13573 | not_kr2_device = (((base_page & 0x8000) == 0) || | |
13574 | (((base_page & 0x8000) && | |
13575 | ((next_page & 0xe0) == 0x2)))); | |
13576 | ||
13577 | /* In case KR2 is already disabled, check if we need to re-enable it */ | |
13578 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { | |
13579 | if (!not_kr2_device) { | |
13580 | DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, | |
05fcaeac | 13581 | next_page); |
4e7b4997 YR |
13582 | bnx2x_kr2_recovery(params, vars, phy); |
13583 | } | |
13584 | return; | |
13585 | } | |
13586 | /* KR2 is enabled, but not KR2 device */ | |
13587 | if (not_kr2_device) { | |
13588 | /* Disable KR2 on both lanes */ | |
13589 | DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page); | |
13590 | bnx2x_disable_kr2(params, vars, phy); | |
4e4b14c9 YR |
13591 | /* Restart AN on leading lane */ |
13592 | bnx2x_warpcore_restart_AN_KR(phy, params); | |
4e7b4997 YR |
13593 | return; |
13594 | } | |
13595 | } | |
13596 | ||
3deb8167 YR |
13597 | void bnx2x_period_func(struct link_params *params, struct link_vars *vars) |
13598 | { | |
de6f3377 | 13599 | u16 phy_idx; |
55098c5c | 13600 | struct bnx2x *bp = params->bp; |
de6f3377 YR |
13601 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { |
13602 | if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { | |
13603 | bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); | |
55098c5c YR |
13604 | if (bnx2x_check_half_open_conn(params, vars, 1) != |
13605 | 0) | |
13606 | DP(NETIF_MSG_LINK, "Fault detection failed\n"); | |
de6f3377 YR |
13607 | break; |
13608 | } | |
13609 | } | |
13610 | ||
a9077bfd YR |
13611 | if (CHIP_IS_E3(bp)) { |
13612 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; | |
13613 | bnx2x_set_aer_mmd(params, phy); | |
4e7b4997 | 13614 | if ((phy->supported & SUPPORTED_20000baseKR2_Full) && |
d521de04 | 13615 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) |
4e7b4997 | 13616 | bnx2x_check_kr2_wa(params, vars, phy); |
3deb8167 | 13617 | bnx2x_check_over_curr(params, vars); |
d0b8a6f9 YM |
13618 | if (vars->rx_tx_asic_rst) |
13619 | bnx2x_warpcore_config_runtime(phy, params, vars); | |
13620 | ||
13621 | if ((REG_RD(bp, params->shmem_base + | |
13622 | offsetof(struct shmem_region, dev_info. | |
13623 | port_hw_config[params->port].default_cfg)) | |
13624 | & PORT_HW_CFG_NET_SERDES_IF_MASK) == | |
13625 | PORT_HW_CFG_NET_SERDES_IF_SFI) { | |
13626 | if (bnx2x_is_sfp_module_plugged(phy, params)) { | |
13627 | bnx2x_sfp_tx_fault_detection(phy, params, vars); | |
13628 | } else if (vars->link_status & | |
13629 | LINK_STATUS_SFP_TX_FAULT) { | |
13630 | /* Clean trail, interrupt corrects the leds */ | |
13631 | vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; | |
13632 | vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; | |
13633 | /* Update link status in the shared memory */ | |
13634 | bnx2x_update_mng(params, vars->link_status); | |
13635 | } | |
13636 | } | |
a9077bfd | 13637 | } |
3deb8167 YR |
13638 | } |
13639 | ||
d90d96ba YR |
13640 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, |
13641 | u32 shmem_base, | |
a22f0788 | 13642 | u32 shmem2_base, |
d90d96ba YR |
13643 | u8 port) |
13644 | { | |
13645 | u8 phy_index, fan_failure_det_req = 0; | |
13646 | struct bnx2x_phy phy; | |
13647 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
13648 | phy_index++) { | |
a22f0788 | 13649 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
d90d96ba YR |
13650 | port, &phy) |
13651 | != 0) { | |
13652 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13653 | return 0; | |
13654 | } | |
13655 | fan_failure_det_req |= (phy.flags & | |
13656 | FLAGS_FAN_FAILURE_DET_REQ); | |
13657 | } | |
13658 | return fan_failure_det_req; | |
13659 | } | |
13660 | ||
13661 | void bnx2x_hw_reset_phy(struct link_params *params) | |
13662 | { | |
13663 | u8 phy_index; | |
985848f8 YR |
13664 | struct bnx2x *bp = params->bp; |
13665 | bnx2x_update_mng(params, 0); | |
13666 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, | |
13667 | (NIG_MASK_XGXS0_LINK_STATUS | | |
13668 | NIG_MASK_XGXS0_LINK10G | | |
13669 | NIG_MASK_SERDES0_LINK_STATUS | | |
13670 | NIG_MASK_MI_INT)); | |
13671 | ||
13672 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
d90d96ba YR |
13673 | phy_index++) { |
13674 | if (params->phy[phy_index].hw_reset) { | |
13675 | params->phy[phy_index].hw_reset( | |
13676 | ¶ms->phy[phy_index], | |
13677 | params); | |
13678 | params->phy[phy_index] = phy_null; | |
13679 | } | |
13680 | } | |
13681 | } | |
020c7e3f YR |
13682 | |
13683 | void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, | |
13684 | u32 chip_id, u32 shmem_base, u32 shmem2_base, | |
13685 | u8 port) | |
13686 | { | |
13687 | u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; | |
13688 | u32 val; | |
13689 | u32 offset, aeu_mask, swap_val, swap_override, sync_offset; | |
3c9ada22 YR |
13690 | if (CHIP_IS_E3(bp)) { |
13691 | if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, | |
13692 | shmem_base, | |
13693 | port, | |
13694 | &gpio_num, | |
13695 | &gpio_port) != 0) | |
13696 | return; | |
13697 | } else { | |
020c7e3f YR |
13698 | struct bnx2x_phy phy; |
13699 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
13700 | phy_index++) { | |
13701 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, | |
13702 | shmem2_base, port, &phy) | |
13703 | != 0) { | |
13704 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13705 | return; | |
13706 | } | |
13707 | if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { | |
13708 | gpio_num = MISC_REGISTERS_GPIO_3; | |
13709 | gpio_port = port; | |
13710 | break; | |
13711 | } | |
13712 | } | |
13713 | } | |
13714 | ||
13715 | if (gpio_num == 0xff) | |
13716 | return; | |
13717 | ||
13718 | /* Set GPIO3 to trigger SFP+ module insertion/removal */ | |
13719 | bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); | |
13720 | ||
13721 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
13722 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
13723 | gpio_port ^= (swap_val && swap_override); | |
13724 | ||
13725 | vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << | |
13726 | (gpio_num + (gpio_port << 2)); | |
13727 | ||
13728 | sync_offset = shmem_base + | |
13729 | offsetof(struct shmem_region, | |
13730 | dev_info.port_hw_config[port].aeu_int_mask); | |
13731 | REG_WR(bp, sync_offset, vars->aeu_int_mask); | |
13732 | ||
13733 | DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", | |
13734 | gpio_num, gpio_port, vars->aeu_int_mask); | |
13735 | ||
13736 | if (port == 0) | |
13737 | offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; | |
13738 | else | |
13739 | offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; | |
13740 | ||
13741 | /* Open appropriate AEU for interrupts */ | |
13742 | aeu_mask = REG_RD(bp, offset); | |
13743 | aeu_mask |= vars->aeu_int_mask; | |
13744 | REG_WR(bp, offset, aeu_mask); | |
13745 | ||
13746 | /* Enable the GPIO to trigger interrupt */ | |
13747 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); | |
13748 | val |= 1 << (gpio_num + (gpio_port << 2)); | |
13749 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); | |
13750 | } |