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85b26ea1 | 1 | /* Copyright 2008-2012 Broadcom Corporation |
ea4e040a YR |
2 | * |
3 | * Unless you and Broadcom execute a separate written software license | |
4 | * agreement governing use of this software, this software is licensed to you | |
5 | * under the terms of the GNU General Public License version 2, available | |
6 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
7 | * | |
8 | * Notwithstanding the above, under no circumstances may you combine this | |
9 | * software in any way with any other Broadcom software provided under a | |
10 | * license other than the GPL, without Broadcom's express prior written | |
11 | * consent. | |
12 | * | |
13 | * Written by Yaniv Rosner | |
14 | * | |
15 | */ | |
16 | ||
7995c64e JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
ea4e040a YR |
19 | #include <linux/kernel.h> |
20 | #include <linux/errno.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ethtool.h> | |
25 | #include <linux/mutex.h> | |
ea4e040a | 26 | |
ea4e040a | 27 | #include "bnx2x.h" |
619c5cb6 VZ |
28 | #include "bnx2x_cmn.h" |
29 | ||
ea4e040a | 30 | /********************************************************/ |
3196a88a | 31 | #define ETH_HLEN 14 |
cd88ccee YR |
32 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
33 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
ea4e040a YR |
34 | #define ETH_MIN_PACKET_SIZE 60 |
35 | #define ETH_MAX_PACKET_SIZE 1500 | |
36 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
37 | #define MDIO_ACCESS_TIMEOUT 1000 | |
3c9ada22 YR |
38 | #define WC_LANE_MAX 4 |
39 | #define I2C_SWITCH_WIDTH 2 | |
40 | #define I2C_BSC0 0 | |
41 | #define I2C_BSC1 1 | |
42 | #define I2C_WA_RETRY_CNT 3 | |
43 | #define MCPR_IMC_COMMAND_READ_OP 1 | |
44 | #define MCPR_IMC_COMMAND_WRITE_OP 2 | |
ea4e040a | 45 | |
26ffaf36 YR |
46 | /* LED Blink rate that will achieve ~15.9Hz */ |
47 | #define LED_BLINK_RATE_VAL_E3 354 | |
48 | #define LED_BLINK_RATE_VAL_E1X_E2 480 | |
ea4e040a | 49 | /***********************************************************/ |
3196a88a | 50 | /* Shortcut definitions */ |
ea4e040a YR |
51 | /***********************************************************/ |
52 | ||
2f904460 EG |
53 | #define NIG_LATCH_BC_ENABLE_MI_INT 0 |
54 | ||
55 | #define NIG_STATUS_EMAC0_MI_INT \ | |
56 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT | |
ea4e040a YR |
57 | #define NIG_STATUS_XGXS0_LINK10G \ |
58 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G | |
59 | #define NIG_STATUS_XGXS0_LINK_STATUS \ | |
60 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS | |
61 | #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ | |
62 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE | |
63 | #define NIG_STATUS_SERDES0_LINK_STATUS \ | |
64 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS | |
65 | #define NIG_MASK_MI_INT \ | |
66 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT | |
67 | #define NIG_MASK_XGXS0_LINK10G \ | |
68 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G | |
69 | #define NIG_MASK_XGXS0_LINK_STATUS \ | |
70 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS | |
71 | #define NIG_MASK_SERDES0_LINK_STATUS \ | |
72 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS | |
73 | ||
74 | #define MDIO_AN_CL73_OR_37_COMPLETE \ | |
75 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ | |
76 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) | |
77 | ||
78 | #define XGXS_RESET_BITS \ | |
79 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ | |
80 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ | |
81 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ | |
82 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ | |
83 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) | |
84 | ||
85 | #define SERDES_RESET_BITS \ | |
86 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ | |
87 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ | |
88 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ | |
89 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) | |
90 | ||
91 | #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 | |
92 | #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 | |
cd88ccee | 93 | #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM |
3196a88a | 94 | #define AUTONEG_PARALLEL \ |
ea4e040a | 95 | SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION |
3196a88a | 96 | #define AUTONEG_SGMII_FIBER_AUTODET \ |
ea4e040a | 97 | SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT |
3196a88a | 98 | #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY |
ea4e040a YR |
99 | |
100 | #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ | |
101 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE | |
102 | #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ | |
103 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE | |
104 | #define GP_STATUS_SPEED_MASK \ | |
105 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK | |
106 | #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M | |
107 | #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M | |
108 | #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G | |
109 | #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G | |
110 | #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G | |
111 | #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G | |
112 | #define GP_STATUS_10G_HIG \ | |
113 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG | |
114 | #define GP_STATUS_10G_CX4 \ | |
115 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 | |
ea4e040a YR |
116 | #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX |
117 | #define GP_STATUS_10G_KX4 \ | |
118 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 | |
3c9ada22 YR |
119 | #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR |
120 | #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI | |
121 | #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS | |
122 | #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI | |
cd88ccee YR |
123 | #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD |
124 | #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD | |
ea4e040a | 125 | #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD |
cd88ccee | 126 | #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 |
ea4e040a YR |
127 | #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD |
128 | #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD | |
129 | #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD | |
130 | #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD | |
131 | #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD | |
132 | #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD | |
133 | #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD | |
cd88ccee YR |
134 | #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD |
135 | #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD | |
3c9ada22 YR |
136 | #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD |
137 | #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD | |
6583e33b YR |
138 | |
139 | ||
140 | ||
589abe3a | 141 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 |
cd88ccee | 142 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 |
589abe3a EG |
143 | #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 |
144 | ||
4d295db0 EG |
145 | |
146 | #define SFP_EEPROM_COMP_CODE_ADDR 0x3 | |
147 | #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) | |
148 | #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) | |
149 | #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) | |
150 | ||
589abe3a EG |
151 | #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 |
152 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 | |
cd88ccee | 153 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 |
4d295db0 | 154 | |
cd88ccee | 155 | #define SFP_EEPROM_OPTIONS_ADDR 0x40 |
589abe3a | 156 | #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 |
cd88ccee | 157 | #define SFP_EEPROM_OPTIONS_SIZE 2 |
589abe3a | 158 | |
cd88ccee YR |
159 | #define EDC_MODE_LINEAR 0x0022 |
160 | #define EDC_MODE_LIMITING 0x0044 | |
161 | #define EDC_MODE_PASSIVE_DAC 0x0055 | |
4d295db0 | 162 | |
866cedae YR |
163 | /* BRB default for class 0 E2 */ |
164 | #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170 | |
165 | #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250 | |
166 | #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10 | |
167 | #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50 | |
4d295db0 | 168 | |
9380bb9e YR |
169 | /* BRB thresholds for E2*/ |
170 | #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170 | |
171 | #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0 | |
172 | ||
173 | #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250 | |
174 | #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0 | |
175 | ||
176 | #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10 | |
177 | #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90 | |
178 | ||
179 | #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50 | |
180 | #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250 | |
181 | ||
866cedae YR |
182 | /* BRB default for class 0 E3A0 */ |
183 | #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290 | |
184 | #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410 | |
185 | #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10 | |
186 | #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50 | |
187 | ||
9380bb9e YR |
188 | /* BRB thresholds for E3A0 */ |
189 | #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290 | |
190 | #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0 | |
191 | ||
192 | #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410 | |
193 | #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0 | |
194 | ||
195 | #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10 | |
196 | #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170 | |
197 | ||
198 | #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50 | |
199 | #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410 | |
200 | ||
866cedae YR |
201 | /* BRB default for E3B0 */ |
202 | #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330 | |
203 | #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490 | |
204 | #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15 | |
205 | #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55 | |
9380bb9e YR |
206 | |
207 | /* BRB thresholds for E3B0 2 port mode*/ | |
208 | #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025 | |
209 | #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0 | |
210 | ||
211 | #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025 | |
212 | #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0 | |
213 | ||
214 | #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10 | |
215 | #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025 | |
216 | ||
217 | #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50 | |
218 | #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025 | |
219 | ||
220 | /* only for E3B0*/ | |
221 | #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025 | |
222 | #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025 | |
223 | ||
224 | /* Lossy +Lossless GUARANTIED == GUART */ | |
225 | #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284 | |
226 | /* Lossless +Lossless*/ | |
227 | #define PFC_E3B0_2P_PAUSE_LB_GUART 236 | |
228 | /* Lossy +Lossy*/ | |
229 | #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342 | |
230 | ||
231 | /* Lossy +Lossless*/ | |
232 | #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284 | |
233 | /* Lossless +Lossless*/ | |
234 | #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236 | |
235 | /* Lossy +Lossy*/ | |
236 | #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336 | |
237 | #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80 | |
238 | ||
239 | #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0 | |
240 | #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0 | |
241 | ||
242 | /* BRB thresholds for E3B0 4 port mode */ | |
243 | #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304 | |
244 | #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0 | |
245 | ||
246 | #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384 | |
247 | #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0 | |
248 | ||
249 | #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10 | |
250 | #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304 | |
251 | ||
252 | #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50 | |
253 | #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384 | |
254 | ||
9380bb9e YR |
255 | /* only for E3B0*/ |
256 | #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304 | |
257 | #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384 | |
2f751a80 | 258 | #define PFC_E3B0_4P_LB_GUART 120 |
9380bb9e YR |
259 | |
260 | #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120 | |
2f751a80 | 261 | #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80 |
9380bb9e YR |
262 | |
263 | #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80 | |
2f751a80 | 264 | #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120 |
9380bb9e | 265 | |
866cedae YR |
266 | /* Pause defines*/ |
267 | #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330 | |
268 | #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490 | |
269 | #define DEFAULT_E3B0_LB_GUART 40 | |
270 | ||
271 | #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40 | |
272 | #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0 | |
273 | ||
274 | #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40 | |
275 | #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0 | |
276 | ||
277 | /* ETS defines*/ | |
9380bb9e YR |
278 | #define DCBX_INVALID_COS (0xFF) |
279 | ||
bcab15c5 VZ |
280 | #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) |
281 | #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) | |
9380bb9e YR |
282 | #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) |
283 | #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) | |
284 | #define ETS_E3B0_PBF_MIN_W_VAL (10000) | |
285 | ||
286 | #define MAX_PACKET_SIZE (9700) | |
3c9ada22 | 287 | #define WC_UC_TIMEOUT 100 |
a9077bfd | 288 | #define MAX_KR_LINK_RETRY 4 |
9380bb9e | 289 | |
ea4e040a YR |
290 | /**********************************************************/ |
291 | /* INTERFACE */ | |
292 | /**********************************************************/ | |
e10bc84d | 293 | |
cd2be89b | 294 | #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
e10bc84d | 295 | bnx2x_cl45_write(_bp, _phy, \ |
7aa0711f | 296 | (_phy)->def_md_devad, \ |
ea4e040a YR |
297 | (_bank + (_addr & 0xf)), \ |
298 | _val) | |
299 | ||
cd2be89b | 300 | #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
e10bc84d | 301 | bnx2x_cl45_read(_bp, _phy, \ |
7aa0711f | 302 | (_phy)->def_md_devad, \ |
ea4e040a YR |
303 | (_bank + (_addr & 0xf)), \ |
304 | _val) | |
305 | ||
ea4e040a YR |
306 | static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) |
307 | { | |
308 | u32 val = REG_RD(bp, reg); | |
309 | ||
310 | val |= bits; | |
311 | REG_WR(bp, reg, val); | |
312 | return val; | |
313 | } | |
314 | ||
315 | static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) | |
316 | { | |
317 | u32 val = REG_RD(bp, reg); | |
318 | ||
319 | val &= ~bits; | |
320 | REG_WR(bp, reg, val); | |
321 | return val; | |
322 | } | |
323 | ||
3c9ada22 YR |
324 | /******************************************************************/ |
325 | /* EPIO/GPIO section */ | |
326 | /******************************************************************/ | |
3deb8167 YR |
327 | static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) |
328 | { | |
329 | u32 epio_mask, gp_oenable; | |
330 | *en = 0; | |
331 | /* Sanity check */ | |
332 | if (epio_pin > 31) { | |
333 | DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); | |
334 | return; | |
335 | } | |
336 | ||
337 | epio_mask = 1 << epio_pin; | |
338 | /* Set this EPIO to output */ | |
339 | gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); | |
340 | REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); | |
341 | ||
342 | *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; | |
343 | } | |
3c9ada22 YR |
344 | static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) |
345 | { | |
346 | u32 epio_mask, gp_output, gp_oenable; | |
347 | ||
348 | /* Sanity check */ | |
349 | if (epio_pin > 31) { | |
350 | DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); | |
351 | return; | |
352 | } | |
353 | DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); | |
354 | epio_mask = 1 << epio_pin; | |
355 | /* Set this EPIO to output */ | |
356 | gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); | |
357 | if (en) | |
358 | gp_output |= epio_mask; | |
359 | else | |
360 | gp_output &= ~epio_mask; | |
361 | ||
362 | REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); | |
363 | ||
364 | /* Set the value for this EPIO */ | |
365 | gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); | |
366 | REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); | |
367 | } | |
368 | ||
369 | static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) | |
370 | { | |
371 | if (pin_cfg == PIN_CFG_NA) | |
372 | return; | |
373 | if (pin_cfg >= PIN_CFG_EPIO0) { | |
374 | bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); | |
375 | } else { | |
376 | u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; | |
377 | u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; | |
378 | bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); | |
379 | } | |
380 | } | |
381 | ||
3deb8167 YR |
382 | static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) |
383 | { | |
384 | if (pin_cfg == PIN_CFG_NA) | |
385 | return -EINVAL; | |
386 | if (pin_cfg >= PIN_CFG_EPIO0) { | |
387 | bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); | |
388 | } else { | |
389 | u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; | |
390 | u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; | |
391 | *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); | |
392 | } | |
393 | return 0; | |
394 | ||
395 | } | |
bcab15c5 VZ |
396 | /******************************************************************/ |
397 | /* ETS section */ | |
398 | /******************************************************************/ | |
6c3218c6 | 399 | static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) |
bcab15c5 VZ |
400 | { |
401 | /* ETS disabled configuration*/ | |
402 | struct bnx2x *bp = params->bp; | |
403 | ||
6c3218c6 | 404 | DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); |
bcab15c5 | 405 | |
8f73f0b9 | 406 | /* mapping between entry priority to client number (0,1,2 -debug and |
bcab15c5 VZ |
407 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) |
408 | * 3bits client num. | |
409 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
410 | * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 | |
411 | */ | |
412 | ||
413 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); | |
8f73f0b9 | 414 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
bcab15c5 VZ |
415 | * as strict. Bits 0,1,2 - debug and management entries, 3 - |
416 | * COS0 entry, 4 - COS1 entry. | |
417 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT | |
418 | * bit4 bit3 bit2 bit1 bit0 | |
419 | * MCP and debug are strict | |
420 | */ | |
421 | ||
422 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); | |
423 | /* defines which entries (clients) are subjected to WFQ arbitration */ | |
424 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); | |
8f73f0b9 | 425 | /* For strict priority entries defines the number of consecutive |
2cf7acf9 YR |
426 | * slots for the highest priority. |
427 | */ | |
bcab15c5 | 428 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); |
8f73f0b9 | 429 | /* mapping between the CREDIT_WEIGHT registers and actual client |
bcab15c5 VZ |
430 | * numbers |
431 | */ | |
432 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); | |
433 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); | |
434 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); | |
435 | ||
436 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); | |
437 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); | |
438 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); | |
439 | /* ETS mode disable */ | |
440 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); | |
8f73f0b9 | 441 | /* If ETS mode is enabled (there is no strict priority) defines a WFQ |
bcab15c5 VZ |
442 | * weight for COS0/COS1. |
443 | */ | |
444 | REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); | |
445 | REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); | |
446 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ | |
447 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); | |
448 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); | |
449 | /* Defines the number of consecutive slots for the strict priority */ | |
450 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); | |
451 | } | |
6c3218c6 YR |
452 | /****************************************************************************** |
453 | * Description: | |
454 | * Getting min_w_val will be set according to line speed . | |
455 | *. | |
456 | ******************************************************************************/ | |
457 | static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) | |
458 | { | |
459 | u32 min_w_val = 0; | |
460 | /* Calculate min_w_val.*/ | |
461 | if (vars->link_up) { | |
de0396f4 | 462 | if (vars->line_speed == SPEED_20000) |
6c3218c6 YR |
463 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; |
464 | else | |
465 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; | |
466 | } else | |
467 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; | |
8f73f0b9 YR |
468 | /* If the link isn't up (static configuration for example ) The |
469 | * link will be according to 20GBPS. | |
470 | */ | |
6c3218c6 YR |
471 | return min_w_val; |
472 | } | |
473 | /****************************************************************************** | |
474 | * Description: | |
475 | * Getting credit upper bound form min_w_val. | |
476 | *. | |
477 | ******************************************************************************/ | |
478 | static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) | |
479 | { | |
480 | const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), | |
481 | MAX_PACKET_SIZE); | |
482 | return credit_upper_bound; | |
483 | } | |
484 | /****************************************************************************** | |
485 | * Description: | |
486 | * Set credit upper bound for NIG. | |
487 | *. | |
488 | ******************************************************************************/ | |
489 | static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( | |
490 | const struct link_params *params, | |
491 | const u32 min_w_val) | |
492 | { | |
493 | struct bnx2x *bp = params->bp; | |
494 | const u8 port = params->port; | |
495 | const u32 credit_upper_bound = | |
496 | bnx2x_ets_get_credit_upper_bound(min_w_val); | |
497 | ||
498 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : | |
499 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); | |
500 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : | |
501 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); | |
502 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : | |
503 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); | |
504 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : | |
505 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); | |
506 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : | |
507 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); | |
508 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : | |
509 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); | |
510 | ||
de0396f4 | 511 | if (!port) { |
6c3218c6 YR |
512 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, |
513 | credit_upper_bound); | |
514 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, | |
515 | credit_upper_bound); | |
516 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, | |
517 | credit_upper_bound); | |
518 | } | |
519 | } | |
520 | /****************************************************************************** | |
521 | * Description: | |
522 | * Will return the NIG ETS registers to init values.Except | |
523 | * credit_upper_bound. | |
524 | * That isn't used in this configuration (No WFQ is enabled) and will be | |
525 | * configured acording to spec | |
526 | *. | |
527 | ******************************************************************************/ | |
528 | static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, | |
529 | const struct link_vars *vars) | |
530 | { | |
531 | struct bnx2x *bp = params->bp; | |
532 | const u8 port = params->port; | |
533 | const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); | |
8f73f0b9 | 534 | /* Mapping between entry priority to client number (0,1,2 -debug and |
6c3218c6 YR |
535 | * management clients, 3 - COS0 client, 4 - COS1, ... 8 - |
536 | * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by | |
537 | * reset value or init tool | |
538 | */ | |
539 | if (port) { | |
540 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); | |
541 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); | |
542 | } else { | |
543 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); | |
544 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); | |
545 | } | |
8f73f0b9 YR |
546 | /* For strict priority entries defines the number of consecutive |
547 | * slots for the highest priority. | |
548 | */ | |
6c3218c6 YR |
549 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : |
550 | NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); | |
8f73f0b9 | 551 | /* Mapping between the CREDIT_WEIGHT registers and actual client |
6c3218c6 YR |
552 | * numbers |
553 | */ | |
6c3218c6 YR |
554 | if (port) { |
555 | /*Port 1 has 6 COS*/ | |
556 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); | |
557 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); | |
558 | } else { | |
559 | /*Port 0 has 9 COS*/ | |
560 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, | |
561 | 0x43210876); | |
562 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); | |
563 | } | |
564 | ||
8f73f0b9 | 565 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
6c3218c6 YR |
566 | * as strict. Bits 0,1,2 - debug and management entries, 3 - |
567 | * COS0 entry, 4 - COS1 entry. | |
568 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT | |
569 | * bit4 bit3 bit2 bit1 bit0 | |
570 | * MCP and debug are strict | |
571 | */ | |
572 | if (port) | |
573 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); | |
574 | else | |
575 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); | |
576 | /* defines which entries (clients) are subjected to WFQ arbitration */ | |
577 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : | |
578 | NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); | |
579 | ||
8f73f0b9 YR |
580 | /* Please notice the register address are note continuous and a |
581 | * for here is note appropriate.In 2 port mode port0 only COS0-5 | |
582 | * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 | |
583 | * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT | |
584 | * are never used for WFQ | |
585 | */ | |
6c3218c6 YR |
586 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : |
587 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); | |
588 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : | |
589 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); | |
590 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : | |
591 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); | |
592 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : | |
593 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); | |
594 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : | |
595 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); | |
596 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : | |
597 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); | |
de0396f4 | 598 | if (!port) { |
6c3218c6 YR |
599 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); |
600 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); | |
601 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); | |
602 | } | |
603 | ||
604 | bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); | |
605 | } | |
606 | /****************************************************************************** | |
607 | * Description: | |
608 | * Set credit upper bound for PBF. | |
609 | *. | |
610 | ******************************************************************************/ | |
611 | static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( | |
612 | const struct link_params *params, | |
613 | const u32 min_w_val) | |
614 | { | |
615 | struct bnx2x *bp = params->bp; | |
616 | const u32 credit_upper_bound = | |
617 | bnx2x_ets_get_credit_upper_bound(min_w_val); | |
618 | const u8 port = params->port; | |
619 | u32 base_upper_bound = 0; | |
620 | u8 max_cos = 0; | |
621 | u8 i = 0; | |
8f73f0b9 YR |
622 | /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 |
623 | * port mode port1 has COS0-2 that can be used for WFQ. | |
624 | */ | |
de0396f4 | 625 | if (!port) { |
6c3218c6 YR |
626 | base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; |
627 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; | |
628 | } else { | |
629 | base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; | |
630 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; | |
631 | } | |
632 | ||
633 | for (i = 0; i < max_cos; i++) | |
634 | REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); | |
635 | } | |
636 | ||
637 | /****************************************************************************** | |
638 | * Description: | |
639 | * Will return the PBF ETS registers to init values.Except | |
640 | * credit_upper_bound. | |
641 | * That isn't used in this configuration (No WFQ is enabled) and will be | |
642 | * configured acording to spec | |
643 | *. | |
644 | ******************************************************************************/ | |
645 | static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) | |
646 | { | |
647 | struct bnx2x *bp = params->bp; | |
648 | const u8 port = params->port; | |
649 | const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; | |
650 | u8 i = 0; | |
651 | u32 base_weight = 0; | |
652 | u8 max_cos = 0; | |
653 | ||
8f73f0b9 | 654 | /* Mapping between entry priority to client number 0 - COS0 |
6c3218c6 YR |
655 | * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. |
656 | * TODO_ETS - Should be done by reset value or init tool | |
657 | */ | |
658 | if (port) | |
659 | /* 0x688 (|011|0 10|00 1|000) */ | |
660 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); | |
661 | else | |
662 | /* (10 1|100 |011|0 10|00 1|000) */ | |
663 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); | |
664 | ||
665 | /* TODO_ETS - Should be done by reset value or init tool */ | |
666 | if (port) | |
667 | /* 0x688 (|011|0 10|00 1|000)*/ | |
668 | REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); | |
669 | else | |
670 | /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ | |
671 | REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); | |
672 | ||
673 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : | |
674 | PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); | |
675 | ||
676 | ||
677 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : | |
678 | PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); | |
679 | ||
680 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : | |
681 | PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); | |
8f73f0b9 YR |
682 | /* In 2 port mode port0 has COS0-5 that can be used for WFQ. |
683 | * In 4 port mode port1 has COS0-2 that can be used for WFQ. | |
684 | */ | |
de0396f4 | 685 | if (!port) { |
6c3218c6 YR |
686 | base_weight = PBF_REG_COS0_WEIGHT_P0; |
687 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; | |
688 | } else { | |
689 | base_weight = PBF_REG_COS0_WEIGHT_P1; | |
690 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; | |
691 | } | |
692 | ||
693 | for (i = 0; i < max_cos; i++) | |
694 | REG_WR(bp, base_weight + (0x4 * i), 0); | |
695 | ||
696 | bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); | |
697 | } | |
698 | /****************************************************************************** | |
699 | * Description: | |
700 | * E3B0 disable will return basicly the values to init values. | |
701 | *. | |
702 | ******************************************************************************/ | |
703 | static int bnx2x_ets_e3b0_disabled(const struct link_params *params, | |
704 | const struct link_vars *vars) | |
705 | { | |
706 | struct bnx2x *bp = params->bp; | |
707 | ||
708 | if (!CHIP_IS_E3B0(bp)) { | |
94f05b0f JP |
709 | DP(NETIF_MSG_LINK, |
710 | "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); | |
6c3218c6 YR |
711 | return -EINVAL; |
712 | } | |
713 | ||
714 | bnx2x_ets_e3b0_nig_disabled(params, vars); | |
715 | ||
716 | bnx2x_ets_e3b0_pbf_disabled(params); | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
721 | /****************************************************************************** | |
722 | * Description: | |
723 | * Disable will return basicly the values to init values. | |
8f73f0b9 | 724 | * |
6c3218c6 YR |
725 | ******************************************************************************/ |
726 | int bnx2x_ets_disabled(struct link_params *params, | |
727 | struct link_vars *vars) | |
728 | { | |
729 | struct bnx2x *bp = params->bp; | |
730 | int bnx2x_status = 0; | |
731 | ||
732 | if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) | |
733 | bnx2x_ets_e2e3a0_disabled(params); | |
734 | else if (CHIP_IS_E3B0(bp)) | |
735 | bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); | |
736 | else { | |
737 | DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); | |
738 | return -EINVAL; | |
739 | } | |
740 | ||
741 | return bnx2x_status; | |
742 | } | |
743 | ||
744 | /****************************************************************************** | |
745 | * Description | |
746 | * Set the COS mappimg to SP and BW until this point all the COS are not | |
747 | * set as SP or BW. | |
748 | ******************************************************************************/ | |
749 | static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, | |
750 | const struct bnx2x_ets_params *ets_params, | |
751 | const u8 cos_sp_bitmap, | |
752 | const u8 cos_bw_bitmap) | |
753 | { | |
754 | struct bnx2x *bp = params->bp; | |
755 | const u8 port = params->port; | |
756 | const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); | |
757 | const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; | |
758 | const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; | |
759 | const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; | |
760 | ||
761 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : | |
762 | NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); | |
763 | ||
764 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : | |
765 | PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); | |
bcab15c5 | 766 | |
6c3218c6 YR |
767 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : |
768 | NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, | |
769 | nig_cli_subject2wfq_bitmap); | |
770 | ||
771 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : | |
772 | PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, | |
773 | pbf_cli_subject2wfq_bitmap); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | /****************************************************************************** | |
779 | * Description: | |
780 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are | |
781 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. | |
782 | ******************************************************************************/ | |
783 | static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, | |
784 | const u8 cos_entry, | |
785 | const u32 min_w_val_nig, | |
786 | const u32 min_w_val_pbf, | |
787 | const u16 total_bw, | |
788 | const u8 bw, | |
789 | const u8 port) | |
790 | { | |
791 | u32 nig_reg_adress_crd_weight = 0; | |
792 | u32 pbf_reg_adress_crd_weight = 0; | |
c482e6c0 YR |
793 | /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ |
794 | const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; | |
795 | const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; | |
6c3218c6 YR |
796 | |
797 | switch (cos_entry) { | |
798 | case 0: | |
799 | nig_reg_adress_crd_weight = | |
800 | (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : | |
801 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; | |
802 | pbf_reg_adress_crd_weight = (port) ? | |
803 | PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; | |
804 | break; | |
805 | case 1: | |
806 | nig_reg_adress_crd_weight = (port) ? | |
807 | NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : | |
808 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; | |
809 | pbf_reg_adress_crd_weight = (port) ? | |
810 | PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; | |
811 | break; | |
812 | case 2: | |
813 | nig_reg_adress_crd_weight = (port) ? | |
814 | NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : | |
815 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; | |
816 | ||
817 | pbf_reg_adress_crd_weight = (port) ? | |
818 | PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; | |
819 | break; | |
820 | case 3: | |
821 | if (port) | |
822 | return -EINVAL; | |
823 | nig_reg_adress_crd_weight = | |
824 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; | |
825 | pbf_reg_adress_crd_weight = | |
826 | PBF_REG_COS3_WEIGHT_P0; | |
827 | break; | |
828 | case 4: | |
829 | if (port) | |
830 | return -EINVAL; | |
831 | nig_reg_adress_crd_weight = | |
832 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; | |
833 | pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; | |
834 | break; | |
835 | case 5: | |
836 | if (port) | |
837 | return -EINVAL; | |
838 | nig_reg_adress_crd_weight = | |
839 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; | |
840 | pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; | |
841 | break; | |
842 | } | |
843 | ||
844 | REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); | |
845 | ||
846 | REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); | |
847 | ||
848 | return 0; | |
849 | } | |
850 | /****************************************************************************** | |
851 | * Description: | |
852 | * Calculate the total BW.A value of 0 isn't legal. | |
8f73f0b9 | 853 | * |
6c3218c6 YR |
854 | ******************************************************************************/ |
855 | static int bnx2x_ets_e3b0_get_total_bw( | |
856 | const struct link_params *params, | |
870516e1 | 857 | struct bnx2x_ets_params *ets_params, |
6c3218c6 YR |
858 | u16 *total_bw) |
859 | { | |
860 | struct bnx2x *bp = params->bp; | |
861 | u8 cos_idx = 0; | |
870516e1 | 862 | u8 is_bw_cos_exist = 0; |
6c3218c6 YR |
863 | |
864 | *total_bw = 0 ; | |
865 | /* Calculate total BW requested */ | |
866 | for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { | |
de0396f4 | 867 | if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { |
870516e1 YR |
868 | is_bw_cos_exist = 1; |
869 | if (!ets_params->cos[cos_idx].params.bw_params.bw) { | |
870 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" | |
871 | "was set to 0\n"); | |
8f73f0b9 | 872 | /* This is to prevent a state when ramrods |
870516e1 | 873 | * can't be sent |
8f73f0b9 | 874 | */ |
870516e1 YR |
875 | ets_params->cos[cos_idx].params.bw_params.bw |
876 | = 1; | |
877 | } | |
c482e6c0 YR |
878 | *total_bw += |
879 | ets_params->cos[cos_idx].params.bw_params.bw; | |
6c3218c6 | 880 | } |
6c3218c6 YR |
881 | } |
882 | ||
c482e6c0 | 883 | /* Check total BW is valid */ |
de0396f4 YR |
884 | if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { |
885 | if (*total_bw == 0) { | |
94f05b0f | 886 | DP(NETIF_MSG_LINK, |
2f751a80 | 887 | "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); |
6c3218c6 YR |
888 | return -EINVAL; |
889 | } | |
94f05b0f | 890 | DP(NETIF_MSG_LINK, |
2f751a80 | 891 | "bnx2x_ets_E3B0_config total BW should be 100\n"); |
8f73f0b9 | 892 | /* We can handle a case whre the BW isn't 100 this can happen |
2f751a80 YR |
893 | * if the TC are joined. |
894 | */ | |
6c3218c6 YR |
895 | } |
896 | return 0; | |
897 | } | |
898 | ||
899 | /****************************************************************************** | |
900 | * Description: | |
901 | * Invalidate all the sp_pri_to_cos. | |
8f73f0b9 | 902 | * |
6c3218c6 YR |
903 | ******************************************************************************/ |
904 | static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) | |
905 | { | |
906 | u8 pri = 0; | |
907 | for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) | |
908 | sp_pri_to_cos[pri] = DCBX_INVALID_COS; | |
909 | } | |
910 | /****************************************************************************** | |
911 | * Description: | |
912 | * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers | |
913 | * according to sp_pri_to_cos. | |
8f73f0b9 | 914 | * |
6c3218c6 YR |
915 | ******************************************************************************/ |
916 | static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, | |
917 | u8 *sp_pri_to_cos, const u8 pri, | |
918 | const u8 cos_entry) | |
919 | { | |
920 | struct bnx2x *bp = params->bp; | |
921 | const u8 port = params->port; | |
922 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
923 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
924 | ||
7e5998aa DC |
925 | if (pri >= max_num_of_cos) { |
926 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " | |
927 | "parameter Illegal strict priority\n"); | |
928 | return -EINVAL; | |
929 | } | |
930 | ||
de0396f4 | 931 | if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { |
6c3218c6 | 932 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " |
94f05b0f | 933 | "parameter There can't be two COS's with " |
6c3218c6 YR |
934 | "the same strict pri\n"); |
935 | return -EINVAL; | |
936 | } | |
937 | ||
6c3218c6 YR |
938 | sp_pri_to_cos[pri] = cos_entry; |
939 | return 0; | |
940 | ||
941 | } | |
942 | ||
943 | /****************************************************************************** | |
944 | * Description: | |
945 | * Returns the correct value according to COS and priority in | |
946 | * the sp_pri_cli register. | |
8f73f0b9 | 947 | * |
6c3218c6 YR |
948 | ******************************************************************************/ |
949 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, | |
950 | const u8 pri_set, | |
951 | const u8 pri_offset, | |
952 | const u8 entry_size) | |
953 | { | |
954 | u64 pri_cli_nig = 0; | |
955 | pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * | |
956 | (pri_set + pri_offset)); | |
957 | ||
958 | return pri_cli_nig; | |
959 | } | |
960 | /****************************************************************************** | |
961 | * Description: | |
962 | * Returns the correct value according to COS and priority in the | |
963 | * sp_pri_cli register for NIG. | |
8f73f0b9 | 964 | * |
6c3218c6 YR |
965 | ******************************************************************************/ |
966 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) | |
967 | { | |
968 | /* MCP Dbg0 and dbg1 are always with higher strict pri*/ | |
969 | const u8 nig_cos_offset = 3; | |
970 | const u8 nig_pri_offset = 3; | |
971 | ||
972 | return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, | |
973 | nig_pri_offset, 4); | |
974 | ||
975 | } | |
976 | /****************************************************************************** | |
977 | * Description: | |
978 | * Returns the correct value according to COS and priority in the | |
979 | * sp_pri_cli register for PBF. | |
8f73f0b9 | 980 | * |
6c3218c6 YR |
981 | ******************************************************************************/ |
982 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) | |
983 | { | |
984 | const u8 pbf_cos_offset = 0; | |
985 | const u8 pbf_pri_offset = 0; | |
986 | ||
987 | return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, | |
988 | pbf_pri_offset, 3); | |
989 | ||
990 | } | |
991 | ||
992 | /****************************************************************************** | |
993 | * Description: | |
994 | * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers | |
995 | * according to sp_pri_to_cos.(which COS has higher priority) | |
8f73f0b9 | 996 | * |
6c3218c6 YR |
997 | ******************************************************************************/ |
998 | static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, | |
999 | u8 *sp_pri_to_cos) | |
1000 | { | |
1001 | struct bnx2x *bp = params->bp; | |
1002 | u8 i = 0; | |
1003 | const u8 port = params->port; | |
1004 | /* MCP Dbg0 and dbg1 are always with higher strict pri*/ | |
1005 | u64 pri_cli_nig = 0x210; | |
1006 | u32 pri_cli_pbf = 0x0; | |
1007 | u8 pri_set = 0; | |
1008 | u8 pri_bitmask = 0; | |
1009 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
1010 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
1011 | ||
1012 | u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; | |
1013 | ||
1014 | /* Set all the strict priority first */ | |
1015 | for (i = 0; i < max_num_of_cos; i++) { | |
de0396f4 YR |
1016 | if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { |
1017 | if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { | |
6c3218c6 YR |
1018 | DP(NETIF_MSG_LINK, |
1019 | "bnx2x_ets_e3b0_sp_set_pri_cli_reg " | |
1020 | "invalid cos entry\n"); | |
1021 | return -EINVAL; | |
1022 | } | |
1023 | ||
1024 | pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( | |
1025 | sp_pri_to_cos[i], pri_set); | |
1026 | ||
1027 | pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( | |
1028 | sp_pri_to_cos[i], pri_set); | |
1029 | pri_bitmask = 1 << sp_pri_to_cos[i]; | |
1030 | /* COS is used remove it from bitmap.*/ | |
de0396f4 | 1031 | if (!(pri_bitmask & cos_bit_to_set)) { |
6c3218c6 YR |
1032 | DP(NETIF_MSG_LINK, |
1033 | "bnx2x_ets_e3b0_sp_set_pri_cli_reg " | |
1034 | "invalid There can't be two COS's with" | |
1035 | " the same strict pri\n"); | |
1036 | return -EINVAL; | |
1037 | } | |
1038 | cos_bit_to_set &= ~pri_bitmask; | |
1039 | pri_set++; | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | /* Set all the Non strict priority i= COS*/ | |
1044 | for (i = 0; i < max_num_of_cos; i++) { | |
1045 | pri_bitmask = 1 << i; | |
1046 | /* Check if COS was already used for SP */ | |
1047 | if (pri_bitmask & cos_bit_to_set) { | |
1048 | /* COS wasn't used for SP */ | |
1049 | pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( | |
1050 | i, pri_set); | |
1051 | ||
1052 | pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( | |
1053 | i, pri_set); | |
1054 | /* COS is used remove it from bitmap.*/ | |
1055 | cos_bit_to_set &= ~pri_bitmask; | |
1056 | pri_set++; | |
1057 | } | |
1058 | } | |
1059 | ||
1060 | if (pri_set != max_num_of_cos) { | |
1061 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " | |
1062 | "entries were set\n"); | |
1063 | return -EINVAL; | |
1064 | } | |
1065 | ||
1066 | if (port) { | |
1067 | /* Only 6 usable clients*/ | |
1068 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, | |
1069 | (u32)pri_cli_nig); | |
1070 | ||
1071 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); | |
1072 | } else { | |
1073 | /* Only 9 usable clients*/ | |
1074 | const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); | |
1075 | const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); | |
1076 | ||
1077 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, | |
1078 | pri_cli_nig_lsb); | |
1079 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, | |
1080 | pri_cli_nig_msb); | |
1081 | ||
1082 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); | |
1083 | } | |
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | /****************************************************************************** | |
1088 | * Description: | |
1089 | * Configure the COS to ETS according to BW and SP settings. | |
1090 | ******************************************************************************/ | |
1091 | int bnx2x_ets_e3b0_config(const struct link_params *params, | |
1092 | const struct link_vars *vars, | |
870516e1 | 1093 | struct bnx2x_ets_params *ets_params) |
6c3218c6 YR |
1094 | { |
1095 | struct bnx2x *bp = params->bp; | |
1096 | int bnx2x_status = 0; | |
1097 | const u8 port = params->port; | |
1098 | u16 total_bw = 0; | |
1099 | const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); | |
1100 | const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; | |
1101 | u8 cos_bw_bitmap = 0; | |
1102 | u8 cos_sp_bitmap = 0; | |
1103 | u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; | |
1104 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
1105 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
1106 | u8 cos_entry = 0; | |
1107 | ||
1108 | if (!CHIP_IS_E3B0(bp)) { | |
94f05b0f JP |
1109 | DP(NETIF_MSG_LINK, |
1110 | "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); | |
6c3218c6 YR |
1111 | return -EINVAL; |
1112 | } | |
1113 | ||
1114 | if ((ets_params->num_of_cos > max_num_of_cos)) { | |
1115 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " | |
1116 | "isn't supported\n"); | |
1117 | return -EINVAL; | |
1118 | } | |
1119 | ||
1120 | /* Prepare sp strict priority parameters*/ | |
1121 | bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); | |
1122 | ||
1123 | /* Prepare BW parameters*/ | |
1124 | bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, | |
1125 | &total_bw); | |
de0396f4 | 1126 | if (bnx2x_status) { |
94f05b0f JP |
1127 | DP(NETIF_MSG_LINK, |
1128 | "bnx2x_ets_E3B0_config get_total_bw failed\n"); | |
6c3218c6 YR |
1129 | return -EINVAL; |
1130 | } | |
1131 | ||
8f73f0b9 | 1132 | /* Upper bound is set according to current link speed (min_w_val |
2f751a80 | 1133 | * should be the same for upper bound and COS credit val). |
6c3218c6 YR |
1134 | */ |
1135 | bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); | |
1136 | bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); | |
1137 | ||
1138 | ||
1139 | for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { | |
1140 | if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { | |
1141 | cos_bw_bitmap |= (1 << cos_entry); | |
8f73f0b9 | 1142 | /* The function also sets the BW in HW(not the mappin |
6c3218c6 YR |
1143 | * yet) |
1144 | */ | |
1145 | bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( | |
1146 | bp, cos_entry, min_w_val_nig, min_w_val_pbf, | |
1147 | total_bw, | |
1148 | ets_params->cos[cos_entry].params.bw_params.bw, | |
1149 | port); | |
1150 | } else if (bnx2x_cos_state_strict == | |
1151 | ets_params->cos[cos_entry].state){ | |
1152 | cos_sp_bitmap |= (1 << cos_entry); | |
1153 | ||
1154 | bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( | |
1155 | params, | |
1156 | sp_pri_to_cos, | |
1157 | ets_params->cos[cos_entry].params.sp_params.pri, | |
1158 | cos_entry); | |
1159 | ||
1160 | } else { | |
94f05b0f JP |
1161 | DP(NETIF_MSG_LINK, |
1162 | "bnx2x_ets_e3b0_config cos state not valid\n"); | |
6c3218c6 YR |
1163 | return -EINVAL; |
1164 | } | |
de0396f4 | 1165 | if (bnx2x_status) { |
94f05b0f JP |
1166 | DP(NETIF_MSG_LINK, |
1167 | "bnx2x_ets_e3b0_config set cos bw failed\n"); | |
6c3218c6 YR |
1168 | return bnx2x_status; |
1169 | } | |
1170 | } | |
1171 | ||
1172 | /* Set SP register (which COS has higher priority) */ | |
1173 | bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, | |
1174 | sp_pri_to_cos); | |
1175 | ||
de0396f4 | 1176 | if (bnx2x_status) { |
94f05b0f JP |
1177 | DP(NETIF_MSG_LINK, |
1178 | "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); | |
6c3218c6 YR |
1179 | return bnx2x_status; |
1180 | } | |
1181 | ||
1182 | /* Set client mapping of BW and strict */ | |
1183 | bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, | |
1184 | cos_sp_bitmap, | |
1185 | cos_bw_bitmap); | |
1186 | ||
de0396f4 | 1187 | if (bnx2x_status) { |
6c3218c6 YR |
1188 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); |
1189 | return bnx2x_status; | |
1190 | } | |
1191 | return 0; | |
1192 | } | |
65a001ba | 1193 | static void bnx2x_ets_bw_limit_common(const struct link_params *params) |
bcab15c5 VZ |
1194 | { |
1195 | /* ETS disabled configuration */ | |
1196 | struct bnx2x *bp = params->bp; | |
1197 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); | |
8f73f0b9 | 1198 | /* Defines which entries (clients) are subjected to WFQ arbitration |
2cf7acf9 YR |
1199 | * COS0 0x8 |
1200 | * COS1 0x10 | |
1201 | */ | |
bcab15c5 | 1202 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); |
8f73f0b9 | 1203 | /* Mapping between the ARB_CREDIT_WEIGHT registers and actual |
2cf7acf9 YR |
1204 | * client numbers (WEIGHT_0 does not actually have to represent |
1205 | * client 0) | |
1206 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
1207 | * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 | |
1208 | */ | |
bcab15c5 VZ |
1209 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); |
1210 | ||
1211 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, | |
1212 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1213 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, | |
1214 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1215 | ||
1216 | /* ETS mode enabled*/ | |
1217 | REG_WR(bp, PBF_REG_ETS_ENABLED, 1); | |
1218 | ||
1219 | /* Defines the number of consecutive slots for the strict priority */ | |
1220 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); | |
8f73f0b9 | 1221 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
2cf7acf9 YR |
1222 | * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 |
1223 | * entry, 4 - COS1 entry. | |
1224 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT | |
1225 | * bit4 bit3 bit2 bit1 bit0 | |
1226 | * MCP and debug are strict | |
1227 | */ | |
bcab15c5 VZ |
1228 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); |
1229 | ||
1230 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ | |
1231 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, | |
1232 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1233 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, | |
1234 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1235 | } | |
1236 | ||
1237 | void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, | |
1238 | const u32 cos1_bw) | |
1239 | { | |
1240 | /* ETS disabled configuration*/ | |
1241 | struct bnx2x *bp = params->bp; | |
1242 | const u32 total_bw = cos0_bw + cos1_bw; | |
1243 | u32 cos0_credit_weight = 0; | |
1244 | u32 cos1_credit_weight = 0; | |
1245 | ||
1246 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); | |
1247 | ||
de0396f4 YR |
1248 | if ((!total_bw) || |
1249 | (!cos0_bw) || | |
1250 | (!cos1_bw)) { | |
cd88ccee | 1251 | DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); |
bcab15c5 VZ |
1252 | return; |
1253 | } | |
1254 | ||
1255 | cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ | |
1256 | total_bw; | |
1257 | cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ | |
1258 | total_bw; | |
1259 | ||
1260 | bnx2x_ets_bw_limit_common(params); | |
1261 | ||
1262 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); | |
1263 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); | |
1264 | ||
1265 | REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); | |
1266 | REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); | |
1267 | } | |
1268 | ||
fcf5b650 | 1269 | int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) |
bcab15c5 VZ |
1270 | { |
1271 | /* ETS disabled configuration*/ | |
1272 | struct bnx2x *bp = params->bp; | |
1273 | u32 val = 0; | |
1274 | ||
bcab15c5 | 1275 | DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); |
8f73f0b9 | 1276 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
bcab15c5 VZ |
1277 | * as strict. Bits 0,1,2 - debug and management entries, |
1278 | * 3 - COS0 entry, 4 - COS1 entry. | |
1279 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT | |
1280 | * bit4 bit3 bit2 bit1 bit0 | |
1281 | * MCP and debug are strict | |
1282 | */ | |
1283 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); | |
8f73f0b9 | 1284 | /* For strict priority entries defines the number of consecutive slots |
bcab15c5 VZ |
1285 | * for the highest priority. |
1286 | */ | |
1287 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); | |
1288 | /* ETS mode disable */ | |
1289 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); | |
1290 | /* Defines the number of consecutive slots for the strict priority */ | |
1291 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); | |
1292 | ||
1293 | /* Defines the number of consecutive slots for the strict priority */ | |
1294 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); | |
1295 | ||
8f73f0b9 | 1296 | /* Mapping between entry priority to client number (0,1,2 -debug and |
2cf7acf9 YR |
1297 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) |
1298 | * 3bits client num. | |
1299 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
1300 | * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 | |
1301 | * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 | |
1302 | */ | |
de0396f4 | 1303 | val = (!strict_cos) ? 0x2318 : 0x22E0; |
bcab15c5 VZ |
1304 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); |
1305 | ||
1306 | return 0; | |
1307 | } | |
1308 | /******************************************************************/ | |
e8920674 | 1309 | /* PFC section */ |
bcab15c5 | 1310 | /******************************************************************/ |
9380bb9e YR |
1311 | static void bnx2x_update_pfc_xmac(struct link_params *params, |
1312 | struct link_vars *vars, | |
1313 | u8 is_lb) | |
1314 | { | |
1315 | struct bnx2x *bp = params->bp; | |
1316 | u32 xmac_base; | |
1317 | u32 pause_val, pfc0_val, pfc1_val; | |
1318 | ||
1319 | /* XMAC base adrr */ | |
1320 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1321 | ||
1322 | /* Initialize pause and pfc registers */ | |
1323 | pause_val = 0x18000; | |
1324 | pfc0_val = 0xFFFF8000; | |
1325 | pfc1_val = 0x2; | |
1326 | ||
1327 | /* No PFC support */ | |
1328 | if (!(params->feature_config_flags & | |
1329 | FEATURE_CONFIG_PFC_ENABLED)) { | |
1330 | ||
8f73f0b9 | 1331 | /* RX flow control - Process pause frame in receive direction |
9380bb9e YR |
1332 | */ |
1333 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) | |
1334 | pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; | |
1335 | ||
8f73f0b9 | 1336 | /* TX flow control - Send pause packet when buffer is full */ |
9380bb9e YR |
1337 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
1338 | pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; | |
1339 | } else {/* PFC support */ | |
1340 | pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | | |
1341 | XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | | |
1342 | XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | | |
27d9129f YR |
1343 | XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | |
1344 | XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; | |
1345 | /* Write pause and PFC registers */ | |
1346 | REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); | |
1347 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); | |
1348 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); | |
1349 | pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; | |
1350 | ||
9380bb9e YR |
1351 | } |
1352 | ||
1353 | /* Write pause and PFC registers */ | |
1354 | REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); | |
1355 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); | |
1356 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); | |
1357 | ||
9380bb9e | 1358 | |
b8d6d082 YR |
1359 | /* Set MAC address for source TX Pause/PFC frames */ |
1360 | REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, | |
1361 | ((params->mac_addr[2] << 24) | | |
1362 | (params->mac_addr[3] << 16) | | |
1363 | (params->mac_addr[4] << 8) | | |
1364 | (params->mac_addr[5]))); | |
1365 | REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, | |
1366 | ((params->mac_addr[0] << 8) | | |
1367 | (params->mac_addr[1]))); | |
9380bb9e | 1368 | |
b8d6d082 YR |
1369 | udelay(30); |
1370 | } | |
bcab15c5 | 1371 | |
bcab15c5 | 1372 | |
bcab15c5 VZ |
1373 | static void bnx2x_emac_get_pfc_stat(struct link_params *params, |
1374 | u32 pfc_frames_sent[2], | |
1375 | u32 pfc_frames_received[2]) | |
1376 | { | |
1377 | /* Read pfc statistic */ | |
1378 | struct bnx2x *bp = params->bp; | |
1379 | u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1380 | u32 val_xon = 0; | |
1381 | u32 val_xoff = 0; | |
1382 | ||
1383 | DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n"); | |
1384 | ||
1385 | /* PFC received frames */ | |
1386 | val_xoff = REG_RD(bp, emac_base + | |
1387 | EMAC_REG_RX_PFC_STATS_XOFF_RCVD); | |
1388 | val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; | |
1389 | val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); | |
1390 | val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; | |
1391 | ||
1392 | pfc_frames_received[0] = val_xon + val_xoff; | |
1393 | ||
1394 | /* PFC received sent */ | |
1395 | val_xoff = REG_RD(bp, emac_base + | |
1396 | EMAC_REG_RX_PFC_STATS_XOFF_SENT); | |
1397 | val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; | |
1398 | val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); | |
1399 | val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; | |
1400 | ||
1401 | pfc_frames_sent[0] = val_xon + val_xoff; | |
1402 | } | |
1403 | ||
b8d6d082 | 1404 | /* Read pfc statistic*/ |
bcab15c5 VZ |
1405 | void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars, |
1406 | u32 pfc_frames_sent[2], | |
1407 | u32 pfc_frames_received[2]) | |
1408 | { | |
1409 | /* Read pfc statistic */ | |
1410 | struct bnx2x *bp = params->bp; | |
b8d6d082 | 1411 | |
bcab15c5 VZ |
1412 | DP(NETIF_MSG_LINK, "pfc statistic\n"); |
1413 | ||
1414 | if (!vars->link_up) | |
1415 | return; | |
1416 | ||
de0396f4 | 1417 | if (vars->mac_type == MAC_TYPE_EMAC) { |
b8d6d082 | 1418 | DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n"); |
bcab15c5 VZ |
1419 | bnx2x_emac_get_pfc_stat(params, pfc_frames_sent, |
1420 | pfc_frames_received); | |
bcab15c5 VZ |
1421 | } |
1422 | } | |
1423 | /******************************************************************/ | |
1424 | /* MAC/PBF section */ | |
1425 | /******************************************************************/ | |
a198c142 YR |
1426 | static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port) |
1427 | { | |
1428 | u32 mode, emac_base; | |
8f73f0b9 | 1429 | /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz |
a198c142 YR |
1430 | * (a value of 49==0x31) and make sure that the AUTO poll is off |
1431 | */ | |
1432 | ||
1433 | if (CHIP_IS_E2(bp)) | |
1434 | emac_base = GRCBASE_EMAC0; | |
1435 | else | |
1436 | emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1437 | mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | |
1438 | mode &= ~(EMAC_MDIO_MODE_AUTO_POLL | | |
1439 | EMAC_MDIO_MODE_CLOCK_CNT); | |
3c9ada22 YR |
1440 | if (USES_WARPCORE(bp)) |
1441 | mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT); | |
1442 | else | |
1443 | mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT); | |
a198c142 YR |
1444 | |
1445 | mode |= (EMAC_MDIO_MODE_CLAUSE_45); | |
1446 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode); | |
1447 | ||
1448 | udelay(40); | |
1449 | } | |
2f751a80 YR |
1450 | static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) |
1451 | { | |
1452 | u32 port4mode_ovwr_val; | |
1453 | /* Check 4-port override enabled */ | |
1454 | port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); | |
1455 | if (port4mode_ovwr_val & (1<<0)) { | |
1456 | /* Return 4-port mode override value */ | |
1457 | return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); | |
1458 | } | |
1459 | /* Return 4-port mode from input pin */ | |
1460 | return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
1461 | } | |
a198c142 | 1462 | |
ea4e040a | 1463 | static void bnx2x_emac_init(struct link_params *params, |
cd88ccee | 1464 | struct link_vars *vars) |
ea4e040a YR |
1465 | { |
1466 | /* reset and unreset the emac core */ | |
1467 | struct bnx2x *bp = params->bp; | |
1468 | u8 port = params->port; | |
1469 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1470 | u32 val; | |
1471 | u16 timeout; | |
1472 | ||
1473 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
cd88ccee | 1474 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
ea4e040a YR |
1475 | udelay(5); |
1476 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
cd88ccee | 1477 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
ea4e040a YR |
1478 | |
1479 | /* init emac - use read-modify-write */ | |
1480 | /* self clear reset */ | |
1481 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
3196a88a | 1482 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); |
ea4e040a YR |
1483 | |
1484 | timeout = 200; | |
3196a88a | 1485 | do { |
ea4e040a YR |
1486 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); |
1487 | DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); | |
1488 | if (!timeout) { | |
1489 | DP(NETIF_MSG_LINK, "EMAC timeout!\n"); | |
1490 | return; | |
1491 | } | |
1492 | timeout--; | |
3196a88a | 1493 | } while (val & EMAC_MODE_RESET); |
a198c142 | 1494 | bnx2x_set_mdio_clk(bp, params->chip_id, port); |
ea4e040a YR |
1495 | /* Set mac address */ |
1496 | val = ((params->mac_addr[0] << 8) | | |
1497 | params->mac_addr[1]); | |
3196a88a | 1498 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); |
ea4e040a YR |
1499 | |
1500 | val = ((params->mac_addr[2] << 24) | | |
1501 | (params->mac_addr[3] << 16) | | |
1502 | (params->mac_addr[4] << 8) | | |
1503 | params->mac_addr[5]); | |
3196a88a | 1504 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); |
ea4e040a YR |
1505 | } |
1506 | ||
9380bb9e YR |
1507 | static void bnx2x_set_xumac_nig(struct link_params *params, |
1508 | u16 tx_pause_en, | |
1509 | u8 enable) | |
1510 | { | |
1511 | struct bnx2x *bp = params->bp; | |
1512 | ||
1513 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, | |
1514 | enable); | |
1515 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, | |
1516 | enable); | |
1517 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : | |
1518 | NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); | |
1519 | } | |
1520 | ||
ce7c0489 YR |
1521 | static void bnx2x_umac_disable(struct link_params *params) |
1522 | { | |
1523 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1524 | struct bnx2x *bp = params->bp; | |
1525 | if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & | |
1526 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) | |
1527 | return; | |
1528 | ||
1529 | /* Disable RX and TX */ | |
1530 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0); | |
1531 | } | |
1532 | ||
9380bb9e YR |
1533 | static void bnx2x_umac_enable(struct link_params *params, |
1534 | struct link_vars *vars, u8 lb) | |
1535 | { | |
1536 | u32 val; | |
1537 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1538 | struct bnx2x *bp = params->bp; | |
1539 | /* Reset UMAC */ | |
1540 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1541 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); | |
1542 | usleep_range(1000, 1000); | |
1543 | ||
1544 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1545 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); | |
1546 | ||
1547 | DP(NETIF_MSG_LINK, "enabling UMAC\n"); | |
1548 | ||
9380bb9e YR |
1549 | /* This register opens the gate for the UMAC despite its name */ |
1550 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); | |
1551 | ||
1552 | val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | | |
1553 | UMAC_COMMAND_CONFIG_REG_PAD_EN | | |
1554 | UMAC_COMMAND_CONFIG_REG_SW_RESET | | |
1555 | UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; | |
1556 | switch (vars->line_speed) { | |
1557 | case SPEED_10: | |
1558 | val |= (0<<2); | |
1559 | break; | |
1560 | case SPEED_100: | |
1561 | val |= (1<<2); | |
1562 | break; | |
1563 | case SPEED_1000: | |
1564 | val |= (2<<2); | |
1565 | break; | |
1566 | case SPEED_2500: | |
1567 | val |= (3<<2); | |
1568 | break; | |
1569 | default: | |
1570 | DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", | |
1571 | vars->line_speed); | |
1572 | break; | |
1573 | } | |
9d5b36be YR |
1574 | if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) |
1575 | val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; | |
1576 | ||
1577 | if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
1578 | val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; | |
1579 | ||
e18c56b2 MY |
1580 | if (vars->duplex == DUPLEX_HALF) |
1581 | val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; | |
1582 | ||
9380bb9e YR |
1583 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
1584 | udelay(50); | |
1585 | ||
b8d6d082 YR |
1586 | /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ |
1587 | REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, | |
1588 | ((params->mac_addr[2] << 24) | | |
1589 | (params->mac_addr[3] << 16) | | |
1590 | (params->mac_addr[4] << 8) | | |
1591 | (params->mac_addr[5]))); | |
1592 | REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, | |
1593 | ((params->mac_addr[0] << 8) | | |
1594 | (params->mac_addr[1]))); | |
1595 | ||
9380bb9e YR |
1596 | /* Enable RX and TX */ |
1597 | val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; | |
1598 | val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | | |
3c9ada22 | 1599 | UMAC_COMMAND_CONFIG_REG_RX_ENA; |
9380bb9e YR |
1600 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
1601 | udelay(50); | |
1602 | ||
1603 | /* Remove SW Reset */ | |
1604 | val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; | |
1605 | ||
1606 | /* Check loopback mode */ | |
1607 | if (lb) | |
1608 | val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; | |
1609 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); | |
1610 | ||
8f73f0b9 | 1611 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame |
9380bb9e YR |
1612 | * length used by the MAC receive logic to check frames. |
1613 | */ | |
1614 | REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); | |
1615 | bnx2x_set_xumac_nig(params, | |
1616 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); | |
1617 | vars->mac_type = MAC_TYPE_UMAC; | |
1618 | ||
1619 | } | |
1620 | ||
9380bb9e | 1621 | /* Define the XMAC mode */ |
ce7c0489 | 1622 | static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) |
9380bb9e | 1623 | { |
ce7c0489 | 1624 | struct bnx2x *bp = params->bp; |
9380bb9e YR |
1625 | u32 is_port4mode = bnx2x_is_4_port_mode(bp); |
1626 | ||
8f73f0b9 | 1627 | /* In 4-port mode, need to set the mode only once, so if XMAC is |
2f751a80 YR |
1628 | * already out of reset, it means the mode has already been set, |
1629 | * and it must not* reset the XMAC again, since it controls both | |
1630 | * ports of the path | |
1631 | */ | |
9380bb9e | 1632 | |
ce7c0489 YR |
1633 | if ((CHIP_NUM(bp) == CHIP_NUM_57840) && |
1634 | (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
9380bb9e | 1635 | MISC_REGISTERS_RESET_REG_2_XMAC)) { |
94f05b0f JP |
1636 | DP(NETIF_MSG_LINK, |
1637 | "XMAC already out of reset in 4-port mode\n"); | |
9380bb9e YR |
1638 | return; |
1639 | } | |
1640 | ||
1641 | /* Hard reset */ | |
1642 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1643 | MISC_REGISTERS_RESET_REG_2_XMAC); | |
1644 | usleep_range(1000, 1000); | |
1645 | ||
1646 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1647 | MISC_REGISTERS_RESET_REG_2_XMAC); | |
1648 | if (is_port4mode) { | |
1649 | DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); | |
1650 | ||
8f73f0b9 | 1651 | /* Set the number of ports on the system side to up to 2 */ |
9380bb9e YR |
1652 | REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); |
1653 | ||
1654 | /* Set the number of ports on the Warp Core to 10G */ | |
1655 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); | |
1656 | } else { | |
8f73f0b9 | 1657 | /* Set the number of ports on the system side to 1 */ |
9380bb9e YR |
1658 | REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); |
1659 | if (max_speed == SPEED_10000) { | |
94f05b0f JP |
1660 | DP(NETIF_MSG_LINK, |
1661 | "Init XMAC to 10G x 1 port per path\n"); | |
9380bb9e YR |
1662 | /* Set the number of ports on the Warp Core to 10G */ |
1663 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); | |
1664 | } else { | |
94f05b0f JP |
1665 | DP(NETIF_MSG_LINK, |
1666 | "Init XMAC to 20G x 2 ports per path\n"); | |
9380bb9e YR |
1667 | /* Set the number of ports on the Warp Core to 20G */ |
1668 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); | |
1669 | } | |
1670 | } | |
1671 | /* Soft reset */ | |
1672 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1673 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); | |
1674 | usleep_range(1000, 1000); | |
1675 | ||
1676 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1677 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); | |
1678 | ||
1679 | } | |
1680 | ||
1681 | static void bnx2x_xmac_disable(struct link_params *params) | |
1682 | { | |
1683 | u8 port = params->port; | |
1684 | struct bnx2x *bp = params->bp; | |
b5077662 | 1685 | u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; |
9380bb9e YR |
1686 | |
1687 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
1688 | MISC_REGISTERS_RESET_REG_2_XMAC) { | |
8f73f0b9 | 1689 | /* Send an indication to change the state in the NIG back to XON |
b5077662 YR |
1690 | * Clearing this bit enables the next set of this bit to get |
1691 | * rising edge | |
1692 | */ | |
1693 | pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); | |
1694 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, | |
1695 | (pfc_ctrl & ~(1<<1))); | |
1696 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, | |
1697 | (pfc_ctrl | (1<<1))); | |
9380bb9e YR |
1698 | DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); |
1699 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0); | |
9380bb9e YR |
1700 | } |
1701 | } | |
1702 | ||
1703 | static int bnx2x_xmac_enable(struct link_params *params, | |
1704 | struct link_vars *vars, u8 lb) | |
1705 | { | |
1706 | u32 val, xmac_base; | |
1707 | struct bnx2x *bp = params->bp; | |
1708 | DP(NETIF_MSG_LINK, "enabling XMAC\n"); | |
1709 | ||
1710 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1711 | ||
ce7c0489 | 1712 | bnx2x_xmac_init(params, vars->line_speed); |
9380bb9e | 1713 | |
8f73f0b9 | 1714 | /* This register determines on which events the MAC will assert |
9380bb9e YR |
1715 | * error on the i/f to the NIG along w/ EOP. |
1716 | */ | |
1717 | ||
8f73f0b9 | 1718 | /* This register tells the NIG whether to send traffic to UMAC |
9380bb9e YR |
1719 | * or XMAC |
1720 | */ | |
1721 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); | |
1722 | ||
1723 | /* Set Max packet size */ | |
1724 | REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); | |
1725 | ||
1726 | /* CRC append for Tx packets */ | |
1727 | REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); | |
1728 | ||
1729 | /* update PFC */ | |
1730 | bnx2x_update_pfc_xmac(params, vars, 0); | |
1731 | ||
1732 | /* Enable TX and RX */ | |
1733 | val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; | |
1734 | ||
1735 | /* Check loopback mode */ | |
1736 | if (lb) | |
4d7e25d6 | 1737 | val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; |
9380bb9e YR |
1738 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); |
1739 | bnx2x_set_xumac_nig(params, | |
1740 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); | |
1741 | ||
1742 | vars->mac_type = MAC_TYPE_XMAC; | |
1743 | ||
1744 | return 0; | |
1745 | } | |
2f751a80 | 1746 | |
fcf5b650 | 1747 | static int bnx2x_emac_enable(struct link_params *params, |
9045f6b4 | 1748 | struct link_vars *vars, u8 lb) |
ea4e040a YR |
1749 | { |
1750 | struct bnx2x *bp = params->bp; | |
1751 | u8 port = params->port; | |
1752 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1753 | u32 val; | |
1754 | ||
1755 | DP(NETIF_MSG_LINK, "enabling EMAC\n"); | |
1756 | ||
de6f3377 YR |
1757 | /* Disable BMAC */ |
1758 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1759 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
1760 | ||
ea4e040a YR |
1761 | /* enable emac and not bmac */ |
1762 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); | |
1763 | ||
ea4e040a YR |
1764 | /* ASIC */ |
1765 | if (vars->phy_flags & PHY_XGXS_FLAG) { | |
1766 | u32 ser_lane = ((params->lane_config & | |
cd88ccee YR |
1767 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
1768 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
ea4e040a YR |
1769 | |
1770 | DP(NETIF_MSG_LINK, "XGXS\n"); | |
1771 | /* select the master lanes (out of 0-3) */ | |
cd88ccee | 1772 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); |
ea4e040a | 1773 | /* select XGXS */ |
cd88ccee | 1774 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); |
ea4e040a YR |
1775 | |
1776 | } else { /* SerDes */ | |
1777 | DP(NETIF_MSG_LINK, "SerDes\n"); | |
1778 | /* select SerDes */ | |
cd88ccee | 1779 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); |
ea4e040a YR |
1780 | } |
1781 | ||
811a2f2d | 1782 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, |
cd88ccee | 1783 | EMAC_RX_MODE_RESET); |
811a2f2d | 1784 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, |
cd88ccee | 1785 | EMAC_TX_MODE_RESET); |
ea4e040a YR |
1786 | |
1787 | if (CHIP_REV_IS_SLOW(bp)) { | |
1788 | /* config GMII mode */ | |
1789 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
cd88ccee | 1790 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII)); |
ea4e040a YR |
1791 | } else { /* ASIC */ |
1792 | /* pause enable/disable */ | |
1793 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, | |
1794 | EMAC_RX_MODE_FLOW_EN); | |
ea4e040a YR |
1795 | |
1796 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
bcab15c5 VZ |
1797 | (EMAC_TX_MODE_EXT_PAUSE_EN | |
1798 | EMAC_TX_MODE_FLOW_EN)); | |
1799 | if (!(params->feature_config_flags & | |
1800 | FEATURE_CONFIG_PFC_ENABLED)) { | |
1801 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) | |
1802 | bnx2x_bits_en(bp, emac_base + | |
1803 | EMAC_REG_EMAC_RX_MODE, | |
1804 | EMAC_RX_MODE_FLOW_EN); | |
1805 | ||
1806 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
1807 | bnx2x_bits_en(bp, emac_base + | |
1808 | EMAC_REG_EMAC_TX_MODE, | |
1809 | (EMAC_TX_MODE_EXT_PAUSE_EN | | |
1810 | EMAC_TX_MODE_FLOW_EN)); | |
1811 | } else | |
1812 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
1813 | EMAC_TX_MODE_FLOW_EN); | |
ea4e040a YR |
1814 | } |
1815 | ||
1816 | /* KEEP_VLAN_TAG, promiscuous */ | |
1817 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); | |
1818 | val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; | |
bcab15c5 | 1819 | |
8f73f0b9 | 1820 | /* Setting this bit causes MAC control frames (except for pause |
2cf7acf9 YR |
1821 | * frames) to be passed on for processing. This setting has no |
1822 | * affect on the operation of the pause frames. This bit effects | |
1823 | * all packets regardless of RX Parser packet sorting logic. | |
1824 | * Turn the PFC off to make sure we are in Xon state before | |
1825 | * enabling it. | |
1826 | */ | |
bcab15c5 VZ |
1827 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); |
1828 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { | |
1829 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); | |
1830 | /* Enable PFC again */ | |
1831 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, | |
1832 | EMAC_REG_RX_PFC_MODE_RX_EN | | |
1833 | EMAC_REG_RX_PFC_MODE_TX_EN | | |
1834 | EMAC_REG_RX_PFC_MODE_PRIORITIES); | |
1835 | ||
1836 | EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, | |
1837 | ((0x0101 << | |
1838 | EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | | |
1839 | (0x00ff << | |
1840 | EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); | |
1841 | val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; | |
1842 | } | |
3196a88a | 1843 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); |
ea4e040a YR |
1844 | |
1845 | /* Set Loopback */ | |
1846 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
1847 | if (lb) | |
1848 | val |= 0x810; | |
1849 | else | |
1850 | val &= ~0x810; | |
3196a88a | 1851 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); |
ea4e040a | 1852 | |
6c55c3cd EG |
1853 | /* enable emac */ |
1854 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); | |
1855 | ||
ea4e040a | 1856 | /* enable emac for jumbo packets */ |
3196a88a | 1857 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, |
ea4e040a YR |
1858 | (EMAC_RX_MTU_SIZE_JUMBO_ENA | |
1859 | (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); | |
1860 | ||
1861 | /* strip CRC */ | |
1862 | REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); | |
1863 | ||
1864 | /* disable the NIG in/out to the bmac */ | |
1865 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); | |
1866 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
1867 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); | |
1868 | ||
1869 | /* enable the NIG in/out to the emac */ | |
1870 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); | |
1871 | val = 0; | |
bcab15c5 VZ |
1872 | if ((params->feature_config_flags & |
1873 | FEATURE_CONFIG_PFC_ENABLED) || | |
1874 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
ea4e040a YR |
1875 | val = 1; |
1876 | ||
1877 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); | |
1878 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); | |
1879 | ||
02a23165 | 1880 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); |
ea4e040a YR |
1881 | |
1882 | vars->mac_type = MAC_TYPE_EMAC; | |
1883 | return 0; | |
1884 | } | |
1885 | ||
bcab15c5 VZ |
1886 | static void bnx2x_update_pfc_bmac1(struct link_params *params, |
1887 | struct link_vars *vars) | |
1888 | { | |
1889 | u32 wb_data[2]; | |
1890 | struct bnx2x *bp = params->bp; | |
1891 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
1892 | NIG_REG_INGRESS_BMAC0_MEM; | |
1893 | ||
1894 | u32 val = 0x14; | |
1895 | if ((!(params->feature_config_flags & | |
1896 | FEATURE_CONFIG_PFC_ENABLED)) && | |
1897 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
1898 | /* Enable BigMAC to react on received Pause packets */ | |
1899 | val |= (1<<5); | |
1900 | wb_data[0] = val; | |
1901 | wb_data[1] = 0; | |
1902 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); | |
1903 | ||
1904 | /* tx control */ | |
1905 | val = 0xc0; | |
1906 | if (!(params->feature_config_flags & | |
1907 | FEATURE_CONFIG_PFC_ENABLED) && | |
1908 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
1909 | val |= 0x800000; | |
1910 | wb_data[0] = val; | |
1911 | wb_data[1] = 0; | |
1912 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); | |
1913 | } | |
1914 | ||
1915 | static void bnx2x_update_pfc_bmac2(struct link_params *params, | |
1916 | struct link_vars *vars, | |
1917 | u8 is_lb) | |
f2e0899f | 1918 | { |
8f73f0b9 | 1919 | /* Set rx control: Strip CRC and enable BigMAC to relay |
f2e0899f DK |
1920 | * control packets to the system as well |
1921 | */ | |
1922 | u32 wb_data[2]; | |
1923 | struct bnx2x *bp = params->bp; | |
1924 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
1925 | NIG_REG_INGRESS_BMAC0_MEM; | |
1926 | u32 val = 0x14; | |
ea4e040a | 1927 | |
bcab15c5 VZ |
1928 | if ((!(params->feature_config_flags & |
1929 | FEATURE_CONFIG_PFC_ENABLED)) && | |
1930 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
f2e0899f DK |
1931 | /* Enable BigMAC to react on received Pause packets */ |
1932 | val |= (1<<5); | |
1933 | wb_data[0] = val; | |
1934 | wb_data[1] = 0; | |
cd88ccee | 1935 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); |
f2e0899f | 1936 | udelay(30); |
ea4e040a | 1937 | |
f2e0899f DK |
1938 | /* Tx control */ |
1939 | val = 0xc0; | |
bcab15c5 VZ |
1940 | if (!(params->feature_config_flags & |
1941 | FEATURE_CONFIG_PFC_ENABLED) && | |
1942 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
f2e0899f DK |
1943 | val |= 0x800000; |
1944 | wb_data[0] = val; | |
1945 | wb_data[1] = 0; | |
bcab15c5 VZ |
1946 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); |
1947 | ||
1948 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { | |
1949 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); | |
1950 | /* Enable PFC RX & TX & STATS and set 8 COS */ | |
1951 | wb_data[0] = 0x0; | |
1952 | wb_data[0] |= (1<<0); /* RX */ | |
1953 | wb_data[0] |= (1<<1); /* TX */ | |
1954 | wb_data[0] |= (1<<2); /* Force initial Xon */ | |
1955 | wb_data[0] |= (1<<3); /* 8 cos */ | |
1956 | wb_data[0] |= (1<<5); /* STATS */ | |
1957 | wb_data[1] = 0; | |
1958 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, | |
1959 | wb_data, 2); | |
1960 | /* Clear the force Xon */ | |
1961 | wb_data[0] &= ~(1<<2); | |
1962 | } else { | |
1963 | DP(NETIF_MSG_LINK, "PFC is disabled\n"); | |
1964 | /* disable PFC RX & TX & STATS and set 8 COS */ | |
1965 | wb_data[0] = 0x8; | |
1966 | wb_data[1] = 0; | |
1967 | } | |
1968 | ||
1969 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); | |
f2e0899f | 1970 | |
8f73f0b9 | 1971 | /* Set Time (based unit is 512 bit time) between automatic |
2cf7acf9 YR |
1972 | * re-sending of PP packets amd enable automatic re-send of |
1973 | * Per-Priroity Packet as long as pp_gen is asserted and | |
1974 | * pp_disable is low. | |
1975 | */ | |
f2e0899f | 1976 | val = 0x8000; |
bcab15c5 VZ |
1977 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
1978 | val |= (1<<16); /* enable automatic re-send */ | |
1979 | ||
f2e0899f DK |
1980 | wb_data[0] = val; |
1981 | wb_data[1] = 0; | |
1982 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, | |
cd88ccee | 1983 | wb_data, 2); |
f2e0899f DK |
1984 | |
1985 | /* mac control */ | |
1986 | val = 0x3; /* Enable RX and TX */ | |
1987 | if (is_lb) { | |
1988 | val |= 0x4; /* Local loopback */ | |
1989 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
1990 | } | |
bcab15c5 VZ |
1991 | /* When PFC enabled, Pass pause frames towards the NIG. */ |
1992 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
1993 | val |= ((1<<6)|(1<<5)); | |
f2e0899f DK |
1994 | |
1995 | wb_data[0] = val; | |
1996 | wb_data[1] = 0; | |
cd88ccee | 1997 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
f2e0899f DK |
1998 | } |
1999 | ||
9380bb9e YR |
2000 | /* PFC BRB internal port configuration params */ |
2001 | struct bnx2x_pfc_brb_threshold_val { | |
2002 | u32 pause_xoff; | |
2003 | u32 pause_xon; | |
2004 | u32 full_xoff; | |
2005 | u32 full_xon; | |
2006 | }; | |
2007 | ||
2008 | struct bnx2x_pfc_brb_e3b0_val { | |
866cedae YR |
2009 | u32 per_class_guaranty_mode; |
2010 | u32 lb_guarantied_hyst; | |
9380bb9e YR |
2011 | u32 full_lb_xoff_th; |
2012 | u32 full_lb_xon_threshold; | |
2013 | u32 lb_guarantied; | |
2014 | u32 mac_0_class_t_guarantied; | |
2015 | u32 mac_0_class_t_guarantied_hyst; | |
2016 | u32 mac_1_class_t_guarantied; | |
2017 | u32 mac_1_class_t_guarantied_hyst; | |
2018 | }; | |
2019 | ||
2020 | struct bnx2x_pfc_brb_th_val { | |
2021 | struct bnx2x_pfc_brb_threshold_val pauseable_th; | |
2022 | struct bnx2x_pfc_brb_threshold_val non_pauseable_th; | |
866cedae YR |
2023 | struct bnx2x_pfc_brb_threshold_val default_class0; |
2024 | struct bnx2x_pfc_brb_threshold_val default_class1; | |
2025 | ||
9380bb9e YR |
2026 | }; |
2027 | static int bnx2x_pfc_brb_get_config_params( | |
2028 | struct link_params *params, | |
2029 | struct bnx2x_pfc_brb_th_val *config_val) | |
2030 | { | |
2031 | struct bnx2x *bp = params->bp; | |
2032 | DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n"); | |
866cedae YR |
2033 | |
2034 | config_val->default_class1.pause_xoff = 0; | |
2035 | config_val->default_class1.pause_xon = 0; | |
2036 | config_val->default_class1.full_xoff = 0; | |
2037 | config_val->default_class1.full_xon = 0; | |
2038 | ||
9380bb9e | 2039 | if (CHIP_IS_E2(bp)) { |
8f73f0b9 | 2040 | /* Class0 defaults */ |
866cedae YR |
2041 | config_val->default_class0.pause_xoff = |
2042 | DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR; | |
2043 | config_val->default_class0.pause_xon = | |
2f751a80 | 2044 | DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR; |
866cedae | 2045 | config_val->default_class0.full_xoff = |
2f751a80 | 2046 | DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR; |
866cedae | 2047 | config_val->default_class0.full_xon = |
2f751a80 | 2048 | DEFAULT0_E2_BRB_MAC_FULL_XON_THR; |
8f73f0b9 | 2049 | /* Pause able*/ |
9380bb9e | 2050 | config_val->pauseable_th.pause_xoff = |
2f751a80 | 2051 | PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE; |
9380bb9e | 2052 | config_val->pauseable_th.pause_xon = |
2f751a80 | 2053 | PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE; |
9380bb9e | 2054 | config_val->pauseable_th.full_xoff = |
2f751a80 | 2055 | PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE; |
9380bb9e | 2056 | config_val->pauseable_th.full_xon = |
2f751a80 | 2057 | PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE; |
9380bb9e YR |
2058 | /* non pause able*/ |
2059 | config_val->non_pauseable_th.pause_xoff = | |
2f751a80 | 2060 | PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; |
9380bb9e | 2061 | config_val->non_pauseable_th.pause_xon = |
2f751a80 | 2062 | PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE; |
9380bb9e | 2063 | config_val->non_pauseable_th.full_xoff = |
2f751a80 | 2064 | PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE; |
9380bb9e | 2065 | config_val->non_pauseable_th.full_xon = |
2f751a80 | 2066 | PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE; |
9380bb9e | 2067 | } else if (CHIP_IS_E3A0(bp)) { |
8f73f0b9 | 2068 | /* Class0 defaults */ |
866cedae YR |
2069 | config_val->default_class0.pause_xoff = |
2070 | DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR; | |
2071 | config_val->default_class0.pause_xon = | |
2f751a80 | 2072 | DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR; |
866cedae | 2073 | config_val->default_class0.full_xoff = |
2f751a80 | 2074 | DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR; |
866cedae | 2075 | config_val->default_class0.full_xon = |
2f751a80 | 2076 | DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR; |
8f73f0b9 | 2077 | /* Pause able */ |
9380bb9e | 2078 | config_val->pauseable_th.pause_xoff = |
2f751a80 | 2079 | PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE; |
9380bb9e | 2080 | config_val->pauseable_th.pause_xon = |
2f751a80 | 2081 | PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE; |
9380bb9e | 2082 | config_val->pauseable_th.full_xoff = |
2f751a80 | 2083 | PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE; |
9380bb9e | 2084 | config_val->pauseable_th.full_xon = |
2f751a80 | 2085 | PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE; |
9380bb9e YR |
2086 | /* non pause able*/ |
2087 | config_val->non_pauseable_th.pause_xoff = | |
2f751a80 | 2088 | PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; |
9380bb9e | 2089 | config_val->non_pauseable_th.pause_xon = |
2f751a80 | 2090 | PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE; |
9380bb9e | 2091 | config_val->non_pauseable_th.full_xoff = |
2f751a80 | 2092 | PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE; |
9380bb9e | 2093 | config_val->non_pauseable_th.full_xon = |
2f751a80 | 2094 | PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE; |
9380bb9e | 2095 | } else if (CHIP_IS_E3B0(bp)) { |
8f73f0b9 | 2096 | /* Class0 defaults */ |
866cedae YR |
2097 | config_val->default_class0.pause_xoff = |
2098 | DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR; | |
2099 | config_val->default_class0.pause_xon = | |
2100 | DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR; | |
2101 | config_val->default_class0.full_xoff = | |
2102 | DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR; | |
2103 | config_val->default_class0.full_xon = | |
2104 | DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR; | |
2105 | ||
9380bb9e | 2106 | if (params->phy[INT_PHY].flags & |
2f751a80 | 2107 | FLAGS_4_PORT_MODE) { |
9380bb9e | 2108 | config_val->pauseable_th.pause_xoff = |
866cedae | 2109 | PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE; |
9380bb9e | 2110 | config_val->pauseable_th.pause_xon = |
866cedae | 2111 | PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE; |
9380bb9e | 2112 | config_val->pauseable_th.full_xoff = |
866cedae | 2113 | PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE; |
9380bb9e | 2114 | config_val->pauseable_th.full_xon = |
866cedae | 2115 | PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE; |
9380bb9e YR |
2116 | /* non pause able*/ |
2117 | config_val->non_pauseable_th.pause_xoff = | |
866cedae | 2118 | PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; |
9380bb9e | 2119 | config_val->non_pauseable_th.pause_xon = |
866cedae | 2120 | PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE; |
9380bb9e | 2121 | config_val->non_pauseable_th.full_xoff = |
866cedae | 2122 | PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE; |
9380bb9e | 2123 | config_val->non_pauseable_th.full_xon = |
866cedae YR |
2124 | PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE; |
2125 | } else { | |
2126 | config_val->pauseable_th.pause_xoff = | |
2127 | PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE; | |
2128 | config_val->pauseable_th.pause_xon = | |
2f751a80 YR |
2129 | PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE; |
2130 | config_val->pauseable_th.full_xoff = | |
2131 | PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE; | |
2132 | config_val->pauseable_th.full_xon = | |
2133 | PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE; | |
2134 | /* non pause able*/ | |
2135 | config_val->non_pauseable_th.pause_xoff = | |
2136 | PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; | |
2137 | config_val->non_pauseable_th.pause_xon = | |
2138 | PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE; | |
2139 | config_val->non_pauseable_th.full_xoff = | |
2140 | PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE; | |
2141 | config_val->non_pauseable_th.full_xon = | |
2142 | PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE; | |
2143 | } | |
9380bb9e YR |
2144 | } else |
2145 | return -EINVAL; | |
2146 | ||
2147 | return 0; | |
2148 | } | |
2149 | ||
866cedae YR |
2150 | static void bnx2x_pfc_brb_get_e3b0_config_params( |
2151 | struct link_params *params, | |
2152 | struct bnx2x_pfc_brb_e3b0_val | |
2153 | *e3b0_val, | |
2154 | struct bnx2x_nig_brb_pfc_port_params *pfc_params, | |
2155 | const u8 pfc_enabled) | |
9380bb9e | 2156 | { |
866cedae YR |
2157 | if (pfc_enabled && pfc_params) { |
2158 | e3b0_val->per_class_guaranty_mode = 1; | |
2159 | e3b0_val->lb_guarantied_hyst = 80; | |
2160 | ||
2161 | if (params->phy[INT_PHY].flags & | |
2162 | FLAGS_4_PORT_MODE) { | |
2163 | e3b0_val->full_lb_xoff_th = | |
2164 | PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR; | |
2165 | e3b0_val->full_lb_xon_threshold = | |
2166 | PFC_E3B0_4P_BRB_FULL_LB_XON_THR; | |
2167 | e3b0_val->lb_guarantied = | |
2168 | PFC_E3B0_4P_LB_GUART; | |
2169 | e3b0_val->mac_0_class_t_guarantied = | |
2170 | PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART; | |
2171 | e3b0_val->mac_0_class_t_guarantied_hyst = | |
2172 | PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST; | |
2173 | e3b0_val->mac_1_class_t_guarantied = | |
2174 | PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART; | |
2175 | e3b0_val->mac_1_class_t_guarantied_hyst = | |
2176 | PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST; | |
2177 | } else { | |
2178 | e3b0_val->full_lb_xoff_th = | |
2179 | PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR; | |
2180 | e3b0_val->full_lb_xon_threshold = | |
2181 | PFC_E3B0_2P_BRB_FULL_LB_XON_THR; | |
2182 | e3b0_val->mac_0_class_t_guarantied_hyst = | |
2183 | PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST; | |
2184 | e3b0_val->mac_1_class_t_guarantied = | |
2185 | PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART; | |
2186 | e3b0_val->mac_1_class_t_guarantied_hyst = | |
2187 | PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST; | |
2188 | ||
2189 | if (pfc_params->cos0_pauseable != | |
2190 | pfc_params->cos1_pauseable) { | |
2191 | /* nonpauseable= Lossy + pauseable = Lossless*/ | |
2192 | e3b0_val->lb_guarantied = | |
2193 | PFC_E3B0_2P_MIX_PAUSE_LB_GUART; | |
2194 | e3b0_val->mac_0_class_t_guarantied = | |
2195 | PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART; | |
2196 | } else if (pfc_params->cos0_pauseable) { | |
2197 | /* Lossless +Lossless*/ | |
2198 | e3b0_val->lb_guarantied = | |
2199 | PFC_E3B0_2P_PAUSE_LB_GUART; | |
2200 | e3b0_val->mac_0_class_t_guarantied = | |
2201 | PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART; | |
2202 | } else { | |
2203 | /* Lossy +Lossy*/ | |
2204 | e3b0_val->lb_guarantied = | |
2205 | PFC_E3B0_2P_NON_PAUSE_LB_GUART; | |
2206 | e3b0_val->mac_0_class_t_guarantied = | |
2207 | PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART; | |
2208 | } | |
2209 | } | |
2210 | } else { | |
2211 | e3b0_val->per_class_guaranty_mode = 0; | |
2212 | e3b0_val->lb_guarantied_hyst = 0; | |
9380bb9e | 2213 | e3b0_val->full_lb_xoff_th = |
866cedae | 2214 | DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR; |
9380bb9e | 2215 | e3b0_val->full_lb_xon_threshold = |
866cedae | 2216 | DEFAULT_E3B0_BRB_FULL_LB_XON_THR; |
9380bb9e | 2217 | e3b0_val->lb_guarantied = |
866cedae | 2218 | DEFAULT_E3B0_LB_GUART; |
9380bb9e | 2219 | e3b0_val->mac_0_class_t_guarantied = |
866cedae | 2220 | DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART; |
9380bb9e | 2221 | e3b0_val->mac_0_class_t_guarantied_hyst = |
866cedae | 2222 | DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST; |
9380bb9e | 2223 | e3b0_val->mac_1_class_t_guarantied = |
866cedae | 2224 | DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART; |
9380bb9e | 2225 | e3b0_val->mac_1_class_t_guarantied_hyst = |
866cedae | 2226 | DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST; |
9380bb9e YR |
2227 | } |
2228 | } | |
2229 | static int bnx2x_update_pfc_brb(struct link_params *params, | |
2230 | struct link_vars *vars, | |
2231 | struct bnx2x_nig_brb_pfc_port_params | |
2232 | *pfc_params) | |
bcab15c5 VZ |
2233 | { |
2234 | struct bnx2x *bp = params->bp; | |
9380bb9e YR |
2235 | struct bnx2x_pfc_brb_th_val config_val = { {0} }; |
2236 | struct bnx2x_pfc_brb_threshold_val *reg_th_config = | |
2f751a80 | 2237 | &config_val.pauseable_th; |
9380bb9e | 2238 | struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0}; |
866cedae | 2239 | const int set_pfc = params->feature_config_flags & |
bcab15c5 | 2240 | FEATURE_CONFIG_PFC_ENABLED; |
866cedae | 2241 | const u8 pfc_enabled = (set_pfc && pfc_params); |
9380bb9e YR |
2242 | int bnx2x_status = 0; |
2243 | u8 port = params->port; | |
bcab15c5 VZ |
2244 | |
2245 | /* default - pause configuration */ | |
9380bb9e YR |
2246 | reg_th_config = &config_val.pauseable_th; |
2247 | bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val); | |
de0396f4 | 2248 | if (bnx2x_status) |
9380bb9e | 2249 | return bnx2x_status; |
bcab15c5 | 2250 | |
866cedae | 2251 | if (pfc_enabled) { |
bcab15c5 | 2252 | /* First COS */ |
866cedae YR |
2253 | if (pfc_params->cos0_pauseable) |
2254 | reg_th_config = &config_val.pauseable_th; | |
2255 | else | |
9380bb9e | 2256 | reg_th_config = &config_val.non_pauseable_th; |
866cedae YR |
2257 | } else |
2258 | reg_th_config = &config_val.default_class0; | |
8f73f0b9 | 2259 | /* The number of free blocks below which the pause signal to class 0 |
2cf7acf9 YR |
2260 | * of MAC #n is asserted. n=0,1 |
2261 | */ | |
9380bb9e YR |
2262 | REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 : |
2263 | BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , | |
2264 | reg_th_config->pause_xoff); | |
8f73f0b9 | 2265 | /* The number of free blocks above which the pause signal to class 0 |
2cf7acf9 YR |
2266 | * of MAC #n is de-asserted. n=0,1 |
2267 | */ | |
9380bb9e YR |
2268 | REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 : |
2269 | BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon); | |
8f73f0b9 | 2270 | /* The number of free blocks below which the full signal to class 0 |
2cf7acf9 YR |
2271 | * of MAC #n is asserted. n=0,1 |
2272 | */ | |
9380bb9e YR |
2273 | REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 : |
2274 | BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff); | |
8f73f0b9 | 2275 | /* The number of free blocks above which the full signal to class 0 |
2cf7acf9 YR |
2276 | * of MAC #n is de-asserted. n=0,1 |
2277 | */ | |
9380bb9e YR |
2278 | REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 : |
2279 | BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon); | |
bcab15c5 | 2280 | |
866cedae | 2281 | if (pfc_enabled) { |
bcab15c5 | 2282 | /* Second COS */ |
9380bb9e YR |
2283 | if (pfc_params->cos1_pauseable) |
2284 | reg_th_config = &config_val.pauseable_th; | |
2285 | else | |
2286 | reg_th_config = &config_val.non_pauseable_th; | |
866cedae YR |
2287 | } else |
2288 | reg_th_config = &config_val.default_class1; | |
8f73f0b9 | 2289 | /* The number of free blocks below which the pause signal to |
2f751a80 YR |
2290 | * class 1 of MAC #n is asserted. n=0,1 |
2291 | */ | |
2292 | REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 : | |
2293 | BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, | |
2294 | reg_th_config->pause_xoff); | |
2295 | ||
8f73f0b9 | 2296 | /* The number of free blocks above which the pause signal to |
2f751a80 YR |
2297 | * class 1 of MAC #n is de-asserted. n=0,1 |
2298 | */ | |
2299 | REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 : | |
2300 | BRB1_REG_PAUSE_1_XON_THRESHOLD_0, | |
2301 | reg_th_config->pause_xon); | |
8f73f0b9 | 2302 | /* The number of free blocks below which the full signal to |
2f751a80 YR |
2303 | * class 1 of MAC #n is asserted. n=0,1 |
2304 | */ | |
2305 | REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 : | |
2306 | BRB1_REG_FULL_1_XOFF_THRESHOLD_0, | |
2307 | reg_th_config->full_xoff); | |
8f73f0b9 | 2308 | /* The number of free blocks above which the full signal to |
2f751a80 YR |
2309 | * class 1 of MAC #n is de-asserted. n=0,1 |
2310 | */ | |
2311 | REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 : | |
2312 | BRB1_REG_FULL_1_XON_THRESHOLD_0, | |
2313 | reg_th_config->full_xon); | |
9380bb9e | 2314 | |
866cedae YR |
2315 | if (CHIP_IS_E3B0(bp)) { |
2316 | bnx2x_pfc_brb_get_e3b0_config_params( | |
2317 | params, | |
2318 | &e3b0_val, | |
2319 | pfc_params, | |
2320 | pfc_enabled); | |
9380bb9e | 2321 | |
866cedae YR |
2322 | REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE, |
2323 | e3b0_val.per_class_guaranty_mode); | |
9380bb9e | 2324 | |
8f73f0b9 | 2325 | /* The hysteresis on the guarantied buffer space for the Lb |
2f751a80 YR |
2326 | * port before signaling XON. |
2327 | */ | |
866cedae YR |
2328 | REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, |
2329 | e3b0_val.lb_guarantied_hyst); | |
2f751a80 | 2330 | |
8f73f0b9 | 2331 | /* The number of free blocks below which the full signal to the |
2f751a80 YR |
2332 | * LB port is asserted. |
2333 | */ | |
866cedae | 2334 | REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, |
2f751a80 | 2335 | e3b0_val.full_lb_xoff_th); |
8f73f0b9 | 2336 | /* The number of free blocks above which the full signal to the |
2f751a80 YR |
2337 | * LB port is de-asserted. |
2338 | */ | |
2339 | REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, | |
2340 | e3b0_val.full_lb_xon_threshold); | |
8f73f0b9 | 2341 | /* The number of blocks guarantied for the MAC #n port. n=0,1 |
2f751a80 YR |
2342 | */ |
2343 | ||
8f73f0b9 | 2344 | /* The number of blocks guarantied for the LB port. */ |
2f751a80 YR |
2345 | REG_WR(bp, BRB1_REG_LB_GUARANTIED, |
2346 | e3b0_val.lb_guarantied); | |
2347 | ||
8f73f0b9 | 2348 | /* The number of blocks guarantied for the MAC #n port. */ |
2f751a80 YR |
2349 | REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0, |
2350 | 2 * e3b0_val.mac_0_class_t_guarantied); | |
2351 | REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1, | |
2352 | 2 * e3b0_val.mac_1_class_t_guarantied); | |
8f73f0b9 | 2353 | /* The number of blocks guarantied for class #t in MAC0. t=0,1 |
2f751a80 YR |
2354 | */ |
2355 | REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED, | |
2356 | e3b0_val.mac_0_class_t_guarantied); | |
2357 | REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED, | |
2358 | e3b0_val.mac_0_class_t_guarantied); | |
8f73f0b9 | 2359 | /* The hysteresis on the guarantied buffer space for class in |
2f751a80 YR |
2360 | * MAC0. t=0,1 |
2361 | */ | |
2362 | REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST, | |
2363 | e3b0_val.mac_0_class_t_guarantied_hyst); | |
2364 | REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST, | |
2365 | e3b0_val.mac_0_class_t_guarantied_hyst); | |
2366 | ||
8f73f0b9 | 2367 | /* The number of blocks guarantied for class #t in MAC1.t=0,1 |
2f751a80 YR |
2368 | */ |
2369 | REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED, | |
2370 | e3b0_val.mac_1_class_t_guarantied); | |
2371 | REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED, | |
2372 | e3b0_val.mac_1_class_t_guarantied); | |
8f73f0b9 | 2373 | /* The hysteresis on the guarantied buffer space for class #t |
2f751a80 YR |
2374 | * in MAC1. t=0,1 |
2375 | */ | |
2376 | REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST, | |
2377 | e3b0_val.mac_1_class_t_guarantied_hyst); | |
2378 | REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST, | |
2379 | e3b0_val.mac_1_class_t_guarantied_hyst); | |
2380 | } | |
9380bb9e | 2381 | |
9380bb9e | 2382 | return bnx2x_status; |
bcab15c5 VZ |
2383 | } |
2384 | ||
619c5cb6 VZ |
2385 | /****************************************************************************** |
2386 | * Description: | |
2387 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are | |
2388 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. | |
2389 | ******************************************************************************/ | |
2390 | int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, | |
2391 | u8 cos_entry, | |
2392 | u32 priority_mask, u8 port) | |
2393 | { | |
2394 | u32 nig_reg_rx_priority_mask_add = 0; | |
2395 | ||
2396 | switch (cos_entry) { | |
2397 | case 0: | |
2398 | nig_reg_rx_priority_mask_add = (port) ? | |
2399 | NIG_REG_P1_RX_COS0_PRIORITY_MASK : | |
2400 | NIG_REG_P0_RX_COS0_PRIORITY_MASK; | |
2401 | break; | |
2402 | case 1: | |
2403 | nig_reg_rx_priority_mask_add = (port) ? | |
2404 | NIG_REG_P1_RX_COS1_PRIORITY_MASK : | |
2405 | NIG_REG_P0_RX_COS1_PRIORITY_MASK; | |
2406 | break; | |
2407 | case 2: | |
2408 | nig_reg_rx_priority_mask_add = (port) ? | |
2409 | NIG_REG_P1_RX_COS2_PRIORITY_MASK : | |
2410 | NIG_REG_P0_RX_COS2_PRIORITY_MASK; | |
2411 | break; | |
2412 | case 3: | |
2413 | if (port) | |
2414 | return -EINVAL; | |
2415 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; | |
2416 | break; | |
2417 | case 4: | |
2418 | if (port) | |
2419 | return -EINVAL; | |
2420 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; | |
2421 | break; | |
2422 | case 5: | |
2423 | if (port) | |
2424 | return -EINVAL; | |
2425 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; | |
2426 | break; | |
2427 | } | |
2428 | ||
2429 | REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); | |
2430 | ||
2431 | return 0; | |
2432 | } | |
b8d6d082 YR |
2433 | static void bnx2x_update_mng(struct link_params *params, u32 link_status) |
2434 | { | |
2435 | struct bnx2x *bp = params->bp; | |
2436 | ||
2437 | REG_WR(bp, params->shmem_base + | |
2438 | offsetof(struct shmem_region, | |
2439 | port_mb[params->port].link_status), link_status); | |
2440 | } | |
2441 | ||
bcab15c5 VZ |
2442 | static void bnx2x_update_pfc_nig(struct link_params *params, |
2443 | struct link_vars *vars, | |
2444 | struct bnx2x_nig_brb_pfc_port_params *nig_params) | |
2445 | { | |
2446 | u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; | |
127302bb | 2447 | u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; |
bcab15c5 | 2448 | u32 pkt_priority_to_cos = 0; |
bcab15c5 | 2449 | struct bnx2x *bp = params->bp; |
9380bb9e YR |
2450 | u8 port = params->port; |
2451 | ||
bcab15c5 VZ |
2452 | int set_pfc = params->feature_config_flags & |
2453 | FEATURE_CONFIG_PFC_ENABLED; | |
2454 | DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); | |
2455 | ||
8f73f0b9 | 2456 | /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set |
bcab15c5 VZ |
2457 | * MAC control frames (that are not pause packets) |
2458 | * will be forwarded to the XCM. | |
2459 | */ | |
127302bb YR |
2460 | xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : |
2461 | NIG_REG_LLH0_XCM_MASK); | |
8f73f0b9 | 2462 | /* NIG params will override non PFC params, since it's possible to |
bcab15c5 VZ |
2463 | * do transition from PFC to SAFC |
2464 | */ | |
2465 | if (set_pfc) { | |
2466 | pause_enable = 0; | |
2467 | llfc_out_en = 0; | |
2468 | llfc_enable = 0; | |
9380bb9e YR |
2469 | if (CHIP_IS_E3(bp)) |
2470 | ppp_enable = 0; | |
2471 | else | |
bcab15c5 VZ |
2472 | ppp_enable = 1; |
2473 | xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | |
2474 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
127302bb YR |
2475 | xcm_out_en = 0; |
2476 | hwpfc_enable = 1; | |
bcab15c5 VZ |
2477 | } else { |
2478 | if (nig_params) { | |
2479 | llfc_out_en = nig_params->llfc_out_en; | |
2480 | llfc_enable = nig_params->llfc_enable; | |
2481 | pause_enable = nig_params->pause_enable; | |
8f73f0b9 | 2482 | } else /* Default non PFC mode - PAUSE */ |
bcab15c5 VZ |
2483 | pause_enable = 1; |
2484 | ||
2485 | xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | |
2486 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
127302bb | 2487 | xcm_out_en = 1; |
bcab15c5 VZ |
2488 | } |
2489 | ||
9380bb9e YR |
2490 | if (CHIP_IS_E3(bp)) |
2491 | REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : | |
2492 | NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); | |
bcab15c5 VZ |
2493 | REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : |
2494 | NIG_REG_LLFC_OUT_EN_0, llfc_out_en); | |
2495 | REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : | |
2496 | NIG_REG_LLFC_ENABLE_0, llfc_enable); | |
2497 | REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : | |
2498 | NIG_REG_PAUSE_ENABLE_0, pause_enable); | |
2499 | ||
2500 | REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : | |
2501 | NIG_REG_PPP_ENABLE_0, ppp_enable); | |
2502 | ||
2503 | REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : | |
2504 | NIG_REG_LLH0_XCM_MASK, xcm_mask); | |
2505 | ||
127302bb YR |
2506 | REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : |
2507 | NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); | |
bcab15c5 VZ |
2508 | |
2509 | /* output enable for RX_XCM # IF */ | |
127302bb YR |
2510 | REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : |
2511 | NIG_REG_XCM0_OUT_EN, xcm_out_en); | |
bcab15c5 VZ |
2512 | |
2513 | /* HW PFC TX enable */ | |
127302bb YR |
2514 | REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : |
2515 | NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); | |
bcab15c5 | 2516 | |
bcab15c5 | 2517 | if (nig_params) { |
619c5cb6 | 2518 | u8 i = 0; |
bcab15c5 VZ |
2519 | pkt_priority_to_cos = nig_params->pkt_priority_to_cos; |
2520 | ||
619c5cb6 VZ |
2521 | for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) |
2522 | bnx2x_pfc_nig_rx_priority_mask(bp, i, | |
2523 | nig_params->rx_cos_priority_mask[i], port); | |
bcab15c5 VZ |
2524 | |
2525 | REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : | |
2526 | NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, | |
2527 | nig_params->llfc_high_priority_classes); | |
2528 | ||
2529 | REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : | |
2530 | NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, | |
2531 | nig_params->llfc_low_priority_classes); | |
2532 | } | |
2533 | REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : | |
2534 | NIG_REG_P0_PKT_PRIORITY_TO_COS, | |
2535 | pkt_priority_to_cos); | |
2536 | } | |
2537 | ||
9380bb9e | 2538 | int bnx2x_update_pfc(struct link_params *params, |
bcab15c5 VZ |
2539 | struct link_vars *vars, |
2540 | struct bnx2x_nig_brb_pfc_port_params *pfc_params) | |
2541 | { | |
8f73f0b9 | 2542 | /* The PFC and pause are orthogonal to one another, meaning when |
bcab15c5 VZ |
2543 | * PFC is enabled, the pause are disabled, and when PFC is |
2544 | * disabled, pause are set according to the pause result. | |
2545 | */ | |
2546 | u32 val; | |
2547 | struct bnx2x *bp = params->bp; | |
9380bb9e YR |
2548 | int bnx2x_status = 0; |
2549 | u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); | |
b8d6d082 YR |
2550 | |
2551 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
2552 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
2553 | else | |
2554 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; | |
2555 | ||
2556 | bnx2x_update_mng(params, vars->link_status); | |
2557 | ||
bcab15c5 VZ |
2558 | /* update NIG params */ |
2559 | bnx2x_update_pfc_nig(params, vars, pfc_params); | |
2560 | ||
2561 | /* update BRB params */ | |
9380bb9e | 2562 | bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params); |
de0396f4 | 2563 | if (bnx2x_status) |
9380bb9e | 2564 | return bnx2x_status; |
bcab15c5 VZ |
2565 | |
2566 | if (!vars->link_up) | |
9380bb9e | 2567 | return bnx2x_status; |
bcab15c5 VZ |
2568 | |
2569 | DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); | |
9380bb9e YR |
2570 | if (CHIP_IS_E3(bp)) |
2571 | bnx2x_update_pfc_xmac(params, vars, 0); | |
2572 | else { | |
2573 | val = REG_RD(bp, MISC_REG_RESET_REG_2); | |
2574 | if ((val & | |
3c9ada22 | 2575 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) |
9380bb9e YR |
2576 | == 0) { |
2577 | DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); | |
2578 | bnx2x_emac_enable(params, vars, 0); | |
2579 | return bnx2x_status; | |
2580 | } | |
9380bb9e YR |
2581 | if (CHIP_IS_E2(bp)) |
2582 | bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); | |
2583 | else | |
2584 | bnx2x_update_pfc_bmac1(params, vars); | |
2585 | ||
2586 | val = 0; | |
2587 | if ((params->feature_config_flags & | |
2588 | FEATURE_CONFIG_PFC_ENABLED) || | |
2589 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
2590 | val = 1; | |
2591 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); | |
2592 | } | |
2593 | return bnx2x_status; | |
bcab15c5 | 2594 | } |
f2e0899f | 2595 | |
9380bb9e | 2596 | |
fcf5b650 YR |
2597 | static int bnx2x_bmac1_enable(struct link_params *params, |
2598 | struct link_vars *vars, | |
2599 | u8 is_lb) | |
ea4e040a YR |
2600 | { |
2601 | struct bnx2x *bp = params->bp; | |
2602 | u8 port = params->port; | |
2603 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2604 | NIG_REG_INGRESS_BMAC0_MEM; | |
2605 | u32 wb_data[2]; | |
2606 | u32 val; | |
2607 | ||
f2e0899f | 2608 | DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); |
ea4e040a YR |
2609 | |
2610 | /* XGXS control */ | |
2611 | wb_data[0] = 0x3c; | |
2612 | wb_data[1] = 0; | |
cd88ccee YR |
2613 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, |
2614 | wb_data, 2); | |
ea4e040a YR |
2615 | |
2616 | /* tx MAC SA */ | |
2617 | wb_data[0] = ((params->mac_addr[2] << 24) | | |
2618 | (params->mac_addr[3] << 16) | | |
2619 | (params->mac_addr[4] << 8) | | |
2620 | params->mac_addr[5]); | |
2621 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
2622 | params->mac_addr[1]); | |
cd88ccee | 2623 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); |
ea4e040a | 2624 | |
ea4e040a YR |
2625 | /* mac control */ |
2626 | val = 0x3; | |
2627 | if (is_lb) { | |
2628 | val |= 0x4; | |
2629 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
2630 | } | |
2631 | wb_data[0] = val; | |
2632 | wb_data[1] = 0; | |
cd88ccee | 2633 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); |
ea4e040a | 2634 | |
ea4e040a YR |
2635 | /* set rx mtu */ |
2636 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
2637 | wb_data[1] = 0; | |
cd88ccee | 2638 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); |
ea4e040a | 2639 | |
bcab15c5 | 2640 | bnx2x_update_pfc_bmac1(params, vars); |
ea4e040a YR |
2641 | |
2642 | /* set tx mtu */ | |
2643 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
2644 | wb_data[1] = 0; | |
cd88ccee | 2645 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); |
ea4e040a YR |
2646 | |
2647 | /* set cnt max size */ | |
2648 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
2649 | wb_data[1] = 0; | |
cd88ccee | 2650 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
ea4e040a YR |
2651 | |
2652 | /* configure safc */ | |
2653 | wb_data[0] = 0x1000200; | |
2654 | wb_data[1] = 0; | |
2655 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, | |
2656 | wb_data, 2); | |
f2e0899f DK |
2657 | |
2658 | return 0; | |
2659 | } | |
2660 | ||
fcf5b650 YR |
2661 | static int bnx2x_bmac2_enable(struct link_params *params, |
2662 | struct link_vars *vars, | |
2663 | u8 is_lb) | |
f2e0899f DK |
2664 | { |
2665 | struct bnx2x *bp = params->bp; | |
2666 | u8 port = params->port; | |
2667 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2668 | NIG_REG_INGRESS_BMAC0_MEM; | |
2669 | u32 wb_data[2]; | |
2670 | ||
2671 | DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); | |
2672 | ||
2673 | wb_data[0] = 0; | |
2674 | wb_data[1] = 0; | |
cd88ccee | 2675 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
f2e0899f DK |
2676 | udelay(30); |
2677 | ||
2678 | /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ | |
2679 | wb_data[0] = 0x3c; | |
2680 | wb_data[1] = 0; | |
cd88ccee YR |
2681 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, |
2682 | wb_data, 2); | |
f2e0899f DK |
2683 | |
2684 | udelay(30); | |
2685 | ||
2686 | /* tx MAC SA */ | |
2687 | wb_data[0] = ((params->mac_addr[2] << 24) | | |
2688 | (params->mac_addr[3] << 16) | | |
2689 | (params->mac_addr[4] << 8) | | |
2690 | params->mac_addr[5]); | |
2691 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
2692 | params->mac_addr[1]); | |
2693 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, | |
cd88ccee | 2694 | wb_data, 2); |
f2e0899f DK |
2695 | |
2696 | udelay(30); | |
2697 | ||
2698 | /* Configure SAFC */ | |
2699 | wb_data[0] = 0x1000200; | |
2700 | wb_data[1] = 0; | |
2701 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, | |
cd88ccee | 2702 | wb_data, 2); |
f2e0899f DK |
2703 | udelay(30); |
2704 | ||
2705 | /* set rx mtu */ | |
2706 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
2707 | wb_data[1] = 0; | |
cd88ccee | 2708 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); |
f2e0899f DK |
2709 | udelay(30); |
2710 | ||
2711 | /* set tx mtu */ | |
2712 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
2713 | wb_data[1] = 0; | |
cd88ccee | 2714 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); |
f2e0899f DK |
2715 | udelay(30); |
2716 | /* set cnt max size */ | |
2717 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; | |
2718 | wb_data[1] = 0; | |
cd88ccee | 2719 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
f2e0899f | 2720 | udelay(30); |
bcab15c5 | 2721 | bnx2x_update_pfc_bmac2(params, vars, is_lb); |
f2e0899f DK |
2722 | |
2723 | return 0; | |
2724 | } | |
2725 | ||
fcf5b650 YR |
2726 | static int bnx2x_bmac_enable(struct link_params *params, |
2727 | struct link_vars *vars, | |
2728 | u8 is_lb) | |
f2e0899f | 2729 | { |
fcf5b650 YR |
2730 | int rc = 0; |
2731 | u8 port = params->port; | |
f2e0899f DK |
2732 | struct bnx2x *bp = params->bp; |
2733 | u32 val; | |
2734 | /* reset and unreset the BigMac */ | |
2735 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
cd88ccee | 2736 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
1d9c05d4 | 2737 | msleep(1); |
f2e0899f DK |
2738 | |
2739 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
cd88ccee | 2740 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
f2e0899f DK |
2741 | |
2742 | /* enable access for bmac registers */ | |
2743 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); | |
2744 | ||
2745 | /* Enable BMAC according to BMAC type*/ | |
2746 | if (CHIP_IS_E2(bp)) | |
2747 | rc = bnx2x_bmac2_enable(params, vars, is_lb); | |
2748 | else | |
2749 | rc = bnx2x_bmac1_enable(params, vars, is_lb); | |
ea4e040a YR |
2750 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); |
2751 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); | |
2752 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); | |
2753 | val = 0; | |
bcab15c5 VZ |
2754 | if ((params->feature_config_flags & |
2755 | FEATURE_CONFIG_PFC_ENABLED) || | |
2756 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
ea4e040a YR |
2757 | val = 1; |
2758 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); | |
2759 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); | |
2760 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); | |
2761 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
2762 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); | |
2763 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); | |
2764 | ||
2765 | vars->mac_type = MAC_TYPE_BMAC; | |
f2e0899f | 2766 | return rc; |
ea4e040a YR |
2767 | } |
2768 | ||
ea4e040a YR |
2769 | static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port) |
2770 | { | |
2771 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
cd88ccee | 2772 | NIG_REG_INGRESS_BMAC0_MEM; |
ea4e040a | 2773 | u32 wb_data[2]; |
3196a88a | 2774 | u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); |
ea4e040a YR |
2775 | |
2776 | /* Only if the bmac is out of reset */ | |
2777 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
2778 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && | |
2779 | nig_bmac_enable) { | |
2780 | ||
f2e0899f DK |
2781 | if (CHIP_IS_E2(bp)) { |
2782 | /* Clear Rx Enable bit in BMAC_CONTROL register */ | |
2783 | REG_RD_DMAE(bp, bmac_addr + | |
cd88ccee YR |
2784 | BIGMAC2_REGISTER_BMAC_CONTROL, |
2785 | wb_data, 2); | |
f2e0899f DK |
2786 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
2787 | REG_WR_DMAE(bp, bmac_addr + | |
cd88ccee YR |
2788 | BIGMAC2_REGISTER_BMAC_CONTROL, |
2789 | wb_data, 2); | |
f2e0899f DK |
2790 | } else { |
2791 | /* Clear Rx Enable bit in BMAC_CONTROL register */ | |
2792 | REG_RD_DMAE(bp, bmac_addr + | |
2793 | BIGMAC_REGISTER_BMAC_CONTROL, | |
2794 | wb_data, 2); | |
2795 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; | |
2796 | REG_WR_DMAE(bp, bmac_addr + | |
2797 | BIGMAC_REGISTER_BMAC_CONTROL, | |
2798 | wb_data, 2); | |
2799 | } | |
ea4e040a YR |
2800 | msleep(1); |
2801 | } | |
2802 | } | |
2803 | ||
fcf5b650 YR |
2804 | static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, |
2805 | u32 line_speed) | |
ea4e040a YR |
2806 | { |
2807 | struct bnx2x *bp = params->bp; | |
2808 | u8 port = params->port; | |
2809 | u32 init_crd, crd; | |
2810 | u32 count = 1000; | |
ea4e040a YR |
2811 | |
2812 | /* disable port */ | |
2813 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); | |
2814 | ||
2815 | /* wait for init credit */ | |
2816 | init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); | |
2817 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
2818 | DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); | |
2819 | ||
2820 | while ((init_crd != crd) && count) { | |
2821 | msleep(5); | |
2822 | ||
2823 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
2824 | count--; | |
2825 | } | |
2826 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
2827 | if (init_crd != crd) { | |
2828 | DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", | |
2829 | init_crd, crd); | |
2830 | return -EINVAL; | |
2831 | } | |
2832 | ||
c0700f90 | 2833 | if (flow_ctrl & BNX2X_FLOW_CTRL_RX || |
8c99e7b0 YR |
2834 | line_speed == SPEED_10 || |
2835 | line_speed == SPEED_100 || | |
2836 | line_speed == SPEED_1000 || | |
2837 | line_speed == SPEED_2500) { | |
2838 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); | |
ea4e040a YR |
2839 | /* update threshold */ |
2840 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); | |
2841 | /* update init credit */ | |
cd88ccee | 2842 | init_crd = 778; /* (800-18-4) */ |
ea4e040a YR |
2843 | |
2844 | } else { | |
2845 | u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + | |
2846 | ETH_OVREHEAD)/16; | |
8c99e7b0 | 2847 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); |
ea4e040a YR |
2848 | /* update threshold */ |
2849 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); | |
2850 | /* update init credit */ | |
2851 | switch (line_speed) { | |
ea4e040a YR |
2852 | case SPEED_10000: |
2853 | init_crd = thresh + 553 - 22; | |
2854 | break; | |
ea4e040a YR |
2855 | default: |
2856 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", | |
2857 | line_speed); | |
2858 | return -EINVAL; | |
ea4e040a YR |
2859 | } |
2860 | } | |
2861 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); | |
2862 | DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", | |
2863 | line_speed, init_crd); | |
2864 | ||
2865 | /* probe the credit changes */ | |
2866 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); | |
2867 | msleep(5); | |
2868 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); | |
2869 | ||
2870 | /* enable port */ | |
2871 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); | |
2872 | return 0; | |
2873 | } | |
2874 | ||
e8920674 DK |
2875 | /** |
2876 | * bnx2x_get_emac_base - retrive emac base address | |
2cf7acf9 | 2877 | * |
e8920674 DK |
2878 | * @bp: driver handle |
2879 | * @mdc_mdio_access: access type | |
2880 | * @port: port id | |
2cf7acf9 YR |
2881 | * |
2882 | * This function selects the MDC/MDIO access (through emac0 or | |
2883 | * emac1) depend on the mdc_mdio_access, port, port swapped. Each | |
2884 | * phy has a default access mode, which could also be overridden | |
2885 | * by nvram configuration. This parameter, whether this is the | |
2886 | * default phy configuration, or the nvram overrun | |
2887 | * configuration, is passed here as mdc_mdio_access and selects | |
2888 | * the emac_base for the CL45 read/writes operations | |
2889 | */ | |
c18aa15d YR |
2890 | static u32 bnx2x_get_emac_base(struct bnx2x *bp, |
2891 | u32 mdc_mdio_access, u8 port) | |
ea4e040a | 2892 | { |
c18aa15d YR |
2893 | u32 emac_base = 0; |
2894 | switch (mdc_mdio_access) { | |
2895 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: | |
2896 | break; | |
2897 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: | |
2898 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) | |
2899 | emac_base = GRCBASE_EMAC1; | |
2900 | else | |
2901 | emac_base = GRCBASE_EMAC0; | |
2902 | break; | |
2903 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: | |
589abe3a EG |
2904 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) |
2905 | emac_base = GRCBASE_EMAC0; | |
2906 | else | |
2907 | emac_base = GRCBASE_EMAC1; | |
ea4e040a | 2908 | break; |
c18aa15d YR |
2909 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: |
2910 | emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
2911 | break; | |
2912 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: | |
6378c025 | 2913 | emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; |
ea4e040a YR |
2914 | break; |
2915 | default: | |
ea4e040a YR |
2916 | break; |
2917 | } | |
2918 | return emac_base; | |
2919 | ||
2920 | } | |
2921 | ||
6583e33b YR |
2922 | /******************************************************************/ |
2923 | /* CL22 access functions */ | |
2924 | /******************************************************************/ | |
2925 | static int bnx2x_cl22_write(struct bnx2x *bp, | |
2926 | struct bnx2x_phy *phy, | |
2927 | u16 reg, u16 val) | |
2928 | { | |
2929 | u32 tmp, mode; | |
2930 | u8 i; | |
2931 | int rc = 0; | |
2932 | /* Switch to CL22 */ | |
2933 | mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
2934 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, | |
2935 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); | |
2936 | ||
2937 | /* address */ | |
2938 | tmp = ((phy->addr << 21) | (reg << 16) | val | | |
2939 | EMAC_MDIO_COMM_COMMAND_WRITE_22 | | |
2940 | EMAC_MDIO_COMM_START_BUSY); | |
2941 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); | |
2942 | ||
2943 | for (i = 0; i < 50; i++) { | |
2944 | udelay(10); | |
2945 | ||
2946 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
2947 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
2948 | udelay(5); | |
2949 | break; | |
2950 | } | |
2951 | } | |
2952 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | |
2953 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
2954 | rc = -EFAULT; | |
2955 | } | |
2956 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); | |
2957 | return rc; | |
2958 | } | |
2959 | ||
2960 | static int bnx2x_cl22_read(struct bnx2x *bp, | |
2961 | struct bnx2x_phy *phy, | |
2962 | u16 reg, u16 *ret_val) | |
2963 | { | |
2964 | u32 val, mode; | |
2965 | u16 i; | |
2966 | int rc = 0; | |
2967 | ||
2968 | /* Switch to CL22 */ | |
2969 | mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
2970 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, | |
2971 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); | |
2972 | ||
2973 | /* address */ | |
2974 | val = ((phy->addr << 21) | (reg << 16) | | |
2975 | EMAC_MDIO_COMM_COMMAND_READ_22 | | |
2976 | EMAC_MDIO_COMM_START_BUSY); | |
2977 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); | |
2978 | ||
2979 | for (i = 0; i < 50; i++) { | |
2980 | udelay(10); | |
2981 | ||
2982 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
2983 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
2984 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); | |
2985 | udelay(5); | |
2986 | break; | |
2987 | } | |
2988 | } | |
2989 | if (val & EMAC_MDIO_COMM_START_BUSY) { | |
2990 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
2991 | ||
2992 | *ret_val = 0; | |
2993 | rc = -EFAULT; | |
2994 | } | |
2995 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); | |
2996 | return rc; | |
2997 | } | |
2998 | ||
2cf7acf9 YR |
2999 | /******************************************************************/ |
3000 | /* CL45 access functions */ | |
3001 | /******************************************************************/ | |
a198c142 YR |
3002 | static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, |
3003 | u8 devad, u16 reg, u16 *ret_val) | |
ea4e040a | 3004 | { |
a198c142 YR |
3005 | u32 val; |
3006 | u16 i; | |
fcf5b650 | 3007 | int rc = 0; |
157fa283 YR |
3008 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
3009 | bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
3010 | EMAC_MDIO_STATUS_10MB); | |
ea4e040a | 3011 | /* address */ |
a198c142 | 3012 | val = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
3013 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
3014 | EMAC_MDIO_COMM_START_BUSY); | |
a198c142 | 3015 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
3016 | |
3017 | for (i = 0; i < 50; i++) { | |
3018 | udelay(10); | |
3019 | ||
a198c142 YR |
3020 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
3021 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
ea4e040a YR |
3022 | udelay(5); |
3023 | break; | |
3024 | } | |
3025 | } | |
a198c142 YR |
3026 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
3027 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
6d870c39 | 3028 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
a198c142 | 3029 | *ret_val = 0; |
ea4e040a YR |
3030 | rc = -EFAULT; |
3031 | } else { | |
3032 | /* data */ | |
a198c142 YR |
3033 | val = ((phy->addr << 21) | (devad << 16) | |
3034 | EMAC_MDIO_COMM_COMMAND_READ_45 | | |
ea4e040a | 3035 | EMAC_MDIO_COMM_START_BUSY); |
a198c142 | 3036 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
3037 | |
3038 | for (i = 0; i < 50; i++) { | |
3039 | udelay(10); | |
3040 | ||
a198c142 | 3041 | val = REG_RD(bp, phy->mdio_ctrl + |
cd88ccee | 3042 | EMAC_REG_EMAC_MDIO_COMM); |
a198c142 YR |
3043 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
3044 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); | |
ea4e040a YR |
3045 | break; |
3046 | } | |
3047 | } | |
a198c142 YR |
3048 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
3049 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
6d870c39 | 3050 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
a198c142 | 3051 | *ret_val = 0; |
ea4e040a YR |
3052 | rc = -EFAULT; |
3053 | } | |
3054 | } | |
3c9ada22 YR |
3055 | /* Work around for E3 A0 */ |
3056 | if (phy->flags & FLAGS_MDC_MDIO_WA) { | |
3057 | phy->flags ^= FLAGS_DUMMY_READ; | |
3058 | if (phy->flags & FLAGS_DUMMY_READ) { | |
3059 | u16 temp_val; | |
3060 | bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); | |
3061 | } | |
3062 | } | |
ea4e040a | 3063 | |
157fa283 YR |
3064 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
3065 | bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
3066 | EMAC_MDIO_STATUS_10MB); | |
ea4e040a YR |
3067 | return rc; |
3068 | } | |
3069 | ||
a198c142 YR |
3070 | static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
3071 | u8 devad, u16 reg, u16 val) | |
ea4e040a | 3072 | { |
a198c142 YR |
3073 | u32 tmp; |
3074 | u8 i; | |
fcf5b650 | 3075 | int rc = 0; |
157fa283 YR |
3076 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
3077 | bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
3078 | EMAC_MDIO_STATUS_10MB); | |
ea4e040a YR |
3079 | |
3080 | /* address */ | |
a198c142 | 3081 | tmp = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
3082 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
3083 | EMAC_MDIO_COMM_START_BUSY); | |
a198c142 | 3084 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
3085 | |
3086 | for (i = 0; i < 50; i++) { | |
3087 | udelay(10); | |
3088 | ||
a198c142 YR |
3089 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
3090 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
ea4e040a YR |
3091 | udelay(5); |
3092 | break; | |
3093 | } | |
3094 | } | |
a198c142 YR |
3095 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
3096 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
6d870c39 | 3097 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
ea4e040a | 3098 | rc = -EFAULT; |
ea4e040a YR |
3099 | } else { |
3100 | /* data */ | |
a198c142 YR |
3101 | tmp = ((phy->addr << 21) | (devad << 16) | val | |
3102 | EMAC_MDIO_COMM_COMMAND_WRITE_45 | | |
ea4e040a | 3103 | EMAC_MDIO_COMM_START_BUSY); |
a198c142 | 3104 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
3105 | |
3106 | for (i = 0; i < 50; i++) { | |
3107 | udelay(10); | |
3108 | ||
a198c142 | 3109 | tmp = REG_RD(bp, phy->mdio_ctrl + |
cd88ccee | 3110 | EMAC_REG_EMAC_MDIO_COMM); |
a198c142 YR |
3111 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
3112 | udelay(5); | |
ea4e040a YR |
3113 | break; |
3114 | } | |
3115 | } | |
a198c142 YR |
3116 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
3117 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
6d870c39 | 3118 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
ea4e040a YR |
3119 | rc = -EFAULT; |
3120 | } | |
3121 | } | |
3c9ada22 YR |
3122 | /* Work around for E3 A0 */ |
3123 | if (phy->flags & FLAGS_MDC_MDIO_WA) { | |
3124 | phy->flags ^= FLAGS_DUMMY_READ; | |
3125 | if (phy->flags & FLAGS_DUMMY_READ) { | |
3126 | u16 temp_val; | |
3127 | bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); | |
3128 | } | |
3129 | } | |
157fa283 YR |
3130 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
3131 | bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
3132 | EMAC_MDIO_STATUS_10MB); | |
3c9ada22 YR |
3133 | return rc; |
3134 | } | |
3c9ada22 YR |
3135 | /******************************************************************/ |
3136 | /* BSC access functions from E3 */ | |
3137 | /******************************************************************/ | |
3138 | static void bnx2x_bsc_module_sel(struct link_params *params) | |
3139 | { | |
3140 | int idx; | |
3141 | u32 board_cfg, sfp_ctrl; | |
3142 | u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; | |
3143 | struct bnx2x *bp = params->bp; | |
3144 | u8 port = params->port; | |
3145 | /* Read I2C output PINs */ | |
3146 | board_cfg = REG_RD(bp, params->shmem_base + | |
3147 | offsetof(struct shmem_region, | |
3148 | dev_info.shared_hw_config.board)); | |
3149 | i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; | |
3150 | i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> | |
3151 | SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; | |
3152 | ||
3153 | /* Read I2C output value */ | |
3154 | sfp_ctrl = REG_RD(bp, params->shmem_base + | |
3155 | offsetof(struct shmem_region, | |
3156 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)); | |
3157 | i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; | |
3158 | i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; | |
3159 | DP(NETIF_MSG_LINK, "Setting BSC switch\n"); | |
3160 | for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) | |
3161 | bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); | |
3162 | } | |
3163 | ||
3164 | static int bnx2x_bsc_read(struct link_params *params, | |
3165 | struct bnx2x_phy *phy, | |
3166 | u8 sl_devid, | |
3167 | u16 sl_addr, | |
3168 | u8 lc_addr, | |
3169 | u8 xfer_cnt, | |
3170 | u32 *data_array) | |
3171 | { | |
3172 | u32 val, i; | |
3173 | int rc = 0; | |
3174 | struct bnx2x *bp = params->bp; | |
3175 | ||
3176 | if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) { | |
3177 | DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid); | |
3178 | return -EINVAL; | |
3179 | } | |
3180 | ||
3181 | if (xfer_cnt > 16) { | |
3182 | DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", | |
3183 | xfer_cnt); | |
3184 | return -EINVAL; | |
3185 | } | |
3186 | bnx2x_bsc_module_sel(params); | |
3187 | ||
3188 | xfer_cnt = 16 - lc_addr; | |
3189 | ||
3190 | /* enable the engine */ | |
3191 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3192 | val |= MCPR_IMC_COMMAND_ENABLE; | |
3193 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3194 | ||
3195 | /* program slave device ID */ | |
3196 | val = (sl_devid << 16) | sl_addr; | |
3197 | REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); | |
3198 | ||
3199 | /* start xfer with 0 byte to update the address pointer ???*/ | |
3200 | val = (MCPR_IMC_COMMAND_ENABLE) | | |
3201 | (MCPR_IMC_COMMAND_WRITE_OP << | |
3202 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | | |
3203 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); | |
3204 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3205 | ||
3206 | /* poll for completion */ | |
3207 | i = 0; | |
3208 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3209 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { | |
3210 | udelay(10); | |
3211 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3212 | if (i++ > 1000) { | |
3213 | DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", | |
3214 | i); | |
3215 | rc = -EFAULT; | |
3216 | break; | |
3217 | } | |
3218 | } | |
3219 | if (rc == -EFAULT) | |
3220 | return rc; | |
3221 | ||
3222 | /* start xfer with read op */ | |
3223 | val = (MCPR_IMC_COMMAND_ENABLE) | | |
3224 | (MCPR_IMC_COMMAND_READ_OP << | |
3225 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | | |
3226 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | | |
3227 | (xfer_cnt); | |
3228 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3229 | ||
3230 | /* poll for completion */ | |
3231 | i = 0; | |
3232 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3233 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { | |
3234 | udelay(10); | |
3235 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3236 | if (i++ > 1000) { | |
3237 | DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); | |
3238 | rc = -EFAULT; | |
3239 | break; | |
3240 | } | |
3241 | } | |
3242 | if (rc == -EFAULT) | |
3243 | return rc; | |
3244 | ||
3245 | for (i = (lc_addr >> 2); i < 4; i++) { | |
3246 | data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); | |
3247 | #ifdef __BIG_ENDIAN | |
3248 | data_array[i] = ((data_array[i] & 0x000000ff) << 24) | | |
3249 | ((data_array[i] & 0x0000ff00) << 8) | | |
3250 | ((data_array[i] & 0x00ff0000) >> 8) | | |
3251 | ((data_array[i] & 0xff000000) >> 24); | |
3252 | #endif | |
3253 | } | |
ea4e040a YR |
3254 | return rc; |
3255 | } | |
3256 | ||
3c9ada22 YR |
3257 | static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
3258 | u8 devad, u16 reg, u16 or_val) | |
3259 | { | |
3260 | u16 val; | |
3261 | bnx2x_cl45_read(bp, phy, devad, reg, &val); | |
3262 | bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); | |
3263 | } | |
3264 | ||
fcf5b650 YR |
3265 | int bnx2x_phy_read(struct link_params *params, u8 phy_addr, |
3266 | u8 devad, u16 reg, u16 *ret_val) | |
e10bc84d YR |
3267 | { |
3268 | u8 phy_index; | |
8f73f0b9 | 3269 | /* Probe for the phy according to the given phy_addr, and execute |
e10bc84d YR |
3270 | * the read request on it |
3271 | */ | |
3272 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
3273 | if (params->phy[phy_index].addr == phy_addr) { | |
3274 | return bnx2x_cl45_read(params->bp, | |
3275 | ¶ms->phy[phy_index], devad, | |
3276 | reg, ret_val); | |
3277 | } | |
3278 | } | |
3279 | return -EINVAL; | |
3280 | } | |
3281 | ||
fcf5b650 YR |
3282 | int bnx2x_phy_write(struct link_params *params, u8 phy_addr, |
3283 | u8 devad, u16 reg, u16 val) | |
e10bc84d YR |
3284 | { |
3285 | u8 phy_index; | |
8f73f0b9 | 3286 | /* Probe for the phy according to the given phy_addr, and execute |
e10bc84d YR |
3287 | * the write request on it |
3288 | */ | |
3289 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
3290 | if (params->phy[phy_index].addr == phy_addr) { | |
3291 | return bnx2x_cl45_write(params->bp, | |
3292 | ¶ms->phy[phy_index], devad, | |
3293 | reg, val); | |
3294 | } | |
3295 | } | |
3296 | return -EINVAL; | |
3297 | } | |
3c9ada22 YR |
3298 | static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, |
3299 | struct link_params *params) | |
3300 | { | |
3301 | u8 lane = 0; | |
3302 | struct bnx2x *bp = params->bp; | |
3303 | u32 path_swap, path_swap_ovr; | |
3304 | u8 path, port; | |
3305 | ||
3306 | path = BP_PATH(bp); | |
3307 | port = params->port; | |
3308 | ||
3309 | if (bnx2x_is_4_port_mode(bp)) { | |
3310 | u32 port_swap, port_swap_ovr; | |
3311 | ||
8f73f0b9 | 3312 | /* Figure out path swap value */ |
3c9ada22 YR |
3313 | path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); |
3314 | if (path_swap_ovr & 0x1) | |
3315 | path_swap = (path_swap_ovr & 0x2); | |
3316 | else | |
3317 | path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); | |
3318 | ||
3319 | if (path_swap) | |
3320 | path = path ^ 1; | |
3321 | ||
8f73f0b9 | 3322 | /* Figure out port swap value */ |
3c9ada22 YR |
3323 | port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); |
3324 | if (port_swap_ovr & 0x1) | |
3325 | port_swap = (port_swap_ovr & 0x2); | |
3326 | else | |
3327 | port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); | |
3328 | ||
3329 | if (port_swap) | |
3330 | port = port ^ 1; | |
3331 | ||
3332 | lane = (port<<1) + path; | |
3333 | } else { /* two port mode - no port swap */ | |
3334 | ||
8f73f0b9 | 3335 | /* Figure out path swap value */ |
3c9ada22 YR |
3336 | path_swap_ovr = |
3337 | REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); | |
3338 | if (path_swap_ovr & 0x1) { | |
3339 | path_swap = (path_swap_ovr & 0x2); | |
3340 | } else { | |
3341 | path_swap = | |
3342 | REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); | |
3343 | } | |
3344 | if (path_swap) | |
3345 | path = path ^ 1; | |
3346 | ||
3347 | lane = path << 1 ; | |
3348 | } | |
3349 | return lane; | |
3350 | } | |
e10bc84d | 3351 | |
ec146a6f YR |
3352 | static void bnx2x_set_aer_mmd(struct link_params *params, |
3353 | struct bnx2x_phy *phy) | |
ea4e040a | 3354 | { |
ea4e040a | 3355 | u32 ser_lane; |
f2e0899f DK |
3356 | u16 offset, aer_val; |
3357 | struct bnx2x *bp = params->bp; | |
ea4e040a YR |
3358 | ser_lane = ((params->lane_config & |
3359 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
3360 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
3361 | ||
ec146a6f YR |
3362 | offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? |
3363 | (phy->addr + ser_lane) : 0; | |
3364 | ||
3c9ada22 YR |
3365 | if (USES_WARPCORE(bp)) { |
3366 | aer_val = bnx2x_get_warpcore_lane(phy, params); | |
8f73f0b9 | 3367 | /* In Dual-lane mode, two lanes are joined together, |
3c9ada22 YR |
3368 | * so in order to configure them, the AER broadcast method is |
3369 | * used here. | |
3370 | * 0x200 is the broadcast address for lanes 0,1 | |
3371 | * 0x201 is the broadcast address for lanes 2,3 | |
3372 | */ | |
3373 | if (phy->flags & FLAGS_WC_DUAL_MODE) | |
3374 | aer_val = (aer_val >> 1) | 0x200; | |
3375 | } else if (CHIP_IS_E2(bp)) | |
82a0d475 | 3376 | aer_val = 0x3800 + offset - 1; |
f2e0899f DK |
3377 | else |
3378 | aer_val = 0x3800 + offset; | |
2f751a80 | 3379 | |
cd2be89b | 3380 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
cd88ccee | 3381 | MDIO_AER_BLOCK_AER_REG, aer_val); |
ec146a6f | 3382 | |
ea4e040a YR |
3383 | } |
3384 | ||
de6eae1f YR |
3385 | /******************************************************************/ |
3386 | /* Internal phy section */ | |
3387 | /******************************************************************/ | |
ea4e040a | 3388 | |
de6eae1f YR |
3389 | static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) |
3390 | { | |
3391 | u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
ea4e040a | 3392 | |
de6eae1f YR |
3393 | /* Set Clause 22 */ |
3394 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); | |
3395 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); | |
3396 | udelay(500); | |
3397 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); | |
3398 | udelay(500); | |
3399 | /* Set Clause 45 */ | |
3400 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); | |
ea4e040a YR |
3401 | } |
3402 | ||
de6eae1f | 3403 | static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) |
ea4e040a | 3404 | { |
de6eae1f | 3405 | u32 val; |
ea4e040a | 3406 | |
de6eae1f | 3407 | DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); |
ea4e040a | 3408 | |
de6eae1f | 3409 | val = SERDES_RESET_BITS << (port*16); |
c1b73990 | 3410 | |
de6eae1f YR |
3411 | /* reset and unreset the SerDes/XGXS */ |
3412 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); | |
3413 | udelay(500); | |
3414 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
ea4e040a | 3415 | |
de6eae1f | 3416 | bnx2x_set_serdes_access(bp, port); |
ea4e040a | 3417 | |
cd88ccee YR |
3418 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, |
3419 | DEFAULT_PHY_DEV_ADDR); | |
de6eae1f YR |
3420 | } |
3421 | ||
3422 | static void bnx2x_xgxs_deassert(struct link_params *params) | |
3423 | { | |
3424 | struct bnx2x *bp = params->bp; | |
3425 | u8 port; | |
3426 | u32 val; | |
3427 | DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); | |
3428 | port = params->port; | |
3429 | ||
3430 | val = XGXS_RESET_BITS << (port*16); | |
3431 | ||
3432 | /* reset and unreset the SerDes/XGXS */ | |
3433 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); | |
3434 | udelay(500); | |
3435 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
3436 | ||
cd88ccee | 3437 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0); |
de6eae1f | 3438 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
cd88ccee | 3439 | params->phy[INT_PHY].def_md_devad); |
de6eae1f YR |
3440 | } |
3441 | ||
9045f6b4 YR |
3442 | static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, |
3443 | struct link_params *params, u16 *ieee_fc) | |
3444 | { | |
3445 | struct bnx2x *bp = params->bp; | |
3446 | *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; | |
8f73f0b9 | 3447 | /* Resolve pause mode and advertisement Please refer to Table |
9045f6b4 YR |
3448 | * 28B-3 of the 802.3ab-1999 spec |
3449 | */ | |
3450 | ||
3451 | switch (phy->req_flow_ctrl) { | |
3452 | case BNX2X_FLOW_CTRL_AUTO: | |
3453 | if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) | |
3454 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
3455 | else | |
3456 | *ieee_fc |= | |
3457 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
3458 | break; | |
3459 | ||
3460 | case BNX2X_FLOW_CTRL_TX: | |
3461 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
3462 | break; | |
3463 | ||
3464 | case BNX2X_FLOW_CTRL_RX: | |
3465 | case BNX2X_FLOW_CTRL_BOTH: | |
3466 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
3467 | break; | |
3468 | ||
3469 | case BNX2X_FLOW_CTRL_NONE: | |
3470 | default: | |
3471 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; | |
3472 | break; | |
3473 | } | |
3474 | DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); | |
3475 | } | |
3476 | ||
3477 | static void set_phy_vars(struct link_params *params, | |
3478 | struct link_vars *vars) | |
3479 | { | |
3480 | struct bnx2x *bp = params->bp; | |
3481 | u8 actual_phy_idx, phy_index, link_cfg_idx; | |
3482 | u8 phy_config_swapped = params->multi_phy_config & | |
3483 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
3484 | for (phy_index = INT_PHY; phy_index < params->num_phys; | |
3485 | phy_index++) { | |
3486 | link_cfg_idx = LINK_CONFIG_IDX(phy_index); | |
3487 | actual_phy_idx = phy_index; | |
3488 | if (phy_config_swapped) { | |
3489 | if (phy_index == EXT_PHY1) | |
3490 | actual_phy_idx = EXT_PHY2; | |
3491 | else if (phy_index == EXT_PHY2) | |
3492 | actual_phy_idx = EXT_PHY1; | |
3493 | } | |
3494 | params->phy[actual_phy_idx].req_flow_ctrl = | |
3495 | params->req_flow_ctrl[link_cfg_idx]; | |
3496 | ||
3497 | params->phy[actual_phy_idx].req_line_speed = | |
3498 | params->req_line_speed[link_cfg_idx]; | |
3499 | ||
3500 | params->phy[actual_phy_idx].speed_cap_mask = | |
3501 | params->speed_cap_mask[link_cfg_idx]; | |
a22f0788 | 3502 | |
9045f6b4 YR |
3503 | params->phy[actual_phy_idx].req_duplex = |
3504 | params->req_duplex[link_cfg_idx]; | |
3505 | ||
3506 | if (params->req_line_speed[link_cfg_idx] == | |
3507 | SPEED_AUTO_NEG) | |
3508 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
3509 | ||
3510 | DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," | |
3511 | " speed_cap_mask %x\n", | |
3512 | params->phy[actual_phy_idx].req_flow_ctrl, | |
3513 | params->phy[actual_phy_idx].req_line_speed, | |
3514 | params->phy[actual_phy_idx].speed_cap_mask); | |
3515 | } | |
3516 | } | |
3517 | ||
3518 | static void bnx2x_ext_phy_set_pause(struct link_params *params, | |
3519 | struct bnx2x_phy *phy, | |
3520 | struct link_vars *vars) | |
3521 | { | |
3522 | u16 val; | |
3523 | struct bnx2x *bp = params->bp; | |
3524 | /* read modify write pause advertizing */ | |
3525 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); | |
3526 | ||
3527 | val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; | |
3528 | ||
3529 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
3530 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
3531 | if ((vars->ieee_fc & | |
3532 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
3533 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
3534 | val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
3535 | } | |
3536 | if ((vars->ieee_fc & | |
3537 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
3538 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
3539 | val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
3540 | } | |
3541 | DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); | |
3542 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); | |
3543 | } | |
3544 | ||
3545 | static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) | |
3546 | { /* LD LP */ | |
3547 | switch (pause_result) { /* ASYM P ASYM P */ | |
3548 | case 0xb: /* 1 0 1 1 */ | |
3549 | vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; | |
3550 | break; | |
3551 | ||
3552 | case 0xe: /* 1 1 1 0 */ | |
3553 | vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; | |
3554 | break; | |
3555 | ||
3556 | case 0x5: /* 0 1 0 1 */ | |
3557 | case 0x7: /* 0 1 1 1 */ | |
3558 | case 0xd: /* 1 1 0 1 */ | |
3559 | case 0xf: /* 1 1 1 1 */ | |
3560 | vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; | |
3561 | break; | |
3562 | ||
3563 | default: | |
3564 | break; | |
3565 | } | |
3566 | if (pause_result & (1<<0)) | |
3567 | vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; | |
3568 | if (pause_result & (1<<1)) | |
3569 | vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; | |
8f73f0b9 | 3570 | |
9045f6b4 YR |
3571 | } |
3572 | ||
9e7e8399 MY |
3573 | static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, |
3574 | struct link_params *params, | |
3575 | struct link_vars *vars) | |
9045f6b4 | 3576 | { |
9045f6b4 YR |
3577 | u16 ld_pause; /* local */ |
3578 | u16 lp_pause; /* link partner */ | |
3579 | u16 pause_result; | |
9e7e8399 MY |
3580 | struct bnx2x *bp = params->bp; |
3581 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { | |
3582 | bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); | |
3583 | bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); | |
ca05f29c YR |
3584 | } else if (CHIP_IS_E3(bp) && |
3585 | SINGLE_MEDIA_DIRECT(params)) { | |
3586 | u8 lane = bnx2x_get_warpcore_lane(phy, params); | |
3587 | u16 gp_status, gp_mask; | |
3588 | bnx2x_cl45_read(bp, phy, | |
3589 | MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, | |
3590 | &gp_status); | |
3591 | gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | | |
3592 | MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << | |
3593 | lane; | |
3594 | if ((gp_status & gp_mask) == gp_mask) { | |
3595 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3596 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3597 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3598 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3599 | } else { | |
3600 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3601 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
3602 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3603 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
3604 | ld_pause = ((ld_pause & | |
3605 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
3606 | << 3); | |
3607 | lp_pause = ((lp_pause & | |
3608 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
3609 | << 3); | |
3610 | } | |
9e7e8399 MY |
3611 | } else { |
3612 | bnx2x_cl45_read(bp, phy, | |
3613 | MDIO_AN_DEVAD, | |
3614 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3615 | bnx2x_cl45_read(bp, phy, | |
3616 | MDIO_AN_DEVAD, | |
3617 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3618 | } | |
3619 | pause_result = (ld_pause & | |
3620 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; | |
3621 | pause_result |= (lp_pause & | |
3622 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; | |
3623 | DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); | |
3624 | bnx2x_pause_resolve(vars, pause_result); | |
9045f6b4 | 3625 | |
9e7e8399 | 3626 | } |
8f73f0b9 | 3627 | |
9e7e8399 MY |
3628 | static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, |
3629 | struct link_params *params, | |
3630 | struct link_vars *vars) | |
3631 | { | |
3632 | u8 ret = 0; | |
9045f6b4 | 3633 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
9e7e8399 MY |
3634 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { |
3635 | /* Update the advertised flow-controled of LD/LP in AN */ | |
3636 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
3637 | bnx2x_ext_phy_update_adv_fc(phy, params, vars); | |
3638 | /* But set the flow-control result as the requested one */ | |
9045f6b4 | 3639 | vars->flow_ctrl = phy->req_flow_ctrl; |
9e7e8399 | 3640 | } else if (phy->req_line_speed != SPEED_AUTO_NEG) |
9045f6b4 YR |
3641 | vars->flow_ctrl = params->req_fc_auto_adv; |
3642 | else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
3643 | ret = 1; | |
9e7e8399 | 3644 | bnx2x_ext_phy_update_adv_fc(phy, params, vars); |
9045f6b4 YR |
3645 | } |
3646 | return ret; | |
3647 | } | |
3c9ada22 YR |
3648 | /******************************************************************/ |
3649 | /* Warpcore section */ | |
3650 | /******************************************************************/ | |
3651 | /* The init_internal_warpcore should mirror the xgxs, | |
3652 | * i.e. reset the lane (if needed), set aer for the | |
3653 | * init configuration, and set/clear SGMII flag. Internal | |
3654 | * phy init is done purely in phy_init stage. | |
3655 | */ | |
3656 | static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, | |
3657 | struct link_params *params, | |
3658 | struct link_vars *vars) { | |
a34bc969 | 3659 | u16 val16 = 0, lane, bam37 = 0; |
3c9ada22 YR |
3660 | struct bnx2x *bp = params->bp; |
3661 | DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); | |
6a51c0d1 YR |
3662 | /* Set to default registers that may be overriden by 10G force */ |
3663 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3664 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7); | |
3665 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3666 | MDIO_WC_REG_PAR_DET_10G_CTRL, 0); | |
3667 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3668 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0); | |
3669 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3670 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff); | |
3671 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3672 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555); | |
3673 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | |
3674 | MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0); | |
3675 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3676 | MDIO_WC_REG_RX66_CONTROL, 0x7415); | |
3677 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3678 | MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190); | |
a9077bfd YR |
3679 | /* Disable Autoneg: re-enable it after adv is done. */ |
3680 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3681 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0); | |
3682 | ||
3c9ada22 YR |
3683 | /* Check adding advertisement for 1G KX */ |
3684 | if (((vars->line_speed == SPEED_AUTO_NEG) && | |
3685 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
3686 | (vars->line_speed == SPEED_1000)) { | |
3687 | u16 sd_digital; | |
3688 | val16 |= (1<<5); | |
3689 | ||
3690 | /* Enable CL37 1G Parallel Detect */ | |
3691 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3692 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital); | |
3693 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3694 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
3695 | (sd_digital | 0x1)); | |
3696 | ||
3697 | DP(NETIF_MSG_LINK, "Advertize 1G\n"); | |
3698 | } | |
3699 | if (((vars->line_speed == SPEED_AUTO_NEG) && | |
3700 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
3701 | (vars->line_speed == SPEED_10000)) { | |
3702 | /* Check adding advertisement for 10G KR */ | |
3703 | val16 |= (1<<7); | |
3704 | /* Enable 10G Parallel Detect */ | |
3705 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3706 | MDIO_WC_REG_PAR_DET_10G_CTRL, 1); | |
3707 | ||
3708 | DP(NETIF_MSG_LINK, "Advertize 10G\n"); | |
3709 | } | |
3710 | ||
3711 | /* Set Transmit PMD settings */ | |
3712 | lane = bnx2x_get_warpcore_lane(phy, params); | |
3713 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3714 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | |
3715 | ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | |
3716 | (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | |
3717 | (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); | |
3718 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3719 | MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, | |
3720 | 0x03f0); | |
3721 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3722 | MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, | |
3723 | 0x03f0); | |
3c9ada22 YR |
3724 | |
3725 | /* Advertised speeds */ | |
3726 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3727 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16); | |
3728 | ||
6b1f3900 YR |
3729 | /* Advertised and set FEC (Forward Error Correction) */ |
3730 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3731 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, | |
3732 | (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | | |
3733 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); | |
3734 | ||
a34bc969 YR |
3735 | /* Enable CL37 BAM */ |
3736 | if (REG_RD(bp, params->shmem_base + | |
3737 | offsetof(struct shmem_region, dev_info. | |
3738 | port_hw_config[params->port].default_cfg)) & | |
3739 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
3740 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3741 | MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37); | |
3742 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3743 | MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1); | |
3744 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); | |
3745 | } | |
3746 | ||
3c9ada22 YR |
3747 | /* Advertise pause */ |
3748 | bnx2x_ext_phy_set_pause(params, phy, vars); | |
8f73f0b9 | 3749 | /* Set KR Autoneg Work-Around flag for Warpcore version older than D108 |
6ab48a5c YR |
3750 | */ |
3751 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3752 | MDIO_WC_REG_UC_INFO_B1_VERSION, &val16); | |
3753 | if (val16 < 0xd108) { | |
3754 | DP(NETIF_MSG_LINK, "Enable AN KR work-around\n"); | |
3755 | vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; | |
3756 | } | |
3c9ada22 YR |
3757 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
3758 | MDIO_WC_REG_DIGITAL5_MISC7, &val16); | |
3759 | ||
3760 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3761 | MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100); | |
a9077bfd YR |
3762 | |
3763 | /* Over 1G - AN local device user page 1 */ | |
3764 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3765 | MDIO_WC_REG_DIGITAL3_UP1, 0x1f); | |
3766 | ||
3767 | /* Enable Autoneg */ | |
3768 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
1b85ae52 | 3769 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); |
a9077bfd | 3770 | |
3c9ada22 YR |
3771 | } |
3772 | ||
3773 | static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, | |
3774 | struct link_params *params, | |
3775 | struct link_vars *vars) | |
3776 | { | |
3777 | struct bnx2x *bp = params->bp; | |
3778 | u16 val; | |
3779 | ||
3780 | /* Disable Autoneg */ | |
3781 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3782 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7); | |
3783 | ||
3784 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3785 | MDIO_WC_REG_PAR_DET_10G_CTRL, 0); | |
3786 | ||
3787 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3788 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00); | |
3789 | ||
3790 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3791 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0); | |
3792 | ||
3793 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3794 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); | |
3795 | ||
3796 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3797 | MDIO_WC_REG_DIGITAL3_UP1, 0x1); | |
3798 | ||
3799 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3800 | MDIO_WC_REG_DIGITAL5_MISC7, 0xa); | |
3801 | ||
3802 | /* Disable CL36 PCS Tx */ | |
3803 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3804 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0); | |
3805 | ||
3806 | /* Double Wide Single Data Rate @ pll rate */ | |
3807 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3808 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF); | |
3809 | ||
3810 | /* Leave cl72 training enable, needed for KR */ | |
3811 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | |
3812 | MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150, | |
3813 | 0x2); | |
3814 | ||
3815 | /* Leave CL72 enabled */ | |
3816 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3817 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, | |
3818 | &val); | |
3819 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3820 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, | |
3821 | val | 0x3800); | |
3822 | ||
3823 | /* Set speed via PMA/PMD register */ | |
3824 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | |
3825 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); | |
3826 | ||
3827 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | |
3828 | MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); | |
3829 | ||
8f73f0b9 | 3830 | /* Enable encoded forced speed */ |
3c9ada22 YR |
3831 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
3832 | MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); | |
3833 | ||
3834 | /* Turn TX scramble payload only the 64/66 scrambler */ | |
3835 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3836 | MDIO_WC_REG_TX66_CONTROL, 0x9); | |
3837 | ||
3838 | /* Turn RX scramble payload only the 64/66 scrambler */ | |
3839 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
3840 | MDIO_WC_REG_RX66_CONTROL, 0xF9); | |
3841 | ||
3842 | /* set and clear loopback to cause a reset to 64/66 decoder */ | |
3843 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3844 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); | |
3845 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3846 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); | |
3847 | ||
3848 | } | |
3849 | ||
3850 | static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, | |
3851 | struct link_params *params, | |
3852 | u8 is_xfi) | |
3853 | { | |
3854 | struct bnx2x *bp = params->bp; | |
3855 | u16 misc1_val, tap_val, tx_driver_val, lane, val; | |
3856 | /* Hold rxSeqStart */ | |
3857 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3858 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val); | |
3859 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3860 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000)); | |
3861 | ||
3862 | /* Hold tx_fifo_reset */ | |
3863 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3864 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val); | |
3865 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3866 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1)); | |
3867 | ||
3868 | /* Disable CL73 AN */ | |
3869 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); | |
3870 | ||
3871 | /* Disable 100FX Enable and Auto-Detect */ | |
3872 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3873 | MDIO_WC_REG_FX100_CTRL1, &val); | |
3874 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3875 | MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA)); | |
3876 | ||
3877 | /* Disable 100FX Idle detect */ | |
3878 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3879 | MDIO_WC_REG_FX100_CTRL3, &val); | |
3880 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3881 | MDIO_WC_REG_FX100_CTRL3, (val | 0x0080)); | |
3882 | ||
3883 | /* Set Block address to Remote PHY & Clear forced_speed[5] */ | |
3884 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3885 | MDIO_WC_REG_DIGITAL4_MISC3, &val); | |
3886 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3887 | MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F)); | |
3888 | ||
3889 | /* Turn off auto-detect & fiber mode */ | |
3890 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3891 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val); | |
3892 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3893 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
3894 | (val & 0xFFEE)); | |
3895 | ||
3896 | /* Set filter_force_link, disable_false_link and parallel_detect */ | |
3897 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3898 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); | |
3899 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3900 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
3901 | ((val | 0x0006) & 0xFFFE)); | |
3902 | ||
3903 | /* Set XFI / SFI */ | |
3904 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3905 | MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); | |
3906 | ||
3907 | misc1_val &= ~(0x1f); | |
3908 | ||
3909 | if (is_xfi) { | |
3910 | misc1_val |= 0x5; | |
3911 | tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | | |
3912 | (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | |
3913 | (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); | |
3914 | tx_driver_val = | |
3915 | ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | |
3916 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | |
3917 | (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); | |
3918 | ||
3919 | } else { | |
3920 | misc1_val |= 0x9; | |
25182fc2 YR |
3921 | tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | |
3922 | (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | |
3923 | (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); | |
3c9ada22 | 3924 | tx_driver_val = |
25182fc2 | 3925 | ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | |
3c9ada22 | 3926 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | |
25182fc2 | 3927 | (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); |
3c9ada22 YR |
3928 | } |
3929 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3930 | MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); | |
3931 | ||
3932 | /* Set Transmit PMD settings */ | |
3933 | lane = bnx2x_get_warpcore_lane(phy, params); | |
3934 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3935 | MDIO_WC_REG_TX_FIR_TAP, | |
3936 | tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); | |
3937 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3938 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | |
3939 | tx_driver_val); | |
3940 | ||
3941 | /* Enable fiber mode, enable and invert sig_det */ | |
3942 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3943 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val); | |
3944 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3945 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd); | |
3946 | ||
3947 | /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ | |
3948 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3949 | MDIO_WC_REG_DIGITAL4_MISC3, &val); | |
3950 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3951 | MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080); | |
3952 | ||
3953 | /* 10G XFI Full Duplex */ | |
3954 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3955 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); | |
3956 | ||
3957 | /* Release tx_fifo_reset */ | |
3958 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3959 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val); | |
3960 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3961 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE); | |
3962 | ||
3963 | /* Release rxSeqStart */ | |
3964 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3965 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val); | |
3966 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3967 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF)); | |
3968 | } | |
3969 | ||
3970 | static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp, | |
3971 | struct bnx2x_phy *phy) | |
3972 | { | |
3973 | DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n"); | |
3974 | } | |
3975 | ||
3976 | static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, | |
3977 | struct bnx2x_phy *phy, | |
3978 | u16 lane) | |
3979 | { | |
3980 | /* Rx0 anaRxControl1G */ | |
3981 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3982 | MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); | |
3983 | ||
3984 | /* Rx2 anaRxControl1G */ | |
3985 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3986 | MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); | |
3987 | ||
3988 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3989 | MDIO_WC_REG_RX66_SCW0, 0xE070); | |
3990 | ||
3991 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3992 | MDIO_WC_REG_RX66_SCW1, 0xC0D0); | |
3993 | ||
3994 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3995 | MDIO_WC_REG_RX66_SCW2, 0xA0B0); | |
3996 | ||
3997 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3998 | MDIO_WC_REG_RX66_SCW3, 0x8090); | |
3999 | ||
4000 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4001 | MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); | |
4002 | ||
4003 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4004 | MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); | |
4005 | ||
4006 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4007 | MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); | |
4008 | ||
4009 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4010 | MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); | |
4011 | ||
4012 | /* Serdes Digital Misc1 */ | |
4013 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4014 | MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); | |
4015 | ||
4016 | /* Serdes Digital4 Misc3 */ | |
4017 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4018 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); | |
4019 | ||
4020 | /* Set Transmit PMD settings */ | |
4021 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4022 | MDIO_WC_REG_TX_FIR_TAP, | |
4023 | ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | | |
4024 | (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | |
4025 | (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) | | |
4026 | MDIO_WC_REG_TX_FIR_TAP_ENABLE)); | |
4027 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4028 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | |
4029 | ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | |
4030 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | |
4031 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); | |
4032 | } | |
4033 | ||
4034 | static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, | |
4035 | struct link_params *params, | |
521683da YR |
4036 | u8 fiber_mode, |
4037 | u8 always_autoneg) | |
3c9ada22 YR |
4038 | { |
4039 | struct bnx2x *bp = params->bp; | |
4040 | u16 val16, digctrl_kx1, digctrl_kx2; | |
3c9ada22 YR |
4041 | |
4042 | /* Clear XFI clock comp in non-10G single lane mode. */ | |
4043 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4044 | MDIO_WC_REG_RX66_CONTROL, &val16); | |
4045 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4046 | MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13)); | |
4047 | ||
521683da | 4048 | if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { |
3c9ada22 YR |
4049 | /* SGMII Autoneg */ |
4050 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4051 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
4052 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4053 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, | |
4054 | val16 | 0x1000); | |
4055 | DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); | |
4056 | } else { | |
4057 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4058 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
521683da | 4059 | val16 &= 0xcebf; |
3c9ada22 YR |
4060 | switch (phy->req_line_speed) { |
4061 | case SPEED_10: | |
4062 | break; | |
4063 | case SPEED_100: | |
4064 | val16 |= 0x2000; | |
4065 | break; | |
4066 | case SPEED_1000: | |
4067 | val16 |= 0x0040; | |
4068 | break; | |
4069 | default: | |
94f05b0f JP |
4070 | DP(NETIF_MSG_LINK, |
4071 | "Speed not supported: 0x%x\n", phy->req_line_speed); | |
3c9ada22 YR |
4072 | return; |
4073 | } | |
4074 | ||
4075 | if (phy->req_duplex == DUPLEX_FULL) | |
4076 | val16 |= 0x0100; | |
4077 | ||
4078 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4079 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); | |
4080 | ||
4081 | DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", | |
4082 | phy->req_line_speed); | |
4083 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4084 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
4085 | DP(NETIF_MSG_LINK, " (readback) %x\n", val16); | |
4086 | } | |
4087 | ||
4088 | /* SGMII Slave mode and disable signal detect */ | |
4089 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4090 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); | |
4091 | if (fiber_mode) | |
4092 | digctrl_kx1 = 1; | |
4093 | else | |
4094 | digctrl_kx1 &= 0xff4a; | |
4095 | ||
4096 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4097 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4098 | digctrl_kx1); | |
4099 | ||
4100 | /* Turn off parallel detect */ | |
4101 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4102 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); | |
4103 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4104 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4105 | (digctrl_kx2 & ~(1<<2))); | |
4106 | ||
4107 | /* Re-enable parallel detect */ | |
4108 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4109 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4110 | (digctrl_kx2 | (1<<2))); | |
4111 | ||
4112 | /* Enable autodet */ | |
4113 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4114 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4115 | (digctrl_kx1 | 0x10)); | |
4116 | } | |
4117 | ||
4118 | static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, | |
4119 | struct bnx2x_phy *phy, | |
4120 | u8 reset) | |
4121 | { | |
4122 | u16 val; | |
4123 | /* Take lane out of reset after configuration is finished */ | |
4124 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4125 | MDIO_WC_REG_DIGITAL5_MISC6, &val); | |
4126 | if (reset) | |
4127 | val |= 0xC000; | |
4128 | else | |
4129 | val &= 0x3FFF; | |
4130 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4131 | MDIO_WC_REG_DIGITAL5_MISC6, val); | |
4132 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4133 | MDIO_WC_REG_DIGITAL5_MISC6, &val); | |
4134 | } | |
2f751a80 | 4135 | /* Clear SFI/XFI link settings registers */ |
3c9ada22 YR |
4136 | static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, |
4137 | struct link_params *params, | |
4138 | u16 lane) | |
4139 | { | |
4140 | struct bnx2x *bp = params->bp; | |
4141 | u16 val16; | |
4142 | ||
4143 | /* Set XFI clock comp as default. */ | |
4144 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4145 | MDIO_WC_REG_RX66_CONTROL, &val16); | |
4146 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4147 | MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13)); | |
4148 | ||
4149 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
4150 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); | |
4151 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4152 | MDIO_WC_REG_FX100_CTRL1, 0x014a); | |
4153 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4154 | MDIO_WC_REG_FX100_CTRL3, 0x0800); | |
4155 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4156 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8008); | |
4157 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4158 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195); | |
4159 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4160 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007); | |
4161 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4162 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002); | |
4163 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4164 | MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000); | |
4165 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4166 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4167 | MDIO_WC_REG_TX_FIR_TAP, 0x0000); | |
4168 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4169 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); | |
4170 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4171 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); | |
4172 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4173 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140); | |
4174 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
4175 | } | |
4176 | ||
4177 | static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, | |
4178 | u32 chip_id, | |
4179 | u32 shmem_base, u8 port, | |
4180 | u8 *gpio_num, u8 *gpio_port) | |
4181 | { | |
4182 | u32 cfg_pin; | |
4183 | *gpio_num = 0; | |
4184 | *gpio_port = 0; | |
4185 | if (CHIP_IS_E3(bp)) { | |
4186 | cfg_pin = (REG_RD(bp, shmem_base + | |
4187 | offsetof(struct shmem_region, | |
4188 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
4189 | PORT_HW_CFG_E3_MOD_ABS_MASK) >> | |
4190 | PORT_HW_CFG_E3_MOD_ABS_SHIFT; | |
4191 | ||
8f73f0b9 | 4192 | /* Should not happen. This function called upon interrupt |
3c9ada22 YR |
4193 | * triggered by GPIO ( since EPIO can only generate interrupts |
4194 | * to MCP). | |
4195 | * So if this function was called and none of the GPIOs was set, | |
4196 | * it means the shit hit the fan. | |
4197 | */ | |
4198 | if ((cfg_pin < PIN_CFG_GPIO0_P0) || | |
4199 | (cfg_pin > PIN_CFG_GPIO3_P1)) { | |
94f05b0f JP |
4200 | DP(NETIF_MSG_LINK, |
4201 | "ERROR: Invalid cfg pin %x for module detect indication\n", | |
4202 | cfg_pin); | |
3c9ada22 YR |
4203 | return -EINVAL; |
4204 | } | |
4205 | ||
4206 | *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; | |
4207 | *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; | |
4208 | } else { | |
4209 | *gpio_num = MISC_REGISTERS_GPIO_3; | |
4210 | *gpio_port = port; | |
4211 | } | |
4212 | DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port); | |
4213 | return 0; | |
4214 | } | |
4215 | ||
4216 | static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, | |
4217 | struct link_params *params) | |
4218 | { | |
4219 | struct bnx2x *bp = params->bp; | |
4220 | u8 gpio_num, gpio_port; | |
4221 | u32 gpio_val; | |
4222 | if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, | |
4223 | params->shmem_base, params->port, | |
4224 | &gpio_num, &gpio_port) != 0) | |
4225 | return 0; | |
4226 | gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); | |
4227 | ||
4228 | /* Call the handling function in case module is detected */ | |
4229 | if (gpio_val == 0) | |
4230 | return 1; | |
4231 | else | |
4232 | return 0; | |
4233 | } | |
a9077bfd YR |
4234 | static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, |
4235 | struct link_params *params) | |
4236 | { | |
4237 | u16 gp2_status_reg0, lane; | |
4238 | struct bnx2x *bp = params->bp; | |
4239 | ||
4240 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4241 | ||
4242 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, | |
4243 | &gp2_status_reg0); | |
4244 | ||
4245 | return (gp2_status_reg0 >> (8+lane)) & 0x1; | |
4246 | } | |
4247 | ||
4248 | static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, | |
4249 | struct link_params *params, | |
4250 | struct link_vars *vars) | |
4251 | { | |
4252 | struct bnx2x *bp = params->bp; | |
4253 | u32 serdes_net_if; | |
4254 | u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; | |
4255 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
4256 | ||
4257 | vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; | |
4258 | ||
4259 | if (!vars->turn_to_run_wc_rt) | |
4260 | return; | |
4261 | ||
4262 | /* return if there is no link partner */ | |
4263 | if (!(bnx2x_warpcore_get_sigdet(phy, params))) { | |
4264 | DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n"); | |
4265 | return; | |
4266 | } | |
4267 | ||
4268 | if (vars->rx_tx_asic_rst) { | |
4269 | serdes_net_if = (REG_RD(bp, params->shmem_base + | |
4270 | offsetof(struct shmem_region, dev_info. | |
4271 | port_hw_config[params->port].default_cfg)) & | |
4272 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
4273 | ||
4274 | switch (serdes_net_if) { | |
4275 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
4276 | /* Do we get link yet? */ | |
4277 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, | |
4278 | &gp_status1); | |
4279 | lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ | |
4280 | /*10G KR*/ | |
4281 | lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; | |
4282 | ||
4283 | DP(NETIF_MSG_LINK, | |
4284 | "gp_status1 0x%x\n", gp_status1); | |
4285 | ||
4286 | if (lnkup_kr || lnkup) { | |
4287 | vars->rx_tx_asic_rst = 0; | |
4288 | DP(NETIF_MSG_LINK, | |
4289 | "link up, rx_tx_asic_rst 0x%x\n", | |
4290 | vars->rx_tx_asic_rst); | |
4291 | } else { | |
8f73f0b9 | 4292 | /* Reset the lane to see if link comes up.*/ |
a9077bfd YR |
4293 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
4294 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
4295 | ||
4296 | /* restart Autoneg */ | |
4297 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
4298 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); | |
4299 | ||
4300 | vars->rx_tx_asic_rst--; | |
4301 | DP(NETIF_MSG_LINK, "0x%x retry left\n", | |
4302 | vars->rx_tx_asic_rst); | |
4303 | } | |
4304 | break; | |
4305 | ||
4306 | default: | |
4307 | break; | |
4308 | } | |
4309 | ||
4310 | } /*params->rx_tx_asic_rst*/ | |
4311 | ||
4312 | } | |
3c9ada22 YR |
4313 | static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, |
4314 | struct link_params *params, | |
4315 | struct link_vars *vars) | |
4316 | { | |
4317 | struct bnx2x *bp = params->bp; | |
4318 | u32 serdes_net_if; | |
4319 | u8 fiber_mode; | |
4320 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
4321 | serdes_net_if = (REG_RD(bp, params->shmem_base + | |
4322 | offsetof(struct shmem_region, dev_info. | |
4323 | port_hw_config[params->port].default_cfg)) & | |
4324 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
4325 | DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " | |
4326 | "serdes_net_if = 0x%x\n", | |
4327 | vars->line_speed, serdes_net_if); | |
4328 | bnx2x_set_aer_mmd(params, phy); | |
4329 | ||
4330 | vars->phy_flags |= PHY_XGXS_FLAG; | |
4331 | if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || | |
4332 | (phy->req_line_speed && | |
4333 | ((phy->req_line_speed == SPEED_100) || | |
4334 | (phy->req_line_speed == SPEED_10)))) { | |
4335 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4336 | DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); | |
4337 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
521683da | 4338 | bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); |
3c9ada22 YR |
4339 | } else { |
4340 | switch (serdes_net_if) { | |
4341 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
4342 | /* Enable KR Auto Neg */ | |
6a51c0d1 | 4343 | if (params->loopback_mode != LOOPBACK_EXT) |
3c9ada22 YR |
4344 | bnx2x_warpcore_enable_AN_KR(phy, params, vars); |
4345 | else { | |
4346 | DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); | |
4347 | bnx2x_warpcore_set_10G_KR(phy, params, vars); | |
4348 | } | |
4349 | break; | |
4350 | ||
4351 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | |
4352 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
4353 | if (vars->line_speed == SPEED_10000) { | |
4354 | DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); | |
4355 | bnx2x_warpcore_set_10G_XFI(phy, params, 1); | |
4356 | } else { | |
4357 | if (SINGLE_MEDIA_DIRECT(params)) { | |
4358 | DP(NETIF_MSG_LINK, "1G Fiber\n"); | |
4359 | fiber_mode = 1; | |
4360 | } else { | |
4361 | DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); | |
4362 | fiber_mode = 0; | |
4363 | } | |
4364 | bnx2x_warpcore_set_sgmii_speed(phy, | |
4365 | params, | |
521683da YR |
4366 | fiber_mode, |
4367 | 0); | |
3c9ada22 YR |
4368 | } |
4369 | ||
4370 | break; | |
4371 | ||
4372 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | |
4373 | ||
4374 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
4375 | if (vars->line_speed == SPEED_10000) { | |
4376 | DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); | |
4377 | bnx2x_warpcore_set_10G_XFI(phy, params, 0); | |
4378 | } else if (vars->line_speed == SPEED_1000) { | |
4379 | DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); | |
521683da YR |
4380 | bnx2x_warpcore_set_sgmii_speed( |
4381 | phy, params, 1, 0); | |
3c9ada22 YR |
4382 | } |
4383 | /* Issue Module detection */ | |
4384 | if (bnx2x_is_sfp_module_plugged(phy, params)) | |
4385 | bnx2x_sfp_module_detection(phy, params); | |
4386 | break; | |
4387 | ||
4388 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: | |
4389 | if (vars->line_speed != SPEED_20000) { | |
4390 | DP(NETIF_MSG_LINK, "Speed not supported yet\n"); | |
4391 | return; | |
4392 | } | |
4393 | DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); | |
4394 | bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); | |
4395 | /* Issue Module detection */ | |
4396 | ||
4397 | bnx2x_sfp_module_detection(phy, params); | |
4398 | break; | |
4399 | ||
4400 | case PORT_HW_CFG_NET_SERDES_IF_KR2: | |
4401 | if (vars->line_speed != SPEED_20000) { | |
4402 | DP(NETIF_MSG_LINK, "Speed not supported yet\n"); | |
4403 | return; | |
4404 | } | |
4405 | DP(NETIF_MSG_LINK, "Setting 20G KR2\n"); | |
4406 | bnx2x_warpcore_set_20G_KR2(bp, phy); | |
4407 | break; | |
4408 | ||
4409 | default: | |
94f05b0f JP |
4410 | DP(NETIF_MSG_LINK, |
4411 | "Unsupported Serdes Net Interface 0x%x\n", | |
4412 | serdes_net_if); | |
3c9ada22 YR |
4413 | return; |
4414 | } | |
4415 | } | |
4416 | ||
4417 | /* Take lane out of reset after configuration is finished */ | |
4418 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
4419 | DP(NETIF_MSG_LINK, "Exit config init\n"); | |
4420 | } | |
4421 | ||
4422 | static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, | |
4423 | struct bnx2x_phy *phy, | |
4424 | u8 tx_en) | |
4425 | { | |
4426 | struct bnx2x *bp = params->bp; | |
4427 | u32 cfg_pin; | |
4428 | u8 port = params->port; | |
4429 | ||
4430 | cfg_pin = REG_RD(bp, params->shmem_base + | |
4431 | offsetof(struct shmem_region, | |
4432 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
4433 | PORT_HW_CFG_TX_LASER_MASK; | |
4434 | /* Set the !tx_en since this pin is DISABLE_TX_LASER */ | |
4435 | DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); | |
4436 | /* For 20G, the expected pin to be used is 3 pins after the current */ | |
4437 | ||
4438 | bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); | |
4439 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) | |
4440 | bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); | |
4441 | } | |
4442 | ||
4443 | static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, | |
4444 | struct link_params *params) | |
4445 | { | |
4446 | struct bnx2x *bp = params->bp; | |
4447 | u16 val16; | |
4448 | bnx2x_sfp_e3_set_transmitter(params, phy, 0); | |
4449 | bnx2x_set_mdio_clk(bp, params->chip_id, params->port); | |
4450 | bnx2x_set_aer_mmd(params, phy); | |
4451 | /* Global register */ | |
4452 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
4453 | ||
4454 | /* Clear loopback settings (if any) */ | |
4455 | /* 10G & 20G */ | |
4456 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4457 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
4458 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4459 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 & | |
4460 | 0xBFFF); | |
4461 | ||
4462 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4463 | MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16); | |
4464 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4465 | MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe); | |
4466 | ||
4467 | /* Update those 1-copy registers */ | |
4468 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4469 | MDIO_AER_BLOCK_AER_REG, 0); | |
8f73f0b9 | 4470 | /* Enable 1G MDIO (1-copy) */ |
3c9ada22 YR |
4471 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
4472 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4473 | &val16); | |
4474 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4475 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4476 | val16 & ~0x10); | |
4477 | ||
4478 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4479 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); | |
4480 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4481 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, | |
4482 | val16 & 0xff00); | |
4483 | ||
4484 | } | |
4485 | ||
4486 | static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, | |
4487 | struct link_params *params) | |
4488 | { | |
4489 | struct bnx2x *bp = params->bp; | |
4490 | u16 val16; | |
4491 | u32 lane; | |
4492 | DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", | |
4493 | params->loopback_mode, phy->req_line_speed); | |
4494 | ||
4495 | if (phy->req_line_speed < SPEED_10000) { | |
4496 | /* 10/100/1000 */ | |
4497 | ||
4498 | /* Update those 1-copy registers */ | |
4499 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4500 | MDIO_AER_BLOCK_AER_REG, 0); | |
4501 | /* Enable 1G MDIO (1-copy) */ | |
4502 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4503 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4504 | &val16); | |
4505 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4506 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4507 | val16 | 0x10); | |
4508 | /* Set 1G loopback based on lane (1-copy) */ | |
4509 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4510 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4511 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); | |
4512 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4513 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, | |
4514 | val16 | (1<<lane)); | |
4515 | ||
4516 | /* Switch back to 4-copy registers */ | |
4517 | bnx2x_set_aer_mmd(params, phy); | |
3c9ada22 YR |
4518 | } else { |
4519 | /* 10G & 20G */ | |
4520 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4521 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
4522 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4523 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 | | |
4524 | 0x4000); | |
4525 | ||
4526 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4527 | MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16); | |
4528 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4529 | MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1); | |
4530 | } | |
4531 | } | |
4532 | ||
4533 | ||
2f751a80 YR |
4534 | void bnx2x_sync_link(struct link_params *params, |
4535 | struct link_vars *vars) | |
de6eae1f YR |
4536 | { |
4537 | struct bnx2x *bp = params->bp; | |
9380bb9e | 4538 | u8 link_10g_plus; |
de6f3377 YR |
4539 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) |
4540 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; | |
2f751a80 | 4541 | vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); |
de6eae1f YR |
4542 | if (vars->link_up) { |
4543 | DP(NETIF_MSG_LINK, "phy link up\n"); | |
4544 | ||
4545 | vars->phy_link_up = 1; | |
4546 | vars->duplex = DUPLEX_FULL; | |
4547 | switch (vars->link_status & | |
cd88ccee | 4548 | LINK_STATUS_SPEED_AND_DUPLEX_MASK) { |
8f73f0b9 YR |
4549 | case LINK_10THD: |
4550 | vars->duplex = DUPLEX_HALF; | |
4551 | /* Fall thru */ | |
4552 | case LINK_10TFD: | |
4553 | vars->line_speed = SPEED_10; | |
4554 | break; | |
de6eae1f | 4555 | |
8f73f0b9 YR |
4556 | case LINK_100TXHD: |
4557 | vars->duplex = DUPLEX_HALF; | |
4558 | /* Fall thru */ | |
4559 | case LINK_100T4: | |
4560 | case LINK_100TXFD: | |
4561 | vars->line_speed = SPEED_100; | |
4562 | break; | |
de6eae1f | 4563 | |
8f73f0b9 YR |
4564 | case LINK_1000THD: |
4565 | vars->duplex = DUPLEX_HALF; | |
4566 | /* Fall thru */ | |
4567 | case LINK_1000TFD: | |
4568 | vars->line_speed = SPEED_1000; | |
4569 | break; | |
de6eae1f | 4570 | |
8f73f0b9 YR |
4571 | case LINK_2500THD: |
4572 | vars->duplex = DUPLEX_HALF; | |
4573 | /* Fall thru */ | |
4574 | case LINK_2500TFD: | |
4575 | vars->line_speed = SPEED_2500; | |
4576 | break; | |
de6eae1f | 4577 | |
8f73f0b9 YR |
4578 | case LINK_10GTFD: |
4579 | vars->line_speed = SPEED_10000; | |
4580 | break; | |
4581 | case LINK_20GTFD: | |
4582 | vars->line_speed = SPEED_20000; | |
4583 | break; | |
4584 | default: | |
4585 | break; | |
de6eae1f | 4586 | } |
de6eae1f YR |
4587 | vars->flow_ctrl = 0; |
4588 | if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) | |
4589 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; | |
4590 | ||
4591 | if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) | |
4592 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; | |
4593 | ||
4594 | if (!vars->flow_ctrl) | |
4595 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
4596 | ||
4597 | if (vars->line_speed && | |
4598 | ((vars->line_speed == SPEED_10) || | |
4599 | (vars->line_speed == SPEED_100))) { | |
4600 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4601 | } else { | |
4602 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
4603 | } | |
3c9ada22 YR |
4604 | if (vars->line_speed && |
4605 | USES_WARPCORE(bp) && | |
4606 | (vars->line_speed == SPEED_1000)) | |
4607 | vars->phy_flags |= PHY_SGMII_FLAG; | |
de6eae1f | 4608 | /* anything 10 and over uses the bmac */ |
9380bb9e YR |
4609 | link_10g_plus = (vars->line_speed >= SPEED_10000); |
4610 | ||
4611 | if (link_10g_plus) { | |
4612 | if (USES_WARPCORE(bp)) | |
4613 | vars->mac_type = MAC_TYPE_XMAC; | |
4614 | else | |
3c9ada22 | 4615 | vars->mac_type = MAC_TYPE_BMAC; |
9380bb9e YR |
4616 | } else { |
4617 | if (USES_WARPCORE(bp)) | |
4618 | vars->mac_type = MAC_TYPE_UMAC; | |
3c9ada22 YR |
4619 | else |
4620 | vars->mac_type = MAC_TYPE_EMAC; | |
9380bb9e | 4621 | } |
de6eae1f YR |
4622 | } else { /* link down */ |
4623 | DP(NETIF_MSG_LINK, "phy link down\n"); | |
4624 | ||
4625 | vars->phy_link_up = 0; | |
4626 | ||
4627 | vars->line_speed = 0; | |
4628 | vars->duplex = DUPLEX_FULL; | |
4629 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
4630 | ||
4631 | /* indicate no mac active */ | |
4632 | vars->mac_type = MAC_TYPE_NONE; | |
de6f3377 YR |
4633 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) |
4634 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
de6eae1f | 4635 | } |
2f751a80 YR |
4636 | } |
4637 | ||
4638 | void bnx2x_link_status_update(struct link_params *params, | |
4639 | struct link_vars *vars) | |
4640 | { | |
4641 | struct bnx2x *bp = params->bp; | |
4642 | u8 port = params->port; | |
4643 | u32 sync_offset, media_types; | |
4644 | /* Update PHY configuration */ | |
4645 | set_phy_vars(params, vars); | |
de6eae1f | 4646 | |
2f751a80 YR |
4647 | vars->link_status = REG_RD(bp, params->shmem_base + |
4648 | offsetof(struct shmem_region, | |
4649 | port_mb[port].link_status)); | |
4650 | ||
4651 | vars->phy_flags = PHY_XGXS_FLAG; | |
4652 | bnx2x_sync_link(params, vars); | |
1ac9e428 YR |
4653 | /* Sync media type */ |
4654 | sync_offset = params->shmem_base + | |
4655 | offsetof(struct shmem_region, | |
4656 | dev_info.port_hw_config[port].media_type); | |
4657 | media_types = REG_RD(bp, sync_offset); | |
4658 | ||
4659 | params->phy[INT_PHY].media_type = | |
4660 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> | |
4661 | PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; | |
4662 | params->phy[EXT_PHY1].media_type = | |
4663 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> | |
4664 | PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; | |
4665 | params->phy[EXT_PHY2].media_type = | |
4666 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> | |
4667 | PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; | |
4668 | DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); | |
4669 | ||
020c7e3f YR |
4670 | /* Sync AEU offset */ |
4671 | sync_offset = params->shmem_base + | |
4672 | offsetof(struct shmem_region, | |
4673 | dev_info.port_hw_config[port].aeu_int_mask); | |
4674 | ||
4675 | vars->aeu_int_mask = REG_RD(bp, sync_offset); | |
4676 | ||
b8d6d082 YR |
4677 | /* Sync PFC status */ |
4678 | if (vars->link_status & LINK_STATUS_PFC_ENABLED) | |
4679 | params->feature_config_flags |= | |
4680 | FEATURE_CONFIG_PFC_ENABLED; | |
4681 | else | |
4682 | params->feature_config_flags &= | |
4683 | ~FEATURE_CONFIG_PFC_ENABLED; | |
4684 | ||
020c7e3f YR |
4685 | DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", |
4686 | vars->link_status, vars->phy_link_up, vars->aeu_int_mask); | |
de6eae1f YR |
4687 | DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", |
4688 | vars->line_speed, vars->duplex, vars->flow_ctrl); | |
4689 | } | |
4690 | ||
de6eae1f YR |
4691 | static void bnx2x_set_master_ln(struct link_params *params, |
4692 | struct bnx2x_phy *phy) | |
4693 | { | |
4694 | struct bnx2x *bp = params->bp; | |
4695 | u16 new_master_ln, ser_lane; | |
cd88ccee | 4696 | ser_lane = ((params->lane_config & |
de6eae1f | 4697 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
cd88ccee | 4698 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); |
de6eae1f YR |
4699 | |
4700 | /* set the master_ln for AN */ | |
cd2be89b | 4701 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4702 | MDIO_REG_BANK_XGXS_BLOCK2, |
4703 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
4704 | &new_master_ln); | |
de6eae1f | 4705 | |
cd2be89b | 4706 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4707 | MDIO_REG_BANK_XGXS_BLOCK2 , |
4708 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
4709 | (new_master_ln | ser_lane)); | |
de6eae1f YR |
4710 | } |
4711 | ||
fcf5b650 YR |
4712 | static int bnx2x_reset_unicore(struct link_params *params, |
4713 | struct bnx2x_phy *phy, | |
4714 | u8 set_serdes) | |
de6eae1f YR |
4715 | { |
4716 | struct bnx2x *bp = params->bp; | |
4717 | u16 mii_control; | |
4718 | u16 i; | |
cd2be89b | 4719 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4720 | MDIO_REG_BANK_COMBO_IEEE0, |
4721 | MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); | |
de6eae1f YR |
4722 | |
4723 | /* reset the unicore */ | |
cd2be89b | 4724 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4725 | MDIO_REG_BANK_COMBO_IEEE0, |
4726 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
4727 | (mii_control | | |
4728 | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); | |
de6eae1f YR |
4729 | if (set_serdes) |
4730 | bnx2x_set_serdes_access(bp, params->port); | |
4731 | ||
4732 | /* wait for the reset to self clear */ | |
4733 | for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { | |
4734 | udelay(5); | |
4735 | ||
4736 | /* the reset erased the previous bank value */ | |
cd2be89b | 4737 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4738 | MDIO_REG_BANK_COMBO_IEEE0, |
4739 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
4740 | &mii_control); | |
de6eae1f YR |
4741 | |
4742 | if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { | |
4743 | udelay(5); | |
4744 | return 0; | |
4745 | } | |
4746 | } | |
ea4e040a | 4747 | |
6d870c39 YR |
4748 | netdev_err(bp->dev, "Warning: PHY was not initialized," |
4749 | " Port %d\n", | |
4750 | params->port); | |
ea4e040a YR |
4751 | DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); |
4752 | return -EINVAL; | |
4753 | ||
4754 | } | |
4755 | ||
e10bc84d YR |
4756 | static void bnx2x_set_swap_lanes(struct link_params *params, |
4757 | struct bnx2x_phy *phy) | |
ea4e040a YR |
4758 | { |
4759 | struct bnx2x *bp = params->bp; | |
8f73f0b9 YR |
4760 | /* Each two bits represents a lane number: |
4761 | * No swap is 0123 => 0x1b no need to enable the swap | |
2cf7acf9 | 4762 | */ |
2f751a80 | 4763 | u16 rx_lane_swap, tx_lane_swap; |
ea4e040a | 4764 | |
ea4e040a | 4765 | rx_lane_swap = ((params->lane_config & |
cd88ccee YR |
4766 | PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> |
4767 | PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); | |
ea4e040a | 4768 | tx_lane_swap = ((params->lane_config & |
cd88ccee YR |
4769 | PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> |
4770 | PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); | |
ea4e040a YR |
4771 | |
4772 | if (rx_lane_swap != 0x1b) { | |
cd2be89b | 4773 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4774 | MDIO_REG_BANK_XGXS_BLOCK2, |
4775 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, | |
4776 | (rx_lane_swap | | |
4777 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | | |
4778 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); | |
ea4e040a | 4779 | } else { |
cd2be89b | 4780 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4781 | MDIO_REG_BANK_XGXS_BLOCK2, |
4782 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); | |
ea4e040a YR |
4783 | } |
4784 | ||
4785 | if (tx_lane_swap != 0x1b) { | |
cd2be89b | 4786 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4787 | MDIO_REG_BANK_XGXS_BLOCK2, |
4788 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, | |
4789 | (tx_lane_swap | | |
4790 | MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); | |
ea4e040a | 4791 | } else { |
cd2be89b | 4792 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4793 | MDIO_REG_BANK_XGXS_BLOCK2, |
4794 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); | |
ea4e040a YR |
4795 | } |
4796 | } | |
4797 | ||
e10bc84d YR |
4798 | static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, |
4799 | struct link_params *params) | |
ea4e040a YR |
4800 | { |
4801 | struct bnx2x *bp = params->bp; | |
4802 | u16 control2; | |
cd2be89b | 4803 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4804 | MDIO_REG_BANK_SERDES_DIGITAL, |
4805 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
4806 | &control2); | |
7aa0711f | 4807 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
18afb0a6 YR |
4808 | control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; |
4809 | else | |
4810 | control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; | |
7aa0711f YR |
4811 | DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", |
4812 | phy->speed_cap_mask, control2); | |
cd2be89b | 4813 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4814 | MDIO_REG_BANK_SERDES_DIGITAL, |
4815 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
4816 | control2); | |
ea4e040a | 4817 | |
e10bc84d | 4818 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && |
c18aa15d | 4819 | (phy->speed_cap_mask & |
18afb0a6 | 4820 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { |
ea4e040a YR |
4821 | DP(NETIF_MSG_LINK, "XGXS\n"); |
4822 | ||
cd2be89b | 4823 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4824 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
4825 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, | |
4826 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); | |
ea4e040a | 4827 | |
cd2be89b | 4828 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4829 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
4830 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
4831 | &control2); | |
ea4e040a YR |
4832 | |
4833 | ||
4834 | control2 |= | |
4835 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; | |
4836 | ||
cd2be89b | 4837 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4838 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
4839 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
4840 | control2); | |
ea4e040a YR |
4841 | |
4842 | /* Disable parallel detection of HiG */ | |
cd2be89b | 4843 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4844 | MDIO_REG_BANK_XGXS_BLOCK2, |
4845 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, | |
4846 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | | |
4847 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); | |
ea4e040a YR |
4848 | } |
4849 | } | |
4850 | ||
e10bc84d YR |
4851 | static void bnx2x_set_autoneg(struct bnx2x_phy *phy, |
4852 | struct link_params *params, | |
cd88ccee YR |
4853 | struct link_vars *vars, |
4854 | u8 enable_cl73) | |
ea4e040a YR |
4855 | { |
4856 | struct bnx2x *bp = params->bp; | |
4857 | u16 reg_val; | |
4858 | ||
4859 | /* CL37 Autoneg */ | |
cd2be89b | 4860 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4861 | MDIO_REG_BANK_COMBO_IEEE0, |
4862 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
ea4e040a YR |
4863 | |
4864 | /* CL37 Autoneg Enabled */ | |
8c99e7b0 | 4865 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
4866 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; |
4867 | else /* CL37 Autoneg Disabled */ | |
4868 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
4869 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); | |
4870 | ||
cd2be89b | 4871 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4872 | MDIO_REG_BANK_COMBO_IEEE0, |
4873 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
ea4e040a YR |
4874 | |
4875 | /* Enable/Disable Autodetection */ | |
4876 | ||
cd2be89b | 4877 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4878 | MDIO_REG_BANK_SERDES_DIGITAL, |
4879 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); | |
239d686d EG |
4880 | reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | |
4881 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); | |
4882 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; | |
8c99e7b0 | 4883 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
4884 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; |
4885 | else | |
4886 | reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; | |
4887 | ||
cd2be89b | 4888 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4889 | MDIO_REG_BANK_SERDES_DIGITAL, |
4890 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); | |
ea4e040a YR |
4891 | |
4892 | /* Enable TetonII and BAM autoneg */ | |
cd2be89b | 4893 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4894 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
4895 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
ea4e040a | 4896 | ®_val); |
8c99e7b0 | 4897 | if (vars->line_speed == SPEED_AUTO_NEG) { |
ea4e040a YR |
4898 | /* Enable BAM aneg Mode and TetonII aneg Mode */ |
4899 | reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
4900 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
4901 | } else { | |
4902 | /* TetonII and BAM Autoneg Disabled */ | |
4903 | reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
4904 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
4905 | } | |
cd2be89b | 4906 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4907 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
4908 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
4909 | reg_val); | |
ea4e040a | 4910 | |
239d686d EG |
4911 | if (enable_cl73) { |
4912 | /* Enable Cl73 FSM status bits */ | |
cd2be89b | 4913 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4914 | MDIO_REG_BANK_CL73_USERB0, |
4915 | MDIO_CL73_USERB0_CL73_UCTRL, | |
4916 | 0xe); | |
239d686d EG |
4917 | |
4918 | /* Enable BAM Station Manager*/ | |
cd2be89b | 4919 | CL22_WR_OVER_CL45(bp, phy, |
239d686d EG |
4920 | MDIO_REG_BANK_CL73_USERB0, |
4921 | MDIO_CL73_USERB0_CL73_BAM_CTRL1, | |
4922 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | | |
4923 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | | |
4924 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); | |
4925 | ||
7846e471 | 4926 | /* Advertise CL73 link speeds */ |
cd2be89b | 4927 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4928 | MDIO_REG_BANK_CL73_IEEEB1, |
4929 | MDIO_CL73_IEEEB1_AN_ADV2, | |
4930 | ®_val); | |
7aa0711f | 4931 | if (phy->speed_cap_mask & |
7846e471 YR |
4932 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
4933 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; | |
7aa0711f | 4934 | if (phy->speed_cap_mask & |
7846e471 YR |
4935 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
4936 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; | |
239d686d | 4937 | |
cd2be89b | 4938 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4939 | MDIO_REG_BANK_CL73_IEEEB1, |
4940 | MDIO_CL73_IEEEB1_AN_ADV2, | |
4941 | reg_val); | |
239d686d | 4942 | |
239d686d EG |
4943 | /* CL73 Autoneg Enabled */ |
4944 | reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; | |
4945 | ||
4946 | } else /* CL73 Autoneg Disabled */ | |
4947 | reg_val = 0; | |
ea4e040a | 4948 | |
cd2be89b | 4949 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4950 | MDIO_REG_BANK_CL73_IEEEB0, |
4951 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); | |
ea4e040a YR |
4952 | } |
4953 | ||
4954 | /* program SerDes, forced speed */ | |
e10bc84d YR |
4955 | static void bnx2x_program_serdes(struct bnx2x_phy *phy, |
4956 | struct link_params *params, | |
cd88ccee | 4957 | struct link_vars *vars) |
ea4e040a YR |
4958 | { |
4959 | struct bnx2x *bp = params->bp; | |
4960 | u16 reg_val; | |
4961 | ||
57937203 | 4962 | /* program duplex, disable autoneg and sgmii*/ |
cd2be89b | 4963 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4964 | MDIO_REG_BANK_COMBO_IEEE0, |
4965 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
ea4e040a | 4966 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | |
57937203 EG |
4967 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
4968 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); | |
7aa0711f | 4969 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a | 4970 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; |
cd2be89b | 4971 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4972 | MDIO_REG_BANK_COMBO_IEEE0, |
4973 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
ea4e040a | 4974 | |
8f73f0b9 | 4975 | /* Program speed |
2cf7acf9 YR |
4976 | * - needed only if the speed is greater than 1G (2.5G or 10G) |
4977 | */ | |
cd2be89b | 4978 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4979 | MDIO_REG_BANK_SERDES_DIGITAL, |
4980 | MDIO_SERDES_DIGITAL_MISC1, ®_val); | |
8c99e7b0 YR |
4981 | /* clearing the speed value before setting the right speed */ |
4982 | DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); | |
4983 | ||
4984 | reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | | |
4985 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
4986 | ||
4987 | if (!((vars->line_speed == SPEED_1000) || | |
4988 | (vars->line_speed == SPEED_100) || | |
4989 | (vars->line_speed == SPEED_10))) { | |
4990 | ||
ea4e040a YR |
4991 | reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | |
4992 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
8c99e7b0 | 4993 | if (vars->line_speed == SPEED_10000) |
ea4e040a YR |
4994 | reg_val |= |
4995 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; | |
8c99e7b0 YR |
4996 | } |
4997 | ||
cd2be89b | 4998 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4999 | MDIO_REG_BANK_SERDES_DIGITAL, |
5000 | MDIO_SERDES_DIGITAL_MISC1, reg_val); | |
8c99e7b0 | 5001 | |
ea4e040a YR |
5002 | } |
5003 | ||
9045f6b4 YR |
5004 | static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, |
5005 | struct link_params *params) | |
ea4e040a YR |
5006 | { |
5007 | struct bnx2x *bp = params->bp; | |
5008 | u16 val = 0; | |
5009 | ||
ea4e040a | 5010 | /* set extended capabilities */ |
7aa0711f | 5011 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) |
ea4e040a | 5012 | val |= MDIO_OVER_1G_UP1_2_5G; |
7aa0711f | 5013 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
ea4e040a | 5014 | val |= MDIO_OVER_1G_UP1_10G; |
cd2be89b | 5015 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5016 | MDIO_REG_BANK_OVER_1G, |
5017 | MDIO_OVER_1G_UP1, val); | |
ea4e040a | 5018 | |
cd2be89b | 5019 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5020 | MDIO_REG_BANK_OVER_1G, |
5021 | MDIO_OVER_1G_UP3, 0x400); | |
ea4e040a YR |
5022 | } |
5023 | ||
9045f6b4 YR |
5024 | static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, |
5025 | struct link_params *params, | |
5026 | u16 ieee_fc) | |
8c99e7b0 YR |
5027 | { |
5028 | struct bnx2x *bp = params->bp; | |
7846e471 | 5029 | u16 val; |
8c99e7b0 | 5030 | /* for AN, we are always publishing full duplex */ |
ea4e040a | 5031 | |
cd2be89b | 5032 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5033 | MDIO_REG_BANK_COMBO_IEEE0, |
5034 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); | |
cd2be89b | 5035 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5036 | MDIO_REG_BANK_CL73_IEEEB1, |
5037 | MDIO_CL73_IEEEB1_AN_ADV1, &val); | |
7846e471 YR |
5038 | val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; |
5039 | val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); | |
cd2be89b | 5040 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5041 | MDIO_REG_BANK_CL73_IEEEB1, |
5042 | MDIO_CL73_IEEEB1_AN_ADV1, val); | |
ea4e040a YR |
5043 | } |
5044 | ||
e10bc84d YR |
5045 | static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, |
5046 | struct link_params *params, | |
5047 | u8 enable_cl73) | |
ea4e040a YR |
5048 | { |
5049 | struct bnx2x *bp = params->bp; | |
3a36f2ef | 5050 | u16 mii_control; |
239d686d | 5051 | |
ea4e040a | 5052 | DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); |
3a36f2ef | 5053 | /* Enable and restart BAM/CL37 aneg */ |
ea4e040a | 5054 | |
239d686d | 5055 | if (enable_cl73) { |
cd2be89b | 5056 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5057 | MDIO_REG_BANK_CL73_IEEEB0, |
5058 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5059 | &mii_control); | |
239d686d | 5060 | |
cd2be89b | 5061 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5062 | MDIO_REG_BANK_CL73_IEEEB0, |
5063 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5064 | (mii_control | | |
5065 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | | |
5066 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); | |
239d686d EG |
5067 | } else { |
5068 | ||
cd2be89b | 5069 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5070 | MDIO_REG_BANK_COMBO_IEEE0, |
5071 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5072 | &mii_control); | |
239d686d EG |
5073 | DP(NETIF_MSG_LINK, |
5074 | "bnx2x_restart_autoneg mii_control before = 0x%x\n", | |
5075 | mii_control); | |
cd2be89b | 5076 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5077 | MDIO_REG_BANK_COMBO_IEEE0, |
5078 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5079 | (mii_control | | |
5080 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
5081 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); | |
239d686d | 5082 | } |
ea4e040a YR |
5083 | } |
5084 | ||
e10bc84d YR |
5085 | static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, |
5086 | struct link_params *params, | |
cd88ccee | 5087 | struct link_vars *vars) |
ea4e040a YR |
5088 | { |
5089 | struct bnx2x *bp = params->bp; | |
5090 | u16 control1; | |
5091 | ||
5092 | /* in SGMII mode, the unicore is always slave */ | |
5093 | ||
cd2be89b | 5094 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5095 | MDIO_REG_BANK_SERDES_DIGITAL, |
5096 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
5097 | &control1); | |
ea4e040a YR |
5098 | control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; |
5099 | /* set sgmii mode (and not fiber) */ | |
5100 | control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | | |
5101 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | | |
5102 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); | |
cd2be89b | 5103 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5104 | MDIO_REG_BANK_SERDES_DIGITAL, |
5105 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
5106 | control1); | |
ea4e040a YR |
5107 | |
5108 | /* if forced speed */ | |
8c99e7b0 | 5109 | if (!(vars->line_speed == SPEED_AUTO_NEG)) { |
ea4e040a YR |
5110 | /* set speed, disable autoneg */ |
5111 | u16 mii_control; | |
5112 | ||
cd2be89b | 5113 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5114 | MDIO_REG_BANK_COMBO_IEEE0, |
5115 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5116 | &mii_control); | |
ea4e040a YR |
5117 | mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
5118 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| | |
5119 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); | |
5120 | ||
8c99e7b0 | 5121 | switch (vars->line_speed) { |
ea4e040a YR |
5122 | case SPEED_100: |
5123 | mii_control |= | |
5124 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; | |
5125 | break; | |
5126 | case SPEED_1000: | |
5127 | mii_control |= | |
5128 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; | |
5129 | break; | |
5130 | case SPEED_10: | |
5131 | /* there is nothing to set for 10M */ | |
5132 | break; | |
5133 | default: | |
5134 | /* invalid speed for SGMII */ | |
8c99e7b0 YR |
5135 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
5136 | vars->line_speed); | |
ea4e040a YR |
5137 | break; |
5138 | } | |
5139 | ||
5140 | /* setting the full duplex */ | |
7aa0711f | 5141 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a YR |
5142 | mii_control |= |
5143 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; | |
cd2be89b | 5144 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5145 | MDIO_REG_BANK_COMBO_IEEE0, |
5146 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5147 | mii_control); | |
ea4e040a YR |
5148 | |
5149 | } else { /* AN mode */ | |
5150 | /* enable and restart AN */ | |
e10bc84d | 5151 | bnx2x_restart_autoneg(phy, params, 0); |
ea4e040a YR |
5152 | } |
5153 | } | |
5154 | ||
8f73f0b9 | 5155 | /* Link management |
ea4e040a | 5156 | */ |
fcf5b650 YR |
5157 | static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, |
5158 | struct link_params *params) | |
15ddd2d0 YR |
5159 | { |
5160 | struct bnx2x *bp = params->bp; | |
5161 | u16 pd_10g, status2_1000x; | |
7aa0711f YR |
5162 | if (phy->req_line_speed != SPEED_AUTO_NEG) |
5163 | return 0; | |
cd2be89b | 5164 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5165 | MDIO_REG_BANK_SERDES_DIGITAL, |
5166 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
5167 | &status2_1000x); | |
cd2be89b | 5168 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5169 | MDIO_REG_BANK_SERDES_DIGITAL, |
5170 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
5171 | &status2_1000x); | |
15ddd2d0 YR |
5172 | if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { |
5173 | DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", | |
5174 | params->port); | |
5175 | return 1; | |
5176 | } | |
5177 | ||
cd2be89b | 5178 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5179 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
5180 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, | |
5181 | &pd_10g); | |
15ddd2d0 YR |
5182 | |
5183 | if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { | |
5184 | DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", | |
5185 | params->port); | |
5186 | return 1; | |
5187 | } | |
5188 | return 0; | |
5189 | } | |
ea4e040a | 5190 | |
9e7e8399 MY |
5191 | static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, |
5192 | struct link_params *params, | |
5193 | struct link_vars *vars, | |
5194 | u32 gp_status) | |
5195 | { | |
5196 | u16 ld_pause; /* local driver */ | |
5197 | u16 lp_pause; /* link partner */ | |
5198 | u16 pause_result; | |
5199 | struct bnx2x *bp = params->bp; | |
5200 | if ((gp_status & | |
5201 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
5202 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == | |
5203 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
5204 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { | |
5205 | ||
5206 | CL22_RD_OVER_CL45(bp, phy, | |
5207 | MDIO_REG_BANK_CL73_IEEEB1, | |
5208 | MDIO_CL73_IEEEB1_AN_ADV1, | |
5209 | &ld_pause); | |
5210 | CL22_RD_OVER_CL45(bp, phy, | |
5211 | MDIO_REG_BANK_CL73_IEEEB1, | |
5212 | MDIO_CL73_IEEEB1_AN_LP_ADV1, | |
5213 | &lp_pause); | |
5214 | pause_result = (ld_pause & | |
5215 | MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; | |
5216 | pause_result |= (lp_pause & | |
5217 | MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; | |
5218 | DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); | |
5219 | } else { | |
5220 | CL22_RD_OVER_CL45(bp, phy, | |
5221 | MDIO_REG_BANK_COMBO_IEEE0, | |
5222 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, | |
5223 | &ld_pause); | |
5224 | CL22_RD_OVER_CL45(bp, phy, | |
5225 | MDIO_REG_BANK_COMBO_IEEE0, | |
5226 | MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, | |
5227 | &lp_pause); | |
5228 | pause_result = (ld_pause & | |
5229 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; | |
5230 | pause_result |= (lp_pause & | |
5231 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; | |
5232 | DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); | |
5233 | } | |
5234 | bnx2x_pause_resolve(vars, pause_result); | |
5235 | ||
5236 | } | |
5237 | ||
e10bc84d YR |
5238 | static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, |
5239 | struct link_params *params, | |
5240 | struct link_vars *vars, | |
5241 | u32 gp_status) | |
ea4e040a YR |
5242 | { |
5243 | struct bnx2x *bp = params->bp; | |
c0700f90 | 5244 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a YR |
5245 | |
5246 | /* resolve from gp_status in case of AN complete and not sgmii */ | |
9e7e8399 MY |
5247 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { |
5248 | /* Update the advertised flow-controled of LD/LP in AN */ | |
5249 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
5250 | bnx2x_update_adv_fc(phy, params, vars, gp_status); | |
5251 | /* But set the flow-control result as the requested one */ | |
7aa0711f | 5252 | vars->flow_ctrl = phy->req_flow_ctrl; |
9e7e8399 | 5253 | } else if (phy->req_line_speed != SPEED_AUTO_NEG) |
7aa0711f YR |
5254 | vars->flow_ctrl = params->req_fc_auto_adv; |
5255 | else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && | |
5256 | (!(vars->phy_flags & PHY_SGMII_FLAG))) { | |
e10bc84d | 5257 | if (bnx2x_direct_parallel_detect_used(phy, params)) { |
15ddd2d0 YR |
5258 | vars->flow_ctrl = params->req_fc_auto_adv; |
5259 | return; | |
5260 | } | |
9e7e8399 | 5261 | bnx2x_update_adv_fc(phy, params, vars, gp_status); |
ea4e040a YR |
5262 | } |
5263 | DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); | |
5264 | } | |
5265 | ||
e10bc84d YR |
5266 | static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, |
5267 | struct link_params *params) | |
239d686d EG |
5268 | { |
5269 | struct bnx2x *bp = params->bp; | |
9045f6b4 | 5270 | u16 rx_status, ustat_val, cl37_fsm_received; |
239d686d EG |
5271 | DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); |
5272 | /* Step 1: Make sure signal is detected */ | |
cd2be89b | 5273 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5274 | MDIO_REG_BANK_RX0, |
5275 | MDIO_RX0_RX_STATUS, | |
5276 | &rx_status); | |
239d686d EG |
5277 | if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != |
5278 | (MDIO_RX0_RX_STATUS_SIGDET)) { | |
5279 | DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." | |
5280 | "rx_status(0x80b0) = 0x%x\n", rx_status); | |
cd2be89b | 5281 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5282 | MDIO_REG_BANK_CL73_IEEEB0, |
5283 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5284 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); | |
239d686d EG |
5285 | return; |
5286 | } | |
5287 | /* Step 2: Check CL73 state machine */ | |
cd2be89b | 5288 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5289 | MDIO_REG_BANK_CL73_USERB0, |
5290 | MDIO_CL73_USERB0_CL73_USTAT1, | |
5291 | &ustat_val); | |
239d686d EG |
5292 | if ((ustat_val & |
5293 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
5294 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != | |
5295 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
5296 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { | |
5297 | DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " | |
5298 | "ustat_val(0x8371) = 0x%x\n", ustat_val); | |
5299 | return; | |
5300 | } | |
8f73f0b9 | 5301 | /* Step 3: Check CL37 Message Pages received to indicate LP |
2cf7acf9 YR |
5302 | * supports only CL37 |
5303 | */ | |
cd2be89b | 5304 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5305 | MDIO_REG_BANK_REMOTE_PHY, |
5306 | MDIO_REMOTE_PHY_MISC_RX_STATUS, | |
9045f6b4 YR |
5307 | &cl37_fsm_received); |
5308 | if ((cl37_fsm_received & | |
239d686d EG |
5309 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | |
5310 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != | |
5311 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | | |
5312 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { | |
5313 | DP(NETIF_MSG_LINK, "No CL37 FSM were received. " | |
5314 | "misc_rx_status(0x8330) = 0x%x\n", | |
9045f6b4 | 5315 | cl37_fsm_received); |
239d686d EG |
5316 | return; |
5317 | } | |
8f73f0b9 | 5318 | /* The combined cl37/cl73 fsm state information indicating that |
2cf7acf9 YR |
5319 | * we are connected to a device which does not support cl73, but |
5320 | * does support cl37 BAM. In this case we disable cl73 and | |
5321 | * restart cl37 auto-neg | |
5322 | */ | |
5323 | ||
239d686d | 5324 | /* Disable CL73 */ |
cd2be89b | 5325 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5326 | MDIO_REG_BANK_CL73_IEEEB0, |
5327 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5328 | 0); | |
239d686d | 5329 | /* Restart CL37 autoneg */ |
e10bc84d | 5330 | bnx2x_restart_autoneg(phy, params, 0); |
239d686d EG |
5331 | DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); |
5332 | } | |
7aa0711f YR |
5333 | |
5334 | static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, | |
5335 | struct link_params *params, | |
5336 | struct link_vars *vars, | |
5337 | u32 gp_status) | |
5338 | { | |
5339 | if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) | |
5340 | vars->link_status |= | |
5341 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5342 | ||
5343 | if (bnx2x_direct_parallel_detect_used(phy, params)) | |
5344 | vars->link_status |= | |
5345 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
5346 | } | |
3c9ada22 YR |
5347 | static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, |
5348 | struct link_params *params, | |
5349 | struct link_vars *vars, | |
5350 | u16 is_link_up, | |
5351 | u16 speed_mask, | |
5352 | u16 is_duplex) | |
ea4e040a YR |
5353 | { |
5354 | struct bnx2x *bp = params->bp; | |
7aa0711f YR |
5355 | if (phy->req_line_speed == SPEED_AUTO_NEG) |
5356 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
3c9ada22 YR |
5357 | if (is_link_up) { |
5358 | DP(NETIF_MSG_LINK, "phy link up\n"); | |
ea4e040a YR |
5359 | |
5360 | vars->phy_link_up = 1; | |
5361 | vars->link_status |= LINK_STATUS_LINK_UP; | |
5362 | ||
3c9ada22 | 5363 | switch (speed_mask) { |
ea4e040a | 5364 | case GP_STATUS_10M: |
3c9ada22 | 5365 | vars->line_speed = SPEED_10; |
ea4e040a YR |
5366 | if (vars->duplex == DUPLEX_FULL) |
5367 | vars->link_status |= LINK_10TFD; | |
5368 | else | |
5369 | vars->link_status |= LINK_10THD; | |
5370 | break; | |
5371 | ||
5372 | case GP_STATUS_100M: | |
3c9ada22 | 5373 | vars->line_speed = SPEED_100; |
ea4e040a YR |
5374 | if (vars->duplex == DUPLEX_FULL) |
5375 | vars->link_status |= LINK_100TXFD; | |
5376 | else | |
5377 | vars->link_status |= LINK_100TXHD; | |
5378 | break; | |
5379 | ||
5380 | case GP_STATUS_1G: | |
5381 | case GP_STATUS_1G_KX: | |
3c9ada22 | 5382 | vars->line_speed = SPEED_1000; |
ea4e040a YR |
5383 | if (vars->duplex == DUPLEX_FULL) |
5384 | vars->link_status |= LINK_1000TFD; | |
5385 | else | |
5386 | vars->link_status |= LINK_1000THD; | |
5387 | break; | |
5388 | ||
5389 | case GP_STATUS_2_5G: | |
3c9ada22 | 5390 | vars->line_speed = SPEED_2500; |
ea4e040a YR |
5391 | if (vars->duplex == DUPLEX_FULL) |
5392 | vars->link_status |= LINK_2500TFD; | |
5393 | else | |
5394 | vars->link_status |= LINK_2500THD; | |
5395 | break; | |
5396 | ||
5397 | case GP_STATUS_5G: | |
5398 | case GP_STATUS_6G: | |
5399 | DP(NETIF_MSG_LINK, | |
5400 | "link speed unsupported gp_status 0x%x\n", | |
3c9ada22 | 5401 | speed_mask); |
ea4e040a | 5402 | return -EINVAL; |
ab6ad5a4 | 5403 | |
ea4e040a YR |
5404 | case GP_STATUS_10G_KX4: |
5405 | case GP_STATUS_10G_HIG: | |
5406 | case GP_STATUS_10G_CX4: | |
3c9ada22 YR |
5407 | case GP_STATUS_10G_KR: |
5408 | case GP_STATUS_10G_SFI: | |
5409 | case GP_STATUS_10G_XFI: | |
5410 | vars->line_speed = SPEED_10000; | |
ea4e040a YR |
5411 | vars->link_status |= LINK_10GTFD; |
5412 | break; | |
3c9ada22 YR |
5413 | case GP_STATUS_20G_DXGXS: |
5414 | vars->line_speed = SPEED_20000; | |
5415 | vars->link_status |= LINK_20GTFD; | |
5416 | break; | |
ea4e040a YR |
5417 | default: |
5418 | DP(NETIF_MSG_LINK, | |
5419 | "link speed unsupported gp_status 0x%x\n", | |
3c9ada22 | 5420 | speed_mask); |
ab6ad5a4 | 5421 | return -EINVAL; |
ea4e040a | 5422 | } |
ea4e040a YR |
5423 | } else { /* link_down */ |
5424 | DP(NETIF_MSG_LINK, "phy link down\n"); | |
5425 | ||
5426 | vars->phy_link_up = 0; | |
57963ed9 | 5427 | |
ea4e040a | 5428 | vars->duplex = DUPLEX_FULL; |
c0700f90 | 5429 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a | 5430 | vars->mac_type = MAC_TYPE_NONE; |
3c9ada22 YR |
5431 | } |
5432 | DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", | |
5433 | vars->phy_link_up, vars->line_speed); | |
5434 | return 0; | |
5435 | } | |
5436 | ||
5437 | static int bnx2x_link_settings_status(struct bnx2x_phy *phy, | |
5438 | struct link_params *params, | |
5439 | struct link_vars *vars) | |
5440 | { | |
3c9ada22 YR |
5441 | struct bnx2x *bp = params->bp; |
5442 | ||
5443 | u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; | |
5444 | int rc = 0; | |
5445 | ||
5446 | /* Read gp_status */ | |
5447 | CL22_RD_OVER_CL45(bp, phy, | |
5448 | MDIO_REG_BANK_GP_STATUS, | |
5449 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
5450 | &gp_status); | |
5451 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) | |
5452 | duplex = DUPLEX_FULL; | |
5453 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) | |
5454 | link_up = 1; | |
5455 | speed_mask = gp_status & GP_STATUS_SPEED_MASK; | |
5456 | DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", | |
5457 | gp_status, link_up, speed_mask); | |
5458 | rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, | |
5459 | duplex); | |
5460 | if (rc == -EINVAL) | |
5461 | return rc; | |
239d686d | 5462 | |
3c9ada22 YR |
5463 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { |
5464 | if (SINGLE_MEDIA_DIRECT(params)) { | |
5465 | bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); | |
5466 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
5467 | bnx2x_xgxs_an_resolve(phy, params, vars, | |
5468 | gp_status); | |
5469 | } | |
5470 | } else { /* link_down */ | |
c18aa15d YR |
5471 | if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
5472 | SINGLE_MEDIA_DIRECT(params)) { | |
239d686d | 5473 | /* Check signal is detected */ |
c18aa15d | 5474 | bnx2x_check_fallback_to_cl37(phy, params); |
239d686d | 5475 | } |
ea4e040a YR |
5476 | } |
5477 | ||
9e7e8399 MY |
5478 | /* Read LP advertised speeds*/ |
5479 | if (SINGLE_MEDIA_DIRECT(params) && | |
5480 | (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { | |
5481 | u16 val; | |
5482 | ||
5483 | CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, | |
5484 | MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); | |
5485 | ||
5486 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) | |
5487 | vars->link_status |= | |
5488 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
5489 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | | |
5490 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) | |
5491 | vars->link_status |= | |
5492 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5493 | ||
5494 | CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, | |
5495 | MDIO_OVER_1G_LP_UP1, &val); | |
5496 | ||
5497 | if (val & MDIO_OVER_1G_UP1_2_5G) | |
5498 | vars->link_status |= | |
5499 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; | |
5500 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) | |
5501 | vars->link_status |= | |
5502 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5503 | } | |
5504 | ||
a22f0788 YR |
5505 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", |
5506 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
ea4e040a YR |
5507 | return rc; |
5508 | } | |
5509 | ||
3c9ada22 YR |
5510 | static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, |
5511 | struct link_params *params, | |
5512 | struct link_vars *vars) | |
5513 | { | |
3c9ada22 | 5514 | struct bnx2x *bp = params->bp; |
3c9ada22 YR |
5515 | u8 lane; |
5516 | u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; | |
5517 | int rc = 0; | |
5518 | lane = bnx2x_get_warpcore_lane(phy, params); | |
5519 | /* Read gp_status */ | |
5520 | if (phy->req_line_speed > SPEED_10000) { | |
5521 | u16 temp_link_up; | |
5522 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5523 | 1, &temp_link_up); | |
5524 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5525 | 1, &link_up); | |
5526 | DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", | |
5527 | temp_link_up, link_up); | |
5528 | link_up &= (1<<2); | |
5529 | if (link_up) | |
5530 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
5531 | } else { | |
5532 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5533 | MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1); | |
5534 | DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); | |
5535 | /* Check for either KR or generic link up. */ | |
5536 | gp_status1 = ((gp_status1 >> 8) & 0xf) | | |
5537 | ((gp_status1 >> 12) & 0xf); | |
5538 | link_up = gp_status1 & (1 << lane); | |
5539 | if (link_up && SINGLE_MEDIA_DIRECT(params)) { | |
5540 | u16 pd, gp_status4; | |
5541 | if (phy->req_line_speed == SPEED_AUTO_NEG) { | |
5542 | /* Check Autoneg complete */ | |
5543 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5544 | MDIO_WC_REG_GP2_STATUS_GP_2_4, | |
5545 | &gp_status4); | |
5546 | if (gp_status4 & ((1<<12)<<lane)) | |
5547 | vars->link_status |= | |
5548 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5549 | ||
5550 | /* Check parallel detect used */ | |
5551 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5552 | MDIO_WC_REG_PAR_DET_10G_STATUS, | |
5553 | &pd); | |
5554 | if (pd & (1<<15)) | |
5555 | vars->link_status |= | |
5556 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
5557 | } | |
5558 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
5559 | } | |
5560 | } | |
5561 | ||
9e7e8399 MY |
5562 | if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && |
5563 | SINGLE_MEDIA_DIRECT(params)) { | |
5564 | u16 val; | |
5565 | ||
5566 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
5567 | MDIO_AN_REG_LP_AUTO_NEG2, &val); | |
5568 | ||
5569 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) | |
5570 | vars->link_status |= | |
5571 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
5572 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | | |
5573 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) | |
5574 | vars->link_status |= | |
5575 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5576 | ||
5577 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5578 | MDIO_WC_REG_DIGITAL3_LP_UP1, &val); | |
5579 | ||
5580 | if (val & MDIO_OVER_1G_UP1_2_5G) | |
5581 | vars->link_status |= | |
5582 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; | |
5583 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) | |
5584 | vars->link_status |= | |
5585 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5586 | ||
5587 | } | |
5588 | ||
5589 | ||
3c9ada22 YR |
5590 | if (lane < 2) { |
5591 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5592 | MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); | |
5593 | } else { | |
5594 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5595 | MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); | |
5596 | } | |
5597 | DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); | |
5598 | ||
5599 | if ((lane & 1) == 0) | |
5600 | gp_speed <<= 8; | |
5601 | gp_speed &= 0x3f00; | |
5602 | ||
5603 | ||
5604 | rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, | |
5605 | duplex); | |
5606 | ||
5607 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", | |
5608 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
5609 | return rc; | |
5610 | } | |
ed8680a7 | 5611 | static void bnx2x_set_gmii_tx_driver(struct link_params *params) |
ea4e040a YR |
5612 | { |
5613 | struct bnx2x *bp = params->bp; | |
e10bc84d | 5614 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; |
ea4e040a YR |
5615 | u16 lp_up2; |
5616 | u16 tx_driver; | |
c2c8b03e | 5617 | u16 bank; |
ea4e040a YR |
5618 | |
5619 | /* read precomp */ | |
cd2be89b | 5620 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5621 | MDIO_REG_BANK_OVER_1G, |
5622 | MDIO_OVER_1G_LP_UP2, &lp_up2); | |
ea4e040a | 5623 | |
ea4e040a YR |
5624 | /* bits [10:7] at lp_up2, positioned at [15:12] */ |
5625 | lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> | |
5626 | MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << | |
5627 | MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); | |
5628 | ||
c2c8b03e EG |
5629 | if (lp_up2 == 0) |
5630 | return; | |
5631 | ||
5632 | for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; | |
5633 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { | |
cd2be89b | 5634 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5635 | bank, |
5636 | MDIO_TX0_TX_DRIVER, &tx_driver); | |
c2c8b03e EG |
5637 | |
5638 | /* replace tx_driver bits [15:12] */ | |
5639 | if (lp_up2 != | |
5640 | (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { | |
5641 | tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; | |
5642 | tx_driver |= lp_up2; | |
cd2be89b | 5643 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5644 | bank, |
5645 | MDIO_TX0_TX_DRIVER, tx_driver); | |
c2c8b03e | 5646 | } |
ea4e040a YR |
5647 | } |
5648 | } | |
5649 | ||
fcf5b650 YR |
5650 | static int bnx2x_emac_program(struct link_params *params, |
5651 | struct link_vars *vars) | |
ea4e040a YR |
5652 | { |
5653 | struct bnx2x *bp = params->bp; | |
5654 | u8 port = params->port; | |
5655 | u16 mode = 0; | |
5656 | ||
5657 | DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); | |
5658 | bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + | |
cd88ccee YR |
5659 | EMAC_REG_EMAC_MODE, |
5660 | (EMAC_MODE_25G_MODE | | |
5661 | EMAC_MODE_PORT_MII_10M | | |
5662 | EMAC_MODE_HALF_DUPLEX)); | |
b7737c9b | 5663 | switch (vars->line_speed) { |
ea4e040a YR |
5664 | case SPEED_10: |
5665 | mode |= EMAC_MODE_PORT_MII_10M; | |
5666 | break; | |
5667 | ||
5668 | case SPEED_100: | |
5669 | mode |= EMAC_MODE_PORT_MII; | |
5670 | break; | |
5671 | ||
5672 | case SPEED_1000: | |
5673 | mode |= EMAC_MODE_PORT_GMII; | |
5674 | break; | |
5675 | ||
5676 | case SPEED_2500: | |
5677 | mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); | |
5678 | break; | |
5679 | ||
5680 | default: | |
5681 | /* 10G not valid for EMAC */ | |
b7737c9b YR |
5682 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
5683 | vars->line_speed); | |
ea4e040a YR |
5684 | return -EINVAL; |
5685 | } | |
5686 | ||
b7737c9b | 5687 | if (vars->duplex == DUPLEX_HALF) |
ea4e040a YR |
5688 | mode |= EMAC_MODE_HALF_DUPLEX; |
5689 | bnx2x_bits_en(bp, | |
cd88ccee YR |
5690 | GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, |
5691 | mode); | |
ea4e040a | 5692 | |
7f02c4ad | 5693 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
ea4e040a YR |
5694 | return 0; |
5695 | } | |
5696 | ||
de6eae1f YR |
5697 | static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, |
5698 | struct link_params *params) | |
b7737c9b | 5699 | { |
de6eae1f YR |
5700 | |
5701 | u16 bank, i = 0; | |
5702 | struct bnx2x *bp = params->bp; | |
5703 | ||
5704 | for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; | |
5705 | bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { | |
cd2be89b | 5706 | CL22_WR_OVER_CL45(bp, phy, |
de6eae1f YR |
5707 | bank, |
5708 | MDIO_RX0_RX_EQ_BOOST, | |
5709 | phy->rx_preemphasis[i]); | |
5710 | } | |
5711 | ||
5712 | for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; | |
5713 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { | |
cd2be89b | 5714 | CL22_WR_OVER_CL45(bp, phy, |
de6eae1f YR |
5715 | bank, |
5716 | MDIO_TX0_TX_DRIVER, | |
5717 | phy->tx_preemphasis[i]); | |
5718 | } | |
5719 | } | |
5720 | ||
ec146a6f YR |
5721 | static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, |
5722 | struct link_params *params, | |
5723 | struct link_vars *vars) | |
de6eae1f YR |
5724 | { |
5725 | struct bnx2x *bp = params->bp; | |
5726 | u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || | |
5727 | (params->loopback_mode == LOOPBACK_XGXS)); | |
5728 | if (!(vars->phy_flags & PHY_SGMII_FLAG)) { | |
5729 | if (SINGLE_MEDIA_DIRECT(params) && | |
5730 | (params->feature_config_flags & | |
5731 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) | |
5732 | bnx2x_set_preemphasis(phy, params); | |
5733 | ||
5734 | /* forced speed requested? */ | |
5735 | if (vars->line_speed != SPEED_AUTO_NEG || | |
5736 | (SINGLE_MEDIA_DIRECT(params) && | |
cd88ccee | 5737 | params->loopback_mode == LOOPBACK_EXT)) { |
de6eae1f YR |
5738 | DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); |
5739 | ||
5740 | /* disable autoneg */ | |
5741 | bnx2x_set_autoneg(phy, params, vars, 0); | |
5742 | ||
5743 | /* program speed and duplex */ | |
5744 | bnx2x_program_serdes(phy, params, vars); | |
5745 | ||
5746 | } else { /* AN_mode */ | |
5747 | DP(NETIF_MSG_LINK, "not SGMII, AN\n"); | |
5748 | ||
5749 | /* AN enabled */ | |
9045f6b4 | 5750 | bnx2x_set_brcm_cl37_advertisement(phy, params); |
de6eae1f YR |
5751 | |
5752 | /* program duplex & pause advertisement (for aneg) */ | |
9045f6b4 YR |
5753 | bnx2x_set_ieee_aneg_advertisement(phy, params, |
5754 | vars->ieee_fc); | |
de6eae1f YR |
5755 | |
5756 | /* enable autoneg */ | |
5757 | bnx2x_set_autoneg(phy, params, vars, enable_cl73); | |
5758 | ||
5759 | /* enable and restart AN */ | |
5760 | bnx2x_restart_autoneg(phy, params, enable_cl73); | |
5761 | } | |
5762 | ||
5763 | } else { /* SGMII mode */ | |
5764 | DP(NETIF_MSG_LINK, "SGMII\n"); | |
5765 | ||
5766 | bnx2x_initialize_sgmii_process(phy, params, vars); | |
5767 | } | |
5768 | } | |
5769 | ||
ec146a6f YR |
5770 | static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, |
5771 | struct link_params *params, | |
5772 | struct link_vars *vars) | |
b7737c9b | 5773 | { |
fcf5b650 | 5774 | int rc; |
ec146a6f | 5775 | vars->phy_flags |= PHY_XGXS_FLAG; |
b7737c9b YR |
5776 | if ((phy->req_line_speed && |
5777 | ((phy->req_line_speed == SPEED_100) || | |
5778 | (phy->req_line_speed == SPEED_10))) || | |
5779 | (!phy->req_line_speed && | |
5780 | (phy->speed_cap_mask >= | |
5781 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && | |
5782 | (phy->speed_cap_mask < | |
ec146a6f YR |
5783 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || |
5784 | (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) | |
b7737c9b YR |
5785 | vars->phy_flags |= PHY_SGMII_FLAG; |
5786 | else | |
5787 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
5788 | ||
5789 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
ec146a6f YR |
5790 | bnx2x_set_aer_mmd(params, phy); |
5791 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) | |
5792 | bnx2x_set_master_ln(params, phy); | |
b7737c9b YR |
5793 | |
5794 | rc = bnx2x_reset_unicore(params, phy, 0); | |
5795 | /* reset the SerDes and wait for reset bit return low */ | |
5796 | if (rc != 0) | |
5797 | return rc; | |
5798 | ||
ec146a6f | 5799 | bnx2x_set_aer_mmd(params, phy); |
b7737c9b | 5800 | /* setting the masterLn_def again after the reset */ |
ec146a6f YR |
5801 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { |
5802 | bnx2x_set_master_ln(params, phy); | |
5803 | bnx2x_set_swap_lanes(params, phy); | |
5804 | } | |
b7737c9b YR |
5805 | |
5806 | return rc; | |
5807 | } | |
c18aa15d | 5808 | |
de6eae1f | 5809 | static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, |
6d870c39 YR |
5810 | struct bnx2x_phy *phy, |
5811 | struct link_params *params) | |
ea4e040a | 5812 | { |
de6eae1f | 5813 | u16 cnt, ctrl; |
25985edc | 5814 | /* Wait for soft reset to get cleared up to 1 sec */ |
de6eae1f | 5815 | for (cnt = 0; cnt < 1000; cnt++) { |
52c4d6c4 | 5816 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
6583e33b YR |
5817 | bnx2x_cl22_read(bp, phy, |
5818 | MDIO_PMA_REG_CTRL, &ctrl); | |
5819 | else | |
5820 | bnx2x_cl45_read(bp, phy, | |
5821 | MDIO_PMA_DEVAD, | |
5822 | MDIO_PMA_REG_CTRL, &ctrl); | |
de6eae1f YR |
5823 | if (!(ctrl & (1<<15))) |
5824 | break; | |
5825 | msleep(1); | |
5826 | } | |
6d870c39 YR |
5827 | |
5828 | if (cnt == 1000) | |
5829 | netdev_err(bp->dev, "Warning: PHY was not initialized," | |
5830 | " Port %d\n", | |
5831 | params->port); | |
de6eae1f YR |
5832 | DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); |
5833 | return cnt; | |
ea4e040a YR |
5834 | } |
5835 | ||
de6eae1f | 5836 | static void bnx2x_link_int_enable(struct link_params *params) |
a35da8db | 5837 | { |
de6eae1f YR |
5838 | u8 port = params->port; |
5839 | u32 mask; | |
5840 | struct bnx2x *bp = params->bp; | |
c18aa15d | 5841 | |
2cf7acf9 | 5842 | /* Setting the status to report on link up for either XGXS or SerDes */ |
3c9ada22 YR |
5843 | if (CHIP_IS_E3(bp)) { |
5844 | mask = NIG_MASK_XGXS0_LINK_STATUS; | |
5845 | if (!(SINGLE_MEDIA_DIRECT(params))) | |
5846 | mask |= NIG_MASK_MI_INT; | |
5847 | } else if (params->switch_cfg == SWITCH_CFG_10G) { | |
de6eae1f YR |
5848 | mask = (NIG_MASK_XGXS0_LINK10G | |
5849 | NIG_MASK_XGXS0_LINK_STATUS); | |
5850 | DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); | |
5851 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
5852 | params->phy[INT_PHY].type != | |
5853 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { | |
5854 | mask |= NIG_MASK_MI_INT; | |
5855 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
5856 | } | |
5857 | ||
5858 | } else { /* SerDes */ | |
5859 | mask = NIG_MASK_SERDES0_LINK_STATUS; | |
5860 | DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); | |
5861 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
5862 | params->phy[INT_PHY].type != | |
5863 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { | |
5864 | mask |= NIG_MASK_MI_INT; | |
5865 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
5866 | } | |
5867 | } | |
5868 | bnx2x_bits_en(bp, | |
5869 | NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | |
5870 | mask); | |
5871 | ||
5872 | DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, | |
5873 | (params->switch_cfg == SWITCH_CFG_10G), | |
5874 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
5875 | DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", | |
5876 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
5877 | REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), | |
5878 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); | |
5879 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", | |
5880 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
5881 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
a35da8db EG |
5882 | } |
5883 | ||
a22f0788 YR |
5884 | static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, |
5885 | u8 exp_mi_int) | |
a35da8db | 5886 | { |
a22f0788 YR |
5887 | u32 latch_status = 0; |
5888 | ||
8f73f0b9 | 5889 | /* Disable the MI INT ( external phy int ) by writing 1 to the |
a22f0788 YR |
5890 | * status register. Link down indication is high-active-signal, |
5891 | * so in this case we need to write the status to clear the XOR | |
de6eae1f YR |
5892 | */ |
5893 | /* Read Latched signals */ | |
5894 | latch_status = REG_RD(bp, | |
a22f0788 YR |
5895 | NIG_REG_LATCH_STATUS_0 + port*8); |
5896 | DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); | |
de6eae1f | 5897 | /* Handle only those with latched-signal=up.*/ |
a22f0788 YR |
5898 | if (exp_mi_int) |
5899 | bnx2x_bits_en(bp, | |
5900 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
5901 | + port*4, | |
5902 | NIG_STATUS_EMAC0_MI_INT); | |
5903 | else | |
5904 | bnx2x_bits_dis(bp, | |
5905 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
5906 | + port*4, | |
5907 | NIG_STATUS_EMAC0_MI_INT); | |
5908 | ||
de6eae1f | 5909 | if (latch_status & 1) { |
a22f0788 | 5910 | |
de6eae1f YR |
5911 | /* For all latched-signal=up : Re-Arm Latch signals */ |
5912 | REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, | |
cd88ccee | 5913 | (latch_status & 0xfffe) | (latch_status & 1)); |
de6eae1f | 5914 | } |
a22f0788 | 5915 | /* For all latched-signal=up,Write original_signal to status */ |
a35da8db EG |
5916 | } |
5917 | ||
de6eae1f | 5918 | static void bnx2x_link_int_ack(struct link_params *params, |
3c9ada22 | 5919 | struct link_vars *vars, u8 is_10g_plus) |
b1607af5 | 5920 | { |
e10bc84d | 5921 | struct bnx2x *bp = params->bp; |
de6eae1f | 5922 | u8 port = params->port; |
3c9ada22 | 5923 | u32 mask; |
8f73f0b9 | 5924 | /* First reset all status we assume only one line will be |
2cf7acf9 YR |
5925 | * change at a time |
5926 | */ | |
de6eae1f | 5927 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
cd88ccee YR |
5928 | (NIG_STATUS_XGXS0_LINK10G | |
5929 | NIG_STATUS_XGXS0_LINK_STATUS | | |
5930 | NIG_STATUS_SERDES0_LINK_STATUS)); | |
de6eae1f | 5931 | if (vars->phy_link_up) { |
3c9ada22 YR |
5932 | if (USES_WARPCORE(bp)) |
5933 | mask = NIG_STATUS_XGXS0_LINK_STATUS; | |
5934 | else { | |
5935 | if (is_10g_plus) | |
5936 | mask = NIG_STATUS_XGXS0_LINK10G; | |
5937 | else if (params->switch_cfg == SWITCH_CFG_10G) { | |
8f73f0b9 | 5938 | /* Disable the link interrupt by writing 1 to |
3c9ada22 YR |
5939 | * the relevant lane in the status register |
5940 | */ | |
5941 | u32 ser_lane = | |
5942 | ((params->lane_config & | |
de6eae1f YR |
5943 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
5944 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
3c9ada22 YR |
5945 | mask = ((1 << ser_lane) << |
5946 | NIG_STATUS_XGXS0_LINK_STATUS_SIZE); | |
5947 | } else | |
5948 | mask = NIG_STATUS_SERDES0_LINK_STATUS; | |
de6eae1f | 5949 | } |
3c9ada22 YR |
5950 | DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", |
5951 | mask); | |
5952 | bnx2x_bits_en(bp, | |
5953 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | |
5954 | mask); | |
ea4e040a | 5955 | } |
ea4e040a | 5956 | } |
ea4e040a | 5957 | |
fcf5b650 | 5958 | static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) |
de6eae1f YR |
5959 | { |
5960 | u8 *str_ptr = str; | |
5961 | u32 mask = 0xf0000000; | |
5962 | u8 shift = 8*4; | |
5963 | u8 digit; | |
a22f0788 | 5964 | u8 remove_leading_zeros = 1; |
de6eae1f YR |
5965 | if (*len < 10) { |
5966 | /* Need more than 10chars for this format */ | |
5967 | *str_ptr = '\0'; | |
a22f0788 | 5968 | (*len)--; |
de6eae1f | 5969 | return -EINVAL; |
ea4e040a | 5970 | } |
de6eae1f | 5971 | while (shift > 0) { |
ea4e040a | 5972 | |
de6eae1f YR |
5973 | shift -= 4; |
5974 | digit = ((num & mask) >> shift); | |
a22f0788 YR |
5975 | if (digit == 0 && remove_leading_zeros) { |
5976 | mask = mask >> 4; | |
5977 | continue; | |
5978 | } else if (digit < 0xa) | |
de6eae1f YR |
5979 | *str_ptr = digit + '0'; |
5980 | else | |
5981 | *str_ptr = digit - 0xa + 'a'; | |
a22f0788 | 5982 | remove_leading_zeros = 0; |
de6eae1f | 5983 | str_ptr++; |
a22f0788 | 5984 | (*len)--; |
de6eae1f YR |
5985 | mask = mask >> 4; |
5986 | if (shift == 4*4) { | |
a22f0788 | 5987 | *str_ptr = '.'; |
de6eae1f | 5988 | str_ptr++; |
a22f0788 YR |
5989 | (*len)--; |
5990 | remove_leading_zeros = 1; | |
ea4e040a | 5991 | } |
ea4e040a | 5992 | } |
de6eae1f | 5993 | return 0; |
ea4e040a YR |
5994 | } |
5995 | ||
a22f0788 | 5996 | |
fcf5b650 | 5997 | static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
ea4e040a | 5998 | { |
de6eae1f YR |
5999 | str[0] = '\0'; |
6000 | (*len)--; | |
6001 | return 0; | |
6002 | } | |
ea4e040a | 6003 | |
a1e785e0 MY |
6004 | int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, |
6005 | u16 len) | |
de6eae1f YR |
6006 | { |
6007 | struct bnx2x *bp; | |
6008 | u32 spirom_ver = 0; | |
fcf5b650 | 6009 | int status = 0; |
de6eae1f | 6010 | u8 *ver_p = version; |
a22f0788 | 6011 | u16 remain_len = len; |
de6eae1f YR |
6012 | if (version == NULL || params == NULL) |
6013 | return -EINVAL; | |
6014 | bp = params->bp; | |
ea4e040a | 6015 | |
de6eae1f YR |
6016 | /* Extract first external phy*/ |
6017 | version[0] = '\0'; | |
6018 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); | |
ea4e040a | 6019 | |
a22f0788 | 6020 | if (params->phy[EXT_PHY1].format_fw_ver) { |
de6eae1f YR |
6021 | status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, |
6022 | ver_p, | |
a22f0788 YR |
6023 | &remain_len); |
6024 | ver_p += (len - remain_len); | |
6025 | } | |
6026 | if ((params->num_phys == MAX_PHYS) && | |
6027 | (params->phy[EXT_PHY2].ver_addr != 0)) { | |
cd88ccee | 6028 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); |
a22f0788 YR |
6029 | if (params->phy[EXT_PHY2].format_fw_ver) { |
6030 | *ver_p = '/'; | |
6031 | ver_p++; | |
6032 | remain_len--; | |
6033 | status |= params->phy[EXT_PHY2].format_fw_ver( | |
6034 | spirom_ver, | |
6035 | ver_p, | |
6036 | &remain_len); | |
6037 | ver_p = version + (len - remain_len); | |
6038 | } | |
6039 | } | |
6040 | *ver_p = '\0'; | |
de6eae1f | 6041 | return status; |
6bbca910 | 6042 | } |
ea4e040a | 6043 | |
de6eae1f YR |
6044 | static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, |
6045 | struct link_params *params) | |
589abe3a | 6046 | { |
de6eae1f | 6047 | u8 port = params->port; |
589abe3a | 6048 | struct bnx2x *bp = params->bp; |
589abe3a | 6049 | |
de6eae1f | 6050 | if (phy->req_line_speed != SPEED_1000) { |
3c9ada22 | 6051 | u32 md_devad = 0; |
589abe3a | 6052 | |
de6eae1f | 6053 | DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); |
589abe3a | 6054 | |
3c9ada22 YR |
6055 | if (!CHIP_IS_E3(bp)) { |
6056 | /* change the uni_phy_addr in the nig */ | |
6057 | md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + | |
6058 | port*0x18)); | |
cc1cb004 | 6059 | |
3c9ada22 YR |
6060 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
6061 | 0x5); | |
6062 | } | |
589abe3a | 6063 | |
de6eae1f | 6064 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
6065 | 5, |
6066 | (MDIO_REG_BANK_AER_BLOCK + | |
6067 | (MDIO_AER_BLOCK_AER_REG & 0xf)), | |
6068 | 0x2800); | |
589abe3a | 6069 | |
de6eae1f | 6070 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
6071 | 5, |
6072 | (MDIO_REG_BANK_CL73_IEEEB0 + | |
6073 | (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), | |
6074 | 0x6041); | |
de6eae1f YR |
6075 | msleep(200); |
6076 | /* set aer mmd back */ | |
ec146a6f | 6077 | bnx2x_set_aer_mmd(params, phy); |
589abe3a | 6078 | |
3c9ada22 YR |
6079 | if (!CHIP_IS_E3(bp)) { |
6080 | /* and md_devad */ | |
6081 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, | |
6082 | md_devad); | |
6083 | } | |
de6eae1f YR |
6084 | } else { |
6085 | u16 mii_ctrl; | |
6086 | DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); | |
6087 | bnx2x_cl45_read(bp, phy, 5, | |
6088 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
6089 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
6090 | &mii_ctrl); | |
6091 | bnx2x_cl45_write(bp, phy, 5, | |
6092 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
6093 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
6094 | mii_ctrl | | |
6095 | MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); | |
6096 | } | |
589abe3a EG |
6097 | } |
6098 | ||
fcf5b650 YR |
6099 | int bnx2x_set_led(struct link_params *params, |
6100 | struct link_vars *vars, u8 mode, u32 speed) | |
4d295db0 | 6101 | { |
de6eae1f YR |
6102 | u8 port = params->port; |
6103 | u16 hw_led_mode = params->hw_led_mode; | |
fcf5b650 YR |
6104 | int rc = 0; |
6105 | u8 phy_idx; | |
de6eae1f YR |
6106 | u32 tmp; |
6107 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
589abe3a | 6108 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
6109 | DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); |
6110 | DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", | |
6111 | speed, hw_led_mode); | |
7f02c4ad YR |
6112 | /* In case */ |
6113 | for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { | |
6114 | if (params->phy[phy_idx].set_link_led) { | |
6115 | params->phy[phy_idx].set_link_led( | |
6116 | ¶ms->phy[phy_idx], params, mode); | |
6117 | } | |
6118 | } | |
6119 | ||
de6eae1f | 6120 | switch (mode) { |
7f02c4ad | 6121 | case LED_MODE_FRONT_PANEL_OFF: |
de6eae1f YR |
6122 | case LED_MODE_OFF: |
6123 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); | |
6124 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
cd88ccee | 6125 | SHARED_HW_CFG_LED_MAC1); |
589abe3a | 6126 | |
de6eae1f | 6127 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
001cea77 | 6128 | if (params->phy[EXT_PHY1].type == |
9379c9be YR |
6129 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
6130 | tmp &= ~(EMAC_LED_1000MB_OVERRIDE | | |
6131 | EMAC_LED_100MB_OVERRIDE | | |
6132 | EMAC_LED_10MB_OVERRIDE); | |
6133 | else | |
6134 | tmp |= EMAC_LED_OVERRIDE; | |
6135 | ||
6136 | EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); | |
de6eae1f | 6137 | break; |
589abe3a | 6138 | |
de6eae1f | 6139 | case LED_MODE_OPER: |
8f73f0b9 | 6140 | /* For all other phys, OPER mode is same as ON, so in case |
7f02c4ad | 6141 | * link is down, do nothing |
2cf7acf9 | 6142 | */ |
7f02c4ad YR |
6143 | if (!vars->link_up) |
6144 | break; | |
6145 | case LED_MODE_ON: | |
e4d78f12 YR |
6146 | if (((params->phy[EXT_PHY1].type == |
6147 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || | |
6148 | (params->phy[EXT_PHY1].type == | |
6149 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && | |
1f48353a | 6150 | CHIP_IS_E2(bp) && params->num_phys == 2) { |
8f73f0b9 | 6151 | /* This is a work-around for E2+8727 Configurations */ |
1f48353a YR |
6152 | if (mode == LED_MODE_ON || |
6153 | speed == SPEED_10000){ | |
6154 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); | |
6155 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
6156 | ||
6157 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); | |
6158 | EMAC_WR(bp, EMAC_REG_EMAC_LED, | |
6159 | (tmp | EMAC_LED_OVERRIDE)); | |
8f73f0b9 | 6160 | /* Return here without enabling traffic |
ab505dec | 6161 | * LED blink and setting rate in ON mode. |
793bd450 YR |
6162 | * In oper mode, enabling LED blink |
6163 | * and setting rate is needed. | |
6164 | */ | |
6165 | if (mode == LED_MODE_ON) | |
6166 | return rc; | |
1f48353a | 6167 | } |
793bd450 | 6168 | } else if (SINGLE_MEDIA_DIRECT(params)) { |
8f73f0b9 | 6169 | /* This is a work-around for HW issue found when link |
2cf7acf9 YR |
6170 | * is up in CL73 |
6171 | */ | |
ab505dec YR |
6172 | if ((!CHIP_IS_E3(bp)) || |
6173 | (CHIP_IS_E3(bp) && | |
6174 | mode == LED_MODE_ON)) | |
6175 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
6176 | ||
793bd450 YR |
6177 | if (CHIP_IS_E1x(bp) || |
6178 | CHIP_IS_E2(bp) || | |
6179 | (mode == LED_MODE_ON)) | |
6180 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); | |
6181 | else | |
6182 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
6183 | hw_led_mode); | |
001cea77 YR |
6184 | } else if ((params->phy[EXT_PHY1].type == |
6185 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && | |
9379c9be | 6186 | (mode == LED_MODE_ON)) { |
001cea77 YR |
6187 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); |
6188 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); | |
9379c9be YR |
6189 | EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | |
6190 | EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); | |
6191 | /* Break here; otherwise, it'll disable the | |
6192 | * intended override. | |
6193 | */ | |
6194 | break; | |
793bd450 | 6195 | } else |
001cea77 YR |
6196 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, |
6197 | hw_led_mode); | |
589abe3a | 6198 | |
cd88ccee | 6199 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); |
de6eae1f | 6200 | /* Set blinking rate to ~15.9Hz */ |
26ffaf36 YR |
6201 | if (CHIP_IS_E3(bp)) |
6202 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, | |
6203 | LED_BLINK_RATE_VAL_E3); | |
6204 | else | |
6205 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, | |
6206 | LED_BLINK_RATE_VAL_E1X_E2); | |
de6eae1f | 6207 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + |
cd88ccee | 6208 | port*4, 1); |
9379c9be YR |
6209 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
6210 | EMAC_WR(bp, EMAC_REG_EMAC_LED, | |
6211 | (tmp & (~EMAC_LED_OVERRIDE))); | |
589abe3a | 6212 | |
de6eae1f YR |
6213 | if (CHIP_IS_E1(bp) && |
6214 | ((speed == SPEED_2500) || | |
6215 | (speed == SPEED_1000) || | |
6216 | (speed == SPEED_100) || | |
6217 | (speed == SPEED_10))) { | |
8f73f0b9 | 6218 | /* For speeds less than 10G LED scheme is different */ |
de6eae1f | 6219 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 |
cd88ccee | 6220 | + port*4, 1); |
de6eae1f | 6221 | REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + |
cd88ccee | 6222 | port*4, 0); |
de6eae1f | 6223 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + |
cd88ccee | 6224 | port*4, 1); |
de6eae1f YR |
6225 | } |
6226 | break; | |
589abe3a | 6227 | |
de6eae1f YR |
6228 | default: |
6229 | rc = -EINVAL; | |
6230 | DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", | |
6231 | mode); | |
6232 | break; | |
589abe3a | 6233 | } |
de6eae1f | 6234 | return rc; |
589abe3a | 6235 | |
4d295db0 EG |
6236 | } |
6237 | ||
8f73f0b9 | 6238 | /* This function comes to reflect the actual link state read DIRECTLY from the |
a22f0788 YR |
6239 | * HW |
6240 | */ | |
fcf5b650 YR |
6241 | int bnx2x_test_link(struct link_params *params, struct link_vars *vars, |
6242 | u8 is_serdes) | |
4d295db0 EG |
6243 | { |
6244 | struct bnx2x *bp = params->bp; | |
de6eae1f | 6245 | u16 gp_status = 0, phy_index = 0; |
a22f0788 YR |
6246 | u8 ext_phy_link_up = 0, serdes_phy_type; |
6247 | struct link_vars temp_vars; | |
3c9ada22 YR |
6248 | struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; |
6249 | ||
6250 | if (CHIP_IS_E3(bp)) { | |
6251 | u16 link_up; | |
6252 | if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] | |
6253 | > SPEED_10000) { | |
6254 | /* Check 20G link */ | |
6255 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6256 | 1, &link_up); | |
6257 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6258 | 1, &link_up); | |
6259 | link_up &= (1<<2); | |
6260 | } else { | |
6261 | /* Check 10G link and below*/ | |
6262 | u8 lane = bnx2x_get_warpcore_lane(int_phy, params); | |
6263 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6264 | MDIO_WC_REG_GP2_STATUS_GP_2_1, | |
6265 | &gp_status); | |
6266 | gp_status = ((gp_status >> 8) & 0xf) | | |
6267 | ((gp_status >> 12) & 0xf); | |
6268 | link_up = gp_status & (1 << lane); | |
6269 | } | |
6270 | if (!link_up) | |
6271 | return -ESRCH; | |
6272 | } else { | |
6273 | CL22_RD_OVER_CL45(bp, int_phy, | |
cd88ccee YR |
6274 | MDIO_REG_BANK_GP_STATUS, |
6275 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
6276 | &gp_status); | |
de6eae1f | 6277 | /* link is up only if both local phy and external phy are up */ |
a22f0788 YR |
6278 | if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) |
6279 | return -ESRCH; | |
3c9ada22 YR |
6280 | } |
6281 | /* In XGXS loopback mode, do not check external PHY */ | |
6282 | if (params->loopback_mode == LOOPBACK_XGXS) | |
6283 | return 0; | |
a22f0788 YR |
6284 | |
6285 | switch (params->num_phys) { | |
6286 | case 1: | |
6287 | /* No external PHY */ | |
6288 | return 0; | |
6289 | case 2: | |
6290 | ext_phy_link_up = params->phy[EXT_PHY1].read_status( | |
6291 | ¶ms->phy[EXT_PHY1], | |
6292 | params, &temp_vars); | |
6293 | break; | |
6294 | case 3: /* Dual Media */ | |
de6eae1f YR |
6295 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6296 | phy_index++) { | |
a22f0788 YR |
6297 | serdes_phy_type = ((params->phy[phy_index].media_type == |
6298 | ETH_PHY_SFP_FIBER) || | |
6299 | (params->phy[phy_index].media_type == | |
1ac9e428 YR |
6300 | ETH_PHY_XFP_FIBER) || |
6301 | (params->phy[phy_index].media_type == | |
6302 | ETH_PHY_DA_TWINAX)); | |
a22f0788 YR |
6303 | |
6304 | if (is_serdes != serdes_phy_type) | |
6305 | continue; | |
6306 | if (params->phy[phy_index].read_status) { | |
6307 | ext_phy_link_up |= | |
de6eae1f YR |
6308 | params->phy[phy_index].read_status( |
6309 | ¶ms->phy[phy_index], | |
6310 | params, &temp_vars); | |
a22f0788 | 6311 | } |
de6eae1f | 6312 | } |
a22f0788 | 6313 | break; |
4d295db0 | 6314 | } |
a22f0788 YR |
6315 | if (ext_phy_link_up) |
6316 | return 0; | |
de6eae1f YR |
6317 | return -ESRCH; |
6318 | } | |
4d295db0 | 6319 | |
fcf5b650 YR |
6320 | static int bnx2x_link_initialize(struct link_params *params, |
6321 | struct link_vars *vars) | |
de6eae1f | 6322 | { |
fcf5b650 | 6323 | int rc = 0; |
de6eae1f YR |
6324 | u8 phy_index, non_ext_phy; |
6325 | struct bnx2x *bp = params->bp; | |
8f73f0b9 | 6326 | /* In case of external phy existence, the line speed would be the |
2cf7acf9 YR |
6327 | * line speed linked up by the external phy. In case it is direct |
6328 | * only, then the line_speed during initialization will be | |
6329 | * equal to the req_line_speed | |
6330 | */ | |
de6eae1f | 6331 | vars->line_speed = params->phy[INT_PHY].req_line_speed; |
4d295db0 | 6332 | |
8f73f0b9 | 6333 | /* Initialize the internal phy in case this is a direct board |
de6eae1f YR |
6334 | * (no external phys), or this board has external phy which requires |
6335 | * to first. | |
6336 | */ | |
3c9ada22 YR |
6337 | if (!USES_WARPCORE(bp)) |
6338 | bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); | |
de6eae1f YR |
6339 | /* init ext phy and enable link state int */ |
6340 | non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || | |
6341 | (params->loopback_mode == LOOPBACK_XGXS)); | |
4d295db0 | 6342 | |
de6eae1f YR |
6343 | if (non_ext_phy || |
6344 | (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || | |
6345 | (params->loopback_mode == LOOPBACK_EXT_PHY)) { | |
6346 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; | |
3c9ada22 YR |
6347 | if (vars->line_speed == SPEED_AUTO_NEG && |
6348 | (CHIP_IS_E1x(bp) || | |
6349 | CHIP_IS_E2(bp))) | |
de6eae1f | 6350 | bnx2x_set_parallel_detection(phy, params); |
ec146a6f YR |
6351 | if (params->phy[INT_PHY].config_init) |
6352 | params->phy[INT_PHY].config_init(phy, | |
6353 | params, | |
6354 | vars); | |
4d295db0 EG |
6355 | } |
6356 | ||
de6eae1f | 6357 | /* Init external phy*/ |
fd36a2e6 YR |
6358 | if (non_ext_phy) { |
6359 | if (params->phy[INT_PHY].supported & | |
6360 | SUPPORTED_FIBRE) | |
6361 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6362 | } else { | |
de6eae1f YR |
6363 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6364 | phy_index++) { | |
8f73f0b9 | 6365 | /* No need to initialize second phy in case of first |
a22f0788 YR |
6366 | * phy only selection. In case of second phy, we do |
6367 | * need to initialize the first phy, since they are | |
6368 | * connected. | |
2cf7acf9 | 6369 | */ |
fd36a2e6 YR |
6370 | if (params->phy[phy_index].supported & |
6371 | SUPPORTED_FIBRE) | |
6372 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6373 | ||
a22f0788 YR |
6374 | if (phy_index == EXT_PHY2 && |
6375 | (bnx2x_phy_selection(params) == | |
6376 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { | |
94f05b0f JP |
6377 | DP(NETIF_MSG_LINK, |
6378 | "Not initializing second phy\n"); | |
a22f0788 YR |
6379 | continue; |
6380 | } | |
de6eae1f YR |
6381 | params->phy[phy_index].config_init( |
6382 | ¶ms->phy[phy_index], | |
6383 | params, vars); | |
6384 | } | |
fd36a2e6 | 6385 | } |
de6eae1f YR |
6386 | /* Reset the interrupt indication after phy was initialized */ |
6387 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + | |
6388 | params->port*4, | |
6389 | (NIG_STATUS_XGXS0_LINK10G | | |
6390 | NIG_STATUS_XGXS0_LINK_STATUS | | |
6391 | NIG_STATUS_SERDES0_LINK_STATUS | | |
6392 | NIG_MASK_MI_INT)); | |
6393 | return rc; | |
6394 | } | |
4d295db0 | 6395 | |
de6eae1f YR |
6396 | static void bnx2x_int_link_reset(struct bnx2x_phy *phy, |
6397 | struct link_params *params) | |
6398 | { | |
6399 | /* reset the SerDes/XGXS */ | |
cd88ccee YR |
6400 | REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, |
6401 | (0x1ff << (params->port*16))); | |
589abe3a EG |
6402 | } |
6403 | ||
de6eae1f YR |
6404 | static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, |
6405 | struct link_params *params) | |
4d295db0 | 6406 | { |
de6eae1f YR |
6407 | struct bnx2x *bp = params->bp; |
6408 | u8 gpio_port; | |
6409 | /* HW reset */ | |
f2e0899f DK |
6410 | if (CHIP_IS_E2(bp)) |
6411 | gpio_port = BP_PATH(bp); | |
6412 | else | |
6413 | gpio_port = params->port; | |
de6eae1f | 6414 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee YR |
6415 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
6416 | gpio_port); | |
de6eae1f | 6417 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee YR |
6418 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
6419 | gpio_port); | |
de6eae1f | 6420 | DP(NETIF_MSG_LINK, "reset external PHY\n"); |
4d295db0 | 6421 | } |
589abe3a | 6422 | |
fcf5b650 YR |
6423 | static int bnx2x_update_link_down(struct link_params *params, |
6424 | struct link_vars *vars) | |
589abe3a EG |
6425 | { |
6426 | struct bnx2x *bp = params->bp; | |
de6eae1f | 6427 | u8 port = params->port; |
589abe3a | 6428 | |
de6eae1f | 6429 | DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); |
7f02c4ad | 6430 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
3deb8167 | 6431 | vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; |
de6eae1f YR |
6432 | /* indicate no mac active */ |
6433 | vars->mac_type = MAC_TYPE_NONE; | |
ab6ad5a4 | 6434 | |
de6eae1f | 6435 | /* update shared memory */ |
fd36a2e6 YR |
6436 | vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK | |
6437 | LINK_STATUS_LINK_UP | | |
de6f3377 | 6438 | LINK_STATUS_PHYSICAL_LINK_FLAG | |
fd36a2e6 YR |
6439 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | |
6440 | LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | | |
6441 | LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | | |
9e7e8399 MY |
6442 | LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | |
6443 | LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | | |
6444 | LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE); | |
de6eae1f YR |
6445 | vars->line_speed = 0; |
6446 | bnx2x_update_mng(params, vars->link_status); | |
589abe3a | 6447 | |
de6eae1f YR |
6448 | /* activate nig drain */ |
6449 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); | |
4d295db0 | 6450 | |
de6eae1f | 6451 | /* disable emac */ |
9380bb9e YR |
6452 | if (!CHIP_IS_E3(bp)) |
6453 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
de6eae1f YR |
6454 | |
6455 | msleep(10); | |
9380bb9e YR |
6456 | /* reset BigMac/Xmac */ |
6457 | if (CHIP_IS_E1x(bp) || | |
6458 | CHIP_IS_E2(bp)) { | |
6459 | bnx2x_bmac_rx_disable(bp, params->port); | |
6460 | REG_WR(bp, GRCBASE_MISC + | |
6461 | MISC_REGISTERS_RESET_REG_2_CLEAR, | |
cd88ccee | 6462 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
9380bb9e | 6463 | } |
ce7c0489 | 6464 | if (CHIP_IS_E3(bp)) { |
9380bb9e | 6465 | bnx2x_xmac_disable(params); |
ce7c0489 YR |
6466 | bnx2x_umac_disable(params); |
6467 | } | |
9380bb9e | 6468 | |
589abe3a EG |
6469 | return 0; |
6470 | } | |
de6eae1f | 6471 | |
fcf5b650 YR |
6472 | static int bnx2x_update_link_up(struct link_params *params, |
6473 | struct link_vars *vars, | |
6474 | u8 link_10g) | |
589abe3a EG |
6475 | { |
6476 | struct bnx2x *bp = params->bp; | |
55098c5c | 6477 | u8 phy_idx, port = params->port; |
fcf5b650 | 6478 | int rc = 0; |
4d295db0 | 6479 | |
de6f3377 YR |
6480 | vars->link_status |= (LINK_STATUS_LINK_UP | |
6481 | LINK_STATUS_PHYSICAL_LINK_FLAG); | |
3deb8167 | 6482 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; |
7f02c4ad | 6483 | |
de6eae1f YR |
6484 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
6485 | vars->link_status |= | |
6486 | LINK_STATUS_TX_FLOW_CONTROL_ENABLED; | |
589abe3a | 6487 | |
de6eae1f YR |
6488 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
6489 | vars->link_status |= | |
6490 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED; | |
9380bb9e | 6491 | if (USES_WARPCORE(bp)) { |
3deb8167 YR |
6492 | if (link_10g) { |
6493 | if (bnx2x_xmac_enable(params, vars, 0) == | |
6494 | -ESRCH) { | |
6495 | DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); | |
6496 | vars->link_up = 0; | |
6497 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
6498 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
6499 | } | |
6500 | } else | |
9380bb9e | 6501 | bnx2x_umac_enable(params, vars, 0); |
7f02c4ad | 6502 | bnx2x_set_led(params, vars, |
9380bb9e YR |
6503 | LED_MODE_OPER, vars->line_speed); |
6504 | } | |
6505 | if ((CHIP_IS_E1x(bp) || | |
6506 | CHIP_IS_E2(bp))) { | |
6507 | if (link_10g) { | |
3deb8167 YR |
6508 | if (bnx2x_bmac_enable(params, vars, 0) == |
6509 | -ESRCH) { | |
6510 | DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); | |
6511 | vars->link_up = 0; | |
6512 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
6513 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
6514 | } | |
cc1cb004 | 6515 | |
9380bb9e YR |
6516 | bnx2x_set_led(params, vars, |
6517 | LED_MODE_OPER, SPEED_10000); | |
6518 | } else { | |
6519 | rc = bnx2x_emac_program(params, vars); | |
6520 | bnx2x_emac_enable(params, vars, 0); | |
6521 | ||
6522 | /* AN complete? */ | |
6523 | if ((vars->link_status & | |
6524 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) | |
6525 | && (!(vars->phy_flags & PHY_SGMII_FLAG)) && | |
6526 | SINGLE_MEDIA_DIRECT(params)) | |
6527 | bnx2x_set_gmii_tx_driver(params); | |
6528 | } | |
de6eae1f | 6529 | } |
cc1cb004 | 6530 | |
de6eae1f | 6531 | /* PBF - link up */ |
9380bb9e | 6532 | if (CHIP_IS_E1x(bp)) |
f2e0899f DK |
6533 | rc |= bnx2x_pbf_update(params, vars->flow_ctrl, |
6534 | vars->line_speed); | |
589abe3a | 6535 | |
de6eae1f YR |
6536 | /* disable drain */ |
6537 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); | |
589abe3a | 6538 | |
de6eae1f YR |
6539 | /* update shared memory */ |
6540 | bnx2x_update_mng(params, vars->link_status); | |
55098c5c YR |
6541 | |
6542 | /* Check remote fault */ | |
6543 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { | |
6544 | if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { | |
6545 | bnx2x_check_half_open_conn(params, vars, 0); | |
6546 | break; | |
6547 | } | |
6548 | } | |
de6eae1f YR |
6549 | msleep(20); |
6550 | return rc; | |
589abe3a | 6551 | } |
8f73f0b9 | 6552 | /* The bnx2x_link_update function should be called upon link |
de6eae1f YR |
6553 | * interrupt. |
6554 | * Link is considered up as follows: | |
6555 | * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs | |
6556 | * to be up | |
6557 | * - SINGLE_MEDIA - The link between the 577xx and the external | |
6558 | * phy (XGXS) need to up as well as the external link of the | |
6559 | * phy (PHY_EXT1) | |
6560 | * - DUAL_MEDIA - The link between the 577xx and the first | |
6561 | * external phy needs to be up, and at least one of the 2 | |
6562 | * external phy link must be up. | |
6563 | */ | |
fcf5b650 | 6564 | int bnx2x_link_update(struct link_params *params, struct link_vars *vars) |
4d295db0 | 6565 | { |
de6eae1f YR |
6566 | struct bnx2x *bp = params->bp; |
6567 | struct link_vars phy_vars[MAX_PHYS]; | |
6568 | u8 port = params->port; | |
3c9ada22 | 6569 | u8 link_10g_plus, phy_index; |
fcf5b650 YR |
6570 | u8 ext_phy_link_up = 0, cur_link_up; |
6571 | int rc = 0; | |
de6eae1f YR |
6572 | u8 is_mi_int = 0; |
6573 | u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; | |
6574 | u8 active_external_phy = INT_PHY; | |
3deb8167 | 6575 | vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; |
de6eae1f YR |
6576 | for (phy_index = INT_PHY; phy_index < params->num_phys; |
6577 | phy_index++) { | |
6578 | phy_vars[phy_index].flow_ctrl = 0; | |
6579 | phy_vars[phy_index].link_status = 0; | |
6580 | phy_vars[phy_index].line_speed = 0; | |
6581 | phy_vars[phy_index].duplex = DUPLEX_FULL; | |
6582 | phy_vars[phy_index].phy_link_up = 0; | |
6583 | phy_vars[phy_index].link_up = 0; | |
c688fe2f | 6584 | phy_vars[phy_index].fault_detected = 0; |
de6eae1f | 6585 | } |
4d295db0 | 6586 | |
3c9ada22 YR |
6587 | if (USES_WARPCORE(bp)) |
6588 | bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); | |
6589 | ||
de6eae1f YR |
6590 | DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", |
6591 | port, (vars->phy_flags & PHY_XGXS_FLAG), | |
6592 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
4d295db0 | 6593 | |
de6eae1f | 6594 | is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + |
cd88ccee | 6595 | port*0x18) > 0); |
de6eae1f YR |
6596 | DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", |
6597 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
6598 | is_mi_int, | |
cd88ccee | 6599 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); |
4d295db0 | 6600 | |
de6eae1f YR |
6601 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", |
6602 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
6603 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
4d295db0 | 6604 | |
de6eae1f | 6605 | /* disable emac */ |
9380bb9e YR |
6606 | if (!CHIP_IS_E3(bp)) |
6607 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
4d295db0 | 6608 | |
8f73f0b9 | 6609 | /* Step 1: |
2cf7acf9 YR |
6610 | * Check external link change only for external phys, and apply |
6611 | * priority selection between them in case the link on both phys | |
9045f6b4 | 6612 | * is up. Note that instead of the common vars, a temporary |
2cf7acf9 YR |
6613 | * vars argument is used since each phy may have different link/ |
6614 | * speed/duplex result | |
6615 | */ | |
de6eae1f YR |
6616 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6617 | phy_index++) { | |
6618 | struct bnx2x_phy *phy = ¶ms->phy[phy_index]; | |
6619 | if (!phy->read_status) | |
6620 | continue; | |
6621 | /* Read link status and params of this ext phy */ | |
6622 | cur_link_up = phy->read_status(phy, params, | |
6623 | &phy_vars[phy_index]); | |
6624 | if (cur_link_up) { | |
6625 | DP(NETIF_MSG_LINK, "phy in index %d link is up\n", | |
6626 | phy_index); | |
6627 | } else { | |
6628 | DP(NETIF_MSG_LINK, "phy in index %d link is down\n", | |
6629 | phy_index); | |
6630 | continue; | |
6631 | } | |
e10bc84d | 6632 | |
de6eae1f YR |
6633 | if (!ext_phy_link_up) { |
6634 | ext_phy_link_up = 1; | |
6635 | active_external_phy = phy_index; | |
a22f0788 YR |
6636 | } else { |
6637 | switch (bnx2x_phy_selection(params)) { | |
6638 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
6639 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
8f73f0b9 | 6640 | /* In this option, the first PHY makes sure to pass the |
a22f0788 YR |
6641 | * traffic through itself only. |
6642 | * Its not clear how to reset the link on the second phy | |
2cf7acf9 | 6643 | */ |
a22f0788 YR |
6644 | active_external_phy = EXT_PHY1; |
6645 | break; | |
6646 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
8f73f0b9 | 6647 | /* In this option, the first PHY makes sure to pass the |
a22f0788 | 6648 | * traffic through the second PHY. |
2cf7acf9 | 6649 | */ |
a22f0788 YR |
6650 | active_external_phy = EXT_PHY2; |
6651 | break; | |
6652 | default: | |
8f73f0b9 | 6653 | /* Link indication on both PHYs with the following cases |
a22f0788 YR |
6654 | * is invalid: |
6655 | * - FIRST_PHY means that second phy wasn't initialized, | |
6656 | * hence its link is expected to be down | |
6657 | * - SECOND_PHY means that first phy should not be able | |
6658 | * to link up by itself (using configuration) | |
6659 | * - DEFAULT should be overriden during initialiazation | |
2cf7acf9 | 6660 | */ |
a22f0788 YR |
6661 | DP(NETIF_MSG_LINK, "Invalid link indication" |
6662 | "mpc=0x%x. DISABLING LINK !!!\n", | |
6663 | params->multi_phy_config); | |
6664 | ext_phy_link_up = 0; | |
6665 | break; | |
6666 | } | |
589abe3a | 6667 | } |
589abe3a | 6668 | } |
de6eae1f | 6669 | prev_line_speed = vars->line_speed; |
8f73f0b9 | 6670 | /* Step 2: |
2cf7acf9 YR |
6671 | * Read the status of the internal phy. In case of |
6672 | * DIRECT_SINGLE_MEDIA board, this link is the external link, | |
6673 | * otherwise this is the link between the 577xx and the first | |
6674 | * external phy | |
6675 | */ | |
de6eae1f YR |
6676 | if (params->phy[INT_PHY].read_status) |
6677 | params->phy[INT_PHY].read_status( | |
6678 | ¶ms->phy[INT_PHY], | |
6679 | params, vars); | |
8f73f0b9 | 6680 | /* The INT_PHY flow control reside in the vars. This include the |
de6eae1f YR |
6681 | * case where the speed or flow control are not set to AUTO. |
6682 | * Otherwise, the active external phy flow control result is set | |
6683 | * to the vars. The ext_phy_line_speed is needed to check if the | |
6684 | * speed is different between the internal phy and external phy. | |
6685 | * This case may be result of intermediate link speed change. | |
4d295db0 | 6686 | */ |
de6eae1f YR |
6687 | if (active_external_phy > INT_PHY) { |
6688 | vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; | |
8f73f0b9 | 6689 | /* Link speed is taken from the XGXS. AN and FC result from |
de6eae1f | 6690 | * the external phy. |
4d295db0 | 6691 | */ |
de6eae1f | 6692 | vars->link_status |= phy_vars[active_external_phy].link_status; |
a22f0788 | 6693 | |
8f73f0b9 | 6694 | /* if active_external_phy is first PHY and link is up - disable |
a22f0788 YR |
6695 | * disable TX on second external PHY |
6696 | */ | |
6697 | if (active_external_phy == EXT_PHY1) { | |
6698 | if (params->phy[EXT_PHY2].phy_specific_func) { | |
94f05b0f JP |
6699 | DP(NETIF_MSG_LINK, |
6700 | "Disabling TX on EXT_PHY2\n"); | |
a22f0788 YR |
6701 | params->phy[EXT_PHY2].phy_specific_func( |
6702 | ¶ms->phy[EXT_PHY2], | |
6703 | params, DISABLE_TX); | |
6704 | } | |
6705 | } | |
6706 | ||
de6eae1f YR |
6707 | ext_phy_line_speed = phy_vars[active_external_phy].line_speed; |
6708 | vars->duplex = phy_vars[active_external_phy].duplex; | |
6709 | if (params->phy[active_external_phy].supported & | |
6710 | SUPPORTED_FIBRE) | |
6711 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
fd36a2e6 YR |
6712 | else |
6713 | vars->link_status &= ~LINK_STATUS_SERDES_LINK; | |
de6eae1f YR |
6714 | DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", |
6715 | active_external_phy); | |
6716 | } | |
a22f0788 YR |
6717 | |
6718 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
6719 | phy_index++) { | |
6720 | if (params->phy[phy_index].flags & | |
6721 | FLAGS_REARM_LATCH_SIGNAL) { | |
6722 | bnx2x_rearm_latch_signal(bp, port, | |
6723 | phy_index == | |
6724 | active_external_phy); | |
6725 | break; | |
6726 | } | |
6727 | } | |
de6eae1f YR |
6728 | DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," |
6729 | " ext_phy_line_speed = %d\n", vars->flow_ctrl, | |
6730 | vars->link_status, ext_phy_line_speed); | |
8f73f0b9 | 6731 | /* Upon link speed change set the NIG into drain mode. Comes to |
de6eae1f YR |
6732 | * deals with possible FIFO glitch due to clk change when speed |
6733 | * is decreased without link down indicator | |
6734 | */ | |
4d295db0 | 6735 | |
de6eae1f YR |
6736 | if (vars->phy_link_up) { |
6737 | if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && | |
6738 | (ext_phy_line_speed != vars->line_speed)) { | |
6739 | DP(NETIF_MSG_LINK, "Internal link speed %d is" | |
6740 | " different than the external" | |
6741 | " link speed %d\n", vars->line_speed, | |
6742 | ext_phy_line_speed); | |
6743 | vars->phy_link_up = 0; | |
6744 | } else if (prev_line_speed != vars->line_speed) { | |
cd88ccee YR |
6745 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, |
6746 | 0); | |
de6eae1f YR |
6747 | msleep(1); |
6748 | } | |
6749 | } | |
e10bc84d | 6750 | |
de6eae1f | 6751 | /* anything 10 and over uses the bmac */ |
3c9ada22 | 6752 | link_10g_plus = (vars->line_speed >= SPEED_10000); |
589abe3a | 6753 | |
3c9ada22 | 6754 | bnx2x_link_int_ack(params, vars, link_10g_plus); |
589abe3a | 6755 | |
8f73f0b9 | 6756 | /* In case external phy link is up, and internal link is down |
2cf7acf9 YR |
6757 | * (not initialized yet probably after link initialization, it |
6758 | * needs to be initialized. | |
6759 | * Note that after link down-up as result of cable plug, the xgxs | |
6760 | * link would probably become up again without the need | |
6761 | * initialize it | |
6762 | */ | |
de6eae1f YR |
6763 | if (!(SINGLE_MEDIA_DIRECT(params))) { |
6764 | DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," | |
6765 | " init_preceding = %d\n", ext_phy_link_up, | |
6766 | vars->phy_link_up, | |
6767 | params->phy[EXT_PHY1].flags & | |
6768 | FLAGS_INIT_XGXS_FIRST); | |
6769 | if (!(params->phy[EXT_PHY1].flags & | |
6770 | FLAGS_INIT_XGXS_FIRST) | |
6771 | && ext_phy_link_up && !vars->phy_link_up) { | |
6772 | vars->line_speed = ext_phy_line_speed; | |
6773 | if (vars->line_speed < SPEED_1000) | |
6774 | vars->phy_flags |= PHY_SGMII_FLAG; | |
6775 | else | |
6776 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
ec146a6f YR |
6777 | |
6778 | if (params->phy[INT_PHY].config_init) | |
6779 | params->phy[INT_PHY].config_init( | |
6780 | ¶ms->phy[INT_PHY], params, | |
de6eae1f | 6781 | vars); |
4d295db0 | 6782 | } |
589abe3a | 6783 | } |
8f73f0b9 | 6784 | /* Link is up only if both local phy and external phy (in case of |
9045f6b4 | 6785 | * non-direct board) are up and no fault detected on active PHY. |
4d295db0 | 6786 | */ |
de6eae1f YR |
6787 | vars->link_up = (vars->phy_link_up && |
6788 | (ext_phy_link_up || | |
c688fe2f YR |
6789 | SINGLE_MEDIA_DIRECT(params)) && |
6790 | (phy_vars[active_external_phy].fault_detected == 0)); | |
de6eae1f | 6791 | |
27d9129f YR |
6792 | /* Update the PFC configuration in case it was changed */ |
6793 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
6794 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
6795 | else | |
6796 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; | |
6797 | ||
de6eae1f | 6798 | if (vars->link_up) |
3c9ada22 | 6799 | rc = bnx2x_update_link_up(params, vars, link_10g_plus); |
4d295db0 | 6800 | else |
de6eae1f | 6801 | rc = bnx2x_update_link_down(params, vars); |
589abe3a | 6802 | |
a3348722 BW |
6803 | /* Update MCP link status was changed */ |
6804 | if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) | |
6805 | bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); | |
6806 | ||
4d295db0 | 6807 | return rc; |
589abe3a EG |
6808 | } |
6809 | ||
de6eae1f YR |
6810 | /*****************************************************************************/ |
6811 | /* External Phy section */ | |
6812 | /*****************************************************************************/ | |
6813 | void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) | |
6814 | { | |
6815 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 6816 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
de6eae1f YR |
6817 | msleep(1); |
6818 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 6819 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); |
de6eae1f | 6820 | } |
589abe3a | 6821 | |
de6eae1f YR |
6822 | static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, |
6823 | u32 spirom_ver, u32 ver_addr) | |
6824 | { | |
6825 | DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", | |
6826 | (u16)(spirom_ver>>16), (u16)spirom_ver, port); | |
4d295db0 | 6827 | |
de6eae1f YR |
6828 | if (ver_addr) |
6829 | REG_WR(bp, ver_addr, spirom_ver); | |
589abe3a EG |
6830 | } |
6831 | ||
de6eae1f YR |
6832 | static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, |
6833 | struct bnx2x_phy *phy, | |
6834 | u8 port) | |
6bbca910 | 6835 | { |
de6eae1f YR |
6836 | u16 fw_ver1, fw_ver2; |
6837 | ||
6838 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
cd88ccee | 6839 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); |
de6eae1f | 6840 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
cd88ccee | 6841 | MDIO_PMA_REG_ROM_VER2, &fw_ver2); |
de6eae1f YR |
6842 | bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), |
6843 | phy->ver_addr); | |
ea4e040a | 6844 | } |
ab6ad5a4 | 6845 | |
de6eae1f YR |
6846 | static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, |
6847 | struct bnx2x_phy *phy, | |
6848 | struct link_vars *vars) | |
6849 | { | |
6850 | u16 val; | |
6851 | bnx2x_cl45_read(bp, phy, | |
6852 | MDIO_AN_DEVAD, | |
6853 | MDIO_AN_REG_STATUS, &val); | |
6854 | bnx2x_cl45_read(bp, phy, | |
6855 | MDIO_AN_DEVAD, | |
6856 | MDIO_AN_REG_STATUS, &val); | |
6857 | if (val & (1<<5)) | |
6858 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
6859 | if ((val & (1<<0)) == 0) | |
6860 | vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; | |
6861 | } | |
6862 | ||
6863 | /******************************************************************/ | |
6864 | /* common BCM8073/BCM8727 PHY SECTION */ | |
6865 | /******************************************************************/ | |
6866 | static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, | |
6867 | struct link_params *params, | |
6868 | struct link_vars *vars) | |
6869 | { | |
6870 | struct bnx2x *bp = params->bp; | |
6871 | if (phy->req_line_speed == SPEED_10 || | |
6872 | phy->req_line_speed == SPEED_100) { | |
6873 | vars->flow_ctrl = phy->req_flow_ctrl; | |
6874 | return; | |
6875 | } | |
6876 | ||
6877 | if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && | |
6878 | (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { | |
6879 | u16 pause_result; | |
6880 | u16 ld_pause; /* local */ | |
6881 | u16 lp_pause; /* link partner */ | |
6882 | bnx2x_cl45_read(bp, phy, | |
6883 | MDIO_AN_DEVAD, | |
6884 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
6885 | ||
6886 | bnx2x_cl45_read(bp, phy, | |
6887 | MDIO_AN_DEVAD, | |
6888 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
6889 | pause_result = (ld_pause & | |
6890 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; | |
6891 | pause_result |= (lp_pause & | |
6892 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; | |
6893 | ||
6894 | bnx2x_pause_resolve(vars, pause_result); | |
6895 | DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", | |
6896 | pause_result); | |
6897 | } | |
6898 | } | |
fcf5b650 YR |
6899 | static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, |
6900 | struct bnx2x_phy *phy, | |
6901 | u8 port) | |
de6eae1f | 6902 | { |
5c99274b YR |
6903 | u32 count = 0; |
6904 | u16 fw_ver1, fw_msgout; | |
fcf5b650 | 6905 | int rc = 0; |
5c99274b | 6906 | |
de6eae1f YR |
6907 | /* Boot port from external ROM */ |
6908 | /* EDC grst */ | |
6909 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6910 | MDIO_PMA_DEVAD, |
6911 | MDIO_PMA_REG_GEN_CTRL, | |
6912 | 0x0001); | |
de6eae1f YR |
6913 | |
6914 | /* ucode reboot and rst */ | |
6915 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6916 | MDIO_PMA_DEVAD, |
6917 | MDIO_PMA_REG_GEN_CTRL, | |
6918 | 0x008c); | |
de6eae1f YR |
6919 | |
6920 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6921 | MDIO_PMA_DEVAD, |
6922 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
de6eae1f YR |
6923 | |
6924 | /* Reset internal microprocessor */ | |
6925 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6926 | MDIO_PMA_DEVAD, |
6927 | MDIO_PMA_REG_GEN_CTRL, | |
6928 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
de6eae1f YR |
6929 | |
6930 | /* Release srst bit */ | |
6931 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6932 | MDIO_PMA_DEVAD, |
6933 | MDIO_PMA_REG_GEN_CTRL, | |
6934 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
de6eae1f | 6935 | |
5c99274b YR |
6936 | /* Delay 100ms per the PHY specifications */ |
6937 | msleep(100); | |
6938 | ||
6939 | /* 8073 sometimes taking longer to download */ | |
6940 | do { | |
6941 | count++; | |
6942 | if (count > 300) { | |
6943 | DP(NETIF_MSG_LINK, | |
6944 | "bnx2x_8073_8727_external_rom_boot port %x:" | |
6945 | "Download failed. fw version = 0x%x\n", | |
6946 | port, fw_ver1); | |
6947 | rc = -EINVAL; | |
6948 | break; | |
6949 | } | |
6950 | ||
6951 | bnx2x_cl45_read(bp, phy, | |
6952 | MDIO_PMA_DEVAD, | |
6953 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); | |
6954 | bnx2x_cl45_read(bp, phy, | |
6955 | MDIO_PMA_DEVAD, | |
6956 | MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); | |
6957 | ||
6958 | msleep(1); | |
6959 | } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || | |
6960 | ((fw_msgout & 0xff) != 0x03 && (phy->type == | |
6961 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); | |
de6eae1f YR |
6962 | |
6963 | /* Clear ser_boot_ctl bit */ | |
6964 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6965 | MDIO_PMA_DEVAD, |
6966 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
de6eae1f | 6967 | bnx2x_save_bcm_spirom_ver(bp, phy, port); |
5c99274b YR |
6968 | |
6969 | DP(NETIF_MSG_LINK, | |
6970 | "bnx2x_8073_8727_external_rom_boot port %x:" | |
6971 | "Download complete. fw version = 0x%x\n", | |
6972 | port, fw_ver1); | |
6973 | ||
6974 | return rc; | |
de6eae1f YR |
6975 | } |
6976 | ||
de6eae1f YR |
6977 | /******************************************************************/ |
6978 | /* BCM8073 PHY SECTION */ | |
6979 | /******************************************************************/ | |
fcf5b650 | 6980 | static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) |
de6eae1f YR |
6981 | { |
6982 | /* This is only required for 8073A1, version 102 only */ | |
6983 | u16 val; | |
6984 | ||
6985 | /* Read 8073 HW revision*/ | |
6986 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
6987 | MDIO_PMA_DEVAD, |
6988 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
de6eae1f YR |
6989 | |
6990 | if (val != 1) { | |
6991 | /* No need to workaround in 8073 A1 */ | |
6992 | return 0; | |
6993 | } | |
6994 | ||
6995 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
6996 | MDIO_PMA_DEVAD, |
6997 | MDIO_PMA_REG_ROM_VER2, &val); | |
de6eae1f YR |
6998 | |
6999 | /* SNR should be applied only for version 0x102 */ | |
7000 | if (val != 0x102) | |
7001 | return 0; | |
7002 | ||
7003 | return 1; | |
7004 | } | |
7005 | ||
fcf5b650 | 7006 | static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) |
de6eae1f YR |
7007 | { |
7008 | u16 val, cnt, cnt1 ; | |
7009 | ||
7010 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7011 | MDIO_PMA_DEVAD, |
7012 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
de6eae1f YR |
7013 | |
7014 | if (val > 0) { | |
7015 | /* No need to workaround in 8073 A1 */ | |
7016 | return 0; | |
7017 | } | |
7018 | /* XAUI workaround in 8073 A0: */ | |
7019 | ||
8f73f0b9 | 7020 | /* After loading the boot ROM and restarting Autoneg, poll |
2cf7acf9 YR |
7021 | * Dev1, Reg $C820: |
7022 | */ | |
de6eae1f YR |
7023 | |
7024 | for (cnt = 0; cnt < 1000; cnt++) { | |
7025 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7026 | MDIO_PMA_DEVAD, |
7027 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
7028 | &val); | |
8f73f0b9 | 7029 | /* If bit [14] = 0 or bit [13] = 0, continue on with |
2cf7acf9 YR |
7030 | * system initialization (XAUI work-around not required, as |
7031 | * these bits indicate 2.5G or 1G link up). | |
7032 | */ | |
de6eae1f YR |
7033 | if (!(val & (1<<14)) || !(val & (1<<13))) { |
7034 | DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); | |
7035 | return 0; | |
7036 | } else if (!(val & (1<<15))) { | |
2cf7acf9 | 7037 | DP(NETIF_MSG_LINK, "bit 15 went off\n"); |
8f73f0b9 | 7038 | /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's |
2cf7acf9 YR |
7039 | * MSB (bit15) goes to 1 (indicating that the XAUI |
7040 | * workaround has completed), then continue on with | |
7041 | * system initialization. | |
7042 | */ | |
de6eae1f YR |
7043 | for (cnt1 = 0; cnt1 < 1000; cnt1++) { |
7044 | bnx2x_cl45_read(bp, phy, | |
7045 | MDIO_PMA_DEVAD, | |
7046 | MDIO_PMA_REG_8073_XAUI_WA, &val); | |
7047 | if (val & (1<<15)) { | |
7048 | DP(NETIF_MSG_LINK, | |
7049 | "XAUI workaround has completed\n"); | |
7050 | return 0; | |
7051 | } | |
7052 | msleep(3); | |
7053 | } | |
7054 | break; | |
7055 | } | |
7056 | msleep(3); | |
7057 | } | |
7058 | DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); | |
7059 | return -EINVAL; | |
7060 | } | |
7061 | ||
7062 | static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) | |
7063 | { | |
7064 | /* Force KR or KX */ | |
7065 | bnx2x_cl45_write(bp, phy, | |
7066 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
7067 | bnx2x_cl45_write(bp, phy, | |
7068 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); | |
7069 | bnx2x_cl45_write(bp, phy, | |
7070 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); | |
7071 | bnx2x_cl45_write(bp, phy, | |
7072 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
7073 | } | |
7074 | ||
6bbca910 | 7075 | static void bnx2x_8073_set_pause_cl37(struct link_params *params, |
e10bc84d YR |
7076 | struct bnx2x_phy *phy, |
7077 | struct link_vars *vars) | |
ea4e040a | 7078 | { |
6bbca910 | 7079 | u16 cl37_val; |
e10bc84d YR |
7080 | struct bnx2x *bp = params->bp; |
7081 | bnx2x_cl45_read(bp, phy, | |
62b29a5d | 7082 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); |
6bbca910 YR |
7083 | |
7084 | cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
7085 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
e10bc84d | 7086 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
6bbca910 YR |
7087 | if ((vars->ieee_fc & |
7088 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == | |
7089 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { | |
7090 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; | |
7091 | } | |
7092 | if ((vars->ieee_fc & | |
7093 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
7094 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
7095 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
7096 | } | |
7097 | if ((vars->ieee_fc & | |
7098 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
7099 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
7100 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
7101 | } | |
7102 | DP(NETIF_MSG_LINK, | |
7103 | "Ext phy AN advertize cl37 0x%x\n", cl37_val); | |
7104 | ||
e10bc84d | 7105 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 7106 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); |
6bbca910 | 7107 | msleep(500); |
ea4e040a YR |
7108 | } |
7109 | ||
fcf5b650 YR |
7110 | static int bnx2x_8073_config_init(struct bnx2x_phy *phy, |
7111 | struct link_params *params, | |
7112 | struct link_vars *vars) | |
ea4e040a | 7113 | { |
e10bc84d | 7114 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
7115 | u16 val = 0, tmp1; |
7116 | u8 gpio_port; | |
7117 | DP(NETIF_MSG_LINK, "Init 8073\n"); | |
e10bc84d | 7118 | |
f2e0899f DK |
7119 | if (CHIP_IS_E2(bp)) |
7120 | gpio_port = BP_PATH(bp); | |
7121 | else | |
7122 | gpio_port = params->port; | |
de6eae1f YR |
7123 | /* Restore normal power mode*/ |
7124 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 7125 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
e10bc84d | 7126 | |
de6eae1f | 7127 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 7128 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
ea4e040a | 7129 | |
de6eae1f YR |
7130 | /* enable LASI */ |
7131 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 7132 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); |
de6eae1f | 7133 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 7134 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); |
c2c8b03e | 7135 | |
de6eae1f | 7136 | bnx2x_8073_set_pause_cl37(params, phy, vars); |
57963ed9 | 7137 | |
e10bc84d | 7138 | bnx2x_cl45_read(bp, phy, |
de6eae1f | 7139 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); |
2f904460 | 7140 | |
de6eae1f | 7141 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 7142 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); |
2f904460 | 7143 | |
de6eae1f | 7144 | DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); |
a1e4be39 | 7145 | |
74d7a119 YR |
7146 | /* Swap polarity if required - Must be done only in non-1G mode */ |
7147 | if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
7148 | /* Configure the 8073 to swap _P and _N of the KR lines */ | |
7149 | DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); | |
7150 | /* 10G Rx/Tx and 1G Tx signal polarity swap */ | |
7151 | bnx2x_cl45_read(bp, phy, | |
7152 | MDIO_PMA_DEVAD, | |
7153 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); | |
7154 | bnx2x_cl45_write(bp, phy, | |
7155 | MDIO_PMA_DEVAD, | |
7156 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, | |
7157 | (val | (3<<9))); | |
7158 | } | |
7159 | ||
7160 | ||
de6eae1f | 7161 | /* Enable CL37 BAM */ |
121839be YR |
7162 | if (REG_RD(bp, params->shmem_base + |
7163 | offsetof(struct shmem_region, dev_info. | |
7164 | port_hw_config[params->port].default_cfg)) & | |
7165 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
57963ed9 | 7166 | |
121839be YR |
7167 | bnx2x_cl45_read(bp, phy, |
7168 | MDIO_AN_DEVAD, | |
7169 | MDIO_AN_REG_8073_BAM, &val); | |
7170 | bnx2x_cl45_write(bp, phy, | |
7171 | MDIO_AN_DEVAD, | |
7172 | MDIO_AN_REG_8073_BAM, val | 1); | |
7173 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); | |
7174 | } | |
de6eae1f YR |
7175 | if (params->loopback_mode == LOOPBACK_EXT) { |
7176 | bnx2x_807x_force_10G(bp, phy); | |
7177 | DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); | |
7178 | return 0; | |
7179 | } else { | |
7180 | bnx2x_cl45_write(bp, phy, | |
7181 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); | |
7182 | } | |
7183 | if (phy->req_line_speed != SPEED_AUTO_NEG) { | |
7184 | if (phy->req_line_speed == SPEED_10000) { | |
7185 | val = (1<<7); | |
7186 | } else if (phy->req_line_speed == SPEED_2500) { | |
7187 | val = (1<<5); | |
8f73f0b9 | 7188 | /* Note that 2.5G works only when used with 1G |
25985edc | 7189 | * advertisement |
2cf7acf9 | 7190 | */ |
de6eae1f YR |
7191 | } else |
7192 | val = (1<<5); | |
7193 | } else { | |
7194 | val = 0; | |
7195 | if (phy->speed_cap_mask & | |
7196 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
7197 | val |= (1<<7); | |
57963ed9 | 7198 | |
25985edc | 7199 | /* Note that 2.5G works only when used with 1G advertisement */ |
de6eae1f YR |
7200 | if (phy->speed_cap_mask & |
7201 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | | |
7202 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) | |
7203 | val |= (1<<5); | |
7204 | DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); | |
7205 | } | |
57963ed9 | 7206 | |
de6eae1f YR |
7207 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); |
7208 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); | |
57963ed9 | 7209 | |
de6eae1f YR |
7210 | if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && |
7211 | (phy->req_line_speed == SPEED_AUTO_NEG)) || | |
7212 | (phy->req_line_speed == SPEED_2500)) { | |
7213 | u16 phy_ver; | |
7214 | /* Allow 2.5G for A1 and above */ | |
7215 | bnx2x_cl45_read(bp, phy, | |
7216 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, | |
7217 | &phy_ver); | |
7218 | DP(NETIF_MSG_LINK, "Add 2.5G\n"); | |
7219 | if (phy_ver > 0) | |
7220 | tmp1 |= 1; | |
7221 | else | |
7222 | tmp1 &= 0xfffe; | |
7223 | } else { | |
7224 | DP(NETIF_MSG_LINK, "Disable 2.5G\n"); | |
7225 | tmp1 &= 0xfffe; | |
7226 | } | |
57963ed9 | 7227 | |
de6eae1f YR |
7228 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); |
7229 | /* Add support for CL37 (passive mode) II */ | |
57963ed9 | 7230 | |
de6eae1f YR |
7231 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); |
7232 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, | |
7233 | (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? | |
7234 | 0x20 : 0x40))); | |
57963ed9 | 7235 | |
de6eae1f YR |
7236 | /* Add support for CL37 (passive mode) III */ |
7237 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
57963ed9 | 7238 | |
8f73f0b9 | 7239 | /* The SNR will improve about 2db by changing BW and FEE main |
2cf7acf9 YR |
7240 | * tap. Rest commands are executed after link is up |
7241 | * Change FFE main cursor to 5 in EDC register | |
7242 | */ | |
de6eae1f YR |
7243 | if (bnx2x_8073_is_snr_needed(bp, phy)) |
7244 | bnx2x_cl45_write(bp, phy, | |
7245 | MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, | |
7246 | 0xFB0C); | |
57963ed9 | 7247 | |
de6eae1f YR |
7248 | /* Enable FEC (Forware Error Correction) Request in the AN */ |
7249 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); | |
7250 | tmp1 |= (1<<15); | |
7251 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); | |
57963ed9 | 7252 | |
de6eae1f | 7253 | bnx2x_ext_phy_set_pause(params, phy, vars); |
57963ed9 | 7254 | |
de6eae1f YR |
7255 | /* Restart autoneg */ |
7256 | msleep(500); | |
7257 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
7258 | DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", | |
7259 | ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); | |
7260 | return 0; | |
b7737c9b | 7261 | } |
ea4e040a | 7262 | |
de6eae1f | 7263 | static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
7264 | struct link_params *params, |
7265 | struct link_vars *vars) | |
7266 | { | |
7267 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
7268 | u8 link_up = 0; |
7269 | u16 val1, val2; | |
7270 | u16 link_status = 0; | |
7271 | u16 an1000_status = 0; | |
a35da8db | 7272 | |
de6eae1f | 7273 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 7274 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
b7737c9b | 7275 | |
de6eae1f | 7276 | DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); |
ea4e040a | 7277 | |
de6eae1f YR |
7278 | /* clear the interrupt LASI status register */ |
7279 | bnx2x_cl45_read(bp, phy, | |
7280 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
7281 | bnx2x_cl45_read(bp, phy, | |
7282 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); | |
7283 | DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); | |
7284 | /* Clear MSG-OUT */ | |
7285 | bnx2x_cl45_read(bp, phy, | |
7286 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
7287 | ||
7288 | /* Check the LASI */ | |
7289 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 7290 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); |
de6eae1f YR |
7291 | |
7292 | DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); | |
7293 | ||
7294 | /* Check the link status */ | |
7295 | bnx2x_cl45_read(bp, phy, | |
7296 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
7297 | DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); | |
7298 | ||
7299 | bnx2x_cl45_read(bp, phy, | |
7300 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
7301 | bnx2x_cl45_read(bp, phy, | |
7302 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
7303 | link_up = ((val1 & 4) == 4); | |
7304 | DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); | |
7305 | ||
7306 | if (link_up && | |
7307 | ((phy->req_line_speed != SPEED_10000))) { | |
7308 | if (bnx2x_8073_xaui_wa(bp, phy) != 0) | |
7309 | return 0; | |
62b29a5d | 7310 | } |
de6eae1f YR |
7311 | bnx2x_cl45_read(bp, phy, |
7312 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
7313 | bnx2x_cl45_read(bp, phy, | |
7314 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
62b29a5d | 7315 | |
de6eae1f YR |
7316 | /* Check the link status on 1.1.2 */ |
7317 | bnx2x_cl45_read(bp, phy, | |
7318 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
7319 | bnx2x_cl45_read(bp, phy, | |
7320 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
7321 | DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," | |
7322 | "an_link_status=0x%x\n", val2, val1, an1000_status); | |
62b29a5d | 7323 | |
de6eae1f YR |
7324 | link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); |
7325 | if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { | |
8f73f0b9 | 7326 | /* The SNR will improve about 2dbby changing the BW and FEE main |
2cf7acf9 YR |
7327 | * tap. The 1st write to change FFE main tap is set before |
7328 | * restart AN. Change PLL Bandwidth in EDC register | |
7329 | */ | |
62b29a5d | 7330 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
7331 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, |
7332 | 0x26BC); | |
62b29a5d | 7333 | |
de6eae1f | 7334 | /* Change CDR Bandwidth in EDC register */ |
62b29a5d | 7335 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
7336 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, |
7337 | 0x0333); | |
7338 | } | |
7339 | bnx2x_cl45_read(bp, phy, | |
7340 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
7341 | &link_status); | |
62b29a5d | 7342 | |
de6eae1f YR |
7343 | /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ |
7344 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { | |
7345 | link_up = 1; | |
7346 | vars->line_speed = SPEED_10000; | |
7347 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", | |
7348 | params->port); | |
7349 | } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { | |
7350 | link_up = 1; | |
7351 | vars->line_speed = SPEED_2500; | |
7352 | DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", | |
7353 | params->port); | |
7354 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { | |
7355 | link_up = 1; | |
7356 | vars->line_speed = SPEED_1000; | |
7357 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
7358 | params->port); | |
7359 | } else { | |
7360 | link_up = 0; | |
7361 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
7362 | params->port); | |
62b29a5d | 7363 | } |
de6eae1f YR |
7364 | |
7365 | if (link_up) { | |
74d7a119 YR |
7366 | /* Swap polarity if required */ |
7367 | if (params->lane_config & | |
7368 | PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
7369 | /* Configure the 8073 to swap P and N of the KR lines */ | |
7370 | bnx2x_cl45_read(bp, phy, | |
7371 | MDIO_XS_DEVAD, | |
7372 | MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); | |
8f73f0b9 | 7373 | /* Set bit 3 to invert Rx in 1G mode and clear this bit |
2cf7acf9 YR |
7374 | * when it`s in 10G mode. |
7375 | */ | |
74d7a119 YR |
7376 | if (vars->line_speed == SPEED_1000) { |
7377 | DP(NETIF_MSG_LINK, "Swapping 1G polarity for" | |
7378 | "the 8073\n"); | |
7379 | val1 |= (1<<3); | |
7380 | } else | |
7381 | val1 &= ~(1<<3); | |
7382 | ||
7383 | bnx2x_cl45_write(bp, phy, | |
7384 | MDIO_XS_DEVAD, | |
7385 | MDIO_XS_REG_8073_RX_CTRL_PCIE, | |
7386 | val1); | |
7387 | } | |
de6eae1f YR |
7388 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); |
7389 | bnx2x_8073_resolve_fc(phy, params, vars); | |
791f18c0 | 7390 | vars->duplex = DUPLEX_FULL; |
de6eae1f | 7391 | } |
9e7e8399 MY |
7392 | |
7393 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
7394 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
7395 | MDIO_AN_REG_LP_AUTO_NEG2, &val1); | |
7396 | ||
7397 | if (val1 & (1<<5)) | |
7398 | vars->link_status |= | |
7399 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
7400 | if (val1 & (1<<7)) | |
7401 | vars->link_status |= | |
7402 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
7403 | } | |
7404 | ||
de6eae1f | 7405 | return link_up; |
b7737c9b YR |
7406 | } |
7407 | ||
de6eae1f YR |
7408 | static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, |
7409 | struct link_params *params) | |
7410 | { | |
7411 | struct bnx2x *bp = params->bp; | |
7412 | u8 gpio_port; | |
f2e0899f DK |
7413 | if (CHIP_IS_E2(bp)) |
7414 | gpio_port = BP_PATH(bp); | |
7415 | else | |
7416 | gpio_port = params->port; | |
de6eae1f YR |
7417 | DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", |
7418 | gpio_port); | |
7419 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee YR |
7420 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
7421 | gpio_port); | |
de6eae1f YR |
7422 | } |
7423 | ||
7424 | /******************************************************************/ | |
7425 | /* BCM8705 PHY SECTION */ | |
7426 | /******************************************************************/ | |
fcf5b650 YR |
7427 | static int bnx2x_8705_config_init(struct bnx2x_phy *phy, |
7428 | struct link_params *params, | |
7429 | struct link_vars *vars) | |
b7737c9b YR |
7430 | { |
7431 | struct bnx2x *bp = params->bp; | |
de6eae1f | 7432 | DP(NETIF_MSG_LINK, "init 8705\n"); |
b7737c9b YR |
7433 | /* Restore normal power mode*/ |
7434 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 7435 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
7436 | /* HW reset */ |
7437 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
7438 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
6d870c39 | 7439 | bnx2x_wait_reset_complete(bp, phy, params); |
b7737c9b | 7440 | |
de6eae1f YR |
7441 | bnx2x_cl45_write(bp, phy, |
7442 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); | |
7443 | bnx2x_cl45_write(bp, phy, | |
7444 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); | |
7445 | bnx2x_cl45_write(bp, phy, | |
7446 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); | |
7447 | bnx2x_cl45_write(bp, phy, | |
7448 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); | |
7449 | /* BCM8705 doesn't have microcode, hence the 0 */ | |
7450 | bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); | |
7451 | return 0; | |
7452 | } | |
4d295db0 | 7453 | |
de6eae1f YR |
7454 | static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, |
7455 | struct link_params *params, | |
7456 | struct link_vars *vars) | |
7457 | { | |
7458 | u8 link_up = 0; | |
7459 | u16 val1, rx_sd; | |
7460 | struct bnx2x *bp = params->bp; | |
7461 | DP(NETIF_MSG_LINK, "read status 8705\n"); | |
7462 | bnx2x_cl45_read(bp, phy, | |
7463 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
7464 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 7465 | |
de6eae1f YR |
7466 | bnx2x_cl45_read(bp, phy, |
7467 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
7468 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 7469 | |
de6eae1f YR |
7470 | bnx2x_cl45_read(bp, phy, |
7471 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); | |
c2c8b03e | 7472 | |
de6eae1f YR |
7473 | bnx2x_cl45_read(bp, phy, |
7474 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
7475 | bnx2x_cl45_read(bp, phy, | |
7476 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
c2c8b03e | 7477 | |
de6eae1f YR |
7478 | DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); |
7479 | link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); | |
7480 | if (link_up) { | |
7481 | vars->line_speed = SPEED_10000; | |
7482 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
62b29a5d | 7483 | } |
de6eae1f YR |
7484 | return link_up; |
7485 | } | |
d90d96ba | 7486 | |
de6eae1f YR |
7487 | /******************************************************************/ |
7488 | /* SFP+ module Section */ | |
7489 | /******************************************************************/ | |
85242eea YR |
7490 | static void bnx2x_set_disable_pmd_transmit(struct link_params *params, |
7491 | struct bnx2x_phy *phy, | |
7492 | u8 pmd_dis) | |
7493 | { | |
7494 | struct bnx2x *bp = params->bp; | |
8f73f0b9 | 7495 | /* Disable transmitter only for bootcodes which can enable it afterwards |
85242eea YR |
7496 | * (for D3 link) |
7497 | */ | |
7498 | if (pmd_dis) { | |
7499 | if (params->feature_config_flags & | |
7500 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) | |
7501 | DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); | |
7502 | else { | |
7503 | DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); | |
7504 | return; | |
7505 | } | |
7506 | } else | |
7507 | DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); | |
7508 | bnx2x_cl45_write(bp, phy, | |
7509 | MDIO_PMA_DEVAD, | |
7510 | MDIO_PMA_REG_TX_DISABLE, pmd_dis); | |
7511 | } | |
7512 | ||
a8db5b4c YR |
7513 | static u8 bnx2x_get_gpio_port(struct link_params *params) |
7514 | { | |
7515 | u8 gpio_port; | |
7516 | u32 swap_val, swap_override; | |
7517 | struct bnx2x *bp = params->bp; | |
7518 | if (CHIP_IS_E2(bp)) | |
7519 | gpio_port = BP_PATH(bp); | |
7520 | else | |
7521 | gpio_port = params->port; | |
7522 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
7523 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
7524 | return gpio_port ^ (swap_val && swap_override); | |
7525 | } | |
3c9ada22 YR |
7526 | |
7527 | static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, | |
7528 | struct bnx2x_phy *phy, | |
7529 | u8 tx_en) | |
de6eae1f YR |
7530 | { |
7531 | u16 val; | |
a8db5b4c YR |
7532 | u8 port = params->port; |
7533 | struct bnx2x *bp = params->bp; | |
7534 | u32 tx_en_mode; | |
d90d96ba | 7535 | |
de6eae1f | 7536 | /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ |
a8db5b4c YR |
7537 | tx_en_mode = REG_RD(bp, params->shmem_base + |
7538 | offsetof(struct shmem_region, | |
7539 | dev_info.port_hw_config[port].sfp_ctrl)) & | |
7540 | PORT_HW_CFG_TX_LASER_MASK; | |
7541 | DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " | |
7542 | "mode = %x\n", tx_en, port, tx_en_mode); | |
7543 | switch (tx_en_mode) { | |
7544 | case PORT_HW_CFG_TX_LASER_MDIO: | |
d90d96ba | 7545 | |
a8db5b4c YR |
7546 | bnx2x_cl45_read(bp, phy, |
7547 | MDIO_PMA_DEVAD, | |
7548 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
7549 | &val); | |
b7737c9b | 7550 | |
a8db5b4c YR |
7551 | if (tx_en) |
7552 | val &= ~(1<<15); | |
7553 | else | |
7554 | val |= (1<<15); | |
7555 | ||
7556 | bnx2x_cl45_write(bp, phy, | |
7557 | MDIO_PMA_DEVAD, | |
7558 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
7559 | val); | |
7560 | break; | |
7561 | case PORT_HW_CFG_TX_LASER_GPIO0: | |
7562 | case PORT_HW_CFG_TX_LASER_GPIO1: | |
7563 | case PORT_HW_CFG_TX_LASER_GPIO2: | |
7564 | case PORT_HW_CFG_TX_LASER_GPIO3: | |
7565 | { | |
7566 | u16 gpio_pin; | |
7567 | u8 gpio_port, gpio_mode; | |
7568 | if (tx_en) | |
7569 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; | |
7570 | else | |
7571 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; | |
7572 | ||
7573 | gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; | |
7574 | gpio_port = bnx2x_get_gpio_port(params); | |
7575 | bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); | |
7576 | break; | |
7577 | } | |
7578 | default: | |
7579 | DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); | |
7580 | break; | |
7581 | } | |
b7737c9b YR |
7582 | } |
7583 | ||
3c9ada22 YR |
7584 | static void bnx2x_sfp_set_transmitter(struct link_params *params, |
7585 | struct bnx2x_phy *phy, | |
7586 | u8 tx_en) | |
7587 | { | |
7588 | struct bnx2x *bp = params->bp; | |
7589 | DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); | |
7590 | if (CHIP_IS_E3(bp)) | |
7591 | bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); | |
7592 | else | |
7593 | bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); | |
7594 | } | |
7595 | ||
fcf5b650 YR |
7596 | static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7597 | struct link_params *params, | |
7598 | u16 addr, u8 byte_cnt, u8 *o_buf) | |
b7737c9b YR |
7599 | { |
7600 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
7601 | u16 val = 0; |
7602 | u16 i; | |
7603 | if (byte_cnt > 16) { | |
94f05b0f JP |
7604 | DP(NETIF_MSG_LINK, |
7605 | "Reading from eeprom is limited to 0xf\n"); | |
de6eae1f YR |
7606 | return -EINVAL; |
7607 | } | |
7608 | /* Set the read command byte count */ | |
62b29a5d | 7609 | bnx2x_cl45_write(bp, phy, |
de6eae1f | 7610 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, |
cd88ccee | 7611 | (byte_cnt | 0xa000)); |
ea4e040a | 7612 | |
de6eae1f YR |
7613 | /* Set the read command address */ |
7614 | bnx2x_cl45_write(bp, phy, | |
7615 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
cd88ccee | 7616 | addr); |
ea4e040a | 7617 | |
de6eae1f | 7618 | /* Activate read command */ |
62b29a5d | 7619 | bnx2x_cl45_write(bp, phy, |
de6eae1f | 7620 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, |
cd88ccee | 7621 | 0x2c0f); |
ea4e040a | 7622 | |
de6eae1f YR |
7623 | /* Wait up to 500us for command complete status */ |
7624 | for (i = 0; i < 100; i++) { | |
7625 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7626 | MDIO_PMA_DEVAD, |
7627 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7628 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7629 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
7630 | break; | |
7631 | udelay(5); | |
62b29a5d | 7632 | } |
62b29a5d | 7633 | |
de6eae1f YR |
7634 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
7635 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
7636 | DP(NETIF_MSG_LINK, | |
7637 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
7638 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
7639 | return -EINVAL; | |
62b29a5d | 7640 | } |
e10bc84d | 7641 | |
de6eae1f YR |
7642 | /* Read the buffer */ |
7643 | for (i = 0; i < byte_cnt; i++) { | |
62b29a5d | 7644 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
7645 | MDIO_PMA_DEVAD, |
7646 | MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); | |
de6eae1f | 7647 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); |
62b29a5d | 7648 | } |
6bbca910 | 7649 | |
de6eae1f YR |
7650 | for (i = 0; i < 100; i++) { |
7651 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7652 | MDIO_PMA_DEVAD, |
7653 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7654 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7655 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
6f38ad93 | 7656 | return 0; |
de6eae1f YR |
7657 | msleep(1); |
7658 | } | |
7659 | return -EINVAL; | |
b7737c9b | 7660 | } |
4d295db0 | 7661 | |
3c9ada22 YR |
7662 | static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7663 | struct link_params *params, | |
7664 | u16 addr, u8 byte_cnt, | |
7665 | u8 *o_buf) | |
7666 | { | |
7667 | int rc = 0; | |
7668 | u8 i, j = 0, cnt = 0; | |
7669 | u32 data_array[4]; | |
7670 | u16 addr32; | |
7671 | struct bnx2x *bp = params->bp; | |
3c9ada22 | 7672 | if (byte_cnt > 16) { |
94f05b0f JP |
7673 | DP(NETIF_MSG_LINK, |
7674 | "Reading from eeprom is limited to 16 bytes\n"); | |
3c9ada22 YR |
7675 | return -EINVAL; |
7676 | } | |
7677 | ||
7678 | /* 4 byte aligned address */ | |
7679 | addr32 = addr & (~0x3); | |
7680 | do { | |
7681 | rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt, | |
7682 | data_array); | |
7683 | } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); | |
7684 | ||
7685 | if (rc == 0) { | |
7686 | for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { | |
7687 | o_buf[j] = *((u8 *)data_array + i); | |
7688 | j++; | |
7689 | } | |
7690 | } | |
7691 | ||
7692 | return rc; | |
7693 | } | |
7694 | ||
fcf5b650 YR |
7695 | static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7696 | struct link_params *params, | |
7697 | u16 addr, u8 byte_cnt, u8 *o_buf) | |
b7737c9b | 7698 | { |
b7737c9b | 7699 | struct bnx2x *bp = params->bp; |
de6eae1f | 7700 | u16 val, i; |
ea4e040a | 7701 | |
de6eae1f | 7702 | if (byte_cnt > 16) { |
94f05b0f JP |
7703 | DP(NETIF_MSG_LINK, |
7704 | "Reading from eeprom is limited to 0xf\n"); | |
de6eae1f YR |
7705 | return -EINVAL; |
7706 | } | |
4d295db0 | 7707 | |
de6eae1f YR |
7708 | /* Need to read from 1.8000 to clear it */ |
7709 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7710 | MDIO_PMA_DEVAD, |
7711 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
7712 | &val); | |
4d295db0 | 7713 | |
de6eae1f | 7714 | /* Set the read command byte count */ |
62b29a5d | 7715 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7716 | MDIO_PMA_DEVAD, |
7717 | MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, | |
7718 | ((byte_cnt < 2) ? 2 : byte_cnt)); | |
ea4e040a | 7719 | |
de6eae1f | 7720 | /* Set the read command address */ |
62b29a5d | 7721 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7722 | MDIO_PMA_DEVAD, |
7723 | MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
7724 | addr); | |
de6eae1f | 7725 | /* Set the destination address */ |
62b29a5d | 7726 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7727 | MDIO_PMA_DEVAD, |
7728 | 0x8004, | |
7729 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); | |
62b29a5d | 7730 | |
de6eae1f | 7731 | /* Activate read command */ |
62b29a5d | 7732 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7733 | MDIO_PMA_DEVAD, |
7734 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
7735 | 0x8002); | |
8f73f0b9 | 7736 | /* Wait appropriate time for two-wire command to finish before |
2cf7acf9 YR |
7737 | * polling the status register |
7738 | */ | |
de6eae1f | 7739 | msleep(1); |
4d295db0 | 7740 | |
de6eae1f YR |
7741 | /* Wait up to 500us for command complete status */ |
7742 | for (i = 0; i < 100; i++) { | |
62b29a5d | 7743 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
7744 | MDIO_PMA_DEVAD, |
7745 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7746 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7747 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
7748 | break; | |
7749 | udelay(5); | |
62b29a5d | 7750 | } |
4d295db0 | 7751 | |
de6eae1f YR |
7752 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
7753 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
7754 | DP(NETIF_MSG_LINK, | |
7755 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
7756 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
65a001ba | 7757 | return -EFAULT; |
de6eae1f | 7758 | } |
62b29a5d | 7759 | |
de6eae1f YR |
7760 | /* Read the buffer */ |
7761 | for (i = 0; i < byte_cnt; i++) { | |
7762 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7763 | MDIO_PMA_DEVAD, |
7764 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); | |
de6eae1f YR |
7765 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); |
7766 | } | |
4d295db0 | 7767 | |
de6eae1f YR |
7768 | for (i = 0; i < 100; i++) { |
7769 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7770 | MDIO_PMA_DEVAD, |
7771 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7772 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7773 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
6f38ad93 | 7774 | return 0; |
de6eae1f | 7775 | msleep(1); |
62b29a5d YR |
7776 | } |
7777 | ||
de6eae1f | 7778 | return -EINVAL; |
b7737c9b YR |
7779 | } |
7780 | ||
fcf5b650 YR |
7781 | int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7782 | struct link_params *params, u16 addr, | |
7783 | u8 byte_cnt, u8 *o_buf) | |
b7737c9b | 7784 | { |
fcf5b650 | 7785 | int rc = -EINVAL; |
e4d78f12 YR |
7786 | switch (phy->type) { |
7787 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
7788 | rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr, | |
7789 | byte_cnt, o_buf); | |
7790 | break; | |
7791 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
7792 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
7793 | rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr, | |
7794 | byte_cnt, o_buf); | |
7795 | break; | |
3c9ada22 YR |
7796 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
7797 | rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr, | |
7798 | byte_cnt, o_buf); | |
7799 | break; | |
e4d78f12 YR |
7800 | } |
7801 | return rc; | |
b7737c9b YR |
7802 | } |
7803 | ||
fcf5b650 YR |
7804 | static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, |
7805 | struct link_params *params, | |
7806 | u16 *edc_mode) | |
b7737c9b YR |
7807 | { |
7808 | struct bnx2x *bp = params->bp; | |
1ac9e428 | 7809 | u32 sync_offset = 0, phy_idx, media_types; |
de6eae1f YR |
7810 | u8 val, check_limiting_mode = 0; |
7811 | *edc_mode = EDC_MODE_LIMITING; | |
62b29a5d | 7812 | |
1ac9e428 | 7813 | phy->media_type = ETH_PHY_UNSPECIFIED; |
de6eae1f YR |
7814 | /* First check for copper cable */ |
7815 | if (bnx2x_read_sfp_module_eeprom(phy, | |
7816 | params, | |
7817 | SFP_EEPROM_CON_TYPE_ADDR, | |
7818 | 1, | |
7819 | &val) != 0) { | |
7820 | DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); | |
7821 | return -EINVAL; | |
7822 | } | |
a1e4be39 | 7823 | |
de6eae1f YR |
7824 | switch (val) { |
7825 | case SFP_EEPROM_CON_TYPE_VAL_COPPER: | |
7826 | { | |
7827 | u8 copper_module_type; | |
1ac9e428 | 7828 | phy->media_type = ETH_PHY_DA_TWINAX; |
8f73f0b9 | 7829 | /* Check if its active cable (includes SFP+ module) |
2cf7acf9 YR |
7830 | * of passive cable |
7831 | */ | |
de6eae1f YR |
7832 | if (bnx2x_read_sfp_module_eeprom(phy, |
7833 | params, | |
7834 | SFP_EEPROM_FC_TX_TECH_ADDR, | |
7835 | 1, | |
9045f6b4 | 7836 | &copper_module_type) != 0) { |
de6eae1f YR |
7837 | DP(NETIF_MSG_LINK, |
7838 | "Failed to read copper-cable-type" | |
7839 | " from SFP+ EEPROM\n"); | |
7840 | return -EINVAL; | |
7841 | } | |
4f60dab1 | 7842 | |
de6eae1f YR |
7843 | if (copper_module_type & |
7844 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { | |
7845 | DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); | |
7846 | check_limiting_mode = 1; | |
7847 | } else if (copper_module_type & | |
7848 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { | |
94f05b0f JP |
7849 | DP(NETIF_MSG_LINK, |
7850 | "Passive Copper cable detected\n"); | |
de6eae1f YR |
7851 | *edc_mode = |
7852 | EDC_MODE_PASSIVE_DAC; | |
7853 | } else { | |
94f05b0f JP |
7854 | DP(NETIF_MSG_LINK, |
7855 | "Unknown copper-cable-type 0x%x !!!\n", | |
7856 | copper_module_type); | |
de6eae1f YR |
7857 | return -EINVAL; |
7858 | } | |
7859 | break; | |
62b29a5d | 7860 | } |
de6eae1f | 7861 | case SFP_EEPROM_CON_TYPE_VAL_LC: |
1ac9e428 | 7862 | phy->media_type = ETH_PHY_SFP_FIBER; |
de6eae1f YR |
7863 | DP(NETIF_MSG_LINK, "Optic module detected\n"); |
7864 | check_limiting_mode = 1; | |
7865 | break; | |
7866 | default: | |
7867 | DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", | |
7868 | val); | |
7869 | return -EINVAL; | |
62b29a5d | 7870 | } |
1ac9e428 YR |
7871 | sync_offset = params->shmem_base + |
7872 | offsetof(struct shmem_region, | |
7873 | dev_info.port_hw_config[params->port].media_type); | |
7874 | media_types = REG_RD(bp, sync_offset); | |
7875 | /* Update media type for non-PMF sync */ | |
7876 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { | |
7877 | if (&(params->phy[phy_idx]) == phy) { | |
7878 | media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << | |
7879 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); | |
7880 | media_types |= ((phy->media_type & | |
7881 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << | |
7882 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); | |
7883 | break; | |
7884 | } | |
7885 | } | |
7886 | REG_WR(bp, sync_offset, media_types); | |
de6eae1f YR |
7887 | if (check_limiting_mode) { |
7888 | u8 options[SFP_EEPROM_OPTIONS_SIZE]; | |
7889 | if (bnx2x_read_sfp_module_eeprom(phy, | |
7890 | params, | |
7891 | SFP_EEPROM_OPTIONS_ADDR, | |
7892 | SFP_EEPROM_OPTIONS_SIZE, | |
7893 | options) != 0) { | |
94f05b0f JP |
7894 | DP(NETIF_MSG_LINK, |
7895 | "Failed to read Option field from module EEPROM\n"); | |
de6eae1f YR |
7896 | return -EINVAL; |
7897 | } | |
7898 | if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) | |
7899 | *edc_mode = EDC_MODE_LINEAR; | |
7900 | else | |
7901 | *edc_mode = EDC_MODE_LIMITING; | |
62b29a5d | 7902 | } |
de6eae1f | 7903 | DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); |
62b29a5d | 7904 | return 0; |
b7737c9b | 7905 | } |
8f73f0b9 | 7906 | /* This function read the relevant field from the module (SFP+), and verify it |
2cf7acf9 YR |
7907 | * is compliant with this board |
7908 | */ | |
fcf5b650 YR |
7909 | static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, |
7910 | struct link_params *params) | |
b7737c9b YR |
7911 | { |
7912 | struct bnx2x *bp = params->bp; | |
a22f0788 YR |
7913 | u32 val, cmd; |
7914 | u32 fw_resp, fw_cmd_param; | |
de6eae1f YR |
7915 | char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; |
7916 | char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; | |
a22f0788 | 7917 | phy->flags &= ~FLAGS_SFP_NOT_APPROVED; |
de6eae1f YR |
7918 | val = REG_RD(bp, params->shmem_base + |
7919 | offsetof(struct shmem_region, dev_info. | |
7920 | port_feature_config[params->port].config)); | |
7921 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
7922 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { | |
7923 | DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); | |
7924 | return 0; | |
7925 | } | |
ea4e040a | 7926 | |
a22f0788 YR |
7927 | if (params->feature_config_flags & |
7928 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { | |
7929 | /* Use specific phy request */ | |
7930 | cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; | |
7931 | } else if (params->feature_config_flags & | |
7932 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { | |
7933 | /* Use first phy request only in case of non-dual media*/ | |
7934 | if (DUAL_MEDIA(params)) { | |
94f05b0f JP |
7935 | DP(NETIF_MSG_LINK, |
7936 | "FW does not support OPT MDL verification\n"); | |
a22f0788 YR |
7937 | return -EINVAL; |
7938 | } | |
7939 | cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; | |
7940 | } else { | |
7941 | /* No support in OPT MDL detection */ | |
94f05b0f JP |
7942 | DP(NETIF_MSG_LINK, |
7943 | "FW does not support OPT MDL verification\n"); | |
de6eae1f YR |
7944 | return -EINVAL; |
7945 | } | |
523224a3 | 7946 | |
a22f0788 YR |
7947 | fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); |
7948 | fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); | |
de6eae1f YR |
7949 | if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { |
7950 | DP(NETIF_MSG_LINK, "Approved module\n"); | |
7951 | return 0; | |
7952 | } | |
b7737c9b | 7953 | |
de6eae1f YR |
7954 | /* format the warning message */ |
7955 | if (bnx2x_read_sfp_module_eeprom(phy, | |
7956 | params, | |
cd88ccee YR |
7957 | SFP_EEPROM_VENDOR_NAME_ADDR, |
7958 | SFP_EEPROM_VENDOR_NAME_SIZE, | |
7959 | (u8 *)vendor_name)) | |
de6eae1f YR |
7960 | vendor_name[0] = '\0'; |
7961 | else | |
7962 | vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; | |
7963 | if (bnx2x_read_sfp_module_eeprom(phy, | |
7964 | params, | |
cd88ccee YR |
7965 | SFP_EEPROM_PART_NO_ADDR, |
7966 | SFP_EEPROM_PART_NO_SIZE, | |
7967 | (u8 *)vendor_pn)) | |
de6eae1f YR |
7968 | vendor_pn[0] = '\0'; |
7969 | else | |
7970 | vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; | |
7971 | ||
6d870c39 YR |
7972 | netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," |
7973 | " Port %d from %s part number %s\n", | |
7974 | params->port, vendor_name, vendor_pn); | |
59a2e53b YR |
7975 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != |
7976 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) | |
7977 | phy->flags |= FLAGS_SFP_NOT_APPROVED; | |
de6eae1f | 7978 | return -EINVAL; |
b7737c9b | 7979 | } |
7aa0711f | 7980 | |
fcf5b650 YR |
7981 | static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, |
7982 | struct link_params *params) | |
7aa0711f | 7983 | |
4d295db0 | 7984 | { |
de6eae1f | 7985 | u8 val; |
4d295db0 | 7986 | struct bnx2x *bp = params->bp; |
de6eae1f | 7987 | u16 timeout; |
8f73f0b9 | 7988 | /* Initialization time after hot-plug may take up to 300ms for |
2cf7acf9 YR |
7989 | * some phys type ( e.g. JDSU ) |
7990 | */ | |
7991 | ||
de6eae1f YR |
7992 | for (timeout = 0; timeout < 60; timeout++) { |
7993 | if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val) | |
7994 | == 0) { | |
94f05b0f JP |
7995 | DP(NETIF_MSG_LINK, |
7996 | "SFP+ module initialization took %d ms\n", | |
7997 | timeout * 5); | |
de6eae1f YR |
7998 | return 0; |
7999 | } | |
8000 | msleep(5); | |
8001 | } | |
8002 | return -EINVAL; | |
8003 | } | |
4d295db0 | 8004 | |
de6eae1f YR |
8005 | static void bnx2x_8727_power_module(struct bnx2x *bp, |
8006 | struct bnx2x_phy *phy, | |
8007 | u8 is_power_up) { | |
8008 | /* Make sure GPIOs are not using for LED mode */ | |
8009 | u16 val; | |
8f73f0b9 | 8010 | /* In the GPIO register, bit 4 is use to determine if the GPIOs are |
de6eae1f YR |
8011 | * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for |
8012 | * output | |
3c9ada22 YR |
8013 | * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 |
8014 | * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 | |
de6eae1f YR |
8015 | * where the 1st bit is the over-current(only input), and 2nd bit is |
8016 | * for power( only output ) | |
2cf7acf9 | 8017 | * |
de6eae1f YR |
8018 | * In case of NOC feature is disabled and power is up, set GPIO control |
8019 | * as input to enable listening of over-current indication | |
8020 | */ | |
8021 | if (phy->flags & FLAGS_NOC) | |
8022 | return; | |
27d02432 | 8023 | if (is_power_up) |
de6eae1f YR |
8024 | val = (1<<4); |
8025 | else | |
8f73f0b9 | 8026 | /* Set GPIO control to OUTPUT, and set the power bit |
de6eae1f YR |
8027 | * to according to the is_power_up |
8028 | */ | |
27d02432 | 8029 | val = (1<<1); |
4d295db0 | 8030 | |
de6eae1f YR |
8031 | bnx2x_cl45_write(bp, phy, |
8032 | MDIO_PMA_DEVAD, | |
8033 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
8034 | val); | |
8035 | } | |
4d295db0 | 8036 | |
fcf5b650 YR |
8037 | static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, |
8038 | struct bnx2x_phy *phy, | |
8039 | u16 edc_mode) | |
de6eae1f YR |
8040 | { |
8041 | u16 cur_limiting_mode; | |
4d295db0 | 8042 | |
de6eae1f | 8043 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8044 | MDIO_PMA_DEVAD, |
8045 | MDIO_PMA_REG_ROM_VER2, | |
8046 | &cur_limiting_mode); | |
de6eae1f YR |
8047 | DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", |
8048 | cur_limiting_mode); | |
8049 | ||
8050 | if (edc_mode == EDC_MODE_LIMITING) { | |
cd88ccee | 8051 | DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); |
e10bc84d | 8052 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 8053 | MDIO_PMA_DEVAD, |
de6eae1f YR |
8054 | MDIO_PMA_REG_ROM_VER2, |
8055 | EDC_MODE_LIMITING); | |
8056 | } else { /* LRM mode ( default )*/ | |
4d295db0 | 8057 | |
de6eae1f | 8058 | DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); |
4d295db0 | 8059 | |
8f73f0b9 | 8060 | /* Changing to LRM mode takes quite few seconds. So do it only |
2cf7acf9 YR |
8061 | * if current mode is limiting (default is LRM) |
8062 | */ | |
de6eae1f YR |
8063 | if (cur_limiting_mode != EDC_MODE_LIMITING) |
8064 | return 0; | |
4d295db0 | 8065 | |
de6eae1f | 8066 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8067 | MDIO_PMA_DEVAD, |
8068 | MDIO_PMA_REG_LRM_MODE, | |
8069 | 0); | |
de6eae1f | 8070 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8071 | MDIO_PMA_DEVAD, |
8072 | MDIO_PMA_REG_ROM_VER2, | |
8073 | 0x128); | |
de6eae1f | 8074 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8075 | MDIO_PMA_DEVAD, |
8076 | MDIO_PMA_REG_MISC_CTRL0, | |
8077 | 0x4008); | |
de6eae1f | 8078 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8079 | MDIO_PMA_DEVAD, |
8080 | MDIO_PMA_REG_LRM_MODE, | |
8081 | 0xaaaa); | |
4d295db0 | 8082 | } |
de6eae1f | 8083 | return 0; |
4d295db0 EG |
8084 | } |
8085 | ||
fcf5b650 YR |
8086 | static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, |
8087 | struct bnx2x_phy *phy, | |
8088 | u16 edc_mode) | |
ea4e040a | 8089 | { |
de6eae1f YR |
8090 | u16 phy_identifier; |
8091 | u16 rom_ver2_val; | |
62b29a5d | 8092 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8093 | MDIO_PMA_DEVAD, |
8094 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8095 | &phy_identifier); | |
ea4e040a | 8096 | |
de6eae1f | 8097 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8098 | MDIO_PMA_DEVAD, |
8099 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8100 | (phy_identifier & ~(1<<9))); | |
ea4e040a | 8101 | |
62b29a5d | 8102 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8103 | MDIO_PMA_DEVAD, |
8104 | MDIO_PMA_REG_ROM_VER2, | |
8105 | &rom_ver2_val); | |
de6eae1f YR |
8106 | /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ |
8107 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
8108 | MDIO_PMA_DEVAD, |
8109 | MDIO_PMA_REG_ROM_VER2, | |
8110 | (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); | |
4d295db0 | 8111 | |
de6eae1f | 8112 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8113 | MDIO_PMA_DEVAD, |
8114 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8115 | (phy_identifier | (1<<9))); | |
4d295db0 | 8116 | |
de6eae1f | 8117 | return 0; |
b7737c9b | 8118 | } |
ea4e040a | 8119 | |
a22f0788 YR |
8120 | static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, |
8121 | struct link_params *params, | |
8122 | u32 action) | |
8123 | { | |
8124 | struct bnx2x *bp = params->bp; | |
8125 | ||
8126 | switch (action) { | |
8127 | case DISABLE_TX: | |
a8db5b4c | 8128 | bnx2x_sfp_set_transmitter(params, phy, 0); |
a22f0788 YR |
8129 | break; |
8130 | case ENABLE_TX: | |
8131 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) | |
a8db5b4c | 8132 | bnx2x_sfp_set_transmitter(params, phy, 1); |
a22f0788 YR |
8133 | break; |
8134 | default: | |
8135 | DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", | |
8136 | action); | |
8137 | return; | |
8138 | } | |
8139 | } | |
8140 | ||
3c9ada22 | 8141 | static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, |
a8db5b4c YR |
8142 | u8 gpio_mode) |
8143 | { | |
8144 | struct bnx2x *bp = params->bp; | |
8145 | ||
8146 | u32 fault_led_gpio = REG_RD(bp, params->shmem_base + | |
8147 | offsetof(struct shmem_region, | |
8148 | dev_info.port_hw_config[params->port].sfp_ctrl)) & | |
8149 | PORT_HW_CFG_FAULT_MODULE_LED_MASK; | |
8150 | switch (fault_led_gpio) { | |
8151 | case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: | |
8152 | return; | |
8153 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: | |
8154 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: | |
8155 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: | |
8156 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: | |
8157 | { | |
8158 | u8 gpio_port = bnx2x_get_gpio_port(params); | |
8159 | u16 gpio_pin = fault_led_gpio - | |
8160 | PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; | |
8161 | DP(NETIF_MSG_LINK, "Set fault module-detected led " | |
8162 | "pin %x port %x mode %x\n", | |
8163 | gpio_pin, gpio_port, gpio_mode); | |
8164 | bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); | |
8165 | } | |
8166 | break; | |
8167 | default: | |
8168 | DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", | |
8169 | fault_led_gpio); | |
8170 | } | |
8171 | } | |
8172 | ||
3c9ada22 YR |
8173 | static void bnx2x_set_e3_module_fault_led(struct link_params *params, |
8174 | u8 gpio_mode) | |
8175 | { | |
8176 | u32 pin_cfg; | |
8177 | u8 port = params->port; | |
8178 | struct bnx2x *bp = params->bp; | |
8179 | pin_cfg = (REG_RD(bp, params->shmem_base + | |
8180 | offsetof(struct shmem_region, | |
8181 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
8182 | PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> | |
8183 | PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; | |
8184 | DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", | |
8185 | gpio_mode, pin_cfg); | |
8186 | bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); | |
8187 | } | |
8188 | ||
8189 | static void bnx2x_set_sfp_module_fault_led(struct link_params *params, | |
8190 | u8 gpio_mode) | |
8191 | { | |
8192 | struct bnx2x *bp = params->bp; | |
8193 | DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); | |
8194 | if (CHIP_IS_E3(bp)) { | |
8f73f0b9 | 8195 | /* Low ==> if SFP+ module is supported otherwise |
3c9ada22 YR |
8196 | * High ==> if SFP+ module is not on the approved vendor list |
8197 | */ | |
8198 | bnx2x_set_e3_module_fault_led(params, gpio_mode); | |
8199 | } else | |
8200 | bnx2x_set_e1e2_module_fault_led(params, gpio_mode); | |
8201 | } | |
8202 | ||
8203 | static void bnx2x_warpcore_power_module(struct link_params *params, | |
8204 | struct bnx2x_phy *phy, | |
8205 | u8 power) | |
8206 | { | |
8207 | u32 pin_cfg; | |
8208 | struct bnx2x *bp = params->bp; | |
8209 | ||
8210 | pin_cfg = (REG_RD(bp, params->shmem_base + | |
8211 | offsetof(struct shmem_region, | |
8212 | dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & | |
8213 | PORT_HW_CFG_E3_PWR_DIS_MASK) >> | |
8214 | PORT_HW_CFG_E3_PWR_DIS_SHIFT; | |
985848f8 YR |
8215 | |
8216 | if (pin_cfg == PIN_CFG_NA) | |
8217 | return; | |
3c9ada22 YR |
8218 | DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", |
8219 | power, pin_cfg); | |
8f73f0b9 | 8220 | /* Low ==> corresponding SFP+ module is powered |
3c9ada22 YR |
8221 | * high ==> the SFP+ module is powered down |
8222 | */ | |
8223 | bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); | |
8224 | } | |
8225 | ||
985848f8 YR |
8226 | static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, |
8227 | struct link_params *params) | |
8228 | { | |
b76070b4 | 8229 | struct bnx2x *bp = params->bp; |
985848f8 | 8230 | bnx2x_warpcore_power_module(params, phy, 0); |
b76070b4 YR |
8231 | /* Put Warpcore in low power mode */ |
8232 | REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); | |
8233 | ||
8234 | /* Put LCPLL in low power mode */ | |
8235 | REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); | |
8236 | REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); | |
8237 | REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); | |
985848f8 YR |
8238 | } |
8239 | ||
e4d78f12 YR |
8240 | static void bnx2x_power_sfp_module(struct link_params *params, |
8241 | struct bnx2x_phy *phy, | |
8242 | u8 power) | |
8243 | { | |
8244 | struct bnx2x *bp = params->bp; | |
8245 | DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); | |
8246 | ||
8247 | switch (phy->type) { | |
8248 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
8249 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
8250 | bnx2x_8727_power_module(params->bp, phy, power); | |
8251 | break; | |
3c9ada22 YR |
8252 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
8253 | bnx2x_warpcore_power_module(params, phy, power); | |
8254 | break; | |
8255 | default: | |
8256 | break; | |
8257 | } | |
8258 | } | |
8259 | static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, | |
8260 | struct bnx2x_phy *phy, | |
8261 | u16 edc_mode) | |
8262 | { | |
8263 | u16 val = 0; | |
8264 | u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; | |
8265 | struct bnx2x *bp = params->bp; | |
8266 | ||
8267 | u8 lane = bnx2x_get_warpcore_lane(phy, params); | |
8268 | /* This is a global register which controls all lanes */ | |
8269 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
8270 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); | |
8271 | val &= ~(0xf << (lane << 2)); | |
8272 | ||
8273 | switch (edc_mode) { | |
8274 | case EDC_MODE_LINEAR: | |
8275 | case EDC_MODE_LIMITING: | |
8276 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; | |
8277 | break; | |
8278 | case EDC_MODE_PASSIVE_DAC: | |
8279 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; | |
8280 | break; | |
e4d78f12 YR |
8281 | default: |
8282 | break; | |
8283 | } | |
3c9ada22 YR |
8284 | |
8285 | val |= (mode << (lane << 2)); | |
8286 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
8287 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); | |
8288 | /* A must read */ | |
8289 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
8290 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); | |
8291 | ||
19af03a3 YR |
8292 | /* Restart microcode to re-read the new mode */ |
8293 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
8294 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
3c9ada22 | 8295 | |
e4d78f12 YR |
8296 | } |
8297 | ||
8298 | static void bnx2x_set_limiting_mode(struct link_params *params, | |
8299 | struct bnx2x_phy *phy, | |
8300 | u16 edc_mode) | |
8301 | { | |
8302 | switch (phy->type) { | |
8303 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
8304 | bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); | |
8305 | break; | |
8306 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
8307 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
8308 | bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); | |
8309 | break; | |
3c9ada22 YR |
8310 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
8311 | bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); | |
8312 | break; | |
e4d78f12 YR |
8313 | } |
8314 | } | |
8315 | ||
fcf5b650 YR |
8316 | int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, |
8317 | struct link_params *params) | |
b7737c9b | 8318 | { |
b7737c9b | 8319 | struct bnx2x *bp = params->bp; |
de6eae1f | 8320 | u16 edc_mode; |
fcf5b650 | 8321 | int rc = 0; |
ea4e040a | 8322 | |
de6eae1f YR |
8323 | u32 val = REG_RD(bp, params->shmem_base + |
8324 | offsetof(struct shmem_region, dev_info. | |
8325 | port_feature_config[params->port].config)); | |
62b29a5d | 8326 | |
de6eae1f YR |
8327 | DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", |
8328 | params->port); | |
e4d78f12 YR |
8329 | /* Power up module */ |
8330 | bnx2x_power_sfp_module(params, phy, 1); | |
de6eae1f YR |
8331 | if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { |
8332 | DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); | |
8333 | return -EINVAL; | |
cd88ccee | 8334 | } else if (bnx2x_verify_sfp_module(phy, params) != 0) { |
de6eae1f YR |
8335 | /* check SFP+ module compatibility */ |
8336 | DP(NETIF_MSG_LINK, "Module verification failed!!\n"); | |
8337 | rc = -EINVAL; | |
8338 | /* Turn on fault module-detected led */ | |
a8db5b4c YR |
8339 | bnx2x_set_sfp_module_fault_led(params, |
8340 | MISC_REGISTERS_GPIO_HIGH); | |
8341 | ||
e4d78f12 YR |
8342 | /* Check if need to power down the SFP+ module */ |
8343 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8344 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { | |
de6eae1f | 8345 | DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); |
e4d78f12 | 8346 | bnx2x_power_sfp_module(params, phy, 0); |
de6eae1f YR |
8347 | return rc; |
8348 | } | |
8349 | } else { | |
8350 | /* Turn off fault module-detected led */ | |
a8db5b4c | 8351 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); |
62b29a5d | 8352 | } |
b7737c9b | 8353 | |
8f73f0b9 | 8354 | /* Check and set limiting mode / LRM mode on 8726. On 8727 it |
2cf7acf9 YR |
8355 | * is done automatically |
8356 | */ | |
e4d78f12 YR |
8357 | bnx2x_set_limiting_mode(params, phy, edc_mode); |
8358 | ||
8f73f0b9 | 8359 | /* Enable transmit for this module if the module is approved, or |
de6eae1f YR |
8360 | * if unapproved modules should also enable the Tx laser |
8361 | */ | |
8362 | if (rc == 0 || | |
8363 | (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != | |
8364 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
a8db5b4c | 8365 | bnx2x_sfp_set_transmitter(params, phy, 1); |
de6eae1f | 8366 | else |
a8db5b4c | 8367 | bnx2x_sfp_set_transmitter(params, phy, 0); |
b7737c9b | 8368 | |
de6eae1f YR |
8369 | return rc; |
8370 | } | |
8371 | ||
8372 | void bnx2x_handle_module_detect_int(struct link_params *params) | |
b7737c9b YR |
8373 | { |
8374 | struct bnx2x *bp = params->bp; | |
3c9ada22 | 8375 | struct bnx2x_phy *phy; |
de6eae1f | 8376 | u32 gpio_val; |
3c9ada22 YR |
8377 | u8 gpio_num, gpio_port; |
8378 | if (CHIP_IS_E3(bp)) | |
8379 | phy = ¶ms->phy[INT_PHY]; | |
8380 | else | |
8381 | phy = ¶ms->phy[EXT_PHY1]; | |
8382 | ||
8383 | if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, | |
8384 | params->port, &gpio_num, &gpio_port) == | |
8385 | -EINVAL) { | |
8386 | DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); | |
8387 | return; | |
8388 | } | |
4d295db0 | 8389 | |
de6eae1f | 8390 | /* Set valid module led off */ |
a8db5b4c | 8391 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); |
4d295db0 | 8392 | |
2cf7acf9 | 8393 | /* Get current gpio val reflecting module plugged in / out*/ |
3c9ada22 | 8394 | gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); |
62b29a5d | 8395 | |
de6eae1f YR |
8396 | /* Call the handling function in case module is detected */ |
8397 | if (gpio_val == 0) { | |
e4d78f12 | 8398 | bnx2x_power_sfp_module(params, phy, 1); |
3c9ada22 | 8399 | bnx2x_set_gpio_int(bp, gpio_num, |
de6eae1f | 8400 | MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, |
3c9ada22 | 8401 | gpio_port); |
de6eae1f YR |
8402 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) |
8403 | bnx2x_sfp_module_detection(phy, params); | |
8404 | else | |
8405 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); | |
8406 | } else { | |
8407 | u32 val = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
8408 | offsetof(struct shmem_region, dev_info. |
8409 | port_feature_config[params->port]. | |
8410 | config)); | |
3c9ada22 | 8411 | bnx2x_set_gpio_int(bp, gpio_num, |
de6eae1f | 8412 | MISC_REGISTERS_GPIO_INT_OUTPUT_SET, |
3c9ada22 | 8413 | gpio_port); |
8f73f0b9 | 8414 | /* Module was plugged out. |
2cf7acf9 YR |
8415 | * Disable transmit for this module |
8416 | */ | |
1ac9e428 | 8417 | phy->media_type = ETH_PHY_NOT_PRESENT; |
de6f3377 YR |
8418 | if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
8419 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) || | |
8420 | CHIP_IS_E3(bp)) | |
a8db5b4c | 8421 | bnx2x_sfp_set_transmitter(params, phy, 0); |
62b29a5d | 8422 | } |
de6eae1f | 8423 | } |
62b29a5d | 8424 | |
c688fe2f YR |
8425 | /******************************************************************/ |
8426 | /* Used by 8706 and 8727 */ | |
8427 | /******************************************************************/ | |
8428 | static void bnx2x_sfp_mask_fault(struct bnx2x *bp, | |
8429 | struct bnx2x_phy *phy, | |
8430 | u16 alarm_status_offset, | |
8431 | u16 alarm_ctrl_offset) | |
8432 | { | |
8433 | u16 alarm_status, val; | |
8434 | bnx2x_cl45_read(bp, phy, | |
8435 | MDIO_PMA_DEVAD, alarm_status_offset, | |
8436 | &alarm_status); | |
8437 | bnx2x_cl45_read(bp, phy, | |
8438 | MDIO_PMA_DEVAD, alarm_status_offset, | |
8439 | &alarm_status); | |
8440 | /* Mask or enable the fault event. */ | |
8441 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); | |
8442 | if (alarm_status & (1<<0)) | |
8443 | val &= ~(1<<0); | |
8444 | else | |
8445 | val |= (1<<0); | |
8446 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); | |
8447 | } | |
de6eae1f YR |
8448 | /******************************************************************/ |
8449 | /* common BCM8706/BCM8726 PHY SECTION */ | |
8450 | /******************************************************************/ | |
8451 | static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, | |
8452 | struct link_params *params, | |
8453 | struct link_vars *vars) | |
8454 | { | |
8455 | u8 link_up = 0; | |
8456 | u16 val1, val2, rx_sd, pcs_status; | |
8457 | struct bnx2x *bp = params->bp; | |
8458 | DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); | |
8459 | /* Clear RX Alarm*/ | |
62b29a5d | 8460 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8461 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); |
c688fe2f | 8462 | |
60d2fe03 YR |
8463 | bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, |
8464 | MDIO_PMA_LASI_TXCTRL); | |
c688fe2f | 8465 | |
de6eae1f YR |
8466 | /* clear LASI indication*/ |
8467 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 8468 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f | 8469 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8470 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); |
de6eae1f | 8471 | DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); |
62b29a5d YR |
8472 | |
8473 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
8474 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); |
8475 | bnx2x_cl45_read(bp, phy, | |
8476 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); | |
8477 | bnx2x_cl45_read(bp, phy, | |
8478 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
8479 | bnx2x_cl45_read(bp, phy, | |
8480 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
62b29a5d | 8481 | |
de6eae1f YR |
8482 | DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" |
8483 | " link_status 0x%x\n", rx_sd, pcs_status, val2); | |
8f73f0b9 | 8484 | /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status |
2cf7acf9 | 8485 | * are set, or if the autoneg bit 1 is set |
de6eae1f YR |
8486 | */ |
8487 | link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); | |
8488 | if (link_up) { | |
8489 | if (val2 & (1<<1)) | |
8490 | vars->line_speed = SPEED_1000; | |
8491 | else | |
8492 | vars->line_speed = SPEED_10000; | |
62b29a5d | 8493 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
791f18c0 | 8494 | vars->duplex = DUPLEX_FULL; |
de6eae1f | 8495 | } |
c688fe2f YR |
8496 | |
8497 | /* Capture 10G link fault. Read twice to clear stale value. */ | |
8498 | if (vars->line_speed == SPEED_10000) { | |
8499 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 8500 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f | 8501 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
60d2fe03 | 8502 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
8503 | if (val1 & (1<<0)) |
8504 | vars->fault_detected = 1; | |
8505 | } | |
8506 | ||
62b29a5d | 8507 | return link_up; |
b7737c9b | 8508 | } |
62b29a5d | 8509 | |
de6eae1f YR |
8510 | /******************************************************************/ |
8511 | /* BCM8706 PHY SECTION */ | |
8512 | /******************************************************************/ | |
8513 | static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, | |
b7737c9b YR |
8514 | struct link_params *params, |
8515 | struct link_vars *vars) | |
8516 | { | |
a8db5b4c YR |
8517 | u32 tx_en_mode; |
8518 | u16 cnt, val, tmp1; | |
b7737c9b | 8519 | struct bnx2x *bp = params->bp; |
3deb8167 | 8520 | |
de6eae1f | 8521 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee | 8522 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
8523 | /* HW reset */ |
8524 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
8525 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
6d870c39 | 8526 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 8527 | |
de6eae1f YR |
8528 | /* Wait until fw is loaded */ |
8529 | for (cnt = 0; cnt < 100; cnt++) { | |
8530 | bnx2x_cl45_read(bp, phy, | |
8531 | MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); | |
8532 | if (val) | |
8533 | break; | |
8534 | msleep(10); | |
8535 | } | |
8536 | DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); | |
8537 | if ((params->feature_config_flags & | |
8538 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
8539 | u8 i; | |
8540 | u16 reg; | |
8541 | for (i = 0; i < 4; i++) { | |
8542 | reg = MDIO_XS_8706_REG_BANK_RX0 + | |
8543 | i*(MDIO_XS_8706_REG_BANK_RX1 - | |
8544 | MDIO_XS_8706_REG_BANK_RX0); | |
8545 | bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); | |
8546 | /* Clear first 3 bits of the control */ | |
8547 | val &= ~0x7; | |
8548 | /* Set control bits according to configuration */ | |
8549 | val |= (phy->rx_preemphasis[i] & 0x7); | |
8550 | DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" | |
8551 | " reg 0x%x <-- val 0x%x\n", reg, val); | |
8552 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); | |
8553 | } | |
8554 | } | |
8555 | /* Force speed */ | |
8556 | if (phy->req_line_speed == SPEED_10000) { | |
8557 | DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); | |
ea4e040a | 8558 | |
de6eae1f YR |
8559 | bnx2x_cl45_write(bp, phy, |
8560 | MDIO_PMA_DEVAD, | |
8561 | MDIO_PMA_REG_DIGITAL_CTRL, 0x400); | |
8562 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8563 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, |
c688fe2f YR |
8564 | 0); |
8565 | /* Arm LASI for link and Tx fault. */ | |
8566 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8567 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); |
de6eae1f | 8568 | } else { |
25985edc | 8569 | /* Force 1Gbps using autoneg with 1G advertisement */ |
6bbca910 | 8570 | |
de6eae1f YR |
8571 | /* Allow CL37 through CL73 */ |
8572 | DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); | |
8573 | bnx2x_cl45_write(bp, phy, | |
8574 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
6bbca910 | 8575 | |
25985edc | 8576 | /* Enable Full-Duplex advertisement on CL37 */ |
de6eae1f YR |
8577 | bnx2x_cl45_write(bp, phy, |
8578 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); | |
8579 | /* Enable CL37 AN */ | |
8580 | bnx2x_cl45_write(bp, phy, | |
8581 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
8582 | /* 1G support */ | |
8583 | bnx2x_cl45_write(bp, phy, | |
8584 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); | |
6bbca910 | 8585 | |
de6eae1f YR |
8586 | /* Enable clause 73 AN */ |
8587 | bnx2x_cl45_write(bp, phy, | |
8588 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
8589 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8590 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
8591 | 0x0400); |
8592 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8593 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, |
de6eae1f YR |
8594 | 0x0004); |
8595 | } | |
8596 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
a8db5b4c | 8597 | |
8f73f0b9 | 8598 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low |
a8db5b4c YR |
8599 | * power mode, if TX Laser is disabled |
8600 | */ | |
8601 | ||
8602 | tx_en_mode = REG_RD(bp, params->shmem_base + | |
8603 | offsetof(struct shmem_region, | |
8604 | dev_info.port_hw_config[params->port].sfp_ctrl)) | |
8605 | & PORT_HW_CFG_TX_LASER_MASK; | |
8606 | ||
8607 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { | |
8608 | DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); | |
8609 | bnx2x_cl45_read(bp, phy, | |
8610 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); | |
8611 | tmp1 |= 0x1; | |
8612 | bnx2x_cl45_write(bp, phy, | |
8613 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); | |
8614 | } | |
8615 | ||
de6eae1f YR |
8616 | return 0; |
8617 | } | |
ea4e040a | 8618 | |
fcf5b650 YR |
8619 | static int bnx2x_8706_read_status(struct bnx2x_phy *phy, |
8620 | struct link_params *params, | |
8621 | struct link_vars *vars) | |
de6eae1f YR |
8622 | { |
8623 | return bnx2x_8706_8726_read_status(phy, params, vars); | |
8624 | } | |
6bbca910 | 8625 | |
de6eae1f YR |
8626 | /******************************************************************/ |
8627 | /* BCM8726 PHY SECTION */ | |
8628 | /******************************************************************/ | |
8629 | static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, | |
8630 | struct link_params *params) | |
8631 | { | |
8632 | struct bnx2x *bp = params->bp; | |
8633 | DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); | |
8634 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); | |
8635 | } | |
62b29a5d | 8636 | |
de6eae1f YR |
8637 | static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, |
8638 | struct link_params *params) | |
8639 | { | |
8640 | struct bnx2x *bp = params->bp; | |
8641 | /* Need to wait 100ms after reset */ | |
8642 | msleep(100); | |
62b29a5d | 8643 | |
de6eae1f YR |
8644 | /* Micro controller re-boot */ |
8645 | bnx2x_cl45_write(bp, phy, | |
8646 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); | |
62b29a5d | 8647 | |
de6eae1f YR |
8648 | /* Set soft reset */ |
8649 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
8650 | MDIO_PMA_DEVAD, |
8651 | MDIO_PMA_REG_GEN_CTRL, | |
8652 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
62b29a5d | 8653 | |
de6eae1f | 8654 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8655 | MDIO_PMA_DEVAD, |
8656 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
6bbca910 | 8657 | |
de6eae1f | 8658 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8659 | MDIO_PMA_DEVAD, |
8660 | MDIO_PMA_REG_GEN_CTRL, | |
8661 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
de6eae1f YR |
8662 | |
8663 | /* wait for 150ms for microcode load */ | |
8664 | msleep(150); | |
8665 | ||
8666 | /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ | |
8667 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
8668 | MDIO_PMA_DEVAD, |
8669 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
de6eae1f YR |
8670 | |
8671 | msleep(200); | |
8672 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
b7737c9b YR |
8673 | } |
8674 | ||
de6eae1f | 8675 | static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
8676 | struct link_params *params, |
8677 | struct link_vars *vars) | |
8678 | { | |
8679 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
8680 | u16 val1; |
8681 | u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); | |
62b29a5d YR |
8682 | if (link_up) { |
8683 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
8684 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, |
8685 | &val1); | |
8686 | if (val1 & (1<<15)) { | |
8687 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); | |
8688 | link_up = 0; | |
8689 | vars->line_speed = 0; | |
8690 | } | |
62b29a5d YR |
8691 | } |
8692 | return link_up; | |
b7737c9b YR |
8693 | } |
8694 | ||
de6eae1f | 8695 | |
fcf5b650 YR |
8696 | static int bnx2x_8726_config_init(struct bnx2x_phy *phy, |
8697 | struct link_params *params, | |
8698 | struct link_vars *vars) | |
b7737c9b YR |
8699 | { |
8700 | struct bnx2x *bp = params->bp; | |
de6eae1f | 8701 | DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); |
62b29a5d | 8702 | |
de6eae1f | 8703 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
6d870c39 | 8704 | bnx2x_wait_reset_complete(bp, phy, params); |
62b29a5d | 8705 | |
de6eae1f | 8706 | bnx2x_8726_external_rom_boot(phy, params); |
62b29a5d | 8707 | |
8f73f0b9 | 8708 | /* Need to call module detected on initialization since the module |
2cf7acf9 YR |
8709 | * detection triggered by actual module insertion might occur before |
8710 | * driver is loaded, and when driver is loaded, it reset all | |
8711 | * registers, including the transmitter | |
8712 | */ | |
de6eae1f | 8713 | bnx2x_sfp_module_detection(phy, params); |
62b29a5d | 8714 | |
de6eae1f YR |
8715 | if (phy->req_line_speed == SPEED_1000) { |
8716 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
8717 | bnx2x_cl45_write(bp, phy, | |
8718 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
8719 | bnx2x_cl45_write(bp, phy, | |
8720 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
8721 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8722 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); |
de6eae1f | 8723 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 8724 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
8725 | 0x400); |
8726 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && | |
8727 | (phy->speed_cap_mask & | |
8728 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && | |
8729 | ((phy->speed_cap_mask & | |
8730 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
8731 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
8732 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
8733 | /* Set Flow control */ | |
8734 | bnx2x_ext_phy_set_pause(params, phy, vars); | |
8735 | bnx2x_cl45_write(bp, phy, | |
8736 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); | |
8737 | bnx2x_cl45_write(bp, phy, | |
8738 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
8739 | bnx2x_cl45_write(bp, phy, | |
8740 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); | |
8741 | bnx2x_cl45_write(bp, phy, | |
8742 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
8743 | bnx2x_cl45_write(bp, phy, | |
8744 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
8f73f0b9 | 8745 | /* Enable RX-ALARM control to receive interrupt for 1G speed |
2cf7acf9 YR |
8746 | * change |
8747 | */ | |
de6eae1f | 8748 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 8749 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); |
de6eae1f | 8750 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 8751 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f | 8752 | 0x400); |
62b29a5d | 8753 | |
de6eae1f YR |
8754 | } else { /* Default 10G. Set only LASI control */ |
8755 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8756 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); |
7aa0711f YR |
8757 | } |
8758 | ||
de6eae1f YR |
8759 | /* Set TX PreEmphasis if needed */ |
8760 | if ((params->feature_config_flags & | |
8761 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
94f05b0f JP |
8762 | DP(NETIF_MSG_LINK, |
8763 | "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", | |
de6eae1f YR |
8764 | phy->tx_preemphasis[0], |
8765 | phy->tx_preemphasis[1]); | |
8766 | bnx2x_cl45_write(bp, phy, | |
8767 | MDIO_PMA_DEVAD, | |
8768 | MDIO_PMA_REG_8726_TX_CTRL1, | |
8769 | phy->tx_preemphasis[0]); | |
c18aa15d | 8770 | |
de6eae1f YR |
8771 | bnx2x_cl45_write(bp, phy, |
8772 | MDIO_PMA_DEVAD, | |
8773 | MDIO_PMA_REG_8726_TX_CTRL2, | |
8774 | phy->tx_preemphasis[1]); | |
8775 | } | |
ab6ad5a4 | 8776 | |
de6eae1f | 8777 | return 0; |
ab6ad5a4 | 8778 | |
ea4e040a YR |
8779 | } |
8780 | ||
de6eae1f YR |
8781 | static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, |
8782 | struct link_params *params) | |
2f904460 | 8783 | { |
de6eae1f YR |
8784 | struct bnx2x *bp = params->bp; |
8785 | DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); | |
8786 | /* Set serial boot control for external load */ | |
8787 | bnx2x_cl45_write(bp, phy, | |
8788 | MDIO_PMA_DEVAD, | |
8789 | MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
8790 | } | |
8791 | ||
8792 | /******************************************************************/ | |
8793 | /* BCM8727 PHY SECTION */ | |
8794 | /******************************************************************/ | |
7f02c4ad YR |
8795 | |
8796 | static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, | |
8797 | struct link_params *params, u8 mode) | |
8798 | { | |
8799 | struct bnx2x *bp = params->bp; | |
8800 | u16 led_mode_bitmask = 0; | |
8801 | u16 gpio_pins_bitmask = 0; | |
8802 | u16 val; | |
8803 | /* Only NOC flavor requires to set the LED specifically */ | |
8804 | if (!(phy->flags & FLAGS_NOC)) | |
8805 | return; | |
8806 | switch (mode) { | |
8807 | case LED_MODE_FRONT_PANEL_OFF: | |
8808 | case LED_MODE_OFF: | |
8809 | led_mode_bitmask = 0; | |
8810 | gpio_pins_bitmask = 0x03; | |
8811 | break; | |
8812 | case LED_MODE_ON: | |
8813 | led_mode_bitmask = 0; | |
8814 | gpio_pins_bitmask = 0x02; | |
8815 | break; | |
8816 | case LED_MODE_OPER: | |
8817 | led_mode_bitmask = 0x60; | |
8818 | gpio_pins_bitmask = 0x11; | |
8819 | break; | |
8820 | } | |
8821 | bnx2x_cl45_read(bp, phy, | |
8822 | MDIO_PMA_DEVAD, | |
8823 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
8824 | &val); | |
8825 | val &= 0xff8f; | |
8826 | val |= led_mode_bitmask; | |
8827 | bnx2x_cl45_write(bp, phy, | |
8828 | MDIO_PMA_DEVAD, | |
8829 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
8830 | val); | |
8831 | bnx2x_cl45_read(bp, phy, | |
8832 | MDIO_PMA_DEVAD, | |
8833 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
8834 | &val); | |
8835 | val &= 0xffe0; | |
8836 | val |= gpio_pins_bitmask; | |
8837 | bnx2x_cl45_write(bp, phy, | |
8838 | MDIO_PMA_DEVAD, | |
8839 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
8840 | val); | |
8841 | } | |
de6eae1f YR |
8842 | static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, |
8843 | struct link_params *params) { | |
8844 | u32 swap_val, swap_override; | |
8845 | u8 port; | |
8f73f0b9 | 8846 | /* The PHY reset is controlled by GPIO 1. Fake the port number |
de6eae1f | 8847 | * to cancel the swap done in set_gpio() |
2f904460 | 8848 | */ |
de6eae1f YR |
8849 | struct bnx2x *bp = params->bp; |
8850 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
8851 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
8852 | port = (swap_val && swap_override) ^ 1; | |
8853 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 8854 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
2f904460 | 8855 | } |
e10bc84d | 8856 | |
fcf5b650 YR |
8857 | static int bnx2x_8727_config_init(struct bnx2x_phy *phy, |
8858 | struct link_params *params, | |
8859 | struct link_vars *vars) | |
ea4e040a | 8860 | { |
a8db5b4c YR |
8861 | u32 tx_en_mode; |
8862 | u16 tmp1, val, mod_abs, tmp2; | |
de6eae1f YR |
8863 | u16 rx_alarm_ctrl_val; |
8864 | u16 lasi_ctrl_val; | |
ea4e040a | 8865 | struct bnx2x *bp = params->bp; |
de6eae1f | 8866 | /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ |
ea4e040a | 8867 | |
6d870c39 | 8868 | bnx2x_wait_reset_complete(bp, phy, params); |
de6eae1f | 8869 | rx_alarm_ctrl_val = (1<<2) | (1<<5) ; |
c688fe2f YR |
8870 | /* Should be 0x6 to enable XS on Tx side. */ |
8871 | lasi_ctrl_val = 0x0006; | |
ea4e040a | 8872 | |
de6eae1f YR |
8873 | DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); |
8874 | /* enable LASI */ | |
8875 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8876 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f | 8877 | rx_alarm_ctrl_val); |
c688fe2f | 8878 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 8879 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, |
c688fe2f | 8880 | 0); |
de6eae1f | 8881 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 8882 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val); |
ea4e040a | 8883 | |
8f73f0b9 | 8884 | /* Initially configure MOD_ABS to interrupt when module is |
2cf7acf9 YR |
8885 | * presence( bit 8) |
8886 | */ | |
de6eae1f YR |
8887 | bnx2x_cl45_read(bp, phy, |
8888 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
8f73f0b9 | 8889 | /* Set EDC off by setting OPTXLOS signal input to low (bit 9). |
2cf7acf9 YR |
8890 | * When the EDC is off it locks onto a reference clock and avoids |
8891 | * becoming 'lost' | |
8892 | */ | |
7f02c4ad YR |
8893 | mod_abs &= ~(1<<8); |
8894 | if (!(phy->flags & FLAGS_NOC)) | |
8895 | mod_abs &= ~(1<<9); | |
de6eae1f YR |
8896 | bnx2x_cl45_write(bp, phy, |
8897 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 8898 | |
ea4e040a | 8899 | |
85242eea YR |
8900 | /* Enable/Disable PHY transmitter output */ |
8901 | bnx2x_set_disable_pmd_transmit(params, phy, 0); | |
8902 | ||
de6eae1f YR |
8903 | /* Make MOD_ABS give interrupt on change */ |
8904 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
8905 | &val); | |
8906 | val |= (1<<12); | |
7f02c4ad YR |
8907 | if (phy->flags & FLAGS_NOC) |
8908 | val |= (3<<5); | |
b7737c9b | 8909 | |
8f73f0b9 | 8910 | /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 |
7f02c4ad YR |
8911 | * status which reflect SFP+ module over-current |
8912 | */ | |
8913 | if (!(phy->flags & FLAGS_NOC)) | |
8914 | val &= 0xff8f; /* Reset bits 4-6 */ | |
de6eae1f YR |
8915 | bnx2x_cl45_write(bp, phy, |
8916 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val); | |
ea4e040a | 8917 | |
de6eae1f YR |
8918 | bnx2x_8727_power_module(bp, phy, 1); |
8919 | ||
8920 | bnx2x_cl45_read(bp, phy, | |
8921 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); | |
8922 | ||
8923 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 8924 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); |
de6eae1f YR |
8925 | |
8926 | /* Set option 1G speed */ | |
8927 | if (phy->req_line_speed == SPEED_1000) { | |
8928 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
8929 | bnx2x_cl45_write(bp, phy, | |
8930 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
8931 | bnx2x_cl45_write(bp, phy, | |
8932 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
8933 | bnx2x_cl45_read(bp, phy, | |
8934 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); | |
8935 | DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); | |
8f73f0b9 | 8936 | /* Power down the XAUI until link is up in case of dual-media |
a22f0788 YR |
8937 | * and 1G |
8938 | */ | |
8939 | if (DUAL_MEDIA(params)) { | |
8940 | bnx2x_cl45_read(bp, phy, | |
8941 | MDIO_PMA_DEVAD, | |
8942 | MDIO_PMA_REG_8727_PCS_GP, &val); | |
8943 | val |= (3<<10); | |
8944 | bnx2x_cl45_write(bp, phy, | |
8945 | MDIO_PMA_DEVAD, | |
8946 | MDIO_PMA_REG_8727_PCS_GP, val); | |
8947 | } | |
de6eae1f YR |
8948 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
8949 | ((phy->speed_cap_mask & | |
8950 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && | |
8951 | ((phy->speed_cap_mask & | |
8952 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
8953 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
8954 | ||
8955 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
8956 | bnx2x_cl45_write(bp, phy, | |
8957 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); | |
8958 | bnx2x_cl45_write(bp, phy, | |
8959 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); | |
8960 | } else { | |
8f73f0b9 | 8961 | /* Since the 8727 has only single reset pin, need to set the 10G |
de6eae1f YR |
8962 | * registers although it is default |
8963 | */ | |
8964 | bnx2x_cl45_write(bp, phy, | |
8965 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, | |
8966 | 0x0020); | |
8967 | bnx2x_cl45_write(bp, phy, | |
8968 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); | |
8969 | bnx2x_cl45_write(bp, phy, | |
8970 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
8971 | bnx2x_cl45_write(bp, phy, | |
8972 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, | |
8973 | 0x0008); | |
ea4e040a | 8974 | } |
ea4e040a | 8975 | |
8f73f0b9 | 8976 | /* Set 2-wire transfer rate of SFP+ module EEPROM |
de6eae1f YR |
8977 | * to 100Khz since some DACs(direct attached cables) do |
8978 | * not work at 400Khz. | |
8979 | */ | |
8980 | bnx2x_cl45_write(bp, phy, | |
8981 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, | |
8982 | 0xa001); | |
b7737c9b | 8983 | |
de6eae1f YR |
8984 | /* Set TX PreEmphasis if needed */ |
8985 | if ((params->feature_config_flags & | |
8986 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
8987 | DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", | |
8988 | phy->tx_preemphasis[0], | |
8989 | phy->tx_preemphasis[1]); | |
8990 | bnx2x_cl45_write(bp, phy, | |
8991 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, | |
8992 | phy->tx_preemphasis[0]); | |
ea4e040a | 8993 | |
de6eae1f YR |
8994 | bnx2x_cl45_write(bp, phy, |
8995 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, | |
8996 | phy->tx_preemphasis[1]); | |
8997 | } | |
ea4e040a | 8998 | |
8f73f0b9 | 8999 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low |
a8db5b4c YR |
9000 | * power mode, if TX Laser is disabled |
9001 | */ | |
9002 | tx_en_mode = REG_RD(bp, params->shmem_base + | |
9003 | offsetof(struct shmem_region, | |
9004 | dev_info.port_hw_config[params->port].sfp_ctrl)) | |
9005 | & PORT_HW_CFG_TX_LASER_MASK; | |
9006 | ||
9007 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { | |
9008 | ||
9009 | DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); | |
9010 | bnx2x_cl45_read(bp, phy, | |
9011 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); | |
9012 | tmp2 |= 0x1000; | |
9013 | tmp2 &= 0xFFEF; | |
9014 | bnx2x_cl45_write(bp, phy, | |
9015 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); | |
59a2e53b YR |
9016 | bnx2x_cl45_read(bp, phy, |
9017 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, | |
9018 | &tmp2); | |
9019 | bnx2x_cl45_write(bp, phy, | |
9020 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, | |
9021 | (tmp2 & 0x7fff)); | |
a8db5b4c YR |
9022 | } |
9023 | ||
de6eae1f | 9024 | return 0; |
ea4e040a YR |
9025 | } |
9026 | ||
de6eae1f YR |
9027 | static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, |
9028 | struct link_params *params) | |
ea4e040a | 9029 | { |
ea4e040a | 9030 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
9031 | u16 mod_abs, rx_alarm_status; |
9032 | u32 val = REG_RD(bp, params->shmem_base + | |
9033 | offsetof(struct shmem_region, dev_info. | |
9034 | port_feature_config[params->port]. | |
9035 | config)); | |
9036 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
9037 | MDIO_PMA_DEVAD, |
9038 | MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
de6eae1f | 9039 | if (mod_abs & (1<<8)) { |
ea4e040a | 9040 | |
de6eae1f | 9041 | /* Module is absent */ |
94f05b0f JP |
9042 | DP(NETIF_MSG_LINK, |
9043 | "MOD_ABS indication show module is absent\n"); | |
1ac9e428 | 9044 | phy->media_type = ETH_PHY_NOT_PRESENT; |
8f73f0b9 | 9045 | /* 1. Set mod_abs to detect next module |
2cf7acf9 YR |
9046 | * presence event |
9047 | * 2. Set EDC off by setting OPTXLOS signal input to low | |
9048 | * (bit 9). | |
9049 | * When the EDC is off it locks onto a reference clock and | |
9050 | * avoids becoming 'lost'. | |
9051 | */ | |
7f02c4ad YR |
9052 | mod_abs &= ~(1<<8); |
9053 | if (!(phy->flags & FLAGS_NOC)) | |
9054 | mod_abs &= ~(1<<9); | |
de6eae1f | 9055 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
9056 | MDIO_PMA_DEVAD, |
9057 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9058 | |
8f73f0b9 | 9059 | /* Clear RX alarm since it stays up as long as |
2cf7acf9 YR |
9060 | * the mod_abs wasn't changed |
9061 | */ | |
de6eae1f | 9062 | bnx2x_cl45_read(bp, phy, |
cd88ccee | 9063 | MDIO_PMA_DEVAD, |
60d2fe03 | 9064 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
ea4e040a | 9065 | |
de6eae1f YR |
9066 | } else { |
9067 | /* Module is present */ | |
94f05b0f JP |
9068 | DP(NETIF_MSG_LINK, |
9069 | "MOD_ABS indication show module is present\n"); | |
8f73f0b9 | 9070 | /* First disable transmitter, and if the module is ok, the |
2cf7acf9 YR |
9071 | * module_detection will enable it |
9072 | * 1. Set mod_abs to detect next module absent event ( bit 8) | |
9073 | * 2. Restore the default polarity of the OPRXLOS signal and | |
9074 | * this signal will then correctly indicate the presence or | |
9075 | * absence of the Rx signal. (bit 9) | |
9076 | */ | |
7f02c4ad YR |
9077 | mod_abs |= (1<<8); |
9078 | if (!(phy->flags & FLAGS_NOC)) | |
9079 | mod_abs |= (1<<9); | |
e10bc84d | 9080 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
9081 | MDIO_PMA_DEVAD, |
9082 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9083 | |
8f73f0b9 | 9084 | /* Clear RX alarm since it stays up as long as the mod_abs |
2cf7acf9 YR |
9085 | * wasn't changed. This is need to be done before calling the |
9086 | * module detection, otherwise it will clear* the link update | |
9087 | * alarm | |
9088 | */ | |
de6eae1f YR |
9089 | bnx2x_cl45_read(bp, phy, |
9090 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9091 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
ea4e040a | 9092 | |
ea4e040a | 9093 | |
de6eae1f YR |
9094 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
9095 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
a8db5b4c | 9096 | bnx2x_sfp_set_transmitter(params, phy, 0); |
de6eae1f YR |
9097 | |
9098 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) | |
9099 | bnx2x_sfp_module_detection(phy, params); | |
9100 | else | |
9101 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); | |
ea4e040a | 9102 | } |
de6eae1f YR |
9103 | |
9104 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", | |
2cf7acf9 YR |
9105 | rx_alarm_status); |
9106 | /* No need to check link status in case of module plugged in/out */ | |
ea4e040a YR |
9107 | } |
9108 | ||
de6eae1f YR |
9109 | static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, |
9110 | struct link_params *params, | |
9111 | struct link_vars *vars) | |
9112 | ||
ea4e040a YR |
9113 | { |
9114 | struct bnx2x *bp = params->bp; | |
27d02432 | 9115 | u8 link_up = 0, oc_port = params->port; |
de6eae1f | 9116 | u16 link_status = 0; |
a22f0788 YR |
9117 | u16 rx_alarm_status, lasi_ctrl, val1; |
9118 | ||
9119 | /* If PHY is not initialized, do not check link status */ | |
9120 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 9121 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, |
a22f0788 YR |
9122 | &lasi_ctrl); |
9123 | if (!lasi_ctrl) | |
9124 | return 0; | |
9125 | ||
9045f6b4 | 9126 | /* Check the LASI on Rx */ |
de6eae1f | 9127 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 9128 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, |
de6eae1f YR |
9129 | &rx_alarm_status); |
9130 | vars->line_speed = 0; | |
9131 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); | |
9132 | ||
60d2fe03 YR |
9133 | bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, |
9134 | MDIO_PMA_LASI_TXCTRL); | |
c688fe2f | 9135 | |
de6eae1f | 9136 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 9137 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f YR |
9138 | |
9139 | DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); | |
9140 | ||
9141 | /* Clear MSG-OUT */ | |
9142 | bnx2x_cl45_read(bp, phy, | |
9143 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
9144 | ||
8f73f0b9 | 9145 | /* If a module is present and there is need to check |
de6eae1f YR |
9146 | * for over current |
9147 | */ | |
9148 | if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { | |
9149 | /* Check over-current using 8727 GPIO0 input*/ | |
9150 | bnx2x_cl45_read(bp, phy, | |
9151 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, | |
9152 | &val1); | |
9153 | ||
9154 | if ((val1 & (1<<8)) == 0) { | |
27d02432 YR |
9155 | if (!CHIP_IS_E1x(bp)) |
9156 | oc_port = BP_PATH(bp) + (params->port << 1); | |
94f05b0f JP |
9157 | DP(NETIF_MSG_LINK, |
9158 | "8727 Power fault has been detected on port %d\n", | |
9159 | oc_port); | |
2f751a80 YR |
9160 | netdev_err(bp->dev, "Error: Power fault on Port %d has " |
9161 | "been detected and the power to " | |
9162 | "that SFP+ module has been removed " | |
9163 | "to prevent failure of the card. " | |
9164 | "Please remove the SFP+ module and " | |
9165 | "restart the system to clear this " | |
9166 | "error.\n", | |
27d02432 | 9167 | oc_port); |
2cf7acf9 | 9168 | /* Disable all RX_ALARMs except for mod_abs */ |
de6eae1f YR |
9169 | bnx2x_cl45_write(bp, phy, |
9170 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9171 | MDIO_PMA_LASI_RXCTRL, (1<<5)); |
de6eae1f YR |
9172 | |
9173 | bnx2x_cl45_read(bp, phy, | |
9174 | MDIO_PMA_DEVAD, | |
9175 | MDIO_PMA_REG_PHY_IDENTIFIER, &val1); | |
9176 | /* Wait for module_absent_event */ | |
9177 | val1 |= (1<<8); | |
9178 | bnx2x_cl45_write(bp, phy, | |
9179 | MDIO_PMA_DEVAD, | |
9180 | MDIO_PMA_REG_PHY_IDENTIFIER, val1); | |
9181 | /* Clear RX alarm */ | |
9182 | bnx2x_cl45_read(bp, phy, | |
9183 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9184 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
de6eae1f YR |
9185 | return 0; |
9186 | } | |
9187 | } /* Over current check */ | |
9188 | ||
9189 | /* When module absent bit is set, check module */ | |
9190 | if (rx_alarm_status & (1<<5)) { | |
9191 | bnx2x_8727_handle_mod_abs(phy, params); | |
9192 | /* Enable all mod_abs and link detection bits */ | |
9193 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 9194 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
9195 | ((1<<5) | (1<<2))); |
9196 | } | |
59a2e53b YR |
9197 | |
9198 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { | |
9199 | DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); | |
9200 | bnx2x_sfp_set_transmitter(params, phy, 1); | |
9201 | } else { | |
de6eae1f YR |
9202 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); |
9203 | return 0; | |
9204 | } | |
9205 | ||
9206 | bnx2x_cl45_read(bp, phy, | |
9207 | MDIO_PMA_DEVAD, | |
9208 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); | |
9209 | ||
8f73f0b9 | 9210 | /* Bits 0..2 --> speed detected, |
2cf7acf9 YR |
9211 | * Bits 13..15--> link is down |
9212 | */ | |
de6eae1f YR |
9213 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { |
9214 | link_up = 1; | |
9215 | vars->line_speed = SPEED_10000; | |
2cf7acf9 YR |
9216 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", |
9217 | params->port); | |
de6eae1f YR |
9218 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { |
9219 | link_up = 1; | |
9220 | vars->line_speed = SPEED_1000; | |
9221 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
9222 | params->port); | |
9223 | } else { | |
9224 | link_up = 0; | |
9225 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
9226 | params->port); | |
9227 | } | |
c688fe2f YR |
9228 | |
9229 | /* Capture 10G link fault. */ | |
9230 | if (vars->line_speed == SPEED_10000) { | |
9231 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 9232 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
9233 | |
9234 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 9235 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
9236 | |
9237 | if (val1 & (1<<0)) { | |
9238 | vars->fault_detected = 1; | |
9239 | } | |
9240 | } | |
9241 | ||
791f18c0 | 9242 | if (link_up) { |
de6eae1f | 9243 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
791f18c0 YR |
9244 | vars->duplex = DUPLEX_FULL; |
9245 | DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); | |
9246 | } | |
a22f0788 YR |
9247 | |
9248 | if ((DUAL_MEDIA(params)) && | |
9249 | (phy->req_line_speed == SPEED_1000)) { | |
9250 | bnx2x_cl45_read(bp, phy, | |
9251 | MDIO_PMA_DEVAD, | |
9252 | MDIO_PMA_REG_8727_PCS_GP, &val1); | |
8f73f0b9 | 9253 | /* In case of dual-media board and 1G, power up the XAUI side, |
a22f0788 YR |
9254 | * otherwise power it down. For 10G it is done automatically |
9255 | */ | |
9256 | if (link_up) | |
9257 | val1 &= ~(3<<10); | |
9258 | else | |
9259 | val1 |= (3<<10); | |
9260 | bnx2x_cl45_write(bp, phy, | |
9261 | MDIO_PMA_DEVAD, | |
9262 | MDIO_PMA_REG_8727_PCS_GP, val1); | |
9263 | } | |
de6eae1f | 9264 | return link_up; |
b7737c9b | 9265 | } |
ea4e040a | 9266 | |
de6eae1f YR |
9267 | static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, |
9268 | struct link_params *params) | |
b7737c9b YR |
9269 | { |
9270 | struct bnx2x *bp = params->bp; | |
85242eea YR |
9271 | |
9272 | /* Enable/Disable PHY transmitter output */ | |
9273 | bnx2x_set_disable_pmd_transmit(params, phy, 1); | |
9274 | ||
de6eae1f | 9275 | /* Disable Transmitter */ |
a8db5b4c | 9276 | bnx2x_sfp_set_transmitter(params, phy, 0); |
a22f0788 | 9277 | /* Clear LASI */ |
60d2fe03 | 9278 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); |
a22f0788 | 9279 | |
ea4e040a | 9280 | } |
c18aa15d | 9281 | |
de6eae1f YR |
9282 | /******************************************************************/ |
9283 | /* BCM8481/BCM84823/BCM84833 PHY SECTION */ | |
9284 | /******************************************************************/ | |
9285 | static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |
11b2ec6b YR |
9286 | struct bnx2x *bp, |
9287 | u8 port) | |
ea4e040a | 9288 | { |
bac27bd9 | 9289 | u16 val, fw_ver1, fw_ver2, cnt; |
ea4e040a | 9290 | |
11b2ec6b YR |
9291 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
9292 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); | |
8267bbb0 | 9293 | bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, |
11b2ec6b YR |
9294 | phy->ver_addr); |
9295 | } else { | |
9296 | /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ | |
9297 | /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ | |
9298 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014); | |
9299 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
9300 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000); | |
9301 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300); | |
9302 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009); | |
9303 | ||
9304 | for (cnt = 0; cnt < 100; cnt++) { | |
9305 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
9306 | if (val & 1) | |
9307 | break; | |
9308 | udelay(5); | |
9309 | } | |
9310 | if (cnt == 100) { | |
9311 | DP(NETIF_MSG_LINK, "Unable to read 848xx " | |
9312 | "phy fw version(1)\n"); | |
9313 | bnx2x_save_spirom_version(bp, port, 0, | |
9314 | phy->ver_addr); | |
9315 | return; | |
9316 | } | |
c87bca1e | 9317 | |
ea4e040a | 9318 | |
11b2ec6b YR |
9319 | /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ |
9320 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); | |
9321 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
9322 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); | |
9323 | for (cnt = 0; cnt < 100; cnt++) { | |
9324 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
9325 | if (val & 1) | |
9326 | break; | |
9327 | udelay(5); | |
9328 | } | |
9329 | if (cnt == 100) { | |
9330 | DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " | |
9331 | "version(2)\n"); | |
9332 | bnx2x_save_spirom_version(bp, port, 0, | |
9333 | phy->ver_addr); | |
9334 | return; | |
9335 | } | |
ea4e040a | 9336 | |
11b2ec6b YR |
9337 | /* lower 16 bits of the register SPI_FW_STATUS */ |
9338 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); | |
9339 | /* upper 16 bits of register SPI_FW_STATUS */ | |
9340 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); | |
ea4e040a | 9341 | |
11b2ec6b | 9342 | bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, |
de6eae1f | 9343 | phy->ver_addr); |
ea4e040a YR |
9344 | } |
9345 | ||
de6eae1f | 9346 | } |
de6eae1f YR |
9347 | static void bnx2x_848xx_set_led(struct bnx2x *bp, |
9348 | struct bnx2x_phy *phy) | |
ea4e040a | 9349 | { |
521683da | 9350 | u16 val, offset; |
7846e471 | 9351 | |
de6eae1f YR |
9352 | /* PHYC_CTL_LED_CTL */ |
9353 | bnx2x_cl45_read(bp, phy, | |
9354 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9355 | MDIO_PMA_REG_8481_LINK_SIGNAL, &val); |
de6eae1f YR |
9356 | val &= 0xFE00; |
9357 | val |= 0x0092; | |
345b5d52 | 9358 | |
de6eae1f YR |
9359 | bnx2x_cl45_write(bp, phy, |
9360 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9361 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); |
ea4e040a | 9362 | |
de6eae1f YR |
9363 | bnx2x_cl45_write(bp, phy, |
9364 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9365 | MDIO_PMA_REG_8481_LED1_MASK, |
de6eae1f | 9366 | 0x80); |
ea4e040a | 9367 | |
de6eae1f YR |
9368 | bnx2x_cl45_write(bp, phy, |
9369 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9370 | MDIO_PMA_REG_8481_LED2_MASK, |
de6eae1f | 9371 | 0x18); |
ea4e040a | 9372 | |
f25b3c8b | 9373 | /* Select activity source by Tx and Rx, as suggested by PHY AE */ |
de6eae1f YR |
9374 | bnx2x_cl45_write(bp, phy, |
9375 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9376 | MDIO_PMA_REG_8481_LED3_MASK, |
f25b3c8b YR |
9377 | 0x0006); |
9378 | ||
9379 | /* Select the closest activity blink rate to that in 10/100/1000 */ | |
9380 | bnx2x_cl45_write(bp, phy, | |
9381 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9382 | MDIO_PMA_REG_8481_LED3_BLINK, |
f25b3c8b YR |
9383 | 0); |
9384 | ||
521683da YR |
9385 | /* Configure the blink rate to ~15.9 Hz */ |
9386 | bnx2x_cl45_write(bp, phy, | |
f25b3c8b | 9387 | MDIO_PMA_DEVAD, |
521683da YR |
9388 | MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, |
9389 | MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ); | |
f25b3c8b | 9390 | |
521683da YR |
9391 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) |
9392 | offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; | |
9393 | else | |
9394 | offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; | |
9395 | ||
9396 | bnx2x_cl45_read(bp, phy, | |
9397 | MDIO_PMA_DEVAD, offset, &val); | |
9398 | val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/ | |
f25b3c8b | 9399 | bnx2x_cl45_write(bp, phy, |
521683da | 9400 | MDIO_PMA_DEVAD, offset, val); |
ea4e040a | 9401 | |
de6eae1f YR |
9402 | /* 'Interrupt Mask' */ |
9403 | bnx2x_cl45_write(bp, phy, | |
9404 | MDIO_AN_DEVAD, | |
9405 | 0xFFFB, 0xFFFD); | |
ea4e040a YR |
9406 | } |
9407 | ||
fcf5b650 YR |
9408 | static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, |
9409 | struct link_params *params, | |
9410 | struct link_vars *vars) | |
ea4e040a | 9411 | { |
c18aa15d | 9412 | struct bnx2x *bp = params->bp; |
521683da | 9413 | u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val; |
bac27bd9 | 9414 | |
817a8aa8 | 9415 | if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
11b2ec6b YR |
9416 | /* Save spirom version */ |
9417 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); | |
9418 | } | |
8f73f0b9 | 9419 | /* This phy uses the NIG latch mechanism since link indication |
2cf7acf9 YR |
9420 | * arrives through its LED4 and not via its LASI signal, so we |
9421 | * get steady signal instead of clear on read | |
9422 | */ | |
de6eae1f YR |
9423 | bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, |
9424 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
ea4e040a | 9425 | |
de6eae1f YR |
9426 | bnx2x_cl45_write(bp, phy, |
9427 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); | |
ea4e040a | 9428 | |
de6eae1f | 9429 | bnx2x_848xx_set_led(bp, phy); |
ea4e040a | 9430 | |
de6eae1f YR |
9431 | /* set 1000 speed advertisement */ |
9432 | bnx2x_cl45_read(bp, phy, | |
9433 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
9434 | &an_1000_val); | |
57963ed9 | 9435 | |
de6eae1f YR |
9436 | bnx2x_ext_phy_set_pause(params, phy, vars); |
9437 | bnx2x_cl45_read(bp, phy, | |
9438 | MDIO_AN_DEVAD, | |
9439 | MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
9440 | &an_10_100_val); | |
9441 | bnx2x_cl45_read(bp, phy, | |
9442 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
9443 | &autoneg_val); | |
9444 | /* Disable forced speed */ | |
9445 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); | |
9446 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); | |
ea4e040a | 9447 | |
de6eae1f YR |
9448 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
9449 | (phy->speed_cap_mask & | |
9450 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
9451 | (phy->req_line_speed == SPEED_1000)) { | |
9452 | an_1000_val |= (1<<8); | |
9453 | autoneg_val |= (1<<9 | 1<<12); | |
9454 | if (phy->req_duplex == DUPLEX_FULL) | |
9455 | an_1000_val |= (1<<9); | |
9456 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); | |
9457 | } else | |
9458 | an_1000_val &= ~((1<<8) | (1<<9)); | |
ea4e040a | 9459 | |
de6eae1f YR |
9460 | bnx2x_cl45_write(bp, phy, |
9461 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
9462 | an_1000_val); | |
ea4e040a | 9463 | |
0520e63a | 9464 | /* set 100 speed advertisement */ |
75318327 | 9465 | if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
de6eae1f | 9466 | (phy->speed_cap_mask & |
0520e63a | 9467 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | |
75318327 | 9468 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) { |
de6eae1f YR |
9469 | an_10_100_val |= (1<<7); |
9470 | /* Enable autoneg and restart autoneg for legacy speeds */ | |
9471 | autoneg_val |= (1<<9 | 1<<12); | |
b7737c9b | 9472 | |
de6eae1f YR |
9473 | if (phy->req_duplex == DUPLEX_FULL) |
9474 | an_10_100_val |= (1<<8); | |
9475 | DP(NETIF_MSG_LINK, "Advertising 100M\n"); | |
9476 | } | |
9477 | /* set 10 speed advertisement */ | |
9478 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
0520e63a YR |
9479 | (phy->speed_cap_mask & |
9480 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | | |
9481 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) && | |
9482 | (phy->supported & | |
9483 | (SUPPORTED_10baseT_Half | | |
9484 | SUPPORTED_10baseT_Full)))) { | |
de6eae1f YR |
9485 | an_10_100_val |= (1<<5); |
9486 | autoneg_val |= (1<<9 | 1<<12); | |
9487 | if (phy->req_duplex == DUPLEX_FULL) | |
9488 | an_10_100_val |= (1<<6); | |
9489 | DP(NETIF_MSG_LINK, "Advertising 10M\n"); | |
9490 | } | |
b7737c9b | 9491 | |
de6eae1f | 9492 | /* Only 10/100 are allowed to work in FORCE mode */ |
0520e63a YR |
9493 | if ((phy->req_line_speed == SPEED_100) && |
9494 | (phy->supported & | |
9495 | (SUPPORTED_100baseT_Half | | |
9496 | SUPPORTED_100baseT_Full))) { | |
de6eae1f YR |
9497 | autoneg_val |= (1<<13); |
9498 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
9499 | bnx2x_cl45_write(bp, phy, | |
9500 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
9501 | (1<<15 | 1<<9 | 7<<0)); | |
521683da YR |
9502 | /* The PHY needs this set even for forced link. */ |
9503 | an_10_100_val |= (1<<8) | (1<<7); | |
de6eae1f YR |
9504 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); |
9505 | } | |
0520e63a YR |
9506 | if ((phy->req_line_speed == SPEED_10) && |
9507 | (phy->supported & | |
9508 | (SUPPORTED_10baseT_Half | | |
9509 | SUPPORTED_10baseT_Full))) { | |
de6eae1f YR |
9510 | /* Enabled AUTO-MDIX when autoneg is disabled */ |
9511 | bnx2x_cl45_write(bp, phy, | |
9512 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
9513 | (1<<15 | 1<<9 | 7<<0)); | |
9514 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); | |
9515 | } | |
b7737c9b | 9516 | |
de6eae1f YR |
9517 | bnx2x_cl45_write(bp, phy, |
9518 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
9519 | an_10_100_val); | |
b7737c9b | 9520 | |
de6eae1f YR |
9521 | if (phy->req_duplex == DUPLEX_FULL) |
9522 | autoneg_val |= (1<<8); | |
b7737c9b | 9523 | |
8f73f0b9 | 9524 | /* Always write this if this is not 84833. |
fd38f73e YR |
9525 | * For 84833, write it only when it's a forced speed. |
9526 | */ | |
9527 | if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || | |
9528 | ((autoneg_val & (1<<12)) == 0)) | |
9529 | bnx2x_cl45_write(bp, phy, | |
de6eae1f YR |
9530 | MDIO_AN_DEVAD, |
9531 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); | |
b7737c9b | 9532 | |
de6eae1f YR |
9533 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
9534 | (phy->speed_cap_mask & | |
9535 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
9536 | (phy->req_line_speed == SPEED_10000)) { | |
9045f6b4 YR |
9537 | DP(NETIF_MSG_LINK, "Advertising 10G\n"); |
9538 | /* Restart autoneg for 10G*/ | |
de6eae1f | 9539 | |
521683da YR |
9540 | bnx2x_cl45_read(bp, phy, |
9541 | MDIO_AN_DEVAD, | |
9542 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9543 | &an_10g_val); | |
9045f6b4 | 9544 | bnx2x_cl45_write(bp, phy, |
521683da YR |
9545 | MDIO_AN_DEVAD, |
9546 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9547 | an_10g_val | 0x1000); | |
9548 | bnx2x_cl45_write(bp, phy, | |
9549 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, | |
9550 | 0x3200); | |
fd38f73e | 9551 | } else |
de6eae1f YR |
9552 | bnx2x_cl45_write(bp, phy, |
9553 | MDIO_AN_DEVAD, | |
9554 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9555 | 1); | |
fd38f73e | 9556 | |
de6eae1f | 9557 | return 0; |
b7737c9b YR |
9558 | } |
9559 | ||
fcf5b650 YR |
9560 | static int bnx2x_8481_config_init(struct bnx2x_phy *phy, |
9561 | struct link_params *params, | |
9562 | struct link_vars *vars) | |
ea4e040a YR |
9563 | { |
9564 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
9565 | /* Restore normal power mode*/ |
9566 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 9567 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
b7737c9b | 9568 | |
de6eae1f YR |
9569 | /* HW reset */ |
9570 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
6d870c39 | 9571 | bnx2x_wait_reset_complete(bp, phy, params); |
ab6ad5a4 | 9572 | |
de6eae1f YR |
9573 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
9574 | return bnx2x_848xx_cmn_config_init(phy, params, vars); | |
9575 | } | |
ea4e040a | 9576 | |
521683da YR |
9577 | #define PHY84833_CMDHDLR_WAIT 300 |
9578 | #define PHY84833_CMDHDLR_MAX_ARGS 5 | |
9579 | static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, | |
bac27bd9 | 9580 | struct link_params *params, |
521683da YR |
9581 | u16 fw_cmd, |
9582 | u16 cmd_args[]) | |
bac27bd9 YR |
9583 | { |
9584 | u32 idx; | |
9585 | u16 val; | |
bac27bd9 | 9586 | struct bnx2x *bp = params->bp; |
bac27bd9 YR |
9587 | /* Write CMD_OPEN_OVERRIDE to STATUS reg */ |
9588 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
521683da YR |
9589 | MDIO_84833_CMD_HDLR_STATUS, |
9590 | PHY84833_STATUS_CMD_OPEN_OVERRIDE); | |
9591 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { | |
bac27bd9 | 9592 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9593 | MDIO_84833_CMD_HDLR_STATUS, &val); |
9594 | if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) | |
bac27bd9 YR |
9595 | break; |
9596 | msleep(1); | |
9597 | } | |
521683da YR |
9598 | if (idx >= PHY84833_CMDHDLR_WAIT) { |
9599 | DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); | |
bac27bd9 YR |
9600 | return -EINVAL; |
9601 | } | |
9602 | ||
521683da YR |
9603 | /* Prepare argument(s) and issue command */ |
9604 | for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) { | |
9605 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
9606 | MDIO_84833_CMD_HDLR_DATA1 + idx, | |
9607 | cmd_args[idx]); | |
9608 | } | |
bac27bd9 | 9609 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9610 | MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); |
9611 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { | |
bac27bd9 | 9612 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9613 | MDIO_84833_CMD_HDLR_STATUS, &val); |
9614 | if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || | |
9615 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) | |
bac27bd9 YR |
9616 | break; |
9617 | msleep(1); | |
9618 | } | |
521683da YR |
9619 | if ((idx >= PHY84833_CMDHDLR_WAIT) || |
9620 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { | |
9621 | DP(NETIF_MSG_LINK, "FW cmd failed.\n"); | |
bac27bd9 YR |
9622 | return -EINVAL; |
9623 | } | |
521683da YR |
9624 | /* Gather returning data */ |
9625 | for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) { | |
9626 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, | |
9627 | MDIO_84833_CMD_HDLR_DATA1 + idx, | |
9628 | &cmd_args[idx]); | |
9629 | } | |
bac27bd9 | 9630 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9631 | MDIO_84833_CMD_HDLR_STATUS, |
9632 | PHY84833_STATUS_CMD_CLEAR_COMPLETE); | |
bac27bd9 YR |
9633 | return 0; |
9634 | } | |
9635 | ||
0d40f0d4 | 9636 | |
521683da YR |
9637 | static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, |
9638 | struct link_params *params, | |
9639 | struct link_vars *vars) | |
9640 | { | |
9641 | u32 pair_swap; | |
9642 | u16 data[PHY84833_CMDHDLR_MAX_ARGS]; | |
9643 | int status; | |
9644 | struct bnx2x *bp = params->bp; | |
9645 | ||
9646 | /* Check for configuration. */ | |
9647 | pair_swap = REG_RD(bp, params->shmem_base + | |
9648 | offsetof(struct shmem_region, | |
9649 | dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & | |
9650 | PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; | |
9651 | ||
9652 | if (pair_swap == 0) | |
9653 | return 0; | |
9654 | ||
9655 | /* Only the second argument is used for this command */ | |
9656 | data[1] = (u16)pair_swap; | |
9657 | ||
9658 | status = bnx2x_84833_cmd_hdlr(phy, params, | |
9659 | PHY84833_CMD_SET_PAIR_SWAP, data); | |
9660 | if (status == 0) | |
9661 | DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); | |
9662 | ||
9663 | return status; | |
9664 | } | |
9665 | ||
985848f8 YR |
9666 | static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, |
9667 | u32 shmem_base_path[], | |
9668 | u32 chip_id) | |
0d40f0d4 YR |
9669 | { |
9670 | u32 reset_pin[2]; | |
9671 | u32 idx; | |
9672 | u8 reset_gpios; | |
9673 | if (CHIP_IS_E3(bp)) { | |
9674 | /* Assume that these will be GPIOs, not EPIOs. */ | |
9675 | for (idx = 0; idx < 2; idx++) { | |
9676 | /* Map config param to register bit. */ | |
9677 | reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + | |
9678 | offsetof(struct shmem_region, | |
9679 | dev_info.port_hw_config[0].e3_cmn_pin_cfg)); | |
9680 | reset_pin[idx] = (reset_pin[idx] & | |
9681 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
9682 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
9683 | reset_pin[idx] -= PIN_CFG_GPIO0_P0; | |
9684 | reset_pin[idx] = (1 << reset_pin[idx]); | |
9685 | } | |
9686 | reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); | |
9687 | } else { | |
9688 | /* E2, look from diff place of shmem. */ | |
9689 | for (idx = 0; idx < 2; idx++) { | |
9690 | reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + | |
9691 | offsetof(struct shmem_region, | |
9692 | dev_info.port_hw_config[0].default_cfg)); | |
9693 | reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; | |
9694 | reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; | |
9695 | reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; | |
9696 | reset_pin[idx] = (1 << reset_pin[idx]); | |
9697 | } | |
9698 | reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); | |
9699 | } | |
9700 | ||
985848f8 YR |
9701 | return reset_gpios; |
9702 | } | |
9703 | ||
9704 | static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, | |
9705 | struct link_params *params) | |
9706 | { | |
9707 | struct bnx2x *bp = params->bp; | |
9708 | u8 reset_gpios; | |
9709 | u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + | |
9710 | offsetof(struct shmem2_region, | |
9711 | other_shmem_base_addr)); | |
9712 | ||
9713 | u32 shmem_base_path[2]; | |
99bf7f34 YR |
9714 | |
9715 | /* Work around for 84833 LED failure inside RESET status */ | |
9716 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
9717 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
9718 | MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); | |
9719 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
9720 | MDIO_AN_REG_8481_1G_100T_EXT_CTRL, | |
9721 | MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); | |
9722 | ||
985848f8 YR |
9723 | shmem_base_path[0] = params->shmem_base; |
9724 | shmem_base_path[1] = other_shmem_base_addr; | |
9725 | ||
9726 | reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, | |
9727 | params->chip_id); | |
9728 | ||
9729 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); | |
9730 | udelay(10); | |
9731 | DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", | |
9732 | reset_gpios); | |
9733 | ||
9734 | return 0; | |
9735 | } | |
9736 | ||
a89a1d4a | 9737 | #define PHY84833_CONSTANT_LATENCY 1193 |
fcf5b650 YR |
9738 | static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, |
9739 | struct link_params *params, | |
9740 | struct link_vars *vars) | |
de6eae1f YR |
9741 | { |
9742 | struct bnx2x *bp = params->bp; | |
6a71bbe0 | 9743 | u8 port, initialize = 1; |
bac27bd9 | 9744 | u16 val; |
521683da YR |
9745 | u32 actual_phy_selection, cms_enable; |
9746 | u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; | |
fcf5b650 | 9747 | int rc = 0; |
7f02c4ad | 9748 | |
de6eae1f | 9749 | msleep(1); |
bac27bd9 YR |
9750 | |
9751 | if (!(CHIP_IS_E1(bp))) | |
6a71bbe0 YR |
9752 | port = BP_PATH(bp); |
9753 | else | |
9754 | port = params->port; | |
bac27bd9 YR |
9755 | |
9756 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
9757 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
9758 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, | |
9759 | port); | |
9760 | } else { | |
985848f8 | 9761 | /* MDIO reset */ |
bac27bd9 YR |
9762 | bnx2x_cl45_write(bp, phy, |
9763 | MDIO_PMA_DEVAD, | |
9764 | MDIO_PMA_REG_CTRL, 0x8000); | |
521683da YR |
9765 | } |
9766 | ||
9767 | bnx2x_wait_reset_complete(bp, phy, params); | |
9768 | ||
9769 | /* Wait for GPHY to come out of reset */ | |
9770 | msleep(50); | |
11b2ec6b | 9771 | if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
8f73f0b9 | 9772 | /* BCM84823 requires that XGXS links up first @ 10G for normal |
521683da YR |
9773 | * behavior. |
9774 | */ | |
9775 | u16 temp; | |
9776 | temp = vars->line_speed; | |
9777 | vars->line_speed = SPEED_10000; | |
9778 | bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); | |
9779 | bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); | |
9780 | vars->line_speed = temp; | |
9781 | } | |
a22f0788 YR |
9782 | |
9783 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, | |
bac27bd9 | 9784 | MDIO_CTL_REG_84823_MEDIA, &val); |
a22f0788 YR |
9785 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | |
9786 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK | | |
9787 | MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | | |
9788 | MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | | |
9789 | MDIO_CTL_REG_84823_MEDIA_FIBER_1G); | |
0d40f0d4 YR |
9790 | |
9791 | if (CHIP_IS_E3(bp)) { | |
9792 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | | |
9793 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK); | |
9794 | } else { | |
9795 | val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | | |
9796 | MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); | |
9797 | } | |
a22f0788 YR |
9798 | |
9799 | actual_phy_selection = bnx2x_phy_selection(params); | |
9800 | ||
9801 | switch (actual_phy_selection) { | |
9802 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
25985edc | 9803 | /* Do nothing. Essentially this is like the priority copper */ |
a22f0788 YR |
9804 | break; |
9805 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
9806 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; | |
9807 | break; | |
9808 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
9809 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; | |
9810 | break; | |
9811 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
9812 | /* Do nothing here. The first PHY won't be initialized at all */ | |
9813 | break; | |
9814 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
9815 | val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; | |
9816 | initialize = 0; | |
9817 | break; | |
9818 | } | |
9819 | if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) | |
9820 | val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; | |
9821 | ||
9822 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
bac27bd9 | 9823 | MDIO_CTL_REG_84823_MEDIA, val); |
a22f0788 YR |
9824 | DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", |
9825 | params->multi_phy_config, val); | |
9826 | ||
11b2ec6b YR |
9827 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
9828 | bnx2x_84833_pair_swap_cfg(phy, params, vars); | |
a89a1d4a | 9829 | |
096b9527 YR |
9830 | /* Keep AutogrEEEn disabled. */ |
9831 | cmd_args[0] = 0x0; | |
11b2ec6b YR |
9832 | cmd_args[1] = 0x0; |
9833 | cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; | |
9834 | cmd_args[3] = PHY84833_CONSTANT_LATENCY; | |
9835 | rc = bnx2x_84833_cmd_hdlr(phy, params, | |
9836 | PHY84833_CMD_SET_EEE_MODE, cmd_args); | |
9837 | if (rc != 0) | |
9838 | DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); | |
9839 | } | |
a22f0788 YR |
9840 | if (initialize) |
9841 | rc = bnx2x_848xx_cmn_config_init(phy, params, vars); | |
9842 | else | |
11b2ec6b | 9843 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); |
a89a1d4a YR |
9844 | /* 84833 PHY has a better feature and doesn't need to support this. */ |
9845 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
9846 | cms_enable = REG_RD(bp, params->shmem_base + | |
1bef68e3 YR |
9847 | offsetof(struct shmem_region, |
9848 | dev_info.port_hw_config[params->port].default_cfg)) & | |
9849 | PORT_HW_CFG_ENABLE_CMS_MASK; | |
9850 | ||
a89a1d4a YR |
9851 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
9852 | MDIO_CTL_REG_84823_USER_CTRL_REG, &val); | |
9853 | if (cms_enable) | |
9854 | val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; | |
9855 | else | |
9856 | val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; | |
9857 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
9858 | MDIO_CTL_REG_84823_USER_CTRL_REG, val); | |
9859 | } | |
1bef68e3 | 9860 | |
11b2ec6b YR |
9861 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
9862 | /* Bring PHY out of super isolate mode as the final step. */ | |
9863 | bnx2x_cl45_read(bp, phy, | |
9864 | MDIO_CTL_DEVAD, | |
9865 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); | |
9866 | val &= ~MDIO_84833_SUPER_ISOLATE; | |
9867 | bnx2x_cl45_write(bp, phy, | |
9868 | MDIO_CTL_DEVAD, | |
9869 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); | |
9870 | } | |
a22f0788 | 9871 | return rc; |
de6eae1f | 9872 | } |
ea4e040a | 9873 | |
de6eae1f | 9874 | static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, |
cd88ccee YR |
9875 | struct link_params *params, |
9876 | struct link_vars *vars) | |
de6eae1f YR |
9877 | { |
9878 | struct bnx2x *bp = params->bp; | |
bac27bd9 | 9879 | u16 val, val1, val2; |
de6eae1f | 9880 | u8 link_up = 0; |
ea4e040a | 9881 | |
c87bca1e | 9882 | |
de6eae1f YR |
9883 | /* Check 10G-BaseT link status */ |
9884 | /* Check PMD signal ok */ | |
9885 | bnx2x_cl45_read(bp, phy, | |
9886 | MDIO_AN_DEVAD, 0xFFFA, &val1); | |
9887 | bnx2x_cl45_read(bp, phy, | |
bac27bd9 | 9888 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, |
de6eae1f YR |
9889 | &val2); |
9890 | DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); | |
ea4e040a | 9891 | |
de6eae1f YR |
9892 | /* Check link 10G */ |
9893 | if (val2 & (1<<11)) { | |
ea4e040a | 9894 | vars->line_speed = SPEED_10000; |
791f18c0 | 9895 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
9896 | link_up = 1; |
9897 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
9898 | } else { /* Check Legacy speed link */ | |
9899 | u16 legacy_status, legacy_speed; | |
ea4e040a | 9900 | |
de6eae1f YR |
9901 | /* Enable expansion register 0x42 (Operation mode status) */ |
9902 | bnx2x_cl45_write(bp, phy, | |
9903 | MDIO_AN_DEVAD, | |
9904 | MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); | |
ea4e040a | 9905 | |
de6eae1f YR |
9906 | /* Get legacy speed operation status */ |
9907 | bnx2x_cl45_read(bp, phy, | |
9908 | MDIO_AN_DEVAD, | |
9909 | MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, | |
9910 | &legacy_status); | |
ea4e040a | 9911 | |
94f05b0f JP |
9912 | DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", |
9913 | legacy_status); | |
de6eae1f YR |
9914 | link_up = ((legacy_status & (1<<11)) == (1<<11)); |
9915 | if (link_up) { | |
9916 | legacy_speed = (legacy_status & (3<<9)); | |
9917 | if (legacy_speed == (0<<9)) | |
9918 | vars->line_speed = SPEED_10; | |
9919 | else if (legacy_speed == (1<<9)) | |
9920 | vars->line_speed = SPEED_100; | |
9921 | else if (legacy_speed == (2<<9)) | |
9922 | vars->line_speed = SPEED_1000; | |
9923 | else /* Should not happen */ | |
9924 | vars->line_speed = 0; | |
ea4e040a | 9925 | |
de6eae1f YR |
9926 | if (legacy_status & (1<<8)) |
9927 | vars->duplex = DUPLEX_FULL; | |
9928 | else | |
9929 | vars->duplex = DUPLEX_HALF; | |
ea4e040a | 9930 | |
94f05b0f JP |
9931 | DP(NETIF_MSG_LINK, |
9932 | "Link is up in %dMbps, is_duplex_full= %d\n", | |
9933 | vars->line_speed, | |
9934 | (vars->duplex == DUPLEX_FULL)); | |
de6eae1f YR |
9935 | /* Check legacy speed AN resolution */ |
9936 | bnx2x_cl45_read(bp, phy, | |
9937 | MDIO_AN_DEVAD, | |
9938 | MDIO_AN_REG_8481_LEGACY_MII_STATUS, | |
9939 | &val); | |
9940 | if (val & (1<<5)) | |
9941 | vars->link_status |= | |
9942 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
9943 | bnx2x_cl45_read(bp, phy, | |
9944 | MDIO_AN_DEVAD, | |
9945 | MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, | |
9946 | &val); | |
9947 | if ((val & (1<<0)) == 0) | |
9948 | vars->link_status |= | |
9949 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
ea4e040a | 9950 | } |
ea4e040a | 9951 | } |
de6eae1f YR |
9952 | if (link_up) { |
9953 | DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n", | |
9954 | vars->line_speed); | |
9955 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
9e7e8399 MY |
9956 | |
9957 | /* Read LP advertised speeds */ | |
9958 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
9959 | MDIO_AN_REG_CL37_FC_LP, &val); | |
9960 | if (val & (1<<5)) | |
9961 | vars->link_status |= | |
9962 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; | |
9963 | if (val & (1<<6)) | |
9964 | vars->link_status |= | |
9965 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; | |
9966 | if (val & (1<<7)) | |
9967 | vars->link_status |= | |
9968 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; | |
9969 | if (val & (1<<8)) | |
9970 | vars->link_status |= | |
9971 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; | |
9972 | if (val & (1<<9)) | |
9973 | vars->link_status |= | |
9974 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; | |
9975 | ||
9976 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
9977 | MDIO_AN_REG_1000T_STATUS, &val); | |
9978 | ||
9979 | if (val & (1<<10)) | |
9980 | vars->link_status |= | |
9981 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; | |
9982 | if (val & (1<<11)) | |
9983 | vars->link_status |= | |
9984 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
9985 | ||
9986 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
9987 | MDIO_AN_REG_MASTER_STATUS, &val); | |
9988 | ||
9989 | if (val & (1<<11)) | |
9990 | vars->link_status |= | |
9991 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
de6eae1f | 9992 | } |
589abe3a | 9993 | |
de6eae1f | 9994 | return link_up; |
b7737c9b YR |
9995 | } |
9996 | ||
fcf5b650 YR |
9997 | |
9998 | static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) | |
b7737c9b | 9999 | { |
fcf5b650 | 10000 | int status = 0; |
de6eae1f YR |
10001 | u32 spirom_ver; |
10002 | spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); | |
10003 | status = bnx2x_format_ver(spirom_ver, str, len); | |
10004 | return status; | |
b7737c9b | 10005 | } |
de6eae1f YR |
10006 | |
10007 | static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, | |
10008 | struct link_params *params) | |
b7737c9b | 10009 | { |
de6eae1f | 10010 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 10011 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); |
de6eae1f | 10012 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 10013 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); |
b7737c9b | 10014 | } |
de6eae1f | 10015 | |
b7737c9b YR |
10016 | static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, |
10017 | struct link_params *params) | |
10018 | { | |
10019 | bnx2x_cl45_write(params->bp, phy, | |
10020 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
10021 | bnx2x_cl45_write(params->bp, phy, | |
10022 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); | |
10023 | } | |
10024 | ||
10025 | static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, | |
10026 | struct link_params *params) | |
10027 | { | |
10028 | struct bnx2x *bp = params->bp; | |
6a71bbe0 | 10029 | u8 port; |
0d40f0d4 | 10030 | u16 val16; |
bac27bd9 | 10031 | |
f93fb016 | 10032 | if (!(CHIP_IS_E1x(bp))) |
6a71bbe0 YR |
10033 | port = BP_PATH(bp); |
10034 | else | |
10035 | port = params->port; | |
bac27bd9 YR |
10036 | |
10037 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
10038 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
10039 | MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
10040 | port); | |
10041 | } else { | |
0d40f0d4 YR |
10042 | bnx2x_cl45_read(bp, phy, |
10043 | MDIO_CTL_DEVAD, | |
11b2ec6b YR |
10044 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); |
10045 | val16 |= MDIO_84833_SUPER_ISOLATE; | |
fd38f73e | 10046 | bnx2x_cl45_write(bp, phy, |
11b2ec6b YR |
10047 | MDIO_CTL_DEVAD, |
10048 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); | |
bac27bd9 | 10049 | } |
b7737c9b YR |
10050 | } |
10051 | ||
7f02c4ad YR |
10052 | static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, |
10053 | struct link_params *params, u8 mode) | |
10054 | { | |
10055 | struct bnx2x *bp = params->bp; | |
10056 | u16 val; | |
bac27bd9 YR |
10057 | u8 port; |
10058 | ||
f93fb016 | 10059 | if (!(CHIP_IS_E1x(bp))) |
bac27bd9 YR |
10060 | port = BP_PATH(bp); |
10061 | else | |
10062 | port = params->port; | |
7f02c4ad YR |
10063 | |
10064 | switch (mode) { | |
10065 | case LED_MODE_OFF: | |
10066 | ||
bac27bd9 | 10067 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); |
7f02c4ad YR |
10068 | |
10069 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10070 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10071 | ||
10072 | /* Set LED masks */ | |
10073 | bnx2x_cl45_write(bp, phy, | |
10074 | MDIO_PMA_DEVAD, | |
10075 | MDIO_PMA_REG_8481_LED1_MASK, | |
10076 | 0x0); | |
10077 | ||
10078 | bnx2x_cl45_write(bp, phy, | |
10079 | MDIO_PMA_DEVAD, | |
10080 | MDIO_PMA_REG_8481_LED2_MASK, | |
10081 | 0x0); | |
10082 | ||
10083 | bnx2x_cl45_write(bp, phy, | |
10084 | MDIO_PMA_DEVAD, | |
10085 | MDIO_PMA_REG_8481_LED3_MASK, | |
10086 | 0x0); | |
10087 | ||
10088 | bnx2x_cl45_write(bp, phy, | |
10089 | MDIO_PMA_DEVAD, | |
10090 | MDIO_PMA_REG_8481_LED5_MASK, | |
10091 | 0x0); | |
10092 | ||
10093 | } else { | |
10094 | bnx2x_cl45_write(bp, phy, | |
10095 | MDIO_PMA_DEVAD, | |
10096 | MDIO_PMA_REG_8481_LED1_MASK, | |
10097 | 0x0); | |
10098 | } | |
10099 | break; | |
10100 | case LED_MODE_FRONT_PANEL_OFF: | |
10101 | ||
10102 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", | |
bac27bd9 | 10103 | port); |
7f02c4ad YR |
10104 | |
10105 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10106 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10107 | ||
10108 | /* Set LED masks */ | |
10109 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10110 | MDIO_PMA_DEVAD, |
10111 | MDIO_PMA_REG_8481_LED1_MASK, | |
10112 | 0x0); | |
7f02c4ad YR |
10113 | |
10114 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10115 | MDIO_PMA_DEVAD, |
10116 | MDIO_PMA_REG_8481_LED2_MASK, | |
10117 | 0x0); | |
7f02c4ad YR |
10118 | |
10119 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10120 | MDIO_PMA_DEVAD, |
10121 | MDIO_PMA_REG_8481_LED3_MASK, | |
10122 | 0x0); | |
7f02c4ad YR |
10123 | |
10124 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10125 | MDIO_PMA_DEVAD, |
10126 | MDIO_PMA_REG_8481_LED5_MASK, | |
10127 | 0x20); | |
7f02c4ad YR |
10128 | |
10129 | } else { | |
10130 | bnx2x_cl45_write(bp, phy, | |
10131 | MDIO_PMA_DEVAD, | |
10132 | MDIO_PMA_REG_8481_LED1_MASK, | |
10133 | 0x0); | |
10134 | } | |
10135 | break; | |
10136 | case LED_MODE_ON: | |
10137 | ||
bac27bd9 | 10138 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); |
7f02c4ad YR |
10139 | |
10140 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10141 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10142 | /* Set control reg */ | |
10143 | bnx2x_cl45_read(bp, phy, | |
10144 | MDIO_PMA_DEVAD, | |
10145 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10146 | &val); | |
10147 | val &= 0x8000; | |
10148 | val |= 0x2492; | |
10149 | ||
10150 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10151 | MDIO_PMA_DEVAD, |
10152 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10153 | val); | |
7f02c4ad YR |
10154 | |
10155 | /* Set LED masks */ | |
10156 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10157 | MDIO_PMA_DEVAD, |
10158 | MDIO_PMA_REG_8481_LED1_MASK, | |
10159 | 0x0); | |
7f02c4ad YR |
10160 | |
10161 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10162 | MDIO_PMA_DEVAD, |
10163 | MDIO_PMA_REG_8481_LED2_MASK, | |
10164 | 0x20); | |
7f02c4ad YR |
10165 | |
10166 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10167 | MDIO_PMA_DEVAD, |
10168 | MDIO_PMA_REG_8481_LED3_MASK, | |
10169 | 0x20); | |
7f02c4ad YR |
10170 | |
10171 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10172 | MDIO_PMA_DEVAD, |
10173 | MDIO_PMA_REG_8481_LED5_MASK, | |
10174 | 0x0); | |
7f02c4ad YR |
10175 | } else { |
10176 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10177 | MDIO_PMA_DEVAD, |
10178 | MDIO_PMA_REG_8481_LED1_MASK, | |
10179 | 0x20); | |
7f02c4ad YR |
10180 | } |
10181 | break; | |
10182 | ||
10183 | case LED_MODE_OPER: | |
10184 | ||
bac27bd9 | 10185 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); |
7f02c4ad YR |
10186 | |
10187 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10188 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10189 | ||
10190 | /* Set control reg */ | |
10191 | bnx2x_cl45_read(bp, phy, | |
10192 | MDIO_PMA_DEVAD, | |
10193 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10194 | &val); | |
10195 | ||
10196 | if (!((val & | |
cd88ccee YR |
10197 | MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) |
10198 | >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { | |
2cf7acf9 | 10199 | DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); |
7f02c4ad YR |
10200 | bnx2x_cl45_write(bp, phy, |
10201 | MDIO_PMA_DEVAD, | |
10202 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10203 | 0xa492); | |
10204 | } | |
10205 | ||
10206 | /* Set LED masks */ | |
10207 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10208 | MDIO_PMA_DEVAD, |
10209 | MDIO_PMA_REG_8481_LED1_MASK, | |
10210 | 0x10); | |
7f02c4ad YR |
10211 | |
10212 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10213 | MDIO_PMA_DEVAD, |
10214 | MDIO_PMA_REG_8481_LED2_MASK, | |
10215 | 0x80); | |
7f02c4ad YR |
10216 | |
10217 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10218 | MDIO_PMA_DEVAD, |
10219 | MDIO_PMA_REG_8481_LED3_MASK, | |
10220 | 0x98); | |
7f02c4ad YR |
10221 | |
10222 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10223 | MDIO_PMA_DEVAD, |
10224 | MDIO_PMA_REG_8481_LED5_MASK, | |
10225 | 0x40); | |
7f02c4ad YR |
10226 | |
10227 | } else { | |
10228 | bnx2x_cl45_write(bp, phy, | |
10229 | MDIO_PMA_DEVAD, | |
10230 | MDIO_PMA_REG_8481_LED1_MASK, | |
10231 | 0x80); | |
53eda06d YR |
10232 | |
10233 | /* Tell LED3 to blink on source */ | |
10234 | bnx2x_cl45_read(bp, phy, | |
10235 | MDIO_PMA_DEVAD, | |
10236 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10237 | &val); | |
10238 | val &= ~(7<<6); | |
10239 | val |= (1<<6); /* A83B[8:6]= 1 */ | |
10240 | bnx2x_cl45_write(bp, phy, | |
10241 | MDIO_PMA_DEVAD, | |
10242 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10243 | val); | |
7f02c4ad YR |
10244 | } |
10245 | break; | |
10246 | } | |
0d40f0d4 | 10247 | |
8f73f0b9 | 10248 | /* This is a workaround for E3+84833 until autoneg |
0d40f0d4 YR |
10249 | * restart is fixed in f/w |
10250 | */ | |
10251 | if (CHIP_IS_E3(bp)) { | |
10252 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
10253 | MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); | |
10254 | } | |
7f02c4ad | 10255 | } |
0d40f0d4 | 10256 | |
6583e33b | 10257 | /******************************************************************/ |
52c4d6c4 | 10258 | /* 54618SE PHY SECTION */ |
6583e33b | 10259 | /******************************************************************/ |
52c4d6c4 | 10260 | static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, |
6583e33b YR |
10261 | struct link_params *params, |
10262 | struct link_vars *vars) | |
10263 | { | |
10264 | struct bnx2x *bp = params->bp; | |
10265 | u8 port; | |
10266 | u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; | |
10267 | u32 cfg_pin; | |
10268 | ||
52c4d6c4 | 10269 | DP(NETIF_MSG_LINK, "54618SE cfg init\n"); |
6583e33b YR |
10270 | usleep_range(1000, 1000); |
10271 | ||
8f73f0b9 | 10272 | /* This works with E3 only, no need to check the chip |
2f751a80 YR |
10273 | * before determining the port. |
10274 | */ | |
6583e33b YR |
10275 | port = params->port; |
10276 | ||
10277 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
10278 | offsetof(struct shmem_region, | |
10279 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
10280 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10281 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10282 | ||
10283 | /* Drive pin high to bring the GPHY out of reset. */ | |
10284 | bnx2x_set_cfg_pin(bp, cfg_pin, 1); | |
10285 | ||
10286 | /* wait for GPHY to reset */ | |
10287 | msleep(50); | |
10288 | ||
10289 | /* reset phy */ | |
10290 | bnx2x_cl22_write(bp, phy, | |
10291 | MDIO_PMA_REG_CTRL, 0x8000); | |
10292 | bnx2x_wait_reset_complete(bp, phy, params); | |
10293 | ||
8f73f0b9 | 10294 | /* Wait for GPHY to reset */ |
6583e33b YR |
10295 | msleep(50); |
10296 | ||
10297 | /* Configure LED4: set to INTR (0x6). */ | |
10298 | /* Accessing shadow register 0xe. */ | |
10299 | bnx2x_cl22_write(bp, phy, | |
10300 | MDIO_REG_GPHY_SHADOW, | |
10301 | MDIO_REG_GPHY_SHADOW_LED_SEL2); | |
10302 | bnx2x_cl22_read(bp, phy, | |
10303 | MDIO_REG_GPHY_SHADOW, | |
10304 | &temp); | |
10305 | temp &= ~(0xf << 4); | |
10306 | temp |= (0x6 << 4); | |
10307 | bnx2x_cl22_write(bp, phy, | |
10308 | MDIO_REG_GPHY_SHADOW, | |
10309 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10310 | /* Configure INTR based on link status change. */ | |
10311 | bnx2x_cl22_write(bp, phy, | |
10312 | MDIO_REG_INTR_MASK, | |
10313 | ~MDIO_REG_INTR_MASK_LINK_STATUS); | |
10314 | ||
10315 | /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ | |
10316 | bnx2x_cl22_write(bp, phy, | |
10317 | MDIO_REG_GPHY_SHADOW, | |
10318 | MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); | |
10319 | bnx2x_cl22_read(bp, phy, | |
10320 | MDIO_REG_GPHY_SHADOW, | |
10321 | &temp); | |
10322 | temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; | |
10323 | bnx2x_cl22_write(bp, phy, | |
10324 | MDIO_REG_GPHY_SHADOW, | |
10325 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10326 | ||
10327 | /* Set up fc */ | |
10328 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
10329 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
10330 | fc_val = 0; | |
10331 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
10332 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) | |
10333 | fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
10334 | ||
10335 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
10336 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
10337 | fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
10338 | ||
10339 | /* read all advertisement */ | |
10340 | bnx2x_cl22_read(bp, phy, | |
10341 | 0x09, | |
10342 | &an_1000_val); | |
10343 | ||
10344 | bnx2x_cl22_read(bp, phy, | |
10345 | 0x04, | |
10346 | &an_10_100_val); | |
10347 | ||
10348 | bnx2x_cl22_read(bp, phy, | |
10349 | MDIO_PMA_REG_CTRL, | |
10350 | &autoneg_val); | |
10351 | ||
10352 | /* Disable forced speed */ | |
10353 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); | |
10354 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | | |
10355 | (1<<11)); | |
10356 | ||
10357 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
10358 | (phy->speed_cap_mask & | |
10359 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
10360 | (phy->req_line_speed == SPEED_1000)) { | |
10361 | an_1000_val |= (1<<8); | |
10362 | autoneg_val |= (1<<9 | 1<<12); | |
10363 | if (phy->req_duplex == DUPLEX_FULL) | |
10364 | an_1000_val |= (1<<9); | |
10365 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); | |
10366 | } else | |
10367 | an_1000_val &= ~((1<<8) | (1<<9)); | |
10368 | ||
10369 | bnx2x_cl22_write(bp, phy, | |
10370 | 0x09, | |
10371 | an_1000_val); | |
10372 | bnx2x_cl22_read(bp, phy, | |
10373 | 0x09, | |
10374 | &an_1000_val); | |
10375 | ||
10376 | /* set 100 speed advertisement */ | |
10377 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
10378 | (phy->speed_cap_mask & | |
10379 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | | |
10380 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) { | |
10381 | an_10_100_val |= (1<<7); | |
10382 | /* Enable autoneg and restart autoneg for legacy speeds */ | |
10383 | autoneg_val |= (1<<9 | 1<<12); | |
10384 | ||
10385 | if (phy->req_duplex == DUPLEX_FULL) | |
10386 | an_10_100_val |= (1<<8); | |
10387 | DP(NETIF_MSG_LINK, "Advertising 100M\n"); | |
10388 | } | |
10389 | ||
10390 | /* set 10 speed advertisement */ | |
10391 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
10392 | (phy->speed_cap_mask & | |
10393 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | | |
10394 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) { | |
10395 | an_10_100_val |= (1<<5); | |
10396 | autoneg_val |= (1<<9 | 1<<12); | |
10397 | if (phy->req_duplex == DUPLEX_FULL) | |
10398 | an_10_100_val |= (1<<6); | |
10399 | DP(NETIF_MSG_LINK, "Advertising 10M\n"); | |
10400 | } | |
10401 | ||
10402 | /* Only 10/100 are allowed to work in FORCE mode */ | |
10403 | if (phy->req_line_speed == SPEED_100) { | |
10404 | autoneg_val |= (1<<13); | |
10405 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
10406 | bnx2x_cl22_write(bp, phy, | |
10407 | 0x18, | |
10408 | (1<<15 | 1<<9 | 7<<0)); | |
10409 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); | |
10410 | } | |
10411 | if (phy->req_line_speed == SPEED_10) { | |
10412 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
10413 | bnx2x_cl22_write(bp, phy, | |
10414 | 0x18, | |
10415 | (1<<15 | 1<<9 | 7<<0)); | |
10416 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); | |
10417 | } | |
10418 | ||
a89a1d4a YR |
10419 | /* Check if we should turn on Auto-GrEEEn */ |
10420 | bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp); | |
10421 | if (temp == MDIO_REG_GPHY_ID_54618SE) { | |
10422 | if (params->feature_config_flags & | |
10423 | FEATURE_CONFIG_AUTOGREEEN_ENABLED) { | |
10424 | temp = 6; | |
10425 | DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); | |
10426 | } else { | |
10427 | temp = 0; | |
10428 | DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n"); | |
10429 | } | |
10430 | bnx2x_cl22_write(bp, phy, | |
10431 | MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD); | |
10432 | bnx2x_cl22_write(bp, phy, | |
10433 | MDIO_REG_GPHY_CL45_DATA_REG, | |
10434 | MDIO_REG_GPHY_EEE_ADV); | |
10435 | bnx2x_cl22_write(bp, phy, | |
10436 | MDIO_REG_GPHY_CL45_ADDR_REG, | |
10437 | (0x1 << 14) | MDIO_AN_DEVAD); | |
10438 | bnx2x_cl22_write(bp, phy, | |
10439 | MDIO_REG_GPHY_CL45_DATA_REG, | |
10440 | temp); | |
10441 | } | |
10442 | ||
6583e33b YR |
10443 | bnx2x_cl22_write(bp, phy, |
10444 | 0x04, | |
10445 | an_10_100_val | fc_val); | |
10446 | ||
10447 | if (phy->req_duplex == DUPLEX_FULL) | |
10448 | autoneg_val |= (1<<8); | |
10449 | ||
10450 | bnx2x_cl22_write(bp, phy, | |
10451 | MDIO_PMA_REG_CTRL, autoneg_val); | |
10452 | ||
10453 | return 0; | |
10454 | } | |
10455 | ||
1d125bd5 YR |
10456 | |
10457 | static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, | |
10458 | struct link_params *params, u8 mode) | |
10459 | { | |
10460 | struct bnx2x *bp = params->bp; | |
10461 | u16 temp; | |
10462 | ||
10463 | bnx2x_cl22_write(bp, phy, | |
10464 | MDIO_REG_GPHY_SHADOW, | |
10465 | MDIO_REG_GPHY_SHADOW_LED_SEL1); | |
10466 | bnx2x_cl22_read(bp, phy, | |
10467 | MDIO_REG_GPHY_SHADOW, | |
10468 | &temp); | |
10469 | temp &= 0xff00; | |
10470 | ||
10471 | DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); | |
10472 | switch (mode) { | |
10473 | case LED_MODE_FRONT_PANEL_OFF: | |
10474 | case LED_MODE_OFF: | |
10475 | temp |= 0x00ee; | |
10476 | break; | |
10477 | case LED_MODE_OPER: | |
10478 | temp |= 0x0001; | |
10479 | break; | |
10480 | case LED_MODE_ON: | |
10481 | temp |= 0x00ff; | |
10482 | break; | |
10483 | default: | |
10484 | break; | |
10485 | } | |
10486 | bnx2x_cl22_write(bp, phy, | |
10487 | MDIO_REG_GPHY_SHADOW, | |
10488 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10489 | return; | |
10490 | } | |
10491 | ||
10492 | ||
52c4d6c4 YR |
10493 | static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, |
10494 | struct link_params *params) | |
6583e33b YR |
10495 | { |
10496 | struct bnx2x *bp = params->bp; | |
10497 | u32 cfg_pin; | |
10498 | u8 port; | |
10499 | ||
8f73f0b9 | 10500 | /* In case of no EPIO routed to reset the GPHY, put it |
d2059a06 YR |
10501 | * in low power mode. |
10502 | */ | |
10503 | bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); | |
8f73f0b9 | 10504 | /* This works with E3 only, no need to check the chip |
d2059a06 YR |
10505 | * before determining the port. |
10506 | */ | |
6583e33b YR |
10507 | port = params->port; |
10508 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
10509 | offsetof(struct shmem_region, | |
10510 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
10511 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10512 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10513 | ||
10514 | /* Drive pin low to put GPHY in reset. */ | |
10515 | bnx2x_set_cfg_pin(bp, cfg_pin, 0); | |
10516 | } | |
10517 | ||
52c4d6c4 YR |
10518 | static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, |
10519 | struct link_params *params, | |
10520 | struct link_vars *vars) | |
6583e33b YR |
10521 | { |
10522 | struct bnx2x *bp = params->bp; | |
10523 | u16 val; | |
10524 | u8 link_up = 0; | |
10525 | u16 legacy_status, legacy_speed; | |
10526 | ||
10527 | /* Get speed operation status */ | |
10528 | bnx2x_cl22_read(bp, phy, | |
10529 | 0x19, | |
10530 | &legacy_status); | |
52c4d6c4 | 10531 | DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); |
6583e33b YR |
10532 | |
10533 | /* Read status to clear the PHY interrupt. */ | |
10534 | bnx2x_cl22_read(bp, phy, | |
10535 | MDIO_REG_INTR_STATUS, | |
10536 | &val); | |
10537 | ||
10538 | link_up = ((legacy_status & (1<<2)) == (1<<2)); | |
10539 | ||
10540 | if (link_up) { | |
10541 | legacy_speed = (legacy_status & (7<<8)); | |
10542 | if (legacy_speed == (7<<8)) { | |
10543 | vars->line_speed = SPEED_1000; | |
10544 | vars->duplex = DUPLEX_FULL; | |
10545 | } else if (legacy_speed == (6<<8)) { | |
10546 | vars->line_speed = SPEED_1000; | |
10547 | vars->duplex = DUPLEX_HALF; | |
10548 | } else if (legacy_speed == (5<<8)) { | |
10549 | vars->line_speed = SPEED_100; | |
10550 | vars->duplex = DUPLEX_FULL; | |
10551 | } | |
10552 | /* Omitting 100Base-T4 for now */ | |
10553 | else if (legacy_speed == (3<<8)) { | |
10554 | vars->line_speed = SPEED_100; | |
10555 | vars->duplex = DUPLEX_HALF; | |
10556 | } else if (legacy_speed == (2<<8)) { | |
10557 | vars->line_speed = SPEED_10; | |
10558 | vars->duplex = DUPLEX_FULL; | |
10559 | } else if (legacy_speed == (1<<8)) { | |
10560 | vars->line_speed = SPEED_10; | |
10561 | vars->duplex = DUPLEX_HALF; | |
10562 | } else /* Should not happen */ | |
10563 | vars->line_speed = 0; | |
10564 | ||
94f05b0f JP |
10565 | DP(NETIF_MSG_LINK, |
10566 | "Link is up in %dMbps, is_duplex_full= %d\n", | |
10567 | vars->line_speed, | |
10568 | (vars->duplex == DUPLEX_FULL)); | |
6583e33b YR |
10569 | |
10570 | /* Check legacy speed AN resolution */ | |
10571 | bnx2x_cl22_read(bp, phy, | |
10572 | 0x01, | |
10573 | &val); | |
10574 | if (val & (1<<5)) | |
10575 | vars->link_status |= | |
10576 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
10577 | bnx2x_cl22_read(bp, phy, | |
10578 | 0x06, | |
10579 | &val); | |
10580 | if ((val & (1<<0)) == 0) | |
10581 | vars->link_status |= | |
10582 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
10583 | ||
52c4d6c4 | 10584 | DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", |
6583e33b | 10585 | vars->line_speed); |
52c4d6c4 YR |
10586 | |
10587 | /* Report whether EEE is resolved. */ | |
10588 | bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val); | |
10589 | if (val == MDIO_REG_GPHY_ID_54618SE) { | |
10590 | if (vars->link_status & | |
10591 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) | |
10592 | val = 0; | |
10593 | else { | |
10594 | bnx2x_cl22_write(bp, phy, | |
10595 | MDIO_REG_GPHY_CL45_ADDR_REG, | |
10596 | MDIO_AN_DEVAD); | |
10597 | bnx2x_cl22_write(bp, phy, | |
10598 | MDIO_REG_GPHY_CL45_DATA_REG, | |
10599 | MDIO_REG_GPHY_EEE_RESOLVED); | |
10600 | bnx2x_cl22_write(bp, phy, | |
10601 | MDIO_REG_GPHY_CL45_ADDR_REG, | |
10602 | (0x1 << 14) | MDIO_AN_DEVAD); | |
10603 | bnx2x_cl22_read(bp, phy, | |
10604 | MDIO_REG_GPHY_CL45_DATA_REG, | |
10605 | &val); | |
10606 | } | |
10607 | DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val); | |
10608 | } | |
10609 | ||
6583e33b | 10610 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
9e7e8399 MY |
10611 | |
10612 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
8f73f0b9 | 10613 | /* Report LP advertised speeds */ |
9e7e8399 MY |
10614 | bnx2x_cl22_read(bp, phy, 0x5, &val); |
10615 | ||
10616 | if (val & (1<<5)) | |
10617 | vars->link_status |= | |
10618 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; | |
10619 | if (val & (1<<6)) | |
10620 | vars->link_status |= | |
10621 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; | |
10622 | if (val & (1<<7)) | |
10623 | vars->link_status |= | |
10624 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; | |
10625 | if (val & (1<<8)) | |
10626 | vars->link_status |= | |
10627 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; | |
10628 | if (val & (1<<9)) | |
10629 | vars->link_status |= | |
10630 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; | |
10631 | ||
10632 | bnx2x_cl22_read(bp, phy, 0xa, &val); | |
10633 | if (val & (1<<10)) | |
10634 | vars->link_status |= | |
10635 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; | |
10636 | if (val & (1<<11)) | |
10637 | vars->link_status |= | |
10638 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
10639 | } | |
6583e33b YR |
10640 | } |
10641 | return link_up; | |
10642 | } | |
10643 | ||
52c4d6c4 YR |
10644 | static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, |
10645 | struct link_params *params) | |
6583e33b YR |
10646 | { |
10647 | struct bnx2x *bp = params->bp; | |
10648 | u16 val; | |
10649 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
10650 | ||
52c4d6c4 | 10651 | DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); |
6583e33b YR |
10652 | |
10653 | /* Enable master/slave manual mmode and set to master */ | |
10654 | /* mii write 9 [bits set 11 12] */ | |
10655 | bnx2x_cl22_write(bp, phy, 0x09, 3<<11); | |
10656 | ||
10657 | /* forced 1G and disable autoneg */ | |
10658 | /* set val [mii read 0] */ | |
10659 | /* set val [expr $val & [bits clear 6 12 13]] */ | |
10660 | /* set val [expr $val | [bits set 6 8]] */ | |
10661 | /* mii write 0 $val */ | |
10662 | bnx2x_cl22_read(bp, phy, 0x00, &val); | |
10663 | val &= ~((1<<6) | (1<<12) | (1<<13)); | |
10664 | val |= (1<<6) | (1<<8); | |
10665 | bnx2x_cl22_write(bp, phy, 0x00, val); | |
10666 | ||
10667 | /* Set external loopback and Tx using 6dB coding */ | |
10668 | /* mii write 0x18 7 */ | |
10669 | /* set val [mii read 0x18] */ | |
10670 | /* mii write 0x18 [expr $val | [bits set 10 15]] */ | |
10671 | bnx2x_cl22_write(bp, phy, 0x18, 7); | |
10672 | bnx2x_cl22_read(bp, phy, 0x18, &val); | |
10673 | bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); | |
10674 | ||
10675 | /* This register opens the gate for the UMAC despite its name */ | |
10676 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); | |
10677 | ||
8f73f0b9 | 10678 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame |
6583e33b YR |
10679 | * length used by the MAC receive logic to check frames. |
10680 | */ | |
10681 | REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); | |
10682 | } | |
10683 | ||
de6eae1f YR |
10684 | /******************************************************************/ |
10685 | /* SFX7101 PHY SECTION */ | |
10686 | /******************************************************************/ | |
10687 | static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, | |
10688 | struct link_params *params) | |
b7737c9b YR |
10689 | { |
10690 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
10691 | /* SFX7101_XGXS_TEST1 */ |
10692 | bnx2x_cl45_write(bp, phy, | |
10693 | MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); | |
589abe3a EG |
10694 | } |
10695 | ||
fcf5b650 YR |
10696 | static int bnx2x_7101_config_init(struct bnx2x_phy *phy, |
10697 | struct link_params *params, | |
10698 | struct link_vars *vars) | |
ea4e040a | 10699 | { |
de6eae1f | 10700 | u16 fw_ver1, fw_ver2, val; |
ea4e040a | 10701 | struct bnx2x *bp = params->bp; |
de6eae1f | 10702 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); |
ea4e040a | 10703 | |
de6eae1f YR |
10704 | /* Restore normal power mode*/ |
10705 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 10706 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
10707 | /* HW reset */ |
10708 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
6d870c39 | 10709 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 10710 | |
de6eae1f | 10711 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 10712 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); |
de6eae1f YR |
10713 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); |
10714 | bnx2x_cl45_write(bp, phy, | |
10715 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); | |
ea4e040a | 10716 | |
de6eae1f YR |
10717 | bnx2x_ext_phy_set_pause(params, phy, vars); |
10718 | /* Restart autoneg */ | |
10719 | bnx2x_cl45_read(bp, phy, | |
10720 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); | |
10721 | val |= 0x200; | |
10722 | bnx2x_cl45_write(bp, phy, | |
10723 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); | |
ea4e040a | 10724 | |
de6eae1f YR |
10725 | /* Save spirom version */ |
10726 | bnx2x_cl45_read(bp, phy, | |
10727 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); | |
ea4e040a | 10728 | |
de6eae1f YR |
10729 | bnx2x_cl45_read(bp, phy, |
10730 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); | |
10731 | bnx2x_save_spirom_version(bp, params->port, | |
10732 | (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); | |
10733 | return 0; | |
10734 | } | |
ea4e040a | 10735 | |
de6eae1f YR |
10736 | static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, |
10737 | struct link_params *params, | |
10738 | struct link_vars *vars) | |
57963ed9 YR |
10739 | { |
10740 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
10741 | u8 link_up; |
10742 | u16 val1, val2; | |
10743 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 10744 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); |
de6eae1f | 10745 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 10746 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f YR |
10747 | DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", |
10748 | val2, val1); | |
10749 | bnx2x_cl45_read(bp, phy, | |
10750 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
10751 | bnx2x_cl45_read(bp, phy, | |
10752 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
10753 | DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", | |
10754 | val2, val1); | |
10755 | link_up = ((val1 & 4) == 4); | |
2cf7acf9 | 10756 | /* if link is up print the AN outcome of the SFX7101 PHY */ |
de6eae1f YR |
10757 | if (link_up) { |
10758 | bnx2x_cl45_read(bp, phy, | |
10759 | MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, | |
10760 | &val2); | |
10761 | vars->line_speed = SPEED_10000; | |
791f18c0 | 10762 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
10763 | DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", |
10764 | val2, (val2 & (1<<14))); | |
10765 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
10766 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
9e7e8399 MY |
10767 | |
10768 | /* read LP advertised speeds */ | |
10769 | if (val2 & (1<<11)) | |
10770 | vars->link_status |= | |
10771 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
de6eae1f YR |
10772 | } |
10773 | return link_up; | |
10774 | } | |
6c55c3cd | 10775 | |
fcf5b650 | 10776 | static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
de6eae1f YR |
10777 | { |
10778 | if (*len < 5) | |
10779 | return -EINVAL; | |
10780 | str[0] = (spirom_ver & 0xFF); | |
10781 | str[1] = (spirom_ver & 0xFF00) >> 8; | |
10782 | str[2] = (spirom_ver & 0xFF0000) >> 16; | |
10783 | str[3] = (spirom_ver & 0xFF000000) >> 24; | |
10784 | str[4] = '\0'; | |
10785 | *len -= 5; | |
57963ed9 YR |
10786 | return 0; |
10787 | } | |
10788 | ||
de6eae1f | 10789 | void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) |
57963ed9 | 10790 | { |
de6eae1f | 10791 | u16 val, cnt; |
7aa0711f | 10792 | |
de6eae1f | 10793 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
10794 | MDIO_PMA_DEVAD, |
10795 | MDIO_PMA_REG_7101_RESET, &val); | |
57963ed9 | 10796 | |
de6eae1f YR |
10797 | for (cnt = 0; cnt < 10; cnt++) { |
10798 | msleep(50); | |
10799 | /* Writes a self-clearing reset */ | |
10800 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10801 | MDIO_PMA_DEVAD, |
10802 | MDIO_PMA_REG_7101_RESET, | |
10803 | (val | (1<<15))); | |
de6eae1f YR |
10804 | /* Wait for clear */ |
10805 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
10806 | MDIO_PMA_DEVAD, |
10807 | MDIO_PMA_REG_7101_RESET, &val); | |
0c786f02 | 10808 | |
de6eae1f YR |
10809 | if ((val & (1<<15)) == 0) |
10810 | break; | |
57963ed9 | 10811 | } |
57963ed9 | 10812 | } |
ea4e040a | 10813 | |
de6eae1f YR |
10814 | static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, |
10815 | struct link_params *params) { | |
10816 | /* Low power mode is controlled by GPIO 2 */ | |
10817 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 10818 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
de6eae1f YR |
10819 | /* The PHY reset is controlled by GPIO 1 */ |
10820 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 10821 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
de6eae1f | 10822 | } |
ea4e040a | 10823 | |
7f02c4ad YR |
10824 | static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, |
10825 | struct link_params *params, u8 mode) | |
10826 | { | |
10827 | u16 val = 0; | |
10828 | struct bnx2x *bp = params->bp; | |
10829 | switch (mode) { | |
10830 | case LED_MODE_FRONT_PANEL_OFF: | |
10831 | case LED_MODE_OFF: | |
10832 | val = 2; | |
10833 | break; | |
10834 | case LED_MODE_ON: | |
10835 | val = 1; | |
10836 | break; | |
10837 | case LED_MODE_OPER: | |
10838 | val = 0; | |
10839 | break; | |
10840 | } | |
10841 | bnx2x_cl45_write(bp, phy, | |
10842 | MDIO_PMA_DEVAD, | |
10843 | MDIO_PMA_REG_7107_LINK_LED_CNTL, | |
10844 | val); | |
10845 | } | |
10846 | ||
de6eae1f YR |
10847 | /******************************************************************/ |
10848 | /* STATIC PHY DECLARATION */ | |
10849 | /******************************************************************/ | |
ea4e040a | 10850 | |
de6eae1f YR |
10851 | static struct bnx2x_phy phy_null = { |
10852 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, | |
10853 | .addr = 0, | |
de6eae1f | 10854 | .def_md_devad = 0, |
9045f6b4 | 10855 | .flags = FLAGS_INIT_XGXS_FIRST, |
de6eae1f YR |
10856 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10857 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10858 | .mdio_ctrl = 0, | |
10859 | .supported = 0, | |
10860 | .media_type = ETH_PHY_NOT_PRESENT, | |
10861 | .ver_addr = 0, | |
cd88ccee YR |
10862 | .req_flow_ctrl = 0, |
10863 | .req_line_speed = 0, | |
10864 | .speed_cap_mask = 0, | |
de6eae1f YR |
10865 | .req_duplex = 0, |
10866 | .rsrv = 0, | |
10867 | .config_init = (config_init_t)NULL, | |
10868 | .read_status = (read_status_t)NULL, | |
10869 | .link_reset = (link_reset_t)NULL, | |
10870 | .config_loopback = (config_loopback_t)NULL, | |
10871 | .format_fw_ver = (format_fw_ver_t)NULL, | |
10872 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
10873 | .set_link_led = (set_link_led_t)NULL, |
10874 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 10875 | }; |
ea4e040a | 10876 | |
de6eae1f YR |
10877 | static struct bnx2x_phy phy_serdes = { |
10878 | .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, | |
10879 | .addr = 0xff, | |
de6eae1f | 10880 | .def_md_devad = 0, |
9045f6b4 | 10881 | .flags = 0, |
de6eae1f YR |
10882 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10883 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10884 | .mdio_ctrl = 0, | |
10885 | .supported = (SUPPORTED_10baseT_Half | | |
10886 | SUPPORTED_10baseT_Full | | |
10887 | SUPPORTED_100baseT_Half | | |
10888 | SUPPORTED_100baseT_Full | | |
10889 | SUPPORTED_1000baseT_Full | | |
10890 | SUPPORTED_2500baseX_Full | | |
10891 | SUPPORTED_TP | | |
10892 | SUPPORTED_Autoneg | | |
10893 | SUPPORTED_Pause | | |
10894 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 10895 | .media_type = ETH_PHY_BASE_T, |
de6eae1f YR |
10896 | .ver_addr = 0, |
10897 | .req_flow_ctrl = 0, | |
cd88ccee YR |
10898 | .req_line_speed = 0, |
10899 | .speed_cap_mask = 0, | |
de6eae1f YR |
10900 | .req_duplex = 0, |
10901 | .rsrv = 0, | |
ec146a6f | 10902 | .config_init = (config_init_t)bnx2x_xgxs_config_init, |
de6eae1f YR |
10903 | .read_status = (read_status_t)bnx2x_link_settings_status, |
10904 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
10905 | .config_loopback = (config_loopback_t)NULL, | |
10906 | .format_fw_ver = (format_fw_ver_t)NULL, | |
10907 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
10908 | .set_link_led = (set_link_led_t)NULL, |
10909 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 10910 | }; |
b7737c9b YR |
10911 | |
10912 | static struct bnx2x_phy phy_xgxs = { | |
10913 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | |
10914 | .addr = 0xff, | |
b7737c9b | 10915 | .def_md_devad = 0, |
9045f6b4 | 10916 | .flags = 0, |
b7737c9b YR |
10917 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10918 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10919 | .mdio_ctrl = 0, | |
10920 | .supported = (SUPPORTED_10baseT_Half | | |
10921 | SUPPORTED_10baseT_Full | | |
10922 | SUPPORTED_100baseT_Half | | |
10923 | SUPPORTED_100baseT_Full | | |
10924 | SUPPORTED_1000baseT_Full | | |
10925 | SUPPORTED_2500baseX_Full | | |
10926 | SUPPORTED_10000baseT_Full | | |
10927 | SUPPORTED_FIBRE | | |
10928 | SUPPORTED_Autoneg | | |
10929 | SUPPORTED_Pause | | |
10930 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 10931 | .media_type = ETH_PHY_CX4, |
b7737c9b YR |
10932 | .ver_addr = 0, |
10933 | .req_flow_ctrl = 0, | |
cd88ccee YR |
10934 | .req_line_speed = 0, |
10935 | .speed_cap_mask = 0, | |
b7737c9b YR |
10936 | .req_duplex = 0, |
10937 | .rsrv = 0, | |
ec146a6f | 10938 | .config_init = (config_init_t)bnx2x_xgxs_config_init, |
b7737c9b YR |
10939 | .read_status = (read_status_t)bnx2x_link_settings_status, |
10940 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
10941 | .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, | |
10942 | .format_fw_ver = (format_fw_ver_t)NULL, | |
10943 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
10944 | .set_link_led = (set_link_led_t)NULL, |
10945 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b | 10946 | }; |
3c9ada22 YR |
10947 | static struct bnx2x_phy phy_warpcore = { |
10948 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | |
10949 | .addr = 0xff, | |
10950 | .def_md_devad = 0, | |
55098c5c YR |
10951 | .flags = (FLAGS_HW_LOCK_REQUIRED | |
10952 | FLAGS_TX_ERROR_CHECK), | |
3c9ada22 YR |
10953 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10954 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10955 | .mdio_ctrl = 0, | |
10956 | .supported = (SUPPORTED_10baseT_Half | | |
8f73f0b9 YR |
10957 | SUPPORTED_10baseT_Full | |
10958 | SUPPORTED_100baseT_Half | | |
10959 | SUPPORTED_100baseT_Full | | |
10960 | SUPPORTED_1000baseT_Full | | |
10961 | SUPPORTED_10000baseT_Full | | |
10962 | SUPPORTED_20000baseKR2_Full | | |
10963 | SUPPORTED_20000baseMLD2_Full | | |
10964 | SUPPORTED_FIBRE | | |
10965 | SUPPORTED_Autoneg | | |
10966 | SUPPORTED_Pause | | |
10967 | SUPPORTED_Asym_Pause), | |
3c9ada22 YR |
10968 | .media_type = ETH_PHY_UNSPECIFIED, |
10969 | .ver_addr = 0, | |
10970 | .req_flow_ctrl = 0, | |
10971 | .req_line_speed = 0, | |
10972 | .speed_cap_mask = 0, | |
10973 | /* req_duplex = */0, | |
10974 | /* rsrv = */0, | |
10975 | .config_init = (config_init_t)bnx2x_warpcore_config_init, | |
10976 | .read_status = (read_status_t)bnx2x_warpcore_read_status, | |
10977 | .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, | |
10978 | .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, | |
10979 | .format_fw_ver = (format_fw_ver_t)NULL, | |
985848f8 | 10980 | .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, |
3c9ada22 YR |
10981 | .set_link_led = (set_link_led_t)NULL, |
10982 | .phy_specific_func = (phy_specific_func_t)NULL | |
10983 | }; | |
10984 | ||
b7737c9b YR |
10985 | |
10986 | static struct bnx2x_phy phy_7101 = { | |
10987 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, | |
10988 | .addr = 0xff, | |
b7737c9b | 10989 | .def_md_devad = 0, |
9045f6b4 | 10990 | .flags = FLAGS_FAN_FAILURE_DET_REQ, |
b7737c9b YR |
10991 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10992 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10993 | .mdio_ctrl = 0, | |
10994 | .supported = (SUPPORTED_10000baseT_Full | | |
10995 | SUPPORTED_TP | | |
10996 | SUPPORTED_Autoneg | | |
10997 | SUPPORTED_Pause | | |
10998 | SUPPORTED_Asym_Pause), | |
10999 | .media_type = ETH_PHY_BASE_T, | |
11000 | .ver_addr = 0, | |
11001 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11002 | .req_line_speed = 0, |
11003 | .speed_cap_mask = 0, | |
b7737c9b YR |
11004 | .req_duplex = 0, |
11005 | .rsrv = 0, | |
11006 | .config_init = (config_init_t)bnx2x_7101_config_init, | |
11007 | .read_status = (read_status_t)bnx2x_7101_read_status, | |
11008 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11009 | .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, | |
11010 | .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, | |
11011 | .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, | |
7f02c4ad | 11012 | .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, |
a22f0788 | 11013 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b YR |
11014 | }; |
11015 | static struct bnx2x_phy phy_8073 = { | |
11016 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, | |
11017 | .addr = 0xff, | |
b7737c9b | 11018 | .def_md_devad = 0, |
9045f6b4 | 11019 | .flags = FLAGS_HW_LOCK_REQUIRED, |
b7737c9b YR |
11020 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11021 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11022 | .mdio_ctrl = 0, | |
11023 | .supported = (SUPPORTED_10000baseT_Full | | |
11024 | SUPPORTED_2500baseX_Full | | |
11025 | SUPPORTED_1000baseT_Full | | |
11026 | SUPPORTED_FIBRE | | |
11027 | SUPPORTED_Autoneg | | |
11028 | SUPPORTED_Pause | | |
11029 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11030 | .media_type = ETH_PHY_KR, |
b7737c9b | 11031 | .ver_addr = 0, |
cd88ccee YR |
11032 | .req_flow_ctrl = 0, |
11033 | .req_line_speed = 0, | |
11034 | .speed_cap_mask = 0, | |
b7737c9b YR |
11035 | .req_duplex = 0, |
11036 | .rsrv = 0, | |
62b29a5d | 11037 | .config_init = (config_init_t)bnx2x_8073_config_init, |
b7737c9b YR |
11038 | .read_status = (read_status_t)bnx2x_8073_read_status, |
11039 | .link_reset = (link_reset_t)bnx2x_8073_link_reset, | |
11040 | .config_loopback = (config_loopback_t)NULL, | |
11041 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11042 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11043 | .set_link_led = (set_link_led_t)NULL, |
11044 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11045 | }; |
11046 | static struct bnx2x_phy phy_8705 = { | |
11047 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, | |
11048 | .addr = 0xff, | |
b7737c9b | 11049 | .def_md_devad = 0, |
9045f6b4 | 11050 | .flags = FLAGS_INIT_XGXS_FIRST, |
b7737c9b YR |
11051 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11052 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11053 | .mdio_ctrl = 0, | |
11054 | .supported = (SUPPORTED_10000baseT_Full | | |
11055 | SUPPORTED_FIBRE | | |
11056 | SUPPORTED_Pause | | |
11057 | SUPPORTED_Asym_Pause), | |
11058 | .media_type = ETH_PHY_XFP_FIBER, | |
11059 | .ver_addr = 0, | |
11060 | .req_flow_ctrl = 0, | |
11061 | .req_line_speed = 0, | |
11062 | .speed_cap_mask = 0, | |
11063 | .req_duplex = 0, | |
11064 | .rsrv = 0, | |
11065 | .config_init = (config_init_t)bnx2x_8705_config_init, | |
11066 | .read_status = (read_status_t)bnx2x_8705_read_status, | |
11067 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11068 | .config_loopback = (config_loopback_t)NULL, | |
11069 | .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, | |
11070 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11071 | .set_link_led = (set_link_led_t)NULL, |
11072 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11073 | }; |
11074 | static struct bnx2x_phy phy_8706 = { | |
11075 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, | |
11076 | .addr = 0xff, | |
b7737c9b | 11077 | .def_md_devad = 0, |
05822420 | 11078 | .flags = FLAGS_INIT_XGXS_FIRST, |
b7737c9b YR |
11079 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11080 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11081 | .mdio_ctrl = 0, | |
11082 | .supported = (SUPPORTED_10000baseT_Full | | |
11083 | SUPPORTED_1000baseT_Full | | |
11084 | SUPPORTED_FIBRE | | |
11085 | SUPPORTED_Pause | | |
11086 | SUPPORTED_Asym_Pause), | |
11087 | .media_type = ETH_PHY_SFP_FIBER, | |
11088 | .ver_addr = 0, | |
11089 | .req_flow_ctrl = 0, | |
11090 | .req_line_speed = 0, | |
11091 | .speed_cap_mask = 0, | |
11092 | .req_duplex = 0, | |
11093 | .rsrv = 0, | |
11094 | .config_init = (config_init_t)bnx2x_8706_config_init, | |
11095 | .read_status = (read_status_t)bnx2x_8706_read_status, | |
11096 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11097 | .config_loopback = (config_loopback_t)NULL, | |
11098 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11099 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11100 | .set_link_led = (set_link_led_t)NULL, |
11101 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11102 | }; |
11103 | ||
11104 | static struct bnx2x_phy phy_8726 = { | |
11105 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, | |
11106 | .addr = 0xff, | |
9045f6b4 | 11107 | .def_md_devad = 0, |
b7737c9b | 11108 | .flags = (FLAGS_HW_LOCK_REQUIRED | |
55098c5c YR |
11109 | FLAGS_INIT_XGXS_FIRST | |
11110 | FLAGS_TX_ERROR_CHECK), | |
b7737c9b YR |
11111 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11112 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11113 | .mdio_ctrl = 0, | |
11114 | .supported = (SUPPORTED_10000baseT_Full | | |
11115 | SUPPORTED_1000baseT_Full | | |
11116 | SUPPORTED_Autoneg | | |
11117 | SUPPORTED_FIBRE | | |
11118 | SUPPORTED_Pause | | |
11119 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11120 | .media_type = ETH_PHY_NOT_PRESENT, |
b7737c9b YR |
11121 | .ver_addr = 0, |
11122 | .req_flow_ctrl = 0, | |
11123 | .req_line_speed = 0, | |
11124 | .speed_cap_mask = 0, | |
11125 | .req_duplex = 0, | |
11126 | .rsrv = 0, | |
11127 | .config_init = (config_init_t)bnx2x_8726_config_init, | |
11128 | .read_status = (read_status_t)bnx2x_8726_read_status, | |
11129 | .link_reset = (link_reset_t)bnx2x_8726_link_reset, | |
11130 | .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, | |
11131 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11132 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11133 | .set_link_led = (set_link_led_t)NULL, |
11134 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11135 | }; |
11136 | ||
11137 | static struct bnx2x_phy phy_8727 = { | |
11138 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, | |
11139 | .addr = 0xff, | |
b7737c9b | 11140 | .def_md_devad = 0, |
55098c5c YR |
11141 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11142 | FLAGS_TX_ERROR_CHECK), | |
b7737c9b YR |
11143 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11144 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11145 | .mdio_ctrl = 0, | |
11146 | .supported = (SUPPORTED_10000baseT_Full | | |
11147 | SUPPORTED_1000baseT_Full | | |
b7737c9b YR |
11148 | SUPPORTED_FIBRE | |
11149 | SUPPORTED_Pause | | |
11150 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11151 | .media_type = ETH_PHY_NOT_PRESENT, |
b7737c9b YR |
11152 | .ver_addr = 0, |
11153 | .req_flow_ctrl = 0, | |
11154 | .req_line_speed = 0, | |
11155 | .speed_cap_mask = 0, | |
11156 | .req_duplex = 0, | |
11157 | .rsrv = 0, | |
11158 | .config_init = (config_init_t)bnx2x_8727_config_init, | |
11159 | .read_status = (read_status_t)bnx2x_8727_read_status, | |
11160 | .link_reset = (link_reset_t)bnx2x_8727_link_reset, | |
11161 | .config_loopback = (config_loopback_t)NULL, | |
11162 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11163 | .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, | |
7f02c4ad | 11164 | .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, |
a22f0788 | 11165 | .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func |
b7737c9b YR |
11166 | }; |
11167 | static struct bnx2x_phy phy_8481 = { | |
11168 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, | |
11169 | .addr = 0xff, | |
9045f6b4 | 11170 | .def_md_devad = 0, |
a22f0788 YR |
11171 | .flags = FLAGS_FAN_FAILURE_DET_REQ | |
11172 | FLAGS_REARM_LATCH_SIGNAL, | |
b7737c9b YR |
11173 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11174 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11175 | .mdio_ctrl = 0, | |
11176 | .supported = (SUPPORTED_10baseT_Half | | |
11177 | SUPPORTED_10baseT_Full | | |
11178 | SUPPORTED_100baseT_Half | | |
11179 | SUPPORTED_100baseT_Full | | |
11180 | SUPPORTED_1000baseT_Full | | |
11181 | SUPPORTED_10000baseT_Full | | |
11182 | SUPPORTED_TP | | |
11183 | SUPPORTED_Autoneg | | |
11184 | SUPPORTED_Pause | | |
11185 | SUPPORTED_Asym_Pause), | |
11186 | .media_type = ETH_PHY_BASE_T, | |
11187 | .ver_addr = 0, | |
11188 | .req_flow_ctrl = 0, | |
11189 | .req_line_speed = 0, | |
11190 | .speed_cap_mask = 0, | |
11191 | .req_duplex = 0, | |
11192 | .rsrv = 0, | |
11193 | .config_init = (config_init_t)bnx2x_8481_config_init, | |
11194 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11195 | .link_reset = (link_reset_t)bnx2x_8481_link_reset, | |
11196 | .config_loopback = (config_loopback_t)NULL, | |
11197 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
11198 | .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, | |
7f02c4ad | 11199 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
a22f0788 | 11200 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b YR |
11201 | }; |
11202 | ||
de6eae1f YR |
11203 | static struct bnx2x_phy phy_84823 = { |
11204 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, | |
11205 | .addr = 0xff, | |
9045f6b4 | 11206 | .def_md_devad = 0, |
55098c5c YR |
11207 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11208 | FLAGS_REARM_LATCH_SIGNAL | | |
11209 | FLAGS_TX_ERROR_CHECK), | |
de6eae1f YR |
11210 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11211 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11212 | .mdio_ctrl = 0, | |
11213 | .supported = (SUPPORTED_10baseT_Half | | |
11214 | SUPPORTED_10baseT_Full | | |
11215 | SUPPORTED_100baseT_Half | | |
11216 | SUPPORTED_100baseT_Full | | |
11217 | SUPPORTED_1000baseT_Full | | |
11218 | SUPPORTED_10000baseT_Full | | |
11219 | SUPPORTED_TP | | |
11220 | SUPPORTED_Autoneg | | |
11221 | SUPPORTED_Pause | | |
11222 | SUPPORTED_Asym_Pause), | |
11223 | .media_type = ETH_PHY_BASE_T, | |
11224 | .ver_addr = 0, | |
11225 | .req_flow_ctrl = 0, | |
11226 | .req_line_speed = 0, | |
11227 | .speed_cap_mask = 0, | |
11228 | .req_duplex = 0, | |
11229 | .rsrv = 0, | |
11230 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
11231 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11232 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
11233 | .config_loopback = (config_loopback_t)NULL, | |
11234 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
11235 | .hw_reset = (hw_reset_t)NULL, | |
7f02c4ad | 11236 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
a22f0788 | 11237 | .phy_specific_func = (phy_specific_func_t)NULL |
de6eae1f YR |
11238 | }; |
11239 | ||
c87bca1e YR |
11240 | static struct bnx2x_phy phy_84833 = { |
11241 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, | |
11242 | .addr = 0xff, | |
9045f6b4 | 11243 | .def_md_devad = 0, |
55098c5c YR |
11244 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11245 | FLAGS_REARM_LATCH_SIGNAL | | |
11246 | FLAGS_TX_ERROR_CHECK), | |
c87bca1e YR |
11247 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11248 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11249 | .mdio_ctrl = 0, | |
0520e63a | 11250 | .supported = (SUPPORTED_100baseT_Half | |
c87bca1e YR |
11251 | SUPPORTED_100baseT_Full | |
11252 | SUPPORTED_1000baseT_Full | | |
11253 | SUPPORTED_10000baseT_Full | | |
11254 | SUPPORTED_TP | | |
11255 | SUPPORTED_Autoneg | | |
11256 | SUPPORTED_Pause | | |
11257 | SUPPORTED_Asym_Pause), | |
11258 | .media_type = ETH_PHY_BASE_T, | |
11259 | .ver_addr = 0, | |
11260 | .req_flow_ctrl = 0, | |
11261 | .req_line_speed = 0, | |
11262 | .speed_cap_mask = 0, | |
11263 | .req_duplex = 0, | |
11264 | .rsrv = 0, | |
11265 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
11266 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11267 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
11268 | .config_loopback = (config_loopback_t)NULL, | |
11269 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
985848f8 | 11270 | .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, |
c87bca1e YR |
11271 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
11272 | .phy_specific_func = (phy_specific_func_t)NULL | |
11273 | }; | |
11274 | ||
52c4d6c4 YR |
11275 | static struct bnx2x_phy phy_54618se = { |
11276 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, | |
6583e33b YR |
11277 | .addr = 0xff, |
11278 | .def_md_devad = 0, | |
11279 | .flags = FLAGS_INIT_XGXS_FIRST, | |
11280 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11281 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11282 | .mdio_ctrl = 0, | |
11283 | .supported = (SUPPORTED_10baseT_Half | | |
11284 | SUPPORTED_10baseT_Full | | |
11285 | SUPPORTED_100baseT_Half | | |
11286 | SUPPORTED_100baseT_Full | | |
11287 | SUPPORTED_1000baseT_Full | | |
11288 | SUPPORTED_TP | | |
11289 | SUPPORTED_Autoneg | | |
11290 | SUPPORTED_Pause | | |
11291 | SUPPORTED_Asym_Pause), | |
11292 | .media_type = ETH_PHY_BASE_T, | |
11293 | .ver_addr = 0, | |
11294 | .req_flow_ctrl = 0, | |
11295 | .req_line_speed = 0, | |
11296 | .speed_cap_mask = 0, | |
11297 | /* req_duplex = */0, | |
11298 | /* rsrv = */0, | |
52c4d6c4 YR |
11299 | .config_init = (config_init_t)bnx2x_54618se_config_init, |
11300 | .read_status = (read_status_t)bnx2x_54618se_read_status, | |
11301 | .link_reset = (link_reset_t)bnx2x_54618se_link_reset, | |
11302 | .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, | |
6583e33b YR |
11303 | .format_fw_ver = (format_fw_ver_t)NULL, |
11304 | .hw_reset = (hw_reset_t)NULL, | |
1d125bd5 | 11305 | .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, |
6583e33b YR |
11306 | .phy_specific_func = (phy_specific_func_t)NULL |
11307 | }; | |
de6eae1f YR |
11308 | /*****************************************************************/ |
11309 | /* */ | |
11310 | /* Populate the phy according. Main function: bnx2x_populate_phy */ | |
11311 | /* */ | |
11312 | /*****************************************************************/ | |
11313 | ||
11314 | static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, | |
11315 | struct bnx2x_phy *phy, u8 port, | |
11316 | u8 phy_index) | |
11317 | { | |
11318 | /* Get the 4 lanes xgxs config rx and tx */ | |
11319 | u32 rx = 0, tx = 0, i; | |
11320 | for (i = 0; i < 2; i++) { | |
8f73f0b9 YR |
11321 | /* INT_PHY and EXT_PHY1 share the same value location in |
11322 | * the shmem. When num_phys is greater than 1, than this value | |
de6eae1f YR |
11323 | * applies only to EXT_PHY1 |
11324 | */ | |
a22f0788 YR |
11325 | if (phy_index == INT_PHY || phy_index == EXT_PHY1) { |
11326 | rx = REG_RD(bp, shmem_base + | |
11327 | offsetof(struct shmem_region, | |
cd88ccee | 11328 | dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); |
a22f0788 YR |
11329 | |
11330 | tx = REG_RD(bp, shmem_base + | |
11331 | offsetof(struct shmem_region, | |
cd88ccee | 11332 | dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); |
a22f0788 YR |
11333 | } else { |
11334 | rx = REG_RD(bp, shmem_base + | |
11335 | offsetof(struct shmem_region, | |
cd88ccee | 11336 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
de6eae1f | 11337 | |
a22f0788 YR |
11338 | tx = REG_RD(bp, shmem_base + |
11339 | offsetof(struct shmem_region, | |
cd88ccee | 11340 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
a22f0788 | 11341 | } |
de6eae1f YR |
11342 | |
11343 | phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); | |
11344 | phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); | |
11345 | ||
11346 | phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); | |
11347 | phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); | |
11348 | } | |
11349 | } | |
11350 | ||
11351 | static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, | |
11352 | u8 phy_index, u8 port) | |
11353 | { | |
11354 | u32 ext_phy_config = 0; | |
11355 | switch (phy_index) { | |
11356 | case EXT_PHY1: | |
11357 | ext_phy_config = REG_RD(bp, shmem_base + | |
11358 | offsetof(struct shmem_region, | |
11359 | dev_info.port_hw_config[port].external_phy_config)); | |
11360 | break; | |
a22f0788 YR |
11361 | case EXT_PHY2: |
11362 | ext_phy_config = REG_RD(bp, shmem_base + | |
11363 | offsetof(struct shmem_region, | |
11364 | dev_info.port_hw_config[port].external_phy_config2)); | |
11365 | break; | |
de6eae1f YR |
11366 | default: |
11367 | DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); | |
11368 | return -EINVAL; | |
11369 | } | |
11370 | ||
11371 | return ext_phy_config; | |
11372 | } | |
fcf5b650 YR |
11373 | static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, |
11374 | struct bnx2x_phy *phy) | |
de6eae1f YR |
11375 | { |
11376 | u32 phy_addr; | |
11377 | u32 chip_id; | |
11378 | u32 switch_cfg = (REG_RD(bp, shmem_base + | |
11379 | offsetof(struct shmem_region, | |
11380 | dev_info.port_feature_config[port].link_config)) & | |
11381 | PORT_FEATURE_CONNECTED_SWITCH_MASK); | |
ec15b898 YR |
11382 | chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | |
11383 | ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); | |
11384 | ||
3c9ada22 YR |
11385 | DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); |
11386 | if (USES_WARPCORE(bp)) { | |
11387 | u32 serdes_net_if; | |
de6eae1f | 11388 | phy_addr = REG_RD(bp, |
3c9ada22 YR |
11389 | MISC_REG_WC0_CTRL_PHY_ADDR); |
11390 | *phy = phy_warpcore; | |
11391 | if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) | |
11392 | phy->flags |= FLAGS_4_PORT_MODE; | |
11393 | else | |
11394 | phy->flags &= ~FLAGS_4_PORT_MODE; | |
11395 | /* Check Dual mode */ | |
11396 | serdes_net_if = (REG_RD(bp, shmem_base + | |
11397 | offsetof(struct shmem_region, dev_info. | |
11398 | port_hw_config[port].default_cfg)) & | |
11399 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
8f73f0b9 | 11400 | /* Set the appropriate supported and flags indications per |
3c9ada22 YR |
11401 | * interface type of the chip |
11402 | */ | |
11403 | switch (serdes_net_if) { | |
11404 | case PORT_HW_CFG_NET_SERDES_IF_SGMII: | |
11405 | phy->supported &= (SUPPORTED_10baseT_Half | | |
11406 | SUPPORTED_10baseT_Full | | |
11407 | SUPPORTED_100baseT_Half | | |
11408 | SUPPORTED_100baseT_Full | | |
11409 | SUPPORTED_1000baseT_Full | | |
11410 | SUPPORTED_FIBRE | | |
11411 | SUPPORTED_Autoneg | | |
11412 | SUPPORTED_Pause | | |
11413 | SUPPORTED_Asym_Pause); | |
11414 | phy->media_type = ETH_PHY_BASE_T; | |
11415 | break; | |
11416 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | |
11417 | phy->media_type = ETH_PHY_XFP_FIBER; | |
11418 | break; | |
11419 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | |
11420 | phy->supported &= (SUPPORTED_1000baseT_Full | | |
11421 | SUPPORTED_10000baseT_Full | | |
11422 | SUPPORTED_FIBRE | | |
11423 | SUPPORTED_Pause | | |
11424 | SUPPORTED_Asym_Pause); | |
11425 | phy->media_type = ETH_PHY_SFP_FIBER; | |
11426 | break; | |
11427 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
11428 | phy->media_type = ETH_PHY_KR; | |
11429 | phy->supported &= (SUPPORTED_1000baseT_Full | | |
11430 | SUPPORTED_10000baseT_Full | | |
11431 | SUPPORTED_FIBRE | | |
11432 | SUPPORTED_Autoneg | | |
11433 | SUPPORTED_Pause | | |
11434 | SUPPORTED_Asym_Pause); | |
11435 | break; | |
11436 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: | |
11437 | phy->media_type = ETH_PHY_KR; | |
11438 | phy->flags |= FLAGS_WC_DUAL_MODE; | |
11439 | phy->supported &= (SUPPORTED_20000baseMLD2_Full | | |
11440 | SUPPORTED_FIBRE | | |
11441 | SUPPORTED_Pause | | |
11442 | SUPPORTED_Asym_Pause); | |
11443 | break; | |
11444 | case PORT_HW_CFG_NET_SERDES_IF_KR2: | |
11445 | phy->media_type = ETH_PHY_KR; | |
11446 | phy->flags |= FLAGS_WC_DUAL_MODE; | |
11447 | phy->supported &= (SUPPORTED_20000baseKR2_Full | | |
11448 | SUPPORTED_FIBRE | | |
11449 | SUPPORTED_Pause | | |
11450 | SUPPORTED_Asym_Pause); | |
11451 | break; | |
11452 | default: | |
11453 | DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", | |
11454 | serdes_net_if); | |
11455 | break; | |
11456 | } | |
11457 | ||
8f73f0b9 | 11458 | /* Enable MDC/MDIO work-around for E3 A0 since free running MDC |
3c9ada22 YR |
11459 | * was not set as expected. For B0, ECO will be enabled so there |
11460 | * won't be an issue there | |
11461 | */ | |
11462 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
11463 | phy->flags |= FLAGS_MDC_MDIO_WA; | |
157fa283 YR |
11464 | else |
11465 | phy->flags |= FLAGS_MDC_MDIO_WA_B0; | |
3c9ada22 YR |
11466 | } else { |
11467 | switch (switch_cfg) { | |
11468 | case SWITCH_CFG_1G: | |
11469 | phy_addr = REG_RD(bp, | |
11470 | NIG_REG_SERDES0_CTRL_PHY_ADDR + | |
11471 | port * 0x10); | |
11472 | *phy = phy_serdes; | |
11473 | break; | |
11474 | case SWITCH_CFG_10G: | |
11475 | phy_addr = REG_RD(bp, | |
11476 | NIG_REG_XGXS0_CTRL_PHY_ADDR + | |
11477 | port * 0x18); | |
11478 | *phy = phy_xgxs; | |
11479 | break; | |
11480 | default: | |
11481 | DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); | |
11482 | return -EINVAL; | |
11483 | } | |
de6eae1f YR |
11484 | } |
11485 | phy->addr = (u8)phy_addr; | |
11486 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, | |
11487 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, | |
11488 | port); | |
f2e0899f DK |
11489 | if (CHIP_IS_E2(bp)) |
11490 | phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; | |
11491 | else | |
11492 | phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; | |
de6eae1f YR |
11493 | |
11494 | DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", | |
11495 | port, phy->addr, phy->mdio_ctrl); | |
11496 | ||
11497 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); | |
11498 | return 0; | |
11499 | } | |
11500 | ||
fcf5b650 YR |
11501 | static int bnx2x_populate_ext_phy(struct bnx2x *bp, |
11502 | u8 phy_index, | |
11503 | u32 shmem_base, | |
11504 | u32 shmem2_base, | |
11505 | u8 port, | |
11506 | struct bnx2x_phy *phy) | |
de6eae1f YR |
11507 | { |
11508 | u32 ext_phy_config, phy_type, config2; | |
11509 | u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; | |
11510 | ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, | |
11511 | phy_index, port); | |
11512 | phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
11513 | /* Select the phy type */ | |
11514 | switch (phy_type) { | |
11515 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
11516 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; | |
11517 | *phy = phy_8073; | |
11518 | break; | |
11519 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | |
11520 | *phy = phy_8705; | |
11521 | break; | |
11522 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | |
11523 | *phy = phy_8706; | |
11524 | break; | |
11525 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
11526 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
11527 | *phy = phy_8726; | |
11528 | break; | |
11529 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
11530 | /* BCM8727_NOC => BCM8727 no over current */ | |
11531 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
11532 | *phy = phy_8727; | |
11533 | phy->flags |= FLAGS_NOC; | |
11534 | break; | |
e4d78f12 | 11535 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
de6eae1f YR |
11536 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
11537 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
11538 | *phy = phy_8727; | |
11539 | break; | |
11540 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: | |
11541 | *phy = phy_8481; | |
11542 | break; | |
11543 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | |
11544 | *phy = phy_84823; | |
11545 | break; | |
c87bca1e YR |
11546 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
11547 | *phy = phy_84833; | |
11548 | break; | |
3756a89f | 11549 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: |
52c4d6c4 YR |
11550 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: |
11551 | *phy = phy_54618se; | |
6583e33b | 11552 | break; |
de6eae1f YR |
11553 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: |
11554 | *phy = phy_7101; | |
11555 | break; | |
11556 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: | |
11557 | *phy = phy_null; | |
11558 | return -EINVAL; | |
11559 | default: | |
11560 | *phy = phy_null; | |
6db5193b YR |
11561 | /* In case external PHY wasn't found */ |
11562 | if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && | |
11563 | (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
11564 | return -EINVAL; | |
de6eae1f YR |
11565 | return 0; |
11566 | } | |
11567 | ||
11568 | phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); | |
11569 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); | |
11570 | ||
8f73f0b9 | 11571 | /* The shmem address of the phy version is located on different |
2cf7acf9 YR |
11572 | * structures. In case this structure is too old, do not set |
11573 | * the address | |
11574 | */ | |
de6eae1f YR |
11575 | config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, |
11576 | dev_info.shared_hw_config.config2)); | |
a22f0788 YR |
11577 | if (phy_index == EXT_PHY1) { |
11578 | phy->ver_addr = shmem_base + offsetof(struct shmem_region, | |
11579 | port_mb[port].ext_phy_fw_version); | |
de6eae1f | 11580 | |
cd88ccee YR |
11581 | /* Check specific mdc mdio settings */ |
11582 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) | |
11583 | mdc_mdio_access = config2 & | |
11584 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; | |
a22f0788 YR |
11585 | } else { |
11586 | u32 size = REG_RD(bp, shmem2_base); | |
de6eae1f | 11587 | |
a22f0788 YR |
11588 | if (size > |
11589 | offsetof(struct shmem2_region, ext_phy_fw_version2)) { | |
11590 | phy->ver_addr = shmem2_base + | |
11591 | offsetof(struct shmem2_region, | |
11592 | ext_phy_fw_version2[port]); | |
11593 | } | |
11594 | /* Check specific mdc mdio settings */ | |
11595 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) | |
11596 | mdc_mdio_access = (config2 & | |
11597 | SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> | |
11598 | (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - | |
11599 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); | |
11600 | } | |
de6eae1f YR |
11601 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); |
11602 | ||
75318327 YR |
11603 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
11604 | (phy->ver_addr)) { | |
8f73f0b9 | 11605 | /* Remove 100Mb link supported for BCM84833 when phy fw |
75318327 YR |
11606 | * version lower than or equal to 1.39 |
11607 | */ | |
11608 | u32 raw_ver = REG_RD(bp, phy->ver_addr); | |
11609 | if (((raw_ver & 0x7F) <= 39) && | |
11610 | (((raw_ver & 0xF80) >> 7) <= 1)) | |
11611 | phy->supported &= ~(SUPPORTED_100baseT_Half | | |
11612 | SUPPORTED_100baseT_Full); | |
11613 | } | |
11614 | ||
8f73f0b9 | 11615 | /* In case mdc/mdio_access of the external phy is different than the |
de6eae1f YR |
11616 | * mdc/mdio access of the XGXS, a HW lock must be taken in each access |
11617 | * to prevent one port interfere with another port's CL45 operations. | |
11618 | */ | |
11619 | if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH) | |
11620 | phy->flags |= FLAGS_HW_LOCK_REQUIRED; | |
11621 | DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", | |
11622 | phy_type, port, phy_index); | |
11623 | DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", | |
11624 | phy->addr, phy->mdio_ctrl); | |
11625 | return 0; | |
11626 | } | |
11627 | ||
fcf5b650 YR |
11628 | static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, |
11629 | u32 shmem2_base, u8 port, struct bnx2x_phy *phy) | |
de6eae1f | 11630 | { |
fcf5b650 | 11631 | int status = 0; |
de6eae1f YR |
11632 | phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; |
11633 | if (phy_index == INT_PHY) | |
11634 | return bnx2x_populate_int_phy(bp, shmem_base, port, phy); | |
a22f0788 | 11635 | status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
11636 | port, phy); |
11637 | return status; | |
11638 | } | |
11639 | ||
11640 | static void bnx2x_phy_def_cfg(struct link_params *params, | |
11641 | struct bnx2x_phy *phy, | |
a22f0788 | 11642 | u8 phy_index) |
de6eae1f YR |
11643 | { |
11644 | struct bnx2x *bp = params->bp; | |
11645 | u32 link_config; | |
11646 | /* Populate the default phy configuration for MF mode */ | |
a22f0788 YR |
11647 | if (phy_index == EXT_PHY2) { |
11648 | link_config = REG_RD(bp, params->shmem_base + | |
cd88ccee | 11649 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
11650 | port_feature_config[params->port].link_config2)); |
11651 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
11652 | offsetof(struct shmem_region, |
11653 | dev_info. | |
a22f0788 YR |
11654 | port_hw_config[params->port].speed_capability_mask2)); |
11655 | } else { | |
11656 | link_config = REG_RD(bp, params->shmem_base + | |
cd88ccee | 11657 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
11658 | port_feature_config[params->port].link_config)); |
11659 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
11660 | offsetof(struct shmem_region, |
11661 | dev_info. | |
11662 | port_hw_config[params->port].speed_capability_mask)); | |
a22f0788 | 11663 | } |
94f05b0f JP |
11664 | DP(NETIF_MSG_LINK, |
11665 | "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", | |
11666 | phy_index, link_config, phy->speed_cap_mask); | |
de6eae1f YR |
11667 | |
11668 | phy->req_duplex = DUPLEX_FULL; | |
11669 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
11670 | case PORT_FEATURE_LINK_SPEED_10M_HALF: | |
11671 | phy->req_duplex = DUPLEX_HALF; | |
11672 | case PORT_FEATURE_LINK_SPEED_10M_FULL: | |
11673 | phy->req_line_speed = SPEED_10; | |
11674 | break; | |
11675 | case PORT_FEATURE_LINK_SPEED_100M_HALF: | |
11676 | phy->req_duplex = DUPLEX_HALF; | |
11677 | case PORT_FEATURE_LINK_SPEED_100M_FULL: | |
11678 | phy->req_line_speed = SPEED_100; | |
11679 | break; | |
11680 | case PORT_FEATURE_LINK_SPEED_1G: | |
11681 | phy->req_line_speed = SPEED_1000; | |
11682 | break; | |
11683 | case PORT_FEATURE_LINK_SPEED_2_5G: | |
11684 | phy->req_line_speed = SPEED_2500; | |
11685 | break; | |
11686 | case PORT_FEATURE_LINK_SPEED_10G_CX4: | |
11687 | phy->req_line_speed = SPEED_10000; | |
11688 | break; | |
11689 | default: | |
11690 | phy->req_line_speed = SPEED_AUTO_NEG; | |
11691 | break; | |
11692 | } | |
11693 | ||
11694 | switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { | |
11695 | case PORT_FEATURE_FLOW_CONTROL_AUTO: | |
11696 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; | |
11697 | break; | |
11698 | case PORT_FEATURE_FLOW_CONTROL_TX: | |
11699 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; | |
11700 | break; | |
11701 | case PORT_FEATURE_FLOW_CONTROL_RX: | |
11702 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; | |
11703 | break; | |
11704 | case PORT_FEATURE_FLOW_CONTROL_BOTH: | |
11705 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; | |
11706 | break; | |
11707 | default: | |
11708 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
11709 | break; | |
11710 | } | |
11711 | } | |
11712 | ||
a22f0788 YR |
11713 | u32 bnx2x_phy_selection(struct link_params *params) |
11714 | { | |
11715 | u32 phy_config_swapped, prio_cfg; | |
11716 | u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; | |
11717 | ||
11718 | phy_config_swapped = params->multi_phy_config & | |
11719 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
11720 | ||
11721 | prio_cfg = params->multi_phy_config & | |
11722 | PORT_HW_CFG_PHY_SELECTION_MASK; | |
11723 | ||
11724 | if (phy_config_swapped) { | |
11725 | switch (prio_cfg) { | |
11726 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
11727 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; | |
11728 | break; | |
11729 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
11730 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; | |
11731 | break; | |
11732 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
11733 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
11734 | break; | |
11735 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
11736 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
11737 | break; | |
11738 | } | |
11739 | } else | |
11740 | return_cfg = prio_cfg; | |
11741 | ||
11742 | return return_cfg; | |
11743 | } | |
11744 | ||
11745 | ||
fcf5b650 | 11746 | int bnx2x_phy_probe(struct link_params *params) |
de6eae1f | 11747 | { |
2f751a80 | 11748 | u8 phy_index, actual_phy_idx; |
1ac9e428 | 11749 | u32 phy_config_swapped, sync_offset, media_types; |
de6eae1f YR |
11750 | struct bnx2x *bp = params->bp; |
11751 | struct bnx2x_phy *phy; | |
11752 | params->num_phys = 0; | |
11753 | DP(NETIF_MSG_LINK, "Begin phy probe\n"); | |
a22f0788 YR |
11754 | phy_config_swapped = params->multi_phy_config & |
11755 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
de6eae1f YR |
11756 | |
11757 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
11758 | phy_index++) { | |
de6eae1f | 11759 | actual_phy_idx = phy_index; |
a22f0788 YR |
11760 | if (phy_config_swapped) { |
11761 | if (phy_index == EXT_PHY1) | |
11762 | actual_phy_idx = EXT_PHY2; | |
11763 | else if (phy_index == EXT_PHY2) | |
11764 | actual_phy_idx = EXT_PHY1; | |
11765 | } | |
11766 | DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," | |
11767 | " actual_phy_idx %x\n", phy_config_swapped, | |
11768 | phy_index, actual_phy_idx); | |
de6eae1f YR |
11769 | phy = ¶ms->phy[actual_phy_idx]; |
11770 | if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, | |
a22f0788 | 11771 | params->shmem2_base, params->port, |
de6eae1f YR |
11772 | phy) != 0) { |
11773 | params->num_phys = 0; | |
11774 | DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", | |
11775 | phy_index); | |
11776 | for (phy_index = INT_PHY; | |
11777 | phy_index < MAX_PHYS; | |
11778 | phy_index++) | |
11779 | *phy = phy_null; | |
11780 | return -EINVAL; | |
11781 | } | |
11782 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) | |
11783 | break; | |
11784 | ||
55098c5c YR |
11785 | if (params->feature_config_flags & |
11786 | FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) | |
11787 | phy->flags &= ~FLAGS_TX_ERROR_CHECK; | |
11788 | ||
1ac9e428 YR |
11789 | sync_offset = params->shmem_base + |
11790 | offsetof(struct shmem_region, | |
11791 | dev_info.port_hw_config[params->port].media_type); | |
11792 | media_types = REG_RD(bp, sync_offset); | |
11793 | ||
8f73f0b9 | 11794 | /* Update media type for non-PMF sync only for the first time |
1ac9e428 YR |
11795 | * In case the media type changes afterwards, it will be updated |
11796 | * using the update_status function | |
11797 | */ | |
11798 | if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << | |
11799 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
11800 | actual_phy_idx))) == 0) { | |
11801 | media_types |= ((phy->media_type & | |
11802 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << | |
11803 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
11804 | actual_phy_idx)); | |
11805 | } | |
11806 | REG_WR(bp, sync_offset, media_types); | |
11807 | ||
a22f0788 | 11808 | bnx2x_phy_def_cfg(params, phy, phy_index); |
de6eae1f YR |
11809 | params->num_phys++; |
11810 | } | |
11811 | ||
11812 | DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); | |
11813 | return 0; | |
11814 | } | |
11815 | ||
9045f6b4 YR |
11816 | void bnx2x_init_bmac_loopback(struct link_params *params, |
11817 | struct link_vars *vars) | |
de6eae1f YR |
11818 | { |
11819 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
11820 | vars->link_up = 1; |
11821 | vars->line_speed = SPEED_10000; | |
11822 | vars->duplex = DUPLEX_FULL; | |
11823 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
11824 | vars->mac_type = MAC_TYPE_BMAC; | |
b7737c9b | 11825 | |
de6eae1f | 11826 | vars->phy_flags = PHY_XGXS_FLAG; |
b7737c9b | 11827 | |
de6eae1f | 11828 | bnx2x_xgxs_deassert(params); |
b7737c9b | 11829 | |
de6eae1f YR |
11830 | /* set bmac loopback */ |
11831 | bnx2x_bmac_enable(params, vars, 1); | |
b7737c9b | 11832 | |
cd88ccee | 11833 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
9045f6b4 | 11834 | } |
b7737c9b | 11835 | |
9045f6b4 YR |
11836 | void bnx2x_init_emac_loopback(struct link_params *params, |
11837 | struct link_vars *vars) | |
11838 | { | |
11839 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
11840 | vars->link_up = 1; |
11841 | vars->line_speed = SPEED_1000; | |
11842 | vars->duplex = DUPLEX_FULL; | |
11843 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
11844 | vars->mac_type = MAC_TYPE_EMAC; | |
b7737c9b | 11845 | |
de6eae1f | 11846 | vars->phy_flags = PHY_XGXS_FLAG; |
e10bc84d | 11847 | |
de6eae1f YR |
11848 | bnx2x_xgxs_deassert(params); |
11849 | /* set bmac loopback */ | |
11850 | bnx2x_emac_enable(params, vars, 1); | |
11851 | bnx2x_emac_program(params, vars); | |
cd88ccee | 11852 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
9045f6b4 | 11853 | } |
b7737c9b | 11854 | |
9380bb9e YR |
11855 | void bnx2x_init_xmac_loopback(struct link_params *params, |
11856 | struct link_vars *vars) | |
11857 | { | |
11858 | struct bnx2x *bp = params->bp; | |
11859 | vars->link_up = 1; | |
11860 | if (!params->req_line_speed[0]) | |
11861 | vars->line_speed = SPEED_10000; | |
11862 | else | |
11863 | vars->line_speed = params->req_line_speed[0]; | |
11864 | vars->duplex = DUPLEX_FULL; | |
11865 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
11866 | vars->mac_type = MAC_TYPE_XMAC; | |
11867 | vars->phy_flags = PHY_XGXS_FLAG; | |
8f73f0b9 | 11868 | /* Set WC to loopback mode since link is required to provide clock |
9380bb9e YR |
11869 | * to the XMAC in 20G mode |
11870 | */ | |
afad009a YR |
11871 | bnx2x_set_aer_mmd(params, ¶ms->phy[0]); |
11872 | bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); | |
11873 | params->phy[INT_PHY].config_loopback( | |
3c9ada22 YR |
11874 | ¶ms->phy[INT_PHY], |
11875 | params); | |
afad009a | 11876 | |
9380bb9e YR |
11877 | bnx2x_xmac_enable(params, vars, 1); |
11878 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
11879 | } | |
11880 | ||
11881 | void bnx2x_init_umac_loopback(struct link_params *params, | |
11882 | struct link_vars *vars) | |
11883 | { | |
11884 | struct bnx2x *bp = params->bp; | |
11885 | vars->link_up = 1; | |
11886 | vars->line_speed = SPEED_1000; | |
11887 | vars->duplex = DUPLEX_FULL; | |
11888 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
11889 | vars->mac_type = MAC_TYPE_UMAC; | |
11890 | vars->phy_flags = PHY_XGXS_FLAG; | |
11891 | bnx2x_umac_enable(params, vars, 1); | |
11892 | ||
11893 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
11894 | } | |
11895 | ||
9045f6b4 YR |
11896 | void bnx2x_init_xgxs_loopback(struct link_params *params, |
11897 | struct link_vars *vars) | |
11898 | { | |
11899 | struct bnx2x *bp = params->bp; | |
de6eae1f | 11900 | vars->link_up = 1; |
de6eae1f | 11901 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
a22f0788 | 11902 | vars->duplex = DUPLEX_FULL; |
9045f6b4 | 11903 | if (params->req_line_speed[0] == SPEED_1000) |
a22f0788 | 11904 | vars->line_speed = SPEED_1000; |
9045f6b4 | 11905 | else |
a22f0788 | 11906 | vars->line_speed = SPEED_10000; |
62b29a5d | 11907 | |
9380bb9e YR |
11908 | if (!USES_WARPCORE(bp)) |
11909 | bnx2x_xgxs_deassert(params); | |
9045f6b4 YR |
11910 | bnx2x_link_initialize(params, vars); |
11911 | ||
11912 | if (params->req_line_speed[0] == SPEED_1000) { | |
9380bb9e YR |
11913 | if (USES_WARPCORE(bp)) |
11914 | bnx2x_umac_enable(params, vars, 0); | |
11915 | else { | |
11916 | bnx2x_emac_program(params, vars); | |
11917 | bnx2x_emac_enable(params, vars, 0); | |
11918 | } | |
11919 | } else { | |
11920 | if (USES_WARPCORE(bp)) | |
11921 | bnx2x_xmac_enable(params, vars, 0); | |
11922 | else | |
11923 | bnx2x_bmac_enable(params, vars, 0); | |
11924 | } | |
9045f6b4 | 11925 | |
de6eae1f YR |
11926 | if (params->loopback_mode == LOOPBACK_XGXS) { |
11927 | /* set 10G XGXS loopback */ | |
11928 | params->phy[INT_PHY].config_loopback( | |
11929 | ¶ms->phy[INT_PHY], | |
11930 | params); | |
c18aa15d | 11931 | |
de6eae1f YR |
11932 | } else { |
11933 | /* set external phy loopback */ | |
11934 | u8 phy_index; | |
11935 | for (phy_index = EXT_PHY1; | |
11936 | phy_index < params->num_phys; phy_index++) { | |
11937 | if (params->phy[phy_index].config_loopback) | |
11938 | params->phy[phy_index].config_loopback( | |
11939 | ¶ms->phy[phy_index], | |
11940 | params); | |
11941 | } | |
11942 | } | |
cd88ccee | 11943 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
de6eae1f | 11944 | |
9045f6b4 YR |
11945 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
11946 | } | |
11947 | ||
11948 | int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) | |
11949 | { | |
11950 | struct bnx2x *bp = params->bp; | |
11951 | DP(NETIF_MSG_LINK, "Phy Initialization started\n"); | |
11952 | DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", | |
11953 | params->req_line_speed[0], params->req_flow_ctrl[0]); | |
11954 | DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", | |
11955 | params->req_line_speed[1], params->req_flow_ctrl[1]); | |
11956 | vars->link_status = 0; | |
11957 | vars->phy_link_up = 0; | |
11958 | vars->link_up = 0; | |
11959 | vars->line_speed = 0; | |
11960 | vars->duplex = DUPLEX_FULL; | |
11961 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
11962 | vars->mac_type = MAC_TYPE_NONE; | |
11963 | vars->phy_flags = 0; | |
11964 | ||
11965 | /* disable attentions */ | |
11966 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, | |
11967 | (NIG_MASK_XGXS0_LINK_STATUS | | |
11968 | NIG_MASK_XGXS0_LINK10G | | |
11969 | NIG_MASK_SERDES0_LINK_STATUS | | |
11970 | NIG_MASK_MI_INT)); | |
11971 | ||
11972 | bnx2x_emac_init(params, vars); | |
11973 | ||
27d9129f YR |
11974 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
11975 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
11976 | ||
9045f6b4 YR |
11977 | if (params->num_phys == 0) { |
11978 | DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); | |
11979 | return -EINVAL; | |
11980 | } | |
11981 | set_phy_vars(params, vars); | |
11982 | ||
11983 | DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); | |
11984 | switch (params->loopback_mode) { | |
11985 | case LOOPBACK_BMAC: | |
11986 | bnx2x_init_bmac_loopback(params, vars); | |
11987 | break; | |
11988 | case LOOPBACK_EMAC: | |
11989 | bnx2x_init_emac_loopback(params, vars); | |
11990 | break; | |
9380bb9e YR |
11991 | case LOOPBACK_XMAC: |
11992 | bnx2x_init_xmac_loopback(params, vars); | |
11993 | break; | |
11994 | case LOOPBACK_UMAC: | |
11995 | bnx2x_init_umac_loopback(params, vars); | |
11996 | break; | |
9045f6b4 YR |
11997 | case LOOPBACK_XGXS: |
11998 | case LOOPBACK_EXT_PHY: | |
11999 | bnx2x_init_xgxs_loopback(params, vars); | |
12000 | break; | |
12001 | default: | |
9380bb9e YR |
12002 | if (!CHIP_IS_E3(bp)) { |
12003 | if (params->switch_cfg == SWITCH_CFG_10G) | |
12004 | bnx2x_xgxs_deassert(params); | |
12005 | else | |
12006 | bnx2x_serdes_deassert(bp, params->port); | |
12007 | } | |
de6eae1f YR |
12008 | bnx2x_link_initialize(params, vars); |
12009 | msleep(30); | |
12010 | bnx2x_link_int_enable(params); | |
9045f6b4 | 12011 | break; |
de6eae1f | 12012 | } |
55098c5c | 12013 | bnx2x_update_mng(params, vars->link_status); |
e10bc84d YR |
12014 | return 0; |
12015 | } | |
fcf5b650 YR |
12016 | |
12017 | int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, | |
12018 | u8 reset_ext_phy) | |
b7737c9b YR |
12019 | { |
12020 | struct bnx2x *bp = params->bp; | |
cf1d972c | 12021 | u8 phy_index, port = params->port, clear_latch_ind = 0; |
de6eae1f YR |
12022 | DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); |
12023 | /* disable attentions */ | |
12024 | vars->link_status = 0; | |
12025 | bnx2x_update_mng(params, vars->link_status); | |
12026 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | |
cd88ccee YR |
12027 | (NIG_MASK_XGXS0_LINK_STATUS | |
12028 | NIG_MASK_XGXS0_LINK10G | | |
12029 | NIG_MASK_SERDES0_LINK_STATUS | | |
12030 | NIG_MASK_MI_INT)); | |
b7737c9b | 12031 | |
de6eae1f YR |
12032 | /* activate nig drain */ |
12033 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); | |
b7737c9b | 12034 | |
de6eae1f | 12035 | /* disable nig egress interface */ |
9380bb9e YR |
12036 | if (!CHIP_IS_E3(bp)) { |
12037 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); | |
12038 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); | |
12039 | } | |
b7737c9b | 12040 | |
de6eae1f | 12041 | /* Stop BigMac rx */ |
9380bb9e YR |
12042 | if (!CHIP_IS_E3(bp)) |
12043 | bnx2x_bmac_rx_disable(bp, port); | |
ce7c0489 | 12044 | else { |
9380bb9e | 12045 | bnx2x_xmac_disable(params); |
ce7c0489 YR |
12046 | bnx2x_umac_disable(params); |
12047 | } | |
de6eae1f | 12048 | /* disable emac */ |
9380bb9e YR |
12049 | if (!CHIP_IS_E3(bp)) |
12050 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
b7737c9b | 12051 | |
de6eae1f | 12052 | msleep(10); |
25985edc | 12053 | /* The PHY reset is controlled by GPIO 1 |
de6eae1f YR |
12054 | * Hold it as vars low |
12055 | */ | |
12056 | /* clear link led */ | |
ca7b91bb | 12057 | bnx2x_set_mdio_clk(bp, params->chip_id, port); |
7f02c4ad YR |
12058 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
12059 | ||
de6eae1f YR |
12060 | if (reset_ext_phy) { |
12061 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
12062 | phy_index++) { | |
28f4881c YR |
12063 | if (params->phy[phy_index].link_reset) { |
12064 | bnx2x_set_aer_mmd(params, | |
12065 | ¶ms->phy[phy_index]); | |
de6eae1f YR |
12066 | params->phy[phy_index].link_reset( |
12067 | ¶ms->phy[phy_index], | |
12068 | params); | |
28f4881c | 12069 | } |
cf1d972c YR |
12070 | if (params->phy[phy_index].flags & |
12071 | FLAGS_REARM_LATCH_SIGNAL) | |
12072 | clear_latch_ind = 1; | |
b7737c9b | 12073 | } |
b7737c9b YR |
12074 | } |
12075 | ||
cf1d972c YR |
12076 | if (clear_latch_ind) { |
12077 | /* Clear latching indication */ | |
12078 | bnx2x_rearm_latch_signal(bp, port, 0); | |
12079 | bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, | |
12080 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
12081 | } | |
de6eae1f YR |
12082 | if (params->phy[INT_PHY].link_reset) |
12083 | params->phy[INT_PHY].link_reset( | |
12084 | ¶ms->phy[INT_PHY], params); | |
b7737c9b | 12085 | |
de6eae1f | 12086 | /* disable nig ingress interface */ |
9380bb9e | 12087 | if (!CHIP_IS_E3(bp)) { |
ce7c0489 YR |
12088 | /* reset BigMac */ |
12089 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
12090 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
9380bb9e YR |
12091 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); |
12092 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); | |
ce7c0489 YR |
12093 | } else { |
12094 | u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
12095 | bnx2x_set_xumac_nig(params, 0, 0); | |
12096 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
12097 | MISC_REGISTERS_RESET_REG_2_XMAC) | |
12098 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, | |
12099 | XMAC_CTRL_REG_SOFT_RESET); | |
9380bb9e | 12100 | } |
de6eae1f | 12101 | vars->link_up = 0; |
3c9ada22 | 12102 | vars->phy_flags = 0; |
b7737c9b YR |
12103 | return 0; |
12104 | } | |
12105 | ||
de6eae1f YR |
12106 | /****************************************************************************/ |
12107 | /* Common function */ | |
12108 | /****************************************************************************/ | |
fcf5b650 YR |
12109 | static int bnx2x_8073_common_init_phy(struct bnx2x *bp, |
12110 | u32 shmem_base_path[], | |
12111 | u32 shmem2_base_path[], u8 phy_index, | |
12112 | u32 chip_id) | |
6bbca910 | 12113 | { |
e10bc84d YR |
12114 | struct bnx2x_phy phy[PORT_MAX]; |
12115 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
6bbca910 | 12116 | u16 val; |
c8e64df4 | 12117 | s8 port = 0; |
f2e0899f | 12118 | s8 port_of_path = 0; |
c8e64df4 YR |
12119 | u32 swap_val, swap_override; |
12120 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
12121 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
12122 | port ^= (swap_val && swap_override); | |
12123 | bnx2x_ext_phy_hw_reset(bp, port); | |
6bbca910 YR |
12124 | /* PART1 - Reset both phys */ |
12125 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f2e0899f DK |
12126 | u32 shmem_base, shmem2_base; |
12127 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 12128 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
12129 | shmem_base = shmem_base_path[0]; |
12130 | shmem2_base = shmem2_base_path[0]; | |
12131 | port_of_path = port; | |
3c9ada22 YR |
12132 | } else { |
12133 | shmem_base = shmem_base_path[port]; | |
12134 | shmem2_base = shmem2_base_path[port]; | |
12135 | port_of_path = 0; | |
f2e0899f DK |
12136 | } |
12137 | ||
6bbca910 | 12138 | /* Extract the ext phy address for the port */ |
a22f0788 | 12139 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 12140 | port_of_path, &phy[port]) != |
e10bc84d YR |
12141 | 0) { |
12142 | DP(NETIF_MSG_LINK, "populate_phy failed\n"); | |
12143 | return -EINVAL; | |
12144 | } | |
6bbca910 | 12145 | /* disable attentions */ |
6a71bbe0 YR |
12146 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
12147 | port_of_path*4, | |
cd88ccee YR |
12148 | (NIG_MASK_XGXS0_LINK_STATUS | |
12149 | NIG_MASK_XGXS0_LINK10G | | |
12150 | NIG_MASK_SERDES0_LINK_STATUS | | |
12151 | NIG_MASK_MI_INT)); | |
6bbca910 | 12152 | |
6bbca910 | 12153 | /* Need to take the phy out of low power mode in order |
8f73f0b9 YR |
12154 | * to write to access its registers |
12155 | */ | |
6bbca910 | 12156 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee YR |
12157 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
12158 | port); | |
6bbca910 YR |
12159 | |
12160 | /* Reset the phy */ | |
e10bc84d | 12161 | bnx2x_cl45_write(bp, &phy[port], |
cd88ccee YR |
12162 | MDIO_PMA_DEVAD, |
12163 | MDIO_PMA_REG_CTRL, | |
12164 | 1<<15); | |
6bbca910 YR |
12165 | } |
12166 | ||
12167 | /* Add delay of 150ms after reset */ | |
12168 | msleep(150); | |
12169 | ||
e10bc84d YR |
12170 | if (phy[PORT_0].addr & 0x1) { |
12171 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
12172 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
12173 | } else { | |
12174 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
12175 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
12176 | } | |
12177 | ||
6bbca910 YR |
12178 | /* PART2 - Download firmware to both phys */ |
12179 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
3c9ada22 | 12180 | if (CHIP_IS_E1x(bp)) |
f2e0899f | 12181 | port_of_path = port; |
3c9ada22 YR |
12182 | else |
12183 | port_of_path = 0; | |
6bbca910 | 12184 | |
f2e0899f DK |
12185 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
12186 | phy_blk[port]->addr); | |
5c99274b YR |
12187 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
12188 | port_of_path)) | |
6bbca910 | 12189 | return -EINVAL; |
6bbca910 YR |
12190 | |
12191 | /* Only set bit 10 = 1 (Tx power down) */ | |
e10bc84d | 12192 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12193 | MDIO_PMA_DEVAD, |
12194 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
6bbca910 YR |
12195 | |
12196 | /* Phase1 of TX_POWER_DOWN reset */ | |
e10bc84d | 12197 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12198 | MDIO_PMA_DEVAD, |
12199 | MDIO_PMA_REG_TX_POWER_DOWN, | |
12200 | (val | 1<<10)); | |
6bbca910 YR |
12201 | } |
12202 | ||
8f73f0b9 | 12203 | /* Toggle Transmitter: Power down and then up with 600ms delay |
2cf7acf9 YR |
12204 | * between |
12205 | */ | |
6bbca910 YR |
12206 | msleep(600); |
12207 | ||
12208 | /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ | |
12209 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f5372251 | 12210 | /* Phase2 of POWER_DOWN_RESET */ |
6bbca910 | 12211 | /* Release bit 10 (Release Tx power down) */ |
e10bc84d | 12212 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12213 | MDIO_PMA_DEVAD, |
12214 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
6bbca910 | 12215 | |
e10bc84d | 12216 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12217 | MDIO_PMA_DEVAD, |
12218 | MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); | |
6bbca910 YR |
12219 | msleep(15); |
12220 | ||
12221 | /* Read modify write the SPI-ROM version select register */ | |
e10bc84d | 12222 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12223 | MDIO_PMA_DEVAD, |
12224 | MDIO_PMA_REG_EDC_FFE_MAIN, &val); | |
e10bc84d | 12225 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12226 | MDIO_PMA_DEVAD, |
12227 | MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); | |
6bbca910 YR |
12228 | |
12229 | /* set GPIO2 back to LOW */ | |
12230 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 12231 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
6bbca910 YR |
12232 | } |
12233 | return 0; | |
6bbca910 | 12234 | } |
fcf5b650 YR |
12235 | static int bnx2x_8726_common_init_phy(struct bnx2x *bp, |
12236 | u32 shmem_base_path[], | |
12237 | u32 shmem2_base_path[], u8 phy_index, | |
12238 | u32 chip_id) | |
de6eae1f YR |
12239 | { |
12240 | u32 val; | |
12241 | s8 port; | |
12242 | struct bnx2x_phy phy; | |
12243 | /* Use port1 because of the static port-swap */ | |
12244 | /* Enable the module detection interrupt */ | |
12245 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); | |
12246 | val |= ((1<<MISC_REGISTERS_GPIO_3)| | |
12247 | (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); | |
12248 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); | |
12249 | ||
650154bf | 12250 | bnx2x_ext_phy_hw_reset(bp, 0); |
de6eae1f YR |
12251 | msleep(5); |
12252 | for (port = 0; port < PORT_MAX; port++) { | |
f2e0899f DK |
12253 | u32 shmem_base, shmem2_base; |
12254 | ||
12255 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 12256 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
12257 | shmem_base = shmem_base_path[0]; |
12258 | shmem2_base = shmem2_base_path[0]; | |
3c9ada22 YR |
12259 | } else { |
12260 | shmem_base = shmem_base_path[port]; | |
12261 | shmem2_base = shmem2_base_path[port]; | |
f2e0899f | 12262 | } |
de6eae1f | 12263 | /* Extract the ext phy address for the port */ |
a22f0788 | 12264 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
12265 | port, &phy) != |
12266 | 0) { | |
12267 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
12268 | return -EINVAL; | |
12269 | } | |
12270 | ||
12271 | /* Reset phy*/ | |
12272 | bnx2x_cl45_write(bp, &phy, | |
12273 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
12274 | ||
12275 | ||
12276 | /* Set fault module detected LED on */ | |
12277 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
cd88ccee YR |
12278 | MISC_REGISTERS_GPIO_HIGH, |
12279 | port); | |
de6eae1f YR |
12280 | } |
12281 | ||
12282 | return 0; | |
12283 | } | |
a8db5b4c YR |
12284 | static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, |
12285 | u8 *io_gpio, u8 *io_port) | |
12286 | { | |
12287 | ||
12288 | u32 phy_gpio_reset = REG_RD(bp, shmem_base + | |
12289 | offsetof(struct shmem_region, | |
12290 | dev_info.port_hw_config[PORT_0].default_cfg)); | |
12291 | switch (phy_gpio_reset) { | |
12292 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: | |
12293 | *io_gpio = 0; | |
12294 | *io_port = 0; | |
12295 | break; | |
12296 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: | |
12297 | *io_gpio = 1; | |
12298 | *io_port = 0; | |
12299 | break; | |
12300 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: | |
12301 | *io_gpio = 2; | |
12302 | *io_port = 0; | |
12303 | break; | |
12304 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: | |
12305 | *io_gpio = 3; | |
12306 | *io_port = 0; | |
12307 | break; | |
12308 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: | |
12309 | *io_gpio = 0; | |
12310 | *io_port = 1; | |
12311 | break; | |
12312 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: | |
12313 | *io_gpio = 1; | |
12314 | *io_port = 1; | |
12315 | break; | |
12316 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: | |
12317 | *io_gpio = 2; | |
12318 | *io_port = 1; | |
12319 | break; | |
12320 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: | |
12321 | *io_gpio = 3; | |
12322 | *io_port = 1; | |
12323 | break; | |
12324 | default: | |
12325 | /* Don't override the io_gpio and io_port */ | |
12326 | break; | |
12327 | } | |
12328 | } | |
fcf5b650 YR |
12329 | |
12330 | static int bnx2x_8727_common_init_phy(struct bnx2x *bp, | |
12331 | u32 shmem_base_path[], | |
12332 | u32 shmem2_base_path[], u8 phy_index, | |
12333 | u32 chip_id) | |
4d295db0 | 12334 | { |
a8db5b4c | 12335 | s8 port, reset_gpio; |
4d295db0 | 12336 | u32 swap_val, swap_override; |
e10bc84d YR |
12337 | struct bnx2x_phy phy[PORT_MAX]; |
12338 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
f2e0899f | 12339 | s8 port_of_path; |
cd88ccee YR |
12340 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); |
12341 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
4d295db0 | 12342 | |
a8db5b4c | 12343 | reset_gpio = MISC_REGISTERS_GPIO_1; |
a22f0788 | 12344 | port = 1; |
4d295db0 | 12345 | |
8f73f0b9 | 12346 | /* Retrieve the reset gpio/port which control the reset. |
a8db5b4c YR |
12347 | * Default is GPIO1, PORT1 |
12348 | */ | |
12349 | bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], | |
12350 | (u8 *)&reset_gpio, (u8 *)&port); | |
a22f0788 YR |
12351 | |
12352 | /* Calculate the port based on port swap */ | |
12353 | port ^= (swap_val && swap_override); | |
12354 | ||
a8db5b4c YR |
12355 | /* Initiate PHY reset*/ |
12356 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
12357 | port); | |
12358 | msleep(1); | |
12359 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, | |
12360 | port); | |
12361 | ||
a22f0788 | 12362 | msleep(5); |
bc7f0a05 | 12363 | |
4d295db0 | 12364 | /* PART1 - Reset both phys */ |
a22f0788 | 12365 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
f2e0899f DK |
12366 | u32 shmem_base, shmem2_base; |
12367 | ||
12368 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 12369 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
12370 | shmem_base = shmem_base_path[0]; |
12371 | shmem2_base = shmem2_base_path[0]; | |
12372 | port_of_path = port; | |
3c9ada22 YR |
12373 | } else { |
12374 | shmem_base = shmem_base_path[port]; | |
12375 | shmem2_base = shmem2_base_path[port]; | |
12376 | port_of_path = 0; | |
f2e0899f DK |
12377 | } |
12378 | ||
4d295db0 | 12379 | /* Extract the ext phy address for the port */ |
a22f0788 | 12380 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 12381 | port_of_path, &phy[port]) != |
e10bc84d YR |
12382 | 0) { |
12383 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
12384 | return -EINVAL; | |
12385 | } | |
4d295db0 | 12386 | /* disable attentions */ |
f2e0899f DK |
12387 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
12388 | port_of_path*4, | |
12389 | (NIG_MASK_XGXS0_LINK_STATUS | | |
12390 | NIG_MASK_XGXS0_LINK10G | | |
12391 | NIG_MASK_SERDES0_LINK_STATUS | | |
12392 | NIG_MASK_MI_INT)); | |
4d295db0 | 12393 | |
4d295db0 EG |
12394 | |
12395 | /* Reset the phy */ | |
e10bc84d | 12396 | bnx2x_cl45_write(bp, &phy[port], |
cd88ccee | 12397 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
4d295db0 EG |
12398 | } |
12399 | ||
12400 | /* Add delay of 150ms after reset */ | |
12401 | msleep(150); | |
e10bc84d YR |
12402 | if (phy[PORT_0].addr & 0x1) { |
12403 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
12404 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
12405 | } else { | |
12406 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
12407 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
12408 | } | |
4d295db0 | 12409 | /* PART2 - Download firmware to both phys */ |
e10bc84d | 12410 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
3c9ada22 | 12411 | if (CHIP_IS_E1x(bp)) |
f2e0899f | 12412 | port_of_path = port; |
3c9ada22 YR |
12413 | else |
12414 | port_of_path = 0; | |
f2e0899f DK |
12415 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
12416 | phy_blk[port]->addr); | |
5c99274b YR |
12417 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
12418 | port_of_path)) | |
4d295db0 | 12419 | return -EINVAL; |
85242eea YR |
12420 | /* Disable PHY transmitter output */ |
12421 | bnx2x_cl45_write(bp, phy_blk[port], | |
12422 | MDIO_PMA_DEVAD, | |
12423 | MDIO_PMA_REG_TX_DISABLE, 1); | |
4d295db0 | 12424 | |
5c99274b | 12425 | } |
4d295db0 EG |
12426 | return 0; |
12427 | } | |
12428 | ||
521683da YR |
12429 | static int bnx2x_84833_common_init_phy(struct bnx2x *bp, |
12430 | u32 shmem_base_path[], | |
12431 | u32 shmem2_base_path[], | |
12432 | u8 phy_index, | |
12433 | u32 chip_id) | |
12434 | { | |
12435 | u8 reset_gpios; | |
521683da YR |
12436 | reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); |
12437 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); | |
12438 | udelay(10); | |
12439 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); | |
12440 | DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", | |
12441 | reset_gpios); | |
11b2ec6b YR |
12442 | return 0; |
12443 | } | |
521683da | 12444 | |
11b2ec6b YR |
12445 | static int bnx2x_84833_pre_init_phy(struct bnx2x *bp, |
12446 | struct bnx2x_phy *phy) | |
12447 | { | |
12448 | u16 val, cnt; | |
12449 | /* Wait for FW completing its initialization. */ | |
12450 | for (cnt = 0; cnt < 1500; cnt++) { | |
12451 | bnx2x_cl45_read(bp, phy, | |
521683da YR |
12452 | MDIO_PMA_DEVAD, |
12453 | MDIO_PMA_REG_CTRL, &val); | |
11b2ec6b YR |
12454 | if (!(val & (1<<15))) |
12455 | break; | |
12456 | msleep(1); | |
12457 | } | |
12458 | if (cnt >= 1500) { | |
12459 | DP(NETIF_MSG_LINK, "84833 reset timeout\n"); | |
12460 | return -EINVAL; | |
521683da YR |
12461 | } |
12462 | ||
11b2ec6b YR |
12463 | /* Put the port in super isolate mode. */ |
12464 | bnx2x_cl45_read(bp, phy, | |
12465 | MDIO_CTL_DEVAD, | |
12466 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); | |
12467 | val |= MDIO_84833_SUPER_ISOLATE; | |
12468 | bnx2x_cl45_write(bp, phy, | |
12469 | MDIO_CTL_DEVAD, | |
12470 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); | |
12471 | ||
12472 | /* Save spirom version */ | |
12473 | bnx2x_save_848xx_spirom_version(phy, bp, PORT_0); | |
521683da YR |
12474 | return 0; |
12475 | } | |
12476 | ||
11b2ec6b YR |
12477 | int bnx2x_pre_init_phy(struct bnx2x *bp, |
12478 | u32 shmem_base, | |
12479 | u32 shmem2_base, | |
12480 | u32 chip_id) | |
12481 | { | |
12482 | int rc = 0; | |
12483 | struct bnx2x_phy phy; | |
12484 | bnx2x_set_mdio_clk(bp, chip_id, PORT_0); | |
12485 | if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base, | |
12486 | PORT_0, &phy)) { | |
12487 | DP(NETIF_MSG_LINK, "populate_phy failed\n"); | |
12488 | return -EINVAL; | |
12489 | } | |
12490 | switch (phy.type) { | |
12491 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: | |
12492 | rc = bnx2x_84833_pre_init_phy(bp, &phy); | |
12493 | break; | |
12494 | default: | |
12495 | break; | |
12496 | } | |
12497 | return rc; | |
12498 | } | |
521683da | 12499 | |
fcf5b650 YR |
12500 | static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], |
12501 | u32 shmem2_base_path[], u8 phy_index, | |
12502 | u32 ext_phy_type, u32 chip_id) | |
6bbca910 | 12503 | { |
fcf5b650 | 12504 | int rc = 0; |
6bbca910 YR |
12505 | |
12506 | switch (ext_phy_type) { | |
12507 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
f2e0899f DK |
12508 | rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, |
12509 | shmem2_base_path, | |
12510 | phy_index, chip_id); | |
6bbca910 | 12511 | break; |
e4d78f12 | 12512 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
4d295db0 EG |
12513 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
12514 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
f2e0899f DK |
12515 | rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, |
12516 | shmem2_base_path, | |
12517 | phy_index, chip_id); | |
4d295db0 EG |
12518 | break; |
12519 | ||
589abe3a | 12520 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
8f73f0b9 | 12521 | /* GPIO1 affects both ports, so there's need to pull |
2cf7acf9 YR |
12522 | * it for single port alone |
12523 | */ | |
f2e0899f DK |
12524 | rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, |
12525 | shmem2_base_path, | |
12526 | phy_index, chip_id); | |
a22f0788 | 12527 | break; |
0d40f0d4 | 12528 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
8f73f0b9 | 12529 | /* GPIO3's are linked, and so both need to be toggled |
0d40f0d4 YR |
12530 | * to obtain required 2us pulse. |
12531 | */ | |
521683da YR |
12532 | rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, |
12533 | shmem2_base_path, | |
12534 | phy_index, chip_id); | |
0d40f0d4 | 12535 | break; |
a22f0788 YR |
12536 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: |
12537 | rc = -EINVAL; | |
4f60dab1 | 12538 | break; |
6bbca910 YR |
12539 | default: |
12540 | DP(NETIF_MSG_LINK, | |
2cf7acf9 YR |
12541 | "ext_phy 0x%x common init not required\n", |
12542 | ext_phy_type); | |
6bbca910 YR |
12543 | break; |
12544 | } | |
12545 | ||
6d870c39 YR |
12546 | if (rc != 0) |
12547 | netdev_err(bp->dev, "Warning: PHY was not initialized," | |
12548 | " Port %d\n", | |
12549 | 0); | |
6bbca910 YR |
12550 | return rc; |
12551 | } | |
12552 | ||
fcf5b650 YR |
12553 | int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], |
12554 | u32 shmem2_base_path[], u32 chip_id) | |
a22f0788 | 12555 | { |
fcf5b650 | 12556 | int rc = 0; |
3c9ada22 YR |
12557 | u32 phy_ver, val; |
12558 | u8 phy_index = 0; | |
a22f0788 | 12559 | u32 ext_phy_type, ext_phy_config; |
a198c142 YR |
12560 | bnx2x_set_mdio_clk(bp, chip_id, PORT_0); |
12561 | bnx2x_set_mdio_clk(bp, chip_id, PORT_1); | |
a22f0788 | 12562 | DP(NETIF_MSG_LINK, "Begin common phy init\n"); |
3c9ada22 YR |
12563 | if (CHIP_IS_E3(bp)) { |
12564 | /* Enable EPIO */ | |
12565 | val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); | |
12566 | REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); | |
12567 | } | |
b21a3424 YR |
12568 | /* Check if common init was already done */ |
12569 | phy_ver = REG_RD(bp, shmem_base_path[0] + | |
12570 | offsetof(struct shmem_region, | |
12571 | port_mb[PORT_0].ext_phy_fw_version)); | |
12572 | if (phy_ver) { | |
12573 | DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", | |
12574 | phy_ver); | |
12575 | return 0; | |
12576 | } | |
12577 | ||
a22f0788 YR |
12578 | /* Read the ext_phy_type for arbitrary port(0) */ |
12579 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
12580 | phy_index++) { | |
12581 | ext_phy_config = bnx2x_get_ext_phy_config(bp, | |
f2e0899f | 12582 | shmem_base_path[0], |
a22f0788 YR |
12583 | phy_index, 0); |
12584 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
f2e0899f DK |
12585 | rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, |
12586 | shmem2_base_path, | |
12587 | phy_index, ext_phy_type, | |
12588 | chip_id); | |
a22f0788 YR |
12589 | } |
12590 | return rc; | |
12591 | } | |
d90d96ba | 12592 | |
3deb8167 YR |
12593 | static void bnx2x_check_over_curr(struct link_params *params, |
12594 | struct link_vars *vars) | |
12595 | { | |
12596 | struct bnx2x *bp = params->bp; | |
12597 | u32 cfg_pin; | |
12598 | u8 port = params->port; | |
12599 | u32 pin_val; | |
12600 | ||
12601 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
12602 | offsetof(struct shmem_region, | |
12603 | dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & | |
12604 | PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> | |
12605 | PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; | |
12606 | ||
12607 | /* Ignore check if no external input PIN available */ | |
12608 | if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) | |
12609 | return; | |
12610 | ||
12611 | if (!pin_val) { | |
12612 | if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { | |
12613 | netdev_err(bp->dev, "Error: Power fault on Port %d has" | |
12614 | " been detected and the power to " | |
12615 | "that SFP+ module has been removed" | |
12616 | " to prevent failure of the card." | |
12617 | " Please remove the SFP+ module and" | |
12618 | " restart the system to clear this" | |
12619 | " error.\n", | |
12620 | params->port); | |
12621 | vars->phy_flags |= PHY_OVER_CURRENT_FLAG; | |
12622 | } | |
12623 | } else | |
12624 | vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; | |
12625 | } | |
12626 | ||
12627 | static void bnx2x_analyze_link_error(struct link_params *params, | |
55098c5c YR |
12628 | struct link_vars *vars, u32 lss_status, |
12629 | u8 notify) | |
3deb8167 YR |
12630 | { |
12631 | struct bnx2x *bp = params->bp; | |
12632 | /* Compare new value with previous value */ | |
12633 | u8 led_mode; | |
12634 | u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0; | |
12635 | ||
3deb8167 YR |
12636 | if ((lss_status ^ half_open_conn) == 0) |
12637 | return; | |
12638 | ||
12639 | /* If values differ */ | |
12640 | DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up, | |
12641 | half_open_conn, lss_status); | |
12642 | ||
8f73f0b9 | 12643 | /* a. Update shmem->link_status accordingly |
3deb8167 YR |
12644 | * b. Update link_vars->link_up |
12645 | */ | |
12646 | if (lss_status) { | |
de6f3377 | 12647 | DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n"); |
3deb8167 YR |
12648 | vars->link_status &= ~LINK_STATUS_LINK_UP; |
12649 | vars->link_up = 0; | |
12650 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
55098c5c YR |
12651 | |
12652 | /* activate nig drain */ | |
12653 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); | |
8f73f0b9 | 12654 | /* Set LED mode to off since the PHY doesn't know about these |
3deb8167 YR |
12655 | * errors |
12656 | */ | |
12657 | led_mode = LED_MODE_OFF; | |
12658 | } else { | |
de6f3377 | 12659 | DP(NETIF_MSG_LINK, "Remote Fault cleared\n"); |
3deb8167 YR |
12660 | vars->link_status |= LINK_STATUS_LINK_UP; |
12661 | vars->link_up = 1; | |
12662 | vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; | |
12663 | led_mode = LED_MODE_OPER; | |
55098c5c YR |
12664 | |
12665 | /* Clear nig drain */ | |
12666 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
3deb8167 | 12667 | } |
55098c5c | 12668 | bnx2x_sync_link(params, vars); |
3deb8167 YR |
12669 | /* Update the LED according to the link state */ |
12670 | bnx2x_set_led(params, vars, led_mode, SPEED_10000); | |
12671 | ||
12672 | /* Update link status in the shared memory */ | |
12673 | bnx2x_update_mng(params, vars->link_status); | |
12674 | ||
12675 | /* C. Trigger General Attention */ | |
12676 | vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; | |
55098c5c YR |
12677 | if (notify) |
12678 | bnx2x_notify_link_changed(bp); | |
3deb8167 YR |
12679 | } |
12680 | ||
de6f3377 YR |
12681 | /****************************************************************************** |
12682 | * Description: | |
12683 | * This function checks for half opened connection change indication. | |
12684 | * When such change occurs, it calls the bnx2x_analyze_link_error | |
12685 | * to check if Remote Fault is set or cleared. Reception of remote fault | |
12686 | * status message in the MAC indicates that the peer's MAC has detected | |
12687 | * a fault, for example, due to break in the TX side of fiber. | |
12688 | * | |
12689 | ******************************************************************************/ | |
55098c5c YR |
12690 | int bnx2x_check_half_open_conn(struct link_params *params, |
12691 | struct link_vars *vars, | |
12692 | u8 notify) | |
3deb8167 YR |
12693 | { |
12694 | struct bnx2x *bp = params->bp; | |
12695 | u32 lss_status = 0; | |
12696 | u32 mac_base; | |
12697 | /* In case link status is physically up @ 10G do */ | |
55098c5c YR |
12698 | if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || |
12699 | (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) | |
12700 | return 0; | |
3deb8167 | 12701 | |
de6f3377 | 12702 | if (CHIP_IS_E3(bp) && |
3deb8167 | 12703 | (REG_RD(bp, MISC_REG_RESET_REG_2) & |
de6f3377 YR |
12704 | (MISC_REGISTERS_RESET_REG_2_XMAC))) { |
12705 | /* Check E3 XMAC */ | |
8f73f0b9 | 12706 | /* Note that link speed cannot be queried here, since it may be |
de6f3377 YR |
12707 | * zero while link is down. In case UMAC is active, LSS will |
12708 | * simply not be set | |
12709 | */ | |
12710 | mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
12711 | ||
12712 | /* Clear stick bits (Requires rising edge) */ | |
12713 | REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); | |
12714 | REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, | |
12715 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | | |
12716 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); | |
12717 | if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) | |
12718 | lss_status = 1; | |
12719 | ||
55098c5c | 12720 | bnx2x_analyze_link_error(params, vars, lss_status, notify); |
de6f3377 YR |
12721 | } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & |
12722 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { | |
3deb8167 YR |
12723 | /* Check E1X / E2 BMAC */ |
12724 | u32 lss_status_reg; | |
12725 | u32 wb_data[2]; | |
12726 | mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
12727 | NIG_REG_INGRESS_BMAC0_MEM; | |
12728 | /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ | |
12729 | if (CHIP_IS_E2(bp)) | |
12730 | lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; | |
12731 | else | |
12732 | lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; | |
12733 | ||
12734 | REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); | |
12735 | lss_status = (wb_data[0] > 0); | |
12736 | ||
55098c5c | 12737 | bnx2x_analyze_link_error(params, vars, lss_status, notify); |
3deb8167 | 12738 | } |
55098c5c | 12739 | return 0; |
3deb8167 YR |
12740 | } |
12741 | ||
12742 | void bnx2x_period_func(struct link_params *params, struct link_vars *vars) | |
12743 | { | |
de6f3377 | 12744 | u16 phy_idx; |
55098c5c | 12745 | struct bnx2x *bp = params->bp; |
de6f3377 YR |
12746 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { |
12747 | if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { | |
12748 | bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); | |
55098c5c YR |
12749 | if (bnx2x_check_half_open_conn(params, vars, 1) != |
12750 | 0) | |
12751 | DP(NETIF_MSG_LINK, "Fault detection failed\n"); | |
de6f3377 YR |
12752 | break; |
12753 | } | |
12754 | } | |
12755 | ||
a9077bfd YR |
12756 | if (CHIP_IS_E3(bp)) { |
12757 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; | |
12758 | bnx2x_set_aer_mmd(params, phy); | |
3deb8167 | 12759 | bnx2x_check_over_curr(params, vars); |
a9077bfd YR |
12760 | bnx2x_warpcore_config_runtime(phy, params, vars); |
12761 | } | |
12762 | ||
3deb8167 YR |
12763 | } |
12764 | ||
a22f0788 | 12765 | u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base) |
d90d96ba YR |
12766 | { |
12767 | u8 phy_index; | |
12768 | struct bnx2x_phy phy; | |
12769 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
12770 | phy_index++) { | |
a22f0788 | 12771 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
d90d96ba YR |
12772 | 0, &phy) != 0) { |
12773 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
12774 | return 0; | |
12775 | } | |
12776 | ||
12777 | if (phy.flags & FLAGS_HW_LOCK_REQUIRED) | |
12778 | return 1; | |
12779 | } | |
12780 | return 0; | |
12781 | } | |
12782 | ||
12783 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, | |
12784 | u32 shmem_base, | |
a22f0788 | 12785 | u32 shmem2_base, |
d90d96ba YR |
12786 | u8 port) |
12787 | { | |
12788 | u8 phy_index, fan_failure_det_req = 0; | |
12789 | struct bnx2x_phy phy; | |
12790 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
12791 | phy_index++) { | |
a22f0788 | 12792 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
d90d96ba YR |
12793 | port, &phy) |
12794 | != 0) { | |
12795 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
12796 | return 0; | |
12797 | } | |
12798 | fan_failure_det_req |= (phy.flags & | |
12799 | FLAGS_FAN_FAILURE_DET_REQ); | |
12800 | } | |
12801 | return fan_failure_det_req; | |
12802 | } | |
12803 | ||
12804 | void bnx2x_hw_reset_phy(struct link_params *params) | |
12805 | { | |
12806 | u8 phy_index; | |
985848f8 YR |
12807 | struct bnx2x *bp = params->bp; |
12808 | bnx2x_update_mng(params, 0); | |
12809 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, | |
12810 | (NIG_MASK_XGXS0_LINK_STATUS | | |
12811 | NIG_MASK_XGXS0_LINK10G | | |
12812 | NIG_MASK_SERDES0_LINK_STATUS | | |
12813 | NIG_MASK_MI_INT)); | |
12814 | ||
12815 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
d90d96ba YR |
12816 | phy_index++) { |
12817 | if (params->phy[phy_index].hw_reset) { | |
12818 | params->phy[phy_index].hw_reset( | |
12819 | ¶ms->phy[phy_index], | |
12820 | params); | |
12821 | params->phy[phy_index] = phy_null; | |
12822 | } | |
12823 | } | |
12824 | } | |
020c7e3f YR |
12825 | |
12826 | void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, | |
12827 | u32 chip_id, u32 shmem_base, u32 shmem2_base, | |
12828 | u8 port) | |
12829 | { | |
12830 | u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; | |
12831 | u32 val; | |
12832 | u32 offset, aeu_mask, swap_val, swap_override, sync_offset; | |
3c9ada22 YR |
12833 | if (CHIP_IS_E3(bp)) { |
12834 | if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, | |
12835 | shmem_base, | |
12836 | port, | |
12837 | &gpio_num, | |
12838 | &gpio_port) != 0) | |
12839 | return; | |
12840 | } else { | |
020c7e3f YR |
12841 | struct bnx2x_phy phy; |
12842 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
12843 | phy_index++) { | |
12844 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, | |
12845 | shmem2_base, port, &phy) | |
12846 | != 0) { | |
12847 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
12848 | return; | |
12849 | } | |
12850 | if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { | |
12851 | gpio_num = MISC_REGISTERS_GPIO_3; | |
12852 | gpio_port = port; | |
12853 | break; | |
12854 | } | |
12855 | } | |
12856 | } | |
12857 | ||
12858 | if (gpio_num == 0xff) | |
12859 | return; | |
12860 | ||
12861 | /* Set GPIO3 to trigger SFP+ module insertion/removal */ | |
12862 | bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); | |
12863 | ||
12864 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
12865 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
12866 | gpio_port ^= (swap_val && swap_override); | |
12867 | ||
12868 | vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << | |
12869 | (gpio_num + (gpio_port << 2)); | |
12870 | ||
12871 | sync_offset = shmem_base + | |
12872 | offsetof(struct shmem_region, | |
12873 | dev_info.port_hw_config[port].aeu_int_mask); | |
12874 | REG_WR(bp, sync_offset, vars->aeu_int_mask); | |
12875 | ||
12876 | DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", | |
12877 | gpio_num, gpio_port, vars->aeu_int_mask); | |
12878 | ||
12879 | if (port == 0) | |
12880 | offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; | |
12881 | else | |
12882 | offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; | |
12883 | ||
12884 | /* Open appropriate AEU for interrupts */ | |
12885 | aeu_mask = REG_RD(bp, offset); | |
12886 | aeu_mask |= vars->aeu_int_mask; | |
12887 | REG_WR(bp, offset, aeu_mask); | |
12888 | ||
12889 | /* Enable the GPIO to trigger interrupt */ | |
12890 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); | |
12891 | val |= 1 << (gpio_num + (gpio_port << 2)); | |
12892 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); | |
12893 | } |