[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_link.h

/* Copyright 2008-2012 Broadcom Corporation
 *
 * Unless you and Broadcom execute a separate written software license
 * agreement governing use of this software, this software is licensed to you
 * under the terms of the GNU General Public License version 2, available
 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
 *
 * Notwithstanding the above, under no circumstances may you combine this
 * software in any way with any other Broadcom software provided under a
 * license other than the GPL, without Broadcom's express prior written
 * consent.
 *
 * Written by Yaniv Rosner
 *
 */

#ifndef BNX2X_LINK_H
#define BNX2X_LINK_H


/***********************************************************/
/*                         Defines                         */
/***********************************************************/
#define DEFAULT_PHY_DEV_ADDR	3
#define E2_DEFAULT_PHY_DEV_ADDR	5


#define BNX2X_FLOW_CTRL_AUTO		PORT_FEATURE_FLOW_CONTROL_AUTO
#define BNX2X_FLOW_CTRL_TX		PORT_FEATURE_FLOW_CONTROL_TX
#define BNX2X_FLOW_CTRL_RX		PORT_FEATURE_FLOW_CONTROL_RX
#define BNX2X_FLOW_CTRL_BOTH		PORT_FEATURE_FLOW_CONTROL_BOTH
#define BNX2X_FLOW_CTRL_NONE		PORT_FEATURE_FLOW_CONTROL_NONE

#define NET_SERDES_IF_XFI		1
#define NET_SERDES_IF_SFI		2
#define NET_SERDES_IF_KR		3
#define NET_SERDES_IF_DXGXS	4

#define SPEED_AUTO_NEG		0
#define SPEED_20000		20000

#define SFP_EEPROM_PAGE_SIZE			16
#define SFP_EEPROM_VENDOR_NAME_ADDR		0x14
#define SFP_EEPROM_VENDOR_NAME_SIZE		16
#define SFP_EEPROM_VENDOR_OUI_ADDR		0x25
#define SFP_EEPROM_VENDOR_OUI_SIZE		3
#define SFP_EEPROM_PART_NO_ADDR			0x28
#define SFP_EEPROM_PART_NO_SIZE			16
#define SFP_EEPROM_REVISION_ADDR		0x38
#define SFP_EEPROM_REVISION_SIZE		4
#define SFP_EEPROM_SERIAL_ADDR			0x44
#define SFP_EEPROM_SERIAL_SIZE			16
#define SFP_EEPROM_DATE_ADDR			0x54 /* ASCII YYMMDD */
#define SFP_EEPROM_DATE_SIZE			6
#define PWR_FLT_ERR_MSG_LEN			250

#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
		((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
		(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
		 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
		((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)

/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
#define SINGLE_MEDIA_DIRECT(params)	(params->num_phys == 1)
/* Single Media board contains single external phy */
#define SINGLE_MEDIA(params)		(params->num_phys == 2)
/* Dual Media board contains two external phy with different media */
#define DUAL_MEDIA(params)		(params->num_phys == 3)

#define FW_PARAM_PHY_ADDR_MASK		0x000000FF
#define FW_PARAM_PHY_TYPE_MASK		0x0000FF00
#define FW_PARAM_MDIO_CTRL_MASK		0xFFFF0000
#define FW_PARAM_MDIO_CTRL_OFFSET		16
#define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
					   FW_PARAM_PHY_ADDR_MASK)
#define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
					   FW_PARAM_PHY_TYPE_MASK)
#define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
					    FW_PARAM_MDIO_CTRL_MASK) >> \
					    FW_PARAM_MDIO_CTRL_OFFSET)
#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
	(phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)


#define PFC_BRB_FULL_LB_XOFF_THRESHOLD				170
#define PFC_BRB_FULL_LB_XON_THRESHOLD				250

#define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))

#define BMAC_CONTROL_RX_ENABLE		2
/***********************************************************/
/*                         Structs                         */
/***********************************************************/
#define INT_PHY		0
#define EXT_PHY1	1
#define EXT_PHY2	2
#define MAX_PHYS	3

/* Same configuration is shared between the XGXS and the first external phy */
#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
					 0 : (_phy_idx - 1))
/***********************************************************/
/*                      bnx2x_phy struct                     */
/*  Defines the required arguments and function per phy    */
/***********************************************************/
struct link_vars;
struct link_params;
struct bnx2x_phy;

typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
			    struct link_vars *vars);
typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
			    struct link_vars *vars);
typedef void (*link_reset_t)(struct bnx2x_phy *phy,
			     struct link_params *params);
typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
				  struct link_params *params);
typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
			       struct link_params *params, u8 mode);
typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
				    struct link_params *params, u32 action);
struct bnx2x_reg_set {
	u8  devad;
	u16 reg;
	u16 val;
};

struct bnx2x_phy {
	u32 type;

	/* Loaded during init */
	u8 addr;
	u8 def_md_devad;
	u16 flags;
	/* Require HW lock */
#define FLAGS_HW_LOCK_REQUIRED		(1<<0)
	/* No Over-Current detection */
#define FLAGS_NOC			(1<<1)
	/* Fan failure detection required */
#define FLAGS_FAN_FAILURE_DET_REQ	(1<<2)
	/* Initialize first the XGXS and only then the phy itself */
#define FLAGS_INIT_XGXS_FIRST		(1<<3)
#define FLAGS_WC_DUAL_MODE		(1<<4)
#define FLAGS_4_PORT_MODE		(1<<5)
#define FLAGS_REARM_LATCH_SIGNAL	(1<<6)
#define FLAGS_SFP_NOT_APPROVED		(1<<7)
#define FLAGS_MDC_MDIO_WA		(1<<8)
#define FLAGS_DUMMY_READ		(1<<9)
#define FLAGS_MDC_MDIO_WA_B0		(1<<10)
#define FLAGS_TX_ERROR_CHECK		(1<<12)
#define FLAGS_EEE			(1<<13)

	/* preemphasis values for the rx side */
	u16 rx_preemphasis[4];

	/* preemphasis values for the tx side */
	u16 tx_preemphasis[4];

	/* EMAC address for access MDIO */
	u32 mdio_ctrl;

	u32 supported;

	u32 media_type;
#define	ETH_PHY_UNSPECIFIED	0x0
#define	ETH_PHY_SFPP_10G_FIBER	0x1
#define	ETH_PHY_XFP_FIBER		0x2
#define	ETH_PHY_DA_TWINAX		0x3
#define	ETH_PHY_BASE_T		0x4
#define	ETH_PHY_SFP_1G_FIBER	0x5
#define	ETH_PHY_KR		0xf0
#define	ETH_PHY_CX4		0xf1
#define	ETH_PHY_NOT_PRESENT	0xff

	/* The address in which version is located*/
	u32 ver_addr;

	u16 req_flow_ctrl;

	u16 req_line_speed;

	u32 speed_cap_mask;

	u16 req_duplex;
	u16 rsrv;
	/* Called per phy/port init, and it configures LASI, speed, autoneg,
	 duplex, flow control negotiation, etc. */
	config_init_t config_init;

	/* Called due to interrupt. It determines the link, speed */
	read_status_t read_status;

	/* Called when driver is unloading. Should reset the phy */
	link_reset_t link_reset;

	/* Set the loopback configuration for the phy */
	config_loopback_t config_loopback;

	/* Format the given raw number into str up to len */
	format_fw_ver_t format_fw_ver;

	/* Reset the phy (both ports) */
	hw_reset_t hw_reset;

	/* Set link led mode (on/off/oper)*/
	set_link_led_t set_link_led;

	/* PHY Specific tasks */
	phy_specific_func_t phy_specific_func;
#define DISABLE_TX	1
#define ENABLE_TX	2
#define PHY_INIT	3
};

/* Inputs parameters to the CLC */
struct link_params {

	u8 port;

	/* Default / User Configuration */
	u8 loopback_mode;
#define LOOPBACK_NONE		0
#define LOOPBACK_EMAC		1
#define LOOPBACK_BMAC		2
#define LOOPBACK_XGXS		3
#define LOOPBACK_EXT_PHY	4
#define LOOPBACK_EXT		5
#define LOOPBACK_UMAC		6
#define LOOPBACK_XMAC		7

	/* Device parameters */
	u8 mac_addr[6];

	u16 req_duplex[LINK_CONFIG_SIZE];
	u16 req_flow_ctrl[LINK_CONFIG_SIZE];

	u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */

	/* shmem parameters */
	u32 shmem_base;
	u32 shmem2_base;
	u32 speed_cap_mask[LINK_CONFIG_SIZE];
	u32 switch_cfg;
#define SWITCH_CFG_1G		PORT_FEATURE_CON_SWITCH_1G_SWITCH
#define SWITCH_CFG_10G		PORT_FEATURE_CON_SWITCH_10G_SWITCH
#define SWITCH_CFG_AUTO_DETECT	PORT_FEATURE_CON_SWITCH_AUTO_DETECT

	u32 lane_config;

	/* Phy register parameter */
	u32 chip_id;

	/* features */
	u32 feature_config_flags;
#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED	(1<<0)
#define FEATURE_CONFIG_PFC_ENABLED			(1<<1)
#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY		(1<<2)
#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY	(1<<3)
#define FEATURE_CONFIG_BC_SUPPORTS_AFEX			(1<<8)
#define FEATURE_CONFIG_AUTOGREEEN_ENABLED			(1<<9)
#define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED		(1<<10)
#define FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET		(1<<11)
	/* Will be populated during common init */
	struct bnx2x_phy phy[MAX_PHYS];

	/* Will be populated during common init */
	u8 num_phys;

	u8 rsrv;

	/* Used to configure the EEE Tx LPI timer, has several modes of
	 * operation, according to bits 29:28 -
	 * 2'b00: Timer will be configured by nvram, output will be the value
	 *        from nvram.
	 * 2'b01: Timer will be configured by nvram, output will be in
	 *        microseconds.
	 * 2'b10: bits 1:0 contain an nvram value which will be used instead
	 *        of the one located in the nvram. Output will be that value.
	 * 2'b11: bits 19:0 contain the idle timer in microseconds; output
	 *        will be in microseconds.
	 * Bits 31:30 should be 2'b11 in order for EEE to be enabled.
	 */
	u32 eee_mode;
#define EEE_MODE_NVRAM_BALANCED_TIME		(0xa00)
#define EEE_MODE_NVRAM_AGGRESSIVE_TIME		(0x100)
#define EEE_MODE_NVRAM_LATENCY_TIME		(0x6000)
#define EEE_MODE_NVRAM_MASK		(0x3)
#define EEE_MODE_TIMER_MASK		(0xfffff)
#define EEE_MODE_OUTPUT_TIME		(1<<28)
#define EEE_MODE_OVERRIDE_NVRAM		(1<<29)
#define EEE_MODE_ENABLE_LPI		(1<<30)
#define EEE_MODE_ADV_LPI			(1<<31)

	u16 hw_led_mode; /* part of the hw_config read from the shmem */
	u32 multi_phy_config;

	/* Device pointer passed to all callback functions */
	struct bnx2x *bp;
	u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
				req_flow_ctrl is set to AUTO */
	u16 rsrv1;
	u32 lfa_base;
};

/* Output parameters */
struct link_vars {
	u8 phy_flags;
#define PHY_XGXS_FLAG			(1<<0)
#define PHY_SGMII_FLAG			(1<<1)
#define PHY_PHYSICAL_LINK_FLAG		(1<<2)
#define PHY_HALF_OPEN_CONN_FLAG		(1<<3)
#define PHY_OVER_CURRENT_FLAG		(1<<4)
#define PHY_SFP_TX_FAULT_FLAG		(1<<5)

	u8 mac_type;
#define MAC_TYPE_NONE		0
#define MAC_TYPE_EMAC		1
#define MAC_TYPE_BMAC		2
#define MAC_TYPE_UMAC		3
#define MAC_TYPE_XMAC		4

	u8 phy_link_up; /* internal phy link indication */
	u8 link_up;

	u16 line_speed;
	u16 duplex;

	u16 flow_ctrl;
	u16 ieee_fc;

	/* The same definitions as the shmem parameter */
	u32 link_status;
	u32 eee_status;
	u8 fault_detected;
	u8 rsrv1;
	u16 periodic_flags;
#define PERIODIC_FLAGS_LINK_EVENT	0x0001

	u32 aeu_int_mask;
	u8 rx_tx_asic_rst;
	u8 turn_to_run_wc_rt;
	u16 rsrv2;
};

/***********************************************************/
/*                         Functions                       */
/***********************************************************/
int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);

/* Reset the link. Should be called when driver or interface goes down
   Before calling phy firmware upgrade, the reset_ext_phy should be set
   to 0 */
int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
		     u8 reset_ext_phy);
int bnx2x_lfa_reset(struct link_params *params, struct link_vars *vars);
/* bnx2x_link_update should be called upon link interrupt */
int bnx2x_link_update(struct link_params *params, struct link_vars *vars);

/* use the following phy functions to read/write from external_phy
  In order to use it to read/write internal phy registers, use
  DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
  the register */
int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
		   u8 devad, u16 reg, u16 *ret_val);

int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
		    u8 devad, u16 reg, u16 val);

/* Reads the link_status from the shmem,
   and update the link vars accordingly */
void bnx2x_link_status_update(struct link_params *input,
			    struct link_vars *output);
/* returns string representing the fw_version of the external phy */
int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
				 u16 len);

/* Set/Unset the led
   Basically, the CLC takes care of the led for the link, but in case one needs
   to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
   blink the led, and LED_MODE_OFF to set the led off.*/
int bnx2x_set_led(struct link_params *params,
		  struct link_vars *vars, u8 mode, u32 speed);
#define LED_MODE_OFF			0
#define LED_MODE_ON			1
#define LED_MODE_OPER			2
#define LED_MODE_FRONT_PANEL_OFF	3

/* bnx2x_handle_module_detect_int should be called upon module detection
   interrupt */
void bnx2x_handle_module_detect_int(struct link_params *params);

/* Get the actual link status. In case it returns 0, link is up,
	otherwise link is down*/
int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
		    u8 is_serdes);

/* One-time initialization for external phy after power up */
int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
			  u32 shmem2_base_path[], u32 chip_id);

/* Reset the external PHY using GPIO */
void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);

/* Reset the external of SFX7101 */
void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);

/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
				 struct link_params *params, u16 addr,
				 u8 byte_cnt, u8 *o_buf);

void bnx2x_hw_reset_phy(struct link_params *params);

/* Checks if HW lock is required for this phy/board type */
u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
			  u32 shmem2_base);

/* Check swap bit and adjust PHY order */
u32 bnx2x_phy_selection(struct link_params *params);

/* Probe the phys on board, and populate them in "params" */
int bnx2x_phy_probe(struct link_params *params);

/* Checks if fan failure detection is required on one of the phys on board */
u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
			     u32 shmem2_base, u8 port);


/* DCBX structs */

/* Number of maximum COS per chip */
#define DCBX_E2E3_MAX_NUM_COS		(2)
#define DCBX_E3B0_MAX_NUM_COS_PORT0	(6)
#define DCBX_E3B0_MAX_NUM_COS_PORT1	(3)
#define DCBX_E3B0_MAX_NUM_COS		( \
			MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
			    DCBX_E3B0_MAX_NUM_COS_PORT1))

#define DCBX_MAX_NUM_COS			( \
			MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
			    DCBX_E2E3_MAX_NUM_COS))

/* PFC port configuration params */
struct bnx2x_nig_brb_pfc_port_params {
	/* NIG */
	u32 pause_enable;
	u32 llfc_out_en;
	u32 llfc_enable;
	u32 pkt_priority_to_cos;
	u8 num_of_rx_cos_priority_mask;
	u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
	u32 llfc_high_priority_classes;
	u32 llfc_low_priority_classes;
	/* BRB */
	u32 cos0_pauseable;
	u32 cos1_pauseable;
};


/* ETS port configuration params */
struct bnx2x_ets_bw_params {
	u8 bw;
};

struct bnx2x_ets_sp_params {
	/**
	 * valid values are 0 - 5. 0 is highest strict priority.
	 * There can't be two COS's with the same pri.
	 */
	u8 pri;
};

enum bnx2x_cos_state {
	bnx2x_cos_state_strict = 0,
	bnx2x_cos_state_bw = 1,
};

struct bnx2x_ets_cos_params {
	enum bnx2x_cos_state state ;
	union {
		struct bnx2x_ets_bw_params bw_params;
		struct bnx2x_ets_sp_params sp_params;
	} params;
};

struct bnx2x_ets_params {
	u8 num_of_cos; /* Number of valid COS entries*/
	struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS];
};

/* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
 * when link is already up
 */
int bnx2x_update_pfc(struct link_params *params,
		      struct link_vars *vars,
		      struct bnx2x_nig_brb_pfc_port_params *pfc_params);


/* Used to configure the ETS to disable */
int bnx2x_ets_disabled(struct link_params *params,
		       struct link_vars *vars);

/* Used to configure the ETS to BW limited */
void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
			const u32 cos1_bw);

/* Used to configure the ETS to strict */
int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);


/*  Configure the COS to ETS according to BW and SP settings.*/
int bnx2x_ets_e3b0_config(const struct link_params *params,
			 const struct link_vars *vars,
			 struct bnx2x_ets_params *ets_params);
/* Read pfc statistic*/
void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
						 u32 pfc_frames_sent[2],
						 u32 pfc_frames_received[2]);
void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
			    u32 chip_id, u32 shmem_base, u32 shmem2_base,
			    u8 port);

int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
			       struct link_params *params);

void bnx2x_period_func(struct link_params *params, struct link_vars *vars);

int bnx2x_check_half_open_conn(struct link_params *params,
			       struct link_vars *vars, u8 notify);
#endif /* BNX2X_LINK_H */
Commit	Line	Data
85b26ea1	1	/* Copyright 2008-2012 Broadcom Corporation
ea4e040a YR	2	*
	3	* Unless you and Broadcom execute a separate written software license
	4	* agreement governing use of this software, this software is licensed to you
	5	* under the terms of the GNU General Public License version 2, available
	6	* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
	7	*
	8	* Notwithstanding the above, under no circumstances may you combine this
	9	* software in any way with any other Broadcom software provided under a
	10	* license other than the GPL, without Broadcom's express prior written
	11	* consent.
	12	*
	13	* Written by Yaniv Rosner
	14	*
	15	*/
	16
	17	#ifndef BNX2X_LINK_H
	18	#define BNX2X_LINK_H
	19
	20
	21
	22	/***********************************************************/
	23	/* Defines */
	24	/***********************************************************/
f2e0899f DK	25	#define DEFAULT_PHY_DEV_ADDR 3
f2e0899f DK	26	#define E2_DEFAULT_PHY_DEV_ADDR 5
ea4e040a YR	27
	28
	29
c0700f90 DM	30	#define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
	31	#define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
	32	#define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
	33	#define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
	34	#define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
ea4e040a	35
3c9ada22 YR	36	#define NET_SERDES_IF_XFI 1
	37	#define NET_SERDES_IF_SFI 2
	38	#define NET_SERDES_IF_KR 3
	39	#define NET_SERDES_IF_DXGXS 4
	40
cd88ccee	41	#define SPEED_AUTO_NEG 0
3c9ada22	42	#define SPEED_20000 20000
ea4e040a	43
24ea818e	44	#define SFP_EEPROM_PAGE_SIZE 16
4d295db0 EG	45	#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
	46	#define SFP_EEPROM_VENDOR_NAME_SIZE 16
	47	#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
	48	#define SFP_EEPROM_VENDOR_OUI_SIZE 3
cd88ccee YR	49	#define SFP_EEPROM_PART_NO_ADDR 0x28
cd88ccee YR	50	#define SFP_EEPROM_PART_NO_SIZE 16
3c9ada22 YR	51	#define SFP_EEPROM_REVISION_ADDR 0x38
	52	#define SFP_EEPROM_REVISION_SIZE 4
	53	#define SFP_EEPROM_SERIAL_ADDR 0x44
	54	#define SFP_EEPROM_SERIAL_SIZE 16
	55	#define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
	56	#define SFP_EEPROM_DATE_SIZE 6
4d295db0	57	#define PWR_FLT_ERR_MSG_LEN 250
b7737c9b YR	58
	59	#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
	60	((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
	61	#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
	62	(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
	63	PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
	64	#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
	65	((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
	66
e10bc84d YR	67	/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
	68	#define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
	69	/* Single Media board contains single external phy */
	70	#define SINGLE_MEDIA(params) (params->num_phys == 2)
a22f0788 YR	71	/* Dual Media board contains two external phy with different media */
a22f0788 YR	72	#define DUAL_MEDIA(params) (params->num_phys == 3)
3c9ada22 YR	73
	74	#define FW_PARAM_PHY_ADDR_MASK 0x000000FF
	75	#define FW_PARAM_PHY_TYPE_MASK 0x0000FF00
	76	#define FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
cd88ccee	77	#define FW_PARAM_MDIO_CTRL_OFFSET 16
3c9ada22 YR	78	#define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
	79	FW_PARAM_PHY_ADDR_MASK)
	80	#define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
	81	FW_PARAM_PHY_TYPE_MASK)
	82	#define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
	83	FW_PARAM_MDIO_CTRL_MASK) >> \
	84	FW_PARAM_MDIO_CTRL_OFFSET)
a22f0788 YR	85	#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
a22f0788 YR	86	(phy_addr \| phy_type \| mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
bcab15c5	87
bcab15c5 VZ	88
	89	#define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
	90	#define PFC_BRB_FULL_LB_XON_THRESHOLD 250
	91
619c5cb6	92	#define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
452427b0 YM	93
452427b0 YM	94	#define BMAC_CONTROL_RX_ENABLE 2
ea4e040a YR	95	/***********************************************************/
	96	/* Structs */
	97	/***********************************************************/
e10bc84d YR	98	#define INT_PHY 0
e10bc84d YR	99	#define EXT_PHY1 1
a22f0788 YR	100	#define EXT_PHY2 2
a22f0788 YR	101	#define MAX_PHYS 3
e10bc84d	102
b7737c9b YR	103	/* Same configuration is shared between the XGXS and the first external phy */
	104	#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
	105	#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
	106	0 : (_phy_idx - 1))
e10bc84d YR	107	/***********************************************************/
	108	/* bnx2x_phy struct */
	109	/* Defines the required arguments and function per phy */
	110	/***********************************************************/
	111	struct link_vars;
	112	struct link_params;
	113	struct bnx2x_phy;
	114
b7737c9b YR	115	typedef u8 (config_init_t)(struct bnx2x_phy phy, struct link_params *params,
	116	struct link_vars *vars);
	117	typedef u8 (read_status_t)(struct bnx2x_phy phy, struct link_params *params,
	118	struct link_vars *vars);
	119	typedef void (link_reset_t)(struct bnx2x_phy phy,
	120	struct link_params *params);
	121	typedef void (config_loopback_t)(struct bnx2x_phy phy,
	122	struct link_params *params);
	123	typedef u8 (format_fw_ver_t)(u32 raw, u8 str, u16 *len);
	124	typedef void (hw_reset_t)(struct bnx2x_phy phy, struct link_params *params);
	125	typedef void (set_link_led_t)(struct bnx2x_phy phy,
	126	struct link_params *params, u8 mode);
a22f0788 YR	127	typedef void (phy_specific_func_t)(struct bnx2x_phy phy,
a22f0788 YR	128	struct link_params *params, u32 action);
a351d497 YM	129	struct bnx2x_reg_set {
	130	u8 devad;
	131	u16 reg;
	132	u16 val;
	133	};
b7737c9b	134
e10bc84d YR	135	struct bnx2x_phy {
	136	u32 type;
	137
	138	/* Loaded during init */
	139	u8 addr;
9045f6b4 YR	140	u8 def_md_devad;
9045f6b4 YR	141	u16 flags;
b7737c9b YR	142	/* Require HW lock */
	143	#define FLAGS_HW_LOCK_REQUIRED (1<<0)
	144	/* No Over-Current detection */
	145	#define FLAGS_NOC (1<<1)
	146	/* Fan failure detection required */
	147	#define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
	148	/* Initialize first the XGXS and only then the phy itself */
a22f0788	149	#define FLAGS_INIT_XGXS_FIRST (1<<3)
3c9ada22	150	#define FLAGS_WC_DUAL_MODE (1<<4)
9380bb9e	151	#define FLAGS_4_PORT_MODE (1<<5)
a22f0788 YR	152	#define FLAGS_REARM_LATCH_SIGNAL (1<<6)
a22f0788 YR	153	#define FLAGS_SFP_NOT_APPROVED (1<<7)
3c9ada22 YR	154	#define FLAGS_MDC_MDIO_WA (1<<8)
3c9ada22 YR	155	#define FLAGS_DUMMY_READ (1<<9)
157fa283	156	#define FLAGS_MDC_MDIO_WA_B0 (1<<10)
de6f3377	157	#define FLAGS_TX_ERROR_CHECK (1<<12)
26964bb7	158	#define FLAGS_EEE (1<<13)
b7737c9b	159
b7737c9b YR	160	/* preemphasis values for the rx side */
	161	u16 rx_preemphasis[4];
	162
	163	/* preemphasis values for the tx side */
	164	u16 tx_preemphasis[4];
	165
	166	/* EMAC address for access MDIO */
e10bc84d	167	u32 mdio_ctrl;
b7737c9b YR	168
	169	u32 supported;
	170
	171	u32 media_type;
dbef807e YM	172	#define ETH_PHY_UNSPECIFIED 0x0
	173	#define ETH_PHY_SFPP_10G_FIBER 0x1
	174	#define ETH_PHY_XFP_FIBER 0x2
	175	#define ETH_PHY_DA_TWINAX 0x3
	176	#define ETH_PHY_BASE_T 0x4
	177	#define ETH_PHY_SFP_1G_FIBER 0x5
	178	#define ETH_PHY_KR 0xf0
	179	#define ETH_PHY_CX4 0xf1
	180	#define ETH_PHY_NOT_PRESENT 0xff
b7737c9b YR	181
	182	/* The address in which version is located*/
	183	u32 ver_addr;
	184
	185	u16 req_flow_ctrl;
	186
	187	u16 req_line_speed;
	188
	189	u32 speed_cap_mask;
	190
	191	u16 req_duplex;
	192	u16 rsrv;
	193	/* Called per phy/port init, and it configures LASI, speed, autoneg,
	194	duplex, flow control negotiation, etc. */
	195	config_init_t config_init;
	196
	197	/* Called due to interrupt. It determines the link, speed */
	198	read_status_t read_status;
	199
	200	/* Called when driver is unloading. Should reset the phy */
	201	link_reset_t link_reset;
	202
	203	/* Set the loopback configuration for the phy */
	204	config_loopback_t config_loopback;
	205
	206	/* Format the given raw number into str up to len */
	207	format_fw_ver_t format_fw_ver;
	208
	209	/* Reset the phy (both ports) */
	210	hw_reset_t hw_reset;
	211
	212	/* Set link led mode (on/off/oper)*/
	213	set_link_led_t set_link_led;
a22f0788 YR	214
	215	/* PHY Specific tasks */
	216	phy_specific_func_t phy_specific_func;
	217	#define DISABLE_TX 1
	218	#define ENABLE_TX 2
5c107fda	219	#define PHY_INIT 3
e10bc84d YR	220	};
e10bc84d YR	221
ea4e040a YR	222	/* Inputs parameters to the CLC */
	223	struct link_params {
	224
	225	u8 port;
	226
	227	/* Default / User Configuration */
	228	u8 loopback_mode;
cd88ccee YR	229	#define LOOPBACK_NONE 0
	230	#define LOOPBACK_EMAC 1
	231	#define LOOPBACK_BMAC 2
de6eae1f	232	#define LOOPBACK_XGXS 3
ea4e040a	233	#define LOOPBACK_EXT_PHY 4
cd88ccee YR	234	#define LOOPBACK_EXT 5
	235	#define LOOPBACK_UMAC 6
	236	#define LOOPBACK_XMAC 7
ea4e040a	237
ea4e040a YR	238	/* Device parameters */
ea4e040a YR	239	u8 mac_addr[6];
8c99e7b0	240
a22f0788 YR	241	u16 req_duplex[LINK_CONFIG_SIZE];
	242	u16 req_flow_ctrl[LINK_CONFIG_SIZE];
	243
	244	u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
	245
ea4e040a YR	246	/* shmem parameters */
ea4e040a YR	247	u32 shmem_base;
a22f0788 YR	248	u32 shmem2_base;
a22f0788 YR	249	u32 speed_cap_mask[LINK_CONFIG_SIZE];
ea4e040a YR	250	u32 switch_cfg;
	251	#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
	252	#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
	253	#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
	254
ea4e040a	255	u32 lane_config;
659bc5c4	256
ea4e040a YR	257	/* Phy register parameter */
	258	u32 chip_id;
	259
cd88ccee	260	/* features */
589abe3a	261	u32 feature_config_flags;
cd88ccee YR	262	#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
	263	#define FEATURE_CONFIG_PFC_ENABLED (1<<1)
	264	#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
a22f0788	265	#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
a3348722	266	#define FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8)
a89a1d4a	267	#define FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
85242eea	268	#define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
55098c5c	269	#define FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
e10bc84d YR	270	/* Will be populated during common init */
	271	struct bnx2x_phy phy[MAX_PHYS];
	272
	273	/* Will be populated during common init */
	274	u8 num_phys;
1ef70b9c	275
b7737c9b	276	u8 rsrv;
c8c60d88 YM	277
	278	/* Used to configure the EEE Tx LPI timer, has several modes of
	279	* operation, according to bits 29:28 -
	280	* 2'b00: Timer will be configured by nvram, output will be the value
	281	* from nvram.
	282	* 2'b01: Timer will be configured by nvram, output will be in
	283	* microseconds.
	284	* 2'b10: bits 1:0 contain an nvram value which will be used instead
	285	* of the one located in the nvram. Output will be that value.
	286	* 2'b11: bits 19:0 contain the idle timer in microseconds; output
	287	* will be in microseconds.
	288	* Bits 31:30 should be 2'b11 in order for EEE to be enabled.
	289	*/
	290	u32 eee_mode;
	291	#define EEE_MODE_NVRAM_BALANCED_TIME (0xa00)
	292	#define EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100)
	293	#define EEE_MODE_NVRAM_LATENCY_TIME (0x6000)
	294	#define EEE_MODE_NVRAM_MASK (0x3)
	295	#define EEE_MODE_TIMER_MASK (0xfffff)
	296	#define EEE_MODE_OUTPUT_TIME (1<<28)
	297	#define EEE_MODE_OVERRIDE_NVRAM (1<<29)
	298	#define EEE_MODE_ENABLE_LPI (1<<30)
	299	#define EEE_MODE_ADV_LPI (1<<31)
	300
b7737c9b	301	u16 hw_led_mode; /* part of the hw_config read from the shmem */
a22f0788	302	u32 multi_phy_config;
b7737c9b	303
ea4e040a YR	304	/* Device pointer passed to all callback functions */
ea4e040a YR	305	struct bnx2x *bp;
a22f0788 YR	306	u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
a22f0788 YR	307	req_flow_ctrl is set to AUTO */
d3a8f13b YR	308	u16 rsrv1;
d3a8f13b YR	309	u32 lfa_base;
ea4e040a YR	310	};
	311
	312	/* Output parameters */
	313	struct link_vars {
1ef70b9c	314	u8 phy_flags;
3c9ada22 YR	315	#define PHY_XGXS_FLAG (1<<0)
3c9ada22 YR	316	#define PHY_SGMII_FLAG (1<<1)
3deb8167 YR	317	#define PHY_PHYSICAL_LINK_FLAG (1<<2)
	318	#define PHY_HALF_OPEN_CONN_FLAG (1<<3)
	319	#define PHY_OVER_CURRENT_FLAG (1<<4)
d0b8a6f9	320	#define PHY_SFP_TX_FAULT_FLAG (1<<5)
1ef70b9c EG	321
	322	u8 mac_type;
	323	#define MAC_TYPE_NONE 0
	324	#define MAC_TYPE_EMAC 1
	325	#define MAC_TYPE_BMAC 2
619c5cb6 VZ	326	#define MAC_TYPE_UMAC 3
619c5cb6 VZ	327	#define MAC_TYPE_XMAC 4
1ef70b9c	328
ea4e040a YR	329	u8 phy_link_up; /* internal phy link indication */
ea4e040a YR	330	u8 link_up;
1ef70b9c EG	331
1ef70b9c EG	332	u16 line_speed;
ea4e040a	333	u16 duplex;
1ef70b9c	334
ea4e040a	335	u16 flow_ctrl;
1ef70b9c	336	u16 ieee_fc;
ea4e040a	337
ea4e040a YR	338	/* The same definitions as the shmem parameter */
ea4e040a YR	339	u32 link_status;
c8c60d88	340	u32 eee_status;
c688fe2f YR	341	u8 fault_detected;
c688fe2f YR	342	u8 rsrv1;
3deb8167 YR	343	u16 periodic_flags;
	344	#define PERIODIC_FLAGS_LINK_EVENT 0x0001
	345
020c7e3f	346	u32 aeu_int_mask;
a9077bfd YR	347	u8 rx_tx_asic_rst;
	348	u8 turn_to_run_wc_rt;
	349	u16 rsrv2;
ea4e040a YR	350	};
	351
	352	/***********************************************************/
	353	/* Functions */
	354	/***********************************************************/
fcf5b650	355	int bnx2x_phy_init(struct link_params params, struct link_vars vars);
ea4e040a	356
589abe3a EG	357	/* Reset the link. Should be called when driver or interface goes down
	358	Before calling phy firmware upgrade, the reset_ext_phy should be set
	359	to 0 */
fcf5b650 YR	360	int bnx2x_link_reset(struct link_params params, struct link_vars vars,
fcf5b650 YR	361	u8 reset_ext_phy);
5d07d868	362	int bnx2x_lfa_reset(struct link_params params, struct link_vars vars);
ea4e040a	363	/* bnx2x_link_update should be called upon link interrupt */
fcf5b650	364	int bnx2x_link_update(struct link_params params, struct link_vars vars);
ea4e040a	365
e10bc84d	366	/* use the following phy functions to read/write from external_phy
ea4e040a YR	367	In order to use it to read/write internal phy registers, use
ea4e040a YR	368	DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
ea4e040a	369	the register */
fcf5b650 YR	370	int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
	371	u8 devad, u16 reg, u16 *ret_val);
	372
	373	int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
	374	u8 devad, u16 reg, u16 val);
ea4e040a	375
ea4e040a	376	/* Reads the link_status from the shmem,
33471629	377	and update the link vars accordingly */
ea4e040a YR	378	void bnx2x_link_status_update(struct link_params *input,
	379	struct link_vars *output);
	380	/* returns string representing the fw_version of the external phy */
a1e785e0 MY	381	int bnx2x_get_ext_phy_fw_version(struct link_params params, u8 version,
a1e785e0 MY	382	u16 len);
ea4e040a YR	383
	384	/* Set/Unset the led
	385	Basically, the CLC takes care of the led for the link, but in case one needs
33471629	386	to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
ea4e040a	387	blink the led, and LED_MODE_OFF to set the led off.*/
fcf5b650 YR	388	int bnx2x_set_led(struct link_params *params,
fcf5b650 YR	389	struct link_vars *vars, u8 mode, u32 speed);
7f02c4ad YR	390	#define LED_MODE_OFF 0
	391	#define LED_MODE_ON 1
	392	#define LED_MODE_OPER 2
	393	#define LED_MODE_FRONT_PANEL_OFF 3
ea4e040a	394
589abe3a EG	395	/* bnx2x_handle_module_detect_int should be called upon module detection
	396	interrupt */
	397	void bnx2x_handle_module_detect_int(struct link_params *params);
	398
ea4e040a YR	399	/* Get the actual link status. In case it returns 0, link is up,
ea4e040a YR	400	otherwise link is down*/
fcf5b650 YR	401	int bnx2x_test_link(struct link_params params, struct link_vars vars,
fcf5b650 YR	402	u8 is_serdes);
ea4e040a	403
6bbca910	404	/* One-time initialization for external phy after power up */
fcf5b650 YR	405	int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
fcf5b650 YR	406	u32 shmem2_base_path[], u32 chip_id);
ea4e040a	407
f57a6025 EG	408	/* Reset the external PHY using GPIO */
	409	void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
	410
e10bc84d YR	411	/* Reset the external of SFX7101 */
e10bc84d YR	412	void bnx2x_sfx7101_sp_sw_reset(struct bnx2x bp, struct bnx2x_phy phy);
356e2385	413
65a001ba	414	/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
fcf5b650 YR	415	int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
	416	struct link_params *params, u16 addr,
	417	u8 byte_cnt, u8 *o_buf);
65a001ba	418
d90d96ba YR	419	void bnx2x_hw_reset_phy(struct link_params *params);
	420
	421	/* Checks if HW lock is required for this phy/board type */
a22f0788 YR	422	u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
	423	u32 shmem2_base);
	424
a22f0788 YR	425	/* Check swap bit and adjust PHY order */
	426	u32 bnx2x_phy_selection(struct link_params *params);
	427
e10bc84d	428	/* Probe the phys on board, and populate them in "params" */
fcf5b650 YR	429	int bnx2x_phy_probe(struct link_params *params);
fcf5b650 YR	430
d90d96ba	431	/* Checks if fan failure detection is required on one of the phys on board */
a22f0788 YR	432	u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
a22f0788 YR	433	u32 shmem2_base, u8 port);
d90d96ba	434
9380bb9e YR	435
9380bb9e YR	436
619c5cb6 VZ	437	/* DCBX structs */
	438
	439	/* Number of maximum COS per chip */
	440	#define DCBX_E2E3_MAX_NUM_COS (2)
	441	#define DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
	442	#define DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
	443	#define DCBX_E3B0_MAX_NUM_COS ( \
	444	MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
	445	DCBX_E3B0_MAX_NUM_COS_PORT1))
	446
	447	#define DCBX_MAX_NUM_COS ( \
	448	MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
	449	DCBX_E2E3_MAX_NUM_COS))
	450
e4901dde VZ	451	/* PFC port configuration params */
	452	struct bnx2x_nig_brb_pfc_port_params {
	453	/* NIG */
	454	u32 pause_enable;
	455	u32 llfc_out_en;
	456	u32 llfc_enable;
	457	u32 pkt_priority_to_cos;
619c5cb6 VZ	458	u8 num_of_rx_cos_priority_mask;
619c5cb6 VZ	459	u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
e4901dde VZ	460	u32 llfc_high_priority_classes;
	461	u32 llfc_low_priority_classes;
	462	/* BRB */
	463	u32 cos0_pauseable;
	464	u32 cos1_pauseable;
	465	};
	466
6c3218c6 YR	467
	468	/* ETS port configuration params */
	469	struct bnx2x_ets_bw_params {
	470	u8 bw;
	471	};
	472
	473	struct bnx2x_ets_sp_params {
	474	/**
	475	* valid values are 0 - 5. 0 is highest strict priority.
	476	* There can't be two COS's with the same pri.
	477	*/
	478	u8 pri;
	479	};
	480
	481	enum bnx2x_cos_state {
	482	bnx2x_cos_state_strict = 0,
	483	bnx2x_cos_state_bw = 1,
	484	};
	485
	486	struct bnx2x_ets_cos_params {
	487	enum bnx2x_cos_state state ;
	488	union {
	489	struct bnx2x_ets_bw_params bw_params;
	490	struct bnx2x_ets_sp_params sp_params;
	491	} params;
	492	};
	493
	494	struct bnx2x_ets_params {
	495	u8 num_of_cos; /* Number of valid COS entries*/
	496	struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS];
	497	};
	498
1aa8b471	499	/* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
e4901dde VZ	500	* when link is already up
e4901dde VZ	501	*/
9380bb9e	502	int bnx2x_update_pfc(struct link_params *params,
e4901dde VZ	503	struct link_vars *vars,
	504	struct bnx2x_nig_brb_pfc_port_params *pfc_params);
	505
	506
	507	/* Used to configure the ETS to disable */
6c3218c6 YR	508	int bnx2x_ets_disabled(struct link_params *params,
6c3218c6 YR	509	struct link_vars *vars);
e4901dde VZ	510
	511	/* Used to configure the ETS to BW limited */
	512	void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
cd88ccee	513	const u32 cos1_bw);
e4901dde VZ	514
e4901dde VZ	515	/* Used to configure the ETS to strict */
fcf5b650	516	int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
e4901dde	517
6c3218c6 YR	518
	519	/* Configure the COS to ETS according to BW and SP settings.*/
	520	int bnx2x_ets_e3b0_config(const struct link_params *params,
	521	const struct link_vars *vars,
870516e1	522	struct bnx2x_ets_params *ets_params);
e4901dde VZ	523	/* Read pfc statistic*/
	524	void bnx2x_pfc_statistic(struct link_params params, struct link_vars vars,
	525	u32 pfc_frames_sent[2],
	526	u32 pfc_frames_received[2]);
020c7e3f YR	527	void bnx2x_init_mod_abs_int(struct bnx2x bp, struct link_vars vars,
	528	u32 chip_id, u32 shmem_base, u32 shmem2_base,
	529	u8 port);
3c9ada22 YR	530
	531	int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
	532	struct link_params *params);
3deb8167 YR	533
	534	void bnx2x_period_func(struct link_params params, struct link_vars vars);
	535
55098c5c YR	536	int bnx2x_check_half_open_conn(struct link_params *params,
55098c5c YR	537	struct link_vars *vars, u8 notify);
ea4e040a	538	#endif /* BNX2X_LINK_H */