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34f80b04 | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
a2fbb9ea | 2 | * |
5de92408 | 3 | * Copyright (c) 2007-2011 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 14 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
15 | * |
16 | */ | |
17 | ||
a2fbb9ea ET |
18 | #include <linux/module.h> |
19 | #include <linux/moduleparam.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/device.h> /* for dev_info() */ | |
22 | #include <linux/timer.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/slab.h> | |
a2fbb9ea ET |
26 | #include <linux/interrupt.h> |
27 | #include <linux/pci.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/netdevice.h> | |
30 | #include <linux/etherdevice.h> | |
31 | #include <linux/skbuff.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/bitops.h> | |
34 | #include <linux/irq.h> | |
35 | #include <linux/delay.h> | |
36 | #include <asm/byteorder.h> | |
37 | #include <linux/time.h> | |
38 | #include <linux/ethtool.h> | |
39 | #include <linux/mii.h> | |
0c6671b0 | 40 | #include <linux/if_vlan.h> |
a2fbb9ea | 41 | #include <net/ip.h> |
619c5cb6 | 42 | #include <net/ipv6.h> |
a2fbb9ea ET |
43 | #include <net/tcp.h> |
44 | #include <net/checksum.h> | |
34f80b04 | 45 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
46 | #include <linux/workqueue.h> |
47 | #include <linux/crc32.h> | |
34f80b04 | 48 | #include <linux/crc32c.h> |
a2fbb9ea ET |
49 | #include <linux/prefetch.h> |
50 | #include <linux/zlib.h> | |
a2fbb9ea | 51 | #include <linux/io.h> |
45229b42 | 52 | #include <linux/stringify.h> |
7ab24bfd | 53 | #include <linux/vmalloc.h> |
a2fbb9ea | 54 | |
a2fbb9ea ET |
55 | #include "bnx2x.h" |
56 | #include "bnx2x_init.h" | |
94a78b79 | 57 | #include "bnx2x_init_ops.h" |
9f6c9258 | 58 | #include "bnx2x_cmn.h" |
e4901dde | 59 | #include "bnx2x_dcb.h" |
042181f5 | 60 | #include "bnx2x_sp.h" |
a2fbb9ea | 61 | |
94a78b79 VZ |
62 | #include <linux/firmware.h> |
63 | #include "bnx2x_fw_file_hdr.h" | |
64 | /* FW files */ | |
45229b42 BH |
65 | #define FW_FILE_VERSION \ |
66 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
67 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
68 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
69 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
70 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
71 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 72 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 73 | |
34f80b04 EG |
74 | /* Time in jiffies before concluding the transmitter is hung */ |
75 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 76 | |
53a10565 | 77 | static char version[] __devinitdata = |
619c5cb6 | 78 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
79 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
80 | ||
24e3fcef | 81 | MODULE_AUTHOR("Eliezer Tamir"); |
f2e0899f | 82 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
619c5cb6 VZ |
83 | "BCM57710/57711/57711E/" |
84 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
85 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
86 | MODULE_LICENSE("GPL"); |
87 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
88 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
89 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 90 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 91 | |
555f6c78 EG |
92 | static int multi_mode = 1; |
93 | module_param(multi_mode, int, 0); | |
ca00392c EG |
94 | MODULE_PARM_DESC(multi_mode, " Multi queue mode " |
95 | "(0 Disable; 1 Enable (default))"); | |
96 | ||
d6214d7a | 97 | int num_queues; |
54b9ddaa VZ |
98 | module_param(num_queues, int, 0); |
99 | MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" | |
100 | " (default is as a number of CPUs)"); | |
555f6c78 | 101 | |
19680c48 | 102 | static int disable_tpa; |
19680c48 | 103 | module_param(disable_tpa, int, 0); |
9898f86d | 104 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 105 | |
9ee3d37b DK |
106 | #define INT_MODE_INTx 1 |
107 | #define INT_MODE_MSI 2 | |
8badd27a EG |
108 | static int int_mode; |
109 | module_param(int_mode, int, 0); | |
619c5cb6 | 110 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 111 | "(1 INT#x; 2 MSI)"); |
8badd27a | 112 | |
a18f5128 EG |
113 | static int dropless_fc; |
114 | module_param(dropless_fc, int, 0); | |
115 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); | |
116 | ||
9898f86d | 117 | static int poll; |
a2fbb9ea | 118 | module_param(poll, int, 0); |
9898f86d | 119 | MODULE_PARM_DESC(poll, " Use polling (for debug)"); |
8d5726c4 EG |
120 | |
121 | static int mrrs = -1; | |
122 | module_param(mrrs, int, 0); | |
123 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); | |
124 | ||
9898f86d | 125 | static int debug; |
a2fbb9ea | 126 | module_param(debug, int, 0); |
9898f86d EG |
127 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
128 | ||
a2fbb9ea | 129 | |
619c5cb6 VZ |
130 | |
131 | struct workqueue_struct *bnx2x_wq; | |
ec6ba945 | 132 | |
a2fbb9ea ET |
133 | enum bnx2x_board_type { |
134 | BCM57710 = 0, | |
619c5cb6 VZ |
135 | BCM57711, |
136 | BCM57711E, | |
137 | BCM57712, | |
138 | BCM57712_MF, | |
139 | BCM57800, | |
140 | BCM57800_MF, | |
141 | BCM57810, | |
142 | BCM57810_MF, | |
143 | BCM57840, | |
144 | BCM57840_MF | |
a2fbb9ea ET |
145 | }; |
146 | ||
34f80b04 | 147 | /* indexed by board_type, above */ |
53a10565 | 148 | static struct { |
a2fbb9ea ET |
149 | char *name; |
150 | } board_info[] __devinitdata = { | |
619c5cb6 VZ |
151 | { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
152 | { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, | |
153 | { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, | |
154 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, | |
155 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, | |
156 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, | |
157 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, | |
158 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, | |
159 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, | |
160 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, | |
161 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " | |
162 | "Ethernet Multi Function"} | |
a2fbb9ea ET |
163 | }; |
164 | ||
619c5cb6 VZ |
165 | #ifndef PCI_DEVICE_ID_NX2_57710 |
166 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
167 | #endif | |
168 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
169 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
170 | #endif | |
171 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
172 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
173 | #endif | |
174 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
175 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
176 | #endif | |
177 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
178 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
179 | #endif | |
180 | #ifndef PCI_DEVICE_ID_NX2_57800 | |
181 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
182 | #endif | |
183 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
184 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
185 | #endif | |
186 | #ifndef PCI_DEVICE_ID_NX2_57810 | |
187 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
188 | #endif | |
189 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
190 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
191 | #endif | |
192 | #ifndef PCI_DEVICE_ID_NX2_57840 | |
193 | #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 | |
194 | #endif | |
195 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
196 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
197 | #endif | |
a3aa1884 | 198 | static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { |
e4ed7113 EG |
199 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
200 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
201 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 202 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 VZ |
203 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
204 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, | |
205 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
206 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, | |
207 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
208 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, | |
209 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, | |
a2fbb9ea ET |
210 | { 0 } |
211 | }; | |
212 | ||
213 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
214 | ||
215 | /**************************************************************************** | |
216 | * General service functions | |
217 | ****************************************************************************/ | |
218 | ||
619c5cb6 VZ |
219 | static inline void __storm_memset_dma_mapping(struct bnx2x *bp, |
220 | u32 addr, dma_addr_t mapping) | |
221 | { | |
222 | REG_WR(bp, addr, U64_LO(mapping)); | |
223 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
224 | } | |
225 | ||
226 | static inline void storm_memset_spq_addr(struct bnx2x *bp, | |
227 | dma_addr_t mapping, u16 abs_fid) | |
228 | { | |
229 | u32 addr = XSEM_REG_FAST_MEMORY + | |
230 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
231 | ||
232 | __storm_memset_dma_mapping(bp, addr, mapping); | |
233 | } | |
234 | ||
235 | static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, | |
236 | u16 pf_id) | |
523224a3 | 237 | { |
619c5cb6 VZ |
238 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
239 | pf_id); | |
240 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
241 | pf_id); | |
242 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
243 | pf_id); | |
244 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
245 | pf_id); | |
523224a3 DK |
246 | } |
247 | ||
619c5cb6 VZ |
248 | static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
249 | u8 enable) | |
250 | { | |
251 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
252 | enable); | |
253 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
254 | enable); | |
255 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
256 | enable); | |
257 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
258 | enable); | |
259 | } | |
523224a3 DK |
260 | |
261 | static inline void storm_memset_eq_data(struct bnx2x *bp, | |
262 | struct event_ring_data *eq_data, | |
263 | u16 pfid) | |
264 | { | |
265 | size_t size = sizeof(struct event_ring_data); | |
266 | ||
267 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
268 | ||
269 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
270 | } | |
271 | ||
272 | static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, | |
273 | u16 pfid) | |
274 | { | |
275 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
276 | REG_WR16(bp, addr, eq_prod); | |
277 | } | |
278 | ||
a2fbb9ea ET |
279 | /* used only at init |
280 | * locking is done by mcp | |
281 | */ | |
8d96286a | 282 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
283 | { |
284 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
285 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
286 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
287 | PCICFG_VENDOR_ID_OFFSET); | |
288 | } | |
289 | ||
a2fbb9ea ET |
290 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
291 | { | |
292 | u32 val; | |
293 | ||
294 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
295 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
296 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
297 | PCICFG_VENDOR_ID_OFFSET); | |
298 | ||
299 | return val; | |
300 | } | |
a2fbb9ea | 301 | |
f2e0899f DK |
302 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
303 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
304 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
305 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
306 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
307 | ||
8d96286a | 308 | static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, |
309 | int msglvl) | |
f2e0899f DK |
310 | { |
311 | u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; | |
312 | ||
313 | switch (dmae->opcode & DMAE_COMMAND_DST) { | |
314 | case DMAE_CMD_DST_PCI: | |
315 | if (src_type == DMAE_CMD_SRC_PCI) | |
316 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
317 | "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" | |
318 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
319 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
320 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
321 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
322 | dmae->comp_val); | |
323 | else | |
324 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
325 | "src [%08x], len [%d*4], dst [%x:%08x]\n" | |
326 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
327 | dmae->opcode, dmae->src_addr_lo >> 2, | |
328 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
329 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
330 | dmae->comp_val); | |
331 | break; | |
332 | case DMAE_CMD_DST_GRC: | |
333 | if (src_type == DMAE_CMD_SRC_PCI) | |
334 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
335 | "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" | |
336 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
337 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
338 | dmae->len, dmae->dst_addr_lo >> 2, | |
339 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
340 | dmae->comp_val); | |
341 | else | |
342 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
343 | "src [%08x], len [%d*4], dst [%08x]\n" | |
344 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
345 | dmae->opcode, dmae->src_addr_lo >> 2, | |
346 | dmae->len, dmae->dst_addr_lo >> 2, | |
347 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
348 | dmae->comp_val); | |
349 | break; | |
350 | default: | |
351 | if (src_type == DMAE_CMD_SRC_PCI) | |
352 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
353 | DP_LEVEL "src_addr [%x:%08x] len [%d * 4] " | |
354 | "dst_addr [none]\n" | |
355 | DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
356 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
357 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
358 | dmae->comp_val); | |
359 | else | |
360 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
361 | DP_LEVEL "src_addr [%08x] len [%d * 4] " | |
362 | "dst_addr [none]\n" | |
363 | DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
364 | dmae->opcode, dmae->src_addr_lo >> 2, | |
365 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
366 | dmae->comp_val); | |
367 | break; | |
368 | } | |
369 | ||
370 | } | |
371 | ||
a2fbb9ea | 372 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 373 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
374 | { |
375 | u32 cmd_offset; | |
376 | int i; | |
377 | ||
378 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
379 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
380 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
381 | ||
ad8d3948 EG |
382 | DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", |
383 | idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
384 | } |
385 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
386 | } | |
387 | ||
f2e0899f | 388 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 389 | { |
f2e0899f DK |
390 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
391 | DMAE_CMD_C_ENABLE); | |
392 | } | |
ad8d3948 | 393 | |
f2e0899f DK |
394 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
395 | { | |
396 | return opcode & ~DMAE_CMD_SRC_RESET; | |
397 | } | |
ad8d3948 | 398 | |
f2e0899f DK |
399 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
400 | bool with_comp, u8 comp_type) | |
401 | { | |
402 | u32 opcode = 0; | |
403 | ||
404 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
405 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 406 | |
f2e0899f DK |
407 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
408 | ||
409 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
410 | opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) | | |
411 | (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
412 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); | |
a2fbb9ea | 413 | |
a2fbb9ea | 414 | #ifdef __BIG_ENDIAN |
f2e0899f | 415 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 416 | #else |
f2e0899f | 417 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 418 | #endif |
f2e0899f DK |
419 | if (with_comp) |
420 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
421 | return opcode; | |
422 | } | |
423 | ||
8d96286a | 424 | static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
425 | struct dmae_command *dmae, | |
426 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
427 | { |
428 | memset(dmae, 0, sizeof(struct dmae_command)); | |
429 | ||
430 | /* set the opcode */ | |
431 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
432 | true, DMAE_COMP_PCI); | |
433 | ||
434 | /* fill in the completion parameters */ | |
435 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
436 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
437 | dmae->comp_val = DMAE_COMP_VAL; | |
438 | } | |
439 | ||
440 | /* issue a dmae command over the init-channel and wailt for completion */ | |
8d96286a | 441 | static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, |
442 | struct dmae_command *dmae) | |
f2e0899f DK |
443 | { |
444 | u32 *wb_comp = bnx2x_sp(bp, wb_comp); | |
5e374b5a | 445 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
446 | int rc = 0; |
447 | ||
448 | DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", | |
a2fbb9ea ET |
449 | bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], |
450 | bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); | |
a2fbb9ea | 451 | |
619c5cb6 VZ |
452 | /* |
453 | * Lock the dmae channel. Disable BHs to prevent a dead-lock | |
454 | * as long as this code is called both from syscall context and | |
455 | * from ndo_set_rx_mode() flow that may be called from BH. | |
456 | */ | |
6e30dd4e | 457 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 458 | |
f2e0899f | 459 | /* reset completion */ |
a2fbb9ea ET |
460 | *wb_comp = 0; |
461 | ||
f2e0899f DK |
462 | /* post the command on the channel used for initializations */ |
463 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 464 | |
f2e0899f | 465 | /* wait for completion */ |
a2fbb9ea | 466 | udelay(5); |
f2e0899f | 467 | while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 EG |
468 | DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); |
469 | ||
ad8d3948 | 470 | if (!cnt) { |
c3eefaf6 | 471 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
472 | rc = DMAE_TIMEOUT; |
473 | goto unlock; | |
a2fbb9ea | 474 | } |
ad8d3948 | 475 | cnt--; |
f2e0899f | 476 | udelay(50); |
a2fbb9ea | 477 | } |
f2e0899f DK |
478 | if (*wb_comp & DMAE_PCI_ERR_FLAG) { |
479 | BNX2X_ERR("DMAE PCI error!\n"); | |
480 | rc = DMAE_PCI_ERROR; | |
481 | } | |
482 | ||
483 | DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", | |
484 | bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], | |
485 | bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); | |
ad8d3948 | 486 | |
f2e0899f | 487 | unlock: |
6e30dd4e | 488 | spin_unlock_bh(&bp->dmae_lock); |
f2e0899f DK |
489 | return rc; |
490 | } | |
491 | ||
492 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
493 | u32 len32) | |
494 | { | |
495 | struct dmae_command dmae; | |
496 | ||
497 | if (!bp->dmae_ready) { | |
498 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
499 | ||
500 | DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)" | |
501 | " using indirect\n", dst_addr, len32); | |
502 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
503 | return; | |
504 | } | |
505 | ||
506 | /* set opcode and fixed command fields */ | |
507 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
508 | ||
509 | /* fill in addresses and len */ | |
510 | dmae.src_addr_lo = U64_LO(dma_addr); | |
511 | dmae.src_addr_hi = U64_HI(dma_addr); | |
512 | dmae.dst_addr_lo = dst_addr >> 2; | |
513 | dmae.dst_addr_hi = 0; | |
514 | dmae.len = len32; | |
515 | ||
516 | bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); | |
517 | ||
518 | /* issue the command and wait for completion */ | |
519 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
a2fbb9ea ET |
520 | } |
521 | ||
c18487ee | 522 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 523 | { |
5ff7b6d4 | 524 | struct dmae_command dmae; |
ad8d3948 EG |
525 | |
526 | if (!bp->dmae_ready) { | |
527 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
528 | int i; | |
529 | ||
530 | DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)" | |
531 | " using indirect\n", src_addr, len32); | |
532 | for (i = 0; i < len32; i++) | |
533 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
534 | return; | |
535 | } | |
536 | ||
f2e0899f DK |
537 | /* set opcode and fixed command fields */ |
538 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 539 | |
f2e0899f | 540 | /* fill in addresses and len */ |
5ff7b6d4 EG |
541 | dmae.src_addr_lo = src_addr >> 2; |
542 | dmae.src_addr_hi = 0; | |
543 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
544 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
545 | dmae.len = len32; | |
ad8d3948 | 546 | |
f2e0899f | 547 | bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); |
ad8d3948 | 548 | |
f2e0899f DK |
549 | /* issue the command and wait for completion */ |
550 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
ad8d3948 EG |
551 | } |
552 | ||
8d96286a | 553 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
554 | u32 addr, u32 len) | |
573f2035 | 555 | { |
02e3c6cb | 556 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
557 | int offset = 0; |
558 | ||
02e3c6cb | 559 | while (len > dmae_wr_max) { |
573f2035 | 560 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
561 | addr + offset, dmae_wr_max); |
562 | offset += dmae_wr_max * 4; | |
563 | len -= dmae_wr_max; | |
573f2035 EG |
564 | } |
565 | ||
566 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
567 | } | |
568 | ||
ad8d3948 EG |
569 | /* used only for slowpath so not inlined */ |
570 | static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) | |
571 | { | |
572 | u32 wb_write[2]; | |
573 | ||
574 | wb_write[0] = val_hi; | |
575 | wb_write[1] = val_lo; | |
576 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
a2fbb9ea | 577 | } |
a2fbb9ea | 578 | |
ad8d3948 EG |
579 | #ifdef USE_WB_RD |
580 | static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) | |
581 | { | |
582 | u32 wb_data[2]; | |
583 | ||
584 | REG_RD_DMAE(bp, reg, wb_data, 2); | |
585 | ||
586 | return HILO_U64(wb_data[0], wb_data[1]); | |
587 | } | |
588 | #endif | |
589 | ||
a2fbb9ea ET |
590 | static int bnx2x_mc_assert(struct bnx2x *bp) |
591 | { | |
a2fbb9ea | 592 | char last_idx; |
34f80b04 EG |
593 | int i, rc = 0; |
594 | u32 row0, row1, row2, row3; | |
595 | ||
596 | /* XSTORM */ | |
597 | last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + | |
598 | XSTORM_ASSERT_LIST_INDEX_OFFSET); | |
599 | if (last_idx) | |
600 | BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
601 | ||
602 | /* print the asserts */ | |
603 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
604 | ||
605 | row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
606 | XSTORM_ASSERT_LIST_OFFSET(i)); | |
607 | row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
608 | XSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
609 | row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
610 | XSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
611 | row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
612 | XSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
613 | ||
614 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
615 | BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" | |
616 | " 0x%08x 0x%08x 0x%08x\n", | |
617 | i, row3, row2, row1, row0); | |
618 | rc++; | |
619 | } else { | |
620 | break; | |
621 | } | |
622 | } | |
623 | ||
624 | /* TSTORM */ | |
625 | last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + | |
626 | TSTORM_ASSERT_LIST_INDEX_OFFSET); | |
627 | if (last_idx) | |
628 | BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
629 | ||
630 | /* print the asserts */ | |
631 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
632 | ||
633 | row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
634 | TSTORM_ASSERT_LIST_OFFSET(i)); | |
635 | row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
636 | TSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
637 | row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
638 | TSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
639 | row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
640 | TSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
641 | ||
642 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
643 | BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" | |
644 | " 0x%08x 0x%08x 0x%08x\n", | |
645 | i, row3, row2, row1, row0); | |
646 | rc++; | |
647 | } else { | |
648 | break; | |
649 | } | |
650 | } | |
651 | ||
652 | /* CSTORM */ | |
653 | last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + | |
654 | CSTORM_ASSERT_LIST_INDEX_OFFSET); | |
655 | if (last_idx) | |
656 | BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
657 | ||
658 | /* print the asserts */ | |
659 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
660 | ||
661 | row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
662 | CSTORM_ASSERT_LIST_OFFSET(i)); | |
663 | row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
664 | CSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
665 | row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
666 | CSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
667 | row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
668 | CSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
669 | ||
670 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
671 | BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" | |
672 | " 0x%08x 0x%08x 0x%08x\n", | |
673 | i, row3, row2, row1, row0); | |
674 | rc++; | |
675 | } else { | |
676 | break; | |
677 | } | |
678 | } | |
679 | ||
680 | /* USTORM */ | |
681 | last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + | |
682 | USTORM_ASSERT_LIST_INDEX_OFFSET); | |
683 | if (last_idx) | |
684 | BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
685 | ||
686 | /* print the asserts */ | |
687 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
688 | ||
689 | row0 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
690 | USTORM_ASSERT_LIST_OFFSET(i)); | |
691 | row1 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
692 | USTORM_ASSERT_LIST_OFFSET(i) + 4); | |
693 | row2 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
694 | USTORM_ASSERT_LIST_OFFSET(i) + 8); | |
695 | row3 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
696 | USTORM_ASSERT_LIST_OFFSET(i) + 12); | |
697 | ||
698 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
699 | BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" | |
700 | " 0x%08x 0x%08x 0x%08x\n", | |
701 | i, row3, row2, row1, row0); | |
702 | rc++; | |
703 | } else { | |
704 | break; | |
a2fbb9ea ET |
705 | } |
706 | } | |
34f80b04 | 707 | |
a2fbb9ea ET |
708 | return rc; |
709 | } | |
c14423fe | 710 | |
7a25cc73 | 711 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 712 | { |
7a25cc73 | 713 | u32 addr, val; |
a2fbb9ea | 714 | u32 mark, offset; |
4781bfad | 715 | __be32 data[9]; |
a2fbb9ea | 716 | int word; |
f2e0899f | 717 | u32 trace_shmem_base; |
2145a920 VZ |
718 | if (BP_NOMCP(bp)) { |
719 | BNX2X_ERR("NO MCP - can not dump\n"); | |
720 | return; | |
721 | } | |
7a25cc73 DK |
722 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
723 | (bp->common.bc_ver & 0xff0000) >> 16, | |
724 | (bp->common.bc_ver & 0xff00) >> 8, | |
725 | (bp->common.bc_ver & 0xff)); | |
726 | ||
727 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
728 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
729 | printk("%s" "MCP PC at 0x%x\n", lvl, val); | |
cdaa7cb8 | 730 | |
f2e0899f DK |
731 | if (BP_PATH(bp) == 0) |
732 | trace_shmem_base = bp->common.shmem_base; | |
733 | else | |
734 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
735 | addr = trace_shmem_base - 0x0800 + 4; | |
cdaa7cb8 | 736 | mark = REG_RD(bp, addr); |
f2e0899f DK |
737 | mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) |
738 | + ((mark + 0x3) & ~0x3) - 0x08000000; | |
7a25cc73 | 739 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 740 | |
7a25cc73 | 741 | printk("%s", lvl); |
f2e0899f | 742 | for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 743 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 744 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 745 | data[8] = 0x0; |
7995c64e | 746 | pr_cont("%s", (char *)data); |
a2fbb9ea | 747 | } |
cdaa7cb8 | 748 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 749 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 750 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 751 | data[8] = 0x0; |
7995c64e | 752 | pr_cont("%s", (char *)data); |
a2fbb9ea | 753 | } |
7a25cc73 DK |
754 | printk("%s" "end of fw dump\n", lvl); |
755 | } | |
756 | ||
757 | static inline void bnx2x_fw_dump(struct bnx2x *bp) | |
758 | { | |
759 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
760 | } |
761 | ||
6c719d00 | 762 | void bnx2x_panic_dump(struct bnx2x *bp) |
a2fbb9ea ET |
763 | { |
764 | int i; | |
523224a3 DK |
765 | u16 j; |
766 | struct hc_sp_status_block_data sp_sb_data; | |
767 | int func = BP_FUNC(bp); | |
768 | #ifdef BNX2X_STOP_ON_ERROR | |
769 | u16 start = 0, end = 0; | |
6383c0b3 | 770 | u8 cos; |
523224a3 | 771 | #endif |
a2fbb9ea | 772 | |
66e855f3 YG |
773 | bp->stats_state = STATS_STATE_DISABLED; |
774 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); | |
775 | ||
a2fbb9ea ET |
776 | BNX2X_ERR("begin crash dump -----------------\n"); |
777 | ||
8440d2b6 EG |
778 | /* Indices */ |
779 | /* Common */ | |
523224a3 | 780 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" |
619c5cb6 VZ |
781 | " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", |
782 | bp->def_idx, bp->def_att_idx, bp->attn_state, | |
783 | bp->spq_prod_idx, bp->stats_counter); | |
523224a3 DK |
784 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", |
785 | bp->def_status_blk->atten_status_block.attn_bits, | |
786 | bp->def_status_blk->atten_status_block.attn_bits_ack, | |
787 | bp->def_status_blk->atten_status_block.status_block_id, | |
788 | bp->def_status_blk->atten_status_block.attn_bits_index); | |
789 | BNX2X_ERR(" def ("); | |
790 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
791 | pr_cont("0x%x%s", | |
792 | bp->def_status_blk->sp_sb.index_values[i], | |
793 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
794 | ||
795 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
796 | *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
797 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
798 | i*sizeof(u32)); | |
799 | ||
619c5cb6 | 800 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) " |
523224a3 | 801 | "pf_id(0x%x) vnic_id(0x%x) " |
619c5cb6 VZ |
802 | "vf_id(0x%x) vf_valid (0x%x) " |
803 | "state(0x%x)\n", | |
523224a3 DK |
804 | sp_sb_data.igu_sb_id, |
805 | sp_sb_data.igu_seg_id, | |
806 | sp_sb_data.p_func.pf_id, | |
807 | sp_sb_data.p_func.vnic_id, | |
808 | sp_sb_data.p_func.vf_id, | |
619c5cb6 VZ |
809 | sp_sb_data.p_func.vf_valid, |
810 | sp_sb_data.state); | |
523224a3 | 811 | |
8440d2b6 | 812 | |
ec6ba945 | 813 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 814 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 815 | int loop; |
f2e0899f | 816 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
817 | struct hc_status_block_data_e1x sb_data_e1x; |
818 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
819 | CHIP_IS_E1x(bp) ? |
820 | sb_data_e1x.common.state_machine : | |
821 | sb_data_e2.common.state_machine; | |
523224a3 | 822 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
823 | CHIP_IS_E1x(bp) ? |
824 | sb_data_e1x.index_data : | |
825 | sb_data_e2.index_data; | |
6383c0b3 | 826 | u8 data_size, cos; |
523224a3 | 827 | u32 *sb_data_p; |
6383c0b3 | 828 | struct bnx2x_fp_txdata txdata; |
523224a3 DK |
829 | |
830 | /* Rx */ | |
cdaa7cb8 | 831 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" |
523224a3 | 832 | " rx_comp_prod(0x%x)" |
cdaa7cb8 | 833 | " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 834 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 835 | fp->rx_comp_prod, |
66e855f3 | 836 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
cdaa7cb8 | 837 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" |
523224a3 | 838 | " fp_hc_idx(0x%x)\n", |
8440d2b6 | 839 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 840 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 841 | |
523224a3 | 842 | /* Tx */ |
6383c0b3 AE |
843 | for_each_cos_in_tx_queue(fp, cos) |
844 | { | |
845 | txdata = fp->txdata[cos]; | |
846 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" | |
847 | " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" | |
848 | " *tx_cons_sb(0x%x)\n", | |
849 | i, txdata.tx_pkt_prod, | |
850 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
851 | txdata.tx_bd_cons, | |
852 | le16_to_cpu(*txdata.tx_cons_sb)); | |
853 | } | |
523224a3 | 854 | |
619c5cb6 VZ |
855 | loop = CHIP_IS_E1x(bp) ? |
856 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
857 | |
858 | /* host sb data */ | |
859 | ||
ec6ba945 VZ |
860 | #ifdef BCM_CNIC |
861 | if (IS_FCOE_FP(fp)) | |
862 | continue; | |
863 | #endif | |
523224a3 DK |
864 | BNX2X_ERR(" run indexes ("); |
865 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
866 | pr_cont("0x%x%s", | |
867 | fp->sb_running_index[j], | |
868 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
869 | ||
870 | BNX2X_ERR(" indexes ("); | |
871 | for (j = 0; j < loop; j++) | |
872 | pr_cont("0x%x%s", | |
873 | fp->sb_index_values[j], | |
874 | (j == loop - 1) ? ")" : " "); | |
875 | /* fw sb data */ | |
619c5cb6 VZ |
876 | data_size = CHIP_IS_E1x(bp) ? |
877 | sizeof(struct hc_status_block_data_e1x) : | |
878 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 879 | data_size /= sizeof(u32); |
619c5cb6 VZ |
880 | sb_data_p = CHIP_IS_E1x(bp) ? |
881 | (u32 *)&sb_data_e1x : | |
882 | (u32 *)&sb_data_e2; | |
523224a3 DK |
883 | /* copy sb data in here */ |
884 | for (j = 0; j < data_size; j++) | |
885 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
886 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
887 | j * sizeof(u32)); | |
888 | ||
619c5cb6 VZ |
889 | if (!CHIP_IS_E1x(bp)) { |
890 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " | |
891 | "vnic_id(0x%x) same_igu_sb_1b(0x%x) " | |
892 | "state(0x%x)\n", | |
f2e0899f DK |
893 | sb_data_e2.common.p_func.pf_id, |
894 | sb_data_e2.common.p_func.vf_id, | |
895 | sb_data_e2.common.p_func.vf_valid, | |
896 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
897 | sb_data_e2.common.same_igu_sb_1b, |
898 | sb_data_e2.common.state); | |
f2e0899f | 899 | } else { |
619c5cb6 VZ |
900 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " |
901 | "vnic_id(0x%x) same_igu_sb_1b(0x%x) " | |
902 | "state(0x%x)\n", | |
f2e0899f DK |
903 | sb_data_e1x.common.p_func.pf_id, |
904 | sb_data_e1x.common.p_func.vf_id, | |
905 | sb_data_e1x.common.p_func.vf_valid, | |
906 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
907 | sb_data_e1x.common.same_igu_sb_1b, |
908 | sb_data_e1x.common.state); | |
f2e0899f | 909 | } |
523224a3 DK |
910 | |
911 | /* SB_SMs data */ | |
912 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
913 | pr_cont("SM[%d] __flags (0x%x) " | |
914 | "igu_sb_id (0x%x) igu_seg_id(0x%x) " | |
915 | "time_to_expire (0x%x) " | |
916 | "timer_value(0x%x)\n", j, | |
917 | hc_sm_p[j].__flags, | |
918 | hc_sm_p[j].igu_sb_id, | |
919 | hc_sm_p[j].igu_seg_id, | |
920 | hc_sm_p[j].time_to_expire, | |
921 | hc_sm_p[j].timer_value); | |
922 | } | |
923 | ||
924 | /* Indecies data */ | |
925 | for (j = 0; j < loop; j++) { | |
926 | pr_cont("INDEX[%d] flags (0x%x) " | |
927 | "timeout (0x%x)\n", j, | |
928 | hc_index_p[j].flags, | |
929 | hc_index_p[j].timeout); | |
930 | } | |
8440d2b6 | 931 | } |
a2fbb9ea | 932 | |
523224a3 | 933 | #ifdef BNX2X_STOP_ON_ERROR |
8440d2b6 EG |
934 | /* Rings */ |
935 | /* Rx */ | |
ec6ba945 | 936 | for_each_rx_queue(bp, i) { |
8440d2b6 | 937 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea ET |
938 | |
939 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); | |
940 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 941 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
942 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
943 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
944 | ||
c3eefaf6 EG |
945 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
946 | i, j, rx_bd[1], rx_bd[0], sw_bd->skb); | |
a2fbb9ea ET |
947 | } |
948 | ||
3196a88a EG |
949 | start = RX_SGE(fp->rx_sge_prod); |
950 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 951 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
952 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
953 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
954 | ||
c3eefaf6 EG |
955 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
956 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
957 | } |
958 | ||
a2fbb9ea ET |
959 | start = RCQ_BD(fp->rx_comp_cons - 10); |
960 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 961 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
962 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
963 | ||
c3eefaf6 EG |
964 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
965 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
966 | } |
967 | } | |
968 | ||
8440d2b6 | 969 | /* Tx */ |
ec6ba945 | 970 | for_each_tx_queue(bp, i) { |
8440d2b6 | 971 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
6383c0b3 AE |
972 | for_each_cos_in_tx_queue(fp, cos) { |
973 | struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; | |
974 | ||
975 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); | |
976 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
977 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
978 | struct sw_tx_bd *sw_bd = | |
979 | &txdata->tx_buf_ring[j]; | |
980 | ||
981 | BNX2X_ERR("fp%d: txdata %d, " | |
982 | "packet[%x]=[%p,%x]\n", | |
983 | i, cos, j, sw_bd->skb, | |
984 | sw_bd->first_bd); | |
985 | } | |
8440d2b6 | 986 | |
6383c0b3 AE |
987 | start = TX_BD(txdata->tx_bd_cons - 10); |
988 | end = TX_BD(txdata->tx_bd_cons + 254); | |
989 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
990 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 991 | |
6383c0b3 AE |
992 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" |
993 | "[%x:%x:%x:%x]\n", | |
994 | i, cos, j, tx_bd[0], tx_bd[1], | |
995 | tx_bd[2], tx_bd[3]); | |
996 | } | |
8440d2b6 EG |
997 | } |
998 | } | |
523224a3 | 999 | #endif |
34f80b04 | 1000 | bnx2x_fw_dump(bp); |
a2fbb9ea ET |
1001 | bnx2x_mc_assert(bp); |
1002 | BNX2X_ERR("end crash dump -----------------\n"); | |
a2fbb9ea ET |
1003 | } |
1004 | ||
619c5cb6 VZ |
1005 | /* |
1006 | * FLR Support for E2 | |
1007 | * | |
1008 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
1009 | * initialization. | |
1010 | */ | |
1011 | #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ | |
1012 | #define FLR_WAIT_INTERAVAL 50 /* usec */ | |
1013 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */ | |
1014 | ||
1015 | struct pbf_pN_buf_regs { | |
1016 | int pN; | |
1017 | u32 init_crd; | |
1018 | u32 crd; | |
1019 | u32 crd_freed; | |
1020 | }; | |
1021 | ||
1022 | struct pbf_pN_cmd_regs { | |
1023 | int pN; | |
1024 | u32 lines_occup; | |
1025 | u32 lines_freed; | |
1026 | }; | |
1027 | ||
1028 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
1029 | struct pbf_pN_buf_regs *regs, | |
1030 | u32 poll_count) | |
1031 | { | |
1032 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
1033 | u32 cur_cnt = poll_count; | |
1034 | ||
1035 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
1036 | crd = crd_start = REG_RD(bp, regs->crd); | |
1037 | init_crd = REG_RD(bp, regs->init_crd); | |
1038 | ||
1039 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
1040 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
1041 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
1042 | ||
1043 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
1044 | (init_crd - crd_start))) { | |
1045 | if (cur_cnt--) { | |
1046 | udelay(FLR_WAIT_INTERAVAL); | |
1047 | crd = REG_RD(bp, regs->crd); | |
1048 | crd_freed = REG_RD(bp, regs->crd_freed); | |
1049 | } else { | |
1050 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
1051 | regs->pN); | |
1052 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
1053 | regs->pN, crd); | |
1054 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
1055 | regs->pN, crd_freed); | |
1056 | break; | |
1057 | } | |
1058 | } | |
1059 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
1060 | poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); | |
1061 | } | |
1062 | ||
1063 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
1064 | struct pbf_pN_cmd_regs *regs, | |
1065 | u32 poll_count) | |
1066 | { | |
1067 | u32 occup, to_free, freed, freed_start; | |
1068 | u32 cur_cnt = poll_count; | |
1069 | ||
1070 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
1071 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
1072 | ||
1073 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
1074 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
1075 | ||
1076 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
1077 | if (cur_cnt--) { | |
1078 | udelay(FLR_WAIT_INTERAVAL); | |
1079 | occup = REG_RD(bp, regs->lines_occup); | |
1080 | freed = REG_RD(bp, regs->lines_freed); | |
1081 | } else { | |
1082 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
1083 | regs->pN); | |
1084 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
1085 | regs->pN, occup); | |
1086 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
1087 | regs->pN, freed); | |
1088 | break; | |
1089 | } | |
1090 | } | |
1091 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
1092 | poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); | |
1093 | } | |
1094 | ||
1095 | static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, | |
1096 | u32 expected, u32 poll_count) | |
1097 | { | |
1098 | u32 cur_cnt = poll_count; | |
1099 | u32 val; | |
1100 | ||
1101 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
1102 | udelay(FLR_WAIT_INTERAVAL); | |
1103 | ||
1104 | return val; | |
1105 | } | |
1106 | ||
1107 | static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, | |
1108 | char *msg, u32 poll_cnt) | |
1109 | { | |
1110 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1111 | if (val != 0) { | |
1112 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1113 | return 1; | |
1114 | } | |
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
1119 | { | |
1120 | /* adjust polling timeout */ | |
1121 | if (CHIP_REV_IS_EMUL(bp)) | |
1122 | return FLR_POLL_CNT * 2000; | |
1123 | ||
1124 | if (CHIP_REV_IS_FPGA(bp)) | |
1125 | return FLR_POLL_CNT * 120; | |
1126 | ||
1127 | return FLR_POLL_CNT; | |
1128 | } | |
1129 | ||
1130 | static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) | |
1131 | { | |
1132 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1133 | {0, (CHIP_IS_E3B0(bp)) ? | |
1134 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1135 | PBF_REG_P0_TQ_OCCUPANCY, | |
1136 | (CHIP_IS_E3B0(bp)) ? | |
1137 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1138 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1139 | {1, (CHIP_IS_E3B0(bp)) ? | |
1140 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1141 | PBF_REG_P1_TQ_OCCUPANCY, | |
1142 | (CHIP_IS_E3B0(bp)) ? | |
1143 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1144 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1145 | {4, (CHIP_IS_E3B0(bp)) ? | |
1146 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1147 | PBF_REG_P4_TQ_OCCUPANCY, | |
1148 | (CHIP_IS_E3B0(bp)) ? | |
1149 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1150 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1151 | }; | |
1152 | ||
1153 | struct pbf_pN_buf_regs buf_regs[] = { | |
1154 | {0, (CHIP_IS_E3B0(bp)) ? | |
1155 | PBF_REG_INIT_CRD_Q0 : | |
1156 | PBF_REG_P0_INIT_CRD , | |
1157 | (CHIP_IS_E3B0(bp)) ? | |
1158 | PBF_REG_CREDIT_Q0 : | |
1159 | PBF_REG_P0_CREDIT, | |
1160 | (CHIP_IS_E3B0(bp)) ? | |
1161 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1162 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1163 | {1, (CHIP_IS_E3B0(bp)) ? | |
1164 | PBF_REG_INIT_CRD_Q1 : | |
1165 | PBF_REG_P1_INIT_CRD, | |
1166 | (CHIP_IS_E3B0(bp)) ? | |
1167 | PBF_REG_CREDIT_Q1 : | |
1168 | PBF_REG_P1_CREDIT, | |
1169 | (CHIP_IS_E3B0(bp)) ? | |
1170 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1171 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1172 | {4, (CHIP_IS_E3B0(bp)) ? | |
1173 | PBF_REG_INIT_CRD_LB_Q : | |
1174 | PBF_REG_P4_INIT_CRD, | |
1175 | (CHIP_IS_E3B0(bp)) ? | |
1176 | PBF_REG_CREDIT_LB_Q : | |
1177 | PBF_REG_P4_CREDIT, | |
1178 | (CHIP_IS_E3B0(bp)) ? | |
1179 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1180 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1181 | }; | |
1182 | ||
1183 | int i; | |
1184 | ||
1185 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1186 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1187 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1188 | ||
1189 | ||
1190 | /* Verify the transmission buffers are flushed P0, P1, P4 */ | |
1191 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1192 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1193 | } | |
1194 | ||
1195 | #define OP_GEN_PARAM(param) \ | |
1196 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1197 | ||
1198 | #define OP_GEN_TYPE(type) \ | |
1199 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1200 | ||
1201 | #define OP_GEN_AGG_VECT(index) \ | |
1202 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1203 | ||
1204 | ||
1205 | static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, | |
1206 | u32 poll_cnt) | |
1207 | { | |
1208 | struct sdm_op_gen op_gen = {0}; | |
1209 | ||
1210 | u32 comp_addr = BAR_CSTRORM_INTMEM + | |
1211 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1212 | int ret = 0; | |
1213 | ||
1214 | if (REG_RD(bp, comp_addr)) { | |
1215 | BNX2X_ERR("Cleanup complete is not 0\n"); | |
1216 | return 1; | |
1217 | } | |
1218 | ||
1219 | op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); | |
1220 | op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1221 | op_gen.command |= OP_GEN_AGG_VECT(clnup_func); | |
1222 | op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
1223 | ||
1224 | DP(BNX2X_MSG_SP, "FW Final cleanup\n"); | |
1225 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); | |
1226 | ||
1227 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1228 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
1229 | ret = 1; | |
1230 | } | |
1231 | /* Zero completion for nxt FLR */ | |
1232 | REG_WR(bp, comp_addr, 0); | |
1233 | ||
1234 | return ret; | |
1235 | } | |
1236 | ||
1237 | static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) | |
1238 | { | |
1239 | int pos; | |
1240 | u16 status; | |
1241 | ||
77c98e6a | 1242 | pos = pci_pcie_cap(dev); |
619c5cb6 VZ |
1243 | if (!pos) |
1244 | return false; | |
1245 | ||
1246 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); | |
1247 | return status & PCI_EXP_DEVSTA_TRPND; | |
1248 | } | |
1249 | ||
1250 | /* PF FLR specific routines | |
1251 | */ | |
1252 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1253 | { | |
1254 | ||
1255 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ | |
1256 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1257 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1258 | "CFC PF usage counter timed out", | |
1259 | poll_cnt)) | |
1260 | return 1; | |
1261 | ||
1262 | ||
1263 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ | |
1264 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1265 | DORQ_REG_PF_USAGE_CNT, | |
1266 | "DQ PF usage counter timed out", | |
1267 | poll_cnt)) | |
1268 | return 1; | |
1269 | ||
1270 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1271 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1272 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1273 | "QM PF usage counter timed out", | |
1274 | poll_cnt)) | |
1275 | return 1; | |
1276 | ||
1277 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1278 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1279 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1280 | "Timers VNIC usage counter timed out", | |
1281 | poll_cnt)) | |
1282 | return 1; | |
1283 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1284 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1285 | "Timers NUM_SCANS usage counter timed out", | |
1286 | poll_cnt)) | |
1287 | return 1; | |
1288 | ||
1289 | /* Wait DMAE PF usage counter to zero */ | |
1290 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1291 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
1292 | "DMAE dommand register timed out", | |
1293 | poll_cnt)) | |
1294 | return 1; | |
1295 | ||
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1300 | { | |
1301 | u32 val; | |
1302 | ||
1303 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1304 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1305 | ||
1306 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1307 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1308 | ||
1309 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1310 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1311 | ||
1312 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1313 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1314 | ||
1315 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1316 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1317 | ||
1318 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1319 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1320 | ||
1321 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1322 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1323 | ||
1324 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1325 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1326 | val); | |
1327 | } | |
1328 | ||
1329 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1330 | { | |
1331 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1332 | ||
1333 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1334 | ||
1335 | /* Re-enable PF target read access */ | |
1336 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1337 | ||
1338 | /* Poll HW usage counters */ | |
1339 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) | |
1340 | return -EBUSY; | |
1341 | ||
1342 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1343 | ||
1344 | /* Send the FW cleanup command */ | |
1345 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1346 | return -EBUSY; | |
1347 | ||
1348 | /* ATC cleanup */ | |
1349 | ||
1350 | /* Verify TX hw is flushed */ | |
1351 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1352 | ||
1353 | /* Wait 100ms (not adjusted according to platform) */ | |
1354 | msleep(100); | |
1355 | ||
1356 | /* Verify no pending pci transactions */ | |
1357 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1358 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1359 | ||
1360 | /* Debug */ | |
1361 | bnx2x_hw_enable_status(bp); | |
1362 | ||
1363 | /* | |
1364 | * Master enable - Due to WB DMAE writes performed before this | |
1365 | * register is re-initialized as part of the regular function init | |
1366 | */ | |
1367 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1368 | ||
1369 | return 0; | |
1370 | } | |
1371 | ||
f2e0899f | 1372 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1373 | { |
34f80b04 | 1374 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1375 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1376 | u32 val = REG_RD(bp, addr); | |
1377 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
8badd27a | 1378 | int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; |
a2fbb9ea ET |
1379 | |
1380 | if (msix) { | |
8badd27a EG |
1381 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1382 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1383 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1384 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
8badd27a EG |
1385 | } else if (msi) { |
1386 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1387 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1388 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1389 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1390 | } else { |
1391 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1392 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1393 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1394 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1395 | |
a0fd065c DK |
1396 | if (!CHIP_IS_E1(bp)) { |
1397 | DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", | |
1398 | val, port, addr); | |
615f8fd9 | 1399 | |
a0fd065c | 1400 | REG_WR(bp, addr, val); |
615f8fd9 | 1401 | |
a0fd065c DK |
1402 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1403 | } | |
a2fbb9ea ET |
1404 | } |
1405 | ||
a0fd065c DK |
1406 | if (CHIP_IS_E1(bp)) |
1407 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1408 | ||
8badd27a EG |
1409 | DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", |
1410 | val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1411 | |
1412 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1413 | /* |
1414 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1415 | */ | |
1416 | mmiowb(); | |
1417 | barrier(); | |
34f80b04 | 1418 | |
f2e0899f | 1419 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1420 | /* init leading/trailing edge */ |
fb3bff17 | 1421 | if (IS_MF(bp)) { |
8badd27a | 1422 | val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); |
34f80b04 | 1423 | if (bp->port.pmf) |
4acac6a5 EG |
1424 | /* enable nig and gpio3 attention */ |
1425 | val |= 0x1100; | |
34f80b04 EG |
1426 | } else |
1427 | val = 0xffff; | |
1428 | ||
1429 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1430 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1431 | } | |
37dbbf32 EG |
1432 | |
1433 | /* Make sure that interrupts are indeed enabled from here on */ | |
1434 | mmiowb(); | |
a2fbb9ea ET |
1435 | } |
1436 | ||
f2e0899f DK |
1437 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1438 | { | |
1439 | u32 val; | |
1440 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
1441 | int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; | |
1442 | ||
1443 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1444 | ||
1445 | if (msix) { | |
1446 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1447 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1448 | val |= (IGU_PF_CONF_FUNC_EN | | |
1449 | IGU_PF_CONF_MSI_MSIX_EN | | |
1450 | IGU_PF_CONF_ATTN_BIT_EN); | |
1451 | } else if (msi) { | |
1452 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
1453 | val |= (IGU_PF_CONF_FUNC_EN | | |
1454 | IGU_PF_CONF_MSI_MSIX_EN | | |
1455 | IGU_PF_CONF_ATTN_BIT_EN | | |
1456 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1457 | } else { | |
1458 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
1459 | val |= (IGU_PF_CONF_FUNC_EN | | |
1460 | IGU_PF_CONF_INT_LINE_EN | | |
1461 | IGU_PF_CONF_ATTN_BIT_EN | | |
1462 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1463 | } | |
1464 | ||
1465 | DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", | |
1466 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
1467 | ||
1468 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1469 | ||
1470 | barrier(); | |
1471 | ||
1472 | /* init leading/trailing edge */ | |
1473 | if (IS_MF(bp)) { | |
1474 | val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); | |
1475 | if (bp->port.pmf) | |
1476 | /* enable nig and gpio3 attention */ | |
1477 | val |= 0x1100; | |
1478 | } else | |
1479 | val = 0xffff; | |
1480 | ||
1481 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1482 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1483 | ||
1484 | /* Make sure that interrupts are indeed enabled from here on */ | |
1485 | mmiowb(); | |
1486 | } | |
1487 | ||
1488 | void bnx2x_int_enable(struct bnx2x *bp) | |
1489 | { | |
1490 | if (bp->common.int_block == INT_BLOCK_HC) | |
1491 | bnx2x_hc_int_enable(bp); | |
1492 | else | |
1493 | bnx2x_igu_int_enable(bp); | |
1494 | } | |
1495 | ||
1496 | static void bnx2x_hc_int_disable(struct bnx2x *bp) | |
a2fbb9ea | 1497 | { |
34f80b04 | 1498 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1499 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1500 | u32 val = REG_RD(bp, addr); | |
1501 | ||
a0fd065c DK |
1502 | /* |
1503 | * in E1 we must use only PCI configuration space to disable | |
1504 | * MSI/MSIX capablility | |
1505 | * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
1506 | */ | |
1507 | if (CHIP_IS_E1(bp)) { | |
1508 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
1509 | * Use mask register to prevent from HC sending interrupts | |
1510 | * after we exit the function | |
1511 | */ | |
1512 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
1513 | ||
1514 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1515 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1516 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
1517 | } else | |
1518 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1519 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1520 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1521 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1522 | |
1523 | DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", | |
1524 | val, port, addr); | |
1525 | ||
8badd27a EG |
1526 | /* flush all outstanding writes */ |
1527 | mmiowb(); | |
1528 | ||
a2fbb9ea ET |
1529 | REG_WR(bp, addr, val); |
1530 | if (REG_RD(bp, addr) != val) | |
1531 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1532 | } | |
1533 | ||
f2e0899f DK |
1534 | static void bnx2x_igu_int_disable(struct bnx2x *bp) |
1535 | { | |
1536 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1537 | ||
1538 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
1539 | IGU_PF_CONF_INT_LINE_EN | | |
1540 | IGU_PF_CONF_ATTN_BIT_EN); | |
1541 | ||
1542 | DP(NETIF_MSG_INTR, "write %x to IGU\n", val); | |
1543 | ||
1544 | /* flush all outstanding writes */ | |
1545 | mmiowb(); | |
1546 | ||
1547 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1548 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
1549 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1550 | } | |
1551 | ||
6383c0b3 | 1552 | void bnx2x_int_disable(struct bnx2x *bp) |
f2e0899f DK |
1553 | { |
1554 | if (bp->common.int_block == INT_BLOCK_HC) | |
1555 | bnx2x_hc_int_disable(bp); | |
1556 | else | |
1557 | bnx2x_igu_int_disable(bp); | |
1558 | } | |
1559 | ||
9f6c9258 | 1560 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1561 | { |
a2fbb9ea | 1562 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1563 | int i, offset; |
a2fbb9ea | 1564 | |
f8ef6e44 YG |
1565 | if (disable_hw) |
1566 | /* prevent the HW from sending interrupts */ | |
1567 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1568 | |
1569 | /* make sure all ISRs are done */ | |
1570 | if (msix) { | |
8badd27a EG |
1571 | synchronize_irq(bp->msix_table[0].vector); |
1572 | offset = 1; | |
37b091ba MC |
1573 | #ifdef BCM_CNIC |
1574 | offset++; | |
1575 | #endif | |
ec6ba945 | 1576 | for_each_eth_queue(bp, i) |
754a2f52 | 1577 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1578 | } else |
1579 | synchronize_irq(bp->pdev->irq); | |
1580 | ||
1581 | /* make sure sp_task is not running */ | |
1cf167f2 | 1582 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1583 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1584 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1585 | } |
1586 | ||
34f80b04 | 1587 | /* fast path */ |
a2fbb9ea ET |
1588 | |
1589 | /* | |
34f80b04 | 1590 | * General service functions |
a2fbb9ea ET |
1591 | */ |
1592 | ||
72fd0718 VZ |
1593 | /* Return true if succeeded to acquire the lock */ |
1594 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1595 | { | |
1596 | u32 lock_status; | |
1597 | u32 resource_bit = (1 << resource); | |
1598 | int func = BP_FUNC(bp); | |
1599 | u32 hw_lock_control_reg; | |
1600 | ||
1601 | DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); | |
1602 | ||
1603 | /* Validating that the resource is within range */ | |
1604 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
1605 | DP(NETIF_MSG_HW, | |
1606 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", | |
1607 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1608 | return false; |
72fd0718 VZ |
1609 | } |
1610 | ||
1611 | if (func <= 5) | |
1612 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1613 | else | |
1614 | hw_lock_control_reg = | |
1615 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1616 | ||
1617 | /* Try to acquire the lock */ | |
1618 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1619 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1620 | if (lock_status & resource_bit) | |
1621 | return true; | |
1622 | ||
1623 | DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); | |
1624 | return false; | |
1625 | } | |
1626 | ||
c9ee9206 VZ |
1627 | /** |
1628 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1629 | * | |
1630 | * @bp: driver handle | |
1631 | * | |
1632 | * Returns the recovery leader resource id according to the engine this function | |
1633 | * belongs to. Currently only only 2 engines is supported. | |
1634 | */ | |
1635 | static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) | |
1636 | { | |
1637 | if (BP_PATH(bp)) | |
1638 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1639 | else | |
1640 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1641 | } | |
1642 | ||
1643 | /** | |
1644 | * bnx2x_trylock_leader_lock- try to aquire a leader lock. | |
1645 | * | |
1646 | * @bp: driver handle | |
1647 | * | |
1648 | * Tries to aquire a leader lock for cuurent engine. | |
1649 | */ | |
1650 | static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) | |
1651 | { | |
1652 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1653 | } | |
1654 | ||
993ac7b5 | 1655 | #ifdef BCM_CNIC |
619c5cb6 | 1656 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
993ac7b5 | 1657 | #endif |
3196a88a | 1658 | |
619c5cb6 | 1659 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1660 | { |
1661 | struct bnx2x *bp = fp->bp; | |
1662 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1663 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 VZ |
1664 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
1665 | struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; | |
a2fbb9ea | 1666 | |
34f80b04 | 1667 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1668 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1669 | fp->index, cid, command, bp->state, |
34f80b04 | 1670 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1671 | |
619c5cb6 VZ |
1672 | switch (command) { |
1673 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1674 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1675 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1676 | break; | |
d6cae238 | 1677 | |
619c5cb6 | 1678 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1679 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1680 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1681 | break; |
1682 | ||
6383c0b3 AE |
1683 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
1684 | DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); | |
1685 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
1686 | break; | |
1687 | ||
619c5cb6 | 1688 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1689 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1690 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1691 | break; |
1692 | ||
619c5cb6 | 1693 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
d6cae238 | 1694 | DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); |
619c5cb6 | 1695 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1696 | break; |
1697 | ||
619c5cb6 | 1698 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1699 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1700 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1701 | break; |
619c5cb6 VZ |
1702 | |
1703 | default: | |
1704 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1705 | command, fp->index); | |
1706 | return; | |
523224a3 | 1707 | } |
3196a88a | 1708 | |
619c5cb6 VZ |
1709 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1710 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1711 | /* q_obj->complete_cmd() failure means that this was | |
1712 | * an unexpected completion. | |
1713 | * | |
1714 | * In this case we don't want to increase the bp->spq_left | |
1715 | * because apparently we haven't sent this command the first | |
1716 | * place. | |
1717 | */ | |
1718 | #ifdef BNX2X_STOP_ON_ERROR | |
1719 | bnx2x_panic(); | |
1720 | #else | |
1721 | return; | |
1722 | #endif | |
1723 | ||
8fe23fbd | 1724 | smp_mb__before_atomic_inc(); |
6e30dd4e | 1725 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 VZ |
1726 | /* push the change in bp->spq_left and towards the memory */ |
1727 | smp_mb__after_atomic_inc(); | |
49d66772 | 1728 | |
d6cae238 VZ |
1729 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1730 | ||
523224a3 | 1731 | return; |
a2fbb9ea ET |
1732 | } |
1733 | ||
619c5cb6 VZ |
1734 | void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
1735 | u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) | |
1736 | { | |
1737 | u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; | |
1738 | ||
1739 | bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, | |
1740 | start); | |
1741 | } | |
1742 | ||
9f6c9258 | 1743 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1744 | { |
555f6c78 | 1745 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1746 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1747 | u16 mask; |
ca00392c | 1748 | int i; |
6383c0b3 | 1749 | u8 cos; |
a2fbb9ea | 1750 | |
34f80b04 | 1751 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1752 | if (unlikely(status == 0)) { |
1753 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1754 | return IRQ_NONE; | |
1755 | } | |
f5372251 | 1756 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1757 | |
3196a88a EG |
1758 | #ifdef BNX2X_STOP_ON_ERROR |
1759 | if (unlikely(bp->panic)) | |
1760 | return IRQ_HANDLED; | |
1761 | #endif | |
1762 | ||
ec6ba945 | 1763 | for_each_eth_queue(bp, i) { |
ca00392c | 1764 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1765 | |
6383c0b3 | 1766 | mask = 0x2 << (fp->index + CNIC_PRESENT); |
ca00392c | 1767 | if (status & mask) { |
619c5cb6 | 1768 | /* Handle Rx or Tx according to SB id */ |
54b9ddaa | 1769 | prefetch(fp->rx_cons_sb); |
6383c0b3 AE |
1770 | for_each_cos_in_tx_queue(fp, cos) |
1771 | prefetch(fp->txdata[cos].tx_cons_sb); | |
523224a3 | 1772 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
54b9ddaa | 1773 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1774 | status &= ~mask; |
1775 | } | |
a2fbb9ea ET |
1776 | } |
1777 | ||
993ac7b5 | 1778 | #ifdef BCM_CNIC |
523224a3 | 1779 | mask = 0x2; |
993ac7b5 MC |
1780 | if (status & (mask | 0x1)) { |
1781 | struct cnic_ops *c_ops = NULL; | |
1782 | ||
619c5cb6 VZ |
1783 | if (likely(bp->state == BNX2X_STATE_OPEN)) { |
1784 | rcu_read_lock(); | |
1785 | c_ops = rcu_dereference(bp->cnic_ops); | |
1786 | if (c_ops) | |
1787 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1788 | rcu_read_unlock(); | |
1789 | } | |
993ac7b5 MC |
1790 | |
1791 | status &= ~mask; | |
1792 | } | |
1793 | #endif | |
a2fbb9ea | 1794 | |
34f80b04 | 1795 | if (unlikely(status & 0x1)) { |
1cf167f2 | 1796 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
1797 | |
1798 | status &= ~0x1; | |
1799 | if (!status) | |
1800 | return IRQ_HANDLED; | |
1801 | } | |
1802 | ||
cdaa7cb8 VZ |
1803 | if (unlikely(status)) |
1804 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1805 | status); |
a2fbb9ea | 1806 | |
c18487ee | 1807 | return IRQ_HANDLED; |
a2fbb9ea ET |
1808 | } |
1809 | ||
c18487ee YR |
1810 | /* Link */ |
1811 | ||
1812 | /* | |
1813 | * General service functions | |
1814 | */ | |
a2fbb9ea | 1815 | |
9f6c9258 | 1816 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1817 | { |
1818 | u32 lock_status; | |
1819 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1820 | int func = BP_FUNC(bp); |
1821 | u32 hw_lock_control_reg; | |
c18487ee | 1822 | int cnt; |
a2fbb9ea | 1823 | |
c18487ee YR |
1824 | /* Validating that the resource is within range */ |
1825 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
1826 | DP(NETIF_MSG_HW, | |
1827 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", | |
1828 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
1829 | return -EINVAL; | |
1830 | } | |
a2fbb9ea | 1831 | |
4a37fb66 YG |
1832 | if (func <= 5) { |
1833 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1834 | } else { | |
1835 | hw_lock_control_reg = | |
1836 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1837 | } | |
1838 | ||
c18487ee | 1839 | /* Validating that the resource is not already taken */ |
4a37fb66 | 1840 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee YR |
1841 | if (lock_status & resource_bit) { |
1842 | DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", | |
1843 | lock_status, resource_bit); | |
1844 | return -EEXIST; | |
1845 | } | |
a2fbb9ea | 1846 | |
46230476 EG |
1847 | /* Try for 5 second every 5ms */ |
1848 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 1849 | /* Try to acquire the lock */ |
4a37fb66 YG |
1850 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
1851 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
1852 | if (lock_status & resource_bit) |
1853 | return 0; | |
a2fbb9ea | 1854 | |
c18487ee | 1855 | msleep(5); |
a2fbb9ea | 1856 | } |
c18487ee YR |
1857 | DP(NETIF_MSG_HW, "Timeout\n"); |
1858 | return -EAGAIN; | |
1859 | } | |
a2fbb9ea | 1860 | |
c9ee9206 VZ |
1861 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
1862 | { | |
1863 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1864 | } | |
1865 | ||
9f6c9258 | 1866 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1867 | { |
1868 | u32 lock_status; | |
1869 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1870 | int func = BP_FUNC(bp); |
1871 | u32 hw_lock_control_reg; | |
a2fbb9ea | 1872 | |
72fd0718 VZ |
1873 | DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); |
1874 | ||
c18487ee YR |
1875 | /* Validating that the resource is within range */ |
1876 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
1877 | DP(NETIF_MSG_HW, | |
1878 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", | |
1879 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
1880 | return -EINVAL; | |
1881 | } | |
1882 | ||
4a37fb66 YG |
1883 | if (func <= 5) { |
1884 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1885 | } else { | |
1886 | hw_lock_control_reg = | |
1887 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1888 | } | |
1889 | ||
c18487ee | 1890 | /* Validating that the resource is currently taken */ |
4a37fb66 | 1891 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee YR |
1892 | if (!(lock_status & resource_bit)) { |
1893 | DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", | |
1894 | lock_status, resource_bit); | |
1895 | return -EFAULT; | |
a2fbb9ea ET |
1896 | } |
1897 | ||
9f6c9258 DK |
1898 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
1899 | return 0; | |
c18487ee | 1900 | } |
a2fbb9ea | 1901 | |
9f6c9258 | 1902 | |
4acac6a5 EG |
1903 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
1904 | { | |
1905 | /* The GPIO should be swapped if swap register is set and active */ | |
1906 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1907 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1908 | int gpio_shift = gpio_num + | |
1909 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1910 | u32 gpio_mask = (1 << gpio_shift); | |
1911 | u32 gpio_reg; | |
1912 | int value; | |
1913 | ||
1914 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1915 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1916 | return -EINVAL; | |
1917 | } | |
1918 | ||
1919 | /* read GPIO value */ | |
1920 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1921 | ||
1922 | /* get the requested pin value */ | |
1923 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
1924 | value = 1; | |
1925 | else | |
1926 | value = 0; | |
1927 | ||
1928 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); | |
1929 | ||
1930 | return value; | |
1931 | } | |
1932 | ||
17de50b7 | 1933 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
1934 | { |
1935 | /* The GPIO should be swapped if swap register is set and active */ | |
1936 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 1937 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
1938 | int gpio_shift = gpio_num + |
1939 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1940 | u32 gpio_mask = (1 << gpio_shift); | |
1941 | u32 gpio_reg; | |
a2fbb9ea | 1942 | |
c18487ee YR |
1943 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
1944 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1945 | return -EINVAL; | |
1946 | } | |
a2fbb9ea | 1947 | |
4a37fb66 | 1948 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
1949 | /* read GPIO and mask except the float bits */ |
1950 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 1951 | |
c18487ee YR |
1952 | switch (mode) { |
1953 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
1954 | DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", | |
1955 | gpio_num, gpio_shift); | |
1956 | /* clear FLOAT and set CLR */ | |
1957 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1958 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
1959 | break; | |
a2fbb9ea | 1960 | |
c18487ee YR |
1961 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
1962 | DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", | |
1963 | gpio_num, gpio_shift); | |
1964 | /* clear FLOAT and set SET */ | |
1965 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1966 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
1967 | break; | |
a2fbb9ea | 1968 | |
17de50b7 | 1969 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
c18487ee YR |
1970 | DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", |
1971 | gpio_num, gpio_shift); | |
1972 | /* set FLOAT */ | |
1973 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1974 | break; | |
a2fbb9ea | 1975 | |
c18487ee YR |
1976 | default: |
1977 | break; | |
a2fbb9ea ET |
1978 | } |
1979 | ||
c18487ee | 1980 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 1981 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 1982 | |
c18487ee | 1983 | return 0; |
a2fbb9ea ET |
1984 | } |
1985 | ||
0d40f0d4 YR |
1986 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
1987 | { | |
1988 | u32 gpio_reg = 0; | |
1989 | int rc = 0; | |
1990 | ||
1991 | /* Any port swapping should be handled by caller. */ | |
1992 | ||
1993 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1994 | /* read GPIO and mask except the float bits */ | |
1995 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1996 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1997 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1998 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
1999 | ||
2000 | switch (mode) { | |
2001 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
2002 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
2003 | /* set CLR */ | |
2004 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2005 | break; | |
2006 | ||
2007 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
2008 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
2009 | /* set SET */ | |
2010 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
2011 | break; | |
2012 | ||
2013 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
2014 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
2015 | /* set FLOAT */ | |
2016 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2017 | break; | |
2018 | ||
2019 | default: | |
2020 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
2021 | rc = -EINVAL; | |
2022 | break; | |
2023 | } | |
2024 | ||
2025 | if (rc == 0) | |
2026 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
2027 | ||
2028 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2029 | ||
2030 | return rc; | |
2031 | } | |
2032 | ||
4acac6a5 EG |
2033 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
2034 | { | |
2035 | /* The GPIO should be swapped if swap register is set and active */ | |
2036 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2037 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2038 | int gpio_shift = gpio_num + | |
2039 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2040 | u32 gpio_mask = (1 << gpio_shift); | |
2041 | u32 gpio_reg; | |
2042 | ||
2043 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2044 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2045 | return -EINVAL; | |
2046 | } | |
2047 | ||
2048 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2049 | /* read GPIO int */ | |
2050 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
2051 | ||
2052 | switch (mode) { | |
2053 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
2054 | DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " | |
2055 | "output low\n", gpio_num, gpio_shift); | |
2056 | /* clear SET and set CLR */ | |
2057 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2058 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2059 | break; | |
2060 | ||
2061 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
2062 | DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " | |
2063 | "output high\n", gpio_num, gpio_shift); | |
2064 | /* clear CLR and set SET */ | |
2065 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2066 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2067 | break; | |
2068 | ||
2069 | default: | |
2070 | break; | |
2071 | } | |
2072 | ||
2073 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2074 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2075 | ||
2076 | return 0; | |
2077 | } | |
2078 | ||
c18487ee | 2079 | static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) |
a2fbb9ea | 2080 | { |
c18487ee YR |
2081 | u32 spio_mask = (1 << spio_num); |
2082 | u32 spio_reg; | |
a2fbb9ea | 2083 | |
c18487ee YR |
2084 | if ((spio_num < MISC_REGISTERS_SPIO_4) || |
2085 | (spio_num > MISC_REGISTERS_SPIO_7)) { | |
2086 | BNX2X_ERR("Invalid SPIO %d\n", spio_num); | |
2087 | return -EINVAL; | |
a2fbb9ea ET |
2088 | } |
2089 | ||
4a37fb66 | 2090 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee YR |
2091 | /* read SPIO and mask except the float bits */ |
2092 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); | |
a2fbb9ea | 2093 | |
c18487ee | 2094 | switch (mode) { |
6378c025 | 2095 | case MISC_REGISTERS_SPIO_OUTPUT_LOW: |
c18487ee YR |
2096 | DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); |
2097 | /* clear FLOAT and set CLR */ | |
2098 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2099 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); | |
2100 | break; | |
a2fbb9ea | 2101 | |
6378c025 | 2102 | case MISC_REGISTERS_SPIO_OUTPUT_HIGH: |
c18487ee YR |
2103 | DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); |
2104 | /* clear FLOAT and set SET */ | |
2105 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2106 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); | |
2107 | break; | |
a2fbb9ea | 2108 | |
c18487ee YR |
2109 | case MISC_REGISTERS_SPIO_INPUT_HI_Z: |
2110 | DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); | |
2111 | /* set FLOAT */ | |
2112 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2113 | break; | |
a2fbb9ea | 2114 | |
c18487ee YR |
2115 | default: |
2116 | break; | |
a2fbb9ea ET |
2117 | } |
2118 | ||
c18487ee | 2119 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2120 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2121 | |
a2fbb9ea ET |
2122 | return 0; |
2123 | } | |
2124 | ||
9f6c9258 | 2125 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2126 | { |
a22f0788 | 2127 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
ad33ea3a EG |
2128 | switch (bp->link_vars.ieee_fc & |
2129 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2130 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: |
a22f0788 | 2131 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2132 | ADVERTISED_Pause); |
c18487ee | 2133 | break; |
356e2385 | 2134 | |
c18487ee | 2135 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2136 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2137 | ADVERTISED_Pause); |
c18487ee | 2138 | break; |
356e2385 | 2139 | |
c18487ee | 2140 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2141 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2142 | break; |
356e2385 | 2143 | |
c18487ee | 2144 | default: |
a22f0788 | 2145 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2146 | ADVERTISED_Pause); |
c18487ee YR |
2147 | break; |
2148 | } | |
2149 | } | |
f1410647 | 2150 | |
9f6c9258 | 2151 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
c18487ee | 2152 | { |
19680c48 EG |
2153 | if (!BP_NOMCP(bp)) { |
2154 | u8 rc; | |
a22f0788 YR |
2155 | int cfx_idx = bnx2x_get_link_cfg_idx(bp); |
2156 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
1cb0c788 YR |
2157 | /* |
2158 | * Initialize link parameters structure variables | |
2159 | * It is recommended to turn off RX FC for jumbo frames | |
2160 | * for better performance | |
2161 | */ | |
2162 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
c0700f90 | 2163 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; |
8c99e7b0 | 2164 | else |
c0700f90 | 2165 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; |
a2fbb9ea | 2166 | |
4a37fb66 | 2167 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2168 | |
a22f0788 | 2169 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2170 | struct link_params *lp = &bp->link_params; |
2171 | lp->loopback_mode = LOOPBACK_XGXS; | |
2172 | /* do PHY loopback at 10G speed, if possible */ | |
2173 | if (lp->req_line_speed[cfx_idx] < SPEED_10000) { | |
2174 | if (lp->speed_cap_mask[cfx_idx] & | |
2175 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2176 | lp->req_line_speed[cfx_idx] = | |
2177 | SPEED_10000; | |
2178 | else | |
2179 | lp->req_line_speed[cfx_idx] = | |
2180 | SPEED_1000; | |
2181 | } | |
a22f0788 | 2182 | } |
b5bf9068 | 2183 | |
19680c48 | 2184 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2185 | |
4a37fb66 | 2186 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2187 | |
3c96c68b EG |
2188 | bnx2x_calc_fc_adv(bp); |
2189 | ||
b5bf9068 EG |
2190 | if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { |
2191 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
19680c48 | 2192 | bnx2x_link_report(bp); |
3deb8167 YR |
2193 | } else |
2194 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2195 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2196 | return rc; |
2197 | } | |
f5372251 | 2198 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2199 | return -EINVAL; |
a2fbb9ea ET |
2200 | } |
2201 | ||
9f6c9258 | 2202 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2203 | { |
19680c48 | 2204 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2205 | bnx2x_acquire_phy_lock(bp); |
54c2fb78 | 2206 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
19680c48 | 2207 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2208 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2209 | |
19680c48 EG |
2210 | bnx2x_calc_fc_adv(bp); |
2211 | } else | |
f5372251 | 2212 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2213 | } |
a2fbb9ea | 2214 | |
c18487ee YR |
2215 | static void bnx2x__link_reset(struct bnx2x *bp) |
2216 | { | |
19680c48 | 2217 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2218 | bnx2x_acquire_phy_lock(bp); |
589abe3a | 2219 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
4a37fb66 | 2220 | bnx2x_release_phy_lock(bp); |
19680c48 | 2221 | } else |
f5372251 | 2222 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2223 | } |
a2fbb9ea | 2224 | |
a22f0788 | 2225 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2226 | { |
2145a920 | 2227 | u8 rc = 0; |
a2fbb9ea | 2228 | |
2145a920 VZ |
2229 | if (!BP_NOMCP(bp)) { |
2230 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2231 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2232 | is_serdes); | |
2145a920 VZ |
2233 | bnx2x_release_phy_lock(bp); |
2234 | } else | |
2235 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2236 | |
c18487ee YR |
2237 | return rc; |
2238 | } | |
a2fbb9ea | 2239 | |
8a1c38d1 | 2240 | static void bnx2x_init_port_minmax(struct bnx2x *bp) |
34f80b04 | 2241 | { |
8a1c38d1 EG |
2242 | u32 r_param = bp->link_vars.line_speed / 8; |
2243 | u32 fair_periodic_timeout_usec; | |
2244 | u32 t_fair; | |
34f80b04 | 2245 | |
8a1c38d1 EG |
2246 | memset(&(bp->cmng.rs_vars), 0, |
2247 | sizeof(struct rate_shaping_vars_per_port)); | |
2248 | memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); | |
34f80b04 | 2249 | |
8a1c38d1 EG |
2250 | /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ |
2251 | bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; | |
34f80b04 | 2252 | |
8a1c38d1 EG |
2253 | /* this is the threshold below which no timer arming will occur |
2254 | 1.25 coefficient is for the threshold to be a little bigger | |
2255 | than the real time, to compensate for timer in-accuracy */ | |
2256 | bp->cmng.rs_vars.rs_threshold = | |
34f80b04 EG |
2257 | (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; |
2258 | ||
8a1c38d1 EG |
2259 | /* resolution of fairness timer */ |
2260 | fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; | |
2261 | /* for 10G it is 1000usec. for 1G it is 10000usec. */ | |
2262 | t_fair = T_FAIR_COEF / bp->link_vars.line_speed; | |
34f80b04 | 2263 | |
8a1c38d1 EG |
2264 | /* this is the threshold below which we won't arm the timer anymore */ |
2265 | bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; | |
34f80b04 | 2266 | |
8a1c38d1 EG |
2267 | /* we multiply by 1e3/8 to get bytes/msec. |
2268 | We don't want the credits to pass a credit | |
2269 | of the t_fair*FAIR_MEM (algorithm resolution) */ | |
2270 | bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; | |
2271 | /* since each tick is 4 usec */ | |
2272 | bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; | |
34f80b04 EG |
2273 | } |
2274 | ||
2691d51d EG |
2275 | /* Calculates the sum of vn_min_rates. |
2276 | It's needed for further normalizing of the min_rates. | |
2277 | Returns: | |
2278 | sum of vn_min_rates. | |
2279 | or | |
2280 | 0 - if all the min_rates are 0. | |
2281 | In the later case fainess algorithm should be deactivated. | |
2282 | If not all min_rates are zero then those that are zeroes will be set to 1. | |
2283 | */ | |
2284 | static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) | |
2285 | { | |
2286 | int all_zero = 1; | |
2691d51d EG |
2287 | int vn; |
2288 | ||
2289 | bp->vn_weight_sum = 0; | |
2290 | for (vn = VN_0; vn < E1HVN_MAX; vn++) { | |
f2e0899f | 2291 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2292 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2293 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2294 | ||
2295 | /* Skip hidden vns */ | |
2296 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
2297 | continue; | |
2298 | ||
2299 | /* If min rate is zero - set it to 1 */ | |
2300 | if (!vn_min_rate) | |
2301 | vn_min_rate = DEF_MIN_RATE; | |
2302 | else | |
2303 | all_zero = 0; | |
2304 | ||
2305 | bp->vn_weight_sum += vn_min_rate; | |
2306 | } | |
2307 | ||
30ae438b DK |
2308 | /* if ETS or all min rates are zeros - disable fairness */ |
2309 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
2310 | bp->cmng.flags.cmng_enables &= | |
2311 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | |
2312 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2313 | } else if (all_zero) { | |
b015e3d1 EG |
2314 | bp->cmng.flags.cmng_enables &= |
2315 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | |
2316 | DP(NETIF_MSG_IFUP, "All MIN values are zeroes" | |
2317 | " fairness will be disabled\n"); | |
2318 | } else | |
2319 | bp->cmng.flags.cmng_enables |= | |
2320 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | |
2691d51d EG |
2321 | } |
2322 | ||
f2e0899f | 2323 | static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) |
34f80b04 EG |
2324 | { |
2325 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2326 | struct fairness_vars_per_vn m_fair_vn; | |
f2e0899f DK |
2327 | u32 vn_cfg = bp->mf_config[vn]; |
2328 | int func = 2*vn + BP_PORT(bp); | |
34f80b04 EG |
2329 | u16 vn_min_rate, vn_max_rate; |
2330 | int i; | |
2331 | ||
2332 | /* If function is hidden - set min and max to zeroes */ | |
2333 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { | |
2334 | vn_min_rate = 0; | |
2335 | vn_max_rate = 0; | |
2336 | ||
2337 | } else { | |
faa6fcbb DK |
2338 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2339 | ||
34f80b04 EG |
2340 | vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2341 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
faa6fcbb DK |
2342 | /* If fairness is enabled (not all min rates are zeroes) and |
2343 | if current min rate is zero - set it to 1. | |
2344 | This is a requirement of the algorithm. */ | |
f2e0899f | 2345 | if (bp->vn_weight_sum && (vn_min_rate == 0)) |
34f80b04 | 2346 | vn_min_rate = DEF_MIN_RATE; |
faa6fcbb DK |
2347 | |
2348 | if (IS_MF_SI(bp)) | |
2349 | /* maxCfg in percents of linkspeed */ | |
2350 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
2351 | else | |
2352 | /* maxCfg is absolute in 100Mb units */ | |
2353 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2354 | } |
f85582f8 | 2355 | |
8a1c38d1 | 2356 | DP(NETIF_MSG_IFUP, |
b015e3d1 | 2357 | "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", |
8a1c38d1 | 2358 | func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); |
34f80b04 EG |
2359 | |
2360 | memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); | |
2361 | memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); | |
2362 | ||
2363 | /* global vn counter - maximal Mbps for this vn */ | |
2364 | m_rs_vn.vn_counter.rate = vn_max_rate; | |
2365 | ||
2366 | /* quota - number of bytes transmitted in this period */ | |
2367 | m_rs_vn.vn_counter.quota = | |
2368 | (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2369 | ||
8a1c38d1 | 2370 | if (bp->vn_weight_sum) { |
34f80b04 EG |
2371 | /* credit for each period of the fairness algorithm: |
2372 | number of bytes in T_FAIR (the vn share the port rate). | |
8a1c38d1 EG |
2373 | vn_weight_sum should not be larger than 10000, thus |
2374 | T_FAIR_COEF / (8 * vn_weight_sum) will always be greater | |
2375 | than zero */ | |
34f80b04 | 2376 | m_fair_vn.vn_credit_delta = |
cdaa7cb8 VZ |
2377 | max_t(u32, (vn_min_rate * (T_FAIR_COEF / |
2378 | (8 * bp->vn_weight_sum))), | |
ff80ee02 DK |
2379 | (bp->cmng.fair_vars.fair_threshold + |
2380 | MIN_ABOVE_THRESH)); | |
cdaa7cb8 | 2381 | DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", |
34f80b04 EG |
2382 | m_fair_vn.vn_credit_delta); |
2383 | } | |
2384 | ||
34f80b04 EG |
2385 | /* Store it to internal memory */ |
2386 | for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) | |
2387 | REG_WR(bp, BAR_XSTRORM_INTMEM + | |
2388 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, | |
2389 | ((u32 *)(&m_rs_vn))[i]); | |
2390 | ||
2391 | for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) | |
2392 | REG_WR(bp, BAR_XSTRORM_INTMEM + | |
2393 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, | |
2394 | ((u32 *)(&m_fair_vn))[i]); | |
2395 | } | |
f85582f8 | 2396 | |
523224a3 DK |
2397 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2398 | { | |
2399 | if (CHIP_REV_IS_SLOW(bp)) | |
2400 | return CMNG_FNS_NONE; | |
fb3bff17 | 2401 | if (IS_MF(bp)) |
523224a3 DK |
2402 | return CMNG_FNS_MINMAX; |
2403 | ||
2404 | return CMNG_FNS_NONE; | |
2405 | } | |
2406 | ||
2ae17f66 | 2407 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2408 | { |
0793f83f | 2409 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2410 | |
2411 | if (BP_NOMCP(bp)) | |
2412 | return; /* what should be the default bvalue in this case */ | |
2413 | ||
0793f83f DK |
2414 | /* For 2 port configuration the absolute function number formula |
2415 | * is: | |
2416 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2417 | * | |
2418 | * and there are 4 functions per port | |
2419 | * | |
2420 | * For 4 port configuration it is | |
2421 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2422 | * | |
2423 | * and there are 2 functions per port | |
2424 | */ | |
523224a3 | 2425 | for (vn = VN_0; vn < E1HVN_MAX; vn++) { |
0793f83f DK |
2426 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2427 | ||
2428 | if (func >= E1H_FUNC_MAX) | |
2429 | break; | |
2430 | ||
f2e0899f | 2431 | bp->mf_config[vn] = |
523224a3 DK |
2432 | MF_CFG_RD(bp, func_mf_config[func].config); |
2433 | } | |
2434 | } | |
2435 | ||
2436 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2437 | { | |
2438 | ||
2439 | if (cmng_type == CMNG_FNS_MINMAX) { | |
2440 | int vn; | |
2441 | ||
2442 | /* clear cmng_enables */ | |
2443 | bp->cmng.flags.cmng_enables = 0; | |
2444 | ||
2445 | /* read mf conf from shmem */ | |
2446 | if (read_cfg) | |
2447 | bnx2x_read_mf_cfg(bp); | |
2448 | ||
2449 | /* Init rate shaping and fairness contexts */ | |
2450 | bnx2x_init_port_minmax(bp); | |
2451 | ||
2452 | /* vn_weight_sum and enable fairness if not 0 */ | |
2453 | bnx2x_calc_vn_weight_sum(bp); | |
2454 | ||
2455 | /* calculate and set min-max rate for each vn */ | |
c4154f25 DK |
2456 | if (bp->port.pmf) |
2457 | for (vn = VN_0; vn < E1HVN_MAX; vn++) | |
2458 | bnx2x_init_vn_minmax(bp, vn); | |
523224a3 DK |
2459 | |
2460 | /* always enable rate shaping and fairness */ | |
2461 | bp->cmng.flags.cmng_enables |= | |
2462 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; | |
2463 | if (!bp->vn_weight_sum) | |
2464 | DP(NETIF_MSG_IFUP, "All MIN values are zeroes" | |
2465 | " fairness will be disabled\n"); | |
2466 | return; | |
2467 | } | |
2468 | ||
2469 | /* rate shaping and fairness are disabled */ | |
2470 | DP(NETIF_MSG_IFUP, | |
2471 | "rate shaping and fairness are disabled\n"); | |
2472 | } | |
34f80b04 | 2473 | |
523224a3 DK |
2474 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) |
2475 | { | |
2476 | int port = BP_PORT(bp); | |
2477 | int func; | |
2478 | int vn; | |
2479 | ||
2480 | /* Set the attention towards other drivers on the same port */ | |
2481 | for (vn = VN_0; vn < E1HVN_MAX; vn++) { | |
2482 | if (vn == BP_E1HVN(bp)) | |
2483 | continue; | |
2484 | ||
2485 | func = ((vn << 1) | port); | |
2486 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + | |
2487 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); | |
2488 | } | |
2489 | } | |
8a1c38d1 | 2490 | |
c18487ee YR |
2491 | /* This function is called upon link interrupt */ |
2492 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2493 | { | |
bb2a0f7a YG |
2494 | /* Make sure that we are synced with the current statistics */ |
2495 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2496 | ||
c18487ee | 2497 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2498 | |
bb2a0f7a YG |
2499 | if (bp->link_vars.link_up) { |
2500 | ||
1c06328c | 2501 | /* dropless flow control */ |
f2e0899f | 2502 | if (!CHIP_IS_E1(bp) && bp->dropless_fc) { |
1c06328c EG |
2503 | int port = BP_PORT(bp); |
2504 | u32 pause_enabled = 0; | |
2505 | ||
2506 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2507 | pause_enabled = 1; | |
2508 | ||
2509 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
ca00392c | 2510 | USTORM_ETH_PAUSE_ENABLED_OFFSET(port), |
1c06328c EG |
2511 | pause_enabled); |
2512 | } | |
2513 | ||
619c5cb6 | 2514 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2515 | struct host_port_stats *pstats; |
2516 | ||
2517 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2518 | /* reset old mac stats */ |
bb2a0f7a YG |
2519 | memset(&(pstats->mac_stx[0]), 0, |
2520 | sizeof(struct mac_stx)); | |
2521 | } | |
f34d28ea | 2522 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2523 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2524 | } | |
2525 | ||
f2e0899f DK |
2526 | if (bp->link_vars.link_up && bp->link_vars.line_speed) { |
2527 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
8a1c38d1 | 2528 | |
f2e0899f DK |
2529 | if (cmng_fns != CMNG_FNS_NONE) { |
2530 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2531 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2532 | } else | |
2533 | /* rate shaping and fairness are disabled */ | |
2534 | DP(NETIF_MSG_IFUP, | |
2535 | "single function mode without fairness\n"); | |
34f80b04 | 2536 | } |
9fdc3e95 | 2537 | |
2ae17f66 VZ |
2538 | __bnx2x_link_report(bp); |
2539 | ||
9fdc3e95 DK |
2540 | if (IS_MF(bp)) |
2541 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2542 | } |
a2fbb9ea | 2543 | |
9f6c9258 | 2544 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2545 | { |
2ae17f66 | 2546 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2547 | return; |
a2fbb9ea | 2548 | |
c18487ee | 2549 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2550 | |
bb2a0f7a YG |
2551 | if (bp->link_vars.link_up) |
2552 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2553 | else | |
2554 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2555 | ||
c18487ee YR |
2556 | /* indicate link status */ |
2557 | bnx2x_link_report(bp); | |
a2fbb9ea | 2558 | } |
a2fbb9ea | 2559 | |
34f80b04 EG |
2560 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2561 | { | |
2562 | int port = BP_PORT(bp); | |
2563 | u32 val; | |
2564 | ||
2565 | bp->port.pmf = 1; | |
2566 | DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); | |
2567 | ||
3deb8167 YR |
2568 | /* |
2569 | * We need the mb() to ensure the ordering between the writing to | |
2570 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2571 | */ | |
2572 | smp_mb(); | |
2573 | ||
2574 | /* queue a periodic task */ | |
2575 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2576 | ||
ef01854e DK |
2577 | bnx2x_dcbx_pmf_update(bp); |
2578 | ||
34f80b04 EG |
2579 | /* enable nig attention */ |
2580 | val = (0xff0f | (1 << (BP_E1HVN(bp) + 4))); | |
f2e0899f DK |
2581 | if (bp->common.int_block == INT_BLOCK_HC) { |
2582 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2583 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2584 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2585 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2586 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2587 | } | |
bb2a0f7a YG |
2588 | |
2589 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2590 | } |
2591 | ||
c18487ee | 2592 | /* end of Link */ |
a2fbb9ea ET |
2593 | |
2594 | /* slow path */ | |
2595 | ||
2596 | /* | |
2597 | * General service functions | |
2598 | */ | |
2599 | ||
2691d51d | 2600 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 2601 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 2602 | { |
f2e0899f | 2603 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 2604 | u32 seq; |
2691d51d EG |
2605 | u32 rc = 0; |
2606 | u32 cnt = 1; | |
2607 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
2608 | ||
c4ff7cbf | 2609 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 2610 | seq = ++bp->fw_seq; |
f2e0899f DK |
2611 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
2612 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
2613 | ||
754a2f52 DK |
2614 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
2615 | (command | seq), param); | |
2691d51d EG |
2616 | |
2617 | do { | |
2618 | /* let the FW do it's magic ... */ | |
2619 | msleep(delay); | |
2620 | ||
f2e0899f | 2621 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 2622 | |
c4ff7cbf EG |
2623 | /* Give the FW up to 5 second (500*10ms) */ |
2624 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
2625 | |
2626 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
2627 | cnt*delay, rc, seq); | |
2628 | ||
2629 | /* is this a reply to our command? */ | |
2630 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
2631 | rc &= FW_MSG_CODE_MASK; | |
2632 | else { | |
2633 | /* FW BUG! */ | |
2634 | BNX2X_ERR("FW failed to respond!\n"); | |
2635 | bnx2x_fw_dump(bp); | |
2636 | rc = 0; | |
2637 | } | |
c4ff7cbf | 2638 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
2639 | |
2640 | return rc; | |
2641 | } | |
2642 | ||
ec6ba945 VZ |
2643 | static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp) |
2644 | { | |
2645 | #ifdef BCM_CNIC | |
619c5cb6 VZ |
2646 | /* Statistics are not supported for CNIC Clients at the moment */ |
2647 | if (IS_FCOE_FP(fp)) | |
ec6ba945 VZ |
2648 | return false; |
2649 | #endif | |
2650 | return true; | |
2651 | } | |
2652 | ||
619c5cb6 VZ |
2653 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
2654 | { | |
2655 | if (CHIP_IS_E1x(bp)) { | |
2656 | struct tstorm_eth_function_common_config tcfg = {0}; | |
2657 | ||
2658 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
2659 | } | |
2660 | ||
2661 | /* Enable the function in the FW */ | |
2662 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
2663 | storm_memset_func_en(bp, p->func_id, 1); | |
2664 | ||
2665 | /* spq */ | |
2666 | if (p->func_flgs & FUNC_FLG_SPQ) { | |
2667 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); | |
2668 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
2669 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
2670 | } | |
2671 | } | |
2672 | ||
6383c0b3 AE |
2673 | /** |
2674 | * bnx2x_get_tx_only_flags - Return common flags | |
2675 | * | |
2676 | * @bp device handle | |
2677 | * @fp queue handle | |
2678 | * @zero_stats TRUE if statistics zeroing is needed | |
2679 | * | |
2680 | * Return the flags that are common for the Tx-only and not normal connections. | |
2681 | */ | |
2682 | static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, | |
2683 | struct bnx2x_fastpath *fp, | |
2684 | bool zero_stats) | |
28912902 | 2685 | { |
619c5cb6 VZ |
2686 | unsigned long flags = 0; |
2687 | ||
2688 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
2689 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 2690 | |
6383c0b3 AE |
2691 | /* tx only connections collect statistics (on the same index as the |
2692 | * parent connection). The statistics are zeroed when the parent | |
2693 | * connection is initialized. | |
2694 | */ | |
2695 | if (stat_counter_valid(bp, fp)) { | |
2696 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
2697 | if (zero_stats) | |
2698 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
2699 | } | |
2700 | ||
2701 | return flags; | |
2702 | } | |
2703 | ||
2704 | static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, | |
2705 | struct bnx2x_fastpath *fp, | |
2706 | bool leading) | |
2707 | { | |
2708 | unsigned long flags = 0; | |
2709 | ||
619c5cb6 VZ |
2710 | /* calculate other queue flags */ |
2711 | if (IS_MF_SD(bp)) | |
2712 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 2713 | |
619c5cb6 VZ |
2714 | if (IS_FCOE_FP(fp)) |
2715 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); | |
523224a3 | 2716 | |
f5219d8e | 2717 | if (!fp->disable_tpa) { |
619c5cb6 | 2718 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e VZ |
2719 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
2720 | } | |
619c5cb6 | 2721 | |
619c5cb6 VZ |
2722 | if (leading) { |
2723 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
2724 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
2725 | } | |
523224a3 | 2726 | |
619c5cb6 VZ |
2727 | /* Always set HW VLAN stripping */ |
2728 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 2729 | |
6383c0b3 AE |
2730 | |
2731 | return flags | bnx2x_get_common_flags(bp, fp, true); | |
523224a3 DK |
2732 | } |
2733 | ||
619c5cb6 | 2734 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
2735 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
2736 | u8 cos) | |
619c5cb6 VZ |
2737 | { |
2738 | gen_init->stat_id = bnx2x_stats_id(fp); | |
2739 | gen_init->spcl_id = fp->cl_id; | |
2740 | ||
2741 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
2742 | if (IS_FCOE_FP(fp)) | |
2743 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
2744 | else | |
2745 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
2746 | |
2747 | gen_init->cos = cos; | |
619c5cb6 VZ |
2748 | } |
2749 | ||
2750 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 2751 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 2752 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 2753 | { |
619c5cb6 | 2754 | u8 max_sge = 0; |
523224a3 DK |
2755 | u16 sge_sz = 0; |
2756 | u16 tpa_agg_size = 0; | |
2757 | ||
523224a3 DK |
2758 | if (!fp->disable_tpa) { |
2759 | pause->sge_th_hi = 250; | |
2760 | pause->sge_th_lo = 150; | |
2761 | tpa_agg_size = min_t(u32, | |
2762 | (min_t(u32, 8, MAX_SKB_FRAGS) * | |
2763 | SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); | |
2764 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> | |
2765 | SGE_PAGE_SHIFT; | |
2766 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
2767 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
2768 | sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, | |
2769 | 0xffff); | |
2770 | } | |
2771 | ||
2772 | /* pause - not for e1 */ | |
2773 | if (!CHIP_IS_E1(bp)) { | |
2774 | pause->bd_th_hi = 350; | |
2775 | pause->bd_th_lo = 250; | |
2776 | pause->rcq_th_hi = 350; | |
2777 | pause->rcq_th_lo = 250; | |
619c5cb6 | 2778 | |
523224a3 DK |
2779 | pause->pri_map = 1; |
2780 | } | |
2781 | ||
2782 | /* rxq setup */ | |
523224a3 DK |
2783 | rxq_init->dscr_map = fp->rx_desc_mapping; |
2784 | rxq_init->sge_map = fp->rx_sge_mapping; | |
2785 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
2786 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 2787 | |
619c5cb6 VZ |
2788 | /* This should be a maximum number of data bytes that may be |
2789 | * placed on the BD (not including paddings). | |
2790 | */ | |
2791 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN - | |
2792 | IP_HEADER_ALIGNMENT_PADDING; | |
a8c94b91 | 2793 | |
523224a3 | 2794 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
2795 | rxq_init->tpa_agg_sz = tpa_agg_size; |
2796 | rxq_init->sge_buf_sz = sge_sz; | |
2797 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 VZ |
2798 | rxq_init->rss_engine_id = BP_FUNC(bp); |
2799 | ||
2800 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
2801 | * | |
2802 | * For PF Clients it should be the maximum avaliable number. | |
2803 | * VF driver(s) may want to define it to a smaller value. | |
2804 | */ | |
2805 | rxq_init->max_tpa_queues = | |
2806 | (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 : | |
2807 | ETH_MAX_AGGREGATION_QUEUES_E1H_E2); | |
2808 | ||
523224a3 DK |
2809 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
2810 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
2811 | ||
ec6ba945 VZ |
2812 | if (IS_FCOE_FP(fp)) |
2813 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
2814 | else | |
6383c0b3 | 2815 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
523224a3 DK |
2816 | } |
2817 | ||
619c5cb6 | 2818 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
2819 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
2820 | u8 cos) | |
523224a3 | 2821 | { |
6383c0b3 AE |
2822 | txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; |
2823 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; | |
523224a3 DK |
2824 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
2825 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 2826 | |
619c5cb6 VZ |
2827 | /* |
2828 | * set the tss leading client id for TX classfication == | |
2829 | * leading RSS client id | |
2830 | */ | |
2831 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
2832 | ||
ec6ba945 VZ |
2833 | if (IS_FCOE_FP(fp)) { |
2834 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
2835 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
2836 | } | |
523224a3 DK |
2837 | } |
2838 | ||
8d96286a | 2839 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
2840 | { |
2841 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 DK |
2842 | struct event_ring_data eq_data = { {0} }; |
2843 | u16 flags; | |
2844 | ||
619c5cb6 | 2845 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2846 | /* reset IGU PF statistics: MSIX + ATTN */ |
2847 | /* PF */ | |
2848 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2849 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2850 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2851 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2852 | /* ATTN */ | |
2853 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2854 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2855 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
2856 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2857 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2858 | } | |
2859 | ||
523224a3 DK |
2860 | /* function setup flags */ |
2861 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | |
2862 | ||
619c5cb6 VZ |
2863 | /* This flag is relevant for E1x only. |
2864 | * E2 doesn't have a TPA configuration in a function level. | |
523224a3 | 2865 | */ |
619c5cb6 | 2866 | flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; |
523224a3 DK |
2867 | |
2868 | func_init.func_flgs = flags; | |
2869 | func_init.pf_id = BP_FUNC(bp); | |
2870 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
2871 | func_init.spq_map = bp->spq_mapping; |
2872 | func_init.spq_prod = bp->spq_prod_idx; | |
2873 | ||
2874 | bnx2x_func_init(bp, &func_init); | |
2875 | ||
2876 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
2877 | ||
2878 | /* | |
619c5cb6 VZ |
2879 | * Congestion management values depend on the link rate |
2880 | * There is no active link so initial link rate is set to 10 Gbps. | |
2881 | * When the link comes up The congestion management values are | |
2882 | * re-calculated according to the actual link rate. | |
2883 | */ | |
523224a3 DK |
2884 | bp->link_vars.line_speed = SPEED_10000; |
2885 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
2886 | ||
2887 | /* Only the PMF sets the HW */ | |
2888 | if (bp->port.pmf) | |
2889 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2890 | ||
523224a3 DK |
2891 | /* init Event Queue */ |
2892 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); | |
2893 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
2894 | eq_data.producer = bp->eq_prod; | |
2895 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
2896 | eq_data.sb_id = DEF_SB_ID; | |
2897 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
2898 | } | |
2899 | ||
2900 | ||
2901 | static void bnx2x_e1h_disable(struct bnx2x *bp) | |
2902 | { | |
2903 | int port = BP_PORT(bp); | |
2904 | ||
619c5cb6 | 2905 | bnx2x_tx_disable(bp); |
523224a3 DK |
2906 | |
2907 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
2908 | } |
2909 | ||
2910 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
2911 | { | |
2912 | int port = BP_PORT(bp); | |
2913 | ||
2914 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); | |
2915 | ||
2916 | /* Tx queue should be only reenabled */ | |
2917 | netif_tx_wake_all_queues(bp->dev); | |
2918 | ||
2919 | /* | |
2920 | * Should not call netif_carrier_on since it will be called if the link | |
2921 | * is up when checking for link state | |
2922 | */ | |
2923 | } | |
2924 | ||
0793f83f DK |
2925 | /* called due to MCP event (on pmf): |
2926 | * reread new bandwidth configuration | |
2927 | * configure FW | |
2928 | * notify others function about the change | |
2929 | */ | |
2930 | static inline void bnx2x_config_mf_bw(struct bnx2x *bp) | |
2931 | { | |
2932 | if (bp->link_vars.link_up) { | |
2933 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
2934 | bnx2x_link_sync_notify(bp); | |
2935 | } | |
2936 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2937 | } | |
2938 | ||
2939 | static inline void bnx2x_set_mf_bw(struct bnx2x *bp) | |
2940 | { | |
2941 | bnx2x_config_mf_bw(bp); | |
2942 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
2943 | } | |
2944 | ||
523224a3 DK |
2945 | static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) |
2946 | { | |
2947 | DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); | |
2948 | ||
2949 | if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { | |
2950 | ||
2951 | /* | |
2952 | * This is the only place besides the function initialization | |
2953 | * where the bp->flags can change so it is done without any | |
2954 | * locks | |
2955 | */ | |
f2e0899f | 2956 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
523224a3 DK |
2957 | DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); |
2958 | bp->flags |= MF_FUNC_DIS; | |
2959 | ||
2960 | bnx2x_e1h_disable(bp); | |
2961 | } else { | |
2962 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2963 | bp->flags &= ~MF_FUNC_DIS; | |
2964 | ||
2965 | bnx2x_e1h_enable(bp); | |
2966 | } | |
2967 | dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; | |
2968 | } | |
2969 | if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { | |
0793f83f | 2970 | bnx2x_config_mf_bw(bp); |
523224a3 DK |
2971 | dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; |
2972 | } | |
2973 | ||
2974 | /* Report results to MCP */ | |
2975 | if (dcc_event) | |
2976 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); | |
2977 | else | |
2978 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); | |
2979 | } | |
2980 | ||
2981 | /* must be called under the spq lock */ | |
2982 | static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) | |
2983 | { | |
2984 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
2985 | ||
2986 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
2987 | bp->spq_prod_bd = bp->spq; | |
2988 | bp->spq_prod_idx = 0; | |
2989 | DP(NETIF_MSG_TIMER, "end of spq\n"); | |
2990 | } else { | |
2991 | bp->spq_prod_bd++; | |
2992 | bp->spq_prod_idx++; | |
2993 | } | |
2994 | return next_spe; | |
2995 | } | |
2996 | ||
2997 | /* must be called under the spq lock */ | |
28912902 MC |
2998 | static inline void bnx2x_sp_prod_update(struct bnx2x *bp) |
2999 | { | |
3000 | int func = BP_FUNC(bp); | |
3001 | ||
53e51e2f VZ |
3002 | /* |
3003 | * Make sure that BD data is updated before writing the producer: | |
3004 | * BD data is written to the memory, the producer is read from the | |
3005 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3006 | */ | |
3007 | mb(); | |
28912902 | 3008 | |
523224a3 | 3009 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3010 | bp->spq_prod_idx); |
28912902 MC |
3011 | mmiowb(); |
3012 | } | |
3013 | ||
619c5cb6 VZ |
3014 | /** |
3015 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3016 | * | |
3017 | * @cmd: command to check | |
3018 | * @cmd_type: command type | |
3019 | */ | |
3020 | static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) | |
3021 | { | |
3022 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3023 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3024 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3025 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3026 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3027 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3028 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3029 | return true; | |
3030 | else | |
3031 | return false; | |
3032 | ||
3033 | } | |
3034 | ||
3035 | ||
3036 | /** | |
3037 | * bnx2x_sp_post - place a single command on an SP ring | |
3038 | * | |
3039 | * @bp: driver handle | |
3040 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3041 | * @cid: SW CID the command is related to | |
3042 | * @data_hi: command private data address (high 32 bits) | |
3043 | * @data_lo: command private data address (low 32 bits) | |
3044 | * @cmd_type: command type (e.g. NONE, ETH) | |
3045 | * | |
3046 | * SP data is handled as if it's always an address pair, thus data fields are | |
3047 | * not swapped to little endian in upper functions. Instead this function swaps | |
3048 | * data as if it's two u32 fields. | |
3049 | */ | |
9f6c9258 | 3050 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3051 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3052 | { |
28912902 | 3053 | struct eth_spe *spe; |
523224a3 | 3054 | u16 type; |
619c5cb6 | 3055 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3056 | |
a2fbb9ea ET |
3057 | #ifdef BNX2X_STOP_ON_ERROR |
3058 | if (unlikely(bp->panic)) | |
3059 | return -EIO; | |
3060 | #endif | |
3061 | ||
34f80b04 | 3062 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3063 | |
6e30dd4e VZ |
3064 | if (common) { |
3065 | if (!atomic_read(&bp->eq_spq_left)) { | |
3066 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3067 | spin_unlock_bh(&bp->spq_lock); | |
3068 | bnx2x_panic(); | |
3069 | return -EBUSY; | |
3070 | } | |
3071 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3072 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3073 | spin_unlock_bh(&bp->spq_lock); | |
3074 | bnx2x_panic(); | |
3075 | return -EBUSY; | |
a2fbb9ea | 3076 | } |
f1410647 | 3077 | |
28912902 MC |
3078 | spe = bnx2x_sp_get_next(bp); |
3079 | ||
a2fbb9ea | 3080 | /* CID needs port number to be encoded int it */ |
28912902 | 3081 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3082 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3083 | HW_CID(bp, cid)); | |
523224a3 | 3084 | |
619c5cb6 | 3085 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; |
a2fbb9ea | 3086 | |
523224a3 DK |
3087 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & |
3088 | SPE_HDR_FUNCTION_ID); | |
a2fbb9ea | 3089 | |
523224a3 DK |
3090 | spe->hdr.type = cpu_to_le16(type); |
3091 | ||
3092 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3093 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3094 | ||
d6cae238 VZ |
3095 | /* |
3096 | * It's ok if the actual decrement is issued towards the memory | |
3097 | * somewhere between the spin_lock and spin_unlock. Thus no | |
3098 | * more explict memory barrier is needed. | |
3099 | */ | |
3100 | if (common) | |
3101 | atomic_dec(&bp->eq_spq_left); | |
3102 | else | |
3103 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3104 | |
a2fbb9ea | 3105 | |
cdaa7cb8 | 3106 | DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, |
d6cae238 VZ |
3107 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " |
3108 | "type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3109 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3110 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3111 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3112 | HW_CID(bp, cid), data_hi, data_lo, type, |
3113 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3114 | |
28912902 | 3115 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3116 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3117 | return 0; |
3118 | } | |
3119 | ||
3120 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3121 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3122 | { |
72fd0718 | 3123 | u32 j, val; |
34f80b04 | 3124 | int rc = 0; |
a2fbb9ea ET |
3125 | |
3126 | might_sleep(); | |
72fd0718 | 3127 | for (j = 0; j < 1000; j++) { |
a2fbb9ea ET |
3128 | val = (1UL << 31); |
3129 | REG_WR(bp, GRCBASE_MCP + 0x9c, val); | |
3130 | val = REG_RD(bp, GRCBASE_MCP + 0x9c); | |
3131 | if (val & (1L << 31)) | |
3132 | break; | |
3133 | ||
3134 | msleep(5); | |
3135 | } | |
a2fbb9ea | 3136 | if (!(val & (1L << 31))) { |
19680c48 | 3137 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3138 | rc = -EBUSY; |
3139 | } | |
3140 | ||
3141 | return rc; | |
3142 | } | |
3143 | ||
4a37fb66 YG |
3144 | /* release split MCP access lock register */ |
3145 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3146 | { |
72fd0718 | 3147 | REG_WR(bp, GRCBASE_MCP + 0x9c, 0); |
a2fbb9ea ET |
3148 | } |
3149 | ||
523224a3 DK |
3150 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3151 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3152 | ||
a2fbb9ea ET |
3153 | static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
3154 | { | |
523224a3 | 3155 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3156 | u16 rc = 0; |
3157 | ||
3158 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3159 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3160 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3161 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3162 | } |
523224a3 DK |
3163 | |
3164 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3165 | bp->def_idx = def_sb->sp_sb.running_index; | |
3166 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3167 | } |
523224a3 DK |
3168 | |
3169 | /* Do not reorder: indecies reading should complete before handling */ | |
3170 | barrier(); | |
a2fbb9ea ET |
3171 | return rc; |
3172 | } | |
3173 | ||
3174 | /* | |
3175 | * slow path service functions | |
3176 | */ | |
3177 | ||
3178 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3179 | { | |
34f80b04 | 3180 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3181 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3182 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3183 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3184 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3185 | u32 aeu_mask; |
87942b46 | 3186 | u32 nig_mask = 0; |
f2e0899f | 3187 | u32 reg_addr; |
a2fbb9ea | 3188 | |
a2fbb9ea ET |
3189 | if (bp->attn_state & asserted) |
3190 | BNX2X_ERR("IGU ERROR\n"); | |
3191 | ||
3fcaf2e5 EG |
3192 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
3193 | aeu_mask = REG_RD(bp, aeu_addr); | |
3194 | ||
a2fbb9ea | 3195 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 3196 | aeu_mask, asserted); |
72fd0718 | 3197 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 3198 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 3199 | |
3fcaf2e5 EG |
3200 | REG_WR(bp, aeu_addr, aeu_mask); |
3201 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 3202 | |
3fcaf2e5 | 3203 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 3204 | bp->attn_state |= asserted; |
3fcaf2e5 | 3205 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
3206 | |
3207 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
3208 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 3209 | |
a5e9a7cf EG |
3210 | bnx2x_acquire_phy_lock(bp); |
3211 | ||
877e9aa4 | 3212 | /* save nig interrupt mask */ |
87942b46 | 3213 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 3214 | |
361c391e YR |
3215 | /* If nig_mask is not set, no need to call the update |
3216 | * function. | |
3217 | */ | |
3218 | if (nig_mask) { | |
3219 | REG_WR(bp, nig_int_mask_addr, 0); | |
3220 | ||
3221 | bnx2x_link_attn(bp); | |
3222 | } | |
a2fbb9ea ET |
3223 | |
3224 | /* handle unicore attn? */ | |
3225 | } | |
3226 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
3227 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
3228 | ||
3229 | if (asserted & GPIO_2_FUNC) | |
3230 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
3231 | ||
3232 | if (asserted & GPIO_3_FUNC) | |
3233 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
3234 | ||
3235 | if (asserted & GPIO_4_FUNC) | |
3236 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
3237 | ||
3238 | if (port == 0) { | |
3239 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
3240 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
3241 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
3242 | } | |
3243 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
3244 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
3245 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
3246 | } | |
3247 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
3248 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
3249 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
3250 | } | |
3251 | } else { | |
3252 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
3253 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
3254 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
3255 | } | |
3256 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
3257 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
3258 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
3259 | } | |
3260 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
3261 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
3262 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
3263 | } | |
3264 | } | |
3265 | ||
3266 | } /* if hardwired */ | |
3267 | ||
f2e0899f DK |
3268 | if (bp->common.int_block == INT_BLOCK_HC) |
3269 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
3270 | COMMAND_REG_ATTN_BITS_SET); | |
3271 | else | |
3272 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
3273 | ||
3274 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
3275 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
3276 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
3277 | |
3278 | /* now set back the mask */ | |
a5e9a7cf | 3279 | if (asserted & ATTN_NIG_FOR_FUNC) { |
87942b46 | 3280 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
3281 | bnx2x_release_phy_lock(bp); |
3282 | } | |
a2fbb9ea ET |
3283 | } |
3284 | ||
fd4ef40d EG |
3285 | static inline void bnx2x_fan_failure(struct bnx2x *bp) |
3286 | { | |
3287 | int port = BP_PORT(bp); | |
b7737c9b | 3288 | u32 ext_phy_config; |
fd4ef40d | 3289 | /* mark the failure */ |
b7737c9b YR |
3290 | ext_phy_config = |
3291 | SHMEM_RD(bp, | |
3292 | dev_info.port_hw_config[port].external_phy_config); | |
3293 | ||
3294 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
3295 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 3296 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 3297 | ext_phy_config); |
fd4ef40d EG |
3298 | |
3299 | /* log the failure */ | |
cdaa7cb8 VZ |
3300 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused" |
3301 | " the driver to shutdown the card to prevent permanent" | |
3302 | " damage. Please contact OEM Support for assistance\n"); | |
fd4ef40d | 3303 | } |
ab6ad5a4 | 3304 | |
877e9aa4 | 3305 | static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 3306 | { |
34f80b04 | 3307 | int port = BP_PORT(bp); |
877e9aa4 | 3308 | int reg_offset; |
d90d96ba | 3309 | u32 val; |
877e9aa4 | 3310 | |
34f80b04 EG |
3311 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
3312 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 3313 | |
34f80b04 | 3314 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
3315 | |
3316 | val = REG_RD(bp, reg_offset); | |
3317 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
3318 | REG_WR(bp, reg_offset, val); | |
3319 | ||
3320 | BNX2X_ERR("SPIO5 hw attention\n"); | |
3321 | ||
fd4ef40d | 3322 | /* Fan failure attention */ |
d90d96ba | 3323 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 3324 | bnx2x_fan_failure(bp); |
877e9aa4 | 3325 | } |
34f80b04 | 3326 | |
3deb8167 | 3327 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
3328 | bnx2x_acquire_phy_lock(bp); |
3329 | bnx2x_handle_module_detect_int(&bp->link_params); | |
3330 | bnx2x_release_phy_lock(bp); | |
3331 | } | |
3332 | ||
34f80b04 EG |
3333 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
3334 | ||
3335 | val = REG_RD(bp, reg_offset); | |
3336 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
3337 | REG_WR(bp, reg_offset, val); | |
3338 | ||
3339 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 3340 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
3341 | bnx2x_panic(); |
3342 | } | |
877e9aa4 ET |
3343 | } |
3344 | ||
3345 | static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) | |
3346 | { | |
3347 | u32 val; | |
3348 | ||
0626b899 | 3349 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
3350 | |
3351 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
3352 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
3353 | /* DORQ discard attention */ | |
3354 | if (val & 0x2) | |
3355 | BNX2X_ERR("FATAL error from DORQ\n"); | |
3356 | } | |
34f80b04 EG |
3357 | |
3358 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
3359 | ||
3360 | int port = BP_PORT(bp); | |
3361 | int reg_offset; | |
3362 | ||
3363 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
3364 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
3365 | ||
3366 | val = REG_RD(bp, reg_offset); | |
3367 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
3368 | REG_WR(bp, reg_offset, val); | |
3369 | ||
3370 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 3371 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
3372 | bnx2x_panic(); |
3373 | } | |
877e9aa4 ET |
3374 | } |
3375 | ||
3376 | static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) | |
3377 | { | |
3378 | u32 val; | |
3379 | ||
3380 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
3381 | ||
3382 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
3383 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
3384 | /* CFC error attention */ | |
3385 | if (val & 0x2) | |
3386 | BNX2X_ERR("FATAL error from CFC\n"); | |
3387 | } | |
3388 | ||
3389 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 3390 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 3391 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
3392 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
3393 | if (val & 0x18000) | |
3394 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
3395 | |
3396 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
3397 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
3398 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
3399 | } | |
877e9aa4 | 3400 | } |
34f80b04 EG |
3401 | |
3402 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
3403 | ||
3404 | int port = BP_PORT(bp); | |
3405 | int reg_offset; | |
3406 | ||
3407 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
3408 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
3409 | ||
3410 | val = REG_RD(bp, reg_offset); | |
3411 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
3412 | REG_WR(bp, reg_offset, val); | |
3413 | ||
3414 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 3415 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
3416 | bnx2x_panic(); |
3417 | } | |
877e9aa4 ET |
3418 | } |
3419 | ||
3420 | static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) | |
3421 | { | |
34f80b04 EG |
3422 | u32 val; |
3423 | ||
877e9aa4 ET |
3424 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
3425 | ||
34f80b04 EG |
3426 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
3427 | int func = BP_FUNC(bp); | |
3428 | ||
3429 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
f2e0899f DK |
3430 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
3431 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
3432 | val = SHMEM_RD(bp, | |
3433 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
2691d51d EG |
3434 | if (val & DRV_STATUS_DCC_EVENT_MASK) |
3435 | bnx2x_dcc_event(bp, | |
3436 | (val & DRV_STATUS_DCC_EVENT_MASK)); | |
0793f83f DK |
3437 | |
3438 | if (val & DRV_STATUS_SET_MF_BW) | |
3439 | bnx2x_set_mf_bw(bp); | |
3440 | ||
2691d51d | 3441 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
3442 | bnx2x_pmf_update(bp); |
3443 | ||
e4901dde | 3444 | if (bp->port.pmf && |
785b9b1a SR |
3445 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
3446 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
3447 | /* start dcbx state machine */ |
3448 | bnx2x_dcbx_set_params(bp, | |
3449 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
3deb8167 YR |
3450 | if (bp->link_vars.periodic_flags & |
3451 | PERIODIC_FLAGS_LINK_EVENT) { | |
3452 | /* sync with link */ | |
3453 | bnx2x_acquire_phy_lock(bp); | |
3454 | bp->link_vars.periodic_flags &= | |
3455 | ~PERIODIC_FLAGS_LINK_EVENT; | |
3456 | bnx2x_release_phy_lock(bp); | |
3457 | if (IS_MF(bp)) | |
3458 | bnx2x_link_sync_notify(bp); | |
3459 | bnx2x_link_report(bp); | |
3460 | } | |
3461 | /* Always call it here: bnx2x_link_report() will | |
3462 | * prevent the link indication duplication. | |
3463 | */ | |
3464 | bnx2x__link_status_update(bp); | |
34f80b04 | 3465 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
3466 | |
3467 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 3468 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
3469 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
3470 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
3471 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
3472 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
3473 | bnx2x_panic(); | |
3474 | ||
3475 | } else if (attn & BNX2X_MCP_ASSERT) { | |
3476 | ||
3477 | BNX2X_ERR("MCP assert!\n"); | |
3478 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 3479 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
3480 | |
3481 | } else | |
3482 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
3483 | } | |
3484 | ||
3485 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
3486 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
3487 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
3488 | val = CHIP_IS_E1(bp) ? 0 : |
3489 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
3490 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
3491 | } | |
3492 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
3493 | val = CHIP_IS_E1(bp) ? 0 : |
3494 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
3495 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
3496 | } | |
877e9aa4 | 3497 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
3498 | } |
3499 | } | |
3500 | ||
c9ee9206 VZ |
3501 | /* |
3502 | * Bits map: | |
3503 | * 0-7 - Engine0 load counter. | |
3504 | * 8-15 - Engine1 load counter. | |
3505 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
3506 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
3507 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
3508 | * on the engine | |
3509 | * 19 - Engine1 ONE_IS_LOADED. | |
3510 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
3511 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
3512 | * just the one belonging to its engine). | |
3513 | * | |
3514 | */ | |
3515 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
3516 | ||
3517 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
3518 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
3519 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
3520 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
3521 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
3522 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
3523 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
3524 | ||
3525 | /* | |
3526 | * Set the GLOBAL_RESET bit. | |
3527 | * | |
3528 | * Should be run under rtnl lock | |
3529 | */ | |
3530 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
3531 | { | |
3532 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3533 | ||
3534 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); | |
3535 | barrier(); | |
3536 | mmiowb(); | |
3537 | } | |
3538 | ||
3539 | /* | |
3540 | * Clear the GLOBAL_RESET bit. | |
3541 | * | |
3542 | * Should be run under rtnl lock | |
3543 | */ | |
3544 | static inline void bnx2x_clear_reset_global(struct bnx2x *bp) | |
3545 | { | |
3546 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3547 | ||
3548 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); | |
3549 | barrier(); | |
3550 | mmiowb(); | |
3551 | } | |
f85582f8 | 3552 | |
72fd0718 | 3553 | /* |
c9ee9206 VZ |
3554 | * Checks the GLOBAL_RESET bit. |
3555 | * | |
72fd0718 VZ |
3556 | * should be run under rtnl lock |
3557 | */ | |
c9ee9206 VZ |
3558 | static inline bool bnx2x_reset_is_global(struct bnx2x *bp) |
3559 | { | |
3560 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3561 | ||
3562 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
3563 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
3564 | } | |
3565 | ||
3566 | /* | |
3567 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
3568 | * | |
3569 | * Should be run under rtnl lock | |
3570 | */ | |
72fd0718 VZ |
3571 | static inline void bnx2x_set_reset_done(struct bnx2x *bp) |
3572 | { | |
c9ee9206 VZ |
3573 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3574 | u32 bit = BP_PATH(bp) ? | |
3575 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3576 | ||
3577 | /* Clear the bit */ | |
3578 | val &= ~bit; | |
3579 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
72fd0718 VZ |
3580 | barrier(); |
3581 | mmiowb(); | |
3582 | } | |
3583 | ||
3584 | /* | |
c9ee9206 VZ |
3585 | * Set RESET_IN_PROGRESS for the current engine. |
3586 | * | |
72fd0718 VZ |
3587 | * should be run under rtnl lock |
3588 | */ | |
c9ee9206 | 3589 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 3590 | { |
c9ee9206 VZ |
3591 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3592 | u32 bit = BP_PATH(bp) ? | |
3593 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3594 | ||
3595 | /* Set the bit */ | |
3596 | val |= bit; | |
3597 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
72fd0718 VZ |
3598 | barrier(); |
3599 | mmiowb(); | |
3600 | } | |
3601 | ||
3602 | /* | |
c9ee9206 | 3603 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
3604 | * should be run under rtnl lock |
3605 | */ | |
c9ee9206 | 3606 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 3607 | { |
c9ee9206 VZ |
3608 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3609 | u32 bit = engine ? | |
3610 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3611 | ||
3612 | /* return false if bit is set */ | |
3613 | return (val & bit) ? false : true; | |
72fd0718 VZ |
3614 | } |
3615 | ||
3616 | /* | |
c9ee9206 VZ |
3617 | * Increment the load counter for the current engine. |
3618 | * | |
72fd0718 VZ |
3619 | * should be run under rtnl lock |
3620 | */ | |
c9ee9206 | 3621 | void bnx2x_inc_load_cnt(struct bnx2x *bp) |
72fd0718 | 3622 | { |
c9ee9206 VZ |
3623 | u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3624 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : | |
3625 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3626 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3627 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 VZ |
3628 | |
3629 | DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); | |
3630 | ||
c9ee9206 VZ |
3631 | /* get the current counter value */ |
3632 | val1 = (val & mask) >> shift; | |
3633 | ||
3634 | /* increment... */ | |
3635 | val1++; | |
3636 | ||
3637 | /* clear the old value */ | |
3638 | val &= ~mask; | |
3639 | ||
3640 | /* set the new one */ | |
3641 | val |= ((val1 << shift) & mask); | |
3642 | ||
3643 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
72fd0718 VZ |
3644 | barrier(); |
3645 | mmiowb(); | |
3646 | } | |
3647 | ||
c9ee9206 VZ |
3648 | /** |
3649 | * bnx2x_dec_load_cnt - decrement the load counter | |
3650 | * | |
3651 | * @bp: driver handle | |
3652 | * | |
3653 | * Should be run under rtnl lock. | |
3654 | * Decrements the load counter for the current engine. Returns | |
3655 | * the new counter value. | |
72fd0718 | 3656 | */ |
9f6c9258 | 3657 | u32 bnx2x_dec_load_cnt(struct bnx2x *bp) |
72fd0718 | 3658 | { |
c9ee9206 VZ |
3659 | u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3660 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : | |
3661 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3662 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3663 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 VZ |
3664 | |
3665 | DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); | |
3666 | ||
c9ee9206 VZ |
3667 | /* get the current counter value */ |
3668 | val1 = (val & mask) >> shift; | |
3669 | ||
3670 | /* decrement... */ | |
3671 | val1--; | |
3672 | ||
3673 | /* clear the old value */ | |
3674 | val &= ~mask; | |
3675 | ||
3676 | /* set the new one */ | |
3677 | val |= ((val1 << shift) & mask); | |
3678 | ||
3679 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
72fd0718 VZ |
3680 | barrier(); |
3681 | mmiowb(); | |
3682 | ||
3683 | return val1; | |
3684 | } | |
3685 | ||
3686 | /* | |
c9ee9206 VZ |
3687 | * Read the load counter for the current engine. |
3688 | * | |
72fd0718 VZ |
3689 | * should be run under rtnl lock |
3690 | */ | |
c9ee9206 | 3691 | static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine) |
72fd0718 | 3692 | { |
c9ee9206 VZ |
3693 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
3694 | BNX2X_PATH0_LOAD_CNT_MASK); | |
3695 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3696 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
3697 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3698 | ||
3699 | DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); | |
3700 | ||
3701 | val = (val & mask) >> shift; | |
3702 | ||
3703 | DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val); | |
3704 | ||
3705 | return val; | |
72fd0718 VZ |
3706 | } |
3707 | ||
c9ee9206 VZ |
3708 | /* |
3709 | * Reset the load counter for the current engine. | |
3710 | * | |
3711 | * should be run under rtnl lock | |
3712 | */ | |
72fd0718 VZ |
3713 | static inline void bnx2x_clear_load_cnt(struct bnx2x *bp) |
3714 | { | |
c9ee9206 VZ |
3715 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3716 | u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : | |
3717 | BNX2X_PATH0_LOAD_CNT_MASK); | |
3718 | ||
3719 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); | |
72fd0718 VZ |
3720 | } |
3721 | ||
3722 | static inline void _print_next_block(int idx, const char *blk) | |
3723 | { | |
3724 | if (idx) | |
3725 | pr_cont(", "); | |
3726 | pr_cont("%s", blk); | |
3727 | } | |
3728 | ||
c9ee9206 VZ |
3729 | static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, |
3730 | bool print) | |
72fd0718 VZ |
3731 | { |
3732 | int i = 0; | |
3733 | u32 cur_bit = 0; | |
3734 | for (i = 0; sig; i++) { | |
3735 | cur_bit = ((u32)0x1 << i); | |
3736 | if (sig & cur_bit) { | |
3737 | switch (cur_bit) { | |
3738 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
c9ee9206 VZ |
3739 | if (print) |
3740 | _print_next_block(par_num++, "BRB"); | |
72fd0718 VZ |
3741 | break; |
3742 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
c9ee9206 VZ |
3743 | if (print) |
3744 | _print_next_block(par_num++, "PARSER"); | |
72fd0718 VZ |
3745 | break; |
3746 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
c9ee9206 VZ |
3747 | if (print) |
3748 | _print_next_block(par_num++, "TSDM"); | |
72fd0718 VZ |
3749 | break; |
3750 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
c9ee9206 VZ |
3751 | if (print) |
3752 | _print_next_block(par_num++, | |
3753 | "SEARCHER"); | |
3754 | break; | |
3755 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
3756 | if (print) | |
3757 | _print_next_block(par_num++, "TCM"); | |
72fd0718 VZ |
3758 | break; |
3759 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3760 | if (print) |
3761 | _print_next_block(par_num++, "TSEMI"); | |
3762 | break; | |
3763 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
3764 | if (print) | |
3765 | _print_next_block(par_num++, "XPB"); | |
72fd0718 VZ |
3766 | break; |
3767 | } | |
3768 | ||
3769 | /* Clear the bit */ | |
3770 | sig &= ~cur_bit; | |
3771 | } | |
3772 | } | |
3773 | ||
3774 | return par_num; | |
3775 | } | |
3776 | ||
c9ee9206 VZ |
3777 | static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, |
3778 | bool *global, bool print) | |
72fd0718 VZ |
3779 | { |
3780 | int i = 0; | |
3781 | u32 cur_bit = 0; | |
3782 | for (i = 0; sig; i++) { | |
3783 | cur_bit = ((u32)0x1 << i); | |
3784 | if (sig & cur_bit) { | |
3785 | switch (cur_bit) { | |
c9ee9206 VZ |
3786 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
3787 | if (print) | |
3788 | _print_next_block(par_num++, "PBF"); | |
72fd0718 VZ |
3789 | break; |
3790 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
c9ee9206 VZ |
3791 | if (print) |
3792 | _print_next_block(par_num++, "QM"); | |
3793 | break; | |
3794 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
3795 | if (print) | |
3796 | _print_next_block(par_num++, "TM"); | |
72fd0718 VZ |
3797 | break; |
3798 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
c9ee9206 VZ |
3799 | if (print) |
3800 | _print_next_block(par_num++, "XSDM"); | |
3801 | break; | |
3802 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
3803 | if (print) | |
3804 | _print_next_block(par_num++, "XCM"); | |
72fd0718 VZ |
3805 | break; |
3806 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3807 | if (print) |
3808 | _print_next_block(par_num++, "XSEMI"); | |
72fd0718 VZ |
3809 | break; |
3810 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
c9ee9206 VZ |
3811 | if (print) |
3812 | _print_next_block(par_num++, | |
3813 | "DOORBELLQ"); | |
3814 | break; | |
3815 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
3816 | if (print) | |
3817 | _print_next_block(par_num++, "NIG"); | |
72fd0718 VZ |
3818 | break; |
3819 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 VZ |
3820 | if (print) |
3821 | _print_next_block(par_num++, | |
3822 | "VAUX PCI CORE"); | |
3823 | *global = true; | |
72fd0718 VZ |
3824 | break; |
3825 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
c9ee9206 VZ |
3826 | if (print) |
3827 | _print_next_block(par_num++, "DEBUG"); | |
72fd0718 VZ |
3828 | break; |
3829 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
c9ee9206 VZ |
3830 | if (print) |
3831 | _print_next_block(par_num++, "USDM"); | |
72fd0718 | 3832 | break; |
8736c826 VZ |
3833 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
3834 | if (print) | |
3835 | _print_next_block(par_num++, "UCM"); | |
3836 | break; | |
72fd0718 | 3837 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
c9ee9206 VZ |
3838 | if (print) |
3839 | _print_next_block(par_num++, "USEMI"); | |
72fd0718 VZ |
3840 | break; |
3841 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
c9ee9206 VZ |
3842 | if (print) |
3843 | _print_next_block(par_num++, "UPB"); | |
72fd0718 VZ |
3844 | break; |
3845 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
c9ee9206 VZ |
3846 | if (print) |
3847 | _print_next_block(par_num++, "CSDM"); | |
72fd0718 | 3848 | break; |
8736c826 VZ |
3849 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
3850 | if (print) | |
3851 | _print_next_block(par_num++, "CCM"); | |
3852 | break; | |
72fd0718 VZ |
3853 | } |
3854 | ||
3855 | /* Clear the bit */ | |
3856 | sig &= ~cur_bit; | |
3857 | } | |
3858 | } | |
3859 | ||
3860 | return par_num; | |
3861 | } | |
3862 | ||
c9ee9206 VZ |
3863 | static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, |
3864 | bool print) | |
72fd0718 VZ |
3865 | { |
3866 | int i = 0; | |
3867 | u32 cur_bit = 0; | |
3868 | for (i = 0; sig; i++) { | |
3869 | cur_bit = ((u32)0x1 << i); | |
3870 | if (sig & cur_bit) { | |
3871 | switch (cur_bit) { | |
3872 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3873 | if (print) |
3874 | _print_next_block(par_num++, "CSEMI"); | |
72fd0718 VZ |
3875 | break; |
3876 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
c9ee9206 VZ |
3877 | if (print) |
3878 | _print_next_block(par_num++, "PXP"); | |
72fd0718 VZ |
3879 | break; |
3880 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
c9ee9206 VZ |
3881 | if (print) |
3882 | _print_next_block(par_num++, | |
72fd0718 VZ |
3883 | "PXPPCICLOCKCLIENT"); |
3884 | break; | |
3885 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
c9ee9206 VZ |
3886 | if (print) |
3887 | _print_next_block(par_num++, "CFC"); | |
72fd0718 VZ |
3888 | break; |
3889 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
c9ee9206 VZ |
3890 | if (print) |
3891 | _print_next_block(par_num++, "CDU"); | |
3892 | break; | |
3893 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
3894 | if (print) | |
3895 | _print_next_block(par_num++, "DMAE"); | |
72fd0718 VZ |
3896 | break; |
3897 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
c9ee9206 VZ |
3898 | if (print) |
3899 | _print_next_block(par_num++, "IGU"); | |
72fd0718 VZ |
3900 | break; |
3901 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
c9ee9206 VZ |
3902 | if (print) |
3903 | _print_next_block(par_num++, "MISC"); | |
72fd0718 VZ |
3904 | break; |
3905 | } | |
3906 | ||
3907 | /* Clear the bit */ | |
3908 | sig &= ~cur_bit; | |
3909 | } | |
3910 | } | |
3911 | ||
3912 | return par_num; | |
3913 | } | |
3914 | ||
c9ee9206 VZ |
3915 | static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, |
3916 | bool *global, bool print) | |
72fd0718 VZ |
3917 | { |
3918 | int i = 0; | |
3919 | u32 cur_bit = 0; | |
3920 | for (i = 0; sig; i++) { | |
3921 | cur_bit = ((u32)0x1 << i); | |
3922 | if (sig & cur_bit) { | |
3923 | switch (cur_bit) { | |
3924 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 VZ |
3925 | if (print) |
3926 | _print_next_block(par_num++, "MCP ROM"); | |
3927 | *global = true; | |
72fd0718 VZ |
3928 | break; |
3929 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 VZ |
3930 | if (print) |
3931 | _print_next_block(par_num++, | |
3932 | "MCP UMP RX"); | |
3933 | *global = true; | |
72fd0718 VZ |
3934 | break; |
3935 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 VZ |
3936 | if (print) |
3937 | _print_next_block(par_num++, | |
3938 | "MCP UMP TX"); | |
3939 | *global = true; | |
72fd0718 VZ |
3940 | break; |
3941 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
c9ee9206 VZ |
3942 | if (print) |
3943 | _print_next_block(par_num++, | |
3944 | "MCP SCPAD"); | |
3945 | *global = true; | |
72fd0718 VZ |
3946 | break; |
3947 | } | |
3948 | ||
3949 | /* Clear the bit */ | |
3950 | sig &= ~cur_bit; | |
3951 | } | |
3952 | } | |
3953 | ||
3954 | return par_num; | |
3955 | } | |
3956 | ||
8736c826 VZ |
3957 | static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, |
3958 | bool print) | |
3959 | { | |
3960 | int i = 0; | |
3961 | u32 cur_bit = 0; | |
3962 | for (i = 0; sig; i++) { | |
3963 | cur_bit = ((u32)0x1 << i); | |
3964 | if (sig & cur_bit) { | |
3965 | switch (cur_bit) { | |
3966 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
3967 | if (print) | |
3968 | _print_next_block(par_num++, "PGLUE_B"); | |
3969 | break; | |
3970 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
3971 | if (print) | |
3972 | _print_next_block(par_num++, "ATC"); | |
3973 | break; | |
3974 | } | |
3975 | ||
3976 | /* Clear the bit */ | |
3977 | sig &= ~cur_bit; | |
3978 | } | |
3979 | } | |
3980 | ||
3981 | return par_num; | |
3982 | } | |
3983 | ||
c9ee9206 | 3984 | static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
8736c826 | 3985 | u32 *sig) |
72fd0718 | 3986 | { |
8736c826 VZ |
3987 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
3988 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
3989 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
3990 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
3991 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 VZ |
3992 | int par_num = 0; |
3993 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " | |
8736c826 VZ |
3994 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " |
3995 | "[4]:0x%08x\n", | |
3996 | sig[0] & HW_PRTY_ASSERT_SET_0, | |
3997 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
3998 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
3999 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4000 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
c9ee9206 VZ |
4001 | if (print) |
4002 | netdev_err(bp->dev, | |
4003 | "Parity errors detected in blocks: "); | |
4004 | par_num = bnx2x_check_blocks_with_parity0( | |
8736c826 | 4005 | sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); |
c9ee9206 | 4006 | par_num = bnx2x_check_blocks_with_parity1( |
8736c826 | 4007 | sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); |
c9ee9206 | 4008 | par_num = bnx2x_check_blocks_with_parity2( |
8736c826 | 4009 | sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); |
c9ee9206 | 4010 | par_num = bnx2x_check_blocks_with_parity3( |
8736c826 VZ |
4011 | sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); |
4012 | par_num = bnx2x_check_blocks_with_parity4( | |
4013 | sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); | |
4014 | ||
c9ee9206 VZ |
4015 | if (print) |
4016 | pr_cont("\n"); | |
8736c826 | 4017 | |
72fd0718 VZ |
4018 | return true; |
4019 | } else | |
4020 | return false; | |
4021 | } | |
4022 | ||
c9ee9206 VZ |
4023 | /** |
4024 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
4025 | * | |
4026 | * @bp: driver handle | |
4027 | * @global: true if there was a global attention | |
4028 | * @print: show parity attention in syslog | |
4029 | */ | |
4030 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 4031 | { |
8736c826 | 4032 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
4033 | int port = BP_PORT(bp); |
4034 | ||
4035 | attn.sig[0] = REG_RD(bp, | |
4036 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
4037 | port*4); | |
4038 | attn.sig[1] = REG_RD(bp, | |
4039 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
4040 | port*4); | |
4041 | attn.sig[2] = REG_RD(bp, | |
4042 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
4043 | port*4); | |
4044 | attn.sig[3] = REG_RD(bp, | |
4045 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
4046 | port*4); | |
4047 | ||
8736c826 VZ |
4048 | if (!CHIP_IS_E1x(bp)) |
4049 | attn.sig[4] = REG_RD(bp, | |
4050 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
4051 | port*4); | |
4052 | ||
4053 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
4054 | } |
4055 | ||
f2e0899f DK |
4056 | |
4057 | static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) | |
4058 | { | |
4059 | u32 val; | |
4060 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
4061 | ||
4062 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
4063 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
4064 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
4065 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4066 | "ADDRESS_ERROR\n"); | |
4067 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) | |
4068 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4069 | "INCORRECT_RCV_BEHAVIOR\n"); | |
4070 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) | |
4071 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4072 | "WAS_ERROR_ATTN\n"); | |
4073 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) | |
4074 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4075 | "VF_LENGTH_VIOLATION_ATTN\n"); | |
4076 | if (val & | |
4077 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
4078 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4079 | "VF_GRC_SPACE_VIOLATION_ATTN\n"); | |
4080 | if (val & | |
4081 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
4082 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4083 | "VF_MSIX_BAR_VIOLATION_ATTN\n"); | |
4084 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) | |
4085 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4086 | "TCPL_ERROR_ATTN\n"); | |
4087 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) | |
4088 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4089 | "TCPL_IN_TWO_RCBS_ATTN\n"); | |
4090 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) | |
4091 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4092 | "CSSNOOP_FIFO_OVERFLOW\n"); | |
4093 | } | |
4094 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
4095 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
4096 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
4097 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
4098 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
4099 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
4100 | BNX2X_ERR("ATC_ATC_INT_STS_REG" | |
4101 | "_ATC_TCPL_TO_NOT_PEND\n"); | |
4102 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) | |
4103 | BNX2X_ERR("ATC_ATC_INT_STS_REG_" | |
4104 | "ATC_GPA_MULTIPLE_HITS\n"); | |
4105 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) | |
4106 | BNX2X_ERR("ATC_ATC_INT_STS_REG_" | |
4107 | "ATC_RCPL_TO_EMPTY_CNT\n"); | |
4108 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) | |
4109 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
4110 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
4111 | BNX2X_ERR("ATC_ATC_INT_STS_REG_" | |
4112 | "ATC_IREQ_LESS_THAN_STU\n"); | |
4113 | } | |
4114 | ||
4115 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4116 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
4117 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
4118 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4119 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
4120 | } | |
4121 | ||
4122 | } | |
4123 | ||
72fd0718 VZ |
4124 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
4125 | { | |
4126 | struct attn_route attn, *group_mask; | |
34f80b04 | 4127 | int port = BP_PORT(bp); |
877e9aa4 | 4128 | int index; |
a2fbb9ea ET |
4129 | u32 reg_addr; |
4130 | u32 val; | |
3fcaf2e5 | 4131 | u32 aeu_mask; |
c9ee9206 | 4132 | bool global = false; |
a2fbb9ea ET |
4133 | |
4134 | /* need to take HW lock because MCP or other port might also | |
4135 | try to handle this event */ | |
4a37fb66 | 4136 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 4137 | |
c9ee9206 VZ |
4138 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
4139 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 4140 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 4141 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
4142 | /* Disable HW interrupts */ |
4143 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
4144 | /* In case of parity errors don't handle attentions so that |
4145 | * other function would "see" parity errors. | |
4146 | */ | |
c9ee9206 VZ |
4147 | #else |
4148 | bnx2x_panic(); | |
4149 | #endif | |
4150 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
4151 | return; |
4152 | } | |
4153 | ||
a2fbb9ea ET |
4154 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
4155 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
4156 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
4157 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 4158 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4159 | attn.sig[4] = |
4160 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
4161 | else | |
4162 | attn.sig[4] = 0; | |
4163 | ||
4164 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
4165 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
4166 | |
4167 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
4168 | if (deasserted & (1 << index)) { | |
72fd0718 | 4169 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 4170 | |
f2e0899f DK |
4171 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x " |
4172 | "%08x %08x %08x\n", | |
4173 | index, | |
4174 | group_mask->sig[0], group_mask->sig[1], | |
4175 | group_mask->sig[2], group_mask->sig[3], | |
4176 | group_mask->sig[4]); | |
a2fbb9ea | 4177 | |
f2e0899f DK |
4178 | bnx2x_attn_int_deasserted4(bp, |
4179 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 4180 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 4181 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 4182 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 4183 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 4184 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 4185 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 4186 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 4187 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
4188 | } |
4189 | } | |
4190 | ||
4a37fb66 | 4191 | bnx2x_release_alr(bp); |
a2fbb9ea | 4192 | |
f2e0899f DK |
4193 | if (bp->common.int_block == INT_BLOCK_HC) |
4194 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4195 | COMMAND_REG_ATTN_BITS_CLR); | |
4196 | else | |
4197 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
4198 | |
4199 | val = ~deasserted; | |
f2e0899f DK |
4200 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
4201 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 4202 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 4203 | |
a2fbb9ea | 4204 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 4205 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
4206 | |
4207 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
4208 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
4209 | ||
3fcaf2e5 EG |
4210 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4211 | aeu_mask = REG_RD(bp, reg_addr); | |
4212 | ||
4213 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
4214 | aeu_mask, deasserted); | |
72fd0718 | 4215 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 4216 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4217 | |
3fcaf2e5 EG |
4218 | REG_WR(bp, reg_addr, aeu_mask); |
4219 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
4220 | |
4221 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
4222 | bp->attn_state &= ~deasserted; | |
4223 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
4224 | } | |
4225 | ||
4226 | static void bnx2x_attn_int(struct bnx2x *bp) | |
4227 | { | |
4228 | /* read local copy of bits */ | |
68d59484 EG |
4229 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
4230 | attn_bits); | |
4231 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
4232 | attn_bits_ack); | |
a2fbb9ea ET |
4233 | u32 attn_state = bp->attn_state; |
4234 | ||
4235 | /* look for changed bits */ | |
4236 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
4237 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
4238 | ||
4239 | DP(NETIF_MSG_HW, | |
4240 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
4241 | attn_bits, attn_ack, asserted, deasserted); | |
4242 | ||
4243 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 4244 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
4245 | |
4246 | /* handle bits that were raised */ | |
4247 | if (asserted) | |
4248 | bnx2x_attn_int_asserted(bp, asserted); | |
4249 | ||
4250 | if (deasserted) | |
4251 | bnx2x_attn_int_deasserted(bp, deasserted); | |
4252 | } | |
4253 | ||
619c5cb6 VZ |
4254 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
4255 | u16 index, u8 op, u8 update) | |
4256 | { | |
4257 | u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
4258 | ||
4259 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, | |
4260 | igu_addr); | |
4261 | } | |
4262 | ||
523224a3 DK |
4263 | static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
4264 | { | |
4265 | /* No memory barriers */ | |
4266 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
4267 | mmiowb(); /* keep prod updates ordered */ | |
4268 | } | |
4269 | ||
4270 | #ifdef BCM_CNIC | |
4271 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, | |
4272 | union event_ring_elem *elem) | |
4273 | { | |
619c5cb6 VZ |
4274 | u8 err = elem->message.error; |
4275 | ||
523224a3 | 4276 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
4277 | (cid < bp->cnic_eth_dev.starting_cid && |
4278 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
4279 | return 1; |
4280 | ||
4281 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
4282 | ||
619c5cb6 VZ |
4283 | if (unlikely(err)) { |
4284 | ||
523224a3 DK |
4285 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
4286 | cid); | |
4287 | bnx2x_panic_dump(bp); | |
4288 | } | |
619c5cb6 | 4289 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
4290 | return 0; |
4291 | } | |
4292 | #endif | |
4293 | ||
619c5cb6 VZ |
4294 | static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
4295 | { | |
4296 | struct bnx2x_mcast_ramrod_params rparam; | |
4297 | int rc; | |
4298 | ||
4299 | memset(&rparam, 0, sizeof(rparam)); | |
4300 | ||
4301 | rparam.mcast_obj = &bp->mcast_obj; | |
4302 | ||
4303 | netif_addr_lock_bh(bp->dev); | |
4304 | ||
4305 | /* Clear pending state for the last command */ | |
4306 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
4307 | ||
4308 | /* If there are pending mcast commands - send them */ | |
4309 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
4310 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
4311 | if (rc < 0) | |
4312 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
4313 | rc); | |
4314 | } | |
4315 | ||
4316 | netif_addr_unlock_bh(bp->dev); | |
4317 | } | |
4318 | ||
4319 | static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, | |
4320 | union event_ring_elem *elem) | |
4321 | { | |
4322 | unsigned long ramrod_flags = 0; | |
4323 | int rc = 0; | |
4324 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
4325 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
4326 | ||
4327 | /* Always push next commands out, don't wait here */ | |
4328 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
4329 | ||
4330 | switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { | |
4331 | case BNX2X_FILTER_MAC_PENDING: | |
4332 | #ifdef BCM_CNIC | |
4333 | if (cid == BNX2X_ISCSI_ETH_CID) | |
4334 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; | |
4335 | else | |
4336 | #endif | |
4337 | vlan_mac_obj = &bp->fp[cid].mac_obj; | |
4338 | ||
4339 | break; | |
4340 | vlan_mac_obj = &bp->fp[cid].mac_obj; | |
4341 | ||
4342 | case BNX2X_FILTER_MCAST_PENDING: | |
4343 | /* This is only relevant for 57710 where multicast MACs are | |
4344 | * configured as unicast MACs using the same ramrod. | |
4345 | */ | |
4346 | bnx2x_handle_mcast_eqe(bp); | |
4347 | return; | |
4348 | default: | |
4349 | BNX2X_ERR("Unsupported classification command: %d\n", | |
4350 | elem->message.data.eth_event.echo); | |
4351 | return; | |
4352 | } | |
4353 | ||
4354 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
4355 | ||
4356 | if (rc < 0) | |
4357 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
4358 | else if (rc > 0) | |
4359 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
4360 | ||
4361 | } | |
4362 | ||
4363 | #ifdef BCM_CNIC | |
4364 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); | |
4365 | #endif | |
4366 | ||
4367 | static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) | |
4368 | { | |
4369 | netif_addr_lock_bh(bp->dev); | |
4370 | ||
4371 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
4372 | ||
4373 | /* Send rx_mode command again if was requested */ | |
4374 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
4375 | bnx2x_set_storm_rx_mode(bp); | |
4376 | #ifdef BCM_CNIC | |
4377 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, | |
4378 | &bp->sp_state)) | |
4379 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
4380 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
4381 | &bp->sp_state)) | |
4382 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
4383 | #endif | |
4384 | ||
4385 | netif_addr_unlock_bh(bp->dev); | |
4386 | } | |
4387 | ||
4388 | static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( | |
4389 | struct bnx2x *bp, u32 cid) | |
4390 | { | |
6383c0b3 | 4391 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d", cid); |
619c5cb6 VZ |
4392 | #ifdef BCM_CNIC |
4393 | if (cid == BNX2X_FCOE_ETH_CID) | |
4394 | return &bnx2x_fcoe(bp, q_obj); | |
4395 | else | |
4396 | #endif | |
6383c0b3 | 4397 | return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); |
619c5cb6 VZ |
4398 | } |
4399 | ||
523224a3 DK |
4400 | static void bnx2x_eq_int(struct bnx2x *bp) |
4401 | { | |
4402 | u16 hw_cons, sw_cons, sw_prod; | |
4403 | union event_ring_elem *elem; | |
4404 | u32 cid; | |
4405 | u8 opcode; | |
4406 | int spqe_cnt = 0; | |
619c5cb6 VZ |
4407 | struct bnx2x_queue_sp_obj *q_obj; |
4408 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
4409 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
4410 | |
4411 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
4412 | ||
4413 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
4414 | * when we get the the next-page we nned to adjust so the loop | |
4415 | * condition below will be met. The next element is the size of a | |
4416 | * regular element and hence incrementing by 1 | |
4417 | */ | |
4418 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
4419 | hw_cons++; | |
4420 | ||
25985edc | 4421 | /* This function may never run in parallel with itself for a |
523224a3 DK |
4422 | * specific bp, thus there is no need in "paired" read memory |
4423 | * barrier here. | |
4424 | */ | |
4425 | sw_cons = bp->eq_cons; | |
4426 | sw_prod = bp->eq_prod; | |
4427 | ||
d6cae238 | 4428 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 4429 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
4430 | |
4431 | for (; sw_cons != hw_cons; | |
4432 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
4433 | ||
4434 | ||
4435 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; | |
4436 | ||
4437 | cid = SW_CID(elem->message.data.cfc_del_event.cid); | |
4438 | opcode = elem->message.opcode; | |
4439 | ||
4440 | ||
4441 | /* handle eq element */ | |
4442 | switch (opcode) { | |
4443 | case EVENT_RING_OPCODE_STAT_QUERY: | |
619c5cb6 VZ |
4444 | DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", |
4445 | bp->stats_comp++); | |
523224a3 | 4446 | /* nothing to do with stats comp */ |
d6cae238 | 4447 | goto next_spqe; |
523224a3 DK |
4448 | |
4449 | case EVENT_RING_OPCODE_CFC_DEL: | |
4450 | /* handle according to cid range */ | |
4451 | /* | |
4452 | * we may want to verify here that the bp state is | |
4453 | * HALTING | |
4454 | */ | |
d6cae238 | 4455 | DP(BNX2X_MSG_SP, |
523224a3 DK |
4456 | "got delete ramrod for MULTI[%d]\n", cid); |
4457 | #ifdef BCM_CNIC | |
4458 | if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
4459 | goto next_spqe; | |
4460 | #endif | |
619c5cb6 VZ |
4461 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
4462 | ||
4463 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
4464 | break; | |
4465 | ||
4466 | ||
523224a3 DK |
4467 | |
4468 | goto next_spqe; | |
e4901dde VZ |
4469 | |
4470 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
d6cae238 | 4471 | DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); |
6debea87 DK |
4472 | if (f_obj->complete_cmd(bp, f_obj, |
4473 | BNX2X_F_CMD_TX_STOP)) | |
4474 | break; | |
e4901dde VZ |
4475 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
4476 | goto next_spqe; | |
619c5cb6 | 4477 | |
e4901dde | 4478 | case EVENT_RING_OPCODE_START_TRAFFIC: |
d6cae238 | 4479 | DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); |
6debea87 DK |
4480 | if (f_obj->complete_cmd(bp, f_obj, |
4481 | BNX2X_F_CMD_TX_START)) | |
4482 | break; | |
e4901dde VZ |
4483 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
4484 | goto next_spqe; | |
619c5cb6 | 4485 | case EVENT_RING_OPCODE_FUNCTION_START: |
d6cae238 | 4486 | DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); |
619c5cb6 VZ |
4487 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
4488 | break; | |
4489 | ||
4490 | goto next_spqe; | |
4491 | ||
4492 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
d6cae238 | 4493 | DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); |
619c5cb6 VZ |
4494 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
4495 | break; | |
4496 | ||
4497 | goto next_spqe; | |
523224a3 DK |
4498 | } |
4499 | ||
4500 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
4501 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
4502 | BNX2X_STATE_OPEN): | |
4503 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 4504 | BNX2X_STATE_OPENING_WAIT4_PORT): |
619c5cb6 VZ |
4505 | cid = elem->message.data.eth_event.echo & |
4506 | BNX2X_SWCID_MASK; | |
d6cae238 | 4507 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
619c5cb6 VZ |
4508 | cid); |
4509 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
4510 | break; |
4511 | ||
619c5cb6 VZ |
4512 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
4513 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
4514 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 4515 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
4516 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
4517 | BNX2X_STATE_OPEN): | |
4518 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4519 | BNX2X_STATE_DIAG): | |
4520 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4521 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 4522 | DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); |
619c5cb6 | 4523 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
4524 | break; |
4525 | ||
619c5cb6 VZ |
4526 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
4527 | BNX2X_STATE_OPEN): | |
4528 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4529 | BNX2X_STATE_DIAG): | |
4530 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4531 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 4532 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 4533 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
4534 | break; |
4535 | ||
619c5cb6 VZ |
4536 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
4537 | BNX2X_STATE_OPEN): | |
4538 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
4539 | BNX2X_STATE_DIAG): | |
4540 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 4541 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 4542 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 4543 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
4544 | break; |
4545 | default: | |
4546 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
4547 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
4548 | elem->message.opcode, bp->state); | |
523224a3 DK |
4549 | } |
4550 | next_spqe: | |
4551 | spqe_cnt++; | |
4552 | } /* for */ | |
4553 | ||
8fe23fbd | 4554 | smp_mb__before_atomic_inc(); |
6e30dd4e | 4555 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
4556 | |
4557 | bp->eq_cons = sw_cons; | |
4558 | bp->eq_prod = sw_prod; | |
4559 | /* Make sure that above mem writes were issued towards the memory */ | |
4560 | smp_wmb(); | |
4561 | ||
4562 | /* update producer */ | |
4563 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
4564 | } | |
4565 | ||
a2fbb9ea ET |
4566 | static void bnx2x_sp_task(struct work_struct *work) |
4567 | { | |
1cf167f2 | 4568 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea ET |
4569 | u16 status; |
4570 | ||
a2fbb9ea | 4571 | status = bnx2x_update_dsb_idx(bp); |
34f80b04 EG |
4572 | /* if (status == 0) */ |
4573 | /* BNX2X_ERR("spurious slowpath interrupt!\n"); */ | |
a2fbb9ea | 4574 | |
cdaa7cb8 | 4575 | DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); |
a2fbb9ea | 4576 | |
877e9aa4 | 4577 | /* HW attentions */ |
523224a3 | 4578 | if (status & BNX2X_DEF_SB_ATT_IDX) { |
a2fbb9ea | 4579 | bnx2x_attn_int(bp); |
523224a3 | 4580 | status &= ~BNX2X_DEF_SB_ATT_IDX; |
cdaa7cb8 VZ |
4581 | } |
4582 | ||
523224a3 DK |
4583 | /* SP events: STAT_QUERY and others */ |
4584 | if (status & BNX2X_DEF_SB_IDX) { | |
ec6ba945 VZ |
4585 | #ifdef BCM_CNIC |
4586 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 4587 | |
ec6ba945 | 4588 | if ((!NO_FCOE(bp)) && |
019dbb4c VZ |
4589 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
4590 | /* | |
4591 | * Prevent local bottom-halves from running as | |
4592 | * we are going to change the local NAPI list. | |
4593 | */ | |
4594 | local_bh_disable(); | |
ec6ba945 | 4595 | napi_schedule(&bnx2x_fcoe(bp, napi)); |
019dbb4c VZ |
4596 | local_bh_enable(); |
4597 | } | |
ec6ba945 | 4598 | #endif |
523224a3 DK |
4599 | /* Handle EQ completions */ |
4600 | bnx2x_eq_int(bp); | |
4601 | ||
4602 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
4603 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
4604 | ||
4605 | status &= ~BNX2X_DEF_SB_IDX; | |
cdaa7cb8 VZ |
4606 | } |
4607 | ||
4608 | if (unlikely(status)) | |
4609 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
4610 | status); | |
a2fbb9ea | 4611 | |
523224a3 DK |
4612 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, |
4613 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
a2fbb9ea ET |
4614 | } |
4615 | ||
9f6c9258 | 4616 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
4617 | { |
4618 | struct net_device *dev = dev_instance; | |
4619 | struct bnx2x *bp = netdev_priv(dev); | |
4620 | ||
523224a3 DK |
4621 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
4622 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
4623 | |
4624 | #ifdef BNX2X_STOP_ON_ERROR | |
4625 | if (unlikely(bp->panic)) | |
4626 | return IRQ_HANDLED; | |
4627 | #endif | |
4628 | ||
993ac7b5 MC |
4629 | #ifdef BCM_CNIC |
4630 | { | |
4631 | struct cnic_ops *c_ops; | |
4632 | ||
4633 | rcu_read_lock(); | |
4634 | c_ops = rcu_dereference(bp->cnic_ops); | |
4635 | if (c_ops) | |
4636 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
4637 | rcu_read_unlock(); | |
4638 | } | |
4639 | #endif | |
1cf167f2 | 4640 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
4641 | |
4642 | return IRQ_HANDLED; | |
4643 | } | |
4644 | ||
4645 | /* end of slow path */ | |
4646 | ||
619c5cb6 VZ |
4647 | |
4648 | void bnx2x_drv_pulse(struct bnx2x *bp) | |
4649 | { | |
4650 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
4651 | bp->fw_drv_pulse_wr_seq); | |
4652 | } | |
4653 | ||
4654 | ||
a2fbb9ea ET |
4655 | static void bnx2x_timer(unsigned long data) |
4656 | { | |
6383c0b3 | 4657 | u8 cos; |
a2fbb9ea ET |
4658 | struct bnx2x *bp = (struct bnx2x *) data; |
4659 | ||
4660 | if (!netif_running(bp->dev)) | |
4661 | return; | |
4662 | ||
a2fbb9ea ET |
4663 | if (poll) { |
4664 | struct bnx2x_fastpath *fp = &bp->fp[0]; | |
a2fbb9ea | 4665 | |
6383c0b3 AE |
4666 | for_each_cos_in_tx_queue(fp, cos) |
4667 | bnx2x_tx_int(bp, &fp->txdata[cos]); | |
b8ee8328 | 4668 | bnx2x_rx_int(fp, 1000); |
a2fbb9ea ET |
4669 | } |
4670 | ||
34f80b04 | 4671 | if (!BP_NOMCP(bp)) { |
f2e0899f | 4672 | int mb_idx = BP_FW_MB_IDX(bp); |
a2fbb9ea ET |
4673 | u32 drv_pulse; |
4674 | u32 mcp_pulse; | |
4675 | ||
4676 | ++bp->fw_drv_pulse_wr_seq; | |
4677 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
4678 | /* TBD - add SYSTEM_TIME */ | |
4679 | drv_pulse = bp->fw_drv_pulse_wr_seq; | |
619c5cb6 | 4680 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 4681 | |
f2e0899f | 4682 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
4683 | MCP_PULSE_SEQ_MASK); |
4684 | /* The delta between driver pulse and mcp response | |
4685 | * should be 1 (before mcp response) or 0 (after mcp response) | |
4686 | */ | |
4687 | if ((drv_pulse != mcp_pulse) && | |
4688 | (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { | |
4689 | /* someone lost a heartbeat... */ | |
4690 | BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
4691 | drv_pulse, mcp_pulse); | |
4692 | } | |
4693 | } | |
4694 | ||
f34d28ea | 4695 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 4696 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 4697 | |
a2fbb9ea ET |
4698 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
4699 | } | |
4700 | ||
4701 | /* end of Statistics */ | |
4702 | ||
4703 | /* nic init */ | |
4704 | ||
4705 | /* | |
4706 | * nic init service functions | |
4707 | */ | |
4708 | ||
523224a3 | 4709 | static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 4710 | { |
523224a3 DK |
4711 | u32 i; |
4712 | if (!(len%4) && !(addr%4)) | |
4713 | for (i = 0; i < len; i += 4) | |
4714 | REG_WR(bp, addr + i, fill); | |
4715 | else | |
4716 | for (i = 0; i < len; i++) | |
4717 | REG_WR8(bp, addr + i, fill); | |
34f80b04 | 4718 | |
34f80b04 EG |
4719 | } |
4720 | ||
523224a3 DK |
4721 | /* helper: writes FP SP data to FW - data_size in dwords */ |
4722 | static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, | |
4723 | int fw_sb_id, | |
4724 | u32 *sb_data_p, | |
4725 | u32 data_size) | |
34f80b04 | 4726 | { |
a2fbb9ea | 4727 | int index; |
523224a3 DK |
4728 | for (index = 0; index < data_size; index++) |
4729 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
4730 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
4731 | sizeof(u32)*index, | |
4732 | *(sb_data_p + index)); | |
4733 | } | |
a2fbb9ea | 4734 | |
523224a3 DK |
4735 | static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
4736 | { | |
4737 | u32 *sb_data_p; | |
4738 | u32 data_size = 0; | |
f2e0899f | 4739 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 4740 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 4741 | |
523224a3 | 4742 | /* disable the function first */ |
619c5cb6 | 4743 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 4744 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 4745 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
4746 | sb_data_e2.common.p_func.vf_valid = false; |
4747 | sb_data_p = (u32 *)&sb_data_e2; | |
4748 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
4749 | } else { | |
4750 | memset(&sb_data_e1x, 0, | |
4751 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 4752 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
4753 | sb_data_e1x.common.p_func.vf_valid = false; |
4754 | sb_data_p = (u32 *)&sb_data_e1x; | |
4755 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
4756 | } | |
523224a3 | 4757 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 4758 | |
523224a3 DK |
4759 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
4760 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
4761 | CSTORM_STATUS_BLOCK_SIZE); | |
4762 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
4763 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
4764 | CSTORM_SYNC_BLOCK_SIZE); | |
4765 | } | |
34f80b04 | 4766 | |
523224a3 DK |
4767 | /* helper: writes SP SB data to FW */ |
4768 | static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, | |
4769 | struct hc_sp_status_block_data *sp_sb_data) | |
4770 | { | |
4771 | int func = BP_FUNC(bp); | |
4772 | int i; | |
4773 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
4774 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
4775 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
4776 | i*sizeof(u32), | |
4777 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
4778 | } |
4779 | ||
523224a3 | 4780 | static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
4781 | { |
4782 | int func = BP_FUNC(bp); | |
523224a3 DK |
4783 | struct hc_sp_status_block_data sp_sb_data; |
4784 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 4785 | |
619c5cb6 | 4786 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
4787 | sp_sb_data.p_func.vf_valid = false; |
4788 | ||
4789 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
4790 | ||
4791 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
4792 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
4793 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
4794 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
4795 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
4796 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
4797 | ||
4798 | } | |
4799 | ||
4800 | ||
4801 | static inline | |
4802 | void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, | |
4803 | int igu_sb_id, int igu_seg_id) | |
4804 | { | |
4805 | hc_sm->igu_sb_id = igu_sb_id; | |
4806 | hc_sm->igu_seg_id = igu_seg_id; | |
4807 | hc_sm->timer_value = 0xFF; | |
4808 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
4809 | } |
4810 | ||
8d96286a | 4811 | static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 4812 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 4813 | { |
523224a3 DK |
4814 | int igu_seg_id; |
4815 | ||
f2e0899f | 4816 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
4817 | struct hc_status_block_data_e1x sb_data_e1x; |
4818 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
4819 | int data_size; |
4820 | u32 *sb_data_p; | |
4821 | ||
f2e0899f DK |
4822 | if (CHIP_INT_MODE_IS_BC(bp)) |
4823 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
4824 | else | |
4825 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
4826 | |
4827 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
4828 | ||
619c5cb6 | 4829 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 4830 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 4831 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
4832 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
4833 | sb_data_e2.common.p_func.vf_id = vfid; | |
4834 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
4835 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
4836 | sb_data_e2.common.same_igu_sb_1b = true; | |
4837 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
4838 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
4839 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
4840 | sb_data_p = (u32 *)&sb_data_e2; |
4841 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
4842 | } else { | |
4843 | memset(&sb_data_e1x, 0, | |
4844 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 4845 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
4846 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
4847 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
4848 | sb_data_e1x.common.p_func.vf_valid = false; | |
4849 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
4850 | sb_data_e1x.common.same_igu_sb_1b = true; | |
4851 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
4852 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
4853 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
4854 | sb_data_p = (u32 *)&sb_data_e1x; |
4855 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
4856 | } | |
523224a3 DK |
4857 | |
4858 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
4859 | igu_sb_id, igu_seg_id); | |
4860 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
4861 | igu_sb_id, igu_seg_id); | |
4862 | ||
4863 | DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); | |
4864 | ||
4865 | /* write indecies to HW */ | |
4866 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); | |
4867 | } | |
4868 | ||
619c5cb6 | 4869 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
4870 | u16 tx_usec, u16 rx_usec) |
4871 | { | |
6383c0b3 | 4872 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 4873 | false, rx_usec); |
6383c0b3 AE |
4874 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
4875 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
4876 | tx_usec); | |
4877 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
4878 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
4879 | tx_usec); | |
4880 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
4881 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
4882 | tx_usec); | |
523224a3 | 4883 | } |
f2e0899f | 4884 | |
523224a3 DK |
4885 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
4886 | { | |
4887 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
4888 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
4889 | int igu_sp_sb_index; | |
4890 | int igu_seg_id; | |
34f80b04 EG |
4891 | int port = BP_PORT(bp); |
4892 | int func = BP_FUNC(bp); | |
523224a3 | 4893 | int reg_offset; |
a2fbb9ea | 4894 | u64 section; |
523224a3 DK |
4895 | int index; |
4896 | struct hc_sp_status_block_data sp_sb_data; | |
4897 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
4898 | ||
f2e0899f DK |
4899 | if (CHIP_INT_MODE_IS_BC(bp)) { |
4900 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
4901 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
4902 | } else { | |
4903 | igu_sp_sb_index = bp->igu_dsb_id; | |
4904 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
4905 | } | |
a2fbb9ea ET |
4906 | |
4907 | /* ATTN */ | |
523224a3 | 4908 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 4909 | atten_status_block); |
523224a3 | 4910 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 4911 | |
49d66772 ET |
4912 | bp->attn_state = 0; |
4913 | ||
a2fbb9ea ET |
4914 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
4915 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
34f80b04 | 4916 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
4917 | int sindex; |
4918 | /* take care of sig[0]..sig[4] */ | |
4919 | for (sindex = 0; sindex < 4; sindex++) | |
4920 | bp->attn_group[index].sig[sindex] = | |
4921 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 4922 | |
619c5cb6 | 4923 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4924 | /* |
4925 | * enable5 is separate from the rest of the registers, | |
4926 | * and therefore the address skip is 4 | |
4927 | * and not 16 between the different groups | |
4928 | */ | |
4929 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
4930 | reg_offset + 0x10 + 0x4*index); | |
4931 | else | |
4932 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
4933 | } |
4934 | ||
f2e0899f DK |
4935 | if (bp->common.int_block == INT_BLOCK_HC) { |
4936 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
4937 | HC_REG_ATTN_MSG0_ADDR_L); | |
4938 | ||
4939 | REG_WR(bp, reg_offset, U64_LO(section)); | |
4940 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 4941 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
4942 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
4943 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
4944 | } | |
a2fbb9ea | 4945 | |
523224a3 DK |
4946 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
4947 | sp_sb); | |
a2fbb9ea | 4948 | |
523224a3 | 4949 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 4950 | |
619c5cb6 | 4951 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
4952 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
4953 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
4954 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
4955 | sp_sb_data.igu_seg_id = igu_seg_id; | |
4956 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 4957 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 4958 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 4959 | |
523224a3 | 4960 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 4961 | |
523224a3 | 4962 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
4963 | } |
4964 | ||
9f6c9258 | 4965 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 4966 | { |
a2fbb9ea ET |
4967 | int i; |
4968 | ||
ec6ba945 | 4969 | for_each_eth_queue(bp, i) |
523224a3 | 4970 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 4971 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
4972 | } |
4973 | ||
a2fbb9ea ET |
4974 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
4975 | { | |
a2fbb9ea | 4976 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 4977 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 4978 | |
a2fbb9ea | 4979 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
4980 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
4981 | bp->spq_prod_bd = bp->spq; | |
4982 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
4983 | } |
4984 | ||
523224a3 | 4985 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
4986 | { |
4987 | int i; | |
523224a3 DK |
4988 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
4989 | union event_ring_elem *elem = | |
4990 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 4991 | |
523224a3 DK |
4992 | elem->next_page.addr.hi = |
4993 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
4994 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
4995 | elem->next_page.addr.lo = | |
4996 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
4997 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 4998 | } |
523224a3 DK |
4999 | bp->eq_cons = 0; |
5000 | bp->eq_prod = NUM_EQ_DESC; | |
5001 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
6e30dd4e VZ |
5002 | /* we want a warning message before it gets rought... */ |
5003 | atomic_set(&bp->eq_spq_left, | |
5004 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
5005 | } |
5006 | ||
619c5cb6 VZ |
5007 | |
5008 | /* called with netif_addr_lock_bh() */ | |
5009 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, | |
5010 | unsigned long rx_mode_flags, | |
5011 | unsigned long rx_accept_flags, | |
5012 | unsigned long tx_accept_flags, | |
5013 | unsigned long ramrod_flags) | |
ab532cf3 | 5014 | { |
619c5cb6 VZ |
5015 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
5016 | int rc; | |
5017 | ||
5018 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
5019 | ||
5020 | /* Prepare ramrod parameters */ | |
5021 | ramrod_param.cid = 0; | |
5022 | ramrod_param.cl_id = cl_id; | |
5023 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
5024 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 5025 | |
619c5cb6 VZ |
5026 | ramrod_param.pstate = &bp->sp_state; |
5027 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 5028 | |
619c5cb6 VZ |
5029 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
5030 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
5031 | ||
5032 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5033 | ||
5034 | ramrod_param.ramrod_flags = ramrod_flags; | |
5035 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
5036 | ||
5037 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
5038 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
5039 | ||
5040 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
5041 | if (rc < 0) { | |
5042 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
5043 | return; | |
5044 | } | |
a2fbb9ea ET |
5045 | } |
5046 | ||
619c5cb6 VZ |
5047 | /* called with netif_addr_lock_bh() */ |
5048 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |
471de716 | 5049 | { |
619c5cb6 VZ |
5050 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; |
5051 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
471de716 | 5052 | |
619c5cb6 VZ |
5053 | #ifdef BCM_CNIC |
5054 | if (!NO_FCOE(bp)) | |
5055 | ||
5056 | /* Configure rx_mode of FCoE Queue */ | |
5057 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
5058 | #endif | |
5059 | ||
5060 | switch (bp->rx_mode) { | |
5061 | case BNX2X_RX_MODE_NONE: | |
5062 | /* | |
5063 | * 'drop all' supersedes any accept flags that may have been | |
5064 | * passed to the function. | |
5065 | */ | |
5066 | break; | |
5067 | case BNX2X_RX_MODE_NORMAL: | |
5068 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5069 | __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); | |
5070 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5071 | ||
5072 | /* internal switching mode */ | |
5073 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5074 | __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); | |
5075 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5076 | ||
5077 | break; | |
5078 | case BNX2X_RX_MODE_ALLMULTI: | |
5079 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5080 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5081 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5082 | ||
5083 | /* internal switching mode */ | |
5084 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5085 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5086 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5087 | ||
5088 | break; | |
5089 | case BNX2X_RX_MODE_PROMISC: | |
5090 | /* According to deffinition of SI mode, iface in promisc mode | |
5091 | * should receive matched and unmatched (in resolution of port) | |
5092 | * unicast packets. | |
5093 | */ | |
5094 | __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); | |
5095 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5096 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5097 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5098 | ||
5099 | /* internal switching mode */ | |
5100 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5101 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5102 | ||
5103 | if (IS_MF_SI(bp)) | |
5104 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); | |
5105 | else | |
5106 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5107 | ||
5108 | break; | |
5109 | default: | |
5110 | BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); | |
5111 | return; | |
5112 | } | |
de832a55 | 5113 | |
619c5cb6 VZ |
5114 | if (bp->rx_mode != BNX2X_RX_MODE_NONE) { |
5115 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); | |
5116 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); | |
34f80b04 EG |
5117 | } |
5118 | ||
619c5cb6 VZ |
5119 | __set_bit(RAMROD_RX, &ramrod_flags); |
5120 | __set_bit(RAMROD_TX, &ramrod_flags); | |
5121 | ||
5122 | bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, | |
5123 | tx_accept_flags, ramrod_flags); | |
5124 | } | |
5125 | ||
5126 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
5127 | { | |
5128 | int i; | |
5129 | ||
0793f83f DK |
5130 | if (IS_MF_SI(bp)) |
5131 | /* | |
5132 | * In switch independent mode, the TSTORM needs to accept | |
5133 | * packets that failed classification, since approximate match | |
5134 | * mac addresses aren't written to NIG LLH | |
5135 | */ | |
5136 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5137 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); | |
619c5cb6 VZ |
5138 | else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ |
5139 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5140 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); | |
0793f83f | 5141 | |
523224a3 DK |
5142 | /* Zero this manually as its initialization is |
5143 | currently missing in the initTool */ | |
5144 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 5145 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 5146 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 5147 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5148 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
5149 | CHIP_INT_MODE_IS_BC(bp) ? | |
5150 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
5151 | } | |
523224a3 | 5152 | } |
8a1c38d1 | 5153 | |
471de716 EG |
5154 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
5155 | { | |
5156 | switch (load_code) { | |
5157 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 5158 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
5159 | bnx2x_init_internal_common(bp); |
5160 | /* no break */ | |
5161 | ||
5162 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 5163 | /* nothing to do */ |
471de716 EG |
5164 | /* no break */ |
5165 | ||
5166 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
5167 | /* internal memory per function is |
5168 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
5169 | break; |
5170 | ||
5171 | default: | |
5172 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
5173 | break; | |
5174 | } | |
5175 | } | |
5176 | ||
619c5cb6 | 5177 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 5178 | { |
6383c0b3 | 5179 | return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; |
619c5cb6 | 5180 | } |
523224a3 | 5181 | |
619c5cb6 VZ |
5182 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
5183 | { | |
6383c0b3 | 5184 | return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; |
619c5cb6 VZ |
5185 | } |
5186 | ||
5187 | static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) | |
5188 | { | |
5189 | if (CHIP_IS_E1x(fp->bp)) | |
5190 | return BP_L_ID(fp->bp) + fp->index; | |
5191 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
5192 | return bnx2x_fp_igu_sb_id(fp); | |
5193 | } | |
5194 | ||
6383c0b3 | 5195 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
5196 | { |
5197 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 5198 | u8 cos; |
619c5cb6 | 5199 | unsigned long q_type = 0; |
6383c0b3 | 5200 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
523224a3 | 5201 | |
b3b83c3f | 5202 | fp->cid = fp_idx; |
619c5cb6 VZ |
5203 | fp->cl_id = bnx2x_fp_cl_id(fp); |
5204 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
5205 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 5206 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
5207 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
5208 | ||
523224a3 | 5209 | /* init shortcut */ |
619c5cb6 | 5210 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
523224a3 DK |
5211 | /* Setup SB indicies */ |
5212 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; | |
523224a3 | 5213 | |
619c5cb6 VZ |
5214 | /* Configure Queue State object */ |
5215 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
5216 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
5217 | |
5218 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
5219 | ||
5220 | /* init tx data */ | |
5221 | for_each_cos_in_tx_queue(fp, cos) { | |
5222 | bnx2x_init_txdata(bp, &fp->txdata[cos], | |
5223 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos), | |
5224 | FP_COS_TO_TXQ(fp, cos), | |
5225 | BNX2X_TX_SB_INDEX_BASE + cos); | |
5226 | cids[cos] = fp->txdata[cos].cid; | |
5227 | } | |
5228 | ||
5229 | bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, | |
5230 | BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
5231 | bnx2x_sp_mapping(bp, q_rdata), q_type); | |
619c5cb6 VZ |
5232 | |
5233 | /** | |
5234 | * Configure classification DBs: Always enable Tx switching | |
5235 | */ | |
5236 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
5237 | ||
523224a3 DK |
5238 | DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " |
5239 | "cl_id %d fw_sb %d igu_sb %d\n", | |
619c5cb6 | 5240 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, |
523224a3 DK |
5241 | fp->igu_sb_id); |
5242 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
5243 | fp->fw_sb_id, fp->igu_sb_id); | |
5244 | ||
5245 | bnx2x_update_fpsb_idx(fp); | |
5246 | } | |
5247 | ||
9f6c9258 | 5248 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) |
a2fbb9ea ET |
5249 | { |
5250 | int i; | |
5251 | ||
ec6ba945 | 5252 | for_each_eth_queue(bp, i) |
6383c0b3 | 5253 | bnx2x_init_eth_fp(bp, i); |
37b091ba | 5254 | #ifdef BCM_CNIC |
ec6ba945 VZ |
5255 | if (!NO_FCOE(bp)) |
5256 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
5257 | |
5258 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
5259 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 5260 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 5261 | |
37b091ba | 5262 | #endif |
a2fbb9ea | 5263 | |
020c7e3f YR |
5264 | /* Initialize MOD_ABS interrupts */ |
5265 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
5266 | bp->common.shmem_base, bp->common.shmem2_base, | |
5267 | BP_PORT(bp)); | |
16119785 EG |
5268 | /* ensure status block indices were read */ |
5269 | rmb(); | |
5270 | ||
523224a3 | 5271 | bnx2x_init_def_sb(bp); |
5c862848 | 5272 | bnx2x_update_dsb_idx(bp); |
a2fbb9ea | 5273 | bnx2x_init_rx_rings(bp); |
523224a3 | 5274 | bnx2x_init_tx_rings(bp); |
a2fbb9ea | 5275 | bnx2x_init_sp_ring(bp); |
523224a3 | 5276 | bnx2x_init_eq_ring(bp); |
471de716 | 5277 | bnx2x_init_internal(bp, load_code); |
523224a3 | 5278 | bnx2x_pf_init(bp); |
0ef00459 EG |
5279 | bnx2x_stats_init(bp); |
5280 | ||
0ef00459 EG |
5281 | /* flush all before enabling interrupts */ |
5282 | mb(); | |
5283 | mmiowb(); | |
5284 | ||
615f8fd9 | 5285 | bnx2x_int_enable(bp); |
eb8da205 EG |
5286 | |
5287 | /* Check for SPIO5 */ | |
5288 | bnx2x_attn_int_deasserted0(bp, | |
5289 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
5290 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
5291 | } |
5292 | ||
5293 | /* end of nic init */ | |
5294 | ||
5295 | /* | |
5296 | * gzip service functions | |
5297 | */ | |
5298 | ||
5299 | static int bnx2x_gunzip_init(struct bnx2x *bp) | |
5300 | { | |
1a983142 FT |
5301 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
5302 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
5303 | if (bp->gunzip_buf == NULL) |
5304 | goto gunzip_nomem1; | |
5305 | ||
5306 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
5307 | if (bp->strm == NULL) | |
5308 | goto gunzip_nomem2; | |
5309 | ||
7ab24bfd | 5310 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
5311 | if (bp->strm->workspace == NULL) |
5312 | goto gunzip_nomem3; | |
5313 | ||
5314 | return 0; | |
5315 | ||
5316 | gunzip_nomem3: | |
5317 | kfree(bp->strm); | |
5318 | bp->strm = NULL; | |
5319 | ||
5320 | gunzip_nomem2: | |
1a983142 FT |
5321 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5322 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5323 | bp->gunzip_buf = NULL; |
5324 | ||
5325 | gunzip_nomem1: | |
cdaa7cb8 VZ |
5326 | netdev_err(bp->dev, "Cannot allocate firmware buffer for" |
5327 | " un-compression\n"); | |
a2fbb9ea ET |
5328 | return -ENOMEM; |
5329 | } | |
5330 | ||
5331 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
5332 | { | |
b3b83c3f | 5333 | if (bp->strm) { |
7ab24bfd | 5334 | vfree(bp->strm->workspace); |
b3b83c3f DK |
5335 | kfree(bp->strm); |
5336 | bp->strm = NULL; | |
5337 | } | |
a2fbb9ea ET |
5338 | |
5339 | if (bp->gunzip_buf) { | |
1a983142 FT |
5340 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5341 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5342 | bp->gunzip_buf = NULL; |
5343 | } | |
5344 | } | |
5345 | ||
94a78b79 | 5346 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
5347 | { |
5348 | int n, rc; | |
5349 | ||
5350 | /* check gzip header */ | |
94a78b79 VZ |
5351 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
5352 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 5353 | return -EINVAL; |
94a78b79 | 5354 | } |
a2fbb9ea ET |
5355 | |
5356 | n = 10; | |
5357 | ||
34f80b04 | 5358 | #define FNAME 0x8 |
a2fbb9ea ET |
5359 | |
5360 | if (zbuf[3] & FNAME) | |
5361 | while ((zbuf[n++] != 0) && (n < len)); | |
5362 | ||
94a78b79 | 5363 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
5364 | bp->strm->avail_in = len - n; |
5365 | bp->strm->next_out = bp->gunzip_buf; | |
5366 | bp->strm->avail_out = FW_BUF_SIZE; | |
5367 | ||
5368 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
5369 | if (rc != Z_OK) | |
5370 | return rc; | |
5371 | ||
5372 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
5373 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
5374 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
5375 | bp->strm->msg); | |
a2fbb9ea ET |
5376 | |
5377 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
5378 | if (bp->gunzip_outlen & 0x3) | |
cdaa7cb8 VZ |
5379 | netdev_err(bp->dev, "Firmware decompression error:" |
5380 | " gunzip_outlen (%d) not aligned\n", | |
5381 | bp->gunzip_outlen); | |
a2fbb9ea ET |
5382 | bp->gunzip_outlen >>= 2; |
5383 | ||
5384 | zlib_inflateEnd(bp->strm); | |
5385 | ||
5386 | if (rc == Z_STREAM_END) | |
5387 | return 0; | |
5388 | ||
5389 | return rc; | |
5390 | } | |
5391 | ||
5392 | /* nic load/unload */ | |
5393 | ||
5394 | /* | |
34f80b04 | 5395 | * General service functions |
a2fbb9ea ET |
5396 | */ |
5397 | ||
5398 | /* send a NIG loopback debug packet */ | |
5399 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
5400 | { | |
a2fbb9ea | 5401 | u32 wb_write[3]; |
a2fbb9ea ET |
5402 | |
5403 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
5404 | wb_write[0] = 0x55555555; |
5405 | wb_write[1] = 0x55555555; | |
34f80b04 | 5406 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 5407 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5408 | |
5409 | /* NON-IP protocol */ | |
a2fbb9ea ET |
5410 | wb_write[0] = 0x09000000; |
5411 | wb_write[1] = 0x55555555; | |
34f80b04 | 5412 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 5413 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5414 | } |
5415 | ||
5416 | /* some of the internal memories | |
5417 | * are not directly readable from the driver | |
5418 | * to test them we send debug packets | |
5419 | */ | |
5420 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
5421 | { | |
5422 | int factor; | |
5423 | int count, i; | |
5424 | u32 val = 0; | |
5425 | ||
ad8d3948 | 5426 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 5427 | factor = 120; |
ad8d3948 EG |
5428 | else if (CHIP_REV_IS_EMUL(bp)) |
5429 | factor = 200; | |
5430 | else | |
a2fbb9ea | 5431 | factor = 1; |
a2fbb9ea | 5432 | |
a2fbb9ea ET |
5433 | /* Disable inputs of parser neighbor blocks */ |
5434 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5435 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5436 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5437 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5438 | |
5439 | /* Write 0 to parser credits for CFC search request */ | |
5440 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5441 | ||
5442 | /* send Ethernet packet */ | |
5443 | bnx2x_lb_pckt(bp); | |
5444 | ||
5445 | /* TODO do i reset NIG statistic? */ | |
5446 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
5447 | count = 1000 * factor; | |
5448 | while (count) { | |
34f80b04 | 5449 | |
a2fbb9ea ET |
5450 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5451 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5452 | if (val == 0x10) |
5453 | break; | |
5454 | ||
5455 | msleep(10); | |
5456 | count--; | |
5457 | } | |
5458 | if (val != 0x10) { | |
5459 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5460 | return -1; | |
5461 | } | |
5462 | ||
5463 | /* Wait until PRS register shows 1 packet */ | |
5464 | count = 1000 * factor; | |
5465 | while (count) { | |
5466 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
5467 | if (val == 1) |
5468 | break; | |
5469 | ||
5470 | msleep(10); | |
5471 | count--; | |
5472 | } | |
5473 | if (val != 0x1) { | |
5474 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5475 | return -2; | |
5476 | } | |
5477 | ||
5478 | /* Reset and init BRB, PRS */ | |
34f80b04 | 5479 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 5480 | msleep(50); |
34f80b04 | 5481 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 5482 | msleep(50); |
619c5cb6 VZ |
5483 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
5484 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
5485 | |
5486 | DP(NETIF_MSG_HW, "part2\n"); | |
5487 | ||
5488 | /* Disable inputs of parser neighbor blocks */ | |
5489 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5490 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5491 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5492 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5493 | |
5494 | /* Write 0 to parser credits for CFC search request */ | |
5495 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5496 | ||
5497 | /* send 10 Ethernet packets */ | |
5498 | for (i = 0; i < 10; i++) | |
5499 | bnx2x_lb_pckt(bp); | |
5500 | ||
5501 | /* Wait until NIG register shows 10 + 1 | |
5502 | packets of size 11*0x10 = 0xb0 */ | |
5503 | count = 1000 * factor; | |
5504 | while (count) { | |
34f80b04 | 5505 | |
a2fbb9ea ET |
5506 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5507 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5508 | if (val == 0xb0) |
5509 | break; | |
5510 | ||
5511 | msleep(10); | |
5512 | count--; | |
5513 | } | |
5514 | if (val != 0xb0) { | |
5515 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5516 | return -3; | |
5517 | } | |
5518 | ||
5519 | /* Wait until PRS register shows 2 packets */ | |
5520 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
5521 | if (val != 2) | |
5522 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5523 | ||
5524 | /* Write 1 to parser credits for CFC search request */ | |
5525 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
5526 | ||
5527 | /* Wait until PRS register shows 3 packets */ | |
5528 | msleep(10 * factor); | |
5529 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
5530 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
5531 | if (val != 3) | |
5532 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5533 | ||
5534 | /* clear NIG EOP FIFO */ | |
5535 | for (i = 0; i < 11; i++) | |
5536 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
5537 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
5538 | if (val != 1) { | |
5539 | BNX2X_ERR("clear of NIG failed\n"); | |
5540 | return -4; | |
5541 | } | |
5542 | ||
5543 | /* Reset and init BRB, PRS, NIG */ | |
5544 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
5545 | msleep(50); | |
5546 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
5547 | msleep(50); | |
619c5cb6 VZ |
5548 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
5549 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
37b091ba | 5550 | #ifndef BCM_CNIC |
a2fbb9ea ET |
5551 | /* set NIC mode */ |
5552 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
5553 | #endif | |
5554 | ||
5555 | /* Enable inputs of parser neighbor blocks */ | |
5556 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
5557 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
5558 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 5559 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
5560 | |
5561 | DP(NETIF_MSG_HW, "done\n"); | |
5562 | ||
5563 | return 0; /* OK */ | |
5564 | } | |
5565 | ||
4a33bc03 | 5566 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea ET |
5567 | { |
5568 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
619c5cb6 | 5569 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5570 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
5571 | else | |
5572 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
5573 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
5574 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
5575 | /* |
5576 | * mask read length error interrupts in brb for parser | |
5577 | * (parsing unit and 'checksum and crc' unit) | |
5578 | * these errors are legal (PU reads fixed length and CAC can cause | |
5579 | * read length error on truncated packets) | |
5580 | */ | |
5581 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
5582 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
5583 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
5584 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
5585 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
5586 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
5587 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
5588 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
5589 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
5590 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
5591 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
5592 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
5593 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
5594 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
5595 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
5596 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
5597 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
5598 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
5599 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 5600 | |
34f80b04 EG |
5601 | if (CHIP_REV_IS_FPGA(bp)) |
5602 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); | |
619c5cb6 | 5603 | else if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5604 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, |
5605 | (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | |
5606 | | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
5607 | | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN | |
5608 | | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | |
5609 | | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); | |
34f80b04 EG |
5610 | else |
5611 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); | |
a2fbb9ea ET |
5612 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
5613 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
5614 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 5615 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
5616 | |
5617 | if (!CHIP_IS_E1x(bp)) | |
5618 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
5619 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
5620 | ||
a2fbb9ea ET |
5621 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
5622 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 5623 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 5624 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
5625 | } |
5626 | ||
81f75bbf EG |
5627 | static void bnx2x_reset_common(struct bnx2x *bp) |
5628 | { | |
619c5cb6 VZ |
5629 | u32 val = 0x1400; |
5630 | ||
81f75bbf EG |
5631 | /* reset_common */ |
5632 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
5633 | 0xd3ffff7f); | |
619c5cb6 VZ |
5634 | |
5635 | if (CHIP_IS_E3(bp)) { | |
5636 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
5637 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
5638 | } | |
5639 | ||
5640 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
5641 | } | |
5642 | ||
5643 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
5644 | { | |
5645 | bp->dmae_ready = 0; | |
5646 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
5647 | } |
5648 | ||
573f2035 EG |
5649 | static void bnx2x_init_pxp(struct bnx2x *bp) |
5650 | { | |
5651 | u16 devctl; | |
5652 | int r_order, w_order; | |
5653 | ||
5654 | pci_read_config_word(bp->pdev, | |
b6c2f86e | 5655 | pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
5656 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
5657 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
5658 | if (bp->mrrs == -1) | |
5659 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
5660 | else { | |
5661 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
5662 | r_order = bp->mrrs; | |
5663 | } | |
5664 | ||
5665 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
5666 | } | |
fd4ef40d EG |
5667 | |
5668 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
5669 | { | |
2145a920 | 5670 | int is_required; |
fd4ef40d | 5671 | u32 val; |
2145a920 | 5672 | int port; |
fd4ef40d | 5673 | |
2145a920 VZ |
5674 | if (BP_NOMCP(bp)) |
5675 | return; | |
5676 | ||
5677 | is_required = 0; | |
fd4ef40d EG |
5678 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
5679 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
5680 | ||
5681 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
5682 | is_required = 1; | |
5683 | ||
5684 | /* | |
5685 | * The fan failure mechanism is usually related to the PHY type since | |
5686 | * the power consumption of the board is affected by the PHY. Currently, | |
5687 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
5688 | */ | |
5689 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
5690 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 5691 | is_required |= |
d90d96ba YR |
5692 | bnx2x_fan_failure_det_req( |
5693 | bp, | |
5694 | bp->common.shmem_base, | |
a22f0788 | 5695 | bp->common.shmem2_base, |
d90d96ba | 5696 | port); |
fd4ef40d EG |
5697 | } |
5698 | ||
5699 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
5700 | ||
5701 | if (is_required == 0) | |
5702 | return; | |
5703 | ||
5704 | /* Fan failure is indicated by SPIO 5 */ | |
5705 | bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, | |
5706 | MISC_REGISTERS_SPIO_INPUT_HI_Z); | |
5707 | ||
5708 | /* set to active low mode */ | |
5709 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
5710 | val |= ((1 << MISC_REGISTERS_SPIO_5) << | |
cdaa7cb8 | 5711 | MISC_REGISTERS_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
5712 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
5713 | ||
5714 | /* enable interrupt to signal the IGU */ | |
5715 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
5716 | val |= (1 << MISC_REGISTERS_SPIO_5); | |
5717 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); | |
5718 | } | |
5719 | ||
f2e0899f DK |
5720 | static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) |
5721 | { | |
5722 | u32 offset = 0; | |
5723 | ||
5724 | if (CHIP_IS_E1(bp)) | |
5725 | return; | |
5726 | if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) | |
5727 | return; | |
5728 | ||
5729 | switch (BP_ABS_FUNC(bp)) { | |
5730 | case 0: | |
5731 | offset = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
5732 | break; | |
5733 | case 1: | |
5734 | offset = PXP2_REG_PGL_PRETEND_FUNC_F1; | |
5735 | break; | |
5736 | case 2: | |
5737 | offset = PXP2_REG_PGL_PRETEND_FUNC_F2; | |
5738 | break; | |
5739 | case 3: | |
5740 | offset = PXP2_REG_PGL_PRETEND_FUNC_F3; | |
5741 | break; | |
5742 | case 4: | |
5743 | offset = PXP2_REG_PGL_PRETEND_FUNC_F4; | |
5744 | break; | |
5745 | case 5: | |
5746 | offset = PXP2_REG_PGL_PRETEND_FUNC_F5; | |
5747 | break; | |
5748 | case 6: | |
5749 | offset = PXP2_REG_PGL_PRETEND_FUNC_F6; | |
5750 | break; | |
5751 | case 7: | |
5752 | offset = PXP2_REG_PGL_PRETEND_FUNC_F7; | |
5753 | break; | |
5754 | default: | |
5755 | return; | |
5756 | } | |
5757 | ||
5758 | REG_WR(bp, offset, pretend_func_num); | |
5759 | REG_RD(bp, offset); | |
5760 | DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); | |
5761 | } | |
5762 | ||
c9ee9206 | 5763 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
5764 | { |
5765 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
5766 | val &= ~IGU_PF_CONF_FUNC_EN; | |
5767 | ||
5768 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
5769 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
5770 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
5771 | } | |
5772 | ||
619c5cb6 VZ |
5773 | static inline void bnx2x__common_init_phy(struct bnx2x *bp) |
5774 | { | |
5775 | u32 shmem_base[2], shmem2_base[2]; | |
5776 | shmem_base[0] = bp->common.shmem_base; | |
5777 | shmem2_base[0] = bp->common.shmem2_base; | |
5778 | if (!CHIP_IS_E1x(bp)) { | |
5779 | shmem_base[1] = | |
5780 | SHMEM2_RD(bp, other_shmem_base_addr); | |
5781 | shmem2_base[1] = | |
5782 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
5783 | } | |
5784 | bnx2x_acquire_phy_lock(bp); | |
5785 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
5786 | bp->common.chip_id); | |
5787 | bnx2x_release_phy_lock(bp); | |
5788 | } | |
5789 | ||
5790 | /** | |
5791 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
5792 | * | |
5793 | * @bp: driver handle | |
5794 | */ | |
5795 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 5796 | { |
619c5cb6 | 5797 | u32 val; |
a2fbb9ea | 5798 | |
f2e0899f | 5799 | DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 5800 | |
81f75bbf | 5801 | bnx2x_reset_common(bp); |
34f80b04 | 5802 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 5803 | |
619c5cb6 VZ |
5804 | val = 0xfffc; |
5805 | if (CHIP_IS_E3(bp)) { | |
5806 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
5807 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
5808 | } | |
5809 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
5810 | ||
5811 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); | |
a2fbb9ea | 5812 | |
619c5cb6 VZ |
5813 | if (!CHIP_IS_E1x(bp)) { |
5814 | u8 abs_func_id; | |
f2e0899f DK |
5815 | |
5816 | /** | |
5817 | * 4-port mode or 2-port mode we need to turn of master-enable | |
5818 | * for everyone, after that, turn it back on for self. | |
5819 | * so, we disregard multi-function or not, and always disable | |
5820 | * for all functions on the given path, this means 0,2,4,6 for | |
5821 | * path 0 and 1,3,5,7 for path 1 | |
5822 | */ | |
619c5cb6 VZ |
5823 | for (abs_func_id = BP_PATH(bp); |
5824 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
5825 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
5826 | REG_WR(bp, |
5827 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
5828 | 1); | |
5829 | continue; | |
5830 | } | |
5831 | ||
619c5cb6 | 5832 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
5833 | /* clear pf enable */ |
5834 | bnx2x_pf_disable(bp); | |
5835 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
5836 | } | |
5837 | } | |
a2fbb9ea | 5838 | |
619c5cb6 | 5839 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
5840 | if (CHIP_IS_E1(bp)) { |
5841 | /* enable HW interrupt from PXP on USDM overflow | |
5842 | bit 16 on INT_MASK_0 */ | |
5843 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
5844 | } | |
a2fbb9ea | 5845 | |
619c5cb6 | 5846 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 5847 | bnx2x_init_pxp(bp); |
a2fbb9ea ET |
5848 | |
5849 | #ifdef __BIG_ENDIAN | |
34f80b04 EG |
5850 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); |
5851 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); | |
5852 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); | |
5853 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); | |
5854 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); | |
8badd27a EG |
5855 | /* make sure this value is 0 */ |
5856 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
34f80b04 EG |
5857 | |
5858 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ | |
5859 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); | |
5860 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); | |
5861 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); | |
5862 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); | |
a2fbb9ea ET |
5863 | #endif |
5864 | ||
523224a3 DK |
5865 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
5866 | ||
34f80b04 EG |
5867 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
5868 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 5869 | |
34f80b04 EG |
5870 | /* let the HW do it's magic ... */ |
5871 | msleep(100); | |
5872 | /* finish PXP init */ | |
5873 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
5874 | if (val != 1) { | |
5875 | BNX2X_ERR("PXP2 CFG failed\n"); | |
5876 | return -EBUSY; | |
5877 | } | |
5878 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
5879 | if (val != 1) { | |
5880 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
5881 | return -EBUSY; | |
5882 | } | |
a2fbb9ea | 5883 | |
f2e0899f DK |
5884 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
5885 | * have entries with value "0" and valid bit on. | |
5886 | * This needs to be done by the first PF that is loaded in a path | |
5887 | * (i.e. common phase) | |
5888 | */ | |
619c5cb6 VZ |
5889 | if (!CHIP_IS_E1x(bp)) { |
5890 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
5891 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
5892 | * This occurs when a different function (func2,3) is being marked | |
5893 | * as "scan-off". Real-life scenario for example: if a driver is being | |
5894 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
5895 | * the ilt, translate to a logical address and send a request to read/write. | |
5896 | * Since the ilt for the function that is down is not valid, this will cause | |
5897 | * a translation error which is unrecoverable. | |
5898 | * The Workaround is intended to make sure that when this happens nothing fatal | |
5899 | * will occur. The workaround: | |
5900 | * 1. First PF driver which loads on a path will: | |
5901 | * a. After taking the chip out of reset, by using pretend, | |
5902 | * it will write "0" to the following registers of | |
5903 | * the other vnics. | |
5904 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
5905 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
5906 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
5907 | * And for itself it will write '1' to | |
5908 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
5909 | * dmae-operations (writing to pram for example.) | |
5910 | * note: can be done for only function 6,7 but cleaner this | |
5911 | * way. | |
5912 | * b. Write zero+valid to the entire ILT. | |
5913 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
5914 | * VNIC3 (of that port). The range allocated will be the | |
5915 | * entire ILT. This is needed to prevent ILT range error. | |
5916 | * 2. Any PF driver load flow: | |
5917 | * a. ILT update with the physical addresses of the allocated | |
5918 | * logical pages. | |
5919 | * b. Wait 20msec. - note that this timeout is needed to make | |
5920 | * sure there are no requests in one of the PXP internal | |
5921 | * queues with "old" ILT addresses. | |
5922 | * c. PF enable in the PGLC. | |
5923 | * d. Clear the was_error of the PF in the PGLC. (could have | |
5924 | * occured while driver was down) | |
5925 | * e. PF enable in the CFC (WEAK + STRONG) | |
5926 | * f. Timers scan enable | |
5927 | * 3. PF driver unload flow: | |
5928 | * a. Clear the Timers scan_en. | |
5929 | * b. Polling for scan_on=0 for that PF. | |
5930 | * c. Clear the PF enable bit in the PXP. | |
5931 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
5932 | * e. Write zero+valid to all ILT entries (The valid bit must | |
5933 | * stay set) | |
5934 | * f. If this is VNIC 3 of a port then also init | |
5935 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
5936 | * to the last enrty in the ILT. | |
5937 | * | |
5938 | * Notes: | |
5939 | * Currently the PF error in the PGLC is non recoverable. | |
5940 | * In the future the there will be a recovery routine for this error. | |
5941 | * Currently attention is masked. | |
5942 | * Having an MCP lock on the load/unload process does not guarantee that | |
5943 | * there is no Timer disable during Func6/7 enable. This is because the | |
5944 | * Timers scan is currently being cleared by the MCP on FLR. | |
5945 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
5946 | * there is error before clearing it. But the flow above is simpler and | |
5947 | * more general. | |
5948 | * All ILT entries are written by zero+valid and not just PF6/7 | |
5949 | * ILT entries since in the future the ILT entries allocation for | |
5950 | * PF-s might be dynamic. | |
5951 | */ | |
f2e0899f DK |
5952 | struct ilt_client_info ilt_cli; |
5953 | struct bnx2x_ilt ilt; | |
5954 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
5955 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
5956 | ||
b595076a | 5957 | /* initialize dummy TM client */ |
f2e0899f DK |
5958 | ilt_cli.start = 0; |
5959 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
5960 | ilt_cli.client_num = ILT_CLIENT_TM; | |
5961 | ||
5962 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
5963 | * Step 2: set the timers first/last ilt entry to point | |
5964 | * to the entire range to prevent ILT range error for 3rd/4th | |
619c5cb6 | 5965 | * vnic (this code assumes existance of the vnic) |
f2e0899f DK |
5966 | * |
5967 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
5968 | * with dummy TM client | |
5969 | * | |
5970 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
5971 | * and his brother are split registers | |
5972 | */ | |
5973 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
5974 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
5975 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
5976 | ||
5977 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
5978 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
5979 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
5980 | } | |
5981 | ||
5982 | ||
34f80b04 EG |
5983 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
5984 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 5985 | |
619c5cb6 | 5986 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5987 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
5988 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 5989 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 5990 | |
619c5cb6 | 5991 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
5992 | |
5993 | /* let the HW do it's magic ... */ | |
5994 | do { | |
5995 | msleep(200); | |
5996 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
5997 | } while (factor-- && (val != 1)); | |
5998 | ||
5999 | if (val != 1) { | |
6000 | BNX2X_ERR("ATC_INIT failed\n"); | |
6001 | return -EBUSY; | |
6002 | } | |
6003 | } | |
6004 | ||
619c5cb6 | 6005 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 6006 | |
34f80b04 EG |
6007 | /* clean the DMAE memory */ |
6008 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
6009 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
6010 | ||
6011 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
6012 | ||
6013 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
6014 | ||
6015 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 6016 | |
619c5cb6 | 6017 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 6018 | |
34f80b04 EG |
6019 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
6020 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
6021 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
6022 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
6023 | ||
619c5cb6 | 6024 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 6025 | |
f85582f8 | 6026 | |
523224a3 DK |
6027 | /* QM queues pointers table */ |
6028 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
6029 | ||
34f80b04 EG |
6030 | /* soft reset pulse */ |
6031 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
6032 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 6033 | |
37b091ba | 6034 | #ifdef BCM_CNIC |
619c5cb6 | 6035 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); |
a2fbb9ea | 6036 | #endif |
a2fbb9ea | 6037 | |
619c5cb6 | 6038 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
523224a3 | 6039 | REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); |
619c5cb6 | 6040 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
6041 | /* enable hw interrupt from doorbell Q */ |
6042 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 6043 | |
619c5cb6 | 6044 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 6045 | |
619c5cb6 | 6046 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 6047 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 6048 | |
f2e0899f | 6049 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 6050 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 6051 | |
619c5cb6 VZ |
6052 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) |
6053 | /* Bit-map indicating which L2 hdrs may appear | |
6054 | * after the basic Ethernet header | |
6055 | */ | |
6056 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
6057 | bp->path_has_ovlan ? 7 : 6); | |
a2fbb9ea | 6058 | |
619c5cb6 VZ |
6059 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
6060 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
6061 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
6062 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 6063 | |
619c5cb6 VZ |
6064 | if (!CHIP_IS_E1x(bp)) { |
6065 | /* reset VFC memories */ | |
6066 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6067 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6068 | VFC_MEMORIES_RST_REG_RAM_RST); | |
6069 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6070 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6071 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 6072 | |
619c5cb6 VZ |
6073 | msleep(20); |
6074 | } | |
a2fbb9ea | 6075 | |
619c5cb6 VZ |
6076 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
6077 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
6078 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
6079 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 6080 | |
34f80b04 EG |
6081 | /* sync semi rtc */ |
6082 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6083 | 0x80000000); | |
6084 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
6085 | 0x80000000); | |
a2fbb9ea | 6086 | |
619c5cb6 VZ |
6087 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
6088 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
6089 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 6090 | |
619c5cb6 VZ |
6091 | if (!CHIP_IS_E1x(bp)) |
6092 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
6093 | bp->path_has_ovlan ? 7 : 6); | |
f2e0899f | 6094 | |
34f80b04 | 6095 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 6096 | |
619c5cb6 VZ |
6097 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
6098 | ||
37b091ba MC |
6099 | #ifdef BCM_CNIC |
6100 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
6101 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
6102 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
6103 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
6104 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
6105 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
6106 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
6107 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
6108 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
6109 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
6110 | #endif | |
34f80b04 | 6111 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 6112 | |
34f80b04 EG |
6113 | if (sizeof(union cdu_context) != 1024) |
6114 | /* we currently assume that a context is 1024 bytes */ | |
cdaa7cb8 VZ |
6115 | dev_alert(&bp->pdev->dev, "please adjust the size " |
6116 | "of cdu_context(%ld)\n", | |
7995c64e | 6117 | (long)sizeof(union cdu_context)); |
a2fbb9ea | 6118 | |
619c5cb6 | 6119 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
6120 | val = (4 << 24) + (0 << 12) + 1024; |
6121 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 6122 | |
619c5cb6 | 6123 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 6124 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
6125 | /* enable context validation interrupt from CFC */ |
6126 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
6127 | ||
6128 | /* set the thresholds to prevent CFC/CDU race */ | |
6129 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 6130 | |
619c5cb6 | 6131 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 6132 | |
619c5cb6 | 6133 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
6134 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
6135 | ||
619c5cb6 VZ |
6136 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
6137 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 6138 | |
34f80b04 EG |
6139 | /* Reset PCIE errors for debug */ |
6140 | REG_WR(bp, 0x2814, 0xffffffff); | |
6141 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 6142 | |
619c5cb6 | 6143 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6144 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
6145 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
6146 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
6147 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
6148 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
6149 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
6150 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
6151 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
6152 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
6153 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
6154 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
6155 | } | |
6156 | ||
619c5cb6 | 6157 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 6158 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
6159 | /* in E3 this done in per-port section */ |
6160 | if (!CHIP_IS_E3(bp)) | |
6161 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 6162 | } |
619c5cb6 VZ |
6163 | if (CHIP_IS_E1H(bp)) |
6164 | /* not applicable for E2 (and above ...) */ | |
6165 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
6166 | |
6167 | if (CHIP_REV_IS_SLOW(bp)) | |
6168 | msleep(200); | |
6169 | ||
6170 | /* finish CFC init */ | |
6171 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
6172 | if (val != 1) { | |
6173 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
6174 | return -EBUSY; | |
6175 | } | |
6176 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
6177 | if (val != 1) { | |
6178 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
6179 | return -EBUSY; | |
6180 | } | |
6181 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
6182 | if (val != 1) { | |
6183 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
6184 | return -EBUSY; | |
6185 | } | |
6186 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 6187 | |
f2e0899f DK |
6188 | if (CHIP_IS_E1(bp)) { |
6189 | /* read NIG statistic | |
6190 | to see if this is our first up since powerup */ | |
6191 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
6192 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 6193 | |
f2e0899f DK |
6194 | /* do internal memory self test */ |
6195 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
6196 | BNX2X_ERR("internal mem self test failed\n"); | |
6197 | return -EBUSY; | |
6198 | } | |
34f80b04 EG |
6199 | } |
6200 | ||
fd4ef40d EG |
6201 | bnx2x_setup_fan_failure_detection(bp); |
6202 | ||
34f80b04 EG |
6203 | /* clear PXP2 attentions */ |
6204 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 6205 | |
4a33bc03 | 6206 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 6207 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 6208 | |
6bbca910 | 6209 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
6210 | if (CHIP_IS_E1x(bp)) |
6211 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
6212 | } else |
6213 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
6214 | ||
34f80b04 EG |
6215 | return 0; |
6216 | } | |
a2fbb9ea | 6217 | |
619c5cb6 VZ |
6218 | /** |
6219 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
6220 | * | |
6221 | * @bp: driver handle | |
6222 | */ | |
6223 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
6224 | { | |
6225 | int rc = bnx2x_init_hw_common(bp); | |
6226 | ||
6227 | if (rc) | |
6228 | return rc; | |
6229 | ||
6230 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
6231 | if (!BP_NOMCP(bp)) | |
6232 | bnx2x__common_init_phy(bp); | |
6233 | ||
6234 | return 0; | |
6235 | } | |
6236 | ||
523224a3 | 6237 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
6238 | { |
6239 | int port = BP_PORT(bp); | |
619c5cb6 | 6240 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 6241 | u32 low, high; |
34f80b04 | 6242 | u32 val; |
a2fbb9ea | 6243 | |
619c5cb6 VZ |
6244 | bnx2x__link_reset(bp); |
6245 | ||
cdaa7cb8 | 6246 | DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); |
34f80b04 EG |
6247 | |
6248 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 6249 | |
619c5cb6 VZ |
6250 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
6251 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
6252 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 6253 | |
f2e0899f DK |
6254 | /* Timers bug workaround: disables the pf_master bit in pglue at |
6255 | * common phase, we need to enable it here before any dmae access are | |
6256 | * attempted. Therefore we manually added the enable-master to the | |
6257 | * port phase (it also happens in the function phase) | |
6258 | */ | |
619c5cb6 | 6259 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6260 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
6261 | ||
619c5cb6 VZ |
6262 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6263 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6264 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
6265 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6266 | ||
6267 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6268 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6269 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6270 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 6271 | |
523224a3 DK |
6272 | /* QM cid (connection) count */ |
6273 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 6274 | |
523224a3 | 6275 | #ifdef BCM_CNIC |
619c5cb6 | 6276 | bnx2x_init_block(bp, BLOCK_TM, init_phase); |
37b091ba MC |
6277 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); |
6278 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
a2fbb9ea | 6279 | #endif |
cdaa7cb8 | 6280 | |
619c5cb6 | 6281 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f DK |
6282 | |
6283 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { | |
619c5cb6 VZ |
6284 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
6285 | ||
6286 | if (IS_MF(bp)) | |
6287 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
6288 | else if (bp->dev->mtu > 4096) { | |
6289 | if (bp->flags & ONE_PORT_FLAG) | |
6290 | low = 160; | |
6291 | else { | |
6292 | val = bp->dev->mtu; | |
6293 | /* (24*1024 + val*4)/256 */ | |
6294 | low = 96 + (val/64) + | |
6295 | ((val % 64) ? 1 : 0); | |
6296 | } | |
6297 | } else | |
6298 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
6299 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
6300 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
6301 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 6302 | } |
1c06328c | 6303 | |
619c5cb6 VZ |
6304 | if (CHIP_MODE_IS_4_PORT(bp)) |
6305 | REG_WR(bp, (BP_PORT(bp) ? | |
6306 | BRB1_REG_MAC_GUARANTIED_1 : | |
6307 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 6308 | |
ca00392c | 6309 | |
619c5cb6 VZ |
6310 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
6311 | if (CHIP_IS_E3B0(bp)) | |
6312 | /* Ovlan exists only if we are in multi-function + | |
6313 | * switch-dependent mode, in switch-independent there | |
6314 | * is no ovlan headers | |
6315 | */ | |
6316 | REG_WR(bp, BP_PORT(bp) ? | |
6317 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
6318 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
6319 | (bp->path_has_ovlan ? 7 : 6)); | |
356e2385 | 6320 | |
619c5cb6 VZ |
6321 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
6322 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
6323 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
6324 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 6325 | |
619c5cb6 VZ |
6326 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
6327 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6328 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6329 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 6330 | |
619c5cb6 VZ |
6331 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
6332 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 6333 | |
619c5cb6 VZ |
6334 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
6335 | ||
6336 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
6337 | /* configure PBF to work without PAUSE mtu 9000 */ |
6338 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 6339 | |
f2e0899f DK |
6340 | /* update threshold */ |
6341 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
6342 | /* update init credit */ | |
6343 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 6344 | |
f2e0899f DK |
6345 | /* probe changes */ |
6346 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
6347 | udelay(50); | |
6348 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
6349 | } | |
a2fbb9ea | 6350 | |
37b091ba | 6351 | #ifdef BCM_CNIC |
619c5cb6 | 6352 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); |
a2fbb9ea | 6353 | #endif |
619c5cb6 VZ |
6354 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
6355 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
6356 | |
6357 | if (CHIP_IS_E1(bp)) { | |
6358 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
6359 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
6360 | } | |
619c5cb6 | 6361 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 6362 | |
619c5cb6 | 6363 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 6364 | |
619c5cb6 | 6365 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 EG |
6366 | /* init aeu_mask_attn_func_0/1: |
6367 | * - SF mode: bits 3-7 are masked. only bits 0-2 are in use | |
6368 | * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF | |
6369 | * bits 4-7 are used for "per vn group attention" */ | |
e4901dde VZ |
6370 | val = IS_MF(bp) ? 0xF7 : 0x7; |
6371 | /* Enable DCBX attention for all but E1 */ | |
6372 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
6373 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 6374 | |
619c5cb6 VZ |
6375 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
6376 | ||
6377 | if (!CHIP_IS_E1x(bp)) { | |
6378 | /* Bit-map indicating which L2 hdrs may appear after the | |
6379 | * basic Ethernet header | |
6380 | */ | |
6381 | REG_WR(bp, BP_PORT(bp) ? | |
6382 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
6383 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
6384 | IS_MF_SD(bp) ? 7 : 6); | |
6385 | ||
6386 | if (CHIP_IS_E3(bp)) | |
6387 | REG_WR(bp, BP_PORT(bp) ? | |
6388 | NIG_REG_LLH1_MF_MODE : | |
6389 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
6390 | } | |
6391 | if (!CHIP_IS_E3(bp)) | |
6392 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 6393 | |
f2e0899f | 6394 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 6395 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 6396 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 6397 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 6398 | |
619c5cb6 | 6399 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6400 | val = 0; |
6401 | switch (bp->mf_mode) { | |
6402 | case MULTI_FUNCTION_SD: | |
6403 | val = 1; | |
6404 | break; | |
6405 | case MULTI_FUNCTION_SI: | |
6406 | val = 2; | |
6407 | break; | |
6408 | } | |
6409 | ||
6410 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
6411 | NIG_REG_LLH0_CLS_TYPE), val); | |
6412 | } | |
1c06328c EG |
6413 | { |
6414 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
6415 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
6416 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
6417 | } | |
34f80b04 EG |
6418 | } |
6419 | ||
619c5cb6 VZ |
6420 | |
6421 | /* If SPIO5 is set to generate interrupts, enable it for this port */ | |
6422 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
6423 | if (val & (1 << MISC_REGISTERS_SPIO_5)) { | |
4d295db0 EG |
6424 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
6425 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
6426 | val = REG_RD(bp, reg_addr); | |
f1410647 | 6427 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 6428 | REG_WR(bp, reg_addr, val); |
f1410647 | 6429 | } |
a2fbb9ea | 6430 | |
34f80b04 EG |
6431 | return 0; |
6432 | } | |
6433 | ||
34f80b04 EG |
6434 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
6435 | { | |
6436 | int reg; | |
6437 | ||
f2e0899f | 6438 | if (CHIP_IS_E1(bp)) |
34f80b04 | 6439 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
6440 | else |
6441 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 EG |
6442 | |
6443 | bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); | |
6444 | } | |
6445 | ||
f2e0899f DK |
6446 | static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) |
6447 | { | |
619c5cb6 | 6448 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
6449 | } |
6450 | ||
6451 | static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) | |
6452 | { | |
6453 | u32 i, base = FUNC_ILT_BASE(func); | |
6454 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
6455 | bnx2x_ilt_wr(bp, i, 0); | |
6456 | } | |
6457 | ||
523224a3 | 6458 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
6459 | { |
6460 | int port = BP_PORT(bp); | |
6461 | int func = BP_FUNC(bp); | |
619c5cb6 | 6462 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
6463 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
6464 | u16 cdu_ilt_start; | |
8badd27a | 6465 | u32 addr, val; |
f4a66897 VZ |
6466 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
6467 | int i, main_mem_width; | |
34f80b04 | 6468 | |
cdaa7cb8 | 6469 | DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); |
34f80b04 | 6470 | |
619c5cb6 VZ |
6471 | /* FLR cleanup - hmmm */ |
6472 | if (!CHIP_IS_E1x(bp)) | |
6473 | bnx2x_pf_flr_clnup(bp); | |
6474 | ||
8badd27a | 6475 | /* set MSI reconfigure capability */ |
f2e0899f DK |
6476 | if (bp->common.int_block == INT_BLOCK_HC) { |
6477 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
6478 | val = REG_RD(bp, addr); | |
6479 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
6480 | REG_WR(bp, addr, val); | |
6481 | } | |
8badd27a | 6482 | |
619c5cb6 VZ |
6483 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
6484 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
6485 | ||
523224a3 DK |
6486 | ilt = BP_ILT(bp); |
6487 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 6488 | |
523224a3 DK |
6489 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
6490 | ilt->lines[cdu_ilt_start + i].page = | |
6491 | bp->context.vcxt + (ILT_PAGE_CIDS * i); | |
6492 | ilt->lines[cdu_ilt_start + i].page_mapping = | |
6493 | bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); | |
6494 | /* cdu ilt pages are allocated manually so there's no need to | |
6495 | set the size */ | |
37b091ba | 6496 | } |
523224a3 | 6497 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 6498 | |
523224a3 DK |
6499 | #ifdef BCM_CNIC |
6500 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
37b091ba | 6501 | |
523224a3 DK |
6502 | /* T1 hash bits value determines the T1 number of entries */ |
6503 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
6504 | #endif | |
37b091ba | 6505 | |
523224a3 DK |
6506 | #ifndef BCM_CNIC |
6507 | /* set NIC mode */ | |
6508 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6509 | #endif /* BCM_CNIC */ | |
37b091ba | 6510 | |
619c5cb6 | 6511 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6512 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
6513 | ||
6514 | /* Turn on a single ISR mode in IGU if driver is going to use | |
6515 | * INT#x or MSI | |
6516 | */ | |
6517 | if (!(bp->flags & USING_MSIX_FLAG)) | |
6518 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
6519 | /* | |
6520 | * Timers workaround bug: function init part. | |
6521 | * Need to wait 20msec after initializing ILT, | |
6522 | * needed to make sure there are no requests in | |
6523 | * one of the PXP internal queues with "old" ILT addresses | |
6524 | */ | |
6525 | msleep(20); | |
6526 | /* | |
6527 | * Master enable - Due to WB DMAE writes performed before this | |
6528 | * register is re-initialized as part of the regular function | |
6529 | * init | |
6530 | */ | |
6531 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
6532 | /* Enable the function in IGU */ | |
6533 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
6534 | } | |
6535 | ||
523224a3 | 6536 | bp->dmae_ready = 1; |
34f80b04 | 6537 | |
619c5cb6 | 6538 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 6539 | |
619c5cb6 | 6540 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6541 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); |
6542 | ||
619c5cb6 VZ |
6543 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6544 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6545 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
6546 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
6547 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
6548 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6549 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6550 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6551 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
6552 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
6553 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6554 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6555 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
6556 | ||
6557 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
6558 | REG_WR(bp, QM_REG_PF_EN, 1); |
6559 | ||
619c5cb6 VZ |
6560 | if (!CHIP_IS_E1x(bp)) { |
6561 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6562 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6563 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6564 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6565 | } | |
6566 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6567 | ||
6568 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
6569 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
6570 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); | |
6571 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
6572 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
6573 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
6574 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
6575 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
6576 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
6577 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
6578 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
6579 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
6580 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
6581 | ||
619c5cb6 | 6582 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 6583 | |
619c5cb6 | 6584 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 6585 | |
619c5cb6 | 6586 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6587 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
6588 | ||
fb3bff17 | 6589 | if (IS_MF(bp)) { |
34f80b04 | 6590 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
fb3bff17 | 6591 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
34f80b04 EG |
6592 | } |
6593 | ||
619c5cb6 | 6594 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 6595 | |
34f80b04 | 6596 | /* HC init per function */ |
f2e0899f DK |
6597 | if (bp->common.int_block == INT_BLOCK_HC) { |
6598 | if (CHIP_IS_E1H(bp)) { | |
6599 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
6600 | ||
6601 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
6602 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
6603 | } | |
619c5cb6 | 6604 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
6605 | |
6606 | } else { | |
6607 | int num_segs, sb_idx, prod_offset; | |
6608 | ||
34f80b04 EG |
6609 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
6610 | ||
619c5cb6 | 6611 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6612 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
6613 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
6614 | } | |
6615 | ||
619c5cb6 | 6616 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 6617 | |
619c5cb6 | 6618 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6619 | int dsb_idx = 0; |
6620 | /** | |
6621 | * Producer memory: | |
6622 | * E2 mode: address 0-135 match to the mapping memory; | |
6623 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
6624 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
6625 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
6626 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
6627 | * 144-147 reserved. | |
6628 | * | |
6629 | * E1.5 mode - In backward compatible mode; | |
6630 | * for non default SB; each even line in the memory | |
6631 | * holds the U producer and each odd line hold | |
6632 | * the C producer. The first 128 producers are for | |
6633 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
6634 | * producers are for the DSB for each PF. | |
6635 | * Each PF has five segments: (the order inside each | |
6636 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
6637 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
6638 | * 144-147 attn prods; | |
6639 | */ | |
6640 | /* non-default-status-blocks */ | |
6641 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
6642 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
6643 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
6644 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
6645 | num_segs; | |
6646 | ||
6647 | for (i = 0; i < num_segs; i++) { | |
6648 | addr = IGU_REG_PROD_CONS_MEMORY + | |
6649 | (prod_offset + i) * 4; | |
6650 | REG_WR(bp, addr, 0); | |
6651 | } | |
6652 | /* send consumer update with value 0 */ | |
6653 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
6654 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
6655 | bnx2x_igu_clear_sb(bp, | |
6656 | bp->igu_base_sb + sb_idx); | |
6657 | } | |
6658 | ||
6659 | /* default-status-blocks */ | |
6660 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
6661 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
6662 | ||
6663 | if (CHIP_MODE_IS_4_PORT(bp)) | |
6664 | dsb_idx = BP_FUNC(bp); | |
6665 | else | |
6666 | dsb_idx = BP_E1HVN(bp); | |
6667 | ||
6668 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
6669 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
6670 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
6671 | ||
6672 | for (i = 0; i < (num_segs * E1HVN_MAX); | |
6673 | i += E1HVN_MAX) { | |
6674 | addr = IGU_REG_PROD_CONS_MEMORY + | |
6675 | (prod_offset + i)*4; | |
6676 | REG_WR(bp, addr, 0); | |
6677 | } | |
6678 | /* send consumer update with 0 */ | |
6679 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
6680 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6681 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
6682 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6683 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
6684 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6685 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
6686 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6687 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
6688 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6689 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
6690 | } else { | |
6691 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6692 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
6693 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6694 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
6695 | } | |
6696 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
6697 | ||
6698 | /* !!! these should become driver const once | |
6699 | rf-tool supports split-68 const */ | |
6700 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
6701 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
6702 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
6703 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
6704 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
6705 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
6706 | } | |
34f80b04 | 6707 | } |
34f80b04 | 6708 | |
c14423fe | 6709 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
6710 | REG_WR(bp, 0x2114, 0xffffffff); |
6711 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 6712 | |
f4a66897 VZ |
6713 | if (CHIP_IS_E1x(bp)) { |
6714 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
6715 | main_mem_base = HC_REG_MAIN_MEMORY + | |
6716 | BP_PORT(bp) * (main_mem_size * 4); | |
6717 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
6718 | main_mem_width = 8; | |
6719 | ||
6720 | val = REG_RD(bp, main_mem_prty_clr); | |
6721 | if (val) | |
6722 | DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " | |
6723 | "block during " | |
6724 | "function init (0x%x)!\n", val); | |
6725 | ||
6726 | /* Clear "false" parity errors in MSI-X table */ | |
6727 | for (i = main_mem_base; | |
6728 | i < main_mem_base + main_mem_size * 4; | |
6729 | i += main_mem_width) { | |
6730 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
6731 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
6732 | i, main_mem_width / 4); | |
6733 | } | |
6734 | /* Clear HC parity attention */ | |
6735 | REG_RD(bp, main_mem_prty_clr); | |
6736 | } | |
6737 | ||
619c5cb6 VZ |
6738 | #ifdef BNX2X_STOP_ON_ERROR |
6739 | /* Enable STORMs SP logging */ | |
6740 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
6741 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6742 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
6743 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6744 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
6745 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6746 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
6747 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6748 | #endif | |
6749 | ||
b7737c9b | 6750 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 6751 | |
34f80b04 EG |
6752 | return 0; |
6753 | } | |
6754 | ||
a2fbb9ea | 6755 | |
9f6c9258 | 6756 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 6757 | { |
a2fbb9ea | 6758 | /* fastpath */ |
b3b83c3f | 6759 | bnx2x_free_fp_mem(bp); |
a2fbb9ea ET |
6760 | /* end of fastpath */ |
6761 | ||
6762 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
523224a3 | 6763 | sizeof(struct host_sp_status_block)); |
a2fbb9ea | 6764 | |
619c5cb6 VZ |
6765 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
6766 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
6767 | ||
a2fbb9ea | 6768 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 6769 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 6770 | |
523224a3 DK |
6771 | BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, |
6772 | bp->context.size); | |
6773 | ||
6774 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); | |
6775 | ||
6776 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 6777 | |
37b091ba | 6778 | #ifdef BCM_CNIC |
619c5cb6 | 6779 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6780 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, |
6781 | sizeof(struct host_hc_status_block_e2)); | |
6782 | else | |
6783 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
6784 | sizeof(struct host_hc_status_block_e1x)); | |
f85582f8 | 6785 | |
523224a3 | 6786 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
a2fbb9ea | 6787 | #endif |
f85582f8 | 6788 | |
7a9b2557 | 6789 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 6790 | |
523224a3 DK |
6791 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
6792 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
619c5cb6 VZ |
6793 | } |
6794 | ||
6795 | static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) | |
6796 | { | |
6797 | int num_groups; | |
6798 | ||
6799 | /* number of eth_queues */ | |
6800 | u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp); | |
6801 | ||
6802 | /* Total number of FW statistics requests = | |
6803 | * 1 for port stats + 1 for PF stats + num_eth_queues */ | |
6804 | bp->fw_stats_num = 2 + num_queue_stats; | |
523224a3 | 6805 | |
619c5cb6 VZ |
6806 | |
6807 | /* Request is built from stats_query_header and an array of | |
6808 | * stats_query_cmd_group each of which contains | |
6809 | * STATS_QUERY_CMD_COUNT rules. The real number or requests is | |
6810 | * configured in the stats_query_header. | |
6811 | */ | |
6812 | num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT + | |
6813 | (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0); | |
6814 | ||
6815 | bp->fw_stats_req_sz = sizeof(struct stats_query_header) + | |
6816 | num_groups * sizeof(struct stats_query_cmd_group); | |
6817 | ||
6818 | /* Data for statistics requests + stats_conter | |
6819 | * | |
6820 | * stats_counter holds per-STORM counters that are incremented | |
6821 | * when STORM has finished with the current request. | |
6822 | */ | |
6823 | bp->fw_stats_data_sz = sizeof(struct per_port_stats) + | |
6824 | sizeof(struct per_pf_stats) + | |
6825 | sizeof(struct per_queue_stats) * num_queue_stats + | |
6826 | sizeof(struct stats_counter); | |
6827 | ||
6828 | BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, | |
6829 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
6830 | ||
6831 | /* Set shortcuts */ | |
6832 | bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; | |
6833 | bp->fw_stats_req_mapping = bp->fw_stats_mapping; | |
6834 | ||
6835 | bp->fw_stats_data = (struct bnx2x_fw_stats_data *) | |
6836 | ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); | |
6837 | ||
6838 | bp->fw_stats_data_mapping = bp->fw_stats_mapping + | |
6839 | bp->fw_stats_req_sz; | |
6840 | return 0; | |
6841 | ||
6842 | alloc_mem_err: | |
6843 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, | |
6844 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
6845 | return -ENOMEM; | |
a2fbb9ea ET |
6846 | } |
6847 | ||
f2e0899f | 6848 | |
9f6c9258 | 6849 | int bnx2x_alloc_mem(struct bnx2x *bp) |
a2fbb9ea | 6850 | { |
523224a3 | 6851 | #ifdef BCM_CNIC |
619c5cb6 VZ |
6852 | if (!CHIP_IS_E1x(bp)) |
6853 | /* size = the status block + ramrod buffers */ | |
f2e0899f DK |
6854 | BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, |
6855 | sizeof(struct host_hc_status_block_e2)); | |
6856 | else | |
6857 | BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, | |
6858 | sizeof(struct host_hc_status_block_e1x)); | |
8badd27a | 6859 | |
523224a3 DK |
6860 | /* allocate searcher T2 table */ |
6861 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
6862 | #endif | |
a2fbb9ea | 6863 | |
8badd27a | 6864 | |
523224a3 DK |
6865 | BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, |
6866 | sizeof(struct host_sp_status_block)); | |
a2fbb9ea | 6867 | |
523224a3 DK |
6868 | BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, |
6869 | sizeof(struct bnx2x_slowpath)); | |
a2fbb9ea | 6870 | |
619c5cb6 VZ |
6871 | /* Allocated memory for FW statistics */ |
6872 | if (bnx2x_alloc_fw_stats_mem(bp)) | |
6873 | goto alloc_mem_err; | |
6874 | ||
6383c0b3 | 6875 | bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); |
f85582f8 | 6876 | |
523224a3 DK |
6877 | BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, |
6878 | bp->context.size); | |
65abd74d | 6879 | |
523224a3 | 6880 | BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); |
65abd74d | 6881 | |
523224a3 DK |
6882 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
6883 | goto alloc_mem_err; | |
65abd74d | 6884 | |
9f6c9258 DK |
6885 | /* Slow path ring */ |
6886 | BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); | |
65abd74d | 6887 | |
523224a3 DK |
6888 | /* EQ */ |
6889 | BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, | |
6890 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
ab532cf3 | 6891 | |
b3b83c3f DK |
6892 | |
6893 | /* fastpath */ | |
6894 | /* need to be done at the end, since it's self adjusting to amount | |
6895 | * of memory available for RSS queues | |
6896 | */ | |
6897 | if (bnx2x_alloc_fp_mem(bp)) | |
6898 | goto alloc_mem_err; | |
9f6c9258 | 6899 | return 0; |
e1510706 | 6900 | |
9f6c9258 DK |
6901 | alloc_mem_err: |
6902 | bnx2x_free_mem(bp); | |
6903 | return -ENOMEM; | |
65abd74d YG |
6904 | } |
6905 | ||
a2fbb9ea ET |
6906 | /* |
6907 | * Init service functions | |
6908 | */ | |
a2fbb9ea | 6909 | |
619c5cb6 VZ |
6910 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
6911 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
6912 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 6913 | { |
619c5cb6 VZ |
6914 | int rc; |
6915 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 6916 | |
619c5cb6 | 6917 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 6918 | |
619c5cb6 VZ |
6919 | /* Fill general parameters */ |
6920 | ramrod_param.vlan_mac_obj = obj; | |
6921 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 6922 | |
619c5cb6 VZ |
6923 | /* Fill a user request section if needed */ |
6924 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
6925 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 6926 | |
619c5cb6 | 6927 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 6928 | |
619c5cb6 VZ |
6929 | /* Set the command: ADD or DEL */ |
6930 | if (set) | |
6931 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
6932 | else | |
6933 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
6934 | } |
6935 | ||
619c5cb6 VZ |
6936 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
6937 | if (rc < 0) | |
6938 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); | |
6939 | return rc; | |
a2fbb9ea ET |
6940 | } |
6941 | ||
619c5cb6 VZ |
6942 | int bnx2x_del_all_macs(struct bnx2x *bp, |
6943 | struct bnx2x_vlan_mac_obj *mac_obj, | |
6944 | int mac_type, bool wait_for_comp) | |
e665bfda | 6945 | { |
619c5cb6 VZ |
6946 | int rc; |
6947 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 6948 | |
619c5cb6 VZ |
6949 | /* Wait for completion of requested */ |
6950 | if (wait_for_comp) | |
6951 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 6952 | |
619c5cb6 VZ |
6953 | /* Set the mac type of addresses we want to clear */ |
6954 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 6955 | |
619c5cb6 VZ |
6956 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
6957 | if (rc < 0) | |
6958 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 6959 | |
619c5cb6 | 6960 | return rc; |
0793f83f DK |
6961 | } |
6962 | ||
619c5cb6 | 6963 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 6964 | { |
619c5cb6 | 6965 | unsigned long ramrod_flags = 0; |
e665bfda | 6966 | |
619c5cb6 | 6967 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
0793f83f | 6968 | |
619c5cb6 VZ |
6969 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
6970 | /* Eth MAC is set on RSS leading client (fp[0]) */ | |
6971 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, | |
6972 | BNX2X_ETH_MAC, &ramrod_flags); | |
e665bfda | 6973 | } |
6e30dd4e | 6974 | |
619c5cb6 | 6975 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 6976 | { |
619c5cb6 | 6977 | return bnx2x_setup_queue(bp, &bp->fp[0], 1); |
993ac7b5 | 6978 | } |
a2fbb9ea | 6979 | |
d6214d7a | 6980 | /** |
e8920674 | 6981 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 6982 | * |
e8920674 | 6983 | * @bp: driver handle |
d6214d7a | 6984 | * |
e8920674 | 6985 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 6986 | */ |
9ee3d37b | 6987 | static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 6988 | { |
9ee3d37b | 6989 | switch (int_mode) { |
d6214d7a DK |
6990 | case INT_MODE_MSI: |
6991 | bnx2x_enable_msi(bp); | |
6992 | /* falling through... */ | |
6993 | case INT_MODE_INTx: | |
6383c0b3 | 6994 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; |
d6214d7a | 6995 | DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); |
ca00392c | 6996 | break; |
d6214d7a DK |
6997 | default: |
6998 | /* Set number of queues according to bp->multi_mode value */ | |
6999 | bnx2x_set_num_queues(bp); | |
ca00392c | 7000 | |
d6214d7a DK |
7001 | DP(NETIF_MSG_IFUP, "set number of queues to %d\n", |
7002 | bp->num_queues); | |
ca00392c | 7003 | |
d6214d7a DK |
7004 | /* if we can't use MSI-X we only need one fp, |
7005 | * so try to enable MSI-X with the requested number of fp's | |
7006 | * and fallback to MSI or legacy INTx with one fp | |
7007 | */ | |
9ee3d37b | 7008 | if (bnx2x_enable_msix(bp)) { |
d6214d7a DK |
7009 | /* failed to enable MSI-X */ |
7010 | if (bp->multi_mode) | |
7011 | DP(NETIF_MSG_IFUP, | |
7012 | "Multi requested but failed to " | |
7013 | "enable MSI-X (%d), " | |
7014 | "set number of queues to %d\n", | |
7015 | bp->num_queues, | |
6383c0b3 AE |
7016 | 1 + NON_ETH_CONTEXT_USE); |
7017 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; | |
d6214d7a | 7018 | |
9ee3d37b | 7019 | /* Try to enable MSI */ |
d6214d7a DK |
7020 | if (!(bp->flags & DISABLE_MSI_FLAG)) |
7021 | bnx2x_enable_msi(bp); | |
7022 | } | |
9f6c9258 DK |
7023 | break; |
7024 | } | |
a2fbb9ea ET |
7025 | } |
7026 | ||
c2bff63f DK |
7027 | /* must be called prioir to any HW initializations */ |
7028 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) | |
7029 | { | |
7030 | return L2_ILT_LINES(bp); | |
7031 | } | |
7032 | ||
523224a3 DK |
7033 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
7034 | { | |
7035 | struct ilt_client_info *ilt_client; | |
7036 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
7037 | u16 line = 0; | |
7038 | ||
7039 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
7040 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
7041 | ||
7042 | /* CDU */ | |
7043 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
7044 | ilt_client->client_num = ILT_CLIENT_CDU; | |
7045 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
7046 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
7047 | ilt_client->start = line; | |
619c5cb6 | 7048 | line += bnx2x_cid_ilt_lines(bp); |
523224a3 DK |
7049 | #ifdef BCM_CNIC |
7050 | line += CNIC_ILT_LINES; | |
7051 | #endif | |
7052 | ilt_client->end = line - 1; | |
7053 | ||
7054 | DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " | |
7055 | "flags 0x%x, hw psz %d\n", | |
7056 | ilt_client->start, | |
7057 | ilt_client->end, | |
7058 | ilt_client->page_size, | |
7059 | ilt_client->flags, | |
7060 | ilog2(ilt_client->page_size >> 12)); | |
7061 | ||
7062 | /* QM */ | |
7063 | if (QM_INIT(bp->qm_cid_count)) { | |
7064 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
7065 | ilt_client->client_num = ILT_CLIENT_QM; | |
7066 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
7067 | ilt_client->flags = 0; | |
7068 | ilt_client->start = line; | |
7069 | ||
7070 | /* 4 bytes for each cid */ | |
7071 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
7072 | QM_ILT_PAGE_SZ); | |
7073 | ||
7074 | ilt_client->end = line - 1; | |
7075 | ||
7076 | DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " | |
7077 | "flags 0x%x, hw psz %d\n", | |
7078 | ilt_client->start, | |
7079 | ilt_client->end, | |
7080 | ilt_client->page_size, | |
7081 | ilt_client->flags, | |
7082 | ilog2(ilt_client->page_size >> 12)); | |
7083 | ||
7084 | } | |
7085 | /* SRC */ | |
7086 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
7087 | #ifdef BCM_CNIC | |
7088 | ilt_client->client_num = ILT_CLIENT_SRC; | |
7089 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
7090 | ilt_client->flags = 0; | |
7091 | ilt_client->start = line; | |
7092 | line += SRC_ILT_LINES; | |
7093 | ilt_client->end = line - 1; | |
7094 | ||
7095 | DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " | |
7096 | "flags 0x%x, hw psz %d\n", | |
7097 | ilt_client->start, | |
7098 | ilt_client->end, | |
7099 | ilt_client->page_size, | |
7100 | ilt_client->flags, | |
7101 | ilog2(ilt_client->page_size >> 12)); | |
7102 | ||
7103 | #else | |
7104 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7105 | #endif | |
9f6c9258 | 7106 | |
523224a3 DK |
7107 | /* TM */ |
7108 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
7109 | #ifdef BCM_CNIC | |
7110 | ilt_client->client_num = ILT_CLIENT_TM; | |
7111 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
7112 | ilt_client->flags = 0; | |
7113 | ilt_client->start = line; | |
7114 | line += TM_ILT_LINES; | |
7115 | ilt_client->end = line - 1; | |
7116 | ||
7117 | DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " | |
7118 | "flags 0x%x, hw psz %d\n", | |
7119 | ilt_client->start, | |
7120 | ilt_client->end, | |
7121 | ilt_client->page_size, | |
7122 | ilt_client->flags, | |
7123 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 7124 | |
523224a3 DK |
7125 | #else |
7126 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7127 | #endif | |
619c5cb6 | 7128 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 7129 | } |
f85582f8 | 7130 | |
619c5cb6 VZ |
7131 | /** |
7132 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
7133 | * | |
7134 | * @bp: driver handle | |
7135 | * @fp: pointer to fastpath | |
7136 | * @init_params: pointer to parameters structure | |
7137 | * | |
7138 | * parameters configured: | |
7139 | * - HC configuration | |
7140 | * - Queue's CDU context | |
7141 | */ | |
7142 | static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, | |
7143 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) | |
a2fbb9ea | 7144 | { |
6383c0b3 AE |
7145 | |
7146 | u8 cos; | |
619c5cb6 VZ |
7147 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
7148 | if (!IS_FCOE_FP(fp)) { | |
7149 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
7150 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
7151 | ||
7152 | /* If HC is supporterd, enable host coalescing in the transition | |
7153 | * to INIT state. | |
7154 | */ | |
7155 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
7156 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
7157 | ||
7158 | /* HC rate */ | |
7159 | init_params->rx.hc_rate = bp->rx_ticks ? | |
7160 | (1000000 / bp->rx_ticks) : 0; | |
7161 | init_params->tx.hc_rate = bp->tx_ticks ? | |
7162 | (1000000 / bp->tx_ticks) : 0; | |
7163 | ||
7164 | /* FW SB ID */ | |
7165 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
7166 | fp->fw_sb_id; | |
7167 | ||
7168 | /* | |
7169 | * CQ index among the SB indices: FCoE clients uses the default | |
7170 | * SB, therefore it's different. | |
7171 | */ | |
6383c0b3 AE |
7172 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
7173 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
7174 | } |
7175 | ||
6383c0b3 AE |
7176 | /* set maximum number of COSs supported by this queue */ |
7177 | init_params->max_cos = fp->max_cos; | |
7178 | ||
7179 | DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d", | |
7180 | fp->index, init_params->max_cos); | |
7181 | ||
7182 | /* set the context pointers queue object */ | |
7183 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) | |
7184 | init_params->cxts[cos] = | |
7185 | &bp->context.vcxt[fp->txdata[cos].cid].eth; | |
619c5cb6 VZ |
7186 | } |
7187 | ||
6383c0b3 AE |
7188 | int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
7189 | struct bnx2x_queue_state_params *q_params, | |
7190 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
7191 | int tx_index, bool leading) | |
7192 | { | |
7193 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
7194 | ||
7195 | /* Set the command */ | |
7196 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
7197 | ||
7198 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
7199 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
7200 | ||
7201 | /* choose the index of the cid to send the slow path on */ | |
7202 | tx_only_params->cid_index = tx_index; | |
7203 | ||
7204 | /* Set general TX_ONLY_SETUP parameters */ | |
7205 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
7206 | ||
7207 | /* Set Tx TX_ONLY_SETUP parameters */ | |
7208 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
7209 | ||
7210 | DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" | |
7211 | "cos %d, primary cid %d, cid %d, " | |
7212 | "client id %d, sp-client id %d, flags %lx", | |
7213 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], | |
7214 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
7215 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
7216 | ||
7217 | /* send the ramrod */ | |
7218 | return bnx2x_queue_state_change(bp, q_params); | |
7219 | } | |
7220 | ||
7221 | ||
619c5cb6 VZ |
7222 | /** |
7223 | * bnx2x_setup_queue - setup queue | |
7224 | * | |
7225 | * @bp: driver handle | |
7226 | * @fp: pointer to fastpath | |
7227 | * @leading: is leading | |
7228 | * | |
7229 | * This function performs 2 steps in a Queue state machine | |
7230 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
7231 | */ | |
7232 | ||
7233 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
7234 | bool leading) | |
7235 | { | |
7236 | struct bnx2x_queue_state_params q_params = {0}; | |
7237 | struct bnx2x_queue_setup_params *setup_params = | |
7238 | &q_params.params.setup; | |
6383c0b3 AE |
7239 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
7240 | &q_params.params.tx_only; | |
a2fbb9ea | 7241 | int rc; |
6383c0b3 AE |
7242 | u8 tx_index; |
7243 | ||
7244 | DP(BNX2X_MSG_SP, "setting up queue %d", fp->index); | |
a2fbb9ea | 7245 | |
ec6ba945 VZ |
7246 | /* reset IGU state skip FCoE L2 queue */ |
7247 | if (!IS_FCOE_FP(fp)) | |
7248 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 7249 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 7250 | |
619c5cb6 VZ |
7251 | q_params.q_obj = &fp->q_obj; |
7252 | /* We want to wait for completion in this context */ | |
7253 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7254 | |
619c5cb6 VZ |
7255 | /* Prepare the INIT parameters */ |
7256 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 7257 | |
619c5cb6 VZ |
7258 | /* Set the command */ |
7259 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
7260 | ||
7261 | /* Change the state to INIT */ | |
7262 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7263 | if (rc) { | |
6383c0b3 | 7264 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
7265 | return rc; |
7266 | } | |
ec6ba945 | 7267 | |
6383c0b3 AE |
7268 | DP(BNX2X_MSG_SP, "init complete"); |
7269 | ||
7270 | ||
619c5cb6 VZ |
7271 | /* Now move the Queue to the SETUP state... */ |
7272 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 7273 | |
619c5cb6 VZ |
7274 | /* Set QUEUE flags */ |
7275 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 7276 | |
619c5cb6 | 7277 | /* Set general SETUP parameters */ |
6383c0b3 AE |
7278 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
7279 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 7280 | |
6383c0b3 | 7281 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
7282 | &setup_params->rxq_params); |
7283 | ||
6383c0b3 AE |
7284 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
7285 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
7286 | |
7287 | /* Set the command */ | |
7288 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
7289 | ||
7290 | /* Change the state to SETUP */ | |
7291 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
7292 | if (rc) { |
7293 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
7294 | return rc; | |
7295 | } | |
7296 | ||
7297 | /* loop through the relevant tx-only indices */ | |
7298 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7299 | tx_index < fp->max_cos; | |
7300 | tx_index++) { | |
7301 | ||
7302 | /* prepare and send tx-only ramrod*/ | |
7303 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
7304 | tx_only_params, tx_index, leading); | |
7305 | if (rc) { | |
7306 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
7307 | fp->index, tx_index); | |
7308 | return rc; | |
7309 | } | |
7310 | } | |
523224a3 | 7311 | |
34f80b04 | 7312 | return rc; |
a2fbb9ea ET |
7313 | } |
7314 | ||
619c5cb6 | 7315 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 7316 | { |
619c5cb6 | 7317 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 7318 | struct bnx2x_fp_txdata *txdata; |
619c5cb6 | 7319 | struct bnx2x_queue_state_params q_params = {0}; |
6383c0b3 AE |
7320 | int rc, tx_index; |
7321 | ||
7322 | DP(BNX2X_MSG_SP, "stopping queue %d cid %d", index, fp->cid); | |
a2fbb9ea | 7323 | |
619c5cb6 VZ |
7324 | q_params.q_obj = &fp->q_obj; |
7325 | /* We want to wait for completion in this context */ | |
7326 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7327 | |
6383c0b3 AE |
7328 | |
7329 | /* close tx-only connections */ | |
7330 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7331 | tx_index < fp->max_cos; | |
7332 | tx_index++){ | |
7333 | ||
7334 | /* ascertain this is a normal queue*/ | |
7335 | txdata = &fp->txdata[tx_index]; | |
7336 | ||
7337 | DP(BNX2X_MSG_SP, "stopping tx-only queue %d", | |
7338 | txdata->txq_index); | |
7339 | ||
7340 | /* send halt terminate on tx-only connection */ | |
7341 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
7342 | memset(&q_params.params.terminate, 0, | |
7343 | sizeof(q_params.params.terminate)); | |
7344 | q_params.params.terminate.cid_index = tx_index; | |
7345 | ||
7346 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7347 | if (rc) | |
7348 | return rc; | |
7349 | ||
7350 | /* send halt terminate on tx-only connection */ | |
7351 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
7352 | memset(&q_params.params.cfc_del, 0, | |
7353 | sizeof(q_params.params.cfc_del)); | |
7354 | q_params.params.cfc_del.cid_index = tx_index; | |
7355 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7356 | if (rc) | |
7357 | return rc; | |
7358 | } | |
7359 | /* Stop the primary connection: */ | |
7360 | /* ...halt the connection */ | |
619c5cb6 VZ |
7361 | q_params.cmd = BNX2X_Q_CMD_HALT; |
7362 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7363 | if (rc) | |
da5a662a | 7364 | return rc; |
a2fbb9ea | 7365 | |
6383c0b3 | 7366 | /* ...terminate the connection */ |
619c5cb6 | 7367 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
7368 | memset(&q_params.params.terminate, 0, |
7369 | sizeof(q_params.params.terminate)); | |
7370 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
7371 | rc = bnx2x_queue_state_change(bp, &q_params); |
7372 | if (rc) | |
523224a3 | 7373 | return rc; |
6383c0b3 | 7374 | /* ...delete cfc entry */ |
619c5cb6 | 7375 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
7376 | memset(&q_params.params.cfc_del, 0, |
7377 | sizeof(q_params.params.cfc_del)); | |
7378 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 7379 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
7380 | } |
7381 | ||
7382 | ||
34f80b04 EG |
7383 | static void bnx2x_reset_func(struct bnx2x *bp) |
7384 | { | |
7385 | int port = BP_PORT(bp); | |
7386 | int func = BP_FUNC(bp); | |
f2e0899f | 7387 | int i; |
523224a3 DK |
7388 | |
7389 | /* Disable the function in the FW */ | |
7390 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
7391 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
7392 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
7393 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
7394 | ||
7395 | /* FP SBs */ | |
ec6ba945 | 7396 | for_each_eth_queue(bp, i) { |
523224a3 | 7397 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 7398 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
7399 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
7400 | SB_DISABLED); | |
523224a3 DK |
7401 | } |
7402 | ||
619c5cb6 VZ |
7403 | #ifdef BCM_CNIC |
7404 | /* CNIC SB */ | |
7405 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
7406 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), | |
7407 | SB_DISABLED); | |
7408 | #endif | |
523224a3 | 7409 | /* SP SB */ |
619c5cb6 | 7410 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
7411 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
7412 | SB_DISABLED); | |
523224a3 DK |
7413 | |
7414 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
7415 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
7416 | 0); | |
34f80b04 EG |
7417 | |
7418 | /* Configure IGU */ | |
f2e0899f DK |
7419 | if (bp->common.int_block == INT_BLOCK_HC) { |
7420 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7421 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7422 | } else { | |
7423 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
7424 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
7425 | } | |
34f80b04 | 7426 | |
37b091ba MC |
7427 | #ifdef BCM_CNIC |
7428 | /* Disable Timer scan */ | |
7429 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
7430 | /* | |
7431 | * Wait for at least 10ms and up to 2 second for the timers scan to | |
7432 | * complete | |
7433 | */ | |
7434 | for (i = 0; i < 200; i++) { | |
7435 | msleep(10); | |
7436 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) | |
7437 | break; | |
7438 | } | |
7439 | #endif | |
34f80b04 | 7440 | /* Clear ILT */ |
f2e0899f DK |
7441 | bnx2x_clear_func_ilt(bp, func); |
7442 | ||
7443 | /* Timers workaround bug for E2: if this is vnic-3, | |
7444 | * we need to set the entire ilt range for this timers. | |
7445 | */ | |
619c5cb6 | 7446 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
7447 | struct ilt_client_info ilt_cli; |
7448 | /* use dummy TM client */ | |
7449 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
7450 | ilt_cli.start = 0; | |
7451 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
7452 | ilt_cli.client_num = ILT_CLIENT_TM; | |
7453 | ||
7454 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
7455 | } | |
7456 | ||
7457 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 7458 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 7459 | bnx2x_pf_disable(bp); |
523224a3 DK |
7460 | |
7461 | bp->dmae_ready = 0; | |
34f80b04 EG |
7462 | } |
7463 | ||
7464 | static void bnx2x_reset_port(struct bnx2x *bp) | |
7465 | { | |
7466 | int port = BP_PORT(bp); | |
7467 | u32 val; | |
7468 | ||
619c5cb6 VZ |
7469 | /* Reset physical Link */ |
7470 | bnx2x__link_reset(bp); | |
7471 | ||
34f80b04 EG |
7472 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
7473 | ||
7474 | /* Do not rcv packets to BRB */ | |
7475 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
7476 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
7477 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
7478 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
7479 | ||
7480 | /* Configure AEU */ | |
7481 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
7482 | ||
7483 | msleep(100); | |
7484 | /* Check for BRB port occupancy */ | |
7485 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
7486 | if (val) | |
7487 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 7488 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
7489 | |
7490 | /* TODO: Close Doorbell port? */ | |
7491 | } | |
7492 | ||
619c5cb6 | 7493 | static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 7494 | { |
619c5cb6 | 7495 | struct bnx2x_func_state_params func_params = {0}; |
34f80b04 | 7496 | |
619c5cb6 VZ |
7497 | /* Prepare parameters for function state transitions */ |
7498 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 7499 | |
619c5cb6 VZ |
7500 | func_params.f_obj = &bp->func_obj; |
7501 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 7502 | |
619c5cb6 | 7503 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 7504 | |
619c5cb6 | 7505 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
7506 | } |
7507 | ||
619c5cb6 | 7508 | static inline int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 7509 | { |
619c5cb6 VZ |
7510 | struct bnx2x_func_state_params func_params = {0}; |
7511 | int rc; | |
228241eb | 7512 | |
619c5cb6 VZ |
7513 | /* Prepare parameters for function state transitions */ |
7514 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7515 | func_params.f_obj = &bp->func_obj; | |
7516 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 7517 | |
619c5cb6 VZ |
7518 | /* |
7519 | * Try to stop the function the 'good way'. If fails (in case | |
7520 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
7521 | * not in a debug mode, perform a state transaction in order to | |
7522 | * enable further HW_RESET transaction. | |
7523 | */ | |
7524 | rc = bnx2x_func_state_change(bp, &func_params); | |
7525 | if (rc) { | |
34f80b04 | 7526 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 7527 | return rc; |
34f80b04 | 7528 | #else |
619c5cb6 VZ |
7529 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " |
7530 | "transaction\n"); | |
7531 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); | |
7532 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 7533 | #endif |
228241eb | 7534 | } |
a2fbb9ea | 7535 | |
619c5cb6 VZ |
7536 | return 0; |
7537 | } | |
523224a3 | 7538 | |
619c5cb6 VZ |
7539 | /** |
7540 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
7541 | * | |
7542 | * @bp: driver handle | |
7543 | * @unload_mode: requested function's unload mode | |
7544 | * | |
7545 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
7546 | */ | |
7547 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
7548 | { | |
7549 | u32 reset_code = 0; | |
7550 | int port = BP_PORT(bp); | |
3101c2bc | 7551 | |
619c5cb6 | 7552 | /* Select the UNLOAD request mode */ |
65abd74d YG |
7553 | if (unload_mode == UNLOAD_NORMAL) |
7554 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
7555 | ||
7d0446c2 | 7556 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 7557 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 7558 | |
7d0446c2 | 7559 | else if (bp->wol) { |
65abd74d YG |
7560 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
7561 | u8 *mac_addr = bp->dev->dev_addr; | |
7562 | u32 val; | |
7563 | /* The mac address is written to entries 1-4 to | |
7564 | preserve entry 0 which is used by the PMF */ | |
7565 | u8 entry = (BP_E1HVN(bp) + 1)*8; | |
7566 | ||
7567 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
7568 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
7569 | ||
7570 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
7571 | (mac_addr[4] << 8) | mac_addr[5]; | |
7572 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
7573 | ||
7574 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; | |
7575 | ||
7576 | } else | |
7577 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 7578 | |
619c5cb6 VZ |
7579 | /* Send the request to the MCP */ |
7580 | if (!BP_NOMCP(bp)) | |
7581 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
7582 | else { | |
7583 | int path = BP_PATH(bp); | |
7584 | ||
7585 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " | |
7586 | "%d, %d, %d\n", | |
7587 | path, load_count[path][0], load_count[path][1], | |
7588 | load_count[path][2]); | |
7589 | load_count[path][0]--; | |
7590 | load_count[path][1 + port]--; | |
7591 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " | |
7592 | "%d, %d, %d\n", | |
7593 | path, load_count[path][0], load_count[path][1], | |
7594 | load_count[path][2]); | |
7595 | if (load_count[path][0] == 0) | |
7596 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; | |
7597 | else if (load_count[path][1 + port] == 0) | |
7598 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; | |
7599 | else | |
7600 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
7601 | } | |
7602 | ||
7603 | return reset_code; | |
7604 | } | |
7605 | ||
7606 | /** | |
7607 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
7608 | * | |
7609 | * @bp: driver handle | |
7610 | */ | |
7611 | void bnx2x_send_unload_done(struct bnx2x *bp) | |
7612 | { | |
7613 | /* Report UNLOAD_DONE to MCP */ | |
7614 | if (!BP_NOMCP(bp)) | |
7615 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
7616 | } | |
7617 | ||
6debea87 DK |
7618 | static inline int bnx2x_func_wait_started(struct bnx2x *bp) |
7619 | { | |
7620 | int tout = 50; | |
7621 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
7622 | ||
7623 | if (!bp->port.pmf) | |
7624 | return 0; | |
7625 | ||
7626 | /* | |
7627 | * (assumption: No Attention from MCP at this stage) | |
7628 | * PMF probably in the middle of TXdisable/enable transaction | |
7629 | * 1. Sync IRS for default SB | |
7630 | * 2. Sync SP queue - this guarantes us that attention handling started | |
7631 | * 3. Wait, that TXdisable/enable transaction completes | |
7632 | * | |
7633 | * 1+2 guranty that if DCBx attention was scheduled it already changed | |
7634 | * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy | |
7635 | * received complettion for the transaction the state is TX_STOPPED. | |
7636 | * State will return to STARTED after completion of TX_STOPPED-->STARTED | |
7637 | * transaction. | |
7638 | */ | |
7639 | ||
7640 | /* make sure default SB ISR is done */ | |
7641 | if (msix) | |
7642 | synchronize_irq(bp->msix_table[0].vector); | |
7643 | else | |
7644 | synchronize_irq(bp->pdev->irq); | |
7645 | ||
7646 | flush_workqueue(bnx2x_wq); | |
7647 | ||
7648 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
7649 | BNX2X_F_STATE_STARTED && tout--) | |
7650 | msleep(20); | |
7651 | ||
7652 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
7653 | BNX2X_F_STATE_STARTED) { | |
7654 | #ifdef BNX2X_STOP_ON_ERROR | |
7655 | return -EBUSY; | |
7656 | #else | |
7657 | /* | |
7658 | * Failed to complete the transaction in a "good way" | |
7659 | * Force both transactions with CLR bit | |
7660 | */ | |
7661 | struct bnx2x_func_state_params func_params = {0}; | |
7662 | ||
7663 | DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " | |
7664 | "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); | |
7665 | ||
7666 | func_params.f_obj = &bp->func_obj; | |
7667 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
7668 | &func_params.ramrod_flags); | |
7669 | ||
7670 | /* STARTED-->TX_ST0PPED */ | |
7671 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
7672 | bnx2x_func_state_change(bp, &func_params); | |
7673 | ||
7674 | /* TX_ST0PPED-->STARTED */ | |
7675 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
7676 | return bnx2x_func_state_change(bp, &func_params); | |
7677 | #endif | |
7678 | } | |
7679 | ||
7680 | return 0; | |
7681 | } | |
7682 | ||
619c5cb6 VZ |
7683 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) |
7684 | { | |
7685 | int port = BP_PORT(bp); | |
6383c0b3 AE |
7686 | int i, rc = 0; |
7687 | u8 cos; | |
619c5cb6 VZ |
7688 | struct bnx2x_mcast_ramrod_params rparam = {0}; |
7689 | u32 reset_code; | |
7690 | ||
7691 | /* Wait until tx fastpath tasks complete */ | |
7692 | for_each_tx_queue(bp, i) { | |
7693 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
7694 | ||
6383c0b3 AE |
7695 | for_each_cos_in_tx_queue(fp, cos) |
7696 | rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); | |
619c5cb6 VZ |
7697 | #ifdef BNX2X_STOP_ON_ERROR |
7698 | if (rc) | |
7699 | return; | |
7700 | #endif | |
7701 | } | |
7702 | ||
7703 | /* Give HW time to discard old tx messages */ | |
7704 | usleep_range(1000, 1000); | |
7705 | ||
7706 | /* Clean all ETH MACs */ | |
7707 | rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); | |
7708 | if (rc < 0) | |
7709 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
7710 | ||
7711 | /* Clean up UC list */ | |
7712 | rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, | |
7713 | true); | |
7714 | if (rc < 0) | |
7715 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " | |
7716 | "%d\n", rc); | |
7717 | ||
7718 | /* Disable LLH */ | |
7719 | if (!CHIP_IS_E1(bp)) | |
7720 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
7721 | ||
7722 | /* Set "drop all" (stop Rx). | |
7723 | * We need to take a netif_addr_lock() here in order to prevent | |
7724 | * a race between the completion code and this code. | |
7725 | */ | |
7726 | netif_addr_lock_bh(bp->dev); | |
7727 | /* Schedule the rx_mode command */ | |
7728 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
7729 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
7730 | else | |
7731 | bnx2x_set_storm_rx_mode(bp); | |
7732 | ||
7733 | /* Cleanup multicast configuration */ | |
7734 | rparam.mcast_obj = &bp->mcast_obj; | |
7735 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
7736 | if (rc < 0) | |
7737 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
7738 | ||
7739 | netif_addr_unlock_bh(bp->dev); | |
7740 | ||
7741 | ||
6debea87 DK |
7742 | |
7743 | /* | |
7744 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
7745 | * this function should perform FUNC, PORT or COMMON HW | |
7746 | * reset. | |
7747 | */ | |
7748 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
7749 | ||
7750 | /* | |
7751 | * (assumption: No Attention from MCP at this stage) | |
7752 | * PMF probably in the middle of TXdisable/enable transaction | |
7753 | */ | |
7754 | rc = bnx2x_func_wait_started(bp); | |
7755 | if (rc) { | |
7756 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
7757 | #ifdef BNX2X_STOP_ON_ERROR | |
7758 | return; | |
7759 | #endif | |
7760 | } | |
7761 | ||
34f80b04 | 7762 | /* Close multi and leading connections |
619c5cb6 VZ |
7763 | * Completions for ramrods are collected in a synchronous way |
7764 | */ | |
523224a3 | 7765 | for_each_queue(bp, i) |
619c5cb6 | 7766 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
7767 | #ifdef BNX2X_STOP_ON_ERROR |
7768 | return; | |
7769 | #else | |
228241eb | 7770 | goto unload_error; |
523224a3 | 7771 | #endif |
619c5cb6 VZ |
7772 | /* If SP settings didn't get completed so far - something |
7773 | * very wrong has happen. | |
7774 | */ | |
7775 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
7776 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 7777 | |
619c5cb6 VZ |
7778 | #ifndef BNX2X_STOP_ON_ERROR |
7779 | unload_error: | |
7780 | #endif | |
523224a3 | 7781 | rc = bnx2x_func_stop(bp); |
da5a662a | 7782 | if (rc) { |
523224a3 | 7783 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 7784 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 7785 | return; |
523224a3 | 7786 | #endif |
34f80b04 | 7787 | } |
a2fbb9ea | 7788 | |
523224a3 DK |
7789 | /* Disable HW interrupts, NAPI */ |
7790 | bnx2x_netif_stop(bp, 1); | |
7791 | ||
7792 | /* Release IRQs */ | |
d6214d7a | 7793 | bnx2x_free_irq(bp); |
523224a3 | 7794 | |
a2fbb9ea | 7795 | /* Reset the chip */ |
619c5cb6 VZ |
7796 | rc = bnx2x_reset_hw(bp, reset_code); |
7797 | if (rc) | |
7798 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 7799 | |
356e2385 | 7800 | |
619c5cb6 VZ |
7801 | /* Report UNLOAD_DONE to MCP */ |
7802 | bnx2x_send_unload_done(bp); | |
72fd0718 VZ |
7803 | } |
7804 | ||
9f6c9258 | 7805 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
7806 | { |
7807 | u32 val; | |
7808 | ||
7809 | DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); | |
7810 | ||
7811 | if (CHIP_IS_E1(bp)) { | |
7812 | int port = BP_PORT(bp); | |
7813 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
7814 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
7815 | ||
7816 | val = REG_RD(bp, addr); | |
7817 | val &= ~(0x300); | |
7818 | REG_WR(bp, addr, val); | |
619c5cb6 | 7819 | } else { |
72fd0718 VZ |
7820 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
7821 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
7822 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
7823 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
7824 | } | |
7825 | } | |
7826 | ||
72fd0718 VZ |
7827 | /* Close gates #2, #3 and #4: */ |
7828 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
7829 | { | |
c9ee9206 | 7830 | u32 val; |
72fd0718 VZ |
7831 | |
7832 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
7833 | if (!CHIP_IS_E1(bp)) { | |
7834 | /* #4 */ | |
c9ee9206 | 7835 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 7836 | /* #2 */ |
c9ee9206 | 7837 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
7838 | } |
7839 | ||
7840 | /* #3 */ | |
c9ee9206 VZ |
7841 | if (CHIP_IS_E1x(bp)) { |
7842 | /* Prevent interrupts from HC on both ports */ | |
7843 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
7844 | REG_WR(bp, HC_REG_CONFIG_1, | |
7845 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
7846 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
7847 | ||
7848 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
7849 | REG_WR(bp, HC_REG_CONFIG_0, | |
7850 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
7851 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
7852 | } else { | |
7853 | /* Prevent incomming interrupts in IGU */ | |
7854 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); | |
7855 | ||
7856 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
7857 | (!close) ? | |
7858 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
7859 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
7860 | } | |
72fd0718 VZ |
7861 | |
7862 | DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", | |
7863 | close ? "closing" : "opening"); | |
7864 | mmiowb(); | |
7865 | } | |
7866 | ||
7867 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
7868 | ||
7869 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
7870 | { | |
7871 | /* Do some magic... */ | |
7872 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
7873 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
7874 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
7875 | } | |
7876 | ||
e8920674 DK |
7877 | /** |
7878 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 7879 | * |
e8920674 DK |
7880 | * @bp: driver handle |
7881 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
7882 | */ |
7883 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
7884 | { | |
7885 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
7886 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
7887 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
7888 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
7889 | } | |
7890 | ||
f85582f8 | 7891 | /** |
e8920674 | 7892 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 7893 | * |
e8920674 DK |
7894 | * @bp: driver handle |
7895 | * @magic_val: old value of 'magic' bit. | |
7896 | * | |
7897 | * Takes care of CLP configurations. | |
72fd0718 VZ |
7898 | */ |
7899 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
7900 | { | |
7901 | u32 shmem; | |
7902 | u32 validity_offset; | |
7903 | ||
7904 | DP(NETIF_MSG_HW, "Starting\n"); | |
7905 | ||
7906 | /* Set `magic' bit in order to save MF config */ | |
7907 | if (!CHIP_IS_E1(bp)) | |
7908 | bnx2x_clp_reset_prep(bp, magic_val); | |
7909 | ||
7910 | /* Get shmem offset */ | |
7911 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
7912 | validity_offset = offsetof(struct shmem_region, validity_map[0]); | |
7913 | ||
7914 | /* Clear validity map flags */ | |
7915 | if (shmem > 0) | |
7916 | REG_WR(bp, shmem + validity_offset, 0); | |
7917 | } | |
7918 | ||
7919 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
7920 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
7921 | ||
e8920674 DK |
7922 | /** |
7923 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 7924 | * |
e8920674 | 7925 | * @bp: driver handle |
72fd0718 VZ |
7926 | */ |
7927 | static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) | |
7928 | { | |
7929 | /* special handling for emulation and FPGA, | |
7930 | wait 10 times longer */ | |
7931 | if (CHIP_REV_IS_SLOW(bp)) | |
7932 | msleep(MCP_ONE_TIMEOUT*10); | |
7933 | else | |
7934 | msleep(MCP_ONE_TIMEOUT); | |
7935 | } | |
7936 | ||
1b6e2ceb DK |
7937 | /* |
7938 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
7939 | */ | |
7940 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 7941 | { |
1b6e2ceb DK |
7942 | int cnt = 0; |
7943 | u32 val = 0; | |
72fd0718 | 7944 | |
1b6e2ceb DK |
7945 | do { |
7946 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
7947 | if (bp->common.shmem_base) { | |
7948 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
7949 | if (val & SHR_MEM_VALIDITY_MB) | |
7950 | return 0; | |
7951 | } | |
72fd0718 | 7952 | |
1b6e2ceb | 7953 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 7954 | |
1b6e2ceb | 7955 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 7956 | |
1b6e2ceb | 7957 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 7958 | |
1b6e2ceb DK |
7959 | return -ENODEV; |
7960 | } | |
72fd0718 | 7961 | |
1b6e2ceb DK |
7962 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
7963 | { | |
7964 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 7965 | |
72fd0718 VZ |
7966 | /* Restore the `magic' bit value */ |
7967 | if (!CHIP_IS_E1(bp)) | |
7968 | bnx2x_clp_reset_done(bp, magic_val); | |
7969 | ||
7970 | return rc; | |
7971 | } | |
7972 | ||
7973 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
7974 | { | |
7975 | if (!CHIP_IS_E1(bp)) { | |
7976 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
7977 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
7978 | mmiowb(); |
7979 | } | |
7980 | } | |
7981 | ||
7982 | /* | |
7983 | * Reset the whole chip except for: | |
7984 | * - PCIE core | |
7985 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
7986 | * one reset bit) | |
7987 | * - IGU | |
7988 | * - MISC (including AEU) | |
7989 | * - GRC | |
7990 | * - RBCN, RBCP | |
7991 | */ | |
c9ee9206 | 7992 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
7993 | { |
7994 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 7995 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
7996 | |
7997 | /* | |
7998 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
7999 | * (per chip) blocks. | |
8000 | */ | |
8001 | global_bits2 = | |
8002 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
8003 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 8004 | |
8736c826 | 8005 | /* Don't reset the following blocks */ |
72fd0718 VZ |
8006 | not_reset_mask1 = |
8007 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
8008 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
8009 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
8010 | ||
8011 | not_reset_mask2 = | |
c9ee9206 | 8012 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
8013 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
8014 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
8015 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
8016 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
8017 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
8018 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
8019 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
8020 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
8021 | MISC_REGISTERS_RESET_REG_2_PGLC; | |
72fd0718 | 8022 | |
8736c826 VZ |
8023 | /* |
8024 | * Keep the following blocks in reset: | |
8025 | * - all xxMACs are handled by the bnx2x_link code. | |
8026 | */ | |
8027 | stay_reset2 = | |
8028 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
8029 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
8030 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
8031 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
8032 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
8033 | MISC_REGISTERS_RESET_REG_2_UMAC1 | | |
8034 | MISC_REGISTERS_RESET_REG_2_XMAC | | |
8035 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
8036 | ||
8037 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
8038 | reset_mask1 = 0xffffffff; |
8039 | ||
8040 | if (CHIP_IS_E1(bp)) | |
8041 | reset_mask2 = 0xffff; | |
8736c826 | 8042 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 8043 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
8044 | else if (CHIP_IS_E2(bp)) |
8045 | reset_mask2 = 0xfffff; | |
8046 | else /* CHIP_IS_E3 */ | |
8047 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
8048 | |
8049 | /* Don't reset global blocks unless we need to */ | |
8050 | if (!global) | |
8051 | reset_mask2 &= ~global_bits2; | |
8052 | ||
8053 | /* | |
8054 | * In case of attention in the QM, we need to reset PXP | |
8055 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
8056 | * because otherwise QM reset would release 'close the gates' shortly | |
8057 | * before resetting the PXP, then the PSWRQ would send a write | |
8058 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
8059 | * read the payload data from PSWWR, but PSWWR would not | |
8060 | * respond. The write queue in PGLUE would stuck, dmae commands | |
8061 | * would not return. Therefore it's important to reset the second | |
8062 | * reset register (containing the | |
8063 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
8064 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
8065 | * bit). | |
8066 | */ | |
72fd0718 VZ |
8067 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
8068 | reset_mask2 & (~not_reset_mask2)); | |
8069 | ||
c9ee9206 VZ |
8070 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
8071 | reset_mask1 & (~not_reset_mask1)); | |
8072 | ||
72fd0718 VZ |
8073 | barrier(); |
8074 | mmiowb(); | |
8075 | ||
8736c826 VZ |
8076 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
8077 | reset_mask2 & (~stay_reset2)); | |
8078 | ||
8079 | barrier(); | |
8080 | mmiowb(); | |
8081 | ||
c9ee9206 | 8082 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
8083 | mmiowb(); |
8084 | } | |
8085 | ||
c9ee9206 VZ |
8086 | /** |
8087 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
8088 | * It should get cleared in no more than 1s. | |
8089 | * | |
8090 | * @bp: driver handle | |
8091 | * | |
8092 | * It should get cleared in no more than 1s. Returns 0 if | |
8093 | * pending writes bit gets cleared. | |
8094 | */ | |
8095 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
8096 | { | |
8097 | u32 cnt = 1000; | |
8098 | u32 pend_bits = 0; | |
8099 | ||
8100 | do { | |
8101 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
8102 | ||
8103 | if (pend_bits == 0) | |
8104 | break; | |
8105 | ||
8106 | usleep_range(1000, 1000); | |
8107 | } while (cnt-- > 0); | |
8108 | ||
8109 | if (cnt <= 0) { | |
8110 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
8111 | pend_bits); | |
8112 | return -EBUSY; | |
8113 | } | |
8114 | ||
8115 | return 0; | |
8116 | } | |
8117 | ||
8118 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
8119 | { |
8120 | int cnt = 1000; | |
8121 | u32 val = 0; | |
8122 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
8123 | ||
8124 | ||
8125 | /* Empty the Tetris buffer, wait for 1s */ | |
8126 | do { | |
8127 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
8128 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
8129 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
8130 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
8131 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
8132 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && | |
8133 | ((port_is_idle_0 & 0x1) == 0x1) && | |
8134 | ((port_is_idle_1 & 0x1) == 0x1) && | |
8135 | (pgl_exp_rom2 == 0xffffffff)) | |
8136 | break; | |
c9ee9206 | 8137 | usleep_range(1000, 1000); |
72fd0718 VZ |
8138 | } while (cnt-- > 0); |
8139 | ||
8140 | if (cnt <= 0) { | |
8141 | DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" | |
8142 | " are still" | |
8143 | " outstanding read requests after 1s!\n"); | |
8144 | DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," | |
8145 | " port_is_idle_0=0x%08x," | |
8146 | " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
8147 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, | |
8148 | pgl_exp_rom2); | |
8149 | return -EAGAIN; | |
8150 | } | |
8151 | ||
8152 | barrier(); | |
8153 | ||
8154 | /* Close gates #2, #3 and #4 */ | |
8155 | bnx2x_set_234_gates(bp, true); | |
8156 | ||
c9ee9206 VZ |
8157 | /* Poll for IGU VQs for 57712 and newer chips */ |
8158 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
8159 | return -EAGAIN; | |
8160 | ||
8161 | ||
72fd0718 VZ |
8162 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
8163 | ||
8164 | /* Clear "unprepared" bit */ | |
8165 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
8166 | barrier(); | |
8167 | ||
8168 | /* Make sure all is written to the chip before the reset */ | |
8169 | mmiowb(); | |
8170 | ||
8171 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
8172 | * PSWHST, GRC and PSWRD Tetris buffer. | |
8173 | */ | |
c9ee9206 | 8174 | usleep_range(1000, 1000); |
72fd0718 VZ |
8175 | |
8176 | /* Prepare to chip reset: */ | |
8177 | /* MCP */ | |
c9ee9206 VZ |
8178 | if (global) |
8179 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
8180 | |
8181 | /* PXP */ | |
8182 | bnx2x_pxp_prep(bp); | |
8183 | barrier(); | |
8184 | ||
8185 | /* reset the chip */ | |
c9ee9206 | 8186 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
8187 | barrier(); |
8188 | ||
8189 | /* Recover after reset: */ | |
8190 | /* MCP */ | |
c9ee9206 | 8191 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
8192 | return -EAGAIN; |
8193 | ||
c9ee9206 VZ |
8194 | /* TBD: Add resetting the NO_MCP mode DB here */ |
8195 | ||
72fd0718 VZ |
8196 | /* PXP */ |
8197 | bnx2x_pxp_prep(bp); | |
8198 | ||
8199 | /* Open the gates #2, #3 and #4 */ | |
8200 | bnx2x_set_234_gates(bp, false); | |
8201 | ||
8202 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
8203 | * reset state, re-enable attentions. */ | |
8204 | ||
a2fbb9ea ET |
8205 | return 0; |
8206 | } | |
8207 | ||
c9ee9206 | 8208 | int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
8209 | { |
8210 | int rc = 0; | |
c9ee9206 VZ |
8211 | bool global = bnx2x_reset_is_global(bp); |
8212 | ||
72fd0718 | 8213 | /* Try to recover after the failure */ |
c9ee9206 VZ |
8214 | if (bnx2x_process_kill(bp, global)) { |
8215 | netdev_err(bp->dev, "Something bad had happen on engine %d! " | |
8216 | "Aii!\n", BP_PATH(bp)); | |
72fd0718 VZ |
8217 | rc = -EAGAIN; |
8218 | goto exit_leader_reset; | |
8219 | } | |
8220 | ||
c9ee9206 VZ |
8221 | /* |
8222 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
8223 | * state. | |
8224 | */ | |
72fd0718 | 8225 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
8226 | if (global) |
8227 | bnx2x_clear_reset_global(bp); | |
72fd0718 VZ |
8228 | |
8229 | exit_leader_reset: | |
8230 | bp->is_leader = 0; | |
c9ee9206 VZ |
8231 | bnx2x_release_leader_lock(bp); |
8232 | smp_mb(); | |
72fd0718 VZ |
8233 | return rc; |
8234 | } | |
8235 | ||
c9ee9206 VZ |
8236 | static inline void bnx2x_recovery_failed(struct bnx2x *bp) |
8237 | { | |
8238 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
8239 | ||
8240 | /* Disconnect this device */ | |
8241 | netif_device_detach(bp->dev); | |
8242 | ||
8243 | /* | |
8244 | * Block ifup for all function on this engine until "process kill" | |
8245 | * or power cycle. | |
8246 | */ | |
8247 | bnx2x_set_reset_in_progress(bp); | |
8248 | ||
8249 | /* Shut down the power */ | |
8250 | bnx2x_set_power_state(bp, PCI_D3hot); | |
8251 | ||
8252 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
8253 | ||
8254 | smp_mb(); | |
8255 | } | |
8256 | ||
8257 | /* | |
8258 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 8259 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
8260 | * will never be called when netif_running(bp->dev) is false. |
8261 | */ | |
8262 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
8263 | { | |
c9ee9206 VZ |
8264 | bool global = false; |
8265 | ||
72fd0718 VZ |
8266 | DP(NETIF_MSG_HW, "Handling parity\n"); |
8267 | while (1) { | |
8268 | switch (bp->recovery_state) { | |
8269 | case BNX2X_RECOVERY_INIT: | |
8270 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
c9ee9206 VZ |
8271 | bnx2x_chk_parity_attn(bp, &global, false); |
8272 | ||
72fd0718 | 8273 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
8274 | if (bnx2x_trylock_leader_lock(bp)) { |
8275 | bnx2x_set_reset_in_progress(bp); | |
8276 | /* | |
8277 | * Check if there is a global attention and if | |
8278 | * there was a global attention, set the global | |
8279 | * reset bit. | |
8280 | */ | |
8281 | ||
8282 | if (global) | |
8283 | bnx2x_set_reset_global(bp); | |
8284 | ||
72fd0718 | 8285 | bp->is_leader = 1; |
c9ee9206 | 8286 | } |
72fd0718 VZ |
8287 | |
8288 | /* Stop the driver */ | |
8289 | /* If interface has been removed - break */ | |
8290 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) | |
8291 | return; | |
8292 | ||
8293 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 VZ |
8294 | |
8295 | /* | |
8296 | * Reset MCP command sequence number and MCP mail box | |
8297 | * sequence as we are going to reset the MCP. | |
8298 | */ | |
8299 | if (global) { | |
8300 | bp->fw_seq = 0; | |
8301 | bp->fw_drv_pulse_wr_seq = 0; | |
8302 | } | |
8303 | ||
8304 | /* Ensure "is_leader", MCP command sequence and | |
8305 | * "recovery_state" update values are seen on other | |
8306 | * CPUs. | |
72fd0718 | 8307 | */ |
c9ee9206 | 8308 | smp_mb(); |
72fd0718 VZ |
8309 | break; |
8310 | ||
8311 | case BNX2X_RECOVERY_WAIT: | |
8312 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
8313 | if (bp->is_leader) { | |
c9ee9206 VZ |
8314 | int other_engine = BP_PATH(bp) ? 0 : 1; |
8315 | u32 other_load_counter = | |
8316 | bnx2x_get_load_cnt(bp, other_engine); | |
8317 | u32 load_counter = | |
8318 | bnx2x_get_load_cnt(bp, BP_PATH(bp)); | |
8319 | global = bnx2x_reset_is_global(bp); | |
8320 | ||
8321 | /* | |
8322 | * In case of a parity in a global block, let | |
8323 | * the first leader that performs a | |
8324 | * leader_reset() reset the global blocks in | |
8325 | * order to clear global attentions. Otherwise | |
8326 | * the the gates will remain closed for that | |
8327 | * engine. | |
8328 | */ | |
8329 | if (load_counter || | |
8330 | (global && other_load_counter)) { | |
72fd0718 VZ |
8331 | /* Wait until all other functions get |
8332 | * down. | |
8333 | */ | |
7be08a72 | 8334 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
8335 | HZ/10); |
8336 | return; | |
8337 | } else { | |
8338 | /* If all other functions got down - | |
8339 | * try to bring the chip back to | |
8340 | * normal. In any case it's an exit | |
8341 | * point for a leader. | |
8342 | */ | |
c9ee9206 VZ |
8343 | if (bnx2x_leader_reset(bp)) { |
8344 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
8345 | return; |
8346 | } | |
8347 | ||
c9ee9206 VZ |
8348 | /* If we are here, means that the |
8349 | * leader has succeeded and doesn't | |
8350 | * want to be a leader any more. Try | |
8351 | * to continue as a none-leader. | |
8352 | */ | |
8353 | break; | |
72fd0718 VZ |
8354 | } |
8355 | } else { /* non-leader */ | |
c9ee9206 | 8356 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
8357 | /* Try to get a LEADER_LOCK HW lock as |
8358 | * long as a former leader may have | |
8359 | * been unloaded by the user or | |
8360 | * released a leadership by another | |
8361 | * reason. | |
8362 | */ | |
c9ee9206 | 8363 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
8364 | /* I'm a leader now! Restart a |
8365 | * switch case. | |
8366 | */ | |
8367 | bp->is_leader = 1; | |
8368 | break; | |
8369 | } | |
8370 | ||
7be08a72 | 8371 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
8372 | HZ/10); |
8373 | return; | |
8374 | ||
c9ee9206 VZ |
8375 | } else { |
8376 | /* | |
8377 | * If there was a global attention, wait | |
8378 | * for it to be cleared. | |
8379 | */ | |
8380 | if (bnx2x_reset_is_global(bp)) { | |
8381 | schedule_delayed_work( | |
7be08a72 AE |
8382 | &bp->sp_rtnl_task, |
8383 | HZ/10); | |
c9ee9206 VZ |
8384 | return; |
8385 | } | |
8386 | ||
8387 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) | |
8388 | bnx2x_recovery_failed(bp); | |
8389 | else { | |
8390 | bp->recovery_state = | |
8391 | BNX2X_RECOVERY_DONE; | |
8392 | smp_mb(); | |
8393 | } | |
8394 | ||
72fd0718 VZ |
8395 | return; |
8396 | } | |
8397 | } | |
8398 | default: | |
8399 | return; | |
8400 | } | |
8401 | } | |
8402 | } | |
8403 | ||
8404 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is | |
8405 | * scheduled on a general queue in order to prevent a dead lock. | |
8406 | */ | |
7be08a72 | 8407 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 8408 | { |
7be08a72 | 8409 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
8410 | |
8411 | rtnl_lock(); | |
8412 | ||
8413 | if (!netif_running(bp->dev)) | |
7be08a72 AE |
8414 | goto sp_rtnl_exit; |
8415 | ||
8416 | /* if stop on error is defined no recovery flows should be executed */ | |
8417 | #ifdef BNX2X_STOP_ON_ERROR | |
8418 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " | |
8419 | "so reset not done to allow debug dump,\n" | |
8420 | "you will need to reboot when done\n"); | |
b1fb8740 | 8421 | goto sp_rtnl_not_reset; |
7be08a72 | 8422 | #endif |
34f80b04 | 8423 | |
7be08a72 AE |
8424 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
8425 | /* | |
b1fb8740 VZ |
8426 | * Clear all pending SP commands as we are going to reset the |
8427 | * function anyway. | |
7be08a72 | 8428 | */ |
b1fb8740 VZ |
8429 | bp->sp_rtnl_state = 0; |
8430 | smp_mb(); | |
8431 | ||
72fd0718 | 8432 | bnx2x_parity_recover(bp); |
b1fb8740 VZ |
8433 | |
8434 | goto sp_rtnl_exit; | |
8435 | } | |
8436 | ||
8437 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
8438 | /* | |
8439 | * Clear all pending SP commands as we are going to reset the | |
8440 | * function anyway. | |
8441 | */ | |
8442 | bp->sp_rtnl_state = 0; | |
8443 | smp_mb(); | |
8444 | ||
72fd0718 VZ |
8445 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); |
8446 | bnx2x_nic_load(bp, LOAD_NORMAL); | |
b1fb8740 VZ |
8447 | |
8448 | goto sp_rtnl_exit; | |
72fd0718 | 8449 | } |
b1fb8740 VZ |
8450 | #ifdef BNX2X_STOP_ON_ERROR |
8451 | sp_rtnl_not_reset: | |
8452 | #endif | |
8453 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
8454 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
34f80b04 | 8455 | |
7be08a72 | 8456 | sp_rtnl_exit: |
34f80b04 EG |
8457 | rtnl_unlock(); |
8458 | } | |
8459 | ||
a2fbb9ea ET |
8460 | /* end of nic load/unload */ |
8461 | ||
3deb8167 YR |
8462 | static void bnx2x_period_task(struct work_struct *work) |
8463 | { | |
8464 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
8465 | ||
8466 | if (!netif_running(bp->dev)) | |
8467 | goto period_task_exit; | |
8468 | ||
8469 | if (CHIP_REV_IS_SLOW(bp)) { | |
8470 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
8471 | goto period_task_exit; | |
8472 | } | |
8473 | ||
8474 | bnx2x_acquire_phy_lock(bp); | |
8475 | /* | |
8476 | * The barrier is needed to ensure the ordering between the writing to | |
8477 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
8478 | * the reading here. | |
8479 | */ | |
8480 | smp_mb(); | |
8481 | if (bp->port.pmf) { | |
8482 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
8483 | ||
8484 | /* Re-queue task in 1 sec */ | |
8485 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
8486 | } | |
8487 | ||
8488 | bnx2x_release_phy_lock(bp); | |
8489 | period_task_exit: | |
8490 | return; | |
8491 | } | |
8492 | ||
a2fbb9ea ET |
8493 | /* |
8494 | * Init service functions | |
8495 | */ | |
8496 | ||
8d96286a | 8497 | static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
8498 | { |
8499 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
8500 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
8501 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
8502 | } |
8503 | ||
f2e0899f | 8504 | static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) |
f1ef27ef | 8505 | { |
f2e0899f | 8506 | u32 reg = bnx2x_get_pretend_reg(bp); |
f1ef27ef EG |
8507 | |
8508 | /* Flush all outstanding writes */ | |
8509 | mmiowb(); | |
8510 | ||
8511 | /* Pretend to be function 0 */ | |
8512 | REG_WR(bp, reg, 0); | |
f2e0899f | 8513 | REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ |
f1ef27ef EG |
8514 | |
8515 | /* From now we are in the "like-E1" mode */ | |
8516 | bnx2x_int_disable(bp); | |
8517 | ||
8518 | /* Flush all outstanding writes */ | |
8519 | mmiowb(); | |
8520 | ||
f2e0899f DK |
8521 | /* Restore the original function */ |
8522 | REG_WR(bp, reg, BP_ABS_FUNC(bp)); | |
8523 | REG_RD(bp, reg); | |
f1ef27ef EG |
8524 | } |
8525 | ||
f2e0899f | 8526 | static inline void bnx2x_undi_int_disable(struct bnx2x *bp) |
f1ef27ef | 8527 | { |
f2e0899f | 8528 | if (CHIP_IS_E1(bp)) |
f1ef27ef | 8529 | bnx2x_int_disable(bp); |
f2e0899f DK |
8530 | else |
8531 | bnx2x_undi_int_disable_e1h(bp); | |
f1ef27ef EG |
8532 | } |
8533 | ||
34f80b04 EG |
8534 | static void __devinit bnx2x_undi_unload(struct bnx2x *bp) |
8535 | { | |
8536 | u32 val; | |
8537 | ||
8538 | /* Check if there is any driver already loaded */ | |
8539 | val = REG_RD(bp, MISC_REG_UNPREPARED); | |
8540 | if (val == 0x1) { | |
8541 | /* Check if it is the UNDI driver | |
8542 | * UNDI driver initializes CID offset for normal bell to 0x7 | |
8543 | */ | |
4a37fb66 | 8544 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); |
34f80b04 EG |
8545 | val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); |
8546 | if (val == 0x7) { | |
8547 | u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
f2e0899f DK |
8548 | /* save our pf_num */ |
8549 | int orig_pf_num = bp->pf_num; | |
619c5cb6 VZ |
8550 | int port; |
8551 | u32 swap_en, swap_val, value; | |
34f80b04 | 8552 | |
b4661739 EG |
8553 | /* clear the UNDI indication */ |
8554 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
8555 | ||
34f80b04 EG |
8556 | BNX2X_DEV_INFO("UNDI is active! reset device\n"); |
8557 | ||
8558 | /* try unload UNDI on port 0 */ | |
f2e0899f | 8559 | bp->pf_num = 0; |
da5a662a | 8560 | bp->fw_seq = |
f2e0899f | 8561 | (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & |
da5a662a | 8562 | DRV_MSG_SEQ_NUMBER_MASK); |
a22f0788 | 8563 | reset_code = bnx2x_fw_command(bp, reset_code, 0); |
34f80b04 EG |
8564 | |
8565 | /* if UNDI is loaded on the other port */ | |
8566 | if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { | |
8567 | ||
da5a662a | 8568 | /* send "DONE" for previous unload */ |
a22f0788 YR |
8569 | bnx2x_fw_command(bp, |
8570 | DRV_MSG_CODE_UNLOAD_DONE, 0); | |
da5a662a VZ |
8571 | |
8572 | /* unload UNDI on port 1 */ | |
f2e0899f | 8573 | bp->pf_num = 1; |
da5a662a | 8574 | bp->fw_seq = |
f2e0899f | 8575 | (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & |
da5a662a VZ |
8576 | DRV_MSG_SEQ_NUMBER_MASK); |
8577 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
8578 | ||
a22f0788 | 8579 | bnx2x_fw_command(bp, reset_code, 0); |
34f80b04 EG |
8580 | } |
8581 | ||
b4661739 EG |
8582 | /* now it's safe to release the lock */ |
8583 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); | |
8584 | ||
f2e0899f | 8585 | bnx2x_undi_int_disable(bp); |
619c5cb6 | 8586 | port = BP_PORT(bp); |
da5a662a VZ |
8587 | |
8588 | /* close input traffic and wait for it */ | |
8589 | /* Do not rcv packets to BRB */ | |
619c5cb6 VZ |
8590 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : |
8591 | NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); | |
da5a662a VZ |
8592 | /* Do not direct rcv packets that are not for MCP to |
8593 | * the BRB */ | |
619c5cb6 VZ |
8594 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : |
8595 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
da5a662a | 8596 | /* clear AEU */ |
619c5cb6 VZ |
8597 | REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
8598 | MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); | |
da5a662a VZ |
8599 | msleep(10); |
8600 | ||
8601 | /* save NIG port swap info */ | |
8602 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
8603 | swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
34f80b04 EG |
8604 | /* reset device */ |
8605 | REG_WR(bp, | |
8606 | GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
da5a662a | 8607 | 0xd3ffffff); |
619c5cb6 VZ |
8608 | |
8609 | value = 0x1400; | |
8610 | if (CHIP_IS_E3(bp)) { | |
8611 | value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
8612 | value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
8613 | } | |
8614 | ||
34f80b04 EG |
8615 | REG_WR(bp, |
8616 | GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
619c5cb6 VZ |
8617 | value); |
8618 | ||
da5a662a VZ |
8619 | /* take the NIG out of reset and restore swap values */ |
8620 | REG_WR(bp, | |
8621 | GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
8622 | MISC_REGISTERS_RESET_REG_1_RST_NIG); | |
8623 | REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); | |
8624 | REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); | |
8625 | ||
8626 | /* send unload done to the MCP */ | |
a22f0788 | 8627 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); |
da5a662a VZ |
8628 | |
8629 | /* restore our func and fw_seq */ | |
f2e0899f | 8630 | bp->pf_num = orig_pf_num; |
da5a662a | 8631 | bp->fw_seq = |
f2e0899f | 8632 | (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & |
da5a662a | 8633 | DRV_MSG_SEQ_NUMBER_MASK); |
b4661739 EG |
8634 | } else |
8635 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); | |
34f80b04 EG |
8636 | } |
8637 | } | |
8638 | ||
8639 | static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) | |
8640 | { | |
8641 | u32 val, val2, val3, val4, id; | |
72ce58c3 | 8642 | u16 pmc; |
34f80b04 EG |
8643 | |
8644 | /* Get the chip revision id and number. */ | |
8645 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
8646 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
8647 | id = ((val & 0xffff) << 16); | |
8648 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
8649 | id |= ((val & 0xf) << 12); | |
8650 | val = REG_RD(bp, MISC_REG_CHIP_METAL); | |
8651 | id |= ((val & 0xff) << 4); | |
5a40e08e | 8652 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
8653 | id |= (val & 0xf); |
8654 | bp->common.chip_id = id; | |
523224a3 DK |
8655 | |
8656 | /* Set doorbell size */ | |
8657 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
8658 | ||
619c5cb6 | 8659 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8660 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
8661 | if ((val & 1) == 0) | |
8662 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
8663 | else | |
8664 | val = (val >> 1) & 1; | |
8665 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
8666 | "2_PORT_MODE"); | |
8667 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
8668 | CHIP_2_PORT_MODE; | |
8669 | ||
8670 | if (CHIP_MODE_IS_4_PORT(bp)) | |
8671 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
8672 | else | |
8673 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
8674 | } else { | |
8675 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
8676 | bp->pfid = bp->pf_num; /* 0..7 */ | |
8677 | } | |
8678 | ||
f2e0899f DK |
8679 | bp->link_params.chip_id = bp->common.chip_id; |
8680 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 8681 | |
1c06328c EG |
8682 | val = (REG_RD(bp, 0x2874) & 0x55); |
8683 | if ((bp->common.chip_id & 0x1) || | |
8684 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
8685 | bp->flags |= ONE_PORT_FLAG; | |
8686 | BNX2X_DEV_INFO("single port device\n"); | |
8687 | } | |
8688 | ||
34f80b04 | 8689 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 8690 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
8691 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
8692 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
8693 | bp->common.flash_size, bp->common.flash_size); | |
8694 | ||
1b6e2ceb DK |
8695 | bnx2x_init_shmem(bp); |
8696 | ||
619c5cb6 VZ |
8697 | |
8698 | ||
f2e0899f DK |
8699 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
8700 | MISC_REG_GENERIC_CR_1 : | |
8701 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 8702 | |
34f80b04 | 8703 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 8704 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
2691d51d EG |
8705 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
8706 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 8707 | |
f2e0899f | 8708 | if (!bp->common.shmem_base) { |
34f80b04 EG |
8709 | BNX2X_DEV_INFO("MCP not active\n"); |
8710 | bp->flags |= NO_MCP_FLAG; | |
8711 | return; | |
8712 | } | |
8713 | ||
34f80b04 | 8714 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 8715 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
8716 | |
8717 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
8718 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
8719 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
8720 | ||
c2c8b03e EG |
8721 | bp->link_params.feature_config_flags = 0; |
8722 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
8723 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
8724 | bp->link_params.feature_config_flags |= | |
8725 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
8726 | else | |
8727 | bp->link_params.feature_config_flags &= | |
8728 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
8729 | ||
34f80b04 EG |
8730 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
8731 | bp->common.bc_ver = val; | |
8732 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
8733 | if (val < BNX2X_BC_VER) { | |
8734 | /* for now only warn | |
8735 | * later we might need to enforce this */ | |
f2e0899f DK |
8736 | BNX2X_ERR("This driver needs bc_ver %X but found %X, " |
8737 | "please upgrade BC\n", BNX2X_BC_VER, val); | |
34f80b04 | 8738 | } |
4d295db0 | 8739 | bp->link_params.feature_config_flags |= |
a22f0788 | 8740 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
8741 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
8742 | ||
a22f0788 YR |
8743 | bp->link_params.feature_config_flags |= |
8744 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
8745 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
72ce58c3 | 8746 | |
85242eea YR |
8747 | bp->link_params.feature_config_flags |= |
8748 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
8749 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
8750 | ||
f9a3ebbe DK |
8751 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); |
8752 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; | |
8753 | ||
72ce58c3 | 8754 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 8755 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
8756 | |
8757 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
8758 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
8759 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
8760 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
8761 | ||
cdaa7cb8 VZ |
8762 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
8763 | val, val2, val3, val4); | |
34f80b04 EG |
8764 | } |
8765 | ||
f2e0899f DK |
8766 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
8767 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
8768 | ||
8769 | static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) | |
8770 | { | |
8771 | int pfid = BP_FUNC(bp); | |
8772 | int vn = BP_E1HVN(bp); | |
8773 | int igu_sb_id; | |
8774 | u32 val; | |
6383c0b3 | 8775 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
8776 | |
8777 | bp->igu_base_sb = 0xff; | |
f2e0899f | 8778 | if (CHIP_INT_MODE_IS_BC(bp)) { |
6383c0b3 | 8779 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
8780 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
8781 | FP_SB_MAX_E1x; | |
8782 | ||
8783 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
8784 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
8785 | ||
8786 | return; | |
8787 | } | |
8788 | ||
8789 | /* IGU in normal mode - read CAM */ | |
8790 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
8791 | igu_sb_id++) { | |
8792 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
8793 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
8794 | continue; | |
8795 | fid = IGU_FID(val); | |
8796 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
8797 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
8798 | continue; | |
8799 | if (IGU_VEC(val) == 0) | |
8800 | /* default status block */ | |
8801 | bp->igu_dsb_id = igu_sb_id; | |
8802 | else { | |
8803 | if (bp->igu_base_sb == 0xff) | |
8804 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 8805 | igu_sb_cnt++; |
f2e0899f DK |
8806 | } |
8807 | } | |
8808 | } | |
619c5cb6 | 8809 | |
6383c0b3 AE |
8810 | #ifdef CONFIG_PCI_MSI |
8811 | /* | |
8812 | * It's expected that number of CAM entries for this functions is equal | |
8813 | * to the number evaluated based on the MSI-X table size. We want a | |
8814 | * harsh warning if these values are different! | |
619c5cb6 | 8815 | */ |
6383c0b3 AE |
8816 | WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); |
8817 | #endif | |
619c5cb6 | 8818 | |
6383c0b3 | 8819 | if (igu_sb_cnt == 0) |
f2e0899f DK |
8820 | BNX2X_ERR("CAM configuration error\n"); |
8821 | } | |
8822 | ||
34f80b04 EG |
8823 | static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, |
8824 | u32 switch_cfg) | |
a2fbb9ea | 8825 | { |
a22f0788 YR |
8826 | int cfg_size = 0, idx, port = BP_PORT(bp); |
8827 | ||
8828 | /* Aggregation of supported attributes of all external phys */ | |
8829 | bp->port.supported[0] = 0; | |
8830 | bp->port.supported[1] = 0; | |
b7737c9b YR |
8831 | switch (bp->link_params.num_phys) { |
8832 | case 1: | |
a22f0788 YR |
8833 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
8834 | cfg_size = 1; | |
8835 | break; | |
b7737c9b | 8836 | case 2: |
a22f0788 YR |
8837 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
8838 | cfg_size = 1; | |
8839 | break; | |
8840 | case 3: | |
8841 | if (bp->link_params.multi_phy_config & | |
8842 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
8843 | bp->port.supported[1] = | |
8844 | bp->link_params.phy[EXT_PHY1].supported; | |
8845 | bp->port.supported[0] = | |
8846 | bp->link_params.phy[EXT_PHY2].supported; | |
8847 | } else { | |
8848 | bp->port.supported[0] = | |
8849 | bp->link_params.phy[EXT_PHY1].supported; | |
8850 | bp->port.supported[1] = | |
8851 | bp->link_params.phy[EXT_PHY2].supported; | |
8852 | } | |
8853 | cfg_size = 2; | |
8854 | break; | |
b7737c9b | 8855 | } |
a2fbb9ea | 8856 | |
a22f0788 | 8857 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
b7737c9b | 8858 | BNX2X_ERR("NVRAM config error. BAD phy config." |
a22f0788 | 8859 | "PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 8860 | SHMEM_RD(bp, |
a22f0788 YR |
8861 | dev_info.port_hw_config[port].external_phy_config), |
8862 | SHMEM_RD(bp, | |
8863 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 8864 | return; |
f85582f8 | 8865 | } |
a2fbb9ea | 8866 | |
619c5cb6 VZ |
8867 | if (CHIP_IS_E3(bp)) |
8868 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
8869 | else { | |
8870 | switch (switch_cfg) { | |
8871 | case SWITCH_CFG_1G: | |
8872 | bp->port.phy_addr = REG_RD( | |
8873 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
8874 | break; | |
8875 | case SWITCH_CFG_10G: | |
8876 | bp->port.phy_addr = REG_RD( | |
8877 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
8878 | break; | |
8879 | default: | |
8880 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
8881 | bp->port.link_config[0]); | |
8882 | return; | |
8883 | } | |
a2fbb9ea | 8884 | } |
619c5cb6 | 8885 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
8886 | /* mask what we support according to speed_cap_mask per configuration */ |
8887 | for (idx = 0; idx < cfg_size; idx++) { | |
8888 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 8889 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 8890 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 8891 | |
a22f0788 | 8892 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8893 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 8894 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 8895 | |
a22f0788 | 8896 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8897 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 8898 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 8899 | |
a22f0788 | 8900 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8901 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 8902 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 8903 | |
a22f0788 | 8904 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8905 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 8906 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 8907 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 8908 | |
a22f0788 | 8909 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8910 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 8911 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 8912 | |
a22f0788 | 8913 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8914 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 YR |
8915 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
8916 | ||
8917 | } | |
a2fbb9ea | 8918 | |
a22f0788 YR |
8919 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
8920 | bp->port.supported[1]); | |
a2fbb9ea ET |
8921 | } |
8922 | ||
34f80b04 | 8923 | static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 8924 | { |
a22f0788 YR |
8925 | u32 link_config, idx, cfg_size = 0; |
8926 | bp->port.advertising[0] = 0; | |
8927 | bp->port.advertising[1] = 0; | |
8928 | switch (bp->link_params.num_phys) { | |
8929 | case 1: | |
8930 | case 2: | |
8931 | cfg_size = 1; | |
8932 | break; | |
8933 | case 3: | |
8934 | cfg_size = 2; | |
8935 | break; | |
8936 | } | |
8937 | for (idx = 0; idx < cfg_size; idx++) { | |
8938 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
8939 | link_config = bp->port.link_config[idx]; | |
8940 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 8941 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
8942 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
8943 | bp->link_params.req_line_speed[idx] = | |
8944 | SPEED_AUTO_NEG; | |
8945 | bp->port.advertising[idx] |= | |
8946 | bp->port.supported[idx]; | |
f85582f8 DK |
8947 | } else { |
8948 | /* force 10G, no AN */ | |
a22f0788 YR |
8949 | bp->link_params.req_line_speed[idx] = |
8950 | SPEED_10000; | |
8951 | bp->port.advertising[idx] |= | |
8952 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 8953 | ADVERTISED_FIBRE); |
a22f0788 | 8954 | continue; |
f85582f8 DK |
8955 | } |
8956 | break; | |
a2fbb9ea | 8957 | |
f85582f8 | 8958 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
8959 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
8960 | bp->link_params.req_line_speed[idx] = | |
8961 | SPEED_10; | |
8962 | bp->port.advertising[idx] |= | |
8963 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
8964 | ADVERTISED_TP); |
8965 | } else { | |
754a2f52 | 8966 | BNX2X_ERR("NVRAM config error. " |
f85582f8 DK |
8967 | "Invalid link_config 0x%x" |
8968 | " speed_cap_mask 0x%x\n", | |
8969 | link_config, | |
a22f0788 | 8970 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
8971 | return; |
8972 | } | |
8973 | break; | |
a2fbb9ea | 8974 | |
f85582f8 | 8975 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
8976 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
8977 | bp->link_params.req_line_speed[idx] = | |
8978 | SPEED_10; | |
8979 | bp->link_params.req_duplex[idx] = | |
8980 | DUPLEX_HALF; | |
8981 | bp->port.advertising[idx] |= | |
8982 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
8983 | ADVERTISED_TP); |
8984 | } else { | |
754a2f52 | 8985 | BNX2X_ERR("NVRAM config error. " |
f85582f8 DK |
8986 | "Invalid link_config 0x%x" |
8987 | " speed_cap_mask 0x%x\n", | |
8988 | link_config, | |
8989 | bp->link_params.speed_cap_mask[idx]); | |
8990 | return; | |
8991 | } | |
8992 | break; | |
a2fbb9ea | 8993 | |
f85582f8 DK |
8994 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
8995 | if (bp->port.supported[idx] & | |
8996 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
8997 | bp->link_params.req_line_speed[idx] = |
8998 | SPEED_100; | |
8999 | bp->port.advertising[idx] |= | |
9000 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
9001 | ADVERTISED_TP); |
9002 | } else { | |
754a2f52 | 9003 | BNX2X_ERR("NVRAM config error. " |
f85582f8 DK |
9004 | "Invalid link_config 0x%x" |
9005 | " speed_cap_mask 0x%x\n", | |
9006 | link_config, | |
9007 | bp->link_params.speed_cap_mask[idx]); | |
9008 | return; | |
9009 | } | |
9010 | break; | |
a2fbb9ea | 9011 | |
f85582f8 DK |
9012 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
9013 | if (bp->port.supported[idx] & | |
9014 | SUPPORTED_100baseT_Half) { | |
9015 | bp->link_params.req_line_speed[idx] = | |
9016 | SPEED_100; | |
9017 | bp->link_params.req_duplex[idx] = | |
9018 | DUPLEX_HALF; | |
a22f0788 YR |
9019 | bp->port.advertising[idx] |= |
9020 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
9021 | ADVERTISED_TP); |
9022 | } else { | |
754a2f52 | 9023 | BNX2X_ERR("NVRAM config error. " |
cdaa7cb8 VZ |
9024 | "Invalid link_config 0x%x" |
9025 | " speed_cap_mask 0x%x\n", | |
a22f0788 YR |
9026 | link_config, |
9027 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
9028 | return; |
9029 | } | |
9030 | break; | |
a2fbb9ea | 9031 | |
f85582f8 | 9032 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
9033 | if (bp->port.supported[idx] & |
9034 | SUPPORTED_1000baseT_Full) { | |
9035 | bp->link_params.req_line_speed[idx] = | |
9036 | SPEED_1000; | |
9037 | bp->port.advertising[idx] |= | |
9038 | (ADVERTISED_1000baseT_Full | | |
f85582f8 DK |
9039 | ADVERTISED_TP); |
9040 | } else { | |
754a2f52 | 9041 | BNX2X_ERR("NVRAM config error. " |
cdaa7cb8 VZ |
9042 | "Invalid link_config 0x%x" |
9043 | " speed_cap_mask 0x%x\n", | |
a22f0788 YR |
9044 | link_config, |
9045 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
9046 | return; |
9047 | } | |
9048 | break; | |
a2fbb9ea | 9049 | |
f85582f8 | 9050 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
9051 | if (bp->port.supported[idx] & |
9052 | SUPPORTED_2500baseX_Full) { | |
9053 | bp->link_params.req_line_speed[idx] = | |
9054 | SPEED_2500; | |
9055 | bp->port.advertising[idx] |= | |
9056 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 9057 | ADVERTISED_TP); |
f85582f8 | 9058 | } else { |
754a2f52 | 9059 | BNX2X_ERR("NVRAM config error. " |
cdaa7cb8 VZ |
9060 | "Invalid link_config 0x%x" |
9061 | " speed_cap_mask 0x%x\n", | |
a22f0788 | 9062 | link_config, |
f85582f8 DK |
9063 | bp->link_params.speed_cap_mask[idx]); |
9064 | return; | |
9065 | } | |
9066 | break; | |
a2fbb9ea | 9067 | |
f85582f8 | 9068 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
9069 | if (bp->port.supported[idx] & |
9070 | SUPPORTED_10000baseT_Full) { | |
9071 | bp->link_params.req_line_speed[idx] = | |
9072 | SPEED_10000; | |
9073 | bp->port.advertising[idx] |= | |
9074 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 9075 | ADVERTISED_FIBRE); |
f85582f8 | 9076 | } else { |
754a2f52 | 9077 | BNX2X_ERR("NVRAM config error. " |
cdaa7cb8 VZ |
9078 | "Invalid link_config 0x%x" |
9079 | " speed_cap_mask 0x%x\n", | |
a22f0788 | 9080 | link_config, |
f85582f8 DK |
9081 | bp->link_params.speed_cap_mask[idx]); |
9082 | return; | |
9083 | } | |
9084 | break; | |
3c9ada22 YR |
9085 | case PORT_FEATURE_LINK_SPEED_20G: |
9086 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 9087 | |
3c9ada22 | 9088 | break; |
f85582f8 | 9089 | default: |
754a2f52 DK |
9090 | BNX2X_ERR("NVRAM config error. " |
9091 | "BAD link speed link_config 0x%x\n", | |
9092 | link_config); | |
f85582f8 DK |
9093 | bp->link_params.req_line_speed[idx] = |
9094 | SPEED_AUTO_NEG; | |
9095 | bp->port.advertising[idx] = | |
9096 | bp->port.supported[idx]; | |
9097 | break; | |
9098 | } | |
a2fbb9ea | 9099 | |
a22f0788 | 9100 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 9101 | PORT_FEATURE_FLOW_CONTROL_MASK); |
a22f0788 YR |
9102 | if ((bp->link_params.req_flow_ctrl[idx] == |
9103 | BNX2X_FLOW_CTRL_AUTO) && | |
9104 | !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { | |
9105 | bp->link_params.req_flow_ctrl[idx] = | |
9106 | BNX2X_FLOW_CTRL_NONE; | |
9107 | } | |
a2fbb9ea | 9108 | |
a22f0788 YR |
9109 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" |
9110 | " 0x%x advertising 0x%x\n", | |
9111 | bp->link_params.req_line_speed[idx], | |
9112 | bp->link_params.req_duplex[idx], | |
9113 | bp->link_params.req_flow_ctrl[idx], | |
9114 | bp->port.advertising[idx]); | |
9115 | } | |
a2fbb9ea ET |
9116 | } |
9117 | ||
e665bfda MC |
9118 | static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
9119 | { | |
9120 | mac_hi = cpu_to_be16(mac_hi); | |
9121 | mac_lo = cpu_to_be32(mac_lo); | |
9122 | memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); | |
9123 | memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); | |
9124 | } | |
9125 | ||
34f80b04 | 9126 | static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 9127 | { |
34f80b04 | 9128 | int port = BP_PORT(bp); |
589abe3a | 9129 | u32 config; |
6f38ad93 | 9130 | u32 ext_phy_type, ext_phy_config; |
a2fbb9ea | 9131 | |
c18487ee | 9132 | bp->link_params.bp = bp; |
34f80b04 | 9133 | bp->link_params.port = port; |
c18487ee | 9134 | |
c18487ee | 9135 | bp->link_params.lane_config = |
a2fbb9ea | 9136 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 9137 | |
a22f0788 | 9138 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea ET |
9139 | SHMEM_RD(bp, |
9140 | dev_info.port_hw_config[port].speed_capability_mask); | |
a22f0788 YR |
9141 | bp->link_params.speed_cap_mask[1] = |
9142 | SHMEM_RD(bp, | |
9143 | dev_info.port_hw_config[port].speed_capability_mask2); | |
9144 | bp->port.link_config[0] = | |
a2fbb9ea ET |
9145 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
9146 | ||
a22f0788 YR |
9147 | bp->port.link_config[1] = |
9148 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 9149 | |
a22f0788 YR |
9150 | bp->link_params.multi_phy_config = |
9151 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
9152 | /* If the device is capable of WoL, set the default state according |
9153 | * to the HW | |
9154 | */ | |
4d295db0 | 9155 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
9156 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
9157 | (config & PORT_FEATURE_WOL_ENABLED)); | |
9158 | ||
f85582f8 | 9159 | BNX2X_DEV_INFO("lane_config 0x%08x " |
a22f0788 | 9160 | "speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 9161 | bp->link_params.lane_config, |
a22f0788 YR |
9162 | bp->link_params.speed_cap_mask[0], |
9163 | bp->port.link_config[0]); | |
a2fbb9ea | 9164 | |
a22f0788 | 9165 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 9166 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 9167 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 9168 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
9169 | |
9170 | bnx2x_link_settings_requested(bp); | |
9171 | ||
01cd4528 EG |
9172 | /* |
9173 | * If connected directly, work with the internal PHY, otherwise, work | |
9174 | * with the external PHY | |
9175 | */ | |
b7737c9b YR |
9176 | ext_phy_config = |
9177 | SHMEM_RD(bp, | |
9178 | dev_info.port_hw_config[port].external_phy_config); | |
9179 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 9180 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 9181 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
9182 | |
9183 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
9184 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
9185 | bp->mdio.prtad = | |
b7737c9b | 9186 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d YR |
9187 | |
9188 | /* | |
9189 | * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) | |
9190 | * In MF mode, it is set to cover self test cases | |
9191 | */ | |
9192 | if (IS_MF(bp)) | |
9193 | bp->port.need_hw_lock = 1; | |
9194 | else | |
9195 | bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, | |
9196 | bp->common.shmem_base, | |
9197 | bp->common.shmem2_base); | |
0793f83f | 9198 | } |
01cd4528 | 9199 | |
2ba45142 VZ |
9200 | #ifdef BCM_CNIC |
9201 | static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) | |
9202 | { | |
bf61ee14 VZ |
9203 | int port = BP_PORT(bp); |
9204 | int func = BP_ABS_FUNC(bp); | |
9205 | ||
2ba45142 | 9206 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 9207 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 9208 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 9209 | drv_lic_key[port].max_fcoe_conn); |
2ba45142 VZ |
9210 | |
9211 | /* Get the number of maximum allowed iSCSI and FCoE connections */ | |
9212 | bp->cnic_eth_dev.max_iscsi_conn = | |
9213 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
9214 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
9215 | ||
9216 | bp->cnic_eth_dev.max_fcoe_conn = | |
9217 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
9218 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
9219 | ||
bf61ee14 VZ |
9220 | /* Read the WWN: */ |
9221 | if (!IS_MF(bp)) { | |
9222 | /* Port info */ | |
9223 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
9224 | SHMEM_RD(bp, | |
9225 | dev_info.port_hw_config[port]. | |
9226 | fcoe_wwn_port_name_upper); | |
9227 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
9228 | SHMEM_RD(bp, | |
9229 | dev_info.port_hw_config[port]. | |
9230 | fcoe_wwn_port_name_lower); | |
9231 | ||
9232 | /* Node info */ | |
9233 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
9234 | SHMEM_RD(bp, | |
9235 | dev_info.port_hw_config[port]. | |
9236 | fcoe_wwn_node_name_upper); | |
9237 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
9238 | SHMEM_RD(bp, | |
9239 | dev_info.port_hw_config[port]. | |
9240 | fcoe_wwn_node_name_lower); | |
9241 | } else if (!IS_MF_SD(bp)) { | |
9242 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); | |
9243 | ||
9244 | /* | |
9245 | * Read the WWN info only if the FCoE feature is enabled for | |
9246 | * this function. | |
9247 | */ | |
9248 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
9249 | /* Port info */ | |
9250 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
9251 | MF_CFG_RD(bp, func_ext_config[func]. | |
9252 | fcoe_wwn_port_name_upper); | |
9253 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
9254 | MF_CFG_RD(bp, func_ext_config[func]. | |
9255 | fcoe_wwn_port_name_lower); | |
9256 | ||
9257 | /* Node info */ | |
9258 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
9259 | MF_CFG_RD(bp, func_ext_config[func]. | |
9260 | fcoe_wwn_node_name_upper); | |
9261 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
9262 | MF_CFG_RD(bp, func_ext_config[func]. | |
9263 | fcoe_wwn_node_name_lower); | |
9264 | } | |
9265 | } | |
9266 | ||
2ba45142 VZ |
9267 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n", |
9268 | bp->cnic_eth_dev.max_iscsi_conn, | |
9269 | bp->cnic_eth_dev.max_fcoe_conn); | |
9270 | ||
bf61ee14 VZ |
9271 | /* |
9272 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
9273 | * disable the feature. |
9274 | */ | |
9275 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9276 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; | |
9277 | ||
9278 | if (!bp->cnic_eth_dev.max_fcoe_conn) | |
9279 | bp->flags |= NO_FCOE_FLAG; | |
9280 | } | |
9281 | #endif | |
9282 | ||
0793f83f DK |
9283 | static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
9284 | { | |
9285 | u32 val, val2; | |
9286 | int func = BP_ABS_FUNC(bp); | |
9287 | int port = BP_PORT(bp); | |
2ba45142 VZ |
9288 | #ifdef BCM_CNIC |
9289 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; | |
9290 | u8 *fip_mac = bp->fip_mac; | |
9291 | #endif | |
0793f83f | 9292 | |
619c5cb6 VZ |
9293 | /* Zero primary MAC configuration */ |
9294 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
9295 | ||
0793f83f DK |
9296 | if (BP_NOMCP(bp)) { |
9297 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
9298 | random_ether_addr(bp->dev->dev_addr); | |
9299 | } else if (IS_MF(bp)) { | |
9300 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
9301 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
9302 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
9303 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
9304 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
37b091ba MC |
9305 | |
9306 | #ifdef BCM_CNIC | |
2ba45142 VZ |
9307 | /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or |
9308 | * FCoE MAC then the appropriate feature should be disabled. | |
9309 | */ | |
0793f83f DK |
9310 | if (IS_MF_SI(bp)) { |
9311 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); | |
9312 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
9313 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
9314 | iscsi_mac_addr_upper); | |
9315 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
9316 | iscsi_mac_addr_lower); | |
2ba45142 | 9317 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
0f9dad10 JP |
9318 | BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", |
9319 | iscsi_mac); | |
2ba45142 VZ |
9320 | } else |
9321 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; | |
9322 | ||
9323 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
9324 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
9325 | fcoe_mac_addr_upper); | |
9326 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
9327 | fcoe_mac_addr_lower); | |
2ba45142 | 9328 | bnx2x_set_mac_buf(fip_mac, val, val2); |
0f9dad10 JP |
9329 | BNX2X_DEV_INFO("Read FCoE L2 MAC to %pM\n", |
9330 | fip_mac); | |
2ba45142 | 9331 | |
2ba45142 VZ |
9332 | } else |
9333 | bp->flags |= NO_FCOE_FLAG; | |
0793f83f | 9334 | } |
37b091ba | 9335 | #endif |
0793f83f DK |
9336 | } else { |
9337 | /* in SF read MACs from port configuration */ | |
9338 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
9339 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
9340 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
9341 | ||
9342 | #ifdef BCM_CNIC | |
9343 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9344 | iscsi_mac_upper); | |
9345 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9346 | iscsi_mac_lower); | |
2ba45142 | 9347 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
9348 | |
9349 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9350 | fcoe_fip_mac_upper); | |
9351 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9352 | fcoe_fip_mac_lower); | |
9353 | bnx2x_set_mac_buf(fip_mac, val, val2); | |
0793f83f DK |
9354 | #endif |
9355 | } | |
9356 | ||
9357 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); | |
9358 | memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); | |
9359 | ||
ec6ba945 | 9360 | #ifdef BCM_CNIC |
c03bd39c VZ |
9361 | /* Set the FCoE MAC in MF_SD mode */ |
9362 | if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp)) | |
9363 | memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); | |
426b9241 DK |
9364 | |
9365 | /* Disable iSCSI if MAC configuration is | |
9366 | * invalid. | |
9367 | */ | |
9368 | if (!is_valid_ether_addr(iscsi_mac)) { | |
9369 | bp->flags |= NO_ISCSI_FLAG; | |
9370 | memset(iscsi_mac, 0, ETH_ALEN); | |
9371 | } | |
9372 | ||
9373 | /* Disable FCoE if MAC configuration is | |
9374 | * invalid. | |
9375 | */ | |
9376 | if (!is_valid_ether_addr(fip_mac)) { | |
9377 | bp->flags |= NO_FCOE_FLAG; | |
9378 | memset(bp->fip_mac, 0, ETH_ALEN); | |
9379 | } | |
ec6ba945 | 9380 | #endif |
619c5cb6 VZ |
9381 | |
9382 | if (!is_valid_ether_addr(bp->dev->dev_addr)) | |
9383 | dev_err(&bp->pdev->dev, | |
9384 | "bad Ethernet MAC address configuration: " | |
0f9dad10 | 9385 | "%pM, change it manually before bringing up " |
619c5cb6 | 9386 | "the appropriate network interface\n", |
0f9dad10 | 9387 | bp->dev->dev_addr); |
34f80b04 EG |
9388 | } |
9389 | ||
9390 | static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |
9391 | { | |
0793f83f | 9392 | int /*abs*/func = BP_ABS_FUNC(bp); |
b8ee8328 | 9393 | int vn; |
0793f83f | 9394 | u32 val = 0; |
34f80b04 | 9395 | int rc = 0; |
a2fbb9ea | 9396 | |
34f80b04 | 9397 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 9398 | |
6383c0b3 AE |
9399 | /* |
9400 | * initialize IGU parameters | |
9401 | */ | |
f2e0899f DK |
9402 | if (CHIP_IS_E1x(bp)) { |
9403 | bp->common.int_block = INT_BLOCK_HC; | |
9404 | ||
9405 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
9406 | bp->igu_base_sb = 0; | |
f2e0899f DK |
9407 | } else { |
9408 | bp->common.int_block = INT_BLOCK_IGU; | |
9409 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); | |
619c5cb6 VZ |
9410 | |
9411 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
9412 | int tout = 5000; | |
9413 | ||
9414 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
9415 | ||
9416 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
9417 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
9418 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
9419 | ||
9420 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
9421 | tout--; | |
9422 | usleep_range(1000, 1000); | |
9423 | } | |
9424 | ||
9425 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
9426 | dev_err(&bp->pdev->dev, | |
9427 | "FORCING Normal Mode failed!!!\n"); | |
9428 | return -EPERM; | |
9429 | } | |
9430 | } | |
9431 | ||
f2e0899f | 9432 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 9433 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
9434 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
9435 | } else | |
619c5cb6 | 9436 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 9437 | |
f2e0899f DK |
9438 | bnx2x_get_igu_cam_info(bp); |
9439 | ||
9440 | } | |
619c5cb6 VZ |
9441 | |
9442 | /* | |
9443 | * set base FW non-default (fast path) status block id, this value is | |
9444 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
9445 | * determine the id used by the FW. | |
9446 | */ | |
9447 | if (CHIP_IS_E1x(bp)) | |
9448 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
9449 | else /* | |
9450 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
9451 | * the same queue are indicated on the same IGU SB). So we prefer | |
9452 | * FW and IGU SBs to be the same value. | |
9453 | */ | |
9454 | bp->base_fw_ndsb = bp->igu_base_sb; | |
9455 | ||
9456 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
9457 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
9458 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
9459 | |
9460 | /* | |
9461 | * Initialize MF configuration | |
9462 | */ | |
523224a3 | 9463 | |
fb3bff17 DK |
9464 | bp->mf_ov = 0; |
9465 | bp->mf_mode = 0; | |
f2e0899f | 9466 | vn = BP_E1HVN(bp); |
0793f83f | 9467 | |
f2e0899f | 9468 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
9469 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
9470 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
9471 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
9472 | ||
f2e0899f DK |
9473 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
9474 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
9475 | else | |
9476 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
9477 | offsetof(struct shmem_region, func_mb) + |
9478 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
9479 | /* |
9480 | * get mf configuration: | |
25985edc | 9481 | * 1. existence of MF configuration |
0793f83f DK |
9482 | * 2. MAC address must be legal (check only upper bytes) |
9483 | * for Switch-Independent mode; | |
9484 | * OVLAN must be legal for Switch-Dependent mode | |
9485 | * 3. SF_MODE configures specific MF mode | |
9486 | */ | |
9487 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
9488 | /* get mf configuration */ | |
9489 | val = SHMEM_RD(bp, | |
9490 | dev_info.shared_feature_config.config); | |
9491 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
9492 | ||
9493 | switch (val) { | |
9494 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
9495 | val = MF_CFG_RD(bp, func_mf_config[func]. | |
9496 | mac_upper); | |
9497 | /* check for legal mac (upper bytes)*/ | |
9498 | if (val != 0xffff) { | |
9499 | bp->mf_mode = MULTI_FUNCTION_SI; | |
9500 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
9501 | func_mf_config[func].config); | |
9502 | } else | |
619c5cb6 VZ |
9503 | BNX2X_DEV_INFO("illegal MAC address " |
9504 | "for SI\n"); | |
0793f83f DK |
9505 | break; |
9506 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: | |
9507 | /* get OV configuration */ | |
9508 | val = MF_CFG_RD(bp, | |
9509 | func_mf_config[FUNC_0].e1hov_tag); | |
9510 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
9511 | ||
9512 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
9513 | bp->mf_mode = MULTI_FUNCTION_SD; | |
9514 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
9515 | func_mf_config[func].config); | |
9516 | } else | |
754a2f52 | 9517 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f DK |
9518 | break; |
9519 | default: | |
9520 | /* Unknown configuration: reset mf_config */ | |
9521 | bp->mf_config[vn] = 0; | |
754a2f52 | 9522 | BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); |
0793f83f DK |
9523 | } |
9524 | } | |
a2fbb9ea | 9525 | |
2691d51d | 9526 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 9527 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 9528 | |
0793f83f DK |
9529 | switch (bp->mf_mode) { |
9530 | case MULTI_FUNCTION_SD: | |
9531 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
9532 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 9533 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 9534 | bp->mf_ov = val; |
619c5cb6 VZ |
9535 | bp->path_has_ovlan = true; |
9536 | ||
9537 | BNX2X_DEV_INFO("MF OV for func %d is %d " | |
9538 | "(0x%04x)\n", func, bp->mf_ov, | |
9539 | bp->mf_ov); | |
2691d51d | 9540 | } else { |
619c5cb6 VZ |
9541 | dev_err(&bp->pdev->dev, |
9542 | "No valid MF OV for func %d, " | |
9543 | "aborting\n", func); | |
9544 | return -EPERM; | |
34f80b04 | 9545 | } |
0793f83f DK |
9546 | break; |
9547 | case MULTI_FUNCTION_SI: | |
9548 | BNX2X_DEV_INFO("func %d is in MF " | |
9549 | "switch-independent mode\n", func); | |
9550 | break; | |
9551 | default: | |
9552 | if (vn) { | |
619c5cb6 VZ |
9553 | dev_err(&bp->pdev->dev, |
9554 | "VN %d is in a single function mode, " | |
9555 | "aborting\n", vn); | |
9556 | return -EPERM; | |
2691d51d | 9557 | } |
0793f83f | 9558 | break; |
34f80b04 | 9559 | } |
0793f83f | 9560 | |
619c5cb6 VZ |
9561 | /* check if other port on the path needs ovlan: |
9562 | * Since MF configuration is shared between ports | |
9563 | * Possible mixed modes are only | |
9564 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
9565 | */ | |
9566 | if (CHIP_MODE_IS_4_PORT(bp) && | |
9567 | !bp->path_has_ovlan && | |
9568 | !IS_MF(bp) && | |
9569 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
9570 | u8 other_port = !BP_PORT(bp); | |
9571 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
9572 | val = MF_CFG_RD(bp, | |
9573 | func_mf_config[other_func].e1hov_tag); | |
9574 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
9575 | bp->path_has_ovlan = true; | |
9576 | } | |
34f80b04 | 9577 | } |
a2fbb9ea | 9578 | |
f2e0899f DK |
9579 | /* adjust igu_sb_cnt to MF for E1x */ |
9580 | if (CHIP_IS_E1x(bp) && IS_MF(bp)) | |
523224a3 DK |
9581 | bp->igu_sb_cnt /= E1HVN_MAX; |
9582 | ||
619c5cb6 VZ |
9583 | /* port info */ |
9584 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 9585 | |
34f80b04 | 9586 | if (!BP_NOMCP(bp)) { |
f2e0899f DK |
9587 | bp->fw_seq = |
9588 | (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
9589 | DRV_MSG_SEQ_NUMBER_MASK); | |
34f80b04 EG |
9590 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); |
9591 | } | |
9592 | ||
0793f83f DK |
9593 | /* Get MAC addresses */ |
9594 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 9595 | |
2ba45142 VZ |
9596 | #ifdef BCM_CNIC |
9597 | bnx2x_get_cnic_info(bp); | |
9598 | #endif | |
9599 | ||
619c5cb6 VZ |
9600 | /* Get current FW pulse sequence */ |
9601 | if (!BP_NOMCP(bp)) { | |
9602 | int mb_idx = BP_FW_MB_IDX(bp); | |
9603 | ||
9604 | bp->fw_drv_pulse_wr_seq = | |
9605 | (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) & | |
9606 | DRV_PULSE_SEQ_MASK); | |
9607 | BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); | |
9608 | } | |
9609 | ||
34f80b04 EG |
9610 | return rc; |
9611 | } | |
9612 | ||
34f24c7f VZ |
9613 | static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) |
9614 | { | |
9615 | int cnt, i, block_end, rodi; | |
9616 | char vpd_data[BNX2X_VPD_LEN+1]; | |
9617 | char str_id_reg[VENDOR_ID_LEN+1]; | |
9618 | char str_id_cap[VENDOR_ID_LEN+1]; | |
9619 | u8 len; | |
9620 | ||
9621 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data); | |
9622 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); | |
9623 | ||
9624 | if (cnt < BNX2X_VPD_LEN) | |
9625 | goto out_not_found; | |
9626 | ||
9627 | i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN, | |
9628 | PCI_VPD_LRDT_RO_DATA); | |
9629 | if (i < 0) | |
9630 | goto out_not_found; | |
9631 | ||
9632 | ||
9633 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + | |
9634 | pci_vpd_lrdt_size(&vpd_data[i]); | |
9635 | ||
9636 | i += PCI_VPD_LRDT_TAG_SIZE; | |
9637 | ||
9638 | if (block_end > BNX2X_VPD_LEN) | |
9639 | goto out_not_found; | |
9640 | ||
9641 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
9642 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
9643 | if (rodi < 0) | |
9644 | goto out_not_found; | |
9645 | ||
9646 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
9647 | ||
9648 | if (len != VENDOR_ID_LEN) | |
9649 | goto out_not_found; | |
9650 | ||
9651 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
9652 | ||
9653 | /* vendor specific info */ | |
9654 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
9655 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
9656 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
9657 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
9658 | ||
9659 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
9660 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
9661 | if (rodi >= 0) { | |
9662 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
9663 | ||
9664 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
9665 | ||
9666 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
9667 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
9668 | bp->fw_ver[len] = ' '; | |
9669 | } | |
9670 | } | |
9671 | return; | |
9672 | } | |
9673 | out_not_found: | |
9674 | return; | |
9675 | } | |
9676 | ||
619c5cb6 VZ |
9677 | static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) |
9678 | { | |
9679 | u32 flags = 0; | |
9680 | ||
9681 | if (CHIP_REV_IS_FPGA(bp)) | |
9682 | SET_FLAGS(flags, MODE_FPGA); | |
9683 | else if (CHIP_REV_IS_EMUL(bp)) | |
9684 | SET_FLAGS(flags, MODE_EMUL); | |
9685 | else | |
9686 | SET_FLAGS(flags, MODE_ASIC); | |
9687 | ||
9688 | if (CHIP_MODE_IS_4_PORT(bp)) | |
9689 | SET_FLAGS(flags, MODE_PORT4); | |
9690 | else | |
9691 | SET_FLAGS(flags, MODE_PORT2); | |
9692 | ||
9693 | if (CHIP_IS_E2(bp)) | |
9694 | SET_FLAGS(flags, MODE_E2); | |
9695 | else if (CHIP_IS_E3(bp)) { | |
9696 | SET_FLAGS(flags, MODE_E3); | |
9697 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
9698 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
9699 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
9700 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
9701 | } |
9702 | ||
9703 | if (IS_MF(bp)) { | |
9704 | SET_FLAGS(flags, MODE_MF); | |
9705 | switch (bp->mf_mode) { | |
9706 | case MULTI_FUNCTION_SD: | |
9707 | SET_FLAGS(flags, MODE_MF_SD); | |
9708 | break; | |
9709 | case MULTI_FUNCTION_SI: | |
9710 | SET_FLAGS(flags, MODE_MF_SI); | |
9711 | break; | |
9712 | } | |
9713 | } else | |
9714 | SET_FLAGS(flags, MODE_SF); | |
9715 | ||
9716 | #if defined(__LITTLE_ENDIAN) | |
9717 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
9718 | #else /*(__BIG_ENDIAN)*/ | |
9719 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
9720 | #endif | |
9721 | INIT_MODE_FLAGS(bp) = flags; | |
9722 | } | |
9723 | ||
34f80b04 EG |
9724 | static int __devinit bnx2x_init_bp(struct bnx2x *bp) |
9725 | { | |
f2e0899f | 9726 | int func; |
87942b46 | 9727 | int timer_interval; |
34f80b04 EG |
9728 | int rc; |
9729 | ||
34f80b04 | 9730 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 9731 | mutex_init(&bp->fw_mb_mutex); |
bb7e95c8 | 9732 | spin_lock_init(&bp->stats_lock); |
993ac7b5 MC |
9733 | #ifdef BCM_CNIC |
9734 | mutex_init(&bp->cnic_mutex); | |
9735 | #endif | |
a2fbb9ea | 9736 | |
1cf167f2 | 9737 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 9738 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 9739 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
34f80b04 | 9740 | rc = bnx2x_get_hwinfo(bp); |
619c5cb6 VZ |
9741 | if (rc) |
9742 | return rc; | |
34f80b04 | 9743 | |
619c5cb6 VZ |
9744 | bnx2x_set_modes_bitmap(bp); |
9745 | ||
9746 | rc = bnx2x_alloc_mem_bp(bp); | |
9747 | if (rc) | |
9748 | return rc; | |
523224a3 | 9749 | |
34f24c7f | 9750 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
9751 | |
9752 | func = BP_FUNC(bp); | |
9753 | ||
34f80b04 EG |
9754 | /* need to reset chip if undi was active */ |
9755 | if (!BP_NOMCP(bp)) | |
9756 | bnx2x_undi_unload(bp); | |
9757 | ||
9758 | if (CHIP_REV_IS_FPGA(bp)) | |
cdaa7cb8 | 9759 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
9760 | |
9761 | if (BP_NOMCP(bp) && (func == 0)) | |
cdaa7cb8 VZ |
9762 | dev_err(&bp->pdev->dev, "MCP disabled, " |
9763 | "must load devices in order!\n"); | |
34f80b04 | 9764 | |
555f6c78 | 9765 | bp->multi_mode = multi_mode; |
555f6c78 | 9766 | |
7a9b2557 VZ |
9767 | /* Set TPA flags */ |
9768 | if (disable_tpa) { | |
9769 | bp->flags &= ~TPA_ENABLE_FLAG; | |
9770 | bp->dev->features &= ~NETIF_F_LRO; | |
9771 | } else { | |
9772 | bp->flags |= TPA_ENABLE_FLAG; | |
9773 | bp->dev->features |= NETIF_F_LRO; | |
9774 | } | |
5d7cd496 | 9775 | bp->disable_tpa = disable_tpa; |
7a9b2557 | 9776 | |
a18f5128 EG |
9777 | if (CHIP_IS_E1(bp)) |
9778 | bp->dropless_fc = 0; | |
9779 | else | |
9780 | bp->dropless_fc = dropless_fc; | |
9781 | ||
8d5726c4 | 9782 | bp->mrrs = mrrs; |
7a9b2557 | 9783 | |
34f80b04 | 9784 | bp->tx_ring_size = MAX_TX_AVAIL; |
34f80b04 | 9785 | |
7d323bfd | 9786 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
9787 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
9788 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 9789 | |
87942b46 EG |
9790 | timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); |
9791 | bp->current_interval = (poll ? poll : timer_interval); | |
34f80b04 EG |
9792 | |
9793 | init_timer(&bp->timer); | |
9794 | bp->timer.expires = jiffies + bp->current_interval; | |
9795 | bp->timer.data = (unsigned long) bp; | |
9796 | bp->timer.function = bnx2x_timer; | |
9797 | ||
785b9b1a | 9798 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); |
e4901dde VZ |
9799 | bnx2x_dcbx_init_params(bp); |
9800 | ||
619c5cb6 VZ |
9801 | #ifdef BCM_CNIC |
9802 | if (CHIP_IS_E1x(bp)) | |
9803 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
9804 | else | |
9805 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
9806 | #endif | |
9807 | ||
6383c0b3 AE |
9808 | /* multiple tx priority */ |
9809 | if (CHIP_IS_E1x(bp)) | |
9810 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; | |
9811 | if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) | |
9812 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; | |
9813 | if (CHIP_IS_E3B0(bp)) | |
9814 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; | |
9815 | ||
34f80b04 | 9816 | return rc; |
a2fbb9ea ET |
9817 | } |
9818 | ||
a2fbb9ea | 9819 | |
de0c62db DK |
9820 | /**************************************************************************** |
9821 | * General service functions | |
9822 | ****************************************************************************/ | |
a2fbb9ea | 9823 | |
619c5cb6 VZ |
9824 | /* |
9825 | * net_device service functions | |
9826 | */ | |
9827 | ||
bb2a0f7a | 9828 | /* called with rtnl_lock */ |
a2fbb9ea ET |
9829 | static int bnx2x_open(struct net_device *dev) |
9830 | { | |
9831 | struct bnx2x *bp = netdev_priv(dev); | |
c9ee9206 VZ |
9832 | bool global = false; |
9833 | int other_engine = BP_PATH(bp) ? 0 : 1; | |
9834 | u32 other_load_counter, load_counter; | |
a2fbb9ea | 9835 | |
6eccabb3 EG |
9836 | netif_carrier_off(dev); |
9837 | ||
a2fbb9ea ET |
9838 | bnx2x_set_power_state(bp, PCI_D0); |
9839 | ||
c9ee9206 VZ |
9840 | other_load_counter = bnx2x_get_load_cnt(bp, other_engine); |
9841 | load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp)); | |
9842 | ||
9843 | /* | |
9844 | * If parity had happen during the unload, then attentions | |
9845 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we | |
9846 | * want the first function loaded on the current engine to | |
9847 | * complete the recovery. | |
9848 | */ | |
9849 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
9850 | bnx2x_chk_parity_attn(bp, &global, true)) | |
72fd0718 | 9851 | do { |
c9ee9206 VZ |
9852 | /* |
9853 | * If there are attentions and they are in a global | |
9854 | * blocks, set the GLOBAL_RESET bit regardless whether | |
9855 | * it will be this function that will complete the | |
9856 | * recovery or not. | |
72fd0718 | 9857 | */ |
c9ee9206 VZ |
9858 | if (global) |
9859 | bnx2x_set_reset_global(bp); | |
72fd0718 | 9860 | |
c9ee9206 VZ |
9861 | /* |
9862 | * Only the first function on the current engine should | |
9863 | * try to recover in open. In case of attentions in | |
9864 | * global blocks only the first in the chip should try | |
9865 | * to recover. | |
72fd0718 | 9866 | */ |
c9ee9206 VZ |
9867 | if ((!load_counter && |
9868 | (!global || !other_load_counter)) && | |
9869 | bnx2x_trylock_leader_lock(bp) && | |
9870 | !bnx2x_leader_reset(bp)) { | |
9871 | netdev_info(bp->dev, "Recovered in open\n"); | |
72fd0718 VZ |
9872 | break; |
9873 | } | |
9874 | ||
c9ee9206 | 9875 | /* recovery has failed... */ |
72fd0718 | 9876 | bnx2x_set_power_state(bp, PCI_D3hot); |
c9ee9206 | 9877 | bp->recovery_state = BNX2X_RECOVERY_FAILED; |
72fd0718 | 9878 | |
c9ee9206 | 9879 | netdev_err(bp->dev, "Recovery flow hasn't been properly" |
72fd0718 VZ |
9880 | " completed yet. Try again later. If u still see this" |
9881 | " message after a few retries then power cycle is" | |
c9ee9206 | 9882 | " required.\n"); |
72fd0718 VZ |
9883 | |
9884 | return -EAGAIN; | |
9885 | } while (0); | |
72fd0718 VZ |
9886 | |
9887 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
bb2a0f7a | 9888 | return bnx2x_nic_load(bp, LOAD_OPEN); |
a2fbb9ea ET |
9889 | } |
9890 | ||
bb2a0f7a | 9891 | /* called with rtnl_lock */ |
a2fbb9ea ET |
9892 | static int bnx2x_close(struct net_device *dev) |
9893 | { | |
a2fbb9ea ET |
9894 | struct bnx2x *bp = netdev_priv(dev); |
9895 | ||
9896 | /* Unload the driver, release IRQs */ | |
bb2a0f7a | 9897 | bnx2x_nic_unload(bp, UNLOAD_CLOSE); |
c9ee9206 VZ |
9898 | |
9899 | /* Power off */ | |
d3dbfee0 | 9900 | bnx2x_set_power_state(bp, PCI_D3hot); |
a2fbb9ea ET |
9901 | |
9902 | return 0; | |
9903 | } | |
9904 | ||
619c5cb6 VZ |
9905 | static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
9906 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 9907 | { |
619c5cb6 VZ |
9908 | int mc_count = netdev_mc_count(bp->dev); |
9909 | struct bnx2x_mcast_list_elem *mc_mac = | |
9910 | kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); | |
9911 | struct netdev_hw_addr *ha; | |
6e30dd4e | 9912 | |
619c5cb6 VZ |
9913 | if (!mc_mac) |
9914 | return -ENOMEM; | |
6e30dd4e | 9915 | |
619c5cb6 | 9916 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 9917 | |
619c5cb6 VZ |
9918 | netdev_for_each_mc_addr(ha, bp->dev) { |
9919 | mc_mac->mac = bnx2x_mc_addr(ha); | |
9920 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
9921 | mc_mac++; | |
6e30dd4e | 9922 | } |
619c5cb6 VZ |
9923 | |
9924 | p->mcast_list_len = mc_count; | |
9925 | ||
9926 | return 0; | |
6e30dd4e VZ |
9927 | } |
9928 | ||
619c5cb6 VZ |
9929 | static inline void bnx2x_free_mcast_macs_list( |
9930 | struct bnx2x_mcast_ramrod_params *p) | |
9931 | { | |
9932 | struct bnx2x_mcast_list_elem *mc_mac = | |
9933 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
9934 | link); | |
9935 | ||
9936 | WARN_ON(!mc_mac); | |
9937 | kfree(mc_mac); | |
9938 | } | |
9939 | ||
9940 | /** | |
9941 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
9942 | * | |
9943 | * @bp: driver handle | |
6e30dd4e | 9944 | * |
619c5cb6 | 9945 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 9946 | */ |
619c5cb6 | 9947 | static inline int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 9948 | { |
619c5cb6 | 9949 | int rc; |
6e30dd4e | 9950 | struct net_device *dev = bp->dev; |
6e30dd4e | 9951 | struct netdev_hw_addr *ha; |
619c5cb6 VZ |
9952 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; |
9953 | unsigned long ramrod_flags = 0; | |
6e30dd4e | 9954 | |
619c5cb6 VZ |
9955 | /* First schedule a cleanup up of old configuration */ |
9956 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
9957 | if (rc < 0) { | |
9958 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
9959 | return rc; | |
9960 | } | |
6e30dd4e VZ |
9961 | |
9962 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
9963 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
9964 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
9965 | if (rc < 0) { | |
9966 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", | |
9967 | rc); | |
9968 | return rc; | |
6e30dd4e VZ |
9969 | } |
9970 | } | |
9971 | ||
619c5cb6 VZ |
9972 | /* Execute the pending commands */ |
9973 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
9974 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
9975 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
9976 | } |
9977 | ||
619c5cb6 | 9978 | static inline int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 9979 | { |
619c5cb6 VZ |
9980 | struct net_device *dev = bp->dev; |
9981 | struct bnx2x_mcast_ramrod_params rparam = {0}; | |
9982 | int rc = 0; | |
6e30dd4e | 9983 | |
619c5cb6 | 9984 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 9985 | |
619c5cb6 VZ |
9986 | /* first, clear all configured multicast MACs */ |
9987 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
9988 | if (rc < 0) { | |
9989 | BNX2X_ERR("Failed to clear multicast " | |
9990 | "configuration: %d\n", rc); | |
9991 | return rc; | |
9992 | } | |
6e30dd4e | 9993 | |
619c5cb6 VZ |
9994 | /* then, configure a new MACs list */ |
9995 | if (netdev_mc_count(dev)) { | |
9996 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
9997 | if (rc) { | |
9998 | BNX2X_ERR("Failed to create multicast MACs " | |
9999 | "list: %d\n", rc); | |
10000 | return rc; | |
10001 | } | |
6e30dd4e | 10002 | |
619c5cb6 VZ |
10003 | /* Now add the new MACs */ |
10004 | rc = bnx2x_config_mcast(bp, &rparam, | |
10005 | BNX2X_MCAST_CMD_ADD); | |
10006 | if (rc < 0) | |
10007 | BNX2X_ERR("Failed to set a new multicast " | |
10008 | "configuration: %d\n", rc); | |
6e30dd4e | 10009 | |
619c5cb6 VZ |
10010 | bnx2x_free_mcast_macs_list(&rparam); |
10011 | } | |
6e30dd4e | 10012 | |
619c5cb6 | 10013 | return rc; |
6e30dd4e VZ |
10014 | } |
10015 | ||
6e30dd4e | 10016 | |
619c5cb6 | 10017 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
9f6c9258 | 10018 | void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
10019 | { |
10020 | struct bnx2x *bp = netdev_priv(dev); | |
10021 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 EG |
10022 | |
10023 | if (bp->state != BNX2X_STATE_OPEN) { | |
10024 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
10025 | return; | |
10026 | } | |
10027 | ||
619c5cb6 | 10028 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 EG |
10029 | |
10030 | if (dev->flags & IFF_PROMISC) | |
10031 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
619c5cb6 VZ |
10032 | else if ((dev->flags & IFF_ALLMULTI) || |
10033 | ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && | |
10034 | CHIP_IS_E1(bp))) | |
34f80b04 | 10035 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
6e30dd4e VZ |
10036 | else { |
10037 | /* some multicasts */ | |
619c5cb6 | 10038 | if (bnx2x_set_mc_list(bp) < 0) |
6e30dd4e | 10039 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
34f80b04 | 10040 | |
619c5cb6 | 10041 | if (bnx2x_set_uc_list(bp) < 0) |
6e30dd4e | 10042 | rx_mode = BNX2X_RX_MODE_PROMISC; |
34f80b04 EG |
10043 | } |
10044 | ||
10045 | bp->rx_mode = rx_mode; | |
619c5cb6 VZ |
10046 | |
10047 | /* Schedule the rx_mode command */ | |
10048 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
10049 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
10050 | return; | |
10051 | } | |
10052 | ||
34f80b04 EG |
10053 | bnx2x_set_storm_rx_mode(bp); |
10054 | } | |
10055 | ||
c18487ee | 10056 | /* called with rtnl_lock */ |
01cd4528 EG |
10057 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
10058 | int devad, u16 addr) | |
a2fbb9ea | 10059 | { |
01cd4528 EG |
10060 | struct bnx2x *bp = netdev_priv(netdev); |
10061 | u16 value; | |
10062 | int rc; | |
a2fbb9ea | 10063 | |
01cd4528 EG |
10064 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
10065 | prtad, devad, addr); | |
a2fbb9ea | 10066 | |
01cd4528 EG |
10067 | /* The HW expects different devad if CL22 is used */ |
10068 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 10069 | |
01cd4528 | 10070 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 10071 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
10072 | bnx2x_release_phy_lock(bp); |
10073 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 10074 | |
01cd4528 EG |
10075 | if (!rc) |
10076 | rc = value; | |
10077 | return rc; | |
10078 | } | |
a2fbb9ea | 10079 | |
01cd4528 EG |
10080 | /* called with rtnl_lock */ |
10081 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
10082 | u16 addr, u16 value) | |
10083 | { | |
10084 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
10085 | int rc; |
10086 | ||
10087 | DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," | |
10088 | " value 0x%x\n", prtad, devad, addr, value); | |
10089 | ||
01cd4528 EG |
10090 | /* The HW expects different devad if CL22 is used */ |
10091 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 10092 | |
01cd4528 | 10093 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 10094 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
10095 | bnx2x_release_phy_lock(bp); |
10096 | return rc; | |
10097 | } | |
c18487ee | 10098 | |
01cd4528 EG |
10099 | /* called with rtnl_lock */ |
10100 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
10101 | { | |
10102 | struct bnx2x *bp = netdev_priv(dev); | |
10103 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 10104 | |
01cd4528 EG |
10105 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", |
10106 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
a2fbb9ea | 10107 | |
01cd4528 EG |
10108 | if (!netif_running(dev)) |
10109 | return -EAGAIN; | |
10110 | ||
10111 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
a2fbb9ea ET |
10112 | } |
10113 | ||
257ddbda | 10114 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
10115 | static void poll_bnx2x(struct net_device *dev) |
10116 | { | |
10117 | struct bnx2x *bp = netdev_priv(dev); | |
10118 | ||
10119 | disable_irq(bp->pdev->irq); | |
10120 | bnx2x_interrupt(bp->pdev->irq, dev); | |
10121 | enable_irq(bp->pdev->irq); | |
10122 | } | |
10123 | #endif | |
10124 | ||
c64213cd SH |
10125 | static const struct net_device_ops bnx2x_netdev_ops = { |
10126 | .ndo_open = bnx2x_open, | |
10127 | .ndo_stop = bnx2x_close, | |
10128 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 10129 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 10130 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd SH |
10131 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
10132 | .ndo_validate_addr = eth_validate_addr, | |
10133 | .ndo_do_ioctl = bnx2x_ioctl, | |
10134 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
10135 | .ndo_fix_features = bnx2x_fix_features, |
10136 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 10137 | .ndo_tx_timeout = bnx2x_tx_timeout, |
257ddbda | 10138 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
10139 | .ndo_poll_controller = poll_bnx2x, |
10140 | #endif | |
6383c0b3 AE |
10141 | .ndo_setup_tc = bnx2x_setup_tc, |
10142 | ||
bf61ee14 VZ |
10143 | #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) |
10144 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, | |
10145 | #endif | |
c64213cd SH |
10146 | }; |
10147 | ||
619c5cb6 VZ |
10148 | static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) |
10149 | { | |
10150 | struct device *dev = &bp->pdev->dev; | |
10151 | ||
10152 | if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { | |
10153 | bp->flags |= USING_DAC_FLAG; | |
10154 | if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { | |
10155 | dev_err(dev, "dma_set_coherent_mask failed, " | |
10156 | "aborting\n"); | |
10157 | return -EIO; | |
10158 | } | |
10159 | } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { | |
10160 | dev_err(dev, "System does not support DMA, aborting\n"); | |
10161 | return -EIO; | |
10162 | } | |
10163 | ||
10164 | return 0; | |
10165 | } | |
10166 | ||
34f80b04 | 10167 | static int __devinit bnx2x_init_dev(struct pci_dev *pdev, |
619c5cb6 VZ |
10168 | struct net_device *dev, |
10169 | unsigned long board_type) | |
a2fbb9ea ET |
10170 | { |
10171 | struct bnx2x *bp; | |
10172 | int rc; | |
10173 | ||
10174 | SET_NETDEV_DEV(dev, &pdev->dev); | |
10175 | bp = netdev_priv(dev); | |
10176 | ||
34f80b04 EG |
10177 | bp->dev = dev; |
10178 | bp->pdev = pdev; | |
a2fbb9ea | 10179 | bp->flags = 0; |
f2e0899f | 10180 | bp->pf_num = PCI_FUNC(pdev->devfn); |
a2fbb9ea ET |
10181 | |
10182 | rc = pci_enable_device(pdev); | |
10183 | if (rc) { | |
cdaa7cb8 VZ |
10184 | dev_err(&bp->pdev->dev, |
10185 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
10186 | goto err_out; |
10187 | } | |
10188 | ||
10189 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
10190 | dev_err(&bp->pdev->dev, |
10191 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
10192 | rc = -ENODEV; |
10193 | goto err_out_disable; | |
10194 | } | |
10195 | ||
10196 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
10197 | dev_err(&bp->pdev->dev, "Cannot find second PCI device" |
10198 | " base address, aborting\n"); | |
a2fbb9ea ET |
10199 | rc = -ENODEV; |
10200 | goto err_out_disable; | |
10201 | } | |
10202 | ||
34f80b04 EG |
10203 | if (atomic_read(&pdev->enable_cnt) == 1) { |
10204 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
10205 | if (rc) { | |
cdaa7cb8 VZ |
10206 | dev_err(&bp->pdev->dev, |
10207 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
10208 | goto err_out_disable; |
10209 | } | |
a2fbb9ea | 10210 | |
34f80b04 EG |
10211 | pci_set_master(pdev); |
10212 | pci_save_state(pdev); | |
10213 | } | |
a2fbb9ea ET |
10214 | |
10215 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
10216 | if (bp->pm_cap == 0) { | |
cdaa7cb8 VZ |
10217 | dev_err(&bp->pdev->dev, |
10218 | "Cannot find power management capability, aborting\n"); | |
a2fbb9ea ET |
10219 | rc = -EIO; |
10220 | goto err_out_release; | |
10221 | } | |
10222 | ||
77c98e6a JM |
10223 | if (!pci_is_pcie(pdev)) { |
10224 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); | |
a2fbb9ea ET |
10225 | rc = -EIO; |
10226 | goto err_out_release; | |
10227 | } | |
10228 | ||
619c5cb6 VZ |
10229 | rc = bnx2x_set_coherency_mask(bp); |
10230 | if (rc) | |
a2fbb9ea | 10231 | goto err_out_release; |
a2fbb9ea | 10232 | |
34f80b04 EG |
10233 | dev->mem_start = pci_resource_start(pdev, 0); |
10234 | dev->base_addr = dev->mem_start; | |
10235 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
10236 | |
10237 | dev->irq = pdev->irq; | |
10238 | ||
275f165f | 10239 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 10240 | if (!bp->regview) { |
cdaa7cb8 VZ |
10241 | dev_err(&bp->pdev->dev, |
10242 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
10243 | rc = -ENOMEM; |
10244 | goto err_out_release; | |
10245 | } | |
10246 | ||
a2fbb9ea ET |
10247 | bnx2x_set_power_state(bp, PCI_D0); |
10248 | ||
34f80b04 EG |
10249 | /* clean indirect addresses */ |
10250 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
10251 | PCICFG_VENDOR_ID_OFFSET); | |
10252 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0); | |
10253 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0); | |
10254 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0); | |
10255 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0); | |
a2fbb9ea | 10256 | |
2189400b | 10257 | /* |
619c5cb6 | 10258 | * Enable internal target-read (in case we are probed after PF FLR). |
2189400b | 10259 | * Must be done prior to any BAR read access. Only for 57712 and up |
619c5cb6 | 10260 | */ |
2189400b SR |
10261 | if (board_type != BCM57710 && |
10262 | board_type != BCM57711 && | |
10263 | board_type != BCM57711E) | |
10264 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
619c5cb6 | 10265 | |
72fd0718 VZ |
10266 | /* Reset the load counter */ |
10267 | bnx2x_clear_load_cnt(bp); | |
10268 | ||
34f80b04 | 10269 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 10270 | |
c64213cd | 10271 | dev->netdev_ops = &bnx2x_netdev_ops; |
de0c62db | 10272 | bnx2x_set_ethtool_ops(dev); |
5316bc0b | 10273 | |
66371c44 MM |
10274 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
10275 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | | |
10276 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX; | |
10277 | ||
10278 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
10279 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
10280 | ||
10281 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; | |
5316bc0b | 10282 | if (bp->flags & USING_DAC_FLAG) |
66371c44 | 10283 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 10284 | |
538dd2e3 MB |
10285 | /* Add Loopback capability to the device */ |
10286 | dev->hw_features |= NETIF_F_LOOPBACK; | |
10287 | ||
98507672 | 10288 | #ifdef BCM_DCBNL |
785b9b1a SR |
10289 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
10290 | #endif | |
10291 | ||
01cd4528 EG |
10292 | /* get_port_hwinfo() will set prtad and mmds properly */ |
10293 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
10294 | bp->mdio.mmds = 0; | |
10295 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
10296 | bp->mdio.dev = dev; | |
10297 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
10298 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
10299 | ||
a2fbb9ea ET |
10300 | return 0; |
10301 | ||
a2fbb9ea | 10302 | err_out_release: |
34f80b04 EG |
10303 | if (atomic_read(&pdev->enable_cnt) == 1) |
10304 | pci_release_regions(pdev); | |
a2fbb9ea ET |
10305 | |
10306 | err_out_disable: | |
10307 | pci_disable_device(pdev); | |
10308 | pci_set_drvdata(pdev, NULL); | |
10309 | ||
10310 | err_out: | |
10311 | return rc; | |
10312 | } | |
10313 | ||
37f9ce62 EG |
10314 | static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, |
10315 | int *width, int *speed) | |
25047950 ET |
10316 | { |
10317 | u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); | |
10318 | ||
37f9ce62 | 10319 | *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; |
25047950 | 10320 | |
37f9ce62 EG |
10321 | /* return value of 1=2.5GHz 2=5GHz */ |
10322 | *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; | |
25047950 | 10323 | } |
37f9ce62 | 10324 | |
6891dd25 | 10325 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 10326 | { |
37f9ce62 | 10327 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
10328 | struct bnx2x_fw_file_hdr *fw_hdr; |
10329 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 10330 | u32 offset, len, num_ops; |
37f9ce62 | 10331 | u16 *ops_offsets; |
94a78b79 | 10332 | int i; |
37f9ce62 | 10333 | const u8 *fw_ver; |
94a78b79 VZ |
10334 | |
10335 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) | |
10336 | return -EINVAL; | |
10337 | ||
10338 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
10339 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
10340 | ||
10341 | /* Make sure none of the offsets and sizes make us read beyond | |
10342 | * the end of the firmware data */ | |
10343 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
10344 | offset = be32_to_cpu(sections[i].offset); | |
10345 | len = be32_to_cpu(sections[i].len); | |
10346 | if (offset + len > firmware->size) { | |
cdaa7cb8 VZ |
10347 | dev_err(&bp->pdev->dev, |
10348 | "Section %d length is out of bounds\n", i); | |
94a78b79 VZ |
10349 | return -EINVAL; |
10350 | } | |
10351 | } | |
10352 | ||
10353 | /* Likewise for the init_ops offsets */ | |
10354 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
10355 | ops_offsets = (u16 *)(firmware->data + offset); | |
10356 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); | |
10357 | ||
10358 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
10359 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
cdaa7cb8 VZ |
10360 | dev_err(&bp->pdev->dev, |
10361 | "Section offset %d is out of bounds\n", i); | |
94a78b79 VZ |
10362 | return -EINVAL; |
10363 | } | |
10364 | } | |
10365 | ||
10366 | /* Check FW version */ | |
10367 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
10368 | fw_ver = firmware->data + offset; | |
10369 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
10370 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
10371 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
10372 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
cdaa7cb8 VZ |
10373 | dev_err(&bp->pdev->dev, |
10374 | "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", | |
94a78b79 VZ |
10375 | fw_ver[0], fw_ver[1], fw_ver[2], |
10376 | fw_ver[3], BCM_5710_FW_MAJOR_VERSION, | |
10377 | BCM_5710_FW_MINOR_VERSION, | |
10378 | BCM_5710_FW_REVISION_VERSION, | |
10379 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 10380 | return -EINVAL; |
94a78b79 VZ |
10381 | } |
10382 | ||
10383 | return 0; | |
10384 | } | |
10385 | ||
ab6ad5a4 | 10386 | static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 10387 | { |
ab6ad5a4 EG |
10388 | const __be32 *source = (const __be32 *)_source; |
10389 | u32 *target = (u32 *)_target; | |
94a78b79 | 10390 | u32 i; |
94a78b79 VZ |
10391 | |
10392 | for (i = 0; i < n/4; i++) | |
10393 | target[i] = be32_to_cpu(source[i]); | |
10394 | } | |
10395 | ||
10396 | /* | |
10397 | Ops array is stored in the following format: | |
10398 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
10399 | */ | |
ab6ad5a4 | 10400 | static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 10401 | { |
ab6ad5a4 EG |
10402 | const __be32 *source = (const __be32 *)_source; |
10403 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 10404 | u32 i, j, tmp; |
94a78b79 | 10405 | |
ab6ad5a4 | 10406 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
10407 | tmp = be32_to_cpu(source[j]); |
10408 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
10409 | target[i].offset = tmp & 0xffffff; |
10410 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
10411 | } |
10412 | } | |
ab6ad5a4 | 10413 | |
523224a3 DK |
10414 | /** |
10415 | * IRO array is stored in the following format: | |
10416 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } | |
10417 | */ | |
10418 | static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) | |
10419 | { | |
10420 | const __be32 *source = (const __be32 *)_source; | |
10421 | struct iro *target = (struct iro *)_target; | |
10422 | u32 i, j, tmp; | |
10423 | ||
10424 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
10425 | target[i].base = be32_to_cpu(source[j]); | |
10426 | j++; | |
10427 | tmp = be32_to_cpu(source[j]); | |
10428 | target[i].m1 = (tmp >> 16) & 0xffff; | |
10429 | target[i].m2 = tmp & 0xffff; | |
10430 | j++; | |
10431 | tmp = be32_to_cpu(source[j]); | |
10432 | target[i].m3 = (tmp >> 16) & 0xffff; | |
10433 | target[i].size = tmp & 0xffff; | |
10434 | j++; | |
10435 | } | |
10436 | } | |
10437 | ||
ab6ad5a4 | 10438 | static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 10439 | { |
ab6ad5a4 EG |
10440 | const __be16 *source = (const __be16 *)_source; |
10441 | u16 *target = (u16 *)_target; | |
94a78b79 | 10442 | u32 i; |
94a78b79 VZ |
10443 | |
10444 | for (i = 0; i < n/2; i++) | |
10445 | target[i] = be16_to_cpu(source[i]); | |
10446 | } | |
10447 | ||
7995c64e JP |
10448 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
10449 | do { \ | |
10450 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
10451 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
10452 | if (!bp->arr) { \ | |
10453 | pr_err("Failed to allocate %d bytes for "#arr"\n", len); \ | |
10454 | goto lbl; \ | |
10455 | } \ | |
10456 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ | |
10457 | (u8 *)bp->arr, len); \ | |
10458 | } while (0) | |
94a78b79 | 10459 | |
6891dd25 | 10460 | int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 10461 | { |
45229b42 | 10462 | const char *fw_file_name; |
94a78b79 | 10463 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 10464 | int rc; |
94a78b79 | 10465 | |
94a78b79 | 10466 | if (CHIP_IS_E1(bp)) |
45229b42 | 10467 | fw_file_name = FW_FILE_NAME_E1; |
cdaa7cb8 | 10468 | else if (CHIP_IS_E1H(bp)) |
45229b42 | 10469 | fw_file_name = FW_FILE_NAME_E1H; |
619c5cb6 | 10470 | else if (!CHIP_IS_E1x(bp)) |
f2e0899f | 10471 | fw_file_name = FW_FILE_NAME_E2; |
cdaa7cb8 | 10472 | else { |
6891dd25 | 10473 | BNX2X_ERR("Unsupported chip revision\n"); |
cdaa7cb8 VZ |
10474 | return -EINVAL; |
10475 | } | |
94a78b79 | 10476 | |
6891dd25 | 10477 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); |
94a78b79 | 10478 | |
6891dd25 | 10479 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
94a78b79 | 10480 | if (rc) { |
6891dd25 | 10481 | BNX2X_ERR("Can't load firmware file %s\n", fw_file_name); |
94a78b79 VZ |
10482 | goto request_firmware_exit; |
10483 | } | |
10484 | ||
10485 | rc = bnx2x_check_firmware(bp); | |
10486 | if (rc) { | |
6891dd25 | 10487 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); |
94a78b79 VZ |
10488 | goto request_firmware_exit; |
10489 | } | |
10490 | ||
10491 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
10492 | ||
10493 | /* Initialize the pointers to the init arrays */ | |
10494 | /* Blob */ | |
10495 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
10496 | ||
10497 | /* Opcodes */ | |
10498 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
10499 | ||
10500 | /* Offsets */ | |
ab6ad5a4 EG |
10501 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
10502 | be16_to_cpu_n); | |
94a78b79 VZ |
10503 | |
10504 | /* STORMs firmware */ | |
573f2035 EG |
10505 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
10506 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
10507 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
10508 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
10509 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
10510 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
10511 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
10512 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
10513 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
10514 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
10515 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
10516 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
10517 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
10518 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
10519 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
10520 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
10521 | /* IRO */ |
10522 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
10523 | |
10524 | return 0; | |
ab6ad5a4 | 10525 | |
523224a3 DK |
10526 | iro_alloc_err: |
10527 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
10528 | init_offsets_alloc_err: |
10529 | kfree(bp->init_ops); | |
10530 | init_ops_alloc_err: | |
10531 | kfree(bp->init_data); | |
10532 | request_firmware_exit: | |
10533 | release_firmware(bp->firmware); | |
10534 | ||
10535 | return rc; | |
10536 | } | |
10537 | ||
619c5cb6 VZ |
10538 | static void bnx2x_release_firmware(struct bnx2x *bp) |
10539 | { | |
10540 | kfree(bp->init_ops_offsets); | |
10541 | kfree(bp->init_ops); | |
10542 | kfree(bp->init_data); | |
10543 | release_firmware(bp->firmware); | |
10544 | } | |
10545 | ||
10546 | ||
10547 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { | |
10548 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
10549 | .init_hw_cmn = bnx2x_init_hw_common, | |
10550 | .init_hw_port = bnx2x_init_hw_port, | |
10551 | .init_hw_func = bnx2x_init_hw_func, | |
10552 | ||
10553 | .reset_hw_cmn = bnx2x_reset_common, | |
10554 | .reset_hw_port = bnx2x_reset_port, | |
10555 | .reset_hw_func = bnx2x_reset_func, | |
10556 | ||
10557 | .gunzip_init = bnx2x_gunzip_init, | |
10558 | .gunzip_end = bnx2x_gunzip_end, | |
10559 | ||
10560 | .init_fw = bnx2x_init_firmware, | |
10561 | .release_fw = bnx2x_release_firmware, | |
10562 | }; | |
10563 | ||
10564 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
10565 | { | |
10566 | /* Prepare DMAE related driver resources */ | |
10567 | bnx2x_setup_dmae(bp); | |
10568 | ||
10569 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
10570 | bnx2x_sp(bp, func_rdata), | |
10571 | bnx2x_sp_mapping(bp, func_rdata), | |
10572 | &bnx2x_func_sp_drv); | |
10573 | } | |
10574 | ||
10575 | /* must be called after sriov-enable */ | |
6383c0b3 | 10576 | static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 10577 | { |
6383c0b3 | 10578 | int cid_count = BNX2X_L2_CID_COUNT(bp); |
94a78b79 | 10579 | |
523224a3 DK |
10580 | #ifdef BCM_CNIC |
10581 | cid_count += CNIC_CID_MAX; | |
10582 | #endif | |
10583 | return roundup(cid_count, QM_CID_ROUND); | |
10584 | } | |
f85582f8 | 10585 | |
619c5cb6 | 10586 | /** |
6383c0b3 | 10587 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
10588 | * |
10589 | * @dev: pci device | |
10590 | * | |
10591 | */ | |
6383c0b3 | 10592 | static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) |
619c5cb6 VZ |
10593 | { |
10594 | int pos; | |
10595 | u16 control; | |
10596 | ||
10597 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); | |
6383c0b3 AE |
10598 | |
10599 | /* | |
10600 | * If MSI-X is not supported - return number of SBs needed to support | |
10601 | * one fast path queue: one FP queue + SB for CNIC | |
10602 | */ | |
619c5cb6 | 10603 | if (!pos) |
6383c0b3 | 10604 | return 1 + CNIC_PRESENT; |
619c5cb6 | 10605 | |
6383c0b3 AE |
10606 | /* |
10607 | * The value in the PCI configuration space is the index of the last | |
10608 | * entry, namely one less than the actual size of the table, which is | |
10609 | * exactly what we want to return from this function: number of all SBs | |
10610 | * without the default SB. | |
10611 | */ | |
619c5cb6 | 10612 | pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); |
6383c0b3 | 10613 | return control & PCI_MSIX_FLAGS_QSIZE; |
619c5cb6 VZ |
10614 | } |
10615 | ||
a2fbb9ea ET |
10616 | static int __devinit bnx2x_init_one(struct pci_dev *pdev, |
10617 | const struct pci_device_id *ent) | |
10618 | { | |
a2fbb9ea ET |
10619 | struct net_device *dev = NULL; |
10620 | struct bnx2x *bp; | |
37f9ce62 | 10621 | int pcie_width, pcie_speed; |
6383c0b3 AE |
10622 | int rc, max_non_def_sbs; |
10623 | int rx_count, tx_count, rss_count; | |
10624 | /* | |
10625 | * An estimated maximum supported CoS number according to the chip | |
10626 | * version. | |
10627 | * We will try to roughly estimate the maximum number of CoSes this chip | |
10628 | * may support in order to minimize the memory allocated for Tx | |
10629 | * netdev_queue's. This number will be accurately calculated during the | |
10630 | * initialization of bp->max_cos based on the chip versions AND chip | |
10631 | * revision in the bnx2x_init_bp(). | |
10632 | */ | |
10633 | u8 max_cos_est = 0; | |
523224a3 | 10634 | |
f2e0899f DK |
10635 | switch (ent->driver_data) { |
10636 | case BCM57710: | |
10637 | case BCM57711: | |
10638 | case BCM57711E: | |
6383c0b3 AE |
10639 | max_cos_est = BNX2X_MULTI_TX_COS_E1X; |
10640 | break; | |
10641 | ||
f2e0899f | 10642 | case BCM57712: |
619c5cb6 | 10643 | case BCM57712_MF: |
6383c0b3 AE |
10644 | max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; |
10645 | break; | |
10646 | ||
619c5cb6 VZ |
10647 | case BCM57800: |
10648 | case BCM57800_MF: | |
10649 | case BCM57810: | |
10650 | case BCM57810_MF: | |
10651 | case BCM57840: | |
10652 | case BCM57840_MF: | |
6383c0b3 | 10653 | max_cos_est = BNX2X_MULTI_TX_COS_E3B0; |
f2e0899f | 10654 | break; |
a2fbb9ea | 10655 | |
f2e0899f DK |
10656 | default: |
10657 | pr_err("Unknown board_type (%ld), aborting\n", | |
10658 | ent->driver_data); | |
870634b0 | 10659 | return -ENODEV; |
f2e0899f DK |
10660 | } |
10661 | ||
6383c0b3 AE |
10662 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); |
10663 | ||
10664 | /* !!! FIXME !!! | |
10665 | * Do not allow the maximum SB count to grow above 16 | |
10666 | * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. | |
10667 | * We will use the FP_SB_MAX_E1x macro for this matter. | |
10668 | */ | |
10669 | max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); | |
10670 | ||
10671 | WARN_ON(!max_non_def_sbs); | |
10672 | ||
10673 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
10674 | rss_count = max_non_def_sbs - CNIC_PRESENT; | |
10675 | ||
10676 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
10677 | rx_count = rss_count + FCOE_PRESENT; | |
10678 | ||
10679 | /* | |
10680 | * Maximum number of netdev Tx queues: | |
10681 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 | |
10682 | */ | |
10683 | tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; | |
f85582f8 | 10684 | |
a2fbb9ea | 10685 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 10686 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
34f80b04 | 10687 | if (!dev) { |
cdaa7cb8 | 10688 | dev_err(&pdev->dev, "Cannot allocate net device\n"); |
a2fbb9ea | 10689 | return -ENOMEM; |
34f80b04 | 10690 | } |
a2fbb9ea | 10691 | |
a2fbb9ea | 10692 | bp = netdev_priv(dev); |
a2fbb9ea | 10693 | |
6383c0b3 AE |
10694 | DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", |
10695 | tx_count, rx_count); | |
df4770de | 10696 | |
6383c0b3 AE |
10697 | bp->igu_sb_cnt = max_non_def_sbs; |
10698 | bp->msg_enable = debug; | |
10699 | pci_set_drvdata(pdev, dev); | |
523224a3 | 10700 | |
619c5cb6 | 10701 | rc = bnx2x_init_dev(pdev, dev, ent->driver_data); |
a2fbb9ea ET |
10702 | if (rc < 0) { |
10703 | free_netdev(dev); | |
10704 | return rc; | |
10705 | } | |
10706 | ||
6383c0b3 | 10707 | DP(NETIF_MSG_DRV, "max_non_def_sbs %d", max_non_def_sbs); |
619c5cb6 | 10708 | |
34f80b04 | 10709 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
10710 | if (rc) |
10711 | goto init_one_exit; | |
10712 | ||
6383c0b3 AE |
10713 | /* |
10714 | * Map doorbels here as we need the real value of bp->max_cos which | |
10715 | * is initialized in bnx2x_init_bp(). | |
10716 | */ | |
10717 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), | |
10718 | min_t(u64, BNX2X_DB_SIZE(bp), | |
10719 | pci_resource_len(pdev, 2))); | |
10720 | if (!bp->doorbells) { | |
10721 | dev_err(&bp->pdev->dev, | |
10722 | "Cannot map doorbell space, aborting\n"); | |
10723 | rc = -ENOMEM; | |
10724 | goto init_one_exit; | |
10725 | } | |
10726 | ||
523224a3 | 10727 | /* calc qm_cid_count */ |
6383c0b3 | 10728 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
523224a3 | 10729 | |
ec6ba945 | 10730 | #ifdef BCM_CNIC |
928ad22a DK |
10731 | /* disable FCOE L2 queue for E1x and E3*/ |
10732 | if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp)) | |
ec6ba945 VZ |
10733 | bp->flags |= NO_FCOE_FLAG; |
10734 | ||
10735 | #endif | |
10736 | ||
25985edc | 10737 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
d6214d7a DK |
10738 | * needed, set bp->num_queues appropriately. |
10739 | */ | |
10740 | bnx2x_set_int_mode(bp); | |
10741 | ||
10742 | /* Add all NAPI objects */ | |
10743 | bnx2x_add_all_napi(bp); | |
10744 | ||
b340007f VZ |
10745 | rc = register_netdev(dev); |
10746 | if (rc) { | |
10747 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
10748 | goto init_one_exit; | |
10749 | } | |
10750 | ||
ec6ba945 VZ |
10751 | #ifdef BCM_CNIC |
10752 | if (!NO_FCOE(bp)) { | |
10753 | /* Add storage MAC address */ | |
10754 | rtnl_lock(); | |
10755 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
10756 | rtnl_unlock(); | |
10757 | } | |
10758 | #endif | |
10759 | ||
37f9ce62 | 10760 | bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); |
d6214d7a | 10761 | |
cdaa7cb8 VZ |
10762 | netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx," |
10763 | " IRQ %d, ", board_info[ent->driver_data].name, | |
10764 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
f2e0899f DK |
10765 | pcie_width, |
10766 | ((!CHIP_IS_E2(bp) && pcie_speed == 2) || | |
10767 | (CHIP_IS_E2(bp) && pcie_speed == 1)) ? | |
10768 | "5GHz (Gen2)" : "2.5GHz", | |
cdaa7cb8 VZ |
10769 | dev->base_addr, bp->pdev->irq); |
10770 | pr_cont("node addr %pM\n", dev->dev_addr); | |
c016201c | 10771 | |
a2fbb9ea | 10772 | return 0; |
34f80b04 EG |
10773 | |
10774 | init_one_exit: | |
10775 | if (bp->regview) | |
10776 | iounmap(bp->regview); | |
10777 | ||
10778 | if (bp->doorbells) | |
10779 | iounmap(bp->doorbells); | |
10780 | ||
10781 | free_netdev(dev); | |
10782 | ||
10783 | if (atomic_read(&pdev->enable_cnt) == 1) | |
10784 | pci_release_regions(pdev); | |
10785 | ||
10786 | pci_disable_device(pdev); | |
10787 | pci_set_drvdata(pdev, NULL); | |
10788 | ||
10789 | return rc; | |
a2fbb9ea ET |
10790 | } |
10791 | ||
10792 | static void __devexit bnx2x_remove_one(struct pci_dev *pdev) | |
10793 | { | |
10794 | struct net_device *dev = pci_get_drvdata(pdev); | |
228241eb ET |
10795 | struct bnx2x *bp; |
10796 | ||
10797 | if (!dev) { | |
cdaa7cb8 | 10798 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); |
228241eb ET |
10799 | return; |
10800 | } | |
228241eb | 10801 | bp = netdev_priv(dev); |
a2fbb9ea | 10802 | |
ec6ba945 VZ |
10803 | #ifdef BCM_CNIC |
10804 | /* Delete storage MAC address */ | |
10805 | if (!NO_FCOE(bp)) { | |
10806 | rtnl_lock(); | |
10807 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
10808 | rtnl_unlock(); | |
10809 | } | |
10810 | #endif | |
10811 | ||
98507672 SR |
10812 | #ifdef BCM_DCBNL |
10813 | /* Delete app tlvs from dcbnl */ | |
10814 | bnx2x_dcbnl_update_applist(bp, true); | |
10815 | #endif | |
10816 | ||
a2fbb9ea ET |
10817 | unregister_netdev(dev); |
10818 | ||
d6214d7a DK |
10819 | /* Delete all NAPI objects */ |
10820 | bnx2x_del_all_napi(bp); | |
10821 | ||
084d6cbb VZ |
10822 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
10823 | bnx2x_set_power_state(bp, PCI_D0); | |
10824 | ||
d6214d7a DK |
10825 | /* Disable MSI/MSI-X */ |
10826 | bnx2x_disable_msi(bp); | |
f85582f8 | 10827 | |
084d6cbb VZ |
10828 | /* Power off */ |
10829 | bnx2x_set_power_state(bp, PCI_D3hot); | |
10830 | ||
72fd0718 | 10831 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 10832 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
72fd0718 | 10833 | |
a2fbb9ea ET |
10834 | if (bp->regview) |
10835 | iounmap(bp->regview); | |
10836 | ||
10837 | if (bp->doorbells) | |
10838 | iounmap(bp->doorbells); | |
10839 | ||
523224a3 DK |
10840 | bnx2x_free_mem_bp(bp); |
10841 | ||
a2fbb9ea | 10842 | free_netdev(dev); |
34f80b04 EG |
10843 | |
10844 | if (atomic_read(&pdev->enable_cnt) == 1) | |
10845 | pci_release_regions(pdev); | |
10846 | ||
a2fbb9ea ET |
10847 | pci_disable_device(pdev); |
10848 | pci_set_drvdata(pdev, NULL); | |
10849 | } | |
10850 | ||
f8ef6e44 YG |
10851 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
10852 | { | |
10853 | int i; | |
10854 | ||
10855 | bp->state = BNX2X_STATE_ERROR; | |
10856 | ||
10857 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
10858 | ||
619c5cb6 VZ |
10859 | #ifdef BCM_CNIC |
10860 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
10861 | #endif | |
10862 | /* Stop Tx */ | |
10863 | bnx2x_tx_disable(bp); | |
10864 | ||
f8ef6e44 YG |
10865 | bnx2x_netif_stop(bp, 0); |
10866 | ||
10867 | del_timer_sync(&bp->timer); | |
619c5cb6 VZ |
10868 | |
10869 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
f8ef6e44 YG |
10870 | |
10871 | /* Release IRQs */ | |
d6214d7a | 10872 | bnx2x_free_irq(bp); |
f8ef6e44 | 10873 | |
f8ef6e44 YG |
10874 | /* Free SKBs, SGEs, TPA pool and driver internals */ |
10875 | bnx2x_free_skbs(bp); | |
523224a3 | 10876 | |
ec6ba945 | 10877 | for_each_rx_queue(bp, i) |
f8ef6e44 | 10878 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); |
d6214d7a | 10879 | |
f8ef6e44 YG |
10880 | bnx2x_free_mem(bp); |
10881 | ||
10882 | bp->state = BNX2X_STATE_CLOSED; | |
10883 | ||
619c5cb6 VZ |
10884 | netif_carrier_off(bp->dev); |
10885 | ||
f8ef6e44 YG |
10886 | return 0; |
10887 | } | |
10888 | ||
10889 | static void bnx2x_eeh_recover(struct bnx2x *bp) | |
10890 | { | |
10891 | u32 val; | |
10892 | ||
10893 | mutex_init(&bp->port.phy_mutex); | |
10894 | ||
10895 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
10896 | bp->link_params.shmem_base = bp->common.shmem_base; | |
10897 | BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base); | |
10898 | ||
10899 | if (!bp->common.shmem_base || | |
10900 | (bp->common.shmem_base < 0xA0000) || | |
10901 | (bp->common.shmem_base >= 0xC0000)) { | |
10902 | BNX2X_DEV_INFO("MCP not active\n"); | |
10903 | bp->flags |= NO_MCP_FLAG; | |
10904 | return; | |
10905 | } | |
10906 | ||
10907 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
10908 | if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
10909 | != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
10910 | BNX2X_ERR("BAD MCP validity signature\n"); | |
10911 | ||
10912 | if (!BP_NOMCP(bp)) { | |
f2e0899f DK |
10913 | bp->fw_seq = |
10914 | (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
10915 | DRV_MSG_SEQ_NUMBER_MASK); | |
f8ef6e44 YG |
10916 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); |
10917 | } | |
10918 | } | |
10919 | ||
493adb1f WX |
10920 | /** |
10921 | * bnx2x_io_error_detected - called when PCI error is detected | |
10922 | * @pdev: Pointer to PCI device | |
10923 | * @state: The current pci connection state | |
10924 | * | |
10925 | * This function is called after a PCI bus error affecting | |
10926 | * this device has been detected. | |
10927 | */ | |
10928 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
10929 | pci_channel_state_t state) | |
10930 | { | |
10931 | struct net_device *dev = pci_get_drvdata(pdev); | |
10932 | struct bnx2x *bp = netdev_priv(dev); | |
10933 | ||
10934 | rtnl_lock(); | |
10935 | ||
10936 | netif_device_detach(dev); | |
10937 | ||
07ce50e4 DN |
10938 | if (state == pci_channel_io_perm_failure) { |
10939 | rtnl_unlock(); | |
10940 | return PCI_ERS_RESULT_DISCONNECT; | |
10941 | } | |
10942 | ||
493adb1f | 10943 | if (netif_running(dev)) |
f8ef6e44 | 10944 | bnx2x_eeh_nic_unload(bp); |
493adb1f WX |
10945 | |
10946 | pci_disable_device(pdev); | |
10947 | ||
10948 | rtnl_unlock(); | |
10949 | ||
10950 | /* Request a slot reset */ | |
10951 | return PCI_ERS_RESULT_NEED_RESET; | |
10952 | } | |
10953 | ||
10954 | /** | |
10955 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
10956 | * @pdev: Pointer to PCI device | |
10957 | * | |
10958 | * Restart the card from scratch, as if from a cold-boot. | |
10959 | */ | |
10960 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
10961 | { | |
10962 | struct net_device *dev = pci_get_drvdata(pdev); | |
10963 | struct bnx2x *bp = netdev_priv(dev); | |
10964 | ||
10965 | rtnl_lock(); | |
10966 | ||
10967 | if (pci_enable_device(pdev)) { | |
10968 | dev_err(&pdev->dev, | |
10969 | "Cannot re-enable PCI device after reset\n"); | |
10970 | rtnl_unlock(); | |
10971 | return PCI_ERS_RESULT_DISCONNECT; | |
10972 | } | |
10973 | ||
10974 | pci_set_master(pdev); | |
10975 | pci_restore_state(pdev); | |
10976 | ||
10977 | if (netif_running(dev)) | |
10978 | bnx2x_set_power_state(bp, PCI_D0); | |
10979 | ||
10980 | rtnl_unlock(); | |
10981 | ||
10982 | return PCI_ERS_RESULT_RECOVERED; | |
10983 | } | |
10984 | ||
10985 | /** | |
10986 | * bnx2x_io_resume - called when traffic can start flowing again | |
10987 | * @pdev: Pointer to PCI device | |
10988 | * | |
10989 | * This callback is called when the error recovery driver tells us that | |
10990 | * its OK to resume normal operation. | |
10991 | */ | |
10992 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
10993 | { | |
10994 | struct net_device *dev = pci_get_drvdata(pdev); | |
10995 | struct bnx2x *bp = netdev_priv(dev); | |
10996 | ||
72fd0718 | 10997 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
754a2f52 DK |
10998 | netdev_err(bp->dev, "Handling parity error recovery. " |
10999 | "Try again later\n"); | |
72fd0718 VZ |
11000 | return; |
11001 | } | |
11002 | ||
493adb1f WX |
11003 | rtnl_lock(); |
11004 | ||
f8ef6e44 YG |
11005 | bnx2x_eeh_recover(bp); |
11006 | ||
493adb1f | 11007 | if (netif_running(dev)) |
f8ef6e44 | 11008 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
11009 | |
11010 | netif_device_attach(dev); | |
11011 | ||
11012 | rtnl_unlock(); | |
11013 | } | |
11014 | ||
11015 | static struct pci_error_handlers bnx2x_err_handler = { | |
11016 | .error_detected = bnx2x_io_error_detected, | |
356e2385 EG |
11017 | .slot_reset = bnx2x_io_slot_reset, |
11018 | .resume = bnx2x_io_resume, | |
493adb1f WX |
11019 | }; |
11020 | ||
a2fbb9ea | 11021 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
11022 | .name = DRV_MODULE_NAME, |
11023 | .id_table = bnx2x_pci_tbl, | |
11024 | .probe = bnx2x_init_one, | |
11025 | .remove = __devexit_p(bnx2x_remove_one), | |
11026 | .suspend = bnx2x_suspend, | |
11027 | .resume = bnx2x_resume, | |
11028 | .err_handler = &bnx2x_err_handler, | |
a2fbb9ea ET |
11029 | }; |
11030 | ||
11031 | static int __init bnx2x_init(void) | |
11032 | { | |
dd21ca6d SG |
11033 | int ret; |
11034 | ||
7995c64e | 11035 | pr_info("%s", version); |
938cf541 | 11036 | |
1cf167f2 EG |
11037 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
11038 | if (bnx2x_wq == NULL) { | |
7995c64e | 11039 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
11040 | return -ENOMEM; |
11041 | } | |
11042 | ||
dd21ca6d SG |
11043 | ret = pci_register_driver(&bnx2x_pci_driver); |
11044 | if (ret) { | |
7995c64e | 11045 | pr_err("Cannot register driver\n"); |
dd21ca6d SG |
11046 | destroy_workqueue(bnx2x_wq); |
11047 | } | |
11048 | return ret; | |
a2fbb9ea ET |
11049 | } |
11050 | ||
11051 | static void __exit bnx2x_cleanup(void) | |
11052 | { | |
11053 | pci_unregister_driver(&bnx2x_pci_driver); | |
1cf167f2 EG |
11054 | |
11055 | destroy_workqueue(bnx2x_wq); | |
a2fbb9ea ET |
11056 | } |
11057 | ||
3deb8167 YR |
11058 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
11059 | { | |
11060 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
11061 | } | |
11062 | ||
a2fbb9ea ET |
11063 | module_init(bnx2x_init); |
11064 | module_exit(bnx2x_cleanup); | |
11065 | ||
993ac7b5 | 11066 | #ifdef BCM_CNIC |
619c5cb6 VZ |
11067 | /** |
11068 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
11069 | * | |
11070 | * @bp: driver handle | |
11071 | * @set: set or clear the CAM entry | |
11072 | * | |
11073 | * This function will wait until the ramdord completion returns. | |
11074 | * Return 0 if success, -ENODEV if ramrod doesn't return. | |
11075 | */ | |
11076 | static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) | |
11077 | { | |
11078 | unsigned long ramrod_flags = 0; | |
11079 | ||
11080 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
11081 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
11082 | &bp->iscsi_l2_mac_obj, true, | |
11083 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
11084 | } | |
993ac7b5 MC |
11085 | |
11086 | /* count denotes the number of new completions we have seen */ | |
11087 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
11088 | { | |
11089 | struct eth_spe *spe; | |
11090 | ||
11091 | #ifdef BNX2X_STOP_ON_ERROR | |
11092 | if (unlikely(bp->panic)) | |
11093 | return; | |
11094 | #endif | |
11095 | ||
11096 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 11097 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
11098 | bp->cnic_spq_pending -= count; |
11099 | ||
993ac7b5 | 11100 | |
c2bff63f DK |
11101 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
11102 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
11103 | & SPE_HDR_CONN_TYPE) >> | |
11104 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
11105 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
11106 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
11107 | |
11108 | /* Set validation for iSCSI L2 client before sending SETUP | |
11109 | * ramrod | |
11110 | */ | |
11111 | if (type == ETH_CONNECTION_TYPE) { | |
c2bff63f | 11112 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) |
619c5cb6 VZ |
11113 | bnx2x_set_ctx_validation(bp, &bp->context. |
11114 | vcxt[BNX2X_ISCSI_ETH_CID].eth, | |
11115 | BNX2X_ISCSI_ETH_CID); | |
c2bff63f DK |
11116 | } |
11117 | ||
619c5cb6 VZ |
11118 | /* |
11119 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
11120 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
11121 | * COMMON ramrods is not more than the EQ and SPQ can |
11122 | * accommodate. | |
c2bff63f | 11123 | */ |
6e30dd4e VZ |
11124 | if (type == ETH_CONNECTION_TYPE) { |
11125 | if (!atomic_read(&bp->cq_spq_left)) | |
11126 | break; | |
11127 | else | |
11128 | atomic_dec(&bp->cq_spq_left); | |
11129 | } else if (type == NONE_CONNECTION_TYPE) { | |
11130 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
11131 | break; |
11132 | else | |
6e30dd4e | 11133 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
11134 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
11135 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
11136 | if (bp->cnic_spq_pending >= |
11137 | bp->cnic_eth_dev.max_kwqe_pending) | |
11138 | break; | |
11139 | else | |
11140 | bp->cnic_spq_pending++; | |
11141 | } else { | |
11142 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
11143 | bnx2x_panic(); | |
993ac7b5 | 11144 | break; |
c2bff63f | 11145 | } |
993ac7b5 MC |
11146 | |
11147 | spe = bnx2x_sp_get_next(bp); | |
11148 | *spe = *bp->cnic_kwq_cons; | |
11149 | ||
993ac7b5 MC |
11150 | DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", |
11151 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); | |
11152 | ||
11153 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
11154 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
11155 | else | |
11156 | bp->cnic_kwq_cons++; | |
11157 | } | |
11158 | bnx2x_sp_prod_update(bp); | |
11159 | spin_unlock_bh(&bp->spq_lock); | |
11160 | } | |
11161 | ||
11162 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
11163 | struct kwqe_16 *kwqes[], u32 count) | |
11164 | { | |
11165 | struct bnx2x *bp = netdev_priv(dev); | |
11166 | int i; | |
11167 | ||
11168 | #ifdef BNX2X_STOP_ON_ERROR | |
11169 | if (unlikely(bp->panic)) | |
11170 | return -EIO; | |
11171 | #endif | |
11172 | ||
11173 | spin_lock_bh(&bp->spq_lock); | |
11174 | ||
11175 | for (i = 0; i < count; i++) { | |
11176 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
11177 | ||
11178 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
11179 | break; | |
11180 | ||
11181 | *bp->cnic_kwq_prod = *spe; | |
11182 | ||
11183 | bp->cnic_kwq_pending++; | |
11184 | ||
11185 | DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", | |
11186 | spe->hdr.conn_and_cmd_data, spe->hdr.type, | |
523224a3 DK |
11187 | spe->data.update_data_addr.hi, |
11188 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
11189 | bp->cnic_kwq_pending); |
11190 | ||
11191 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
11192 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
11193 | else | |
11194 | bp->cnic_kwq_prod++; | |
11195 | } | |
11196 | ||
11197 | spin_unlock_bh(&bp->spq_lock); | |
11198 | ||
11199 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
11200 | bnx2x_cnic_sp_post(bp, 0); | |
11201 | ||
11202 | return i; | |
11203 | } | |
11204 | ||
11205 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
11206 | { | |
11207 | struct cnic_ops *c_ops; | |
11208 | int rc = 0; | |
11209 | ||
11210 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
11211 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
11212 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
11213 | if (c_ops) |
11214 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
11215 | mutex_unlock(&bp->cnic_mutex); | |
11216 | ||
11217 | return rc; | |
11218 | } | |
11219 | ||
11220 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
11221 | { | |
11222 | struct cnic_ops *c_ops; | |
11223 | int rc = 0; | |
11224 | ||
11225 | rcu_read_lock(); | |
11226 | c_ops = rcu_dereference(bp->cnic_ops); | |
11227 | if (c_ops) | |
11228 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
11229 | rcu_read_unlock(); | |
11230 | ||
11231 | return rc; | |
11232 | } | |
11233 | ||
11234 | /* | |
11235 | * for commands that have no data | |
11236 | */ | |
9f6c9258 | 11237 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
11238 | { |
11239 | struct cnic_ctl_info ctl = {0}; | |
11240 | ||
11241 | ctl.cmd = cmd; | |
11242 | ||
11243 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
11244 | } | |
11245 | ||
619c5cb6 | 11246 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 11247 | { |
619c5cb6 | 11248 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
11249 | |
11250 | /* first we tell CNIC and only then we count this as a completion */ | |
11251 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
11252 | ctl.data.comp.cid = cid; | |
619c5cb6 | 11253 | ctl.data.comp.error = err; |
993ac7b5 MC |
11254 | |
11255 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 11256 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
11257 | } |
11258 | ||
619c5cb6 VZ |
11259 | |
11260 | /* Called with netif_addr_lock_bh() taken. | |
11261 | * Sets an rx_mode config for an iSCSI ETH client. | |
11262 | * Doesn't block. | |
11263 | * Completion should be checked outside. | |
11264 | */ | |
11265 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
11266 | { | |
11267 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
11268 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
11269 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
11270 | ||
11271 | if (start) { | |
11272 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
11273 | * because it's the only way for UIO Queue to accept | |
11274 | * multicasts (in non-promiscuous mode only one Queue per | |
11275 | * function will receive multicast packets (leading in our | |
11276 | * case). | |
11277 | */ | |
11278 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
11279 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
11280 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
11281 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
11282 | ||
11283 | /* Clear STOP_PENDING bit if START is requested */ | |
11284 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
11285 | ||
11286 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
11287 | } else | |
11288 | /* Clear START_PENDING bit if STOP is requested */ | |
11289 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
11290 | ||
11291 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
11292 | set_bit(sched_state, &bp->sp_state); | |
11293 | else { | |
11294 | __set_bit(RAMROD_RX, &ramrod_flags); | |
11295 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
11296 | ramrod_flags); | |
11297 | } | |
11298 | } | |
11299 | ||
11300 | ||
993ac7b5 MC |
11301 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
11302 | { | |
11303 | struct bnx2x *bp = netdev_priv(dev); | |
11304 | int rc = 0; | |
11305 | ||
11306 | switch (ctl->cmd) { | |
11307 | case DRV_CTL_CTXTBL_WR_CMD: { | |
11308 | u32 index = ctl->data.io.offset; | |
11309 | dma_addr_t addr = ctl->data.io.dma_addr; | |
11310 | ||
11311 | bnx2x_ilt_wr(bp, index, addr); | |
11312 | break; | |
11313 | } | |
11314 | ||
c2bff63f DK |
11315 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
11316 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
11317 | |
11318 | bnx2x_cnic_sp_post(bp, count); | |
11319 | break; | |
11320 | } | |
11321 | ||
11322 | /* rtnl_lock is held. */ | |
11323 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
11324 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
11325 | unsigned long sp_bits = 0; | |
11326 | ||
11327 | /* Configure the iSCSI classification object */ | |
11328 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
11329 | cp->iscsi_l2_client_id, | |
11330 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
11331 | bnx2x_sp(bp, mac_rdata), | |
11332 | bnx2x_sp_mapping(bp, mac_rdata), | |
11333 | BNX2X_FILTER_MAC_PENDING, | |
11334 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
11335 | &bp->macs_pool); | |
ec6ba945 | 11336 | |
523224a3 | 11337 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
11338 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
11339 | if (rc) | |
11340 | break; | |
523224a3 DK |
11341 | |
11342 | mmiowb(); | |
11343 | barrier(); | |
11344 | ||
619c5cb6 VZ |
11345 | /* Start accepting on iSCSI L2 ring */ |
11346 | ||
11347 | netif_addr_lock_bh(dev); | |
11348 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
11349 | netif_addr_unlock_bh(dev); | |
11350 | ||
11351 | /* bits to wait on */ | |
11352 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
11353 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
11354 | ||
11355 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
11356 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 11357 | |
993ac7b5 MC |
11358 | break; |
11359 | } | |
11360 | ||
11361 | /* rtnl_lock is held. */ | |
11362 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 11363 | unsigned long sp_bits = 0; |
993ac7b5 | 11364 | |
523224a3 | 11365 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
11366 | netif_addr_lock_bh(dev); |
11367 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
11368 | netif_addr_unlock_bh(dev); | |
11369 | ||
11370 | /* bits to wait on */ | |
11371 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
11372 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
11373 | ||
11374 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
11375 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
11376 | |
11377 | mmiowb(); | |
11378 | barrier(); | |
11379 | ||
11380 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
11381 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
11382 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
11383 | break; |
11384 | } | |
c2bff63f DK |
11385 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
11386 | int count = ctl->data.credit.credit_count; | |
11387 | ||
11388 | smp_mb__before_atomic_inc(); | |
6e30dd4e | 11389 | atomic_add(count, &bp->cq_spq_left); |
c2bff63f DK |
11390 | smp_mb__after_atomic_inc(); |
11391 | break; | |
11392 | } | |
993ac7b5 MC |
11393 | |
11394 | default: | |
11395 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
11396 | rc = -EINVAL; | |
11397 | } | |
11398 | ||
11399 | return rc; | |
11400 | } | |
11401 | ||
9f6c9258 | 11402 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
11403 | { |
11404 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
11405 | ||
11406 | if (bp->flags & USING_MSIX_FLAG) { | |
11407 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
11408 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
11409 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
11410 | } else { | |
11411 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
11412 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
11413 | } | |
619c5cb6 | 11414 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
11415 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
11416 | else | |
11417 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
11418 | ||
619c5cb6 VZ |
11419 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
11420 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
11421 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
11422 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 11423 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
11424 | |
11425 | cp->num_irq = 2; | |
11426 | } | |
11427 | ||
11428 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, | |
11429 | void *data) | |
11430 | { | |
11431 | struct bnx2x *bp = netdev_priv(dev); | |
11432 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
11433 | ||
11434 | if (ops == NULL) | |
11435 | return -EINVAL; | |
11436 | ||
993ac7b5 MC |
11437 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
11438 | if (!bp->cnic_kwq) | |
11439 | return -ENOMEM; | |
11440 | ||
11441 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
11442 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
11443 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
11444 | ||
11445 | bp->cnic_spq_pending = 0; | |
11446 | bp->cnic_kwq_pending = 0; | |
11447 | ||
11448 | bp->cnic_data = data; | |
11449 | ||
11450 | cp->num_irq = 0; | |
619c5cb6 | 11451 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 11452 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 11453 | |
993ac7b5 | 11454 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 11455 | |
993ac7b5 MC |
11456 | rcu_assign_pointer(bp->cnic_ops, ops); |
11457 | ||
11458 | return 0; | |
11459 | } | |
11460 | ||
11461 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
11462 | { | |
11463 | struct bnx2x *bp = netdev_priv(dev); | |
11464 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
11465 | ||
11466 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 MC |
11467 | cp->drv_state = 0; |
11468 | rcu_assign_pointer(bp->cnic_ops, NULL); | |
11469 | mutex_unlock(&bp->cnic_mutex); | |
11470 | synchronize_rcu(); | |
11471 | kfree(bp->cnic_kwq); | |
11472 | bp->cnic_kwq = NULL; | |
11473 | ||
11474 | return 0; | |
11475 | } | |
11476 | ||
11477 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) | |
11478 | { | |
11479 | struct bnx2x *bp = netdev_priv(dev); | |
11480 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
11481 | ||
2ba45142 VZ |
11482 | /* If both iSCSI and FCoE are disabled - return NULL in |
11483 | * order to indicate CNIC that it should not try to work | |
11484 | * with this device. | |
11485 | */ | |
11486 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
11487 | return NULL; | |
11488 | ||
993ac7b5 MC |
11489 | cp->drv_owner = THIS_MODULE; |
11490 | cp->chip_id = CHIP_ID(bp); | |
11491 | cp->pdev = bp->pdev; | |
11492 | cp->io_base = bp->regview; | |
11493 | cp->io_base2 = bp->doorbells; | |
11494 | cp->max_kwqe_pending = 8; | |
523224a3 | 11495 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
11496 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
11497 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 11498 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 11499 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
11500 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
11501 | cp->drv_ctl = bnx2x_drv_ctl; | |
11502 | cp->drv_register_cnic = bnx2x_register_cnic; | |
11503 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
ec6ba945 | 11504 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; |
619c5cb6 VZ |
11505 | cp->iscsi_l2_client_id = |
11506 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
c2bff63f DK |
11507 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; |
11508 | ||
2ba45142 VZ |
11509 | if (NO_ISCSI_OOO(bp)) |
11510 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
11511 | ||
11512 | if (NO_ISCSI(bp)) | |
11513 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
11514 | ||
11515 | if (NO_FCOE(bp)) | |
11516 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
11517 | ||
c2bff63f DK |
11518 | DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " |
11519 | "starting cid %d\n", | |
11520 | cp->ctx_blk_size, | |
11521 | cp->ctx_tbl_offset, | |
11522 | cp->ctx_tbl_len, | |
11523 | cp->starting_cid); | |
993ac7b5 MC |
11524 | return cp; |
11525 | } | |
11526 | EXPORT_SYMBOL(bnx2x_cnic_probe); | |
11527 | ||
11528 | #endif /* BCM_CNIC */ | |
94a78b79 | 11529 |