]>
Commit | Line | Data |
---|---|---|
34f80b04 | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
a2fbb9ea | 2 | * |
85b26ea1 | 3 | * Copyright (c) 2007-2012 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 14 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
15 | * |
16 | */ | |
17 | ||
f1deab50 JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
a2fbb9ea ET |
20 | #include <linux/module.h> |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/device.h> /* for dev_info() */ | |
24 | #include <linux/timer.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/slab.h> | |
a2fbb9ea ET |
28 | #include <linux/interrupt.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/bitops.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/byteorder.h> | |
39 | #include <linux/time.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/mii.h> | |
0c6671b0 | 42 | #include <linux/if_vlan.h> |
a2fbb9ea | 43 | #include <net/ip.h> |
619c5cb6 | 44 | #include <net/ipv6.h> |
a2fbb9ea ET |
45 | #include <net/tcp.h> |
46 | #include <net/checksum.h> | |
34f80b04 | 47 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
48 | #include <linux/workqueue.h> |
49 | #include <linux/crc32.h> | |
34f80b04 | 50 | #include <linux/crc32c.h> |
a2fbb9ea ET |
51 | #include <linux/prefetch.h> |
52 | #include <linux/zlib.h> | |
a2fbb9ea | 53 | #include <linux/io.h> |
452427b0 | 54 | #include <linux/semaphore.h> |
45229b42 | 55 | #include <linux/stringify.h> |
7ab24bfd | 56 | #include <linux/vmalloc.h> |
a2fbb9ea | 57 | |
a2fbb9ea ET |
58 | #include "bnx2x.h" |
59 | #include "bnx2x_init.h" | |
94a78b79 | 60 | #include "bnx2x_init_ops.h" |
9f6c9258 | 61 | #include "bnx2x_cmn.h" |
e4901dde | 62 | #include "bnx2x_dcb.h" |
042181f5 | 63 | #include "bnx2x_sp.h" |
a2fbb9ea | 64 | |
94a78b79 VZ |
65 | #include <linux/firmware.h> |
66 | #include "bnx2x_fw_file_hdr.h" | |
67 | /* FW files */ | |
45229b42 BH |
68 | #define FW_FILE_VERSION \ |
69 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
70 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
71 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
72 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
73 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
74 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 75 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 76 | |
34f80b04 EG |
77 | /* Time in jiffies before concluding the transmitter is hung */ |
78 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 79 | |
53a10565 | 80 | static char version[] __devinitdata = |
619c5cb6 | 81 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
82 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
83 | ||
24e3fcef | 84 | MODULE_AUTHOR("Eliezer Tamir"); |
f2e0899f | 85 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
619c5cb6 VZ |
86 | "BCM57710/57711/57711E/" |
87 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
88 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
89 | MODULE_LICENSE("GPL"); |
90 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
91 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
92 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 93 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 94 | |
ca00392c | 95 | |
d6214d7a | 96 | int num_queues; |
54b9ddaa | 97 | module_param(num_queues, int, 0); |
96305234 DK |
98 | MODULE_PARM_DESC(num_queues, |
99 | " Set number of queues (default is as a number of CPUs)"); | |
555f6c78 | 100 | |
19680c48 | 101 | static int disable_tpa; |
19680c48 | 102 | module_param(disable_tpa, int, 0); |
9898f86d | 103 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 104 | |
9ee3d37b DK |
105 | #define INT_MODE_INTx 1 |
106 | #define INT_MODE_MSI 2 | |
8badd27a EG |
107 | static int int_mode; |
108 | module_param(int_mode, int, 0); | |
619c5cb6 | 109 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 110 | "(1 INT#x; 2 MSI)"); |
8badd27a | 111 | |
a18f5128 EG |
112 | static int dropless_fc; |
113 | module_param(dropless_fc, int, 0); | |
114 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); | |
115 | ||
8d5726c4 EG |
116 | static int mrrs = -1; |
117 | module_param(mrrs, int, 0); | |
118 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); | |
119 | ||
9898f86d | 120 | static int debug; |
a2fbb9ea | 121 | module_param(debug, int, 0); |
9898f86d EG |
122 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
123 | ||
a2fbb9ea | 124 | |
619c5cb6 VZ |
125 | |
126 | struct workqueue_struct *bnx2x_wq; | |
ec6ba945 | 127 | |
a2fbb9ea ET |
128 | enum bnx2x_board_type { |
129 | BCM57710 = 0, | |
619c5cb6 VZ |
130 | BCM57711, |
131 | BCM57711E, | |
132 | BCM57712, | |
133 | BCM57712_MF, | |
134 | BCM57800, | |
135 | BCM57800_MF, | |
136 | BCM57810, | |
137 | BCM57810_MF, | |
138 | BCM57840, | |
7e8e02df BW |
139 | BCM57840_MF, |
140 | BCM57811, | |
141 | BCM57811_MF | |
a2fbb9ea ET |
142 | }; |
143 | ||
34f80b04 | 144 | /* indexed by board_type, above */ |
53a10565 | 145 | static struct { |
a2fbb9ea ET |
146 | char *name; |
147 | } board_info[] __devinitdata = { | |
619c5cb6 VZ |
148 | { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
149 | { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, | |
150 | { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, | |
151 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, | |
152 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, | |
153 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, | |
154 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, | |
155 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, | |
156 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, | |
157 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, | |
7e8e02df BW |
158 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"}, |
159 | { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"}, | |
160 | { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"}, | |
a2fbb9ea ET |
161 | }; |
162 | ||
619c5cb6 VZ |
163 | #ifndef PCI_DEVICE_ID_NX2_57710 |
164 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
165 | #endif | |
166 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
167 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
168 | #endif | |
169 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
170 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
171 | #endif | |
172 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
173 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
174 | #endif | |
175 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
176 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
177 | #endif | |
178 | #ifndef PCI_DEVICE_ID_NX2_57800 | |
179 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
180 | #endif | |
181 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
182 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
183 | #endif | |
184 | #ifndef PCI_DEVICE_ID_NX2_57810 | |
185 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
186 | #endif | |
187 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
188 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
189 | #endif | |
190 | #ifndef PCI_DEVICE_ID_NX2_57840 | |
191 | #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 | |
192 | #endif | |
193 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
194 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
195 | #endif | |
7e8e02df BW |
196 | #ifndef PCI_DEVICE_ID_NX2_57811 |
197 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 | |
198 | #endif | |
199 | #ifndef PCI_DEVICE_ID_NX2_57811_MF | |
200 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF | |
201 | #endif | |
a3aa1884 | 202 | static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { |
e4ed7113 EG |
203 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
204 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
205 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 206 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 VZ |
207 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
208 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, | |
209 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
210 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, | |
211 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
212 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, | |
213 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, | |
7e8e02df BW |
214 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
215 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, | |
a2fbb9ea ET |
216 | { 0 } |
217 | }; | |
218 | ||
219 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
220 | ||
452427b0 YM |
221 | /* Global resources for unloading a previously loaded device */ |
222 | #define BNX2X_PREV_WAIT_NEEDED 1 | |
223 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); | |
224 | static LIST_HEAD(bnx2x_prev_list); | |
a2fbb9ea ET |
225 | /**************************************************************************** |
226 | * General service functions | |
227 | ****************************************************************************/ | |
228 | ||
1191cb83 | 229 | static void __storm_memset_dma_mapping(struct bnx2x *bp, |
619c5cb6 VZ |
230 | u32 addr, dma_addr_t mapping) |
231 | { | |
232 | REG_WR(bp, addr, U64_LO(mapping)); | |
233 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
234 | } | |
235 | ||
1191cb83 ED |
236 | static void storm_memset_spq_addr(struct bnx2x *bp, |
237 | dma_addr_t mapping, u16 abs_fid) | |
619c5cb6 VZ |
238 | { |
239 | u32 addr = XSEM_REG_FAST_MEMORY + | |
240 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
241 | ||
242 | __storm_memset_dma_mapping(bp, addr, mapping); | |
243 | } | |
244 | ||
1191cb83 ED |
245 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, |
246 | u16 pf_id) | |
523224a3 | 247 | { |
619c5cb6 VZ |
248 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
249 | pf_id); | |
250 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
251 | pf_id); | |
252 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
253 | pf_id); | |
254 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
255 | pf_id); | |
523224a3 DK |
256 | } |
257 | ||
1191cb83 ED |
258 | static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
259 | u8 enable) | |
619c5cb6 VZ |
260 | { |
261 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
262 | enable); | |
263 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
264 | enable); | |
265 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
266 | enable); | |
267 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
268 | enable); | |
269 | } | |
523224a3 | 270 | |
1191cb83 ED |
271 | static void storm_memset_eq_data(struct bnx2x *bp, |
272 | struct event_ring_data *eq_data, | |
523224a3 DK |
273 | u16 pfid) |
274 | { | |
275 | size_t size = sizeof(struct event_ring_data); | |
276 | ||
277 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
278 | ||
279 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
280 | } | |
281 | ||
1191cb83 ED |
282 | static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, |
283 | u16 pfid) | |
523224a3 DK |
284 | { |
285 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
286 | REG_WR16(bp, addr, eq_prod); | |
287 | } | |
288 | ||
a2fbb9ea ET |
289 | /* used only at init |
290 | * locking is done by mcp | |
291 | */ | |
8d96286a | 292 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
293 | { |
294 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
295 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
296 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
297 | PCICFG_VENDOR_ID_OFFSET); | |
298 | } | |
299 | ||
a2fbb9ea ET |
300 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
301 | { | |
302 | u32 val; | |
303 | ||
304 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
305 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
306 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
307 | PCICFG_VENDOR_ID_OFFSET); | |
308 | ||
309 | return val; | |
310 | } | |
a2fbb9ea | 311 | |
f2e0899f DK |
312 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
313 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
314 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
315 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
316 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
317 | ||
f2e0899f | 318 | |
a2fbb9ea | 319 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 320 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
321 | { |
322 | u32 cmd_offset; | |
323 | int i; | |
324 | ||
325 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
326 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
327 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
328 | } |
329 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
330 | } | |
331 | ||
f2e0899f | 332 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 333 | { |
f2e0899f DK |
334 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
335 | DMAE_CMD_C_ENABLE); | |
336 | } | |
ad8d3948 | 337 | |
f2e0899f DK |
338 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
339 | { | |
340 | return opcode & ~DMAE_CMD_SRC_RESET; | |
341 | } | |
ad8d3948 | 342 | |
f2e0899f DK |
343 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
344 | bool with_comp, u8 comp_type) | |
345 | { | |
346 | u32 opcode = 0; | |
347 | ||
348 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
349 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 350 | |
f2e0899f DK |
351 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
352 | ||
353 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
354 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
355 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 356 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 357 | |
a2fbb9ea | 358 | #ifdef __BIG_ENDIAN |
f2e0899f | 359 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 360 | #else |
f2e0899f | 361 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 362 | #endif |
f2e0899f DK |
363 | if (with_comp) |
364 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
365 | return opcode; | |
366 | } | |
367 | ||
8d96286a | 368 | static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
369 | struct dmae_command *dmae, | |
370 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
371 | { |
372 | memset(dmae, 0, sizeof(struct dmae_command)); | |
373 | ||
374 | /* set the opcode */ | |
375 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
376 | true, DMAE_COMP_PCI); | |
377 | ||
378 | /* fill in the completion parameters */ | |
379 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
380 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
381 | dmae->comp_val = DMAE_COMP_VAL; | |
382 | } | |
383 | ||
384 | /* issue a dmae command over the init-channel and wailt for completion */ | |
8d96286a | 385 | static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, |
386 | struct dmae_command *dmae) | |
f2e0899f DK |
387 | { |
388 | u32 *wb_comp = bnx2x_sp(bp, wb_comp); | |
5e374b5a | 389 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
390 | int rc = 0; |
391 | ||
619c5cb6 VZ |
392 | /* |
393 | * Lock the dmae channel. Disable BHs to prevent a dead-lock | |
394 | * as long as this code is called both from syscall context and | |
395 | * from ndo_set_rx_mode() flow that may be called from BH. | |
396 | */ | |
6e30dd4e | 397 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 398 | |
f2e0899f | 399 | /* reset completion */ |
a2fbb9ea ET |
400 | *wb_comp = 0; |
401 | ||
f2e0899f DK |
402 | /* post the command on the channel used for initializations */ |
403 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 404 | |
f2e0899f | 405 | /* wait for completion */ |
a2fbb9ea | 406 | udelay(5); |
f2e0899f | 407 | while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 | 408 | |
95c6c616 AE |
409 | if (!cnt || |
410 | (bp->recovery_state != BNX2X_RECOVERY_DONE && | |
411 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
c3eefaf6 | 412 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
413 | rc = DMAE_TIMEOUT; |
414 | goto unlock; | |
a2fbb9ea | 415 | } |
ad8d3948 | 416 | cnt--; |
f2e0899f | 417 | udelay(50); |
a2fbb9ea | 418 | } |
f2e0899f DK |
419 | if (*wb_comp & DMAE_PCI_ERR_FLAG) { |
420 | BNX2X_ERR("DMAE PCI error!\n"); | |
421 | rc = DMAE_PCI_ERROR; | |
422 | } | |
423 | ||
f2e0899f | 424 | unlock: |
6e30dd4e | 425 | spin_unlock_bh(&bp->dmae_lock); |
f2e0899f DK |
426 | return rc; |
427 | } | |
428 | ||
429 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
430 | u32 len32) | |
431 | { | |
432 | struct dmae_command dmae; | |
433 | ||
434 | if (!bp->dmae_ready) { | |
435 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
436 | ||
127a425e AE |
437 | if (CHIP_IS_E1(bp)) |
438 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
439 | else | |
440 | bnx2x_init_str_wr(bp, dst_addr, data, len32); | |
f2e0899f DK |
441 | return; |
442 | } | |
443 | ||
444 | /* set opcode and fixed command fields */ | |
445 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
446 | ||
447 | /* fill in addresses and len */ | |
448 | dmae.src_addr_lo = U64_LO(dma_addr); | |
449 | dmae.src_addr_hi = U64_HI(dma_addr); | |
450 | dmae.dst_addr_lo = dst_addr >> 2; | |
451 | dmae.dst_addr_hi = 0; | |
452 | dmae.len = len32; | |
453 | ||
f2e0899f DK |
454 | /* issue the command and wait for completion */ |
455 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
a2fbb9ea ET |
456 | } |
457 | ||
c18487ee | 458 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 459 | { |
5ff7b6d4 | 460 | struct dmae_command dmae; |
ad8d3948 EG |
461 | |
462 | if (!bp->dmae_ready) { | |
463 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
464 | int i; | |
465 | ||
51c1a580 | 466 | if (CHIP_IS_E1(bp)) |
127a425e AE |
467 | for (i = 0; i < len32; i++) |
468 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
51c1a580 | 469 | else |
127a425e AE |
470 | for (i = 0; i < len32; i++) |
471 | data[i] = REG_RD(bp, src_addr + i*4); | |
472 | ||
ad8d3948 EG |
473 | return; |
474 | } | |
475 | ||
f2e0899f DK |
476 | /* set opcode and fixed command fields */ |
477 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 478 | |
f2e0899f | 479 | /* fill in addresses and len */ |
5ff7b6d4 EG |
480 | dmae.src_addr_lo = src_addr >> 2; |
481 | dmae.src_addr_hi = 0; | |
482 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
483 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
484 | dmae.len = len32; | |
ad8d3948 | 485 | |
f2e0899f DK |
486 | /* issue the command and wait for completion */ |
487 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
ad8d3948 EG |
488 | } |
489 | ||
8d96286a | 490 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
491 | u32 addr, u32 len) | |
573f2035 | 492 | { |
02e3c6cb | 493 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
494 | int offset = 0; |
495 | ||
02e3c6cb | 496 | while (len > dmae_wr_max) { |
573f2035 | 497 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
498 | addr + offset, dmae_wr_max); |
499 | offset += dmae_wr_max * 4; | |
500 | len -= dmae_wr_max; | |
573f2035 EG |
501 | } |
502 | ||
503 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
504 | } | |
505 | ||
a2fbb9ea ET |
506 | static int bnx2x_mc_assert(struct bnx2x *bp) |
507 | { | |
a2fbb9ea | 508 | char last_idx; |
34f80b04 EG |
509 | int i, rc = 0; |
510 | u32 row0, row1, row2, row3; | |
511 | ||
512 | /* XSTORM */ | |
513 | last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + | |
514 | XSTORM_ASSERT_LIST_INDEX_OFFSET); | |
515 | if (last_idx) | |
516 | BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
517 | ||
518 | /* print the asserts */ | |
519 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
520 | ||
521 | row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
522 | XSTORM_ASSERT_LIST_OFFSET(i)); | |
523 | row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
524 | XSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
525 | row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
526 | XSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
527 | row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
528 | XSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
529 | ||
530 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 531 | BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
532 | i, row3, row2, row1, row0); |
533 | rc++; | |
534 | } else { | |
535 | break; | |
536 | } | |
537 | } | |
538 | ||
539 | /* TSTORM */ | |
540 | last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + | |
541 | TSTORM_ASSERT_LIST_INDEX_OFFSET); | |
542 | if (last_idx) | |
543 | BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
544 | ||
545 | /* print the asserts */ | |
546 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
547 | ||
548 | row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
549 | TSTORM_ASSERT_LIST_OFFSET(i)); | |
550 | row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
551 | TSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
552 | row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
553 | TSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
554 | row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
555 | TSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
556 | ||
557 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 558 | BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
559 | i, row3, row2, row1, row0); |
560 | rc++; | |
561 | } else { | |
562 | break; | |
563 | } | |
564 | } | |
565 | ||
566 | /* CSTORM */ | |
567 | last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + | |
568 | CSTORM_ASSERT_LIST_INDEX_OFFSET); | |
569 | if (last_idx) | |
570 | BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
571 | ||
572 | /* print the asserts */ | |
573 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
574 | ||
575 | row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
576 | CSTORM_ASSERT_LIST_OFFSET(i)); | |
577 | row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
578 | CSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
579 | row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
580 | CSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
581 | row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
582 | CSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
583 | ||
584 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 585 | BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
586 | i, row3, row2, row1, row0); |
587 | rc++; | |
588 | } else { | |
589 | break; | |
590 | } | |
591 | } | |
592 | ||
593 | /* USTORM */ | |
594 | last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + | |
595 | USTORM_ASSERT_LIST_INDEX_OFFSET); | |
596 | if (last_idx) | |
597 | BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
598 | ||
599 | /* print the asserts */ | |
600 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
601 | ||
602 | row0 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
603 | USTORM_ASSERT_LIST_OFFSET(i)); | |
604 | row1 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
605 | USTORM_ASSERT_LIST_OFFSET(i) + 4); | |
606 | row2 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
607 | USTORM_ASSERT_LIST_OFFSET(i) + 8); | |
608 | row3 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
609 | USTORM_ASSERT_LIST_OFFSET(i) + 12); | |
610 | ||
611 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 612 | BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
613 | i, row3, row2, row1, row0); |
614 | rc++; | |
615 | } else { | |
616 | break; | |
a2fbb9ea ET |
617 | } |
618 | } | |
34f80b04 | 619 | |
a2fbb9ea ET |
620 | return rc; |
621 | } | |
c14423fe | 622 | |
7a25cc73 | 623 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 624 | { |
7a25cc73 | 625 | u32 addr, val; |
a2fbb9ea | 626 | u32 mark, offset; |
4781bfad | 627 | __be32 data[9]; |
a2fbb9ea | 628 | int word; |
f2e0899f | 629 | u32 trace_shmem_base; |
2145a920 VZ |
630 | if (BP_NOMCP(bp)) { |
631 | BNX2X_ERR("NO MCP - can not dump\n"); | |
632 | return; | |
633 | } | |
7a25cc73 DK |
634 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
635 | (bp->common.bc_ver & 0xff0000) >> 16, | |
636 | (bp->common.bc_ver & 0xff00) >> 8, | |
637 | (bp->common.bc_ver & 0xff)); | |
638 | ||
639 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
640 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
51c1a580 | 641 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
cdaa7cb8 | 642 | |
f2e0899f DK |
643 | if (BP_PATH(bp) == 0) |
644 | trace_shmem_base = bp->common.shmem_base; | |
645 | else | |
646 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
de128804 DK |
647 | addr = trace_shmem_base - 0x800; |
648 | ||
649 | /* validate TRCB signature */ | |
650 | mark = REG_RD(bp, addr); | |
651 | if (mark != MFW_TRACE_SIGNATURE) { | |
652 | BNX2X_ERR("Trace buffer signature is missing."); | |
653 | return ; | |
654 | } | |
655 | ||
656 | /* read cyclic buffer pointer */ | |
657 | addr += 4; | |
cdaa7cb8 | 658 | mark = REG_RD(bp, addr); |
f2e0899f DK |
659 | mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) |
660 | + ((mark + 0x3) & ~0x3) - 0x08000000; | |
7a25cc73 | 661 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 662 | |
7a25cc73 | 663 | printk("%s", lvl); |
f2e0899f | 664 | for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 665 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 666 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 667 | data[8] = 0x0; |
7995c64e | 668 | pr_cont("%s", (char *)data); |
a2fbb9ea | 669 | } |
cdaa7cb8 | 670 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 671 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 672 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 673 | data[8] = 0x0; |
7995c64e | 674 | pr_cont("%s", (char *)data); |
a2fbb9ea | 675 | } |
7a25cc73 DK |
676 | printk("%s" "end of fw dump\n", lvl); |
677 | } | |
678 | ||
1191cb83 | 679 | static void bnx2x_fw_dump(struct bnx2x *bp) |
7a25cc73 DK |
680 | { |
681 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
682 | } |
683 | ||
6c719d00 | 684 | void bnx2x_panic_dump(struct bnx2x *bp) |
a2fbb9ea ET |
685 | { |
686 | int i; | |
523224a3 DK |
687 | u16 j; |
688 | struct hc_sp_status_block_data sp_sb_data; | |
689 | int func = BP_FUNC(bp); | |
690 | #ifdef BNX2X_STOP_ON_ERROR | |
691 | u16 start = 0, end = 0; | |
6383c0b3 | 692 | u8 cos; |
523224a3 | 693 | #endif |
a2fbb9ea | 694 | |
66e855f3 | 695 | bp->stats_state = STATS_STATE_DISABLED; |
7a752993 | 696 | bp->eth_stats.unrecoverable_error++; |
66e855f3 YG |
697 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
698 | ||
a2fbb9ea ET |
699 | BNX2X_ERR("begin crash dump -----------------\n"); |
700 | ||
8440d2b6 EG |
701 | /* Indices */ |
702 | /* Common */ | |
51c1a580 | 703 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", |
619c5cb6 VZ |
704 | bp->def_idx, bp->def_att_idx, bp->attn_state, |
705 | bp->spq_prod_idx, bp->stats_counter); | |
523224a3 DK |
706 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", |
707 | bp->def_status_blk->atten_status_block.attn_bits, | |
708 | bp->def_status_blk->atten_status_block.attn_bits_ack, | |
709 | bp->def_status_blk->atten_status_block.status_block_id, | |
710 | bp->def_status_blk->atten_status_block.attn_bits_index); | |
711 | BNX2X_ERR(" def ("); | |
712 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
713 | pr_cont("0x%x%s", | |
f1deab50 JP |
714 | bp->def_status_blk->sp_sb.index_values[i], |
715 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
523224a3 DK |
716 | |
717 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
718 | *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
719 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
720 | i*sizeof(u32)); | |
721 | ||
f1deab50 | 722 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", |
523224a3 DK |
723 | sp_sb_data.igu_sb_id, |
724 | sp_sb_data.igu_seg_id, | |
725 | sp_sb_data.p_func.pf_id, | |
726 | sp_sb_data.p_func.vnic_id, | |
727 | sp_sb_data.p_func.vf_id, | |
619c5cb6 VZ |
728 | sp_sb_data.p_func.vf_valid, |
729 | sp_sb_data.state); | |
523224a3 | 730 | |
8440d2b6 | 731 | |
ec6ba945 | 732 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 733 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 734 | int loop; |
f2e0899f | 735 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
736 | struct hc_status_block_data_e1x sb_data_e1x; |
737 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
738 | CHIP_IS_E1x(bp) ? |
739 | sb_data_e1x.common.state_machine : | |
740 | sb_data_e2.common.state_machine; | |
523224a3 | 741 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
742 | CHIP_IS_E1x(bp) ? |
743 | sb_data_e1x.index_data : | |
744 | sb_data_e2.index_data; | |
6383c0b3 | 745 | u8 data_size, cos; |
523224a3 | 746 | u32 *sb_data_p; |
6383c0b3 | 747 | struct bnx2x_fp_txdata txdata; |
523224a3 DK |
748 | |
749 | /* Rx */ | |
51c1a580 | 750 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 751 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 752 | fp->rx_comp_prod, |
66e855f3 | 753 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
51c1a580 | 754 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
8440d2b6 | 755 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 756 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 757 | |
523224a3 | 758 | /* Tx */ |
6383c0b3 AE |
759 | for_each_cos_in_tx_queue(fp, cos) |
760 | { | |
65565884 | 761 | txdata = *fp->txdata_ptr[cos]; |
51c1a580 | 762 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
6383c0b3 AE |
763 | i, txdata.tx_pkt_prod, |
764 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
765 | txdata.tx_bd_cons, | |
766 | le16_to_cpu(*txdata.tx_cons_sb)); | |
767 | } | |
523224a3 | 768 | |
619c5cb6 VZ |
769 | loop = CHIP_IS_E1x(bp) ? |
770 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
771 | |
772 | /* host sb data */ | |
773 | ||
ec6ba945 VZ |
774 | #ifdef BCM_CNIC |
775 | if (IS_FCOE_FP(fp)) | |
776 | continue; | |
777 | #endif | |
523224a3 DK |
778 | BNX2X_ERR(" run indexes ("); |
779 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
780 | pr_cont("0x%x%s", | |
781 | fp->sb_running_index[j], | |
782 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
783 | ||
784 | BNX2X_ERR(" indexes ("); | |
785 | for (j = 0; j < loop; j++) | |
786 | pr_cont("0x%x%s", | |
787 | fp->sb_index_values[j], | |
788 | (j == loop - 1) ? ")" : " "); | |
789 | /* fw sb data */ | |
619c5cb6 VZ |
790 | data_size = CHIP_IS_E1x(bp) ? |
791 | sizeof(struct hc_status_block_data_e1x) : | |
792 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 793 | data_size /= sizeof(u32); |
619c5cb6 VZ |
794 | sb_data_p = CHIP_IS_E1x(bp) ? |
795 | (u32 *)&sb_data_e1x : | |
796 | (u32 *)&sb_data_e2; | |
523224a3 DK |
797 | /* copy sb data in here */ |
798 | for (j = 0; j < data_size; j++) | |
799 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
800 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
801 | j * sizeof(u32)); | |
802 | ||
619c5cb6 | 803 | if (!CHIP_IS_E1x(bp)) { |
51c1a580 | 804 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
805 | sb_data_e2.common.p_func.pf_id, |
806 | sb_data_e2.common.p_func.vf_id, | |
807 | sb_data_e2.common.p_func.vf_valid, | |
808 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
809 | sb_data_e2.common.same_igu_sb_1b, |
810 | sb_data_e2.common.state); | |
f2e0899f | 811 | } else { |
51c1a580 | 812 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
813 | sb_data_e1x.common.p_func.pf_id, |
814 | sb_data_e1x.common.p_func.vf_id, | |
815 | sb_data_e1x.common.p_func.vf_valid, | |
816 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
817 | sb_data_e1x.common.same_igu_sb_1b, |
818 | sb_data_e1x.common.state); | |
f2e0899f | 819 | } |
523224a3 DK |
820 | |
821 | /* SB_SMs data */ | |
822 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
51c1a580 MS |
823 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
824 | j, hc_sm_p[j].__flags, | |
825 | hc_sm_p[j].igu_sb_id, | |
826 | hc_sm_p[j].igu_seg_id, | |
827 | hc_sm_p[j].time_to_expire, | |
828 | hc_sm_p[j].timer_value); | |
523224a3 DK |
829 | } |
830 | ||
831 | /* Indecies data */ | |
832 | for (j = 0; j < loop; j++) { | |
51c1a580 | 833 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
523224a3 DK |
834 | hc_index_p[j].flags, |
835 | hc_index_p[j].timeout); | |
836 | } | |
8440d2b6 | 837 | } |
a2fbb9ea | 838 | |
523224a3 | 839 | #ifdef BNX2X_STOP_ON_ERROR |
8440d2b6 EG |
840 | /* Rings */ |
841 | /* Rx */ | |
ec6ba945 | 842 | for_each_rx_queue(bp, i) { |
8440d2b6 | 843 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea ET |
844 | |
845 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); | |
846 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 847 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
848 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
849 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
850 | ||
c3eefaf6 | 851 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
44151acb | 852 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
a2fbb9ea ET |
853 | } |
854 | ||
3196a88a EG |
855 | start = RX_SGE(fp->rx_sge_prod); |
856 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 857 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
858 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
859 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
860 | ||
c3eefaf6 EG |
861 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
862 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
863 | } |
864 | ||
a2fbb9ea ET |
865 | start = RCQ_BD(fp->rx_comp_cons - 10); |
866 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 867 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
868 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
869 | ||
c3eefaf6 EG |
870 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
871 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
872 | } |
873 | } | |
874 | ||
8440d2b6 | 875 | /* Tx */ |
ec6ba945 | 876 | for_each_tx_queue(bp, i) { |
8440d2b6 | 877 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
6383c0b3 | 878 | for_each_cos_in_tx_queue(fp, cos) { |
65565884 | 879 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
6383c0b3 AE |
880 | |
881 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); | |
882 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
883 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
884 | struct sw_tx_bd *sw_bd = | |
885 | &txdata->tx_buf_ring[j]; | |
886 | ||
51c1a580 | 887 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
6383c0b3 AE |
888 | i, cos, j, sw_bd->skb, |
889 | sw_bd->first_bd); | |
890 | } | |
8440d2b6 | 891 | |
6383c0b3 AE |
892 | start = TX_BD(txdata->tx_bd_cons - 10); |
893 | end = TX_BD(txdata->tx_bd_cons + 254); | |
894 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
895 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 896 | |
51c1a580 | 897 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
6383c0b3 AE |
898 | i, cos, j, tx_bd[0], tx_bd[1], |
899 | tx_bd[2], tx_bd[3]); | |
900 | } | |
8440d2b6 EG |
901 | } |
902 | } | |
523224a3 | 903 | #endif |
34f80b04 | 904 | bnx2x_fw_dump(bp); |
a2fbb9ea ET |
905 | bnx2x_mc_assert(bp); |
906 | BNX2X_ERR("end crash dump -----------------\n"); | |
a2fbb9ea ET |
907 | } |
908 | ||
619c5cb6 VZ |
909 | /* |
910 | * FLR Support for E2 | |
911 | * | |
912 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
913 | * initialization. | |
914 | */ | |
915 | #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ | |
89db4ad8 AE |
916 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
917 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ | |
619c5cb6 VZ |
918 | |
919 | struct pbf_pN_buf_regs { | |
920 | int pN; | |
921 | u32 init_crd; | |
922 | u32 crd; | |
923 | u32 crd_freed; | |
924 | }; | |
925 | ||
926 | struct pbf_pN_cmd_regs { | |
927 | int pN; | |
928 | u32 lines_occup; | |
929 | u32 lines_freed; | |
930 | }; | |
931 | ||
932 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
933 | struct pbf_pN_buf_regs *regs, | |
934 | u32 poll_count) | |
935 | { | |
936 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
937 | u32 cur_cnt = poll_count; | |
938 | ||
939 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
940 | crd = crd_start = REG_RD(bp, regs->crd); | |
941 | init_crd = REG_RD(bp, regs->init_crd); | |
942 | ||
943 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
944 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
945 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
946 | ||
947 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
948 | (init_crd - crd_start))) { | |
949 | if (cur_cnt--) { | |
89db4ad8 | 950 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
951 | crd = REG_RD(bp, regs->crd); |
952 | crd_freed = REG_RD(bp, regs->crd_freed); | |
953 | } else { | |
954 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
955 | regs->pN); | |
956 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
957 | regs->pN, crd); | |
958 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
959 | regs->pN, crd_freed); | |
960 | break; | |
961 | } | |
962 | } | |
963 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
89db4ad8 | 964 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
965 | } |
966 | ||
967 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
968 | struct pbf_pN_cmd_regs *regs, | |
969 | u32 poll_count) | |
970 | { | |
971 | u32 occup, to_free, freed, freed_start; | |
972 | u32 cur_cnt = poll_count; | |
973 | ||
974 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
975 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
976 | ||
977 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
978 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
979 | ||
980 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
981 | if (cur_cnt--) { | |
89db4ad8 | 982 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
983 | occup = REG_RD(bp, regs->lines_occup); |
984 | freed = REG_RD(bp, regs->lines_freed); | |
985 | } else { | |
986 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
987 | regs->pN); | |
988 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
989 | regs->pN, occup); | |
990 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
991 | regs->pN, freed); | |
992 | break; | |
993 | } | |
994 | } | |
995 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
89db4ad8 | 996 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
997 | } |
998 | ||
1191cb83 ED |
999 | static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, |
1000 | u32 expected, u32 poll_count) | |
619c5cb6 VZ |
1001 | { |
1002 | u32 cur_cnt = poll_count; | |
1003 | u32 val; | |
1004 | ||
1005 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
89db4ad8 | 1006 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1007 | |
1008 | return val; | |
1009 | } | |
1010 | ||
1191cb83 ED |
1011 | static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, |
1012 | char *msg, u32 poll_cnt) | |
619c5cb6 VZ |
1013 | { |
1014 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1015 | if (val != 0) { | |
1016 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1017 | return 1; | |
1018 | } | |
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
1023 | { | |
1024 | /* adjust polling timeout */ | |
1025 | if (CHIP_REV_IS_EMUL(bp)) | |
1026 | return FLR_POLL_CNT * 2000; | |
1027 | ||
1028 | if (CHIP_REV_IS_FPGA(bp)) | |
1029 | return FLR_POLL_CNT * 120; | |
1030 | ||
1031 | return FLR_POLL_CNT; | |
1032 | } | |
1033 | ||
1034 | static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) | |
1035 | { | |
1036 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1037 | {0, (CHIP_IS_E3B0(bp)) ? | |
1038 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1039 | PBF_REG_P0_TQ_OCCUPANCY, | |
1040 | (CHIP_IS_E3B0(bp)) ? | |
1041 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1042 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1043 | {1, (CHIP_IS_E3B0(bp)) ? | |
1044 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1045 | PBF_REG_P1_TQ_OCCUPANCY, | |
1046 | (CHIP_IS_E3B0(bp)) ? | |
1047 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1048 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1049 | {4, (CHIP_IS_E3B0(bp)) ? | |
1050 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1051 | PBF_REG_P4_TQ_OCCUPANCY, | |
1052 | (CHIP_IS_E3B0(bp)) ? | |
1053 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1054 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1055 | }; | |
1056 | ||
1057 | struct pbf_pN_buf_regs buf_regs[] = { | |
1058 | {0, (CHIP_IS_E3B0(bp)) ? | |
1059 | PBF_REG_INIT_CRD_Q0 : | |
1060 | PBF_REG_P0_INIT_CRD , | |
1061 | (CHIP_IS_E3B0(bp)) ? | |
1062 | PBF_REG_CREDIT_Q0 : | |
1063 | PBF_REG_P0_CREDIT, | |
1064 | (CHIP_IS_E3B0(bp)) ? | |
1065 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1066 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1067 | {1, (CHIP_IS_E3B0(bp)) ? | |
1068 | PBF_REG_INIT_CRD_Q1 : | |
1069 | PBF_REG_P1_INIT_CRD, | |
1070 | (CHIP_IS_E3B0(bp)) ? | |
1071 | PBF_REG_CREDIT_Q1 : | |
1072 | PBF_REG_P1_CREDIT, | |
1073 | (CHIP_IS_E3B0(bp)) ? | |
1074 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1075 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1076 | {4, (CHIP_IS_E3B0(bp)) ? | |
1077 | PBF_REG_INIT_CRD_LB_Q : | |
1078 | PBF_REG_P4_INIT_CRD, | |
1079 | (CHIP_IS_E3B0(bp)) ? | |
1080 | PBF_REG_CREDIT_LB_Q : | |
1081 | PBF_REG_P4_CREDIT, | |
1082 | (CHIP_IS_E3B0(bp)) ? | |
1083 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1084 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1085 | }; | |
1086 | ||
1087 | int i; | |
1088 | ||
1089 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1090 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1091 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1092 | ||
1093 | ||
1094 | /* Verify the transmission buffers are flushed P0, P1, P4 */ | |
1095 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1096 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1097 | } | |
1098 | ||
1099 | #define OP_GEN_PARAM(param) \ | |
1100 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1101 | ||
1102 | #define OP_GEN_TYPE(type) \ | |
1103 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1104 | ||
1105 | #define OP_GEN_AGG_VECT(index) \ | |
1106 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1107 | ||
1108 | ||
1191cb83 | 1109 | static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, |
619c5cb6 VZ |
1110 | u32 poll_cnt) |
1111 | { | |
1112 | struct sdm_op_gen op_gen = {0}; | |
1113 | ||
1114 | u32 comp_addr = BAR_CSTRORM_INTMEM + | |
1115 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1116 | int ret = 0; | |
1117 | ||
1118 | if (REG_RD(bp, comp_addr)) { | |
89db4ad8 | 1119 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
619c5cb6 VZ |
1120 | return 1; |
1121 | } | |
1122 | ||
1123 | op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); | |
1124 | op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1125 | op_gen.command |= OP_GEN_AGG_VECT(clnup_func); | |
1126 | op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
1127 | ||
89db4ad8 | 1128 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
619c5cb6 VZ |
1129 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); |
1130 | ||
1131 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1132 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
51c1a580 MS |
1133 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
1134 | (REG_RD(bp, comp_addr))); | |
619c5cb6 VZ |
1135 | ret = 1; |
1136 | } | |
1137 | /* Zero completion for nxt FLR */ | |
1138 | REG_WR(bp, comp_addr, 0); | |
1139 | ||
1140 | return ret; | |
1141 | } | |
1142 | ||
1191cb83 | 1143 | static u8 bnx2x_is_pcie_pending(struct pci_dev *dev) |
619c5cb6 VZ |
1144 | { |
1145 | int pos; | |
1146 | u16 status; | |
1147 | ||
77c98e6a | 1148 | pos = pci_pcie_cap(dev); |
619c5cb6 VZ |
1149 | if (!pos) |
1150 | return false; | |
1151 | ||
1152 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); | |
1153 | return status & PCI_EXP_DEVSTA_TRPND; | |
1154 | } | |
1155 | ||
1156 | /* PF FLR specific routines | |
1157 | */ | |
1158 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1159 | { | |
1160 | ||
1161 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ | |
1162 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1163 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1164 | "CFC PF usage counter timed out", | |
1165 | poll_cnt)) | |
1166 | return 1; | |
1167 | ||
1168 | ||
1169 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ | |
1170 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1171 | DORQ_REG_PF_USAGE_CNT, | |
1172 | "DQ PF usage counter timed out", | |
1173 | poll_cnt)) | |
1174 | return 1; | |
1175 | ||
1176 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1177 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1178 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1179 | "QM PF usage counter timed out", | |
1180 | poll_cnt)) | |
1181 | return 1; | |
1182 | ||
1183 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1184 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1185 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1186 | "Timers VNIC usage counter timed out", | |
1187 | poll_cnt)) | |
1188 | return 1; | |
1189 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1190 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1191 | "Timers NUM_SCANS usage counter timed out", | |
1192 | poll_cnt)) | |
1193 | return 1; | |
1194 | ||
1195 | /* Wait DMAE PF usage counter to zero */ | |
1196 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1197 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
1198 | "DMAE dommand register timed out", | |
1199 | poll_cnt)) | |
1200 | return 1; | |
1201 | ||
1202 | return 0; | |
1203 | } | |
1204 | ||
1205 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1206 | { | |
1207 | u32 val; | |
1208 | ||
1209 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1210 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1211 | ||
1212 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1213 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1214 | ||
1215 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1216 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1217 | ||
1218 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1219 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1220 | ||
1221 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1222 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1223 | ||
1224 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1225 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1226 | ||
1227 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1228 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1229 | ||
1230 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1231 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1232 | val); | |
1233 | } | |
1234 | ||
1235 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1236 | { | |
1237 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1238 | ||
1239 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1240 | ||
1241 | /* Re-enable PF target read access */ | |
1242 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1243 | ||
1244 | /* Poll HW usage counters */ | |
89db4ad8 | 1245 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
619c5cb6 VZ |
1246 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
1247 | return -EBUSY; | |
1248 | ||
1249 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1250 | ||
1251 | /* Send the FW cleanup command */ | |
1252 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1253 | return -EBUSY; | |
1254 | ||
1255 | /* ATC cleanup */ | |
1256 | ||
1257 | /* Verify TX hw is flushed */ | |
1258 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1259 | ||
1260 | /* Wait 100ms (not adjusted according to platform) */ | |
1261 | msleep(100); | |
1262 | ||
1263 | /* Verify no pending pci transactions */ | |
1264 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1265 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1266 | ||
1267 | /* Debug */ | |
1268 | bnx2x_hw_enable_status(bp); | |
1269 | ||
1270 | /* | |
1271 | * Master enable - Due to WB DMAE writes performed before this | |
1272 | * register is re-initialized as part of the regular function init | |
1273 | */ | |
1274 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1275 | ||
1276 | return 0; | |
1277 | } | |
1278 | ||
f2e0899f | 1279 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1280 | { |
34f80b04 | 1281 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1282 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1283 | u32 val = REG_RD(bp, addr); | |
69c326b3 DK |
1284 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1285 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1286 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
a2fbb9ea ET |
1287 | |
1288 | if (msix) { | |
8badd27a EG |
1289 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1290 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1291 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1292 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
69c326b3 DK |
1293 | if (single_msix) |
1294 | val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; | |
8badd27a EG |
1295 | } else if (msi) { |
1296 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1297 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1298 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1299 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1300 | } else { |
1301 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1302 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1303 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1304 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1305 | |
a0fd065c | 1306 | if (!CHIP_IS_E1(bp)) { |
51c1a580 MS |
1307 | DP(NETIF_MSG_IFUP, |
1308 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); | |
615f8fd9 | 1309 | |
a0fd065c | 1310 | REG_WR(bp, addr, val); |
615f8fd9 | 1311 | |
a0fd065c DK |
1312 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1313 | } | |
a2fbb9ea ET |
1314 | } |
1315 | ||
a0fd065c DK |
1316 | if (CHIP_IS_E1(bp)) |
1317 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1318 | ||
51c1a580 MS |
1319 | DP(NETIF_MSG_IFUP, |
1320 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, | |
1321 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1322 | |
1323 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1324 | /* |
1325 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1326 | */ | |
1327 | mmiowb(); | |
1328 | barrier(); | |
34f80b04 | 1329 | |
f2e0899f | 1330 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1331 | /* init leading/trailing edge */ |
fb3bff17 | 1332 | if (IS_MF(bp)) { |
3395a033 | 1333 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1334 | if (bp->port.pmf) |
4acac6a5 EG |
1335 | /* enable nig and gpio3 attention */ |
1336 | val |= 0x1100; | |
34f80b04 EG |
1337 | } else |
1338 | val = 0xffff; | |
1339 | ||
1340 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1341 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1342 | } | |
37dbbf32 EG |
1343 | |
1344 | /* Make sure that interrupts are indeed enabled from here on */ | |
1345 | mmiowb(); | |
a2fbb9ea ET |
1346 | } |
1347 | ||
f2e0899f DK |
1348 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1349 | { | |
1350 | u32 val; | |
30a5de77 DK |
1351 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1352 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1353 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
f2e0899f DK |
1354 | |
1355 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1356 | ||
1357 | if (msix) { | |
1358 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1359 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1360 | val |= (IGU_PF_CONF_FUNC_EN | | |
1361 | IGU_PF_CONF_MSI_MSIX_EN | | |
1362 | IGU_PF_CONF_ATTN_BIT_EN); | |
30a5de77 DK |
1363 | |
1364 | if (single_msix) | |
1365 | val |= IGU_PF_CONF_SINGLE_ISR_EN; | |
f2e0899f DK |
1366 | } else if (msi) { |
1367 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
1368 | val |= (IGU_PF_CONF_FUNC_EN | | |
1369 | IGU_PF_CONF_MSI_MSIX_EN | | |
1370 | IGU_PF_CONF_ATTN_BIT_EN | | |
1371 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1372 | } else { | |
1373 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
1374 | val |= (IGU_PF_CONF_FUNC_EN | | |
1375 | IGU_PF_CONF_INT_LINE_EN | | |
1376 | IGU_PF_CONF_ATTN_BIT_EN | | |
1377 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1378 | } | |
1379 | ||
51c1a580 | 1380 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
f2e0899f DK |
1381 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
1382 | ||
1383 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1384 | ||
79a8557a YM |
1385 | if (val & IGU_PF_CONF_INT_LINE_EN) |
1386 | pci_intx(bp->pdev, true); | |
1387 | ||
f2e0899f DK |
1388 | barrier(); |
1389 | ||
1390 | /* init leading/trailing edge */ | |
1391 | if (IS_MF(bp)) { | |
3395a033 | 1392 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1393 | if (bp->port.pmf) |
1394 | /* enable nig and gpio3 attention */ | |
1395 | val |= 0x1100; | |
1396 | } else | |
1397 | val = 0xffff; | |
1398 | ||
1399 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1400 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1401 | ||
1402 | /* Make sure that interrupts are indeed enabled from here on */ | |
1403 | mmiowb(); | |
1404 | } | |
1405 | ||
1406 | void bnx2x_int_enable(struct bnx2x *bp) | |
1407 | { | |
1408 | if (bp->common.int_block == INT_BLOCK_HC) | |
1409 | bnx2x_hc_int_enable(bp); | |
1410 | else | |
1411 | bnx2x_igu_int_enable(bp); | |
1412 | } | |
1413 | ||
1414 | static void bnx2x_hc_int_disable(struct bnx2x *bp) | |
a2fbb9ea | 1415 | { |
34f80b04 | 1416 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1417 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1418 | u32 val = REG_RD(bp, addr); | |
1419 | ||
a0fd065c DK |
1420 | /* |
1421 | * in E1 we must use only PCI configuration space to disable | |
1422 | * MSI/MSIX capablility | |
1423 | * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
1424 | */ | |
1425 | if (CHIP_IS_E1(bp)) { | |
1426 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
1427 | * Use mask register to prevent from HC sending interrupts | |
1428 | * after we exit the function | |
1429 | */ | |
1430 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
1431 | ||
1432 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1433 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1434 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
1435 | } else | |
1436 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1437 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1438 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1439 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea | 1440 | |
51c1a580 MS |
1441 | DP(NETIF_MSG_IFDOWN, |
1442 | "write %x to HC %d (addr 0x%x)\n", | |
a2fbb9ea ET |
1443 | val, port, addr); |
1444 | ||
8badd27a EG |
1445 | /* flush all outstanding writes */ |
1446 | mmiowb(); | |
1447 | ||
a2fbb9ea ET |
1448 | REG_WR(bp, addr, val); |
1449 | if (REG_RD(bp, addr) != val) | |
1450 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1451 | } | |
1452 | ||
f2e0899f DK |
1453 | static void bnx2x_igu_int_disable(struct bnx2x *bp) |
1454 | { | |
1455 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1456 | ||
1457 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
1458 | IGU_PF_CONF_INT_LINE_EN | | |
1459 | IGU_PF_CONF_ATTN_BIT_EN); | |
1460 | ||
51c1a580 | 1461 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); |
f2e0899f DK |
1462 | |
1463 | /* flush all outstanding writes */ | |
1464 | mmiowb(); | |
1465 | ||
1466 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1467 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
1468 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1469 | } | |
1470 | ||
6383c0b3 | 1471 | void bnx2x_int_disable(struct bnx2x *bp) |
f2e0899f DK |
1472 | { |
1473 | if (bp->common.int_block == INT_BLOCK_HC) | |
1474 | bnx2x_hc_int_disable(bp); | |
1475 | else | |
1476 | bnx2x_igu_int_disable(bp); | |
1477 | } | |
1478 | ||
9f6c9258 | 1479 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1480 | { |
a2fbb9ea | 1481 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1482 | int i, offset; |
a2fbb9ea | 1483 | |
f8ef6e44 YG |
1484 | if (disable_hw) |
1485 | /* prevent the HW from sending interrupts */ | |
1486 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1487 | |
1488 | /* make sure all ISRs are done */ | |
1489 | if (msix) { | |
8badd27a EG |
1490 | synchronize_irq(bp->msix_table[0].vector); |
1491 | offset = 1; | |
37b091ba MC |
1492 | #ifdef BCM_CNIC |
1493 | offset++; | |
1494 | #endif | |
ec6ba945 | 1495 | for_each_eth_queue(bp, i) |
754a2f52 | 1496 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1497 | } else |
1498 | synchronize_irq(bp->pdev->irq); | |
1499 | ||
1500 | /* make sure sp_task is not running */ | |
1cf167f2 | 1501 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1502 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1503 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1504 | } |
1505 | ||
34f80b04 | 1506 | /* fast path */ |
a2fbb9ea ET |
1507 | |
1508 | /* | |
34f80b04 | 1509 | * General service functions |
a2fbb9ea ET |
1510 | */ |
1511 | ||
72fd0718 VZ |
1512 | /* Return true if succeeded to acquire the lock */ |
1513 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1514 | { | |
1515 | u32 lock_status; | |
1516 | u32 resource_bit = (1 << resource); | |
1517 | int func = BP_FUNC(bp); | |
1518 | u32 hw_lock_control_reg; | |
1519 | ||
51c1a580 MS |
1520 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1521 | "Trying to take a lock on resource %d\n", resource); | |
72fd0718 VZ |
1522 | |
1523 | /* Validating that the resource is within range */ | |
1524 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1525 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
72fd0718 VZ |
1526 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
1527 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1528 | return false; |
72fd0718 VZ |
1529 | } |
1530 | ||
1531 | if (func <= 5) | |
1532 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1533 | else | |
1534 | hw_lock_control_reg = | |
1535 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1536 | ||
1537 | /* Try to acquire the lock */ | |
1538 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1539 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1540 | if (lock_status & resource_bit) | |
1541 | return true; | |
1542 | ||
51c1a580 MS |
1543 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1544 | "Failed to get a lock on resource %d\n", resource); | |
72fd0718 VZ |
1545 | return false; |
1546 | } | |
1547 | ||
c9ee9206 VZ |
1548 | /** |
1549 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1550 | * | |
1551 | * @bp: driver handle | |
1552 | * | |
1553 | * Returns the recovery leader resource id according to the engine this function | |
1554 | * belongs to. Currently only only 2 engines is supported. | |
1555 | */ | |
1191cb83 | 1556 | static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) |
c9ee9206 VZ |
1557 | { |
1558 | if (BP_PATH(bp)) | |
1559 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1560 | else | |
1561 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1562 | } | |
1563 | ||
1564 | /** | |
1565 | * bnx2x_trylock_leader_lock- try to aquire a leader lock. | |
1566 | * | |
1567 | * @bp: driver handle | |
1568 | * | |
1191cb83 | 1569 | * Tries to aquire a leader lock for current engine. |
c9ee9206 | 1570 | */ |
1191cb83 | 1571 | static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) |
c9ee9206 VZ |
1572 | { |
1573 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1574 | } | |
1575 | ||
993ac7b5 | 1576 | #ifdef BCM_CNIC |
619c5cb6 | 1577 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
993ac7b5 | 1578 | #endif |
3196a88a | 1579 | |
619c5cb6 | 1580 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1581 | { |
1582 | struct bnx2x *bp = fp->bp; | |
1583 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1584 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 | 1585 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
15192a8c | 1586 | struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a2fbb9ea | 1587 | |
34f80b04 | 1588 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1589 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1590 | fp->index, cid, command, bp->state, |
34f80b04 | 1591 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1592 | |
619c5cb6 VZ |
1593 | switch (command) { |
1594 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1595 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1596 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1597 | break; | |
d6cae238 | 1598 | |
619c5cb6 | 1599 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1600 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1601 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1602 | break; |
1603 | ||
6383c0b3 | 1604 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
51c1a580 | 1605 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
6383c0b3 AE |
1606 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
1607 | break; | |
1608 | ||
619c5cb6 | 1609 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1610 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1611 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1612 | break; |
1613 | ||
619c5cb6 | 1614 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
d6cae238 | 1615 | DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); |
619c5cb6 | 1616 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1617 | break; |
1618 | ||
619c5cb6 | 1619 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1620 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1621 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1622 | break; |
619c5cb6 VZ |
1623 | |
1624 | default: | |
1625 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1626 | command, fp->index); | |
1627 | return; | |
523224a3 | 1628 | } |
3196a88a | 1629 | |
619c5cb6 VZ |
1630 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1631 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1632 | /* q_obj->complete_cmd() failure means that this was | |
1633 | * an unexpected completion. | |
1634 | * | |
1635 | * In this case we don't want to increase the bp->spq_left | |
1636 | * because apparently we haven't sent this command the first | |
1637 | * place. | |
1638 | */ | |
1639 | #ifdef BNX2X_STOP_ON_ERROR | |
1640 | bnx2x_panic(); | |
1641 | #else | |
1642 | return; | |
1643 | #endif | |
1644 | ||
8fe23fbd | 1645 | smp_mb__before_atomic_inc(); |
6e30dd4e | 1646 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 VZ |
1647 | /* push the change in bp->spq_left and towards the memory */ |
1648 | smp_mb__after_atomic_inc(); | |
49d66772 | 1649 | |
d6cae238 VZ |
1650 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1651 | ||
a3348722 BW |
1652 | if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && |
1653 | (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { | |
1654 | /* if Q update ramrod is completed for last Q in AFEX vif set | |
1655 | * flow, then ACK MCP at the end | |
1656 | * | |
1657 | * mark pending ACK to MCP bit. | |
1658 | * prevent case that both bits are cleared. | |
1659 | * At the end of load/unload driver checks that | |
1660 | * sp_state is cleaerd, and this order prevents | |
1661 | * races | |
1662 | */ | |
1663 | smp_mb__before_clear_bit(); | |
1664 | set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); | |
1665 | wmb(); | |
1666 | clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
1667 | smp_mb__after_clear_bit(); | |
1668 | ||
1669 | /* schedule workqueue to send ack to MCP */ | |
1670 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); | |
1671 | } | |
1672 | ||
523224a3 | 1673 | return; |
a2fbb9ea ET |
1674 | } |
1675 | ||
619c5cb6 VZ |
1676 | void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
1677 | u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) | |
1678 | { | |
1679 | u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; | |
1680 | ||
1681 | bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, | |
1682 | start); | |
1683 | } | |
1684 | ||
9f6c9258 | 1685 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1686 | { |
555f6c78 | 1687 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1688 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1689 | u16 mask; |
ca00392c | 1690 | int i; |
6383c0b3 | 1691 | u8 cos; |
a2fbb9ea | 1692 | |
34f80b04 | 1693 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1694 | if (unlikely(status == 0)) { |
1695 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1696 | return IRQ_NONE; | |
1697 | } | |
f5372251 | 1698 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1699 | |
3196a88a EG |
1700 | #ifdef BNX2X_STOP_ON_ERROR |
1701 | if (unlikely(bp->panic)) | |
1702 | return IRQ_HANDLED; | |
1703 | #endif | |
1704 | ||
ec6ba945 | 1705 | for_each_eth_queue(bp, i) { |
ca00392c | 1706 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1707 | |
6383c0b3 | 1708 | mask = 0x2 << (fp->index + CNIC_PRESENT); |
ca00392c | 1709 | if (status & mask) { |
619c5cb6 | 1710 | /* Handle Rx or Tx according to SB id */ |
54b9ddaa | 1711 | prefetch(fp->rx_cons_sb); |
6383c0b3 | 1712 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 1713 | prefetch(fp->txdata_ptr[cos]->tx_cons_sb); |
523224a3 | 1714 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
54b9ddaa | 1715 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1716 | status &= ~mask; |
1717 | } | |
a2fbb9ea ET |
1718 | } |
1719 | ||
993ac7b5 | 1720 | #ifdef BCM_CNIC |
523224a3 | 1721 | mask = 0x2; |
993ac7b5 MC |
1722 | if (status & (mask | 0x1)) { |
1723 | struct cnic_ops *c_ops = NULL; | |
1724 | ||
619c5cb6 VZ |
1725 | if (likely(bp->state == BNX2X_STATE_OPEN)) { |
1726 | rcu_read_lock(); | |
1727 | c_ops = rcu_dereference(bp->cnic_ops); | |
1728 | if (c_ops) | |
1729 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1730 | rcu_read_unlock(); | |
1731 | } | |
993ac7b5 MC |
1732 | |
1733 | status &= ~mask; | |
1734 | } | |
1735 | #endif | |
a2fbb9ea | 1736 | |
34f80b04 | 1737 | if (unlikely(status & 0x1)) { |
1cf167f2 | 1738 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
1739 | |
1740 | status &= ~0x1; | |
1741 | if (!status) | |
1742 | return IRQ_HANDLED; | |
1743 | } | |
1744 | ||
cdaa7cb8 VZ |
1745 | if (unlikely(status)) |
1746 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1747 | status); |
a2fbb9ea | 1748 | |
c18487ee | 1749 | return IRQ_HANDLED; |
a2fbb9ea ET |
1750 | } |
1751 | ||
c18487ee YR |
1752 | /* Link */ |
1753 | ||
1754 | /* | |
1755 | * General service functions | |
1756 | */ | |
a2fbb9ea | 1757 | |
9f6c9258 | 1758 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1759 | { |
1760 | u32 lock_status; | |
1761 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1762 | int func = BP_FUNC(bp); |
1763 | u32 hw_lock_control_reg; | |
c18487ee | 1764 | int cnt; |
a2fbb9ea | 1765 | |
c18487ee YR |
1766 | /* Validating that the resource is within range */ |
1767 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1768 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1769 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1770 | return -EINVAL; | |
1771 | } | |
a2fbb9ea | 1772 | |
4a37fb66 YG |
1773 | if (func <= 5) { |
1774 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1775 | } else { | |
1776 | hw_lock_control_reg = | |
1777 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1778 | } | |
1779 | ||
c18487ee | 1780 | /* Validating that the resource is not already taken */ |
4a37fb66 | 1781 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1782 | if (lock_status & resource_bit) { |
51c1a580 | 1783 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
c18487ee YR |
1784 | lock_status, resource_bit); |
1785 | return -EEXIST; | |
1786 | } | |
a2fbb9ea | 1787 | |
46230476 EG |
1788 | /* Try for 5 second every 5ms */ |
1789 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 1790 | /* Try to acquire the lock */ |
4a37fb66 YG |
1791 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
1792 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
1793 | if (lock_status & resource_bit) |
1794 | return 0; | |
a2fbb9ea | 1795 | |
c18487ee | 1796 | msleep(5); |
a2fbb9ea | 1797 | } |
51c1a580 | 1798 | BNX2X_ERR("Timeout\n"); |
c18487ee YR |
1799 | return -EAGAIN; |
1800 | } | |
a2fbb9ea | 1801 | |
c9ee9206 VZ |
1802 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
1803 | { | |
1804 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1805 | } | |
1806 | ||
9f6c9258 | 1807 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1808 | { |
1809 | u32 lock_status; | |
1810 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1811 | int func = BP_FUNC(bp); |
1812 | u32 hw_lock_control_reg; | |
a2fbb9ea | 1813 | |
c18487ee YR |
1814 | /* Validating that the resource is within range */ |
1815 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1816 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1817 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1818 | return -EINVAL; | |
1819 | } | |
1820 | ||
4a37fb66 YG |
1821 | if (func <= 5) { |
1822 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1823 | } else { | |
1824 | hw_lock_control_reg = | |
1825 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1826 | } | |
1827 | ||
c18487ee | 1828 | /* Validating that the resource is currently taken */ |
4a37fb66 | 1829 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1830 | if (!(lock_status & resource_bit)) { |
51c1a580 | 1831 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n", |
c18487ee YR |
1832 | lock_status, resource_bit); |
1833 | return -EFAULT; | |
a2fbb9ea ET |
1834 | } |
1835 | ||
9f6c9258 DK |
1836 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
1837 | return 0; | |
c18487ee | 1838 | } |
a2fbb9ea | 1839 | |
9f6c9258 | 1840 | |
4acac6a5 EG |
1841 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
1842 | { | |
1843 | /* The GPIO should be swapped if swap register is set and active */ | |
1844 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1845 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1846 | int gpio_shift = gpio_num + | |
1847 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1848 | u32 gpio_mask = (1 << gpio_shift); | |
1849 | u32 gpio_reg; | |
1850 | int value; | |
1851 | ||
1852 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1853 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1854 | return -EINVAL; | |
1855 | } | |
1856 | ||
1857 | /* read GPIO value */ | |
1858 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1859 | ||
1860 | /* get the requested pin value */ | |
1861 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
1862 | value = 1; | |
1863 | else | |
1864 | value = 0; | |
1865 | ||
1866 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); | |
1867 | ||
1868 | return value; | |
1869 | } | |
1870 | ||
17de50b7 | 1871 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
1872 | { |
1873 | /* The GPIO should be swapped if swap register is set and active */ | |
1874 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 1875 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
1876 | int gpio_shift = gpio_num + |
1877 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1878 | u32 gpio_mask = (1 << gpio_shift); | |
1879 | u32 gpio_reg; | |
a2fbb9ea | 1880 | |
c18487ee YR |
1881 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
1882 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1883 | return -EINVAL; | |
1884 | } | |
a2fbb9ea | 1885 | |
4a37fb66 | 1886 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
1887 | /* read GPIO and mask except the float bits */ |
1888 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 1889 | |
c18487ee YR |
1890 | switch (mode) { |
1891 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
51c1a580 MS |
1892 | DP(NETIF_MSG_LINK, |
1893 | "Set GPIO %d (shift %d) -> output low\n", | |
c18487ee YR |
1894 | gpio_num, gpio_shift); |
1895 | /* clear FLOAT and set CLR */ | |
1896 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1897 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
1898 | break; | |
a2fbb9ea | 1899 | |
c18487ee | 1900 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
51c1a580 MS |
1901 | DP(NETIF_MSG_LINK, |
1902 | "Set GPIO %d (shift %d) -> output high\n", | |
c18487ee YR |
1903 | gpio_num, gpio_shift); |
1904 | /* clear FLOAT and set SET */ | |
1905 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1906 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
1907 | break; | |
a2fbb9ea | 1908 | |
17de50b7 | 1909 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
51c1a580 MS |
1910 | DP(NETIF_MSG_LINK, |
1911 | "Set GPIO %d (shift %d) -> input\n", | |
c18487ee YR |
1912 | gpio_num, gpio_shift); |
1913 | /* set FLOAT */ | |
1914 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1915 | break; | |
a2fbb9ea | 1916 | |
c18487ee YR |
1917 | default: |
1918 | break; | |
a2fbb9ea ET |
1919 | } |
1920 | ||
c18487ee | 1921 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 1922 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 1923 | |
c18487ee | 1924 | return 0; |
a2fbb9ea ET |
1925 | } |
1926 | ||
0d40f0d4 YR |
1927 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
1928 | { | |
1929 | u32 gpio_reg = 0; | |
1930 | int rc = 0; | |
1931 | ||
1932 | /* Any port swapping should be handled by caller. */ | |
1933 | ||
1934 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1935 | /* read GPIO and mask except the float bits */ | |
1936 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1937 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1938 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1939 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
1940 | ||
1941 | switch (mode) { | |
1942 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
1943 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
1944 | /* set CLR */ | |
1945 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1946 | break; | |
1947 | ||
1948 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
1949 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
1950 | /* set SET */ | |
1951 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
1952 | break; | |
1953 | ||
1954 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
1955 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
1956 | /* set FLOAT */ | |
1957 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1958 | break; | |
1959 | ||
1960 | default: | |
1961 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
1962 | rc = -EINVAL; | |
1963 | break; | |
1964 | } | |
1965 | ||
1966 | if (rc == 0) | |
1967 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
1968 | ||
1969 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1970 | ||
1971 | return rc; | |
1972 | } | |
1973 | ||
4acac6a5 EG |
1974 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
1975 | { | |
1976 | /* The GPIO should be swapped if swap register is set and active */ | |
1977 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1978 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1979 | int gpio_shift = gpio_num + | |
1980 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1981 | u32 gpio_mask = (1 << gpio_shift); | |
1982 | u32 gpio_reg; | |
1983 | ||
1984 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1985 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1986 | return -EINVAL; | |
1987 | } | |
1988 | ||
1989 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1990 | /* read GPIO int */ | |
1991 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
1992 | ||
1993 | switch (mode) { | |
1994 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
51c1a580 MS |
1995 | DP(NETIF_MSG_LINK, |
1996 | "Clear GPIO INT %d (shift %d) -> output low\n", | |
1997 | gpio_num, gpio_shift); | |
4acac6a5 EG |
1998 | /* clear SET and set CLR */ |
1999 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2000 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2001 | break; | |
2002 | ||
2003 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
51c1a580 MS |
2004 | DP(NETIF_MSG_LINK, |
2005 | "Set GPIO INT %d (shift %d) -> output high\n", | |
2006 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2007 | /* clear CLR and set SET */ |
2008 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2009 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2010 | break; | |
2011 | ||
2012 | default: | |
2013 | break; | |
2014 | } | |
2015 | ||
2016 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2017 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2018 | ||
2019 | return 0; | |
2020 | } | |
2021 | ||
c18487ee | 2022 | static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) |
a2fbb9ea | 2023 | { |
c18487ee YR |
2024 | u32 spio_mask = (1 << spio_num); |
2025 | u32 spio_reg; | |
a2fbb9ea | 2026 | |
c18487ee YR |
2027 | if ((spio_num < MISC_REGISTERS_SPIO_4) || |
2028 | (spio_num > MISC_REGISTERS_SPIO_7)) { | |
2029 | BNX2X_ERR("Invalid SPIO %d\n", spio_num); | |
2030 | return -EINVAL; | |
a2fbb9ea ET |
2031 | } |
2032 | ||
4a37fb66 | 2033 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee YR |
2034 | /* read SPIO and mask except the float bits */ |
2035 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); | |
a2fbb9ea | 2036 | |
c18487ee | 2037 | switch (mode) { |
6378c025 | 2038 | case MISC_REGISTERS_SPIO_OUTPUT_LOW: |
51c1a580 | 2039 | DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num); |
c18487ee YR |
2040 | /* clear FLOAT and set CLR */ |
2041 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2042 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); | |
2043 | break; | |
a2fbb9ea | 2044 | |
6378c025 | 2045 | case MISC_REGISTERS_SPIO_OUTPUT_HIGH: |
51c1a580 | 2046 | DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num); |
c18487ee YR |
2047 | /* clear FLOAT and set SET */ |
2048 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2049 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); | |
2050 | break; | |
a2fbb9ea | 2051 | |
c18487ee | 2052 | case MISC_REGISTERS_SPIO_INPUT_HI_Z: |
51c1a580 | 2053 | DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num); |
c18487ee YR |
2054 | /* set FLOAT */ |
2055 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2056 | break; | |
a2fbb9ea | 2057 | |
c18487ee YR |
2058 | default: |
2059 | break; | |
a2fbb9ea ET |
2060 | } |
2061 | ||
c18487ee | 2062 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2063 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2064 | |
a2fbb9ea ET |
2065 | return 0; |
2066 | } | |
2067 | ||
9f6c9258 | 2068 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2069 | { |
a22f0788 | 2070 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
ad33ea3a EG |
2071 | switch (bp->link_vars.ieee_fc & |
2072 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2073 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: |
a22f0788 | 2074 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2075 | ADVERTISED_Pause); |
c18487ee | 2076 | break; |
356e2385 | 2077 | |
c18487ee | 2078 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2079 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2080 | ADVERTISED_Pause); |
c18487ee | 2081 | break; |
356e2385 | 2082 | |
c18487ee | 2083 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2084 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2085 | break; |
356e2385 | 2086 | |
c18487ee | 2087 | default: |
a22f0788 | 2088 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2089 | ADVERTISED_Pause); |
c18487ee YR |
2090 | break; |
2091 | } | |
2092 | } | |
f1410647 | 2093 | |
9f6c9258 | 2094 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
c18487ee | 2095 | { |
19680c48 EG |
2096 | if (!BP_NOMCP(bp)) { |
2097 | u8 rc; | |
a22f0788 YR |
2098 | int cfx_idx = bnx2x_get_link_cfg_idx(bp); |
2099 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
1cb0c788 YR |
2100 | /* |
2101 | * Initialize link parameters structure variables | |
2102 | * It is recommended to turn off RX FC for jumbo frames | |
2103 | * for better performance | |
2104 | */ | |
2105 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
c0700f90 | 2106 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; |
8c99e7b0 | 2107 | else |
c0700f90 | 2108 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; |
a2fbb9ea | 2109 | |
4a37fb66 | 2110 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2111 | |
a22f0788 | 2112 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2113 | struct link_params *lp = &bp->link_params; |
2114 | lp->loopback_mode = LOOPBACK_XGXS; | |
2115 | /* do PHY loopback at 10G speed, if possible */ | |
2116 | if (lp->req_line_speed[cfx_idx] < SPEED_10000) { | |
2117 | if (lp->speed_cap_mask[cfx_idx] & | |
2118 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2119 | lp->req_line_speed[cfx_idx] = | |
2120 | SPEED_10000; | |
2121 | else | |
2122 | lp->req_line_speed[cfx_idx] = | |
2123 | SPEED_1000; | |
2124 | } | |
a22f0788 | 2125 | } |
b5bf9068 | 2126 | |
8970b2e4 MS |
2127 | if (load_mode == LOAD_LOOPBACK_EXT) { |
2128 | struct link_params *lp = &bp->link_params; | |
2129 | lp->loopback_mode = LOOPBACK_EXT; | |
2130 | } | |
2131 | ||
19680c48 | 2132 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2133 | |
4a37fb66 | 2134 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2135 | |
3c96c68b EG |
2136 | bnx2x_calc_fc_adv(bp); |
2137 | ||
b5bf9068 EG |
2138 | if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { |
2139 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
19680c48 | 2140 | bnx2x_link_report(bp); |
3deb8167 YR |
2141 | } else |
2142 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2143 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2144 | return rc; |
2145 | } | |
f5372251 | 2146 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2147 | return -EINVAL; |
a2fbb9ea ET |
2148 | } |
2149 | ||
9f6c9258 | 2150 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2151 | { |
19680c48 | 2152 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2153 | bnx2x_acquire_phy_lock(bp); |
54c2fb78 | 2154 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
19680c48 | 2155 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2156 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2157 | |
19680c48 EG |
2158 | bnx2x_calc_fc_adv(bp); |
2159 | } else | |
f5372251 | 2160 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2161 | } |
a2fbb9ea | 2162 | |
c18487ee YR |
2163 | static void bnx2x__link_reset(struct bnx2x *bp) |
2164 | { | |
19680c48 | 2165 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2166 | bnx2x_acquire_phy_lock(bp); |
589abe3a | 2167 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
4a37fb66 | 2168 | bnx2x_release_phy_lock(bp); |
19680c48 | 2169 | } else |
f5372251 | 2170 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2171 | } |
a2fbb9ea | 2172 | |
a22f0788 | 2173 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2174 | { |
2145a920 | 2175 | u8 rc = 0; |
a2fbb9ea | 2176 | |
2145a920 VZ |
2177 | if (!BP_NOMCP(bp)) { |
2178 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2179 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2180 | is_serdes); | |
2145a920 VZ |
2181 | bnx2x_release_phy_lock(bp); |
2182 | } else | |
2183 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2184 | |
c18487ee YR |
2185 | return rc; |
2186 | } | |
a2fbb9ea | 2187 | |
34f80b04 | 2188 | |
2691d51d EG |
2189 | /* Calculates the sum of vn_min_rates. |
2190 | It's needed for further normalizing of the min_rates. | |
2191 | Returns: | |
2192 | sum of vn_min_rates. | |
2193 | or | |
2194 | 0 - if all the min_rates are 0. | |
2195 | In the later case fainess algorithm should be deactivated. | |
2196 | If not all min_rates are zero then those that are zeroes will be set to 1. | |
2197 | */ | |
b475d78f YM |
2198 | static void bnx2x_calc_vn_min(struct bnx2x *bp, |
2199 | struct cmng_init_input *input) | |
2691d51d EG |
2200 | { |
2201 | int all_zero = 1; | |
2691d51d EG |
2202 | int vn; |
2203 | ||
3395a033 | 2204 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2205 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2206 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2207 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2208 | ||
2209 | /* Skip hidden vns */ | |
2210 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
b475d78f | 2211 | vn_min_rate = 0; |
2691d51d | 2212 | /* If min rate is zero - set it to 1 */ |
b475d78f | 2213 | else if (!vn_min_rate) |
2691d51d EG |
2214 | vn_min_rate = DEF_MIN_RATE; |
2215 | else | |
2216 | all_zero = 0; | |
2217 | ||
b475d78f | 2218 | input->vnic_min_rate[vn] = vn_min_rate; |
2691d51d EG |
2219 | } |
2220 | ||
30ae438b DK |
2221 | /* if ETS or all min rates are zeros - disable fairness */ |
2222 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
b475d78f | 2223 | input->flags.cmng_enables &= |
30ae438b DK |
2224 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2225 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2226 | } else if (all_zero) { | |
b475d78f | 2227 | input->flags.cmng_enables &= |
b015e3d1 | 2228 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
b475d78f YM |
2229 | DP(NETIF_MSG_IFUP, |
2230 | "All MIN values are zeroes fairness will be disabled\n"); | |
b015e3d1 | 2231 | } else |
b475d78f | 2232 | input->flags.cmng_enables |= |
b015e3d1 | 2233 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2691d51d EG |
2234 | } |
2235 | ||
b475d78f YM |
2236 | static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, |
2237 | struct cmng_init_input *input) | |
34f80b04 | 2238 | { |
b475d78f | 2239 | u16 vn_max_rate; |
f2e0899f | 2240 | u32 vn_cfg = bp->mf_config[vn]; |
34f80b04 | 2241 | |
b475d78f | 2242 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
34f80b04 | 2243 | vn_max_rate = 0; |
b475d78f | 2244 | else { |
faa6fcbb DK |
2245 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2246 | ||
b475d78f | 2247 | if (IS_MF_SI(bp)) { |
faa6fcbb DK |
2248 | /* maxCfg in percents of linkspeed */ |
2249 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
b475d78f | 2250 | } else /* SD modes */ |
faa6fcbb DK |
2251 | /* maxCfg is absolute in 100Mb units */ |
2252 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2253 | } |
f85582f8 | 2254 | |
b475d78f | 2255 | DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); |
34f80b04 | 2256 | |
b475d78f | 2257 | input->vnic_max_rate[vn] = vn_max_rate; |
34f80b04 | 2258 | } |
f85582f8 | 2259 | |
b475d78f | 2260 | |
523224a3 DK |
2261 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2262 | { | |
2263 | if (CHIP_REV_IS_SLOW(bp)) | |
2264 | return CMNG_FNS_NONE; | |
fb3bff17 | 2265 | if (IS_MF(bp)) |
523224a3 DK |
2266 | return CMNG_FNS_MINMAX; |
2267 | ||
2268 | return CMNG_FNS_NONE; | |
2269 | } | |
2270 | ||
2ae17f66 | 2271 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2272 | { |
0793f83f | 2273 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2274 | |
2275 | if (BP_NOMCP(bp)) | |
2276 | return; /* what should be the default bvalue in this case */ | |
2277 | ||
0793f83f DK |
2278 | /* For 2 port configuration the absolute function number formula |
2279 | * is: | |
2280 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2281 | * | |
2282 | * and there are 4 functions per port | |
2283 | * | |
2284 | * For 4 port configuration it is | |
2285 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2286 | * | |
2287 | * and there are 2 functions per port | |
2288 | */ | |
3395a033 | 2289 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2290 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2291 | ||
2292 | if (func >= E1H_FUNC_MAX) | |
2293 | break; | |
2294 | ||
f2e0899f | 2295 | bp->mf_config[vn] = |
523224a3 DK |
2296 | MF_CFG_RD(bp, func_mf_config[func].config); |
2297 | } | |
a3348722 BW |
2298 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
2299 | DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); | |
2300 | bp->flags |= MF_FUNC_DIS; | |
2301 | } else { | |
2302 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2303 | bp->flags &= ~MF_FUNC_DIS; | |
2304 | } | |
523224a3 DK |
2305 | } |
2306 | ||
2307 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2308 | { | |
b475d78f YM |
2309 | struct cmng_init_input input; |
2310 | memset(&input, 0, sizeof(struct cmng_init_input)); | |
2311 | ||
2312 | input.port_rate = bp->link_vars.line_speed; | |
523224a3 DK |
2313 | |
2314 | if (cmng_type == CMNG_FNS_MINMAX) { | |
2315 | int vn; | |
2316 | ||
523224a3 DK |
2317 | /* read mf conf from shmem */ |
2318 | if (read_cfg) | |
2319 | bnx2x_read_mf_cfg(bp); | |
2320 | ||
523224a3 | 2321 | /* vn_weight_sum and enable fairness if not 0 */ |
b475d78f | 2322 | bnx2x_calc_vn_min(bp, &input); |
523224a3 DK |
2323 | |
2324 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2325 | if (bp->port.pmf) |
3395a033 | 2326 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
b475d78f | 2327 | bnx2x_calc_vn_max(bp, vn, &input); |
523224a3 DK |
2328 | |
2329 | /* always enable rate shaping and fairness */ | |
b475d78f | 2330 | input.flags.cmng_enables |= |
523224a3 | 2331 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; |
b475d78f YM |
2332 | |
2333 | bnx2x_init_cmng(&input, &bp->cmng); | |
523224a3 DK |
2334 | return; |
2335 | } | |
2336 | ||
2337 | /* rate shaping and fairness are disabled */ | |
2338 | DP(NETIF_MSG_IFUP, | |
2339 | "rate shaping and fairness are disabled\n"); | |
2340 | } | |
34f80b04 | 2341 | |
1191cb83 ED |
2342 | static void storm_memset_cmng(struct bnx2x *bp, |
2343 | struct cmng_init *cmng, | |
2344 | u8 port) | |
2345 | { | |
2346 | int vn; | |
2347 | size_t size = sizeof(struct cmng_struct_per_port); | |
2348 | ||
2349 | u32 addr = BAR_XSTRORM_INTMEM + | |
2350 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
2351 | ||
2352 | __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); | |
2353 | ||
2354 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
2355 | int func = func_by_vn(bp, vn); | |
2356 | ||
2357 | addr = BAR_XSTRORM_INTMEM + | |
2358 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); | |
2359 | size = sizeof(struct rate_shaping_vars_per_vn); | |
2360 | __storm_memset_struct(bp, addr, size, | |
2361 | (u32 *)&cmng->vnic.vnic_max_rate[vn]); | |
2362 | ||
2363 | addr = BAR_XSTRORM_INTMEM + | |
2364 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); | |
2365 | size = sizeof(struct fairness_vars_per_vn); | |
2366 | __storm_memset_struct(bp, addr, size, | |
2367 | (u32 *)&cmng->vnic.vnic_min_rate[vn]); | |
2368 | } | |
2369 | } | |
2370 | ||
c18487ee YR |
2371 | /* This function is called upon link interrupt */ |
2372 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2373 | { | |
bb2a0f7a YG |
2374 | /* Make sure that we are synced with the current statistics */ |
2375 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2376 | ||
c18487ee | 2377 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2378 | |
bb2a0f7a YG |
2379 | if (bp->link_vars.link_up) { |
2380 | ||
1c06328c | 2381 | /* dropless flow control */ |
f2e0899f | 2382 | if (!CHIP_IS_E1(bp) && bp->dropless_fc) { |
1c06328c EG |
2383 | int port = BP_PORT(bp); |
2384 | u32 pause_enabled = 0; | |
2385 | ||
2386 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2387 | pause_enabled = 1; | |
2388 | ||
2389 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
ca00392c | 2390 | USTORM_ETH_PAUSE_ENABLED_OFFSET(port), |
1c06328c EG |
2391 | pause_enabled); |
2392 | } | |
2393 | ||
619c5cb6 | 2394 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2395 | struct host_port_stats *pstats; |
2396 | ||
2397 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2398 | /* reset old mac stats */ |
bb2a0f7a YG |
2399 | memset(&(pstats->mac_stx[0]), 0, |
2400 | sizeof(struct mac_stx)); | |
2401 | } | |
f34d28ea | 2402 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2403 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2404 | } | |
2405 | ||
f2e0899f DK |
2406 | if (bp->link_vars.link_up && bp->link_vars.line_speed) { |
2407 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
8a1c38d1 | 2408 | |
f2e0899f DK |
2409 | if (cmng_fns != CMNG_FNS_NONE) { |
2410 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2411 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2412 | } else | |
2413 | /* rate shaping and fairness are disabled */ | |
2414 | DP(NETIF_MSG_IFUP, | |
2415 | "single function mode without fairness\n"); | |
34f80b04 | 2416 | } |
9fdc3e95 | 2417 | |
2ae17f66 VZ |
2418 | __bnx2x_link_report(bp); |
2419 | ||
9fdc3e95 DK |
2420 | if (IS_MF(bp)) |
2421 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2422 | } |
a2fbb9ea | 2423 | |
9f6c9258 | 2424 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2425 | { |
2ae17f66 | 2426 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2427 | return; |
a2fbb9ea | 2428 | |
00253a8c DK |
2429 | /* read updated dcb configuration */ |
2430 | bnx2x_dcbx_pmf_update(bp); | |
2431 | ||
c18487ee | 2432 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2433 | |
bb2a0f7a YG |
2434 | if (bp->link_vars.link_up) |
2435 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2436 | else | |
2437 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2438 | ||
c18487ee YR |
2439 | /* indicate link status */ |
2440 | bnx2x_link_report(bp); | |
a2fbb9ea | 2441 | } |
a2fbb9ea | 2442 | |
a3348722 BW |
2443 | static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, |
2444 | u16 vlan_val, u8 allowed_prio) | |
2445 | { | |
2446 | struct bnx2x_func_state_params func_params = {0}; | |
2447 | struct bnx2x_func_afex_update_params *f_update_params = | |
2448 | &func_params.params.afex_update; | |
2449 | ||
2450 | func_params.f_obj = &bp->func_obj; | |
2451 | func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; | |
2452 | ||
2453 | /* no need to wait for RAMROD completion, so don't | |
2454 | * set RAMROD_COMP_WAIT flag | |
2455 | */ | |
2456 | ||
2457 | f_update_params->vif_id = vifid; | |
2458 | f_update_params->afex_default_vlan = vlan_val; | |
2459 | f_update_params->allowed_priorities = allowed_prio; | |
2460 | ||
2461 | /* if ramrod can not be sent, response to MCP immediately */ | |
2462 | if (bnx2x_func_state_change(bp, &func_params) < 0) | |
2463 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
2464 | ||
2465 | return 0; | |
2466 | } | |
2467 | ||
2468 | static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, | |
2469 | u16 vif_index, u8 func_bit_map) | |
2470 | { | |
2471 | struct bnx2x_func_state_params func_params = {0}; | |
2472 | struct bnx2x_func_afex_viflists_params *update_params = | |
2473 | &func_params.params.afex_viflists; | |
2474 | int rc; | |
2475 | u32 drv_msg_code; | |
2476 | ||
2477 | /* validate only LIST_SET and LIST_GET are received from switch */ | |
2478 | if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) | |
2479 | BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", | |
2480 | cmd_type); | |
2481 | ||
2482 | func_params.f_obj = &bp->func_obj; | |
2483 | func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; | |
2484 | ||
2485 | /* set parameters according to cmd_type */ | |
2486 | update_params->afex_vif_list_command = cmd_type; | |
2487 | update_params->vif_list_index = cpu_to_le16(vif_index); | |
2488 | update_params->func_bit_map = | |
2489 | (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; | |
2490 | update_params->func_to_clear = 0; | |
2491 | drv_msg_code = | |
2492 | (cmd_type == VIF_LIST_RULE_GET) ? | |
2493 | DRV_MSG_CODE_AFEX_LISTGET_ACK : | |
2494 | DRV_MSG_CODE_AFEX_LISTSET_ACK; | |
2495 | ||
2496 | /* if ramrod can not be sent, respond to MCP immediately for | |
2497 | * SET and GET requests (other are not triggered from MCP) | |
2498 | */ | |
2499 | rc = bnx2x_func_state_change(bp, &func_params); | |
2500 | if (rc < 0) | |
2501 | bnx2x_fw_command(bp, drv_msg_code, 0); | |
2502 | ||
2503 | return 0; | |
2504 | } | |
2505 | ||
2506 | static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) | |
2507 | { | |
2508 | struct afex_stats afex_stats; | |
2509 | u32 func = BP_ABS_FUNC(bp); | |
2510 | u32 mf_config; | |
2511 | u16 vlan_val; | |
2512 | u32 vlan_prio; | |
2513 | u16 vif_id; | |
2514 | u8 allowed_prio; | |
2515 | u8 vlan_mode; | |
2516 | u32 addr_to_write, vifid, addrs, stats_type, i; | |
2517 | ||
2518 | if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { | |
2519 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2520 | DP(BNX2X_MSG_MCP, | |
2521 | "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); | |
2522 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); | |
2523 | } | |
2524 | ||
2525 | if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { | |
2526 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2527 | addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); | |
2528 | DP(BNX2X_MSG_MCP, | |
2529 | "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", | |
2530 | vifid, addrs); | |
2531 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, | |
2532 | addrs); | |
2533 | } | |
2534 | ||
2535 | if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { | |
2536 | addr_to_write = SHMEM2_RD(bp, | |
2537 | afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); | |
2538 | stats_type = SHMEM2_RD(bp, | |
2539 | afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2540 | ||
2541 | DP(BNX2X_MSG_MCP, | |
2542 | "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", | |
2543 | addr_to_write); | |
2544 | ||
2545 | bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); | |
2546 | ||
2547 | /* write response to scratchpad, for MCP */ | |
2548 | for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) | |
2549 | REG_WR(bp, addr_to_write + i*sizeof(u32), | |
2550 | *(((u32 *)(&afex_stats))+i)); | |
2551 | ||
2552 | /* send ack message to MCP */ | |
2553 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); | |
2554 | } | |
2555 | ||
2556 | if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { | |
2557 | mf_config = MF_CFG_RD(bp, func_mf_config[func].config); | |
2558 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2559 | DP(BNX2X_MSG_MCP, | |
2560 | "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", | |
2561 | mf_config); | |
2562 | ||
2563 | /* if VIF_SET is "enabled" */ | |
2564 | if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { | |
2565 | /* set rate limit directly to internal RAM */ | |
2566 | struct cmng_init_input cmng_input; | |
2567 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2568 | size_t size = sizeof(struct rate_shaping_vars_per_vn); | |
2569 | u32 addr = BAR_XSTRORM_INTMEM + | |
2570 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); | |
2571 | ||
2572 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2573 | ||
2574 | bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); | |
2575 | m_rs_vn.vn_counter.rate = | |
2576 | cmng_input.vnic_max_rate[BP_VN(bp)]; | |
2577 | m_rs_vn.vn_counter.quota = | |
2578 | (m_rs_vn.vn_counter.rate * | |
2579 | RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2580 | ||
2581 | __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); | |
2582 | ||
2583 | /* read relevant values from mf_cfg struct in shmem */ | |
2584 | vif_id = | |
2585 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2586 | FUNC_MF_CFG_E1HOV_TAG_MASK) >> | |
2587 | FUNC_MF_CFG_E1HOV_TAG_SHIFT; | |
2588 | vlan_val = | |
2589 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2590 | FUNC_MF_CFG_AFEX_VLAN_MASK) >> | |
2591 | FUNC_MF_CFG_AFEX_VLAN_SHIFT; | |
2592 | vlan_prio = (mf_config & | |
2593 | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> | |
2594 | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; | |
2595 | vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); | |
2596 | vlan_mode = | |
2597 | (MF_CFG_RD(bp, | |
2598 | func_mf_config[func].afex_config) & | |
2599 | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> | |
2600 | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; | |
2601 | allowed_prio = | |
2602 | (MF_CFG_RD(bp, | |
2603 | func_mf_config[func].afex_config) & | |
2604 | FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> | |
2605 | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; | |
2606 | ||
2607 | /* send ramrod to FW, return in case of failure */ | |
2608 | if (bnx2x_afex_func_update(bp, vif_id, vlan_val, | |
2609 | allowed_prio)) | |
2610 | return; | |
2611 | ||
2612 | bp->afex_def_vlan_tag = vlan_val; | |
2613 | bp->afex_vlan_mode = vlan_mode; | |
2614 | } else { | |
2615 | /* notify link down because BP->flags is disabled */ | |
2616 | bnx2x_link_report(bp); | |
2617 | ||
2618 | /* send INVALID VIF ramrod to FW */ | |
2619 | bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); | |
2620 | ||
2621 | /* Reset the default afex VLAN */ | |
2622 | bp->afex_def_vlan_tag = -1; | |
2623 | } | |
2624 | } | |
2625 | } | |
2626 | ||
34f80b04 EG |
2627 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2628 | { | |
2629 | int port = BP_PORT(bp); | |
2630 | u32 val; | |
2631 | ||
2632 | bp->port.pmf = 1; | |
51c1a580 | 2633 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
34f80b04 | 2634 | |
3deb8167 YR |
2635 | /* |
2636 | * We need the mb() to ensure the ordering between the writing to | |
2637 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2638 | */ | |
2639 | smp_mb(); | |
2640 | ||
2641 | /* queue a periodic task */ | |
2642 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2643 | ||
ef01854e DK |
2644 | bnx2x_dcbx_pmf_update(bp); |
2645 | ||
34f80b04 | 2646 | /* enable nig attention */ |
3395a033 | 2647 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
2648 | if (bp->common.int_block == INT_BLOCK_HC) { |
2649 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2650 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2651 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2652 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2653 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2654 | } | |
bb2a0f7a YG |
2655 | |
2656 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2657 | } |
2658 | ||
c18487ee | 2659 | /* end of Link */ |
a2fbb9ea ET |
2660 | |
2661 | /* slow path */ | |
2662 | ||
2663 | /* | |
2664 | * General service functions | |
2665 | */ | |
2666 | ||
2691d51d | 2667 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 2668 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 2669 | { |
f2e0899f | 2670 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 2671 | u32 seq; |
2691d51d EG |
2672 | u32 rc = 0; |
2673 | u32 cnt = 1; | |
2674 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
2675 | ||
c4ff7cbf | 2676 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 2677 | seq = ++bp->fw_seq; |
f2e0899f DK |
2678 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
2679 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
2680 | ||
754a2f52 DK |
2681 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
2682 | (command | seq), param); | |
2691d51d EG |
2683 | |
2684 | do { | |
2685 | /* let the FW do it's magic ... */ | |
2686 | msleep(delay); | |
2687 | ||
f2e0899f | 2688 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 2689 | |
c4ff7cbf EG |
2690 | /* Give the FW up to 5 second (500*10ms) */ |
2691 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
2692 | |
2693 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
2694 | cnt*delay, rc, seq); | |
2695 | ||
2696 | /* is this a reply to our command? */ | |
2697 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
2698 | rc &= FW_MSG_CODE_MASK; | |
2699 | else { | |
2700 | /* FW BUG! */ | |
2701 | BNX2X_ERR("FW failed to respond!\n"); | |
2702 | bnx2x_fw_dump(bp); | |
2703 | rc = 0; | |
2704 | } | |
c4ff7cbf | 2705 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
2706 | |
2707 | return rc; | |
2708 | } | |
2709 | ||
ec6ba945 | 2710 | |
1191cb83 ED |
2711 | static void storm_memset_func_cfg(struct bnx2x *bp, |
2712 | struct tstorm_eth_function_common_config *tcfg, | |
2713 | u16 abs_fid) | |
2714 | { | |
2715 | size_t size = sizeof(struct tstorm_eth_function_common_config); | |
2716 | ||
2717 | u32 addr = BAR_TSTRORM_INTMEM + | |
2718 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); | |
2719 | ||
2720 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); | |
2721 | } | |
2722 | ||
619c5cb6 VZ |
2723 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
2724 | { | |
2725 | if (CHIP_IS_E1x(bp)) { | |
2726 | struct tstorm_eth_function_common_config tcfg = {0}; | |
2727 | ||
2728 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
2729 | } | |
2730 | ||
2731 | /* Enable the function in the FW */ | |
2732 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
2733 | storm_memset_func_en(bp, p->func_id, 1); | |
2734 | ||
2735 | /* spq */ | |
2736 | if (p->func_flgs & FUNC_FLG_SPQ) { | |
2737 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); | |
2738 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
2739 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
2740 | } | |
2741 | } | |
2742 | ||
6383c0b3 AE |
2743 | /** |
2744 | * bnx2x_get_tx_only_flags - Return common flags | |
2745 | * | |
2746 | * @bp device handle | |
2747 | * @fp queue handle | |
2748 | * @zero_stats TRUE if statistics zeroing is needed | |
2749 | * | |
2750 | * Return the flags that are common for the Tx-only and not normal connections. | |
2751 | */ | |
1191cb83 ED |
2752 | static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, |
2753 | struct bnx2x_fastpath *fp, | |
2754 | bool zero_stats) | |
28912902 | 2755 | { |
619c5cb6 VZ |
2756 | unsigned long flags = 0; |
2757 | ||
2758 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
2759 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 2760 | |
6383c0b3 AE |
2761 | /* tx only connections collect statistics (on the same index as the |
2762 | * parent connection). The statistics are zeroed when the parent | |
2763 | * connection is initialized. | |
2764 | */ | |
50f0a562 BW |
2765 | |
2766 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
2767 | if (zero_stats) | |
2768 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
2769 | ||
6383c0b3 AE |
2770 | |
2771 | return flags; | |
2772 | } | |
2773 | ||
1191cb83 ED |
2774 | static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, |
2775 | struct bnx2x_fastpath *fp, | |
2776 | bool leading) | |
6383c0b3 AE |
2777 | { |
2778 | unsigned long flags = 0; | |
2779 | ||
619c5cb6 VZ |
2780 | /* calculate other queue flags */ |
2781 | if (IS_MF_SD(bp)) | |
2782 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 2783 | |
a3348722 | 2784 | if (IS_FCOE_FP(fp)) { |
619c5cb6 | 2785 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); |
a3348722 BW |
2786 | /* For FCoE - force usage of default priority (for afex) */ |
2787 | __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); | |
2788 | } | |
523224a3 | 2789 | |
f5219d8e | 2790 | if (!fp->disable_tpa) { |
619c5cb6 | 2791 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e | 2792 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
621b4d66 DK |
2793 | if (fp->mode == TPA_MODE_GRO) |
2794 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); | |
f5219d8e | 2795 | } |
619c5cb6 | 2796 | |
619c5cb6 VZ |
2797 | if (leading) { |
2798 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
2799 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
2800 | } | |
523224a3 | 2801 | |
619c5cb6 VZ |
2802 | /* Always set HW VLAN stripping */ |
2803 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 2804 | |
a3348722 BW |
2805 | /* configure silent vlan removal */ |
2806 | if (IS_MF_AFEX(bp)) | |
2807 | __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); | |
2808 | ||
6383c0b3 AE |
2809 | |
2810 | return flags | bnx2x_get_common_flags(bp, fp, true); | |
523224a3 DK |
2811 | } |
2812 | ||
619c5cb6 | 2813 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
2814 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
2815 | u8 cos) | |
619c5cb6 VZ |
2816 | { |
2817 | gen_init->stat_id = bnx2x_stats_id(fp); | |
2818 | gen_init->spcl_id = fp->cl_id; | |
2819 | ||
2820 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
2821 | if (IS_FCOE_FP(fp)) | |
2822 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
2823 | else | |
2824 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
2825 | |
2826 | gen_init->cos = cos; | |
619c5cb6 VZ |
2827 | } |
2828 | ||
2829 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 2830 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 2831 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 2832 | { |
619c5cb6 | 2833 | u8 max_sge = 0; |
523224a3 DK |
2834 | u16 sge_sz = 0; |
2835 | u16 tpa_agg_size = 0; | |
2836 | ||
523224a3 | 2837 | if (!fp->disable_tpa) { |
dfacf138 DK |
2838 | pause->sge_th_lo = SGE_TH_LO(bp); |
2839 | pause->sge_th_hi = SGE_TH_HI(bp); | |
2840 | ||
2841 | /* validate SGE ring has enough to cross high threshold */ | |
2842 | WARN_ON(bp->dropless_fc && | |
2843 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
2844 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
2845 | ||
523224a3 DK |
2846 | tpa_agg_size = min_t(u32, |
2847 | (min_t(u32, 8, MAX_SKB_FRAGS) * | |
2848 | SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); | |
2849 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> | |
2850 | SGE_PAGE_SHIFT; | |
2851 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
2852 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
2853 | sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, | |
2854 | 0xffff); | |
2855 | } | |
2856 | ||
2857 | /* pause - not for e1 */ | |
2858 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
2859 | pause->bd_th_lo = BD_TH_LO(bp); |
2860 | pause->bd_th_hi = BD_TH_HI(bp); | |
2861 | ||
2862 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
2863 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
2864 | /* | |
2865 | * validate that rings have enough entries to cross | |
2866 | * high thresholds | |
2867 | */ | |
2868 | WARN_ON(bp->dropless_fc && | |
2869 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
2870 | bp->rx_ring_size); | |
2871 | WARN_ON(bp->dropless_fc && | |
2872 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
2873 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 2874 | |
523224a3 DK |
2875 | pause->pri_map = 1; |
2876 | } | |
2877 | ||
2878 | /* rxq setup */ | |
523224a3 DK |
2879 | rxq_init->dscr_map = fp->rx_desc_mapping; |
2880 | rxq_init->sge_map = fp->rx_sge_mapping; | |
2881 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
2882 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 2883 | |
619c5cb6 VZ |
2884 | /* This should be a maximum number of data bytes that may be |
2885 | * placed on the BD (not including paddings). | |
2886 | */ | |
e52fcb24 ED |
2887 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
2888 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; | |
a8c94b91 | 2889 | |
523224a3 | 2890 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
2891 | rxq_init->tpa_agg_sz = tpa_agg_size; |
2892 | rxq_init->sge_buf_sz = sge_sz; | |
2893 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 | 2894 | rxq_init->rss_engine_id = BP_FUNC(bp); |
259afa1f | 2895 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
619c5cb6 VZ |
2896 | |
2897 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
2898 | * | |
2899 | * For PF Clients it should be the maximum avaliable number. | |
2900 | * VF driver(s) may want to define it to a smaller value. | |
2901 | */ | |
dfacf138 | 2902 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 2903 | |
523224a3 DK |
2904 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
2905 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
2906 | ||
ec6ba945 VZ |
2907 | if (IS_FCOE_FP(fp)) |
2908 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
2909 | else | |
6383c0b3 | 2910 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
a3348722 BW |
2911 | /* configure silent vlan removal |
2912 | * if multi function mode is afex, then mask default vlan | |
2913 | */ | |
2914 | if (IS_MF_AFEX(bp)) { | |
2915 | rxq_init->silent_removal_value = bp->afex_def_vlan_tag; | |
2916 | rxq_init->silent_removal_mask = VLAN_VID_MASK; | |
2917 | } | |
523224a3 DK |
2918 | } |
2919 | ||
619c5cb6 | 2920 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
2921 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
2922 | u8 cos) | |
523224a3 | 2923 | { |
65565884 | 2924 | txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; |
6383c0b3 | 2925 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; |
523224a3 DK |
2926 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
2927 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 2928 | |
619c5cb6 VZ |
2929 | /* |
2930 | * set the tss leading client id for TX classfication == | |
2931 | * leading RSS client id | |
2932 | */ | |
2933 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
2934 | ||
ec6ba945 VZ |
2935 | if (IS_FCOE_FP(fp)) { |
2936 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
2937 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
2938 | } | |
523224a3 DK |
2939 | } |
2940 | ||
8d96286a | 2941 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
2942 | { |
2943 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 DK |
2944 | struct event_ring_data eq_data = { {0} }; |
2945 | u16 flags; | |
2946 | ||
619c5cb6 | 2947 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2948 | /* reset IGU PF statistics: MSIX + ATTN */ |
2949 | /* PF */ | |
2950 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2951 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2952 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2953 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2954 | /* ATTN */ | |
2955 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2956 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2957 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
2958 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2959 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2960 | } | |
2961 | ||
523224a3 DK |
2962 | /* function setup flags */ |
2963 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | |
2964 | ||
619c5cb6 VZ |
2965 | /* This flag is relevant for E1x only. |
2966 | * E2 doesn't have a TPA configuration in a function level. | |
523224a3 | 2967 | */ |
619c5cb6 | 2968 | flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; |
523224a3 DK |
2969 | |
2970 | func_init.func_flgs = flags; | |
2971 | func_init.pf_id = BP_FUNC(bp); | |
2972 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
2973 | func_init.spq_map = bp->spq_mapping; |
2974 | func_init.spq_prod = bp->spq_prod_idx; | |
2975 | ||
2976 | bnx2x_func_init(bp, &func_init); | |
2977 | ||
2978 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
2979 | ||
2980 | /* | |
619c5cb6 VZ |
2981 | * Congestion management values depend on the link rate |
2982 | * There is no active link so initial link rate is set to 10 Gbps. | |
2983 | * When the link comes up The congestion management values are | |
2984 | * re-calculated according to the actual link rate. | |
2985 | */ | |
523224a3 DK |
2986 | bp->link_vars.line_speed = SPEED_10000; |
2987 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
2988 | ||
2989 | /* Only the PMF sets the HW */ | |
2990 | if (bp->port.pmf) | |
2991 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2992 | ||
523224a3 DK |
2993 | /* init Event Queue */ |
2994 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); | |
2995 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
2996 | eq_data.producer = bp->eq_prod; | |
2997 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
2998 | eq_data.sb_id = DEF_SB_ID; | |
2999 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
3000 | } | |
3001 | ||
3002 | ||
3003 | static void bnx2x_e1h_disable(struct bnx2x *bp) | |
3004 | { | |
3005 | int port = BP_PORT(bp); | |
3006 | ||
619c5cb6 | 3007 | bnx2x_tx_disable(bp); |
523224a3 DK |
3008 | |
3009 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
3010 | } |
3011 | ||
3012 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
3013 | { | |
3014 | int port = BP_PORT(bp); | |
3015 | ||
3016 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); | |
3017 | ||
3018 | /* Tx queue should be only reenabled */ | |
3019 | netif_tx_wake_all_queues(bp->dev); | |
3020 | ||
3021 | /* | |
3022 | * Should not call netif_carrier_on since it will be called if the link | |
3023 | * is up when checking for link state | |
3024 | */ | |
3025 | } | |
3026 | ||
1d187b34 BW |
3027 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
3028 | ||
3029 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) | |
3030 | { | |
3031 | struct eth_stats_info *ether_stat = | |
3032 | &bp->slowpath->drv_info_to_mcp.ether_stat; | |
3033 | ||
3034 | /* leave last char as NULL */ | |
3035 | memcpy(ether_stat->version, DRV_MODULE_VERSION, | |
3036 | ETH_STAT_INFO_VERSION_LEN - 1); | |
3037 | ||
15192a8c BW |
3038 | bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj, |
3039 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | |
3040 | ether_stat->mac_local); | |
1d187b34 BW |
3041 | |
3042 | ether_stat->mtu_size = bp->dev->mtu; | |
3043 | ||
3044 | if (bp->dev->features & NETIF_F_RXCSUM) | |
3045 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | |
3046 | if (bp->dev->features & NETIF_F_TSO) | |
3047 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; | |
3048 | ether_stat->feature_flags |= bp->common.boot_mode; | |
3049 | ||
3050 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; | |
3051 | ||
3052 | ether_stat->txq_size = bp->tx_ring_size; | |
3053 | ether_stat->rxq_size = bp->rx_ring_size; | |
3054 | } | |
3055 | ||
3056 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) | |
3057 | { | |
f2fd5c34 | 3058 | #ifdef BCM_CNIC |
1d187b34 BW |
3059 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; |
3060 | struct fcoe_stats_info *fcoe_stat = | |
3061 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; | |
3062 | ||
3063 | memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN); | |
3064 | ||
3065 | fcoe_stat->qos_priority = | |
3066 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | |
3067 | ||
3068 | /* insert FCoE stats from ramrod response */ | |
3069 | if (!NO_FCOE(bp)) { | |
3070 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = | |
65565884 | 3071 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3072 | tstorm_queue_statistics; |
3073 | ||
3074 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = | |
65565884 | 3075 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3076 | xstorm_queue_statistics; |
3077 | ||
3078 | struct fcoe_statistics_params *fw_fcoe_stat = | |
3079 | &bp->fw_stats_data->fcoe; | |
3080 | ||
3081 | ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, | |
3082 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); | |
3083 | ||
3084 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3085 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, | |
3086 | fcoe_stat->rx_bytes_lo, | |
3087 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); | |
3088 | ||
3089 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3090 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, | |
3091 | fcoe_stat->rx_bytes_lo, | |
3092 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); | |
3093 | ||
3094 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3095 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, | |
3096 | fcoe_stat->rx_bytes_lo, | |
3097 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); | |
3098 | ||
3099 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3100 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); | |
3101 | ||
3102 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3103 | fcoe_q_tstorm_stats->rcv_ucast_pkts); | |
3104 | ||
3105 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3106 | fcoe_q_tstorm_stats->rcv_bcast_pkts); | |
3107 | ||
3108 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
f33f1fcc | 3109 | fcoe_q_tstorm_stats->rcv_mcast_pkts); |
1d187b34 BW |
3110 | |
3111 | ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, | |
3112 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); | |
3113 | ||
3114 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3115 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, | |
3116 | fcoe_stat->tx_bytes_lo, | |
3117 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); | |
3118 | ||
3119 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3120 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, | |
3121 | fcoe_stat->tx_bytes_lo, | |
3122 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); | |
3123 | ||
3124 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3125 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, | |
3126 | fcoe_stat->tx_bytes_lo, | |
3127 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); | |
3128 | ||
3129 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3130 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); | |
3131 | ||
3132 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3133 | fcoe_q_xstorm_stats->ucast_pkts_sent); | |
3134 | ||
3135 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3136 | fcoe_q_xstorm_stats->bcast_pkts_sent); | |
3137 | ||
3138 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3139 | fcoe_q_xstorm_stats->mcast_pkts_sent); | |
3140 | } | |
3141 | ||
1d187b34 BW |
3142 | /* ask L5 driver to add data to the struct */ |
3143 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); | |
3144 | #endif | |
3145 | } | |
3146 | ||
3147 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) | |
3148 | { | |
f2fd5c34 | 3149 | #ifdef BCM_CNIC |
1d187b34 BW |
3150 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; |
3151 | struct iscsi_stats_info *iscsi_stat = | |
3152 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; | |
3153 | ||
3154 | memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); | |
3155 | ||
3156 | iscsi_stat->qos_priority = | |
3157 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | |
3158 | ||
1d187b34 BW |
3159 | /* ask L5 driver to add data to the struct */ |
3160 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); | |
3161 | #endif | |
3162 | } | |
3163 | ||
0793f83f DK |
3164 | /* called due to MCP event (on pmf): |
3165 | * reread new bandwidth configuration | |
3166 | * configure FW | |
3167 | * notify others function about the change | |
3168 | */ | |
1191cb83 | 3169 | static void bnx2x_config_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3170 | { |
3171 | if (bp->link_vars.link_up) { | |
3172 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
3173 | bnx2x_link_sync_notify(bp); | |
3174 | } | |
3175 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3176 | } | |
3177 | ||
1191cb83 | 3178 | static void bnx2x_set_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3179 | { |
3180 | bnx2x_config_mf_bw(bp); | |
3181 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
3182 | } | |
3183 | ||
c8c60d88 YM |
3184 | static void bnx2x_handle_eee_event(struct bnx2x *bp) |
3185 | { | |
3186 | DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); | |
3187 | bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); | |
3188 | } | |
3189 | ||
1d187b34 BW |
3190 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
3191 | { | |
3192 | enum drv_info_opcode op_code; | |
3193 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); | |
3194 | ||
3195 | /* if drv_info version supported by MFW doesn't match - send NACK */ | |
3196 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { | |
3197 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3198 | return; | |
3199 | } | |
3200 | ||
3201 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> | |
3202 | DRV_INFO_CONTROL_OP_CODE_SHIFT; | |
3203 | ||
3204 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3205 | sizeof(union drv_info_to_mcp)); | |
3206 | ||
3207 | switch (op_code) { | |
3208 | case ETH_STATS_OPCODE: | |
3209 | bnx2x_drv_info_ether_stat(bp); | |
3210 | break; | |
3211 | case FCOE_STATS_OPCODE: | |
3212 | bnx2x_drv_info_fcoe_stat(bp); | |
3213 | break; | |
3214 | case ISCSI_STATS_OPCODE: | |
3215 | bnx2x_drv_info_iscsi_stat(bp); | |
3216 | break; | |
3217 | default: | |
3218 | /* if op code isn't supported - send NACK */ | |
3219 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3220 | return; | |
3221 | } | |
3222 | ||
3223 | /* if we got drv_info attn from MFW then these fields are defined in | |
3224 | * shmem2 for sure | |
3225 | */ | |
3226 | SHMEM2_WR(bp, drv_info_host_addr_lo, | |
3227 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3228 | SHMEM2_WR(bp, drv_info_host_addr_hi, | |
3229 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3230 | ||
3231 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); | |
3232 | } | |
3233 | ||
523224a3 DK |
3234 | static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) |
3235 | { | |
3236 | DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); | |
3237 | ||
3238 | if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { | |
3239 | ||
3240 | /* | |
3241 | * This is the only place besides the function initialization | |
3242 | * where the bp->flags can change so it is done without any | |
3243 | * locks | |
3244 | */ | |
f2e0899f | 3245 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
51c1a580 | 3246 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
523224a3 DK |
3247 | bp->flags |= MF_FUNC_DIS; |
3248 | ||
3249 | bnx2x_e1h_disable(bp); | |
3250 | } else { | |
51c1a580 | 3251 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
523224a3 DK |
3252 | bp->flags &= ~MF_FUNC_DIS; |
3253 | ||
3254 | bnx2x_e1h_enable(bp); | |
3255 | } | |
3256 | dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; | |
3257 | } | |
3258 | if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { | |
0793f83f | 3259 | bnx2x_config_mf_bw(bp); |
523224a3 DK |
3260 | dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; |
3261 | } | |
3262 | ||
3263 | /* Report results to MCP */ | |
3264 | if (dcc_event) | |
3265 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); | |
3266 | else | |
3267 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); | |
3268 | } | |
3269 | ||
3270 | /* must be called under the spq lock */ | |
1191cb83 | 3271 | static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) |
523224a3 DK |
3272 | { |
3273 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3274 | ||
3275 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3276 | bp->spq_prod_bd = bp->spq; | |
3277 | bp->spq_prod_idx = 0; | |
51c1a580 | 3278 | DP(BNX2X_MSG_SP, "end of spq\n"); |
523224a3 DK |
3279 | } else { |
3280 | bp->spq_prod_bd++; | |
3281 | bp->spq_prod_idx++; | |
3282 | } | |
3283 | return next_spe; | |
3284 | } | |
3285 | ||
3286 | /* must be called under the spq lock */ | |
1191cb83 | 3287 | static void bnx2x_sp_prod_update(struct bnx2x *bp) |
28912902 MC |
3288 | { |
3289 | int func = BP_FUNC(bp); | |
3290 | ||
53e51e2f VZ |
3291 | /* |
3292 | * Make sure that BD data is updated before writing the producer: | |
3293 | * BD data is written to the memory, the producer is read from the | |
3294 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3295 | */ | |
3296 | mb(); | |
28912902 | 3297 | |
523224a3 | 3298 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3299 | bp->spq_prod_idx); |
28912902 MC |
3300 | mmiowb(); |
3301 | } | |
3302 | ||
619c5cb6 VZ |
3303 | /** |
3304 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3305 | * | |
3306 | * @cmd: command to check | |
3307 | * @cmd_type: command type | |
3308 | */ | |
1191cb83 | 3309 | static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) |
619c5cb6 VZ |
3310 | { |
3311 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3312 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3313 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3314 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3315 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3316 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3317 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3318 | return true; | |
3319 | else | |
3320 | return false; | |
3321 | ||
3322 | } | |
3323 | ||
3324 | ||
3325 | /** | |
3326 | * bnx2x_sp_post - place a single command on an SP ring | |
3327 | * | |
3328 | * @bp: driver handle | |
3329 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3330 | * @cid: SW CID the command is related to | |
3331 | * @data_hi: command private data address (high 32 bits) | |
3332 | * @data_lo: command private data address (low 32 bits) | |
3333 | * @cmd_type: command type (e.g. NONE, ETH) | |
3334 | * | |
3335 | * SP data is handled as if it's always an address pair, thus data fields are | |
3336 | * not swapped to little endian in upper functions. Instead this function swaps | |
3337 | * data as if it's two u32 fields. | |
3338 | */ | |
9f6c9258 | 3339 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3340 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3341 | { |
28912902 | 3342 | struct eth_spe *spe; |
523224a3 | 3343 | u16 type; |
619c5cb6 | 3344 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3345 | |
a2fbb9ea | 3346 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
3347 | if (unlikely(bp->panic)) { |
3348 | BNX2X_ERR("Can't post SP when there is panic\n"); | |
a2fbb9ea | 3349 | return -EIO; |
51c1a580 | 3350 | } |
a2fbb9ea ET |
3351 | #endif |
3352 | ||
34f80b04 | 3353 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3354 | |
6e30dd4e VZ |
3355 | if (common) { |
3356 | if (!atomic_read(&bp->eq_spq_left)) { | |
3357 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3358 | spin_unlock_bh(&bp->spq_lock); | |
3359 | bnx2x_panic(); | |
3360 | return -EBUSY; | |
3361 | } | |
3362 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3363 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3364 | spin_unlock_bh(&bp->spq_lock); | |
3365 | bnx2x_panic(); | |
3366 | return -EBUSY; | |
a2fbb9ea | 3367 | } |
f1410647 | 3368 | |
28912902 MC |
3369 | spe = bnx2x_sp_get_next(bp); |
3370 | ||
a2fbb9ea | 3371 | /* CID needs port number to be encoded int it */ |
28912902 | 3372 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3373 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3374 | HW_CID(bp, cid)); | |
523224a3 | 3375 | |
619c5cb6 | 3376 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; |
a2fbb9ea | 3377 | |
523224a3 DK |
3378 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & |
3379 | SPE_HDR_FUNCTION_ID); | |
a2fbb9ea | 3380 | |
523224a3 DK |
3381 | spe->hdr.type = cpu_to_le16(type); |
3382 | ||
3383 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3384 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3385 | ||
d6cae238 VZ |
3386 | /* |
3387 | * It's ok if the actual decrement is issued towards the memory | |
3388 | * somewhere between the spin_lock and spin_unlock. Thus no | |
3389 | * more explict memory barrier is needed. | |
3390 | */ | |
3391 | if (common) | |
3392 | atomic_dec(&bp->eq_spq_left); | |
3393 | else | |
3394 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3395 | |
a2fbb9ea | 3396 | |
51c1a580 MS |
3397 | DP(BNX2X_MSG_SP, |
3398 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3399 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3400 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3401 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3402 | HW_CID(bp, cid), data_hi, data_lo, type, |
3403 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3404 | |
28912902 | 3405 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3406 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3407 | return 0; |
3408 | } | |
3409 | ||
3410 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3411 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3412 | { |
72fd0718 | 3413 | u32 j, val; |
34f80b04 | 3414 | int rc = 0; |
a2fbb9ea ET |
3415 | |
3416 | might_sleep(); | |
72fd0718 | 3417 | for (j = 0; j < 1000; j++) { |
a2fbb9ea ET |
3418 | val = (1UL << 31); |
3419 | REG_WR(bp, GRCBASE_MCP + 0x9c, val); | |
3420 | val = REG_RD(bp, GRCBASE_MCP + 0x9c); | |
3421 | if (val & (1L << 31)) | |
3422 | break; | |
3423 | ||
3424 | msleep(5); | |
3425 | } | |
a2fbb9ea | 3426 | if (!(val & (1L << 31))) { |
19680c48 | 3427 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3428 | rc = -EBUSY; |
3429 | } | |
3430 | ||
3431 | return rc; | |
3432 | } | |
3433 | ||
4a37fb66 YG |
3434 | /* release split MCP access lock register */ |
3435 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3436 | { |
72fd0718 | 3437 | REG_WR(bp, GRCBASE_MCP + 0x9c, 0); |
a2fbb9ea ET |
3438 | } |
3439 | ||
523224a3 DK |
3440 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3441 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3442 | ||
1191cb83 | 3443 | static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
a2fbb9ea | 3444 | { |
523224a3 | 3445 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3446 | u16 rc = 0; |
3447 | ||
3448 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3449 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3450 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3451 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3452 | } |
523224a3 DK |
3453 | |
3454 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3455 | bp->def_idx = def_sb->sp_sb.running_index; | |
3456 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3457 | } |
523224a3 DK |
3458 | |
3459 | /* Do not reorder: indecies reading should complete before handling */ | |
3460 | barrier(); | |
a2fbb9ea ET |
3461 | return rc; |
3462 | } | |
3463 | ||
3464 | /* | |
3465 | * slow path service functions | |
3466 | */ | |
3467 | ||
3468 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3469 | { | |
34f80b04 | 3470 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3471 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3472 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3473 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3474 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3475 | u32 aeu_mask; |
87942b46 | 3476 | u32 nig_mask = 0; |
f2e0899f | 3477 | u32 reg_addr; |
a2fbb9ea | 3478 | |
a2fbb9ea ET |
3479 | if (bp->attn_state & asserted) |
3480 | BNX2X_ERR("IGU ERROR\n"); | |
3481 | ||
3fcaf2e5 EG |
3482 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
3483 | aeu_mask = REG_RD(bp, aeu_addr); | |
3484 | ||
a2fbb9ea | 3485 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 3486 | aeu_mask, asserted); |
72fd0718 | 3487 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 3488 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 3489 | |
3fcaf2e5 EG |
3490 | REG_WR(bp, aeu_addr, aeu_mask); |
3491 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 3492 | |
3fcaf2e5 | 3493 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 3494 | bp->attn_state |= asserted; |
3fcaf2e5 | 3495 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
3496 | |
3497 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
3498 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 3499 | |
a5e9a7cf EG |
3500 | bnx2x_acquire_phy_lock(bp); |
3501 | ||
877e9aa4 | 3502 | /* save nig interrupt mask */ |
87942b46 | 3503 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 3504 | |
361c391e YR |
3505 | /* If nig_mask is not set, no need to call the update |
3506 | * function. | |
3507 | */ | |
3508 | if (nig_mask) { | |
3509 | REG_WR(bp, nig_int_mask_addr, 0); | |
3510 | ||
3511 | bnx2x_link_attn(bp); | |
3512 | } | |
a2fbb9ea ET |
3513 | |
3514 | /* handle unicore attn? */ | |
3515 | } | |
3516 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
3517 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
3518 | ||
3519 | if (asserted & GPIO_2_FUNC) | |
3520 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
3521 | ||
3522 | if (asserted & GPIO_3_FUNC) | |
3523 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
3524 | ||
3525 | if (asserted & GPIO_4_FUNC) | |
3526 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
3527 | ||
3528 | if (port == 0) { | |
3529 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
3530 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
3531 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
3532 | } | |
3533 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
3534 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
3535 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
3536 | } | |
3537 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
3538 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
3539 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
3540 | } | |
3541 | } else { | |
3542 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
3543 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
3544 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
3545 | } | |
3546 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
3547 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
3548 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
3549 | } | |
3550 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
3551 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
3552 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
3553 | } | |
3554 | } | |
3555 | ||
3556 | } /* if hardwired */ | |
3557 | ||
f2e0899f DK |
3558 | if (bp->common.int_block == INT_BLOCK_HC) |
3559 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
3560 | COMMAND_REG_ATTN_BITS_SET); | |
3561 | else | |
3562 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
3563 | ||
3564 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
3565 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
3566 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
3567 | |
3568 | /* now set back the mask */ | |
a5e9a7cf | 3569 | if (asserted & ATTN_NIG_FOR_FUNC) { |
87942b46 | 3570 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
3571 | bnx2x_release_phy_lock(bp); |
3572 | } | |
a2fbb9ea ET |
3573 | } |
3574 | ||
1191cb83 | 3575 | static void bnx2x_fan_failure(struct bnx2x *bp) |
fd4ef40d EG |
3576 | { |
3577 | int port = BP_PORT(bp); | |
b7737c9b | 3578 | u32 ext_phy_config; |
fd4ef40d | 3579 | /* mark the failure */ |
b7737c9b YR |
3580 | ext_phy_config = |
3581 | SHMEM_RD(bp, | |
3582 | dev_info.port_hw_config[port].external_phy_config); | |
3583 | ||
3584 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
3585 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 3586 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 3587 | ext_phy_config); |
fd4ef40d EG |
3588 | |
3589 | /* log the failure */ | |
51c1a580 MS |
3590 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
3591 | "Please contact OEM Support for assistance\n"); | |
8304859a AE |
3592 | |
3593 | /* | |
3594 | * Scheudle device reset (unload) | |
3595 | * This is due to some boards consuming sufficient power when driver is | |
3596 | * up to overheat if fan fails. | |
3597 | */ | |
3598 | smp_mb__before_clear_bit(); | |
3599 | set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); | |
3600 | smp_mb__after_clear_bit(); | |
3601 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
3602 | ||
fd4ef40d | 3603 | } |
ab6ad5a4 | 3604 | |
1191cb83 | 3605 | static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 3606 | { |
34f80b04 | 3607 | int port = BP_PORT(bp); |
877e9aa4 | 3608 | int reg_offset; |
d90d96ba | 3609 | u32 val; |
877e9aa4 | 3610 | |
34f80b04 EG |
3611 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
3612 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 3613 | |
34f80b04 | 3614 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
3615 | |
3616 | val = REG_RD(bp, reg_offset); | |
3617 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
3618 | REG_WR(bp, reg_offset, val); | |
3619 | ||
3620 | BNX2X_ERR("SPIO5 hw attention\n"); | |
3621 | ||
fd4ef40d | 3622 | /* Fan failure attention */ |
d90d96ba | 3623 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 3624 | bnx2x_fan_failure(bp); |
877e9aa4 | 3625 | } |
34f80b04 | 3626 | |
3deb8167 | 3627 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
3628 | bnx2x_acquire_phy_lock(bp); |
3629 | bnx2x_handle_module_detect_int(&bp->link_params); | |
3630 | bnx2x_release_phy_lock(bp); | |
3631 | } | |
3632 | ||
34f80b04 EG |
3633 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
3634 | ||
3635 | val = REG_RD(bp, reg_offset); | |
3636 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
3637 | REG_WR(bp, reg_offset, val); | |
3638 | ||
3639 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 3640 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
3641 | bnx2x_panic(); |
3642 | } | |
877e9aa4 ET |
3643 | } |
3644 | ||
1191cb83 | 3645 | static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
3646 | { |
3647 | u32 val; | |
3648 | ||
0626b899 | 3649 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
3650 | |
3651 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
3652 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
3653 | /* DORQ discard attention */ | |
3654 | if (val & 0x2) | |
3655 | BNX2X_ERR("FATAL error from DORQ\n"); | |
3656 | } | |
34f80b04 EG |
3657 | |
3658 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
3659 | ||
3660 | int port = BP_PORT(bp); | |
3661 | int reg_offset; | |
3662 | ||
3663 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
3664 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
3665 | ||
3666 | val = REG_RD(bp, reg_offset); | |
3667 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
3668 | REG_WR(bp, reg_offset, val); | |
3669 | ||
3670 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 3671 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
3672 | bnx2x_panic(); |
3673 | } | |
877e9aa4 ET |
3674 | } |
3675 | ||
1191cb83 | 3676 | static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
3677 | { |
3678 | u32 val; | |
3679 | ||
3680 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
3681 | ||
3682 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
3683 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
3684 | /* CFC error attention */ | |
3685 | if (val & 0x2) | |
3686 | BNX2X_ERR("FATAL error from CFC\n"); | |
3687 | } | |
3688 | ||
3689 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 3690 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 3691 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
3692 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
3693 | if (val & 0x18000) | |
3694 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
3695 | |
3696 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
3697 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
3698 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
3699 | } | |
877e9aa4 | 3700 | } |
34f80b04 EG |
3701 | |
3702 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
3703 | ||
3704 | int port = BP_PORT(bp); | |
3705 | int reg_offset; | |
3706 | ||
3707 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
3708 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
3709 | ||
3710 | val = REG_RD(bp, reg_offset); | |
3711 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
3712 | REG_WR(bp, reg_offset, val); | |
3713 | ||
3714 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 3715 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
3716 | bnx2x_panic(); |
3717 | } | |
877e9aa4 ET |
3718 | } |
3719 | ||
1191cb83 | 3720 | static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) |
877e9aa4 | 3721 | { |
34f80b04 EG |
3722 | u32 val; |
3723 | ||
877e9aa4 ET |
3724 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
3725 | ||
34f80b04 EG |
3726 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
3727 | int func = BP_FUNC(bp); | |
3728 | ||
3729 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
a3348722 | 3730 | bnx2x_read_mf_cfg(bp); |
f2e0899f DK |
3731 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
3732 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
3733 | val = SHMEM_RD(bp, | |
3734 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
2691d51d EG |
3735 | if (val & DRV_STATUS_DCC_EVENT_MASK) |
3736 | bnx2x_dcc_event(bp, | |
3737 | (val & DRV_STATUS_DCC_EVENT_MASK)); | |
0793f83f DK |
3738 | |
3739 | if (val & DRV_STATUS_SET_MF_BW) | |
3740 | bnx2x_set_mf_bw(bp); | |
3741 | ||
1d187b34 BW |
3742 | if (val & DRV_STATUS_DRV_INFO_REQ) |
3743 | bnx2x_handle_drv_info_req(bp); | |
2691d51d | 3744 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
3745 | bnx2x_pmf_update(bp); |
3746 | ||
e4901dde | 3747 | if (bp->port.pmf && |
785b9b1a SR |
3748 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
3749 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
3750 | /* start dcbx state machine */ |
3751 | bnx2x_dcbx_set_params(bp, | |
3752 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
a3348722 BW |
3753 | if (val & DRV_STATUS_AFEX_EVENT_MASK) |
3754 | bnx2x_handle_afex_cmd(bp, | |
3755 | val & DRV_STATUS_AFEX_EVENT_MASK); | |
c8c60d88 YM |
3756 | if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) |
3757 | bnx2x_handle_eee_event(bp); | |
3deb8167 YR |
3758 | if (bp->link_vars.periodic_flags & |
3759 | PERIODIC_FLAGS_LINK_EVENT) { | |
3760 | /* sync with link */ | |
3761 | bnx2x_acquire_phy_lock(bp); | |
3762 | bp->link_vars.periodic_flags &= | |
3763 | ~PERIODIC_FLAGS_LINK_EVENT; | |
3764 | bnx2x_release_phy_lock(bp); | |
3765 | if (IS_MF(bp)) | |
3766 | bnx2x_link_sync_notify(bp); | |
3767 | bnx2x_link_report(bp); | |
3768 | } | |
3769 | /* Always call it here: bnx2x_link_report() will | |
3770 | * prevent the link indication duplication. | |
3771 | */ | |
3772 | bnx2x__link_status_update(bp); | |
34f80b04 | 3773 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
3774 | |
3775 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 3776 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
3777 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
3778 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
3779 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
3780 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
3781 | bnx2x_panic(); | |
3782 | ||
3783 | } else if (attn & BNX2X_MCP_ASSERT) { | |
3784 | ||
3785 | BNX2X_ERR("MCP assert!\n"); | |
3786 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 3787 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
3788 | |
3789 | } else | |
3790 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
3791 | } | |
3792 | ||
3793 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
3794 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
3795 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
3796 | val = CHIP_IS_E1(bp) ? 0 : |
3797 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
3798 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
3799 | } | |
3800 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
3801 | val = CHIP_IS_E1(bp) ? 0 : |
3802 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
3803 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
3804 | } | |
877e9aa4 | 3805 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
3806 | } |
3807 | } | |
3808 | ||
c9ee9206 VZ |
3809 | /* |
3810 | * Bits map: | |
3811 | * 0-7 - Engine0 load counter. | |
3812 | * 8-15 - Engine1 load counter. | |
3813 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
3814 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
3815 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
3816 | * on the engine | |
3817 | * 19 - Engine1 ONE_IS_LOADED. | |
3818 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
3819 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
3820 | * just the one belonging to its engine). | |
3821 | * | |
3822 | */ | |
3823 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
3824 | ||
3825 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
3826 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
3827 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
3828 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
3829 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
3830 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
3831 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
3832 | ||
3833 | /* | |
3834 | * Set the GLOBAL_RESET bit. | |
3835 | * | |
3836 | * Should be run under rtnl lock | |
3837 | */ | |
3838 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
3839 | { | |
f16da43b AE |
3840 | u32 val; |
3841 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
3842 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 3843 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
f16da43b | 3844 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 VZ |
3845 | } |
3846 | ||
3847 | /* | |
3848 | * Clear the GLOBAL_RESET bit. | |
3849 | * | |
3850 | * Should be run under rtnl lock | |
3851 | */ | |
1191cb83 | 3852 | static void bnx2x_clear_reset_global(struct bnx2x *bp) |
c9ee9206 | 3853 | { |
f16da43b AE |
3854 | u32 val; |
3855 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
3856 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 3857 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
f16da43b | 3858 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 | 3859 | } |
f85582f8 | 3860 | |
72fd0718 | 3861 | /* |
c9ee9206 VZ |
3862 | * Checks the GLOBAL_RESET bit. |
3863 | * | |
72fd0718 VZ |
3864 | * should be run under rtnl lock |
3865 | */ | |
1191cb83 | 3866 | static bool bnx2x_reset_is_global(struct bnx2x *bp) |
c9ee9206 VZ |
3867 | { |
3868 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3869 | ||
3870 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
3871 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
3872 | } | |
3873 | ||
3874 | /* | |
3875 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
3876 | * | |
3877 | * Should be run under rtnl lock | |
3878 | */ | |
1191cb83 | 3879 | static void bnx2x_set_reset_done(struct bnx2x *bp) |
72fd0718 | 3880 | { |
f16da43b | 3881 | u32 val; |
c9ee9206 VZ |
3882 | u32 bit = BP_PATH(bp) ? |
3883 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
3884 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3885 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
3886 | |
3887 | /* Clear the bit */ | |
3888 | val &= ~bit; | |
3889 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
3890 | |
3891 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
72fd0718 VZ |
3892 | } |
3893 | ||
3894 | /* | |
c9ee9206 VZ |
3895 | * Set RESET_IN_PROGRESS for the current engine. |
3896 | * | |
72fd0718 VZ |
3897 | * should be run under rtnl lock |
3898 | */ | |
c9ee9206 | 3899 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 3900 | { |
f16da43b | 3901 | u32 val; |
c9ee9206 VZ |
3902 | u32 bit = BP_PATH(bp) ? |
3903 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
3904 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3905 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
3906 | |
3907 | /* Set the bit */ | |
3908 | val |= bit; | |
3909 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 3910 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
3911 | } |
3912 | ||
3913 | /* | |
c9ee9206 | 3914 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
3915 | * should be run under rtnl lock |
3916 | */ | |
c9ee9206 | 3917 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 3918 | { |
c9ee9206 VZ |
3919 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3920 | u32 bit = engine ? | |
3921 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3922 | ||
3923 | /* return false if bit is set */ | |
3924 | return (val & bit) ? false : true; | |
72fd0718 VZ |
3925 | } |
3926 | ||
3927 | /* | |
889b9af3 | 3928 | * set pf load for the current pf. |
c9ee9206 | 3929 | * |
72fd0718 VZ |
3930 | * should be run under rtnl lock |
3931 | */ | |
889b9af3 | 3932 | void bnx2x_set_pf_load(struct bnx2x *bp) |
72fd0718 | 3933 | { |
f16da43b | 3934 | u32 val1, val; |
c9ee9206 VZ |
3935 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
3936 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3937 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3938 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 3939 | |
f16da43b AE |
3940 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3941 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3942 | ||
51c1a580 | 3943 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 3944 | |
c9ee9206 VZ |
3945 | /* get the current counter value */ |
3946 | val1 = (val & mask) >> shift; | |
3947 | ||
889b9af3 AE |
3948 | /* set bit of that PF */ |
3949 | val1 |= (1 << bp->pf_num); | |
c9ee9206 VZ |
3950 | |
3951 | /* clear the old value */ | |
3952 | val &= ~mask; | |
3953 | ||
3954 | /* set the new one */ | |
3955 | val |= ((val1 << shift) & mask); | |
3956 | ||
3957 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 3958 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
3959 | } |
3960 | ||
c9ee9206 | 3961 | /** |
889b9af3 | 3962 | * bnx2x_clear_pf_load - clear pf load mark |
c9ee9206 VZ |
3963 | * |
3964 | * @bp: driver handle | |
3965 | * | |
3966 | * Should be run under rtnl lock. | |
3967 | * Decrements the load counter for the current engine. Returns | |
889b9af3 | 3968 | * whether other functions are still loaded |
72fd0718 | 3969 | */ |
889b9af3 | 3970 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
72fd0718 | 3971 | { |
f16da43b | 3972 | u32 val1, val; |
c9ee9206 VZ |
3973 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
3974 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3975 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3976 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 3977 | |
f16da43b AE |
3978 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3979 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
51c1a580 | 3980 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 3981 | |
c9ee9206 VZ |
3982 | /* get the current counter value */ |
3983 | val1 = (val & mask) >> shift; | |
3984 | ||
889b9af3 AE |
3985 | /* clear bit of that PF */ |
3986 | val1 &= ~(1 << bp->pf_num); | |
c9ee9206 VZ |
3987 | |
3988 | /* clear the old value */ | |
3989 | val &= ~mask; | |
3990 | ||
3991 | /* set the new one */ | |
3992 | val |= ((val1 << shift) & mask); | |
3993 | ||
3994 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
3995 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3996 | return val1 != 0; | |
72fd0718 VZ |
3997 | } |
3998 | ||
3999 | /* | |
889b9af3 | 4000 | * Read the load status for the current engine. |
c9ee9206 | 4001 | * |
72fd0718 VZ |
4002 | * should be run under rtnl lock |
4003 | */ | |
1191cb83 | 4004 | static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
72fd0718 | 4005 | { |
c9ee9206 VZ |
4006 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
4007 | BNX2X_PATH0_LOAD_CNT_MASK); | |
4008 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4009 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
4010 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4011 | ||
51c1a580 | 4012 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
c9ee9206 VZ |
4013 | |
4014 | val = (val & mask) >> shift; | |
4015 | ||
51c1a580 MS |
4016 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
4017 | engine, val); | |
c9ee9206 | 4018 | |
889b9af3 | 4019 | return val != 0; |
72fd0718 VZ |
4020 | } |
4021 | ||
c9ee9206 | 4022 | /* |
889b9af3 | 4023 | * Reset the load status for the current engine. |
c9ee9206 | 4024 | */ |
1191cb83 | 4025 | static void bnx2x_clear_load_status(struct bnx2x *bp) |
72fd0718 | 4026 | { |
f16da43b | 4027 | u32 val; |
c9ee9206 | 4028 | u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
f16da43b AE |
4029 | BNX2X_PATH0_LOAD_CNT_MASK); |
4030 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4031 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4032 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); |
f16da43b | 4033 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4034 | } |
4035 | ||
1191cb83 | 4036 | static void _print_next_block(int idx, const char *blk) |
72fd0718 | 4037 | { |
f1deab50 | 4038 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
4039 | } |
4040 | ||
1191cb83 ED |
4041 | static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, |
4042 | bool print) | |
72fd0718 VZ |
4043 | { |
4044 | int i = 0; | |
4045 | u32 cur_bit = 0; | |
4046 | for (i = 0; sig; i++) { | |
4047 | cur_bit = ((u32)0x1 << i); | |
4048 | if (sig & cur_bit) { | |
4049 | switch (cur_bit) { | |
4050 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
c9ee9206 VZ |
4051 | if (print) |
4052 | _print_next_block(par_num++, "BRB"); | |
72fd0718 VZ |
4053 | break; |
4054 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
c9ee9206 VZ |
4055 | if (print) |
4056 | _print_next_block(par_num++, "PARSER"); | |
72fd0718 VZ |
4057 | break; |
4058 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4059 | if (print) |
4060 | _print_next_block(par_num++, "TSDM"); | |
72fd0718 VZ |
4061 | break; |
4062 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
c9ee9206 VZ |
4063 | if (print) |
4064 | _print_next_block(par_num++, | |
4065 | "SEARCHER"); | |
4066 | break; | |
4067 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
4068 | if (print) | |
4069 | _print_next_block(par_num++, "TCM"); | |
72fd0718 VZ |
4070 | break; |
4071 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4072 | if (print) |
4073 | _print_next_block(par_num++, "TSEMI"); | |
4074 | break; | |
4075 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
4076 | if (print) | |
4077 | _print_next_block(par_num++, "XPB"); | |
72fd0718 VZ |
4078 | break; |
4079 | } | |
4080 | ||
4081 | /* Clear the bit */ | |
4082 | sig &= ~cur_bit; | |
4083 | } | |
4084 | } | |
4085 | ||
4086 | return par_num; | |
4087 | } | |
4088 | ||
1191cb83 ED |
4089 | static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, |
4090 | bool *global, bool print) | |
72fd0718 VZ |
4091 | { |
4092 | int i = 0; | |
4093 | u32 cur_bit = 0; | |
4094 | for (i = 0; sig; i++) { | |
4095 | cur_bit = ((u32)0x1 << i); | |
4096 | if (sig & cur_bit) { | |
4097 | switch (cur_bit) { | |
c9ee9206 VZ |
4098 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
4099 | if (print) | |
4100 | _print_next_block(par_num++, "PBF"); | |
72fd0718 VZ |
4101 | break; |
4102 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
c9ee9206 VZ |
4103 | if (print) |
4104 | _print_next_block(par_num++, "QM"); | |
4105 | break; | |
4106 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
4107 | if (print) | |
4108 | _print_next_block(par_num++, "TM"); | |
72fd0718 VZ |
4109 | break; |
4110 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4111 | if (print) |
4112 | _print_next_block(par_num++, "XSDM"); | |
4113 | break; | |
4114 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
4115 | if (print) | |
4116 | _print_next_block(par_num++, "XCM"); | |
72fd0718 VZ |
4117 | break; |
4118 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4119 | if (print) |
4120 | _print_next_block(par_num++, "XSEMI"); | |
72fd0718 VZ |
4121 | break; |
4122 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
c9ee9206 VZ |
4123 | if (print) |
4124 | _print_next_block(par_num++, | |
4125 | "DOORBELLQ"); | |
4126 | break; | |
4127 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
4128 | if (print) | |
4129 | _print_next_block(par_num++, "NIG"); | |
72fd0718 VZ |
4130 | break; |
4131 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 VZ |
4132 | if (print) |
4133 | _print_next_block(par_num++, | |
4134 | "VAUX PCI CORE"); | |
4135 | *global = true; | |
72fd0718 VZ |
4136 | break; |
4137 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
c9ee9206 VZ |
4138 | if (print) |
4139 | _print_next_block(par_num++, "DEBUG"); | |
72fd0718 VZ |
4140 | break; |
4141 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
c9ee9206 VZ |
4142 | if (print) |
4143 | _print_next_block(par_num++, "USDM"); | |
72fd0718 | 4144 | break; |
8736c826 VZ |
4145 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
4146 | if (print) | |
4147 | _print_next_block(par_num++, "UCM"); | |
4148 | break; | |
72fd0718 | 4149 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
c9ee9206 VZ |
4150 | if (print) |
4151 | _print_next_block(par_num++, "USEMI"); | |
72fd0718 VZ |
4152 | break; |
4153 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
c9ee9206 VZ |
4154 | if (print) |
4155 | _print_next_block(par_num++, "UPB"); | |
72fd0718 VZ |
4156 | break; |
4157 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4158 | if (print) |
4159 | _print_next_block(par_num++, "CSDM"); | |
72fd0718 | 4160 | break; |
8736c826 VZ |
4161 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
4162 | if (print) | |
4163 | _print_next_block(par_num++, "CCM"); | |
4164 | break; | |
72fd0718 VZ |
4165 | } |
4166 | ||
4167 | /* Clear the bit */ | |
4168 | sig &= ~cur_bit; | |
4169 | } | |
4170 | } | |
4171 | ||
4172 | return par_num; | |
4173 | } | |
4174 | ||
1191cb83 ED |
4175 | static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, |
4176 | bool print) | |
72fd0718 VZ |
4177 | { |
4178 | int i = 0; | |
4179 | u32 cur_bit = 0; | |
4180 | for (i = 0; sig; i++) { | |
4181 | cur_bit = ((u32)0x1 << i); | |
4182 | if (sig & cur_bit) { | |
4183 | switch (cur_bit) { | |
4184 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4185 | if (print) |
4186 | _print_next_block(par_num++, "CSEMI"); | |
72fd0718 VZ |
4187 | break; |
4188 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
c9ee9206 VZ |
4189 | if (print) |
4190 | _print_next_block(par_num++, "PXP"); | |
72fd0718 VZ |
4191 | break; |
4192 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
c9ee9206 VZ |
4193 | if (print) |
4194 | _print_next_block(par_num++, | |
72fd0718 VZ |
4195 | "PXPPCICLOCKCLIENT"); |
4196 | break; | |
4197 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
c9ee9206 VZ |
4198 | if (print) |
4199 | _print_next_block(par_num++, "CFC"); | |
72fd0718 VZ |
4200 | break; |
4201 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
c9ee9206 VZ |
4202 | if (print) |
4203 | _print_next_block(par_num++, "CDU"); | |
4204 | break; | |
4205 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
4206 | if (print) | |
4207 | _print_next_block(par_num++, "DMAE"); | |
72fd0718 VZ |
4208 | break; |
4209 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
c9ee9206 VZ |
4210 | if (print) |
4211 | _print_next_block(par_num++, "IGU"); | |
72fd0718 VZ |
4212 | break; |
4213 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
c9ee9206 VZ |
4214 | if (print) |
4215 | _print_next_block(par_num++, "MISC"); | |
72fd0718 VZ |
4216 | break; |
4217 | } | |
4218 | ||
4219 | /* Clear the bit */ | |
4220 | sig &= ~cur_bit; | |
4221 | } | |
4222 | } | |
4223 | ||
4224 | return par_num; | |
4225 | } | |
4226 | ||
1191cb83 ED |
4227 | static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, |
4228 | bool *global, bool print) | |
72fd0718 VZ |
4229 | { |
4230 | int i = 0; | |
4231 | u32 cur_bit = 0; | |
4232 | for (i = 0; sig; i++) { | |
4233 | cur_bit = ((u32)0x1 << i); | |
4234 | if (sig & cur_bit) { | |
4235 | switch (cur_bit) { | |
4236 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 VZ |
4237 | if (print) |
4238 | _print_next_block(par_num++, "MCP ROM"); | |
4239 | *global = true; | |
72fd0718 VZ |
4240 | break; |
4241 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 VZ |
4242 | if (print) |
4243 | _print_next_block(par_num++, | |
4244 | "MCP UMP RX"); | |
4245 | *global = true; | |
72fd0718 VZ |
4246 | break; |
4247 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 VZ |
4248 | if (print) |
4249 | _print_next_block(par_num++, | |
4250 | "MCP UMP TX"); | |
4251 | *global = true; | |
72fd0718 VZ |
4252 | break; |
4253 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
c9ee9206 VZ |
4254 | if (print) |
4255 | _print_next_block(par_num++, | |
4256 | "MCP SCPAD"); | |
4257 | *global = true; | |
72fd0718 VZ |
4258 | break; |
4259 | } | |
4260 | ||
4261 | /* Clear the bit */ | |
4262 | sig &= ~cur_bit; | |
4263 | } | |
4264 | } | |
4265 | ||
4266 | return par_num; | |
4267 | } | |
4268 | ||
1191cb83 ED |
4269 | static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, |
4270 | bool print) | |
8736c826 VZ |
4271 | { |
4272 | int i = 0; | |
4273 | u32 cur_bit = 0; | |
4274 | for (i = 0; sig; i++) { | |
4275 | cur_bit = ((u32)0x1 << i); | |
4276 | if (sig & cur_bit) { | |
4277 | switch (cur_bit) { | |
4278 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
4279 | if (print) | |
4280 | _print_next_block(par_num++, "PGLUE_B"); | |
4281 | break; | |
4282 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
4283 | if (print) | |
4284 | _print_next_block(par_num++, "ATC"); | |
4285 | break; | |
4286 | } | |
4287 | ||
4288 | /* Clear the bit */ | |
4289 | sig &= ~cur_bit; | |
4290 | } | |
4291 | } | |
4292 | ||
4293 | return par_num; | |
4294 | } | |
4295 | ||
1191cb83 ED |
4296 | static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
4297 | u32 *sig) | |
72fd0718 | 4298 | { |
8736c826 VZ |
4299 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4300 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4301 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4302 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4303 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 | 4304 | int par_num = 0; |
51c1a580 MS |
4305 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
4306 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", | |
8736c826 VZ |
4307 | sig[0] & HW_PRTY_ASSERT_SET_0, |
4308 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4309 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4310 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4311 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
c9ee9206 VZ |
4312 | if (print) |
4313 | netdev_err(bp->dev, | |
4314 | "Parity errors detected in blocks: "); | |
4315 | par_num = bnx2x_check_blocks_with_parity0( | |
8736c826 | 4316 | sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); |
c9ee9206 | 4317 | par_num = bnx2x_check_blocks_with_parity1( |
8736c826 | 4318 | sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); |
c9ee9206 | 4319 | par_num = bnx2x_check_blocks_with_parity2( |
8736c826 | 4320 | sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); |
c9ee9206 | 4321 | par_num = bnx2x_check_blocks_with_parity3( |
8736c826 VZ |
4322 | sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); |
4323 | par_num = bnx2x_check_blocks_with_parity4( | |
4324 | sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); | |
4325 | ||
c9ee9206 VZ |
4326 | if (print) |
4327 | pr_cont("\n"); | |
8736c826 | 4328 | |
72fd0718 VZ |
4329 | return true; |
4330 | } else | |
4331 | return false; | |
4332 | } | |
4333 | ||
c9ee9206 VZ |
4334 | /** |
4335 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
4336 | * | |
4337 | * @bp: driver handle | |
4338 | * @global: true if there was a global attention | |
4339 | * @print: show parity attention in syslog | |
4340 | */ | |
4341 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 4342 | { |
8736c826 | 4343 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
4344 | int port = BP_PORT(bp); |
4345 | ||
4346 | attn.sig[0] = REG_RD(bp, | |
4347 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
4348 | port*4); | |
4349 | attn.sig[1] = REG_RD(bp, | |
4350 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
4351 | port*4); | |
4352 | attn.sig[2] = REG_RD(bp, | |
4353 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
4354 | port*4); | |
4355 | attn.sig[3] = REG_RD(bp, | |
4356 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
4357 | port*4); | |
4358 | ||
8736c826 VZ |
4359 | if (!CHIP_IS_E1x(bp)) |
4360 | attn.sig[4] = REG_RD(bp, | |
4361 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
4362 | port*4); | |
4363 | ||
4364 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
4365 | } |
4366 | ||
f2e0899f | 4367 | |
1191cb83 | 4368 | static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) |
f2e0899f DK |
4369 | { |
4370 | u32 val; | |
4371 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
4372 | ||
4373 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
4374 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
4375 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
51c1a580 | 4376 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
f2e0899f | 4377 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
51c1a580 | 4378 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
f2e0899f | 4379 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
51c1a580 | 4380 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
f2e0899f | 4381 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
51c1a580 | 4382 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
f2e0899f DK |
4383 | if (val & |
4384 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
51c1a580 | 4385 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
f2e0899f DK |
4386 | if (val & |
4387 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
51c1a580 | 4388 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
f2e0899f | 4389 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
51c1a580 | 4390 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
f2e0899f | 4391 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
51c1a580 | 4392 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
f2e0899f | 4393 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
51c1a580 | 4394 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
f2e0899f DK |
4395 | } |
4396 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
4397 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
4398 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
4399 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
4400 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
4401 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
51c1a580 | 4402 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
f2e0899f | 4403 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
51c1a580 | 4404 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
f2e0899f | 4405 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
51c1a580 | 4406 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
f2e0899f DK |
4407 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
4408 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
4409 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
51c1a580 | 4410 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
f2e0899f DK |
4411 | } |
4412 | ||
4413 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4414 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
4415 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
4416 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4417 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
4418 | } | |
4419 | ||
4420 | } | |
4421 | ||
72fd0718 VZ |
4422 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
4423 | { | |
4424 | struct attn_route attn, *group_mask; | |
34f80b04 | 4425 | int port = BP_PORT(bp); |
877e9aa4 | 4426 | int index; |
a2fbb9ea ET |
4427 | u32 reg_addr; |
4428 | u32 val; | |
3fcaf2e5 | 4429 | u32 aeu_mask; |
c9ee9206 | 4430 | bool global = false; |
a2fbb9ea ET |
4431 | |
4432 | /* need to take HW lock because MCP or other port might also | |
4433 | try to handle this event */ | |
4a37fb66 | 4434 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 4435 | |
c9ee9206 VZ |
4436 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
4437 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 4438 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 4439 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
4440 | /* Disable HW interrupts */ |
4441 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
4442 | /* In case of parity errors don't handle attentions so that |
4443 | * other function would "see" parity errors. | |
4444 | */ | |
c9ee9206 VZ |
4445 | #else |
4446 | bnx2x_panic(); | |
4447 | #endif | |
4448 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
4449 | return; |
4450 | } | |
4451 | ||
a2fbb9ea ET |
4452 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
4453 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
4454 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
4455 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 4456 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4457 | attn.sig[4] = |
4458 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
4459 | else | |
4460 | attn.sig[4] = 0; | |
4461 | ||
4462 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
4463 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
4464 | |
4465 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
4466 | if (deasserted & (1 << index)) { | |
72fd0718 | 4467 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 4468 | |
51c1a580 | 4469 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
f2e0899f DK |
4470 | index, |
4471 | group_mask->sig[0], group_mask->sig[1], | |
4472 | group_mask->sig[2], group_mask->sig[3], | |
4473 | group_mask->sig[4]); | |
a2fbb9ea | 4474 | |
f2e0899f DK |
4475 | bnx2x_attn_int_deasserted4(bp, |
4476 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 4477 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 4478 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 4479 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 4480 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 4481 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 4482 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 4483 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 4484 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
4485 | } |
4486 | } | |
4487 | ||
4a37fb66 | 4488 | bnx2x_release_alr(bp); |
a2fbb9ea | 4489 | |
f2e0899f DK |
4490 | if (bp->common.int_block == INT_BLOCK_HC) |
4491 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4492 | COMMAND_REG_ATTN_BITS_CLR); | |
4493 | else | |
4494 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
4495 | |
4496 | val = ~deasserted; | |
f2e0899f DK |
4497 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
4498 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 4499 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 4500 | |
a2fbb9ea | 4501 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 4502 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
4503 | |
4504 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
4505 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
4506 | ||
3fcaf2e5 EG |
4507 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4508 | aeu_mask = REG_RD(bp, reg_addr); | |
4509 | ||
4510 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
4511 | aeu_mask, deasserted); | |
72fd0718 | 4512 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 4513 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4514 | |
3fcaf2e5 EG |
4515 | REG_WR(bp, reg_addr, aeu_mask); |
4516 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
4517 | |
4518 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
4519 | bp->attn_state &= ~deasserted; | |
4520 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
4521 | } | |
4522 | ||
4523 | static void bnx2x_attn_int(struct bnx2x *bp) | |
4524 | { | |
4525 | /* read local copy of bits */ | |
68d59484 EG |
4526 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
4527 | attn_bits); | |
4528 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
4529 | attn_bits_ack); | |
a2fbb9ea ET |
4530 | u32 attn_state = bp->attn_state; |
4531 | ||
4532 | /* look for changed bits */ | |
4533 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
4534 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
4535 | ||
4536 | DP(NETIF_MSG_HW, | |
4537 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
4538 | attn_bits, attn_ack, asserted, deasserted); | |
4539 | ||
4540 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 4541 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
4542 | |
4543 | /* handle bits that were raised */ | |
4544 | if (asserted) | |
4545 | bnx2x_attn_int_asserted(bp, asserted); | |
4546 | ||
4547 | if (deasserted) | |
4548 | bnx2x_attn_int_deasserted(bp, deasserted); | |
4549 | } | |
4550 | ||
619c5cb6 VZ |
4551 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
4552 | u16 index, u8 op, u8 update) | |
4553 | { | |
4554 | u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
4555 | ||
4556 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, | |
4557 | igu_addr); | |
4558 | } | |
4559 | ||
1191cb83 | 4560 | static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
523224a3 DK |
4561 | { |
4562 | /* No memory barriers */ | |
4563 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
4564 | mmiowb(); /* keep prod updates ordered */ | |
4565 | } | |
4566 | ||
4567 | #ifdef BCM_CNIC | |
4568 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, | |
4569 | union event_ring_elem *elem) | |
4570 | { | |
619c5cb6 VZ |
4571 | u8 err = elem->message.error; |
4572 | ||
523224a3 | 4573 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
4574 | (cid < bp->cnic_eth_dev.starting_cid && |
4575 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
4576 | return 1; |
4577 | ||
4578 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
4579 | ||
619c5cb6 VZ |
4580 | if (unlikely(err)) { |
4581 | ||
523224a3 DK |
4582 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
4583 | cid); | |
4584 | bnx2x_panic_dump(bp); | |
4585 | } | |
619c5cb6 | 4586 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
4587 | return 0; |
4588 | } | |
4589 | #endif | |
4590 | ||
1191cb83 | 4591 | static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
4592 | { |
4593 | struct bnx2x_mcast_ramrod_params rparam; | |
4594 | int rc; | |
4595 | ||
4596 | memset(&rparam, 0, sizeof(rparam)); | |
4597 | ||
4598 | rparam.mcast_obj = &bp->mcast_obj; | |
4599 | ||
4600 | netif_addr_lock_bh(bp->dev); | |
4601 | ||
4602 | /* Clear pending state for the last command */ | |
4603 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
4604 | ||
4605 | /* If there are pending mcast commands - send them */ | |
4606 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
4607 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
4608 | if (rc < 0) | |
4609 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
4610 | rc); | |
4611 | } | |
4612 | ||
4613 | netif_addr_unlock_bh(bp->dev); | |
4614 | } | |
4615 | ||
1191cb83 ED |
4616 | static void bnx2x_handle_classification_eqe(struct bnx2x *bp, |
4617 | union event_ring_elem *elem) | |
619c5cb6 VZ |
4618 | { |
4619 | unsigned long ramrod_flags = 0; | |
4620 | int rc = 0; | |
4621 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
4622 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
4623 | ||
4624 | /* Always push next commands out, don't wait here */ | |
4625 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
4626 | ||
4627 | switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { | |
4628 | case BNX2X_FILTER_MAC_PENDING: | |
51c1a580 | 4629 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
619c5cb6 | 4630 | #ifdef BCM_CNIC |
37ae41a9 | 4631 | if (cid == BNX2X_ISCSI_ETH_CID(bp)) |
619c5cb6 VZ |
4632 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; |
4633 | else | |
4634 | #endif | |
15192a8c | 4635 | vlan_mac_obj = &bp->sp_objs[cid].mac_obj; |
619c5cb6 VZ |
4636 | |
4637 | break; | |
619c5cb6 | 4638 | case BNX2X_FILTER_MCAST_PENDING: |
51c1a580 | 4639 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
619c5cb6 VZ |
4640 | /* This is only relevant for 57710 where multicast MACs are |
4641 | * configured as unicast MACs using the same ramrod. | |
4642 | */ | |
4643 | bnx2x_handle_mcast_eqe(bp); | |
4644 | return; | |
4645 | default: | |
4646 | BNX2X_ERR("Unsupported classification command: %d\n", | |
4647 | elem->message.data.eth_event.echo); | |
4648 | return; | |
4649 | } | |
4650 | ||
4651 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
4652 | ||
4653 | if (rc < 0) | |
4654 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
4655 | else if (rc > 0) | |
4656 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
4657 | ||
4658 | } | |
4659 | ||
4660 | #ifdef BCM_CNIC | |
4661 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); | |
4662 | #endif | |
4663 | ||
1191cb83 | 4664 | static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
4665 | { |
4666 | netif_addr_lock_bh(bp->dev); | |
4667 | ||
4668 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
4669 | ||
4670 | /* Send rx_mode command again if was requested */ | |
4671 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
4672 | bnx2x_set_storm_rx_mode(bp); | |
4673 | #ifdef BCM_CNIC | |
4674 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, | |
4675 | &bp->sp_state)) | |
4676 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
4677 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
4678 | &bp->sp_state)) | |
4679 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
4680 | #endif | |
4681 | ||
4682 | netif_addr_unlock_bh(bp->dev); | |
4683 | } | |
4684 | ||
1191cb83 | 4685 | static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, |
a3348722 BW |
4686 | union event_ring_elem *elem) |
4687 | { | |
4688 | if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { | |
4689 | DP(BNX2X_MSG_SP, | |
4690 | "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", | |
4691 | elem->message.data.vif_list_event.func_bit_map); | |
4692 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, | |
4693 | elem->message.data.vif_list_event.func_bit_map); | |
4694 | } else if (elem->message.data.vif_list_event.echo == | |
4695 | VIF_LIST_RULE_SET) { | |
4696 | DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); | |
4697 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); | |
4698 | } | |
4699 | } | |
4700 | ||
4701 | /* called with rtnl_lock */ | |
1191cb83 | 4702 | static void bnx2x_after_function_update(struct bnx2x *bp) |
a3348722 BW |
4703 | { |
4704 | int q, rc; | |
4705 | struct bnx2x_fastpath *fp; | |
4706 | struct bnx2x_queue_state_params queue_params = {NULL}; | |
4707 | struct bnx2x_queue_update_params *q_update_params = | |
4708 | &queue_params.params.update; | |
4709 | ||
4710 | /* Send Q update command with afex vlan removal values for all Qs */ | |
4711 | queue_params.cmd = BNX2X_Q_CMD_UPDATE; | |
4712 | ||
4713 | /* set silent vlan removal values according to vlan mode */ | |
4714 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | |
4715 | &q_update_params->update_flags); | |
4716 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
4717 | &q_update_params->update_flags); | |
4718 | __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
4719 | ||
4720 | /* in access mode mark mask and value are 0 to strip all vlans */ | |
4721 | if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { | |
4722 | q_update_params->silent_removal_value = 0; | |
4723 | q_update_params->silent_removal_mask = 0; | |
4724 | } else { | |
4725 | q_update_params->silent_removal_value = | |
4726 | (bp->afex_def_vlan_tag & VLAN_VID_MASK); | |
4727 | q_update_params->silent_removal_mask = VLAN_VID_MASK; | |
4728 | } | |
4729 | ||
4730 | for_each_eth_queue(bp, q) { | |
4731 | /* Set the appropriate Queue object */ | |
4732 | fp = &bp->fp[q]; | |
15192a8c | 4733 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
4734 | |
4735 | /* send the ramrod */ | |
4736 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
4737 | if (rc < 0) | |
4738 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
4739 | q); | |
4740 | } | |
4741 | ||
4742 | #ifdef BCM_CNIC | |
4743 | if (!NO_FCOE(bp)) { | |
65565884 | 4744 | fp = &bp->fp[FCOE_IDX(bp)]; |
15192a8c | 4745 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
4746 | |
4747 | /* clear pending completion bit */ | |
4748 | __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
4749 | ||
4750 | /* mark latest Q bit */ | |
4751 | smp_mb__before_clear_bit(); | |
4752 | set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
4753 | smp_mb__after_clear_bit(); | |
4754 | ||
4755 | /* send Q update ramrod for FCoE Q */ | |
4756 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
4757 | if (rc < 0) | |
4758 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
4759 | q); | |
4760 | } else { | |
4761 | /* If no FCoE ring - ACK MCP now */ | |
4762 | bnx2x_link_report(bp); | |
4763 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
4764 | } | |
4765 | #else | |
4766 | /* If no FCoE ring - ACK MCP now */ | |
4767 | bnx2x_link_report(bp); | |
4768 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
4769 | #endif /* BCM_CNIC */ | |
4770 | } | |
4771 | ||
1191cb83 | 4772 | static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( |
619c5cb6 VZ |
4773 | struct bnx2x *bp, u32 cid) |
4774 | { | |
94f05b0f | 4775 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
619c5cb6 | 4776 | #ifdef BCM_CNIC |
37ae41a9 | 4777 | if (cid == BNX2X_FCOE_ETH_CID(bp)) |
15192a8c | 4778 | return &bnx2x_fcoe_sp_obj(bp, q_obj); |
619c5cb6 VZ |
4779 | else |
4780 | #endif | |
15192a8c | 4781 | return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; |
619c5cb6 VZ |
4782 | } |
4783 | ||
523224a3 DK |
4784 | static void bnx2x_eq_int(struct bnx2x *bp) |
4785 | { | |
4786 | u16 hw_cons, sw_cons, sw_prod; | |
4787 | union event_ring_elem *elem; | |
4788 | u32 cid; | |
4789 | u8 opcode; | |
4790 | int spqe_cnt = 0; | |
619c5cb6 VZ |
4791 | struct bnx2x_queue_sp_obj *q_obj; |
4792 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
4793 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
4794 | |
4795 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
4796 | ||
4797 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
4798 | * when we get the the next-page we nned to adjust so the loop | |
4799 | * condition below will be met. The next element is the size of a | |
4800 | * regular element and hence incrementing by 1 | |
4801 | */ | |
4802 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
4803 | hw_cons++; | |
4804 | ||
25985edc | 4805 | /* This function may never run in parallel with itself for a |
523224a3 DK |
4806 | * specific bp, thus there is no need in "paired" read memory |
4807 | * barrier here. | |
4808 | */ | |
4809 | sw_cons = bp->eq_cons; | |
4810 | sw_prod = bp->eq_prod; | |
4811 | ||
d6cae238 | 4812 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 4813 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
4814 | |
4815 | for (; sw_cons != hw_cons; | |
4816 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
4817 | ||
4818 | ||
4819 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; | |
4820 | ||
4821 | cid = SW_CID(elem->message.data.cfc_del_event.cid); | |
4822 | opcode = elem->message.opcode; | |
4823 | ||
4824 | ||
4825 | /* handle eq element */ | |
4826 | switch (opcode) { | |
4827 | case EVENT_RING_OPCODE_STAT_QUERY: | |
51c1a580 MS |
4828 | DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, |
4829 | "got statistics comp event %d\n", | |
619c5cb6 | 4830 | bp->stats_comp++); |
523224a3 | 4831 | /* nothing to do with stats comp */ |
d6cae238 | 4832 | goto next_spqe; |
523224a3 DK |
4833 | |
4834 | case EVENT_RING_OPCODE_CFC_DEL: | |
4835 | /* handle according to cid range */ | |
4836 | /* | |
4837 | * we may want to verify here that the bp state is | |
4838 | * HALTING | |
4839 | */ | |
d6cae238 | 4840 | DP(BNX2X_MSG_SP, |
523224a3 DK |
4841 | "got delete ramrod for MULTI[%d]\n", cid); |
4842 | #ifdef BCM_CNIC | |
4843 | if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
4844 | goto next_spqe; | |
4845 | #endif | |
619c5cb6 VZ |
4846 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
4847 | ||
4848 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
4849 | break; | |
4850 | ||
4851 | ||
523224a3 DK |
4852 | |
4853 | goto next_spqe; | |
e4901dde VZ |
4854 | |
4855 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
51c1a580 | 4856 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
6debea87 DK |
4857 | if (f_obj->complete_cmd(bp, f_obj, |
4858 | BNX2X_F_CMD_TX_STOP)) | |
4859 | break; | |
e4901dde VZ |
4860 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
4861 | goto next_spqe; | |
619c5cb6 | 4862 | |
e4901dde | 4863 | case EVENT_RING_OPCODE_START_TRAFFIC: |
51c1a580 | 4864 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
6debea87 DK |
4865 | if (f_obj->complete_cmd(bp, f_obj, |
4866 | BNX2X_F_CMD_TX_START)) | |
4867 | break; | |
e4901dde VZ |
4868 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
4869 | goto next_spqe; | |
a3348722 BW |
4870 | case EVENT_RING_OPCODE_FUNCTION_UPDATE: |
4871 | DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, | |
4872 | "AFEX: ramrod completed FUNCTION_UPDATE\n"); | |
4873 | f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_AFEX_UPDATE); | |
4874 | ||
4875 | /* We will perform the Queues update from sp_rtnl task | |
4876 | * as all Queue SP operations should run under | |
4877 | * rtnl_lock. | |
4878 | */ | |
4879 | smp_mb__before_clear_bit(); | |
4880 | set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, | |
4881 | &bp->sp_rtnl_state); | |
4882 | smp_mb__after_clear_bit(); | |
4883 | ||
4884 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
4885 | goto next_spqe; | |
4886 | ||
4887 | case EVENT_RING_OPCODE_AFEX_VIF_LISTS: | |
4888 | f_obj->complete_cmd(bp, f_obj, | |
4889 | BNX2X_F_CMD_AFEX_VIFLISTS); | |
4890 | bnx2x_after_afex_vif_lists(bp, elem); | |
4891 | goto next_spqe; | |
619c5cb6 | 4892 | case EVENT_RING_OPCODE_FUNCTION_START: |
51c1a580 MS |
4893 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
4894 | "got FUNC_START ramrod\n"); | |
619c5cb6 VZ |
4895 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
4896 | break; | |
4897 | ||
4898 | goto next_spqe; | |
4899 | ||
4900 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
51c1a580 MS |
4901 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
4902 | "got FUNC_STOP ramrod\n"); | |
619c5cb6 VZ |
4903 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
4904 | break; | |
4905 | ||
4906 | goto next_spqe; | |
523224a3 DK |
4907 | } |
4908 | ||
4909 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
4910 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
4911 | BNX2X_STATE_OPEN): | |
4912 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 4913 | BNX2X_STATE_OPENING_WAIT4_PORT): |
619c5cb6 VZ |
4914 | cid = elem->message.data.eth_event.echo & |
4915 | BNX2X_SWCID_MASK; | |
d6cae238 | 4916 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
619c5cb6 VZ |
4917 | cid); |
4918 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
4919 | break; |
4920 | ||
619c5cb6 VZ |
4921 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
4922 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
4923 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 4924 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
4925 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
4926 | BNX2X_STATE_OPEN): | |
4927 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4928 | BNX2X_STATE_DIAG): | |
4929 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4930 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 4931 | DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); |
619c5cb6 | 4932 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
4933 | break; |
4934 | ||
619c5cb6 VZ |
4935 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
4936 | BNX2X_STATE_OPEN): | |
4937 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4938 | BNX2X_STATE_DIAG): | |
4939 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4940 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 4941 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 4942 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
4943 | break; |
4944 | ||
619c5cb6 VZ |
4945 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
4946 | BNX2X_STATE_OPEN): | |
4947 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
4948 | BNX2X_STATE_DIAG): | |
4949 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 4950 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 4951 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 4952 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
4953 | break; |
4954 | default: | |
4955 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
4956 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
4957 | elem->message.opcode, bp->state); | |
523224a3 DK |
4958 | } |
4959 | next_spqe: | |
4960 | spqe_cnt++; | |
4961 | } /* for */ | |
4962 | ||
8fe23fbd | 4963 | smp_mb__before_atomic_inc(); |
6e30dd4e | 4964 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
4965 | |
4966 | bp->eq_cons = sw_cons; | |
4967 | bp->eq_prod = sw_prod; | |
4968 | /* Make sure that above mem writes were issued towards the memory */ | |
4969 | smp_wmb(); | |
4970 | ||
4971 | /* update producer */ | |
4972 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
4973 | } | |
4974 | ||
a2fbb9ea ET |
4975 | static void bnx2x_sp_task(struct work_struct *work) |
4976 | { | |
1cf167f2 | 4977 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea ET |
4978 | u16 status; |
4979 | ||
a2fbb9ea | 4980 | status = bnx2x_update_dsb_idx(bp); |
34f80b04 EG |
4981 | /* if (status == 0) */ |
4982 | /* BNX2X_ERR("spurious slowpath interrupt!\n"); */ | |
a2fbb9ea | 4983 | |
51c1a580 | 4984 | DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status); |
a2fbb9ea | 4985 | |
877e9aa4 | 4986 | /* HW attentions */ |
523224a3 | 4987 | if (status & BNX2X_DEF_SB_ATT_IDX) { |
a2fbb9ea | 4988 | bnx2x_attn_int(bp); |
523224a3 | 4989 | status &= ~BNX2X_DEF_SB_ATT_IDX; |
cdaa7cb8 VZ |
4990 | } |
4991 | ||
523224a3 DK |
4992 | /* SP events: STAT_QUERY and others */ |
4993 | if (status & BNX2X_DEF_SB_IDX) { | |
ec6ba945 VZ |
4994 | #ifdef BCM_CNIC |
4995 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 4996 | |
ec6ba945 | 4997 | if ((!NO_FCOE(bp)) && |
019dbb4c VZ |
4998 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
4999 | /* | |
5000 | * Prevent local bottom-halves from running as | |
5001 | * we are going to change the local NAPI list. | |
5002 | */ | |
5003 | local_bh_disable(); | |
ec6ba945 | 5004 | napi_schedule(&bnx2x_fcoe(bp, napi)); |
019dbb4c VZ |
5005 | local_bh_enable(); |
5006 | } | |
ec6ba945 | 5007 | #endif |
523224a3 DK |
5008 | /* Handle EQ completions */ |
5009 | bnx2x_eq_int(bp); | |
5010 | ||
5011 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
5012 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
5013 | ||
5014 | status &= ~BNX2X_DEF_SB_IDX; | |
cdaa7cb8 VZ |
5015 | } |
5016 | ||
5017 | if (unlikely(status)) | |
51c1a580 | 5018 | DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n", |
cdaa7cb8 | 5019 | status); |
a2fbb9ea | 5020 | |
523224a3 DK |
5021 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, |
5022 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
a3348722 BW |
5023 | |
5024 | /* afex - poll to check if VIFSET_ACK should be sent to MFW */ | |
5025 | if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, | |
5026 | &bp->sp_state)) { | |
5027 | bnx2x_link_report(bp); | |
5028 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5029 | } | |
a2fbb9ea ET |
5030 | } |
5031 | ||
9f6c9258 | 5032 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
5033 | { |
5034 | struct net_device *dev = dev_instance; | |
5035 | struct bnx2x *bp = netdev_priv(dev); | |
5036 | ||
523224a3 DK |
5037 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
5038 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
5039 | |
5040 | #ifdef BNX2X_STOP_ON_ERROR | |
5041 | if (unlikely(bp->panic)) | |
5042 | return IRQ_HANDLED; | |
5043 | #endif | |
5044 | ||
993ac7b5 MC |
5045 | #ifdef BCM_CNIC |
5046 | { | |
5047 | struct cnic_ops *c_ops; | |
5048 | ||
5049 | rcu_read_lock(); | |
5050 | c_ops = rcu_dereference(bp->cnic_ops); | |
5051 | if (c_ops) | |
5052 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
5053 | rcu_read_unlock(); | |
5054 | } | |
5055 | #endif | |
1cf167f2 | 5056 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
5057 | |
5058 | return IRQ_HANDLED; | |
5059 | } | |
5060 | ||
5061 | /* end of slow path */ | |
5062 | ||
619c5cb6 VZ |
5063 | |
5064 | void bnx2x_drv_pulse(struct bnx2x *bp) | |
5065 | { | |
5066 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
5067 | bp->fw_drv_pulse_wr_seq); | |
5068 | } | |
5069 | ||
5070 | ||
a2fbb9ea ET |
5071 | static void bnx2x_timer(unsigned long data) |
5072 | { | |
5073 | struct bnx2x *bp = (struct bnx2x *) data; | |
5074 | ||
5075 | if (!netif_running(bp->dev)) | |
5076 | return; | |
5077 | ||
34f80b04 | 5078 | if (!BP_NOMCP(bp)) { |
f2e0899f | 5079 | int mb_idx = BP_FW_MB_IDX(bp); |
a2fbb9ea ET |
5080 | u32 drv_pulse; |
5081 | u32 mcp_pulse; | |
5082 | ||
5083 | ++bp->fw_drv_pulse_wr_seq; | |
5084 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
5085 | /* TBD - add SYSTEM_TIME */ | |
5086 | drv_pulse = bp->fw_drv_pulse_wr_seq; | |
619c5cb6 | 5087 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 5088 | |
f2e0899f | 5089 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
5090 | MCP_PULSE_SEQ_MASK); |
5091 | /* The delta between driver pulse and mcp response | |
5092 | * should be 1 (before mcp response) or 0 (after mcp response) | |
5093 | */ | |
5094 | if ((drv_pulse != mcp_pulse) && | |
5095 | (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { | |
5096 | /* someone lost a heartbeat... */ | |
5097 | BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
5098 | drv_pulse, mcp_pulse); | |
5099 | } | |
5100 | } | |
5101 | ||
f34d28ea | 5102 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 5103 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 5104 | |
a2fbb9ea ET |
5105 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
5106 | } | |
5107 | ||
5108 | /* end of Statistics */ | |
5109 | ||
5110 | /* nic init */ | |
5111 | ||
5112 | /* | |
5113 | * nic init service functions | |
5114 | */ | |
5115 | ||
1191cb83 | 5116 | static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 5117 | { |
523224a3 DK |
5118 | u32 i; |
5119 | if (!(len%4) && !(addr%4)) | |
5120 | for (i = 0; i < len; i += 4) | |
5121 | REG_WR(bp, addr + i, fill); | |
5122 | else | |
5123 | for (i = 0; i < len; i++) | |
5124 | REG_WR8(bp, addr + i, fill); | |
34f80b04 | 5125 | |
34f80b04 EG |
5126 | } |
5127 | ||
523224a3 | 5128 | /* helper: writes FP SP data to FW - data_size in dwords */ |
1191cb83 ED |
5129 | static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, |
5130 | int fw_sb_id, | |
5131 | u32 *sb_data_p, | |
5132 | u32 data_size) | |
34f80b04 | 5133 | { |
a2fbb9ea | 5134 | int index; |
523224a3 DK |
5135 | for (index = 0; index < data_size; index++) |
5136 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5137 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
5138 | sizeof(u32)*index, | |
5139 | *(sb_data_p + index)); | |
5140 | } | |
a2fbb9ea | 5141 | |
1191cb83 | 5142 | static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
523224a3 DK |
5143 | { |
5144 | u32 *sb_data_p; | |
5145 | u32 data_size = 0; | |
f2e0899f | 5146 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 5147 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 5148 | |
523224a3 | 5149 | /* disable the function first */ |
619c5cb6 | 5150 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5151 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5152 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
5153 | sb_data_e2.common.p_func.vf_valid = false; |
5154 | sb_data_p = (u32 *)&sb_data_e2; | |
5155 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
5156 | } else { | |
5157 | memset(&sb_data_e1x, 0, | |
5158 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5159 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
5160 | sb_data_e1x.common.p_func.vf_valid = false; |
5161 | sb_data_p = (u32 *)&sb_data_e1x; | |
5162 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
5163 | } | |
523224a3 | 5164 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 5165 | |
523224a3 DK |
5166 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
5167 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
5168 | CSTORM_STATUS_BLOCK_SIZE); | |
5169 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5170 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
5171 | CSTORM_SYNC_BLOCK_SIZE); | |
5172 | } | |
34f80b04 | 5173 | |
523224a3 | 5174 | /* helper: writes SP SB data to FW */ |
1191cb83 | 5175 | static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, |
523224a3 DK |
5176 | struct hc_sp_status_block_data *sp_sb_data) |
5177 | { | |
5178 | int func = BP_FUNC(bp); | |
5179 | int i; | |
5180 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
5181 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5182 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
5183 | i*sizeof(u32), | |
5184 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
5185 | } |
5186 | ||
1191cb83 | 5187 | static void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
5188 | { |
5189 | int func = BP_FUNC(bp); | |
523224a3 DK |
5190 | struct hc_sp_status_block_data sp_sb_data; |
5191 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 5192 | |
619c5cb6 | 5193 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
5194 | sp_sb_data.p_func.vf_valid = false; |
5195 | ||
5196 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
5197 | ||
5198 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5199 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
5200 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
5201 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5202 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
5203 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
5204 | ||
5205 | } | |
5206 | ||
5207 | ||
1191cb83 | 5208 | static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, |
523224a3 DK |
5209 | int igu_sb_id, int igu_seg_id) |
5210 | { | |
5211 | hc_sm->igu_sb_id = igu_sb_id; | |
5212 | hc_sm->igu_seg_id = igu_seg_id; | |
5213 | hc_sm->timer_value = 0xFF; | |
5214 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
5215 | } |
5216 | ||
150966ad AE |
5217 | |
5218 | /* allocates state machine ids. */ | |
1191cb83 | 5219 | static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) |
150966ad AE |
5220 | { |
5221 | /* zero out state machine indices */ | |
5222 | /* rx indices */ | |
5223 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5224 | ||
5225 | /* tx indices */ | |
5226 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5227 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
5228 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
5229 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
5230 | ||
5231 | /* map indices */ | |
5232 | /* rx indices */ | |
5233 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
5234 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5235 | ||
5236 | /* tx indices */ | |
5237 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
5238 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5239 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
5240 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5241 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
5242 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5243 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
5244 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5245 | } | |
5246 | ||
8d96286a | 5247 | static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 5248 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 5249 | { |
523224a3 DK |
5250 | int igu_seg_id; |
5251 | ||
f2e0899f | 5252 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
5253 | struct hc_status_block_data_e1x sb_data_e1x; |
5254 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
5255 | int data_size; |
5256 | u32 *sb_data_p; | |
5257 | ||
f2e0899f DK |
5258 | if (CHIP_INT_MODE_IS_BC(bp)) |
5259 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
5260 | else | |
5261 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
5262 | |
5263 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
5264 | ||
619c5cb6 | 5265 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5266 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5267 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
5268 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
5269 | sb_data_e2.common.p_func.vf_id = vfid; | |
5270 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
5271 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
5272 | sb_data_e2.common.same_igu_sb_1b = true; | |
5273 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
5274 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
5275 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
5276 | sb_data_p = (u32 *)&sb_data_e2; |
5277 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 5278 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
5279 | } else { |
5280 | memset(&sb_data_e1x, 0, | |
5281 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5282 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
5283 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
5284 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
5285 | sb_data_e1x.common.p_func.vf_valid = false; | |
5286 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
5287 | sb_data_e1x.common.same_igu_sb_1b = true; | |
5288 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
5289 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
5290 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
5291 | sb_data_p = (u32 *)&sb_data_e1x; |
5292 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 5293 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 5294 | } |
523224a3 DK |
5295 | |
5296 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
5297 | igu_sb_id, igu_seg_id); | |
5298 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
5299 | igu_sb_id, igu_seg_id); | |
5300 | ||
51c1a580 | 5301 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
523224a3 DK |
5302 | |
5303 | /* write indecies to HW */ | |
5304 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); | |
5305 | } | |
5306 | ||
619c5cb6 | 5307 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
5308 | u16 tx_usec, u16 rx_usec) |
5309 | { | |
6383c0b3 | 5310 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 5311 | false, rx_usec); |
6383c0b3 AE |
5312 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
5313 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
5314 | tx_usec); | |
5315 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5316 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
5317 | tx_usec); | |
5318 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5319 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
5320 | tx_usec); | |
523224a3 | 5321 | } |
f2e0899f | 5322 | |
523224a3 DK |
5323 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
5324 | { | |
5325 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
5326 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
5327 | int igu_sp_sb_index; | |
5328 | int igu_seg_id; | |
34f80b04 EG |
5329 | int port = BP_PORT(bp); |
5330 | int func = BP_FUNC(bp); | |
f2eaeb58 | 5331 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 5332 | u64 section; |
523224a3 DK |
5333 | int index; |
5334 | struct hc_sp_status_block_data sp_sb_data; | |
5335 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
5336 | ||
f2e0899f DK |
5337 | if (CHIP_INT_MODE_IS_BC(bp)) { |
5338 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
5339 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
5340 | } else { | |
5341 | igu_sp_sb_index = bp->igu_dsb_id; | |
5342 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
5343 | } | |
a2fbb9ea ET |
5344 | |
5345 | /* ATTN */ | |
523224a3 | 5346 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 5347 | atten_status_block); |
523224a3 | 5348 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 5349 | |
49d66772 ET |
5350 | bp->attn_state = 0; |
5351 | ||
a2fbb9ea ET |
5352 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
5353 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
5354 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
5355 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 5356 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
5357 | int sindex; |
5358 | /* take care of sig[0]..sig[4] */ | |
5359 | for (sindex = 0; sindex < 4; sindex++) | |
5360 | bp->attn_group[index].sig[sindex] = | |
5361 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 5362 | |
619c5cb6 | 5363 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5364 | /* |
5365 | * enable5 is separate from the rest of the registers, | |
5366 | * and therefore the address skip is 4 | |
5367 | * and not 16 between the different groups | |
5368 | */ | |
5369 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 5370 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
5371 | else |
5372 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
5373 | } |
5374 | ||
f2e0899f DK |
5375 | if (bp->common.int_block == INT_BLOCK_HC) { |
5376 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
5377 | HC_REG_ATTN_MSG0_ADDR_L); | |
5378 | ||
5379 | REG_WR(bp, reg_offset, U64_LO(section)); | |
5380 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 5381 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5382 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
5383 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
5384 | } | |
a2fbb9ea | 5385 | |
523224a3 DK |
5386 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
5387 | sp_sb); | |
a2fbb9ea | 5388 | |
523224a3 | 5389 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 5390 | |
619c5cb6 | 5391 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
5392 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
5393 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
5394 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
5395 | sp_sb_data.igu_seg_id = igu_seg_id; | |
5396 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 5397 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 5398 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 5399 | |
523224a3 | 5400 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 5401 | |
523224a3 | 5402 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
5403 | } |
5404 | ||
9f6c9258 | 5405 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 5406 | { |
a2fbb9ea ET |
5407 | int i; |
5408 | ||
ec6ba945 | 5409 | for_each_eth_queue(bp, i) |
523224a3 | 5410 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 5411 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
5412 | } |
5413 | ||
a2fbb9ea ET |
5414 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
5415 | { | |
a2fbb9ea | 5416 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 5417 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 5418 | |
a2fbb9ea | 5419 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
5420 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
5421 | bp->spq_prod_bd = bp->spq; | |
5422 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
5423 | } |
5424 | ||
523224a3 | 5425 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
5426 | { |
5427 | int i; | |
523224a3 DK |
5428 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
5429 | union event_ring_elem *elem = | |
5430 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 5431 | |
523224a3 DK |
5432 | elem->next_page.addr.hi = |
5433 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
5434 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
5435 | elem->next_page.addr.lo = | |
5436 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
5437 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 5438 | } |
523224a3 DK |
5439 | bp->eq_cons = 0; |
5440 | bp->eq_prod = NUM_EQ_DESC; | |
5441 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
6e30dd4e VZ |
5442 | /* we want a warning message before it gets rought... */ |
5443 | atomic_set(&bp->eq_spq_left, | |
5444 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
5445 | } |
5446 | ||
619c5cb6 VZ |
5447 | |
5448 | /* called with netif_addr_lock_bh() */ | |
5449 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, | |
5450 | unsigned long rx_mode_flags, | |
5451 | unsigned long rx_accept_flags, | |
5452 | unsigned long tx_accept_flags, | |
5453 | unsigned long ramrod_flags) | |
ab532cf3 | 5454 | { |
619c5cb6 VZ |
5455 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
5456 | int rc; | |
5457 | ||
5458 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
5459 | ||
5460 | /* Prepare ramrod parameters */ | |
5461 | ramrod_param.cid = 0; | |
5462 | ramrod_param.cl_id = cl_id; | |
5463 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
5464 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 5465 | |
619c5cb6 VZ |
5466 | ramrod_param.pstate = &bp->sp_state; |
5467 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 5468 | |
619c5cb6 VZ |
5469 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
5470 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
5471 | ||
5472 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5473 | ||
5474 | ramrod_param.ramrod_flags = ramrod_flags; | |
5475 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
5476 | ||
5477 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
5478 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
5479 | ||
5480 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
5481 | if (rc < 0) { | |
5482 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
5483 | return; | |
5484 | } | |
a2fbb9ea ET |
5485 | } |
5486 | ||
619c5cb6 VZ |
5487 | /* called with netif_addr_lock_bh() */ |
5488 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |
471de716 | 5489 | { |
619c5cb6 VZ |
5490 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; |
5491 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
471de716 | 5492 | |
619c5cb6 VZ |
5493 | #ifdef BCM_CNIC |
5494 | if (!NO_FCOE(bp)) | |
5495 | ||
5496 | /* Configure rx_mode of FCoE Queue */ | |
5497 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
5498 | #endif | |
5499 | ||
5500 | switch (bp->rx_mode) { | |
5501 | case BNX2X_RX_MODE_NONE: | |
5502 | /* | |
5503 | * 'drop all' supersedes any accept flags that may have been | |
5504 | * passed to the function. | |
5505 | */ | |
5506 | break; | |
5507 | case BNX2X_RX_MODE_NORMAL: | |
5508 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5509 | __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); | |
5510 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5511 | ||
5512 | /* internal switching mode */ | |
5513 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5514 | __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); | |
5515 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5516 | ||
5517 | break; | |
5518 | case BNX2X_RX_MODE_ALLMULTI: | |
5519 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5520 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5521 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5522 | ||
5523 | /* internal switching mode */ | |
5524 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5525 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5526 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5527 | ||
5528 | break; | |
5529 | case BNX2X_RX_MODE_PROMISC: | |
5530 | /* According to deffinition of SI mode, iface in promisc mode | |
5531 | * should receive matched and unmatched (in resolution of port) | |
5532 | * unicast packets. | |
5533 | */ | |
5534 | __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); | |
5535 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5536 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5537 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5538 | ||
5539 | /* internal switching mode */ | |
5540 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5541 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5542 | ||
5543 | if (IS_MF_SI(bp)) | |
5544 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); | |
5545 | else | |
5546 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5547 | ||
5548 | break; | |
5549 | default: | |
5550 | BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); | |
5551 | return; | |
5552 | } | |
de832a55 | 5553 | |
619c5cb6 VZ |
5554 | if (bp->rx_mode != BNX2X_RX_MODE_NONE) { |
5555 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); | |
5556 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); | |
34f80b04 EG |
5557 | } |
5558 | ||
619c5cb6 VZ |
5559 | __set_bit(RAMROD_RX, &ramrod_flags); |
5560 | __set_bit(RAMROD_TX, &ramrod_flags); | |
5561 | ||
5562 | bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, | |
5563 | tx_accept_flags, ramrod_flags); | |
5564 | } | |
5565 | ||
5566 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
5567 | { | |
5568 | int i; | |
5569 | ||
0793f83f DK |
5570 | if (IS_MF_SI(bp)) |
5571 | /* | |
5572 | * In switch independent mode, the TSTORM needs to accept | |
5573 | * packets that failed classification, since approximate match | |
5574 | * mac addresses aren't written to NIG LLH | |
5575 | */ | |
5576 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5577 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); | |
619c5cb6 VZ |
5578 | else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ |
5579 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5580 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); | |
0793f83f | 5581 | |
523224a3 DK |
5582 | /* Zero this manually as its initialization is |
5583 | currently missing in the initTool */ | |
5584 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 5585 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 5586 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 5587 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5588 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
5589 | CHIP_INT_MODE_IS_BC(bp) ? | |
5590 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
5591 | } | |
523224a3 | 5592 | } |
8a1c38d1 | 5593 | |
471de716 EG |
5594 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
5595 | { | |
5596 | switch (load_code) { | |
5597 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 5598 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
5599 | bnx2x_init_internal_common(bp); |
5600 | /* no break */ | |
5601 | ||
5602 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 5603 | /* nothing to do */ |
471de716 EG |
5604 | /* no break */ |
5605 | ||
5606 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
5607 | /* internal memory per function is |
5608 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
5609 | break; |
5610 | ||
5611 | default: | |
5612 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
5613 | break; | |
5614 | } | |
5615 | } | |
5616 | ||
619c5cb6 | 5617 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 5618 | { |
6383c0b3 | 5619 | return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; |
619c5cb6 | 5620 | } |
523224a3 | 5621 | |
619c5cb6 VZ |
5622 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
5623 | { | |
6383c0b3 | 5624 | return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; |
619c5cb6 VZ |
5625 | } |
5626 | ||
1191cb83 | 5627 | static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) |
619c5cb6 VZ |
5628 | { |
5629 | if (CHIP_IS_E1x(fp->bp)) | |
5630 | return BP_L_ID(fp->bp) + fp->index; | |
5631 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
5632 | return bnx2x_fp_igu_sb_id(fp); | |
5633 | } | |
5634 | ||
6383c0b3 | 5635 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
5636 | { |
5637 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 5638 | u8 cos; |
619c5cb6 | 5639 | unsigned long q_type = 0; |
6383c0b3 | 5640 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 5641 | fp->rx_queue = fp_idx; |
b3b83c3f | 5642 | fp->cid = fp_idx; |
619c5cb6 VZ |
5643 | fp->cl_id = bnx2x_fp_cl_id(fp); |
5644 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
5645 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 5646 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
5647 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
5648 | ||
523224a3 | 5649 | /* init shortcut */ |
619c5cb6 | 5650 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
7a752993 | 5651 | |
523224a3 DK |
5652 | /* Setup SB indicies */ |
5653 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; | |
523224a3 | 5654 | |
619c5cb6 VZ |
5655 | /* Configure Queue State object */ |
5656 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
5657 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
5658 | |
5659 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
5660 | ||
5661 | /* init tx data */ | |
5662 | for_each_cos_in_tx_queue(fp, cos) { | |
65565884 MS |
5663 | bnx2x_init_txdata(bp, fp->txdata_ptr[cos], |
5664 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), | |
5665 | FP_COS_TO_TXQ(fp, cos, bp), | |
5666 | BNX2X_TX_SB_INDEX_BASE + cos, fp); | |
5667 | cids[cos] = fp->txdata_ptr[cos]->cid; | |
6383c0b3 AE |
5668 | } |
5669 | ||
15192a8c BW |
5670 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, |
5671 | fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 5672 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 VZ |
5673 | |
5674 | /** | |
5675 | * Configure classification DBs: Always enable Tx switching | |
5676 | */ | |
5677 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
5678 | ||
51c1a580 | 5679 | DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", |
619c5cb6 | 5680 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, |
523224a3 DK |
5681 | fp->igu_sb_id); |
5682 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
5683 | fp->fw_sb_id, fp->igu_sb_id); | |
5684 | ||
5685 | bnx2x_update_fpsb_idx(fp); | |
5686 | } | |
5687 | ||
1191cb83 ED |
5688 | static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) |
5689 | { | |
5690 | int i; | |
5691 | ||
5692 | for (i = 1; i <= NUM_TX_RINGS; i++) { | |
5693 | struct eth_tx_next_bd *tx_next_bd = | |
5694 | &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
5695 | ||
5696 | tx_next_bd->addr_hi = | |
5697 | cpu_to_le32(U64_HI(txdata->tx_desc_mapping + | |
5698 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
5699 | tx_next_bd->addr_lo = | |
5700 | cpu_to_le32(U64_LO(txdata->tx_desc_mapping + | |
5701 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
5702 | } | |
5703 | ||
5704 | SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); | |
5705 | txdata->tx_db.data.zero_fill1 = 0; | |
5706 | txdata->tx_db.data.prod = 0; | |
5707 | ||
5708 | txdata->tx_pkt_prod = 0; | |
5709 | txdata->tx_pkt_cons = 0; | |
5710 | txdata->tx_bd_prod = 0; | |
5711 | txdata->tx_bd_cons = 0; | |
5712 | txdata->tx_pkt = 0; | |
5713 | } | |
5714 | ||
5715 | static void bnx2x_init_tx_rings(struct bnx2x *bp) | |
5716 | { | |
5717 | int i; | |
5718 | u8 cos; | |
5719 | ||
5720 | for_each_tx_queue(bp, i) | |
5721 | for_each_cos_in_tx_queue(&bp->fp[i], cos) | |
65565884 | 5722 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); |
1191cb83 ED |
5723 | } |
5724 | ||
9f6c9258 | 5725 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) |
a2fbb9ea ET |
5726 | { |
5727 | int i; | |
5728 | ||
ec6ba945 | 5729 | for_each_eth_queue(bp, i) |
6383c0b3 | 5730 | bnx2x_init_eth_fp(bp, i); |
37b091ba | 5731 | #ifdef BCM_CNIC |
ec6ba945 VZ |
5732 | if (!NO_FCOE(bp)) |
5733 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
5734 | |
5735 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
5736 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 5737 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 5738 | |
37b091ba | 5739 | #endif |
a2fbb9ea | 5740 | |
020c7e3f YR |
5741 | /* Initialize MOD_ABS interrupts */ |
5742 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
5743 | bp->common.shmem_base, bp->common.shmem2_base, | |
5744 | BP_PORT(bp)); | |
16119785 EG |
5745 | /* ensure status block indices were read */ |
5746 | rmb(); | |
5747 | ||
523224a3 | 5748 | bnx2x_init_def_sb(bp); |
5c862848 | 5749 | bnx2x_update_dsb_idx(bp); |
a2fbb9ea | 5750 | bnx2x_init_rx_rings(bp); |
523224a3 | 5751 | bnx2x_init_tx_rings(bp); |
a2fbb9ea | 5752 | bnx2x_init_sp_ring(bp); |
523224a3 | 5753 | bnx2x_init_eq_ring(bp); |
471de716 | 5754 | bnx2x_init_internal(bp, load_code); |
523224a3 | 5755 | bnx2x_pf_init(bp); |
0ef00459 EG |
5756 | bnx2x_stats_init(bp); |
5757 | ||
0ef00459 EG |
5758 | /* flush all before enabling interrupts */ |
5759 | mb(); | |
5760 | mmiowb(); | |
5761 | ||
615f8fd9 | 5762 | bnx2x_int_enable(bp); |
eb8da205 EG |
5763 | |
5764 | /* Check for SPIO5 */ | |
5765 | bnx2x_attn_int_deasserted0(bp, | |
5766 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
5767 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
5768 | } |
5769 | ||
5770 | /* end of nic init */ | |
5771 | ||
5772 | /* | |
5773 | * gzip service functions | |
5774 | */ | |
5775 | ||
5776 | static int bnx2x_gunzip_init(struct bnx2x *bp) | |
5777 | { | |
1a983142 FT |
5778 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
5779 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
5780 | if (bp->gunzip_buf == NULL) |
5781 | goto gunzip_nomem1; | |
5782 | ||
5783 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
5784 | if (bp->strm == NULL) | |
5785 | goto gunzip_nomem2; | |
5786 | ||
7ab24bfd | 5787 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
5788 | if (bp->strm->workspace == NULL) |
5789 | goto gunzip_nomem3; | |
5790 | ||
5791 | return 0; | |
5792 | ||
5793 | gunzip_nomem3: | |
5794 | kfree(bp->strm); | |
5795 | bp->strm = NULL; | |
5796 | ||
5797 | gunzip_nomem2: | |
1a983142 FT |
5798 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5799 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5800 | bp->gunzip_buf = NULL; |
5801 | ||
5802 | gunzip_nomem1: | |
51c1a580 | 5803 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
a2fbb9ea ET |
5804 | return -ENOMEM; |
5805 | } | |
5806 | ||
5807 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
5808 | { | |
b3b83c3f | 5809 | if (bp->strm) { |
7ab24bfd | 5810 | vfree(bp->strm->workspace); |
b3b83c3f DK |
5811 | kfree(bp->strm); |
5812 | bp->strm = NULL; | |
5813 | } | |
a2fbb9ea ET |
5814 | |
5815 | if (bp->gunzip_buf) { | |
1a983142 FT |
5816 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5817 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5818 | bp->gunzip_buf = NULL; |
5819 | } | |
5820 | } | |
5821 | ||
94a78b79 | 5822 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
5823 | { |
5824 | int n, rc; | |
5825 | ||
5826 | /* check gzip header */ | |
94a78b79 VZ |
5827 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
5828 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 5829 | return -EINVAL; |
94a78b79 | 5830 | } |
a2fbb9ea ET |
5831 | |
5832 | n = 10; | |
5833 | ||
34f80b04 | 5834 | #define FNAME 0x8 |
a2fbb9ea ET |
5835 | |
5836 | if (zbuf[3] & FNAME) | |
5837 | while ((zbuf[n++] != 0) && (n < len)); | |
5838 | ||
94a78b79 | 5839 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
5840 | bp->strm->avail_in = len - n; |
5841 | bp->strm->next_out = bp->gunzip_buf; | |
5842 | bp->strm->avail_out = FW_BUF_SIZE; | |
5843 | ||
5844 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
5845 | if (rc != Z_OK) | |
5846 | return rc; | |
5847 | ||
5848 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
5849 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
5850 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
5851 | bp->strm->msg); | |
a2fbb9ea ET |
5852 | |
5853 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
5854 | if (bp->gunzip_outlen & 0x3) | |
51c1a580 MS |
5855 | netdev_err(bp->dev, |
5856 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", | |
cdaa7cb8 | 5857 | bp->gunzip_outlen); |
a2fbb9ea ET |
5858 | bp->gunzip_outlen >>= 2; |
5859 | ||
5860 | zlib_inflateEnd(bp->strm); | |
5861 | ||
5862 | if (rc == Z_STREAM_END) | |
5863 | return 0; | |
5864 | ||
5865 | return rc; | |
5866 | } | |
5867 | ||
5868 | /* nic load/unload */ | |
5869 | ||
5870 | /* | |
34f80b04 | 5871 | * General service functions |
a2fbb9ea ET |
5872 | */ |
5873 | ||
5874 | /* send a NIG loopback debug packet */ | |
5875 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
5876 | { | |
a2fbb9ea | 5877 | u32 wb_write[3]; |
a2fbb9ea ET |
5878 | |
5879 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
5880 | wb_write[0] = 0x55555555; |
5881 | wb_write[1] = 0x55555555; | |
34f80b04 | 5882 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 5883 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5884 | |
5885 | /* NON-IP protocol */ | |
a2fbb9ea ET |
5886 | wb_write[0] = 0x09000000; |
5887 | wb_write[1] = 0x55555555; | |
34f80b04 | 5888 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 5889 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5890 | } |
5891 | ||
5892 | /* some of the internal memories | |
5893 | * are not directly readable from the driver | |
5894 | * to test them we send debug packets | |
5895 | */ | |
5896 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
5897 | { | |
5898 | int factor; | |
5899 | int count, i; | |
5900 | u32 val = 0; | |
5901 | ||
ad8d3948 | 5902 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 5903 | factor = 120; |
ad8d3948 EG |
5904 | else if (CHIP_REV_IS_EMUL(bp)) |
5905 | factor = 200; | |
5906 | else | |
a2fbb9ea | 5907 | factor = 1; |
a2fbb9ea | 5908 | |
a2fbb9ea ET |
5909 | /* Disable inputs of parser neighbor blocks */ |
5910 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5911 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5912 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5913 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5914 | |
5915 | /* Write 0 to parser credits for CFC search request */ | |
5916 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5917 | ||
5918 | /* send Ethernet packet */ | |
5919 | bnx2x_lb_pckt(bp); | |
5920 | ||
5921 | /* TODO do i reset NIG statistic? */ | |
5922 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
5923 | count = 1000 * factor; | |
5924 | while (count) { | |
34f80b04 | 5925 | |
a2fbb9ea ET |
5926 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5927 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5928 | if (val == 0x10) |
5929 | break; | |
5930 | ||
5931 | msleep(10); | |
5932 | count--; | |
5933 | } | |
5934 | if (val != 0x10) { | |
5935 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5936 | return -1; | |
5937 | } | |
5938 | ||
5939 | /* Wait until PRS register shows 1 packet */ | |
5940 | count = 1000 * factor; | |
5941 | while (count) { | |
5942 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
5943 | if (val == 1) |
5944 | break; | |
5945 | ||
5946 | msleep(10); | |
5947 | count--; | |
5948 | } | |
5949 | if (val != 0x1) { | |
5950 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5951 | return -2; | |
5952 | } | |
5953 | ||
5954 | /* Reset and init BRB, PRS */ | |
34f80b04 | 5955 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 5956 | msleep(50); |
34f80b04 | 5957 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 5958 | msleep(50); |
619c5cb6 VZ |
5959 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
5960 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
5961 | |
5962 | DP(NETIF_MSG_HW, "part2\n"); | |
5963 | ||
5964 | /* Disable inputs of parser neighbor blocks */ | |
5965 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5966 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5967 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5968 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5969 | |
5970 | /* Write 0 to parser credits for CFC search request */ | |
5971 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5972 | ||
5973 | /* send 10 Ethernet packets */ | |
5974 | for (i = 0; i < 10; i++) | |
5975 | bnx2x_lb_pckt(bp); | |
5976 | ||
5977 | /* Wait until NIG register shows 10 + 1 | |
5978 | packets of size 11*0x10 = 0xb0 */ | |
5979 | count = 1000 * factor; | |
5980 | while (count) { | |
34f80b04 | 5981 | |
a2fbb9ea ET |
5982 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5983 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5984 | if (val == 0xb0) |
5985 | break; | |
5986 | ||
5987 | msleep(10); | |
5988 | count--; | |
5989 | } | |
5990 | if (val != 0xb0) { | |
5991 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5992 | return -3; | |
5993 | } | |
5994 | ||
5995 | /* Wait until PRS register shows 2 packets */ | |
5996 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
5997 | if (val != 2) | |
5998 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5999 | ||
6000 | /* Write 1 to parser credits for CFC search request */ | |
6001 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
6002 | ||
6003 | /* Wait until PRS register shows 3 packets */ | |
6004 | msleep(10 * factor); | |
6005 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6006 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6007 | if (val != 3) | |
6008 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6009 | ||
6010 | /* clear NIG EOP FIFO */ | |
6011 | for (i = 0; i < 11; i++) | |
6012 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
6013 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
6014 | if (val != 1) { | |
6015 | BNX2X_ERR("clear of NIG failed\n"); | |
6016 | return -4; | |
6017 | } | |
6018 | ||
6019 | /* Reset and init BRB, PRS, NIG */ | |
6020 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
6021 | msleep(50); | |
6022 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
6023 | msleep(50); | |
619c5cb6 VZ |
6024 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6025 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
37b091ba | 6026 | #ifndef BCM_CNIC |
a2fbb9ea ET |
6027 | /* set NIC mode */ |
6028 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6029 | #endif | |
6030 | ||
6031 | /* Enable inputs of parser neighbor blocks */ | |
6032 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
6033 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
6034 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 6035 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
6036 | |
6037 | DP(NETIF_MSG_HW, "done\n"); | |
6038 | ||
6039 | return 0; /* OK */ | |
6040 | } | |
6041 | ||
4a33bc03 | 6042 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea ET |
6043 | { |
6044 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
619c5cb6 | 6045 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6046 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
6047 | else | |
6048 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
6049 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
6050 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
6051 | /* |
6052 | * mask read length error interrupts in brb for parser | |
6053 | * (parsing unit and 'checksum and crc' unit) | |
6054 | * these errors are legal (PU reads fixed length and CAC can cause | |
6055 | * read length error on truncated packets) | |
6056 | */ | |
6057 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
6058 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
6059 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
6060 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
6061 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
6062 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
6063 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
6064 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6065 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
6066 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
6067 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
6068 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
6069 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6070 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
6071 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
6072 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
6073 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
6074 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
6075 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 6076 | |
34f80b04 EG |
6077 | if (CHIP_REV_IS_FPGA(bp)) |
6078 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); | |
619c5cb6 | 6079 | else if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6080 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, |
6081 | (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | |
6082 | | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
6083 | | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN | |
6084 | | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | |
6085 | | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); | |
34f80b04 EG |
6086 | else |
6087 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); | |
a2fbb9ea ET |
6088 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
6089 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
6090 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 6091 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
6092 | |
6093 | if (!CHIP_IS_E1x(bp)) | |
6094 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
6095 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
6096 | ||
a2fbb9ea ET |
6097 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
6098 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 6099 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 6100 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
6101 | } |
6102 | ||
81f75bbf EG |
6103 | static void bnx2x_reset_common(struct bnx2x *bp) |
6104 | { | |
619c5cb6 VZ |
6105 | u32 val = 0x1400; |
6106 | ||
81f75bbf EG |
6107 | /* reset_common */ |
6108 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6109 | 0xd3ffff7f); | |
619c5cb6 VZ |
6110 | |
6111 | if (CHIP_IS_E3(bp)) { | |
6112 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6113 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6114 | } | |
6115 | ||
6116 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
6117 | } | |
6118 | ||
6119 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
6120 | { | |
6121 | bp->dmae_ready = 0; | |
6122 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
6123 | } |
6124 | ||
573f2035 EG |
6125 | static void bnx2x_init_pxp(struct bnx2x *bp) |
6126 | { | |
6127 | u16 devctl; | |
6128 | int r_order, w_order; | |
6129 | ||
6130 | pci_read_config_word(bp->pdev, | |
b6c2f86e | 6131 | pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
6132 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
6133 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
6134 | if (bp->mrrs == -1) | |
6135 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
6136 | else { | |
6137 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
6138 | r_order = bp->mrrs; | |
6139 | } | |
6140 | ||
6141 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
6142 | } | |
fd4ef40d EG |
6143 | |
6144 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
6145 | { | |
2145a920 | 6146 | int is_required; |
fd4ef40d | 6147 | u32 val; |
2145a920 | 6148 | int port; |
fd4ef40d | 6149 | |
2145a920 VZ |
6150 | if (BP_NOMCP(bp)) |
6151 | return; | |
6152 | ||
6153 | is_required = 0; | |
fd4ef40d EG |
6154 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
6155 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
6156 | ||
6157 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
6158 | is_required = 1; | |
6159 | ||
6160 | /* | |
6161 | * The fan failure mechanism is usually related to the PHY type since | |
6162 | * the power consumption of the board is affected by the PHY. Currently, | |
6163 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
6164 | */ | |
6165 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
6166 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 6167 | is_required |= |
d90d96ba YR |
6168 | bnx2x_fan_failure_det_req( |
6169 | bp, | |
6170 | bp->common.shmem_base, | |
a22f0788 | 6171 | bp->common.shmem2_base, |
d90d96ba | 6172 | port); |
fd4ef40d EG |
6173 | } |
6174 | ||
6175 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
6176 | ||
6177 | if (is_required == 0) | |
6178 | return; | |
6179 | ||
6180 | /* Fan failure is indicated by SPIO 5 */ | |
6181 | bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, | |
6182 | MISC_REGISTERS_SPIO_INPUT_HI_Z); | |
6183 | ||
6184 | /* set to active low mode */ | |
6185 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
6186 | val |= ((1 << MISC_REGISTERS_SPIO_5) << | |
cdaa7cb8 | 6187 | MISC_REGISTERS_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
6188 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
6189 | ||
6190 | /* enable interrupt to signal the IGU */ | |
6191 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
6192 | val |= (1 << MISC_REGISTERS_SPIO_5); | |
6193 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); | |
6194 | } | |
6195 | ||
f2e0899f DK |
6196 | static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) |
6197 | { | |
6198 | u32 offset = 0; | |
6199 | ||
6200 | if (CHIP_IS_E1(bp)) | |
6201 | return; | |
6202 | if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) | |
6203 | return; | |
6204 | ||
6205 | switch (BP_ABS_FUNC(bp)) { | |
6206 | case 0: | |
6207 | offset = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
6208 | break; | |
6209 | case 1: | |
6210 | offset = PXP2_REG_PGL_PRETEND_FUNC_F1; | |
6211 | break; | |
6212 | case 2: | |
6213 | offset = PXP2_REG_PGL_PRETEND_FUNC_F2; | |
6214 | break; | |
6215 | case 3: | |
6216 | offset = PXP2_REG_PGL_PRETEND_FUNC_F3; | |
6217 | break; | |
6218 | case 4: | |
6219 | offset = PXP2_REG_PGL_PRETEND_FUNC_F4; | |
6220 | break; | |
6221 | case 5: | |
6222 | offset = PXP2_REG_PGL_PRETEND_FUNC_F5; | |
6223 | break; | |
6224 | case 6: | |
6225 | offset = PXP2_REG_PGL_PRETEND_FUNC_F6; | |
6226 | break; | |
6227 | case 7: | |
6228 | offset = PXP2_REG_PGL_PRETEND_FUNC_F7; | |
6229 | break; | |
6230 | default: | |
6231 | return; | |
6232 | } | |
6233 | ||
6234 | REG_WR(bp, offset, pretend_func_num); | |
6235 | REG_RD(bp, offset); | |
6236 | DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); | |
6237 | } | |
6238 | ||
c9ee9206 | 6239 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
6240 | { |
6241 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
6242 | val &= ~IGU_PF_CONF_FUNC_EN; | |
6243 | ||
6244 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
6245 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6246 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
6247 | } | |
6248 | ||
1191cb83 | 6249 | static void bnx2x__common_init_phy(struct bnx2x *bp) |
619c5cb6 VZ |
6250 | { |
6251 | u32 shmem_base[2], shmem2_base[2]; | |
6252 | shmem_base[0] = bp->common.shmem_base; | |
6253 | shmem2_base[0] = bp->common.shmem2_base; | |
6254 | if (!CHIP_IS_E1x(bp)) { | |
6255 | shmem_base[1] = | |
6256 | SHMEM2_RD(bp, other_shmem_base_addr); | |
6257 | shmem2_base[1] = | |
6258 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
6259 | } | |
6260 | bnx2x_acquire_phy_lock(bp); | |
6261 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
6262 | bp->common.chip_id); | |
6263 | bnx2x_release_phy_lock(bp); | |
6264 | } | |
6265 | ||
6266 | /** | |
6267 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
6268 | * | |
6269 | * @bp: driver handle | |
6270 | */ | |
6271 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 6272 | { |
619c5cb6 | 6273 | u32 val; |
a2fbb9ea | 6274 | |
51c1a580 | 6275 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 6276 | |
2031bd3a DK |
6277 | /* |
6278 | * take the UNDI lock to protect undi_unload flow from accessing | |
6279 | * registers while we're resetting the chip | |
6280 | */ | |
7a06a122 | 6281 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6282 | |
81f75bbf | 6283 | bnx2x_reset_common(bp); |
34f80b04 | 6284 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 6285 | |
619c5cb6 VZ |
6286 | val = 0xfffc; |
6287 | if (CHIP_IS_E3(bp)) { | |
6288 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6289 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6290 | } | |
6291 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
6292 | ||
7a06a122 | 6293 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6294 | |
619c5cb6 | 6295 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 6296 | |
619c5cb6 VZ |
6297 | if (!CHIP_IS_E1x(bp)) { |
6298 | u8 abs_func_id; | |
f2e0899f DK |
6299 | |
6300 | /** | |
6301 | * 4-port mode or 2-port mode we need to turn of master-enable | |
6302 | * for everyone, after that, turn it back on for self. | |
6303 | * so, we disregard multi-function or not, and always disable | |
6304 | * for all functions on the given path, this means 0,2,4,6 for | |
6305 | * path 0 and 1,3,5,7 for path 1 | |
6306 | */ | |
619c5cb6 VZ |
6307 | for (abs_func_id = BP_PATH(bp); |
6308 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
6309 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
6310 | REG_WR(bp, |
6311 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
6312 | 1); | |
6313 | continue; | |
6314 | } | |
6315 | ||
619c5cb6 | 6316 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
6317 | /* clear pf enable */ |
6318 | bnx2x_pf_disable(bp); | |
6319 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6320 | } | |
6321 | } | |
a2fbb9ea | 6322 | |
619c5cb6 | 6323 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
6324 | if (CHIP_IS_E1(bp)) { |
6325 | /* enable HW interrupt from PXP on USDM overflow | |
6326 | bit 16 on INT_MASK_0 */ | |
6327 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
6328 | } | |
a2fbb9ea | 6329 | |
619c5cb6 | 6330 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 6331 | bnx2x_init_pxp(bp); |
a2fbb9ea ET |
6332 | |
6333 | #ifdef __BIG_ENDIAN | |
34f80b04 EG |
6334 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); |
6335 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); | |
6336 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); | |
6337 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); | |
6338 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); | |
8badd27a EG |
6339 | /* make sure this value is 0 */ |
6340 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
34f80b04 EG |
6341 | |
6342 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ | |
6343 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); | |
6344 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); | |
6345 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); | |
6346 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); | |
a2fbb9ea ET |
6347 | #endif |
6348 | ||
523224a3 DK |
6349 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
6350 | ||
34f80b04 EG |
6351 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
6352 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 6353 | |
34f80b04 EG |
6354 | /* let the HW do it's magic ... */ |
6355 | msleep(100); | |
6356 | /* finish PXP init */ | |
6357 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
6358 | if (val != 1) { | |
6359 | BNX2X_ERR("PXP2 CFG failed\n"); | |
6360 | return -EBUSY; | |
6361 | } | |
6362 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
6363 | if (val != 1) { | |
6364 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
6365 | return -EBUSY; | |
6366 | } | |
a2fbb9ea | 6367 | |
f2e0899f DK |
6368 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
6369 | * have entries with value "0" and valid bit on. | |
6370 | * This needs to be done by the first PF that is loaded in a path | |
6371 | * (i.e. common phase) | |
6372 | */ | |
619c5cb6 VZ |
6373 | if (!CHIP_IS_E1x(bp)) { |
6374 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
6375 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
6376 | * This occurs when a different function (func2,3) is being marked | |
6377 | * as "scan-off". Real-life scenario for example: if a driver is being | |
6378 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
6379 | * the ilt, translate to a logical address and send a request to read/write. | |
6380 | * Since the ilt for the function that is down is not valid, this will cause | |
6381 | * a translation error which is unrecoverable. | |
6382 | * The Workaround is intended to make sure that when this happens nothing fatal | |
6383 | * will occur. The workaround: | |
6384 | * 1. First PF driver which loads on a path will: | |
6385 | * a. After taking the chip out of reset, by using pretend, | |
6386 | * it will write "0" to the following registers of | |
6387 | * the other vnics. | |
6388 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6389 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
6390 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
6391 | * And for itself it will write '1' to | |
6392 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
6393 | * dmae-operations (writing to pram for example.) | |
6394 | * note: can be done for only function 6,7 but cleaner this | |
6395 | * way. | |
6396 | * b. Write zero+valid to the entire ILT. | |
6397 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
6398 | * VNIC3 (of that port). The range allocated will be the | |
6399 | * entire ILT. This is needed to prevent ILT range error. | |
6400 | * 2. Any PF driver load flow: | |
6401 | * a. ILT update with the physical addresses of the allocated | |
6402 | * logical pages. | |
6403 | * b. Wait 20msec. - note that this timeout is needed to make | |
6404 | * sure there are no requests in one of the PXP internal | |
6405 | * queues with "old" ILT addresses. | |
6406 | * c. PF enable in the PGLC. | |
6407 | * d. Clear the was_error of the PF in the PGLC. (could have | |
6408 | * occured while driver was down) | |
6409 | * e. PF enable in the CFC (WEAK + STRONG) | |
6410 | * f. Timers scan enable | |
6411 | * 3. PF driver unload flow: | |
6412 | * a. Clear the Timers scan_en. | |
6413 | * b. Polling for scan_on=0 for that PF. | |
6414 | * c. Clear the PF enable bit in the PXP. | |
6415 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
6416 | * e. Write zero+valid to all ILT entries (The valid bit must | |
6417 | * stay set) | |
6418 | * f. If this is VNIC 3 of a port then also init | |
6419 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
6420 | * to the last enrty in the ILT. | |
6421 | * | |
6422 | * Notes: | |
6423 | * Currently the PF error in the PGLC is non recoverable. | |
6424 | * In the future the there will be a recovery routine for this error. | |
6425 | * Currently attention is masked. | |
6426 | * Having an MCP lock on the load/unload process does not guarantee that | |
6427 | * there is no Timer disable during Func6/7 enable. This is because the | |
6428 | * Timers scan is currently being cleared by the MCP on FLR. | |
6429 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
6430 | * there is error before clearing it. But the flow above is simpler and | |
6431 | * more general. | |
6432 | * All ILT entries are written by zero+valid and not just PF6/7 | |
6433 | * ILT entries since in the future the ILT entries allocation for | |
6434 | * PF-s might be dynamic. | |
6435 | */ | |
f2e0899f DK |
6436 | struct ilt_client_info ilt_cli; |
6437 | struct bnx2x_ilt ilt; | |
6438 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
6439 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
6440 | ||
b595076a | 6441 | /* initialize dummy TM client */ |
f2e0899f DK |
6442 | ilt_cli.start = 0; |
6443 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
6444 | ilt_cli.client_num = ILT_CLIENT_TM; | |
6445 | ||
6446 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
6447 | * Step 2: set the timers first/last ilt entry to point | |
6448 | * to the entire range to prevent ILT range error for 3rd/4th | |
619c5cb6 | 6449 | * vnic (this code assumes existance of the vnic) |
f2e0899f DK |
6450 | * |
6451 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
6452 | * with dummy TM client | |
6453 | * | |
6454 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
6455 | * and his brother are split registers | |
6456 | */ | |
6457 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
6458 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
6459 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6460 | ||
6461 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
6462 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
6463 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
6464 | } | |
6465 | ||
6466 | ||
34f80b04 EG |
6467 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
6468 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 6469 | |
619c5cb6 | 6470 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6471 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
6472 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 6473 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 6474 | |
619c5cb6 | 6475 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
6476 | |
6477 | /* let the HW do it's magic ... */ | |
6478 | do { | |
6479 | msleep(200); | |
6480 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
6481 | } while (factor-- && (val != 1)); | |
6482 | ||
6483 | if (val != 1) { | |
6484 | BNX2X_ERR("ATC_INIT failed\n"); | |
6485 | return -EBUSY; | |
6486 | } | |
6487 | } | |
6488 | ||
619c5cb6 | 6489 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 6490 | |
34f80b04 EG |
6491 | /* clean the DMAE memory */ |
6492 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
6493 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
6494 | ||
6495 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
6496 | ||
6497 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
6498 | ||
6499 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 6500 | |
619c5cb6 | 6501 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 6502 | |
34f80b04 EG |
6503 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
6504 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
6505 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
6506 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
6507 | ||
619c5cb6 | 6508 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 6509 | |
f85582f8 | 6510 | |
523224a3 DK |
6511 | /* QM queues pointers table */ |
6512 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
6513 | ||
34f80b04 EG |
6514 | /* soft reset pulse */ |
6515 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
6516 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 6517 | |
37b091ba | 6518 | #ifdef BCM_CNIC |
619c5cb6 | 6519 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); |
a2fbb9ea | 6520 | #endif |
a2fbb9ea | 6521 | |
619c5cb6 | 6522 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
523224a3 | 6523 | REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); |
619c5cb6 | 6524 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
6525 | /* enable hw interrupt from doorbell Q */ |
6526 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 6527 | |
619c5cb6 | 6528 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 6529 | |
619c5cb6 | 6530 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 6531 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 6532 | |
f2e0899f | 6533 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 6534 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 6535 | |
a3348722 BW |
6536 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { |
6537 | if (IS_MF_AFEX(bp)) { | |
6538 | /* configure that VNTag and VLAN headers must be | |
6539 | * received in afex mode | |
6540 | */ | |
6541 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); | |
6542 | REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); | |
6543 | REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); | |
6544 | REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); | |
6545 | REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); | |
6546 | } else { | |
6547 | /* Bit-map indicating which L2 hdrs may appear | |
6548 | * after the basic Ethernet header | |
6549 | */ | |
6550 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
6551 | bp->path_has_ovlan ? 7 : 6); | |
6552 | } | |
6553 | } | |
a2fbb9ea | 6554 | |
619c5cb6 VZ |
6555 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
6556 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
6557 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
6558 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 6559 | |
619c5cb6 VZ |
6560 | if (!CHIP_IS_E1x(bp)) { |
6561 | /* reset VFC memories */ | |
6562 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6563 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6564 | VFC_MEMORIES_RST_REG_RAM_RST); | |
6565 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6566 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6567 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 6568 | |
619c5cb6 VZ |
6569 | msleep(20); |
6570 | } | |
a2fbb9ea | 6571 | |
619c5cb6 VZ |
6572 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
6573 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
6574 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
6575 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 6576 | |
34f80b04 EG |
6577 | /* sync semi rtc */ |
6578 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6579 | 0x80000000); | |
6580 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
6581 | 0x80000000); | |
a2fbb9ea | 6582 | |
619c5cb6 VZ |
6583 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
6584 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
6585 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 6586 | |
a3348722 BW |
6587 | if (!CHIP_IS_E1x(bp)) { |
6588 | if (IS_MF_AFEX(bp)) { | |
6589 | /* configure that VNTag and VLAN headers must be | |
6590 | * sent in afex mode | |
6591 | */ | |
6592 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); | |
6593 | REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); | |
6594 | REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); | |
6595 | REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); | |
6596 | REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); | |
6597 | } else { | |
6598 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
6599 | bp->path_has_ovlan ? 7 : 6); | |
6600 | } | |
6601 | } | |
f2e0899f | 6602 | |
34f80b04 | 6603 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 6604 | |
619c5cb6 VZ |
6605 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
6606 | ||
37b091ba MC |
6607 | #ifdef BCM_CNIC |
6608 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
6609 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
6610 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
6611 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
6612 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
6613 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
6614 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
6615 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
6616 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
6617 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
6618 | #endif | |
34f80b04 | 6619 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 6620 | |
34f80b04 EG |
6621 | if (sizeof(union cdu_context) != 1024) |
6622 | /* we currently assume that a context is 1024 bytes */ | |
51c1a580 MS |
6623 | dev_alert(&bp->pdev->dev, |
6624 | "please adjust the size of cdu_context(%ld)\n", | |
6625 | (long)sizeof(union cdu_context)); | |
a2fbb9ea | 6626 | |
619c5cb6 | 6627 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
6628 | val = (4 << 24) + (0 << 12) + 1024; |
6629 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 6630 | |
619c5cb6 | 6631 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 6632 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
6633 | /* enable context validation interrupt from CFC */ |
6634 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
6635 | ||
6636 | /* set the thresholds to prevent CFC/CDU race */ | |
6637 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 6638 | |
619c5cb6 | 6639 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 6640 | |
619c5cb6 | 6641 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
6642 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
6643 | ||
619c5cb6 VZ |
6644 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
6645 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 6646 | |
34f80b04 EG |
6647 | /* Reset PCIE errors for debug */ |
6648 | REG_WR(bp, 0x2814, 0xffffffff); | |
6649 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 6650 | |
619c5cb6 | 6651 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6652 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
6653 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
6654 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
6655 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
6656 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
6657 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
6658 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
6659 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
6660 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
6661 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
6662 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
6663 | } | |
6664 | ||
619c5cb6 | 6665 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 6666 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
6667 | /* in E3 this done in per-port section */ |
6668 | if (!CHIP_IS_E3(bp)) | |
6669 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 6670 | } |
619c5cb6 VZ |
6671 | if (CHIP_IS_E1H(bp)) |
6672 | /* not applicable for E2 (and above ...) */ | |
6673 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
6674 | |
6675 | if (CHIP_REV_IS_SLOW(bp)) | |
6676 | msleep(200); | |
6677 | ||
6678 | /* finish CFC init */ | |
6679 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
6680 | if (val != 1) { | |
6681 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
6682 | return -EBUSY; | |
6683 | } | |
6684 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
6685 | if (val != 1) { | |
6686 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
6687 | return -EBUSY; | |
6688 | } | |
6689 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
6690 | if (val != 1) { | |
6691 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
6692 | return -EBUSY; | |
6693 | } | |
6694 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 6695 | |
f2e0899f DK |
6696 | if (CHIP_IS_E1(bp)) { |
6697 | /* read NIG statistic | |
6698 | to see if this is our first up since powerup */ | |
6699 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
6700 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 6701 | |
f2e0899f DK |
6702 | /* do internal memory self test */ |
6703 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
6704 | BNX2X_ERR("internal mem self test failed\n"); | |
6705 | return -EBUSY; | |
6706 | } | |
34f80b04 EG |
6707 | } |
6708 | ||
fd4ef40d EG |
6709 | bnx2x_setup_fan_failure_detection(bp); |
6710 | ||
34f80b04 EG |
6711 | /* clear PXP2 attentions */ |
6712 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 6713 | |
4a33bc03 | 6714 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 6715 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 6716 | |
6bbca910 | 6717 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
6718 | if (CHIP_IS_E1x(bp)) |
6719 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
6720 | } else |
6721 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
6722 | ||
34f80b04 EG |
6723 | return 0; |
6724 | } | |
a2fbb9ea | 6725 | |
619c5cb6 VZ |
6726 | /** |
6727 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
6728 | * | |
6729 | * @bp: driver handle | |
6730 | */ | |
6731 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
6732 | { | |
6733 | int rc = bnx2x_init_hw_common(bp); | |
6734 | ||
6735 | if (rc) | |
6736 | return rc; | |
6737 | ||
6738 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
6739 | if (!BP_NOMCP(bp)) | |
6740 | bnx2x__common_init_phy(bp); | |
6741 | ||
6742 | return 0; | |
6743 | } | |
6744 | ||
523224a3 | 6745 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
6746 | { |
6747 | int port = BP_PORT(bp); | |
619c5cb6 | 6748 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 6749 | u32 low, high; |
34f80b04 | 6750 | u32 val; |
a2fbb9ea | 6751 | |
619c5cb6 VZ |
6752 | bnx2x__link_reset(bp); |
6753 | ||
51c1a580 | 6754 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
34f80b04 EG |
6755 | |
6756 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 6757 | |
619c5cb6 VZ |
6758 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
6759 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
6760 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 6761 | |
f2e0899f DK |
6762 | /* Timers bug workaround: disables the pf_master bit in pglue at |
6763 | * common phase, we need to enable it here before any dmae access are | |
6764 | * attempted. Therefore we manually added the enable-master to the | |
6765 | * port phase (it also happens in the function phase) | |
6766 | */ | |
619c5cb6 | 6767 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6768 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
6769 | ||
619c5cb6 VZ |
6770 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6771 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6772 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
6773 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6774 | ||
6775 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6776 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6777 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6778 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 6779 | |
523224a3 DK |
6780 | /* QM cid (connection) count */ |
6781 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 6782 | |
523224a3 | 6783 | #ifdef BCM_CNIC |
619c5cb6 | 6784 | bnx2x_init_block(bp, BLOCK_TM, init_phase); |
37b091ba MC |
6785 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); |
6786 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
a2fbb9ea | 6787 | #endif |
cdaa7cb8 | 6788 | |
619c5cb6 | 6789 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f DK |
6790 | |
6791 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { | |
619c5cb6 VZ |
6792 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
6793 | ||
6794 | if (IS_MF(bp)) | |
6795 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
6796 | else if (bp->dev->mtu > 4096) { | |
6797 | if (bp->flags & ONE_PORT_FLAG) | |
6798 | low = 160; | |
6799 | else { | |
6800 | val = bp->dev->mtu; | |
6801 | /* (24*1024 + val*4)/256 */ | |
6802 | low = 96 + (val/64) + | |
6803 | ((val % 64) ? 1 : 0); | |
6804 | } | |
6805 | } else | |
6806 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
6807 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
6808 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
6809 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 6810 | } |
1c06328c | 6811 | |
619c5cb6 VZ |
6812 | if (CHIP_MODE_IS_4_PORT(bp)) |
6813 | REG_WR(bp, (BP_PORT(bp) ? | |
6814 | BRB1_REG_MAC_GUARANTIED_1 : | |
6815 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 6816 | |
ca00392c | 6817 | |
619c5cb6 | 6818 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
a3348722 BW |
6819 | if (CHIP_IS_E3B0(bp)) { |
6820 | if (IS_MF_AFEX(bp)) { | |
6821 | /* configure headers for AFEX mode */ | |
6822 | REG_WR(bp, BP_PORT(bp) ? | |
6823 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
6824 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); | |
6825 | REG_WR(bp, BP_PORT(bp) ? | |
6826 | PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : | |
6827 | PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); | |
6828 | REG_WR(bp, BP_PORT(bp) ? | |
6829 | PRS_REG_MUST_HAVE_HDRS_PORT_1 : | |
6830 | PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); | |
6831 | } else { | |
6832 | /* Ovlan exists only if we are in multi-function + | |
6833 | * switch-dependent mode, in switch-independent there | |
6834 | * is no ovlan headers | |
6835 | */ | |
6836 | REG_WR(bp, BP_PORT(bp) ? | |
6837 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
6838 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
6839 | (bp->path_has_ovlan ? 7 : 6)); | |
6840 | } | |
6841 | } | |
356e2385 | 6842 | |
619c5cb6 VZ |
6843 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
6844 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
6845 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
6846 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 6847 | |
619c5cb6 VZ |
6848 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
6849 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6850 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6851 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 6852 | |
619c5cb6 VZ |
6853 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
6854 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 6855 | |
619c5cb6 VZ |
6856 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
6857 | ||
6858 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
6859 | /* configure PBF to work without PAUSE mtu 9000 */ |
6860 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 6861 | |
f2e0899f DK |
6862 | /* update threshold */ |
6863 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
6864 | /* update init credit */ | |
6865 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 6866 | |
f2e0899f DK |
6867 | /* probe changes */ |
6868 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
6869 | udelay(50); | |
6870 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
6871 | } | |
a2fbb9ea | 6872 | |
37b091ba | 6873 | #ifdef BCM_CNIC |
619c5cb6 | 6874 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); |
a2fbb9ea | 6875 | #endif |
619c5cb6 VZ |
6876 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
6877 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
6878 | |
6879 | if (CHIP_IS_E1(bp)) { | |
6880 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
6881 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
6882 | } | |
619c5cb6 | 6883 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 6884 | |
619c5cb6 | 6885 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 6886 | |
619c5cb6 | 6887 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 EG |
6888 | /* init aeu_mask_attn_func_0/1: |
6889 | * - SF mode: bits 3-7 are masked. only bits 0-2 are in use | |
6890 | * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF | |
6891 | * bits 4-7 are used for "per vn group attention" */ | |
e4901dde VZ |
6892 | val = IS_MF(bp) ? 0xF7 : 0x7; |
6893 | /* Enable DCBX attention for all but E1 */ | |
6894 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
6895 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 6896 | |
619c5cb6 VZ |
6897 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
6898 | ||
6899 | if (!CHIP_IS_E1x(bp)) { | |
6900 | /* Bit-map indicating which L2 hdrs may appear after the | |
6901 | * basic Ethernet header | |
6902 | */ | |
a3348722 BW |
6903 | if (IS_MF_AFEX(bp)) |
6904 | REG_WR(bp, BP_PORT(bp) ? | |
6905 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
6906 | NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); | |
6907 | else | |
6908 | REG_WR(bp, BP_PORT(bp) ? | |
6909 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
6910 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
6911 | IS_MF_SD(bp) ? 7 : 6); | |
619c5cb6 VZ |
6912 | |
6913 | if (CHIP_IS_E3(bp)) | |
6914 | REG_WR(bp, BP_PORT(bp) ? | |
6915 | NIG_REG_LLH1_MF_MODE : | |
6916 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
6917 | } | |
6918 | if (!CHIP_IS_E3(bp)) | |
6919 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 6920 | |
f2e0899f | 6921 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 6922 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 6923 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 6924 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 6925 | |
619c5cb6 | 6926 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6927 | val = 0; |
6928 | switch (bp->mf_mode) { | |
6929 | case MULTI_FUNCTION_SD: | |
6930 | val = 1; | |
6931 | break; | |
6932 | case MULTI_FUNCTION_SI: | |
a3348722 | 6933 | case MULTI_FUNCTION_AFEX: |
f2e0899f DK |
6934 | val = 2; |
6935 | break; | |
6936 | } | |
6937 | ||
6938 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
6939 | NIG_REG_LLH0_CLS_TYPE), val); | |
6940 | } | |
1c06328c EG |
6941 | { |
6942 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
6943 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
6944 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
6945 | } | |
34f80b04 EG |
6946 | } |
6947 | ||
619c5cb6 VZ |
6948 | |
6949 | /* If SPIO5 is set to generate interrupts, enable it for this port */ | |
6950 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
6951 | if (val & (1 << MISC_REGISTERS_SPIO_5)) { | |
4d295db0 EG |
6952 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
6953 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
6954 | val = REG_RD(bp, reg_addr); | |
f1410647 | 6955 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 6956 | REG_WR(bp, reg_addr, val); |
f1410647 | 6957 | } |
a2fbb9ea | 6958 | |
34f80b04 EG |
6959 | return 0; |
6960 | } | |
6961 | ||
34f80b04 EG |
6962 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
6963 | { | |
6964 | int reg; | |
32d68de1 | 6965 | u32 wb_write[2]; |
34f80b04 | 6966 | |
f2e0899f | 6967 | if (CHIP_IS_E1(bp)) |
34f80b04 | 6968 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
6969 | else |
6970 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 | 6971 | |
32d68de1 YM |
6972 | wb_write[0] = ONCHIP_ADDR1(addr); |
6973 | wb_write[1] = ONCHIP_ADDR2(addr); | |
6974 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
34f80b04 EG |
6975 | } |
6976 | ||
1191cb83 ED |
6977 | static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, |
6978 | u8 idu_sb_id, bool is_Pf) | |
6979 | { | |
6980 | u32 data, ctl, cnt = 100; | |
6981 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
6982 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
6983 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
6984 | u32 sb_bit = 1 << (idu_sb_id%32); | |
6985 | u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; | |
6986 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; | |
6987 | ||
6988 | /* Not supported in BC mode */ | |
6989 | if (CHIP_INT_MODE_IS_BC(bp)) | |
6990 | return; | |
6991 | ||
6992 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
6993 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
6994 | IGU_REGULAR_CLEANUP_SET | | |
6995 | IGU_REGULAR_BCLEANUP; | |
6996 | ||
6997 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
6998 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
6999 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
7000 | ||
7001 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7002 | data, igu_addr_data); | |
7003 | REG_WR(bp, igu_addr_data, data); | |
7004 | mmiowb(); | |
7005 | barrier(); | |
7006 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7007 | ctl, igu_addr_ctl); | |
7008 | REG_WR(bp, igu_addr_ctl, ctl); | |
7009 | mmiowb(); | |
7010 | barrier(); | |
7011 | ||
7012 | /* wait for clean up to finish */ | |
7013 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
7014 | msleep(20); | |
7015 | ||
7016 | ||
7017 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { | |
7018 | DP(NETIF_MSG_HW, | |
7019 | "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
7020 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
7021 | } | |
7022 | } | |
7023 | ||
7024 | static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) | |
f2e0899f | 7025 | { |
619c5cb6 | 7026 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
7027 | } |
7028 | ||
1191cb83 | 7029 | static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) |
f2e0899f DK |
7030 | { |
7031 | u32 i, base = FUNC_ILT_BASE(func); | |
7032 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
7033 | bnx2x_ilt_wr(bp, i, 0); | |
7034 | } | |
7035 | ||
523224a3 | 7036 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
7037 | { |
7038 | int port = BP_PORT(bp); | |
7039 | int func = BP_FUNC(bp); | |
619c5cb6 | 7040 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
7041 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
7042 | u16 cdu_ilt_start; | |
8badd27a | 7043 | u32 addr, val; |
f4a66897 | 7044 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
89db4ad8 | 7045 | int i, main_mem_width, rc; |
34f80b04 | 7046 | |
51c1a580 | 7047 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
34f80b04 | 7048 | |
619c5cb6 | 7049 | /* FLR cleanup - hmmm */ |
89db4ad8 AE |
7050 | if (!CHIP_IS_E1x(bp)) { |
7051 | rc = bnx2x_pf_flr_clnup(bp); | |
7052 | if (rc) | |
7053 | return rc; | |
7054 | } | |
619c5cb6 | 7055 | |
8badd27a | 7056 | /* set MSI reconfigure capability */ |
f2e0899f DK |
7057 | if (bp->common.int_block == INT_BLOCK_HC) { |
7058 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
7059 | val = REG_RD(bp, addr); | |
7060 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
7061 | REG_WR(bp, addr, val); | |
7062 | } | |
8badd27a | 7063 | |
619c5cb6 VZ |
7064 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
7065 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
7066 | ||
523224a3 DK |
7067 | ilt = BP_ILT(bp); |
7068 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 7069 | |
523224a3 | 7070 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
a052997e | 7071 | ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; |
523224a3 | 7072 | ilt->lines[cdu_ilt_start + i].page_mapping = |
a052997e MS |
7073 | bp->context[i].cxt_mapping; |
7074 | ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; | |
37b091ba | 7075 | } |
523224a3 | 7076 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 7077 | |
523224a3 DK |
7078 | #ifdef BCM_CNIC |
7079 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
37b091ba | 7080 | |
523224a3 DK |
7081 | /* T1 hash bits value determines the T1 number of entries */ |
7082 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
7083 | #endif | |
37b091ba | 7084 | |
523224a3 DK |
7085 | #ifndef BCM_CNIC |
7086 | /* set NIC mode */ | |
7087 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
7088 | #endif /* BCM_CNIC */ | |
37b091ba | 7089 | |
619c5cb6 | 7090 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7091 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
7092 | ||
7093 | /* Turn on a single ISR mode in IGU if driver is going to use | |
7094 | * INT#x or MSI | |
7095 | */ | |
7096 | if (!(bp->flags & USING_MSIX_FLAG)) | |
7097 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
7098 | /* | |
7099 | * Timers workaround bug: function init part. | |
7100 | * Need to wait 20msec after initializing ILT, | |
7101 | * needed to make sure there are no requests in | |
7102 | * one of the PXP internal queues with "old" ILT addresses | |
7103 | */ | |
7104 | msleep(20); | |
7105 | /* | |
7106 | * Master enable - Due to WB DMAE writes performed before this | |
7107 | * register is re-initialized as part of the regular function | |
7108 | * init | |
7109 | */ | |
7110 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
7111 | /* Enable the function in IGU */ | |
7112 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
7113 | } | |
7114 | ||
523224a3 | 7115 | bp->dmae_ready = 1; |
34f80b04 | 7116 | |
619c5cb6 | 7117 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 7118 | |
619c5cb6 | 7119 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7120 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); |
7121 | ||
619c5cb6 VZ |
7122 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7123 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7124 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
7125 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7126 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
7127 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7128 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7129 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7130 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
7131 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
7132 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7133 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7134 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
7135 | ||
7136 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7137 | REG_WR(bp, QM_REG_PF_EN, 1); |
7138 | ||
619c5cb6 VZ |
7139 | if (!CHIP_IS_E1x(bp)) { |
7140 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7141 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7142 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7143 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7144 | } | |
7145 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7146 | ||
7147 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7148 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
7149 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); | |
7150 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
7151 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
7152 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7153 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7154 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
7155 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
7156 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
7157 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
7158 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7159 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
7160 | ||
619c5cb6 | 7161 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 7162 | |
619c5cb6 | 7163 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 7164 | |
619c5cb6 | 7165 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7166 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
7167 | ||
fb3bff17 | 7168 | if (IS_MF(bp)) { |
34f80b04 | 7169 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
fb3bff17 | 7170 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
34f80b04 EG |
7171 | } |
7172 | ||
619c5cb6 | 7173 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 7174 | |
34f80b04 | 7175 | /* HC init per function */ |
f2e0899f DK |
7176 | if (bp->common.int_block == INT_BLOCK_HC) { |
7177 | if (CHIP_IS_E1H(bp)) { | |
7178 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
7179 | ||
7180 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7181 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7182 | } | |
619c5cb6 | 7183 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
7184 | |
7185 | } else { | |
7186 | int num_segs, sb_idx, prod_offset; | |
7187 | ||
34f80b04 EG |
7188 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
7189 | ||
619c5cb6 | 7190 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7191 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
7192 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
7193 | } | |
7194 | ||
619c5cb6 | 7195 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7196 | |
619c5cb6 | 7197 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7198 | int dsb_idx = 0; |
7199 | /** | |
7200 | * Producer memory: | |
7201 | * E2 mode: address 0-135 match to the mapping memory; | |
7202 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
7203 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
7204 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
7205 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
7206 | * 144-147 reserved. | |
7207 | * | |
7208 | * E1.5 mode - In backward compatible mode; | |
7209 | * for non default SB; each even line in the memory | |
7210 | * holds the U producer and each odd line hold | |
7211 | * the C producer. The first 128 producers are for | |
7212 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
7213 | * producers are for the DSB for each PF. | |
7214 | * Each PF has five segments: (the order inside each | |
7215 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
7216 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
7217 | * 144-147 attn prods; | |
7218 | */ | |
7219 | /* non-default-status-blocks */ | |
7220 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7221 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
7222 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
7223 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
7224 | num_segs; | |
7225 | ||
7226 | for (i = 0; i < num_segs; i++) { | |
7227 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7228 | (prod_offset + i) * 4; | |
7229 | REG_WR(bp, addr, 0); | |
7230 | } | |
7231 | /* send consumer update with value 0 */ | |
7232 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
7233 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7234 | bnx2x_igu_clear_sb(bp, | |
7235 | bp->igu_base_sb + sb_idx); | |
7236 | } | |
7237 | ||
7238 | /* default-status-blocks */ | |
7239 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7240 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
7241 | ||
7242 | if (CHIP_MODE_IS_4_PORT(bp)) | |
7243 | dsb_idx = BP_FUNC(bp); | |
7244 | else | |
3395a033 | 7245 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
7246 | |
7247 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
7248 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
7249 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
7250 | ||
3395a033 DK |
7251 | /* |
7252 | * igu prods come in chunks of E1HVN_MAX (4) - | |
7253 | * does not matters what is the current chip mode | |
7254 | */ | |
f2e0899f DK |
7255 | for (i = 0; i < (num_segs * E1HVN_MAX); |
7256 | i += E1HVN_MAX) { | |
7257 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7258 | (prod_offset + i)*4; | |
7259 | REG_WR(bp, addr, 0); | |
7260 | } | |
7261 | /* send consumer update with 0 */ | |
7262 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
7263 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7264 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7265 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7266 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
7267 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7268 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
7269 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7270 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
7271 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7272 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7273 | } else { | |
7274 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7275 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7276 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7277 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7278 | } | |
7279 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
7280 | ||
7281 | /* !!! these should become driver const once | |
7282 | rf-tool supports split-68 const */ | |
7283 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
7284 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
7285 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
7286 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
7287 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
7288 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
7289 | } | |
34f80b04 | 7290 | } |
34f80b04 | 7291 | |
c14423fe | 7292 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
7293 | REG_WR(bp, 0x2114, 0xffffffff); |
7294 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 7295 | |
f4a66897 VZ |
7296 | if (CHIP_IS_E1x(bp)) { |
7297 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
7298 | main_mem_base = HC_REG_MAIN_MEMORY + | |
7299 | BP_PORT(bp) * (main_mem_size * 4); | |
7300 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
7301 | main_mem_width = 8; | |
7302 | ||
7303 | val = REG_RD(bp, main_mem_prty_clr); | |
7304 | if (val) | |
51c1a580 MS |
7305 | DP(NETIF_MSG_HW, |
7306 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", | |
7307 | val); | |
f4a66897 VZ |
7308 | |
7309 | /* Clear "false" parity errors in MSI-X table */ | |
7310 | for (i = main_mem_base; | |
7311 | i < main_mem_base + main_mem_size * 4; | |
7312 | i += main_mem_width) { | |
7313 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
7314 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
7315 | i, main_mem_width / 4); | |
7316 | } | |
7317 | /* Clear HC parity attention */ | |
7318 | REG_RD(bp, main_mem_prty_clr); | |
7319 | } | |
7320 | ||
619c5cb6 VZ |
7321 | #ifdef BNX2X_STOP_ON_ERROR |
7322 | /* Enable STORMs SP logging */ | |
7323 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
7324 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7325 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
7326 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7327 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
7328 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7329 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
7330 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7331 | #endif | |
7332 | ||
b7737c9b | 7333 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 7334 | |
34f80b04 EG |
7335 | return 0; |
7336 | } | |
7337 | ||
a2fbb9ea | 7338 | |
9f6c9258 | 7339 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 7340 | { |
a052997e MS |
7341 | int i; |
7342 | ||
a2fbb9ea | 7343 | /* fastpath */ |
b3b83c3f | 7344 | bnx2x_free_fp_mem(bp); |
a2fbb9ea ET |
7345 | /* end of fastpath */ |
7346 | ||
7347 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
523224a3 | 7348 | sizeof(struct host_sp_status_block)); |
a2fbb9ea | 7349 | |
619c5cb6 VZ |
7350 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
7351 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
7352 | ||
a2fbb9ea | 7353 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 7354 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 7355 | |
a052997e MS |
7356 | for (i = 0; i < L2_ILT_LINES(bp); i++) |
7357 | BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, | |
7358 | bp->context[i].size); | |
523224a3 DK |
7359 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); |
7360 | ||
7361 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 7362 | |
37b091ba | 7363 | #ifdef BCM_CNIC |
619c5cb6 | 7364 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7365 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, |
7366 | sizeof(struct host_hc_status_block_e2)); | |
7367 | else | |
7368 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
7369 | sizeof(struct host_hc_status_block_e1x)); | |
f85582f8 | 7370 | |
523224a3 | 7371 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
a2fbb9ea | 7372 | #endif |
f85582f8 | 7373 | |
7a9b2557 | 7374 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 7375 | |
523224a3 DK |
7376 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
7377 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
619c5cb6 VZ |
7378 | } |
7379 | ||
1191cb83 | 7380 | static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) |
619c5cb6 VZ |
7381 | { |
7382 | int num_groups; | |
50f0a562 | 7383 | int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; |
619c5cb6 | 7384 | |
50f0a562 BW |
7385 | /* number of queues for statistics is number of eth queues + FCoE */ |
7386 | u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; | |
619c5cb6 VZ |
7387 | |
7388 | /* Total number of FW statistics requests = | |
50f0a562 BW |
7389 | * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + |
7390 | * num of queues | |
7391 | */ | |
7392 | bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; | |
523224a3 | 7393 | |
619c5cb6 VZ |
7394 | |
7395 | /* Request is built from stats_query_header and an array of | |
7396 | * stats_query_cmd_group each of which contains | |
7397 | * STATS_QUERY_CMD_COUNT rules. The real number or requests is | |
7398 | * configured in the stats_query_header. | |
7399 | */ | |
50f0a562 BW |
7400 | num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + |
7401 | (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); | |
619c5cb6 VZ |
7402 | |
7403 | bp->fw_stats_req_sz = sizeof(struct stats_query_header) + | |
7404 | num_groups * sizeof(struct stats_query_cmd_group); | |
7405 | ||
7406 | /* Data for statistics requests + stats_conter | |
7407 | * | |
7408 | * stats_counter holds per-STORM counters that are incremented | |
7409 | * when STORM has finished with the current request. | |
50f0a562 BW |
7410 | * |
7411 | * memory for FCoE offloaded statistics are counted anyway, | |
7412 | * even if they will not be sent. | |
619c5cb6 VZ |
7413 | */ |
7414 | bp->fw_stats_data_sz = sizeof(struct per_port_stats) + | |
7415 | sizeof(struct per_pf_stats) + | |
50f0a562 | 7416 | sizeof(struct fcoe_statistics_params) + |
619c5cb6 VZ |
7417 | sizeof(struct per_queue_stats) * num_queue_stats + |
7418 | sizeof(struct stats_counter); | |
7419 | ||
7420 | BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, | |
7421 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
7422 | ||
7423 | /* Set shortcuts */ | |
7424 | bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; | |
7425 | bp->fw_stats_req_mapping = bp->fw_stats_mapping; | |
7426 | ||
7427 | bp->fw_stats_data = (struct bnx2x_fw_stats_data *) | |
7428 | ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); | |
7429 | ||
7430 | bp->fw_stats_data_mapping = bp->fw_stats_mapping + | |
7431 | bp->fw_stats_req_sz; | |
7432 | return 0; | |
7433 | ||
7434 | alloc_mem_err: | |
7435 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, | |
7436 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
51c1a580 | 7437 | BNX2X_ERR("Can't allocate memory\n"); |
619c5cb6 | 7438 | return -ENOMEM; |
a2fbb9ea ET |
7439 | } |
7440 | ||
f2e0899f | 7441 | |
9f6c9258 | 7442 | int bnx2x_alloc_mem(struct bnx2x *bp) |
a2fbb9ea | 7443 | { |
a052997e MS |
7444 | int i, allocated, context_size; |
7445 | ||
523224a3 | 7446 | #ifdef BCM_CNIC |
619c5cb6 VZ |
7447 | if (!CHIP_IS_E1x(bp)) |
7448 | /* size = the status block + ramrod buffers */ | |
f2e0899f DK |
7449 | BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, |
7450 | sizeof(struct host_hc_status_block_e2)); | |
7451 | else | |
7452 | BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, | |
7453 | sizeof(struct host_hc_status_block_e1x)); | |
8badd27a | 7454 | |
523224a3 DK |
7455 | /* allocate searcher T2 table */ |
7456 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
7457 | #endif | |
a2fbb9ea | 7458 | |
8badd27a | 7459 | |
523224a3 DK |
7460 | BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, |
7461 | sizeof(struct host_sp_status_block)); | |
a2fbb9ea | 7462 | |
523224a3 DK |
7463 | BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, |
7464 | sizeof(struct bnx2x_slowpath)); | |
a2fbb9ea | 7465 | |
82fa848c MY |
7466 | #ifdef BCM_CNIC |
7467 | /* write address to which L5 should insert its values */ | |
7468 | bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp; | |
7469 | #endif | |
7470 | ||
619c5cb6 VZ |
7471 | /* Allocated memory for FW statistics */ |
7472 | if (bnx2x_alloc_fw_stats_mem(bp)) | |
7473 | goto alloc_mem_err; | |
7474 | ||
a052997e MS |
7475 | /* Allocate memory for CDU context: |
7476 | * This memory is allocated separately and not in the generic ILT | |
7477 | * functions because CDU differs in few aspects: | |
7478 | * 1. There are multiple entities allocating memory for context - | |
7479 | * 'regular' driver, CNIC and SRIOV driver. Each separately controls | |
7480 | * its own ILT lines. | |
7481 | * 2. Since CDU page-size is not a single 4KB page (which is the case | |
7482 | * for the other ILT clients), to be efficient we want to support | |
7483 | * allocation of sub-page-size in the last entry. | |
7484 | * 3. Context pointers are used by the driver to pass to FW / update | |
7485 | * the context (for the other ILT clients the pointers are used just to | |
7486 | * free the memory during unload). | |
7487 | */ | |
7488 | context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); | |
65abd74d | 7489 | |
a052997e MS |
7490 | for (i = 0, allocated = 0; allocated < context_size; i++) { |
7491 | bp->context[i].size = min(CDU_ILT_PAGE_SZ, | |
7492 | (context_size - allocated)); | |
7493 | BNX2X_PCI_ALLOC(bp->context[i].vcxt, | |
7494 | &bp->context[i].cxt_mapping, | |
7495 | bp->context[i].size); | |
7496 | allocated += bp->context[i].size; | |
7497 | } | |
523224a3 | 7498 | BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); |
65abd74d | 7499 | |
523224a3 DK |
7500 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
7501 | goto alloc_mem_err; | |
65abd74d | 7502 | |
9f6c9258 DK |
7503 | /* Slow path ring */ |
7504 | BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); | |
65abd74d | 7505 | |
523224a3 DK |
7506 | /* EQ */ |
7507 | BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, | |
7508 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
ab532cf3 | 7509 | |
b3b83c3f DK |
7510 | |
7511 | /* fastpath */ | |
7512 | /* need to be done at the end, since it's self adjusting to amount | |
7513 | * of memory available for RSS queues | |
7514 | */ | |
7515 | if (bnx2x_alloc_fp_mem(bp)) | |
7516 | goto alloc_mem_err; | |
9f6c9258 | 7517 | return 0; |
e1510706 | 7518 | |
9f6c9258 DK |
7519 | alloc_mem_err: |
7520 | bnx2x_free_mem(bp); | |
51c1a580 | 7521 | BNX2X_ERR("Can't allocate memory\n"); |
9f6c9258 | 7522 | return -ENOMEM; |
65abd74d YG |
7523 | } |
7524 | ||
a2fbb9ea ET |
7525 | /* |
7526 | * Init service functions | |
7527 | */ | |
a2fbb9ea | 7528 | |
619c5cb6 VZ |
7529 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
7530 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
7531 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 7532 | { |
619c5cb6 VZ |
7533 | int rc; |
7534 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 7535 | |
619c5cb6 | 7536 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 7537 | |
619c5cb6 VZ |
7538 | /* Fill general parameters */ |
7539 | ramrod_param.vlan_mac_obj = obj; | |
7540 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 7541 | |
619c5cb6 VZ |
7542 | /* Fill a user request section if needed */ |
7543 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
7544 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 7545 | |
619c5cb6 | 7546 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 7547 | |
619c5cb6 VZ |
7548 | /* Set the command: ADD or DEL */ |
7549 | if (set) | |
7550 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
7551 | else | |
7552 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
7553 | } |
7554 | ||
619c5cb6 VZ |
7555 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7556 | if (rc < 0) | |
7557 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); | |
7558 | return rc; | |
a2fbb9ea ET |
7559 | } |
7560 | ||
619c5cb6 VZ |
7561 | int bnx2x_del_all_macs(struct bnx2x *bp, |
7562 | struct bnx2x_vlan_mac_obj *mac_obj, | |
7563 | int mac_type, bool wait_for_comp) | |
e665bfda | 7564 | { |
619c5cb6 VZ |
7565 | int rc; |
7566 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 7567 | |
619c5cb6 VZ |
7568 | /* Wait for completion of requested */ |
7569 | if (wait_for_comp) | |
7570 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 7571 | |
619c5cb6 VZ |
7572 | /* Set the mac type of addresses we want to clear */ |
7573 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 7574 | |
619c5cb6 VZ |
7575 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
7576 | if (rc < 0) | |
7577 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 7578 | |
619c5cb6 | 7579 | return rc; |
0793f83f DK |
7580 | } |
7581 | ||
619c5cb6 | 7582 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 7583 | { |
619c5cb6 | 7584 | unsigned long ramrod_flags = 0; |
e665bfda | 7585 | |
614c76df | 7586 | #ifdef BCM_CNIC |
a3348722 BW |
7587 | if (is_zero_ether_addr(bp->dev->dev_addr) && |
7588 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) { | |
51c1a580 MS |
7589 | DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, |
7590 | "Ignoring Zero MAC for STORAGE SD mode\n"); | |
614c76df DK |
7591 | return 0; |
7592 | } | |
7593 | #endif | |
7594 | ||
619c5cb6 | 7595 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
0793f83f | 7596 | |
619c5cb6 VZ |
7597 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
7598 | /* Eth MAC is set on RSS leading client (fp[0]) */ | |
15192a8c BW |
7599 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj, |
7600 | set, BNX2X_ETH_MAC, &ramrod_flags); | |
e665bfda | 7601 | } |
6e30dd4e | 7602 | |
619c5cb6 | 7603 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 7604 | { |
619c5cb6 | 7605 | return bnx2x_setup_queue(bp, &bp->fp[0], 1); |
993ac7b5 | 7606 | } |
a2fbb9ea | 7607 | |
d6214d7a | 7608 | /** |
e8920674 | 7609 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 7610 | * |
e8920674 | 7611 | * @bp: driver handle |
d6214d7a | 7612 | * |
e8920674 | 7613 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 7614 | */ |
9ee3d37b | 7615 | static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 7616 | { |
9ee3d37b | 7617 | switch (int_mode) { |
d6214d7a DK |
7618 | case INT_MODE_MSI: |
7619 | bnx2x_enable_msi(bp); | |
7620 | /* falling through... */ | |
7621 | case INT_MODE_INTx: | |
6383c0b3 | 7622 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; |
51c1a580 | 7623 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
ca00392c | 7624 | break; |
d6214d7a | 7625 | default: |
30a5de77 | 7626 | /* Set number of queues for MSI-X mode */ |
d6214d7a | 7627 | bnx2x_set_num_queues(bp); |
ca00392c | 7628 | |
51c1a580 | 7629 | BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); |
ca00392c | 7630 | |
d6214d7a DK |
7631 | /* if we can't use MSI-X we only need one fp, |
7632 | * so try to enable MSI-X with the requested number of fp's | |
7633 | * and fallback to MSI or legacy INTx with one fp | |
7634 | */ | |
30a5de77 DK |
7635 | if (bnx2x_enable_msix(bp) || |
7636 | bp->flags & USING_SINGLE_MSIX_FLAG) { | |
7637 | /* failed to enable multiple MSI-X */ | |
7638 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", | |
51c1a580 MS |
7639 | bp->num_queues, 1 + NON_ETH_CONTEXT_USE); |
7640 | ||
6383c0b3 | 7641 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; |
d6214d7a | 7642 | |
9ee3d37b | 7643 | /* Try to enable MSI */ |
30a5de77 DK |
7644 | if (!(bp->flags & USING_SINGLE_MSIX_FLAG) && |
7645 | !(bp->flags & DISABLE_MSI_FLAG)) | |
d6214d7a DK |
7646 | bnx2x_enable_msi(bp); |
7647 | } | |
9f6c9258 DK |
7648 | break; |
7649 | } | |
a2fbb9ea ET |
7650 | } |
7651 | ||
c2bff63f DK |
7652 | /* must be called prioir to any HW initializations */ |
7653 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) | |
7654 | { | |
7655 | return L2_ILT_LINES(bp); | |
7656 | } | |
7657 | ||
523224a3 DK |
7658 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
7659 | { | |
7660 | struct ilt_client_info *ilt_client; | |
7661 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
7662 | u16 line = 0; | |
7663 | ||
7664 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
7665 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
7666 | ||
7667 | /* CDU */ | |
7668 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
7669 | ilt_client->client_num = ILT_CLIENT_CDU; | |
7670 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
7671 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
7672 | ilt_client->start = line; | |
619c5cb6 | 7673 | line += bnx2x_cid_ilt_lines(bp); |
523224a3 DK |
7674 | #ifdef BCM_CNIC |
7675 | line += CNIC_ILT_LINES; | |
7676 | #endif | |
7677 | ilt_client->end = line - 1; | |
7678 | ||
51c1a580 | 7679 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
523224a3 DK |
7680 | ilt_client->start, |
7681 | ilt_client->end, | |
7682 | ilt_client->page_size, | |
7683 | ilt_client->flags, | |
7684 | ilog2(ilt_client->page_size >> 12)); | |
7685 | ||
7686 | /* QM */ | |
7687 | if (QM_INIT(bp->qm_cid_count)) { | |
7688 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
7689 | ilt_client->client_num = ILT_CLIENT_QM; | |
7690 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
7691 | ilt_client->flags = 0; | |
7692 | ilt_client->start = line; | |
7693 | ||
7694 | /* 4 bytes for each cid */ | |
7695 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
7696 | QM_ILT_PAGE_SZ); | |
7697 | ||
7698 | ilt_client->end = line - 1; | |
7699 | ||
51c1a580 MS |
7700 | DP(NETIF_MSG_IFUP, |
7701 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7702 | ilt_client->start, |
7703 | ilt_client->end, | |
7704 | ilt_client->page_size, | |
7705 | ilt_client->flags, | |
7706 | ilog2(ilt_client->page_size >> 12)); | |
7707 | ||
7708 | } | |
7709 | /* SRC */ | |
7710 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
7711 | #ifdef BCM_CNIC | |
7712 | ilt_client->client_num = ILT_CLIENT_SRC; | |
7713 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
7714 | ilt_client->flags = 0; | |
7715 | ilt_client->start = line; | |
7716 | line += SRC_ILT_LINES; | |
7717 | ilt_client->end = line - 1; | |
7718 | ||
51c1a580 MS |
7719 | DP(NETIF_MSG_IFUP, |
7720 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7721 | ilt_client->start, |
7722 | ilt_client->end, | |
7723 | ilt_client->page_size, | |
7724 | ilt_client->flags, | |
7725 | ilog2(ilt_client->page_size >> 12)); | |
7726 | ||
7727 | #else | |
7728 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7729 | #endif | |
9f6c9258 | 7730 | |
523224a3 DK |
7731 | /* TM */ |
7732 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
7733 | #ifdef BCM_CNIC | |
7734 | ilt_client->client_num = ILT_CLIENT_TM; | |
7735 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
7736 | ilt_client->flags = 0; | |
7737 | ilt_client->start = line; | |
7738 | line += TM_ILT_LINES; | |
7739 | ilt_client->end = line - 1; | |
7740 | ||
51c1a580 MS |
7741 | DP(NETIF_MSG_IFUP, |
7742 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7743 | ilt_client->start, |
7744 | ilt_client->end, | |
7745 | ilt_client->page_size, | |
7746 | ilt_client->flags, | |
7747 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 7748 | |
523224a3 DK |
7749 | #else |
7750 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7751 | #endif | |
619c5cb6 | 7752 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 7753 | } |
f85582f8 | 7754 | |
619c5cb6 VZ |
7755 | /** |
7756 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
7757 | * | |
7758 | * @bp: driver handle | |
7759 | * @fp: pointer to fastpath | |
7760 | * @init_params: pointer to parameters structure | |
7761 | * | |
7762 | * parameters configured: | |
7763 | * - HC configuration | |
7764 | * - Queue's CDU context | |
7765 | */ | |
1191cb83 | 7766 | static void bnx2x_pf_q_prep_init(struct bnx2x *bp, |
619c5cb6 | 7767 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) |
a2fbb9ea | 7768 | { |
6383c0b3 AE |
7769 | |
7770 | u8 cos; | |
a052997e MS |
7771 | int cxt_index, cxt_offset; |
7772 | ||
619c5cb6 VZ |
7773 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
7774 | if (!IS_FCOE_FP(fp)) { | |
7775 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
7776 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
7777 | ||
7778 | /* If HC is supporterd, enable host coalescing in the transition | |
7779 | * to INIT state. | |
7780 | */ | |
7781 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
7782 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
7783 | ||
7784 | /* HC rate */ | |
7785 | init_params->rx.hc_rate = bp->rx_ticks ? | |
7786 | (1000000 / bp->rx_ticks) : 0; | |
7787 | init_params->tx.hc_rate = bp->tx_ticks ? | |
7788 | (1000000 / bp->tx_ticks) : 0; | |
7789 | ||
7790 | /* FW SB ID */ | |
7791 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
7792 | fp->fw_sb_id; | |
7793 | ||
7794 | /* | |
7795 | * CQ index among the SB indices: FCoE clients uses the default | |
7796 | * SB, therefore it's different. | |
7797 | */ | |
6383c0b3 AE |
7798 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
7799 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
7800 | } |
7801 | ||
6383c0b3 AE |
7802 | /* set maximum number of COSs supported by this queue */ |
7803 | init_params->max_cos = fp->max_cos; | |
7804 | ||
51c1a580 | 7805 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
7806 | fp->index, init_params->max_cos); |
7807 | ||
7808 | /* set the context pointers queue object */ | |
a052997e | 7809 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { |
65565884 MS |
7810 | cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; |
7811 | cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * | |
a052997e | 7812 | ILT_PAGE_CIDS); |
6383c0b3 | 7813 | init_params->cxts[cos] = |
a052997e MS |
7814 | &bp->context[cxt_index].vcxt[cxt_offset].eth; |
7815 | } | |
619c5cb6 VZ |
7816 | } |
7817 | ||
6383c0b3 AE |
7818 | int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
7819 | struct bnx2x_queue_state_params *q_params, | |
7820 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
7821 | int tx_index, bool leading) | |
7822 | { | |
7823 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
7824 | ||
7825 | /* Set the command */ | |
7826 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
7827 | ||
7828 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
7829 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
7830 | ||
7831 | /* choose the index of the cid to send the slow path on */ | |
7832 | tx_only_params->cid_index = tx_index; | |
7833 | ||
7834 | /* Set general TX_ONLY_SETUP parameters */ | |
7835 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
7836 | ||
7837 | /* Set Tx TX_ONLY_SETUP parameters */ | |
7838 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
7839 | ||
51c1a580 MS |
7840 | DP(NETIF_MSG_IFUP, |
7841 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", | |
6383c0b3 AE |
7842 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
7843 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
7844 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
7845 | ||
7846 | /* send the ramrod */ | |
7847 | return bnx2x_queue_state_change(bp, q_params); | |
7848 | } | |
7849 | ||
7850 | ||
619c5cb6 VZ |
7851 | /** |
7852 | * bnx2x_setup_queue - setup queue | |
7853 | * | |
7854 | * @bp: driver handle | |
7855 | * @fp: pointer to fastpath | |
7856 | * @leading: is leading | |
7857 | * | |
7858 | * This function performs 2 steps in a Queue state machine | |
7859 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
7860 | */ | |
7861 | ||
7862 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
7863 | bool leading) | |
7864 | { | |
3b603066 | 7865 | struct bnx2x_queue_state_params q_params = {NULL}; |
619c5cb6 VZ |
7866 | struct bnx2x_queue_setup_params *setup_params = |
7867 | &q_params.params.setup; | |
6383c0b3 AE |
7868 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
7869 | &q_params.params.tx_only; | |
a2fbb9ea | 7870 | int rc; |
6383c0b3 AE |
7871 | u8 tx_index; |
7872 | ||
51c1a580 | 7873 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 7874 | |
ec6ba945 VZ |
7875 | /* reset IGU state skip FCoE L2 queue */ |
7876 | if (!IS_FCOE_FP(fp)) | |
7877 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 7878 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 7879 | |
15192a8c | 7880 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
7881 | /* We want to wait for completion in this context */ |
7882 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7883 | |
619c5cb6 VZ |
7884 | /* Prepare the INIT parameters */ |
7885 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 7886 | |
619c5cb6 VZ |
7887 | /* Set the command */ |
7888 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
7889 | ||
7890 | /* Change the state to INIT */ | |
7891 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7892 | if (rc) { | |
6383c0b3 | 7893 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
7894 | return rc; |
7895 | } | |
ec6ba945 | 7896 | |
51c1a580 | 7897 | DP(NETIF_MSG_IFUP, "init complete\n"); |
6383c0b3 AE |
7898 | |
7899 | ||
619c5cb6 VZ |
7900 | /* Now move the Queue to the SETUP state... */ |
7901 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 7902 | |
619c5cb6 VZ |
7903 | /* Set QUEUE flags */ |
7904 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 7905 | |
619c5cb6 | 7906 | /* Set general SETUP parameters */ |
6383c0b3 AE |
7907 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
7908 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 7909 | |
6383c0b3 | 7910 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
7911 | &setup_params->rxq_params); |
7912 | ||
6383c0b3 AE |
7913 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
7914 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
7915 | |
7916 | /* Set the command */ | |
7917 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
7918 | ||
7919 | /* Change the state to SETUP */ | |
7920 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
7921 | if (rc) { |
7922 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
7923 | return rc; | |
7924 | } | |
7925 | ||
7926 | /* loop through the relevant tx-only indices */ | |
7927 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7928 | tx_index < fp->max_cos; | |
7929 | tx_index++) { | |
7930 | ||
7931 | /* prepare and send tx-only ramrod*/ | |
7932 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
7933 | tx_only_params, tx_index, leading); | |
7934 | if (rc) { | |
7935 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
7936 | fp->index, tx_index); | |
7937 | return rc; | |
7938 | } | |
7939 | } | |
523224a3 | 7940 | |
34f80b04 | 7941 | return rc; |
a2fbb9ea ET |
7942 | } |
7943 | ||
619c5cb6 | 7944 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 7945 | { |
619c5cb6 | 7946 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 7947 | struct bnx2x_fp_txdata *txdata; |
3b603066 | 7948 | struct bnx2x_queue_state_params q_params = {NULL}; |
6383c0b3 AE |
7949 | int rc, tx_index; |
7950 | ||
51c1a580 | 7951 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 7952 | |
15192a8c | 7953 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
7954 | /* We want to wait for completion in this context */ |
7955 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7956 | |
6383c0b3 AE |
7957 | |
7958 | /* close tx-only connections */ | |
7959 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7960 | tx_index < fp->max_cos; | |
7961 | tx_index++){ | |
7962 | ||
7963 | /* ascertain this is a normal queue*/ | |
65565884 | 7964 | txdata = fp->txdata_ptr[tx_index]; |
6383c0b3 | 7965 | |
51c1a580 | 7966 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
6383c0b3 AE |
7967 | txdata->txq_index); |
7968 | ||
7969 | /* send halt terminate on tx-only connection */ | |
7970 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
7971 | memset(&q_params.params.terminate, 0, | |
7972 | sizeof(q_params.params.terminate)); | |
7973 | q_params.params.terminate.cid_index = tx_index; | |
7974 | ||
7975 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7976 | if (rc) | |
7977 | return rc; | |
7978 | ||
7979 | /* send halt terminate on tx-only connection */ | |
7980 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
7981 | memset(&q_params.params.cfc_del, 0, | |
7982 | sizeof(q_params.params.cfc_del)); | |
7983 | q_params.params.cfc_del.cid_index = tx_index; | |
7984 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7985 | if (rc) | |
7986 | return rc; | |
7987 | } | |
7988 | /* Stop the primary connection: */ | |
7989 | /* ...halt the connection */ | |
619c5cb6 VZ |
7990 | q_params.cmd = BNX2X_Q_CMD_HALT; |
7991 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7992 | if (rc) | |
da5a662a | 7993 | return rc; |
a2fbb9ea | 7994 | |
6383c0b3 | 7995 | /* ...terminate the connection */ |
619c5cb6 | 7996 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
7997 | memset(&q_params.params.terminate, 0, |
7998 | sizeof(q_params.params.terminate)); | |
7999 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
8000 | rc = bnx2x_queue_state_change(bp, &q_params); |
8001 | if (rc) | |
523224a3 | 8002 | return rc; |
6383c0b3 | 8003 | /* ...delete cfc entry */ |
619c5cb6 | 8004 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
8005 | memset(&q_params.params.cfc_del, 0, |
8006 | sizeof(q_params.params.cfc_del)); | |
8007 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 8008 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
8009 | } |
8010 | ||
8011 | ||
34f80b04 EG |
8012 | static void bnx2x_reset_func(struct bnx2x *bp) |
8013 | { | |
8014 | int port = BP_PORT(bp); | |
8015 | int func = BP_FUNC(bp); | |
f2e0899f | 8016 | int i; |
523224a3 DK |
8017 | |
8018 | /* Disable the function in the FW */ | |
8019 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
8020 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
8021 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
8022 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
8023 | ||
8024 | /* FP SBs */ | |
ec6ba945 | 8025 | for_each_eth_queue(bp, i) { |
523224a3 | 8026 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 8027 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8028 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
8029 | SB_DISABLED); | |
523224a3 DK |
8030 | } |
8031 | ||
619c5cb6 VZ |
8032 | #ifdef BCM_CNIC |
8033 | /* CNIC SB */ | |
8034 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
8035 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), | |
8036 | SB_DISABLED); | |
8037 | #endif | |
523224a3 | 8038 | /* SP SB */ |
619c5cb6 | 8039 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8040 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
8041 | SB_DISABLED); | |
523224a3 DK |
8042 | |
8043 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
8044 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
8045 | 0); | |
34f80b04 EG |
8046 | |
8047 | /* Configure IGU */ | |
f2e0899f DK |
8048 | if (bp->common.int_block == INT_BLOCK_HC) { |
8049 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
8050 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
8051 | } else { | |
8052 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
8053 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
8054 | } | |
34f80b04 | 8055 | |
37b091ba MC |
8056 | #ifdef BCM_CNIC |
8057 | /* Disable Timer scan */ | |
8058 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
8059 | /* | |
8060 | * Wait for at least 10ms and up to 2 second for the timers scan to | |
8061 | * complete | |
8062 | */ | |
8063 | for (i = 0; i < 200; i++) { | |
8064 | msleep(10); | |
8065 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) | |
8066 | break; | |
8067 | } | |
8068 | #endif | |
34f80b04 | 8069 | /* Clear ILT */ |
f2e0899f DK |
8070 | bnx2x_clear_func_ilt(bp, func); |
8071 | ||
8072 | /* Timers workaround bug for E2: if this is vnic-3, | |
8073 | * we need to set the entire ilt range for this timers. | |
8074 | */ | |
619c5cb6 | 8075 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
8076 | struct ilt_client_info ilt_cli; |
8077 | /* use dummy TM client */ | |
8078 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
8079 | ilt_cli.start = 0; | |
8080 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
8081 | ilt_cli.client_num = ILT_CLIENT_TM; | |
8082 | ||
8083 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
8084 | } | |
8085 | ||
8086 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 8087 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 8088 | bnx2x_pf_disable(bp); |
523224a3 DK |
8089 | |
8090 | bp->dmae_ready = 0; | |
34f80b04 EG |
8091 | } |
8092 | ||
8093 | static void bnx2x_reset_port(struct bnx2x *bp) | |
8094 | { | |
8095 | int port = BP_PORT(bp); | |
8096 | u32 val; | |
8097 | ||
619c5cb6 VZ |
8098 | /* Reset physical Link */ |
8099 | bnx2x__link_reset(bp); | |
8100 | ||
34f80b04 EG |
8101 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
8102 | ||
8103 | /* Do not rcv packets to BRB */ | |
8104 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
8105 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
8106 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
8107 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
8108 | ||
8109 | /* Configure AEU */ | |
8110 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
8111 | ||
8112 | msleep(100); | |
8113 | /* Check for BRB port occupancy */ | |
8114 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
8115 | if (val) | |
8116 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 8117 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
8118 | |
8119 | /* TODO: Close Doorbell port? */ | |
8120 | } | |
8121 | ||
1191cb83 | 8122 | static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 8123 | { |
3b603066 | 8124 | struct bnx2x_func_state_params func_params = {NULL}; |
34f80b04 | 8125 | |
619c5cb6 VZ |
8126 | /* Prepare parameters for function state transitions */ |
8127 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 8128 | |
619c5cb6 VZ |
8129 | func_params.f_obj = &bp->func_obj; |
8130 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 8131 | |
619c5cb6 | 8132 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 8133 | |
619c5cb6 | 8134 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
8135 | } |
8136 | ||
1191cb83 | 8137 | static int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 8138 | { |
3b603066 | 8139 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 | 8140 | int rc; |
228241eb | 8141 | |
619c5cb6 VZ |
8142 | /* Prepare parameters for function state transitions */ |
8143 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
8144 | func_params.f_obj = &bp->func_obj; | |
8145 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 8146 | |
619c5cb6 VZ |
8147 | /* |
8148 | * Try to stop the function the 'good way'. If fails (in case | |
8149 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
8150 | * not in a debug mode, perform a state transaction in order to | |
8151 | * enable further HW_RESET transaction. | |
8152 | */ | |
8153 | rc = bnx2x_func_state_change(bp, &func_params); | |
8154 | if (rc) { | |
34f80b04 | 8155 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 8156 | return rc; |
34f80b04 | 8157 | #else |
51c1a580 | 8158 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
619c5cb6 VZ |
8159 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
8160 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 8161 | #endif |
228241eb | 8162 | } |
a2fbb9ea | 8163 | |
619c5cb6 VZ |
8164 | return 0; |
8165 | } | |
523224a3 | 8166 | |
619c5cb6 VZ |
8167 | /** |
8168 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
8169 | * | |
8170 | * @bp: driver handle | |
8171 | * @unload_mode: requested function's unload mode | |
8172 | * | |
8173 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
8174 | */ | |
8175 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
8176 | { | |
8177 | u32 reset_code = 0; | |
8178 | int port = BP_PORT(bp); | |
3101c2bc | 8179 | |
619c5cb6 | 8180 | /* Select the UNLOAD request mode */ |
65abd74d YG |
8181 | if (unload_mode == UNLOAD_NORMAL) |
8182 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
8183 | ||
7d0446c2 | 8184 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 8185 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 8186 | |
7d0446c2 | 8187 | else if (bp->wol) { |
65abd74d YG |
8188 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
8189 | u8 *mac_addr = bp->dev->dev_addr; | |
8190 | u32 val; | |
f9977903 DK |
8191 | u16 pmc; |
8192 | ||
65abd74d | 8193 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
8194 | * preserve entry 0 which is used by the PMF |
8195 | */ | |
3395a033 | 8196 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
8197 | |
8198 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
8199 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
8200 | ||
8201 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
8202 | (mac_addr[4] << 8) | mac_addr[5]; | |
8203 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
8204 | ||
f9977903 DK |
8205 | /* Enable the PME and clear the status */ |
8206 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); | |
8207 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; | |
8208 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); | |
8209 | ||
65abd74d YG |
8210 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
8211 | ||
8212 | } else | |
8213 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 8214 | |
619c5cb6 VZ |
8215 | /* Send the request to the MCP */ |
8216 | if (!BP_NOMCP(bp)) | |
8217 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
8218 | else { | |
8219 | int path = BP_PATH(bp); | |
8220 | ||
51c1a580 | 8221 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8222 | path, load_count[path][0], load_count[path][1], |
8223 | load_count[path][2]); | |
8224 | load_count[path][0]--; | |
8225 | load_count[path][1 + port]--; | |
51c1a580 | 8226 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8227 | path, load_count[path][0], load_count[path][1], |
8228 | load_count[path][2]); | |
8229 | if (load_count[path][0] == 0) | |
8230 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; | |
8231 | else if (load_count[path][1 + port] == 0) | |
8232 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; | |
8233 | else | |
8234 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
8235 | } | |
8236 | ||
8237 | return reset_code; | |
8238 | } | |
8239 | ||
8240 | /** | |
8241 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
8242 | * | |
8243 | * @bp: driver handle | |
8244 | */ | |
8245 | void bnx2x_send_unload_done(struct bnx2x *bp) | |
8246 | { | |
8247 | /* Report UNLOAD_DONE to MCP */ | |
8248 | if (!BP_NOMCP(bp)) | |
8249 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
8250 | } | |
8251 | ||
1191cb83 | 8252 | static int bnx2x_func_wait_started(struct bnx2x *bp) |
6debea87 DK |
8253 | { |
8254 | int tout = 50; | |
8255 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
8256 | ||
8257 | if (!bp->port.pmf) | |
8258 | return 0; | |
8259 | ||
8260 | /* | |
8261 | * (assumption: No Attention from MCP at this stage) | |
8262 | * PMF probably in the middle of TXdisable/enable transaction | |
8263 | * 1. Sync IRS for default SB | |
8264 | * 2. Sync SP queue - this guarantes us that attention handling started | |
8265 | * 3. Wait, that TXdisable/enable transaction completes | |
8266 | * | |
8267 | * 1+2 guranty that if DCBx attention was scheduled it already changed | |
8268 | * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy | |
8269 | * received complettion for the transaction the state is TX_STOPPED. | |
8270 | * State will return to STARTED after completion of TX_STOPPED-->STARTED | |
8271 | * transaction. | |
8272 | */ | |
8273 | ||
8274 | /* make sure default SB ISR is done */ | |
8275 | if (msix) | |
8276 | synchronize_irq(bp->msix_table[0].vector); | |
8277 | else | |
8278 | synchronize_irq(bp->pdev->irq); | |
8279 | ||
8280 | flush_workqueue(bnx2x_wq); | |
8281 | ||
8282 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8283 | BNX2X_F_STATE_STARTED && tout--) | |
8284 | msleep(20); | |
8285 | ||
8286 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8287 | BNX2X_F_STATE_STARTED) { | |
8288 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 8289 | BNX2X_ERR("Wrong function state\n"); |
6debea87 DK |
8290 | return -EBUSY; |
8291 | #else | |
8292 | /* | |
8293 | * Failed to complete the transaction in a "good way" | |
8294 | * Force both transactions with CLR bit | |
8295 | */ | |
3b603066 | 8296 | struct bnx2x_func_state_params func_params = {NULL}; |
6debea87 | 8297 | |
51c1a580 MS |
8298 | DP(NETIF_MSG_IFDOWN, |
8299 | "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); | |
6debea87 DK |
8300 | |
8301 | func_params.f_obj = &bp->func_obj; | |
8302 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
8303 | &func_params.ramrod_flags); | |
8304 | ||
8305 | /* STARTED-->TX_ST0PPED */ | |
8306 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
8307 | bnx2x_func_state_change(bp, &func_params); | |
8308 | ||
8309 | /* TX_ST0PPED-->STARTED */ | |
8310 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
8311 | return bnx2x_func_state_change(bp, &func_params); | |
8312 | #endif | |
8313 | } | |
8314 | ||
8315 | return 0; | |
8316 | } | |
8317 | ||
619c5cb6 VZ |
8318 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) |
8319 | { | |
8320 | int port = BP_PORT(bp); | |
6383c0b3 AE |
8321 | int i, rc = 0; |
8322 | u8 cos; | |
3b603066 | 8323 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 VZ |
8324 | u32 reset_code; |
8325 | ||
8326 | /* Wait until tx fastpath tasks complete */ | |
8327 | for_each_tx_queue(bp, i) { | |
8328 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
8329 | ||
6383c0b3 | 8330 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 8331 | rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); |
619c5cb6 VZ |
8332 | #ifdef BNX2X_STOP_ON_ERROR |
8333 | if (rc) | |
8334 | return; | |
8335 | #endif | |
8336 | } | |
8337 | ||
8338 | /* Give HW time to discard old tx messages */ | |
8339 | usleep_range(1000, 1000); | |
8340 | ||
8341 | /* Clean all ETH MACs */ | |
15192a8c BW |
8342 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, |
8343 | false); | |
619c5cb6 VZ |
8344 | if (rc < 0) |
8345 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
8346 | ||
8347 | /* Clean up UC list */ | |
15192a8c | 8348 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, |
619c5cb6 VZ |
8349 | true); |
8350 | if (rc < 0) | |
51c1a580 MS |
8351 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
8352 | rc); | |
619c5cb6 VZ |
8353 | |
8354 | /* Disable LLH */ | |
8355 | if (!CHIP_IS_E1(bp)) | |
8356 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
8357 | ||
8358 | /* Set "drop all" (stop Rx). | |
8359 | * We need to take a netif_addr_lock() here in order to prevent | |
8360 | * a race between the completion code and this code. | |
8361 | */ | |
8362 | netif_addr_lock_bh(bp->dev); | |
8363 | /* Schedule the rx_mode command */ | |
8364 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
8365 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
8366 | else | |
8367 | bnx2x_set_storm_rx_mode(bp); | |
8368 | ||
8369 | /* Cleanup multicast configuration */ | |
8370 | rparam.mcast_obj = &bp->mcast_obj; | |
8371 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
8372 | if (rc < 0) | |
8373 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
8374 | ||
8375 | netif_addr_unlock_bh(bp->dev); | |
8376 | ||
8377 | ||
6debea87 DK |
8378 | |
8379 | /* | |
8380 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
8381 | * this function should perform FUNC, PORT or COMMON HW | |
8382 | * reset. | |
8383 | */ | |
8384 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
8385 | ||
8386 | /* | |
8387 | * (assumption: No Attention from MCP at this stage) | |
8388 | * PMF probably in the middle of TXdisable/enable transaction | |
8389 | */ | |
8390 | rc = bnx2x_func_wait_started(bp); | |
8391 | if (rc) { | |
8392 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
8393 | #ifdef BNX2X_STOP_ON_ERROR | |
8394 | return; | |
8395 | #endif | |
8396 | } | |
8397 | ||
34f80b04 | 8398 | /* Close multi and leading connections |
619c5cb6 VZ |
8399 | * Completions for ramrods are collected in a synchronous way |
8400 | */ | |
523224a3 | 8401 | for_each_queue(bp, i) |
619c5cb6 | 8402 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
8403 | #ifdef BNX2X_STOP_ON_ERROR |
8404 | return; | |
8405 | #else | |
228241eb | 8406 | goto unload_error; |
523224a3 | 8407 | #endif |
619c5cb6 VZ |
8408 | /* If SP settings didn't get completed so far - something |
8409 | * very wrong has happen. | |
8410 | */ | |
8411 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
8412 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 8413 | |
619c5cb6 VZ |
8414 | #ifndef BNX2X_STOP_ON_ERROR |
8415 | unload_error: | |
8416 | #endif | |
523224a3 | 8417 | rc = bnx2x_func_stop(bp); |
da5a662a | 8418 | if (rc) { |
523224a3 | 8419 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 8420 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 8421 | return; |
523224a3 | 8422 | #endif |
34f80b04 | 8423 | } |
a2fbb9ea | 8424 | |
523224a3 DK |
8425 | /* Disable HW interrupts, NAPI */ |
8426 | bnx2x_netif_stop(bp, 1); | |
8427 | ||
8428 | /* Release IRQs */ | |
d6214d7a | 8429 | bnx2x_free_irq(bp); |
523224a3 | 8430 | |
a2fbb9ea | 8431 | /* Reset the chip */ |
619c5cb6 VZ |
8432 | rc = bnx2x_reset_hw(bp, reset_code); |
8433 | if (rc) | |
8434 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 8435 | |
356e2385 | 8436 | |
619c5cb6 VZ |
8437 | /* Report UNLOAD_DONE to MCP */ |
8438 | bnx2x_send_unload_done(bp); | |
72fd0718 VZ |
8439 | } |
8440 | ||
9f6c9258 | 8441 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
8442 | { |
8443 | u32 val; | |
8444 | ||
51c1a580 | 8445 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
72fd0718 VZ |
8446 | |
8447 | if (CHIP_IS_E1(bp)) { | |
8448 | int port = BP_PORT(bp); | |
8449 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
8450 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
8451 | ||
8452 | val = REG_RD(bp, addr); | |
8453 | val &= ~(0x300); | |
8454 | REG_WR(bp, addr, val); | |
619c5cb6 | 8455 | } else { |
72fd0718 VZ |
8456 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
8457 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
8458 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
8459 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
8460 | } | |
8461 | } | |
8462 | ||
72fd0718 VZ |
8463 | /* Close gates #2, #3 and #4: */ |
8464 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
8465 | { | |
c9ee9206 | 8466 | u32 val; |
72fd0718 VZ |
8467 | |
8468 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
8469 | if (!CHIP_IS_E1(bp)) { | |
8470 | /* #4 */ | |
c9ee9206 | 8471 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 8472 | /* #2 */ |
c9ee9206 | 8473 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
8474 | } |
8475 | ||
8476 | /* #3 */ | |
c9ee9206 VZ |
8477 | if (CHIP_IS_E1x(bp)) { |
8478 | /* Prevent interrupts from HC on both ports */ | |
8479 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
8480 | REG_WR(bp, HC_REG_CONFIG_1, | |
8481 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
8482 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
8483 | ||
8484 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
8485 | REG_WR(bp, HC_REG_CONFIG_0, | |
8486 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
8487 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
8488 | } else { | |
8489 | /* Prevent incomming interrupts in IGU */ | |
8490 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); | |
8491 | ||
8492 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
8493 | (!close) ? | |
8494 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
8495 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
8496 | } | |
72fd0718 | 8497 | |
51c1a580 | 8498 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
72fd0718 VZ |
8499 | close ? "closing" : "opening"); |
8500 | mmiowb(); | |
8501 | } | |
8502 | ||
8503 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
8504 | ||
8505 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
8506 | { | |
8507 | /* Do some magic... */ | |
8508 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
8509 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
8510 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
8511 | } | |
8512 | ||
e8920674 DK |
8513 | /** |
8514 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 8515 | * |
e8920674 DK |
8516 | * @bp: driver handle |
8517 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
8518 | */ |
8519 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
8520 | { | |
8521 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
8522 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
8523 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
8524 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
8525 | } | |
8526 | ||
f85582f8 | 8527 | /** |
e8920674 | 8528 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 8529 | * |
e8920674 DK |
8530 | * @bp: driver handle |
8531 | * @magic_val: old value of 'magic' bit. | |
8532 | * | |
8533 | * Takes care of CLP configurations. | |
72fd0718 VZ |
8534 | */ |
8535 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
8536 | { | |
8537 | u32 shmem; | |
8538 | u32 validity_offset; | |
8539 | ||
51c1a580 | 8540 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
72fd0718 VZ |
8541 | |
8542 | /* Set `magic' bit in order to save MF config */ | |
8543 | if (!CHIP_IS_E1(bp)) | |
8544 | bnx2x_clp_reset_prep(bp, magic_val); | |
8545 | ||
8546 | /* Get shmem offset */ | |
8547 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
8548 | validity_offset = offsetof(struct shmem_region, validity_map[0]); | |
8549 | ||
8550 | /* Clear validity map flags */ | |
8551 | if (shmem > 0) | |
8552 | REG_WR(bp, shmem + validity_offset, 0); | |
8553 | } | |
8554 | ||
8555 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
8556 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
8557 | ||
e8920674 DK |
8558 | /** |
8559 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 8560 | * |
e8920674 | 8561 | * @bp: driver handle |
72fd0718 | 8562 | */ |
1191cb83 | 8563 | static void bnx2x_mcp_wait_one(struct bnx2x *bp) |
72fd0718 VZ |
8564 | { |
8565 | /* special handling for emulation and FPGA, | |
8566 | wait 10 times longer */ | |
8567 | if (CHIP_REV_IS_SLOW(bp)) | |
8568 | msleep(MCP_ONE_TIMEOUT*10); | |
8569 | else | |
8570 | msleep(MCP_ONE_TIMEOUT); | |
8571 | } | |
8572 | ||
1b6e2ceb DK |
8573 | /* |
8574 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
8575 | */ | |
8576 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 8577 | { |
1b6e2ceb DK |
8578 | int cnt = 0; |
8579 | u32 val = 0; | |
72fd0718 | 8580 | |
1b6e2ceb DK |
8581 | do { |
8582 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
8583 | if (bp->common.shmem_base) { | |
8584 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
8585 | if (val & SHR_MEM_VALIDITY_MB) | |
8586 | return 0; | |
8587 | } | |
72fd0718 | 8588 | |
1b6e2ceb | 8589 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 8590 | |
1b6e2ceb | 8591 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 8592 | |
1b6e2ceb | 8593 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 8594 | |
1b6e2ceb DK |
8595 | return -ENODEV; |
8596 | } | |
72fd0718 | 8597 | |
1b6e2ceb DK |
8598 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
8599 | { | |
8600 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 8601 | |
72fd0718 VZ |
8602 | /* Restore the `magic' bit value */ |
8603 | if (!CHIP_IS_E1(bp)) | |
8604 | bnx2x_clp_reset_done(bp, magic_val); | |
8605 | ||
8606 | return rc; | |
8607 | } | |
8608 | ||
8609 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
8610 | { | |
8611 | if (!CHIP_IS_E1(bp)) { | |
8612 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
8613 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
8614 | mmiowb(); |
8615 | } | |
8616 | } | |
8617 | ||
8618 | /* | |
8619 | * Reset the whole chip except for: | |
8620 | * - PCIE core | |
8621 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
8622 | * one reset bit) | |
8623 | * - IGU | |
8624 | * - MISC (including AEU) | |
8625 | * - GRC | |
8626 | * - RBCN, RBCP | |
8627 | */ | |
c9ee9206 | 8628 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
8629 | { |
8630 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 8631 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
8632 | |
8633 | /* | |
8634 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
8635 | * (per chip) blocks. | |
8636 | */ | |
8637 | global_bits2 = | |
8638 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
8639 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 8640 | |
8736c826 | 8641 | /* Don't reset the following blocks */ |
72fd0718 VZ |
8642 | not_reset_mask1 = |
8643 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
8644 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
8645 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
8646 | ||
8647 | not_reset_mask2 = | |
c9ee9206 | 8648 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
8649 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
8650 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
8651 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
8652 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
8653 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
8654 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
8655 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
8656 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
8657 | MISC_REGISTERS_RESET_REG_2_PGLC; | |
72fd0718 | 8658 | |
8736c826 VZ |
8659 | /* |
8660 | * Keep the following blocks in reset: | |
8661 | * - all xxMACs are handled by the bnx2x_link code. | |
8662 | */ | |
8663 | stay_reset2 = | |
8664 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
8665 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
8666 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
8667 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
8668 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
8669 | MISC_REGISTERS_RESET_REG_2_UMAC1 | | |
8670 | MISC_REGISTERS_RESET_REG_2_XMAC | | |
8671 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
8672 | ||
8673 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
8674 | reset_mask1 = 0xffffffff; |
8675 | ||
8676 | if (CHIP_IS_E1(bp)) | |
8677 | reset_mask2 = 0xffff; | |
8736c826 | 8678 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 8679 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
8680 | else if (CHIP_IS_E2(bp)) |
8681 | reset_mask2 = 0xfffff; | |
8682 | else /* CHIP_IS_E3 */ | |
8683 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
8684 | |
8685 | /* Don't reset global blocks unless we need to */ | |
8686 | if (!global) | |
8687 | reset_mask2 &= ~global_bits2; | |
8688 | ||
8689 | /* | |
8690 | * In case of attention in the QM, we need to reset PXP | |
8691 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
8692 | * because otherwise QM reset would release 'close the gates' shortly | |
8693 | * before resetting the PXP, then the PSWRQ would send a write | |
8694 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
8695 | * read the payload data from PSWWR, but PSWWR would not | |
8696 | * respond. The write queue in PGLUE would stuck, dmae commands | |
8697 | * would not return. Therefore it's important to reset the second | |
8698 | * reset register (containing the | |
8699 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
8700 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
8701 | * bit). | |
8702 | */ | |
72fd0718 VZ |
8703 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
8704 | reset_mask2 & (~not_reset_mask2)); | |
8705 | ||
c9ee9206 VZ |
8706 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
8707 | reset_mask1 & (~not_reset_mask1)); | |
8708 | ||
72fd0718 VZ |
8709 | barrier(); |
8710 | mmiowb(); | |
8711 | ||
8736c826 VZ |
8712 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
8713 | reset_mask2 & (~stay_reset2)); | |
8714 | ||
8715 | barrier(); | |
8716 | mmiowb(); | |
8717 | ||
c9ee9206 | 8718 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
8719 | mmiowb(); |
8720 | } | |
8721 | ||
c9ee9206 VZ |
8722 | /** |
8723 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
8724 | * It should get cleared in no more than 1s. | |
8725 | * | |
8726 | * @bp: driver handle | |
8727 | * | |
8728 | * It should get cleared in no more than 1s. Returns 0 if | |
8729 | * pending writes bit gets cleared. | |
8730 | */ | |
8731 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
8732 | { | |
8733 | u32 cnt = 1000; | |
8734 | u32 pend_bits = 0; | |
8735 | ||
8736 | do { | |
8737 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
8738 | ||
8739 | if (pend_bits == 0) | |
8740 | break; | |
8741 | ||
8742 | usleep_range(1000, 1000); | |
8743 | } while (cnt-- > 0); | |
8744 | ||
8745 | if (cnt <= 0) { | |
8746 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
8747 | pend_bits); | |
8748 | return -EBUSY; | |
8749 | } | |
8750 | ||
8751 | return 0; | |
8752 | } | |
8753 | ||
8754 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
8755 | { |
8756 | int cnt = 1000; | |
8757 | u32 val = 0; | |
8758 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
8759 | ||
8760 | ||
8761 | /* Empty the Tetris buffer, wait for 1s */ | |
8762 | do { | |
8763 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
8764 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
8765 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
8766 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
8767 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
8768 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && | |
8769 | ((port_is_idle_0 & 0x1) == 0x1) && | |
8770 | ((port_is_idle_1 & 0x1) == 0x1) && | |
8771 | (pgl_exp_rom2 == 0xffffffff)) | |
8772 | break; | |
c9ee9206 | 8773 | usleep_range(1000, 1000); |
72fd0718 VZ |
8774 | } while (cnt-- > 0); |
8775 | ||
8776 | if (cnt <= 0) { | |
51c1a580 MS |
8777 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
8778 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
72fd0718 VZ |
8779 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
8780 | pgl_exp_rom2); | |
8781 | return -EAGAIN; | |
8782 | } | |
8783 | ||
8784 | barrier(); | |
8785 | ||
8786 | /* Close gates #2, #3 and #4 */ | |
8787 | bnx2x_set_234_gates(bp, true); | |
8788 | ||
c9ee9206 VZ |
8789 | /* Poll for IGU VQs for 57712 and newer chips */ |
8790 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
8791 | return -EAGAIN; | |
8792 | ||
8793 | ||
72fd0718 VZ |
8794 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
8795 | ||
8796 | /* Clear "unprepared" bit */ | |
8797 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
8798 | barrier(); | |
8799 | ||
8800 | /* Make sure all is written to the chip before the reset */ | |
8801 | mmiowb(); | |
8802 | ||
8803 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
8804 | * PSWHST, GRC and PSWRD Tetris buffer. | |
8805 | */ | |
c9ee9206 | 8806 | usleep_range(1000, 1000); |
72fd0718 VZ |
8807 | |
8808 | /* Prepare to chip reset: */ | |
8809 | /* MCP */ | |
c9ee9206 VZ |
8810 | if (global) |
8811 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
8812 | |
8813 | /* PXP */ | |
8814 | bnx2x_pxp_prep(bp); | |
8815 | barrier(); | |
8816 | ||
8817 | /* reset the chip */ | |
c9ee9206 | 8818 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
8819 | barrier(); |
8820 | ||
8821 | /* Recover after reset: */ | |
8822 | /* MCP */ | |
c9ee9206 | 8823 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
8824 | return -EAGAIN; |
8825 | ||
c9ee9206 VZ |
8826 | /* TBD: Add resetting the NO_MCP mode DB here */ |
8827 | ||
72fd0718 VZ |
8828 | /* PXP */ |
8829 | bnx2x_pxp_prep(bp); | |
8830 | ||
8831 | /* Open the gates #2, #3 and #4 */ | |
8832 | bnx2x_set_234_gates(bp, false); | |
8833 | ||
8834 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
8835 | * reset state, re-enable attentions. */ | |
8836 | ||
a2fbb9ea ET |
8837 | return 0; |
8838 | } | |
8839 | ||
c9ee9206 | 8840 | int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
8841 | { |
8842 | int rc = 0; | |
c9ee9206 | 8843 | bool global = bnx2x_reset_is_global(bp); |
95c6c616 AE |
8844 | u32 load_code; |
8845 | ||
8846 | /* if not going to reset MCP - load "fake" driver to reset HW while | |
8847 | * driver is owner of the HW | |
8848 | */ | |
8849 | if (!global && !BP_NOMCP(bp)) { | |
8850 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0); | |
8851 | if (!load_code) { | |
8852 | BNX2X_ERR("MCP response failure, aborting\n"); | |
8853 | rc = -EAGAIN; | |
8854 | goto exit_leader_reset; | |
8855 | } | |
8856 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && | |
8857 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { | |
8858 | BNX2X_ERR("MCP unexpected resp, aborting\n"); | |
8859 | rc = -EAGAIN; | |
8860 | goto exit_leader_reset2; | |
8861 | } | |
8862 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
8863 | if (!load_code) { | |
8864 | BNX2X_ERR("MCP response failure, aborting\n"); | |
8865 | rc = -EAGAIN; | |
8866 | goto exit_leader_reset2; | |
8867 | } | |
8868 | } | |
c9ee9206 | 8869 | |
72fd0718 | 8870 | /* Try to recover after the failure */ |
c9ee9206 | 8871 | if (bnx2x_process_kill(bp, global)) { |
51c1a580 MS |
8872 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
8873 | BP_PATH(bp)); | |
72fd0718 | 8874 | rc = -EAGAIN; |
95c6c616 | 8875 | goto exit_leader_reset2; |
72fd0718 VZ |
8876 | } |
8877 | ||
c9ee9206 VZ |
8878 | /* |
8879 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
8880 | * state. | |
8881 | */ | |
72fd0718 | 8882 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
8883 | if (global) |
8884 | bnx2x_clear_reset_global(bp); | |
72fd0718 | 8885 | |
95c6c616 AE |
8886 | exit_leader_reset2: |
8887 | /* unload "fake driver" if it was loaded */ | |
8888 | if (!global && !BP_NOMCP(bp)) { | |
8889 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); | |
8890 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
8891 | } | |
72fd0718 VZ |
8892 | exit_leader_reset: |
8893 | bp->is_leader = 0; | |
c9ee9206 VZ |
8894 | bnx2x_release_leader_lock(bp); |
8895 | smp_mb(); | |
72fd0718 VZ |
8896 | return rc; |
8897 | } | |
8898 | ||
1191cb83 | 8899 | static void bnx2x_recovery_failed(struct bnx2x *bp) |
c9ee9206 VZ |
8900 | { |
8901 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
8902 | ||
8903 | /* Disconnect this device */ | |
8904 | netif_device_detach(bp->dev); | |
8905 | ||
8906 | /* | |
8907 | * Block ifup for all function on this engine until "process kill" | |
8908 | * or power cycle. | |
8909 | */ | |
8910 | bnx2x_set_reset_in_progress(bp); | |
8911 | ||
8912 | /* Shut down the power */ | |
8913 | bnx2x_set_power_state(bp, PCI_D3hot); | |
8914 | ||
8915 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
8916 | ||
8917 | smp_mb(); | |
8918 | } | |
8919 | ||
8920 | /* | |
8921 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 8922 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
8923 | * will never be called when netif_running(bp->dev) is false. |
8924 | */ | |
8925 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
8926 | { | |
c9ee9206 | 8927 | bool global = false; |
7a752993 | 8928 | u32 error_recovered, error_unrecovered; |
95c6c616 | 8929 | bool is_parity; |
c9ee9206 | 8930 | |
72fd0718 VZ |
8931 | DP(NETIF_MSG_HW, "Handling parity\n"); |
8932 | while (1) { | |
8933 | switch (bp->recovery_state) { | |
8934 | case BNX2X_RECOVERY_INIT: | |
8935 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
95c6c616 AE |
8936 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
8937 | WARN_ON(!is_parity); | |
c9ee9206 | 8938 | |
72fd0718 | 8939 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
8940 | if (bnx2x_trylock_leader_lock(bp)) { |
8941 | bnx2x_set_reset_in_progress(bp); | |
8942 | /* | |
8943 | * Check if there is a global attention and if | |
8944 | * there was a global attention, set the global | |
8945 | * reset bit. | |
8946 | */ | |
8947 | ||
8948 | if (global) | |
8949 | bnx2x_set_reset_global(bp); | |
8950 | ||
72fd0718 | 8951 | bp->is_leader = 1; |
c9ee9206 | 8952 | } |
72fd0718 VZ |
8953 | |
8954 | /* Stop the driver */ | |
8955 | /* If interface has been removed - break */ | |
8956 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) | |
8957 | return; | |
8958 | ||
8959 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 | 8960 | |
c9ee9206 VZ |
8961 | /* Ensure "is_leader", MCP command sequence and |
8962 | * "recovery_state" update values are seen on other | |
8963 | * CPUs. | |
72fd0718 | 8964 | */ |
c9ee9206 | 8965 | smp_mb(); |
72fd0718 VZ |
8966 | break; |
8967 | ||
8968 | case BNX2X_RECOVERY_WAIT: | |
8969 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
8970 | if (bp->is_leader) { | |
c9ee9206 | 8971 | int other_engine = BP_PATH(bp) ? 0 : 1; |
889b9af3 AE |
8972 | bool other_load_status = |
8973 | bnx2x_get_load_status(bp, other_engine); | |
8974 | bool load_status = | |
8975 | bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
8976 | global = bnx2x_reset_is_global(bp); |
8977 | ||
8978 | /* | |
8979 | * In case of a parity in a global block, let | |
8980 | * the first leader that performs a | |
8981 | * leader_reset() reset the global blocks in | |
8982 | * order to clear global attentions. Otherwise | |
8983 | * the the gates will remain closed for that | |
8984 | * engine. | |
8985 | */ | |
889b9af3 AE |
8986 | if (load_status || |
8987 | (global && other_load_status)) { | |
72fd0718 VZ |
8988 | /* Wait until all other functions get |
8989 | * down. | |
8990 | */ | |
7be08a72 | 8991 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
8992 | HZ/10); |
8993 | return; | |
8994 | } else { | |
8995 | /* If all other functions got down - | |
8996 | * try to bring the chip back to | |
8997 | * normal. In any case it's an exit | |
8998 | * point for a leader. | |
8999 | */ | |
c9ee9206 VZ |
9000 | if (bnx2x_leader_reset(bp)) { |
9001 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
9002 | return; |
9003 | } | |
9004 | ||
c9ee9206 VZ |
9005 | /* If we are here, means that the |
9006 | * leader has succeeded and doesn't | |
9007 | * want to be a leader any more. Try | |
9008 | * to continue as a none-leader. | |
9009 | */ | |
9010 | break; | |
72fd0718 VZ |
9011 | } |
9012 | } else { /* non-leader */ | |
c9ee9206 | 9013 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
9014 | /* Try to get a LEADER_LOCK HW lock as |
9015 | * long as a former leader may have | |
9016 | * been unloaded by the user or | |
9017 | * released a leadership by another | |
9018 | * reason. | |
9019 | */ | |
c9ee9206 | 9020 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
9021 | /* I'm a leader now! Restart a |
9022 | * switch case. | |
9023 | */ | |
9024 | bp->is_leader = 1; | |
9025 | break; | |
9026 | } | |
9027 | ||
7be08a72 | 9028 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9029 | HZ/10); |
9030 | return; | |
9031 | ||
c9ee9206 VZ |
9032 | } else { |
9033 | /* | |
9034 | * If there was a global attention, wait | |
9035 | * for it to be cleared. | |
9036 | */ | |
9037 | if (bnx2x_reset_is_global(bp)) { | |
9038 | schedule_delayed_work( | |
7be08a72 AE |
9039 | &bp->sp_rtnl_task, |
9040 | HZ/10); | |
c9ee9206 VZ |
9041 | return; |
9042 | } | |
9043 | ||
7a752993 AE |
9044 | error_recovered = |
9045 | bp->eth_stats.recoverable_error; | |
9046 | error_unrecovered = | |
9047 | bp->eth_stats.unrecoverable_error; | |
95c6c616 AE |
9048 | bp->recovery_state = |
9049 | BNX2X_RECOVERY_NIC_LOADING; | |
9050 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { | |
7a752993 | 9051 | error_unrecovered++; |
95c6c616 | 9052 | netdev_err(bp->dev, |
51c1a580 | 9053 | "Recovery failed. Power cycle needed\n"); |
95c6c616 AE |
9054 | /* Disconnect this device */ |
9055 | netif_device_detach(bp->dev); | |
9056 | /* Shut down the power */ | |
9057 | bnx2x_set_power_state( | |
9058 | bp, PCI_D3hot); | |
9059 | smp_mb(); | |
9060 | } else { | |
c9ee9206 VZ |
9061 | bp->recovery_state = |
9062 | BNX2X_RECOVERY_DONE; | |
7a752993 | 9063 | error_recovered++; |
c9ee9206 VZ |
9064 | smp_mb(); |
9065 | } | |
7a752993 AE |
9066 | bp->eth_stats.recoverable_error = |
9067 | error_recovered; | |
9068 | bp->eth_stats.unrecoverable_error = | |
9069 | error_unrecovered; | |
c9ee9206 | 9070 | |
72fd0718 VZ |
9071 | return; |
9072 | } | |
9073 | } | |
9074 | default: | |
9075 | return; | |
9076 | } | |
9077 | } | |
9078 | } | |
9079 | ||
56ad3152 MS |
9080 | static int bnx2x_close(struct net_device *dev); |
9081 | ||
72fd0718 VZ |
9082 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
9083 | * scheduled on a general queue in order to prevent a dead lock. | |
9084 | */ | |
7be08a72 | 9085 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 9086 | { |
7be08a72 | 9087 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
9088 | |
9089 | rtnl_lock(); | |
9090 | ||
9091 | if (!netif_running(bp->dev)) | |
7be08a72 AE |
9092 | goto sp_rtnl_exit; |
9093 | ||
9094 | /* if stop on error is defined no recovery flows should be executed */ | |
9095 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 9096 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
7be08a72 | 9097 | "you will need to reboot when done\n"); |
b1fb8740 | 9098 | goto sp_rtnl_not_reset; |
7be08a72 | 9099 | #endif |
34f80b04 | 9100 | |
7be08a72 AE |
9101 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
9102 | /* | |
b1fb8740 VZ |
9103 | * Clear all pending SP commands as we are going to reset the |
9104 | * function anyway. | |
7be08a72 | 9105 | */ |
b1fb8740 VZ |
9106 | bp->sp_rtnl_state = 0; |
9107 | smp_mb(); | |
9108 | ||
72fd0718 | 9109 | bnx2x_parity_recover(bp); |
b1fb8740 VZ |
9110 | |
9111 | goto sp_rtnl_exit; | |
9112 | } | |
9113 | ||
9114 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
9115 | /* | |
9116 | * Clear all pending SP commands as we are going to reset the | |
9117 | * function anyway. | |
9118 | */ | |
9119 | bp->sp_rtnl_state = 0; | |
9120 | smp_mb(); | |
9121 | ||
72fd0718 VZ |
9122 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); |
9123 | bnx2x_nic_load(bp, LOAD_NORMAL); | |
b1fb8740 VZ |
9124 | |
9125 | goto sp_rtnl_exit; | |
72fd0718 | 9126 | } |
b1fb8740 VZ |
9127 | #ifdef BNX2X_STOP_ON_ERROR |
9128 | sp_rtnl_not_reset: | |
9129 | #endif | |
9130 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
9131 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
a3348722 BW |
9132 | if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) |
9133 | bnx2x_after_function_update(bp); | |
8304859a AE |
9134 | /* |
9135 | * in case of fan failure we need to reset id if the "stop on error" | |
9136 | * debug flag is set, since we trying to prevent permanent overheating | |
9137 | * damage | |
9138 | */ | |
9139 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { | |
51c1a580 | 9140 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
8304859a AE |
9141 | netif_device_detach(bp->dev); |
9142 | bnx2x_close(bp->dev); | |
9143 | } | |
9144 | ||
7be08a72 | 9145 | sp_rtnl_exit: |
34f80b04 EG |
9146 | rtnl_unlock(); |
9147 | } | |
9148 | ||
a2fbb9ea ET |
9149 | /* end of nic load/unload */ |
9150 | ||
3deb8167 YR |
9151 | static void bnx2x_period_task(struct work_struct *work) |
9152 | { | |
9153 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
9154 | ||
9155 | if (!netif_running(bp->dev)) | |
9156 | goto period_task_exit; | |
9157 | ||
9158 | if (CHIP_REV_IS_SLOW(bp)) { | |
9159 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
9160 | goto period_task_exit; | |
9161 | } | |
9162 | ||
9163 | bnx2x_acquire_phy_lock(bp); | |
9164 | /* | |
9165 | * The barrier is needed to ensure the ordering between the writing to | |
9166 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
9167 | * the reading here. | |
9168 | */ | |
9169 | smp_mb(); | |
9170 | if (bp->port.pmf) { | |
9171 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
9172 | ||
9173 | /* Re-queue task in 1 sec */ | |
9174 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
9175 | } | |
9176 | ||
9177 | bnx2x_release_phy_lock(bp); | |
9178 | period_task_exit: | |
9179 | return; | |
9180 | } | |
9181 | ||
a2fbb9ea ET |
9182 | /* |
9183 | * Init service functions | |
9184 | */ | |
9185 | ||
8d96286a | 9186 | static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
9187 | { |
9188 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
9189 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
9190 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
9191 | } |
9192 | ||
f2e0899f | 9193 | static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) |
f1ef27ef | 9194 | { |
f2e0899f | 9195 | u32 reg = bnx2x_get_pretend_reg(bp); |
f1ef27ef EG |
9196 | |
9197 | /* Flush all outstanding writes */ | |
9198 | mmiowb(); | |
9199 | ||
9200 | /* Pretend to be function 0 */ | |
9201 | REG_WR(bp, reg, 0); | |
f2e0899f | 9202 | REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ |
f1ef27ef EG |
9203 | |
9204 | /* From now we are in the "like-E1" mode */ | |
9205 | bnx2x_int_disable(bp); | |
9206 | ||
9207 | /* Flush all outstanding writes */ | |
9208 | mmiowb(); | |
9209 | ||
f2e0899f DK |
9210 | /* Restore the original function */ |
9211 | REG_WR(bp, reg, BP_ABS_FUNC(bp)); | |
9212 | REG_RD(bp, reg); | |
f1ef27ef EG |
9213 | } |
9214 | ||
f2e0899f | 9215 | static inline void bnx2x_undi_int_disable(struct bnx2x *bp) |
f1ef27ef | 9216 | { |
f2e0899f | 9217 | if (CHIP_IS_E1(bp)) |
f1ef27ef | 9218 | bnx2x_int_disable(bp); |
f2e0899f DK |
9219 | else |
9220 | bnx2x_undi_int_disable_e1h(bp); | |
f1ef27ef EG |
9221 | } |
9222 | ||
452427b0 | 9223 | static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp) |
34f80b04 | 9224 | { |
452427b0 YM |
9225 | u32 val, base_addr, offset, mask, reset_reg; |
9226 | bool mac_stopped = false; | |
9227 | u8 port = BP_PORT(bp); | |
34f80b04 | 9228 | |
452427b0 | 9229 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
f16da43b | 9230 | |
452427b0 YM |
9231 | if (!CHIP_IS_E3(bp)) { |
9232 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
9233 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; | |
9234 | if ((mask & reset_reg) && val) { | |
9235 | u32 wb_data[2]; | |
9236 | BNX2X_DEV_INFO("Disable bmac Rx\n"); | |
9237 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM | |
9238 | : NIG_REG_INGRESS_BMAC0_MEM; | |
9239 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL | |
9240 | : BIGMAC_REGISTER_BMAC_CONTROL; | |
7a06a122 | 9241 | |
452427b0 YM |
9242 | /* |
9243 | * use rd/wr since we cannot use dmae. This is safe | |
9244 | * since MCP won't access the bus due to the request | |
9245 | * to unload, and no function on the path can be | |
9246 | * loaded at this time. | |
9247 | */ | |
9248 | wb_data[0] = REG_RD(bp, base_addr + offset); | |
9249 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); | |
9250 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; | |
9251 | REG_WR(bp, base_addr + offset, wb_data[0]); | |
9252 | REG_WR(bp, base_addr + offset + 0x4, wb_data[1]); | |
9253 | ||
9254 | } | |
9255 | BNX2X_DEV_INFO("Disable emac Rx\n"); | |
9256 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0); | |
9257 | ||
9258 | mac_stopped = true; | |
9259 | } else { | |
9260 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
9261 | BNX2X_DEV_INFO("Disable xmac Rx\n"); | |
9262 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
9263 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); | |
9264 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9265 | val & ~(1 << 1)); | |
9266 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9267 | val | (1 << 1)); | |
9268 | REG_WR(bp, base_addr + XMAC_REG_CTRL, 0); | |
9269 | mac_stopped = true; | |
9270 | } | |
9271 | mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; | |
9272 | if (mask & reset_reg) { | |
9273 | BNX2X_DEV_INFO("Disable umac Rx\n"); | |
9274 | base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
9275 | REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0); | |
9276 | mac_stopped = true; | |
9277 | } | |
9278 | } | |
9279 | ||
9280 | if (mac_stopped) | |
9281 | msleep(20); | |
9282 | ||
9283 | } | |
9284 | ||
9285 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) | |
9286 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) | |
9287 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) | |
9288 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) | |
9289 | ||
9290 | static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, | |
9291 | u8 inc) | |
9292 | { | |
9293 | u16 rcq, bd; | |
9294 | u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port)); | |
9295 | ||
9296 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; | |
9297 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; | |
9298 | ||
9299 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); | |
9300 | REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg); | |
9301 | ||
9302 | BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", | |
9303 | port, bd, rcq); | |
9304 | } | |
9305 | ||
9306 | static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp) | |
9307 | { | |
9308 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
9309 | if (!rc) { | |
9310 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9311 | return -EBUSY; | |
9312 | } | |
9313 | ||
9314 | return 0; | |
9315 | } | |
9316 | ||
9317 | static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp) | |
9318 | { | |
9319 | struct bnx2x_prev_path_list *tmp_list; | |
9320 | int rc = false; | |
9321 | ||
9322 | if (down_trylock(&bnx2x_prev_sem)) | |
9323 | return false; | |
9324 | ||
9325 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) { | |
9326 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
9327 | bp->pdev->bus->number == tmp_list->bus && | |
9328 | BP_PATH(bp) == tmp_list->path) { | |
9329 | rc = true; | |
9330 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | |
9331 | BP_PATH(bp)); | |
9332 | break; | |
9333 | } | |
9334 | } | |
9335 | ||
9336 | up(&bnx2x_prev_sem); | |
9337 | ||
9338 | return rc; | |
9339 | } | |
9340 | ||
9341 | static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp) | |
9342 | { | |
9343 | struct bnx2x_prev_path_list *tmp_list; | |
9344 | int rc; | |
9345 | ||
9346 | tmp_list = (struct bnx2x_prev_path_list *) | |
9347 | kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); | |
9348 | if (!tmp_list) { | |
9349 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | |
9350 | return -ENOMEM; | |
9351 | } | |
9352 | ||
9353 | tmp_list->bus = bp->pdev->bus->number; | |
9354 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | |
9355 | tmp_list->path = BP_PATH(bp); | |
9356 | ||
9357 | rc = down_interruptible(&bnx2x_prev_sem); | |
9358 | if (rc) { | |
9359 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
9360 | kfree(tmp_list); | |
9361 | } else { | |
9362 | BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n", | |
9363 | BP_PATH(bp)); | |
9364 | list_add(&tmp_list->list, &bnx2x_prev_list); | |
9365 | up(&bnx2x_prev_sem); | |
9366 | } | |
9367 | ||
9368 | return rc; | |
9369 | } | |
9370 | ||
9371 | static bool __devinit bnx2x_can_flr(struct bnx2x *bp) | |
9372 | { | |
9373 | int pos; | |
9374 | u32 cap; | |
9375 | struct pci_dev *dev = bp->pdev; | |
9376 | ||
9377 | pos = pci_pcie_cap(dev); | |
9378 | if (!pos) | |
9379 | return false; | |
9380 | ||
9381 | pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); | |
9382 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
9383 | return false; | |
9384 | ||
9385 | return true; | |
9386 | } | |
9387 | ||
9388 | static int __devinit bnx2x_do_flr(struct bnx2x *bp) | |
9389 | { | |
9390 | int i, pos; | |
9391 | u16 status; | |
9392 | struct pci_dev *dev = bp->pdev; | |
9393 | ||
9394 | /* probe the capability first */ | |
9395 | if (bnx2x_can_flr(bp)) | |
9396 | return -ENOTTY; | |
9397 | ||
9398 | pos = pci_pcie_cap(dev); | |
9399 | if (!pos) | |
9400 | return -ENOTTY; | |
9401 | ||
9402 | /* Wait for Transaction Pending bit clean */ | |
9403 | for (i = 0; i < 4; i++) { | |
9404 | if (i) | |
9405 | msleep((1 << (i - 1)) * 100); | |
9406 | ||
9407 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); | |
9408 | if (!(status & PCI_EXP_DEVSTA_TRPND)) | |
9409 | goto clear; | |
9410 | } | |
9411 | ||
9412 | dev_err(&dev->dev, | |
9413 | "transaction is not cleared; proceeding with reset anyway\n"); | |
9414 | ||
9415 | clear: | |
9416 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | |
9417 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | |
9418 | bp->common.bc_ver); | |
9419 | return -EINVAL; | |
9420 | } | |
9421 | ||
9422 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); | |
9423 | ||
9424 | return 0; | |
9425 | } | |
9426 | ||
9427 | static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp) | |
9428 | { | |
9429 | int rc; | |
9430 | ||
9431 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); | |
9432 | ||
9433 | /* Test if previous unload process was already finished for this path */ | |
9434 | if (bnx2x_prev_is_path_marked(bp)) | |
9435 | return bnx2x_prev_mcp_done(bp); | |
9436 | ||
9437 | /* If function has FLR capabilities, and existing FW version matches | |
9438 | * the one required, then FLR will be sufficient to clean any residue | |
9439 | * left by previous driver | |
9440 | */ | |
9441 | if (bnx2x_test_firmware_version(bp, false) && bnx2x_can_flr(bp)) | |
9442 | return bnx2x_do_flr(bp); | |
9443 | ||
9444 | /* Close the MCP request, return failure*/ | |
9445 | rc = bnx2x_prev_mcp_done(bp); | |
9446 | if (!rc) | |
9447 | rc = BNX2X_PREV_WAIT_NEEDED; | |
9448 | ||
9449 | return rc; | |
9450 | } | |
9451 | ||
9452 | static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp) | |
9453 | { | |
9454 | u32 reset_reg, tmp_reg = 0, rc; | |
9455 | /* It is possible a previous function received 'common' answer, | |
9456 | * but hasn't loaded yet, therefore creating a scenario of | |
9457 | * multiple functions receiving 'common' on the same path. | |
9458 | */ | |
9459 | BNX2X_DEV_INFO("Common unload Flow\n"); | |
9460 | ||
9461 | if (bnx2x_prev_is_path_marked(bp)) | |
9462 | return bnx2x_prev_mcp_done(bp); | |
9463 | ||
9464 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); | |
9465 | ||
9466 | /* Reset should be performed after BRB is emptied */ | |
9467 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { | |
9468 | u32 timer_count = 1000; | |
9469 | bool prev_undi = false; | |
9470 | ||
9471 | /* Close the MAC Rx to prevent BRB from filling up */ | |
9472 | bnx2x_prev_unload_close_mac(bp); | |
9473 | ||
9474 | /* Check if the UNDI driver was previously loaded | |
34f80b04 EG |
9475 | * UNDI driver initializes CID offset for normal bell to 0x7 |
9476 | */ | |
452427b0 YM |
9477 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); |
9478 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { | |
9479 | tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST); | |
9480 | if (tmp_reg == 0x7) { | |
9481 | BNX2X_DEV_INFO("UNDI previously loaded\n"); | |
9482 | prev_undi = true; | |
9483 | /* clear the UNDI indication */ | |
9484 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
34f80b04 | 9485 | } |
452427b0 YM |
9486 | } |
9487 | /* wait until BRB is empty */ | |
9488 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); | |
9489 | while (timer_count) { | |
9490 | u32 prev_brb = tmp_reg; | |
34f80b04 | 9491 | |
452427b0 YM |
9492 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
9493 | if (!tmp_reg) | |
9494 | break; | |
619c5cb6 | 9495 | |
452427b0 | 9496 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
619c5cb6 | 9497 | |
452427b0 YM |
9498 | /* reset timer as long as BRB actually gets emptied */ |
9499 | if (prev_brb > tmp_reg) | |
9500 | timer_count = 1000; | |
9501 | else | |
9502 | timer_count--; | |
da5a662a | 9503 | |
452427b0 YM |
9504 | /* If UNDI resides in memory, manually increment it */ |
9505 | if (prev_undi) | |
9506 | bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1); | |
da5a662a | 9507 | |
452427b0 | 9508 | udelay(10); |
7a06a122 | 9509 | } |
452427b0 YM |
9510 | |
9511 | if (!timer_count) | |
9512 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); | |
9513 | ||
34f80b04 | 9514 | } |
f16da43b | 9515 | |
452427b0 YM |
9516 | /* No packets are in the pipeline, path is ready for reset */ |
9517 | bnx2x_reset_common(bp); | |
9518 | ||
9519 | rc = bnx2x_prev_mark_path(bp); | |
9520 | if (rc) { | |
9521 | bnx2x_prev_mcp_done(bp); | |
9522 | return rc; | |
9523 | } | |
9524 | ||
9525 | return bnx2x_prev_mcp_done(bp); | |
9526 | } | |
9527 | ||
24f06716 AE |
9528 | /* previous driver DMAE transaction may have occurred when pre-boot stage ended |
9529 | * and boot began, or when kdump kernel was loaded. Either case would invalidate | |
9530 | * the addresses of the transaction, resulting in was-error bit set in the pci | |
9531 | * causing all hw-to-host pcie transactions to timeout. If this happened we want | |
9532 | * to clear the interrupt which detected this from the pglueb and the was done | |
9533 | * bit | |
9534 | */ | |
9535 | static void __devinit bnx2x_prev_interrupted_dmae(struct bnx2x *bp) | |
9536 | { | |
9537 | u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS); | |
9538 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) { | |
9539 | BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing"); | |
9540 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << BP_FUNC(bp)); | |
9541 | } | |
9542 | } | |
9543 | ||
452427b0 YM |
9544 | static int __devinit bnx2x_prev_unload(struct bnx2x *bp) |
9545 | { | |
9546 | int time_counter = 10; | |
9547 | u32 rc, fw, hw_lock_reg, hw_lock_val; | |
9548 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); | |
9549 | ||
24f06716 AE |
9550 | /* clear hw from errors which may have resulted from an interrupted |
9551 | * dmae transaction. | |
9552 | */ | |
9553 | bnx2x_prev_interrupted_dmae(bp); | |
9554 | ||
9555 | /* Release previously held locks */ | |
452427b0 YM |
9556 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? |
9557 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : | |
9558 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); | |
9559 | ||
9560 | hw_lock_val = (REG_RD(bp, hw_lock_reg)); | |
9561 | if (hw_lock_val) { | |
9562 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { | |
9563 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); | |
9564 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
9565 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); | |
9566 | } | |
9567 | ||
9568 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); | |
9569 | REG_WR(bp, hw_lock_reg, 0xffffffff); | |
9570 | } else | |
9571 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); | |
9572 | ||
9573 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { | |
9574 | BNX2X_DEV_INFO("Release previously held alr\n"); | |
9575 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); | |
9576 | } | |
9577 | ||
9578 | ||
9579 | do { | |
9580 | /* Lock MCP using an unload request */ | |
9581 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | |
9582 | if (!fw) { | |
9583 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9584 | rc = -EBUSY; | |
9585 | break; | |
9586 | } | |
9587 | ||
9588 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) { | |
9589 | rc = bnx2x_prev_unload_common(bp); | |
9590 | break; | |
9591 | } | |
9592 | ||
9593 | /* non-common reply from MCP night require looping */ | |
9594 | rc = bnx2x_prev_unload_uncommon(bp); | |
9595 | if (rc != BNX2X_PREV_WAIT_NEEDED) | |
9596 | break; | |
9597 | ||
9598 | msleep(20); | |
9599 | } while (--time_counter); | |
9600 | ||
9601 | if (!time_counter || rc) { | |
9602 | BNX2X_ERR("Failed unloading previous driver, aborting\n"); | |
9603 | rc = -EBUSY; | |
9604 | } | |
9605 | ||
9606 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); | |
9607 | ||
9608 | return rc; | |
34f80b04 EG |
9609 | } |
9610 | ||
9611 | static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) | |
9612 | { | |
1d187b34 | 9613 | u32 val, val2, val3, val4, id, boot_mode; |
72ce58c3 | 9614 | u16 pmc; |
34f80b04 EG |
9615 | |
9616 | /* Get the chip revision id and number. */ | |
9617 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
9618 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
9619 | id = ((val & 0xffff) << 16); | |
9620 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
9621 | id |= ((val & 0xf) << 12); | |
9622 | val = REG_RD(bp, MISC_REG_CHIP_METAL); | |
9623 | id |= ((val & 0xff) << 4); | |
5a40e08e | 9624 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
9625 | id |= (val & 0xf); |
9626 | bp->common.chip_id = id; | |
523224a3 | 9627 | |
7e8e02df BW |
9628 | /* force 57811 according to MISC register */ |
9629 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { | |
9630 | if (CHIP_IS_57810(bp)) | |
9631 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | | |
9632 | (bp->common.chip_id & 0x0000FFFF); | |
9633 | else if (CHIP_IS_57810_MF(bp)) | |
9634 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | | |
9635 | (bp->common.chip_id & 0x0000FFFF); | |
9636 | bp->common.chip_id |= 0x1; | |
9637 | } | |
9638 | ||
523224a3 DK |
9639 | /* Set doorbell size */ |
9640 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
9641 | ||
619c5cb6 | 9642 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
9643 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
9644 | if ((val & 1) == 0) | |
9645 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
9646 | else | |
9647 | val = (val >> 1) & 1; | |
9648 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
9649 | "2_PORT_MODE"); | |
9650 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
9651 | CHIP_2_PORT_MODE; | |
9652 | ||
9653 | if (CHIP_MODE_IS_4_PORT(bp)) | |
9654 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
9655 | else | |
9656 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
9657 | } else { | |
9658 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
9659 | bp->pfid = bp->pf_num; /* 0..7 */ | |
9660 | } | |
9661 | ||
51c1a580 MS |
9662 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
9663 | ||
f2e0899f DK |
9664 | bp->link_params.chip_id = bp->common.chip_id; |
9665 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 9666 | |
1c06328c EG |
9667 | val = (REG_RD(bp, 0x2874) & 0x55); |
9668 | if ((bp->common.chip_id & 0x1) || | |
9669 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
9670 | bp->flags |= ONE_PORT_FLAG; | |
9671 | BNX2X_DEV_INFO("single port device\n"); | |
9672 | } | |
9673 | ||
34f80b04 | 9674 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 9675 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
9676 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
9677 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
9678 | bp->common.flash_size, bp->common.flash_size); | |
9679 | ||
1b6e2ceb DK |
9680 | bnx2x_init_shmem(bp); |
9681 | ||
619c5cb6 VZ |
9682 | |
9683 | ||
f2e0899f DK |
9684 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
9685 | MISC_REG_GENERIC_CR_1 : | |
9686 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 9687 | |
34f80b04 | 9688 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 9689 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
2691d51d EG |
9690 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
9691 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 9692 | |
f2e0899f | 9693 | if (!bp->common.shmem_base) { |
34f80b04 EG |
9694 | BNX2X_DEV_INFO("MCP not active\n"); |
9695 | bp->flags |= NO_MCP_FLAG; | |
9696 | return; | |
9697 | } | |
9698 | ||
34f80b04 | 9699 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 9700 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
9701 | |
9702 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
9703 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
9704 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
9705 | ||
c2c8b03e EG |
9706 | bp->link_params.feature_config_flags = 0; |
9707 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
9708 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
9709 | bp->link_params.feature_config_flags |= | |
9710 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
9711 | else | |
9712 | bp->link_params.feature_config_flags &= | |
9713 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
9714 | ||
34f80b04 EG |
9715 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
9716 | bp->common.bc_ver = val; | |
9717 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
9718 | if (val < BNX2X_BC_VER) { | |
9719 | /* for now only warn | |
9720 | * later we might need to enforce this */ | |
51c1a580 MS |
9721 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
9722 | BNX2X_BC_VER, val); | |
34f80b04 | 9723 | } |
4d295db0 | 9724 | bp->link_params.feature_config_flags |= |
a22f0788 | 9725 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
9726 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
9727 | ||
a22f0788 YR |
9728 | bp->link_params.feature_config_flags |= |
9729 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
9730 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
a3348722 BW |
9731 | bp->link_params.feature_config_flags |= |
9732 | (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? | |
9733 | FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; | |
85242eea YR |
9734 | bp->link_params.feature_config_flags |= |
9735 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
9736 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
0e898dd7 BW |
9737 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
9738 | BC_SUPPORTS_PFC_STATS : 0; | |
85242eea | 9739 | |
1d187b34 BW |
9740 | boot_mode = SHMEM_RD(bp, |
9741 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & | |
9742 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; | |
9743 | switch (boot_mode) { | |
9744 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: | |
9745 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; | |
9746 | break; | |
9747 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: | |
9748 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; | |
9749 | break; | |
9750 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: | |
9751 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; | |
9752 | break; | |
9753 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: | |
9754 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; | |
9755 | break; | |
9756 | } | |
9757 | ||
f9a3ebbe DK |
9758 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); |
9759 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; | |
9760 | ||
72ce58c3 | 9761 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 9762 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
9763 | |
9764 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
9765 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
9766 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
9767 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
9768 | ||
cdaa7cb8 VZ |
9769 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
9770 | val, val2, val3, val4); | |
34f80b04 EG |
9771 | } |
9772 | ||
f2e0899f DK |
9773 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
9774 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
9775 | ||
9776 | static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) | |
9777 | { | |
9778 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
9779 | int igu_sb_id; |
9780 | u32 val; | |
6383c0b3 | 9781 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
9782 | |
9783 | bp->igu_base_sb = 0xff; | |
f2e0899f | 9784 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 9785 | int vn = BP_VN(bp); |
6383c0b3 | 9786 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
9787 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
9788 | FP_SB_MAX_E1x; | |
9789 | ||
9790 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
9791 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
9792 | ||
9793 | return; | |
9794 | } | |
9795 | ||
9796 | /* IGU in normal mode - read CAM */ | |
9797 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
9798 | igu_sb_id++) { | |
9799 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
9800 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
9801 | continue; | |
9802 | fid = IGU_FID(val); | |
9803 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
9804 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
9805 | continue; | |
9806 | if (IGU_VEC(val) == 0) | |
9807 | /* default status block */ | |
9808 | bp->igu_dsb_id = igu_sb_id; | |
9809 | else { | |
9810 | if (bp->igu_base_sb == 0xff) | |
9811 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 9812 | igu_sb_cnt++; |
f2e0899f DK |
9813 | } |
9814 | } | |
9815 | } | |
619c5cb6 | 9816 | |
6383c0b3 AE |
9817 | #ifdef CONFIG_PCI_MSI |
9818 | /* | |
9819 | * It's expected that number of CAM entries for this functions is equal | |
9820 | * to the number evaluated based on the MSI-X table size. We want a | |
9821 | * harsh warning if these values are different! | |
619c5cb6 | 9822 | */ |
6383c0b3 AE |
9823 | WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); |
9824 | #endif | |
619c5cb6 | 9825 | |
6383c0b3 | 9826 | if (igu_sb_cnt == 0) |
f2e0899f DK |
9827 | BNX2X_ERR("CAM configuration error\n"); |
9828 | } | |
9829 | ||
34f80b04 EG |
9830 | static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, |
9831 | u32 switch_cfg) | |
a2fbb9ea | 9832 | { |
a22f0788 YR |
9833 | int cfg_size = 0, idx, port = BP_PORT(bp); |
9834 | ||
9835 | /* Aggregation of supported attributes of all external phys */ | |
9836 | bp->port.supported[0] = 0; | |
9837 | bp->port.supported[1] = 0; | |
b7737c9b YR |
9838 | switch (bp->link_params.num_phys) { |
9839 | case 1: | |
a22f0788 YR |
9840 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
9841 | cfg_size = 1; | |
9842 | break; | |
b7737c9b | 9843 | case 2: |
a22f0788 YR |
9844 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
9845 | cfg_size = 1; | |
9846 | break; | |
9847 | case 3: | |
9848 | if (bp->link_params.multi_phy_config & | |
9849 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
9850 | bp->port.supported[1] = | |
9851 | bp->link_params.phy[EXT_PHY1].supported; | |
9852 | bp->port.supported[0] = | |
9853 | bp->link_params.phy[EXT_PHY2].supported; | |
9854 | } else { | |
9855 | bp->port.supported[0] = | |
9856 | bp->link_params.phy[EXT_PHY1].supported; | |
9857 | bp->port.supported[1] = | |
9858 | bp->link_params.phy[EXT_PHY2].supported; | |
9859 | } | |
9860 | cfg_size = 2; | |
9861 | break; | |
b7737c9b | 9862 | } |
a2fbb9ea | 9863 | |
a22f0788 | 9864 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
51c1a580 | 9865 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 9866 | SHMEM_RD(bp, |
a22f0788 YR |
9867 | dev_info.port_hw_config[port].external_phy_config), |
9868 | SHMEM_RD(bp, | |
9869 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 9870 | return; |
f85582f8 | 9871 | } |
a2fbb9ea | 9872 | |
619c5cb6 VZ |
9873 | if (CHIP_IS_E3(bp)) |
9874 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
9875 | else { | |
9876 | switch (switch_cfg) { | |
9877 | case SWITCH_CFG_1G: | |
9878 | bp->port.phy_addr = REG_RD( | |
9879 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
9880 | break; | |
9881 | case SWITCH_CFG_10G: | |
9882 | bp->port.phy_addr = REG_RD( | |
9883 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
9884 | break; | |
9885 | default: | |
9886 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
9887 | bp->port.link_config[0]); | |
9888 | return; | |
9889 | } | |
a2fbb9ea | 9890 | } |
619c5cb6 | 9891 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
9892 | /* mask what we support according to speed_cap_mask per configuration */ |
9893 | for (idx = 0; idx < cfg_size; idx++) { | |
9894 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 9895 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 9896 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 9897 | |
a22f0788 | 9898 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9899 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 9900 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 9901 | |
a22f0788 | 9902 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9903 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 9904 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 9905 | |
a22f0788 | 9906 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9907 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 9908 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 9909 | |
a22f0788 | 9910 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9911 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 9912 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 9913 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 9914 | |
a22f0788 | 9915 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9916 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 9917 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 9918 | |
a22f0788 | 9919 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 9920 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 YR |
9921 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
9922 | ||
9923 | } | |
a2fbb9ea | 9924 | |
a22f0788 YR |
9925 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
9926 | bp->port.supported[1]); | |
a2fbb9ea ET |
9927 | } |
9928 | ||
34f80b04 | 9929 | static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 9930 | { |
a22f0788 YR |
9931 | u32 link_config, idx, cfg_size = 0; |
9932 | bp->port.advertising[0] = 0; | |
9933 | bp->port.advertising[1] = 0; | |
9934 | switch (bp->link_params.num_phys) { | |
9935 | case 1: | |
9936 | case 2: | |
9937 | cfg_size = 1; | |
9938 | break; | |
9939 | case 3: | |
9940 | cfg_size = 2; | |
9941 | break; | |
9942 | } | |
9943 | for (idx = 0; idx < cfg_size; idx++) { | |
9944 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
9945 | link_config = bp->port.link_config[idx]; | |
9946 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 9947 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
9948 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
9949 | bp->link_params.req_line_speed[idx] = | |
9950 | SPEED_AUTO_NEG; | |
9951 | bp->port.advertising[idx] |= | |
9952 | bp->port.supported[idx]; | |
10bd1f24 MY |
9953 | if (bp->link_params.phy[EXT_PHY1].type == |
9954 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
9955 | bp->port.advertising[idx] |= | |
9956 | (SUPPORTED_100baseT_Half | | |
9957 | SUPPORTED_100baseT_Full); | |
f85582f8 DK |
9958 | } else { |
9959 | /* force 10G, no AN */ | |
a22f0788 YR |
9960 | bp->link_params.req_line_speed[idx] = |
9961 | SPEED_10000; | |
9962 | bp->port.advertising[idx] |= | |
9963 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 9964 | ADVERTISED_FIBRE); |
a22f0788 | 9965 | continue; |
f85582f8 DK |
9966 | } |
9967 | break; | |
a2fbb9ea | 9968 | |
f85582f8 | 9969 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
9970 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
9971 | bp->link_params.req_line_speed[idx] = | |
9972 | SPEED_10; | |
9973 | bp->port.advertising[idx] |= | |
9974 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
9975 | ADVERTISED_TP); |
9976 | } else { | |
51c1a580 | 9977 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 | 9978 | link_config, |
a22f0788 | 9979 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
9980 | return; |
9981 | } | |
9982 | break; | |
a2fbb9ea | 9983 | |
f85582f8 | 9984 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
9985 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
9986 | bp->link_params.req_line_speed[idx] = | |
9987 | SPEED_10; | |
9988 | bp->link_params.req_duplex[idx] = | |
9989 | DUPLEX_HALF; | |
9990 | bp->port.advertising[idx] |= | |
9991 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
9992 | ADVERTISED_TP); |
9993 | } else { | |
51c1a580 | 9994 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
9995 | link_config, |
9996 | bp->link_params.speed_cap_mask[idx]); | |
9997 | return; | |
9998 | } | |
9999 | break; | |
a2fbb9ea | 10000 | |
f85582f8 DK |
10001 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
10002 | if (bp->port.supported[idx] & | |
10003 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
10004 | bp->link_params.req_line_speed[idx] = |
10005 | SPEED_100; | |
10006 | bp->port.advertising[idx] |= | |
10007 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
10008 | ADVERTISED_TP); |
10009 | } else { | |
51c1a580 | 10010 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
10011 | link_config, |
10012 | bp->link_params.speed_cap_mask[idx]); | |
10013 | return; | |
10014 | } | |
10015 | break; | |
a2fbb9ea | 10016 | |
f85582f8 DK |
10017 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
10018 | if (bp->port.supported[idx] & | |
10019 | SUPPORTED_100baseT_Half) { | |
10020 | bp->link_params.req_line_speed[idx] = | |
10021 | SPEED_100; | |
10022 | bp->link_params.req_duplex[idx] = | |
10023 | DUPLEX_HALF; | |
a22f0788 YR |
10024 | bp->port.advertising[idx] |= |
10025 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
10026 | ADVERTISED_TP); |
10027 | } else { | |
51c1a580 | 10028 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
10029 | link_config, |
10030 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
10031 | return; |
10032 | } | |
10033 | break; | |
a2fbb9ea | 10034 | |
f85582f8 | 10035 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
10036 | if (bp->port.supported[idx] & |
10037 | SUPPORTED_1000baseT_Full) { | |
10038 | bp->link_params.req_line_speed[idx] = | |
10039 | SPEED_1000; | |
10040 | bp->port.advertising[idx] |= | |
10041 | (ADVERTISED_1000baseT_Full | | |
f85582f8 DK |
10042 | ADVERTISED_TP); |
10043 | } else { | |
51c1a580 | 10044 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
10045 | link_config, |
10046 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
10047 | return; |
10048 | } | |
10049 | break; | |
a2fbb9ea | 10050 | |
f85582f8 | 10051 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
10052 | if (bp->port.supported[idx] & |
10053 | SUPPORTED_2500baseX_Full) { | |
10054 | bp->link_params.req_line_speed[idx] = | |
10055 | SPEED_2500; | |
10056 | bp->port.advertising[idx] |= | |
10057 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 10058 | ADVERTISED_TP); |
f85582f8 | 10059 | } else { |
51c1a580 | 10060 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 10061 | link_config, |
f85582f8 DK |
10062 | bp->link_params.speed_cap_mask[idx]); |
10063 | return; | |
10064 | } | |
10065 | break; | |
a2fbb9ea | 10066 | |
f85582f8 | 10067 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
10068 | if (bp->port.supported[idx] & |
10069 | SUPPORTED_10000baseT_Full) { | |
10070 | bp->link_params.req_line_speed[idx] = | |
10071 | SPEED_10000; | |
10072 | bp->port.advertising[idx] |= | |
10073 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 10074 | ADVERTISED_FIBRE); |
f85582f8 | 10075 | } else { |
51c1a580 | 10076 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 10077 | link_config, |
f85582f8 DK |
10078 | bp->link_params.speed_cap_mask[idx]); |
10079 | return; | |
10080 | } | |
10081 | break; | |
3c9ada22 YR |
10082 | case PORT_FEATURE_LINK_SPEED_20G: |
10083 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 10084 | |
3c9ada22 | 10085 | break; |
f85582f8 | 10086 | default: |
51c1a580 | 10087 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
754a2f52 | 10088 | link_config); |
f85582f8 DK |
10089 | bp->link_params.req_line_speed[idx] = |
10090 | SPEED_AUTO_NEG; | |
10091 | bp->port.advertising[idx] = | |
10092 | bp->port.supported[idx]; | |
10093 | break; | |
10094 | } | |
a2fbb9ea | 10095 | |
a22f0788 | 10096 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 10097 | PORT_FEATURE_FLOW_CONTROL_MASK); |
a22f0788 YR |
10098 | if ((bp->link_params.req_flow_ctrl[idx] == |
10099 | BNX2X_FLOW_CTRL_AUTO) && | |
10100 | !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { | |
10101 | bp->link_params.req_flow_ctrl[idx] = | |
10102 | BNX2X_FLOW_CTRL_NONE; | |
10103 | } | |
a2fbb9ea | 10104 | |
51c1a580 | 10105 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
a22f0788 YR |
10106 | bp->link_params.req_line_speed[idx], |
10107 | bp->link_params.req_duplex[idx], | |
10108 | bp->link_params.req_flow_ctrl[idx], | |
10109 | bp->port.advertising[idx]); | |
10110 | } | |
a2fbb9ea ET |
10111 | } |
10112 | ||
e665bfda MC |
10113 | static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
10114 | { | |
10115 | mac_hi = cpu_to_be16(mac_hi); | |
10116 | mac_lo = cpu_to_be32(mac_lo); | |
10117 | memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); | |
10118 | memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); | |
10119 | } | |
10120 | ||
34f80b04 | 10121 | static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 10122 | { |
34f80b04 | 10123 | int port = BP_PORT(bp); |
589abe3a | 10124 | u32 config; |
c8c60d88 | 10125 | u32 ext_phy_type, ext_phy_config, eee_mode; |
a2fbb9ea | 10126 | |
c18487ee | 10127 | bp->link_params.bp = bp; |
34f80b04 | 10128 | bp->link_params.port = port; |
c18487ee | 10129 | |
c18487ee | 10130 | bp->link_params.lane_config = |
a2fbb9ea | 10131 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 10132 | |
a22f0788 | 10133 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea ET |
10134 | SHMEM_RD(bp, |
10135 | dev_info.port_hw_config[port].speed_capability_mask); | |
a22f0788 YR |
10136 | bp->link_params.speed_cap_mask[1] = |
10137 | SHMEM_RD(bp, | |
10138 | dev_info.port_hw_config[port].speed_capability_mask2); | |
10139 | bp->port.link_config[0] = | |
a2fbb9ea ET |
10140 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
10141 | ||
a22f0788 YR |
10142 | bp->port.link_config[1] = |
10143 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 10144 | |
a22f0788 YR |
10145 | bp->link_params.multi_phy_config = |
10146 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
10147 | /* If the device is capable of WoL, set the default state according |
10148 | * to the HW | |
10149 | */ | |
4d295db0 | 10150 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
10151 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
10152 | (config & PORT_FEATURE_WOL_ENABLED)); | |
10153 | ||
51c1a580 | 10154 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 10155 | bp->link_params.lane_config, |
a22f0788 YR |
10156 | bp->link_params.speed_cap_mask[0], |
10157 | bp->port.link_config[0]); | |
a2fbb9ea | 10158 | |
a22f0788 | 10159 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 10160 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 10161 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 10162 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
10163 | |
10164 | bnx2x_link_settings_requested(bp); | |
10165 | ||
01cd4528 EG |
10166 | /* |
10167 | * If connected directly, work with the internal PHY, otherwise, work | |
10168 | * with the external PHY | |
10169 | */ | |
b7737c9b YR |
10170 | ext_phy_config = |
10171 | SHMEM_RD(bp, | |
10172 | dev_info.port_hw_config[port].external_phy_config); | |
10173 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 10174 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 10175 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
10176 | |
10177 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
10178 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
10179 | bp->mdio.prtad = | |
b7737c9b | 10180 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d YR |
10181 | |
10182 | /* | |
10183 | * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) | |
10184 | * In MF mode, it is set to cover self test cases | |
10185 | */ | |
10186 | if (IS_MF(bp)) | |
10187 | bp->port.need_hw_lock = 1; | |
10188 | else | |
10189 | bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, | |
10190 | bp->common.shmem_base, | |
10191 | bp->common.shmem2_base); | |
c8c60d88 YM |
10192 | |
10193 | /* Configure link feature according to nvram value */ | |
10194 | eee_mode = (((SHMEM_RD(bp, dev_info. | |
10195 | port_feature_config[port].eee_power_mode)) & | |
10196 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
10197 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
10198 | if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { | |
10199 | bp->link_params.eee_mode = EEE_MODE_ADV_LPI | | |
10200 | EEE_MODE_ENABLE_LPI | | |
10201 | EEE_MODE_OUTPUT_TIME; | |
10202 | } else { | |
10203 | bp->link_params.eee_mode = 0; | |
10204 | } | |
0793f83f | 10205 | } |
01cd4528 | 10206 | |
b306f5ed | 10207 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 10208 | { |
9e62e912 | 10209 | u32 no_flags = NO_ISCSI_FLAG; |
7185bb33 | 10210 | #ifdef BCM_CNIC |
bf61ee14 | 10211 | int port = BP_PORT(bp); |
bf61ee14 | 10212 | |
2ba45142 | 10213 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 10214 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 10215 | |
b306f5ed | 10216 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
10217 | bp->cnic_eth_dev.max_iscsi_conn = |
10218 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
10219 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
10220 | ||
b306f5ed DK |
10221 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
10222 | bp->cnic_eth_dev.max_iscsi_conn); | |
10223 | ||
10224 | /* | |
10225 | * If maximum allowed number of connections is zero - | |
10226 | * disable the feature. | |
10227 | */ | |
10228 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9e62e912 | 10229 | bp->flags |= no_flags; |
7185bb33 | 10230 | #else |
9e62e912 | 10231 | bp->flags |= no_flags; |
7185bb33 | 10232 | #endif |
b306f5ed DK |
10233 | } |
10234 | ||
9e62e912 DK |
10235 | #ifdef BCM_CNIC |
10236 | static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) | |
10237 | { | |
10238 | /* Port info */ | |
10239 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10240 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); | |
10241 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10242 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); | |
10243 | ||
10244 | /* Node info */ | |
10245 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10246 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); | |
10247 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10248 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); | |
10249 | } | |
10250 | #endif | |
b306f5ed DK |
10251 | static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) |
10252 | { | |
7185bb33 | 10253 | #ifdef BCM_CNIC |
b306f5ed DK |
10254 | int port = BP_PORT(bp); |
10255 | int func = BP_ABS_FUNC(bp); | |
10256 | ||
10257 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, | |
10258 | drv_lic_key[port].max_fcoe_conn); | |
10259 | ||
10260 | /* Get the number of maximum allowed FCoE connections */ | |
2ba45142 VZ |
10261 | bp->cnic_eth_dev.max_fcoe_conn = |
10262 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
10263 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
10264 | ||
bf61ee14 VZ |
10265 | /* Read the WWN: */ |
10266 | if (!IS_MF(bp)) { | |
10267 | /* Port info */ | |
10268 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10269 | SHMEM_RD(bp, | |
10270 | dev_info.port_hw_config[port]. | |
10271 | fcoe_wwn_port_name_upper); | |
10272 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10273 | SHMEM_RD(bp, | |
10274 | dev_info.port_hw_config[port]. | |
10275 | fcoe_wwn_port_name_lower); | |
10276 | ||
10277 | /* Node info */ | |
10278 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10279 | SHMEM_RD(bp, | |
10280 | dev_info.port_hw_config[port]. | |
10281 | fcoe_wwn_node_name_upper); | |
10282 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10283 | SHMEM_RD(bp, | |
10284 | dev_info.port_hw_config[port]. | |
10285 | fcoe_wwn_node_name_lower); | |
10286 | } else if (!IS_MF_SD(bp)) { | |
10287 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); | |
10288 | ||
10289 | /* | |
10290 | * Read the WWN info only if the FCoE feature is enabled for | |
10291 | * this function. | |
10292 | */ | |
9e62e912 DK |
10293 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) |
10294 | bnx2x_get_ext_wwn_info(bp, func); | |
10295 | ||
10296 | } else if (IS_MF_FCOE_SD(bp)) | |
10297 | bnx2x_get_ext_wwn_info(bp, func); | |
bf61ee14 | 10298 | |
b306f5ed | 10299 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 10300 | |
bf61ee14 VZ |
10301 | /* |
10302 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
10303 | * disable the feature. |
10304 | */ | |
2ba45142 VZ |
10305 | if (!bp->cnic_eth_dev.max_fcoe_conn) |
10306 | bp->flags |= NO_FCOE_FLAG; | |
7185bb33 DK |
10307 | #else |
10308 | bp->flags |= NO_FCOE_FLAG; | |
10309 | #endif | |
2ba45142 | 10310 | } |
b306f5ed DK |
10311 | |
10312 | static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) | |
10313 | { | |
10314 | /* | |
10315 | * iSCSI may be dynamically disabled but reading | |
10316 | * info here we will decrease memory usage by driver | |
10317 | * if the feature is disabled for good | |
10318 | */ | |
10319 | bnx2x_get_iscsi_info(bp); | |
10320 | bnx2x_get_fcoe_info(bp); | |
10321 | } | |
2ba45142 | 10322 | |
0793f83f DK |
10323 | static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
10324 | { | |
10325 | u32 val, val2; | |
10326 | int func = BP_ABS_FUNC(bp); | |
10327 | int port = BP_PORT(bp); | |
2ba45142 VZ |
10328 | #ifdef BCM_CNIC |
10329 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; | |
10330 | u8 *fip_mac = bp->fip_mac; | |
10331 | #endif | |
0793f83f | 10332 | |
619c5cb6 VZ |
10333 | /* Zero primary MAC configuration */ |
10334 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
10335 | ||
0793f83f DK |
10336 | if (BP_NOMCP(bp)) { |
10337 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
7ce5d222 | 10338 | eth_hw_addr_random(bp->dev); |
0793f83f DK |
10339 | } else if (IS_MF(bp)) { |
10340 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
10341 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
10342 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
10343 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
10344 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
37b091ba MC |
10345 | |
10346 | #ifdef BCM_CNIC | |
614c76df DK |
10347 | /* |
10348 | * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or | |
2ba45142 | 10349 | * FCoE MAC then the appropriate feature should be disabled. |
9e62e912 DK |
10350 | * |
10351 | * In non SD mode features configuration comes from | |
10352 | * struct func_ext_config. | |
2ba45142 | 10353 | */ |
9e62e912 | 10354 | if (!IS_MF_SD(bp)) { |
0793f83f DK |
10355 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
10356 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
10357 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
10358 | iscsi_mac_addr_upper); | |
10359 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
10360 | iscsi_mac_addr_lower); | |
2ba45142 | 10361 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
0f9dad10 JP |
10362 | BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", |
10363 | iscsi_mac); | |
2ba45142 VZ |
10364 | } else |
10365 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; | |
10366 | ||
10367 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
10368 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
10369 | fcoe_mac_addr_upper); | |
10370 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
10371 | fcoe_mac_addr_lower); | |
2ba45142 | 10372 | bnx2x_set_mac_buf(fip_mac, val, val2); |
614c76df | 10373 | BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", |
0f9dad10 | 10374 | fip_mac); |
2ba45142 | 10375 | |
2ba45142 VZ |
10376 | } else |
10377 | bp->flags |= NO_FCOE_FLAG; | |
a3348722 BW |
10378 | |
10379 | bp->mf_ext_config = cfg; | |
10380 | ||
9e62e912 DK |
10381 | } else { /* SD MODE */ |
10382 | if (IS_MF_STORAGE_SD(bp)) { | |
10383 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { | |
10384 | /* use primary mac as iscsi mac */ | |
10385 | memcpy(iscsi_mac, bp->dev->dev_addr, | |
10386 | ETH_ALEN); | |
10387 | ||
10388 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); | |
10389 | BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", | |
10390 | iscsi_mac); | |
10391 | } else { /* FCoE */ | |
10392 | memcpy(fip_mac, bp->dev->dev_addr, | |
10393 | ETH_ALEN); | |
10394 | BNX2X_DEV_INFO("SD FCoE MODE\n"); | |
10395 | BNX2X_DEV_INFO("Read FIP MAC: %pM\n", | |
10396 | fip_mac); | |
10397 | } | |
614c76df DK |
10398 | /* Zero primary MAC configuration */ |
10399 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
614c76df | 10400 | } |
0793f83f | 10401 | } |
a3348722 BW |
10402 | |
10403 | if (IS_MF_FCOE_AFEX(bp)) | |
10404 | /* use FIP MAC as primary MAC */ | |
10405 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); | |
10406 | ||
37b091ba | 10407 | #endif |
0793f83f DK |
10408 | } else { |
10409 | /* in SF read MACs from port configuration */ | |
10410 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
10411 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
10412 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
10413 | ||
10414 | #ifdef BCM_CNIC | |
10415 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
10416 | iscsi_mac_upper); | |
10417 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
10418 | iscsi_mac_lower); | |
2ba45142 | 10419 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
10420 | |
10421 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
10422 | fcoe_fip_mac_upper); | |
10423 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
10424 | fcoe_fip_mac_lower); | |
10425 | bnx2x_set_mac_buf(fip_mac, val, val2); | |
0793f83f DK |
10426 | #endif |
10427 | } | |
10428 | ||
10429 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); | |
10430 | memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); | |
10431 | ||
ec6ba945 | 10432 | #ifdef BCM_CNIC |
426b9241 DK |
10433 | /* Disable iSCSI if MAC configuration is |
10434 | * invalid. | |
10435 | */ | |
10436 | if (!is_valid_ether_addr(iscsi_mac)) { | |
10437 | bp->flags |= NO_ISCSI_FLAG; | |
10438 | memset(iscsi_mac, 0, ETH_ALEN); | |
10439 | } | |
10440 | ||
10441 | /* Disable FCoE if MAC configuration is | |
10442 | * invalid. | |
10443 | */ | |
10444 | if (!is_valid_ether_addr(fip_mac)) { | |
10445 | bp->flags |= NO_FCOE_FLAG; | |
10446 | memset(bp->fip_mac, 0, ETH_ALEN); | |
10447 | } | |
ec6ba945 | 10448 | #endif |
619c5cb6 | 10449 | |
614c76df | 10450 | if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) |
619c5cb6 | 10451 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10452 | "bad Ethernet MAC address configuration: %pM\n" |
10453 | "change it manually before bringing up the appropriate network interface\n", | |
0f9dad10 | 10454 | bp->dev->dev_addr); |
51c1a580 MS |
10455 | |
10456 | ||
34f80b04 EG |
10457 | } |
10458 | ||
10459 | static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |
10460 | { | |
0793f83f | 10461 | int /*abs*/func = BP_ABS_FUNC(bp); |
b8ee8328 | 10462 | int vn; |
0793f83f | 10463 | u32 val = 0; |
34f80b04 | 10464 | int rc = 0; |
a2fbb9ea | 10465 | |
34f80b04 | 10466 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 10467 | |
6383c0b3 AE |
10468 | /* |
10469 | * initialize IGU parameters | |
10470 | */ | |
f2e0899f DK |
10471 | if (CHIP_IS_E1x(bp)) { |
10472 | bp->common.int_block = INT_BLOCK_HC; | |
10473 | ||
10474 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
10475 | bp->igu_base_sb = 0; | |
f2e0899f DK |
10476 | } else { |
10477 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 DK |
10478 | |
10479 | /* do not allow device reset during IGU info preocessing */ | |
10480 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | |
10481 | ||
f2e0899f | 10482 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
10483 | |
10484 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
10485 | int tout = 5000; | |
10486 | ||
10487 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
10488 | ||
10489 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
10490 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
10491 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
10492 | ||
10493 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
10494 | tout--; | |
10495 | usleep_range(1000, 1000); | |
10496 | } | |
10497 | ||
10498 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
10499 | dev_err(&bp->pdev->dev, | |
10500 | "FORCING Normal Mode failed!!!\n"); | |
10501 | return -EPERM; | |
10502 | } | |
10503 | } | |
10504 | ||
f2e0899f | 10505 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 10506 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
10507 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
10508 | } else | |
619c5cb6 | 10509 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 10510 | |
f2e0899f DK |
10511 | bnx2x_get_igu_cam_info(bp); |
10512 | ||
7a06a122 | 10513 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
f2e0899f | 10514 | } |
619c5cb6 VZ |
10515 | |
10516 | /* | |
10517 | * set base FW non-default (fast path) status block id, this value is | |
10518 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
10519 | * determine the id used by the FW. | |
10520 | */ | |
10521 | if (CHIP_IS_E1x(bp)) | |
10522 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
10523 | else /* | |
10524 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
10525 | * the same queue are indicated on the same IGU SB). So we prefer | |
10526 | * FW and IGU SBs to be the same value. | |
10527 | */ | |
10528 | bp->base_fw_ndsb = bp->igu_base_sb; | |
10529 | ||
10530 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
10531 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
10532 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
10533 | |
10534 | /* | |
10535 | * Initialize MF configuration | |
10536 | */ | |
523224a3 | 10537 | |
fb3bff17 DK |
10538 | bp->mf_ov = 0; |
10539 | bp->mf_mode = 0; | |
3395a033 | 10540 | vn = BP_VN(bp); |
0793f83f | 10541 | |
f2e0899f | 10542 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
10543 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
10544 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
10545 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
10546 | ||
f2e0899f DK |
10547 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
10548 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
10549 | else | |
10550 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
10551 | offsetof(struct shmem_region, func_mb) + |
10552 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
10553 | /* |
10554 | * get mf configuration: | |
25985edc | 10555 | * 1. existence of MF configuration |
0793f83f DK |
10556 | * 2. MAC address must be legal (check only upper bytes) |
10557 | * for Switch-Independent mode; | |
10558 | * OVLAN must be legal for Switch-Dependent mode | |
10559 | * 3. SF_MODE configures specific MF mode | |
10560 | */ | |
10561 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
10562 | /* get mf configuration */ | |
10563 | val = SHMEM_RD(bp, | |
10564 | dev_info.shared_feature_config.config); | |
10565 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
10566 | ||
10567 | switch (val) { | |
10568 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
10569 | val = MF_CFG_RD(bp, func_mf_config[func]. | |
10570 | mac_upper); | |
10571 | /* check for legal mac (upper bytes)*/ | |
10572 | if (val != 0xffff) { | |
10573 | bp->mf_mode = MULTI_FUNCTION_SI; | |
10574 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10575 | func_mf_config[func].config); | |
10576 | } else | |
51c1a580 | 10577 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); |
0793f83f | 10578 | break; |
a3348722 BW |
10579 | case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: |
10580 | if ((!CHIP_IS_E1x(bp)) && | |
10581 | (MF_CFG_RD(bp, func_mf_config[func]. | |
10582 | mac_upper) != 0xffff) && | |
10583 | (SHMEM2_HAS(bp, | |
10584 | afex_driver_support))) { | |
10585 | bp->mf_mode = MULTI_FUNCTION_AFEX; | |
10586 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10587 | func_mf_config[func].config); | |
10588 | } else { | |
10589 | BNX2X_DEV_INFO("can not configure afex mode\n"); | |
10590 | } | |
10591 | break; | |
0793f83f DK |
10592 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: |
10593 | /* get OV configuration */ | |
10594 | val = MF_CFG_RD(bp, | |
10595 | func_mf_config[FUNC_0].e1hov_tag); | |
10596 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
10597 | ||
10598 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
10599 | bp->mf_mode = MULTI_FUNCTION_SD; | |
10600 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10601 | func_mf_config[func].config); | |
10602 | } else | |
754a2f52 | 10603 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f DK |
10604 | break; |
10605 | default: | |
10606 | /* Unknown configuration: reset mf_config */ | |
10607 | bp->mf_config[vn] = 0; | |
51c1a580 | 10608 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
0793f83f DK |
10609 | } |
10610 | } | |
a2fbb9ea | 10611 | |
2691d51d | 10612 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 10613 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 10614 | |
0793f83f DK |
10615 | switch (bp->mf_mode) { |
10616 | case MULTI_FUNCTION_SD: | |
10617 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
10618 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 10619 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 10620 | bp->mf_ov = val; |
619c5cb6 VZ |
10621 | bp->path_has_ovlan = true; |
10622 | ||
51c1a580 MS |
10623 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
10624 | func, bp->mf_ov, bp->mf_ov); | |
2691d51d | 10625 | } else { |
619c5cb6 | 10626 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10627 | "No valid MF OV for func %d, aborting\n", |
10628 | func); | |
619c5cb6 | 10629 | return -EPERM; |
34f80b04 | 10630 | } |
0793f83f | 10631 | break; |
a3348722 BW |
10632 | case MULTI_FUNCTION_AFEX: |
10633 | BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); | |
10634 | break; | |
0793f83f | 10635 | case MULTI_FUNCTION_SI: |
51c1a580 MS |
10636 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
10637 | func); | |
0793f83f DK |
10638 | break; |
10639 | default: | |
10640 | if (vn) { | |
619c5cb6 | 10641 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10642 | "VN %d is in a single function mode, aborting\n", |
10643 | vn); | |
619c5cb6 | 10644 | return -EPERM; |
2691d51d | 10645 | } |
0793f83f | 10646 | break; |
34f80b04 | 10647 | } |
0793f83f | 10648 | |
619c5cb6 VZ |
10649 | /* check if other port on the path needs ovlan: |
10650 | * Since MF configuration is shared between ports | |
10651 | * Possible mixed modes are only | |
10652 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
10653 | */ | |
10654 | if (CHIP_MODE_IS_4_PORT(bp) && | |
10655 | !bp->path_has_ovlan && | |
10656 | !IS_MF(bp) && | |
10657 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
10658 | u8 other_port = !BP_PORT(bp); | |
10659 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
10660 | val = MF_CFG_RD(bp, | |
10661 | func_mf_config[other_func].e1hov_tag); | |
10662 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
10663 | bp->path_has_ovlan = true; | |
10664 | } | |
34f80b04 | 10665 | } |
a2fbb9ea | 10666 | |
f2e0899f DK |
10667 | /* adjust igu_sb_cnt to MF for E1x */ |
10668 | if (CHIP_IS_E1x(bp) && IS_MF(bp)) | |
523224a3 DK |
10669 | bp->igu_sb_cnt /= E1HVN_MAX; |
10670 | ||
619c5cb6 VZ |
10671 | /* port info */ |
10672 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 10673 | |
0793f83f DK |
10674 | /* Get MAC addresses */ |
10675 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 10676 | |
2ba45142 | 10677 | bnx2x_get_cnic_info(bp); |
2ba45142 | 10678 | |
34f80b04 EG |
10679 | return rc; |
10680 | } | |
10681 | ||
34f24c7f VZ |
10682 | static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) |
10683 | { | |
10684 | int cnt, i, block_end, rodi; | |
fcdf95cb | 10685 | char vpd_start[BNX2X_VPD_LEN+1]; |
34f24c7f VZ |
10686 | char str_id_reg[VENDOR_ID_LEN+1]; |
10687 | char str_id_cap[VENDOR_ID_LEN+1]; | |
fcdf95cb BW |
10688 | char *vpd_data; |
10689 | char *vpd_extended_data = NULL; | |
34f24c7f VZ |
10690 | u8 len; |
10691 | ||
fcdf95cb | 10692 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); |
34f24c7f VZ |
10693 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
10694 | ||
10695 | if (cnt < BNX2X_VPD_LEN) | |
10696 | goto out_not_found; | |
10697 | ||
fcdf95cb BW |
10698 | /* VPD RO tag should be first tag after identifier string, hence |
10699 | * we should be able to find it in first BNX2X_VPD_LEN chars | |
10700 | */ | |
10701 | i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, | |
34f24c7f VZ |
10702 | PCI_VPD_LRDT_RO_DATA); |
10703 | if (i < 0) | |
10704 | goto out_not_found; | |
10705 | ||
34f24c7f | 10706 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + |
fcdf95cb | 10707 | pci_vpd_lrdt_size(&vpd_start[i]); |
34f24c7f VZ |
10708 | |
10709 | i += PCI_VPD_LRDT_TAG_SIZE; | |
10710 | ||
fcdf95cb BW |
10711 | if (block_end > BNX2X_VPD_LEN) { |
10712 | vpd_extended_data = kmalloc(block_end, GFP_KERNEL); | |
10713 | if (vpd_extended_data == NULL) | |
10714 | goto out_not_found; | |
10715 | ||
10716 | /* read rest of vpd image into vpd_extended_data */ | |
10717 | memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); | |
10718 | cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, | |
10719 | block_end - BNX2X_VPD_LEN, | |
10720 | vpd_extended_data + BNX2X_VPD_LEN); | |
10721 | if (cnt < (block_end - BNX2X_VPD_LEN)) | |
10722 | goto out_not_found; | |
10723 | vpd_data = vpd_extended_data; | |
10724 | } else | |
10725 | vpd_data = vpd_start; | |
10726 | ||
10727 | /* now vpd_data holds full vpd content in both cases */ | |
34f24c7f VZ |
10728 | |
10729 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
10730 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
10731 | if (rodi < 0) | |
10732 | goto out_not_found; | |
10733 | ||
10734 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
10735 | ||
10736 | if (len != VENDOR_ID_LEN) | |
10737 | goto out_not_found; | |
10738 | ||
10739 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10740 | ||
10741 | /* vendor specific info */ | |
10742 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
10743 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
10744 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
10745 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
10746 | ||
10747 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
10748 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
10749 | if (rodi >= 0) { | |
10750 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
10751 | ||
10752 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10753 | ||
10754 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
10755 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
10756 | bp->fw_ver[len] = ' '; | |
10757 | } | |
10758 | } | |
fcdf95cb | 10759 | kfree(vpd_extended_data); |
34f24c7f VZ |
10760 | return; |
10761 | } | |
10762 | out_not_found: | |
fcdf95cb | 10763 | kfree(vpd_extended_data); |
34f24c7f VZ |
10764 | return; |
10765 | } | |
10766 | ||
619c5cb6 VZ |
10767 | static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) |
10768 | { | |
10769 | u32 flags = 0; | |
10770 | ||
10771 | if (CHIP_REV_IS_FPGA(bp)) | |
10772 | SET_FLAGS(flags, MODE_FPGA); | |
10773 | else if (CHIP_REV_IS_EMUL(bp)) | |
10774 | SET_FLAGS(flags, MODE_EMUL); | |
10775 | else | |
10776 | SET_FLAGS(flags, MODE_ASIC); | |
10777 | ||
10778 | if (CHIP_MODE_IS_4_PORT(bp)) | |
10779 | SET_FLAGS(flags, MODE_PORT4); | |
10780 | else | |
10781 | SET_FLAGS(flags, MODE_PORT2); | |
10782 | ||
10783 | if (CHIP_IS_E2(bp)) | |
10784 | SET_FLAGS(flags, MODE_E2); | |
10785 | else if (CHIP_IS_E3(bp)) { | |
10786 | SET_FLAGS(flags, MODE_E3); | |
10787 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
10788 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
10789 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
10790 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
10791 | } |
10792 | ||
10793 | if (IS_MF(bp)) { | |
10794 | SET_FLAGS(flags, MODE_MF); | |
10795 | switch (bp->mf_mode) { | |
10796 | case MULTI_FUNCTION_SD: | |
10797 | SET_FLAGS(flags, MODE_MF_SD); | |
10798 | break; | |
10799 | case MULTI_FUNCTION_SI: | |
10800 | SET_FLAGS(flags, MODE_MF_SI); | |
10801 | break; | |
a3348722 BW |
10802 | case MULTI_FUNCTION_AFEX: |
10803 | SET_FLAGS(flags, MODE_MF_AFEX); | |
10804 | break; | |
619c5cb6 VZ |
10805 | } |
10806 | } else | |
10807 | SET_FLAGS(flags, MODE_SF); | |
10808 | ||
10809 | #if defined(__LITTLE_ENDIAN) | |
10810 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
10811 | #else /*(__BIG_ENDIAN)*/ | |
10812 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
10813 | #endif | |
10814 | INIT_MODE_FLAGS(bp) = flags; | |
10815 | } | |
10816 | ||
34f80b04 EG |
10817 | static int __devinit bnx2x_init_bp(struct bnx2x *bp) |
10818 | { | |
f2e0899f | 10819 | int func; |
34f80b04 EG |
10820 | int rc; |
10821 | ||
34f80b04 | 10822 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 10823 | mutex_init(&bp->fw_mb_mutex); |
bb7e95c8 | 10824 | spin_lock_init(&bp->stats_lock); |
993ac7b5 MC |
10825 | #ifdef BCM_CNIC |
10826 | mutex_init(&bp->cnic_mutex); | |
10827 | #endif | |
a2fbb9ea | 10828 | |
1cf167f2 | 10829 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 10830 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 10831 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
34f80b04 | 10832 | rc = bnx2x_get_hwinfo(bp); |
619c5cb6 VZ |
10833 | if (rc) |
10834 | return rc; | |
34f80b04 | 10835 | |
619c5cb6 VZ |
10836 | bnx2x_set_modes_bitmap(bp); |
10837 | ||
10838 | rc = bnx2x_alloc_mem_bp(bp); | |
10839 | if (rc) | |
10840 | return rc; | |
523224a3 | 10841 | |
34f24c7f | 10842 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
10843 | |
10844 | func = BP_FUNC(bp); | |
10845 | ||
34f80b04 | 10846 | /* need to reset chip if undi was active */ |
452427b0 YM |
10847 | if (!BP_NOMCP(bp)) { |
10848 | /* init fw_seq */ | |
10849 | bp->fw_seq = | |
10850 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
10851 | DRV_MSG_SEQ_NUMBER_MASK; | |
10852 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
10853 | ||
10854 | bnx2x_prev_unload(bp); | |
10855 | } | |
10856 | ||
34f80b04 EG |
10857 | |
10858 | if (CHIP_REV_IS_FPGA(bp)) | |
cdaa7cb8 | 10859 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
10860 | |
10861 | if (BP_NOMCP(bp) && (func == 0)) | |
51c1a580 | 10862 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
34f80b04 | 10863 | |
614c76df DK |
10864 | bp->disable_tpa = disable_tpa; |
10865 | ||
10866 | #ifdef BCM_CNIC | |
a3348722 | 10867 | bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp); |
614c76df DK |
10868 | #endif |
10869 | ||
7a9b2557 | 10870 | /* Set TPA flags */ |
614c76df | 10871 | if (bp->disable_tpa) { |
621b4d66 | 10872 | bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
10873 | bp->dev->features &= ~NETIF_F_LRO; |
10874 | } else { | |
621b4d66 | 10875 | bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
10876 | bp->dev->features |= NETIF_F_LRO; |
10877 | } | |
10878 | ||
a18f5128 EG |
10879 | if (CHIP_IS_E1(bp)) |
10880 | bp->dropless_fc = 0; | |
10881 | else | |
10882 | bp->dropless_fc = dropless_fc; | |
10883 | ||
8d5726c4 | 10884 | bp->mrrs = mrrs; |
7a9b2557 | 10885 | |
a3348722 | 10886 | bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; |
34f80b04 | 10887 | |
7d323bfd | 10888 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
10889 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
10890 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 10891 | |
fc543637 | 10892 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
34f80b04 EG |
10893 | |
10894 | init_timer(&bp->timer); | |
10895 | bp->timer.expires = jiffies + bp->current_interval; | |
10896 | bp->timer.data = (unsigned long) bp; | |
10897 | bp->timer.function = bnx2x_timer; | |
10898 | ||
785b9b1a | 10899 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); |
e4901dde VZ |
10900 | bnx2x_dcbx_init_params(bp); |
10901 | ||
619c5cb6 VZ |
10902 | #ifdef BCM_CNIC |
10903 | if (CHIP_IS_E1x(bp)) | |
10904 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
10905 | else | |
10906 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
10907 | #endif | |
10908 | ||
6383c0b3 AE |
10909 | /* multiple tx priority */ |
10910 | if (CHIP_IS_E1x(bp)) | |
10911 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; | |
10912 | if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) | |
10913 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; | |
10914 | if (CHIP_IS_E3B0(bp)) | |
10915 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; | |
10916 | ||
34f80b04 | 10917 | return rc; |
a2fbb9ea ET |
10918 | } |
10919 | ||
a2fbb9ea | 10920 | |
de0c62db DK |
10921 | /**************************************************************************** |
10922 | * General service functions | |
10923 | ****************************************************************************/ | |
a2fbb9ea | 10924 | |
619c5cb6 VZ |
10925 | /* |
10926 | * net_device service functions | |
10927 | */ | |
10928 | ||
bb2a0f7a | 10929 | /* called with rtnl_lock */ |
a2fbb9ea ET |
10930 | static int bnx2x_open(struct net_device *dev) |
10931 | { | |
10932 | struct bnx2x *bp = netdev_priv(dev); | |
c9ee9206 VZ |
10933 | bool global = false; |
10934 | int other_engine = BP_PATH(bp) ? 0 : 1; | |
889b9af3 | 10935 | bool other_load_status, load_status; |
a2fbb9ea | 10936 | |
1355b704 MY |
10937 | bp->stats_init = true; |
10938 | ||
6eccabb3 EG |
10939 | netif_carrier_off(dev); |
10940 | ||
a2fbb9ea ET |
10941 | bnx2x_set_power_state(bp, PCI_D0); |
10942 | ||
889b9af3 AE |
10943 | other_load_status = bnx2x_get_load_status(bp, other_engine); |
10944 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
10945 | |
10946 | /* | |
10947 | * If parity had happen during the unload, then attentions | |
10948 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we | |
10949 | * want the first function loaded on the current engine to | |
10950 | * complete the recovery. | |
10951 | */ | |
10952 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
10953 | bnx2x_chk_parity_attn(bp, &global, true)) | |
72fd0718 | 10954 | do { |
c9ee9206 VZ |
10955 | /* |
10956 | * If there are attentions and they are in a global | |
10957 | * blocks, set the GLOBAL_RESET bit regardless whether | |
10958 | * it will be this function that will complete the | |
10959 | * recovery or not. | |
72fd0718 | 10960 | */ |
c9ee9206 VZ |
10961 | if (global) |
10962 | bnx2x_set_reset_global(bp); | |
72fd0718 | 10963 | |
c9ee9206 VZ |
10964 | /* |
10965 | * Only the first function on the current engine should | |
10966 | * try to recover in open. In case of attentions in | |
10967 | * global blocks only the first in the chip should try | |
10968 | * to recover. | |
72fd0718 | 10969 | */ |
889b9af3 AE |
10970 | if ((!load_status && |
10971 | (!global || !other_load_status)) && | |
c9ee9206 VZ |
10972 | bnx2x_trylock_leader_lock(bp) && |
10973 | !bnx2x_leader_reset(bp)) { | |
10974 | netdev_info(bp->dev, "Recovered in open\n"); | |
72fd0718 VZ |
10975 | break; |
10976 | } | |
10977 | ||
c9ee9206 | 10978 | /* recovery has failed... */ |
72fd0718 | 10979 | bnx2x_set_power_state(bp, PCI_D3hot); |
c9ee9206 | 10980 | bp->recovery_state = BNX2X_RECOVERY_FAILED; |
72fd0718 | 10981 | |
51c1a580 MS |
10982 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
10983 | "If you still see this message after a few retries then power cycle is required.\n"); | |
72fd0718 VZ |
10984 | |
10985 | return -EAGAIN; | |
10986 | } while (0); | |
72fd0718 VZ |
10987 | |
10988 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
bb2a0f7a | 10989 | return bnx2x_nic_load(bp, LOAD_OPEN); |
a2fbb9ea ET |
10990 | } |
10991 | ||
bb2a0f7a | 10992 | /* called with rtnl_lock */ |
56ad3152 | 10993 | static int bnx2x_close(struct net_device *dev) |
a2fbb9ea | 10994 | { |
a2fbb9ea ET |
10995 | struct bnx2x *bp = netdev_priv(dev); |
10996 | ||
10997 | /* Unload the driver, release IRQs */ | |
bb2a0f7a | 10998 | bnx2x_nic_unload(bp, UNLOAD_CLOSE); |
c9ee9206 VZ |
10999 | |
11000 | /* Power off */ | |
d3dbfee0 | 11001 | bnx2x_set_power_state(bp, PCI_D3hot); |
a2fbb9ea ET |
11002 | |
11003 | return 0; | |
11004 | } | |
11005 | ||
1191cb83 ED |
11006 | static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
11007 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 11008 | { |
619c5cb6 VZ |
11009 | int mc_count = netdev_mc_count(bp->dev); |
11010 | struct bnx2x_mcast_list_elem *mc_mac = | |
11011 | kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); | |
11012 | struct netdev_hw_addr *ha; | |
6e30dd4e | 11013 | |
619c5cb6 VZ |
11014 | if (!mc_mac) |
11015 | return -ENOMEM; | |
6e30dd4e | 11016 | |
619c5cb6 | 11017 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 11018 | |
619c5cb6 VZ |
11019 | netdev_for_each_mc_addr(ha, bp->dev) { |
11020 | mc_mac->mac = bnx2x_mc_addr(ha); | |
11021 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
11022 | mc_mac++; | |
6e30dd4e | 11023 | } |
619c5cb6 VZ |
11024 | |
11025 | p->mcast_list_len = mc_count; | |
11026 | ||
11027 | return 0; | |
6e30dd4e VZ |
11028 | } |
11029 | ||
1191cb83 | 11030 | static void bnx2x_free_mcast_macs_list( |
619c5cb6 VZ |
11031 | struct bnx2x_mcast_ramrod_params *p) |
11032 | { | |
11033 | struct bnx2x_mcast_list_elem *mc_mac = | |
11034 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
11035 | link); | |
11036 | ||
11037 | WARN_ON(!mc_mac); | |
11038 | kfree(mc_mac); | |
11039 | } | |
11040 | ||
11041 | /** | |
11042 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
11043 | * | |
11044 | * @bp: driver handle | |
6e30dd4e | 11045 | * |
619c5cb6 | 11046 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 11047 | */ |
1191cb83 | 11048 | static int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 11049 | { |
619c5cb6 | 11050 | int rc; |
6e30dd4e | 11051 | struct net_device *dev = bp->dev; |
6e30dd4e | 11052 | struct netdev_hw_addr *ha; |
15192a8c | 11053 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; |
619c5cb6 | 11054 | unsigned long ramrod_flags = 0; |
6e30dd4e | 11055 | |
619c5cb6 VZ |
11056 | /* First schedule a cleanup up of old configuration */ |
11057 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
11058 | if (rc < 0) { | |
11059 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
11060 | return rc; | |
11061 | } | |
6e30dd4e VZ |
11062 | |
11063 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
11064 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
11065 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
11066 | if (rc < 0) { | |
11067 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", | |
11068 | rc); | |
11069 | return rc; | |
6e30dd4e VZ |
11070 | } |
11071 | } | |
11072 | ||
619c5cb6 VZ |
11073 | /* Execute the pending commands */ |
11074 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
11075 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
11076 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
11077 | } |
11078 | ||
1191cb83 | 11079 | static int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 11080 | { |
619c5cb6 | 11081 | struct net_device *dev = bp->dev; |
3b603066 | 11082 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 | 11083 | int rc = 0; |
6e30dd4e | 11084 | |
619c5cb6 | 11085 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 11086 | |
619c5cb6 VZ |
11087 | /* first, clear all configured multicast MACs */ |
11088 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
11089 | if (rc < 0) { | |
51c1a580 | 11090 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
619c5cb6 VZ |
11091 | return rc; |
11092 | } | |
6e30dd4e | 11093 | |
619c5cb6 VZ |
11094 | /* then, configure a new MACs list */ |
11095 | if (netdev_mc_count(dev)) { | |
11096 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
11097 | if (rc) { | |
51c1a580 MS |
11098 | BNX2X_ERR("Failed to create multicast MACs list: %d\n", |
11099 | rc); | |
619c5cb6 VZ |
11100 | return rc; |
11101 | } | |
6e30dd4e | 11102 | |
619c5cb6 VZ |
11103 | /* Now add the new MACs */ |
11104 | rc = bnx2x_config_mcast(bp, &rparam, | |
11105 | BNX2X_MCAST_CMD_ADD); | |
11106 | if (rc < 0) | |
51c1a580 MS |
11107 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
11108 | rc); | |
6e30dd4e | 11109 | |
619c5cb6 VZ |
11110 | bnx2x_free_mcast_macs_list(&rparam); |
11111 | } | |
6e30dd4e | 11112 | |
619c5cb6 | 11113 | return rc; |
6e30dd4e VZ |
11114 | } |
11115 | ||
6e30dd4e | 11116 | |
619c5cb6 | 11117 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
9f6c9258 | 11118 | void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
11119 | { |
11120 | struct bnx2x *bp = netdev_priv(dev); | |
11121 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 EG |
11122 | |
11123 | if (bp->state != BNX2X_STATE_OPEN) { | |
11124 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
11125 | return; | |
11126 | } | |
11127 | ||
619c5cb6 | 11128 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 EG |
11129 | |
11130 | if (dev->flags & IFF_PROMISC) | |
11131 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
619c5cb6 VZ |
11132 | else if ((dev->flags & IFF_ALLMULTI) || |
11133 | ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && | |
11134 | CHIP_IS_E1(bp))) | |
34f80b04 | 11135 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
6e30dd4e VZ |
11136 | else { |
11137 | /* some multicasts */ | |
619c5cb6 | 11138 | if (bnx2x_set_mc_list(bp) < 0) |
6e30dd4e | 11139 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
34f80b04 | 11140 | |
619c5cb6 | 11141 | if (bnx2x_set_uc_list(bp) < 0) |
6e30dd4e | 11142 | rx_mode = BNX2X_RX_MODE_PROMISC; |
34f80b04 EG |
11143 | } |
11144 | ||
11145 | bp->rx_mode = rx_mode; | |
614c76df DK |
11146 | #ifdef BCM_CNIC |
11147 | /* handle ISCSI SD mode */ | |
11148 | if (IS_MF_ISCSI_SD(bp)) | |
11149 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
11150 | #endif | |
619c5cb6 VZ |
11151 | |
11152 | /* Schedule the rx_mode command */ | |
11153 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
11154 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
11155 | return; | |
11156 | } | |
11157 | ||
34f80b04 EG |
11158 | bnx2x_set_storm_rx_mode(bp); |
11159 | } | |
11160 | ||
c18487ee | 11161 | /* called with rtnl_lock */ |
01cd4528 EG |
11162 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
11163 | int devad, u16 addr) | |
a2fbb9ea | 11164 | { |
01cd4528 EG |
11165 | struct bnx2x *bp = netdev_priv(netdev); |
11166 | u16 value; | |
11167 | int rc; | |
a2fbb9ea | 11168 | |
01cd4528 EG |
11169 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
11170 | prtad, devad, addr); | |
a2fbb9ea | 11171 | |
01cd4528 EG |
11172 | /* The HW expects different devad if CL22 is used */ |
11173 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 11174 | |
01cd4528 | 11175 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11176 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
11177 | bnx2x_release_phy_lock(bp); |
11178 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 11179 | |
01cd4528 EG |
11180 | if (!rc) |
11181 | rc = value; | |
11182 | return rc; | |
11183 | } | |
a2fbb9ea | 11184 | |
01cd4528 EG |
11185 | /* called with rtnl_lock */ |
11186 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
11187 | u16 addr, u16 value) | |
11188 | { | |
11189 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
11190 | int rc; |
11191 | ||
51c1a580 MS |
11192 | DP(NETIF_MSG_LINK, |
11193 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", | |
11194 | prtad, devad, addr, value); | |
01cd4528 | 11195 | |
01cd4528 EG |
11196 | /* The HW expects different devad if CL22 is used */ |
11197 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 11198 | |
01cd4528 | 11199 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11200 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
11201 | bnx2x_release_phy_lock(bp); |
11202 | return rc; | |
11203 | } | |
c18487ee | 11204 | |
01cd4528 EG |
11205 | /* called with rtnl_lock */ |
11206 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
11207 | { | |
11208 | struct bnx2x *bp = netdev_priv(dev); | |
11209 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 11210 | |
01cd4528 EG |
11211 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", |
11212 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
a2fbb9ea | 11213 | |
01cd4528 EG |
11214 | if (!netif_running(dev)) |
11215 | return -EAGAIN; | |
11216 | ||
11217 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
a2fbb9ea ET |
11218 | } |
11219 | ||
257ddbda | 11220 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
11221 | static void poll_bnx2x(struct net_device *dev) |
11222 | { | |
11223 | struct bnx2x *bp = netdev_priv(dev); | |
11224 | ||
11225 | disable_irq(bp->pdev->irq); | |
11226 | bnx2x_interrupt(bp->pdev->irq, dev); | |
11227 | enable_irq(bp->pdev->irq); | |
11228 | } | |
11229 | #endif | |
11230 | ||
614c76df DK |
11231 | static int bnx2x_validate_addr(struct net_device *dev) |
11232 | { | |
11233 | struct bnx2x *bp = netdev_priv(dev); | |
11234 | ||
51c1a580 MS |
11235 | if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { |
11236 | BNX2X_ERR("Non-valid Ethernet address\n"); | |
614c76df | 11237 | return -EADDRNOTAVAIL; |
51c1a580 | 11238 | } |
614c76df DK |
11239 | return 0; |
11240 | } | |
11241 | ||
c64213cd SH |
11242 | static const struct net_device_ops bnx2x_netdev_ops = { |
11243 | .ndo_open = bnx2x_open, | |
11244 | .ndo_stop = bnx2x_close, | |
11245 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 11246 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 11247 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd | 11248 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
614c76df | 11249 | .ndo_validate_addr = bnx2x_validate_addr, |
c64213cd SH |
11250 | .ndo_do_ioctl = bnx2x_ioctl, |
11251 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
11252 | .ndo_fix_features = bnx2x_fix_features, |
11253 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 11254 | .ndo_tx_timeout = bnx2x_tx_timeout, |
257ddbda | 11255 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
11256 | .ndo_poll_controller = poll_bnx2x, |
11257 | #endif | |
6383c0b3 AE |
11258 | .ndo_setup_tc = bnx2x_setup_tc, |
11259 | ||
bf61ee14 VZ |
11260 | #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) |
11261 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, | |
11262 | #endif | |
c64213cd SH |
11263 | }; |
11264 | ||
1191cb83 | 11265 | static int bnx2x_set_coherency_mask(struct bnx2x *bp) |
619c5cb6 VZ |
11266 | { |
11267 | struct device *dev = &bp->pdev->dev; | |
11268 | ||
11269 | if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { | |
11270 | bp->flags |= USING_DAC_FLAG; | |
11271 | if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { | |
51c1a580 | 11272 | dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); |
619c5cb6 VZ |
11273 | return -EIO; |
11274 | } | |
11275 | } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { | |
11276 | dev_err(dev, "System does not support DMA, aborting\n"); | |
11277 | return -EIO; | |
11278 | } | |
11279 | ||
11280 | return 0; | |
11281 | } | |
11282 | ||
34f80b04 | 11283 | static int __devinit bnx2x_init_dev(struct pci_dev *pdev, |
619c5cb6 VZ |
11284 | struct net_device *dev, |
11285 | unsigned long board_type) | |
a2fbb9ea ET |
11286 | { |
11287 | struct bnx2x *bp; | |
11288 | int rc; | |
c22610d0 | 11289 | u32 pci_cfg_dword; |
65087cfe AE |
11290 | bool chip_is_e1x = (board_type == BCM57710 || |
11291 | board_type == BCM57711 || | |
11292 | board_type == BCM57711E); | |
a2fbb9ea ET |
11293 | |
11294 | SET_NETDEV_DEV(dev, &pdev->dev); | |
11295 | bp = netdev_priv(dev); | |
11296 | ||
34f80b04 EG |
11297 | bp->dev = dev; |
11298 | bp->pdev = pdev; | |
a2fbb9ea | 11299 | bp->flags = 0; |
a2fbb9ea ET |
11300 | |
11301 | rc = pci_enable_device(pdev); | |
11302 | if (rc) { | |
cdaa7cb8 VZ |
11303 | dev_err(&bp->pdev->dev, |
11304 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
11305 | goto err_out; |
11306 | } | |
11307 | ||
11308 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
11309 | dev_err(&bp->pdev->dev, |
11310 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
11311 | rc = -ENODEV; |
11312 | goto err_out_disable; | |
11313 | } | |
11314 | ||
11315 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
11316 | dev_err(&bp->pdev->dev, "Cannot find second PCI device" |
11317 | " base address, aborting\n"); | |
a2fbb9ea ET |
11318 | rc = -ENODEV; |
11319 | goto err_out_disable; | |
11320 | } | |
11321 | ||
34f80b04 EG |
11322 | if (atomic_read(&pdev->enable_cnt) == 1) { |
11323 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
11324 | if (rc) { | |
cdaa7cb8 VZ |
11325 | dev_err(&bp->pdev->dev, |
11326 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
11327 | goto err_out_disable; |
11328 | } | |
a2fbb9ea | 11329 | |
34f80b04 EG |
11330 | pci_set_master(pdev); |
11331 | pci_save_state(pdev); | |
11332 | } | |
a2fbb9ea ET |
11333 | |
11334 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
11335 | if (bp->pm_cap == 0) { | |
cdaa7cb8 VZ |
11336 | dev_err(&bp->pdev->dev, |
11337 | "Cannot find power management capability, aborting\n"); | |
a2fbb9ea ET |
11338 | rc = -EIO; |
11339 | goto err_out_release; | |
11340 | } | |
11341 | ||
77c98e6a | 11342 | if (!pci_is_pcie(pdev)) { |
51c1a580 | 11343 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
a2fbb9ea ET |
11344 | rc = -EIO; |
11345 | goto err_out_release; | |
11346 | } | |
11347 | ||
619c5cb6 VZ |
11348 | rc = bnx2x_set_coherency_mask(bp); |
11349 | if (rc) | |
a2fbb9ea | 11350 | goto err_out_release; |
a2fbb9ea | 11351 | |
34f80b04 EG |
11352 | dev->mem_start = pci_resource_start(pdev, 0); |
11353 | dev->base_addr = dev->mem_start; | |
11354 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
11355 | |
11356 | dev->irq = pdev->irq; | |
11357 | ||
275f165f | 11358 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 11359 | if (!bp->regview) { |
cdaa7cb8 VZ |
11360 | dev_err(&bp->pdev->dev, |
11361 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
11362 | rc = -ENOMEM; |
11363 | goto err_out_release; | |
11364 | } | |
11365 | ||
c22610d0 AE |
11366 | /* In E1/E1H use pci device function given by kernel. |
11367 | * In E2/E3 read physical function from ME register since these chips | |
11368 | * support Physical Device Assignment where kernel BDF maybe arbitrary | |
11369 | * (depending on hypervisor). | |
11370 | */ | |
11371 | if (chip_is_e1x) | |
11372 | bp->pf_num = PCI_FUNC(pdev->devfn); | |
11373 | else {/* chip is E2/3*/ | |
11374 | pci_read_config_dword(bp->pdev, | |
11375 | PCICFG_ME_REGISTER, &pci_cfg_dword); | |
11376 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> | |
11377 | ME_REG_ABS_PF_NUM_SHIFT); | |
11378 | } | |
51c1a580 | 11379 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
c22610d0 | 11380 | |
a2fbb9ea ET |
11381 | bnx2x_set_power_state(bp, PCI_D0); |
11382 | ||
34f80b04 EG |
11383 | /* clean indirect addresses */ |
11384 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
11385 | PCICFG_VENDOR_ID_OFFSET); | |
a5c53dbc DK |
11386 | /* |
11387 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
11388 | * is not used by the driver. |
11389 | */ | |
11390 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
11391 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
11392 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
11393 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
a5c53dbc | 11394 | |
65087cfe | 11395 | if (chip_is_e1x) { |
a5c53dbc DK |
11396 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); |
11397 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
11398 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
11399 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
11400 | } | |
a2fbb9ea | 11401 | |
2189400b | 11402 | /* |
619c5cb6 | 11403 | * Enable internal target-read (in case we are probed after PF FLR). |
2189400b | 11404 | * Must be done prior to any BAR read access. Only for 57712 and up |
619c5cb6 | 11405 | */ |
65087cfe | 11406 | if (!chip_is_e1x) |
2189400b | 11407 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); |
619c5cb6 | 11408 | |
72fd0718 | 11409 | /* Reset the load counter */ |
889b9af3 | 11410 | bnx2x_clear_load_status(bp); |
72fd0718 | 11411 | |
34f80b04 | 11412 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 11413 | |
c64213cd | 11414 | dev->netdev_ops = &bnx2x_netdev_ops; |
de0c62db | 11415 | bnx2x_set_ethtool_ops(dev); |
5316bc0b | 11416 | |
01789349 JP |
11417 | dev->priv_flags |= IFF_UNICAST_FLT; |
11418 | ||
66371c44 | 11419 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
621b4d66 DK |
11420 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
11421 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | | |
11422 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; | |
66371c44 MM |
11423 | |
11424 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
11425 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
11426 | ||
11427 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; | |
5316bc0b | 11428 | if (bp->flags & USING_DAC_FLAG) |
66371c44 | 11429 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 11430 | |
538dd2e3 MB |
11431 | /* Add Loopback capability to the device */ |
11432 | dev->hw_features |= NETIF_F_LOOPBACK; | |
11433 | ||
98507672 | 11434 | #ifdef BCM_DCBNL |
785b9b1a SR |
11435 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
11436 | #endif | |
11437 | ||
01cd4528 EG |
11438 | /* get_port_hwinfo() will set prtad and mmds properly */ |
11439 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
11440 | bp->mdio.mmds = 0; | |
11441 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
11442 | bp->mdio.dev = dev; | |
11443 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
11444 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
11445 | ||
a2fbb9ea ET |
11446 | return 0; |
11447 | ||
a2fbb9ea | 11448 | err_out_release: |
34f80b04 EG |
11449 | if (atomic_read(&pdev->enable_cnt) == 1) |
11450 | pci_release_regions(pdev); | |
a2fbb9ea ET |
11451 | |
11452 | err_out_disable: | |
11453 | pci_disable_device(pdev); | |
11454 | pci_set_drvdata(pdev, NULL); | |
11455 | ||
11456 | err_out: | |
11457 | return rc; | |
11458 | } | |
11459 | ||
37f9ce62 EG |
11460 | static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, |
11461 | int *width, int *speed) | |
25047950 ET |
11462 | { |
11463 | u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); | |
11464 | ||
37f9ce62 | 11465 | *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; |
25047950 | 11466 | |
37f9ce62 EG |
11467 | /* return value of 1=2.5GHz 2=5GHz */ |
11468 | *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; | |
25047950 | 11469 | } |
37f9ce62 | 11470 | |
6891dd25 | 11471 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 11472 | { |
37f9ce62 | 11473 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
11474 | struct bnx2x_fw_file_hdr *fw_hdr; |
11475 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 11476 | u32 offset, len, num_ops; |
37f9ce62 | 11477 | u16 *ops_offsets; |
94a78b79 | 11478 | int i; |
37f9ce62 | 11479 | const u8 *fw_ver; |
94a78b79 | 11480 | |
51c1a580 MS |
11481 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
11482 | BNX2X_ERR("Wrong FW size\n"); | |
94a78b79 | 11483 | return -EINVAL; |
51c1a580 | 11484 | } |
94a78b79 VZ |
11485 | |
11486 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
11487 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
11488 | ||
11489 | /* Make sure none of the offsets and sizes make us read beyond | |
11490 | * the end of the firmware data */ | |
11491 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
11492 | offset = be32_to_cpu(sections[i].offset); | |
11493 | len = be32_to_cpu(sections[i].len); | |
11494 | if (offset + len > firmware->size) { | |
51c1a580 | 11495 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
94a78b79 VZ |
11496 | return -EINVAL; |
11497 | } | |
11498 | } | |
11499 | ||
11500 | /* Likewise for the init_ops offsets */ | |
11501 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
11502 | ops_offsets = (u16 *)(firmware->data + offset); | |
11503 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); | |
11504 | ||
11505 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
11506 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
51c1a580 | 11507 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
94a78b79 VZ |
11508 | return -EINVAL; |
11509 | } | |
11510 | } | |
11511 | ||
11512 | /* Check FW version */ | |
11513 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
11514 | fw_ver = firmware->data + offset; | |
11515 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
11516 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
11517 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
11518 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
51c1a580 MS |
11519 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
11520 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], | |
11521 | BCM_5710_FW_MAJOR_VERSION, | |
94a78b79 VZ |
11522 | BCM_5710_FW_MINOR_VERSION, |
11523 | BCM_5710_FW_REVISION_VERSION, | |
11524 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 11525 | return -EINVAL; |
94a78b79 VZ |
11526 | } |
11527 | ||
11528 | return 0; | |
11529 | } | |
11530 | ||
1191cb83 | 11531 | static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11532 | { |
ab6ad5a4 EG |
11533 | const __be32 *source = (const __be32 *)_source; |
11534 | u32 *target = (u32 *)_target; | |
94a78b79 | 11535 | u32 i; |
94a78b79 VZ |
11536 | |
11537 | for (i = 0; i < n/4; i++) | |
11538 | target[i] = be32_to_cpu(source[i]); | |
11539 | } | |
11540 | ||
11541 | /* | |
11542 | Ops array is stored in the following format: | |
11543 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
11544 | */ | |
1191cb83 | 11545 | static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11546 | { |
ab6ad5a4 EG |
11547 | const __be32 *source = (const __be32 *)_source; |
11548 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 11549 | u32 i, j, tmp; |
94a78b79 | 11550 | |
ab6ad5a4 | 11551 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
11552 | tmp = be32_to_cpu(source[j]); |
11553 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
11554 | target[i].offset = tmp & 0xffffff; |
11555 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
11556 | } |
11557 | } | |
ab6ad5a4 | 11558 | |
523224a3 DK |
11559 | /** |
11560 | * IRO array is stored in the following format: | |
11561 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } | |
11562 | */ | |
1191cb83 | 11563 | static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) |
523224a3 DK |
11564 | { |
11565 | const __be32 *source = (const __be32 *)_source; | |
11566 | struct iro *target = (struct iro *)_target; | |
11567 | u32 i, j, tmp; | |
11568 | ||
11569 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
11570 | target[i].base = be32_to_cpu(source[j]); | |
11571 | j++; | |
11572 | tmp = be32_to_cpu(source[j]); | |
11573 | target[i].m1 = (tmp >> 16) & 0xffff; | |
11574 | target[i].m2 = tmp & 0xffff; | |
11575 | j++; | |
11576 | tmp = be32_to_cpu(source[j]); | |
11577 | target[i].m3 = (tmp >> 16) & 0xffff; | |
11578 | target[i].size = tmp & 0xffff; | |
11579 | j++; | |
11580 | } | |
11581 | } | |
11582 | ||
1191cb83 | 11583 | static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11584 | { |
ab6ad5a4 EG |
11585 | const __be16 *source = (const __be16 *)_source; |
11586 | u16 *target = (u16 *)_target; | |
94a78b79 | 11587 | u32 i; |
94a78b79 VZ |
11588 | |
11589 | for (i = 0; i < n/2; i++) | |
11590 | target[i] = be16_to_cpu(source[i]); | |
11591 | } | |
11592 | ||
7995c64e JP |
11593 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
11594 | do { \ | |
11595 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
11596 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
e404decb | 11597 | if (!bp->arr) \ |
7995c64e | 11598 | goto lbl; \ |
7995c64e JP |
11599 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
11600 | (u8 *)bp->arr, len); \ | |
11601 | } while (0) | |
94a78b79 | 11602 | |
3b603066 | 11603 | static int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 11604 | { |
c0ea452e | 11605 | const char *fw_file_name; |
94a78b79 | 11606 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 11607 | int rc; |
94a78b79 | 11608 | |
c0ea452e MS |
11609 | if (bp->firmware) |
11610 | return 0; | |
94a78b79 | 11611 | |
c0ea452e MS |
11612 | if (CHIP_IS_E1(bp)) |
11613 | fw_file_name = FW_FILE_NAME_E1; | |
11614 | else if (CHIP_IS_E1H(bp)) | |
11615 | fw_file_name = FW_FILE_NAME_E1H; | |
11616 | else if (!CHIP_IS_E1x(bp)) | |
11617 | fw_file_name = FW_FILE_NAME_E2; | |
11618 | else { | |
11619 | BNX2X_ERR("Unsupported chip revision\n"); | |
11620 | return -EINVAL; | |
11621 | } | |
11622 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); | |
94a78b79 | 11623 | |
c0ea452e MS |
11624 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
11625 | if (rc) { | |
11626 | BNX2X_ERR("Can't load firmware file %s\n", | |
11627 | fw_file_name); | |
11628 | goto request_firmware_exit; | |
11629 | } | |
eb2afd4a | 11630 | |
c0ea452e MS |
11631 | rc = bnx2x_check_firmware(bp); |
11632 | if (rc) { | |
11633 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); | |
11634 | goto request_firmware_exit; | |
94a78b79 VZ |
11635 | } |
11636 | ||
11637 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
11638 | ||
11639 | /* Initialize the pointers to the init arrays */ | |
11640 | /* Blob */ | |
11641 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
11642 | ||
11643 | /* Opcodes */ | |
11644 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
11645 | ||
11646 | /* Offsets */ | |
ab6ad5a4 EG |
11647 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
11648 | be16_to_cpu_n); | |
94a78b79 VZ |
11649 | |
11650 | /* STORMs firmware */ | |
573f2035 EG |
11651 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
11652 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
11653 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
11654 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
11655 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
11656 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
11657 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
11658 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
11659 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
11660 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
11661 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
11662 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
11663 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
11664 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
11665 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
11666 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
11667 | /* IRO */ |
11668 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
11669 | |
11670 | return 0; | |
ab6ad5a4 | 11671 | |
523224a3 DK |
11672 | iro_alloc_err: |
11673 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
11674 | init_offsets_alloc_err: |
11675 | kfree(bp->init_ops); | |
11676 | init_ops_alloc_err: | |
11677 | kfree(bp->init_data); | |
11678 | request_firmware_exit: | |
11679 | release_firmware(bp->firmware); | |
127d0a19 | 11680 | bp->firmware = NULL; |
94a78b79 VZ |
11681 | |
11682 | return rc; | |
11683 | } | |
11684 | ||
619c5cb6 VZ |
11685 | static void bnx2x_release_firmware(struct bnx2x *bp) |
11686 | { | |
11687 | kfree(bp->init_ops_offsets); | |
11688 | kfree(bp->init_ops); | |
11689 | kfree(bp->init_data); | |
11690 | release_firmware(bp->firmware); | |
eb2afd4a | 11691 | bp->firmware = NULL; |
619c5cb6 VZ |
11692 | } |
11693 | ||
11694 | ||
11695 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { | |
11696 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
11697 | .init_hw_cmn = bnx2x_init_hw_common, | |
11698 | .init_hw_port = bnx2x_init_hw_port, | |
11699 | .init_hw_func = bnx2x_init_hw_func, | |
11700 | ||
11701 | .reset_hw_cmn = bnx2x_reset_common, | |
11702 | .reset_hw_port = bnx2x_reset_port, | |
11703 | .reset_hw_func = bnx2x_reset_func, | |
11704 | ||
11705 | .gunzip_init = bnx2x_gunzip_init, | |
11706 | .gunzip_end = bnx2x_gunzip_end, | |
11707 | ||
11708 | .init_fw = bnx2x_init_firmware, | |
11709 | .release_fw = bnx2x_release_firmware, | |
11710 | }; | |
11711 | ||
11712 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
11713 | { | |
11714 | /* Prepare DMAE related driver resources */ | |
11715 | bnx2x_setup_dmae(bp); | |
11716 | ||
11717 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
11718 | bnx2x_sp(bp, func_rdata), | |
11719 | bnx2x_sp_mapping(bp, func_rdata), | |
a3348722 BW |
11720 | bnx2x_sp(bp, func_afex_rdata), |
11721 | bnx2x_sp_mapping(bp, func_afex_rdata), | |
619c5cb6 VZ |
11722 | &bnx2x_func_sp_drv); |
11723 | } | |
11724 | ||
11725 | /* must be called after sriov-enable */ | |
1191cb83 | 11726 | static int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 11727 | { |
37ae41a9 | 11728 | int cid_count = BNX2X_L2_MAX_CID(bp); |
94a78b79 | 11729 | |
523224a3 DK |
11730 | #ifdef BCM_CNIC |
11731 | cid_count += CNIC_CID_MAX; | |
11732 | #endif | |
11733 | return roundup(cid_count, QM_CID_ROUND); | |
11734 | } | |
f85582f8 | 11735 | |
619c5cb6 | 11736 | /** |
6383c0b3 | 11737 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
11738 | * |
11739 | * @dev: pci device | |
11740 | * | |
11741 | */ | |
1191cb83 | 11742 | static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) |
619c5cb6 VZ |
11743 | { |
11744 | int pos; | |
11745 | u16 control; | |
11746 | ||
11747 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); | |
6383c0b3 AE |
11748 | |
11749 | /* | |
11750 | * If MSI-X is not supported - return number of SBs needed to support | |
11751 | * one fast path queue: one FP queue + SB for CNIC | |
11752 | */ | |
619c5cb6 | 11753 | if (!pos) |
6383c0b3 | 11754 | return 1 + CNIC_PRESENT; |
619c5cb6 | 11755 | |
6383c0b3 AE |
11756 | /* |
11757 | * The value in the PCI configuration space is the index of the last | |
11758 | * entry, namely one less than the actual size of the table, which is | |
11759 | * exactly what we want to return from this function: number of all SBs | |
11760 | * without the default SB. | |
11761 | */ | |
619c5cb6 | 11762 | pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); |
6383c0b3 | 11763 | return control & PCI_MSIX_FLAGS_QSIZE; |
619c5cb6 VZ |
11764 | } |
11765 | ||
a2fbb9ea ET |
11766 | static int __devinit bnx2x_init_one(struct pci_dev *pdev, |
11767 | const struct pci_device_id *ent) | |
11768 | { | |
a2fbb9ea ET |
11769 | struct net_device *dev = NULL; |
11770 | struct bnx2x *bp; | |
37f9ce62 | 11771 | int pcie_width, pcie_speed; |
6383c0b3 | 11772 | int rc, max_non_def_sbs; |
65565884 | 11773 | int rx_count, tx_count, rss_count, doorbell_size; |
6383c0b3 AE |
11774 | /* |
11775 | * An estimated maximum supported CoS number according to the chip | |
11776 | * version. | |
11777 | * We will try to roughly estimate the maximum number of CoSes this chip | |
11778 | * may support in order to minimize the memory allocated for Tx | |
11779 | * netdev_queue's. This number will be accurately calculated during the | |
11780 | * initialization of bp->max_cos based on the chip versions AND chip | |
11781 | * revision in the bnx2x_init_bp(). | |
11782 | */ | |
11783 | u8 max_cos_est = 0; | |
523224a3 | 11784 | |
f2e0899f DK |
11785 | switch (ent->driver_data) { |
11786 | case BCM57710: | |
11787 | case BCM57711: | |
11788 | case BCM57711E: | |
6383c0b3 AE |
11789 | max_cos_est = BNX2X_MULTI_TX_COS_E1X; |
11790 | break; | |
11791 | ||
f2e0899f | 11792 | case BCM57712: |
619c5cb6 | 11793 | case BCM57712_MF: |
6383c0b3 AE |
11794 | max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; |
11795 | break; | |
11796 | ||
619c5cb6 VZ |
11797 | case BCM57800: |
11798 | case BCM57800_MF: | |
11799 | case BCM57810: | |
11800 | case BCM57810_MF: | |
11801 | case BCM57840: | |
11802 | case BCM57840_MF: | |
7e8e02df BW |
11803 | case BCM57811: |
11804 | case BCM57811_MF: | |
6383c0b3 | 11805 | max_cos_est = BNX2X_MULTI_TX_COS_E3B0; |
f2e0899f | 11806 | break; |
a2fbb9ea | 11807 | |
f2e0899f DK |
11808 | default: |
11809 | pr_err("Unknown board_type (%ld), aborting\n", | |
11810 | ent->driver_data); | |
870634b0 | 11811 | return -ENODEV; |
f2e0899f DK |
11812 | } |
11813 | ||
6383c0b3 AE |
11814 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); |
11815 | ||
6383c0b3 AE |
11816 | WARN_ON(!max_non_def_sbs); |
11817 | ||
11818 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
11819 | rss_count = max_non_def_sbs - CNIC_PRESENT; | |
11820 | ||
11821 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
11822 | rx_count = rss_count + FCOE_PRESENT; | |
11823 | ||
11824 | /* | |
11825 | * Maximum number of netdev Tx queues: | |
37ae41a9 | 11826 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 |
6383c0b3 | 11827 | */ |
37ae41a9 | 11828 | tx_count = rss_count * max_cos_est + FCOE_PRESENT; |
f85582f8 | 11829 | |
a2fbb9ea | 11830 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 11831 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
41de8d4c | 11832 | if (!dev) |
a2fbb9ea ET |
11833 | return -ENOMEM; |
11834 | ||
a2fbb9ea | 11835 | bp = netdev_priv(dev); |
a2fbb9ea | 11836 | |
6383c0b3 AE |
11837 | bp->igu_sb_cnt = max_non_def_sbs; |
11838 | bp->msg_enable = debug; | |
11839 | pci_set_drvdata(pdev, dev); | |
523224a3 | 11840 | |
619c5cb6 | 11841 | rc = bnx2x_init_dev(pdev, dev, ent->driver_data); |
a2fbb9ea ET |
11842 | if (rc < 0) { |
11843 | free_netdev(dev); | |
11844 | return rc; | |
11845 | } | |
11846 | ||
51c1a580 | 11847 | BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs); |
619c5cb6 | 11848 | |
60aa0509 MS |
11849 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
11850 | tx_count, rx_count); | |
11851 | ||
34f80b04 | 11852 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
11853 | if (rc) |
11854 | goto init_one_exit; | |
11855 | ||
6383c0b3 AE |
11856 | /* |
11857 | * Map doorbels here as we need the real value of bp->max_cos which | |
11858 | * is initialized in bnx2x_init_bp(). | |
11859 | */ | |
37ae41a9 MS |
11860 | doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); |
11861 | if (doorbell_size > pci_resource_len(pdev, 2)) { | |
11862 | dev_err(&bp->pdev->dev, | |
11863 | "Cannot map doorbells, bar size too small, aborting\n"); | |
11864 | rc = -ENOMEM; | |
11865 | goto init_one_exit; | |
11866 | } | |
6383c0b3 | 11867 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), |
37ae41a9 | 11868 | doorbell_size); |
6383c0b3 AE |
11869 | if (!bp->doorbells) { |
11870 | dev_err(&bp->pdev->dev, | |
11871 | "Cannot map doorbell space, aborting\n"); | |
11872 | rc = -ENOMEM; | |
11873 | goto init_one_exit; | |
11874 | } | |
11875 | ||
523224a3 | 11876 | /* calc qm_cid_count */ |
6383c0b3 | 11877 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
523224a3 | 11878 | |
ec6ba945 | 11879 | #ifdef BCM_CNIC |
62ac0dc9 DK |
11880 | /* disable FCOE L2 queue for E1x */ |
11881 | if (CHIP_IS_E1x(bp)) | |
ec6ba945 VZ |
11882 | bp->flags |= NO_FCOE_FLAG; |
11883 | ||
11884 | #endif | |
11885 | ||
25985edc | 11886 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
d6214d7a DK |
11887 | * needed, set bp->num_queues appropriately. |
11888 | */ | |
11889 | bnx2x_set_int_mode(bp); | |
11890 | ||
11891 | /* Add all NAPI objects */ | |
11892 | bnx2x_add_all_napi(bp); | |
11893 | ||
b340007f VZ |
11894 | rc = register_netdev(dev); |
11895 | if (rc) { | |
11896 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
11897 | goto init_one_exit; | |
11898 | } | |
11899 | ||
ec6ba945 VZ |
11900 | #ifdef BCM_CNIC |
11901 | if (!NO_FCOE(bp)) { | |
11902 | /* Add storage MAC address */ | |
11903 | rtnl_lock(); | |
11904 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
11905 | rtnl_unlock(); | |
11906 | } | |
11907 | #endif | |
11908 | ||
37f9ce62 | 11909 | bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); |
d6214d7a | 11910 | |
51c1a580 MS |
11911 | BNX2X_DEV_INFO( |
11912 | "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", | |
94f05b0f JP |
11913 | board_info[ent->driver_data].name, |
11914 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
11915 | pcie_width, | |
11916 | ((!CHIP_IS_E2(bp) && pcie_speed == 2) || | |
11917 | (CHIP_IS_E2(bp) && pcie_speed == 1)) ? | |
11918 | "5GHz (Gen2)" : "2.5GHz", | |
11919 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
c016201c | 11920 | |
a2fbb9ea | 11921 | return 0; |
34f80b04 EG |
11922 | |
11923 | init_one_exit: | |
11924 | if (bp->regview) | |
11925 | iounmap(bp->regview); | |
11926 | ||
11927 | if (bp->doorbells) | |
11928 | iounmap(bp->doorbells); | |
11929 | ||
11930 | free_netdev(dev); | |
11931 | ||
11932 | if (atomic_read(&pdev->enable_cnt) == 1) | |
11933 | pci_release_regions(pdev); | |
11934 | ||
11935 | pci_disable_device(pdev); | |
11936 | pci_set_drvdata(pdev, NULL); | |
11937 | ||
11938 | return rc; | |
a2fbb9ea ET |
11939 | } |
11940 | ||
11941 | static void __devexit bnx2x_remove_one(struct pci_dev *pdev) | |
11942 | { | |
11943 | struct net_device *dev = pci_get_drvdata(pdev); | |
228241eb ET |
11944 | struct bnx2x *bp; |
11945 | ||
11946 | if (!dev) { | |
cdaa7cb8 | 11947 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); |
228241eb ET |
11948 | return; |
11949 | } | |
228241eb | 11950 | bp = netdev_priv(dev); |
a2fbb9ea | 11951 | |
ec6ba945 VZ |
11952 | #ifdef BCM_CNIC |
11953 | /* Delete storage MAC address */ | |
11954 | if (!NO_FCOE(bp)) { | |
11955 | rtnl_lock(); | |
11956 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
11957 | rtnl_unlock(); | |
11958 | } | |
11959 | #endif | |
11960 | ||
98507672 SR |
11961 | #ifdef BCM_DCBNL |
11962 | /* Delete app tlvs from dcbnl */ | |
11963 | bnx2x_dcbnl_update_applist(bp, true); | |
11964 | #endif | |
11965 | ||
a2fbb9ea ET |
11966 | unregister_netdev(dev); |
11967 | ||
d6214d7a DK |
11968 | /* Delete all NAPI objects */ |
11969 | bnx2x_del_all_napi(bp); | |
11970 | ||
084d6cbb VZ |
11971 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
11972 | bnx2x_set_power_state(bp, PCI_D0); | |
11973 | ||
d6214d7a DK |
11974 | /* Disable MSI/MSI-X */ |
11975 | bnx2x_disable_msi(bp); | |
f85582f8 | 11976 | |
084d6cbb VZ |
11977 | /* Power off */ |
11978 | bnx2x_set_power_state(bp, PCI_D3hot); | |
11979 | ||
72fd0718 | 11980 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 11981 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
72fd0718 | 11982 | |
a2fbb9ea ET |
11983 | if (bp->regview) |
11984 | iounmap(bp->regview); | |
11985 | ||
11986 | if (bp->doorbells) | |
11987 | iounmap(bp->doorbells); | |
11988 | ||
eb2afd4a DK |
11989 | bnx2x_release_firmware(bp); |
11990 | ||
523224a3 DK |
11991 | bnx2x_free_mem_bp(bp); |
11992 | ||
a2fbb9ea | 11993 | free_netdev(dev); |
34f80b04 EG |
11994 | |
11995 | if (atomic_read(&pdev->enable_cnt) == 1) | |
11996 | pci_release_regions(pdev); | |
11997 | ||
a2fbb9ea ET |
11998 | pci_disable_device(pdev); |
11999 | pci_set_drvdata(pdev, NULL); | |
12000 | } | |
12001 | ||
f8ef6e44 YG |
12002 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
12003 | { | |
12004 | int i; | |
12005 | ||
12006 | bp->state = BNX2X_STATE_ERROR; | |
12007 | ||
12008 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
12009 | ||
619c5cb6 VZ |
12010 | #ifdef BCM_CNIC |
12011 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
12012 | #endif | |
12013 | /* Stop Tx */ | |
12014 | bnx2x_tx_disable(bp); | |
12015 | ||
f8ef6e44 YG |
12016 | bnx2x_netif_stop(bp, 0); |
12017 | ||
12018 | del_timer_sync(&bp->timer); | |
619c5cb6 VZ |
12019 | |
12020 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
f8ef6e44 YG |
12021 | |
12022 | /* Release IRQs */ | |
d6214d7a | 12023 | bnx2x_free_irq(bp); |
f8ef6e44 | 12024 | |
f8ef6e44 YG |
12025 | /* Free SKBs, SGEs, TPA pool and driver internals */ |
12026 | bnx2x_free_skbs(bp); | |
523224a3 | 12027 | |
ec6ba945 | 12028 | for_each_rx_queue(bp, i) |
f8ef6e44 | 12029 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); |
d6214d7a | 12030 | |
f8ef6e44 YG |
12031 | bnx2x_free_mem(bp); |
12032 | ||
12033 | bp->state = BNX2X_STATE_CLOSED; | |
12034 | ||
619c5cb6 VZ |
12035 | netif_carrier_off(bp->dev); |
12036 | ||
f8ef6e44 YG |
12037 | return 0; |
12038 | } | |
12039 | ||
12040 | static void bnx2x_eeh_recover(struct bnx2x *bp) | |
12041 | { | |
12042 | u32 val; | |
12043 | ||
12044 | mutex_init(&bp->port.phy_mutex); | |
12045 | ||
f8ef6e44 YG |
12046 | |
12047 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
12048 | if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
12049 | != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
12050 | BNX2X_ERR("BAD MCP validity signature\n"); | |
f8ef6e44 YG |
12051 | } |
12052 | ||
493adb1f WX |
12053 | /** |
12054 | * bnx2x_io_error_detected - called when PCI error is detected | |
12055 | * @pdev: Pointer to PCI device | |
12056 | * @state: The current pci connection state | |
12057 | * | |
12058 | * This function is called after a PCI bus error affecting | |
12059 | * this device has been detected. | |
12060 | */ | |
12061 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
12062 | pci_channel_state_t state) | |
12063 | { | |
12064 | struct net_device *dev = pci_get_drvdata(pdev); | |
12065 | struct bnx2x *bp = netdev_priv(dev); | |
12066 | ||
12067 | rtnl_lock(); | |
12068 | ||
12069 | netif_device_detach(dev); | |
12070 | ||
07ce50e4 DN |
12071 | if (state == pci_channel_io_perm_failure) { |
12072 | rtnl_unlock(); | |
12073 | return PCI_ERS_RESULT_DISCONNECT; | |
12074 | } | |
12075 | ||
493adb1f | 12076 | if (netif_running(dev)) |
f8ef6e44 | 12077 | bnx2x_eeh_nic_unload(bp); |
493adb1f WX |
12078 | |
12079 | pci_disable_device(pdev); | |
12080 | ||
12081 | rtnl_unlock(); | |
12082 | ||
12083 | /* Request a slot reset */ | |
12084 | return PCI_ERS_RESULT_NEED_RESET; | |
12085 | } | |
12086 | ||
12087 | /** | |
12088 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
12089 | * @pdev: Pointer to PCI device | |
12090 | * | |
12091 | * Restart the card from scratch, as if from a cold-boot. | |
12092 | */ | |
12093 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
12094 | { | |
12095 | struct net_device *dev = pci_get_drvdata(pdev); | |
12096 | struct bnx2x *bp = netdev_priv(dev); | |
12097 | ||
12098 | rtnl_lock(); | |
12099 | ||
12100 | if (pci_enable_device(pdev)) { | |
12101 | dev_err(&pdev->dev, | |
12102 | "Cannot re-enable PCI device after reset\n"); | |
12103 | rtnl_unlock(); | |
12104 | return PCI_ERS_RESULT_DISCONNECT; | |
12105 | } | |
12106 | ||
12107 | pci_set_master(pdev); | |
12108 | pci_restore_state(pdev); | |
12109 | ||
12110 | if (netif_running(dev)) | |
12111 | bnx2x_set_power_state(bp, PCI_D0); | |
12112 | ||
12113 | rtnl_unlock(); | |
12114 | ||
12115 | return PCI_ERS_RESULT_RECOVERED; | |
12116 | } | |
12117 | ||
12118 | /** | |
12119 | * bnx2x_io_resume - called when traffic can start flowing again | |
12120 | * @pdev: Pointer to PCI device | |
12121 | * | |
12122 | * This callback is called when the error recovery driver tells us that | |
12123 | * its OK to resume normal operation. | |
12124 | */ | |
12125 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
12126 | { | |
12127 | struct net_device *dev = pci_get_drvdata(pdev); | |
12128 | struct bnx2x *bp = netdev_priv(dev); | |
12129 | ||
72fd0718 | 12130 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 12131 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
72fd0718 VZ |
12132 | return; |
12133 | } | |
12134 | ||
493adb1f WX |
12135 | rtnl_lock(); |
12136 | ||
f8ef6e44 YG |
12137 | bnx2x_eeh_recover(bp); |
12138 | ||
493adb1f | 12139 | if (netif_running(dev)) |
f8ef6e44 | 12140 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
12141 | |
12142 | netif_device_attach(dev); | |
12143 | ||
12144 | rtnl_unlock(); | |
12145 | } | |
12146 | ||
12147 | static struct pci_error_handlers bnx2x_err_handler = { | |
12148 | .error_detected = bnx2x_io_error_detected, | |
356e2385 EG |
12149 | .slot_reset = bnx2x_io_slot_reset, |
12150 | .resume = bnx2x_io_resume, | |
493adb1f WX |
12151 | }; |
12152 | ||
a2fbb9ea | 12153 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
12154 | .name = DRV_MODULE_NAME, |
12155 | .id_table = bnx2x_pci_tbl, | |
12156 | .probe = bnx2x_init_one, | |
12157 | .remove = __devexit_p(bnx2x_remove_one), | |
12158 | .suspend = bnx2x_suspend, | |
12159 | .resume = bnx2x_resume, | |
12160 | .err_handler = &bnx2x_err_handler, | |
a2fbb9ea ET |
12161 | }; |
12162 | ||
12163 | static int __init bnx2x_init(void) | |
12164 | { | |
dd21ca6d SG |
12165 | int ret; |
12166 | ||
7995c64e | 12167 | pr_info("%s", version); |
938cf541 | 12168 | |
1cf167f2 EG |
12169 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
12170 | if (bnx2x_wq == NULL) { | |
7995c64e | 12171 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
12172 | return -ENOMEM; |
12173 | } | |
12174 | ||
dd21ca6d SG |
12175 | ret = pci_register_driver(&bnx2x_pci_driver); |
12176 | if (ret) { | |
7995c64e | 12177 | pr_err("Cannot register driver\n"); |
dd21ca6d SG |
12178 | destroy_workqueue(bnx2x_wq); |
12179 | } | |
12180 | return ret; | |
a2fbb9ea ET |
12181 | } |
12182 | ||
12183 | static void __exit bnx2x_cleanup(void) | |
12184 | { | |
452427b0 | 12185 | struct list_head *pos, *q; |
a2fbb9ea | 12186 | pci_unregister_driver(&bnx2x_pci_driver); |
1cf167f2 EG |
12187 | |
12188 | destroy_workqueue(bnx2x_wq); | |
452427b0 YM |
12189 | |
12190 | /* Free globablly allocated resources */ | |
12191 | list_for_each_safe(pos, q, &bnx2x_prev_list) { | |
12192 | struct bnx2x_prev_path_list *tmp = | |
12193 | list_entry(pos, struct bnx2x_prev_path_list, list); | |
12194 | list_del(pos); | |
12195 | kfree(tmp); | |
12196 | } | |
a2fbb9ea ET |
12197 | } |
12198 | ||
3deb8167 YR |
12199 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
12200 | { | |
12201 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
12202 | } | |
12203 | ||
a2fbb9ea ET |
12204 | module_init(bnx2x_init); |
12205 | module_exit(bnx2x_cleanup); | |
12206 | ||
993ac7b5 | 12207 | #ifdef BCM_CNIC |
619c5cb6 VZ |
12208 | /** |
12209 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
12210 | * | |
12211 | * @bp: driver handle | |
12212 | * @set: set or clear the CAM entry | |
12213 | * | |
12214 | * This function will wait until the ramdord completion returns. | |
12215 | * Return 0 if success, -ENODEV if ramrod doesn't return. | |
12216 | */ | |
1191cb83 | 12217 | static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) |
619c5cb6 VZ |
12218 | { |
12219 | unsigned long ramrod_flags = 0; | |
12220 | ||
12221 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
12222 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
12223 | &bp->iscsi_l2_mac_obj, true, | |
12224 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
12225 | } | |
993ac7b5 MC |
12226 | |
12227 | /* count denotes the number of new completions we have seen */ | |
12228 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
12229 | { | |
12230 | struct eth_spe *spe; | |
a052997e | 12231 | int cxt_index, cxt_offset; |
993ac7b5 MC |
12232 | |
12233 | #ifdef BNX2X_STOP_ON_ERROR | |
12234 | if (unlikely(bp->panic)) | |
12235 | return; | |
12236 | #endif | |
12237 | ||
12238 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 12239 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
12240 | bp->cnic_spq_pending -= count; |
12241 | ||
993ac7b5 | 12242 | |
c2bff63f DK |
12243 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
12244 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
12245 | & SPE_HDR_CONN_TYPE) >> | |
12246 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
12247 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
12248 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
12249 | |
12250 | /* Set validation for iSCSI L2 client before sending SETUP | |
12251 | * ramrod | |
12252 | */ | |
12253 | if (type == ETH_CONNECTION_TYPE) { | |
a052997e | 12254 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { |
37ae41a9 | 12255 | cxt_index = BNX2X_ISCSI_ETH_CID(bp) / |
a052997e | 12256 | ILT_PAGE_CIDS; |
37ae41a9 | 12257 | cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - |
a052997e MS |
12258 | (cxt_index * ILT_PAGE_CIDS); |
12259 | bnx2x_set_ctx_validation(bp, | |
12260 | &bp->context[cxt_index]. | |
12261 | vcxt[cxt_offset].eth, | |
37ae41a9 | 12262 | BNX2X_ISCSI_ETH_CID(bp)); |
a052997e | 12263 | } |
c2bff63f DK |
12264 | } |
12265 | ||
619c5cb6 VZ |
12266 | /* |
12267 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
12268 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
12269 | * COMMON ramrods is not more than the EQ and SPQ can |
12270 | * accommodate. | |
c2bff63f | 12271 | */ |
6e30dd4e VZ |
12272 | if (type == ETH_CONNECTION_TYPE) { |
12273 | if (!atomic_read(&bp->cq_spq_left)) | |
12274 | break; | |
12275 | else | |
12276 | atomic_dec(&bp->cq_spq_left); | |
12277 | } else if (type == NONE_CONNECTION_TYPE) { | |
12278 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
12279 | break; |
12280 | else | |
6e30dd4e | 12281 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
12282 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
12283 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
12284 | if (bp->cnic_spq_pending >= |
12285 | bp->cnic_eth_dev.max_kwqe_pending) | |
12286 | break; | |
12287 | else | |
12288 | bp->cnic_spq_pending++; | |
12289 | } else { | |
12290 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
12291 | bnx2x_panic(); | |
993ac7b5 | 12292 | break; |
c2bff63f | 12293 | } |
993ac7b5 MC |
12294 | |
12295 | spe = bnx2x_sp_get_next(bp); | |
12296 | *spe = *bp->cnic_kwq_cons; | |
12297 | ||
51c1a580 | 12298 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
993ac7b5 MC |
12299 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
12300 | ||
12301 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
12302 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
12303 | else | |
12304 | bp->cnic_kwq_cons++; | |
12305 | } | |
12306 | bnx2x_sp_prod_update(bp); | |
12307 | spin_unlock_bh(&bp->spq_lock); | |
12308 | } | |
12309 | ||
12310 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
12311 | struct kwqe_16 *kwqes[], u32 count) | |
12312 | { | |
12313 | struct bnx2x *bp = netdev_priv(dev); | |
12314 | int i; | |
12315 | ||
12316 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 MS |
12317 | if (unlikely(bp->panic)) { |
12318 | BNX2X_ERR("Can't post to SP queue while panic\n"); | |
993ac7b5 | 12319 | return -EIO; |
51c1a580 | 12320 | } |
993ac7b5 MC |
12321 | #endif |
12322 | ||
95c6c616 AE |
12323 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
12324 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
51c1a580 | 12325 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
95c6c616 AE |
12326 | return -EAGAIN; |
12327 | } | |
12328 | ||
993ac7b5 MC |
12329 | spin_lock_bh(&bp->spq_lock); |
12330 | ||
12331 | for (i = 0; i < count; i++) { | |
12332 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
12333 | ||
12334 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
12335 | break; | |
12336 | ||
12337 | *bp->cnic_kwq_prod = *spe; | |
12338 | ||
12339 | bp->cnic_kwq_pending++; | |
12340 | ||
51c1a580 | 12341 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
993ac7b5 | 12342 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
523224a3 DK |
12343 | spe->data.update_data_addr.hi, |
12344 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
12345 | bp->cnic_kwq_pending); |
12346 | ||
12347 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
12348 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
12349 | else | |
12350 | bp->cnic_kwq_prod++; | |
12351 | } | |
12352 | ||
12353 | spin_unlock_bh(&bp->spq_lock); | |
12354 | ||
12355 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
12356 | bnx2x_cnic_sp_post(bp, 0); | |
12357 | ||
12358 | return i; | |
12359 | } | |
12360 | ||
12361 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
12362 | { | |
12363 | struct cnic_ops *c_ops; | |
12364 | int rc = 0; | |
12365 | ||
12366 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
12367 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
12368 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
12369 | if (c_ops) |
12370 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
12371 | mutex_unlock(&bp->cnic_mutex); | |
12372 | ||
12373 | return rc; | |
12374 | } | |
12375 | ||
12376 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
12377 | { | |
12378 | struct cnic_ops *c_ops; | |
12379 | int rc = 0; | |
12380 | ||
12381 | rcu_read_lock(); | |
12382 | c_ops = rcu_dereference(bp->cnic_ops); | |
12383 | if (c_ops) | |
12384 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
12385 | rcu_read_unlock(); | |
12386 | ||
12387 | return rc; | |
12388 | } | |
12389 | ||
12390 | /* | |
12391 | * for commands that have no data | |
12392 | */ | |
9f6c9258 | 12393 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
12394 | { |
12395 | struct cnic_ctl_info ctl = {0}; | |
12396 | ||
12397 | ctl.cmd = cmd; | |
12398 | ||
12399 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
12400 | } | |
12401 | ||
619c5cb6 | 12402 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 12403 | { |
619c5cb6 | 12404 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
12405 | |
12406 | /* first we tell CNIC and only then we count this as a completion */ | |
12407 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
12408 | ctl.data.comp.cid = cid; | |
619c5cb6 | 12409 | ctl.data.comp.error = err; |
993ac7b5 MC |
12410 | |
12411 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 12412 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
12413 | } |
12414 | ||
619c5cb6 VZ |
12415 | |
12416 | /* Called with netif_addr_lock_bh() taken. | |
12417 | * Sets an rx_mode config for an iSCSI ETH client. | |
12418 | * Doesn't block. | |
12419 | * Completion should be checked outside. | |
12420 | */ | |
12421 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
12422 | { | |
12423 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
12424 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
12425 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
12426 | ||
12427 | if (start) { | |
12428 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
12429 | * because it's the only way for UIO Queue to accept | |
12430 | * multicasts (in non-promiscuous mode only one Queue per | |
12431 | * function will receive multicast packets (leading in our | |
12432 | * case). | |
12433 | */ | |
12434 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
12435 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
12436 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
12437 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
12438 | ||
12439 | /* Clear STOP_PENDING bit if START is requested */ | |
12440 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
12441 | ||
12442 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
12443 | } else | |
12444 | /* Clear START_PENDING bit if STOP is requested */ | |
12445 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
12446 | ||
12447 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
12448 | set_bit(sched_state, &bp->sp_state); | |
12449 | else { | |
12450 | __set_bit(RAMROD_RX, &ramrod_flags); | |
12451 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
12452 | ramrod_flags); | |
12453 | } | |
12454 | } | |
12455 | ||
12456 | ||
993ac7b5 MC |
12457 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
12458 | { | |
12459 | struct bnx2x *bp = netdev_priv(dev); | |
12460 | int rc = 0; | |
12461 | ||
12462 | switch (ctl->cmd) { | |
12463 | case DRV_CTL_CTXTBL_WR_CMD: { | |
12464 | u32 index = ctl->data.io.offset; | |
12465 | dma_addr_t addr = ctl->data.io.dma_addr; | |
12466 | ||
12467 | bnx2x_ilt_wr(bp, index, addr); | |
12468 | break; | |
12469 | } | |
12470 | ||
c2bff63f DK |
12471 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
12472 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
12473 | |
12474 | bnx2x_cnic_sp_post(bp, count); | |
12475 | break; | |
12476 | } | |
12477 | ||
12478 | /* rtnl_lock is held. */ | |
12479 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
12480 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
12481 | unsigned long sp_bits = 0; | |
12482 | ||
12483 | /* Configure the iSCSI classification object */ | |
12484 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
12485 | cp->iscsi_l2_client_id, | |
12486 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
12487 | bnx2x_sp(bp, mac_rdata), | |
12488 | bnx2x_sp_mapping(bp, mac_rdata), | |
12489 | BNX2X_FILTER_MAC_PENDING, | |
12490 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
12491 | &bp->macs_pool); | |
ec6ba945 | 12492 | |
523224a3 | 12493 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
12494 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
12495 | if (rc) | |
12496 | break; | |
523224a3 DK |
12497 | |
12498 | mmiowb(); | |
12499 | barrier(); | |
12500 | ||
619c5cb6 VZ |
12501 | /* Start accepting on iSCSI L2 ring */ |
12502 | ||
12503 | netif_addr_lock_bh(dev); | |
12504 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
12505 | netif_addr_unlock_bh(dev); | |
12506 | ||
12507 | /* bits to wait on */ | |
12508 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
12509 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
12510 | ||
12511 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
12512 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 12513 | |
993ac7b5 MC |
12514 | break; |
12515 | } | |
12516 | ||
12517 | /* rtnl_lock is held. */ | |
12518 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 12519 | unsigned long sp_bits = 0; |
993ac7b5 | 12520 | |
523224a3 | 12521 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
12522 | netif_addr_lock_bh(dev); |
12523 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
12524 | netif_addr_unlock_bh(dev); | |
12525 | ||
12526 | /* bits to wait on */ | |
12527 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
12528 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
12529 | ||
12530 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
12531 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
12532 | |
12533 | mmiowb(); | |
12534 | barrier(); | |
12535 | ||
12536 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
12537 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
12538 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
12539 | break; |
12540 | } | |
c2bff63f DK |
12541 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
12542 | int count = ctl->data.credit.credit_count; | |
12543 | ||
12544 | smp_mb__before_atomic_inc(); | |
6e30dd4e | 12545 | atomic_add(count, &bp->cq_spq_left); |
c2bff63f DK |
12546 | smp_mb__after_atomic_inc(); |
12547 | break; | |
12548 | } | |
1d187b34 BW |
12549 | case DRV_CTL_ULP_REGISTER_CMD: { |
12550 | int ulp_type = ctl->data.ulp_type; | |
12551 | ||
12552 | if (CHIP_IS_E3(bp)) { | |
12553 | int idx = BP_FW_MB_IDX(bp); | |
12554 | u32 cap; | |
12555 | ||
12556 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
12557 | if (ulp_type == CNIC_ULP_ISCSI) | |
12558 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
12559 | else if (ulp_type == CNIC_ULP_FCOE) | |
12560 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
12561 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
12562 | } | |
12563 | break; | |
12564 | } | |
12565 | case DRV_CTL_ULP_UNREGISTER_CMD: { | |
12566 | int ulp_type = ctl->data.ulp_type; | |
12567 | ||
12568 | if (CHIP_IS_E3(bp)) { | |
12569 | int idx = BP_FW_MB_IDX(bp); | |
12570 | u32 cap; | |
12571 | ||
12572 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
12573 | if (ulp_type == CNIC_ULP_ISCSI) | |
12574 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
12575 | else if (ulp_type == CNIC_ULP_FCOE) | |
12576 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
12577 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
12578 | } | |
12579 | break; | |
12580 | } | |
993ac7b5 MC |
12581 | |
12582 | default: | |
12583 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
12584 | rc = -EINVAL; | |
12585 | } | |
12586 | ||
12587 | return rc; | |
12588 | } | |
12589 | ||
9f6c9258 | 12590 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
12591 | { |
12592 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12593 | ||
12594 | if (bp->flags & USING_MSIX_FLAG) { | |
12595 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
12596 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
12597 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
12598 | } else { | |
12599 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
12600 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
12601 | } | |
619c5cb6 | 12602 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
12603 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
12604 | else | |
12605 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
12606 | ||
619c5cb6 VZ |
12607 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
12608 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
12609 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
12610 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 12611 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
12612 | |
12613 | cp->num_irq = 2; | |
12614 | } | |
12615 | ||
37ae41a9 MS |
12616 | void bnx2x_setup_cnic_info(struct bnx2x *bp) |
12617 | { | |
12618 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12619 | ||
12620 | ||
12621 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + | |
12622 | bnx2x_cid_ilt_lines(bp); | |
12623 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; | |
12624 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); | |
12625 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); | |
12626 | ||
12627 | if (NO_ISCSI_OOO(bp)) | |
12628 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
12629 | } | |
12630 | ||
993ac7b5 MC |
12631 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, |
12632 | void *data) | |
12633 | { | |
12634 | struct bnx2x *bp = netdev_priv(dev); | |
12635 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12636 | ||
51c1a580 MS |
12637 | if (ops == NULL) { |
12638 | BNX2X_ERR("NULL ops received\n"); | |
993ac7b5 | 12639 | return -EINVAL; |
51c1a580 | 12640 | } |
993ac7b5 | 12641 | |
993ac7b5 MC |
12642 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
12643 | if (!bp->cnic_kwq) | |
12644 | return -ENOMEM; | |
12645 | ||
12646 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
12647 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
12648 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
12649 | ||
12650 | bp->cnic_spq_pending = 0; | |
12651 | bp->cnic_kwq_pending = 0; | |
12652 | ||
12653 | bp->cnic_data = data; | |
12654 | ||
12655 | cp->num_irq = 0; | |
619c5cb6 | 12656 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 12657 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 12658 | |
993ac7b5 | 12659 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 12660 | |
993ac7b5 MC |
12661 | rcu_assign_pointer(bp->cnic_ops, ops); |
12662 | ||
12663 | return 0; | |
12664 | } | |
12665 | ||
12666 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
12667 | { | |
12668 | struct bnx2x *bp = netdev_priv(dev); | |
12669 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12670 | ||
12671 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 | 12672 | cp->drv_state = 0; |
2cfa5a04 | 12673 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
993ac7b5 MC |
12674 | mutex_unlock(&bp->cnic_mutex); |
12675 | synchronize_rcu(); | |
12676 | kfree(bp->cnic_kwq); | |
12677 | bp->cnic_kwq = NULL; | |
12678 | ||
12679 | return 0; | |
12680 | } | |
12681 | ||
12682 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) | |
12683 | { | |
12684 | struct bnx2x *bp = netdev_priv(dev); | |
12685 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
12686 | ||
2ba45142 VZ |
12687 | /* If both iSCSI and FCoE are disabled - return NULL in |
12688 | * order to indicate CNIC that it should not try to work | |
12689 | * with this device. | |
12690 | */ | |
12691 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
12692 | return NULL; | |
12693 | ||
993ac7b5 MC |
12694 | cp->drv_owner = THIS_MODULE; |
12695 | cp->chip_id = CHIP_ID(bp); | |
12696 | cp->pdev = bp->pdev; | |
12697 | cp->io_base = bp->regview; | |
12698 | cp->io_base2 = bp->doorbells; | |
12699 | cp->max_kwqe_pending = 8; | |
523224a3 | 12700 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
12701 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
12702 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 12703 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 12704 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
12705 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
12706 | cp->drv_ctl = bnx2x_drv_ctl; | |
12707 | cp->drv_register_cnic = bnx2x_register_cnic; | |
12708 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
37ae41a9 | 12709 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); |
619c5cb6 VZ |
12710 | cp->iscsi_l2_client_id = |
12711 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
37ae41a9 | 12712 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); |
c2bff63f | 12713 | |
2ba45142 VZ |
12714 | if (NO_ISCSI_OOO(bp)) |
12715 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
12716 | ||
12717 | if (NO_ISCSI(bp)) | |
12718 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
12719 | ||
12720 | if (NO_FCOE(bp)) | |
12721 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
12722 | ||
51c1a580 MS |
12723 | BNX2X_DEV_INFO( |
12724 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", | |
c2bff63f DK |
12725 | cp->ctx_blk_size, |
12726 | cp->ctx_tbl_offset, | |
12727 | cp->ctx_tbl_len, | |
12728 | cp->starting_cid); | |
993ac7b5 MC |
12729 | return cp; |
12730 | } | |
12731 | EXPORT_SYMBOL(bnx2x_cnic_probe); | |
12732 | ||
12733 | #endif /* BCM_CNIC */ | |
94a78b79 | 12734 |