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Commit | Line | Data |
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34f80b04 | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
a2fbb9ea | 2 | * |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 14 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
15 | * |
16 | */ | |
17 | ||
f1deab50 JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
a2fbb9ea ET |
20 | #include <linux/module.h> |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/device.h> /* for dev_info() */ | |
24 | #include <linux/timer.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/slab.h> | |
a2fbb9ea ET |
28 | #include <linux/interrupt.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/bitops.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/byteorder.h> | |
39 | #include <linux/time.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/mii.h> | |
0c6671b0 | 42 | #include <linux/if_vlan.h> |
a2fbb9ea | 43 | #include <net/ip.h> |
619c5cb6 | 44 | #include <net/ipv6.h> |
a2fbb9ea ET |
45 | #include <net/tcp.h> |
46 | #include <net/checksum.h> | |
34f80b04 | 47 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
48 | #include <linux/workqueue.h> |
49 | #include <linux/crc32.h> | |
34f80b04 | 50 | #include <linux/crc32c.h> |
a2fbb9ea ET |
51 | #include <linux/prefetch.h> |
52 | #include <linux/zlib.h> | |
a2fbb9ea | 53 | #include <linux/io.h> |
452427b0 | 54 | #include <linux/semaphore.h> |
45229b42 | 55 | #include <linux/stringify.h> |
7ab24bfd | 56 | #include <linux/vmalloc.h> |
a2fbb9ea | 57 | |
a2fbb9ea ET |
58 | #include "bnx2x.h" |
59 | #include "bnx2x_init.h" | |
94a78b79 | 60 | #include "bnx2x_init_ops.h" |
9f6c9258 | 61 | #include "bnx2x_cmn.h" |
1ab4434c | 62 | #include "bnx2x_vfpf.h" |
e4901dde | 63 | #include "bnx2x_dcb.h" |
042181f5 | 64 | #include "bnx2x_sp.h" |
a2fbb9ea | 65 | |
94a78b79 VZ |
66 | #include <linux/firmware.h> |
67 | #include "bnx2x_fw_file_hdr.h" | |
68 | /* FW files */ | |
45229b42 BH |
69 | #define FW_FILE_VERSION \ |
70 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
71 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
72 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
73 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
74 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
75 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 76 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 77 | |
34f80b04 EG |
78 | /* Time in jiffies before concluding the transmitter is hung */ |
79 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 80 | |
0329aba1 | 81 | static char version[] = |
619c5cb6 | 82 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
83 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
84 | ||
24e3fcef | 85 | MODULE_AUTHOR("Eliezer Tamir"); |
f2e0899f | 86 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
619c5cb6 VZ |
87 | "BCM57710/57711/57711E/" |
88 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
89 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
90 | MODULE_LICENSE("GPL"); |
91 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
92 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
93 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 94 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 95 | |
d6214d7a | 96 | int num_queues; |
54b9ddaa | 97 | module_param(num_queues, int, 0); |
96305234 DK |
98 | MODULE_PARM_DESC(num_queues, |
99 | " Set number of queues (default is as a number of CPUs)"); | |
555f6c78 | 100 | |
19680c48 | 101 | static int disable_tpa; |
19680c48 | 102 | module_param(disable_tpa, int, 0); |
9898f86d | 103 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 104 | |
0e8d2ec5 | 105 | int int_mode; |
8badd27a | 106 | module_param(int_mode, int, 0); |
619c5cb6 | 107 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 108 | "(1 INT#x; 2 MSI)"); |
8badd27a | 109 | |
a18f5128 EG |
110 | static int dropless_fc; |
111 | module_param(dropless_fc, int, 0); | |
112 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); | |
113 | ||
8d5726c4 EG |
114 | static int mrrs = -1; |
115 | module_param(mrrs, int, 0); | |
116 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); | |
117 | ||
9898f86d | 118 | static int debug; |
a2fbb9ea | 119 | module_param(debug, int, 0); |
9898f86d EG |
120 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
121 | ||
619c5cb6 | 122 | struct workqueue_struct *bnx2x_wq; |
ec6ba945 | 123 | |
1ef1d45a BW |
124 | struct bnx2x_mac_vals { |
125 | u32 xmac_addr; | |
126 | u32 xmac_val; | |
127 | u32 emac_addr; | |
128 | u32 emac_val; | |
129 | u32 umac_addr; | |
130 | u32 umac_val; | |
131 | u32 bmac_addr; | |
132 | u32 bmac_val[2]; | |
133 | }; | |
134 | ||
a2fbb9ea ET |
135 | enum bnx2x_board_type { |
136 | BCM57710 = 0, | |
619c5cb6 VZ |
137 | BCM57711, |
138 | BCM57711E, | |
139 | BCM57712, | |
140 | BCM57712_MF, | |
1ab4434c | 141 | BCM57712_VF, |
619c5cb6 VZ |
142 | BCM57800, |
143 | BCM57800_MF, | |
1ab4434c | 144 | BCM57800_VF, |
619c5cb6 VZ |
145 | BCM57810, |
146 | BCM57810_MF, | |
1ab4434c | 147 | BCM57810_VF, |
c3def943 YM |
148 | BCM57840_4_10, |
149 | BCM57840_2_20, | |
7e8e02df | 150 | BCM57840_MF, |
1ab4434c | 151 | BCM57840_VF, |
7e8e02df | 152 | BCM57811, |
1ab4434c AE |
153 | BCM57811_MF, |
154 | BCM57840_O, | |
155 | BCM57840_MFO, | |
156 | BCM57811_VF | |
a2fbb9ea ET |
157 | }; |
158 | ||
34f80b04 | 159 | /* indexed by board_type, above */ |
53a10565 | 160 | static struct { |
a2fbb9ea | 161 | char *name; |
0329aba1 | 162 | } board_info[] = { |
1ab4434c AE |
163 | [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
164 | [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, | |
165 | [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, | |
166 | [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, | |
167 | [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, | |
168 | [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" }, | |
169 | [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, | |
170 | [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, | |
171 | [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" }, | |
172 | [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, | |
173 | [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, | |
174 | [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" }, | |
175 | [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" }, | |
176 | [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" }, | |
177 | [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
178 | [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }, | |
179 | [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" }, | |
180 | [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" }, | |
181 | [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, | |
182 | [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
183 | [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" } | |
a2fbb9ea ET |
184 | }; |
185 | ||
619c5cb6 VZ |
186 | #ifndef PCI_DEVICE_ID_NX2_57710 |
187 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
188 | #endif | |
189 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
190 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
191 | #endif | |
192 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
193 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
194 | #endif | |
195 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
196 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
197 | #endif | |
198 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
199 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
200 | #endif | |
8395be5e AE |
201 | #ifndef PCI_DEVICE_ID_NX2_57712_VF |
202 | #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF | |
203 | #endif | |
619c5cb6 VZ |
204 | #ifndef PCI_DEVICE_ID_NX2_57800 |
205 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
206 | #endif | |
207 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
208 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
209 | #endif | |
8395be5e AE |
210 | #ifndef PCI_DEVICE_ID_NX2_57800_VF |
211 | #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF | |
212 | #endif | |
619c5cb6 VZ |
213 | #ifndef PCI_DEVICE_ID_NX2_57810 |
214 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
215 | #endif | |
216 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
217 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
218 | #endif | |
c3def943 YM |
219 | #ifndef PCI_DEVICE_ID_NX2_57840_O |
220 | #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE | |
221 | #endif | |
8395be5e AE |
222 | #ifndef PCI_DEVICE_ID_NX2_57810_VF |
223 | #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF | |
224 | #endif | |
c3def943 YM |
225 | #ifndef PCI_DEVICE_ID_NX2_57840_4_10 |
226 | #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 | |
227 | #endif | |
228 | #ifndef PCI_DEVICE_ID_NX2_57840_2_20 | |
229 | #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 | |
230 | #endif | |
231 | #ifndef PCI_DEVICE_ID_NX2_57840_MFO | |
232 | #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE | |
619c5cb6 VZ |
233 | #endif |
234 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
235 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
236 | #endif | |
8395be5e AE |
237 | #ifndef PCI_DEVICE_ID_NX2_57840_VF |
238 | #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF | |
239 | #endif | |
7e8e02df BW |
240 | #ifndef PCI_DEVICE_ID_NX2_57811 |
241 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 | |
242 | #endif | |
243 | #ifndef PCI_DEVICE_ID_NX2_57811_MF | |
244 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF | |
245 | #endif | |
8395be5e AE |
246 | #ifndef PCI_DEVICE_ID_NX2_57811_VF |
247 | #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF | |
248 | #endif | |
249 | ||
a3aa1884 | 250 | static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { |
e4ed7113 EG |
251 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
252 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
253 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 254 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 | 255 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
8395be5e | 256 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, |
619c5cb6 VZ |
257 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, |
258 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
8395be5e | 259 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, |
619c5cb6 VZ |
260 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, |
261 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
c3def943 YM |
262 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, |
263 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, | |
264 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, | |
8395be5e | 265 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, |
c3def943 | 266 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, |
619c5cb6 | 267 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, |
8395be5e | 268 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, |
7e8e02df BW |
269 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
270 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, | |
8395be5e | 271 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, |
a2fbb9ea ET |
272 | { 0 } |
273 | }; | |
274 | ||
275 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
276 | ||
452427b0 YM |
277 | /* Global resources for unloading a previously loaded device */ |
278 | #define BNX2X_PREV_WAIT_NEEDED 1 | |
279 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); | |
280 | static LIST_HEAD(bnx2x_prev_list); | |
a2fbb9ea ET |
281 | /**************************************************************************** |
282 | * General service functions | |
283 | ****************************************************************************/ | |
284 | ||
1191cb83 | 285 | static void __storm_memset_dma_mapping(struct bnx2x *bp, |
619c5cb6 VZ |
286 | u32 addr, dma_addr_t mapping) |
287 | { | |
288 | REG_WR(bp, addr, U64_LO(mapping)); | |
289 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
290 | } | |
291 | ||
1191cb83 ED |
292 | static void storm_memset_spq_addr(struct bnx2x *bp, |
293 | dma_addr_t mapping, u16 abs_fid) | |
619c5cb6 VZ |
294 | { |
295 | u32 addr = XSEM_REG_FAST_MEMORY + | |
296 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
297 | ||
298 | __storm_memset_dma_mapping(bp, addr, mapping); | |
299 | } | |
300 | ||
1191cb83 ED |
301 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, |
302 | u16 pf_id) | |
523224a3 | 303 | { |
619c5cb6 VZ |
304 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
305 | pf_id); | |
306 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
307 | pf_id); | |
308 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
309 | pf_id); | |
310 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
311 | pf_id); | |
523224a3 DK |
312 | } |
313 | ||
1191cb83 ED |
314 | static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
315 | u8 enable) | |
619c5cb6 VZ |
316 | { |
317 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
318 | enable); | |
319 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
320 | enable); | |
321 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
322 | enable); | |
323 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
324 | enable); | |
325 | } | |
523224a3 | 326 | |
1191cb83 ED |
327 | static void storm_memset_eq_data(struct bnx2x *bp, |
328 | struct event_ring_data *eq_data, | |
523224a3 DK |
329 | u16 pfid) |
330 | { | |
331 | size_t size = sizeof(struct event_ring_data); | |
332 | ||
333 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
334 | ||
335 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
336 | } | |
337 | ||
1191cb83 ED |
338 | static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, |
339 | u16 pfid) | |
523224a3 DK |
340 | { |
341 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
342 | REG_WR16(bp, addr, eq_prod); | |
343 | } | |
344 | ||
a2fbb9ea ET |
345 | /* used only at init |
346 | * locking is done by mcp | |
347 | */ | |
8d96286a | 348 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
349 | { |
350 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
351 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
352 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
353 | PCICFG_VENDOR_ID_OFFSET); | |
354 | } | |
355 | ||
a2fbb9ea ET |
356 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
357 | { | |
358 | u32 val; | |
359 | ||
360 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
361 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
362 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
363 | PCICFG_VENDOR_ID_OFFSET); | |
364 | ||
365 | return val; | |
366 | } | |
a2fbb9ea | 367 | |
f2e0899f DK |
368 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
369 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
370 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
371 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
372 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
373 | ||
6bf07b8e YM |
374 | static void bnx2x_dp_dmae(struct bnx2x *bp, |
375 | struct dmae_command *dmae, int msglvl) | |
fd1fc79d AE |
376 | { |
377 | u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; | |
6bf07b8e | 378 | int i; |
fd1fc79d AE |
379 | |
380 | switch (dmae->opcode & DMAE_COMMAND_DST) { | |
381 | case DMAE_CMD_DST_PCI: | |
382 | if (src_type == DMAE_CMD_SRC_PCI) | |
383 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
384 | "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" | |
385 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
386 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
387 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
388 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
389 | dmae->comp_val); | |
390 | else | |
391 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
392 | "src [%08x], len [%d*4], dst [%x:%08x]\n" | |
393 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
394 | dmae->opcode, dmae->src_addr_lo >> 2, | |
395 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
396 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
397 | dmae->comp_val); | |
398 | break; | |
399 | case DMAE_CMD_DST_GRC: | |
400 | if (src_type == DMAE_CMD_SRC_PCI) | |
401 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
402 | "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" | |
403 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
404 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
405 | dmae->len, dmae->dst_addr_lo >> 2, | |
406 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
407 | dmae->comp_val); | |
408 | else | |
409 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
410 | "src [%08x], len [%d*4], dst [%08x]\n" | |
411 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
412 | dmae->opcode, dmae->src_addr_lo >> 2, | |
413 | dmae->len, dmae->dst_addr_lo >> 2, | |
414 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
415 | dmae->comp_val); | |
416 | break; | |
417 | default: | |
418 | if (src_type == DMAE_CMD_SRC_PCI) | |
419 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
420 | "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" | |
421 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
422 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
423 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
424 | dmae->comp_val); | |
425 | else | |
426 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
427 | "src_addr [%08x] len [%d * 4] dst_addr [none]\n" | |
428 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
429 | dmae->opcode, dmae->src_addr_lo >> 2, | |
430 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
431 | dmae->comp_val); | |
432 | break; | |
433 | } | |
6bf07b8e YM |
434 | |
435 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) | |
436 | DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", | |
437 | i, *(((u32 *)dmae) + i)); | |
fd1fc79d | 438 | } |
f2e0899f | 439 | |
a2fbb9ea | 440 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 441 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
442 | { |
443 | u32 cmd_offset; | |
444 | int i; | |
445 | ||
446 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
447 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
448 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
449 | } |
450 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
451 | } | |
452 | ||
f2e0899f | 453 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 454 | { |
f2e0899f DK |
455 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
456 | DMAE_CMD_C_ENABLE); | |
457 | } | |
ad8d3948 | 458 | |
f2e0899f DK |
459 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
460 | { | |
461 | return opcode & ~DMAE_CMD_SRC_RESET; | |
462 | } | |
ad8d3948 | 463 | |
f2e0899f DK |
464 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
465 | bool with_comp, u8 comp_type) | |
466 | { | |
467 | u32 opcode = 0; | |
468 | ||
469 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
470 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 471 | |
f2e0899f DK |
472 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
473 | ||
474 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
475 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
476 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 477 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 478 | |
a2fbb9ea | 479 | #ifdef __BIG_ENDIAN |
f2e0899f | 480 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 481 | #else |
f2e0899f | 482 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 483 | #endif |
f2e0899f DK |
484 | if (with_comp) |
485 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
486 | return opcode; | |
487 | } | |
488 | ||
fd1fc79d | 489 | void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
8d96286a | 490 | struct dmae_command *dmae, |
491 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
492 | { |
493 | memset(dmae, 0, sizeof(struct dmae_command)); | |
494 | ||
495 | /* set the opcode */ | |
496 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
497 | true, DMAE_COMP_PCI); | |
498 | ||
499 | /* fill in the completion parameters */ | |
500 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
501 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
502 | dmae->comp_val = DMAE_COMP_VAL; | |
503 | } | |
504 | ||
fd1fc79d AE |
505 | /* issue a dmae command over the init-channel and wait for completion */ |
506 | int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae) | |
f2e0899f DK |
507 | { |
508 | u32 *wb_comp = bnx2x_sp(bp, wb_comp); | |
5e374b5a | 509 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
510 | int rc = 0; |
511 | ||
6bf07b8e YM |
512 | bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); |
513 | ||
514 | /* Lock the dmae channel. Disable BHs to prevent a dead-lock | |
619c5cb6 VZ |
515 | * as long as this code is called both from syscall context and |
516 | * from ndo_set_rx_mode() flow that may be called from BH. | |
517 | */ | |
6e30dd4e | 518 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 519 | |
f2e0899f | 520 | /* reset completion */ |
a2fbb9ea ET |
521 | *wb_comp = 0; |
522 | ||
f2e0899f DK |
523 | /* post the command on the channel used for initializations */ |
524 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 525 | |
f2e0899f | 526 | /* wait for completion */ |
a2fbb9ea | 527 | udelay(5); |
f2e0899f | 528 | while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 | 529 | |
95c6c616 AE |
530 | if (!cnt || |
531 | (bp->recovery_state != BNX2X_RECOVERY_DONE && | |
532 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
c3eefaf6 | 533 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
534 | rc = DMAE_TIMEOUT; |
535 | goto unlock; | |
a2fbb9ea | 536 | } |
ad8d3948 | 537 | cnt--; |
f2e0899f | 538 | udelay(50); |
a2fbb9ea | 539 | } |
f2e0899f DK |
540 | if (*wb_comp & DMAE_PCI_ERR_FLAG) { |
541 | BNX2X_ERR("DMAE PCI error!\n"); | |
542 | rc = DMAE_PCI_ERROR; | |
543 | } | |
544 | ||
f2e0899f | 545 | unlock: |
6e30dd4e | 546 | spin_unlock_bh(&bp->dmae_lock); |
f2e0899f DK |
547 | return rc; |
548 | } | |
549 | ||
550 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
551 | u32 len32) | |
552 | { | |
6bf07b8e | 553 | int rc; |
f2e0899f DK |
554 | struct dmae_command dmae; |
555 | ||
556 | if (!bp->dmae_ready) { | |
557 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
558 | ||
127a425e AE |
559 | if (CHIP_IS_E1(bp)) |
560 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
561 | else | |
562 | bnx2x_init_str_wr(bp, dst_addr, data, len32); | |
f2e0899f DK |
563 | return; |
564 | } | |
565 | ||
566 | /* set opcode and fixed command fields */ | |
567 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
568 | ||
569 | /* fill in addresses and len */ | |
570 | dmae.src_addr_lo = U64_LO(dma_addr); | |
571 | dmae.src_addr_hi = U64_HI(dma_addr); | |
572 | dmae.dst_addr_lo = dst_addr >> 2; | |
573 | dmae.dst_addr_hi = 0; | |
574 | dmae.len = len32; | |
575 | ||
f2e0899f | 576 | /* issue the command and wait for completion */ |
6bf07b8e YM |
577 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae); |
578 | if (rc) { | |
579 | BNX2X_ERR("DMAE returned failure %d\n", rc); | |
580 | bnx2x_panic(); | |
581 | } | |
a2fbb9ea ET |
582 | } |
583 | ||
c18487ee | 584 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 585 | { |
6bf07b8e | 586 | int rc; |
5ff7b6d4 | 587 | struct dmae_command dmae; |
ad8d3948 EG |
588 | |
589 | if (!bp->dmae_ready) { | |
590 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
591 | int i; | |
592 | ||
51c1a580 | 593 | if (CHIP_IS_E1(bp)) |
127a425e AE |
594 | for (i = 0; i < len32; i++) |
595 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
51c1a580 | 596 | else |
127a425e AE |
597 | for (i = 0; i < len32; i++) |
598 | data[i] = REG_RD(bp, src_addr + i*4); | |
599 | ||
ad8d3948 EG |
600 | return; |
601 | } | |
602 | ||
f2e0899f DK |
603 | /* set opcode and fixed command fields */ |
604 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 605 | |
f2e0899f | 606 | /* fill in addresses and len */ |
5ff7b6d4 EG |
607 | dmae.src_addr_lo = src_addr >> 2; |
608 | dmae.src_addr_hi = 0; | |
609 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
610 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
611 | dmae.len = len32; | |
ad8d3948 | 612 | |
f2e0899f | 613 | /* issue the command and wait for completion */ |
6bf07b8e YM |
614 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae); |
615 | if (rc) { | |
616 | BNX2X_ERR("DMAE returned failure %d\n", rc); | |
617 | bnx2x_panic(); | |
c957d09f | 618 | } |
ad8d3948 EG |
619 | } |
620 | ||
8d96286a | 621 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
622 | u32 addr, u32 len) | |
573f2035 | 623 | { |
02e3c6cb | 624 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
625 | int offset = 0; |
626 | ||
02e3c6cb | 627 | while (len > dmae_wr_max) { |
573f2035 | 628 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
629 | addr + offset, dmae_wr_max); |
630 | offset += dmae_wr_max * 4; | |
631 | len -= dmae_wr_max; | |
573f2035 EG |
632 | } |
633 | ||
634 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
635 | } | |
636 | ||
a2fbb9ea ET |
637 | static int bnx2x_mc_assert(struct bnx2x *bp) |
638 | { | |
a2fbb9ea | 639 | char last_idx; |
34f80b04 EG |
640 | int i, rc = 0; |
641 | u32 row0, row1, row2, row3; | |
642 | ||
643 | /* XSTORM */ | |
644 | last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + | |
645 | XSTORM_ASSERT_LIST_INDEX_OFFSET); | |
646 | if (last_idx) | |
647 | BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
648 | ||
649 | /* print the asserts */ | |
650 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
651 | ||
652 | row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
653 | XSTORM_ASSERT_LIST_OFFSET(i)); | |
654 | row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
655 | XSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
656 | row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
657 | XSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
658 | row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
659 | XSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
660 | ||
661 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 662 | BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
663 | i, row3, row2, row1, row0); |
664 | rc++; | |
665 | } else { | |
666 | break; | |
667 | } | |
668 | } | |
669 | ||
670 | /* TSTORM */ | |
671 | last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + | |
672 | TSTORM_ASSERT_LIST_INDEX_OFFSET); | |
673 | if (last_idx) | |
674 | BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
675 | ||
676 | /* print the asserts */ | |
677 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
678 | ||
679 | row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
680 | TSTORM_ASSERT_LIST_OFFSET(i)); | |
681 | row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
682 | TSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
683 | row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
684 | TSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
685 | row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
686 | TSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
687 | ||
688 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 689 | BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
690 | i, row3, row2, row1, row0); |
691 | rc++; | |
692 | } else { | |
693 | break; | |
694 | } | |
695 | } | |
696 | ||
697 | /* CSTORM */ | |
698 | last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + | |
699 | CSTORM_ASSERT_LIST_INDEX_OFFSET); | |
700 | if (last_idx) | |
701 | BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
702 | ||
703 | /* print the asserts */ | |
704 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
705 | ||
706 | row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
707 | CSTORM_ASSERT_LIST_OFFSET(i)); | |
708 | row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
709 | CSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
710 | row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
711 | CSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
712 | row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
713 | CSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
714 | ||
715 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 716 | BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
717 | i, row3, row2, row1, row0); |
718 | rc++; | |
719 | } else { | |
720 | break; | |
721 | } | |
722 | } | |
723 | ||
724 | /* USTORM */ | |
725 | last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + | |
726 | USTORM_ASSERT_LIST_INDEX_OFFSET); | |
727 | if (last_idx) | |
728 | BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
729 | ||
730 | /* print the asserts */ | |
731 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
732 | ||
733 | row0 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
734 | USTORM_ASSERT_LIST_OFFSET(i)); | |
735 | row1 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
736 | USTORM_ASSERT_LIST_OFFSET(i) + 4); | |
737 | row2 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
738 | USTORM_ASSERT_LIST_OFFSET(i) + 8); | |
739 | row3 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
740 | USTORM_ASSERT_LIST_OFFSET(i) + 12); | |
741 | ||
742 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 743 | BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
744 | i, row3, row2, row1, row0); |
745 | rc++; | |
746 | } else { | |
747 | break; | |
a2fbb9ea ET |
748 | } |
749 | } | |
34f80b04 | 750 | |
a2fbb9ea ET |
751 | return rc; |
752 | } | |
c14423fe | 753 | |
7a25cc73 | 754 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 755 | { |
7a25cc73 | 756 | u32 addr, val; |
a2fbb9ea | 757 | u32 mark, offset; |
4781bfad | 758 | __be32 data[9]; |
a2fbb9ea | 759 | int word; |
f2e0899f | 760 | u32 trace_shmem_base; |
2145a920 VZ |
761 | if (BP_NOMCP(bp)) { |
762 | BNX2X_ERR("NO MCP - can not dump\n"); | |
763 | return; | |
764 | } | |
7a25cc73 DK |
765 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
766 | (bp->common.bc_ver & 0xff0000) >> 16, | |
767 | (bp->common.bc_ver & 0xff00) >> 8, | |
768 | (bp->common.bc_ver & 0xff)); | |
769 | ||
770 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
771 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
51c1a580 | 772 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
cdaa7cb8 | 773 | |
f2e0899f DK |
774 | if (BP_PATH(bp) == 0) |
775 | trace_shmem_base = bp->common.shmem_base; | |
776 | else | |
777 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
de128804 DK |
778 | addr = trace_shmem_base - 0x800; |
779 | ||
780 | /* validate TRCB signature */ | |
781 | mark = REG_RD(bp, addr); | |
782 | if (mark != MFW_TRACE_SIGNATURE) { | |
783 | BNX2X_ERR("Trace buffer signature is missing."); | |
784 | return ; | |
785 | } | |
786 | ||
787 | /* read cyclic buffer pointer */ | |
788 | addr += 4; | |
cdaa7cb8 | 789 | mark = REG_RD(bp, addr); |
f2e0899f DK |
790 | mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) |
791 | + ((mark + 0x3) & ~0x3) - 0x08000000; | |
7a25cc73 | 792 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 793 | |
7a25cc73 | 794 | printk("%s", lvl); |
2de67439 YM |
795 | |
796 | /* dump buffer after the mark */ | |
f2e0899f | 797 | for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 798 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 799 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 800 | data[8] = 0x0; |
7995c64e | 801 | pr_cont("%s", (char *)data); |
a2fbb9ea | 802 | } |
2de67439 YM |
803 | |
804 | /* dump buffer before the mark */ | |
cdaa7cb8 | 805 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 806 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 807 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 808 | data[8] = 0x0; |
7995c64e | 809 | pr_cont("%s", (char *)data); |
a2fbb9ea | 810 | } |
7a25cc73 DK |
811 | printk("%s" "end of fw dump\n", lvl); |
812 | } | |
813 | ||
1191cb83 | 814 | static void bnx2x_fw_dump(struct bnx2x *bp) |
7a25cc73 DK |
815 | { |
816 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
817 | } |
818 | ||
823e1d90 YM |
819 | static void bnx2x_hc_int_disable(struct bnx2x *bp) |
820 | { | |
821 | int port = BP_PORT(bp); | |
822 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; | |
823 | u32 val = REG_RD(bp, addr); | |
824 | ||
825 | /* in E1 we must use only PCI configuration space to disable | |
16a5fd92 YM |
826 | * MSI/MSIX capability |
827 | * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
823e1d90 YM |
828 | */ |
829 | if (CHIP_IS_E1(bp)) { | |
830 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
831 | * Use mask register to prevent from HC sending interrupts | |
832 | * after we exit the function | |
833 | */ | |
834 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
835 | ||
836 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
837 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
838 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
839 | } else | |
840 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
841 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
842 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
843 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
844 | ||
845 | DP(NETIF_MSG_IFDOWN, | |
846 | "write %x to HC %d (addr 0x%x)\n", | |
847 | val, port, addr); | |
848 | ||
849 | /* flush all outstanding writes */ | |
850 | mmiowb(); | |
851 | ||
852 | REG_WR(bp, addr, val); | |
853 | if (REG_RD(bp, addr) != val) | |
6bf07b8e | 854 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
823e1d90 YM |
855 | } |
856 | ||
857 | static void bnx2x_igu_int_disable(struct bnx2x *bp) | |
858 | { | |
859 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
860 | ||
861 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
862 | IGU_PF_CONF_INT_LINE_EN | | |
863 | IGU_PF_CONF_ATTN_BIT_EN); | |
864 | ||
865 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); | |
866 | ||
867 | /* flush all outstanding writes */ | |
868 | mmiowb(); | |
869 | ||
870 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
871 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
6bf07b8e | 872 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
823e1d90 YM |
873 | } |
874 | ||
875 | static void bnx2x_int_disable(struct bnx2x *bp) | |
876 | { | |
877 | if (bp->common.int_block == INT_BLOCK_HC) | |
878 | bnx2x_hc_int_disable(bp); | |
879 | else | |
880 | bnx2x_igu_int_disable(bp); | |
881 | } | |
882 | ||
883 | void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) | |
a2fbb9ea ET |
884 | { |
885 | int i; | |
523224a3 DK |
886 | u16 j; |
887 | struct hc_sp_status_block_data sp_sb_data; | |
888 | int func = BP_FUNC(bp); | |
889 | #ifdef BNX2X_STOP_ON_ERROR | |
890 | u16 start = 0, end = 0; | |
6383c0b3 | 891 | u8 cos; |
523224a3 | 892 | #endif |
823e1d90 YM |
893 | if (disable_int) |
894 | bnx2x_int_disable(bp); | |
a2fbb9ea | 895 | |
66e855f3 | 896 | bp->stats_state = STATS_STATE_DISABLED; |
7a752993 | 897 | bp->eth_stats.unrecoverable_error++; |
66e855f3 YG |
898 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
899 | ||
a2fbb9ea ET |
900 | BNX2X_ERR("begin crash dump -----------------\n"); |
901 | ||
8440d2b6 EG |
902 | /* Indices */ |
903 | /* Common */ | |
51c1a580 | 904 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", |
619c5cb6 VZ |
905 | bp->def_idx, bp->def_att_idx, bp->attn_state, |
906 | bp->spq_prod_idx, bp->stats_counter); | |
523224a3 DK |
907 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", |
908 | bp->def_status_blk->atten_status_block.attn_bits, | |
909 | bp->def_status_blk->atten_status_block.attn_bits_ack, | |
910 | bp->def_status_blk->atten_status_block.status_block_id, | |
911 | bp->def_status_blk->atten_status_block.attn_bits_index); | |
912 | BNX2X_ERR(" def ("); | |
913 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
914 | pr_cont("0x%x%s", | |
f1deab50 JP |
915 | bp->def_status_blk->sp_sb.index_values[i], |
916 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
523224a3 DK |
917 | |
918 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
919 | *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
920 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
921 | i*sizeof(u32)); | |
922 | ||
f1deab50 | 923 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", |
523224a3 DK |
924 | sp_sb_data.igu_sb_id, |
925 | sp_sb_data.igu_seg_id, | |
926 | sp_sb_data.p_func.pf_id, | |
927 | sp_sb_data.p_func.vnic_id, | |
928 | sp_sb_data.p_func.vf_id, | |
619c5cb6 VZ |
929 | sp_sb_data.p_func.vf_valid, |
930 | sp_sb_data.state); | |
523224a3 | 931 | |
ec6ba945 | 932 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 933 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 934 | int loop; |
f2e0899f | 935 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
936 | struct hc_status_block_data_e1x sb_data_e1x; |
937 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
938 | CHIP_IS_E1x(bp) ? |
939 | sb_data_e1x.common.state_machine : | |
940 | sb_data_e2.common.state_machine; | |
523224a3 | 941 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
942 | CHIP_IS_E1x(bp) ? |
943 | sb_data_e1x.index_data : | |
944 | sb_data_e2.index_data; | |
6383c0b3 | 945 | u8 data_size, cos; |
523224a3 | 946 | u32 *sb_data_p; |
6383c0b3 | 947 | struct bnx2x_fp_txdata txdata; |
523224a3 DK |
948 | |
949 | /* Rx */ | |
51c1a580 | 950 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 951 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 952 | fp->rx_comp_prod, |
66e855f3 | 953 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
51c1a580 | 954 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
8440d2b6 | 955 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 956 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 957 | |
523224a3 | 958 | /* Tx */ |
6383c0b3 AE |
959 | for_each_cos_in_tx_queue(fp, cos) |
960 | { | |
65565884 | 961 | txdata = *fp->txdata_ptr[cos]; |
51c1a580 | 962 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
6383c0b3 AE |
963 | i, txdata.tx_pkt_prod, |
964 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
965 | txdata.tx_bd_cons, | |
966 | le16_to_cpu(*txdata.tx_cons_sb)); | |
967 | } | |
523224a3 | 968 | |
619c5cb6 VZ |
969 | loop = CHIP_IS_E1x(bp) ? |
970 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
971 | |
972 | /* host sb data */ | |
973 | ||
ec6ba945 VZ |
974 | if (IS_FCOE_FP(fp)) |
975 | continue; | |
55c11941 | 976 | |
523224a3 DK |
977 | BNX2X_ERR(" run indexes ("); |
978 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
979 | pr_cont("0x%x%s", | |
980 | fp->sb_running_index[j], | |
981 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
982 | ||
983 | BNX2X_ERR(" indexes ("); | |
984 | for (j = 0; j < loop; j++) | |
985 | pr_cont("0x%x%s", | |
986 | fp->sb_index_values[j], | |
987 | (j == loop - 1) ? ")" : " "); | |
988 | /* fw sb data */ | |
619c5cb6 VZ |
989 | data_size = CHIP_IS_E1x(bp) ? |
990 | sizeof(struct hc_status_block_data_e1x) : | |
991 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 992 | data_size /= sizeof(u32); |
619c5cb6 VZ |
993 | sb_data_p = CHIP_IS_E1x(bp) ? |
994 | (u32 *)&sb_data_e1x : | |
995 | (u32 *)&sb_data_e2; | |
523224a3 DK |
996 | /* copy sb data in here */ |
997 | for (j = 0; j < data_size; j++) | |
998 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
999 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
1000 | j * sizeof(u32)); | |
1001 | ||
619c5cb6 | 1002 | if (!CHIP_IS_E1x(bp)) { |
51c1a580 | 1003 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
1004 | sb_data_e2.common.p_func.pf_id, |
1005 | sb_data_e2.common.p_func.vf_id, | |
1006 | sb_data_e2.common.p_func.vf_valid, | |
1007 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
1008 | sb_data_e2.common.same_igu_sb_1b, |
1009 | sb_data_e2.common.state); | |
f2e0899f | 1010 | } else { |
51c1a580 | 1011 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
1012 | sb_data_e1x.common.p_func.pf_id, |
1013 | sb_data_e1x.common.p_func.vf_id, | |
1014 | sb_data_e1x.common.p_func.vf_valid, | |
1015 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
1016 | sb_data_e1x.common.same_igu_sb_1b, |
1017 | sb_data_e1x.common.state); | |
f2e0899f | 1018 | } |
523224a3 DK |
1019 | |
1020 | /* SB_SMs data */ | |
1021 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
51c1a580 MS |
1022 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
1023 | j, hc_sm_p[j].__flags, | |
1024 | hc_sm_p[j].igu_sb_id, | |
1025 | hc_sm_p[j].igu_seg_id, | |
1026 | hc_sm_p[j].time_to_expire, | |
1027 | hc_sm_p[j].timer_value); | |
523224a3 DK |
1028 | } |
1029 | ||
16a5fd92 | 1030 | /* Indices data */ |
523224a3 | 1031 | for (j = 0; j < loop; j++) { |
51c1a580 | 1032 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
523224a3 DK |
1033 | hc_index_p[j].flags, |
1034 | hc_index_p[j].timeout); | |
1035 | } | |
8440d2b6 | 1036 | } |
a2fbb9ea | 1037 | |
523224a3 | 1038 | #ifdef BNX2X_STOP_ON_ERROR |
04c46736 YM |
1039 | |
1040 | /* event queue */ | |
6bf07b8e | 1041 | BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); |
04c46736 YM |
1042 | for (i = 0; i < NUM_EQ_DESC; i++) { |
1043 | u32 *data = (u32 *)&bp->eq_ring[i].message.data; | |
1044 | ||
1045 | BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n", | |
1046 | i, bp->eq_ring[i].message.opcode, | |
1047 | bp->eq_ring[i].message.error); | |
1048 | BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]); | |
1049 | } | |
1050 | ||
8440d2b6 EG |
1051 | /* Rings */ |
1052 | /* Rx */ | |
55c11941 | 1053 | for_each_valid_rx_queue(bp, i) { |
8440d2b6 | 1054 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea ET |
1055 | |
1056 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); | |
1057 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 1058 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
1059 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
1060 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
1061 | ||
c3eefaf6 | 1062 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
44151acb | 1063 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
a2fbb9ea ET |
1064 | } |
1065 | ||
3196a88a EG |
1066 | start = RX_SGE(fp->rx_sge_prod); |
1067 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 1068 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
1069 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
1070 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
1071 | ||
c3eefaf6 EG |
1072 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
1073 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
1074 | } |
1075 | ||
a2fbb9ea ET |
1076 | start = RCQ_BD(fp->rx_comp_cons - 10); |
1077 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 1078 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
1079 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
1080 | ||
c3eefaf6 EG |
1081 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
1082 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
1083 | } |
1084 | } | |
1085 | ||
8440d2b6 | 1086 | /* Tx */ |
55c11941 | 1087 | for_each_valid_tx_queue(bp, i) { |
8440d2b6 | 1088 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
6383c0b3 | 1089 | for_each_cos_in_tx_queue(fp, cos) { |
65565884 | 1090 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
6383c0b3 AE |
1091 | |
1092 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); | |
1093 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
1094 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1095 | struct sw_tx_bd *sw_bd = | |
1096 | &txdata->tx_buf_ring[j]; | |
1097 | ||
51c1a580 | 1098 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
6383c0b3 AE |
1099 | i, cos, j, sw_bd->skb, |
1100 | sw_bd->first_bd); | |
1101 | } | |
8440d2b6 | 1102 | |
6383c0b3 AE |
1103 | start = TX_BD(txdata->tx_bd_cons - 10); |
1104 | end = TX_BD(txdata->tx_bd_cons + 254); | |
1105 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1106 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 1107 | |
51c1a580 | 1108 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
6383c0b3 AE |
1109 | i, cos, j, tx_bd[0], tx_bd[1], |
1110 | tx_bd[2], tx_bd[3]); | |
1111 | } | |
8440d2b6 EG |
1112 | } |
1113 | } | |
523224a3 | 1114 | #endif |
34f80b04 | 1115 | bnx2x_fw_dump(bp); |
a2fbb9ea ET |
1116 | bnx2x_mc_assert(bp); |
1117 | BNX2X_ERR("end crash dump -----------------\n"); | |
a2fbb9ea ET |
1118 | } |
1119 | ||
619c5cb6 VZ |
1120 | /* |
1121 | * FLR Support for E2 | |
1122 | * | |
1123 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
1124 | * initialization. | |
1125 | */ | |
16a5fd92 | 1126 | #define FLR_WAIT_USEC 10000 /* 10 milliseconds */ |
89db4ad8 AE |
1127 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
1128 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ | |
619c5cb6 VZ |
1129 | |
1130 | struct pbf_pN_buf_regs { | |
1131 | int pN; | |
1132 | u32 init_crd; | |
1133 | u32 crd; | |
1134 | u32 crd_freed; | |
1135 | }; | |
1136 | ||
1137 | struct pbf_pN_cmd_regs { | |
1138 | int pN; | |
1139 | u32 lines_occup; | |
1140 | u32 lines_freed; | |
1141 | }; | |
1142 | ||
1143 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
1144 | struct pbf_pN_buf_regs *regs, | |
1145 | u32 poll_count) | |
1146 | { | |
1147 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
1148 | u32 cur_cnt = poll_count; | |
1149 | ||
1150 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
1151 | crd = crd_start = REG_RD(bp, regs->crd); | |
1152 | init_crd = REG_RD(bp, regs->init_crd); | |
1153 | ||
1154 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
1155 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
1156 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
1157 | ||
1158 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
1159 | (init_crd - crd_start))) { | |
1160 | if (cur_cnt--) { | |
89db4ad8 | 1161 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1162 | crd = REG_RD(bp, regs->crd); |
1163 | crd_freed = REG_RD(bp, regs->crd_freed); | |
1164 | } else { | |
1165 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
1166 | regs->pN); | |
1167 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
1168 | regs->pN, crd); | |
1169 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
1170 | regs->pN, crd_freed); | |
1171 | break; | |
1172 | } | |
1173 | } | |
1174 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
89db4ad8 | 1175 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1176 | } |
1177 | ||
1178 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
1179 | struct pbf_pN_cmd_regs *regs, | |
1180 | u32 poll_count) | |
1181 | { | |
1182 | u32 occup, to_free, freed, freed_start; | |
1183 | u32 cur_cnt = poll_count; | |
1184 | ||
1185 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
1186 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
1187 | ||
1188 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
1189 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
1190 | ||
1191 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
1192 | if (cur_cnt--) { | |
89db4ad8 | 1193 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1194 | occup = REG_RD(bp, regs->lines_occup); |
1195 | freed = REG_RD(bp, regs->lines_freed); | |
1196 | } else { | |
1197 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
1198 | regs->pN); | |
1199 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
1200 | regs->pN, occup); | |
1201 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
1202 | regs->pN, freed); | |
1203 | break; | |
1204 | } | |
1205 | } | |
1206 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
89db4ad8 | 1207 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1208 | } |
1209 | ||
1191cb83 ED |
1210 | static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, |
1211 | u32 expected, u32 poll_count) | |
619c5cb6 VZ |
1212 | { |
1213 | u32 cur_cnt = poll_count; | |
1214 | u32 val; | |
1215 | ||
1216 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
89db4ad8 | 1217 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1218 | |
1219 | return val; | |
1220 | } | |
1221 | ||
d16132ce AE |
1222 | int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, |
1223 | char *msg, u32 poll_cnt) | |
619c5cb6 VZ |
1224 | { |
1225 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1226 | if (val != 0) { | |
1227 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1228 | return 1; | |
1229 | } | |
1230 | return 0; | |
1231 | } | |
1232 | ||
d16132ce AE |
1233 | /* Common routines with VF FLR cleanup */ |
1234 | u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
619c5cb6 VZ |
1235 | { |
1236 | /* adjust polling timeout */ | |
1237 | if (CHIP_REV_IS_EMUL(bp)) | |
1238 | return FLR_POLL_CNT * 2000; | |
1239 | ||
1240 | if (CHIP_REV_IS_FPGA(bp)) | |
1241 | return FLR_POLL_CNT * 120; | |
1242 | ||
1243 | return FLR_POLL_CNT; | |
1244 | } | |
1245 | ||
d16132ce | 1246 | void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) |
619c5cb6 VZ |
1247 | { |
1248 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1249 | {0, (CHIP_IS_E3B0(bp)) ? | |
1250 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1251 | PBF_REG_P0_TQ_OCCUPANCY, | |
1252 | (CHIP_IS_E3B0(bp)) ? | |
1253 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1254 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1255 | {1, (CHIP_IS_E3B0(bp)) ? | |
1256 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1257 | PBF_REG_P1_TQ_OCCUPANCY, | |
1258 | (CHIP_IS_E3B0(bp)) ? | |
1259 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1260 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1261 | {4, (CHIP_IS_E3B0(bp)) ? | |
1262 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1263 | PBF_REG_P4_TQ_OCCUPANCY, | |
1264 | (CHIP_IS_E3B0(bp)) ? | |
1265 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1266 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1267 | }; | |
1268 | ||
1269 | struct pbf_pN_buf_regs buf_regs[] = { | |
1270 | {0, (CHIP_IS_E3B0(bp)) ? | |
1271 | PBF_REG_INIT_CRD_Q0 : | |
1272 | PBF_REG_P0_INIT_CRD , | |
1273 | (CHIP_IS_E3B0(bp)) ? | |
1274 | PBF_REG_CREDIT_Q0 : | |
1275 | PBF_REG_P0_CREDIT, | |
1276 | (CHIP_IS_E3B0(bp)) ? | |
1277 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1278 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1279 | {1, (CHIP_IS_E3B0(bp)) ? | |
1280 | PBF_REG_INIT_CRD_Q1 : | |
1281 | PBF_REG_P1_INIT_CRD, | |
1282 | (CHIP_IS_E3B0(bp)) ? | |
1283 | PBF_REG_CREDIT_Q1 : | |
1284 | PBF_REG_P1_CREDIT, | |
1285 | (CHIP_IS_E3B0(bp)) ? | |
1286 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1287 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1288 | {4, (CHIP_IS_E3B0(bp)) ? | |
1289 | PBF_REG_INIT_CRD_LB_Q : | |
1290 | PBF_REG_P4_INIT_CRD, | |
1291 | (CHIP_IS_E3B0(bp)) ? | |
1292 | PBF_REG_CREDIT_LB_Q : | |
1293 | PBF_REG_P4_CREDIT, | |
1294 | (CHIP_IS_E3B0(bp)) ? | |
1295 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1296 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1297 | }; | |
1298 | ||
1299 | int i; | |
1300 | ||
1301 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1302 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1303 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1304 | ||
619c5cb6 VZ |
1305 | /* Verify the transmission buffers are flushed P0, P1, P4 */ |
1306 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1307 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1308 | } | |
1309 | ||
1310 | #define OP_GEN_PARAM(param) \ | |
1311 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1312 | ||
1313 | #define OP_GEN_TYPE(type) \ | |
1314 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1315 | ||
1316 | #define OP_GEN_AGG_VECT(index) \ | |
1317 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1318 | ||
d16132ce | 1319 | int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) |
619c5cb6 | 1320 | { |
86564c3f | 1321 | u32 op_gen_command = 0; |
619c5cb6 VZ |
1322 | u32 comp_addr = BAR_CSTRORM_INTMEM + |
1323 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1324 | int ret = 0; | |
1325 | ||
1326 | if (REG_RD(bp, comp_addr)) { | |
89db4ad8 | 1327 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
619c5cb6 VZ |
1328 | return 1; |
1329 | } | |
1330 | ||
86564c3f YM |
1331 | op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); |
1332 | op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1333 | op_gen_command |= OP_GEN_AGG_VECT(clnup_func); | |
1334 | op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
619c5cb6 | 1335 | |
89db4ad8 | 1336 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
86564c3f | 1337 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); |
619c5cb6 VZ |
1338 | |
1339 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1340 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
51c1a580 MS |
1341 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
1342 | (REG_RD(bp, comp_addr))); | |
d16132ce AE |
1343 | bnx2x_panic(); |
1344 | return 1; | |
619c5cb6 | 1345 | } |
16a5fd92 | 1346 | /* Zero completion for next FLR */ |
619c5cb6 VZ |
1347 | REG_WR(bp, comp_addr, 0); |
1348 | ||
1349 | return ret; | |
1350 | } | |
1351 | ||
b56e9670 | 1352 | u8 bnx2x_is_pcie_pending(struct pci_dev *dev) |
619c5cb6 | 1353 | { |
619c5cb6 VZ |
1354 | u16 status; |
1355 | ||
2a80eebc | 1356 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
619c5cb6 VZ |
1357 | return status & PCI_EXP_DEVSTA_TRPND; |
1358 | } | |
1359 | ||
1360 | /* PF FLR specific routines | |
1361 | */ | |
1362 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1363 | { | |
619c5cb6 VZ |
1364 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ |
1365 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1366 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1367 | "CFC PF usage counter timed out", | |
1368 | poll_cnt)) | |
1369 | return 1; | |
1370 | ||
619c5cb6 VZ |
1371 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ |
1372 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1373 | DORQ_REG_PF_USAGE_CNT, | |
1374 | "DQ PF usage counter timed out", | |
1375 | poll_cnt)) | |
1376 | return 1; | |
1377 | ||
1378 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1379 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1380 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1381 | "QM PF usage counter timed out", | |
1382 | poll_cnt)) | |
1383 | return 1; | |
1384 | ||
1385 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1386 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1387 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1388 | "Timers VNIC usage counter timed out", | |
1389 | poll_cnt)) | |
1390 | return 1; | |
1391 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1392 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1393 | "Timers NUM_SCANS usage counter timed out", | |
1394 | poll_cnt)) | |
1395 | return 1; | |
1396 | ||
1397 | /* Wait DMAE PF usage counter to zero */ | |
1398 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1399 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
6bf07b8e | 1400 | "DMAE command register timed out", |
619c5cb6 VZ |
1401 | poll_cnt)) |
1402 | return 1; | |
1403 | ||
1404 | return 0; | |
1405 | } | |
1406 | ||
1407 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1408 | { | |
1409 | u32 val; | |
1410 | ||
1411 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1412 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1413 | ||
1414 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1415 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1416 | ||
1417 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1418 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1419 | ||
1420 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1421 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1422 | ||
1423 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1424 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1425 | ||
1426 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1427 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1428 | ||
1429 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1430 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1431 | ||
1432 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1433 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1434 | val); | |
1435 | } | |
1436 | ||
1437 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1438 | { | |
1439 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1440 | ||
1441 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1442 | ||
1443 | /* Re-enable PF target read access */ | |
1444 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1445 | ||
1446 | /* Poll HW usage counters */ | |
89db4ad8 | 1447 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
619c5cb6 VZ |
1448 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
1449 | return -EBUSY; | |
1450 | ||
1451 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1452 | ||
1453 | /* Send the FW cleanup command */ | |
1454 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1455 | return -EBUSY; | |
1456 | ||
1457 | /* ATC cleanup */ | |
1458 | ||
1459 | /* Verify TX hw is flushed */ | |
1460 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1461 | ||
1462 | /* Wait 100ms (not adjusted according to platform) */ | |
1463 | msleep(100); | |
1464 | ||
1465 | /* Verify no pending pci transactions */ | |
1466 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1467 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1468 | ||
1469 | /* Debug */ | |
1470 | bnx2x_hw_enable_status(bp); | |
1471 | ||
1472 | /* | |
1473 | * Master enable - Due to WB DMAE writes performed before this | |
1474 | * register is re-initialized as part of the regular function init | |
1475 | */ | |
1476 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1477 | ||
1478 | return 0; | |
1479 | } | |
1480 | ||
f2e0899f | 1481 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1482 | { |
34f80b04 | 1483 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1484 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1485 | u32 val = REG_RD(bp, addr); | |
69c326b3 DK |
1486 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1487 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1488 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
a2fbb9ea ET |
1489 | |
1490 | if (msix) { | |
8badd27a EG |
1491 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1492 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1493 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1494 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
69c326b3 DK |
1495 | if (single_msix) |
1496 | val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; | |
8badd27a EG |
1497 | } else if (msi) { |
1498 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1499 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1500 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1501 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1502 | } else { |
1503 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1504 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1505 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1506 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1507 | |
a0fd065c | 1508 | if (!CHIP_IS_E1(bp)) { |
51c1a580 MS |
1509 | DP(NETIF_MSG_IFUP, |
1510 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); | |
615f8fd9 | 1511 | |
a0fd065c | 1512 | REG_WR(bp, addr, val); |
615f8fd9 | 1513 | |
a0fd065c DK |
1514 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1515 | } | |
a2fbb9ea ET |
1516 | } |
1517 | ||
a0fd065c DK |
1518 | if (CHIP_IS_E1(bp)) |
1519 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1520 | ||
51c1a580 MS |
1521 | DP(NETIF_MSG_IFUP, |
1522 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, | |
1523 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1524 | |
1525 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1526 | /* |
1527 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1528 | */ | |
1529 | mmiowb(); | |
1530 | barrier(); | |
34f80b04 | 1531 | |
f2e0899f | 1532 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1533 | /* init leading/trailing edge */ |
fb3bff17 | 1534 | if (IS_MF(bp)) { |
3395a033 | 1535 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1536 | if (bp->port.pmf) |
4acac6a5 EG |
1537 | /* enable nig and gpio3 attention */ |
1538 | val |= 0x1100; | |
34f80b04 EG |
1539 | } else |
1540 | val = 0xffff; | |
1541 | ||
1542 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1543 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1544 | } | |
37dbbf32 EG |
1545 | |
1546 | /* Make sure that interrupts are indeed enabled from here on */ | |
1547 | mmiowb(); | |
a2fbb9ea ET |
1548 | } |
1549 | ||
f2e0899f DK |
1550 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1551 | { | |
1552 | u32 val; | |
30a5de77 DK |
1553 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1554 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1555 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
f2e0899f DK |
1556 | |
1557 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1558 | ||
1559 | if (msix) { | |
1560 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1561 | IGU_PF_CONF_SINGLE_ISR_EN); | |
ebe61d80 | 1562 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
f2e0899f | 1563 | IGU_PF_CONF_ATTN_BIT_EN); |
30a5de77 DK |
1564 | |
1565 | if (single_msix) | |
1566 | val |= IGU_PF_CONF_SINGLE_ISR_EN; | |
f2e0899f DK |
1567 | } else if (msi) { |
1568 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
ebe61d80 | 1569 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
f2e0899f DK |
1570 | IGU_PF_CONF_ATTN_BIT_EN | |
1571 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1572 | } else { | |
1573 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
ebe61d80 | 1574 | val |= (IGU_PF_CONF_INT_LINE_EN | |
f2e0899f DK |
1575 | IGU_PF_CONF_ATTN_BIT_EN | |
1576 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1577 | } | |
1578 | ||
ebe61d80 YM |
1579 | /* Clean previous status - need to configure igu prior to ack*/ |
1580 | if ((!msix) || single_msix) { | |
1581 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1582 | bnx2x_ack_int(bp); | |
1583 | } | |
1584 | ||
1585 | val |= IGU_PF_CONF_FUNC_EN; | |
1586 | ||
51c1a580 | 1587 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
f2e0899f DK |
1588 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
1589 | ||
1590 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1591 | ||
79a8557a YM |
1592 | if (val & IGU_PF_CONF_INT_LINE_EN) |
1593 | pci_intx(bp->pdev, true); | |
1594 | ||
f2e0899f DK |
1595 | barrier(); |
1596 | ||
1597 | /* init leading/trailing edge */ | |
1598 | if (IS_MF(bp)) { | |
3395a033 | 1599 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1600 | if (bp->port.pmf) |
1601 | /* enable nig and gpio3 attention */ | |
1602 | val |= 0x1100; | |
1603 | } else | |
1604 | val = 0xffff; | |
1605 | ||
1606 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1607 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1608 | ||
1609 | /* Make sure that interrupts are indeed enabled from here on */ | |
1610 | mmiowb(); | |
1611 | } | |
1612 | ||
1613 | void bnx2x_int_enable(struct bnx2x *bp) | |
1614 | { | |
1615 | if (bp->common.int_block == INT_BLOCK_HC) | |
1616 | bnx2x_hc_int_enable(bp); | |
1617 | else | |
1618 | bnx2x_igu_int_enable(bp); | |
1619 | } | |
1620 | ||
9f6c9258 | 1621 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1622 | { |
a2fbb9ea | 1623 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1624 | int i, offset; |
a2fbb9ea | 1625 | |
f8ef6e44 YG |
1626 | if (disable_hw) |
1627 | /* prevent the HW from sending interrupts */ | |
1628 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1629 | |
1630 | /* make sure all ISRs are done */ | |
1631 | if (msix) { | |
8badd27a EG |
1632 | synchronize_irq(bp->msix_table[0].vector); |
1633 | offset = 1; | |
55c11941 MS |
1634 | if (CNIC_SUPPORT(bp)) |
1635 | offset++; | |
ec6ba945 | 1636 | for_each_eth_queue(bp, i) |
754a2f52 | 1637 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1638 | } else |
1639 | synchronize_irq(bp->pdev->irq); | |
1640 | ||
1641 | /* make sure sp_task is not running */ | |
1cf167f2 | 1642 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1643 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1644 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1645 | } |
1646 | ||
34f80b04 | 1647 | /* fast path */ |
a2fbb9ea ET |
1648 | |
1649 | /* | |
34f80b04 | 1650 | * General service functions |
a2fbb9ea ET |
1651 | */ |
1652 | ||
72fd0718 VZ |
1653 | /* Return true if succeeded to acquire the lock */ |
1654 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1655 | { | |
1656 | u32 lock_status; | |
1657 | u32 resource_bit = (1 << resource); | |
1658 | int func = BP_FUNC(bp); | |
1659 | u32 hw_lock_control_reg; | |
1660 | ||
51c1a580 MS |
1661 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1662 | "Trying to take a lock on resource %d\n", resource); | |
72fd0718 VZ |
1663 | |
1664 | /* Validating that the resource is within range */ | |
1665 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1666 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
72fd0718 VZ |
1667 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
1668 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1669 | return false; |
72fd0718 VZ |
1670 | } |
1671 | ||
1672 | if (func <= 5) | |
1673 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1674 | else | |
1675 | hw_lock_control_reg = | |
1676 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1677 | ||
1678 | /* Try to acquire the lock */ | |
1679 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1680 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1681 | if (lock_status & resource_bit) | |
1682 | return true; | |
1683 | ||
51c1a580 MS |
1684 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1685 | "Failed to get a lock on resource %d\n", resource); | |
72fd0718 VZ |
1686 | return false; |
1687 | } | |
1688 | ||
c9ee9206 VZ |
1689 | /** |
1690 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1691 | * | |
1692 | * @bp: driver handle | |
1693 | * | |
1694 | * Returns the recovery leader resource id according to the engine this function | |
1695 | * belongs to. Currently only only 2 engines is supported. | |
1696 | */ | |
1191cb83 | 1697 | static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) |
c9ee9206 VZ |
1698 | { |
1699 | if (BP_PATH(bp)) | |
1700 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1701 | else | |
1702 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1703 | } | |
1704 | ||
1705 | /** | |
2de67439 | 1706 | * bnx2x_trylock_leader_lock- try to acquire a leader lock. |
c9ee9206 VZ |
1707 | * |
1708 | * @bp: driver handle | |
1709 | * | |
2de67439 | 1710 | * Tries to acquire a leader lock for current engine. |
c9ee9206 | 1711 | */ |
1191cb83 | 1712 | static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) |
c9ee9206 VZ |
1713 | { |
1714 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1715 | } | |
1716 | ||
619c5cb6 | 1717 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
55c11941 | 1718 | |
fd1fc79d AE |
1719 | /* schedule the sp task and mark that interrupt occurred (runs from ISR) */ |
1720 | static int bnx2x_schedule_sp_task(struct bnx2x *bp) | |
1721 | { | |
1722 | /* Set the interrupt occurred bit for the sp-task to recognize it | |
1723 | * must ack the interrupt and transition according to the IGU | |
1724 | * state machine. | |
1725 | */ | |
1726 | atomic_set(&bp->interrupt_occurred, 1); | |
1727 | ||
1728 | /* The sp_task must execute only after this bit | |
1729 | * is set, otherwise we will get out of sync and miss all | |
1730 | * further interrupts. Hence, the barrier. | |
1731 | */ | |
1732 | smp_wmb(); | |
1733 | ||
1734 | /* schedule sp_task to workqueue */ | |
1735 | return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); | |
1736 | } | |
3196a88a | 1737 | |
619c5cb6 | 1738 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1739 | { |
1740 | struct bnx2x *bp = fp->bp; | |
1741 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1742 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 | 1743 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
15192a8c | 1744 | struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a2fbb9ea | 1745 | |
34f80b04 | 1746 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1747 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1748 | fp->index, cid, command, bp->state, |
34f80b04 | 1749 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1750 | |
fd1fc79d AE |
1751 | /* If cid is within VF range, replace the slowpath object with the |
1752 | * one corresponding to this VF | |
1753 | */ | |
1754 | if (cid >= BNX2X_FIRST_VF_CID && | |
1755 | cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) | |
1756 | bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); | |
1757 | ||
619c5cb6 VZ |
1758 | switch (command) { |
1759 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1760 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1761 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1762 | break; | |
d6cae238 | 1763 | |
619c5cb6 | 1764 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1765 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1766 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1767 | break; |
1768 | ||
6383c0b3 | 1769 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
51c1a580 | 1770 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
6383c0b3 AE |
1771 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
1772 | break; | |
1773 | ||
619c5cb6 | 1774 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1775 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1776 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1777 | break; |
1778 | ||
619c5cb6 | 1779 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
6bf07b8e | 1780 | DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid); |
619c5cb6 | 1781 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1782 | break; |
1783 | ||
619c5cb6 | 1784 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1785 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1786 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1787 | break; |
619c5cb6 VZ |
1788 | |
1789 | default: | |
1790 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1791 | command, fp->index); | |
1792 | return; | |
523224a3 | 1793 | } |
3196a88a | 1794 | |
619c5cb6 VZ |
1795 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1796 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1797 | /* q_obj->complete_cmd() failure means that this was | |
1798 | * an unexpected completion. | |
1799 | * | |
1800 | * In this case we don't want to increase the bp->spq_left | |
1801 | * because apparently we haven't sent this command the first | |
1802 | * place. | |
1803 | */ | |
1804 | #ifdef BNX2X_STOP_ON_ERROR | |
1805 | bnx2x_panic(); | |
1806 | #else | |
1807 | return; | |
1808 | #endif | |
fd1fc79d AE |
1809 | /* SRIOV: reschedule any 'in_progress' operations */ |
1810 | bnx2x_iov_sp_event(bp, cid, true); | |
619c5cb6 | 1811 | |
8fe23fbd | 1812 | smp_mb__before_atomic_inc(); |
6e30dd4e | 1813 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 VZ |
1814 | /* push the change in bp->spq_left and towards the memory */ |
1815 | smp_mb__after_atomic_inc(); | |
49d66772 | 1816 | |
d6cae238 VZ |
1817 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1818 | ||
a3348722 BW |
1819 | if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && |
1820 | (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { | |
1821 | /* if Q update ramrod is completed for last Q in AFEX vif set | |
1822 | * flow, then ACK MCP at the end | |
1823 | * | |
1824 | * mark pending ACK to MCP bit. | |
1825 | * prevent case that both bits are cleared. | |
1826 | * At the end of load/unload driver checks that | |
2de67439 | 1827 | * sp_state is cleared, and this order prevents |
a3348722 BW |
1828 | * races |
1829 | */ | |
1830 | smp_mb__before_clear_bit(); | |
1831 | set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); | |
1832 | wmb(); | |
1833 | clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
1834 | smp_mb__after_clear_bit(); | |
1835 | ||
fd1fc79d AE |
1836 | /* schedule the sp task as mcp ack is required */ |
1837 | bnx2x_schedule_sp_task(bp); | |
a3348722 BW |
1838 | } |
1839 | ||
523224a3 | 1840 | return; |
a2fbb9ea ET |
1841 | } |
1842 | ||
9f6c9258 | 1843 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1844 | { |
555f6c78 | 1845 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1846 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1847 | u16 mask; |
ca00392c | 1848 | int i; |
6383c0b3 | 1849 | u8 cos; |
a2fbb9ea | 1850 | |
34f80b04 | 1851 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1852 | if (unlikely(status == 0)) { |
1853 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1854 | return IRQ_NONE; | |
1855 | } | |
f5372251 | 1856 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1857 | |
3196a88a EG |
1858 | #ifdef BNX2X_STOP_ON_ERROR |
1859 | if (unlikely(bp->panic)) | |
1860 | return IRQ_HANDLED; | |
1861 | #endif | |
1862 | ||
ec6ba945 | 1863 | for_each_eth_queue(bp, i) { |
ca00392c | 1864 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1865 | |
55c11941 | 1866 | mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); |
ca00392c | 1867 | if (status & mask) { |
619c5cb6 | 1868 | /* Handle Rx or Tx according to SB id */ |
6383c0b3 | 1869 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 1870 | prefetch(fp->txdata_ptr[cos]->tx_cons_sb); |
523224a3 | 1871 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
54b9ddaa | 1872 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1873 | status &= ~mask; |
1874 | } | |
a2fbb9ea ET |
1875 | } |
1876 | ||
55c11941 MS |
1877 | if (CNIC_SUPPORT(bp)) { |
1878 | mask = 0x2; | |
1879 | if (status & (mask | 0x1)) { | |
1880 | struct cnic_ops *c_ops = NULL; | |
993ac7b5 | 1881 | |
ad9b4359 MC |
1882 | rcu_read_lock(); |
1883 | c_ops = rcu_dereference(bp->cnic_ops); | |
1884 | if (c_ops && (bp->cnic_eth_dev.drv_state & | |
1885 | CNIC_DRV_STATE_HANDLES_IRQ)) | |
1886 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1887 | rcu_read_unlock(); | |
993ac7b5 | 1888 | |
55c11941 MS |
1889 | status &= ~mask; |
1890 | } | |
993ac7b5 | 1891 | } |
a2fbb9ea | 1892 | |
34f80b04 | 1893 | if (unlikely(status & 0x1)) { |
fd1fc79d AE |
1894 | |
1895 | /* schedule sp task to perform default status block work, ack | |
1896 | * attentions and enable interrupts. | |
1897 | */ | |
1898 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
1899 | |
1900 | status &= ~0x1; | |
1901 | if (!status) | |
1902 | return IRQ_HANDLED; | |
1903 | } | |
1904 | ||
cdaa7cb8 VZ |
1905 | if (unlikely(status)) |
1906 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1907 | status); |
a2fbb9ea | 1908 | |
c18487ee | 1909 | return IRQ_HANDLED; |
a2fbb9ea ET |
1910 | } |
1911 | ||
c18487ee YR |
1912 | /* Link */ |
1913 | ||
1914 | /* | |
1915 | * General service functions | |
1916 | */ | |
a2fbb9ea | 1917 | |
9f6c9258 | 1918 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1919 | { |
1920 | u32 lock_status; | |
1921 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1922 | int func = BP_FUNC(bp); |
1923 | u32 hw_lock_control_reg; | |
c18487ee | 1924 | int cnt; |
a2fbb9ea | 1925 | |
c18487ee YR |
1926 | /* Validating that the resource is within range */ |
1927 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1928 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1929 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1930 | return -EINVAL; | |
1931 | } | |
a2fbb9ea | 1932 | |
4a37fb66 YG |
1933 | if (func <= 5) { |
1934 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1935 | } else { | |
1936 | hw_lock_control_reg = | |
1937 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1938 | } | |
1939 | ||
c18487ee | 1940 | /* Validating that the resource is not already taken */ |
4a37fb66 | 1941 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1942 | if (lock_status & resource_bit) { |
51c1a580 | 1943 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
c18487ee YR |
1944 | lock_status, resource_bit); |
1945 | return -EEXIST; | |
1946 | } | |
a2fbb9ea | 1947 | |
46230476 EG |
1948 | /* Try for 5 second every 5ms */ |
1949 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 1950 | /* Try to acquire the lock */ |
4a37fb66 YG |
1951 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
1952 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
1953 | if (lock_status & resource_bit) |
1954 | return 0; | |
a2fbb9ea | 1955 | |
639d65b8 | 1956 | usleep_range(5000, 10000); |
a2fbb9ea | 1957 | } |
51c1a580 | 1958 | BNX2X_ERR("Timeout\n"); |
c18487ee YR |
1959 | return -EAGAIN; |
1960 | } | |
a2fbb9ea | 1961 | |
c9ee9206 VZ |
1962 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
1963 | { | |
1964 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1965 | } | |
1966 | ||
9f6c9258 | 1967 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1968 | { |
1969 | u32 lock_status; | |
1970 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1971 | int func = BP_FUNC(bp); |
1972 | u32 hw_lock_control_reg; | |
a2fbb9ea | 1973 | |
c18487ee YR |
1974 | /* Validating that the resource is within range */ |
1975 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1976 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1977 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1978 | return -EINVAL; | |
1979 | } | |
1980 | ||
4a37fb66 YG |
1981 | if (func <= 5) { |
1982 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1983 | } else { | |
1984 | hw_lock_control_reg = | |
1985 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1986 | } | |
1987 | ||
c18487ee | 1988 | /* Validating that the resource is currently taken */ |
4a37fb66 | 1989 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1990 | if (!(lock_status & resource_bit)) { |
6bf07b8e YM |
1991 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n", |
1992 | lock_status, resource_bit); | |
c18487ee | 1993 | return -EFAULT; |
a2fbb9ea ET |
1994 | } |
1995 | ||
9f6c9258 DK |
1996 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
1997 | return 0; | |
c18487ee | 1998 | } |
a2fbb9ea | 1999 | |
4acac6a5 EG |
2000 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
2001 | { | |
2002 | /* The GPIO should be swapped if swap register is set and active */ | |
2003 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2004 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2005 | int gpio_shift = gpio_num + | |
2006 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2007 | u32 gpio_mask = (1 << gpio_shift); | |
2008 | u32 gpio_reg; | |
2009 | int value; | |
2010 | ||
2011 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2012 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2013 | return -EINVAL; | |
2014 | } | |
2015 | ||
2016 | /* read GPIO value */ | |
2017 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2018 | ||
2019 | /* get the requested pin value */ | |
2020 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
2021 | value = 1; | |
2022 | else | |
2023 | value = 0; | |
2024 | ||
2025 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); | |
2026 | ||
2027 | return value; | |
2028 | } | |
2029 | ||
17de50b7 | 2030 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
2031 | { |
2032 | /* The GPIO should be swapped if swap register is set and active */ | |
2033 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 2034 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
2035 | int gpio_shift = gpio_num + |
2036 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2037 | u32 gpio_mask = (1 << gpio_shift); | |
2038 | u32 gpio_reg; | |
a2fbb9ea | 2039 | |
c18487ee YR |
2040 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
2041 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2042 | return -EINVAL; | |
2043 | } | |
a2fbb9ea | 2044 | |
4a37fb66 | 2045 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
2046 | /* read GPIO and mask except the float bits */ |
2047 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 2048 | |
c18487ee YR |
2049 | switch (mode) { |
2050 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
51c1a580 MS |
2051 | DP(NETIF_MSG_LINK, |
2052 | "Set GPIO %d (shift %d) -> output low\n", | |
c18487ee YR |
2053 | gpio_num, gpio_shift); |
2054 | /* clear FLOAT and set CLR */ | |
2055 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2056 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
2057 | break; | |
a2fbb9ea | 2058 | |
c18487ee | 2059 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
51c1a580 MS |
2060 | DP(NETIF_MSG_LINK, |
2061 | "Set GPIO %d (shift %d) -> output high\n", | |
c18487ee YR |
2062 | gpio_num, gpio_shift); |
2063 | /* clear FLOAT and set SET */ | |
2064 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2065 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
2066 | break; | |
a2fbb9ea | 2067 | |
17de50b7 | 2068 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
51c1a580 MS |
2069 | DP(NETIF_MSG_LINK, |
2070 | "Set GPIO %d (shift %d) -> input\n", | |
c18487ee YR |
2071 | gpio_num, gpio_shift); |
2072 | /* set FLOAT */ | |
2073 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2074 | break; | |
a2fbb9ea | 2075 | |
c18487ee YR |
2076 | default: |
2077 | break; | |
a2fbb9ea ET |
2078 | } |
2079 | ||
c18487ee | 2080 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 2081 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 2082 | |
c18487ee | 2083 | return 0; |
a2fbb9ea ET |
2084 | } |
2085 | ||
0d40f0d4 YR |
2086 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
2087 | { | |
2088 | u32 gpio_reg = 0; | |
2089 | int rc = 0; | |
2090 | ||
2091 | /* Any port swapping should be handled by caller. */ | |
2092 | ||
2093 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2094 | /* read GPIO and mask except the float bits */ | |
2095 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2096 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2097 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2098 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
2099 | ||
2100 | switch (mode) { | |
2101 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
2102 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
2103 | /* set CLR */ | |
2104 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2105 | break; | |
2106 | ||
2107 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
2108 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
2109 | /* set SET */ | |
2110 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
2111 | break; | |
2112 | ||
2113 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
2114 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
2115 | /* set FLOAT */ | |
2116 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2117 | break; | |
2118 | ||
2119 | default: | |
2120 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
2121 | rc = -EINVAL; | |
2122 | break; | |
2123 | } | |
2124 | ||
2125 | if (rc == 0) | |
2126 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
2127 | ||
2128 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2129 | ||
2130 | return rc; | |
2131 | } | |
2132 | ||
4acac6a5 EG |
2133 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
2134 | { | |
2135 | /* The GPIO should be swapped if swap register is set and active */ | |
2136 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2137 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2138 | int gpio_shift = gpio_num + | |
2139 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2140 | u32 gpio_mask = (1 << gpio_shift); | |
2141 | u32 gpio_reg; | |
2142 | ||
2143 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2144 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2145 | return -EINVAL; | |
2146 | } | |
2147 | ||
2148 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2149 | /* read GPIO int */ | |
2150 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
2151 | ||
2152 | switch (mode) { | |
2153 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
51c1a580 MS |
2154 | DP(NETIF_MSG_LINK, |
2155 | "Clear GPIO INT %d (shift %d) -> output low\n", | |
2156 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2157 | /* clear SET and set CLR */ |
2158 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2159 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2160 | break; | |
2161 | ||
2162 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
51c1a580 MS |
2163 | DP(NETIF_MSG_LINK, |
2164 | "Set GPIO INT %d (shift %d) -> output high\n", | |
2165 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2166 | /* clear CLR and set SET */ |
2167 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2168 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2169 | break; | |
2170 | ||
2171 | default: | |
2172 | break; | |
2173 | } | |
2174 | ||
2175 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2176 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2177 | ||
2178 | return 0; | |
2179 | } | |
2180 | ||
d6d99a3f | 2181 | static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) |
a2fbb9ea | 2182 | { |
c18487ee | 2183 | u32 spio_reg; |
a2fbb9ea | 2184 | |
d6d99a3f YM |
2185 | /* Only 2 SPIOs are configurable */ |
2186 | if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { | |
2187 | BNX2X_ERR("Invalid SPIO 0x%x\n", spio); | |
c18487ee | 2188 | return -EINVAL; |
a2fbb9ea ET |
2189 | } |
2190 | ||
4a37fb66 | 2191 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2192 | /* read SPIO and mask except the float bits */ |
d6d99a3f | 2193 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); |
a2fbb9ea | 2194 | |
c18487ee | 2195 | switch (mode) { |
d6d99a3f YM |
2196 | case MISC_SPIO_OUTPUT_LOW: |
2197 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); | |
c18487ee | 2198 | /* clear FLOAT and set CLR */ |
d6d99a3f YM |
2199 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2200 | spio_reg |= (spio << MISC_SPIO_CLR_POS); | |
c18487ee | 2201 | break; |
a2fbb9ea | 2202 | |
d6d99a3f YM |
2203 | case MISC_SPIO_OUTPUT_HIGH: |
2204 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); | |
c18487ee | 2205 | /* clear FLOAT and set SET */ |
d6d99a3f YM |
2206 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2207 | spio_reg |= (spio << MISC_SPIO_SET_POS); | |
c18487ee | 2208 | break; |
a2fbb9ea | 2209 | |
d6d99a3f YM |
2210 | case MISC_SPIO_INPUT_HI_Z: |
2211 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); | |
c18487ee | 2212 | /* set FLOAT */ |
d6d99a3f | 2213 | spio_reg |= (spio << MISC_SPIO_FLOAT_POS); |
c18487ee | 2214 | break; |
a2fbb9ea | 2215 | |
c18487ee YR |
2216 | default: |
2217 | break; | |
a2fbb9ea ET |
2218 | } |
2219 | ||
c18487ee | 2220 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2221 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2222 | |
a2fbb9ea ET |
2223 | return 0; |
2224 | } | |
2225 | ||
9f6c9258 | 2226 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2227 | { |
a22f0788 | 2228 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
ad33ea3a EG |
2229 | switch (bp->link_vars.ieee_fc & |
2230 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2231 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: |
a22f0788 | 2232 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2233 | ADVERTISED_Pause); |
c18487ee | 2234 | break; |
356e2385 | 2235 | |
c18487ee | 2236 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2237 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2238 | ADVERTISED_Pause); |
c18487ee | 2239 | break; |
356e2385 | 2240 | |
c18487ee | 2241 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2242 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2243 | break; |
356e2385 | 2244 | |
c18487ee | 2245 | default: |
a22f0788 | 2246 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2247 | ADVERTISED_Pause); |
c18487ee YR |
2248 | break; |
2249 | } | |
2250 | } | |
f1410647 | 2251 | |
cd1dfce2 | 2252 | static void bnx2x_set_requested_fc(struct bnx2x *bp) |
c18487ee | 2253 | { |
cd1dfce2 YM |
2254 | /* Initialize link parameters structure variables |
2255 | * It is recommended to turn off RX FC for jumbo frames | |
2256 | * for better performance | |
2257 | */ | |
2258 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
2259 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; | |
2260 | else | |
2261 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; | |
2262 | } | |
a2fbb9ea | 2263 | |
9156b30b DK |
2264 | static void bnx2x_init_dropless_fc(struct bnx2x *bp) |
2265 | { | |
2266 | u32 pause_enabled = 0; | |
2267 | ||
2268 | if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { | |
2269 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2270 | pause_enabled = 1; | |
2271 | ||
2272 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
2273 | USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), | |
2274 | pause_enabled); | |
2275 | } | |
2276 | ||
2277 | DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n", | |
2278 | pause_enabled ? "enabled" : "disabled"); | |
2279 | } | |
2280 | ||
cd1dfce2 YM |
2281 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
2282 | { | |
2283 | int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); | |
2284 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
2285 | ||
2286 | if (!BP_NOMCP(bp)) { | |
2287 | bnx2x_set_requested_fc(bp); | |
4a37fb66 | 2288 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2289 | |
a22f0788 | 2290 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2291 | struct link_params *lp = &bp->link_params; |
2292 | lp->loopback_mode = LOOPBACK_XGXS; | |
2293 | /* do PHY loopback at 10G speed, if possible */ | |
2294 | if (lp->req_line_speed[cfx_idx] < SPEED_10000) { | |
2295 | if (lp->speed_cap_mask[cfx_idx] & | |
2296 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2297 | lp->req_line_speed[cfx_idx] = | |
2298 | SPEED_10000; | |
2299 | else | |
2300 | lp->req_line_speed[cfx_idx] = | |
2301 | SPEED_1000; | |
2302 | } | |
a22f0788 | 2303 | } |
b5bf9068 | 2304 | |
8970b2e4 MS |
2305 | if (load_mode == LOAD_LOOPBACK_EXT) { |
2306 | struct link_params *lp = &bp->link_params; | |
2307 | lp->loopback_mode = LOOPBACK_EXT; | |
2308 | } | |
2309 | ||
19680c48 | 2310 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2311 | |
4a37fb66 | 2312 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2313 | |
9156b30b DK |
2314 | bnx2x_init_dropless_fc(bp); |
2315 | ||
3c96c68b EG |
2316 | bnx2x_calc_fc_adv(bp); |
2317 | ||
cd1dfce2 | 2318 | if (bp->link_vars.link_up) { |
b5bf9068 | 2319 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
19680c48 | 2320 | bnx2x_link_report(bp); |
cd1dfce2 YM |
2321 | } |
2322 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2323 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2324 | return rc; |
2325 | } | |
f5372251 | 2326 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2327 | return -EINVAL; |
a2fbb9ea ET |
2328 | } |
2329 | ||
9f6c9258 | 2330 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2331 | { |
19680c48 | 2332 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2333 | bnx2x_acquire_phy_lock(bp); |
19680c48 | 2334 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2335 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2336 | |
9156b30b DK |
2337 | bnx2x_init_dropless_fc(bp); |
2338 | ||
19680c48 EG |
2339 | bnx2x_calc_fc_adv(bp); |
2340 | } else | |
f5372251 | 2341 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2342 | } |
a2fbb9ea | 2343 | |
c18487ee YR |
2344 | static void bnx2x__link_reset(struct bnx2x *bp) |
2345 | { | |
19680c48 | 2346 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2347 | bnx2x_acquire_phy_lock(bp); |
5d07d868 | 2348 | bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2349 | bnx2x_release_phy_lock(bp); |
19680c48 | 2350 | } else |
f5372251 | 2351 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2352 | } |
a2fbb9ea | 2353 | |
5d07d868 YM |
2354 | void bnx2x_force_link_reset(struct bnx2x *bp) |
2355 | { | |
2356 | bnx2x_acquire_phy_lock(bp); | |
2357 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); | |
2358 | bnx2x_release_phy_lock(bp); | |
2359 | } | |
2360 | ||
a22f0788 | 2361 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2362 | { |
2145a920 | 2363 | u8 rc = 0; |
a2fbb9ea | 2364 | |
2145a920 VZ |
2365 | if (!BP_NOMCP(bp)) { |
2366 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2367 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2368 | is_serdes); | |
2145a920 VZ |
2369 | bnx2x_release_phy_lock(bp); |
2370 | } else | |
2371 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2372 | |
c18487ee YR |
2373 | return rc; |
2374 | } | |
a2fbb9ea | 2375 | |
2691d51d EG |
2376 | /* Calculates the sum of vn_min_rates. |
2377 | It's needed for further normalizing of the min_rates. | |
2378 | Returns: | |
2379 | sum of vn_min_rates. | |
2380 | or | |
2381 | 0 - if all the min_rates are 0. | |
16a5fd92 | 2382 | In the later case fairness algorithm should be deactivated. |
2691d51d EG |
2383 | If not all min_rates are zero then those that are zeroes will be set to 1. |
2384 | */ | |
b475d78f YM |
2385 | static void bnx2x_calc_vn_min(struct bnx2x *bp, |
2386 | struct cmng_init_input *input) | |
2691d51d EG |
2387 | { |
2388 | int all_zero = 1; | |
2691d51d EG |
2389 | int vn; |
2390 | ||
3395a033 | 2391 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2392 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2393 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2394 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2395 | ||
2396 | /* Skip hidden vns */ | |
2397 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
b475d78f | 2398 | vn_min_rate = 0; |
2691d51d | 2399 | /* If min rate is zero - set it to 1 */ |
b475d78f | 2400 | else if (!vn_min_rate) |
2691d51d EG |
2401 | vn_min_rate = DEF_MIN_RATE; |
2402 | else | |
2403 | all_zero = 0; | |
2404 | ||
b475d78f | 2405 | input->vnic_min_rate[vn] = vn_min_rate; |
2691d51d EG |
2406 | } |
2407 | ||
30ae438b DK |
2408 | /* if ETS or all min rates are zeros - disable fairness */ |
2409 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
b475d78f | 2410 | input->flags.cmng_enables &= |
30ae438b DK |
2411 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2412 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2413 | } else if (all_zero) { | |
b475d78f | 2414 | input->flags.cmng_enables &= |
b015e3d1 | 2415 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
b475d78f YM |
2416 | DP(NETIF_MSG_IFUP, |
2417 | "All MIN values are zeroes fairness will be disabled\n"); | |
b015e3d1 | 2418 | } else |
b475d78f | 2419 | input->flags.cmng_enables |= |
b015e3d1 | 2420 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2691d51d EG |
2421 | } |
2422 | ||
b475d78f YM |
2423 | static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, |
2424 | struct cmng_init_input *input) | |
34f80b04 | 2425 | { |
b475d78f | 2426 | u16 vn_max_rate; |
f2e0899f | 2427 | u32 vn_cfg = bp->mf_config[vn]; |
34f80b04 | 2428 | |
b475d78f | 2429 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
34f80b04 | 2430 | vn_max_rate = 0; |
b475d78f | 2431 | else { |
faa6fcbb DK |
2432 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2433 | ||
b475d78f | 2434 | if (IS_MF_SI(bp)) { |
faa6fcbb DK |
2435 | /* maxCfg in percents of linkspeed */ |
2436 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
b475d78f | 2437 | } else /* SD modes */ |
faa6fcbb DK |
2438 | /* maxCfg is absolute in 100Mb units */ |
2439 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2440 | } |
f85582f8 | 2441 | |
b475d78f | 2442 | DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); |
34f80b04 | 2443 | |
b475d78f | 2444 | input->vnic_max_rate[vn] = vn_max_rate; |
34f80b04 | 2445 | } |
f85582f8 | 2446 | |
523224a3 DK |
2447 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2448 | { | |
2449 | if (CHIP_REV_IS_SLOW(bp)) | |
2450 | return CMNG_FNS_NONE; | |
fb3bff17 | 2451 | if (IS_MF(bp)) |
523224a3 DK |
2452 | return CMNG_FNS_MINMAX; |
2453 | ||
2454 | return CMNG_FNS_NONE; | |
2455 | } | |
2456 | ||
2ae17f66 | 2457 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2458 | { |
0793f83f | 2459 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2460 | |
2461 | if (BP_NOMCP(bp)) | |
16a5fd92 | 2462 | return; /* what should be the default value in this case */ |
523224a3 | 2463 | |
0793f83f DK |
2464 | /* For 2 port configuration the absolute function number formula |
2465 | * is: | |
2466 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2467 | * | |
2468 | * and there are 4 functions per port | |
2469 | * | |
2470 | * For 4 port configuration it is | |
2471 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2472 | * | |
2473 | * and there are 2 functions per port | |
2474 | */ | |
3395a033 | 2475 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2476 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2477 | ||
2478 | if (func >= E1H_FUNC_MAX) | |
2479 | break; | |
2480 | ||
f2e0899f | 2481 | bp->mf_config[vn] = |
523224a3 DK |
2482 | MF_CFG_RD(bp, func_mf_config[func].config); |
2483 | } | |
a3348722 BW |
2484 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
2485 | DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); | |
2486 | bp->flags |= MF_FUNC_DIS; | |
2487 | } else { | |
2488 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2489 | bp->flags &= ~MF_FUNC_DIS; | |
2490 | } | |
523224a3 DK |
2491 | } |
2492 | ||
2493 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2494 | { | |
b475d78f YM |
2495 | struct cmng_init_input input; |
2496 | memset(&input, 0, sizeof(struct cmng_init_input)); | |
2497 | ||
2498 | input.port_rate = bp->link_vars.line_speed; | |
523224a3 | 2499 | |
568e2426 | 2500 | if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) { |
523224a3 DK |
2501 | int vn; |
2502 | ||
523224a3 DK |
2503 | /* read mf conf from shmem */ |
2504 | if (read_cfg) | |
2505 | bnx2x_read_mf_cfg(bp); | |
2506 | ||
523224a3 | 2507 | /* vn_weight_sum and enable fairness if not 0 */ |
b475d78f | 2508 | bnx2x_calc_vn_min(bp, &input); |
523224a3 DK |
2509 | |
2510 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2511 | if (bp->port.pmf) |
3395a033 | 2512 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
b475d78f | 2513 | bnx2x_calc_vn_max(bp, vn, &input); |
523224a3 DK |
2514 | |
2515 | /* always enable rate shaping and fairness */ | |
b475d78f | 2516 | input.flags.cmng_enables |= |
523224a3 | 2517 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; |
b475d78f YM |
2518 | |
2519 | bnx2x_init_cmng(&input, &bp->cmng); | |
523224a3 DK |
2520 | return; |
2521 | } | |
2522 | ||
2523 | /* rate shaping and fairness are disabled */ | |
2524 | DP(NETIF_MSG_IFUP, | |
2525 | "rate shaping and fairness are disabled\n"); | |
2526 | } | |
34f80b04 | 2527 | |
1191cb83 ED |
2528 | static void storm_memset_cmng(struct bnx2x *bp, |
2529 | struct cmng_init *cmng, | |
2530 | u8 port) | |
2531 | { | |
2532 | int vn; | |
2533 | size_t size = sizeof(struct cmng_struct_per_port); | |
2534 | ||
2535 | u32 addr = BAR_XSTRORM_INTMEM + | |
2536 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
2537 | ||
2538 | __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); | |
2539 | ||
2540 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
2541 | int func = func_by_vn(bp, vn); | |
2542 | ||
2543 | addr = BAR_XSTRORM_INTMEM + | |
2544 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); | |
2545 | size = sizeof(struct rate_shaping_vars_per_vn); | |
2546 | __storm_memset_struct(bp, addr, size, | |
2547 | (u32 *)&cmng->vnic.vnic_max_rate[vn]); | |
2548 | ||
2549 | addr = BAR_XSTRORM_INTMEM + | |
2550 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); | |
2551 | size = sizeof(struct fairness_vars_per_vn); | |
2552 | __storm_memset_struct(bp, addr, size, | |
2553 | (u32 *)&cmng->vnic.vnic_min_rate[vn]); | |
2554 | } | |
2555 | } | |
2556 | ||
568e2426 DK |
2557 | /* init cmng mode in HW according to local configuration */ |
2558 | void bnx2x_set_local_cmng(struct bnx2x *bp) | |
2559 | { | |
2560 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
2561 | ||
2562 | if (cmng_fns != CMNG_FNS_NONE) { | |
2563 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2564 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2565 | } else { | |
2566 | /* rate shaping and fairness are disabled */ | |
2567 | DP(NETIF_MSG_IFUP, | |
2568 | "single function mode without fairness\n"); | |
2569 | } | |
2570 | } | |
2571 | ||
c18487ee YR |
2572 | /* This function is called upon link interrupt */ |
2573 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2574 | { | |
bb2a0f7a YG |
2575 | /* Make sure that we are synced with the current statistics */ |
2576 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2577 | ||
c18487ee | 2578 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2579 | |
9156b30b | 2580 | bnx2x_init_dropless_fc(bp); |
1c06328c | 2581 | |
9156b30b | 2582 | if (bp->link_vars.link_up) { |
1c06328c | 2583 | |
619c5cb6 | 2584 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2585 | struct host_port_stats *pstats; |
2586 | ||
2587 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2588 | /* reset old mac stats */ |
bb2a0f7a YG |
2589 | memset(&(pstats->mac_stx[0]), 0, |
2590 | sizeof(struct mac_stx)); | |
2591 | } | |
f34d28ea | 2592 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2593 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2594 | } | |
2595 | ||
568e2426 DK |
2596 | if (bp->link_vars.link_up && bp->link_vars.line_speed) |
2597 | bnx2x_set_local_cmng(bp); | |
9fdc3e95 | 2598 | |
2ae17f66 VZ |
2599 | __bnx2x_link_report(bp); |
2600 | ||
9fdc3e95 DK |
2601 | if (IS_MF(bp)) |
2602 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2603 | } |
a2fbb9ea | 2604 | |
9f6c9258 | 2605 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2606 | { |
2ae17f66 | 2607 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2608 | return; |
a2fbb9ea | 2609 | |
00253a8c | 2610 | /* read updated dcb configuration */ |
ad5afc89 AE |
2611 | if (IS_PF(bp)) { |
2612 | bnx2x_dcbx_pmf_update(bp); | |
2613 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); | |
2614 | if (bp->link_vars.link_up) | |
2615 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2616 | else | |
2617 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2618 | /* indicate link status */ | |
2619 | bnx2x_link_report(bp); | |
a2fbb9ea | 2620 | |
ad5afc89 AE |
2621 | } else { /* VF */ |
2622 | bp->port.supported[0] |= (SUPPORTED_10baseT_Half | | |
2623 | SUPPORTED_10baseT_Full | | |
2624 | SUPPORTED_100baseT_Half | | |
2625 | SUPPORTED_100baseT_Full | | |
2626 | SUPPORTED_1000baseT_Full | | |
2627 | SUPPORTED_2500baseX_Full | | |
2628 | SUPPORTED_10000baseT_Full | | |
2629 | SUPPORTED_TP | | |
2630 | SUPPORTED_FIBRE | | |
2631 | SUPPORTED_Autoneg | | |
2632 | SUPPORTED_Pause | | |
2633 | SUPPORTED_Asym_Pause); | |
2634 | bp->port.advertising[0] = bp->port.supported[0]; | |
2635 | ||
2636 | bp->link_params.bp = bp; | |
2637 | bp->link_params.port = BP_PORT(bp); | |
2638 | bp->link_params.req_duplex[0] = DUPLEX_FULL; | |
2639 | bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; | |
2640 | bp->link_params.req_line_speed[0] = SPEED_10000; | |
2641 | bp->link_params.speed_cap_mask[0] = 0x7f0000; | |
2642 | bp->link_params.switch_cfg = SWITCH_CFG_10G; | |
2643 | bp->link_vars.mac_type = MAC_TYPE_BMAC; | |
2644 | bp->link_vars.line_speed = SPEED_10000; | |
2645 | bp->link_vars.link_status = | |
2646 | (LINK_STATUS_LINK_UP | | |
2647 | LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); | |
2648 | bp->link_vars.link_up = 1; | |
2649 | bp->link_vars.duplex = DUPLEX_FULL; | |
2650 | bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
2651 | __bnx2x_link_report(bp); | |
bb2a0f7a | 2652 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
ad5afc89 | 2653 | } |
a2fbb9ea | 2654 | } |
a2fbb9ea | 2655 | |
a3348722 BW |
2656 | static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, |
2657 | u16 vlan_val, u8 allowed_prio) | |
2658 | { | |
86564c3f | 2659 | struct bnx2x_func_state_params func_params = {NULL}; |
a3348722 BW |
2660 | struct bnx2x_func_afex_update_params *f_update_params = |
2661 | &func_params.params.afex_update; | |
2662 | ||
2663 | func_params.f_obj = &bp->func_obj; | |
2664 | func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; | |
2665 | ||
2666 | /* no need to wait for RAMROD completion, so don't | |
2667 | * set RAMROD_COMP_WAIT flag | |
2668 | */ | |
2669 | ||
2670 | f_update_params->vif_id = vifid; | |
2671 | f_update_params->afex_default_vlan = vlan_val; | |
2672 | f_update_params->allowed_priorities = allowed_prio; | |
2673 | ||
2674 | /* if ramrod can not be sent, response to MCP immediately */ | |
2675 | if (bnx2x_func_state_change(bp, &func_params) < 0) | |
2676 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
2677 | ||
2678 | return 0; | |
2679 | } | |
2680 | ||
2681 | static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, | |
2682 | u16 vif_index, u8 func_bit_map) | |
2683 | { | |
86564c3f | 2684 | struct bnx2x_func_state_params func_params = {NULL}; |
a3348722 BW |
2685 | struct bnx2x_func_afex_viflists_params *update_params = |
2686 | &func_params.params.afex_viflists; | |
2687 | int rc; | |
2688 | u32 drv_msg_code; | |
2689 | ||
2690 | /* validate only LIST_SET and LIST_GET are received from switch */ | |
2691 | if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) | |
2692 | BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", | |
2693 | cmd_type); | |
2694 | ||
2695 | func_params.f_obj = &bp->func_obj; | |
2696 | func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; | |
2697 | ||
2698 | /* set parameters according to cmd_type */ | |
2699 | update_params->afex_vif_list_command = cmd_type; | |
86564c3f | 2700 | update_params->vif_list_index = vif_index; |
a3348722 BW |
2701 | update_params->func_bit_map = |
2702 | (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; | |
2703 | update_params->func_to_clear = 0; | |
2704 | drv_msg_code = | |
2705 | (cmd_type == VIF_LIST_RULE_GET) ? | |
2706 | DRV_MSG_CODE_AFEX_LISTGET_ACK : | |
2707 | DRV_MSG_CODE_AFEX_LISTSET_ACK; | |
2708 | ||
2709 | /* if ramrod can not be sent, respond to MCP immediately for | |
2710 | * SET and GET requests (other are not triggered from MCP) | |
2711 | */ | |
2712 | rc = bnx2x_func_state_change(bp, &func_params); | |
2713 | if (rc < 0) | |
2714 | bnx2x_fw_command(bp, drv_msg_code, 0); | |
2715 | ||
2716 | return 0; | |
2717 | } | |
2718 | ||
2719 | static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) | |
2720 | { | |
2721 | struct afex_stats afex_stats; | |
2722 | u32 func = BP_ABS_FUNC(bp); | |
2723 | u32 mf_config; | |
2724 | u16 vlan_val; | |
2725 | u32 vlan_prio; | |
2726 | u16 vif_id; | |
2727 | u8 allowed_prio; | |
2728 | u8 vlan_mode; | |
2729 | u32 addr_to_write, vifid, addrs, stats_type, i; | |
2730 | ||
2731 | if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { | |
2732 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2733 | DP(BNX2X_MSG_MCP, | |
2734 | "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); | |
2735 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); | |
2736 | } | |
2737 | ||
2738 | if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { | |
2739 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2740 | addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); | |
2741 | DP(BNX2X_MSG_MCP, | |
2742 | "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", | |
2743 | vifid, addrs); | |
2744 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, | |
2745 | addrs); | |
2746 | } | |
2747 | ||
2748 | if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { | |
2749 | addr_to_write = SHMEM2_RD(bp, | |
2750 | afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); | |
2751 | stats_type = SHMEM2_RD(bp, | |
2752 | afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2753 | ||
2754 | DP(BNX2X_MSG_MCP, | |
2755 | "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", | |
2756 | addr_to_write); | |
2757 | ||
2758 | bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); | |
2759 | ||
2760 | /* write response to scratchpad, for MCP */ | |
2761 | for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) | |
2762 | REG_WR(bp, addr_to_write + i*sizeof(u32), | |
2763 | *(((u32 *)(&afex_stats))+i)); | |
2764 | ||
2765 | /* send ack message to MCP */ | |
2766 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); | |
2767 | } | |
2768 | ||
2769 | if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { | |
2770 | mf_config = MF_CFG_RD(bp, func_mf_config[func].config); | |
2771 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2772 | DP(BNX2X_MSG_MCP, | |
2773 | "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", | |
2774 | mf_config); | |
2775 | ||
2776 | /* if VIF_SET is "enabled" */ | |
2777 | if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { | |
2778 | /* set rate limit directly to internal RAM */ | |
2779 | struct cmng_init_input cmng_input; | |
2780 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2781 | size_t size = sizeof(struct rate_shaping_vars_per_vn); | |
2782 | u32 addr = BAR_XSTRORM_INTMEM + | |
2783 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); | |
2784 | ||
2785 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2786 | ||
2787 | bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); | |
2788 | m_rs_vn.vn_counter.rate = | |
2789 | cmng_input.vnic_max_rate[BP_VN(bp)]; | |
2790 | m_rs_vn.vn_counter.quota = | |
2791 | (m_rs_vn.vn_counter.rate * | |
2792 | RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2793 | ||
2794 | __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); | |
2795 | ||
2796 | /* read relevant values from mf_cfg struct in shmem */ | |
2797 | vif_id = | |
2798 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2799 | FUNC_MF_CFG_E1HOV_TAG_MASK) >> | |
2800 | FUNC_MF_CFG_E1HOV_TAG_SHIFT; | |
2801 | vlan_val = | |
2802 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2803 | FUNC_MF_CFG_AFEX_VLAN_MASK) >> | |
2804 | FUNC_MF_CFG_AFEX_VLAN_SHIFT; | |
2805 | vlan_prio = (mf_config & | |
2806 | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> | |
2807 | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; | |
2808 | vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); | |
2809 | vlan_mode = | |
2810 | (MF_CFG_RD(bp, | |
2811 | func_mf_config[func].afex_config) & | |
2812 | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> | |
2813 | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; | |
2814 | allowed_prio = | |
2815 | (MF_CFG_RD(bp, | |
2816 | func_mf_config[func].afex_config) & | |
2817 | FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> | |
2818 | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; | |
2819 | ||
2820 | /* send ramrod to FW, return in case of failure */ | |
2821 | if (bnx2x_afex_func_update(bp, vif_id, vlan_val, | |
2822 | allowed_prio)) | |
2823 | return; | |
2824 | ||
2825 | bp->afex_def_vlan_tag = vlan_val; | |
2826 | bp->afex_vlan_mode = vlan_mode; | |
2827 | } else { | |
2828 | /* notify link down because BP->flags is disabled */ | |
2829 | bnx2x_link_report(bp); | |
2830 | ||
2831 | /* send INVALID VIF ramrod to FW */ | |
2832 | bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); | |
2833 | ||
2834 | /* Reset the default afex VLAN */ | |
2835 | bp->afex_def_vlan_tag = -1; | |
2836 | } | |
2837 | } | |
2838 | } | |
2839 | ||
34f80b04 EG |
2840 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2841 | { | |
2842 | int port = BP_PORT(bp); | |
2843 | u32 val; | |
2844 | ||
2845 | bp->port.pmf = 1; | |
51c1a580 | 2846 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
34f80b04 | 2847 | |
3deb8167 YR |
2848 | /* |
2849 | * We need the mb() to ensure the ordering between the writing to | |
2850 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2851 | */ | |
2852 | smp_mb(); | |
2853 | ||
2854 | /* queue a periodic task */ | |
2855 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2856 | ||
ef01854e DK |
2857 | bnx2x_dcbx_pmf_update(bp); |
2858 | ||
34f80b04 | 2859 | /* enable nig attention */ |
3395a033 | 2860 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
2861 | if (bp->common.int_block == INT_BLOCK_HC) { |
2862 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2863 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2864 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2865 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2866 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2867 | } | |
bb2a0f7a YG |
2868 | |
2869 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2870 | } |
2871 | ||
c18487ee | 2872 | /* end of Link */ |
a2fbb9ea ET |
2873 | |
2874 | /* slow path */ | |
2875 | ||
2876 | /* | |
2877 | * General service functions | |
2878 | */ | |
2879 | ||
2691d51d | 2880 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 2881 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 2882 | { |
f2e0899f | 2883 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 2884 | u32 seq; |
2691d51d EG |
2885 | u32 rc = 0; |
2886 | u32 cnt = 1; | |
2887 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
2888 | ||
c4ff7cbf | 2889 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 2890 | seq = ++bp->fw_seq; |
f2e0899f DK |
2891 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
2892 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
2893 | ||
754a2f52 DK |
2894 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
2895 | (command | seq), param); | |
2691d51d EG |
2896 | |
2897 | do { | |
2898 | /* let the FW do it's magic ... */ | |
2899 | msleep(delay); | |
2900 | ||
f2e0899f | 2901 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 2902 | |
c4ff7cbf EG |
2903 | /* Give the FW up to 5 second (500*10ms) */ |
2904 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
2905 | |
2906 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
2907 | cnt*delay, rc, seq); | |
2908 | ||
2909 | /* is this a reply to our command? */ | |
2910 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
2911 | rc &= FW_MSG_CODE_MASK; | |
2912 | else { | |
2913 | /* FW BUG! */ | |
2914 | BNX2X_ERR("FW failed to respond!\n"); | |
2915 | bnx2x_fw_dump(bp); | |
2916 | rc = 0; | |
2917 | } | |
c4ff7cbf | 2918 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
2919 | |
2920 | return rc; | |
2921 | } | |
2922 | ||
1191cb83 ED |
2923 | static void storm_memset_func_cfg(struct bnx2x *bp, |
2924 | struct tstorm_eth_function_common_config *tcfg, | |
2925 | u16 abs_fid) | |
2926 | { | |
2927 | size_t size = sizeof(struct tstorm_eth_function_common_config); | |
2928 | ||
2929 | u32 addr = BAR_TSTRORM_INTMEM + | |
2930 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); | |
2931 | ||
2932 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); | |
2933 | } | |
2934 | ||
619c5cb6 VZ |
2935 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
2936 | { | |
2937 | if (CHIP_IS_E1x(bp)) { | |
2938 | struct tstorm_eth_function_common_config tcfg = {0}; | |
2939 | ||
2940 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
2941 | } | |
2942 | ||
2943 | /* Enable the function in the FW */ | |
2944 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
2945 | storm_memset_func_en(bp, p->func_id, 1); | |
2946 | ||
2947 | /* spq */ | |
2948 | if (p->func_flgs & FUNC_FLG_SPQ) { | |
2949 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); | |
2950 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
2951 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
2952 | } | |
2953 | } | |
2954 | ||
6383c0b3 | 2955 | /** |
16a5fd92 | 2956 | * bnx2x_get_common_flags - Return common flags |
6383c0b3 AE |
2957 | * |
2958 | * @bp device handle | |
2959 | * @fp queue handle | |
2960 | * @zero_stats TRUE if statistics zeroing is needed | |
2961 | * | |
2962 | * Return the flags that are common for the Tx-only and not normal connections. | |
2963 | */ | |
1191cb83 ED |
2964 | static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, |
2965 | struct bnx2x_fastpath *fp, | |
2966 | bool zero_stats) | |
28912902 | 2967 | { |
619c5cb6 VZ |
2968 | unsigned long flags = 0; |
2969 | ||
2970 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
2971 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 2972 | |
6383c0b3 | 2973 | /* tx only connections collect statistics (on the same index as the |
91226790 DK |
2974 | * parent connection). The statistics are zeroed when the parent |
2975 | * connection is initialized. | |
6383c0b3 | 2976 | */ |
50f0a562 BW |
2977 | |
2978 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
2979 | if (zero_stats) | |
2980 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
2981 | ||
91226790 | 2982 | __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags); |
e287a75c | 2983 | __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags); |
6383c0b3 | 2984 | |
823e1d90 YM |
2985 | #ifdef BNX2X_STOP_ON_ERROR |
2986 | __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); | |
2987 | #endif | |
2988 | ||
6383c0b3 AE |
2989 | return flags; |
2990 | } | |
2991 | ||
1191cb83 ED |
2992 | static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, |
2993 | struct bnx2x_fastpath *fp, | |
2994 | bool leading) | |
6383c0b3 AE |
2995 | { |
2996 | unsigned long flags = 0; | |
2997 | ||
619c5cb6 VZ |
2998 | /* calculate other queue flags */ |
2999 | if (IS_MF_SD(bp)) | |
3000 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 3001 | |
a3348722 | 3002 | if (IS_FCOE_FP(fp)) { |
619c5cb6 | 3003 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); |
a3348722 BW |
3004 | /* For FCoE - force usage of default priority (for afex) */ |
3005 | __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); | |
3006 | } | |
523224a3 | 3007 | |
f5219d8e | 3008 | if (!fp->disable_tpa) { |
619c5cb6 | 3009 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e | 3010 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
621b4d66 DK |
3011 | if (fp->mode == TPA_MODE_GRO) |
3012 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); | |
f5219d8e | 3013 | } |
619c5cb6 | 3014 | |
619c5cb6 VZ |
3015 | if (leading) { |
3016 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
3017 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
3018 | } | |
523224a3 | 3019 | |
619c5cb6 VZ |
3020 | /* Always set HW VLAN stripping */ |
3021 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 3022 | |
a3348722 BW |
3023 | /* configure silent vlan removal */ |
3024 | if (IS_MF_AFEX(bp)) | |
3025 | __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); | |
3026 | ||
6383c0b3 | 3027 | return flags | bnx2x_get_common_flags(bp, fp, true); |
523224a3 DK |
3028 | } |
3029 | ||
619c5cb6 | 3030 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
3031 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
3032 | u8 cos) | |
619c5cb6 VZ |
3033 | { |
3034 | gen_init->stat_id = bnx2x_stats_id(fp); | |
3035 | gen_init->spcl_id = fp->cl_id; | |
3036 | ||
3037 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
3038 | if (IS_FCOE_FP(fp)) | |
3039 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
3040 | else | |
3041 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
3042 | |
3043 | gen_init->cos = cos; | |
619c5cb6 VZ |
3044 | } |
3045 | ||
3046 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 3047 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 3048 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 3049 | { |
619c5cb6 | 3050 | u8 max_sge = 0; |
523224a3 DK |
3051 | u16 sge_sz = 0; |
3052 | u16 tpa_agg_size = 0; | |
3053 | ||
523224a3 | 3054 | if (!fp->disable_tpa) { |
dfacf138 DK |
3055 | pause->sge_th_lo = SGE_TH_LO(bp); |
3056 | pause->sge_th_hi = SGE_TH_HI(bp); | |
3057 | ||
3058 | /* validate SGE ring has enough to cross high threshold */ | |
3059 | WARN_ON(bp->dropless_fc && | |
3060 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
3061 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
3062 | ||
924d75ab | 3063 | tpa_agg_size = TPA_AGG_SIZE; |
523224a3 DK |
3064 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> |
3065 | SGE_PAGE_SHIFT; | |
3066 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
3067 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
924d75ab | 3068 | sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); |
523224a3 DK |
3069 | } |
3070 | ||
3071 | /* pause - not for e1 */ | |
3072 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
3073 | pause->bd_th_lo = BD_TH_LO(bp); |
3074 | pause->bd_th_hi = BD_TH_HI(bp); | |
3075 | ||
3076 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
3077 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
3078 | /* | |
3079 | * validate that rings have enough entries to cross | |
3080 | * high thresholds | |
3081 | */ | |
3082 | WARN_ON(bp->dropless_fc && | |
3083 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
3084 | bp->rx_ring_size); | |
3085 | WARN_ON(bp->dropless_fc && | |
3086 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
3087 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 3088 | |
523224a3 DK |
3089 | pause->pri_map = 1; |
3090 | } | |
3091 | ||
3092 | /* rxq setup */ | |
523224a3 DK |
3093 | rxq_init->dscr_map = fp->rx_desc_mapping; |
3094 | rxq_init->sge_map = fp->rx_sge_mapping; | |
3095 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
3096 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 3097 | |
619c5cb6 VZ |
3098 | /* This should be a maximum number of data bytes that may be |
3099 | * placed on the BD (not including paddings). | |
3100 | */ | |
e52fcb24 | 3101 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
3cdeec22 | 3102 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; |
a8c94b91 | 3103 | |
523224a3 | 3104 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
3105 | rxq_init->tpa_agg_sz = tpa_agg_size; |
3106 | rxq_init->sge_buf_sz = sge_sz; | |
3107 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 | 3108 | rxq_init->rss_engine_id = BP_FUNC(bp); |
259afa1f | 3109 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
619c5cb6 VZ |
3110 | |
3111 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
3112 | * | |
2de67439 | 3113 | * For PF Clients it should be the maximum available number. |
619c5cb6 VZ |
3114 | * VF driver(s) may want to define it to a smaller value. |
3115 | */ | |
dfacf138 | 3116 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 3117 | |
523224a3 DK |
3118 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
3119 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
3120 | ||
ec6ba945 VZ |
3121 | if (IS_FCOE_FP(fp)) |
3122 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
3123 | else | |
6383c0b3 | 3124 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
a3348722 BW |
3125 | /* configure silent vlan removal |
3126 | * if multi function mode is afex, then mask default vlan | |
3127 | */ | |
3128 | if (IS_MF_AFEX(bp)) { | |
3129 | rxq_init->silent_removal_value = bp->afex_def_vlan_tag; | |
3130 | rxq_init->silent_removal_mask = VLAN_VID_MASK; | |
3131 | } | |
523224a3 DK |
3132 | } |
3133 | ||
619c5cb6 | 3134 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
3135 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
3136 | u8 cos) | |
523224a3 | 3137 | { |
65565884 | 3138 | txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; |
6383c0b3 | 3139 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; |
523224a3 DK |
3140 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
3141 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 3142 | |
619c5cb6 | 3143 | /* |
16a5fd92 | 3144 | * set the tss leading client id for TX classification == |
619c5cb6 VZ |
3145 | * leading RSS client id |
3146 | */ | |
3147 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
3148 | ||
ec6ba945 VZ |
3149 | if (IS_FCOE_FP(fp)) { |
3150 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
3151 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
3152 | } | |
523224a3 DK |
3153 | } |
3154 | ||
8d96286a | 3155 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
3156 | { |
3157 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 DK |
3158 | struct event_ring_data eq_data = { {0} }; |
3159 | u16 flags; | |
3160 | ||
619c5cb6 | 3161 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
3162 | /* reset IGU PF statistics: MSIX + ATTN */ |
3163 | /* PF */ | |
3164 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3165 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3166 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3167 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3168 | /* ATTN */ | |
3169 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3170 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3171 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
3172 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3173 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3174 | } | |
3175 | ||
523224a3 DK |
3176 | /* function setup flags */ |
3177 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | |
3178 | ||
619c5cb6 VZ |
3179 | /* This flag is relevant for E1x only. |
3180 | * E2 doesn't have a TPA configuration in a function level. | |
523224a3 | 3181 | */ |
619c5cb6 | 3182 | flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; |
523224a3 DK |
3183 | |
3184 | func_init.func_flgs = flags; | |
3185 | func_init.pf_id = BP_FUNC(bp); | |
3186 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
3187 | func_init.spq_map = bp->spq_mapping; |
3188 | func_init.spq_prod = bp->spq_prod_idx; | |
3189 | ||
3190 | bnx2x_func_init(bp, &func_init); | |
3191 | ||
3192 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
3193 | ||
3194 | /* | |
619c5cb6 VZ |
3195 | * Congestion management values depend on the link rate |
3196 | * There is no active link so initial link rate is set to 10 Gbps. | |
3197 | * When the link comes up The congestion management values are | |
3198 | * re-calculated according to the actual link rate. | |
3199 | */ | |
523224a3 DK |
3200 | bp->link_vars.line_speed = SPEED_10000; |
3201 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
3202 | ||
3203 | /* Only the PMF sets the HW */ | |
3204 | if (bp->port.pmf) | |
3205 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3206 | ||
86564c3f | 3207 | /* init Event Queue - PCI bus guarantees correct endianity*/ |
523224a3 DK |
3208 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); |
3209 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
3210 | eq_data.producer = bp->eq_prod; | |
3211 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
3212 | eq_data.sb_id = DEF_SB_ID; | |
3213 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
3214 | } | |
3215 | ||
523224a3 DK |
3216 | static void bnx2x_e1h_disable(struct bnx2x *bp) |
3217 | { | |
3218 | int port = BP_PORT(bp); | |
3219 | ||
619c5cb6 | 3220 | bnx2x_tx_disable(bp); |
523224a3 DK |
3221 | |
3222 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
3223 | } |
3224 | ||
3225 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
3226 | { | |
3227 | int port = BP_PORT(bp); | |
3228 | ||
3229 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); | |
3230 | ||
16a5fd92 | 3231 | /* Tx queue should be only re-enabled */ |
523224a3 DK |
3232 | netif_tx_wake_all_queues(bp->dev); |
3233 | ||
3234 | /* | |
3235 | * Should not call netif_carrier_on since it will be called if the link | |
3236 | * is up when checking for link state | |
3237 | */ | |
3238 | } | |
3239 | ||
1d187b34 BW |
3240 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
3241 | ||
3242 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) | |
3243 | { | |
3244 | struct eth_stats_info *ether_stat = | |
3245 | &bp->slowpath->drv_info_to_mcp.ether_stat; | |
3ec9f9ca AE |
3246 | struct bnx2x_vlan_mac_obj *mac_obj = |
3247 | &bp->sp_objs->mac_obj; | |
3248 | int i; | |
1d187b34 | 3249 | |
786fdf0b DC |
3250 | strlcpy(ether_stat->version, DRV_MODULE_VERSION, |
3251 | ETH_STAT_INFO_VERSION_LEN); | |
1d187b34 | 3252 | |
3ec9f9ca AE |
3253 | /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the |
3254 | * mac_local field in ether_stat struct. The base address is offset by 2 | |
3255 | * bytes to account for the field being 8 bytes but a mac address is | |
3256 | * only 6 bytes. Likewise, the stride for the get_n_elements function is | |
3257 | * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes | |
3258 | * allocated by the ether_stat struct, so the macs will land in their | |
3259 | * proper positions. | |
3260 | */ | |
3261 | for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) | |
3262 | memset(ether_stat->mac_local + i, 0, | |
3263 | sizeof(ether_stat->mac_local[0])); | |
3264 | mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, | |
3265 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | |
3266 | ether_stat->mac_local + MAC_PAD, MAC_PAD, | |
3267 | ETH_ALEN); | |
1d187b34 | 3268 | ether_stat->mtu_size = bp->dev->mtu; |
1d187b34 BW |
3269 | if (bp->dev->features & NETIF_F_RXCSUM) |
3270 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | |
3271 | if (bp->dev->features & NETIF_F_TSO) | |
3272 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; | |
3273 | ether_stat->feature_flags |= bp->common.boot_mode; | |
3274 | ||
3275 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; | |
3276 | ||
3277 | ether_stat->txq_size = bp->tx_ring_size; | |
3278 | ether_stat->rxq_size = bp->rx_ring_size; | |
3279 | } | |
3280 | ||
3281 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) | |
3282 | { | |
3283 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3284 | struct fcoe_stats_info *fcoe_stat = | |
3285 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; | |
3286 | ||
55c11941 MS |
3287 | if (!CNIC_LOADED(bp)) |
3288 | return; | |
3289 | ||
3ec9f9ca | 3290 | memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); |
1d187b34 BW |
3291 | |
3292 | fcoe_stat->qos_priority = | |
3293 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | |
3294 | ||
3295 | /* insert FCoE stats from ramrod response */ | |
3296 | if (!NO_FCOE(bp)) { | |
3297 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = | |
65565884 | 3298 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3299 | tstorm_queue_statistics; |
3300 | ||
3301 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = | |
65565884 | 3302 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3303 | xstorm_queue_statistics; |
3304 | ||
3305 | struct fcoe_statistics_params *fw_fcoe_stat = | |
3306 | &bp->fw_stats_data->fcoe; | |
3307 | ||
86564c3f YM |
3308 | ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, |
3309 | fcoe_stat->rx_bytes_lo, | |
3310 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); | |
1d187b34 | 3311 | |
86564c3f YM |
3312 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3313 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, | |
3314 | fcoe_stat->rx_bytes_lo, | |
3315 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); | |
1d187b34 | 3316 | |
86564c3f YM |
3317 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3318 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, | |
3319 | fcoe_stat->rx_bytes_lo, | |
3320 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); | |
1d187b34 | 3321 | |
86564c3f YM |
3322 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3323 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, | |
3324 | fcoe_stat->rx_bytes_lo, | |
3325 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); | |
1d187b34 | 3326 | |
86564c3f YM |
3327 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3328 | fcoe_stat->rx_frames_lo, | |
3329 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); | |
1d187b34 | 3330 | |
86564c3f YM |
3331 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3332 | fcoe_stat->rx_frames_lo, | |
3333 | fcoe_q_tstorm_stats->rcv_ucast_pkts); | |
1d187b34 | 3334 | |
86564c3f YM |
3335 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3336 | fcoe_stat->rx_frames_lo, | |
3337 | fcoe_q_tstorm_stats->rcv_bcast_pkts); | |
1d187b34 | 3338 | |
86564c3f YM |
3339 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3340 | fcoe_stat->rx_frames_lo, | |
3341 | fcoe_q_tstorm_stats->rcv_mcast_pkts); | |
1d187b34 | 3342 | |
86564c3f YM |
3343 | ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, |
3344 | fcoe_stat->tx_bytes_lo, | |
3345 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); | |
1d187b34 | 3346 | |
86564c3f YM |
3347 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3348 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, | |
3349 | fcoe_stat->tx_bytes_lo, | |
3350 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); | |
1d187b34 | 3351 | |
86564c3f YM |
3352 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3353 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, | |
3354 | fcoe_stat->tx_bytes_lo, | |
3355 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); | |
1d187b34 | 3356 | |
86564c3f YM |
3357 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3358 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, | |
3359 | fcoe_stat->tx_bytes_lo, | |
3360 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); | |
1d187b34 | 3361 | |
86564c3f YM |
3362 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3363 | fcoe_stat->tx_frames_lo, | |
3364 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); | |
1d187b34 | 3365 | |
86564c3f YM |
3366 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3367 | fcoe_stat->tx_frames_lo, | |
3368 | fcoe_q_xstorm_stats->ucast_pkts_sent); | |
1d187b34 | 3369 | |
86564c3f YM |
3370 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3371 | fcoe_stat->tx_frames_lo, | |
3372 | fcoe_q_xstorm_stats->bcast_pkts_sent); | |
1d187b34 | 3373 | |
86564c3f YM |
3374 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3375 | fcoe_stat->tx_frames_lo, | |
3376 | fcoe_q_xstorm_stats->mcast_pkts_sent); | |
1d187b34 BW |
3377 | } |
3378 | ||
1d187b34 BW |
3379 | /* ask L5 driver to add data to the struct */ |
3380 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); | |
1d187b34 BW |
3381 | } |
3382 | ||
3383 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) | |
3384 | { | |
3385 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3386 | struct iscsi_stats_info *iscsi_stat = | |
3387 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; | |
3388 | ||
55c11941 MS |
3389 | if (!CNIC_LOADED(bp)) |
3390 | return; | |
3391 | ||
3ec9f9ca AE |
3392 | memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, |
3393 | ETH_ALEN); | |
1d187b34 BW |
3394 | |
3395 | iscsi_stat->qos_priority = | |
3396 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | |
3397 | ||
1d187b34 BW |
3398 | /* ask L5 driver to add data to the struct */ |
3399 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); | |
1d187b34 BW |
3400 | } |
3401 | ||
0793f83f DK |
3402 | /* called due to MCP event (on pmf): |
3403 | * reread new bandwidth configuration | |
3404 | * configure FW | |
3405 | * notify others function about the change | |
3406 | */ | |
1191cb83 | 3407 | static void bnx2x_config_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3408 | { |
3409 | if (bp->link_vars.link_up) { | |
3410 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
3411 | bnx2x_link_sync_notify(bp); | |
3412 | } | |
3413 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3414 | } | |
3415 | ||
1191cb83 | 3416 | static void bnx2x_set_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3417 | { |
3418 | bnx2x_config_mf_bw(bp); | |
3419 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
3420 | } | |
3421 | ||
c8c60d88 YM |
3422 | static void bnx2x_handle_eee_event(struct bnx2x *bp) |
3423 | { | |
3424 | DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); | |
3425 | bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); | |
3426 | } | |
3427 | ||
1d187b34 BW |
3428 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
3429 | { | |
3430 | enum drv_info_opcode op_code; | |
3431 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); | |
3432 | ||
3433 | /* if drv_info version supported by MFW doesn't match - send NACK */ | |
3434 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { | |
3435 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3436 | return; | |
3437 | } | |
3438 | ||
3439 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> | |
3440 | DRV_INFO_CONTROL_OP_CODE_SHIFT; | |
3441 | ||
3442 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3443 | sizeof(union drv_info_to_mcp)); | |
3444 | ||
3445 | switch (op_code) { | |
3446 | case ETH_STATS_OPCODE: | |
3447 | bnx2x_drv_info_ether_stat(bp); | |
3448 | break; | |
3449 | case FCOE_STATS_OPCODE: | |
3450 | bnx2x_drv_info_fcoe_stat(bp); | |
3451 | break; | |
3452 | case ISCSI_STATS_OPCODE: | |
3453 | bnx2x_drv_info_iscsi_stat(bp); | |
3454 | break; | |
3455 | default: | |
3456 | /* if op code isn't supported - send NACK */ | |
3457 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3458 | return; | |
3459 | } | |
3460 | ||
3461 | /* if we got drv_info attn from MFW then these fields are defined in | |
3462 | * shmem2 for sure | |
3463 | */ | |
3464 | SHMEM2_WR(bp, drv_info_host_addr_lo, | |
3465 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3466 | SHMEM2_WR(bp, drv_info_host_addr_hi, | |
3467 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3468 | ||
3469 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); | |
3470 | } | |
3471 | ||
523224a3 DK |
3472 | static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) |
3473 | { | |
3474 | DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); | |
3475 | ||
3476 | if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { | |
3477 | ||
3478 | /* | |
3479 | * This is the only place besides the function initialization | |
3480 | * where the bp->flags can change so it is done without any | |
3481 | * locks | |
3482 | */ | |
f2e0899f | 3483 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
51c1a580 | 3484 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
523224a3 DK |
3485 | bp->flags |= MF_FUNC_DIS; |
3486 | ||
3487 | bnx2x_e1h_disable(bp); | |
3488 | } else { | |
51c1a580 | 3489 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
523224a3 DK |
3490 | bp->flags &= ~MF_FUNC_DIS; |
3491 | ||
3492 | bnx2x_e1h_enable(bp); | |
3493 | } | |
3494 | dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; | |
3495 | } | |
3496 | if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { | |
0793f83f | 3497 | bnx2x_config_mf_bw(bp); |
523224a3 DK |
3498 | dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; |
3499 | } | |
3500 | ||
3501 | /* Report results to MCP */ | |
3502 | if (dcc_event) | |
3503 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); | |
3504 | else | |
3505 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); | |
3506 | } | |
3507 | ||
3508 | /* must be called under the spq lock */ | |
1191cb83 | 3509 | static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) |
523224a3 DK |
3510 | { |
3511 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3512 | ||
3513 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3514 | bp->spq_prod_bd = bp->spq; | |
3515 | bp->spq_prod_idx = 0; | |
51c1a580 | 3516 | DP(BNX2X_MSG_SP, "end of spq\n"); |
523224a3 DK |
3517 | } else { |
3518 | bp->spq_prod_bd++; | |
3519 | bp->spq_prod_idx++; | |
3520 | } | |
3521 | return next_spe; | |
3522 | } | |
3523 | ||
3524 | /* must be called under the spq lock */ | |
1191cb83 | 3525 | static void bnx2x_sp_prod_update(struct bnx2x *bp) |
28912902 MC |
3526 | { |
3527 | int func = BP_FUNC(bp); | |
3528 | ||
53e51e2f VZ |
3529 | /* |
3530 | * Make sure that BD data is updated before writing the producer: | |
3531 | * BD data is written to the memory, the producer is read from the | |
3532 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3533 | */ | |
3534 | mb(); | |
28912902 | 3535 | |
523224a3 | 3536 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3537 | bp->spq_prod_idx); |
28912902 MC |
3538 | mmiowb(); |
3539 | } | |
3540 | ||
619c5cb6 VZ |
3541 | /** |
3542 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3543 | * | |
3544 | * @cmd: command to check | |
3545 | * @cmd_type: command type | |
3546 | */ | |
1191cb83 | 3547 | static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) |
619c5cb6 VZ |
3548 | { |
3549 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3550 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3551 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3552 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3553 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3554 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3555 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3556 | return true; | |
3557 | else | |
3558 | return false; | |
619c5cb6 VZ |
3559 | } |
3560 | ||
619c5cb6 VZ |
3561 | /** |
3562 | * bnx2x_sp_post - place a single command on an SP ring | |
3563 | * | |
3564 | * @bp: driver handle | |
3565 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3566 | * @cid: SW CID the command is related to | |
3567 | * @data_hi: command private data address (high 32 bits) | |
3568 | * @data_lo: command private data address (low 32 bits) | |
3569 | * @cmd_type: command type (e.g. NONE, ETH) | |
3570 | * | |
3571 | * SP data is handled as if it's always an address pair, thus data fields are | |
3572 | * not swapped to little endian in upper functions. Instead this function swaps | |
3573 | * data as if it's two u32 fields. | |
3574 | */ | |
9f6c9258 | 3575 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3576 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3577 | { |
28912902 | 3578 | struct eth_spe *spe; |
523224a3 | 3579 | u16 type; |
619c5cb6 | 3580 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3581 | |
a2fbb9ea | 3582 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
3583 | if (unlikely(bp->panic)) { |
3584 | BNX2X_ERR("Can't post SP when there is panic\n"); | |
a2fbb9ea | 3585 | return -EIO; |
51c1a580 | 3586 | } |
a2fbb9ea ET |
3587 | #endif |
3588 | ||
34f80b04 | 3589 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3590 | |
6e30dd4e VZ |
3591 | if (common) { |
3592 | if (!atomic_read(&bp->eq_spq_left)) { | |
3593 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3594 | spin_unlock_bh(&bp->spq_lock); | |
3595 | bnx2x_panic(); | |
3596 | return -EBUSY; | |
3597 | } | |
3598 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3599 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3600 | spin_unlock_bh(&bp->spq_lock); | |
3601 | bnx2x_panic(); | |
3602 | return -EBUSY; | |
a2fbb9ea | 3603 | } |
f1410647 | 3604 | |
28912902 MC |
3605 | spe = bnx2x_sp_get_next(bp); |
3606 | ||
a2fbb9ea | 3607 | /* CID needs port number to be encoded int it */ |
28912902 | 3608 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3609 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3610 | HW_CID(bp, cid)); | |
523224a3 | 3611 | |
619c5cb6 | 3612 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; |
a2fbb9ea | 3613 | |
523224a3 DK |
3614 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & |
3615 | SPE_HDR_FUNCTION_ID); | |
a2fbb9ea | 3616 | |
523224a3 DK |
3617 | spe->hdr.type = cpu_to_le16(type); |
3618 | ||
3619 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3620 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3621 | ||
d6cae238 VZ |
3622 | /* |
3623 | * It's ok if the actual decrement is issued towards the memory | |
3624 | * somewhere between the spin_lock and spin_unlock. Thus no | |
16a5fd92 | 3625 | * more explicit memory barrier is needed. |
d6cae238 VZ |
3626 | */ |
3627 | if (common) | |
3628 | atomic_dec(&bp->eq_spq_left); | |
3629 | else | |
3630 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3631 | |
51c1a580 MS |
3632 | DP(BNX2X_MSG_SP, |
3633 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3634 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3635 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3636 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3637 | HW_CID(bp, cid), data_hi, data_lo, type, |
3638 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3639 | |
28912902 | 3640 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3641 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3642 | return 0; |
3643 | } | |
3644 | ||
3645 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3646 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3647 | { |
72fd0718 | 3648 | u32 j, val; |
34f80b04 | 3649 | int rc = 0; |
a2fbb9ea ET |
3650 | |
3651 | might_sleep(); | |
72fd0718 | 3652 | for (j = 0; j < 1000; j++) { |
3cdeec22 YM |
3653 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); |
3654 | val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); | |
3655 | if (val & MCPR_ACCESS_LOCK_LOCK) | |
a2fbb9ea ET |
3656 | break; |
3657 | ||
639d65b8 | 3658 | usleep_range(5000, 10000); |
a2fbb9ea | 3659 | } |
3cdeec22 | 3660 | if (!(val & MCPR_ACCESS_LOCK_LOCK)) { |
19680c48 | 3661 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3662 | rc = -EBUSY; |
3663 | } | |
3664 | ||
3665 | return rc; | |
3666 | } | |
3667 | ||
4a37fb66 YG |
3668 | /* release split MCP access lock register */ |
3669 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3670 | { |
3cdeec22 | 3671 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); |
a2fbb9ea ET |
3672 | } |
3673 | ||
523224a3 DK |
3674 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3675 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3676 | ||
1191cb83 | 3677 | static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
a2fbb9ea | 3678 | { |
523224a3 | 3679 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3680 | u16 rc = 0; |
3681 | ||
3682 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3683 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3684 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3685 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3686 | } |
523224a3 DK |
3687 | |
3688 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3689 | bp->def_idx = def_sb->sp_sb.running_index; | |
3690 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3691 | } |
523224a3 | 3692 | |
16a5fd92 | 3693 | /* Do not reorder: indices reading should complete before handling */ |
523224a3 | 3694 | barrier(); |
a2fbb9ea ET |
3695 | return rc; |
3696 | } | |
3697 | ||
3698 | /* | |
3699 | * slow path service functions | |
3700 | */ | |
3701 | ||
3702 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3703 | { | |
34f80b04 | 3704 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3705 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3706 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3707 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3708 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3709 | u32 aeu_mask; |
87942b46 | 3710 | u32 nig_mask = 0; |
f2e0899f | 3711 | u32 reg_addr; |
a2fbb9ea | 3712 | |
a2fbb9ea ET |
3713 | if (bp->attn_state & asserted) |
3714 | BNX2X_ERR("IGU ERROR\n"); | |
3715 | ||
3fcaf2e5 EG |
3716 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
3717 | aeu_mask = REG_RD(bp, aeu_addr); | |
3718 | ||
a2fbb9ea | 3719 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 3720 | aeu_mask, asserted); |
72fd0718 | 3721 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 3722 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 3723 | |
3fcaf2e5 EG |
3724 | REG_WR(bp, aeu_addr, aeu_mask); |
3725 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 3726 | |
3fcaf2e5 | 3727 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 3728 | bp->attn_state |= asserted; |
3fcaf2e5 | 3729 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
3730 | |
3731 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
3732 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 3733 | |
a5e9a7cf EG |
3734 | bnx2x_acquire_phy_lock(bp); |
3735 | ||
877e9aa4 | 3736 | /* save nig interrupt mask */ |
87942b46 | 3737 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 3738 | |
361c391e YR |
3739 | /* If nig_mask is not set, no need to call the update |
3740 | * function. | |
3741 | */ | |
3742 | if (nig_mask) { | |
3743 | REG_WR(bp, nig_int_mask_addr, 0); | |
3744 | ||
3745 | bnx2x_link_attn(bp); | |
3746 | } | |
a2fbb9ea ET |
3747 | |
3748 | /* handle unicore attn? */ | |
3749 | } | |
3750 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
3751 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
3752 | ||
3753 | if (asserted & GPIO_2_FUNC) | |
3754 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
3755 | ||
3756 | if (asserted & GPIO_3_FUNC) | |
3757 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
3758 | ||
3759 | if (asserted & GPIO_4_FUNC) | |
3760 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
3761 | ||
3762 | if (port == 0) { | |
3763 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
3764 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
3765 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
3766 | } | |
3767 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
3768 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
3769 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
3770 | } | |
3771 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
3772 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
3773 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
3774 | } | |
3775 | } else { | |
3776 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
3777 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
3778 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
3779 | } | |
3780 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
3781 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
3782 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
3783 | } | |
3784 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
3785 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
3786 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
3787 | } | |
3788 | } | |
3789 | ||
3790 | } /* if hardwired */ | |
3791 | ||
f2e0899f DK |
3792 | if (bp->common.int_block == INT_BLOCK_HC) |
3793 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
3794 | COMMAND_REG_ATTN_BITS_SET); | |
3795 | else | |
3796 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
3797 | ||
3798 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
3799 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
3800 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
3801 | |
3802 | /* now set back the mask */ | |
a5e9a7cf | 3803 | if (asserted & ATTN_NIG_FOR_FUNC) { |
27c1151c YR |
3804 | /* Verify that IGU ack through BAR was written before restoring |
3805 | * NIG mask. This loop should exit after 2-3 iterations max. | |
3806 | */ | |
3807 | if (bp->common.int_block != INT_BLOCK_HC) { | |
3808 | u32 cnt = 0, igu_acked; | |
3809 | do { | |
3810 | igu_acked = REG_RD(bp, | |
3811 | IGU_REG_ATTENTION_ACK_BITS); | |
3812 | } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && | |
3813 | (++cnt < MAX_IGU_ATTN_ACK_TO)); | |
3814 | if (!igu_acked) | |
3815 | DP(NETIF_MSG_HW, | |
3816 | "Failed to verify IGU ack on time\n"); | |
3817 | barrier(); | |
3818 | } | |
87942b46 | 3819 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
3820 | bnx2x_release_phy_lock(bp); |
3821 | } | |
a2fbb9ea ET |
3822 | } |
3823 | ||
1191cb83 | 3824 | static void bnx2x_fan_failure(struct bnx2x *bp) |
fd4ef40d EG |
3825 | { |
3826 | int port = BP_PORT(bp); | |
b7737c9b | 3827 | u32 ext_phy_config; |
fd4ef40d | 3828 | /* mark the failure */ |
b7737c9b YR |
3829 | ext_phy_config = |
3830 | SHMEM_RD(bp, | |
3831 | dev_info.port_hw_config[port].external_phy_config); | |
3832 | ||
3833 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
3834 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 3835 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 3836 | ext_phy_config); |
fd4ef40d EG |
3837 | |
3838 | /* log the failure */ | |
51c1a580 MS |
3839 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
3840 | "Please contact OEM Support for assistance\n"); | |
8304859a | 3841 | |
16a5fd92 | 3842 | /* Schedule device reset (unload) |
8304859a AE |
3843 | * This is due to some boards consuming sufficient power when driver is |
3844 | * up to overheat if fan fails. | |
3845 | */ | |
3846 | smp_mb__before_clear_bit(); | |
3847 | set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); | |
3848 | smp_mb__after_clear_bit(); | |
3849 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
fd4ef40d | 3850 | } |
ab6ad5a4 | 3851 | |
1191cb83 | 3852 | static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 3853 | { |
34f80b04 | 3854 | int port = BP_PORT(bp); |
877e9aa4 | 3855 | int reg_offset; |
d90d96ba | 3856 | u32 val; |
877e9aa4 | 3857 | |
34f80b04 EG |
3858 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
3859 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 3860 | |
34f80b04 | 3861 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
3862 | |
3863 | val = REG_RD(bp, reg_offset); | |
3864 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
3865 | REG_WR(bp, reg_offset, val); | |
3866 | ||
3867 | BNX2X_ERR("SPIO5 hw attention\n"); | |
3868 | ||
fd4ef40d | 3869 | /* Fan failure attention */ |
d90d96ba | 3870 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 3871 | bnx2x_fan_failure(bp); |
877e9aa4 | 3872 | } |
34f80b04 | 3873 | |
3deb8167 | 3874 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
3875 | bnx2x_acquire_phy_lock(bp); |
3876 | bnx2x_handle_module_detect_int(&bp->link_params); | |
3877 | bnx2x_release_phy_lock(bp); | |
3878 | } | |
3879 | ||
34f80b04 EG |
3880 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
3881 | ||
3882 | val = REG_RD(bp, reg_offset); | |
3883 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
3884 | REG_WR(bp, reg_offset, val); | |
3885 | ||
3886 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 3887 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
3888 | bnx2x_panic(); |
3889 | } | |
877e9aa4 ET |
3890 | } |
3891 | ||
1191cb83 | 3892 | static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
3893 | { |
3894 | u32 val; | |
3895 | ||
0626b899 | 3896 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
3897 | |
3898 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
3899 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
3900 | /* DORQ discard attention */ | |
3901 | if (val & 0x2) | |
3902 | BNX2X_ERR("FATAL error from DORQ\n"); | |
3903 | } | |
34f80b04 EG |
3904 | |
3905 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
3906 | ||
3907 | int port = BP_PORT(bp); | |
3908 | int reg_offset; | |
3909 | ||
3910 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
3911 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
3912 | ||
3913 | val = REG_RD(bp, reg_offset); | |
3914 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
3915 | REG_WR(bp, reg_offset, val); | |
3916 | ||
3917 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 3918 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
3919 | bnx2x_panic(); |
3920 | } | |
877e9aa4 ET |
3921 | } |
3922 | ||
1191cb83 | 3923 | static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
3924 | { |
3925 | u32 val; | |
3926 | ||
3927 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
3928 | ||
3929 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
3930 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
3931 | /* CFC error attention */ | |
3932 | if (val & 0x2) | |
3933 | BNX2X_ERR("FATAL error from CFC\n"); | |
3934 | } | |
3935 | ||
3936 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 3937 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 3938 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
3939 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
3940 | if (val & 0x18000) | |
3941 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
3942 | |
3943 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
3944 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
3945 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
3946 | } | |
877e9aa4 | 3947 | } |
34f80b04 EG |
3948 | |
3949 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
3950 | ||
3951 | int port = BP_PORT(bp); | |
3952 | int reg_offset; | |
3953 | ||
3954 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
3955 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
3956 | ||
3957 | val = REG_RD(bp, reg_offset); | |
3958 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
3959 | REG_WR(bp, reg_offset, val); | |
3960 | ||
3961 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 3962 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
3963 | bnx2x_panic(); |
3964 | } | |
877e9aa4 ET |
3965 | } |
3966 | ||
1191cb83 | 3967 | static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) |
877e9aa4 | 3968 | { |
34f80b04 EG |
3969 | u32 val; |
3970 | ||
877e9aa4 ET |
3971 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
3972 | ||
34f80b04 EG |
3973 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
3974 | int func = BP_FUNC(bp); | |
3975 | ||
3976 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
a3348722 | 3977 | bnx2x_read_mf_cfg(bp); |
f2e0899f DK |
3978 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
3979 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
3980 | val = SHMEM_RD(bp, | |
3981 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
2691d51d EG |
3982 | if (val & DRV_STATUS_DCC_EVENT_MASK) |
3983 | bnx2x_dcc_event(bp, | |
3984 | (val & DRV_STATUS_DCC_EVENT_MASK)); | |
0793f83f DK |
3985 | |
3986 | if (val & DRV_STATUS_SET_MF_BW) | |
3987 | bnx2x_set_mf_bw(bp); | |
3988 | ||
1d187b34 BW |
3989 | if (val & DRV_STATUS_DRV_INFO_REQ) |
3990 | bnx2x_handle_drv_info_req(bp); | |
d16132ce AE |
3991 | |
3992 | if (val & DRV_STATUS_VF_DISABLED) | |
3993 | bnx2x_vf_handle_flr_event(bp); | |
3994 | ||
2691d51d | 3995 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
3996 | bnx2x_pmf_update(bp); |
3997 | ||
e4901dde | 3998 | if (bp->port.pmf && |
785b9b1a SR |
3999 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
4000 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
4001 | /* start dcbx state machine */ |
4002 | bnx2x_dcbx_set_params(bp, | |
4003 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
a3348722 BW |
4004 | if (val & DRV_STATUS_AFEX_EVENT_MASK) |
4005 | bnx2x_handle_afex_cmd(bp, | |
4006 | val & DRV_STATUS_AFEX_EVENT_MASK); | |
c8c60d88 YM |
4007 | if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) |
4008 | bnx2x_handle_eee_event(bp); | |
3deb8167 YR |
4009 | if (bp->link_vars.periodic_flags & |
4010 | PERIODIC_FLAGS_LINK_EVENT) { | |
4011 | /* sync with link */ | |
4012 | bnx2x_acquire_phy_lock(bp); | |
4013 | bp->link_vars.periodic_flags &= | |
4014 | ~PERIODIC_FLAGS_LINK_EVENT; | |
4015 | bnx2x_release_phy_lock(bp); | |
4016 | if (IS_MF(bp)) | |
4017 | bnx2x_link_sync_notify(bp); | |
4018 | bnx2x_link_report(bp); | |
4019 | } | |
4020 | /* Always call it here: bnx2x_link_report() will | |
4021 | * prevent the link indication duplication. | |
4022 | */ | |
4023 | bnx2x__link_status_update(bp); | |
34f80b04 | 4024 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
4025 | |
4026 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 4027 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
4028 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
4029 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
4030 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
4031 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
4032 | bnx2x_panic(); | |
4033 | ||
4034 | } else if (attn & BNX2X_MCP_ASSERT) { | |
4035 | ||
4036 | BNX2X_ERR("MCP assert!\n"); | |
4037 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 4038 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
4039 | |
4040 | } else | |
4041 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
4042 | } | |
4043 | ||
4044 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
4045 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
4046 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
4047 | val = CHIP_IS_E1(bp) ? 0 : |
4048 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
4049 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
4050 | } | |
4051 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
4052 | val = CHIP_IS_E1(bp) ? 0 : |
4053 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
4054 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
4055 | } | |
877e9aa4 | 4056 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
4057 | } |
4058 | } | |
4059 | ||
c9ee9206 VZ |
4060 | /* |
4061 | * Bits map: | |
4062 | * 0-7 - Engine0 load counter. | |
4063 | * 8-15 - Engine1 load counter. | |
4064 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
4065 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
4066 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
4067 | * on the engine | |
4068 | * 19 - Engine1 ONE_IS_LOADED. | |
4069 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
4070 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
4071 | * just the one belonging to its engine). | |
4072 | * | |
4073 | */ | |
4074 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
4075 | ||
4076 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
4077 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
4078 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
4079 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
4080 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
4081 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
4082 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
4083 | ||
4084 | /* | |
4085 | * Set the GLOBAL_RESET bit. | |
4086 | * | |
4087 | * Should be run under rtnl lock | |
4088 | */ | |
4089 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
4090 | { | |
f16da43b AE |
4091 | u32 val; |
4092 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4093 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4094 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
f16da43b | 4095 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 VZ |
4096 | } |
4097 | ||
4098 | /* | |
4099 | * Clear the GLOBAL_RESET bit. | |
4100 | * | |
4101 | * Should be run under rtnl lock | |
4102 | */ | |
1191cb83 | 4103 | static void bnx2x_clear_reset_global(struct bnx2x *bp) |
c9ee9206 | 4104 | { |
f16da43b AE |
4105 | u32 val; |
4106 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4107 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4108 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
f16da43b | 4109 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 | 4110 | } |
f85582f8 | 4111 | |
72fd0718 | 4112 | /* |
c9ee9206 VZ |
4113 | * Checks the GLOBAL_RESET bit. |
4114 | * | |
72fd0718 VZ |
4115 | * should be run under rtnl lock |
4116 | */ | |
1191cb83 | 4117 | static bool bnx2x_reset_is_global(struct bnx2x *bp) |
c9ee9206 | 4118 | { |
3cdeec22 | 4119 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
c9ee9206 VZ |
4120 | |
4121 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
4122 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
4123 | } | |
4124 | ||
4125 | /* | |
4126 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
4127 | * | |
4128 | * Should be run under rtnl lock | |
4129 | */ | |
1191cb83 | 4130 | static void bnx2x_set_reset_done(struct bnx2x *bp) |
72fd0718 | 4131 | { |
f16da43b | 4132 | u32 val; |
c9ee9206 VZ |
4133 | u32 bit = BP_PATH(bp) ? |
4134 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4135 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4136 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4137 | |
4138 | /* Clear the bit */ | |
4139 | val &= ~bit; | |
4140 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4141 | |
4142 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
72fd0718 VZ |
4143 | } |
4144 | ||
4145 | /* | |
c9ee9206 VZ |
4146 | * Set RESET_IN_PROGRESS for the current engine. |
4147 | * | |
72fd0718 VZ |
4148 | * should be run under rtnl lock |
4149 | */ | |
c9ee9206 | 4150 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 4151 | { |
f16da43b | 4152 | u32 val; |
c9ee9206 VZ |
4153 | u32 bit = BP_PATH(bp) ? |
4154 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4155 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4156 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4157 | |
4158 | /* Set the bit */ | |
4159 | val |= bit; | |
4160 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4161 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4162 | } |
4163 | ||
4164 | /* | |
c9ee9206 | 4165 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
4166 | * should be run under rtnl lock |
4167 | */ | |
c9ee9206 | 4168 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 4169 | { |
3cdeec22 | 4170 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
c9ee9206 VZ |
4171 | u32 bit = engine ? |
4172 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
4173 | ||
4174 | /* return false if bit is set */ | |
4175 | return (val & bit) ? false : true; | |
72fd0718 VZ |
4176 | } |
4177 | ||
4178 | /* | |
889b9af3 | 4179 | * set pf load for the current pf. |
c9ee9206 | 4180 | * |
72fd0718 VZ |
4181 | * should be run under rtnl lock |
4182 | */ | |
889b9af3 | 4183 | void bnx2x_set_pf_load(struct bnx2x *bp) |
72fd0718 | 4184 | { |
f16da43b | 4185 | u32 val1, val; |
c9ee9206 VZ |
4186 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4187 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4188 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4189 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4190 | |
f16da43b AE |
4191 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4192 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4193 | ||
51c1a580 | 4194 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4195 | |
c9ee9206 VZ |
4196 | /* get the current counter value */ |
4197 | val1 = (val & mask) >> shift; | |
4198 | ||
889b9af3 AE |
4199 | /* set bit of that PF */ |
4200 | val1 |= (1 << bp->pf_num); | |
c9ee9206 VZ |
4201 | |
4202 | /* clear the old value */ | |
4203 | val &= ~mask; | |
4204 | ||
4205 | /* set the new one */ | |
4206 | val |= ((val1 << shift) & mask); | |
4207 | ||
4208 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4209 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4210 | } |
4211 | ||
c9ee9206 | 4212 | /** |
889b9af3 | 4213 | * bnx2x_clear_pf_load - clear pf load mark |
c9ee9206 VZ |
4214 | * |
4215 | * @bp: driver handle | |
4216 | * | |
4217 | * Should be run under rtnl lock. | |
4218 | * Decrements the load counter for the current engine. Returns | |
889b9af3 | 4219 | * whether other functions are still loaded |
72fd0718 | 4220 | */ |
889b9af3 | 4221 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
72fd0718 | 4222 | { |
f16da43b | 4223 | u32 val1, val; |
c9ee9206 VZ |
4224 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4225 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4226 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4227 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4228 | |
f16da43b AE |
4229 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4230 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
51c1a580 | 4231 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4232 | |
c9ee9206 VZ |
4233 | /* get the current counter value */ |
4234 | val1 = (val & mask) >> shift; | |
4235 | ||
889b9af3 AE |
4236 | /* clear bit of that PF */ |
4237 | val1 &= ~(1 << bp->pf_num); | |
c9ee9206 VZ |
4238 | |
4239 | /* clear the old value */ | |
4240 | val &= ~mask; | |
4241 | ||
4242 | /* set the new one */ | |
4243 | val |= ((val1 << shift) & mask); | |
4244 | ||
4245 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4246 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4247 | return val1 != 0; | |
72fd0718 VZ |
4248 | } |
4249 | ||
4250 | /* | |
889b9af3 | 4251 | * Read the load status for the current engine. |
c9ee9206 | 4252 | * |
72fd0718 VZ |
4253 | * should be run under rtnl lock |
4254 | */ | |
1191cb83 | 4255 | static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
72fd0718 | 4256 | { |
c9ee9206 VZ |
4257 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
4258 | BNX2X_PATH0_LOAD_CNT_MASK); | |
4259 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4260 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
4261 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4262 | ||
51c1a580 | 4263 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
c9ee9206 VZ |
4264 | |
4265 | val = (val & mask) >> shift; | |
4266 | ||
51c1a580 MS |
4267 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
4268 | engine, val); | |
c9ee9206 | 4269 | |
889b9af3 | 4270 | return val != 0; |
72fd0718 VZ |
4271 | } |
4272 | ||
6bf07b8e YM |
4273 | static void _print_parity(struct bnx2x *bp, u32 reg) |
4274 | { | |
4275 | pr_cont(" [0x%08x] ", REG_RD(bp, reg)); | |
4276 | } | |
4277 | ||
1191cb83 | 4278 | static void _print_next_block(int idx, const char *blk) |
72fd0718 | 4279 | { |
f1deab50 | 4280 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
4281 | } |
4282 | ||
6bf07b8e YM |
4283 | static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, |
4284 | int par_num, bool print) | |
72fd0718 VZ |
4285 | { |
4286 | int i = 0; | |
4287 | u32 cur_bit = 0; | |
4288 | for (i = 0; sig; i++) { | |
4289 | cur_bit = ((u32)0x1 << i); | |
4290 | if (sig & cur_bit) { | |
4291 | switch (cur_bit) { | |
4292 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
6bf07b8e | 4293 | if (print) { |
c9ee9206 | 4294 | _print_next_block(par_num++, "BRB"); |
6bf07b8e YM |
4295 | _print_parity(bp, |
4296 | BRB1_REG_BRB1_PRTY_STS); | |
4297 | } | |
72fd0718 VZ |
4298 | break; |
4299 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
6bf07b8e | 4300 | if (print) { |
c9ee9206 | 4301 | _print_next_block(par_num++, "PARSER"); |
6bf07b8e YM |
4302 | _print_parity(bp, PRS_REG_PRS_PRTY_STS); |
4303 | } | |
72fd0718 VZ |
4304 | break; |
4305 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
6bf07b8e | 4306 | if (print) { |
c9ee9206 | 4307 | _print_next_block(par_num++, "TSDM"); |
6bf07b8e YM |
4308 | _print_parity(bp, |
4309 | TSDM_REG_TSDM_PRTY_STS); | |
4310 | } | |
72fd0718 VZ |
4311 | break; |
4312 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
6bf07b8e | 4313 | if (print) { |
c9ee9206 VZ |
4314 | _print_next_block(par_num++, |
4315 | "SEARCHER"); | |
6bf07b8e YM |
4316 | _print_parity(bp, SRC_REG_SRC_PRTY_STS); |
4317 | } | |
c9ee9206 VZ |
4318 | break; |
4319 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
6bf07b8e | 4320 | if (print) { |
c9ee9206 | 4321 | _print_next_block(par_num++, "TCM"); |
6bf07b8e YM |
4322 | _print_parity(bp, |
4323 | TCM_REG_TCM_PRTY_STS); | |
4324 | } | |
72fd0718 VZ |
4325 | break; |
4326 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
6bf07b8e | 4327 | if (print) { |
c9ee9206 | 4328 | _print_next_block(par_num++, "TSEMI"); |
6bf07b8e YM |
4329 | _print_parity(bp, |
4330 | TSEM_REG_TSEM_PRTY_STS_0); | |
4331 | _print_parity(bp, | |
4332 | TSEM_REG_TSEM_PRTY_STS_1); | |
4333 | } | |
c9ee9206 VZ |
4334 | break; |
4335 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
6bf07b8e | 4336 | if (print) { |
c9ee9206 | 4337 | _print_next_block(par_num++, "XPB"); |
6bf07b8e YM |
4338 | _print_parity(bp, GRCBASE_XPB + |
4339 | PB_REG_PB_PRTY_STS); | |
4340 | } | |
72fd0718 VZ |
4341 | break; |
4342 | } | |
4343 | ||
4344 | /* Clear the bit */ | |
4345 | sig &= ~cur_bit; | |
4346 | } | |
4347 | } | |
4348 | ||
4349 | return par_num; | |
4350 | } | |
4351 | ||
6bf07b8e YM |
4352 | static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, |
4353 | int par_num, bool *global, | |
4354 | bool print) | |
72fd0718 VZ |
4355 | { |
4356 | int i = 0; | |
4357 | u32 cur_bit = 0; | |
4358 | for (i = 0; sig; i++) { | |
4359 | cur_bit = ((u32)0x1 << i); | |
4360 | if (sig & cur_bit) { | |
4361 | switch (cur_bit) { | |
c9ee9206 | 4362 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
6bf07b8e | 4363 | if (print) { |
c9ee9206 | 4364 | _print_next_block(par_num++, "PBF"); |
6bf07b8e YM |
4365 | _print_parity(bp, PBF_REG_PBF_PRTY_STS); |
4366 | } | |
72fd0718 VZ |
4367 | break; |
4368 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
6bf07b8e | 4369 | if (print) { |
c9ee9206 | 4370 | _print_next_block(par_num++, "QM"); |
6bf07b8e YM |
4371 | _print_parity(bp, QM_REG_QM_PRTY_STS); |
4372 | } | |
c9ee9206 VZ |
4373 | break; |
4374 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
6bf07b8e | 4375 | if (print) { |
c9ee9206 | 4376 | _print_next_block(par_num++, "TM"); |
6bf07b8e YM |
4377 | _print_parity(bp, TM_REG_TM_PRTY_STS); |
4378 | } | |
72fd0718 VZ |
4379 | break; |
4380 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
6bf07b8e | 4381 | if (print) { |
c9ee9206 | 4382 | _print_next_block(par_num++, "XSDM"); |
6bf07b8e YM |
4383 | _print_parity(bp, |
4384 | XSDM_REG_XSDM_PRTY_STS); | |
4385 | } | |
c9ee9206 VZ |
4386 | break; |
4387 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
6bf07b8e | 4388 | if (print) { |
c9ee9206 | 4389 | _print_next_block(par_num++, "XCM"); |
6bf07b8e YM |
4390 | _print_parity(bp, XCM_REG_XCM_PRTY_STS); |
4391 | } | |
72fd0718 VZ |
4392 | break; |
4393 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
6bf07b8e | 4394 | if (print) { |
c9ee9206 | 4395 | _print_next_block(par_num++, "XSEMI"); |
6bf07b8e YM |
4396 | _print_parity(bp, |
4397 | XSEM_REG_XSEM_PRTY_STS_0); | |
4398 | _print_parity(bp, | |
4399 | XSEM_REG_XSEM_PRTY_STS_1); | |
4400 | } | |
72fd0718 VZ |
4401 | break; |
4402 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
6bf07b8e | 4403 | if (print) { |
c9ee9206 VZ |
4404 | _print_next_block(par_num++, |
4405 | "DOORBELLQ"); | |
6bf07b8e YM |
4406 | _print_parity(bp, |
4407 | DORQ_REG_DORQ_PRTY_STS); | |
4408 | } | |
c9ee9206 VZ |
4409 | break; |
4410 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
6bf07b8e | 4411 | if (print) { |
c9ee9206 | 4412 | _print_next_block(par_num++, "NIG"); |
6bf07b8e YM |
4413 | if (CHIP_IS_E1x(bp)) { |
4414 | _print_parity(bp, | |
4415 | NIG_REG_NIG_PRTY_STS); | |
4416 | } else { | |
4417 | _print_parity(bp, | |
4418 | NIG_REG_NIG_PRTY_STS_0); | |
4419 | _print_parity(bp, | |
4420 | NIG_REG_NIG_PRTY_STS_1); | |
4421 | } | |
4422 | } | |
72fd0718 VZ |
4423 | break; |
4424 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 VZ |
4425 | if (print) |
4426 | _print_next_block(par_num++, | |
4427 | "VAUX PCI CORE"); | |
4428 | *global = true; | |
72fd0718 VZ |
4429 | break; |
4430 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
6bf07b8e | 4431 | if (print) { |
c9ee9206 | 4432 | _print_next_block(par_num++, "DEBUG"); |
6bf07b8e YM |
4433 | _print_parity(bp, DBG_REG_DBG_PRTY_STS); |
4434 | } | |
72fd0718 VZ |
4435 | break; |
4436 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
6bf07b8e | 4437 | if (print) { |
c9ee9206 | 4438 | _print_next_block(par_num++, "USDM"); |
6bf07b8e YM |
4439 | _print_parity(bp, |
4440 | USDM_REG_USDM_PRTY_STS); | |
4441 | } | |
72fd0718 | 4442 | break; |
8736c826 | 4443 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
6bf07b8e | 4444 | if (print) { |
8736c826 | 4445 | _print_next_block(par_num++, "UCM"); |
6bf07b8e YM |
4446 | _print_parity(bp, UCM_REG_UCM_PRTY_STS); |
4447 | } | |
8736c826 | 4448 | break; |
72fd0718 | 4449 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
6bf07b8e | 4450 | if (print) { |
c9ee9206 | 4451 | _print_next_block(par_num++, "USEMI"); |
6bf07b8e YM |
4452 | _print_parity(bp, |
4453 | USEM_REG_USEM_PRTY_STS_0); | |
4454 | _print_parity(bp, | |
4455 | USEM_REG_USEM_PRTY_STS_1); | |
4456 | } | |
72fd0718 VZ |
4457 | break; |
4458 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
6bf07b8e | 4459 | if (print) { |
c9ee9206 | 4460 | _print_next_block(par_num++, "UPB"); |
6bf07b8e YM |
4461 | _print_parity(bp, GRCBASE_UPB + |
4462 | PB_REG_PB_PRTY_STS); | |
4463 | } | |
72fd0718 VZ |
4464 | break; |
4465 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
6bf07b8e | 4466 | if (print) { |
c9ee9206 | 4467 | _print_next_block(par_num++, "CSDM"); |
6bf07b8e YM |
4468 | _print_parity(bp, |
4469 | CSDM_REG_CSDM_PRTY_STS); | |
4470 | } | |
72fd0718 | 4471 | break; |
8736c826 | 4472 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
6bf07b8e | 4473 | if (print) { |
8736c826 | 4474 | _print_next_block(par_num++, "CCM"); |
6bf07b8e YM |
4475 | _print_parity(bp, CCM_REG_CCM_PRTY_STS); |
4476 | } | |
8736c826 | 4477 | break; |
72fd0718 VZ |
4478 | } |
4479 | ||
4480 | /* Clear the bit */ | |
4481 | sig &= ~cur_bit; | |
4482 | } | |
4483 | } | |
4484 | ||
4485 | return par_num; | |
4486 | } | |
4487 | ||
6bf07b8e YM |
4488 | static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, |
4489 | int par_num, bool print) | |
72fd0718 VZ |
4490 | { |
4491 | int i = 0; | |
4492 | u32 cur_bit = 0; | |
4493 | for (i = 0; sig; i++) { | |
4494 | cur_bit = ((u32)0x1 << i); | |
4495 | if (sig & cur_bit) { | |
4496 | switch (cur_bit) { | |
4497 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
6bf07b8e | 4498 | if (print) { |
c9ee9206 | 4499 | _print_next_block(par_num++, "CSEMI"); |
6bf07b8e YM |
4500 | _print_parity(bp, |
4501 | CSEM_REG_CSEM_PRTY_STS_0); | |
4502 | _print_parity(bp, | |
4503 | CSEM_REG_CSEM_PRTY_STS_1); | |
4504 | } | |
72fd0718 VZ |
4505 | break; |
4506 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
6bf07b8e | 4507 | if (print) { |
c9ee9206 | 4508 | _print_next_block(par_num++, "PXP"); |
6bf07b8e YM |
4509 | _print_parity(bp, PXP_REG_PXP_PRTY_STS); |
4510 | _print_parity(bp, | |
4511 | PXP2_REG_PXP2_PRTY_STS_0); | |
4512 | _print_parity(bp, | |
4513 | PXP2_REG_PXP2_PRTY_STS_1); | |
4514 | } | |
72fd0718 VZ |
4515 | break; |
4516 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
c9ee9206 VZ |
4517 | if (print) |
4518 | _print_next_block(par_num++, | |
72fd0718 VZ |
4519 | "PXPPCICLOCKCLIENT"); |
4520 | break; | |
4521 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
6bf07b8e | 4522 | if (print) { |
c9ee9206 | 4523 | _print_next_block(par_num++, "CFC"); |
6bf07b8e YM |
4524 | _print_parity(bp, |
4525 | CFC_REG_CFC_PRTY_STS); | |
4526 | } | |
72fd0718 VZ |
4527 | break; |
4528 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
6bf07b8e | 4529 | if (print) { |
c9ee9206 | 4530 | _print_next_block(par_num++, "CDU"); |
6bf07b8e YM |
4531 | _print_parity(bp, CDU_REG_CDU_PRTY_STS); |
4532 | } | |
c9ee9206 VZ |
4533 | break; |
4534 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
6bf07b8e | 4535 | if (print) { |
c9ee9206 | 4536 | _print_next_block(par_num++, "DMAE"); |
6bf07b8e YM |
4537 | _print_parity(bp, |
4538 | DMAE_REG_DMAE_PRTY_STS); | |
4539 | } | |
72fd0718 VZ |
4540 | break; |
4541 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
6bf07b8e | 4542 | if (print) { |
c9ee9206 | 4543 | _print_next_block(par_num++, "IGU"); |
6bf07b8e YM |
4544 | if (CHIP_IS_E1x(bp)) |
4545 | _print_parity(bp, | |
4546 | HC_REG_HC_PRTY_STS); | |
4547 | else | |
4548 | _print_parity(bp, | |
4549 | IGU_REG_IGU_PRTY_STS); | |
4550 | } | |
72fd0718 VZ |
4551 | break; |
4552 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
6bf07b8e | 4553 | if (print) { |
c9ee9206 | 4554 | _print_next_block(par_num++, "MISC"); |
6bf07b8e YM |
4555 | _print_parity(bp, |
4556 | MISC_REG_MISC_PRTY_STS); | |
4557 | } | |
72fd0718 VZ |
4558 | break; |
4559 | } | |
4560 | ||
4561 | /* Clear the bit */ | |
4562 | sig &= ~cur_bit; | |
4563 | } | |
4564 | } | |
4565 | ||
4566 | return par_num; | |
4567 | } | |
4568 | ||
1191cb83 ED |
4569 | static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, |
4570 | bool *global, bool print) | |
72fd0718 VZ |
4571 | { |
4572 | int i = 0; | |
4573 | u32 cur_bit = 0; | |
4574 | for (i = 0; sig; i++) { | |
4575 | cur_bit = ((u32)0x1 << i); | |
4576 | if (sig & cur_bit) { | |
4577 | switch (cur_bit) { | |
4578 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 VZ |
4579 | if (print) |
4580 | _print_next_block(par_num++, "MCP ROM"); | |
4581 | *global = true; | |
72fd0718 VZ |
4582 | break; |
4583 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 VZ |
4584 | if (print) |
4585 | _print_next_block(par_num++, | |
4586 | "MCP UMP RX"); | |
4587 | *global = true; | |
72fd0718 VZ |
4588 | break; |
4589 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 VZ |
4590 | if (print) |
4591 | _print_next_block(par_num++, | |
4592 | "MCP UMP TX"); | |
4593 | *global = true; | |
72fd0718 VZ |
4594 | break; |
4595 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
c9ee9206 VZ |
4596 | if (print) |
4597 | _print_next_block(par_num++, | |
4598 | "MCP SCPAD"); | |
4599 | *global = true; | |
72fd0718 VZ |
4600 | break; |
4601 | } | |
4602 | ||
4603 | /* Clear the bit */ | |
4604 | sig &= ~cur_bit; | |
4605 | } | |
4606 | } | |
4607 | ||
4608 | return par_num; | |
4609 | } | |
4610 | ||
6bf07b8e YM |
4611 | static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, |
4612 | int par_num, bool print) | |
8736c826 VZ |
4613 | { |
4614 | int i = 0; | |
4615 | u32 cur_bit = 0; | |
4616 | for (i = 0; sig; i++) { | |
4617 | cur_bit = ((u32)0x1 << i); | |
4618 | if (sig & cur_bit) { | |
4619 | switch (cur_bit) { | |
4620 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
6bf07b8e | 4621 | if (print) { |
8736c826 | 4622 | _print_next_block(par_num++, "PGLUE_B"); |
6bf07b8e YM |
4623 | _print_parity(bp, |
4624 | PGLUE_B_REG_PGLUE_B_PRTY_STS); | |
4625 | } | |
8736c826 VZ |
4626 | break; |
4627 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
6bf07b8e | 4628 | if (print) { |
8736c826 | 4629 | _print_next_block(par_num++, "ATC"); |
6bf07b8e YM |
4630 | _print_parity(bp, |
4631 | ATC_REG_ATC_PRTY_STS); | |
4632 | } | |
8736c826 VZ |
4633 | break; |
4634 | } | |
4635 | ||
4636 | /* Clear the bit */ | |
4637 | sig &= ~cur_bit; | |
4638 | } | |
4639 | } | |
4640 | ||
4641 | return par_num; | |
4642 | } | |
4643 | ||
1191cb83 ED |
4644 | static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
4645 | u32 *sig) | |
72fd0718 | 4646 | { |
8736c826 VZ |
4647 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4648 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4649 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4650 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4651 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 | 4652 | int par_num = 0; |
51c1a580 MS |
4653 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
4654 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", | |
8736c826 VZ |
4655 | sig[0] & HW_PRTY_ASSERT_SET_0, |
4656 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4657 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4658 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4659 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
c9ee9206 VZ |
4660 | if (print) |
4661 | netdev_err(bp->dev, | |
4662 | "Parity errors detected in blocks: "); | |
6bf07b8e | 4663 | par_num = bnx2x_check_blocks_with_parity0(bp, |
8736c826 | 4664 | sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); |
6bf07b8e | 4665 | par_num = bnx2x_check_blocks_with_parity1(bp, |
8736c826 | 4666 | sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); |
6bf07b8e | 4667 | par_num = bnx2x_check_blocks_with_parity2(bp, |
8736c826 | 4668 | sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); |
c9ee9206 | 4669 | par_num = bnx2x_check_blocks_with_parity3( |
8736c826 | 4670 | sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); |
6bf07b8e | 4671 | par_num = bnx2x_check_blocks_with_parity4(bp, |
8736c826 VZ |
4672 | sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); |
4673 | ||
c9ee9206 VZ |
4674 | if (print) |
4675 | pr_cont("\n"); | |
8736c826 | 4676 | |
72fd0718 VZ |
4677 | return true; |
4678 | } else | |
4679 | return false; | |
4680 | } | |
4681 | ||
c9ee9206 VZ |
4682 | /** |
4683 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
4684 | * | |
4685 | * @bp: driver handle | |
4686 | * @global: true if there was a global attention | |
4687 | * @print: show parity attention in syslog | |
4688 | */ | |
4689 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 4690 | { |
8736c826 | 4691 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
4692 | int port = BP_PORT(bp); |
4693 | ||
4694 | attn.sig[0] = REG_RD(bp, | |
4695 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
4696 | port*4); | |
4697 | attn.sig[1] = REG_RD(bp, | |
4698 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
4699 | port*4); | |
4700 | attn.sig[2] = REG_RD(bp, | |
4701 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
4702 | port*4); | |
4703 | attn.sig[3] = REG_RD(bp, | |
4704 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
4705 | port*4); | |
4706 | ||
8736c826 VZ |
4707 | if (!CHIP_IS_E1x(bp)) |
4708 | attn.sig[4] = REG_RD(bp, | |
4709 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
4710 | port*4); | |
4711 | ||
4712 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
4713 | } |
4714 | ||
1191cb83 | 4715 | static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) |
f2e0899f DK |
4716 | { |
4717 | u32 val; | |
4718 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
4719 | ||
4720 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
4721 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
4722 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
51c1a580 | 4723 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
f2e0899f | 4724 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
51c1a580 | 4725 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
f2e0899f | 4726 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
51c1a580 | 4727 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
f2e0899f | 4728 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
51c1a580 | 4729 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
f2e0899f DK |
4730 | if (val & |
4731 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
51c1a580 | 4732 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
f2e0899f DK |
4733 | if (val & |
4734 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
51c1a580 | 4735 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
f2e0899f | 4736 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
51c1a580 | 4737 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
f2e0899f | 4738 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
51c1a580 | 4739 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
f2e0899f | 4740 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
51c1a580 | 4741 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
f2e0899f DK |
4742 | } |
4743 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
4744 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
4745 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
4746 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
4747 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
4748 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
51c1a580 | 4749 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
f2e0899f | 4750 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
51c1a580 | 4751 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
f2e0899f | 4752 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
51c1a580 | 4753 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
f2e0899f DK |
4754 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
4755 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
4756 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
51c1a580 | 4757 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
f2e0899f DK |
4758 | } |
4759 | ||
4760 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4761 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
4762 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
4763 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4764 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
4765 | } | |
f2e0899f DK |
4766 | } |
4767 | ||
72fd0718 VZ |
4768 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
4769 | { | |
4770 | struct attn_route attn, *group_mask; | |
34f80b04 | 4771 | int port = BP_PORT(bp); |
877e9aa4 | 4772 | int index; |
a2fbb9ea ET |
4773 | u32 reg_addr; |
4774 | u32 val; | |
3fcaf2e5 | 4775 | u32 aeu_mask; |
c9ee9206 | 4776 | bool global = false; |
a2fbb9ea ET |
4777 | |
4778 | /* need to take HW lock because MCP or other port might also | |
4779 | try to handle this event */ | |
4a37fb66 | 4780 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 4781 | |
c9ee9206 VZ |
4782 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
4783 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 4784 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 4785 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
4786 | /* Disable HW interrupts */ |
4787 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
4788 | /* In case of parity errors don't handle attentions so that |
4789 | * other function would "see" parity errors. | |
4790 | */ | |
c9ee9206 VZ |
4791 | #else |
4792 | bnx2x_panic(); | |
4793 | #endif | |
4794 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
4795 | return; |
4796 | } | |
4797 | ||
a2fbb9ea ET |
4798 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
4799 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
4800 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
4801 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 4802 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4803 | attn.sig[4] = |
4804 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
4805 | else | |
4806 | attn.sig[4] = 0; | |
4807 | ||
4808 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
4809 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
4810 | |
4811 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
4812 | if (deasserted & (1 << index)) { | |
72fd0718 | 4813 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 4814 | |
51c1a580 | 4815 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
f2e0899f DK |
4816 | index, |
4817 | group_mask->sig[0], group_mask->sig[1], | |
4818 | group_mask->sig[2], group_mask->sig[3], | |
4819 | group_mask->sig[4]); | |
a2fbb9ea | 4820 | |
f2e0899f DK |
4821 | bnx2x_attn_int_deasserted4(bp, |
4822 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 4823 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 4824 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 4825 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 4826 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 4827 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 4828 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 4829 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 4830 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
4831 | } |
4832 | } | |
4833 | ||
4a37fb66 | 4834 | bnx2x_release_alr(bp); |
a2fbb9ea | 4835 | |
f2e0899f DK |
4836 | if (bp->common.int_block == INT_BLOCK_HC) |
4837 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4838 | COMMAND_REG_ATTN_BITS_CLR); | |
4839 | else | |
4840 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
4841 | |
4842 | val = ~deasserted; | |
f2e0899f DK |
4843 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
4844 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 4845 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 4846 | |
a2fbb9ea | 4847 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 4848 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
4849 | |
4850 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
4851 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
4852 | ||
3fcaf2e5 EG |
4853 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4854 | aeu_mask = REG_RD(bp, reg_addr); | |
4855 | ||
4856 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
4857 | aeu_mask, deasserted); | |
72fd0718 | 4858 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 4859 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4860 | |
3fcaf2e5 EG |
4861 | REG_WR(bp, reg_addr, aeu_mask); |
4862 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
4863 | |
4864 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
4865 | bp->attn_state &= ~deasserted; | |
4866 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
4867 | } | |
4868 | ||
4869 | static void bnx2x_attn_int(struct bnx2x *bp) | |
4870 | { | |
4871 | /* read local copy of bits */ | |
68d59484 EG |
4872 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
4873 | attn_bits); | |
4874 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
4875 | attn_bits_ack); | |
a2fbb9ea ET |
4876 | u32 attn_state = bp->attn_state; |
4877 | ||
4878 | /* look for changed bits */ | |
4879 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
4880 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
4881 | ||
4882 | DP(NETIF_MSG_HW, | |
4883 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
4884 | attn_bits, attn_ack, asserted, deasserted); | |
4885 | ||
4886 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 4887 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
4888 | |
4889 | /* handle bits that were raised */ | |
4890 | if (asserted) | |
4891 | bnx2x_attn_int_asserted(bp, asserted); | |
4892 | ||
4893 | if (deasserted) | |
4894 | bnx2x_attn_int_deasserted(bp, deasserted); | |
4895 | } | |
4896 | ||
619c5cb6 VZ |
4897 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
4898 | u16 index, u8 op, u8 update) | |
4899 | { | |
dc1ba591 AE |
4900 | u32 igu_addr = bp->igu_base_addr; |
4901 | igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
619c5cb6 VZ |
4902 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, |
4903 | igu_addr); | |
4904 | } | |
4905 | ||
1191cb83 | 4906 | static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
523224a3 DK |
4907 | { |
4908 | /* No memory barriers */ | |
4909 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
4910 | mmiowb(); /* keep prod updates ordered */ | |
4911 | } | |
4912 | ||
523224a3 DK |
4913 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, |
4914 | union event_ring_elem *elem) | |
4915 | { | |
619c5cb6 VZ |
4916 | u8 err = elem->message.error; |
4917 | ||
523224a3 | 4918 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
4919 | (cid < bp->cnic_eth_dev.starting_cid && |
4920 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
4921 | return 1; |
4922 | ||
4923 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
4924 | ||
619c5cb6 VZ |
4925 | if (unlikely(err)) { |
4926 | ||
523224a3 DK |
4927 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
4928 | cid); | |
823e1d90 | 4929 | bnx2x_panic_dump(bp, false); |
523224a3 | 4930 | } |
619c5cb6 | 4931 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
4932 | return 0; |
4933 | } | |
523224a3 | 4934 | |
1191cb83 | 4935 | static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
4936 | { |
4937 | struct bnx2x_mcast_ramrod_params rparam; | |
4938 | int rc; | |
4939 | ||
4940 | memset(&rparam, 0, sizeof(rparam)); | |
4941 | ||
4942 | rparam.mcast_obj = &bp->mcast_obj; | |
4943 | ||
4944 | netif_addr_lock_bh(bp->dev); | |
4945 | ||
4946 | /* Clear pending state for the last command */ | |
4947 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
4948 | ||
4949 | /* If there are pending mcast commands - send them */ | |
4950 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
4951 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
4952 | if (rc < 0) | |
4953 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
4954 | rc); | |
4955 | } | |
4956 | ||
4957 | netif_addr_unlock_bh(bp->dev); | |
4958 | } | |
4959 | ||
1191cb83 ED |
4960 | static void bnx2x_handle_classification_eqe(struct bnx2x *bp, |
4961 | union event_ring_elem *elem) | |
619c5cb6 VZ |
4962 | { |
4963 | unsigned long ramrod_flags = 0; | |
4964 | int rc = 0; | |
4965 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
4966 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
4967 | ||
4968 | /* Always push next commands out, don't wait here */ | |
4969 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
4970 | ||
86564c3f YM |
4971 | switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo) |
4972 | >> BNX2X_SWCID_SHIFT) { | |
619c5cb6 | 4973 | case BNX2X_FILTER_MAC_PENDING: |
51c1a580 | 4974 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
55c11941 | 4975 | if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) |
619c5cb6 VZ |
4976 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; |
4977 | else | |
15192a8c | 4978 | vlan_mac_obj = &bp->sp_objs[cid].mac_obj; |
619c5cb6 VZ |
4979 | |
4980 | break; | |
619c5cb6 | 4981 | case BNX2X_FILTER_MCAST_PENDING: |
51c1a580 | 4982 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
619c5cb6 VZ |
4983 | /* This is only relevant for 57710 where multicast MACs are |
4984 | * configured as unicast MACs using the same ramrod. | |
4985 | */ | |
4986 | bnx2x_handle_mcast_eqe(bp); | |
4987 | return; | |
4988 | default: | |
4989 | BNX2X_ERR("Unsupported classification command: %d\n", | |
4990 | elem->message.data.eth_event.echo); | |
4991 | return; | |
4992 | } | |
4993 | ||
4994 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
4995 | ||
4996 | if (rc < 0) | |
4997 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
4998 | else if (rc > 0) | |
4999 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
619c5cb6 VZ |
5000 | } |
5001 | ||
619c5cb6 | 5002 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); |
619c5cb6 | 5003 | |
1191cb83 | 5004 | static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
5005 | { |
5006 | netif_addr_lock_bh(bp->dev); | |
5007 | ||
5008 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5009 | ||
5010 | /* Send rx_mode command again if was requested */ | |
5011 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
5012 | bnx2x_set_storm_rx_mode(bp); | |
619c5cb6 VZ |
5013 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, |
5014 | &bp->sp_state)) | |
5015 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
5016 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
5017 | &bp->sp_state)) | |
5018 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
619c5cb6 VZ |
5019 | |
5020 | netif_addr_unlock_bh(bp->dev); | |
5021 | } | |
5022 | ||
1191cb83 | 5023 | static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, |
a3348722 BW |
5024 | union event_ring_elem *elem) |
5025 | { | |
5026 | if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { | |
5027 | DP(BNX2X_MSG_SP, | |
5028 | "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", | |
5029 | elem->message.data.vif_list_event.func_bit_map); | |
5030 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, | |
5031 | elem->message.data.vif_list_event.func_bit_map); | |
5032 | } else if (elem->message.data.vif_list_event.echo == | |
5033 | VIF_LIST_RULE_SET) { | |
5034 | DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); | |
5035 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); | |
5036 | } | |
5037 | } | |
5038 | ||
5039 | /* called with rtnl_lock */ | |
1191cb83 | 5040 | static void bnx2x_after_function_update(struct bnx2x *bp) |
a3348722 BW |
5041 | { |
5042 | int q, rc; | |
5043 | struct bnx2x_fastpath *fp; | |
5044 | struct bnx2x_queue_state_params queue_params = {NULL}; | |
5045 | struct bnx2x_queue_update_params *q_update_params = | |
5046 | &queue_params.params.update; | |
5047 | ||
2de67439 | 5048 | /* Send Q update command with afex vlan removal values for all Qs */ |
a3348722 BW |
5049 | queue_params.cmd = BNX2X_Q_CMD_UPDATE; |
5050 | ||
5051 | /* set silent vlan removal values according to vlan mode */ | |
5052 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | |
5053 | &q_update_params->update_flags); | |
5054 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
5055 | &q_update_params->update_flags); | |
5056 | __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
5057 | ||
5058 | /* in access mode mark mask and value are 0 to strip all vlans */ | |
5059 | if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { | |
5060 | q_update_params->silent_removal_value = 0; | |
5061 | q_update_params->silent_removal_mask = 0; | |
5062 | } else { | |
5063 | q_update_params->silent_removal_value = | |
5064 | (bp->afex_def_vlan_tag & VLAN_VID_MASK); | |
5065 | q_update_params->silent_removal_mask = VLAN_VID_MASK; | |
5066 | } | |
5067 | ||
5068 | for_each_eth_queue(bp, q) { | |
5069 | /* Set the appropriate Queue object */ | |
5070 | fp = &bp->fp[q]; | |
15192a8c | 5071 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
5072 | |
5073 | /* send the ramrod */ | |
5074 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
5075 | if (rc < 0) | |
5076 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
5077 | q); | |
5078 | } | |
5079 | ||
fea75645 | 5080 | if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { |
65565884 | 5081 | fp = &bp->fp[FCOE_IDX(bp)]; |
15192a8c | 5082 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
5083 | |
5084 | /* clear pending completion bit */ | |
5085 | __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
5086 | ||
5087 | /* mark latest Q bit */ | |
5088 | smp_mb__before_clear_bit(); | |
5089 | set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
5090 | smp_mb__after_clear_bit(); | |
5091 | ||
5092 | /* send Q update ramrod for FCoE Q */ | |
5093 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
5094 | if (rc < 0) | |
5095 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
5096 | q); | |
5097 | } else { | |
5098 | /* If no FCoE ring - ACK MCP now */ | |
5099 | bnx2x_link_report(bp); | |
5100 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5101 | } | |
a3348722 BW |
5102 | } |
5103 | ||
1191cb83 | 5104 | static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( |
619c5cb6 VZ |
5105 | struct bnx2x *bp, u32 cid) |
5106 | { | |
94f05b0f | 5107 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
55c11941 MS |
5108 | |
5109 | if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) | |
15192a8c | 5110 | return &bnx2x_fcoe_sp_obj(bp, q_obj); |
619c5cb6 | 5111 | else |
15192a8c | 5112 | return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; |
619c5cb6 VZ |
5113 | } |
5114 | ||
523224a3 DK |
5115 | static void bnx2x_eq_int(struct bnx2x *bp) |
5116 | { | |
5117 | u16 hw_cons, sw_cons, sw_prod; | |
5118 | union event_ring_elem *elem; | |
55c11941 | 5119 | u8 echo; |
523224a3 DK |
5120 | u32 cid; |
5121 | u8 opcode; | |
fd1fc79d | 5122 | int rc, spqe_cnt = 0; |
619c5cb6 VZ |
5123 | struct bnx2x_queue_sp_obj *q_obj; |
5124 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
5125 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
5126 | |
5127 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
5128 | ||
5129 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
16a5fd92 | 5130 | * when we get the next-page we need to adjust so the loop |
523224a3 DK |
5131 | * condition below will be met. The next element is the size of a |
5132 | * regular element and hence incrementing by 1 | |
5133 | */ | |
5134 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
5135 | hw_cons++; | |
5136 | ||
25985edc | 5137 | /* This function may never run in parallel with itself for a |
523224a3 DK |
5138 | * specific bp, thus there is no need in "paired" read memory |
5139 | * barrier here. | |
5140 | */ | |
5141 | sw_cons = bp->eq_cons; | |
5142 | sw_prod = bp->eq_prod; | |
5143 | ||
d6cae238 | 5144 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 5145 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
5146 | |
5147 | for (; sw_cons != hw_cons; | |
5148 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
5149 | ||
523224a3 DK |
5150 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; |
5151 | ||
fd1fc79d AE |
5152 | rc = bnx2x_iov_eq_sp_event(bp, elem); |
5153 | if (!rc) { | |
5154 | DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", | |
5155 | rc); | |
5156 | goto next_spqe; | |
5157 | } | |
523224a3 | 5158 | |
86564c3f YM |
5159 | /* elem CID originates from FW; actually LE */ |
5160 | cid = SW_CID((__force __le32) | |
5161 | elem->message.data.cfc_del_event.cid); | |
5162 | opcode = elem->message.opcode; | |
523224a3 DK |
5163 | |
5164 | /* handle eq element */ | |
5165 | switch (opcode) { | |
fd1fc79d AE |
5166 | case EVENT_RING_OPCODE_VF_PF_CHANNEL: |
5167 | DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n"); | |
5168 | bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event); | |
5169 | continue; | |
5170 | ||
523224a3 | 5171 | case EVENT_RING_OPCODE_STAT_QUERY: |
51c1a580 MS |
5172 | DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, |
5173 | "got statistics comp event %d\n", | |
619c5cb6 | 5174 | bp->stats_comp++); |
523224a3 | 5175 | /* nothing to do with stats comp */ |
d6cae238 | 5176 | goto next_spqe; |
523224a3 DK |
5177 | |
5178 | case EVENT_RING_OPCODE_CFC_DEL: | |
5179 | /* handle according to cid range */ | |
5180 | /* | |
5181 | * we may want to verify here that the bp state is | |
5182 | * HALTING | |
5183 | */ | |
d6cae238 | 5184 | DP(BNX2X_MSG_SP, |
523224a3 | 5185 | "got delete ramrod for MULTI[%d]\n", cid); |
55c11941 MS |
5186 | |
5187 | if (CNIC_LOADED(bp) && | |
5188 | !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
523224a3 | 5189 | goto next_spqe; |
55c11941 | 5190 | |
619c5cb6 VZ |
5191 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
5192 | ||
5193 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
5194 | break; | |
5195 | ||
523224a3 | 5196 | goto next_spqe; |
e4901dde VZ |
5197 | |
5198 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
51c1a580 | 5199 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
6debea87 DK |
5200 | if (f_obj->complete_cmd(bp, f_obj, |
5201 | BNX2X_F_CMD_TX_STOP)) | |
5202 | break; | |
e4901dde VZ |
5203 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
5204 | goto next_spqe; | |
619c5cb6 | 5205 | |
e4901dde | 5206 | case EVENT_RING_OPCODE_START_TRAFFIC: |
51c1a580 | 5207 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
6debea87 DK |
5208 | if (f_obj->complete_cmd(bp, f_obj, |
5209 | BNX2X_F_CMD_TX_START)) | |
5210 | break; | |
e4901dde VZ |
5211 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
5212 | goto next_spqe; | |
55c11941 | 5213 | |
a3348722 | 5214 | case EVENT_RING_OPCODE_FUNCTION_UPDATE: |
55c11941 MS |
5215 | echo = elem->message.data.function_update_event.echo; |
5216 | if (echo == SWITCH_UPDATE) { | |
5217 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, | |
5218 | "got FUNC_SWITCH_UPDATE ramrod\n"); | |
5219 | if (f_obj->complete_cmd( | |
5220 | bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) | |
5221 | break; | |
a3348722 | 5222 | |
55c11941 MS |
5223 | } else { |
5224 | DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, | |
5225 | "AFEX: ramrod completed FUNCTION_UPDATE\n"); | |
5226 | f_obj->complete_cmd(bp, f_obj, | |
5227 | BNX2X_F_CMD_AFEX_UPDATE); | |
5228 | ||
5229 | /* We will perform the Queues update from | |
5230 | * sp_rtnl task as all Queue SP operations | |
5231 | * should run under rtnl_lock. | |
5232 | */ | |
5233 | smp_mb__before_clear_bit(); | |
5234 | set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, | |
5235 | &bp->sp_rtnl_state); | |
5236 | smp_mb__after_clear_bit(); | |
5237 | ||
5238 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
5239 | } | |
a3348722 | 5240 | |
a3348722 BW |
5241 | goto next_spqe; |
5242 | ||
5243 | case EVENT_RING_OPCODE_AFEX_VIF_LISTS: | |
5244 | f_obj->complete_cmd(bp, f_obj, | |
5245 | BNX2X_F_CMD_AFEX_VIFLISTS); | |
5246 | bnx2x_after_afex_vif_lists(bp, elem); | |
5247 | goto next_spqe; | |
619c5cb6 | 5248 | case EVENT_RING_OPCODE_FUNCTION_START: |
51c1a580 MS |
5249 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5250 | "got FUNC_START ramrod\n"); | |
619c5cb6 VZ |
5251 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
5252 | break; | |
5253 | ||
5254 | goto next_spqe; | |
5255 | ||
5256 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
51c1a580 MS |
5257 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5258 | "got FUNC_STOP ramrod\n"); | |
619c5cb6 VZ |
5259 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
5260 | break; | |
5261 | ||
5262 | goto next_spqe; | |
523224a3 DK |
5263 | } |
5264 | ||
5265 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
5266 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
5267 | BNX2X_STATE_OPEN): | |
5268 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 5269 | BNX2X_STATE_OPENING_WAIT4_PORT): |
619c5cb6 VZ |
5270 | cid = elem->message.data.eth_event.echo & |
5271 | BNX2X_SWCID_MASK; | |
d6cae238 | 5272 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
619c5cb6 VZ |
5273 | cid); |
5274 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
5275 | break; |
5276 | ||
619c5cb6 VZ |
5277 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
5278 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
5279 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 5280 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
5281 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
5282 | BNX2X_STATE_OPEN): | |
5283 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5284 | BNX2X_STATE_DIAG): | |
5285 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5286 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5287 | DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); |
619c5cb6 | 5288 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
5289 | break; |
5290 | ||
619c5cb6 VZ |
5291 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
5292 | BNX2X_STATE_OPEN): | |
5293 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5294 | BNX2X_STATE_DIAG): | |
5295 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5296 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5297 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 5298 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
5299 | break; |
5300 | ||
619c5cb6 VZ |
5301 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
5302 | BNX2X_STATE_OPEN): | |
5303 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
5304 | BNX2X_STATE_DIAG): | |
5305 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 5306 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 5307 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 5308 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
5309 | break; |
5310 | default: | |
5311 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
5312 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
5313 | elem->message.opcode, bp->state); | |
523224a3 DK |
5314 | } |
5315 | next_spqe: | |
5316 | spqe_cnt++; | |
5317 | } /* for */ | |
5318 | ||
8fe23fbd | 5319 | smp_mb__before_atomic_inc(); |
6e30dd4e | 5320 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
5321 | |
5322 | bp->eq_cons = sw_cons; | |
5323 | bp->eq_prod = sw_prod; | |
5324 | /* Make sure that above mem writes were issued towards the memory */ | |
5325 | smp_wmb(); | |
5326 | ||
5327 | /* update producer */ | |
5328 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
5329 | } | |
5330 | ||
a2fbb9ea ET |
5331 | static void bnx2x_sp_task(struct work_struct *work) |
5332 | { | |
1cf167f2 | 5333 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea | 5334 | |
fd1fc79d | 5335 | DP(BNX2X_MSG_SP, "sp task invoked\n"); |
a2fbb9ea | 5336 | |
16a5fd92 | 5337 | /* make sure the atomic interrupt_occurred has been written */ |
fd1fc79d AE |
5338 | smp_rmb(); |
5339 | if (atomic_read(&bp->interrupt_occurred)) { | |
a2fbb9ea | 5340 | |
fd1fc79d AE |
5341 | /* what work needs to be performed? */ |
5342 | u16 status = bnx2x_update_dsb_idx(bp); | |
cdaa7cb8 | 5343 | |
fd1fc79d AE |
5344 | DP(BNX2X_MSG_SP, "status %x\n", status); |
5345 | DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); | |
5346 | atomic_set(&bp->interrupt_occurred, 0); | |
5347 | ||
5348 | /* HW attentions */ | |
5349 | if (status & BNX2X_DEF_SB_ATT_IDX) { | |
5350 | bnx2x_attn_int(bp); | |
5351 | status &= ~BNX2X_DEF_SB_ATT_IDX; | |
5352 | } | |
5353 | ||
5354 | /* SP events: STAT_QUERY and others */ | |
5355 | if (status & BNX2X_DEF_SB_IDX) { | |
5356 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 5357 | |
55c11941 | 5358 | if (FCOE_INIT(bp) && |
fd1fc79d AE |
5359 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
5360 | /* Prevent local bottom-halves from running as | |
5361 | * we are going to change the local NAPI list. | |
5362 | */ | |
5363 | local_bh_disable(); | |
5364 | napi_schedule(&bnx2x_fcoe(bp, napi)); | |
5365 | local_bh_enable(); | |
5366 | } | |
5367 | ||
5368 | /* Handle EQ completions */ | |
5369 | bnx2x_eq_int(bp); | |
5370 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
5371 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
5372 | ||
5373 | status &= ~BNX2X_DEF_SB_IDX; | |
019dbb4c | 5374 | } |
55c11941 | 5375 | |
fd1fc79d AE |
5376 | /* if status is non zero then perhaps something went wrong */ |
5377 | if (unlikely(status)) | |
5378 | DP(BNX2X_MSG_SP, | |
5379 | "got an unknown interrupt! (status 0x%x)\n", status); | |
523224a3 | 5380 | |
fd1fc79d AE |
5381 | /* ack status block only if something was actually handled */ |
5382 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, | |
5383 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
cdaa7cb8 VZ |
5384 | } |
5385 | ||
fd1fc79d AE |
5386 | /* must be called after the EQ processing (since eq leads to sriov |
5387 | * ramrod completion flows). | |
5388 | * This flow may have been scheduled by the arrival of a ramrod | |
5389 | * completion, or by the sriov code rescheduling itself. | |
5390 | */ | |
5391 | bnx2x_iov_sp_task(bp); | |
a3348722 BW |
5392 | |
5393 | /* afex - poll to check if VIFSET_ACK should be sent to MFW */ | |
5394 | if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, | |
5395 | &bp->sp_state)) { | |
5396 | bnx2x_link_report(bp); | |
5397 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5398 | } | |
a2fbb9ea ET |
5399 | } |
5400 | ||
9f6c9258 | 5401 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
5402 | { |
5403 | struct net_device *dev = dev_instance; | |
5404 | struct bnx2x *bp = netdev_priv(dev); | |
5405 | ||
523224a3 DK |
5406 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
5407 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
5408 | |
5409 | #ifdef BNX2X_STOP_ON_ERROR | |
5410 | if (unlikely(bp->panic)) | |
5411 | return IRQ_HANDLED; | |
5412 | #endif | |
5413 | ||
55c11941 | 5414 | if (CNIC_LOADED(bp)) { |
993ac7b5 MC |
5415 | struct cnic_ops *c_ops; |
5416 | ||
5417 | rcu_read_lock(); | |
5418 | c_ops = rcu_dereference(bp->cnic_ops); | |
5419 | if (c_ops) | |
5420 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
5421 | rcu_read_unlock(); | |
5422 | } | |
55c11941 | 5423 | |
fd1fc79d AE |
5424 | /* schedule sp task to perform default status block work, ack |
5425 | * attentions and enable interrupts. | |
5426 | */ | |
5427 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
5428 | |
5429 | return IRQ_HANDLED; | |
5430 | } | |
5431 | ||
5432 | /* end of slow path */ | |
5433 | ||
619c5cb6 VZ |
5434 | void bnx2x_drv_pulse(struct bnx2x *bp) |
5435 | { | |
5436 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
5437 | bp->fw_drv_pulse_wr_seq); | |
5438 | } | |
5439 | ||
a2fbb9ea ET |
5440 | static void bnx2x_timer(unsigned long data) |
5441 | { | |
5442 | struct bnx2x *bp = (struct bnx2x *) data; | |
5443 | ||
5444 | if (!netif_running(bp->dev)) | |
5445 | return; | |
5446 | ||
67c431a5 AE |
5447 | if (IS_PF(bp) && |
5448 | !BP_NOMCP(bp)) { | |
f2e0899f | 5449 | int mb_idx = BP_FW_MB_IDX(bp); |
a2fbb9ea ET |
5450 | u32 drv_pulse; |
5451 | u32 mcp_pulse; | |
5452 | ||
5453 | ++bp->fw_drv_pulse_wr_seq; | |
5454 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
5455 | /* TBD - add SYSTEM_TIME */ | |
5456 | drv_pulse = bp->fw_drv_pulse_wr_seq; | |
619c5cb6 | 5457 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 5458 | |
f2e0899f | 5459 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
5460 | MCP_PULSE_SEQ_MASK); |
5461 | /* The delta between driver pulse and mcp response | |
5462 | * should be 1 (before mcp response) or 0 (after mcp response) | |
5463 | */ | |
5464 | if ((drv_pulse != mcp_pulse) && | |
5465 | (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { | |
5466 | /* someone lost a heartbeat... */ | |
5467 | BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
5468 | drv_pulse, mcp_pulse); | |
5469 | } | |
5470 | } | |
5471 | ||
f34d28ea | 5472 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 5473 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 5474 | |
abc5a021 | 5475 | /* sample pf vf bulletin board for new posts from pf */ |
37173488 YM |
5476 | if (IS_VF(bp)) |
5477 | bnx2x_timer_sriov(bp); | |
78c3bcc5 | 5478 | |
a2fbb9ea ET |
5479 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
5480 | } | |
5481 | ||
5482 | /* end of Statistics */ | |
5483 | ||
5484 | /* nic init */ | |
5485 | ||
5486 | /* | |
5487 | * nic init service functions | |
5488 | */ | |
5489 | ||
1191cb83 | 5490 | static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 5491 | { |
523224a3 DK |
5492 | u32 i; |
5493 | if (!(len%4) && !(addr%4)) | |
5494 | for (i = 0; i < len; i += 4) | |
5495 | REG_WR(bp, addr + i, fill); | |
5496 | else | |
5497 | for (i = 0; i < len; i++) | |
5498 | REG_WR8(bp, addr + i, fill); | |
34f80b04 EG |
5499 | } |
5500 | ||
523224a3 | 5501 | /* helper: writes FP SP data to FW - data_size in dwords */ |
1191cb83 ED |
5502 | static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, |
5503 | int fw_sb_id, | |
5504 | u32 *sb_data_p, | |
5505 | u32 data_size) | |
34f80b04 | 5506 | { |
a2fbb9ea | 5507 | int index; |
523224a3 DK |
5508 | for (index = 0; index < data_size; index++) |
5509 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5510 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
5511 | sizeof(u32)*index, | |
5512 | *(sb_data_p + index)); | |
5513 | } | |
a2fbb9ea | 5514 | |
1191cb83 | 5515 | static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
523224a3 DK |
5516 | { |
5517 | u32 *sb_data_p; | |
5518 | u32 data_size = 0; | |
f2e0899f | 5519 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 5520 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 5521 | |
523224a3 | 5522 | /* disable the function first */ |
619c5cb6 | 5523 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5524 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5525 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
5526 | sb_data_e2.common.p_func.vf_valid = false; |
5527 | sb_data_p = (u32 *)&sb_data_e2; | |
5528 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
5529 | } else { | |
5530 | memset(&sb_data_e1x, 0, | |
5531 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5532 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
5533 | sb_data_e1x.common.p_func.vf_valid = false; |
5534 | sb_data_p = (u32 *)&sb_data_e1x; | |
5535 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
5536 | } | |
523224a3 | 5537 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 5538 | |
523224a3 DK |
5539 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
5540 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
5541 | CSTORM_STATUS_BLOCK_SIZE); | |
5542 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5543 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
5544 | CSTORM_SYNC_BLOCK_SIZE); | |
5545 | } | |
34f80b04 | 5546 | |
523224a3 | 5547 | /* helper: writes SP SB data to FW */ |
1191cb83 | 5548 | static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, |
523224a3 DK |
5549 | struct hc_sp_status_block_data *sp_sb_data) |
5550 | { | |
5551 | int func = BP_FUNC(bp); | |
5552 | int i; | |
5553 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
5554 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5555 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
5556 | i*sizeof(u32), | |
5557 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
5558 | } |
5559 | ||
1191cb83 | 5560 | static void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
5561 | { |
5562 | int func = BP_FUNC(bp); | |
523224a3 DK |
5563 | struct hc_sp_status_block_data sp_sb_data; |
5564 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 5565 | |
619c5cb6 | 5566 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
5567 | sp_sb_data.p_func.vf_valid = false; |
5568 | ||
5569 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
5570 | ||
5571 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5572 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
5573 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
5574 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5575 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
5576 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
523224a3 DK |
5577 | } |
5578 | ||
1191cb83 | 5579 | static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, |
523224a3 DK |
5580 | int igu_sb_id, int igu_seg_id) |
5581 | { | |
5582 | hc_sm->igu_sb_id = igu_sb_id; | |
5583 | hc_sm->igu_seg_id = igu_seg_id; | |
5584 | hc_sm->timer_value = 0xFF; | |
5585 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
5586 | } |
5587 | ||
150966ad | 5588 | /* allocates state machine ids. */ |
1191cb83 | 5589 | static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) |
150966ad AE |
5590 | { |
5591 | /* zero out state machine indices */ | |
5592 | /* rx indices */ | |
5593 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5594 | ||
5595 | /* tx indices */ | |
5596 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5597 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
5598 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
5599 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
5600 | ||
5601 | /* map indices */ | |
5602 | /* rx indices */ | |
5603 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
5604 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5605 | ||
5606 | /* tx indices */ | |
5607 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
5608 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5609 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
5610 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5611 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
5612 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5613 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
5614 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5615 | } | |
5616 | ||
b93288d5 | 5617 | void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 5618 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 5619 | { |
523224a3 DK |
5620 | int igu_seg_id; |
5621 | ||
f2e0899f | 5622 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
5623 | struct hc_status_block_data_e1x sb_data_e1x; |
5624 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
5625 | int data_size; |
5626 | u32 *sb_data_p; | |
5627 | ||
f2e0899f DK |
5628 | if (CHIP_INT_MODE_IS_BC(bp)) |
5629 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
5630 | else | |
5631 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
5632 | |
5633 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
5634 | ||
619c5cb6 | 5635 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5636 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5637 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
5638 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
5639 | sb_data_e2.common.p_func.vf_id = vfid; | |
5640 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
5641 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
5642 | sb_data_e2.common.same_igu_sb_1b = true; | |
5643 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
5644 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
5645 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
5646 | sb_data_p = (u32 *)&sb_data_e2; |
5647 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 5648 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
5649 | } else { |
5650 | memset(&sb_data_e1x, 0, | |
5651 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5652 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
5653 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
5654 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
5655 | sb_data_e1x.common.p_func.vf_valid = false; | |
5656 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
5657 | sb_data_e1x.common.same_igu_sb_1b = true; | |
5658 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
5659 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
5660 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
5661 | sb_data_p = (u32 *)&sb_data_e1x; |
5662 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 5663 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 5664 | } |
523224a3 DK |
5665 | |
5666 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
5667 | igu_sb_id, igu_seg_id); | |
5668 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
5669 | igu_sb_id, igu_seg_id); | |
5670 | ||
51c1a580 | 5671 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
523224a3 | 5672 | |
86564c3f | 5673 | /* write indices to HW - PCI guarantees endianity of regpairs */ |
523224a3 DK |
5674 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
5675 | } | |
5676 | ||
619c5cb6 | 5677 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
5678 | u16 tx_usec, u16 rx_usec) |
5679 | { | |
6383c0b3 | 5680 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 5681 | false, rx_usec); |
6383c0b3 AE |
5682 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
5683 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
5684 | tx_usec); | |
5685 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5686 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
5687 | tx_usec); | |
5688 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5689 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
5690 | tx_usec); | |
523224a3 | 5691 | } |
f2e0899f | 5692 | |
523224a3 DK |
5693 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
5694 | { | |
5695 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
5696 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
5697 | int igu_sp_sb_index; | |
5698 | int igu_seg_id; | |
34f80b04 EG |
5699 | int port = BP_PORT(bp); |
5700 | int func = BP_FUNC(bp); | |
f2eaeb58 | 5701 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 5702 | u64 section; |
523224a3 DK |
5703 | int index; |
5704 | struct hc_sp_status_block_data sp_sb_data; | |
5705 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
5706 | ||
f2e0899f DK |
5707 | if (CHIP_INT_MODE_IS_BC(bp)) { |
5708 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
5709 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
5710 | } else { | |
5711 | igu_sp_sb_index = bp->igu_dsb_id; | |
5712 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
5713 | } | |
a2fbb9ea ET |
5714 | |
5715 | /* ATTN */ | |
523224a3 | 5716 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 5717 | atten_status_block); |
523224a3 | 5718 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 5719 | |
49d66772 ET |
5720 | bp->attn_state = 0; |
5721 | ||
a2fbb9ea ET |
5722 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
5723 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
5724 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
5725 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 5726 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
5727 | int sindex; |
5728 | /* take care of sig[0]..sig[4] */ | |
5729 | for (sindex = 0; sindex < 4; sindex++) | |
5730 | bp->attn_group[index].sig[sindex] = | |
5731 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 5732 | |
619c5cb6 | 5733 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5734 | /* |
5735 | * enable5 is separate from the rest of the registers, | |
5736 | * and therefore the address skip is 4 | |
5737 | * and not 16 between the different groups | |
5738 | */ | |
5739 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 5740 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
5741 | else |
5742 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
5743 | } |
5744 | ||
f2e0899f DK |
5745 | if (bp->common.int_block == INT_BLOCK_HC) { |
5746 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
5747 | HC_REG_ATTN_MSG0_ADDR_L); | |
5748 | ||
5749 | REG_WR(bp, reg_offset, U64_LO(section)); | |
5750 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 5751 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5752 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
5753 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
5754 | } | |
a2fbb9ea | 5755 | |
523224a3 DK |
5756 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
5757 | sp_sb); | |
a2fbb9ea | 5758 | |
523224a3 | 5759 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 5760 | |
86564c3f | 5761 | /* PCI guarantees endianity of regpairs */ |
619c5cb6 | 5762 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
5763 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
5764 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
5765 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
5766 | sp_sb_data.igu_seg_id = igu_seg_id; | |
5767 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 5768 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 5769 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 5770 | |
523224a3 | 5771 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 5772 | |
523224a3 | 5773 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
5774 | } |
5775 | ||
9f6c9258 | 5776 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 5777 | { |
a2fbb9ea ET |
5778 | int i; |
5779 | ||
ec6ba945 | 5780 | for_each_eth_queue(bp, i) |
523224a3 | 5781 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 5782 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
5783 | } |
5784 | ||
a2fbb9ea ET |
5785 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
5786 | { | |
a2fbb9ea | 5787 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 5788 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 5789 | |
a2fbb9ea | 5790 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
5791 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
5792 | bp->spq_prod_bd = bp->spq; | |
5793 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
5794 | } |
5795 | ||
523224a3 | 5796 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
5797 | { |
5798 | int i; | |
523224a3 DK |
5799 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
5800 | union event_ring_elem *elem = | |
5801 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 5802 | |
523224a3 DK |
5803 | elem->next_page.addr.hi = |
5804 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
5805 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
5806 | elem->next_page.addr.lo = | |
5807 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
5808 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 5809 | } |
523224a3 DK |
5810 | bp->eq_cons = 0; |
5811 | bp->eq_prod = NUM_EQ_DESC; | |
5812 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
16a5fd92 | 5813 | /* we want a warning message before it gets wrought... */ |
6e30dd4e VZ |
5814 | atomic_set(&bp->eq_spq_left, |
5815 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
5816 | } |
5817 | ||
619c5cb6 | 5818 | /* called with netif_addr_lock_bh() */ |
924d75ab YM |
5819 | int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
5820 | unsigned long rx_mode_flags, | |
5821 | unsigned long rx_accept_flags, | |
5822 | unsigned long tx_accept_flags, | |
5823 | unsigned long ramrod_flags) | |
ab532cf3 | 5824 | { |
619c5cb6 VZ |
5825 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
5826 | int rc; | |
5827 | ||
5828 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
5829 | ||
5830 | /* Prepare ramrod parameters */ | |
5831 | ramrod_param.cid = 0; | |
5832 | ramrod_param.cl_id = cl_id; | |
5833 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
5834 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 5835 | |
619c5cb6 VZ |
5836 | ramrod_param.pstate = &bp->sp_state; |
5837 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 5838 | |
619c5cb6 VZ |
5839 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
5840 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
5841 | ||
5842 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5843 | ||
5844 | ramrod_param.ramrod_flags = ramrod_flags; | |
5845 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
5846 | ||
5847 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
5848 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
5849 | ||
5850 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
5851 | if (rc < 0) { | |
5852 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
924d75ab | 5853 | return rc; |
619c5cb6 | 5854 | } |
924d75ab YM |
5855 | |
5856 | return 0; | |
a2fbb9ea ET |
5857 | } |
5858 | ||
86564c3f YM |
5859 | static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, |
5860 | unsigned long *rx_accept_flags, | |
5861 | unsigned long *tx_accept_flags) | |
471de716 | 5862 | { |
924d75ab YM |
5863 | /* Clear the flags first */ |
5864 | *rx_accept_flags = 0; | |
5865 | *tx_accept_flags = 0; | |
619c5cb6 | 5866 | |
924d75ab | 5867 | switch (rx_mode) { |
619c5cb6 VZ |
5868 | case BNX2X_RX_MODE_NONE: |
5869 | /* | |
5870 | * 'drop all' supersedes any accept flags that may have been | |
5871 | * passed to the function. | |
5872 | */ | |
5873 | break; | |
5874 | case BNX2X_RX_MODE_NORMAL: | |
924d75ab YM |
5875 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
5876 | __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags); | |
5877 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
5878 | |
5879 | /* internal switching mode */ | |
924d75ab YM |
5880 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
5881 | __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags); | |
5882 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 VZ |
5883 | |
5884 | break; | |
5885 | case BNX2X_RX_MODE_ALLMULTI: | |
924d75ab YM |
5886 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
5887 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); | |
5888 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
5889 | |
5890 | /* internal switching mode */ | |
924d75ab YM |
5891 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
5892 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); | |
5893 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 VZ |
5894 | |
5895 | break; | |
5896 | case BNX2X_RX_MODE_PROMISC: | |
16a5fd92 | 5897 | /* According to definition of SI mode, iface in promisc mode |
619c5cb6 VZ |
5898 | * should receive matched and unmatched (in resolution of port) |
5899 | * unicast packets. | |
5900 | */ | |
924d75ab YM |
5901 | __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags); |
5902 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); | |
5903 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); | |
5904 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
5905 | |
5906 | /* internal switching mode */ | |
924d75ab YM |
5907 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); |
5908 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 VZ |
5909 | |
5910 | if (IS_MF_SI(bp)) | |
924d75ab | 5911 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags); |
619c5cb6 | 5912 | else |
924d75ab | 5913 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
619c5cb6 VZ |
5914 | |
5915 | break; | |
5916 | default: | |
924d75ab YM |
5917 | BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode); |
5918 | return -EINVAL; | |
619c5cb6 | 5919 | } |
de832a55 | 5920 | |
924d75ab | 5921 | /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */ |
619c5cb6 | 5922 | if (bp->rx_mode != BNX2X_RX_MODE_NONE) { |
924d75ab YM |
5923 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); |
5924 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); | |
34f80b04 EG |
5925 | } |
5926 | ||
924d75ab YM |
5927 | return 0; |
5928 | } | |
5929 | ||
5930 | /* called with netif_addr_lock_bh() */ | |
5931 | int bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |
5932 | { | |
5933 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; | |
5934 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
5935 | int rc; | |
5936 | ||
5937 | if (!NO_FCOE(bp)) | |
5938 | /* Configure rx_mode of FCoE Queue */ | |
5939 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
5940 | ||
5941 | rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, | |
5942 | &tx_accept_flags); | |
5943 | if (rc) | |
5944 | return rc; | |
5945 | ||
619c5cb6 VZ |
5946 | __set_bit(RAMROD_RX, &ramrod_flags); |
5947 | __set_bit(RAMROD_TX, &ramrod_flags); | |
5948 | ||
924d75ab YM |
5949 | return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, |
5950 | rx_accept_flags, tx_accept_flags, | |
5951 | ramrod_flags); | |
619c5cb6 VZ |
5952 | } |
5953 | ||
5954 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
5955 | { | |
5956 | int i; | |
5957 | ||
0793f83f DK |
5958 | if (IS_MF_SI(bp)) |
5959 | /* | |
5960 | * In switch independent mode, the TSTORM needs to accept | |
5961 | * packets that failed classification, since approximate match | |
5962 | * mac addresses aren't written to NIG LLH | |
5963 | */ | |
5964 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5965 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); | |
619c5cb6 VZ |
5966 | else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ |
5967 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5968 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); | |
0793f83f | 5969 | |
523224a3 DK |
5970 | /* Zero this manually as its initialization is |
5971 | currently missing in the initTool */ | |
5972 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 5973 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 5974 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 5975 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5976 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
5977 | CHIP_INT_MODE_IS_BC(bp) ? | |
5978 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
5979 | } | |
523224a3 | 5980 | } |
8a1c38d1 | 5981 | |
471de716 EG |
5982 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
5983 | { | |
5984 | switch (load_code) { | |
5985 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 5986 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
5987 | bnx2x_init_internal_common(bp); |
5988 | /* no break */ | |
5989 | ||
5990 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 5991 | /* nothing to do */ |
471de716 EG |
5992 | /* no break */ |
5993 | ||
5994 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
5995 | /* internal memory per function is |
5996 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
5997 | break; |
5998 | ||
5999 | default: | |
6000 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
6001 | break; | |
6002 | } | |
6003 | } | |
6004 | ||
619c5cb6 | 6005 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 6006 | { |
55c11941 | 6007 | return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 | 6008 | } |
523224a3 | 6009 | |
619c5cb6 VZ |
6010 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
6011 | { | |
55c11941 | 6012 | return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 VZ |
6013 | } |
6014 | ||
1191cb83 | 6015 | static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) |
619c5cb6 VZ |
6016 | { |
6017 | if (CHIP_IS_E1x(fp->bp)) | |
6018 | return BP_L_ID(fp->bp) + fp->index; | |
6019 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
6020 | return bnx2x_fp_igu_sb_id(fp); | |
6021 | } | |
6022 | ||
6383c0b3 | 6023 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
6024 | { |
6025 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 6026 | u8 cos; |
619c5cb6 | 6027 | unsigned long q_type = 0; |
6383c0b3 | 6028 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 6029 | fp->rx_queue = fp_idx; |
b3b83c3f | 6030 | fp->cid = fp_idx; |
619c5cb6 VZ |
6031 | fp->cl_id = bnx2x_fp_cl_id(fp); |
6032 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
6033 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 6034 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
6035 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
6036 | ||
523224a3 | 6037 | /* init shortcut */ |
619c5cb6 | 6038 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
7a752993 | 6039 | |
16a5fd92 | 6040 | /* Setup SB indices */ |
523224a3 | 6041 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; |
523224a3 | 6042 | |
619c5cb6 VZ |
6043 | /* Configure Queue State object */ |
6044 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
6045 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
6046 | |
6047 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
6048 | ||
6049 | /* init tx data */ | |
6050 | for_each_cos_in_tx_queue(fp, cos) { | |
65565884 MS |
6051 | bnx2x_init_txdata(bp, fp->txdata_ptr[cos], |
6052 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), | |
6053 | FP_COS_TO_TXQ(fp, cos, bp), | |
6054 | BNX2X_TX_SB_INDEX_BASE + cos, fp); | |
6055 | cids[cos] = fp->txdata_ptr[cos]->cid; | |
6383c0b3 AE |
6056 | } |
6057 | ||
ad5afc89 AE |
6058 | /* nothing more for vf to do here */ |
6059 | if (IS_VF(bp)) | |
6060 | return; | |
6061 | ||
6062 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
6063 | fp->fw_sb_id, fp->igu_sb_id); | |
6064 | bnx2x_update_fpsb_idx(fp); | |
15192a8c BW |
6065 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, |
6066 | fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 6067 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 VZ |
6068 | |
6069 | /** | |
6070 | * Configure classification DBs: Always enable Tx switching | |
6071 | */ | |
6072 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
6073 | ||
ad5afc89 AE |
6074 | DP(NETIF_MSG_IFUP, |
6075 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
6076 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
6077 | fp->igu_sb_id); | |
523224a3 DK |
6078 | } |
6079 | ||
1191cb83 ED |
6080 | static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) |
6081 | { | |
6082 | int i; | |
6083 | ||
6084 | for (i = 1; i <= NUM_TX_RINGS; i++) { | |
6085 | struct eth_tx_next_bd *tx_next_bd = | |
6086 | &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
6087 | ||
6088 | tx_next_bd->addr_hi = | |
6089 | cpu_to_le32(U64_HI(txdata->tx_desc_mapping + | |
6090 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
6091 | tx_next_bd->addr_lo = | |
6092 | cpu_to_le32(U64_LO(txdata->tx_desc_mapping + | |
6093 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
6094 | } | |
6095 | ||
639d65b8 YM |
6096 | *txdata->tx_cons_sb = cpu_to_le16(0); |
6097 | ||
1191cb83 ED |
6098 | SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); |
6099 | txdata->tx_db.data.zero_fill1 = 0; | |
6100 | txdata->tx_db.data.prod = 0; | |
6101 | ||
6102 | txdata->tx_pkt_prod = 0; | |
6103 | txdata->tx_pkt_cons = 0; | |
6104 | txdata->tx_bd_prod = 0; | |
6105 | txdata->tx_bd_cons = 0; | |
6106 | txdata->tx_pkt = 0; | |
6107 | } | |
6108 | ||
55c11941 MS |
6109 | static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) |
6110 | { | |
6111 | int i; | |
6112 | ||
6113 | for_each_tx_queue_cnic(bp, i) | |
6114 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); | |
6115 | } | |
d76a6111 | 6116 | |
1191cb83 ED |
6117 | static void bnx2x_init_tx_rings(struct bnx2x *bp) |
6118 | { | |
6119 | int i; | |
6120 | u8 cos; | |
6121 | ||
55c11941 | 6122 | for_each_eth_queue(bp, i) |
1191cb83 | 6123 | for_each_cos_in_tx_queue(&bp->fp[i], cos) |
65565884 | 6124 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); |
1191cb83 ED |
6125 | } |
6126 | ||
55c11941 | 6127 | void bnx2x_nic_init_cnic(struct bnx2x *bp) |
a2fbb9ea | 6128 | { |
ec6ba945 VZ |
6129 | if (!NO_FCOE(bp)) |
6130 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
6131 | |
6132 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
6133 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 6134 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 6135 | |
55c11941 MS |
6136 | /* ensure status block indices were read */ |
6137 | rmb(); | |
6138 | bnx2x_init_rx_rings_cnic(bp); | |
6139 | bnx2x_init_tx_rings_cnic(bp); | |
6140 | ||
6141 | /* flush all */ | |
6142 | mb(); | |
6143 | mmiowb(); | |
6144 | } | |
a2fbb9ea | 6145 | |
ecf01c22 | 6146 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp) |
55c11941 MS |
6147 | { |
6148 | int i; | |
6149 | ||
ecf01c22 | 6150 | /* Setup NIC internals and enable interrupts */ |
55c11941 MS |
6151 | for_each_eth_queue(bp, i) |
6152 | bnx2x_init_eth_fp(bp, i); | |
ad5afc89 AE |
6153 | |
6154 | /* ensure status block indices were read */ | |
6155 | rmb(); | |
6156 | bnx2x_init_rx_rings(bp); | |
6157 | bnx2x_init_tx_rings(bp); | |
6158 | ||
ecf01c22 YM |
6159 | if (IS_PF(bp)) { |
6160 | /* Initialize MOD_ABS interrupts */ | |
6161 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
6162 | bp->common.shmem_base, | |
6163 | bp->common.shmem2_base, BP_PORT(bp)); | |
ad5afc89 | 6164 | |
ecf01c22 YM |
6165 | /* initialize the default status block and sp ring */ |
6166 | bnx2x_init_def_sb(bp); | |
6167 | bnx2x_update_dsb_idx(bp); | |
6168 | bnx2x_init_sp_ring(bp); | |
3cdeec22 YM |
6169 | } else { |
6170 | bnx2x_memset_stats(bp); | |
ecf01c22 YM |
6171 | } |
6172 | } | |
16119785 | 6173 | |
ecf01c22 YM |
6174 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) |
6175 | { | |
523224a3 | 6176 | bnx2x_init_eq_ring(bp); |
471de716 | 6177 | bnx2x_init_internal(bp, load_code); |
523224a3 | 6178 | bnx2x_pf_init(bp); |
0ef00459 EG |
6179 | bnx2x_stats_init(bp); |
6180 | ||
0ef00459 EG |
6181 | /* flush all before enabling interrupts */ |
6182 | mb(); | |
6183 | mmiowb(); | |
6184 | ||
615f8fd9 | 6185 | bnx2x_int_enable(bp); |
eb8da205 EG |
6186 | |
6187 | /* Check for SPIO5 */ | |
6188 | bnx2x_attn_int_deasserted0(bp, | |
6189 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
6190 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
6191 | } |
6192 | ||
ecf01c22 | 6193 | /* gzip service functions */ |
a2fbb9ea ET |
6194 | static int bnx2x_gunzip_init(struct bnx2x *bp) |
6195 | { | |
1a983142 FT |
6196 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
6197 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
6198 | if (bp->gunzip_buf == NULL) |
6199 | goto gunzip_nomem1; | |
6200 | ||
6201 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
6202 | if (bp->strm == NULL) | |
6203 | goto gunzip_nomem2; | |
6204 | ||
7ab24bfd | 6205 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
6206 | if (bp->strm->workspace == NULL) |
6207 | goto gunzip_nomem3; | |
6208 | ||
6209 | return 0; | |
6210 | ||
6211 | gunzip_nomem3: | |
6212 | kfree(bp->strm); | |
6213 | bp->strm = NULL; | |
6214 | ||
6215 | gunzip_nomem2: | |
1a983142 FT |
6216 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6217 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6218 | bp->gunzip_buf = NULL; |
6219 | ||
6220 | gunzip_nomem1: | |
51c1a580 | 6221 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
a2fbb9ea ET |
6222 | return -ENOMEM; |
6223 | } | |
6224 | ||
6225 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
6226 | { | |
b3b83c3f | 6227 | if (bp->strm) { |
7ab24bfd | 6228 | vfree(bp->strm->workspace); |
b3b83c3f DK |
6229 | kfree(bp->strm); |
6230 | bp->strm = NULL; | |
6231 | } | |
a2fbb9ea ET |
6232 | |
6233 | if (bp->gunzip_buf) { | |
1a983142 FT |
6234 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6235 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6236 | bp->gunzip_buf = NULL; |
6237 | } | |
6238 | } | |
6239 | ||
94a78b79 | 6240 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
6241 | { |
6242 | int n, rc; | |
6243 | ||
6244 | /* check gzip header */ | |
94a78b79 VZ |
6245 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
6246 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 6247 | return -EINVAL; |
94a78b79 | 6248 | } |
a2fbb9ea ET |
6249 | |
6250 | n = 10; | |
6251 | ||
34f80b04 | 6252 | #define FNAME 0x8 |
a2fbb9ea ET |
6253 | |
6254 | if (zbuf[3] & FNAME) | |
6255 | while ((zbuf[n++] != 0) && (n < len)); | |
6256 | ||
94a78b79 | 6257 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
6258 | bp->strm->avail_in = len - n; |
6259 | bp->strm->next_out = bp->gunzip_buf; | |
6260 | bp->strm->avail_out = FW_BUF_SIZE; | |
6261 | ||
6262 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
6263 | if (rc != Z_OK) | |
6264 | return rc; | |
6265 | ||
6266 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
6267 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
6268 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
6269 | bp->strm->msg); | |
a2fbb9ea ET |
6270 | |
6271 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
6272 | if (bp->gunzip_outlen & 0x3) | |
51c1a580 MS |
6273 | netdev_err(bp->dev, |
6274 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", | |
cdaa7cb8 | 6275 | bp->gunzip_outlen); |
a2fbb9ea ET |
6276 | bp->gunzip_outlen >>= 2; |
6277 | ||
6278 | zlib_inflateEnd(bp->strm); | |
6279 | ||
6280 | if (rc == Z_STREAM_END) | |
6281 | return 0; | |
6282 | ||
6283 | return rc; | |
6284 | } | |
6285 | ||
6286 | /* nic load/unload */ | |
6287 | ||
6288 | /* | |
34f80b04 | 6289 | * General service functions |
a2fbb9ea ET |
6290 | */ |
6291 | ||
6292 | /* send a NIG loopback debug packet */ | |
6293 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
6294 | { | |
a2fbb9ea | 6295 | u32 wb_write[3]; |
a2fbb9ea ET |
6296 | |
6297 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
6298 | wb_write[0] = 0x55555555; |
6299 | wb_write[1] = 0x55555555; | |
34f80b04 | 6300 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 6301 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6302 | |
6303 | /* NON-IP protocol */ | |
a2fbb9ea ET |
6304 | wb_write[0] = 0x09000000; |
6305 | wb_write[1] = 0x55555555; | |
34f80b04 | 6306 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 6307 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6308 | } |
6309 | ||
6310 | /* some of the internal memories | |
6311 | * are not directly readable from the driver | |
6312 | * to test them we send debug packets | |
6313 | */ | |
6314 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
6315 | { | |
6316 | int factor; | |
6317 | int count, i; | |
6318 | u32 val = 0; | |
6319 | ||
ad8d3948 | 6320 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 6321 | factor = 120; |
ad8d3948 EG |
6322 | else if (CHIP_REV_IS_EMUL(bp)) |
6323 | factor = 200; | |
6324 | else | |
a2fbb9ea | 6325 | factor = 1; |
a2fbb9ea | 6326 | |
a2fbb9ea ET |
6327 | /* Disable inputs of parser neighbor blocks */ |
6328 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6329 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6330 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6331 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6332 | |
6333 | /* Write 0 to parser credits for CFC search request */ | |
6334 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6335 | ||
6336 | /* send Ethernet packet */ | |
6337 | bnx2x_lb_pckt(bp); | |
6338 | ||
6339 | /* TODO do i reset NIG statistic? */ | |
6340 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6341 | count = 1000 * factor; | |
6342 | while (count) { | |
34f80b04 | 6343 | |
a2fbb9ea ET |
6344 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6345 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6346 | if (val == 0x10) |
6347 | break; | |
6348 | ||
639d65b8 | 6349 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6350 | count--; |
6351 | } | |
6352 | if (val != 0x10) { | |
6353 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6354 | return -1; | |
6355 | } | |
6356 | ||
6357 | /* Wait until PRS register shows 1 packet */ | |
6358 | count = 1000 * factor; | |
6359 | while (count) { | |
6360 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
6361 | if (val == 1) |
6362 | break; | |
6363 | ||
639d65b8 | 6364 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6365 | count--; |
6366 | } | |
6367 | if (val != 0x1) { | |
6368 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6369 | return -2; | |
6370 | } | |
6371 | ||
6372 | /* Reset and init BRB, PRS */ | |
34f80b04 | 6373 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 6374 | msleep(50); |
34f80b04 | 6375 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 6376 | msleep(50); |
619c5cb6 VZ |
6377 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6378 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
6379 | |
6380 | DP(NETIF_MSG_HW, "part2\n"); | |
6381 | ||
6382 | /* Disable inputs of parser neighbor blocks */ | |
6383 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6384 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6385 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6386 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6387 | |
6388 | /* Write 0 to parser credits for CFC search request */ | |
6389 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6390 | ||
6391 | /* send 10 Ethernet packets */ | |
6392 | for (i = 0; i < 10; i++) | |
6393 | bnx2x_lb_pckt(bp); | |
6394 | ||
6395 | /* Wait until NIG register shows 10 + 1 | |
6396 | packets of size 11*0x10 = 0xb0 */ | |
6397 | count = 1000 * factor; | |
6398 | while (count) { | |
34f80b04 | 6399 | |
a2fbb9ea ET |
6400 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6401 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6402 | if (val == 0xb0) |
6403 | break; | |
6404 | ||
639d65b8 | 6405 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6406 | count--; |
6407 | } | |
6408 | if (val != 0xb0) { | |
6409 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6410 | return -3; | |
6411 | } | |
6412 | ||
6413 | /* Wait until PRS register shows 2 packets */ | |
6414 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6415 | if (val != 2) | |
6416 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6417 | ||
6418 | /* Write 1 to parser credits for CFC search request */ | |
6419 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
6420 | ||
6421 | /* Wait until PRS register shows 3 packets */ | |
6422 | msleep(10 * factor); | |
6423 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6424 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6425 | if (val != 3) | |
6426 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6427 | ||
6428 | /* clear NIG EOP FIFO */ | |
6429 | for (i = 0; i < 11; i++) | |
6430 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
6431 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
6432 | if (val != 1) { | |
6433 | BNX2X_ERR("clear of NIG failed\n"); | |
6434 | return -4; | |
6435 | } | |
6436 | ||
6437 | /* Reset and init BRB, PRS, NIG */ | |
6438 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
6439 | msleep(50); | |
6440 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
6441 | msleep(50); | |
619c5cb6 VZ |
6442 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6443 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
55c11941 MS |
6444 | if (!CNIC_SUPPORT(bp)) |
6445 | /* set NIC mode */ | |
6446 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
a2fbb9ea ET |
6447 | |
6448 | /* Enable inputs of parser neighbor blocks */ | |
6449 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
6450 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
6451 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 6452 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
6453 | |
6454 | DP(NETIF_MSG_HW, "done\n"); | |
6455 | ||
6456 | return 0; /* OK */ | |
6457 | } | |
6458 | ||
4a33bc03 | 6459 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea | 6460 | { |
b343d002 YM |
6461 | u32 val; |
6462 | ||
a2fbb9ea | 6463 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); |
619c5cb6 | 6464 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6465 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
6466 | else | |
6467 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
6468 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
6469 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
6470 | /* |
6471 | * mask read length error interrupts in brb for parser | |
6472 | * (parsing unit and 'checksum and crc' unit) | |
6473 | * these errors are legal (PU reads fixed length and CAC can cause | |
6474 | * read length error on truncated packets) | |
6475 | */ | |
6476 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
6477 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
6478 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
6479 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
6480 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
6481 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
6482 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
6483 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6484 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
6485 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
6486 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
6487 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
6488 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6489 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
6490 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
6491 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
6492 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
6493 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
6494 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 6495 | |
b343d002 YM |
6496 | val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
6497 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | | |
6498 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; | |
6499 | if (!CHIP_IS_E1x(bp)) | |
6500 | val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | | |
6501 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; | |
6502 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); | |
6503 | ||
a2fbb9ea ET |
6504 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
6505 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
6506 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 6507 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
6508 | |
6509 | if (!CHIP_IS_E1x(bp)) | |
6510 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
6511 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
6512 | ||
a2fbb9ea ET |
6513 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
6514 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 6515 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 6516 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
6517 | } |
6518 | ||
81f75bbf EG |
6519 | static void bnx2x_reset_common(struct bnx2x *bp) |
6520 | { | |
619c5cb6 VZ |
6521 | u32 val = 0x1400; |
6522 | ||
81f75bbf EG |
6523 | /* reset_common */ |
6524 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6525 | 0xd3ffff7f); | |
619c5cb6 VZ |
6526 | |
6527 | if (CHIP_IS_E3(bp)) { | |
6528 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6529 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6530 | } | |
6531 | ||
6532 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
6533 | } | |
6534 | ||
6535 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
6536 | { | |
6537 | bp->dmae_ready = 0; | |
6538 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
6539 | } |
6540 | ||
573f2035 EG |
6541 | static void bnx2x_init_pxp(struct bnx2x *bp) |
6542 | { | |
6543 | u16 devctl; | |
6544 | int r_order, w_order; | |
6545 | ||
2a80eebc | 6546 | pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
6547 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
6548 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
6549 | if (bp->mrrs == -1) | |
6550 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
6551 | else { | |
6552 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
6553 | r_order = bp->mrrs; | |
6554 | } | |
6555 | ||
6556 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
6557 | } | |
fd4ef40d EG |
6558 | |
6559 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
6560 | { | |
2145a920 | 6561 | int is_required; |
fd4ef40d | 6562 | u32 val; |
2145a920 | 6563 | int port; |
fd4ef40d | 6564 | |
2145a920 VZ |
6565 | if (BP_NOMCP(bp)) |
6566 | return; | |
6567 | ||
6568 | is_required = 0; | |
fd4ef40d EG |
6569 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
6570 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
6571 | ||
6572 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
6573 | is_required = 1; | |
6574 | ||
6575 | /* | |
6576 | * The fan failure mechanism is usually related to the PHY type since | |
6577 | * the power consumption of the board is affected by the PHY. Currently, | |
6578 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
6579 | */ | |
6580 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
6581 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 6582 | is_required |= |
d90d96ba YR |
6583 | bnx2x_fan_failure_det_req( |
6584 | bp, | |
6585 | bp->common.shmem_base, | |
a22f0788 | 6586 | bp->common.shmem2_base, |
d90d96ba | 6587 | port); |
fd4ef40d EG |
6588 | } |
6589 | ||
6590 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
6591 | ||
6592 | if (is_required == 0) | |
6593 | return; | |
6594 | ||
6595 | /* Fan failure is indicated by SPIO 5 */ | |
d6d99a3f | 6596 | bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); |
fd4ef40d EG |
6597 | |
6598 | /* set to active low mode */ | |
6599 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
d6d99a3f | 6600 | val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
6601 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
6602 | ||
6603 | /* enable interrupt to signal the IGU */ | |
6604 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 6605 | val |= MISC_SPIO_SPIO5; |
fd4ef40d EG |
6606 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); |
6607 | } | |
6608 | ||
c9ee9206 | 6609 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
6610 | { |
6611 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
6612 | val &= ~IGU_PF_CONF_FUNC_EN; | |
6613 | ||
6614 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
6615 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6616 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
6617 | } | |
6618 | ||
1191cb83 | 6619 | static void bnx2x__common_init_phy(struct bnx2x *bp) |
619c5cb6 VZ |
6620 | { |
6621 | u32 shmem_base[2], shmem2_base[2]; | |
b884d95b YR |
6622 | /* Avoid common init in case MFW supports LFA */ |
6623 | if (SHMEM2_RD(bp, size) > | |
6624 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
6625 | return; | |
619c5cb6 VZ |
6626 | shmem_base[0] = bp->common.shmem_base; |
6627 | shmem2_base[0] = bp->common.shmem2_base; | |
6628 | if (!CHIP_IS_E1x(bp)) { | |
6629 | shmem_base[1] = | |
6630 | SHMEM2_RD(bp, other_shmem_base_addr); | |
6631 | shmem2_base[1] = | |
6632 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
6633 | } | |
6634 | bnx2x_acquire_phy_lock(bp); | |
6635 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
6636 | bp->common.chip_id); | |
6637 | bnx2x_release_phy_lock(bp); | |
6638 | } | |
6639 | ||
6640 | /** | |
6641 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
6642 | * | |
6643 | * @bp: driver handle | |
6644 | */ | |
6645 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 6646 | { |
619c5cb6 | 6647 | u32 val; |
a2fbb9ea | 6648 | |
51c1a580 | 6649 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 6650 | |
2031bd3a | 6651 | /* |
2de67439 | 6652 | * take the RESET lock to protect undi_unload flow from accessing |
2031bd3a DK |
6653 | * registers while we're resetting the chip |
6654 | */ | |
7a06a122 | 6655 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6656 | |
81f75bbf | 6657 | bnx2x_reset_common(bp); |
34f80b04 | 6658 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 6659 | |
619c5cb6 VZ |
6660 | val = 0xfffc; |
6661 | if (CHIP_IS_E3(bp)) { | |
6662 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6663 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6664 | } | |
6665 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
6666 | ||
7a06a122 | 6667 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6668 | |
619c5cb6 | 6669 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 6670 | |
619c5cb6 VZ |
6671 | if (!CHIP_IS_E1x(bp)) { |
6672 | u8 abs_func_id; | |
f2e0899f DK |
6673 | |
6674 | /** | |
6675 | * 4-port mode or 2-port mode we need to turn of master-enable | |
6676 | * for everyone, after that, turn it back on for self. | |
6677 | * so, we disregard multi-function or not, and always disable | |
6678 | * for all functions on the given path, this means 0,2,4,6 for | |
6679 | * path 0 and 1,3,5,7 for path 1 | |
6680 | */ | |
619c5cb6 VZ |
6681 | for (abs_func_id = BP_PATH(bp); |
6682 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
6683 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
6684 | REG_WR(bp, |
6685 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
6686 | 1); | |
6687 | continue; | |
6688 | } | |
6689 | ||
619c5cb6 | 6690 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
6691 | /* clear pf enable */ |
6692 | bnx2x_pf_disable(bp); | |
6693 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6694 | } | |
6695 | } | |
a2fbb9ea | 6696 | |
619c5cb6 | 6697 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
6698 | if (CHIP_IS_E1(bp)) { |
6699 | /* enable HW interrupt from PXP on USDM overflow | |
6700 | bit 16 on INT_MASK_0 */ | |
6701 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
6702 | } | |
a2fbb9ea | 6703 | |
619c5cb6 | 6704 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 6705 | bnx2x_init_pxp(bp); |
a2fbb9ea ET |
6706 | |
6707 | #ifdef __BIG_ENDIAN | |
34f80b04 EG |
6708 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); |
6709 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); | |
6710 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); | |
6711 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); | |
6712 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); | |
8badd27a EG |
6713 | /* make sure this value is 0 */ |
6714 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
34f80b04 EG |
6715 | |
6716 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ | |
6717 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); | |
6718 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); | |
6719 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); | |
6720 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); | |
a2fbb9ea ET |
6721 | #endif |
6722 | ||
523224a3 DK |
6723 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
6724 | ||
34f80b04 EG |
6725 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
6726 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 6727 | |
34f80b04 EG |
6728 | /* let the HW do it's magic ... */ |
6729 | msleep(100); | |
6730 | /* finish PXP init */ | |
6731 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
6732 | if (val != 1) { | |
6733 | BNX2X_ERR("PXP2 CFG failed\n"); | |
6734 | return -EBUSY; | |
6735 | } | |
6736 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
6737 | if (val != 1) { | |
6738 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
6739 | return -EBUSY; | |
6740 | } | |
a2fbb9ea | 6741 | |
f2e0899f DK |
6742 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
6743 | * have entries with value "0" and valid bit on. | |
6744 | * This needs to be done by the first PF that is loaded in a path | |
6745 | * (i.e. common phase) | |
6746 | */ | |
619c5cb6 VZ |
6747 | if (!CHIP_IS_E1x(bp)) { |
6748 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
6749 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
6750 | * This occurs when a different function (func2,3) is being marked | |
6751 | * as "scan-off". Real-life scenario for example: if a driver is being | |
6752 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
6753 | * the ilt, translate to a logical address and send a request to read/write. | |
6754 | * Since the ilt for the function that is down is not valid, this will cause | |
6755 | * a translation error which is unrecoverable. | |
6756 | * The Workaround is intended to make sure that when this happens nothing fatal | |
6757 | * will occur. The workaround: | |
6758 | * 1. First PF driver which loads on a path will: | |
6759 | * a. After taking the chip out of reset, by using pretend, | |
6760 | * it will write "0" to the following registers of | |
6761 | * the other vnics. | |
6762 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6763 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
6764 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
6765 | * And for itself it will write '1' to | |
6766 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
6767 | * dmae-operations (writing to pram for example.) | |
6768 | * note: can be done for only function 6,7 but cleaner this | |
6769 | * way. | |
6770 | * b. Write zero+valid to the entire ILT. | |
6771 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
6772 | * VNIC3 (of that port). The range allocated will be the | |
6773 | * entire ILT. This is needed to prevent ILT range error. | |
6774 | * 2. Any PF driver load flow: | |
6775 | * a. ILT update with the physical addresses of the allocated | |
6776 | * logical pages. | |
6777 | * b. Wait 20msec. - note that this timeout is needed to make | |
6778 | * sure there are no requests in one of the PXP internal | |
6779 | * queues with "old" ILT addresses. | |
6780 | * c. PF enable in the PGLC. | |
6781 | * d. Clear the was_error of the PF in the PGLC. (could have | |
2de67439 | 6782 | * occurred while driver was down) |
619c5cb6 VZ |
6783 | * e. PF enable in the CFC (WEAK + STRONG) |
6784 | * f. Timers scan enable | |
6785 | * 3. PF driver unload flow: | |
6786 | * a. Clear the Timers scan_en. | |
6787 | * b. Polling for scan_on=0 for that PF. | |
6788 | * c. Clear the PF enable bit in the PXP. | |
6789 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
6790 | * e. Write zero+valid to all ILT entries (The valid bit must | |
6791 | * stay set) | |
6792 | * f. If this is VNIC 3 of a port then also init | |
6793 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
16a5fd92 | 6794 | * to the last entry in the ILT. |
619c5cb6 VZ |
6795 | * |
6796 | * Notes: | |
6797 | * Currently the PF error in the PGLC is non recoverable. | |
6798 | * In the future the there will be a recovery routine for this error. | |
6799 | * Currently attention is masked. | |
6800 | * Having an MCP lock on the load/unload process does not guarantee that | |
6801 | * there is no Timer disable during Func6/7 enable. This is because the | |
6802 | * Timers scan is currently being cleared by the MCP on FLR. | |
6803 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
6804 | * there is error before clearing it. But the flow above is simpler and | |
6805 | * more general. | |
6806 | * All ILT entries are written by zero+valid and not just PF6/7 | |
6807 | * ILT entries since in the future the ILT entries allocation for | |
6808 | * PF-s might be dynamic. | |
6809 | */ | |
f2e0899f DK |
6810 | struct ilt_client_info ilt_cli; |
6811 | struct bnx2x_ilt ilt; | |
6812 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
6813 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
6814 | ||
b595076a | 6815 | /* initialize dummy TM client */ |
f2e0899f DK |
6816 | ilt_cli.start = 0; |
6817 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
6818 | ilt_cli.client_num = ILT_CLIENT_TM; | |
6819 | ||
6820 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
6821 | * Step 2: set the timers first/last ilt entry to point | |
6822 | * to the entire range to prevent ILT range error for 3rd/4th | |
2de67439 | 6823 | * vnic (this code assumes existence of the vnic) |
f2e0899f DK |
6824 | * |
6825 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
6826 | * with dummy TM client | |
6827 | * | |
6828 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
6829 | * and his brother are split registers | |
6830 | */ | |
6831 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
6832 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
6833 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6834 | ||
6835 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
6836 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
6837 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
6838 | } | |
6839 | ||
34f80b04 EG |
6840 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
6841 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 6842 | |
619c5cb6 | 6843 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6844 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
6845 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 6846 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 6847 | |
619c5cb6 | 6848 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
6849 | |
6850 | /* let the HW do it's magic ... */ | |
6851 | do { | |
6852 | msleep(200); | |
6853 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
6854 | } while (factor-- && (val != 1)); | |
6855 | ||
6856 | if (val != 1) { | |
6857 | BNX2X_ERR("ATC_INIT failed\n"); | |
6858 | return -EBUSY; | |
6859 | } | |
6860 | } | |
6861 | ||
619c5cb6 | 6862 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 6863 | |
b56e9670 AE |
6864 | bnx2x_iov_init_dmae(bp); |
6865 | ||
34f80b04 EG |
6866 | /* clean the DMAE memory */ |
6867 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
6868 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
6869 | ||
6870 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
6871 | ||
6872 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
6873 | ||
6874 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 6875 | |
619c5cb6 | 6876 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 6877 | |
34f80b04 EG |
6878 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
6879 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
6880 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
6881 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
6882 | ||
619c5cb6 | 6883 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 6884 | |
523224a3 DK |
6885 | /* QM queues pointers table */ |
6886 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
6887 | ||
34f80b04 EG |
6888 | /* soft reset pulse */ |
6889 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
6890 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 6891 | |
55c11941 MS |
6892 | if (CNIC_SUPPORT(bp)) |
6893 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); | |
a2fbb9ea | 6894 | |
619c5cb6 | 6895 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
523224a3 | 6896 | REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); |
619c5cb6 | 6897 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
6898 | /* enable hw interrupt from doorbell Q */ |
6899 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 6900 | |
619c5cb6 | 6901 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 6902 | |
619c5cb6 | 6903 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 6904 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 6905 | |
f2e0899f | 6906 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 6907 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 6908 | |
a3348722 BW |
6909 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { |
6910 | if (IS_MF_AFEX(bp)) { | |
6911 | /* configure that VNTag and VLAN headers must be | |
6912 | * received in afex mode | |
6913 | */ | |
6914 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); | |
6915 | REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); | |
6916 | REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); | |
6917 | REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); | |
6918 | REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); | |
6919 | } else { | |
6920 | /* Bit-map indicating which L2 hdrs may appear | |
6921 | * after the basic Ethernet header | |
6922 | */ | |
6923 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
6924 | bp->path_has_ovlan ? 7 : 6); | |
6925 | } | |
6926 | } | |
a2fbb9ea | 6927 | |
619c5cb6 VZ |
6928 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
6929 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
6930 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
6931 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 6932 | |
619c5cb6 VZ |
6933 | if (!CHIP_IS_E1x(bp)) { |
6934 | /* reset VFC memories */ | |
6935 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6936 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6937 | VFC_MEMORIES_RST_REG_RAM_RST); | |
6938 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6939 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6940 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 6941 | |
619c5cb6 VZ |
6942 | msleep(20); |
6943 | } | |
a2fbb9ea | 6944 | |
619c5cb6 VZ |
6945 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
6946 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
6947 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
6948 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 6949 | |
34f80b04 EG |
6950 | /* sync semi rtc */ |
6951 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6952 | 0x80000000); | |
6953 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
6954 | 0x80000000); | |
a2fbb9ea | 6955 | |
619c5cb6 VZ |
6956 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
6957 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
6958 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 6959 | |
a3348722 BW |
6960 | if (!CHIP_IS_E1x(bp)) { |
6961 | if (IS_MF_AFEX(bp)) { | |
6962 | /* configure that VNTag and VLAN headers must be | |
6963 | * sent in afex mode | |
6964 | */ | |
6965 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); | |
6966 | REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); | |
6967 | REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); | |
6968 | REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); | |
6969 | REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); | |
6970 | } else { | |
6971 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
6972 | bp->path_has_ovlan ? 7 : 6); | |
6973 | } | |
6974 | } | |
f2e0899f | 6975 | |
34f80b04 | 6976 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 6977 | |
619c5cb6 VZ |
6978 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
6979 | ||
55c11941 MS |
6980 | if (CNIC_SUPPORT(bp)) { |
6981 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
6982 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
6983 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
6984 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
6985 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
6986 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
6987 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
6988 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
6989 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
6990 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
6991 | } | |
34f80b04 | 6992 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 6993 | |
34f80b04 EG |
6994 | if (sizeof(union cdu_context) != 1024) |
6995 | /* we currently assume that a context is 1024 bytes */ | |
51c1a580 MS |
6996 | dev_alert(&bp->pdev->dev, |
6997 | "please adjust the size of cdu_context(%ld)\n", | |
6998 | (long)sizeof(union cdu_context)); | |
a2fbb9ea | 6999 | |
619c5cb6 | 7000 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
7001 | val = (4 << 24) + (0 << 12) + 1024; |
7002 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 7003 | |
619c5cb6 | 7004 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 7005 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
7006 | /* enable context validation interrupt from CFC */ |
7007 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
7008 | ||
7009 | /* set the thresholds to prevent CFC/CDU race */ | |
7010 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 7011 | |
619c5cb6 | 7012 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 7013 | |
619c5cb6 | 7014 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
7015 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
7016 | ||
619c5cb6 VZ |
7017 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
7018 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 7019 | |
34f80b04 EG |
7020 | /* Reset PCIE errors for debug */ |
7021 | REG_WR(bp, 0x2814, 0xffffffff); | |
7022 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 7023 | |
619c5cb6 | 7024 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7025 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
7026 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
7027 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
7028 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
7029 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
7030 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
7031 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
7032 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
7033 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
7034 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
7035 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
7036 | } | |
7037 | ||
619c5cb6 | 7038 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 7039 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
7040 | /* in E3 this done in per-port section */ |
7041 | if (!CHIP_IS_E3(bp)) | |
7042 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 7043 | } |
619c5cb6 VZ |
7044 | if (CHIP_IS_E1H(bp)) |
7045 | /* not applicable for E2 (and above ...) */ | |
7046 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
7047 | |
7048 | if (CHIP_REV_IS_SLOW(bp)) | |
7049 | msleep(200); | |
7050 | ||
7051 | /* finish CFC init */ | |
7052 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
7053 | if (val != 1) { | |
7054 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
7055 | return -EBUSY; | |
7056 | } | |
7057 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
7058 | if (val != 1) { | |
7059 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
7060 | return -EBUSY; | |
7061 | } | |
7062 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
7063 | if (val != 1) { | |
7064 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
7065 | return -EBUSY; | |
7066 | } | |
7067 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 7068 | |
f2e0899f DK |
7069 | if (CHIP_IS_E1(bp)) { |
7070 | /* read NIG statistic | |
7071 | to see if this is our first up since powerup */ | |
7072 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
7073 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 7074 | |
f2e0899f DK |
7075 | /* do internal memory self test */ |
7076 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
7077 | BNX2X_ERR("internal mem self test failed\n"); | |
7078 | return -EBUSY; | |
7079 | } | |
34f80b04 EG |
7080 | } |
7081 | ||
fd4ef40d EG |
7082 | bnx2x_setup_fan_failure_detection(bp); |
7083 | ||
34f80b04 EG |
7084 | /* clear PXP2 attentions */ |
7085 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 7086 | |
4a33bc03 | 7087 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 7088 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 7089 | |
6bbca910 | 7090 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
7091 | if (CHIP_IS_E1x(bp)) |
7092 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
7093 | } else |
7094 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
7095 | ||
34f80b04 EG |
7096 | return 0; |
7097 | } | |
a2fbb9ea | 7098 | |
619c5cb6 VZ |
7099 | /** |
7100 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
7101 | * | |
7102 | * @bp: driver handle | |
7103 | */ | |
7104 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
7105 | { | |
7106 | int rc = bnx2x_init_hw_common(bp); | |
7107 | ||
7108 | if (rc) | |
7109 | return rc; | |
7110 | ||
7111 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
7112 | if (!BP_NOMCP(bp)) | |
7113 | bnx2x__common_init_phy(bp); | |
7114 | ||
7115 | return 0; | |
7116 | } | |
7117 | ||
523224a3 | 7118 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
7119 | { |
7120 | int port = BP_PORT(bp); | |
619c5cb6 | 7121 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 7122 | u32 low, high; |
34f80b04 | 7123 | u32 val; |
a2fbb9ea | 7124 | |
51c1a580 | 7125 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
34f80b04 EG |
7126 | |
7127 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 7128 | |
619c5cb6 VZ |
7129 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
7130 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
7131 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 7132 | |
f2e0899f DK |
7133 | /* Timers bug workaround: disables the pf_master bit in pglue at |
7134 | * common phase, we need to enable it here before any dmae access are | |
7135 | * attempted. Therefore we manually added the enable-master to the | |
7136 | * port phase (it also happens in the function phase) | |
7137 | */ | |
619c5cb6 | 7138 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7139 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
7140 | ||
619c5cb6 VZ |
7141 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7142 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7143 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
7144 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7145 | ||
7146 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7147 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7148 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7149 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 7150 | |
523224a3 DK |
7151 | /* QM cid (connection) count */ |
7152 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 7153 | |
55c11941 MS |
7154 | if (CNIC_SUPPORT(bp)) { |
7155 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7156 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); | |
7157 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
7158 | } | |
cdaa7cb8 | 7159 | |
619c5cb6 | 7160 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f | 7161 | |
2b674047 DK |
7162 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
7163 | ||
f2e0899f | 7164 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { |
619c5cb6 VZ |
7165 | |
7166 | if (IS_MF(bp)) | |
7167 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
7168 | else if (bp->dev->mtu > 4096) { | |
7169 | if (bp->flags & ONE_PORT_FLAG) | |
7170 | low = 160; | |
7171 | else { | |
7172 | val = bp->dev->mtu; | |
7173 | /* (24*1024 + val*4)/256 */ | |
7174 | low = 96 + (val/64) + | |
7175 | ((val % 64) ? 1 : 0); | |
7176 | } | |
7177 | } else | |
7178 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
7179 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
7180 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
7181 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 7182 | } |
1c06328c | 7183 | |
619c5cb6 VZ |
7184 | if (CHIP_MODE_IS_4_PORT(bp)) |
7185 | REG_WR(bp, (BP_PORT(bp) ? | |
7186 | BRB1_REG_MAC_GUARANTIED_1 : | |
7187 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 7188 | |
619c5cb6 | 7189 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
a3348722 BW |
7190 | if (CHIP_IS_E3B0(bp)) { |
7191 | if (IS_MF_AFEX(bp)) { | |
7192 | /* configure headers for AFEX mode */ | |
7193 | REG_WR(bp, BP_PORT(bp) ? | |
7194 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7195 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); | |
7196 | REG_WR(bp, BP_PORT(bp) ? | |
7197 | PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : | |
7198 | PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); | |
7199 | REG_WR(bp, BP_PORT(bp) ? | |
7200 | PRS_REG_MUST_HAVE_HDRS_PORT_1 : | |
7201 | PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); | |
7202 | } else { | |
7203 | /* Ovlan exists only if we are in multi-function + | |
7204 | * switch-dependent mode, in switch-independent there | |
7205 | * is no ovlan headers | |
7206 | */ | |
7207 | REG_WR(bp, BP_PORT(bp) ? | |
7208 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7209 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
7210 | (bp->path_has_ovlan ? 7 : 6)); | |
7211 | } | |
7212 | } | |
356e2385 | 7213 | |
619c5cb6 VZ |
7214 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
7215 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7216 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7217 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 7218 | |
619c5cb6 VZ |
7219 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
7220 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7221 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7222 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 7223 | |
619c5cb6 VZ |
7224 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
7225 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 7226 | |
619c5cb6 VZ |
7227 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
7228 | ||
7229 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
7230 | /* configure PBF to work without PAUSE mtu 9000 */ |
7231 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 7232 | |
f2e0899f DK |
7233 | /* update threshold */ |
7234 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
7235 | /* update init credit */ | |
7236 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 7237 | |
f2e0899f DK |
7238 | /* probe changes */ |
7239 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
7240 | udelay(50); | |
7241 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
7242 | } | |
a2fbb9ea | 7243 | |
55c11941 MS |
7244 | if (CNIC_SUPPORT(bp)) |
7245 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7246 | ||
619c5cb6 VZ |
7247 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
7248 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
7249 | |
7250 | if (CHIP_IS_E1(bp)) { | |
7251 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7252 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7253 | } | |
619c5cb6 | 7254 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 7255 | |
619c5cb6 | 7256 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7257 | |
619c5cb6 | 7258 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 | 7259 | /* init aeu_mask_attn_func_0/1: |
16a5fd92 YM |
7260 | * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use |
7261 | * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF | |
34f80b04 | 7262 | * bits 4-7 are used for "per vn group attention" */ |
e4901dde VZ |
7263 | val = IS_MF(bp) ? 0xF7 : 0x7; |
7264 | /* Enable DCBX attention for all but E1 */ | |
7265 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
7266 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 7267 | |
619c5cb6 VZ |
7268 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
7269 | ||
7270 | if (!CHIP_IS_E1x(bp)) { | |
7271 | /* Bit-map indicating which L2 hdrs may appear after the | |
7272 | * basic Ethernet header | |
7273 | */ | |
a3348722 BW |
7274 | if (IS_MF_AFEX(bp)) |
7275 | REG_WR(bp, BP_PORT(bp) ? | |
7276 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7277 | NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); | |
7278 | else | |
7279 | REG_WR(bp, BP_PORT(bp) ? | |
7280 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7281 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
7282 | IS_MF_SD(bp) ? 7 : 6); | |
619c5cb6 VZ |
7283 | |
7284 | if (CHIP_IS_E3(bp)) | |
7285 | REG_WR(bp, BP_PORT(bp) ? | |
7286 | NIG_REG_LLH1_MF_MODE : | |
7287 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
7288 | } | |
7289 | if (!CHIP_IS_E3(bp)) | |
7290 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 7291 | |
f2e0899f | 7292 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 7293 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 7294 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 7295 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 7296 | |
619c5cb6 | 7297 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7298 | val = 0; |
7299 | switch (bp->mf_mode) { | |
7300 | case MULTI_FUNCTION_SD: | |
7301 | val = 1; | |
7302 | break; | |
7303 | case MULTI_FUNCTION_SI: | |
a3348722 | 7304 | case MULTI_FUNCTION_AFEX: |
f2e0899f DK |
7305 | val = 2; |
7306 | break; | |
7307 | } | |
7308 | ||
7309 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
7310 | NIG_REG_LLH0_CLS_TYPE), val); | |
7311 | } | |
1c06328c EG |
7312 | { |
7313 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
7314 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
7315 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
7316 | } | |
34f80b04 EG |
7317 | } |
7318 | ||
619c5cb6 VZ |
7319 | /* If SPIO5 is set to generate interrupts, enable it for this port */ |
7320 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 7321 | if (val & MISC_SPIO_SPIO5) { |
4d295db0 EG |
7322 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
7323 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
7324 | val = REG_RD(bp, reg_addr); | |
f1410647 | 7325 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 7326 | REG_WR(bp, reg_addr, val); |
f1410647 | 7327 | } |
a2fbb9ea | 7328 | |
34f80b04 EG |
7329 | return 0; |
7330 | } | |
7331 | ||
34f80b04 EG |
7332 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
7333 | { | |
7334 | int reg; | |
32d68de1 | 7335 | u32 wb_write[2]; |
34f80b04 | 7336 | |
f2e0899f | 7337 | if (CHIP_IS_E1(bp)) |
34f80b04 | 7338 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
7339 | else |
7340 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 | 7341 | |
32d68de1 YM |
7342 | wb_write[0] = ONCHIP_ADDR1(addr); |
7343 | wb_write[1] = ONCHIP_ADDR2(addr); | |
7344 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
34f80b04 EG |
7345 | } |
7346 | ||
b56e9670 | 7347 | void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) |
1191cb83 ED |
7348 | { |
7349 | u32 data, ctl, cnt = 100; | |
7350 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
7351 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
7352 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
7353 | u32 sb_bit = 1 << (idu_sb_id%32); | |
b56e9670 | 7354 | u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; |
1191cb83 ED |
7355 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; |
7356 | ||
7357 | /* Not supported in BC mode */ | |
7358 | if (CHIP_INT_MODE_IS_BC(bp)) | |
7359 | return; | |
7360 | ||
7361 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
7362 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
7363 | IGU_REGULAR_CLEANUP_SET | | |
7364 | IGU_REGULAR_BCLEANUP; | |
7365 | ||
7366 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
7367 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
7368 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
7369 | ||
7370 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7371 | data, igu_addr_data); | |
7372 | REG_WR(bp, igu_addr_data, data); | |
7373 | mmiowb(); | |
7374 | barrier(); | |
7375 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7376 | ctl, igu_addr_ctl); | |
7377 | REG_WR(bp, igu_addr_ctl, ctl); | |
7378 | mmiowb(); | |
7379 | barrier(); | |
7380 | ||
7381 | /* wait for clean up to finish */ | |
7382 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
7383 | msleep(20); | |
7384 | ||
1191cb83 ED |
7385 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { |
7386 | DP(NETIF_MSG_HW, | |
7387 | "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
7388 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
7389 | } | |
7390 | } | |
7391 | ||
7392 | static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) | |
f2e0899f | 7393 | { |
619c5cb6 | 7394 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
7395 | } |
7396 | ||
1191cb83 | 7397 | static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) |
f2e0899f DK |
7398 | { |
7399 | u32 i, base = FUNC_ILT_BASE(func); | |
7400 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
7401 | bnx2x_ilt_wr(bp, i, 0); | |
7402 | } | |
7403 | ||
910cc727 | 7404 | static void bnx2x_init_searcher(struct bnx2x *bp) |
55c11941 MS |
7405 | { |
7406 | int port = BP_PORT(bp); | |
7407 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
7408 | /* T1 hash bits value determines the T1 number of entries */ | |
7409 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
7410 | } | |
7411 | ||
7412 | static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) | |
7413 | { | |
7414 | int rc; | |
7415 | struct bnx2x_func_state_params func_params = {NULL}; | |
7416 | struct bnx2x_func_switch_update_params *switch_update_params = | |
7417 | &func_params.params.switch_update; | |
7418 | ||
7419 | /* Prepare parameters for function state transitions */ | |
7420 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7421 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
7422 | ||
7423 | func_params.f_obj = &bp->func_obj; | |
7424 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
7425 | ||
7426 | /* Function parameters */ | |
7427 | switch_update_params->suspend = suspend; | |
7428 | ||
7429 | rc = bnx2x_func_state_change(bp, &func_params); | |
7430 | ||
7431 | return rc; | |
7432 | } | |
7433 | ||
910cc727 | 7434 | static int bnx2x_reset_nic_mode(struct bnx2x *bp) |
55c11941 MS |
7435 | { |
7436 | int rc, i, port = BP_PORT(bp); | |
7437 | int vlan_en = 0, mac_en[NUM_MACS]; | |
7438 | ||
55c11941 MS |
7439 | /* Close input from network */ |
7440 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7441 | bnx2x_set_rx_filter(&bp->link_params, 0); | |
7442 | } else { | |
7443 | vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7444 | NIG_REG_LLH0_FUNC_EN); | |
7445 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7446 | NIG_REG_LLH0_FUNC_EN, 0); | |
7447 | for (i = 0; i < NUM_MACS; i++) { | |
7448 | mac_en[i] = REG_RD(bp, port ? | |
7449 | (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7450 | 4 * i) : | |
7451 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + | |
7452 | 4 * i)); | |
7453 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7454 | 4 * i) : | |
7455 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); | |
7456 | } | |
7457 | } | |
7458 | ||
7459 | /* Close BMC to host */ | |
7460 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7461 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); | |
7462 | ||
7463 | /* Suspend Tx switching to the PF. Completion of this ramrod | |
7464 | * further guarantees that all the packets of that PF / child | |
7465 | * VFs in BRB were processed by the Parser, so it is safe to | |
7466 | * change the NIC_MODE register. | |
7467 | */ | |
7468 | rc = bnx2x_func_switch_update(bp, 1); | |
7469 | if (rc) { | |
7470 | BNX2X_ERR("Can't suspend tx-switching!\n"); | |
7471 | return rc; | |
7472 | } | |
7473 | ||
7474 | /* Change NIC_MODE register */ | |
7475 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7476 | ||
7477 | /* Open input from network */ | |
7478 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7479 | bnx2x_set_rx_filter(&bp->link_params, 1); | |
7480 | } else { | |
7481 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7482 | NIG_REG_LLH0_FUNC_EN, vlan_en); | |
7483 | for (i = 0; i < NUM_MACS; i++) { | |
7484 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7485 | 4 * i) : | |
7486 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), | |
7487 | mac_en[i]); | |
7488 | } | |
7489 | } | |
7490 | ||
7491 | /* Enable BMC to host */ | |
7492 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7493 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); | |
7494 | ||
7495 | /* Resume Tx switching to the PF */ | |
7496 | rc = bnx2x_func_switch_update(bp, 0); | |
7497 | if (rc) { | |
7498 | BNX2X_ERR("Can't resume tx-switching!\n"); | |
7499 | return rc; | |
7500 | } | |
7501 | ||
7502 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7503 | return 0; | |
7504 | } | |
7505 | ||
7506 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp) | |
7507 | { | |
7508 | int rc; | |
7509 | ||
7510 | bnx2x_ilt_init_op_cnic(bp, INITOP_SET); | |
7511 | ||
7512 | if (CONFIGURE_NIC_MODE(bp)) { | |
16a5fd92 | 7513 | /* Configure searcher as part of function hw init */ |
55c11941 MS |
7514 | bnx2x_init_searcher(bp); |
7515 | ||
7516 | /* Reset NIC mode */ | |
7517 | rc = bnx2x_reset_nic_mode(bp); | |
7518 | if (rc) | |
7519 | BNX2X_ERR("Can't change NIC mode!\n"); | |
7520 | return rc; | |
7521 | } | |
7522 | ||
7523 | return 0; | |
7524 | } | |
7525 | ||
523224a3 | 7526 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
7527 | { |
7528 | int port = BP_PORT(bp); | |
7529 | int func = BP_FUNC(bp); | |
619c5cb6 | 7530 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
7531 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
7532 | u16 cdu_ilt_start; | |
8badd27a | 7533 | u32 addr, val; |
f4a66897 | 7534 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
89db4ad8 | 7535 | int i, main_mem_width, rc; |
34f80b04 | 7536 | |
51c1a580 | 7537 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
34f80b04 | 7538 | |
619c5cb6 | 7539 | /* FLR cleanup - hmmm */ |
89db4ad8 AE |
7540 | if (!CHIP_IS_E1x(bp)) { |
7541 | rc = bnx2x_pf_flr_clnup(bp); | |
04c46736 YM |
7542 | if (rc) { |
7543 | bnx2x_fw_dump(bp); | |
89db4ad8 | 7544 | return rc; |
04c46736 | 7545 | } |
89db4ad8 | 7546 | } |
619c5cb6 | 7547 | |
8badd27a | 7548 | /* set MSI reconfigure capability */ |
f2e0899f DK |
7549 | if (bp->common.int_block == INT_BLOCK_HC) { |
7550 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
7551 | val = REG_RD(bp, addr); | |
7552 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
7553 | REG_WR(bp, addr, val); | |
7554 | } | |
8badd27a | 7555 | |
619c5cb6 VZ |
7556 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
7557 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
7558 | ||
523224a3 DK |
7559 | ilt = BP_ILT(bp); |
7560 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 7561 | |
290ca2bb AE |
7562 | if (IS_SRIOV(bp)) |
7563 | cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; | |
7564 | cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); | |
7565 | ||
7566 | /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes | |
7567 | * those of the VFs, so start line should be reset | |
7568 | */ | |
7569 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
523224a3 | 7570 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
a052997e | 7571 | ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; |
523224a3 | 7572 | ilt->lines[cdu_ilt_start + i].page_mapping = |
a052997e MS |
7573 | bp->context[i].cxt_mapping; |
7574 | ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; | |
37b091ba | 7575 | } |
290ca2bb | 7576 | |
523224a3 | 7577 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 7578 | |
55c11941 MS |
7579 | if (!CONFIGURE_NIC_MODE(bp)) { |
7580 | bnx2x_init_searcher(bp); | |
7581 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7582 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7583 | } else { | |
7584 | /* Set NIC mode */ | |
7585 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6bf07b8e | 7586 | DP(NETIF_MSG_IFUP, "NIC MODE configured\n"); |
55c11941 | 7587 | } |
37b091ba | 7588 | |
619c5cb6 | 7589 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7590 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
7591 | ||
7592 | /* Turn on a single ISR mode in IGU if driver is going to use | |
7593 | * INT#x or MSI | |
7594 | */ | |
7595 | if (!(bp->flags & USING_MSIX_FLAG)) | |
7596 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
7597 | /* | |
7598 | * Timers workaround bug: function init part. | |
7599 | * Need to wait 20msec after initializing ILT, | |
7600 | * needed to make sure there are no requests in | |
7601 | * one of the PXP internal queues with "old" ILT addresses | |
7602 | */ | |
7603 | msleep(20); | |
7604 | /* | |
7605 | * Master enable - Due to WB DMAE writes performed before this | |
7606 | * register is re-initialized as part of the regular function | |
7607 | * init | |
7608 | */ | |
7609 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
7610 | /* Enable the function in IGU */ | |
7611 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
7612 | } | |
7613 | ||
523224a3 | 7614 | bp->dmae_ready = 1; |
34f80b04 | 7615 | |
619c5cb6 | 7616 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 7617 | |
619c5cb6 | 7618 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7619 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); |
7620 | ||
619c5cb6 VZ |
7621 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7622 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7623 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
7624 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7625 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
7626 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7627 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7628 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7629 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
7630 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
7631 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7632 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7633 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
7634 | ||
7635 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7636 | REG_WR(bp, QM_REG_PF_EN, 1); |
7637 | ||
619c5cb6 VZ |
7638 | if (!CHIP_IS_E1x(bp)) { |
7639 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7640 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7641 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7642 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7643 | } | |
7644 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7645 | ||
7646 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7647 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
b56e9670 AE |
7648 | |
7649 | bnx2x_iov_init_dq(bp); | |
7650 | ||
619c5cb6 VZ |
7651 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
7652 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
7653 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
7654 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7655 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7656 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
7657 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
7658 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
7659 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
7660 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7661 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
7662 | ||
619c5cb6 | 7663 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 7664 | |
619c5cb6 | 7665 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 7666 | |
619c5cb6 | 7667 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7668 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
7669 | ||
fb3bff17 | 7670 | if (IS_MF(bp)) { |
34f80b04 | 7671 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
fb3bff17 | 7672 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
34f80b04 EG |
7673 | } |
7674 | ||
619c5cb6 | 7675 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 7676 | |
34f80b04 | 7677 | /* HC init per function */ |
f2e0899f DK |
7678 | if (bp->common.int_block == INT_BLOCK_HC) { |
7679 | if (CHIP_IS_E1H(bp)) { | |
7680 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
7681 | ||
7682 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7683 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7684 | } | |
619c5cb6 | 7685 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
7686 | |
7687 | } else { | |
7688 | int num_segs, sb_idx, prod_offset; | |
7689 | ||
34f80b04 EG |
7690 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
7691 | ||
619c5cb6 | 7692 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7693 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
7694 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
7695 | } | |
7696 | ||
619c5cb6 | 7697 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7698 | |
619c5cb6 | 7699 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7700 | int dsb_idx = 0; |
7701 | /** | |
7702 | * Producer memory: | |
7703 | * E2 mode: address 0-135 match to the mapping memory; | |
7704 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
7705 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
7706 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
7707 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
7708 | * 144-147 reserved. | |
7709 | * | |
7710 | * E1.5 mode - In backward compatible mode; | |
7711 | * for non default SB; each even line in the memory | |
7712 | * holds the U producer and each odd line hold | |
7713 | * the C producer. The first 128 producers are for | |
7714 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
7715 | * producers are for the DSB for each PF. | |
7716 | * Each PF has five segments: (the order inside each | |
7717 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
7718 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
7719 | * 144-147 attn prods; | |
7720 | */ | |
7721 | /* non-default-status-blocks */ | |
7722 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7723 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
7724 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
7725 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
7726 | num_segs; | |
7727 | ||
7728 | for (i = 0; i < num_segs; i++) { | |
7729 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7730 | (prod_offset + i) * 4; | |
7731 | REG_WR(bp, addr, 0); | |
7732 | } | |
7733 | /* send consumer update with value 0 */ | |
7734 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
7735 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7736 | bnx2x_igu_clear_sb(bp, | |
7737 | bp->igu_base_sb + sb_idx); | |
7738 | } | |
7739 | ||
7740 | /* default-status-blocks */ | |
7741 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7742 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
7743 | ||
7744 | if (CHIP_MODE_IS_4_PORT(bp)) | |
7745 | dsb_idx = BP_FUNC(bp); | |
7746 | else | |
3395a033 | 7747 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
7748 | |
7749 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
7750 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
7751 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
7752 | ||
3395a033 DK |
7753 | /* |
7754 | * igu prods come in chunks of E1HVN_MAX (4) - | |
7755 | * does not matters what is the current chip mode | |
7756 | */ | |
f2e0899f DK |
7757 | for (i = 0; i < (num_segs * E1HVN_MAX); |
7758 | i += E1HVN_MAX) { | |
7759 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7760 | (prod_offset + i)*4; | |
7761 | REG_WR(bp, addr, 0); | |
7762 | } | |
7763 | /* send consumer update with 0 */ | |
7764 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
7765 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7766 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7767 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7768 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
7769 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7770 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
7771 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7772 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
7773 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7774 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7775 | } else { | |
7776 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7777 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7778 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7779 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7780 | } | |
7781 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
7782 | ||
16a5fd92 | 7783 | /* !!! These should become driver const once |
f2e0899f DK |
7784 | rf-tool supports split-68 const */ |
7785 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
7786 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
7787 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
7788 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
7789 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
7790 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
7791 | } | |
34f80b04 | 7792 | } |
34f80b04 | 7793 | |
c14423fe | 7794 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
7795 | REG_WR(bp, 0x2114, 0xffffffff); |
7796 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 7797 | |
f4a66897 VZ |
7798 | if (CHIP_IS_E1x(bp)) { |
7799 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
7800 | main_mem_base = HC_REG_MAIN_MEMORY + | |
7801 | BP_PORT(bp) * (main_mem_size * 4); | |
7802 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
7803 | main_mem_width = 8; | |
7804 | ||
7805 | val = REG_RD(bp, main_mem_prty_clr); | |
7806 | if (val) | |
51c1a580 MS |
7807 | DP(NETIF_MSG_HW, |
7808 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", | |
7809 | val); | |
f4a66897 VZ |
7810 | |
7811 | /* Clear "false" parity errors in MSI-X table */ | |
7812 | for (i = main_mem_base; | |
7813 | i < main_mem_base + main_mem_size * 4; | |
7814 | i += main_mem_width) { | |
7815 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
7816 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
7817 | i, main_mem_width / 4); | |
7818 | } | |
7819 | /* Clear HC parity attention */ | |
7820 | REG_RD(bp, main_mem_prty_clr); | |
7821 | } | |
7822 | ||
619c5cb6 VZ |
7823 | #ifdef BNX2X_STOP_ON_ERROR |
7824 | /* Enable STORMs SP logging */ | |
7825 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
7826 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7827 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
7828 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7829 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
7830 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7831 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
7832 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7833 | #endif | |
7834 | ||
b7737c9b | 7835 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 7836 | |
34f80b04 EG |
7837 | return 0; |
7838 | } | |
7839 | ||
55c11941 MS |
7840 | void bnx2x_free_mem_cnic(struct bnx2x *bp) |
7841 | { | |
7842 | bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); | |
7843 | ||
7844 | if (!CHIP_IS_E1x(bp)) | |
7845 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, | |
7846 | sizeof(struct host_hc_status_block_e2)); | |
7847 | else | |
7848 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
7849 | sizeof(struct host_hc_status_block_e1x)); | |
7850 | ||
7851 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); | |
7852 | } | |
7853 | ||
9f6c9258 | 7854 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 7855 | { |
a052997e MS |
7856 | int i; |
7857 | ||
a2fbb9ea | 7858 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, |
523224a3 | 7859 | sizeof(struct host_sp_status_block)); |
a2fbb9ea | 7860 | |
619c5cb6 VZ |
7861 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
7862 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
7863 | ||
a2fbb9ea | 7864 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 7865 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 7866 | |
a052997e MS |
7867 | for (i = 0; i < L2_ILT_LINES(bp); i++) |
7868 | BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, | |
7869 | bp->context[i].size); | |
523224a3 DK |
7870 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); |
7871 | ||
7872 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 7873 | |
7a9b2557 | 7874 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 7875 | |
523224a3 DK |
7876 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
7877 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
580d9d08 | 7878 | |
05952246 YM |
7879 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
7880 | ||
580d9d08 | 7881 | bnx2x_iov_free_mem(bp); |
619c5cb6 VZ |
7882 | } |
7883 | ||
55c11941 | 7884 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp) |
a2fbb9ea | 7885 | { |
619c5cb6 VZ |
7886 | if (!CHIP_IS_E1x(bp)) |
7887 | /* size = the status block + ramrod buffers */ | |
f2e0899f DK |
7888 | BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, |
7889 | sizeof(struct host_hc_status_block_e2)); | |
7890 | else | |
55c11941 MS |
7891 | BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, |
7892 | &bp->cnic_sb_mapping, | |
7893 | sizeof(struct | |
7894 | host_hc_status_block_e1x)); | |
8badd27a | 7895 | |
2f7a3122 | 7896 | if (CONFIGURE_NIC_MODE(bp) && !bp->t2) |
16a5fd92 | 7897 | /* allocate searcher T2 table, as it wasn't allocated before */ |
55c11941 MS |
7898 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); |
7899 | ||
7900 | /* write address to which L5 should insert its values */ | |
7901 | bp->cnic_eth_dev.addr_drv_info_to_mcp = | |
7902 | &bp->slowpath->drv_info_to_mcp; | |
7903 | ||
7904 | if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) | |
7905 | goto alloc_mem_err; | |
7906 | ||
7907 | return 0; | |
7908 | ||
7909 | alloc_mem_err: | |
7910 | bnx2x_free_mem_cnic(bp); | |
7911 | BNX2X_ERR("Can't allocate memory\n"); | |
7912 | return -ENOMEM; | |
7913 | } | |
7914 | ||
7915 | int bnx2x_alloc_mem(struct bnx2x *bp) | |
7916 | { | |
7917 | int i, allocated, context_size; | |
a2fbb9ea | 7918 | |
2f7a3122 | 7919 | if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) |
55c11941 MS |
7920 | /* allocate searcher T2 table */ |
7921 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
8badd27a | 7922 | |
523224a3 DK |
7923 | BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, |
7924 | sizeof(struct host_sp_status_block)); | |
a2fbb9ea | 7925 | |
523224a3 DK |
7926 | BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, |
7927 | sizeof(struct bnx2x_slowpath)); | |
a2fbb9ea | 7928 | |
a052997e MS |
7929 | /* Allocate memory for CDU context: |
7930 | * This memory is allocated separately and not in the generic ILT | |
7931 | * functions because CDU differs in few aspects: | |
7932 | * 1. There are multiple entities allocating memory for context - | |
7933 | * 'regular' driver, CNIC and SRIOV driver. Each separately controls | |
7934 | * its own ILT lines. | |
7935 | * 2. Since CDU page-size is not a single 4KB page (which is the case | |
7936 | * for the other ILT clients), to be efficient we want to support | |
7937 | * allocation of sub-page-size in the last entry. | |
7938 | * 3. Context pointers are used by the driver to pass to FW / update | |
7939 | * the context (for the other ILT clients the pointers are used just to | |
7940 | * free the memory during unload). | |
7941 | */ | |
7942 | context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); | |
65abd74d | 7943 | |
a052997e MS |
7944 | for (i = 0, allocated = 0; allocated < context_size; i++) { |
7945 | bp->context[i].size = min(CDU_ILT_PAGE_SZ, | |
7946 | (context_size - allocated)); | |
7947 | BNX2X_PCI_ALLOC(bp->context[i].vcxt, | |
7948 | &bp->context[i].cxt_mapping, | |
7949 | bp->context[i].size); | |
7950 | allocated += bp->context[i].size; | |
7951 | } | |
523224a3 | 7952 | BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); |
65abd74d | 7953 | |
523224a3 DK |
7954 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
7955 | goto alloc_mem_err; | |
65abd74d | 7956 | |
67c431a5 AE |
7957 | if (bnx2x_iov_alloc_mem(bp)) |
7958 | goto alloc_mem_err; | |
7959 | ||
9f6c9258 DK |
7960 | /* Slow path ring */ |
7961 | BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); | |
65abd74d | 7962 | |
523224a3 DK |
7963 | /* EQ */ |
7964 | BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, | |
7965 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
ab532cf3 | 7966 | |
9f6c9258 | 7967 | return 0; |
e1510706 | 7968 | |
9f6c9258 DK |
7969 | alloc_mem_err: |
7970 | bnx2x_free_mem(bp); | |
51c1a580 | 7971 | BNX2X_ERR("Can't allocate memory\n"); |
9f6c9258 | 7972 | return -ENOMEM; |
65abd74d YG |
7973 | } |
7974 | ||
a2fbb9ea ET |
7975 | /* |
7976 | * Init service functions | |
7977 | */ | |
a2fbb9ea | 7978 | |
619c5cb6 VZ |
7979 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
7980 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
7981 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 7982 | { |
619c5cb6 VZ |
7983 | int rc; |
7984 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 7985 | |
619c5cb6 | 7986 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 7987 | |
619c5cb6 VZ |
7988 | /* Fill general parameters */ |
7989 | ramrod_param.vlan_mac_obj = obj; | |
7990 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 7991 | |
619c5cb6 VZ |
7992 | /* Fill a user request section if needed */ |
7993 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
7994 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 7995 | |
619c5cb6 | 7996 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 7997 | |
619c5cb6 VZ |
7998 | /* Set the command: ADD or DEL */ |
7999 | if (set) | |
8000 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
8001 | else | |
8002 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
8003 | } |
8004 | ||
619c5cb6 | 8005 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7b5342d9 YM |
8006 | |
8007 | if (rc == -EEXIST) { | |
8008 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); | |
8009 | /* do not treat adding same MAC as error */ | |
8010 | rc = 0; | |
8011 | } else if (rc < 0) | |
619c5cb6 | 8012 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); |
7b5342d9 | 8013 | |
619c5cb6 | 8014 | return rc; |
a2fbb9ea ET |
8015 | } |
8016 | ||
619c5cb6 VZ |
8017 | int bnx2x_del_all_macs(struct bnx2x *bp, |
8018 | struct bnx2x_vlan_mac_obj *mac_obj, | |
8019 | int mac_type, bool wait_for_comp) | |
e665bfda | 8020 | { |
619c5cb6 VZ |
8021 | int rc; |
8022 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 8023 | |
619c5cb6 VZ |
8024 | /* Wait for completion of requested */ |
8025 | if (wait_for_comp) | |
8026 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 8027 | |
619c5cb6 VZ |
8028 | /* Set the mac type of addresses we want to clear */ |
8029 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 8030 | |
619c5cb6 VZ |
8031 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
8032 | if (rc < 0) | |
8033 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 8034 | |
619c5cb6 | 8035 | return rc; |
0793f83f DK |
8036 | } |
8037 | ||
619c5cb6 | 8038 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 8039 | { |
a3348722 BW |
8040 | if (is_zero_ether_addr(bp->dev->dev_addr) && |
8041 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) { | |
51c1a580 MS |
8042 | DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, |
8043 | "Ignoring Zero MAC for STORAGE SD mode\n"); | |
614c76df DK |
8044 | return 0; |
8045 | } | |
614c76df | 8046 | |
f8f4f61a DK |
8047 | if (IS_PF(bp)) { |
8048 | unsigned long ramrod_flags = 0; | |
0793f83f | 8049 | |
f8f4f61a DK |
8050 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
8051 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
8052 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, | |
8053 | &bp->sp_objs->mac_obj, set, | |
8054 | BNX2X_ETH_MAC, &ramrod_flags); | |
8055 | } else { /* vf */ | |
8056 | return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, | |
8057 | bp->fp->index, true); | |
8058 | } | |
e665bfda | 8059 | } |
6e30dd4e | 8060 | |
619c5cb6 | 8061 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 8062 | { |
619c5cb6 | 8063 | return bnx2x_setup_queue(bp, &bp->fp[0], 1); |
993ac7b5 | 8064 | } |
a2fbb9ea | 8065 | |
d6214d7a | 8066 | /** |
e8920674 | 8067 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 8068 | * |
e8920674 | 8069 | * @bp: driver handle |
d6214d7a | 8070 | * |
e8920674 | 8071 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 8072 | */ |
1ab4434c | 8073 | int bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 8074 | { |
1ab4434c AE |
8075 | int rc = 0; |
8076 | ||
8077 | if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) | |
8078 | return -EINVAL; | |
8079 | ||
9ee3d37b | 8080 | switch (int_mode) { |
1ab4434c AE |
8081 | case BNX2X_INT_MODE_MSIX: |
8082 | /* attempt to enable msix */ | |
8083 | rc = bnx2x_enable_msix(bp); | |
8084 | ||
8085 | /* msix attained */ | |
8086 | if (!rc) | |
8087 | return 0; | |
8088 | ||
8089 | /* vfs use only msix */ | |
8090 | if (rc && IS_VF(bp)) | |
8091 | return rc; | |
8092 | ||
8093 | /* failed to enable multiple MSI-X */ | |
8094 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", | |
8095 | bp->num_queues, | |
8096 | 1 + bp->num_cnic_queues); | |
8097 | ||
8098 | /* falling through... */ | |
8099 | case BNX2X_INT_MODE_MSI: | |
d6214d7a | 8100 | bnx2x_enable_msi(bp); |
1ab4434c | 8101 | |
d6214d7a | 8102 | /* falling through... */ |
1ab4434c | 8103 | case BNX2X_INT_MODE_INTX: |
55c11941 MS |
8104 | bp->num_ethernet_queues = 1; |
8105 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; | |
51c1a580 | 8106 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
ca00392c | 8107 | break; |
d6214d7a | 8108 | default: |
1ab4434c AE |
8109 | BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); |
8110 | return -EINVAL; | |
9f6c9258 | 8111 | } |
1ab4434c | 8112 | return 0; |
a2fbb9ea ET |
8113 | } |
8114 | ||
1ab4434c | 8115 | /* must be called prior to any HW initializations */ |
c2bff63f DK |
8116 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) |
8117 | { | |
290ca2bb AE |
8118 | if (IS_SRIOV(bp)) |
8119 | return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; | |
c2bff63f DK |
8120 | return L2_ILT_LINES(bp); |
8121 | } | |
8122 | ||
523224a3 DK |
8123 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
8124 | { | |
8125 | struct ilt_client_info *ilt_client; | |
8126 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
8127 | u16 line = 0; | |
8128 | ||
8129 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
8130 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
8131 | ||
8132 | /* CDU */ | |
8133 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
8134 | ilt_client->client_num = ILT_CLIENT_CDU; | |
8135 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
8136 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
8137 | ilt_client->start = line; | |
619c5cb6 | 8138 | line += bnx2x_cid_ilt_lines(bp); |
55c11941 MS |
8139 | |
8140 | if (CNIC_SUPPORT(bp)) | |
8141 | line += CNIC_ILT_LINES; | |
523224a3 DK |
8142 | ilt_client->end = line - 1; |
8143 | ||
51c1a580 | 8144 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
523224a3 DK |
8145 | ilt_client->start, |
8146 | ilt_client->end, | |
8147 | ilt_client->page_size, | |
8148 | ilt_client->flags, | |
8149 | ilog2(ilt_client->page_size >> 12)); | |
8150 | ||
8151 | /* QM */ | |
8152 | if (QM_INIT(bp->qm_cid_count)) { | |
8153 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
8154 | ilt_client->client_num = ILT_CLIENT_QM; | |
8155 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
8156 | ilt_client->flags = 0; | |
8157 | ilt_client->start = line; | |
8158 | ||
8159 | /* 4 bytes for each cid */ | |
8160 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
8161 | QM_ILT_PAGE_SZ); | |
8162 | ||
8163 | ilt_client->end = line - 1; | |
8164 | ||
51c1a580 MS |
8165 | DP(NETIF_MSG_IFUP, |
8166 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
8167 | ilt_client->start, |
8168 | ilt_client->end, | |
8169 | ilt_client->page_size, | |
8170 | ilt_client->flags, | |
8171 | ilog2(ilt_client->page_size >> 12)); | |
523224a3 | 8172 | } |
523224a3 | 8173 | |
55c11941 MS |
8174 | if (CNIC_SUPPORT(bp)) { |
8175 | /* SRC */ | |
8176 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
8177 | ilt_client->client_num = ILT_CLIENT_SRC; | |
8178 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
8179 | ilt_client->flags = 0; | |
8180 | ilt_client->start = line; | |
8181 | line += SRC_ILT_LINES; | |
8182 | ilt_client->end = line - 1; | |
523224a3 | 8183 | |
55c11941 MS |
8184 | DP(NETIF_MSG_IFUP, |
8185 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8186 | ilt_client->start, | |
8187 | ilt_client->end, | |
8188 | ilt_client->page_size, | |
8189 | ilt_client->flags, | |
8190 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 8191 | |
55c11941 MS |
8192 | /* TM */ |
8193 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
8194 | ilt_client->client_num = ILT_CLIENT_TM; | |
8195 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
8196 | ilt_client->flags = 0; | |
8197 | ilt_client->start = line; | |
8198 | line += TM_ILT_LINES; | |
8199 | ilt_client->end = line - 1; | |
523224a3 | 8200 | |
55c11941 MS |
8201 | DP(NETIF_MSG_IFUP, |
8202 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8203 | ilt_client->start, | |
8204 | ilt_client->end, | |
8205 | ilt_client->page_size, | |
8206 | ilt_client->flags, | |
8207 | ilog2(ilt_client->page_size >> 12)); | |
8208 | } | |
9f6c9258 | 8209 | |
619c5cb6 | 8210 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 8211 | } |
f85582f8 | 8212 | |
619c5cb6 VZ |
8213 | /** |
8214 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
8215 | * | |
8216 | * @bp: driver handle | |
8217 | * @fp: pointer to fastpath | |
8218 | * @init_params: pointer to parameters structure | |
8219 | * | |
8220 | * parameters configured: | |
8221 | * - HC configuration | |
8222 | * - Queue's CDU context | |
8223 | */ | |
1191cb83 | 8224 | static void bnx2x_pf_q_prep_init(struct bnx2x *bp, |
619c5cb6 | 8225 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) |
a2fbb9ea | 8226 | { |
6383c0b3 | 8227 | u8 cos; |
a052997e MS |
8228 | int cxt_index, cxt_offset; |
8229 | ||
619c5cb6 VZ |
8230 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
8231 | if (!IS_FCOE_FP(fp)) { | |
8232 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
8233 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
8234 | ||
16a5fd92 | 8235 | /* If HC is supported, enable host coalescing in the transition |
619c5cb6 VZ |
8236 | * to INIT state. |
8237 | */ | |
8238 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
8239 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
8240 | ||
8241 | /* HC rate */ | |
8242 | init_params->rx.hc_rate = bp->rx_ticks ? | |
8243 | (1000000 / bp->rx_ticks) : 0; | |
8244 | init_params->tx.hc_rate = bp->tx_ticks ? | |
8245 | (1000000 / bp->tx_ticks) : 0; | |
8246 | ||
8247 | /* FW SB ID */ | |
8248 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
8249 | fp->fw_sb_id; | |
8250 | ||
8251 | /* | |
8252 | * CQ index among the SB indices: FCoE clients uses the default | |
8253 | * SB, therefore it's different. | |
8254 | */ | |
6383c0b3 AE |
8255 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
8256 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
8257 | } |
8258 | ||
6383c0b3 AE |
8259 | /* set maximum number of COSs supported by this queue */ |
8260 | init_params->max_cos = fp->max_cos; | |
8261 | ||
51c1a580 | 8262 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
8263 | fp->index, init_params->max_cos); |
8264 | ||
8265 | /* set the context pointers queue object */ | |
a052997e | 8266 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { |
65565884 MS |
8267 | cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; |
8268 | cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * | |
a052997e | 8269 | ILT_PAGE_CIDS); |
6383c0b3 | 8270 | init_params->cxts[cos] = |
a052997e MS |
8271 | &bp->context[cxt_index].vcxt[cxt_offset].eth; |
8272 | } | |
619c5cb6 VZ |
8273 | } |
8274 | ||
910cc727 | 8275 | static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
6383c0b3 AE |
8276 | struct bnx2x_queue_state_params *q_params, |
8277 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
8278 | int tx_index, bool leading) | |
8279 | { | |
8280 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
8281 | ||
8282 | /* Set the command */ | |
8283 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
8284 | ||
8285 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
8286 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
8287 | ||
8288 | /* choose the index of the cid to send the slow path on */ | |
8289 | tx_only_params->cid_index = tx_index; | |
8290 | ||
8291 | /* Set general TX_ONLY_SETUP parameters */ | |
8292 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
8293 | ||
8294 | /* Set Tx TX_ONLY_SETUP parameters */ | |
8295 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
8296 | ||
51c1a580 MS |
8297 | DP(NETIF_MSG_IFUP, |
8298 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", | |
6383c0b3 AE |
8299 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
8300 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
8301 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
8302 | ||
8303 | /* send the ramrod */ | |
8304 | return bnx2x_queue_state_change(bp, q_params); | |
8305 | } | |
8306 | ||
619c5cb6 VZ |
8307 | /** |
8308 | * bnx2x_setup_queue - setup queue | |
8309 | * | |
8310 | * @bp: driver handle | |
8311 | * @fp: pointer to fastpath | |
8312 | * @leading: is leading | |
8313 | * | |
8314 | * This function performs 2 steps in a Queue state machine | |
8315 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
8316 | */ | |
8317 | ||
8318 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
8319 | bool leading) | |
8320 | { | |
3b603066 | 8321 | struct bnx2x_queue_state_params q_params = {NULL}; |
619c5cb6 VZ |
8322 | struct bnx2x_queue_setup_params *setup_params = |
8323 | &q_params.params.setup; | |
6383c0b3 AE |
8324 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
8325 | &q_params.params.tx_only; | |
a2fbb9ea | 8326 | int rc; |
6383c0b3 AE |
8327 | u8 tx_index; |
8328 | ||
51c1a580 | 8329 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 8330 | |
ec6ba945 VZ |
8331 | /* reset IGU state skip FCoE L2 queue */ |
8332 | if (!IS_FCOE_FP(fp)) | |
8333 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 8334 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 8335 | |
15192a8c | 8336 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8337 | /* We want to wait for completion in this context */ |
8338 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8339 | |
619c5cb6 VZ |
8340 | /* Prepare the INIT parameters */ |
8341 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 8342 | |
619c5cb6 VZ |
8343 | /* Set the command */ |
8344 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
8345 | ||
8346 | /* Change the state to INIT */ | |
8347 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8348 | if (rc) { | |
6383c0b3 | 8349 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
8350 | return rc; |
8351 | } | |
ec6ba945 | 8352 | |
51c1a580 | 8353 | DP(NETIF_MSG_IFUP, "init complete\n"); |
6383c0b3 | 8354 | |
619c5cb6 VZ |
8355 | /* Now move the Queue to the SETUP state... */ |
8356 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 8357 | |
619c5cb6 VZ |
8358 | /* Set QUEUE flags */ |
8359 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 8360 | |
619c5cb6 | 8361 | /* Set general SETUP parameters */ |
6383c0b3 AE |
8362 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
8363 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 8364 | |
6383c0b3 | 8365 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
8366 | &setup_params->rxq_params); |
8367 | ||
6383c0b3 AE |
8368 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
8369 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
8370 | |
8371 | /* Set the command */ | |
8372 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
8373 | ||
55c11941 MS |
8374 | if (IS_FCOE_FP(fp)) |
8375 | bp->fcoe_init = true; | |
8376 | ||
619c5cb6 VZ |
8377 | /* Change the state to SETUP */ |
8378 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
8379 | if (rc) { |
8380 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
8381 | return rc; | |
8382 | } | |
8383 | ||
8384 | /* loop through the relevant tx-only indices */ | |
8385 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8386 | tx_index < fp->max_cos; | |
8387 | tx_index++) { | |
8388 | ||
8389 | /* prepare and send tx-only ramrod*/ | |
8390 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
8391 | tx_only_params, tx_index, leading); | |
8392 | if (rc) { | |
8393 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
8394 | fp->index, tx_index); | |
8395 | return rc; | |
8396 | } | |
8397 | } | |
523224a3 | 8398 | |
34f80b04 | 8399 | return rc; |
a2fbb9ea ET |
8400 | } |
8401 | ||
619c5cb6 | 8402 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 8403 | { |
619c5cb6 | 8404 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 8405 | struct bnx2x_fp_txdata *txdata; |
3b603066 | 8406 | struct bnx2x_queue_state_params q_params = {NULL}; |
6383c0b3 AE |
8407 | int rc, tx_index; |
8408 | ||
51c1a580 | 8409 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 8410 | |
15192a8c | 8411 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8412 | /* We want to wait for completion in this context */ |
8413 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8414 | |
6383c0b3 AE |
8415 | /* close tx-only connections */ |
8416 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8417 | tx_index < fp->max_cos; | |
8418 | tx_index++){ | |
8419 | ||
8420 | /* ascertain this is a normal queue*/ | |
65565884 | 8421 | txdata = fp->txdata_ptr[tx_index]; |
6383c0b3 | 8422 | |
51c1a580 | 8423 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
6383c0b3 AE |
8424 | txdata->txq_index); |
8425 | ||
8426 | /* send halt terminate on tx-only connection */ | |
8427 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
8428 | memset(&q_params.params.terminate, 0, | |
8429 | sizeof(q_params.params.terminate)); | |
8430 | q_params.params.terminate.cid_index = tx_index; | |
8431 | ||
8432 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8433 | if (rc) | |
8434 | return rc; | |
8435 | ||
8436 | /* send halt terminate on tx-only connection */ | |
8437 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
8438 | memset(&q_params.params.cfc_del, 0, | |
8439 | sizeof(q_params.params.cfc_del)); | |
8440 | q_params.params.cfc_del.cid_index = tx_index; | |
8441 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8442 | if (rc) | |
8443 | return rc; | |
8444 | } | |
8445 | /* Stop the primary connection: */ | |
8446 | /* ...halt the connection */ | |
619c5cb6 VZ |
8447 | q_params.cmd = BNX2X_Q_CMD_HALT; |
8448 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8449 | if (rc) | |
da5a662a | 8450 | return rc; |
a2fbb9ea | 8451 | |
6383c0b3 | 8452 | /* ...terminate the connection */ |
619c5cb6 | 8453 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
8454 | memset(&q_params.params.terminate, 0, |
8455 | sizeof(q_params.params.terminate)); | |
8456 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
8457 | rc = bnx2x_queue_state_change(bp, &q_params); |
8458 | if (rc) | |
523224a3 | 8459 | return rc; |
6383c0b3 | 8460 | /* ...delete cfc entry */ |
619c5cb6 | 8461 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
8462 | memset(&q_params.params.cfc_del, 0, |
8463 | sizeof(q_params.params.cfc_del)); | |
8464 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 8465 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
8466 | } |
8467 | ||
34f80b04 EG |
8468 | static void bnx2x_reset_func(struct bnx2x *bp) |
8469 | { | |
8470 | int port = BP_PORT(bp); | |
8471 | int func = BP_FUNC(bp); | |
f2e0899f | 8472 | int i; |
523224a3 DK |
8473 | |
8474 | /* Disable the function in the FW */ | |
8475 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
8476 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
8477 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
8478 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
8479 | ||
8480 | /* FP SBs */ | |
ec6ba945 | 8481 | for_each_eth_queue(bp, i) { |
523224a3 | 8482 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 8483 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8484 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
8485 | SB_DISABLED); | |
523224a3 DK |
8486 | } |
8487 | ||
55c11941 MS |
8488 | if (CNIC_LOADED(bp)) |
8489 | /* CNIC SB */ | |
8490 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
8491 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET | |
8492 | (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); | |
8493 | ||
523224a3 | 8494 | /* SP SB */ |
619c5cb6 | 8495 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
2de67439 YM |
8496 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
8497 | SB_DISABLED); | |
523224a3 DK |
8498 | |
8499 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
8500 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
8501 | 0); | |
34f80b04 EG |
8502 | |
8503 | /* Configure IGU */ | |
f2e0899f DK |
8504 | if (bp->common.int_block == INT_BLOCK_HC) { |
8505 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
8506 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
8507 | } else { | |
8508 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
8509 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
8510 | } | |
34f80b04 | 8511 | |
55c11941 MS |
8512 | if (CNIC_LOADED(bp)) { |
8513 | /* Disable Timer scan */ | |
8514 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
8515 | /* | |
8516 | * Wait for at least 10ms and up to 2 second for the timers | |
8517 | * scan to complete | |
8518 | */ | |
8519 | for (i = 0; i < 200; i++) { | |
639d65b8 | 8520 | usleep_range(10000, 20000); |
55c11941 MS |
8521 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) |
8522 | break; | |
8523 | } | |
37b091ba | 8524 | } |
34f80b04 | 8525 | /* Clear ILT */ |
f2e0899f DK |
8526 | bnx2x_clear_func_ilt(bp, func); |
8527 | ||
8528 | /* Timers workaround bug for E2: if this is vnic-3, | |
8529 | * we need to set the entire ilt range for this timers. | |
8530 | */ | |
619c5cb6 | 8531 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
8532 | struct ilt_client_info ilt_cli; |
8533 | /* use dummy TM client */ | |
8534 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
8535 | ilt_cli.start = 0; | |
8536 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
8537 | ilt_cli.client_num = ILT_CLIENT_TM; | |
8538 | ||
8539 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
8540 | } | |
8541 | ||
8542 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 8543 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 8544 | bnx2x_pf_disable(bp); |
523224a3 DK |
8545 | |
8546 | bp->dmae_ready = 0; | |
34f80b04 EG |
8547 | } |
8548 | ||
8549 | static void bnx2x_reset_port(struct bnx2x *bp) | |
8550 | { | |
8551 | int port = BP_PORT(bp); | |
8552 | u32 val; | |
8553 | ||
619c5cb6 VZ |
8554 | /* Reset physical Link */ |
8555 | bnx2x__link_reset(bp); | |
8556 | ||
34f80b04 EG |
8557 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
8558 | ||
8559 | /* Do not rcv packets to BRB */ | |
8560 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
8561 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
8562 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
8563 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
8564 | ||
8565 | /* Configure AEU */ | |
8566 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
8567 | ||
8568 | msleep(100); | |
8569 | /* Check for BRB port occupancy */ | |
8570 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
8571 | if (val) | |
8572 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 8573 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
8574 | |
8575 | /* TODO: Close Doorbell port? */ | |
8576 | } | |
8577 | ||
1191cb83 | 8578 | static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 8579 | { |
3b603066 | 8580 | struct bnx2x_func_state_params func_params = {NULL}; |
34f80b04 | 8581 | |
619c5cb6 VZ |
8582 | /* Prepare parameters for function state transitions */ |
8583 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 8584 | |
619c5cb6 VZ |
8585 | func_params.f_obj = &bp->func_obj; |
8586 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 8587 | |
619c5cb6 | 8588 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 8589 | |
619c5cb6 | 8590 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
8591 | } |
8592 | ||
1191cb83 | 8593 | static int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 8594 | { |
3b603066 | 8595 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 | 8596 | int rc; |
228241eb | 8597 | |
619c5cb6 VZ |
8598 | /* Prepare parameters for function state transitions */ |
8599 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
8600 | func_params.f_obj = &bp->func_obj; | |
8601 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 8602 | |
619c5cb6 VZ |
8603 | /* |
8604 | * Try to stop the function the 'good way'. If fails (in case | |
8605 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
8606 | * not in a debug mode, perform a state transaction in order to | |
8607 | * enable further HW_RESET transaction. | |
8608 | */ | |
8609 | rc = bnx2x_func_state_change(bp, &func_params); | |
8610 | if (rc) { | |
34f80b04 | 8611 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 8612 | return rc; |
34f80b04 | 8613 | #else |
51c1a580 | 8614 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
619c5cb6 VZ |
8615 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
8616 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 8617 | #endif |
228241eb | 8618 | } |
a2fbb9ea | 8619 | |
619c5cb6 VZ |
8620 | return 0; |
8621 | } | |
523224a3 | 8622 | |
619c5cb6 VZ |
8623 | /** |
8624 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
8625 | * | |
8626 | * @bp: driver handle | |
8627 | * @unload_mode: requested function's unload mode | |
8628 | * | |
8629 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
8630 | */ | |
8631 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
8632 | { | |
8633 | u32 reset_code = 0; | |
8634 | int port = BP_PORT(bp); | |
3101c2bc | 8635 | |
619c5cb6 | 8636 | /* Select the UNLOAD request mode */ |
65abd74d YG |
8637 | if (unload_mode == UNLOAD_NORMAL) |
8638 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
8639 | ||
7d0446c2 | 8640 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 8641 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 8642 | |
7d0446c2 | 8643 | else if (bp->wol) { |
65abd74d YG |
8644 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
8645 | u8 *mac_addr = bp->dev->dev_addr; | |
8646 | u32 val; | |
f9977903 DK |
8647 | u16 pmc; |
8648 | ||
65abd74d | 8649 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
8650 | * preserve entry 0 which is used by the PMF |
8651 | */ | |
3395a033 | 8652 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
8653 | |
8654 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
8655 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
8656 | ||
8657 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
8658 | (mac_addr[4] << 8) | mac_addr[5]; | |
8659 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
8660 | ||
f9977903 DK |
8661 | /* Enable the PME and clear the status */ |
8662 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); | |
8663 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; | |
8664 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); | |
8665 | ||
65abd74d YG |
8666 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
8667 | ||
8668 | } else | |
8669 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 8670 | |
619c5cb6 VZ |
8671 | /* Send the request to the MCP */ |
8672 | if (!BP_NOMCP(bp)) | |
8673 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
8674 | else { | |
8675 | int path = BP_PATH(bp); | |
8676 | ||
51c1a580 | 8677 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8678 | path, load_count[path][0], load_count[path][1], |
8679 | load_count[path][2]); | |
8680 | load_count[path][0]--; | |
8681 | load_count[path][1 + port]--; | |
51c1a580 | 8682 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8683 | path, load_count[path][0], load_count[path][1], |
8684 | load_count[path][2]); | |
8685 | if (load_count[path][0] == 0) | |
8686 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; | |
8687 | else if (load_count[path][1 + port] == 0) | |
8688 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; | |
8689 | else | |
8690 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
8691 | } | |
8692 | ||
8693 | return reset_code; | |
8694 | } | |
8695 | ||
8696 | /** | |
8697 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
8698 | * | |
8699 | * @bp: driver handle | |
5d07d868 | 8700 | * @keep_link: true iff link should be kept up |
619c5cb6 | 8701 | */ |
5d07d868 | 8702 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) |
619c5cb6 | 8703 | { |
5d07d868 YM |
8704 | u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; |
8705 | ||
619c5cb6 VZ |
8706 | /* Report UNLOAD_DONE to MCP */ |
8707 | if (!BP_NOMCP(bp)) | |
5d07d868 | 8708 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); |
619c5cb6 VZ |
8709 | } |
8710 | ||
1191cb83 | 8711 | static int bnx2x_func_wait_started(struct bnx2x *bp) |
6debea87 DK |
8712 | { |
8713 | int tout = 50; | |
8714 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
8715 | ||
8716 | if (!bp->port.pmf) | |
8717 | return 0; | |
8718 | ||
8719 | /* | |
8720 | * (assumption: No Attention from MCP at this stage) | |
16a5fd92 | 8721 | * PMF probably in the middle of TX disable/enable transaction |
6debea87 | 8722 | * 1. Sync IRS for default SB |
16a5fd92 YM |
8723 | * 2. Sync SP queue - this guarantees us that attention handling started |
8724 | * 3. Wait, that TX disable/enable transaction completes | |
6debea87 | 8725 | * |
16a5fd92 YM |
8726 | * 1+2 guarantee that if DCBx attention was scheduled it already changed |
8727 | * pending bit of transaction from STARTED-->TX_STOPPED, if we already | |
8728 | * received completion for the transaction the state is TX_STOPPED. | |
6debea87 DK |
8729 | * State will return to STARTED after completion of TX_STOPPED-->STARTED |
8730 | * transaction. | |
8731 | */ | |
8732 | ||
8733 | /* make sure default SB ISR is done */ | |
8734 | if (msix) | |
8735 | synchronize_irq(bp->msix_table[0].vector); | |
8736 | else | |
8737 | synchronize_irq(bp->pdev->irq); | |
8738 | ||
8739 | flush_workqueue(bnx2x_wq); | |
8740 | ||
8741 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8742 | BNX2X_F_STATE_STARTED && tout--) | |
8743 | msleep(20); | |
8744 | ||
8745 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8746 | BNX2X_F_STATE_STARTED) { | |
8747 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 8748 | BNX2X_ERR("Wrong function state\n"); |
6debea87 DK |
8749 | return -EBUSY; |
8750 | #else | |
8751 | /* | |
8752 | * Failed to complete the transaction in a "good way" | |
8753 | * Force both transactions with CLR bit | |
8754 | */ | |
3b603066 | 8755 | struct bnx2x_func_state_params func_params = {NULL}; |
6debea87 | 8756 | |
51c1a580 | 8757 | DP(NETIF_MSG_IFDOWN, |
6bf07b8e | 8758 | "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); |
6debea87 DK |
8759 | |
8760 | func_params.f_obj = &bp->func_obj; | |
8761 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
8762 | &func_params.ramrod_flags); | |
8763 | ||
8764 | /* STARTED-->TX_ST0PPED */ | |
8765 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
8766 | bnx2x_func_state_change(bp, &func_params); | |
8767 | ||
8768 | /* TX_ST0PPED-->STARTED */ | |
8769 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
8770 | return bnx2x_func_state_change(bp, &func_params); | |
8771 | #endif | |
8772 | } | |
8773 | ||
8774 | return 0; | |
8775 | } | |
8776 | ||
5d07d868 | 8777 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) |
619c5cb6 VZ |
8778 | { |
8779 | int port = BP_PORT(bp); | |
6383c0b3 AE |
8780 | int i, rc = 0; |
8781 | u8 cos; | |
3b603066 | 8782 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 VZ |
8783 | u32 reset_code; |
8784 | ||
8785 | /* Wait until tx fastpath tasks complete */ | |
8786 | for_each_tx_queue(bp, i) { | |
8787 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
8788 | ||
6383c0b3 | 8789 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 8790 | rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); |
619c5cb6 VZ |
8791 | #ifdef BNX2X_STOP_ON_ERROR |
8792 | if (rc) | |
8793 | return; | |
8794 | #endif | |
8795 | } | |
8796 | ||
8797 | /* Give HW time to discard old tx messages */ | |
0926d499 | 8798 | usleep_range(1000, 2000); |
619c5cb6 VZ |
8799 | |
8800 | /* Clean all ETH MACs */ | |
15192a8c BW |
8801 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, |
8802 | false); | |
619c5cb6 VZ |
8803 | if (rc < 0) |
8804 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
8805 | ||
8806 | /* Clean up UC list */ | |
15192a8c | 8807 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, |
619c5cb6 VZ |
8808 | true); |
8809 | if (rc < 0) | |
51c1a580 MS |
8810 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
8811 | rc); | |
619c5cb6 VZ |
8812 | |
8813 | /* Disable LLH */ | |
8814 | if (!CHIP_IS_E1(bp)) | |
8815 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
8816 | ||
8817 | /* Set "drop all" (stop Rx). | |
8818 | * We need to take a netif_addr_lock() here in order to prevent | |
8819 | * a race between the completion code and this code. | |
8820 | */ | |
8821 | netif_addr_lock_bh(bp->dev); | |
8822 | /* Schedule the rx_mode command */ | |
8823 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
8824 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
8825 | else | |
8826 | bnx2x_set_storm_rx_mode(bp); | |
8827 | ||
8828 | /* Cleanup multicast configuration */ | |
8829 | rparam.mcast_obj = &bp->mcast_obj; | |
8830 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
8831 | if (rc < 0) | |
8832 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
8833 | ||
8834 | netif_addr_unlock_bh(bp->dev); | |
8835 | ||
f1929b01 | 8836 | bnx2x_iov_chip_cleanup(bp); |
619c5cb6 | 8837 | |
6debea87 DK |
8838 | /* |
8839 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
8840 | * this function should perform FUNC, PORT or COMMON HW | |
8841 | * reset. | |
8842 | */ | |
8843 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
8844 | ||
8845 | /* | |
8846 | * (assumption: No Attention from MCP at this stage) | |
16a5fd92 | 8847 | * PMF probably in the middle of TX disable/enable transaction |
6debea87 DK |
8848 | */ |
8849 | rc = bnx2x_func_wait_started(bp); | |
8850 | if (rc) { | |
8851 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
8852 | #ifdef BNX2X_STOP_ON_ERROR | |
8853 | return; | |
8854 | #endif | |
8855 | } | |
8856 | ||
34f80b04 | 8857 | /* Close multi and leading connections |
619c5cb6 VZ |
8858 | * Completions for ramrods are collected in a synchronous way |
8859 | */ | |
55c11941 | 8860 | for_each_eth_queue(bp, i) |
619c5cb6 | 8861 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
8862 | #ifdef BNX2X_STOP_ON_ERROR |
8863 | return; | |
8864 | #else | |
228241eb | 8865 | goto unload_error; |
523224a3 | 8866 | #endif |
55c11941 MS |
8867 | |
8868 | if (CNIC_LOADED(bp)) { | |
8869 | for_each_cnic_queue(bp, i) | |
8870 | if (bnx2x_stop_queue(bp, i)) | |
8871 | #ifdef BNX2X_STOP_ON_ERROR | |
8872 | return; | |
8873 | #else | |
8874 | goto unload_error; | |
8875 | #endif | |
8876 | } | |
8877 | ||
619c5cb6 VZ |
8878 | /* If SP settings didn't get completed so far - something |
8879 | * very wrong has happen. | |
8880 | */ | |
8881 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
8882 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 8883 | |
619c5cb6 VZ |
8884 | #ifndef BNX2X_STOP_ON_ERROR |
8885 | unload_error: | |
8886 | #endif | |
523224a3 | 8887 | rc = bnx2x_func_stop(bp); |
da5a662a | 8888 | if (rc) { |
523224a3 | 8889 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 8890 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 8891 | return; |
523224a3 | 8892 | #endif |
34f80b04 | 8893 | } |
a2fbb9ea | 8894 | |
523224a3 DK |
8895 | /* Disable HW interrupts, NAPI */ |
8896 | bnx2x_netif_stop(bp, 1); | |
26614ba5 MS |
8897 | /* Delete all NAPI objects */ |
8898 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
8899 | if (CNIC_LOADED(bp)) |
8900 | bnx2x_del_all_napi_cnic(bp); | |
523224a3 DK |
8901 | |
8902 | /* Release IRQs */ | |
d6214d7a | 8903 | bnx2x_free_irq(bp); |
523224a3 | 8904 | |
a2fbb9ea | 8905 | /* Reset the chip */ |
619c5cb6 VZ |
8906 | rc = bnx2x_reset_hw(bp, reset_code); |
8907 | if (rc) | |
8908 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 8909 | |
619c5cb6 | 8910 | /* Report UNLOAD_DONE to MCP */ |
5d07d868 | 8911 | bnx2x_send_unload_done(bp, keep_link); |
72fd0718 VZ |
8912 | } |
8913 | ||
9f6c9258 | 8914 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
8915 | { |
8916 | u32 val; | |
8917 | ||
51c1a580 | 8918 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
72fd0718 VZ |
8919 | |
8920 | if (CHIP_IS_E1(bp)) { | |
8921 | int port = BP_PORT(bp); | |
8922 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
8923 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
8924 | ||
8925 | val = REG_RD(bp, addr); | |
8926 | val &= ~(0x300); | |
8927 | REG_WR(bp, addr, val); | |
619c5cb6 | 8928 | } else { |
72fd0718 VZ |
8929 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
8930 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
8931 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
8932 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
8933 | } | |
8934 | } | |
8935 | ||
72fd0718 VZ |
8936 | /* Close gates #2, #3 and #4: */ |
8937 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
8938 | { | |
c9ee9206 | 8939 | u32 val; |
72fd0718 VZ |
8940 | |
8941 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
8942 | if (!CHIP_IS_E1(bp)) { | |
8943 | /* #4 */ | |
c9ee9206 | 8944 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 8945 | /* #2 */ |
c9ee9206 | 8946 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
8947 | } |
8948 | ||
8949 | /* #3 */ | |
c9ee9206 VZ |
8950 | if (CHIP_IS_E1x(bp)) { |
8951 | /* Prevent interrupts from HC on both ports */ | |
8952 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
8953 | REG_WR(bp, HC_REG_CONFIG_1, | |
8954 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
8955 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
8956 | ||
8957 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
8958 | REG_WR(bp, HC_REG_CONFIG_0, | |
8959 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
8960 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
8961 | } else { | |
d82603c6 | 8962 | /* Prevent incoming interrupts in IGU */ |
c9ee9206 VZ |
8963 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
8964 | ||
8965 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
8966 | (!close) ? | |
8967 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
8968 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
8969 | } | |
72fd0718 | 8970 | |
51c1a580 | 8971 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
72fd0718 VZ |
8972 | close ? "closing" : "opening"); |
8973 | mmiowb(); | |
8974 | } | |
8975 | ||
8976 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
8977 | ||
8978 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
8979 | { | |
8980 | /* Do some magic... */ | |
8981 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
8982 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
8983 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
8984 | } | |
8985 | ||
e8920674 DK |
8986 | /** |
8987 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 8988 | * |
e8920674 DK |
8989 | * @bp: driver handle |
8990 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
8991 | */ |
8992 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
8993 | { | |
8994 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
8995 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
8996 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
8997 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
8998 | } | |
8999 | ||
f85582f8 | 9000 | /** |
e8920674 | 9001 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 9002 | * |
e8920674 DK |
9003 | * @bp: driver handle |
9004 | * @magic_val: old value of 'magic' bit. | |
9005 | * | |
9006 | * Takes care of CLP configurations. | |
72fd0718 VZ |
9007 | */ |
9008 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
9009 | { | |
9010 | u32 shmem; | |
9011 | u32 validity_offset; | |
9012 | ||
51c1a580 | 9013 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
72fd0718 VZ |
9014 | |
9015 | /* Set `magic' bit in order to save MF config */ | |
9016 | if (!CHIP_IS_E1(bp)) | |
9017 | bnx2x_clp_reset_prep(bp, magic_val); | |
9018 | ||
9019 | /* Get shmem offset */ | |
9020 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
c55e771b BW |
9021 | validity_offset = |
9022 | offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); | |
72fd0718 VZ |
9023 | |
9024 | /* Clear validity map flags */ | |
9025 | if (shmem > 0) | |
9026 | REG_WR(bp, shmem + validity_offset, 0); | |
9027 | } | |
9028 | ||
9029 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
9030 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
9031 | ||
e8920674 DK |
9032 | /** |
9033 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 9034 | * |
e8920674 | 9035 | * @bp: driver handle |
72fd0718 | 9036 | */ |
1191cb83 | 9037 | static void bnx2x_mcp_wait_one(struct bnx2x *bp) |
72fd0718 VZ |
9038 | { |
9039 | /* special handling for emulation and FPGA, | |
9040 | wait 10 times longer */ | |
9041 | if (CHIP_REV_IS_SLOW(bp)) | |
9042 | msleep(MCP_ONE_TIMEOUT*10); | |
9043 | else | |
9044 | msleep(MCP_ONE_TIMEOUT); | |
9045 | } | |
9046 | ||
1b6e2ceb DK |
9047 | /* |
9048 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
9049 | */ | |
9050 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 9051 | { |
1b6e2ceb DK |
9052 | int cnt = 0; |
9053 | u32 val = 0; | |
72fd0718 | 9054 | |
1b6e2ceb DK |
9055 | do { |
9056 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
9057 | if (bp->common.shmem_base) { | |
9058 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
9059 | if (val & SHR_MEM_VALIDITY_MB) | |
9060 | return 0; | |
9061 | } | |
72fd0718 | 9062 | |
1b6e2ceb | 9063 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 9064 | |
1b6e2ceb | 9065 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 9066 | |
1b6e2ceb | 9067 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 9068 | |
1b6e2ceb DK |
9069 | return -ENODEV; |
9070 | } | |
72fd0718 | 9071 | |
1b6e2ceb DK |
9072 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
9073 | { | |
9074 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 9075 | |
72fd0718 VZ |
9076 | /* Restore the `magic' bit value */ |
9077 | if (!CHIP_IS_E1(bp)) | |
9078 | bnx2x_clp_reset_done(bp, magic_val); | |
9079 | ||
9080 | return rc; | |
9081 | } | |
9082 | ||
9083 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
9084 | { | |
9085 | if (!CHIP_IS_E1(bp)) { | |
9086 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
9087 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
9088 | mmiowb(); |
9089 | } | |
9090 | } | |
9091 | ||
9092 | /* | |
9093 | * Reset the whole chip except for: | |
9094 | * - PCIE core | |
9095 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
9096 | * one reset bit) | |
9097 | * - IGU | |
9098 | * - MISC (including AEU) | |
9099 | * - GRC | |
9100 | * - RBCN, RBCP | |
9101 | */ | |
c9ee9206 | 9102 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
9103 | { |
9104 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 9105 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
9106 | |
9107 | /* | |
9108 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
9109 | * (per chip) blocks. | |
9110 | */ | |
9111 | global_bits2 = | |
9112 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
9113 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 9114 | |
c55e771b BW |
9115 | /* Don't reset the following blocks. |
9116 | * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be | |
9117 | * reset, as in 4 port device they might still be owned | |
9118 | * by the MCP (there is only one leader per path). | |
9119 | */ | |
72fd0718 VZ |
9120 | not_reset_mask1 = |
9121 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
9122 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
9123 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
9124 | ||
9125 | not_reset_mask2 = | |
c9ee9206 | 9126 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
9127 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
9128 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
9129 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
9130 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
9131 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
9132 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
9133 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
9134 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
c55e771b BW |
9135 | MISC_REGISTERS_RESET_REG_2_PGLC | |
9136 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
9137 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
9138 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
9139 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
9140 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
9141 | MISC_REGISTERS_RESET_REG_2_UMAC1; | |
72fd0718 | 9142 | |
8736c826 VZ |
9143 | /* |
9144 | * Keep the following blocks in reset: | |
9145 | * - all xxMACs are handled by the bnx2x_link code. | |
9146 | */ | |
9147 | stay_reset2 = | |
8736c826 VZ |
9148 | MISC_REGISTERS_RESET_REG_2_XMAC | |
9149 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
9150 | ||
9151 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
9152 | reset_mask1 = 0xffffffff; |
9153 | ||
9154 | if (CHIP_IS_E1(bp)) | |
9155 | reset_mask2 = 0xffff; | |
8736c826 | 9156 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 9157 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
9158 | else if (CHIP_IS_E2(bp)) |
9159 | reset_mask2 = 0xfffff; | |
9160 | else /* CHIP_IS_E3 */ | |
9161 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
9162 | |
9163 | /* Don't reset global blocks unless we need to */ | |
9164 | if (!global) | |
9165 | reset_mask2 &= ~global_bits2; | |
9166 | ||
9167 | /* | |
9168 | * In case of attention in the QM, we need to reset PXP | |
9169 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
9170 | * because otherwise QM reset would release 'close the gates' shortly | |
9171 | * before resetting the PXP, then the PSWRQ would send a write | |
9172 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
9173 | * read the payload data from PSWWR, but PSWWR would not | |
9174 | * respond. The write queue in PGLUE would stuck, dmae commands | |
9175 | * would not return. Therefore it's important to reset the second | |
9176 | * reset register (containing the | |
9177 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
9178 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
9179 | * bit). | |
9180 | */ | |
72fd0718 VZ |
9181 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
9182 | reset_mask2 & (~not_reset_mask2)); | |
9183 | ||
c9ee9206 VZ |
9184 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
9185 | reset_mask1 & (~not_reset_mask1)); | |
9186 | ||
72fd0718 VZ |
9187 | barrier(); |
9188 | mmiowb(); | |
9189 | ||
8736c826 VZ |
9190 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
9191 | reset_mask2 & (~stay_reset2)); | |
9192 | ||
9193 | barrier(); | |
9194 | mmiowb(); | |
9195 | ||
c9ee9206 | 9196 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
9197 | mmiowb(); |
9198 | } | |
9199 | ||
c9ee9206 VZ |
9200 | /** |
9201 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
9202 | * It should get cleared in no more than 1s. | |
9203 | * | |
9204 | * @bp: driver handle | |
9205 | * | |
9206 | * It should get cleared in no more than 1s. Returns 0 if | |
9207 | * pending writes bit gets cleared. | |
9208 | */ | |
9209 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
9210 | { | |
9211 | u32 cnt = 1000; | |
9212 | u32 pend_bits = 0; | |
9213 | ||
9214 | do { | |
9215 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
9216 | ||
9217 | if (pend_bits == 0) | |
9218 | break; | |
9219 | ||
0926d499 | 9220 | usleep_range(1000, 2000); |
c9ee9206 VZ |
9221 | } while (cnt-- > 0); |
9222 | ||
9223 | if (cnt <= 0) { | |
9224 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
9225 | pend_bits); | |
9226 | return -EBUSY; | |
9227 | } | |
9228 | ||
9229 | return 0; | |
9230 | } | |
9231 | ||
9232 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
9233 | { |
9234 | int cnt = 1000; | |
9235 | u32 val = 0; | |
9236 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
2de67439 | 9237 | u32 tags_63_32 = 0; |
72fd0718 VZ |
9238 | |
9239 | /* Empty the Tetris buffer, wait for 1s */ | |
9240 | do { | |
9241 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
9242 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
9243 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
9244 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
9245 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
c55e771b BW |
9246 | if (CHIP_IS_E3(bp)) |
9247 | tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); | |
9248 | ||
72fd0718 VZ |
9249 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && |
9250 | ((port_is_idle_0 & 0x1) == 0x1) && | |
9251 | ((port_is_idle_1 & 0x1) == 0x1) && | |
c55e771b BW |
9252 | (pgl_exp_rom2 == 0xffffffff) && |
9253 | (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) | |
72fd0718 | 9254 | break; |
0926d499 | 9255 | usleep_range(1000, 2000); |
72fd0718 VZ |
9256 | } while (cnt-- > 0); |
9257 | ||
9258 | if (cnt <= 0) { | |
51c1a580 MS |
9259 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
9260 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
72fd0718 VZ |
9261 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
9262 | pgl_exp_rom2); | |
9263 | return -EAGAIN; | |
9264 | } | |
9265 | ||
9266 | barrier(); | |
9267 | ||
9268 | /* Close gates #2, #3 and #4 */ | |
9269 | bnx2x_set_234_gates(bp, true); | |
9270 | ||
c9ee9206 VZ |
9271 | /* Poll for IGU VQs for 57712 and newer chips */ |
9272 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
9273 | return -EAGAIN; | |
9274 | ||
72fd0718 VZ |
9275 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
9276 | ||
9277 | /* Clear "unprepared" bit */ | |
9278 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
9279 | barrier(); | |
9280 | ||
9281 | /* Make sure all is written to the chip before the reset */ | |
9282 | mmiowb(); | |
9283 | ||
9284 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
9285 | * PSWHST, GRC and PSWRD Tetris buffer. | |
9286 | */ | |
0926d499 | 9287 | usleep_range(1000, 2000); |
72fd0718 VZ |
9288 | |
9289 | /* Prepare to chip reset: */ | |
9290 | /* MCP */ | |
c9ee9206 VZ |
9291 | if (global) |
9292 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
9293 | |
9294 | /* PXP */ | |
9295 | bnx2x_pxp_prep(bp); | |
9296 | barrier(); | |
9297 | ||
9298 | /* reset the chip */ | |
c9ee9206 | 9299 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
9300 | barrier(); |
9301 | ||
9302 | /* Recover after reset: */ | |
9303 | /* MCP */ | |
c9ee9206 | 9304 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
9305 | return -EAGAIN; |
9306 | ||
c9ee9206 VZ |
9307 | /* TBD: Add resetting the NO_MCP mode DB here */ |
9308 | ||
72fd0718 VZ |
9309 | /* Open the gates #2, #3 and #4 */ |
9310 | bnx2x_set_234_gates(bp, false); | |
9311 | ||
9312 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
9313 | * reset state, re-enable attentions. */ | |
9314 | ||
a2fbb9ea ET |
9315 | return 0; |
9316 | } | |
9317 | ||
910cc727 | 9318 | static int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
9319 | { |
9320 | int rc = 0; | |
c9ee9206 | 9321 | bool global = bnx2x_reset_is_global(bp); |
95c6c616 AE |
9322 | u32 load_code; |
9323 | ||
9324 | /* if not going to reset MCP - load "fake" driver to reset HW while | |
9325 | * driver is owner of the HW | |
9326 | */ | |
9327 | if (!global && !BP_NOMCP(bp)) { | |
5d07d868 YM |
9328 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, |
9329 | DRV_MSG_CODE_LOAD_REQ_WITH_LFA); | |
95c6c616 AE |
9330 | if (!load_code) { |
9331 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9332 | rc = -EAGAIN; | |
9333 | goto exit_leader_reset; | |
9334 | } | |
9335 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && | |
9336 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { | |
9337 | BNX2X_ERR("MCP unexpected resp, aborting\n"); | |
9338 | rc = -EAGAIN; | |
9339 | goto exit_leader_reset2; | |
9340 | } | |
9341 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
9342 | if (!load_code) { | |
9343 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9344 | rc = -EAGAIN; | |
9345 | goto exit_leader_reset2; | |
9346 | } | |
9347 | } | |
c9ee9206 | 9348 | |
72fd0718 | 9349 | /* Try to recover after the failure */ |
c9ee9206 | 9350 | if (bnx2x_process_kill(bp, global)) { |
51c1a580 MS |
9351 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
9352 | BP_PATH(bp)); | |
72fd0718 | 9353 | rc = -EAGAIN; |
95c6c616 | 9354 | goto exit_leader_reset2; |
72fd0718 VZ |
9355 | } |
9356 | ||
c9ee9206 VZ |
9357 | /* |
9358 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
9359 | * state. | |
9360 | */ | |
72fd0718 | 9361 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
9362 | if (global) |
9363 | bnx2x_clear_reset_global(bp); | |
72fd0718 | 9364 | |
95c6c616 AE |
9365 | exit_leader_reset2: |
9366 | /* unload "fake driver" if it was loaded */ | |
9367 | if (!global && !BP_NOMCP(bp)) { | |
9368 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); | |
9369 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
9370 | } | |
72fd0718 VZ |
9371 | exit_leader_reset: |
9372 | bp->is_leader = 0; | |
c9ee9206 VZ |
9373 | bnx2x_release_leader_lock(bp); |
9374 | smp_mb(); | |
72fd0718 VZ |
9375 | return rc; |
9376 | } | |
9377 | ||
1191cb83 | 9378 | static void bnx2x_recovery_failed(struct bnx2x *bp) |
c9ee9206 VZ |
9379 | { |
9380 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
9381 | ||
9382 | /* Disconnect this device */ | |
9383 | netif_device_detach(bp->dev); | |
9384 | ||
9385 | /* | |
9386 | * Block ifup for all function on this engine until "process kill" | |
9387 | * or power cycle. | |
9388 | */ | |
9389 | bnx2x_set_reset_in_progress(bp); | |
9390 | ||
9391 | /* Shut down the power */ | |
9392 | bnx2x_set_power_state(bp, PCI_D3hot); | |
9393 | ||
9394 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
9395 | ||
9396 | smp_mb(); | |
9397 | } | |
9398 | ||
9399 | /* | |
9400 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 9401 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
9402 | * will never be called when netif_running(bp->dev) is false. |
9403 | */ | |
9404 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
9405 | { | |
c9ee9206 | 9406 | bool global = false; |
7a752993 | 9407 | u32 error_recovered, error_unrecovered; |
95c6c616 | 9408 | bool is_parity; |
c9ee9206 | 9409 | |
72fd0718 VZ |
9410 | DP(NETIF_MSG_HW, "Handling parity\n"); |
9411 | while (1) { | |
9412 | switch (bp->recovery_state) { | |
9413 | case BNX2X_RECOVERY_INIT: | |
9414 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
95c6c616 AE |
9415 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
9416 | WARN_ON(!is_parity); | |
c9ee9206 | 9417 | |
72fd0718 | 9418 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
9419 | if (bnx2x_trylock_leader_lock(bp)) { |
9420 | bnx2x_set_reset_in_progress(bp); | |
9421 | /* | |
9422 | * Check if there is a global attention and if | |
9423 | * there was a global attention, set the global | |
9424 | * reset bit. | |
9425 | */ | |
9426 | ||
9427 | if (global) | |
9428 | bnx2x_set_reset_global(bp); | |
9429 | ||
72fd0718 | 9430 | bp->is_leader = 1; |
c9ee9206 | 9431 | } |
72fd0718 VZ |
9432 | |
9433 | /* Stop the driver */ | |
9434 | /* If interface has been removed - break */ | |
5d07d868 | 9435 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) |
72fd0718 VZ |
9436 | return; |
9437 | ||
9438 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 | 9439 | |
c9ee9206 VZ |
9440 | /* Ensure "is_leader", MCP command sequence and |
9441 | * "recovery_state" update values are seen on other | |
9442 | * CPUs. | |
72fd0718 | 9443 | */ |
c9ee9206 | 9444 | smp_mb(); |
72fd0718 VZ |
9445 | break; |
9446 | ||
9447 | case BNX2X_RECOVERY_WAIT: | |
9448 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
9449 | if (bp->is_leader) { | |
c9ee9206 | 9450 | int other_engine = BP_PATH(bp) ? 0 : 1; |
889b9af3 AE |
9451 | bool other_load_status = |
9452 | bnx2x_get_load_status(bp, other_engine); | |
9453 | bool load_status = | |
9454 | bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
9455 | global = bnx2x_reset_is_global(bp); |
9456 | ||
9457 | /* | |
9458 | * In case of a parity in a global block, let | |
9459 | * the first leader that performs a | |
9460 | * leader_reset() reset the global blocks in | |
9461 | * order to clear global attentions. Otherwise | |
16a5fd92 | 9462 | * the gates will remain closed for that |
c9ee9206 VZ |
9463 | * engine. |
9464 | */ | |
889b9af3 AE |
9465 | if (load_status || |
9466 | (global && other_load_status)) { | |
72fd0718 VZ |
9467 | /* Wait until all other functions get |
9468 | * down. | |
9469 | */ | |
7be08a72 | 9470 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9471 | HZ/10); |
9472 | return; | |
9473 | } else { | |
9474 | /* If all other functions got down - | |
9475 | * try to bring the chip back to | |
9476 | * normal. In any case it's an exit | |
9477 | * point for a leader. | |
9478 | */ | |
c9ee9206 VZ |
9479 | if (bnx2x_leader_reset(bp)) { |
9480 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
9481 | return; |
9482 | } | |
9483 | ||
c9ee9206 VZ |
9484 | /* If we are here, means that the |
9485 | * leader has succeeded and doesn't | |
9486 | * want to be a leader any more. Try | |
9487 | * to continue as a none-leader. | |
9488 | */ | |
9489 | break; | |
72fd0718 VZ |
9490 | } |
9491 | } else { /* non-leader */ | |
c9ee9206 | 9492 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
9493 | /* Try to get a LEADER_LOCK HW lock as |
9494 | * long as a former leader may have | |
9495 | * been unloaded by the user or | |
9496 | * released a leadership by another | |
9497 | * reason. | |
9498 | */ | |
c9ee9206 | 9499 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
9500 | /* I'm a leader now! Restart a |
9501 | * switch case. | |
9502 | */ | |
9503 | bp->is_leader = 1; | |
9504 | break; | |
9505 | } | |
9506 | ||
7be08a72 | 9507 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9508 | HZ/10); |
9509 | return; | |
9510 | ||
c9ee9206 VZ |
9511 | } else { |
9512 | /* | |
9513 | * If there was a global attention, wait | |
9514 | * for it to be cleared. | |
9515 | */ | |
9516 | if (bnx2x_reset_is_global(bp)) { | |
9517 | schedule_delayed_work( | |
7be08a72 AE |
9518 | &bp->sp_rtnl_task, |
9519 | HZ/10); | |
c9ee9206 VZ |
9520 | return; |
9521 | } | |
9522 | ||
7a752993 AE |
9523 | error_recovered = |
9524 | bp->eth_stats.recoverable_error; | |
9525 | error_unrecovered = | |
9526 | bp->eth_stats.unrecoverable_error; | |
95c6c616 AE |
9527 | bp->recovery_state = |
9528 | BNX2X_RECOVERY_NIC_LOADING; | |
9529 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { | |
7a752993 | 9530 | error_unrecovered++; |
95c6c616 | 9531 | netdev_err(bp->dev, |
51c1a580 | 9532 | "Recovery failed. Power cycle needed\n"); |
95c6c616 AE |
9533 | /* Disconnect this device */ |
9534 | netif_device_detach(bp->dev); | |
9535 | /* Shut down the power */ | |
9536 | bnx2x_set_power_state( | |
9537 | bp, PCI_D3hot); | |
9538 | smp_mb(); | |
9539 | } else { | |
c9ee9206 VZ |
9540 | bp->recovery_state = |
9541 | BNX2X_RECOVERY_DONE; | |
7a752993 | 9542 | error_recovered++; |
c9ee9206 VZ |
9543 | smp_mb(); |
9544 | } | |
7a752993 AE |
9545 | bp->eth_stats.recoverable_error = |
9546 | error_recovered; | |
9547 | bp->eth_stats.unrecoverable_error = | |
9548 | error_unrecovered; | |
c9ee9206 | 9549 | |
72fd0718 VZ |
9550 | return; |
9551 | } | |
9552 | } | |
9553 | default: | |
9554 | return; | |
9555 | } | |
9556 | } | |
9557 | } | |
9558 | ||
56ad3152 MS |
9559 | static int bnx2x_close(struct net_device *dev); |
9560 | ||
72fd0718 VZ |
9561 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
9562 | * scheduled on a general queue in order to prevent a dead lock. | |
9563 | */ | |
7be08a72 | 9564 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 9565 | { |
7be08a72 | 9566 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
9567 | |
9568 | rtnl_lock(); | |
9569 | ||
8395be5e AE |
9570 | if (!netif_running(bp->dev)) { |
9571 | rtnl_unlock(); | |
9572 | return; | |
9573 | } | |
7be08a72 | 9574 | |
6bf07b8e | 9575 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
7be08a72 | 9576 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e YM |
9577 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
9578 | "you will need to reboot when done\n"); | |
9579 | goto sp_rtnl_not_reset; | |
7be08a72 | 9580 | #endif |
7be08a72 | 9581 | /* |
b1fb8740 VZ |
9582 | * Clear all pending SP commands as we are going to reset the |
9583 | * function anyway. | |
7be08a72 | 9584 | */ |
b1fb8740 VZ |
9585 | bp->sp_rtnl_state = 0; |
9586 | smp_mb(); | |
9587 | ||
72fd0718 | 9588 | bnx2x_parity_recover(bp); |
b1fb8740 | 9589 | |
8395be5e AE |
9590 | rtnl_unlock(); |
9591 | return; | |
b1fb8740 VZ |
9592 | } |
9593 | ||
9594 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
6bf07b8e YM |
9595 | #ifdef BNX2X_STOP_ON_ERROR |
9596 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" | |
9597 | "you will need to reboot when done\n"); | |
9598 | goto sp_rtnl_not_reset; | |
9599 | #endif | |
9600 | ||
b1fb8740 VZ |
9601 | /* |
9602 | * Clear all pending SP commands as we are going to reset the | |
9603 | * function anyway. | |
9604 | */ | |
9605 | bp->sp_rtnl_state = 0; | |
9606 | smp_mb(); | |
9607 | ||
5d07d868 | 9608 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); |
72fd0718 | 9609 | bnx2x_nic_load(bp, LOAD_NORMAL); |
b1fb8740 | 9610 | |
8395be5e AE |
9611 | rtnl_unlock(); |
9612 | return; | |
72fd0718 | 9613 | } |
b1fb8740 VZ |
9614 | #ifdef BNX2X_STOP_ON_ERROR |
9615 | sp_rtnl_not_reset: | |
9616 | #endif | |
9617 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
9618 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
a3348722 BW |
9619 | if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) |
9620 | bnx2x_after_function_update(bp); | |
8304859a AE |
9621 | /* |
9622 | * in case of fan failure we need to reset id if the "stop on error" | |
9623 | * debug flag is set, since we trying to prevent permanent overheating | |
9624 | * damage | |
9625 | */ | |
9626 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { | |
51c1a580 | 9627 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
8304859a AE |
9628 | netif_device_detach(bp->dev); |
9629 | bnx2x_close(bp->dev); | |
8395be5e AE |
9630 | rtnl_unlock(); |
9631 | return; | |
8304859a AE |
9632 | } |
9633 | ||
381ac16b AE |
9634 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { |
9635 | DP(BNX2X_MSG_SP, | |
9636 | "sending set mcast vf pf channel message from rtnl sp-task\n"); | |
9637 | bnx2x_vfpf_set_mcast(bp->dev); | |
9638 | } | |
78c3bcc5 AE |
9639 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, |
9640 | &bp->sp_rtnl_state)){ | |
9641 | if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) { | |
9642 | bnx2x_tx_disable(bp); | |
9643 | BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n"); | |
9644 | } | |
9645 | } | |
381ac16b AE |
9646 | |
9647 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, | |
9648 | &bp->sp_rtnl_state)) { | |
9649 | DP(BNX2X_MSG_SP, | |
9650 | "sending set storm rx mode vf pf channel message from rtnl sp-task\n"); | |
9651 | bnx2x_vfpf_storm_rx_mode(bp); | |
9652 | } | |
9653 | ||
3ec9f9ca AE |
9654 | if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, |
9655 | &bp->sp_rtnl_state)) | |
9656 | bnx2x_pf_set_vfs_vlan(bp); | |
9657 | ||
07b4eb3b DK |
9658 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) |
9659 | bnx2x_dcbx_stop_hw_tx(bp); | |
9660 | ||
9661 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_RESUME, &bp->sp_rtnl_state)) | |
9662 | bnx2x_dcbx_resume_hw_tx(bp); | |
9663 | ||
8395be5e AE |
9664 | /* work which needs rtnl lock not-taken (as it takes the lock itself and |
9665 | * can be called from other contexts as well) | |
9666 | */ | |
34f80b04 | 9667 | rtnl_unlock(); |
8395be5e | 9668 | |
6411280a | 9669 | /* enable SR-IOV if applicable */ |
8395be5e | 9670 | if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, |
3c76feff AE |
9671 | &bp->sp_rtnl_state)) { |
9672 | bnx2x_disable_sriov(bp); | |
6411280a | 9673 | bnx2x_enable_sriov(bp); |
3c76feff | 9674 | } |
34f80b04 EG |
9675 | } |
9676 | ||
3deb8167 YR |
9677 | static void bnx2x_period_task(struct work_struct *work) |
9678 | { | |
9679 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
9680 | ||
9681 | if (!netif_running(bp->dev)) | |
9682 | goto period_task_exit; | |
9683 | ||
9684 | if (CHIP_REV_IS_SLOW(bp)) { | |
9685 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
9686 | goto period_task_exit; | |
9687 | } | |
9688 | ||
9689 | bnx2x_acquire_phy_lock(bp); | |
9690 | /* | |
9691 | * The barrier is needed to ensure the ordering between the writing to | |
9692 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
9693 | * the reading here. | |
9694 | */ | |
9695 | smp_mb(); | |
9696 | if (bp->port.pmf) { | |
9697 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
9698 | ||
9699 | /* Re-queue task in 1 sec */ | |
9700 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
9701 | } | |
9702 | ||
9703 | bnx2x_release_phy_lock(bp); | |
9704 | period_task_exit: | |
9705 | return; | |
9706 | } | |
9707 | ||
a2fbb9ea ET |
9708 | /* |
9709 | * Init service functions | |
9710 | */ | |
9711 | ||
b56e9670 | 9712 | u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
9713 | { |
9714 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
9715 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
9716 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
9717 | } |
9718 | ||
1ef1d45a BW |
9719 | static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, |
9720 | struct bnx2x_mac_vals *vals) | |
34f80b04 | 9721 | { |
452427b0 YM |
9722 | u32 val, base_addr, offset, mask, reset_reg; |
9723 | bool mac_stopped = false; | |
9724 | u8 port = BP_PORT(bp); | |
34f80b04 | 9725 | |
1ef1d45a BW |
9726 | /* reset addresses as they also mark which values were changed */ |
9727 | vals->bmac_addr = 0; | |
9728 | vals->umac_addr = 0; | |
9729 | vals->xmac_addr = 0; | |
9730 | vals->emac_addr = 0; | |
9731 | ||
452427b0 | 9732 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
f16da43b | 9733 | |
452427b0 YM |
9734 | if (!CHIP_IS_E3(bp)) { |
9735 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
9736 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; | |
9737 | if ((mask & reset_reg) && val) { | |
9738 | u32 wb_data[2]; | |
9739 | BNX2X_DEV_INFO("Disable bmac Rx\n"); | |
9740 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM | |
9741 | : NIG_REG_INGRESS_BMAC0_MEM; | |
9742 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL | |
9743 | : BIGMAC_REGISTER_BMAC_CONTROL; | |
7a06a122 | 9744 | |
452427b0 YM |
9745 | /* |
9746 | * use rd/wr since we cannot use dmae. This is safe | |
9747 | * since MCP won't access the bus due to the request | |
9748 | * to unload, and no function on the path can be | |
9749 | * loaded at this time. | |
9750 | */ | |
9751 | wb_data[0] = REG_RD(bp, base_addr + offset); | |
9752 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); | |
1ef1d45a BW |
9753 | vals->bmac_addr = base_addr + offset; |
9754 | vals->bmac_val[0] = wb_data[0]; | |
9755 | vals->bmac_val[1] = wb_data[1]; | |
452427b0 | 9756 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
1ef1d45a BW |
9757 | REG_WR(bp, vals->bmac_addr, wb_data[0]); |
9758 | REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); | |
452427b0 YM |
9759 | } |
9760 | BNX2X_DEV_INFO("Disable emac Rx\n"); | |
1ef1d45a BW |
9761 | vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; |
9762 | vals->emac_val = REG_RD(bp, vals->emac_addr); | |
9763 | REG_WR(bp, vals->emac_addr, 0); | |
452427b0 YM |
9764 | mac_stopped = true; |
9765 | } else { | |
9766 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
9767 | BNX2X_DEV_INFO("Disable xmac Rx\n"); | |
9768 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
9769 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); | |
9770 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9771 | val & ~(1 << 1)); | |
9772 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9773 | val | (1 << 1)); | |
1ef1d45a BW |
9774 | vals->xmac_addr = base_addr + XMAC_REG_CTRL; |
9775 | vals->xmac_val = REG_RD(bp, vals->xmac_addr); | |
9776 | REG_WR(bp, vals->xmac_addr, 0); | |
452427b0 YM |
9777 | mac_stopped = true; |
9778 | } | |
9779 | mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; | |
9780 | if (mask & reset_reg) { | |
9781 | BNX2X_DEV_INFO("Disable umac Rx\n"); | |
9782 | base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1ef1d45a BW |
9783 | vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG; |
9784 | vals->umac_val = REG_RD(bp, vals->umac_addr); | |
9785 | REG_WR(bp, vals->umac_addr, 0); | |
452427b0 YM |
9786 | mac_stopped = true; |
9787 | } | |
9788 | } | |
9789 | ||
9790 | if (mac_stopped) | |
9791 | msleep(20); | |
452427b0 YM |
9792 | } |
9793 | ||
9794 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) | |
9795 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) | |
9796 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) | |
9797 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) | |
9798 | ||
1dd06ae8 | 9799 | static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc) |
452427b0 YM |
9800 | { |
9801 | u16 rcq, bd; | |
9802 | u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port)); | |
9803 | ||
9804 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; | |
9805 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; | |
9806 | ||
9807 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); | |
9808 | REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg); | |
9809 | ||
9810 | BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", | |
9811 | port, bd, rcq); | |
9812 | } | |
9813 | ||
0329aba1 | 9814 | static int bnx2x_prev_mcp_done(struct bnx2x *bp) |
452427b0 | 9815 | { |
5d07d868 YM |
9816 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, |
9817 | DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); | |
452427b0 YM |
9818 | if (!rc) { |
9819 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9820 | return -EBUSY; | |
9821 | } | |
9822 | ||
9823 | return 0; | |
9824 | } | |
9825 | ||
c63da990 BW |
9826 | static struct bnx2x_prev_path_list * |
9827 | bnx2x_prev_path_get_entry(struct bnx2x *bp) | |
9828 | { | |
9829 | struct bnx2x_prev_path_list *tmp_list; | |
9830 | ||
9831 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) | |
9832 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
9833 | bp->pdev->bus->number == tmp_list->bus && | |
9834 | BP_PATH(bp) == tmp_list->path) | |
9835 | return tmp_list; | |
9836 | ||
9837 | return NULL; | |
9838 | } | |
9839 | ||
7fa6f340 YM |
9840 | static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) |
9841 | { | |
9842 | struct bnx2x_prev_path_list *tmp_list; | |
9843 | int rc; | |
9844 | ||
9845 | rc = down_interruptible(&bnx2x_prev_sem); | |
9846 | if (rc) { | |
9847 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
9848 | return rc; | |
9849 | } | |
9850 | ||
9851 | tmp_list = bnx2x_prev_path_get_entry(bp); | |
9852 | if (tmp_list) { | |
9853 | tmp_list->aer = 1; | |
9854 | rc = 0; | |
9855 | } else { | |
9856 | BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n", | |
9857 | BP_PATH(bp)); | |
9858 | } | |
9859 | ||
9860 | up(&bnx2x_prev_sem); | |
9861 | ||
9862 | return rc; | |
9863 | } | |
9864 | ||
0329aba1 | 9865 | static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) |
452427b0 YM |
9866 | { |
9867 | struct bnx2x_prev_path_list *tmp_list; | |
9868 | int rc = false; | |
9869 | ||
9870 | if (down_trylock(&bnx2x_prev_sem)) | |
9871 | return false; | |
9872 | ||
7fa6f340 YM |
9873 | tmp_list = bnx2x_prev_path_get_entry(bp); |
9874 | if (tmp_list) { | |
9875 | if (tmp_list->aer) { | |
9876 | DP(NETIF_MSG_HW, "Path %d was marked by AER\n", | |
9877 | BP_PATH(bp)); | |
9878 | } else { | |
452427b0 YM |
9879 | rc = true; |
9880 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | |
9881 | BP_PATH(bp)); | |
452427b0 YM |
9882 | } |
9883 | } | |
9884 | ||
9885 | up(&bnx2x_prev_sem); | |
9886 | ||
9887 | return rc; | |
9888 | } | |
9889 | ||
178135c1 DK |
9890 | bool bnx2x_port_after_undi(struct bnx2x *bp) |
9891 | { | |
9892 | struct bnx2x_prev_path_list *entry; | |
9893 | bool val; | |
9894 | ||
9895 | down(&bnx2x_prev_sem); | |
9896 | ||
9897 | entry = bnx2x_prev_path_get_entry(bp); | |
9898 | val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); | |
9899 | ||
9900 | up(&bnx2x_prev_sem); | |
9901 | ||
9902 | return val; | |
9903 | } | |
9904 | ||
c63da990 | 9905 | static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) |
452427b0 YM |
9906 | { |
9907 | struct bnx2x_prev_path_list *tmp_list; | |
9908 | int rc; | |
9909 | ||
7fa6f340 YM |
9910 | rc = down_interruptible(&bnx2x_prev_sem); |
9911 | if (rc) { | |
9912 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
9913 | return rc; | |
9914 | } | |
9915 | ||
9916 | /* Check whether the entry for this path already exists */ | |
9917 | tmp_list = bnx2x_prev_path_get_entry(bp); | |
9918 | if (tmp_list) { | |
9919 | if (!tmp_list->aer) { | |
9920 | BNX2X_ERR("Re-Marking the path.\n"); | |
9921 | } else { | |
9922 | DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", | |
9923 | BP_PATH(bp)); | |
9924 | tmp_list->aer = 0; | |
9925 | } | |
9926 | up(&bnx2x_prev_sem); | |
9927 | return 0; | |
9928 | } | |
9929 | up(&bnx2x_prev_sem); | |
9930 | ||
9931 | /* Create an entry for this path and add it */ | |
ea4b3857 | 9932 | tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); |
452427b0 YM |
9933 | if (!tmp_list) { |
9934 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | |
9935 | return -ENOMEM; | |
9936 | } | |
9937 | ||
9938 | tmp_list->bus = bp->pdev->bus->number; | |
9939 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | |
9940 | tmp_list->path = BP_PATH(bp); | |
7fa6f340 | 9941 | tmp_list->aer = 0; |
c63da990 | 9942 | tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; |
452427b0 YM |
9943 | |
9944 | rc = down_interruptible(&bnx2x_prev_sem); | |
9945 | if (rc) { | |
9946 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
9947 | kfree(tmp_list); | |
9948 | } else { | |
7fa6f340 YM |
9949 | DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", |
9950 | BP_PATH(bp)); | |
452427b0 YM |
9951 | list_add(&tmp_list->list, &bnx2x_prev_list); |
9952 | up(&bnx2x_prev_sem); | |
9953 | } | |
9954 | ||
9955 | return rc; | |
9956 | } | |
9957 | ||
0329aba1 | 9958 | static int bnx2x_do_flr(struct bnx2x *bp) |
452427b0 | 9959 | { |
2a80eebc | 9960 | int i; |
452427b0 YM |
9961 | u16 status; |
9962 | struct pci_dev *dev = bp->pdev; | |
9963 | ||
8eee694c YM |
9964 | if (CHIP_IS_E1x(bp)) { |
9965 | BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); | |
9966 | return -EINVAL; | |
9967 | } | |
9968 | ||
9969 | /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ | |
9970 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | |
9971 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | |
9972 | bp->common.bc_ver); | |
9973 | return -EINVAL; | |
9974 | } | |
452427b0 | 9975 | |
452427b0 YM |
9976 | /* Wait for Transaction Pending bit clean */ |
9977 | for (i = 0; i < 4; i++) { | |
9978 | if (i) | |
9979 | msleep((1 << (i - 1)) * 100); | |
9980 | ||
2a80eebc | 9981 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
452427b0 YM |
9982 | if (!(status & PCI_EXP_DEVSTA_TRPND)) |
9983 | goto clear; | |
9984 | } | |
9985 | ||
9986 | dev_err(&dev->dev, | |
9987 | "transaction is not cleared; proceeding with reset anyway\n"); | |
9988 | ||
9989 | clear: | |
452427b0 | 9990 | |
8eee694c | 9991 | BNX2X_DEV_INFO("Initiating FLR\n"); |
452427b0 YM |
9992 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); |
9993 | ||
9994 | return 0; | |
9995 | } | |
9996 | ||
0329aba1 | 9997 | static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) |
452427b0 YM |
9998 | { |
9999 | int rc; | |
10000 | ||
10001 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); | |
10002 | ||
10003 | /* Test if previous unload process was already finished for this path */ | |
10004 | if (bnx2x_prev_is_path_marked(bp)) | |
10005 | return bnx2x_prev_mcp_done(bp); | |
10006 | ||
04c46736 YM |
10007 | BNX2X_DEV_INFO("Path is unmarked\n"); |
10008 | ||
452427b0 YM |
10009 | /* If function has FLR capabilities, and existing FW version matches |
10010 | * the one required, then FLR will be sufficient to clean any residue | |
10011 | * left by previous driver | |
10012 | */ | |
ad5afc89 | 10013 | rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION); |
8eee694c YM |
10014 | |
10015 | if (!rc) { | |
10016 | /* fw version is good */ | |
10017 | BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); | |
10018 | rc = bnx2x_do_flr(bp); | |
10019 | } | |
10020 | ||
10021 | if (!rc) { | |
10022 | /* FLR was performed */ | |
10023 | BNX2X_DEV_INFO("FLR successful\n"); | |
10024 | return 0; | |
10025 | } | |
10026 | ||
10027 | BNX2X_DEV_INFO("Could not FLR\n"); | |
452427b0 YM |
10028 | |
10029 | /* Close the MCP request, return failure*/ | |
10030 | rc = bnx2x_prev_mcp_done(bp); | |
10031 | if (!rc) | |
10032 | rc = BNX2X_PREV_WAIT_NEEDED; | |
10033 | ||
10034 | return rc; | |
10035 | } | |
10036 | ||
0329aba1 | 10037 | static int bnx2x_prev_unload_common(struct bnx2x *bp) |
452427b0 YM |
10038 | { |
10039 | u32 reset_reg, tmp_reg = 0, rc; | |
c63da990 | 10040 | bool prev_undi = false; |
1ef1d45a BW |
10041 | struct bnx2x_mac_vals mac_vals; |
10042 | ||
452427b0 YM |
10043 | /* It is possible a previous function received 'common' answer, |
10044 | * but hasn't loaded yet, therefore creating a scenario of | |
10045 | * multiple functions receiving 'common' on the same path. | |
10046 | */ | |
10047 | BNX2X_DEV_INFO("Common unload Flow\n"); | |
10048 | ||
1ef1d45a BW |
10049 | memset(&mac_vals, 0, sizeof(mac_vals)); |
10050 | ||
452427b0 YM |
10051 | if (bnx2x_prev_is_path_marked(bp)) |
10052 | return bnx2x_prev_mcp_done(bp); | |
10053 | ||
10054 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); | |
10055 | ||
10056 | /* Reset should be performed after BRB is emptied */ | |
10057 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { | |
10058 | u32 timer_count = 1000; | |
452427b0 YM |
10059 | |
10060 | /* Close the MAC Rx to prevent BRB from filling up */ | |
1ef1d45a BW |
10061 | bnx2x_prev_unload_close_mac(bp, &mac_vals); |
10062 | ||
10063 | /* close LLH filters towards the BRB */ | |
10064 | bnx2x_set_rx_filter(&bp->link_params, 0); | |
452427b0 YM |
10065 | |
10066 | /* Check if the UNDI driver was previously loaded | |
34f80b04 EG |
10067 | * UNDI driver initializes CID offset for normal bell to 0x7 |
10068 | */ | |
452427b0 YM |
10069 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { |
10070 | tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST); | |
10071 | if (tmp_reg == 0x7) { | |
10072 | BNX2X_DEV_INFO("UNDI previously loaded\n"); | |
10073 | prev_undi = true; | |
10074 | /* clear the UNDI indication */ | |
10075 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
a74801c5 YM |
10076 | /* clear possible idle check errors */ |
10077 | REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); | |
34f80b04 | 10078 | } |
452427b0 | 10079 | } |
d46f7c4d DK |
10080 | if (!CHIP_IS_E1x(bp)) |
10081 | /* block FW from writing to host */ | |
10082 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
10083 | ||
452427b0 YM |
10084 | /* wait until BRB is empty */ |
10085 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); | |
10086 | while (timer_count) { | |
10087 | u32 prev_brb = tmp_reg; | |
34f80b04 | 10088 | |
452427b0 YM |
10089 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
10090 | if (!tmp_reg) | |
10091 | break; | |
619c5cb6 | 10092 | |
452427b0 | 10093 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
619c5cb6 | 10094 | |
452427b0 YM |
10095 | /* reset timer as long as BRB actually gets emptied */ |
10096 | if (prev_brb > tmp_reg) | |
10097 | timer_count = 1000; | |
10098 | else | |
10099 | timer_count--; | |
da5a662a | 10100 | |
452427b0 YM |
10101 | /* If UNDI resides in memory, manually increment it */ |
10102 | if (prev_undi) | |
10103 | bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1); | |
da5a662a | 10104 | |
452427b0 | 10105 | udelay(10); |
7a06a122 | 10106 | } |
452427b0 YM |
10107 | |
10108 | if (!timer_count) | |
10109 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); | |
34f80b04 | 10110 | } |
f16da43b | 10111 | |
452427b0 YM |
10112 | /* No packets are in the pipeline, path is ready for reset */ |
10113 | bnx2x_reset_common(bp); | |
10114 | ||
1ef1d45a BW |
10115 | if (mac_vals.xmac_addr) |
10116 | REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); | |
10117 | if (mac_vals.umac_addr) | |
10118 | REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val); | |
10119 | if (mac_vals.emac_addr) | |
10120 | REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); | |
10121 | if (mac_vals.bmac_addr) { | |
10122 | REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); | |
10123 | REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); | |
10124 | } | |
10125 | ||
c63da990 | 10126 | rc = bnx2x_prev_mark_path(bp, prev_undi); |
452427b0 YM |
10127 | if (rc) { |
10128 | bnx2x_prev_mcp_done(bp); | |
10129 | return rc; | |
10130 | } | |
10131 | ||
10132 | return bnx2x_prev_mcp_done(bp); | |
10133 | } | |
10134 | ||
24f06716 AE |
10135 | /* previous driver DMAE transaction may have occurred when pre-boot stage ended |
10136 | * and boot began, or when kdump kernel was loaded. Either case would invalidate | |
10137 | * the addresses of the transaction, resulting in was-error bit set in the pci | |
10138 | * causing all hw-to-host pcie transactions to timeout. If this happened we want | |
10139 | * to clear the interrupt which detected this from the pglueb and the was done | |
10140 | * bit | |
10141 | */ | |
0329aba1 | 10142 | static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp) |
24f06716 | 10143 | { |
4a25417c AE |
10144 | if (!CHIP_IS_E1x(bp)) { |
10145 | u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS); | |
10146 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) { | |
04c46736 YM |
10147 | DP(BNX2X_MSG_SP, |
10148 | "'was error' bit was found to be set in pglueb upon startup. Clearing\n"); | |
4a25417c AE |
10149 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, |
10150 | 1 << BP_FUNC(bp)); | |
10151 | } | |
24f06716 AE |
10152 | } |
10153 | } | |
10154 | ||
0329aba1 | 10155 | static int bnx2x_prev_unload(struct bnx2x *bp) |
452427b0 YM |
10156 | { |
10157 | int time_counter = 10; | |
10158 | u32 rc, fw, hw_lock_reg, hw_lock_val; | |
10159 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); | |
10160 | ||
24f06716 AE |
10161 | /* clear hw from errors which may have resulted from an interrupted |
10162 | * dmae transaction. | |
10163 | */ | |
10164 | bnx2x_prev_interrupted_dmae(bp); | |
10165 | ||
10166 | /* Release previously held locks */ | |
452427b0 YM |
10167 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? |
10168 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : | |
10169 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); | |
10170 | ||
3cdeec22 | 10171 | hw_lock_val = REG_RD(bp, hw_lock_reg); |
452427b0 YM |
10172 | if (hw_lock_val) { |
10173 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { | |
10174 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); | |
10175 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
10176 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); | |
10177 | } | |
10178 | ||
10179 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); | |
10180 | REG_WR(bp, hw_lock_reg, 0xffffffff); | |
10181 | } else | |
10182 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); | |
10183 | ||
10184 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { | |
10185 | BNX2X_DEV_INFO("Release previously held alr\n"); | |
3cdeec22 | 10186 | bnx2x_release_alr(bp); |
452427b0 YM |
10187 | } |
10188 | ||
452427b0 | 10189 | do { |
7fa6f340 | 10190 | int aer = 0; |
452427b0 YM |
10191 | /* Lock MCP using an unload request */ |
10192 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | |
10193 | if (!fw) { | |
10194 | BNX2X_ERR("MCP response failure, aborting\n"); | |
10195 | rc = -EBUSY; | |
10196 | break; | |
10197 | } | |
10198 | ||
7fa6f340 YM |
10199 | rc = down_interruptible(&bnx2x_prev_sem); |
10200 | if (rc) { | |
10201 | BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n", | |
10202 | rc); | |
10203 | } else { | |
10204 | /* If Path is marked by EEH, ignore unload status */ | |
10205 | aer = !!(bnx2x_prev_path_get_entry(bp) && | |
10206 | bnx2x_prev_path_get_entry(bp)->aer); | |
60cde81f | 10207 | up(&bnx2x_prev_sem); |
7fa6f340 | 10208 | } |
7fa6f340 YM |
10209 | |
10210 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) { | |
452427b0 YM |
10211 | rc = bnx2x_prev_unload_common(bp); |
10212 | break; | |
10213 | } | |
10214 | ||
16a5fd92 | 10215 | /* non-common reply from MCP might require looping */ |
452427b0 YM |
10216 | rc = bnx2x_prev_unload_uncommon(bp); |
10217 | if (rc != BNX2X_PREV_WAIT_NEEDED) | |
10218 | break; | |
10219 | ||
10220 | msleep(20); | |
10221 | } while (--time_counter); | |
10222 | ||
10223 | if (!time_counter || rc) { | |
10224 | BNX2X_ERR("Failed unloading previous driver, aborting\n"); | |
10225 | rc = -EBUSY; | |
10226 | } | |
10227 | ||
c63da990 | 10228 | /* Mark function if its port was used to boot from SAN */ |
178135c1 | 10229 | if (bnx2x_port_after_undi(bp)) |
c63da990 BW |
10230 | bp->link_params.feature_config_flags |= |
10231 | FEATURE_CONFIG_BOOT_FROM_SAN; | |
10232 | ||
452427b0 YM |
10233 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); |
10234 | ||
10235 | return rc; | |
34f80b04 EG |
10236 | } |
10237 | ||
0329aba1 | 10238 | static void bnx2x_get_common_hwinfo(struct bnx2x *bp) |
34f80b04 | 10239 | { |
1d187b34 | 10240 | u32 val, val2, val3, val4, id, boot_mode; |
72ce58c3 | 10241 | u16 pmc; |
34f80b04 EG |
10242 | |
10243 | /* Get the chip revision id and number. */ | |
10244 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
10245 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
10246 | id = ((val & 0xffff) << 16); | |
10247 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
10248 | id |= ((val & 0xf) << 12); | |
f22fdf25 YM |
10249 | |
10250 | /* Metal is read from PCI regs, but we can't access >=0x400 from | |
10251 | * the configuration space (so we need to reg_rd) | |
10252 | */ | |
10253 | val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); | |
10254 | id |= (((val >> 24) & 0xf) << 4); | |
5a40e08e | 10255 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
10256 | id |= (val & 0xf); |
10257 | bp->common.chip_id = id; | |
523224a3 | 10258 | |
7e8e02df BW |
10259 | /* force 57811 according to MISC register */ |
10260 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { | |
10261 | if (CHIP_IS_57810(bp)) | |
10262 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | | |
10263 | (bp->common.chip_id & 0x0000FFFF); | |
10264 | else if (CHIP_IS_57810_MF(bp)) | |
10265 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | | |
10266 | (bp->common.chip_id & 0x0000FFFF); | |
10267 | bp->common.chip_id |= 0x1; | |
10268 | } | |
10269 | ||
523224a3 DK |
10270 | /* Set doorbell size */ |
10271 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
10272 | ||
619c5cb6 | 10273 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
10274 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
10275 | if ((val & 1) == 0) | |
10276 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
10277 | else | |
10278 | val = (val >> 1) & 1; | |
10279 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
10280 | "2_PORT_MODE"); | |
10281 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
10282 | CHIP_2_PORT_MODE; | |
10283 | ||
10284 | if (CHIP_MODE_IS_4_PORT(bp)) | |
10285 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
10286 | else | |
10287 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
10288 | } else { | |
10289 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
10290 | bp->pfid = bp->pf_num; /* 0..7 */ | |
10291 | } | |
10292 | ||
51c1a580 MS |
10293 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
10294 | ||
f2e0899f DK |
10295 | bp->link_params.chip_id = bp->common.chip_id; |
10296 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 10297 | |
1c06328c EG |
10298 | val = (REG_RD(bp, 0x2874) & 0x55); |
10299 | if ((bp->common.chip_id & 0x1) || | |
10300 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
10301 | bp->flags |= ONE_PORT_FLAG; | |
10302 | BNX2X_DEV_INFO("single port device\n"); | |
10303 | } | |
10304 | ||
34f80b04 | 10305 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 10306 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
10307 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
10308 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
10309 | bp->common.flash_size, bp->common.flash_size); | |
10310 | ||
1b6e2ceb DK |
10311 | bnx2x_init_shmem(bp); |
10312 | ||
f2e0899f DK |
10313 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
10314 | MISC_REG_GENERIC_CR_1 : | |
10315 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 10316 | |
34f80b04 | 10317 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 10318 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
b884d95b YR |
10319 | if (SHMEM2_RD(bp, size) > |
10320 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
10321 | bp->link_params.lfa_base = | |
10322 | REG_RD(bp, bp->common.shmem2_base + | |
10323 | (u32)offsetof(struct shmem2_region, | |
10324 | lfa_host_addr[BP_PORT(bp)])); | |
10325 | else | |
10326 | bp->link_params.lfa_base = 0; | |
2691d51d EG |
10327 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
10328 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 10329 | |
f2e0899f | 10330 | if (!bp->common.shmem_base) { |
34f80b04 EG |
10331 | BNX2X_DEV_INFO("MCP not active\n"); |
10332 | bp->flags |= NO_MCP_FLAG; | |
10333 | return; | |
10334 | } | |
10335 | ||
34f80b04 | 10336 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 10337 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
10338 | |
10339 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
10340 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
10341 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
10342 | ||
c2c8b03e EG |
10343 | bp->link_params.feature_config_flags = 0; |
10344 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
10345 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
10346 | bp->link_params.feature_config_flags |= | |
10347 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
10348 | else | |
10349 | bp->link_params.feature_config_flags &= | |
10350 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
10351 | ||
34f80b04 EG |
10352 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
10353 | bp->common.bc_ver = val; | |
10354 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
10355 | if (val < BNX2X_BC_VER) { | |
10356 | /* for now only warn | |
10357 | * later we might need to enforce this */ | |
51c1a580 MS |
10358 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
10359 | BNX2X_BC_VER, val); | |
34f80b04 | 10360 | } |
4d295db0 | 10361 | bp->link_params.feature_config_flags |= |
a22f0788 | 10362 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
10363 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
10364 | ||
a22f0788 YR |
10365 | bp->link_params.feature_config_flags |= |
10366 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
10367 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
a3348722 BW |
10368 | bp->link_params.feature_config_flags |= |
10369 | (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? | |
10370 | FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; | |
85242eea YR |
10371 | bp->link_params.feature_config_flags |= |
10372 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
10373 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
55386fe8 YR |
10374 | |
10375 | bp->link_params.feature_config_flags |= | |
10376 | (val >= REQ_BC_VER_4_MT_SUPPORTED) ? | |
10377 | FEATURE_CONFIG_MT_SUPPORT : 0; | |
10378 | ||
0e898dd7 BW |
10379 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
10380 | BC_SUPPORTS_PFC_STATS : 0; | |
85242eea | 10381 | |
2e499d3c BW |
10382 | bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? |
10383 | BC_SUPPORTS_FCOE_FEATURES : 0; | |
10384 | ||
9876879f BW |
10385 | bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? |
10386 | BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; | |
a6d3a5ba BW |
10387 | |
10388 | bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? | |
10389 | BC_SUPPORTS_RMMOD_CMD : 0; | |
10390 | ||
1d187b34 BW |
10391 | boot_mode = SHMEM_RD(bp, |
10392 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & | |
10393 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; | |
10394 | switch (boot_mode) { | |
10395 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: | |
10396 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; | |
10397 | break; | |
10398 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: | |
10399 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; | |
10400 | break; | |
10401 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: | |
10402 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; | |
10403 | break; | |
10404 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: | |
10405 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; | |
10406 | break; | |
10407 | } | |
10408 | ||
f9a3ebbe DK |
10409 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); |
10410 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; | |
10411 | ||
72ce58c3 | 10412 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 10413 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
10414 | |
10415 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
10416 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
10417 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
10418 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
10419 | ||
cdaa7cb8 VZ |
10420 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
10421 | val, val2, val3, val4); | |
34f80b04 EG |
10422 | } |
10423 | ||
f2e0899f DK |
10424 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
10425 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
10426 | ||
0329aba1 | 10427 | static int bnx2x_get_igu_cam_info(struct bnx2x *bp) |
f2e0899f DK |
10428 | { |
10429 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
10430 | int igu_sb_id; |
10431 | u32 val; | |
6383c0b3 | 10432 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
10433 | |
10434 | bp->igu_base_sb = 0xff; | |
f2e0899f | 10435 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 10436 | int vn = BP_VN(bp); |
6383c0b3 | 10437 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
10438 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
10439 | FP_SB_MAX_E1x; | |
10440 | ||
10441 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
10442 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
10443 | ||
9b341bb1 | 10444 | return 0; |
f2e0899f DK |
10445 | } |
10446 | ||
10447 | /* IGU in normal mode - read CAM */ | |
10448 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
10449 | igu_sb_id++) { | |
10450 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
10451 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
10452 | continue; | |
10453 | fid = IGU_FID(val); | |
10454 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
10455 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
10456 | continue; | |
10457 | if (IGU_VEC(val) == 0) | |
10458 | /* default status block */ | |
10459 | bp->igu_dsb_id = igu_sb_id; | |
10460 | else { | |
10461 | if (bp->igu_base_sb == 0xff) | |
10462 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 10463 | igu_sb_cnt++; |
f2e0899f DK |
10464 | } |
10465 | } | |
10466 | } | |
619c5cb6 | 10467 | |
6383c0b3 | 10468 | #ifdef CONFIG_PCI_MSI |
185d4c8b AE |
10469 | /* Due to new PF resource allocation by MFW T7.4 and above, it's |
10470 | * optional that number of CAM entries will not be equal to the value | |
10471 | * advertised in PCI. | |
10472 | * Driver should use the minimal value of both as the actual status | |
10473 | * block count | |
619c5cb6 | 10474 | */ |
185d4c8b | 10475 | bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); |
6383c0b3 | 10476 | #endif |
619c5cb6 | 10477 | |
9b341bb1 | 10478 | if (igu_sb_cnt == 0) { |
f2e0899f | 10479 | BNX2X_ERR("CAM configuration error\n"); |
9b341bb1 BW |
10480 | return -EINVAL; |
10481 | } | |
10482 | ||
10483 | return 0; | |
f2e0899f DK |
10484 | } |
10485 | ||
1dd06ae8 | 10486 | static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) |
a2fbb9ea | 10487 | { |
a22f0788 YR |
10488 | int cfg_size = 0, idx, port = BP_PORT(bp); |
10489 | ||
10490 | /* Aggregation of supported attributes of all external phys */ | |
10491 | bp->port.supported[0] = 0; | |
10492 | bp->port.supported[1] = 0; | |
b7737c9b YR |
10493 | switch (bp->link_params.num_phys) { |
10494 | case 1: | |
a22f0788 YR |
10495 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
10496 | cfg_size = 1; | |
10497 | break; | |
b7737c9b | 10498 | case 2: |
a22f0788 YR |
10499 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
10500 | cfg_size = 1; | |
10501 | break; | |
10502 | case 3: | |
10503 | if (bp->link_params.multi_phy_config & | |
10504 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
10505 | bp->port.supported[1] = | |
10506 | bp->link_params.phy[EXT_PHY1].supported; | |
10507 | bp->port.supported[0] = | |
10508 | bp->link_params.phy[EXT_PHY2].supported; | |
10509 | } else { | |
10510 | bp->port.supported[0] = | |
10511 | bp->link_params.phy[EXT_PHY1].supported; | |
10512 | bp->port.supported[1] = | |
10513 | bp->link_params.phy[EXT_PHY2].supported; | |
10514 | } | |
10515 | cfg_size = 2; | |
10516 | break; | |
b7737c9b | 10517 | } |
a2fbb9ea | 10518 | |
a22f0788 | 10519 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
51c1a580 | 10520 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 10521 | SHMEM_RD(bp, |
a22f0788 YR |
10522 | dev_info.port_hw_config[port].external_phy_config), |
10523 | SHMEM_RD(bp, | |
10524 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 10525 | return; |
f85582f8 | 10526 | } |
a2fbb9ea | 10527 | |
619c5cb6 VZ |
10528 | if (CHIP_IS_E3(bp)) |
10529 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
10530 | else { | |
10531 | switch (switch_cfg) { | |
10532 | case SWITCH_CFG_1G: | |
10533 | bp->port.phy_addr = REG_RD( | |
10534 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
10535 | break; | |
10536 | case SWITCH_CFG_10G: | |
10537 | bp->port.phy_addr = REG_RD( | |
10538 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
10539 | break; | |
10540 | default: | |
10541 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
10542 | bp->port.link_config[0]); | |
10543 | return; | |
10544 | } | |
a2fbb9ea | 10545 | } |
619c5cb6 | 10546 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
10547 | /* mask what we support according to speed_cap_mask per configuration */ |
10548 | for (idx = 0; idx < cfg_size; idx++) { | |
10549 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 10550 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 10551 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 10552 | |
a22f0788 | 10553 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10554 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 10555 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 10556 | |
a22f0788 | 10557 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10558 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 10559 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 10560 | |
a22f0788 | 10561 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10562 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 10563 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 10564 | |
a22f0788 | 10565 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10566 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 10567 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 10568 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 10569 | |
a22f0788 | 10570 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10571 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 10572 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 10573 | |
a22f0788 | 10574 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10575 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 | 10576 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
b8e0d884 YR |
10577 | |
10578 | if (!(bp->link_params.speed_cap_mask[idx] & | |
10579 | PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) | |
10580 | bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; | |
a22f0788 | 10581 | } |
a2fbb9ea | 10582 | |
a22f0788 YR |
10583 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
10584 | bp->port.supported[1]); | |
a2fbb9ea ET |
10585 | } |
10586 | ||
0329aba1 | 10587 | static void bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 10588 | { |
a22f0788 YR |
10589 | u32 link_config, idx, cfg_size = 0; |
10590 | bp->port.advertising[0] = 0; | |
10591 | bp->port.advertising[1] = 0; | |
10592 | switch (bp->link_params.num_phys) { | |
10593 | case 1: | |
10594 | case 2: | |
10595 | cfg_size = 1; | |
10596 | break; | |
10597 | case 3: | |
10598 | cfg_size = 2; | |
10599 | break; | |
10600 | } | |
10601 | for (idx = 0; idx < cfg_size; idx++) { | |
10602 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
10603 | link_config = bp->port.link_config[idx]; | |
10604 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 10605 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
10606 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
10607 | bp->link_params.req_line_speed[idx] = | |
10608 | SPEED_AUTO_NEG; | |
10609 | bp->port.advertising[idx] |= | |
10610 | bp->port.supported[idx]; | |
10bd1f24 MY |
10611 | if (bp->link_params.phy[EXT_PHY1].type == |
10612 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
10613 | bp->port.advertising[idx] |= | |
10614 | (SUPPORTED_100baseT_Half | | |
10615 | SUPPORTED_100baseT_Full); | |
f85582f8 DK |
10616 | } else { |
10617 | /* force 10G, no AN */ | |
a22f0788 YR |
10618 | bp->link_params.req_line_speed[idx] = |
10619 | SPEED_10000; | |
10620 | bp->port.advertising[idx] |= | |
10621 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 10622 | ADVERTISED_FIBRE); |
a22f0788 | 10623 | continue; |
f85582f8 DK |
10624 | } |
10625 | break; | |
a2fbb9ea | 10626 | |
f85582f8 | 10627 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
10628 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
10629 | bp->link_params.req_line_speed[idx] = | |
10630 | SPEED_10; | |
10631 | bp->port.advertising[idx] |= | |
10632 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
10633 | ADVERTISED_TP); |
10634 | } else { | |
51c1a580 | 10635 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 | 10636 | link_config, |
a22f0788 | 10637 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
10638 | return; |
10639 | } | |
10640 | break; | |
a2fbb9ea | 10641 | |
f85582f8 | 10642 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
10643 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
10644 | bp->link_params.req_line_speed[idx] = | |
10645 | SPEED_10; | |
10646 | bp->link_params.req_duplex[idx] = | |
10647 | DUPLEX_HALF; | |
10648 | bp->port.advertising[idx] |= | |
10649 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
10650 | ADVERTISED_TP); |
10651 | } else { | |
51c1a580 | 10652 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
10653 | link_config, |
10654 | bp->link_params.speed_cap_mask[idx]); | |
10655 | return; | |
10656 | } | |
10657 | break; | |
a2fbb9ea | 10658 | |
f85582f8 DK |
10659 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
10660 | if (bp->port.supported[idx] & | |
10661 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
10662 | bp->link_params.req_line_speed[idx] = |
10663 | SPEED_100; | |
10664 | bp->port.advertising[idx] |= | |
10665 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
10666 | ADVERTISED_TP); |
10667 | } else { | |
51c1a580 | 10668 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
10669 | link_config, |
10670 | bp->link_params.speed_cap_mask[idx]); | |
10671 | return; | |
10672 | } | |
10673 | break; | |
a2fbb9ea | 10674 | |
f85582f8 DK |
10675 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
10676 | if (bp->port.supported[idx] & | |
10677 | SUPPORTED_100baseT_Half) { | |
10678 | bp->link_params.req_line_speed[idx] = | |
10679 | SPEED_100; | |
10680 | bp->link_params.req_duplex[idx] = | |
10681 | DUPLEX_HALF; | |
a22f0788 YR |
10682 | bp->port.advertising[idx] |= |
10683 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
10684 | ADVERTISED_TP); |
10685 | } else { | |
51c1a580 | 10686 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
10687 | link_config, |
10688 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
10689 | return; |
10690 | } | |
10691 | break; | |
a2fbb9ea | 10692 | |
f85582f8 | 10693 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
10694 | if (bp->port.supported[idx] & |
10695 | SUPPORTED_1000baseT_Full) { | |
10696 | bp->link_params.req_line_speed[idx] = | |
10697 | SPEED_1000; | |
10698 | bp->port.advertising[idx] |= | |
10699 | (ADVERTISED_1000baseT_Full | | |
f85582f8 DK |
10700 | ADVERTISED_TP); |
10701 | } else { | |
51c1a580 | 10702 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
10703 | link_config, |
10704 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
10705 | return; |
10706 | } | |
10707 | break; | |
a2fbb9ea | 10708 | |
f85582f8 | 10709 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
10710 | if (bp->port.supported[idx] & |
10711 | SUPPORTED_2500baseX_Full) { | |
10712 | bp->link_params.req_line_speed[idx] = | |
10713 | SPEED_2500; | |
10714 | bp->port.advertising[idx] |= | |
10715 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 10716 | ADVERTISED_TP); |
f85582f8 | 10717 | } else { |
51c1a580 | 10718 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 10719 | link_config, |
f85582f8 DK |
10720 | bp->link_params.speed_cap_mask[idx]); |
10721 | return; | |
10722 | } | |
10723 | break; | |
a2fbb9ea | 10724 | |
f85582f8 | 10725 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
10726 | if (bp->port.supported[idx] & |
10727 | SUPPORTED_10000baseT_Full) { | |
10728 | bp->link_params.req_line_speed[idx] = | |
10729 | SPEED_10000; | |
10730 | bp->port.advertising[idx] |= | |
10731 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 10732 | ADVERTISED_FIBRE); |
f85582f8 | 10733 | } else { |
51c1a580 | 10734 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 10735 | link_config, |
f85582f8 DK |
10736 | bp->link_params.speed_cap_mask[idx]); |
10737 | return; | |
10738 | } | |
10739 | break; | |
3c9ada22 YR |
10740 | case PORT_FEATURE_LINK_SPEED_20G: |
10741 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 10742 | |
3c9ada22 | 10743 | break; |
f85582f8 | 10744 | default: |
51c1a580 | 10745 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
754a2f52 | 10746 | link_config); |
f85582f8 DK |
10747 | bp->link_params.req_line_speed[idx] = |
10748 | SPEED_AUTO_NEG; | |
10749 | bp->port.advertising[idx] = | |
10750 | bp->port.supported[idx]; | |
10751 | break; | |
10752 | } | |
a2fbb9ea | 10753 | |
a22f0788 | 10754 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 10755 | PORT_FEATURE_FLOW_CONTROL_MASK); |
cd1dfce2 YM |
10756 | if (bp->link_params.req_flow_ctrl[idx] == |
10757 | BNX2X_FLOW_CTRL_AUTO) { | |
10758 | if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) | |
10759 | bp->link_params.req_flow_ctrl[idx] = | |
10760 | BNX2X_FLOW_CTRL_NONE; | |
10761 | else | |
10762 | bnx2x_set_requested_fc(bp); | |
a22f0788 | 10763 | } |
a2fbb9ea | 10764 | |
51c1a580 | 10765 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
a22f0788 YR |
10766 | bp->link_params.req_line_speed[idx], |
10767 | bp->link_params.req_duplex[idx], | |
10768 | bp->link_params.req_flow_ctrl[idx], | |
10769 | bp->port.advertising[idx]); | |
10770 | } | |
a2fbb9ea ET |
10771 | } |
10772 | ||
0329aba1 | 10773 | static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
e665bfda | 10774 | { |
86564c3f YM |
10775 | __be16 mac_hi_be = cpu_to_be16(mac_hi); |
10776 | __be32 mac_lo_be = cpu_to_be32(mac_lo); | |
10777 | memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be)); | |
10778 | memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be)); | |
e665bfda MC |
10779 | } |
10780 | ||
0329aba1 | 10781 | static void bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 10782 | { |
34f80b04 | 10783 | int port = BP_PORT(bp); |
589abe3a | 10784 | u32 config; |
c8c60d88 | 10785 | u32 ext_phy_type, ext_phy_config, eee_mode; |
a2fbb9ea | 10786 | |
c18487ee | 10787 | bp->link_params.bp = bp; |
34f80b04 | 10788 | bp->link_params.port = port; |
c18487ee | 10789 | |
c18487ee | 10790 | bp->link_params.lane_config = |
a2fbb9ea | 10791 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 10792 | |
a22f0788 | 10793 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea | 10794 | SHMEM_RD(bp, |
b0261926 YR |
10795 | dev_info.port_hw_config[port].speed_capability_mask) & |
10796 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | |
a22f0788 YR |
10797 | bp->link_params.speed_cap_mask[1] = |
10798 | SHMEM_RD(bp, | |
b0261926 YR |
10799 | dev_info.port_hw_config[port].speed_capability_mask2) & |
10800 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | |
a22f0788 | 10801 | bp->port.link_config[0] = |
a2fbb9ea ET |
10802 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
10803 | ||
a22f0788 YR |
10804 | bp->port.link_config[1] = |
10805 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 10806 | |
a22f0788 YR |
10807 | bp->link_params.multi_phy_config = |
10808 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
10809 | /* If the device is capable of WoL, set the default state according |
10810 | * to the HW | |
10811 | */ | |
4d295db0 | 10812 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
10813 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
10814 | (config & PORT_FEATURE_WOL_ENABLED)); | |
10815 | ||
4ba7699b YM |
10816 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == |
10817 | PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) | |
10818 | bp->flags |= NO_ISCSI_FLAG; | |
10819 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == | |
10820 | PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) | |
10821 | bp->flags |= NO_FCOE_FLAG; | |
10822 | ||
51c1a580 | 10823 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 10824 | bp->link_params.lane_config, |
a22f0788 YR |
10825 | bp->link_params.speed_cap_mask[0], |
10826 | bp->port.link_config[0]); | |
a2fbb9ea | 10827 | |
a22f0788 | 10828 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 10829 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 10830 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 10831 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
10832 | |
10833 | bnx2x_link_settings_requested(bp); | |
10834 | ||
01cd4528 EG |
10835 | /* |
10836 | * If connected directly, work with the internal PHY, otherwise, work | |
10837 | * with the external PHY | |
10838 | */ | |
b7737c9b YR |
10839 | ext_phy_config = |
10840 | SHMEM_RD(bp, | |
10841 | dev_info.port_hw_config[port].external_phy_config); | |
10842 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 10843 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 10844 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
10845 | |
10846 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
10847 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
10848 | bp->mdio.prtad = | |
b7737c9b | 10849 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d | 10850 | |
c8c60d88 YM |
10851 | /* Configure link feature according to nvram value */ |
10852 | eee_mode = (((SHMEM_RD(bp, dev_info. | |
10853 | port_feature_config[port].eee_power_mode)) & | |
10854 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
10855 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
10856 | if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { | |
10857 | bp->link_params.eee_mode = EEE_MODE_ADV_LPI | | |
10858 | EEE_MODE_ENABLE_LPI | | |
10859 | EEE_MODE_OUTPUT_TIME; | |
10860 | } else { | |
10861 | bp->link_params.eee_mode = 0; | |
10862 | } | |
0793f83f | 10863 | } |
01cd4528 | 10864 | |
b306f5ed | 10865 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 10866 | { |
9e62e912 | 10867 | u32 no_flags = NO_ISCSI_FLAG; |
bf61ee14 | 10868 | int port = BP_PORT(bp); |
2ba45142 | 10869 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 10870 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 10871 | |
55c11941 MS |
10872 | if (!CNIC_SUPPORT(bp)) { |
10873 | bp->flags |= no_flags; | |
10874 | return; | |
10875 | } | |
10876 | ||
b306f5ed | 10877 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
10878 | bp->cnic_eth_dev.max_iscsi_conn = |
10879 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
10880 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
10881 | ||
b306f5ed DK |
10882 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
10883 | bp->cnic_eth_dev.max_iscsi_conn); | |
10884 | ||
10885 | /* | |
10886 | * If maximum allowed number of connections is zero - | |
10887 | * disable the feature. | |
10888 | */ | |
10889 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9e62e912 | 10890 | bp->flags |= no_flags; |
b306f5ed DK |
10891 | } |
10892 | ||
0329aba1 | 10893 | static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) |
9e62e912 DK |
10894 | { |
10895 | /* Port info */ | |
10896 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10897 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); | |
10898 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10899 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); | |
10900 | ||
10901 | /* Node info */ | |
10902 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10903 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); | |
10904 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10905 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); | |
10906 | } | |
86800194 DK |
10907 | |
10908 | static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) | |
10909 | { | |
10910 | u8 count = 0; | |
10911 | ||
10912 | if (IS_MF(bp)) { | |
10913 | u8 fid; | |
10914 | ||
10915 | /* iterate over absolute function ids for this path: */ | |
10916 | for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { | |
10917 | if (IS_MF_SD(bp)) { | |
10918 | u32 cfg = MF_CFG_RD(bp, | |
10919 | func_mf_config[fid].config); | |
10920 | ||
10921 | if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) && | |
10922 | ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) == | |
10923 | FUNC_MF_CFG_PROTOCOL_FCOE)) | |
10924 | count++; | |
10925 | } else { | |
10926 | u32 cfg = MF_CFG_RD(bp, | |
10927 | func_ext_config[fid]. | |
10928 | func_cfg); | |
10929 | ||
10930 | if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) && | |
10931 | (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)) | |
10932 | count++; | |
10933 | } | |
10934 | } | |
10935 | } else { /* SF */ | |
10936 | int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; | |
10937 | ||
10938 | for (port = 0; port < port_cnt; port++) { | |
10939 | u32 lic = SHMEM_RD(bp, | |
10940 | drv_lic_key[port].max_fcoe_conn) ^ | |
10941 | FW_ENCODE_32BIT_PATTERN; | |
10942 | if (lic) | |
10943 | count++; | |
10944 | } | |
10945 | } | |
10946 | ||
10947 | return count; | |
10948 | } | |
10949 | ||
0329aba1 | 10950 | static void bnx2x_get_fcoe_info(struct bnx2x *bp) |
b306f5ed DK |
10951 | { |
10952 | int port = BP_PORT(bp); | |
10953 | int func = BP_ABS_FUNC(bp); | |
b306f5ed DK |
10954 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
10955 | drv_lic_key[port].max_fcoe_conn); | |
86800194 | 10956 | u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); |
b306f5ed | 10957 | |
55c11941 MS |
10958 | if (!CNIC_SUPPORT(bp)) { |
10959 | bp->flags |= NO_FCOE_FLAG; | |
10960 | return; | |
10961 | } | |
10962 | ||
b306f5ed | 10963 | /* Get the number of maximum allowed FCoE connections */ |
2ba45142 VZ |
10964 | bp->cnic_eth_dev.max_fcoe_conn = |
10965 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
10966 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
10967 | ||
0eb43b4b BPG |
10968 | /* Calculate the number of maximum allowed FCoE tasks */ |
10969 | bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; | |
86800194 DK |
10970 | |
10971 | /* check if FCoE resources must be shared between different functions */ | |
10972 | if (num_fcoe_func) | |
10973 | bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; | |
0eb43b4b | 10974 | |
bf61ee14 VZ |
10975 | /* Read the WWN: */ |
10976 | if (!IS_MF(bp)) { | |
10977 | /* Port info */ | |
10978 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10979 | SHMEM_RD(bp, | |
2de67439 | 10980 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
10981 | fcoe_wwn_port_name_upper); |
10982 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10983 | SHMEM_RD(bp, | |
2de67439 | 10984 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
10985 | fcoe_wwn_port_name_lower); |
10986 | ||
10987 | /* Node info */ | |
10988 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10989 | SHMEM_RD(bp, | |
2de67439 | 10990 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
10991 | fcoe_wwn_node_name_upper); |
10992 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10993 | SHMEM_RD(bp, | |
2de67439 | 10994 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
10995 | fcoe_wwn_node_name_lower); |
10996 | } else if (!IS_MF_SD(bp)) { | |
bf61ee14 VZ |
10997 | /* |
10998 | * Read the WWN info only if the FCoE feature is enabled for | |
10999 | * this function. | |
11000 | */ | |
7b5342d9 | 11001 | if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) |
9e62e912 DK |
11002 | bnx2x_get_ext_wwn_info(bp, func); |
11003 | ||
382e513a | 11004 | } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) { |
9e62e912 | 11005 | bnx2x_get_ext_wwn_info(bp, func); |
382e513a | 11006 | } |
bf61ee14 | 11007 | |
b306f5ed | 11008 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 11009 | |
bf61ee14 VZ |
11010 | /* |
11011 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
11012 | * disable the feature. |
11013 | */ | |
2ba45142 VZ |
11014 | if (!bp->cnic_eth_dev.max_fcoe_conn) |
11015 | bp->flags |= NO_FCOE_FLAG; | |
11016 | } | |
b306f5ed | 11017 | |
0329aba1 | 11018 | static void bnx2x_get_cnic_info(struct bnx2x *bp) |
b306f5ed DK |
11019 | { |
11020 | /* | |
11021 | * iSCSI may be dynamically disabled but reading | |
11022 | * info here we will decrease memory usage by driver | |
11023 | * if the feature is disabled for good | |
11024 | */ | |
11025 | bnx2x_get_iscsi_info(bp); | |
11026 | bnx2x_get_fcoe_info(bp); | |
11027 | } | |
2ba45142 | 11028 | |
0329aba1 | 11029 | static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) |
0793f83f DK |
11030 | { |
11031 | u32 val, val2; | |
11032 | int func = BP_ABS_FUNC(bp); | |
11033 | int port = BP_PORT(bp); | |
2ba45142 VZ |
11034 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; |
11035 | u8 *fip_mac = bp->fip_mac; | |
0793f83f | 11036 | |
55c11941 MS |
11037 | if (IS_MF(bp)) { |
11038 | /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or | |
2ba45142 | 11039 | * FCoE MAC then the appropriate feature should be disabled. |
55c11941 MS |
11040 | * In non SD mode features configuration comes from struct |
11041 | * func_ext_config. | |
2ba45142 | 11042 | */ |
55c11941 | 11043 | if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) { |
0793f83f DK |
11044 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
11045 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
11046 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 11047 | iscsi_mac_addr_upper); |
0793f83f | 11048 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 11049 | iscsi_mac_addr_lower); |
2ba45142 | 11050 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
55c11941 MS |
11051 | BNX2X_DEV_INFO |
11052 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
11053 | } else { | |
2ba45142 | 11054 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
55c11941 | 11055 | } |
2ba45142 VZ |
11056 | |
11057 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
11058 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 11059 | fcoe_mac_addr_upper); |
2ba45142 | 11060 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 11061 | fcoe_mac_addr_lower); |
2ba45142 | 11062 | bnx2x_set_mac_buf(fip_mac, val, val2); |
55c11941 MS |
11063 | BNX2X_DEV_INFO |
11064 | ("Read FCoE L2 MAC: %pM\n", fip_mac); | |
11065 | } else { | |
2ba45142 | 11066 | bp->flags |= NO_FCOE_FLAG; |
55c11941 | 11067 | } |
a3348722 BW |
11068 | |
11069 | bp->mf_ext_config = cfg; | |
11070 | ||
9e62e912 | 11071 | } else { /* SD MODE */ |
55c11941 MS |
11072 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { |
11073 | /* use primary mac as iscsi mac */ | |
11074 | memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); | |
11075 | ||
11076 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); | |
11077 | BNX2X_DEV_INFO | |
11078 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
11079 | } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { | |
11080 | /* use primary mac as fip mac */ | |
11081 | memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); | |
11082 | BNX2X_DEV_INFO("SD FCoE MODE\n"); | |
11083 | BNX2X_DEV_INFO | |
11084 | ("Read FIP MAC: %pM\n", fip_mac); | |
614c76df | 11085 | } |
0793f83f | 11086 | } |
a3348722 | 11087 | |
82594f8f YM |
11088 | /* If this is a storage-only interface, use SAN mac as |
11089 | * primary MAC. Notice that for SD this is already the case, | |
11090 | * as the SAN mac was copied from the primary MAC. | |
11091 | */ | |
11092 | if (IS_MF_FCOE_AFEX(bp)) | |
a3348722 | 11093 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); |
0793f83f | 11094 | } else { |
0793f83f | 11095 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11096 | iscsi_mac_upper); |
0793f83f | 11097 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11098 | iscsi_mac_lower); |
2ba45142 | 11099 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
11100 | |
11101 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
55c11941 | 11102 | fcoe_fip_mac_upper); |
c03bd39c | 11103 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11104 | fcoe_fip_mac_lower); |
c03bd39c | 11105 | bnx2x_set_mac_buf(fip_mac, val, val2); |
0793f83f DK |
11106 | } |
11107 | ||
55c11941 | 11108 | /* Disable iSCSI OOO if MAC configuration is invalid. */ |
426b9241 | 11109 | if (!is_valid_ether_addr(iscsi_mac)) { |
55c11941 | 11110 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
426b9241 DK |
11111 | memset(iscsi_mac, 0, ETH_ALEN); |
11112 | } | |
11113 | ||
55c11941 | 11114 | /* Disable FCoE if MAC configuration is invalid. */ |
426b9241 DK |
11115 | if (!is_valid_ether_addr(fip_mac)) { |
11116 | bp->flags |= NO_FCOE_FLAG; | |
11117 | memset(bp->fip_mac, 0, ETH_ALEN); | |
11118 | } | |
55c11941 MS |
11119 | } |
11120 | ||
0329aba1 | 11121 | static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
55c11941 MS |
11122 | { |
11123 | u32 val, val2; | |
11124 | int func = BP_ABS_FUNC(bp); | |
11125 | int port = BP_PORT(bp); | |
11126 | ||
11127 | /* Zero primary MAC configuration */ | |
11128 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
11129 | ||
11130 | if (BP_NOMCP(bp)) { | |
11131 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
11132 | eth_hw_addr_random(bp->dev); | |
11133 | } else if (IS_MF(bp)) { | |
11134 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
11135 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
11136 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
11137 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
11138 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
11139 | ||
11140 | if (CNIC_SUPPORT(bp)) | |
11141 | bnx2x_get_cnic_mac_hwinfo(bp); | |
11142 | } else { | |
11143 | /* in SF read MACs from port configuration */ | |
11144 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
11145 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
11146 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
11147 | ||
11148 | if (CNIC_SUPPORT(bp)) | |
11149 | bnx2x_get_cnic_mac_hwinfo(bp); | |
11150 | } | |
11151 | ||
11152 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); | |
619c5cb6 | 11153 | |
614c76df | 11154 | if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) |
619c5cb6 | 11155 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11156 | "bad Ethernet MAC address configuration: %pM\n" |
11157 | "change it manually before bringing up the appropriate network interface\n", | |
0f9dad10 | 11158 | bp->dev->dev_addr); |
7964211d | 11159 | } |
51c1a580 | 11160 | |
0329aba1 | 11161 | static bool bnx2x_get_dropless_info(struct bnx2x *bp) |
7964211d YM |
11162 | { |
11163 | int tmp; | |
11164 | u32 cfg; | |
51c1a580 | 11165 | |
7964211d YM |
11166 | if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { |
11167 | /* Take function: tmp = func */ | |
11168 | tmp = BP_ABS_FUNC(bp); | |
11169 | cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); | |
11170 | cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); | |
11171 | } else { | |
11172 | /* Take port: tmp = port */ | |
11173 | tmp = BP_PORT(bp); | |
11174 | cfg = SHMEM_RD(bp, | |
11175 | dev_info.port_hw_config[tmp].generic_features); | |
11176 | cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); | |
11177 | } | |
11178 | return cfg; | |
34f80b04 EG |
11179 | } |
11180 | ||
0329aba1 | 11181 | static int bnx2x_get_hwinfo(struct bnx2x *bp) |
34f80b04 | 11182 | { |
0793f83f | 11183 | int /*abs*/func = BP_ABS_FUNC(bp); |
b8ee8328 | 11184 | int vn; |
0793f83f | 11185 | u32 val = 0; |
34f80b04 | 11186 | int rc = 0; |
a2fbb9ea | 11187 | |
34f80b04 | 11188 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 11189 | |
6383c0b3 AE |
11190 | /* |
11191 | * initialize IGU parameters | |
11192 | */ | |
f2e0899f DK |
11193 | if (CHIP_IS_E1x(bp)) { |
11194 | bp->common.int_block = INT_BLOCK_HC; | |
11195 | ||
11196 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
11197 | bp->igu_base_sb = 0; | |
f2e0899f DK |
11198 | } else { |
11199 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 | 11200 | |
16a5fd92 | 11201 | /* do not allow device reset during IGU info processing */ |
7a06a122 DK |
11202 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
11203 | ||
f2e0899f | 11204 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
11205 | |
11206 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
11207 | int tout = 5000; | |
11208 | ||
11209 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
11210 | ||
11211 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
11212 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
11213 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
11214 | ||
11215 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
11216 | tout--; | |
0926d499 | 11217 | usleep_range(1000, 2000); |
619c5cb6 VZ |
11218 | } |
11219 | ||
11220 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
11221 | dev_err(&bp->pdev->dev, | |
11222 | "FORCING Normal Mode failed!!!\n"); | |
9b341bb1 BW |
11223 | bnx2x_release_hw_lock(bp, |
11224 | HW_LOCK_RESOURCE_RESET); | |
619c5cb6 VZ |
11225 | return -EPERM; |
11226 | } | |
11227 | } | |
11228 | ||
f2e0899f | 11229 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 11230 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
11231 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
11232 | } else | |
619c5cb6 | 11233 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 11234 | |
9b341bb1 | 11235 | rc = bnx2x_get_igu_cam_info(bp); |
7a06a122 | 11236 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
9b341bb1 BW |
11237 | if (rc) |
11238 | return rc; | |
f2e0899f | 11239 | } |
619c5cb6 VZ |
11240 | |
11241 | /* | |
11242 | * set base FW non-default (fast path) status block id, this value is | |
11243 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
11244 | * determine the id used by the FW. | |
11245 | */ | |
11246 | if (CHIP_IS_E1x(bp)) | |
11247 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
11248 | else /* | |
11249 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
11250 | * the same queue are indicated on the same IGU SB). So we prefer | |
11251 | * FW and IGU SBs to be the same value. | |
11252 | */ | |
11253 | bp->base_fw_ndsb = bp->igu_base_sb; | |
11254 | ||
11255 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
11256 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
11257 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
11258 | |
11259 | /* | |
11260 | * Initialize MF configuration | |
11261 | */ | |
523224a3 | 11262 | |
fb3bff17 DK |
11263 | bp->mf_ov = 0; |
11264 | bp->mf_mode = 0; | |
3395a033 | 11265 | vn = BP_VN(bp); |
0793f83f | 11266 | |
f2e0899f | 11267 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
11268 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
11269 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
11270 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
11271 | ||
f2e0899f DK |
11272 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
11273 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
11274 | else | |
11275 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
11276 | offsetof(struct shmem_region, func_mb) + |
11277 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
11278 | /* |
11279 | * get mf configuration: | |
16a5fd92 | 11280 | * 1. Existence of MF configuration |
0793f83f DK |
11281 | * 2. MAC address must be legal (check only upper bytes) |
11282 | * for Switch-Independent mode; | |
11283 | * OVLAN must be legal for Switch-Dependent mode | |
11284 | * 3. SF_MODE configures specific MF mode | |
11285 | */ | |
11286 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
11287 | /* get mf configuration */ | |
11288 | val = SHMEM_RD(bp, | |
11289 | dev_info.shared_feature_config.config); | |
11290 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
11291 | ||
11292 | switch (val) { | |
11293 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
11294 | val = MF_CFG_RD(bp, func_mf_config[func]. | |
11295 | mac_upper); | |
11296 | /* check for legal mac (upper bytes)*/ | |
11297 | if (val != 0xffff) { | |
11298 | bp->mf_mode = MULTI_FUNCTION_SI; | |
11299 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
11300 | func_mf_config[func].config); | |
11301 | } else | |
51c1a580 | 11302 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); |
0793f83f | 11303 | break; |
a3348722 BW |
11304 | case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: |
11305 | if ((!CHIP_IS_E1x(bp)) && | |
11306 | (MF_CFG_RD(bp, func_mf_config[func]. | |
11307 | mac_upper) != 0xffff) && | |
11308 | (SHMEM2_HAS(bp, | |
11309 | afex_driver_support))) { | |
11310 | bp->mf_mode = MULTI_FUNCTION_AFEX; | |
11311 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
11312 | func_mf_config[func].config); | |
11313 | } else { | |
11314 | BNX2X_DEV_INFO("can not configure afex mode\n"); | |
11315 | } | |
11316 | break; | |
0793f83f DK |
11317 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: |
11318 | /* get OV configuration */ | |
11319 | val = MF_CFG_RD(bp, | |
11320 | func_mf_config[FUNC_0].e1hov_tag); | |
11321 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
11322 | ||
11323 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
11324 | bp->mf_mode = MULTI_FUNCTION_SD; | |
11325 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
11326 | func_mf_config[func].config); | |
11327 | } else | |
754a2f52 | 11328 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f | 11329 | break; |
3786b942 AE |
11330 | case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: |
11331 | bp->mf_config[vn] = 0; | |
11332 | break; | |
0793f83f DK |
11333 | default: |
11334 | /* Unknown configuration: reset mf_config */ | |
11335 | bp->mf_config[vn] = 0; | |
51c1a580 | 11336 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
0793f83f DK |
11337 | } |
11338 | } | |
a2fbb9ea | 11339 | |
2691d51d | 11340 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 11341 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 11342 | |
0793f83f DK |
11343 | switch (bp->mf_mode) { |
11344 | case MULTI_FUNCTION_SD: | |
11345 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
11346 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 11347 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 11348 | bp->mf_ov = val; |
619c5cb6 VZ |
11349 | bp->path_has_ovlan = true; |
11350 | ||
51c1a580 MS |
11351 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
11352 | func, bp->mf_ov, bp->mf_ov); | |
2691d51d | 11353 | } else { |
619c5cb6 | 11354 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11355 | "No valid MF OV for func %d, aborting\n", |
11356 | func); | |
619c5cb6 | 11357 | return -EPERM; |
34f80b04 | 11358 | } |
0793f83f | 11359 | break; |
a3348722 BW |
11360 | case MULTI_FUNCTION_AFEX: |
11361 | BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); | |
11362 | break; | |
0793f83f | 11363 | case MULTI_FUNCTION_SI: |
51c1a580 MS |
11364 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
11365 | func); | |
0793f83f DK |
11366 | break; |
11367 | default: | |
11368 | if (vn) { | |
619c5cb6 | 11369 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11370 | "VN %d is in a single function mode, aborting\n", |
11371 | vn); | |
619c5cb6 | 11372 | return -EPERM; |
2691d51d | 11373 | } |
0793f83f | 11374 | break; |
34f80b04 | 11375 | } |
0793f83f | 11376 | |
619c5cb6 VZ |
11377 | /* check if other port on the path needs ovlan: |
11378 | * Since MF configuration is shared between ports | |
11379 | * Possible mixed modes are only | |
11380 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
11381 | */ | |
11382 | if (CHIP_MODE_IS_4_PORT(bp) && | |
11383 | !bp->path_has_ovlan && | |
11384 | !IS_MF(bp) && | |
11385 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
11386 | u8 other_port = !BP_PORT(bp); | |
11387 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
11388 | val = MF_CFG_RD(bp, | |
11389 | func_mf_config[other_func].e1hov_tag); | |
11390 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
11391 | bp->path_has_ovlan = true; | |
11392 | } | |
34f80b04 | 11393 | } |
a2fbb9ea | 11394 | |
f2e0899f DK |
11395 | /* adjust igu_sb_cnt to MF for E1x */ |
11396 | if (CHIP_IS_E1x(bp) && IS_MF(bp)) | |
523224a3 DK |
11397 | bp->igu_sb_cnt /= E1HVN_MAX; |
11398 | ||
619c5cb6 VZ |
11399 | /* port info */ |
11400 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 11401 | |
0793f83f DK |
11402 | /* Get MAC addresses */ |
11403 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 11404 | |
2ba45142 | 11405 | bnx2x_get_cnic_info(bp); |
2ba45142 | 11406 | |
34f80b04 EG |
11407 | return rc; |
11408 | } | |
11409 | ||
0329aba1 | 11410 | static void bnx2x_read_fwinfo(struct bnx2x *bp) |
34f24c7f VZ |
11411 | { |
11412 | int cnt, i, block_end, rodi; | |
fcdf95cb | 11413 | char vpd_start[BNX2X_VPD_LEN+1]; |
34f24c7f VZ |
11414 | char str_id_reg[VENDOR_ID_LEN+1]; |
11415 | char str_id_cap[VENDOR_ID_LEN+1]; | |
fcdf95cb BW |
11416 | char *vpd_data; |
11417 | char *vpd_extended_data = NULL; | |
34f24c7f VZ |
11418 | u8 len; |
11419 | ||
fcdf95cb | 11420 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); |
34f24c7f VZ |
11421 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
11422 | ||
11423 | if (cnt < BNX2X_VPD_LEN) | |
11424 | goto out_not_found; | |
11425 | ||
fcdf95cb BW |
11426 | /* VPD RO tag should be first tag after identifier string, hence |
11427 | * we should be able to find it in first BNX2X_VPD_LEN chars | |
11428 | */ | |
11429 | i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, | |
34f24c7f VZ |
11430 | PCI_VPD_LRDT_RO_DATA); |
11431 | if (i < 0) | |
11432 | goto out_not_found; | |
11433 | ||
34f24c7f | 11434 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + |
fcdf95cb | 11435 | pci_vpd_lrdt_size(&vpd_start[i]); |
34f24c7f VZ |
11436 | |
11437 | i += PCI_VPD_LRDT_TAG_SIZE; | |
11438 | ||
fcdf95cb BW |
11439 | if (block_end > BNX2X_VPD_LEN) { |
11440 | vpd_extended_data = kmalloc(block_end, GFP_KERNEL); | |
11441 | if (vpd_extended_data == NULL) | |
11442 | goto out_not_found; | |
11443 | ||
11444 | /* read rest of vpd image into vpd_extended_data */ | |
11445 | memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); | |
11446 | cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, | |
11447 | block_end - BNX2X_VPD_LEN, | |
11448 | vpd_extended_data + BNX2X_VPD_LEN); | |
11449 | if (cnt < (block_end - BNX2X_VPD_LEN)) | |
11450 | goto out_not_found; | |
11451 | vpd_data = vpd_extended_data; | |
11452 | } else | |
11453 | vpd_data = vpd_start; | |
11454 | ||
11455 | /* now vpd_data holds full vpd content in both cases */ | |
34f24c7f VZ |
11456 | |
11457 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
11458 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
11459 | if (rodi < 0) | |
11460 | goto out_not_found; | |
11461 | ||
11462 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
11463 | ||
11464 | if (len != VENDOR_ID_LEN) | |
11465 | goto out_not_found; | |
11466 | ||
11467 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11468 | ||
11469 | /* vendor specific info */ | |
11470 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
11471 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
11472 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
11473 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
11474 | ||
11475 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
11476 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
11477 | if (rodi >= 0) { | |
11478 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
11479 | ||
11480 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11481 | ||
11482 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
11483 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
11484 | bp->fw_ver[len] = ' '; | |
11485 | } | |
11486 | } | |
fcdf95cb | 11487 | kfree(vpd_extended_data); |
34f24c7f VZ |
11488 | return; |
11489 | } | |
11490 | out_not_found: | |
fcdf95cb | 11491 | kfree(vpd_extended_data); |
34f24c7f VZ |
11492 | return; |
11493 | } | |
11494 | ||
0329aba1 | 11495 | static void bnx2x_set_modes_bitmap(struct bnx2x *bp) |
619c5cb6 VZ |
11496 | { |
11497 | u32 flags = 0; | |
11498 | ||
11499 | if (CHIP_REV_IS_FPGA(bp)) | |
11500 | SET_FLAGS(flags, MODE_FPGA); | |
11501 | else if (CHIP_REV_IS_EMUL(bp)) | |
11502 | SET_FLAGS(flags, MODE_EMUL); | |
11503 | else | |
11504 | SET_FLAGS(flags, MODE_ASIC); | |
11505 | ||
11506 | if (CHIP_MODE_IS_4_PORT(bp)) | |
11507 | SET_FLAGS(flags, MODE_PORT4); | |
11508 | else | |
11509 | SET_FLAGS(flags, MODE_PORT2); | |
11510 | ||
11511 | if (CHIP_IS_E2(bp)) | |
11512 | SET_FLAGS(flags, MODE_E2); | |
11513 | else if (CHIP_IS_E3(bp)) { | |
11514 | SET_FLAGS(flags, MODE_E3); | |
11515 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
11516 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
11517 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
11518 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
11519 | } |
11520 | ||
11521 | if (IS_MF(bp)) { | |
11522 | SET_FLAGS(flags, MODE_MF); | |
11523 | switch (bp->mf_mode) { | |
11524 | case MULTI_FUNCTION_SD: | |
11525 | SET_FLAGS(flags, MODE_MF_SD); | |
11526 | break; | |
11527 | case MULTI_FUNCTION_SI: | |
11528 | SET_FLAGS(flags, MODE_MF_SI); | |
11529 | break; | |
a3348722 BW |
11530 | case MULTI_FUNCTION_AFEX: |
11531 | SET_FLAGS(flags, MODE_MF_AFEX); | |
11532 | break; | |
619c5cb6 VZ |
11533 | } |
11534 | } else | |
11535 | SET_FLAGS(flags, MODE_SF); | |
11536 | ||
11537 | #if defined(__LITTLE_ENDIAN) | |
11538 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
11539 | #else /*(__BIG_ENDIAN)*/ | |
11540 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
11541 | #endif | |
11542 | INIT_MODE_FLAGS(bp) = flags; | |
11543 | } | |
11544 | ||
0329aba1 | 11545 | static int bnx2x_init_bp(struct bnx2x *bp) |
34f80b04 | 11546 | { |
f2e0899f | 11547 | int func; |
34f80b04 EG |
11548 | int rc; |
11549 | ||
34f80b04 | 11550 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 11551 | mutex_init(&bp->fw_mb_mutex); |
bb7e95c8 | 11552 | spin_lock_init(&bp->stats_lock); |
507393eb | 11553 | sema_init(&bp->stats_sema, 1); |
55c11941 | 11554 | |
1cf167f2 | 11555 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 11556 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 11557 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
1ab4434c AE |
11558 | if (IS_PF(bp)) { |
11559 | rc = bnx2x_get_hwinfo(bp); | |
11560 | if (rc) | |
11561 | return rc; | |
11562 | } else { | |
e09b74d0 | 11563 | eth_zero_addr(bp->dev->dev_addr); |
1ab4434c | 11564 | } |
34f80b04 | 11565 | |
619c5cb6 VZ |
11566 | bnx2x_set_modes_bitmap(bp); |
11567 | ||
11568 | rc = bnx2x_alloc_mem_bp(bp); | |
11569 | if (rc) | |
11570 | return rc; | |
523224a3 | 11571 | |
34f24c7f | 11572 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
11573 | |
11574 | func = BP_FUNC(bp); | |
11575 | ||
34f80b04 | 11576 | /* need to reset chip if undi was active */ |
1ab4434c | 11577 | if (IS_PF(bp) && !BP_NOMCP(bp)) { |
452427b0 YM |
11578 | /* init fw_seq */ |
11579 | bp->fw_seq = | |
11580 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
11581 | DRV_MSG_SEQ_NUMBER_MASK; | |
11582 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
11583 | ||
11584 | bnx2x_prev_unload(bp); | |
11585 | } | |
11586 | ||
34f80b04 | 11587 | if (CHIP_REV_IS_FPGA(bp)) |
cdaa7cb8 | 11588 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
11589 | |
11590 | if (BP_NOMCP(bp) && (func == 0)) | |
51c1a580 | 11591 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
34f80b04 | 11592 | |
614c76df | 11593 | bp->disable_tpa = disable_tpa; |
a3348722 | 11594 | bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp); |
614c76df | 11595 | |
7a9b2557 | 11596 | /* Set TPA flags */ |
614c76df | 11597 | if (bp->disable_tpa) { |
621b4d66 | 11598 | bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
11599 | bp->dev->features &= ~NETIF_F_LRO; |
11600 | } else { | |
621b4d66 | 11601 | bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
11602 | bp->dev->features |= NETIF_F_LRO; |
11603 | } | |
11604 | ||
a18f5128 EG |
11605 | if (CHIP_IS_E1(bp)) |
11606 | bp->dropless_fc = 0; | |
11607 | else | |
7964211d | 11608 | bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); |
a18f5128 | 11609 | |
8d5726c4 | 11610 | bp->mrrs = mrrs; |
7a9b2557 | 11611 | |
a3348722 | 11612 | bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; |
1ab4434c AE |
11613 | if (IS_VF(bp)) |
11614 | bp->rx_ring_size = MAX_RX_AVAIL; | |
34f80b04 | 11615 | |
7d323bfd | 11616 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
11617 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
11618 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 11619 | |
fc543637 | 11620 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
34f80b04 EG |
11621 | |
11622 | init_timer(&bp->timer); | |
11623 | bp->timer.expires = jiffies + bp->current_interval; | |
11624 | bp->timer.data = (unsigned long) bp; | |
11625 | bp->timer.function = bnx2x_timer; | |
11626 | ||
0370cf90 BW |
11627 | if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && |
11628 | SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && | |
11629 | SHMEM2_RD(bp, dcbx_lldp_params_offset) && | |
11630 | SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) { | |
11631 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); | |
11632 | bnx2x_dcbx_init_params(bp); | |
11633 | } else { | |
11634 | bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); | |
11635 | } | |
e4901dde | 11636 | |
619c5cb6 VZ |
11637 | if (CHIP_IS_E1x(bp)) |
11638 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
11639 | else | |
11640 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
619c5cb6 | 11641 | |
6383c0b3 | 11642 | /* multiple tx priority */ |
1ab4434c AE |
11643 | if (IS_VF(bp)) |
11644 | bp->max_cos = 1; | |
11645 | else if (CHIP_IS_E1x(bp)) | |
6383c0b3 | 11646 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; |
1ab4434c | 11647 | else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) |
6383c0b3 | 11648 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; |
1ab4434c | 11649 | else if (CHIP_IS_E3B0(bp)) |
6383c0b3 | 11650 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; |
1ab4434c AE |
11651 | else |
11652 | BNX2X_ERR("unknown chip %x revision %x\n", | |
11653 | CHIP_NUM(bp), CHIP_REV(bp)); | |
11654 | BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); | |
6383c0b3 | 11655 | |
55c11941 MS |
11656 | /* We need at least one default status block for slow-path events, |
11657 | * second status block for the L2 queue, and a third status block for | |
16a5fd92 | 11658 | * CNIC if supported. |
55c11941 MS |
11659 | */ |
11660 | if (CNIC_SUPPORT(bp)) | |
11661 | bp->min_msix_vec_cnt = 3; | |
11662 | else | |
11663 | bp->min_msix_vec_cnt = 2; | |
11664 | BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); | |
11665 | ||
5bb680d6 MS |
11666 | bp->dump_preset_idx = 1; |
11667 | ||
34f80b04 | 11668 | return rc; |
a2fbb9ea ET |
11669 | } |
11670 | ||
de0c62db DK |
11671 | /**************************************************************************** |
11672 | * General service functions | |
11673 | ****************************************************************************/ | |
a2fbb9ea | 11674 | |
619c5cb6 VZ |
11675 | /* |
11676 | * net_device service functions | |
11677 | */ | |
11678 | ||
bb2a0f7a | 11679 | /* called with rtnl_lock */ |
a2fbb9ea ET |
11680 | static int bnx2x_open(struct net_device *dev) |
11681 | { | |
11682 | struct bnx2x *bp = netdev_priv(dev); | |
c9ee9206 VZ |
11683 | bool global = false; |
11684 | int other_engine = BP_PATH(bp) ? 0 : 1; | |
889b9af3 | 11685 | bool other_load_status, load_status; |
8395be5e | 11686 | int rc; |
a2fbb9ea | 11687 | |
1355b704 MY |
11688 | bp->stats_init = true; |
11689 | ||
6eccabb3 EG |
11690 | netif_carrier_off(dev); |
11691 | ||
a2fbb9ea ET |
11692 | bnx2x_set_power_state(bp, PCI_D0); |
11693 | ||
ad5afc89 | 11694 | /* If parity had happen during the unload, then attentions |
c9ee9206 VZ |
11695 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we |
11696 | * want the first function loaded on the current engine to | |
11697 | * complete the recovery. | |
ad5afc89 | 11698 | * Parity recovery is only relevant for PF driver. |
c9ee9206 | 11699 | */ |
ad5afc89 AE |
11700 | if (IS_PF(bp)) { |
11701 | other_load_status = bnx2x_get_load_status(bp, other_engine); | |
11702 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); | |
11703 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
11704 | bnx2x_chk_parity_attn(bp, &global, true)) { | |
11705 | do { | |
11706 | /* If there are attentions and they are in a | |
11707 | * global blocks, set the GLOBAL_RESET bit | |
11708 | * regardless whether it will be this function | |
11709 | * that will complete the recovery or not. | |
11710 | */ | |
11711 | if (global) | |
11712 | bnx2x_set_reset_global(bp); | |
72fd0718 | 11713 | |
ad5afc89 AE |
11714 | /* Only the first function on the current |
11715 | * engine should try to recover in open. In case | |
11716 | * of attentions in global blocks only the first | |
11717 | * in the chip should try to recover. | |
11718 | */ | |
11719 | if ((!load_status && | |
11720 | (!global || !other_load_status)) && | |
11721 | bnx2x_trylock_leader_lock(bp) && | |
11722 | !bnx2x_leader_reset(bp)) { | |
11723 | netdev_info(bp->dev, | |
11724 | "Recovered in open\n"); | |
11725 | break; | |
11726 | } | |
72fd0718 | 11727 | |
ad5afc89 AE |
11728 | /* recovery has failed... */ |
11729 | bnx2x_set_power_state(bp, PCI_D3hot); | |
11730 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
72fd0718 | 11731 | |
ad5afc89 AE |
11732 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
11733 | "If you still see this message after a few retries then power cycle is required.\n"); | |
72fd0718 | 11734 | |
ad5afc89 AE |
11735 | return -EAGAIN; |
11736 | } while (0); | |
11737 | } | |
11738 | } | |
72fd0718 VZ |
11739 | |
11740 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
8395be5e AE |
11741 | rc = bnx2x_nic_load(bp, LOAD_OPEN); |
11742 | if (rc) | |
11743 | return rc; | |
11744 | return bnx2x_open_epilog(bp); | |
a2fbb9ea ET |
11745 | } |
11746 | ||
bb2a0f7a | 11747 | /* called with rtnl_lock */ |
56ad3152 | 11748 | static int bnx2x_close(struct net_device *dev) |
a2fbb9ea | 11749 | { |
a2fbb9ea ET |
11750 | struct bnx2x *bp = netdev_priv(dev); |
11751 | ||
11752 | /* Unload the driver, release IRQs */ | |
5d07d868 | 11753 | bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); |
c9ee9206 | 11754 | |
a2fbb9ea ET |
11755 | return 0; |
11756 | } | |
11757 | ||
1191cb83 ED |
11758 | static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
11759 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 11760 | { |
619c5cb6 VZ |
11761 | int mc_count = netdev_mc_count(bp->dev); |
11762 | struct bnx2x_mcast_list_elem *mc_mac = | |
11763 | kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); | |
11764 | struct netdev_hw_addr *ha; | |
6e30dd4e | 11765 | |
619c5cb6 VZ |
11766 | if (!mc_mac) |
11767 | return -ENOMEM; | |
6e30dd4e | 11768 | |
619c5cb6 | 11769 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 11770 | |
619c5cb6 VZ |
11771 | netdev_for_each_mc_addr(ha, bp->dev) { |
11772 | mc_mac->mac = bnx2x_mc_addr(ha); | |
11773 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
11774 | mc_mac++; | |
6e30dd4e | 11775 | } |
619c5cb6 VZ |
11776 | |
11777 | p->mcast_list_len = mc_count; | |
11778 | ||
11779 | return 0; | |
6e30dd4e VZ |
11780 | } |
11781 | ||
1191cb83 | 11782 | static void bnx2x_free_mcast_macs_list( |
619c5cb6 VZ |
11783 | struct bnx2x_mcast_ramrod_params *p) |
11784 | { | |
11785 | struct bnx2x_mcast_list_elem *mc_mac = | |
11786 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
11787 | link); | |
11788 | ||
11789 | WARN_ON(!mc_mac); | |
11790 | kfree(mc_mac); | |
11791 | } | |
11792 | ||
11793 | /** | |
11794 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
11795 | * | |
11796 | * @bp: driver handle | |
6e30dd4e | 11797 | * |
619c5cb6 | 11798 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 11799 | */ |
1191cb83 | 11800 | static int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 11801 | { |
619c5cb6 | 11802 | int rc; |
6e30dd4e | 11803 | struct net_device *dev = bp->dev; |
6e30dd4e | 11804 | struct netdev_hw_addr *ha; |
15192a8c | 11805 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; |
619c5cb6 | 11806 | unsigned long ramrod_flags = 0; |
6e30dd4e | 11807 | |
619c5cb6 VZ |
11808 | /* First schedule a cleanup up of old configuration */ |
11809 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
11810 | if (rc < 0) { | |
11811 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
11812 | return rc; | |
11813 | } | |
6e30dd4e VZ |
11814 | |
11815 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
11816 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
11817 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
7b5342d9 YM |
11818 | if (rc == -EEXIST) { |
11819 | DP(BNX2X_MSG_SP, | |
11820 | "Failed to schedule ADD operations: %d\n", rc); | |
11821 | /* do not treat adding same MAC as error */ | |
11822 | rc = 0; | |
11823 | ||
11824 | } else if (rc < 0) { | |
11825 | ||
619c5cb6 VZ |
11826 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", |
11827 | rc); | |
11828 | return rc; | |
6e30dd4e VZ |
11829 | } |
11830 | } | |
11831 | ||
619c5cb6 VZ |
11832 | /* Execute the pending commands */ |
11833 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
11834 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
11835 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
11836 | } |
11837 | ||
1191cb83 | 11838 | static int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 11839 | { |
619c5cb6 | 11840 | struct net_device *dev = bp->dev; |
3b603066 | 11841 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 | 11842 | int rc = 0; |
6e30dd4e | 11843 | |
619c5cb6 | 11844 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 11845 | |
619c5cb6 VZ |
11846 | /* first, clear all configured multicast MACs */ |
11847 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
11848 | if (rc < 0) { | |
51c1a580 | 11849 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
619c5cb6 VZ |
11850 | return rc; |
11851 | } | |
6e30dd4e | 11852 | |
619c5cb6 VZ |
11853 | /* then, configure a new MACs list */ |
11854 | if (netdev_mc_count(dev)) { | |
11855 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
11856 | if (rc) { | |
51c1a580 MS |
11857 | BNX2X_ERR("Failed to create multicast MACs list: %d\n", |
11858 | rc); | |
619c5cb6 VZ |
11859 | return rc; |
11860 | } | |
6e30dd4e | 11861 | |
619c5cb6 VZ |
11862 | /* Now add the new MACs */ |
11863 | rc = bnx2x_config_mcast(bp, &rparam, | |
11864 | BNX2X_MCAST_CMD_ADD); | |
11865 | if (rc < 0) | |
51c1a580 MS |
11866 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
11867 | rc); | |
6e30dd4e | 11868 | |
619c5cb6 VZ |
11869 | bnx2x_free_mcast_macs_list(&rparam); |
11870 | } | |
6e30dd4e | 11871 | |
619c5cb6 | 11872 | return rc; |
6e30dd4e VZ |
11873 | } |
11874 | ||
619c5cb6 | 11875 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
9f6c9258 | 11876 | void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
11877 | { |
11878 | struct bnx2x *bp = netdev_priv(dev); | |
11879 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 EG |
11880 | |
11881 | if (bp->state != BNX2X_STATE_OPEN) { | |
11882 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
11883 | return; | |
11884 | } | |
11885 | ||
619c5cb6 | 11886 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 EG |
11887 | |
11888 | if (dev->flags & IFF_PROMISC) | |
11889 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
619c5cb6 VZ |
11890 | else if ((dev->flags & IFF_ALLMULTI) || |
11891 | ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && | |
11892 | CHIP_IS_E1(bp))) | |
34f80b04 | 11893 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
6e30dd4e | 11894 | else { |
381ac16b AE |
11895 | if (IS_PF(bp)) { |
11896 | /* some multicasts */ | |
11897 | if (bnx2x_set_mc_list(bp) < 0) | |
11898 | rx_mode = BNX2X_RX_MODE_ALLMULTI; | |
34f80b04 | 11899 | |
381ac16b AE |
11900 | if (bnx2x_set_uc_list(bp) < 0) |
11901 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
11902 | } else { | |
11903 | /* configuring mcast to a vf involves sleeping (when we | |
11904 | * wait for the pf's response). Since this function is | |
11905 | * called from non sleepable context we must schedule | |
11906 | * a work item for this purpose | |
11907 | */ | |
11908 | smp_mb__before_clear_bit(); | |
11909 | set_bit(BNX2X_SP_RTNL_VFPF_MCAST, | |
11910 | &bp->sp_rtnl_state); | |
11911 | smp_mb__after_clear_bit(); | |
11912 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
11913 | } | |
34f80b04 EG |
11914 | } |
11915 | ||
11916 | bp->rx_mode = rx_mode; | |
614c76df DK |
11917 | /* handle ISCSI SD mode */ |
11918 | if (IS_MF_ISCSI_SD(bp)) | |
11919 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
619c5cb6 VZ |
11920 | |
11921 | /* Schedule the rx_mode command */ | |
11922 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
11923 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
11924 | return; | |
11925 | } | |
11926 | ||
381ac16b AE |
11927 | if (IS_PF(bp)) { |
11928 | bnx2x_set_storm_rx_mode(bp); | |
11929 | } else { | |
11930 | /* configuring rx mode to storms in a vf involves sleeping (when | |
11931 | * we wait for the pf's response). Since this function is | |
11932 | * called from non sleepable context we must schedule | |
11933 | * a work item for this purpose | |
11934 | */ | |
11935 | smp_mb__before_clear_bit(); | |
11936 | set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, | |
11937 | &bp->sp_rtnl_state); | |
11938 | smp_mb__after_clear_bit(); | |
11939 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
11940 | } | |
34f80b04 EG |
11941 | } |
11942 | ||
c18487ee | 11943 | /* called with rtnl_lock */ |
01cd4528 EG |
11944 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
11945 | int devad, u16 addr) | |
a2fbb9ea | 11946 | { |
01cd4528 EG |
11947 | struct bnx2x *bp = netdev_priv(netdev); |
11948 | u16 value; | |
11949 | int rc; | |
a2fbb9ea | 11950 | |
01cd4528 EG |
11951 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
11952 | prtad, devad, addr); | |
a2fbb9ea | 11953 | |
01cd4528 EG |
11954 | /* The HW expects different devad if CL22 is used */ |
11955 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 11956 | |
01cd4528 | 11957 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11958 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
11959 | bnx2x_release_phy_lock(bp); |
11960 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 11961 | |
01cd4528 EG |
11962 | if (!rc) |
11963 | rc = value; | |
11964 | return rc; | |
11965 | } | |
a2fbb9ea | 11966 | |
01cd4528 EG |
11967 | /* called with rtnl_lock */ |
11968 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
11969 | u16 addr, u16 value) | |
11970 | { | |
11971 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
11972 | int rc; |
11973 | ||
51c1a580 MS |
11974 | DP(NETIF_MSG_LINK, |
11975 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", | |
11976 | prtad, devad, addr, value); | |
01cd4528 | 11977 | |
01cd4528 EG |
11978 | /* The HW expects different devad if CL22 is used */ |
11979 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 11980 | |
01cd4528 | 11981 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11982 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
11983 | bnx2x_release_phy_lock(bp); |
11984 | return rc; | |
11985 | } | |
c18487ee | 11986 | |
01cd4528 EG |
11987 | /* called with rtnl_lock */ |
11988 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
11989 | { | |
11990 | struct bnx2x *bp = netdev_priv(dev); | |
11991 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 11992 | |
01cd4528 EG |
11993 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", |
11994 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
a2fbb9ea | 11995 | |
01cd4528 EG |
11996 | if (!netif_running(dev)) |
11997 | return -EAGAIN; | |
11998 | ||
11999 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
a2fbb9ea ET |
12000 | } |
12001 | ||
257ddbda | 12002 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
12003 | static void poll_bnx2x(struct net_device *dev) |
12004 | { | |
12005 | struct bnx2x *bp = netdev_priv(dev); | |
14a15d61 | 12006 | int i; |
a2fbb9ea | 12007 | |
14a15d61 MS |
12008 | for_each_eth_queue(bp, i) { |
12009 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
12010 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); | |
12011 | } | |
a2fbb9ea ET |
12012 | } |
12013 | #endif | |
12014 | ||
614c76df DK |
12015 | static int bnx2x_validate_addr(struct net_device *dev) |
12016 | { | |
12017 | struct bnx2x *bp = netdev_priv(dev); | |
12018 | ||
e09b74d0 AE |
12019 | /* query the bulletin board for mac address configured by the PF */ |
12020 | if (IS_VF(bp)) | |
12021 | bnx2x_sample_bulletin(bp); | |
12022 | ||
51c1a580 MS |
12023 | if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { |
12024 | BNX2X_ERR("Non-valid Ethernet address\n"); | |
614c76df | 12025 | return -EADDRNOTAVAIL; |
51c1a580 | 12026 | } |
614c76df DK |
12027 | return 0; |
12028 | } | |
12029 | ||
c64213cd SH |
12030 | static const struct net_device_ops bnx2x_netdev_ops = { |
12031 | .ndo_open = bnx2x_open, | |
12032 | .ndo_stop = bnx2x_close, | |
12033 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 12034 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 12035 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd | 12036 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
614c76df | 12037 | .ndo_validate_addr = bnx2x_validate_addr, |
c64213cd SH |
12038 | .ndo_do_ioctl = bnx2x_ioctl, |
12039 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
12040 | .ndo_fix_features = bnx2x_fix_features, |
12041 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 12042 | .ndo_tx_timeout = bnx2x_tx_timeout, |
257ddbda | 12043 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
12044 | .ndo_poll_controller = poll_bnx2x, |
12045 | #endif | |
6383c0b3 | 12046 | .ndo_setup_tc = bnx2x_setup_tc, |
6411280a | 12047 | #ifdef CONFIG_BNX2X_SRIOV |
abc5a021 | 12048 | .ndo_set_vf_mac = bnx2x_set_vf_mac, |
3cdeec22 | 12049 | .ndo_set_vf_vlan = bnx2x_set_vf_vlan, |
3ec9f9ca | 12050 | .ndo_get_vf_config = bnx2x_get_vf_config, |
6411280a | 12051 | #endif |
55c11941 | 12052 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
12053 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, |
12054 | #endif | |
8f20aa57 | 12055 | |
e0d1095a | 12056 | #ifdef CONFIG_NET_RX_BUSY_POLL |
8b80cda5 | 12057 | .ndo_busy_poll = bnx2x_low_latency_recv, |
8f20aa57 | 12058 | #endif |
c64213cd SH |
12059 | }; |
12060 | ||
1191cb83 | 12061 | static int bnx2x_set_coherency_mask(struct bnx2x *bp) |
619c5cb6 VZ |
12062 | { |
12063 | struct device *dev = &bp->pdev->dev; | |
12064 | ||
12065 | if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { | |
12066 | bp->flags |= USING_DAC_FLAG; | |
12067 | if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { | |
51c1a580 | 12068 | dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); |
619c5cb6 VZ |
12069 | return -EIO; |
12070 | } | |
12071 | } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { | |
12072 | dev_err(dev, "System does not support DMA, aborting\n"); | |
12073 | return -EIO; | |
12074 | } | |
12075 | ||
12076 | return 0; | |
12077 | } | |
12078 | ||
1ab4434c AE |
12079 | static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, |
12080 | struct net_device *dev, unsigned long board_type) | |
a2fbb9ea | 12081 | { |
a2fbb9ea | 12082 | int rc; |
c22610d0 | 12083 | u32 pci_cfg_dword; |
65087cfe AE |
12084 | bool chip_is_e1x = (board_type == BCM57710 || |
12085 | board_type == BCM57711 || | |
12086 | board_type == BCM57711E); | |
a2fbb9ea ET |
12087 | |
12088 | SET_NETDEV_DEV(dev, &pdev->dev); | |
a2fbb9ea | 12089 | |
34f80b04 EG |
12090 | bp->dev = dev; |
12091 | bp->pdev = pdev; | |
a2fbb9ea ET |
12092 | |
12093 | rc = pci_enable_device(pdev); | |
12094 | if (rc) { | |
cdaa7cb8 VZ |
12095 | dev_err(&bp->pdev->dev, |
12096 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
12097 | goto err_out; |
12098 | } | |
12099 | ||
12100 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
12101 | dev_err(&bp->pdev->dev, |
12102 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
12103 | rc = -ENODEV; |
12104 | goto err_out_disable; | |
12105 | } | |
12106 | ||
1ab4434c AE |
12107 | if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { |
12108 | dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); | |
a2fbb9ea ET |
12109 | rc = -ENODEV; |
12110 | goto err_out_disable; | |
12111 | } | |
12112 | ||
092a5fc9 YR |
12113 | pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); |
12114 | if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == | |
12115 | PCICFG_REVESION_ID_ERROR_VAL) { | |
12116 | pr_err("PCI device error, probably due to fan failure, aborting\n"); | |
12117 | rc = -ENODEV; | |
12118 | goto err_out_disable; | |
12119 | } | |
12120 | ||
34f80b04 EG |
12121 | if (atomic_read(&pdev->enable_cnt) == 1) { |
12122 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
12123 | if (rc) { | |
cdaa7cb8 VZ |
12124 | dev_err(&bp->pdev->dev, |
12125 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
12126 | goto err_out_disable; |
12127 | } | |
a2fbb9ea | 12128 | |
34f80b04 EG |
12129 | pci_set_master(pdev); |
12130 | pci_save_state(pdev); | |
12131 | } | |
a2fbb9ea | 12132 | |
1ab4434c | 12133 | if (IS_PF(bp)) { |
b8a39dd2 | 12134 | bp->pm_cap = pdev->pm_cap; |
1ab4434c AE |
12135 | if (bp->pm_cap == 0) { |
12136 | dev_err(&bp->pdev->dev, | |
12137 | "Cannot find power management capability, aborting\n"); | |
12138 | rc = -EIO; | |
12139 | goto err_out_release; | |
12140 | } | |
a2fbb9ea ET |
12141 | } |
12142 | ||
77c98e6a | 12143 | if (!pci_is_pcie(pdev)) { |
51c1a580 | 12144 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
a2fbb9ea ET |
12145 | rc = -EIO; |
12146 | goto err_out_release; | |
12147 | } | |
12148 | ||
619c5cb6 VZ |
12149 | rc = bnx2x_set_coherency_mask(bp); |
12150 | if (rc) | |
a2fbb9ea | 12151 | goto err_out_release; |
a2fbb9ea | 12152 | |
34f80b04 EG |
12153 | dev->mem_start = pci_resource_start(pdev, 0); |
12154 | dev->base_addr = dev->mem_start; | |
12155 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
12156 | |
12157 | dev->irq = pdev->irq; | |
12158 | ||
275f165f | 12159 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 12160 | if (!bp->regview) { |
cdaa7cb8 VZ |
12161 | dev_err(&bp->pdev->dev, |
12162 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
12163 | rc = -ENOMEM; |
12164 | goto err_out_release; | |
12165 | } | |
12166 | ||
c22610d0 AE |
12167 | /* In E1/E1H use pci device function given by kernel. |
12168 | * In E2/E3 read physical function from ME register since these chips | |
12169 | * support Physical Device Assignment where kernel BDF maybe arbitrary | |
12170 | * (depending on hypervisor). | |
12171 | */ | |
2de67439 | 12172 | if (chip_is_e1x) { |
c22610d0 | 12173 | bp->pf_num = PCI_FUNC(pdev->devfn); |
2de67439 YM |
12174 | } else { |
12175 | /* chip is E2/3*/ | |
c22610d0 AE |
12176 | pci_read_config_dword(bp->pdev, |
12177 | PCICFG_ME_REGISTER, &pci_cfg_dword); | |
12178 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> | |
2de67439 | 12179 | ME_REG_ABS_PF_NUM_SHIFT); |
c22610d0 | 12180 | } |
51c1a580 | 12181 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
c22610d0 | 12182 | |
34f80b04 EG |
12183 | /* clean indirect addresses */ |
12184 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
12185 | PCICFG_VENDOR_ID_OFFSET); | |
a5c53dbc DK |
12186 | /* |
12187 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
12188 | * is not used by the driver. |
12189 | */ | |
1ab4434c AE |
12190 | if (IS_PF(bp)) { |
12191 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
12192 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
12193 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
12194 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
12195 | ||
12196 | if (chip_is_e1x) { | |
12197 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); | |
12198 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
12199 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
12200 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
12201 | } | |
a5c53dbc | 12202 | |
1ab4434c AE |
12203 | /* Enable internal target-read (in case we are probed after PF |
12204 | * FLR). Must be done prior to any BAR read access. Only for | |
12205 | * 57712 and up | |
12206 | */ | |
12207 | if (!chip_is_e1x) | |
12208 | REG_WR(bp, | |
12209 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
a5c53dbc | 12210 | } |
a2fbb9ea | 12211 | |
34f80b04 | 12212 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 12213 | |
c64213cd | 12214 | dev->netdev_ops = &bnx2x_netdev_ops; |
005a07ba | 12215 | bnx2x_set_ethtool_ops(bp, dev); |
5316bc0b | 12216 | |
01789349 JP |
12217 | dev->priv_flags |= IFF_UNICAST_FLT; |
12218 | ||
66371c44 | 12219 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
621b4d66 DK |
12220 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
12221 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | | |
f646968f | 12222 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX; |
a848ade4 | 12223 | if (!CHIP_IS_E1x(bp)) { |
65bc0cfe | 12224 | dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL; |
a848ade4 DK |
12225 | dev->hw_enc_features = |
12226 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | | |
12227 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | | |
65bc0cfe | 12228 | NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL; |
a848ade4 | 12229 | } |
66371c44 MM |
12230 | |
12231 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
12232 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
12233 | ||
f646968f | 12234 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; |
5316bc0b | 12235 | if (bp->flags & USING_DAC_FLAG) |
66371c44 | 12236 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 12237 | |
538dd2e3 MB |
12238 | /* Add Loopback capability to the device */ |
12239 | dev->hw_features |= NETIF_F_LOOPBACK; | |
12240 | ||
98507672 | 12241 | #ifdef BCM_DCBNL |
785b9b1a SR |
12242 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
12243 | #endif | |
12244 | ||
01cd4528 EG |
12245 | /* get_port_hwinfo() will set prtad and mmds properly */ |
12246 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
12247 | bp->mdio.mmds = 0; | |
12248 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
12249 | bp->mdio.dev = dev; | |
12250 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
12251 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
12252 | ||
a2fbb9ea ET |
12253 | return 0; |
12254 | ||
a2fbb9ea | 12255 | err_out_release: |
34f80b04 EG |
12256 | if (atomic_read(&pdev->enable_cnt) == 1) |
12257 | pci_release_regions(pdev); | |
a2fbb9ea ET |
12258 | |
12259 | err_out_disable: | |
12260 | pci_disable_device(pdev); | |
12261 | pci_set_drvdata(pdev, NULL); | |
12262 | ||
12263 | err_out: | |
12264 | return rc; | |
12265 | } | |
12266 | ||
ca1ee4b2 DK |
12267 | static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, |
12268 | enum bnx2x_pci_bus_speed *speed) | |
25047950 | 12269 | { |
ca1ee4b2 | 12270 | u32 link_speed, val = 0; |
25047950 | 12271 | |
1ab4434c | 12272 | pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val); |
37f9ce62 | 12273 | *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; |
25047950 | 12274 | |
ca1ee4b2 DK |
12275 | link_speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; |
12276 | ||
12277 | switch (link_speed) { | |
12278 | case 3: | |
12279 | *speed = BNX2X_PCI_LINK_SPEED_8000; | |
12280 | break; | |
12281 | case 2: | |
12282 | *speed = BNX2X_PCI_LINK_SPEED_5000; | |
12283 | break; | |
12284 | default: | |
12285 | *speed = BNX2X_PCI_LINK_SPEED_2500; | |
12286 | } | |
25047950 | 12287 | } |
37f9ce62 | 12288 | |
6891dd25 | 12289 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 12290 | { |
37f9ce62 | 12291 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
12292 | struct bnx2x_fw_file_hdr *fw_hdr; |
12293 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 12294 | u32 offset, len, num_ops; |
86564c3f | 12295 | __be16 *ops_offsets; |
94a78b79 | 12296 | int i; |
37f9ce62 | 12297 | const u8 *fw_ver; |
94a78b79 | 12298 | |
51c1a580 MS |
12299 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
12300 | BNX2X_ERR("Wrong FW size\n"); | |
94a78b79 | 12301 | return -EINVAL; |
51c1a580 | 12302 | } |
94a78b79 VZ |
12303 | |
12304 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
12305 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
12306 | ||
12307 | /* Make sure none of the offsets and sizes make us read beyond | |
12308 | * the end of the firmware data */ | |
12309 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
12310 | offset = be32_to_cpu(sections[i].offset); | |
12311 | len = be32_to_cpu(sections[i].len); | |
12312 | if (offset + len > firmware->size) { | |
51c1a580 | 12313 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
94a78b79 VZ |
12314 | return -EINVAL; |
12315 | } | |
12316 | } | |
12317 | ||
12318 | /* Likewise for the init_ops offsets */ | |
12319 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
86564c3f | 12320 | ops_offsets = (__force __be16 *)(firmware->data + offset); |
94a78b79 VZ |
12321 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); |
12322 | ||
12323 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
12324 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
51c1a580 | 12325 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
94a78b79 VZ |
12326 | return -EINVAL; |
12327 | } | |
12328 | } | |
12329 | ||
12330 | /* Check FW version */ | |
12331 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
12332 | fw_ver = firmware->data + offset; | |
12333 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
12334 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
12335 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
12336 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
51c1a580 MS |
12337 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
12338 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], | |
12339 | BCM_5710_FW_MAJOR_VERSION, | |
94a78b79 VZ |
12340 | BCM_5710_FW_MINOR_VERSION, |
12341 | BCM_5710_FW_REVISION_VERSION, | |
12342 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 12343 | return -EINVAL; |
94a78b79 VZ |
12344 | } |
12345 | ||
12346 | return 0; | |
12347 | } | |
12348 | ||
1191cb83 | 12349 | static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 12350 | { |
ab6ad5a4 EG |
12351 | const __be32 *source = (const __be32 *)_source; |
12352 | u32 *target = (u32 *)_target; | |
94a78b79 | 12353 | u32 i; |
94a78b79 VZ |
12354 | |
12355 | for (i = 0; i < n/4; i++) | |
12356 | target[i] = be32_to_cpu(source[i]); | |
12357 | } | |
12358 | ||
12359 | /* | |
12360 | Ops array is stored in the following format: | |
12361 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
12362 | */ | |
1191cb83 | 12363 | static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 12364 | { |
ab6ad5a4 EG |
12365 | const __be32 *source = (const __be32 *)_source; |
12366 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 12367 | u32 i, j, tmp; |
94a78b79 | 12368 | |
ab6ad5a4 | 12369 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
12370 | tmp = be32_to_cpu(source[j]); |
12371 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
12372 | target[i].offset = tmp & 0xffffff; |
12373 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
12374 | } |
12375 | } | |
ab6ad5a4 | 12376 | |
1aa8b471 | 12377 | /* IRO array is stored in the following format: |
523224a3 DK |
12378 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } |
12379 | */ | |
1191cb83 | 12380 | static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) |
523224a3 DK |
12381 | { |
12382 | const __be32 *source = (const __be32 *)_source; | |
12383 | struct iro *target = (struct iro *)_target; | |
12384 | u32 i, j, tmp; | |
12385 | ||
12386 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
12387 | target[i].base = be32_to_cpu(source[j]); | |
12388 | j++; | |
12389 | tmp = be32_to_cpu(source[j]); | |
12390 | target[i].m1 = (tmp >> 16) & 0xffff; | |
12391 | target[i].m2 = tmp & 0xffff; | |
12392 | j++; | |
12393 | tmp = be32_to_cpu(source[j]); | |
12394 | target[i].m3 = (tmp >> 16) & 0xffff; | |
12395 | target[i].size = tmp & 0xffff; | |
12396 | j++; | |
12397 | } | |
12398 | } | |
12399 | ||
1191cb83 | 12400 | static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 12401 | { |
ab6ad5a4 EG |
12402 | const __be16 *source = (const __be16 *)_source; |
12403 | u16 *target = (u16 *)_target; | |
94a78b79 | 12404 | u32 i; |
94a78b79 VZ |
12405 | |
12406 | for (i = 0; i < n/2; i++) | |
12407 | target[i] = be16_to_cpu(source[i]); | |
12408 | } | |
12409 | ||
7995c64e JP |
12410 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
12411 | do { \ | |
12412 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
12413 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
e404decb | 12414 | if (!bp->arr) \ |
7995c64e | 12415 | goto lbl; \ |
7995c64e JP |
12416 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
12417 | (u8 *)bp->arr, len); \ | |
12418 | } while (0) | |
94a78b79 | 12419 | |
3b603066 | 12420 | static int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 12421 | { |
c0ea452e | 12422 | const char *fw_file_name; |
94a78b79 | 12423 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 12424 | int rc; |
94a78b79 | 12425 | |
c0ea452e MS |
12426 | if (bp->firmware) |
12427 | return 0; | |
94a78b79 | 12428 | |
c0ea452e MS |
12429 | if (CHIP_IS_E1(bp)) |
12430 | fw_file_name = FW_FILE_NAME_E1; | |
12431 | else if (CHIP_IS_E1H(bp)) | |
12432 | fw_file_name = FW_FILE_NAME_E1H; | |
12433 | else if (!CHIP_IS_E1x(bp)) | |
12434 | fw_file_name = FW_FILE_NAME_E2; | |
12435 | else { | |
12436 | BNX2X_ERR("Unsupported chip revision\n"); | |
12437 | return -EINVAL; | |
12438 | } | |
12439 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); | |
94a78b79 | 12440 | |
c0ea452e MS |
12441 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
12442 | if (rc) { | |
12443 | BNX2X_ERR("Can't load firmware file %s\n", | |
12444 | fw_file_name); | |
12445 | goto request_firmware_exit; | |
12446 | } | |
eb2afd4a | 12447 | |
c0ea452e MS |
12448 | rc = bnx2x_check_firmware(bp); |
12449 | if (rc) { | |
12450 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); | |
12451 | goto request_firmware_exit; | |
94a78b79 VZ |
12452 | } |
12453 | ||
12454 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
12455 | ||
12456 | /* Initialize the pointers to the init arrays */ | |
12457 | /* Blob */ | |
12458 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
12459 | ||
12460 | /* Opcodes */ | |
12461 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
12462 | ||
12463 | /* Offsets */ | |
ab6ad5a4 EG |
12464 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
12465 | be16_to_cpu_n); | |
94a78b79 VZ |
12466 | |
12467 | /* STORMs firmware */ | |
573f2035 EG |
12468 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
12469 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
12470 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
12471 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
12472 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
12473 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
12474 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
12475 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
12476 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
12477 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
12478 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
12479 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
12480 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
12481 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
12482 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
12483 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
12484 | /* IRO */ |
12485 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
12486 | |
12487 | return 0; | |
ab6ad5a4 | 12488 | |
523224a3 DK |
12489 | iro_alloc_err: |
12490 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
12491 | init_offsets_alloc_err: |
12492 | kfree(bp->init_ops); | |
12493 | init_ops_alloc_err: | |
12494 | kfree(bp->init_data); | |
12495 | request_firmware_exit: | |
12496 | release_firmware(bp->firmware); | |
127d0a19 | 12497 | bp->firmware = NULL; |
94a78b79 VZ |
12498 | |
12499 | return rc; | |
12500 | } | |
12501 | ||
619c5cb6 VZ |
12502 | static void bnx2x_release_firmware(struct bnx2x *bp) |
12503 | { | |
12504 | kfree(bp->init_ops_offsets); | |
12505 | kfree(bp->init_ops); | |
12506 | kfree(bp->init_data); | |
12507 | release_firmware(bp->firmware); | |
eb2afd4a | 12508 | bp->firmware = NULL; |
619c5cb6 VZ |
12509 | } |
12510 | ||
619c5cb6 VZ |
12511 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { |
12512 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
12513 | .init_hw_cmn = bnx2x_init_hw_common, | |
12514 | .init_hw_port = bnx2x_init_hw_port, | |
12515 | .init_hw_func = bnx2x_init_hw_func, | |
12516 | ||
12517 | .reset_hw_cmn = bnx2x_reset_common, | |
12518 | .reset_hw_port = bnx2x_reset_port, | |
12519 | .reset_hw_func = bnx2x_reset_func, | |
12520 | ||
12521 | .gunzip_init = bnx2x_gunzip_init, | |
12522 | .gunzip_end = bnx2x_gunzip_end, | |
12523 | ||
12524 | .init_fw = bnx2x_init_firmware, | |
12525 | .release_fw = bnx2x_release_firmware, | |
12526 | }; | |
12527 | ||
12528 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
12529 | { | |
12530 | /* Prepare DMAE related driver resources */ | |
12531 | bnx2x_setup_dmae(bp); | |
12532 | ||
12533 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
12534 | bnx2x_sp(bp, func_rdata), | |
12535 | bnx2x_sp_mapping(bp, func_rdata), | |
a3348722 BW |
12536 | bnx2x_sp(bp, func_afex_rdata), |
12537 | bnx2x_sp_mapping(bp, func_afex_rdata), | |
619c5cb6 VZ |
12538 | &bnx2x_func_sp_drv); |
12539 | } | |
12540 | ||
12541 | /* must be called after sriov-enable */ | |
1191cb83 | 12542 | static int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 12543 | { |
37ae41a9 | 12544 | int cid_count = BNX2X_L2_MAX_CID(bp); |
94a78b79 | 12545 | |
290ca2bb AE |
12546 | if (IS_SRIOV(bp)) |
12547 | cid_count += BNX2X_VF_CIDS; | |
12548 | ||
55c11941 MS |
12549 | if (CNIC_SUPPORT(bp)) |
12550 | cid_count += CNIC_CID_MAX; | |
290ca2bb | 12551 | |
523224a3 DK |
12552 | return roundup(cid_count, QM_CID_ROUND); |
12553 | } | |
f85582f8 | 12554 | |
619c5cb6 | 12555 | /** |
6383c0b3 | 12556 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
12557 | * |
12558 | * @dev: pci device | |
12559 | * | |
12560 | */ | |
55c11941 | 12561 | static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, |
1ab4434c | 12562 | int cnic_cnt, bool is_vf) |
619c5cb6 | 12563 | { |
1ab4434c AE |
12564 | int pos, index; |
12565 | u16 control = 0; | |
619c5cb6 VZ |
12566 | |
12567 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); | |
6383c0b3 AE |
12568 | |
12569 | /* | |
12570 | * If MSI-X is not supported - return number of SBs needed to support | |
12571 | * one fast path queue: one FP queue + SB for CNIC | |
12572 | */ | |
1ab4434c AE |
12573 | if (!pos) { |
12574 | dev_info(&pdev->dev, "no msix capability found\n"); | |
55c11941 | 12575 | return 1 + cnic_cnt; |
1ab4434c AE |
12576 | } |
12577 | dev_info(&pdev->dev, "msix capability found\n"); | |
619c5cb6 | 12578 | |
6383c0b3 AE |
12579 | /* |
12580 | * The value in the PCI configuration space is the index of the last | |
12581 | * entry, namely one less than the actual size of the table, which is | |
12582 | * exactly what we want to return from this function: number of all SBs | |
12583 | * without the default SB. | |
1ab4434c | 12584 | * For VFs there is no default SB, then we return (index+1). |
6383c0b3 | 12585 | */ |
619c5cb6 | 12586 | pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); |
619c5cb6 | 12587 | |
1ab4434c | 12588 | index = control & PCI_MSIX_FLAGS_QSIZE; |
4bd9b0ff | 12589 | |
1ab4434c AE |
12590 | return is_vf ? index + 1 : index; |
12591 | } | |
523224a3 | 12592 | |
1ab4434c AE |
12593 | static int set_max_cos_est(int chip_id) |
12594 | { | |
12595 | switch (chip_id) { | |
f2e0899f DK |
12596 | case BCM57710: |
12597 | case BCM57711: | |
12598 | case BCM57711E: | |
1ab4434c | 12599 | return BNX2X_MULTI_TX_COS_E1X; |
f2e0899f | 12600 | case BCM57712: |
619c5cb6 | 12601 | case BCM57712_MF: |
1ab4434c AE |
12602 | case BCM57712_VF: |
12603 | return BNX2X_MULTI_TX_COS_E2_E3A0; | |
619c5cb6 VZ |
12604 | case BCM57800: |
12605 | case BCM57800_MF: | |
1ab4434c | 12606 | case BCM57800_VF: |
619c5cb6 VZ |
12607 | case BCM57810: |
12608 | case BCM57810_MF: | |
c3def943 YM |
12609 | case BCM57840_4_10: |
12610 | case BCM57840_2_20: | |
1ab4434c | 12611 | case BCM57840_O: |
c3def943 | 12612 | case BCM57840_MFO: |
1ab4434c | 12613 | case BCM57810_VF: |
619c5cb6 | 12614 | case BCM57840_MF: |
1ab4434c | 12615 | case BCM57840_VF: |
7e8e02df BW |
12616 | case BCM57811: |
12617 | case BCM57811_MF: | |
1ab4434c AE |
12618 | case BCM57811_VF: |
12619 | return BNX2X_MULTI_TX_COS_E3B0; | |
12620 | return 1; | |
f2e0899f | 12621 | default: |
1ab4434c | 12622 | pr_err("Unknown board_type (%d), aborting\n", chip_id); |
870634b0 | 12623 | return -ENODEV; |
f2e0899f | 12624 | } |
1ab4434c | 12625 | } |
f2e0899f | 12626 | |
1ab4434c AE |
12627 | static int set_is_vf(int chip_id) |
12628 | { | |
12629 | switch (chip_id) { | |
12630 | case BCM57712_VF: | |
12631 | case BCM57800_VF: | |
12632 | case BCM57810_VF: | |
12633 | case BCM57840_VF: | |
12634 | case BCM57811_VF: | |
12635 | return true; | |
12636 | default: | |
12637 | return false; | |
12638 | } | |
12639 | } | |
6383c0b3 | 12640 | |
1ab4434c AE |
12641 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); |
12642 | ||
12643 | static int bnx2x_init_one(struct pci_dev *pdev, | |
12644 | const struct pci_device_id *ent) | |
12645 | { | |
12646 | struct net_device *dev = NULL; | |
12647 | struct bnx2x *bp; | |
ca1ee4b2 DK |
12648 | int pcie_width; |
12649 | enum bnx2x_pci_bus_speed pcie_speed; | |
1ab4434c AE |
12650 | int rc, max_non_def_sbs; |
12651 | int rx_count, tx_count, rss_count, doorbell_size; | |
12652 | int max_cos_est; | |
12653 | bool is_vf; | |
12654 | int cnic_cnt; | |
12655 | ||
12656 | /* An estimated maximum supported CoS number according to the chip | |
12657 | * version. | |
12658 | * We will try to roughly estimate the maximum number of CoSes this chip | |
12659 | * may support in order to minimize the memory allocated for Tx | |
12660 | * netdev_queue's. This number will be accurately calculated during the | |
12661 | * initialization of bp->max_cos based on the chip versions AND chip | |
12662 | * revision in the bnx2x_init_bp(). | |
12663 | */ | |
12664 | max_cos_est = set_max_cos_est(ent->driver_data); | |
12665 | if (max_cos_est < 0) | |
12666 | return max_cos_est; | |
12667 | is_vf = set_is_vf(ent->driver_data); | |
12668 | cnic_cnt = is_vf ? 0 : 1; | |
12669 | ||
12670 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf); | |
6383c0b3 AE |
12671 | |
12672 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
1ab4434c AE |
12673 | rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt; |
12674 | ||
12675 | if (rss_count < 1) | |
12676 | return -EINVAL; | |
6383c0b3 AE |
12677 | |
12678 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
55c11941 | 12679 | rx_count = rss_count + cnic_cnt; |
6383c0b3 | 12680 | |
1ab4434c | 12681 | /* Maximum number of netdev Tx queues: |
37ae41a9 | 12682 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 |
6383c0b3 | 12683 | */ |
55c11941 | 12684 | tx_count = rss_count * max_cos_est + cnic_cnt; |
f85582f8 | 12685 | |
a2fbb9ea | 12686 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 12687 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
41de8d4c | 12688 | if (!dev) |
a2fbb9ea ET |
12689 | return -ENOMEM; |
12690 | ||
a2fbb9ea | 12691 | bp = netdev_priv(dev); |
a2fbb9ea | 12692 | |
1ab4434c AE |
12693 | bp->flags = 0; |
12694 | if (is_vf) | |
12695 | bp->flags |= IS_VF_FLAG; | |
12696 | ||
6383c0b3 | 12697 | bp->igu_sb_cnt = max_non_def_sbs; |
1ab4434c | 12698 | bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; |
6383c0b3 | 12699 | bp->msg_enable = debug; |
55c11941 | 12700 | bp->cnic_support = cnic_cnt; |
4bd9b0ff | 12701 | bp->cnic_probe = bnx2x_cnic_probe; |
55c11941 | 12702 | |
6383c0b3 | 12703 | pci_set_drvdata(pdev, dev); |
523224a3 | 12704 | |
1ab4434c | 12705 | rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); |
a2fbb9ea ET |
12706 | if (rc < 0) { |
12707 | free_netdev(dev); | |
12708 | return rc; | |
12709 | } | |
12710 | ||
1ab4434c AE |
12711 | BNX2X_DEV_INFO("This is a %s function\n", |
12712 | IS_PF(bp) ? "physical" : "virtual"); | |
55c11941 | 12713 | BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); |
1ab4434c | 12714 | BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); |
60aa0509 | 12715 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
2de67439 | 12716 | tx_count, rx_count); |
60aa0509 | 12717 | |
34f80b04 | 12718 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
12719 | if (rc) |
12720 | goto init_one_exit; | |
12721 | ||
1ab4434c AE |
12722 | /* Map doorbells here as we need the real value of bp->max_cos which |
12723 | * is initialized in bnx2x_init_bp() to determine the number of | |
12724 | * l2 connections. | |
6383c0b3 | 12725 | */ |
1ab4434c | 12726 | if (IS_VF(bp)) { |
1d6f3cd8 | 12727 | bp->doorbells = bnx2x_vf_doorbells(bp); |
6411280a AE |
12728 | rc = bnx2x_vf_pci_alloc(bp); |
12729 | if (rc) | |
12730 | goto init_one_exit; | |
1ab4434c AE |
12731 | } else { |
12732 | doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); | |
12733 | if (doorbell_size > pci_resource_len(pdev, 2)) { | |
12734 | dev_err(&bp->pdev->dev, | |
12735 | "Cannot map doorbells, bar size too small, aborting\n"); | |
12736 | rc = -ENOMEM; | |
12737 | goto init_one_exit; | |
12738 | } | |
12739 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), | |
12740 | doorbell_size); | |
37ae41a9 | 12741 | } |
6383c0b3 AE |
12742 | if (!bp->doorbells) { |
12743 | dev_err(&bp->pdev->dev, | |
12744 | "Cannot map doorbell space, aborting\n"); | |
12745 | rc = -ENOMEM; | |
12746 | goto init_one_exit; | |
12747 | } | |
12748 | ||
be1f1ffa AE |
12749 | if (IS_VF(bp)) { |
12750 | rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); | |
12751 | if (rc) | |
12752 | goto init_one_exit; | |
12753 | } | |
12754 | ||
3c76feff AE |
12755 | /* Enable SRIOV if capability found in configuration space */ |
12756 | rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); | |
290ca2bb AE |
12757 | if (rc) |
12758 | goto init_one_exit; | |
12759 | ||
523224a3 | 12760 | /* calc qm_cid_count */ |
6383c0b3 | 12761 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
1ab4434c | 12762 | BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); |
523224a3 | 12763 | |
55c11941 | 12764 | /* disable FCOE L2 queue for E1x*/ |
62ac0dc9 | 12765 | if (CHIP_IS_E1x(bp)) |
ec6ba945 VZ |
12766 | bp->flags |= NO_FCOE_FLAG; |
12767 | ||
0e8d2ec5 MS |
12768 | /* Set bp->num_queues for MSI-X mode*/ |
12769 | bnx2x_set_num_queues(bp); | |
12770 | ||
25985edc | 12771 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
0e8d2ec5 | 12772 | * needed. |
d6214d7a | 12773 | */ |
1ab4434c AE |
12774 | rc = bnx2x_set_int_mode(bp); |
12775 | if (rc) { | |
12776 | dev_err(&pdev->dev, "Cannot set interrupts\n"); | |
12777 | goto init_one_exit; | |
12778 | } | |
04c46736 | 12779 | BNX2X_DEV_INFO("set interrupts successfully\n"); |
d6214d7a | 12780 | |
1ab4434c | 12781 | /* register the net device */ |
b340007f VZ |
12782 | rc = register_netdev(dev); |
12783 | if (rc) { | |
12784 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
12785 | goto init_one_exit; | |
12786 | } | |
1ab4434c | 12787 | BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); |
b340007f | 12788 | |
ec6ba945 VZ |
12789 | if (!NO_FCOE(bp)) { |
12790 | /* Add storage MAC address */ | |
12791 | rtnl_lock(); | |
12792 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
12793 | rtnl_unlock(); | |
12794 | } | |
ec6ba945 | 12795 | |
37f9ce62 | 12796 | bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); |
1ab4434c AE |
12797 | BNX2X_DEV_INFO("got pcie width %d and speed %d\n", |
12798 | pcie_width, pcie_speed); | |
d6214d7a | 12799 | |
ca1ee4b2 DK |
12800 | BNX2X_DEV_INFO("%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", |
12801 | board_info[ent->driver_data].name, | |
12802 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
12803 | pcie_width, | |
12804 | pcie_speed == BNX2X_PCI_LINK_SPEED_2500 ? "2.5GHz" : | |
12805 | pcie_speed == BNX2X_PCI_LINK_SPEED_5000 ? "5.0GHz" : | |
12806 | pcie_speed == BNX2X_PCI_LINK_SPEED_8000 ? "8.0GHz" : | |
12807 | "Unknown", | |
12808 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
c016201c | 12809 | |
a2fbb9ea | 12810 | return 0; |
34f80b04 EG |
12811 | |
12812 | init_one_exit: | |
12813 | if (bp->regview) | |
12814 | iounmap(bp->regview); | |
12815 | ||
1ab4434c | 12816 | if (IS_PF(bp) && bp->doorbells) |
34f80b04 EG |
12817 | iounmap(bp->doorbells); |
12818 | ||
12819 | free_netdev(dev); | |
12820 | ||
12821 | if (atomic_read(&pdev->enable_cnt) == 1) | |
12822 | pci_release_regions(pdev); | |
12823 | ||
12824 | pci_disable_device(pdev); | |
12825 | pci_set_drvdata(pdev, NULL); | |
12826 | ||
12827 | return rc; | |
a2fbb9ea ET |
12828 | } |
12829 | ||
b030ed2f YM |
12830 | static void __bnx2x_remove(struct pci_dev *pdev, |
12831 | struct net_device *dev, | |
12832 | struct bnx2x *bp, | |
12833 | bool remove_netdev) | |
a2fbb9ea | 12834 | { |
ec6ba945 VZ |
12835 | /* Delete storage MAC address */ |
12836 | if (!NO_FCOE(bp)) { | |
12837 | rtnl_lock(); | |
12838 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
12839 | rtnl_unlock(); | |
12840 | } | |
ec6ba945 | 12841 | |
98507672 SR |
12842 | #ifdef BCM_DCBNL |
12843 | /* Delete app tlvs from dcbnl */ | |
12844 | bnx2x_dcbnl_update_applist(bp, true); | |
12845 | #endif | |
12846 | ||
a6d3a5ba BW |
12847 | if (IS_PF(bp) && |
12848 | !BP_NOMCP(bp) && | |
12849 | (bp->flags & BC_SUPPORTS_RMMOD_CMD)) | |
12850 | bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); | |
12851 | ||
b030ed2f YM |
12852 | /* Close the interface - either directly or implicitly */ |
12853 | if (remove_netdev) { | |
12854 | unregister_netdev(dev); | |
12855 | } else { | |
12856 | rtnl_lock(); | |
6ef5a92c | 12857 | dev_close(dev); |
b030ed2f YM |
12858 | rtnl_unlock(); |
12859 | } | |
a2fbb9ea | 12860 | |
78c3bcc5 AE |
12861 | bnx2x_iov_remove_one(bp); |
12862 | ||
084d6cbb | 12863 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
1ab4434c AE |
12864 | if (IS_PF(bp)) |
12865 | bnx2x_set_power_state(bp, PCI_D0); | |
084d6cbb | 12866 | |
d6214d7a DK |
12867 | /* Disable MSI/MSI-X */ |
12868 | bnx2x_disable_msi(bp); | |
f85582f8 | 12869 | |
084d6cbb | 12870 | /* Power off */ |
1ab4434c AE |
12871 | if (IS_PF(bp)) |
12872 | bnx2x_set_power_state(bp, PCI_D3hot); | |
084d6cbb | 12873 | |
72fd0718 | 12874 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 12875 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
290ca2bb | 12876 | |
4513f925 AE |
12877 | /* send message via vfpf channel to release the resources of this vf */ |
12878 | if (IS_VF(bp)) | |
12879 | bnx2x_vfpf_release(bp); | |
72fd0718 | 12880 | |
b030ed2f YM |
12881 | /* Assumes no further PCIe PM changes will occur */ |
12882 | if (system_state == SYSTEM_POWER_OFF) { | |
12883 | pci_wake_from_d3(pdev, bp->wol); | |
12884 | pci_set_power_state(pdev, PCI_D3hot); | |
12885 | } | |
12886 | ||
a2fbb9ea ET |
12887 | if (bp->regview) |
12888 | iounmap(bp->regview); | |
12889 | ||
1ab4434c AE |
12890 | /* for vf doorbells are part of the regview and were unmapped along with |
12891 | * it. FW is only loaded by PF. | |
12892 | */ | |
12893 | if (IS_PF(bp)) { | |
12894 | if (bp->doorbells) | |
12895 | iounmap(bp->doorbells); | |
eb2afd4a | 12896 | |
1ab4434c AE |
12897 | bnx2x_release_firmware(bp); |
12898 | } | |
523224a3 DK |
12899 | bnx2x_free_mem_bp(bp); |
12900 | ||
b030ed2f YM |
12901 | if (remove_netdev) |
12902 | free_netdev(dev); | |
34f80b04 EG |
12903 | |
12904 | if (atomic_read(&pdev->enable_cnt) == 1) | |
12905 | pci_release_regions(pdev); | |
12906 | ||
a2fbb9ea ET |
12907 | pci_disable_device(pdev); |
12908 | pci_set_drvdata(pdev, NULL); | |
12909 | } | |
12910 | ||
b030ed2f YM |
12911 | static void bnx2x_remove_one(struct pci_dev *pdev) |
12912 | { | |
12913 | struct net_device *dev = pci_get_drvdata(pdev); | |
12914 | struct bnx2x *bp; | |
12915 | ||
12916 | if (!dev) { | |
12917 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); | |
12918 | return; | |
12919 | } | |
12920 | bp = netdev_priv(dev); | |
12921 | ||
12922 | __bnx2x_remove(pdev, dev, bp, true); | |
12923 | } | |
12924 | ||
f8ef6e44 YG |
12925 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
12926 | { | |
7fa6f340 | 12927 | bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; |
f8ef6e44 YG |
12928 | |
12929 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
12930 | ||
55c11941 MS |
12931 | if (CNIC_LOADED(bp)) |
12932 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
12933 | ||
619c5cb6 VZ |
12934 | /* Stop Tx */ |
12935 | bnx2x_tx_disable(bp); | |
26614ba5 MS |
12936 | /* Delete all NAPI objects */ |
12937 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
12938 | if (CNIC_LOADED(bp)) |
12939 | bnx2x_del_all_napi_cnic(bp); | |
7fa6f340 | 12940 | netdev_reset_tc(bp->dev); |
f8ef6e44 YG |
12941 | |
12942 | del_timer_sync(&bp->timer); | |
7fa6f340 YM |
12943 | cancel_delayed_work(&bp->sp_task); |
12944 | cancel_delayed_work(&bp->period_task); | |
619c5cb6 | 12945 | |
7fa6f340 YM |
12946 | spin_lock_bh(&bp->stats_lock); |
12947 | bp->stats_state = STATS_STATE_DISABLED; | |
12948 | spin_unlock_bh(&bp->stats_lock); | |
f8ef6e44 | 12949 | |
7fa6f340 | 12950 | bnx2x_save_statistics(bp); |
f8ef6e44 | 12951 | |
619c5cb6 VZ |
12952 | netif_carrier_off(bp->dev); |
12953 | ||
f8ef6e44 YG |
12954 | return 0; |
12955 | } | |
12956 | ||
493adb1f WX |
12957 | /** |
12958 | * bnx2x_io_error_detected - called when PCI error is detected | |
12959 | * @pdev: Pointer to PCI device | |
12960 | * @state: The current pci connection state | |
12961 | * | |
12962 | * This function is called after a PCI bus error affecting | |
12963 | * this device has been detected. | |
12964 | */ | |
12965 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
12966 | pci_channel_state_t state) | |
12967 | { | |
12968 | struct net_device *dev = pci_get_drvdata(pdev); | |
12969 | struct bnx2x *bp = netdev_priv(dev); | |
12970 | ||
12971 | rtnl_lock(); | |
12972 | ||
7fa6f340 YM |
12973 | BNX2X_ERR("IO error detected\n"); |
12974 | ||
493adb1f WX |
12975 | netif_device_detach(dev); |
12976 | ||
07ce50e4 DN |
12977 | if (state == pci_channel_io_perm_failure) { |
12978 | rtnl_unlock(); | |
12979 | return PCI_ERS_RESULT_DISCONNECT; | |
12980 | } | |
12981 | ||
493adb1f | 12982 | if (netif_running(dev)) |
f8ef6e44 | 12983 | bnx2x_eeh_nic_unload(bp); |
493adb1f | 12984 | |
7fa6f340 YM |
12985 | bnx2x_prev_path_mark_eeh(bp); |
12986 | ||
493adb1f WX |
12987 | pci_disable_device(pdev); |
12988 | ||
12989 | rtnl_unlock(); | |
12990 | ||
12991 | /* Request a slot reset */ | |
12992 | return PCI_ERS_RESULT_NEED_RESET; | |
12993 | } | |
12994 | ||
12995 | /** | |
12996 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
12997 | * @pdev: Pointer to PCI device | |
12998 | * | |
12999 | * Restart the card from scratch, as if from a cold-boot. | |
13000 | */ | |
13001 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
13002 | { | |
13003 | struct net_device *dev = pci_get_drvdata(pdev); | |
13004 | struct bnx2x *bp = netdev_priv(dev); | |
7fa6f340 | 13005 | int i; |
493adb1f WX |
13006 | |
13007 | rtnl_lock(); | |
7fa6f340 | 13008 | BNX2X_ERR("IO slot reset initializing...\n"); |
493adb1f WX |
13009 | if (pci_enable_device(pdev)) { |
13010 | dev_err(&pdev->dev, | |
13011 | "Cannot re-enable PCI device after reset\n"); | |
13012 | rtnl_unlock(); | |
13013 | return PCI_ERS_RESULT_DISCONNECT; | |
13014 | } | |
13015 | ||
13016 | pci_set_master(pdev); | |
13017 | pci_restore_state(pdev); | |
70632d0a | 13018 | pci_save_state(pdev); |
493adb1f WX |
13019 | |
13020 | if (netif_running(dev)) | |
13021 | bnx2x_set_power_state(bp, PCI_D0); | |
13022 | ||
7fa6f340 YM |
13023 | if (netif_running(dev)) { |
13024 | BNX2X_ERR("IO slot reset --> driver unload\n"); | |
e68072ef YM |
13025 | |
13026 | /* MCP should have been reset; Need to wait for validity */ | |
13027 | bnx2x_init_shmem(bp); | |
13028 | ||
7fa6f340 YM |
13029 | if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { |
13030 | u32 v; | |
13031 | ||
13032 | v = SHMEM2_RD(bp, | |
13033 | drv_capabilities_flag[BP_FW_MB_IDX(bp)]); | |
13034 | SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], | |
13035 | v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); | |
13036 | } | |
13037 | bnx2x_drain_tx_queues(bp); | |
13038 | bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); | |
13039 | bnx2x_netif_stop(bp, 1); | |
13040 | bnx2x_free_irq(bp); | |
13041 | ||
13042 | /* Report UNLOAD_DONE to MCP */ | |
13043 | bnx2x_send_unload_done(bp, true); | |
13044 | ||
13045 | bp->sp_state = 0; | |
13046 | bp->port.pmf = 0; | |
13047 | ||
13048 | bnx2x_prev_unload(bp); | |
13049 | ||
16a5fd92 | 13050 | /* We should have reseted the engine, so It's fair to |
7fa6f340 YM |
13051 | * assume the FW will no longer write to the bnx2x driver. |
13052 | */ | |
13053 | bnx2x_squeeze_objects(bp); | |
13054 | bnx2x_free_skbs(bp); | |
13055 | for_each_rx_queue(bp, i) | |
13056 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); | |
13057 | bnx2x_free_fp_mem(bp); | |
13058 | bnx2x_free_mem(bp); | |
13059 | ||
13060 | bp->state = BNX2X_STATE_CLOSED; | |
13061 | } | |
13062 | ||
493adb1f WX |
13063 | rtnl_unlock(); |
13064 | ||
13065 | return PCI_ERS_RESULT_RECOVERED; | |
13066 | } | |
13067 | ||
13068 | /** | |
13069 | * bnx2x_io_resume - called when traffic can start flowing again | |
13070 | * @pdev: Pointer to PCI device | |
13071 | * | |
13072 | * This callback is called when the error recovery driver tells us that | |
13073 | * its OK to resume normal operation. | |
13074 | */ | |
13075 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
13076 | { | |
13077 | struct net_device *dev = pci_get_drvdata(pdev); | |
13078 | struct bnx2x *bp = netdev_priv(dev); | |
13079 | ||
72fd0718 | 13080 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 13081 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
72fd0718 VZ |
13082 | return; |
13083 | } | |
13084 | ||
493adb1f WX |
13085 | rtnl_lock(); |
13086 | ||
7fa6f340 YM |
13087 | bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & |
13088 | DRV_MSG_SEQ_NUMBER_MASK; | |
13089 | ||
493adb1f | 13090 | if (netif_running(dev)) |
f8ef6e44 | 13091 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
13092 | |
13093 | netif_device_attach(dev); | |
13094 | ||
13095 | rtnl_unlock(); | |
13096 | } | |
13097 | ||
3646f0e5 | 13098 | static const struct pci_error_handlers bnx2x_err_handler = { |
493adb1f | 13099 | .error_detected = bnx2x_io_error_detected, |
356e2385 EG |
13100 | .slot_reset = bnx2x_io_slot_reset, |
13101 | .resume = bnx2x_io_resume, | |
493adb1f WX |
13102 | }; |
13103 | ||
b030ed2f YM |
13104 | static void bnx2x_shutdown(struct pci_dev *pdev) |
13105 | { | |
13106 | struct net_device *dev = pci_get_drvdata(pdev); | |
13107 | struct bnx2x *bp; | |
13108 | ||
13109 | if (!dev) | |
13110 | return; | |
13111 | ||
13112 | bp = netdev_priv(dev); | |
13113 | if (!bp) | |
13114 | return; | |
13115 | ||
13116 | rtnl_lock(); | |
13117 | netif_device_detach(dev); | |
13118 | rtnl_unlock(); | |
13119 | ||
13120 | /* Don't remove the netdevice, as there are scenarios which will cause | |
13121 | * the kernel to hang, e.g., when trying to remove bnx2i while the | |
13122 | * rootfs is mounted from SAN. | |
13123 | */ | |
13124 | __bnx2x_remove(pdev, dev, bp, false); | |
13125 | } | |
13126 | ||
a2fbb9ea | 13127 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
13128 | .name = DRV_MODULE_NAME, |
13129 | .id_table = bnx2x_pci_tbl, | |
13130 | .probe = bnx2x_init_one, | |
0329aba1 | 13131 | .remove = bnx2x_remove_one, |
493adb1f WX |
13132 | .suspend = bnx2x_suspend, |
13133 | .resume = bnx2x_resume, | |
13134 | .err_handler = &bnx2x_err_handler, | |
3c76feff AE |
13135 | #ifdef CONFIG_BNX2X_SRIOV |
13136 | .sriov_configure = bnx2x_sriov_configure, | |
13137 | #endif | |
b030ed2f | 13138 | .shutdown = bnx2x_shutdown, |
a2fbb9ea ET |
13139 | }; |
13140 | ||
13141 | static int __init bnx2x_init(void) | |
13142 | { | |
dd21ca6d SG |
13143 | int ret; |
13144 | ||
7995c64e | 13145 | pr_info("%s", version); |
938cf541 | 13146 | |
1cf167f2 EG |
13147 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
13148 | if (bnx2x_wq == NULL) { | |
7995c64e | 13149 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
13150 | return -ENOMEM; |
13151 | } | |
13152 | ||
dd21ca6d SG |
13153 | ret = pci_register_driver(&bnx2x_pci_driver); |
13154 | if (ret) { | |
7995c64e | 13155 | pr_err("Cannot register driver\n"); |
dd21ca6d SG |
13156 | destroy_workqueue(bnx2x_wq); |
13157 | } | |
13158 | return ret; | |
a2fbb9ea ET |
13159 | } |
13160 | ||
13161 | static void __exit bnx2x_cleanup(void) | |
13162 | { | |
452427b0 | 13163 | struct list_head *pos, *q; |
d76a6111 | 13164 | |
a2fbb9ea | 13165 | pci_unregister_driver(&bnx2x_pci_driver); |
1cf167f2 EG |
13166 | |
13167 | destroy_workqueue(bnx2x_wq); | |
452427b0 | 13168 | |
16a5fd92 | 13169 | /* Free globally allocated resources */ |
452427b0 YM |
13170 | list_for_each_safe(pos, q, &bnx2x_prev_list) { |
13171 | struct bnx2x_prev_path_list *tmp = | |
13172 | list_entry(pos, struct bnx2x_prev_path_list, list); | |
13173 | list_del(pos); | |
13174 | kfree(tmp); | |
13175 | } | |
a2fbb9ea ET |
13176 | } |
13177 | ||
3deb8167 YR |
13178 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
13179 | { | |
13180 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
13181 | } | |
13182 | ||
a2fbb9ea ET |
13183 | module_init(bnx2x_init); |
13184 | module_exit(bnx2x_cleanup); | |
13185 | ||
619c5cb6 VZ |
13186 | /** |
13187 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
13188 | * | |
13189 | * @bp: driver handle | |
13190 | * @set: set or clear the CAM entry | |
13191 | * | |
16a5fd92 | 13192 | * This function will wait until the ramrod completion returns. |
619c5cb6 VZ |
13193 | * Return 0 if success, -ENODEV if ramrod doesn't return. |
13194 | */ | |
1191cb83 | 13195 | static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) |
619c5cb6 VZ |
13196 | { |
13197 | unsigned long ramrod_flags = 0; | |
13198 | ||
13199 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
13200 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
13201 | &bp->iscsi_l2_mac_obj, true, | |
13202 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
13203 | } | |
993ac7b5 MC |
13204 | |
13205 | /* count denotes the number of new completions we have seen */ | |
13206 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
13207 | { | |
13208 | struct eth_spe *spe; | |
a052997e | 13209 | int cxt_index, cxt_offset; |
993ac7b5 MC |
13210 | |
13211 | #ifdef BNX2X_STOP_ON_ERROR | |
13212 | if (unlikely(bp->panic)) | |
13213 | return; | |
13214 | #endif | |
13215 | ||
13216 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 13217 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
13218 | bp->cnic_spq_pending -= count; |
13219 | ||
c2bff63f DK |
13220 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
13221 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
13222 | & SPE_HDR_CONN_TYPE) >> | |
13223 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
13224 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
13225 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
13226 | |
13227 | /* Set validation for iSCSI L2 client before sending SETUP | |
13228 | * ramrod | |
13229 | */ | |
13230 | if (type == ETH_CONNECTION_TYPE) { | |
a052997e | 13231 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { |
37ae41a9 | 13232 | cxt_index = BNX2X_ISCSI_ETH_CID(bp) / |
a052997e | 13233 | ILT_PAGE_CIDS; |
37ae41a9 | 13234 | cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - |
a052997e MS |
13235 | (cxt_index * ILT_PAGE_CIDS); |
13236 | bnx2x_set_ctx_validation(bp, | |
13237 | &bp->context[cxt_index]. | |
13238 | vcxt[cxt_offset].eth, | |
37ae41a9 | 13239 | BNX2X_ISCSI_ETH_CID(bp)); |
a052997e | 13240 | } |
c2bff63f DK |
13241 | } |
13242 | ||
619c5cb6 VZ |
13243 | /* |
13244 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
13245 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
13246 | * COMMON ramrods is not more than the EQ and SPQ can |
13247 | * accommodate. | |
c2bff63f | 13248 | */ |
6e30dd4e VZ |
13249 | if (type == ETH_CONNECTION_TYPE) { |
13250 | if (!atomic_read(&bp->cq_spq_left)) | |
13251 | break; | |
13252 | else | |
13253 | atomic_dec(&bp->cq_spq_left); | |
13254 | } else if (type == NONE_CONNECTION_TYPE) { | |
13255 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
13256 | break; |
13257 | else | |
6e30dd4e | 13258 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
13259 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
13260 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
13261 | if (bp->cnic_spq_pending >= |
13262 | bp->cnic_eth_dev.max_kwqe_pending) | |
13263 | break; | |
13264 | else | |
13265 | bp->cnic_spq_pending++; | |
13266 | } else { | |
13267 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
13268 | bnx2x_panic(); | |
993ac7b5 | 13269 | break; |
c2bff63f | 13270 | } |
993ac7b5 MC |
13271 | |
13272 | spe = bnx2x_sp_get_next(bp); | |
13273 | *spe = *bp->cnic_kwq_cons; | |
13274 | ||
51c1a580 | 13275 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
993ac7b5 MC |
13276 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
13277 | ||
13278 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
13279 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
13280 | else | |
13281 | bp->cnic_kwq_cons++; | |
13282 | } | |
13283 | bnx2x_sp_prod_update(bp); | |
13284 | spin_unlock_bh(&bp->spq_lock); | |
13285 | } | |
13286 | ||
13287 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
13288 | struct kwqe_16 *kwqes[], u32 count) | |
13289 | { | |
13290 | struct bnx2x *bp = netdev_priv(dev); | |
13291 | int i; | |
13292 | ||
13293 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 MS |
13294 | if (unlikely(bp->panic)) { |
13295 | BNX2X_ERR("Can't post to SP queue while panic\n"); | |
993ac7b5 | 13296 | return -EIO; |
51c1a580 | 13297 | } |
993ac7b5 MC |
13298 | #endif |
13299 | ||
95c6c616 AE |
13300 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
13301 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
51c1a580 | 13302 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
95c6c616 AE |
13303 | return -EAGAIN; |
13304 | } | |
13305 | ||
993ac7b5 MC |
13306 | spin_lock_bh(&bp->spq_lock); |
13307 | ||
13308 | for (i = 0; i < count; i++) { | |
13309 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
13310 | ||
13311 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
13312 | break; | |
13313 | ||
13314 | *bp->cnic_kwq_prod = *spe; | |
13315 | ||
13316 | bp->cnic_kwq_pending++; | |
13317 | ||
51c1a580 | 13318 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
993ac7b5 | 13319 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
523224a3 DK |
13320 | spe->data.update_data_addr.hi, |
13321 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
13322 | bp->cnic_kwq_pending); |
13323 | ||
13324 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
13325 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
13326 | else | |
13327 | bp->cnic_kwq_prod++; | |
13328 | } | |
13329 | ||
13330 | spin_unlock_bh(&bp->spq_lock); | |
13331 | ||
13332 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
13333 | bnx2x_cnic_sp_post(bp, 0); | |
13334 | ||
13335 | return i; | |
13336 | } | |
13337 | ||
13338 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
13339 | { | |
13340 | struct cnic_ops *c_ops; | |
13341 | int rc = 0; | |
13342 | ||
13343 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
13344 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
13345 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
13346 | if (c_ops) |
13347 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
13348 | mutex_unlock(&bp->cnic_mutex); | |
13349 | ||
13350 | return rc; | |
13351 | } | |
13352 | ||
13353 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
13354 | { | |
13355 | struct cnic_ops *c_ops; | |
13356 | int rc = 0; | |
13357 | ||
13358 | rcu_read_lock(); | |
13359 | c_ops = rcu_dereference(bp->cnic_ops); | |
13360 | if (c_ops) | |
13361 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
13362 | rcu_read_unlock(); | |
13363 | ||
13364 | return rc; | |
13365 | } | |
13366 | ||
13367 | /* | |
13368 | * for commands that have no data | |
13369 | */ | |
9f6c9258 | 13370 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
13371 | { |
13372 | struct cnic_ctl_info ctl = {0}; | |
13373 | ||
13374 | ctl.cmd = cmd; | |
13375 | ||
13376 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
13377 | } | |
13378 | ||
619c5cb6 | 13379 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 13380 | { |
619c5cb6 | 13381 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
13382 | |
13383 | /* first we tell CNIC and only then we count this as a completion */ | |
13384 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
13385 | ctl.data.comp.cid = cid; | |
619c5cb6 | 13386 | ctl.data.comp.error = err; |
993ac7b5 MC |
13387 | |
13388 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 13389 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
13390 | } |
13391 | ||
619c5cb6 VZ |
13392 | /* Called with netif_addr_lock_bh() taken. |
13393 | * Sets an rx_mode config for an iSCSI ETH client. | |
13394 | * Doesn't block. | |
13395 | * Completion should be checked outside. | |
13396 | */ | |
13397 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
13398 | { | |
13399 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
13400 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
13401 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
13402 | ||
13403 | if (start) { | |
13404 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
13405 | * because it's the only way for UIO Queue to accept | |
13406 | * multicasts (in non-promiscuous mode only one Queue per | |
13407 | * function will receive multicast packets (leading in our | |
13408 | * case). | |
13409 | */ | |
13410 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
13411 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
13412 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
13413 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
13414 | ||
13415 | /* Clear STOP_PENDING bit if START is requested */ | |
13416 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
13417 | ||
13418 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
13419 | } else | |
13420 | /* Clear START_PENDING bit if STOP is requested */ | |
13421 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
13422 | ||
13423 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
13424 | set_bit(sched_state, &bp->sp_state); | |
13425 | else { | |
13426 | __set_bit(RAMROD_RX, &ramrod_flags); | |
13427 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
13428 | ramrod_flags); | |
13429 | } | |
13430 | } | |
13431 | ||
993ac7b5 MC |
13432 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
13433 | { | |
13434 | struct bnx2x *bp = netdev_priv(dev); | |
13435 | int rc = 0; | |
13436 | ||
13437 | switch (ctl->cmd) { | |
13438 | case DRV_CTL_CTXTBL_WR_CMD: { | |
13439 | u32 index = ctl->data.io.offset; | |
13440 | dma_addr_t addr = ctl->data.io.dma_addr; | |
13441 | ||
13442 | bnx2x_ilt_wr(bp, index, addr); | |
13443 | break; | |
13444 | } | |
13445 | ||
c2bff63f DK |
13446 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
13447 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
13448 | |
13449 | bnx2x_cnic_sp_post(bp, count); | |
13450 | break; | |
13451 | } | |
13452 | ||
13453 | /* rtnl_lock is held. */ | |
13454 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
13455 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
13456 | unsigned long sp_bits = 0; | |
13457 | ||
13458 | /* Configure the iSCSI classification object */ | |
13459 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
13460 | cp->iscsi_l2_client_id, | |
13461 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
13462 | bnx2x_sp(bp, mac_rdata), | |
13463 | bnx2x_sp_mapping(bp, mac_rdata), | |
13464 | BNX2X_FILTER_MAC_PENDING, | |
13465 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
13466 | &bp->macs_pool); | |
ec6ba945 | 13467 | |
523224a3 | 13468 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
13469 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
13470 | if (rc) | |
13471 | break; | |
523224a3 DK |
13472 | |
13473 | mmiowb(); | |
13474 | barrier(); | |
13475 | ||
619c5cb6 VZ |
13476 | /* Start accepting on iSCSI L2 ring */ |
13477 | ||
13478 | netif_addr_lock_bh(dev); | |
13479 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
13480 | netif_addr_unlock_bh(dev); | |
13481 | ||
13482 | /* bits to wait on */ | |
13483 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
13484 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
13485 | ||
13486 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
13487 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 13488 | |
993ac7b5 MC |
13489 | break; |
13490 | } | |
13491 | ||
13492 | /* rtnl_lock is held. */ | |
13493 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 13494 | unsigned long sp_bits = 0; |
993ac7b5 | 13495 | |
523224a3 | 13496 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
13497 | netif_addr_lock_bh(dev); |
13498 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
13499 | netif_addr_unlock_bh(dev); | |
13500 | ||
13501 | /* bits to wait on */ | |
13502 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
13503 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
13504 | ||
13505 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
13506 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
13507 | |
13508 | mmiowb(); | |
13509 | barrier(); | |
13510 | ||
13511 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
13512 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
13513 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
13514 | break; |
13515 | } | |
c2bff63f DK |
13516 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
13517 | int count = ctl->data.credit.credit_count; | |
13518 | ||
13519 | smp_mb__before_atomic_inc(); | |
6e30dd4e | 13520 | atomic_add(count, &bp->cq_spq_left); |
c2bff63f DK |
13521 | smp_mb__after_atomic_inc(); |
13522 | break; | |
13523 | } | |
1d187b34 | 13524 | case DRV_CTL_ULP_REGISTER_CMD: { |
2e499d3c | 13525 | int ulp_type = ctl->data.register_data.ulp_type; |
1d187b34 BW |
13526 | |
13527 | if (CHIP_IS_E3(bp)) { | |
13528 | int idx = BP_FW_MB_IDX(bp); | |
2e499d3c BW |
13529 | u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); |
13530 | int path = BP_PATH(bp); | |
13531 | int port = BP_PORT(bp); | |
13532 | int i; | |
13533 | u32 scratch_offset; | |
13534 | u32 *host_addr; | |
1d187b34 | 13535 | |
2e499d3c | 13536 | /* first write capability to shmem2 */ |
1d187b34 BW |
13537 | if (ulp_type == CNIC_ULP_ISCSI) |
13538 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
13539 | else if (ulp_type == CNIC_ULP_FCOE) | |
13540 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
13541 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
2e499d3c BW |
13542 | |
13543 | if ((ulp_type != CNIC_ULP_FCOE) || | |
13544 | (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || | |
13545 | (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) | |
13546 | break; | |
13547 | ||
13548 | /* if reached here - should write fcoe capabilities */ | |
13549 | scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); | |
13550 | if (!scratch_offset) | |
13551 | break; | |
13552 | scratch_offset += offsetof(struct glob_ncsi_oem_data, | |
13553 | fcoe_features[path][port]); | |
13554 | host_addr = (u32 *) &(ctl->data.register_data. | |
13555 | fcoe_features); | |
13556 | for (i = 0; i < sizeof(struct fcoe_capabilities); | |
13557 | i += 4) | |
13558 | REG_WR(bp, scratch_offset + i, | |
13559 | *(host_addr + i/4)); | |
1d187b34 BW |
13560 | } |
13561 | break; | |
13562 | } | |
2e499d3c | 13563 | |
1d187b34 BW |
13564 | case DRV_CTL_ULP_UNREGISTER_CMD: { |
13565 | int ulp_type = ctl->data.ulp_type; | |
13566 | ||
13567 | if (CHIP_IS_E3(bp)) { | |
13568 | int idx = BP_FW_MB_IDX(bp); | |
13569 | u32 cap; | |
13570 | ||
13571 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
13572 | if (ulp_type == CNIC_ULP_ISCSI) | |
13573 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
13574 | else if (ulp_type == CNIC_ULP_FCOE) | |
13575 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
13576 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
13577 | } | |
13578 | break; | |
13579 | } | |
993ac7b5 MC |
13580 | |
13581 | default: | |
13582 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
13583 | rc = -EINVAL; | |
13584 | } | |
13585 | ||
13586 | return rc; | |
13587 | } | |
13588 | ||
9f6c9258 | 13589 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
13590 | { |
13591 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13592 | ||
13593 | if (bp->flags & USING_MSIX_FLAG) { | |
13594 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
13595 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
13596 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
13597 | } else { | |
13598 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
13599 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
13600 | } | |
619c5cb6 | 13601 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
13602 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
13603 | else | |
13604 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
13605 | ||
619c5cb6 VZ |
13606 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
13607 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
13608 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
13609 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 13610 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
13611 | |
13612 | cp->num_irq = 2; | |
13613 | } | |
13614 | ||
37ae41a9 MS |
13615 | void bnx2x_setup_cnic_info(struct bnx2x *bp) |
13616 | { | |
13617 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13618 | ||
37ae41a9 MS |
13619 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
13620 | bnx2x_cid_ilt_lines(bp); | |
13621 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; | |
13622 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); | |
13623 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); | |
13624 | ||
13625 | if (NO_ISCSI_OOO(bp)) | |
13626 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
13627 | } | |
13628 | ||
993ac7b5 MC |
13629 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, |
13630 | void *data) | |
13631 | { | |
13632 | struct bnx2x *bp = netdev_priv(dev); | |
13633 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
55c11941 MS |
13634 | int rc; |
13635 | ||
13636 | DP(NETIF_MSG_IFUP, "Register_cnic called\n"); | |
993ac7b5 | 13637 | |
51c1a580 MS |
13638 | if (ops == NULL) { |
13639 | BNX2X_ERR("NULL ops received\n"); | |
993ac7b5 | 13640 | return -EINVAL; |
51c1a580 | 13641 | } |
993ac7b5 | 13642 | |
55c11941 MS |
13643 | if (!CNIC_SUPPORT(bp)) { |
13644 | BNX2X_ERR("Can't register CNIC when not supported\n"); | |
13645 | return -EOPNOTSUPP; | |
13646 | } | |
13647 | ||
13648 | if (!CNIC_LOADED(bp)) { | |
13649 | rc = bnx2x_load_cnic(bp); | |
13650 | if (rc) { | |
13651 | BNX2X_ERR("CNIC-related load failed\n"); | |
13652 | return rc; | |
13653 | } | |
55c11941 MS |
13654 | } |
13655 | ||
13656 | bp->cnic_enabled = true; | |
13657 | ||
993ac7b5 MC |
13658 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
13659 | if (!bp->cnic_kwq) | |
13660 | return -ENOMEM; | |
13661 | ||
13662 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
13663 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
13664 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
13665 | ||
13666 | bp->cnic_spq_pending = 0; | |
13667 | bp->cnic_kwq_pending = 0; | |
13668 | ||
13669 | bp->cnic_data = data; | |
13670 | ||
13671 | cp->num_irq = 0; | |
619c5cb6 | 13672 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 13673 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 13674 | |
993ac7b5 | 13675 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 13676 | |
993ac7b5 MC |
13677 | rcu_assign_pointer(bp->cnic_ops, ops); |
13678 | ||
13679 | return 0; | |
13680 | } | |
13681 | ||
13682 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
13683 | { | |
13684 | struct bnx2x *bp = netdev_priv(dev); | |
13685 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13686 | ||
13687 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 | 13688 | cp->drv_state = 0; |
2cfa5a04 | 13689 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
993ac7b5 MC |
13690 | mutex_unlock(&bp->cnic_mutex); |
13691 | synchronize_rcu(); | |
fea75645 | 13692 | bp->cnic_enabled = false; |
993ac7b5 MC |
13693 | kfree(bp->cnic_kwq); |
13694 | bp->cnic_kwq = NULL; | |
13695 | ||
13696 | return 0; | |
13697 | } | |
13698 | ||
13699 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) | |
13700 | { | |
13701 | struct bnx2x *bp = netdev_priv(dev); | |
13702 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13703 | ||
2ba45142 VZ |
13704 | /* If both iSCSI and FCoE are disabled - return NULL in |
13705 | * order to indicate CNIC that it should not try to work | |
13706 | * with this device. | |
13707 | */ | |
13708 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
13709 | return NULL; | |
13710 | ||
993ac7b5 MC |
13711 | cp->drv_owner = THIS_MODULE; |
13712 | cp->chip_id = CHIP_ID(bp); | |
13713 | cp->pdev = bp->pdev; | |
13714 | cp->io_base = bp->regview; | |
13715 | cp->io_base2 = bp->doorbells; | |
13716 | cp->max_kwqe_pending = 8; | |
523224a3 | 13717 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
13718 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
13719 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 13720 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 13721 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
13722 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
13723 | cp->drv_ctl = bnx2x_drv_ctl; | |
13724 | cp->drv_register_cnic = bnx2x_register_cnic; | |
13725 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
37ae41a9 | 13726 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); |
619c5cb6 VZ |
13727 | cp->iscsi_l2_client_id = |
13728 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
37ae41a9 | 13729 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); |
c2bff63f | 13730 | |
2ba45142 VZ |
13731 | if (NO_ISCSI_OOO(bp)) |
13732 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
13733 | ||
13734 | if (NO_ISCSI(bp)) | |
13735 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
13736 | ||
13737 | if (NO_FCOE(bp)) | |
13738 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
13739 | ||
51c1a580 MS |
13740 | BNX2X_DEV_INFO( |
13741 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", | |
c2bff63f DK |
13742 | cp->ctx_blk_size, |
13743 | cp->ctx_tbl_offset, | |
13744 | cp->ctx_tbl_len, | |
13745 | cp->starting_cid); | |
993ac7b5 MC |
13746 | return cp; |
13747 | } | |
993ac7b5 | 13748 | |
6411280a | 13749 | u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) |
9b176b6b | 13750 | { |
6411280a AE |
13751 | struct bnx2x *bp = fp->bp; |
13752 | u32 offset = BAR_USTRORM_INTMEM; | |
abc5a021 | 13753 | |
6411280a AE |
13754 | if (IS_VF(bp)) |
13755 | return bnx2x_vf_ustorm_prods_offset(bp, fp); | |
13756 | else if (!CHIP_IS_E1x(bp)) | |
13757 | offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); | |
13758 | else | |
13759 | offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); | |
8d9ac297 | 13760 | |
6411280a | 13761 | return offset; |
8d9ac297 | 13762 | } |
381ac16b | 13763 | |
6411280a AE |
13764 | /* called only on E1H or E2. |
13765 | * When pretending to be PF, the pretend value is the function number 0...7 | |
13766 | * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID | |
13767 | * combination | |
13768 | */ | |
13769 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) | |
381ac16b | 13770 | { |
6411280a | 13771 | u32 pretend_reg; |
381ac16b | 13772 | |
23826850 | 13773 | if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) |
6411280a | 13774 | return -1; |
381ac16b | 13775 | |
6411280a AE |
13776 | /* get my own pretend register */ |
13777 | pretend_reg = bnx2x_get_pretend_reg(bp); | |
13778 | REG_WR(bp, pretend_reg, pretend_func_val); | |
13779 | REG_RD(bp, pretend_reg); | |
381ac16b AE |
13780 | return 0; |
13781 | } |