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fou: fix IPv6 Kconfig options
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
4ad79e13 1/* bnx2x_main.c: QLogic Everest network driver.
a2fbb9ea 2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
4ad79e13
YM		 4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
a2fbb9ea
ET		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
08f6dd89 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
24e3fcef 12 * Written by: Eliezer Tamir
a2fbb9ea
ET		 13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 15 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 16 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 17 *
18 */
19
f1deab50
JP		 20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
a2fbb9ea
ET		 22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/kernel.h>
25#include <linux/device.h> /* for dev_info() */
26#include <linux/timer.h>
27#include <linux/errno.h>
28#include <linux/ioport.h>
29#include <linux/slab.h>
a2fbb9ea
ET		 30#include <linux/interrupt.h>
31#include <linux/pci.h>
33d8e6a5 32#include <linux/aer.h>
a2fbb9ea
ET		 33#include <linux/init.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/dma-mapping.h>
38#include <linux/bitops.h>
39#include <linux/irq.h>
40#include <linux/delay.h>
41#include <asm/byteorder.h>
42#include <linux/time.h>
43#include <linux/ethtool.h>
44#include <linux/mii.h>
0c6671b0 45#include <linux/if_vlan.h>
c9931896 46#include <linux/crash_dump.h>
a2fbb9ea 47#include <net/ip.h>
619c5cb6 48#include <net/ipv6.h>
a2fbb9ea 49#include <net/tcp.h>
51de7bb9 50#include <net/vxlan.h>
a2fbb9ea 51#include <net/checksum.h>
34f80b04 52#include <net/ip6_checksum.h>
a2fbb9ea
ET		 53#include <linux/workqueue.h>
54#include <linux/crc32.h>
34f80b04 55#include <linux/crc32c.h>
a2fbb9ea
ET		 56#include <linux/prefetch.h>
57#include <linux/zlib.h>
a2fbb9ea 58#include <linux/io.h>
452427b0 59#include <linux/semaphore.h>
45229b42 60#include <linux/stringify.h>
7ab24bfd 61#include <linux/vmalloc.h>
4fee7dab 62#if IS_ENABLED(CONFIG_BNX2X_GENEVE)
883ce97d
YM		 63#include <net/geneve.h>
64#endif
a2fbb9ea
ET		 65#include "bnx2x.h"
66#include "bnx2x_init.h"
94a78b79 67#include "bnx2x_init_ops.h"
9f6c9258 68#include "bnx2x_cmn.h"
1ab4434c 69#include "bnx2x_vfpf.h"
e4901dde 70#include "bnx2x_dcb.h"
042181f5 71#include "bnx2x_sp.h"
94a78b79
VZ		 72#include <linux/firmware.h>
73#include "bnx2x_fw_file_hdr.h"
74/* FW files */
45229b42
BH		 75#define FW_FILE_VERSION \
76 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
77 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
78 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
79 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 80#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
81#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 82#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 83
34f80b04
EG		 84/* Time in jiffies before concluding the transmitter is hung */
85#define TX_TIMEOUT (5*HZ)
a2fbb9ea 86
0329aba1 87static char version[] =
4ad79e13 88 "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 89 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
90
24e3fcef 91MODULE_AUTHOR("Eliezer Tamir");
4ad79e13 92MODULE_DESCRIPTION("QLogic "
619c5cb6
VZ		 93 "BCM57710/57711/57711E/"
94 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
95 "57840/57840_MF Driver");
a2fbb9ea
ET		 96MODULE_LICENSE("GPL");
97MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 98MODULE_FIRMWARE(FW_FILE_NAME_E1);
99MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 100MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 101
a8f47eb7 102int bnx2x_num_queues;
1c8bb760 103module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
96305234
DK		 104MODULE_PARM_DESC(num_queues,
105 " Set number of queues (default is as a number of CPUs)");
555f6c78 106
19680c48 107static int disable_tpa;
1c8bb760 108module_param(disable_tpa, int, S_IRUGO);
9898f86d 109MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 110
a8f47eb7 111static int int_mode;
1c8bb760 112module_param(int_mode, int, S_IRUGO);
619c5cb6 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 114 "(1 INT#x; 2 MSI)");
8badd27a 115
a18f5128 116static int dropless_fc;
1c8bb760 117module_param(dropless_fc, int, S_IRUGO);
a18f5128
EG		 118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
119
8d5726c4 120static int mrrs = -1;
1c8bb760 121module_param(mrrs, int, S_IRUGO);
8d5726c4
EG		 122MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
123
9898f86d 124static int debug;
1c8bb760 125module_param(debug, int, S_IRUGO);
9898f86d
EG		 126MODULE_PARM_DESC(debug, " Default debug msglevel");
127
370d4a26
YM		 128static struct workqueue_struct *bnx2x_wq;
129struct workqueue_struct *bnx2x_iov_wq;
ec6ba945 130
1ef1d45a
BW		 131struct bnx2x_mac_vals {
132 u32 xmac_addr;
133 u32 xmac_val;
134 u32 emac_addr;
135 u32 emac_val;
3d6b7253
YM		 136 u32 umac_addr[2];
137 u32 umac_val[2];
1ef1d45a
BW		 138 u32 bmac_addr;
139 u32 bmac_val[2];
140};
141
a2fbb9ea
ET		 142enum bnx2x_board_type {
143 BCM57710 = 0,
619c5cb6
VZ		 144 BCM57711,
145 BCM57711E,
146 BCM57712,
147 BCM57712_MF,
1ab4434c 148 BCM57712_VF,
619c5cb6
VZ		 149 BCM57800,
150 BCM57800_MF,
1ab4434c 151 BCM57800_VF,
619c5cb6
VZ		 152 BCM57810,
153 BCM57810_MF,
1ab4434c 154 BCM57810_VF,
c3def943
YM		 155 BCM57840_4_10,
156 BCM57840_2_20,
7e8e02df 157 BCM57840_MF,
1ab4434c 158 BCM57840_VF,
7e8e02df 159 BCM57811,
1ab4434c
AE		 160 BCM57811_MF,
161 BCM57840_O,
162 BCM57840_MFO,
163 BCM57811_VF
a2fbb9ea
ET		 164};
165
34f80b04 166/* indexed by board_type, above */
53a10565 167static struct {
a2fbb9ea 168 char *name;
0329aba1 169} board_info[] = {
4ad79e13
YM		 170 [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
171 [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" },
172 [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" },
173 [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" },
174 [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
175 [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
176 [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" },
177 [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
178 [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
179 [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" },
180 [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
181 [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
182 [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
183 [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
184 [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
185 [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
186 [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" },
187 [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
188 [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
189 [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
190 [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 191};
192
619c5cb6
VZ		 193#ifndef PCI_DEVICE_ID_NX2_57710
194#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
195#endif
196#ifndef PCI_DEVICE_ID_NX2_57711
197#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
198#endif
199#ifndef PCI_DEVICE_ID_NX2_57711E
200#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
201#endif
202#ifndef PCI_DEVICE_ID_NX2_57712
203#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
204#endif
205#ifndef PCI_DEVICE_ID_NX2_57712_MF
206#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
207#endif
8395be5e
AE		 208#ifndef PCI_DEVICE_ID_NX2_57712_VF
209#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
210#endif
619c5cb6
VZ		 211#ifndef PCI_DEVICE_ID_NX2_57800
212#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
213#endif
214#ifndef PCI_DEVICE_ID_NX2_57800_MF
215#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
216#endif
8395be5e
AE		 217#ifndef PCI_DEVICE_ID_NX2_57800_VF
218#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
219#endif
619c5cb6
VZ		 220#ifndef PCI_DEVICE_ID_NX2_57810
221#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
222#endif
223#ifndef PCI_DEVICE_ID_NX2_57810_MF
224#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
225#endif
c3def943
YM		 226#ifndef PCI_DEVICE_ID_NX2_57840_O
227#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
228#endif
8395be5e
AE		 229#ifndef PCI_DEVICE_ID_NX2_57810_VF
230#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
231#endif
c3def943
YM		 232#ifndef PCI_DEVICE_ID_NX2_57840_4_10
233#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
234#endif
235#ifndef PCI_DEVICE_ID_NX2_57840_2_20
236#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
237#endif
238#ifndef PCI_DEVICE_ID_NX2_57840_MFO
239#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 240#endif
241#ifndef PCI_DEVICE_ID_NX2_57840_MF
242#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
243#endif
8395be5e
AE		 244#ifndef PCI_DEVICE_ID_NX2_57840_VF
245#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
246#endif
7e8e02df
BW		 247#ifndef PCI_DEVICE_ID_NX2_57811
248#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
249#endif
250#ifndef PCI_DEVICE_ID_NX2_57811_MF
251#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
252#endif
8395be5e
AE		 253#ifndef PCI_DEVICE_ID_NX2_57811_VF
254#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
255#endif
256
9baa3c34 257static const struct pci_device_id bnx2x_pci_tbl[] = {
e4ed7113
EG		 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6 262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
8395be5e 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
619c5cb6
VZ		 264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
8395be5e 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
619c5cb6
VZ		 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
9c9a6524 271 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
c3def943 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
8395be5e 273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
c3def943 274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 275 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
9c9a6524 276 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
8395be5e 277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
9c9a6524 278 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
7e8e02df
BW		 279 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
280 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
8395be5e 281 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
a2fbb9ea
ET		 282 { 0 }
283};
284
285MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
286
452427b0
YM		 287/* Global resources for unloading a previously loaded device */
288#define BNX2X_PREV_WAIT_NEEDED 1
289static DEFINE_SEMAPHORE(bnx2x_prev_sem);
290static LIST_HEAD(bnx2x_prev_list);
a8f47eb7 291
292/* Forward declaration */
293static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
294static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
295static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
296
a2fbb9ea
ET		 297/****************************************************************************
298* General service functions
299****************************************************************************/
300
eeed018c
MK		 301static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
302
1191cb83 303static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 304 u32 addr, dma_addr_t mapping)
305{
306 REG_WR(bp, addr, U64_LO(mapping));
307 REG_WR(bp, addr + 4, U64_HI(mapping));
308}
309
1191cb83
ED		 310static void storm_memset_spq_addr(struct bnx2x *bp,
311 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 312{
313 u32 addr = XSEM_REG_FAST_MEMORY +
314 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
315
316 __storm_memset_dma_mapping(bp, addr, mapping);
317}
318
1191cb83
ED		 319static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
320 u16 pf_id)
523224a3 321{
619c5cb6
VZ		 322 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
323 pf_id);
324 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
325 pf_id);
326 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
327 pf_id);
328 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
329 pf_id);
523224a3
DK		 330}
331
1191cb83
ED		 332static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
333 u8 enable)
619c5cb6
VZ		 334{
335 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
336 enable);
337 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
338 enable);
339 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
340 enable);
341 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
342 enable);
343}
523224a3 344
1191cb83
ED		 345static void storm_memset_eq_data(struct bnx2x *bp,
346 struct event_ring_data *eq_data,
523224a3
DK		 347 u16 pfid)
348{
349 size_t size = sizeof(struct event_ring_data);
350
351 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
352
353 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
354}
355
1191cb83
ED		 356static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
357 u16 pfid)
523224a3
DK		 358{
359 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
360 REG_WR16(bp, addr, eq_prod);
361}
362
a2fbb9ea
ET		 363/* used only at init
364 * locking is done by mcp
365 */
8d96286a 366static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 367{
368 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
369 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
370 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
371 PCICFG_VENDOR_ID_OFFSET);
372}
373
a2fbb9ea
ET		 374static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
375{
376 u32 val;
377
378 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
379 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
380 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
381 PCICFG_VENDOR_ID_OFFSET);
382
383 return val;
384}
a2fbb9ea 385
f2e0899f
DK		 386#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
387#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
388#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
389#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
390#define DMAE_DP_DST_NONE "dst_addr [none]"
391
6bf07b8e
YM		 392static void bnx2x_dp_dmae(struct bnx2x *bp,
393 struct dmae_command *dmae, int msglvl)
fd1fc79d
AE		 394{
395 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
6bf07b8e 396 int i;
fd1fc79d
AE		 397
398 switch (dmae->opcode & DMAE_COMMAND_DST) {
399 case DMAE_CMD_DST_PCI:
400 if (src_type == DMAE_CMD_SRC_PCI)
401 DP(msglvl, "DMAE: opcode 0x%08x\n"
402 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
403 "comp_addr [%x:%08x], comp_val 0x%08x\n",
404 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
405 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
406 dmae->comp_addr_hi, dmae->comp_addr_lo,
407 dmae->comp_val);
408 else
409 DP(msglvl, "DMAE: opcode 0x%08x\n"
410 "src [%08x], len [%d*4], dst [%x:%08x]\n"
411 "comp_addr [%x:%08x], comp_val 0x%08x\n",
412 dmae->opcode, dmae->src_addr_lo >> 2,
413 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
414 dmae->comp_addr_hi, dmae->comp_addr_lo,
415 dmae->comp_val);
416 break;
417 case DMAE_CMD_DST_GRC:
418 if (src_type == DMAE_CMD_SRC_PCI)
419 DP(msglvl, "DMAE: opcode 0x%08x\n"
420 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
421 "comp_addr [%x:%08x], comp_val 0x%08x\n",
422 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
423 dmae->len, dmae->dst_addr_lo >> 2,
424 dmae->comp_addr_hi, dmae->comp_addr_lo,
425 dmae->comp_val);
426 else
427 DP(msglvl, "DMAE: opcode 0x%08x\n"
428 "src [%08x], len [%d*4], dst [%08x]\n"
429 "comp_addr [%x:%08x], comp_val 0x%08x\n",
430 dmae->opcode, dmae->src_addr_lo >> 2,
431 dmae->len, dmae->dst_addr_lo >> 2,
432 dmae->comp_addr_hi, dmae->comp_addr_lo,
433 dmae->comp_val);
434 break;
435 default:
436 if (src_type == DMAE_CMD_SRC_PCI)
437 DP(msglvl, "DMAE: opcode 0x%08x\n"
438 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
439 "comp_addr [%x:%08x] comp_val 0x%08x\n",
440 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
441 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
442 dmae->comp_val);
443 else
444 DP(msglvl, "DMAE: opcode 0x%08x\n"
445 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
446 "comp_addr [%x:%08x] comp_val 0x%08x\n",
447 dmae->opcode, dmae->src_addr_lo >> 2,
448 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
449 dmae->comp_val);
450 break;
451 }
6bf07b8e
YM		 452
453 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
454 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
455 i, *(((u32 *)dmae) + i));
fd1fc79d 456}
f2e0899f 457
a2fbb9ea 458/* copy command into DMAE command memory and set DMAE command go */
6c719d00 459void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 460{
461 u32 cmd_offset;
462 int i;
463
464 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
465 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
466 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 467 }
468 REG_WR(bp, dmae_reg_go_c[idx], 1);
469}
470
f2e0899f 471u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 472{
f2e0899f
DK		 473 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
474 DMAE_CMD_C_ENABLE);
475}
ad8d3948 476
f2e0899f
DK		 477u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
478{
479 return opcode & ~DMAE_CMD_SRC_RESET;
480}
ad8d3948 481
f2e0899f
DK		 482u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
483 bool with_comp, u8 comp_type)
484{
485 u32 opcode = 0;
486
487 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
488 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 489
f2e0899f
DK		 490 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
491
492 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 493 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
494 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 495 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 496
a2fbb9ea 497#ifdef __BIG_ENDIAN
f2e0899f 498 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 499#else
f2e0899f 500 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 501#endif
f2e0899f
DK		 502 if (with_comp)
503 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
504 return opcode;
505}
506
fd1fc79d 507void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 508 struct dmae_command *dmae,
509 u8 src_type, u8 dst_type)
f2e0899f
DK		 510{
511 memset(dmae, 0, sizeof(struct dmae_command));
512
513 /* set the opcode */
514 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
515 true, DMAE_COMP_PCI);
516
517 /* fill in the completion parameters */
518 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
519 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
520 dmae->comp_val = DMAE_COMP_VAL;
521}
522
fd1fc79d 523/* issue a dmae command over the init-channel and wait for completion */
32316a46
AE		 524int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
525 u32 *comp)
f2e0899f 526{
5e374b5a 527 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 528 int rc = 0;
529
6bf07b8e
YM		 530 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
531
532 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
619c5cb6
VZ		 533 * as long as this code is called both from syscall context and
534 * from ndo_set_rx_mode() flow that may be called from BH.
535 */
eeed018c 536
6e30dd4e 537 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 538
f2e0899f 539 /* reset completion */
32316a46 540 *comp = 0;
a2fbb9ea 541
f2e0899f
DK		 542 /* post the command on the channel used for initializations */
543 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 544
f2e0899f 545 /* wait for completion */
a2fbb9ea 546 udelay(5);
32316a46 547 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 548
95c6c616
AE		 549 if (!cnt ||
550 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
551 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 552 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 553 rc = DMAE_TIMEOUT;
554 goto unlock;
a2fbb9ea 555 }
ad8d3948 556 cnt--;
f2e0899f 557 udelay(50);
a2fbb9ea 558 }
32316a46 559 if (*comp & DMAE_PCI_ERR_FLAG) {
f2e0899f
DK		 560 BNX2X_ERR("DMAE PCI error!\n");
561 rc = DMAE_PCI_ERROR;
562 }
563
f2e0899f 564unlock:
eeed018c 565
6e30dd4e 566 spin_unlock_bh(&bp->dmae_lock);
eeed018c 567
f2e0899f
DK		 568 return rc;
569}
570
571void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
572 u32 len32)
573{
6bf07b8e 574 int rc;
f2e0899f
DK		 575 struct dmae_command dmae;
576
577 if (!bp->dmae_ready) {
578 u32 *data = bnx2x_sp(bp, wb_data[0]);
579
127a425e
AE		 580 if (CHIP_IS_E1(bp))
581 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
582 else
583 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 584 return;
585 }
586
587 /* set opcode and fixed command fields */
588 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
589
590 /* fill in addresses and len */
591 dmae.src_addr_lo = U64_LO(dma_addr);
592 dmae.src_addr_hi = U64_HI(dma_addr);
593 dmae.dst_addr_lo = dst_addr >> 2;
594 dmae.dst_addr_hi = 0;
595 dmae.len = len32;
596
f2e0899f 597 /* issue the command and wait for completion */
32316a46 598 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 599 if (rc) {
600 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 601#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 602 bnx2x_panic();
9dcd9acd 603#endif
6bf07b8e 604 }
a2fbb9ea
ET		 605}
606
c18487ee 607void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 608{
6bf07b8e 609 int rc;
5ff7b6d4 610 struct dmae_command dmae;
ad8d3948
EG		 611
612 if (!bp->dmae_ready) {
613 u32 *data = bnx2x_sp(bp, wb_data[0]);
614 int i;
615
51c1a580 616 if (CHIP_IS_E1(bp))
127a425e
AE		 617 for (i = 0; i < len32; i++)
618 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 619 else
127a425e
AE		 620 for (i = 0; i < len32; i++)
621 data[i] = REG_RD(bp, src_addr + i*4);
622
ad8d3948
EG		 623 return;
624 }
625
f2e0899f
DK		 626 /* set opcode and fixed command fields */
627 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 628
f2e0899f 629 /* fill in addresses and len */
5ff7b6d4
EG		 630 dmae.src_addr_lo = src_addr >> 2;
631 dmae.src_addr_hi = 0;
632 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
633 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
634 dmae.len = len32;
ad8d3948 635
f2e0899f 636 /* issue the command and wait for completion */
32316a46 637 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 638 if (rc) {
639 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 640#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 641 bnx2x_panic();
9dcd9acd 642#endif
c957d09f 643 }
ad8d3948
EG		 644}
645
8d96286a 646static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
647 u32 addr, u32 len)
573f2035 648{
02e3c6cb 649 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 650 int offset = 0;
651
02e3c6cb 652 while (len > dmae_wr_max) {
573f2035 653 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 654 addr + offset, dmae_wr_max);
655 offset += dmae_wr_max * 4;
656 len -= dmae_wr_max;
573f2035
EG		 657 }
658
659 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
660}
661
97539f1e
AE		 662enum storms {
663 XSTORM,
664 TSTORM,
665 CSTORM,
666 USTORM,
667 MAX_STORMS
668};
34f80b04 669
97539f1e
AE		 670#define STORMS_NUM 4
671#define REGS_IN_ENTRY 4
34f80b04 672
97539f1e
AE		 673static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
674 enum storms storm,
675 int entry)
676{
677 switch (storm) {
678 case XSTORM:
679 return XSTORM_ASSERT_LIST_OFFSET(entry);
680 case TSTORM:
681 return TSTORM_ASSERT_LIST_OFFSET(entry);
682 case CSTORM:
683 return CSTORM_ASSERT_LIST_OFFSET(entry);
684 case USTORM:
685 return USTORM_ASSERT_LIST_OFFSET(entry);
686 case MAX_STORMS:
687 default:
688 BNX2X_ERR("unknown storm\n");
34f80b04 689 }
97539f1e
AE		 690 return -EINVAL;
691}
34f80b04 692
97539f1e
AE		 693static int bnx2x_mc_assert(struct bnx2x *bp)
694{
695 char last_idx;
696 int i, j, rc = 0;
697 enum storms storm;
698 u32 regs[REGS_IN_ENTRY];
699 u32 bar_storm_intmem[STORMS_NUM] = {
700 BAR_XSTRORM_INTMEM,
701 BAR_TSTRORM_INTMEM,
702 BAR_CSTRORM_INTMEM,
703 BAR_USTRORM_INTMEM
704 };
705 u32 storm_assert_list_index[STORMS_NUM] = {
706 XSTORM_ASSERT_LIST_INDEX_OFFSET,
707 TSTORM_ASSERT_LIST_INDEX_OFFSET,
708 CSTORM_ASSERT_LIST_INDEX_OFFSET,
709 USTORM_ASSERT_LIST_INDEX_OFFSET
710 };
711 char *storms_string[STORMS_NUM] = {
712 "XSTORM",
713 "TSTORM",
714 "CSTORM",
715 "USTORM"
716 };
717
718 for (storm = XSTORM; storm < MAX_STORMS; storm++) {
719 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
720 storm_assert_list_index[storm]);
721 if (last_idx)
722 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
723 storms_string[storm], last_idx);
724
725 /* print the asserts */
726 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
727 /* read a single assert entry */
728 for (j = 0; j < REGS_IN_ENTRY; j++)
729 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
730 bnx2x_get_assert_list_entry(bp,
731 storm,
732 i) +
733 sizeof(u32) * j);
734
735 /* log entry if it contains a valid assert */
736 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
737 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
738 storms_string[storm], i, regs[3],
739 regs[2], regs[1], regs[0]);
740 rc++;
741 } else {
742 break;
743 }
a2fbb9ea
ET		 744 }
745 }
34f80b04 746
97539f1e
AE		 747 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
748 CHIP_IS_E1(bp) ? "everest1" :
749 CHIP_IS_E1H(bp) ? "everest1h" :
750 CHIP_IS_E2(bp) ? "everest2" : "everest3",
751 BCM_5710_FW_MAJOR_VERSION,
752 BCM_5710_FW_MINOR_VERSION,
753 BCM_5710_FW_REVISION_VERSION);
754
a2fbb9ea
ET		 755 return rc;
756}
c14423fe 757
1a6974b2
YM		 758#define MCPR_TRACE_BUFFER_SIZE (0x800)
759#define SCRATCH_BUFFER_SIZE(bp) \
760 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
761
7a25cc73 762void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 763{
7a25cc73 764 u32 addr, val;
a2fbb9ea 765 u32 mark, offset;
4781bfad 766 __be32 data[9];
a2fbb9ea 767 int word;
f2e0899f 768 u32 trace_shmem_base;
2145a920
VZ		 769 if (BP_NOMCP(bp)) {
770 BNX2X_ERR("NO MCP - can not dump\n");
771 return;
772 }
7a25cc73
DK		 773 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
774 (bp->common.bc_ver & 0xff0000) >> 16,
775 (bp->common.bc_ver & 0xff00) >> 8,
776 (bp->common.bc_ver & 0xff));
777
778 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
779 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 780 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 781
f2e0899f
DK		 782 if (BP_PATH(bp) == 0)
783 trace_shmem_base = bp->common.shmem_base;
784 else
785 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
1a6974b2
YM		 786
787 /* sanity */
788 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
789 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
790 SCRATCH_BUFFER_SIZE(bp)) {
791 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
792 trace_shmem_base);
793 return;
794 }
795
796 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
de128804
DK		 797
798 /* validate TRCB signature */
799 mark = REG_RD(bp, addr);
800 if (mark != MFW_TRACE_SIGNATURE) {
801 BNX2X_ERR("Trace buffer signature is missing.");
802 return ;
803 }
804
805 /* read cyclic buffer pointer */
806 addr += 4;
cdaa7cb8 807 mark = REG_RD(bp, addr);
1a6974b2
YM		 808 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
809 if (mark >= trace_shmem_base || mark < addr + 4) {
810 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
811 return;
812 }
7a25cc73 813 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 814
7a25cc73 815 printk("%s", lvl);
2de67439
YM		 816
817 /* dump buffer after the mark */
1a6974b2 818 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 819 for (word = 0; word < 8; word++)
cdaa7cb8 820 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 821 data[8] = 0x0;
7995c64e 822 pr_cont("%s", (char *)data);
a2fbb9ea 823 }
2de67439
YM		 824
825 /* dump buffer before the mark */
cdaa7cb8 826 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 827 for (word = 0; word < 8; word++)
cdaa7cb8 828 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 829 data[8] = 0x0;
7995c64e 830 pr_cont("%s", (char *)data);
a2fbb9ea 831 }
7a25cc73
DK		 832 printk("%s" "end of fw dump\n", lvl);
833}
834
1191cb83 835static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 836{
837 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 838}
839
823e1d90
YM		 840static void bnx2x_hc_int_disable(struct bnx2x *bp)
841{
842 int port = BP_PORT(bp);
843 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
844 u32 val = REG_RD(bp, addr);
845
846 /* in E1 we must use only PCI configuration space to disable
16a5fd92
YM		 847 * MSI/MSIX capability
848 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
823e1d90
YM		 849 */
850 if (CHIP_IS_E1(bp)) {
851 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
852 * Use mask register to prevent from HC sending interrupts
853 * after we exit the function
854 */
855 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
856
857 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
858 HC_CONFIG_0_REG_INT_LINE_EN_0 |
859 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
860 } else
861 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
862 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
863 HC_CONFIG_0_REG_INT_LINE_EN_0 |
864 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
865
866 DP(NETIF_MSG_IFDOWN,
867 "write %x to HC %d (addr 0x%x)\n",
868 val, port, addr);
869
870 /* flush all outstanding writes */
871 mmiowb();
872
873 REG_WR(bp, addr, val);
874 if (REG_RD(bp, addr) != val)
6bf07b8e 875 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 876}
877
878static void bnx2x_igu_int_disable(struct bnx2x *bp)
879{
880 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
881
882 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
883 IGU_PF_CONF_INT_LINE_EN |
884 IGU_PF_CONF_ATTN_BIT_EN);
885
886 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
887
888 /* flush all outstanding writes */
889 mmiowb();
890
891 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
892 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
6bf07b8e 893 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 894}
895
896static void bnx2x_int_disable(struct bnx2x *bp)
897{
898 if (bp->common.int_block == INT_BLOCK_HC)
899 bnx2x_hc_int_disable(bp);
900 else
901 bnx2x_igu_int_disable(bp);
902}
903
904void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
a2fbb9ea
ET		 905{
906 int i;
523224a3
DK		 907 u16 j;
908 struct hc_sp_status_block_data sp_sb_data;
909 int func = BP_FUNC(bp);
910#ifdef BNX2X_STOP_ON_ERROR
911 u16 start = 0, end = 0;
6383c0b3 912 u8 cos;
523224a3 913#endif
0155a27c 914 if (IS_PF(bp) && disable_int)
823e1d90 915 bnx2x_int_disable(bp);
a2fbb9ea 916
66e855f3 917 bp->stats_state = STATS_STATE_DISABLED;
7a752993 918 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 919 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
920
a2fbb9ea
ET		 921 BNX2X_ERR("begin crash dump -----------------\n");
922
8440d2b6
EG		 923 /* Indices */
924 /* Common */
0155a27c
YM		 925 if (IS_PF(bp)) {
926 struct host_sp_status_block *def_sb = bp->def_status_blk;
927 int data_size, cstorm_offset;
928
929 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
930 bp->def_idx, bp->def_att_idx, bp->attn_state,
931 bp->spq_prod_idx, bp->stats_counter);
932 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
933 def_sb->atten_status_block.attn_bits,
934 def_sb->atten_status_block.attn_bits_ack,
935 def_sb->atten_status_block.status_block_id,
936 def_sb->atten_status_block.attn_bits_index);
937 BNX2X_ERR(" def (");
938 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
939 pr_cont("0x%x%s",
940 def_sb->sp_sb.index_values[i],
941 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
942
943 data_size = sizeof(struct hc_sp_status_block_data) /
944 sizeof(u32);
945 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
946 for (i = 0; i < data_size; i++)
947 *((u32 *)&sp_sb_data + i) =
948 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
949 i * sizeof(u32));
950
951 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
952 sp_sb_data.igu_sb_id,
953 sp_sb_data.igu_seg_id,
954 sp_sb_data.p_func.pf_id,
955 sp_sb_data.p_func.vnic_id,
956 sp_sb_data.p_func.vf_id,
957 sp_sb_data.p_func.vf_valid,
958 sp_sb_data.state);
959 }
523224a3 960
ec6ba945 961 for_each_eth_queue(bp, i) {
a2fbb9ea 962 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 963 int loop;
f2e0899f 964 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 965 struct hc_status_block_data_e1x sb_data_e1x;
966 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 967 CHIP_IS_E1x(bp) ?
968 sb_data_e1x.common.state_machine :
969 sb_data_e2.common.state_machine;
523224a3 970 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 971 CHIP_IS_E1x(bp) ?
972 sb_data_e1x.index_data :
973 sb_data_e2.index_data;
6383c0b3 974 u8 data_size, cos;
523224a3 975 u32 *sb_data_p;
6383c0b3 976 struct bnx2x_fp_txdata txdata;
523224a3 977
e2611998
YM		 978 if (!bp->fp)
979 break;
980
981 if (!fp->rx_cons_sb)
982 continue;
983
523224a3 984 /* Rx */
51c1a580 985 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 986 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 987 fp->rx_comp_prod,
66e855f3 988 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 989 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 990 fp->rx_sge_prod, fp->last_max_sge,
523224a3 991 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 992
523224a3 993 /* Tx */
6383c0b3
AE		 994 for_each_cos_in_tx_queue(fp, cos)
995 {
1fc3de94 996 if (!fp->txdata_ptr[cos])
e2611998
YM		 997 break;
998
65565884 999 txdata = *fp->txdata_ptr[cos];
e2611998
YM		 1000
1001 if (!txdata.tx_cons_sb)
1002 continue;
1003
51c1a580 1004 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 1005 i, txdata.tx_pkt_prod,
1006 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1007 txdata.tx_bd_cons,
1008 le16_to_cpu(*txdata.tx_cons_sb));
1009 }
523224a3 1010
619c5cb6
VZ		 1011 loop = CHIP_IS_E1x(bp) ?
1012 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 1013
1014 /* host sb data */
1015
ec6ba945
VZ		 1016 if (IS_FCOE_FP(fp))
1017 continue;
55c11941 1018
523224a3
DK		 1019 BNX2X_ERR(" run indexes (");
1020 for (j = 0; j < HC_SB_MAX_SM; j++)
1021 pr_cont("0x%x%s",
1022 fp->sb_running_index[j],
1023 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1024
1025 BNX2X_ERR(" indexes (");
1026 for (j = 0; j < loop; j++)
1027 pr_cont("0x%x%s",
1028 fp->sb_index_values[j],
1029 (j == loop - 1) ? ")" : " ");
0155a27c
YM		 1030
1031 /* VF cannot access FW refelection for status block */
1032 if (IS_VF(bp))
1033 continue;
1034
523224a3 1035 /* fw sb data */
619c5cb6
VZ		 1036 data_size = CHIP_IS_E1x(bp) ?
1037 sizeof(struct hc_status_block_data_e1x) :
1038 sizeof(struct hc_status_block_data_e2);
523224a3 1039 data_size /= sizeof(u32);
619c5cb6
VZ		 1040 sb_data_p = CHIP_IS_E1x(bp) ?
1041 (u32 *)&sb_data_e1x :
1042 (u32 *)&sb_data_e2;
523224a3
DK		 1043 /* copy sb data in here */
1044 for (j = 0; j < data_size; j++)
1045 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1046 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1047 j * sizeof(u32));
1048
619c5cb6 1049 if (!CHIP_IS_E1x(bp)) {
51c1a580 1050 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1051 sb_data_e2.common.p_func.pf_id,
1052 sb_data_e2.common.p_func.vf_id,
1053 sb_data_e2.common.p_func.vf_valid,
1054 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 1055 sb_data_e2.common.same_igu_sb_1b,
1056 sb_data_e2.common.state);
f2e0899f 1057 } else {
51c1a580 1058 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1059 sb_data_e1x.common.p_func.pf_id,
1060 sb_data_e1x.common.p_func.vf_id,
1061 sb_data_e1x.common.p_func.vf_valid,
1062 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 1063 sb_data_e1x.common.same_igu_sb_1b,
1064 sb_data_e1x.common.state);
f2e0899f 1065 }
523224a3
DK		 1066
1067 /* SB_SMs data */
1068 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 1069 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1070 j, hc_sm_p[j].__flags,
1071 hc_sm_p[j].igu_sb_id,
1072 hc_sm_p[j].igu_seg_id,
1073 hc_sm_p[j].time_to_expire,
1074 hc_sm_p[j].timer_value);
523224a3
DK		 1075 }
1076
16a5fd92 1077 /* Indices data */
523224a3 1078 for (j = 0; j < loop; j++) {
51c1a580 1079 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 1080 hc_index_p[j].flags,
1081 hc_index_p[j].timeout);
1082 }
8440d2b6 1083 }
a2fbb9ea 1084
523224a3 1085#ifdef BNX2X_STOP_ON_ERROR
0155a27c
YM		 1086 if (IS_PF(bp)) {
1087 /* event queue */
1088 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1089 for (i = 0; i < NUM_EQ_DESC; i++) {
1090 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1091
1092 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1093 i, bp->eq_ring[i].message.opcode,
1094 bp->eq_ring[i].message.error);
1095 BNX2X_ERR("data: %x %x %x\n",
1096 data[0], data[1], data[2]);
1097 }
04c46736
YM		 1098 }
1099
8440d2b6
EG		 1100 /* Rings */
1101 /* Rx */
55c11941 1102 for_each_valid_rx_queue(bp, i) {
8440d2b6 1103 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1104
e2611998
YM		 1105 if (!bp->fp)
1106 break;
1107
1108 if (!fp->rx_cons_sb)
1109 continue;
1110
a2fbb9ea
ET		 1111 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1112 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1113 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1114 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1115 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1116
c3eefaf6 1117 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 1118 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 1119 }
1120
3196a88a
EG		 1121 start = RX_SGE(fp->rx_sge_prod);
1122 end = RX_SGE(fp->last_max_sge);
8440d2b6 1123 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1124 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1125 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1126
c3eefaf6
EG		 1127 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1128 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1129 }
1130
a2fbb9ea
ET		 1131 start = RCQ_BD(fp->rx_comp_cons - 10);
1132 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1133 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1134 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1135
c3eefaf6
EG		 1136 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1137 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1138 }
1139 }
1140
8440d2b6 1141 /* Tx */
55c11941 1142 for_each_valid_tx_queue(bp, i) {
8440d2b6 1143 struct bnx2x_fastpath *fp = &bp->fp[i];
e2611998
YM		 1144
1145 if (!bp->fp)
1146 break;
1147
6383c0b3 1148 for_each_cos_in_tx_queue(fp, cos) {
65565884 1149 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3 1150
1fc3de94 1151 if (!fp->txdata_ptr[cos])
e2611998
YM		 1152 break;
1153
ea36475a 1154 if (!txdata->tx_cons_sb)
e2611998
YM		 1155 continue;
1156
6383c0b3
AE		 1157 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1158 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1159 for (j = start; j != end; j = TX_BD(j + 1)) {
1160 struct sw_tx_bd *sw_bd =
1161 &txdata->tx_buf_ring[j];
1162
51c1a580 1163 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 1164 i, cos, j, sw_bd->skb,
1165 sw_bd->first_bd);
1166 }
8440d2b6 1167
6383c0b3
AE		 1168 start = TX_BD(txdata->tx_bd_cons - 10);
1169 end = TX_BD(txdata->tx_bd_cons + 254);
1170 for (j = start; j != end; j = TX_BD(j + 1)) {
1171 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 1172
51c1a580 1173 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 1174 i, cos, j, tx_bd[0], tx_bd[1],
1175 tx_bd[2], tx_bd[3]);
1176 }
8440d2b6
EG		 1177 }
1178 }
523224a3 1179#endif
0155a27c
YM		 1180 if (IS_PF(bp)) {
1181 bnx2x_fw_dump(bp);
1182 bnx2x_mc_assert(bp);
1183 }
a2fbb9ea 1184 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1185}
1186
619c5cb6
VZ		 1187/*
1188 * FLR Support for E2
1189 *
1190 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1191 * initialization.
1192 */
16a5fd92 1193#define FLR_WAIT_USEC 10000 /* 10 milliseconds */
89db4ad8
AE		 1194#define FLR_WAIT_INTERVAL 50 /* usec */
1195#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1196
1197struct pbf_pN_buf_regs {
1198 int pN;
1199 u32 init_crd;
1200 u32 crd;
1201 u32 crd_freed;
1202};
1203
1204struct pbf_pN_cmd_regs {
1205 int pN;
1206 u32 lines_occup;
1207 u32 lines_freed;
1208};
1209
1210static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1211 struct pbf_pN_buf_regs *regs,
1212 u32 poll_count)
1213{
1214 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1215 u32 cur_cnt = poll_count;
1216
1217 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1218 crd = crd_start = REG_RD(bp, regs->crd);
1219 init_crd = REG_RD(bp, regs->init_crd);
1220
1221 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1222 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1223 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1224
1225 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1226 (init_crd - crd_start))) {
1227 if (cur_cnt--) {
89db4ad8 1228 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1229 crd = REG_RD(bp, regs->crd);
1230 crd_freed = REG_RD(bp, regs->crd_freed);
1231 } else {
1232 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1233 regs->pN);
1234 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1235 regs->pN, crd);
1236 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1237 regs->pN, crd_freed);
1238 break;
1239 }
1240 }
1241 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1242 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1243}
1244
1245static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1246 struct pbf_pN_cmd_regs *regs,
1247 u32 poll_count)
1248{
1249 u32 occup, to_free, freed, freed_start;
1250 u32 cur_cnt = poll_count;
1251
1252 occup = to_free = REG_RD(bp, regs->lines_occup);
1253 freed = freed_start = REG_RD(bp, regs->lines_freed);
1254
1255 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1256 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1257
1258 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1259 if (cur_cnt--) {
89db4ad8 1260 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1261 occup = REG_RD(bp, regs->lines_occup);
1262 freed = REG_RD(bp, regs->lines_freed);
1263 } else {
1264 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1265 regs->pN);
1266 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1267 regs->pN, occup);
1268 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1269 regs->pN, freed);
1270 break;
1271 }
1272 }
1273 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1274 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1275}
1276
1191cb83
ED		 1277static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1278 u32 expected, u32 poll_count)
619c5cb6
VZ		 1279{
1280 u32 cur_cnt = poll_count;
1281 u32 val;
1282
1283 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1284 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1285
1286 return val;
1287}
1288
d16132ce
AE		 1289int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1290 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1291{
1292 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1293 if (val != 0) {
1294 BNX2X_ERR("%s usage count=%d\n", msg, val);
1295 return 1;
1296 }
1297 return 0;
1298}
1299
d16132ce
AE		 1300/* Common routines with VF FLR cleanup */
1301u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
619c5cb6
VZ		 1302{
1303 /* adjust polling timeout */
1304 if (CHIP_REV_IS_EMUL(bp))
1305 return FLR_POLL_CNT * 2000;
1306
1307 if (CHIP_REV_IS_FPGA(bp))
1308 return FLR_POLL_CNT * 120;
1309
1310 return FLR_POLL_CNT;
1311}
1312
d16132ce 1313void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
619c5cb6
VZ		 1314{
1315 struct pbf_pN_cmd_regs cmd_regs[] = {
1316 {0, (CHIP_IS_E3B0(bp)) ?
1317 PBF_REG_TQ_OCCUPANCY_Q0 :
1318 PBF_REG_P0_TQ_OCCUPANCY,
1319 (CHIP_IS_E3B0(bp)) ?
1320 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1321 PBF_REG_P0_TQ_LINES_FREED_CNT},
1322 {1, (CHIP_IS_E3B0(bp)) ?
1323 PBF_REG_TQ_OCCUPANCY_Q1 :
1324 PBF_REG_P1_TQ_OCCUPANCY,
1325 (CHIP_IS_E3B0(bp)) ?
1326 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1327 PBF_REG_P1_TQ_LINES_FREED_CNT},
1328 {4, (CHIP_IS_E3B0(bp)) ?
1329 PBF_REG_TQ_OCCUPANCY_LB_Q :
1330 PBF_REG_P4_TQ_OCCUPANCY,
1331 (CHIP_IS_E3B0(bp)) ?
1332 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1333 PBF_REG_P4_TQ_LINES_FREED_CNT}
1334 };
1335
1336 struct pbf_pN_buf_regs buf_regs[] = {
1337 {0, (CHIP_IS_E3B0(bp)) ?
1338 PBF_REG_INIT_CRD_Q0 :
1339 PBF_REG_P0_INIT_CRD ,
1340 (CHIP_IS_E3B0(bp)) ?
1341 PBF_REG_CREDIT_Q0 :
1342 PBF_REG_P0_CREDIT,
1343 (CHIP_IS_E3B0(bp)) ?
1344 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1345 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1346 {1, (CHIP_IS_E3B0(bp)) ?
1347 PBF_REG_INIT_CRD_Q1 :
1348 PBF_REG_P1_INIT_CRD,
1349 (CHIP_IS_E3B0(bp)) ?
1350 PBF_REG_CREDIT_Q1 :
1351 PBF_REG_P1_CREDIT,
1352 (CHIP_IS_E3B0(bp)) ?
1353 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1354 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1355 {4, (CHIP_IS_E3B0(bp)) ?
1356 PBF_REG_INIT_CRD_LB_Q :
1357 PBF_REG_P4_INIT_CRD,
1358 (CHIP_IS_E3B0(bp)) ?
1359 PBF_REG_CREDIT_LB_Q :
1360 PBF_REG_P4_CREDIT,
1361 (CHIP_IS_E3B0(bp)) ?
1362 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1363 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1364 };
1365
1366 int i;
1367
1368 /* Verify the command queues are flushed P0, P1, P4 */
1369 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1370 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1371
619c5cb6
VZ		 1372 /* Verify the transmission buffers are flushed P0, P1, P4 */
1373 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1374 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1375}
1376
1377#define OP_GEN_PARAM(param) \
1378 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1379
1380#define OP_GEN_TYPE(type) \
1381 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1382
1383#define OP_GEN_AGG_VECT(index) \
1384 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1385
d16132ce 1386int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
619c5cb6 1387{
86564c3f 1388 u32 op_gen_command = 0;
619c5cb6
VZ		 1389 u32 comp_addr = BAR_CSTRORM_INTMEM +
1390 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1391 int ret = 0;
1392
1393 if (REG_RD(bp, comp_addr)) {
89db4ad8 1394 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1395 return 1;
1396 }
1397
86564c3f
YM		 1398 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1399 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1400 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1401 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
619c5cb6 1402
89db4ad8 1403 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
86564c3f 1404 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
619c5cb6
VZ		 1405
1406 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1407 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1408 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1409 (REG_RD(bp, comp_addr)));
d16132ce
AE		 1410 bnx2x_panic();
1411 return 1;
619c5cb6 1412 }
16a5fd92 1413 /* Zero completion for next FLR */
619c5cb6
VZ		 1414 REG_WR(bp, comp_addr, 0);
1415
1416 return ret;
1417}
1418
b56e9670 1419u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1420{
619c5cb6
VZ		 1421 u16 status;
1422
2a80eebc 1423 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1424 return status & PCI_EXP_DEVSTA_TRPND;
1425}
1426
1427/* PF FLR specific routines
1428*/
1429static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1430{
619c5cb6
VZ		 1431 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1432 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1433 CFC_REG_NUM_LCIDS_INSIDE_PF,
1434 "CFC PF usage counter timed out",
1435 poll_cnt))
1436 return 1;
1437
619c5cb6
VZ		 1438 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1439 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1440 DORQ_REG_PF_USAGE_CNT,
1441 "DQ PF usage counter timed out",
1442 poll_cnt))
1443 return 1;
1444
1445 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1446 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1447 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1448 "QM PF usage counter timed out",
1449 poll_cnt))
1450 return 1;
1451
1452 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1453 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1454 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1455 "Timers VNIC usage counter timed out",
1456 poll_cnt))
1457 return 1;
1458 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1459 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1460 "Timers NUM_SCANS usage counter timed out",
1461 poll_cnt))
1462 return 1;
1463
1464 /* Wait DMAE PF usage counter to zero */
1465 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1466 dmae_reg_go_c[INIT_DMAE_C(bp)],
6bf07b8e 1467 "DMAE command register timed out",
619c5cb6
VZ		 1468 poll_cnt))
1469 return 1;
1470
1471 return 0;
1472}
1473
1474static void bnx2x_hw_enable_status(struct bnx2x *bp)
1475{
1476 u32 val;
1477
1478 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1479 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1480
1481 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1482 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1483
1484 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1485 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1486
1487 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1488 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1489
1490 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1491 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1492
1493 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1494 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1495
1496 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1497 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1498
1499 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1500 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1501 val);
1502}
1503
1504static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1505{
1506 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1507
1508 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1509
1510 /* Re-enable PF target read access */
1511 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1512
1513 /* Poll HW usage counters */
89db4ad8 1514 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1515 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1516 return -EBUSY;
1517
1518 /* Zero the igu 'trailing edge' and 'leading edge' */
1519
1520 /* Send the FW cleanup command */
1521 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1522 return -EBUSY;
1523
1524 /* ATC cleanup */
1525
1526 /* Verify TX hw is flushed */
1527 bnx2x_tx_hw_flushed(bp, poll_cnt);
1528
1529 /* Wait 100ms (not adjusted according to platform) */
1530 msleep(100);
1531
1532 /* Verify no pending pci transactions */
1533 if (bnx2x_is_pcie_pending(bp->pdev))
1534 BNX2X_ERR("PCIE Transactions still pending\n");
1535
1536 /* Debug */
1537 bnx2x_hw_enable_status(bp);
1538
1539 /*
1540 * Master enable - Due to WB DMAE writes performed before this
1541 * register is re-initialized as part of the regular function init
1542 */
1543 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1544
1545 return 0;
1546}
1547
f2e0899f 1548static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1549{
34f80b04 1550 int port = BP_PORT(bp);
a2fbb9ea
ET		 1551 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1552 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1553 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1554 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1555 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1556
1557 if (msix) {
8badd27a
EG		 1558 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1559 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1560 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1561 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1562 if (single_msix)
1563 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1564 } else if (msi) {
1565 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1566 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1567 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1568 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1569 } else {
1570 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1571 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1572 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1573 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1574
a0fd065c 1575 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1576 DP(NETIF_MSG_IFUP,
1577 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1578
a0fd065c 1579 REG_WR(bp, addr, val);
615f8fd9 1580
a0fd065c
DK		 1581 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1582 }
a2fbb9ea
ET		 1583 }
1584
a0fd065c
DK		 1585 if (CHIP_IS_E1(bp))
1586 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1587
51c1a580
MS		 1588 DP(NETIF_MSG_IFUP,
1589 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1590 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1591
1592 REG_WR(bp, addr, val);
37dbbf32
EG		 1593 /*
1594 * Ensure that HC_CONFIG is written before leading/trailing edge config
1595 */
1596 mmiowb();
1597 barrier();
34f80b04 1598
f2e0899f 1599 if (!CHIP_IS_E1(bp)) {
34f80b04 1600 /* init leading/trailing edge */
fb3bff17 1601 if (IS_MF(bp)) {
3395a033 1602 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1603 if (bp->port.pmf)
4acac6a5
EG		 1604 /* enable nig and gpio3 attention */
1605 val |= 0x1100;
34f80b04
EG		 1606 } else
1607 val = 0xffff;
1608
1609 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1610 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1611 }
37dbbf32
EG		 1612
1613 /* Make sure that interrupts are indeed enabled from here on */
1614 mmiowb();
a2fbb9ea
ET		 1615}
1616
f2e0899f
DK		 1617static void bnx2x_igu_int_enable(struct bnx2x *bp)
1618{
1619 u32 val;
30a5de77
DK		 1620 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1621 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1622 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1623
1624 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1625
1626 if (msix) {
1627 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1628 IGU_PF_CONF_SINGLE_ISR_EN);
ebe61d80 1629 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f 1630 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1631
1632 if (single_msix)
1633 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1634 } else if (msi) {
1635 val &= ~IGU_PF_CONF_INT_LINE_EN;
ebe61d80 1636 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f
DK		 1637 IGU_PF_CONF_ATTN_BIT_EN |
1638 IGU_PF_CONF_SINGLE_ISR_EN);
1639 } else {
1640 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
ebe61d80 1641 val |= (IGU_PF_CONF_INT_LINE_EN |
f2e0899f
DK		 1642 IGU_PF_CONF_ATTN_BIT_EN |
1643 IGU_PF_CONF_SINGLE_ISR_EN);
1644 }
1645
ebe61d80
YM		 1646 /* Clean previous status - need to configure igu prior to ack*/
1647 if ((!msix) || single_msix) {
1648 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1649 bnx2x_ack_int(bp);
1650 }
1651
1652 val |= IGU_PF_CONF_FUNC_EN;
1653
51c1a580 1654 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1655 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1656
1657 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1658
79a8557a
YM		 1659 if (val & IGU_PF_CONF_INT_LINE_EN)
1660 pci_intx(bp->pdev, true);
1661
f2e0899f
DK		 1662 barrier();
1663
1664 /* init leading/trailing edge */
1665 if (IS_MF(bp)) {
3395a033 1666 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1667 if (bp->port.pmf)
1668 /* enable nig and gpio3 attention */
1669 val |= 0x1100;
1670 } else
1671 val = 0xffff;
1672
1673 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1674 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1675
1676 /* Make sure that interrupts are indeed enabled from here on */
1677 mmiowb();
1678}
1679
1680void bnx2x_int_enable(struct bnx2x *bp)
1681{
1682 if (bp->common.int_block == INT_BLOCK_HC)
1683 bnx2x_hc_int_enable(bp);
1684 else
1685 bnx2x_igu_int_enable(bp);
1686}
1687
9f6c9258 1688void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1689{
a2fbb9ea 1690 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1691 int i, offset;
a2fbb9ea 1692
f8ef6e44
YG		 1693 if (disable_hw)
1694 /* prevent the HW from sending interrupts */
1695 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1696
1697 /* make sure all ISRs are done */
1698 if (msix) {
8badd27a
EG		 1699 synchronize_irq(bp->msix_table[0].vector);
1700 offset = 1;
55c11941
MS		 1701 if (CNIC_SUPPORT(bp))
1702 offset++;
ec6ba945 1703 for_each_eth_queue(bp, i)
754a2f52 1704 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1705 } else
1706 synchronize_irq(bp->pdev->irq);
1707
1708 /* make sure sp_task is not running */
1cf167f2 1709 cancel_delayed_work(&bp->sp_task);
3deb8167 1710 cancel_delayed_work(&bp->period_task);
1cf167f2 1711 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1712}
1713
34f80b04 1714/* fast path */
a2fbb9ea
ET		 1715
1716/*
34f80b04 1717 * General service functions
a2fbb9ea
ET		 1718 */
1719
72fd0718
VZ		 1720/* Return true if succeeded to acquire the lock */
1721static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1722{
1723 u32 lock_status;
1724 u32 resource_bit = (1 << resource);
1725 int func = BP_FUNC(bp);
1726 u32 hw_lock_control_reg;
1727
51c1a580
MS		 1728 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1729 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1730
1731 /* Validating that the resource is within range */
1732 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1733 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1734 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1735 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1736 return false;
72fd0718
VZ		 1737 }
1738
1739 if (func <= 5)
1740 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1741 else
1742 hw_lock_control_reg =
1743 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1744
1745 /* Try to acquire the lock */
1746 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1747 lock_status = REG_RD(bp, hw_lock_control_reg);
1748 if (lock_status & resource_bit)
1749 return true;
1750
51c1a580
MS		 1751 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1752 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1753 return false;
1754}
1755
c9ee9206
VZ		 1756/**
1757 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1758 *
1759 * @bp: driver handle
1760 *
1761 * Returns the recovery leader resource id according to the engine this function
1762 * belongs to. Currently only only 2 engines is supported.
1763 */
1191cb83 1764static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1765{
1766 if (BP_PATH(bp))
1767 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1768 else
1769 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1770}
1771
1772/**
2de67439 1773 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
c9ee9206
VZ		 1774 *
1775 * @bp: driver handle
1776 *
2de67439 1777 * Tries to acquire a leader lock for current engine.
c9ee9206 1778 */
1191cb83 1779static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1780{
1781 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1782}
1783
619c5cb6 1784static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1785
fd1fc79d
AE		 1786/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1787static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1788{
1789 /* Set the interrupt occurred bit for the sp-task to recognize it
1790 * must ack the interrupt and transition according to the IGU
1791 * state machine.
1792 */
1793 atomic_set(&bp->interrupt_occurred, 1);
1794
1795 /* The sp_task must execute only after this bit
1796 * is set, otherwise we will get out of sync and miss all
1797 * further interrupts. Hence, the barrier.
1798 */
1799 smp_wmb();
1800
1801 /* schedule sp_task to workqueue */
1802 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1803}
3196a88a 1804
619c5cb6 1805void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1806{
1807 struct bnx2x *bp = fp->bp;
1808 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1809 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1810 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1811 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1812
34f80b04 1813 DP(BNX2X_MSG_SP,
a2fbb9ea 1814 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1815 fp->index, cid, command, bp->state,
34f80b04 1816 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1817
fd1fc79d
AE		 1818 /* If cid is within VF range, replace the slowpath object with the
1819 * one corresponding to this VF
1820 */
1821 if (cid >= BNX2X_FIRST_VF_CID &&
1822 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1823 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1824
619c5cb6
VZ		 1825 switch (command) {
1826 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1827 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1828 drv_cmd = BNX2X_Q_CMD_UPDATE;
1829 break;
d6cae238 1830
619c5cb6 1831 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1832 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1833 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1834 break;
1835
6383c0b3 1836 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1837 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1838 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1839 break;
1840
619c5cb6 1841 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1842 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1843 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1844 break;
1845
619c5cb6 1846 case (RAMROD_CMD_ID_ETH_TERMINATE):
6bf07b8e 1847 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
619c5cb6 1848 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1849 break;
1850
619c5cb6 1851 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1852 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1853 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1854 break;
619c5cb6 1855
14a94ebd
MK		 1856 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1857 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1858 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1859 break;
1860
619c5cb6
VZ		 1861 default:
1862 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1863 command, fp->index);
1864 return;
523224a3 1865 }
3196a88a 1866
619c5cb6
VZ		 1867 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1868 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1869 /* q_obj->complete_cmd() failure means that this was
1870 * an unexpected completion.
1871 *
1872 * In this case we don't want to increase the bp->spq_left
1873 * because apparently we haven't sent this command the first
1874 * place.
1875 */
1876#ifdef BNX2X_STOP_ON_ERROR
1877 bnx2x_panic();
1878#else
1879 return;
1880#endif
1881
4e857c58 1882 smp_mb__before_atomic();
6e30dd4e 1883 atomic_inc(&bp->cq_spq_left);
619c5cb6 1884 /* push the change in bp->spq_left and towards the memory */
4e857c58 1885 smp_mb__after_atomic();
49d66772 1886
d6cae238
VZ		 1887 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1888
a3348722
BW		 1889 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1890 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1891 /* if Q update ramrod is completed for last Q in AFEX vif set
1892 * flow, then ACK MCP at the end
1893 *
1894 * mark pending ACK to MCP bit.
1895 * prevent case that both bits are cleared.
1896 * At the end of load/unload driver checks that
2de67439 1897 * sp_state is cleared, and this order prevents
a3348722
BW		 1898 * races
1899 */
4e857c58 1900 smp_mb__before_atomic();
a3348722
BW		 1901 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1902 wmb();
1903 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 1904 smp_mb__after_atomic();
a3348722 1905
fd1fc79d
AE		 1906 /* schedule the sp task as mcp ack is required */
1907 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1908 }
1909
523224a3 1910 return;
a2fbb9ea
ET		 1911}
1912
9f6c9258 1913irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1914{
555f6c78 1915 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1916 u16 status = bnx2x_ack_int(bp);
34f80b04 1917 u16 mask;
ca00392c 1918 int i;
6383c0b3 1919 u8 cos;
a2fbb9ea 1920
34f80b04 1921 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1922 if (unlikely(status == 0)) {
1923 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1924 return IRQ_NONE;
1925 }
f5372251 1926 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1927
3196a88a
EG		 1928#ifdef BNX2X_STOP_ON_ERROR
1929 if (unlikely(bp->panic))
1930 return IRQ_HANDLED;
1931#endif
1932
ec6ba945 1933 for_each_eth_queue(bp, i) {
ca00392c 1934 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1935
55c11941 1936 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1937 if (status & mask) {
619c5cb6 1938 /* Handle Rx or Tx according to SB id */
6383c0b3 1939 for_each_cos_in_tx_queue(fp, cos)
65565884 1940 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1941 prefetch(&fp->sb_running_index[SM_RX_ID]);
f5fbf115 1942 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1943 status &= ~mask;
1944 }
a2fbb9ea
ET		 1945 }
1946
55c11941
MS		 1947 if (CNIC_SUPPORT(bp)) {
1948 mask = 0x2;
1949 if (status & (mask | 0x1)) {
1950 struct cnic_ops *c_ops = NULL;
993ac7b5 1951
ad9b4359
MC		 1952 rcu_read_lock();
1953 c_ops = rcu_dereference(bp->cnic_ops);
1954 if (c_ops && (bp->cnic_eth_dev.drv_state &
1955 CNIC_DRV_STATE_HANDLES_IRQ))
1956 c_ops->cnic_handler(bp->cnic_data, NULL);
1957 rcu_read_unlock();
993ac7b5 1958
55c11941
MS		 1959 status &= ~mask;
1960 }
993ac7b5 1961 }
a2fbb9ea 1962
34f80b04 1963 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1964
1965 /* schedule sp task to perform default status block work, ack
1966 * attentions and enable interrupts.
1967 */
1968 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1969
1970 status &= ~0x1;
1971 if (!status)
1972 return IRQ_HANDLED;
1973 }
1974
cdaa7cb8
VZ		 1975 if (unlikely(status))
1976 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1977 status);
a2fbb9ea 1978
c18487ee 1979 return IRQ_HANDLED;
a2fbb9ea
ET		 1980}
1981
c18487ee
YR		 1982/* Link */
1983
1984/*
1985 * General service functions
1986 */
a2fbb9ea 1987
9f6c9258 1988int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1989{
1990 u32 lock_status;
1991 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1992 int func = BP_FUNC(bp);
1993 u32 hw_lock_control_reg;
c18487ee 1994 int cnt;
a2fbb9ea 1995
c18487ee
YR		 1996 /* Validating that the resource is within range */
1997 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1998 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1999 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2000 return -EINVAL;
2001 }
a2fbb9ea 2002
4a37fb66
YG		 2003 if (func <= 5) {
2004 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2005 } else {
2006 hw_lock_control_reg =
2007 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2008 }
2009
c18487ee 2010 /* Validating that the resource is not already taken */
4a37fb66 2011 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2012 if (lock_status & resource_bit) {
51c1a580 2013 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 2014 lock_status, resource_bit);
2015 return -EEXIST;
2016 }
a2fbb9ea 2017
46230476
EG		 2018 /* Try for 5 second every 5ms */
2019 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 2020 /* Try to acquire the lock */
4a37fb66
YG		 2021 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2022 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 2023 if (lock_status & resource_bit)
2024 return 0;
a2fbb9ea 2025
639d65b8 2026 usleep_range(5000, 10000);
a2fbb9ea 2027 }
51c1a580 2028 BNX2X_ERR("Timeout\n");
c18487ee
YR		 2029 return -EAGAIN;
2030}
a2fbb9ea 2031
c9ee9206
VZ		 2032int bnx2x_release_leader_lock(struct bnx2x *bp)
2033{
2034 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2035}
2036
9f6c9258 2037int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 2038{
2039 u32 lock_status;
2040 u32 resource_bit = (1 << resource);
4a37fb66
YG		 2041 int func = BP_FUNC(bp);
2042 u32 hw_lock_control_reg;
a2fbb9ea 2043
c18487ee
YR		 2044 /* Validating that the resource is within range */
2045 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2046 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2047 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2048 return -EINVAL;
2049 }
2050
4a37fb66
YG		 2051 if (func <= 5) {
2052 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2053 } else {
2054 hw_lock_control_reg =
2055 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2056 }
2057
c18487ee 2058 /* Validating that the resource is currently taken */
4a37fb66 2059 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2060 if (!(lock_status & resource_bit)) {
6bf07b8e
YM		 2061 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2062 lock_status, resource_bit);
c18487ee 2063 return -EFAULT;
a2fbb9ea
ET		 2064 }
2065
9f6c9258
DK		 2066 REG_WR(bp, hw_lock_control_reg, resource_bit);
2067 return 0;
c18487ee 2068}
a2fbb9ea 2069
4acac6a5
EG		 2070int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2071{
2072 /* The GPIO should be swapped if swap register is set and active */
2073 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2074 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2075 int gpio_shift = gpio_num +
2076 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2077 u32 gpio_mask = (1 << gpio_shift);
2078 u32 gpio_reg;
2079 int value;
2080
2081 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2082 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2083 return -EINVAL;
2084 }
2085
2086 /* read GPIO value */
2087 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2088
2089 /* get the requested pin value */
2090 if ((gpio_reg & gpio_mask) == gpio_mask)
2091 value = 1;
2092 else
2093 value = 0;
2094
4acac6a5
EG		 2095 return value;
2096}
2097
17de50b7 2098int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 2099{
2100 /* The GPIO should be swapped if swap register is set and active */
2101 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 2102 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 2103 int gpio_shift = gpio_num +
2104 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2105 u32 gpio_mask = (1 << gpio_shift);
2106 u32 gpio_reg;
a2fbb9ea 2107
c18487ee
YR		 2108 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2109 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2110 return -EINVAL;
2111 }
a2fbb9ea 2112
4a37fb66 2113 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 2114 /* read GPIO and mask except the float bits */
2115 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 2116
c18487ee
YR		 2117 switch (mode) {
2118 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 2119 DP(NETIF_MSG_LINK,
2120 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 2121 gpio_num, gpio_shift);
2122 /* clear FLOAT and set CLR */
2123 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2124 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2125 break;
a2fbb9ea 2126
c18487ee 2127 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2128 DP(NETIF_MSG_LINK,
2129 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2130 gpio_num, gpio_shift);
2131 /* clear FLOAT and set SET */
2132 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2133 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2134 break;
a2fbb9ea 2135
17de50b7 2136 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2137 DP(NETIF_MSG_LINK,
2138 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2139 gpio_num, gpio_shift);
2140 /* set FLOAT */
2141 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2142 break;
a2fbb9ea 2143
c18487ee
YR		 2144 default:
2145 break;
a2fbb9ea
ET		 2146 }
2147
c18487ee 2148 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2149 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2150
c18487ee 2151 return 0;
a2fbb9ea
ET		 2152}
2153
0d40f0d4
YR		 2154int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2155{
2156 u32 gpio_reg = 0;
2157 int rc = 0;
2158
2159 /* Any port swapping should be handled by caller. */
2160
2161 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2162 /* read GPIO and mask except the float bits */
2163 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2164 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2165 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2166 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2167
2168 switch (mode) {
2169 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2170 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2171 /* set CLR */
2172 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2173 break;
2174
2175 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2176 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2177 /* set SET */
2178 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2179 break;
2180
2181 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2182 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2183 /* set FLOAT */
2184 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2185 break;
2186
2187 default:
2188 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2189 rc = -EINVAL;
2190 break;
2191 }
2192
2193 if (rc == 0)
2194 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2195
2196 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2197
2198 return rc;
2199}
2200
4acac6a5
EG		 2201int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2202{
2203 /* The GPIO should be swapped if swap register is set and active */
2204 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2205 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2206 int gpio_shift = gpio_num +
2207 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2208 u32 gpio_mask = (1 << gpio_shift);
2209 u32 gpio_reg;
2210
2211 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2212 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2213 return -EINVAL;
2214 }
2215
2216 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2217 /* read GPIO int */
2218 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2219
2220 switch (mode) {
2221 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2222 DP(NETIF_MSG_LINK,
2223 "Clear GPIO INT %d (shift %d) -> output low\n",
2224 gpio_num, gpio_shift);
4acac6a5
EG		 2225 /* clear SET and set CLR */
2226 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2227 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2228 break;
2229
2230 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2231 DP(NETIF_MSG_LINK,
2232 "Set GPIO INT %d (shift %d) -> output high\n",
2233 gpio_num, gpio_shift);
4acac6a5
EG		 2234 /* clear CLR and set SET */
2235 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2236 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2237 break;
2238
2239 default:
2240 break;
2241 }
2242
2243 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2244 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2245
2246 return 0;
2247}
2248
d6d99a3f 2249static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2250{
c18487ee 2251 u32 spio_reg;
a2fbb9ea 2252
d6d99a3f
YM		 2253 /* Only 2 SPIOs are configurable */
2254 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2255 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2256 return -EINVAL;
a2fbb9ea
ET		 2257 }
2258
4a37fb66 2259 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2260 /* read SPIO and mask except the float bits */
d6d99a3f 2261 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2262
c18487ee 2263 switch (mode) {
d6d99a3f
YM		 2264 case MISC_SPIO_OUTPUT_LOW:
2265 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2266 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2267 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2268 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2269 break;
a2fbb9ea 2270
d6d99a3f
YM		 2271 case MISC_SPIO_OUTPUT_HIGH:
2272 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2273 /* clear FLOAT and set SET */
d6d99a3f
YM		 2274 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2275 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2276 break;
a2fbb9ea 2277
d6d99a3f
YM		 2278 case MISC_SPIO_INPUT_HI_Z:
2279 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2280 /* set FLOAT */
d6d99a3f 2281 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2282 break;
a2fbb9ea 2283
c18487ee
YR		 2284 default:
2285 break;
a2fbb9ea
ET		 2286 }
2287
c18487ee 2288 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2289 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2290
a2fbb9ea
ET		 2291 return 0;
2292}
2293
9f6c9258 2294void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2295{
a22f0788 2296 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1359d73c
YM		 2297
2298 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2299 ADVERTISED_Pause);
ad33ea3a
EG		 2300 switch (bp->link_vars.ieee_fc &
2301 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2302 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2303 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2304 ADVERTISED_Pause);
c18487ee 2305 break;
356e2385 2306
c18487ee 2307 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2308 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2309 break;
356e2385 2310
c18487ee 2311 default:
c18487ee
YR		 2312 break;
2313 }
2314}
f1410647 2315
cd1dfce2 2316static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2317{
cd1dfce2
YM		 2318 /* Initialize link parameters structure variables
2319 * It is recommended to turn off RX FC for jumbo frames
2320 * for better performance
2321 */
2322 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2323 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2324 else
2325 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2326}
a2fbb9ea 2327
9156b30b
DK		 2328static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2329{
2330 u32 pause_enabled = 0;
2331
2332 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2333 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2334 pause_enabled = 1;
2335
2336 REG_WR(bp, BAR_USTRORM_INTMEM +
2337 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2338 pause_enabled);
2339 }
2340
2341 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2342 pause_enabled ? "enabled" : "disabled");
2343}
2344
cd1dfce2
YM		 2345int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2346{
2347 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2348 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2349
2350 if (!BP_NOMCP(bp)) {
2351 bnx2x_set_requested_fc(bp);
4a37fb66 2352 bnx2x_acquire_phy_lock(bp);
b5bf9068 2353
a22f0788 2354 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2355 struct link_params *lp = &bp->link_params;
2356 lp->loopback_mode = LOOPBACK_XGXS;
2f43b821
YM		 2357 /* Prefer doing PHY loopback at highest speed */
2358 if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
1cb0c788 2359 if (lp->speed_cap_mask[cfx_idx] &
2f43b821 2360 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
1cb0c788 2361 lp->req_line_speed[cfx_idx] =
2f43b821
YM		 2362 SPEED_20000;
2363 else if (lp->speed_cap_mask[cfx_idx] &
2364 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2365 lp->req_line_speed[cfx_idx] =
2366 SPEED_10000;
1cb0c788
YR		 2367 else
2368 lp->req_line_speed[cfx_idx] =
2369 SPEED_1000;
2370 }
a22f0788 2371 }
b5bf9068 2372
8970b2e4
MS		 2373 if (load_mode == LOAD_LOOPBACK_EXT) {
2374 struct link_params *lp = &bp->link_params;
2375 lp->loopback_mode = LOOPBACK_EXT;
2376 }
2377
19680c48 2378 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2379
4a37fb66 2380 bnx2x_release_phy_lock(bp);
a2fbb9ea 2381
9156b30b
DK		 2382 bnx2x_init_dropless_fc(bp);
2383
3c96c68b
EG		 2384 bnx2x_calc_fc_adv(bp);
2385
cd1dfce2 2386 if (bp->link_vars.link_up) {
b5bf9068 2387 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2388 bnx2x_link_report(bp);
cd1dfce2
YM		 2389 }
2390 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2391 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2392 return rc;
2393 }
f5372251 2394 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2395 return -EINVAL;
a2fbb9ea
ET		 2396}
2397
9f6c9258 2398void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2399{
19680c48 2400 if (!BP_NOMCP(bp)) {
4a37fb66 2401 bnx2x_acquire_phy_lock(bp);
19680c48 2402 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2403 bnx2x_release_phy_lock(bp);
a2fbb9ea 2404
9156b30b
DK		 2405 bnx2x_init_dropless_fc(bp);
2406
19680c48
EG		 2407 bnx2x_calc_fc_adv(bp);
2408 } else
f5372251 2409 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2410}
a2fbb9ea 2411
c18487ee
YR		 2412static void bnx2x__link_reset(struct bnx2x *bp)
2413{
19680c48 2414 if (!BP_NOMCP(bp)) {
4a37fb66 2415 bnx2x_acquire_phy_lock(bp);
5d07d868 2416 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2417 bnx2x_release_phy_lock(bp);
19680c48 2418 } else
f5372251 2419 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2420}
a2fbb9ea 2421
5d07d868
YM		 2422void bnx2x_force_link_reset(struct bnx2x *bp)
2423{
2424 bnx2x_acquire_phy_lock(bp);
2425 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2426 bnx2x_release_phy_lock(bp);
2427}
2428
a22f0788 2429u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2430{
2145a920 2431 u8 rc = 0;
a2fbb9ea 2432
2145a920
VZ		 2433 if (!BP_NOMCP(bp)) {
2434 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2435 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2436 is_serdes);
2145a920
VZ		 2437 bnx2x_release_phy_lock(bp);
2438 } else
2439 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2440
c18487ee
YR		 2441 return rc;
2442}
a2fbb9ea 2443
2691d51d
EG		 2444/* Calculates the sum of vn_min_rates.
2445 It's needed for further normalizing of the min_rates.
2446 Returns:
2447 sum of vn_min_rates.
2448 or
2449 0 - if all the min_rates are 0.
16a5fd92 2450 In the later case fairness algorithm should be deactivated.
2691d51d
EG		 2451 If not all min_rates are zero then those that are zeroes will be set to 1.
2452 */
b475d78f
YM		 2453static void bnx2x_calc_vn_min(struct bnx2x *bp,
2454 struct cmng_init_input *input)
2691d51d
EG		 2455{
2456 int all_zero = 1;
2691d51d
EG		 2457 int vn;
2458
3395a033 2459 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2460 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2461 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2462 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2463
2464 /* Skip hidden vns */
2465 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2466 vn_min_rate = 0;
2691d51d 2467 /* If min rate is zero - set it to 1 */
b475d78f 2468 else if (!vn_min_rate)
2691d51d
EG		 2469 vn_min_rate = DEF_MIN_RATE;
2470 else
2471 all_zero = 0;
2472
b475d78f 2473 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2474 }
2475
30ae438b
DK		 2476 /* if ETS or all min rates are zeros - disable fairness */
2477 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2478 input->flags.cmng_enables &=
30ae438b
DK		 2479 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2480 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2481 } else if (all_zero) {
b475d78f 2482 input->flags.cmng_enables &=
b015e3d1 2483 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2484 DP(NETIF_MSG_IFUP,
2485 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2486 } else
b475d78f 2487 input->flags.cmng_enables |=
b015e3d1 2488 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2489}
2490
b475d78f
YM		 2491static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2492 struct cmng_init_input *input)
34f80b04 2493{
b475d78f 2494 u16 vn_max_rate;
f2e0899f 2495 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2496
b475d78f 2497 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2498 vn_max_rate = 0;
b475d78f 2499 else {
faa6fcbb
DK		 2500 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2501
da3cc2da 2502 if (IS_MF_PERCENT_BW(bp)) {
faa6fcbb
DK		 2503 /* maxCfg in percents of linkspeed */
2504 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2505 } else /* SD modes */
faa6fcbb
DK		 2506 /* maxCfg is absolute in 100Mb units */
2507 vn_max_rate = maxCfg * 100;
34f80b04 2508 }
f85582f8 2509
b475d78f 2510 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2511
b475d78f 2512 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2513}
f85582f8 2514
523224a3
DK		 2515static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2516{
2517 if (CHIP_REV_IS_SLOW(bp))
2518 return CMNG_FNS_NONE;
fb3bff17 2519 if (IS_MF(bp))
523224a3
DK		 2520 return CMNG_FNS_MINMAX;
2521
2522 return CMNG_FNS_NONE;
2523}
2524
2ae17f66 2525void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2526{
0793f83f 2527 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2528
2529 if (BP_NOMCP(bp))
16a5fd92 2530 return; /* what should be the default value in this case */
523224a3 2531
0793f83f
DK		 2532 /* For 2 port configuration the absolute function number formula
2533 * is:
2534 * abs_func = 2 * vn + BP_PORT + BP_PATH
2535 *
2536 * and there are 4 functions per port
2537 *
2538 * For 4 port configuration it is
2539 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2540 *
2541 * and there are 2 functions per port
2542 */
3395a033 2543 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2544 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2545
2546 if (func >= E1H_FUNC_MAX)
2547 break;
2548
f2e0899f 2549 bp->mf_config[vn] =
523224a3
DK		 2550 MF_CFG_RD(bp, func_mf_config[func].config);
2551 }
a3348722
BW		 2552 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2553 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2554 bp->flags |= MF_FUNC_DIS;
2555 } else {
2556 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2557 bp->flags &= ~MF_FUNC_DIS;
2558 }
523224a3
DK		 2559}
2560
2561static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2562{
b475d78f
YM		 2563 struct cmng_init_input input;
2564 memset(&input, 0, sizeof(struct cmng_init_input));
2565
2566 input.port_rate = bp->link_vars.line_speed;
523224a3 2567
568e2426 2568 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
523224a3
DK		 2569 int vn;
2570
523224a3
DK		 2571 /* read mf conf from shmem */
2572 if (read_cfg)
2573 bnx2x_read_mf_cfg(bp);
2574
523224a3 2575 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2576 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2577
2578 /* calculate and set min-max rate for each vn */
c4154f25 2579 if (bp->port.pmf)
3395a033 2580 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2581 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2582
2583 /* always enable rate shaping and fairness */
b475d78f 2584 input.flags.cmng_enables |=
523224a3 2585 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2586
2587 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2588 return;
2589 }
2590
2591 /* rate shaping and fairness are disabled */
2592 DP(NETIF_MSG_IFUP,
2593 "rate shaping and fairness are disabled\n");
2594}
34f80b04 2595
1191cb83
ED		 2596static void storm_memset_cmng(struct bnx2x *bp,
2597 struct cmng_init *cmng,
2598 u8 port)
2599{
2600 int vn;
2601 size_t size = sizeof(struct cmng_struct_per_port);
2602
2603 u32 addr = BAR_XSTRORM_INTMEM +
2604 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2605
2606 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2607
2608 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2609 int func = func_by_vn(bp, vn);
2610
2611 addr = BAR_XSTRORM_INTMEM +
2612 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2613 size = sizeof(struct rate_shaping_vars_per_vn);
2614 __storm_memset_struct(bp, addr, size,
2615 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2616
2617 addr = BAR_XSTRORM_INTMEM +
2618 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2619 size = sizeof(struct fairness_vars_per_vn);
2620 __storm_memset_struct(bp, addr, size,
2621 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2622 }
2623}
2624
568e2426
DK		 2625/* init cmng mode in HW according to local configuration */
2626void bnx2x_set_local_cmng(struct bnx2x *bp)
2627{
2628 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2629
2630 if (cmng_fns != CMNG_FNS_NONE) {
2631 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2632 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2633 } else {
2634 /* rate shaping and fairness are disabled */
2635 DP(NETIF_MSG_IFUP,
2636 "single function mode without fairness\n");
2637 }
2638}
2639
c18487ee
YR		 2640/* This function is called upon link interrupt */
2641static void bnx2x_link_attn(struct bnx2x *bp)
2642{
bb2a0f7a
YG		 2643 /* Make sure that we are synced with the current statistics */
2644 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2645
c18487ee 2646 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2647
9156b30b 2648 bnx2x_init_dropless_fc(bp);
1c06328c 2649
9156b30b 2650 if (bp->link_vars.link_up) {
1c06328c 2651
619c5cb6 2652 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2653 struct host_port_stats *pstats;
2654
2655 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2656 /* reset old mac stats */
bb2a0f7a
YG		 2657 memset(&(pstats->mac_stx[0]), 0,
2658 sizeof(struct mac_stx));
2659 }
f34d28ea 2660 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2661 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2662 }
2663
568e2426
DK		 2664 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2665 bnx2x_set_local_cmng(bp);
9fdc3e95 2666
2ae17f66
VZ		 2667 __bnx2x_link_report(bp);
2668
9fdc3e95
DK		 2669 if (IS_MF(bp))
2670 bnx2x_link_sync_notify(bp);
c18487ee 2671}
a2fbb9ea 2672
9f6c9258 2673void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2674{
2ae17f66 2675 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2676 return;
a2fbb9ea 2677
00253a8c 2678 /* read updated dcb configuration */
ad5afc89
AE		 2679 if (IS_PF(bp)) {
2680 bnx2x_dcbx_pmf_update(bp);
2681 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2682 if (bp->link_vars.link_up)
2683 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2684 else
2685 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2686 /* indicate link status */
2687 bnx2x_link_report(bp);
a2fbb9ea 2688
ad5afc89
AE		 2689 } else { /* VF */
2690 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2691 SUPPORTED_10baseT_Full |
2692 SUPPORTED_100baseT_Half |
2693 SUPPORTED_100baseT_Full |
2694 SUPPORTED_1000baseT_Full |
2695 SUPPORTED_2500baseX_Full |
2696 SUPPORTED_10000baseT_Full |
2697 SUPPORTED_TP |
2698 SUPPORTED_FIBRE |
2699 SUPPORTED_Autoneg |
2700 SUPPORTED_Pause |
2701 SUPPORTED_Asym_Pause);
2702 bp->port.advertising[0] = bp->port.supported[0];
2703
2704 bp->link_params.bp = bp;
2705 bp->link_params.port = BP_PORT(bp);
2706 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2707 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2708 bp->link_params.req_line_speed[0] = SPEED_10000;
2709 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2710 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2711 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2712 bp->link_vars.line_speed = SPEED_10000;
2713 bp->link_vars.link_status =
2714 (LINK_STATUS_LINK_UP |
2715 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2716 bp->link_vars.link_up = 1;
2717 bp->link_vars.duplex = DUPLEX_FULL;
2718 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2719 __bnx2x_link_report(bp);
6495d15a
DK		 2720
2721 bnx2x_sample_bulletin(bp);
2722
2723 /* if bulletin board did not have an update for link status
2724 * __bnx2x_link_report will report current status
2725 * but it will NOT duplicate report in case of already reported
2726 * during sampling bulletin board.
2727 */
bb2a0f7a 2728 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2729 }
a2fbb9ea 2730}
a2fbb9ea 2731
a3348722
BW		 2732static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2733 u16 vlan_val, u8 allowed_prio)
2734{
86564c3f 2735 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2736 struct bnx2x_func_afex_update_params *f_update_params =
2737 &func_params.params.afex_update;
2738
2739 func_params.f_obj = &bp->func_obj;
2740 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2741
2742 /* no need to wait for RAMROD completion, so don't
2743 * set RAMROD_COMP_WAIT flag
2744 */
2745
2746 f_update_params->vif_id = vifid;
2747 f_update_params->afex_default_vlan = vlan_val;
2748 f_update_params->allowed_priorities = allowed_prio;
2749
2750 /* if ramrod can not be sent, response to MCP immediately */
2751 if (bnx2x_func_state_change(bp, &func_params) < 0)
2752 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2753
2754 return 0;
2755}
2756
2757static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2758 u16 vif_index, u8 func_bit_map)
2759{
86564c3f 2760 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2761 struct bnx2x_func_afex_viflists_params *update_params =
2762 &func_params.params.afex_viflists;
2763 int rc;
2764 u32 drv_msg_code;
2765
2766 /* validate only LIST_SET and LIST_GET are received from switch */
2767 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2768 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2769 cmd_type);
2770
2771 func_params.f_obj = &bp->func_obj;
2772 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2773
2774 /* set parameters according to cmd_type */
2775 update_params->afex_vif_list_command = cmd_type;
86564c3f 2776 update_params->vif_list_index = vif_index;
a3348722
BW		 2777 update_params->func_bit_map =
2778 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2779 update_params->func_to_clear = 0;
2780 drv_msg_code =
2781 (cmd_type == VIF_LIST_RULE_GET) ?
2782 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2783 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2784
2785 /* if ramrod can not be sent, respond to MCP immediately for
2786 * SET and GET requests (other are not triggered from MCP)
2787 */
2788 rc = bnx2x_func_state_change(bp, &func_params);
2789 if (rc < 0)
2790 bnx2x_fw_command(bp, drv_msg_code, 0);
2791
2792 return 0;
2793}
2794
2795static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2796{
2797 struct afex_stats afex_stats;
2798 u32 func = BP_ABS_FUNC(bp);
2799 u32 mf_config;
2800 u16 vlan_val;
2801 u32 vlan_prio;
2802 u16 vif_id;
2803 u8 allowed_prio;
2804 u8 vlan_mode;
2805 u32 addr_to_write, vifid, addrs, stats_type, i;
2806
2807 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2808 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2809 DP(BNX2X_MSG_MCP,
2810 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2811 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2812 }
2813
2814 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2815 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2816 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2817 DP(BNX2X_MSG_MCP,
2818 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2819 vifid, addrs);
2820 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2821 addrs);
2822 }
2823
2824 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2825 addr_to_write = SHMEM2_RD(bp,
2826 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2827 stats_type = SHMEM2_RD(bp,
2828 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2829
2830 DP(BNX2X_MSG_MCP,
2831 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2832 addr_to_write);
2833
2834 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2835
2836 /* write response to scratchpad, for MCP */
2837 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2838 REG_WR(bp, addr_to_write + i*sizeof(u32),
2839 *(((u32 *)(&afex_stats))+i));
2840
2841 /* send ack message to MCP */
2842 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2843 }
2844
2845 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2846 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2847 bp->mf_config[BP_VN(bp)] = mf_config;
2848 DP(BNX2X_MSG_MCP,
2849 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2850 mf_config);
2851
2852 /* if VIF_SET is "enabled" */
2853 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2854 /* set rate limit directly to internal RAM */
2855 struct cmng_init_input cmng_input;
2856 struct rate_shaping_vars_per_vn m_rs_vn;
2857 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2858 u32 addr = BAR_XSTRORM_INTMEM +
2859 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2860
2861 bp->mf_config[BP_VN(bp)] = mf_config;
2862
2863 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2864 m_rs_vn.vn_counter.rate =
2865 cmng_input.vnic_max_rate[BP_VN(bp)];
2866 m_rs_vn.vn_counter.quota =
2867 (m_rs_vn.vn_counter.rate *
2868 RS_PERIODIC_TIMEOUT_USEC) / 8;
2869
2870 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2871
2872 /* read relevant values from mf_cfg struct in shmem */
2873 vif_id =
2874 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2875 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2876 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2877 vlan_val =
2878 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2879 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2880 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2881 vlan_prio = (mf_config &
2882 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2883 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2884 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2885 vlan_mode =
2886 (MF_CFG_RD(bp,
2887 func_mf_config[func].afex_config) &
2888 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2889 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2890 allowed_prio =
2891 (MF_CFG_RD(bp,
2892 func_mf_config[func].afex_config) &
2893 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2894 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2895
2896 /* send ramrod to FW, return in case of failure */
2897 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2898 allowed_prio))
2899 return;
2900
2901 bp->afex_def_vlan_tag = vlan_val;
2902 bp->afex_vlan_mode = vlan_mode;
2903 } else {
2904 /* notify link down because BP->flags is disabled */
2905 bnx2x_link_report(bp);
2906
2907 /* send INVALID VIF ramrod to FW */
2908 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2909
2910 /* Reset the default afex VLAN */
2911 bp->afex_def_vlan_tag = -1;
2912 }
2913 }
2914}
2915
7609647e
YM		 2916static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2917{
2918 struct bnx2x_func_switch_update_params *switch_update_params;
2919 struct bnx2x_func_state_params func_params;
2920
2921 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2922 switch_update_params = &func_params.params.switch_update;
2923 func_params.f_obj = &bp->func_obj;
2924 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2925
230d00eb 2926 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
7609647e
YM		 2927 int func = BP_ABS_FUNC(bp);
2928 u32 val;
2929
2930 /* Re-learn the S-tag from shmem */
2931 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2932 FUNC_MF_CFG_E1HOV_TAG_MASK;
2933 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2934 bp->mf_ov = val;
2935 } else {
2936 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2937 goto fail;
2938 }
2939
2940 /* Configure new S-tag in LLH */
2941 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2942 bp->mf_ov);
2943
2944 /* Send Ramrod to update FW of change */
2945 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2946 &switch_update_params->changes);
2947 switch_update_params->vlan = bp->mf_ov;
2948
2949 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2950 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2951 bp->mf_ov);
2952 goto fail;
230d00eb
YM		 2953 } else {
2954 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2955 bp->mf_ov);
7609647e 2956 }
230d00eb
YM		 2957 } else {
2958 goto fail;
7609647e
YM		 2959 }
2960
230d00eb
YM		 2961 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2962 return;
7609647e
YM		 2963fail:
2964 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2965}
2966
34f80b04
EG		 2967static void bnx2x_pmf_update(struct bnx2x *bp)
2968{
2969 int port = BP_PORT(bp);
2970 u32 val;
2971
2972 bp->port.pmf = 1;
51c1a580 2973 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2974
3deb8167
YR		 2975 /*
2976 * We need the mb() to ensure the ordering between the writing to
2977 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2978 */
2979 smp_mb();
2980
2981 /* queue a periodic task */
2982 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2983
ef01854e
DK		 2984 bnx2x_dcbx_pmf_update(bp);
2985
34f80b04 2986 /* enable nig attention */
3395a033 2987 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2988 if (bp->common.int_block == INT_BLOCK_HC) {
2989 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2990 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2991 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2992 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2993 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2994 }
bb2a0f7a
YG		 2995
2996 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2997}
2998
c18487ee 2999/* end of Link */
a2fbb9ea
ET		 3000
3001/* slow path */
3002
3003/*
3004 * General service functions
3005 */
3006
2691d51d 3007/* send the MCP a request, block until there is a reply */
a22f0788 3008u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 3009{
f2e0899f 3010 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 3011 u32 seq;
2691d51d
EG		 3012 u32 rc = 0;
3013 u32 cnt = 1;
3014 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3015
c4ff7cbf 3016 mutex_lock(&bp->fw_mb_mutex);
a5971d43 3017 seq = ++bp->fw_seq;
f2e0899f
DK		 3018 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3019 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3020
754a2f52
DK		 3021 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3022 (command | seq), param);
2691d51d
EG		 3023
3024 do {
3025 /* let the FW do it's magic ... */
3026 msleep(delay);
3027
f2e0899f 3028 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 3029
c4ff7cbf
EG		 3030 /* Give the FW up to 5 second (500*10ms) */
3031 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 3032
3033 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3034 cnt*delay, rc, seq);
3035
3036 /* is this a reply to our command? */
3037 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3038 rc &= FW_MSG_CODE_MASK;
3039 else {
3040 /* FW BUG! */
3041 BNX2X_ERR("FW failed to respond!\n");
3042 bnx2x_fw_dump(bp);
3043 rc = 0;
3044 }
c4ff7cbf 3045 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 3046
3047 return rc;
3048}
3049
1191cb83
ED		 3050static void storm_memset_func_cfg(struct bnx2x *bp,
3051 struct tstorm_eth_function_common_config *tcfg,
3052 u16 abs_fid)
3053{
3054 size_t size = sizeof(struct tstorm_eth_function_common_config);
3055
3056 u32 addr = BAR_TSTRORM_INTMEM +
3057 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3058
3059 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3060}
3061
619c5cb6
VZ		 3062void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3063{
3064 if (CHIP_IS_E1x(bp)) {
3065 struct tstorm_eth_function_common_config tcfg = {0};
3066
3067 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3068 }
3069
3070 /* Enable the function in the FW */
3071 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3072 storm_memset_func_en(bp, p->func_id, 1);
3073
3074 /* spq */
05cc5a39 3075 if (p->spq_active) {
619c5cb6
VZ		 3076 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3077 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3078 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3079 }
3080}
3081
6383c0b3 3082/**
16a5fd92 3083 * bnx2x_get_common_flags - Return common flags
6383c0b3
AE		 3084 *
3085 * @bp device handle
3086 * @fp queue handle
3087 * @zero_stats TRUE if statistics zeroing is needed
3088 *
3089 * Return the flags that are common for the Tx-only and not normal connections.
3090 */
1191cb83
ED		 3091static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3092 struct bnx2x_fastpath *fp,
3093 bool zero_stats)
28912902 3094{
619c5cb6
VZ		 3095 unsigned long flags = 0;
3096
3097 /* PF driver will always initialize the Queue to an ACTIVE state */
3098 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 3099
6383c0b3 3100 /* tx only connections collect statistics (on the same index as the
91226790
DK		 3101 * parent connection). The statistics are zeroed when the parent
3102 * connection is initialized.
6383c0b3 3103 */
50f0a562
BW		 3104
3105 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3106 if (zero_stats)
3107 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3108
c14db202
YM		 3109 if (bp->flags & TX_SWITCHING)
3110 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3111
91226790 3112 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
e287a75c 3113 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
6383c0b3 3114
823e1d90
YM		 3115#ifdef BNX2X_STOP_ON_ERROR
3116 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3117#endif
3118
6383c0b3
AE		 3119 return flags;
3120}
3121
1191cb83
ED		 3122static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3123 struct bnx2x_fastpath *fp,
3124 bool leading)
6383c0b3
AE		 3125{
3126 unsigned long flags = 0;
3127
619c5cb6
VZ		 3128 /* calculate other queue flags */
3129 if (IS_MF_SD(bp))
3130 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 3131
a3348722 3132 if (IS_FCOE_FP(fp)) {
619c5cb6 3133 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 3134 /* For FCoE - force usage of default priority (for afex) */
3135 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3136 }
523224a3 3137
7e6b4d44 3138 if (fp->mode != TPA_MODE_DISABLED) {
619c5cb6 3139 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 3140 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 3141 if (fp->mode == TPA_MODE_GRO)
3142 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 3143 }
619c5cb6 3144
619c5cb6
VZ		 3145 if (leading) {
3146 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3147 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3148 }
523224a3 3149
619c5cb6
VZ		 3150 /* Always set HW VLAN stripping */
3151 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 3152
a3348722
BW		 3153 /* configure silent vlan removal */
3154 if (IS_MF_AFEX(bp))
3155 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3156
6383c0b3 3157 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 3158}
3159
619c5cb6 3160static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 3161 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3162 u8 cos)
619c5cb6
VZ		 3163{
3164 gen_init->stat_id = bnx2x_stats_id(fp);
3165 gen_init->spcl_id = fp->cl_id;
3166
3167 /* Always use mini-jumbo MTU for FCoE L2 ring */
3168 if (IS_FCOE_FP(fp))
3169 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3170 else
3171 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 3172
3173 gen_init->cos = cos;
02dc4025
YM		 3174
3175 gen_init->fp_hsi = ETH_FP_HSI_VERSION;
619c5cb6
VZ		 3176}
3177
3178static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 3179 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 3180 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 3181{
619c5cb6 3182 u8 max_sge = 0;
523224a3
DK		 3183 u16 sge_sz = 0;
3184 u16 tpa_agg_size = 0;
3185
7e6b4d44 3186 if (fp->mode != TPA_MODE_DISABLED) {
dfacf138
DK		 3187 pause->sge_th_lo = SGE_TH_LO(bp);
3188 pause->sge_th_hi = SGE_TH_HI(bp);
3189
3190 /* validate SGE ring has enough to cross high threshold */
3191 WARN_ON(bp->dropless_fc &&
3192 pause->sge_th_hi + FW_PREFETCH_CNT >
3193 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3194
924d75ab 3195 tpa_agg_size = TPA_AGG_SIZE;
523224a3
DK		 3196 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3197 SGE_PAGE_SHIFT;
3198 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3199 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
924d75ab 3200 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
523224a3
DK		 3201 }
3202
3203 /* pause - not for e1 */
3204 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3205 pause->bd_th_lo = BD_TH_LO(bp);
3206 pause->bd_th_hi = BD_TH_HI(bp);
3207
3208 pause->rcq_th_lo = RCQ_TH_LO(bp);
3209 pause->rcq_th_hi = RCQ_TH_HI(bp);
3210 /*
3211 * validate that rings have enough entries to cross
3212 * high thresholds
3213 */
3214 WARN_ON(bp->dropless_fc &&
3215 pause->bd_th_hi + FW_PREFETCH_CNT >
3216 bp->rx_ring_size);
3217 WARN_ON(bp->dropless_fc &&
3218 pause->rcq_th_hi + FW_PREFETCH_CNT >
3219 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3220
523224a3
DK		 3221 pause->pri_map = 1;
3222 }
3223
3224 /* rxq setup */
523224a3
DK		 3225 rxq_init->dscr_map = fp->rx_desc_mapping;
3226 rxq_init->sge_map = fp->rx_sge_mapping;
3227 rxq_init->rcq_map = fp->rx_comp_mapping;
3228 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3229
619c5cb6
VZ		 3230 /* This should be a maximum number of data bytes that may be
3231 * placed on the BD (not including paddings).
3232 */
e52fcb24 3233 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3cdeec22 3234 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3235
523224a3 3236 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3237 rxq_init->tpa_agg_sz = tpa_agg_size;
3238 rxq_init->sge_buf_sz = sge_sz;
3239 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3240 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3241 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3242
3243 /* Maximum number or simultaneous TPA aggregation for this Queue.
3244 *
2de67439 3245 * For PF Clients it should be the maximum available number.
619c5cb6
VZ		 3246 * VF driver(s) may want to define it to a smaller value.
3247 */
dfacf138 3248 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3249
523224a3
DK		 3250 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3251 rxq_init->fw_sb_id = fp->fw_sb_id;
3252
ec6ba945
VZ		 3253 if (IS_FCOE_FP(fp))
3254 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3255 else
6383c0b3 3256 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3257 /* configure silent vlan removal
3258 * if multi function mode is afex, then mask default vlan
3259 */
3260 if (IS_MF_AFEX(bp)) {
3261 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3262 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3263 }
523224a3
DK		 3264}
3265
619c5cb6 3266static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3267 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3268 u8 cos)
523224a3 3269{
65565884 3270 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3271 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3272 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3273 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3274
619c5cb6 3275 /*
16a5fd92 3276 * set the tss leading client id for TX classification ==
619c5cb6
VZ		 3277 * leading RSS client id
3278 */
3279 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3280
ec6ba945
VZ		 3281 if (IS_FCOE_FP(fp)) {
3282 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3283 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3284 }
523224a3
DK		 3285}
3286
8d96286a 3287static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3288{
3289 struct bnx2x_func_init_params func_init = {0};
523224a3 3290 struct event_ring_data eq_data = { {0} };
523224a3 3291
619c5cb6 3292 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3293 /* reset IGU PF statistics: MSIX + ATTN */
3294 /* PF */
3295 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3296 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3297 (CHIP_MODE_IS_4_PORT(bp) ?
3298 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3299 /* ATTN */
3300 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3301 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3302 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3303 (CHIP_MODE_IS_4_PORT(bp) ?
3304 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3305 }
3306
05cc5a39 3307 func_init.spq_active = true;
523224a3
DK		 3308 func_init.pf_id = BP_FUNC(bp);
3309 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3310 func_init.spq_map = bp->spq_mapping;
3311 func_init.spq_prod = bp->spq_prod_idx;
3312
3313 bnx2x_func_init(bp, &func_init);
3314
3315 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3316
3317 /*
619c5cb6
VZ		 3318 * Congestion management values depend on the link rate
3319 * There is no active link so initial link rate is set to 10 Gbps.
3320 * When the link comes up The congestion management values are
3321 * re-calculated according to the actual link rate.
3322 */
523224a3
DK		 3323 bp->link_vars.line_speed = SPEED_10000;
3324 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3325
3326 /* Only the PMF sets the HW */
3327 if (bp->port.pmf)
3328 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3329
86564c3f 3330 /* init Event Queue - PCI bus guarantees correct endianity*/
523224a3
DK		 3331 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3332 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3333 eq_data.producer = bp->eq_prod;
3334 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3335 eq_data.sb_id = DEF_SB_ID;
3336 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3337}
3338
523224a3
DK		 3339static void bnx2x_e1h_disable(struct bnx2x *bp)
3340{
3341 int port = BP_PORT(bp);
3342
619c5cb6 3343 bnx2x_tx_disable(bp);
523224a3
DK		 3344
3345 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3346}
3347
3348static void bnx2x_e1h_enable(struct bnx2x *bp)
3349{
3350 int port = BP_PORT(bp);
3351
7609647e
YM		 3352 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3353 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
523224a3 3354
16a5fd92 3355 /* Tx queue should be only re-enabled */
523224a3
DK		 3356 netif_tx_wake_all_queues(bp->dev);
3357
3358 /*
3359 * Should not call netif_carrier_on since it will be called if the link
3360 * is up when checking for link state
3361 */
3362}
3363
1d187b34
BW		 3364#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3365
3366static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3367{
3368 struct eth_stats_info *ether_stat =
3369 &bp->slowpath->drv_info_to_mcp.ether_stat;
3ec9f9ca
AE		 3370 struct bnx2x_vlan_mac_obj *mac_obj =
3371 &bp->sp_objs->mac_obj;
3372 int i;
1d187b34 3373
786fdf0b
DC		 3374 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3375 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3376
3ec9f9ca
AE		 3377 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3378 * mac_local field in ether_stat struct. The base address is offset by 2
3379 * bytes to account for the field being 8 bytes but a mac address is
3380 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3381 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3382 * allocated by the ether_stat struct, so the macs will land in their
3383 * proper positions.
3384 */
3385 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3386 memset(ether_stat->mac_local + i, 0,
3387 sizeof(ether_stat->mac_local[0]));
3388 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3389 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3390 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3391 ETH_ALEN);
1d187b34 3392 ether_stat->mtu_size = bp->dev->mtu;
1d187b34
BW		 3393 if (bp->dev->features & NETIF_F_RXCSUM)
3394 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3395 if (bp->dev->features & NETIF_F_TSO)
3396 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3397 ether_stat->feature_flags |= bp->common.boot_mode;
3398
3399 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3400
3401 ether_stat->txq_size = bp->tx_ring_size;
3402 ether_stat->rxq_size = bp->rx_ring_size;
0c757dee 3403
fcf93a0a 3404#ifdef CONFIG_BNX2X_SRIOV
0c757dee 3405 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
fcf93a0a 3406#endif
1d187b34
BW		 3407}
3408
3409static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3410{
3411 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3412 struct fcoe_stats_info *fcoe_stat =
3413 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3414
55c11941
MS		 3415 if (!CNIC_LOADED(bp))
3416 return;
3417
3ec9f9ca 3418 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3419
3420 fcoe_stat->qos_priority =
3421 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3422
3423 /* insert FCoE stats from ramrod response */
3424 if (!NO_FCOE(bp)) {
3425 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3426 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3427 tstorm_queue_statistics;
3428
3429 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3430 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3431 xstorm_queue_statistics;
3432
3433 struct fcoe_statistics_params *fw_fcoe_stat =
3434 &bp->fw_stats_data->fcoe;
3435
86564c3f
YM		 3436 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3437 fcoe_stat->rx_bytes_lo,
3438 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
1d187b34 3439
86564c3f
YM		 3440 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3441 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3442 fcoe_stat->rx_bytes_lo,
3443 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
1d187b34 3444
86564c3f
YM		 3445 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3446 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3447 fcoe_stat->rx_bytes_lo,
3448 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
1d187b34 3449
86564c3f
YM		 3450 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3451 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3452 fcoe_stat->rx_bytes_lo,
3453 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
1d187b34 3454
86564c3f
YM		 3455 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3456 fcoe_stat->rx_frames_lo,
3457 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
1d187b34 3458
86564c3f
YM		 3459 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3460 fcoe_stat->rx_frames_lo,
3461 fcoe_q_tstorm_stats->rcv_ucast_pkts);
1d187b34 3462
86564c3f
YM		 3463 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3464 fcoe_stat->rx_frames_lo,
3465 fcoe_q_tstorm_stats->rcv_bcast_pkts);
1d187b34 3466
86564c3f
YM		 3467 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3468 fcoe_stat->rx_frames_lo,
3469 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34 3470
86564c3f
YM		 3471 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3472 fcoe_stat->tx_bytes_lo,
3473 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
1d187b34 3474
86564c3f
YM		 3475 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3476 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3477 fcoe_stat->tx_bytes_lo,
3478 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
1d187b34 3479
86564c3f
YM		 3480 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3481 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3482 fcoe_stat->tx_bytes_lo,
3483 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
1d187b34 3484
86564c3f
YM		 3485 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3486 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3487 fcoe_stat->tx_bytes_lo,
3488 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
1d187b34 3489
86564c3f
YM		 3490 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3491 fcoe_stat->tx_frames_lo,
3492 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
1d187b34 3493
86564c3f
YM		 3494 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3495 fcoe_stat->tx_frames_lo,
3496 fcoe_q_xstorm_stats->ucast_pkts_sent);
1d187b34 3497
86564c3f
YM		 3498 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3499 fcoe_stat->tx_frames_lo,
3500 fcoe_q_xstorm_stats->bcast_pkts_sent);
1d187b34 3501
86564c3f
YM		 3502 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3503 fcoe_stat->tx_frames_lo,
3504 fcoe_q_xstorm_stats->mcast_pkts_sent);
1d187b34
BW		 3505 }
3506
1d187b34
BW		 3507 /* ask L5 driver to add data to the struct */
3508 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3509}
3510
3511static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3512{
3513 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3514 struct iscsi_stats_info *iscsi_stat =
3515 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3516
55c11941
MS		 3517 if (!CNIC_LOADED(bp))
3518 return;
3519
3ec9f9ca
AE		 3520 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3521 ETH_ALEN);
1d187b34
BW		 3522
3523 iscsi_stat->qos_priority =
3524 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3525
1d187b34
BW		 3526 /* ask L5 driver to add data to the struct */
3527 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3528}
3529
0793f83f
DK		 3530/* called due to MCP event (on pmf):
3531 * reread new bandwidth configuration
3532 * configure FW
3533 * notify others function about the change
3534 */
1191cb83 3535static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3536{
3537 if (bp->link_vars.link_up) {
3538 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3539 bnx2x_link_sync_notify(bp);
3540 }
3541 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3542}
3543
1191cb83 3544static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3545{
3546 bnx2x_config_mf_bw(bp);
3547 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3548}
3549
c8c60d88
YM		 3550static void bnx2x_handle_eee_event(struct bnx2x *bp)
3551{
3552 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3553 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3554}
3555
42f8277f
YM		 3556#define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3557#define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3558
1d187b34
BW		 3559static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3560{
3561 enum drv_info_opcode op_code;
3562 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
42f8277f
YM		 3563 bool release = false;
3564 int wait;
1d187b34
BW		 3565
3566 /* if drv_info version supported by MFW doesn't match - send NACK */
3567 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3568 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3569 return;
3570 }
3571
3572 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3573 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3574
42f8277f
YM		 3575 /* Must prevent other flows from accessing drv_info_to_mcp */
3576 mutex_lock(&bp->drv_info_mutex);
3577
1d187b34
BW		 3578 memset(&bp->slowpath->drv_info_to_mcp, 0,
3579 sizeof(union drv_info_to_mcp));
3580
3581 switch (op_code) {
3582 case ETH_STATS_OPCODE:
3583 bnx2x_drv_info_ether_stat(bp);
3584 break;
3585 case FCOE_STATS_OPCODE:
3586 bnx2x_drv_info_fcoe_stat(bp);
3587 break;
3588 case ISCSI_STATS_OPCODE:
3589 bnx2x_drv_info_iscsi_stat(bp);
3590 break;
3591 default:
3592 /* if op code isn't supported - send NACK */
3593 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
42f8277f 3594 goto out;
1d187b34
BW		 3595 }
3596
3597 /* if we got drv_info attn from MFW then these fields are defined in
3598 * shmem2 for sure
3599 */
3600 SHMEM2_WR(bp, drv_info_host_addr_lo,
3601 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3602 SHMEM2_WR(bp, drv_info_host_addr_hi,
3603 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3604
3605 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
42f8277f
YM		 3606
3607 /* Since possible management wants both this and get_driver_version
3608 * need to wait until management notifies us it finished utilizing
3609 * the buffer.
3610 */
3611 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3612 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3613 } else if (!bp->drv_info_mng_owner) {
3614 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3615
3616 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3617 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3618
3619 /* Management is done; need to clear indication */
3620 if (indication & bit) {
3621 SHMEM2_WR(bp, mfw_drv_indication,
3622 indication & ~bit);
3623 release = true;
3624 break;
3625 }
3626
3627 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3628 }
3629 }
3630 if (!release) {
3631 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3632 bp->drv_info_mng_owner = true;
3633 }
3634
3635out:
3636 mutex_unlock(&bp->drv_info_mutex);
3637}
3638
3639static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3640{
3641 u8 vals[4];
3642 int i = 0;
3643
3644 if (bnx2x_format) {
3645 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3646 &vals[0], &vals[1], &vals[2], &vals[3]);
3647 if (i > 0)
3648 vals[0] -= '0';
3649 } else {
3650 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3651 &vals[0], &vals[1], &vals[2], &vals[3]);
3652 }
3653
3654 while (i < 4)
3655 vals[i++] = 0;
3656
3657 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3658}
3659
3660void bnx2x_update_mng_version(struct bnx2x *bp)
3661{
3662 u32 iscsiver = DRV_VER_NOT_LOADED;
3663 u32 fcoever = DRV_VER_NOT_LOADED;
3664 u32 ethver = DRV_VER_NOT_LOADED;
3665 int idx = BP_FW_MB_IDX(bp);
3666 u8 *version;
3667
3668 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3669 return;
3670
3671 mutex_lock(&bp->drv_info_mutex);
3672 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3673 if (bp->drv_info_mng_owner)
3674 goto out;
3675
3676 if (bp->state != BNX2X_STATE_OPEN)
3677 goto out;
3678
3679 /* Parse ethernet driver version */
3680 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3681 if (!CNIC_LOADED(bp))
3682 goto out;
3683
3684 /* Try getting storage driver version via cnic */
3685 memset(&bp->slowpath->drv_info_to_mcp, 0,
3686 sizeof(union drv_info_to_mcp));
3687 bnx2x_drv_info_iscsi_stat(bp);
3688 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3689 iscsiver = bnx2x_update_mng_version_utility(version, false);
3690
3691 memset(&bp->slowpath->drv_info_to_mcp, 0,
3692 sizeof(union drv_info_to_mcp));
3693 bnx2x_drv_info_fcoe_stat(bp);
3694 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3695 fcoever = bnx2x_update_mng_version_utility(version, false);
3696
3697out:
3698 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3699 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3700 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3701
3702 mutex_unlock(&bp->drv_info_mutex);
3703
3704 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3705 ethver, iscsiver, fcoever);
1d187b34
BW		 3706}
3707
c48f350f
YM		 3708void bnx2x_update_mfw_dump(struct bnx2x *bp)
3709{
c48f350f
YM		 3710 u32 drv_ver;
3711 u32 valid_dump;
3712
3713 if (!SHMEM2_HAS(bp, drv_info))
3714 return;
3715
a19a19de
AB		 3716 /* Update Driver load time, possibly broken in y2038 */
3717 SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
c48f350f
YM		 3718
3719 drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3720 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3721
3722 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3723
3724 /* Check & notify On-Chip dump. */
3725 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3726
3727 if (valid_dump & FIRST_DUMP_VALID)
3728 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3729
3730 if (valid_dump & SECOND_DUMP_VALID)
3731 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3732}
3733
7609647e 3734static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
523224a3 3735{
7609647e
YM		 3736 u32 cmd_ok, cmd_fail;
3737
3738 /* sanity */
3739 if (event & DRV_STATUS_DCC_EVENT_MASK &&
3740 event & DRV_STATUS_OEM_EVENT_MASK) {
3741 BNX2X_ERR("Received simultaneous events %08x\n", event);
3742 return;
3743 }
523224a3 3744
7609647e
YM		 3745 if (event & DRV_STATUS_DCC_EVENT_MASK) {
3746 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3747 cmd_ok = DRV_MSG_CODE_DCC_OK;
3748 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3749 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3750 cmd_ok = DRV_MSG_CODE_OEM_OK;
3751 }
523224a3 3752
7609647e
YM		 3753 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3754
3755 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3756 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3757 /* This is the only place besides the function initialization
523224a3
DK		 3758 * where the bp->flags can change so it is done without any
3759 * locks
3760 */
f2e0899f 3761 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3762 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3763 bp->flags |= MF_FUNC_DIS;
3764
3765 bnx2x_e1h_disable(bp);
3766 } else {
51c1a580 3767 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3768 bp->flags &= ~MF_FUNC_DIS;
3769
3770 bnx2x_e1h_enable(bp);
3771 }
7609647e
YM		 3772 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3773 DRV_STATUS_OEM_DISABLE_ENABLE_PF);
523224a3 3774 }
7609647e
YM		 3775
3776 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3777 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
0793f83f 3778 bnx2x_config_mf_bw(bp);
7609647e
YM		 3779 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3780 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
523224a3
DK		 3781 }
3782
3783 /* Report results to MCP */
7609647e
YM		 3784 if (event)
3785 bnx2x_fw_command(bp, cmd_fail, 0);
523224a3 3786 else
7609647e 3787 bnx2x_fw_command(bp, cmd_ok, 0);
523224a3
DK		 3788}
3789
3790/* must be called under the spq lock */
1191cb83 3791static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3792{
3793 struct eth_spe *next_spe = bp->spq_prod_bd;
3794
3795 if (bp->spq_prod_bd == bp->spq_last_bd) {
3796 bp->spq_prod_bd = bp->spq;
3797 bp->spq_prod_idx = 0;
51c1a580 3798 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3799 } else {
3800 bp->spq_prod_bd++;
3801 bp->spq_prod_idx++;
3802 }
3803 return next_spe;
3804}
3805
3806/* must be called under the spq lock */
1191cb83 3807static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3808{
3809 int func = BP_FUNC(bp);
3810
53e51e2f
VZ		 3811 /*
3812 * Make sure that BD data is updated before writing the producer:
3813 * BD data is written to the memory, the producer is read from the
3814 * memory, thus we need a full memory barrier to ensure the ordering.
3815 */
3816 mb();
28912902 3817
523224a3 3818 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3819 bp->spq_prod_idx);
28912902
MC		 3820 mmiowb();
3821}
3822
619c5cb6
VZ		 3823/**
3824 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3825 *
3826 * @cmd: command to check
3827 * @cmd_type: command type
3828 */
1191cb83 3829static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3830{
3831 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3832 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3833 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3834 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3835 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3836 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3837 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3838 return true;
3839 else
3840 return false;
619c5cb6
VZ		 3841}
3842
619c5cb6
VZ		 3843/**
3844 * bnx2x_sp_post - place a single command on an SP ring
3845 *
3846 * @bp: driver handle
3847 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3848 * @cid: SW CID the command is related to
3849 * @data_hi: command private data address (high 32 bits)
3850 * @data_lo: command private data address (low 32 bits)
3851 * @cmd_type: command type (e.g. NONE, ETH)
3852 *
3853 * SP data is handled as if it's always an address pair, thus data fields are
3854 * not swapped to little endian in upper functions. Instead this function swaps
3855 * data as if it's two u32 fields.
3856 */
9f6c9258 3857int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3858 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3859{
28912902 3860 struct eth_spe *spe;
523224a3 3861 u16 type;
619c5cb6 3862 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3863
a2fbb9ea 3864#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3865 if (unlikely(bp->panic)) {
3866 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3867 return -EIO;
51c1a580 3868 }
a2fbb9ea
ET		 3869#endif
3870
34f80b04 3871 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3872
6e30dd4e
VZ		 3873 if (common) {
3874 if (!atomic_read(&bp->eq_spq_left)) {
3875 BNX2X_ERR("BUG! EQ ring full!\n");
3876 spin_unlock_bh(&bp->spq_lock);
3877 bnx2x_panic();
3878 return -EBUSY;
3879 }
3880 } else if (!atomic_read(&bp->cq_spq_left)) {
3881 BNX2X_ERR("BUG! SPQ ring full!\n");
3882 spin_unlock_bh(&bp->spq_lock);
3883 bnx2x_panic();
3884 return -EBUSY;
a2fbb9ea 3885 }
f1410647 3886
28912902
MC		 3887 spe = bnx2x_sp_get_next(bp);
3888
a2fbb9ea 3889 /* CID needs port number to be encoded int it */
28912902 3890 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3891 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3892 HW_CID(bp, cid));
523224a3 3893
14a94ebd
MK		 3894 /* In some cases, type may already contain the func-id
3895 * mainly in SRIOV related use cases, so we add it here only
3896 * if it's not already set.
3897 */
3898 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3899 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3900 SPE_HDR_CONN_TYPE;
3901 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3902 SPE_HDR_FUNCTION_ID);
3903 } else {
3904 type = cmd_type;
3905 }
a2fbb9ea 3906
523224a3
DK		 3907 spe->hdr.type = cpu_to_le16(type);
3908
3909 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3910 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3911
d6cae238
VZ		 3912 /*
3913 * It's ok if the actual decrement is issued towards the memory
3914 * somewhere between the spin_lock and spin_unlock. Thus no
16a5fd92 3915 * more explicit memory barrier is needed.
d6cae238
VZ		 3916 */
3917 if (common)
3918 atomic_dec(&bp->eq_spq_left);
3919 else
3920 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3921
51c1a580
MS		 3922 DP(BNX2X_MSG_SP,
3923 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3924 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3925 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3926 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3927 HW_CID(bp, cid), data_hi, data_lo, type,
3928 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3929
28912902 3930 bnx2x_sp_prod_update(bp);
34f80b04 3931 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3932 return 0;
3933}
3934
3935/* acquire split MCP access lock register */
4a37fb66 3936static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3937{
72fd0718 3938 u32 j, val;
34f80b04 3939 int rc = 0;
a2fbb9ea
ET		 3940
3941 might_sleep();
72fd0718 3942 for (j = 0; j < 1000; j++) {
3cdeec22
YM		 3943 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3944 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3945 if (val & MCPR_ACCESS_LOCK_LOCK)
a2fbb9ea
ET		 3946 break;
3947
639d65b8 3948 usleep_range(5000, 10000);
a2fbb9ea 3949 }
3cdeec22 3950 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
19680c48 3951 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3952 rc = -EBUSY;
3953 }
3954
3955 return rc;
3956}
3957
4a37fb66
YG		 3958/* release split MCP access lock register */
3959static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3960{
3cdeec22 3961 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
a2fbb9ea
ET		 3962}
3963
523224a3
DK		 3964#define BNX2X_DEF_SB_ATT_IDX 0x0001
3965#define BNX2X_DEF_SB_IDX 0x0002
3966
1191cb83 3967static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3968{
523224a3 3969 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3970 u16 rc = 0;
3971
3972 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3973 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3974 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3975 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3976 }
523224a3
DK		 3977
3978 if (bp->def_idx != def_sb->sp_sb.running_index) {
3979 bp->def_idx = def_sb->sp_sb.running_index;
3980 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3981 }
523224a3 3982
16a5fd92 3983 /* Do not reorder: indices reading should complete before handling */
523224a3 3984 barrier();
a2fbb9ea
ET		 3985 return rc;
3986}
3987
3988/*
3989 * slow path service functions
3990 */
3991
3992static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3993{
34f80b04 3994 int port = BP_PORT(bp);
a2fbb9ea
ET		 3995 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3996 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3997 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3998 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3999 u32 aeu_mask;
87942b46 4000 u32 nig_mask = 0;
f2e0899f 4001 u32 reg_addr;
a2fbb9ea 4002
a2fbb9ea
ET		 4003 if (bp->attn_state & asserted)
4004 BNX2X_ERR("IGU ERROR\n");
4005
3fcaf2e5
EG		 4006 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4007 aeu_mask = REG_RD(bp, aeu_addr);
4008
a2fbb9ea 4009 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 4010 aeu_mask, asserted);
72fd0718 4011 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 4012 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4013
3fcaf2e5
EG		 4014 REG_WR(bp, aeu_addr, aeu_mask);
4015 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 4016
3fcaf2e5 4017 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 4018 bp->attn_state |= asserted;
3fcaf2e5 4019 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 4020
4021 if (asserted & ATTN_HARD_WIRED_MASK) {
4022 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 4023
a5e9a7cf
EG		 4024 bnx2x_acquire_phy_lock(bp);
4025
877e9aa4 4026 /* save nig interrupt mask */
87942b46 4027 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 4028
361c391e
YR		 4029 /* If nig_mask is not set, no need to call the update
4030 * function.
4031 */
4032 if (nig_mask) {
4033 REG_WR(bp, nig_int_mask_addr, 0);
4034
4035 bnx2x_link_attn(bp);
4036 }
a2fbb9ea
ET		 4037
4038 /* handle unicore attn? */
4039 }
4040 if (asserted & ATTN_SW_TIMER_4_FUNC)
4041 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4042
4043 if (asserted & GPIO_2_FUNC)
4044 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4045
4046 if (asserted & GPIO_3_FUNC)
4047 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4048
4049 if (asserted & GPIO_4_FUNC)
4050 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4051
4052 if (port == 0) {
4053 if (asserted & ATTN_GENERAL_ATTN_1) {
4054 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4055 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4056 }
4057 if (asserted & ATTN_GENERAL_ATTN_2) {
4058 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4059 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4060 }
4061 if (asserted & ATTN_GENERAL_ATTN_3) {
4062 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4063 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4064 }
4065 } else {
4066 if (asserted & ATTN_GENERAL_ATTN_4) {
4067 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4068 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4069 }
4070 if (asserted & ATTN_GENERAL_ATTN_5) {
4071 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4072 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4073 }
4074 if (asserted & ATTN_GENERAL_ATTN_6) {
4075 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4076 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4077 }
4078 }
4079
4080 } /* if hardwired */
4081
f2e0899f
DK		 4082 if (bp->common.int_block == INT_BLOCK_HC)
4083 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4084 COMMAND_REG_ATTN_BITS_SET);
4085 else
4086 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4087
4088 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4089 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4090 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 4091
4092 /* now set back the mask */
a5e9a7cf 4093 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 4094 /* Verify that IGU ack through BAR was written before restoring
4095 * NIG mask. This loop should exit after 2-3 iterations max.
4096 */
4097 if (bp->common.int_block != INT_BLOCK_HC) {
4098 u32 cnt = 0, igu_acked;
4099 do {
4100 igu_acked = REG_RD(bp,
4101 IGU_REG_ATTENTION_ACK_BITS);
4102 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4103 (++cnt < MAX_IGU_ATTN_ACK_TO));
4104 if (!igu_acked)
4105 DP(NETIF_MSG_HW,
4106 "Failed to verify IGU ack on time\n");
4107 barrier();
4108 }
87942b46 4109 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 4110 bnx2x_release_phy_lock(bp);
4111 }
a2fbb9ea
ET		 4112}
4113
1191cb83 4114static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 4115{
4116 int port = BP_PORT(bp);
b7737c9b 4117 u32 ext_phy_config;
fd4ef40d 4118 /* mark the failure */
b7737c9b
YR		 4119 ext_phy_config =
4120 SHMEM_RD(bp,
4121 dev_info.port_hw_config[port].external_phy_config);
4122
4123 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4124 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 4125 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 4126 ext_phy_config);
fd4ef40d
EG		 4127
4128 /* log the failure */
51c1a580
MS		 4129 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4130 "Please contact OEM Support for assistance\n");
8304859a 4131
16a5fd92 4132 /* Schedule device reset (unload)
8304859a
AE		 4133 * This is due to some boards consuming sufficient power when driver is
4134 * up to overheat if fan fails.
4135 */
230bb0f3 4136 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
fd4ef40d 4137}
ab6ad5a4 4138
1191cb83 4139static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 4140{
34f80b04 4141 int port = BP_PORT(bp);
877e9aa4 4142 int reg_offset;
d90d96ba 4143 u32 val;
877e9aa4 4144
34f80b04
EG		 4145 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4146 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 4147
34f80b04 4148 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 4149
4150 val = REG_RD(bp, reg_offset);
4151 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4152 REG_WR(bp, reg_offset, val);
4153
4154 BNX2X_ERR("SPIO5 hw attention\n");
4155
fd4ef40d 4156 /* Fan failure attention */
d90d96ba 4157 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 4158 bnx2x_fan_failure(bp);
877e9aa4 4159 }
34f80b04 4160
3deb8167 4161 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 4162 bnx2x_acquire_phy_lock(bp);
4163 bnx2x_handle_module_detect_int(&bp->link_params);
4164 bnx2x_release_phy_lock(bp);
4165 }
4166
34f80b04
EG		 4167 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4168
4169 val = REG_RD(bp, reg_offset);
4170 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4171 REG_WR(bp, reg_offset, val);
4172
4173 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 4174 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 4175 bnx2x_panic();
4176 }
877e9aa4
ET		 4177}
4178
1191cb83 4179static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4180{
4181 u32 val;
4182
0626b899 4183 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 4184
4185 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4186 BNX2X_ERR("DB hw attention 0x%x\n", val);
4187 /* DORQ discard attention */
4188 if (val & 0x2)
4189 BNX2X_ERR("FATAL error from DORQ\n");
4190 }
34f80b04
EG		 4191
4192 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4193
4194 int port = BP_PORT(bp);
4195 int reg_offset;
4196
4197 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4198 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4199
4200 val = REG_RD(bp, reg_offset);
4201 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4202 REG_WR(bp, reg_offset, val);
4203
4204 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 4205 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 4206 bnx2x_panic();
4207 }
877e9aa4
ET		 4208}
4209
1191cb83 4210static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4211{
4212 u32 val;
4213
4214 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4215
4216 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4217 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4218 /* CFC error attention */
4219 if (val & 0x2)
4220 BNX2X_ERR("FATAL error from CFC\n");
4221 }
4222
4223 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 4224 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 4225 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 4226 /* RQ_USDMDP_FIFO_OVERFLOW */
4227 if (val & 0x18000)
4228 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 4229
4230 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4231 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4232 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4233 }
877e9aa4 4234 }
34f80b04
EG		 4235
4236 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4237
4238 int port = BP_PORT(bp);
4239 int reg_offset;
4240
4241 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4242 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4243
4244 val = REG_RD(bp, reg_offset);
4245 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4246 REG_WR(bp, reg_offset, val);
4247
4248 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 4249 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 4250 bnx2x_panic();
4251 }
877e9aa4
ET		 4252}
4253
1191cb83 4254static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 4255{
34f80b04
EG		 4256 u32 val;
4257
877e9aa4
ET		 4258 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4259
34f80b04
EG		 4260 if (attn & BNX2X_PMF_LINK_ASSERT) {
4261 int func = BP_FUNC(bp);
4262
4263 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 4264 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 4265 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4266 func_mf_config[BP_ABS_FUNC(bp)].config);
4267 val = SHMEM_RD(bp,
4268 func_mb[BP_FW_MB_IDX(bp)].drv_status);
7609647e
YM		 4269
4270 if (val & (DRV_STATUS_DCC_EVENT_MASK |
4271 DRV_STATUS_OEM_EVENT_MASK))
4272 bnx2x_oem_event(bp,
4273 (val & (DRV_STATUS_DCC_EVENT_MASK |
4274 DRV_STATUS_OEM_EVENT_MASK)));
0793f83f
DK		 4275
4276 if (val & DRV_STATUS_SET_MF_BW)
4277 bnx2x_set_mf_bw(bp);
4278
1d187b34
BW		 4279 if (val & DRV_STATUS_DRV_INFO_REQ)
4280 bnx2x_handle_drv_info_req(bp);
d16132ce
AE		 4281
4282 if (val & DRV_STATUS_VF_DISABLED)
370d4a26
YM		 4283 bnx2x_schedule_iov_task(bp,
4284 BNX2X_IOV_HANDLE_FLR);
d16132ce 4285
2691d51d 4286 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 4287 bnx2x_pmf_update(bp);
4288
e4901dde 4289 if (bp->port.pmf &&
785b9b1a
SR		 4290 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4291 bp->dcbx_enabled > 0)
e4901dde
VZ		 4292 /* start dcbx state machine */
4293 bnx2x_dcbx_set_params(bp,
4294 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 4295 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4296 bnx2x_handle_afex_cmd(bp,
4297 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 4298 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4299 bnx2x_handle_eee_event(bp);
7609647e
YM		 4300
4301 if (val & DRV_STATUS_OEM_UPDATE_SVID)
4302 bnx2x_handle_update_svid_cmd(bp);
4303
3deb8167
YR		 4304 if (bp->link_vars.periodic_flags &
4305 PERIODIC_FLAGS_LINK_EVENT) {
4306 /* sync with link */
4307 bnx2x_acquire_phy_lock(bp);
4308 bp->link_vars.periodic_flags &=
4309 ~PERIODIC_FLAGS_LINK_EVENT;
4310 bnx2x_release_phy_lock(bp);
4311 if (IS_MF(bp))
4312 bnx2x_link_sync_notify(bp);
4313 bnx2x_link_report(bp);
4314 }
4315 /* Always call it here: bnx2x_link_report() will
4316 * prevent the link indication duplication.
4317 */
4318 bnx2x__link_status_update(bp);
34f80b04 4319 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 4320
4321 BNX2X_ERR("MC assert!\n");
d6cae238 4322 bnx2x_mc_assert(bp);
877e9aa4
ET		 4323 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4324 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4325 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4326 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4327 bnx2x_panic();
4328
4329 } else if (attn & BNX2X_MCP_ASSERT) {
4330
4331 BNX2X_ERR("MCP assert!\n");
4332 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 4333 bnx2x_fw_dump(bp);
877e9aa4
ET		 4334
4335 } else
4336 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4337 }
4338
4339 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 4340 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4341 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 4342 val = CHIP_IS_E1(bp) ? 0 :
4343 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 4344 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4345 }
4346 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 4347 val = CHIP_IS_E1(bp) ? 0 :
4348 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 4349 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4350 }
877e9aa4 4351 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 4352 }
4353}
4354
c9ee9206
VZ		 4355/*
4356 * Bits map:
4357 * 0-7 - Engine0 load counter.
4358 * 8-15 - Engine1 load counter.
4359 * 16 - Engine0 RESET_IN_PROGRESS bit.
4360 * 17 - Engine1 RESET_IN_PROGRESS bit.
4361 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4362 * on the engine
4363 * 19 - Engine1 ONE_IS_LOADED.
4364 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4365 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4366 * just the one belonging to its engine).
4367 *
4368 */
4369#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4370
4371#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4372#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4373#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4374#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4375#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4376#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4377#define BNX2X_GLOBAL_RESET_BIT 0x00040000
4378
4379/*
4380 * Set the GLOBAL_RESET bit.
4381 *
4382 * Should be run under rtnl lock
4383 */
4384void bnx2x_set_reset_global(struct bnx2x *bp)
4385{
f16da43b
AE		 4386 u32 val;
4387 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4388 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4389 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4390 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4391}
4392
4393/*
4394 * Clear the GLOBAL_RESET bit.
4395 *
4396 * Should be run under rtnl lock
4397 */
1191cb83 4398static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4399{
f16da43b
AE		 4400 u32 val;
4401 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4402 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4403 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4404 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4405}
f85582f8 4406
72fd0718 4407/*
c9ee9206
VZ		 4408 * Checks the GLOBAL_RESET bit.
4409 *
72fd0718
VZ		 4410 * should be run under rtnl lock
4411 */
1191cb83 4412static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206 4413{
3cdeec22 4414 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4415
4416 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4417 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4418}
4419
4420/*
4421 * Clear RESET_IN_PROGRESS bit for the current engine.
4422 *
4423 * Should be run under rtnl lock
4424 */
1191cb83 4425static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4426{
f16da43b 4427 u32 val;
c9ee9206
VZ		 4428 u32 bit = BP_PATH(bp) ?
4429 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4430 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4431 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4432
4433 /* Clear the bit */
4434 val &= ~bit;
4435 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4436
4437 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4438}
4439
4440/*
c9ee9206
VZ		 4441 * Set RESET_IN_PROGRESS for the current engine.
4442 *
72fd0718
VZ		 4443 * should be run under rtnl lock
4444 */
c9ee9206 4445void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4446{
f16da43b 4447 u32 val;
c9ee9206
VZ		 4448 u32 bit = BP_PATH(bp) ?
4449 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4450 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4451 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4452
4453 /* Set the bit */
4454 val |= bit;
4455 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4456 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4457}
4458
4459/*
c9ee9206 4460 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4461 * should be run under rtnl lock
4462 */
c9ee9206 4463bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4464{
3cdeec22 4465 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4466 u32 bit = engine ?
4467 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4468
4469 /* return false if bit is set */
4470 return (val & bit) ? false : true;
72fd0718
VZ		 4471}
4472
4473/*
889b9af3 4474 * set pf load for the current pf.
c9ee9206 4475 *
72fd0718
VZ		 4476 * should be run under rtnl lock
4477 */
889b9af3 4478void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4479{
f16da43b 4480 u32 val1, val;
c9ee9206
VZ		 4481 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4482 BNX2X_PATH0_LOAD_CNT_MASK;
4483 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4484 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4485
f16da43b
AE		 4486 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4487 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4488
51c1a580 4489 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4490
c9ee9206
VZ		 4491 /* get the current counter value */
4492 val1 = (val & mask) >> shift;
4493
889b9af3
AE		 4494 /* set bit of that PF */
4495 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4496
4497 /* clear the old value */
4498 val &= ~mask;
4499
4500 /* set the new one */
4501 val |= ((val1 << shift) & mask);
4502
4503 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4504 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4505}
4506
c9ee9206 4507/**
889b9af3 4508 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4509 *
4510 * @bp: driver handle
4511 *
4512 * Should be run under rtnl lock.
4513 * Decrements the load counter for the current engine. Returns
889b9af3 4514 * whether other functions are still loaded
72fd0718 4515 */
889b9af3 4516bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4517{
f16da43b 4518 u32 val1, val;
c9ee9206
VZ		 4519 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4520 BNX2X_PATH0_LOAD_CNT_MASK;
4521 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4522 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4523
f16da43b
AE		 4524 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4525 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4526 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4527
c9ee9206
VZ		 4528 /* get the current counter value */
4529 val1 = (val & mask) >> shift;
4530
889b9af3
AE		 4531 /* clear bit of that PF */
4532 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4533
4534 /* clear the old value */
4535 val &= ~mask;
4536
4537 /* set the new one */
4538 val |= ((val1 << shift) & mask);
4539
4540 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4541 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4542 return val1 != 0;
72fd0718
VZ		 4543}
4544
4545/*
889b9af3 4546 * Read the load status for the current engine.
c9ee9206 4547 *
72fd0718
VZ		 4548 * should be run under rtnl lock
4549 */
1191cb83 4550static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4551{
c9ee9206
VZ		 4552 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4553 BNX2X_PATH0_LOAD_CNT_MASK);
4554 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4555 BNX2X_PATH0_LOAD_CNT_SHIFT);
4556 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4557
51c1a580 4558 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4559
4560 val = (val & mask) >> shift;
4561
51c1a580
MS		 4562 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4563 engine, val);
c9ee9206 4564
889b9af3 4565 return val != 0;
72fd0718
VZ		 4566}
4567
6bf07b8e
YM		 4568static void _print_parity(struct bnx2x *bp, u32 reg)
4569{
4570 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4571}
4572
1191cb83 4573static void _print_next_block(int idx, const char *blk)
72fd0718 4574{
f1deab50 4575 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4576}
4577
4293b9f5
DK		 4578static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4579 int *par_num, bool print)
72fd0718 4580{
4293b9f5
DK		 4581 u32 cur_bit;
4582 bool res;
4583 int i;
4584
4585 res = false;
4586
72fd0718 4587 for (i = 0; sig; i++) {
4293b9f5 4588 cur_bit = (0x1UL << i);
72fd0718 4589 if (sig & cur_bit) {
4293b9f5
DK		 4590 res |= true; /* Each bit is real error! */
4591
4592 if (print) {
4593 switch (cur_bit) {
4594 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4595 _print_next_block((*par_num)++, "BRB");
6bf07b8e
YM		 4596 _print_parity(bp,
4597 BRB1_REG_BRB1_PRTY_STS);
4293b9f5
DK		 4598 break;
4599 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4600 _print_next_block((*par_num)++,
4601 "PARSER");
6bf07b8e 4602 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4293b9f5
DK		 4603 break;
4604 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4605 _print_next_block((*par_num)++, "TSDM");
6bf07b8e
YM		 4606 _print_parity(bp,
4607 TSDM_REG_TSDM_PRTY_STS);
4293b9f5
DK		 4608 break;
4609 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4610 _print_next_block((*par_num)++,
c9ee9206 4611 "SEARCHER");
6bf07b8e 4612 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4293b9f5
DK		 4613 break;
4614 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4615 _print_next_block((*par_num)++, "TCM");
4616 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4617 break;
4618 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4619 _print_next_block((*par_num)++,
4620 "TSEMI");
6bf07b8e
YM		 4621 _print_parity(bp,
4622 TSEM_REG_TSEM_PRTY_STS_0);
4623 _print_parity(bp,
4624 TSEM_REG_TSEM_PRTY_STS_1);
4293b9f5
DK		 4625 break;
4626 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4627 _print_next_block((*par_num)++, "XPB");
6bf07b8e
YM		 4628 _print_parity(bp, GRCBASE_XPB +
4629 PB_REG_PB_PRTY_STS);
4293b9f5 4630 break;
6bf07b8e 4631 }
72fd0718
VZ		 4632 }
4633
4634 /* Clear the bit */
4635 sig &= ~cur_bit;
4636 }
4637 }
4638
4293b9f5 4639 return res;
72fd0718
VZ		 4640}
4641
4293b9f5
DK		 4642static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4643 int *par_num, bool *global,
6bf07b8e 4644 bool print)
72fd0718 4645{
4293b9f5
DK		 4646 u32 cur_bit;
4647 bool res;
4648 int i;
4649
4650 res = false;
4651
72fd0718 4652 for (i = 0; sig; i++) {
4293b9f5 4653 cur_bit = (0x1UL << i);
72fd0718 4654 if (sig & cur_bit) {
4293b9f5 4655 res |= true; /* Each bit is real error! */
72fd0718 4656 switch (cur_bit) {
c9ee9206 4657 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
6bf07b8e 4658 if (print) {
4293b9f5 4659 _print_next_block((*par_num)++, "PBF");
6bf07b8e
YM		 4660 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4661 }
72fd0718
VZ		 4662 break;
4663 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
6bf07b8e 4664 if (print) {
4293b9f5 4665 _print_next_block((*par_num)++, "QM");
6bf07b8e
YM		 4666 _print_parity(bp, QM_REG_QM_PRTY_STS);
4667 }
c9ee9206
VZ		 4668 break;
4669 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
6bf07b8e 4670 if (print) {
4293b9f5 4671 _print_next_block((*par_num)++, "TM");
6bf07b8e
YM		 4672 _print_parity(bp, TM_REG_TM_PRTY_STS);
4673 }
72fd0718
VZ		 4674 break;
4675 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
6bf07b8e 4676 if (print) {
4293b9f5 4677 _print_next_block((*par_num)++, "XSDM");
6bf07b8e
YM		 4678 _print_parity(bp,
4679 XSDM_REG_XSDM_PRTY_STS);
4680 }
c9ee9206
VZ		 4681 break;
4682 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
6bf07b8e 4683 if (print) {
4293b9f5 4684 _print_next_block((*par_num)++, "XCM");
6bf07b8e
YM		 4685 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4686 }
72fd0718
VZ		 4687 break;
4688 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
6bf07b8e 4689 if (print) {
4293b9f5
DK		 4690 _print_next_block((*par_num)++,
4691 "XSEMI");
6bf07b8e
YM		 4692 _print_parity(bp,
4693 XSEM_REG_XSEM_PRTY_STS_0);
4694 _print_parity(bp,
4695 XSEM_REG_XSEM_PRTY_STS_1);
4696 }
72fd0718
VZ		 4697 break;
4698 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
6bf07b8e 4699 if (print) {
4293b9f5 4700 _print_next_block((*par_num)++,
c9ee9206 4701 "DOORBELLQ");
6bf07b8e
YM		 4702 _print_parity(bp,
4703 DORQ_REG_DORQ_PRTY_STS);
4704 }
c9ee9206
VZ		 4705 break;
4706 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
6bf07b8e 4707 if (print) {
4293b9f5 4708 _print_next_block((*par_num)++, "NIG");
6bf07b8e
YM		 4709 if (CHIP_IS_E1x(bp)) {
4710 _print_parity(bp,
4711 NIG_REG_NIG_PRTY_STS);
4712 } else {
4713 _print_parity(bp,
4714 NIG_REG_NIG_PRTY_STS_0);
4715 _print_parity(bp,
4716 NIG_REG_NIG_PRTY_STS_1);
4717 }
4718 }
72fd0718
VZ		 4719 break;
4720 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206 4721 if (print)
4293b9f5 4722 _print_next_block((*par_num)++,
c9ee9206
VZ		 4723 "VAUX PCI CORE");
4724 *global = true;
72fd0718
VZ		 4725 break;
4726 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
6bf07b8e 4727 if (print) {
4293b9f5
DK		 4728 _print_next_block((*par_num)++,
4729 "DEBUG");
6bf07b8e
YM		 4730 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4731 }
72fd0718
VZ		 4732 break;
4733 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
6bf07b8e 4734 if (print) {
4293b9f5 4735 _print_next_block((*par_num)++, "USDM");
6bf07b8e
YM		 4736 _print_parity(bp,
4737 USDM_REG_USDM_PRTY_STS);
4738 }
72fd0718 4739 break;
8736c826 4740 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
6bf07b8e 4741 if (print) {
4293b9f5 4742 _print_next_block((*par_num)++, "UCM");
6bf07b8e
YM		 4743 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4744 }
8736c826 4745 break;
72fd0718 4746 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
6bf07b8e 4747 if (print) {
4293b9f5
DK		 4748 _print_next_block((*par_num)++,
4749 "USEMI");
6bf07b8e
YM		 4750 _print_parity(bp,
4751 USEM_REG_USEM_PRTY_STS_0);
4752 _print_parity(bp,
4753 USEM_REG_USEM_PRTY_STS_1);
4754 }
72fd0718
VZ		 4755 break;
4756 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
6bf07b8e 4757 if (print) {
4293b9f5 4758 _print_next_block((*par_num)++, "UPB");
6bf07b8e
YM		 4759 _print_parity(bp, GRCBASE_UPB +
4760 PB_REG_PB_PRTY_STS);
4761 }
72fd0718
VZ		 4762 break;
4763 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
6bf07b8e 4764 if (print) {
4293b9f5 4765 _print_next_block((*par_num)++, "CSDM");
6bf07b8e
YM		 4766 _print_parity(bp,
4767 CSDM_REG_CSDM_PRTY_STS);
4768 }
72fd0718 4769 break;
8736c826 4770 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
6bf07b8e 4771 if (print) {
4293b9f5 4772 _print_next_block((*par_num)++, "CCM");
6bf07b8e
YM		 4773 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4774 }
8736c826 4775 break;
72fd0718
VZ		 4776 }
4777
4778 /* Clear the bit */
4779 sig &= ~cur_bit;
4780 }
4781 }
4782
4293b9f5 4783 return res;
72fd0718
VZ		 4784}
4785
4293b9f5
DK		 4786static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4787 int *par_num, bool print)
72fd0718 4788{
4293b9f5
DK		 4789 u32 cur_bit;
4790 bool res;
4791 int i;
4792
4793 res = false;
4794
72fd0718 4795 for (i = 0; sig; i++) {
4293b9f5 4796 cur_bit = (0x1UL << i);
72fd0718 4797 if (sig & cur_bit) {
0c23ad37 4798 res = true; /* Each bit is real error! */
4293b9f5
DK		 4799 if (print) {
4800 switch (cur_bit) {
4801 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4802 _print_next_block((*par_num)++,
4803 "CSEMI");
6bf07b8e
YM		 4804 _print_parity(bp,
4805 CSEM_REG_CSEM_PRTY_STS_0);
4806 _print_parity(bp,
4807 CSEM_REG_CSEM_PRTY_STS_1);
4293b9f5
DK		 4808 break;
4809 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4810 _print_next_block((*par_num)++, "PXP");
6bf07b8e
YM		 4811 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4812 _print_parity(bp,
4813 PXP2_REG_PXP2_PRTY_STS_0);
4814 _print_parity(bp,
4815 PXP2_REG_PXP2_PRTY_STS_1);
4293b9f5
DK		 4816 break;
4817 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4818 _print_next_block((*par_num)++,
4819 "PXPPCICLOCKCLIENT");
4820 break;
4821 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4822 _print_next_block((*par_num)++, "CFC");
6bf07b8e
YM		 4823 _print_parity(bp,
4824 CFC_REG_CFC_PRTY_STS);
4293b9f5
DK		 4825 break;
4826 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4827 _print_next_block((*par_num)++, "CDU");
6bf07b8e 4828 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4293b9f5
DK		 4829 break;
4830 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4831 _print_next_block((*par_num)++, "DMAE");
6bf07b8e
YM		 4832 _print_parity(bp,
4833 DMAE_REG_DMAE_PRTY_STS);
4293b9f5
DK		 4834 break;
4835 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4836 _print_next_block((*par_num)++, "IGU");
6bf07b8e
YM		 4837 if (CHIP_IS_E1x(bp))
4838 _print_parity(bp,
4839 HC_REG_HC_PRTY_STS);
4840 else
4841 _print_parity(bp,
4842 IGU_REG_IGU_PRTY_STS);
4293b9f5
DK		 4843 break;
4844 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4845 _print_next_block((*par_num)++, "MISC");
6bf07b8e
YM		 4846 _print_parity(bp,
4847 MISC_REG_MISC_PRTY_STS);
4293b9f5 4848 break;
6bf07b8e 4849 }
72fd0718
VZ		 4850 }
4851
4852 /* Clear the bit */
4853 sig &= ~cur_bit;
4854 }
4855 }
4856
4293b9f5 4857 return res;
72fd0718
VZ		 4858}
4859
4293b9f5
DK		 4860static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4861 int *par_num, bool *global,
4862 bool print)
72fd0718 4863{
4293b9f5
DK		 4864 bool res = false;
4865 u32 cur_bit;
4866 int i;
4867
72fd0718 4868 for (i = 0; sig; i++) {
4293b9f5 4869 cur_bit = (0x1UL << i);
72fd0718
VZ		 4870 if (sig & cur_bit) {
4871 switch (cur_bit) {
4872 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206 4873 if (print)
4293b9f5
DK		 4874 _print_next_block((*par_num)++,
4875 "MCP ROM");
c9ee9206 4876 *global = true;
0c23ad37 4877 res = true;
72fd0718
VZ		 4878 break;
4879 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206 4880 if (print)
4293b9f5 4881 _print_next_block((*par_num)++,
c9ee9206
VZ		 4882 "MCP UMP RX");
4883 *global = true;
0c23ad37 4884 res = true;
72fd0718
VZ		 4885 break;
4886 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206 4887 if (print)
4293b9f5 4888 _print_next_block((*par_num)++,
c9ee9206
VZ		 4889 "MCP UMP TX");
4890 *global = true;
0c23ad37 4891 res = true;
72fd0718
VZ		 4892 break;
4893 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
ad6afbe9 4894 (*par_num)++;
4293b9f5
DK		 4895 /* clear latched SCPAD PATIRY from MCP */
4896 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4897 1UL << 10);
72fd0718
VZ		 4898 break;
4899 }
4900
4901 /* Clear the bit */
4902 sig &= ~cur_bit;
4903 }
4904 }
4905
4293b9f5 4906 return res;
72fd0718
VZ		 4907}
4908
4293b9f5
DK		 4909static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4910 int *par_num, bool print)
8736c826 4911{
4293b9f5
DK		 4912 u32 cur_bit;
4913 bool res;
4914 int i;
4915
4916 res = false;
4917
8736c826 4918 for (i = 0; sig; i++) {
4293b9f5 4919 cur_bit = (0x1UL << i);
8736c826 4920 if (sig & cur_bit) {
0c23ad37 4921 res = true; /* Each bit is real error! */
4293b9f5
DK		 4922 if (print) {
4923 switch (cur_bit) {
4924 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4925 _print_next_block((*par_num)++,
4926 "PGLUE_B");
6bf07b8e 4927 _print_parity(bp,
4293b9f5
DK		 4928 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4929 break;
4930 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4931 _print_next_block((*par_num)++, "ATC");
6bf07b8e
YM		 4932 _print_parity(bp,
4933 ATC_REG_ATC_PRTY_STS);
4293b9f5 4934 break;
6bf07b8e 4935 }
8736c826 4936 }
8736c826
VZ		 4937 /* Clear the bit */
4938 sig &= ~cur_bit;
4939 }
4940 }
4941
4293b9f5 4942 return res;
8736c826
VZ		 4943}
4944
1191cb83
ED		 4945static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4946 u32 *sig)
72fd0718 4947{
4293b9f5
DK		 4948 bool res = false;
4949
8736c826
VZ		 4950 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4951 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4952 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4953 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4954 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4955 int par_num = 0;
ad6afbe9 4956
51c1a580
MS		 4957 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4958 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4959 sig[0] & HW_PRTY_ASSERT_SET_0,
4960 sig[1] & HW_PRTY_ASSERT_SET_1,
4961 sig[2] & HW_PRTY_ASSERT_SET_2,
4962 sig[3] & HW_PRTY_ASSERT_SET_3,
4963 sig[4] & HW_PRTY_ASSERT_SET_4);
ad6afbe9
MC		 4964 if (print) {
4965 if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4966 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4967 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4968 (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4969 (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4970 netdev_err(bp->dev,
4971 "Parity errors detected in blocks: ");
4972 } else {
4973 print = false;
4974 }
4975 }
4293b9f5
DK		 4976 res |= bnx2x_check_blocks_with_parity0(bp,
4977 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4978 res |= bnx2x_check_blocks_with_parity1(bp,
4979 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4980 res |= bnx2x_check_blocks_with_parity2(bp,
4981 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4982 res |= bnx2x_check_blocks_with_parity3(bp,
4983 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4984 res |= bnx2x_check_blocks_with_parity4(bp,
4985 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
8736c826 4986
c9ee9206
VZ		 4987 if (print)
4988 pr_cont("\n");
4293b9f5 4989 }
8736c826 4990
4293b9f5 4991 return res;
72fd0718
VZ		 4992}
4993
c9ee9206
VZ		 4994/**
4995 * bnx2x_chk_parity_attn - checks for parity attentions.
4996 *
4997 * @bp: driver handle
4998 * @global: true if there was a global attention
4999 * @print: show parity attention in syslog
5000 */
5001bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 5002{
8736c826 5003 struct attn_route attn = { {0} };
72fd0718
VZ		 5004 int port = BP_PORT(bp);
5005
5006 attn.sig[0] = REG_RD(bp,
5007 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5008 port*4);
5009 attn.sig[1] = REG_RD(bp,
5010 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5011 port*4);
5012 attn.sig[2] = REG_RD(bp,
5013 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5014 port*4);
5015 attn.sig[3] = REG_RD(bp,
5016 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5017 port*4);
0a5ccb75
YM		 5018 /* Since MCP attentions can't be disabled inside the block, we need to
5019 * read AEU registers to see whether they're currently disabled
5020 */
5021 attn.sig[3] &= ((REG_RD(bp,
5022 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5023 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5024 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5025 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
72fd0718 5026
8736c826
VZ		 5027 if (!CHIP_IS_E1x(bp))
5028 attn.sig[4] = REG_RD(bp,
5029 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5030 port*4);
5031
5032 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 5033}
5034
1191cb83 5035static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 5036{
5037 u32 val;
5038 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5039
5040 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5041 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5042 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 5043 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 5044 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 5045 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 5046 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 5047 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 5048 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 5049 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 5050 if (val &
5051 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 5052 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 5053 if (val &
5054 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 5055 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 5056 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 5057 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 5058 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 5059 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 5060 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 5061 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 5062 }
5063 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5064 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5065 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5066 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5067 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5068 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 5069 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 5070 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 5071 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 5072 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 5073 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 5074 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5075 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5076 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 5077 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 5078 }
5079
5080 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5081 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5082 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5083 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5084 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5085 }
f2e0899f
DK		 5086}
5087
72fd0718
VZ		 5088static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5089{
5090 struct attn_route attn, *group_mask;
34f80b04 5091 int port = BP_PORT(bp);
877e9aa4 5092 int index;
a2fbb9ea
ET		 5093 u32 reg_addr;
5094 u32 val;
3fcaf2e5 5095 u32 aeu_mask;
c9ee9206 5096 bool global = false;
a2fbb9ea
ET		 5097
5098 /* need to take HW lock because MCP or other port might also
5099 try to handle this event */
4a37fb66 5100 bnx2x_acquire_alr(bp);
a2fbb9ea 5101
c9ee9206
VZ		 5102 if (bnx2x_chk_parity_attn(bp, &global, true)) {
5103#ifndef BNX2X_STOP_ON_ERROR
72fd0718 5104 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 5105 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 5106 /* Disable HW interrupts */
5107 bnx2x_int_disable(bp);
72fd0718
VZ		 5108 /* In case of parity errors don't handle attentions so that
5109 * other function would "see" parity errors.
5110 */
c9ee9206
VZ		 5111#else
5112 bnx2x_panic();
5113#endif
5114 bnx2x_release_alr(bp);
72fd0718
VZ		 5115 return;
5116 }
5117
a2fbb9ea
ET		 5118 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5119 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5120 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5121 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 5122 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5123 attn.sig[4] =
5124 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5125 else
5126 attn.sig[4] = 0;
5127
5128 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5129 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 5130
5131 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5132 if (deasserted & (1 << index)) {
72fd0718 5133 group_mask = &bp->attn_group[index];
a2fbb9ea 5134
51c1a580 5135 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 5136 index,
5137 group_mask->sig[0], group_mask->sig[1],
5138 group_mask->sig[2], group_mask->sig[3],
5139 group_mask->sig[4]);
a2fbb9ea 5140
f2e0899f
DK		 5141 bnx2x_attn_int_deasserted4(bp,
5142 attn.sig[4] & group_mask->sig[4]);
877e9aa4 5143 bnx2x_attn_int_deasserted3(bp,
72fd0718 5144 attn.sig[3] & group_mask->sig[3]);
877e9aa4 5145 bnx2x_attn_int_deasserted1(bp,
72fd0718 5146 attn.sig[1] & group_mask->sig[1]);
877e9aa4 5147 bnx2x_attn_int_deasserted2(bp,
72fd0718 5148 attn.sig[2] & group_mask->sig[2]);
877e9aa4 5149 bnx2x_attn_int_deasserted0(bp,
72fd0718 5150 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 5151 }
5152 }
5153
4a37fb66 5154 bnx2x_release_alr(bp);
a2fbb9ea 5155
f2e0899f
DK		 5156 if (bp->common.int_block == INT_BLOCK_HC)
5157 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5158 COMMAND_REG_ATTN_BITS_CLR);
5159 else
5160 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 5161
5162 val = ~deasserted;
f2e0899f
DK		 5163 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5164 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 5165 REG_WR(bp, reg_addr, val);
a2fbb9ea 5166
a2fbb9ea 5167 if (~bp->attn_state & deasserted)
3fcaf2e5 5168 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 5169
5170 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5171 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5172
3fcaf2e5
EG		 5173 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5174 aeu_mask = REG_RD(bp, reg_addr);
5175
5176 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5177 aeu_mask, deasserted);
72fd0718 5178 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 5179 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 5180
3fcaf2e5
EG		 5181 REG_WR(bp, reg_addr, aeu_mask);
5182 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 5183
5184 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5185 bp->attn_state &= ~deasserted;
5186 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5187}
5188
5189static void bnx2x_attn_int(struct bnx2x *bp)
5190{
5191 /* read local copy of bits */
68d59484
EG		 5192 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5193 attn_bits);
5194 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5195 attn_bits_ack);
a2fbb9ea
ET		 5196 u32 attn_state = bp->attn_state;
5197
5198 /* look for changed bits */
5199 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5200 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5201
5202 DP(NETIF_MSG_HW,
5203 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5204 attn_bits, attn_ack, asserted, deasserted);
5205
5206 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 5207 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 5208
5209 /* handle bits that were raised */
5210 if (asserted)
5211 bnx2x_attn_int_asserted(bp, asserted);
5212
5213 if (deasserted)
5214 bnx2x_attn_int_deasserted(bp, deasserted);
5215}
5216
619c5cb6
VZ		 5217void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5218 u16 index, u8 op, u8 update)
5219{
dc1ba591
AE		 5220 u32 igu_addr = bp->igu_base_addr;
5221 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 5222 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5223 igu_addr);
5224}
5225
1191cb83 5226static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 5227{
5228 /* No memory barriers */
5229 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5230 mmiowb(); /* keep prod updates ordered */
5231}
5232
523224a3
DK		 5233static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5234 union event_ring_elem *elem)
5235{
619c5cb6
VZ		 5236 u8 err = elem->message.error;
5237
523224a3 5238 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 5239 (cid < bp->cnic_eth_dev.starting_cid &&
5240 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 5241 return 1;
5242
5243 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5244
619c5cb6
VZ		 5245 if (unlikely(err)) {
5246
523224a3
DK		 5247 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5248 cid);
823e1d90 5249 bnx2x_panic_dump(bp, false);
523224a3 5250 }
619c5cb6 5251 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 5252 return 0;
5253}
523224a3 5254
1191cb83 5255static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5256{
5257 struct bnx2x_mcast_ramrod_params rparam;
5258 int rc;
5259
5260 memset(&rparam, 0, sizeof(rparam));
5261
5262 rparam.mcast_obj = &bp->mcast_obj;
5263
5264 netif_addr_lock_bh(bp->dev);
5265
5266 /* Clear pending state for the last command */
5267 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5268
5269 /* If there are pending mcast commands - send them */
5270 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5271 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5272 if (rc < 0)
5273 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5274 rc);
5275 }
5276
5277 netif_addr_unlock_bh(bp->dev);
5278}
5279
1191cb83
ED		 5280static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5281 union event_ring_elem *elem)
619c5cb6
VZ		 5282{
5283 unsigned long ramrod_flags = 0;
5284 int rc = 0;
9cd753a1
MS		 5285 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
5286 u32 cid = echo & BNX2X_SWCID_MASK;
619c5cb6
VZ		 5287 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5288
5289 /* Always push next commands out, don't wait here */
5290 __set_bit(RAMROD_CONT, &ramrod_flags);
5291
9cd753a1 5292 switch (echo >> BNX2X_SWCID_SHIFT) {
619c5cb6 5293 case BNX2X_FILTER_MAC_PENDING:
51c1a580 5294 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 5295 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 5296 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5297 else
15192a8c 5298 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6 5299
05cc5a39
YM		 5300 break;
5301 case BNX2X_FILTER_VLAN_PENDING:
5302 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5303 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
619c5cb6 5304 break;
619c5cb6 5305 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 5306 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 5307 /* This is only relevant for 57710 where multicast MACs are
5308 * configured as unicast MACs using the same ramrod.
5309 */
5310 bnx2x_handle_mcast_eqe(bp);
5311 return;
5312 default:
9cd753a1 5313 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
619c5cb6
VZ		 5314 return;
5315 }
5316
5317 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5318
5319 if (rc < 0)
5320 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5321 else if (rc > 0)
5322 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
619c5cb6
VZ		 5323}
5324
619c5cb6 5325static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 5326
1191cb83 5327static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5328{
5329 netif_addr_lock_bh(bp->dev);
5330
5331 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5332
5333 /* Send rx_mode command again if was requested */
5334 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5335 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 5336 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5337 &bp->sp_state))
5338 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5339 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5340 &bp->sp_state))
5341 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 5342
5343 netif_addr_unlock_bh(bp->dev);
5344}
5345
1191cb83 5346static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 5347 union event_ring_elem *elem)
5348{
5349 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5350 DP(BNX2X_MSG_SP,
5351 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5352 elem->message.data.vif_list_event.func_bit_map);
5353 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5354 elem->message.data.vif_list_event.func_bit_map);
5355 } else if (elem->message.data.vif_list_event.echo ==
5356 VIF_LIST_RULE_SET) {
5357 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5358 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5359 }
5360}
5361
5362/* called with rtnl_lock */
1191cb83 5363static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 5364{
5365 int q, rc;
5366 struct bnx2x_fastpath *fp;
5367 struct bnx2x_queue_state_params queue_params = {NULL};
5368 struct bnx2x_queue_update_params *q_update_params =
5369 &queue_params.params.update;
5370
2de67439 5371 /* Send Q update command with afex vlan removal values for all Qs */
a3348722
BW		 5372 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5373
5374 /* set silent vlan removal values according to vlan mode */
5375 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5376 &q_update_params->update_flags);
5377 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5378 &q_update_params->update_flags);
5379 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5380
5381 /* in access mode mark mask and value are 0 to strip all vlans */
5382 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5383 q_update_params->silent_removal_value = 0;
5384 q_update_params->silent_removal_mask = 0;
5385 } else {
5386 q_update_params->silent_removal_value =
5387 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5388 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5389 }
5390
5391 for_each_eth_queue(bp, q) {
5392 /* Set the appropriate Queue object */
5393 fp = &bp->fp[q];
15192a8c 5394 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5395
5396 /* send the ramrod */
5397 rc = bnx2x_queue_state_change(bp, &queue_params);
5398 if (rc < 0)
5399 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5400 q);
5401 }
5402
fea75645 5403 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
65565884 5404 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 5405 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5406
5407 /* clear pending completion bit */
5408 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5409
5410 /* mark latest Q bit */
4e857c58 5411 smp_mb__before_atomic();
a3348722 5412 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 5413 smp_mb__after_atomic();
a3348722
BW		 5414
5415 /* send Q update ramrod for FCoE Q */
5416 rc = bnx2x_queue_state_change(bp, &queue_params);
5417 if (rc < 0)
5418 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5419 q);
5420 } else {
5421 /* If no FCoE ring - ACK MCP now */
5422 bnx2x_link_report(bp);
5423 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5424 }
a3348722
BW		 5425}
5426
1191cb83 5427static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 5428 struct bnx2x *bp, u32 cid)
5429{
94f05b0f 5430 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 5431
5432 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 5433 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 5434 else
15192a8c 5435 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 5436}
5437
523224a3
DK		 5438static void bnx2x_eq_int(struct bnx2x *bp)
5439{
5440 u16 hw_cons, sw_cons, sw_prod;
5441 union event_ring_elem *elem;
55c11941 5442 u8 echo;
523224a3
DK		 5443 u32 cid;
5444 u8 opcode;
fd1fc79d 5445 int rc, spqe_cnt = 0;
619c5cb6
VZ		 5446 struct bnx2x_queue_sp_obj *q_obj;
5447 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5448 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 5449
5450 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5451
5452 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
16a5fd92 5453 * when we get the next-page we need to adjust so the loop
523224a3
DK		 5454 * condition below will be met. The next element is the size of a
5455 * regular element and hence incrementing by 1
5456 */
5457 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5458 hw_cons++;
5459
25985edc 5460 /* This function may never run in parallel with itself for a
523224a3
DK		 5461 * specific bp, thus there is no need in "paired" read memory
5462 * barrier here.
5463 */
5464 sw_cons = bp->eq_cons;
5465 sw_prod = bp->eq_prod;
5466
d6cae238 5467 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 5468 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 5469
5470 for (; sw_cons != hw_cons;
5471 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5472
523224a3
DK		 5473 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5474
fd1fc79d
AE		 5475 rc = bnx2x_iov_eq_sp_event(bp, elem);
5476 if (!rc) {
5477 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5478 rc);
5479 goto next_spqe;
5480 }
523224a3 5481
86564c3f 5482 opcode = elem->message.opcode;
523224a3
DK		 5483
5484 /* handle eq element */
5485 switch (opcode) {
fd1fc79d 5486 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
370d4a26
YM		 5487 bnx2x_vf_mbx_schedule(bp,
5488 &elem->message.data.vf_pf_event);
fd1fc79d
AE		 5489 continue;
5490
523224a3 5491 case EVENT_RING_OPCODE_STAT_QUERY:
76ca70fa
YM		 5492 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5493 "got statistics comp event %d\n",
5494 bp->stats_comp++);
523224a3 5495 /* nothing to do with stats comp */
d6cae238 5496 goto next_spqe;
523224a3
DK		 5497
5498 case EVENT_RING_OPCODE_CFC_DEL:
5499 /* handle according to cid range */
5500 /*
5501 * we may want to verify here that the bp state is
5502 * HALTING
5503 */
ca4f2d50
MS		 5504
5505 /* elem CID originates from FW; actually LE */
da472731 5506 cid = SW_CID(elem->message.data.cfc_del_event.cid);
ca4f2d50 5507
d6cae238 5508 DP(BNX2X_MSG_SP,
523224a3 5509 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 5510
5511 if (CNIC_LOADED(bp) &&
5512 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 5513 goto next_spqe;
55c11941 5514
619c5cb6
VZ		 5515 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5516
5517 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5518 break;
5519
523224a3 5520 goto next_spqe;
e4901dde
VZ		 5521
5522 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5523 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6ffa39f2 5524 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
6debea87
DK		 5525 if (f_obj->complete_cmd(bp, f_obj,
5526 BNX2X_F_CMD_TX_STOP))
5527 break;
e4901dde 5528 goto next_spqe;
619c5cb6 5529
e4901dde 5530 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5531 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6ffa39f2 5532 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
6debea87
DK		 5533 if (f_obj->complete_cmd(bp, f_obj,
5534 BNX2X_F_CMD_TX_START))
5535 break;
e4901dde 5536 goto next_spqe;
55c11941 5537
a3348722 5538 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5539 echo = elem->message.data.function_update_event.echo;
5540 if (echo == SWITCH_UPDATE) {
5541 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5542 "got FUNC_SWITCH_UPDATE ramrod\n");
5543 if (f_obj->complete_cmd(
5544 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5545 break;
a3348722 5546
55c11941 5547 } else {
230bb0f3
YM		 5548 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5549
55c11941
MS		 5550 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5551 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5552 f_obj->complete_cmd(bp, f_obj,
5553 BNX2X_F_CMD_AFEX_UPDATE);
5554
5555 /* We will perform the Queues update from
5556 * sp_rtnl task as all Queue SP operations
5557 * should run under rtnl_lock.
5558 */
230bb0f3 5559 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
55c11941 5560 }
a3348722 5561
a3348722
BW		 5562 goto next_spqe;
5563
5564 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5565 f_obj->complete_cmd(bp, f_obj,
5566 BNX2X_F_CMD_AFEX_VIFLISTS);
5567 bnx2x_after_afex_vif_lists(bp, elem);
5568 goto next_spqe;
619c5cb6 5569 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5570 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5571 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5572 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5573 break;
5574
5575 goto next_spqe;
5576
5577 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5578 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5579 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5580 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5581 break;
5582
5583 goto next_spqe;
eeed018c
MK		 5584
5585 case EVENT_RING_OPCODE_SET_TIMESYNC:
5586 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5587 "got set_timesync ramrod completion\n");
5588 if (f_obj->complete_cmd(bp, f_obj,
5589 BNX2X_F_CMD_SET_TIMESYNC))
5590 break;
5591 goto next_spqe;
523224a3
DK		 5592 }
5593
5594 switch (opcode | bp->state) {
619c5cb6
VZ		 5595 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5596 BNX2X_STATE_OPEN):
5597 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5598 BNX2X_STATE_OPENING_WAIT4_PORT):
28311f8e
YM		 5599 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5600 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5601 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
9cd753a1 5602 SW_CID(elem->message.data.eth_event.echo));
619c5cb6 5603 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5604 break;
5605
619c5cb6
VZ		 5606 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5607 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5608 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5609 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5610 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5611 BNX2X_STATE_OPEN):
5612 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5613 BNX2X_STATE_DIAG):
5614 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5615 BNX2X_STATE_CLOSING_WAIT4_HALT):
05cc5a39 5616 DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
619c5cb6 5617 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5618 break;
5619
619c5cb6
VZ		 5620 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5621 BNX2X_STATE_OPEN):
5622 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5623 BNX2X_STATE_DIAG):
5624 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5625 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5626 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5627 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5628 break;
5629
619c5cb6
VZ		 5630 case (EVENT_RING_OPCODE_FILTERS_RULES |
5631 BNX2X_STATE_OPEN):
5632 case (EVENT_RING_OPCODE_FILTERS_RULES |
5633 BNX2X_STATE_DIAG):
5634 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5635 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5636 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5637 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5638 break;
5639 default:
5640 /* unknown event log error and continue */
619c5cb6
VZ		 5641 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5642 elem->message.opcode, bp->state);
523224a3
DK		 5643 }
5644next_spqe:
5645 spqe_cnt++;
5646 } /* for */
5647
4e857c58 5648 smp_mb__before_atomic();
6e30dd4e 5649 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5650
5651 bp->eq_cons = sw_cons;
5652 bp->eq_prod = sw_prod;
5653 /* Make sure that above mem writes were issued towards the memory */
5654 smp_wmb();
5655
5656 /* update producer */
5657 bnx2x_update_eq_prod(bp, bp->eq_prod);
5658}
5659
a2fbb9ea
ET		 5660static void bnx2x_sp_task(struct work_struct *work)
5661{
1cf167f2 5662 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5663
fd1fc79d 5664 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5665
16a5fd92 5666 /* make sure the atomic interrupt_occurred has been written */
fd1fc79d
AE		 5667 smp_rmb();
5668 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5669
fd1fc79d
AE		 5670 /* what work needs to be performed? */
5671 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5672
fd1fc79d
AE		 5673 DP(BNX2X_MSG_SP, "status %x\n", status);
5674 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5675 atomic_set(&bp->interrupt_occurred, 0);
5676
5677 /* HW attentions */
5678 if (status & BNX2X_DEF_SB_ATT_IDX) {
5679 bnx2x_attn_int(bp);
5680 status &= ~BNX2X_DEF_SB_ATT_IDX;
5681 }
5682
5683 /* SP events: STAT_QUERY and others */
5684 if (status & BNX2X_DEF_SB_IDX) {
5685 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5686
7e88009b 5687 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5688 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5689 /* Prevent local bottom-halves from running as
5690 * we are going to change the local NAPI list.
5691 */
5692 local_bh_disable();
5693 napi_schedule(&bnx2x_fcoe(bp, napi));
5694 local_bh_enable();
5695 }
5696
5697 /* Handle EQ completions */
5698 bnx2x_eq_int(bp);
5699 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5700 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5701
5702 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5703 }
55c11941 5704
fd1fc79d
AE		 5705 /* if status is non zero then perhaps something went wrong */
5706 if (unlikely(status))
5707 DP(BNX2X_MSG_SP,
5708 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5709
fd1fc79d
AE		 5710 /* ack status block only if something was actually handled */
5711 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5712 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
cdaa7cb8
VZ		 5713 }
5714
a3348722
BW		 5715 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5716 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5717 &bp->sp_state)) {
5718 bnx2x_link_report(bp);
5719 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5720 }
a2fbb9ea
ET		 5721}
5722
9f6c9258 5723irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5724{
5725 struct net_device *dev = dev_instance;
5726 struct bnx2x *bp = netdev_priv(dev);
5727
523224a3
DK		 5728 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5729 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5730
5731#ifdef BNX2X_STOP_ON_ERROR
5732 if (unlikely(bp->panic))
5733 return IRQ_HANDLED;
5734#endif
5735
55c11941 5736 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5737 struct cnic_ops *c_ops;
5738
5739 rcu_read_lock();
5740 c_ops = rcu_dereference(bp->cnic_ops);
5741 if (c_ops)
5742 c_ops->cnic_handler(bp->cnic_data, NULL);
5743 rcu_read_unlock();
5744 }
55c11941 5745
fd1fc79d
AE		 5746 /* schedule sp task to perform default status block work, ack
5747 * attentions and enable interrupts.
5748 */
5749 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5750
5751 return IRQ_HANDLED;
5752}
5753
5754/* end of slow path */
5755
619c5cb6
VZ		 5756void bnx2x_drv_pulse(struct bnx2x *bp)
5757{
5758 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5759 bp->fw_drv_pulse_wr_seq);
5760}
5761
a2fbb9ea
ET		 5762static void bnx2x_timer(unsigned long data)
5763{
5764 struct bnx2x *bp = (struct bnx2x *) data;
5765
5766 if (!netif_running(bp->dev))
5767 return;
5768
67c431a5
AE		 5769 if (IS_PF(bp) &&
5770 !BP_NOMCP(bp)) {
f2e0899f 5771 int mb_idx = BP_FW_MB_IDX(bp);
4c868664
EG		 5772 u16 drv_pulse;
5773 u16 mcp_pulse;
a2fbb9ea
ET		 5774
5775 ++bp->fw_drv_pulse_wr_seq;
5776 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
a2fbb9ea 5777 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5778 bnx2x_drv_pulse(bp);
a2fbb9ea 5779
f2e0899f 5780 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5781 MCP_PULSE_SEQ_MASK);
5782 /* The delta between driver pulse and mcp response
4c868664
EG		 5783 * should not get too big. If the MFW is more than 5 pulses
5784 * behind, we should worry about it enough to generate an error
5785 * log.
a2fbb9ea 5786 */
4c868664
EG		 5787 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5788 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
a2fbb9ea 5789 drv_pulse, mcp_pulse);
a2fbb9ea
ET		 5790 }
5791
f34d28ea 5792 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5793 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5794
abc5a021 5795 /* sample pf vf bulletin board for new posts from pf */
37173488
YM		 5796 if (IS_VF(bp))
5797 bnx2x_timer_sriov(bp);
78c3bcc5 5798
a2fbb9ea
ET		 5799 mod_timer(&bp->timer, jiffies + bp->current_interval);
5800}
5801
5802/* end of Statistics */
5803
5804/* nic init */
5805
5806/*
5807 * nic init service functions
5808 */
5809
1191cb83 5810static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5811{
523224a3
DK		 5812 u32 i;
5813 if (!(len%4) && !(addr%4))
5814 for (i = 0; i < len; i += 4)
5815 REG_WR(bp, addr + i, fill);
5816 else
5817 for (i = 0; i < len; i++)
5818 REG_WR8(bp, addr + i, fill);
34f80b04
EG		 5819}
5820
523224a3 5821/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5822static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5823 int fw_sb_id,
5824 u32 *sb_data_p,
5825 u32 data_size)
34f80b04 5826{
a2fbb9ea 5827 int index;
523224a3
DK		 5828 for (index = 0; index < data_size; index++)
5829 REG_WR(bp, BAR_CSTRORM_INTMEM +
5830 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5831 sizeof(u32)*index,
5832 *(sb_data_p + index));
5833}
a2fbb9ea 5834
1191cb83 5835static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5836{
5837 u32 *sb_data_p;
5838 u32 data_size = 0;
f2e0899f 5839 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5840 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5841
523224a3 5842 /* disable the function first */
619c5cb6 5843 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5844 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5845 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5846 sb_data_e2.common.p_func.vf_valid = false;
5847 sb_data_p = (u32 *)&sb_data_e2;
5848 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5849 } else {
5850 memset(&sb_data_e1x, 0,
5851 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5852 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5853 sb_data_e1x.common.p_func.vf_valid = false;
5854 sb_data_p = (u32 *)&sb_data_e1x;
5855 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5856 }
523224a3 5857 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5858
523224a3
DK		 5859 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5860 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5861 CSTORM_STATUS_BLOCK_SIZE);
5862 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5863 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5864 CSTORM_SYNC_BLOCK_SIZE);
5865}
34f80b04 5866
523224a3 5867/* helper: writes SP SB data to FW */
1191cb83 5868static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5869 struct hc_sp_status_block_data *sp_sb_data)
5870{
5871 int func = BP_FUNC(bp);
5872 int i;
5873 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5874 REG_WR(bp, BAR_CSTRORM_INTMEM +
5875 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5876 i*sizeof(u32),
5877 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5878}
5879
1191cb83 5880static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5881{
5882 int func = BP_FUNC(bp);
523224a3
DK		 5883 struct hc_sp_status_block_data sp_sb_data;
5884 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5885
619c5cb6 5886 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5887 sp_sb_data.p_func.vf_valid = false;
5888
5889 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5890
5891 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5892 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5893 CSTORM_SP_STATUS_BLOCK_SIZE);
5894 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5895 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5896 CSTORM_SP_SYNC_BLOCK_SIZE);
523224a3
DK		 5897}
5898
1191cb83 5899static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5900 int igu_sb_id, int igu_seg_id)
5901{
5902 hc_sm->igu_sb_id = igu_sb_id;
5903 hc_sm->igu_seg_id = igu_seg_id;
5904 hc_sm->timer_value = 0xFF;
5905 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5906}
5907
150966ad 5908/* allocates state machine ids. */
1191cb83 5909static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5910{
5911 /* zero out state machine indices */
5912 /* rx indices */
5913 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5914
5915 /* tx indices */
5916 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5917 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5918 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5919 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5920
5921 /* map indices */
5922 /* rx indices */
5923 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5924 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5925
5926 /* tx indices */
5927 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5928 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5929 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5930 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5931 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5932 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5933 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5934 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5935}
5936
b93288d5 5937void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5938 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5939{
523224a3
DK		 5940 int igu_seg_id;
5941
f2e0899f 5942 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5943 struct hc_status_block_data_e1x sb_data_e1x;
5944 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5945 int data_size;
5946 u32 *sb_data_p;
5947
f2e0899f
DK		 5948 if (CHIP_INT_MODE_IS_BC(bp))
5949 igu_seg_id = HC_SEG_ACCESS_NORM;
5950 else
5951 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5952
5953 bnx2x_zero_fp_sb(bp, fw_sb_id);
5954
619c5cb6 5955 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5956 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5957 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5958 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5959 sb_data_e2.common.p_func.vf_id = vfid;
5960 sb_data_e2.common.p_func.vf_valid = vf_valid;
5961 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5962 sb_data_e2.common.same_igu_sb_1b = true;
5963 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5964 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5965 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5966 sb_data_p = (u32 *)&sb_data_e2;
5967 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5968 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5969 } else {
5970 memset(&sb_data_e1x, 0,
5971 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5972 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5973 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5974 sb_data_e1x.common.p_func.vf_id = 0xff;
5975 sb_data_e1x.common.p_func.vf_valid = false;
5976 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5977 sb_data_e1x.common.same_igu_sb_1b = true;
5978 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5979 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5980 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5981 sb_data_p = (u32 *)&sb_data_e1x;
5982 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5983 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5984 }
523224a3
DK		 5985
5986 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5987 igu_sb_id, igu_seg_id);
5988 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5989 igu_sb_id, igu_seg_id);
5990
51c1a580 5991 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3 5992
86564c3f 5993 /* write indices to HW - PCI guarantees endianity of regpairs */
523224a3
DK		 5994 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5995}
5996
619c5cb6 5997static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5998 u16 tx_usec, u16 rx_usec)
5999{
6383c0b3 6000 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 6001 false, rx_usec);
6383c0b3
AE		 6002 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6003 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6004 tx_usec);
6005 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6006 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6007 tx_usec);
6008 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6009 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6010 tx_usec);
523224a3 6011}
f2e0899f 6012
523224a3
DK		 6013static void bnx2x_init_def_sb(struct bnx2x *bp)
6014{
6015 struct host_sp_status_block *def_sb = bp->def_status_blk;
6016 dma_addr_t mapping = bp->def_status_blk_mapping;
6017 int igu_sp_sb_index;
6018 int igu_seg_id;
34f80b04
EG		 6019 int port = BP_PORT(bp);
6020 int func = BP_FUNC(bp);
f2eaeb58 6021 int reg_offset, reg_offset_en5;
a2fbb9ea 6022 u64 section;
523224a3
DK		 6023 int index;
6024 struct hc_sp_status_block_data sp_sb_data;
6025 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6026
f2e0899f
DK		 6027 if (CHIP_INT_MODE_IS_BC(bp)) {
6028 igu_sp_sb_index = DEF_SB_IGU_ID;
6029 igu_seg_id = HC_SEG_ACCESS_DEF;
6030 } else {
6031 igu_sp_sb_index = bp->igu_dsb_id;
6032 igu_seg_id = IGU_SEG_ACCESS_DEF;
6033 }
a2fbb9ea
ET		 6034
6035 /* ATTN */
523224a3 6036 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 6037 atten_status_block);
523224a3 6038 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 6039
49d66772
ET		 6040 bp->attn_state = 0;
6041
a2fbb9ea
ET		 6042 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6043 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 6044 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6045 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 6046 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 6047 int sindex;
6048 /* take care of sig[0]..sig[4] */
6049 for (sindex = 0; sindex < 4; sindex++)
6050 bp->attn_group[index].sig[sindex] =
6051 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 6052
619c5cb6 6053 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6054 /*
6055 * enable5 is separate from the rest of the registers,
6056 * and therefore the address skip is 4
6057 * and not 16 between the different groups
6058 */
6059 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 6060 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 6061 else
6062 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 6063 }
6064
f2e0899f
DK		 6065 if (bp->common.int_block == INT_BLOCK_HC) {
6066 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6067 HC_REG_ATTN_MSG0_ADDR_L);
6068
6069 REG_WR(bp, reg_offset, U64_LO(section));
6070 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 6071 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6072 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6073 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6074 }
a2fbb9ea 6075
523224a3
DK		 6076 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6077 sp_sb);
a2fbb9ea 6078
523224a3 6079 bnx2x_zero_sp_sb(bp);
a2fbb9ea 6080
86564c3f 6081 /* PCI guarantees endianity of regpairs */
619c5cb6 6082 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 6083 sp_sb_data.host_sb_addr.lo = U64_LO(section);
6084 sp_sb_data.host_sb_addr.hi = U64_HI(section);
6085 sp_sb_data.igu_sb_id = igu_sp_sb_index;
6086 sp_sb_data.igu_seg_id = igu_seg_id;
6087 sp_sb_data.p_func.pf_id = func;
f2e0899f 6088 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 6089 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 6090
523224a3 6091 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 6092
523224a3 6093 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 6094}
6095
9f6c9258 6096void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 6097{
a2fbb9ea
ET		 6098 int i;
6099
ec6ba945 6100 for_each_eth_queue(bp, i)
523224a3 6101 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 6102 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 6103}
6104
a2fbb9ea
ET		 6105static void bnx2x_init_sp_ring(struct bnx2x *bp)
6106{
a2fbb9ea 6107 spin_lock_init(&bp->spq_lock);
6e30dd4e 6108 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 6109
a2fbb9ea 6110 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 6111 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6112 bp->spq_prod_bd = bp->spq;
6113 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 6114}
6115
523224a3 6116static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 6117{
6118 int i;
523224a3
DK		 6119 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6120 union event_ring_elem *elem =
6121 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 6122
523224a3
DK		 6123 elem->next_page.addr.hi =
6124 cpu_to_le32(U64_HI(bp->eq_mapping +
6125 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6126 elem->next_page.addr.lo =
6127 cpu_to_le32(U64_LO(bp->eq_mapping +
6128 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 6129 }
523224a3
DK		 6130 bp->eq_cons = 0;
6131 bp->eq_prod = NUM_EQ_DESC;
6132 bp->eq_cons_sb = BNX2X_EQ_INDEX;
16a5fd92 6133 /* we want a warning message before it gets wrought... */
6e30dd4e
VZ		 6134 atomic_set(&bp->eq_spq_left,
6135 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 6136}
6137
619c5cb6 6138/* called with netif_addr_lock_bh() */
a8f47eb7 6139static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6140 unsigned long rx_mode_flags,
6141 unsigned long rx_accept_flags,
6142 unsigned long tx_accept_flags,
6143 unsigned long ramrod_flags)
ab532cf3 6144{
619c5cb6
VZ		 6145 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6146 int rc;
6147
6148 memset(&ramrod_param, 0, sizeof(ramrod_param));
6149
6150 /* Prepare ramrod parameters */
6151 ramrod_param.cid = 0;
6152 ramrod_param.cl_id = cl_id;
6153 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6154 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 6155
619c5cb6
VZ		 6156 ramrod_param.pstate = &bp->sp_state;
6157 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 6158
619c5cb6
VZ		 6159 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6160 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6161
6162 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6163
6164 ramrod_param.ramrod_flags = ramrod_flags;
6165 ramrod_param.rx_mode_flags = rx_mode_flags;
6166
6167 ramrod_param.rx_accept_flags = rx_accept_flags;
6168 ramrod_param.tx_accept_flags = tx_accept_flags;
6169
6170 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6171 if (rc < 0) {
6172 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
924d75ab 6173 return rc;
619c5cb6 6174 }
924d75ab
YM		 6175
6176 return 0;
a2fbb9ea
ET		 6177}
6178
86564c3f
YM		 6179static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6180 unsigned long *rx_accept_flags,
6181 unsigned long *tx_accept_flags)
471de716 6182{
924d75ab
YM		 6183 /* Clear the flags first */
6184 *rx_accept_flags = 0;
6185 *tx_accept_flags = 0;
619c5cb6 6186
924d75ab 6187 switch (rx_mode) {
619c5cb6
VZ		 6188 case BNX2X_RX_MODE_NONE:
6189 /*
6190 * 'drop all' supersedes any accept flags that may have been
6191 * passed to the function.
6192 */
6193 break;
6194 case BNX2X_RX_MODE_NORMAL:
924d75ab
YM		 6195 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6196 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6197 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6198
6199 /* internal switching mode */
924d75ab
YM		 6200 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6201 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6202 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6 6203
05cc5a39
YM		 6204 if (bp->accept_any_vlan) {
6205 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6206 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6207 }
6208
619c5cb6
VZ		 6209 break;
6210 case BNX2X_RX_MODE_ALLMULTI:
924d75ab
YM		 6211 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6212 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6213 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6214
6215 /* internal switching mode */
924d75ab
YM		 6216 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6217 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6218 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6 6219
05cc5a39
YM		 6220 if (bp->accept_any_vlan) {
6221 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6222 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6223 }
6224
619c5cb6
VZ		 6225 break;
6226 case BNX2X_RX_MODE_PROMISC:
16a5fd92 6227 /* According to definition of SI mode, iface in promisc mode
619c5cb6
VZ		 6228 * should receive matched and unmatched (in resolution of port)
6229 * unicast packets.
6230 */
924d75ab
YM		 6231 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6232 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6233 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6234 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6235
6236 /* internal switching mode */
924d75ab
YM		 6237 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6238 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6239
6240 if (IS_MF_SI(bp))
924d75ab 6241 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
619c5cb6 6242 else
924d75ab 6243 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
619c5cb6 6244
05cc5a39
YM		 6245 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6246 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6247
619c5cb6
VZ		 6248 break;
6249 default:
924d75ab
YM		 6250 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6251 return -EINVAL;
619c5cb6 6252 }
de832a55 6253
924d75ab
YM		 6254 return 0;
6255}
6256
6257/* called with netif_addr_lock_bh() */
a8f47eb7 6258static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
924d75ab
YM		 6259{
6260 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6261 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6262 int rc;
6263
6264 if (!NO_FCOE(bp))
6265 /* Configure rx_mode of FCoE Queue */
6266 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6267
6268 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6269 &tx_accept_flags);
6270 if (rc)
6271 return rc;
6272
619c5cb6
VZ		 6273 __set_bit(RAMROD_RX, &ramrod_flags);
6274 __set_bit(RAMROD_TX, &ramrod_flags);
6275
924d75ab
YM		 6276 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6277 rx_accept_flags, tx_accept_flags,
6278 ramrod_flags);
619c5cb6
VZ		 6279}
6280
6281static void bnx2x_init_internal_common(struct bnx2x *bp)
6282{
6283 int i;
6284
523224a3
DK		 6285 /* Zero this manually as its initialization is
6286 currently missing in the initTool */
6287 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 6288 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 6289 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 6290 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6291 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6292 CHIP_INT_MODE_IS_BC(bp) ?
6293 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6294 }
523224a3 6295}
8a1c38d1 6296
471de716
EG		 6297static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6298{
6299 switch (load_code) {
6300 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 6301 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 6302 bnx2x_init_internal_common(bp);
6303 /* no break */
6304
6305 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 6306 /* nothing to do */
471de716
EG		 6307 /* no break */
6308
6309 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 6310 /* internal memory per function is
6311 initialized inside bnx2x_pf_init */
471de716
EG		 6312 break;
6313
6314 default:
6315 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6316 break;
6317 }
6318}
6319
619c5cb6 6320static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 6321{
55c11941 6322 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 6323}
523224a3 6324
619c5cb6
VZ		 6325static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6326{
55c11941 6327 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 6328}
6329
1191cb83 6330static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 6331{
6332 if (CHIP_IS_E1x(fp->bp))
6333 return BP_L_ID(fp->bp) + fp->index;
6334 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6335 return bnx2x_fp_igu_sb_id(fp);
6336}
6337
6383c0b3 6338static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 6339{
6340 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 6341 u8 cos;
619c5cb6 6342 unsigned long q_type = 0;
6383c0b3 6343 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 6344 fp->rx_queue = fp_idx;
b3b83c3f 6345 fp->cid = fp_idx;
619c5cb6
VZ		 6346 fp->cl_id = bnx2x_fp_cl_id(fp);
6347 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6348 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 6349 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 6350 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6351
523224a3 6352 /* init shortcut */
619c5cb6 6353 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 6354
16a5fd92 6355 /* Setup SB indices */
523224a3 6356 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 6357
619c5cb6
VZ		 6358 /* Configure Queue State object */
6359 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6360 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 6361
6362 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6363
6364 /* init tx data */
6365 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 6366 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6367 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6368 FP_COS_TO_TXQ(fp, cos, bp),
6369 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6370 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 6371 }
6372
ad5afc89
AE		 6373 /* nothing more for vf to do here */
6374 if (IS_VF(bp))
6375 return;
6376
6377 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6378 fp->fw_sb_id, fp->igu_sb_id);
6379 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 6380 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6381 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 6382 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 6383
6384 /**
6385 * Configure classification DBs: Always enable Tx switching
6386 */
6387 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6388
ad5afc89
AE		 6389 DP(NETIF_MSG_IFUP,
6390 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6391 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6392 fp->igu_sb_id);
523224a3
DK		 6393}
6394
1191cb83
ED		 6395static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6396{
6397 int i;
6398
6399 for (i = 1; i <= NUM_TX_RINGS; i++) {
6400 struct eth_tx_next_bd *tx_next_bd =
6401 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6402
6403 tx_next_bd->addr_hi =
6404 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6405 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6406 tx_next_bd->addr_lo =
6407 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6408 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6409 }
6410
639d65b8
YM		 6411 *txdata->tx_cons_sb = cpu_to_le16(0);
6412
1191cb83
ED		 6413 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6414 txdata->tx_db.data.zero_fill1 = 0;
6415 txdata->tx_db.data.prod = 0;
6416
6417 txdata->tx_pkt_prod = 0;
6418 txdata->tx_pkt_cons = 0;
6419 txdata->tx_bd_prod = 0;
6420 txdata->tx_bd_cons = 0;
6421 txdata->tx_pkt = 0;
6422}
6423
55c11941
MS		 6424static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6425{
6426 int i;
6427
6428 for_each_tx_queue_cnic(bp, i)
6429 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6430}
d76a6111 6431
1191cb83
ED		 6432static void bnx2x_init_tx_rings(struct bnx2x *bp)
6433{
6434 int i;
6435 u8 cos;
6436
55c11941 6437 for_each_eth_queue(bp, i)
1191cb83 6438 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 6439 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 6440}
6441
a8f47eb7 6442static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6443{
6444 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6445 unsigned long q_type = 0;
6446
6447 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6448 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6449 BNX2X_FCOE_ETH_CL_ID_IDX);
6450 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6451 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6452 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6453 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6454 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6455 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6456 fp);
6457
6458 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6459
6460 /* qZone id equals to FW (per path) client id */
6461 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6462 /* init shortcut */
6463 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6464 bnx2x_rx_ustorm_prods_offset(fp);
6465
6466 /* Configure Queue State object */
6467 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6468 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6469
6470 /* No multi-CoS for FCoE L2 client */
6471 BUG_ON(fp->max_cos != 1);
6472
6473 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6474 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6475 bnx2x_sp_mapping(bp, q_rdata), q_type);
6476
6477 DP(NETIF_MSG_IFUP,
6478 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6479 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6480 fp->igu_sb_id);
6481}
6482
55c11941 6483void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 6484{
ec6ba945
VZ		 6485 if (!NO_FCOE(bp))
6486 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 6487
6488 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6489 BNX2X_VF_ID_INVALID, false,
619c5cb6 6490 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 6491
55c11941
MS		 6492 /* ensure status block indices were read */
6493 rmb();
6494 bnx2x_init_rx_rings_cnic(bp);
6495 bnx2x_init_tx_rings_cnic(bp);
6496
6497 /* flush all */
6498 mb();
6499 mmiowb();
6500}
a2fbb9ea 6501
ecf01c22 6502void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
55c11941
MS		 6503{
6504 int i;
6505
ecf01c22 6506 /* Setup NIC internals and enable interrupts */
55c11941
MS		 6507 for_each_eth_queue(bp, i)
6508 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 6509
6510 /* ensure status block indices were read */
6511 rmb();
6512 bnx2x_init_rx_rings(bp);
6513 bnx2x_init_tx_rings(bp);
6514
ecf01c22
YM		 6515 if (IS_PF(bp)) {
6516 /* Initialize MOD_ABS interrupts */
6517 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6518 bp->common.shmem_base,
6519 bp->common.shmem2_base, BP_PORT(bp));
ad5afc89 6520
ecf01c22
YM		 6521 /* initialize the default status block and sp ring */
6522 bnx2x_init_def_sb(bp);
6523 bnx2x_update_dsb_idx(bp);
6524 bnx2x_init_sp_ring(bp);
3cdeec22
YM		 6525 } else {
6526 bnx2x_memset_stats(bp);
ecf01c22
YM		 6527 }
6528}
16119785 6529
ecf01c22
YM		 6530void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6531{
523224a3 6532 bnx2x_init_eq_ring(bp);
471de716 6533 bnx2x_init_internal(bp, load_code);
523224a3 6534 bnx2x_pf_init(bp);
0ef00459
EG		 6535 bnx2x_stats_init(bp);
6536
0ef00459
EG		 6537 /* flush all before enabling interrupts */
6538 mb();
6539 mmiowb();
6540
615f8fd9 6541 bnx2x_int_enable(bp);
eb8da205
EG		 6542
6543 /* Check for SPIO5 */
6544 bnx2x_attn_int_deasserted0(bp,
6545 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6546 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 6547}
6548
ecf01c22 6549/* gzip service functions */
a2fbb9ea
ET		 6550static int bnx2x_gunzip_init(struct bnx2x *bp)
6551{
1a983142
FT		 6552 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6553 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 6554 if (bp->gunzip_buf == NULL)
6555 goto gunzip_nomem1;
6556
6557 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6558 if (bp->strm == NULL)
6559 goto gunzip_nomem2;
6560
7ab24bfd 6561 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 6562 if (bp->strm->workspace == NULL)
6563 goto gunzip_nomem3;
6564
6565 return 0;
6566
6567gunzip_nomem3:
6568 kfree(bp->strm);
6569 bp->strm = NULL;
6570
6571gunzip_nomem2:
1a983142
FT		 6572 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6573 bp->gunzip_mapping);
a2fbb9ea
ET		 6574 bp->gunzip_buf = NULL;
6575
6576gunzip_nomem1:
51c1a580 6577 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6578 return -ENOMEM;
6579}
6580
6581static void bnx2x_gunzip_end(struct bnx2x *bp)
6582{
b3b83c3f 6583 if (bp->strm) {
7ab24bfd 6584 vfree(bp->strm->workspace);
b3b83c3f
DK		 6585 kfree(bp->strm);
6586 bp->strm = NULL;
6587 }
a2fbb9ea
ET		 6588
6589 if (bp->gunzip_buf) {
1a983142
FT		 6590 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6591 bp->gunzip_mapping);
a2fbb9ea
ET		 6592 bp->gunzip_buf = NULL;
6593 }
6594}
6595
94a78b79 6596static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6597{
6598 int n, rc;
6599
6600 /* check gzip header */
94a78b79
VZ		 6601 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6602 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6603 return -EINVAL;
94a78b79 6604 }
a2fbb9ea
ET		 6605
6606 n = 10;
6607
34f80b04 6608#define FNAME 0x8
a2fbb9ea
ET		 6609
6610 if (zbuf[3] & FNAME)
6611 while ((zbuf[n++] != 0) && (n < len));
6612
94a78b79 6613 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6614 bp->strm->avail_in = len - n;
6615 bp->strm->next_out = bp->gunzip_buf;
6616 bp->strm->avail_out = FW_BUF_SIZE;
6617
6618 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6619 if (rc != Z_OK)
6620 return rc;
6621
6622 rc = zlib_inflate(bp->strm, Z_FINISH);
6623 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6624 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6625 bp->strm->msg);
a2fbb9ea
ET		 6626
6627 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6628 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6629 netdev_err(bp->dev,
6630 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6631 bp->gunzip_outlen);
a2fbb9ea
ET		 6632 bp->gunzip_outlen >>= 2;
6633
6634 zlib_inflateEnd(bp->strm);
6635
6636 if (rc == Z_STREAM_END)
6637 return 0;
6638
6639 return rc;
6640}
6641
6642/* nic load/unload */
6643
6644/*
34f80b04 6645 * General service functions
a2fbb9ea
ET		 6646 */
6647
6648/* send a NIG loopback debug packet */
6649static void bnx2x_lb_pckt(struct bnx2x *bp)
6650{
a2fbb9ea 6651 u32 wb_write[3];
a2fbb9ea
ET		 6652
6653 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6654 wb_write[0] = 0x55555555;
6655 wb_write[1] = 0x55555555;
34f80b04 6656 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6657 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6658
6659 /* NON-IP protocol */
a2fbb9ea
ET		 6660 wb_write[0] = 0x09000000;
6661 wb_write[1] = 0x55555555;
34f80b04 6662 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6663 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6664}
6665
6666/* some of the internal memories
6667 * are not directly readable from the driver
6668 * to test them we send debug packets
6669 */
6670static int bnx2x_int_mem_test(struct bnx2x *bp)
6671{
6672 int factor;
6673 int count, i;
6674 u32 val = 0;
6675
ad8d3948 6676 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6677 factor = 120;
ad8d3948
EG		 6678 else if (CHIP_REV_IS_EMUL(bp))
6679 factor = 200;
6680 else
a2fbb9ea 6681 factor = 1;
a2fbb9ea 6682
a2fbb9ea
ET		 6683 /* Disable inputs of parser neighbor blocks */
6684 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6685 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6686 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6687 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6688
6689 /* Write 0 to parser credits for CFC search request */
6690 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6691
6692 /* send Ethernet packet */
6693 bnx2x_lb_pckt(bp);
6694
6695 /* TODO do i reset NIG statistic? */
6696 /* Wait until NIG register shows 1 packet of size 0x10 */
6697 count = 1000 * factor;
6698 while (count) {
34f80b04 6699
a2fbb9ea
ET		 6700 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6701 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6702 if (val == 0x10)
6703 break;
6704
639d65b8 6705 usleep_range(10000, 20000);
a2fbb9ea
ET		 6706 count--;
6707 }
6708 if (val != 0x10) {
6709 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6710 return -1;
6711 }
6712
6713 /* Wait until PRS register shows 1 packet */
6714 count = 1000 * factor;
6715 while (count) {
6716 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6717 if (val == 1)
6718 break;
6719
639d65b8 6720 usleep_range(10000, 20000);
a2fbb9ea
ET		 6721 count--;
6722 }
6723 if (val != 0x1) {
6724 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6725 return -2;
6726 }
6727
6728 /* Reset and init BRB, PRS */
34f80b04 6729 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6730 msleep(50);
34f80b04 6731 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6732 msleep(50);
619c5cb6
VZ		 6733 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6734 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6735
6736 DP(NETIF_MSG_HW, "part2\n");
6737
6738 /* Disable inputs of parser neighbor blocks */
6739 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6740 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6741 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6742 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6743
6744 /* Write 0 to parser credits for CFC search request */
6745 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6746
6747 /* send 10 Ethernet packets */
6748 for (i = 0; i < 10; i++)
6749 bnx2x_lb_pckt(bp);
6750
6751 /* Wait until NIG register shows 10 + 1
6752 packets of size 11*0x10 = 0xb0 */
6753 count = 1000 * factor;
6754 while (count) {
34f80b04 6755
a2fbb9ea
ET		 6756 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6757 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6758 if (val == 0xb0)
6759 break;
6760
639d65b8 6761 usleep_range(10000, 20000);
a2fbb9ea
ET		 6762 count--;
6763 }
6764 if (val != 0xb0) {
6765 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6766 return -3;
6767 }
6768
6769 /* Wait until PRS register shows 2 packets */
6770 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6771 if (val != 2)
6772 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6773
6774 /* Write 1 to parser credits for CFC search request */
6775 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6776
6777 /* Wait until PRS register shows 3 packets */
6778 msleep(10 * factor);
6779 /* Wait until NIG register shows 1 packet of size 0x10 */
6780 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6781 if (val != 3)
6782 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6783
6784 /* clear NIG EOP FIFO */
6785 for (i = 0; i < 11; i++)
6786 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6787 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6788 if (val != 1) {
6789 BNX2X_ERR("clear of NIG failed\n");
6790 return -4;
6791 }
6792
6793 /* Reset and init BRB, PRS, NIG */
6794 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6795 msleep(50);
6796 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6797 msleep(50);
619c5cb6
VZ		 6798 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6799 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6800 if (!CNIC_SUPPORT(bp))
6801 /* set NIC mode */
6802 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6803
6804 /* Enable inputs of parser neighbor blocks */
6805 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6806 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6807 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6808 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6809
6810 DP(NETIF_MSG_HW, "done\n");
6811
6812 return 0; /* OK */
6813}
6814
4a33bc03 6815static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6816{
b343d002
YM		 6817 u32 val;
6818
a2fbb9ea 6819 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6820 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6821 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6822 else
6823 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6824 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6825 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6826 /*
6827 * mask read length error interrupts in brb for parser
6828 * (parsing unit and 'checksum and crc' unit)
6829 * these errors are legal (PU reads fixed length and CAC can cause
6830 * read length error on truncated packets)
6831 */
6832 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6833 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6834 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6835 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6836 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6837 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6838/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6839/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6840 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6841 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6842 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6843/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6844/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6845 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6846 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6847 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6848 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6849/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6850/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6851
b343d002
YM		 6852 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6853 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6854 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6855 if (!CHIP_IS_E1x(bp))
6856 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6857 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6858 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6859
a2fbb9ea
ET		 6860 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6861 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6862 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6863/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6864
6865 if (!CHIP_IS_E1x(bp))
6866 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6867 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6868
a2fbb9ea
ET		 6869 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6870 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6871/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6872 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6873}
6874
81f75bbf
EG		 6875static void bnx2x_reset_common(struct bnx2x *bp)
6876{
619c5cb6
VZ		 6877 u32 val = 0x1400;
6878
81f75bbf
EG		 6879 /* reset_common */
6880 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6881 0xd3ffff7f);
619c5cb6
VZ		 6882
6883 if (CHIP_IS_E3(bp)) {
6884 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6885 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6886 }
6887
6888 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6889}
6890
6891static void bnx2x_setup_dmae(struct bnx2x *bp)
6892{
6893 bp->dmae_ready = 0;
6894 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6895}
6896
573f2035
EG		 6897static void bnx2x_init_pxp(struct bnx2x *bp)
6898{
6899 u16 devctl;
6900 int r_order, w_order;
6901
2a80eebc 6902 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6903 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6904 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6905 if (bp->mrrs == -1)
6906 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6907 else {
6908 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6909 r_order = bp->mrrs;
6910 }
6911
6912 bnx2x_init_pxp_arb(bp, r_order, w_order);
6913}
fd4ef40d
EG		 6914
6915static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6916{
2145a920 6917 int is_required;
fd4ef40d 6918 u32 val;
2145a920 6919 int port;
fd4ef40d 6920
2145a920
VZ		 6921 if (BP_NOMCP(bp))
6922 return;
6923
6924 is_required = 0;
fd4ef40d
EG		 6925 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6926 SHARED_HW_CFG_FAN_FAILURE_MASK;
6927
6928 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6929 is_required = 1;
6930
6931 /*
6932 * The fan failure mechanism is usually related to the PHY type since
6933 * the power consumption of the board is affected by the PHY. Currently,
6934 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6935 */
6936 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6937 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6938 is_required |=
d90d96ba
YR		 6939 bnx2x_fan_failure_det_req(
6940 bp,
6941 bp->common.shmem_base,
a22f0788 6942 bp->common.shmem2_base,
d90d96ba 6943 port);
fd4ef40d
EG		 6944 }
6945
6946 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6947
6948 if (is_required == 0)
6949 return;
6950
6951 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6952 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6953
6954 /* set to active low mode */
6955 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6956 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6957 REG_WR(bp, MISC_REG_SPIO_INT, val);
6958
6959 /* enable interrupt to signal the IGU */
6960 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6961 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6962 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6963}
6964
c9ee9206 6965void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6966{
6967 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6968 val &= ~IGU_PF_CONF_FUNC_EN;
6969
6970 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6971 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6972 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6973}
6974
1191cb83 6975static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6976{
6977 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6978 /* Avoid common init in case MFW supports LFA */
6979 if (SHMEM2_RD(bp, size) >
6980 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6981 return;
619c5cb6
VZ		 6982 shmem_base[0] = bp->common.shmem_base;
6983 shmem2_base[0] = bp->common.shmem2_base;
6984 if (!CHIP_IS_E1x(bp)) {
6985 shmem_base[1] =
6986 SHMEM2_RD(bp, other_shmem_base_addr);
6987 shmem2_base[1] =
6988 SHMEM2_RD(bp, other_shmem2_base_addr);
6989 }
6990 bnx2x_acquire_phy_lock(bp);
6991 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6992 bp->common.chip_id);
6993 bnx2x_release_phy_lock(bp);
6994}
6995
04860eb7
MC		 6996static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6997{
6998 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6999 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
7000 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7001 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7002 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7003
7004 /* make sure this value is 0 */
7005 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7006
7007 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7008 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7009 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7010 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7011}
7012
7013static void bnx2x_set_endianity(struct bnx2x *bp)
7014{
7015#ifdef __BIG_ENDIAN
7016 bnx2x_config_endianity(bp, 1);
7017#else
7018 bnx2x_config_endianity(bp, 0);
7019#endif
7020}
7021
7022static void bnx2x_reset_endianity(struct bnx2x *bp)
7023{
7024 bnx2x_config_endianity(bp, 0);
7025}
7026
619c5cb6
VZ		 7027/**
7028 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7029 *
7030 * @bp: driver handle
7031 */
7032static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 7033{
619c5cb6 7034 u32 val;
a2fbb9ea 7035
51c1a580 7036 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 7037
2031bd3a 7038 /*
2de67439 7039 * take the RESET lock to protect undi_unload flow from accessing
2031bd3a
DK		 7040 * registers while we're resetting the chip
7041 */
7a06a122 7042 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 7043
81f75bbf 7044 bnx2x_reset_common(bp);
34f80b04 7045 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 7046
619c5cb6
VZ		 7047 val = 0xfffc;
7048 if (CHIP_IS_E3(bp)) {
7049 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7050 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7051 }
7052 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7053
7a06a122 7054 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 7055
619c5cb6 7056 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 7057
619c5cb6
VZ		 7058 if (!CHIP_IS_E1x(bp)) {
7059 u8 abs_func_id;
f2e0899f
DK		 7060
7061 /**
7062 * 4-port mode or 2-port mode we need to turn of master-enable
7063 * for everyone, after that, turn it back on for self.
7064 * so, we disregard multi-function or not, and always disable
7065 * for all functions on the given path, this means 0,2,4,6 for
7066 * path 0 and 1,3,5,7 for path 1
7067 */
619c5cb6
VZ		 7068 for (abs_func_id = BP_PATH(bp);
7069 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7070 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 7071 REG_WR(bp,
7072 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7073 1);
7074 continue;
7075 }
7076
619c5cb6 7077 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 7078 /* clear pf enable */
7079 bnx2x_pf_disable(bp);
7080 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7081 }
7082 }
a2fbb9ea 7083
619c5cb6 7084 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 7085 if (CHIP_IS_E1(bp)) {
7086 /* enable HW interrupt from PXP on USDM overflow
7087 bit 16 on INT_MASK_0 */
7088 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7089 }
a2fbb9ea 7090
619c5cb6 7091 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 7092 bnx2x_init_pxp(bp);
04860eb7 7093 bnx2x_set_endianity(bp);
523224a3
DK		 7094 bnx2x_ilt_init_page_size(bp, INITOP_SET);
7095
34f80b04
EG		 7096 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7097 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 7098
34f80b04
EG		 7099 /* let the HW do it's magic ... */
7100 msleep(100);
7101 /* finish PXP init */
7102 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7103 if (val != 1) {
7104 BNX2X_ERR("PXP2 CFG failed\n");
7105 return -EBUSY;
7106 }
7107 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7108 if (val != 1) {
7109 BNX2X_ERR("PXP2 RD_INIT failed\n");
7110 return -EBUSY;
7111 }
a2fbb9ea 7112
f2e0899f
DK		 7113 /* Timers bug workaround E2 only. We need to set the entire ILT to
7114 * have entries with value "0" and valid bit on.
7115 * This needs to be done by the first PF that is loaded in a path
7116 * (i.e. common phase)
7117 */
619c5cb6
VZ		 7118 if (!CHIP_IS_E1x(bp)) {
7119/* In E2 there is a bug in the timers block that can cause function 6 / 7
7120 * (i.e. vnic3) to start even if it is marked as "scan-off".
7121 * This occurs when a different function (func2,3) is being marked
7122 * as "scan-off". Real-life scenario for example: if a driver is being
7123 * load-unloaded while func6,7 are down. This will cause the timer to access
7124 * the ilt, translate to a logical address and send a request to read/write.
7125 * Since the ilt for the function that is down is not valid, this will cause
7126 * a translation error which is unrecoverable.
7127 * The Workaround is intended to make sure that when this happens nothing fatal
7128 * will occur. The workaround:
7129 * 1. First PF driver which loads on a path will:
7130 * a. After taking the chip out of reset, by using pretend,
7131 * it will write "0" to the following registers of
7132 * the other vnics.
7133 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7134 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7135 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7136 * And for itself it will write '1' to
7137 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7138 * dmae-operations (writing to pram for example.)
7139 * note: can be done for only function 6,7 but cleaner this
7140 * way.
7141 * b. Write zero+valid to the entire ILT.
7142 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7143 * VNIC3 (of that port). The range allocated will be the
7144 * entire ILT. This is needed to prevent ILT range error.
7145 * 2. Any PF driver load flow:
7146 * a. ILT update with the physical addresses of the allocated
7147 * logical pages.
7148 * b. Wait 20msec. - note that this timeout is needed to make
7149 * sure there are no requests in one of the PXP internal
7150 * queues with "old" ILT addresses.
7151 * c. PF enable in the PGLC.
7152 * d. Clear the was_error of the PF in the PGLC. (could have
2de67439 7153 * occurred while driver was down)
619c5cb6
VZ		 7154 * e. PF enable in the CFC (WEAK + STRONG)
7155 * f. Timers scan enable
7156 * 3. PF driver unload flow:
7157 * a. Clear the Timers scan_en.
7158 * b. Polling for scan_on=0 for that PF.
7159 * c. Clear the PF enable bit in the PXP.
7160 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7161 * e. Write zero+valid to all ILT entries (The valid bit must
7162 * stay set)
7163 * f. If this is VNIC 3 of a port then also init
7164 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16a5fd92 7165 * to the last entry in the ILT.
619c5cb6
VZ		 7166 *
7167 * Notes:
7168 * Currently the PF error in the PGLC is non recoverable.
7169 * In the future the there will be a recovery routine for this error.
7170 * Currently attention is masked.
7171 * Having an MCP lock on the load/unload process does not guarantee that
7172 * there is no Timer disable during Func6/7 enable. This is because the
7173 * Timers scan is currently being cleared by the MCP on FLR.
7174 * Step 2.d can be done only for PF6/7 and the driver can also check if
7175 * there is error before clearing it. But the flow above is simpler and
7176 * more general.
7177 * All ILT entries are written by zero+valid and not just PF6/7
7178 * ILT entries since in the future the ILT entries allocation for
7179 * PF-s might be dynamic.
7180 */
f2e0899f
DK		 7181 struct ilt_client_info ilt_cli;
7182 struct bnx2x_ilt ilt;
7183 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7184 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7185
b595076a 7186 /* initialize dummy TM client */
f2e0899f
DK		 7187 ilt_cli.start = 0;
7188 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7189 ilt_cli.client_num = ILT_CLIENT_TM;
7190
7191 /* Step 1: set zeroes to all ilt page entries with valid bit on
7192 * Step 2: set the timers first/last ilt entry to point
7193 * to the entire range to prevent ILT range error for 3rd/4th
2de67439 7194 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 7195 *
7196 * both steps performed by call to bnx2x_ilt_client_init_op()
7197 * with dummy TM client
7198 *
7199 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7200 * and his brother are split registers
7201 */
7202 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7203 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7204 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7205
7206 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7207 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7208 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7209 }
7210
34f80b04
EG		 7211 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7212 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 7213
619c5cb6 7214 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7215 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7216 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 7217 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 7218
619c5cb6 7219 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 7220
7221 /* let the HW do it's magic ... */
7222 do {
7223 msleep(200);
7224 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7225 } while (factor-- && (val != 1));
7226
7227 if (val != 1) {
7228 BNX2X_ERR("ATC_INIT failed\n");
7229 return -EBUSY;
7230 }
7231 }
7232
619c5cb6 7233 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 7234
b56e9670
AE		 7235 bnx2x_iov_init_dmae(bp);
7236
34f80b04
EG		 7237 /* clean the DMAE memory */
7238 bp->dmae_ready = 1;
619c5cb6
VZ		 7239 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7240
7241 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7242
7243 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7244
7245 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 7246
619c5cb6 7247 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 7248
34f80b04
EG		 7249 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7250 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7251 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7252 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7253
619c5cb6 7254 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 7255
523224a3
DK		 7256 /* QM queues pointers table */
7257 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7258
34f80b04
EG		 7259 /* soft reset pulse */
7260 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7261 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 7262
55c11941
MS		 7263 if (CNIC_SUPPORT(bp))
7264 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 7265
619c5cb6 7266 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
b9871bcf 7267
619c5cb6 7268 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 7269 /* enable hw interrupt from doorbell Q */
7270 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 7271
619c5cb6 7272 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 7273
619c5cb6 7274 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 7275 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 7276
f2e0899f 7277 if (!CHIP_IS_E1(bp))
619c5cb6 7278 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 7279
a3348722
BW		 7280 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7281 if (IS_MF_AFEX(bp)) {
7282 /* configure that VNTag and VLAN headers must be
7283 * received in afex mode
7284 */
7285 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7286 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7287 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7288 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7289 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7290 } else {
7291 /* Bit-map indicating which L2 hdrs may appear
7292 * after the basic Ethernet header
7293 */
7294 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7295 bp->path_has_ovlan ? 7 : 6);
7296 }
7297 }
a2fbb9ea 7298
619c5cb6
VZ		 7299 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7300 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7301 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7302 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 7303
619c5cb6
VZ		 7304 if (!CHIP_IS_E1x(bp)) {
7305 /* reset VFC memories */
7306 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7307 VFC_MEMORIES_RST_REG_CAM_RST |
7308 VFC_MEMORIES_RST_REG_RAM_RST);
7309 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7310 VFC_MEMORIES_RST_REG_CAM_RST |
7311 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 7312
619c5cb6
VZ		 7313 msleep(20);
7314 }
a2fbb9ea 7315
619c5cb6
VZ		 7316 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7317 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7318 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7319 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 7320
34f80b04
EG		 7321 /* sync semi rtc */
7322 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7323 0x80000000);
7324 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7325 0x80000000);
a2fbb9ea 7326
619c5cb6
VZ		 7327 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7328 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7329 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 7330
a3348722
BW		 7331 if (!CHIP_IS_E1x(bp)) {
7332 if (IS_MF_AFEX(bp)) {
7333 /* configure that VNTag and VLAN headers must be
7334 * sent in afex mode
7335 */
7336 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7337 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7338 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7339 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7340 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7341 } else {
7342 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7343 bp->path_has_ovlan ? 7 : 6);
7344 }
7345 }
f2e0899f 7346
34f80b04 7347 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 7348
619c5cb6
VZ		 7349 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7350
55c11941
MS		 7351 if (CNIC_SUPPORT(bp)) {
7352 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7353 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7354 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7355 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7356 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7357 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7358 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7359 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7360 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7361 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7362 }
34f80b04 7363 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 7364
34f80b04
EG		 7365 if (sizeof(union cdu_context) != 1024)
7366 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 7367 dev_alert(&bp->pdev->dev,
7368 "please adjust the size of cdu_context(%ld)\n",
7369 (long)sizeof(union cdu_context));
a2fbb9ea 7370
619c5cb6 7371 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 7372 val = (4 << 24) + (0 << 12) + 1024;
7373 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 7374
619c5cb6 7375 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 7376 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 7377 /* enable context validation interrupt from CFC */
7378 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7379
7380 /* set the thresholds to prevent CFC/CDU race */
7381 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 7382
619c5cb6 7383 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 7384
619c5cb6 7385 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 7386 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7387
619c5cb6
VZ		 7388 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7389 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 7390
34f80b04
EG		 7391 /* Reset PCIE errors for debug */
7392 REG_WR(bp, 0x2814, 0xffffffff);
7393 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 7394
619c5cb6 7395 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7396 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7397 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7398 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7399 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7400 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7401 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7402 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7403 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7404 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7405 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7406 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7407 }
7408
619c5cb6 7409 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 7410 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 7411 /* in E3 this done in per-port section */
7412 if (!CHIP_IS_E3(bp))
7413 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 7414 }
619c5cb6
VZ		 7415 if (CHIP_IS_E1H(bp))
7416 /* not applicable for E2 (and above ...) */
7417 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 7418
7419 if (CHIP_REV_IS_SLOW(bp))
7420 msleep(200);
7421
7422 /* finish CFC init */
7423 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7424 if (val != 1) {
7425 BNX2X_ERR("CFC LL_INIT failed\n");
7426 return -EBUSY;
7427 }
7428 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7429 if (val != 1) {
7430 BNX2X_ERR("CFC AC_INIT failed\n");
7431 return -EBUSY;
7432 }
7433 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7434 if (val != 1) {
7435 BNX2X_ERR("CFC CAM_INIT failed\n");
7436 return -EBUSY;
7437 }
7438 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 7439
f2e0899f
DK		 7440 if (CHIP_IS_E1(bp)) {
7441 /* read NIG statistic
7442 to see if this is our first up since powerup */
7443 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7444 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 7445
f2e0899f
DK		 7446 /* do internal memory self test */
7447 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7448 BNX2X_ERR("internal mem self test failed\n");
7449 return -EBUSY;
7450 }
34f80b04
EG		 7451 }
7452
fd4ef40d
EG		 7453 bnx2x_setup_fan_failure_detection(bp);
7454
34f80b04
EG		 7455 /* clear PXP2 attentions */
7456 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 7457
4a33bc03 7458 bnx2x_enable_blocks_attention(bp);
c9ee9206 7459 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 7460
6bbca910 7461 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 7462 if (CHIP_IS_E1x(bp))
7463 bnx2x__common_init_phy(bp);
6bbca910
YR		 7464 } else
7465 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7466
230d00eb
YM		 7467 if (SHMEM2_HAS(bp, netproc_fw_ver))
7468 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7469
34f80b04
EG		 7470 return 0;
7471}
a2fbb9ea 7472
619c5cb6
VZ		 7473/**
7474 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7475 *
7476 * @bp: driver handle
7477 */
7478static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7479{
7480 int rc = bnx2x_init_hw_common(bp);
7481
7482 if (rc)
7483 return rc;
7484
7485 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7486 if (!BP_NOMCP(bp))
7487 bnx2x__common_init_phy(bp);
7488
7489 return 0;
7490}
7491
523224a3 7492static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 7493{
7494 int port = BP_PORT(bp);
619c5cb6 7495 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 7496 u32 low, high;
4293b9f5 7497 u32 val, reg;
a2fbb9ea 7498
51c1a580 7499 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 7500
7501 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 7502
619c5cb6
VZ		 7503 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7504 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7505 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 7506
f2e0899f
DK		 7507 /* Timers bug workaround: disables the pf_master bit in pglue at
7508 * common phase, we need to enable it here before any dmae access are
7509 * attempted. Therefore we manually added the enable-master to the
7510 * port phase (it also happens in the function phase)
7511 */
619c5cb6 7512 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7513 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7514
619c5cb6
VZ		 7515 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7516 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7517 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7518 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7519
7520 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7521 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7522 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7523 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 7524
523224a3
DK		 7525 /* QM cid (connection) count */
7526 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 7527
55c11941
MS		 7528 if (CNIC_SUPPORT(bp)) {
7529 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7530 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7531 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7532 }
cdaa7cb8 7533
619c5cb6 7534 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 7535
2b674047
DK		 7536 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7537
f2e0899f 7538 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 7539
7540 if (IS_MF(bp))
7541 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7542 else if (bp->dev->mtu > 4096) {
7543 if (bp->flags & ONE_PORT_FLAG)
7544 low = 160;
7545 else {
7546 val = bp->dev->mtu;
7547 /* (24*1024 + val*4)/256 */
7548 low = 96 + (val/64) +
7549 ((val % 64) ? 1 : 0);
7550 }
7551 } else
7552 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7553 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 7554 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7555 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 7556 }
1c06328c 7557
619c5cb6
VZ		 7558 if (CHIP_MODE_IS_4_PORT(bp))
7559 REG_WR(bp, (BP_PORT(bp) ?
7560 BRB1_REG_MAC_GUARANTIED_1 :
7561 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 7562
619c5cb6 7563 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 7564 if (CHIP_IS_E3B0(bp)) {
7565 if (IS_MF_AFEX(bp)) {
7566 /* configure headers for AFEX mode */
7567 REG_WR(bp, BP_PORT(bp) ?
7568 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7569 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7570 REG_WR(bp, BP_PORT(bp) ?
7571 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7572 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7573 REG_WR(bp, BP_PORT(bp) ?
7574 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7575 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7576 } else {
7577 /* Ovlan exists only if we are in multi-function +
7578 * switch-dependent mode, in switch-independent there
7579 * is no ovlan headers
7580 */
7581 REG_WR(bp, BP_PORT(bp) ?
7582 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7583 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7584 (bp->path_has_ovlan ? 7 : 6));
7585 }
7586 }
356e2385 7587
619c5cb6
VZ		 7588 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7589 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7590 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7591 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7592
619c5cb6
VZ		 7593 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7594 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7595 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7596 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7597
619c5cb6
VZ		 7598 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7599 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7600
619c5cb6
VZ		 7601 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7602
7603 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7604 /* configure PBF to work without PAUSE mtu 9000 */
7605 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7606
f2e0899f
DK		 7607 /* update threshold */
7608 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7609 /* update init credit */
7610 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7611
f2e0899f
DK		 7612 /* probe changes */
7613 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7614 udelay(50);
7615 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7616 }
a2fbb9ea 7617
55c11941
MS		 7618 if (CNIC_SUPPORT(bp))
7619 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7620
619c5cb6
VZ		 7621 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7622 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7623
7624 if (CHIP_IS_E1(bp)) {
7625 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7626 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7627 }
619c5cb6 7628 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7629
619c5cb6 7630 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7631
619c5cb6 7632 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04 7633 /* init aeu_mask_attn_func_0/1:
16a5fd92
YM		 7634 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7635 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
34f80b04 7636 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7637 val = IS_MF(bp) ? 0xF7 : 0x7;
7638 /* Enable DCBX attention for all but E1 */
7639 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7640 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7641
4293b9f5
DK		 7642 /* SCPAD_PARITY should NOT trigger close the gates */
7643 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7644 REG_WR(bp, reg,
7645 REG_RD(bp, reg) &
7646 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7647
7648 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7649 REG_WR(bp, reg,
7650 REG_RD(bp, reg) &
7651 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7652
619c5cb6
VZ		 7653 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7654
7655 if (!CHIP_IS_E1x(bp)) {
7656 /* Bit-map indicating which L2 hdrs may appear after the
7657 * basic Ethernet header
7658 */
a3348722
BW		 7659 if (IS_MF_AFEX(bp))
7660 REG_WR(bp, BP_PORT(bp) ?
7661 NIG_REG_P1_HDRS_AFTER_BASIC :
7662 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7663 else
7664 REG_WR(bp, BP_PORT(bp) ?
7665 NIG_REG_P1_HDRS_AFTER_BASIC :
7666 NIG_REG_P0_HDRS_AFTER_BASIC,
7667 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7668
7669 if (CHIP_IS_E3(bp))
7670 REG_WR(bp, BP_PORT(bp) ?
7671 NIG_REG_LLH1_MF_MODE :
7672 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7673 }
7674 if (!CHIP_IS_E3(bp))
7675 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7676
f2e0899f 7677 if (!CHIP_IS_E1(bp)) {
fb3bff17 7678 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7679 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7680 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7681
619c5cb6 7682 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7683 val = 0;
7684 switch (bp->mf_mode) {
7685 case MULTI_FUNCTION_SD:
7686 val = 1;
7687 break;
7688 case MULTI_FUNCTION_SI:
a3348722 7689 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7690 val = 2;
7691 break;
7692 }
7693
7694 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7695 NIG_REG_LLH0_CLS_TYPE), val);
7696 }
1c06328c
EG		 7697 {
7698 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7699 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7700 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7701 }
34f80b04
EG		 7702 }
7703
619c5cb6
VZ		 7704 /* If SPIO5 is set to generate interrupts, enable it for this port */
7705 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7706 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7707 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7708 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7709 val = REG_RD(bp, reg_addr);
f1410647 7710 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7711 REG_WR(bp, reg_addr, val);
f1410647 7712 }
a2fbb9ea 7713
34f80b04
EG		 7714 return 0;
7715}
7716
34f80b04
EG		 7717static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7718{
7719 int reg;
32d68de1 7720 u32 wb_write[2];
34f80b04 7721
f2e0899f 7722 if (CHIP_IS_E1(bp))
34f80b04 7723 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7724 else
7725 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7726
32d68de1
YM		 7727 wb_write[0] = ONCHIP_ADDR1(addr);
7728 wb_write[1] = ONCHIP_ADDR2(addr);
7729 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7730}
7731
b56e9670 7732void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7733{
7734 u32 data, ctl, cnt = 100;
7735 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7736 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7737 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7738 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7739 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7740 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7741
7742 /* Not supported in BC mode */
7743 if (CHIP_INT_MODE_IS_BC(bp))
7744 return;
7745
7746 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7747 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7748 IGU_REGULAR_CLEANUP_SET |
7749 IGU_REGULAR_BCLEANUP;
7750
7751 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7752 func_encode << IGU_CTRL_REG_FID_SHIFT |
7753 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7754
7755 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7756 data, igu_addr_data);
7757 REG_WR(bp, igu_addr_data, data);
7758 mmiowb();
7759 barrier();
7760 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7761 ctl, igu_addr_ctl);
7762 REG_WR(bp, igu_addr_ctl, ctl);
7763 mmiowb();
7764 barrier();
7765
7766 /* wait for clean up to finish */
7767 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7768 msleep(20);
7769
1191cb83
ED		 7770 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7771 DP(NETIF_MSG_HW,
7772 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7773 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7774 }
7775}
7776
7777static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7778{
619c5cb6 7779 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7780}
7781
1191cb83 7782static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7783{
7784 u32 i, base = FUNC_ILT_BASE(func);
7785 for (i = base; i < base + ILT_PER_FUNC; i++)
7786 bnx2x_ilt_wr(bp, i, 0);
7787}
7788
910cc727 7789static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7790{
7791 int port = BP_PORT(bp);
7792 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7793 /* T1 hash bits value determines the T1 number of entries */
7794 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7795}
7796
7797static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7798{
7799 int rc;
7800 struct bnx2x_func_state_params func_params = {NULL};
7801 struct bnx2x_func_switch_update_params *switch_update_params =
7802 &func_params.params.switch_update;
7803
7804 /* Prepare parameters for function state transitions */
7805 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7806 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7807
7808 func_params.f_obj = &bp->func_obj;
7809 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7810
7811 /* Function parameters */
e42780b6
DK		 7812 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7813 &switch_update_params->changes);
7814 if (suspend)
7815 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7816 &switch_update_params->changes);
55c11941
MS		 7817
7818 rc = bnx2x_func_state_change(bp, &func_params);
7819
7820 return rc;
7821}
7822
910cc727 7823static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7824{
7825 int rc, i, port = BP_PORT(bp);
7826 int vlan_en = 0, mac_en[NUM_MACS];
7827
55c11941
MS		 7828 /* Close input from network */
7829 if (bp->mf_mode == SINGLE_FUNCTION) {
7830 bnx2x_set_rx_filter(&bp->link_params, 0);
7831 } else {
7832 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7833 NIG_REG_LLH0_FUNC_EN);
7834 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7835 NIG_REG_LLH0_FUNC_EN, 0);
7836 for (i = 0; i < NUM_MACS; i++) {
7837 mac_en[i] = REG_RD(bp, port ?
7838 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7839 4 * i) :
7840 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7841 4 * i));
7842 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7843 4 * i) :
7844 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7845 }
7846 }
7847
7848 /* Close BMC to host */
7849 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7850 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7851
7852 /* Suspend Tx switching to the PF. Completion of this ramrod
7853 * further guarantees that all the packets of that PF / child
7854 * VFs in BRB were processed by the Parser, so it is safe to
7855 * change the NIC_MODE register.
7856 */
7857 rc = bnx2x_func_switch_update(bp, 1);
7858 if (rc) {
7859 BNX2X_ERR("Can't suspend tx-switching!\n");
7860 return rc;
7861 }
7862
7863 /* Change NIC_MODE register */
7864 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7865
7866 /* Open input from network */
7867 if (bp->mf_mode == SINGLE_FUNCTION) {
7868 bnx2x_set_rx_filter(&bp->link_params, 1);
7869 } else {
7870 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7871 NIG_REG_LLH0_FUNC_EN, vlan_en);
7872 for (i = 0; i < NUM_MACS; i++) {
7873 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7874 4 * i) :
7875 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7876 mac_en[i]);
7877 }
7878 }
7879
7880 /* Enable BMC to host */
7881 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7882 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7883
7884 /* Resume Tx switching to the PF */
7885 rc = bnx2x_func_switch_update(bp, 0);
7886 if (rc) {
7887 BNX2X_ERR("Can't resume tx-switching!\n");
7888 return rc;
7889 }
7890
7891 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7892 return 0;
7893}
7894
7895int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7896{
7897 int rc;
7898
7899 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7900
7901 if (CONFIGURE_NIC_MODE(bp)) {
16a5fd92 7902 /* Configure searcher as part of function hw init */
55c11941
MS		 7903 bnx2x_init_searcher(bp);
7904
7905 /* Reset NIC mode */
7906 rc = bnx2x_reset_nic_mode(bp);
7907 if (rc)
7908 BNX2X_ERR("Can't change NIC mode!\n");
7909 return rc;
7910 }
7911
7912 return 0;
7913}
7914
da254fbc
YM		 7915/* previous driver DMAE transaction may have occurred when pre-boot stage ended
7916 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7917 * the addresses of the transaction, resulting in was-error bit set in the pci
7918 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7919 * to clear the interrupt which detected this from the pglueb and the was done
7920 * bit
7921 */
7922static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7923{
7924 if (!CHIP_IS_E1x(bp))
7925 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7926 1 << BP_ABS_FUNC(bp));
7927}
7928
523224a3 7929static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7930{
7931 int port = BP_PORT(bp);
7932 int func = BP_FUNC(bp);
619c5cb6 7933 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7934 struct bnx2x_ilt *ilt = BP_ILT(bp);
7935 u16 cdu_ilt_start;
8badd27a 7936 u32 addr, val;
f4a66897 7937 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7938 int i, main_mem_width, rc;
34f80b04 7939
51c1a580 7940 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7941
619c5cb6 7942 /* FLR cleanup - hmmm */
89db4ad8
AE		 7943 if (!CHIP_IS_E1x(bp)) {
7944 rc = bnx2x_pf_flr_clnup(bp);
04c46736
YM		 7945 if (rc) {
7946 bnx2x_fw_dump(bp);
89db4ad8 7947 return rc;
04c46736 7948 }
89db4ad8 7949 }
619c5cb6 7950
8badd27a 7951 /* set MSI reconfigure capability */
f2e0899f
DK		 7952 if (bp->common.int_block == INT_BLOCK_HC) {
7953 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7954 val = REG_RD(bp, addr);
7955 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7956 REG_WR(bp, addr, val);
7957 }
8badd27a 7958
619c5cb6
VZ		 7959 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7960 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7961
523224a3
DK		 7962 ilt = BP_ILT(bp);
7963 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7964
290ca2bb
AE		 7965 if (IS_SRIOV(bp))
7966 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7967 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7968
7969 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7970 * those of the VFs, so start line should be reset
7971 */
7972 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7973 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7974 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7975 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7976 bp->context[i].cxt_mapping;
7977 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7978 }
290ca2bb 7979
523224a3 7980 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7981
55c11941
MS		 7982 if (!CONFIGURE_NIC_MODE(bp)) {
7983 bnx2x_init_searcher(bp);
7984 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7985 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7986 } else {
7987 /* Set NIC mode */
7988 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6bf07b8e 7989 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
55c11941 7990 }
37b091ba 7991
619c5cb6 7992 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7993 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7994
7995 /* Turn on a single ISR mode in IGU if driver is going to use
7996 * INT#x or MSI
7997 */
7998 if (!(bp->flags & USING_MSIX_FLAG))
7999 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
8000 /*
8001 * Timers workaround bug: function init part.
8002 * Need to wait 20msec after initializing ILT,
8003 * needed to make sure there are no requests in
8004 * one of the PXP internal queues with "old" ILT addresses
8005 */
8006 msleep(20);
8007 /*
8008 * Master enable - Due to WB DMAE writes performed before this
8009 * register is re-initialized as part of the regular function
8010 * init
8011 */
8012 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8013 /* Enable the function in IGU */
8014 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8015 }
8016
523224a3 8017 bp->dmae_ready = 1;
34f80b04 8018
619c5cb6 8019 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 8020
da254fbc 8021 bnx2x_clean_pglue_errors(bp);
f2e0899f 8022
619c5cb6
VZ		 8023 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8024 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8025 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8026 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8027 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8028 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8029 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8030 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8031 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8032 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8033 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8034 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8035 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8036
8037 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 8038 REG_WR(bp, QM_REG_PF_EN, 1);
8039
619c5cb6
VZ		 8040 if (!CHIP_IS_E1x(bp)) {
8041 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8042 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8043 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8044 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8045 }
8046 bnx2x_init_block(bp, BLOCK_QM, init_phase);
8047
8048 bnx2x_init_block(bp, BLOCK_TM, init_phase);
8049 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
c19d65c9 8050 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
b56e9670
AE		 8051
8052 bnx2x_iov_init_dq(bp);
8053
619c5cb6
VZ		 8054 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8055 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8056 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8057 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8058 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8059 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8060 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8061 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8062 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8063 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 8064 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8065
619c5cb6 8066 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 8067
619c5cb6 8068 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 8069
619c5cb6 8070 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 8071 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8072
fb3bff17 8073 if (IS_MF(bp)) {
7609647e
YM		 8074 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8075 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8076 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8077 bp->mf_ov);
8078 }
34f80b04
EG		 8079 }
8080
619c5cb6 8081 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 8082
34f80b04 8083 /* HC init per function */
f2e0899f
DK		 8084 if (bp->common.int_block == INT_BLOCK_HC) {
8085 if (CHIP_IS_E1H(bp)) {
8086 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8087
8088 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8089 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8090 }
619c5cb6 8091 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 8092
8093 } else {
8094 int num_segs, sb_idx, prod_offset;
8095
34f80b04
EG		 8096 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8097
619c5cb6 8098 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8099 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8100 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8101 }
8102
619c5cb6 8103 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 8104
619c5cb6 8105 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8106 int dsb_idx = 0;
8107 /**
8108 * Producer memory:
8109 * E2 mode: address 0-135 match to the mapping memory;
8110 * 136 - PF0 default prod; 137 - PF1 default prod;
8111 * 138 - PF2 default prod; 139 - PF3 default prod;
8112 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8113 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8114 * 144-147 reserved.
8115 *
8116 * E1.5 mode - In backward compatible mode;
8117 * for non default SB; each even line in the memory
8118 * holds the U producer and each odd line hold
8119 * the C producer. The first 128 producers are for
8120 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8121 * producers are for the DSB for each PF.
8122 * Each PF has five segments: (the order inside each
8123 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8124 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8125 * 144-147 attn prods;
8126 */
8127 /* non-default-status-blocks */
8128 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8129 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8130 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8131 prod_offset = (bp->igu_base_sb + sb_idx) *
8132 num_segs;
8133
8134 for (i = 0; i < num_segs; i++) {
8135 addr = IGU_REG_PROD_CONS_MEMORY +
8136 (prod_offset + i) * 4;
8137 REG_WR(bp, addr, 0);
8138 }
8139 /* send consumer update with value 0 */
8140 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8141 USTORM_ID, 0, IGU_INT_NOP, 1);
8142 bnx2x_igu_clear_sb(bp,
8143 bp->igu_base_sb + sb_idx);
8144 }
8145
8146 /* default-status-blocks */
8147 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8148 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8149
8150 if (CHIP_MODE_IS_4_PORT(bp))
8151 dsb_idx = BP_FUNC(bp);
8152 else
3395a033 8153 dsb_idx = BP_VN(bp);
f2e0899f
DK		 8154
8155 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8156 IGU_BC_BASE_DSB_PROD + dsb_idx :
8157 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8158
3395a033
DK		 8159 /*
8160 * igu prods come in chunks of E1HVN_MAX (4) -
8161 * does not matters what is the current chip mode
8162 */
f2e0899f
DK		 8163 for (i = 0; i < (num_segs * E1HVN_MAX);
8164 i += E1HVN_MAX) {
8165 addr = IGU_REG_PROD_CONS_MEMORY +
8166 (prod_offset + i)*4;
8167 REG_WR(bp, addr, 0);
8168 }
8169 /* send consumer update with 0 */
8170 if (CHIP_INT_MODE_IS_BC(bp)) {
8171 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8172 USTORM_ID, 0, IGU_INT_NOP, 1);
8173 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8174 CSTORM_ID, 0, IGU_INT_NOP, 1);
8175 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8176 XSTORM_ID, 0, IGU_INT_NOP, 1);
8177 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8178 TSTORM_ID, 0, IGU_INT_NOP, 1);
8179 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8180 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8181 } else {
8182 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8183 USTORM_ID, 0, IGU_INT_NOP, 1);
8184 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8185 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8186 }
8187 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8188
16a5fd92 8189 /* !!! These should become driver const once
f2e0899f
DK		 8190 rf-tool supports split-68 const */
8191 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8192 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8193 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8194 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8195 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8196 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8197 }
34f80b04 8198 }
34f80b04 8199
c14423fe 8200 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 8201 REG_WR(bp, 0x2114, 0xffffffff);
8202 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 8203
f4a66897
VZ		 8204 if (CHIP_IS_E1x(bp)) {
8205 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8206 main_mem_base = HC_REG_MAIN_MEMORY +
8207 BP_PORT(bp) * (main_mem_size * 4);
8208 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8209 main_mem_width = 8;
8210
8211 val = REG_RD(bp, main_mem_prty_clr);
8212 if (val)
51c1a580
MS		 8213 DP(NETIF_MSG_HW,
8214 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8215 val);
f4a66897
VZ		 8216
8217 /* Clear "false" parity errors in MSI-X table */
8218 for (i = main_mem_base;
8219 i < main_mem_base + main_mem_size * 4;
8220 i += main_mem_width) {
8221 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8222 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8223 i, main_mem_width / 4);
8224 }
8225 /* Clear HC parity attention */
8226 REG_RD(bp, main_mem_prty_clr);
8227 }
8228
619c5cb6
VZ		 8229#ifdef BNX2X_STOP_ON_ERROR
8230 /* Enable STORMs SP logging */
8231 REG_WR8(bp, BAR_USTRORM_INTMEM +
8232 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8233 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8234 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8235 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8236 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8237 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8238 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8239#endif
8240
b7737c9b 8241 bnx2x_phy_probe(&bp->link_params);
f85582f8 8242
34f80b04
EG		 8243 return 0;
8244}
8245
55c11941
MS		 8246void bnx2x_free_mem_cnic(struct bnx2x *bp)
8247{
8248 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8249
8250 if (!CHIP_IS_E1x(bp))
8251 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8252 sizeof(struct host_hc_status_block_e2));
8253 else
8254 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8255 sizeof(struct host_hc_status_block_e1x));
8256
8257 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8258}
8259
9f6c9258 8260void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 8261{
a052997e
MS		 8262 int i;
8263
619c5cb6
VZ		 8264 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8265 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8266
b4cddbd6
AE		 8267 if (IS_VF(bp))
8268 return;
8269
8270 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8271 sizeof(struct host_sp_status_block));
8272
a2fbb9ea 8273 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 8274 sizeof(struct bnx2x_slowpath));
a2fbb9ea 8275
a052997e
MS		 8276 for (i = 0; i < L2_ILT_LINES(bp); i++)
8277 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8278 bp->context[i].size);
523224a3
DK		 8279 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8280
8281 BNX2X_FREE(bp->ilt->lines);
f85582f8 8282
7a9b2557 8283 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 8284
523224a3
DK		 8285 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8286 BCM_PAGE_SIZE * NUM_EQ_PAGES);
580d9d08 8287
05952246
YM		 8288 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8289
580d9d08 8290 bnx2x_iov_free_mem(bp);
619c5cb6
VZ		 8291}
8292
55c11941 8293int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 8294{
cd2b0389 8295 if (!CHIP_IS_E1x(bp)) {
619c5cb6 8296 /* size = the status block + ramrod buffers */
cd2b0389
JP		 8297 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8298 sizeof(struct host_hc_status_block_e2));
8299 if (!bp->cnic_sb.e2_sb)
8300 goto alloc_mem_err;
8301 } else {
8302 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8303 sizeof(struct host_hc_status_block_e1x));
8304 if (!bp->cnic_sb.e1x_sb)
8305 goto alloc_mem_err;
8306 }
8badd27a 8307
cd2b0389 8308 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
16a5fd92 8309 /* allocate searcher T2 table, as it wasn't allocated before */
cd2b0389
JP		 8310 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8311 if (!bp->t2)
8312 goto alloc_mem_err;
8313 }
55c11941
MS		 8314
8315 /* write address to which L5 should insert its values */
8316 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8317 &bp->slowpath->drv_info_to_mcp;
8318
8319 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8320 goto alloc_mem_err;
8321
8322 return 0;
8323
8324alloc_mem_err:
8325 bnx2x_free_mem_cnic(bp);
8326 BNX2X_ERR("Can't allocate memory\n");
8327 return -ENOMEM;
8328}
8329
8330int bnx2x_alloc_mem(struct bnx2x *bp)
8331{
8332 int i, allocated, context_size;
a2fbb9ea 8333
cd2b0389 8334 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
55c11941 8335 /* allocate searcher T2 table */
cd2b0389
JP		 8336 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8337 if (!bp->t2)
8338 goto alloc_mem_err;
8339 }
8badd27a 8340
cd2b0389
JP		 8341 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8342 sizeof(struct host_sp_status_block));
8343 if (!bp->def_status_blk)
8344 goto alloc_mem_err;
a2fbb9ea 8345
cd2b0389
JP		 8346 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8347 sizeof(struct bnx2x_slowpath));
8348 if (!bp->slowpath)
8349 goto alloc_mem_err;
a2fbb9ea 8350
a052997e
MS		 8351 /* Allocate memory for CDU context:
8352 * This memory is allocated separately and not in the generic ILT
8353 * functions because CDU differs in few aspects:
8354 * 1. There are multiple entities allocating memory for context -
8355 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8356 * its own ILT lines.
8357 * 2. Since CDU page-size is not a single 4KB page (which is the case
8358 * for the other ILT clients), to be efficient we want to support
8359 * allocation of sub-page-size in the last entry.
8360 * 3. Context pointers are used by the driver to pass to FW / update
8361 * the context (for the other ILT clients the pointers are used just to
8362 * free the memory during unload).
8363 */
8364 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 8365
a052997e
MS		 8366 for (i = 0, allocated = 0; allocated < context_size; i++) {
8367 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8368 (context_size - allocated));
cd2b0389
JP		 8369 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8370 bp->context[i].size);
8371 if (!bp->context[i].vcxt)
8372 goto alloc_mem_err;
a052997e
MS		 8373 allocated += bp->context[i].size;
8374 }
cd2b0389
JP		 8375 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8376 GFP_KERNEL);
8377 if (!bp->ilt->lines)
8378 goto alloc_mem_err;
65abd74d 8379
523224a3
DK		 8380 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8381 goto alloc_mem_err;
65abd74d 8382
67c431a5
AE		 8383 if (bnx2x_iov_alloc_mem(bp))
8384 goto alloc_mem_err;
8385
9f6c9258 8386 /* Slow path ring */
cd2b0389
JP		 8387 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8388 if (!bp->spq)
8389 goto alloc_mem_err;
65abd74d 8390
523224a3 8391 /* EQ */
cd2b0389
JP		 8392 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8393 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8394 if (!bp->eq_ring)
8395 goto alloc_mem_err;
ab532cf3 8396
9f6c9258 8397 return 0;
e1510706 8398
9f6c9258
DK		 8399alloc_mem_err:
8400 bnx2x_free_mem(bp);
51c1a580 8401 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 8402 return -ENOMEM;
65abd74d
YG		 8403}
8404
a2fbb9ea
ET		 8405/*
8406 * Init service functions
8407 */
a2fbb9ea 8408
619c5cb6
VZ		 8409int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8410 struct bnx2x_vlan_mac_obj *obj, bool set,
8411 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 8412{
619c5cb6
VZ		 8413 int rc;
8414 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 8415
619c5cb6 8416 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 8417
619c5cb6
VZ		 8418 /* Fill general parameters */
8419 ramrod_param.vlan_mac_obj = obj;
8420 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 8421
619c5cb6
VZ		 8422 /* Fill a user request section if needed */
8423 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8424 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 8425
619c5cb6 8426 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 8427
619c5cb6
VZ		 8428 /* Set the command: ADD or DEL */
8429 if (set)
8430 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8431 else
8432 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 8433 }
8434
619c5cb6 8435 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 8436
8437 if (rc == -EEXIST) {
8438 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8439 /* do not treat adding same MAC as error */
8440 rc = 0;
8441 } else if (rc < 0)
619c5cb6 8442 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 8443
619c5cb6 8444 return rc;
a2fbb9ea
ET		 8445}
8446
05cc5a39
YM		 8447int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8448 struct bnx2x_vlan_mac_obj *obj, bool set,
8449 unsigned long *ramrod_flags)
8450{
8451 int rc;
8452 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8453
8454 memset(&ramrod_param, 0, sizeof(ramrod_param));
8455
8456 /* Fill general parameters */
8457 ramrod_param.vlan_mac_obj = obj;
8458 ramrod_param.ramrod_flags = *ramrod_flags;
8459
8460 /* Fill a user request section if needed */
8461 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8462 ramrod_param.user_req.u.vlan.vlan = vlan;
8463 /* Set the command: ADD or DEL */
8464 if (set)
8465 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8466 else
8467 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8468 }
8469
8470 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8471
8472 if (rc == -EEXIST) {
8473 /* Do not treat adding same vlan as error. */
8474 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8475 rc = 0;
8476 } else if (rc < 0) {
8477 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8478 }
8479
8480 return rc;
8481}
8482
619c5cb6
VZ		 8483int bnx2x_del_all_macs(struct bnx2x *bp,
8484 struct bnx2x_vlan_mac_obj *mac_obj,
8485 int mac_type, bool wait_for_comp)
e665bfda 8486{
619c5cb6
VZ		 8487 int rc;
8488 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 8489
619c5cb6
VZ		 8490 /* Wait for completion of requested */
8491 if (wait_for_comp)
8492 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 8493
619c5cb6
VZ		 8494 /* Set the mac type of addresses we want to clear */
8495 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 8496
619c5cb6
VZ		 8497 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8498 if (rc < 0)
8499 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 8500
619c5cb6 8501 return rc;
0793f83f
DK		 8502}
8503
619c5cb6 8504int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 8505{
f8f4f61a
DK		 8506 if (IS_PF(bp)) {
8507 unsigned long ramrod_flags = 0;
0793f83f 8508
f8f4f61a
DK		 8509 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8510 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8511 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8512 &bp->sp_objs->mac_obj, set,
8513 BNX2X_ETH_MAC, &ramrod_flags);
8514 } else { /* vf */
8515 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
bb9e9c1d 8516 bp->fp->index, set);
f8f4f61a 8517 }
e665bfda 8518}
6e30dd4e 8519
619c5cb6 8520int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 8521{
60cad4e6
AE		 8522 if (IS_PF(bp))
8523 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8524 else /* VF */
8525 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
993ac7b5 8526}
a2fbb9ea 8527
d6214d7a 8528/**
e8920674 8529 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 8530 *
e8920674 8531 * @bp: driver handle
d6214d7a 8532 *
e8920674 8533 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 8534 */
1ab4434c 8535int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 8536{
1ab4434c
AE		 8537 int rc = 0;
8538
60cad4e6
AE		 8539 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8540 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
1ab4434c 8541 return -EINVAL;
60cad4e6 8542 }
1ab4434c 8543
9ee3d37b 8544 switch (int_mode) {
1ab4434c
AE		 8545 case BNX2X_INT_MODE_MSIX:
8546 /* attempt to enable msix */
8547 rc = bnx2x_enable_msix(bp);
8548
8549 /* msix attained */
8550 if (!rc)
8551 return 0;
8552
8553 /* vfs use only msix */
8554 if (rc && IS_VF(bp))
8555 return rc;
8556
8557 /* failed to enable multiple MSI-X */
8558 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8559 bp->num_queues,
8560 1 + bp->num_cnic_queues);
8561
8562 /* falling through... */
8563 case BNX2X_INT_MODE_MSI:
d6214d7a 8564 bnx2x_enable_msi(bp);
1ab4434c 8565
d6214d7a 8566 /* falling through... */
1ab4434c 8567 case BNX2X_INT_MODE_INTX:
55c11941
MS		 8568 bp->num_ethernet_queues = 1;
8569 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 8570 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 8571 break;
d6214d7a 8572 default:
1ab4434c
AE		 8573 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8574 return -EINVAL;
9f6c9258 8575 }
1ab4434c 8576 return 0;
a2fbb9ea
ET		 8577}
8578
1ab4434c 8579/* must be called prior to any HW initializations */
c2bff63f
DK		 8580static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8581{
290ca2bb
AE		 8582 if (IS_SRIOV(bp))
8583 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 8584 return L2_ILT_LINES(bp);
8585}
8586
523224a3
DK		 8587void bnx2x_ilt_set_info(struct bnx2x *bp)
8588{
8589 struct ilt_client_info *ilt_client;
8590 struct bnx2x_ilt *ilt = BP_ILT(bp);
8591 u16 line = 0;
8592
8593 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8594 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8595
8596 /* CDU */
8597 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8598 ilt_client->client_num = ILT_CLIENT_CDU;
8599 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8600 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8601 ilt_client->start = line;
619c5cb6 8602 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 8603
8604 if (CNIC_SUPPORT(bp))
8605 line += CNIC_ILT_LINES;
523224a3
DK		 8606 ilt_client->end = line - 1;
8607
51c1a580 8608 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8609 ilt_client->start,
8610 ilt_client->end,
8611 ilt_client->page_size,
8612 ilt_client->flags,
8613 ilog2(ilt_client->page_size >> 12));
8614
8615 /* QM */
8616 if (QM_INIT(bp->qm_cid_count)) {
8617 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8618 ilt_client->client_num = ILT_CLIENT_QM;
8619 ilt_client->page_size = QM_ILT_PAGE_SZ;
8620 ilt_client->flags = 0;
8621 ilt_client->start = line;
8622
8623 /* 4 bytes for each cid */
8624 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8625 QM_ILT_PAGE_SZ);
8626
8627 ilt_client->end = line - 1;
8628
51c1a580
MS		 8629 DP(NETIF_MSG_IFUP,
8630 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8631 ilt_client->start,
8632 ilt_client->end,
8633 ilt_client->page_size,
8634 ilt_client->flags,
8635 ilog2(ilt_client->page_size >> 12));
523224a3 8636 }
523224a3 8637
55c11941
MS		 8638 if (CNIC_SUPPORT(bp)) {
8639 /* SRC */
8640 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8641 ilt_client->client_num = ILT_CLIENT_SRC;
8642 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8643 ilt_client->flags = 0;
8644 ilt_client->start = line;
8645 line += SRC_ILT_LINES;
8646 ilt_client->end = line - 1;
523224a3 8647
55c11941
MS		 8648 DP(NETIF_MSG_IFUP,
8649 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8650 ilt_client->start,
8651 ilt_client->end,
8652 ilt_client->page_size,
8653 ilt_client->flags,
8654 ilog2(ilt_client->page_size >> 12));
9f6c9258 8655
55c11941
MS		 8656 /* TM */
8657 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8658 ilt_client->client_num = ILT_CLIENT_TM;
8659 ilt_client->page_size = TM_ILT_PAGE_SZ;
8660 ilt_client->flags = 0;
8661 ilt_client->start = line;
8662 line += TM_ILT_LINES;
8663 ilt_client->end = line - 1;
523224a3 8664
55c11941
MS		 8665 DP(NETIF_MSG_IFUP,
8666 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8667 ilt_client->start,
8668 ilt_client->end,
8669 ilt_client->page_size,
8670 ilt_client->flags,
8671 ilog2(ilt_client->page_size >> 12));
8672 }
9f6c9258 8673
619c5cb6 8674 BUG_ON(line > ILT_MAX_LINES);
523224a3 8675}
f85582f8 8676
619c5cb6
VZ		 8677/**
8678 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8679 *
8680 * @bp: driver handle
8681 * @fp: pointer to fastpath
8682 * @init_params: pointer to parameters structure
8683 *
8684 * parameters configured:
8685 * - HC configuration
8686 * - Queue's CDU context
8687 */
1191cb83 8688static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8689 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8690{
6383c0b3 8691 u8 cos;
a052997e
MS		 8692 int cxt_index, cxt_offset;
8693
619c5cb6
VZ		 8694 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8695 if (!IS_FCOE_FP(fp)) {
8696 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8697 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8698
16a5fd92 8699 /* If HC is supported, enable host coalescing in the transition
619c5cb6
VZ		 8700 * to INIT state.
8701 */
8702 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8703 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8704
8705 /* HC rate */
8706 init_params->rx.hc_rate = bp->rx_ticks ?
8707 (1000000 / bp->rx_ticks) : 0;
8708 init_params->tx.hc_rate = bp->tx_ticks ?
8709 (1000000 / bp->tx_ticks) : 0;
8710
8711 /* FW SB ID */
8712 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8713 fp->fw_sb_id;
8714
8715 /*
8716 * CQ index among the SB indices: FCoE clients uses the default
8717 * SB, therefore it's different.
8718 */
6383c0b3
AE		 8719 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8720 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8721 }
8722
6383c0b3
AE		 8723 /* set maximum number of COSs supported by this queue */
8724 init_params->max_cos = fp->max_cos;
8725
51c1a580 8726 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8727 fp->index, init_params->max_cos);
8728
8729 /* set the context pointers queue object */
a052997e 8730 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8731 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8732 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8733 ILT_PAGE_CIDS);
6383c0b3 8734 init_params->cxts[cos] =
a052997e
MS		 8735 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8736 }
619c5cb6
VZ		 8737}
8738
910cc727 8739static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8740 struct bnx2x_queue_state_params *q_params,
8741 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8742 int tx_index, bool leading)
8743{
8744 memset(tx_only_params, 0, sizeof(*tx_only_params));
8745
8746 /* Set the command */
8747 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8748
8749 /* Set tx-only QUEUE flags: don't zero statistics */
8750 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8751
8752 /* choose the index of the cid to send the slow path on */
8753 tx_only_params->cid_index = tx_index;
8754
8755 /* Set general TX_ONLY_SETUP parameters */
8756 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8757
8758 /* Set Tx TX_ONLY_SETUP parameters */
8759 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8760
51c1a580
MS		 8761 DP(NETIF_MSG_IFUP,
8762 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8763 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8764 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8765 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8766
8767 /* send the ramrod */
8768 return bnx2x_queue_state_change(bp, q_params);
8769}
8770
619c5cb6
VZ		 8771/**
8772 * bnx2x_setup_queue - setup queue
8773 *
8774 * @bp: driver handle
8775 * @fp: pointer to fastpath
8776 * @leading: is leading
8777 *
8778 * This function performs 2 steps in a Queue state machine
8779 * actually: 1) RESET->INIT 2) INIT->SETUP
8780 */
8781
8782int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8783 bool leading)
8784{
3b603066 8785 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8786 struct bnx2x_queue_setup_params *setup_params =
8787 &q_params.params.setup;
6383c0b3
AE		 8788 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8789 &q_params.params.tx_only;
a2fbb9ea 8790 int rc;
6383c0b3
AE		 8791 u8 tx_index;
8792
51c1a580 8793 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8794
ec6ba945
VZ		 8795 /* reset IGU state skip FCoE L2 queue */
8796 if (!IS_FCOE_FP(fp))
8797 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8798 IGU_INT_ENABLE, 0);
a2fbb9ea 8799
15192a8c 8800 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8801 /* We want to wait for completion in this context */
8802 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8803
619c5cb6
VZ		 8804 /* Prepare the INIT parameters */
8805 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8806
619c5cb6
VZ		 8807 /* Set the command */
8808 q_params.cmd = BNX2X_Q_CMD_INIT;
8809
8810 /* Change the state to INIT */
8811 rc = bnx2x_queue_state_change(bp, &q_params);
8812 if (rc) {
6383c0b3 8813 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8814 return rc;
8815 }
ec6ba945 8816
51c1a580 8817 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3 8818
619c5cb6
VZ		 8819 /* Now move the Queue to the SETUP state... */
8820 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8821
619c5cb6
VZ		 8822 /* Set QUEUE flags */
8823 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8824
619c5cb6 8825 /* Set general SETUP parameters */
6383c0b3
AE		 8826 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8827 FIRST_TX_COS_INDEX);
619c5cb6 8828
6383c0b3 8829 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8830 &setup_params->rxq_params);
8831
6383c0b3
AE		 8832 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8833 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8834
8835 /* Set the command */
8836 q_params.cmd = BNX2X_Q_CMD_SETUP;
8837
55c11941
MS		 8838 if (IS_FCOE_FP(fp))
8839 bp->fcoe_init = true;
8840
619c5cb6
VZ		 8841 /* Change the state to SETUP */
8842 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8843 if (rc) {
8844 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8845 return rc;
8846 }
8847
8848 /* loop through the relevant tx-only indices */
8849 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8850 tx_index < fp->max_cos;
8851 tx_index++) {
8852
8853 /* prepare and send tx-only ramrod*/
8854 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8855 tx_only_params, tx_index, leading);
8856 if (rc) {
8857 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8858 fp->index, tx_index);
8859 return rc;
8860 }
8861 }
523224a3 8862
34f80b04 8863 return rc;
a2fbb9ea
ET		 8864}
8865
619c5cb6 8866static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8867{
619c5cb6 8868 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8869 struct bnx2x_fp_txdata *txdata;
3b603066 8870 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8871 int rc, tx_index;
8872
51c1a580 8873 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8874
15192a8c 8875 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8876 /* We want to wait for completion in this context */
8877 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8878
6383c0b3
AE		 8879 /* close tx-only connections */
8880 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8881 tx_index < fp->max_cos;
8882 tx_index++){
8883
8884 /* ascertain this is a normal queue*/
65565884 8885 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8886
51c1a580 8887 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8888 txdata->txq_index);
8889
8890 /* send halt terminate on tx-only connection */
8891 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8892 memset(&q_params.params.terminate, 0,
8893 sizeof(q_params.params.terminate));
8894 q_params.params.terminate.cid_index = tx_index;
8895
8896 rc = bnx2x_queue_state_change(bp, &q_params);
8897 if (rc)
8898 return rc;
8899
8900 /* send halt terminate on tx-only connection */
8901 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8902 memset(&q_params.params.cfc_del, 0,
8903 sizeof(q_params.params.cfc_del));
8904 q_params.params.cfc_del.cid_index = tx_index;
8905 rc = bnx2x_queue_state_change(bp, &q_params);
8906 if (rc)
8907 return rc;
8908 }
8909 /* Stop the primary connection: */
8910 /* ...halt the connection */
619c5cb6
VZ		 8911 q_params.cmd = BNX2X_Q_CMD_HALT;
8912 rc = bnx2x_queue_state_change(bp, &q_params);
8913 if (rc)
da5a662a 8914 return rc;
a2fbb9ea 8915
6383c0b3 8916 /* ...terminate the connection */
619c5cb6 8917 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8918 memset(&q_params.params.terminate, 0,
8919 sizeof(q_params.params.terminate));
8920 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8921 rc = bnx2x_queue_state_change(bp, &q_params);
8922 if (rc)
523224a3 8923 return rc;
6383c0b3 8924 /* ...delete cfc entry */
619c5cb6 8925 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8926 memset(&q_params.params.cfc_del, 0,
8927 sizeof(q_params.params.cfc_del));
8928 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8929 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8930}
8931
34f80b04
EG		 8932static void bnx2x_reset_func(struct bnx2x *bp)
8933{
8934 int port = BP_PORT(bp);
8935 int func = BP_FUNC(bp);
f2e0899f 8936 int i;
523224a3
DK		 8937
8938 /* Disable the function in the FW */
8939 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8940 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8941 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8942 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8943
8944 /* FP SBs */
ec6ba945 8945 for_each_eth_queue(bp, i) {
523224a3 8946 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8947 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8948 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8949 SB_DISABLED);
523224a3
DK		 8950 }
8951
55c11941
MS		 8952 if (CNIC_LOADED(bp))
8953 /* CNIC SB */
8954 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8955 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8956 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8957
523224a3 8958 /* SP SB */
619c5cb6 8959 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2de67439
YM		 8960 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8961 SB_DISABLED);
523224a3
DK		 8962
8963 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8964 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8965 0);
34f80b04
EG		 8966
8967 /* Configure IGU */
f2e0899f
DK		 8968 if (bp->common.int_block == INT_BLOCK_HC) {
8969 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8970 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8971 } else {
8972 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8973 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8974 }
34f80b04 8975
55c11941
MS		 8976 if (CNIC_LOADED(bp)) {
8977 /* Disable Timer scan */
8978 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8979 /*
8980 * Wait for at least 10ms and up to 2 second for the timers
8981 * scan to complete
8982 */
8983 for (i = 0; i < 200; i++) {
639d65b8 8984 usleep_range(10000, 20000);
55c11941
MS		 8985 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8986 break;
8987 }
37b091ba 8988 }
34f80b04 8989 /* Clear ILT */
f2e0899f
DK		 8990 bnx2x_clear_func_ilt(bp, func);
8991
8992 /* Timers workaround bug for E2: if this is vnic-3,
8993 * we need to set the entire ilt range for this timers.
8994 */
619c5cb6 8995 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 8996 struct ilt_client_info ilt_cli;
8997 /* use dummy TM client */
8998 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8999 ilt_cli.start = 0;
9000 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9001 ilt_cli.client_num = ILT_CLIENT_TM;
9002
9003 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9004 }
9005
9006 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 9007 if (!CHIP_IS_E1x(bp))
f2e0899f 9008 bnx2x_pf_disable(bp);
523224a3
DK		 9009
9010 bp->dmae_ready = 0;
34f80b04
EG		 9011}
9012
9013static void bnx2x_reset_port(struct bnx2x *bp)
9014{
9015 int port = BP_PORT(bp);
9016 u32 val;
9017
619c5cb6
VZ		 9018 /* Reset physical Link */
9019 bnx2x__link_reset(bp);
9020
34f80b04
EG		 9021 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9022
9023 /* Do not rcv packets to BRB */
9024 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9025 /* Do not direct rcv packets that are not for MCP to the BRB */
9026 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9027 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9028
9029 /* Configure AEU */
9030 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9031
9032 msleep(100);
9033 /* Check for BRB port occupancy */
9034 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9035 if (val)
9036 DP(NETIF_MSG_IFDOWN,
33471629 9037 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 9038
9039 /* TODO: Close Doorbell port? */
9040}
9041
1191cb83 9042static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 9043{
3b603066 9044 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 9045
619c5cb6
VZ		 9046 /* Prepare parameters for function state transitions */
9047 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 9048
619c5cb6
VZ		 9049 func_params.f_obj = &bp->func_obj;
9050 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 9051
619c5cb6 9052 func_params.params.hw_init.load_phase = load_code;
49d66772 9053
619c5cb6 9054 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 9055}
9056
1191cb83 9057static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 9058{
3b603066 9059 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 9060 int rc;
228241eb 9061
619c5cb6
VZ		 9062 /* Prepare parameters for function state transitions */
9063 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9064 func_params.f_obj = &bp->func_obj;
9065 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 9066
619c5cb6
VZ		 9067 /*
9068 * Try to stop the function the 'good way'. If fails (in case
9069 * of a parity error during bnx2x_chip_cleanup()) and we are
9070 * not in a debug mode, perform a state transaction in order to
9071 * enable further HW_RESET transaction.
9072 */
9073 rc = bnx2x_func_state_change(bp, &func_params);
9074 if (rc) {
34f80b04 9075#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 9076 return rc;
34f80b04 9077#else
51c1a580 9078 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 9079 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9080 return bnx2x_func_state_change(bp, &func_params);
34f80b04 9081#endif
228241eb 9082 }
a2fbb9ea 9083
619c5cb6
VZ		 9084 return 0;
9085}
523224a3 9086
619c5cb6
VZ		 9087/**
9088 * bnx2x_send_unload_req - request unload mode from the MCP.
9089 *
9090 * @bp: driver handle
9091 * @unload_mode: requested function's unload mode
9092 *
9093 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9094 */
9095u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9096{
9097 u32 reset_code = 0;
9098 int port = BP_PORT(bp);
3101c2bc 9099
619c5cb6 9100 /* Select the UNLOAD request mode */
65abd74d
YG		 9101 if (unload_mode == UNLOAD_NORMAL)
9102 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9103
7d0446c2 9104 else if (bp->flags & NO_WOL_FLAG)
65abd74d 9105 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 9106
7d0446c2 9107 else if (bp->wol) {
65abd74d
YG		 9108 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9109 u8 *mac_addr = bp->dev->dev_addr;
29ed74c3 9110 struct pci_dev *pdev = bp->pdev;
65abd74d 9111 u32 val;
f9977903
DK		 9112 u16 pmc;
9113
65abd74d 9114 /* The mac address is written to entries 1-4 to
f9977903
DK		 9115 * preserve entry 0 which is used by the PMF
9116 */
3395a033 9117 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 9118
9119 val = (mac_addr[0] << 8) | mac_addr[1];
9120 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9121
9122 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9123 (mac_addr[4] << 8) | mac_addr[5];
9124 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9125
f9977903 9126 /* Enable the PME and clear the status */
29ed74c3 9127 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
f9977903 9128 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
29ed74c3 9129 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
f9977903 9130
65abd74d
YG		 9131 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9132
9133 } else
9134 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 9135
619c5cb6
VZ		 9136 /* Send the request to the MCP */
9137 if (!BP_NOMCP(bp))
9138 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9139 else {
9140 int path = BP_PATH(bp);
9141
51c1a580 9142 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
a8f47eb7 9143 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9144 bnx2x_load_count[path][2]);
9145 bnx2x_load_count[path][0]--;
9146 bnx2x_load_count[path][1 + port]--;
51c1a580 9147 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
a8f47eb7 9148 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9149 bnx2x_load_count[path][2]);
9150 if (bnx2x_load_count[path][0] == 0)
619c5cb6 9151 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
a8f47eb7 9152 else if (bnx2x_load_count[path][1 + port] == 0)
619c5cb6
VZ		 9153 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9154 else
9155 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9156 }
9157
9158 return reset_code;
9159}
9160
9161/**
9162 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9163 *
9164 * @bp: driver handle
5d07d868 9165 * @keep_link: true iff link should be kept up
619c5cb6 9166 */
5d07d868 9167void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 9168{
5d07d868
YM		 9169 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9170
619c5cb6
VZ		 9171 /* Report UNLOAD_DONE to MCP */
9172 if (!BP_NOMCP(bp))
5d07d868 9173 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 9174}
9175
1191cb83 9176static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 9177{
9178 int tout = 50;
9179 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9180
9181 if (!bp->port.pmf)
9182 return 0;
9183
9184 /*
9185 * (assumption: No Attention from MCP at this stage)
16a5fd92 9186 * PMF probably in the middle of TX disable/enable transaction
6debea87 9187 * 1. Sync IRS for default SB
16a5fd92
YM		 9188 * 2. Sync SP queue - this guarantees us that attention handling started
9189 * 3. Wait, that TX disable/enable transaction completes
6debea87 9190 *
16a5fd92
YM		 9191 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9192 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9193 * received completion for the transaction the state is TX_STOPPED.
6debea87
DK		 9194 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9195 * transaction.
9196 */
9197
9198 /* make sure default SB ISR is done */
9199 if (msix)
9200 synchronize_irq(bp->msix_table[0].vector);
9201 else
9202 synchronize_irq(bp->pdev->irq);
9203
9204 flush_workqueue(bnx2x_wq);
370d4a26 9205 flush_workqueue(bnx2x_iov_wq);
6debea87
DK		 9206
9207 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9208 BNX2X_F_STATE_STARTED && tout--)
9209 msleep(20);
9210
9211 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9212 BNX2X_F_STATE_STARTED) {
9213#ifdef BNX2X_STOP_ON_ERROR
51c1a580 9214 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 9215 return -EBUSY;
9216#else
9217 /*
9218 * Failed to complete the transaction in a "good way"
9219 * Force both transactions with CLR bit
9220 */
3b603066 9221 struct bnx2x_func_state_params func_params = {NULL};
6debea87 9222
51c1a580 9223 DP(NETIF_MSG_IFDOWN,
0c23ad37 9224 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
6debea87
DK		 9225
9226 func_params.f_obj = &bp->func_obj;
9227 __set_bit(RAMROD_DRV_CLR_ONLY,
9228 &func_params.ramrod_flags);
9229
9230 /* STARTED-->TX_ST0PPED */
9231 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9232 bnx2x_func_state_change(bp, &func_params);
9233
9234 /* TX_ST0PPED-->STARTED */
9235 func_params.cmd = BNX2X_F_CMD_TX_START;
9236 return bnx2x_func_state_change(bp, &func_params);
9237#endif
9238 }
9239
9240 return 0;
9241}
9242
eeed018c
MK		 9243static void bnx2x_disable_ptp(struct bnx2x *bp)
9244{
9245 int port = BP_PORT(bp);
9246
9247 /* Disable sending PTP packets to host */
9248 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9249 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9250
9251 /* Reset PTP event detection rules */
9252 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9253 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9254 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9255 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9256 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9257 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9258 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9259 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9260
9261 /* Disable the PTP feature */
9262 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9263 NIG_REG_P0_PTP_EN, 0x0);
9264}
9265
9266/* Called during unload, to stop PTP-related stuff */
1444c301 9267static void bnx2x_stop_ptp(struct bnx2x *bp)
eeed018c
MK		 9268{
9269 /* Cancel PTP work queue. Should be done after the Tx queues are
9270 * drained to prevent additional scheduling.
9271 */
9272 cancel_work_sync(&bp->ptp_task);
9273
9274 if (bp->ptp_tx_skb) {
9275 dev_kfree_skb_any(bp->ptp_tx_skb);
9276 bp->ptp_tx_skb = NULL;
9277 }
9278
9279 /* Disable PTP in HW */
9280 bnx2x_disable_ptp(bp);
9281
9282 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9283}
9284
5d07d868 9285void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 9286{
9287 int port = BP_PORT(bp);
6383c0b3
AE		 9288 int i, rc = 0;
9289 u8 cos;
3b603066 9290 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 9291 u32 reset_code;
9292
9293 /* Wait until tx fastpath tasks complete */
9294 for_each_tx_queue(bp, i) {
9295 struct bnx2x_fastpath *fp = &bp->fp[i];
9296
6383c0b3 9297 for_each_cos_in_tx_queue(fp, cos)
65565884 9298 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 9299#ifdef BNX2X_STOP_ON_ERROR
9300 if (rc)
9301 return;
9302#endif
9303 }
9304
9305 /* Give HW time to discard old tx messages */
0926d499 9306 usleep_range(1000, 2000);
619c5cb6
VZ		 9307
9308 /* Clean all ETH MACs */
15192a8c
BW		 9309 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9310 false);
619c5cb6
VZ		 9311 if (rc < 0)
9312 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9313
9314 /* Clean up UC list */
15192a8c 9315 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 9316 true);
9317 if (rc < 0)
51c1a580
MS		 9318 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9319 rc);
619c5cb6
VZ		 9320
9321 /* Disable LLH */
9322 if (!CHIP_IS_E1(bp))
9323 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9324
9325 /* Set "drop all" (stop Rx).
9326 * We need to take a netif_addr_lock() here in order to prevent
9327 * a race between the completion code and this code.
9328 */
9329 netif_addr_lock_bh(bp->dev);
9330 /* Schedule the rx_mode command */
9331 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9332 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9333 else
9334 bnx2x_set_storm_rx_mode(bp);
9335
9336 /* Cleanup multicast configuration */
9337 rparam.mcast_obj = &bp->mcast_obj;
9338 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9339 if (rc < 0)
9340 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9341
9342 netif_addr_unlock_bh(bp->dev);
9343
f1929b01 9344 bnx2x_iov_chip_cleanup(bp);
619c5cb6 9345
6debea87
DK		 9346 /*
9347 * Send the UNLOAD_REQUEST to the MCP. This will return if
9348 * this function should perform FUNC, PORT or COMMON HW
9349 * reset.
9350 */
9351 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9352
9353 /*
9354 * (assumption: No Attention from MCP at this stage)
16a5fd92 9355 * PMF probably in the middle of TX disable/enable transaction
6debea87
DK		 9356 */
9357 rc = bnx2x_func_wait_started(bp);
9358 if (rc) {
9359 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9360#ifdef BNX2X_STOP_ON_ERROR
9361 return;
9362#endif
9363 }
9364
34f80b04 9365 /* Close multi and leading connections
619c5cb6
VZ		 9366 * Completions for ramrods are collected in a synchronous way
9367 */
55c11941 9368 for_each_eth_queue(bp, i)
619c5cb6 9369 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 9370#ifdef BNX2X_STOP_ON_ERROR
9371 return;
9372#else
228241eb 9373 goto unload_error;
523224a3 9374#endif
55c11941
MS		 9375
9376 if (CNIC_LOADED(bp)) {
9377 for_each_cnic_queue(bp, i)
9378 if (bnx2x_stop_queue(bp, i))
9379#ifdef BNX2X_STOP_ON_ERROR
9380 return;
9381#else
9382 goto unload_error;
9383#endif
9384 }
9385
619c5cb6
VZ		 9386 /* If SP settings didn't get completed so far - something
9387 * very wrong has happen.
9388 */
9389 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9390 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 9391
619c5cb6
VZ		 9392#ifndef BNX2X_STOP_ON_ERROR
9393unload_error:
9394#endif
523224a3 9395 rc = bnx2x_func_stop(bp);
da5a662a 9396 if (rc) {
523224a3 9397 BNX2X_ERR("Function stop failed!\n");
da5a662a 9398#ifdef BNX2X_STOP_ON_ERROR
523224a3 9399 return;
523224a3 9400#endif
34f80b04 9401 }
a2fbb9ea 9402
eeed018c
MK		 9403 /* stop_ptp should be after the Tx queues are drained to prevent
9404 * scheduling to the cancelled PTP work queue. It should also be after
9405 * function stop ramrod is sent, since as part of this ramrod FW access
9406 * PTP registers.
9407 */
d53c66a5
ED		 9408 if (bp->flags & PTP_SUPPORTED)
9409 bnx2x_stop_ptp(bp);
eeed018c 9410
523224a3
DK		 9411 /* Disable HW interrupts, NAPI */
9412 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 9413 /* Delete all NAPI objects */
9414 bnx2x_del_all_napi(bp);
55c11941
MS		 9415 if (CNIC_LOADED(bp))
9416 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 9417
9418 /* Release IRQs */
d6214d7a 9419 bnx2x_free_irq(bp);
523224a3 9420
a2fbb9ea 9421 /* Reset the chip */
619c5cb6
VZ		 9422 rc = bnx2x_reset_hw(bp, reset_code);
9423 if (rc)
9424 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 9425
619c5cb6 9426 /* Report UNLOAD_DONE to MCP */
5d07d868 9427 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 9428}
9429
9f6c9258 9430void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 9431{
9432 u32 val;
9433
51c1a580 9434 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 9435
9436 if (CHIP_IS_E1(bp)) {
9437 int port = BP_PORT(bp);
9438 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9439 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9440
9441 val = REG_RD(bp, addr);
9442 val &= ~(0x300);
9443 REG_WR(bp, addr, val);
619c5cb6 9444 } else {
72fd0718
VZ		 9445 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9446 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9447 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9448 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9449 }
9450}
9451
72fd0718
VZ		 9452/* Close gates #2, #3 and #4: */
9453static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9454{
c9ee9206 9455 u32 val;
72fd0718
VZ		 9456
9457 /* Gates #2 and #4a are closed/opened for "not E1" only */
9458 if (!CHIP_IS_E1(bp)) {
9459 /* #4 */
c9ee9206 9460 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 9461 /* #2 */
c9ee9206 9462 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 9463 }
9464
9465 /* #3 */
c9ee9206
VZ		 9466 if (CHIP_IS_E1x(bp)) {
9467 /* Prevent interrupts from HC on both ports */
9468 val = REG_RD(bp, HC_REG_CONFIG_1);
9469 REG_WR(bp, HC_REG_CONFIG_1,
9470 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9471 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9472
9473 val = REG_RD(bp, HC_REG_CONFIG_0);
9474 REG_WR(bp, HC_REG_CONFIG_0,
9475 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9476 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9477 } else {
d82603c6 9478 /* Prevent incoming interrupts in IGU */
c9ee9206
VZ		 9479 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9480
9481 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9482 (!close) ?
9483 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9484 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9485 }
72fd0718 9486
51c1a580 9487 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 9488 close ? "closing" : "opening");
9489 mmiowb();
9490}
9491
9492#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9493
9494static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9495{
9496 /* Do some magic... */
9497 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9498 *magic_val = val & SHARED_MF_CLP_MAGIC;
9499 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9500}
9501
e8920674
DK		 9502/**
9503 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 9504 *
e8920674
DK		 9505 * @bp: driver handle
9506 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 9507 */
9508static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9509{
9510 /* Restore the `magic' bit value... */
72fd0718
VZ		 9511 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9512 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9513 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9514}
9515
f85582f8 9516/**
e8920674 9517 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 9518 *
e8920674
DK		 9519 * @bp: driver handle
9520 * @magic_val: old value of 'magic' bit.
9521 *
9522 * Takes care of CLP configurations.
72fd0718
VZ		 9523 */
9524static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9525{
9526 u32 shmem;
9527 u32 validity_offset;
9528
51c1a580 9529 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 9530
9531 /* Set `magic' bit in order to save MF config */
9532 if (!CHIP_IS_E1(bp))
9533 bnx2x_clp_reset_prep(bp, magic_val);
9534
9535 /* Get shmem offset */
9536 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 9537 validity_offset =
9538 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 9539
9540 /* Clear validity map flags */
9541 if (shmem > 0)
9542 REG_WR(bp, shmem + validity_offset, 0);
9543}
9544
9545#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9546#define MCP_ONE_TIMEOUT 100 /* 100 ms */
9547
e8920674
DK		 9548/**
9549 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 9550 *
e8920674 9551 * @bp: driver handle
72fd0718 9552 */
1191cb83 9553static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 9554{
9555 /* special handling for emulation and FPGA,
9556 wait 10 times longer */
9557 if (CHIP_REV_IS_SLOW(bp))
9558 msleep(MCP_ONE_TIMEOUT*10);
9559 else
9560 msleep(MCP_ONE_TIMEOUT);
9561}
9562
1b6e2ceb
DK		 9563/*
9564 * initializes bp->common.shmem_base and waits for validity signature to appear
9565 */
9566static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 9567{
1b6e2ceb
DK		 9568 int cnt = 0;
9569 u32 val = 0;
72fd0718 9570
1b6e2ceb
DK		 9571 do {
9572 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9573 if (bp->common.shmem_base) {
9574 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9575 if (val & SHR_MEM_VALIDITY_MB)
9576 return 0;
9577 }
72fd0718 9578
1b6e2ceb 9579 bnx2x_mcp_wait_one(bp);
72fd0718 9580
1b6e2ceb 9581 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 9582
1b6e2ceb 9583 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 9584
1b6e2ceb
DK		 9585 return -ENODEV;
9586}
72fd0718 9587
1b6e2ceb
DK		 9588static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9589{
9590 int rc = bnx2x_init_shmem(bp);
72fd0718 9591
72fd0718
VZ		 9592 /* Restore the `magic' bit value */
9593 if (!CHIP_IS_E1(bp))
9594 bnx2x_clp_reset_done(bp, magic_val);
9595
9596 return rc;
9597}
9598
9599static void bnx2x_pxp_prep(struct bnx2x *bp)
9600{
9601 if (!CHIP_IS_E1(bp)) {
9602 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9603 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 9604 mmiowb();
9605 }
9606}
9607
9608/*
9609 * Reset the whole chip except for:
9610 * - PCIE core
9611 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9612 * one reset bit)
9613 * - IGU
9614 * - MISC (including AEU)
9615 * - GRC
9616 * - RBCN, RBCP
9617 */
c9ee9206 9618static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 9619{
9620 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 9621 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 9622
9623 /*
9624 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9625 * (per chip) blocks.
9626 */
9627 global_bits2 =
9628 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9629 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 9630
c55e771b
BW		 9631 /* Don't reset the following blocks.
9632 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9633 * reset, as in 4 port device they might still be owned
9634 * by the MCP (there is only one leader per path).
9635 */
72fd0718
VZ		 9636 not_reset_mask1 =
9637 MISC_REGISTERS_RESET_REG_1_RST_HC |
9638 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9639 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9640
9641 not_reset_mask2 =
c9ee9206 9642 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 9643 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9644 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9645 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9646 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9647 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9648 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 9649 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9650 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 9651 MISC_REGISTERS_RESET_REG_2_PGLC |
9652 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9653 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9654 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9655 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9656 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9657 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 9658
8736c826
VZ		 9659 /*
9660 * Keep the following blocks in reset:
9661 * - all xxMACs are handled by the bnx2x_link code.
9662 */
9663 stay_reset2 =
8736c826
VZ		 9664 MISC_REGISTERS_RESET_REG_2_XMAC |
9665 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9666
9667 /* Full reset masks according to the chip */
72fd0718
VZ		 9668 reset_mask1 = 0xffffffff;
9669
9670 if (CHIP_IS_E1(bp))
9671 reset_mask2 = 0xffff;
8736c826 9672 else if (CHIP_IS_E1H(bp))
72fd0718 9673 reset_mask2 = 0x1ffff;
8736c826
VZ		 9674 else if (CHIP_IS_E2(bp))
9675 reset_mask2 = 0xfffff;
9676 else /* CHIP_IS_E3 */
9677 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 9678
9679 /* Don't reset global blocks unless we need to */
9680 if (!global)
9681 reset_mask2 &= ~global_bits2;
9682
9683 /*
9684 * In case of attention in the QM, we need to reset PXP
9685 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9686 * because otherwise QM reset would release 'close the gates' shortly
9687 * before resetting the PXP, then the PSWRQ would send a write
9688 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9689 * read the payload data from PSWWR, but PSWWR would not
9690 * respond. The write queue in PGLUE would stuck, dmae commands
9691 * would not return. Therefore it's important to reset the second
9692 * reset register (containing the
9693 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9694 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9695 * bit).
9696 */
72fd0718
VZ		 9697 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9698 reset_mask2 & (~not_reset_mask2));
9699
c9ee9206
VZ		 9700 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9701 reset_mask1 & (~not_reset_mask1));
9702
72fd0718
VZ		 9703 barrier();
9704 mmiowb();
9705
8736c826
VZ		 9706 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9707 reset_mask2 & (~stay_reset2));
9708
9709 barrier();
9710 mmiowb();
9711
c9ee9206 9712 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 9713 mmiowb();
9714}
9715
c9ee9206
VZ		 9716/**
9717 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9718 * It should get cleared in no more than 1s.
9719 *
9720 * @bp: driver handle
9721 *
9722 * It should get cleared in no more than 1s. Returns 0 if
9723 * pending writes bit gets cleared.
9724 */
9725static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9726{
9727 u32 cnt = 1000;
9728 u32 pend_bits = 0;
9729
9730 do {
9731 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9732
9733 if (pend_bits == 0)
9734 break;
9735
0926d499 9736 usleep_range(1000, 2000);
c9ee9206
VZ		 9737 } while (cnt-- > 0);
9738
9739 if (cnt <= 0) {
9740 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9741 pend_bits);
9742 return -EBUSY;
9743 }
9744
9745 return 0;
9746}
9747
9748static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9749{
9750 int cnt = 1000;
9751 u32 val = 0;
9752 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
2de67439 9753 u32 tags_63_32 = 0;
72fd0718
VZ		 9754
9755 /* Empty the Tetris buffer, wait for 1s */
9756 do {
9757 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9758 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9759 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9760 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9761 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9762 if (CHIP_IS_E3(bp))
9763 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9764
72fd0718
VZ		 9765 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9766 ((port_is_idle_0 & 0x1) == 0x1) &&
9767 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9768 (pgl_exp_rom2 == 0xffffffff) &&
9769 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9770 break;
0926d499 9771 usleep_range(1000, 2000);
72fd0718
VZ		 9772 } while (cnt-- > 0);
9773
9774 if (cnt <= 0) {
51c1a580
MS		 9775 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9776 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9777 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9778 pgl_exp_rom2);
9779 return -EAGAIN;
9780 }
9781
9782 barrier();
9783
9784 /* Close gates #2, #3 and #4 */
9785 bnx2x_set_234_gates(bp, true);
9786
c9ee9206
VZ		 9787 /* Poll for IGU VQs for 57712 and newer chips */
9788 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9789 return -EAGAIN;
9790
72fd0718
VZ		 9791 /* TBD: Indicate that "process kill" is in progress to MCP */
9792
9793 /* Clear "unprepared" bit */
9794 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9795 barrier();
9796
9797 /* Make sure all is written to the chip before the reset */
9798 mmiowb();
9799
9800 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9801 * PSWHST, GRC and PSWRD Tetris buffer.
9802 */
0926d499 9803 usleep_range(1000, 2000);
72fd0718
VZ		 9804
9805 /* Prepare to chip reset: */
9806 /* MCP */
c9ee9206
VZ		 9807 if (global)
9808 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9809
9810 /* PXP */
9811 bnx2x_pxp_prep(bp);
9812 barrier();
9813
9814 /* reset the chip */
c9ee9206 9815 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9816 barrier();
9817
9dcd9acd
DK		 9818 /* clear errors in PGB */
9819 if (!CHIP_IS_E1x(bp))
9820 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9821
72fd0718
VZ		 9822 /* Recover after reset: */
9823 /* MCP */
c9ee9206 9824 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9825 return -EAGAIN;
9826
c9ee9206
VZ		 9827 /* TBD: Add resetting the NO_MCP mode DB here */
9828
72fd0718
VZ		 9829 /* Open the gates #2, #3 and #4 */
9830 bnx2x_set_234_gates(bp, false);
9831
9832 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9833 * reset state, re-enable attentions. */
9834
a2fbb9ea
ET		 9835 return 0;
9836}
9837
910cc727 9838static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9839{
9840 int rc = 0;
c9ee9206 9841 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9842 u32 load_code;
9843
9844 /* if not going to reset MCP - load "fake" driver to reset HW while
9845 * driver is owner of the HW
9846 */
9847 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9848 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9849 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9850 if (!load_code) {
9851 BNX2X_ERR("MCP response failure, aborting\n");
9852 rc = -EAGAIN;
9853 goto exit_leader_reset;
9854 }
9855 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9856 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9857 BNX2X_ERR("MCP unexpected resp, aborting\n");
9858 rc = -EAGAIN;
9859 goto exit_leader_reset2;
9860 }
9861 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9862 if (!load_code) {
9863 BNX2X_ERR("MCP response failure, aborting\n");
9864 rc = -EAGAIN;
9865 goto exit_leader_reset2;
9866 }
9867 }
c9ee9206 9868
72fd0718 9869 /* Try to recover after the failure */
c9ee9206 9870 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9871 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9872 BP_PATH(bp));
72fd0718 9873 rc = -EAGAIN;
95c6c616 9874 goto exit_leader_reset2;
72fd0718
VZ		 9875 }
9876
c9ee9206
VZ		 9877 /*
9878 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9879 * state.
9880 */
72fd0718 9881 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9882 if (global)
9883 bnx2x_clear_reset_global(bp);
72fd0718 9884
95c6c616
AE		 9885exit_leader_reset2:
9886 /* unload "fake driver" if it was loaded */
9887 if (!global && !BP_NOMCP(bp)) {
9888 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9889 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9890 }
72fd0718
VZ		 9891exit_leader_reset:
9892 bp->is_leader = 0;
c9ee9206
VZ		 9893 bnx2x_release_leader_lock(bp);
9894 smp_mb();
72fd0718
VZ		 9895 return rc;
9896}
9897
1191cb83 9898static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9899{
9900 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9901
9902 /* Disconnect this device */
9903 netif_device_detach(bp->dev);
9904
9905 /*
9906 * Block ifup for all function on this engine until "process kill"
9907 * or power cycle.
9908 */
9909 bnx2x_set_reset_in_progress(bp);
9910
9911 /* Shut down the power */
9912 bnx2x_set_power_state(bp, PCI_D3hot);
9913
9914 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9915
9916 smp_mb();
9917}
9918
9919/*
9920 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9921 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9922 * will never be called when netif_running(bp->dev) is false.
9923 */
9924static void bnx2x_parity_recover(struct bnx2x *bp)
9925{
c9ee9206 9926 bool global = false;
7a752993 9927 u32 error_recovered, error_unrecovered;
95c6c616 9928 bool is_parity;
c9ee9206 9929
72fd0718
VZ		 9930 DP(NETIF_MSG_HW, "Handling parity\n");
9931 while (1) {
9932 switch (bp->recovery_state) {
9933 case BNX2X_RECOVERY_INIT:
9934 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9935 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9936 WARN_ON(!is_parity);
c9ee9206 9937
72fd0718 9938 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9939 if (bnx2x_trylock_leader_lock(bp)) {
9940 bnx2x_set_reset_in_progress(bp);
9941 /*
9942 * Check if there is a global attention and if
9943 * there was a global attention, set the global
9944 * reset bit.
9945 */
9946
9947 if (global)
9948 bnx2x_set_reset_global(bp);
9949
72fd0718 9950 bp->is_leader = 1;
c9ee9206 9951 }
72fd0718
VZ		 9952
9953 /* Stop the driver */
9954 /* If interface has been removed - break */
5d07d868 9955 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 9956 return;
9957
9958 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 9959
c9ee9206
VZ		 9960 /* Ensure "is_leader", MCP command sequence and
9961 * "recovery_state" update values are seen on other
9962 * CPUs.
72fd0718 9963 */
c9ee9206 9964 smp_mb();
72fd0718
VZ		 9965 break;
9966
9967 case BNX2X_RECOVERY_WAIT:
9968 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9969 if (bp->is_leader) {
c9ee9206 9970 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 9971 bool other_load_status =
9972 bnx2x_get_load_status(bp, other_engine);
9973 bool load_status =
9974 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 9975 global = bnx2x_reset_is_global(bp);
9976
9977 /*
9978 * In case of a parity in a global block, let
9979 * the first leader that performs a
9980 * leader_reset() reset the global blocks in
9981 * order to clear global attentions. Otherwise
16a5fd92 9982 * the gates will remain closed for that
c9ee9206
VZ		 9983 * engine.
9984 */
889b9af3
AE		 9985 if (load_status ||
9986 (global && other_load_status)) {
72fd0718
VZ		 9987 /* Wait until all other functions get
9988 * down.
9989 */
7be08a72 9990 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9991 HZ/10);
9992 return;
9993 } else {
9994 /* If all other functions got down -
9995 * try to bring the chip back to
9996 * normal. In any case it's an exit
9997 * point for a leader.
9998 */
c9ee9206
VZ		 9999 if (bnx2x_leader_reset(bp)) {
10000 bnx2x_recovery_failed(bp);
72fd0718
VZ		 10001 return;
10002 }
10003
c9ee9206
VZ		 10004 /* If we are here, means that the
10005 * leader has succeeded and doesn't
10006 * want to be a leader any more. Try
10007 * to continue as a none-leader.
10008 */
10009 break;
72fd0718
VZ		 10010 }
10011 } else { /* non-leader */
c9ee9206 10012 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 10013 /* Try to get a LEADER_LOCK HW lock as
10014 * long as a former leader may have
10015 * been unloaded by the user or
10016 * released a leadership by another
10017 * reason.
10018 */
c9ee9206 10019 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 10020 /* I'm a leader now! Restart a
10021 * switch case.
10022 */
10023 bp->is_leader = 1;
10024 break;
10025 }
10026
7be08a72 10027 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 10028 HZ/10);
10029 return;
10030
c9ee9206
VZ		 10031 } else {
10032 /*
10033 * If there was a global attention, wait
10034 * for it to be cleared.
10035 */
10036 if (bnx2x_reset_is_global(bp)) {
10037 schedule_delayed_work(
7be08a72
AE		 10038 &bp->sp_rtnl_task,
10039 HZ/10);
c9ee9206
VZ		 10040 return;
10041 }
10042
7a752993
AE		 10043 error_recovered =
10044 bp->eth_stats.recoverable_error;
10045 error_unrecovered =
10046 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 10047 bp->recovery_state =
10048 BNX2X_RECOVERY_NIC_LOADING;
10049 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 10050 error_unrecovered++;
95c6c616 10051 netdev_err(bp->dev,
51c1a580 10052 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 10053 /* Disconnect this device */
10054 netif_device_detach(bp->dev);
10055 /* Shut down the power */
10056 bnx2x_set_power_state(
10057 bp, PCI_D3hot);
10058 smp_mb();
10059 } else {
c9ee9206
VZ		 10060 bp->recovery_state =
10061 BNX2X_RECOVERY_DONE;
7a752993 10062 error_recovered++;
c9ee9206
VZ		 10063 smp_mb();
10064 }
7a752993
AE		 10065 bp->eth_stats.recoverable_error =
10066 error_recovered;
10067 bp->eth_stats.unrecoverable_error =
10068 error_unrecovered;
c9ee9206 10069
72fd0718
VZ		 10070 return;
10071 }
10072 }
10073 default:
10074 return;
10075 }
10076 }
10077}
10078
4fee7dab 10079#if defined(CONFIG_BNX2X_VXLAN) || IS_ENABLED(CONFIG_BNX2X_GENEVE)
883ce97d 10080static int bnx2x_udp_port_update(struct bnx2x *bp)
f34fa14c
RB		 10081{
10082 struct bnx2x_func_switch_update_params *switch_update_params;
10083 struct bnx2x_func_state_params func_params = {NULL};
883ce97d
YM		 10084 struct bnx2x_udp_tunnel *udp_tunnel;
10085 u16 vxlan_port = 0, geneve_port = 0;
f34fa14c
RB		 10086 int rc;
10087
10088 switch_update_params = &func_params.params.switch_update;
10089
10090 /* Prepare parameters for function state transitions */
10091 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10092 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10093
10094 func_params.f_obj = &bp->func_obj;
10095 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10096
10097 /* Function parameters */
10098 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10099 &switch_update_params->changes);
883ce97d
YM		 10100
10101 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) {
10102 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE];
10103 geneve_port = udp_tunnel->dst_port;
10104 switch_update_params->geneve_dst_port = geneve_port;
10105 }
10106
10107 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) {
10108 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN];
10109 vxlan_port = udp_tunnel->dst_port;
10110 switch_update_params->vxlan_dst_port = vxlan_port;
10111 }
10112
10113 /* Re-enable inner-rss for the offloaded UDP tunnels */
10114 __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
10115 &switch_update_params->changes);
10116
f34fa14c
RB		 10117 rc = bnx2x_func_state_change(bp, &func_params);
10118 if (rc)
883ce97d
YM		 10119 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n",
10120 vxlan_port, geneve_port, rc);
10121 else
10122 DP(BNX2X_MSG_SP,
10123 "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n",
10124 vxlan_port, geneve_port);
10125
f34fa14c
RB		 10126 return rc;
10127}
10128
883ce97d
YM		 10129static void __bnx2x_add_udp_port(struct bnx2x *bp, u16 port,
10130 enum bnx2x_udp_port_type type)
f34fa14c 10131{
883ce97d
YM		 10132 struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10133
10134 if (!netif_running(bp->dev) || !IS_PF(bp))
10135 return;
10136
10137 if (udp_port->count && udp_port->dst_port == port) {
10138 udp_port->count++;
f34fa14c 10139 return;
883ce97d 10140 }
f34fa14c 10141
883ce97d
YM		 10142 if (udp_port->count) {
10143 DP(BNX2X_MSG_SP,
10144 "UDP tunnel [%d] - destination port limit reached\n",
10145 type);
ac7eccd4
JB		 10146 return;
10147 }
10148
883ce97d
YM		 10149 udp_port->dst_port = port;
10150 udp_port->count = 1;
10151 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10152}
10153
10154static void __bnx2x_del_udp_port(struct bnx2x *bp, u16 port,
10155 enum bnx2x_udp_port_type type)
10156{
10157 struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10158
10159 if (!IS_PF(bp))
10160 return;
10161
10162 if (!udp_port->count || udp_port->dst_port != port) {
10163 DP(BNX2X_MSG_SP, "Invalid UDP tunnel [%d] port\n",
10164 type);
f34fa14c
RB		 10165 return;
10166 }
10167
883ce97d
YM		 10168 /* Remove reference, and make certain it's no longer in use */
10169 udp_port->count--;
10170 if (udp_port->count)
10171 return;
10172 udp_port->dst_port = 0;
10173
10174 if (netif_running(bp->dev))
10175 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10176 else
10177 DP(BNX2X_MSG_SP, "Deleted UDP tunnel [%d] port %d\n",
10178 type, port);
f34fa14c 10179}
883ce97d 10180#endif
f34fa14c 10181
883ce97d 10182#ifdef CONFIG_BNX2X_VXLAN
f34fa14c
RB		 10183static void bnx2x_add_vxlan_port(struct net_device *netdev,
10184 sa_family_t sa_family, __be16 port)
10185{
10186 struct bnx2x *bp = netdev_priv(netdev);
10187 u16 t_port = ntohs(port);
10188
883ce97d 10189 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
f34fa14c
RB		 10190}
10191
883ce97d
YM		 10192static void bnx2x_del_vxlan_port(struct net_device *netdev,
10193 sa_family_t sa_family, __be16 port)
f34fa14c 10194{
883ce97d
YM		 10195 struct bnx2x *bp = netdev_priv(netdev);
10196 u16 t_port = ntohs(port);
f34fa14c 10197
883ce97d
YM		 10198 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10199}
10200#endif
10201
4fee7dab 10202#if IS_ENABLED(CONFIG_BNX2X_GENEVE)
883ce97d
YM		 10203static void bnx2x_add_geneve_port(struct net_device *netdev,
10204 sa_family_t sa_family, __be16 port)
10205{
10206 struct bnx2x *bp = netdev_priv(netdev);
10207 u16 t_port = ntohs(port);
10208
10209 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
f34fa14c
RB		 10210}
10211
883ce97d
YM		 10212static void bnx2x_del_geneve_port(struct net_device *netdev,
10213 sa_family_t sa_family, __be16 port)
f34fa14c
RB		 10214{
10215 struct bnx2x *bp = netdev_priv(netdev);
10216 u16 t_port = ntohs(port);
10217
883ce97d 10218 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
f34fa14c
RB		 10219}
10220#endif
10221
56ad3152
MS		 10222static int bnx2x_close(struct net_device *dev);
10223
72fd0718
VZ		 10224/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10225 * scheduled on a general queue in order to prevent a dead lock.
10226 */
7be08a72 10227static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 10228{
7be08a72 10229 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 10230
10231 rtnl_lock();
10232
8395be5e
AE		 10233 if (!netif_running(bp->dev)) {
10234 rtnl_unlock();
10235 return;
10236 }
7be08a72 10237
6bf07b8e 10238 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
7be08a72 10239#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e
YM		 10240 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10241 "you will need to reboot when done\n");
10242 goto sp_rtnl_not_reset;
7be08a72 10243#endif
7be08a72 10244 /*
b1fb8740
VZ		 10245 * Clear all pending SP commands as we are going to reset the
10246 * function anyway.
7be08a72 10247 */
b1fb8740
VZ		 10248 bp->sp_rtnl_state = 0;
10249 smp_mb();
10250
72fd0718 10251 bnx2x_parity_recover(bp);
b1fb8740 10252
8395be5e
AE		 10253 rtnl_unlock();
10254 return;
b1fb8740
VZ		 10255 }
10256
10257 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
6bf07b8e
YM		 10258#ifdef BNX2X_STOP_ON_ERROR
10259 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10260 "you will need to reboot when done\n");
10261 goto sp_rtnl_not_reset;
10262#endif
10263
b1fb8740
VZ		 10264 /*
10265 * Clear all pending SP commands as we are going to reset the
10266 * function anyway.
10267 */
10268 bp->sp_rtnl_state = 0;
10269 smp_mb();
10270
5d07d868 10271 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
72fd0718 10272 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740 10273
8395be5e
AE		 10274 rtnl_unlock();
10275 return;
72fd0718 10276 }
b1fb8740
VZ		 10277#ifdef BNX2X_STOP_ON_ERROR
10278sp_rtnl_not_reset:
10279#endif
10280 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10281 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 10282 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10283 bnx2x_after_function_update(bp);
8304859a
AE		 10284 /*
10285 * in case of fan failure we need to reset id if the "stop on error"
10286 * debug flag is set, since we trying to prevent permanent overheating
10287 * damage
10288 */
10289 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 10290 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 10291 netif_device_detach(bp->dev);
10292 bnx2x_close(bp->dev);
8395be5e
AE		 10293 rtnl_unlock();
10294 return;
8304859a
AE		 10295 }
10296
381ac16b
AE		 10297 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10298 DP(BNX2X_MSG_SP,
10299 "sending set mcast vf pf channel message from rtnl sp-task\n");
10300 bnx2x_vfpf_set_mcast(bp->dev);
10301 }
78c3bcc5
AE		 10302 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10303 &bp->sp_rtnl_state)){
10304 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10305 bnx2x_tx_disable(bp);
10306 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10307 }
10308 }
381ac16b 10309
8b09be5f
YM		 10310 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10311 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10312 bnx2x_set_rx_mode_inner(bp);
381ac16b
AE		 10313 }
10314
3ec9f9ca
AE		 10315 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10316 &bp->sp_rtnl_state))
10317 bnx2x_pf_set_vfs_vlan(bp);
10318
6ffa39f2 10319 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
07b4eb3b 10320 bnx2x_dcbx_stop_hw_tx(bp);
07b4eb3b 10321 bnx2x_dcbx_resume_hw_tx(bp);
6ffa39f2 10322 }
07b4eb3b 10323
42f8277f
YM		 10324 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10325 &bp->sp_rtnl_state))
10326 bnx2x_update_mng_version(bp);
10327
4fee7dab 10328#if defined(CONFIG_BNX2X_VXLAN) || IS_ENABLED(CONFIG_BNX2X_GENEVE)
883ce97d 10329 if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT,
f34fa14c 10330 &bp->sp_rtnl_state)) {
883ce97d
YM		 10331 if (bnx2x_udp_port_update(bp)) {
10332 /* On error, forget configuration */
10333 memset(bp->udp_tunnel_ports, 0,
10334 sizeof(struct bnx2x_udp_tunnel) *
10335 BNX2X_UDP_PORT_MAX);
10336 } else {
10337 /* Since we don't store additional port information,
10338 * if no port is configured for any feature ask for
10339 * information about currently configured ports.
10340 */
10341#ifdef CONFIG_BNX2X_VXLAN
10342 if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count)
10343 vxlan_get_rx_port(bp->dev);
10344#endif
4fee7dab 10345#if IS_ENABLED(CONFIG_BNX2X_GENEVE)
883ce97d
YM		 10346 if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count)
10347 geneve_get_rx_port(bp->dev);
10348#endif
f34fa14c
RB		 10349 }
10350 }
10351#endif
10352
8395be5e
AE		 10353 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10354 * can be called from other contexts as well)
10355 */
34f80b04 10356 rtnl_unlock();
8395be5e 10357
6411280a 10358 /* enable SR-IOV if applicable */
8395be5e 10359 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
3c76feff
AE		 10360 &bp->sp_rtnl_state)) {
10361 bnx2x_disable_sriov(bp);
6411280a 10362 bnx2x_enable_sriov(bp);
3c76feff 10363 }
34f80b04
EG		 10364}
10365
3deb8167
YR		 10366static void bnx2x_period_task(struct work_struct *work)
10367{
10368 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10369
10370 if (!netif_running(bp->dev))
10371 goto period_task_exit;
10372
10373 if (CHIP_REV_IS_SLOW(bp)) {
10374 BNX2X_ERR("period task called on emulation, ignoring\n");
10375 goto period_task_exit;
10376 }
10377
10378 bnx2x_acquire_phy_lock(bp);
10379 /*
10380 * The barrier is needed to ensure the ordering between the writing to
10381 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10382 * the reading here.
10383 */
10384 smp_mb();
10385 if (bp->port.pmf) {
10386 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10387
10388 /* Re-queue task in 1 sec */
10389 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10390 }
10391
10392 bnx2x_release_phy_lock(bp);
10393period_task_exit:
10394 return;
10395}
10396
a2fbb9ea
ET		 10397/*
10398 * Init service functions
10399 */
10400
a8f47eb7 10401static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 10402{
10403 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10404 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10405 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 10406}
10407
3d6b7253
YM		 10408static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10409 u8 port, u32 reset_reg,
10410 struct bnx2x_mac_vals *vals)
10411{
10412 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10413 u32 base_addr;
10414
10415 if (!(mask & reset_reg))
10416 return false;
10417
10418 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10419 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10420 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10421 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10422 REG_WR(bp, vals->umac_addr[port], 0);
10423
10424 return true;
10425}
10426
1ef1d45a
BW		 10427static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10428 struct bnx2x_mac_vals *vals)
34f80b04 10429{
452427b0
YM		 10430 u32 val, base_addr, offset, mask, reset_reg;
10431 bool mac_stopped = false;
10432 u8 port = BP_PORT(bp);
34f80b04 10433
1ef1d45a 10434 /* reset addresses as they also mark which values were changed */
3d6b7253 10435 memset(vals, 0, sizeof(*vals));
1ef1d45a 10436
452427b0 10437 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 10438
452427b0
YM		 10439 if (!CHIP_IS_E3(bp)) {
10440 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10441 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10442 if ((mask & reset_reg) && val) {
10443 u32 wb_data[2];
10444 BNX2X_DEV_INFO("Disable bmac Rx\n");
10445 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10446 : NIG_REG_INGRESS_BMAC0_MEM;
10447 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10448 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 10449
452427b0
YM		 10450 /*
10451 * use rd/wr since we cannot use dmae. This is safe
10452 * since MCP won't access the bus due to the request
10453 * to unload, and no function on the path can be
10454 * loaded at this time.
10455 */
10456 wb_data[0] = REG_RD(bp, base_addr + offset);
10457 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
1ef1d45a
BW		 10458 vals->bmac_addr = base_addr + offset;
10459 vals->bmac_val[0] = wb_data[0];
10460 vals->bmac_val[1] = wb_data[1];
452427b0 10461 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1ef1d45a
BW		 10462 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10463 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
452427b0
YM		 10464 }
10465 BNX2X_DEV_INFO("Disable emac Rx\n");
1ef1d45a
BW		 10466 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10467 vals->emac_val = REG_RD(bp, vals->emac_addr);
10468 REG_WR(bp, vals->emac_addr, 0);
452427b0
YM		 10469 mac_stopped = true;
10470 } else {
10471 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10472 BNX2X_DEV_INFO("Disable xmac Rx\n");
10473 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10474 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10475 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10476 val & ~(1 << 1));
10477 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10478 val | (1 << 1));
1ef1d45a
BW		 10479 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10480 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10481 REG_WR(bp, vals->xmac_addr, 0);
452427b0
YM		 10482 mac_stopped = true;
10483 }
3d6b7253
YM		 10484
10485 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10486 reset_reg, vals);
10487 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10488 reset_reg, vals);
452427b0
YM		 10489 }
10490
10491 if (mac_stopped)
10492 msleep(20);
452427b0
YM		 10493}
10494
10495#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
7c3afd85
YM		 10496#define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10497 0x1848 + ((f) << 4))
452427b0
YM		 10498#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10499#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10500#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10501
91ebb929
YM		 10502#define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10503#define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10504#define BCM_5710_UNDI_FW_MF_VERS (0x05)
b17b0ca1
YM		 10505
10506static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10507{
10508 /* UNDI marks its presence in DORQ -
10509 * it initializes CID offset for normal bell to 0x7
10510 */
10511 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10512 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10513 return false;
10514
10515 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10516 BNX2X_DEV_INFO("UNDI previously loaded\n");
10517 return true;
10518 }
10519
10520 return false;
10521}
10522
7c3afd85 10523static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
452427b0
YM		 10524{
10525 u16 rcq, bd;
7c3afd85 10526 u32 addr, tmp_reg;
452427b0 10527
7c3afd85
YM		 10528 if (BP_FUNC(bp) < 2)
10529 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10530 else
10531 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10532
10533 tmp_reg = REG_RD(bp, addr);
452427b0
YM		 10534 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10535 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10536
10537 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
7c3afd85 10538 REG_WR(bp, addr, tmp_reg);
452427b0 10539
7c3afd85
YM		 10540 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10541 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
452427b0
YM		 10542}
10543
0329aba1 10544static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 10545{
5d07d868
YM		 10546 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10547 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 10548 if (!rc) {
10549 BNX2X_ERR("MCP response failure, aborting\n");
10550 return -EBUSY;
10551 }
10552
10553 return 0;
10554}
10555
c63da990
BW		 10556static struct bnx2x_prev_path_list *
10557 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10558{
10559 struct bnx2x_prev_path_list *tmp_list;
10560
10561 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10562 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10563 bp->pdev->bus->number == tmp_list->bus &&
10564 BP_PATH(bp) == tmp_list->path)
10565 return tmp_list;
10566
10567 return NULL;
10568}
10569
7fa6f340
YM		 10570static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10571{
10572 struct bnx2x_prev_path_list *tmp_list;
10573 int rc;
10574
10575 rc = down_interruptible(&bnx2x_prev_sem);
10576 if (rc) {
10577 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10578 return rc;
10579 }
10580
10581 tmp_list = bnx2x_prev_path_get_entry(bp);
10582 if (tmp_list) {
10583 tmp_list->aer = 1;
10584 rc = 0;
10585 } else {
10586 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10587 BP_PATH(bp));
10588 }
10589
10590 up(&bnx2x_prev_sem);
10591
10592 return rc;
10593}
10594
0329aba1 10595static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 10596{
10597 struct bnx2x_prev_path_list *tmp_list;
b85d717c 10598 bool rc = false;
452427b0
YM		 10599
10600 if (down_trylock(&bnx2x_prev_sem))
10601 return false;
10602
7fa6f340
YM		 10603 tmp_list = bnx2x_prev_path_get_entry(bp);
10604 if (tmp_list) {
10605 if (tmp_list->aer) {
10606 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10607 BP_PATH(bp));
10608 } else {
452427b0
YM		 10609 rc = true;
10610 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10611 BP_PATH(bp));
452427b0
YM		 10612 }
10613 }
10614
10615 up(&bnx2x_prev_sem);
10616
10617 return rc;
10618}
10619
178135c1
DK		 10620bool bnx2x_port_after_undi(struct bnx2x *bp)
10621{
10622 struct bnx2x_prev_path_list *entry;
10623 bool val;
10624
10625 down(&bnx2x_prev_sem);
10626
10627 entry = bnx2x_prev_path_get_entry(bp);
10628 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10629
10630 up(&bnx2x_prev_sem);
10631
10632 return val;
10633}
10634
c63da990 10635static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 10636{
10637 struct bnx2x_prev_path_list *tmp_list;
10638 int rc;
10639
7fa6f340
YM		 10640 rc = down_interruptible(&bnx2x_prev_sem);
10641 if (rc) {
10642 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10643 return rc;
10644 }
10645
10646 /* Check whether the entry for this path already exists */
10647 tmp_list = bnx2x_prev_path_get_entry(bp);
10648 if (tmp_list) {
10649 if (!tmp_list->aer) {
10650 BNX2X_ERR("Re-Marking the path.\n");
10651 } else {
10652 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10653 BP_PATH(bp));
10654 tmp_list->aer = 0;
10655 }
10656 up(&bnx2x_prev_sem);
10657 return 0;
10658 }
10659 up(&bnx2x_prev_sem);
10660
10661 /* Create an entry for this path and add it */
ea4b3857 10662 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 10663 if (!tmp_list) {
10664 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10665 return -ENOMEM;
10666 }
10667
10668 tmp_list->bus = bp->pdev->bus->number;
10669 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10670 tmp_list->path = BP_PATH(bp);
7fa6f340 10671 tmp_list->aer = 0;
c63da990 10672 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 10673
10674 rc = down_interruptible(&bnx2x_prev_sem);
10675 if (rc) {
10676 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10677 kfree(tmp_list);
10678 } else {
7fa6f340
YM		 10679 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10680 BP_PATH(bp));
452427b0
YM		 10681 list_add(&tmp_list->list, &bnx2x_prev_list);
10682 up(&bnx2x_prev_sem);
10683 }
10684
10685 return rc;
10686}
10687
0329aba1 10688static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 10689{
452427b0
YM		 10690 struct pci_dev *dev = bp->pdev;
10691
8eee694c
YM		 10692 if (CHIP_IS_E1x(bp)) {
10693 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10694 return -EINVAL;
10695 }
10696
10697 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10698 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10699 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10700 bp->common.bc_ver);
10701 return -EINVAL;
10702 }
452427b0 10703
8903b9eb
CL		 10704 if (!pci_wait_for_pending_transaction(dev))
10705 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
452427b0 10706
8eee694c 10707 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 10708 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10709
10710 return 0;
10711}
10712
0329aba1 10713static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 10714{
10715 int rc;
10716
10717 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10718
10719 /* Test if previous unload process was already finished for this path */
10720 if (bnx2x_prev_is_path_marked(bp))
10721 return bnx2x_prev_mcp_done(bp);
10722
04c46736
YM		 10723 BNX2X_DEV_INFO("Path is unmarked\n");
10724
b17b0ca1
YM		 10725 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10726 if (bnx2x_prev_is_after_undi(bp))
10727 goto out;
10728
452427b0
YM		 10729 /* If function has FLR capabilities, and existing FW version matches
10730 * the one required, then FLR will be sufficient to clean any residue
10731 * left by previous driver
10732 */
91ebb929 10733 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
8eee694c
YM		 10734
10735 if (!rc) {
10736 /* fw version is good */
10737 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10738 rc = bnx2x_do_flr(bp);
10739 }
10740
10741 if (!rc) {
10742 /* FLR was performed */
10743 BNX2X_DEV_INFO("FLR successful\n");
10744 return 0;
10745 }
10746
10747 BNX2X_DEV_INFO("Could not FLR\n");
452427b0 10748
b17b0ca1 10749out:
452427b0
YM		 10750 /* Close the MCP request, return failure*/
10751 rc = bnx2x_prev_mcp_done(bp);
10752 if (!rc)
10753 rc = BNX2X_PREV_WAIT_NEEDED;
10754
10755 return rc;
10756}
10757
0329aba1 10758static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 10759{
10760 u32 reset_reg, tmp_reg = 0, rc;
c63da990 10761 bool prev_undi = false;
1ef1d45a
BW		 10762 struct bnx2x_mac_vals mac_vals;
10763
452427b0
YM		 10764 /* It is possible a previous function received 'common' answer,
10765 * but hasn't loaded yet, therefore creating a scenario of
10766 * multiple functions receiving 'common' on the same path.
10767 */
10768 BNX2X_DEV_INFO("Common unload Flow\n");
10769
1ef1d45a
BW		 10770 memset(&mac_vals, 0, sizeof(mac_vals));
10771
452427b0
YM		 10772 if (bnx2x_prev_is_path_marked(bp))
10773 return bnx2x_prev_mcp_done(bp);
10774
10775 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10776
10777 /* Reset should be performed after BRB is emptied */
10778 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10779 u32 timer_count = 1000;
452427b0
YM		 10780
10781 /* Close the MAC Rx to prevent BRB from filling up */
1ef1d45a
BW		 10782 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10783
3d6b7253 10784 /* close LLH filters for both ports towards the BRB */
1ef1d45a 10785 bnx2x_set_rx_filter(&bp->link_params, 0);
3d6b7253 10786 bp->link_params.port ^= 1;
1ef1d45a 10787 bnx2x_set_rx_filter(&bp->link_params, 0);
3d6b7253 10788 bp->link_params.port ^= 1;
452427b0 10789
b17b0ca1
YM		 10790 /* Check if the UNDI driver was previously loaded */
10791 if (bnx2x_prev_is_after_undi(bp)) {
10792 prev_undi = true;
10793 /* clear the UNDI indication */
10794 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10795 /* clear possible idle check errors */
10796 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
452427b0 10797 }
d46f7c4d
DK		 10798 if (!CHIP_IS_E1x(bp))
10799 /* block FW from writing to host */
10800 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10801
452427b0
YM		 10802 /* wait until BRB is empty */
10803 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10804 while (timer_count) {
10805 u32 prev_brb = tmp_reg;
34f80b04 10806
452427b0
YM		 10807 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10808 if (!tmp_reg)
10809 break;
619c5cb6 10810
452427b0 10811 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 10812
452427b0
YM		 10813 /* reset timer as long as BRB actually gets emptied */
10814 if (prev_brb > tmp_reg)
10815 timer_count = 1000;
10816 else
10817 timer_count--;
da5a662a 10818
7c3afd85
YM		 10819 /* If UNDI resides in memory, manually increment it */
10820 if (prev_undi)
10821 bnx2x_prev_unload_undi_inc(bp, 1);
10822
452427b0 10823 udelay(10);
7a06a122 10824 }
452427b0
YM		 10825
10826 if (!timer_count)
10827 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
34f80b04 10828 }
f16da43b 10829
452427b0
YM		 10830 /* No packets are in the pipeline, path is ready for reset */
10831 bnx2x_reset_common(bp);
10832
1ef1d45a
BW		 10833 if (mac_vals.xmac_addr)
10834 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
3d6b7253
YM		 10835 if (mac_vals.umac_addr[0])
10836 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10837 if (mac_vals.umac_addr[1])
10838 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
1ef1d45a
BW		 10839 if (mac_vals.emac_addr)
10840 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10841 if (mac_vals.bmac_addr) {
10842 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10843 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10844 }
10845
c63da990 10846 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 10847 if (rc) {
10848 bnx2x_prev_mcp_done(bp);
10849 return rc;
10850 }
10851
10852 return bnx2x_prev_mcp_done(bp);
10853}
10854
0329aba1 10855static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 10856{
10857 int time_counter = 10;
10858 u32 rc, fw, hw_lock_reg, hw_lock_val;
10859 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10860
24f06716
AE		 10861 /* clear hw from errors which may have resulted from an interrupted
10862 * dmae transaction.
10863 */
da254fbc 10864 bnx2x_clean_pglue_errors(bp);
24f06716
AE		 10865
10866 /* Release previously held locks */
452427b0
YM		 10867 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10868 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10869 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10870
3cdeec22 10871 hw_lock_val = REG_RD(bp, hw_lock_reg);
452427b0
YM		 10872 if (hw_lock_val) {
10873 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10874 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10875 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10876 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10877 }
10878
10879 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10880 REG_WR(bp, hw_lock_reg, 0xffffffff);
10881 } else
10882 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10883
10884 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10885 BNX2X_DEV_INFO("Release previously held alr\n");
3cdeec22 10886 bnx2x_release_alr(bp);
452427b0
YM		 10887 }
10888
452427b0 10889 do {
7fa6f340 10890 int aer = 0;
452427b0
YM		 10891 /* Lock MCP using an unload request */
10892 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10893 if (!fw) {
10894 BNX2X_ERR("MCP response failure, aborting\n");
10895 rc = -EBUSY;
10896 break;
10897 }
10898
7fa6f340
YM		 10899 rc = down_interruptible(&bnx2x_prev_sem);
10900 if (rc) {
10901 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10902 rc);
10903 } else {
10904 /* If Path is marked by EEH, ignore unload status */
10905 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10906 bnx2x_prev_path_get_entry(bp)->aer);
60cde81f 10907 up(&bnx2x_prev_sem);
7fa6f340 10908 }
7fa6f340
YM		 10909
10910 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
452427b0
YM		 10911 rc = bnx2x_prev_unload_common(bp);
10912 break;
10913 }
10914
16a5fd92 10915 /* non-common reply from MCP might require looping */
452427b0
YM		 10916 rc = bnx2x_prev_unload_uncommon(bp);
10917 if (rc != BNX2X_PREV_WAIT_NEEDED)
10918 break;
10919
10920 msleep(20);
10921 } while (--time_counter);
10922
10923 if (!time_counter || rc) {
91ebb929
YM		 10924 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10925 rc = -EPROBE_DEFER;
452427b0
YM		 10926 }
10927
c63da990 10928 /* Mark function if its port was used to boot from SAN */
178135c1 10929 if (bnx2x_port_after_undi(bp))
c63da990
BW		 10930 bp->link_params.feature_config_flags |=
10931 FEATURE_CONFIG_BOOT_FROM_SAN;
10932
452427b0
YM		 10933 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10934
10935 return rc;
34f80b04
EG		 10936}
10937
0329aba1 10938static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 10939{
1d187b34 10940 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 10941 u16 pmc;
34f80b04
EG		 10942
10943 /* Get the chip revision id and number. */
10944 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10945 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10946 id = ((val & 0xffff) << 16);
10947 val = REG_RD(bp, MISC_REG_CHIP_REV);
10948 id |= ((val & 0xf) << 12);
f22fdf25
YM		 10949
10950 /* Metal is read from PCI regs, but we can't access >=0x400 from
10951 * the configuration space (so we need to reg_rd)
10952 */
10953 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10954 id |= (((val >> 24) & 0xf) << 4);
5a40e08e 10955 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 10956 id |= (val & 0xf);
10957 bp->common.chip_id = id;
523224a3 10958
7e8e02df
BW		 10959 /* force 57811 according to MISC register */
10960 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10961 if (CHIP_IS_57810(bp))
10962 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10963 (bp->common.chip_id & 0x0000FFFF);
10964 else if (CHIP_IS_57810_MF(bp))
10965 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10966 (bp->common.chip_id & 0x0000FFFF);
10967 bp->common.chip_id |= 0x1;
10968 }
10969
523224a3
DK		 10970 /* Set doorbell size */
10971 bp->db_size = (1 << BNX2X_DB_SHIFT);
10972
619c5cb6 10973 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 10974 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10975 if ((val & 1) == 0)
10976 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10977 else
10978 val = (val >> 1) & 1;
10979 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10980 "2_PORT_MODE");
10981 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10982 CHIP_2_PORT_MODE;
10983
10984 if (CHIP_MODE_IS_4_PORT(bp))
10985 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10986 else
10987 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10988 } else {
10989 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10990 bp->pfid = bp->pf_num; /* 0..7 */
10991 }
10992
51c1a580
MS		 10993 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10994
f2e0899f
DK		 10995 bp->link_params.chip_id = bp->common.chip_id;
10996 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 10997
1c06328c
EG		 10998 val = (REG_RD(bp, 0x2874) & 0x55);
10999 if ((bp->common.chip_id & 0x1) ||
11000 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
11001 bp->flags |= ONE_PORT_FLAG;
11002 BNX2X_DEV_INFO("single port device\n");
11003 }
11004
34f80b04 11005 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 11006 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 11007 (val & MCPR_NVM_CFG4_FLASH_SIZE));
11008 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
11009 bp->common.flash_size, bp->common.flash_size);
11010
1b6e2ceb
DK		 11011 bnx2x_init_shmem(bp);
11012
f2e0899f
DK		 11013 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
11014 MISC_REG_GENERIC_CR_1 :
11015 MISC_REG_GENERIC_CR_0));
1b6e2ceb 11016
34f80b04 11017 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 11018 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 11019 if (SHMEM2_RD(bp, size) >
11020 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
11021 bp->link_params.lfa_base =
11022 REG_RD(bp, bp->common.shmem2_base +
11023 (u32)offsetof(struct shmem2_region,
11024 lfa_host_addr[BP_PORT(bp)]));
11025 else
11026 bp->link_params.lfa_base = 0;
2691d51d
EG		 11027 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
11028 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 11029
f2e0899f 11030 if (!bp->common.shmem_base) {
34f80b04
EG		 11031 BNX2X_DEV_INFO("MCP not active\n");
11032 bp->flags |= NO_MCP_FLAG;
11033 return;
11034 }
11035
34f80b04 11036 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 11037 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 11038
11039 bp->link_params.hw_led_mode = ((bp->common.hw_config &
11040 SHARED_HW_CFG_LED_MODE_MASK) >>
11041 SHARED_HW_CFG_LED_MODE_SHIFT);
11042
c2c8b03e
EG		 11043 bp->link_params.feature_config_flags = 0;
11044 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
11045 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
11046 bp->link_params.feature_config_flags |=
11047 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11048 else
11049 bp->link_params.feature_config_flags &=
11050 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11051
34f80b04
EG		 11052 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
11053 bp->common.bc_ver = val;
11054 BNX2X_DEV_INFO("bc_ver %X\n", val);
11055 if (val < BNX2X_BC_VER) {
11056 /* for now only warn
11057 * later we might need to enforce this */
51c1a580
MS		 11058 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11059 BNX2X_BC_VER, val);
34f80b04 11060 }
4d295db0 11061 bp->link_params.feature_config_flags |=
a22f0788 11062 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 11063 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
11064
a22f0788
YR		 11065 bp->link_params.feature_config_flags |=
11066 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11067 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 11068 bp->link_params.feature_config_flags |=
11069 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11070 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 11071 bp->link_params.feature_config_flags |=
11072 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11073 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 11074
11075 bp->link_params.feature_config_flags |=
11076 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11077 FEATURE_CONFIG_MT_SUPPORT : 0;
11078
0e898dd7
BW		 11079 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11080 BC_SUPPORTS_PFC_STATS : 0;
85242eea 11081
2e499d3c
BW		 11082 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11083 BC_SUPPORTS_FCOE_FEATURES : 0;
11084
9876879f
BW		 11085 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11086 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
a6d3a5ba
BW		 11087
11088 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11089 BC_SUPPORTS_RMMOD_CMD : 0;
11090
1d187b34
BW		 11091 boot_mode = SHMEM_RD(bp,
11092 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11093 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11094 switch (boot_mode) {
11095 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11096 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11097 break;
11098 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11099 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11100 break;
11101 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11102 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11103 break;
11104 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11105 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11106 break;
11107 }
11108
29ed74c3 11109 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
f9a3ebbe
DK		 11110 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11111
72ce58c3 11112 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 11113 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 11114
11115 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11116 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11117 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11118 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11119
cdaa7cb8
VZ		 11120 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11121 val, val2, val3, val4);
34f80b04
EG		 11122}
11123
f2e0899f
DK		 11124#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11125#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11126
0329aba1 11127static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 11128{
11129 int pfid = BP_FUNC(bp);
f2e0899f
DK		 11130 int igu_sb_id;
11131 u32 val;
6383c0b3 11132 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 11133
11134 bp->igu_base_sb = 0xff;
f2e0899f 11135 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 11136 int vn = BP_VN(bp);
6383c0b3 11137 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 11138 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11139 FP_SB_MAX_E1x;
11140
11141 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
11142 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11143
9b341bb1 11144 return 0;
f2e0899f
DK		 11145 }
11146
11147 /* IGU in normal mode - read CAM */
11148 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11149 igu_sb_id++) {
11150 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11151 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11152 continue;
11153 fid = IGU_FID(val);
11154 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11155 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11156 continue;
11157 if (IGU_VEC(val) == 0)
11158 /* default status block */
11159 bp->igu_dsb_id = igu_sb_id;
11160 else {
11161 if (bp->igu_base_sb == 0xff)
11162 bp->igu_base_sb = igu_sb_id;
6383c0b3 11163 igu_sb_cnt++;
f2e0899f
DK		 11164 }
11165 }
11166 }
619c5cb6 11167
6383c0b3 11168#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 11169 /* Due to new PF resource allocation by MFW T7.4 and above, it's
11170 * optional that number of CAM entries will not be equal to the value
11171 * advertised in PCI.
11172 * Driver should use the minimal value of both as the actual status
11173 * block count
619c5cb6 11174 */
185d4c8b 11175 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 11176#endif
619c5cb6 11177
9b341bb1 11178 if (igu_sb_cnt == 0) {
f2e0899f 11179 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 11180 return -EINVAL;
11181 }
11182
11183 return 0;
f2e0899f
DK		 11184}
11185
1dd06ae8 11186static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 11187{
a22f0788
YR		 11188 int cfg_size = 0, idx, port = BP_PORT(bp);
11189
11190 /* Aggregation of supported attributes of all external phys */
11191 bp->port.supported[0] = 0;
11192 bp->port.supported[1] = 0;
b7737c9b
YR		 11193 switch (bp->link_params.num_phys) {
11194 case 1:
a22f0788
YR		 11195 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11196 cfg_size = 1;
11197 break;
b7737c9b 11198 case 2:
a22f0788
YR		 11199 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11200 cfg_size = 1;
11201 break;
11202 case 3:
11203 if (bp->link_params.multi_phy_config &
11204 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11205 bp->port.supported[1] =
11206 bp->link_params.phy[EXT_PHY1].supported;
11207 bp->port.supported[0] =
11208 bp->link_params.phy[EXT_PHY2].supported;
11209 } else {
11210 bp->port.supported[0] =
11211 bp->link_params.phy[EXT_PHY1].supported;
11212 bp->port.supported[1] =
11213 bp->link_params.phy[EXT_PHY2].supported;
11214 }
11215 cfg_size = 2;
11216 break;
b7737c9b 11217 }
a2fbb9ea 11218
a22f0788 11219 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 11220 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 11221 SHMEM_RD(bp,
a22f0788
YR		 11222 dev_info.port_hw_config[port].external_phy_config),
11223 SHMEM_RD(bp,
11224 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 11225 return;
f85582f8 11226 }
a2fbb9ea 11227
619c5cb6
VZ		 11228 if (CHIP_IS_E3(bp))
11229 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11230 else {
11231 switch (switch_cfg) {
11232 case SWITCH_CFG_1G:
11233 bp->port.phy_addr = REG_RD(
11234 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11235 break;
11236 case SWITCH_CFG_10G:
11237 bp->port.phy_addr = REG_RD(
11238 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11239 break;
11240 default:
11241 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11242 bp->port.link_config[0]);
11243 return;
11244 }
a2fbb9ea 11245 }
619c5cb6 11246 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 11247 /* mask what we support according to speed_cap_mask per configuration */
11248 for (idx = 0; idx < cfg_size; idx++) {
11249 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11250 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 11251 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 11252
a22f0788 11253 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11254 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 11255 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 11256
a22f0788 11257 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11258 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 11259 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 11260
a22f0788 11261 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11262 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 11263 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 11264
a22f0788 11265 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11266 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 11267 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 11268 SUPPORTED_1000baseT_Full);
a2fbb9ea 11269
a22f0788 11270 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11271 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 11272 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 11273
a22f0788 11274 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11275 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788 11276 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
b8e0d884
YR		 11277
11278 if (!(bp->link_params.speed_cap_mask[idx] &
11279 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11280 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
a22f0788 11281 }
a2fbb9ea 11282
a22f0788
YR		 11283 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11284 bp->port.supported[1]);
a2fbb9ea
ET		 11285}
11286
0329aba1 11287static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 11288{
a22f0788
YR		 11289 u32 link_config, idx, cfg_size = 0;
11290 bp->port.advertising[0] = 0;
11291 bp->port.advertising[1] = 0;
11292 switch (bp->link_params.num_phys) {
11293 case 1:
11294 case 2:
11295 cfg_size = 1;
11296 break;
11297 case 3:
11298 cfg_size = 2;
11299 break;
11300 }
11301 for (idx = 0; idx < cfg_size; idx++) {
11302 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11303 link_config = bp->port.link_config[idx];
11304 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 11305 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 11306 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11307 bp->link_params.req_line_speed[idx] =
11308 SPEED_AUTO_NEG;
11309 bp->port.advertising[idx] |=
11310 bp->port.supported[idx];
10bd1f24
MY		 11311 if (bp->link_params.phy[EXT_PHY1].type ==
11312 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11313 bp->port.advertising[idx] |=
11314 (SUPPORTED_100baseT_Half |
11315 SUPPORTED_100baseT_Full);
f85582f8
DK		 11316 } else {
11317 /* force 10G, no AN */
a22f0788
YR		 11318 bp->link_params.req_line_speed[idx] =
11319 SPEED_10000;
11320 bp->port.advertising[idx] |=
11321 (ADVERTISED_10000baseT_Full |
f85582f8 11322 ADVERTISED_FIBRE);
a22f0788 11323 continue;
f85582f8
DK		 11324 }
11325 break;
a2fbb9ea 11326
f85582f8 11327 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 11328 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11329 bp->link_params.req_line_speed[idx] =
11330 SPEED_10;
11331 bp->port.advertising[idx] |=
11332 (ADVERTISED_10baseT_Full |
f85582f8
DK		 11333 ADVERTISED_TP);
11334 } else {
51c1a580 11335 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 11336 link_config,
a22f0788 11337 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11338 return;
11339 }
11340 break;
a2fbb9ea 11341
f85582f8 11342 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 11343 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11344 bp->link_params.req_line_speed[idx] =
11345 SPEED_10;
11346 bp->link_params.req_duplex[idx] =
11347 DUPLEX_HALF;
11348 bp->port.advertising[idx] |=
11349 (ADVERTISED_10baseT_Half |
f85582f8
DK		 11350 ADVERTISED_TP);
11351 } else {
51c1a580 11352 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11353 link_config,
11354 bp->link_params.speed_cap_mask[idx]);
11355 return;
11356 }
11357 break;
a2fbb9ea 11358
f85582f8
DK		 11359 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11360 if (bp->port.supported[idx] &
11361 SUPPORTED_100baseT_Full) {
a22f0788
YR		 11362 bp->link_params.req_line_speed[idx] =
11363 SPEED_100;
11364 bp->port.advertising[idx] |=
11365 (ADVERTISED_100baseT_Full |
f85582f8
DK		 11366 ADVERTISED_TP);
11367 } else {
51c1a580 11368 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11369 link_config,
11370 bp->link_params.speed_cap_mask[idx]);
11371 return;
11372 }
11373 break;
a2fbb9ea 11374
f85582f8
DK		 11375 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11376 if (bp->port.supported[idx] &
11377 SUPPORTED_100baseT_Half) {
11378 bp->link_params.req_line_speed[idx] =
11379 SPEED_100;
11380 bp->link_params.req_duplex[idx] =
11381 DUPLEX_HALF;
a22f0788
YR		 11382 bp->port.advertising[idx] |=
11383 (ADVERTISED_100baseT_Half |
f85582f8
DK		 11384 ADVERTISED_TP);
11385 } else {
51c1a580 11386 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11387 link_config,
11388 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11389 return;
11390 }
11391 break;
a2fbb9ea 11392
f85582f8 11393 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 11394 if (bp->port.supported[idx] &
11395 SUPPORTED_1000baseT_Full) {
11396 bp->link_params.req_line_speed[idx] =
11397 SPEED_1000;
11398 bp->port.advertising[idx] |=
11399 (ADVERTISED_1000baseT_Full |
f85582f8 11400 ADVERTISED_TP);
5d67c1c5
YM		 11401 } else if (bp->port.supported[idx] &
11402 SUPPORTED_1000baseKX_Full) {
11403 bp->link_params.req_line_speed[idx] =
11404 SPEED_1000;
11405 bp->port.advertising[idx] |=
11406 ADVERTISED_1000baseKX_Full;
f85582f8 11407 } else {
51c1a580 11408 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11409 link_config,
11410 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11411 return;
11412 }
11413 break;
a2fbb9ea 11414
f85582f8 11415 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 11416 if (bp->port.supported[idx] &
11417 SUPPORTED_2500baseX_Full) {
11418 bp->link_params.req_line_speed[idx] =
11419 SPEED_2500;
11420 bp->port.advertising[idx] |=
11421 (ADVERTISED_2500baseX_Full |
34f80b04 11422 ADVERTISED_TP);
f85582f8 11423 } else {
51c1a580 11424 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11425 link_config,
f85582f8
DK		 11426 bp->link_params.speed_cap_mask[idx]);
11427 return;
11428 }
11429 break;
a2fbb9ea 11430
f85582f8 11431 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 11432 if (bp->port.supported[idx] &
11433 SUPPORTED_10000baseT_Full) {
11434 bp->link_params.req_line_speed[idx] =
11435 SPEED_10000;
11436 bp->port.advertising[idx] |=
11437 (ADVERTISED_10000baseT_Full |
34f80b04 11438 ADVERTISED_FIBRE);
5d67c1c5
YM		 11439 } else if (bp->port.supported[idx] &
11440 SUPPORTED_10000baseKR_Full) {
11441 bp->link_params.req_line_speed[idx] =
11442 SPEED_10000;
11443 bp->port.advertising[idx] |=
11444 (ADVERTISED_10000baseKR_Full |
11445 ADVERTISED_FIBRE);
f85582f8 11446 } else {
51c1a580 11447 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11448 link_config,
f85582f8
DK		 11449 bp->link_params.speed_cap_mask[idx]);
11450 return;
11451 }
11452 break;
3c9ada22
YR		 11453 case PORT_FEATURE_LINK_SPEED_20G:
11454 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 11455
3c9ada22 11456 break;
f85582f8 11457 default:
51c1a580 11458 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 11459 link_config);
f85582f8
DK		 11460 bp->link_params.req_line_speed[idx] =
11461 SPEED_AUTO_NEG;
11462 bp->port.advertising[idx] =
11463 bp->port.supported[idx];
11464 break;
11465 }
a2fbb9ea 11466
a22f0788 11467 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 11468 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 11469 if (bp->link_params.req_flow_ctrl[idx] ==
11470 BNX2X_FLOW_CTRL_AUTO) {
11471 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11472 bp->link_params.req_flow_ctrl[idx] =
11473 BNX2X_FLOW_CTRL_NONE;
11474 else
11475 bnx2x_set_requested_fc(bp);
a22f0788 11476 }
a2fbb9ea 11477
51c1a580 11478 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 11479 bp->link_params.req_line_speed[idx],
11480 bp->link_params.req_duplex[idx],
11481 bp->link_params.req_flow_ctrl[idx],
11482 bp->port.advertising[idx]);
11483 }
a2fbb9ea
ET		 11484}
11485
0329aba1 11486static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda 11487{
86564c3f
YM		 11488 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11489 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11490 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11491 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
e665bfda
MC		 11492}
11493
0329aba1 11494static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 11495{
34f80b04 11496 int port = BP_PORT(bp);
589abe3a 11497 u32 config;
c8c60d88 11498 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 11499
c18487ee 11500 bp->link_params.bp = bp;
34f80b04 11501 bp->link_params.port = port;
c18487ee 11502
c18487ee 11503 bp->link_params.lane_config =
a2fbb9ea 11504 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 11505
a22f0788 11506 bp->link_params.speed_cap_mask[0] =
a2fbb9ea 11507 SHMEM_RD(bp,
b0261926
YR		 11508 dev_info.port_hw_config[port].speed_capability_mask) &
11509 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788
YR		 11510 bp->link_params.speed_cap_mask[1] =
11511 SHMEM_RD(bp,
b0261926
YR		 11512 dev_info.port_hw_config[port].speed_capability_mask2) &
11513 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788 11514 bp->port.link_config[0] =
a2fbb9ea
ET		 11515 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11516
a22f0788
YR		 11517 bp->port.link_config[1] =
11518 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 11519
a22f0788
YR		 11520 bp->link_params.multi_phy_config =
11521 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 11522 /* If the device is capable of WoL, set the default state according
11523 * to the HW
11524 */
4d295db0 11525 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 11526 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11527 (config & PORT_FEATURE_WOL_ENABLED));
11528
4ba7699b
YM		 11529 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11530 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11531 bp->flags |= NO_ISCSI_FLAG;
11532 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11533 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11534 bp->flags |= NO_FCOE_FLAG;
11535
51c1a580 11536 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 11537 bp->link_params.lane_config,
a22f0788
YR		 11538 bp->link_params.speed_cap_mask[0],
11539 bp->port.link_config[0]);
a2fbb9ea 11540
a22f0788 11541 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 11542 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 11543 bnx2x_phy_probe(&bp->link_params);
c18487ee 11544 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 11545
11546 bnx2x_link_settings_requested(bp);
11547
01cd4528
EG		 11548 /*
11549 * If connected directly, work with the internal PHY, otherwise, work
11550 * with the external PHY
11551 */
b7737c9b
YR		 11552 ext_phy_config =
11553 SHMEM_RD(bp,
11554 dev_info.port_hw_config[port].external_phy_config);
11555 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 11556 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 11557 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 11558
11559 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11560 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11561 bp->mdio.prtad =
b7737c9b 11562 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 11563
c8c60d88
YM		 11564 /* Configure link feature according to nvram value */
11565 eee_mode = (((SHMEM_RD(bp, dev_info.
11566 port_feature_config[port].eee_power_mode)) &
11567 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11568 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11569 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11570 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11571 EEE_MODE_ENABLE_LPI |
11572 EEE_MODE_OUTPUT_TIME;
11573 } else {
11574 bp->link_params.eee_mode = 0;
11575 }
0793f83f 11576}
01cd4528 11577
b306f5ed 11578void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 11579{
9e62e912 11580 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 11581 int port = BP_PORT(bp);
2ba45142 11582 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 11583 drv_lic_key[port].max_iscsi_conn);
2ba45142 11584
55c11941
MS		 11585 if (!CNIC_SUPPORT(bp)) {
11586 bp->flags |= no_flags;
11587 return;
11588 }
11589
b306f5ed 11590 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 11591 bp->cnic_eth_dev.max_iscsi_conn =
11592 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11593 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11594
b306f5ed
DK		 11595 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11596 bp->cnic_eth_dev.max_iscsi_conn);
11597
11598 /*
11599 * If maximum allowed number of connections is zero -
11600 * disable the feature.
11601 */
11602 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 11603 bp->flags |= no_flags;
b306f5ed
DK		 11604}
11605
0329aba1 11606static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 11607{
11608 /* Port info */
11609 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11610 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11611 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11612 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11613
11614 /* Node info */
11615 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11616 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11617 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11618 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11619}
86800194
DK		 11620
11621static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11622{
11623 u8 count = 0;
11624
11625 if (IS_MF(bp)) {
11626 u8 fid;
11627
11628 /* iterate over absolute function ids for this path: */
11629 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11630 if (IS_MF_SD(bp)) {
11631 u32 cfg = MF_CFG_RD(bp,
11632 func_mf_config[fid].config);
11633
11634 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11635 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11636 FUNC_MF_CFG_PROTOCOL_FCOE))
11637 count++;
11638 } else {
11639 u32 cfg = MF_CFG_RD(bp,
11640 func_ext_config[fid].
11641 func_cfg);
11642
11643 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11644 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11645 count++;
11646 }
11647 }
11648 } else { /* SF */
11649 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11650
11651 for (port = 0; port < port_cnt; port++) {
11652 u32 lic = SHMEM_RD(bp,
11653 drv_lic_key[port].max_fcoe_conn) ^
11654 FW_ENCODE_32BIT_PATTERN;
11655 if (lic)
11656 count++;
11657 }
11658 }
11659
11660 return count;
11661}
11662
0329aba1 11663static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 11664{
11665 int port = BP_PORT(bp);
11666 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 11667 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11668 drv_lic_key[port].max_fcoe_conn);
86800194 11669 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
b306f5ed 11670
55c11941
MS		 11671 if (!CNIC_SUPPORT(bp)) {
11672 bp->flags |= NO_FCOE_FLAG;
11673 return;
11674 }
11675
b306f5ed 11676 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 11677 bp->cnic_eth_dev.max_fcoe_conn =
11678 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11679 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11680
0eb43b4b
BPG		 11681 /* Calculate the number of maximum allowed FCoE tasks */
11682 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
86800194
DK		 11683
11684 /* check if FCoE resources must be shared between different functions */
11685 if (num_fcoe_func)
11686 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
0eb43b4b 11687
bf61ee14
VZ		 11688 /* Read the WWN: */
11689 if (!IS_MF(bp)) {
11690 /* Port info */
11691 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11692 SHMEM_RD(bp,
2de67439 11693 dev_info.port_hw_config[port].
bf61ee14
VZ		 11694 fcoe_wwn_port_name_upper);
11695 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11696 SHMEM_RD(bp,
2de67439 11697 dev_info.port_hw_config[port].
bf61ee14
VZ		 11698 fcoe_wwn_port_name_lower);
11699
11700 /* Node info */
11701 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11702 SHMEM_RD(bp,
2de67439 11703 dev_info.port_hw_config[port].
bf61ee14
VZ		 11704 fcoe_wwn_node_name_upper);
11705 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11706 SHMEM_RD(bp,
2de67439 11707 dev_info.port_hw_config[port].
bf61ee14
VZ		 11708 fcoe_wwn_node_name_lower);
11709 } else if (!IS_MF_SD(bp)) {
2e98ffc2 11710 /* Read the WWN info only if the FCoE feature is enabled for
bf61ee14
VZ		 11711 * this function.
11712 */
2e98ffc2
DK		 11713 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11714 bnx2x_get_ext_wwn_info(bp, func);
11715 } else {
11716 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912 11717 bnx2x_get_ext_wwn_info(bp, func);
382e513a 11718 }
bf61ee14 11719
b306f5ed 11720 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 11721
bf61ee14
VZ		 11722 /*
11723 * If maximum allowed number of connections is zero -
2ba45142
VZ		 11724 * disable the feature.
11725 */
2ba45142
VZ		 11726 if (!bp->cnic_eth_dev.max_fcoe_conn)
11727 bp->flags |= NO_FCOE_FLAG;
11728}
b306f5ed 11729
0329aba1 11730static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 11731{
11732 /*
11733 * iSCSI may be dynamically disabled but reading
11734 * info here we will decrease memory usage by driver
11735 * if the feature is disabled for good
11736 */
11737 bnx2x_get_iscsi_info(bp);
11738 bnx2x_get_fcoe_info(bp);
11739}
2ba45142 11740
0329aba1 11741static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 11742{
11743 u32 val, val2;
11744 int func = BP_ABS_FUNC(bp);
11745 int port = BP_PORT(bp);
2ba45142
VZ		 11746 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11747 u8 *fip_mac = bp->fip_mac;
0793f83f 11748
55c11941
MS		 11749 if (IS_MF(bp)) {
11750 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 11751 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 11752 * In non SD mode features configuration comes from struct
11753 * func_ext_config.
2ba45142 11754 */
2e98ffc2 11755 if (!IS_MF_SD(bp)) {
0793f83f
DK		 11756 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11757 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11758 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11759 iscsi_mac_addr_upper);
0793f83f 11760 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11761 iscsi_mac_addr_lower);
2ba45142 11762 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 11763 BNX2X_DEV_INFO
11764 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11765 } else {
2ba45142 11766 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 11767 }
2ba45142
VZ		 11768
11769 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11770 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11771 fcoe_mac_addr_upper);
2ba45142 11772 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11773 fcoe_mac_addr_lower);
2ba45142 11774 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 11775 BNX2X_DEV_INFO
11776 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11777 } else {
2ba45142 11778 bp->flags |= NO_FCOE_FLAG;
55c11941 11779 }
a3348722
BW		 11780
11781 bp->mf_ext_config = cfg;
11782
9e62e912 11783 } else { /* SD MODE */
55c11941
MS		 11784 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11785 /* use primary mac as iscsi mac */
11786 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11787
11788 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11789 BNX2X_DEV_INFO
11790 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11791 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11792 /* use primary mac as fip mac */
11793 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11794 BNX2X_DEV_INFO("SD FCoE MODE\n");
11795 BNX2X_DEV_INFO
11796 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 11797 }
0793f83f 11798 }
a3348722 11799
82594f8f
YM		 11800 /* If this is a storage-only interface, use SAN mac as
11801 * primary MAC. Notice that for SD this is already the case,
11802 * as the SAN mac was copied from the primary MAC.
11803 */
11804 if (IS_MF_FCOE_AFEX(bp))
a3348722 11805 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
0793f83f 11806 } else {
0793f83f 11807 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11808 iscsi_mac_upper);
0793f83f 11809 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11810 iscsi_mac_lower);
2ba45142 11811 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 11812
11813 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11814 fcoe_fip_mac_upper);
c03bd39c 11815 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11816 fcoe_fip_mac_lower);
c03bd39c 11817 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 11818 }
11819
55c11941 11820 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 11821 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 11822 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
c7bf7169 11823 eth_zero_addr(iscsi_mac);
426b9241
DK		 11824 }
11825
55c11941 11826 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 11827 if (!is_valid_ether_addr(fip_mac)) {
11828 bp->flags |= NO_FCOE_FLAG;
c7bf7169 11829 eth_zero_addr(bp->fip_mac);
426b9241 11830 }
55c11941
MS		 11831}
11832
0329aba1 11833static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 11834{
11835 u32 val, val2;
11836 int func = BP_ABS_FUNC(bp);
11837 int port = BP_PORT(bp);
11838
11839 /* Zero primary MAC configuration */
c7bf7169 11840 eth_zero_addr(bp->dev->dev_addr);
55c11941
MS		 11841
11842 if (BP_NOMCP(bp)) {
11843 BNX2X_ERROR("warning: random MAC workaround active\n");
11844 eth_hw_addr_random(bp->dev);
11845 } else if (IS_MF(bp)) {
11846 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11847 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11848 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11849 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11850 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11851
11852 if (CNIC_SUPPORT(bp))
11853 bnx2x_get_cnic_mac_hwinfo(bp);
11854 } else {
11855 /* in SF read MACs from port configuration */
11856 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11857 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11858 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11859
11860 if (CNIC_SUPPORT(bp))
11861 bnx2x_get_cnic_mac_hwinfo(bp);
11862 }
11863
3d7d562c
YM		 11864 if (!BP_NOMCP(bp)) {
11865 /* Read physical port identifier from shmem */
11866 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11867 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11868 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11869 bp->flags |= HAS_PHYS_PORT_ID;
11870 }
11871
55c11941 11872 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 11873
2e98ffc2 11874 if (!is_valid_ether_addr(bp->dev->dev_addr))
619c5cb6 11875 dev_err(&bp->pdev->dev,
51c1a580
MS		 11876 "bad Ethernet MAC address configuration: %pM\n"
11877 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 11878 bp->dev->dev_addr);
7964211d 11879}
51c1a580 11880
0329aba1 11881static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 11882{
11883 int tmp;
11884 u32 cfg;
51c1a580 11885
aeeddb8b 11886 if (IS_VF(bp))
4e833c59 11887 return false;
aeeddb8b 11888
7964211d
YM		 11889 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11890 /* Take function: tmp = func */
11891 tmp = BP_ABS_FUNC(bp);
11892 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11893 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11894 } else {
11895 /* Take port: tmp = port */
11896 tmp = BP_PORT(bp);
11897 cfg = SHMEM_RD(bp,
11898 dev_info.port_hw_config[tmp].generic_features);
11899 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11900 }
11901 return cfg;
34f80b04
EG		 11902}
11903
83bad206
YM		 11904static void validate_set_si_mode(struct bnx2x *bp)
11905{
11906 u8 func = BP_ABS_FUNC(bp);
11907 u32 val;
11908
11909 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11910
11911 /* check for legal mac (upper bytes) */
11912 if (val != 0xffff) {
11913 bp->mf_mode = MULTI_FUNCTION_SI;
11914 bp->mf_config[BP_VN(bp)] =
11915 MF_CFG_RD(bp, func_mf_config[func].config);
11916 } else
11917 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11918}
11919
0329aba1 11920static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 11921{
0793f83f 11922 int /*abs*/func = BP_ABS_FUNC(bp);
230d00eb 11923 int vn, mfw_vn;
83bad206 11924 u32 val = 0, val2 = 0;
34f80b04 11925 int rc = 0;
a2fbb9ea 11926
0f587f1b
YM		 11927 /* Validate that chip access is feasible */
11928 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11929 dev_err(&bp->pdev->dev,
11930 "Chip read returns all Fs. Preventing probe from continuing\n");
11931 return -EINVAL;
11932 }
11933
34f80b04 11934 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 11935
6383c0b3
AE		 11936 /*
11937 * initialize IGU parameters
11938 */
f2e0899f
DK		 11939 if (CHIP_IS_E1x(bp)) {
11940 bp->common.int_block = INT_BLOCK_HC;
11941
11942 bp->igu_dsb_id = DEF_SB_IGU_ID;
11943 bp->igu_base_sb = 0;
f2e0899f
DK		 11944 } else {
11945 bp->common.int_block = INT_BLOCK_IGU;
7a06a122 11946
16a5fd92 11947 /* do not allow device reset during IGU info processing */
7a06a122
DK		 11948 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11949
f2e0899f 11950 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 11951
11952 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11953 int tout = 5000;
11954
11955 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11956
11957 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11958 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11959 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11960
11961 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11962 tout--;
0926d499 11963 usleep_range(1000, 2000);
619c5cb6
VZ		 11964 }
11965
11966 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11967 dev_err(&bp->pdev->dev,
11968 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 11969 bnx2x_release_hw_lock(bp,
11970 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 11971 return -EPERM;
11972 }
11973 }
11974
f2e0899f 11975 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 11976 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 11977 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11978 } else
619c5cb6 11979 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 11980
9b341bb1 11981 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 11982 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 11983 if (rc)
11984 return rc;
f2e0899f 11985 }
619c5cb6
VZ		 11986
11987 /*
11988 * set base FW non-default (fast path) status block id, this value is
11989 * used to initialize the fw_sb_id saved on the fp/queue structure to
11990 * determine the id used by the FW.
11991 */
11992 if (CHIP_IS_E1x(bp))
11993 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11994 else /*
11995 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11996 * the same queue are indicated on the same IGU SB). So we prefer
11997 * FW and IGU SBs to be the same value.
11998 */
11999 bp->base_fw_ndsb = bp->igu_base_sb;
12000
12001 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
12002 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
12003 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 12004
12005 /*
12006 * Initialize MF configuration
12007 */
523224a3 12008
fb3bff17
DK		 12009 bp->mf_ov = 0;
12010 bp->mf_mode = 0;
7609647e 12011 bp->mf_sub_mode = 0;
3395a033 12012 vn = BP_VN(bp);
230d00eb 12013 mfw_vn = BP_FW_MB_IDX(bp);
0793f83f 12014
f2e0899f 12015 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 12016 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
12017 bp->common.shmem2_base, SHMEM2_RD(bp, size),
12018 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
12019
f2e0899f
DK		 12020 if (SHMEM2_HAS(bp, mf_cfg_addr))
12021 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
12022 else
12023 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 12024 offsetof(struct shmem_region, func_mb) +
12025 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 12026 /*
12027 * get mf configuration:
16a5fd92 12028 * 1. Existence of MF configuration
0793f83f
DK		 12029 * 2. MAC address must be legal (check only upper bytes)
12030 * for Switch-Independent mode;
12031 * OVLAN must be legal for Switch-Dependent mode
12032 * 3. SF_MODE configures specific MF mode
12033 */
12034 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12035 /* get mf configuration */
12036 val = SHMEM_RD(bp,
12037 dev_info.shared_feature_config.config);
12038 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
12039
12040 switch (val) {
12041 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
83bad206 12042 validate_set_si_mode(bp);
0793f83f 12043 break;
a3348722
BW		 12044 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
12045 if ((!CHIP_IS_E1x(bp)) &&
12046 (MF_CFG_RD(bp, func_mf_config[func].
12047 mac_upper) != 0xffff) &&
12048 (SHMEM2_HAS(bp,
12049 afex_driver_support))) {
12050 bp->mf_mode = MULTI_FUNCTION_AFEX;
12051 bp->mf_config[vn] = MF_CFG_RD(bp,
12052 func_mf_config[func].config);
12053 } else {
12054 BNX2X_DEV_INFO("can not configure afex mode\n");
12055 }
12056 break;
0793f83f
DK		 12057 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
12058 /* get OV configuration */
12059 val = MF_CFG_RD(bp,
12060 func_mf_config[FUNC_0].e1hov_tag);
12061 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
12062
12063 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12064 bp->mf_mode = MULTI_FUNCTION_SD;
12065 bp->mf_config[vn] = MF_CFG_RD(bp,
12066 func_mf_config[func].config);
12067 } else
754a2f52 12068 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f 12069 break;
230d00eb
YM		 12070 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12071 bp->mf_mode = MULTI_FUNCTION_SD;
12072 bp->mf_sub_mode = SUB_MF_MODE_BD;
12073 bp->mf_config[vn] =
12074 MF_CFG_RD(bp,
12075 func_mf_config[func].config);
12076
12077 if (SHMEM2_HAS(bp, mtu_size)) {
12078 int mtu_idx = BP_FW_MB_IDX(bp);
12079 u16 mtu_size;
12080 u32 mtu;
12081
12082 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12083 mtu_size = (u16)mtu;
12084 DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12085 mtu_size, mtu);
12086
12087 /* if valid: update device mtu */
12088 if (((mtu_size + ETH_HLEN) >=
12089 ETH_MIN_PACKET_SIZE) &&
12090 (mtu_size <=
12091 ETH_MAX_JUMBO_PACKET_SIZE))
12092 bp->dev->mtu = mtu_size;
12093 }
12094 break;
7609647e
YM		 12095 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12096 bp->mf_mode = MULTI_FUNCTION_SD;
12097 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12098 bp->mf_config[vn] =
12099 MF_CFG_RD(bp,
12100 func_mf_config[func].config);
12101 break;
3786b942
AE		 12102 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12103 bp->mf_config[vn] = 0;
12104 break;
83bad206
YM		 12105 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12106 val2 = SHMEM_RD(bp,
12107 dev_info.shared_hw_config.config_3);
12108 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12109 switch (val2) {
12110 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12111 validate_set_si_mode(bp);
12112 bp->mf_sub_mode =
12113 SUB_MF_MODE_NPAR1_DOT_5;
12114 break;
12115 default:
12116 /* Unknown configuration */
12117 bp->mf_config[vn] = 0;
12118 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12119 val);
12120 }
12121 break;
0793f83f
DK		 12122 default:
12123 /* Unknown configuration: reset mf_config */
12124 bp->mf_config[vn] = 0;
51c1a580 12125 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 12126 }
12127 }
a2fbb9ea 12128
2691d51d 12129 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 12130 IS_MF(bp) ? "multi" : "single");
2691d51d 12131
0793f83f
DK		 12132 switch (bp->mf_mode) {
12133 case MULTI_FUNCTION_SD:
12134 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12135 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 12136 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 12137 bp->mf_ov = val;
619c5cb6
VZ		 12138 bp->path_has_ovlan = true;
12139
51c1a580
MS		 12140 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12141 func, bp->mf_ov, bp->mf_ov);
230d00eb
YM		 12142 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12143 (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
7609647e 12144 dev_err(&bp->pdev->dev,
230d00eb 12145 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
7609647e
YM		 12146 func);
12147 bp->path_has_ovlan = true;
2691d51d 12148 } else {
619c5cb6 12149 dev_err(&bp->pdev->dev,
51c1a580
MS		 12150 "No valid MF OV for func %d, aborting\n",
12151 func);
619c5cb6 12152 return -EPERM;
34f80b04 12153 }
0793f83f 12154 break;
a3348722
BW		 12155 case MULTI_FUNCTION_AFEX:
12156 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12157 break;
0793f83f 12158 case MULTI_FUNCTION_SI:
51c1a580
MS		 12159 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12160 func);
0793f83f
DK		 12161 break;
12162 default:
12163 if (vn) {
619c5cb6 12164 dev_err(&bp->pdev->dev,
51c1a580
MS		 12165 "VN %d is in a single function mode, aborting\n",
12166 vn);
619c5cb6 12167 return -EPERM;
2691d51d 12168 }
0793f83f 12169 break;
34f80b04 12170 }
0793f83f 12171
619c5cb6
VZ		 12172 /* check if other port on the path needs ovlan:
12173 * Since MF configuration is shared between ports
12174 * Possible mixed modes are only
12175 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12176 */
12177 if (CHIP_MODE_IS_4_PORT(bp) &&
12178 !bp->path_has_ovlan &&
12179 !IS_MF(bp) &&
12180 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12181 u8 other_port = !BP_PORT(bp);
12182 u8 other_func = BP_PATH(bp) + 2*other_port;
12183 val = MF_CFG_RD(bp,
12184 func_mf_config[other_func].e1hov_tag);
12185 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12186 bp->path_has_ovlan = true;
12187 }
34f80b04 12188 }
a2fbb9ea 12189
e848582c
DK		 12190 /* adjust igu_sb_cnt to MF for E1H */
12191 if (CHIP_IS_E1H(bp) && IS_MF(bp))
12192 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
523224a3 12193
619c5cb6
VZ		 12194 /* port info */
12195 bnx2x_get_port_hwinfo(bp);
f2e0899f 12196
0793f83f
DK		 12197 /* Get MAC addresses */
12198 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 12199
2ba45142 12200 bnx2x_get_cnic_info(bp);
2ba45142 12201
34f80b04
EG		 12202 return rc;
12203}
12204
0329aba1 12205static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 12206{
12207 int cnt, i, block_end, rodi;
fcdf95cb 12208 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 12209 char str_id_reg[VENDOR_ID_LEN+1];
12210 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 12211 char *vpd_data;
12212 char *vpd_extended_data = NULL;
34f24c7f
VZ		 12213 u8 len;
12214
fcdf95cb 12215 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 12216 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12217
12218 if (cnt < BNX2X_VPD_LEN)
12219 goto out_not_found;
12220
fcdf95cb
BW		 12221 /* VPD RO tag should be first tag after identifier string, hence
12222 * we should be able to find it in first BNX2X_VPD_LEN chars
12223 */
12224 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 12225 PCI_VPD_LRDT_RO_DATA);
12226 if (i < 0)
12227 goto out_not_found;
12228
34f24c7f 12229 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 12230 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 12231
12232 i += PCI_VPD_LRDT_TAG_SIZE;
12233
fcdf95cb
BW		 12234 if (block_end > BNX2X_VPD_LEN) {
12235 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12236 if (vpd_extended_data == NULL)
12237 goto out_not_found;
12238
12239 /* read rest of vpd image into vpd_extended_data */
12240 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12241 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12242 block_end - BNX2X_VPD_LEN,
12243 vpd_extended_data + BNX2X_VPD_LEN);
12244 if (cnt < (block_end - BNX2X_VPD_LEN))
12245 goto out_not_found;
12246 vpd_data = vpd_extended_data;
12247 } else
12248 vpd_data = vpd_start;
12249
12250 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 12251
12252 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12253 PCI_VPD_RO_KEYWORD_MFR_ID);
12254 if (rodi < 0)
12255 goto out_not_found;
12256
12257 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12258
12259 if (len != VENDOR_ID_LEN)
12260 goto out_not_found;
12261
12262 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12263
12264 /* vendor specific info */
12265 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12266 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12267 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12268 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12269
12270 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12271 PCI_VPD_RO_KEYWORD_VENDOR0);
12272 if (rodi >= 0) {
12273 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12274
12275 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12276
12277 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12278 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12279 bp->fw_ver[len] = ' ';
12280 }
12281 }
fcdf95cb 12282 kfree(vpd_extended_data);
34f24c7f
VZ		 12283 return;
12284 }
12285out_not_found:
fcdf95cb 12286 kfree(vpd_extended_data);
34f24c7f
VZ		 12287 return;
12288}
12289
0329aba1 12290static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 12291{
12292 u32 flags = 0;
12293
12294 if (CHIP_REV_IS_FPGA(bp))
12295 SET_FLAGS(flags, MODE_FPGA);
12296 else if (CHIP_REV_IS_EMUL(bp))
12297 SET_FLAGS(flags, MODE_EMUL);
12298 else
12299 SET_FLAGS(flags, MODE_ASIC);
12300
12301 if (CHIP_MODE_IS_4_PORT(bp))
12302 SET_FLAGS(flags, MODE_PORT4);
12303 else
12304 SET_FLAGS(flags, MODE_PORT2);
12305
12306 if (CHIP_IS_E2(bp))
12307 SET_FLAGS(flags, MODE_E2);
12308 else if (CHIP_IS_E3(bp)) {
12309 SET_FLAGS(flags, MODE_E3);
12310 if (CHIP_REV(bp) == CHIP_REV_Ax)
12311 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 12312 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12313 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 12314 }
12315
12316 if (IS_MF(bp)) {
12317 SET_FLAGS(flags, MODE_MF);
12318 switch (bp->mf_mode) {
12319 case MULTI_FUNCTION_SD:
12320 SET_FLAGS(flags, MODE_MF_SD);
12321 break;
12322 case MULTI_FUNCTION_SI:
12323 SET_FLAGS(flags, MODE_MF_SI);
12324 break;
a3348722
BW		 12325 case MULTI_FUNCTION_AFEX:
12326 SET_FLAGS(flags, MODE_MF_AFEX);
12327 break;
619c5cb6
VZ		 12328 }
12329 } else
12330 SET_FLAGS(flags, MODE_SF);
12331
12332#if defined(__LITTLE_ENDIAN)
12333 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12334#else /*(__BIG_ENDIAN)*/
12335 SET_FLAGS(flags, MODE_BIG_ENDIAN);
12336#endif
12337 INIT_MODE_FLAGS(bp) = flags;
12338}
12339
0329aba1 12340static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 12341{
f2e0899f 12342 int func;
34f80b04
EG		 12343 int rc;
12344
34f80b04 12345 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 12346 mutex_init(&bp->fw_mb_mutex);
42f8277f 12347 mutex_init(&bp->drv_info_mutex);
c6e36d8c 12348 sema_init(&bp->stats_lock, 1);
42f8277f 12349 bp->drv_info_mng_owner = false;
05cc5a39 12350 INIT_LIST_HEAD(&bp->vlan_reg);
55c11941 12351
1cf167f2 12352 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 12353 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 12354 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
370d4a26 12355 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
1ab4434c
AE		 12356 if (IS_PF(bp)) {
12357 rc = bnx2x_get_hwinfo(bp);
12358 if (rc)
12359 return rc;
12360 } else {
e09b74d0 12361 eth_zero_addr(bp->dev->dev_addr);
1ab4434c 12362 }
34f80b04 12363
619c5cb6
VZ		 12364 bnx2x_set_modes_bitmap(bp);
12365
12366 rc = bnx2x_alloc_mem_bp(bp);
12367 if (rc)
12368 return rc;
523224a3 12369
34f24c7f 12370 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 12371
12372 func = BP_FUNC(bp);
12373
34f80b04 12374 /* need to reset chip if undi was active */
1ab4434c 12375 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 12376 /* init fw_seq */
12377 bp->fw_seq =
12378 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12379 DRV_MSG_SEQ_NUMBER_MASK;
12380 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12381
91ebb929
YM		 12382 rc = bnx2x_prev_unload(bp);
12383 if (rc) {
12384 bnx2x_free_mem_bp(bp);
12385 return rc;
12386 }
452427b0
YM		 12387 }
12388
34f80b04 12389 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 12390 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 12391
12392 if (BP_NOMCP(bp) && (func == 0))
51c1a580 12393 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 12394
614c76df 12395 bp->disable_tpa = disable_tpa;
2e98ffc2 12396 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
94d9de3c 12397 /* Reduce memory usage in kdump environment by disabling TPA */
c9931896 12398 bp->disable_tpa |= is_kdump_kernel();
614c76df 12399
7a9b2557 12400 /* Set TPA flags */
614c76df 12401 if (bp->disable_tpa) {
d9b9e860 12402 bp->dev->hw_features &= ~NETIF_F_LRO;
7a9b2557 12403 bp->dev->features &= ~NETIF_F_LRO;
7a9b2557
VZ		 12404 }
12405
a18f5128
EG		 12406 if (CHIP_IS_E1(bp))
12407 bp->dropless_fc = 0;
12408 else
7964211d 12409 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 12410
8d5726c4 12411 bp->mrrs = mrrs;
7a9b2557 12412
2e98ffc2 12413 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 12414 if (IS_VF(bp))
12415 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 12416
7d323bfd 12417 /* make sure that the numbers are in the right granularity */
523224a3
DK		 12418 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12419 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 12420
fc543637 12421 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 12422
12423 init_timer(&bp->timer);
12424 bp->timer.expires = jiffies + bp->current_interval;
12425 bp->timer.data = (unsigned long) bp;
12426 bp->timer.function = bnx2x_timer;
12427
0370cf90
BW		 12428 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12429 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
9c73267d 12430 SHMEM2_HAS(bp, dcbx_en) &&
0370cf90 12431 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
9c73267d
YM		 12432 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) &&
12433 SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) {
0370cf90
BW		 12434 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12435 bnx2x_dcbx_init_params(bp);
12436 } else {
12437 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12438 }
e4901dde 12439
619c5cb6
VZ		 12440 if (CHIP_IS_E1x(bp))
12441 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12442 else
12443 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 12444
6383c0b3 12445 /* multiple tx priority */
1ab4434c
AE		 12446 if (IS_VF(bp))
12447 bp->max_cos = 1;
12448 else if (CHIP_IS_E1x(bp))
6383c0b3 12449 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 12450 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 12451 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 12452 else if (CHIP_IS_E3B0(bp))
6383c0b3 12453 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 12454 else
12455 BNX2X_ERR("unknown chip %x revision %x\n",
12456 CHIP_NUM(bp), CHIP_REV(bp));
12457 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 12458
55c11941
MS		 12459 /* We need at least one default status block for slow-path events,
12460 * second status block for the L2 queue, and a third status block for
16a5fd92 12461 * CNIC if supported.
55c11941 12462 */
60cad4e6
AE		 12463 if (IS_VF(bp))
12464 bp->min_msix_vec_cnt = 1;
12465 else if (CNIC_SUPPORT(bp))
55c11941 12466 bp->min_msix_vec_cnt = 3;
60cad4e6 12467 else /* PF w/o cnic */
55c11941
MS		 12468 bp->min_msix_vec_cnt = 2;
12469 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12470
5bb680d6
MS		 12471 bp->dump_preset_idx = 1;
12472
eeed018c
MK		 12473 if (CHIP_IS_E3B0(bp))
12474 bp->flags |= PTP_SUPPORTED;
12475
34f80b04 12476 return rc;
a2fbb9ea
ET		 12477}
12478
de0c62db
DK		 12479/****************************************************************************
12480* General service functions
12481****************************************************************************/
a2fbb9ea 12482
619c5cb6
VZ		 12483/*
12484 * net_device service functions
12485 */
12486
bb2a0f7a 12487/* called with rtnl_lock */
a2fbb9ea
ET		 12488static int bnx2x_open(struct net_device *dev)
12489{
12490 struct bnx2x *bp = netdev_priv(dev);
8395be5e 12491 int rc;
a2fbb9ea 12492
1355b704
MY		 12493 bp->stats_init = true;
12494
6eccabb3
EG		 12495 netif_carrier_off(dev);
12496
a2fbb9ea
ET		 12497 bnx2x_set_power_state(bp, PCI_D0);
12498
ad5afc89 12499 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 12500 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12501 * want the first function loaded on the current engine to
12502 * complete the recovery.
ad5afc89 12503 * Parity recovery is only relevant for PF driver.
c9ee9206 12504 */
ad5afc89 12505 if (IS_PF(bp)) {
1a6974b2
YM		 12506 int other_engine = BP_PATH(bp) ? 0 : 1;
12507 bool other_load_status, load_status;
12508 bool global = false;
12509
ad5afc89
AE		 12510 other_load_status = bnx2x_get_load_status(bp, other_engine);
12511 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12512 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12513 bnx2x_chk_parity_attn(bp, &global, true)) {
12514 do {
12515 /* If there are attentions and they are in a
12516 * global blocks, set the GLOBAL_RESET bit
12517 * regardless whether it will be this function
12518 * that will complete the recovery or not.
12519 */
12520 if (global)
12521 bnx2x_set_reset_global(bp);
72fd0718 12522
ad5afc89
AE		 12523 /* Only the first function on the current
12524 * engine should try to recover in open. In case
12525 * of attentions in global blocks only the first
12526 * in the chip should try to recover.
12527 */
12528 if ((!load_status &&
12529 (!global || !other_load_status)) &&
12530 bnx2x_trylock_leader_lock(bp) &&
12531 !bnx2x_leader_reset(bp)) {
12532 netdev_info(bp->dev,
12533 "Recovered in open\n");
12534 break;
12535 }
72fd0718 12536
ad5afc89
AE		 12537 /* recovery has failed... */
12538 bnx2x_set_power_state(bp, PCI_D3hot);
12539 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 12540
ad5afc89
AE		 12541 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12542 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 12543
ad5afc89
AE		 12544 return -EAGAIN;
12545 } while (0);
12546 }
12547 }
72fd0718
VZ		 12548
12549 bp->recovery_state = BNX2X_RECOVERY_DONE;
8395be5e
AE		 12550 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12551 if (rc)
12552 return rc;
f34fa14c
RB		 12553
12554#ifdef CONFIG_BNX2X_VXLAN
12555 if (IS_PF(bp))
12556 vxlan_get_rx_port(dev);
12557#endif
4fee7dab 12558#if IS_ENABLED(CONFIG_BNX2X_GENEVE)
883ce97d
YM		 12559 if (IS_PF(bp))
12560 geneve_get_rx_port(dev);
12561#endif
f34fa14c 12562
9a8130bc 12563 return 0;
a2fbb9ea
ET		 12564}
12565
bb2a0f7a 12566/* called with rtnl_lock */
56ad3152 12567static int bnx2x_close(struct net_device *dev)
a2fbb9ea 12568{
a2fbb9ea
ET		 12569 struct bnx2x *bp = netdev_priv(dev);
12570
12571 /* Unload the driver, release IRQs */
5d07d868 12572 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206 12573
a2fbb9ea
ET		 12574 return 0;
12575}
12576
1191cb83
ED		 12577static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12578 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 12579{
619c5cb6
VZ		 12580 int mc_count = netdev_mc_count(bp->dev);
12581 struct bnx2x_mcast_list_elem *mc_mac =
cd2b0389 12582 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
619c5cb6 12583 struct netdev_hw_addr *ha;
6e30dd4e 12584
619c5cb6
VZ		 12585 if (!mc_mac)
12586 return -ENOMEM;
6e30dd4e 12587
619c5cb6 12588 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 12589
619c5cb6
VZ		 12590 netdev_for_each_mc_addr(ha, bp->dev) {
12591 mc_mac->mac = bnx2x_mc_addr(ha);
12592 list_add_tail(&mc_mac->link, &p->mcast_list);
12593 mc_mac++;
6e30dd4e 12594 }
619c5cb6
VZ		 12595
12596 p->mcast_list_len = mc_count;
12597
12598 return 0;
6e30dd4e
VZ		 12599}
12600
1191cb83 12601static void bnx2x_free_mcast_macs_list(
619c5cb6
VZ		 12602 struct bnx2x_mcast_ramrod_params *p)
12603{
12604 struct bnx2x_mcast_list_elem *mc_mac =
12605 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12606 link);
12607
12608 WARN_ON(!mc_mac);
12609 kfree(mc_mac);
12610}
12611
12612/**
12613 * bnx2x_set_uc_list - configure a new unicast MACs list.
12614 *
12615 * @bp: driver handle
6e30dd4e 12616 *
619c5cb6 12617 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 12618 */
1191cb83 12619static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 12620{
619c5cb6 12621 int rc;
6e30dd4e 12622 struct net_device *dev = bp->dev;
6e30dd4e 12623 struct netdev_hw_addr *ha;
15192a8c 12624 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 12625 unsigned long ramrod_flags = 0;
6e30dd4e 12626
619c5cb6
VZ		 12627 /* First schedule a cleanup up of old configuration */
12628 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12629 if (rc < 0) {
12630 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12631 return rc;
12632 }
6e30dd4e
VZ		 12633
12634 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 12635 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12636 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 12637 if (rc == -EEXIST) {
12638 DP(BNX2X_MSG_SP,
12639 "Failed to schedule ADD operations: %d\n", rc);
12640 /* do not treat adding same MAC as error */
12641 rc = 0;
12642
12643 } else if (rc < 0) {
12644
619c5cb6
VZ		 12645 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12646 rc);
12647 return rc;
6e30dd4e
VZ		 12648 }
12649 }
12650
619c5cb6
VZ		 12651 /* Execute the pending commands */
12652 __set_bit(RAMROD_CONT, &ramrod_flags);
12653 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12654 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 12655}
12656
1191cb83 12657static int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 12658{
619c5cb6 12659 struct net_device *dev = bp->dev;
3b603066 12660 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 12661 int rc = 0;
6e30dd4e 12662
619c5cb6 12663 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 12664
619c5cb6
VZ		 12665 /* first, clear all configured multicast MACs */
12666 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12667 if (rc < 0) {
51c1a580 12668 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 12669 return rc;
12670 }
6e30dd4e 12671
619c5cb6
VZ		 12672 /* then, configure a new MACs list */
12673 if (netdev_mc_count(dev)) {
12674 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12675 if (rc) {
51c1a580
MS		 12676 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12677 rc);
619c5cb6
VZ		 12678 return rc;
12679 }
6e30dd4e 12680
619c5cb6
VZ		 12681 /* Now add the new MACs */
12682 rc = bnx2x_config_mcast(bp, &rparam,
12683 BNX2X_MCAST_CMD_ADD);
12684 if (rc < 0)
51c1a580
MS		 12685 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12686 rc);
6e30dd4e 12687
619c5cb6
VZ		 12688 bnx2x_free_mcast_macs_list(&rparam);
12689 }
6e30dd4e 12690
619c5cb6 12691 return rc;
6e30dd4e
VZ		 12692}
12693
619c5cb6 12694/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
a8f47eb7 12695static void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 12696{
12697 struct bnx2x *bp = netdev_priv(dev);
34f80b04
EG		 12698
12699 if (bp->state != BNX2X_STATE_OPEN) {
12700 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12701 return;
8b09be5f
YM		 12702 } else {
12703 /* Schedule an SP task to handle rest of change */
230bb0f3
YM		 12704 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12705 NETIF_MSG_IFUP);
34f80b04 12706 }
8b09be5f
YM		 12707}
12708
12709void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12710{
12711 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04 12712
619c5cb6 12713 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04 12714
8b09be5f
YM		 12715 netif_addr_lock_bh(bp->dev);
12716
12717 if (bp->dev->flags & IFF_PROMISC) {
34f80b04 12718 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f
YM		 12719 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12720 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12721 CHIP_IS_E1(bp))) {
34f80b04 12722 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8b09be5f 12723 } else {
381ac16b
AE		 12724 if (IS_PF(bp)) {
12725 /* some multicasts */
12726 if (bnx2x_set_mc_list(bp) < 0)
12727 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 12728
8b09be5f
YM		 12729 /* release bh lock, as bnx2x_set_uc_list might sleep */
12730 netif_addr_unlock_bh(bp->dev);
381ac16b
AE		 12731 if (bnx2x_set_uc_list(bp) < 0)
12732 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f 12733 netif_addr_lock_bh(bp->dev);
381ac16b
AE		 12734 } else {
12735 /* configuring mcast to a vf involves sleeping (when we
8b09be5f 12736 * wait for the pf's response).
381ac16b 12737 */
230bb0f3
YM		 12738 bnx2x_schedule_sp_rtnl(bp,
12739 BNX2X_SP_RTNL_VFPF_MCAST, 0);
381ac16b 12740 }
34f80b04
EG		 12741 }
12742
12743 bp->rx_mode = rx_mode;
614c76df 12744 /* handle ISCSI SD mode */
2e98ffc2 12745 if (IS_MF_ISCSI_ONLY(bp))
614c76df 12746 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 12747
12748 /* Schedule the rx_mode command */
12749 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12750 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8b09be5f 12751 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 12752 return;
12753 }
12754
381ac16b
AE		 12755 if (IS_PF(bp)) {
12756 bnx2x_set_storm_rx_mode(bp);
8b09be5f 12757 netif_addr_unlock_bh(bp->dev);
381ac16b 12758 } else {
8b09be5f
YM		 12759 /* VF will need to request the PF to make this change, and so
12760 * the VF needs to release the bottom-half lock prior to the
12761 * request (as it will likely require sleep on the VF side)
381ac16b 12762 */
8b09be5f
YM		 12763 netif_addr_unlock_bh(bp->dev);
12764 bnx2x_vfpf_storm_rx_mode(bp);
381ac16b 12765 }
34f80b04
EG		 12766}
12767
c18487ee 12768/* called with rtnl_lock */
01cd4528
EG		 12769static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12770 int devad, u16 addr)
a2fbb9ea 12771{
01cd4528
EG		 12772 struct bnx2x *bp = netdev_priv(netdev);
12773 u16 value;
12774 int rc;
a2fbb9ea 12775
01cd4528
EG		 12776 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12777 prtad, devad, addr);
a2fbb9ea 12778
01cd4528
EG		 12779 /* The HW expects different devad if CL22 is used */
12780 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 12781
01cd4528 12782 bnx2x_acquire_phy_lock(bp);
e10bc84d 12783 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 12784 bnx2x_release_phy_lock(bp);
12785 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 12786
01cd4528
EG		 12787 if (!rc)
12788 rc = value;
12789 return rc;
12790}
a2fbb9ea 12791
01cd4528
EG		 12792/* called with rtnl_lock */
12793static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12794 u16 addr, u16 value)
12795{
12796 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 12797 int rc;
12798
51c1a580
MS		 12799 DP(NETIF_MSG_LINK,
12800 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12801 prtad, devad, addr, value);
01cd4528 12802
01cd4528
EG		 12803 /* The HW expects different devad if CL22 is used */
12804 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 12805
01cd4528 12806 bnx2x_acquire_phy_lock(bp);
e10bc84d 12807 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 12808 bnx2x_release_phy_lock(bp);
12809 return rc;
12810}
c18487ee 12811
01cd4528
EG		 12812/* called with rtnl_lock */
12813static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12814{
12815 struct bnx2x *bp = netdev_priv(dev);
12816 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 12817
01cd4528
EG		 12818 if (!netif_running(dev))
12819 return -EAGAIN;
12820
eeed018c
MK		 12821 switch (cmd) {
12822 case SIOCSHWTSTAMP:
12823 return bnx2x_hwtstamp_ioctl(bp, ifr);
12824 default:
12825 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12826 mdio->phy_id, mdio->reg_num, mdio->val_in);
12827 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12828 }
a2fbb9ea
ET		 12829}
12830
257ddbda 12831#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 12832static void poll_bnx2x(struct net_device *dev)
12833{
12834 struct bnx2x *bp = netdev_priv(dev);
14a15d61 12835 int i;
a2fbb9ea 12836
14a15d61
MS		 12837 for_each_eth_queue(bp, i) {
12838 struct bnx2x_fastpath *fp = &bp->fp[i];
12839 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12840 }
a2fbb9ea
ET		 12841}
12842#endif
12843
614c76df
DK		 12844static int bnx2x_validate_addr(struct net_device *dev)
12845{
12846 struct bnx2x *bp = netdev_priv(dev);
12847
e09b74d0
AE		 12848 /* query the bulletin board for mac address configured by the PF */
12849 if (IS_VF(bp))
12850 bnx2x_sample_bulletin(bp);
12851
2e98ffc2 12852 if (!is_valid_ether_addr(dev->dev_addr)) {
51c1a580 12853 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 12854 return -EADDRNOTAVAIL;
51c1a580 12855 }
614c76df
DK		 12856 return 0;
12857}
12858
3d7d562c 12859static int bnx2x_get_phys_port_id(struct net_device *netdev,
02637fce 12860 struct netdev_phys_item_id *ppid)
3d7d562c
YM		 12861{
12862 struct bnx2x *bp = netdev_priv(netdev);
12863
12864 if (!(bp->flags & HAS_PHYS_PORT_ID))
12865 return -EOPNOTSUPP;
12866
12867 ppid->id_len = sizeof(bp->phys_port_id);
12868 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12869
12870 return 0;
12871}
12872
5f35227e
JG		 12873static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12874 struct net_device *dev,
12875 netdev_features_t features)
51de7bb9 12876{
8cb65d00 12877 features = vlan_features_check(skb, features);
5f35227e 12878 return vxlan_features_check(skb, features);
51de7bb9
JS		 12879}
12880
05cc5a39
YM		 12881static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12882{
12883 int rc;
12884
12885 if (IS_PF(bp)) {
12886 unsigned long ramrod_flags = 0;
12887
12888 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12889 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
12890 add, &ramrod_flags);
12891 } else {
12892 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
12893 }
12894
12895 return rc;
12896}
12897
12898int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
12899{
12900 struct bnx2x_vlan_entry *vlan;
12901 int rc = 0;
12902
12903 if (!bp->vlan_cnt) {
12904 DP(NETIF_MSG_IFUP, "No need to re-configure vlan filters\n");
12905 return 0;
12906 }
12907
12908 list_for_each_entry(vlan, &bp->vlan_reg, link) {
12909 /* Prepare for cleanup in case of errors */
12910 if (rc) {
12911 vlan->hw = false;
12912 continue;
12913 }
12914
12915 if (!vlan->hw)
12916 continue;
12917
12918 DP(NETIF_MSG_IFUP, "Re-configuring vlan 0x%04x\n", vlan->vid);
12919
12920 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12921 if (rc) {
12922 BNX2X_ERR("Unable to configure VLAN %d\n", vlan->vid);
12923 vlan->hw = false;
12924 rc = -EINVAL;
12925 continue;
12926 }
12927 }
12928
12929 return rc;
12930}
12931
12932static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
12933{
12934 struct bnx2x *bp = netdev_priv(dev);
12935 struct bnx2x_vlan_entry *vlan;
12936 bool hw = false;
12937 int rc = 0;
12938
12939 if (!netif_running(bp->dev)) {
12940 DP(NETIF_MSG_IFUP,
12941 "Ignoring VLAN configuration the interface is down\n");
12942 return -EFAULT;
12943 }
12944
12945 DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
12946
12947 vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
12948 if (!vlan)
12949 return -ENOMEM;
12950
12951 bp->vlan_cnt++;
12952 if (bp->vlan_cnt > bp->vlan_credit && !bp->accept_any_vlan) {
12953 DP(NETIF_MSG_IFUP, "Accept all VLAN raised\n");
12954 bp->accept_any_vlan = true;
12955 if (IS_PF(bp))
12956 bnx2x_set_rx_mode_inner(bp);
12957 else
12958 bnx2x_vfpf_storm_rx_mode(bp);
12959 } else if (bp->vlan_cnt <= bp->vlan_credit) {
12960 rc = __bnx2x_vlan_configure_vid(bp, vid, true);
12961 hw = true;
12962 }
12963
12964 vlan->vid = vid;
12965 vlan->hw = hw;
12966
12967 if (!rc) {
12968 list_add(&vlan->link, &bp->vlan_reg);
12969 } else {
12970 bp->vlan_cnt--;
12971 kfree(vlan);
12972 }
12973
12974 DP(NETIF_MSG_IFUP, "Adding VLAN result %d\n", rc);
12975
12976 return rc;
12977}
12978
12979static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
12980{
12981 struct bnx2x *bp = netdev_priv(dev);
12982 struct bnx2x_vlan_entry *vlan;
12983 int rc = 0;
12984
12985 if (!netif_running(bp->dev)) {
12986 DP(NETIF_MSG_IFUP,
12987 "Ignoring VLAN configuration the interface is down\n");
12988 return -EFAULT;
12989 }
12990
12991 DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
12992
12993 if (!bp->vlan_cnt) {
12994 BNX2X_ERR("Unable to kill VLAN %d\n", vid);
12995 return -EINVAL;
12996 }
12997
12998 list_for_each_entry(vlan, &bp->vlan_reg, link)
12999 if (vlan->vid == vid)
13000 break;
13001
13002 if (vlan->vid != vid) {
13003 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
13004 return -EINVAL;
13005 }
13006
13007 if (vlan->hw)
13008 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
13009
13010 list_del(&vlan->link);
13011 kfree(vlan);
13012
13013 bp->vlan_cnt--;
13014
13015 if (bp->vlan_cnt <= bp->vlan_credit && bp->accept_any_vlan) {
13016 /* Configure all non-configured entries */
13017 list_for_each_entry(vlan, &bp->vlan_reg, link) {
13018 if (vlan->hw)
13019 continue;
13020
13021 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
13022 if (rc) {
13023 BNX2X_ERR("Unable to config VLAN %d\n",
13024 vlan->vid);
13025 continue;
13026 }
13027 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n",
13028 vlan->vid);
13029 vlan->hw = true;
13030 }
13031 DP(NETIF_MSG_IFUP, "Accept all VLAN Removed\n");
13032 bp->accept_any_vlan = false;
13033 if (IS_PF(bp))
13034 bnx2x_set_rx_mode_inner(bp);
13035 else
13036 bnx2x_vfpf_storm_rx_mode(bp);
13037 }
13038
13039 DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
13040
13041 return rc;
13042}
13043
c64213cd
SH		 13044static const struct net_device_ops bnx2x_netdev_ops = {
13045 .ndo_open = bnx2x_open,
13046 .ndo_stop = bnx2x_close,
13047 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 13048 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 13049 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 13050 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 13051 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 13052 .ndo_do_ioctl = bnx2x_ioctl,
13053 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 13054 .ndo_fix_features = bnx2x_fix_features,
13055 .ndo_set_features = bnx2x_set_features,
c64213cd 13056 .ndo_tx_timeout = bnx2x_tx_timeout,
05cc5a39
YM		 13057 .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid,
13058 .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid,
257ddbda 13059#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 13060 .ndo_poll_controller = poll_bnx2x,
13061#endif
e4c6734e 13062 .ndo_setup_tc = __bnx2x_setup_tc,
6411280a 13063#ifdef CONFIG_BNX2X_SRIOV
abc5a021 13064 .ndo_set_vf_mac = bnx2x_set_vf_mac,
3cdeec22 13065 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
3ec9f9ca 13066 .ndo_get_vf_config = bnx2x_get_vf_config,
6411280a 13067#endif
55c11941 13068#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 13069 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
13070#endif
8f20aa57 13071
3d7d562c 13072 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
6495d15a 13073 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
5f35227e 13074 .ndo_features_check = bnx2x_features_check,
f34fa14c
RB		 13075#ifdef CONFIG_BNX2X_VXLAN
13076 .ndo_add_vxlan_port = bnx2x_add_vxlan_port,
13077 .ndo_del_vxlan_port = bnx2x_del_vxlan_port,
13078#endif
4fee7dab 13079#if IS_ENABLED(CONFIG_BNX2X_GENEVE)
883ce97d
YM		 13080 .ndo_add_geneve_port = bnx2x_add_geneve_port,
13081 .ndo_del_geneve_port = bnx2x_del_geneve_port,
13082#endif
c64213cd
SH		 13083};
13084
1191cb83 13085static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 13086{
13087 struct device *dev = &bp->pdev->dev;
13088
8ceafbfa
LT		 13089 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13090 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
619c5cb6
VZ		 13091 dev_err(dev, "System does not support DMA, aborting\n");
13092 return -EIO;
13093 }
13094
13095 return 0;
13096}
13097
33d8e6a5
YM		 13098static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13099{
13100 if (bp->flags & AER_ENABLED) {
13101 pci_disable_pcie_error_reporting(bp->pdev);
13102 bp->flags &= ~AER_ENABLED;
13103 }
13104}
13105
1ab4434c
AE		 13106static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13107 struct net_device *dev, unsigned long board_type)
a2fbb9ea 13108{
a2fbb9ea 13109 int rc;
c22610d0 13110 u32 pci_cfg_dword;
65087cfe
AE		 13111 bool chip_is_e1x = (board_type == BCM57710 ||
13112 board_type == BCM57711 ||
13113 board_type == BCM57711E);
a2fbb9ea
ET		 13114
13115 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 13116
34f80b04
EG		 13117 bp->dev = dev;
13118 bp->pdev = pdev;
a2fbb9ea
ET		 13119
13120 rc = pci_enable_device(pdev);
13121 if (rc) {
cdaa7cb8
VZ		 13122 dev_err(&bp->pdev->dev,
13123 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 13124 goto err_out;
13125 }
13126
13127 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 13128 dev_err(&bp->pdev->dev,
13129 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 13130 rc = -ENODEV;
13131 goto err_out_disable;
13132 }
13133
1ab4434c
AE		 13134 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13135 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 13136 rc = -ENODEV;
13137 goto err_out_disable;
13138 }
13139
092a5fc9
YR		 13140 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13141 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13142 PCICFG_REVESION_ID_ERROR_VAL) {
13143 pr_err("PCI device error, probably due to fan failure, aborting\n");
13144 rc = -ENODEV;
13145 goto err_out_disable;
13146 }
13147
34f80b04
EG		 13148 if (atomic_read(&pdev->enable_cnt) == 1) {
13149 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13150 if (rc) {
cdaa7cb8
VZ		 13151 dev_err(&bp->pdev->dev,
13152 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 13153 goto err_out_disable;
13154 }
a2fbb9ea 13155
34f80b04
EG		 13156 pci_set_master(pdev);
13157 pci_save_state(pdev);
13158 }
a2fbb9ea 13159
1ab4434c 13160 if (IS_PF(bp)) {
29ed74c3 13161 if (!pdev->pm_cap) {
1ab4434c
AE		 13162 dev_err(&bp->pdev->dev,
13163 "Cannot find power management capability, aborting\n");
13164 rc = -EIO;
13165 goto err_out_release;
13166 }
a2fbb9ea
ET		 13167 }
13168
77c98e6a 13169 if (!pci_is_pcie(pdev)) {
51c1a580 13170 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 13171 rc = -EIO;
13172 goto err_out_release;
13173 }
13174
619c5cb6
VZ		 13175 rc = bnx2x_set_coherency_mask(bp);
13176 if (rc)
a2fbb9ea 13177 goto err_out_release;
a2fbb9ea 13178
34f80b04
EG		 13179 dev->mem_start = pci_resource_start(pdev, 0);
13180 dev->base_addr = dev->mem_start;
13181 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 13182
13183 dev->irq = pdev->irq;
13184
275f165f 13185 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 13186 if (!bp->regview) {
cdaa7cb8
VZ		 13187 dev_err(&bp->pdev->dev,
13188 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 13189 rc = -ENOMEM;
13190 goto err_out_release;
13191 }
13192
c22610d0
AE		 13193 /* In E1/E1H use pci device function given by kernel.
13194 * In E2/E3 read physical function from ME register since these chips
13195 * support Physical Device Assignment where kernel BDF maybe arbitrary
13196 * (depending on hypervisor).
13197 */
2de67439 13198 if (chip_is_e1x) {
c22610d0 13199 bp->pf_num = PCI_FUNC(pdev->devfn);
2de67439
YM		 13200 } else {
13201 /* chip is E2/3*/
c22610d0
AE		 13202 pci_read_config_dword(bp->pdev,
13203 PCICFG_ME_REGISTER, &pci_cfg_dword);
13204 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
2de67439 13205 ME_REG_ABS_PF_NUM_SHIFT);
c22610d0 13206 }
51c1a580 13207 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 13208
34f80b04
EG		 13209 /* clean indirect addresses */
13210 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13211 PCICFG_VENDOR_ID_OFFSET);
33d8e6a5 13212
da293700
BK		 13213 /* Set PCIe reset type to fundamental for EEH recovery */
13214 pdev->needs_freset = 1;
13215
33d8e6a5
YM		 13216 /* AER (Advanced Error reporting) configuration */
13217 rc = pci_enable_pcie_error_reporting(pdev);
13218 if (!rc)
13219 bp->flags |= AER_ENABLED;
13220 else
13221 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13222
a5c53dbc
DK		 13223 /*
13224 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 13225 * is not used by the driver.
13226 */
1ab4434c
AE		 13227 if (IS_PF(bp)) {
13228 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13229 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13230 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13231 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13232
13233 if (chip_is_e1x) {
13234 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13235 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13236 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13237 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13238 }
a5c53dbc 13239
1ab4434c
AE		 13240 /* Enable internal target-read (in case we are probed after PF
13241 * FLR). Must be done prior to any BAR read access. Only for
13242 * 57712 and up
13243 */
13244 if (!chip_is_e1x)
13245 REG_WR(bp,
13246 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 13247 }
a2fbb9ea 13248
34f80b04 13249 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 13250
c64213cd 13251 dev->netdev_ops = &bnx2x_netdev_ops;
005a07ba 13252 bnx2x_set_ethtool_ops(bp, dev);
5316bc0b 13253
01789349
JP		 13254 dev->priv_flags |= IFF_UNICAST_FLT;
13255
66371c44 13256 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 13257 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13258 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
f646968f 13259 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
a8e0c246 13260 if (!chip_is_e1x) {
117401ee 13261 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
7e13318d 13262 NETIF_F_GSO_IPXIP4;
a848ade4
DK		 13263 dev->hw_enc_features =
13264 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13265 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
7e13318d 13266 NETIF_F_GSO_IPXIP4 |
65bc0cfe 13267 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
a848ade4 13268 }
66371c44
MM		 13269
13270 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13271 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13272
05cc5a39
YM		 13273 /* VF with OLD Hypervisor or old PF do not support filtering */
13274 if (IS_PF(bp)) {
ab6d7846 13275 if (chip_is_e1x)
05cc5a39
YM		 13276 bp->accept_any_vlan = true;
13277 else
13278 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
ce7fa78c 13279#ifdef CONFIG_BNX2X_SRIOV
05cc5a39
YM		 13280 } else if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
13281 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
ce7fa78c 13282#endif
05cc5a39
YM		 13283 }
13284
f646968f 13285 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
edd31476 13286 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 13287
538dd2e3
MB		 13288 /* Add Loopback capability to the device */
13289 dev->hw_features |= NETIF_F_LOOPBACK;
13290
98507672 13291#ifdef BCM_DCBNL
785b9b1a
SR		 13292 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13293#endif
13294
01cd4528
EG		 13295 /* get_port_hwinfo() will set prtad and mmds properly */
13296 bp->mdio.prtad = MDIO_PRTAD_NONE;
13297 bp->mdio.mmds = 0;
13298 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13299 bp->mdio.dev = dev;
13300 bp->mdio.mdio_read = bnx2x_mdio_read;
13301 bp->mdio.mdio_write = bnx2x_mdio_write;
13302
a2fbb9ea
ET		 13303 return 0;
13304
a2fbb9ea 13305err_out_release:
34f80b04
EG		 13306 if (atomic_read(&pdev->enable_cnt) == 1)
13307 pci_release_regions(pdev);
a2fbb9ea
ET		 13308
13309err_out_disable:
13310 pci_disable_device(pdev);
a2fbb9ea
ET		 13311
13312err_out:
13313 return rc;
13314}
13315
6891dd25 13316static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 13317{
37f9ce62 13318 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 13319 struct bnx2x_fw_file_hdr *fw_hdr;
13320 struct bnx2x_fw_file_section *sections;
94a78b79 13321 u32 offset, len, num_ops;
86564c3f 13322 __be16 *ops_offsets;
94a78b79 13323 int i;
37f9ce62 13324 const u8 *fw_ver;
94a78b79 13325
51c1a580
MS		 13326 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
13327 BNX2X_ERR("Wrong FW size\n");
94a78b79 13328 return -EINVAL;
51c1a580 13329 }
94a78b79
VZ		 13330
13331 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
13332 sections = (struct bnx2x_fw_file_section *)fw_hdr;
13333
13334 /* Make sure none of the offsets and sizes make us read beyond
13335 * the end of the firmware data */
13336 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
13337 offset = be32_to_cpu(sections[i].offset);
13338 len = be32_to_cpu(sections[i].len);
13339 if (offset + len > firmware->size) {
51c1a580 13340 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 13341 return -EINVAL;
13342 }
13343 }
13344
13345 /* Likewise for the init_ops offsets */
13346 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
86564c3f 13347 ops_offsets = (__force __be16 *)(firmware->data + offset);
94a78b79
VZ		 13348 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
13349
13350 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
13351 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 13352 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 13353 return -EINVAL;
13354 }
13355 }
13356
13357 /* Check FW version */
13358 offset = be32_to_cpu(fw_hdr->fw_version.offset);
13359 fw_ver = firmware->data + offset;
13360 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
13361 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
13362 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
13363 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 13364 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13365 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
13366 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 13367 BCM_5710_FW_MINOR_VERSION,
13368 BCM_5710_FW_REVISION_VERSION,
13369 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 13370 return -EINVAL;
94a78b79
VZ		 13371 }
13372
13373 return 0;
13374}
13375
1191cb83 13376static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 13377{
ab6ad5a4
EG		 13378 const __be32 *source = (const __be32 *)_source;
13379 u32 *target = (u32 *)_target;
94a78b79 13380 u32 i;
94a78b79
VZ		 13381
13382 for (i = 0; i < n/4; i++)
13383 target[i] = be32_to_cpu(source[i]);
13384}
13385
13386/*
13387 Ops array is stored in the following format:
13388 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13389 */
1191cb83 13390static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 13391{
ab6ad5a4
EG		 13392 const __be32 *source = (const __be32 *)_source;
13393 struct raw_op *target = (struct raw_op *)_target;
94a78b79 13394 u32 i, j, tmp;
94a78b79 13395
ab6ad5a4 13396 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 13397 tmp = be32_to_cpu(source[j]);
13398 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 13399 target[i].offset = tmp & 0xffffff;
13400 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 13401 }
13402}
ab6ad5a4 13403
1aa8b471 13404/* IRO array is stored in the following format:
523224a3
DK		 13405 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13406 */
1191cb83 13407static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 13408{
13409 const __be32 *source = (const __be32 *)_source;
13410 struct iro *target = (struct iro *)_target;
13411 u32 i, j, tmp;
13412
13413 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13414 target[i].base = be32_to_cpu(source[j]);
13415 j++;
13416 tmp = be32_to_cpu(source[j]);
13417 target[i].m1 = (tmp >> 16) & 0xffff;
13418 target[i].m2 = tmp & 0xffff;
13419 j++;
13420 tmp = be32_to_cpu(source[j]);
13421 target[i].m3 = (tmp >> 16) & 0xffff;
13422 target[i].size = tmp & 0xffff;
13423 j++;
13424 }
13425}
13426
1191cb83 13427static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 13428{
ab6ad5a4
EG		 13429 const __be16 *source = (const __be16 *)_source;
13430 u16 *target = (u16 *)_target;
94a78b79 13431 u32 i;
94a78b79
VZ		 13432
13433 for (i = 0; i < n/2; i++)
13434 target[i] = be16_to_cpu(source[i]);
13435}
13436
7995c64e
JP		 13437#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13438do { \
13439 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13440 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 13441 if (!bp->arr) \
7995c64e 13442 goto lbl; \
7995c64e
JP		 13443 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13444 (u8 *)bp->arr, len); \
13445} while (0)
94a78b79 13446
3b603066 13447static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 13448{
c0ea452e 13449 const char *fw_file_name;
94a78b79 13450 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 13451 int rc;
94a78b79 13452
c0ea452e
MS		 13453 if (bp->firmware)
13454 return 0;
94a78b79 13455
c0ea452e
MS		 13456 if (CHIP_IS_E1(bp))
13457 fw_file_name = FW_FILE_NAME_E1;
13458 else if (CHIP_IS_E1H(bp))
13459 fw_file_name = FW_FILE_NAME_E1H;
13460 else if (!CHIP_IS_E1x(bp))
13461 fw_file_name = FW_FILE_NAME_E2;
13462 else {
13463 BNX2X_ERR("Unsupported chip revision\n");
13464 return -EINVAL;
13465 }
13466 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 13467
c0ea452e
MS		 13468 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13469 if (rc) {
13470 BNX2X_ERR("Can't load firmware file %s\n",
13471 fw_file_name);
13472 goto request_firmware_exit;
13473 }
eb2afd4a 13474
c0ea452e
MS		 13475 rc = bnx2x_check_firmware(bp);
13476 if (rc) {
13477 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13478 goto request_firmware_exit;
94a78b79
VZ		 13479 }
13480
13481 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13482
13483 /* Initialize the pointers to the init arrays */
13484 /* Blob */
13485 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13486
13487 /* Opcodes */
13488 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13489
13490 /* Offsets */
ab6ad5a4
EG		 13491 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13492 be16_to_cpu_n);
94a78b79
VZ		 13493
13494 /* STORMs firmware */
573f2035
EG		 13495 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13496 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13497 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
13498 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13499 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13500 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13501 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
13502 be32_to_cpu(fw_hdr->usem_pram_data.offset);
13503 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13504 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13505 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
13506 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13507 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13508 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13509 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
13510 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 13511 /* IRO */
13512 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 13513
13514 return 0;
ab6ad5a4 13515
523224a3
DK		 13516iro_alloc_err:
13517 kfree(bp->init_ops_offsets);
94a78b79
VZ		 13518init_offsets_alloc_err:
13519 kfree(bp->init_ops);
13520init_ops_alloc_err:
13521 kfree(bp->init_data);
13522request_firmware_exit:
13523 release_firmware(bp->firmware);
127d0a19 13524 bp->firmware = NULL;
94a78b79
VZ		 13525
13526 return rc;
13527}
13528
619c5cb6
VZ		 13529static void bnx2x_release_firmware(struct bnx2x *bp)
13530{
13531 kfree(bp->init_ops_offsets);
13532 kfree(bp->init_ops);
13533 kfree(bp->init_data);
13534 release_firmware(bp->firmware);
eb2afd4a 13535 bp->firmware = NULL;
619c5cb6
VZ		 13536}
13537
619c5cb6
VZ		 13538static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13539 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13540 .init_hw_cmn = bnx2x_init_hw_common,
13541 .init_hw_port = bnx2x_init_hw_port,
13542 .init_hw_func = bnx2x_init_hw_func,
13543
13544 .reset_hw_cmn = bnx2x_reset_common,
13545 .reset_hw_port = bnx2x_reset_port,
13546 .reset_hw_func = bnx2x_reset_func,
13547
13548 .gunzip_init = bnx2x_gunzip_init,
13549 .gunzip_end = bnx2x_gunzip_end,
13550
13551 .init_fw = bnx2x_init_firmware,
13552 .release_fw = bnx2x_release_firmware,
13553};
13554
13555void bnx2x__init_func_obj(struct bnx2x *bp)
13556{
13557 /* Prepare DMAE related driver resources */
13558 bnx2x_setup_dmae(bp);
13559
13560 bnx2x_init_func_obj(bp, &bp->func_obj,
13561 bnx2x_sp(bp, func_rdata),
13562 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 13563 bnx2x_sp(bp, func_afex_rdata),
13564 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 13565 &bnx2x_func_sp_drv);
13566}
13567
13568/* must be called after sriov-enable */
1191cb83 13569static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 13570{
37ae41a9 13571 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 13572
290ca2bb
AE		 13573 if (IS_SRIOV(bp))
13574 cid_count += BNX2X_VF_CIDS;
13575
55c11941
MS		 13576 if (CNIC_SUPPORT(bp))
13577 cid_count += CNIC_CID_MAX;
290ca2bb 13578
523224a3
DK		 13579 return roundup(cid_count, QM_CID_ROUND);
13580}
f85582f8 13581
619c5cb6 13582/**
6383c0b3 13583 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 13584 *
13585 * @dev: pci device
13586 *
13587 */
60cad4e6 13588static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
619c5cb6 13589{
ae2104be 13590 int index;
1ab4434c 13591 u16 control = 0;
619c5cb6 13592
6383c0b3
AE		 13593 /*
13594 * If MSI-X is not supported - return number of SBs needed to support
13595 * one fast path queue: one FP queue + SB for CNIC
13596 */
ae2104be 13597 if (!pdev->msix_cap) {
1ab4434c 13598 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 13599 return 1 + cnic_cnt;
1ab4434c
AE		 13600 }
13601 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 13602
6383c0b3
AE		 13603 /*
13604 * The value in the PCI configuration space is the index of the last
13605 * entry, namely one less than the actual size of the table, which is
13606 * exactly what we want to return from this function: number of all SBs
13607 * without the default SB.
1ab4434c 13608 * For VFs there is no default SB, then we return (index+1).
6383c0b3 13609 */
73413ffa 13610 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
619c5cb6 13611
1ab4434c 13612 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 13613
60cad4e6 13614 return index;
1ab4434c 13615}
523224a3 13616
1ab4434c
AE		 13617static int set_max_cos_est(int chip_id)
13618{
13619 switch (chip_id) {
f2e0899f
DK		 13620 case BCM57710:
13621 case BCM57711:
13622 case BCM57711E:
1ab4434c 13623 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 13624 case BCM57712:
619c5cb6 13625 case BCM57712_MF:
1ab4434c 13626 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 13627 case BCM57800:
13628 case BCM57800_MF:
13629 case BCM57810:
13630 case BCM57810_MF:
c3def943
YM		 13631 case BCM57840_4_10:
13632 case BCM57840_2_20:
1ab4434c 13633 case BCM57840_O:
c3def943 13634 case BCM57840_MFO:
619c5cb6 13635 case BCM57840_MF:
7e8e02df
BW		 13636 case BCM57811:
13637 case BCM57811_MF:
1ab4434c 13638 return BNX2X_MULTI_TX_COS_E3B0;
b1239723
YM		 13639 case BCM57712_VF:
13640 case BCM57800_VF:
13641 case BCM57810_VF:
13642 case BCM57840_VF:
13643 case BCM57811_VF:
1ab4434c 13644 return 1;
f2e0899f 13645 default:
1ab4434c 13646 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 13647 return -ENODEV;
f2e0899f 13648 }
1ab4434c 13649}
f2e0899f 13650
1ab4434c
AE		 13651static int set_is_vf(int chip_id)
13652{
13653 switch (chip_id) {
13654 case BCM57712_VF:
13655 case BCM57800_VF:
13656 case BCM57810_VF:
13657 case BCM57840_VF:
13658 case BCM57811_VF:
13659 return true;
13660 default:
13661 return false;
13662 }
13663}
6383c0b3 13664
eeed018c
MK		 13665/* nig_tsgen registers relative address */
13666#define tsgen_ctrl 0x0
13667#define tsgen_freecount 0x10
13668#define tsgen_synctime_t0 0x20
13669#define tsgen_offset_t0 0x28
13670#define tsgen_drift_t0 0x30
13671#define tsgen_synctime_t1 0x58
13672#define tsgen_offset_t1 0x60
13673#define tsgen_drift_t1 0x68
13674
13675/* FW workaround for setting drift */
13676static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13677 int best_val, int best_period)
13678{
13679 struct bnx2x_func_state_params func_params = {NULL};
13680 struct bnx2x_func_set_timesync_params *set_timesync_params =
13681 &func_params.params.set_timesync;
13682
13683 /* Prepare parameters for function state transitions */
13684 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13685 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13686
13687 func_params.f_obj = &bp->func_obj;
13688 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13689
13690 /* Function parameters */
13691 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13692 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13693 set_timesync_params->add_sub_drift_adjust_value =
13694 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13695 set_timesync_params->drift_adjust_value = best_val;
13696 set_timesync_params->drift_adjust_period = best_period;
13697
13698 return bnx2x_func_state_change(bp, &func_params);
13699}
13700
13701static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13702{
13703 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13704 int rc;
13705 int drift_dir = 1;
13706 int val, period, period1, period2, dif, dif1, dif2;
13707 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13708
13709 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13710
13711 if (!netif_running(bp->dev)) {
13712 DP(BNX2X_MSG_PTP,
13713 "PTP adjfreq called while the interface is down\n");
13714 return -EFAULT;
13715 }
13716
13717 if (ppb < 0) {
13718 ppb = -ppb;
13719 drift_dir = 0;
13720 }
13721
13722 if (ppb == 0) {
13723 best_val = 1;
13724 best_period = 0x1FFFFFF;
13725 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13726 best_val = 31;
13727 best_period = 1;
13728 } else {
13729 /* Changed not to allow val = 8, 16, 24 as these values
13730 * are not supported in workaround.
13731 */
13732 for (val = 0; val <= 31; val++) {
13733 if ((val & 0x7) == 0)
13734 continue;
13735 period1 = val * 1000000 / ppb;
13736 period2 = period1 + 1;
13737 if (period1 != 0)
13738 dif1 = ppb - (val * 1000000 / period1);
13739 else
13740 dif1 = BNX2X_MAX_PHC_DRIFT;
13741 if (dif1 < 0)
13742 dif1 = -dif1;
13743 dif2 = ppb - (val * 1000000 / period2);
13744 if (dif2 < 0)
13745 dif2 = -dif2;
13746 dif = (dif1 < dif2) ? dif1 : dif2;
13747 period = (dif1 < dif2) ? period1 : period2;
13748 if (dif < best_dif) {
13749 best_dif = dif;
13750 best_val = val;
13751 best_period = period;
13752 }
13753 }
13754 }
13755
13756 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13757 best_period);
13758 if (rc) {
13759 BNX2X_ERR("Failed to set drift\n");
13760 return -EFAULT;
13761 }
13762
bf27c353 13763 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
eeed018c
MK		 13764 best_period);
13765
13766 return 0;
13767}
13768
13769static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13770{
13771 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
eeed018c
MK		 13772
13773 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13774
2e5601f9 13775 timecounter_adjtime(&bp->timecounter, delta);
eeed018c
MK		 13776
13777 return 0;
13778}
13779
5d45186b 13780static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
eeed018c
MK		 13781{
13782 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13783 u64 ns;
eeed018c
MK		 13784
13785 ns = timecounter_read(&bp->timecounter);
13786
13787 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13788
f7dcdefe 13789 *ts = ns_to_timespec64(ns);
eeed018c
MK		 13790
13791 return 0;
13792}
13793
13794static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
5d45186b 13795 const struct timespec64 *ts)
eeed018c
MK		 13796{
13797 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13798 u64 ns;
13799
f7dcdefe 13800 ns = timespec64_to_ns(ts);
eeed018c
MK		 13801
13802 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13803
13804 /* Re-init the timecounter */
13805 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13806
13807 return 0;
13808}
13809
13810/* Enable (or disable) ancillary features of the phc subsystem */
13811static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13812 struct ptp_clock_request *rq, int on)
13813{
13814 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13815
13816 BNX2X_ERR("PHC ancillary features are not supported\n");
13817 return -ENOTSUPP;
13818}
13819
1444c301 13820static void bnx2x_register_phc(struct bnx2x *bp)
eeed018c
MK		 13821{
13822 /* Fill the ptp_clock_info struct and register PTP clock*/
13823 bp->ptp_clock_info.owner = THIS_MODULE;
13824 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13825 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13826 bp->ptp_clock_info.n_alarm = 0;
13827 bp->ptp_clock_info.n_ext_ts = 0;
13828 bp->ptp_clock_info.n_per_out = 0;
13829 bp->ptp_clock_info.pps = 0;
13830 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13831 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
5d45186b
RC		 13832 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13833 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
eeed018c
MK		 13834 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13835
13836 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13837 if (IS_ERR(bp->ptp_clock)) {
13838 bp->ptp_clock = NULL;
13839 BNX2X_ERR("PTP clock registeration failed\n");
13840 }
13841}
13842
1ab4434c
AE		 13843static int bnx2x_init_one(struct pci_dev *pdev,
13844 const struct pci_device_id *ent)
13845{
13846 struct net_device *dev = NULL;
13847 struct bnx2x *bp;
b91e1a1a
YM		 13848 enum pcie_link_width pcie_width;
13849 enum pci_bus_speed pcie_speed;
1ab4434c
AE		 13850 int rc, max_non_def_sbs;
13851 int rx_count, tx_count, rss_count, doorbell_size;
13852 int max_cos_est;
13853 bool is_vf;
13854 int cnic_cnt;
13855
12a8541d
YM		 13856 /* Management FW 'remembers' living interfaces. Allow it some time
13857 * to forget previously living interfaces, allowing a proper re-load.
13858 */
cd9c3997
MS		 13859 if (is_kdump_kernel()) {
13860 ktime_t now = ktime_get_boottime();
13861 ktime_t fw_ready_time = ktime_set(5, 0);
13862
13863 if (ktime_before(now, fw_ready_time))
13864 msleep(ktime_ms_delta(fw_ready_time, now));
13865 }
12a8541d 13866
1ab4434c
AE		 13867 /* An estimated maximum supported CoS number according to the chip
13868 * version.
13869 * We will try to roughly estimate the maximum number of CoSes this chip
13870 * may support in order to minimize the memory allocated for Tx
13871 * netdev_queue's. This number will be accurately calculated during the
13872 * initialization of bp->max_cos based on the chip versions AND chip
13873 * revision in the bnx2x_init_bp().
13874 */
13875 max_cos_est = set_max_cos_est(ent->driver_data);
13876 if (max_cos_est < 0)
13877 return max_cos_est;
13878 is_vf = set_is_vf(ent->driver_data);
13879 cnic_cnt = is_vf ? 0 : 1;
13880
60cad4e6
AE		 13881 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13882
13883 /* add another SB for VF as it has no default SB */
13884 max_non_def_sbs += is_vf ? 1 : 0;
6383c0b3
AE		 13885
13886 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
60cad4e6 13887 rss_count = max_non_def_sbs - cnic_cnt;
1ab4434c
AE		 13888
13889 if (rss_count < 1)
13890 return -EINVAL;
6383c0b3
AE		 13891
13892 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 13893 rx_count = rss_count + cnic_cnt;
6383c0b3 13894
1ab4434c 13895 /* Maximum number of netdev Tx queues:
37ae41a9 13896 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 13897 */
55c11941 13898 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 13899
a2fbb9ea 13900 /* dev zeroed in init_etherdev */
6383c0b3 13901 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 13902 if (!dev)
a2fbb9ea
ET		 13903 return -ENOMEM;
13904
a2fbb9ea 13905 bp = netdev_priv(dev);
a2fbb9ea 13906
1ab4434c
AE		 13907 bp->flags = 0;
13908 if (is_vf)
13909 bp->flags |= IS_VF_FLAG;
13910
6383c0b3 13911 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 13912 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 13913 bp->msg_enable = debug;
55c11941 13914 bp->cnic_support = cnic_cnt;
4bd9b0ff 13915 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 13916
6383c0b3 13917 pci_set_drvdata(pdev, dev);
523224a3 13918
1ab4434c 13919 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 13920 if (rc < 0) {
13921 free_netdev(dev);
13922 return rc;
13923 }
13924
1ab4434c
AE		 13925 BNX2X_DEV_INFO("This is a %s function\n",
13926 IS_PF(bp) ? "physical" : "virtual");
55c11941 13927 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 13928 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509 13929 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
2de67439 13930 tx_count, rx_count);
60aa0509 13931
34f80b04 13932 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 13933 if (rc)
13934 goto init_one_exit;
13935
1ab4434c
AE		 13936 /* Map doorbells here as we need the real value of bp->max_cos which
13937 * is initialized in bnx2x_init_bp() to determine the number of
13938 * l2 connections.
6383c0b3 13939 */
1ab4434c 13940 if (IS_VF(bp)) {
1d6f3cd8 13941 bp->doorbells = bnx2x_vf_doorbells(bp);
6411280a
AE		 13942 rc = bnx2x_vf_pci_alloc(bp);
13943 if (rc)
13944 goto init_one_exit;
1ab4434c
AE		 13945 } else {
13946 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13947 if (doorbell_size > pci_resource_len(pdev, 2)) {
13948 dev_err(&bp->pdev->dev,
13949 "Cannot map doorbells, bar size too small, aborting\n");
13950 rc = -ENOMEM;
13951 goto init_one_exit;
13952 }
13953 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13954 doorbell_size);
37ae41a9 13955 }
6383c0b3
AE		 13956 if (!bp->doorbells) {
13957 dev_err(&bp->pdev->dev,
13958 "Cannot map doorbell space, aborting\n");
13959 rc = -ENOMEM;
13960 goto init_one_exit;
13961 }
13962
be1f1ffa
AE		 13963 if (IS_VF(bp)) {
13964 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13965 if (rc)
13966 goto init_one_exit;
13967 }
13968
3c76feff
AE		 13969 /* Enable SRIOV if capability found in configuration space */
13970 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
290ca2bb
AE		 13971 if (rc)
13972 goto init_one_exit;
13973
523224a3 13974 /* calc qm_cid_count */
6383c0b3 13975 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 13976 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 13977
55c11941 13978 /* disable FCOE L2 queue for E1x*/
62ac0dc9 13979 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 13980 bp->flags |= NO_FCOE_FLAG;
13981
0e8d2ec5
MS		 13982 /* Set bp->num_queues for MSI-X mode*/
13983 bnx2x_set_num_queues(bp);
13984
25985edc 13985 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 13986 * needed.
d6214d7a 13987 */
1ab4434c
AE		 13988 rc = bnx2x_set_int_mode(bp);
13989 if (rc) {
13990 dev_err(&pdev->dev, "Cannot set interrupts\n");
13991 goto init_one_exit;
13992 }
04c46736 13993 BNX2X_DEV_INFO("set interrupts successfully\n");
d6214d7a 13994
1ab4434c 13995 /* register the net device */
b340007f
VZ		 13996 rc = register_netdev(dev);
13997 if (rc) {
13998 dev_err(&pdev->dev, "Cannot register net device\n");
13999 goto init_one_exit;
14000 }
1ab4434c 14001 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 14002
ec6ba945
VZ		 14003 if (!NO_FCOE(bp)) {
14004 /* Add storage MAC address */
14005 rtnl_lock();
14006 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14007 rtnl_unlock();
14008 }
b91e1a1a
YM		 14009 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
14010 pcie_speed == PCI_SPEED_UNKNOWN ||
14011 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
14012 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
14013 else
14014 BNX2X_DEV_INFO(
14015 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
ca1ee4b2
DK		 14016 board_info[ent->driver_data].name,
14017 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
14018 pcie_width,
b91e1a1a
YM		 14019 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
14020 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
14021 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
ca1ee4b2
DK		 14022 "Unknown",
14023 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 14024
eeed018c
MK		 14025 bnx2x_register_phc(bp);
14026
230d00eb
YM		 14027 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
14028 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
14029
a2fbb9ea 14030 return 0;
34f80b04
EG		 14031
14032init_one_exit:
33d8e6a5
YM		 14033 bnx2x_disable_pcie_error_reporting(bp);
14034
34f80b04
EG		 14035 if (bp->regview)
14036 iounmap(bp->regview);
14037
1ab4434c 14038 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 14039 iounmap(bp->doorbells);
14040
14041 free_netdev(dev);
14042
14043 if (atomic_read(&pdev->enable_cnt) == 1)
14044 pci_release_regions(pdev);
14045
14046 pci_disable_device(pdev);
34f80b04
EG		 14047
14048 return rc;
a2fbb9ea
ET		 14049}
14050
b030ed2f
YM		 14051static void __bnx2x_remove(struct pci_dev *pdev,
14052 struct net_device *dev,
14053 struct bnx2x *bp,
14054 bool remove_netdev)
a2fbb9ea 14055{
eeed018c
MK		 14056 if (bp->ptp_clock) {
14057 ptp_clock_unregister(bp->ptp_clock);
14058 bp->ptp_clock = NULL;
14059 }
14060
ec6ba945
VZ		 14061 /* Delete storage MAC address */
14062 if (!NO_FCOE(bp)) {
14063 rtnl_lock();
14064 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14065 rtnl_unlock();
14066 }
ec6ba945 14067
98507672
SR		 14068#ifdef BCM_DCBNL
14069 /* Delete app tlvs from dcbnl */
14070 bnx2x_dcbnl_update_applist(bp, true);
14071#endif
14072
a6d3a5ba
BW		 14073 if (IS_PF(bp) &&
14074 !BP_NOMCP(bp) &&
14075 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14076 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14077
b030ed2f
YM		 14078 /* Close the interface - either directly or implicitly */
14079 if (remove_netdev) {
14080 unregister_netdev(dev);
14081 } else {
14082 rtnl_lock();
6ef5a92c 14083 dev_close(dev);
b030ed2f
YM		 14084 rtnl_unlock();
14085 }
a2fbb9ea 14086
78c3bcc5
AE		 14087 bnx2x_iov_remove_one(bp);
14088
084d6cbb 14089 /* Power on: we can't let PCI layer write to us while we are in D3 */
04860eb7 14090 if (IS_PF(bp)) {
1ab4434c 14091 bnx2x_set_power_state(bp, PCI_D0);
230d00eb 14092 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
084d6cbb 14093
04860eb7
MC		 14094 /* Set endianity registers to reset values in case next driver
14095 * boots in different endianty environment.
14096 */
14097 bnx2x_reset_endianity(bp);
14098 }
14099
d6214d7a
DK		 14100 /* Disable MSI/MSI-X */
14101 bnx2x_disable_msi(bp);
f85582f8 14102
084d6cbb 14103 /* Power off */
1ab4434c
AE		 14104 if (IS_PF(bp))
14105 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 14106
72fd0718 14107 /* Make sure RESET task is not scheduled before continuing */
7be08a72 14108 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb 14109
4513f925
AE		 14110 /* send message via vfpf channel to release the resources of this vf */
14111 if (IS_VF(bp))
14112 bnx2x_vfpf_release(bp);
72fd0718 14113
b030ed2f
YM		 14114 /* Assumes no further PCIe PM changes will occur */
14115 if (system_state == SYSTEM_POWER_OFF) {
14116 pci_wake_from_d3(pdev, bp->wol);
14117 pci_set_power_state(pdev, PCI_D3hot);
14118 }
14119
33d8e6a5 14120 bnx2x_disable_pcie_error_reporting(bp);
d9aee591
YM		 14121 if (remove_netdev) {
14122 if (bp->regview)
14123 iounmap(bp->regview);
33d8e6a5 14124
d9aee591
YM		 14125 /* For vfs, doorbells are part of the regview and were unmapped
14126 * along with it. FW is only loaded by PF.
14127 */
14128 if (IS_PF(bp)) {
14129 if (bp->doorbells)
14130 iounmap(bp->doorbells);
eb2afd4a 14131
d9aee591 14132 bnx2x_release_firmware(bp);
e2a367f8
YM		 14133 } else {
14134 bnx2x_vf_pci_dealloc(bp);
d9aee591
YM		 14135 }
14136 bnx2x_free_mem_bp(bp);
523224a3 14137
b030ed2f 14138 free_netdev(dev);
34f80b04 14139
d9aee591
YM		 14140 if (atomic_read(&pdev->enable_cnt) == 1)
14141 pci_release_regions(pdev);
34f80b04 14142
5f6db130
YM		 14143 pci_disable_device(pdev);
14144 }
a2fbb9ea
ET		 14145}
14146
b030ed2f
YM		 14147static void bnx2x_remove_one(struct pci_dev *pdev)
14148{
14149 struct net_device *dev = pci_get_drvdata(pdev);
14150 struct bnx2x *bp;
14151
14152 if (!dev) {
14153 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14154 return;
14155 }
14156 bp = netdev_priv(dev);
14157
14158 __bnx2x_remove(pdev, dev, bp, true);
14159}
14160
f8ef6e44
YG		 14161static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14162{
7fa6f340 14163 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
f8ef6e44
YG		 14164
14165 bp->rx_mode = BNX2X_RX_MODE_NONE;
14166
55c11941
MS		 14167 if (CNIC_LOADED(bp))
14168 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14169
619c5cb6
VZ		 14170 /* Stop Tx */
14171 bnx2x_tx_disable(bp);
26614ba5
MS		 14172 /* Delete all NAPI objects */
14173 bnx2x_del_all_napi(bp);
55c11941
MS		 14174 if (CNIC_LOADED(bp))
14175 bnx2x_del_all_napi_cnic(bp);
7fa6f340 14176 netdev_reset_tc(bp->dev);
f8ef6e44
YG		 14177
14178 del_timer_sync(&bp->timer);
0c0e6341 14179 cancel_delayed_work_sync(&bp->sp_task);
14180 cancel_delayed_work_sync(&bp->period_task);
619c5cb6 14181
c6e36d8c
YM		 14182 if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14183 bp->stats_state = STATS_STATE_DISABLED;
14184 up(&bp->stats_lock);
14185 }
f8ef6e44 14186
7fa6f340 14187 bnx2x_save_statistics(bp);
f8ef6e44 14188
619c5cb6
VZ		 14189 netif_carrier_off(bp->dev);
14190
f8ef6e44
YG		 14191 return 0;
14192}
14193
493adb1f
WX		 14194/**
14195 * bnx2x_io_error_detected - called when PCI error is detected
14196 * @pdev: Pointer to PCI device
14197 * @state: The current pci connection state
14198 *
14199 * This function is called after a PCI bus error affecting
14200 * this device has been detected.
14201 */
14202static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14203 pci_channel_state_t state)
14204{
14205 struct net_device *dev = pci_get_drvdata(pdev);
14206 struct bnx2x *bp = netdev_priv(dev);
14207
14208 rtnl_lock();
14209
7fa6f340
YM		 14210 BNX2X_ERR("IO error detected\n");
14211
493adb1f
WX		 14212 netif_device_detach(dev);
14213
07ce50e4
DN		 14214 if (state == pci_channel_io_perm_failure) {
14215 rtnl_unlock();
14216 return PCI_ERS_RESULT_DISCONNECT;
14217 }
14218
493adb1f 14219 if (netif_running(dev))
f8ef6e44 14220 bnx2x_eeh_nic_unload(bp);
493adb1f 14221
7fa6f340
YM		 14222 bnx2x_prev_path_mark_eeh(bp);
14223
493adb1f
WX		 14224 pci_disable_device(pdev);
14225
14226 rtnl_unlock();
14227
14228 /* Request a slot reset */
14229 return PCI_ERS_RESULT_NEED_RESET;
14230}
14231
14232/**
14233 * bnx2x_io_slot_reset - called after the PCI bus has been reset
14234 * @pdev: Pointer to PCI device
14235 *
14236 * Restart the card from scratch, as if from a cold-boot.
14237 */
14238static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14239{
14240 struct net_device *dev = pci_get_drvdata(pdev);
14241 struct bnx2x *bp = netdev_priv(dev);
7fa6f340 14242 int i;
493adb1f
WX		 14243
14244 rtnl_lock();
7fa6f340 14245 BNX2X_ERR("IO slot reset initializing...\n");
493adb1f
WX		 14246 if (pci_enable_device(pdev)) {
14247 dev_err(&pdev->dev,
14248 "Cannot re-enable PCI device after reset\n");
14249 rtnl_unlock();
14250 return PCI_ERS_RESULT_DISCONNECT;
14251 }
14252
14253 pci_set_master(pdev);
14254 pci_restore_state(pdev);
70632d0a 14255 pci_save_state(pdev);
493adb1f
WX		 14256
14257 if (netif_running(dev))
14258 bnx2x_set_power_state(bp, PCI_D0);
14259
7fa6f340
YM		 14260 if (netif_running(dev)) {
14261 BNX2X_ERR("IO slot reset --> driver unload\n");
e68072ef
YM		 14262
14263 /* MCP should have been reset; Need to wait for validity */
14264 bnx2x_init_shmem(bp);
14265
7fa6f340
YM		 14266 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14267 u32 v;
14268
14269 v = SHMEM2_RD(bp,
14270 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14271 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14272 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14273 }
14274 bnx2x_drain_tx_queues(bp);
14275 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14276 bnx2x_netif_stop(bp, 1);
14277 bnx2x_free_irq(bp);
14278
14279 /* Report UNLOAD_DONE to MCP */
14280 bnx2x_send_unload_done(bp, true);
14281
14282 bp->sp_state = 0;
14283 bp->port.pmf = 0;
14284
14285 bnx2x_prev_unload(bp);
14286
16a5fd92 14287 /* We should have reseted the engine, so It's fair to
7fa6f340
YM		 14288 * assume the FW will no longer write to the bnx2x driver.
14289 */
14290 bnx2x_squeeze_objects(bp);
14291 bnx2x_free_skbs(bp);
14292 for_each_rx_queue(bp, i)
14293 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14294 bnx2x_free_fp_mem(bp);
14295 bnx2x_free_mem(bp);
14296
14297 bp->state = BNX2X_STATE_CLOSED;
14298 }
14299
493adb1f
WX		 14300 rtnl_unlock();
14301
33d8e6a5
YM		 14302 /* If AER, perform cleanup of the PCIe registers */
14303 if (bp->flags & AER_ENABLED) {
14304 if (pci_cleanup_aer_uncorrect_error_status(pdev))
14305 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14306 else
14307 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14308 }
14309
493adb1f
WX		 14310 return PCI_ERS_RESULT_RECOVERED;
14311}
14312
14313/**
14314 * bnx2x_io_resume - called when traffic can start flowing again
14315 * @pdev: Pointer to PCI device
14316 *
14317 * This callback is called when the error recovery driver tells us that
14318 * its OK to resume normal operation.
14319 */
14320static void bnx2x_io_resume(struct pci_dev *pdev)
14321{
14322 struct net_device *dev = pci_get_drvdata(pdev);
14323 struct bnx2x *bp = netdev_priv(dev);
14324
72fd0718 14325 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 14326 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 14327 return;
14328 }
14329
493adb1f
WX		 14330 rtnl_lock();
14331
7fa6f340
YM		 14332 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14333 DRV_MSG_SEQ_NUMBER_MASK;
14334
493adb1f 14335 if (netif_running(dev))
f8ef6e44 14336 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 14337
14338 netif_device_attach(dev);
14339
14340 rtnl_unlock();
14341}
14342
3646f0e5 14343static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 14344 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 14345 .slot_reset = bnx2x_io_slot_reset,
14346 .resume = bnx2x_io_resume,
493adb1f
WX		 14347};
14348
b030ed2f
YM		 14349static void bnx2x_shutdown(struct pci_dev *pdev)
14350{
14351 struct net_device *dev = pci_get_drvdata(pdev);
14352 struct bnx2x *bp;
14353
14354 if (!dev)
14355 return;
14356
14357 bp = netdev_priv(dev);
14358 if (!bp)
14359 return;
14360
14361 rtnl_lock();
14362 netif_device_detach(dev);
14363 rtnl_unlock();
14364
14365 /* Don't remove the netdevice, as there are scenarios which will cause
14366 * the kernel to hang, e.g., when trying to remove bnx2i while the
14367 * rootfs is mounted from SAN.
14368 */
14369 __bnx2x_remove(pdev, dev, bp, false);
14370}
14371
a2fbb9ea 14372static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 14373 .name = DRV_MODULE_NAME,
14374 .id_table = bnx2x_pci_tbl,
14375 .probe = bnx2x_init_one,
0329aba1 14376 .remove = bnx2x_remove_one,
493adb1f
WX		 14377 .suspend = bnx2x_suspend,
14378 .resume = bnx2x_resume,
14379 .err_handler = &bnx2x_err_handler,
3c76feff
AE		 14380#ifdef CONFIG_BNX2X_SRIOV
14381 .sriov_configure = bnx2x_sriov_configure,
14382#endif
b030ed2f 14383 .shutdown = bnx2x_shutdown,
a2fbb9ea
ET		 14384};
14385
14386static int __init bnx2x_init(void)
14387{
dd21ca6d
SG		 14388 int ret;
14389
7995c64e 14390 pr_info("%s", version);
938cf541 14391
1cf167f2
EG		 14392 bnx2x_wq = create_singlethread_workqueue("bnx2x");
14393 if (bnx2x_wq == NULL) {
7995c64e 14394 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 14395 return -ENOMEM;
14396 }
370d4a26
YM		 14397 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14398 if (!bnx2x_iov_wq) {
14399 pr_err("Cannot create iov workqueue\n");
14400 destroy_workqueue(bnx2x_wq);
14401 return -ENOMEM;
14402 }
1cf167f2 14403
dd21ca6d
SG		 14404 ret = pci_register_driver(&bnx2x_pci_driver);
14405 if (ret) {
7995c64e 14406 pr_err("Cannot register driver\n");
dd21ca6d 14407 destroy_workqueue(bnx2x_wq);
370d4a26 14408 destroy_workqueue(bnx2x_iov_wq);
dd21ca6d
SG		 14409 }
14410 return ret;
a2fbb9ea
ET		 14411}
14412
14413static void __exit bnx2x_cleanup(void)
14414{
452427b0 14415 struct list_head *pos, *q;
d76a6111 14416
a2fbb9ea 14417 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 14418
14419 destroy_workqueue(bnx2x_wq);
370d4a26 14420 destroy_workqueue(bnx2x_iov_wq);
452427b0 14421
16a5fd92 14422 /* Free globally allocated resources */
452427b0
YM		 14423 list_for_each_safe(pos, q, &bnx2x_prev_list) {
14424 struct bnx2x_prev_path_list *tmp =
14425 list_entry(pos, struct bnx2x_prev_path_list, list);
14426 list_del(pos);
14427 kfree(tmp);
14428 }
a2fbb9ea
ET		 14429}
14430
3deb8167
YR		 14431void bnx2x_notify_link_changed(struct bnx2x *bp)
14432{
14433 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14434}
14435
a2fbb9ea
ET		 14436module_init(bnx2x_init);
14437module_exit(bnx2x_cleanup);
14438
619c5cb6
VZ		 14439/**
14440 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14441 *
14442 * @bp: driver handle
14443 * @set: set or clear the CAM entry
14444 *
16a5fd92 14445 * This function will wait until the ramrod completion returns.
619c5cb6
VZ		 14446 * Return 0 if success, -ENODEV if ramrod doesn't return.
14447 */
1191cb83 14448static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 14449{
14450 unsigned long ramrod_flags = 0;
14451
14452 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14453 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14454 &bp->iscsi_l2_mac_obj, true,
14455 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14456}
993ac7b5
MC		 14457
14458/* count denotes the number of new completions we have seen */
14459static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14460{
14461 struct eth_spe *spe;
a052997e 14462 int cxt_index, cxt_offset;
993ac7b5
MC		 14463
14464#ifdef BNX2X_STOP_ON_ERROR
14465 if (unlikely(bp->panic))
14466 return;
14467#endif
14468
14469 spin_lock_bh(&bp->spq_lock);
c2bff63f 14470 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 14471 bp->cnic_spq_pending -= count;
14472
c2bff63f
DK		 14473 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14474 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14475 & SPE_HDR_CONN_TYPE) >>
14476 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 14477 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14478 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 14479
14480 /* Set validation for iSCSI L2 client before sending SETUP
14481 * ramrod
14482 */
14483 if (type == ETH_CONNECTION_TYPE) {
a052997e 14484 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 14485 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 14486 ILT_PAGE_CIDS;
37ae41a9 14487 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 14488 (cxt_index * ILT_PAGE_CIDS);
14489 bnx2x_set_ctx_validation(bp,
14490 &bp->context[cxt_index].
14491 vcxt[cxt_offset].eth,
37ae41a9 14492 BNX2X_ISCSI_ETH_CID(bp));
a052997e 14493 }
c2bff63f
DK		 14494 }
14495
619c5cb6
VZ		 14496 /*
14497 * There may be not more than 8 L2, not more than 8 L5 SPEs
14498 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 14499 * COMMON ramrods is not more than the EQ and SPQ can
14500 * accommodate.
c2bff63f 14501 */
6e30dd4e
VZ		 14502 if (type == ETH_CONNECTION_TYPE) {
14503 if (!atomic_read(&bp->cq_spq_left))
14504 break;
14505 else
14506 atomic_dec(&bp->cq_spq_left);
14507 } else if (type == NONE_CONNECTION_TYPE) {
14508 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 14509 break;
14510 else
6e30dd4e 14511 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 14512 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14513 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 14514 if (bp->cnic_spq_pending >=
14515 bp->cnic_eth_dev.max_kwqe_pending)
14516 break;
14517 else
14518 bp->cnic_spq_pending++;
14519 } else {
14520 BNX2X_ERR("Unknown SPE type: %d\n", type);
14521 bnx2x_panic();
993ac7b5 14522 break;
c2bff63f 14523 }
993ac7b5
MC		 14524
14525 spe = bnx2x_sp_get_next(bp);
14526 *spe = *bp->cnic_kwq_cons;
14527
51c1a580 14528 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 14529 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14530
14531 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14532 bp->cnic_kwq_cons = bp->cnic_kwq;
14533 else
14534 bp->cnic_kwq_cons++;
14535 }
14536 bnx2x_sp_prod_update(bp);
14537 spin_unlock_bh(&bp->spq_lock);
14538}
14539
14540static int bnx2x_cnic_sp_queue(struct net_device *dev,
14541 struct kwqe_16 *kwqes[], u32 count)
14542{
14543 struct bnx2x *bp = netdev_priv(dev);
14544 int i;
14545
14546#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 14547 if (unlikely(bp->panic)) {
14548 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 14549 return -EIO;
51c1a580 14550 }
993ac7b5
MC		 14551#endif
14552
95c6c616
AE		 14553 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14554 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 14555 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 14556 return -EAGAIN;
14557 }
14558
993ac7b5
MC		 14559 spin_lock_bh(&bp->spq_lock);
14560
14561 for (i = 0; i < count; i++) {
14562 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14563
14564 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14565 break;
14566
14567 *bp->cnic_kwq_prod = *spe;
14568
14569 bp->cnic_kwq_pending++;
14570
51c1a580 14571 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 14572 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 14573 spe->data.update_data_addr.hi,
14574 spe->data.update_data_addr.lo,
993ac7b5
MC		 14575 bp->cnic_kwq_pending);
14576
14577 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14578 bp->cnic_kwq_prod = bp->cnic_kwq;
14579 else
14580 bp->cnic_kwq_prod++;
14581 }
14582
14583 spin_unlock_bh(&bp->spq_lock);
14584
14585 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14586 bnx2x_cnic_sp_post(bp, 0);
14587
14588 return i;
14589}
14590
14591static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14592{
14593 struct cnic_ops *c_ops;
14594 int rc = 0;
14595
14596 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 14597 c_ops = rcu_dereference_protected(bp->cnic_ops,
14598 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 14599 if (c_ops)
14600 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14601 mutex_unlock(&bp->cnic_mutex);
14602
14603 return rc;
14604}
14605
14606static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14607{
14608 struct cnic_ops *c_ops;
14609 int rc = 0;
14610
14611 rcu_read_lock();
14612 c_ops = rcu_dereference(bp->cnic_ops);
14613 if (c_ops)
14614 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14615 rcu_read_unlock();
14616
14617 return rc;
14618}
14619
14620/*
14621 * for commands that have no data
14622 */
9f6c9258 14623int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 14624{
14625 struct cnic_ctl_info ctl = {0};
14626
14627 ctl.cmd = cmd;
14628
14629 return bnx2x_cnic_ctl_send(bp, &ctl);
14630}
14631
619c5cb6 14632static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 14633{
619c5cb6 14634 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 14635
14636 /* first we tell CNIC and only then we count this as a completion */
14637 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14638 ctl.data.comp.cid = cid;
619c5cb6 14639 ctl.data.comp.error = err;
993ac7b5
MC		 14640
14641 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 14642 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 14643}
14644
619c5cb6
VZ		 14645/* Called with netif_addr_lock_bh() taken.
14646 * Sets an rx_mode config for an iSCSI ETH client.
14647 * Doesn't block.
14648 * Completion should be checked outside.
14649 */
14650static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14651{
14652 unsigned long accept_flags = 0, ramrod_flags = 0;
14653 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14654 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14655
14656 if (start) {
14657 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14658 * because it's the only way for UIO Queue to accept
14659 * multicasts (in non-promiscuous mode only one Queue per
14660 * function will receive multicast packets (leading in our
14661 * case).
14662 */
14663 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14664 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14665 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14666 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14667
14668 /* Clear STOP_PENDING bit if START is requested */
14669 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14670
14671 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14672 } else
14673 /* Clear START_PENDING bit if STOP is requested */
14674 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14675
14676 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14677 set_bit(sched_state, &bp->sp_state);
14678 else {
14679 __set_bit(RAMROD_RX, &ramrod_flags);
14680 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14681 ramrod_flags);
14682 }
14683}
14684
993ac7b5
MC		 14685static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14686{
14687 struct bnx2x *bp = netdev_priv(dev);
14688 int rc = 0;
14689
14690 switch (ctl->cmd) {
14691 case DRV_CTL_CTXTBL_WR_CMD: {
14692 u32 index = ctl->data.io.offset;
14693 dma_addr_t addr = ctl->data.io.dma_addr;
14694
14695 bnx2x_ilt_wr(bp, index, addr);
14696 break;
14697 }
14698
c2bff63f
DK		 14699 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14700 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 14701
14702 bnx2x_cnic_sp_post(bp, count);
14703 break;
14704 }
14705
14706 /* rtnl_lock is held. */
14707 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 14708 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14709 unsigned long sp_bits = 0;
14710
14711 /* Configure the iSCSI classification object */
14712 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14713 cp->iscsi_l2_client_id,
14714 cp->iscsi_l2_cid, BP_FUNC(bp),
14715 bnx2x_sp(bp, mac_rdata),
14716 bnx2x_sp_mapping(bp, mac_rdata),
14717 BNX2X_FILTER_MAC_PENDING,
14718 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14719 &bp->macs_pool);
ec6ba945 14720
523224a3 14721 /* Set iSCSI MAC address */
619c5cb6
VZ		 14722 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14723 if (rc)
14724 break;
523224a3
DK		 14725
14726 mmiowb();
14727 barrier();
14728
619c5cb6
VZ		 14729 /* Start accepting on iSCSI L2 ring */
14730
14731 netif_addr_lock_bh(dev);
14732 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14733 netif_addr_unlock_bh(dev);
14734
14735 /* bits to wait on */
14736 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14737 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14738
14739 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14740 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 14741
993ac7b5
MC		 14742 break;
14743 }
14744
14745 /* rtnl_lock is held. */
14746 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 14747 unsigned long sp_bits = 0;
993ac7b5 14748
523224a3 14749 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 14750 netif_addr_lock_bh(dev);
14751 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14752 netif_addr_unlock_bh(dev);
14753
14754 /* bits to wait on */
14755 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14756 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14757
14758 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14759 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 14760
14761 mmiowb();
14762 barrier();
14763
14764 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 14765 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14766 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 14767 break;
14768 }
c2bff63f
DK		 14769 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14770 int count = ctl->data.credit.credit_count;
14771
4e857c58 14772 smp_mb__before_atomic();
6e30dd4e 14773 atomic_add(count, &bp->cq_spq_left);
4e857c58 14774 smp_mb__after_atomic();
c2bff63f
DK		 14775 break;
14776 }
1d187b34 14777 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 14778 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 14779
14780 if (CHIP_IS_E3(bp)) {
14781 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 14782 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14783 int path = BP_PATH(bp);
14784 int port = BP_PORT(bp);
14785 int i;
14786 u32 scratch_offset;
14787 u32 *host_addr;
1d187b34 14788
2e499d3c 14789 /* first write capability to shmem2 */
1d187b34
BW		 14790 if (ulp_type == CNIC_ULP_ISCSI)
14791 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14792 else if (ulp_type == CNIC_ULP_FCOE)
14793 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14794 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 14795
14796 if ((ulp_type != CNIC_ULP_FCOE) ||
14797 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14798 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14799 break;
14800
14801 /* if reached here - should write fcoe capabilities */
14802 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14803 if (!scratch_offset)
14804 break;
14805 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14806 fcoe_features[path][port]);
14807 host_addr = (u32 *) &(ctl->data.register_data.
14808 fcoe_features);
14809 for (i = 0; i < sizeof(struct fcoe_capabilities);
14810 i += 4)
14811 REG_WR(bp, scratch_offset + i,
14812 *(host_addr + i/4));
1d187b34 14813 }
42f8277f 14814 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14815 break;
14816 }
2e499d3c 14817
1d187b34
BW		 14818 case DRV_CTL_ULP_UNREGISTER_CMD: {
14819 int ulp_type = ctl->data.ulp_type;
14820
14821 if (CHIP_IS_E3(bp)) {
14822 int idx = BP_FW_MB_IDX(bp);
14823 u32 cap;
14824
14825 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14826 if (ulp_type == CNIC_ULP_ISCSI)
14827 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14828 else if (ulp_type == CNIC_ULP_FCOE)
14829 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14830 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14831 }
42f8277f 14832 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14833 break;
14834 }
993ac7b5
MC		 14835
14836 default:
14837 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14838 rc = -EINVAL;
14839 }
14840
97ac4ef7
YM		 14841 /* For storage-only interfaces, change driver state */
14842 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14843 switch (ctl->drv_state) {
14844 case DRV_NOP:
14845 break;
14846 case DRV_ACTIVE:
14847 bnx2x_set_os_driver_state(bp,
14848 OS_DRIVER_STATE_ACTIVE);
14849 break;
14850 case DRV_INACTIVE:
14851 bnx2x_set_os_driver_state(bp,
14852 OS_DRIVER_STATE_DISABLED);
14853 break;
14854 case DRV_UNLOADED:
14855 bnx2x_set_os_driver_state(bp,
14856 OS_DRIVER_STATE_NOT_LOADED);
14857 break;
14858 default:
14859 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14860 }
14861 }
14862
14863 return rc;
14864}
14865
14866static int bnx2x_get_fc_npiv(struct net_device *dev,
14867 struct cnic_fc_npiv_tbl *cnic_tbl)
14868{
14869 struct bnx2x *bp = netdev_priv(dev);
14870 struct bdn_fc_npiv_tbl *tbl = NULL;
14871 u32 offset, entries;
14872 int rc = -EINVAL;
14873 int i;
14874
14875 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14876 goto out;
14877
14878 DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14879
14880 tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14881 if (!tbl) {
14882 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14883 goto out;
14884 }
14885
14886 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
1e6bb1a3
YM		 14887 if (!offset) {
14888 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n");
14889 goto out;
14890 }
97ac4ef7
YM		 14891 DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14892
14893 /* Read the table contents from nvram */
14894 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14895 BNX2X_ERR("Failed to read FC-NPIV table\n");
14896 goto out;
14897 }
14898
14899 /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14900 * the number of entries back to cpu endianness.
14901 */
14902 entries = tbl->fc_npiv_cfg.num_of_npiv;
14903 entries = (__force u32)be32_to_cpu((__force __be32)entries);
14904 tbl->fc_npiv_cfg.num_of_npiv = entries;
14905
14906 if (!tbl->fc_npiv_cfg.num_of_npiv) {
14907 DP(BNX2X_MSG_MCP,
14908 "No FC-NPIV table [valid, simply not present]\n");
14909 goto out;
14910 } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14911 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14912 tbl->fc_npiv_cfg.num_of_npiv);
14913 goto out;
14914 } else {
14915 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
14916 tbl->fc_npiv_cfg.num_of_npiv);
14917 }
14918
14919 /* Copy the data into cnic-provided struct */
14920 cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
14921 for (i = 0; i < cnic_tbl->count; i++) {
14922 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
14923 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
14924 }
14925
14926 rc = 0;
14927out:
14928 kfree(tbl);
993ac7b5
MC		 14929 return rc;
14930}
14931
9f6c9258 14932void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 14933{
14934 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14935
14936 if (bp->flags & USING_MSIX_FLAG) {
14937 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14938 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14939 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14940 } else {
14941 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14942 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14943 }
619c5cb6 14944 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 14945 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14946 else
14947 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14948
619c5cb6
VZ		 14949 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
14950 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 14951 cp->irq_arr[1].status_blk = bp->def_status_blk;
14952 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 14953 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 14954
14955 cp->num_irq = 2;
14956}
14957
37ae41a9
MS		 14958void bnx2x_setup_cnic_info(struct bnx2x *bp)
14959{
14960 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14961
37ae41a9
MS		 14962 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14963 bnx2x_cid_ilt_lines(bp);
14964 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14965 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14966 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14967
f78afb35
MC		 14968 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14969 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14970 cp->iscsi_l2_cid);
14971
37ae41a9
MS		 14972 if (NO_ISCSI_OOO(bp))
14973 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14974}
14975
993ac7b5
MC		 14976static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14977 void *data)
14978{
14979 struct bnx2x *bp = netdev_priv(dev);
14980 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 14981 int rc;
14982
14983 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 14984
51c1a580
MS		 14985 if (ops == NULL) {
14986 BNX2X_ERR("NULL ops received\n");
993ac7b5 14987 return -EINVAL;
51c1a580 14988 }
993ac7b5 14989
55c11941
MS		 14990 if (!CNIC_SUPPORT(bp)) {
14991 BNX2X_ERR("Can't register CNIC when not supported\n");
14992 return -EOPNOTSUPP;
14993 }
14994
14995 if (!CNIC_LOADED(bp)) {
14996 rc = bnx2x_load_cnic(bp);
14997 if (rc) {
14998 BNX2X_ERR("CNIC-related load failed\n");
14999 return rc;
15000 }
55c11941
MS		 15001 }
15002
15003 bp->cnic_enabled = true;
15004
993ac7b5
MC		 15005 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
15006 if (!bp->cnic_kwq)
15007 return -ENOMEM;
15008
15009 bp->cnic_kwq_cons = bp->cnic_kwq;
15010 bp->cnic_kwq_prod = bp->cnic_kwq;
15011 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
15012
15013 bp->cnic_spq_pending = 0;
15014 bp->cnic_kwq_pending = 0;
15015
15016 bp->cnic_data = data;
15017
15018 cp->num_irq = 0;
619c5cb6 15019 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 15020 cp->iro_arr = bp->iro_arr;
993ac7b5 15021
993ac7b5 15022 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 15023
993ac7b5
MC		 15024 rcu_assign_pointer(bp->cnic_ops, ops);
15025
42f8277f
YM		 15026 /* Schedule driver to read CNIC driver versions */
15027 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
15028
993ac7b5
MC		 15029 return 0;
15030}
15031
15032static int bnx2x_unregister_cnic(struct net_device *dev)
15033{
15034 struct bnx2x *bp = netdev_priv(dev);
15035 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15036
15037 mutex_lock(&bp->cnic_mutex);
993ac7b5 15038 cp->drv_state = 0;
2cfa5a04 15039 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 15040 mutex_unlock(&bp->cnic_mutex);
15041 synchronize_rcu();
fea75645 15042 bp->cnic_enabled = false;
993ac7b5
MC		 15043 kfree(bp->cnic_kwq);
15044 bp->cnic_kwq = NULL;
15045
15046 return 0;
15047}
15048
a8f47eb7 15049static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
993ac7b5
MC		 15050{
15051 struct bnx2x *bp = netdev_priv(dev);
15052 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15053
2ba45142
VZ		 15054 /* If both iSCSI and FCoE are disabled - return NULL in
15055 * order to indicate CNIC that it should not try to work
15056 * with this device.
15057 */
15058 if (NO_ISCSI(bp) && NO_FCOE(bp))
15059 return NULL;
15060
993ac7b5
MC		 15061 cp->drv_owner = THIS_MODULE;
15062 cp->chip_id = CHIP_ID(bp);
15063 cp->pdev = bp->pdev;
15064 cp->io_base = bp->regview;
15065 cp->io_base2 = bp->doorbells;
15066 cp->max_kwqe_pending = 8;
523224a3 15067 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 15068 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15069 bnx2x_cid_ilt_lines(bp);
993ac7b5 15070 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 15071 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 15072 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
15073 cp->drv_ctl = bnx2x_drv_ctl;
97ac4ef7 15074 cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
993ac7b5
MC		 15075 cp->drv_register_cnic = bnx2x_register_cnic;
15076 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 15077 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 15078 cp->iscsi_l2_client_id =
15079 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 15080 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 15081
2ba45142
VZ		 15082 if (NO_ISCSI_OOO(bp))
15083 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15084
15085 if (NO_ISCSI(bp))
15086 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15087
15088 if (NO_FCOE(bp))
15089 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15090
51c1a580
MS		 15091 BNX2X_DEV_INFO(
15092 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 15093 cp->ctx_blk_size,
15094 cp->ctx_tbl_offset,
15095 cp->ctx_tbl_len,
15096 cp->starting_cid);
993ac7b5
MC		 15097 return cp;
15098}
993ac7b5 15099
a8f47eb7 15100static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
9b176b6b 15101{
6411280a
AE		 15102 struct bnx2x *bp = fp->bp;
15103 u32 offset = BAR_USTRORM_INTMEM;
abc5a021 15104
6411280a
AE		 15105 if (IS_VF(bp))
15106 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15107 else if (!CHIP_IS_E1x(bp))
15108 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15109 else
15110 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
8d9ac297 15111
6411280a 15112 return offset;
8d9ac297 15113}
381ac16b 15114
6411280a
AE		 15115/* called only on E1H or E2.
15116 * When pretending to be PF, the pretend value is the function number 0...7
15117 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15118 * combination
15119 */
15120int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
381ac16b 15121{
6411280a 15122 u32 pretend_reg;
381ac16b 15123
23826850 15124 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
6411280a 15125 return -1;
381ac16b 15126
6411280a
AE		 15127 /* get my own pretend register */
15128 pretend_reg = bnx2x_get_pretend_reg(bp);
15129 REG_WR(bp, pretend_reg, pretend_func_val);
15130 REG_RD(bp, pretend_reg);
381ac16b
AE		 15131 return 0;
15132}
eeed018c
MK		 15133
15134static void bnx2x_ptp_task(struct work_struct *work)
15135{
15136 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15137 int port = BP_PORT(bp);
15138 u32 val_seq;
15139 u64 timestamp, ns;
15140 struct skb_shared_hwtstamps shhwtstamps;
15141
15142 /* Read Tx timestamp registers */
15143 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15144 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15145 if (val_seq & 0x10000) {
15146 /* There is a valid timestamp value */
15147 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15148 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15149 timestamp <<= 32;
15150 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15151 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15152 /* Reset timestamp register to allow new timestamp */
15153 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15154 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15155 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15156
15157 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15158 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15159 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15160 dev_kfree_skb_any(bp->ptp_tx_skb);
15161 bp->ptp_tx_skb = NULL;
15162
15163 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15164 timestamp, ns);
15165 } else {
15166 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
15167 /* Reschedule to keep checking for a valid timestamp value */
15168 schedule_work(&bp->ptp_task);
15169 }
15170}
15171
15172void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15173{
15174 int port = BP_PORT(bp);
15175 u64 timestamp, ns;
15176
15177 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15178 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15179 timestamp <<= 32;
15180 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15181 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15182
15183 /* Reset timestamp register to allow new timestamp */
15184 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15185 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15186
15187 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15188
15189 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15190
15191 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15192 timestamp, ns);
15193}
15194
15195/* Read the PHC */
15196static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15197{
15198 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15199 int port = BP_PORT(bp);
15200 u32 wb_data[2];
15201 u64 phc_cycles;
15202
15203 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15204 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15205 phc_cycles = wb_data[1];
15206 phc_cycles = (phc_cycles << 32) + wb_data[0];
15207
15208 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15209
15210 return phc_cycles;
15211}
15212
15213static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15214{
15215 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15216 bp->cyclecounter.read = bnx2x_cyclecounter_read;
f28ba401 15217 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
eeed018c
MK		 15218 bp->cyclecounter.shift = 1;
15219 bp->cyclecounter.mult = 1;
15220}
15221
15222static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15223{
15224 struct bnx2x_func_state_params func_params = {NULL};
15225 struct bnx2x_func_set_timesync_params *set_timesync_params =
15226 &func_params.params.set_timesync;
15227
15228 /* Prepare parameters for function state transitions */
15229 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15230 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15231
15232 func_params.f_obj = &bp->func_obj;
15233 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15234
15235 /* Function parameters */
15236 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15237 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15238
15239 return bnx2x_func_state_change(bp, &func_params);
15240}
15241
1444c301 15242static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
eeed018c
MK		 15243{
15244 struct bnx2x_queue_state_params q_params;
15245 int rc, i;
15246
15247 /* send queue update ramrod to enable PTP packets */
15248 memset(&q_params, 0, sizeof(q_params));
15249 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15250 q_params.cmd = BNX2X_Q_CMD_UPDATE;
15251 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15252 &q_params.params.update.update_flags);
15253 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15254 &q_params.params.update.update_flags);
15255
15256 /* send the ramrod on all the queues of the PF */
15257 for_each_eth_queue(bp, i) {
15258 struct bnx2x_fastpath *fp = &bp->fp[i];
15259
15260 /* Set the appropriate Queue object */
15261 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15262
15263 /* Update the Queue state */
15264 rc = bnx2x_queue_state_change(bp, &q_params);
15265 if (rc) {
15266 BNX2X_ERR("Failed to enable PTP packets\n");
15267 return rc;
15268 }
15269 }
15270
15271 return 0;
15272}
15273
15274int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15275{
15276 int port = BP_PORT(bp);
15277 int rc;
15278
15279 if (!bp->hwtstamp_ioctl_called)
15280 return 0;
15281
15282 switch (bp->tx_type) {
15283 case HWTSTAMP_TX_ON:
15284 bp->flags |= TX_TIMESTAMPING_EN;
15285 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15286 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15287 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15288 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15289 break;
15290 case HWTSTAMP_TX_ONESTEP_SYNC:
15291 BNX2X_ERR("One-step timestamping is not supported\n");
15292 return -ERANGE;
15293 }
15294
15295 switch (bp->rx_filter) {
15296 case HWTSTAMP_FILTER_NONE:
15297 break;
15298 case HWTSTAMP_FILTER_ALL:
15299 case HWTSTAMP_FILTER_SOME:
15300 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15301 break;
15302 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15303 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15304 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15305 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15306 /* Initialize PTP detection for UDP/IPv4 events */
15307 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15308 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15309 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15310 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15311 break;
15312 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15313 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15314 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15315 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15316 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15317 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15318 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15319 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15320 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15321 break;
15322 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15323 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15324 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15325 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15326 /* Initialize PTP detection L2 events */
15327 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15328 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15329 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15330 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15331
15332 break;
15333 case HWTSTAMP_FILTER_PTP_V2_EVENT:
15334 case HWTSTAMP_FILTER_PTP_V2_SYNC:
15335 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15336 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15337 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15338 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15339 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15340 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15341 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15342 break;
15343 }
15344
15345 /* Indicate to FW that this PF expects recorded PTP packets */
15346 rc = bnx2x_enable_ptp_packets(bp);
15347 if (rc)
15348 return rc;
15349
15350 /* Enable sending PTP packets to host */
15351 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15352 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15353
15354 return 0;
15355}
15356
15357static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15358{
15359 struct hwtstamp_config config;
15360 int rc;
15361
15362 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15363
15364 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15365 return -EFAULT;
15366
15367 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15368 config.tx_type, config.rx_filter);
15369
15370 if (config.flags) {
15371 BNX2X_ERR("config.flags is reserved for future use\n");
15372 return -EINVAL;
15373 }
15374
15375 bp->hwtstamp_ioctl_called = 1;
15376 bp->tx_type = config.tx_type;
15377 bp->rx_filter = config.rx_filter;
15378
15379 rc = bnx2x_configure_ptp_filters(bp);
15380 if (rc)
15381 return rc;
15382
15383 config.rx_filter = bp->rx_filter;
15384
15385 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15386 -EFAULT : 0;
15387}
15388
bf27c353 15389/* Configures HW for PTP */
eeed018c
MK		 15390static int bnx2x_configure_ptp(struct bnx2x *bp)
15391{
15392 int rc, port = BP_PORT(bp);
15393 u32 wb_data[2];
15394
15395 /* Reset PTP event detection rules - will be configured in the IOCTL */
15396 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15397 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15398 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15399 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15400 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15401 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15402 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15403 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15404
15405 /* Disable PTP packets to host - will be configured in the IOCTL*/
15406 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15407 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15408
15409 /* Enable the PTP feature */
15410 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15411 NIG_REG_P0_PTP_EN, 0x3F);
15412
15413 /* Enable the free-running counter */
15414 wb_data[0] = 0;
15415 wb_data[1] = 0;
15416 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15417
15418 /* Reset drift register (offset register is not reset) */
15419 rc = bnx2x_send_reset_timesync_ramrod(bp);
15420 if (rc) {
15421 BNX2X_ERR("Failed to reset PHC drift register\n");
15422 return -EFAULT;
15423 }
15424
15425 /* Reset possibly old timestamps */
15426 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15427 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15428 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15429 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15430
15431 return 0;
15432}
15433
15434/* Called during load, to initialize PTP-related stuff */
15435void bnx2x_init_ptp(struct bnx2x *bp)
15436{
15437 int rc;
15438
15439 /* Configure PTP in HW */
15440 rc = bnx2x_configure_ptp(bp);
15441 if (rc) {
15442 BNX2X_ERR("Stopping PTP initialization\n");
15443 return;
15444 }
15445
15446 /* Init work queue for Tx timestamping */
15447 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15448
15449 /* Init cyclecounter and timecounter. This is done only in the first
15450 * load. If done in every load, PTP application will fail when doing
15451 * unload / load (e.g. MTU change) while it is running.
15452 */
15453 if (!bp->timecounter_init_done) {
15454 bnx2x_init_cyclecounter(bp);
15455 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15456 ktime_to_ns(ktime_get_real()));
15457 bp->timecounter_init_done = 1;
15458 }
15459
15460 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
15461}
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