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Commit | Line | Data |
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4ad79e13 | 1 | /* bnx2x_main.c: QLogic Everest network driver. |
a2fbb9ea | 2 | * |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
4ad79e13 YM |
4 | * Copyright (c) 2014 QLogic Corporation |
5 | * All rights reserved | |
a2fbb9ea ET |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
08f6dd89 | 11 | * Maintained by: Ariel Elior <ariel.elior@qlogic.com> |
24e3fcef | 12 | * Written by: Eliezer Tamir |
a2fbb9ea ET |
13 | * Based on code from Michael Chan's bnx2 driver |
14 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 15 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 16 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
17 | * |
18 | */ | |
19 | ||
f1deab50 JP |
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
21 | ||
a2fbb9ea ET |
22 | #include <linux/module.h> |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/device.h> /* for dev_info() */ | |
26 | #include <linux/timer.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/slab.h> | |
a2fbb9ea ET |
30 | #include <linux/interrupt.h> |
31 | #include <linux/pci.h> | |
33d8e6a5 | 32 | #include <linux/aer.h> |
a2fbb9ea ET |
33 | #include <linux/init.h> |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/etherdevice.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/dma-mapping.h> | |
38 | #include <linux/bitops.h> | |
39 | #include <linux/irq.h> | |
40 | #include <linux/delay.h> | |
41 | #include <asm/byteorder.h> | |
42 | #include <linux/time.h> | |
43 | #include <linux/ethtool.h> | |
44 | #include <linux/mii.h> | |
0c6671b0 | 45 | #include <linux/if_vlan.h> |
c9931896 | 46 | #include <linux/crash_dump.h> |
a2fbb9ea | 47 | #include <net/ip.h> |
619c5cb6 | 48 | #include <net/ipv6.h> |
a2fbb9ea | 49 | #include <net/tcp.h> |
51de7bb9 | 50 | #include <net/vxlan.h> |
a2fbb9ea | 51 | #include <net/checksum.h> |
34f80b04 | 52 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
53 | #include <linux/workqueue.h> |
54 | #include <linux/crc32.h> | |
34f80b04 | 55 | #include <linux/crc32c.h> |
a2fbb9ea ET |
56 | #include <linux/prefetch.h> |
57 | #include <linux/zlib.h> | |
a2fbb9ea | 58 | #include <linux/io.h> |
452427b0 | 59 | #include <linux/semaphore.h> |
45229b42 | 60 | #include <linux/stringify.h> |
7ab24bfd | 61 | #include <linux/vmalloc.h> |
883ce97d YM |
62 | #if IS_ENABLED(CONFIG_GENEVE) |
63 | #include <net/geneve.h> | |
64 | #endif | |
a2fbb9ea ET |
65 | #include "bnx2x.h" |
66 | #include "bnx2x_init.h" | |
94a78b79 | 67 | #include "bnx2x_init_ops.h" |
9f6c9258 | 68 | #include "bnx2x_cmn.h" |
1ab4434c | 69 | #include "bnx2x_vfpf.h" |
e4901dde | 70 | #include "bnx2x_dcb.h" |
042181f5 | 71 | #include "bnx2x_sp.h" |
94a78b79 VZ |
72 | #include <linux/firmware.h> |
73 | #include "bnx2x_fw_file_hdr.h" | |
74 | /* FW files */ | |
45229b42 BH |
75 | #define FW_FILE_VERSION \ |
76 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
77 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
78 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
79 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
80 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
81 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 82 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 83 | |
34f80b04 EG |
84 | /* Time in jiffies before concluding the transmitter is hung */ |
85 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 86 | |
0329aba1 | 87 | static char version[] = |
4ad79e13 | 88 | "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
89 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
90 | ||
24e3fcef | 91 | MODULE_AUTHOR("Eliezer Tamir"); |
4ad79e13 | 92 | MODULE_DESCRIPTION("QLogic " |
619c5cb6 VZ |
93 | "BCM57710/57711/57711E/" |
94 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
95 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
96 | MODULE_LICENSE("GPL"); |
97 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
98 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
99 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 100 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 101 | |
a8f47eb7 | 102 | int bnx2x_num_queues; |
1c8bb760 | 103 | module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO); |
96305234 DK |
104 | MODULE_PARM_DESC(num_queues, |
105 | " Set number of queues (default is as a number of CPUs)"); | |
555f6c78 | 106 | |
19680c48 | 107 | static int disable_tpa; |
1c8bb760 | 108 | module_param(disable_tpa, int, S_IRUGO); |
9898f86d | 109 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 110 | |
a8f47eb7 | 111 | static int int_mode; |
1c8bb760 | 112 | module_param(int_mode, int, S_IRUGO); |
619c5cb6 | 113 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 114 | "(1 INT#x; 2 MSI)"); |
8badd27a | 115 | |
a18f5128 | 116 | static int dropless_fc; |
1c8bb760 | 117 | module_param(dropless_fc, int, S_IRUGO); |
a18f5128 EG |
118 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); |
119 | ||
8d5726c4 | 120 | static int mrrs = -1; |
1c8bb760 | 121 | module_param(mrrs, int, S_IRUGO); |
8d5726c4 EG |
122 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); |
123 | ||
9898f86d | 124 | static int debug; |
1c8bb760 | 125 | module_param(debug, int, S_IRUGO); |
9898f86d EG |
126 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
127 | ||
370d4a26 YM |
128 | static struct workqueue_struct *bnx2x_wq; |
129 | struct workqueue_struct *bnx2x_iov_wq; | |
ec6ba945 | 130 | |
1ef1d45a BW |
131 | struct bnx2x_mac_vals { |
132 | u32 xmac_addr; | |
133 | u32 xmac_val; | |
134 | u32 emac_addr; | |
135 | u32 emac_val; | |
3d6b7253 YM |
136 | u32 umac_addr[2]; |
137 | u32 umac_val[2]; | |
1ef1d45a BW |
138 | u32 bmac_addr; |
139 | u32 bmac_val[2]; | |
140 | }; | |
141 | ||
a2fbb9ea ET |
142 | enum bnx2x_board_type { |
143 | BCM57710 = 0, | |
619c5cb6 VZ |
144 | BCM57711, |
145 | BCM57711E, | |
146 | BCM57712, | |
147 | BCM57712_MF, | |
1ab4434c | 148 | BCM57712_VF, |
619c5cb6 VZ |
149 | BCM57800, |
150 | BCM57800_MF, | |
1ab4434c | 151 | BCM57800_VF, |
619c5cb6 VZ |
152 | BCM57810, |
153 | BCM57810_MF, | |
1ab4434c | 154 | BCM57810_VF, |
c3def943 YM |
155 | BCM57840_4_10, |
156 | BCM57840_2_20, | |
7e8e02df | 157 | BCM57840_MF, |
1ab4434c | 158 | BCM57840_VF, |
7e8e02df | 159 | BCM57811, |
1ab4434c AE |
160 | BCM57811_MF, |
161 | BCM57840_O, | |
162 | BCM57840_MFO, | |
163 | BCM57811_VF | |
a2fbb9ea ET |
164 | }; |
165 | ||
34f80b04 | 166 | /* indexed by board_type, above */ |
53a10565 | 167 | static struct { |
a2fbb9ea | 168 | char *name; |
0329aba1 | 169 | } board_info[] = { |
4ad79e13 YM |
170 | [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" }, |
171 | [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" }, | |
172 | [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" }, | |
173 | [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" }, | |
174 | [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" }, | |
175 | [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" }, | |
176 | [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" }, | |
177 | [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" }, | |
178 | [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" }, | |
179 | [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" }, | |
180 | [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" }, | |
181 | [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" }, | |
182 | [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" }, | |
183 | [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" }, | |
184 | [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
185 | [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }, | |
186 | [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" }, | |
187 | [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" }, | |
188 | [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" }, | |
189 | [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
190 | [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" } | |
a2fbb9ea ET |
191 | }; |
192 | ||
619c5cb6 VZ |
193 | #ifndef PCI_DEVICE_ID_NX2_57710 |
194 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
195 | #endif | |
196 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
197 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
198 | #endif | |
199 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
200 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
201 | #endif | |
202 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
203 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
204 | #endif | |
205 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
206 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
207 | #endif | |
8395be5e AE |
208 | #ifndef PCI_DEVICE_ID_NX2_57712_VF |
209 | #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF | |
210 | #endif | |
619c5cb6 VZ |
211 | #ifndef PCI_DEVICE_ID_NX2_57800 |
212 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
213 | #endif | |
214 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
215 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
216 | #endif | |
8395be5e AE |
217 | #ifndef PCI_DEVICE_ID_NX2_57800_VF |
218 | #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF | |
219 | #endif | |
619c5cb6 VZ |
220 | #ifndef PCI_DEVICE_ID_NX2_57810 |
221 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
222 | #endif | |
223 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
224 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
225 | #endif | |
c3def943 YM |
226 | #ifndef PCI_DEVICE_ID_NX2_57840_O |
227 | #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE | |
228 | #endif | |
8395be5e AE |
229 | #ifndef PCI_DEVICE_ID_NX2_57810_VF |
230 | #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF | |
231 | #endif | |
c3def943 YM |
232 | #ifndef PCI_DEVICE_ID_NX2_57840_4_10 |
233 | #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 | |
234 | #endif | |
235 | #ifndef PCI_DEVICE_ID_NX2_57840_2_20 | |
236 | #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 | |
237 | #endif | |
238 | #ifndef PCI_DEVICE_ID_NX2_57840_MFO | |
239 | #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE | |
619c5cb6 VZ |
240 | #endif |
241 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
242 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
243 | #endif | |
8395be5e AE |
244 | #ifndef PCI_DEVICE_ID_NX2_57840_VF |
245 | #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF | |
246 | #endif | |
7e8e02df BW |
247 | #ifndef PCI_DEVICE_ID_NX2_57811 |
248 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 | |
249 | #endif | |
250 | #ifndef PCI_DEVICE_ID_NX2_57811_MF | |
251 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF | |
252 | #endif | |
8395be5e AE |
253 | #ifndef PCI_DEVICE_ID_NX2_57811_VF |
254 | #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF | |
255 | #endif | |
256 | ||
9baa3c34 | 257 | static const struct pci_device_id bnx2x_pci_tbl[] = { |
e4ed7113 EG |
258 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
259 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
260 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 261 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 | 262 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
8395be5e | 263 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, |
619c5cb6 VZ |
264 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, |
265 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
8395be5e | 266 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, |
619c5cb6 VZ |
267 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, |
268 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
c3def943 YM |
269 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, |
270 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, | |
9c9a6524 | 271 | { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, |
c3def943 | 272 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, |
8395be5e | 273 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, |
c3def943 | 274 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, |
619c5cb6 | 275 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, |
9c9a6524 | 276 | { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, |
8395be5e | 277 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, |
9c9a6524 | 278 | { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, |
7e8e02df BW |
279 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
280 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, | |
8395be5e | 281 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, |
a2fbb9ea ET |
282 | { 0 } |
283 | }; | |
284 | ||
285 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
286 | ||
452427b0 YM |
287 | /* Global resources for unloading a previously loaded device */ |
288 | #define BNX2X_PREV_WAIT_NEEDED 1 | |
289 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); | |
290 | static LIST_HEAD(bnx2x_prev_list); | |
a8f47eb7 | 291 | |
292 | /* Forward declaration */ | |
293 | static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); | |
294 | static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); | |
295 | static int bnx2x_set_storm_rx_mode(struct bnx2x *bp); | |
296 | ||
a2fbb9ea ET |
297 | /**************************************************************************** |
298 | * General service functions | |
299 | ****************************************************************************/ | |
300 | ||
eeed018c MK |
301 | static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr); |
302 | ||
1191cb83 | 303 | static void __storm_memset_dma_mapping(struct bnx2x *bp, |
619c5cb6 VZ |
304 | u32 addr, dma_addr_t mapping) |
305 | { | |
306 | REG_WR(bp, addr, U64_LO(mapping)); | |
307 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
308 | } | |
309 | ||
1191cb83 ED |
310 | static void storm_memset_spq_addr(struct bnx2x *bp, |
311 | dma_addr_t mapping, u16 abs_fid) | |
619c5cb6 VZ |
312 | { |
313 | u32 addr = XSEM_REG_FAST_MEMORY + | |
314 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
315 | ||
316 | __storm_memset_dma_mapping(bp, addr, mapping); | |
317 | } | |
318 | ||
1191cb83 ED |
319 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, |
320 | u16 pf_id) | |
523224a3 | 321 | { |
619c5cb6 VZ |
322 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
323 | pf_id); | |
324 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
325 | pf_id); | |
326 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
327 | pf_id); | |
328 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
329 | pf_id); | |
523224a3 DK |
330 | } |
331 | ||
1191cb83 ED |
332 | static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
333 | u8 enable) | |
619c5cb6 VZ |
334 | { |
335 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
336 | enable); | |
337 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
338 | enable); | |
339 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
340 | enable); | |
341 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
342 | enable); | |
343 | } | |
523224a3 | 344 | |
1191cb83 ED |
345 | static void storm_memset_eq_data(struct bnx2x *bp, |
346 | struct event_ring_data *eq_data, | |
523224a3 DK |
347 | u16 pfid) |
348 | { | |
349 | size_t size = sizeof(struct event_ring_data); | |
350 | ||
351 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
352 | ||
353 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
354 | } | |
355 | ||
1191cb83 ED |
356 | static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, |
357 | u16 pfid) | |
523224a3 DK |
358 | { |
359 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
360 | REG_WR16(bp, addr, eq_prod); | |
361 | } | |
362 | ||
a2fbb9ea ET |
363 | /* used only at init |
364 | * locking is done by mcp | |
365 | */ | |
8d96286a | 366 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
367 | { |
368 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
369 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
370 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
371 | PCICFG_VENDOR_ID_OFFSET); | |
372 | } | |
373 | ||
a2fbb9ea ET |
374 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
375 | { | |
376 | u32 val; | |
377 | ||
378 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
379 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
380 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
381 | PCICFG_VENDOR_ID_OFFSET); | |
382 | ||
383 | return val; | |
384 | } | |
a2fbb9ea | 385 | |
f2e0899f DK |
386 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
387 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
388 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
389 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
390 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
391 | ||
6bf07b8e YM |
392 | static void bnx2x_dp_dmae(struct bnx2x *bp, |
393 | struct dmae_command *dmae, int msglvl) | |
fd1fc79d AE |
394 | { |
395 | u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; | |
6bf07b8e | 396 | int i; |
fd1fc79d AE |
397 | |
398 | switch (dmae->opcode & DMAE_COMMAND_DST) { | |
399 | case DMAE_CMD_DST_PCI: | |
400 | if (src_type == DMAE_CMD_SRC_PCI) | |
401 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
402 | "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" | |
403 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
404 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
405 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
406 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
407 | dmae->comp_val); | |
408 | else | |
409 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
410 | "src [%08x], len [%d*4], dst [%x:%08x]\n" | |
411 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
412 | dmae->opcode, dmae->src_addr_lo >> 2, | |
413 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
414 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
415 | dmae->comp_val); | |
416 | break; | |
417 | case DMAE_CMD_DST_GRC: | |
418 | if (src_type == DMAE_CMD_SRC_PCI) | |
419 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
420 | "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" | |
421 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
422 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
423 | dmae->len, dmae->dst_addr_lo >> 2, | |
424 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
425 | dmae->comp_val); | |
426 | else | |
427 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
428 | "src [%08x], len [%d*4], dst [%08x]\n" | |
429 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
430 | dmae->opcode, dmae->src_addr_lo >> 2, | |
431 | dmae->len, dmae->dst_addr_lo >> 2, | |
432 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
433 | dmae->comp_val); | |
434 | break; | |
435 | default: | |
436 | if (src_type == DMAE_CMD_SRC_PCI) | |
437 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
438 | "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" | |
439 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
440 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
441 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
442 | dmae->comp_val); | |
443 | else | |
444 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
445 | "src_addr [%08x] len [%d * 4] dst_addr [none]\n" | |
446 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
447 | dmae->opcode, dmae->src_addr_lo >> 2, | |
448 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
449 | dmae->comp_val); | |
450 | break; | |
451 | } | |
6bf07b8e YM |
452 | |
453 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) | |
454 | DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", | |
455 | i, *(((u32 *)dmae) + i)); | |
fd1fc79d | 456 | } |
f2e0899f | 457 | |
a2fbb9ea | 458 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 459 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
460 | { |
461 | u32 cmd_offset; | |
462 | int i; | |
463 | ||
464 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
465 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
466 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
467 | } |
468 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
469 | } | |
470 | ||
f2e0899f | 471 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 472 | { |
f2e0899f DK |
473 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
474 | DMAE_CMD_C_ENABLE); | |
475 | } | |
ad8d3948 | 476 | |
f2e0899f DK |
477 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
478 | { | |
479 | return opcode & ~DMAE_CMD_SRC_RESET; | |
480 | } | |
ad8d3948 | 481 | |
f2e0899f DK |
482 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
483 | bool with_comp, u8 comp_type) | |
484 | { | |
485 | u32 opcode = 0; | |
486 | ||
487 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
488 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 489 | |
f2e0899f DK |
490 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
491 | ||
492 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
493 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
494 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 495 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 496 | |
a2fbb9ea | 497 | #ifdef __BIG_ENDIAN |
f2e0899f | 498 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 499 | #else |
f2e0899f | 500 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 501 | #endif |
f2e0899f DK |
502 | if (with_comp) |
503 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
504 | return opcode; | |
505 | } | |
506 | ||
fd1fc79d | 507 | void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
8d96286a | 508 | struct dmae_command *dmae, |
509 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
510 | { |
511 | memset(dmae, 0, sizeof(struct dmae_command)); | |
512 | ||
513 | /* set the opcode */ | |
514 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
515 | true, DMAE_COMP_PCI); | |
516 | ||
517 | /* fill in the completion parameters */ | |
518 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
519 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
520 | dmae->comp_val = DMAE_COMP_VAL; | |
521 | } | |
522 | ||
fd1fc79d | 523 | /* issue a dmae command over the init-channel and wait for completion */ |
32316a46 AE |
524 | int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, |
525 | u32 *comp) | |
f2e0899f | 526 | { |
5e374b5a | 527 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
528 | int rc = 0; |
529 | ||
6bf07b8e YM |
530 | bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); |
531 | ||
532 | /* Lock the dmae channel. Disable BHs to prevent a dead-lock | |
619c5cb6 VZ |
533 | * as long as this code is called both from syscall context and |
534 | * from ndo_set_rx_mode() flow that may be called from BH. | |
535 | */ | |
eeed018c | 536 | |
6e30dd4e | 537 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 538 | |
f2e0899f | 539 | /* reset completion */ |
32316a46 | 540 | *comp = 0; |
a2fbb9ea | 541 | |
f2e0899f DK |
542 | /* post the command on the channel used for initializations */ |
543 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 544 | |
f2e0899f | 545 | /* wait for completion */ |
a2fbb9ea | 546 | udelay(5); |
32316a46 | 547 | while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 | 548 | |
95c6c616 AE |
549 | if (!cnt || |
550 | (bp->recovery_state != BNX2X_RECOVERY_DONE && | |
551 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
c3eefaf6 | 552 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
553 | rc = DMAE_TIMEOUT; |
554 | goto unlock; | |
a2fbb9ea | 555 | } |
ad8d3948 | 556 | cnt--; |
f2e0899f | 557 | udelay(50); |
a2fbb9ea | 558 | } |
32316a46 | 559 | if (*comp & DMAE_PCI_ERR_FLAG) { |
f2e0899f DK |
560 | BNX2X_ERR("DMAE PCI error!\n"); |
561 | rc = DMAE_PCI_ERROR; | |
562 | } | |
563 | ||
f2e0899f | 564 | unlock: |
eeed018c | 565 | |
6e30dd4e | 566 | spin_unlock_bh(&bp->dmae_lock); |
eeed018c | 567 | |
f2e0899f DK |
568 | return rc; |
569 | } | |
570 | ||
571 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
572 | u32 len32) | |
573 | { | |
6bf07b8e | 574 | int rc; |
f2e0899f DK |
575 | struct dmae_command dmae; |
576 | ||
577 | if (!bp->dmae_ready) { | |
578 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
579 | ||
127a425e AE |
580 | if (CHIP_IS_E1(bp)) |
581 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
582 | else | |
583 | bnx2x_init_str_wr(bp, dst_addr, data, len32); | |
f2e0899f DK |
584 | return; |
585 | } | |
586 | ||
587 | /* set opcode and fixed command fields */ | |
588 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
589 | ||
590 | /* fill in addresses and len */ | |
591 | dmae.src_addr_lo = U64_LO(dma_addr); | |
592 | dmae.src_addr_hi = U64_HI(dma_addr); | |
593 | dmae.dst_addr_lo = dst_addr >> 2; | |
594 | dmae.dst_addr_hi = 0; | |
595 | dmae.len = len32; | |
596 | ||
f2e0899f | 597 | /* issue the command and wait for completion */ |
32316a46 | 598 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); |
6bf07b8e YM |
599 | if (rc) { |
600 | BNX2X_ERR("DMAE returned failure %d\n", rc); | |
9dcd9acd | 601 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e | 602 | bnx2x_panic(); |
9dcd9acd | 603 | #endif |
6bf07b8e | 604 | } |
a2fbb9ea ET |
605 | } |
606 | ||
c18487ee | 607 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 608 | { |
6bf07b8e | 609 | int rc; |
5ff7b6d4 | 610 | struct dmae_command dmae; |
ad8d3948 EG |
611 | |
612 | if (!bp->dmae_ready) { | |
613 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
614 | int i; | |
615 | ||
51c1a580 | 616 | if (CHIP_IS_E1(bp)) |
127a425e AE |
617 | for (i = 0; i < len32; i++) |
618 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
51c1a580 | 619 | else |
127a425e AE |
620 | for (i = 0; i < len32; i++) |
621 | data[i] = REG_RD(bp, src_addr + i*4); | |
622 | ||
ad8d3948 EG |
623 | return; |
624 | } | |
625 | ||
f2e0899f DK |
626 | /* set opcode and fixed command fields */ |
627 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 628 | |
f2e0899f | 629 | /* fill in addresses and len */ |
5ff7b6d4 EG |
630 | dmae.src_addr_lo = src_addr >> 2; |
631 | dmae.src_addr_hi = 0; | |
632 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
633 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
634 | dmae.len = len32; | |
ad8d3948 | 635 | |
f2e0899f | 636 | /* issue the command and wait for completion */ |
32316a46 | 637 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); |
6bf07b8e YM |
638 | if (rc) { |
639 | BNX2X_ERR("DMAE returned failure %d\n", rc); | |
9dcd9acd | 640 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e | 641 | bnx2x_panic(); |
9dcd9acd | 642 | #endif |
c957d09f | 643 | } |
ad8d3948 EG |
644 | } |
645 | ||
8d96286a | 646 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
647 | u32 addr, u32 len) | |
573f2035 | 648 | { |
02e3c6cb | 649 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
650 | int offset = 0; |
651 | ||
02e3c6cb | 652 | while (len > dmae_wr_max) { |
573f2035 | 653 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
654 | addr + offset, dmae_wr_max); |
655 | offset += dmae_wr_max * 4; | |
656 | len -= dmae_wr_max; | |
573f2035 EG |
657 | } |
658 | ||
659 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
660 | } | |
661 | ||
97539f1e AE |
662 | enum storms { |
663 | XSTORM, | |
664 | TSTORM, | |
665 | CSTORM, | |
666 | USTORM, | |
667 | MAX_STORMS | |
668 | }; | |
34f80b04 | 669 | |
97539f1e AE |
670 | #define STORMS_NUM 4 |
671 | #define REGS_IN_ENTRY 4 | |
34f80b04 | 672 | |
97539f1e AE |
673 | static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp, |
674 | enum storms storm, | |
675 | int entry) | |
676 | { | |
677 | switch (storm) { | |
678 | case XSTORM: | |
679 | return XSTORM_ASSERT_LIST_OFFSET(entry); | |
680 | case TSTORM: | |
681 | return TSTORM_ASSERT_LIST_OFFSET(entry); | |
682 | case CSTORM: | |
683 | return CSTORM_ASSERT_LIST_OFFSET(entry); | |
684 | case USTORM: | |
685 | return USTORM_ASSERT_LIST_OFFSET(entry); | |
686 | case MAX_STORMS: | |
687 | default: | |
688 | BNX2X_ERR("unknown storm\n"); | |
34f80b04 | 689 | } |
97539f1e AE |
690 | return -EINVAL; |
691 | } | |
34f80b04 | 692 | |
97539f1e AE |
693 | static int bnx2x_mc_assert(struct bnx2x *bp) |
694 | { | |
695 | char last_idx; | |
696 | int i, j, rc = 0; | |
697 | enum storms storm; | |
698 | u32 regs[REGS_IN_ENTRY]; | |
699 | u32 bar_storm_intmem[STORMS_NUM] = { | |
700 | BAR_XSTRORM_INTMEM, | |
701 | BAR_TSTRORM_INTMEM, | |
702 | BAR_CSTRORM_INTMEM, | |
703 | BAR_USTRORM_INTMEM | |
704 | }; | |
705 | u32 storm_assert_list_index[STORMS_NUM] = { | |
706 | XSTORM_ASSERT_LIST_INDEX_OFFSET, | |
707 | TSTORM_ASSERT_LIST_INDEX_OFFSET, | |
708 | CSTORM_ASSERT_LIST_INDEX_OFFSET, | |
709 | USTORM_ASSERT_LIST_INDEX_OFFSET | |
710 | }; | |
711 | char *storms_string[STORMS_NUM] = { | |
712 | "XSTORM", | |
713 | "TSTORM", | |
714 | "CSTORM", | |
715 | "USTORM" | |
716 | }; | |
717 | ||
718 | for (storm = XSTORM; storm < MAX_STORMS; storm++) { | |
719 | last_idx = REG_RD8(bp, bar_storm_intmem[storm] + | |
720 | storm_assert_list_index[storm]); | |
721 | if (last_idx) | |
722 | BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n", | |
723 | storms_string[storm], last_idx); | |
724 | ||
725 | /* print the asserts */ | |
726 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
727 | /* read a single assert entry */ | |
728 | for (j = 0; j < REGS_IN_ENTRY; j++) | |
729 | regs[j] = REG_RD(bp, bar_storm_intmem[storm] + | |
730 | bnx2x_get_assert_list_entry(bp, | |
731 | storm, | |
732 | i) + | |
733 | sizeof(u32) * j); | |
734 | ||
735 | /* log entry if it contains a valid assert */ | |
736 | if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
737 | BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
738 | storms_string[storm], i, regs[3], | |
739 | regs[2], regs[1], regs[0]); | |
740 | rc++; | |
741 | } else { | |
742 | break; | |
743 | } | |
a2fbb9ea ET |
744 | } |
745 | } | |
34f80b04 | 746 | |
97539f1e AE |
747 | BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n", |
748 | CHIP_IS_E1(bp) ? "everest1" : | |
749 | CHIP_IS_E1H(bp) ? "everest1h" : | |
750 | CHIP_IS_E2(bp) ? "everest2" : "everest3", | |
751 | BCM_5710_FW_MAJOR_VERSION, | |
752 | BCM_5710_FW_MINOR_VERSION, | |
753 | BCM_5710_FW_REVISION_VERSION); | |
754 | ||
a2fbb9ea ET |
755 | return rc; |
756 | } | |
c14423fe | 757 | |
1a6974b2 YM |
758 | #define MCPR_TRACE_BUFFER_SIZE (0x800) |
759 | #define SCRATCH_BUFFER_SIZE(bp) \ | |
760 | (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000)) | |
761 | ||
7a25cc73 | 762 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 763 | { |
7a25cc73 | 764 | u32 addr, val; |
a2fbb9ea | 765 | u32 mark, offset; |
4781bfad | 766 | __be32 data[9]; |
a2fbb9ea | 767 | int word; |
f2e0899f | 768 | u32 trace_shmem_base; |
2145a920 VZ |
769 | if (BP_NOMCP(bp)) { |
770 | BNX2X_ERR("NO MCP - can not dump\n"); | |
771 | return; | |
772 | } | |
7a25cc73 DK |
773 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
774 | (bp->common.bc_ver & 0xff0000) >> 16, | |
775 | (bp->common.bc_ver & 0xff00) >> 8, | |
776 | (bp->common.bc_ver & 0xff)); | |
777 | ||
778 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
779 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
51c1a580 | 780 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
cdaa7cb8 | 781 | |
f2e0899f DK |
782 | if (BP_PATH(bp) == 0) |
783 | trace_shmem_base = bp->common.shmem_base; | |
784 | else | |
785 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
1a6974b2 YM |
786 | |
787 | /* sanity */ | |
788 | if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE || | |
789 | trace_shmem_base >= MCPR_SCRATCH_BASE(bp) + | |
790 | SCRATCH_BUFFER_SIZE(bp)) { | |
791 | BNX2X_ERR("Unable to dump trace buffer (mark %x)\n", | |
792 | trace_shmem_base); | |
793 | return; | |
794 | } | |
795 | ||
796 | addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE; | |
de128804 DK |
797 | |
798 | /* validate TRCB signature */ | |
799 | mark = REG_RD(bp, addr); | |
800 | if (mark != MFW_TRACE_SIGNATURE) { | |
801 | BNX2X_ERR("Trace buffer signature is missing."); | |
802 | return ; | |
803 | } | |
804 | ||
805 | /* read cyclic buffer pointer */ | |
806 | addr += 4; | |
cdaa7cb8 | 807 | mark = REG_RD(bp, addr); |
1a6974b2 YM |
808 | mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000; |
809 | if (mark >= trace_shmem_base || mark < addr + 4) { | |
810 | BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n"); | |
811 | return; | |
812 | } | |
7a25cc73 | 813 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 814 | |
7a25cc73 | 815 | printk("%s", lvl); |
2de67439 YM |
816 | |
817 | /* dump buffer after the mark */ | |
1a6974b2 | 818 | for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 819 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 820 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 821 | data[8] = 0x0; |
7995c64e | 822 | pr_cont("%s", (char *)data); |
a2fbb9ea | 823 | } |
2de67439 YM |
824 | |
825 | /* dump buffer before the mark */ | |
cdaa7cb8 | 826 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 827 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 828 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 829 | data[8] = 0x0; |
7995c64e | 830 | pr_cont("%s", (char *)data); |
a2fbb9ea | 831 | } |
7a25cc73 DK |
832 | printk("%s" "end of fw dump\n", lvl); |
833 | } | |
834 | ||
1191cb83 | 835 | static void bnx2x_fw_dump(struct bnx2x *bp) |
7a25cc73 DK |
836 | { |
837 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
838 | } |
839 | ||
823e1d90 YM |
840 | static void bnx2x_hc_int_disable(struct bnx2x *bp) |
841 | { | |
842 | int port = BP_PORT(bp); | |
843 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; | |
844 | u32 val = REG_RD(bp, addr); | |
845 | ||
846 | /* in E1 we must use only PCI configuration space to disable | |
16a5fd92 YM |
847 | * MSI/MSIX capability |
848 | * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
823e1d90 YM |
849 | */ |
850 | if (CHIP_IS_E1(bp)) { | |
851 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
852 | * Use mask register to prevent from HC sending interrupts | |
853 | * after we exit the function | |
854 | */ | |
855 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
856 | ||
857 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
858 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
859 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
860 | } else | |
861 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
862 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
863 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
864 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
865 | ||
866 | DP(NETIF_MSG_IFDOWN, | |
867 | "write %x to HC %d (addr 0x%x)\n", | |
868 | val, port, addr); | |
869 | ||
870 | /* flush all outstanding writes */ | |
871 | mmiowb(); | |
872 | ||
873 | REG_WR(bp, addr, val); | |
874 | if (REG_RD(bp, addr) != val) | |
6bf07b8e | 875 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
823e1d90 YM |
876 | } |
877 | ||
878 | static void bnx2x_igu_int_disable(struct bnx2x *bp) | |
879 | { | |
880 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
881 | ||
882 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
883 | IGU_PF_CONF_INT_LINE_EN | | |
884 | IGU_PF_CONF_ATTN_BIT_EN); | |
885 | ||
886 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); | |
887 | ||
888 | /* flush all outstanding writes */ | |
889 | mmiowb(); | |
890 | ||
891 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
892 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
6bf07b8e | 893 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
823e1d90 YM |
894 | } |
895 | ||
896 | static void bnx2x_int_disable(struct bnx2x *bp) | |
897 | { | |
898 | if (bp->common.int_block == INT_BLOCK_HC) | |
899 | bnx2x_hc_int_disable(bp); | |
900 | else | |
901 | bnx2x_igu_int_disable(bp); | |
902 | } | |
903 | ||
904 | void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) | |
a2fbb9ea ET |
905 | { |
906 | int i; | |
523224a3 DK |
907 | u16 j; |
908 | struct hc_sp_status_block_data sp_sb_data; | |
909 | int func = BP_FUNC(bp); | |
910 | #ifdef BNX2X_STOP_ON_ERROR | |
911 | u16 start = 0, end = 0; | |
6383c0b3 | 912 | u8 cos; |
523224a3 | 913 | #endif |
0155a27c | 914 | if (IS_PF(bp) && disable_int) |
823e1d90 | 915 | bnx2x_int_disable(bp); |
a2fbb9ea | 916 | |
66e855f3 | 917 | bp->stats_state = STATS_STATE_DISABLED; |
7a752993 | 918 | bp->eth_stats.unrecoverable_error++; |
66e855f3 YG |
919 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
920 | ||
a2fbb9ea ET |
921 | BNX2X_ERR("begin crash dump -----------------\n"); |
922 | ||
8440d2b6 EG |
923 | /* Indices */ |
924 | /* Common */ | |
0155a27c YM |
925 | if (IS_PF(bp)) { |
926 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
927 | int data_size, cstorm_offset; | |
928 | ||
929 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", | |
930 | bp->def_idx, bp->def_att_idx, bp->attn_state, | |
931 | bp->spq_prod_idx, bp->stats_counter); | |
932 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", | |
933 | def_sb->atten_status_block.attn_bits, | |
934 | def_sb->atten_status_block.attn_bits_ack, | |
935 | def_sb->atten_status_block.status_block_id, | |
936 | def_sb->atten_status_block.attn_bits_index); | |
937 | BNX2X_ERR(" def ("); | |
938 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
939 | pr_cont("0x%x%s", | |
940 | def_sb->sp_sb.index_values[i], | |
941 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
942 | ||
943 | data_size = sizeof(struct hc_sp_status_block_data) / | |
944 | sizeof(u32); | |
945 | cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func); | |
946 | for (i = 0; i < data_size; i++) | |
947 | *((u32 *)&sp_sb_data + i) = | |
948 | REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset + | |
949 | i * sizeof(u32)); | |
950 | ||
951 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", | |
952 | sp_sb_data.igu_sb_id, | |
953 | sp_sb_data.igu_seg_id, | |
954 | sp_sb_data.p_func.pf_id, | |
955 | sp_sb_data.p_func.vnic_id, | |
956 | sp_sb_data.p_func.vf_id, | |
957 | sp_sb_data.p_func.vf_valid, | |
958 | sp_sb_data.state); | |
959 | } | |
523224a3 | 960 | |
ec6ba945 | 961 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 962 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 963 | int loop; |
f2e0899f | 964 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
965 | struct hc_status_block_data_e1x sb_data_e1x; |
966 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
967 | CHIP_IS_E1x(bp) ? |
968 | sb_data_e1x.common.state_machine : | |
969 | sb_data_e2.common.state_machine; | |
523224a3 | 970 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
971 | CHIP_IS_E1x(bp) ? |
972 | sb_data_e1x.index_data : | |
973 | sb_data_e2.index_data; | |
6383c0b3 | 974 | u8 data_size, cos; |
523224a3 | 975 | u32 *sb_data_p; |
6383c0b3 | 976 | struct bnx2x_fp_txdata txdata; |
523224a3 | 977 | |
e2611998 YM |
978 | if (!bp->fp) |
979 | break; | |
980 | ||
981 | if (!fp->rx_cons_sb) | |
982 | continue; | |
983 | ||
523224a3 | 984 | /* Rx */ |
51c1a580 | 985 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 986 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 987 | fp->rx_comp_prod, |
66e855f3 | 988 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
51c1a580 | 989 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
8440d2b6 | 990 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 991 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 992 | |
523224a3 | 993 | /* Tx */ |
6383c0b3 AE |
994 | for_each_cos_in_tx_queue(fp, cos) |
995 | { | |
1fc3de94 | 996 | if (!fp->txdata_ptr[cos]) |
e2611998 YM |
997 | break; |
998 | ||
65565884 | 999 | txdata = *fp->txdata_ptr[cos]; |
e2611998 YM |
1000 | |
1001 | if (!txdata.tx_cons_sb) | |
1002 | continue; | |
1003 | ||
51c1a580 | 1004 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
6383c0b3 AE |
1005 | i, txdata.tx_pkt_prod, |
1006 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
1007 | txdata.tx_bd_cons, | |
1008 | le16_to_cpu(*txdata.tx_cons_sb)); | |
1009 | } | |
523224a3 | 1010 | |
619c5cb6 VZ |
1011 | loop = CHIP_IS_E1x(bp) ? |
1012 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
1013 | |
1014 | /* host sb data */ | |
1015 | ||
ec6ba945 VZ |
1016 | if (IS_FCOE_FP(fp)) |
1017 | continue; | |
55c11941 | 1018 | |
523224a3 DK |
1019 | BNX2X_ERR(" run indexes ("); |
1020 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
1021 | pr_cont("0x%x%s", | |
1022 | fp->sb_running_index[j], | |
1023 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
1024 | ||
1025 | BNX2X_ERR(" indexes ("); | |
1026 | for (j = 0; j < loop; j++) | |
1027 | pr_cont("0x%x%s", | |
1028 | fp->sb_index_values[j], | |
1029 | (j == loop - 1) ? ")" : " "); | |
0155a27c YM |
1030 | |
1031 | /* VF cannot access FW refelection for status block */ | |
1032 | if (IS_VF(bp)) | |
1033 | continue; | |
1034 | ||
523224a3 | 1035 | /* fw sb data */ |
619c5cb6 VZ |
1036 | data_size = CHIP_IS_E1x(bp) ? |
1037 | sizeof(struct hc_status_block_data_e1x) : | |
1038 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 1039 | data_size /= sizeof(u32); |
619c5cb6 VZ |
1040 | sb_data_p = CHIP_IS_E1x(bp) ? |
1041 | (u32 *)&sb_data_e1x : | |
1042 | (u32 *)&sb_data_e2; | |
523224a3 DK |
1043 | /* copy sb data in here */ |
1044 | for (j = 0; j < data_size; j++) | |
1045 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
1046 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
1047 | j * sizeof(u32)); | |
1048 | ||
619c5cb6 | 1049 | if (!CHIP_IS_E1x(bp)) { |
51c1a580 | 1050 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
1051 | sb_data_e2.common.p_func.pf_id, |
1052 | sb_data_e2.common.p_func.vf_id, | |
1053 | sb_data_e2.common.p_func.vf_valid, | |
1054 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
1055 | sb_data_e2.common.same_igu_sb_1b, |
1056 | sb_data_e2.common.state); | |
f2e0899f | 1057 | } else { |
51c1a580 | 1058 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
1059 | sb_data_e1x.common.p_func.pf_id, |
1060 | sb_data_e1x.common.p_func.vf_id, | |
1061 | sb_data_e1x.common.p_func.vf_valid, | |
1062 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
1063 | sb_data_e1x.common.same_igu_sb_1b, |
1064 | sb_data_e1x.common.state); | |
f2e0899f | 1065 | } |
523224a3 DK |
1066 | |
1067 | /* SB_SMs data */ | |
1068 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
51c1a580 MS |
1069 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
1070 | j, hc_sm_p[j].__flags, | |
1071 | hc_sm_p[j].igu_sb_id, | |
1072 | hc_sm_p[j].igu_seg_id, | |
1073 | hc_sm_p[j].time_to_expire, | |
1074 | hc_sm_p[j].timer_value); | |
523224a3 DK |
1075 | } |
1076 | ||
16a5fd92 | 1077 | /* Indices data */ |
523224a3 | 1078 | for (j = 0; j < loop; j++) { |
51c1a580 | 1079 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
523224a3 DK |
1080 | hc_index_p[j].flags, |
1081 | hc_index_p[j].timeout); | |
1082 | } | |
8440d2b6 | 1083 | } |
a2fbb9ea | 1084 | |
523224a3 | 1085 | #ifdef BNX2X_STOP_ON_ERROR |
0155a27c YM |
1086 | if (IS_PF(bp)) { |
1087 | /* event queue */ | |
1088 | BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); | |
1089 | for (i = 0; i < NUM_EQ_DESC; i++) { | |
1090 | u32 *data = (u32 *)&bp->eq_ring[i].message.data; | |
1091 | ||
1092 | BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n", | |
1093 | i, bp->eq_ring[i].message.opcode, | |
1094 | bp->eq_ring[i].message.error); | |
1095 | BNX2X_ERR("data: %x %x %x\n", | |
1096 | data[0], data[1], data[2]); | |
1097 | } | |
04c46736 YM |
1098 | } |
1099 | ||
8440d2b6 EG |
1100 | /* Rings */ |
1101 | /* Rx */ | |
55c11941 | 1102 | for_each_valid_rx_queue(bp, i) { |
8440d2b6 | 1103 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1104 | |
e2611998 YM |
1105 | if (!bp->fp) |
1106 | break; | |
1107 | ||
1108 | if (!fp->rx_cons_sb) | |
1109 | continue; | |
1110 | ||
a2fbb9ea ET |
1111 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); |
1112 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 1113 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
1114 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
1115 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
1116 | ||
c3eefaf6 | 1117 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
44151acb | 1118 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
a2fbb9ea ET |
1119 | } |
1120 | ||
3196a88a EG |
1121 | start = RX_SGE(fp->rx_sge_prod); |
1122 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 1123 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
1124 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
1125 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
1126 | ||
c3eefaf6 EG |
1127 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
1128 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
1129 | } |
1130 | ||
a2fbb9ea ET |
1131 | start = RCQ_BD(fp->rx_comp_cons - 10); |
1132 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 1133 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
1134 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
1135 | ||
c3eefaf6 EG |
1136 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
1137 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
1138 | } |
1139 | } | |
1140 | ||
8440d2b6 | 1141 | /* Tx */ |
55c11941 | 1142 | for_each_valid_tx_queue(bp, i) { |
8440d2b6 | 1143 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
e2611998 YM |
1144 | |
1145 | if (!bp->fp) | |
1146 | break; | |
1147 | ||
6383c0b3 | 1148 | for_each_cos_in_tx_queue(fp, cos) { |
65565884 | 1149 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
6383c0b3 | 1150 | |
1fc3de94 | 1151 | if (!fp->txdata_ptr[cos]) |
e2611998 YM |
1152 | break; |
1153 | ||
ea36475a | 1154 | if (!txdata->tx_cons_sb) |
e2611998 YM |
1155 | continue; |
1156 | ||
6383c0b3 AE |
1157 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); |
1158 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
1159 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1160 | struct sw_tx_bd *sw_bd = | |
1161 | &txdata->tx_buf_ring[j]; | |
1162 | ||
51c1a580 | 1163 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
6383c0b3 AE |
1164 | i, cos, j, sw_bd->skb, |
1165 | sw_bd->first_bd); | |
1166 | } | |
8440d2b6 | 1167 | |
6383c0b3 AE |
1168 | start = TX_BD(txdata->tx_bd_cons - 10); |
1169 | end = TX_BD(txdata->tx_bd_cons + 254); | |
1170 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1171 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 1172 | |
51c1a580 | 1173 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
6383c0b3 AE |
1174 | i, cos, j, tx_bd[0], tx_bd[1], |
1175 | tx_bd[2], tx_bd[3]); | |
1176 | } | |
8440d2b6 EG |
1177 | } |
1178 | } | |
523224a3 | 1179 | #endif |
0155a27c YM |
1180 | if (IS_PF(bp)) { |
1181 | bnx2x_fw_dump(bp); | |
1182 | bnx2x_mc_assert(bp); | |
1183 | } | |
a2fbb9ea | 1184 | BNX2X_ERR("end crash dump -----------------\n"); |
a2fbb9ea ET |
1185 | } |
1186 | ||
619c5cb6 VZ |
1187 | /* |
1188 | * FLR Support for E2 | |
1189 | * | |
1190 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
1191 | * initialization. | |
1192 | */ | |
16a5fd92 | 1193 | #define FLR_WAIT_USEC 10000 /* 10 milliseconds */ |
89db4ad8 AE |
1194 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
1195 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ | |
619c5cb6 VZ |
1196 | |
1197 | struct pbf_pN_buf_regs { | |
1198 | int pN; | |
1199 | u32 init_crd; | |
1200 | u32 crd; | |
1201 | u32 crd_freed; | |
1202 | }; | |
1203 | ||
1204 | struct pbf_pN_cmd_regs { | |
1205 | int pN; | |
1206 | u32 lines_occup; | |
1207 | u32 lines_freed; | |
1208 | }; | |
1209 | ||
1210 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
1211 | struct pbf_pN_buf_regs *regs, | |
1212 | u32 poll_count) | |
1213 | { | |
1214 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
1215 | u32 cur_cnt = poll_count; | |
1216 | ||
1217 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
1218 | crd = crd_start = REG_RD(bp, regs->crd); | |
1219 | init_crd = REG_RD(bp, regs->init_crd); | |
1220 | ||
1221 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
1222 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
1223 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
1224 | ||
1225 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
1226 | (init_crd - crd_start))) { | |
1227 | if (cur_cnt--) { | |
89db4ad8 | 1228 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1229 | crd = REG_RD(bp, regs->crd); |
1230 | crd_freed = REG_RD(bp, regs->crd_freed); | |
1231 | } else { | |
1232 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
1233 | regs->pN); | |
1234 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
1235 | regs->pN, crd); | |
1236 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
1237 | regs->pN, crd_freed); | |
1238 | break; | |
1239 | } | |
1240 | } | |
1241 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
89db4ad8 | 1242 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1243 | } |
1244 | ||
1245 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
1246 | struct pbf_pN_cmd_regs *regs, | |
1247 | u32 poll_count) | |
1248 | { | |
1249 | u32 occup, to_free, freed, freed_start; | |
1250 | u32 cur_cnt = poll_count; | |
1251 | ||
1252 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
1253 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
1254 | ||
1255 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
1256 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
1257 | ||
1258 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
1259 | if (cur_cnt--) { | |
89db4ad8 | 1260 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1261 | occup = REG_RD(bp, regs->lines_occup); |
1262 | freed = REG_RD(bp, regs->lines_freed); | |
1263 | } else { | |
1264 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
1265 | regs->pN); | |
1266 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
1267 | regs->pN, occup); | |
1268 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
1269 | regs->pN, freed); | |
1270 | break; | |
1271 | } | |
1272 | } | |
1273 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
89db4ad8 | 1274 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1275 | } |
1276 | ||
1191cb83 ED |
1277 | static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, |
1278 | u32 expected, u32 poll_count) | |
619c5cb6 VZ |
1279 | { |
1280 | u32 cur_cnt = poll_count; | |
1281 | u32 val; | |
1282 | ||
1283 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
89db4ad8 | 1284 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1285 | |
1286 | return val; | |
1287 | } | |
1288 | ||
d16132ce AE |
1289 | int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, |
1290 | char *msg, u32 poll_cnt) | |
619c5cb6 VZ |
1291 | { |
1292 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1293 | if (val != 0) { | |
1294 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1295 | return 1; | |
1296 | } | |
1297 | return 0; | |
1298 | } | |
1299 | ||
d16132ce AE |
1300 | /* Common routines with VF FLR cleanup */ |
1301 | u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
619c5cb6 VZ |
1302 | { |
1303 | /* adjust polling timeout */ | |
1304 | if (CHIP_REV_IS_EMUL(bp)) | |
1305 | return FLR_POLL_CNT * 2000; | |
1306 | ||
1307 | if (CHIP_REV_IS_FPGA(bp)) | |
1308 | return FLR_POLL_CNT * 120; | |
1309 | ||
1310 | return FLR_POLL_CNT; | |
1311 | } | |
1312 | ||
d16132ce | 1313 | void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) |
619c5cb6 VZ |
1314 | { |
1315 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1316 | {0, (CHIP_IS_E3B0(bp)) ? | |
1317 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1318 | PBF_REG_P0_TQ_OCCUPANCY, | |
1319 | (CHIP_IS_E3B0(bp)) ? | |
1320 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1321 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1322 | {1, (CHIP_IS_E3B0(bp)) ? | |
1323 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1324 | PBF_REG_P1_TQ_OCCUPANCY, | |
1325 | (CHIP_IS_E3B0(bp)) ? | |
1326 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1327 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1328 | {4, (CHIP_IS_E3B0(bp)) ? | |
1329 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1330 | PBF_REG_P4_TQ_OCCUPANCY, | |
1331 | (CHIP_IS_E3B0(bp)) ? | |
1332 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1333 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1334 | }; | |
1335 | ||
1336 | struct pbf_pN_buf_regs buf_regs[] = { | |
1337 | {0, (CHIP_IS_E3B0(bp)) ? | |
1338 | PBF_REG_INIT_CRD_Q0 : | |
1339 | PBF_REG_P0_INIT_CRD , | |
1340 | (CHIP_IS_E3B0(bp)) ? | |
1341 | PBF_REG_CREDIT_Q0 : | |
1342 | PBF_REG_P0_CREDIT, | |
1343 | (CHIP_IS_E3B0(bp)) ? | |
1344 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1345 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1346 | {1, (CHIP_IS_E3B0(bp)) ? | |
1347 | PBF_REG_INIT_CRD_Q1 : | |
1348 | PBF_REG_P1_INIT_CRD, | |
1349 | (CHIP_IS_E3B0(bp)) ? | |
1350 | PBF_REG_CREDIT_Q1 : | |
1351 | PBF_REG_P1_CREDIT, | |
1352 | (CHIP_IS_E3B0(bp)) ? | |
1353 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1354 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1355 | {4, (CHIP_IS_E3B0(bp)) ? | |
1356 | PBF_REG_INIT_CRD_LB_Q : | |
1357 | PBF_REG_P4_INIT_CRD, | |
1358 | (CHIP_IS_E3B0(bp)) ? | |
1359 | PBF_REG_CREDIT_LB_Q : | |
1360 | PBF_REG_P4_CREDIT, | |
1361 | (CHIP_IS_E3B0(bp)) ? | |
1362 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1363 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1364 | }; | |
1365 | ||
1366 | int i; | |
1367 | ||
1368 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1369 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1370 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1371 | ||
619c5cb6 VZ |
1372 | /* Verify the transmission buffers are flushed P0, P1, P4 */ |
1373 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1374 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1375 | } | |
1376 | ||
1377 | #define OP_GEN_PARAM(param) \ | |
1378 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1379 | ||
1380 | #define OP_GEN_TYPE(type) \ | |
1381 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1382 | ||
1383 | #define OP_GEN_AGG_VECT(index) \ | |
1384 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1385 | ||
d16132ce | 1386 | int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) |
619c5cb6 | 1387 | { |
86564c3f | 1388 | u32 op_gen_command = 0; |
619c5cb6 VZ |
1389 | u32 comp_addr = BAR_CSTRORM_INTMEM + |
1390 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1391 | int ret = 0; | |
1392 | ||
1393 | if (REG_RD(bp, comp_addr)) { | |
89db4ad8 | 1394 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
619c5cb6 VZ |
1395 | return 1; |
1396 | } | |
1397 | ||
86564c3f YM |
1398 | op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); |
1399 | op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1400 | op_gen_command |= OP_GEN_AGG_VECT(clnup_func); | |
1401 | op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
619c5cb6 | 1402 | |
89db4ad8 | 1403 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
86564c3f | 1404 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); |
619c5cb6 VZ |
1405 | |
1406 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1407 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
51c1a580 MS |
1408 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
1409 | (REG_RD(bp, comp_addr))); | |
d16132ce AE |
1410 | bnx2x_panic(); |
1411 | return 1; | |
619c5cb6 | 1412 | } |
16a5fd92 | 1413 | /* Zero completion for next FLR */ |
619c5cb6 VZ |
1414 | REG_WR(bp, comp_addr, 0); |
1415 | ||
1416 | return ret; | |
1417 | } | |
1418 | ||
b56e9670 | 1419 | u8 bnx2x_is_pcie_pending(struct pci_dev *dev) |
619c5cb6 | 1420 | { |
619c5cb6 VZ |
1421 | u16 status; |
1422 | ||
2a80eebc | 1423 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
619c5cb6 VZ |
1424 | return status & PCI_EXP_DEVSTA_TRPND; |
1425 | } | |
1426 | ||
1427 | /* PF FLR specific routines | |
1428 | */ | |
1429 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1430 | { | |
619c5cb6 VZ |
1431 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ |
1432 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1433 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1434 | "CFC PF usage counter timed out", | |
1435 | poll_cnt)) | |
1436 | return 1; | |
1437 | ||
619c5cb6 VZ |
1438 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ |
1439 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1440 | DORQ_REG_PF_USAGE_CNT, | |
1441 | "DQ PF usage counter timed out", | |
1442 | poll_cnt)) | |
1443 | return 1; | |
1444 | ||
1445 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1446 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1447 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1448 | "QM PF usage counter timed out", | |
1449 | poll_cnt)) | |
1450 | return 1; | |
1451 | ||
1452 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1453 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1454 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1455 | "Timers VNIC usage counter timed out", | |
1456 | poll_cnt)) | |
1457 | return 1; | |
1458 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1459 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1460 | "Timers NUM_SCANS usage counter timed out", | |
1461 | poll_cnt)) | |
1462 | return 1; | |
1463 | ||
1464 | /* Wait DMAE PF usage counter to zero */ | |
1465 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1466 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
6bf07b8e | 1467 | "DMAE command register timed out", |
619c5cb6 VZ |
1468 | poll_cnt)) |
1469 | return 1; | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1475 | { | |
1476 | u32 val; | |
1477 | ||
1478 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1479 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1480 | ||
1481 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1482 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1483 | ||
1484 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1485 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1486 | ||
1487 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1488 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1489 | ||
1490 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1491 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1492 | ||
1493 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1494 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1495 | ||
1496 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1497 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1498 | ||
1499 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1500 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1501 | val); | |
1502 | } | |
1503 | ||
1504 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1505 | { | |
1506 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1507 | ||
1508 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1509 | ||
1510 | /* Re-enable PF target read access */ | |
1511 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1512 | ||
1513 | /* Poll HW usage counters */ | |
89db4ad8 | 1514 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
619c5cb6 VZ |
1515 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
1516 | return -EBUSY; | |
1517 | ||
1518 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1519 | ||
1520 | /* Send the FW cleanup command */ | |
1521 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1522 | return -EBUSY; | |
1523 | ||
1524 | /* ATC cleanup */ | |
1525 | ||
1526 | /* Verify TX hw is flushed */ | |
1527 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1528 | ||
1529 | /* Wait 100ms (not adjusted according to platform) */ | |
1530 | msleep(100); | |
1531 | ||
1532 | /* Verify no pending pci transactions */ | |
1533 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1534 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1535 | ||
1536 | /* Debug */ | |
1537 | bnx2x_hw_enable_status(bp); | |
1538 | ||
1539 | /* | |
1540 | * Master enable - Due to WB DMAE writes performed before this | |
1541 | * register is re-initialized as part of the regular function init | |
1542 | */ | |
1543 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1544 | ||
1545 | return 0; | |
1546 | } | |
1547 | ||
f2e0899f | 1548 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1549 | { |
34f80b04 | 1550 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1551 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1552 | u32 val = REG_RD(bp, addr); | |
69c326b3 DK |
1553 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1554 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1555 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
a2fbb9ea ET |
1556 | |
1557 | if (msix) { | |
8badd27a EG |
1558 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1559 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1560 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1561 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
69c326b3 DK |
1562 | if (single_msix) |
1563 | val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; | |
8badd27a EG |
1564 | } else if (msi) { |
1565 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1566 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1567 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1568 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1569 | } else { |
1570 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1571 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1572 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1573 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1574 | |
a0fd065c | 1575 | if (!CHIP_IS_E1(bp)) { |
51c1a580 MS |
1576 | DP(NETIF_MSG_IFUP, |
1577 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); | |
615f8fd9 | 1578 | |
a0fd065c | 1579 | REG_WR(bp, addr, val); |
615f8fd9 | 1580 | |
a0fd065c DK |
1581 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1582 | } | |
a2fbb9ea ET |
1583 | } |
1584 | ||
a0fd065c DK |
1585 | if (CHIP_IS_E1(bp)) |
1586 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1587 | ||
51c1a580 MS |
1588 | DP(NETIF_MSG_IFUP, |
1589 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, | |
1590 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1591 | |
1592 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1593 | /* |
1594 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1595 | */ | |
1596 | mmiowb(); | |
1597 | barrier(); | |
34f80b04 | 1598 | |
f2e0899f | 1599 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1600 | /* init leading/trailing edge */ |
fb3bff17 | 1601 | if (IS_MF(bp)) { |
3395a033 | 1602 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1603 | if (bp->port.pmf) |
4acac6a5 EG |
1604 | /* enable nig and gpio3 attention */ |
1605 | val |= 0x1100; | |
34f80b04 EG |
1606 | } else |
1607 | val = 0xffff; | |
1608 | ||
1609 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1610 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1611 | } | |
37dbbf32 EG |
1612 | |
1613 | /* Make sure that interrupts are indeed enabled from here on */ | |
1614 | mmiowb(); | |
a2fbb9ea ET |
1615 | } |
1616 | ||
f2e0899f DK |
1617 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1618 | { | |
1619 | u32 val; | |
30a5de77 DK |
1620 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1621 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1622 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
f2e0899f DK |
1623 | |
1624 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1625 | ||
1626 | if (msix) { | |
1627 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1628 | IGU_PF_CONF_SINGLE_ISR_EN); | |
ebe61d80 | 1629 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
f2e0899f | 1630 | IGU_PF_CONF_ATTN_BIT_EN); |
30a5de77 DK |
1631 | |
1632 | if (single_msix) | |
1633 | val |= IGU_PF_CONF_SINGLE_ISR_EN; | |
f2e0899f DK |
1634 | } else if (msi) { |
1635 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
ebe61d80 | 1636 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
f2e0899f DK |
1637 | IGU_PF_CONF_ATTN_BIT_EN | |
1638 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1639 | } else { | |
1640 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
ebe61d80 | 1641 | val |= (IGU_PF_CONF_INT_LINE_EN | |
f2e0899f DK |
1642 | IGU_PF_CONF_ATTN_BIT_EN | |
1643 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1644 | } | |
1645 | ||
ebe61d80 YM |
1646 | /* Clean previous status - need to configure igu prior to ack*/ |
1647 | if ((!msix) || single_msix) { | |
1648 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1649 | bnx2x_ack_int(bp); | |
1650 | } | |
1651 | ||
1652 | val |= IGU_PF_CONF_FUNC_EN; | |
1653 | ||
51c1a580 | 1654 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
f2e0899f DK |
1655 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
1656 | ||
1657 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1658 | ||
79a8557a YM |
1659 | if (val & IGU_PF_CONF_INT_LINE_EN) |
1660 | pci_intx(bp->pdev, true); | |
1661 | ||
f2e0899f DK |
1662 | barrier(); |
1663 | ||
1664 | /* init leading/trailing edge */ | |
1665 | if (IS_MF(bp)) { | |
3395a033 | 1666 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1667 | if (bp->port.pmf) |
1668 | /* enable nig and gpio3 attention */ | |
1669 | val |= 0x1100; | |
1670 | } else | |
1671 | val = 0xffff; | |
1672 | ||
1673 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1674 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1675 | ||
1676 | /* Make sure that interrupts are indeed enabled from here on */ | |
1677 | mmiowb(); | |
1678 | } | |
1679 | ||
1680 | void bnx2x_int_enable(struct bnx2x *bp) | |
1681 | { | |
1682 | if (bp->common.int_block == INT_BLOCK_HC) | |
1683 | bnx2x_hc_int_enable(bp); | |
1684 | else | |
1685 | bnx2x_igu_int_enable(bp); | |
1686 | } | |
1687 | ||
9f6c9258 | 1688 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1689 | { |
a2fbb9ea | 1690 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1691 | int i, offset; |
a2fbb9ea | 1692 | |
f8ef6e44 YG |
1693 | if (disable_hw) |
1694 | /* prevent the HW from sending interrupts */ | |
1695 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1696 | |
1697 | /* make sure all ISRs are done */ | |
1698 | if (msix) { | |
8badd27a EG |
1699 | synchronize_irq(bp->msix_table[0].vector); |
1700 | offset = 1; | |
55c11941 MS |
1701 | if (CNIC_SUPPORT(bp)) |
1702 | offset++; | |
ec6ba945 | 1703 | for_each_eth_queue(bp, i) |
754a2f52 | 1704 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1705 | } else |
1706 | synchronize_irq(bp->pdev->irq); | |
1707 | ||
1708 | /* make sure sp_task is not running */ | |
1cf167f2 | 1709 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1710 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1711 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1712 | } |
1713 | ||
34f80b04 | 1714 | /* fast path */ |
a2fbb9ea ET |
1715 | |
1716 | /* | |
34f80b04 | 1717 | * General service functions |
a2fbb9ea ET |
1718 | */ |
1719 | ||
72fd0718 VZ |
1720 | /* Return true if succeeded to acquire the lock */ |
1721 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1722 | { | |
1723 | u32 lock_status; | |
1724 | u32 resource_bit = (1 << resource); | |
1725 | int func = BP_FUNC(bp); | |
1726 | u32 hw_lock_control_reg; | |
1727 | ||
51c1a580 MS |
1728 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1729 | "Trying to take a lock on resource %d\n", resource); | |
72fd0718 VZ |
1730 | |
1731 | /* Validating that the resource is within range */ | |
1732 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1733 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
72fd0718 VZ |
1734 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
1735 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1736 | return false; |
72fd0718 VZ |
1737 | } |
1738 | ||
1739 | if (func <= 5) | |
1740 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1741 | else | |
1742 | hw_lock_control_reg = | |
1743 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1744 | ||
1745 | /* Try to acquire the lock */ | |
1746 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1747 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1748 | if (lock_status & resource_bit) | |
1749 | return true; | |
1750 | ||
51c1a580 MS |
1751 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1752 | "Failed to get a lock on resource %d\n", resource); | |
72fd0718 VZ |
1753 | return false; |
1754 | } | |
1755 | ||
c9ee9206 VZ |
1756 | /** |
1757 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1758 | * | |
1759 | * @bp: driver handle | |
1760 | * | |
1761 | * Returns the recovery leader resource id according to the engine this function | |
1762 | * belongs to. Currently only only 2 engines is supported. | |
1763 | */ | |
1191cb83 | 1764 | static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) |
c9ee9206 VZ |
1765 | { |
1766 | if (BP_PATH(bp)) | |
1767 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1768 | else | |
1769 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1770 | } | |
1771 | ||
1772 | /** | |
2de67439 | 1773 | * bnx2x_trylock_leader_lock- try to acquire a leader lock. |
c9ee9206 VZ |
1774 | * |
1775 | * @bp: driver handle | |
1776 | * | |
2de67439 | 1777 | * Tries to acquire a leader lock for current engine. |
c9ee9206 | 1778 | */ |
1191cb83 | 1779 | static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) |
c9ee9206 VZ |
1780 | { |
1781 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1782 | } | |
1783 | ||
619c5cb6 | 1784 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
55c11941 | 1785 | |
fd1fc79d AE |
1786 | /* schedule the sp task and mark that interrupt occurred (runs from ISR) */ |
1787 | static int bnx2x_schedule_sp_task(struct bnx2x *bp) | |
1788 | { | |
1789 | /* Set the interrupt occurred bit for the sp-task to recognize it | |
1790 | * must ack the interrupt and transition according to the IGU | |
1791 | * state machine. | |
1792 | */ | |
1793 | atomic_set(&bp->interrupt_occurred, 1); | |
1794 | ||
1795 | /* The sp_task must execute only after this bit | |
1796 | * is set, otherwise we will get out of sync and miss all | |
1797 | * further interrupts. Hence, the barrier. | |
1798 | */ | |
1799 | smp_wmb(); | |
1800 | ||
1801 | /* schedule sp_task to workqueue */ | |
1802 | return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); | |
1803 | } | |
3196a88a | 1804 | |
619c5cb6 | 1805 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1806 | { |
1807 | struct bnx2x *bp = fp->bp; | |
1808 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1809 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 | 1810 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
15192a8c | 1811 | struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a2fbb9ea | 1812 | |
34f80b04 | 1813 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1814 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1815 | fp->index, cid, command, bp->state, |
34f80b04 | 1816 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1817 | |
fd1fc79d AE |
1818 | /* If cid is within VF range, replace the slowpath object with the |
1819 | * one corresponding to this VF | |
1820 | */ | |
1821 | if (cid >= BNX2X_FIRST_VF_CID && | |
1822 | cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) | |
1823 | bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); | |
1824 | ||
619c5cb6 VZ |
1825 | switch (command) { |
1826 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1827 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1828 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1829 | break; | |
d6cae238 | 1830 | |
619c5cb6 | 1831 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1832 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1833 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1834 | break; |
1835 | ||
6383c0b3 | 1836 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
51c1a580 | 1837 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
6383c0b3 AE |
1838 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
1839 | break; | |
1840 | ||
619c5cb6 | 1841 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1842 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1843 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1844 | break; |
1845 | ||
619c5cb6 | 1846 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
6bf07b8e | 1847 | DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid); |
619c5cb6 | 1848 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1849 | break; |
1850 | ||
619c5cb6 | 1851 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1852 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1853 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1854 | break; |
619c5cb6 | 1855 | |
14a94ebd MK |
1856 | case (RAMROD_CMD_ID_ETH_TPA_UPDATE): |
1857 | DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid); | |
1858 | drv_cmd = BNX2X_Q_CMD_UPDATE_TPA; | |
1859 | break; | |
1860 | ||
619c5cb6 VZ |
1861 | default: |
1862 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1863 | command, fp->index); | |
1864 | return; | |
523224a3 | 1865 | } |
3196a88a | 1866 | |
619c5cb6 VZ |
1867 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1868 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1869 | /* q_obj->complete_cmd() failure means that this was | |
1870 | * an unexpected completion. | |
1871 | * | |
1872 | * In this case we don't want to increase the bp->spq_left | |
1873 | * because apparently we haven't sent this command the first | |
1874 | * place. | |
1875 | */ | |
1876 | #ifdef BNX2X_STOP_ON_ERROR | |
1877 | bnx2x_panic(); | |
1878 | #else | |
1879 | return; | |
1880 | #endif | |
1881 | ||
4e857c58 | 1882 | smp_mb__before_atomic(); |
6e30dd4e | 1883 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 | 1884 | /* push the change in bp->spq_left and towards the memory */ |
4e857c58 | 1885 | smp_mb__after_atomic(); |
49d66772 | 1886 | |
d6cae238 VZ |
1887 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1888 | ||
a3348722 BW |
1889 | if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && |
1890 | (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { | |
1891 | /* if Q update ramrod is completed for last Q in AFEX vif set | |
1892 | * flow, then ACK MCP at the end | |
1893 | * | |
1894 | * mark pending ACK to MCP bit. | |
1895 | * prevent case that both bits are cleared. | |
1896 | * At the end of load/unload driver checks that | |
2de67439 | 1897 | * sp_state is cleared, and this order prevents |
a3348722 BW |
1898 | * races |
1899 | */ | |
4e857c58 | 1900 | smp_mb__before_atomic(); |
a3348722 BW |
1901 | set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); |
1902 | wmb(); | |
1903 | clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
4e857c58 | 1904 | smp_mb__after_atomic(); |
a3348722 | 1905 | |
fd1fc79d AE |
1906 | /* schedule the sp task as mcp ack is required */ |
1907 | bnx2x_schedule_sp_task(bp); | |
a3348722 BW |
1908 | } |
1909 | ||
523224a3 | 1910 | return; |
a2fbb9ea ET |
1911 | } |
1912 | ||
9f6c9258 | 1913 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1914 | { |
555f6c78 | 1915 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1916 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1917 | u16 mask; |
ca00392c | 1918 | int i; |
6383c0b3 | 1919 | u8 cos; |
a2fbb9ea | 1920 | |
34f80b04 | 1921 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1922 | if (unlikely(status == 0)) { |
1923 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1924 | return IRQ_NONE; | |
1925 | } | |
f5372251 | 1926 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1927 | |
3196a88a EG |
1928 | #ifdef BNX2X_STOP_ON_ERROR |
1929 | if (unlikely(bp->panic)) | |
1930 | return IRQ_HANDLED; | |
1931 | #endif | |
1932 | ||
ec6ba945 | 1933 | for_each_eth_queue(bp, i) { |
ca00392c | 1934 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1935 | |
55c11941 | 1936 | mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); |
ca00392c | 1937 | if (status & mask) { |
619c5cb6 | 1938 | /* Handle Rx or Tx according to SB id */ |
6383c0b3 | 1939 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 1940 | prefetch(fp->txdata_ptr[cos]->tx_cons_sb); |
523224a3 | 1941 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
f5fbf115 | 1942 | napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1943 | status &= ~mask; |
1944 | } | |
a2fbb9ea ET |
1945 | } |
1946 | ||
55c11941 MS |
1947 | if (CNIC_SUPPORT(bp)) { |
1948 | mask = 0x2; | |
1949 | if (status & (mask | 0x1)) { | |
1950 | struct cnic_ops *c_ops = NULL; | |
993ac7b5 | 1951 | |
ad9b4359 MC |
1952 | rcu_read_lock(); |
1953 | c_ops = rcu_dereference(bp->cnic_ops); | |
1954 | if (c_ops && (bp->cnic_eth_dev.drv_state & | |
1955 | CNIC_DRV_STATE_HANDLES_IRQ)) | |
1956 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1957 | rcu_read_unlock(); | |
993ac7b5 | 1958 | |
55c11941 MS |
1959 | status &= ~mask; |
1960 | } | |
993ac7b5 | 1961 | } |
a2fbb9ea | 1962 | |
34f80b04 | 1963 | if (unlikely(status & 0x1)) { |
fd1fc79d AE |
1964 | |
1965 | /* schedule sp task to perform default status block work, ack | |
1966 | * attentions and enable interrupts. | |
1967 | */ | |
1968 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
1969 | |
1970 | status &= ~0x1; | |
1971 | if (!status) | |
1972 | return IRQ_HANDLED; | |
1973 | } | |
1974 | ||
cdaa7cb8 VZ |
1975 | if (unlikely(status)) |
1976 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1977 | status); |
a2fbb9ea | 1978 | |
c18487ee | 1979 | return IRQ_HANDLED; |
a2fbb9ea ET |
1980 | } |
1981 | ||
c18487ee YR |
1982 | /* Link */ |
1983 | ||
1984 | /* | |
1985 | * General service functions | |
1986 | */ | |
a2fbb9ea | 1987 | |
9f6c9258 | 1988 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1989 | { |
1990 | u32 lock_status; | |
1991 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1992 | int func = BP_FUNC(bp); |
1993 | u32 hw_lock_control_reg; | |
c18487ee | 1994 | int cnt; |
a2fbb9ea | 1995 | |
c18487ee YR |
1996 | /* Validating that the resource is within range */ |
1997 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1998 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1999 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
2000 | return -EINVAL; | |
2001 | } | |
a2fbb9ea | 2002 | |
4a37fb66 YG |
2003 | if (func <= 5) { |
2004 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
2005 | } else { | |
2006 | hw_lock_control_reg = | |
2007 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
2008 | } | |
2009 | ||
c18487ee | 2010 | /* Validating that the resource is not already taken */ |
4a37fb66 | 2011 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 2012 | if (lock_status & resource_bit) { |
51c1a580 | 2013 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
c18487ee YR |
2014 | lock_status, resource_bit); |
2015 | return -EEXIST; | |
2016 | } | |
a2fbb9ea | 2017 | |
46230476 EG |
2018 | /* Try for 5 second every 5ms */ |
2019 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 2020 | /* Try to acquire the lock */ |
4a37fb66 YG |
2021 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
2022 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
2023 | if (lock_status & resource_bit) |
2024 | return 0; | |
a2fbb9ea | 2025 | |
639d65b8 | 2026 | usleep_range(5000, 10000); |
a2fbb9ea | 2027 | } |
51c1a580 | 2028 | BNX2X_ERR("Timeout\n"); |
c18487ee YR |
2029 | return -EAGAIN; |
2030 | } | |
a2fbb9ea | 2031 | |
c9ee9206 VZ |
2032 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
2033 | { | |
2034 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
2035 | } | |
2036 | ||
9f6c9258 | 2037 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
2038 | { |
2039 | u32 lock_status; | |
2040 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
2041 | int func = BP_FUNC(bp); |
2042 | u32 hw_lock_control_reg; | |
a2fbb9ea | 2043 | |
c18487ee YR |
2044 | /* Validating that the resource is within range */ |
2045 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 2046 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
2047 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
2048 | return -EINVAL; | |
2049 | } | |
2050 | ||
4a37fb66 YG |
2051 | if (func <= 5) { |
2052 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
2053 | } else { | |
2054 | hw_lock_control_reg = | |
2055 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
2056 | } | |
2057 | ||
c18487ee | 2058 | /* Validating that the resource is currently taken */ |
4a37fb66 | 2059 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 2060 | if (!(lock_status & resource_bit)) { |
6bf07b8e YM |
2061 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n", |
2062 | lock_status, resource_bit); | |
c18487ee | 2063 | return -EFAULT; |
a2fbb9ea ET |
2064 | } |
2065 | ||
9f6c9258 DK |
2066 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
2067 | return 0; | |
c18487ee | 2068 | } |
a2fbb9ea | 2069 | |
4acac6a5 EG |
2070 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
2071 | { | |
2072 | /* The GPIO should be swapped if swap register is set and active */ | |
2073 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2074 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2075 | int gpio_shift = gpio_num + | |
2076 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2077 | u32 gpio_mask = (1 << gpio_shift); | |
2078 | u32 gpio_reg; | |
2079 | int value; | |
2080 | ||
2081 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2082 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2083 | return -EINVAL; | |
2084 | } | |
2085 | ||
2086 | /* read GPIO value */ | |
2087 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2088 | ||
2089 | /* get the requested pin value */ | |
2090 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
2091 | value = 1; | |
2092 | else | |
2093 | value = 0; | |
2094 | ||
4acac6a5 EG |
2095 | return value; |
2096 | } | |
2097 | ||
17de50b7 | 2098 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
2099 | { |
2100 | /* The GPIO should be swapped if swap register is set and active */ | |
2101 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 2102 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
2103 | int gpio_shift = gpio_num + |
2104 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2105 | u32 gpio_mask = (1 << gpio_shift); | |
2106 | u32 gpio_reg; | |
a2fbb9ea | 2107 | |
c18487ee YR |
2108 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
2109 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2110 | return -EINVAL; | |
2111 | } | |
a2fbb9ea | 2112 | |
4a37fb66 | 2113 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
2114 | /* read GPIO and mask except the float bits */ |
2115 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 2116 | |
c18487ee YR |
2117 | switch (mode) { |
2118 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
51c1a580 MS |
2119 | DP(NETIF_MSG_LINK, |
2120 | "Set GPIO %d (shift %d) -> output low\n", | |
c18487ee YR |
2121 | gpio_num, gpio_shift); |
2122 | /* clear FLOAT and set CLR */ | |
2123 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2124 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
2125 | break; | |
a2fbb9ea | 2126 | |
c18487ee | 2127 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
51c1a580 MS |
2128 | DP(NETIF_MSG_LINK, |
2129 | "Set GPIO %d (shift %d) -> output high\n", | |
c18487ee YR |
2130 | gpio_num, gpio_shift); |
2131 | /* clear FLOAT and set SET */ | |
2132 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2133 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
2134 | break; | |
a2fbb9ea | 2135 | |
17de50b7 | 2136 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
51c1a580 MS |
2137 | DP(NETIF_MSG_LINK, |
2138 | "Set GPIO %d (shift %d) -> input\n", | |
c18487ee YR |
2139 | gpio_num, gpio_shift); |
2140 | /* set FLOAT */ | |
2141 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2142 | break; | |
a2fbb9ea | 2143 | |
c18487ee YR |
2144 | default: |
2145 | break; | |
a2fbb9ea ET |
2146 | } |
2147 | ||
c18487ee | 2148 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 2149 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 2150 | |
c18487ee | 2151 | return 0; |
a2fbb9ea ET |
2152 | } |
2153 | ||
0d40f0d4 YR |
2154 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
2155 | { | |
2156 | u32 gpio_reg = 0; | |
2157 | int rc = 0; | |
2158 | ||
2159 | /* Any port swapping should be handled by caller. */ | |
2160 | ||
2161 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2162 | /* read GPIO and mask except the float bits */ | |
2163 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2164 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2165 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2166 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
2167 | ||
2168 | switch (mode) { | |
2169 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
2170 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
2171 | /* set CLR */ | |
2172 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2173 | break; | |
2174 | ||
2175 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
2176 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
2177 | /* set SET */ | |
2178 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
2179 | break; | |
2180 | ||
2181 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
2182 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
2183 | /* set FLOAT */ | |
2184 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2185 | break; | |
2186 | ||
2187 | default: | |
2188 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
2189 | rc = -EINVAL; | |
2190 | break; | |
2191 | } | |
2192 | ||
2193 | if (rc == 0) | |
2194 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
2195 | ||
2196 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2197 | ||
2198 | return rc; | |
2199 | } | |
2200 | ||
4acac6a5 EG |
2201 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
2202 | { | |
2203 | /* The GPIO should be swapped if swap register is set and active */ | |
2204 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2205 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2206 | int gpio_shift = gpio_num + | |
2207 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2208 | u32 gpio_mask = (1 << gpio_shift); | |
2209 | u32 gpio_reg; | |
2210 | ||
2211 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2212 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2213 | return -EINVAL; | |
2214 | } | |
2215 | ||
2216 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2217 | /* read GPIO int */ | |
2218 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
2219 | ||
2220 | switch (mode) { | |
2221 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
51c1a580 MS |
2222 | DP(NETIF_MSG_LINK, |
2223 | "Clear GPIO INT %d (shift %d) -> output low\n", | |
2224 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2225 | /* clear SET and set CLR */ |
2226 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2227 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2228 | break; | |
2229 | ||
2230 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
51c1a580 MS |
2231 | DP(NETIF_MSG_LINK, |
2232 | "Set GPIO INT %d (shift %d) -> output high\n", | |
2233 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2234 | /* clear CLR and set SET */ |
2235 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2236 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2237 | break; | |
2238 | ||
2239 | default: | |
2240 | break; | |
2241 | } | |
2242 | ||
2243 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2244 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2245 | ||
2246 | return 0; | |
2247 | } | |
2248 | ||
d6d99a3f | 2249 | static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) |
a2fbb9ea | 2250 | { |
c18487ee | 2251 | u32 spio_reg; |
a2fbb9ea | 2252 | |
d6d99a3f YM |
2253 | /* Only 2 SPIOs are configurable */ |
2254 | if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { | |
2255 | BNX2X_ERR("Invalid SPIO 0x%x\n", spio); | |
c18487ee | 2256 | return -EINVAL; |
a2fbb9ea ET |
2257 | } |
2258 | ||
4a37fb66 | 2259 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2260 | /* read SPIO and mask except the float bits */ |
d6d99a3f | 2261 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); |
a2fbb9ea | 2262 | |
c18487ee | 2263 | switch (mode) { |
d6d99a3f YM |
2264 | case MISC_SPIO_OUTPUT_LOW: |
2265 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); | |
c18487ee | 2266 | /* clear FLOAT and set CLR */ |
d6d99a3f YM |
2267 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2268 | spio_reg |= (spio << MISC_SPIO_CLR_POS); | |
c18487ee | 2269 | break; |
a2fbb9ea | 2270 | |
d6d99a3f YM |
2271 | case MISC_SPIO_OUTPUT_HIGH: |
2272 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); | |
c18487ee | 2273 | /* clear FLOAT and set SET */ |
d6d99a3f YM |
2274 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2275 | spio_reg |= (spio << MISC_SPIO_SET_POS); | |
c18487ee | 2276 | break; |
a2fbb9ea | 2277 | |
d6d99a3f YM |
2278 | case MISC_SPIO_INPUT_HI_Z: |
2279 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); | |
c18487ee | 2280 | /* set FLOAT */ |
d6d99a3f | 2281 | spio_reg |= (spio << MISC_SPIO_FLOAT_POS); |
c18487ee | 2282 | break; |
a2fbb9ea | 2283 | |
c18487ee YR |
2284 | default: |
2285 | break; | |
a2fbb9ea ET |
2286 | } |
2287 | ||
c18487ee | 2288 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2289 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2290 | |
a2fbb9ea ET |
2291 | return 0; |
2292 | } | |
2293 | ||
9f6c9258 | 2294 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2295 | { |
a22f0788 | 2296 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
1359d73c YM |
2297 | |
2298 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | | |
2299 | ADVERTISED_Pause); | |
ad33ea3a EG |
2300 | switch (bp->link_vars.ieee_fc & |
2301 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2302 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2303 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2304 | ADVERTISED_Pause); |
c18487ee | 2305 | break; |
356e2385 | 2306 | |
c18487ee | 2307 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2308 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2309 | break; |
356e2385 | 2310 | |
c18487ee | 2311 | default: |
c18487ee YR |
2312 | break; |
2313 | } | |
2314 | } | |
f1410647 | 2315 | |
cd1dfce2 | 2316 | static void bnx2x_set_requested_fc(struct bnx2x *bp) |
c18487ee | 2317 | { |
cd1dfce2 YM |
2318 | /* Initialize link parameters structure variables |
2319 | * It is recommended to turn off RX FC for jumbo frames | |
2320 | * for better performance | |
2321 | */ | |
2322 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
2323 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; | |
2324 | else | |
2325 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; | |
2326 | } | |
a2fbb9ea | 2327 | |
9156b30b DK |
2328 | static void bnx2x_init_dropless_fc(struct bnx2x *bp) |
2329 | { | |
2330 | u32 pause_enabled = 0; | |
2331 | ||
2332 | if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { | |
2333 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2334 | pause_enabled = 1; | |
2335 | ||
2336 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
2337 | USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), | |
2338 | pause_enabled); | |
2339 | } | |
2340 | ||
2341 | DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n", | |
2342 | pause_enabled ? "enabled" : "disabled"); | |
2343 | } | |
2344 | ||
cd1dfce2 YM |
2345 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
2346 | { | |
2347 | int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); | |
2348 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
2349 | ||
2350 | if (!BP_NOMCP(bp)) { | |
2351 | bnx2x_set_requested_fc(bp); | |
4a37fb66 | 2352 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2353 | |
a22f0788 | 2354 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2355 | struct link_params *lp = &bp->link_params; |
2356 | lp->loopback_mode = LOOPBACK_XGXS; | |
2f43b821 YM |
2357 | /* Prefer doing PHY loopback at highest speed */ |
2358 | if (lp->req_line_speed[cfx_idx] < SPEED_20000) { | |
1cb0c788 | 2359 | if (lp->speed_cap_mask[cfx_idx] & |
2f43b821 | 2360 | PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) |
1cb0c788 | 2361 | lp->req_line_speed[cfx_idx] = |
2f43b821 YM |
2362 | SPEED_20000; |
2363 | else if (lp->speed_cap_mask[cfx_idx] & | |
2364 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2365 | lp->req_line_speed[cfx_idx] = | |
2366 | SPEED_10000; | |
1cb0c788 YR |
2367 | else |
2368 | lp->req_line_speed[cfx_idx] = | |
2369 | SPEED_1000; | |
2370 | } | |
a22f0788 | 2371 | } |
b5bf9068 | 2372 | |
8970b2e4 MS |
2373 | if (load_mode == LOAD_LOOPBACK_EXT) { |
2374 | struct link_params *lp = &bp->link_params; | |
2375 | lp->loopback_mode = LOOPBACK_EXT; | |
2376 | } | |
2377 | ||
19680c48 | 2378 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2379 | |
4a37fb66 | 2380 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2381 | |
9156b30b DK |
2382 | bnx2x_init_dropless_fc(bp); |
2383 | ||
3c96c68b EG |
2384 | bnx2x_calc_fc_adv(bp); |
2385 | ||
cd1dfce2 | 2386 | if (bp->link_vars.link_up) { |
b5bf9068 | 2387 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
19680c48 | 2388 | bnx2x_link_report(bp); |
cd1dfce2 YM |
2389 | } |
2390 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2391 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2392 | return rc; |
2393 | } | |
f5372251 | 2394 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2395 | return -EINVAL; |
a2fbb9ea ET |
2396 | } |
2397 | ||
9f6c9258 | 2398 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2399 | { |
19680c48 | 2400 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2401 | bnx2x_acquire_phy_lock(bp); |
19680c48 | 2402 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2403 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2404 | |
9156b30b DK |
2405 | bnx2x_init_dropless_fc(bp); |
2406 | ||
19680c48 EG |
2407 | bnx2x_calc_fc_adv(bp); |
2408 | } else | |
f5372251 | 2409 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2410 | } |
a2fbb9ea | 2411 | |
c18487ee YR |
2412 | static void bnx2x__link_reset(struct bnx2x *bp) |
2413 | { | |
19680c48 | 2414 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2415 | bnx2x_acquire_phy_lock(bp); |
5d07d868 | 2416 | bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2417 | bnx2x_release_phy_lock(bp); |
19680c48 | 2418 | } else |
f5372251 | 2419 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2420 | } |
a2fbb9ea | 2421 | |
5d07d868 YM |
2422 | void bnx2x_force_link_reset(struct bnx2x *bp) |
2423 | { | |
2424 | bnx2x_acquire_phy_lock(bp); | |
2425 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); | |
2426 | bnx2x_release_phy_lock(bp); | |
2427 | } | |
2428 | ||
a22f0788 | 2429 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2430 | { |
2145a920 | 2431 | u8 rc = 0; |
a2fbb9ea | 2432 | |
2145a920 VZ |
2433 | if (!BP_NOMCP(bp)) { |
2434 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2435 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2436 | is_serdes); | |
2145a920 VZ |
2437 | bnx2x_release_phy_lock(bp); |
2438 | } else | |
2439 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2440 | |
c18487ee YR |
2441 | return rc; |
2442 | } | |
a2fbb9ea | 2443 | |
2691d51d EG |
2444 | /* Calculates the sum of vn_min_rates. |
2445 | It's needed for further normalizing of the min_rates. | |
2446 | Returns: | |
2447 | sum of vn_min_rates. | |
2448 | or | |
2449 | 0 - if all the min_rates are 0. | |
16a5fd92 | 2450 | In the later case fairness algorithm should be deactivated. |
2691d51d EG |
2451 | If not all min_rates are zero then those that are zeroes will be set to 1. |
2452 | */ | |
b475d78f YM |
2453 | static void bnx2x_calc_vn_min(struct bnx2x *bp, |
2454 | struct cmng_init_input *input) | |
2691d51d EG |
2455 | { |
2456 | int all_zero = 1; | |
2691d51d EG |
2457 | int vn; |
2458 | ||
3395a033 | 2459 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2460 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2461 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2462 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2463 | ||
2464 | /* Skip hidden vns */ | |
2465 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
b475d78f | 2466 | vn_min_rate = 0; |
2691d51d | 2467 | /* If min rate is zero - set it to 1 */ |
b475d78f | 2468 | else if (!vn_min_rate) |
2691d51d EG |
2469 | vn_min_rate = DEF_MIN_RATE; |
2470 | else | |
2471 | all_zero = 0; | |
2472 | ||
b475d78f | 2473 | input->vnic_min_rate[vn] = vn_min_rate; |
2691d51d EG |
2474 | } |
2475 | ||
30ae438b DK |
2476 | /* if ETS or all min rates are zeros - disable fairness */ |
2477 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
b475d78f | 2478 | input->flags.cmng_enables &= |
30ae438b DK |
2479 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2480 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2481 | } else if (all_zero) { | |
b475d78f | 2482 | input->flags.cmng_enables &= |
b015e3d1 | 2483 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
b475d78f YM |
2484 | DP(NETIF_MSG_IFUP, |
2485 | "All MIN values are zeroes fairness will be disabled\n"); | |
b015e3d1 | 2486 | } else |
b475d78f | 2487 | input->flags.cmng_enables |= |
b015e3d1 | 2488 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2691d51d EG |
2489 | } |
2490 | ||
b475d78f YM |
2491 | static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, |
2492 | struct cmng_init_input *input) | |
34f80b04 | 2493 | { |
b475d78f | 2494 | u16 vn_max_rate; |
f2e0899f | 2495 | u32 vn_cfg = bp->mf_config[vn]; |
34f80b04 | 2496 | |
b475d78f | 2497 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
34f80b04 | 2498 | vn_max_rate = 0; |
b475d78f | 2499 | else { |
faa6fcbb DK |
2500 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2501 | ||
da3cc2da | 2502 | if (IS_MF_PERCENT_BW(bp)) { |
faa6fcbb DK |
2503 | /* maxCfg in percents of linkspeed */ |
2504 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
b475d78f | 2505 | } else /* SD modes */ |
faa6fcbb DK |
2506 | /* maxCfg is absolute in 100Mb units */ |
2507 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2508 | } |
f85582f8 | 2509 | |
b475d78f | 2510 | DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); |
34f80b04 | 2511 | |
b475d78f | 2512 | input->vnic_max_rate[vn] = vn_max_rate; |
34f80b04 | 2513 | } |
f85582f8 | 2514 | |
523224a3 DK |
2515 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2516 | { | |
2517 | if (CHIP_REV_IS_SLOW(bp)) | |
2518 | return CMNG_FNS_NONE; | |
fb3bff17 | 2519 | if (IS_MF(bp)) |
523224a3 DK |
2520 | return CMNG_FNS_MINMAX; |
2521 | ||
2522 | return CMNG_FNS_NONE; | |
2523 | } | |
2524 | ||
2ae17f66 | 2525 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2526 | { |
0793f83f | 2527 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2528 | |
2529 | if (BP_NOMCP(bp)) | |
16a5fd92 | 2530 | return; /* what should be the default value in this case */ |
523224a3 | 2531 | |
0793f83f DK |
2532 | /* For 2 port configuration the absolute function number formula |
2533 | * is: | |
2534 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2535 | * | |
2536 | * and there are 4 functions per port | |
2537 | * | |
2538 | * For 4 port configuration it is | |
2539 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2540 | * | |
2541 | * and there are 2 functions per port | |
2542 | */ | |
3395a033 | 2543 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2544 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2545 | ||
2546 | if (func >= E1H_FUNC_MAX) | |
2547 | break; | |
2548 | ||
f2e0899f | 2549 | bp->mf_config[vn] = |
523224a3 DK |
2550 | MF_CFG_RD(bp, func_mf_config[func].config); |
2551 | } | |
a3348722 BW |
2552 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
2553 | DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); | |
2554 | bp->flags |= MF_FUNC_DIS; | |
2555 | } else { | |
2556 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2557 | bp->flags &= ~MF_FUNC_DIS; | |
2558 | } | |
523224a3 DK |
2559 | } |
2560 | ||
2561 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2562 | { | |
b475d78f YM |
2563 | struct cmng_init_input input; |
2564 | memset(&input, 0, sizeof(struct cmng_init_input)); | |
2565 | ||
2566 | input.port_rate = bp->link_vars.line_speed; | |
523224a3 | 2567 | |
568e2426 | 2568 | if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) { |
523224a3 DK |
2569 | int vn; |
2570 | ||
523224a3 DK |
2571 | /* read mf conf from shmem */ |
2572 | if (read_cfg) | |
2573 | bnx2x_read_mf_cfg(bp); | |
2574 | ||
523224a3 | 2575 | /* vn_weight_sum and enable fairness if not 0 */ |
b475d78f | 2576 | bnx2x_calc_vn_min(bp, &input); |
523224a3 DK |
2577 | |
2578 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2579 | if (bp->port.pmf) |
3395a033 | 2580 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
b475d78f | 2581 | bnx2x_calc_vn_max(bp, vn, &input); |
523224a3 DK |
2582 | |
2583 | /* always enable rate shaping and fairness */ | |
b475d78f | 2584 | input.flags.cmng_enables |= |
523224a3 | 2585 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; |
b475d78f YM |
2586 | |
2587 | bnx2x_init_cmng(&input, &bp->cmng); | |
523224a3 DK |
2588 | return; |
2589 | } | |
2590 | ||
2591 | /* rate shaping and fairness are disabled */ | |
2592 | DP(NETIF_MSG_IFUP, | |
2593 | "rate shaping and fairness are disabled\n"); | |
2594 | } | |
34f80b04 | 2595 | |
1191cb83 ED |
2596 | static void storm_memset_cmng(struct bnx2x *bp, |
2597 | struct cmng_init *cmng, | |
2598 | u8 port) | |
2599 | { | |
2600 | int vn; | |
2601 | size_t size = sizeof(struct cmng_struct_per_port); | |
2602 | ||
2603 | u32 addr = BAR_XSTRORM_INTMEM + | |
2604 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
2605 | ||
2606 | __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); | |
2607 | ||
2608 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
2609 | int func = func_by_vn(bp, vn); | |
2610 | ||
2611 | addr = BAR_XSTRORM_INTMEM + | |
2612 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); | |
2613 | size = sizeof(struct rate_shaping_vars_per_vn); | |
2614 | __storm_memset_struct(bp, addr, size, | |
2615 | (u32 *)&cmng->vnic.vnic_max_rate[vn]); | |
2616 | ||
2617 | addr = BAR_XSTRORM_INTMEM + | |
2618 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); | |
2619 | size = sizeof(struct fairness_vars_per_vn); | |
2620 | __storm_memset_struct(bp, addr, size, | |
2621 | (u32 *)&cmng->vnic.vnic_min_rate[vn]); | |
2622 | } | |
2623 | } | |
2624 | ||
568e2426 DK |
2625 | /* init cmng mode in HW according to local configuration */ |
2626 | void bnx2x_set_local_cmng(struct bnx2x *bp) | |
2627 | { | |
2628 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
2629 | ||
2630 | if (cmng_fns != CMNG_FNS_NONE) { | |
2631 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2632 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2633 | } else { | |
2634 | /* rate shaping and fairness are disabled */ | |
2635 | DP(NETIF_MSG_IFUP, | |
2636 | "single function mode without fairness\n"); | |
2637 | } | |
2638 | } | |
2639 | ||
c18487ee YR |
2640 | /* This function is called upon link interrupt */ |
2641 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2642 | { | |
bb2a0f7a YG |
2643 | /* Make sure that we are synced with the current statistics */ |
2644 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2645 | ||
c18487ee | 2646 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2647 | |
9156b30b | 2648 | bnx2x_init_dropless_fc(bp); |
1c06328c | 2649 | |
9156b30b | 2650 | if (bp->link_vars.link_up) { |
1c06328c | 2651 | |
619c5cb6 | 2652 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2653 | struct host_port_stats *pstats; |
2654 | ||
2655 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2656 | /* reset old mac stats */ |
bb2a0f7a YG |
2657 | memset(&(pstats->mac_stx[0]), 0, |
2658 | sizeof(struct mac_stx)); | |
2659 | } | |
f34d28ea | 2660 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2661 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2662 | } | |
2663 | ||
568e2426 DK |
2664 | if (bp->link_vars.link_up && bp->link_vars.line_speed) |
2665 | bnx2x_set_local_cmng(bp); | |
9fdc3e95 | 2666 | |
2ae17f66 VZ |
2667 | __bnx2x_link_report(bp); |
2668 | ||
9fdc3e95 DK |
2669 | if (IS_MF(bp)) |
2670 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2671 | } |
a2fbb9ea | 2672 | |
9f6c9258 | 2673 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2674 | { |
2ae17f66 | 2675 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2676 | return; |
a2fbb9ea | 2677 | |
00253a8c | 2678 | /* read updated dcb configuration */ |
ad5afc89 AE |
2679 | if (IS_PF(bp)) { |
2680 | bnx2x_dcbx_pmf_update(bp); | |
2681 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); | |
2682 | if (bp->link_vars.link_up) | |
2683 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2684 | else | |
2685 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2686 | /* indicate link status */ | |
2687 | bnx2x_link_report(bp); | |
a2fbb9ea | 2688 | |
ad5afc89 AE |
2689 | } else { /* VF */ |
2690 | bp->port.supported[0] |= (SUPPORTED_10baseT_Half | | |
2691 | SUPPORTED_10baseT_Full | | |
2692 | SUPPORTED_100baseT_Half | | |
2693 | SUPPORTED_100baseT_Full | | |
2694 | SUPPORTED_1000baseT_Full | | |
2695 | SUPPORTED_2500baseX_Full | | |
2696 | SUPPORTED_10000baseT_Full | | |
2697 | SUPPORTED_TP | | |
2698 | SUPPORTED_FIBRE | | |
2699 | SUPPORTED_Autoneg | | |
2700 | SUPPORTED_Pause | | |
2701 | SUPPORTED_Asym_Pause); | |
2702 | bp->port.advertising[0] = bp->port.supported[0]; | |
2703 | ||
2704 | bp->link_params.bp = bp; | |
2705 | bp->link_params.port = BP_PORT(bp); | |
2706 | bp->link_params.req_duplex[0] = DUPLEX_FULL; | |
2707 | bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; | |
2708 | bp->link_params.req_line_speed[0] = SPEED_10000; | |
2709 | bp->link_params.speed_cap_mask[0] = 0x7f0000; | |
2710 | bp->link_params.switch_cfg = SWITCH_CFG_10G; | |
2711 | bp->link_vars.mac_type = MAC_TYPE_BMAC; | |
2712 | bp->link_vars.line_speed = SPEED_10000; | |
2713 | bp->link_vars.link_status = | |
2714 | (LINK_STATUS_LINK_UP | | |
2715 | LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); | |
2716 | bp->link_vars.link_up = 1; | |
2717 | bp->link_vars.duplex = DUPLEX_FULL; | |
2718 | bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
2719 | __bnx2x_link_report(bp); | |
6495d15a DK |
2720 | |
2721 | bnx2x_sample_bulletin(bp); | |
2722 | ||
2723 | /* if bulletin board did not have an update for link status | |
2724 | * __bnx2x_link_report will report current status | |
2725 | * but it will NOT duplicate report in case of already reported | |
2726 | * during sampling bulletin board. | |
2727 | */ | |
bb2a0f7a | 2728 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
ad5afc89 | 2729 | } |
a2fbb9ea | 2730 | } |
a2fbb9ea | 2731 | |
a3348722 BW |
2732 | static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, |
2733 | u16 vlan_val, u8 allowed_prio) | |
2734 | { | |
86564c3f | 2735 | struct bnx2x_func_state_params func_params = {NULL}; |
a3348722 BW |
2736 | struct bnx2x_func_afex_update_params *f_update_params = |
2737 | &func_params.params.afex_update; | |
2738 | ||
2739 | func_params.f_obj = &bp->func_obj; | |
2740 | func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; | |
2741 | ||
2742 | /* no need to wait for RAMROD completion, so don't | |
2743 | * set RAMROD_COMP_WAIT flag | |
2744 | */ | |
2745 | ||
2746 | f_update_params->vif_id = vifid; | |
2747 | f_update_params->afex_default_vlan = vlan_val; | |
2748 | f_update_params->allowed_priorities = allowed_prio; | |
2749 | ||
2750 | /* if ramrod can not be sent, response to MCP immediately */ | |
2751 | if (bnx2x_func_state_change(bp, &func_params) < 0) | |
2752 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
2753 | ||
2754 | return 0; | |
2755 | } | |
2756 | ||
2757 | static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, | |
2758 | u16 vif_index, u8 func_bit_map) | |
2759 | { | |
86564c3f | 2760 | struct bnx2x_func_state_params func_params = {NULL}; |
a3348722 BW |
2761 | struct bnx2x_func_afex_viflists_params *update_params = |
2762 | &func_params.params.afex_viflists; | |
2763 | int rc; | |
2764 | u32 drv_msg_code; | |
2765 | ||
2766 | /* validate only LIST_SET and LIST_GET are received from switch */ | |
2767 | if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) | |
2768 | BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", | |
2769 | cmd_type); | |
2770 | ||
2771 | func_params.f_obj = &bp->func_obj; | |
2772 | func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; | |
2773 | ||
2774 | /* set parameters according to cmd_type */ | |
2775 | update_params->afex_vif_list_command = cmd_type; | |
86564c3f | 2776 | update_params->vif_list_index = vif_index; |
a3348722 BW |
2777 | update_params->func_bit_map = |
2778 | (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; | |
2779 | update_params->func_to_clear = 0; | |
2780 | drv_msg_code = | |
2781 | (cmd_type == VIF_LIST_RULE_GET) ? | |
2782 | DRV_MSG_CODE_AFEX_LISTGET_ACK : | |
2783 | DRV_MSG_CODE_AFEX_LISTSET_ACK; | |
2784 | ||
2785 | /* if ramrod can not be sent, respond to MCP immediately for | |
2786 | * SET and GET requests (other are not triggered from MCP) | |
2787 | */ | |
2788 | rc = bnx2x_func_state_change(bp, &func_params); | |
2789 | if (rc < 0) | |
2790 | bnx2x_fw_command(bp, drv_msg_code, 0); | |
2791 | ||
2792 | return 0; | |
2793 | } | |
2794 | ||
2795 | static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) | |
2796 | { | |
2797 | struct afex_stats afex_stats; | |
2798 | u32 func = BP_ABS_FUNC(bp); | |
2799 | u32 mf_config; | |
2800 | u16 vlan_val; | |
2801 | u32 vlan_prio; | |
2802 | u16 vif_id; | |
2803 | u8 allowed_prio; | |
2804 | u8 vlan_mode; | |
2805 | u32 addr_to_write, vifid, addrs, stats_type, i; | |
2806 | ||
2807 | if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { | |
2808 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2809 | DP(BNX2X_MSG_MCP, | |
2810 | "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); | |
2811 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); | |
2812 | } | |
2813 | ||
2814 | if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { | |
2815 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2816 | addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); | |
2817 | DP(BNX2X_MSG_MCP, | |
2818 | "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", | |
2819 | vifid, addrs); | |
2820 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, | |
2821 | addrs); | |
2822 | } | |
2823 | ||
2824 | if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { | |
2825 | addr_to_write = SHMEM2_RD(bp, | |
2826 | afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); | |
2827 | stats_type = SHMEM2_RD(bp, | |
2828 | afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2829 | ||
2830 | DP(BNX2X_MSG_MCP, | |
2831 | "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", | |
2832 | addr_to_write); | |
2833 | ||
2834 | bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); | |
2835 | ||
2836 | /* write response to scratchpad, for MCP */ | |
2837 | for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) | |
2838 | REG_WR(bp, addr_to_write + i*sizeof(u32), | |
2839 | *(((u32 *)(&afex_stats))+i)); | |
2840 | ||
2841 | /* send ack message to MCP */ | |
2842 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); | |
2843 | } | |
2844 | ||
2845 | if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { | |
2846 | mf_config = MF_CFG_RD(bp, func_mf_config[func].config); | |
2847 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2848 | DP(BNX2X_MSG_MCP, | |
2849 | "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", | |
2850 | mf_config); | |
2851 | ||
2852 | /* if VIF_SET is "enabled" */ | |
2853 | if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { | |
2854 | /* set rate limit directly to internal RAM */ | |
2855 | struct cmng_init_input cmng_input; | |
2856 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2857 | size_t size = sizeof(struct rate_shaping_vars_per_vn); | |
2858 | u32 addr = BAR_XSTRORM_INTMEM + | |
2859 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); | |
2860 | ||
2861 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2862 | ||
2863 | bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); | |
2864 | m_rs_vn.vn_counter.rate = | |
2865 | cmng_input.vnic_max_rate[BP_VN(bp)]; | |
2866 | m_rs_vn.vn_counter.quota = | |
2867 | (m_rs_vn.vn_counter.rate * | |
2868 | RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2869 | ||
2870 | __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); | |
2871 | ||
2872 | /* read relevant values from mf_cfg struct in shmem */ | |
2873 | vif_id = | |
2874 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2875 | FUNC_MF_CFG_E1HOV_TAG_MASK) >> | |
2876 | FUNC_MF_CFG_E1HOV_TAG_SHIFT; | |
2877 | vlan_val = | |
2878 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2879 | FUNC_MF_CFG_AFEX_VLAN_MASK) >> | |
2880 | FUNC_MF_CFG_AFEX_VLAN_SHIFT; | |
2881 | vlan_prio = (mf_config & | |
2882 | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> | |
2883 | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; | |
2884 | vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); | |
2885 | vlan_mode = | |
2886 | (MF_CFG_RD(bp, | |
2887 | func_mf_config[func].afex_config) & | |
2888 | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> | |
2889 | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; | |
2890 | allowed_prio = | |
2891 | (MF_CFG_RD(bp, | |
2892 | func_mf_config[func].afex_config) & | |
2893 | FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> | |
2894 | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; | |
2895 | ||
2896 | /* send ramrod to FW, return in case of failure */ | |
2897 | if (bnx2x_afex_func_update(bp, vif_id, vlan_val, | |
2898 | allowed_prio)) | |
2899 | return; | |
2900 | ||
2901 | bp->afex_def_vlan_tag = vlan_val; | |
2902 | bp->afex_vlan_mode = vlan_mode; | |
2903 | } else { | |
2904 | /* notify link down because BP->flags is disabled */ | |
2905 | bnx2x_link_report(bp); | |
2906 | ||
2907 | /* send INVALID VIF ramrod to FW */ | |
2908 | bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); | |
2909 | ||
2910 | /* Reset the default afex VLAN */ | |
2911 | bp->afex_def_vlan_tag = -1; | |
2912 | } | |
2913 | } | |
2914 | } | |
2915 | ||
7609647e YM |
2916 | static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp) |
2917 | { | |
2918 | struct bnx2x_func_switch_update_params *switch_update_params; | |
2919 | struct bnx2x_func_state_params func_params; | |
2920 | ||
2921 | memset(&func_params, 0, sizeof(struct bnx2x_func_state_params)); | |
2922 | switch_update_params = &func_params.params.switch_update; | |
2923 | func_params.f_obj = &bp->func_obj; | |
2924 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
2925 | ||
230d00eb | 2926 | if (IS_MF_UFP(bp) || IS_MF_BD(bp)) { |
7609647e YM |
2927 | int func = BP_ABS_FUNC(bp); |
2928 | u32 val; | |
2929 | ||
2930 | /* Re-learn the S-tag from shmem */ | |
2931 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2932 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2933 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
2934 | bp->mf_ov = val; | |
2935 | } else { | |
2936 | BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n"); | |
2937 | goto fail; | |
2938 | } | |
2939 | ||
2940 | /* Configure new S-tag in LLH */ | |
2941 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, | |
2942 | bp->mf_ov); | |
2943 | ||
2944 | /* Send Ramrod to update FW of change */ | |
2945 | __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG, | |
2946 | &switch_update_params->changes); | |
2947 | switch_update_params->vlan = bp->mf_ov; | |
2948 | ||
2949 | if (bnx2x_func_state_change(bp, &func_params) < 0) { | |
2950 | BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n", | |
2951 | bp->mf_ov); | |
2952 | goto fail; | |
230d00eb YM |
2953 | } else { |
2954 | DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", | |
2955 | bp->mf_ov); | |
7609647e | 2956 | } |
230d00eb YM |
2957 | } else { |
2958 | goto fail; | |
7609647e YM |
2959 | } |
2960 | ||
230d00eb YM |
2961 | bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0); |
2962 | return; | |
7609647e YM |
2963 | fail: |
2964 | bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0); | |
2965 | } | |
2966 | ||
34f80b04 EG |
2967 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2968 | { | |
2969 | int port = BP_PORT(bp); | |
2970 | u32 val; | |
2971 | ||
2972 | bp->port.pmf = 1; | |
51c1a580 | 2973 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
34f80b04 | 2974 | |
3deb8167 YR |
2975 | /* |
2976 | * We need the mb() to ensure the ordering between the writing to | |
2977 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2978 | */ | |
2979 | smp_mb(); | |
2980 | ||
2981 | /* queue a periodic task */ | |
2982 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2983 | ||
ef01854e DK |
2984 | bnx2x_dcbx_pmf_update(bp); |
2985 | ||
34f80b04 | 2986 | /* enable nig attention */ |
3395a033 | 2987 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
2988 | if (bp->common.int_block == INT_BLOCK_HC) { |
2989 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2990 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2991 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2992 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2993 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2994 | } | |
bb2a0f7a YG |
2995 | |
2996 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2997 | } |
2998 | ||
c18487ee | 2999 | /* end of Link */ |
a2fbb9ea ET |
3000 | |
3001 | /* slow path */ | |
3002 | ||
3003 | /* | |
3004 | * General service functions | |
3005 | */ | |
3006 | ||
2691d51d | 3007 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 3008 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 3009 | { |
f2e0899f | 3010 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 3011 | u32 seq; |
2691d51d EG |
3012 | u32 rc = 0; |
3013 | u32 cnt = 1; | |
3014 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
3015 | ||
c4ff7cbf | 3016 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 3017 | seq = ++bp->fw_seq; |
f2e0899f DK |
3018 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
3019 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
3020 | ||
754a2f52 DK |
3021 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
3022 | (command | seq), param); | |
2691d51d EG |
3023 | |
3024 | do { | |
3025 | /* let the FW do it's magic ... */ | |
3026 | msleep(delay); | |
3027 | ||
f2e0899f | 3028 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 3029 | |
c4ff7cbf EG |
3030 | /* Give the FW up to 5 second (500*10ms) */ |
3031 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
3032 | |
3033 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
3034 | cnt*delay, rc, seq); | |
3035 | ||
3036 | /* is this a reply to our command? */ | |
3037 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
3038 | rc &= FW_MSG_CODE_MASK; | |
3039 | else { | |
3040 | /* FW BUG! */ | |
3041 | BNX2X_ERR("FW failed to respond!\n"); | |
3042 | bnx2x_fw_dump(bp); | |
3043 | rc = 0; | |
3044 | } | |
c4ff7cbf | 3045 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
3046 | |
3047 | return rc; | |
3048 | } | |
3049 | ||
1191cb83 ED |
3050 | static void storm_memset_func_cfg(struct bnx2x *bp, |
3051 | struct tstorm_eth_function_common_config *tcfg, | |
3052 | u16 abs_fid) | |
3053 | { | |
3054 | size_t size = sizeof(struct tstorm_eth_function_common_config); | |
3055 | ||
3056 | u32 addr = BAR_TSTRORM_INTMEM + | |
3057 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); | |
3058 | ||
3059 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); | |
3060 | } | |
3061 | ||
619c5cb6 VZ |
3062 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
3063 | { | |
3064 | if (CHIP_IS_E1x(bp)) { | |
3065 | struct tstorm_eth_function_common_config tcfg = {0}; | |
3066 | ||
3067 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
3068 | } | |
3069 | ||
3070 | /* Enable the function in the FW */ | |
3071 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
3072 | storm_memset_func_en(bp, p->func_id, 1); | |
3073 | ||
3074 | /* spq */ | |
05cc5a39 | 3075 | if (p->spq_active) { |
619c5cb6 VZ |
3076 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); |
3077 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
3078 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
3079 | } | |
3080 | } | |
3081 | ||
6383c0b3 | 3082 | /** |
16a5fd92 | 3083 | * bnx2x_get_common_flags - Return common flags |
6383c0b3 AE |
3084 | * |
3085 | * @bp device handle | |
3086 | * @fp queue handle | |
3087 | * @zero_stats TRUE if statistics zeroing is needed | |
3088 | * | |
3089 | * Return the flags that are common for the Tx-only and not normal connections. | |
3090 | */ | |
1191cb83 ED |
3091 | static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, |
3092 | struct bnx2x_fastpath *fp, | |
3093 | bool zero_stats) | |
28912902 | 3094 | { |
619c5cb6 VZ |
3095 | unsigned long flags = 0; |
3096 | ||
3097 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
3098 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 3099 | |
6383c0b3 | 3100 | /* tx only connections collect statistics (on the same index as the |
91226790 DK |
3101 | * parent connection). The statistics are zeroed when the parent |
3102 | * connection is initialized. | |
6383c0b3 | 3103 | */ |
50f0a562 BW |
3104 | |
3105 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
3106 | if (zero_stats) | |
3107 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
3108 | ||
c14db202 YM |
3109 | if (bp->flags & TX_SWITCHING) |
3110 | __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags); | |
3111 | ||
91226790 | 3112 | __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags); |
e287a75c | 3113 | __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags); |
6383c0b3 | 3114 | |
823e1d90 YM |
3115 | #ifdef BNX2X_STOP_ON_ERROR |
3116 | __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); | |
3117 | #endif | |
3118 | ||
6383c0b3 AE |
3119 | return flags; |
3120 | } | |
3121 | ||
1191cb83 ED |
3122 | static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, |
3123 | struct bnx2x_fastpath *fp, | |
3124 | bool leading) | |
6383c0b3 AE |
3125 | { |
3126 | unsigned long flags = 0; | |
3127 | ||
619c5cb6 VZ |
3128 | /* calculate other queue flags */ |
3129 | if (IS_MF_SD(bp)) | |
3130 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 3131 | |
a3348722 | 3132 | if (IS_FCOE_FP(fp)) { |
619c5cb6 | 3133 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); |
a3348722 BW |
3134 | /* For FCoE - force usage of default priority (for afex) */ |
3135 | __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); | |
3136 | } | |
523224a3 | 3137 | |
7e6b4d44 | 3138 | if (fp->mode != TPA_MODE_DISABLED) { |
619c5cb6 | 3139 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e | 3140 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
621b4d66 DK |
3141 | if (fp->mode == TPA_MODE_GRO) |
3142 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); | |
f5219d8e | 3143 | } |
619c5cb6 | 3144 | |
619c5cb6 VZ |
3145 | if (leading) { |
3146 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
3147 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
3148 | } | |
523224a3 | 3149 | |
619c5cb6 VZ |
3150 | /* Always set HW VLAN stripping */ |
3151 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 3152 | |
a3348722 BW |
3153 | /* configure silent vlan removal */ |
3154 | if (IS_MF_AFEX(bp)) | |
3155 | __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); | |
3156 | ||
6383c0b3 | 3157 | return flags | bnx2x_get_common_flags(bp, fp, true); |
523224a3 DK |
3158 | } |
3159 | ||
619c5cb6 | 3160 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
3161 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
3162 | u8 cos) | |
619c5cb6 VZ |
3163 | { |
3164 | gen_init->stat_id = bnx2x_stats_id(fp); | |
3165 | gen_init->spcl_id = fp->cl_id; | |
3166 | ||
3167 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
3168 | if (IS_FCOE_FP(fp)) | |
3169 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
3170 | else | |
3171 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
3172 | |
3173 | gen_init->cos = cos; | |
02dc4025 YM |
3174 | |
3175 | gen_init->fp_hsi = ETH_FP_HSI_VERSION; | |
619c5cb6 VZ |
3176 | } |
3177 | ||
3178 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 3179 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 3180 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 3181 | { |
619c5cb6 | 3182 | u8 max_sge = 0; |
523224a3 DK |
3183 | u16 sge_sz = 0; |
3184 | u16 tpa_agg_size = 0; | |
3185 | ||
7e6b4d44 | 3186 | if (fp->mode != TPA_MODE_DISABLED) { |
dfacf138 DK |
3187 | pause->sge_th_lo = SGE_TH_LO(bp); |
3188 | pause->sge_th_hi = SGE_TH_HI(bp); | |
3189 | ||
3190 | /* validate SGE ring has enough to cross high threshold */ | |
3191 | WARN_ON(bp->dropless_fc && | |
3192 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
3193 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
3194 | ||
924d75ab | 3195 | tpa_agg_size = TPA_AGG_SIZE; |
523224a3 DK |
3196 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> |
3197 | SGE_PAGE_SHIFT; | |
3198 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
3199 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
924d75ab | 3200 | sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); |
523224a3 DK |
3201 | } |
3202 | ||
3203 | /* pause - not for e1 */ | |
3204 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
3205 | pause->bd_th_lo = BD_TH_LO(bp); |
3206 | pause->bd_th_hi = BD_TH_HI(bp); | |
3207 | ||
3208 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
3209 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
3210 | /* | |
3211 | * validate that rings have enough entries to cross | |
3212 | * high thresholds | |
3213 | */ | |
3214 | WARN_ON(bp->dropless_fc && | |
3215 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
3216 | bp->rx_ring_size); | |
3217 | WARN_ON(bp->dropless_fc && | |
3218 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
3219 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 3220 | |
523224a3 DK |
3221 | pause->pri_map = 1; |
3222 | } | |
3223 | ||
3224 | /* rxq setup */ | |
523224a3 DK |
3225 | rxq_init->dscr_map = fp->rx_desc_mapping; |
3226 | rxq_init->sge_map = fp->rx_sge_mapping; | |
3227 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
3228 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 3229 | |
619c5cb6 VZ |
3230 | /* This should be a maximum number of data bytes that may be |
3231 | * placed on the BD (not including paddings). | |
3232 | */ | |
e52fcb24 | 3233 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
3cdeec22 | 3234 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; |
a8c94b91 | 3235 | |
523224a3 | 3236 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
3237 | rxq_init->tpa_agg_sz = tpa_agg_size; |
3238 | rxq_init->sge_buf_sz = sge_sz; | |
3239 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 | 3240 | rxq_init->rss_engine_id = BP_FUNC(bp); |
259afa1f | 3241 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
619c5cb6 VZ |
3242 | |
3243 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
3244 | * | |
2de67439 | 3245 | * For PF Clients it should be the maximum available number. |
619c5cb6 VZ |
3246 | * VF driver(s) may want to define it to a smaller value. |
3247 | */ | |
dfacf138 | 3248 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 3249 | |
523224a3 DK |
3250 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
3251 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
3252 | ||
ec6ba945 VZ |
3253 | if (IS_FCOE_FP(fp)) |
3254 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
3255 | else | |
6383c0b3 | 3256 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
a3348722 BW |
3257 | /* configure silent vlan removal |
3258 | * if multi function mode is afex, then mask default vlan | |
3259 | */ | |
3260 | if (IS_MF_AFEX(bp)) { | |
3261 | rxq_init->silent_removal_value = bp->afex_def_vlan_tag; | |
3262 | rxq_init->silent_removal_mask = VLAN_VID_MASK; | |
3263 | } | |
523224a3 DK |
3264 | } |
3265 | ||
619c5cb6 | 3266 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
3267 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
3268 | u8 cos) | |
523224a3 | 3269 | { |
65565884 | 3270 | txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; |
6383c0b3 | 3271 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; |
523224a3 DK |
3272 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
3273 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 3274 | |
619c5cb6 | 3275 | /* |
16a5fd92 | 3276 | * set the tss leading client id for TX classification == |
619c5cb6 VZ |
3277 | * leading RSS client id |
3278 | */ | |
3279 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
3280 | ||
ec6ba945 VZ |
3281 | if (IS_FCOE_FP(fp)) { |
3282 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
3283 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
3284 | } | |
523224a3 DK |
3285 | } |
3286 | ||
8d96286a | 3287 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
3288 | { |
3289 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 | 3290 | struct event_ring_data eq_data = { {0} }; |
523224a3 | 3291 | |
619c5cb6 | 3292 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
3293 | /* reset IGU PF statistics: MSIX + ATTN */ |
3294 | /* PF */ | |
3295 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3296 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3297 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3298 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3299 | /* ATTN */ | |
3300 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3301 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3302 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
3303 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3304 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3305 | } | |
3306 | ||
05cc5a39 | 3307 | func_init.spq_active = true; |
523224a3 DK |
3308 | func_init.pf_id = BP_FUNC(bp); |
3309 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
3310 | func_init.spq_map = bp->spq_mapping; |
3311 | func_init.spq_prod = bp->spq_prod_idx; | |
3312 | ||
3313 | bnx2x_func_init(bp, &func_init); | |
3314 | ||
3315 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
3316 | ||
3317 | /* | |
619c5cb6 VZ |
3318 | * Congestion management values depend on the link rate |
3319 | * There is no active link so initial link rate is set to 10 Gbps. | |
3320 | * When the link comes up The congestion management values are | |
3321 | * re-calculated according to the actual link rate. | |
3322 | */ | |
523224a3 DK |
3323 | bp->link_vars.line_speed = SPEED_10000; |
3324 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
3325 | ||
3326 | /* Only the PMF sets the HW */ | |
3327 | if (bp->port.pmf) | |
3328 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3329 | ||
86564c3f | 3330 | /* init Event Queue - PCI bus guarantees correct endianity*/ |
523224a3 DK |
3331 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); |
3332 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
3333 | eq_data.producer = bp->eq_prod; | |
3334 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
3335 | eq_data.sb_id = DEF_SB_ID; | |
3336 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
3337 | } | |
3338 | ||
523224a3 DK |
3339 | static void bnx2x_e1h_disable(struct bnx2x *bp) |
3340 | { | |
3341 | int port = BP_PORT(bp); | |
3342 | ||
619c5cb6 | 3343 | bnx2x_tx_disable(bp); |
523224a3 DK |
3344 | |
3345 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
3346 | } |
3347 | ||
3348 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
3349 | { | |
3350 | int port = BP_PORT(bp); | |
3351 | ||
7609647e YM |
3352 | if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) |
3353 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); | |
523224a3 | 3354 | |
16a5fd92 | 3355 | /* Tx queue should be only re-enabled */ |
523224a3 DK |
3356 | netif_tx_wake_all_queues(bp->dev); |
3357 | ||
3358 | /* | |
3359 | * Should not call netif_carrier_on since it will be called if the link | |
3360 | * is up when checking for link state | |
3361 | */ | |
3362 | } | |
3363 | ||
1d187b34 BW |
3364 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
3365 | ||
3366 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) | |
3367 | { | |
3368 | struct eth_stats_info *ether_stat = | |
3369 | &bp->slowpath->drv_info_to_mcp.ether_stat; | |
3ec9f9ca AE |
3370 | struct bnx2x_vlan_mac_obj *mac_obj = |
3371 | &bp->sp_objs->mac_obj; | |
3372 | int i; | |
1d187b34 | 3373 | |
786fdf0b DC |
3374 | strlcpy(ether_stat->version, DRV_MODULE_VERSION, |
3375 | ETH_STAT_INFO_VERSION_LEN); | |
1d187b34 | 3376 | |
3ec9f9ca AE |
3377 | /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the |
3378 | * mac_local field in ether_stat struct. The base address is offset by 2 | |
3379 | * bytes to account for the field being 8 bytes but a mac address is | |
3380 | * only 6 bytes. Likewise, the stride for the get_n_elements function is | |
3381 | * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes | |
3382 | * allocated by the ether_stat struct, so the macs will land in their | |
3383 | * proper positions. | |
3384 | */ | |
3385 | for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) | |
3386 | memset(ether_stat->mac_local + i, 0, | |
3387 | sizeof(ether_stat->mac_local[0])); | |
3388 | mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, | |
3389 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | |
3390 | ether_stat->mac_local + MAC_PAD, MAC_PAD, | |
3391 | ETH_ALEN); | |
1d187b34 | 3392 | ether_stat->mtu_size = bp->dev->mtu; |
1d187b34 BW |
3393 | if (bp->dev->features & NETIF_F_RXCSUM) |
3394 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | |
3395 | if (bp->dev->features & NETIF_F_TSO) | |
3396 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; | |
3397 | ether_stat->feature_flags |= bp->common.boot_mode; | |
3398 | ||
3399 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; | |
3400 | ||
3401 | ether_stat->txq_size = bp->tx_ring_size; | |
3402 | ether_stat->rxq_size = bp->rx_ring_size; | |
0c757dee | 3403 | |
fcf93a0a | 3404 | #ifdef CONFIG_BNX2X_SRIOV |
0c757dee | 3405 | ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0; |
fcf93a0a | 3406 | #endif |
1d187b34 BW |
3407 | } |
3408 | ||
3409 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) | |
3410 | { | |
3411 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3412 | struct fcoe_stats_info *fcoe_stat = | |
3413 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; | |
3414 | ||
55c11941 MS |
3415 | if (!CNIC_LOADED(bp)) |
3416 | return; | |
3417 | ||
3ec9f9ca | 3418 | memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); |
1d187b34 BW |
3419 | |
3420 | fcoe_stat->qos_priority = | |
3421 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | |
3422 | ||
3423 | /* insert FCoE stats from ramrod response */ | |
3424 | if (!NO_FCOE(bp)) { | |
3425 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = | |
65565884 | 3426 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3427 | tstorm_queue_statistics; |
3428 | ||
3429 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = | |
65565884 | 3430 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3431 | xstorm_queue_statistics; |
3432 | ||
3433 | struct fcoe_statistics_params *fw_fcoe_stat = | |
3434 | &bp->fw_stats_data->fcoe; | |
3435 | ||
86564c3f YM |
3436 | ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, |
3437 | fcoe_stat->rx_bytes_lo, | |
3438 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); | |
1d187b34 | 3439 | |
86564c3f YM |
3440 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3441 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, | |
3442 | fcoe_stat->rx_bytes_lo, | |
3443 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); | |
1d187b34 | 3444 | |
86564c3f YM |
3445 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3446 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, | |
3447 | fcoe_stat->rx_bytes_lo, | |
3448 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); | |
1d187b34 | 3449 | |
86564c3f YM |
3450 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3451 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, | |
3452 | fcoe_stat->rx_bytes_lo, | |
3453 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); | |
1d187b34 | 3454 | |
86564c3f YM |
3455 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3456 | fcoe_stat->rx_frames_lo, | |
3457 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); | |
1d187b34 | 3458 | |
86564c3f YM |
3459 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3460 | fcoe_stat->rx_frames_lo, | |
3461 | fcoe_q_tstorm_stats->rcv_ucast_pkts); | |
1d187b34 | 3462 | |
86564c3f YM |
3463 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3464 | fcoe_stat->rx_frames_lo, | |
3465 | fcoe_q_tstorm_stats->rcv_bcast_pkts); | |
1d187b34 | 3466 | |
86564c3f YM |
3467 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3468 | fcoe_stat->rx_frames_lo, | |
3469 | fcoe_q_tstorm_stats->rcv_mcast_pkts); | |
1d187b34 | 3470 | |
86564c3f YM |
3471 | ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, |
3472 | fcoe_stat->tx_bytes_lo, | |
3473 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); | |
1d187b34 | 3474 | |
86564c3f YM |
3475 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3476 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, | |
3477 | fcoe_stat->tx_bytes_lo, | |
3478 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); | |
1d187b34 | 3479 | |
86564c3f YM |
3480 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3481 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, | |
3482 | fcoe_stat->tx_bytes_lo, | |
3483 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); | |
1d187b34 | 3484 | |
86564c3f YM |
3485 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3486 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, | |
3487 | fcoe_stat->tx_bytes_lo, | |
3488 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); | |
1d187b34 | 3489 | |
86564c3f YM |
3490 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3491 | fcoe_stat->tx_frames_lo, | |
3492 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); | |
1d187b34 | 3493 | |
86564c3f YM |
3494 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3495 | fcoe_stat->tx_frames_lo, | |
3496 | fcoe_q_xstorm_stats->ucast_pkts_sent); | |
1d187b34 | 3497 | |
86564c3f YM |
3498 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3499 | fcoe_stat->tx_frames_lo, | |
3500 | fcoe_q_xstorm_stats->bcast_pkts_sent); | |
1d187b34 | 3501 | |
86564c3f YM |
3502 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3503 | fcoe_stat->tx_frames_lo, | |
3504 | fcoe_q_xstorm_stats->mcast_pkts_sent); | |
1d187b34 BW |
3505 | } |
3506 | ||
1d187b34 BW |
3507 | /* ask L5 driver to add data to the struct */ |
3508 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); | |
1d187b34 BW |
3509 | } |
3510 | ||
3511 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) | |
3512 | { | |
3513 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3514 | struct iscsi_stats_info *iscsi_stat = | |
3515 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; | |
3516 | ||
55c11941 MS |
3517 | if (!CNIC_LOADED(bp)) |
3518 | return; | |
3519 | ||
3ec9f9ca AE |
3520 | memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, |
3521 | ETH_ALEN); | |
1d187b34 BW |
3522 | |
3523 | iscsi_stat->qos_priority = | |
3524 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | |
3525 | ||
1d187b34 BW |
3526 | /* ask L5 driver to add data to the struct */ |
3527 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); | |
1d187b34 BW |
3528 | } |
3529 | ||
0793f83f DK |
3530 | /* called due to MCP event (on pmf): |
3531 | * reread new bandwidth configuration | |
3532 | * configure FW | |
3533 | * notify others function about the change | |
3534 | */ | |
1191cb83 | 3535 | static void bnx2x_config_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3536 | { |
3537 | if (bp->link_vars.link_up) { | |
3538 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
3539 | bnx2x_link_sync_notify(bp); | |
3540 | } | |
3541 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3542 | } | |
3543 | ||
1191cb83 | 3544 | static void bnx2x_set_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3545 | { |
3546 | bnx2x_config_mf_bw(bp); | |
3547 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
3548 | } | |
3549 | ||
c8c60d88 YM |
3550 | static void bnx2x_handle_eee_event(struct bnx2x *bp) |
3551 | { | |
3552 | DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); | |
3553 | bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); | |
3554 | } | |
3555 | ||
42f8277f YM |
3556 | #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20) |
3557 | #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25) | |
3558 | ||
1d187b34 BW |
3559 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
3560 | { | |
3561 | enum drv_info_opcode op_code; | |
3562 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); | |
42f8277f YM |
3563 | bool release = false; |
3564 | int wait; | |
1d187b34 BW |
3565 | |
3566 | /* if drv_info version supported by MFW doesn't match - send NACK */ | |
3567 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { | |
3568 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3569 | return; | |
3570 | } | |
3571 | ||
3572 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> | |
3573 | DRV_INFO_CONTROL_OP_CODE_SHIFT; | |
3574 | ||
42f8277f YM |
3575 | /* Must prevent other flows from accessing drv_info_to_mcp */ |
3576 | mutex_lock(&bp->drv_info_mutex); | |
3577 | ||
1d187b34 BW |
3578 | memset(&bp->slowpath->drv_info_to_mcp, 0, |
3579 | sizeof(union drv_info_to_mcp)); | |
3580 | ||
3581 | switch (op_code) { | |
3582 | case ETH_STATS_OPCODE: | |
3583 | bnx2x_drv_info_ether_stat(bp); | |
3584 | break; | |
3585 | case FCOE_STATS_OPCODE: | |
3586 | bnx2x_drv_info_fcoe_stat(bp); | |
3587 | break; | |
3588 | case ISCSI_STATS_OPCODE: | |
3589 | bnx2x_drv_info_iscsi_stat(bp); | |
3590 | break; | |
3591 | default: | |
3592 | /* if op code isn't supported - send NACK */ | |
3593 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
42f8277f | 3594 | goto out; |
1d187b34 BW |
3595 | } |
3596 | ||
3597 | /* if we got drv_info attn from MFW then these fields are defined in | |
3598 | * shmem2 for sure | |
3599 | */ | |
3600 | SHMEM2_WR(bp, drv_info_host_addr_lo, | |
3601 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3602 | SHMEM2_WR(bp, drv_info_host_addr_hi, | |
3603 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3604 | ||
3605 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); | |
42f8277f YM |
3606 | |
3607 | /* Since possible management wants both this and get_driver_version | |
3608 | * need to wait until management notifies us it finished utilizing | |
3609 | * the buffer. | |
3610 | */ | |
3611 | if (!SHMEM2_HAS(bp, mfw_drv_indication)) { | |
3612 | DP(BNX2X_MSG_MCP, "Management does not support indication\n"); | |
3613 | } else if (!bp->drv_info_mng_owner) { | |
3614 | u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1)); | |
3615 | ||
3616 | for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) { | |
3617 | u32 indication = SHMEM2_RD(bp, mfw_drv_indication); | |
3618 | ||
3619 | /* Management is done; need to clear indication */ | |
3620 | if (indication & bit) { | |
3621 | SHMEM2_WR(bp, mfw_drv_indication, | |
3622 | indication & ~bit); | |
3623 | release = true; | |
3624 | break; | |
3625 | } | |
3626 | ||
3627 | msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH); | |
3628 | } | |
3629 | } | |
3630 | if (!release) { | |
3631 | DP(BNX2X_MSG_MCP, "Management did not release indication\n"); | |
3632 | bp->drv_info_mng_owner = true; | |
3633 | } | |
3634 | ||
3635 | out: | |
3636 | mutex_unlock(&bp->drv_info_mutex); | |
3637 | } | |
3638 | ||
3639 | static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format) | |
3640 | { | |
3641 | u8 vals[4]; | |
3642 | int i = 0; | |
3643 | ||
3644 | if (bnx2x_format) { | |
3645 | i = sscanf(version, "1.%c%hhd.%hhd.%hhd", | |
3646 | &vals[0], &vals[1], &vals[2], &vals[3]); | |
3647 | if (i > 0) | |
3648 | vals[0] -= '0'; | |
3649 | } else { | |
3650 | i = sscanf(version, "%hhd.%hhd.%hhd.%hhd", | |
3651 | &vals[0], &vals[1], &vals[2], &vals[3]); | |
3652 | } | |
3653 | ||
3654 | while (i < 4) | |
3655 | vals[i++] = 0; | |
3656 | ||
3657 | return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3]; | |
3658 | } | |
3659 | ||
3660 | void bnx2x_update_mng_version(struct bnx2x *bp) | |
3661 | { | |
3662 | u32 iscsiver = DRV_VER_NOT_LOADED; | |
3663 | u32 fcoever = DRV_VER_NOT_LOADED; | |
3664 | u32 ethver = DRV_VER_NOT_LOADED; | |
3665 | int idx = BP_FW_MB_IDX(bp); | |
3666 | u8 *version; | |
3667 | ||
3668 | if (!SHMEM2_HAS(bp, func_os_drv_ver)) | |
3669 | return; | |
3670 | ||
3671 | mutex_lock(&bp->drv_info_mutex); | |
3672 | /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */ | |
3673 | if (bp->drv_info_mng_owner) | |
3674 | goto out; | |
3675 | ||
3676 | if (bp->state != BNX2X_STATE_OPEN) | |
3677 | goto out; | |
3678 | ||
3679 | /* Parse ethernet driver version */ | |
3680 | ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); | |
3681 | if (!CNIC_LOADED(bp)) | |
3682 | goto out; | |
3683 | ||
3684 | /* Try getting storage driver version via cnic */ | |
3685 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3686 | sizeof(union drv_info_to_mcp)); | |
3687 | bnx2x_drv_info_iscsi_stat(bp); | |
3688 | version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version; | |
3689 | iscsiver = bnx2x_update_mng_version_utility(version, false); | |
3690 | ||
3691 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3692 | sizeof(union drv_info_to_mcp)); | |
3693 | bnx2x_drv_info_fcoe_stat(bp); | |
3694 | version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version; | |
3695 | fcoever = bnx2x_update_mng_version_utility(version, false); | |
3696 | ||
3697 | out: | |
3698 | SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver); | |
3699 | SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver); | |
3700 | SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever); | |
3701 | ||
3702 | mutex_unlock(&bp->drv_info_mutex); | |
3703 | ||
3704 | DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n", | |
3705 | ethver, iscsiver, fcoever); | |
1d187b34 BW |
3706 | } |
3707 | ||
c48f350f YM |
3708 | void bnx2x_update_mfw_dump(struct bnx2x *bp) |
3709 | { | |
c48f350f YM |
3710 | u32 drv_ver; |
3711 | u32 valid_dump; | |
3712 | ||
3713 | if (!SHMEM2_HAS(bp, drv_info)) | |
3714 | return; | |
3715 | ||
a19a19de AB |
3716 | /* Update Driver load time, possibly broken in y2038 */ |
3717 | SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds()); | |
c48f350f YM |
3718 | |
3719 | drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); | |
3720 | SHMEM2_WR(bp, drv_info.drv_ver, drv_ver); | |
3721 | ||
3722 | SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM)); | |
3723 | ||
3724 | /* Check & notify On-Chip dump. */ | |
3725 | valid_dump = SHMEM2_RD(bp, drv_info.valid_dump); | |
3726 | ||
3727 | if (valid_dump & FIRST_DUMP_VALID) | |
3728 | DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n"); | |
3729 | ||
3730 | if (valid_dump & SECOND_DUMP_VALID) | |
3731 | DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n"); | |
3732 | } | |
3733 | ||
7609647e | 3734 | static void bnx2x_oem_event(struct bnx2x *bp, u32 event) |
523224a3 | 3735 | { |
7609647e YM |
3736 | u32 cmd_ok, cmd_fail; |
3737 | ||
3738 | /* sanity */ | |
3739 | if (event & DRV_STATUS_DCC_EVENT_MASK && | |
3740 | event & DRV_STATUS_OEM_EVENT_MASK) { | |
3741 | BNX2X_ERR("Received simultaneous events %08x\n", event); | |
3742 | return; | |
3743 | } | |
523224a3 | 3744 | |
7609647e YM |
3745 | if (event & DRV_STATUS_DCC_EVENT_MASK) { |
3746 | cmd_fail = DRV_MSG_CODE_DCC_FAILURE; | |
3747 | cmd_ok = DRV_MSG_CODE_DCC_OK; | |
3748 | } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ { | |
3749 | cmd_fail = DRV_MSG_CODE_OEM_FAILURE; | |
3750 | cmd_ok = DRV_MSG_CODE_OEM_OK; | |
3751 | } | |
523224a3 | 3752 | |
7609647e YM |
3753 | DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event); |
3754 | ||
3755 | if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF | | |
3756 | DRV_STATUS_OEM_DISABLE_ENABLE_PF)) { | |
3757 | /* This is the only place besides the function initialization | |
523224a3 DK |
3758 | * where the bp->flags can change so it is done without any |
3759 | * locks | |
3760 | */ | |
f2e0899f | 3761 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
51c1a580 | 3762 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
523224a3 DK |
3763 | bp->flags |= MF_FUNC_DIS; |
3764 | ||
3765 | bnx2x_e1h_disable(bp); | |
3766 | } else { | |
51c1a580 | 3767 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
523224a3 DK |
3768 | bp->flags &= ~MF_FUNC_DIS; |
3769 | ||
3770 | bnx2x_e1h_enable(bp); | |
3771 | } | |
7609647e YM |
3772 | event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF | |
3773 | DRV_STATUS_OEM_DISABLE_ENABLE_PF); | |
523224a3 | 3774 | } |
7609647e YM |
3775 | |
3776 | if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | | |
3777 | DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) { | |
0793f83f | 3778 | bnx2x_config_mf_bw(bp); |
7609647e YM |
3779 | event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | |
3780 | DRV_STATUS_OEM_BANDWIDTH_ALLOCATION); | |
523224a3 DK |
3781 | } |
3782 | ||
3783 | /* Report results to MCP */ | |
7609647e YM |
3784 | if (event) |
3785 | bnx2x_fw_command(bp, cmd_fail, 0); | |
523224a3 | 3786 | else |
7609647e | 3787 | bnx2x_fw_command(bp, cmd_ok, 0); |
523224a3 DK |
3788 | } |
3789 | ||
3790 | /* must be called under the spq lock */ | |
1191cb83 | 3791 | static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) |
523224a3 DK |
3792 | { |
3793 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3794 | ||
3795 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3796 | bp->spq_prod_bd = bp->spq; | |
3797 | bp->spq_prod_idx = 0; | |
51c1a580 | 3798 | DP(BNX2X_MSG_SP, "end of spq\n"); |
523224a3 DK |
3799 | } else { |
3800 | bp->spq_prod_bd++; | |
3801 | bp->spq_prod_idx++; | |
3802 | } | |
3803 | return next_spe; | |
3804 | } | |
3805 | ||
3806 | /* must be called under the spq lock */ | |
1191cb83 | 3807 | static void bnx2x_sp_prod_update(struct bnx2x *bp) |
28912902 MC |
3808 | { |
3809 | int func = BP_FUNC(bp); | |
3810 | ||
53e51e2f VZ |
3811 | /* |
3812 | * Make sure that BD data is updated before writing the producer: | |
3813 | * BD data is written to the memory, the producer is read from the | |
3814 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3815 | */ | |
3816 | mb(); | |
28912902 | 3817 | |
523224a3 | 3818 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3819 | bp->spq_prod_idx); |
28912902 MC |
3820 | mmiowb(); |
3821 | } | |
3822 | ||
619c5cb6 VZ |
3823 | /** |
3824 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3825 | * | |
3826 | * @cmd: command to check | |
3827 | * @cmd_type: command type | |
3828 | */ | |
1191cb83 | 3829 | static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) |
619c5cb6 VZ |
3830 | { |
3831 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3832 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3833 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3834 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3835 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3836 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3837 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3838 | return true; | |
3839 | else | |
3840 | return false; | |
619c5cb6 VZ |
3841 | } |
3842 | ||
619c5cb6 VZ |
3843 | /** |
3844 | * bnx2x_sp_post - place a single command on an SP ring | |
3845 | * | |
3846 | * @bp: driver handle | |
3847 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3848 | * @cid: SW CID the command is related to | |
3849 | * @data_hi: command private data address (high 32 bits) | |
3850 | * @data_lo: command private data address (low 32 bits) | |
3851 | * @cmd_type: command type (e.g. NONE, ETH) | |
3852 | * | |
3853 | * SP data is handled as if it's always an address pair, thus data fields are | |
3854 | * not swapped to little endian in upper functions. Instead this function swaps | |
3855 | * data as if it's two u32 fields. | |
3856 | */ | |
9f6c9258 | 3857 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3858 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3859 | { |
28912902 | 3860 | struct eth_spe *spe; |
523224a3 | 3861 | u16 type; |
619c5cb6 | 3862 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3863 | |
a2fbb9ea | 3864 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
3865 | if (unlikely(bp->panic)) { |
3866 | BNX2X_ERR("Can't post SP when there is panic\n"); | |
a2fbb9ea | 3867 | return -EIO; |
51c1a580 | 3868 | } |
a2fbb9ea ET |
3869 | #endif |
3870 | ||
34f80b04 | 3871 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3872 | |
6e30dd4e VZ |
3873 | if (common) { |
3874 | if (!atomic_read(&bp->eq_spq_left)) { | |
3875 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3876 | spin_unlock_bh(&bp->spq_lock); | |
3877 | bnx2x_panic(); | |
3878 | return -EBUSY; | |
3879 | } | |
3880 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3881 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3882 | spin_unlock_bh(&bp->spq_lock); | |
3883 | bnx2x_panic(); | |
3884 | return -EBUSY; | |
a2fbb9ea | 3885 | } |
f1410647 | 3886 | |
28912902 MC |
3887 | spe = bnx2x_sp_get_next(bp); |
3888 | ||
a2fbb9ea | 3889 | /* CID needs port number to be encoded int it */ |
28912902 | 3890 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3891 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3892 | HW_CID(bp, cid)); | |
523224a3 | 3893 | |
14a94ebd MK |
3894 | /* In some cases, type may already contain the func-id |
3895 | * mainly in SRIOV related use cases, so we add it here only | |
3896 | * if it's not already set. | |
3897 | */ | |
3898 | if (!(cmd_type & SPE_HDR_FUNCTION_ID)) { | |
3899 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & | |
3900 | SPE_HDR_CONN_TYPE; | |
3901 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & | |
3902 | SPE_HDR_FUNCTION_ID); | |
3903 | } else { | |
3904 | type = cmd_type; | |
3905 | } | |
a2fbb9ea | 3906 | |
523224a3 DK |
3907 | spe->hdr.type = cpu_to_le16(type); |
3908 | ||
3909 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3910 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3911 | ||
d6cae238 VZ |
3912 | /* |
3913 | * It's ok if the actual decrement is issued towards the memory | |
3914 | * somewhere between the spin_lock and spin_unlock. Thus no | |
16a5fd92 | 3915 | * more explicit memory barrier is needed. |
d6cae238 VZ |
3916 | */ |
3917 | if (common) | |
3918 | atomic_dec(&bp->eq_spq_left); | |
3919 | else | |
3920 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3921 | |
51c1a580 MS |
3922 | DP(BNX2X_MSG_SP, |
3923 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3924 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3925 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3926 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3927 | HW_CID(bp, cid), data_hi, data_lo, type, |
3928 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3929 | |
28912902 | 3930 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3931 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3932 | return 0; |
3933 | } | |
3934 | ||
3935 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3936 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3937 | { |
72fd0718 | 3938 | u32 j, val; |
34f80b04 | 3939 | int rc = 0; |
a2fbb9ea ET |
3940 | |
3941 | might_sleep(); | |
72fd0718 | 3942 | for (j = 0; j < 1000; j++) { |
3cdeec22 YM |
3943 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); |
3944 | val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); | |
3945 | if (val & MCPR_ACCESS_LOCK_LOCK) | |
a2fbb9ea ET |
3946 | break; |
3947 | ||
639d65b8 | 3948 | usleep_range(5000, 10000); |
a2fbb9ea | 3949 | } |
3cdeec22 | 3950 | if (!(val & MCPR_ACCESS_LOCK_LOCK)) { |
19680c48 | 3951 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3952 | rc = -EBUSY; |
3953 | } | |
3954 | ||
3955 | return rc; | |
3956 | } | |
3957 | ||
4a37fb66 YG |
3958 | /* release split MCP access lock register */ |
3959 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3960 | { |
3cdeec22 | 3961 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); |
a2fbb9ea ET |
3962 | } |
3963 | ||
523224a3 DK |
3964 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3965 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3966 | ||
1191cb83 | 3967 | static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
a2fbb9ea | 3968 | { |
523224a3 | 3969 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3970 | u16 rc = 0; |
3971 | ||
3972 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3973 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3974 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3975 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3976 | } |
523224a3 DK |
3977 | |
3978 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3979 | bp->def_idx = def_sb->sp_sb.running_index; | |
3980 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3981 | } |
523224a3 | 3982 | |
16a5fd92 | 3983 | /* Do not reorder: indices reading should complete before handling */ |
523224a3 | 3984 | barrier(); |
a2fbb9ea ET |
3985 | return rc; |
3986 | } | |
3987 | ||
3988 | /* | |
3989 | * slow path service functions | |
3990 | */ | |
3991 | ||
3992 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3993 | { | |
34f80b04 | 3994 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3995 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3996 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3997 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3998 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3999 | u32 aeu_mask; |
87942b46 | 4000 | u32 nig_mask = 0; |
f2e0899f | 4001 | u32 reg_addr; |
a2fbb9ea | 4002 | |
a2fbb9ea ET |
4003 | if (bp->attn_state & asserted) |
4004 | BNX2X_ERR("IGU ERROR\n"); | |
4005 | ||
3fcaf2e5 EG |
4006 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4007 | aeu_mask = REG_RD(bp, aeu_addr); | |
4008 | ||
a2fbb9ea | 4009 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 4010 | aeu_mask, asserted); |
72fd0718 | 4011 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 4012 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4013 | |
3fcaf2e5 EG |
4014 | REG_WR(bp, aeu_addr, aeu_mask); |
4015 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 4016 | |
3fcaf2e5 | 4017 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 4018 | bp->attn_state |= asserted; |
3fcaf2e5 | 4019 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
4020 | |
4021 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
4022 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 4023 | |
a5e9a7cf EG |
4024 | bnx2x_acquire_phy_lock(bp); |
4025 | ||
877e9aa4 | 4026 | /* save nig interrupt mask */ |
87942b46 | 4027 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 4028 | |
361c391e YR |
4029 | /* If nig_mask is not set, no need to call the update |
4030 | * function. | |
4031 | */ | |
4032 | if (nig_mask) { | |
4033 | REG_WR(bp, nig_int_mask_addr, 0); | |
4034 | ||
4035 | bnx2x_link_attn(bp); | |
4036 | } | |
a2fbb9ea ET |
4037 | |
4038 | /* handle unicore attn? */ | |
4039 | } | |
4040 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
4041 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
4042 | ||
4043 | if (asserted & GPIO_2_FUNC) | |
4044 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
4045 | ||
4046 | if (asserted & GPIO_3_FUNC) | |
4047 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
4048 | ||
4049 | if (asserted & GPIO_4_FUNC) | |
4050 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
4051 | ||
4052 | if (port == 0) { | |
4053 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
4054 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
4055 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
4056 | } | |
4057 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
4058 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
4059 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
4060 | } | |
4061 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
4062 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
4063 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
4064 | } | |
4065 | } else { | |
4066 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
4067 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
4068 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
4069 | } | |
4070 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
4071 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
4072 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
4073 | } | |
4074 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
4075 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
4076 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
4077 | } | |
4078 | } | |
4079 | ||
4080 | } /* if hardwired */ | |
4081 | ||
f2e0899f DK |
4082 | if (bp->common.int_block == INT_BLOCK_HC) |
4083 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4084 | COMMAND_REG_ATTN_BITS_SET); | |
4085 | else | |
4086 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
4087 | ||
4088 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
4089 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
4090 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
4091 | |
4092 | /* now set back the mask */ | |
a5e9a7cf | 4093 | if (asserted & ATTN_NIG_FOR_FUNC) { |
27c1151c YR |
4094 | /* Verify that IGU ack through BAR was written before restoring |
4095 | * NIG mask. This loop should exit after 2-3 iterations max. | |
4096 | */ | |
4097 | if (bp->common.int_block != INT_BLOCK_HC) { | |
4098 | u32 cnt = 0, igu_acked; | |
4099 | do { | |
4100 | igu_acked = REG_RD(bp, | |
4101 | IGU_REG_ATTENTION_ACK_BITS); | |
4102 | } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && | |
4103 | (++cnt < MAX_IGU_ATTN_ACK_TO)); | |
4104 | if (!igu_acked) | |
4105 | DP(NETIF_MSG_HW, | |
4106 | "Failed to verify IGU ack on time\n"); | |
4107 | barrier(); | |
4108 | } | |
87942b46 | 4109 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
4110 | bnx2x_release_phy_lock(bp); |
4111 | } | |
a2fbb9ea ET |
4112 | } |
4113 | ||
1191cb83 | 4114 | static void bnx2x_fan_failure(struct bnx2x *bp) |
fd4ef40d EG |
4115 | { |
4116 | int port = BP_PORT(bp); | |
b7737c9b | 4117 | u32 ext_phy_config; |
fd4ef40d | 4118 | /* mark the failure */ |
b7737c9b YR |
4119 | ext_phy_config = |
4120 | SHMEM_RD(bp, | |
4121 | dev_info.port_hw_config[port].external_phy_config); | |
4122 | ||
4123 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
4124 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 4125 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 4126 | ext_phy_config); |
fd4ef40d EG |
4127 | |
4128 | /* log the failure */ | |
51c1a580 MS |
4129 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
4130 | "Please contact OEM Support for assistance\n"); | |
8304859a | 4131 | |
16a5fd92 | 4132 | /* Schedule device reset (unload) |
8304859a AE |
4133 | * This is due to some boards consuming sufficient power when driver is |
4134 | * up to overheat if fan fails. | |
4135 | */ | |
230bb0f3 | 4136 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0); |
fd4ef40d | 4137 | } |
ab6ad5a4 | 4138 | |
1191cb83 | 4139 | static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 4140 | { |
34f80b04 | 4141 | int port = BP_PORT(bp); |
877e9aa4 | 4142 | int reg_offset; |
d90d96ba | 4143 | u32 val; |
877e9aa4 | 4144 | |
34f80b04 EG |
4145 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
4146 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 4147 | |
34f80b04 | 4148 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
4149 | |
4150 | val = REG_RD(bp, reg_offset); | |
4151 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
4152 | REG_WR(bp, reg_offset, val); | |
4153 | ||
4154 | BNX2X_ERR("SPIO5 hw attention\n"); | |
4155 | ||
fd4ef40d | 4156 | /* Fan failure attention */ |
d90d96ba | 4157 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 4158 | bnx2x_fan_failure(bp); |
877e9aa4 | 4159 | } |
34f80b04 | 4160 | |
3deb8167 | 4161 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
4162 | bnx2x_acquire_phy_lock(bp); |
4163 | bnx2x_handle_module_detect_int(&bp->link_params); | |
4164 | bnx2x_release_phy_lock(bp); | |
4165 | } | |
4166 | ||
34f80b04 EG |
4167 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
4168 | ||
4169 | val = REG_RD(bp, reg_offset); | |
4170 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
4171 | REG_WR(bp, reg_offset, val); | |
4172 | ||
4173 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 4174 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
4175 | bnx2x_panic(); |
4176 | } | |
877e9aa4 ET |
4177 | } |
4178 | ||
1191cb83 | 4179 | static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
4180 | { |
4181 | u32 val; | |
4182 | ||
0626b899 | 4183 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
4184 | |
4185 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
4186 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
4187 | /* DORQ discard attention */ | |
4188 | if (val & 0x2) | |
4189 | BNX2X_ERR("FATAL error from DORQ\n"); | |
4190 | } | |
34f80b04 EG |
4191 | |
4192 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
4193 | ||
4194 | int port = BP_PORT(bp); | |
4195 | int reg_offset; | |
4196 | ||
4197 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
4198 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
4199 | ||
4200 | val = REG_RD(bp, reg_offset); | |
4201 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
4202 | REG_WR(bp, reg_offset, val); | |
4203 | ||
4204 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 4205 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
4206 | bnx2x_panic(); |
4207 | } | |
877e9aa4 ET |
4208 | } |
4209 | ||
1191cb83 | 4210 | static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
4211 | { |
4212 | u32 val; | |
4213 | ||
4214 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
4215 | ||
4216 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
4217 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
4218 | /* CFC error attention */ | |
4219 | if (val & 0x2) | |
4220 | BNX2X_ERR("FATAL error from CFC\n"); | |
4221 | } | |
4222 | ||
4223 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 4224 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 4225 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
4226 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
4227 | if (val & 0x18000) | |
4228 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
4229 | |
4230 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
4231 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
4232 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
4233 | } | |
877e9aa4 | 4234 | } |
34f80b04 EG |
4235 | |
4236 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
4237 | ||
4238 | int port = BP_PORT(bp); | |
4239 | int reg_offset; | |
4240 | ||
4241 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
4242 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
4243 | ||
4244 | val = REG_RD(bp, reg_offset); | |
4245 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
4246 | REG_WR(bp, reg_offset, val); | |
4247 | ||
4248 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 4249 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
4250 | bnx2x_panic(); |
4251 | } | |
877e9aa4 ET |
4252 | } |
4253 | ||
1191cb83 | 4254 | static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) |
877e9aa4 | 4255 | { |
34f80b04 EG |
4256 | u32 val; |
4257 | ||
877e9aa4 ET |
4258 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
4259 | ||
34f80b04 EG |
4260 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
4261 | int func = BP_FUNC(bp); | |
4262 | ||
4263 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
a3348722 | 4264 | bnx2x_read_mf_cfg(bp); |
f2e0899f DK |
4265 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
4266 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
4267 | val = SHMEM_RD(bp, | |
4268 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
7609647e YM |
4269 | |
4270 | if (val & (DRV_STATUS_DCC_EVENT_MASK | | |
4271 | DRV_STATUS_OEM_EVENT_MASK)) | |
4272 | bnx2x_oem_event(bp, | |
4273 | (val & (DRV_STATUS_DCC_EVENT_MASK | | |
4274 | DRV_STATUS_OEM_EVENT_MASK))); | |
0793f83f DK |
4275 | |
4276 | if (val & DRV_STATUS_SET_MF_BW) | |
4277 | bnx2x_set_mf_bw(bp); | |
4278 | ||
1d187b34 BW |
4279 | if (val & DRV_STATUS_DRV_INFO_REQ) |
4280 | bnx2x_handle_drv_info_req(bp); | |
d16132ce AE |
4281 | |
4282 | if (val & DRV_STATUS_VF_DISABLED) | |
370d4a26 YM |
4283 | bnx2x_schedule_iov_task(bp, |
4284 | BNX2X_IOV_HANDLE_FLR); | |
d16132ce | 4285 | |
2691d51d | 4286 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
4287 | bnx2x_pmf_update(bp); |
4288 | ||
e4901dde | 4289 | if (bp->port.pmf && |
785b9b1a SR |
4290 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
4291 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
4292 | /* start dcbx state machine */ |
4293 | bnx2x_dcbx_set_params(bp, | |
4294 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
a3348722 BW |
4295 | if (val & DRV_STATUS_AFEX_EVENT_MASK) |
4296 | bnx2x_handle_afex_cmd(bp, | |
4297 | val & DRV_STATUS_AFEX_EVENT_MASK); | |
c8c60d88 YM |
4298 | if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) |
4299 | bnx2x_handle_eee_event(bp); | |
7609647e YM |
4300 | |
4301 | if (val & DRV_STATUS_OEM_UPDATE_SVID) | |
4302 | bnx2x_handle_update_svid_cmd(bp); | |
4303 | ||
3deb8167 YR |
4304 | if (bp->link_vars.periodic_flags & |
4305 | PERIODIC_FLAGS_LINK_EVENT) { | |
4306 | /* sync with link */ | |
4307 | bnx2x_acquire_phy_lock(bp); | |
4308 | bp->link_vars.periodic_flags &= | |
4309 | ~PERIODIC_FLAGS_LINK_EVENT; | |
4310 | bnx2x_release_phy_lock(bp); | |
4311 | if (IS_MF(bp)) | |
4312 | bnx2x_link_sync_notify(bp); | |
4313 | bnx2x_link_report(bp); | |
4314 | } | |
4315 | /* Always call it here: bnx2x_link_report() will | |
4316 | * prevent the link indication duplication. | |
4317 | */ | |
4318 | bnx2x__link_status_update(bp); | |
34f80b04 | 4319 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
4320 | |
4321 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 4322 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
4323 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
4324 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
4325 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
4326 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
4327 | bnx2x_panic(); | |
4328 | ||
4329 | } else if (attn & BNX2X_MCP_ASSERT) { | |
4330 | ||
4331 | BNX2X_ERR("MCP assert!\n"); | |
4332 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 4333 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
4334 | |
4335 | } else | |
4336 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
4337 | } | |
4338 | ||
4339 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
4340 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
4341 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
4342 | val = CHIP_IS_E1(bp) ? 0 : |
4343 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
4344 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
4345 | } | |
4346 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
4347 | val = CHIP_IS_E1(bp) ? 0 : |
4348 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
4349 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
4350 | } | |
877e9aa4 | 4351 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
4352 | } |
4353 | } | |
4354 | ||
c9ee9206 VZ |
4355 | /* |
4356 | * Bits map: | |
4357 | * 0-7 - Engine0 load counter. | |
4358 | * 8-15 - Engine1 load counter. | |
4359 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
4360 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
4361 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
4362 | * on the engine | |
4363 | * 19 - Engine1 ONE_IS_LOADED. | |
4364 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
4365 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
4366 | * just the one belonging to its engine). | |
4367 | * | |
4368 | */ | |
4369 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
4370 | ||
4371 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
4372 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
4373 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
4374 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
4375 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
4376 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
4377 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
4378 | ||
4379 | /* | |
4380 | * Set the GLOBAL_RESET bit. | |
4381 | * | |
4382 | * Should be run under rtnl lock | |
4383 | */ | |
4384 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
4385 | { | |
f16da43b AE |
4386 | u32 val; |
4387 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4388 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4389 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
f16da43b | 4390 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 VZ |
4391 | } |
4392 | ||
4393 | /* | |
4394 | * Clear the GLOBAL_RESET bit. | |
4395 | * | |
4396 | * Should be run under rtnl lock | |
4397 | */ | |
1191cb83 | 4398 | static void bnx2x_clear_reset_global(struct bnx2x *bp) |
c9ee9206 | 4399 | { |
f16da43b AE |
4400 | u32 val; |
4401 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4402 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4403 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
f16da43b | 4404 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 | 4405 | } |
f85582f8 | 4406 | |
72fd0718 | 4407 | /* |
c9ee9206 VZ |
4408 | * Checks the GLOBAL_RESET bit. |
4409 | * | |
72fd0718 VZ |
4410 | * should be run under rtnl lock |
4411 | */ | |
1191cb83 | 4412 | static bool bnx2x_reset_is_global(struct bnx2x *bp) |
c9ee9206 | 4413 | { |
3cdeec22 | 4414 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
c9ee9206 VZ |
4415 | |
4416 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
4417 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
4418 | } | |
4419 | ||
4420 | /* | |
4421 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
4422 | * | |
4423 | * Should be run under rtnl lock | |
4424 | */ | |
1191cb83 | 4425 | static void bnx2x_set_reset_done(struct bnx2x *bp) |
72fd0718 | 4426 | { |
f16da43b | 4427 | u32 val; |
c9ee9206 VZ |
4428 | u32 bit = BP_PATH(bp) ? |
4429 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4430 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4431 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4432 | |
4433 | /* Clear the bit */ | |
4434 | val &= ~bit; | |
4435 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4436 | |
4437 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
72fd0718 VZ |
4438 | } |
4439 | ||
4440 | /* | |
c9ee9206 VZ |
4441 | * Set RESET_IN_PROGRESS for the current engine. |
4442 | * | |
72fd0718 VZ |
4443 | * should be run under rtnl lock |
4444 | */ | |
c9ee9206 | 4445 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 4446 | { |
f16da43b | 4447 | u32 val; |
c9ee9206 VZ |
4448 | u32 bit = BP_PATH(bp) ? |
4449 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4450 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4451 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4452 | |
4453 | /* Set the bit */ | |
4454 | val |= bit; | |
4455 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4456 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4457 | } |
4458 | ||
4459 | /* | |
c9ee9206 | 4460 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
4461 | * should be run under rtnl lock |
4462 | */ | |
c9ee9206 | 4463 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 4464 | { |
3cdeec22 | 4465 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
c9ee9206 VZ |
4466 | u32 bit = engine ? |
4467 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
4468 | ||
4469 | /* return false if bit is set */ | |
4470 | return (val & bit) ? false : true; | |
72fd0718 VZ |
4471 | } |
4472 | ||
4473 | /* | |
889b9af3 | 4474 | * set pf load for the current pf. |
c9ee9206 | 4475 | * |
72fd0718 VZ |
4476 | * should be run under rtnl lock |
4477 | */ | |
889b9af3 | 4478 | void bnx2x_set_pf_load(struct bnx2x *bp) |
72fd0718 | 4479 | { |
f16da43b | 4480 | u32 val1, val; |
c9ee9206 VZ |
4481 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4482 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4483 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4484 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4485 | |
f16da43b AE |
4486 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4487 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4488 | ||
51c1a580 | 4489 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4490 | |
c9ee9206 VZ |
4491 | /* get the current counter value */ |
4492 | val1 = (val & mask) >> shift; | |
4493 | ||
889b9af3 AE |
4494 | /* set bit of that PF */ |
4495 | val1 |= (1 << bp->pf_num); | |
c9ee9206 VZ |
4496 | |
4497 | /* clear the old value */ | |
4498 | val &= ~mask; | |
4499 | ||
4500 | /* set the new one */ | |
4501 | val |= ((val1 << shift) & mask); | |
4502 | ||
4503 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4504 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4505 | } |
4506 | ||
c9ee9206 | 4507 | /** |
889b9af3 | 4508 | * bnx2x_clear_pf_load - clear pf load mark |
c9ee9206 VZ |
4509 | * |
4510 | * @bp: driver handle | |
4511 | * | |
4512 | * Should be run under rtnl lock. | |
4513 | * Decrements the load counter for the current engine. Returns | |
889b9af3 | 4514 | * whether other functions are still loaded |
72fd0718 | 4515 | */ |
889b9af3 | 4516 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
72fd0718 | 4517 | { |
f16da43b | 4518 | u32 val1, val; |
c9ee9206 VZ |
4519 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4520 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4521 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4522 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4523 | |
f16da43b AE |
4524 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4525 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
51c1a580 | 4526 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4527 | |
c9ee9206 VZ |
4528 | /* get the current counter value */ |
4529 | val1 = (val & mask) >> shift; | |
4530 | ||
889b9af3 AE |
4531 | /* clear bit of that PF */ |
4532 | val1 &= ~(1 << bp->pf_num); | |
c9ee9206 VZ |
4533 | |
4534 | /* clear the old value */ | |
4535 | val &= ~mask; | |
4536 | ||
4537 | /* set the new one */ | |
4538 | val |= ((val1 << shift) & mask); | |
4539 | ||
4540 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4541 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4542 | return val1 != 0; | |
72fd0718 VZ |
4543 | } |
4544 | ||
4545 | /* | |
889b9af3 | 4546 | * Read the load status for the current engine. |
c9ee9206 | 4547 | * |
72fd0718 VZ |
4548 | * should be run under rtnl lock |
4549 | */ | |
1191cb83 | 4550 | static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
72fd0718 | 4551 | { |
c9ee9206 VZ |
4552 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
4553 | BNX2X_PATH0_LOAD_CNT_MASK); | |
4554 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4555 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
4556 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4557 | ||
51c1a580 | 4558 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
c9ee9206 VZ |
4559 | |
4560 | val = (val & mask) >> shift; | |
4561 | ||
51c1a580 MS |
4562 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
4563 | engine, val); | |
c9ee9206 | 4564 | |
889b9af3 | 4565 | return val != 0; |
72fd0718 VZ |
4566 | } |
4567 | ||
6bf07b8e YM |
4568 | static void _print_parity(struct bnx2x *bp, u32 reg) |
4569 | { | |
4570 | pr_cont(" [0x%08x] ", REG_RD(bp, reg)); | |
4571 | } | |
4572 | ||
1191cb83 | 4573 | static void _print_next_block(int idx, const char *blk) |
72fd0718 | 4574 | { |
f1deab50 | 4575 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
4576 | } |
4577 | ||
4293b9f5 DK |
4578 | static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, |
4579 | int *par_num, bool print) | |
72fd0718 | 4580 | { |
4293b9f5 DK |
4581 | u32 cur_bit; |
4582 | bool res; | |
4583 | int i; | |
4584 | ||
4585 | res = false; | |
4586 | ||
72fd0718 | 4587 | for (i = 0; sig; i++) { |
4293b9f5 | 4588 | cur_bit = (0x1UL << i); |
72fd0718 | 4589 | if (sig & cur_bit) { |
4293b9f5 DK |
4590 | res |= true; /* Each bit is real error! */ |
4591 | ||
4592 | if (print) { | |
4593 | switch (cur_bit) { | |
4594 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
4595 | _print_next_block((*par_num)++, "BRB"); | |
6bf07b8e YM |
4596 | _print_parity(bp, |
4597 | BRB1_REG_BRB1_PRTY_STS); | |
4293b9f5 DK |
4598 | break; |
4599 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
4600 | _print_next_block((*par_num)++, | |
4601 | "PARSER"); | |
6bf07b8e | 4602 | _print_parity(bp, PRS_REG_PRS_PRTY_STS); |
4293b9f5 DK |
4603 | break; |
4604 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
4605 | _print_next_block((*par_num)++, "TSDM"); | |
6bf07b8e YM |
4606 | _print_parity(bp, |
4607 | TSDM_REG_TSDM_PRTY_STS); | |
4293b9f5 DK |
4608 | break; |
4609 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
4610 | _print_next_block((*par_num)++, | |
c9ee9206 | 4611 | "SEARCHER"); |
6bf07b8e | 4612 | _print_parity(bp, SRC_REG_SRC_PRTY_STS); |
4293b9f5 DK |
4613 | break; |
4614 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
4615 | _print_next_block((*par_num)++, "TCM"); | |
4616 | _print_parity(bp, TCM_REG_TCM_PRTY_STS); | |
4617 | break; | |
4618 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
4619 | _print_next_block((*par_num)++, | |
4620 | "TSEMI"); | |
6bf07b8e YM |
4621 | _print_parity(bp, |
4622 | TSEM_REG_TSEM_PRTY_STS_0); | |
4623 | _print_parity(bp, | |
4624 | TSEM_REG_TSEM_PRTY_STS_1); | |
4293b9f5 DK |
4625 | break; |
4626 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
4627 | _print_next_block((*par_num)++, "XPB"); | |
6bf07b8e YM |
4628 | _print_parity(bp, GRCBASE_XPB + |
4629 | PB_REG_PB_PRTY_STS); | |
4293b9f5 | 4630 | break; |
6bf07b8e | 4631 | } |
72fd0718 VZ |
4632 | } |
4633 | ||
4634 | /* Clear the bit */ | |
4635 | sig &= ~cur_bit; | |
4636 | } | |
4637 | } | |
4638 | ||
4293b9f5 | 4639 | return res; |
72fd0718 VZ |
4640 | } |
4641 | ||
4293b9f5 DK |
4642 | static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, |
4643 | int *par_num, bool *global, | |
6bf07b8e | 4644 | bool print) |
72fd0718 | 4645 | { |
4293b9f5 DK |
4646 | u32 cur_bit; |
4647 | bool res; | |
4648 | int i; | |
4649 | ||
4650 | res = false; | |
4651 | ||
72fd0718 | 4652 | for (i = 0; sig; i++) { |
4293b9f5 | 4653 | cur_bit = (0x1UL << i); |
72fd0718 | 4654 | if (sig & cur_bit) { |
4293b9f5 | 4655 | res |= true; /* Each bit is real error! */ |
72fd0718 | 4656 | switch (cur_bit) { |
c9ee9206 | 4657 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
6bf07b8e | 4658 | if (print) { |
4293b9f5 | 4659 | _print_next_block((*par_num)++, "PBF"); |
6bf07b8e YM |
4660 | _print_parity(bp, PBF_REG_PBF_PRTY_STS); |
4661 | } | |
72fd0718 VZ |
4662 | break; |
4663 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
6bf07b8e | 4664 | if (print) { |
4293b9f5 | 4665 | _print_next_block((*par_num)++, "QM"); |
6bf07b8e YM |
4666 | _print_parity(bp, QM_REG_QM_PRTY_STS); |
4667 | } | |
c9ee9206 VZ |
4668 | break; |
4669 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
6bf07b8e | 4670 | if (print) { |
4293b9f5 | 4671 | _print_next_block((*par_num)++, "TM"); |
6bf07b8e YM |
4672 | _print_parity(bp, TM_REG_TM_PRTY_STS); |
4673 | } | |
72fd0718 VZ |
4674 | break; |
4675 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
6bf07b8e | 4676 | if (print) { |
4293b9f5 | 4677 | _print_next_block((*par_num)++, "XSDM"); |
6bf07b8e YM |
4678 | _print_parity(bp, |
4679 | XSDM_REG_XSDM_PRTY_STS); | |
4680 | } | |
c9ee9206 VZ |
4681 | break; |
4682 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
6bf07b8e | 4683 | if (print) { |
4293b9f5 | 4684 | _print_next_block((*par_num)++, "XCM"); |
6bf07b8e YM |
4685 | _print_parity(bp, XCM_REG_XCM_PRTY_STS); |
4686 | } | |
72fd0718 VZ |
4687 | break; |
4688 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
6bf07b8e | 4689 | if (print) { |
4293b9f5 DK |
4690 | _print_next_block((*par_num)++, |
4691 | "XSEMI"); | |
6bf07b8e YM |
4692 | _print_parity(bp, |
4693 | XSEM_REG_XSEM_PRTY_STS_0); | |
4694 | _print_parity(bp, | |
4695 | XSEM_REG_XSEM_PRTY_STS_1); | |
4696 | } | |
72fd0718 VZ |
4697 | break; |
4698 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
6bf07b8e | 4699 | if (print) { |
4293b9f5 | 4700 | _print_next_block((*par_num)++, |
c9ee9206 | 4701 | "DOORBELLQ"); |
6bf07b8e YM |
4702 | _print_parity(bp, |
4703 | DORQ_REG_DORQ_PRTY_STS); | |
4704 | } | |
c9ee9206 VZ |
4705 | break; |
4706 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
6bf07b8e | 4707 | if (print) { |
4293b9f5 | 4708 | _print_next_block((*par_num)++, "NIG"); |
6bf07b8e YM |
4709 | if (CHIP_IS_E1x(bp)) { |
4710 | _print_parity(bp, | |
4711 | NIG_REG_NIG_PRTY_STS); | |
4712 | } else { | |
4713 | _print_parity(bp, | |
4714 | NIG_REG_NIG_PRTY_STS_0); | |
4715 | _print_parity(bp, | |
4716 | NIG_REG_NIG_PRTY_STS_1); | |
4717 | } | |
4718 | } | |
72fd0718 VZ |
4719 | break; |
4720 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 | 4721 | if (print) |
4293b9f5 | 4722 | _print_next_block((*par_num)++, |
c9ee9206 VZ |
4723 | "VAUX PCI CORE"); |
4724 | *global = true; | |
72fd0718 VZ |
4725 | break; |
4726 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
6bf07b8e | 4727 | if (print) { |
4293b9f5 DK |
4728 | _print_next_block((*par_num)++, |
4729 | "DEBUG"); | |
6bf07b8e YM |
4730 | _print_parity(bp, DBG_REG_DBG_PRTY_STS); |
4731 | } | |
72fd0718 VZ |
4732 | break; |
4733 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
6bf07b8e | 4734 | if (print) { |
4293b9f5 | 4735 | _print_next_block((*par_num)++, "USDM"); |
6bf07b8e YM |
4736 | _print_parity(bp, |
4737 | USDM_REG_USDM_PRTY_STS); | |
4738 | } | |
72fd0718 | 4739 | break; |
8736c826 | 4740 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
6bf07b8e | 4741 | if (print) { |
4293b9f5 | 4742 | _print_next_block((*par_num)++, "UCM"); |
6bf07b8e YM |
4743 | _print_parity(bp, UCM_REG_UCM_PRTY_STS); |
4744 | } | |
8736c826 | 4745 | break; |
72fd0718 | 4746 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
6bf07b8e | 4747 | if (print) { |
4293b9f5 DK |
4748 | _print_next_block((*par_num)++, |
4749 | "USEMI"); | |
6bf07b8e YM |
4750 | _print_parity(bp, |
4751 | USEM_REG_USEM_PRTY_STS_0); | |
4752 | _print_parity(bp, | |
4753 | USEM_REG_USEM_PRTY_STS_1); | |
4754 | } | |
72fd0718 VZ |
4755 | break; |
4756 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
6bf07b8e | 4757 | if (print) { |
4293b9f5 | 4758 | _print_next_block((*par_num)++, "UPB"); |
6bf07b8e YM |
4759 | _print_parity(bp, GRCBASE_UPB + |
4760 | PB_REG_PB_PRTY_STS); | |
4761 | } | |
72fd0718 VZ |
4762 | break; |
4763 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
6bf07b8e | 4764 | if (print) { |
4293b9f5 | 4765 | _print_next_block((*par_num)++, "CSDM"); |
6bf07b8e YM |
4766 | _print_parity(bp, |
4767 | CSDM_REG_CSDM_PRTY_STS); | |
4768 | } | |
72fd0718 | 4769 | break; |
8736c826 | 4770 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
6bf07b8e | 4771 | if (print) { |
4293b9f5 | 4772 | _print_next_block((*par_num)++, "CCM"); |
6bf07b8e YM |
4773 | _print_parity(bp, CCM_REG_CCM_PRTY_STS); |
4774 | } | |
8736c826 | 4775 | break; |
72fd0718 VZ |
4776 | } |
4777 | ||
4778 | /* Clear the bit */ | |
4779 | sig &= ~cur_bit; | |
4780 | } | |
4781 | } | |
4782 | ||
4293b9f5 | 4783 | return res; |
72fd0718 VZ |
4784 | } |
4785 | ||
4293b9f5 DK |
4786 | static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, |
4787 | int *par_num, bool print) | |
72fd0718 | 4788 | { |
4293b9f5 DK |
4789 | u32 cur_bit; |
4790 | bool res; | |
4791 | int i; | |
4792 | ||
4793 | res = false; | |
4794 | ||
72fd0718 | 4795 | for (i = 0; sig; i++) { |
4293b9f5 | 4796 | cur_bit = (0x1UL << i); |
72fd0718 | 4797 | if (sig & cur_bit) { |
0c23ad37 | 4798 | res = true; /* Each bit is real error! */ |
4293b9f5 DK |
4799 | if (print) { |
4800 | switch (cur_bit) { | |
4801 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
4802 | _print_next_block((*par_num)++, | |
4803 | "CSEMI"); | |
6bf07b8e YM |
4804 | _print_parity(bp, |
4805 | CSEM_REG_CSEM_PRTY_STS_0); | |
4806 | _print_parity(bp, | |
4807 | CSEM_REG_CSEM_PRTY_STS_1); | |
4293b9f5 DK |
4808 | break; |
4809 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
4810 | _print_next_block((*par_num)++, "PXP"); | |
6bf07b8e YM |
4811 | _print_parity(bp, PXP_REG_PXP_PRTY_STS); |
4812 | _print_parity(bp, | |
4813 | PXP2_REG_PXP2_PRTY_STS_0); | |
4814 | _print_parity(bp, | |
4815 | PXP2_REG_PXP2_PRTY_STS_1); | |
4293b9f5 DK |
4816 | break; |
4817 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
4818 | _print_next_block((*par_num)++, | |
4819 | "PXPPCICLOCKCLIENT"); | |
4820 | break; | |
4821 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
4822 | _print_next_block((*par_num)++, "CFC"); | |
6bf07b8e YM |
4823 | _print_parity(bp, |
4824 | CFC_REG_CFC_PRTY_STS); | |
4293b9f5 DK |
4825 | break; |
4826 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
4827 | _print_next_block((*par_num)++, "CDU"); | |
6bf07b8e | 4828 | _print_parity(bp, CDU_REG_CDU_PRTY_STS); |
4293b9f5 DK |
4829 | break; |
4830 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
4831 | _print_next_block((*par_num)++, "DMAE"); | |
6bf07b8e YM |
4832 | _print_parity(bp, |
4833 | DMAE_REG_DMAE_PRTY_STS); | |
4293b9f5 DK |
4834 | break; |
4835 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
4836 | _print_next_block((*par_num)++, "IGU"); | |
6bf07b8e YM |
4837 | if (CHIP_IS_E1x(bp)) |
4838 | _print_parity(bp, | |
4839 | HC_REG_HC_PRTY_STS); | |
4840 | else | |
4841 | _print_parity(bp, | |
4842 | IGU_REG_IGU_PRTY_STS); | |
4293b9f5 DK |
4843 | break; |
4844 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
4845 | _print_next_block((*par_num)++, "MISC"); | |
6bf07b8e YM |
4846 | _print_parity(bp, |
4847 | MISC_REG_MISC_PRTY_STS); | |
4293b9f5 | 4848 | break; |
6bf07b8e | 4849 | } |
72fd0718 VZ |
4850 | } |
4851 | ||
4852 | /* Clear the bit */ | |
4853 | sig &= ~cur_bit; | |
4854 | } | |
4855 | } | |
4856 | ||
4293b9f5 | 4857 | return res; |
72fd0718 VZ |
4858 | } |
4859 | ||
4293b9f5 DK |
4860 | static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig, |
4861 | int *par_num, bool *global, | |
4862 | bool print) | |
72fd0718 | 4863 | { |
4293b9f5 DK |
4864 | bool res = false; |
4865 | u32 cur_bit; | |
4866 | int i; | |
4867 | ||
72fd0718 | 4868 | for (i = 0; sig; i++) { |
4293b9f5 | 4869 | cur_bit = (0x1UL << i); |
72fd0718 VZ |
4870 | if (sig & cur_bit) { |
4871 | switch (cur_bit) { | |
4872 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 | 4873 | if (print) |
4293b9f5 DK |
4874 | _print_next_block((*par_num)++, |
4875 | "MCP ROM"); | |
c9ee9206 | 4876 | *global = true; |
0c23ad37 | 4877 | res = true; |
72fd0718 VZ |
4878 | break; |
4879 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 | 4880 | if (print) |
4293b9f5 | 4881 | _print_next_block((*par_num)++, |
c9ee9206 VZ |
4882 | "MCP UMP RX"); |
4883 | *global = true; | |
0c23ad37 | 4884 | res = true; |
72fd0718 VZ |
4885 | break; |
4886 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 | 4887 | if (print) |
4293b9f5 | 4888 | _print_next_block((*par_num)++, |
c9ee9206 VZ |
4889 | "MCP UMP TX"); |
4890 | *global = true; | |
0c23ad37 | 4891 | res = true; |
72fd0718 VZ |
4892 | break; |
4893 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
ad6afbe9 | 4894 | (*par_num)++; |
4293b9f5 DK |
4895 | /* clear latched SCPAD PATIRY from MCP */ |
4896 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, | |
4897 | 1UL << 10); | |
72fd0718 VZ |
4898 | break; |
4899 | } | |
4900 | ||
4901 | /* Clear the bit */ | |
4902 | sig &= ~cur_bit; | |
4903 | } | |
4904 | } | |
4905 | ||
4293b9f5 | 4906 | return res; |
72fd0718 VZ |
4907 | } |
4908 | ||
4293b9f5 DK |
4909 | static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, |
4910 | int *par_num, bool print) | |
8736c826 | 4911 | { |
4293b9f5 DK |
4912 | u32 cur_bit; |
4913 | bool res; | |
4914 | int i; | |
4915 | ||
4916 | res = false; | |
4917 | ||
8736c826 | 4918 | for (i = 0; sig; i++) { |
4293b9f5 | 4919 | cur_bit = (0x1UL << i); |
8736c826 | 4920 | if (sig & cur_bit) { |
0c23ad37 | 4921 | res = true; /* Each bit is real error! */ |
4293b9f5 DK |
4922 | if (print) { |
4923 | switch (cur_bit) { | |
4924 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
4925 | _print_next_block((*par_num)++, | |
4926 | "PGLUE_B"); | |
6bf07b8e | 4927 | _print_parity(bp, |
4293b9f5 DK |
4928 | PGLUE_B_REG_PGLUE_B_PRTY_STS); |
4929 | break; | |
4930 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
4931 | _print_next_block((*par_num)++, "ATC"); | |
6bf07b8e YM |
4932 | _print_parity(bp, |
4933 | ATC_REG_ATC_PRTY_STS); | |
4293b9f5 | 4934 | break; |
6bf07b8e | 4935 | } |
8736c826 | 4936 | } |
8736c826 VZ |
4937 | /* Clear the bit */ |
4938 | sig &= ~cur_bit; | |
4939 | } | |
4940 | } | |
4941 | ||
4293b9f5 | 4942 | return res; |
8736c826 VZ |
4943 | } |
4944 | ||
1191cb83 ED |
4945 | static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
4946 | u32 *sig) | |
72fd0718 | 4947 | { |
4293b9f5 DK |
4948 | bool res = false; |
4949 | ||
8736c826 VZ |
4950 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4951 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4952 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4953 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4954 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 | 4955 | int par_num = 0; |
ad6afbe9 | 4956 | |
51c1a580 MS |
4957 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
4958 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", | |
8736c826 VZ |
4959 | sig[0] & HW_PRTY_ASSERT_SET_0, |
4960 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4961 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4962 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4963 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
ad6afbe9 MC |
4964 | if (print) { |
4965 | if (((sig[0] & HW_PRTY_ASSERT_SET_0) || | |
4966 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4967 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4968 | (sig[4] & HW_PRTY_ASSERT_SET_4)) || | |
4969 | (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) { | |
4970 | netdev_err(bp->dev, | |
4971 | "Parity errors detected in blocks: "); | |
4972 | } else { | |
4973 | print = false; | |
4974 | } | |
4975 | } | |
4293b9f5 DK |
4976 | res |= bnx2x_check_blocks_with_parity0(bp, |
4977 | sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print); | |
4978 | res |= bnx2x_check_blocks_with_parity1(bp, | |
4979 | sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print); | |
4980 | res |= bnx2x_check_blocks_with_parity2(bp, | |
4981 | sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print); | |
4982 | res |= bnx2x_check_blocks_with_parity3(bp, | |
4983 | sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print); | |
4984 | res |= bnx2x_check_blocks_with_parity4(bp, | |
4985 | sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print); | |
8736c826 | 4986 | |
c9ee9206 VZ |
4987 | if (print) |
4988 | pr_cont("\n"); | |
4293b9f5 | 4989 | } |
8736c826 | 4990 | |
4293b9f5 | 4991 | return res; |
72fd0718 VZ |
4992 | } |
4993 | ||
c9ee9206 VZ |
4994 | /** |
4995 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
4996 | * | |
4997 | * @bp: driver handle | |
4998 | * @global: true if there was a global attention | |
4999 | * @print: show parity attention in syslog | |
5000 | */ | |
5001 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 5002 | { |
8736c826 | 5003 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
5004 | int port = BP_PORT(bp); |
5005 | ||
5006 | attn.sig[0] = REG_RD(bp, | |
5007 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
5008 | port*4); | |
5009 | attn.sig[1] = REG_RD(bp, | |
5010 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
5011 | port*4); | |
5012 | attn.sig[2] = REG_RD(bp, | |
5013 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
5014 | port*4); | |
5015 | attn.sig[3] = REG_RD(bp, | |
5016 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
5017 | port*4); | |
0a5ccb75 YM |
5018 | /* Since MCP attentions can't be disabled inside the block, we need to |
5019 | * read AEU registers to see whether they're currently disabled | |
5020 | */ | |
5021 | attn.sig[3] &= ((REG_RD(bp, | |
5022 | !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 | |
5023 | : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) & | |
5024 | MISC_AEU_ENABLE_MCP_PRTY_BITS) | | |
5025 | ~MISC_AEU_ENABLE_MCP_PRTY_BITS); | |
72fd0718 | 5026 | |
8736c826 VZ |
5027 | if (!CHIP_IS_E1x(bp)) |
5028 | attn.sig[4] = REG_RD(bp, | |
5029 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
5030 | port*4); | |
5031 | ||
5032 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
5033 | } |
5034 | ||
1191cb83 | 5035 | static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) |
f2e0899f DK |
5036 | { |
5037 | u32 val; | |
5038 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
5039 | ||
5040 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
5041 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
5042 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
51c1a580 | 5043 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
f2e0899f | 5044 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
51c1a580 | 5045 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
f2e0899f | 5046 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
51c1a580 | 5047 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
f2e0899f | 5048 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
51c1a580 | 5049 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
f2e0899f DK |
5050 | if (val & |
5051 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
51c1a580 | 5052 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
f2e0899f DK |
5053 | if (val & |
5054 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
51c1a580 | 5055 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
f2e0899f | 5056 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
51c1a580 | 5057 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
f2e0899f | 5058 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
51c1a580 | 5059 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
f2e0899f | 5060 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
51c1a580 | 5061 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
f2e0899f DK |
5062 | } |
5063 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
5064 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
5065 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
5066 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
5067 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
5068 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
51c1a580 | 5069 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
f2e0899f | 5070 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
51c1a580 | 5071 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
f2e0899f | 5072 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
51c1a580 | 5073 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
f2e0899f DK |
5074 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
5075 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
5076 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
51c1a580 | 5077 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
f2e0899f DK |
5078 | } |
5079 | ||
5080 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
5081 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
5082 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
5083 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
5084 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
5085 | } | |
f2e0899f DK |
5086 | } |
5087 | ||
72fd0718 VZ |
5088 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
5089 | { | |
5090 | struct attn_route attn, *group_mask; | |
34f80b04 | 5091 | int port = BP_PORT(bp); |
877e9aa4 | 5092 | int index; |
a2fbb9ea ET |
5093 | u32 reg_addr; |
5094 | u32 val; | |
3fcaf2e5 | 5095 | u32 aeu_mask; |
c9ee9206 | 5096 | bool global = false; |
a2fbb9ea ET |
5097 | |
5098 | /* need to take HW lock because MCP or other port might also | |
5099 | try to handle this event */ | |
4a37fb66 | 5100 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 5101 | |
c9ee9206 VZ |
5102 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
5103 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 5104 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 5105 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
5106 | /* Disable HW interrupts */ |
5107 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
5108 | /* In case of parity errors don't handle attentions so that |
5109 | * other function would "see" parity errors. | |
5110 | */ | |
c9ee9206 VZ |
5111 | #else |
5112 | bnx2x_panic(); | |
5113 | #endif | |
5114 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
5115 | return; |
5116 | } | |
5117 | ||
a2fbb9ea ET |
5118 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
5119 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
5120 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
5121 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 5122 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5123 | attn.sig[4] = |
5124 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
5125 | else | |
5126 | attn.sig[4] = 0; | |
5127 | ||
5128 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
5129 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
5130 | |
5131 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
5132 | if (deasserted & (1 << index)) { | |
72fd0718 | 5133 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 5134 | |
51c1a580 | 5135 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
f2e0899f DK |
5136 | index, |
5137 | group_mask->sig[0], group_mask->sig[1], | |
5138 | group_mask->sig[2], group_mask->sig[3], | |
5139 | group_mask->sig[4]); | |
a2fbb9ea | 5140 | |
f2e0899f DK |
5141 | bnx2x_attn_int_deasserted4(bp, |
5142 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 5143 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 5144 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 5145 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 5146 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 5147 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 5148 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 5149 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 5150 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
5151 | } |
5152 | } | |
5153 | ||
4a37fb66 | 5154 | bnx2x_release_alr(bp); |
a2fbb9ea | 5155 | |
f2e0899f DK |
5156 | if (bp->common.int_block == INT_BLOCK_HC) |
5157 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
5158 | COMMAND_REG_ATTN_BITS_CLR); | |
5159 | else | |
5160 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
5161 | |
5162 | val = ~deasserted; | |
f2e0899f DK |
5163 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
5164 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 5165 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 5166 | |
a2fbb9ea | 5167 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 5168 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
5169 | |
5170 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
5171 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
5172 | ||
3fcaf2e5 EG |
5173 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
5174 | aeu_mask = REG_RD(bp, reg_addr); | |
5175 | ||
5176 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
5177 | aeu_mask, deasserted); | |
72fd0718 | 5178 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 5179 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 5180 | |
3fcaf2e5 EG |
5181 | REG_WR(bp, reg_addr, aeu_mask); |
5182 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
5183 | |
5184 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
5185 | bp->attn_state &= ~deasserted; | |
5186 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
5187 | } | |
5188 | ||
5189 | static void bnx2x_attn_int(struct bnx2x *bp) | |
5190 | { | |
5191 | /* read local copy of bits */ | |
68d59484 EG |
5192 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
5193 | attn_bits); | |
5194 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
5195 | attn_bits_ack); | |
a2fbb9ea ET |
5196 | u32 attn_state = bp->attn_state; |
5197 | ||
5198 | /* look for changed bits */ | |
5199 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
5200 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
5201 | ||
5202 | DP(NETIF_MSG_HW, | |
5203 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
5204 | attn_bits, attn_ack, asserted, deasserted); | |
5205 | ||
5206 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 5207 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
5208 | |
5209 | /* handle bits that were raised */ | |
5210 | if (asserted) | |
5211 | bnx2x_attn_int_asserted(bp, asserted); | |
5212 | ||
5213 | if (deasserted) | |
5214 | bnx2x_attn_int_deasserted(bp, deasserted); | |
5215 | } | |
5216 | ||
619c5cb6 VZ |
5217 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
5218 | u16 index, u8 op, u8 update) | |
5219 | { | |
dc1ba591 AE |
5220 | u32 igu_addr = bp->igu_base_addr; |
5221 | igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
619c5cb6 VZ |
5222 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, |
5223 | igu_addr); | |
5224 | } | |
5225 | ||
1191cb83 | 5226 | static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
523224a3 DK |
5227 | { |
5228 | /* No memory barriers */ | |
5229 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
5230 | mmiowb(); /* keep prod updates ordered */ | |
5231 | } | |
5232 | ||
523224a3 DK |
5233 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, |
5234 | union event_ring_elem *elem) | |
5235 | { | |
619c5cb6 VZ |
5236 | u8 err = elem->message.error; |
5237 | ||
523224a3 | 5238 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
5239 | (cid < bp->cnic_eth_dev.starting_cid && |
5240 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
5241 | return 1; |
5242 | ||
5243 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
5244 | ||
619c5cb6 VZ |
5245 | if (unlikely(err)) { |
5246 | ||
523224a3 DK |
5247 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
5248 | cid); | |
823e1d90 | 5249 | bnx2x_panic_dump(bp, false); |
523224a3 | 5250 | } |
619c5cb6 | 5251 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
5252 | return 0; |
5253 | } | |
523224a3 | 5254 | |
1191cb83 | 5255 | static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
5256 | { |
5257 | struct bnx2x_mcast_ramrod_params rparam; | |
5258 | int rc; | |
5259 | ||
5260 | memset(&rparam, 0, sizeof(rparam)); | |
5261 | ||
5262 | rparam.mcast_obj = &bp->mcast_obj; | |
5263 | ||
5264 | netif_addr_lock_bh(bp->dev); | |
5265 | ||
5266 | /* Clear pending state for the last command */ | |
5267 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
5268 | ||
5269 | /* If there are pending mcast commands - send them */ | |
5270 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
5271 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
5272 | if (rc < 0) | |
5273 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
5274 | rc); | |
5275 | } | |
5276 | ||
5277 | netif_addr_unlock_bh(bp->dev); | |
5278 | } | |
5279 | ||
1191cb83 ED |
5280 | static void bnx2x_handle_classification_eqe(struct bnx2x *bp, |
5281 | union event_ring_elem *elem) | |
619c5cb6 VZ |
5282 | { |
5283 | unsigned long ramrod_flags = 0; | |
5284 | int rc = 0; | |
5285 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
5286 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
5287 | ||
5288 | /* Always push next commands out, don't wait here */ | |
5289 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
5290 | ||
86564c3f YM |
5291 | switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo) |
5292 | >> BNX2X_SWCID_SHIFT) { | |
619c5cb6 | 5293 | case BNX2X_FILTER_MAC_PENDING: |
51c1a580 | 5294 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
55c11941 | 5295 | if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) |
619c5cb6 VZ |
5296 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; |
5297 | else | |
15192a8c | 5298 | vlan_mac_obj = &bp->sp_objs[cid].mac_obj; |
619c5cb6 | 5299 | |
05cc5a39 YM |
5300 | break; |
5301 | case BNX2X_FILTER_VLAN_PENDING: | |
5302 | DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n"); | |
5303 | vlan_mac_obj = &bp->sp_objs[cid].vlan_obj; | |
619c5cb6 | 5304 | break; |
619c5cb6 | 5305 | case BNX2X_FILTER_MCAST_PENDING: |
51c1a580 | 5306 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
619c5cb6 VZ |
5307 | /* This is only relevant for 57710 where multicast MACs are |
5308 | * configured as unicast MACs using the same ramrod. | |
5309 | */ | |
5310 | bnx2x_handle_mcast_eqe(bp); | |
5311 | return; | |
5312 | default: | |
5313 | BNX2X_ERR("Unsupported classification command: %d\n", | |
5314 | elem->message.data.eth_event.echo); | |
5315 | return; | |
5316 | } | |
5317 | ||
5318 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
5319 | ||
5320 | if (rc < 0) | |
5321 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
5322 | else if (rc > 0) | |
5323 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
619c5cb6 VZ |
5324 | } |
5325 | ||
619c5cb6 | 5326 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); |
619c5cb6 | 5327 | |
1191cb83 | 5328 | static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
5329 | { |
5330 | netif_addr_lock_bh(bp->dev); | |
5331 | ||
5332 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5333 | ||
5334 | /* Send rx_mode command again if was requested */ | |
5335 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
5336 | bnx2x_set_storm_rx_mode(bp); | |
619c5cb6 VZ |
5337 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, |
5338 | &bp->sp_state)) | |
5339 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
5340 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
5341 | &bp->sp_state)) | |
5342 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
619c5cb6 VZ |
5343 | |
5344 | netif_addr_unlock_bh(bp->dev); | |
5345 | } | |
5346 | ||
1191cb83 | 5347 | static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, |
a3348722 BW |
5348 | union event_ring_elem *elem) |
5349 | { | |
5350 | if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { | |
5351 | DP(BNX2X_MSG_SP, | |
5352 | "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", | |
5353 | elem->message.data.vif_list_event.func_bit_map); | |
5354 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, | |
5355 | elem->message.data.vif_list_event.func_bit_map); | |
5356 | } else if (elem->message.data.vif_list_event.echo == | |
5357 | VIF_LIST_RULE_SET) { | |
5358 | DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); | |
5359 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); | |
5360 | } | |
5361 | } | |
5362 | ||
5363 | /* called with rtnl_lock */ | |
1191cb83 | 5364 | static void bnx2x_after_function_update(struct bnx2x *bp) |
a3348722 BW |
5365 | { |
5366 | int q, rc; | |
5367 | struct bnx2x_fastpath *fp; | |
5368 | struct bnx2x_queue_state_params queue_params = {NULL}; | |
5369 | struct bnx2x_queue_update_params *q_update_params = | |
5370 | &queue_params.params.update; | |
5371 | ||
2de67439 | 5372 | /* Send Q update command with afex vlan removal values for all Qs */ |
a3348722 BW |
5373 | queue_params.cmd = BNX2X_Q_CMD_UPDATE; |
5374 | ||
5375 | /* set silent vlan removal values according to vlan mode */ | |
5376 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | |
5377 | &q_update_params->update_flags); | |
5378 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
5379 | &q_update_params->update_flags); | |
5380 | __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
5381 | ||
5382 | /* in access mode mark mask and value are 0 to strip all vlans */ | |
5383 | if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { | |
5384 | q_update_params->silent_removal_value = 0; | |
5385 | q_update_params->silent_removal_mask = 0; | |
5386 | } else { | |
5387 | q_update_params->silent_removal_value = | |
5388 | (bp->afex_def_vlan_tag & VLAN_VID_MASK); | |
5389 | q_update_params->silent_removal_mask = VLAN_VID_MASK; | |
5390 | } | |
5391 | ||
5392 | for_each_eth_queue(bp, q) { | |
5393 | /* Set the appropriate Queue object */ | |
5394 | fp = &bp->fp[q]; | |
15192a8c | 5395 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
5396 | |
5397 | /* send the ramrod */ | |
5398 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
5399 | if (rc < 0) | |
5400 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
5401 | q); | |
5402 | } | |
5403 | ||
fea75645 | 5404 | if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { |
65565884 | 5405 | fp = &bp->fp[FCOE_IDX(bp)]; |
15192a8c | 5406 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
5407 | |
5408 | /* clear pending completion bit */ | |
5409 | __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
5410 | ||
5411 | /* mark latest Q bit */ | |
4e857c58 | 5412 | smp_mb__before_atomic(); |
a3348722 | 5413 | set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); |
4e857c58 | 5414 | smp_mb__after_atomic(); |
a3348722 BW |
5415 | |
5416 | /* send Q update ramrod for FCoE Q */ | |
5417 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
5418 | if (rc < 0) | |
5419 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
5420 | q); | |
5421 | } else { | |
5422 | /* If no FCoE ring - ACK MCP now */ | |
5423 | bnx2x_link_report(bp); | |
5424 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5425 | } | |
a3348722 BW |
5426 | } |
5427 | ||
1191cb83 | 5428 | static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( |
619c5cb6 VZ |
5429 | struct bnx2x *bp, u32 cid) |
5430 | { | |
94f05b0f | 5431 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
55c11941 MS |
5432 | |
5433 | if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) | |
15192a8c | 5434 | return &bnx2x_fcoe_sp_obj(bp, q_obj); |
619c5cb6 | 5435 | else |
15192a8c | 5436 | return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; |
619c5cb6 VZ |
5437 | } |
5438 | ||
523224a3 DK |
5439 | static void bnx2x_eq_int(struct bnx2x *bp) |
5440 | { | |
5441 | u16 hw_cons, sw_cons, sw_prod; | |
5442 | union event_ring_elem *elem; | |
55c11941 | 5443 | u8 echo; |
523224a3 DK |
5444 | u32 cid; |
5445 | u8 opcode; | |
fd1fc79d | 5446 | int rc, spqe_cnt = 0; |
619c5cb6 VZ |
5447 | struct bnx2x_queue_sp_obj *q_obj; |
5448 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
5449 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
5450 | |
5451 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
5452 | ||
5453 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
16a5fd92 | 5454 | * when we get the next-page we need to adjust so the loop |
523224a3 DK |
5455 | * condition below will be met. The next element is the size of a |
5456 | * regular element and hence incrementing by 1 | |
5457 | */ | |
5458 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
5459 | hw_cons++; | |
5460 | ||
25985edc | 5461 | /* This function may never run in parallel with itself for a |
523224a3 DK |
5462 | * specific bp, thus there is no need in "paired" read memory |
5463 | * barrier here. | |
5464 | */ | |
5465 | sw_cons = bp->eq_cons; | |
5466 | sw_prod = bp->eq_prod; | |
5467 | ||
d6cae238 | 5468 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 5469 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
5470 | |
5471 | for (; sw_cons != hw_cons; | |
5472 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
5473 | ||
523224a3 DK |
5474 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; |
5475 | ||
fd1fc79d AE |
5476 | rc = bnx2x_iov_eq_sp_event(bp, elem); |
5477 | if (!rc) { | |
5478 | DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", | |
5479 | rc); | |
5480 | goto next_spqe; | |
5481 | } | |
523224a3 | 5482 | |
86564c3f YM |
5483 | /* elem CID originates from FW; actually LE */ |
5484 | cid = SW_CID((__force __le32) | |
5485 | elem->message.data.cfc_del_event.cid); | |
5486 | opcode = elem->message.opcode; | |
523224a3 DK |
5487 | |
5488 | /* handle eq element */ | |
5489 | switch (opcode) { | |
fd1fc79d | 5490 | case EVENT_RING_OPCODE_VF_PF_CHANNEL: |
370d4a26 YM |
5491 | bnx2x_vf_mbx_schedule(bp, |
5492 | &elem->message.data.vf_pf_event); | |
fd1fc79d AE |
5493 | continue; |
5494 | ||
523224a3 | 5495 | case EVENT_RING_OPCODE_STAT_QUERY: |
76ca70fa YM |
5496 | DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS), |
5497 | "got statistics comp event %d\n", | |
5498 | bp->stats_comp++); | |
523224a3 | 5499 | /* nothing to do with stats comp */ |
d6cae238 | 5500 | goto next_spqe; |
523224a3 DK |
5501 | |
5502 | case EVENT_RING_OPCODE_CFC_DEL: | |
5503 | /* handle according to cid range */ | |
5504 | /* | |
5505 | * we may want to verify here that the bp state is | |
5506 | * HALTING | |
5507 | */ | |
d6cae238 | 5508 | DP(BNX2X_MSG_SP, |
523224a3 | 5509 | "got delete ramrod for MULTI[%d]\n", cid); |
55c11941 MS |
5510 | |
5511 | if (CNIC_LOADED(bp) && | |
5512 | !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
523224a3 | 5513 | goto next_spqe; |
55c11941 | 5514 | |
619c5cb6 VZ |
5515 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
5516 | ||
5517 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
5518 | break; | |
5519 | ||
523224a3 | 5520 | goto next_spqe; |
e4901dde VZ |
5521 | |
5522 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
51c1a580 | 5523 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
6ffa39f2 | 5524 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
6debea87 DK |
5525 | if (f_obj->complete_cmd(bp, f_obj, |
5526 | BNX2X_F_CMD_TX_STOP)) | |
5527 | break; | |
e4901dde | 5528 | goto next_spqe; |
619c5cb6 | 5529 | |
e4901dde | 5530 | case EVENT_RING_OPCODE_START_TRAFFIC: |
51c1a580 | 5531 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
6ffa39f2 | 5532 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
6debea87 DK |
5533 | if (f_obj->complete_cmd(bp, f_obj, |
5534 | BNX2X_F_CMD_TX_START)) | |
5535 | break; | |
e4901dde | 5536 | goto next_spqe; |
55c11941 | 5537 | |
a3348722 | 5538 | case EVENT_RING_OPCODE_FUNCTION_UPDATE: |
55c11941 MS |
5539 | echo = elem->message.data.function_update_event.echo; |
5540 | if (echo == SWITCH_UPDATE) { | |
5541 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, | |
5542 | "got FUNC_SWITCH_UPDATE ramrod\n"); | |
5543 | if (f_obj->complete_cmd( | |
5544 | bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) | |
5545 | break; | |
a3348722 | 5546 | |
55c11941 | 5547 | } else { |
230bb0f3 YM |
5548 | int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE; |
5549 | ||
55c11941 MS |
5550 | DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, |
5551 | "AFEX: ramrod completed FUNCTION_UPDATE\n"); | |
5552 | f_obj->complete_cmd(bp, f_obj, | |
5553 | BNX2X_F_CMD_AFEX_UPDATE); | |
5554 | ||
5555 | /* We will perform the Queues update from | |
5556 | * sp_rtnl task as all Queue SP operations | |
5557 | * should run under rtnl_lock. | |
5558 | */ | |
230bb0f3 | 5559 | bnx2x_schedule_sp_rtnl(bp, cmd, 0); |
55c11941 | 5560 | } |
a3348722 | 5561 | |
a3348722 BW |
5562 | goto next_spqe; |
5563 | ||
5564 | case EVENT_RING_OPCODE_AFEX_VIF_LISTS: | |
5565 | f_obj->complete_cmd(bp, f_obj, | |
5566 | BNX2X_F_CMD_AFEX_VIFLISTS); | |
5567 | bnx2x_after_afex_vif_lists(bp, elem); | |
5568 | goto next_spqe; | |
619c5cb6 | 5569 | case EVENT_RING_OPCODE_FUNCTION_START: |
51c1a580 MS |
5570 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5571 | "got FUNC_START ramrod\n"); | |
619c5cb6 VZ |
5572 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
5573 | break; | |
5574 | ||
5575 | goto next_spqe; | |
5576 | ||
5577 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
51c1a580 MS |
5578 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5579 | "got FUNC_STOP ramrod\n"); | |
619c5cb6 VZ |
5580 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
5581 | break; | |
5582 | ||
5583 | goto next_spqe; | |
eeed018c MK |
5584 | |
5585 | case EVENT_RING_OPCODE_SET_TIMESYNC: | |
5586 | DP(BNX2X_MSG_SP | BNX2X_MSG_PTP, | |
5587 | "got set_timesync ramrod completion\n"); | |
5588 | if (f_obj->complete_cmd(bp, f_obj, | |
5589 | BNX2X_F_CMD_SET_TIMESYNC)) | |
5590 | break; | |
5591 | goto next_spqe; | |
523224a3 DK |
5592 | } |
5593 | ||
5594 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
5595 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
5596 | BNX2X_STATE_OPEN): | |
5597 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 5598 | BNX2X_STATE_OPENING_WAIT4_PORT): |
28311f8e YM |
5599 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
5600 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
619c5cb6 VZ |
5601 | cid = elem->message.data.eth_event.echo & |
5602 | BNX2X_SWCID_MASK; | |
d6cae238 | 5603 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
619c5cb6 VZ |
5604 | cid); |
5605 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
5606 | break; |
5607 | ||
619c5cb6 VZ |
5608 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
5609 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
5610 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 5611 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
5612 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
5613 | BNX2X_STATE_OPEN): | |
5614 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5615 | BNX2X_STATE_DIAG): | |
5616 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5617 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
05cc5a39 | 5618 | DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n"); |
619c5cb6 | 5619 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
5620 | break; |
5621 | ||
619c5cb6 VZ |
5622 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
5623 | BNX2X_STATE_OPEN): | |
5624 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5625 | BNX2X_STATE_DIAG): | |
5626 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5627 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5628 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 5629 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
5630 | break; |
5631 | ||
619c5cb6 VZ |
5632 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
5633 | BNX2X_STATE_OPEN): | |
5634 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
5635 | BNX2X_STATE_DIAG): | |
5636 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 5637 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 5638 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 5639 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
5640 | break; |
5641 | default: | |
5642 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
5643 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
5644 | elem->message.opcode, bp->state); | |
523224a3 DK |
5645 | } |
5646 | next_spqe: | |
5647 | spqe_cnt++; | |
5648 | } /* for */ | |
5649 | ||
4e857c58 | 5650 | smp_mb__before_atomic(); |
6e30dd4e | 5651 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
5652 | |
5653 | bp->eq_cons = sw_cons; | |
5654 | bp->eq_prod = sw_prod; | |
5655 | /* Make sure that above mem writes were issued towards the memory */ | |
5656 | smp_wmb(); | |
5657 | ||
5658 | /* update producer */ | |
5659 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
5660 | } | |
5661 | ||
a2fbb9ea ET |
5662 | static void bnx2x_sp_task(struct work_struct *work) |
5663 | { | |
1cf167f2 | 5664 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea | 5665 | |
fd1fc79d | 5666 | DP(BNX2X_MSG_SP, "sp task invoked\n"); |
a2fbb9ea | 5667 | |
16a5fd92 | 5668 | /* make sure the atomic interrupt_occurred has been written */ |
fd1fc79d AE |
5669 | smp_rmb(); |
5670 | if (atomic_read(&bp->interrupt_occurred)) { | |
a2fbb9ea | 5671 | |
fd1fc79d AE |
5672 | /* what work needs to be performed? */ |
5673 | u16 status = bnx2x_update_dsb_idx(bp); | |
cdaa7cb8 | 5674 | |
fd1fc79d AE |
5675 | DP(BNX2X_MSG_SP, "status %x\n", status); |
5676 | DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); | |
5677 | atomic_set(&bp->interrupt_occurred, 0); | |
5678 | ||
5679 | /* HW attentions */ | |
5680 | if (status & BNX2X_DEF_SB_ATT_IDX) { | |
5681 | bnx2x_attn_int(bp); | |
5682 | status &= ~BNX2X_DEF_SB_ATT_IDX; | |
5683 | } | |
5684 | ||
5685 | /* SP events: STAT_QUERY and others */ | |
5686 | if (status & BNX2X_DEF_SB_IDX) { | |
5687 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 5688 | |
55c11941 | 5689 | if (FCOE_INIT(bp) && |
fd1fc79d AE |
5690 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
5691 | /* Prevent local bottom-halves from running as | |
5692 | * we are going to change the local NAPI list. | |
5693 | */ | |
5694 | local_bh_disable(); | |
5695 | napi_schedule(&bnx2x_fcoe(bp, napi)); | |
5696 | local_bh_enable(); | |
5697 | } | |
5698 | ||
5699 | /* Handle EQ completions */ | |
5700 | bnx2x_eq_int(bp); | |
5701 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
5702 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
5703 | ||
5704 | status &= ~BNX2X_DEF_SB_IDX; | |
019dbb4c | 5705 | } |
55c11941 | 5706 | |
fd1fc79d AE |
5707 | /* if status is non zero then perhaps something went wrong */ |
5708 | if (unlikely(status)) | |
5709 | DP(BNX2X_MSG_SP, | |
5710 | "got an unknown interrupt! (status 0x%x)\n", status); | |
523224a3 | 5711 | |
fd1fc79d AE |
5712 | /* ack status block only if something was actually handled */ |
5713 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, | |
5714 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
cdaa7cb8 VZ |
5715 | } |
5716 | ||
a3348722 BW |
5717 | /* afex - poll to check if VIFSET_ACK should be sent to MFW */ |
5718 | if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, | |
5719 | &bp->sp_state)) { | |
5720 | bnx2x_link_report(bp); | |
5721 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5722 | } | |
a2fbb9ea ET |
5723 | } |
5724 | ||
9f6c9258 | 5725 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
5726 | { |
5727 | struct net_device *dev = dev_instance; | |
5728 | struct bnx2x *bp = netdev_priv(dev); | |
5729 | ||
523224a3 DK |
5730 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
5731 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
5732 | |
5733 | #ifdef BNX2X_STOP_ON_ERROR | |
5734 | if (unlikely(bp->panic)) | |
5735 | return IRQ_HANDLED; | |
5736 | #endif | |
5737 | ||
55c11941 | 5738 | if (CNIC_LOADED(bp)) { |
993ac7b5 MC |
5739 | struct cnic_ops *c_ops; |
5740 | ||
5741 | rcu_read_lock(); | |
5742 | c_ops = rcu_dereference(bp->cnic_ops); | |
5743 | if (c_ops) | |
5744 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
5745 | rcu_read_unlock(); | |
5746 | } | |
55c11941 | 5747 | |
fd1fc79d AE |
5748 | /* schedule sp task to perform default status block work, ack |
5749 | * attentions and enable interrupts. | |
5750 | */ | |
5751 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
5752 | |
5753 | return IRQ_HANDLED; | |
5754 | } | |
5755 | ||
5756 | /* end of slow path */ | |
5757 | ||
619c5cb6 VZ |
5758 | void bnx2x_drv_pulse(struct bnx2x *bp) |
5759 | { | |
5760 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
5761 | bp->fw_drv_pulse_wr_seq); | |
5762 | } | |
5763 | ||
a2fbb9ea ET |
5764 | static void bnx2x_timer(unsigned long data) |
5765 | { | |
5766 | struct bnx2x *bp = (struct bnx2x *) data; | |
5767 | ||
5768 | if (!netif_running(bp->dev)) | |
5769 | return; | |
5770 | ||
67c431a5 AE |
5771 | if (IS_PF(bp) && |
5772 | !BP_NOMCP(bp)) { | |
f2e0899f | 5773 | int mb_idx = BP_FW_MB_IDX(bp); |
4c868664 EG |
5774 | u16 drv_pulse; |
5775 | u16 mcp_pulse; | |
a2fbb9ea ET |
5776 | |
5777 | ++bp->fw_drv_pulse_wr_seq; | |
5778 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
a2fbb9ea | 5779 | drv_pulse = bp->fw_drv_pulse_wr_seq; |
619c5cb6 | 5780 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 5781 | |
f2e0899f | 5782 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
5783 | MCP_PULSE_SEQ_MASK); |
5784 | /* The delta between driver pulse and mcp response | |
4c868664 EG |
5785 | * should not get too big. If the MFW is more than 5 pulses |
5786 | * behind, we should worry about it enough to generate an error | |
5787 | * log. | |
a2fbb9ea | 5788 | */ |
4c868664 EG |
5789 | if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5) |
5790 | BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
a2fbb9ea | 5791 | drv_pulse, mcp_pulse); |
a2fbb9ea ET |
5792 | } |
5793 | ||
f34d28ea | 5794 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 5795 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 5796 | |
abc5a021 | 5797 | /* sample pf vf bulletin board for new posts from pf */ |
37173488 YM |
5798 | if (IS_VF(bp)) |
5799 | bnx2x_timer_sriov(bp); | |
78c3bcc5 | 5800 | |
a2fbb9ea ET |
5801 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
5802 | } | |
5803 | ||
5804 | /* end of Statistics */ | |
5805 | ||
5806 | /* nic init */ | |
5807 | ||
5808 | /* | |
5809 | * nic init service functions | |
5810 | */ | |
5811 | ||
1191cb83 | 5812 | static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 5813 | { |
523224a3 DK |
5814 | u32 i; |
5815 | if (!(len%4) && !(addr%4)) | |
5816 | for (i = 0; i < len; i += 4) | |
5817 | REG_WR(bp, addr + i, fill); | |
5818 | else | |
5819 | for (i = 0; i < len; i++) | |
5820 | REG_WR8(bp, addr + i, fill); | |
34f80b04 EG |
5821 | } |
5822 | ||
523224a3 | 5823 | /* helper: writes FP SP data to FW - data_size in dwords */ |
1191cb83 ED |
5824 | static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, |
5825 | int fw_sb_id, | |
5826 | u32 *sb_data_p, | |
5827 | u32 data_size) | |
34f80b04 | 5828 | { |
a2fbb9ea | 5829 | int index; |
523224a3 DK |
5830 | for (index = 0; index < data_size; index++) |
5831 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5832 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
5833 | sizeof(u32)*index, | |
5834 | *(sb_data_p + index)); | |
5835 | } | |
a2fbb9ea | 5836 | |
1191cb83 | 5837 | static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
523224a3 DK |
5838 | { |
5839 | u32 *sb_data_p; | |
5840 | u32 data_size = 0; | |
f2e0899f | 5841 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 5842 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 5843 | |
523224a3 | 5844 | /* disable the function first */ |
619c5cb6 | 5845 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5846 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5847 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
5848 | sb_data_e2.common.p_func.vf_valid = false; |
5849 | sb_data_p = (u32 *)&sb_data_e2; | |
5850 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
5851 | } else { | |
5852 | memset(&sb_data_e1x, 0, | |
5853 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5854 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
5855 | sb_data_e1x.common.p_func.vf_valid = false; |
5856 | sb_data_p = (u32 *)&sb_data_e1x; | |
5857 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
5858 | } | |
523224a3 | 5859 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 5860 | |
523224a3 DK |
5861 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
5862 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
5863 | CSTORM_STATUS_BLOCK_SIZE); | |
5864 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5865 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
5866 | CSTORM_SYNC_BLOCK_SIZE); | |
5867 | } | |
34f80b04 | 5868 | |
523224a3 | 5869 | /* helper: writes SP SB data to FW */ |
1191cb83 | 5870 | static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, |
523224a3 DK |
5871 | struct hc_sp_status_block_data *sp_sb_data) |
5872 | { | |
5873 | int func = BP_FUNC(bp); | |
5874 | int i; | |
5875 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
5876 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5877 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
5878 | i*sizeof(u32), | |
5879 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
5880 | } |
5881 | ||
1191cb83 | 5882 | static void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
5883 | { |
5884 | int func = BP_FUNC(bp); | |
523224a3 DK |
5885 | struct hc_sp_status_block_data sp_sb_data; |
5886 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 5887 | |
619c5cb6 | 5888 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
5889 | sp_sb_data.p_func.vf_valid = false; |
5890 | ||
5891 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
5892 | ||
5893 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5894 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
5895 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
5896 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5897 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
5898 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
523224a3 DK |
5899 | } |
5900 | ||
1191cb83 | 5901 | static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, |
523224a3 DK |
5902 | int igu_sb_id, int igu_seg_id) |
5903 | { | |
5904 | hc_sm->igu_sb_id = igu_sb_id; | |
5905 | hc_sm->igu_seg_id = igu_seg_id; | |
5906 | hc_sm->timer_value = 0xFF; | |
5907 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
5908 | } |
5909 | ||
150966ad | 5910 | /* allocates state machine ids. */ |
1191cb83 | 5911 | static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) |
150966ad AE |
5912 | { |
5913 | /* zero out state machine indices */ | |
5914 | /* rx indices */ | |
5915 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5916 | ||
5917 | /* tx indices */ | |
5918 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5919 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
5920 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
5921 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
5922 | ||
5923 | /* map indices */ | |
5924 | /* rx indices */ | |
5925 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
5926 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5927 | ||
5928 | /* tx indices */ | |
5929 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
5930 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5931 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
5932 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5933 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
5934 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5935 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
5936 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5937 | } | |
5938 | ||
b93288d5 | 5939 | void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 5940 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 5941 | { |
523224a3 DK |
5942 | int igu_seg_id; |
5943 | ||
f2e0899f | 5944 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
5945 | struct hc_status_block_data_e1x sb_data_e1x; |
5946 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
5947 | int data_size; |
5948 | u32 *sb_data_p; | |
5949 | ||
f2e0899f DK |
5950 | if (CHIP_INT_MODE_IS_BC(bp)) |
5951 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
5952 | else | |
5953 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
5954 | |
5955 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
5956 | ||
619c5cb6 | 5957 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5958 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5959 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
5960 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
5961 | sb_data_e2.common.p_func.vf_id = vfid; | |
5962 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
5963 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
5964 | sb_data_e2.common.same_igu_sb_1b = true; | |
5965 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
5966 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
5967 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
5968 | sb_data_p = (u32 *)&sb_data_e2; |
5969 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 5970 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
5971 | } else { |
5972 | memset(&sb_data_e1x, 0, | |
5973 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5974 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
5975 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
5976 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
5977 | sb_data_e1x.common.p_func.vf_valid = false; | |
5978 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
5979 | sb_data_e1x.common.same_igu_sb_1b = true; | |
5980 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
5981 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
5982 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
5983 | sb_data_p = (u32 *)&sb_data_e1x; |
5984 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 5985 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 5986 | } |
523224a3 DK |
5987 | |
5988 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
5989 | igu_sb_id, igu_seg_id); | |
5990 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
5991 | igu_sb_id, igu_seg_id); | |
5992 | ||
51c1a580 | 5993 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
523224a3 | 5994 | |
86564c3f | 5995 | /* write indices to HW - PCI guarantees endianity of regpairs */ |
523224a3 DK |
5996 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
5997 | } | |
5998 | ||
619c5cb6 | 5999 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
6000 | u16 tx_usec, u16 rx_usec) |
6001 | { | |
6383c0b3 | 6002 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 6003 | false, rx_usec); |
6383c0b3 AE |
6004 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
6005 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
6006 | tx_usec); | |
6007 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
6008 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
6009 | tx_usec); | |
6010 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
6011 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
6012 | tx_usec); | |
523224a3 | 6013 | } |
f2e0899f | 6014 | |
523224a3 DK |
6015 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
6016 | { | |
6017 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
6018 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
6019 | int igu_sp_sb_index; | |
6020 | int igu_seg_id; | |
34f80b04 EG |
6021 | int port = BP_PORT(bp); |
6022 | int func = BP_FUNC(bp); | |
f2eaeb58 | 6023 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 6024 | u64 section; |
523224a3 DK |
6025 | int index; |
6026 | struct hc_sp_status_block_data sp_sb_data; | |
6027 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
6028 | ||
f2e0899f DK |
6029 | if (CHIP_INT_MODE_IS_BC(bp)) { |
6030 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
6031 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
6032 | } else { | |
6033 | igu_sp_sb_index = bp->igu_dsb_id; | |
6034 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
6035 | } | |
a2fbb9ea ET |
6036 | |
6037 | /* ATTN */ | |
523224a3 | 6038 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 6039 | atten_status_block); |
523224a3 | 6040 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 6041 | |
49d66772 ET |
6042 | bp->attn_state = 0; |
6043 | ||
a2fbb9ea ET |
6044 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
6045 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
6046 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
6047 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 6048 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
6049 | int sindex; |
6050 | /* take care of sig[0]..sig[4] */ | |
6051 | for (sindex = 0; sindex < 4; sindex++) | |
6052 | bp->attn_group[index].sig[sindex] = | |
6053 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 6054 | |
619c5cb6 | 6055 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6056 | /* |
6057 | * enable5 is separate from the rest of the registers, | |
6058 | * and therefore the address skip is 4 | |
6059 | * and not 16 between the different groups | |
6060 | */ | |
6061 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 6062 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
6063 | else |
6064 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
6065 | } |
6066 | ||
f2e0899f DK |
6067 | if (bp->common.int_block == INT_BLOCK_HC) { |
6068 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
6069 | HC_REG_ATTN_MSG0_ADDR_L); | |
6070 | ||
6071 | REG_WR(bp, reg_offset, U64_LO(section)); | |
6072 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 6073 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6074 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
6075 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
6076 | } | |
a2fbb9ea | 6077 | |
523224a3 DK |
6078 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
6079 | sp_sb); | |
a2fbb9ea | 6080 | |
523224a3 | 6081 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 6082 | |
86564c3f | 6083 | /* PCI guarantees endianity of regpairs */ |
619c5cb6 | 6084 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
6085 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
6086 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
6087 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
6088 | sp_sb_data.igu_seg_id = igu_seg_id; | |
6089 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 6090 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 6091 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 6092 | |
523224a3 | 6093 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 6094 | |
523224a3 | 6095 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
6096 | } |
6097 | ||
9f6c9258 | 6098 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 6099 | { |
a2fbb9ea ET |
6100 | int i; |
6101 | ||
ec6ba945 | 6102 | for_each_eth_queue(bp, i) |
523224a3 | 6103 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 6104 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
6105 | } |
6106 | ||
a2fbb9ea ET |
6107 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
6108 | { | |
a2fbb9ea | 6109 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 6110 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 6111 | |
a2fbb9ea | 6112 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
6113 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
6114 | bp->spq_prod_bd = bp->spq; | |
6115 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
6116 | } |
6117 | ||
523224a3 | 6118 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
6119 | { |
6120 | int i; | |
523224a3 DK |
6121 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
6122 | union event_ring_elem *elem = | |
6123 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 6124 | |
523224a3 DK |
6125 | elem->next_page.addr.hi = |
6126 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
6127 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
6128 | elem->next_page.addr.lo = | |
6129 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
6130 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 6131 | } |
523224a3 DK |
6132 | bp->eq_cons = 0; |
6133 | bp->eq_prod = NUM_EQ_DESC; | |
6134 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
16a5fd92 | 6135 | /* we want a warning message before it gets wrought... */ |
6e30dd4e VZ |
6136 | atomic_set(&bp->eq_spq_left, |
6137 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
6138 | } |
6139 | ||
619c5cb6 | 6140 | /* called with netif_addr_lock_bh() */ |
a8f47eb7 | 6141 | static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
6142 | unsigned long rx_mode_flags, | |
6143 | unsigned long rx_accept_flags, | |
6144 | unsigned long tx_accept_flags, | |
6145 | unsigned long ramrod_flags) | |
ab532cf3 | 6146 | { |
619c5cb6 VZ |
6147 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
6148 | int rc; | |
6149 | ||
6150 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
6151 | ||
6152 | /* Prepare ramrod parameters */ | |
6153 | ramrod_param.cid = 0; | |
6154 | ramrod_param.cl_id = cl_id; | |
6155 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
6156 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 6157 | |
619c5cb6 VZ |
6158 | ramrod_param.pstate = &bp->sp_state; |
6159 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 6160 | |
619c5cb6 VZ |
6161 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
6162 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
6163 | ||
6164 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
6165 | ||
6166 | ramrod_param.ramrod_flags = ramrod_flags; | |
6167 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
6168 | ||
6169 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
6170 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
6171 | ||
6172 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
6173 | if (rc < 0) { | |
6174 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
924d75ab | 6175 | return rc; |
619c5cb6 | 6176 | } |
924d75ab YM |
6177 | |
6178 | return 0; | |
a2fbb9ea ET |
6179 | } |
6180 | ||
86564c3f YM |
6181 | static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, |
6182 | unsigned long *rx_accept_flags, | |
6183 | unsigned long *tx_accept_flags) | |
471de716 | 6184 | { |
924d75ab YM |
6185 | /* Clear the flags first */ |
6186 | *rx_accept_flags = 0; | |
6187 | *tx_accept_flags = 0; | |
619c5cb6 | 6188 | |
924d75ab | 6189 | switch (rx_mode) { |
619c5cb6 VZ |
6190 | case BNX2X_RX_MODE_NONE: |
6191 | /* | |
6192 | * 'drop all' supersedes any accept flags that may have been | |
6193 | * passed to the function. | |
6194 | */ | |
6195 | break; | |
6196 | case BNX2X_RX_MODE_NORMAL: | |
924d75ab YM |
6197 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
6198 | __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags); | |
6199 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
6200 | |
6201 | /* internal switching mode */ | |
924d75ab YM |
6202 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
6203 | __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags); | |
6204 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 | 6205 | |
05cc5a39 YM |
6206 | if (bp->accept_any_vlan) { |
6207 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); | |
6208 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); | |
6209 | } | |
6210 | ||
619c5cb6 VZ |
6211 | break; |
6212 | case BNX2X_RX_MODE_ALLMULTI: | |
924d75ab YM |
6213 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
6214 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); | |
6215 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
6216 | |
6217 | /* internal switching mode */ | |
924d75ab YM |
6218 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
6219 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); | |
6220 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 | 6221 | |
05cc5a39 YM |
6222 | if (bp->accept_any_vlan) { |
6223 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); | |
6224 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); | |
6225 | } | |
6226 | ||
619c5cb6 VZ |
6227 | break; |
6228 | case BNX2X_RX_MODE_PROMISC: | |
16a5fd92 | 6229 | /* According to definition of SI mode, iface in promisc mode |
619c5cb6 VZ |
6230 | * should receive matched and unmatched (in resolution of port) |
6231 | * unicast packets. | |
6232 | */ | |
924d75ab YM |
6233 | __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags); |
6234 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); | |
6235 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); | |
6236 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
6237 | |
6238 | /* internal switching mode */ | |
924d75ab YM |
6239 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); |
6240 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 VZ |
6241 | |
6242 | if (IS_MF_SI(bp)) | |
924d75ab | 6243 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags); |
619c5cb6 | 6244 | else |
924d75ab | 6245 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
619c5cb6 | 6246 | |
05cc5a39 YM |
6247 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); |
6248 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); | |
6249 | ||
619c5cb6 VZ |
6250 | break; |
6251 | default: | |
924d75ab YM |
6252 | BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode); |
6253 | return -EINVAL; | |
619c5cb6 | 6254 | } |
de832a55 | 6255 | |
924d75ab YM |
6256 | return 0; |
6257 | } | |
6258 | ||
6259 | /* called with netif_addr_lock_bh() */ | |
a8f47eb7 | 6260 | static int bnx2x_set_storm_rx_mode(struct bnx2x *bp) |
924d75ab YM |
6261 | { |
6262 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; | |
6263 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
6264 | int rc; | |
6265 | ||
6266 | if (!NO_FCOE(bp)) | |
6267 | /* Configure rx_mode of FCoE Queue */ | |
6268 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
6269 | ||
6270 | rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, | |
6271 | &tx_accept_flags); | |
6272 | if (rc) | |
6273 | return rc; | |
6274 | ||
619c5cb6 VZ |
6275 | __set_bit(RAMROD_RX, &ramrod_flags); |
6276 | __set_bit(RAMROD_TX, &ramrod_flags); | |
6277 | ||
924d75ab YM |
6278 | return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, |
6279 | rx_accept_flags, tx_accept_flags, | |
6280 | ramrod_flags); | |
619c5cb6 VZ |
6281 | } |
6282 | ||
6283 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
6284 | { | |
6285 | int i; | |
6286 | ||
523224a3 DK |
6287 | /* Zero this manually as its initialization is |
6288 | currently missing in the initTool */ | |
6289 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 6290 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 6291 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 6292 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6293 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
6294 | CHIP_INT_MODE_IS_BC(bp) ? | |
6295 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
6296 | } | |
523224a3 | 6297 | } |
8a1c38d1 | 6298 | |
471de716 EG |
6299 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
6300 | { | |
6301 | switch (load_code) { | |
6302 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 6303 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
6304 | bnx2x_init_internal_common(bp); |
6305 | /* no break */ | |
6306 | ||
6307 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 6308 | /* nothing to do */ |
471de716 EG |
6309 | /* no break */ |
6310 | ||
6311 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
6312 | /* internal memory per function is |
6313 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
6314 | break; |
6315 | ||
6316 | default: | |
6317 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
6318 | break; | |
6319 | } | |
6320 | } | |
6321 | ||
619c5cb6 | 6322 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 6323 | { |
55c11941 | 6324 | return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 | 6325 | } |
523224a3 | 6326 | |
619c5cb6 VZ |
6327 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
6328 | { | |
55c11941 | 6329 | return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 VZ |
6330 | } |
6331 | ||
1191cb83 | 6332 | static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) |
619c5cb6 VZ |
6333 | { |
6334 | if (CHIP_IS_E1x(fp->bp)) | |
6335 | return BP_L_ID(fp->bp) + fp->index; | |
6336 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
6337 | return bnx2x_fp_igu_sb_id(fp); | |
6338 | } | |
6339 | ||
6383c0b3 | 6340 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
6341 | { |
6342 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 6343 | u8 cos; |
619c5cb6 | 6344 | unsigned long q_type = 0; |
6383c0b3 | 6345 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 6346 | fp->rx_queue = fp_idx; |
b3b83c3f | 6347 | fp->cid = fp_idx; |
619c5cb6 VZ |
6348 | fp->cl_id = bnx2x_fp_cl_id(fp); |
6349 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
6350 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 6351 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
6352 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
6353 | ||
523224a3 | 6354 | /* init shortcut */ |
619c5cb6 | 6355 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
7a752993 | 6356 | |
16a5fd92 | 6357 | /* Setup SB indices */ |
523224a3 | 6358 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; |
523224a3 | 6359 | |
619c5cb6 VZ |
6360 | /* Configure Queue State object */ |
6361 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
6362 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
6363 | |
6364 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
6365 | ||
6366 | /* init tx data */ | |
6367 | for_each_cos_in_tx_queue(fp, cos) { | |
65565884 MS |
6368 | bnx2x_init_txdata(bp, fp->txdata_ptr[cos], |
6369 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), | |
6370 | FP_COS_TO_TXQ(fp, cos, bp), | |
6371 | BNX2X_TX_SB_INDEX_BASE + cos, fp); | |
6372 | cids[cos] = fp->txdata_ptr[cos]->cid; | |
6383c0b3 AE |
6373 | } |
6374 | ||
ad5afc89 AE |
6375 | /* nothing more for vf to do here */ |
6376 | if (IS_VF(bp)) | |
6377 | return; | |
6378 | ||
6379 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
6380 | fp->fw_sb_id, fp->igu_sb_id); | |
6381 | bnx2x_update_fpsb_idx(fp); | |
15192a8c BW |
6382 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, |
6383 | fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 6384 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 VZ |
6385 | |
6386 | /** | |
6387 | * Configure classification DBs: Always enable Tx switching | |
6388 | */ | |
6389 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
6390 | ||
ad5afc89 AE |
6391 | DP(NETIF_MSG_IFUP, |
6392 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
6393 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
6394 | fp->igu_sb_id); | |
523224a3 DK |
6395 | } |
6396 | ||
1191cb83 ED |
6397 | static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) |
6398 | { | |
6399 | int i; | |
6400 | ||
6401 | for (i = 1; i <= NUM_TX_RINGS; i++) { | |
6402 | struct eth_tx_next_bd *tx_next_bd = | |
6403 | &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
6404 | ||
6405 | tx_next_bd->addr_hi = | |
6406 | cpu_to_le32(U64_HI(txdata->tx_desc_mapping + | |
6407 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
6408 | tx_next_bd->addr_lo = | |
6409 | cpu_to_le32(U64_LO(txdata->tx_desc_mapping + | |
6410 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
6411 | } | |
6412 | ||
639d65b8 YM |
6413 | *txdata->tx_cons_sb = cpu_to_le16(0); |
6414 | ||
1191cb83 ED |
6415 | SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); |
6416 | txdata->tx_db.data.zero_fill1 = 0; | |
6417 | txdata->tx_db.data.prod = 0; | |
6418 | ||
6419 | txdata->tx_pkt_prod = 0; | |
6420 | txdata->tx_pkt_cons = 0; | |
6421 | txdata->tx_bd_prod = 0; | |
6422 | txdata->tx_bd_cons = 0; | |
6423 | txdata->tx_pkt = 0; | |
6424 | } | |
6425 | ||
55c11941 MS |
6426 | static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) |
6427 | { | |
6428 | int i; | |
6429 | ||
6430 | for_each_tx_queue_cnic(bp, i) | |
6431 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); | |
6432 | } | |
d76a6111 | 6433 | |
1191cb83 ED |
6434 | static void bnx2x_init_tx_rings(struct bnx2x *bp) |
6435 | { | |
6436 | int i; | |
6437 | u8 cos; | |
6438 | ||
55c11941 | 6439 | for_each_eth_queue(bp, i) |
1191cb83 | 6440 | for_each_cos_in_tx_queue(&bp->fp[i], cos) |
65565884 | 6441 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); |
1191cb83 ED |
6442 | } |
6443 | ||
a8f47eb7 | 6444 | static void bnx2x_init_fcoe_fp(struct bnx2x *bp) |
6445 | { | |
6446 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
6447 | unsigned long q_type = 0; | |
6448 | ||
6449 | bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); | |
6450 | bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, | |
6451 | BNX2X_FCOE_ETH_CL_ID_IDX); | |
6452 | bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); | |
6453 | bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; | |
6454 | bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; | |
6455 | bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; | |
6456 | bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), | |
6457 | fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, | |
6458 | fp); | |
6459 | ||
6460 | DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); | |
6461 | ||
6462 | /* qZone id equals to FW (per path) client id */ | |
6463 | bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); | |
6464 | /* init shortcut */ | |
6465 | bnx2x_fcoe(bp, ustorm_rx_prods_offset) = | |
6466 | bnx2x_rx_ustorm_prods_offset(fp); | |
6467 | ||
6468 | /* Configure Queue State object */ | |
6469 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
6470 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6471 | ||
6472 | /* No multi-CoS for FCoE L2 client */ | |
6473 | BUG_ON(fp->max_cos != 1); | |
6474 | ||
6475 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, | |
6476 | &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6477 | bnx2x_sp_mapping(bp, q_rdata), q_type); | |
6478 | ||
6479 | DP(NETIF_MSG_IFUP, | |
6480 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
6481 | fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
6482 | fp->igu_sb_id); | |
6483 | } | |
6484 | ||
55c11941 | 6485 | void bnx2x_nic_init_cnic(struct bnx2x *bp) |
a2fbb9ea | 6486 | { |
ec6ba945 VZ |
6487 | if (!NO_FCOE(bp)) |
6488 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
6489 | |
6490 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
6491 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 6492 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 6493 | |
55c11941 MS |
6494 | /* ensure status block indices were read */ |
6495 | rmb(); | |
6496 | bnx2x_init_rx_rings_cnic(bp); | |
6497 | bnx2x_init_tx_rings_cnic(bp); | |
6498 | ||
6499 | /* flush all */ | |
6500 | mb(); | |
6501 | mmiowb(); | |
6502 | } | |
a2fbb9ea | 6503 | |
ecf01c22 | 6504 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp) |
55c11941 MS |
6505 | { |
6506 | int i; | |
6507 | ||
ecf01c22 | 6508 | /* Setup NIC internals and enable interrupts */ |
55c11941 MS |
6509 | for_each_eth_queue(bp, i) |
6510 | bnx2x_init_eth_fp(bp, i); | |
ad5afc89 AE |
6511 | |
6512 | /* ensure status block indices were read */ | |
6513 | rmb(); | |
6514 | bnx2x_init_rx_rings(bp); | |
6515 | bnx2x_init_tx_rings(bp); | |
6516 | ||
ecf01c22 YM |
6517 | if (IS_PF(bp)) { |
6518 | /* Initialize MOD_ABS interrupts */ | |
6519 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
6520 | bp->common.shmem_base, | |
6521 | bp->common.shmem2_base, BP_PORT(bp)); | |
ad5afc89 | 6522 | |
ecf01c22 YM |
6523 | /* initialize the default status block and sp ring */ |
6524 | bnx2x_init_def_sb(bp); | |
6525 | bnx2x_update_dsb_idx(bp); | |
6526 | bnx2x_init_sp_ring(bp); | |
3cdeec22 YM |
6527 | } else { |
6528 | bnx2x_memset_stats(bp); | |
ecf01c22 YM |
6529 | } |
6530 | } | |
16119785 | 6531 | |
ecf01c22 YM |
6532 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) |
6533 | { | |
523224a3 | 6534 | bnx2x_init_eq_ring(bp); |
471de716 | 6535 | bnx2x_init_internal(bp, load_code); |
523224a3 | 6536 | bnx2x_pf_init(bp); |
0ef00459 EG |
6537 | bnx2x_stats_init(bp); |
6538 | ||
0ef00459 EG |
6539 | /* flush all before enabling interrupts */ |
6540 | mb(); | |
6541 | mmiowb(); | |
6542 | ||
615f8fd9 | 6543 | bnx2x_int_enable(bp); |
eb8da205 EG |
6544 | |
6545 | /* Check for SPIO5 */ | |
6546 | bnx2x_attn_int_deasserted0(bp, | |
6547 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
6548 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
6549 | } |
6550 | ||
ecf01c22 | 6551 | /* gzip service functions */ |
a2fbb9ea ET |
6552 | static int bnx2x_gunzip_init(struct bnx2x *bp) |
6553 | { | |
1a983142 FT |
6554 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
6555 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
6556 | if (bp->gunzip_buf == NULL) |
6557 | goto gunzip_nomem1; | |
6558 | ||
6559 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
6560 | if (bp->strm == NULL) | |
6561 | goto gunzip_nomem2; | |
6562 | ||
7ab24bfd | 6563 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
6564 | if (bp->strm->workspace == NULL) |
6565 | goto gunzip_nomem3; | |
6566 | ||
6567 | return 0; | |
6568 | ||
6569 | gunzip_nomem3: | |
6570 | kfree(bp->strm); | |
6571 | bp->strm = NULL; | |
6572 | ||
6573 | gunzip_nomem2: | |
1a983142 FT |
6574 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6575 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6576 | bp->gunzip_buf = NULL; |
6577 | ||
6578 | gunzip_nomem1: | |
51c1a580 | 6579 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
a2fbb9ea ET |
6580 | return -ENOMEM; |
6581 | } | |
6582 | ||
6583 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
6584 | { | |
b3b83c3f | 6585 | if (bp->strm) { |
7ab24bfd | 6586 | vfree(bp->strm->workspace); |
b3b83c3f DK |
6587 | kfree(bp->strm); |
6588 | bp->strm = NULL; | |
6589 | } | |
a2fbb9ea ET |
6590 | |
6591 | if (bp->gunzip_buf) { | |
1a983142 FT |
6592 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6593 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6594 | bp->gunzip_buf = NULL; |
6595 | } | |
6596 | } | |
6597 | ||
94a78b79 | 6598 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
6599 | { |
6600 | int n, rc; | |
6601 | ||
6602 | /* check gzip header */ | |
94a78b79 VZ |
6603 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
6604 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 6605 | return -EINVAL; |
94a78b79 | 6606 | } |
a2fbb9ea ET |
6607 | |
6608 | n = 10; | |
6609 | ||
34f80b04 | 6610 | #define FNAME 0x8 |
a2fbb9ea ET |
6611 | |
6612 | if (zbuf[3] & FNAME) | |
6613 | while ((zbuf[n++] != 0) && (n < len)); | |
6614 | ||
94a78b79 | 6615 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
6616 | bp->strm->avail_in = len - n; |
6617 | bp->strm->next_out = bp->gunzip_buf; | |
6618 | bp->strm->avail_out = FW_BUF_SIZE; | |
6619 | ||
6620 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
6621 | if (rc != Z_OK) | |
6622 | return rc; | |
6623 | ||
6624 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
6625 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
6626 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
6627 | bp->strm->msg); | |
a2fbb9ea ET |
6628 | |
6629 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
6630 | if (bp->gunzip_outlen & 0x3) | |
51c1a580 MS |
6631 | netdev_err(bp->dev, |
6632 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", | |
cdaa7cb8 | 6633 | bp->gunzip_outlen); |
a2fbb9ea ET |
6634 | bp->gunzip_outlen >>= 2; |
6635 | ||
6636 | zlib_inflateEnd(bp->strm); | |
6637 | ||
6638 | if (rc == Z_STREAM_END) | |
6639 | return 0; | |
6640 | ||
6641 | return rc; | |
6642 | } | |
6643 | ||
6644 | /* nic load/unload */ | |
6645 | ||
6646 | /* | |
34f80b04 | 6647 | * General service functions |
a2fbb9ea ET |
6648 | */ |
6649 | ||
6650 | /* send a NIG loopback debug packet */ | |
6651 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
6652 | { | |
a2fbb9ea | 6653 | u32 wb_write[3]; |
a2fbb9ea ET |
6654 | |
6655 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
6656 | wb_write[0] = 0x55555555; |
6657 | wb_write[1] = 0x55555555; | |
34f80b04 | 6658 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 6659 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6660 | |
6661 | /* NON-IP protocol */ | |
a2fbb9ea ET |
6662 | wb_write[0] = 0x09000000; |
6663 | wb_write[1] = 0x55555555; | |
34f80b04 | 6664 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 6665 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6666 | } |
6667 | ||
6668 | /* some of the internal memories | |
6669 | * are not directly readable from the driver | |
6670 | * to test them we send debug packets | |
6671 | */ | |
6672 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
6673 | { | |
6674 | int factor; | |
6675 | int count, i; | |
6676 | u32 val = 0; | |
6677 | ||
ad8d3948 | 6678 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 6679 | factor = 120; |
ad8d3948 EG |
6680 | else if (CHIP_REV_IS_EMUL(bp)) |
6681 | factor = 200; | |
6682 | else | |
a2fbb9ea | 6683 | factor = 1; |
a2fbb9ea | 6684 | |
a2fbb9ea ET |
6685 | /* Disable inputs of parser neighbor blocks */ |
6686 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6687 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6688 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6689 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6690 | |
6691 | /* Write 0 to parser credits for CFC search request */ | |
6692 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6693 | ||
6694 | /* send Ethernet packet */ | |
6695 | bnx2x_lb_pckt(bp); | |
6696 | ||
6697 | /* TODO do i reset NIG statistic? */ | |
6698 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6699 | count = 1000 * factor; | |
6700 | while (count) { | |
34f80b04 | 6701 | |
a2fbb9ea ET |
6702 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6703 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6704 | if (val == 0x10) |
6705 | break; | |
6706 | ||
639d65b8 | 6707 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6708 | count--; |
6709 | } | |
6710 | if (val != 0x10) { | |
6711 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6712 | return -1; | |
6713 | } | |
6714 | ||
6715 | /* Wait until PRS register shows 1 packet */ | |
6716 | count = 1000 * factor; | |
6717 | while (count) { | |
6718 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
6719 | if (val == 1) |
6720 | break; | |
6721 | ||
639d65b8 | 6722 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6723 | count--; |
6724 | } | |
6725 | if (val != 0x1) { | |
6726 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6727 | return -2; | |
6728 | } | |
6729 | ||
6730 | /* Reset and init BRB, PRS */ | |
34f80b04 | 6731 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 6732 | msleep(50); |
34f80b04 | 6733 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 6734 | msleep(50); |
619c5cb6 VZ |
6735 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6736 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
6737 | |
6738 | DP(NETIF_MSG_HW, "part2\n"); | |
6739 | ||
6740 | /* Disable inputs of parser neighbor blocks */ | |
6741 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6742 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6743 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6744 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6745 | |
6746 | /* Write 0 to parser credits for CFC search request */ | |
6747 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6748 | ||
6749 | /* send 10 Ethernet packets */ | |
6750 | for (i = 0; i < 10; i++) | |
6751 | bnx2x_lb_pckt(bp); | |
6752 | ||
6753 | /* Wait until NIG register shows 10 + 1 | |
6754 | packets of size 11*0x10 = 0xb0 */ | |
6755 | count = 1000 * factor; | |
6756 | while (count) { | |
34f80b04 | 6757 | |
a2fbb9ea ET |
6758 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6759 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6760 | if (val == 0xb0) |
6761 | break; | |
6762 | ||
639d65b8 | 6763 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6764 | count--; |
6765 | } | |
6766 | if (val != 0xb0) { | |
6767 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6768 | return -3; | |
6769 | } | |
6770 | ||
6771 | /* Wait until PRS register shows 2 packets */ | |
6772 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6773 | if (val != 2) | |
6774 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6775 | ||
6776 | /* Write 1 to parser credits for CFC search request */ | |
6777 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
6778 | ||
6779 | /* Wait until PRS register shows 3 packets */ | |
6780 | msleep(10 * factor); | |
6781 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6782 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6783 | if (val != 3) | |
6784 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6785 | ||
6786 | /* clear NIG EOP FIFO */ | |
6787 | for (i = 0; i < 11; i++) | |
6788 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
6789 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
6790 | if (val != 1) { | |
6791 | BNX2X_ERR("clear of NIG failed\n"); | |
6792 | return -4; | |
6793 | } | |
6794 | ||
6795 | /* Reset and init BRB, PRS, NIG */ | |
6796 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
6797 | msleep(50); | |
6798 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
6799 | msleep(50); | |
619c5cb6 VZ |
6800 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6801 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
55c11941 MS |
6802 | if (!CNIC_SUPPORT(bp)) |
6803 | /* set NIC mode */ | |
6804 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
a2fbb9ea ET |
6805 | |
6806 | /* Enable inputs of parser neighbor blocks */ | |
6807 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
6808 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
6809 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 6810 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
6811 | |
6812 | DP(NETIF_MSG_HW, "done\n"); | |
6813 | ||
6814 | return 0; /* OK */ | |
6815 | } | |
6816 | ||
4a33bc03 | 6817 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea | 6818 | { |
b343d002 YM |
6819 | u32 val; |
6820 | ||
a2fbb9ea | 6821 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); |
619c5cb6 | 6822 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6823 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
6824 | else | |
6825 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
6826 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
6827 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
6828 | /* |
6829 | * mask read length error interrupts in brb for parser | |
6830 | * (parsing unit and 'checksum and crc' unit) | |
6831 | * these errors are legal (PU reads fixed length and CAC can cause | |
6832 | * read length error on truncated packets) | |
6833 | */ | |
6834 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
6835 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
6836 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
6837 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
6838 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
6839 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
6840 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
6841 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6842 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
6843 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
6844 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
6845 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
6846 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6847 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
6848 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
6849 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
6850 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
6851 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
6852 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 6853 | |
b343d002 YM |
6854 | val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
6855 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | | |
6856 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; | |
6857 | if (!CHIP_IS_E1x(bp)) | |
6858 | val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | | |
6859 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; | |
6860 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); | |
6861 | ||
a2fbb9ea ET |
6862 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
6863 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
6864 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 6865 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
6866 | |
6867 | if (!CHIP_IS_E1x(bp)) | |
6868 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
6869 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
6870 | ||
a2fbb9ea ET |
6871 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
6872 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 6873 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 6874 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
6875 | } |
6876 | ||
81f75bbf EG |
6877 | static void bnx2x_reset_common(struct bnx2x *bp) |
6878 | { | |
619c5cb6 VZ |
6879 | u32 val = 0x1400; |
6880 | ||
81f75bbf EG |
6881 | /* reset_common */ |
6882 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6883 | 0xd3ffff7f); | |
619c5cb6 VZ |
6884 | |
6885 | if (CHIP_IS_E3(bp)) { | |
6886 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6887 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6888 | } | |
6889 | ||
6890 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
6891 | } | |
6892 | ||
6893 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
6894 | { | |
6895 | bp->dmae_ready = 0; | |
6896 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
6897 | } |
6898 | ||
573f2035 EG |
6899 | static void bnx2x_init_pxp(struct bnx2x *bp) |
6900 | { | |
6901 | u16 devctl; | |
6902 | int r_order, w_order; | |
6903 | ||
2a80eebc | 6904 | pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
6905 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
6906 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
6907 | if (bp->mrrs == -1) | |
6908 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
6909 | else { | |
6910 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
6911 | r_order = bp->mrrs; | |
6912 | } | |
6913 | ||
6914 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
6915 | } | |
fd4ef40d EG |
6916 | |
6917 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
6918 | { | |
2145a920 | 6919 | int is_required; |
fd4ef40d | 6920 | u32 val; |
2145a920 | 6921 | int port; |
fd4ef40d | 6922 | |
2145a920 VZ |
6923 | if (BP_NOMCP(bp)) |
6924 | return; | |
6925 | ||
6926 | is_required = 0; | |
fd4ef40d EG |
6927 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
6928 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
6929 | ||
6930 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
6931 | is_required = 1; | |
6932 | ||
6933 | /* | |
6934 | * The fan failure mechanism is usually related to the PHY type since | |
6935 | * the power consumption of the board is affected by the PHY. Currently, | |
6936 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
6937 | */ | |
6938 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
6939 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 6940 | is_required |= |
d90d96ba YR |
6941 | bnx2x_fan_failure_det_req( |
6942 | bp, | |
6943 | bp->common.shmem_base, | |
a22f0788 | 6944 | bp->common.shmem2_base, |
d90d96ba | 6945 | port); |
fd4ef40d EG |
6946 | } |
6947 | ||
6948 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
6949 | ||
6950 | if (is_required == 0) | |
6951 | return; | |
6952 | ||
6953 | /* Fan failure is indicated by SPIO 5 */ | |
d6d99a3f | 6954 | bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); |
fd4ef40d EG |
6955 | |
6956 | /* set to active low mode */ | |
6957 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
d6d99a3f | 6958 | val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
6959 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
6960 | ||
6961 | /* enable interrupt to signal the IGU */ | |
6962 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 6963 | val |= MISC_SPIO_SPIO5; |
fd4ef40d EG |
6964 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); |
6965 | } | |
6966 | ||
c9ee9206 | 6967 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
6968 | { |
6969 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
6970 | val &= ~IGU_PF_CONF_FUNC_EN; | |
6971 | ||
6972 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
6973 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6974 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
6975 | } | |
6976 | ||
1191cb83 | 6977 | static void bnx2x__common_init_phy(struct bnx2x *bp) |
619c5cb6 VZ |
6978 | { |
6979 | u32 shmem_base[2], shmem2_base[2]; | |
b884d95b YR |
6980 | /* Avoid common init in case MFW supports LFA */ |
6981 | if (SHMEM2_RD(bp, size) > | |
6982 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
6983 | return; | |
619c5cb6 VZ |
6984 | shmem_base[0] = bp->common.shmem_base; |
6985 | shmem2_base[0] = bp->common.shmem2_base; | |
6986 | if (!CHIP_IS_E1x(bp)) { | |
6987 | shmem_base[1] = | |
6988 | SHMEM2_RD(bp, other_shmem_base_addr); | |
6989 | shmem2_base[1] = | |
6990 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
6991 | } | |
6992 | bnx2x_acquire_phy_lock(bp); | |
6993 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
6994 | bp->common.chip_id); | |
6995 | bnx2x_release_phy_lock(bp); | |
6996 | } | |
6997 | ||
04860eb7 MC |
6998 | static void bnx2x_config_endianity(struct bnx2x *bp, u32 val) |
6999 | { | |
7000 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); | |
7001 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); | |
7002 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); | |
7003 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); | |
7004 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); | |
7005 | ||
7006 | /* make sure this value is 0 */ | |
7007 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
7008 | ||
7009 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); | |
7010 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); | |
7011 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); | |
7012 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); | |
7013 | } | |
7014 | ||
7015 | static void bnx2x_set_endianity(struct bnx2x *bp) | |
7016 | { | |
7017 | #ifdef __BIG_ENDIAN | |
7018 | bnx2x_config_endianity(bp, 1); | |
7019 | #else | |
7020 | bnx2x_config_endianity(bp, 0); | |
7021 | #endif | |
7022 | } | |
7023 | ||
7024 | static void bnx2x_reset_endianity(struct bnx2x *bp) | |
7025 | { | |
7026 | bnx2x_config_endianity(bp, 0); | |
7027 | } | |
7028 | ||
619c5cb6 VZ |
7029 | /** |
7030 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
7031 | * | |
7032 | * @bp: driver handle | |
7033 | */ | |
7034 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 7035 | { |
619c5cb6 | 7036 | u32 val; |
a2fbb9ea | 7037 | |
51c1a580 | 7038 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 7039 | |
2031bd3a | 7040 | /* |
2de67439 | 7041 | * take the RESET lock to protect undi_unload flow from accessing |
2031bd3a DK |
7042 | * registers while we're resetting the chip |
7043 | */ | |
7a06a122 | 7044 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 7045 | |
81f75bbf | 7046 | bnx2x_reset_common(bp); |
34f80b04 | 7047 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 7048 | |
619c5cb6 VZ |
7049 | val = 0xfffc; |
7050 | if (CHIP_IS_E3(bp)) { | |
7051 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
7052 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
7053 | } | |
7054 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
7055 | ||
7a06a122 | 7056 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 7057 | |
619c5cb6 | 7058 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 7059 | |
619c5cb6 VZ |
7060 | if (!CHIP_IS_E1x(bp)) { |
7061 | u8 abs_func_id; | |
f2e0899f DK |
7062 | |
7063 | /** | |
7064 | * 4-port mode or 2-port mode we need to turn of master-enable | |
7065 | * for everyone, after that, turn it back on for self. | |
7066 | * so, we disregard multi-function or not, and always disable | |
7067 | * for all functions on the given path, this means 0,2,4,6 for | |
7068 | * path 0 and 1,3,5,7 for path 1 | |
7069 | */ | |
619c5cb6 VZ |
7070 | for (abs_func_id = BP_PATH(bp); |
7071 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
7072 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
7073 | REG_WR(bp, |
7074 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
7075 | 1); | |
7076 | continue; | |
7077 | } | |
7078 | ||
619c5cb6 | 7079 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
7080 | /* clear pf enable */ |
7081 | bnx2x_pf_disable(bp); | |
7082 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
7083 | } | |
7084 | } | |
a2fbb9ea | 7085 | |
619c5cb6 | 7086 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
7087 | if (CHIP_IS_E1(bp)) { |
7088 | /* enable HW interrupt from PXP on USDM overflow | |
7089 | bit 16 on INT_MASK_0 */ | |
7090 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
7091 | } | |
a2fbb9ea | 7092 | |
619c5cb6 | 7093 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 7094 | bnx2x_init_pxp(bp); |
04860eb7 | 7095 | bnx2x_set_endianity(bp); |
523224a3 DK |
7096 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
7097 | ||
34f80b04 EG |
7098 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
7099 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 7100 | |
34f80b04 EG |
7101 | /* let the HW do it's magic ... */ |
7102 | msleep(100); | |
7103 | /* finish PXP init */ | |
7104 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
7105 | if (val != 1) { | |
7106 | BNX2X_ERR("PXP2 CFG failed\n"); | |
7107 | return -EBUSY; | |
7108 | } | |
7109 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
7110 | if (val != 1) { | |
7111 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
7112 | return -EBUSY; | |
7113 | } | |
a2fbb9ea | 7114 | |
f2e0899f DK |
7115 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
7116 | * have entries with value "0" and valid bit on. | |
7117 | * This needs to be done by the first PF that is loaded in a path | |
7118 | * (i.e. common phase) | |
7119 | */ | |
619c5cb6 VZ |
7120 | if (!CHIP_IS_E1x(bp)) { |
7121 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
7122 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
7123 | * This occurs when a different function (func2,3) is being marked | |
7124 | * as "scan-off". Real-life scenario for example: if a driver is being | |
7125 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
7126 | * the ilt, translate to a logical address and send a request to read/write. | |
7127 | * Since the ilt for the function that is down is not valid, this will cause | |
7128 | * a translation error which is unrecoverable. | |
7129 | * The Workaround is intended to make sure that when this happens nothing fatal | |
7130 | * will occur. The workaround: | |
7131 | * 1. First PF driver which loads on a path will: | |
7132 | * a. After taking the chip out of reset, by using pretend, | |
7133 | * it will write "0" to the following registers of | |
7134 | * the other vnics. | |
7135 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
7136 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
7137 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
7138 | * And for itself it will write '1' to | |
7139 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
7140 | * dmae-operations (writing to pram for example.) | |
7141 | * note: can be done for only function 6,7 but cleaner this | |
7142 | * way. | |
7143 | * b. Write zero+valid to the entire ILT. | |
7144 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
7145 | * VNIC3 (of that port). The range allocated will be the | |
7146 | * entire ILT. This is needed to prevent ILT range error. | |
7147 | * 2. Any PF driver load flow: | |
7148 | * a. ILT update with the physical addresses of the allocated | |
7149 | * logical pages. | |
7150 | * b. Wait 20msec. - note that this timeout is needed to make | |
7151 | * sure there are no requests in one of the PXP internal | |
7152 | * queues with "old" ILT addresses. | |
7153 | * c. PF enable in the PGLC. | |
7154 | * d. Clear the was_error of the PF in the PGLC. (could have | |
2de67439 | 7155 | * occurred while driver was down) |
619c5cb6 VZ |
7156 | * e. PF enable in the CFC (WEAK + STRONG) |
7157 | * f. Timers scan enable | |
7158 | * 3. PF driver unload flow: | |
7159 | * a. Clear the Timers scan_en. | |
7160 | * b. Polling for scan_on=0 for that PF. | |
7161 | * c. Clear the PF enable bit in the PXP. | |
7162 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
7163 | * e. Write zero+valid to all ILT entries (The valid bit must | |
7164 | * stay set) | |
7165 | * f. If this is VNIC 3 of a port then also init | |
7166 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
16a5fd92 | 7167 | * to the last entry in the ILT. |
619c5cb6 VZ |
7168 | * |
7169 | * Notes: | |
7170 | * Currently the PF error in the PGLC is non recoverable. | |
7171 | * In the future the there will be a recovery routine for this error. | |
7172 | * Currently attention is masked. | |
7173 | * Having an MCP lock on the load/unload process does not guarantee that | |
7174 | * there is no Timer disable during Func6/7 enable. This is because the | |
7175 | * Timers scan is currently being cleared by the MCP on FLR. | |
7176 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
7177 | * there is error before clearing it. But the flow above is simpler and | |
7178 | * more general. | |
7179 | * All ILT entries are written by zero+valid and not just PF6/7 | |
7180 | * ILT entries since in the future the ILT entries allocation for | |
7181 | * PF-s might be dynamic. | |
7182 | */ | |
f2e0899f DK |
7183 | struct ilt_client_info ilt_cli; |
7184 | struct bnx2x_ilt ilt; | |
7185 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
7186 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
7187 | ||
b595076a | 7188 | /* initialize dummy TM client */ |
f2e0899f DK |
7189 | ilt_cli.start = 0; |
7190 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
7191 | ilt_cli.client_num = ILT_CLIENT_TM; | |
7192 | ||
7193 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
7194 | * Step 2: set the timers first/last ilt entry to point | |
7195 | * to the entire range to prevent ILT range error for 3rd/4th | |
2de67439 | 7196 | * vnic (this code assumes existence of the vnic) |
f2e0899f DK |
7197 | * |
7198 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
7199 | * with dummy TM client | |
7200 | * | |
7201 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
7202 | * and his brother are split registers | |
7203 | */ | |
7204 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
7205 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
7206 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
7207 | ||
7208 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
7209 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
7210 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
7211 | } | |
7212 | ||
34f80b04 EG |
7213 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
7214 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 7215 | |
619c5cb6 | 7216 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7217 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
7218 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 7219 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 7220 | |
619c5cb6 | 7221 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
7222 | |
7223 | /* let the HW do it's magic ... */ | |
7224 | do { | |
7225 | msleep(200); | |
7226 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
7227 | } while (factor-- && (val != 1)); | |
7228 | ||
7229 | if (val != 1) { | |
7230 | BNX2X_ERR("ATC_INIT failed\n"); | |
7231 | return -EBUSY; | |
7232 | } | |
7233 | } | |
7234 | ||
619c5cb6 | 7235 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 7236 | |
b56e9670 AE |
7237 | bnx2x_iov_init_dmae(bp); |
7238 | ||
34f80b04 EG |
7239 | /* clean the DMAE memory */ |
7240 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
7241 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
7242 | ||
7243 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
7244 | ||
7245 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
7246 | ||
7247 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 7248 | |
619c5cb6 | 7249 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 7250 | |
34f80b04 EG |
7251 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
7252 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
7253 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
7254 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
7255 | ||
619c5cb6 | 7256 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 7257 | |
523224a3 DK |
7258 | /* QM queues pointers table */ |
7259 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
7260 | ||
34f80b04 EG |
7261 | /* soft reset pulse */ |
7262 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
7263 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 7264 | |
55c11941 MS |
7265 | if (CNIC_SUPPORT(bp)) |
7266 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); | |
a2fbb9ea | 7267 | |
619c5cb6 | 7268 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
b9871bcf | 7269 | |
619c5cb6 | 7270 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
7271 | /* enable hw interrupt from doorbell Q */ |
7272 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 7273 | |
619c5cb6 | 7274 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 7275 | |
619c5cb6 | 7276 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 7277 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 7278 | |
f2e0899f | 7279 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 7280 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 7281 | |
a3348722 BW |
7282 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { |
7283 | if (IS_MF_AFEX(bp)) { | |
7284 | /* configure that VNTag and VLAN headers must be | |
7285 | * received in afex mode | |
7286 | */ | |
7287 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); | |
7288 | REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); | |
7289 | REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); | |
7290 | REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); | |
7291 | REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); | |
7292 | } else { | |
7293 | /* Bit-map indicating which L2 hdrs may appear | |
7294 | * after the basic Ethernet header | |
7295 | */ | |
7296 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
7297 | bp->path_has_ovlan ? 7 : 6); | |
7298 | } | |
7299 | } | |
a2fbb9ea | 7300 | |
619c5cb6 VZ |
7301 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
7302 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
7303 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
7304 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 7305 | |
619c5cb6 VZ |
7306 | if (!CHIP_IS_E1x(bp)) { |
7307 | /* reset VFC memories */ | |
7308 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
7309 | VFC_MEMORIES_RST_REG_CAM_RST | | |
7310 | VFC_MEMORIES_RST_REG_RAM_RST); | |
7311 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
7312 | VFC_MEMORIES_RST_REG_CAM_RST | | |
7313 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 7314 | |
619c5cb6 VZ |
7315 | msleep(20); |
7316 | } | |
a2fbb9ea | 7317 | |
619c5cb6 VZ |
7318 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
7319 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
7320 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
7321 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 7322 | |
34f80b04 EG |
7323 | /* sync semi rtc */ |
7324 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
7325 | 0x80000000); | |
7326 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
7327 | 0x80000000); | |
a2fbb9ea | 7328 | |
619c5cb6 VZ |
7329 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
7330 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
7331 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 7332 | |
a3348722 BW |
7333 | if (!CHIP_IS_E1x(bp)) { |
7334 | if (IS_MF_AFEX(bp)) { | |
7335 | /* configure that VNTag and VLAN headers must be | |
7336 | * sent in afex mode | |
7337 | */ | |
7338 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); | |
7339 | REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); | |
7340 | REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); | |
7341 | REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); | |
7342 | REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); | |
7343 | } else { | |
7344 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
7345 | bp->path_has_ovlan ? 7 : 6); | |
7346 | } | |
7347 | } | |
f2e0899f | 7348 | |
34f80b04 | 7349 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 7350 | |
619c5cb6 VZ |
7351 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
7352 | ||
55c11941 MS |
7353 | if (CNIC_SUPPORT(bp)) { |
7354 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
7355 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
7356 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
7357 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
7358 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
7359 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
7360 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
7361 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
7362 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
7363 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
7364 | } | |
34f80b04 | 7365 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 7366 | |
34f80b04 EG |
7367 | if (sizeof(union cdu_context) != 1024) |
7368 | /* we currently assume that a context is 1024 bytes */ | |
51c1a580 MS |
7369 | dev_alert(&bp->pdev->dev, |
7370 | "please adjust the size of cdu_context(%ld)\n", | |
7371 | (long)sizeof(union cdu_context)); | |
a2fbb9ea | 7372 | |
619c5cb6 | 7373 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
7374 | val = (4 << 24) + (0 << 12) + 1024; |
7375 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 7376 | |
619c5cb6 | 7377 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 7378 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
7379 | /* enable context validation interrupt from CFC */ |
7380 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
7381 | ||
7382 | /* set the thresholds to prevent CFC/CDU race */ | |
7383 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 7384 | |
619c5cb6 | 7385 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 7386 | |
619c5cb6 | 7387 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
7388 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
7389 | ||
619c5cb6 VZ |
7390 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
7391 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 7392 | |
34f80b04 EG |
7393 | /* Reset PCIE errors for debug */ |
7394 | REG_WR(bp, 0x2814, 0xffffffff); | |
7395 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 7396 | |
619c5cb6 | 7397 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7398 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
7399 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
7400 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
7401 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
7402 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
7403 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
7404 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
7405 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
7406 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
7407 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
7408 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
7409 | } | |
7410 | ||
619c5cb6 | 7411 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 7412 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
7413 | /* in E3 this done in per-port section */ |
7414 | if (!CHIP_IS_E3(bp)) | |
7415 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 7416 | } |
619c5cb6 VZ |
7417 | if (CHIP_IS_E1H(bp)) |
7418 | /* not applicable for E2 (and above ...) */ | |
7419 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
7420 | |
7421 | if (CHIP_REV_IS_SLOW(bp)) | |
7422 | msleep(200); | |
7423 | ||
7424 | /* finish CFC init */ | |
7425 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
7426 | if (val != 1) { | |
7427 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
7428 | return -EBUSY; | |
7429 | } | |
7430 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
7431 | if (val != 1) { | |
7432 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
7433 | return -EBUSY; | |
7434 | } | |
7435 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
7436 | if (val != 1) { | |
7437 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
7438 | return -EBUSY; | |
7439 | } | |
7440 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 7441 | |
f2e0899f DK |
7442 | if (CHIP_IS_E1(bp)) { |
7443 | /* read NIG statistic | |
7444 | to see if this is our first up since powerup */ | |
7445 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
7446 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 7447 | |
f2e0899f DK |
7448 | /* do internal memory self test */ |
7449 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
7450 | BNX2X_ERR("internal mem self test failed\n"); | |
7451 | return -EBUSY; | |
7452 | } | |
34f80b04 EG |
7453 | } |
7454 | ||
fd4ef40d EG |
7455 | bnx2x_setup_fan_failure_detection(bp); |
7456 | ||
34f80b04 EG |
7457 | /* clear PXP2 attentions */ |
7458 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 7459 | |
4a33bc03 | 7460 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 7461 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 7462 | |
6bbca910 | 7463 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
7464 | if (CHIP_IS_E1x(bp)) |
7465 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
7466 | } else |
7467 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
7468 | ||
230d00eb YM |
7469 | if (SHMEM2_HAS(bp, netproc_fw_ver)) |
7470 | SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM)); | |
7471 | ||
34f80b04 EG |
7472 | return 0; |
7473 | } | |
a2fbb9ea | 7474 | |
619c5cb6 VZ |
7475 | /** |
7476 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
7477 | * | |
7478 | * @bp: driver handle | |
7479 | */ | |
7480 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
7481 | { | |
7482 | int rc = bnx2x_init_hw_common(bp); | |
7483 | ||
7484 | if (rc) | |
7485 | return rc; | |
7486 | ||
7487 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
7488 | if (!BP_NOMCP(bp)) | |
7489 | bnx2x__common_init_phy(bp); | |
7490 | ||
7491 | return 0; | |
7492 | } | |
7493 | ||
523224a3 | 7494 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
7495 | { |
7496 | int port = BP_PORT(bp); | |
619c5cb6 | 7497 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 7498 | u32 low, high; |
4293b9f5 | 7499 | u32 val, reg; |
a2fbb9ea | 7500 | |
51c1a580 | 7501 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
34f80b04 EG |
7502 | |
7503 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 7504 | |
619c5cb6 VZ |
7505 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
7506 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
7507 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 7508 | |
f2e0899f DK |
7509 | /* Timers bug workaround: disables the pf_master bit in pglue at |
7510 | * common phase, we need to enable it here before any dmae access are | |
7511 | * attempted. Therefore we manually added the enable-master to the | |
7512 | * port phase (it also happens in the function phase) | |
7513 | */ | |
619c5cb6 | 7514 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7515 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
7516 | ||
619c5cb6 VZ |
7517 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7518 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7519 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
7520 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7521 | ||
7522 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7523 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7524 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7525 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 7526 | |
523224a3 DK |
7527 | /* QM cid (connection) count */ |
7528 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 7529 | |
55c11941 MS |
7530 | if (CNIC_SUPPORT(bp)) { |
7531 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7532 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); | |
7533 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
7534 | } | |
cdaa7cb8 | 7535 | |
619c5cb6 | 7536 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f | 7537 | |
2b674047 DK |
7538 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
7539 | ||
f2e0899f | 7540 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { |
619c5cb6 VZ |
7541 | |
7542 | if (IS_MF(bp)) | |
7543 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
7544 | else if (bp->dev->mtu > 4096) { | |
7545 | if (bp->flags & ONE_PORT_FLAG) | |
7546 | low = 160; | |
7547 | else { | |
7548 | val = bp->dev->mtu; | |
7549 | /* (24*1024 + val*4)/256 */ | |
7550 | low = 96 + (val/64) + | |
7551 | ((val % 64) ? 1 : 0); | |
7552 | } | |
7553 | } else | |
7554 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
7555 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
7556 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
7557 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 7558 | } |
1c06328c | 7559 | |
619c5cb6 VZ |
7560 | if (CHIP_MODE_IS_4_PORT(bp)) |
7561 | REG_WR(bp, (BP_PORT(bp) ? | |
7562 | BRB1_REG_MAC_GUARANTIED_1 : | |
7563 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 7564 | |
619c5cb6 | 7565 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
a3348722 BW |
7566 | if (CHIP_IS_E3B0(bp)) { |
7567 | if (IS_MF_AFEX(bp)) { | |
7568 | /* configure headers for AFEX mode */ | |
7569 | REG_WR(bp, BP_PORT(bp) ? | |
7570 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7571 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); | |
7572 | REG_WR(bp, BP_PORT(bp) ? | |
7573 | PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : | |
7574 | PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); | |
7575 | REG_WR(bp, BP_PORT(bp) ? | |
7576 | PRS_REG_MUST_HAVE_HDRS_PORT_1 : | |
7577 | PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); | |
7578 | } else { | |
7579 | /* Ovlan exists only if we are in multi-function + | |
7580 | * switch-dependent mode, in switch-independent there | |
7581 | * is no ovlan headers | |
7582 | */ | |
7583 | REG_WR(bp, BP_PORT(bp) ? | |
7584 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7585 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
7586 | (bp->path_has_ovlan ? 7 : 6)); | |
7587 | } | |
7588 | } | |
356e2385 | 7589 | |
619c5cb6 VZ |
7590 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
7591 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7592 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7593 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 7594 | |
619c5cb6 VZ |
7595 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
7596 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7597 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7598 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 7599 | |
619c5cb6 VZ |
7600 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
7601 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 7602 | |
619c5cb6 VZ |
7603 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
7604 | ||
7605 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
7606 | /* configure PBF to work without PAUSE mtu 9000 */ |
7607 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 7608 | |
f2e0899f DK |
7609 | /* update threshold */ |
7610 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
7611 | /* update init credit */ | |
7612 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 7613 | |
f2e0899f DK |
7614 | /* probe changes */ |
7615 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
7616 | udelay(50); | |
7617 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
7618 | } | |
a2fbb9ea | 7619 | |
55c11941 MS |
7620 | if (CNIC_SUPPORT(bp)) |
7621 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7622 | ||
619c5cb6 VZ |
7623 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
7624 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
7625 | |
7626 | if (CHIP_IS_E1(bp)) { | |
7627 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7628 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7629 | } | |
619c5cb6 | 7630 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 7631 | |
619c5cb6 | 7632 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7633 | |
619c5cb6 | 7634 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 | 7635 | /* init aeu_mask_attn_func_0/1: |
16a5fd92 YM |
7636 | * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use |
7637 | * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF | |
34f80b04 | 7638 | * bits 4-7 are used for "per vn group attention" */ |
e4901dde VZ |
7639 | val = IS_MF(bp) ? 0xF7 : 0x7; |
7640 | /* Enable DCBX attention for all but E1 */ | |
7641 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
7642 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 7643 | |
4293b9f5 DK |
7644 | /* SCPAD_PARITY should NOT trigger close the gates */ |
7645 | reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0; | |
7646 | REG_WR(bp, reg, | |
7647 | REG_RD(bp, reg) & | |
7648 | ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); | |
7649 | ||
7650 | reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0; | |
7651 | REG_WR(bp, reg, | |
7652 | REG_RD(bp, reg) & | |
7653 | ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); | |
7654 | ||
619c5cb6 VZ |
7655 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
7656 | ||
7657 | if (!CHIP_IS_E1x(bp)) { | |
7658 | /* Bit-map indicating which L2 hdrs may appear after the | |
7659 | * basic Ethernet header | |
7660 | */ | |
a3348722 BW |
7661 | if (IS_MF_AFEX(bp)) |
7662 | REG_WR(bp, BP_PORT(bp) ? | |
7663 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7664 | NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); | |
7665 | else | |
7666 | REG_WR(bp, BP_PORT(bp) ? | |
7667 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7668 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
7669 | IS_MF_SD(bp) ? 7 : 6); | |
619c5cb6 VZ |
7670 | |
7671 | if (CHIP_IS_E3(bp)) | |
7672 | REG_WR(bp, BP_PORT(bp) ? | |
7673 | NIG_REG_LLH1_MF_MODE : | |
7674 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
7675 | } | |
7676 | if (!CHIP_IS_E3(bp)) | |
7677 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 7678 | |
f2e0899f | 7679 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 7680 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 7681 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 7682 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 7683 | |
619c5cb6 | 7684 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7685 | val = 0; |
7686 | switch (bp->mf_mode) { | |
7687 | case MULTI_FUNCTION_SD: | |
7688 | val = 1; | |
7689 | break; | |
7690 | case MULTI_FUNCTION_SI: | |
a3348722 | 7691 | case MULTI_FUNCTION_AFEX: |
f2e0899f DK |
7692 | val = 2; |
7693 | break; | |
7694 | } | |
7695 | ||
7696 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
7697 | NIG_REG_LLH0_CLS_TYPE), val); | |
7698 | } | |
1c06328c EG |
7699 | { |
7700 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
7701 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
7702 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
7703 | } | |
34f80b04 EG |
7704 | } |
7705 | ||
619c5cb6 VZ |
7706 | /* If SPIO5 is set to generate interrupts, enable it for this port */ |
7707 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 7708 | if (val & MISC_SPIO_SPIO5) { |
4d295db0 EG |
7709 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
7710 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
7711 | val = REG_RD(bp, reg_addr); | |
f1410647 | 7712 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 7713 | REG_WR(bp, reg_addr, val); |
f1410647 | 7714 | } |
a2fbb9ea | 7715 | |
34f80b04 EG |
7716 | return 0; |
7717 | } | |
7718 | ||
34f80b04 EG |
7719 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
7720 | { | |
7721 | int reg; | |
32d68de1 | 7722 | u32 wb_write[2]; |
34f80b04 | 7723 | |
f2e0899f | 7724 | if (CHIP_IS_E1(bp)) |
34f80b04 | 7725 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
7726 | else |
7727 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 | 7728 | |
32d68de1 YM |
7729 | wb_write[0] = ONCHIP_ADDR1(addr); |
7730 | wb_write[1] = ONCHIP_ADDR2(addr); | |
7731 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
34f80b04 EG |
7732 | } |
7733 | ||
b56e9670 | 7734 | void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) |
1191cb83 ED |
7735 | { |
7736 | u32 data, ctl, cnt = 100; | |
7737 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
7738 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
7739 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
7740 | u32 sb_bit = 1 << (idu_sb_id%32); | |
b56e9670 | 7741 | u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; |
1191cb83 ED |
7742 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; |
7743 | ||
7744 | /* Not supported in BC mode */ | |
7745 | if (CHIP_INT_MODE_IS_BC(bp)) | |
7746 | return; | |
7747 | ||
7748 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
7749 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
7750 | IGU_REGULAR_CLEANUP_SET | | |
7751 | IGU_REGULAR_BCLEANUP; | |
7752 | ||
7753 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
7754 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
7755 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
7756 | ||
7757 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7758 | data, igu_addr_data); | |
7759 | REG_WR(bp, igu_addr_data, data); | |
7760 | mmiowb(); | |
7761 | barrier(); | |
7762 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7763 | ctl, igu_addr_ctl); | |
7764 | REG_WR(bp, igu_addr_ctl, ctl); | |
7765 | mmiowb(); | |
7766 | barrier(); | |
7767 | ||
7768 | /* wait for clean up to finish */ | |
7769 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
7770 | msleep(20); | |
7771 | ||
1191cb83 ED |
7772 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { |
7773 | DP(NETIF_MSG_HW, | |
7774 | "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
7775 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
7776 | } | |
7777 | } | |
7778 | ||
7779 | static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) | |
f2e0899f | 7780 | { |
619c5cb6 | 7781 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
7782 | } |
7783 | ||
1191cb83 | 7784 | static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) |
f2e0899f DK |
7785 | { |
7786 | u32 i, base = FUNC_ILT_BASE(func); | |
7787 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
7788 | bnx2x_ilt_wr(bp, i, 0); | |
7789 | } | |
7790 | ||
910cc727 | 7791 | static void bnx2x_init_searcher(struct bnx2x *bp) |
55c11941 MS |
7792 | { |
7793 | int port = BP_PORT(bp); | |
7794 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
7795 | /* T1 hash bits value determines the T1 number of entries */ | |
7796 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
7797 | } | |
7798 | ||
7799 | static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) | |
7800 | { | |
7801 | int rc; | |
7802 | struct bnx2x_func_state_params func_params = {NULL}; | |
7803 | struct bnx2x_func_switch_update_params *switch_update_params = | |
7804 | &func_params.params.switch_update; | |
7805 | ||
7806 | /* Prepare parameters for function state transitions */ | |
7807 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7808 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
7809 | ||
7810 | func_params.f_obj = &bp->func_obj; | |
7811 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
7812 | ||
7813 | /* Function parameters */ | |
e42780b6 DK |
7814 | __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, |
7815 | &switch_update_params->changes); | |
7816 | if (suspend) | |
7817 | __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND, | |
7818 | &switch_update_params->changes); | |
55c11941 MS |
7819 | |
7820 | rc = bnx2x_func_state_change(bp, &func_params); | |
7821 | ||
7822 | return rc; | |
7823 | } | |
7824 | ||
910cc727 | 7825 | static int bnx2x_reset_nic_mode(struct bnx2x *bp) |
55c11941 MS |
7826 | { |
7827 | int rc, i, port = BP_PORT(bp); | |
7828 | int vlan_en = 0, mac_en[NUM_MACS]; | |
7829 | ||
55c11941 MS |
7830 | /* Close input from network */ |
7831 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7832 | bnx2x_set_rx_filter(&bp->link_params, 0); | |
7833 | } else { | |
7834 | vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7835 | NIG_REG_LLH0_FUNC_EN); | |
7836 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7837 | NIG_REG_LLH0_FUNC_EN, 0); | |
7838 | for (i = 0; i < NUM_MACS; i++) { | |
7839 | mac_en[i] = REG_RD(bp, port ? | |
7840 | (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7841 | 4 * i) : | |
7842 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + | |
7843 | 4 * i)); | |
7844 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7845 | 4 * i) : | |
7846 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); | |
7847 | } | |
7848 | } | |
7849 | ||
7850 | /* Close BMC to host */ | |
7851 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7852 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); | |
7853 | ||
7854 | /* Suspend Tx switching to the PF. Completion of this ramrod | |
7855 | * further guarantees that all the packets of that PF / child | |
7856 | * VFs in BRB were processed by the Parser, so it is safe to | |
7857 | * change the NIC_MODE register. | |
7858 | */ | |
7859 | rc = bnx2x_func_switch_update(bp, 1); | |
7860 | if (rc) { | |
7861 | BNX2X_ERR("Can't suspend tx-switching!\n"); | |
7862 | return rc; | |
7863 | } | |
7864 | ||
7865 | /* Change NIC_MODE register */ | |
7866 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7867 | ||
7868 | /* Open input from network */ | |
7869 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7870 | bnx2x_set_rx_filter(&bp->link_params, 1); | |
7871 | } else { | |
7872 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7873 | NIG_REG_LLH0_FUNC_EN, vlan_en); | |
7874 | for (i = 0; i < NUM_MACS; i++) { | |
7875 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7876 | 4 * i) : | |
7877 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), | |
7878 | mac_en[i]); | |
7879 | } | |
7880 | } | |
7881 | ||
7882 | /* Enable BMC to host */ | |
7883 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7884 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); | |
7885 | ||
7886 | /* Resume Tx switching to the PF */ | |
7887 | rc = bnx2x_func_switch_update(bp, 0); | |
7888 | if (rc) { | |
7889 | BNX2X_ERR("Can't resume tx-switching!\n"); | |
7890 | return rc; | |
7891 | } | |
7892 | ||
7893 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7894 | return 0; | |
7895 | } | |
7896 | ||
7897 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp) | |
7898 | { | |
7899 | int rc; | |
7900 | ||
7901 | bnx2x_ilt_init_op_cnic(bp, INITOP_SET); | |
7902 | ||
7903 | if (CONFIGURE_NIC_MODE(bp)) { | |
16a5fd92 | 7904 | /* Configure searcher as part of function hw init */ |
55c11941 MS |
7905 | bnx2x_init_searcher(bp); |
7906 | ||
7907 | /* Reset NIC mode */ | |
7908 | rc = bnx2x_reset_nic_mode(bp); | |
7909 | if (rc) | |
7910 | BNX2X_ERR("Can't change NIC mode!\n"); | |
7911 | return rc; | |
7912 | } | |
7913 | ||
7914 | return 0; | |
7915 | } | |
7916 | ||
da254fbc YM |
7917 | /* previous driver DMAE transaction may have occurred when pre-boot stage ended |
7918 | * and boot began, or when kdump kernel was loaded. Either case would invalidate | |
7919 | * the addresses of the transaction, resulting in was-error bit set in the pci | |
7920 | * causing all hw-to-host pcie transactions to timeout. If this happened we want | |
7921 | * to clear the interrupt which detected this from the pglueb and the was done | |
7922 | * bit | |
7923 | */ | |
7924 | static void bnx2x_clean_pglue_errors(struct bnx2x *bp) | |
7925 | { | |
7926 | if (!CHIP_IS_E1x(bp)) | |
7927 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, | |
7928 | 1 << BP_ABS_FUNC(bp)); | |
7929 | } | |
7930 | ||
523224a3 | 7931 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
7932 | { |
7933 | int port = BP_PORT(bp); | |
7934 | int func = BP_FUNC(bp); | |
619c5cb6 | 7935 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
7936 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
7937 | u16 cdu_ilt_start; | |
8badd27a | 7938 | u32 addr, val; |
f4a66897 | 7939 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
89db4ad8 | 7940 | int i, main_mem_width, rc; |
34f80b04 | 7941 | |
51c1a580 | 7942 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
34f80b04 | 7943 | |
619c5cb6 | 7944 | /* FLR cleanup - hmmm */ |
89db4ad8 AE |
7945 | if (!CHIP_IS_E1x(bp)) { |
7946 | rc = bnx2x_pf_flr_clnup(bp); | |
04c46736 YM |
7947 | if (rc) { |
7948 | bnx2x_fw_dump(bp); | |
89db4ad8 | 7949 | return rc; |
04c46736 | 7950 | } |
89db4ad8 | 7951 | } |
619c5cb6 | 7952 | |
8badd27a | 7953 | /* set MSI reconfigure capability */ |
f2e0899f DK |
7954 | if (bp->common.int_block == INT_BLOCK_HC) { |
7955 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
7956 | val = REG_RD(bp, addr); | |
7957 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
7958 | REG_WR(bp, addr, val); | |
7959 | } | |
8badd27a | 7960 | |
619c5cb6 VZ |
7961 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
7962 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
7963 | ||
523224a3 DK |
7964 | ilt = BP_ILT(bp); |
7965 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 7966 | |
290ca2bb AE |
7967 | if (IS_SRIOV(bp)) |
7968 | cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; | |
7969 | cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); | |
7970 | ||
7971 | /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes | |
7972 | * those of the VFs, so start line should be reset | |
7973 | */ | |
7974 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
523224a3 | 7975 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
a052997e | 7976 | ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; |
523224a3 | 7977 | ilt->lines[cdu_ilt_start + i].page_mapping = |
a052997e MS |
7978 | bp->context[i].cxt_mapping; |
7979 | ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; | |
37b091ba | 7980 | } |
290ca2bb | 7981 | |
523224a3 | 7982 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 7983 | |
55c11941 MS |
7984 | if (!CONFIGURE_NIC_MODE(bp)) { |
7985 | bnx2x_init_searcher(bp); | |
7986 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7987 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7988 | } else { | |
7989 | /* Set NIC mode */ | |
7990 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6bf07b8e | 7991 | DP(NETIF_MSG_IFUP, "NIC MODE configured\n"); |
55c11941 | 7992 | } |
37b091ba | 7993 | |
619c5cb6 | 7994 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7995 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
7996 | ||
7997 | /* Turn on a single ISR mode in IGU if driver is going to use | |
7998 | * INT#x or MSI | |
7999 | */ | |
8000 | if (!(bp->flags & USING_MSIX_FLAG)) | |
8001 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
8002 | /* | |
8003 | * Timers workaround bug: function init part. | |
8004 | * Need to wait 20msec after initializing ILT, | |
8005 | * needed to make sure there are no requests in | |
8006 | * one of the PXP internal queues with "old" ILT addresses | |
8007 | */ | |
8008 | msleep(20); | |
8009 | /* | |
8010 | * Master enable - Due to WB DMAE writes performed before this | |
8011 | * register is re-initialized as part of the regular function | |
8012 | * init | |
8013 | */ | |
8014 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
8015 | /* Enable the function in IGU */ | |
8016 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
8017 | } | |
8018 | ||
523224a3 | 8019 | bp->dmae_ready = 1; |
34f80b04 | 8020 | |
619c5cb6 | 8021 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 8022 | |
da254fbc | 8023 | bnx2x_clean_pglue_errors(bp); |
f2e0899f | 8024 | |
619c5cb6 VZ |
8025 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
8026 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
8027 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
8028 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
8029 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
8030 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
8031 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
8032 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
8033 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
8034 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
8035 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
8036 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
8037 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
8038 | ||
8039 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
8040 | REG_WR(bp, QM_REG_PF_EN, 1); |
8041 | ||
619c5cb6 VZ |
8042 | if (!CHIP_IS_E1x(bp)) { |
8043 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
8044 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
8045 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
8046 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
8047 | } | |
8048 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
8049 | ||
8050 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
8051 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
c19d65c9 | 8052 | REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ |
b56e9670 AE |
8053 | |
8054 | bnx2x_iov_init_dq(bp); | |
8055 | ||
619c5cb6 VZ |
8056 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
8057 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
8058 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
8059 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
8060 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
8061 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
8062 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
8063 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
8064 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
8065 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
8066 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
8067 | ||
619c5cb6 | 8068 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 8069 | |
619c5cb6 | 8070 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 8071 | |
619c5cb6 | 8072 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
8073 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
8074 | ||
fb3bff17 | 8075 | if (IS_MF(bp)) { |
7609647e YM |
8076 | if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) { |
8077 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); | |
8078 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, | |
8079 | bp->mf_ov); | |
8080 | } | |
34f80b04 EG |
8081 | } |
8082 | ||
619c5cb6 | 8083 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 8084 | |
34f80b04 | 8085 | /* HC init per function */ |
f2e0899f DK |
8086 | if (bp->common.int_block == INT_BLOCK_HC) { |
8087 | if (CHIP_IS_E1H(bp)) { | |
8088 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
8089 | ||
8090 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
8091 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
8092 | } | |
619c5cb6 | 8093 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
8094 | |
8095 | } else { | |
8096 | int num_segs, sb_idx, prod_offset; | |
8097 | ||
34f80b04 EG |
8098 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
8099 | ||
619c5cb6 | 8100 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8101 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
8102 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
8103 | } | |
8104 | ||
619c5cb6 | 8105 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 8106 | |
619c5cb6 | 8107 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8108 | int dsb_idx = 0; |
8109 | /** | |
8110 | * Producer memory: | |
8111 | * E2 mode: address 0-135 match to the mapping memory; | |
8112 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
8113 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
8114 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
8115 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
8116 | * 144-147 reserved. | |
8117 | * | |
8118 | * E1.5 mode - In backward compatible mode; | |
8119 | * for non default SB; each even line in the memory | |
8120 | * holds the U producer and each odd line hold | |
8121 | * the C producer. The first 128 producers are for | |
8122 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
8123 | * producers are for the DSB for each PF. | |
8124 | * Each PF has five segments: (the order inside each | |
8125 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
8126 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
8127 | * 144-147 attn prods; | |
8128 | */ | |
8129 | /* non-default-status-blocks */ | |
8130 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
8131 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
8132 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
8133 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
8134 | num_segs; | |
8135 | ||
8136 | for (i = 0; i < num_segs; i++) { | |
8137 | addr = IGU_REG_PROD_CONS_MEMORY + | |
8138 | (prod_offset + i) * 4; | |
8139 | REG_WR(bp, addr, 0); | |
8140 | } | |
8141 | /* send consumer update with value 0 */ | |
8142 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
8143 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
8144 | bnx2x_igu_clear_sb(bp, | |
8145 | bp->igu_base_sb + sb_idx); | |
8146 | } | |
8147 | ||
8148 | /* default-status-blocks */ | |
8149 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
8150 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
8151 | ||
8152 | if (CHIP_MODE_IS_4_PORT(bp)) | |
8153 | dsb_idx = BP_FUNC(bp); | |
8154 | else | |
3395a033 | 8155 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
8156 | |
8157 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
8158 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
8159 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
8160 | ||
3395a033 DK |
8161 | /* |
8162 | * igu prods come in chunks of E1HVN_MAX (4) - | |
8163 | * does not matters what is the current chip mode | |
8164 | */ | |
f2e0899f DK |
8165 | for (i = 0; i < (num_segs * E1HVN_MAX); |
8166 | i += E1HVN_MAX) { | |
8167 | addr = IGU_REG_PROD_CONS_MEMORY + | |
8168 | (prod_offset + i)*4; | |
8169 | REG_WR(bp, addr, 0); | |
8170 | } | |
8171 | /* send consumer update with 0 */ | |
8172 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
8173 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8174 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
8175 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8176 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
8177 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8178 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
8179 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8180 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
8181 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8182 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
8183 | } else { | |
8184 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8185 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
8186 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8187 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
8188 | } | |
8189 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
8190 | ||
16a5fd92 | 8191 | /* !!! These should become driver const once |
f2e0899f DK |
8192 | rf-tool supports split-68 const */ |
8193 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
8194 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
8195 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
8196 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
8197 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
8198 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
8199 | } | |
34f80b04 | 8200 | } |
34f80b04 | 8201 | |
c14423fe | 8202 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
8203 | REG_WR(bp, 0x2114, 0xffffffff); |
8204 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 8205 | |
f4a66897 VZ |
8206 | if (CHIP_IS_E1x(bp)) { |
8207 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
8208 | main_mem_base = HC_REG_MAIN_MEMORY + | |
8209 | BP_PORT(bp) * (main_mem_size * 4); | |
8210 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
8211 | main_mem_width = 8; | |
8212 | ||
8213 | val = REG_RD(bp, main_mem_prty_clr); | |
8214 | if (val) | |
51c1a580 MS |
8215 | DP(NETIF_MSG_HW, |
8216 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", | |
8217 | val); | |
f4a66897 VZ |
8218 | |
8219 | /* Clear "false" parity errors in MSI-X table */ | |
8220 | for (i = main_mem_base; | |
8221 | i < main_mem_base + main_mem_size * 4; | |
8222 | i += main_mem_width) { | |
8223 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
8224 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
8225 | i, main_mem_width / 4); | |
8226 | } | |
8227 | /* Clear HC parity attention */ | |
8228 | REG_RD(bp, main_mem_prty_clr); | |
8229 | } | |
8230 | ||
619c5cb6 VZ |
8231 | #ifdef BNX2X_STOP_ON_ERROR |
8232 | /* Enable STORMs SP logging */ | |
8233 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
8234 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8235 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
8236 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8237 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
8238 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8239 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
8240 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8241 | #endif | |
8242 | ||
b7737c9b | 8243 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 8244 | |
34f80b04 EG |
8245 | return 0; |
8246 | } | |
8247 | ||
55c11941 MS |
8248 | void bnx2x_free_mem_cnic(struct bnx2x *bp) |
8249 | { | |
8250 | bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); | |
8251 | ||
8252 | if (!CHIP_IS_E1x(bp)) | |
8253 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, | |
8254 | sizeof(struct host_hc_status_block_e2)); | |
8255 | else | |
8256 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
8257 | sizeof(struct host_hc_status_block_e1x)); | |
8258 | ||
8259 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); | |
8260 | } | |
8261 | ||
9f6c9258 | 8262 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 8263 | { |
a052997e MS |
8264 | int i; |
8265 | ||
619c5cb6 VZ |
8266 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
8267 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
8268 | ||
b4cddbd6 AE |
8269 | if (IS_VF(bp)) |
8270 | return; | |
8271 | ||
8272 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
8273 | sizeof(struct host_sp_status_block)); | |
8274 | ||
a2fbb9ea | 8275 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 8276 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 8277 | |
a052997e MS |
8278 | for (i = 0; i < L2_ILT_LINES(bp); i++) |
8279 | BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, | |
8280 | bp->context[i].size); | |
523224a3 DK |
8281 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); |
8282 | ||
8283 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 8284 | |
7a9b2557 | 8285 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 8286 | |
523224a3 DK |
8287 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
8288 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
580d9d08 | 8289 | |
05952246 YM |
8290 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
8291 | ||
580d9d08 | 8292 | bnx2x_iov_free_mem(bp); |
619c5cb6 VZ |
8293 | } |
8294 | ||
55c11941 | 8295 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp) |
a2fbb9ea | 8296 | { |
cd2b0389 | 8297 | if (!CHIP_IS_E1x(bp)) { |
619c5cb6 | 8298 | /* size = the status block + ramrod buffers */ |
cd2b0389 JP |
8299 | bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, |
8300 | sizeof(struct host_hc_status_block_e2)); | |
8301 | if (!bp->cnic_sb.e2_sb) | |
8302 | goto alloc_mem_err; | |
8303 | } else { | |
8304 | bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, | |
8305 | sizeof(struct host_hc_status_block_e1x)); | |
8306 | if (!bp->cnic_sb.e1x_sb) | |
8307 | goto alloc_mem_err; | |
8308 | } | |
8badd27a | 8309 | |
cd2b0389 | 8310 | if (CONFIGURE_NIC_MODE(bp) && !bp->t2) { |
16a5fd92 | 8311 | /* allocate searcher T2 table, as it wasn't allocated before */ |
cd2b0389 JP |
8312 | bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); |
8313 | if (!bp->t2) | |
8314 | goto alloc_mem_err; | |
8315 | } | |
55c11941 MS |
8316 | |
8317 | /* write address to which L5 should insert its values */ | |
8318 | bp->cnic_eth_dev.addr_drv_info_to_mcp = | |
8319 | &bp->slowpath->drv_info_to_mcp; | |
8320 | ||
8321 | if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) | |
8322 | goto alloc_mem_err; | |
8323 | ||
8324 | return 0; | |
8325 | ||
8326 | alloc_mem_err: | |
8327 | bnx2x_free_mem_cnic(bp); | |
8328 | BNX2X_ERR("Can't allocate memory\n"); | |
8329 | return -ENOMEM; | |
8330 | } | |
8331 | ||
8332 | int bnx2x_alloc_mem(struct bnx2x *bp) | |
8333 | { | |
8334 | int i, allocated, context_size; | |
a2fbb9ea | 8335 | |
cd2b0389 | 8336 | if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) { |
55c11941 | 8337 | /* allocate searcher T2 table */ |
cd2b0389 JP |
8338 | bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); |
8339 | if (!bp->t2) | |
8340 | goto alloc_mem_err; | |
8341 | } | |
8badd27a | 8342 | |
cd2b0389 JP |
8343 | bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping, |
8344 | sizeof(struct host_sp_status_block)); | |
8345 | if (!bp->def_status_blk) | |
8346 | goto alloc_mem_err; | |
a2fbb9ea | 8347 | |
cd2b0389 JP |
8348 | bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping, |
8349 | sizeof(struct bnx2x_slowpath)); | |
8350 | if (!bp->slowpath) | |
8351 | goto alloc_mem_err; | |
a2fbb9ea | 8352 | |
a052997e MS |
8353 | /* Allocate memory for CDU context: |
8354 | * This memory is allocated separately and not in the generic ILT | |
8355 | * functions because CDU differs in few aspects: | |
8356 | * 1. There are multiple entities allocating memory for context - | |
8357 | * 'regular' driver, CNIC and SRIOV driver. Each separately controls | |
8358 | * its own ILT lines. | |
8359 | * 2. Since CDU page-size is not a single 4KB page (which is the case | |
8360 | * for the other ILT clients), to be efficient we want to support | |
8361 | * allocation of sub-page-size in the last entry. | |
8362 | * 3. Context pointers are used by the driver to pass to FW / update | |
8363 | * the context (for the other ILT clients the pointers are used just to | |
8364 | * free the memory during unload). | |
8365 | */ | |
8366 | context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); | |
65abd74d | 8367 | |
a052997e MS |
8368 | for (i = 0, allocated = 0; allocated < context_size; i++) { |
8369 | bp->context[i].size = min(CDU_ILT_PAGE_SZ, | |
8370 | (context_size - allocated)); | |
cd2b0389 JP |
8371 | bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping, |
8372 | bp->context[i].size); | |
8373 | if (!bp->context[i].vcxt) | |
8374 | goto alloc_mem_err; | |
a052997e MS |
8375 | allocated += bp->context[i].size; |
8376 | } | |
cd2b0389 JP |
8377 | bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line), |
8378 | GFP_KERNEL); | |
8379 | if (!bp->ilt->lines) | |
8380 | goto alloc_mem_err; | |
65abd74d | 8381 | |
523224a3 DK |
8382 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
8383 | goto alloc_mem_err; | |
65abd74d | 8384 | |
67c431a5 AE |
8385 | if (bnx2x_iov_alloc_mem(bp)) |
8386 | goto alloc_mem_err; | |
8387 | ||
9f6c9258 | 8388 | /* Slow path ring */ |
cd2b0389 JP |
8389 | bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE); |
8390 | if (!bp->spq) | |
8391 | goto alloc_mem_err; | |
65abd74d | 8392 | |
523224a3 | 8393 | /* EQ */ |
cd2b0389 JP |
8394 | bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping, |
8395 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
8396 | if (!bp->eq_ring) | |
8397 | goto alloc_mem_err; | |
ab532cf3 | 8398 | |
9f6c9258 | 8399 | return 0; |
e1510706 | 8400 | |
9f6c9258 DK |
8401 | alloc_mem_err: |
8402 | bnx2x_free_mem(bp); | |
51c1a580 | 8403 | BNX2X_ERR("Can't allocate memory\n"); |
9f6c9258 | 8404 | return -ENOMEM; |
65abd74d YG |
8405 | } |
8406 | ||
a2fbb9ea ET |
8407 | /* |
8408 | * Init service functions | |
8409 | */ | |
a2fbb9ea | 8410 | |
619c5cb6 VZ |
8411 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
8412 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
8413 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 8414 | { |
619c5cb6 VZ |
8415 | int rc; |
8416 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 8417 | |
619c5cb6 | 8418 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 8419 | |
619c5cb6 VZ |
8420 | /* Fill general parameters */ |
8421 | ramrod_param.vlan_mac_obj = obj; | |
8422 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 8423 | |
619c5cb6 VZ |
8424 | /* Fill a user request section if needed */ |
8425 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
8426 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 8427 | |
619c5cb6 | 8428 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 8429 | |
619c5cb6 VZ |
8430 | /* Set the command: ADD or DEL */ |
8431 | if (set) | |
8432 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
8433 | else | |
8434 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
8435 | } |
8436 | ||
619c5cb6 | 8437 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7b5342d9 YM |
8438 | |
8439 | if (rc == -EEXIST) { | |
8440 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); | |
8441 | /* do not treat adding same MAC as error */ | |
8442 | rc = 0; | |
8443 | } else if (rc < 0) | |
619c5cb6 | 8444 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); |
7b5342d9 | 8445 | |
619c5cb6 | 8446 | return rc; |
a2fbb9ea ET |
8447 | } |
8448 | ||
05cc5a39 YM |
8449 | int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan, |
8450 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
8451 | unsigned long *ramrod_flags) | |
8452 | { | |
8453 | int rc; | |
8454 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
8455 | ||
8456 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
8457 | ||
8458 | /* Fill general parameters */ | |
8459 | ramrod_param.vlan_mac_obj = obj; | |
8460 | ramrod_param.ramrod_flags = *ramrod_flags; | |
8461 | ||
8462 | /* Fill a user request section if needed */ | |
8463 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
8464 | ramrod_param.user_req.u.vlan.vlan = vlan; | |
8465 | /* Set the command: ADD or DEL */ | |
8466 | if (set) | |
8467 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
8468 | else | |
8469 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
8470 | } | |
8471 | ||
8472 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); | |
8473 | ||
8474 | if (rc == -EEXIST) { | |
8475 | /* Do not treat adding same vlan as error. */ | |
8476 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); | |
8477 | rc = 0; | |
8478 | } else if (rc < 0) { | |
8479 | BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del")); | |
8480 | } | |
8481 | ||
8482 | return rc; | |
8483 | } | |
8484 | ||
619c5cb6 VZ |
8485 | int bnx2x_del_all_macs(struct bnx2x *bp, |
8486 | struct bnx2x_vlan_mac_obj *mac_obj, | |
8487 | int mac_type, bool wait_for_comp) | |
e665bfda | 8488 | { |
619c5cb6 VZ |
8489 | int rc; |
8490 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 8491 | |
619c5cb6 VZ |
8492 | /* Wait for completion of requested */ |
8493 | if (wait_for_comp) | |
8494 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 8495 | |
619c5cb6 VZ |
8496 | /* Set the mac type of addresses we want to clear */ |
8497 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 8498 | |
619c5cb6 VZ |
8499 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
8500 | if (rc < 0) | |
8501 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 8502 | |
619c5cb6 | 8503 | return rc; |
0793f83f DK |
8504 | } |
8505 | ||
619c5cb6 | 8506 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 8507 | { |
f8f4f61a DK |
8508 | if (IS_PF(bp)) { |
8509 | unsigned long ramrod_flags = 0; | |
0793f83f | 8510 | |
f8f4f61a DK |
8511 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
8512 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
8513 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, | |
8514 | &bp->sp_objs->mac_obj, set, | |
8515 | BNX2X_ETH_MAC, &ramrod_flags); | |
8516 | } else { /* vf */ | |
8517 | return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, | |
bb9e9c1d | 8518 | bp->fp->index, set); |
f8f4f61a | 8519 | } |
e665bfda | 8520 | } |
6e30dd4e | 8521 | |
619c5cb6 | 8522 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 8523 | { |
60cad4e6 AE |
8524 | if (IS_PF(bp)) |
8525 | return bnx2x_setup_queue(bp, &bp->fp[0], true); | |
8526 | else /* VF */ | |
8527 | return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); | |
993ac7b5 | 8528 | } |
a2fbb9ea | 8529 | |
d6214d7a | 8530 | /** |
e8920674 | 8531 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 8532 | * |
e8920674 | 8533 | * @bp: driver handle |
d6214d7a | 8534 | * |
e8920674 | 8535 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 8536 | */ |
1ab4434c | 8537 | int bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 8538 | { |
1ab4434c AE |
8539 | int rc = 0; |
8540 | ||
60cad4e6 AE |
8541 | if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) { |
8542 | BNX2X_ERR("VF not loaded since interrupt mode not msix\n"); | |
1ab4434c | 8543 | return -EINVAL; |
60cad4e6 | 8544 | } |
1ab4434c | 8545 | |
9ee3d37b | 8546 | switch (int_mode) { |
1ab4434c AE |
8547 | case BNX2X_INT_MODE_MSIX: |
8548 | /* attempt to enable msix */ | |
8549 | rc = bnx2x_enable_msix(bp); | |
8550 | ||
8551 | /* msix attained */ | |
8552 | if (!rc) | |
8553 | return 0; | |
8554 | ||
8555 | /* vfs use only msix */ | |
8556 | if (rc && IS_VF(bp)) | |
8557 | return rc; | |
8558 | ||
8559 | /* failed to enable multiple MSI-X */ | |
8560 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", | |
8561 | bp->num_queues, | |
8562 | 1 + bp->num_cnic_queues); | |
8563 | ||
8564 | /* falling through... */ | |
8565 | case BNX2X_INT_MODE_MSI: | |
d6214d7a | 8566 | bnx2x_enable_msi(bp); |
1ab4434c | 8567 | |
d6214d7a | 8568 | /* falling through... */ |
1ab4434c | 8569 | case BNX2X_INT_MODE_INTX: |
55c11941 MS |
8570 | bp->num_ethernet_queues = 1; |
8571 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; | |
51c1a580 | 8572 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
ca00392c | 8573 | break; |
d6214d7a | 8574 | default: |
1ab4434c AE |
8575 | BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); |
8576 | return -EINVAL; | |
9f6c9258 | 8577 | } |
1ab4434c | 8578 | return 0; |
a2fbb9ea ET |
8579 | } |
8580 | ||
1ab4434c | 8581 | /* must be called prior to any HW initializations */ |
c2bff63f DK |
8582 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) |
8583 | { | |
290ca2bb AE |
8584 | if (IS_SRIOV(bp)) |
8585 | return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; | |
c2bff63f DK |
8586 | return L2_ILT_LINES(bp); |
8587 | } | |
8588 | ||
523224a3 DK |
8589 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
8590 | { | |
8591 | struct ilt_client_info *ilt_client; | |
8592 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
8593 | u16 line = 0; | |
8594 | ||
8595 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
8596 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
8597 | ||
8598 | /* CDU */ | |
8599 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
8600 | ilt_client->client_num = ILT_CLIENT_CDU; | |
8601 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
8602 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
8603 | ilt_client->start = line; | |
619c5cb6 | 8604 | line += bnx2x_cid_ilt_lines(bp); |
55c11941 MS |
8605 | |
8606 | if (CNIC_SUPPORT(bp)) | |
8607 | line += CNIC_ILT_LINES; | |
523224a3 DK |
8608 | ilt_client->end = line - 1; |
8609 | ||
51c1a580 | 8610 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
523224a3 DK |
8611 | ilt_client->start, |
8612 | ilt_client->end, | |
8613 | ilt_client->page_size, | |
8614 | ilt_client->flags, | |
8615 | ilog2(ilt_client->page_size >> 12)); | |
8616 | ||
8617 | /* QM */ | |
8618 | if (QM_INIT(bp->qm_cid_count)) { | |
8619 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
8620 | ilt_client->client_num = ILT_CLIENT_QM; | |
8621 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
8622 | ilt_client->flags = 0; | |
8623 | ilt_client->start = line; | |
8624 | ||
8625 | /* 4 bytes for each cid */ | |
8626 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
8627 | QM_ILT_PAGE_SZ); | |
8628 | ||
8629 | ilt_client->end = line - 1; | |
8630 | ||
51c1a580 MS |
8631 | DP(NETIF_MSG_IFUP, |
8632 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
8633 | ilt_client->start, |
8634 | ilt_client->end, | |
8635 | ilt_client->page_size, | |
8636 | ilt_client->flags, | |
8637 | ilog2(ilt_client->page_size >> 12)); | |
523224a3 | 8638 | } |
523224a3 | 8639 | |
55c11941 MS |
8640 | if (CNIC_SUPPORT(bp)) { |
8641 | /* SRC */ | |
8642 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
8643 | ilt_client->client_num = ILT_CLIENT_SRC; | |
8644 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
8645 | ilt_client->flags = 0; | |
8646 | ilt_client->start = line; | |
8647 | line += SRC_ILT_LINES; | |
8648 | ilt_client->end = line - 1; | |
523224a3 | 8649 | |
55c11941 MS |
8650 | DP(NETIF_MSG_IFUP, |
8651 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8652 | ilt_client->start, | |
8653 | ilt_client->end, | |
8654 | ilt_client->page_size, | |
8655 | ilt_client->flags, | |
8656 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 8657 | |
55c11941 MS |
8658 | /* TM */ |
8659 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
8660 | ilt_client->client_num = ILT_CLIENT_TM; | |
8661 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
8662 | ilt_client->flags = 0; | |
8663 | ilt_client->start = line; | |
8664 | line += TM_ILT_LINES; | |
8665 | ilt_client->end = line - 1; | |
523224a3 | 8666 | |
55c11941 MS |
8667 | DP(NETIF_MSG_IFUP, |
8668 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8669 | ilt_client->start, | |
8670 | ilt_client->end, | |
8671 | ilt_client->page_size, | |
8672 | ilt_client->flags, | |
8673 | ilog2(ilt_client->page_size >> 12)); | |
8674 | } | |
9f6c9258 | 8675 | |
619c5cb6 | 8676 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 8677 | } |
f85582f8 | 8678 | |
619c5cb6 VZ |
8679 | /** |
8680 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
8681 | * | |
8682 | * @bp: driver handle | |
8683 | * @fp: pointer to fastpath | |
8684 | * @init_params: pointer to parameters structure | |
8685 | * | |
8686 | * parameters configured: | |
8687 | * - HC configuration | |
8688 | * - Queue's CDU context | |
8689 | */ | |
1191cb83 | 8690 | static void bnx2x_pf_q_prep_init(struct bnx2x *bp, |
619c5cb6 | 8691 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) |
a2fbb9ea | 8692 | { |
6383c0b3 | 8693 | u8 cos; |
a052997e MS |
8694 | int cxt_index, cxt_offset; |
8695 | ||
619c5cb6 VZ |
8696 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
8697 | if (!IS_FCOE_FP(fp)) { | |
8698 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
8699 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
8700 | ||
16a5fd92 | 8701 | /* If HC is supported, enable host coalescing in the transition |
619c5cb6 VZ |
8702 | * to INIT state. |
8703 | */ | |
8704 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
8705 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
8706 | ||
8707 | /* HC rate */ | |
8708 | init_params->rx.hc_rate = bp->rx_ticks ? | |
8709 | (1000000 / bp->rx_ticks) : 0; | |
8710 | init_params->tx.hc_rate = bp->tx_ticks ? | |
8711 | (1000000 / bp->tx_ticks) : 0; | |
8712 | ||
8713 | /* FW SB ID */ | |
8714 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
8715 | fp->fw_sb_id; | |
8716 | ||
8717 | /* | |
8718 | * CQ index among the SB indices: FCoE clients uses the default | |
8719 | * SB, therefore it's different. | |
8720 | */ | |
6383c0b3 AE |
8721 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
8722 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
8723 | } |
8724 | ||
6383c0b3 AE |
8725 | /* set maximum number of COSs supported by this queue */ |
8726 | init_params->max_cos = fp->max_cos; | |
8727 | ||
51c1a580 | 8728 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
8729 | fp->index, init_params->max_cos); |
8730 | ||
8731 | /* set the context pointers queue object */ | |
a052997e | 8732 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { |
65565884 MS |
8733 | cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; |
8734 | cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * | |
a052997e | 8735 | ILT_PAGE_CIDS); |
6383c0b3 | 8736 | init_params->cxts[cos] = |
a052997e MS |
8737 | &bp->context[cxt_index].vcxt[cxt_offset].eth; |
8738 | } | |
619c5cb6 VZ |
8739 | } |
8740 | ||
910cc727 | 8741 | static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
6383c0b3 AE |
8742 | struct bnx2x_queue_state_params *q_params, |
8743 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
8744 | int tx_index, bool leading) | |
8745 | { | |
8746 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
8747 | ||
8748 | /* Set the command */ | |
8749 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
8750 | ||
8751 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
8752 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
8753 | ||
8754 | /* choose the index of the cid to send the slow path on */ | |
8755 | tx_only_params->cid_index = tx_index; | |
8756 | ||
8757 | /* Set general TX_ONLY_SETUP parameters */ | |
8758 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
8759 | ||
8760 | /* Set Tx TX_ONLY_SETUP parameters */ | |
8761 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
8762 | ||
51c1a580 MS |
8763 | DP(NETIF_MSG_IFUP, |
8764 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", | |
6383c0b3 AE |
8765 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
8766 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
8767 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
8768 | ||
8769 | /* send the ramrod */ | |
8770 | return bnx2x_queue_state_change(bp, q_params); | |
8771 | } | |
8772 | ||
619c5cb6 VZ |
8773 | /** |
8774 | * bnx2x_setup_queue - setup queue | |
8775 | * | |
8776 | * @bp: driver handle | |
8777 | * @fp: pointer to fastpath | |
8778 | * @leading: is leading | |
8779 | * | |
8780 | * This function performs 2 steps in a Queue state machine | |
8781 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
8782 | */ | |
8783 | ||
8784 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
8785 | bool leading) | |
8786 | { | |
3b603066 | 8787 | struct bnx2x_queue_state_params q_params = {NULL}; |
619c5cb6 VZ |
8788 | struct bnx2x_queue_setup_params *setup_params = |
8789 | &q_params.params.setup; | |
6383c0b3 AE |
8790 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
8791 | &q_params.params.tx_only; | |
a2fbb9ea | 8792 | int rc; |
6383c0b3 AE |
8793 | u8 tx_index; |
8794 | ||
51c1a580 | 8795 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 8796 | |
ec6ba945 VZ |
8797 | /* reset IGU state skip FCoE L2 queue */ |
8798 | if (!IS_FCOE_FP(fp)) | |
8799 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 8800 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 8801 | |
15192a8c | 8802 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8803 | /* We want to wait for completion in this context */ |
8804 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8805 | |
619c5cb6 VZ |
8806 | /* Prepare the INIT parameters */ |
8807 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 8808 | |
619c5cb6 VZ |
8809 | /* Set the command */ |
8810 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
8811 | ||
8812 | /* Change the state to INIT */ | |
8813 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8814 | if (rc) { | |
6383c0b3 | 8815 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
8816 | return rc; |
8817 | } | |
ec6ba945 | 8818 | |
51c1a580 | 8819 | DP(NETIF_MSG_IFUP, "init complete\n"); |
6383c0b3 | 8820 | |
619c5cb6 VZ |
8821 | /* Now move the Queue to the SETUP state... */ |
8822 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 8823 | |
619c5cb6 VZ |
8824 | /* Set QUEUE flags */ |
8825 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 8826 | |
619c5cb6 | 8827 | /* Set general SETUP parameters */ |
6383c0b3 AE |
8828 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
8829 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 8830 | |
6383c0b3 | 8831 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
8832 | &setup_params->rxq_params); |
8833 | ||
6383c0b3 AE |
8834 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
8835 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
8836 | |
8837 | /* Set the command */ | |
8838 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
8839 | ||
55c11941 MS |
8840 | if (IS_FCOE_FP(fp)) |
8841 | bp->fcoe_init = true; | |
8842 | ||
619c5cb6 VZ |
8843 | /* Change the state to SETUP */ |
8844 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
8845 | if (rc) { |
8846 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
8847 | return rc; | |
8848 | } | |
8849 | ||
8850 | /* loop through the relevant tx-only indices */ | |
8851 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8852 | tx_index < fp->max_cos; | |
8853 | tx_index++) { | |
8854 | ||
8855 | /* prepare and send tx-only ramrod*/ | |
8856 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
8857 | tx_only_params, tx_index, leading); | |
8858 | if (rc) { | |
8859 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
8860 | fp->index, tx_index); | |
8861 | return rc; | |
8862 | } | |
8863 | } | |
523224a3 | 8864 | |
34f80b04 | 8865 | return rc; |
a2fbb9ea ET |
8866 | } |
8867 | ||
619c5cb6 | 8868 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 8869 | { |
619c5cb6 | 8870 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 8871 | struct bnx2x_fp_txdata *txdata; |
3b603066 | 8872 | struct bnx2x_queue_state_params q_params = {NULL}; |
6383c0b3 AE |
8873 | int rc, tx_index; |
8874 | ||
51c1a580 | 8875 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 8876 | |
15192a8c | 8877 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8878 | /* We want to wait for completion in this context */ |
8879 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8880 | |
6383c0b3 AE |
8881 | /* close tx-only connections */ |
8882 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8883 | tx_index < fp->max_cos; | |
8884 | tx_index++){ | |
8885 | ||
8886 | /* ascertain this is a normal queue*/ | |
65565884 | 8887 | txdata = fp->txdata_ptr[tx_index]; |
6383c0b3 | 8888 | |
51c1a580 | 8889 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
6383c0b3 AE |
8890 | txdata->txq_index); |
8891 | ||
8892 | /* send halt terminate on tx-only connection */ | |
8893 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
8894 | memset(&q_params.params.terminate, 0, | |
8895 | sizeof(q_params.params.terminate)); | |
8896 | q_params.params.terminate.cid_index = tx_index; | |
8897 | ||
8898 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8899 | if (rc) | |
8900 | return rc; | |
8901 | ||
8902 | /* send halt terminate on tx-only connection */ | |
8903 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
8904 | memset(&q_params.params.cfc_del, 0, | |
8905 | sizeof(q_params.params.cfc_del)); | |
8906 | q_params.params.cfc_del.cid_index = tx_index; | |
8907 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8908 | if (rc) | |
8909 | return rc; | |
8910 | } | |
8911 | /* Stop the primary connection: */ | |
8912 | /* ...halt the connection */ | |
619c5cb6 VZ |
8913 | q_params.cmd = BNX2X_Q_CMD_HALT; |
8914 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8915 | if (rc) | |
da5a662a | 8916 | return rc; |
a2fbb9ea | 8917 | |
6383c0b3 | 8918 | /* ...terminate the connection */ |
619c5cb6 | 8919 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
8920 | memset(&q_params.params.terminate, 0, |
8921 | sizeof(q_params.params.terminate)); | |
8922 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
8923 | rc = bnx2x_queue_state_change(bp, &q_params); |
8924 | if (rc) | |
523224a3 | 8925 | return rc; |
6383c0b3 | 8926 | /* ...delete cfc entry */ |
619c5cb6 | 8927 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
8928 | memset(&q_params.params.cfc_del, 0, |
8929 | sizeof(q_params.params.cfc_del)); | |
8930 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 8931 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
8932 | } |
8933 | ||
34f80b04 EG |
8934 | static void bnx2x_reset_func(struct bnx2x *bp) |
8935 | { | |
8936 | int port = BP_PORT(bp); | |
8937 | int func = BP_FUNC(bp); | |
f2e0899f | 8938 | int i; |
523224a3 DK |
8939 | |
8940 | /* Disable the function in the FW */ | |
8941 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
8942 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
8943 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
8944 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
8945 | ||
8946 | /* FP SBs */ | |
ec6ba945 | 8947 | for_each_eth_queue(bp, i) { |
523224a3 | 8948 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 8949 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8950 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
8951 | SB_DISABLED); | |
523224a3 DK |
8952 | } |
8953 | ||
55c11941 MS |
8954 | if (CNIC_LOADED(bp)) |
8955 | /* CNIC SB */ | |
8956 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
8957 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET | |
8958 | (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); | |
8959 | ||
523224a3 | 8960 | /* SP SB */ |
619c5cb6 | 8961 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
2de67439 YM |
8962 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
8963 | SB_DISABLED); | |
523224a3 DK |
8964 | |
8965 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
8966 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
8967 | 0); | |
34f80b04 EG |
8968 | |
8969 | /* Configure IGU */ | |
f2e0899f DK |
8970 | if (bp->common.int_block == INT_BLOCK_HC) { |
8971 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
8972 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
8973 | } else { | |
8974 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
8975 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
8976 | } | |
34f80b04 | 8977 | |
55c11941 MS |
8978 | if (CNIC_LOADED(bp)) { |
8979 | /* Disable Timer scan */ | |
8980 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
8981 | /* | |
8982 | * Wait for at least 10ms and up to 2 second for the timers | |
8983 | * scan to complete | |
8984 | */ | |
8985 | for (i = 0; i < 200; i++) { | |
639d65b8 | 8986 | usleep_range(10000, 20000); |
55c11941 MS |
8987 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) |
8988 | break; | |
8989 | } | |
37b091ba | 8990 | } |
34f80b04 | 8991 | /* Clear ILT */ |
f2e0899f DK |
8992 | bnx2x_clear_func_ilt(bp, func); |
8993 | ||
8994 | /* Timers workaround bug for E2: if this is vnic-3, | |
8995 | * we need to set the entire ilt range for this timers. | |
8996 | */ | |
619c5cb6 | 8997 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
8998 | struct ilt_client_info ilt_cli; |
8999 | /* use dummy TM client */ | |
9000 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
9001 | ilt_cli.start = 0; | |
9002 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
9003 | ilt_cli.client_num = ILT_CLIENT_TM; | |
9004 | ||
9005 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
9006 | } | |
9007 | ||
9008 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 9009 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 9010 | bnx2x_pf_disable(bp); |
523224a3 DK |
9011 | |
9012 | bp->dmae_ready = 0; | |
34f80b04 EG |
9013 | } |
9014 | ||
9015 | static void bnx2x_reset_port(struct bnx2x *bp) | |
9016 | { | |
9017 | int port = BP_PORT(bp); | |
9018 | u32 val; | |
9019 | ||
619c5cb6 VZ |
9020 | /* Reset physical Link */ |
9021 | bnx2x__link_reset(bp); | |
9022 | ||
34f80b04 EG |
9023 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
9024 | ||
9025 | /* Do not rcv packets to BRB */ | |
9026 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
9027 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
9028 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
9029 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
9030 | ||
9031 | /* Configure AEU */ | |
9032 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
9033 | ||
9034 | msleep(100); | |
9035 | /* Check for BRB port occupancy */ | |
9036 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
9037 | if (val) | |
9038 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 9039 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
9040 | |
9041 | /* TODO: Close Doorbell port? */ | |
9042 | } | |
9043 | ||
1191cb83 | 9044 | static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 9045 | { |
3b603066 | 9046 | struct bnx2x_func_state_params func_params = {NULL}; |
34f80b04 | 9047 | |
619c5cb6 VZ |
9048 | /* Prepare parameters for function state transitions */ |
9049 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 9050 | |
619c5cb6 VZ |
9051 | func_params.f_obj = &bp->func_obj; |
9052 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 9053 | |
619c5cb6 | 9054 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 9055 | |
619c5cb6 | 9056 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
9057 | } |
9058 | ||
1191cb83 | 9059 | static int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 9060 | { |
3b603066 | 9061 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 | 9062 | int rc; |
228241eb | 9063 | |
619c5cb6 VZ |
9064 | /* Prepare parameters for function state transitions */ |
9065 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
9066 | func_params.f_obj = &bp->func_obj; | |
9067 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 9068 | |
619c5cb6 VZ |
9069 | /* |
9070 | * Try to stop the function the 'good way'. If fails (in case | |
9071 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
9072 | * not in a debug mode, perform a state transaction in order to | |
9073 | * enable further HW_RESET transaction. | |
9074 | */ | |
9075 | rc = bnx2x_func_state_change(bp, &func_params); | |
9076 | if (rc) { | |
34f80b04 | 9077 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 9078 | return rc; |
34f80b04 | 9079 | #else |
51c1a580 | 9080 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
619c5cb6 VZ |
9081 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
9082 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 9083 | #endif |
228241eb | 9084 | } |
a2fbb9ea | 9085 | |
619c5cb6 VZ |
9086 | return 0; |
9087 | } | |
523224a3 | 9088 | |
619c5cb6 VZ |
9089 | /** |
9090 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
9091 | * | |
9092 | * @bp: driver handle | |
9093 | * @unload_mode: requested function's unload mode | |
9094 | * | |
9095 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
9096 | */ | |
9097 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
9098 | { | |
9099 | u32 reset_code = 0; | |
9100 | int port = BP_PORT(bp); | |
3101c2bc | 9101 | |
619c5cb6 | 9102 | /* Select the UNLOAD request mode */ |
65abd74d YG |
9103 | if (unload_mode == UNLOAD_NORMAL) |
9104 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
9105 | ||
7d0446c2 | 9106 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 9107 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 9108 | |
7d0446c2 | 9109 | else if (bp->wol) { |
65abd74d YG |
9110 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
9111 | u8 *mac_addr = bp->dev->dev_addr; | |
29ed74c3 | 9112 | struct pci_dev *pdev = bp->pdev; |
65abd74d | 9113 | u32 val; |
f9977903 DK |
9114 | u16 pmc; |
9115 | ||
65abd74d | 9116 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
9117 | * preserve entry 0 which is used by the PMF |
9118 | */ | |
3395a033 | 9119 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
9120 | |
9121 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
9122 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
9123 | ||
9124 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
9125 | (mac_addr[4] << 8) | mac_addr[5]; | |
9126 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
9127 | ||
f9977903 | 9128 | /* Enable the PME and clear the status */ |
29ed74c3 | 9129 | pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc); |
f9977903 | 9130 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; |
29ed74c3 | 9131 | pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc); |
f9977903 | 9132 | |
65abd74d YG |
9133 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
9134 | ||
9135 | } else | |
9136 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 9137 | |
619c5cb6 VZ |
9138 | /* Send the request to the MCP */ |
9139 | if (!BP_NOMCP(bp)) | |
9140 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
9141 | else { | |
9142 | int path = BP_PATH(bp); | |
9143 | ||
51c1a580 | 9144 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
a8f47eb7 | 9145 | path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], |
9146 | bnx2x_load_count[path][2]); | |
9147 | bnx2x_load_count[path][0]--; | |
9148 | bnx2x_load_count[path][1 + port]--; | |
51c1a580 | 9149 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
a8f47eb7 | 9150 | path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], |
9151 | bnx2x_load_count[path][2]); | |
9152 | if (bnx2x_load_count[path][0] == 0) | |
619c5cb6 | 9153 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; |
a8f47eb7 | 9154 | else if (bnx2x_load_count[path][1 + port] == 0) |
619c5cb6 VZ |
9155 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; |
9156 | else | |
9157 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
9158 | } | |
9159 | ||
9160 | return reset_code; | |
9161 | } | |
9162 | ||
9163 | /** | |
9164 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
9165 | * | |
9166 | * @bp: driver handle | |
5d07d868 | 9167 | * @keep_link: true iff link should be kept up |
619c5cb6 | 9168 | */ |
5d07d868 | 9169 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) |
619c5cb6 | 9170 | { |
5d07d868 YM |
9171 | u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; |
9172 | ||
619c5cb6 VZ |
9173 | /* Report UNLOAD_DONE to MCP */ |
9174 | if (!BP_NOMCP(bp)) | |
5d07d868 | 9175 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); |
619c5cb6 VZ |
9176 | } |
9177 | ||
1191cb83 | 9178 | static int bnx2x_func_wait_started(struct bnx2x *bp) |
6debea87 DK |
9179 | { |
9180 | int tout = 50; | |
9181 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
9182 | ||
9183 | if (!bp->port.pmf) | |
9184 | return 0; | |
9185 | ||
9186 | /* | |
9187 | * (assumption: No Attention from MCP at this stage) | |
16a5fd92 | 9188 | * PMF probably in the middle of TX disable/enable transaction |
6debea87 | 9189 | * 1. Sync IRS for default SB |
16a5fd92 YM |
9190 | * 2. Sync SP queue - this guarantees us that attention handling started |
9191 | * 3. Wait, that TX disable/enable transaction completes | |
6debea87 | 9192 | * |
16a5fd92 YM |
9193 | * 1+2 guarantee that if DCBx attention was scheduled it already changed |
9194 | * pending bit of transaction from STARTED-->TX_STOPPED, if we already | |
9195 | * received completion for the transaction the state is TX_STOPPED. | |
6debea87 DK |
9196 | * State will return to STARTED after completion of TX_STOPPED-->STARTED |
9197 | * transaction. | |
9198 | */ | |
9199 | ||
9200 | /* make sure default SB ISR is done */ | |
9201 | if (msix) | |
9202 | synchronize_irq(bp->msix_table[0].vector); | |
9203 | else | |
9204 | synchronize_irq(bp->pdev->irq); | |
9205 | ||
9206 | flush_workqueue(bnx2x_wq); | |
370d4a26 | 9207 | flush_workqueue(bnx2x_iov_wq); |
6debea87 DK |
9208 | |
9209 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
9210 | BNX2X_F_STATE_STARTED && tout--) | |
9211 | msleep(20); | |
9212 | ||
9213 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
9214 | BNX2X_F_STATE_STARTED) { | |
9215 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 9216 | BNX2X_ERR("Wrong function state\n"); |
6debea87 DK |
9217 | return -EBUSY; |
9218 | #else | |
9219 | /* | |
9220 | * Failed to complete the transaction in a "good way" | |
9221 | * Force both transactions with CLR bit | |
9222 | */ | |
3b603066 | 9223 | struct bnx2x_func_state_params func_params = {NULL}; |
6debea87 | 9224 | |
51c1a580 | 9225 | DP(NETIF_MSG_IFDOWN, |
0c23ad37 | 9226 | "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n"); |
6debea87 DK |
9227 | |
9228 | func_params.f_obj = &bp->func_obj; | |
9229 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
9230 | &func_params.ramrod_flags); | |
9231 | ||
9232 | /* STARTED-->TX_ST0PPED */ | |
9233 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
9234 | bnx2x_func_state_change(bp, &func_params); | |
9235 | ||
9236 | /* TX_ST0PPED-->STARTED */ | |
9237 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
9238 | return bnx2x_func_state_change(bp, &func_params); | |
9239 | #endif | |
9240 | } | |
9241 | ||
9242 | return 0; | |
9243 | } | |
9244 | ||
eeed018c MK |
9245 | static void bnx2x_disable_ptp(struct bnx2x *bp) |
9246 | { | |
9247 | int port = BP_PORT(bp); | |
9248 | ||
9249 | /* Disable sending PTP packets to host */ | |
9250 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : | |
9251 | NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); | |
9252 | ||
9253 | /* Reset PTP event detection rules */ | |
9254 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
9255 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); | |
9256 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
9257 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); | |
9258 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : | |
9259 | NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); | |
9260 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : | |
9261 | NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); | |
9262 | ||
9263 | /* Disable the PTP feature */ | |
9264 | REG_WR(bp, port ? NIG_REG_P1_PTP_EN : | |
9265 | NIG_REG_P0_PTP_EN, 0x0); | |
9266 | } | |
9267 | ||
9268 | /* Called during unload, to stop PTP-related stuff */ | |
1444c301 | 9269 | static void bnx2x_stop_ptp(struct bnx2x *bp) |
eeed018c MK |
9270 | { |
9271 | /* Cancel PTP work queue. Should be done after the Tx queues are | |
9272 | * drained to prevent additional scheduling. | |
9273 | */ | |
9274 | cancel_work_sync(&bp->ptp_task); | |
9275 | ||
9276 | if (bp->ptp_tx_skb) { | |
9277 | dev_kfree_skb_any(bp->ptp_tx_skb); | |
9278 | bp->ptp_tx_skb = NULL; | |
9279 | } | |
9280 | ||
9281 | /* Disable PTP in HW */ | |
9282 | bnx2x_disable_ptp(bp); | |
9283 | ||
9284 | DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n"); | |
9285 | } | |
9286 | ||
5d07d868 | 9287 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) |
619c5cb6 VZ |
9288 | { |
9289 | int port = BP_PORT(bp); | |
6383c0b3 AE |
9290 | int i, rc = 0; |
9291 | u8 cos; | |
3b603066 | 9292 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 VZ |
9293 | u32 reset_code; |
9294 | ||
9295 | /* Wait until tx fastpath tasks complete */ | |
9296 | for_each_tx_queue(bp, i) { | |
9297 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
9298 | ||
6383c0b3 | 9299 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 9300 | rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); |
619c5cb6 VZ |
9301 | #ifdef BNX2X_STOP_ON_ERROR |
9302 | if (rc) | |
9303 | return; | |
9304 | #endif | |
9305 | } | |
9306 | ||
9307 | /* Give HW time to discard old tx messages */ | |
0926d499 | 9308 | usleep_range(1000, 2000); |
619c5cb6 VZ |
9309 | |
9310 | /* Clean all ETH MACs */ | |
15192a8c BW |
9311 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, |
9312 | false); | |
619c5cb6 VZ |
9313 | if (rc < 0) |
9314 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
9315 | ||
9316 | /* Clean up UC list */ | |
15192a8c | 9317 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, |
619c5cb6 VZ |
9318 | true); |
9319 | if (rc < 0) | |
51c1a580 MS |
9320 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
9321 | rc); | |
619c5cb6 VZ |
9322 | |
9323 | /* Disable LLH */ | |
9324 | if (!CHIP_IS_E1(bp)) | |
9325 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
9326 | ||
9327 | /* Set "drop all" (stop Rx). | |
9328 | * We need to take a netif_addr_lock() here in order to prevent | |
9329 | * a race between the completion code and this code. | |
9330 | */ | |
9331 | netif_addr_lock_bh(bp->dev); | |
9332 | /* Schedule the rx_mode command */ | |
9333 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
9334 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
9335 | else | |
9336 | bnx2x_set_storm_rx_mode(bp); | |
9337 | ||
9338 | /* Cleanup multicast configuration */ | |
9339 | rparam.mcast_obj = &bp->mcast_obj; | |
9340 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
9341 | if (rc < 0) | |
9342 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
9343 | ||
9344 | netif_addr_unlock_bh(bp->dev); | |
9345 | ||
f1929b01 | 9346 | bnx2x_iov_chip_cleanup(bp); |
619c5cb6 | 9347 | |
6debea87 DK |
9348 | /* |
9349 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
9350 | * this function should perform FUNC, PORT or COMMON HW | |
9351 | * reset. | |
9352 | */ | |
9353 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
9354 | ||
9355 | /* | |
9356 | * (assumption: No Attention from MCP at this stage) | |
16a5fd92 | 9357 | * PMF probably in the middle of TX disable/enable transaction |
6debea87 DK |
9358 | */ |
9359 | rc = bnx2x_func_wait_started(bp); | |
9360 | if (rc) { | |
9361 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
9362 | #ifdef BNX2X_STOP_ON_ERROR | |
9363 | return; | |
9364 | #endif | |
9365 | } | |
9366 | ||
34f80b04 | 9367 | /* Close multi and leading connections |
619c5cb6 VZ |
9368 | * Completions for ramrods are collected in a synchronous way |
9369 | */ | |
55c11941 | 9370 | for_each_eth_queue(bp, i) |
619c5cb6 | 9371 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
9372 | #ifdef BNX2X_STOP_ON_ERROR |
9373 | return; | |
9374 | #else | |
228241eb | 9375 | goto unload_error; |
523224a3 | 9376 | #endif |
55c11941 MS |
9377 | |
9378 | if (CNIC_LOADED(bp)) { | |
9379 | for_each_cnic_queue(bp, i) | |
9380 | if (bnx2x_stop_queue(bp, i)) | |
9381 | #ifdef BNX2X_STOP_ON_ERROR | |
9382 | return; | |
9383 | #else | |
9384 | goto unload_error; | |
9385 | #endif | |
9386 | } | |
9387 | ||
619c5cb6 VZ |
9388 | /* If SP settings didn't get completed so far - something |
9389 | * very wrong has happen. | |
9390 | */ | |
9391 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
9392 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 9393 | |
619c5cb6 VZ |
9394 | #ifndef BNX2X_STOP_ON_ERROR |
9395 | unload_error: | |
9396 | #endif | |
523224a3 | 9397 | rc = bnx2x_func_stop(bp); |
da5a662a | 9398 | if (rc) { |
523224a3 | 9399 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 9400 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 9401 | return; |
523224a3 | 9402 | #endif |
34f80b04 | 9403 | } |
a2fbb9ea | 9404 | |
eeed018c MK |
9405 | /* stop_ptp should be after the Tx queues are drained to prevent |
9406 | * scheduling to the cancelled PTP work queue. It should also be after | |
9407 | * function stop ramrod is sent, since as part of this ramrod FW access | |
9408 | * PTP registers. | |
9409 | */ | |
d53c66a5 ED |
9410 | if (bp->flags & PTP_SUPPORTED) |
9411 | bnx2x_stop_ptp(bp); | |
eeed018c | 9412 | |
523224a3 DK |
9413 | /* Disable HW interrupts, NAPI */ |
9414 | bnx2x_netif_stop(bp, 1); | |
26614ba5 MS |
9415 | /* Delete all NAPI objects */ |
9416 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
9417 | if (CNIC_LOADED(bp)) |
9418 | bnx2x_del_all_napi_cnic(bp); | |
523224a3 DK |
9419 | |
9420 | /* Release IRQs */ | |
d6214d7a | 9421 | bnx2x_free_irq(bp); |
523224a3 | 9422 | |
a2fbb9ea | 9423 | /* Reset the chip */ |
619c5cb6 VZ |
9424 | rc = bnx2x_reset_hw(bp, reset_code); |
9425 | if (rc) | |
9426 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 9427 | |
619c5cb6 | 9428 | /* Report UNLOAD_DONE to MCP */ |
5d07d868 | 9429 | bnx2x_send_unload_done(bp, keep_link); |
72fd0718 VZ |
9430 | } |
9431 | ||
9f6c9258 | 9432 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
9433 | { |
9434 | u32 val; | |
9435 | ||
51c1a580 | 9436 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
72fd0718 VZ |
9437 | |
9438 | if (CHIP_IS_E1(bp)) { | |
9439 | int port = BP_PORT(bp); | |
9440 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
9441 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
9442 | ||
9443 | val = REG_RD(bp, addr); | |
9444 | val &= ~(0x300); | |
9445 | REG_WR(bp, addr, val); | |
619c5cb6 | 9446 | } else { |
72fd0718 VZ |
9447 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
9448 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
9449 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
9450 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
9451 | } | |
9452 | } | |
9453 | ||
72fd0718 VZ |
9454 | /* Close gates #2, #3 and #4: */ |
9455 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
9456 | { | |
c9ee9206 | 9457 | u32 val; |
72fd0718 VZ |
9458 | |
9459 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
9460 | if (!CHIP_IS_E1(bp)) { | |
9461 | /* #4 */ | |
c9ee9206 | 9462 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 9463 | /* #2 */ |
c9ee9206 | 9464 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
9465 | } |
9466 | ||
9467 | /* #3 */ | |
c9ee9206 VZ |
9468 | if (CHIP_IS_E1x(bp)) { |
9469 | /* Prevent interrupts from HC on both ports */ | |
9470 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
9471 | REG_WR(bp, HC_REG_CONFIG_1, | |
9472 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
9473 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
9474 | ||
9475 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
9476 | REG_WR(bp, HC_REG_CONFIG_0, | |
9477 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
9478 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
9479 | } else { | |
d82603c6 | 9480 | /* Prevent incoming interrupts in IGU */ |
c9ee9206 VZ |
9481 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
9482 | ||
9483 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
9484 | (!close) ? | |
9485 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
9486 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
9487 | } | |
72fd0718 | 9488 | |
51c1a580 | 9489 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
72fd0718 VZ |
9490 | close ? "closing" : "opening"); |
9491 | mmiowb(); | |
9492 | } | |
9493 | ||
9494 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
9495 | ||
9496 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
9497 | { | |
9498 | /* Do some magic... */ | |
9499 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
9500 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
9501 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
9502 | } | |
9503 | ||
e8920674 DK |
9504 | /** |
9505 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 9506 | * |
e8920674 DK |
9507 | * @bp: driver handle |
9508 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
9509 | */ |
9510 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
9511 | { | |
9512 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
9513 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
9514 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
9515 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
9516 | } | |
9517 | ||
f85582f8 | 9518 | /** |
e8920674 | 9519 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 9520 | * |
e8920674 DK |
9521 | * @bp: driver handle |
9522 | * @magic_val: old value of 'magic' bit. | |
9523 | * | |
9524 | * Takes care of CLP configurations. | |
72fd0718 VZ |
9525 | */ |
9526 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
9527 | { | |
9528 | u32 shmem; | |
9529 | u32 validity_offset; | |
9530 | ||
51c1a580 | 9531 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
72fd0718 VZ |
9532 | |
9533 | /* Set `magic' bit in order to save MF config */ | |
9534 | if (!CHIP_IS_E1(bp)) | |
9535 | bnx2x_clp_reset_prep(bp, magic_val); | |
9536 | ||
9537 | /* Get shmem offset */ | |
9538 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
c55e771b BW |
9539 | validity_offset = |
9540 | offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); | |
72fd0718 VZ |
9541 | |
9542 | /* Clear validity map flags */ | |
9543 | if (shmem > 0) | |
9544 | REG_WR(bp, shmem + validity_offset, 0); | |
9545 | } | |
9546 | ||
9547 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
9548 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
9549 | ||
e8920674 DK |
9550 | /** |
9551 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 9552 | * |
e8920674 | 9553 | * @bp: driver handle |
72fd0718 | 9554 | */ |
1191cb83 | 9555 | static void bnx2x_mcp_wait_one(struct bnx2x *bp) |
72fd0718 VZ |
9556 | { |
9557 | /* special handling for emulation and FPGA, | |
9558 | wait 10 times longer */ | |
9559 | if (CHIP_REV_IS_SLOW(bp)) | |
9560 | msleep(MCP_ONE_TIMEOUT*10); | |
9561 | else | |
9562 | msleep(MCP_ONE_TIMEOUT); | |
9563 | } | |
9564 | ||
1b6e2ceb DK |
9565 | /* |
9566 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
9567 | */ | |
9568 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 9569 | { |
1b6e2ceb DK |
9570 | int cnt = 0; |
9571 | u32 val = 0; | |
72fd0718 | 9572 | |
1b6e2ceb DK |
9573 | do { |
9574 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
9575 | if (bp->common.shmem_base) { | |
9576 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
9577 | if (val & SHR_MEM_VALIDITY_MB) | |
9578 | return 0; | |
9579 | } | |
72fd0718 | 9580 | |
1b6e2ceb | 9581 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 9582 | |
1b6e2ceb | 9583 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 9584 | |
1b6e2ceb | 9585 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 9586 | |
1b6e2ceb DK |
9587 | return -ENODEV; |
9588 | } | |
72fd0718 | 9589 | |
1b6e2ceb DK |
9590 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
9591 | { | |
9592 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 9593 | |
72fd0718 VZ |
9594 | /* Restore the `magic' bit value */ |
9595 | if (!CHIP_IS_E1(bp)) | |
9596 | bnx2x_clp_reset_done(bp, magic_val); | |
9597 | ||
9598 | return rc; | |
9599 | } | |
9600 | ||
9601 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
9602 | { | |
9603 | if (!CHIP_IS_E1(bp)) { | |
9604 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
9605 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
9606 | mmiowb(); |
9607 | } | |
9608 | } | |
9609 | ||
9610 | /* | |
9611 | * Reset the whole chip except for: | |
9612 | * - PCIE core | |
9613 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
9614 | * one reset bit) | |
9615 | * - IGU | |
9616 | * - MISC (including AEU) | |
9617 | * - GRC | |
9618 | * - RBCN, RBCP | |
9619 | */ | |
c9ee9206 | 9620 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
9621 | { |
9622 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 9623 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
9624 | |
9625 | /* | |
9626 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
9627 | * (per chip) blocks. | |
9628 | */ | |
9629 | global_bits2 = | |
9630 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
9631 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 9632 | |
c55e771b BW |
9633 | /* Don't reset the following blocks. |
9634 | * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be | |
9635 | * reset, as in 4 port device they might still be owned | |
9636 | * by the MCP (there is only one leader per path). | |
9637 | */ | |
72fd0718 VZ |
9638 | not_reset_mask1 = |
9639 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
9640 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
9641 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
9642 | ||
9643 | not_reset_mask2 = | |
c9ee9206 | 9644 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
9645 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
9646 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
9647 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
9648 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
9649 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
9650 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
9651 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
9652 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
c55e771b BW |
9653 | MISC_REGISTERS_RESET_REG_2_PGLC | |
9654 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
9655 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
9656 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
9657 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
9658 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
9659 | MISC_REGISTERS_RESET_REG_2_UMAC1; | |
72fd0718 | 9660 | |
8736c826 VZ |
9661 | /* |
9662 | * Keep the following blocks in reset: | |
9663 | * - all xxMACs are handled by the bnx2x_link code. | |
9664 | */ | |
9665 | stay_reset2 = | |
8736c826 VZ |
9666 | MISC_REGISTERS_RESET_REG_2_XMAC | |
9667 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
9668 | ||
9669 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
9670 | reset_mask1 = 0xffffffff; |
9671 | ||
9672 | if (CHIP_IS_E1(bp)) | |
9673 | reset_mask2 = 0xffff; | |
8736c826 | 9674 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 9675 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
9676 | else if (CHIP_IS_E2(bp)) |
9677 | reset_mask2 = 0xfffff; | |
9678 | else /* CHIP_IS_E3 */ | |
9679 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
9680 | |
9681 | /* Don't reset global blocks unless we need to */ | |
9682 | if (!global) | |
9683 | reset_mask2 &= ~global_bits2; | |
9684 | ||
9685 | /* | |
9686 | * In case of attention in the QM, we need to reset PXP | |
9687 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
9688 | * because otherwise QM reset would release 'close the gates' shortly | |
9689 | * before resetting the PXP, then the PSWRQ would send a write | |
9690 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
9691 | * read the payload data from PSWWR, but PSWWR would not | |
9692 | * respond. The write queue in PGLUE would stuck, dmae commands | |
9693 | * would not return. Therefore it's important to reset the second | |
9694 | * reset register (containing the | |
9695 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
9696 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
9697 | * bit). | |
9698 | */ | |
72fd0718 VZ |
9699 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
9700 | reset_mask2 & (~not_reset_mask2)); | |
9701 | ||
c9ee9206 VZ |
9702 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
9703 | reset_mask1 & (~not_reset_mask1)); | |
9704 | ||
72fd0718 VZ |
9705 | barrier(); |
9706 | mmiowb(); | |
9707 | ||
8736c826 VZ |
9708 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
9709 | reset_mask2 & (~stay_reset2)); | |
9710 | ||
9711 | barrier(); | |
9712 | mmiowb(); | |
9713 | ||
c9ee9206 | 9714 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
9715 | mmiowb(); |
9716 | } | |
9717 | ||
c9ee9206 VZ |
9718 | /** |
9719 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
9720 | * It should get cleared in no more than 1s. | |
9721 | * | |
9722 | * @bp: driver handle | |
9723 | * | |
9724 | * It should get cleared in no more than 1s. Returns 0 if | |
9725 | * pending writes bit gets cleared. | |
9726 | */ | |
9727 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
9728 | { | |
9729 | u32 cnt = 1000; | |
9730 | u32 pend_bits = 0; | |
9731 | ||
9732 | do { | |
9733 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
9734 | ||
9735 | if (pend_bits == 0) | |
9736 | break; | |
9737 | ||
0926d499 | 9738 | usleep_range(1000, 2000); |
c9ee9206 VZ |
9739 | } while (cnt-- > 0); |
9740 | ||
9741 | if (cnt <= 0) { | |
9742 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
9743 | pend_bits); | |
9744 | return -EBUSY; | |
9745 | } | |
9746 | ||
9747 | return 0; | |
9748 | } | |
9749 | ||
9750 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
9751 | { |
9752 | int cnt = 1000; | |
9753 | u32 val = 0; | |
9754 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
2de67439 | 9755 | u32 tags_63_32 = 0; |
72fd0718 VZ |
9756 | |
9757 | /* Empty the Tetris buffer, wait for 1s */ | |
9758 | do { | |
9759 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
9760 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
9761 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
9762 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
9763 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
c55e771b BW |
9764 | if (CHIP_IS_E3(bp)) |
9765 | tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); | |
9766 | ||
72fd0718 VZ |
9767 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && |
9768 | ((port_is_idle_0 & 0x1) == 0x1) && | |
9769 | ((port_is_idle_1 & 0x1) == 0x1) && | |
c55e771b BW |
9770 | (pgl_exp_rom2 == 0xffffffff) && |
9771 | (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) | |
72fd0718 | 9772 | break; |
0926d499 | 9773 | usleep_range(1000, 2000); |
72fd0718 VZ |
9774 | } while (cnt-- > 0); |
9775 | ||
9776 | if (cnt <= 0) { | |
51c1a580 MS |
9777 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
9778 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
72fd0718 VZ |
9779 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
9780 | pgl_exp_rom2); | |
9781 | return -EAGAIN; | |
9782 | } | |
9783 | ||
9784 | barrier(); | |
9785 | ||
9786 | /* Close gates #2, #3 and #4 */ | |
9787 | bnx2x_set_234_gates(bp, true); | |
9788 | ||
c9ee9206 VZ |
9789 | /* Poll for IGU VQs for 57712 and newer chips */ |
9790 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
9791 | return -EAGAIN; | |
9792 | ||
72fd0718 VZ |
9793 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
9794 | ||
9795 | /* Clear "unprepared" bit */ | |
9796 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
9797 | barrier(); | |
9798 | ||
9799 | /* Make sure all is written to the chip before the reset */ | |
9800 | mmiowb(); | |
9801 | ||
9802 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
9803 | * PSWHST, GRC and PSWRD Tetris buffer. | |
9804 | */ | |
0926d499 | 9805 | usleep_range(1000, 2000); |
72fd0718 VZ |
9806 | |
9807 | /* Prepare to chip reset: */ | |
9808 | /* MCP */ | |
c9ee9206 VZ |
9809 | if (global) |
9810 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
9811 | |
9812 | /* PXP */ | |
9813 | bnx2x_pxp_prep(bp); | |
9814 | barrier(); | |
9815 | ||
9816 | /* reset the chip */ | |
c9ee9206 | 9817 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
9818 | barrier(); |
9819 | ||
9dcd9acd DK |
9820 | /* clear errors in PGB */ |
9821 | if (!CHIP_IS_E1x(bp)) | |
9822 | REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); | |
9823 | ||
72fd0718 VZ |
9824 | /* Recover after reset: */ |
9825 | /* MCP */ | |
c9ee9206 | 9826 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
9827 | return -EAGAIN; |
9828 | ||
c9ee9206 VZ |
9829 | /* TBD: Add resetting the NO_MCP mode DB here */ |
9830 | ||
72fd0718 VZ |
9831 | /* Open the gates #2, #3 and #4 */ |
9832 | bnx2x_set_234_gates(bp, false); | |
9833 | ||
9834 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
9835 | * reset state, re-enable attentions. */ | |
9836 | ||
a2fbb9ea ET |
9837 | return 0; |
9838 | } | |
9839 | ||
910cc727 | 9840 | static int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
9841 | { |
9842 | int rc = 0; | |
c9ee9206 | 9843 | bool global = bnx2x_reset_is_global(bp); |
95c6c616 AE |
9844 | u32 load_code; |
9845 | ||
9846 | /* if not going to reset MCP - load "fake" driver to reset HW while | |
9847 | * driver is owner of the HW | |
9848 | */ | |
9849 | if (!global && !BP_NOMCP(bp)) { | |
5d07d868 YM |
9850 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, |
9851 | DRV_MSG_CODE_LOAD_REQ_WITH_LFA); | |
95c6c616 AE |
9852 | if (!load_code) { |
9853 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9854 | rc = -EAGAIN; | |
9855 | goto exit_leader_reset; | |
9856 | } | |
9857 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && | |
9858 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { | |
9859 | BNX2X_ERR("MCP unexpected resp, aborting\n"); | |
9860 | rc = -EAGAIN; | |
9861 | goto exit_leader_reset2; | |
9862 | } | |
9863 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
9864 | if (!load_code) { | |
9865 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9866 | rc = -EAGAIN; | |
9867 | goto exit_leader_reset2; | |
9868 | } | |
9869 | } | |
c9ee9206 | 9870 | |
72fd0718 | 9871 | /* Try to recover after the failure */ |
c9ee9206 | 9872 | if (bnx2x_process_kill(bp, global)) { |
51c1a580 MS |
9873 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
9874 | BP_PATH(bp)); | |
72fd0718 | 9875 | rc = -EAGAIN; |
95c6c616 | 9876 | goto exit_leader_reset2; |
72fd0718 VZ |
9877 | } |
9878 | ||
c9ee9206 VZ |
9879 | /* |
9880 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
9881 | * state. | |
9882 | */ | |
72fd0718 | 9883 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
9884 | if (global) |
9885 | bnx2x_clear_reset_global(bp); | |
72fd0718 | 9886 | |
95c6c616 AE |
9887 | exit_leader_reset2: |
9888 | /* unload "fake driver" if it was loaded */ | |
9889 | if (!global && !BP_NOMCP(bp)) { | |
9890 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); | |
9891 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
9892 | } | |
72fd0718 VZ |
9893 | exit_leader_reset: |
9894 | bp->is_leader = 0; | |
c9ee9206 VZ |
9895 | bnx2x_release_leader_lock(bp); |
9896 | smp_mb(); | |
72fd0718 VZ |
9897 | return rc; |
9898 | } | |
9899 | ||
1191cb83 | 9900 | static void bnx2x_recovery_failed(struct bnx2x *bp) |
c9ee9206 VZ |
9901 | { |
9902 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
9903 | ||
9904 | /* Disconnect this device */ | |
9905 | netif_device_detach(bp->dev); | |
9906 | ||
9907 | /* | |
9908 | * Block ifup for all function on this engine until "process kill" | |
9909 | * or power cycle. | |
9910 | */ | |
9911 | bnx2x_set_reset_in_progress(bp); | |
9912 | ||
9913 | /* Shut down the power */ | |
9914 | bnx2x_set_power_state(bp, PCI_D3hot); | |
9915 | ||
9916 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
9917 | ||
9918 | smp_mb(); | |
9919 | } | |
9920 | ||
9921 | /* | |
9922 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 9923 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
9924 | * will never be called when netif_running(bp->dev) is false. |
9925 | */ | |
9926 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
9927 | { | |
c9ee9206 | 9928 | bool global = false; |
7a752993 | 9929 | u32 error_recovered, error_unrecovered; |
95c6c616 | 9930 | bool is_parity; |
c9ee9206 | 9931 | |
72fd0718 VZ |
9932 | DP(NETIF_MSG_HW, "Handling parity\n"); |
9933 | while (1) { | |
9934 | switch (bp->recovery_state) { | |
9935 | case BNX2X_RECOVERY_INIT: | |
9936 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
95c6c616 AE |
9937 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
9938 | WARN_ON(!is_parity); | |
c9ee9206 | 9939 | |
72fd0718 | 9940 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
9941 | if (bnx2x_trylock_leader_lock(bp)) { |
9942 | bnx2x_set_reset_in_progress(bp); | |
9943 | /* | |
9944 | * Check if there is a global attention and if | |
9945 | * there was a global attention, set the global | |
9946 | * reset bit. | |
9947 | */ | |
9948 | ||
9949 | if (global) | |
9950 | bnx2x_set_reset_global(bp); | |
9951 | ||
72fd0718 | 9952 | bp->is_leader = 1; |
c9ee9206 | 9953 | } |
72fd0718 VZ |
9954 | |
9955 | /* Stop the driver */ | |
9956 | /* If interface has been removed - break */ | |
5d07d868 | 9957 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) |
72fd0718 VZ |
9958 | return; |
9959 | ||
9960 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 | 9961 | |
c9ee9206 VZ |
9962 | /* Ensure "is_leader", MCP command sequence and |
9963 | * "recovery_state" update values are seen on other | |
9964 | * CPUs. | |
72fd0718 | 9965 | */ |
c9ee9206 | 9966 | smp_mb(); |
72fd0718 VZ |
9967 | break; |
9968 | ||
9969 | case BNX2X_RECOVERY_WAIT: | |
9970 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
9971 | if (bp->is_leader) { | |
c9ee9206 | 9972 | int other_engine = BP_PATH(bp) ? 0 : 1; |
889b9af3 AE |
9973 | bool other_load_status = |
9974 | bnx2x_get_load_status(bp, other_engine); | |
9975 | bool load_status = | |
9976 | bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
9977 | global = bnx2x_reset_is_global(bp); |
9978 | ||
9979 | /* | |
9980 | * In case of a parity in a global block, let | |
9981 | * the first leader that performs a | |
9982 | * leader_reset() reset the global blocks in | |
9983 | * order to clear global attentions. Otherwise | |
16a5fd92 | 9984 | * the gates will remain closed for that |
c9ee9206 VZ |
9985 | * engine. |
9986 | */ | |
889b9af3 AE |
9987 | if (load_status || |
9988 | (global && other_load_status)) { | |
72fd0718 VZ |
9989 | /* Wait until all other functions get |
9990 | * down. | |
9991 | */ | |
7be08a72 | 9992 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9993 | HZ/10); |
9994 | return; | |
9995 | } else { | |
9996 | /* If all other functions got down - | |
9997 | * try to bring the chip back to | |
9998 | * normal. In any case it's an exit | |
9999 | * point for a leader. | |
10000 | */ | |
c9ee9206 VZ |
10001 | if (bnx2x_leader_reset(bp)) { |
10002 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
10003 | return; |
10004 | } | |
10005 | ||
c9ee9206 VZ |
10006 | /* If we are here, means that the |
10007 | * leader has succeeded and doesn't | |
10008 | * want to be a leader any more. Try | |
10009 | * to continue as a none-leader. | |
10010 | */ | |
10011 | break; | |
72fd0718 VZ |
10012 | } |
10013 | } else { /* non-leader */ | |
c9ee9206 | 10014 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
10015 | /* Try to get a LEADER_LOCK HW lock as |
10016 | * long as a former leader may have | |
10017 | * been unloaded by the user or | |
10018 | * released a leadership by another | |
10019 | * reason. | |
10020 | */ | |
c9ee9206 | 10021 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
10022 | /* I'm a leader now! Restart a |
10023 | * switch case. | |
10024 | */ | |
10025 | bp->is_leader = 1; | |
10026 | break; | |
10027 | } | |
10028 | ||
7be08a72 | 10029 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
10030 | HZ/10); |
10031 | return; | |
10032 | ||
c9ee9206 VZ |
10033 | } else { |
10034 | /* | |
10035 | * If there was a global attention, wait | |
10036 | * for it to be cleared. | |
10037 | */ | |
10038 | if (bnx2x_reset_is_global(bp)) { | |
10039 | schedule_delayed_work( | |
7be08a72 AE |
10040 | &bp->sp_rtnl_task, |
10041 | HZ/10); | |
c9ee9206 VZ |
10042 | return; |
10043 | } | |
10044 | ||
7a752993 AE |
10045 | error_recovered = |
10046 | bp->eth_stats.recoverable_error; | |
10047 | error_unrecovered = | |
10048 | bp->eth_stats.unrecoverable_error; | |
95c6c616 AE |
10049 | bp->recovery_state = |
10050 | BNX2X_RECOVERY_NIC_LOADING; | |
10051 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { | |
7a752993 | 10052 | error_unrecovered++; |
95c6c616 | 10053 | netdev_err(bp->dev, |
51c1a580 | 10054 | "Recovery failed. Power cycle needed\n"); |
95c6c616 AE |
10055 | /* Disconnect this device */ |
10056 | netif_device_detach(bp->dev); | |
10057 | /* Shut down the power */ | |
10058 | bnx2x_set_power_state( | |
10059 | bp, PCI_D3hot); | |
10060 | smp_mb(); | |
10061 | } else { | |
c9ee9206 VZ |
10062 | bp->recovery_state = |
10063 | BNX2X_RECOVERY_DONE; | |
7a752993 | 10064 | error_recovered++; |
c9ee9206 VZ |
10065 | smp_mb(); |
10066 | } | |
7a752993 AE |
10067 | bp->eth_stats.recoverable_error = |
10068 | error_recovered; | |
10069 | bp->eth_stats.unrecoverable_error = | |
10070 | error_unrecovered; | |
c9ee9206 | 10071 | |
72fd0718 VZ |
10072 | return; |
10073 | } | |
10074 | } | |
10075 | default: | |
10076 | return; | |
10077 | } | |
10078 | } | |
10079 | } | |
10080 | ||
883ce97d YM |
10081 | #if defined(CONFIG_BNX2X_VXLAN) || IS_ENABLED(CONFIG_GENEVE) |
10082 | static int bnx2x_udp_port_update(struct bnx2x *bp) | |
f34fa14c RB |
10083 | { |
10084 | struct bnx2x_func_switch_update_params *switch_update_params; | |
10085 | struct bnx2x_func_state_params func_params = {NULL}; | |
883ce97d YM |
10086 | struct bnx2x_udp_tunnel *udp_tunnel; |
10087 | u16 vxlan_port = 0, geneve_port = 0; | |
f34fa14c RB |
10088 | int rc; |
10089 | ||
10090 | switch_update_params = &func_params.params.switch_update; | |
10091 | ||
10092 | /* Prepare parameters for function state transitions */ | |
10093 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
10094 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
10095 | ||
10096 | func_params.f_obj = &bp->func_obj; | |
10097 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
10098 | ||
10099 | /* Function parameters */ | |
10100 | __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG, | |
10101 | &switch_update_params->changes); | |
883ce97d YM |
10102 | |
10103 | if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) { | |
10104 | udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]; | |
10105 | geneve_port = udp_tunnel->dst_port; | |
10106 | switch_update_params->geneve_dst_port = geneve_port; | |
10107 | } | |
10108 | ||
10109 | if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) { | |
10110 | udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]; | |
10111 | vxlan_port = udp_tunnel->dst_port; | |
10112 | switch_update_params->vxlan_dst_port = vxlan_port; | |
10113 | } | |
10114 | ||
10115 | /* Re-enable inner-rss for the offloaded UDP tunnels */ | |
10116 | __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS, | |
10117 | &switch_update_params->changes); | |
10118 | ||
f34fa14c RB |
10119 | rc = bnx2x_func_state_change(bp, &func_params); |
10120 | if (rc) | |
883ce97d YM |
10121 | BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n", |
10122 | vxlan_port, geneve_port, rc); | |
10123 | else | |
10124 | DP(BNX2X_MSG_SP, | |
10125 | "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n", | |
10126 | vxlan_port, geneve_port); | |
10127 | ||
f34fa14c RB |
10128 | return rc; |
10129 | } | |
10130 | ||
883ce97d YM |
10131 | static void __bnx2x_add_udp_port(struct bnx2x *bp, u16 port, |
10132 | enum bnx2x_udp_port_type type) | |
f34fa14c | 10133 | { |
883ce97d YM |
10134 | struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type]; |
10135 | ||
10136 | if (!netif_running(bp->dev) || !IS_PF(bp)) | |
10137 | return; | |
10138 | ||
10139 | if (udp_port->count && udp_port->dst_port == port) { | |
10140 | udp_port->count++; | |
f34fa14c | 10141 | return; |
883ce97d | 10142 | } |
f34fa14c | 10143 | |
883ce97d YM |
10144 | if (udp_port->count) { |
10145 | DP(BNX2X_MSG_SP, | |
10146 | "UDP tunnel [%d] - destination port limit reached\n", | |
10147 | type); | |
ac7eccd4 JB |
10148 | return; |
10149 | } | |
10150 | ||
883ce97d YM |
10151 | udp_port->dst_port = port; |
10152 | udp_port->count = 1; | |
10153 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0); | |
10154 | } | |
10155 | ||
10156 | static void __bnx2x_del_udp_port(struct bnx2x *bp, u16 port, | |
10157 | enum bnx2x_udp_port_type type) | |
10158 | { | |
10159 | struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type]; | |
10160 | ||
10161 | if (!IS_PF(bp)) | |
10162 | return; | |
10163 | ||
10164 | if (!udp_port->count || udp_port->dst_port != port) { | |
10165 | DP(BNX2X_MSG_SP, "Invalid UDP tunnel [%d] port\n", | |
10166 | type); | |
f34fa14c RB |
10167 | return; |
10168 | } | |
10169 | ||
883ce97d YM |
10170 | /* Remove reference, and make certain it's no longer in use */ |
10171 | udp_port->count--; | |
10172 | if (udp_port->count) | |
10173 | return; | |
10174 | udp_port->dst_port = 0; | |
10175 | ||
10176 | if (netif_running(bp->dev)) | |
10177 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0); | |
10178 | else | |
10179 | DP(BNX2X_MSG_SP, "Deleted UDP tunnel [%d] port %d\n", | |
10180 | type, port); | |
f34fa14c | 10181 | } |
883ce97d | 10182 | #endif |
f34fa14c | 10183 | |
883ce97d | 10184 | #ifdef CONFIG_BNX2X_VXLAN |
f34fa14c RB |
10185 | static void bnx2x_add_vxlan_port(struct net_device *netdev, |
10186 | sa_family_t sa_family, __be16 port) | |
10187 | { | |
10188 | struct bnx2x *bp = netdev_priv(netdev); | |
10189 | u16 t_port = ntohs(port); | |
10190 | ||
883ce97d | 10191 | __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN); |
f34fa14c RB |
10192 | } |
10193 | ||
883ce97d YM |
10194 | static void bnx2x_del_vxlan_port(struct net_device *netdev, |
10195 | sa_family_t sa_family, __be16 port) | |
f34fa14c | 10196 | { |
883ce97d YM |
10197 | struct bnx2x *bp = netdev_priv(netdev); |
10198 | u16 t_port = ntohs(port); | |
f34fa14c | 10199 | |
883ce97d YM |
10200 | __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN); |
10201 | } | |
10202 | #endif | |
10203 | ||
10204 | #if IS_ENABLED(CONFIG_GENEVE) | |
10205 | static void bnx2x_add_geneve_port(struct net_device *netdev, | |
10206 | sa_family_t sa_family, __be16 port) | |
10207 | { | |
10208 | struct bnx2x *bp = netdev_priv(netdev); | |
10209 | u16 t_port = ntohs(port); | |
10210 | ||
10211 | __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE); | |
f34fa14c RB |
10212 | } |
10213 | ||
883ce97d YM |
10214 | static void bnx2x_del_geneve_port(struct net_device *netdev, |
10215 | sa_family_t sa_family, __be16 port) | |
f34fa14c RB |
10216 | { |
10217 | struct bnx2x *bp = netdev_priv(netdev); | |
10218 | u16 t_port = ntohs(port); | |
10219 | ||
883ce97d | 10220 | __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE); |
f34fa14c RB |
10221 | } |
10222 | #endif | |
10223 | ||
56ad3152 MS |
10224 | static int bnx2x_close(struct net_device *dev); |
10225 | ||
72fd0718 VZ |
10226 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
10227 | * scheduled on a general queue in order to prevent a dead lock. | |
10228 | */ | |
7be08a72 | 10229 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 10230 | { |
7be08a72 | 10231 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
10232 | |
10233 | rtnl_lock(); | |
10234 | ||
8395be5e AE |
10235 | if (!netif_running(bp->dev)) { |
10236 | rtnl_unlock(); | |
10237 | return; | |
10238 | } | |
7be08a72 | 10239 | |
6bf07b8e | 10240 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
7be08a72 | 10241 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e YM |
10242 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
10243 | "you will need to reboot when done\n"); | |
10244 | goto sp_rtnl_not_reset; | |
7be08a72 | 10245 | #endif |
7be08a72 | 10246 | /* |
b1fb8740 VZ |
10247 | * Clear all pending SP commands as we are going to reset the |
10248 | * function anyway. | |
7be08a72 | 10249 | */ |
b1fb8740 VZ |
10250 | bp->sp_rtnl_state = 0; |
10251 | smp_mb(); | |
10252 | ||
72fd0718 | 10253 | bnx2x_parity_recover(bp); |
b1fb8740 | 10254 | |
8395be5e AE |
10255 | rtnl_unlock(); |
10256 | return; | |
b1fb8740 VZ |
10257 | } |
10258 | ||
10259 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
6bf07b8e YM |
10260 | #ifdef BNX2X_STOP_ON_ERROR |
10261 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" | |
10262 | "you will need to reboot when done\n"); | |
10263 | goto sp_rtnl_not_reset; | |
10264 | #endif | |
10265 | ||
b1fb8740 VZ |
10266 | /* |
10267 | * Clear all pending SP commands as we are going to reset the | |
10268 | * function anyway. | |
10269 | */ | |
10270 | bp->sp_rtnl_state = 0; | |
10271 | smp_mb(); | |
10272 | ||
5d07d868 | 10273 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); |
72fd0718 | 10274 | bnx2x_nic_load(bp, LOAD_NORMAL); |
b1fb8740 | 10275 | |
8395be5e AE |
10276 | rtnl_unlock(); |
10277 | return; | |
72fd0718 | 10278 | } |
b1fb8740 VZ |
10279 | #ifdef BNX2X_STOP_ON_ERROR |
10280 | sp_rtnl_not_reset: | |
10281 | #endif | |
10282 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
10283 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
a3348722 BW |
10284 | if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) |
10285 | bnx2x_after_function_update(bp); | |
8304859a AE |
10286 | /* |
10287 | * in case of fan failure we need to reset id if the "stop on error" | |
10288 | * debug flag is set, since we trying to prevent permanent overheating | |
10289 | * damage | |
10290 | */ | |
10291 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { | |
51c1a580 | 10292 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
8304859a AE |
10293 | netif_device_detach(bp->dev); |
10294 | bnx2x_close(bp->dev); | |
8395be5e AE |
10295 | rtnl_unlock(); |
10296 | return; | |
8304859a AE |
10297 | } |
10298 | ||
381ac16b AE |
10299 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { |
10300 | DP(BNX2X_MSG_SP, | |
10301 | "sending set mcast vf pf channel message from rtnl sp-task\n"); | |
10302 | bnx2x_vfpf_set_mcast(bp->dev); | |
10303 | } | |
78c3bcc5 AE |
10304 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, |
10305 | &bp->sp_rtnl_state)){ | |
10306 | if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) { | |
10307 | bnx2x_tx_disable(bp); | |
10308 | BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n"); | |
10309 | } | |
10310 | } | |
381ac16b | 10311 | |
8b09be5f YM |
10312 | if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { |
10313 | DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n"); | |
10314 | bnx2x_set_rx_mode_inner(bp); | |
381ac16b AE |
10315 | } |
10316 | ||
3ec9f9ca AE |
10317 | if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, |
10318 | &bp->sp_rtnl_state)) | |
10319 | bnx2x_pf_set_vfs_vlan(bp); | |
10320 | ||
6ffa39f2 | 10321 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) { |
07b4eb3b | 10322 | bnx2x_dcbx_stop_hw_tx(bp); |
07b4eb3b | 10323 | bnx2x_dcbx_resume_hw_tx(bp); |
6ffa39f2 | 10324 | } |
07b4eb3b | 10325 | |
42f8277f YM |
10326 | if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION, |
10327 | &bp->sp_rtnl_state)) | |
10328 | bnx2x_update_mng_version(bp); | |
10329 | ||
883ce97d YM |
10330 | #if defined(CONFIG_BNX2X_VXLAN) || IS_ENABLED(CONFIG_GENEVE) |
10331 | if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT, | |
f34fa14c | 10332 | &bp->sp_rtnl_state)) { |
883ce97d YM |
10333 | if (bnx2x_udp_port_update(bp)) { |
10334 | /* On error, forget configuration */ | |
10335 | memset(bp->udp_tunnel_ports, 0, | |
10336 | sizeof(struct bnx2x_udp_tunnel) * | |
10337 | BNX2X_UDP_PORT_MAX); | |
10338 | } else { | |
10339 | /* Since we don't store additional port information, | |
10340 | * if no port is configured for any feature ask for | |
10341 | * information about currently configured ports. | |
10342 | */ | |
10343 | #ifdef CONFIG_BNX2X_VXLAN | |
10344 | if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) | |
10345 | vxlan_get_rx_port(bp->dev); | |
10346 | #endif | |
10347 | #if IS_ENABLED(CONFIG_GENEVE) | |
10348 | if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) | |
10349 | geneve_get_rx_port(bp->dev); | |
10350 | #endif | |
f34fa14c RB |
10351 | } |
10352 | } | |
10353 | #endif | |
10354 | ||
8395be5e AE |
10355 | /* work which needs rtnl lock not-taken (as it takes the lock itself and |
10356 | * can be called from other contexts as well) | |
10357 | */ | |
34f80b04 | 10358 | rtnl_unlock(); |
8395be5e | 10359 | |
6411280a | 10360 | /* enable SR-IOV if applicable */ |
8395be5e | 10361 | if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, |
3c76feff AE |
10362 | &bp->sp_rtnl_state)) { |
10363 | bnx2x_disable_sriov(bp); | |
6411280a | 10364 | bnx2x_enable_sriov(bp); |
3c76feff | 10365 | } |
34f80b04 EG |
10366 | } |
10367 | ||
3deb8167 YR |
10368 | static void bnx2x_period_task(struct work_struct *work) |
10369 | { | |
10370 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
10371 | ||
10372 | if (!netif_running(bp->dev)) | |
10373 | goto period_task_exit; | |
10374 | ||
10375 | if (CHIP_REV_IS_SLOW(bp)) { | |
10376 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
10377 | goto period_task_exit; | |
10378 | } | |
10379 | ||
10380 | bnx2x_acquire_phy_lock(bp); | |
10381 | /* | |
10382 | * The barrier is needed to ensure the ordering between the writing to | |
10383 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
10384 | * the reading here. | |
10385 | */ | |
10386 | smp_mb(); | |
10387 | if (bp->port.pmf) { | |
10388 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
10389 | ||
10390 | /* Re-queue task in 1 sec */ | |
10391 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
10392 | } | |
10393 | ||
10394 | bnx2x_release_phy_lock(bp); | |
10395 | period_task_exit: | |
10396 | return; | |
10397 | } | |
10398 | ||
a2fbb9ea ET |
10399 | /* |
10400 | * Init service functions | |
10401 | */ | |
10402 | ||
a8f47eb7 | 10403 | static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
10404 | { |
10405 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
10406 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
10407 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
10408 | } |
10409 | ||
3d6b7253 YM |
10410 | static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp, |
10411 | u8 port, u32 reset_reg, | |
10412 | struct bnx2x_mac_vals *vals) | |
10413 | { | |
10414 | u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; | |
10415 | u32 base_addr; | |
10416 | ||
10417 | if (!(mask & reset_reg)) | |
10418 | return false; | |
10419 | ||
10420 | BNX2X_DEV_INFO("Disable umac Rx %02x\n", port); | |
10421 | base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
10422 | vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG; | |
10423 | vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]); | |
10424 | REG_WR(bp, vals->umac_addr[port], 0); | |
10425 | ||
10426 | return true; | |
10427 | } | |
10428 | ||
1ef1d45a BW |
10429 | static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, |
10430 | struct bnx2x_mac_vals *vals) | |
34f80b04 | 10431 | { |
452427b0 YM |
10432 | u32 val, base_addr, offset, mask, reset_reg; |
10433 | bool mac_stopped = false; | |
10434 | u8 port = BP_PORT(bp); | |
34f80b04 | 10435 | |
1ef1d45a | 10436 | /* reset addresses as they also mark which values were changed */ |
3d6b7253 | 10437 | memset(vals, 0, sizeof(*vals)); |
1ef1d45a | 10438 | |
452427b0 | 10439 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
f16da43b | 10440 | |
452427b0 YM |
10441 | if (!CHIP_IS_E3(bp)) { |
10442 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
10443 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; | |
10444 | if ((mask & reset_reg) && val) { | |
10445 | u32 wb_data[2]; | |
10446 | BNX2X_DEV_INFO("Disable bmac Rx\n"); | |
10447 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM | |
10448 | : NIG_REG_INGRESS_BMAC0_MEM; | |
10449 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL | |
10450 | : BIGMAC_REGISTER_BMAC_CONTROL; | |
7a06a122 | 10451 | |
452427b0 YM |
10452 | /* |
10453 | * use rd/wr since we cannot use dmae. This is safe | |
10454 | * since MCP won't access the bus due to the request | |
10455 | * to unload, and no function on the path can be | |
10456 | * loaded at this time. | |
10457 | */ | |
10458 | wb_data[0] = REG_RD(bp, base_addr + offset); | |
10459 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); | |
1ef1d45a BW |
10460 | vals->bmac_addr = base_addr + offset; |
10461 | vals->bmac_val[0] = wb_data[0]; | |
10462 | vals->bmac_val[1] = wb_data[1]; | |
452427b0 | 10463 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
1ef1d45a BW |
10464 | REG_WR(bp, vals->bmac_addr, wb_data[0]); |
10465 | REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); | |
452427b0 YM |
10466 | } |
10467 | BNX2X_DEV_INFO("Disable emac Rx\n"); | |
1ef1d45a BW |
10468 | vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; |
10469 | vals->emac_val = REG_RD(bp, vals->emac_addr); | |
10470 | REG_WR(bp, vals->emac_addr, 0); | |
452427b0 YM |
10471 | mac_stopped = true; |
10472 | } else { | |
10473 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
10474 | BNX2X_DEV_INFO("Disable xmac Rx\n"); | |
10475 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
10476 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); | |
10477 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
10478 | val & ~(1 << 1)); | |
10479 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
10480 | val | (1 << 1)); | |
1ef1d45a BW |
10481 | vals->xmac_addr = base_addr + XMAC_REG_CTRL; |
10482 | vals->xmac_val = REG_RD(bp, vals->xmac_addr); | |
10483 | REG_WR(bp, vals->xmac_addr, 0); | |
452427b0 YM |
10484 | mac_stopped = true; |
10485 | } | |
3d6b7253 YM |
10486 | |
10487 | mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0, | |
10488 | reset_reg, vals); | |
10489 | mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1, | |
10490 | reset_reg, vals); | |
452427b0 YM |
10491 | } |
10492 | ||
10493 | if (mac_stopped) | |
10494 | msleep(20); | |
452427b0 YM |
10495 | } |
10496 | ||
10497 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) | |
7c3afd85 YM |
10498 | #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \ |
10499 | 0x1848 + ((f) << 4)) | |
452427b0 YM |
10500 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) |
10501 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) | |
10502 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) | |
10503 | ||
91ebb929 YM |
10504 | #define BCM_5710_UNDI_FW_MF_MAJOR (0x07) |
10505 | #define BCM_5710_UNDI_FW_MF_MINOR (0x08) | |
10506 | #define BCM_5710_UNDI_FW_MF_VERS (0x05) | |
b17b0ca1 YM |
10507 | |
10508 | static bool bnx2x_prev_is_after_undi(struct bnx2x *bp) | |
10509 | { | |
10510 | /* UNDI marks its presence in DORQ - | |
10511 | * it initializes CID offset for normal bell to 0x7 | |
10512 | */ | |
10513 | if (!(REG_RD(bp, MISC_REG_RESET_REG_1) & | |
10514 | MISC_REGISTERS_RESET_REG_1_RST_DORQ)) | |
10515 | return false; | |
10516 | ||
10517 | if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) { | |
10518 | BNX2X_DEV_INFO("UNDI previously loaded\n"); | |
10519 | return true; | |
10520 | } | |
10521 | ||
10522 | return false; | |
10523 | } | |
10524 | ||
7c3afd85 | 10525 | static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc) |
452427b0 YM |
10526 | { |
10527 | u16 rcq, bd; | |
7c3afd85 | 10528 | u32 addr, tmp_reg; |
452427b0 | 10529 | |
7c3afd85 YM |
10530 | if (BP_FUNC(bp) < 2) |
10531 | addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp)); | |
10532 | else | |
10533 | addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2); | |
10534 | ||
10535 | tmp_reg = REG_RD(bp, addr); | |
452427b0 YM |
10536 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; |
10537 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; | |
10538 | ||
10539 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); | |
7c3afd85 | 10540 | REG_WR(bp, addr, tmp_reg); |
452427b0 | 10541 | |
7c3afd85 YM |
10542 | BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n", |
10543 | BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq); | |
452427b0 YM |
10544 | } |
10545 | ||
0329aba1 | 10546 | static int bnx2x_prev_mcp_done(struct bnx2x *bp) |
452427b0 | 10547 | { |
5d07d868 YM |
10548 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, |
10549 | DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); | |
452427b0 YM |
10550 | if (!rc) { |
10551 | BNX2X_ERR("MCP response failure, aborting\n"); | |
10552 | return -EBUSY; | |
10553 | } | |
10554 | ||
10555 | return 0; | |
10556 | } | |
10557 | ||
c63da990 BW |
10558 | static struct bnx2x_prev_path_list * |
10559 | bnx2x_prev_path_get_entry(struct bnx2x *bp) | |
10560 | { | |
10561 | struct bnx2x_prev_path_list *tmp_list; | |
10562 | ||
10563 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) | |
10564 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
10565 | bp->pdev->bus->number == tmp_list->bus && | |
10566 | BP_PATH(bp) == tmp_list->path) | |
10567 | return tmp_list; | |
10568 | ||
10569 | return NULL; | |
10570 | } | |
10571 | ||
7fa6f340 YM |
10572 | static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) |
10573 | { | |
10574 | struct bnx2x_prev_path_list *tmp_list; | |
10575 | int rc; | |
10576 | ||
10577 | rc = down_interruptible(&bnx2x_prev_sem); | |
10578 | if (rc) { | |
10579 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
10580 | return rc; | |
10581 | } | |
10582 | ||
10583 | tmp_list = bnx2x_prev_path_get_entry(bp); | |
10584 | if (tmp_list) { | |
10585 | tmp_list->aer = 1; | |
10586 | rc = 0; | |
10587 | } else { | |
10588 | BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n", | |
10589 | BP_PATH(bp)); | |
10590 | } | |
10591 | ||
10592 | up(&bnx2x_prev_sem); | |
10593 | ||
10594 | return rc; | |
10595 | } | |
10596 | ||
0329aba1 | 10597 | static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) |
452427b0 YM |
10598 | { |
10599 | struct bnx2x_prev_path_list *tmp_list; | |
b85d717c | 10600 | bool rc = false; |
452427b0 YM |
10601 | |
10602 | if (down_trylock(&bnx2x_prev_sem)) | |
10603 | return false; | |
10604 | ||
7fa6f340 YM |
10605 | tmp_list = bnx2x_prev_path_get_entry(bp); |
10606 | if (tmp_list) { | |
10607 | if (tmp_list->aer) { | |
10608 | DP(NETIF_MSG_HW, "Path %d was marked by AER\n", | |
10609 | BP_PATH(bp)); | |
10610 | } else { | |
452427b0 YM |
10611 | rc = true; |
10612 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | |
10613 | BP_PATH(bp)); | |
452427b0 YM |
10614 | } |
10615 | } | |
10616 | ||
10617 | up(&bnx2x_prev_sem); | |
10618 | ||
10619 | return rc; | |
10620 | } | |
10621 | ||
178135c1 DK |
10622 | bool bnx2x_port_after_undi(struct bnx2x *bp) |
10623 | { | |
10624 | struct bnx2x_prev_path_list *entry; | |
10625 | bool val; | |
10626 | ||
10627 | down(&bnx2x_prev_sem); | |
10628 | ||
10629 | entry = bnx2x_prev_path_get_entry(bp); | |
10630 | val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); | |
10631 | ||
10632 | up(&bnx2x_prev_sem); | |
10633 | ||
10634 | return val; | |
10635 | } | |
10636 | ||
c63da990 | 10637 | static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) |
452427b0 YM |
10638 | { |
10639 | struct bnx2x_prev_path_list *tmp_list; | |
10640 | int rc; | |
10641 | ||
7fa6f340 YM |
10642 | rc = down_interruptible(&bnx2x_prev_sem); |
10643 | if (rc) { | |
10644 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
10645 | return rc; | |
10646 | } | |
10647 | ||
10648 | /* Check whether the entry for this path already exists */ | |
10649 | tmp_list = bnx2x_prev_path_get_entry(bp); | |
10650 | if (tmp_list) { | |
10651 | if (!tmp_list->aer) { | |
10652 | BNX2X_ERR("Re-Marking the path.\n"); | |
10653 | } else { | |
10654 | DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", | |
10655 | BP_PATH(bp)); | |
10656 | tmp_list->aer = 0; | |
10657 | } | |
10658 | up(&bnx2x_prev_sem); | |
10659 | return 0; | |
10660 | } | |
10661 | up(&bnx2x_prev_sem); | |
10662 | ||
10663 | /* Create an entry for this path and add it */ | |
ea4b3857 | 10664 | tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); |
452427b0 YM |
10665 | if (!tmp_list) { |
10666 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | |
10667 | return -ENOMEM; | |
10668 | } | |
10669 | ||
10670 | tmp_list->bus = bp->pdev->bus->number; | |
10671 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | |
10672 | tmp_list->path = BP_PATH(bp); | |
7fa6f340 | 10673 | tmp_list->aer = 0; |
c63da990 | 10674 | tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; |
452427b0 YM |
10675 | |
10676 | rc = down_interruptible(&bnx2x_prev_sem); | |
10677 | if (rc) { | |
10678 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
10679 | kfree(tmp_list); | |
10680 | } else { | |
7fa6f340 YM |
10681 | DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", |
10682 | BP_PATH(bp)); | |
452427b0 YM |
10683 | list_add(&tmp_list->list, &bnx2x_prev_list); |
10684 | up(&bnx2x_prev_sem); | |
10685 | } | |
10686 | ||
10687 | return rc; | |
10688 | } | |
10689 | ||
0329aba1 | 10690 | static int bnx2x_do_flr(struct bnx2x *bp) |
452427b0 | 10691 | { |
452427b0 YM |
10692 | struct pci_dev *dev = bp->pdev; |
10693 | ||
8eee694c YM |
10694 | if (CHIP_IS_E1x(bp)) { |
10695 | BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); | |
10696 | return -EINVAL; | |
10697 | } | |
10698 | ||
10699 | /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ | |
10700 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | |
10701 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | |
10702 | bp->common.bc_ver); | |
10703 | return -EINVAL; | |
10704 | } | |
452427b0 | 10705 | |
8903b9eb CL |
10706 | if (!pci_wait_for_pending_transaction(dev)) |
10707 | dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); | |
452427b0 | 10708 | |
8eee694c | 10709 | BNX2X_DEV_INFO("Initiating FLR\n"); |
452427b0 YM |
10710 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); |
10711 | ||
10712 | return 0; | |
10713 | } | |
10714 | ||
0329aba1 | 10715 | static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) |
452427b0 YM |
10716 | { |
10717 | int rc; | |
10718 | ||
10719 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); | |
10720 | ||
10721 | /* Test if previous unload process was already finished for this path */ | |
10722 | if (bnx2x_prev_is_path_marked(bp)) | |
10723 | return bnx2x_prev_mcp_done(bp); | |
10724 | ||
04c46736 YM |
10725 | BNX2X_DEV_INFO("Path is unmarked\n"); |
10726 | ||
b17b0ca1 YM |
10727 | /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */ |
10728 | if (bnx2x_prev_is_after_undi(bp)) | |
10729 | goto out; | |
10730 | ||
452427b0 YM |
10731 | /* If function has FLR capabilities, and existing FW version matches |
10732 | * the one required, then FLR will be sufficient to clean any residue | |
10733 | * left by previous driver | |
10734 | */ | |
91ebb929 | 10735 | rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false); |
8eee694c YM |
10736 | |
10737 | if (!rc) { | |
10738 | /* fw version is good */ | |
10739 | BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); | |
10740 | rc = bnx2x_do_flr(bp); | |
10741 | } | |
10742 | ||
10743 | if (!rc) { | |
10744 | /* FLR was performed */ | |
10745 | BNX2X_DEV_INFO("FLR successful\n"); | |
10746 | return 0; | |
10747 | } | |
10748 | ||
10749 | BNX2X_DEV_INFO("Could not FLR\n"); | |
452427b0 | 10750 | |
b17b0ca1 | 10751 | out: |
452427b0 YM |
10752 | /* Close the MCP request, return failure*/ |
10753 | rc = bnx2x_prev_mcp_done(bp); | |
10754 | if (!rc) | |
10755 | rc = BNX2X_PREV_WAIT_NEEDED; | |
10756 | ||
10757 | return rc; | |
10758 | } | |
10759 | ||
0329aba1 | 10760 | static int bnx2x_prev_unload_common(struct bnx2x *bp) |
452427b0 YM |
10761 | { |
10762 | u32 reset_reg, tmp_reg = 0, rc; | |
c63da990 | 10763 | bool prev_undi = false; |
1ef1d45a BW |
10764 | struct bnx2x_mac_vals mac_vals; |
10765 | ||
452427b0 YM |
10766 | /* It is possible a previous function received 'common' answer, |
10767 | * but hasn't loaded yet, therefore creating a scenario of | |
10768 | * multiple functions receiving 'common' on the same path. | |
10769 | */ | |
10770 | BNX2X_DEV_INFO("Common unload Flow\n"); | |
10771 | ||
1ef1d45a BW |
10772 | memset(&mac_vals, 0, sizeof(mac_vals)); |
10773 | ||
452427b0 YM |
10774 | if (bnx2x_prev_is_path_marked(bp)) |
10775 | return bnx2x_prev_mcp_done(bp); | |
10776 | ||
10777 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); | |
10778 | ||
10779 | /* Reset should be performed after BRB is emptied */ | |
10780 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { | |
10781 | u32 timer_count = 1000; | |
452427b0 YM |
10782 | |
10783 | /* Close the MAC Rx to prevent BRB from filling up */ | |
1ef1d45a BW |
10784 | bnx2x_prev_unload_close_mac(bp, &mac_vals); |
10785 | ||
3d6b7253 | 10786 | /* close LLH filters for both ports towards the BRB */ |
1ef1d45a | 10787 | bnx2x_set_rx_filter(&bp->link_params, 0); |
3d6b7253 | 10788 | bp->link_params.port ^= 1; |
1ef1d45a | 10789 | bnx2x_set_rx_filter(&bp->link_params, 0); |
3d6b7253 | 10790 | bp->link_params.port ^= 1; |
452427b0 | 10791 | |
b17b0ca1 YM |
10792 | /* Check if the UNDI driver was previously loaded */ |
10793 | if (bnx2x_prev_is_after_undi(bp)) { | |
10794 | prev_undi = true; | |
10795 | /* clear the UNDI indication */ | |
10796 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
10797 | /* clear possible idle check errors */ | |
10798 | REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); | |
452427b0 | 10799 | } |
d46f7c4d DK |
10800 | if (!CHIP_IS_E1x(bp)) |
10801 | /* block FW from writing to host */ | |
10802 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
10803 | ||
452427b0 YM |
10804 | /* wait until BRB is empty */ |
10805 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); | |
10806 | while (timer_count) { | |
10807 | u32 prev_brb = tmp_reg; | |
34f80b04 | 10808 | |
452427b0 YM |
10809 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
10810 | if (!tmp_reg) | |
10811 | break; | |
619c5cb6 | 10812 | |
452427b0 | 10813 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
619c5cb6 | 10814 | |
452427b0 YM |
10815 | /* reset timer as long as BRB actually gets emptied */ |
10816 | if (prev_brb > tmp_reg) | |
10817 | timer_count = 1000; | |
10818 | else | |
10819 | timer_count--; | |
da5a662a | 10820 | |
7c3afd85 YM |
10821 | /* If UNDI resides in memory, manually increment it */ |
10822 | if (prev_undi) | |
10823 | bnx2x_prev_unload_undi_inc(bp, 1); | |
10824 | ||
452427b0 | 10825 | udelay(10); |
7a06a122 | 10826 | } |
452427b0 YM |
10827 | |
10828 | if (!timer_count) | |
10829 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); | |
34f80b04 | 10830 | } |
f16da43b | 10831 | |
452427b0 YM |
10832 | /* No packets are in the pipeline, path is ready for reset */ |
10833 | bnx2x_reset_common(bp); | |
10834 | ||
1ef1d45a BW |
10835 | if (mac_vals.xmac_addr) |
10836 | REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); | |
3d6b7253 YM |
10837 | if (mac_vals.umac_addr[0]) |
10838 | REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); | |
10839 | if (mac_vals.umac_addr[1]) | |
10840 | REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); | |
1ef1d45a BW |
10841 | if (mac_vals.emac_addr) |
10842 | REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); | |
10843 | if (mac_vals.bmac_addr) { | |
10844 | REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); | |
10845 | REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); | |
10846 | } | |
10847 | ||
c63da990 | 10848 | rc = bnx2x_prev_mark_path(bp, prev_undi); |
452427b0 YM |
10849 | if (rc) { |
10850 | bnx2x_prev_mcp_done(bp); | |
10851 | return rc; | |
10852 | } | |
10853 | ||
10854 | return bnx2x_prev_mcp_done(bp); | |
10855 | } | |
10856 | ||
0329aba1 | 10857 | static int bnx2x_prev_unload(struct bnx2x *bp) |
452427b0 YM |
10858 | { |
10859 | int time_counter = 10; | |
10860 | u32 rc, fw, hw_lock_reg, hw_lock_val; | |
10861 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); | |
10862 | ||
24f06716 AE |
10863 | /* clear hw from errors which may have resulted from an interrupted |
10864 | * dmae transaction. | |
10865 | */ | |
da254fbc | 10866 | bnx2x_clean_pglue_errors(bp); |
24f06716 AE |
10867 | |
10868 | /* Release previously held locks */ | |
452427b0 YM |
10869 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? |
10870 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : | |
10871 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); | |
10872 | ||
3cdeec22 | 10873 | hw_lock_val = REG_RD(bp, hw_lock_reg); |
452427b0 YM |
10874 | if (hw_lock_val) { |
10875 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { | |
10876 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); | |
10877 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
10878 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); | |
10879 | } | |
10880 | ||
10881 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); | |
10882 | REG_WR(bp, hw_lock_reg, 0xffffffff); | |
10883 | } else | |
10884 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); | |
10885 | ||
10886 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { | |
10887 | BNX2X_DEV_INFO("Release previously held alr\n"); | |
3cdeec22 | 10888 | bnx2x_release_alr(bp); |
452427b0 YM |
10889 | } |
10890 | ||
452427b0 | 10891 | do { |
7fa6f340 | 10892 | int aer = 0; |
452427b0 YM |
10893 | /* Lock MCP using an unload request */ |
10894 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | |
10895 | if (!fw) { | |
10896 | BNX2X_ERR("MCP response failure, aborting\n"); | |
10897 | rc = -EBUSY; | |
10898 | break; | |
10899 | } | |
10900 | ||
7fa6f340 YM |
10901 | rc = down_interruptible(&bnx2x_prev_sem); |
10902 | if (rc) { | |
10903 | BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n", | |
10904 | rc); | |
10905 | } else { | |
10906 | /* If Path is marked by EEH, ignore unload status */ | |
10907 | aer = !!(bnx2x_prev_path_get_entry(bp) && | |
10908 | bnx2x_prev_path_get_entry(bp)->aer); | |
60cde81f | 10909 | up(&bnx2x_prev_sem); |
7fa6f340 | 10910 | } |
7fa6f340 YM |
10911 | |
10912 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) { | |
452427b0 YM |
10913 | rc = bnx2x_prev_unload_common(bp); |
10914 | break; | |
10915 | } | |
10916 | ||
16a5fd92 | 10917 | /* non-common reply from MCP might require looping */ |
452427b0 YM |
10918 | rc = bnx2x_prev_unload_uncommon(bp); |
10919 | if (rc != BNX2X_PREV_WAIT_NEEDED) | |
10920 | break; | |
10921 | ||
10922 | msleep(20); | |
10923 | } while (--time_counter); | |
10924 | ||
10925 | if (!time_counter || rc) { | |
91ebb929 YM |
10926 | BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n"); |
10927 | rc = -EPROBE_DEFER; | |
452427b0 YM |
10928 | } |
10929 | ||
c63da990 | 10930 | /* Mark function if its port was used to boot from SAN */ |
178135c1 | 10931 | if (bnx2x_port_after_undi(bp)) |
c63da990 BW |
10932 | bp->link_params.feature_config_flags |= |
10933 | FEATURE_CONFIG_BOOT_FROM_SAN; | |
10934 | ||
452427b0 YM |
10935 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); |
10936 | ||
10937 | return rc; | |
34f80b04 EG |
10938 | } |
10939 | ||
0329aba1 | 10940 | static void bnx2x_get_common_hwinfo(struct bnx2x *bp) |
34f80b04 | 10941 | { |
1d187b34 | 10942 | u32 val, val2, val3, val4, id, boot_mode; |
72ce58c3 | 10943 | u16 pmc; |
34f80b04 EG |
10944 | |
10945 | /* Get the chip revision id and number. */ | |
10946 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
10947 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
10948 | id = ((val & 0xffff) << 16); | |
10949 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
10950 | id |= ((val & 0xf) << 12); | |
f22fdf25 YM |
10951 | |
10952 | /* Metal is read from PCI regs, but we can't access >=0x400 from | |
10953 | * the configuration space (so we need to reg_rd) | |
10954 | */ | |
10955 | val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); | |
10956 | id |= (((val >> 24) & 0xf) << 4); | |
5a40e08e | 10957 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
10958 | id |= (val & 0xf); |
10959 | bp->common.chip_id = id; | |
523224a3 | 10960 | |
7e8e02df BW |
10961 | /* force 57811 according to MISC register */ |
10962 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { | |
10963 | if (CHIP_IS_57810(bp)) | |
10964 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | | |
10965 | (bp->common.chip_id & 0x0000FFFF); | |
10966 | else if (CHIP_IS_57810_MF(bp)) | |
10967 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | | |
10968 | (bp->common.chip_id & 0x0000FFFF); | |
10969 | bp->common.chip_id |= 0x1; | |
10970 | } | |
10971 | ||
523224a3 DK |
10972 | /* Set doorbell size */ |
10973 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
10974 | ||
619c5cb6 | 10975 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
10976 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
10977 | if ((val & 1) == 0) | |
10978 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
10979 | else | |
10980 | val = (val >> 1) & 1; | |
10981 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
10982 | "2_PORT_MODE"); | |
10983 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
10984 | CHIP_2_PORT_MODE; | |
10985 | ||
10986 | if (CHIP_MODE_IS_4_PORT(bp)) | |
10987 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
10988 | else | |
10989 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
10990 | } else { | |
10991 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
10992 | bp->pfid = bp->pf_num; /* 0..7 */ | |
10993 | } | |
10994 | ||
51c1a580 MS |
10995 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
10996 | ||
f2e0899f DK |
10997 | bp->link_params.chip_id = bp->common.chip_id; |
10998 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 10999 | |
1c06328c EG |
11000 | val = (REG_RD(bp, 0x2874) & 0x55); |
11001 | if ((bp->common.chip_id & 0x1) || | |
11002 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
11003 | bp->flags |= ONE_PORT_FLAG; | |
11004 | BNX2X_DEV_INFO("single port device\n"); | |
11005 | } | |
11006 | ||
34f80b04 | 11007 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 11008 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
11009 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
11010 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
11011 | bp->common.flash_size, bp->common.flash_size); | |
11012 | ||
1b6e2ceb DK |
11013 | bnx2x_init_shmem(bp); |
11014 | ||
f2e0899f DK |
11015 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
11016 | MISC_REG_GENERIC_CR_1 : | |
11017 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 11018 | |
34f80b04 | 11019 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 11020 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
b884d95b YR |
11021 | if (SHMEM2_RD(bp, size) > |
11022 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
11023 | bp->link_params.lfa_base = | |
11024 | REG_RD(bp, bp->common.shmem2_base + | |
11025 | (u32)offsetof(struct shmem2_region, | |
11026 | lfa_host_addr[BP_PORT(bp)])); | |
11027 | else | |
11028 | bp->link_params.lfa_base = 0; | |
2691d51d EG |
11029 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
11030 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 11031 | |
f2e0899f | 11032 | if (!bp->common.shmem_base) { |
34f80b04 EG |
11033 | BNX2X_DEV_INFO("MCP not active\n"); |
11034 | bp->flags |= NO_MCP_FLAG; | |
11035 | return; | |
11036 | } | |
11037 | ||
34f80b04 | 11038 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 11039 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
11040 | |
11041 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
11042 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
11043 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
11044 | ||
c2c8b03e EG |
11045 | bp->link_params.feature_config_flags = 0; |
11046 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
11047 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
11048 | bp->link_params.feature_config_flags |= | |
11049 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
11050 | else | |
11051 | bp->link_params.feature_config_flags &= | |
11052 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
11053 | ||
34f80b04 EG |
11054 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
11055 | bp->common.bc_ver = val; | |
11056 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
11057 | if (val < BNX2X_BC_VER) { | |
11058 | /* for now only warn | |
11059 | * later we might need to enforce this */ | |
51c1a580 MS |
11060 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
11061 | BNX2X_BC_VER, val); | |
34f80b04 | 11062 | } |
4d295db0 | 11063 | bp->link_params.feature_config_flags |= |
a22f0788 | 11064 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
11065 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
11066 | ||
a22f0788 YR |
11067 | bp->link_params.feature_config_flags |= |
11068 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
11069 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
a3348722 BW |
11070 | bp->link_params.feature_config_flags |= |
11071 | (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? | |
11072 | FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; | |
85242eea YR |
11073 | bp->link_params.feature_config_flags |= |
11074 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
11075 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
55386fe8 YR |
11076 | |
11077 | bp->link_params.feature_config_flags |= | |
11078 | (val >= REQ_BC_VER_4_MT_SUPPORTED) ? | |
11079 | FEATURE_CONFIG_MT_SUPPORT : 0; | |
11080 | ||
0e898dd7 BW |
11081 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
11082 | BC_SUPPORTS_PFC_STATS : 0; | |
85242eea | 11083 | |
2e499d3c BW |
11084 | bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? |
11085 | BC_SUPPORTS_FCOE_FEATURES : 0; | |
11086 | ||
9876879f BW |
11087 | bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? |
11088 | BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; | |
a6d3a5ba BW |
11089 | |
11090 | bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? | |
11091 | BC_SUPPORTS_RMMOD_CMD : 0; | |
11092 | ||
1d187b34 BW |
11093 | boot_mode = SHMEM_RD(bp, |
11094 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & | |
11095 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; | |
11096 | switch (boot_mode) { | |
11097 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: | |
11098 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; | |
11099 | break; | |
11100 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: | |
11101 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; | |
11102 | break; | |
11103 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: | |
11104 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; | |
11105 | break; | |
11106 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: | |
11107 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; | |
11108 | break; | |
11109 | } | |
11110 | ||
29ed74c3 | 11111 | pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc); |
f9a3ebbe DK |
11112 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; |
11113 | ||
72ce58c3 | 11114 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 11115 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
11116 | |
11117 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
11118 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
11119 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
11120 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
11121 | ||
cdaa7cb8 VZ |
11122 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
11123 | val, val2, val3, val4); | |
34f80b04 EG |
11124 | } |
11125 | ||
f2e0899f DK |
11126 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
11127 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
11128 | ||
0329aba1 | 11129 | static int bnx2x_get_igu_cam_info(struct bnx2x *bp) |
f2e0899f DK |
11130 | { |
11131 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
11132 | int igu_sb_id; |
11133 | u32 val; | |
6383c0b3 | 11134 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
11135 | |
11136 | bp->igu_base_sb = 0xff; | |
f2e0899f | 11137 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 11138 | int vn = BP_VN(bp); |
6383c0b3 | 11139 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
11140 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
11141 | FP_SB_MAX_E1x; | |
11142 | ||
11143 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
11144 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
11145 | ||
9b341bb1 | 11146 | return 0; |
f2e0899f DK |
11147 | } |
11148 | ||
11149 | /* IGU in normal mode - read CAM */ | |
11150 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
11151 | igu_sb_id++) { | |
11152 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
11153 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
11154 | continue; | |
11155 | fid = IGU_FID(val); | |
11156 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
11157 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
11158 | continue; | |
11159 | if (IGU_VEC(val) == 0) | |
11160 | /* default status block */ | |
11161 | bp->igu_dsb_id = igu_sb_id; | |
11162 | else { | |
11163 | if (bp->igu_base_sb == 0xff) | |
11164 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 11165 | igu_sb_cnt++; |
f2e0899f DK |
11166 | } |
11167 | } | |
11168 | } | |
619c5cb6 | 11169 | |
6383c0b3 | 11170 | #ifdef CONFIG_PCI_MSI |
185d4c8b AE |
11171 | /* Due to new PF resource allocation by MFW T7.4 and above, it's |
11172 | * optional that number of CAM entries will not be equal to the value | |
11173 | * advertised in PCI. | |
11174 | * Driver should use the minimal value of both as the actual status | |
11175 | * block count | |
619c5cb6 | 11176 | */ |
185d4c8b | 11177 | bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); |
6383c0b3 | 11178 | #endif |
619c5cb6 | 11179 | |
9b341bb1 | 11180 | if (igu_sb_cnt == 0) { |
f2e0899f | 11181 | BNX2X_ERR("CAM configuration error\n"); |
9b341bb1 BW |
11182 | return -EINVAL; |
11183 | } | |
11184 | ||
11185 | return 0; | |
f2e0899f DK |
11186 | } |
11187 | ||
1dd06ae8 | 11188 | static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) |
a2fbb9ea | 11189 | { |
a22f0788 YR |
11190 | int cfg_size = 0, idx, port = BP_PORT(bp); |
11191 | ||
11192 | /* Aggregation of supported attributes of all external phys */ | |
11193 | bp->port.supported[0] = 0; | |
11194 | bp->port.supported[1] = 0; | |
b7737c9b YR |
11195 | switch (bp->link_params.num_phys) { |
11196 | case 1: | |
a22f0788 YR |
11197 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
11198 | cfg_size = 1; | |
11199 | break; | |
b7737c9b | 11200 | case 2: |
a22f0788 YR |
11201 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
11202 | cfg_size = 1; | |
11203 | break; | |
11204 | case 3: | |
11205 | if (bp->link_params.multi_phy_config & | |
11206 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
11207 | bp->port.supported[1] = | |
11208 | bp->link_params.phy[EXT_PHY1].supported; | |
11209 | bp->port.supported[0] = | |
11210 | bp->link_params.phy[EXT_PHY2].supported; | |
11211 | } else { | |
11212 | bp->port.supported[0] = | |
11213 | bp->link_params.phy[EXT_PHY1].supported; | |
11214 | bp->port.supported[1] = | |
11215 | bp->link_params.phy[EXT_PHY2].supported; | |
11216 | } | |
11217 | cfg_size = 2; | |
11218 | break; | |
b7737c9b | 11219 | } |
a2fbb9ea | 11220 | |
a22f0788 | 11221 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
51c1a580 | 11222 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 11223 | SHMEM_RD(bp, |
a22f0788 YR |
11224 | dev_info.port_hw_config[port].external_phy_config), |
11225 | SHMEM_RD(bp, | |
11226 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 11227 | return; |
f85582f8 | 11228 | } |
a2fbb9ea | 11229 | |
619c5cb6 VZ |
11230 | if (CHIP_IS_E3(bp)) |
11231 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
11232 | else { | |
11233 | switch (switch_cfg) { | |
11234 | case SWITCH_CFG_1G: | |
11235 | bp->port.phy_addr = REG_RD( | |
11236 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
11237 | break; | |
11238 | case SWITCH_CFG_10G: | |
11239 | bp->port.phy_addr = REG_RD( | |
11240 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
11241 | break; | |
11242 | default: | |
11243 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
11244 | bp->port.link_config[0]); | |
11245 | return; | |
11246 | } | |
a2fbb9ea | 11247 | } |
619c5cb6 | 11248 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
11249 | /* mask what we support according to speed_cap_mask per configuration */ |
11250 | for (idx = 0; idx < cfg_size; idx++) { | |
11251 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 11252 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 11253 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 11254 | |
a22f0788 | 11255 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11256 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 11257 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 11258 | |
a22f0788 | 11259 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11260 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 11261 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 11262 | |
a22f0788 | 11263 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11264 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 11265 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 11266 | |
a22f0788 | 11267 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11268 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 11269 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 11270 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 11271 | |
a22f0788 | 11272 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11273 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 11274 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 11275 | |
a22f0788 | 11276 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11277 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 | 11278 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
b8e0d884 YR |
11279 | |
11280 | if (!(bp->link_params.speed_cap_mask[idx] & | |
11281 | PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) | |
11282 | bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; | |
a22f0788 | 11283 | } |
a2fbb9ea | 11284 | |
a22f0788 YR |
11285 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
11286 | bp->port.supported[1]); | |
a2fbb9ea ET |
11287 | } |
11288 | ||
0329aba1 | 11289 | static void bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 11290 | { |
a22f0788 YR |
11291 | u32 link_config, idx, cfg_size = 0; |
11292 | bp->port.advertising[0] = 0; | |
11293 | bp->port.advertising[1] = 0; | |
11294 | switch (bp->link_params.num_phys) { | |
11295 | case 1: | |
11296 | case 2: | |
11297 | cfg_size = 1; | |
11298 | break; | |
11299 | case 3: | |
11300 | cfg_size = 2; | |
11301 | break; | |
11302 | } | |
11303 | for (idx = 0; idx < cfg_size; idx++) { | |
11304 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
11305 | link_config = bp->port.link_config[idx]; | |
11306 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 11307 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
11308 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
11309 | bp->link_params.req_line_speed[idx] = | |
11310 | SPEED_AUTO_NEG; | |
11311 | bp->port.advertising[idx] |= | |
11312 | bp->port.supported[idx]; | |
10bd1f24 MY |
11313 | if (bp->link_params.phy[EXT_PHY1].type == |
11314 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
11315 | bp->port.advertising[idx] |= | |
11316 | (SUPPORTED_100baseT_Half | | |
11317 | SUPPORTED_100baseT_Full); | |
f85582f8 DK |
11318 | } else { |
11319 | /* force 10G, no AN */ | |
a22f0788 YR |
11320 | bp->link_params.req_line_speed[idx] = |
11321 | SPEED_10000; | |
11322 | bp->port.advertising[idx] |= | |
11323 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 11324 | ADVERTISED_FIBRE); |
a22f0788 | 11325 | continue; |
f85582f8 DK |
11326 | } |
11327 | break; | |
a2fbb9ea | 11328 | |
f85582f8 | 11329 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
11330 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
11331 | bp->link_params.req_line_speed[idx] = | |
11332 | SPEED_10; | |
11333 | bp->port.advertising[idx] |= | |
11334 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
11335 | ADVERTISED_TP); |
11336 | } else { | |
51c1a580 | 11337 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 | 11338 | link_config, |
a22f0788 | 11339 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
11340 | return; |
11341 | } | |
11342 | break; | |
a2fbb9ea | 11343 | |
f85582f8 | 11344 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
11345 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
11346 | bp->link_params.req_line_speed[idx] = | |
11347 | SPEED_10; | |
11348 | bp->link_params.req_duplex[idx] = | |
11349 | DUPLEX_HALF; | |
11350 | bp->port.advertising[idx] |= | |
11351 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
11352 | ADVERTISED_TP); |
11353 | } else { | |
51c1a580 | 11354 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
11355 | link_config, |
11356 | bp->link_params.speed_cap_mask[idx]); | |
11357 | return; | |
11358 | } | |
11359 | break; | |
a2fbb9ea | 11360 | |
f85582f8 DK |
11361 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
11362 | if (bp->port.supported[idx] & | |
11363 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
11364 | bp->link_params.req_line_speed[idx] = |
11365 | SPEED_100; | |
11366 | bp->port.advertising[idx] |= | |
11367 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
11368 | ADVERTISED_TP); |
11369 | } else { | |
51c1a580 | 11370 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
11371 | link_config, |
11372 | bp->link_params.speed_cap_mask[idx]); | |
11373 | return; | |
11374 | } | |
11375 | break; | |
a2fbb9ea | 11376 | |
f85582f8 DK |
11377 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
11378 | if (bp->port.supported[idx] & | |
11379 | SUPPORTED_100baseT_Half) { | |
11380 | bp->link_params.req_line_speed[idx] = | |
11381 | SPEED_100; | |
11382 | bp->link_params.req_duplex[idx] = | |
11383 | DUPLEX_HALF; | |
a22f0788 YR |
11384 | bp->port.advertising[idx] |= |
11385 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
11386 | ADVERTISED_TP); |
11387 | } else { | |
51c1a580 | 11388 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
11389 | link_config, |
11390 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
11391 | return; |
11392 | } | |
11393 | break; | |
a2fbb9ea | 11394 | |
f85582f8 | 11395 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
11396 | if (bp->port.supported[idx] & |
11397 | SUPPORTED_1000baseT_Full) { | |
11398 | bp->link_params.req_line_speed[idx] = | |
11399 | SPEED_1000; | |
11400 | bp->port.advertising[idx] |= | |
11401 | (ADVERTISED_1000baseT_Full | | |
f85582f8 | 11402 | ADVERTISED_TP); |
5d67c1c5 YM |
11403 | } else if (bp->port.supported[idx] & |
11404 | SUPPORTED_1000baseKX_Full) { | |
11405 | bp->link_params.req_line_speed[idx] = | |
11406 | SPEED_1000; | |
11407 | bp->port.advertising[idx] |= | |
11408 | ADVERTISED_1000baseKX_Full; | |
f85582f8 | 11409 | } else { |
51c1a580 | 11410 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
11411 | link_config, |
11412 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
11413 | return; |
11414 | } | |
11415 | break; | |
a2fbb9ea | 11416 | |
f85582f8 | 11417 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
11418 | if (bp->port.supported[idx] & |
11419 | SUPPORTED_2500baseX_Full) { | |
11420 | bp->link_params.req_line_speed[idx] = | |
11421 | SPEED_2500; | |
11422 | bp->port.advertising[idx] |= | |
11423 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 11424 | ADVERTISED_TP); |
f85582f8 | 11425 | } else { |
51c1a580 | 11426 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 11427 | link_config, |
f85582f8 DK |
11428 | bp->link_params.speed_cap_mask[idx]); |
11429 | return; | |
11430 | } | |
11431 | break; | |
a2fbb9ea | 11432 | |
f85582f8 | 11433 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
11434 | if (bp->port.supported[idx] & |
11435 | SUPPORTED_10000baseT_Full) { | |
11436 | bp->link_params.req_line_speed[idx] = | |
11437 | SPEED_10000; | |
11438 | bp->port.advertising[idx] |= | |
11439 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 11440 | ADVERTISED_FIBRE); |
5d67c1c5 YM |
11441 | } else if (bp->port.supported[idx] & |
11442 | SUPPORTED_10000baseKR_Full) { | |
11443 | bp->link_params.req_line_speed[idx] = | |
11444 | SPEED_10000; | |
11445 | bp->port.advertising[idx] |= | |
11446 | (ADVERTISED_10000baseKR_Full | | |
11447 | ADVERTISED_FIBRE); | |
f85582f8 | 11448 | } else { |
51c1a580 | 11449 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 11450 | link_config, |
f85582f8 DK |
11451 | bp->link_params.speed_cap_mask[idx]); |
11452 | return; | |
11453 | } | |
11454 | break; | |
3c9ada22 YR |
11455 | case PORT_FEATURE_LINK_SPEED_20G: |
11456 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 11457 | |
3c9ada22 | 11458 | break; |
f85582f8 | 11459 | default: |
51c1a580 | 11460 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
754a2f52 | 11461 | link_config); |
f85582f8 DK |
11462 | bp->link_params.req_line_speed[idx] = |
11463 | SPEED_AUTO_NEG; | |
11464 | bp->port.advertising[idx] = | |
11465 | bp->port.supported[idx]; | |
11466 | break; | |
11467 | } | |
a2fbb9ea | 11468 | |
a22f0788 | 11469 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 11470 | PORT_FEATURE_FLOW_CONTROL_MASK); |
cd1dfce2 YM |
11471 | if (bp->link_params.req_flow_ctrl[idx] == |
11472 | BNX2X_FLOW_CTRL_AUTO) { | |
11473 | if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) | |
11474 | bp->link_params.req_flow_ctrl[idx] = | |
11475 | BNX2X_FLOW_CTRL_NONE; | |
11476 | else | |
11477 | bnx2x_set_requested_fc(bp); | |
a22f0788 | 11478 | } |
a2fbb9ea | 11479 | |
51c1a580 | 11480 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
a22f0788 YR |
11481 | bp->link_params.req_line_speed[idx], |
11482 | bp->link_params.req_duplex[idx], | |
11483 | bp->link_params.req_flow_ctrl[idx], | |
11484 | bp->port.advertising[idx]); | |
11485 | } | |
a2fbb9ea ET |
11486 | } |
11487 | ||
0329aba1 | 11488 | static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
e665bfda | 11489 | { |
86564c3f YM |
11490 | __be16 mac_hi_be = cpu_to_be16(mac_hi); |
11491 | __be32 mac_lo_be = cpu_to_be32(mac_lo); | |
11492 | memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be)); | |
11493 | memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be)); | |
e665bfda MC |
11494 | } |
11495 | ||
0329aba1 | 11496 | static void bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 11497 | { |
34f80b04 | 11498 | int port = BP_PORT(bp); |
589abe3a | 11499 | u32 config; |
c8c60d88 | 11500 | u32 ext_phy_type, ext_phy_config, eee_mode; |
a2fbb9ea | 11501 | |
c18487ee | 11502 | bp->link_params.bp = bp; |
34f80b04 | 11503 | bp->link_params.port = port; |
c18487ee | 11504 | |
c18487ee | 11505 | bp->link_params.lane_config = |
a2fbb9ea | 11506 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 11507 | |
a22f0788 | 11508 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea | 11509 | SHMEM_RD(bp, |
b0261926 YR |
11510 | dev_info.port_hw_config[port].speed_capability_mask) & |
11511 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | |
a22f0788 YR |
11512 | bp->link_params.speed_cap_mask[1] = |
11513 | SHMEM_RD(bp, | |
b0261926 YR |
11514 | dev_info.port_hw_config[port].speed_capability_mask2) & |
11515 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | |
a22f0788 | 11516 | bp->port.link_config[0] = |
a2fbb9ea ET |
11517 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
11518 | ||
a22f0788 YR |
11519 | bp->port.link_config[1] = |
11520 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 11521 | |
a22f0788 YR |
11522 | bp->link_params.multi_phy_config = |
11523 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
11524 | /* If the device is capable of WoL, set the default state according |
11525 | * to the HW | |
11526 | */ | |
4d295db0 | 11527 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
11528 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
11529 | (config & PORT_FEATURE_WOL_ENABLED)); | |
11530 | ||
4ba7699b YM |
11531 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == |
11532 | PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) | |
11533 | bp->flags |= NO_ISCSI_FLAG; | |
11534 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == | |
11535 | PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) | |
11536 | bp->flags |= NO_FCOE_FLAG; | |
11537 | ||
51c1a580 | 11538 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 11539 | bp->link_params.lane_config, |
a22f0788 YR |
11540 | bp->link_params.speed_cap_mask[0], |
11541 | bp->port.link_config[0]); | |
a2fbb9ea | 11542 | |
a22f0788 | 11543 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 11544 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 11545 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 11546 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
11547 | |
11548 | bnx2x_link_settings_requested(bp); | |
11549 | ||
01cd4528 EG |
11550 | /* |
11551 | * If connected directly, work with the internal PHY, otherwise, work | |
11552 | * with the external PHY | |
11553 | */ | |
b7737c9b YR |
11554 | ext_phy_config = |
11555 | SHMEM_RD(bp, | |
11556 | dev_info.port_hw_config[port].external_phy_config); | |
11557 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 11558 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 11559 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
11560 | |
11561 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
11562 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
11563 | bp->mdio.prtad = | |
b7737c9b | 11564 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d | 11565 | |
c8c60d88 YM |
11566 | /* Configure link feature according to nvram value */ |
11567 | eee_mode = (((SHMEM_RD(bp, dev_info. | |
11568 | port_feature_config[port].eee_power_mode)) & | |
11569 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
11570 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
11571 | if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { | |
11572 | bp->link_params.eee_mode = EEE_MODE_ADV_LPI | | |
11573 | EEE_MODE_ENABLE_LPI | | |
11574 | EEE_MODE_OUTPUT_TIME; | |
11575 | } else { | |
11576 | bp->link_params.eee_mode = 0; | |
11577 | } | |
0793f83f | 11578 | } |
01cd4528 | 11579 | |
b306f5ed | 11580 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 11581 | { |
9e62e912 | 11582 | u32 no_flags = NO_ISCSI_FLAG; |
bf61ee14 | 11583 | int port = BP_PORT(bp); |
2ba45142 | 11584 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 11585 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 11586 | |
55c11941 MS |
11587 | if (!CNIC_SUPPORT(bp)) { |
11588 | bp->flags |= no_flags; | |
11589 | return; | |
11590 | } | |
11591 | ||
b306f5ed | 11592 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
11593 | bp->cnic_eth_dev.max_iscsi_conn = |
11594 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
11595 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
11596 | ||
b306f5ed DK |
11597 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
11598 | bp->cnic_eth_dev.max_iscsi_conn); | |
11599 | ||
11600 | /* | |
11601 | * If maximum allowed number of connections is zero - | |
11602 | * disable the feature. | |
11603 | */ | |
11604 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9e62e912 | 11605 | bp->flags |= no_flags; |
b306f5ed DK |
11606 | } |
11607 | ||
0329aba1 | 11608 | static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) |
9e62e912 DK |
11609 | { |
11610 | /* Port info */ | |
11611 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
11612 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); | |
11613 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
11614 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); | |
11615 | ||
11616 | /* Node info */ | |
11617 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
11618 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); | |
11619 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
11620 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); | |
11621 | } | |
86800194 DK |
11622 | |
11623 | static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) | |
11624 | { | |
11625 | u8 count = 0; | |
11626 | ||
11627 | if (IS_MF(bp)) { | |
11628 | u8 fid; | |
11629 | ||
11630 | /* iterate over absolute function ids for this path: */ | |
11631 | for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { | |
11632 | if (IS_MF_SD(bp)) { | |
11633 | u32 cfg = MF_CFG_RD(bp, | |
11634 | func_mf_config[fid].config); | |
11635 | ||
11636 | if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) && | |
11637 | ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) == | |
11638 | FUNC_MF_CFG_PROTOCOL_FCOE)) | |
11639 | count++; | |
11640 | } else { | |
11641 | u32 cfg = MF_CFG_RD(bp, | |
11642 | func_ext_config[fid]. | |
11643 | func_cfg); | |
11644 | ||
11645 | if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) && | |
11646 | (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)) | |
11647 | count++; | |
11648 | } | |
11649 | } | |
11650 | } else { /* SF */ | |
11651 | int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; | |
11652 | ||
11653 | for (port = 0; port < port_cnt; port++) { | |
11654 | u32 lic = SHMEM_RD(bp, | |
11655 | drv_lic_key[port].max_fcoe_conn) ^ | |
11656 | FW_ENCODE_32BIT_PATTERN; | |
11657 | if (lic) | |
11658 | count++; | |
11659 | } | |
11660 | } | |
11661 | ||
11662 | return count; | |
11663 | } | |
11664 | ||
0329aba1 | 11665 | static void bnx2x_get_fcoe_info(struct bnx2x *bp) |
b306f5ed DK |
11666 | { |
11667 | int port = BP_PORT(bp); | |
11668 | int func = BP_ABS_FUNC(bp); | |
b306f5ed DK |
11669 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
11670 | drv_lic_key[port].max_fcoe_conn); | |
86800194 | 11671 | u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); |
b306f5ed | 11672 | |
55c11941 MS |
11673 | if (!CNIC_SUPPORT(bp)) { |
11674 | bp->flags |= NO_FCOE_FLAG; | |
11675 | return; | |
11676 | } | |
11677 | ||
b306f5ed | 11678 | /* Get the number of maximum allowed FCoE connections */ |
2ba45142 VZ |
11679 | bp->cnic_eth_dev.max_fcoe_conn = |
11680 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
11681 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
11682 | ||
0eb43b4b BPG |
11683 | /* Calculate the number of maximum allowed FCoE tasks */ |
11684 | bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; | |
86800194 DK |
11685 | |
11686 | /* check if FCoE resources must be shared between different functions */ | |
11687 | if (num_fcoe_func) | |
11688 | bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; | |
0eb43b4b | 11689 | |
bf61ee14 VZ |
11690 | /* Read the WWN: */ |
11691 | if (!IS_MF(bp)) { | |
11692 | /* Port info */ | |
11693 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
11694 | SHMEM_RD(bp, | |
2de67439 | 11695 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11696 | fcoe_wwn_port_name_upper); |
11697 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
11698 | SHMEM_RD(bp, | |
2de67439 | 11699 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11700 | fcoe_wwn_port_name_lower); |
11701 | ||
11702 | /* Node info */ | |
11703 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
11704 | SHMEM_RD(bp, | |
2de67439 | 11705 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11706 | fcoe_wwn_node_name_upper); |
11707 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
11708 | SHMEM_RD(bp, | |
2de67439 | 11709 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11710 | fcoe_wwn_node_name_lower); |
11711 | } else if (!IS_MF_SD(bp)) { | |
2e98ffc2 | 11712 | /* Read the WWN info only if the FCoE feature is enabled for |
bf61ee14 VZ |
11713 | * this function. |
11714 | */ | |
2e98ffc2 DK |
11715 | if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp)) |
11716 | bnx2x_get_ext_wwn_info(bp, func); | |
11717 | } else { | |
11718 | if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) | |
9e62e912 | 11719 | bnx2x_get_ext_wwn_info(bp, func); |
382e513a | 11720 | } |
bf61ee14 | 11721 | |
b306f5ed | 11722 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 11723 | |
bf61ee14 VZ |
11724 | /* |
11725 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
11726 | * disable the feature. |
11727 | */ | |
2ba45142 VZ |
11728 | if (!bp->cnic_eth_dev.max_fcoe_conn) |
11729 | bp->flags |= NO_FCOE_FLAG; | |
11730 | } | |
b306f5ed | 11731 | |
0329aba1 | 11732 | static void bnx2x_get_cnic_info(struct bnx2x *bp) |
b306f5ed DK |
11733 | { |
11734 | /* | |
11735 | * iSCSI may be dynamically disabled but reading | |
11736 | * info here we will decrease memory usage by driver | |
11737 | * if the feature is disabled for good | |
11738 | */ | |
11739 | bnx2x_get_iscsi_info(bp); | |
11740 | bnx2x_get_fcoe_info(bp); | |
11741 | } | |
2ba45142 | 11742 | |
0329aba1 | 11743 | static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) |
0793f83f DK |
11744 | { |
11745 | u32 val, val2; | |
11746 | int func = BP_ABS_FUNC(bp); | |
11747 | int port = BP_PORT(bp); | |
2ba45142 VZ |
11748 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; |
11749 | u8 *fip_mac = bp->fip_mac; | |
0793f83f | 11750 | |
55c11941 MS |
11751 | if (IS_MF(bp)) { |
11752 | /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or | |
2ba45142 | 11753 | * FCoE MAC then the appropriate feature should be disabled. |
55c11941 MS |
11754 | * In non SD mode features configuration comes from struct |
11755 | * func_ext_config. | |
2ba45142 | 11756 | */ |
2e98ffc2 | 11757 | if (!IS_MF_SD(bp)) { |
0793f83f DK |
11758 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
11759 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
11760 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 11761 | iscsi_mac_addr_upper); |
0793f83f | 11762 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 11763 | iscsi_mac_addr_lower); |
2ba45142 | 11764 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
55c11941 MS |
11765 | BNX2X_DEV_INFO |
11766 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
11767 | } else { | |
2ba45142 | 11768 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
55c11941 | 11769 | } |
2ba45142 VZ |
11770 | |
11771 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
11772 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 11773 | fcoe_mac_addr_upper); |
2ba45142 | 11774 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 11775 | fcoe_mac_addr_lower); |
2ba45142 | 11776 | bnx2x_set_mac_buf(fip_mac, val, val2); |
55c11941 MS |
11777 | BNX2X_DEV_INFO |
11778 | ("Read FCoE L2 MAC: %pM\n", fip_mac); | |
11779 | } else { | |
2ba45142 | 11780 | bp->flags |= NO_FCOE_FLAG; |
55c11941 | 11781 | } |
a3348722 BW |
11782 | |
11783 | bp->mf_ext_config = cfg; | |
11784 | ||
9e62e912 | 11785 | } else { /* SD MODE */ |
55c11941 MS |
11786 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { |
11787 | /* use primary mac as iscsi mac */ | |
11788 | memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); | |
11789 | ||
11790 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); | |
11791 | BNX2X_DEV_INFO | |
11792 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
11793 | } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { | |
11794 | /* use primary mac as fip mac */ | |
11795 | memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); | |
11796 | BNX2X_DEV_INFO("SD FCoE MODE\n"); | |
11797 | BNX2X_DEV_INFO | |
11798 | ("Read FIP MAC: %pM\n", fip_mac); | |
614c76df | 11799 | } |
0793f83f | 11800 | } |
a3348722 | 11801 | |
82594f8f YM |
11802 | /* If this is a storage-only interface, use SAN mac as |
11803 | * primary MAC. Notice that for SD this is already the case, | |
11804 | * as the SAN mac was copied from the primary MAC. | |
11805 | */ | |
11806 | if (IS_MF_FCOE_AFEX(bp)) | |
a3348722 | 11807 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); |
0793f83f | 11808 | } else { |
0793f83f | 11809 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11810 | iscsi_mac_upper); |
0793f83f | 11811 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11812 | iscsi_mac_lower); |
2ba45142 | 11813 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
11814 | |
11815 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
55c11941 | 11816 | fcoe_fip_mac_upper); |
c03bd39c | 11817 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11818 | fcoe_fip_mac_lower); |
c03bd39c | 11819 | bnx2x_set_mac_buf(fip_mac, val, val2); |
0793f83f DK |
11820 | } |
11821 | ||
55c11941 | 11822 | /* Disable iSCSI OOO if MAC configuration is invalid. */ |
426b9241 | 11823 | if (!is_valid_ether_addr(iscsi_mac)) { |
55c11941 | 11824 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
c7bf7169 | 11825 | eth_zero_addr(iscsi_mac); |
426b9241 DK |
11826 | } |
11827 | ||
55c11941 | 11828 | /* Disable FCoE if MAC configuration is invalid. */ |
426b9241 DK |
11829 | if (!is_valid_ether_addr(fip_mac)) { |
11830 | bp->flags |= NO_FCOE_FLAG; | |
c7bf7169 | 11831 | eth_zero_addr(bp->fip_mac); |
426b9241 | 11832 | } |
55c11941 MS |
11833 | } |
11834 | ||
0329aba1 | 11835 | static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
55c11941 MS |
11836 | { |
11837 | u32 val, val2; | |
11838 | int func = BP_ABS_FUNC(bp); | |
11839 | int port = BP_PORT(bp); | |
11840 | ||
11841 | /* Zero primary MAC configuration */ | |
c7bf7169 | 11842 | eth_zero_addr(bp->dev->dev_addr); |
55c11941 MS |
11843 | |
11844 | if (BP_NOMCP(bp)) { | |
11845 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
11846 | eth_hw_addr_random(bp->dev); | |
11847 | } else if (IS_MF(bp)) { | |
11848 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
11849 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
11850 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
11851 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
11852 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
11853 | ||
11854 | if (CNIC_SUPPORT(bp)) | |
11855 | bnx2x_get_cnic_mac_hwinfo(bp); | |
11856 | } else { | |
11857 | /* in SF read MACs from port configuration */ | |
11858 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
11859 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
11860 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
11861 | ||
11862 | if (CNIC_SUPPORT(bp)) | |
11863 | bnx2x_get_cnic_mac_hwinfo(bp); | |
11864 | } | |
11865 | ||
3d7d562c YM |
11866 | if (!BP_NOMCP(bp)) { |
11867 | /* Read physical port identifier from shmem */ | |
11868 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
11869 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
11870 | bnx2x_set_mac_buf(bp->phys_port_id, val, val2); | |
11871 | bp->flags |= HAS_PHYS_PORT_ID; | |
11872 | } | |
11873 | ||
55c11941 | 11874 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); |
619c5cb6 | 11875 | |
2e98ffc2 | 11876 | if (!is_valid_ether_addr(bp->dev->dev_addr)) |
619c5cb6 | 11877 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11878 | "bad Ethernet MAC address configuration: %pM\n" |
11879 | "change it manually before bringing up the appropriate network interface\n", | |
0f9dad10 | 11880 | bp->dev->dev_addr); |
7964211d | 11881 | } |
51c1a580 | 11882 | |
0329aba1 | 11883 | static bool bnx2x_get_dropless_info(struct bnx2x *bp) |
7964211d YM |
11884 | { |
11885 | int tmp; | |
11886 | u32 cfg; | |
51c1a580 | 11887 | |
aeeddb8b | 11888 | if (IS_VF(bp)) |
4e833c59 | 11889 | return false; |
aeeddb8b | 11890 | |
7964211d YM |
11891 | if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { |
11892 | /* Take function: tmp = func */ | |
11893 | tmp = BP_ABS_FUNC(bp); | |
11894 | cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); | |
11895 | cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); | |
11896 | } else { | |
11897 | /* Take port: tmp = port */ | |
11898 | tmp = BP_PORT(bp); | |
11899 | cfg = SHMEM_RD(bp, | |
11900 | dev_info.port_hw_config[tmp].generic_features); | |
11901 | cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); | |
11902 | } | |
11903 | return cfg; | |
34f80b04 EG |
11904 | } |
11905 | ||
83bad206 YM |
11906 | static void validate_set_si_mode(struct bnx2x *bp) |
11907 | { | |
11908 | u8 func = BP_ABS_FUNC(bp); | |
11909 | u32 val; | |
11910 | ||
11911 | val = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
11912 | ||
11913 | /* check for legal mac (upper bytes) */ | |
11914 | if (val != 0xffff) { | |
11915 | bp->mf_mode = MULTI_FUNCTION_SI; | |
11916 | bp->mf_config[BP_VN(bp)] = | |
11917 | MF_CFG_RD(bp, func_mf_config[func].config); | |
11918 | } else | |
11919 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); | |
11920 | } | |
11921 | ||
0329aba1 | 11922 | static int bnx2x_get_hwinfo(struct bnx2x *bp) |
34f80b04 | 11923 | { |
0793f83f | 11924 | int /*abs*/func = BP_ABS_FUNC(bp); |
230d00eb | 11925 | int vn, mfw_vn; |
83bad206 | 11926 | u32 val = 0, val2 = 0; |
34f80b04 | 11927 | int rc = 0; |
a2fbb9ea | 11928 | |
0f587f1b YM |
11929 | /* Validate that chip access is feasible */ |
11930 | if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) { | |
11931 | dev_err(&bp->pdev->dev, | |
11932 | "Chip read returns all Fs. Preventing probe from continuing\n"); | |
11933 | return -EINVAL; | |
11934 | } | |
11935 | ||
34f80b04 | 11936 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 11937 | |
6383c0b3 AE |
11938 | /* |
11939 | * initialize IGU parameters | |
11940 | */ | |
f2e0899f DK |
11941 | if (CHIP_IS_E1x(bp)) { |
11942 | bp->common.int_block = INT_BLOCK_HC; | |
11943 | ||
11944 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
11945 | bp->igu_base_sb = 0; | |
f2e0899f DK |
11946 | } else { |
11947 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 | 11948 | |
16a5fd92 | 11949 | /* do not allow device reset during IGU info processing */ |
7a06a122 DK |
11950 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
11951 | ||
f2e0899f | 11952 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
11953 | |
11954 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
11955 | int tout = 5000; | |
11956 | ||
11957 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
11958 | ||
11959 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
11960 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
11961 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
11962 | ||
11963 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
11964 | tout--; | |
0926d499 | 11965 | usleep_range(1000, 2000); |
619c5cb6 VZ |
11966 | } |
11967 | ||
11968 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
11969 | dev_err(&bp->pdev->dev, | |
11970 | "FORCING Normal Mode failed!!!\n"); | |
9b341bb1 BW |
11971 | bnx2x_release_hw_lock(bp, |
11972 | HW_LOCK_RESOURCE_RESET); | |
619c5cb6 VZ |
11973 | return -EPERM; |
11974 | } | |
11975 | } | |
11976 | ||
f2e0899f | 11977 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 11978 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
11979 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
11980 | } else | |
619c5cb6 | 11981 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 11982 | |
9b341bb1 | 11983 | rc = bnx2x_get_igu_cam_info(bp); |
7a06a122 | 11984 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
9b341bb1 BW |
11985 | if (rc) |
11986 | return rc; | |
f2e0899f | 11987 | } |
619c5cb6 VZ |
11988 | |
11989 | /* | |
11990 | * set base FW non-default (fast path) status block id, this value is | |
11991 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
11992 | * determine the id used by the FW. | |
11993 | */ | |
11994 | if (CHIP_IS_E1x(bp)) | |
11995 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
11996 | else /* | |
11997 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
11998 | * the same queue are indicated on the same IGU SB). So we prefer | |
11999 | * FW and IGU SBs to be the same value. | |
12000 | */ | |
12001 | bp->base_fw_ndsb = bp->igu_base_sb; | |
12002 | ||
12003 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
12004 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
12005 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
12006 | |
12007 | /* | |
12008 | * Initialize MF configuration | |
12009 | */ | |
523224a3 | 12010 | |
fb3bff17 DK |
12011 | bp->mf_ov = 0; |
12012 | bp->mf_mode = 0; | |
7609647e | 12013 | bp->mf_sub_mode = 0; |
3395a033 | 12014 | vn = BP_VN(bp); |
230d00eb | 12015 | mfw_vn = BP_FW_MB_IDX(bp); |
0793f83f | 12016 | |
f2e0899f | 12017 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
12018 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
12019 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
12020 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
12021 | ||
f2e0899f DK |
12022 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
12023 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
12024 | else | |
12025 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
12026 | offsetof(struct shmem_region, func_mb) + |
12027 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
12028 | /* |
12029 | * get mf configuration: | |
16a5fd92 | 12030 | * 1. Existence of MF configuration |
0793f83f DK |
12031 | * 2. MAC address must be legal (check only upper bytes) |
12032 | * for Switch-Independent mode; | |
12033 | * OVLAN must be legal for Switch-Dependent mode | |
12034 | * 3. SF_MODE configures specific MF mode | |
12035 | */ | |
12036 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
12037 | /* get mf configuration */ | |
12038 | val = SHMEM_RD(bp, | |
12039 | dev_info.shared_feature_config.config); | |
12040 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
12041 | ||
12042 | switch (val) { | |
12043 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
83bad206 | 12044 | validate_set_si_mode(bp); |
0793f83f | 12045 | break; |
a3348722 BW |
12046 | case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: |
12047 | if ((!CHIP_IS_E1x(bp)) && | |
12048 | (MF_CFG_RD(bp, func_mf_config[func]. | |
12049 | mac_upper) != 0xffff) && | |
12050 | (SHMEM2_HAS(bp, | |
12051 | afex_driver_support))) { | |
12052 | bp->mf_mode = MULTI_FUNCTION_AFEX; | |
12053 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
12054 | func_mf_config[func].config); | |
12055 | } else { | |
12056 | BNX2X_DEV_INFO("can not configure afex mode\n"); | |
12057 | } | |
12058 | break; | |
0793f83f DK |
12059 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: |
12060 | /* get OV configuration */ | |
12061 | val = MF_CFG_RD(bp, | |
12062 | func_mf_config[FUNC_0].e1hov_tag); | |
12063 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
12064 | ||
12065 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
12066 | bp->mf_mode = MULTI_FUNCTION_SD; | |
12067 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
12068 | func_mf_config[func].config); | |
12069 | } else | |
754a2f52 | 12070 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f | 12071 | break; |
230d00eb YM |
12072 | case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE: |
12073 | bp->mf_mode = MULTI_FUNCTION_SD; | |
12074 | bp->mf_sub_mode = SUB_MF_MODE_BD; | |
12075 | bp->mf_config[vn] = | |
12076 | MF_CFG_RD(bp, | |
12077 | func_mf_config[func].config); | |
12078 | ||
12079 | if (SHMEM2_HAS(bp, mtu_size)) { | |
12080 | int mtu_idx = BP_FW_MB_IDX(bp); | |
12081 | u16 mtu_size; | |
12082 | u32 mtu; | |
12083 | ||
12084 | mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]); | |
12085 | mtu_size = (u16)mtu; | |
12086 | DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n", | |
12087 | mtu_size, mtu); | |
12088 | ||
12089 | /* if valid: update device mtu */ | |
12090 | if (((mtu_size + ETH_HLEN) >= | |
12091 | ETH_MIN_PACKET_SIZE) && | |
12092 | (mtu_size <= | |
12093 | ETH_MAX_JUMBO_PACKET_SIZE)) | |
12094 | bp->dev->mtu = mtu_size; | |
12095 | } | |
12096 | break; | |
7609647e YM |
12097 | case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE: |
12098 | bp->mf_mode = MULTI_FUNCTION_SD; | |
12099 | bp->mf_sub_mode = SUB_MF_MODE_UFP; | |
12100 | bp->mf_config[vn] = | |
12101 | MF_CFG_RD(bp, | |
12102 | func_mf_config[func].config); | |
12103 | break; | |
3786b942 AE |
12104 | case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: |
12105 | bp->mf_config[vn] = 0; | |
12106 | break; | |
83bad206 YM |
12107 | case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE: |
12108 | val2 = SHMEM_RD(bp, | |
12109 | dev_info.shared_hw_config.config_3); | |
12110 | val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK; | |
12111 | switch (val2) { | |
12112 | case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5: | |
12113 | validate_set_si_mode(bp); | |
12114 | bp->mf_sub_mode = | |
12115 | SUB_MF_MODE_NPAR1_DOT_5; | |
12116 | break; | |
12117 | default: | |
12118 | /* Unknown configuration */ | |
12119 | bp->mf_config[vn] = 0; | |
12120 | BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n", | |
12121 | val); | |
12122 | } | |
12123 | break; | |
0793f83f DK |
12124 | default: |
12125 | /* Unknown configuration: reset mf_config */ | |
12126 | bp->mf_config[vn] = 0; | |
51c1a580 | 12127 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
0793f83f DK |
12128 | } |
12129 | } | |
a2fbb9ea | 12130 | |
2691d51d | 12131 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 12132 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 12133 | |
0793f83f DK |
12134 | switch (bp->mf_mode) { |
12135 | case MULTI_FUNCTION_SD: | |
12136 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
12137 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 12138 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 12139 | bp->mf_ov = val; |
619c5cb6 VZ |
12140 | bp->path_has_ovlan = true; |
12141 | ||
51c1a580 MS |
12142 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
12143 | func, bp->mf_ov, bp->mf_ov); | |
230d00eb YM |
12144 | } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) || |
12145 | (bp->mf_sub_mode == SUB_MF_MODE_BD)) { | |
7609647e | 12146 | dev_err(&bp->pdev->dev, |
230d00eb | 12147 | "Unexpected - no valid MF OV for func %d in UFP/BD mode\n", |
7609647e YM |
12148 | func); |
12149 | bp->path_has_ovlan = true; | |
2691d51d | 12150 | } else { |
619c5cb6 | 12151 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
12152 | "No valid MF OV for func %d, aborting\n", |
12153 | func); | |
619c5cb6 | 12154 | return -EPERM; |
34f80b04 | 12155 | } |
0793f83f | 12156 | break; |
a3348722 BW |
12157 | case MULTI_FUNCTION_AFEX: |
12158 | BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); | |
12159 | break; | |
0793f83f | 12160 | case MULTI_FUNCTION_SI: |
51c1a580 MS |
12161 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
12162 | func); | |
0793f83f DK |
12163 | break; |
12164 | default: | |
12165 | if (vn) { | |
619c5cb6 | 12166 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
12167 | "VN %d is in a single function mode, aborting\n", |
12168 | vn); | |
619c5cb6 | 12169 | return -EPERM; |
2691d51d | 12170 | } |
0793f83f | 12171 | break; |
34f80b04 | 12172 | } |
0793f83f | 12173 | |
619c5cb6 VZ |
12174 | /* check if other port on the path needs ovlan: |
12175 | * Since MF configuration is shared between ports | |
12176 | * Possible mixed modes are only | |
12177 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
12178 | */ | |
12179 | if (CHIP_MODE_IS_4_PORT(bp) && | |
12180 | !bp->path_has_ovlan && | |
12181 | !IS_MF(bp) && | |
12182 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
12183 | u8 other_port = !BP_PORT(bp); | |
12184 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
12185 | val = MF_CFG_RD(bp, | |
12186 | func_mf_config[other_func].e1hov_tag); | |
12187 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
12188 | bp->path_has_ovlan = true; | |
12189 | } | |
34f80b04 | 12190 | } |
a2fbb9ea | 12191 | |
e848582c DK |
12192 | /* adjust igu_sb_cnt to MF for E1H */ |
12193 | if (CHIP_IS_E1H(bp) && IS_MF(bp)) | |
12194 | bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT); | |
523224a3 | 12195 | |
619c5cb6 VZ |
12196 | /* port info */ |
12197 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 12198 | |
0793f83f DK |
12199 | /* Get MAC addresses */ |
12200 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 12201 | |
2ba45142 | 12202 | bnx2x_get_cnic_info(bp); |
2ba45142 | 12203 | |
34f80b04 EG |
12204 | return rc; |
12205 | } | |
12206 | ||
0329aba1 | 12207 | static void bnx2x_read_fwinfo(struct bnx2x *bp) |
34f24c7f VZ |
12208 | { |
12209 | int cnt, i, block_end, rodi; | |
fcdf95cb | 12210 | char vpd_start[BNX2X_VPD_LEN+1]; |
34f24c7f VZ |
12211 | char str_id_reg[VENDOR_ID_LEN+1]; |
12212 | char str_id_cap[VENDOR_ID_LEN+1]; | |
fcdf95cb BW |
12213 | char *vpd_data; |
12214 | char *vpd_extended_data = NULL; | |
34f24c7f VZ |
12215 | u8 len; |
12216 | ||
fcdf95cb | 12217 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); |
34f24c7f VZ |
12218 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
12219 | ||
12220 | if (cnt < BNX2X_VPD_LEN) | |
12221 | goto out_not_found; | |
12222 | ||
fcdf95cb BW |
12223 | /* VPD RO tag should be first tag after identifier string, hence |
12224 | * we should be able to find it in first BNX2X_VPD_LEN chars | |
12225 | */ | |
12226 | i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, | |
34f24c7f VZ |
12227 | PCI_VPD_LRDT_RO_DATA); |
12228 | if (i < 0) | |
12229 | goto out_not_found; | |
12230 | ||
34f24c7f | 12231 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + |
fcdf95cb | 12232 | pci_vpd_lrdt_size(&vpd_start[i]); |
34f24c7f VZ |
12233 | |
12234 | i += PCI_VPD_LRDT_TAG_SIZE; | |
12235 | ||
fcdf95cb BW |
12236 | if (block_end > BNX2X_VPD_LEN) { |
12237 | vpd_extended_data = kmalloc(block_end, GFP_KERNEL); | |
12238 | if (vpd_extended_data == NULL) | |
12239 | goto out_not_found; | |
12240 | ||
12241 | /* read rest of vpd image into vpd_extended_data */ | |
12242 | memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); | |
12243 | cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, | |
12244 | block_end - BNX2X_VPD_LEN, | |
12245 | vpd_extended_data + BNX2X_VPD_LEN); | |
12246 | if (cnt < (block_end - BNX2X_VPD_LEN)) | |
12247 | goto out_not_found; | |
12248 | vpd_data = vpd_extended_data; | |
12249 | } else | |
12250 | vpd_data = vpd_start; | |
12251 | ||
12252 | /* now vpd_data holds full vpd content in both cases */ | |
34f24c7f VZ |
12253 | |
12254 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
12255 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
12256 | if (rodi < 0) | |
12257 | goto out_not_found; | |
12258 | ||
12259 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
12260 | ||
12261 | if (len != VENDOR_ID_LEN) | |
12262 | goto out_not_found; | |
12263 | ||
12264 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
12265 | ||
12266 | /* vendor specific info */ | |
12267 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
12268 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
12269 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
12270 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
12271 | ||
12272 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
12273 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
12274 | if (rodi >= 0) { | |
12275 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
12276 | ||
12277 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
12278 | ||
12279 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
12280 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
12281 | bp->fw_ver[len] = ' '; | |
12282 | } | |
12283 | } | |
fcdf95cb | 12284 | kfree(vpd_extended_data); |
34f24c7f VZ |
12285 | return; |
12286 | } | |
12287 | out_not_found: | |
fcdf95cb | 12288 | kfree(vpd_extended_data); |
34f24c7f VZ |
12289 | return; |
12290 | } | |
12291 | ||
0329aba1 | 12292 | static void bnx2x_set_modes_bitmap(struct bnx2x *bp) |
619c5cb6 VZ |
12293 | { |
12294 | u32 flags = 0; | |
12295 | ||
12296 | if (CHIP_REV_IS_FPGA(bp)) | |
12297 | SET_FLAGS(flags, MODE_FPGA); | |
12298 | else if (CHIP_REV_IS_EMUL(bp)) | |
12299 | SET_FLAGS(flags, MODE_EMUL); | |
12300 | else | |
12301 | SET_FLAGS(flags, MODE_ASIC); | |
12302 | ||
12303 | if (CHIP_MODE_IS_4_PORT(bp)) | |
12304 | SET_FLAGS(flags, MODE_PORT4); | |
12305 | else | |
12306 | SET_FLAGS(flags, MODE_PORT2); | |
12307 | ||
12308 | if (CHIP_IS_E2(bp)) | |
12309 | SET_FLAGS(flags, MODE_E2); | |
12310 | else if (CHIP_IS_E3(bp)) { | |
12311 | SET_FLAGS(flags, MODE_E3); | |
12312 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
12313 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
12314 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
12315 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
12316 | } |
12317 | ||
12318 | if (IS_MF(bp)) { | |
12319 | SET_FLAGS(flags, MODE_MF); | |
12320 | switch (bp->mf_mode) { | |
12321 | case MULTI_FUNCTION_SD: | |
12322 | SET_FLAGS(flags, MODE_MF_SD); | |
12323 | break; | |
12324 | case MULTI_FUNCTION_SI: | |
12325 | SET_FLAGS(flags, MODE_MF_SI); | |
12326 | break; | |
a3348722 BW |
12327 | case MULTI_FUNCTION_AFEX: |
12328 | SET_FLAGS(flags, MODE_MF_AFEX); | |
12329 | break; | |
619c5cb6 VZ |
12330 | } |
12331 | } else | |
12332 | SET_FLAGS(flags, MODE_SF); | |
12333 | ||
12334 | #if defined(__LITTLE_ENDIAN) | |
12335 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
12336 | #else /*(__BIG_ENDIAN)*/ | |
12337 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
12338 | #endif | |
12339 | INIT_MODE_FLAGS(bp) = flags; | |
12340 | } | |
12341 | ||
0329aba1 | 12342 | static int bnx2x_init_bp(struct bnx2x *bp) |
34f80b04 | 12343 | { |
f2e0899f | 12344 | int func; |
34f80b04 EG |
12345 | int rc; |
12346 | ||
34f80b04 | 12347 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 12348 | mutex_init(&bp->fw_mb_mutex); |
42f8277f | 12349 | mutex_init(&bp->drv_info_mutex); |
c6e36d8c | 12350 | sema_init(&bp->stats_lock, 1); |
42f8277f | 12351 | bp->drv_info_mng_owner = false; |
05cc5a39 | 12352 | INIT_LIST_HEAD(&bp->vlan_reg); |
55c11941 | 12353 | |
1cf167f2 | 12354 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 12355 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 12356 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
370d4a26 | 12357 | INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task); |
1ab4434c AE |
12358 | if (IS_PF(bp)) { |
12359 | rc = bnx2x_get_hwinfo(bp); | |
12360 | if (rc) | |
12361 | return rc; | |
12362 | } else { | |
e09b74d0 | 12363 | eth_zero_addr(bp->dev->dev_addr); |
1ab4434c | 12364 | } |
34f80b04 | 12365 | |
619c5cb6 VZ |
12366 | bnx2x_set_modes_bitmap(bp); |
12367 | ||
12368 | rc = bnx2x_alloc_mem_bp(bp); | |
12369 | if (rc) | |
12370 | return rc; | |
523224a3 | 12371 | |
34f24c7f | 12372 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
12373 | |
12374 | func = BP_FUNC(bp); | |
12375 | ||
34f80b04 | 12376 | /* need to reset chip if undi was active */ |
1ab4434c | 12377 | if (IS_PF(bp) && !BP_NOMCP(bp)) { |
452427b0 YM |
12378 | /* init fw_seq */ |
12379 | bp->fw_seq = | |
12380 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
12381 | DRV_MSG_SEQ_NUMBER_MASK; | |
12382 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
12383 | ||
91ebb929 YM |
12384 | rc = bnx2x_prev_unload(bp); |
12385 | if (rc) { | |
12386 | bnx2x_free_mem_bp(bp); | |
12387 | return rc; | |
12388 | } | |
452427b0 YM |
12389 | } |
12390 | ||
34f80b04 | 12391 | if (CHIP_REV_IS_FPGA(bp)) |
cdaa7cb8 | 12392 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
12393 | |
12394 | if (BP_NOMCP(bp) && (func == 0)) | |
51c1a580 | 12395 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
34f80b04 | 12396 | |
614c76df | 12397 | bp->disable_tpa = disable_tpa; |
2e98ffc2 | 12398 | bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp); |
94d9de3c | 12399 | /* Reduce memory usage in kdump environment by disabling TPA */ |
c9931896 | 12400 | bp->disable_tpa |= is_kdump_kernel(); |
614c76df | 12401 | |
7a9b2557 | 12402 | /* Set TPA flags */ |
614c76df | 12403 | if (bp->disable_tpa) { |
d9b9e860 | 12404 | bp->dev->hw_features &= ~NETIF_F_LRO; |
7a9b2557 | 12405 | bp->dev->features &= ~NETIF_F_LRO; |
7a9b2557 VZ |
12406 | } |
12407 | ||
a18f5128 EG |
12408 | if (CHIP_IS_E1(bp)) |
12409 | bp->dropless_fc = 0; | |
12410 | else | |
7964211d | 12411 | bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); |
a18f5128 | 12412 | |
8d5726c4 | 12413 | bp->mrrs = mrrs; |
7a9b2557 | 12414 | |
2e98ffc2 | 12415 | bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL; |
1ab4434c AE |
12416 | if (IS_VF(bp)) |
12417 | bp->rx_ring_size = MAX_RX_AVAIL; | |
34f80b04 | 12418 | |
7d323bfd | 12419 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
12420 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
12421 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 12422 | |
fc543637 | 12423 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
34f80b04 EG |
12424 | |
12425 | init_timer(&bp->timer); | |
12426 | bp->timer.expires = jiffies + bp->current_interval; | |
12427 | bp->timer.data = (unsigned long) bp; | |
12428 | bp->timer.function = bnx2x_timer; | |
12429 | ||
0370cf90 BW |
12430 | if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && |
12431 | SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && | |
9c73267d | 12432 | SHMEM2_HAS(bp, dcbx_en) && |
0370cf90 | 12433 | SHMEM2_RD(bp, dcbx_lldp_params_offset) && |
9c73267d YM |
12434 | SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) && |
12435 | SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) { | |
0370cf90 BW |
12436 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); |
12437 | bnx2x_dcbx_init_params(bp); | |
12438 | } else { | |
12439 | bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); | |
12440 | } | |
e4901dde | 12441 | |
619c5cb6 VZ |
12442 | if (CHIP_IS_E1x(bp)) |
12443 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
12444 | else | |
12445 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
619c5cb6 | 12446 | |
6383c0b3 | 12447 | /* multiple tx priority */ |
1ab4434c AE |
12448 | if (IS_VF(bp)) |
12449 | bp->max_cos = 1; | |
12450 | else if (CHIP_IS_E1x(bp)) | |
6383c0b3 | 12451 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; |
1ab4434c | 12452 | else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) |
6383c0b3 | 12453 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; |
1ab4434c | 12454 | else if (CHIP_IS_E3B0(bp)) |
6383c0b3 | 12455 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; |
1ab4434c AE |
12456 | else |
12457 | BNX2X_ERR("unknown chip %x revision %x\n", | |
12458 | CHIP_NUM(bp), CHIP_REV(bp)); | |
12459 | BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); | |
6383c0b3 | 12460 | |
55c11941 MS |
12461 | /* We need at least one default status block for slow-path events, |
12462 | * second status block for the L2 queue, and a third status block for | |
16a5fd92 | 12463 | * CNIC if supported. |
55c11941 | 12464 | */ |
60cad4e6 AE |
12465 | if (IS_VF(bp)) |
12466 | bp->min_msix_vec_cnt = 1; | |
12467 | else if (CNIC_SUPPORT(bp)) | |
55c11941 | 12468 | bp->min_msix_vec_cnt = 3; |
60cad4e6 | 12469 | else /* PF w/o cnic */ |
55c11941 MS |
12470 | bp->min_msix_vec_cnt = 2; |
12471 | BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); | |
12472 | ||
5bb680d6 MS |
12473 | bp->dump_preset_idx = 1; |
12474 | ||
eeed018c MK |
12475 | if (CHIP_IS_E3B0(bp)) |
12476 | bp->flags |= PTP_SUPPORTED; | |
12477 | ||
34f80b04 | 12478 | return rc; |
a2fbb9ea ET |
12479 | } |
12480 | ||
de0c62db DK |
12481 | /**************************************************************************** |
12482 | * General service functions | |
12483 | ****************************************************************************/ | |
a2fbb9ea | 12484 | |
619c5cb6 VZ |
12485 | /* |
12486 | * net_device service functions | |
12487 | */ | |
12488 | ||
bb2a0f7a | 12489 | /* called with rtnl_lock */ |
a2fbb9ea ET |
12490 | static int bnx2x_open(struct net_device *dev) |
12491 | { | |
12492 | struct bnx2x *bp = netdev_priv(dev); | |
8395be5e | 12493 | int rc; |
a2fbb9ea | 12494 | |
1355b704 MY |
12495 | bp->stats_init = true; |
12496 | ||
6eccabb3 EG |
12497 | netif_carrier_off(dev); |
12498 | ||
a2fbb9ea ET |
12499 | bnx2x_set_power_state(bp, PCI_D0); |
12500 | ||
ad5afc89 | 12501 | /* If parity had happen during the unload, then attentions |
c9ee9206 VZ |
12502 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we |
12503 | * want the first function loaded on the current engine to | |
12504 | * complete the recovery. | |
ad5afc89 | 12505 | * Parity recovery is only relevant for PF driver. |
c9ee9206 | 12506 | */ |
ad5afc89 | 12507 | if (IS_PF(bp)) { |
1a6974b2 YM |
12508 | int other_engine = BP_PATH(bp) ? 0 : 1; |
12509 | bool other_load_status, load_status; | |
12510 | bool global = false; | |
12511 | ||
ad5afc89 AE |
12512 | other_load_status = bnx2x_get_load_status(bp, other_engine); |
12513 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); | |
12514 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
12515 | bnx2x_chk_parity_attn(bp, &global, true)) { | |
12516 | do { | |
12517 | /* If there are attentions and they are in a | |
12518 | * global blocks, set the GLOBAL_RESET bit | |
12519 | * regardless whether it will be this function | |
12520 | * that will complete the recovery or not. | |
12521 | */ | |
12522 | if (global) | |
12523 | bnx2x_set_reset_global(bp); | |
72fd0718 | 12524 | |
ad5afc89 AE |
12525 | /* Only the first function on the current |
12526 | * engine should try to recover in open. In case | |
12527 | * of attentions in global blocks only the first | |
12528 | * in the chip should try to recover. | |
12529 | */ | |
12530 | if ((!load_status && | |
12531 | (!global || !other_load_status)) && | |
12532 | bnx2x_trylock_leader_lock(bp) && | |
12533 | !bnx2x_leader_reset(bp)) { | |
12534 | netdev_info(bp->dev, | |
12535 | "Recovered in open\n"); | |
12536 | break; | |
12537 | } | |
72fd0718 | 12538 | |
ad5afc89 AE |
12539 | /* recovery has failed... */ |
12540 | bnx2x_set_power_state(bp, PCI_D3hot); | |
12541 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
72fd0718 | 12542 | |
ad5afc89 AE |
12543 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
12544 | "If you still see this message after a few retries then power cycle is required.\n"); | |
72fd0718 | 12545 | |
ad5afc89 AE |
12546 | return -EAGAIN; |
12547 | } while (0); | |
12548 | } | |
12549 | } | |
72fd0718 VZ |
12550 | |
12551 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
8395be5e AE |
12552 | rc = bnx2x_nic_load(bp, LOAD_OPEN); |
12553 | if (rc) | |
12554 | return rc; | |
f34fa14c RB |
12555 | |
12556 | #ifdef CONFIG_BNX2X_VXLAN | |
12557 | if (IS_PF(bp)) | |
12558 | vxlan_get_rx_port(dev); | |
12559 | #endif | |
883ce97d YM |
12560 | #if IS_ENABLED(CONFIG_GENEVE) |
12561 | if (IS_PF(bp)) | |
12562 | geneve_get_rx_port(dev); | |
12563 | #endif | |
f34fa14c | 12564 | |
9a8130bc | 12565 | return 0; |
a2fbb9ea ET |
12566 | } |
12567 | ||
bb2a0f7a | 12568 | /* called with rtnl_lock */ |
56ad3152 | 12569 | static int bnx2x_close(struct net_device *dev) |
a2fbb9ea | 12570 | { |
a2fbb9ea ET |
12571 | struct bnx2x *bp = netdev_priv(dev); |
12572 | ||
12573 | /* Unload the driver, release IRQs */ | |
5d07d868 | 12574 | bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); |
c9ee9206 | 12575 | |
a2fbb9ea ET |
12576 | return 0; |
12577 | } | |
12578 | ||
1191cb83 ED |
12579 | static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
12580 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 12581 | { |
619c5cb6 VZ |
12582 | int mc_count = netdev_mc_count(bp->dev); |
12583 | struct bnx2x_mcast_list_elem *mc_mac = | |
cd2b0389 | 12584 | kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC); |
619c5cb6 | 12585 | struct netdev_hw_addr *ha; |
6e30dd4e | 12586 | |
619c5cb6 VZ |
12587 | if (!mc_mac) |
12588 | return -ENOMEM; | |
6e30dd4e | 12589 | |
619c5cb6 | 12590 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 12591 | |
619c5cb6 VZ |
12592 | netdev_for_each_mc_addr(ha, bp->dev) { |
12593 | mc_mac->mac = bnx2x_mc_addr(ha); | |
12594 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
12595 | mc_mac++; | |
6e30dd4e | 12596 | } |
619c5cb6 VZ |
12597 | |
12598 | p->mcast_list_len = mc_count; | |
12599 | ||
12600 | return 0; | |
6e30dd4e VZ |
12601 | } |
12602 | ||
1191cb83 | 12603 | static void bnx2x_free_mcast_macs_list( |
619c5cb6 VZ |
12604 | struct bnx2x_mcast_ramrod_params *p) |
12605 | { | |
12606 | struct bnx2x_mcast_list_elem *mc_mac = | |
12607 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
12608 | link); | |
12609 | ||
12610 | WARN_ON(!mc_mac); | |
12611 | kfree(mc_mac); | |
12612 | } | |
12613 | ||
12614 | /** | |
12615 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
12616 | * | |
12617 | * @bp: driver handle | |
6e30dd4e | 12618 | * |
619c5cb6 | 12619 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 12620 | */ |
1191cb83 | 12621 | static int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 12622 | { |
619c5cb6 | 12623 | int rc; |
6e30dd4e | 12624 | struct net_device *dev = bp->dev; |
6e30dd4e | 12625 | struct netdev_hw_addr *ha; |
15192a8c | 12626 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; |
619c5cb6 | 12627 | unsigned long ramrod_flags = 0; |
6e30dd4e | 12628 | |
619c5cb6 VZ |
12629 | /* First schedule a cleanup up of old configuration */ |
12630 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
12631 | if (rc < 0) { | |
12632 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
12633 | return rc; | |
12634 | } | |
6e30dd4e VZ |
12635 | |
12636 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
12637 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
12638 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
7b5342d9 YM |
12639 | if (rc == -EEXIST) { |
12640 | DP(BNX2X_MSG_SP, | |
12641 | "Failed to schedule ADD operations: %d\n", rc); | |
12642 | /* do not treat adding same MAC as error */ | |
12643 | rc = 0; | |
12644 | ||
12645 | } else if (rc < 0) { | |
12646 | ||
619c5cb6 VZ |
12647 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", |
12648 | rc); | |
12649 | return rc; | |
6e30dd4e VZ |
12650 | } |
12651 | } | |
12652 | ||
619c5cb6 VZ |
12653 | /* Execute the pending commands */ |
12654 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
12655 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
12656 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
12657 | } |
12658 | ||
1191cb83 | 12659 | static int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 12660 | { |
619c5cb6 | 12661 | struct net_device *dev = bp->dev; |
3b603066 | 12662 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 | 12663 | int rc = 0; |
6e30dd4e | 12664 | |
619c5cb6 | 12665 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 12666 | |
619c5cb6 VZ |
12667 | /* first, clear all configured multicast MACs */ |
12668 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
12669 | if (rc < 0) { | |
51c1a580 | 12670 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
619c5cb6 VZ |
12671 | return rc; |
12672 | } | |
6e30dd4e | 12673 | |
619c5cb6 VZ |
12674 | /* then, configure a new MACs list */ |
12675 | if (netdev_mc_count(dev)) { | |
12676 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
12677 | if (rc) { | |
51c1a580 MS |
12678 | BNX2X_ERR("Failed to create multicast MACs list: %d\n", |
12679 | rc); | |
619c5cb6 VZ |
12680 | return rc; |
12681 | } | |
6e30dd4e | 12682 | |
619c5cb6 VZ |
12683 | /* Now add the new MACs */ |
12684 | rc = bnx2x_config_mcast(bp, &rparam, | |
12685 | BNX2X_MCAST_CMD_ADD); | |
12686 | if (rc < 0) | |
51c1a580 MS |
12687 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
12688 | rc); | |
6e30dd4e | 12689 | |
619c5cb6 VZ |
12690 | bnx2x_free_mcast_macs_list(&rparam); |
12691 | } | |
6e30dd4e | 12692 | |
619c5cb6 | 12693 | return rc; |
6e30dd4e VZ |
12694 | } |
12695 | ||
619c5cb6 | 12696 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
a8f47eb7 | 12697 | static void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
12698 | { |
12699 | struct bnx2x *bp = netdev_priv(dev); | |
34f80b04 EG |
12700 | |
12701 | if (bp->state != BNX2X_STATE_OPEN) { | |
12702 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
12703 | return; | |
8b09be5f YM |
12704 | } else { |
12705 | /* Schedule an SP task to handle rest of change */ | |
230bb0f3 YM |
12706 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE, |
12707 | NETIF_MSG_IFUP); | |
34f80b04 | 12708 | } |
8b09be5f YM |
12709 | } |
12710 | ||
12711 | void bnx2x_set_rx_mode_inner(struct bnx2x *bp) | |
12712 | { | |
12713 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 | 12714 | |
619c5cb6 | 12715 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 | 12716 | |
8b09be5f YM |
12717 | netif_addr_lock_bh(bp->dev); |
12718 | ||
12719 | if (bp->dev->flags & IFF_PROMISC) { | |
34f80b04 | 12720 | rx_mode = BNX2X_RX_MODE_PROMISC; |
8b09be5f YM |
12721 | } else if ((bp->dev->flags & IFF_ALLMULTI) || |
12722 | ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && | |
12723 | CHIP_IS_E1(bp))) { | |
34f80b04 | 12724 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
8b09be5f | 12725 | } else { |
381ac16b AE |
12726 | if (IS_PF(bp)) { |
12727 | /* some multicasts */ | |
12728 | if (bnx2x_set_mc_list(bp) < 0) | |
12729 | rx_mode = BNX2X_RX_MODE_ALLMULTI; | |
34f80b04 | 12730 | |
8b09be5f YM |
12731 | /* release bh lock, as bnx2x_set_uc_list might sleep */ |
12732 | netif_addr_unlock_bh(bp->dev); | |
381ac16b AE |
12733 | if (bnx2x_set_uc_list(bp) < 0) |
12734 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
8b09be5f | 12735 | netif_addr_lock_bh(bp->dev); |
381ac16b AE |
12736 | } else { |
12737 | /* configuring mcast to a vf involves sleeping (when we | |
8b09be5f | 12738 | * wait for the pf's response). |
381ac16b | 12739 | */ |
230bb0f3 YM |
12740 | bnx2x_schedule_sp_rtnl(bp, |
12741 | BNX2X_SP_RTNL_VFPF_MCAST, 0); | |
381ac16b | 12742 | } |
34f80b04 EG |
12743 | } |
12744 | ||
12745 | bp->rx_mode = rx_mode; | |
614c76df | 12746 | /* handle ISCSI SD mode */ |
2e98ffc2 | 12747 | if (IS_MF_ISCSI_ONLY(bp)) |
614c76df | 12748 | bp->rx_mode = BNX2X_RX_MODE_NONE; |
619c5cb6 VZ |
12749 | |
12750 | /* Schedule the rx_mode command */ | |
12751 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
12752 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
8b09be5f | 12753 | netif_addr_unlock_bh(bp->dev); |
619c5cb6 VZ |
12754 | return; |
12755 | } | |
12756 | ||
381ac16b AE |
12757 | if (IS_PF(bp)) { |
12758 | bnx2x_set_storm_rx_mode(bp); | |
8b09be5f | 12759 | netif_addr_unlock_bh(bp->dev); |
381ac16b | 12760 | } else { |
8b09be5f YM |
12761 | /* VF will need to request the PF to make this change, and so |
12762 | * the VF needs to release the bottom-half lock prior to the | |
12763 | * request (as it will likely require sleep on the VF side) | |
381ac16b | 12764 | */ |
8b09be5f YM |
12765 | netif_addr_unlock_bh(bp->dev); |
12766 | bnx2x_vfpf_storm_rx_mode(bp); | |
381ac16b | 12767 | } |
34f80b04 EG |
12768 | } |
12769 | ||
c18487ee | 12770 | /* called with rtnl_lock */ |
01cd4528 EG |
12771 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
12772 | int devad, u16 addr) | |
a2fbb9ea | 12773 | { |
01cd4528 EG |
12774 | struct bnx2x *bp = netdev_priv(netdev); |
12775 | u16 value; | |
12776 | int rc; | |
a2fbb9ea | 12777 | |
01cd4528 EG |
12778 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
12779 | prtad, devad, addr); | |
a2fbb9ea | 12780 | |
01cd4528 EG |
12781 | /* The HW expects different devad if CL22 is used */ |
12782 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 12783 | |
01cd4528 | 12784 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 12785 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
12786 | bnx2x_release_phy_lock(bp); |
12787 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 12788 | |
01cd4528 EG |
12789 | if (!rc) |
12790 | rc = value; | |
12791 | return rc; | |
12792 | } | |
a2fbb9ea | 12793 | |
01cd4528 EG |
12794 | /* called with rtnl_lock */ |
12795 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
12796 | u16 addr, u16 value) | |
12797 | { | |
12798 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
12799 | int rc; |
12800 | ||
51c1a580 MS |
12801 | DP(NETIF_MSG_LINK, |
12802 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", | |
12803 | prtad, devad, addr, value); | |
01cd4528 | 12804 | |
01cd4528 EG |
12805 | /* The HW expects different devad if CL22 is used */ |
12806 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 12807 | |
01cd4528 | 12808 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 12809 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
12810 | bnx2x_release_phy_lock(bp); |
12811 | return rc; | |
12812 | } | |
c18487ee | 12813 | |
01cd4528 EG |
12814 | /* called with rtnl_lock */ |
12815 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
12816 | { | |
12817 | struct bnx2x *bp = netdev_priv(dev); | |
12818 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 12819 | |
01cd4528 EG |
12820 | if (!netif_running(dev)) |
12821 | return -EAGAIN; | |
12822 | ||
eeed018c MK |
12823 | switch (cmd) { |
12824 | case SIOCSHWTSTAMP: | |
12825 | return bnx2x_hwtstamp_ioctl(bp, ifr); | |
12826 | default: | |
12827 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", | |
12828 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
12829 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
12830 | } | |
a2fbb9ea ET |
12831 | } |
12832 | ||
257ddbda | 12833 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
12834 | static void poll_bnx2x(struct net_device *dev) |
12835 | { | |
12836 | struct bnx2x *bp = netdev_priv(dev); | |
14a15d61 | 12837 | int i; |
a2fbb9ea | 12838 | |
14a15d61 MS |
12839 | for_each_eth_queue(bp, i) { |
12840 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
12841 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); | |
12842 | } | |
a2fbb9ea ET |
12843 | } |
12844 | #endif | |
12845 | ||
614c76df DK |
12846 | static int bnx2x_validate_addr(struct net_device *dev) |
12847 | { | |
12848 | struct bnx2x *bp = netdev_priv(dev); | |
12849 | ||
e09b74d0 AE |
12850 | /* query the bulletin board for mac address configured by the PF */ |
12851 | if (IS_VF(bp)) | |
12852 | bnx2x_sample_bulletin(bp); | |
12853 | ||
2e98ffc2 | 12854 | if (!is_valid_ether_addr(dev->dev_addr)) { |
51c1a580 | 12855 | BNX2X_ERR("Non-valid Ethernet address\n"); |
614c76df | 12856 | return -EADDRNOTAVAIL; |
51c1a580 | 12857 | } |
614c76df DK |
12858 | return 0; |
12859 | } | |
12860 | ||
3d7d562c | 12861 | static int bnx2x_get_phys_port_id(struct net_device *netdev, |
02637fce | 12862 | struct netdev_phys_item_id *ppid) |
3d7d562c YM |
12863 | { |
12864 | struct bnx2x *bp = netdev_priv(netdev); | |
12865 | ||
12866 | if (!(bp->flags & HAS_PHYS_PORT_ID)) | |
12867 | return -EOPNOTSUPP; | |
12868 | ||
12869 | ppid->id_len = sizeof(bp->phys_port_id); | |
12870 | memcpy(ppid->id, bp->phys_port_id, ppid->id_len); | |
12871 | ||
12872 | return 0; | |
12873 | } | |
12874 | ||
5f35227e JG |
12875 | static netdev_features_t bnx2x_features_check(struct sk_buff *skb, |
12876 | struct net_device *dev, | |
12877 | netdev_features_t features) | |
51de7bb9 | 12878 | { |
8cb65d00 | 12879 | features = vlan_features_check(skb, features); |
5f35227e | 12880 | return vxlan_features_check(skb, features); |
51de7bb9 JS |
12881 | } |
12882 | ||
05cc5a39 YM |
12883 | static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add) |
12884 | { | |
12885 | int rc; | |
12886 | ||
12887 | if (IS_PF(bp)) { | |
12888 | unsigned long ramrod_flags = 0; | |
12889 | ||
12890 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
12891 | rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj, | |
12892 | add, &ramrod_flags); | |
12893 | } else { | |
12894 | rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add); | |
12895 | } | |
12896 | ||
12897 | return rc; | |
12898 | } | |
12899 | ||
12900 | int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp) | |
12901 | { | |
12902 | struct bnx2x_vlan_entry *vlan; | |
12903 | int rc = 0; | |
12904 | ||
12905 | if (!bp->vlan_cnt) { | |
12906 | DP(NETIF_MSG_IFUP, "No need to re-configure vlan filters\n"); | |
12907 | return 0; | |
12908 | } | |
12909 | ||
12910 | list_for_each_entry(vlan, &bp->vlan_reg, link) { | |
12911 | /* Prepare for cleanup in case of errors */ | |
12912 | if (rc) { | |
12913 | vlan->hw = false; | |
12914 | continue; | |
12915 | } | |
12916 | ||
12917 | if (!vlan->hw) | |
12918 | continue; | |
12919 | ||
12920 | DP(NETIF_MSG_IFUP, "Re-configuring vlan 0x%04x\n", vlan->vid); | |
12921 | ||
12922 | rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true); | |
12923 | if (rc) { | |
12924 | BNX2X_ERR("Unable to configure VLAN %d\n", vlan->vid); | |
12925 | vlan->hw = false; | |
12926 | rc = -EINVAL; | |
12927 | continue; | |
12928 | } | |
12929 | } | |
12930 | ||
12931 | return rc; | |
12932 | } | |
12933 | ||
12934 | static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) | |
12935 | { | |
12936 | struct bnx2x *bp = netdev_priv(dev); | |
12937 | struct bnx2x_vlan_entry *vlan; | |
12938 | bool hw = false; | |
12939 | int rc = 0; | |
12940 | ||
12941 | if (!netif_running(bp->dev)) { | |
12942 | DP(NETIF_MSG_IFUP, | |
12943 | "Ignoring VLAN configuration the interface is down\n"); | |
12944 | return -EFAULT; | |
12945 | } | |
12946 | ||
12947 | DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid); | |
12948 | ||
12949 | vlan = kmalloc(sizeof(*vlan), GFP_KERNEL); | |
12950 | if (!vlan) | |
12951 | return -ENOMEM; | |
12952 | ||
12953 | bp->vlan_cnt++; | |
12954 | if (bp->vlan_cnt > bp->vlan_credit && !bp->accept_any_vlan) { | |
12955 | DP(NETIF_MSG_IFUP, "Accept all VLAN raised\n"); | |
12956 | bp->accept_any_vlan = true; | |
12957 | if (IS_PF(bp)) | |
12958 | bnx2x_set_rx_mode_inner(bp); | |
12959 | else | |
12960 | bnx2x_vfpf_storm_rx_mode(bp); | |
12961 | } else if (bp->vlan_cnt <= bp->vlan_credit) { | |
12962 | rc = __bnx2x_vlan_configure_vid(bp, vid, true); | |
12963 | hw = true; | |
12964 | } | |
12965 | ||
12966 | vlan->vid = vid; | |
12967 | vlan->hw = hw; | |
12968 | ||
12969 | if (!rc) { | |
12970 | list_add(&vlan->link, &bp->vlan_reg); | |
12971 | } else { | |
12972 | bp->vlan_cnt--; | |
12973 | kfree(vlan); | |
12974 | } | |
12975 | ||
12976 | DP(NETIF_MSG_IFUP, "Adding VLAN result %d\n", rc); | |
12977 | ||
12978 | return rc; | |
12979 | } | |
12980 | ||
12981 | static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) | |
12982 | { | |
12983 | struct bnx2x *bp = netdev_priv(dev); | |
12984 | struct bnx2x_vlan_entry *vlan; | |
12985 | int rc = 0; | |
12986 | ||
12987 | if (!netif_running(bp->dev)) { | |
12988 | DP(NETIF_MSG_IFUP, | |
12989 | "Ignoring VLAN configuration the interface is down\n"); | |
12990 | return -EFAULT; | |
12991 | } | |
12992 | ||
12993 | DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid); | |
12994 | ||
12995 | if (!bp->vlan_cnt) { | |
12996 | BNX2X_ERR("Unable to kill VLAN %d\n", vid); | |
12997 | return -EINVAL; | |
12998 | } | |
12999 | ||
13000 | list_for_each_entry(vlan, &bp->vlan_reg, link) | |
13001 | if (vlan->vid == vid) | |
13002 | break; | |
13003 | ||
13004 | if (vlan->vid != vid) { | |
13005 | BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid); | |
13006 | return -EINVAL; | |
13007 | } | |
13008 | ||
13009 | if (vlan->hw) | |
13010 | rc = __bnx2x_vlan_configure_vid(bp, vid, false); | |
13011 | ||
13012 | list_del(&vlan->link); | |
13013 | kfree(vlan); | |
13014 | ||
13015 | bp->vlan_cnt--; | |
13016 | ||
13017 | if (bp->vlan_cnt <= bp->vlan_credit && bp->accept_any_vlan) { | |
13018 | /* Configure all non-configured entries */ | |
13019 | list_for_each_entry(vlan, &bp->vlan_reg, link) { | |
13020 | if (vlan->hw) | |
13021 | continue; | |
13022 | ||
13023 | rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true); | |
13024 | if (rc) { | |
13025 | BNX2X_ERR("Unable to config VLAN %d\n", | |
13026 | vlan->vid); | |
13027 | continue; | |
13028 | } | |
13029 | DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", | |
13030 | vlan->vid); | |
13031 | vlan->hw = true; | |
13032 | } | |
13033 | DP(NETIF_MSG_IFUP, "Accept all VLAN Removed\n"); | |
13034 | bp->accept_any_vlan = false; | |
13035 | if (IS_PF(bp)) | |
13036 | bnx2x_set_rx_mode_inner(bp); | |
13037 | else | |
13038 | bnx2x_vfpf_storm_rx_mode(bp); | |
13039 | } | |
13040 | ||
13041 | DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc); | |
13042 | ||
13043 | return rc; | |
13044 | } | |
13045 | ||
c64213cd SH |
13046 | static const struct net_device_ops bnx2x_netdev_ops = { |
13047 | .ndo_open = bnx2x_open, | |
13048 | .ndo_stop = bnx2x_close, | |
13049 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 13050 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 13051 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd | 13052 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
614c76df | 13053 | .ndo_validate_addr = bnx2x_validate_addr, |
c64213cd SH |
13054 | .ndo_do_ioctl = bnx2x_ioctl, |
13055 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
13056 | .ndo_fix_features = bnx2x_fix_features, |
13057 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 13058 | .ndo_tx_timeout = bnx2x_tx_timeout, |
05cc5a39 YM |
13059 | .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid, |
13060 | .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid, | |
257ddbda | 13061 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
13062 | .ndo_poll_controller = poll_bnx2x, |
13063 | #endif | |
6383c0b3 | 13064 | .ndo_setup_tc = bnx2x_setup_tc, |
6411280a | 13065 | #ifdef CONFIG_BNX2X_SRIOV |
abc5a021 | 13066 | .ndo_set_vf_mac = bnx2x_set_vf_mac, |
3cdeec22 | 13067 | .ndo_set_vf_vlan = bnx2x_set_vf_vlan, |
3ec9f9ca | 13068 | .ndo_get_vf_config = bnx2x_get_vf_config, |
6411280a | 13069 | #endif |
55c11941 | 13070 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
13071 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, |
13072 | #endif | |
8f20aa57 | 13073 | |
3d7d562c | 13074 | .ndo_get_phys_port_id = bnx2x_get_phys_port_id, |
6495d15a | 13075 | .ndo_set_vf_link_state = bnx2x_set_vf_link_state, |
5f35227e | 13076 | .ndo_features_check = bnx2x_features_check, |
f34fa14c RB |
13077 | #ifdef CONFIG_BNX2X_VXLAN |
13078 | .ndo_add_vxlan_port = bnx2x_add_vxlan_port, | |
13079 | .ndo_del_vxlan_port = bnx2x_del_vxlan_port, | |
13080 | #endif | |
883ce97d YM |
13081 | #if IS_ENABLED(CONFIG_GENEVE) |
13082 | .ndo_add_geneve_port = bnx2x_add_geneve_port, | |
13083 | .ndo_del_geneve_port = bnx2x_del_geneve_port, | |
13084 | #endif | |
c64213cd SH |
13085 | }; |
13086 | ||
1191cb83 | 13087 | static int bnx2x_set_coherency_mask(struct bnx2x *bp) |
619c5cb6 VZ |
13088 | { |
13089 | struct device *dev = &bp->pdev->dev; | |
13090 | ||
8ceafbfa LT |
13091 | if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 && |
13092 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) { | |
619c5cb6 VZ |
13093 | dev_err(dev, "System does not support DMA, aborting\n"); |
13094 | return -EIO; | |
13095 | } | |
13096 | ||
13097 | return 0; | |
13098 | } | |
13099 | ||
33d8e6a5 YM |
13100 | static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp) |
13101 | { | |
13102 | if (bp->flags & AER_ENABLED) { | |
13103 | pci_disable_pcie_error_reporting(bp->pdev); | |
13104 | bp->flags &= ~AER_ENABLED; | |
13105 | } | |
13106 | } | |
13107 | ||
1ab4434c AE |
13108 | static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, |
13109 | struct net_device *dev, unsigned long board_type) | |
a2fbb9ea | 13110 | { |
a2fbb9ea | 13111 | int rc; |
c22610d0 | 13112 | u32 pci_cfg_dword; |
65087cfe AE |
13113 | bool chip_is_e1x = (board_type == BCM57710 || |
13114 | board_type == BCM57711 || | |
13115 | board_type == BCM57711E); | |
a2fbb9ea ET |
13116 | |
13117 | SET_NETDEV_DEV(dev, &pdev->dev); | |
a2fbb9ea | 13118 | |
34f80b04 EG |
13119 | bp->dev = dev; |
13120 | bp->pdev = pdev; | |
a2fbb9ea ET |
13121 | |
13122 | rc = pci_enable_device(pdev); | |
13123 | if (rc) { | |
cdaa7cb8 VZ |
13124 | dev_err(&bp->pdev->dev, |
13125 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
13126 | goto err_out; |
13127 | } | |
13128 | ||
13129 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
13130 | dev_err(&bp->pdev->dev, |
13131 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
13132 | rc = -ENODEV; |
13133 | goto err_out_disable; | |
13134 | } | |
13135 | ||
1ab4434c AE |
13136 | if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { |
13137 | dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); | |
a2fbb9ea ET |
13138 | rc = -ENODEV; |
13139 | goto err_out_disable; | |
13140 | } | |
13141 | ||
092a5fc9 YR |
13142 | pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); |
13143 | if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == | |
13144 | PCICFG_REVESION_ID_ERROR_VAL) { | |
13145 | pr_err("PCI device error, probably due to fan failure, aborting\n"); | |
13146 | rc = -ENODEV; | |
13147 | goto err_out_disable; | |
13148 | } | |
13149 | ||
34f80b04 EG |
13150 | if (atomic_read(&pdev->enable_cnt) == 1) { |
13151 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
13152 | if (rc) { | |
cdaa7cb8 VZ |
13153 | dev_err(&bp->pdev->dev, |
13154 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
13155 | goto err_out_disable; |
13156 | } | |
a2fbb9ea | 13157 | |
34f80b04 EG |
13158 | pci_set_master(pdev); |
13159 | pci_save_state(pdev); | |
13160 | } | |
a2fbb9ea | 13161 | |
1ab4434c | 13162 | if (IS_PF(bp)) { |
29ed74c3 | 13163 | if (!pdev->pm_cap) { |
1ab4434c AE |
13164 | dev_err(&bp->pdev->dev, |
13165 | "Cannot find power management capability, aborting\n"); | |
13166 | rc = -EIO; | |
13167 | goto err_out_release; | |
13168 | } | |
a2fbb9ea ET |
13169 | } |
13170 | ||
77c98e6a | 13171 | if (!pci_is_pcie(pdev)) { |
51c1a580 | 13172 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
a2fbb9ea ET |
13173 | rc = -EIO; |
13174 | goto err_out_release; | |
13175 | } | |
13176 | ||
619c5cb6 VZ |
13177 | rc = bnx2x_set_coherency_mask(bp); |
13178 | if (rc) | |
a2fbb9ea | 13179 | goto err_out_release; |
a2fbb9ea | 13180 | |
34f80b04 EG |
13181 | dev->mem_start = pci_resource_start(pdev, 0); |
13182 | dev->base_addr = dev->mem_start; | |
13183 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
13184 | |
13185 | dev->irq = pdev->irq; | |
13186 | ||
275f165f | 13187 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 13188 | if (!bp->regview) { |
cdaa7cb8 VZ |
13189 | dev_err(&bp->pdev->dev, |
13190 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
13191 | rc = -ENOMEM; |
13192 | goto err_out_release; | |
13193 | } | |
13194 | ||
c22610d0 AE |
13195 | /* In E1/E1H use pci device function given by kernel. |
13196 | * In E2/E3 read physical function from ME register since these chips | |
13197 | * support Physical Device Assignment where kernel BDF maybe arbitrary | |
13198 | * (depending on hypervisor). | |
13199 | */ | |
2de67439 | 13200 | if (chip_is_e1x) { |
c22610d0 | 13201 | bp->pf_num = PCI_FUNC(pdev->devfn); |
2de67439 YM |
13202 | } else { |
13203 | /* chip is E2/3*/ | |
c22610d0 AE |
13204 | pci_read_config_dword(bp->pdev, |
13205 | PCICFG_ME_REGISTER, &pci_cfg_dword); | |
13206 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> | |
2de67439 | 13207 | ME_REG_ABS_PF_NUM_SHIFT); |
c22610d0 | 13208 | } |
51c1a580 | 13209 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
c22610d0 | 13210 | |
34f80b04 EG |
13211 | /* clean indirect addresses */ |
13212 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
13213 | PCICFG_VENDOR_ID_OFFSET); | |
33d8e6a5 | 13214 | |
da293700 BK |
13215 | /* Set PCIe reset type to fundamental for EEH recovery */ |
13216 | pdev->needs_freset = 1; | |
13217 | ||
33d8e6a5 YM |
13218 | /* AER (Advanced Error reporting) configuration */ |
13219 | rc = pci_enable_pcie_error_reporting(pdev); | |
13220 | if (!rc) | |
13221 | bp->flags |= AER_ENABLED; | |
13222 | else | |
13223 | BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc); | |
13224 | ||
a5c53dbc DK |
13225 | /* |
13226 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
13227 | * is not used by the driver. |
13228 | */ | |
1ab4434c AE |
13229 | if (IS_PF(bp)) { |
13230 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
13231 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
13232 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
13233 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
13234 | ||
13235 | if (chip_is_e1x) { | |
13236 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); | |
13237 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
13238 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
13239 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
13240 | } | |
a5c53dbc | 13241 | |
1ab4434c AE |
13242 | /* Enable internal target-read (in case we are probed after PF |
13243 | * FLR). Must be done prior to any BAR read access. Only for | |
13244 | * 57712 and up | |
13245 | */ | |
13246 | if (!chip_is_e1x) | |
13247 | REG_WR(bp, | |
13248 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
a5c53dbc | 13249 | } |
a2fbb9ea | 13250 | |
34f80b04 | 13251 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 13252 | |
c64213cd | 13253 | dev->netdev_ops = &bnx2x_netdev_ops; |
005a07ba | 13254 | bnx2x_set_ethtool_ops(bp, dev); |
5316bc0b | 13255 | |
01789349 JP |
13256 | dev->priv_flags |= IFF_UNICAST_FLT; |
13257 | ||
66371c44 | 13258 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
621b4d66 DK |
13259 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
13260 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | | |
f646968f | 13261 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX; |
a8e0c246 | 13262 | if (!chip_is_e1x) { |
117401ee | 13263 | dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL | |
2e3bd6a4 | 13264 | NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT; |
a848ade4 DK |
13265 | dev->hw_enc_features = |
13266 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | | |
13267 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | | |
117401ee | 13268 | NETIF_F_GSO_IPIP | |
2e3bd6a4 | 13269 | NETIF_F_GSO_SIT | |
65bc0cfe | 13270 | NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL; |
a848ade4 | 13271 | } |
66371c44 MM |
13272 | |
13273 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
13274 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
13275 | ||
05cc5a39 YM |
13276 | /* VF with OLD Hypervisor or old PF do not support filtering */ |
13277 | if (IS_PF(bp)) { | |
ab6d7846 | 13278 | if (chip_is_e1x) |
05cc5a39 YM |
13279 | bp->accept_any_vlan = true; |
13280 | else | |
13281 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
ce7fa78c | 13282 | #ifdef CONFIG_BNX2X_SRIOV |
05cc5a39 YM |
13283 | } else if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) { |
13284 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
ce7fa78c | 13285 | #endif |
05cc5a39 YM |
13286 | } |
13287 | ||
f646968f | 13288 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; |
edd31476 | 13289 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 13290 | |
538dd2e3 MB |
13291 | /* Add Loopback capability to the device */ |
13292 | dev->hw_features |= NETIF_F_LOOPBACK; | |
13293 | ||
98507672 | 13294 | #ifdef BCM_DCBNL |
785b9b1a SR |
13295 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
13296 | #endif | |
13297 | ||
01cd4528 EG |
13298 | /* get_port_hwinfo() will set prtad and mmds properly */ |
13299 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
13300 | bp->mdio.mmds = 0; | |
13301 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
13302 | bp->mdio.dev = dev; | |
13303 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
13304 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
13305 | ||
a2fbb9ea ET |
13306 | return 0; |
13307 | ||
a2fbb9ea | 13308 | err_out_release: |
34f80b04 EG |
13309 | if (atomic_read(&pdev->enable_cnt) == 1) |
13310 | pci_release_regions(pdev); | |
a2fbb9ea ET |
13311 | |
13312 | err_out_disable: | |
13313 | pci_disable_device(pdev); | |
a2fbb9ea ET |
13314 | |
13315 | err_out: | |
13316 | return rc; | |
13317 | } | |
13318 | ||
6891dd25 | 13319 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 13320 | { |
37f9ce62 | 13321 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
13322 | struct bnx2x_fw_file_hdr *fw_hdr; |
13323 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 13324 | u32 offset, len, num_ops; |
86564c3f | 13325 | __be16 *ops_offsets; |
94a78b79 | 13326 | int i; |
37f9ce62 | 13327 | const u8 *fw_ver; |
94a78b79 | 13328 | |
51c1a580 MS |
13329 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
13330 | BNX2X_ERR("Wrong FW size\n"); | |
94a78b79 | 13331 | return -EINVAL; |
51c1a580 | 13332 | } |
94a78b79 VZ |
13333 | |
13334 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
13335 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
13336 | ||
13337 | /* Make sure none of the offsets and sizes make us read beyond | |
13338 | * the end of the firmware data */ | |
13339 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
13340 | offset = be32_to_cpu(sections[i].offset); | |
13341 | len = be32_to_cpu(sections[i].len); | |
13342 | if (offset + len > firmware->size) { | |
51c1a580 | 13343 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
94a78b79 VZ |
13344 | return -EINVAL; |
13345 | } | |
13346 | } | |
13347 | ||
13348 | /* Likewise for the init_ops offsets */ | |
13349 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
86564c3f | 13350 | ops_offsets = (__force __be16 *)(firmware->data + offset); |
94a78b79 VZ |
13351 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); |
13352 | ||
13353 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
13354 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
51c1a580 | 13355 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
94a78b79 VZ |
13356 | return -EINVAL; |
13357 | } | |
13358 | } | |
13359 | ||
13360 | /* Check FW version */ | |
13361 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
13362 | fw_ver = firmware->data + offset; | |
13363 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
13364 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
13365 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
13366 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
51c1a580 MS |
13367 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
13368 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], | |
13369 | BCM_5710_FW_MAJOR_VERSION, | |
94a78b79 VZ |
13370 | BCM_5710_FW_MINOR_VERSION, |
13371 | BCM_5710_FW_REVISION_VERSION, | |
13372 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 13373 | return -EINVAL; |
94a78b79 VZ |
13374 | } |
13375 | ||
13376 | return 0; | |
13377 | } | |
13378 | ||
1191cb83 | 13379 | static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 13380 | { |
ab6ad5a4 EG |
13381 | const __be32 *source = (const __be32 *)_source; |
13382 | u32 *target = (u32 *)_target; | |
94a78b79 | 13383 | u32 i; |
94a78b79 VZ |
13384 | |
13385 | for (i = 0; i < n/4; i++) | |
13386 | target[i] = be32_to_cpu(source[i]); | |
13387 | } | |
13388 | ||
13389 | /* | |
13390 | Ops array is stored in the following format: | |
13391 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
13392 | */ | |
1191cb83 | 13393 | static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 13394 | { |
ab6ad5a4 EG |
13395 | const __be32 *source = (const __be32 *)_source; |
13396 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 13397 | u32 i, j, tmp; |
94a78b79 | 13398 | |
ab6ad5a4 | 13399 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
13400 | tmp = be32_to_cpu(source[j]); |
13401 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
13402 | target[i].offset = tmp & 0xffffff; |
13403 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
13404 | } |
13405 | } | |
ab6ad5a4 | 13406 | |
1aa8b471 | 13407 | /* IRO array is stored in the following format: |
523224a3 DK |
13408 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } |
13409 | */ | |
1191cb83 | 13410 | static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) |
523224a3 DK |
13411 | { |
13412 | const __be32 *source = (const __be32 *)_source; | |
13413 | struct iro *target = (struct iro *)_target; | |
13414 | u32 i, j, tmp; | |
13415 | ||
13416 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
13417 | target[i].base = be32_to_cpu(source[j]); | |
13418 | j++; | |
13419 | tmp = be32_to_cpu(source[j]); | |
13420 | target[i].m1 = (tmp >> 16) & 0xffff; | |
13421 | target[i].m2 = tmp & 0xffff; | |
13422 | j++; | |
13423 | tmp = be32_to_cpu(source[j]); | |
13424 | target[i].m3 = (tmp >> 16) & 0xffff; | |
13425 | target[i].size = tmp & 0xffff; | |
13426 | j++; | |
13427 | } | |
13428 | } | |
13429 | ||
1191cb83 | 13430 | static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 13431 | { |
ab6ad5a4 EG |
13432 | const __be16 *source = (const __be16 *)_source; |
13433 | u16 *target = (u16 *)_target; | |
94a78b79 | 13434 | u32 i; |
94a78b79 VZ |
13435 | |
13436 | for (i = 0; i < n/2; i++) | |
13437 | target[i] = be16_to_cpu(source[i]); | |
13438 | } | |
13439 | ||
7995c64e JP |
13440 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
13441 | do { \ | |
13442 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
13443 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
e404decb | 13444 | if (!bp->arr) \ |
7995c64e | 13445 | goto lbl; \ |
7995c64e JP |
13446 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
13447 | (u8 *)bp->arr, len); \ | |
13448 | } while (0) | |
94a78b79 | 13449 | |
3b603066 | 13450 | static int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 13451 | { |
c0ea452e | 13452 | const char *fw_file_name; |
94a78b79 | 13453 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 13454 | int rc; |
94a78b79 | 13455 | |
c0ea452e MS |
13456 | if (bp->firmware) |
13457 | return 0; | |
94a78b79 | 13458 | |
c0ea452e MS |
13459 | if (CHIP_IS_E1(bp)) |
13460 | fw_file_name = FW_FILE_NAME_E1; | |
13461 | else if (CHIP_IS_E1H(bp)) | |
13462 | fw_file_name = FW_FILE_NAME_E1H; | |
13463 | else if (!CHIP_IS_E1x(bp)) | |
13464 | fw_file_name = FW_FILE_NAME_E2; | |
13465 | else { | |
13466 | BNX2X_ERR("Unsupported chip revision\n"); | |
13467 | return -EINVAL; | |
13468 | } | |
13469 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); | |
94a78b79 | 13470 | |
c0ea452e MS |
13471 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
13472 | if (rc) { | |
13473 | BNX2X_ERR("Can't load firmware file %s\n", | |
13474 | fw_file_name); | |
13475 | goto request_firmware_exit; | |
13476 | } | |
eb2afd4a | 13477 | |
c0ea452e MS |
13478 | rc = bnx2x_check_firmware(bp); |
13479 | if (rc) { | |
13480 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); | |
13481 | goto request_firmware_exit; | |
94a78b79 VZ |
13482 | } |
13483 | ||
13484 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
13485 | ||
13486 | /* Initialize the pointers to the init arrays */ | |
13487 | /* Blob */ | |
13488 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
13489 | ||
13490 | /* Opcodes */ | |
13491 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
13492 | ||
13493 | /* Offsets */ | |
ab6ad5a4 EG |
13494 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
13495 | be16_to_cpu_n); | |
94a78b79 VZ |
13496 | |
13497 | /* STORMs firmware */ | |
573f2035 EG |
13498 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
13499 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
13500 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
13501 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
13502 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
13503 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
13504 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
13505 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
13506 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
13507 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
13508 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
13509 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
13510 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
13511 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
13512 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
13513 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
13514 | /* IRO */ |
13515 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
13516 | |
13517 | return 0; | |
ab6ad5a4 | 13518 | |
523224a3 DK |
13519 | iro_alloc_err: |
13520 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
13521 | init_offsets_alloc_err: |
13522 | kfree(bp->init_ops); | |
13523 | init_ops_alloc_err: | |
13524 | kfree(bp->init_data); | |
13525 | request_firmware_exit: | |
13526 | release_firmware(bp->firmware); | |
127d0a19 | 13527 | bp->firmware = NULL; |
94a78b79 VZ |
13528 | |
13529 | return rc; | |
13530 | } | |
13531 | ||
619c5cb6 VZ |
13532 | static void bnx2x_release_firmware(struct bnx2x *bp) |
13533 | { | |
13534 | kfree(bp->init_ops_offsets); | |
13535 | kfree(bp->init_ops); | |
13536 | kfree(bp->init_data); | |
13537 | release_firmware(bp->firmware); | |
eb2afd4a | 13538 | bp->firmware = NULL; |
619c5cb6 VZ |
13539 | } |
13540 | ||
619c5cb6 VZ |
13541 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { |
13542 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
13543 | .init_hw_cmn = bnx2x_init_hw_common, | |
13544 | .init_hw_port = bnx2x_init_hw_port, | |
13545 | .init_hw_func = bnx2x_init_hw_func, | |
13546 | ||
13547 | .reset_hw_cmn = bnx2x_reset_common, | |
13548 | .reset_hw_port = bnx2x_reset_port, | |
13549 | .reset_hw_func = bnx2x_reset_func, | |
13550 | ||
13551 | .gunzip_init = bnx2x_gunzip_init, | |
13552 | .gunzip_end = bnx2x_gunzip_end, | |
13553 | ||
13554 | .init_fw = bnx2x_init_firmware, | |
13555 | .release_fw = bnx2x_release_firmware, | |
13556 | }; | |
13557 | ||
13558 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
13559 | { | |
13560 | /* Prepare DMAE related driver resources */ | |
13561 | bnx2x_setup_dmae(bp); | |
13562 | ||
13563 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
13564 | bnx2x_sp(bp, func_rdata), | |
13565 | bnx2x_sp_mapping(bp, func_rdata), | |
a3348722 BW |
13566 | bnx2x_sp(bp, func_afex_rdata), |
13567 | bnx2x_sp_mapping(bp, func_afex_rdata), | |
619c5cb6 VZ |
13568 | &bnx2x_func_sp_drv); |
13569 | } | |
13570 | ||
13571 | /* must be called after sriov-enable */ | |
1191cb83 | 13572 | static int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 13573 | { |
37ae41a9 | 13574 | int cid_count = BNX2X_L2_MAX_CID(bp); |
94a78b79 | 13575 | |
290ca2bb AE |
13576 | if (IS_SRIOV(bp)) |
13577 | cid_count += BNX2X_VF_CIDS; | |
13578 | ||
55c11941 MS |
13579 | if (CNIC_SUPPORT(bp)) |
13580 | cid_count += CNIC_CID_MAX; | |
290ca2bb | 13581 | |
523224a3 DK |
13582 | return roundup(cid_count, QM_CID_ROUND); |
13583 | } | |
f85582f8 | 13584 | |
619c5cb6 | 13585 | /** |
6383c0b3 | 13586 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
13587 | * |
13588 | * @dev: pci device | |
13589 | * | |
13590 | */ | |
60cad4e6 | 13591 | static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt) |
619c5cb6 | 13592 | { |
ae2104be | 13593 | int index; |
1ab4434c | 13594 | u16 control = 0; |
619c5cb6 | 13595 | |
6383c0b3 AE |
13596 | /* |
13597 | * If MSI-X is not supported - return number of SBs needed to support | |
13598 | * one fast path queue: one FP queue + SB for CNIC | |
13599 | */ | |
ae2104be | 13600 | if (!pdev->msix_cap) { |
1ab4434c | 13601 | dev_info(&pdev->dev, "no msix capability found\n"); |
55c11941 | 13602 | return 1 + cnic_cnt; |
1ab4434c AE |
13603 | } |
13604 | dev_info(&pdev->dev, "msix capability found\n"); | |
619c5cb6 | 13605 | |
6383c0b3 AE |
13606 | /* |
13607 | * The value in the PCI configuration space is the index of the last | |
13608 | * entry, namely one less than the actual size of the table, which is | |
13609 | * exactly what we want to return from this function: number of all SBs | |
13610 | * without the default SB. | |
1ab4434c | 13611 | * For VFs there is no default SB, then we return (index+1). |
6383c0b3 | 13612 | */ |
73413ffa | 13613 | pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control); |
619c5cb6 | 13614 | |
1ab4434c | 13615 | index = control & PCI_MSIX_FLAGS_QSIZE; |
4bd9b0ff | 13616 | |
60cad4e6 | 13617 | return index; |
1ab4434c | 13618 | } |
523224a3 | 13619 | |
1ab4434c AE |
13620 | static int set_max_cos_est(int chip_id) |
13621 | { | |
13622 | switch (chip_id) { | |
f2e0899f DK |
13623 | case BCM57710: |
13624 | case BCM57711: | |
13625 | case BCM57711E: | |
1ab4434c | 13626 | return BNX2X_MULTI_TX_COS_E1X; |
f2e0899f | 13627 | case BCM57712: |
619c5cb6 | 13628 | case BCM57712_MF: |
1ab4434c | 13629 | return BNX2X_MULTI_TX_COS_E2_E3A0; |
619c5cb6 VZ |
13630 | case BCM57800: |
13631 | case BCM57800_MF: | |
13632 | case BCM57810: | |
13633 | case BCM57810_MF: | |
c3def943 YM |
13634 | case BCM57840_4_10: |
13635 | case BCM57840_2_20: | |
1ab4434c | 13636 | case BCM57840_O: |
c3def943 | 13637 | case BCM57840_MFO: |
619c5cb6 | 13638 | case BCM57840_MF: |
7e8e02df BW |
13639 | case BCM57811: |
13640 | case BCM57811_MF: | |
1ab4434c | 13641 | return BNX2X_MULTI_TX_COS_E3B0; |
b1239723 YM |
13642 | case BCM57712_VF: |
13643 | case BCM57800_VF: | |
13644 | case BCM57810_VF: | |
13645 | case BCM57840_VF: | |
13646 | case BCM57811_VF: | |
1ab4434c | 13647 | return 1; |
f2e0899f | 13648 | default: |
1ab4434c | 13649 | pr_err("Unknown board_type (%d), aborting\n", chip_id); |
870634b0 | 13650 | return -ENODEV; |
f2e0899f | 13651 | } |
1ab4434c | 13652 | } |
f2e0899f | 13653 | |
1ab4434c AE |
13654 | static int set_is_vf(int chip_id) |
13655 | { | |
13656 | switch (chip_id) { | |
13657 | case BCM57712_VF: | |
13658 | case BCM57800_VF: | |
13659 | case BCM57810_VF: | |
13660 | case BCM57840_VF: | |
13661 | case BCM57811_VF: | |
13662 | return true; | |
13663 | default: | |
13664 | return false; | |
13665 | } | |
13666 | } | |
6383c0b3 | 13667 | |
eeed018c MK |
13668 | /* nig_tsgen registers relative address */ |
13669 | #define tsgen_ctrl 0x0 | |
13670 | #define tsgen_freecount 0x10 | |
13671 | #define tsgen_synctime_t0 0x20 | |
13672 | #define tsgen_offset_t0 0x28 | |
13673 | #define tsgen_drift_t0 0x30 | |
13674 | #define tsgen_synctime_t1 0x58 | |
13675 | #define tsgen_offset_t1 0x60 | |
13676 | #define tsgen_drift_t1 0x68 | |
13677 | ||
13678 | /* FW workaround for setting drift */ | |
13679 | static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir, | |
13680 | int best_val, int best_period) | |
13681 | { | |
13682 | struct bnx2x_func_state_params func_params = {NULL}; | |
13683 | struct bnx2x_func_set_timesync_params *set_timesync_params = | |
13684 | &func_params.params.set_timesync; | |
13685 | ||
13686 | /* Prepare parameters for function state transitions */ | |
13687 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
13688 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
13689 | ||
13690 | func_params.f_obj = &bp->func_obj; | |
13691 | func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; | |
13692 | ||
13693 | /* Function parameters */ | |
13694 | set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET; | |
13695 | set_timesync_params->offset_cmd = TS_OFFSET_KEEP; | |
13696 | set_timesync_params->add_sub_drift_adjust_value = | |
13697 | drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE; | |
13698 | set_timesync_params->drift_adjust_value = best_val; | |
13699 | set_timesync_params->drift_adjust_period = best_period; | |
13700 | ||
13701 | return bnx2x_func_state_change(bp, &func_params); | |
13702 | } | |
13703 | ||
13704 | static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) | |
13705 | { | |
13706 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13707 | int rc; | |
13708 | int drift_dir = 1; | |
13709 | int val, period, period1, period2, dif, dif1, dif2; | |
13710 | int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0; | |
13711 | ||
13712 | DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb); | |
13713 | ||
13714 | if (!netif_running(bp->dev)) { | |
13715 | DP(BNX2X_MSG_PTP, | |
13716 | "PTP adjfreq called while the interface is down\n"); | |
13717 | return -EFAULT; | |
13718 | } | |
13719 | ||
13720 | if (ppb < 0) { | |
13721 | ppb = -ppb; | |
13722 | drift_dir = 0; | |
13723 | } | |
13724 | ||
13725 | if (ppb == 0) { | |
13726 | best_val = 1; | |
13727 | best_period = 0x1FFFFFF; | |
13728 | } else if (ppb >= BNX2X_MAX_PHC_DRIFT) { | |
13729 | best_val = 31; | |
13730 | best_period = 1; | |
13731 | } else { | |
13732 | /* Changed not to allow val = 8, 16, 24 as these values | |
13733 | * are not supported in workaround. | |
13734 | */ | |
13735 | for (val = 0; val <= 31; val++) { | |
13736 | if ((val & 0x7) == 0) | |
13737 | continue; | |
13738 | period1 = val * 1000000 / ppb; | |
13739 | period2 = period1 + 1; | |
13740 | if (period1 != 0) | |
13741 | dif1 = ppb - (val * 1000000 / period1); | |
13742 | else | |
13743 | dif1 = BNX2X_MAX_PHC_DRIFT; | |
13744 | if (dif1 < 0) | |
13745 | dif1 = -dif1; | |
13746 | dif2 = ppb - (val * 1000000 / period2); | |
13747 | if (dif2 < 0) | |
13748 | dif2 = -dif2; | |
13749 | dif = (dif1 < dif2) ? dif1 : dif2; | |
13750 | period = (dif1 < dif2) ? period1 : period2; | |
13751 | if (dif < best_dif) { | |
13752 | best_dif = dif; | |
13753 | best_val = val; | |
13754 | best_period = period; | |
13755 | } | |
13756 | } | |
13757 | } | |
13758 | ||
13759 | rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val, | |
13760 | best_period); | |
13761 | if (rc) { | |
13762 | BNX2X_ERR("Failed to set drift\n"); | |
13763 | return -EFAULT; | |
13764 | } | |
13765 | ||
bf27c353 | 13766 | DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val, |
eeed018c MK |
13767 | best_period); |
13768 | ||
13769 | return 0; | |
13770 | } | |
13771 | ||
13772 | static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) | |
13773 | { | |
13774 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
eeed018c MK |
13775 | |
13776 | DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta); | |
13777 | ||
2e5601f9 | 13778 | timecounter_adjtime(&bp->timecounter, delta); |
eeed018c MK |
13779 | |
13780 | return 0; | |
13781 | } | |
13782 | ||
5d45186b | 13783 | static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) |
eeed018c MK |
13784 | { |
13785 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13786 | u64 ns; | |
eeed018c MK |
13787 | |
13788 | ns = timecounter_read(&bp->timecounter); | |
13789 | ||
13790 | DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns); | |
13791 | ||
f7dcdefe | 13792 | *ts = ns_to_timespec64(ns); |
eeed018c MK |
13793 | |
13794 | return 0; | |
13795 | } | |
13796 | ||
13797 | static int bnx2x_ptp_settime(struct ptp_clock_info *ptp, | |
5d45186b | 13798 | const struct timespec64 *ts) |
eeed018c MK |
13799 | { |
13800 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13801 | u64 ns; | |
13802 | ||
f7dcdefe | 13803 | ns = timespec64_to_ns(ts); |
eeed018c MK |
13804 | |
13805 | DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns); | |
13806 | ||
13807 | /* Re-init the timecounter */ | |
13808 | timecounter_init(&bp->timecounter, &bp->cyclecounter, ns); | |
13809 | ||
13810 | return 0; | |
13811 | } | |
13812 | ||
13813 | /* Enable (or disable) ancillary features of the phc subsystem */ | |
13814 | static int bnx2x_ptp_enable(struct ptp_clock_info *ptp, | |
13815 | struct ptp_clock_request *rq, int on) | |
13816 | { | |
13817 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13818 | ||
13819 | BNX2X_ERR("PHC ancillary features are not supported\n"); | |
13820 | return -ENOTSUPP; | |
13821 | } | |
13822 | ||
1444c301 | 13823 | static void bnx2x_register_phc(struct bnx2x *bp) |
eeed018c MK |
13824 | { |
13825 | /* Fill the ptp_clock_info struct and register PTP clock*/ | |
13826 | bp->ptp_clock_info.owner = THIS_MODULE; | |
13827 | snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name); | |
13828 | bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */ | |
13829 | bp->ptp_clock_info.n_alarm = 0; | |
13830 | bp->ptp_clock_info.n_ext_ts = 0; | |
13831 | bp->ptp_clock_info.n_per_out = 0; | |
13832 | bp->ptp_clock_info.pps = 0; | |
13833 | bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq; | |
13834 | bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime; | |
5d45186b RC |
13835 | bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime; |
13836 | bp->ptp_clock_info.settime64 = bnx2x_ptp_settime; | |
eeed018c MK |
13837 | bp->ptp_clock_info.enable = bnx2x_ptp_enable; |
13838 | ||
13839 | bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev); | |
13840 | if (IS_ERR(bp->ptp_clock)) { | |
13841 | bp->ptp_clock = NULL; | |
13842 | BNX2X_ERR("PTP clock registeration failed\n"); | |
13843 | } | |
13844 | } | |
13845 | ||
1ab4434c AE |
13846 | static int bnx2x_init_one(struct pci_dev *pdev, |
13847 | const struct pci_device_id *ent) | |
13848 | { | |
13849 | struct net_device *dev = NULL; | |
13850 | struct bnx2x *bp; | |
b91e1a1a YM |
13851 | enum pcie_link_width pcie_width; |
13852 | enum pci_bus_speed pcie_speed; | |
1ab4434c AE |
13853 | int rc, max_non_def_sbs; |
13854 | int rx_count, tx_count, rss_count, doorbell_size; | |
13855 | int max_cos_est; | |
13856 | bool is_vf; | |
13857 | int cnic_cnt; | |
13858 | ||
12a8541d YM |
13859 | /* Management FW 'remembers' living interfaces. Allow it some time |
13860 | * to forget previously living interfaces, allowing a proper re-load. | |
13861 | */ | |
cd9c3997 MS |
13862 | if (is_kdump_kernel()) { |
13863 | ktime_t now = ktime_get_boottime(); | |
13864 | ktime_t fw_ready_time = ktime_set(5, 0); | |
13865 | ||
13866 | if (ktime_before(now, fw_ready_time)) | |
13867 | msleep(ktime_ms_delta(fw_ready_time, now)); | |
13868 | } | |
12a8541d | 13869 | |
1ab4434c AE |
13870 | /* An estimated maximum supported CoS number according to the chip |
13871 | * version. | |
13872 | * We will try to roughly estimate the maximum number of CoSes this chip | |
13873 | * may support in order to minimize the memory allocated for Tx | |
13874 | * netdev_queue's. This number will be accurately calculated during the | |
13875 | * initialization of bp->max_cos based on the chip versions AND chip | |
13876 | * revision in the bnx2x_init_bp(). | |
13877 | */ | |
13878 | max_cos_est = set_max_cos_est(ent->driver_data); | |
13879 | if (max_cos_est < 0) | |
13880 | return max_cos_est; | |
13881 | is_vf = set_is_vf(ent->driver_data); | |
13882 | cnic_cnt = is_vf ? 0 : 1; | |
13883 | ||
60cad4e6 AE |
13884 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt); |
13885 | ||
13886 | /* add another SB for VF as it has no default SB */ | |
13887 | max_non_def_sbs += is_vf ? 1 : 0; | |
6383c0b3 AE |
13888 | |
13889 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
60cad4e6 | 13890 | rss_count = max_non_def_sbs - cnic_cnt; |
1ab4434c AE |
13891 | |
13892 | if (rss_count < 1) | |
13893 | return -EINVAL; | |
6383c0b3 AE |
13894 | |
13895 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
55c11941 | 13896 | rx_count = rss_count + cnic_cnt; |
6383c0b3 | 13897 | |
1ab4434c | 13898 | /* Maximum number of netdev Tx queues: |
37ae41a9 | 13899 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 |
6383c0b3 | 13900 | */ |
55c11941 | 13901 | tx_count = rss_count * max_cos_est + cnic_cnt; |
f85582f8 | 13902 | |
a2fbb9ea | 13903 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 13904 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
41de8d4c | 13905 | if (!dev) |
a2fbb9ea ET |
13906 | return -ENOMEM; |
13907 | ||
a2fbb9ea | 13908 | bp = netdev_priv(dev); |
a2fbb9ea | 13909 | |
1ab4434c AE |
13910 | bp->flags = 0; |
13911 | if (is_vf) | |
13912 | bp->flags |= IS_VF_FLAG; | |
13913 | ||
6383c0b3 | 13914 | bp->igu_sb_cnt = max_non_def_sbs; |
1ab4434c | 13915 | bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; |
6383c0b3 | 13916 | bp->msg_enable = debug; |
55c11941 | 13917 | bp->cnic_support = cnic_cnt; |
4bd9b0ff | 13918 | bp->cnic_probe = bnx2x_cnic_probe; |
55c11941 | 13919 | |
6383c0b3 | 13920 | pci_set_drvdata(pdev, dev); |
523224a3 | 13921 | |
1ab4434c | 13922 | rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); |
a2fbb9ea ET |
13923 | if (rc < 0) { |
13924 | free_netdev(dev); | |
13925 | return rc; | |
13926 | } | |
13927 | ||
1ab4434c AE |
13928 | BNX2X_DEV_INFO("This is a %s function\n", |
13929 | IS_PF(bp) ? "physical" : "virtual"); | |
55c11941 | 13930 | BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); |
1ab4434c | 13931 | BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); |
60aa0509 | 13932 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
2de67439 | 13933 | tx_count, rx_count); |
60aa0509 | 13934 | |
34f80b04 | 13935 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
13936 | if (rc) |
13937 | goto init_one_exit; | |
13938 | ||
1ab4434c AE |
13939 | /* Map doorbells here as we need the real value of bp->max_cos which |
13940 | * is initialized in bnx2x_init_bp() to determine the number of | |
13941 | * l2 connections. | |
6383c0b3 | 13942 | */ |
1ab4434c | 13943 | if (IS_VF(bp)) { |
1d6f3cd8 | 13944 | bp->doorbells = bnx2x_vf_doorbells(bp); |
6411280a AE |
13945 | rc = bnx2x_vf_pci_alloc(bp); |
13946 | if (rc) | |
13947 | goto init_one_exit; | |
1ab4434c AE |
13948 | } else { |
13949 | doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); | |
13950 | if (doorbell_size > pci_resource_len(pdev, 2)) { | |
13951 | dev_err(&bp->pdev->dev, | |
13952 | "Cannot map doorbells, bar size too small, aborting\n"); | |
13953 | rc = -ENOMEM; | |
13954 | goto init_one_exit; | |
13955 | } | |
13956 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), | |
13957 | doorbell_size); | |
37ae41a9 | 13958 | } |
6383c0b3 AE |
13959 | if (!bp->doorbells) { |
13960 | dev_err(&bp->pdev->dev, | |
13961 | "Cannot map doorbell space, aborting\n"); | |
13962 | rc = -ENOMEM; | |
13963 | goto init_one_exit; | |
13964 | } | |
13965 | ||
be1f1ffa AE |
13966 | if (IS_VF(bp)) { |
13967 | rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); | |
13968 | if (rc) | |
13969 | goto init_one_exit; | |
13970 | } | |
13971 | ||
3c76feff AE |
13972 | /* Enable SRIOV if capability found in configuration space */ |
13973 | rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); | |
290ca2bb AE |
13974 | if (rc) |
13975 | goto init_one_exit; | |
13976 | ||
523224a3 | 13977 | /* calc qm_cid_count */ |
6383c0b3 | 13978 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
1ab4434c | 13979 | BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); |
523224a3 | 13980 | |
55c11941 | 13981 | /* disable FCOE L2 queue for E1x*/ |
62ac0dc9 | 13982 | if (CHIP_IS_E1x(bp)) |
ec6ba945 VZ |
13983 | bp->flags |= NO_FCOE_FLAG; |
13984 | ||
0e8d2ec5 MS |
13985 | /* Set bp->num_queues for MSI-X mode*/ |
13986 | bnx2x_set_num_queues(bp); | |
13987 | ||
25985edc | 13988 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
0e8d2ec5 | 13989 | * needed. |
d6214d7a | 13990 | */ |
1ab4434c AE |
13991 | rc = bnx2x_set_int_mode(bp); |
13992 | if (rc) { | |
13993 | dev_err(&pdev->dev, "Cannot set interrupts\n"); | |
13994 | goto init_one_exit; | |
13995 | } | |
04c46736 | 13996 | BNX2X_DEV_INFO("set interrupts successfully\n"); |
d6214d7a | 13997 | |
1ab4434c | 13998 | /* register the net device */ |
b340007f VZ |
13999 | rc = register_netdev(dev); |
14000 | if (rc) { | |
14001 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
14002 | goto init_one_exit; | |
14003 | } | |
1ab4434c | 14004 | BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); |
b340007f | 14005 | |
ec6ba945 VZ |
14006 | if (!NO_FCOE(bp)) { |
14007 | /* Add storage MAC address */ | |
14008 | rtnl_lock(); | |
14009 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
14010 | rtnl_unlock(); | |
14011 | } | |
b91e1a1a YM |
14012 | if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) || |
14013 | pcie_speed == PCI_SPEED_UNKNOWN || | |
14014 | pcie_width == PCIE_LNK_WIDTH_UNKNOWN) | |
14015 | BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n"); | |
14016 | else | |
14017 | BNX2X_DEV_INFO( | |
14018 | "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", | |
ca1ee4b2 DK |
14019 | board_info[ent->driver_data].name, |
14020 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
14021 | pcie_width, | |
b91e1a1a YM |
14022 | pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" : |
14023 | pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" : | |
14024 | pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" : | |
ca1ee4b2 DK |
14025 | "Unknown", |
14026 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
c016201c | 14027 | |
eeed018c MK |
14028 | bnx2x_register_phc(bp); |
14029 | ||
230d00eb YM |
14030 | if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) |
14031 | bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED); | |
14032 | ||
a2fbb9ea | 14033 | return 0; |
34f80b04 EG |
14034 | |
14035 | init_one_exit: | |
33d8e6a5 YM |
14036 | bnx2x_disable_pcie_error_reporting(bp); |
14037 | ||
34f80b04 EG |
14038 | if (bp->regview) |
14039 | iounmap(bp->regview); | |
14040 | ||
1ab4434c | 14041 | if (IS_PF(bp) && bp->doorbells) |
34f80b04 EG |
14042 | iounmap(bp->doorbells); |
14043 | ||
14044 | free_netdev(dev); | |
14045 | ||
14046 | if (atomic_read(&pdev->enable_cnt) == 1) | |
14047 | pci_release_regions(pdev); | |
14048 | ||
14049 | pci_disable_device(pdev); | |
34f80b04 EG |
14050 | |
14051 | return rc; | |
a2fbb9ea ET |
14052 | } |
14053 | ||
b030ed2f YM |
14054 | static void __bnx2x_remove(struct pci_dev *pdev, |
14055 | struct net_device *dev, | |
14056 | struct bnx2x *bp, | |
14057 | bool remove_netdev) | |
a2fbb9ea | 14058 | { |
eeed018c MK |
14059 | if (bp->ptp_clock) { |
14060 | ptp_clock_unregister(bp->ptp_clock); | |
14061 | bp->ptp_clock = NULL; | |
14062 | } | |
14063 | ||
ec6ba945 VZ |
14064 | /* Delete storage MAC address */ |
14065 | if (!NO_FCOE(bp)) { | |
14066 | rtnl_lock(); | |
14067 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
14068 | rtnl_unlock(); | |
14069 | } | |
ec6ba945 | 14070 | |
98507672 SR |
14071 | #ifdef BCM_DCBNL |
14072 | /* Delete app tlvs from dcbnl */ | |
14073 | bnx2x_dcbnl_update_applist(bp, true); | |
14074 | #endif | |
14075 | ||
a6d3a5ba BW |
14076 | if (IS_PF(bp) && |
14077 | !BP_NOMCP(bp) && | |
14078 | (bp->flags & BC_SUPPORTS_RMMOD_CMD)) | |
14079 | bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); | |
14080 | ||
b030ed2f YM |
14081 | /* Close the interface - either directly or implicitly */ |
14082 | if (remove_netdev) { | |
14083 | unregister_netdev(dev); | |
14084 | } else { | |
14085 | rtnl_lock(); | |
6ef5a92c | 14086 | dev_close(dev); |
b030ed2f YM |
14087 | rtnl_unlock(); |
14088 | } | |
a2fbb9ea | 14089 | |
78c3bcc5 AE |
14090 | bnx2x_iov_remove_one(bp); |
14091 | ||
084d6cbb | 14092 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
04860eb7 | 14093 | if (IS_PF(bp)) { |
1ab4434c | 14094 | bnx2x_set_power_state(bp, PCI_D0); |
230d00eb | 14095 | bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED); |
084d6cbb | 14096 | |
04860eb7 MC |
14097 | /* Set endianity registers to reset values in case next driver |
14098 | * boots in different endianty environment. | |
14099 | */ | |
14100 | bnx2x_reset_endianity(bp); | |
14101 | } | |
14102 | ||
d6214d7a DK |
14103 | /* Disable MSI/MSI-X */ |
14104 | bnx2x_disable_msi(bp); | |
f85582f8 | 14105 | |
084d6cbb | 14106 | /* Power off */ |
1ab4434c AE |
14107 | if (IS_PF(bp)) |
14108 | bnx2x_set_power_state(bp, PCI_D3hot); | |
084d6cbb | 14109 | |
72fd0718 | 14110 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 14111 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
290ca2bb | 14112 | |
4513f925 AE |
14113 | /* send message via vfpf channel to release the resources of this vf */ |
14114 | if (IS_VF(bp)) | |
14115 | bnx2x_vfpf_release(bp); | |
72fd0718 | 14116 | |
b030ed2f YM |
14117 | /* Assumes no further PCIe PM changes will occur */ |
14118 | if (system_state == SYSTEM_POWER_OFF) { | |
14119 | pci_wake_from_d3(pdev, bp->wol); | |
14120 | pci_set_power_state(pdev, PCI_D3hot); | |
14121 | } | |
14122 | ||
33d8e6a5 | 14123 | bnx2x_disable_pcie_error_reporting(bp); |
d9aee591 YM |
14124 | if (remove_netdev) { |
14125 | if (bp->regview) | |
14126 | iounmap(bp->regview); | |
33d8e6a5 | 14127 | |
d9aee591 YM |
14128 | /* For vfs, doorbells are part of the regview and were unmapped |
14129 | * along with it. FW is only loaded by PF. | |
14130 | */ | |
14131 | if (IS_PF(bp)) { | |
14132 | if (bp->doorbells) | |
14133 | iounmap(bp->doorbells); | |
eb2afd4a | 14134 | |
d9aee591 | 14135 | bnx2x_release_firmware(bp); |
e2a367f8 YM |
14136 | } else { |
14137 | bnx2x_vf_pci_dealloc(bp); | |
d9aee591 YM |
14138 | } |
14139 | bnx2x_free_mem_bp(bp); | |
523224a3 | 14140 | |
b030ed2f | 14141 | free_netdev(dev); |
34f80b04 | 14142 | |
d9aee591 YM |
14143 | if (atomic_read(&pdev->enable_cnt) == 1) |
14144 | pci_release_regions(pdev); | |
34f80b04 | 14145 | |
5f6db130 YM |
14146 | pci_disable_device(pdev); |
14147 | } | |
a2fbb9ea ET |
14148 | } |
14149 | ||
b030ed2f YM |
14150 | static void bnx2x_remove_one(struct pci_dev *pdev) |
14151 | { | |
14152 | struct net_device *dev = pci_get_drvdata(pdev); | |
14153 | struct bnx2x *bp; | |
14154 | ||
14155 | if (!dev) { | |
14156 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); | |
14157 | return; | |
14158 | } | |
14159 | bp = netdev_priv(dev); | |
14160 | ||
14161 | __bnx2x_remove(pdev, dev, bp, true); | |
14162 | } | |
14163 | ||
f8ef6e44 YG |
14164 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
14165 | { | |
7fa6f340 | 14166 | bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; |
f8ef6e44 YG |
14167 | |
14168 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
14169 | ||
55c11941 MS |
14170 | if (CNIC_LOADED(bp)) |
14171 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
14172 | ||
619c5cb6 VZ |
14173 | /* Stop Tx */ |
14174 | bnx2x_tx_disable(bp); | |
26614ba5 MS |
14175 | /* Delete all NAPI objects */ |
14176 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
14177 | if (CNIC_LOADED(bp)) |
14178 | bnx2x_del_all_napi_cnic(bp); | |
7fa6f340 | 14179 | netdev_reset_tc(bp->dev); |
f8ef6e44 YG |
14180 | |
14181 | del_timer_sync(&bp->timer); | |
0c0e6341 | 14182 | cancel_delayed_work_sync(&bp->sp_task); |
14183 | cancel_delayed_work_sync(&bp->period_task); | |
619c5cb6 | 14184 | |
c6e36d8c YM |
14185 | if (!down_timeout(&bp->stats_lock, HZ / 10)) { |
14186 | bp->stats_state = STATS_STATE_DISABLED; | |
14187 | up(&bp->stats_lock); | |
14188 | } | |
f8ef6e44 | 14189 | |
7fa6f340 | 14190 | bnx2x_save_statistics(bp); |
f8ef6e44 | 14191 | |
619c5cb6 VZ |
14192 | netif_carrier_off(bp->dev); |
14193 | ||
f8ef6e44 YG |
14194 | return 0; |
14195 | } | |
14196 | ||
493adb1f WX |
14197 | /** |
14198 | * bnx2x_io_error_detected - called when PCI error is detected | |
14199 | * @pdev: Pointer to PCI device | |
14200 | * @state: The current pci connection state | |
14201 | * | |
14202 | * This function is called after a PCI bus error affecting | |
14203 | * this device has been detected. | |
14204 | */ | |
14205 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
14206 | pci_channel_state_t state) | |
14207 | { | |
14208 | struct net_device *dev = pci_get_drvdata(pdev); | |
14209 | struct bnx2x *bp = netdev_priv(dev); | |
14210 | ||
14211 | rtnl_lock(); | |
14212 | ||
7fa6f340 YM |
14213 | BNX2X_ERR("IO error detected\n"); |
14214 | ||
493adb1f WX |
14215 | netif_device_detach(dev); |
14216 | ||
07ce50e4 DN |
14217 | if (state == pci_channel_io_perm_failure) { |
14218 | rtnl_unlock(); | |
14219 | return PCI_ERS_RESULT_DISCONNECT; | |
14220 | } | |
14221 | ||
493adb1f | 14222 | if (netif_running(dev)) |
f8ef6e44 | 14223 | bnx2x_eeh_nic_unload(bp); |
493adb1f | 14224 | |
7fa6f340 YM |
14225 | bnx2x_prev_path_mark_eeh(bp); |
14226 | ||
493adb1f WX |
14227 | pci_disable_device(pdev); |
14228 | ||
14229 | rtnl_unlock(); | |
14230 | ||
14231 | /* Request a slot reset */ | |
14232 | return PCI_ERS_RESULT_NEED_RESET; | |
14233 | } | |
14234 | ||
14235 | /** | |
14236 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
14237 | * @pdev: Pointer to PCI device | |
14238 | * | |
14239 | * Restart the card from scratch, as if from a cold-boot. | |
14240 | */ | |
14241 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
14242 | { | |
14243 | struct net_device *dev = pci_get_drvdata(pdev); | |
14244 | struct bnx2x *bp = netdev_priv(dev); | |
7fa6f340 | 14245 | int i; |
493adb1f WX |
14246 | |
14247 | rtnl_lock(); | |
7fa6f340 | 14248 | BNX2X_ERR("IO slot reset initializing...\n"); |
493adb1f WX |
14249 | if (pci_enable_device(pdev)) { |
14250 | dev_err(&pdev->dev, | |
14251 | "Cannot re-enable PCI device after reset\n"); | |
14252 | rtnl_unlock(); | |
14253 | return PCI_ERS_RESULT_DISCONNECT; | |
14254 | } | |
14255 | ||
14256 | pci_set_master(pdev); | |
14257 | pci_restore_state(pdev); | |
70632d0a | 14258 | pci_save_state(pdev); |
493adb1f WX |
14259 | |
14260 | if (netif_running(dev)) | |
14261 | bnx2x_set_power_state(bp, PCI_D0); | |
14262 | ||
7fa6f340 YM |
14263 | if (netif_running(dev)) { |
14264 | BNX2X_ERR("IO slot reset --> driver unload\n"); | |
e68072ef YM |
14265 | |
14266 | /* MCP should have been reset; Need to wait for validity */ | |
14267 | bnx2x_init_shmem(bp); | |
14268 | ||
7fa6f340 YM |
14269 | if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { |
14270 | u32 v; | |
14271 | ||
14272 | v = SHMEM2_RD(bp, | |
14273 | drv_capabilities_flag[BP_FW_MB_IDX(bp)]); | |
14274 | SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], | |
14275 | v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); | |
14276 | } | |
14277 | bnx2x_drain_tx_queues(bp); | |
14278 | bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); | |
14279 | bnx2x_netif_stop(bp, 1); | |
14280 | bnx2x_free_irq(bp); | |
14281 | ||
14282 | /* Report UNLOAD_DONE to MCP */ | |
14283 | bnx2x_send_unload_done(bp, true); | |
14284 | ||
14285 | bp->sp_state = 0; | |
14286 | bp->port.pmf = 0; | |
14287 | ||
14288 | bnx2x_prev_unload(bp); | |
14289 | ||
16a5fd92 | 14290 | /* We should have reseted the engine, so It's fair to |
7fa6f340 YM |
14291 | * assume the FW will no longer write to the bnx2x driver. |
14292 | */ | |
14293 | bnx2x_squeeze_objects(bp); | |
14294 | bnx2x_free_skbs(bp); | |
14295 | for_each_rx_queue(bp, i) | |
14296 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); | |
14297 | bnx2x_free_fp_mem(bp); | |
14298 | bnx2x_free_mem(bp); | |
14299 | ||
14300 | bp->state = BNX2X_STATE_CLOSED; | |
14301 | } | |
14302 | ||
493adb1f WX |
14303 | rtnl_unlock(); |
14304 | ||
33d8e6a5 YM |
14305 | /* If AER, perform cleanup of the PCIe registers */ |
14306 | if (bp->flags & AER_ENABLED) { | |
14307 | if (pci_cleanup_aer_uncorrect_error_status(pdev)) | |
14308 | BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n"); | |
14309 | else | |
14310 | DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n"); | |
14311 | } | |
14312 | ||
493adb1f WX |
14313 | return PCI_ERS_RESULT_RECOVERED; |
14314 | } | |
14315 | ||
14316 | /** | |
14317 | * bnx2x_io_resume - called when traffic can start flowing again | |
14318 | * @pdev: Pointer to PCI device | |
14319 | * | |
14320 | * This callback is called when the error recovery driver tells us that | |
14321 | * its OK to resume normal operation. | |
14322 | */ | |
14323 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
14324 | { | |
14325 | struct net_device *dev = pci_get_drvdata(pdev); | |
14326 | struct bnx2x *bp = netdev_priv(dev); | |
14327 | ||
72fd0718 | 14328 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 14329 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
72fd0718 VZ |
14330 | return; |
14331 | } | |
14332 | ||
493adb1f WX |
14333 | rtnl_lock(); |
14334 | ||
7fa6f340 YM |
14335 | bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & |
14336 | DRV_MSG_SEQ_NUMBER_MASK; | |
14337 | ||
493adb1f | 14338 | if (netif_running(dev)) |
f8ef6e44 | 14339 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
14340 | |
14341 | netif_device_attach(dev); | |
14342 | ||
14343 | rtnl_unlock(); | |
14344 | } | |
14345 | ||
3646f0e5 | 14346 | static const struct pci_error_handlers bnx2x_err_handler = { |
493adb1f | 14347 | .error_detected = bnx2x_io_error_detected, |
356e2385 EG |
14348 | .slot_reset = bnx2x_io_slot_reset, |
14349 | .resume = bnx2x_io_resume, | |
493adb1f WX |
14350 | }; |
14351 | ||
b030ed2f YM |
14352 | static void bnx2x_shutdown(struct pci_dev *pdev) |
14353 | { | |
14354 | struct net_device *dev = pci_get_drvdata(pdev); | |
14355 | struct bnx2x *bp; | |
14356 | ||
14357 | if (!dev) | |
14358 | return; | |
14359 | ||
14360 | bp = netdev_priv(dev); | |
14361 | if (!bp) | |
14362 | return; | |
14363 | ||
14364 | rtnl_lock(); | |
14365 | netif_device_detach(dev); | |
14366 | rtnl_unlock(); | |
14367 | ||
14368 | /* Don't remove the netdevice, as there are scenarios which will cause | |
14369 | * the kernel to hang, e.g., when trying to remove bnx2i while the | |
14370 | * rootfs is mounted from SAN. | |
14371 | */ | |
14372 | __bnx2x_remove(pdev, dev, bp, false); | |
14373 | } | |
14374 | ||
a2fbb9ea | 14375 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
14376 | .name = DRV_MODULE_NAME, |
14377 | .id_table = bnx2x_pci_tbl, | |
14378 | .probe = bnx2x_init_one, | |
0329aba1 | 14379 | .remove = bnx2x_remove_one, |
493adb1f WX |
14380 | .suspend = bnx2x_suspend, |
14381 | .resume = bnx2x_resume, | |
14382 | .err_handler = &bnx2x_err_handler, | |
3c76feff AE |
14383 | #ifdef CONFIG_BNX2X_SRIOV |
14384 | .sriov_configure = bnx2x_sriov_configure, | |
14385 | #endif | |
b030ed2f | 14386 | .shutdown = bnx2x_shutdown, |
a2fbb9ea ET |
14387 | }; |
14388 | ||
14389 | static int __init bnx2x_init(void) | |
14390 | { | |
dd21ca6d SG |
14391 | int ret; |
14392 | ||
7995c64e | 14393 | pr_info("%s", version); |
938cf541 | 14394 | |
1cf167f2 EG |
14395 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
14396 | if (bnx2x_wq == NULL) { | |
7995c64e | 14397 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
14398 | return -ENOMEM; |
14399 | } | |
370d4a26 YM |
14400 | bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov"); |
14401 | if (!bnx2x_iov_wq) { | |
14402 | pr_err("Cannot create iov workqueue\n"); | |
14403 | destroy_workqueue(bnx2x_wq); | |
14404 | return -ENOMEM; | |
14405 | } | |
1cf167f2 | 14406 | |
dd21ca6d SG |
14407 | ret = pci_register_driver(&bnx2x_pci_driver); |
14408 | if (ret) { | |
7995c64e | 14409 | pr_err("Cannot register driver\n"); |
dd21ca6d | 14410 | destroy_workqueue(bnx2x_wq); |
370d4a26 | 14411 | destroy_workqueue(bnx2x_iov_wq); |
dd21ca6d SG |
14412 | } |
14413 | return ret; | |
a2fbb9ea ET |
14414 | } |
14415 | ||
14416 | static void __exit bnx2x_cleanup(void) | |
14417 | { | |
452427b0 | 14418 | struct list_head *pos, *q; |
d76a6111 | 14419 | |
a2fbb9ea | 14420 | pci_unregister_driver(&bnx2x_pci_driver); |
1cf167f2 EG |
14421 | |
14422 | destroy_workqueue(bnx2x_wq); | |
370d4a26 | 14423 | destroy_workqueue(bnx2x_iov_wq); |
452427b0 | 14424 | |
16a5fd92 | 14425 | /* Free globally allocated resources */ |
452427b0 YM |
14426 | list_for_each_safe(pos, q, &bnx2x_prev_list) { |
14427 | struct bnx2x_prev_path_list *tmp = | |
14428 | list_entry(pos, struct bnx2x_prev_path_list, list); | |
14429 | list_del(pos); | |
14430 | kfree(tmp); | |
14431 | } | |
a2fbb9ea ET |
14432 | } |
14433 | ||
3deb8167 YR |
14434 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
14435 | { | |
14436 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
14437 | } | |
14438 | ||
a2fbb9ea ET |
14439 | module_init(bnx2x_init); |
14440 | module_exit(bnx2x_cleanup); | |
14441 | ||
619c5cb6 VZ |
14442 | /** |
14443 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
14444 | * | |
14445 | * @bp: driver handle | |
14446 | * @set: set or clear the CAM entry | |
14447 | * | |
16a5fd92 | 14448 | * This function will wait until the ramrod completion returns. |
619c5cb6 VZ |
14449 | * Return 0 if success, -ENODEV if ramrod doesn't return. |
14450 | */ | |
1191cb83 | 14451 | static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) |
619c5cb6 VZ |
14452 | { |
14453 | unsigned long ramrod_flags = 0; | |
14454 | ||
14455 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
14456 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
14457 | &bp->iscsi_l2_mac_obj, true, | |
14458 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
14459 | } | |
993ac7b5 MC |
14460 | |
14461 | /* count denotes the number of new completions we have seen */ | |
14462 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
14463 | { | |
14464 | struct eth_spe *spe; | |
a052997e | 14465 | int cxt_index, cxt_offset; |
993ac7b5 MC |
14466 | |
14467 | #ifdef BNX2X_STOP_ON_ERROR | |
14468 | if (unlikely(bp->panic)) | |
14469 | return; | |
14470 | #endif | |
14471 | ||
14472 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 14473 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
14474 | bp->cnic_spq_pending -= count; |
14475 | ||
c2bff63f DK |
14476 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
14477 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
14478 | & SPE_HDR_CONN_TYPE) >> | |
14479 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
14480 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
14481 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
14482 | |
14483 | /* Set validation for iSCSI L2 client before sending SETUP | |
14484 | * ramrod | |
14485 | */ | |
14486 | if (type == ETH_CONNECTION_TYPE) { | |
a052997e | 14487 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { |
37ae41a9 | 14488 | cxt_index = BNX2X_ISCSI_ETH_CID(bp) / |
a052997e | 14489 | ILT_PAGE_CIDS; |
37ae41a9 | 14490 | cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - |
a052997e MS |
14491 | (cxt_index * ILT_PAGE_CIDS); |
14492 | bnx2x_set_ctx_validation(bp, | |
14493 | &bp->context[cxt_index]. | |
14494 | vcxt[cxt_offset].eth, | |
37ae41a9 | 14495 | BNX2X_ISCSI_ETH_CID(bp)); |
a052997e | 14496 | } |
c2bff63f DK |
14497 | } |
14498 | ||
619c5cb6 VZ |
14499 | /* |
14500 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
14501 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
14502 | * COMMON ramrods is not more than the EQ and SPQ can |
14503 | * accommodate. | |
c2bff63f | 14504 | */ |
6e30dd4e VZ |
14505 | if (type == ETH_CONNECTION_TYPE) { |
14506 | if (!atomic_read(&bp->cq_spq_left)) | |
14507 | break; | |
14508 | else | |
14509 | atomic_dec(&bp->cq_spq_left); | |
14510 | } else if (type == NONE_CONNECTION_TYPE) { | |
14511 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
14512 | break; |
14513 | else | |
6e30dd4e | 14514 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
14515 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
14516 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
14517 | if (bp->cnic_spq_pending >= |
14518 | bp->cnic_eth_dev.max_kwqe_pending) | |
14519 | break; | |
14520 | else | |
14521 | bp->cnic_spq_pending++; | |
14522 | } else { | |
14523 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
14524 | bnx2x_panic(); | |
993ac7b5 | 14525 | break; |
c2bff63f | 14526 | } |
993ac7b5 MC |
14527 | |
14528 | spe = bnx2x_sp_get_next(bp); | |
14529 | *spe = *bp->cnic_kwq_cons; | |
14530 | ||
51c1a580 | 14531 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
993ac7b5 MC |
14532 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
14533 | ||
14534 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
14535 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
14536 | else | |
14537 | bp->cnic_kwq_cons++; | |
14538 | } | |
14539 | bnx2x_sp_prod_update(bp); | |
14540 | spin_unlock_bh(&bp->spq_lock); | |
14541 | } | |
14542 | ||
14543 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
14544 | struct kwqe_16 *kwqes[], u32 count) | |
14545 | { | |
14546 | struct bnx2x *bp = netdev_priv(dev); | |
14547 | int i; | |
14548 | ||
14549 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 MS |
14550 | if (unlikely(bp->panic)) { |
14551 | BNX2X_ERR("Can't post to SP queue while panic\n"); | |
993ac7b5 | 14552 | return -EIO; |
51c1a580 | 14553 | } |
993ac7b5 MC |
14554 | #endif |
14555 | ||
95c6c616 AE |
14556 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
14557 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
51c1a580 | 14558 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
95c6c616 AE |
14559 | return -EAGAIN; |
14560 | } | |
14561 | ||
993ac7b5 MC |
14562 | spin_lock_bh(&bp->spq_lock); |
14563 | ||
14564 | for (i = 0; i < count; i++) { | |
14565 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
14566 | ||
14567 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
14568 | break; | |
14569 | ||
14570 | *bp->cnic_kwq_prod = *spe; | |
14571 | ||
14572 | bp->cnic_kwq_pending++; | |
14573 | ||
51c1a580 | 14574 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
993ac7b5 | 14575 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
523224a3 DK |
14576 | spe->data.update_data_addr.hi, |
14577 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
14578 | bp->cnic_kwq_pending); |
14579 | ||
14580 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
14581 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
14582 | else | |
14583 | bp->cnic_kwq_prod++; | |
14584 | } | |
14585 | ||
14586 | spin_unlock_bh(&bp->spq_lock); | |
14587 | ||
14588 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
14589 | bnx2x_cnic_sp_post(bp, 0); | |
14590 | ||
14591 | return i; | |
14592 | } | |
14593 | ||
14594 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
14595 | { | |
14596 | struct cnic_ops *c_ops; | |
14597 | int rc = 0; | |
14598 | ||
14599 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
14600 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
14601 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
14602 | if (c_ops) |
14603 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
14604 | mutex_unlock(&bp->cnic_mutex); | |
14605 | ||
14606 | return rc; | |
14607 | } | |
14608 | ||
14609 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
14610 | { | |
14611 | struct cnic_ops *c_ops; | |
14612 | int rc = 0; | |
14613 | ||
14614 | rcu_read_lock(); | |
14615 | c_ops = rcu_dereference(bp->cnic_ops); | |
14616 | if (c_ops) | |
14617 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
14618 | rcu_read_unlock(); | |
14619 | ||
14620 | return rc; | |
14621 | } | |
14622 | ||
14623 | /* | |
14624 | * for commands that have no data | |
14625 | */ | |
9f6c9258 | 14626 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
14627 | { |
14628 | struct cnic_ctl_info ctl = {0}; | |
14629 | ||
14630 | ctl.cmd = cmd; | |
14631 | ||
14632 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
14633 | } | |
14634 | ||
619c5cb6 | 14635 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 14636 | { |
619c5cb6 | 14637 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
14638 | |
14639 | /* first we tell CNIC and only then we count this as a completion */ | |
14640 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
14641 | ctl.data.comp.cid = cid; | |
619c5cb6 | 14642 | ctl.data.comp.error = err; |
993ac7b5 MC |
14643 | |
14644 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 14645 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
14646 | } |
14647 | ||
619c5cb6 VZ |
14648 | /* Called with netif_addr_lock_bh() taken. |
14649 | * Sets an rx_mode config for an iSCSI ETH client. | |
14650 | * Doesn't block. | |
14651 | * Completion should be checked outside. | |
14652 | */ | |
14653 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
14654 | { | |
14655 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
14656 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
14657 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
14658 | ||
14659 | if (start) { | |
14660 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
14661 | * because it's the only way for UIO Queue to accept | |
14662 | * multicasts (in non-promiscuous mode only one Queue per | |
14663 | * function will receive multicast packets (leading in our | |
14664 | * case). | |
14665 | */ | |
14666 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
14667 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
14668 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
14669 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
14670 | ||
14671 | /* Clear STOP_PENDING bit if START is requested */ | |
14672 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
14673 | ||
14674 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
14675 | } else | |
14676 | /* Clear START_PENDING bit if STOP is requested */ | |
14677 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
14678 | ||
14679 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
14680 | set_bit(sched_state, &bp->sp_state); | |
14681 | else { | |
14682 | __set_bit(RAMROD_RX, &ramrod_flags); | |
14683 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
14684 | ramrod_flags); | |
14685 | } | |
14686 | } | |
14687 | ||
993ac7b5 MC |
14688 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
14689 | { | |
14690 | struct bnx2x *bp = netdev_priv(dev); | |
14691 | int rc = 0; | |
14692 | ||
14693 | switch (ctl->cmd) { | |
14694 | case DRV_CTL_CTXTBL_WR_CMD: { | |
14695 | u32 index = ctl->data.io.offset; | |
14696 | dma_addr_t addr = ctl->data.io.dma_addr; | |
14697 | ||
14698 | bnx2x_ilt_wr(bp, index, addr); | |
14699 | break; | |
14700 | } | |
14701 | ||
c2bff63f DK |
14702 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
14703 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
14704 | |
14705 | bnx2x_cnic_sp_post(bp, count); | |
14706 | break; | |
14707 | } | |
14708 | ||
14709 | /* rtnl_lock is held. */ | |
14710 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
14711 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
14712 | unsigned long sp_bits = 0; | |
14713 | ||
14714 | /* Configure the iSCSI classification object */ | |
14715 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
14716 | cp->iscsi_l2_client_id, | |
14717 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
14718 | bnx2x_sp(bp, mac_rdata), | |
14719 | bnx2x_sp_mapping(bp, mac_rdata), | |
14720 | BNX2X_FILTER_MAC_PENDING, | |
14721 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
14722 | &bp->macs_pool); | |
ec6ba945 | 14723 | |
523224a3 | 14724 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
14725 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
14726 | if (rc) | |
14727 | break; | |
523224a3 DK |
14728 | |
14729 | mmiowb(); | |
14730 | barrier(); | |
14731 | ||
619c5cb6 VZ |
14732 | /* Start accepting on iSCSI L2 ring */ |
14733 | ||
14734 | netif_addr_lock_bh(dev); | |
14735 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
14736 | netif_addr_unlock_bh(dev); | |
14737 | ||
14738 | /* bits to wait on */ | |
14739 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
14740 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
14741 | ||
14742 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
14743 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 14744 | |
993ac7b5 MC |
14745 | break; |
14746 | } | |
14747 | ||
14748 | /* rtnl_lock is held. */ | |
14749 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 14750 | unsigned long sp_bits = 0; |
993ac7b5 | 14751 | |
523224a3 | 14752 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
14753 | netif_addr_lock_bh(dev); |
14754 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
14755 | netif_addr_unlock_bh(dev); | |
14756 | ||
14757 | /* bits to wait on */ | |
14758 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
14759 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
14760 | ||
14761 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
14762 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
14763 | |
14764 | mmiowb(); | |
14765 | barrier(); | |
14766 | ||
14767 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
14768 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
14769 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
14770 | break; |
14771 | } | |
c2bff63f DK |
14772 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
14773 | int count = ctl->data.credit.credit_count; | |
14774 | ||
4e857c58 | 14775 | smp_mb__before_atomic(); |
6e30dd4e | 14776 | atomic_add(count, &bp->cq_spq_left); |
4e857c58 | 14777 | smp_mb__after_atomic(); |
c2bff63f DK |
14778 | break; |
14779 | } | |
1d187b34 | 14780 | case DRV_CTL_ULP_REGISTER_CMD: { |
2e499d3c | 14781 | int ulp_type = ctl->data.register_data.ulp_type; |
1d187b34 BW |
14782 | |
14783 | if (CHIP_IS_E3(bp)) { | |
14784 | int idx = BP_FW_MB_IDX(bp); | |
2e499d3c BW |
14785 | u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); |
14786 | int path = BP_PATH(bp); | |
14787 | int port = BP_PORT(bp); | |
14788 | int i; | |
14789 | u32 scratch_offset; | |
14790 | u32 *host_addr; | |
1d187b34 | 14791 | |
2e499d3c | 14792 | /* first write capability to shmem2 */ |
1d187b34 BW |
14793 | if (ulp_type == CNIC_ULP_ISCSI) |
14794 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
14795 | else if (ulp_type == CNIC_ULP_FCOE) | |
14796 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
14797 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
2e499d3c BW |
14798 | |
14799 | if ((ulp_type != CNIC_ULP_FCOE) || | |
14800 | (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || | |
14801 | (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) | |
14802 | break; | |
14803 | ||
14804 | /* if reached here - should write fcoe capabilities */ | |
14805 | scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); | |
14806 | if (!scratch_offset) | |
14807 | break; | |
14808 | scratch_offset += offsetof(struct glob_ncsi_oem_data, | |
14809 | fcoe_features[path][port]); | |
14810 | host_addr = (u32 *) &(ctl->data.register_data. | |
14811 | fcoe_features); | |
14812 | for (i = 0; i < sizeof(struct fcoe_capabilities); | |
14813 | i += 4) | |
14814 | REG_WR(bp, scratch_offset + i, | |
14815 | *(host_addr + i/4)); | |
1d187b34 | 14816 | } |
42f8277f | 14817 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); |
1d187b34 BW |
14818 | break; |
14819 | } | |
2e499d3c | 14820 | |
1d187b34 BW |
14821 | case DRV_CTL_ULP_UNREGISTER_CMD: { |
14822 | int ulp_type = ctl->data.ulp_type; | |
14823 | ||
14824 | if (CHIP_IS_E3(bp)) { | |
14825 | int idx = BP_FW_MB_IDX(bp); | |
14826 | u32 cap; | |
14827 | ||
14828 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
14829 | if (ulp_type == CNIC_ULP_ISCSI) | |
14830 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
14831 | else if (ulp_type == CNIC_ULP_FCOE) | |
14832 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
14833 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
14834 | } | |
42f8277f | 14835 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); |
1d187b34 BW |
14836 | break; |
14837 | } | |
993ac7b5 MC |
14838 | |
14839 | default: | |
14840 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
14841 | rc = -EINVAL; | |
14842 | } | |
14843 | ||
97ac4ef7 YM |
14844 | /* For storage-only interfaces, change driver state */ |
14845 | if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) { | |
14846 | switch (ctl->drv_state) { | |
14847 | case DRV_NOP: | |
14848 | break; | |
14849 | case DRV_ACTIVE: | |
14850 | bnx2x_set_os_driver_state(bp, | |
14851 | OS_DRIVER_STATE_ACTIVE); | |
14852 | break; | |
14853 | case DRV_INACTIVE: | |
14854 | bnx2x_set_os_driver_state(bp, | |
14855 | OS_DRIVER_STATE_DISABLED); | |
14856 | break; | |
14857 | case DRV_UNLOADED: | |
14858 | bnx2x_set_os_driver_state(bp, | |
14859 | OS_DRIVER_STATE_NOT_LOADED); | |
14860 | break; | |
14861 | default: | |
14862 | BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state); | |
14863 | } | |
14864 | } | |
14865 | ||
14866 | return rc; | |
14867 | } | |
14868 | ||
14869 | static int bnx2x_get_fc_npiv(struct net_device *dev, | |
14870 | struct cnic_fc_npiv_tbl *cnic_tbl) | |
14871 | { | |
14872 | struct bnx2x *bp = netdev_priv(dev); | |
14873 | struct bdn_fc_npiv_tbl *tbl = NULL; | |
14874 | u32 offset, entries; | |
14875 | int rc = -EINVAL; | |
14876 | int i; | |
14877 | ||
14878 | if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0])) | |
14879 | goto out; | |
14880 | ||
14881 | DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n"); | |
14882 | ||
14883 | tbl = kmalloc(sizeof(*tbl), GFP_KERNEL); | |
14884 | if (!tbl) { | |
14885 | BNX2X_ERR("Failed to allocate fc_npiv table\n"); | |
14886 | goto out; | |
14887 | } | |
14888 | ||
14889 | offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]); | |
14890 | DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset); | |
14891 | ||
14892 | /* Read the table contents from nvram */ | |
14893 | if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) { | |
14894 | BNX2X_ERR("Failed to read FC-NPIV table\n"); | |
14895 | goto out; | |
14896 | } | |
14897 | ||
14898 | /* Since bnx2x_nvram_read() returns data in be32, we need to convert | |
14899 | * the number of entries back to cpu endianness. | |
14900 | */ | |
14901 | entries = tbl->fc_npiv_cfg.num_of_npiv; | |
14902 | entries = (__force u32)be32_to_cpu((__force __be32)entries); | |
14903 | tbl->fc_npiv_cfg.num_of_npiv = entries; | |
14904 | ||
14905 | if (!tbl->fc_npiv_cfg.num_of_npiv) { | |
14906 | DP(BNX2X_MSG_MCP, | |
14907 | "No FC-NPIV table [valid, simply not present]\n"); | |
14908 | goto out; | |
14909 | } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) { | |
14910 | BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n", | |
14911 | tbl->fc_npiv_cfg.num_of_npiv); | |
14912 | goto out; | |
14913 | } else { | |
14914 | DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n", | |
14915 | tbl->fc_npiv_cfg.num_of_npiv); | |
14916 | } | |
14917 | ||
14918 | /* Copy the data into cnic-provided struct */ | |
14919 | cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv; | |
14920 | for (i = 0; i < cnic_tbl->count; i++) { | |
14921 | memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8); | |
14922 | memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8); | |
14923 | } | |
14924 | ||
14925 | rc = 0; | |
14926 | out: | |
14927 | kfree(tbl); | |
993ac7b5 MC |
14928 | return rc; |
14929 | } | |
14930 | ||
9f6c9258 | 14931 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
14932 | { |
14933 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
14934 | ||
14935 | if (bp->flags & USING_MSIX_FLAG) { | |
14936 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
14937 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
14938 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
14939 | } else { | |
14940 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
14941 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
14942 | } | |
619c5cb6 | 14943 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
14944 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
14945 | else | |
14946 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
14947 | ||
619c5cb6 VZ |
14948 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
14949 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
14950 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
14951 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 14952 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
14953 | |
14954 | cp->num_irq = 2; | |
14955 | } | |
14956 | ||
37ae41a9 MS |
14957 | void bnx2x_setup_cnic_info(struct bnx2x *bp) |
14958 | { | |
14959 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
14960 | ||
37ae41a9 MS |
14961 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
14962 | bnx2x_cid_ilt_lines(bp); | |
14963 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; | |
14964 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); | |
14965 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); | |
14966 | ||
f78afb35 MC |
14967 | DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n", |
14968 | BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid, | |
14969 | cp->iscsi_l2_cid); | |
14970 | ||
37ae41a9 MS |
14971 | if (NO_ISCSI_OOO(bp)) |
14972 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
14973 | } | |
14974 | ||
993ac7b5 MC |
14975 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, |
14976 | void *data) | |
14977 | { | |
14978 | struct bnx2x *bp = netdev_priv(dev); | |
14979 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
55c11941 MS |
14980 | int rc; |
14981 | ||
14982 | DP(NETIF_MSG_IFUP, "Register_cnic called\n"); | |
993ac7b5 | 14983 | |
51c1a580 MS |
14984 | if (ops == NULL) { |
14985 | BNX2X_ERR("NULL ops received\n"); | |
993ac7b5 | 14986 | return -EINVAL; |
51c1a580 | 14987 | } |
993ac7b5 | 14988 | |
55c11941 MS |
14989 | if (!CNIC_SUPPORT(bp)) { |
14990 | BNX2X_ERR("Can't register CNIC when not supported\n"); | |
14991 | return -EOPNOTSUPP; | |
14992 | } | |
14993 | ||
14994 | if (!CNIC_LOADED(bp)) { | |
14995 | rc = bnx2x_load_cnic(bp); | |
14996 | if (rc) { | |
14997 | BNX2X_ERR("CNIC-related load failed\n"); | |
14998 | return rc; | |
14999 | } | |
55c11941 MS |
15000 | } |
15001 | ||
15002 | bp->cnic_enabled = true; | |
15003 | ||
993ac7b5 MC |
15004 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
15005 | if (!bp->cnic_kwq) | |
15006 | return -ENOMEM; | |
15007 | ||
15008 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
15009 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
15010 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
15011 | ||
15012 | bp->cnic_spq_pending = 0; | |
15013 | bp->cnic_kwq_pending = 0; | |
15014 | ||
15015 | bp->cnic_data = data; | |
15016 | ||
15017 | cp->num_irq = 0; | |
619c5cb6 | 15018 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 15019 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 15020 | |
993ac7b5 | 15021 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 15022 | |
993ac7b5 MC |
15023 | rcu_assign_pointer(bp->cnic_ops, ops); |
15024 | ||
42f8277f YM |
15025 | /* Schedule driver to read CNIC driver versions */ |
15026 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); | |
15027 | ||
993ac7b5 MC |
15028 | return 0; |
15029 | } | |
15030 | ||
15031 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
15032 | { | |
15033 | struct bnx2x *bp = netdev_priv(dev); | |
15034 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
15035 | ||
15036 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 | 15037 | cp->drv_state = 0; |
2cfa5a04 | 15038 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
993ac7b5 MC |
15039 | mutex_unlock(&bp->cnic_mutex); |
15040 | synchronize_rcu(); | |
fea75645 | 15041 | bp->cnic_enabled = false; |
993ac7b5 MC |
15042 | kfree(bp->cnic_kwq); |
15043 | bp->cnic_kwq = NULL; | |
15044 | ||
15045 | return 0; | |
15046 | } | |
15047 | ||
a8f47eb7 | 15048 | static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) |
993ac7b5 MC |
15049 | { |
15050 | struct bnx2x *bp = netdev_priv(dev); | |
15051 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
15052 | ||
2ba45142 VZ |
15053 | /* If both iSCSI and FCoE are disabled - return NULL in |
15054 | * order to indicate CNIC that it should not try to work | |
15055 | * with this device. | |
15056 | */ | |
15057 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
15058 | return NULL; | |
15059 | ||
993ac7b5 MC |
15060 | cp->drv_owner = THIS_MODULE; |
15061 | cp->chip_id = CHIP_ID(bp); | |
15062 | cp->pdev = bp->pdev; | |
15063 | cp->io_base = bp->regview; | |
15064 | cp->io_base2 = bp->doorbells; | |
15065 | cp->max_kwqe_pending = 8; | |
523224a3 | 15066 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
15067 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
15068 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 15069 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 15070 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
15071 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
15072 | cp->drv_ctl = bnx2x_drv_ctl; | |
97ac4ef7 | 15073 | cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv; |
993ac7b5 MC |
15074 | cp->drv_register_cnic = bnx2x_register_cnic; |
15075 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
37ae41a9 | 15076 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); |
619c5cb6 VZ |
15077 | cp->iscsi_l2_client_id = |
15078 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
37ae41a9 | 15079 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); |
c2bff63f | 15080 | |
2ba45142 VZ |
15081 | if (NO_ISCSI_OOO(bp)) |
15082 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
15083 | ||
15084 | if (NO_ISCSI(bp)) | |
15085 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
15086 | ||
15087 | if (NO_FCOE(bp)) | |
15088 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
15089 | ||
51c1a580 MS |
15090 | BNX2X_DEV_INFO( |
15091 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", | |
c2bff63f DK |
15092 | cp->ctx_blk_size, |
15093 | cp->ctx_tbl_offset, | |
15094 | cp->ctx_tbl_len, | |
15095 | cp->starting_cid); | |
993ac7b5 MC |
15096 | return cp; |
15097 | } | |
993ac7b5 | 15098 | |
a8f47eb7 | 15099 | static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) |
9b176b6b | 15100 | { |
6411280a AE |
15101 | struct bnx2x *bp = fp->bp; |
15102 | u32 offset = BAR_USTRORM_INTMEM; | |
abc5a021 | 15103 | |
6411280a AE |
15104 | if (IS_VF(bp)) |
15105 | return bnx2x_vf_ustorm_prods_offset(bp, fp); | |
15106 | else if (!CHIP_IS_E1x(bp)) | |
15107 | offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); | |
15108 | else | |
15109 | offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); | |
8d9ac297 | 15110 | |
6411280a | 15111 | return offset; |
8d9ac297 | 15112 | } |
381ac16b | 15113 | |
6411280a AE |
15114 | /* called only on E1H or E2. |
15115 | * When pretending to be PF, the pretend value is the function number 0...7 | |
15116 | * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID | |
15117 | * combination | |
15118 | */ | |
15119 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) | |
381ac16b | 15120 | { |
6411280a | 15121 | u32 pretend_reg; |
381ac16b | 15122 | |
23826850 | 15123 | if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) |
6411280a | 15124 | return -1; |
381ac16b | 15125 | |
6411280a AE |
15126 | /* get my own pretend register */ |
15127 | pretend_reg = bnx2x_get_pretend_reg(bp); | |
15128 | REG_WR(bp, pretend_reg, pretend_func_val); | |
15129 | REG_RD(bp, pretend_reg); | |
381ac16b AE |
15130 | return 0; |
15131 | } | |
eeed018c MK |
15132 | |
15133 | static void bnx2x_ptp_task(struct work_struct *work) | |
15134 | { | |
15135 | struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task); | |
15136 | int port = BP_PORT(bp); | |
15137 | u32 val_seq; | |
15138 | u64 timestamp, ns; | |
15139 | struct skb_shared_hwtstamps shhwtstamps; | |
15140 | ||
15141 | /* Read Tx timestamp registers */ | |
15142 | val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : | |
15143 | NIG_REG_P0_TLLH_PTP_BUF_SEQID); | |
15144 | if (val_seq & 0x10000) { | |
15145 | /* There is a valid timestamp value */ | |
15146 | timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB : | |
15147 | NIG_REG_P0_TLLH_PTP_BUF_TS_MSB); | |
15148 | timestamp <<= 32; | |
15149 | timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB : | |
15150 | NIG_REG_P0_TLLH_PTP_BUF_TS_LSB); | |
15151 | /* Reset timestamp register to allow new timestamp */ | |
15152 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : | |
15153 | NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); | |
15154 | ns = timecounter_cyc2time(&bp->timecounter, timestamp); | |
15155 | ||
15156 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
15157 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
15158 | skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps); | |
15159 | dev_kfree_skb_any(bp->ptp_tx_skb); | |
15160 | bp->ptp_tx_skb = NULL; | |
15161 | ||
15162 | DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n", | |
15163 | timestamp, ns); | |
15164 | } else { | |
15165 | DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n"); | |
15166 | /* Reschedule to keep checking for a valid timestamp value */ | |
15167 | schedule_work(&bp->ptp_task); | |
15168 | } | |
15169 | } | |
15170 | ||
15171 | void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb) | |
15172 | { | |
15173 | int port = BP_PORT(bp); | |
15174 | u64 timestamp, ns; | |
15175 | ||
15176 | timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB : | |
15177 | NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB); | |
15178 | timestamp <<= 32; | |
15179 | timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB : | |
15180 | NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB); | |
15181 | ||
15182 | /* Reset timestamp register to allow new timestamp */ | |
15183 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : | |
15184 | NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); | |
15185 | ||
15186 | ns = timecounter_cyc2time(&bp->timecounter, timestamp); | |
15187 | ||
15188 | skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); | |
15189 | ||
15190 | DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n", | |
15191 | timestamp, ns); | |
15192 | } | |
15193 | ||
15194 | /* Read the PHC */ | |
15195 | static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc) | |
15196 | { | |
15197 | struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter); | |
15198 | int port = BP_PORT(bp); | |
15199 | u32 wb_data[2]; | |
15200 | u64 phc_cycles; | |
15201 | ||
15202 | REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 : | |
15203 | NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2); | |
15204 | phc_cycles = wb_data[1]; | |
15205 | phc_cycles = (phc_cycles << 32) + wb_data[0]; | |
15206 | ||
15207 | DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles); | |
15208 | ||
15209 | return phc_cycles; | |
15210 | } | |
15211 | ||
15212 | static void bnx2x_init_cyclecounter(struct bnx2x *bp) | |
15213 | { | |
15214 | memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter)); | |
15215 | bp->cyclecounter.read = bnx2x_cyclecounter_read; | |
f28ba401 | 15216 | bp->cyclecounter.mask = CYCLECOUNTER_MASK(64); |
eeed018c MK |
15217 | bp->cyclecounter.shift = 1; |
15218 | bp->cyclecounter.mult = 1; | |
15219 | } | |
15220 | ||
15221 | static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp) | |
15222 | { | |
15223 | struct bnx2x_func_state_params func_params = {NULL}; | |
15224 | struct bnx2x_func_set_timesync_params *set_timesync_params = | |
15225 | &func_params.params.set_timesync; | |
15226 | ||
15227 | /* Prepare parameters for function state transitions */ | |
15228 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
15229 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
15230 | ||
15231 | func_params.f_obj = &bp->func_obj; | |
15232 | func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; | |
15233 | ||
15234 | /* Function parameters */ | |
15235 | set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET; | |
15236 | set_timesync_params->offset_cmd = TS_OFFSET_KEEP; | |
15237 | ||
15238 | return bnx2x_func_state_change(bp, &func_params); | |
15239 | } | |
15240 | ||
1444c301 | 15241 | static int bnx2x_enable_ptp_packets(struct bnx2x *bp) |
eeed018c MK |
15242 | { |
15243 | struct bnx2x_queue_state_params q_params; | |
15244 | int rc, i; | |
15245 | ||
15246 | /* send queue update ramrod to enable PTP packets */ | |
15247 | memset(&q_params, 0, sizeof(q_params)); | |
15248 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
15249 | q_params.cmd = BNX2X_Q_CMD_UPDATE; | |
15250 | __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, | |
15251 | &q_params.params.update.update_flags); | |
15252 | __set_bit(BNX2X_Q_UPDATE_PTP_PKTS, | |
15253 | &q_params.params.update.update_flags); | |
15254 | ||
15255 | /* send the ramrod on all the queues of the PF */ | |
15256 | for_each_eth_queue(bp, i) { | |
15257 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
15258 | ||
15259 | /* Set the appropriate Queue object */ | |
15260 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; | |
15261 | ||
15262 | /* Update the Queue state */ | |
15263 | rc = bnx2x_queue_state_change(bp, &q_params); | |
15264 | if (rc) { | |
15265 | BNX2X_ERR("Failed to enable PTP packets\n"); | |
15266 | return rc; | |
15267 | } | |
15268 | } | |
15269 | ||
15270 | return 0; | |
15271 | } | |
15272 | ||
15273 | int bnx2x_configure_ptp_filters(struct bnx2x *bp) | |
15274 | { | |
15275 | int port = BP_PORT(bp); | |
15276 | int rc; | |
15277 | ||
15278 | if (!bp->hwtstamp_ioctl_called) | |
15279 | return 0; | |
15280 | ||
15281 | switch (bp->tx_type) { | |
15282 | case HWTSTAMP_TX_ON: | |
15283 | bp->flags |= TX_TIMESTAMPING_EN; | |
15284 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : | |
15285 | NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA); | |
15286 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : | |
15287 | NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE); | |
15288 | break; | |
15289 | case HWTSTAMP_TX_ONESTEP_SYNC: | |
15290 | BNX2X_ERR("One-step timestamping is not supported\n"); | |
15291 | return -ERANGE; | |
15292 | } | |
15293 | ||
15294 | switch (bp->rx_filter) { | |
15295 | case HWTSTAMP_FILTER_NONE: | |
15296 | break; | |
15297 | case HWTSTAMP_FILTER_ALL: | |
15298 | case HWTSTAMP_FILTER_SOME: | |
15299 | bp->rx_filter = HWTSTAMP_FILTER_NONE; | |
15300 | break; | |
15301 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
15302 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
15303 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
15304 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
15305 | /* Initialize PTP detection for UDP/IPv4 events */ | |
15306 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
15307 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE); | |
15308 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
15309 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE); | |
15310 | break; | |
15311 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
15312 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
15313 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
15314 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; | |
15315 | /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */ | |
15316 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
15317 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA); | |
15318 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
15319 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE); | |
15320 | break; | |
15321 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
15322 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
15323 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
15324 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; | |
15325 | /* Initialize PTP detection L2 events */ | |
15326 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
15327 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF); | |
15328 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
15329 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF); | |
15330 | ||
15331 | break; | |
15332 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
15333 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
15334 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
15335 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
15336 | /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */ | |
15337 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
15338 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA); | |
15339 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
15340 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE); | |
15341 | break; | |
15342 | } | |
15343 | ||
15344 | /* Indicate to FW that this PF expects recorded PTP packets */ | |
15345 | rc = bnx2x_enable_ptp_packets(bp); | |
15346 | if (rc) | |
15347 | return rc; | |
15348 | ||
15349 | /* Enable sending PTP packets to host */ | |
15350 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : | |
15351 | NIG_REG_P0_LLH_PTP_TO_HOST, 0x1); | |
15352 | ||
15353 | return 0; | |
15354 | } | |
15355 | ||
15356 | static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr) | |
15357 | { | |
15358 | struct hwtstamp_config config; | |
15359 | int rc; | |
15360 | ||
15361 | DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n"); | |
15362 | ||
15363 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
15364 | return -EFAULT; | |
15365 | ||
15366 | DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n", | |
15367 | config.tx_type, config.rx_filter); | |
15368 | ||
15369 | if (config.flags) { | |
15370 | BNX2X_ERR("config.flags is reserved for future use\n"); | |
15371 | return -EINVAL; | |
15372 | } | |
15373 | ||
15374 | bp->hwtstamp_ioctl_called = 1; | |
15375 | bp->tx_type = config.tx_type; | |
15376 | bp->rx_filter = config.rx_filter; | |
15377 | ||
15378 | rc = bnx2x_configure_ptp_filters(bp); | |
15379 | if (rc) | |
15380 | return rc; | |
15381 | ||
15382 | config.rx_filter = bp->rx_filter; | |
15383 | ||
15384 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
15385 | -EFAULT : 0; | |
15386 | } | |
15387 | ||
bf27c353 | 15388 | /* Configures HW for PTP */ |
eeed018c MK |
15389 | static int bnx2x_configure_ptp(struct bnx2x *bp) |
15390 | { | |
15391 | int rc, port = BP_PORT(bp); | |
15392 | u32 wb_data[2]; | |
15393 | ||
15394 | /* Reset PTP event detection rules - will be configured in the IOCTL */ | |
15395 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
15396 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); | |
15397 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
15398 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); | |
15399 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : | |
15400 | NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); | |
15401 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : | |
15402 | NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); | |
15403 | ||
15404 | /* Disable PTP packets to host - will be configured in the IOCTL*/ | |
15405 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : | |
15406 | NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); | |
15407 | ||
15408 | /* Enable the PTP feature */ | |
15409 | REG_WR(bp, port ? NIG_REG_P1_PTP_EN : | |
15410 | NIG_REG_P0_PTP_EN, 0x3F); | |
15411 | ||
15412 | /* Enable the free-running counter */ | |
15413 | wb_data[0] = 0; | |
15414 | wb_data[1] = 0; | |
15415 | REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2); | |
15416 | ||
15417 | /* Reset drift register (offset register is not reset) */ | |
15418 | rc = bnx2x_send_reset_timesync_ramrod(bp); | |
15419 | if (rc) { | |
15420 | BNX2X_ERR("Failed to reset PHC drift register\n"); | |
15421 | return -EFAULT; | |
15422 | } | |
15423 | ||
15424 | /* Reset possibly old timestamps */ | |
15425 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : | |
15426 | NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); | |
15427 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : | |
15428 | NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); | |
15429 | ||
15430 | return 0; | |
15431 | } | |
15432 | ||
15433 | /* Called during load, to initialize PTP-related stuff */ | |
15434 | void bnx2x_init_ptp(struct bnx2x *bp) | |
15435 | { | |
15436 | int rc; | |
15437 | ||
15438 | /* Configure PTP in HW */ | |
15439 | rc = bnx2x_configure_ptp(bp); | |
15440 | if (rc) { | |
15441 | BNX2X_ERR("Stopping PTP initialization\n"); | |
15442 | return; | |
15443 | } | |
15444 | ||
15445 | /* Init work queue for Tx timestamping */ | |
15446 | INIT_WORK(&bp->ptp_task, bnx2x_ptp_task); | |
15447 | ||
15448 | /* Init cyclecounter and timecounter. This is done only in the first | |
15449 | * load. If done in every load, PTP application will fail when doing | |
15450 | * unload / load (e.g. MTU change) while it is running. | |
15451 | */ | |
15452 | if (!bp->timecounter_init_done) { | |
15453 | bnx2x_init_cyclecounter(bp); | |
15454 | timecounter_init(&bp->timecounter, &bp->cyclecounter, | |
15455 | ktime_to_ns(ktime_get_real())); | |
15456 | bp->timecounter_init_done = 1; | |
15457 | } | |
15458 | ||
15459 | DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n"); | |
15460 | } |