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Commit | Line | Data |
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34f80b04 | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
a2fbb9ea | 2 | * |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
08f6dd89 | 9 | * Maintained by: Ariel Elior <ariel.elior@qlogic.com> |
24e3fcef | 10 | * Written by: Eliezer Tamir |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 14 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
15 | * |
16 | */ | |
17 | ||
f1deab50 JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
a2fbb9ea ET |
20 | #include <linux/module.h> |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/device.h> /* for dev_info() */ | |
24 | #include <linux/timer.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/slab.h> | |
a2fbb9ea ET |
28 | #include <linux/interrupt.h> |
29 | #include <linux/pci.h> | |
33d8e6a5 | 30 | #include <linux/aer.h> |
a2fbb9ea ET |
31 | #include <linux/init.h> |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/bitops.h> | |
37 | #include <linux/irq.h> | |
38 | #include <linux/delay.h> | |
39 | #include <asm/byteorder.h> | |
40 | #include <linux/time.h> | |
41 | #include <linux/ethtool.h> | |
42 | #include <linux/mii.h> | |
0c6671b0 | 43 | #include <linux/if_vlan.h> |
c9931896 | 44 | #include <linux/crash_dump.h> |
a2fbb9ea | 45 | #include <net/ip.h> |
619c5cb6 | 46 | #include <net/ipv6.h> |
a2fbb9ea | 47 | #include <net/tcp.h> |
51de7bb9 | 48 | #include <net/vxlan.h> |
a2fbb9ea | 49 | #include <net/checksum.h> |
34f80b04 | 50 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
51 | #include <linux/workqueue.h> |
52 | #include <linux/crc32.h> | |
34f80b04 | 53 | #include <linux/crc32c.h> |
a2fbb9ea ET |
54 | #include <linux/prefetch.h> |
55 | #include <linux/zlib.h> | |
a2fbb9ea | 56 | #include <linux/io.h> |
452427b0 | 57 | #include <linux/semaphore.h> |
45229b42 | 58 | #include <linux/stringify.h> |
7ab24bfd | 59 | #include <linux/vmalloc.h> |
a2fbb9ea | 60 | |
a2fbb9ea ET |
61 | #include "bnx2x.h" |
62 | #include "bnx2x_init.h" | |
94a78b79 | 63 | #include "bnx2x_init_ops.h" |
9f6c9258 | 64 | #include "bnx2x_cmn.h" |
1ab4434c | 65 | #include "bnx2x_vfpf.h" |
e4901dde | 66 | #include "bnx2x_dcb.h" |
042181f5 | 67 | #include "bnx2x_sp.h" |
94a78b79 VZ |
68 | #include <linux/firmware.h> |
69 | #include "bnx2x_fw_file_hdr.h" | |
70 | /* FW files */ | |
45229b42 BH |
71 | #define FW_FILE_VERSION \ |
72 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
73 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
74 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
75 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
76 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
77 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 78 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 79 | |
34f80b04 EG |
80 | /* Time in jiffies before concluding the transmitter is hung */ |
81 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 82 | |
0329aba1 | 83 | static char version[] = |
619c5cb6 | 84 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
85 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
86 | ||
24e3fcef | 87 | MODULE_AUTHOR("Eliezer Tamir"); |
f2e0899f | 88 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
619c5cb6 VZ |
89 | "BCM57710/57711/57711E/" |
90 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
91 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
92 | MODULE_LICENSE("GPL"); |
93 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
94 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
95 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 96 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 97 | |
a8f47eb7 | 98 | int bnx2x_num_queues; |
1c8bb760 | 99 | module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO); |
96305234 DK |
100 | MODULE_PARM_DESC(num_queues, |
101 | " Set number of queues (default is as a number of CPUs)"); | |
555f6c78 | 102 | |
19680c48 | 103 | static int disable_tpa; |
1c8bb760 | 104 | module_param(disable_tpa, int, S_IRUGO); |
9898f86d | 105 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 106 | |
a8f47eb7 | 107 | static int int_mode; |
1c8bb760 | 108 | module_param(int_mode, int, S_IRUGO); |
619c5cb6 | 109 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 110 | "(1 INT#x; 2 MSI)"); |
8badd27a | 111 | |
a18f5128 | 112 | static int dropless_fc; |
1c8bb760 | 113 | module_param(dropless_fc, int, S_IRUGO); |
a18f5128 EG |
114 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); |
115 | ||
8d5726c4 | 116 | static int mrrs = -1; |
1c8bb760 | 117 | module_param(mrrs, int, S_IRUGO); |
8d5726c4 EG |
118 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); |
119 | ||
9898f86d | 120 | static int debug; |
1c8bb760 | 121 | module_param(debug, int, S_IRUGO); |
9898f86d EG |
122 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
123 | ||
370d4a26 YM |
124 | static struct workqueue_struct *bnx2x_wq; |
125 | struct workqueue_struct *bnx2x_iov_wq; | |
ec6ba945 | 126 | |
1ef1d45a BW |
127 | struct bnx2x_mac_vals { |
128 | u32 xmac_addr; | |
129 | u32 xmac_val; | |
130 | u32 emac_addr; | |
131 | u32 emac_val; | |
3d6b7253 YM |
132 | u32 umac_addr[2]; |
133 | u32 umac_val[2]; | |
1ef1d45a BW |
134 | u32 bmac_addr; |
135 | u32 bmac_val[2]; | |
136 | }; | |
137 | ||
a2fbb9ea ET |
138 | enum bnx2x_board_type { |
139 | BCM57710 = 0, | |
619c5cb6 VZ |
140 | BCM57711, |
141 | BCM57711E, | |
142 | BCM57712, | |
143 | BCM57712_MF, | |
1ab4434c | 144 | BCM57712_VF, |
619c5cb6 VZ |
145 | BCM57800, |
146 | BCM57800_MF, | |
1ab4434c | 147 | BCM57800_VF, |
619c5cb6 VZ |
148 | BCM57810, |
149 | BCM57810_MF, | |
1ab4434c | 150 | BCM57810_VF, |
c3def943 YM |
151 | BCM57840_4_10, |
152 | BCM57840_2_20, | |
7e8e02df | 153 | BCM57840_MF, |
1ab4434c | 154 | BCM57840_VF, |
7e8e02df | 155 | BCM57811, |
1ab4434c AE |
156 | BCM57811_MF, |
157 | BCM57840_O, | |
158 | BCM57840_MFO, | |
159 | BCM57811_VF | |
a2fbb9ea ET |
160 | }; |
161 | ||
34f80b04 | 162 | /* indexed by board_type, above */ |
53a10565 | 163 | static struct { |
a2fbb9ea | 164 | char *name; |
0329aba1 | 165 | } board_info[] = { |
1ab4434c AE |
166 | [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
167 | [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, | |
168 | [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, | |
169 | [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, | |
170 | [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, | |
171 | [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" }, | |
172 | [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, | |
173 | [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, | |
174 | [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" }, | |
175 | [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, | |
176 | [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, | |
177 | [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" }, | |
178 | [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" }, | |
179 | [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" }, | |
180 | [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
181 | [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }, | |
182 | [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" }, | |
183 | [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" }, | |
184 | [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, | |
185 | [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
186 | [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" } | |
a2fbb9ea ET |
187 | }; |
188 | ||
619c5cb6 VZ |
189 | #ifndef PCI_DEVICE_ID_NX2_57710 |
190 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
191 | #endif | |
192 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
193 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
194 | #endif | |
195 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
196 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
197 | #endif | |
198 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
199 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
200 | #endif | |
201 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
202 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
203 | #endif | |
8395be5e AE |
204 | #ifndef PCI_DEVICE_ID_NX2_57712_VF |
205 | #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF | |
206 | #endif | |
619c5cb6 VZ |
207 | #ifndef PCI_DEVICE_ID_NX2_57800 |
208 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
209 | #endif | |
210 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
211 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
212 | #endif | |
8395be5e AE |
213 | #ifndef PCI_DEVICE_ID_NX2_57800_VF |
214 | #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF | |
215 | #endif | |
619c5cb6 VZ |
216 | #ifndef PCI_DEVICE_ID_NX2_57810 |
217 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
218 | #endif | |
219 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
220 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
221 | #endif | |
c3def943 YM |
222 | #ifndef PCI_DEVICE_ID_NX2_57840_O |
223 | #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE | |
224 | #endif | |
8395be5e AE |
225 | #ifndef PCI_DEVICE_ID_NX2_57810_VF |
226 | #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF | |
227 | #endif | |
c3def943 YM |
228 | #ifndef PCI_DEVICE_ID_NX2_57840_4_10 |
229 | #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 | |
230 | #endif | |
231 | #ifndef PCI_DEVICE_ID_NX2_57840_2_20 | |
232 | #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 | |
233 | #endif | |
234 | #ifndef PCI_DEVICE_ID_NX2_57840_MFO | |
235 | #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE | |
619c5cb6 VZ |
236 | #endif |
237 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
238 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
239 | #endif | |
8395be5e AE |
240 | #ifndef PCI_DEVICE_ID_NX2_57840_VF |
241 | #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF | |
242 | #endif | |
7e8e02df BW |
243 | #ifndef PCI_DEVICE_ID_NX2_57811 |
244 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 | |
245 | #endif | |
246 | #ifndef PCI_DEVICE_ID_NX2_57811_MF | |
247 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF | |
248 | #endif | |
8395be5e AE |
249 | #ifndef PCI_DEVICE_ID_NX2_57811_VF |
250 | #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF | |
251 | #endif | |
252 | ||
9baa3c34 | 253 | static const struct pci_device_id bnx2x_pci_tbl[] = { |
e4ed7113 EG |
254 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
255 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
256 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 257 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 | 258 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
8395be5e | 259 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, |
619c5cb6 VZ |
260 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, |
261 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
8395be5e | 262 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, |
619c5cb6 VZ |
263 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, |
264 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
c3def943 YM |
265 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, |
266 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, | |
267 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, | |
8395be5e | 268 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, |
c3def943 | 269 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, |
619c5cb6 | 270 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, |
8395be5e | 271 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, |
7e8e02df BW |
272 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
273 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, | |
8395be5e | 274 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, |
a2fbb9ea ET |
275 | { 0 } |
276 | }; | |
277 | ||
278 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
279 | ||
452427b0 YM |
280 | /* Global resources for unloading a previously loaded device */ |
281 | #define BNX2X_PREV_WAIT_NEEDED 1 | |
282 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); | |
283 | static LIST_HEAD(bnx2x_prev_list); | |
a8f47eb7 | 284 | |
285 | /* Forward declaration */ | |
286 | static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); | |
287 | static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); | |
288 | static int bnx2x_set_storm_rx_mode(struct bnx2x *bp); | |
289 | ||
a2fbb9ea ET |
290 | /**************************************************************************** |
291 | * General service functions | |
292 | ****************************************************************************/ | |
293 | ||
eeed018c MK |
294 | static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr); |
295 | ||
1191cb83 | 296 | static void __storm_memset_dma_mapping(struct bnx2x *bp, |
619c5cb6 VZ |
297 | u32 addr, dma_addr_t mapping) |
298 | { | |
299 | REG_WR(bp, addr, U64_LO(mapping)); | |
300 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
301 | } | |
302 | ||
1191cb83 ED |
303 | static void storm_memset_spq_addr(struct bnx2x *bp, |
304 | dma_addr_t mapping, u16 abs_fid) | |
619c5cb6 VZ |
305 | { |
306 | u32 addr = XSEM_REG_FAST_MEMORY + | |
307 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
308 | ||
309 | __storm_memset_dma_mapping(bp, addr, mapping); | |
310 | } | |
311 | ||
1191cb83 ED |
312 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, |
313 | u16 pf_id) | |
523224a3 | 314 | { |
619c5cb6 VZ |
315 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
316 | pf_id); | |
317 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
318 | pf_id); | |
319 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
320 | pf_id); | |
321 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
322 | pf_id); | |
523224a3 DK |
323 | } |
324 | ||
1191cb83 ED |
325 | static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
326 | u8 enable) | |
619c5cb6 VZ |
327 | { |
328 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
329 | enable); | |
330 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
331 | enable); | |
332 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
333 | enable); | |
334 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
335 | enable); | |
336 | } | |
523224a3 | 337 | |
1191cb83 ED |
338 | static void storm_memset_eq_data(struct bnx2x *bp, |
339 | struct event_ring_data *eq_data, | |
523224a3 DK |
340 | u16 pfid) |
341 | { | |
342 | size_t size = sizeof(struct event_ring_data); | |
343 | ||
344 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
345 | ||
346 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
347 | } | |
348 | ||
1191cb83 ED |
349 | static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, |
350 | u16 pfid) | |
523224a3 DK |
351 | { |
352 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
353 | REG_WR16(bp, addr, eq_prod); | |
354 | } | |
355 | ||
a2fbb9ea ET |
356 | /* used only at init |
357 | * locking is done by mcp | |
358 | */ | |
8d96286a | 359 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
360 | { |
361 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
362 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
363 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
364 | PCICFG_VENDOR_ID_OFFSET); | |
365 | } | |
366 | ||
a2fbb9ea ET |
367 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
368 | { | |
369 | u32 val; | |
370 | ||
371 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
372 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
373 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
374 | PCICFG_VENDOR_ID_OFFSET); | |
375 | ||
376 | return val; | |
377 | } | |
a2fbb9ea | 378 | |
f2e0899f DK |
379 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
380 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
381 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
382 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
383 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
384 | ||
6bf07b8e YM |
385 | static void bnx2x_dp_dmae(struct bnx2x *bp, |
386 | struct dmae_command *dmae, int msglvl) | |
fd1fc79d AE |
387 | { |
388 | u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; | |
6bf07b8e | 389 | int i; |
fd1fc79d AE |
390 | |
391 | switch (dmae->opcode & DMAE_COMMAND_DST) { | |
392 | case DMAE_CMD_DST_PCI: | |
393 | if (src_type == DMAE_CMD_SRC_PCI) | |
394 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
395 | "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" | |
396 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
397 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
398 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
399 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
400 | dmae->comp_val); | |
401 | else | |
402 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
403 | "src [%08x], len [%d*4], dst [%x:%08x]\n" | |
404 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
405 | dmae->opcode, dmae->src_addr_lo >> 2, | |
406 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
407 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
408 | dmae->comp_val); | |
409 | break; | |
410 | case DMAE_CMD_DST_GRC: | |
411 | if (src_type == DMAE_CMD_SRC_PCI) | |
412 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
413 | "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" | |
414 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
415 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
416 | dmae->len, dmae->dst_addr_lo >> 2, | |
417 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
418 | dmae->comp_val); | |
419 | else | |
420 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
421 | "src [%08x], len [%d*4], dst [%08x]\n" | |
422 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
423 | dmae->opcode, dmae->src_addr_lo >> 2, | |
424 | dmae->len, dmae->dst_addr_lo >> 2, | |
425 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
426 | dmae->comp_val); | |
427 | break; | |
428 | default: | |
429 | if (src_type == DMAE_CMD_SRC_PCI) | |
430 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
431 | "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" | |
432 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
433 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
434 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
435 | dmae->comp_val); | |
436 | else | |
437 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
438 | "src_addr [%08x] len [%d * 4] dst_addr [none]\n" | |
439 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
440 | dmae->opcode, dmae->src_addr_lo >> 2, | |
441 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
442 | dmae->comp_val); | |
443 | break; | |
444 | } | |
6bf07b8e YM |
445 | |
446 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) | |
447 | DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", | |
448 | i, *(((u32 *)dmae) + i)); | |
fd1fc79d | 449 | } |
f2e0899f | 450 | |
a2fbb9ea | 451 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 452 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
453 | { |
454 | u32 cmd_offset; | |
455 | int i; | |
456 | ||
457 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
458 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
459 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
460 | } |
461 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
462 | } | |
463 | ||
f2e0899f | 464 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 465 | { |
f2e0899f DK |
466 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
467 | DMAE_CMD_C_ENABLE); | |
468 | } | |
ad8d3948 | 469 | |
f2e0899f DK |
470 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
471 | { | |
472 | return opcode & ~DMAE_CMD_SRC_RESET; | |
473 | } | |
ad8d3948 | 474 | |
f2e0899f DK |
475 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
476 | bool with_comp, u8 comp_type) | |
477 | { | |
478 | u32 opcode = 0; | |
479 | ||
480 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
481 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 482 | |
f2e0899f DK |
483 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
484 | ||
485 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
486 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
487 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 488 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 489 | |
a2fbb9ea | 490 | #ifdef __BIG_ENDIAN |
f2e0899f | 491 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 492 | #else |
f2e0899f | 493 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 494 | #endif |
f2e0899f DK |
495 | if (with_comp) |
496 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
497 | return opcode; | |
498 | } | |
499 | ||
fd1fc79d | 500 | void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
8d96286a | 501 | struct dmae_command *dmae, |
502 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
503 | { |
504 | memset(dmae, 0, sizeof(struct dmae_command)); | |
505 | ||
506 | /* set the opcode */ | |
507 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
508 | true, DMAE_COMP_PCI); | |
509 | ||
510 | /* fill in the completion parameters */ | |
511 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
512 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
513 | dmae->comp_val = DMAE_COMP_VAL; | |
514 | } | |
515 | ||
fd1fc79d | 516 | /* issue a dmae command over the init-channel and wait for completion */ |
32316a46 AE |
517 | int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, |
518 | u32 *comp) | |
f2e0899f | 519 | { |
5e374b5a | 520 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
521 | int rc = 0; |
522 | ||
6bf07b8e YM |
523 | bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); |
524 | ||
525 | /* Lock the dmae channel. Disable BHs to prevent a dead-lock | |
619c5cb6 VZ |
526 | * as long as this code is called both from syscall context and |
527 | * from ndo_set_rx_mode() flow that may be called from BH. | |
528 | */ | |
eeed018c | 529 | |
6e30dd4e | 530 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 531 | |
f2e0899f | 532 | /* reset completion */ |
32316a46 | 533 | *comp = 0; |
a2fbb9ea | 534 | |
f2e0899f DK |
535 | /* post the command on the channel used for initializations */ |
536 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 537 | |
f2e0899f | 538 | /* wait for completion */ |
a2fbb9ea | 539 | udelay(5); |
32316a46 | 540 | while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 | 541 | |
95c6c616 AE |
542 | if (!cnt || |
543 | (bp->recovery_state != BNX2X_RECOVERY_DONE && | |
544 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
c3eefaf6 | 545 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
546 | rc = DMAE_TIMEOUT; |
547 | goto unlock; | |
a2fbb9ea | 548 | } |
ad8d3948 | 549 | cnt--; |
f2e0899f | 550 | udelay(50); |
a2fbb9ea | 551 | } |
32316a46 | 552 | if (*comp & DMAE_PCI_ERR_FLAG) { |
f2e0899f DK |
553 | BNX2X_ERR("DMAE PCI error!\n"); |
554 | rc = DMAE_PCI_ERROR; | |
555 | } | |
556 | ||
f2e0899f | 557 | unlock: |
eeed018c | 558 | |
6e30dd4e | 559 | spin_unlock_bh(&bp->dmae_lock); |
eeed018c | 560 | |
f2e0899f DK |
561 | return rc; |
562 | } | |
563 | ||
564 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
565 | u32 len32) | |
566 | { | |
6bf07b8e | 567 | int rc; |
f2e0899f DK |
568 | struct dmae_command dmae; |
569 | ||
570 | if (!bp->dmae_ready) { | |
571 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
572 | ||
127a425e AE |
573 | if (CHIP_IS_E1(bp)) |
574 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
575 | else | |
576 | bnx2x_init_str_wr(bp, dst_addr, data, len32); | |
f2e0899f DK |
577 | return; |
578 | } | |
579 | ||
580 | /* set opcode and fixed command fields */ | |
581 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
582 | ||
583 | /* fill in addresses and len */ | |
584 | dmae.src_addr_lo = U64_LO(dma_addr); | |
585 | dmae.src_addr_hi = U64_HI(dma_addr); | |
586 | dmae.dst_addr_lo = dst_addr >> 2; | |
587 | dmae.dst_addr_hi = 0; | |
588 | dmae.len = len32; | |
589 | ||
f2e0899f | 590 | /* issue the command and wait for completion */ |
32316a46 | 591 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); |
6bf07b8e YM |
592 | if (rc) { |
593 | BNX2X_ERR("DMAE returned failure %d\n", rc); | |
9dcd9acd | 594 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e | 595 | bnx2x_panic(); |
9dcd9acd | 596 | #endif |
6bf07b8e | 597 | } |
a2fbb9ea ET |
598 | } |
599 | ||
c18487ee | 600 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 601 | { |
6bf07b8e | 602 | int rc; |
5ff7b6d4 | 603 | struct dmae_command dmae; |
ad8d3948 EG |
604 | |
605 | if (!bp->dmae_ready) { | |
606 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
607 | int i; | |
608 | ||
51c1a580 | 609 | if (CHIP_IS_E1(bp)) |
127a425e AE |
610 | for (i = 0; i < len32; i++) |
611 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
51c1a580 | 612 | else |
127a425e AE |
613 | for (i = 0; i < len32; i++) |
614 | data[i] = REG_RD(bp, src_addr + i*4); | |
615 | ||
ad8d3948 EG |
616 | return; |
617 | } | |
618 | ||
f2e0899f DK |
619 | /* set opcode and fixed command fields */ |
620 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 621 | |
f2e0899f | 622 | /* fill in addresses and len */ |
5ff7b6d4 EG |
623 | dmae.src_addr_lo = src_addr >> 2; |
624 | dmae.src_addr_hi = 0; | |
625 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
626 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
627 | dmae.len = len32; | |
ad8d3948 | 628 | |
f2e0899f | 629 | /* issue the command and wait for completion */ |
32316a46 | 630 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); |
6bf07b8e YM |
631 | if (rc) { |
632 | BNX2X_ERR("DMAE returned failure %d\n", rc); | |
9dcd9acd | 633 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e | 634 | bnx2x_panic(); |
9dcd9acd | 635 | #endif |
c957d09f | 636 | } |
ad8d3948 EG |
637 | } |
638 | ||
8d96286a | 639 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
640 | u32 addr, u32 len) | |
573f2035 | 641 | { |
02e3c6cb | 642 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
643 | int offset = 0; |
644 | ||
02e3c6cb | 645 | while (len > dmae_wr_max) { |
573f2035 | 646 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
647 | addr + offset, dmae_wr_max); |
648 | offset += dmae_wr_max * 4; | |
649 | len -= dmae_wr_max; | |
573f2035 EG |
650 | } |
651 | ||
652 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
653 | } | |
654 | ||
97539f1e AE |
655 | enum storms { |
656 | XSTORM, | |
657 | TSTORM, | |
658 | CSTORM, | |
659 | USTORM, | |
660 | MAX_STORMS | |
661 | }; | |
34f80b04 | 662 | |
97539f1e AE |
663 | #define STORMS_NUM 4 |
664 | #define REGS_IN_ENTRY 4 | |
34f80b04 | 665 | |
97539f1e AE |
666 | static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp, |
667 | enum storms storm, | |
668 | int entry) | |
669 | { | |
670 | switch (storm) { | |
671 | case XSTORM: | |
672 | return XSTORM_ASSERT_LIST_OFFSET(entry); | |
673 | case TSTORM: | |
674 | return TSTORM_ASSERT_LIST_OFFSET(entry); | |
675 | case CSTORM: | |
676 | return CSTORM_ASSERT_LIST_OFFSET(entry); | |
677 | case USTORM: | |
678 | return USTORM_ASSERT_LIST_OFFSET(entry); | |
679 | case MAX_STORMS: | |
680 | default: | |
681 | BNX2X_ERR("unknown storm\n"); | |
34f80b04 | 682 | } |
97539f1e AE |
683 | return -EINVAL; |
684 | } | |
34f80b04 | 685 | |
97539f1e AE |
686 | static int bnx2x_mc_assert(struct bnx2x *bp) |
687 | { | |
688 | char last_idx; | |
689 | int i, j, rc = 0; | |
690 | enum storms storm; | |
691 | u32 regs[REGS_IN_ENTRY]; | |
692 | u32 bar_storm_intmem[STORMS_NUM] = { | |
693 | BAR_XSTRORM_INTMEM, | |
694 | BAR_TSTRORM_INTMEM, | |
695 | BAR_CSTRORM_INTMEM, | |
696 | BAR_USTRORM_INTMEM | |
697 | }; | |
698 | u32 storm_assert_list_index[STORMS_NUM] = { | |
699 | XSTORM_ASSERT_LIST_INDEX_OFFSET, | |
700 | TSTORM_ASSERT_LIST_INDEX_OFFSET, | |
701 | CSTORM_ASSERT_LIST_INDEX_OFFSET, | |
702 | USTORM_ASSERT_LIST_INDEX_OFFSET | |
703 | }; | |
704 | char *storms_string[STORMS_NUM] = { | |
705 | "XSTORM", | |
706 | "TSTORM", | |
707 | "CSTORM", | |
708 | "USTORM" | |
709 | }; | |
710 | ||
711 | for (storm = XSTORM; storm < MAX_STORMS; storm++) { | |
712 | last_idx = REG_RD8(bp, bar_storm_intmem[storm] + | |
713 | storm_assert_list_index[storm]); | |
714 | if (last_idx) | |
715 | BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n", | |
716 | storms_string[storm], last_idx); | |
717 | ||
718 | /* print the asserts */ | |
719 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
720 | /* read a single assert entry */ | |
721 | for (j = 0; j < REGS_IN_ENTRY; j++) | |
722 | regs[j] = REG_RD(bp, bar_storm_intmem[storm] + | |
723 | bnx2x_get_assert_list_entry(bp, | |
724 | storm, | |
725 | i) + | |
726 | sizeof(u32) * j); | |
727 | ||
728 | /* log entry if it contains a valid assert */ | |
729 | if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
730 | BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
731 | storms_string[storm], i, regs[3], | |
732 | regs[2], regs[1], regs[0]); | |
733 | rc++; | |
734 | } else { | |
735 | break; | |
736 | } | |
a2fbb9ea ET |
737 | } |
738 | } | |
34f80b04 | 739 | |
97539f1e AE |
740 | BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n", |
741 | CHIP_IS_E1(bp) ? "everest1" : | |
742 | CHIP_IS_E1H(bp) ? "everest1h" : | |
743 | CHIP_IS_E2(bp) ? "everest2" : "everest3", | |
744 | BCM_5710_FW_MAJOR_VERSION, | |
745 | BCM_5710_FW_MINOR_VERSION, | |
746 | BCM_5710_FW_REVISION_VERSION); | |
747 | ||
a2fbb9ea ET |
748 | return rc; |
749 | } | |
c14423fe | 750 | |
1a6974b2 YM |
751 | #define MCPR_TRACE_BUFFER_SIZE (0x800) |
752 | #define SCRATCH_BUFFER_SIZE(bp) \ | |
753 | (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000)) | |
754 | ||
7a25cc73 | 755 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 756 | { |
7a25cc73 | 757 | u32 addr, val; |
a2fbb9ea | 758 | u32 mark, offset; |
4781bfad | 759 | __be32 data[9]; |
a2fbb9ea | 760 | int word; |
f2e0899f | 761 | u32 trace_shmem_base; |
2145a920 VZ |
762 | if (BP_NOMCP(bp)) { |
763 | BNX2X_ERR("NO MCP - can not dump\n"); | |
764 | return; | |
765 | } | |
7a25cc73 DK |
766 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
767 | (bp->common.bc_ver & 0xff0000) >> 16, | |
768 | (bp->common.bc_ver & 0xff00) >> 8, | |
769 | (bp->common.bc_ver & 0xff)); | |
770 | ||
771 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
772 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
51c1a580 | 773 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
cdaa7cb8 | 774 | |
f2e0899f DK |
775 | if (BP_PATH(bp) == 0) |
776 | trace_shmem_base = bp->common.shmem_base; | |
777 | else | |
778 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
1a6974b2 YM |
779 | |
780 | /* sanity */ | |
781 | if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE || | |
782 | trace_shmem_base >= MCPR_SCRATCH_BASE(bp) + | |
783 | SCRATCH_BUFFER_SIZE(bp)) { | |
784 | BNX2X_ERR("Unable to dump trace buffer (mark %x)\n", | |
785 | trace_shmem_base); | |
786 | return; | |
787 | } | |
788 | ||
789 | addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE; | |
de128804 DK |
790 | |
791 | /* validate TRCB signature */ | |
792 | mark = REG_RD(bp, addr); | |
793 | if (mark != MFW_TRACE_SIGNATURE) { | |
794 | BNX2X_ERR("Trace buffer signature is missing."); | |
795 | return ; | |
796 | } | |
797 | ||
798 | /* read cyclic buffer pointer */ | |
799 | addr += 4; | |
cdaa7cb8 | 800 | mark = REG_RD(bp, addr); |
1a6974b2 YM |
801 | mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000; |
802 | if (mark >= trace_shmem_base || mark < addr + 4) { | |
803 | BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n"); | |
804 | return; | |
805 | } | |
7a25cc73 | 806 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 807 | |
7a25cc73 | 808 | printk("%s", lvl); |
2de67439 YM |
809 | |
810 | /* dump buffer after the mark */ | |
1a6974b2 | 811 | for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 812 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 813 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 814 | data[8] = 0x0; |
7995c64e | 815 | pr_cont("%s", (char *)data); |
a2fbb9ea | 816 | } |
2de67439 YM |
817 | |
818 | /* dump buffer before the mark */ | |
cdaa7cb8 | 819 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 820 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 821 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 822 | data[8] = 0x0; |
7995c64e | 823 | pr_cont("%s", (char *)data); |
a2fbb9ea | 824 | } |
7a25cc73 DK |
825 | printk("%s" "end of fw dump\n", lvl); |
826 | } | |
827 | ||
1191cb83 | 828 | static void bnx2x_fw_dump(struct bnx2x *bp) |
7a25cc73 DK |
829 | { |
830 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
831 | } |
832 | ||
823e1d90 YM |
833 | static void bnx2x_hc_int_disable(struct bnx2x *bp) |
834 | { | |
835 | int port = BP_PORT(bp); | |
836 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; | |
837 | u32 val = REG_RD(bp, addr); | |
838 | ||
839 | /* in E1 we must use only PCI configuration space to disable | |
16a5fd92 YM |
840 | * MSI/MSIX capability |
841 | * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
823e1d90 YM |
842 | */ |
843 | if (CHIP_IS_E1(bp)) { | |
844 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
845 | * Use mask register to prevent from HC sending interrupts | |
846 | * after we exit the function | |
847 | */ | |
848 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
849 | ||
850 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
851 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
852 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
853 | } else | |
854 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
855 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
856 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
857 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
858 | ||
859 | DP(NETIF_MSG_IFDOWN, | |
860 | "write %x to HC %d (addr 0x%x)\n", | |
861 | val, port, addr); | |
862 | ||
863 | /* flush all outstanding writes */ | |
864 | mmiowb(); | |
865 | ||
866 | REG_WR(bp, addr, val); | |
867 | if (REG_RD(bp, addr) != val) | |
6bf07b8e | 868 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
823e1d90 YM |
869 | } |
870 | ||
871 | static void bnx2x_igu_int_disable(struct bnx2x *bp) | |
872 | { | |
873 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
874 | ||
875 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
876 | IGU_PF_CONF_INT_LINE_EN | | |
877 | IGU_PF_CONF_ATTN_BIT_EN); | |
878 | ||
879 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); | |
880 | ||
881 | /* flush all outstanding writes */ | |
882 | mmiowb(); | |
883 | ||
884 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
885 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
6bf07b8e | 886 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
823e1d90 YM |
887 | } |
888 | ||
889 | static void bnx2x_int_disable(struct bnx2x *bp) | |
890 | { | |
891 | if (bp->common.int_block == INT_BLOCK_HC) | |
892 | bnx2x_hc_int_disable(bp); | |
893 | else | |
894 | bnx2x_igu_int_disable(bp); | |
895 | } | |
896 | ||
897 | void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) | |
a2fbb9ea ET |
898 | { |
899 | int i; | |
523224a3 DK |
900 | u16 j; |
901 | struct hc_sp_status_block_data sp_sb_data; | |
902 | int func = BP_FUNC(bp); | |
903 | #ifdef BNX2X_STOP_ON_ERROR | |
904 | u16 start = 0, end = 0; | |
6383c0b3 | 905 | u8 cos; |
523224a3 | 906 | #endif |
0155a27c | 907 | if (IS_PF(bp) && disable_int) |
823e1d90 | 908 | bnx2x_int_disable(bp); |
a2fbb9ea | 909 | |
66e855f3 | 910 | bp->stats_state = STATS_STATE_DISABLED; |
7a752993 | 911 | bp->eth_stats.unrecoverable_error++; |
66e855f3 YG |
912 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
913 | ||
a2fbb9ea ET |
914 | BNX2X_ERR("begin crash dump -----------------\n"); |
915 | ||
8440d2b6 EG |
916 | /* Indices */ |
917 | /* Common */ | |
0155a27c YM |
918 | if (IS_PF(bp)) { |
919 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
920 | int data_size, cstorm_offset; | |
921 | ||
922 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", | |
923 | bp->def_idx, bp->def_att_idx, bp->attn_state, | |
924 | bp->spq_prod_idx, bp->stats_counter); | |
925 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", | |
926 | def_sb->atten_status_block.attn_bits, | |
927 | def_sb->atten_status_block.attn_bits_ack, | |
928 | def_sb->atten_status_block.status_block_id, | |
929 | def_sb->atten_status_block.attn_bits_index); | |
930 | BNX2X_ERR(" def ("); | |
931 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
932 | pr_cont("0x%x%s", | |
933 | def_sb->sp_sb.index_values[i], | |
934 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
935 | ||
936 | data_size = sizeof(struct hc_sp_status_block_data) / | |
937 | sizeof(u32); | |
938 | cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func); | |
939 | for (i = 0; i < data_size; i++) | |
940 | *((u32 *)&sp_sb_data + i) = | |
941 | REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset + | |
942 | i * sizeof(u32)); | |
943 | ||
944 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", | |
945 | sp_sb_data.igu_sb_id, | |
946 | sp_sb_data.igu_seg_id, | |
947 | sp_sb_data.p_func.pf_id, | |
948 | sp_sb_data.p_func.vnic_id, | |
949 | sp_sb_data.p_func.vf_id, | |
950 | sp_sb_data.p_func.vf_valid, | |
951 | sp_sb_data.state); | |
952 | } | |
523224a3 | 953 | |
ec6ba945 | 954 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 955 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 956 | int loop; |
f2e0899f | 957 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
958 | struct hc_status_block_data_e1x sb_data_e1x; |
959 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
960 | CHIP_IS_E1x(bp) ? |
961 | sb_data_e1x.common.state_machine : | |
962 | sb_data_e2.common.state_machine; | |
523224a3 | 963 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
964 | CHIP_IS_E1x(bp) ? |
965 | sb_data_e1x.index_data : | |
966 | sb_data_e2.index_data; | |
6383c0b3 | 967 | u8 data_size, cos; |
523224a3 | 968 | u32 *sb_data_p; |
6383c0b3 | 969 | struct bnx2x_fp_txdata txdata; |
523224a3 | 970 | |
e2611998 YM |
971 | if (!bp->fp) |
972 | break; | |
973 | ||
974 | if (!fp->rx_cons_sb) | |
975 | continue; | |
976 | ||
523224a3 | 977 | /* Rx */ |
51c1a580 | 978 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 979 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 980 | fp->rx_comp_prod, |
66e855f3 | 981 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
51c1a580 | 982 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
8440d2b6 | 983 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 984 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 985 | |
523224a3 | 986 | /* Tx */ |
6383c0b3 AE |
987 | for_each_cos_in_tx_queue(fp, cos) |
988 | { | |
1fc3de94 | 989 | if (!fp->txdata_ptr[cos]) |
e2611998 YM |
990 | break; |
991 | ||
65565884 | 992 | txdata = *fp->txdata_ptr[cos]; |
e2611998 YM |
993 | |
994 | if (!txdata.tx_cons_sb) | |
995 | continue; | |
996 | ||
51c1a580 | 997 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
6383c0b3 AE |
998 | i, txdata.tx_pkt_prod, |
999 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
1000 | txdata.tx_bd_cons, | |
1001 | le16_to_cpu(*txdata.tx_cons_sb)); | |
1002 | } | |
523224a3 | 1003 | |
619c5cb6 VZ |
1004 | loop = CHIP_IS_E1x(bp) ? |
1005 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
1006 | |
1007 | /* host sb data */ | |
1008 | ||
ec6ba945 VZ |
1009 | if (IS_FCOE_FP(fp)) |
1010 | continue; | |
55c11941 | 1011 | |
523224a3 DK |
1012 | BNX2X_ERR(" run indexes ("); |
1013 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
1014 | pr_cont("0x%x%s", | |
1015 | fp->sb_running_index[j], | |
1016 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
1017 | ||
1018 | BNX2X_ERR(" indexes ("); | |
1019 | for (j = 0; j < loop; j++) | |
1020 | pr_cont("0x%x%s", | |
1021 | fp->sb_index_values[j], | |
1022 | (j == loop - 1) ? ")" : " "); | |
0155a27c YM |
1023 | |
1024 | /* VF cannot access FW refelection for status block */ | |
1025 | if (IS_VF(bp)) | |
1026 | continue; | |
1027 | ||
523224a3 | 1028 | /* fw sb data */ |
619c5cb6 VZ |
1029 | data_size = CHIP_IS_E1x(bp) ? |
1030 | sizeof(struct hc_status_block_data_e1x) : | |
1031 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 1032 | data_size /= sizeof(u32); |
619c5cb6 VZ |
1033 | sb_data_p = CHIP_IS_E1x(bp) ? |
1034 | (u32 *)&sb_data_e1x : | |
1035 | (u32 *)&sb_data_e2; | |
523224a3 DK |
1036 | /* copy sb data in here */ |
1037 | for (j = 0; j < data_size; j++) | |
1038 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
1039 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
1040 | j * sizeof(u32)); | |
1041 | ||
619c5cb6 | 1042 | if (!CHIP_IS_E1x(bp)) { |
51c1a580 | 1043 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
1044 | sb_data_e2.common.p_func.pf_id, |
1045 | sb_data_e2.common.p_func.vf_id, | |
1046 | sb_data_e2.common.p_func.vf_valid, | |
1047 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
1048 | sb_data_e2.common.same_igu_sb_1b, |
1049 | sb_data_e2.common.state); | |
f2e0899f | 1050 | } else { |
51c1a580 | 1051 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
1052 | sb_data_e1x.common.p_func.pf_id, |
1053 | sb_data_e1x.common.p_func.vf_id, | |
1054 | sb_data_e1x.common.p_func.vf_valid, | |
1055 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
1056 | sb_data_e1x.common.same_igu_sb_1b, |
1057 | sb_data_e1x.common.state); | |
f2e0899f | 1058 | } |
523224a3 DK |
1059 | |
1060 | /* SB_SMs data */ | |
1061 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
51c1a580 MS |
1062 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
1063 | j, hc_sm_p[j].__flags, | |
1064 | hc_sm_p[j].igu_sb_id, | |
1065 | hc_sm_p[j].igu_seg_id, | |
1066 | hc_sm_p[j].time_to_expire, | |
1067 | hc_sm_p[j].timer_value); | |
523224a3 DK |
1068 | } |
1069 | ||
16a5fd92 | 1070 | /* Indices data */ |
523224a3 | 1071 | for (j = 0; j < loop; j++) { |
51c1a580 | 1072 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
523224a3 DK |
1073 | hc_index_p[j].flags, |
1074 | hc_index_p[j].timeout); | |
1075 | } | |
8440d2b6 | 1076 | } |
a2fbb9ea | 1077 | |
523224a3 | 1078 | #ifdef BNX2X_STOP_ON_ERROR |
0155a27c YM |
1079 | if (IS_PF(bp)) { |
1080 | /* event queue */ | |
1081 | BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); | |
1082 | for (i = 0; i < NUM_EQ_DESC; i++) { | |
1083 | u32 *data = (u32 *)&bp->eq_ring[i].message.data; | |
1084 | ||
1085 | BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n", | |
1086 | i, bp->eq_ring[i].message.opcode, | |
1087 | bp->eq_ring[i].message.error); | |
1088 | BNX2X_ERR("data: %x %x %x\n", | |
1089 | data[0], data[1], data[2]); | |
1090 | } | |
04c46736 YM |
1091 | } |
1092 | ||
8440d2b6 EG |
1093 | /* Rings */ |
1094 | /* Rx */ | |
55c11941 | 1095 | for_each_valid_rx_queue(bp, i) { |
8440d2b6 | 1096 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1097 | |
e2611998 YM |
1098 | if (!bp->fp) |
1099 | break; | |
1100 | ||
1101 | if (!fp->rx_cons_sb) | |
1102 | continue; | |
1103 | ||
a2fbb9ea ET |
1104 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); |
1105 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 1106 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
1107 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
1108 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
1109 | ||
c3eefaf6 | 1110 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
44151acb | 1111 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
a2fbb9ea ET |
1112 | } |
1113 | ||
3196a88a EG |
1114 | start = RX_SGE(fp->rx_sge_prod); |
1115 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 1116 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
1117 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
1118 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
1119 | ||
c3eefaf6 EG |
1120 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
1121 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
1122 | } |
1123 | ||
a2fbb9ea ET |
1124 | start = RCQ_BD(fp->rx_comp_cons - 10); |
1125 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 1126 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
1127 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
1128 | ||
c3eefaf6 EG |
1129 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
1130 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
1131 | } |
1132 | } | |
1133 | ||
8440d2b6 | 1134 | /* Tx */ |
55c11941 | 1135 | for_each_valid_tx_queue(bp, i) { |
8440d2b6 | 1136 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
e2611998 YM |
1137 | |
1138 | if (!bp->fp) | |
1139 | break; | |
1140 | ||
6383c0b3 | 1141 | for_each_cos_in_tx_queue(fp, cos) { |
65565884 | 1142 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
6383c0b3 | 1143 | |
1fc3de94 | 1144 | if (!fp->txdata_ptr[cos]) |
e2611998 YM |
1145 | break; |
1146 | ||
ea36475a | 1147 | if (!txdata->tx_cons_sb) |
e2611998 YM |
1148 | continue; |
1149 | ||
6383c0b3 AE |
1150 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); |
1151 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
1152 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1153 | struct sw_tx_bd *sw_bd = | |
1154 | &txdata->tx_buf_ring[j]; | |
1155 | ||
51c1a580 | 1156 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
6383c0b3 AE |
1157 | i, cos, j, sw_bd->skb, |
1158 | sw_bd->first_bd); | |
1159 | } | |
8440d2b6 | 1160 | |
6383c0b3 AE |
1161 | start = TX_BD(txdata->tx_bd_cons - 10); |
1162 | end = TX_BD(txdata->tx_bd_cons + 254); | |
1163 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1164 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 1165 | |
51c1a580 | 1166 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
6383c0b3 AE |
1167 | i, cos, j, tx_bd[0], tx_bd[1], |
1168 | tx_bd[2], tx_bd[3]); | |
1169 | } | |
8440d2b6 EG |
1170 | } |
1171 | } | |
523224a3 | 1172 | #endif |
0155a27c YM |
1173 | if (IS_PF(bp)) { |
1174 | bnx2x_fw_dump(bp); | |
1175 | bnx2x_mc_assert(bp); | |
1176 | } | |
a2fbb9ea | 1177 | BNX2X_ERR("end crash dump -----------------\n"); |
a2fbb9ea ET |
1178 | } |
1179 | ||
619c5cb6 VZ |
1180 | /* |
1181 | * FLR Support for E2 | |
1182 | * | |
1183 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
1184 | * initialization. | |
1185 | */ | |
16a5fd92 | 1186 | #define FLR_WAIT_USEC 10000 /* 10 milliseconds */ |
89db4ad8 AE |
1187 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
1188 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ | |
619c5cb6 VZ |
1189 | |
1190 | struct pbf_pN_buf_regs { | |
1191 | int pN; | |
1192 | u32 init_crd; | |
1193 | u32 crd; | |
1194 | u32 crd_freed; | |
1195 | }; | |
1196 | ||
1197 | struct pbf_pN_cmd_regs { | |
1198 | int pN; | |
1199 | u32 lines_occup; | |
1200 | u32 lines_freed; | |
1201 | }; | |
1202 | ||
1203 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
1204 | struct pbf_pN_buf_regs *regs, | |
1205 | u32 poll_count) | |
1206 | { | |
1207 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
1208 | u32 cur_cnt = poll_count; | |
1209 | ||
1210 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
1211 | crd = crd_start = REG_RD(bp, regs->crd); | |
1212 | init_crd = REG_RD(bp, regs->init_crd); | |
1213 | ||
1214 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
1215 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
1216 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
1217 | ||
1218 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
1219 | (init_crd - crd_start))) { | |
1220 | if (cur_cnt--) { | |
89db4ad8 | 1221 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1222 | crd = REG_RD(bp, regs->crd); |
1223 | crd_freed = REG_RD(bp, regs->crd_freed); | |
1224 | } else { | |
1225 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
1226 | regs->pN); | |
1227 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
1228 | regs->pN, crd); | |
1229 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
1230 | regs->pN, crd_freed); | |
1231 | break; | |
1232 | } | |
1233 | } | |
1234 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
89db4ad8 | 1235 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1236 | } |
1237 | ||
1238 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
1239 | struct pbf_pN_cmd_regs *regs, | |
1240 | u32 poll_count) | |
1241 | { | |
1242 | u32 occup, to_free, freed, freed_start; | |
1243 | u32 cur_cnt = poll_count; | |
1244 | ||
1245 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
1246 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
1247 | ||
1248 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
1249 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
1250 | ||
1251 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
1252 | if (cur_cnt--) { | |
89db4ad8 | 1253 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1254 | occup = REG_RD(bp, regs->lines_occup); |
1255 | freed = REG_RD(bp, regs->lines_freed); | |
1256 | } else { | |
1257 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
1258 | regs->pN); | |
1259 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
1260 | regs->pN, occup); | |
1261 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
1262 | regs->pN, freed); | |
1263 | break; | |
1264 | } | |
1265 | } | |
1266 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
89db4ad8 | 1267 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1268 | } |
1269 | ||
1191cb83 ED |
1270 | static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, |
1271 | u32 expected, u32 poll_count) | |
619c5cb6 VZ |
1272 | { |
1273 | u32 cur_cnt = poll_count; | |
1274 | u32 val; | |
1275 | ||
1276 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
89db4ad8 | 1277 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1278 | |
1279 | return val; | |
1280 | } | |
1281 | ||
d16132ce AE |
1282 | int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, |
1283 | char *msg, u32 poll_cnt) | |
619c5cb6 VZ |
1284 | { |
1285 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1286 | if (val != 0) { | |
1287 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1288 | return 1; | |
1289 | } | |
1290 | return 0; | |
1291 | } | |
1292 | ||
d16132ce AE |
1293 | /* Common routines with VF FLR cleanup */ |
1294 | u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
619c5cb6 VZ |
1295 | { |
1296 | /* adjust polling timeout */ | |
1297 | if (CHIP_REV_IS_EMUL(bp)) | |
1298 | return FLR_POLL_CNT * 2000; | |
1299 | ||
1300 | if (CHIP_REV_IS_FPGA(bp)) | |
1301 | return FLR_POLL_CNT * 120; | |
1302 | ||
1303 | return FLR_POLL_CNT; | |
1304 | } | |
1305 | ||
d16132ce | 1306 | void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) |
619c5cb6 VZ |
1307 | { |
1308 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1309 | {0, (CHIP_IS_E3B0(bp)) ? | |
1310 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1311 | PBF_REG_P0_TQ_OCCUPANCY, | |
1312 | (CHIP_IS_E3B0(bp)) ? | |
1313 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1314 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1315 | {1, (CHIP_IS_E3B0(bp)) ? | |
1316 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1317 | PBF_REG_P1_TQ_OCCUPANCY, | |
1318 | (CHIP_IS_E3B0(bp)) ? | |
1319 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1320 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1321 | {4, (CHIP_IS_E3B0(bp)) ? | |
1322 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1323 | PBF_REG_P4_TQ_OCCUPANCY, | |
1324 | (CHIP_IS_E3B0(bp)) ? | |
1325 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1326 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1327 | }; | |
1328 | ||
1329 | struct pbf_pN_buf_regs buf_regs[] = { | |
1330 | {0, (CHIP_IS_E3B0(bp)) ? | |
1331 | PBF_REG_INIT_CRD_Q0 : | |
1332 | PBF_REG_P0_INIT_CRD , | |
1333 | (CHIP_IS_E3B0(bp)) ? | |
1334 | PBF_REG_CREDIT_Q0 : | |
1335 | PBF_REG_P0_CREDIT, | |
1336 | (CHIP_IS_E3B0(bp)) ? | |
1337 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1338 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1339 | {1, (CHIP_IS_E3B0(bp)) ? | |
1340 | PBF_REG_INIT_CRD_Q1 : | |
1341 | PBF_REG_P1_INIT_CRD, | |
1342 | (CHIP_IS_E3B0(bp)) ? | |
1343 | PBF_REG_CREDIT_Q1 : | |
1344 | PBF_REG_P1_CREDIT, | |
1345 | (CHIP_IS_E3B0(bp)) ? | |
1346 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1347 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1348 | {4, (CHIP_IS_E3B0(bp)) ? | |
1349 | PBF_REG_INIT_CRD_LB_Q : | |
1350 | PBF_REG_P4_INIT_CRD, | |
1351 | (CHIP_IS_E3B0(bp)) ? | |
1352 | PBF_REG_CREDIT_LB_Q : | |
1353 | PBF_REG_P4_CREDIT, | |
1354 | (CHIP_IS_E3B0(bp)) ? | |
1355 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1356 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1357 | }; | |
1358 | ||
1359 | int i; | |
1360 | ||
1361 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1362 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1363 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1364 | ||
619c5cb6 VZ |
1365 | /* Verify the transmission buffers are flushed P0, P1, P4 */ |
1366 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1367 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1368 | } | |
1369 | ||
1370 | #define OP_GEN_PARAM(param) \ | |
1371 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1372 | ||
1373 | #define OP_GEN_TYPE(type) \ | |
1374 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1375 | ||
1376 | #define OP_GEN_AGG_VECT(index) \ | |
1377 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1378 | ||
d16132ce | 1379 | int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) |
619c5cb6 | 1380 | { |
86564c3f | 1381 | u32 op_gen_command = 0; |
619c5cb6 VZ |
1382 | u32 comp_addr = BAR_CSTRORM_INTMEM + |
1383 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1384 | int ret = 0; | |
1385 | ||
1386 | if (REG_RD(bp, comp_addr)) { | |
89db4ad8 | 1387 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
619c5cb6 VZ |
1388 | return 1; |
1389 | } | |
1390 | ||
86564c3f YM |
1391 | op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); |
1392 | op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1393 | op_gen_command |= OP_GEN_AGG_VECT(clnup_func); | |
1394 | op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
619c5cb6 | 1395 | |
89db4ad8 | 1396 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
86564c3f | 1397 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); |
619c5cb6 VZ |
1398 | |
1399 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1400 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
51c1a580 MS |
1401 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
1402 | (REG_RD(bp, comp_addr))); | |
d16132ce AE |
1403 | bnx2x_panic(); |
1404 | return 1; | |
619c5cb6 | 1405 | } |
16a5fd92 | 1406 | /* Zero completion for next FLR */ |
619c5cb6 VZ |
1407 | REG_WR(bp, comp_addr, 0); |
1408 | ||
1409 | return ret; | |
1410 | } | |
1411 | ||
b56e9670 | 1412 | u8 bnx2x_is_pcie_pending(struct pci_dev *dev) |
619c5cb6 | 1413 | { |
619c5cb6 VZ |
1414 | u16 status; |
1415 | ||
2a80eebc | 1416 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
619c5cb6 VZ |
1417 | return status & PCI_EXP_DEVSTA_TRPND; |
1418 | } | |
1419 | ||
1420 | /* PF FLR specific routines | |
1421 | */ | |
1422 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1423 | { | |
619c5cb6 VZ |
1424 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ |
1425 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1426 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1427 | "CFC PF usage counter timed out", | |
1428 | poll_cnt)) | |
1429 | return 1; | |
1430 | ||
619c5cb6 VZ |
1431 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ |
1432 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1433 | DORQ_REG_PF_USAGE_CNT, | |
1434 | "DQ PF usage counter timed out", | |
1435 | poll_cnt)) | |
1436 | return 1; | |
1437 | ||
1438 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1439 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1440 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1441 | "QM PF usage counter timed out", | |
1442 | poll_cnt)) | |
1443 | return 1; | |
1444 | ||
1445 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1446 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1447 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1448 | "Timers VNIC usage counter timed out", | |
1449 | poll_cnt)) | |
1450 | return 1; | |
1451 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1452 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1453 | "Timers NUM_SCANS usage counter timed out", | |
1454 | poll_cnt)) | |
1455 | return 1; | |
1456 | ||
1457 | /* Wait DMAE PF usage counter to zero */ | |
1458 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1459 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
6bf07b8e | 1460 | "DMAE command register timed out", |
619c5cb6 VZ |
1461 | poll_cnt)) |
1462 | return 1; | |
1463 | ||
1464 | return 0; | |
1465 | } | |
1466 | ||
1467 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1468 | { | |
1469 | u32 val; | |
1470 | ||
1471 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1472 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1473 | ||
1474 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1475 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1476 | ||
1477 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1478 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1479 | ||
1480 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1481 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1482 | ||
1483 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1484 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1485 | ||
1486 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1487 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1488 | ||
1489 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1490 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1491 | ||
1492 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1493 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1494 | val); | |
1495 | } | |
1496 | ||
1497 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1498 | { | |
1499 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1500 | ||
1501 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1502 | ||
1503 | /* Re-enable PF target read access */ | |
1504 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1505 | ||
1506 | /* Poll HW usage counters */ | |
89db4ad8 | 1507 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
619c5cb6 VZ |
1508 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
1509 | return -EBUSY; | |
1510 | ||
1511 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1512 | ||
1513 | /* Send the FW cleanup command */ | |
1514 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1515 | return -EBUSY; | |
1516 | ||
1517 | /* ATC cleanup */ | |
1518 | ||
1519 | /* Verify TX hw is flushed */ | |
1520 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1521 | ||
1522 | /* Wait 100ms (not adjusted according to platform) */ | |
1523 | msleep(100); | |
1524 | ||
1525 | /* Verify no pending pci transactions */ | |
1526 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1527 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1528 | ||
1529 | /* Debug */ | |
1530 | bnx2x_hw_enable_status(bp); | |
1531 | ||
1532 | /* | |
1533 | * Master enable - Due to WB DMAE writes performed before this | |
1534 | * register is re-initialized as part of the regular function init | |
1535 | */ | |
1536 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1537 | ||
1538 | return 0; | |
1539 | } | |
1540 | ||
f2e0899f | 1541 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1542 | { |
34f80b04 | 1543 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1544 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1545 | u32 val = REG_RD(bp, addr); | |
69c326b3 DK |
1546 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1547 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1548 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
a2fbb9ea ET |
1549 | |
1550 | if (msix) { | |
8badd27a EG |
1551 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1552 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1553 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1554 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
69c326b3 DK |
1555 | if (single_msix) |
1556 | val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; | |
8badd27a EG |
1557 | } else if (msi) { |
1558 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1559 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1560 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1561 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1562 | } else { |
1563 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1564 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1565 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1566 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1567 | |
a0fd065c | 1568 | if (!CHIP_IS_E1(bp)) { |
51c1a580 MS |
1569 | DP(NETIF_MSG_IFUP, |
1570 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); | |
615f8fd9 | 1571 | |
a0fd065c | 1572 | REG_WR(bp, addr, val); |
615f8fd9 | 1573 | |
a0fd065c DK |
1574 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1575 | } | |
a2fbb9ea ET |
1576 | } |
1577 | ||
a0fd065c DK |
1578 | if (CHIP_IS_E1(bp)) |
1579 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1580 | ||
51c1a580 MS |
1581 | DP(NETIF_MSG_IFUP, |
1582 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, | |
1583 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1584 | |
1585 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1586 | /* |
1587 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1588 | */ | |
1589 | mmiowb(); | |
1590 | barrier(); | |
34f80b04 | 1591 | |
f2e0899f | 1592 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1593 | /* init leading/trailing edge */ |
fb3bff17 | 1594 | if (IS_MF(bp)) { |
3395a033 | 1595 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1596 | if (bp->port.pmf) |
4acac6a5 EG |
1597 | /* enable nig and gpio3 attention */ |
1598 | val |= 0x1100; | |
34f80b04 EG |
1599 | } else |
1600 | val = 0xffff; | |
1601 | ||
1602 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1603 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1604 | } | |
37dbbf32 EG |
1605 | |
1606 | /* Make sure that interrupts are indeed enabled from here on */ | |
1607 | mmiowb(); | |
a2fbb9ea ET |
1608 | } |
1609 | ||
f2e0899f DK |
1610 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1611 | { | |
1612 | u32 val; | |
30a5de77 DK |
1613 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1614 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1615 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
f2e0899f DK |
1616 | |
1617 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1618 | ||
1619 | if (msix) { | |
1620 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1621 | IGU_PF_CONF_SINGLE_ISR_EN); | |
ebe61d80 | 1622 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
f2e0899f | 1623 | IGU_PF_CONF_ATTN_BIT_EN); |
30a5de77 DK |
1624 | |
1625 | if (single_msix) | |
1626 | val |= IGU_PF_CONF_SINGLE_ISR_EN; | |
f2e0899f DK |
1627 | } else if (msi) { |
1628 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
ebe61d80 | 1629 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
f2e0899f DK |
1630 | IGU_PF_CONF_ATTN_BIT_EN | |
1631 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1632 | } else { | |
1633 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
ebe61d80 | 1634 | val |= (IGU_PF_CONF_INT_LINE_EN | |
f2e0899f DK |
1635 | IGU_PF_CONF_ATTN_BIT_EN | |
1636 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1637 | } | |
1638 | ||
ebe61d80 YM |
1639 | /* Clean previous status - need to configure igu prior to ack*/ |
1640 | if ((!msix) || single_msix) { | |
1641 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1642 | bnx2x_ack_int(bp); | |
1643 | } | |
1644 | ||
1645 | val |= IGU_PF_CONF_FUNC_EN; | |
1646 | ||
51c1a580 | 1647 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
f2e0899f DK |
1648 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
1649 | ||
1650 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1651 | ||
79a8557a YM |
1652 | if (val & IGU_PF_CONF_INT_LINE_EN) |
1653 | pci_intx(bp->pdev, true); | |
1654 | ||
f2e0899f DK |
1655 | barrier(); |
1656 | ||
1657 | /* init leading/trailing edge */ | |
1658 | if (IS_MF(bp)) { | |
3395a033 | 1659 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1660 | if (bp->port.pmf) |
1661 | /* enable nig and gpio3 attention */ | |
1662 | val |= 0x1100; | |
1663 | } else | |
1664 | val = 0xffff; | |
1665 | ||
1666 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1667 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1668 | ||
1669 | /* Make sure that interrupts are indeed enabled from here on */ | |
1670 | mmiowb(); | |
1671 | } | |
1672 | ||
1673 | void bnx2x_int_enable(struct bnx2x *bp) | |
1674 | { | |
1675 | if (bp->common.int_block == INT_BLOCK_HC) | |
1676 | bnx2x_hc_int_enable(bp); | |
1677 | else | |
1678 | bnx2x_igu_int_enable(bp); | |
1679 | } | |
1680 | ||
9f6c9258 | 1681 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1682 | { |
a2fbb9ea | 1683 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1684 | int i, offset; |
a2fbb9ea | 1685 | |
f8ef6e44 YG |
1686 | if (disable_hw) |
1687 | /* prevent the HW from sending interrupts */ | |
1688 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1689 | |
1690 | /* make sure all ISRs are done */ | |
1691 | if (msix) { | |
8badd27a EG |
1692 | synchronize_irq(bp->msix_table[0].vector); |
1693 | offset = 1; | |
55c11941 MS |
1694 | if (CNIC_SUPPORT(bp)) |
1695 | offset++; | |
ec6ba945 | 1696 | for_each_eth_queue(bp, i) |
754a2f52 | 1697 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1698 | } else |
1699 | synchronize_irq(bp->pdev->irq); | |
1700 | ||
1701 | /* make sure sp_task is not running */ | |
1cf167f2 | 1702 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1703 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1704 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1705 | } |
1706 | ||
34f80b04 | 1707 | /* fast path */ |
a2fbb9ea ET |
1708 | |
1709 | /* | |
34f80b04 | 1710 | * General service functions |
a2fbb9ea ET |
1711 | */ |
1712 | ||
72fd0718 VZ |
1713 | /* Return true if succeeded to acquire the lock */ |
1714 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1715 | { | |
1716 | u32 lock_status; | |
1717 | u32 resource_bit = (1 << resource); | |
1718 | int func = BP_FUNC(bp); | |
1719 | u32 hw_lock_control_reg; | |
1720 | ||
51c1a580 MS |
1721 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1722 | "Trying to take a lock on resource %d\n", resource); | |
72fd0718 VZ |
1723 | |
1724 | /* Validating that the resource is within range */ | |
1725 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1726 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
72fd0718 VZ |
1727 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
1728 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1729 | return false; |
72fd0718 VZ |
1730 | } |
1731 | ||
1732 | if (func <= 5) | |
1733 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1734 | else | |
1735 | hw_lock_control_reg = | |
1736 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1737 | ||
1738 | /* Try to acquire the lock */ | |
1739 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1740 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1741 | if (lock_status & resource_bit) | |
1742 | return true; | |
1743 | ||
51c1a580 MS |
1744 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1745 | "Failed to get a lock on resource %d\n", resource); | |
72fd0718 VZ |
1746 | return false; |
1747 | } | |
1748 | ||
c9ee9206 VZ |
1749 | /** |
1750 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1751 | * | |
1752 | * @bp: driver handle | |
1753 | * | |
1754 | * Returns the recovery leader resource id according to the engine this function | |
1755 | * belongs to. Currently only only 2 engines is supported. | |
1756 | */ | |
1191cb83 | 1757 | static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) |
c9ee9206 VZ |
1758 | { |
1759 | if (BP_PATH(bp)) | |
1760 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1761 | else | |
1762 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1763 | } | |
1764 | ||
1765 | /** | |
2de67439 | 1766 | * bnx2x_trylock_leader_lock- try to acquire a leader lock. |
c9ee9206 VZ |
1767 | * |
1768 | * @bp: driver handle | |
1769 | * | |
2de67439 | 1770 | * Tries to acquire a leader lock for current engine. |
c9ee9206 | 1771 | */ |
1191cb83 | 1772 | static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) |
c9ee9206 VZ |
1773 | { |
1774 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1775 | } | |
1776 | ||
619c5cb6 | 1777 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
55c11941 | 1778 | |
fd1fc79d AE |
1779 | /* schedule the sp task and mark that interrupt occurred (runs from ISR) */ |
1780 | static int bnx2x_schedule_sp_task(struct bnx2x *bp) | |
1781 | { | |
1782 | /* Set the interrupt occurred bit for the sp-task to recognize it | |
1783 | * must ack the interrupt and transition according to the IGU | |
1784 | * state machine. | |
1785 | */ | |
1786 | atomic_set(&bp->interrupt_occurred, 1); | |
1787 | ||
1788 | /* The sp_task must execute only after this bit | |
1789 | * is set, otherwise we will get out of sync and miss all | |
1790 | * further interrupts. Hence, the barrier. | |
1791 | */ | |
1792 | smp_wmb(); | |
1793 | ||
1794 | /* schedule sp_task to workqueue */ | |
1795 | return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); | |
1796 | } | |
3196a88a | 1797 | |
619c5cb6 | 1798 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1799 | { |
1800 | struct bnx2x *bp = fp->bp; | |
1801 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1802 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 | 1803 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
15192a8c | 1804 | struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a2fbb9ea | 1805 | |
34f80b04 | 1806 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1807 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1808 | fp->index, cid, command, bp->state, |
34f80b04 | 1809 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1810 | |
fd1fc79d AE |
1811 | /* If cid is within VF range, replace the slowpath object with the |
1812 | * one corresponding to this VF | |
1813 | */ | |
1814 | if (cid >= BNX2X_FIRST_VF_CID && | |
1815 | cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) | |
1816 | bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); | |
1817 | ||
619c5cb6 VZ |
1818 | switch (command) { |
1819 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1820 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1821 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1822 | break; | |
d6cae238 | 1823 | |
619c5cb6 | 1824 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1825 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1826 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1827 | break; |
1828 | ||
6383c0b3 | 1829 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
51c1a580 | 1830 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
6383c0b3 AE |
1831 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
1832 | break; | |
1833 | ||
619c5cb6 | 1834 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1835 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1836 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1837 | break; |
1838 | ||
619c5cb6 | 1839 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
6bf07b8e | 1840 | DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid); |
619c5cb6 | 1841 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1842 | break; |
1843 | ||
619c5cb6 | 1844 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1845 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1846 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1847 | break; |
619c5cb6 | 1848 | |
14a94ebd MK |
1849 | case (RAMROD_CMD_ID_ETH_TPA_UPDATE): |
1850 | DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid); | |
1851 | drv_cmd = BNX2X_Q_CMD_UPDATE_TPA; | |
1852 | break; | |
1853 | ||
619c5cb6 VZ |
1854 | default: |
1855 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1856 | command, fp->index); | |
1857 | return; | |
523224a3 | 1858 | } |
3196a88a | 1859 | |
619c5cb6 VZ |
1860 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1861 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1862 | /* q_obj->complete_cmd() failure means that this was | |
1863 | * an unexpected completion. | |
1864 | * | |
1865 | * In this case we don't want to increase the bp->spq_left | |
1866 | * because apparently we haven't sent this command the first | |
1867 | * place. | |
1868 | */ | |
1869 | #ifdef BNX2X_STOP_ON_ERROR | |
1870 | bnx2x_panic(); | |
1871 | #else | |
1872 | return; | |
1873 | #endif | |
1874 | ||
4e857c58 | 1875 | smp_mb__before_atomic(); |
6e30dd4e | 1876 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 | 1877 | /* push the change in bp->spq_left and towards the memory */ |
4e857c58 | 1878 | smp_mb__after_atomic(); |
49d66772 | 1879 | |
d6cae238 VZ |
1880 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1881 | ||
a3348722 BW |
1882 | if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && |
1883 | (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { | |
1884 | /* if Q update ramrod is completed for last Q in AFEX vif set | |
1885 | * flow, then ACK MCP at the end | |
1886 | * | |
1887 | * mark pending ACK to MCP bit. | |
1888 | * prevent case that both bits are cleared. | |
1889 | * At the end of load/unload driver checks that | |
2de67439 | 1890 | * sp_state is cleared, and this order prevents |
a3348722 BW |
1891 | * races |
1892 | */ | |
4e857c58 | 1893 | smp_mb__before_atomic(); |
a3348722 BW |
1894 | set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); |
1895 | wmb(); | |
1896 | clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
4e857c58 | 1897 | smp_mb__after_atomic(); |
a3348722 | 1898 | |
fd1fc79d AE |
1899 | /* schedule the sp task as mcp ack is required */ |
1900 | bnx2x_schedule_sp_task(bp); | |
a3348722 BW |
1901 | } |
1902 | ||
523224a3 | 1903 | return; |
a2fbb9ea ET |
1904 | } |
1905 | ||
9f6c9258 | 1906 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1907 | { |
555f6c78 | 1908 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1909 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1910 | u16 mask; |
ca00392c | 1911 | int i; |
6383c0b3 | 1912 | u8 cos; |
a2fbb9ea | 1913 | |
34f80b04 | 1914 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1915 | if (unlikely(status == 0)) { |
1916 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1917 | return IRQ_NONE; | |
1918 | } | |
f5372251 | 1919 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1920 | |
3196a88a EG |
1921 | #ifdef BNX2X_STOP_ON_ERROR |
1922 | if (unlikely(bp->panic)) | |
1923 | return IRQ_HANDLED; | |
1924 | #endif | |
1925 | ||
ec6ba945 | 1926 | for_each_eth_queue(bp, i) { |
ca00392c | 1927 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1928 | |
55c11941 | 1929 | mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); |
ca00392c | 1930 | if (status & mask) { |
619c5cb6 | 1931 | /* Handle Rx or Tx according to SB id */ |
6383c0b3 | 1932 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 1933 | prefetch(fp->txdata_ptr[cos]->tx_cons_sb); |
523224a3 | 1934 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
f5fbf115 | 1935 | napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1936 | status &= ~mask; |
1937 | } | |
a2fbb9ea ET |
1938 | } |
1939 | ||
55c11941 MS |
1940 | if (CNIC_SUPPORT(bp)) { |
1941 | mask = 0x2; | |
1942 | if (status & (mask | 0x1)) { | |
1943 | struct cnic_ops *c_ops = NULL; | |
993ac7b5 | 1944 | |
ad9b4359 MC |
1945 | rcu_read_lock(); |
1946 | c_ops = rcu_dereference(bp->cnic_ops); | |
1947 | if (c_ops && (bp->cnic_eth_dev.drv_state & | |
1948 | CNIC_DRV_STATE_HANDLES_IRQ)) | |
1949 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1950 | rcu_read_unlock(); | |
993ac7b5 | 1951 | |
55c11941 MS |
1952 | status &= ~mask; |
1953 | } | |
993ac7b5 | 1954 | } |
a2fbb9ea | 1955 | |
34f80b04 | 1956 | if (unlikely(status & 0x1)) { |
fd1fc79d AE |
1957 | |
1958 | /* schedule sp task to perform default status block work, ack | |
1959 | * attentions and enable interrupts. | |
1960 | */ | |
1961 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
1962 | |
1963 | status &= ~0x1; | |
1964 | if (!status) | |
1965 | return IRQ_HANDLED; | |
1966 | } | |
1967 | ||
cdaa7cb8 VZ |
1968 | if (unlikely(status)) |
1969 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1970 | status); |
a2fbb9ea | 1971 | |
c18487ee | 1972 | return IRQ_HANDLED; |
a2fbb9ea ET |
1973 | } |
1974 | ||
c18487ee YR |
1975 | /* Link */ |
1976 | ||
1977 | /* | |
1978 | * General service functions | |
1979 | */ | |
a2fbb9ea | 1980 | |
9f6c9258 | 1981 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1982 | { |
1983 | u32 lock_status; | |
1984 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1985 | int func = BP_FUNC(bp); |
1986 | u32 hw_lock_control_reg; | |
c18487ee | 1987 | int cnt; |
a2fbb9ea | 1988 | |
c18487ee YR |
1989 | /* Validating that the resource is within range */ |
1990 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1991 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1992 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1993 | return -EINVAL; | |
1994 | } | |
a2fbb9ea | 1995 | |
4a37fb66 YG |
1996 | if (func <= 5) { |
1997 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1998 | } else { | |
1999 | hw_lock_control_reg = | |
2000 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
2001 | } | |
2002 | ||
c18487ee | 2003 | /* Validating that the resource is not already taken */ |
4a37fb66 | 2004 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 2005 | if (lock_status & resource_bit) { |
51c1a580 | 2006 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
c18487ee YR |
2007 | lock_status, resource_bit); |
2008 | return -EEXIST; | |
2009 | } | |
a2fbb9ea | 2010 | |
46230476 EG |
2011 | /* Try for 5 second every 5ms */ |
2012 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 2013 | /* Try to acquire the lock */ |
4a37fb66 YG |
2014 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
2015 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
2016 | if (lock_status & resource_bit) |
2017 | return 0; | |
a2fbb9ea | 2018 | |
639d65b8 | 2019 | usleep_range(5000, 10000); |
a2fbb9ea | 2020 | } |
51c1a580 | 2021 | BNX2X_ERR("Timeout\n"); |
c18487ee YR |
2022 | return -EAGAIN; |
2023 | } | |
a2fbb9ea | 2024 | |
c9ee9206 VZ |
2025 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
2026 | { | |
2027 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
2028 | } | |
2029 | ||
9f6c9258 | 2030 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
2031 | { |
2032 | u32 lock_status; | |
2033 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
2034 | int func = BP_FUNC(bp); |
2035 | u32 hw_lock_control_reg; | |
a2fbb9ea | 2036 | |
c18487ee YR |
2037 | /* Validating that the resource is within range */ |
2038 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 2039 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
2040 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
2041 | return -EINVAL; | |
2042 | } | |
2043 | ||
4a37fb66 YG |
2044 | if (func <= 5) { |
2045 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
2046 | } else { | |
2047 | hw_lock_control_reg = | |
2048 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
2049 | } | |
2050 | ||
c18487ee | 2051 | /* Validating that the resource is currently taken */ |
4a37fb66 | 2052 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 2053 | if (!(lock_status & resource_bit)) { |
6bf07b8e YM |
2054 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n", |
2055 | lock_status, resource_bit); | |
c18487ee | 2056 | return -EFAULT; |
a2fbb9ea ET |
2057 | } |
2058 | ||
9f6c9258 DK |
2059 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
2060 | return 0; | |
c18487ee | 2061 | } |
a2fbb9ea | 2062 | |
4acac6a5 EG |
2063 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
2064 | { | |
2065 | /* The GPIO should be swapped if swap register is set and active */ | |
2066 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2067 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2068 | int gpio_shift = gpio_num + | |
2069 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2070 | u32 gpio_mask = (1 << gpio_shift); | |
2071 | u32 gpio_reg; | |
2072 | int value; | |
2073 | ||
2074 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2075 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2076 | return -EINVAL; | |
2077 | } | |
2078 | ||
2079 | /* read GPIO value */ | |
2080 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2081 | ||
2082 | /* get the requested pin value */ | |
2083 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
2084 | value = 1; | |
2085 | else | |
2086 | value = 0; | |
2087 | ||
4acac6a5 EG |
2088 | return value; |
2089 | } | |
2090 | ||
17de50b7 | 2091 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
2092 | { |
2093 | /* The GPIO should be swapped if swap register is set and active */ | |
2094 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 2095 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
2096 | int gpio_shift = gpio_num + |
2097 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2098 | u32 gpio_mask = (1 << gpio_shift); | |
2099 | u32 gpio_reg; | |
a2fbb9ea | 2100 | |
c18487ee YR |
2101 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
2102 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2103 | return -EINVAL; | |
2104 | } | |
a2fbb9ea | 2105 | |
4a37fb66 | 2106 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
2107 | /* read GPIO and mask except the float bits */ |
2108 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 2109 | |
c18487ee YR |
2110 | switch (mode) { |
2111 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
51c1a580 MS |
2112 | DP(NETIF_MSG_LINK, |
2113 | "Set GPIO %d (shift %d) -> output low\n", | |
c18487ee YR |
2114 | gpio_num, gpio_shift); |
2115 | /* clear FLOAT and set CLR */ | |
2116 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2117 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
2118 | break; | |
a2fbb9ea | 2119 | |
c18487ee | 2120 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
51c1a580 MS |
2121 | DP(NETIF_MSG_LINK, |
2122 | "Set GPIO %d (shift %d) -> output high\n", | |
c18487ee YR |
2123 | gpio_num, gpio_shift); |
2124 | /* clear FLOAT and set SET */ | |
2125 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2126 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
2127 | break; | |
a2fbb9ea | 2128 | |
17de50b7 | 2129 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
51c1a580 MS |
2130 | DP(NETIF_MSG_LINK, |
2131 | "Set GPIO %d (shift %d) -> input\n", | |
c18487ee YR |
2132 | gpio_num, gpio_shift); |
2133 | /* set FLOAT */ | |
2134 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2135 | break; | |
a2fbb9ea | 2136 | |
c18487ee YR |
2137 | default: |
2138 | break; | |
a2fbb9ea ET |
2139 | } |
2140 | ||
c18487ee | 2141 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 2142 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 2143 | |
c18487ee | 2144 | return 0; |
a2fbb9ea ET |
2145 | } |
2146 | ||
0d40f0d4 YR |
2147 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
2148 | { | |
2149 | u32 gpio_reg = 0; | |
2150 | int rc = 0; | |
2151 | ||
2152 | /* Any port swapping should be handled by caller. */ | |
2153 | ||
2154 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2155 | /* read GPIO and mask except the float bits */ | |
2156 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2157 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2158 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2159 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
2160 | ||
2161 | switch (mode) { | |
2162 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
2163 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
2164 | /* set CLR */ | |
2165 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2166 | break; | |
2167 | ||
2168 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
2169 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
2170 | /* set SET */ | |
2171 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
2172 | break; | |
2173 | ||
2174 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
2175 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
2176 | /* set FLOAT */ | |
2177 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2178 | break; | |
2179 | ||
2180 | default: | |
2181 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
2182 | rc = -EINVAL; | |
2183 | break; | |
2184 | } | |
2185 | ||
2186 | if (rc == 0) | |
2187 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
2188 | ||
2189 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2190 | ||
2191 | return rc; | |
2192 | } | |
2193 | ||
4acac6a5 EG |
2194 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
2195 | { | |
2196 | /* The GPIO should be swapped if swap register is set and active */ | |
2197 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2198 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2199 | int gpio_shift = gpio_num + | |
2200 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2201 | u32 gpio_mask = (1 << gpio_shift); | |
2202 | u32 gpio_reg; | |
2203 | ||
2204 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2205 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2206 | return -EINVAL; | |
2207 | } | |
2208 | ||
2209 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2210 | /* read GPIO int */ | |
2211 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
2212 | ||
2213 | switch (mode) { | |
2214 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
51c1a580 MS |
2215 | DP(NETIF_MSG_LINK, |
2216 | "Clear GPIO INT %d (shift %d) -> output low\n", | |
2217 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2218 | /* clear SET and set CLR */ |
2219 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2220 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2221 | break; | |
2222 | ||
2223 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
51c1a580 MS |
2224 | DP(NETIF_MSG_LINK, |
2225 | "Set GPIO INT %d (shift %d) -> output high\n", | |
2226 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2227 | /* clear CLR and set SET */ |
2228 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2229 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2230 | break; | |
2231 | ||
2232 | default: | |
2233 | break; | |
2234 | } | |
2235 | ||
2236 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2237 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2238 | ||
2239 | return 0; | |
2240 | } | |
2241 | ||
d6d99a3f | 2242 | static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) |
a2fbb9ea | 2243 | { |
c18487ee | 2244 | u32 spio_reg; |
a2fbb9ea | 2245 | |
d6d99a3f YM |
2246 | /* Only 2 SPIOs are configurable */ |
2247 | if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { | |
2248 | BNX2X_ERR("Invalid SPIO 0x%x\n", spio); | |
c18487ee | 2249 | return -EINVAL; |
a2fbb9ea ET |
2250 | } |
2251 | ||
4a37fb66 | 2252 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2253 | /* read SPIO and mask except the float bits */ |
d6d99a3f | 2254 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); |
a2fbb9ea | 2255 | |
c18487ee | 2256 | switch (mode) { |
d6d99a3f YM |
2257 | case MISC_SPIO_OUTPUT_LOW: |
2258 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); | |
c18487ee | 2259 | /* clear FLOAT and set CLR */ |
d6d99a3f YM |
2260 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2261 | spio_reg |= (spio << MISC_SPIO_CLR_POS); | |
c18487ee | 2262 | break; |
a2fbb9ea | 2263 | |
d6d99a3f YM |
2264 | case MISC_SPIO_OUTPUT_HIGH: |
2265 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); | |
c18487ee | 2266 | /* clear FLOAT and set SET */ |
d6d99a3f YM |
2267 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2268 | spio_reg |= (spio << MISC_SPIO_SET_POS); | |
c18487ee | 2269 | break; |
a2fbb9ea | 2270 | |
d6d99a3f YM |
2271 | case MISC_SPIO_INPUT_HI_Z: |
2272 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); | |
c18487ee | 2273 | /* set FLOAT */ |
d6d99a3f | 2274 | spio_reg |= (spio << MISC_SPIO_FLOAT_POS); |
c18487ee | 2275 | break; |
a2fbb9ea | 2276 | |
c18487ee YR |
2277 | default: |
2278 | break; | |
a2fbb9ea ET |
2279 | } |
2280 | ||
c18487ee | 2281 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2282 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2283 | |
a2fbb9ea ET |
2284 | return 0; |
2285 | } | |
2286 | ||
9f6c9258 | 2287 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2288 | { |
a22f0788 | 2289 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
1359d73c YM |
2290 | |
2291 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | | |
2292 | ADVERTISED_Pause); | |
ad33ea3a EG |
2293 | switch (bp->link_vars.ieee_fc & |
2294 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2295 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2296 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2297 | ADVERTISED_Pause); |
c18487ee | 2298 | break; |
356e2385 | 2299 | |
c18487ee | 2300 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2301 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2302 | break; |
356e2385 | 2303 | |
c18487ee | 2304 | default: |
c18487ee YR |
2305 | break; |
2306 | } | |
2307 | } | |
f1410647 | 2308 | |
cd1dfce2 | 2309 | static void bnx2x_set_requested_fc(struct bnx2x *bp) |
c18487ee | 2310 | { |
cd1dfce2 YM |
2311 | /* Initialize link parameters structure variables |
2312 | * It is recommended to turn off RX FC for jumbo frames | |
2313 | * for better performance | |
2314 | */ | |
2315 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
2316 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; | |
2317 | else | |
2318 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; | |
2319 | } | |
a2fbb9ea | 2320 | |
9156b30b DK |
2321 | static void bnx2x_init_dropless_fc(struct bnx2x *bp) |
2322 | { | |
2323 | u32 pause_enabled = 0; | |
2324 | ||
2325 | if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { | |
2326 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2327 | pause_enabled = 1; | |
2328 | ||
2329 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
2330 | USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), | |
2331 | pause_enabled); | |
2332 | } | |
2333 | ||
2334 | DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n", | |
2335 | pause_enabled ? "enabled" : "disabled"); | |
2336 | } | |
2337 | ||
cd1dfce2 YM |
2338 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
2339 | { | |
2340 | int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); | |
2341 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
2342 | ||
2343 | if (!BP_NOMCP(bp)) { | |
2344 | bnx2x_set_requested_fc(bp); | |
4a37fb66 | 2345 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2346 | |
a22f0788 | 2347 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2348 | struct link_params *lp = &bp->link_params; |
2349 | lp->loopback_mode = LOOPBACK_XGXS; | |
2350 | /* do PHY loopback at 10G speed, if possible */ | |
2351 | if (lp->req_line_speed[cfx_idx] < SPEED_10000) { | |
2352 | if (lp->speed_cap_mask[cfx_idx] & | |
2353 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2354 | lp->req_line_speed[cfx_idx] = | |
2355 | SPEED_10000; | |
2356 | else | |
2357 | lp->req_line_speed[cfx_idx] = | |
2358 | SPEED_1000; | |
2359 | } | |
a22f0788 | 2360 | } |
b5bf9068 | 2361 | |
8970b2e4 MS |
2362 | if (load_mode == LOAD_LOOPBACK_EXT) { |
2363 | struct link_params *lp = &bp->link_params; | |
2364 | lp->loopback_mode = LOOPBACK_EXT; | |
2365 | } | |
2366 | ||
19680c48 | 2367 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2368 | |
4a37fb66 | 2369 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2370 | |
9156b30b DK |
2371 | bnx2x_init_dropless_fc(bp); |
2372 | ||
3c96c68b EG |
2373 | bnx2x_calc_fc_adv(bp); |
2374 | ||
cd1dfce2 | 2375 | if (bp->link_vars.link_up) { |
b5bf9068 | 2376 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
19680c48 | 2377 | bnx2x_link_report(bp); |
cd1dfce2 YM |
2378 | } |
2379 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2380 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2381 | return rc; |
2382 | } | |
f5372251 | 2383 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2384 | return -EINVAL; |
a2fbb9ea ET |
2385 | } |
2386 | ||
9f6c9258 | 2387 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2388 | { |
19680c48 | 2389 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2390 | bnx2x_acquire_phy_lock(bp); |
19680c48 | 2391 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2392 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2393 | |
9156b30b DK |
2394 | bnx2x_init_dropless_fc(bp); |
2395 | ||
19680c48 EG |
2396 | bnx2x_calc_fc_adv(bp); |
2397 | } else | |
f5372251 | 2398 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2399 | } |
a2fbb9ea | 2400 | |
c18487ee YR |
2401 | static void bnx2x__link_reset(struct bnx2x *bp) |
2402 | { | |
19680c48 | 2403 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2404 | bnx2x_acquire_phy_lock(bp); |
5d07d868 | 2405 | bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2406 | bnx2x_release_phy_lock(bp); |
19680c48 | 2407 | } else |
f5372251 | 2408 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2409 | } |
a2fbb9ea | 2410 | |
5d07d868 YM |
2411 | void bnx2x_force_link_reset(struct bnx2x *bp) |
2412 | { | |
2413 | bnx2x_acquire_phy_lock(bp); | |
2414 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); | |
2415 | bnx2x_release_phy_lock(bp); | |
2416 | } | |
2417 | ||
a22f0788 | 2418 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2419 | { |
2145a920 | 2420 | u8 rc = 0; |
a2fbb9ea | 2421 | |
2145a920 VZ |
2422 | if (!BP_NOMCP(bp)) { |
2423 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2424 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2425 | is_serdes); | |
2145a920 VZ |
2426 | bnx2x_release_phy_lock(bp); |
2427 | } else | |
2428 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2429 | |
c18487ee YR |
2430 | return rc; |
2431 | } | |
a2fbb9ea | 2432 | |
2691d51d EG |
2433 | /* Calculates the sum of vn_min_rates. |
2434 | It's needed for further normalizing of the min_rates. | |
2435 | Returns: | |
2436 | sum of vn_min_rates. | |
2437 | or | |
2438 | 0 - if all the min_rates are 0. | |
16a5fd92 | 2439 | In the later case fairness algorithm should be deactivated. |
2691d51d EG |
2440 | If not all min_rates are zero then those that are zeroes will be set to 1. |
2441 | */ | |
b475d78f YM |
2442 | static void bnx2x_calc_vn_min(struct bnx2x *bp, |
2443 | struct cmng_init_input *input) | |
2691d51d EG |
2444 | { |
2445 | int all_zero = 1; | |
2691d51d EG |
2446 | int vn; |
2447 | ||
3395a033 | 2448 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2449 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2450 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2451 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2452 | ||
2453 | /* Skip hidden vns */ | |
2454 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
b475d78f | 2455 | vn_min_rate = 0; |
2691d51d | 2456 | /* If min rate is zero - set it to 1 */ |
b475d78f | 2457 | else if (!vn_min_rate) |
2691d51d EG |
2458 | vn_min_rate = DEF_MIN_RATE; |
2459 | else | |
2460 | all_zero = 0; | |
2461 | ||
b475d78f | 2462 | input->vnic_min_rate[vn] = vn_min_rate; |
2691d51d EG |
2463 | } |
2464 | ||
30ae438b DK |
2465 | /* if ETS or all min rates are zeros - disable fairness */ |
2466 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
b475d78f | 2467 | input->flags.cmng_enables &= |
30ae438b DK |
2468 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2469 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2470 | } else if (all_zero) { | |
b475d78f | 2471 | input->flags.cmng_enables &= |
b015e3d1 | 2472 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
b475d78f YM |
2473 | DP(NETIF_MSG_IFUP, |
2474 | "All MIN values are zeroes fairness will be disabled\n"); | |
b015e3d1 | 2475 | } else |
b475d78f | 2476 | input->flags.cmng_enables |= |
b015e3d1 | 2477 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2691d51d EG |
2478 | } |
2479 | ||
b475d78f YM |
2480 | static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, |
2481 | struct cmng_init_input *input) | |
34f80b04 | 2482 | { |
b475d78f | 2483 | u16 vn_max_rate; |
f2e0899f | 2484 | u32 vn_cfg = bp->mf_config[vn]; |
34f80b04 | 2485 | |
b475d78f | 2486 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
34f80b04 | 2487 | vn_max_rate = 0; |
b475d78f | 2488 | else { |
faa6fcbb DK |
2489 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2490 | ||
b475d78f | 2491 | if (IS_MF_SI(bp)) { |
faa6fcbb DK |
2492 | /* maxCfg in percents of linkspeed */ |
2493 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
b475d78f | 2494 | } else /* SD modes */ |
faa6fcbb DK |
2495 | /* maxCfg is absolute in 100Mb units */ |
2496 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2497 | } |
f85582f8 | 2498 | |
b475d78f | 2499 | DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); |
34f80b04 | 2500 | |
b475d78f | 2501 | input->vnic_max_rate[vn] = vn_max_rate; |
34f80b04 | 2502 | } |
f85582f8 | 2503 | |
523224a3 DK |
2504 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2505 | { | |
2506 | if (CHIP_REV_IS_SLOW(bp)) | |
2507 | return CMNG_FNS_NONE; | |
fb3bff17 | 2508 | if (IS_MF(bp)) |
523224a3 DK |
2509 | return CMNG_FNS_MINMAX; |
2510 | ||
2511 | return CMNG_FNS_NONE; | |
2512 | } | |
2513 | ||
2ae17f66 | 2514 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2515 | { |
0793f83f | 2516 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2517 | |
2518 | if (BP_NOMCP(bp)) | |
16a5fd92 | 2519 | return; /* what should be the default value in this case */ |
523224a3 | 2520 | |
0793f83f DK |
2521 | /* For 2 port configuration the absolute function number formula |
2522 | * is: | |
2523 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2524 | * | |
2525 | * and there are 4 functions per port | |
2526 | * | |
2527 | * For 4 port configuration it is | |
2528 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2529 | * | |
2530 | * and there are 2 functions per port | |
2531 | */ | |
3395a033 | 2532 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2533 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2534 | ||
2535 | if (func >= E1H_FUNC_MAX) | |
2536 | break; | |
2537 | ||
f2e0899f | 2538 | bp->mf_config[vn] = |
523224a3 DK |
2539 | MF_CFG_RD(bp, func_mf_config[func].config); |
2540 | } | |
a3348722 BW |
2541 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
2542 | DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); | |
2543 | bp->flags |= MF_FUNC_DIS; | |
2544 | } else { | |
2545 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2546 | bp->flags &= ~MF_FUNC_DIS; | |
2547 | } | |
523224a3 DK |
2548 | } |
2549 | ||
2550 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2551 | { | |
b475d78f YM |
2552 | struct cmng_init_input input; |
2553 | memset(&input, 0, sizeof(struct cmng_init_input)); | |
2554 | ||
2555 | input.port_rate = bp->link_vars.line_speed; | |
523224a3 | 2556 | |
568e2426 | 2557 | if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) { |
523224a3 DK |
2558 | int vn; |
2559 | ||
523224a3 DK |
2560 | /* read mf conf from shmem */ |
2561 | if (read_cfg) | |
2562 | bnx2x_read_mf_cfg(bp); | |
2563 | ||
523224a3 | 2564 | /* vn_weight_sum and enable fairness if not 0 */ |
b475d78f | 2565 | bnx2x_calc_vn_min(bp, &input); |
523224a3 DK |
2566 | |
2567 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2568 | if (bp->port.pmf) |
3395a033 | 2569 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
b475d78f | 2570 | bnx2x_calc_vn_max(bp, vn, &input); |
523224a3 DK |
2571 | |
2572 | /* always enable rate shaping and fairness */ | |
b475d78f | 2573 | input.flags.cmng_enables |= |
523224a3 | 2574 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; |
b475d78f YM |
2575 | |
2576 | bnx2x_init_cmng(&input, &bp->cmng); | |
523224a3 DK |
2577 | return; |
2578 | } | |
2579 | ||
2580 | /* rate shaping and fairness are disabled */ | |
2581 | DP(NETIF_MSG_IFUP, | |
2582 | "rate shaping and fairness are disabled\n"); | |
2583 | } | |
34f80b04 | 2584 | |
1191cb83 ED |
2585 | static void storm_memset_cmng(struct bnx2x *bp, |
2586 | struct cmng_init *cmng, | |
2587 | u8 port) | |
2588 | { | |
2589 | int vn; | |
2590 | size_t size = sizeof(struct cmng_struct_per_port); | |
2591 | ||
2592 | u32 addr = BAR_XSTRORM_INTMEM + | |
2593 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
2594 | ||
2595 | __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); | |
2596 | ||
2597 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
2598 | int func = func_by_vn(bp, vn); | |
2599 | ||
2600 | addr = BAR_XSTRORM_INTMEM + | |
2601 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); | |
2602 | size = sizeof(struct rate_shaping_vars_per_vn); | |
2603 | __storm_memset_struct(bp, addr, size, | |
2604 | (u32 *)&cmng->vnic.vnic_max_rate[vn]); | |
2605 | ||
2606 | addr = BAR_XSTRORM_INTMEM + | |
2607 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); | |
2608 | size = sizeof(struct fairness_vars_per_vn); | |
2609 | __storm_memset_struct(bp, addr, size, | |
2610 | (u32 *)&cmng->vnic.vnic_min_rate[vn]); | |
2611 | } | |
2612 | } | |
2613 | ||
568e2426 DK |
2614 | /* init cmng mode in HW according to local configuration */ |
2615 | void bnx2x_set_local_cmng(struct bnx2x *bp) | |
2616 | { | |
2617 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
2618 | ||
2619 | if (cmng_fns != CMNG_FNS_NONE) { | |
2620 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2621 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2622 | } else { | |
2623 | /* rate shaping and fairness are disabled */ | |
2624 | DP(NETIF_MSG_IFUP, | |
2625 | "single function mode without fairness\n"); | |
2626 | } | |
2627 | } | |
2628 | ||
c18487ee YR |
2629 | /* This function is called upon link interrupt */ |
2630 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2631 | { | |
bb2a0f7a YG |
2632 | /* Make sure that we are synced with the current statistics */ |
2633 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2634 | ||
c18487ee | 2635 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2636 | |
9156b30b | 2637 | bnx2x_init_dropless_fc(bp); |
1c06328c | 2638 | |
9156b30b | 2639 | if (bp->link_vars.link_up) { |
1c06328c | 2640 | |
619c5cb6 | 2641 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2642 | struct host_port_stats *pstats; |
2643 | ||
2644 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2645 | /* reset old mac stats */ |
bb2a0f7a YG |
2646 | memset(&(pstats->mac_stx[0]), 0, |
2647 | sizeof(struct mac_stx)); | |
2648 | } | |
f34d28ea | 2649 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2650 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2651 | } | |
2652 | ||
568e2426 DK |
2653 | if (bp->link_vars.link_up && bp->link_vars.line_speed) |
2654 | bnx2x_set_local_cmng(bp); | |
9fdc3e95 | 2655 | |
2ae17f66 VZ |
2656 | __bnx2x_link_report(bp); |
2657 | ||
9fdc3e95 DK |
2658 | if (IS_MF(bp)) |
2659 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2660 | } |
a2fbb9ea | 2661 | |
9f6c9258 | 2662 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2663 | { |
2ae17f66 | 2664 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2665 | return; |
a2fbb9ea | 2666 | |
00253a8c | 2667 | /* read updated dcb configuration */ |
ad5afc89 AE |
2668 | if (IS_PF(bp)) { |
2669 | bnx2x_dcbx_pmf_update(bp); | |
2670 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); | |
2671 | if (bp->link_vars.link_up) | |
2672 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2673 | else | |
2674 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2675 | /* indicate link status */ | |
2676 | bnx2x_link_report(bp); | |
a2fbb9ea | 2677 | |
ad5afc89 AE |
2678 | } else { /* VF */ |
2679 | bp->port.supported[0] |= (SUPPORTED_10baseT_Half | | |
2680 | SUPPORTED_10baseT_Full | | |
2681 | SUPPORTED_100baseT_Half | | |
2682 | SUPPORTED_100baseT_Full | | |
2683 | SUPPORTED_1000baseT_Full | | |
2684 | SUPPORTED_2500baseX_Full | | |
2685 | SUPPORTED_10000baseT_Full | | |
2686 | SUPPORTED_TP | | |
2687 | SUPPORTED_FIBRE | | |
2688 | SUPPORTED_Autoneg | | |
2689 | SUPPORTED_Pause | | |
2690 | SUPPORTED_Asym_Pause); | |
2691 | bp->port.advertising[0] = bp->port.supported[0]; | |
2692 | ||
2693 | bp->link_params.bp = bp; | |
2694 | bp->link_params.port = BP_PORT(bp); | |
2695 | bp->link_params.req_duplex[0] = DUPLEX_FULL; | |
2696 | bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; | |
2697 | bp->link_params.req_line_speed[0] = SPEED_10000; | |
2698 | bp->link_params.speed_cap_mask[0] = 0x7f0000; | |
2699 | bp->link_params.switch_cfg = SWITCH_CFG_10G; | |
2700 | bp->link_vars.mac_type = MAC_TYPE_BMAC; | |
2701 | bp->link_vars.line_speed = SPEED_10000; | |
2702 | bp->link_vars.link_status = | |
2703 | (LINK_STATUS_LINK_UP | | |
2704 | LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); | |
2705 | bp->link_vars.link_up = 1; | |
2706 | bp->link_vars.duplex = DUPLEX_FULL; | |
2707 | bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
2708 | __bnx2x_link_report(bp); | |
6495d15a DK |
2709 | |
2710 | bnx2x_sample_bulletin(bp); | |
2711 | ||
2712 | /* if bulletin board did not have an update for link status | |
2713 | * __bnx2x_link_report will report current status | |
2714 | * but it will NOT duplicate report in case of already reported | |
2715 | * during sampling bulletin board. | |
2716 | */ | |
bb2a0f7a | 2717 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
ad5afc89 | 2718 | } |
a2fbb9ea | 2719 | } |
a2fbb9ea | 2720 | |
a3348722 BW |
2721 | static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, |
2722 | u16 vlan_val, u8 allowed_prio) | |
2723 | { | |
86564c3f | 2724 | struct bnx2x_func_state_params func_params = {NULL}; |
a3348722 BW |
2725 | struct bnx2x_func_afex_update_params *f_update_params = |
2726 | &func_params.params.afex_update; | |
2727 | ||
2728 | func_params.f_obj = &bp->func_obj; | |
2729 | func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; | |
2730 | ||
2731 | /* no need to wait for RAMROD completion, so don't | |
2732 | * set RAMROD_COMP_WAIT flag | |
2733 | */ | |
2734 | ||
2735 | f_update_params->vif_id = vifid; | |
2736 | f_update_params->afex_default_vlan = vlan_val; | |
2737 | f_update_params->allowed_priorities = allowed_prio; | |
2738 | ||
2739 | /* if ramrod can not be sent, response to MCP immediately */ | |
2740 | if (bnx2x_func_state_change(bp, &func_params) < 0) | |
2741 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
2742 | ||
2743 | return 0; | |
2744 | } | |
2745 | ||
2746 | static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, | |
2747 | u16 vif_index, u8 func_bit_map) | |
2748 | { | |
86564c3f | 2749 | struct bnx2x_func_state_params func_params = {NULL}; |
a3348722 BW |
2750 | struct bnx2x_func_afex_viflists_params *update_params = |
2751 | &func_params.params.afex_viflists; | |
2752 | int rc; | |
2753 | u32 drv_msg_code; | |
2754 | ||
2755 | /* validate only LIST_SET and LIST_GET are received from switch */ | |
2756 | if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) | |
2757 | BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", | |
2758 | cmd_type); | |
2759 | ||
2760 | func_params.f_obj = &bp->func_obj; | |
2761 | func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; | |
2762 | ||
2763 | /* set parameters according to cmd_type */ | |
2764 | update_params->afex_vif_list_command = cmd_type; | |
86564c3f | 2765 | update_params->vif_list_index = vif_index; |
a3348722 BW |
2766 | update_params->func_bit_map = |
2767 | (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; | |
2768 | update_params->func_to_clear = 0; | |
2769 | drv_msg_code = | |
2770 | (cmd_type == VIF_LIST_RULE_GET) ? | |
2771 | DRV_MSG_CODE_AFEX_LISTGET_ACK : | |
2772 | DRV_MSG_CODE_AFEX_LISTSET_ACK; | |
2773 | ||
2774 | /* if ramrod can not be sent, respond to MCP immediately for | |
2775 | * SET and GET requests (other are not triggered from MCP) | |
2776 | */ | |
2777 | rc = bnx2x_func_state_change(bp, &func_params); | |
2778 | if (rc < 0) | |
2779 | bnx2x_fw_command(bp, drv_msg_code, 0); | |
2780 | ||
2781 | return 0; | |
2782 | } | |
2783 | ||
2784 | static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) | |
2785 | { | |
2786 | struct afex_stats afex_stats; | |
2787 | u32 func = BP_ABS_FUNC(bp); | |
2788 | u32 mf_config; | |
2789 | u16 vlan_val; | |
2790 | u32 vlan_prio; | |
2791 | u16 vif_id; | |
2792 | u8 allowed_prio; | |
2793 | u8 vlan_mode; | |
2794 | u32 addr_to_write, vifid, addrs, stats_type, i; | |
2795 | ||
2796 | if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { | |
2797 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2798 | DP(BNX2X_MSG_MCP, | |
2799 | "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); | |
2800 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); | |
2801 | } | |
2802 | ||
2803 | if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { | |
2804 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2805 | addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); | |
2806 | DP(BNX2X_MSG_MCP, | |
2807 | "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", | |
2808 | vifid, addrs); | |
2809 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, | |
2810 | addrs); | |
2811 | } | |
2812 | ||
2813 | if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { | |
2814 | addr_to_write = SHMEM2_RD(bp, | |
2815 | afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); | |
2816 | stats_type = SHMEM2_RD(bp, | |
2817 | afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2818 | ||
2819 | DP(BNX2X_MSG_MCP, | |
2820 | "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", | |
2821 | addr_to_write); | |
2822 | ||
2823 | bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); | |
2824 | ||
2825 | /* write response to scratchpad, for MCP */ | |
2826 | for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) | |
2827 | REG_WR(bp, addr_to_write + i*sizeof(u32), | |
2828 | *(((u32 *)(&afex_stats))+i)); | |
2829 | ||
2830 | /* send ack message to MCP */ | |
2831 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); | |
2832 | } | |
2833 | ||
2834 | if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { | |
2835 | mf_config = MF_CFG_RD(bp, func_mf_config[func].config); | |
2836 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2837 | DP(BNX2X_MSG_MCP, | |
2838 | "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", | |
2839 | mf_config); | |
2840 | ||
2841 | /* if VIF_SET is "enabled" */ | |
2842 | if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { | |
2843 | /* set rate limit directly to internal RAM */ | |
2844 | struct cmng_init_input cmng_input; | |
2845 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2846 | size_t size = sizeof(struct rate_shaping_vars_per_vn); | |
2847 | u32 addr = BAR_XSTRORM_INTMEM + | |
2848 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); | |
2849 | ||
2850 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2851 | ||
2852 | bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); | |
2853 | m_rs_vn.vn_counter.rate = | |
2854 | cmng_input.vnic_max_rate[BP_VN(bp)]; | |
2855 | m_rs_vn.vn_counter.quota = | |
2856 | (m_rs_vn.vn_counter.rate * | |
2857 | RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2858 | ||
2859 | __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); | |
2860 | ||
2861 | /* read relevant values from mf_cfg struct in shmem */ | |
2862 | vif_id = | |
2863 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2864 | FUNC_MF_CFG_E1HOV_TAG_MASK) >> | |
2865 | FUNC_MF_CFG_E1HOV_TAG_SHIFT; | |
2866 | vlan_val = | |
2867 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2868 | FUNC_MF_CFG_AFEX_VLAN_MASK) >> | |
2869 | FUNC_MF_CFG_AFEX_VLAN_SHIFT; | |
2870 | vlan_prio = (mf_config & | |
2871 | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> | |
2872 | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; | |
2873 | vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); | |
2874 | vlan_mode = | |
2875 | (MF_CFG_RD(bp, | |
2876 | func_mf_config[func].afex_config) & | |
2877 | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> | |
2878 | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; | |
2879 | allowed_prio = | |
2880 | (MF_CFG_RD(bp, | |
2881 | func_mf_config[func].afex_config) & | |
2882 | FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> | |
2883 | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; | |
2884 | ||
2885 | /* send ramrod to FW, return in case of failure */ | |
2886 | if (bnx2x_afex_func_update(bp, vif_id, vlan_val, | |
2887 | allowed_prio)) | |
2888 | return; | |
2889 | ||
2890 | bp->afex_def_vlan_tag = vlan_val; | |
2891 | bp->afex_vlan_mode = vlan_mode; | |
2892 | } else { | |
2893 | /* notify link down because BP->flags is disabled */ | |
2894 | bnx2x_link_report(bp); | |
2895 | ||
2896 | /* send INVALID VIF ramrod to FW */ | |
2897 | bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); | |
2898 | ||
2899 | /* Reset the default afex VLAN */ | |
2900 | bp->afex_def_vlan_tag = -1; | |
2901 | } | |
2902 | } | |
2903 | } | |
2904 | ||
7609647e YM |
2905 | static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp) |
2906 | { | |
2907 | struct bnx2x_func_switch_update_params *switch_update_params; | |
2908 | struct bnx2x_func_state_params func_params; | |
2909 | ||
2910 | memset(&func_params, 0, sizeof(struct bnx2x_func_state_params)); | |
2911 | switch_update_params = &func_params.params.switch_update; | |
2912 | func_params.f_obj = &bp->func_obj; | |
2913 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
2914 | ||
2915 | if (IS_MF_UFP(bp)) { | |
2916 | int func = BP_ABS_FUNC(bp); | |
2917 | u32 val; | |
2918 | ||
2919 | /* Re-learn the S-tag from shmem */ | |
2920 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2921 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2922 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
2923 | bp->mf_ov = val; | |
2924 | } else { | |
2925 | BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n"); | |
2926 | goto fail; | |
2927 | } | |
2928 | ||
2929 | /* Configure new S-tag in LLH */ | |
2930 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, | |
2931 | bp->mf_ov); | |
2932 | ||
2933 | /* Send Ramrod to update FW of change */ | |
2934 | __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG, | |
2935 | &switch_update_params->changes); | |
2936 | switch_update_params->vlan = bp->mf_ov; | |
2937 | ||
2938 | if (bnx2x_func_state_change(bp, &func_params) < 0) { | |
2939 | BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n", | |
2940 | bp->mf_ov); | |
2941 | goto fail; | |
2942 | } | |
2943 | ||
2944 | DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov); | |
2945 | ||
2946 | bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0); | |
2947 | ||
2948 | return; | |
2949 | } | |
2950 | ||
2951 | /* not supported by SW yet */ | |
2952 | fail: | |
2953 | bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0); | |
2954 | } | |
2955 | ||
34f80b04 EG |
2956 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2957 | { | |
2958 | int port = BP_PORT(bp); | |
2959 | u32 val; | |
2960 | ||
2961 | bp->port.pmf = 1; | |
51c1a580 | 2962 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
34f80b04 | 2963 | |
3deb8167 YR |
2964 | /* |
2965 | * We need the mb() to ensure the ordering between the writing to | |
2966 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2967 | */ | |
2968 | smp_mb(); | |
2969 | ||
2970 | /* queue a periodic task */ | |
2971 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2972 | ||
ef01854e DK |
2973 | bnx2x_dcbx_pmf_update(bp); |
2974 | ||
34f80b04 | 2975 | /* enable nig attention */ |
3395a033 | 2976 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
2977 | if (bp->common.int_block == INT_BLOCK_HC) { |
2978 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2979 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2980 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2981 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2982 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2983 | } | |
bb2a0f7a YG |
2984 | |
2985 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2986 | } |
2987 | ||
c18487ee | 2988 | /* end of Link */ |
a2fbb9ea ET |
2989 | |
2990 | /* slow path */ | |
2991 | ||
2992 | /* | |
2993 | * General service functions | |
2994 | */ | |
2995 | ||
2691d51d | 2996 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 2997 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 2998 | { |
f2e0899f | 2999 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 3000 | u32 seq; |
2691d51d EG |
3001 | u32 rc = 0; |
3002 | u32 cnt = 1; | |
3003 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
3004 | ||
c4ff7cbf | 3005 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 3006 | seq = ++bp->fw_seq; |
f2e0899f DK |
3007 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
3008 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
3009 | ||
754a2f52 DK |
3010 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
3011 | (command | seq), param); | |
2691d51d EG |
3012 | |
3013 | do { | |
3014 | /* let the FW do it's magic ... */ | |
3015 | msleep(delay); | |
3016 | ||
f2e0899f | 3017 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 3018 | |
c4ff7cbf EG |
3019 | /* Give the FW up to 5 second (500*10ms) */ |
3020 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
3021 | |
3022 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
3023 | cnt*delay, rc, seq); | |
3024 | ||
3025 | /* is this a reply to our command? */ | |
3026 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
3027 | rc &= FW_MSG_CODE_MASK; | |
3028 | else { | |
3029 | /* FW BUG! */ | |
3030 | BNX2X_ERR("FW failed to respond!\n"); | |
3031 | bnx2x_fw_dump(bp); | |
3032 | rc = 0; | |
3033 | } | |
c4ff7cbf | 3034 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
3035 | |
3036 | return rc; | |
3037 | } | |
3038 | ||
1191cb83 ED |
3039 | static void storm_memset_func_cfg(struct bnx2x *bp, |
3040 | struct tstorm_eth_function_common_config *tcfg, | |
3041 | u16 abs_fid) | |
3042 | { | |
3043 | size_t size = sizeof(struct tstorm_eth_function_common_config); | |
3044 | ||
3045 | u32 addr = BAR_TSTRORM_INTMEM + | |
3046 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); | |
3047 | ||
3048 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); | |
3049 | } | |
3050 | ||
619c5cb6 VZ |
3051 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
3052 | { | |
3053 | if (CHIP_IS_E1x(bp)) { | |
3054 | struct tstorm_eth_function_common_config tcfg = {0}; | |
3055 | ||
3056 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
3057 | } | |
3058 | ||
3059 | /* Enable the function in the FW */ | |
3060 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
3061 | storm_memset_func_en(bp, p->func_id, 1); | |
3062 | ||
3063 | /* spq */ | |
3064 | if (p->func_flgs & FUNC_FLG_SPQ) { | |
3065 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); | |
3066 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
3067 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
3068 | } | |
3069 | } | |
3070 | ||
6383c0b3 | 3071 | /** |
16a5fd92 | 3072 | * bnx2x_get_common_flags - Return common flags |
6383c0b3 AE |
3073 | * |
3074 | * @bp device handle | |
3075 | * @fp queue handle | |
3076 | * @zero_stats TRUE if statistics zeroing is needed | |
3077 | * | |
3078 | * Return the flags that are common for the Tx-only and not normal connections. | |
3079 | */ | |
1191cb83 ED |
3080 | static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, |
3081 | struct bnx2x_fastpath *fp, | |
3082 | bool zero_stats) | |
28912902 | 3083 | { |
619c5cb6 VZ |
3084 | unsigned long flags = 0; |
3085 | ||
3086 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
3087 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 3088 | |
6383c0b3 | 3089 | /* tx only connections collect statistics (on the same index as the |
91226790 DK |
3090 | * parent connection). The statistics are zeroed when the parent |
3091 | * connection is initialized. | |
6383c0b3 | 3092 | */ |
50f0a562 BW |
3093 | |
3094 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
3095 | if (zero_stats) | |
3096 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
3097 | ||
c14db202 YM |
3098 | if (bp->flags & TX_SWITCHING) |
3099 | __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags); | |
3100 | ||
91226790 | 3101 | __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags); |
e287a75c | 3102 | __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags); |
6383c0b3 | 3103 | |
823e1d90 YM |
3104 | #ifdef BNX2X_STOP_ON_ERROR |
3105 | __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); | |
3106 | #endif | |
3107 | ||
6383c0b3 AE |
3108 | return flags; |
3109 | } | |
3110 | ||
1191cb83 ED |
3111 | static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, |
3112 | struct bnx2x_fastpath *fp, | |
3113 | bool leading) | |
6383c0b3 AE |
3114 | { |
3115 | unsigned long flags = 0; | |
3116 | ||
619c5cb6 VZ |
3117 | /* calculate other queue flags */ |
3118 | if (IS_MF_SD(bp)) | |
3119 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 3120 | |
a3348722 | 3121 | if (IS_FCOE_FP(fp)) { |
619c5cb6 | 3122 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); |
a3348722 BW |
3123 | /* For FCoE - force usage of default priority (for afex) */ |
3124 | __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); | |
3125 | } | |
523224a3 | 3126 | |
7e6b4d44 | 3127 | if (fp->mode != TPA_MODE_DISABLED) { |
619c5cb6 | 3128 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e | 3129 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
621b4d66 DK |
3130 | if (fp->mode == TPA_MODE_GRO) |
3131 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); | |
f5219d8e | 3132 | } |
619c5cb6 | 3133 | |
619c5cb6 VZ |
3134 | if (leading) { |
3135 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
3136 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
3137 | } | |
523224a3 | 3138 | |
619c5cb6 VZ |
3139 | /* Always set HW VLAN stripping */ |
3140 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 3141 | |
a3348722 BW |
3142 | /* configure silent vlan removal */ |
3143 | if (IS_MF_AFEX(bp)) | |
3144 | __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); | |
3145 | ||
6383c0b3 | 3146 | return flags | bnx2x_get_common_flags(bp, fp, true); |
523224a3 DK |
3147 | } |
3148 | ||
619c5cb6 | 3149 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
3150 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
3151 | u8 cos) | |
619c5cb6 VZ |
3152 | { |
3153 | gen_init->stat_id = bnx2x_stats_id(fp); | |
3154 | gen_init->spcl_id = fp->cl_id; | |
3155 | ||
3156 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
3157 | if (IS_FCOE_FP(fp)) | |
3158 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
3159 | else | |
3160 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
3161 | |
3162 | gen_init->cos = cos; | |
02dc4025 YM |
3163 | |
3164 | gen_init->fp_hsi = ETH_FP_HSI_VERSION; | |
619c5cb6 VZ |
3165 | } |
3166 | ||
3167 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 3168 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 3169 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 3170 | { |
619c5cb6 | 3171 | u8 max_sge = 0; |
523224a3 DK |
3172 | u16 sge_sz = 0; |
3173 | u16 tpa_agg_size = 0; | |
3174 | ||
7e6b4d44 | 3175 | if (fp->mode != TPA_MODE_DISABLED) { |
dfacf138 DK |
3176 | pause->sge_th_lo = SGE_TH_LO(bp); |
3177 | pause->sge_th_hi = SGE_TH_HI(bp); | |
3178 | ||
3179 | /* validate SGE ring has enough to cross high threshold */ | |
3180 | WARN_ON(bp->dropless_fc && | |
3181 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
3182 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
3183 | ||
924d75ab | 3184 | tpa_agg_size = TPA_AGG_SIZE; |
523224a3 DK |
3185 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> |
3186 | SGE_PAGE_SHIFT; | |
3187 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
3188 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
924d75ab | 3189 | sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); |
523224a3 DK |
3190 | } |
3191 | ||
3192 | /* pause - not for e1 */ | |
3193 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
3194 | pause->bd_th_lo = BD_TH_LO(bp); |
3195 | pause->bd_th_hi = BD_TH_HI(bp); | |
3196 | ||
3197 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
3198 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
3199 | /* | |
3200 | * validate that rings have enough entries to cross | |
3201 | * high thresholds | |
3202 | */ | |
3203 | WARN_ON(bp->dropless_fc && | |
3204 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
3205 | bp->rx_ring_size); | |
3206 | WARN_ON(bp->dropless_fc && | |
3207 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
3208 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 3209 | |
523224a3 DK |
3210 | pause->pri_map = 1; |
3211 | } | |
3212 | ||
3213 | /* rxq setup */ | |
523224a3 DK |
3214 | rxq_init->dscr_map = fp->rx_desc_mapping; |
3215 | rxq_init->sge_map = fp->rx_sge_mapping; | |
3216 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
3217 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 3218 | |
619c5cb6 VZ |
3219 | /* This should be a maximum number of data bytes that may be |
3220 | * placed on the BD (not including paddings). | |
3221 | */ | |
e52fcb24 | 3222 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
3cdeec22 | 3223 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; |
a8c94b91 | 3224 | |
523224a3 | 3225 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
3226 | rxq_init->tpa_agg_sz = tpa_agg_size; |
3227 | rxq_init->sge_buf_sz = sge_sz; | |
3228 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 | 3229 | rxq_init->rss_engine_id = BP_FUNC(bp); |
259afa1f | 3230 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
619c5cb6 VZ |
3231 | |
3232 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
3233 | * | |
2de67439 | 3234 | * For PF Clients it should be the maximum available number. |
619c5cb6 VZ |
3235 | * VF driver(s) may want to define it to a smaller value. |
3236 | */ | |
dfacf138 | 3237 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 3238 | |
523224a3 DK |
3239 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
3240 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
3241 | ||
ec6ba945 VZ |
3242 | if (IS_FCOE_FP(fp)) |
3243 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
3244 | else | |
6383c0b3 | 3245 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
a3348722 BW |
3246 | /* configure silent vlan removal |
3247 | * if multi function mode is afex, then mask default vlan | |
3248 | */ | |
3249 | if (IS_MF_AFEX(bp)) { | |
3250 | rxq_init->silent_removal_value = bp->afex_def_vlan_tag; | |
3251 | rxq_init->silent_removal_mask = VLAN_VID_MASK; | |
3252 | } | |
523224a3 DK |
3253 | } |
3254 | ||
619c5cb6 | 3255 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
3256 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
3257 | u8 cos) | |
523224a3 | 3258 | { |
65565884 | 3259 | txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; |
6383c0b3 | 3260 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; |
523224a3 DK |
3261 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
3262 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 3263 | |
619c5cb6 | 3264 | /* |
16a5fd92 | 3265 | * set the tss leading client id for TX classification == |
619c5cb6 VZ |
3266 | * leading RSS client id |
3267 | */ | |
3268 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
3269 | ||
ec6ba945 VZ |
3270 | if (IS_FCOE_FP(fp)) { |
3271 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
3272 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
3273 | } | |
523224a3 DK |
3274 | } |
3275 | ||
8d96286a | 3276 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
3277 | { |
3278 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 DK |
3279 | struct event_ring_data eq_data = { {0} }; |
3280 | u16 flags; | |
3281 | ||
619c5cb6 | 3282 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
3283 | /* reset IGU PF statistics: MSIX + ATTN */ |
3284 | /* PF */ | |
3285 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3286 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3287 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3288 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3289 | /* ATTN */ | |
3290 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3291 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3292 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
3293 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3294 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3295 | } | |
3296 | ||
523224a3 DK |
3297 | /* function setup flags */ |
3298 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | |
3299 | ||
619c5cb6 VZ |
3300 | /* This flag is relevant for E1x only. |
3301 | * E2 doesn't have a TPA configuration in a function level. | |
523224a3 | 3302 | */ |
f8dcb5e3 | 3303 | flags |= (bp->dev->features & NETIF_F_LRO) ? FUNC_FLG_TPA : 0; |
523224a3 DK |
3304 | |
3305 | func_init.func_flgs = flags; | |
3306 | func_init.pf_id = BP_FUNC(bp); | |
3307 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
3308 | func_init.spq_map = bp->spq_mapping; |
3309 | func_init.spq_prod = bp->spq_prod_idx; | |
3310 | ||
3311 | bnx2x_func_init(bp, &func_init); | |
3312 | ||
3313 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
3314 | ||
3315 | /* | |
619c5cb6 VZ |
3316 | * Congestion management values depend on the link rate |
3317 | * There is no active link so initial link rate is set to 10 Gbps. | |
3318 | * When the link comes up The congestion management values are | |
3319 | * re-calculated according to the actual link rate. | |
3320 | */ | |
523224a3 DK |
3321 | bp->link_vars.line_speed = SPEED_10000; |
3322 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
3323 | ||
3324 | /* Only the PMF sets the HW */ | |
3325 | if (bp->port.pmf) | |
3326 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3327 | ||
86564c3f | 3328 | /* init Event Queue - PCI bus guarantees correct endianity*/ |
523224a3 DK |
3329 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); |
3330 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
3331 | eq_data.producer = bp->eq_prod; | |
3332 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
3333 | eq_data.sb_id = DEF_SB_ID; | |
3334 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
3335 | } | |
3336 | ||
523224a3 DK |
3337 | static void bnx2x_e1h_disable(struct bnx2x *bp) |
3338 | { | |
3339 | int port = BP_PORT(bp); | |
3340 | ||
619c5cb6 | 3341 | bnx2x_tx_disable(bp); |
523224a3 DK |
3342 | |
3343 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
3344 | } |
3345 | ||
3346 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
3347 | { | |
3348 | int port = BP_PORT(bp); | |
3349 | ||
7609647e YM |
3350 | if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) |
3351 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); | |
523224a3 | 3352 | |
16a5fd92 | 3353 | /* Tx queue should be only re-enabled */ |
523224a3 DK |
3354 | netif_tx_wake_all_queues(bp->dev); |
3355 | ||
3356 | /* | |
3357 | * Should not call netif_carrier_on since it will be called if the link | |
3358 | * is up when checking for link state | |
3359 | */ | |
3360 | } | |
3361 | ||
1d187b34 BW |
3362 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
3363 | ||
3364 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) | |
3365 | { | |
3366 | struct eth_stats_info *ether_stat = | |
3367 | &bp->slowpath->drv_info_to_mcp.ether_stat; | |
3ec9f9ca AE |
3368 | struct bnx2x_vlan_mac_obj *mac_obj = |
3369 | &bp->sp_objs->mac_obj; | |
3370 | int i; | |
1d187b34 | 3371 | |
786fdf0b DC |
3372 | strlcpy(ether_stat->version, DRV_MODULE_VERSION, |
3373 | ETH_STAT_INFO_VERSION_LEN); | |
1d187b34 | 3374 | |
3ec9f9ca AE |
3375 | /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the |
3376 | * mac_local field in ether_stat struct. The base address is offset by 2 | |
3377 | * bytes to account for the field being 8 bytes but a mac address is | |
3378 | * only 6 bytes. Likewise, the stride for the get_n_elements function is | |
3379 | * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes | |
3380 | * allocated by the ether_stat struct, so the macs will land in their | |
3381 | * proper positions. | |
3382 | */ | |
3383 | for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) | |
3384 | memset(ether_stat->mac_local + i, 0, | |
3385 | sizeof(ether_stat->mac_local[0])); | |
3386 | mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, | |
3387 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | |
3388 | ether_stat->mac_local + MAC_PAD, MAC_PAD, | |
3389 | ETH_ALEN); | |
1d187b34 | 3390 | ether_stat->mtu_size = bp->dev->mtu; |
1d187b34 BW |
3391 | if (bp->dev->features & NETIF_F_RXCSUM) |
3392 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | |
3393 | if (bp->dev->features & NETIF_F_TSO) | |
3394 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; | |
3395 | ether_stat->feature_flags |= bp->common.boot_mode; | |
3396 | ||
3397 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; | |
3398 | ||
3399 | ether_stat->txq_size = bp->tx_ring_size; | |
3400 | ether_stat->rxq_size = bp->rx_ring_size; | |
0c757dee | 3401 | |
fcf93a0a | 3402 | #ifdef CONFIG_BNX2X_SRIOV |
0c757dee | 3403 | ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0; |
fcf93a0a | 3404 | #endif |
1d187b34 BW |
3405 | } |
3406 | ||
3407 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) | |
3408 | { | |
3409 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3410 | struct fcoe_stats_info *fcoe_stat = | |
3411 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; | |
3412 | ||
55c11941 MS |
3413 | if (!CNIC_LOADED(bp)) |
3414 | return; | |
3415 | ||
3ec9f9ca | 3416 | memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); |
1d187b34 BW |
3417 | |
3418 | fcoe_stat->qos_priority = | |
3419 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | |
3420 | ||
3421 | /* insert FCoE stats from ramrod response */ | |
3422 | if (!NO_FCOE(bp)) { | |
3423 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = | |
65565884 | 3424 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3425 | tstorm_queue_statistics; |
3426 | ||
3427 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = | |
65565884 | 3428 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3429 | xstorm_queue_statistics; |
3430 | ||
3431 | struct fcoe_statistics_params *fw_fcoe_stat = | |
3432 | &bp->fw_stats_data->fcoe; | |
3433 | ||
86564c3f YM |
3434 | ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, |
3435 | fcoe_stat->rx_bytes_lo, | |
3436 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); | |
1d187b34 | 3437 | |
86564c3f YM |
3438 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3439 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, | |
3440 | fcoe_stat->rx_bytes_lo, | |
3441 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); | |
1d187b34 | 3442 | |
86564c3f YM |
3443 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3444 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, | |
3445 | fcoe_stat->rx_bytes_lo, | |
3446 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); | |
1d187b34 | 3447 | |
86564c3f YM |
3448 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3449 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, | |
3450 | fcoe_stat->rx_bytes_lo, | |
3451 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); | |
1d187b34 | 3452 | |
86564c3f YM |
3453 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3454 | fcoe_stat->rx_frames_lo, | |
3455 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); | |
1d187b34 | 3456 | |
86564c3f YM |
3457 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3458 | fcoe_stat->rx_frames_lo, | |
3459 | fcoe_q_tstorm_stats->rcv_ucast_pkts); | |
1d187b34 | 3460 | |
86564c3f YM |
3461 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3462 | fcoe_stat->rx_frames_lo, | |
3463 | fcoe_q_tstorm_stats->rcv_bcast_pkts); | |
1d187b34 | 3464 | |
86564c3f YM |
3465 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3466 | fcoe_stat->rx_frames_lo, | |
3467 | fcoe_q_tstorm_stats->rcv_mcast_pkts); | |
1d187b34 | 3468 | |
86564c3f YM |
3469 | ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, |
3470 | fcoe_stat->tx_bytes_lo, | |
3471 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); | |
1d187b34 | 3472 | |
86564c3f YM |
3473 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3474 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, | |
3475 | fcoe_stat->tx_bytes_lo, | |
3476 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); | |
1d187b34 | 3477 | |
86564c3f YM |
3478 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3479 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, | |
3480 | fcoe_stat->tx_bytes_lo, | |
3481 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); | |
1d187b34 | 3482 | |
86564c3f YM |
3483 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3484 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, | |
3485 | fcoe_stat->tx_bytes_lo, | |
3486 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); | |
1d187b34 | 3487 | |
86564c3f YM |
3488 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3489 | fcoe_stat->tx_frames_lo, | |
3490 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); | |
1d187b34 | 3491 | |
86564c3f YM |
3492 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3493 | fcoe_stat->tx_frames_lo, | |
3494 | fcoe_q_xstorm_stats->ucast_pkts_sent); | |
1d187b34 | 3495 | |
86564c3f YM |
3496 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3497 | fcoe_stat->tx_frames_lo, | |
3498 | fcoe_q_xstorm_stats->bcast_pkts_sent); | |
1d187b34 | 3499 | |
86564c3f YM |
3500 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3501 | fcoe_stat->tx_frames_lo, | |
3502 | fcoe_q_xstorm_stats->mcast_pkts_sent); | |
1d187b34 BW |
3503 | } |
3504 | ||
1d187b34 BW |
3505 | /* ask L5 driver to add data to the struct */ |
3506 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); | |
1d187b34 BW |
3507 | } |
3508 | ||
3509 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) | |
3510 | { | |
3511 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3512 | struct iscsi_stats_info *iscsi_stat = | |
3513 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; | |
3514 | ||
55c11941 MS |
3515 | if (!CNIC_LOADED(bp)) |
3516 | return; | |
3517 | ||
3ec9f9ca AE |
3518 | memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, |
3519 | ETH_ALEN); | |
1d187b34 BW |
3520 | |
3521 | iscsi_stat->qos_priority = | |
3522 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | |
3523 | ||
1d187b34 BW |
3524 | /* ask L5 driver to add data to the struct */ |
3525 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); | |
1d187b34 BW |
3526 | } |
3527 | ||
0793f83f DK |
3528 | /* called due to MCP event (on pmf): |
3529 | * reread new bandwidth configuration | |
3530 | * configure FW | |
3531 | * notify others function about the change | |
3532 | */ | |
1191cb83 | 3533 | static void bnx2x_config_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3534 | { |
3535 | if (bp->link_vars.link_up) { | |
3536 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
3537 | bnx2x_link_sync_notify(bp); | |
3538 | } | |
3539 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3540 | } | |
3541 | ||
1191cb83 | 3542 | static void bnx2x_set_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3543 | { |
3544 | bnx2x_config_mf_bw(bp); | |
3545 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
3546 | } | |
3547 | ||
c8c60d88 YM |
3548 | static void bnx2x_handle_eee_event(struct bnx2x *bp) |
3549 | { | |
3550 | DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); | |
3551 | bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); | |
3552 | } | |
3553 | ||
42f8277f YM |
3554 | #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20) |
3555 | #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25) | |
3556 | ||
1d187b34 BW |
3557 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
3558 | { | |
3559 | enum drv_info_opcode op_code; | |
3560 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); | |
42f8277f YM |
3561 | bool release = false; |
3562 | int wait; | |
1d187b34 BW |
3563 | |
3564 | /* if drv_info version supported by MFW doesn't match - send NACK */ | |
3565 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { | |
3566 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3567 | return; | |
3568 | } | |
3569 | ||
3570 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> | |
3571 | DRV_INFO_CONTROL_OP_CODE_SHIFT; | |
3572 | ||
42f8277f YM |
3573 | /* Must prevent other flows from accessing drv_info_to_mcp */ |
3574 | mutex_lock(&bp->drv_info_mutex); | |
3575 | ||
1d187b34 BW |
3576 | memset(&bp->slowpath->drv_info_to_mcp, 0, |
3577 | sizeof(union drv_info_to_mcp)); | |
3578 | ||
3579 | switch (op_code) { | |
3580 | case ETH_STATS_OPCODE: | |
3581 | bnx2x_drv_info_ether_stat(bp); | |
3582 | break; | |
3583 | case FCOE_STATS_OPCODE: | |
3584 | bnx2x_drv_info_fcoe_stat(bp); | |
3585 | break; | |
3586 | case ISCSI_STATS_OPCODE: | |
3587 | bnx2x_drv_info_iscsi_stat(bp); | |
3588 | break; | |
3589 | default: | |
3590 | /* if op code isn't supported - send NACK */ | |
3591 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
42f8277f | 3592 | goto out; |
1d187b34 BW |
3593 | } |
3594 | ||
3595 | /* if we got drv_info attn from MFW then these fields are defined in | |
3596 | * shmem2 for sure | |
3597 | */ | |
3598 | SHMEM2_WR(bp, drv_info_host_addr_lo, | |
3599 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3600 | SHMEM2_WR(bp, drv_info_host_addr_hi, | |
3601 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3602 | ||
3603 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); | |
42f8277f YM |
3604 | |
3605 | /* Since possible management wants both this and get_driver_version | |
3606 | * need to wait until management notifies us it finished utilizing | |
3607 | * the buffer. | |
3608 | */ | |
3609 | if (!SHMEM2_HAS(bp, mfw_drv_indication)) { | |
3610 | DP(BNX2X_MSG_MCP, "Management does not support indication\n"); | |
3611 | } else if (!bp->drv_info_mng_owner) { | |
3612 | u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1)); | |
3613 | ||
3614 | for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) { | |
3615 | u32 indication = SHMEM2_RD(bp, mfw_drv_indication); | |
3616 | ||
3617 | /* Management is done; need to clear indication */ | |
3618 | if (indication & bit) { | |
3619 | SHMEM2_WR(bp, mfw_drv_indication, | |
3620 | indication & ~bit); | |
3621 | release = true; | |
3622 | break; | |
3623 | } | |
3624 | ||
3625 | msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH); | |
3626 | } | |
3627 | } | |
3628 | if (!release) { | |
3629 | DP(BNX2X_MSG_MCP, "Management did not release indication\n"); | |
3630 | bp->drv_info_mng_owner = true; | |
3631 | } | |
3632 | ||
3633 | out: | |
3634 | mutex_unlock(&bp->drv_info_mutex); | |
3635 | } | |
3636 | ||
3637 | static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format) | |
3638 | { | |
3639 | u8 vals[4]; | |
3640 | int i = 0; | |
3641 | ||
3642 | if (bnx2x_format) { | |
3643 | i = sscanf(version, "1.%c%hhd.%hhd.%hhd", | |
3644 | &vals[0], &vals[1], &vals[2], &vals[3]); | |
3645 | if (i > 0) | |
3646 | vals[0] -= '0'; | |
3647 | } else { | |
3648 | i = sscanf(version, "%hhd.%hhd.%hhd.%hhd", | |
3649 | &vals[0], &vals[1], &vals[2], &vals[3]); | |
3650 | } | |
3651 | ||
3652 | while (i < 4) | |
3653 | vals[i++] = 0; | |
3654 | ||
3655 | return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3]; | |
3656 | } | |
3657 | ||
3658 | void bnx2x_update_mng_version(struct bnx2x *bp) | |
3659 | { | |
3660 | u32 iscsiver = DRV_VER_NOT_LOADED; | |
3661 | u32 fcoever = DRV_VER_NOT_LOADED; | |
3662 | u32 ethver = DRV_VER_NOT_LOADED; | |
3663 | int idx = BP_FW_MB_IDX(bp); | |
3664 | u8 *version; | |
3665 | ||
3666 | if (!SHMEM2_HAS(bp, func_os_drv_ver)) | |
3667 | return; | |
3668 | ||
3669 | mutex_lock(&bp->drv_info_mutex); | |
3670 | /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */ | |
3671 | if (bp->drv_info_mng_owner) | |
3672 | goto out; | |
3673 | ||
3674 | if (bp->state != BNX2X_STATE_OPEN) | |
3675 | goto out; | |
3676 | ||
3677 | /* Parse ethernet driver version */ | |
3678 | ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); | |
3679 | if (!CNIC_LOADED(bp)) | |
3680 | goto out; | |
3681 | ||
3682 | /* Try getting storage driver version via cnic */ | |
3683 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3684 | sizeof(union drv_info_to_mcp)); | |
3685 | bnx2x_drv_info_iscsi_stat(bp); | |
3686 | version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version; | |
3687 | iscsiver = bnx2x_update_mng_version_utility(version, false); | |
3688 | ||
3689 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3690 | sizeof(union drv_info_to_mcp)); | |
3691 | bnx2x_drv_info_fcoe_stat(bp); | |
3692 | version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version; | |
3693 | fcoever = bnx2x_update_mng_version_utility(version, false); | |
3694 | ||
3695 | out: | |
3696 | SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver); | |
3697 | SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver); | |
3698 | SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever); | |
3699 | ||
3700 | mutex_unlock(&bp->drv_info_mutex); | |
3701 | ||
3702 | DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n", | |
3703 | ethver, iscsiver, fcoever); | |
1d187b34 BW |
3704 | } |
3705 | ||
7609647e | 3706 | static void bnx2x_oem_event(struct bnx2x *bp, u32 event) |
523224a3 | 3707 | { |
7609647e YM |
3708 | u32 cmd_ok, cmd_fail; |
3709 | ||
3710 | /* sanity */ | |
3711 | if (event & DRV_STATUS_DCC_EVENT_MASK && | |
3712 | event & DRV_STATUS_OEM_EVENT_MASK) { | |
3713 | BNX2X_ERR("Received simultaneous events %08x\n", event); | |
3714 | return; | |
3715 | } | |
523224a3 | 3716 | |
7609647e YM |
3717 | if (event & DRV_STATUS_DCC_EVENT_MASK) { |
3718 | cmd_fail = DRV_MSG_CODE_DCC_FAILURE; | |
3719 | cmd_ok = DRV_MSG_CODE_DCC_OK; | |
3720 | } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ { | |
3721 | cmd_fail = DRV_MSG_CODE_OEM_FAILURE; | |
3722 | cmd_ok = DRV_MSG_CODE_OEM_OK; | |
3723 | } | |
523224a3 | 3724 | |
7609647e YM |
3725 | DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event); |
3726 | ||
3727 | if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF | | |
3728 | DRV_STATUS_OEM_DISABLE_ENABLE_PF)) { | |
3729 | /* This is the only place besides the function initialization | |
523224a3 DK |
3730 | * where the bp->flags can change so it is done without any |
3731 | * locks | |
3732 | */ | |
f2e0899f | 3733 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
51c1a580 | 3734 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
523224a3 DK |
3735 | bp->flags |= MF_FUNC_DIS; |
3736 | ||
3737 | bnx2x_e1h_disable(bp); | |
3738 | } else { | |
51c1a580 | 3739 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
523224a3 DK |
3740 | bp->flags &= ~MF_FUNC_DIS; |
3741 | ||
3742 | bnx2x_e1h_enable(bp); | |
3743 | } | |
7609647e YM |
3744 | event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF | |
3745 | DRV_STATUS_OEM_DISABLE_ENABLE_PF); | |
523224a3 | 3746 | } |
7609647e YM |
3747 | |
3748 | if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | | |
3749 | DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) { | |
0793f83f | 3750 | bnx2x_config_mf_bw(bp); |
7609647e YM |
3751 | event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | |
3752 | DRV_STATUS_OEM_BANDWIDTH_ALLOCATION); | |
523224a3 DK |
3753 | } |
3754 | ||
3755 | /* Report results to MCP */ | |
7609647e YM |
3756 | if (event) |
3757 | bnx2x_fw_command(bp, cmd_fail, 0); | |
523224a3 | 3758 | else |
7609647e | 3759 | bnx2x_fw_command(bp, cmd_ok, 0); |
523224a3 DK |
3760 | } |
3761 | ||
3762 | /* must be called under the spq lock */ | |
1191cb83 | 3763 | static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) |
523224a3 DK |
3764 | { |
3765 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3766 | ||
3767 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3768 | bp->spq_prod_bd = bp->spq; | |
3769 | bp->spq_prod_idx = 0; | |
51c1a580 | 3770 | DP(BNX2X_MSG_SP, "end of spq\n"); |
523224a3 DK |
3771 | } else { |
3772 | bp->spq_prod_bd++; | |
3773 | bp->spq_prod_idx++; | |
3774 | } | |
3775 | return next_spe; | |
3776 | } | |
3777 | ||
3778 | /* must be called under the spq lock */ | |
1191cb83 | 3779 | static void bnx2x_sp_prod_update(struct bnx2x *bp) |
28912902 MC |
3780 | { |
3781 | int func = BP_FUNC(bp); | |
3782 | ||
53e51e2f VZ |
3783 | /* |
3784 | * Make sure that BD data is updated before writing the producer: | |
3785 | * BD data is written to the memory, the producer is read from the | |
3786 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3787 | */ | |
3788 | mb(); | |
28912902 | 3789 | |
523224a3 | 3790 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3791 | bp->spq_prod_idx); |
28912902 MC |
3792 | mmiowb(); |
3793 | } | |
3794 | ||
619c5cb6 VZ |
3795 | /** |
3796 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3797 | * | |
3798 | * @cmd: command to check | |
3799 | * @cmd_type: command type | |
3800 | */ | |
1191cb83 | 3801 | static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) |
619c5cb6 VZ |
3802 | { |
3803 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3804 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3805 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3806 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3807 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3808 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3809 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3810 | return true; | |
3811 | else | |
3812 | return false; | |
619c5cb6 VZ |
3813 | } |
3814 | ||
619c5cb6 VZ |
3815 | /** |
3816 | * bnx2x_sp_post - place a single command on an SP ring | |
3817 | * | |
3818 | * @bp: driver handle | |
3819 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3820 | * @cid: SW CID the command is related to | |
3821 | * @data_hi: command private data address (high 32 bits) | |
3822 | * @data_lo: command private data address (low 32 bits) | |
3823 | * @cmd_type: command type (e.g. NONE, ETH) | |
3824 | * | |
3825 | * SP data is handled as if it's always an address pair, thus data fields are | |
3826 | * not swapped to little endian in upper functions. Instead this function swaps | |
3827 | * data as if it's two u32 fields. | |
3828 | */ | |
9f6c9258 | 3829 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3830 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3831 | { |
28912902 | 3832 | struct eth_spe *spe; |
523224a3 | 3833 | u16 type; |
619c5cb6 | 3834 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3835 | |
a2fbb9ea | 3836 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
3837 | if (unlikely(bp->panic)) { |
3838 | BNX2X_ERR("Can't post SP when there is panic\n"); | |
a2fbb9ea | 3839 | return -EIO; |
51c1a580 | 3840 | } |
a2fbb9ea ET |
3841 | #endif |
3842 | ||
34f80b04 | 3843 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3844 | |
6e30dd4e VZ |
3845 | if (common) { |
3846 | if (!atomic_read(&bp->eq_spq_left)) { | |
3847 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3848 | spin_unlock_bh(&bp->spq_lock); | |
3849 | bnx2x_panic(); | |
3850 | return -EBUSY; | |
3851 | } | |
3852 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3853 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3854 | spin_unlock_bh(&bp->spq_lock); | |
3855 | bnx2x_panic(); | |
3856 | return -EBUSY; | |
a2fbb9ea | 3857 | } |
f1410647 | 3858 | |
28912902 MC |
3859 | spe = bnx2x_sp_get_next(bp); |
3860 | ||
a2fbb9ea | 3861 | /* CID needs port number to be encoded int it */ |
28912902 | 3862 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3863 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3864 | HW_CID(bp, cid)); | |
523224a3 | 3865 | |
14a94ebd MK |
3866 | /* In some cases, type may already contain the func-id |
3867 | * mainly in SRIOV related use cases, so we add it here only | |
3868 | * if it's not already set. | |
3869 | */ | |
3870 | if (!(cmd_type & SPE_HDR_FUNCTION_ID)) { | |
3871 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & | |
3872 | SPE_HDR_CONN_TYPE; | |
3873 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & | |
3874 | SPE_HDR_FUNCTION_ID); | |
3875 | } else { | |
3876 | type = cmd_type; | |
3877 | } | |
a2fbb9ea | 3878 | |
523224a3 DK |
3879 | spe->hdr.type = cpu_to_le16(type); |
3880 | ||
3881 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3882 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3883 | ||
d6cae238 VZ |
3884 | /* |
3885 | * It's ok if the actual decrement is issued towards the memory | |
3886 | * somewhere between the spin_lock and spin_unlock. Thus no | |
16a5fd92 | 3887 | * more explicit memory barrier is needed. |
d6cae238 VZ |
3888 | */ |
3889 | if (common) | |
3890 | atomic_dec(&bp->eq_spq_left); | |
3891 | else | |
3892 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3893 | |
51c1a580 MS |
3894 | DP(BNX2X_MSG_SP, |
3895 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3896 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3897 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3898 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3899 | HW_CID(bp, cid), data_hi, data_lo, type, |
3900 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3901 | |
28912902 | 3902 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3903 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3904 | return 0; |
3905 | } | |
3906 | ||
3907 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3908 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3909 | { |
72fd0718 | 3910 | u32 j, val; |
34f80b04 | 3911 | int rc = 0; |
a2fbb9ea ET |
3912 | |
3913 | might_sleep(); | |
72fd0718 | 3914 | for (j = 0; j < 1000; j++) { |
3cdeec22 YM |
3915 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); |
3916 | val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); | |
3917 | if (val & MCPR_ACCESS_LOCK_LOCK) | |
a2fbb9ea ET |
3918 | break; |
3919 | ||
639d65b8 | 3920 | usleep_range(5000, 10000); |
a2fbb9ea | 3921 | } |
3cdeec22 | 3922 | if (!(val & MCPR_ACCESS_LOCK_LOCK)) { |
19680c48 | 3923 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3924 | rc = -EBUSY; |
3925 | } | |
3926 | ||
3927 | return rc; | |
3928 | } | |
3929 | ||
4a37fb66 YG |
3930 | /* release split MCP access lock register */ |
3931 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3932 | { |
3cdeec22 | 3933 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); |
a2fbb9ea ET |
3934 | } |
3935 | ||
523224a3 DK |
3936 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3937 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3938 | ||
1191cb83 | 3939 | static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
a2fbb9ea | 3940 | { |
523224a3 | 3941 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3942 | u16 rc = 0; |
3943 | ||
3944 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3945 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3946 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3947 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3948 | } |
523224a3 DK |
3949 | |
3950 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3951 | bp->def_idx = def_sb->sp_sb.running_index; | |
3952 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3953 | } |
523224a3 | 3954 | |
16a5fd92 | 3955 | /* Do not reorder: indices reading should complete before handling */ |
523224a3 | 3956 | barrier(); |
a2fbb9ea ET |
3957 | return rc; |
3958 | } | |
3959 | ||
3960 | /* | |
3961 | * slow path service functions | |
3962 | */ | |
3963 | ||
3964 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3965 | { | |
34f80b04 | 3966 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3967 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3968 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3969 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3970 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3971 | u32 aeu_mask; |
87942b46 | 3972 | u32 nig_mask = 0; |
f2e0899f | 3973 | u32 reg_addr; |
a2fbb9ea | 3974 | |
a2fbb9ea ET |
3975 | if (bp->attn_state & asserted) |
3976 | BNX2X_ERR("IGU ERROR\n"); | |
3977 | ||
3fcaf2e5 EG |
3978 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
3979 | aeu_mask = REG_RD(bp, aeu_addr); | |
3980 | ||
a2fbb9ea | 3981 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 3982 | aeu_mask, asserted); |
72fd0718 | 3983 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 3984 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 3985 | |
3fcaf2e5 EG |
3986 | REG_WR(bp, aeu_addr, aeu_mask); |
3987 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 3988 | |
3fcaf2e5 | 3989 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 3990 | bp->attn_state |= asserted; |
3fcaf2e5 | 3991 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
3992 | |
3993 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
3994 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 3995 | |
a5e9a7cf EG |
3996 | bnx2x_acquire_phy_lock(bp); |
3997 | ||
877e9aa4 | 3998 | /* save nig interrupt mask */ |
87942b46 | 3999 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 4000 | |
361c391e YR |
4001 | /* If nig_mask is not set, no need to call the update |
4002 | * function. | |
4003 | */ | |
4004 | if (nig_mask) { | |
4005 | REG_WR(bp, nig_int_mask_addr, 0); | |
4006 | ||
4007 | bnx2x_link_attn(bp); | |
4008 | } | |
a2fbb9ea ET |
4009 | |
4010 | /* handle unicore attn? */ | |
4011 | } | |
4012 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
4013 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
4014 | ||
4015 | if (asserted & GPIO_2_FUNC) | |
4016 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
4017 | ||
4018 | if (asserted & GPIO_3_FUNC) | |
4019 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
4020 | ||
4021 | if (asserted & GPIO_4_FUNC) | |
4022 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
4023 | ||
4024 | if (port == 0) { | |
4025 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
4026 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
4027 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
4028 | } | |
4029 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
4030 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
4031 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
4032 | } | |
4033 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
4034 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
4035 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
4036 | } | |
4037 | } else { | |
4038 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
4039 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
4040 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
4041 | } | |
4042 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
4043 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
4044 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
4045 | } | |
4046 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
4047 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
4048 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
4049 | } | |
4050 | } | |
4051 | ||
4052 | } /* if hardwired */ | |
4053 | ||
f2e0899f DK |
4054 | if (bp->common.int_block == INT_BLOCK_HC) |
4055 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4056 | COMMAND_REG_ATTN_BITS_SET); | |
4057 | else | |
4058 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
4059 | ||
4060 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
4061 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
4062 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
4063 | |
4064 | /* now set back the mask */ | |
a5e9a7cf | 4065 | if (asserted & ATTN_NIG_FOR_FUNC) { |
27c1151c YR |
4066 | /* Verify that IGU ack through BAR was written before restoring |
4067 | * NIG mask. This loop should exit after 2-3 iterations max. | |
4068 | */ | |
4069 | if (bp->common.int_block != INT_BLOCK_HC) { | |
4070 | u32 cnt = 0, igu_acked; | |
4071 | do { | |
4072 | igu_acked = REG_RD(bp, | |
4073 | IGU_REG_ATTENTION_ACK_BITS); | |
4074 | } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && | |
4075 | (++cnt < MAX_IGU_ATTN_ACK_TO)); | |
4076 | if (!igu_acked) | |
4077 | DP(NETIF_MSG_HW, | |
4078 | "Failed to verify IGU ack on time\n"); | |
4079 | barrier(); | |
4080 | } | |
87942b46 | 4081 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
4082 | bnx2x_release_phy_lock(bp); |
4083 | } | |
a2fbb9ea ET |
4084 | } |
4085 | ||
1191cb83 | 4086 | static void bnx2x_fan_failure(struct bnx2x *bp) |
fd4ef40d EG |
4087 | { |
4088 | int port = BP_PORT(bp); | |
b7737c9b | 4089 | u32 ext_phy_config; |
fd4ef40d | 4090 | /* mark the failure */ |
b7737c9b YR |
4091 | ext_phy_config = |
4092 | SHMEM_RD(bp, | |
4093 | dev_info.port_hw_config[port].external_phy_config); | |
4094 | ||
4095 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
4096 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 4097 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 4098 | ext_phy_config); |
fd4ef40d EG |
4099 | |
4100 | /* log the failure */ | |
51c1a580 MS |
4101 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
4102 | "Please contact OEM Support for assistance\n"); | |
8304859a | 4103 | |
16a5fd92 | 4104 | /* Schedule device reset (unload) |
8304859a AE |
4105 | * This is due to some boards consuming sufficient power when driver is |
4106 | * up to overheat if fan fails. | |
4107 | */ | |
230bb0f3 | 4108 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0); |
fd4ef40d | 4109 | } |
ab6ad5a4 | 4110 | |
1191cb83 | 4111 | static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 4112 | { |
34f80b04 | 4113 | int port = BP_PORT(bp); |
877e9aa4 | 4114 | int reg_offset; |
d90d96ba | 4115 | u32 val; |
877e9aa4 | 4116 | |
34f80b04 EG |
4117 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
4118 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 4119 | |
34f80b04 | 4120 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
4121 | |
4122 | val = REG_RD(bp, reg_offset); | |
4123 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
4124 | REG_WR(bp, reg_offset, val); | |
4125 | ||
4126 | BNX2X_ERR("SPIO5 hw attention\n"); | |
4127 | ||
fd4ef40d | 4128 | /* Fan failure attention */ |
d90d96ba | 4129 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 4130 | bnx2x_fan_failure(bp); |
877e9aa4 | 4131 | } |
34f80b04 | 4132 | |
3deb8167 | 4133 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
4134 | bnx2x_acquire_phy_lock(bp); |
4135 | bnx2x_handle_module_detect_int(&bp->link_params); | |
4136 | bnx2x_release_phy_lock(bp); | |
4137 | } | |
4138 | ||
34f80b04 EG |
4139 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
4140 | ||
4141 | val = REG_RD(bp, reg_offset); | |
4142 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
4143 | REG_WR(bp, reg_offset, val); | |
4144 | ||
4145 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 4146 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
4147 | bnx2x_panic(); |
4148 | } | |
877e9aa4 ET |
4149 | } |
4150 | ||
1191cb83 | 4151 | static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
4152 | { |
4153 | u32 val; | |
4154 | ||
0626b899 | 4155 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
4156 | |
4157 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
4158 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
4159 | /* DORQ discard attention */ | |
4160 | if (val & 0x2) | |
4161 | BNX2X_ERR("FATAL error from DORQ\n"); | |
4162 | } | |
34f80b04 EG |
4163 | |
4164 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
4165 | ||
4166 | int port = BP_PORT(bp); | |
4167 | int reg_offset; | |
4168 | ||
4169 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
4170 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
4171 | ||
4172 | val = REG_RD(bp, reg_offset); | |
4173 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
4174 | REG_WR(bp, reg_offset, val); | |
4175 | ||
4176 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 4177 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
4178 | bnx2x_panic(); |
4179 | } | |
877e9aa4 ET |
4180 | } |
4181 | ||
1191cb83 | 4182 | static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
4183 | { |
4184 | u32 val; | |
4185 | ||
4186 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
4187 | ||
4188 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
4189 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
4190 | /* CFC error attention */ | |
4191 | if (val & 0x2) | |
4192 | BNX2X_ERR("FATAL error from CFC\n"); | |
4193 | } | |
4194 | ||
4195 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 4196 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 4197 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
4198 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
4199 | if (val & 0x18000) | |
4200 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
4201 | |
4202 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
4203 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
4204 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
4205 | } | |
877e9aa4 | 4206 | } |
34f80b04 EG |
4207 | |
4208 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
4209 | ||
4210 | int port = BP_PORT(bp); | |
4211 | int reg_offset; | |
4212 | ||
4213 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
4214 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
4215 | ||
4216 | val = REG_RD(bp, reg_offset); | |
4217 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
4218 | REG_WR(bp, reg_offset, val); | |
4219 | ||
4220 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 4221 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
4222 | bnx2x_panic(); |
4223 | } | |
877e9aa4 ET |
4224 | } |
4225 | ||
1191cb83 | 4226 | static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) |
877e9aa4 | 4227 | { |
34f80b04 EG |
4228 | u32 val; |
4229 | ||
877e9aa4 ET |
4230 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
4231 | ||
34f80b04 EG |
4232 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
4233 | int func = BP_FUNC(bp); | |
4234 | ||
4235 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
a3348722 | 4236 | bnx2x_read_mf_cfg(bp); |
f2e0899f DK |
4237 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
4238 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
4239 | val = SHMEM_RD(bp, | |
4240 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
7609647e YM |
4241 | |
4242 | if (val & (DRV_STATUS_DCC_EVENT_MASK | | |
4243 | DRV_STATUS_OEM_EVENT_MASK)) | |
4244 | bnx2x_oem_event(bp, | |
4245 | (val & (DRV_STATUS_DCC_EVENT_MASK | | |
4246 | DRV_STATUS_OEM_EVENT_MASK))); | |
0793f83f DK |
4247 | |
4248 | if (val & DRV_STATUS_SET_MF_BW) | |
4249 | bnx2x_set_mf_bw(bp); | |
4250 | ||
1d187b34 BW |
4251 | if (val & DRV_STATUS_DRV_INFO_REQ) |
4252 | bnx2x_handle_drv_info_req(bp); | |
d16132ce AE |
4253 | |
4254 | if (val & DRV_STATUS_VF_DISABLED) | |
370d4a26 YM |
4255 | bnx2x_schedule_iov_task(bp, |
4256 | BNX2X_IOV_HANDLE_FLR); | |
d16132ce | 4257 | |
2691d51d | 4258 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
4259 | bnx2x_pmf_update(bp); |
4260 | ||
e4901dde | 4261 | if (bp->port.pmf && |
785b9b1a SR |
4262 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
4263 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
4264 | /* start dcbx state machine */ |
4265 | bnx2x_dcbx_set_params(bp, | |
4266 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
a3348722 BW |
4267 | if (val & DRV_STATUS_AFEX_EVENT_MASK) |
4268 | bnx2x_handle_afex_cmd(bp, | |
4269 | val & DRV_STATUS_AFEX_EVENT_MASK); | |
c8c60d88 YM |
4270 | if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) |
4271 | bnx2x_handle_eee_event(bp); | |
7609647e YM |
4272 | |
4273 | if (val & DRV_STATUS_OEM_UPDATE_SVID) | |
4274 | bnx2x_handle_update_svid_cmd(bp); | |
4275 | ||
3deb8167 YR |
4276 | if (bp->link_vars.periodic_flags & |
4277 | PERIODIC_FLAGS_LINK_EVENT) { | |
4278 | /* sync with link */ | |
4279 | bnx2x_acquire_phy_lock(bp); | |
4280 | bp->link_vars.periodic_flags &= | |
4281 | ~PERIODIC_FLAGS_LINK_EVENT; | |
4282 | bnx2x_release_phy_lock(bp); | |
4283 | if (IS_MF(bp)) | |
4284 | bnx2x_link_sync_notify(bp); | |
4285 | bnx2x_link_report(bp); | |
4286 | } | |
4287 | /* Always call it here: bnx2x_link_report() will | |
4288 | * prevent the link indication duplication. | |
4289 | */ | |
4290 | bnx2x__link_status_update(bp); | |
34f80b04 | 4291 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
4292 | |
4293 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 4294 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
4295 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
4296 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
4297 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
4298 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
4299 | bnx2x_panic(); | |
4300 | ||
4301 | } else if (attn & BNX2X_MCP_ASSERT) { | |
4302 | ||
4303 | BNX2X_ERR("MCP assert!\n"); | |
4304 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 4305 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
4306 | |
4307 | } else | |
4308 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
4309 | } | |
4310 | ||
4311 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
4312 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
4313 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
4314 | val = CHIP_IS_E1(bp) ? 0 : |
4315 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
4316 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
4317 | } | |
4318 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
4319 | val = CHIP_IS_E1(bp) ? 0 : |
4320 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
4321 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
4322 | } | |
877e9aa4 | 4323 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
4324 | } |
4325 | } | |
4326 | ||
c9ee9206 VZ |
4327 | /* |
4328 | * Bits map: | |
4329 | * 0-7 - Engine0 load counter. | |
4330 | * 8-15 - Engine1 load counter. | |
4331 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
4332 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
4333 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
4334 | * on the engine | |
4335 | * 19 - Engine1 ONE_IS_LOADED. | |
4336 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
4337 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
4338 | * just the one belonging to its engine). | |
4339 | * | |
4340 | */ | |
4341 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
4342 | ||
4343 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
4344 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
4345 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
4346 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
4347 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
4348 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
4349 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
4350 | ||
4351 | /* | |
4352 | * Set the GLOBAL_RESET bit. | |
4353 | * | |
4354 | * Should be run under rtnl lock | |
4355 | */ | |
4356 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
4357 | { | |
f16da43b AE |
4358 | u32 val; |
4359 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4360 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4361 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
f16da43b | 4362 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 VZ |
4363 | } |
4364 | ||
4365 | /* | |
4366 | * Clear the GLOBAL_RESET bit. | |
4367 | * | |
4368 | * Should be run under rtnl lock | |
4369 | */ | |
1191cb83 | 4370 | static void bnx2x_clear_reset_global(struct bnx2x *bp) |
c9ee9206 | 4371 | { |
f16da43b AE |
4372 | u32 val; |
4373 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4374 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4375 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
f16da43b | 4376 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 | 4377 | } |
f85582f8 | 4378 | |
72fd0718 | 4379 | /* |
c9ee9206 VZ |
4380 | * Checks the GLOBAL_RESET bit. |
4381 | * | |
72fd0718 VZ |
4382 | * should be run under rtnl lock |
4383 | */ | |
1191cb83 | 4384 | static bool bnx2x_reset_is_global(struct bnx2x *bp) |
c9ee9206 | 4385 | { |
3cdeec22 | 4386 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
c9ee9206 VZ |
4387 | |
4388 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
4389 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
4390 | } | |
4391 | ||
4392 | /* | |
4393 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
4394 | * | |
4395 | * Should be run under rtnl lock | |
4396 | */ | |
1191cb83 | 4397 | static void bnx2x_set_reset_done(struct bnx2x *bp) |
72fd0718 | 4398 | { |
f16da43b | 4399 | u32 val; |
c9ee9206 VZ |
4400 | u32 bit = BP_PATH(bp) ? |
4401 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4402 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4403 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4404 | |
4405 | /* Clear the bit */ | |
4406 | val &= ~bit; | |
4407 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4408 | |
4409 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
72fd0718 VZ |
4410 | } |
4411 | ||
4412 | /* | |
c9ee9206 VZ |
4413 | * Set RESET_IN_PROGRESS for the current engine. |
4414 | * | |
72fd0718 VZ |
4415 | * should be run under rtnl lock |
4416 | */ | |
c9ee9206 | 4417 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 4418 | { |
f16da43b | 4419 | u32 val; |
c9ee9206 VZ |
4420 | u32 bit = BP_PATH(bp) ? |
4421 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4422 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4423 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4424 | |
4425 | /* Set the bit */ | |
4426 | val |= bit; | |
4427 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4428 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4429 | } |
4430 | ||
4431 | /* | |
c9ee9206 | 4432 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
4433 | * should be run under rtnl lock |
4434 | */ | |
c9ee9206 | 4435 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 4436 | { |
3cdeec22 | 4437 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
c9ee9206 VZ |
4438 | u32 bit = engine ? |
4439 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
4440 | ||
4441 | /* return false if bit is set */ | |
4442 | return (val & bit) ? false : true; | |
72fd0718 VZ |
4443 | } |
4444 | ||
4445 | /* | |
889b9af3 | 4446 | * set pf load for the current pf. |
c9ee9206 | 4447 | * |
72fd0718 VZ |
4448 | * should be run under rtnl lock |
4449 | */ | |
889b9af3 | 4450 | void bnx2x_set_pf_load(struct bnx2x *bp) |
72fd0718 | 4451 | { |
f16da43b | 4452 | u32 val1, val; |
c9ee9206 VZ |
4453 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4454 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4455 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4456 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4457 | |
f16da43b AE |
4458 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4459 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4460 | ||
51c1a580 | 4461 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4462 | |
c9ee9206 VZ |
4463 | /* get the current counter value */ |
4464 | val1 = (val & mask) >> shift; | |
4465 | ||
889b9af3 AE |
4466 | /* set bit of that PF */ |
4467 | val1 |= (1 << bp->pf_num); | |
c9ee9206 VZ |
4468 | |
4469 | /* clear the old value */ | |
4470 | val &= ~mask; | |
4471 | ||
4472 | /* set the new one */ | |
4473 | val |= ((val1 << shift) & mask); | |
4474 | ||
4475 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4476 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4477 | } |
4478 | ||
c9ee9206 | 4479 | /** |
889b9af3 | 4480 | * bnx2x_clear_pf_load - clear pf load mark |
c9ee9206 VZ |
4481 | * |
4482 | * @bp: driver handle | |
4483 | * | |
4484 | * Should be run under rtnl lock. | |
4485 | * Decrements the load counter for the current engine. Returns | |
889b9af3 | 4486 | * whether other functions are still loaded |
72fd0718 | 4487 | */ |
889b9af3 | 4488 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
72fd0718 | 4489 | { |
f16da43b | 4490 | u32 val1, val; |
c9ee9206 VZ |
4491 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4492 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4493 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4494 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4495 | |
f16da43b AE |
4496 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4497 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
51c1a580 | 4498 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4499 | |
c9ee9206 VZ |
4500 | /* get the current counter value */ |
4501 | val1 = (val & mask) >> shift; | |
4502 | ||
889b9af3 AE |
4503 | /* clear bit of that PF */ |
4504 | val1 &= ~(1 << bp->pf_num); | |
c9ee9206 VZ |
4505 | |
4506 | /* clear the old value */ | |
4507 | val &= ~mask; | |
4508 | ||
4509 | /* set the new one */ | |
4510 | val |= ((val1 << shift) & mask); | |
4511 | ||
4512 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4513 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4514 | return val1 != 0; | |
72fd0718 VZ |
4515 | } |
4516 | ||
4517 | /* | |
889b9af3 | 4518 | * Read the load status for the current engine. |
c9ee9206 | 4519 | * |
72fd0718 VZ |
4520 | * should be run under rtnl lock |
4521 | */ | |
1191cb83 | 4522 | static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
72fd0718 | 4523 | { |
c9ee9206 VZ |
4524 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
4525 | BNX2X_PATH0_LOAD_CNT_MASK); | |
4526 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4527 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
4528 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4529 | ||
51c1a580 | 4530 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
c9ee9206 VZ |
4531 | |
4532 | val = (val & mask) >> shift; | |
4533 | ||
51c1a580 MS |
4534 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
4535 | engine, val); | |
c9ee9206 | 4536 | |
889b9af3 | 4537 | return val != 0; |
72fd0718 VZ |
4538 | } |
4539 | ||
6bf07b8e YM |
4540 | static void _print_parity(struct bnx2x *bp, u32 reg) |
4541 | { | |
4542 | pr_cont(" [0x%08x] ", REG_RD(bp, reg)); | |
4543 | } | |
4544 | ||
1191cb83 | 4545 | static void _print_next_block(int idx, const char *blk) |
72fd0718 | 4546 | { |
f1deab50 | 4547 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
4548 | } |
4549 | ||
4293b9f5 DK |
4550 | static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, |
4551 | int *par_num, bool print) | |
72fd0718 | 4552 | { |
4293b9f5 DK |
4553 | u32 cur_bit; |
4554 | bool res; | |
4555 | int i; | |
4556 | ||
4557 | res = false; | |
4558 | ||
72fd0718 | 4559 | for (i = 0; sig; i++) { |
4293b9f5 | 4560 | cur_bit = (0x1UL << i); |
72fd0718 | 4561 | if (sig & cur_bit) { |
4293b9f5 DK |
4562 | res |= true; /* Each bit is real error! */ |
4563 | ||
4564 | if (print) { | |
4565 | switch (cur_bit) { | |
4566 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
4567 | _print_next_block((*par_num)++, "BRB"); | |
6bf07b8e YM |
4568 | _print_parity(bp, |
4569 | BRB1_REG_BRB1_PRTY_STS); | |
4293b9f5 DK |
4570 | break; |
4571 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
4572 | _print_next_block((*par_num)++, | |
4573 | "PARSER"); | |
6bf07b8e | 4574 | _print_parity(bp, PRS_REG_PRS_PRTY_STS); |
4293b9f5 DK |
4575 | break; |
4576 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
4577 | _print_next_block((*par_num)++, "TSDM"); | |
6bf07b8e YM |
4578 | _print_parity(bp, |
4579 | TSDM_REG_TSDM_PRTY_STS); | |
4293b9f5 DK |
4580 | break; |
4581 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
4582 | _print_next_block((*par_num)++, | |
c9ee9206 | 4583 | "SEARCHER"); |
6bf07b8e | 4584 | _print_parity(bp, SRC_REG_SRC_PRTY_STS); |
4293b9f5 DK |
4585 | break; |
4586 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
4587 | _print_next_block((*par_num)++, "TCM"); | |
4588 | _print_parity(bp, TCM_REG_TCM_PRTY_STS); | |
4589 | break; | |
4590 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
4591 | _print_next_block((*par_num)++, | |
4592 | "TSEMI"); | |
6bf07b8e YM |
4593 | _print_parity(bp, |
4594 | TSEM_REG_TSEM_PRTY_STS_0); | |
4595 | _print_parity(bp, | |
4596 | TSEM_REG_TSEM_PRTY_STS_1); | |
4293b9f5 DK |
4597 | break; |
4598 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
4599 | _print_next_block((*par_num)++, "XPB"); | |
6bf07b8e YM |
4600 | _print_parity(bp, GRCBASE_XPB + |
4601 | PB_REG_PB_PRTY_STS); | |
4293b9f5 | 4602 | break; |
6bf07b8e | 4603 | } |
72fd0718 VZ |
4604 | } |
4605 | ||
4606 | /* Clear the bit */ | |
4607 | sig &= ~cur_bit; | |
4608 | } | |
4609 | } | |
4610 | ||
4293b9f5 | 4611 | return res; |
72fd0718 VZ |
4612 | } |
4613 | ||
4293b9f5 DK |
4614 | static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, |
4615 | int *par_num, bool *global, | |
6bf07b8e | 4616 | bool print) |
72fd0718 | 4617 | { |
4293b9f5 DK |
4618 | u32 cur_bit; |
4619 | bool res; | |
4620 | int i; | |
4621 | ||
4622 | res = false; | |
4623 | ||
72fd0718 | 4624 | for (i = 0; sig; i++) { |
4293b9f5 | 4625 | cur_bit = (0x1UL << i); |
72fd0718 | 4626 | if (sig & cur_bit) { |
4293b9f5 | 4627 | res |= true; /* Each bit is real error! */ |
72fd0718 | 4628 | switch (cur_bit) { |
c9ee9206 | 4629 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
6bf07b8e | 4630 | if (print) { |
4293b9f5 | 4631 | _print_next_block((*par_num)++, "PBF"); |
6bf07b8e YM |
4632 | _print_parity(bp, PBF_REG_PBF_PRTY_STS); |
4633 | } | |
72fd0718 VZ |
4634 | break; |
4635 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
6bf07b8e | 4636 | if (print) { |
4293b9f5 | 4637 | _print_next_block((*par_num)++, "QM"); |
6bf07b8e YM |
4638 | _print_parity(bp, QM_REG_QM_PRTY_STS); |
4639 | } | |
c9ee9206 VZ |
4640 | break; |
4641 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
6bf07b8e | 4642 | if (print) { |
4293b9f5 | 4643 | _print_next_block((*par_num)++, "TM"); |
6bf07b8e YM |
4644 | _print_parity(bp, TM_REG_TM_PRTY_STS); |
4645 | } | |
72fd0718 VZ |
4646 | break; |
4647 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
6bf07b8e | 4648 | if (print) { |
4293b9f5 | 4649 | _print_next_block((*par_num)++, "XSDM"); |
6bf07b8e YM |
4650 | _print_parity(bp, |
4651 | XSDM_REG_XSDM_PRTY_STS); | |
4652 | } | |
c9ee9206 VZ |
4653 | break; |
4654 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
6bf07b8e | 4655 | if (print) { |
4293b9f5 | 4656 | _print_next_block((*par_num)++, "XCM"); |
6bf07b8e YM |
4657 | _print_parity(bp, XCM_REG_XCM_PRTY_STS); |
4658 | } | |
72fd0718 VZ |
4659 | break; |
4660 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
6bf07b8e | 4661 | if (print) { |
4293b9f5 DK |
4662 | _print_next_block((*par_num)++, |
4663 | "XSEMI"); | |
6bf07b8e YM |
4664 | _print_parity(bp, |
4665 | XSEM_REG_XSEM_PRTY_STS_0); | |
4666 | _print_parity(bp, | |
4667 | XSEM_REG_XSEM_PRTY_STS_1); | |
4668 | } | |
72fd0718 VZ |
4669 | break; |
4670 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
6bf07b8e | 4671 | if (print) { |
4293b9f5 | 4672 | _print_next_block((*par_num)++, |
c9ee9206 | 4673 | "DOORBELLQ"); |
6bf07b8e YM |
4674 | _print_parity(bp, |
4675 | DORQ_REG_DORQ_PRTY_STS); | |
4676 | } | |
c9ee9206 VZ |
4677 | break; |
4678 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
6bf07b8e | 4679 | if (print) { |
4293b9f5 | 4680 | _print_next_block((*par_num)++, "NIG"); |
6bf07b8e YM |
4681 | if (CHIP_IS_E1x(bp)) { |
4682 | _print_parity(bp, | |
4683 | NIG_REG_NIG_PRTY_STS); | |
4684 | } else { | |
4685 | _print_parity(bp, | |
4686 | NIG_REG_NIG_PRTY_STS_0); | |
4687 | _print_parity(bp, | |
4688 | NIG_REG_NIG_PRTY_STS_1); | |
4689 | } | |
4690 | } | |
72fd0718 VZ |
4691 | break; |
4692 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 | 4693 | if (print) |
4293b9f5 | 4694 | _print_next_block((*par_num)++, |
c9ee9206 VZ |
4695 | "VAUX PCI CORE"); |
4696 | *global = true; | |
72fd0718 VZ |
4697 | break; |
4698 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
6bf07b8e | 4699 | if (print) { |
4293b9f5 DK |
4700 | _print_next_block((*par_num)++, |
4701 | "DEBUG"); | |
6bf07b8e YM |
4702 | _print_parity(bp, DBG_REG_DBG_PRTY_STS); |
4703 | } | |
72fd0718 VZ |
4704 | break; |
4705 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
6bf07b8e | 4706 | if (print) { |
4293b9f5 | 4707 | _print_next_block((*par_num)++, "USDM"); |
6bf07b8e YM |
4708 | _print_parity(bp, |
4709 | USDM_REG_USDM_PRTY_STS); | |
4710 | } | |
72fd0718 | 4711 | break; |
8736c826 | 4712 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
6bf07b8e | 4713 | if (print) { |
4293b9f5 | 4714 | _print_next_block((*par_num)++, "UCM"); |
6bf07b8e YM |
4715 | _print_parity(bp, UCM_REG_UCM_PRTY_STS); |
4716 | } | |
8736c826 | 4717 | break; |
72fd0718 | 4718 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
6bf07b8e | 4719 | if (print) { |
4293b9f5 DK |
4720 | _print_next_block((*par_num)++, |
4721 | "USEMI"); | |
6bf07b8e YM |
4722 | _print_parity(bp, |
4723 | USEM_REG_USEM_PRTY_STS_0); | |
4724 | _print_parity(bp, | |
4725 | USEM_REG_USEM_PRTY_STS_1); | |
4726 | } | |
72fd0718 VZ |
4727 | break; |
4728 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
6bf07b8e | 4729 | if (print) { |
4293b9f5 | 4730 | _print_next_block((*par_num)++, "UPB"); |
6bf07b8e YM |
4731 | _print_parity(bp, GRCBASE_UPB + |
4732 | PB_REG_PB_PRTY_STS); | |
4733 | } | |
72fd0718 VZ |
4734 | break; |
4735 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
6bf07b8e | 4736 | if (print) { |
4293b9f5 | 4737 | _print_next_block((*par_num)++, "CSDM"); |
6bf07b8e YM |
4738 | _print_parity(bp, |
4739 | CSDM_REG_CSDM_PRTY_STS); | |
4740 | } | |
72fd0718 | 4741 | break; |
8736c826 | 4742 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
6bf07b8e | 4743 | if (print) { |
4293b9f5 | 4744 | _print_next_block((*par_num)++, "CCM"); |
6bf07b8e YM |
4745 | _print_parity(bp, CCM_REG_CCM_PRTY_STS); |
4746 | } | |
8736c826 | 4747 | break; |
72fd0718 VZ |
4748 | } |
4749 | ||
4750 | /* Clear the bit */ | |
4751 | sig &= ~cur_bit; | |
4752 | } | |
4753 | } | |
4754 | ||
4293b9f5 | 4755 | return res; |
72fd0718 VZ |
4756 | } |
4757 | ||
4293b9f5 DK |
4758 | static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, |
4759 | int *par_num, bool print) | |
72fd0718 | 4760 | { |
4293b9f5 DK |
4761 | u32 cur_bit; |
4762 | bool res; | |
4763 | int i; | |
4764 | ||
4765 | res = false; | |
4766 | ||
72fd0718 | 4767 | for (i = 0; sig; i++) { |
4293b9f5 | 4768 | cur_bit = (0x1UL << i); |
72fd0718 | 4769 | if (sig & cur_bit) { |
0c23ad37 | 4770 | res = true; /* Each bit is real error! */ |
4293b9f5 DK |
4771 | if (print) { |
4772 | switch (cur_bit) { | |
4773 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
4774 | _print_next_block((*par_num)++, | |
4775 | "CSEMI"); | |
6bf07b8e YM |
4776 | _print_parity(bp, |
4777 | CSEM_REG_CSEM_PRTY_STS_0); | |
4778 | _print_parity(bp, | |
4779 | CSEM_REG_CSEM_PRTY_STS_1); | |
4293b9f5 DK |
4780 | break; |
4781 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
4782 | _print_next_block((*par_num)++, "PXP"); | |
6bf07b8e YM |
4783 | _print_parity(bp, PXP_REG_PXP_PRTY_STS); |
4784 | _print_parity(bp, | |
4785 | PXP2_REG_PXP2_PRTY_STS_0); | |
4786 | _print_parity(bp, | |
4787 | PXP2_REG_PXP2_PRTY_STS_1); | |
4293b9f5 DK |
4788 | break; |
4789 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
4790 | _print_next_block((*par_num)++, | |
4791 | "PXPPCICLOCKCLIENT"); | |
4792 | break; | |
4793 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
4794 | _print_next_block((*par_num)++, "CFC"); | |
6bf07b8e YM |
4795 | _print_parity(bp, |
4796 | CFC_REG_CFC_PRTY_STS); | |
4293b9f5 DK |
4797 | break; |
4798 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
4799 | _print_next_block((*par_num)++, "CDU"); | |
6bf07b8e | 4800 | _print_parity(bp, CDU_REG_CDU_PRTY_STS); |
4293b9f5 DK |
4801 | break; |
4802 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
4803 | _print_next_block((*par_num)++, "DMAE"); | |
6bf07b8e YM |
4804 | _print_parity(bp, |
4805 | DMAE_REG_DMAE_PRTY_STS); | |
4293b9f5 DK |
4806 | break; |
4807 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
4808 | _print_next_block((*par_num)++, "IGU"); | |
6bf07b8e YM |
4809 | if (CHIP_IS_E1x(bp)) |
4810 | _print_parity(bp, | |
4811 | HC_REG_HC_PRTY_STS); | |
4812 | else | |
4813 | _print_parity(bp, | |
4814 | IGU_REG_IGU_PRTY_STS); | |
4293b9f5 DK |
4815 | break; |
4816 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
4817 | _print_next_block((*par_num)++, "MISC"); | |
6bf07b8e YM |
4818 | _print_parity(bp, |
4819 | MISC_REG_MISC_PRTY_STS); | |
4293b9f5 | 4820 | break; |
6bf07b8e | 4821 | } |
72fd0718 VZ |
4822 | } |
4823 | ||
4824 | /* Clear the bit */ | |
4825 | sig &= ~cur_bit; | |
4826 | } | |
4827 | } | |
4828 | ||
4293b9f5 | 4829 | return res; |
72fd0718 VZ |
4830 | } |
4831 | ||
4293b9f5 DK |
4832 | static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig, |
4833 | int *par_num, bool *global, | |
4834 | bool print) | |
72fd0718 | 4835 | { |
4293b9f5 DK |
4836 | bool res = false; |
4837 | u32 cur_bit; | |
4838 | int i; | |
4839 | ||
72fd0718 | 4840 | for (i = 0; sig; i++) { |
4293b9f5 | 4841 | cur_bit = (0x1UL << i); |
72fd0718 VZ |
4842 | if (sig & cur_bit) { |
4843 | switch (cur_bit) { | |
4844 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 | 4845 | if (print) |
4293b9f5 DK |
4846 | _print_next_block((*par_num)++, |
4847 | "MCP ROM"); | |
c9ee9206 | 4848 | *global = true; |
0c23ad37 | 4849 | res = true; |
72fd0718 VZ |
4850 | break; |
4851 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 | 4852 | if (print) |
4293b9f5 | 4853 | _print_next_block((*par_num)++, |
c9ee9206 VZ |
4854 | "MCP UMP RX"); |
4855 | *global = true; | |
0c23ad37 | 4856 | res = true; |
72fd0718 VZ |
4857 | break; |
4858 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 | 4859 | if (print) |
4293b9f5 | 4860 | _print_next_block((*par_num)++, |
c9ee9206 VZ |
4861 | "MCP UMP TX"); |
4862 | *global = true; | |
0c23ad37 | 4863 | res = true; |
72fd0718 VZ |
4864 | break; |
4865 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
c9ee9206 | 4866 | if (print) |
4293b9f5 | 4867 | _print_next_block((*par_num)++, |
c9ee9206 | 4868 | "MCP SCPAD"); |
4293b9f5 DK |
4869 | /* clear latched SCPAD PATIRY from MCP */ |
4870 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, | |
4871 | 1UL << 10); | |
72fd0718 VZ |
4872 | break; |
4873 | } | |
4874 | ||
4875 | /* Clear the bit */ | |
4876 | sig &= ~cur_bit; | |
4877 | } | |
4878 | } | |
4879 | ||
4293b9f5 | 4880 | return res; |
72fd0718 VZ |
4881 | } |
4882 | ||
4293b9f5 DK |
4883 | static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, |
4884 | int *par_num, bool print) | |
8736c826 | 4885 | { |
4293b9f5 DK |
4886 | u32 cur_bit; |
4887 | bool res; | |
4888 | int i; | |
4889 | ||
4890 | res = false; | |
4891 | ||
8736c826 | 4892 | for (i = 0; sig; i++) { |
4293b9f5 | 4893 | cur_bit = (0x1UL << i); |
8736c826 | 4894 | if (sig & cur_bit) { |
0c23ad37 | 4895 | res = true; /* Each bit is real error! */ |
4293b9f5 DK |
4896 | if (print) { |
4897 | switch (cur_bit) { | |
4898 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
4899 | _print_next_block((*par_num)++, | |
4900 | "PGLUE_B"); | |
6bf07b8e | 4901 | _print_parity(bp, |
4293b9f5 DK |
4902 | PGLUE_B_REG_PGLUE_B_PRTY_STS); |
4903 | break; | |
4904 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
4905 | _print_next_block((*par_num)++, "ATC"); | |
6bf07b8e YM |
4906 | _print_parity(bp, |
4907 | ATC_REG_ATC_PRTY_STS); | |
4293b9f5 | 4908 | break; |
6bf07b8e | 4909 | } |
8736c826 | 4910 | } |
8736c826 VZ |
4911 | /* Clear the bit */ |
4912 | sig &= ~cur_bit; | |
4913 | } | |
4914 | } | |
4915 | ||
4293b9f5 | 4916 | return res; |
8736c826 VZ |
4917 | } |
4918 | ||
1191cb83 ED |
4919 | static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
4920 | u32 *sig) | |
72fd0718 | 4921 | { |
4293b9f5 DK |
4922 | bool res = false; |
4923 | ||
8736c826 VZ |
4924 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4925 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4926 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4927 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4928 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 | 4929 | int par_num = 0; |
51c1a580 MS |
4930 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
4931 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", | |
8736c826 VZ |
4932 | sig[0] & HW_PRTY_ASSERT_SET_0, |
4933 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4934 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4935 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4936 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
c9ee9206 VZ |
4937 | if (print) |
4938 | netdev_err(bp->dev, | |
4939 | "Parity errors detected in blocks: "); | |
4293b9f5 DK |
4940 | res |= bnx2x_check_blocks_with_parity0(bp, |
4941 | sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print); | |
4942 | res |= bnx2x_check_blocks_with_parity1(bp, | |
4943 | sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print); | |
4944 | res |= bnx2x_check_blocks_with_parity2(bp, | |
4945 | sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print); | |
4946 | res |= bnx2x_check_blocks_with_parity3(bp, | |
4947 | sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print); | |
4948 | res |= bnx2x_check_blocks_with_parity4(bp, | |
4949 | sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print); | |
8736c826 | 4950 | |
c9ee9206 VZ |
4951 | if (print) |
4952 | pr_cont("\n"); | |
4293b9f5 | 4953 | } |
8736c826 | 4954 | |
4293b9f5 | 4955 | return res; |
72fd0718 VZ |
4956 | } |
4957 | ||
c9ee9206 VZ |
4958 | /** |
4959 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
4960 | * | |
4961 | * @bp: driver handle | |
4962 | * @global: true if there was a global attention | |
4963 | * @print: show parity attention in syslog | |
4964 | */ | |
4965 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 4966 | { |
8736c826 | 4967 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
4968 | int port = BP_PORT(bp); |
4969 | ||
4970 | attn.sig[0] = REG_RD(bp, | |
4971 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
4972 | port*4); | |
4973 | attn.sig[1] = REG_RD(bp, | |
4974 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
4975 | port*4); | |
4976 | attn.sig[2] = REG_RD(bp, | |
4977 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
4978 | port*4); | |
4979 | attn.sig[3] = REG_RD(bp, | |
4980 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
4981 | port*4); | |
0a5ccb75 YM |
4982 | /* Since MCP attentions can't be disabled inside the block, we need to |
4983 | * read AEU registers to see whether they're currently disabled | |
4984 | */ | |
4985 | attn.sig[3] &= ((REG_RD(bp, | |
4986 | !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 | |
4987 | : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) & | |
4988 | MISC_AEU_ENABLE_MCP_PRTY_BITS) | | |
4989 | ~MISC_AEU_ENABLE_MCP_PRTY_BITS); | |
72fd0718 | 4990 | |
8736c826 VZ |
4991 | if (!CHIP_IS_E1x(bp)) |
4992 | attn.sig[4] = REG_RD(bp, | |
4993 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
4994 | port*4); | |
4995 | ||
4996 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
4997 | } |
4998 | ||
1191cb83 | 4999 | static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) |
f2e0899f DK |
5000 | { |
5001 | u32 val; | |
5002 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
5003 | ||
5004 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
5005 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
5006 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
51c1a580 | 5007 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
f2e0899f | 5008 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
51c1a580 | 5009 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
f2e0899f | 5010 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
51c1a580 | 5011 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
f2e0899f | 5012 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
51c1a580 | 5013 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
f2e0899f DK |
5014 | if (val & |
5015 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
51c1a580 | 5016 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
f2e0899f DK |
5017 | if (val & |
5018 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
51c1a580 | 5019 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
f2e0899f | 5020 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
51c1a580 | 5021 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
f2e0899f | 5022 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
51c1a580 | 5023 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
f2e0899f | 5024 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
51c1a580 | 5025 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
f2e0899f DK |
5026 | } |
5027 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
5028 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
5029 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
5030 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
5031 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
5032 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
51c1a580 | 5033 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
f2e0899f | 5034 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
51c1a580 | 5035 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
f2e0899f | 5036 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
51c1a580 | 5037 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
f2e0899f DK |
5038 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
5039 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
5040 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
51c1a580 | 5041 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
f2e0899f DK |
5042 | } |
5043 | ||
5044 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
5045 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
5046 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
5047 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
5048 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
5049 | } | |
f2e0899f DK |
5050 | } |
5051 | ||
72fd0718 VZ |
5052 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
5053 | { | |
5054 | struct attn_route attn, *group_mask; | |
34f80b04 | 5055 | int port = BP_PORT(bp); |
877e9aa4 | 5056 | int index; |
a2fbb9ea ET |
5057 | u32 reg_addr; |
5058 | u32 val; | |
3fcaf2e5 | 5059 | u32 aeu_mask; |
c9ee9206 | 5060 | bool global = false; |
a2fbb9ea ET |
5061 | |
5062 | /* need to take HW lock because MCP or other port might also | |
5063 | try to handle this event */ | |
4a37fb66 | 5064 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 5065 | |
c9ee9206 VZ |
5066 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
5067 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 5068 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 5069 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
5070 | /* Disable HW interrupts */ |
5071 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
5072 | /* In case of parity errors don't handle attentions so that |
5073 | * other function would "see" parity errors. | |
5074 | */ | |
c9ee9206 VZ |
5075 | #else |
5076 | bnx2x_panic(); | |
5077 | #endif | |
5078 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
5079 | return; |
5080 | } | |
5081 | ||
a2fbb9ea ET |
5082 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
5083 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
5084 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
5085 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 5086 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5087 | attn.sig[4] = |
5088 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
5089 | else | |
5090 | attn.sig[4] = 0; | |
5091 | ||
5092 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
5093 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
5094 | |
5095 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
5096 | if (deasserted & (1 << index)) { | |
72fd0718 | 5097 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 5098 | |
51c1a580 | 5099 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
f2e0899f DK |
5100 | index, |
5101 | group_mask->sig[0], group_mask->sig[1], | |
5102 | group_mask->sig[2], group_mask->sig[3], | |
5103 | group_mask->sig[4]); | |
a2fbb9ea | 5104 | |
f2e0899f DK |
5105 | bnx2x_attn_int_deasserted4(bp, |
5106 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 5107 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 5108 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 5109 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 5110 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 5111 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 5112 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 5113 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 5114 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
5115 | } |
5116 | } | |
5117 | ||
4a37fb66 | 5118 | bnx2x_release_alr(bp); |
a2fbb9ea | 5119 | |
f2e0899f DK |
5120 | if (bp->common.int_block == INT_BLOCK_HC) |
5121 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
5122 | COMMAND_REG_ATTN_BITS_CLR); | |
5123 | else | |
5124 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
5125 | |
5126 | val = ~deasserted; | |
f2e0899f DK |
5127 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
5128 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 5129 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 5130 | |
a2fbb9ea | 5131 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 5132 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
5133 | |
5134 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
5135 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
5136 | ||
3fcaf2e5 EG |
5137 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
5138 | aeu_mask = REG_RD(bp, reg_addr); | |
5139 | ||
5140 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
5141 | aeu_mask, deasserted); | |
72fd0718 | 5142 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 5143 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 5144 | |
3fcaf2e5 EG |
5145 | REG_WR(bp, reg_addr, aeu_mask); |
5146 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
5147 | |
5148 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
5149 | bp->attn_state &= ~deasserted; | |
5150 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
5151 | } | |
5152 | ||
5153 | static void bnx2x_attn_int(struct bnx2x *bp) | |
5154 | { | |
5155 | /* read local copy of bits */ | |
68d59484 EG |
5156 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
5157 | attn_bits); | |
5158 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
5159 | attn_bits_ack); | |
a2fbb9ea ET |
5160 | u32 attn_state = bp->attn_state; |
5161 | ||
5162 | /* look for changed bits */ | |
5163 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
5164 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
5165 | ||
5166 | DP(NETIF_MSG_HW, | |
5167 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
5168 | attn_bits, attn_ack, asserted, deasserted); | |
5169 | ||
5170 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 5171 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
5172 | |
5173 | /* handle bits that were raised */ | |
5174 | if (asserted) | |
5175 | bnx2x_attn_int_asserted(bp, asserted); | |
5176 | ||
5177 | if (deasserted) | |
5178 | bnx2x_attn_int_deasserted(bp, deasserted); | |
5179 | } | |
5180 | ||
619c5cb6 VZ |
5181 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
5182 | u16 index, u8 op, u8 update) | |
5183 | { | |
dc1ba591 AE |
5184 | u32 igu_addr = bp->igu_base_addr; |
5185 | igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
619c5cb6 VZ |
5186 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, |
5187 | igu_addr); | |
5188 | } | |
5189 | ||
1191cb83 | 5190 | static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
523224a3 DK |
5191 | { |
5192 | /* No memory barriers */ | |
5193 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
5194 | mmiowb(); /* keep prod updates ordered */ | |
5195 | } | |
5196 | ||
523224a3 DK |
5197 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, |
5198 | union event_ring_elem *elem) | |
5199 | { | |
619c5cb6 VZ |
5200 | u8 err = elem->message.error; |
5201 | ||
523224a3 | 5202 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
5203 | (cid < bp->cnic_eth_dev.starting_cid && |
5204 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
5205 | return 1; |
5206 | ||
5207 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
5208 | ||
619c5cb6 VZ |
5209 | if (unlikely(err)) { |
5210 | ||
523224a3 DK |
5211 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
5212 | cid); | |
823e1d90 | 5213 | bnx2x_panic_dump(bp, false); |
523224a3 | 5214 | } |
619c5cb6 | 5215 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
5216 | return 0; |
5217 | } | |
523224a3 | 5218 | |
1191cb83 | 5219 | static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
5220 | { |
5221 | struct bnx2x_mcast_ramrod_params rparam; | |
5222 | int rc; | |
5223 | ||
5224 | memset(&rparam, 0, sizeof(rparam)); | |
5225 | ||
5226 | rparam.mcast_obj = &bp->mcast_obj; | |
5227 | ||
5228 | netif_addr_lock_bh(bp->dev); | |
5229 | ||
5230 | /* Clear pending state for the last command */ | |
5231 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
5232 | ||
5233 | /* If there are pending mcast commands - send them */ | |
5234 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
5235 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
5236 | if (rc < 0) | |
5237 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
5238 | rc); | |
5239 | } | |
5240 | ||
5241 | netif_addr_unlock_bh(bp->dev); | |
5242 | } | |
5243 | ||
1191cb83 ED |
5244 | static void bnx2x_handle_classification_eqe(struct bnx2x *bp, |
5245 | union event_ring_elem *elem) | |
619c5cb6 VZ |
5246 | { |
5247 | unsigned long ramrod_flags = 0; | |
5248 | int rc = 0; | |
5249 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
5250 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
5251 | ||
5252 | /* Always push next commands out, don't wait here */ | |
5253 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
5254 | ||
86564c3f YM |
5255 | switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo) |
5256 | >> BNX2X_SWCID_SHIFT) { | |
619c5cb6 | 5257 | case BNX2X_FILTER_MAC_PENDING: |
51c1a580 | 5258 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
55c11941 | 5259 | if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) |
619c5cb6 VZ |
5260 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; |
5261 | else | |
15192a8c | 5262 | vlan_mac_obj = &bp->sp_objs[cid].mac_obj; |
619c5cb6 VZ |
5263 | |
5264 | break; | |
619c5cb6 | 5265 | case BNX2X_FILTER_MCAST_PENDING: |
51c1a580 | 5266 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
619c5cb6 VZ |
5267 | /* This is only relevant for 57710 where multicast MACs are |
5268 | * configured as unicast MACs using the same ramrod. | |
5269 | */ | |
5270 | bnx2x_handle_mcast_eqe(bp); | |
5271 | return; | |
5272 | default: | |
5273 | BNX2X_ERR("Unsupported classification command: %d\n", | |
5274 | elem->message.data.eth_event.echo); | |
5275 | return; | |
5276 | } | |
5277 | ||
5278 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
5279 | ||
5280 | if (rc < 0) | |
5281 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
5282 | else if (rc > 0) | |
5283 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
619c5cb6 VZ |
5284 | } |
5285 | ||
619c5cb6 | 5286 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); |
619c5cb6 | 5287 | |
1191cb83 | 5288 | static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
5289 | { |
5290 | netif_addr_lock_bh(bp->dev); | |
5291 | ||
5292 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5293 | ||
5294 | /* Send rx_mode command again if was requested */ | |
5295 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
5296 | bnx2x_set_storm_rx_mode(bp); | |
619c5cb6 VZ |
5297 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, |
5298 | &bp->sp_state)) | |
5299 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
5300 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
5301 | &bp->sp_state)) | |
5302 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
619c5cb6 VZ |
5303 | |
5304 | netif_addr_unlock_bh(bp->dev); | |
5305 | } | |
5306 | ||
1191cb83 | 5307 | static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, |
a3348722 BW |
5308 | union event_ring_elem *elem) |
5309 | { | |
5310 | if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { | |
5311 | DP(BNX2X_MSG_SP, | |
5312 | "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", | |
5313 | elem->message.data.vif_list_event.func_bit_map); | |
5314 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, | |
5315 | elem->message.data.vif_list_event.func_bit_map); | |
5316 | } else if (elem->message.data.vif_list_event.echo == | |
5317 | VIF_LIST_RULE_SET) { | |
5318 | DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); | |
5319 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); | |
5320 | } | |
5321 | } | |
5322 | ||
5323 | /* called with rtnl_lock */ | |
1191cb83 | 5324 | static void bnx2x_after_function_update(struct bnx2x *bp) |
a3348722 BW |
5325 | { |
5326 | int q, rc; | |
5327 | struct bnx2x_fastpath *fp; | |
5328 | struct bnx2x_queue_state_params queue_params = {NULL}; | |
5329 | struct bnx2x_queue_update_params *q_update_params = | |
5330 | &queue_params.params.update; | |
5331 | ||
2de67439 | 5332 | /* Send Q update command with afex vlan removal values for all Qs */ |
a3348722 BW |
5333 | queue_params.cmd = BNX2X_Q_CMD_UPDATE; |
5334 | ||
5335 | /* set silent vlan removal values according to vlan mode */ | |
5336 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | |
5337 | &q_update_params->update_flags); | |
5338 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
5339 | &q_update_params->update_flags); | |
5340 | __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
5341 | ||
5342 | /* in access mode mark mask and value are 0 to strip all vlans */ | |
5343 | if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { | |
5344 | q_update_params->silent_removal_value = 0; | |
5345 | q_update_params->silent_removal_mask = 0; | |
5346 | } else { | |
5347 | q_update_params->silent_removal_value = | |
5348 | (bp->afex_def_vlan_tag & VLAN_VID_MASK); | |
5349 | q_update_params->silent_removal_mask = VLAN_VID_MASK; | |
5350 | } | |
5351 | ||
5352 | for_each_eth_queue(bp, q) { | |
5353 | /* Set the appropriate Queue object */ | |
5354 | fp = &bp->fp[q]; | |
15192a8c | 5355 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
5356 | |
5357 | /* send the ramrod */ | |
5358 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
5359 | if (rc < 0) | |
5360 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
5361 | q); | |
5362 | } | |
5363 | ||
fea75645 | 5364 | if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { |
65565884 | 5365 | fp = &bp->fp[FCOE_IDX(bp)]; |
15192a8c | 5366 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
5367 | |
5368 | /* clear pending completion bit */ | |
5369 | __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
5370 | ||
5371 | /* mark latest Q bit */ | |
4e857c58 | 5372 | smp_mb__before_atomic(); |
a3348722 | 5373 | set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); |
4e857c58 | 5374 | smp_mb__after_atomic(); |
a3348722 BW |
5375 | |
5376 | /* send Q update ramrod for FCoE Q */ | |
5377 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
5378 | if (rc < 0) | |
5379 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
5380 | q); | |
5381 | } else { | |
5382 | /* If no FCoE ring - ACK MCP now */ | |
5383 | bnx2x_link_report(bp); | |
5384 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5385 | } | |
a3348722 BW |
5386 | } |
5387 | ||
1191cb83 | 5388 | static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( |
619c5cb6 VZ |
5389 | struct bnx2x *bp, u32 cid) |
5390 | { | |
94f05b0f | 5391 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
55c11941 MS |
5392 | |
5393 | if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) | |
15192a8c | 5394 | return &bnx2x_fcoe_sp_obj(bp, q_obj); |
619c5cb6 | 5395 | else |
15192a8c | 5396 | return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; |
619c5cb6 VZ |
5397 | } |
5398 | ||
523224a3 DK |
5399 | static void bnx2x_eq_int(struct bnx2x *bp) |
5400 | { | |
5401 | u16 hw_cons, sw_cons, sw_prod; | |
5402 | union event_ring_elem *elem; | |
55c11941 | 5403 | u8 echo; |
523224a3 DK |
5404 | u32 cid; |
5405 | u8 opcode; | |
fd1fc79d | 5406 | int rc, spqe_cnt = 0; |
619c5cb6 VZ |
5407 | struct bnx2x_queue_sp_obj *q_obj; |
5408 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
5409 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
5410 | |
5411 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
5412 | ||
5413 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
16a5fd92 | 5414 | * when we get the next-page we need to adjust so the loop |
523224a3 DK |
5415 | * condition below will be met. The next element is the size of a |
5416 | * regular element and hence incrementing by 1 | |
5417 | */ | |
5418 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
5419 | hw_cons++; | |
5420 | ||
25985edc | 5421 | /* This function may never run in parallel with itself for a |
523224a3 DK |
5422 | * specific bp, thus there is no need in "paired" read memory |
5423 | * barrier here. | |
5424 | */ | |
5425 | sw_cons = bp->eq_cons; | |
5426 | sw_prod = bp->eq_prod; | |
5427 | ||
d6cae238 | 5428 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 5429 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
5430 | |
5431 | for (; sw_cons != hw_cons; | |
5432 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
5433 | ||
523224a3 DK |
5434 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; |
5435 | ||
fd1fc79d AE |
5436 | rc = bnx2x_iov_eq_sp_event(bp, elem); |
5437 | if (!rc) { | |
5438 | DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", | |
5439 | rc); | |
5440 | goto next_spqe; | |
5441 | } | |
523224a3 | 5442 | |
86564c3f YM |
5443 | /* elem CID originates from FW; actually LE */ |
5444 | cid = SW_CID((__force __le32) | |
5445 | elem->message.data.cfc_del_event.cid); | |
5446 | opcode = elem->message.opcode; | |
523224a3 DK |
5447 | |
5448 | /* handle eq element */ | |
5449 | switch (opcode) { | |
fd1fc79d | 5450 | case EVENT_RING_OPCODE_VF_PF_CHANNEL: |
370d4a26 YM |
5451 | bnx2x_vf_mbx_schedule(bp, |
5452 | &elem->message.data.vf_pf_event); | |
fd1fc79d AE |
5453 | continue; |
5454 | ||
523224a3 | 5455 | case EVENT_RING_OPCODE_STAT_QUERY: |
76ca70fa YM |
5456 | DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS), |
5457 | "got statistics comp event %d\n", | |
5458 | bp->stats_comp++); | |
523224a3 | 5459 | /* nothing to do with stats comp */ |
d6cae238 | 5460 | goto next_spqe; |
523224a3 DK |
5461 | |
5462 | case EVENT_RING_OPCODE_CFC_DEL: | |
5463 | /* handle according to cid range */ | |
5464 | /* | |
5465 | * we may want to verify here that the bp state is | |
5466 | * HALTING | |
5467 | */ | |
d6cae238 | 5468 | DP(BNX2X_MSG_SP, |
523224a3 | 5469 | "got delete ramrod for MULTI[%d]\n", cid); |
55c11941 MS |
5470 | |
5471 | if (CNIC_LOADED(bp) && | |
5472 | !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
523224a3 | 5473 | goto next_spqe; |
55c11941 | 5474 | |
619c5cb6 VZ |
5475 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
5476 | ||
5477 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
5478 | break; | |
5479 | ||
523224a3 | 5480 | goto next_spqe; |
e4901dde VZ |
5481 | |
5482 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
51c1a580 | 5483 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
6ffa39f2 | 5484 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
6debea87 DK |
5485 | if (f_obj->complete_cmd(bp, f_obj, |
5486 | BNX2X_F_CMD_TX_STOP)) | |
5487 | break; | |
e4901dde | 5488 | goto next_spqe; |
619c5cb6 | 5489 | |
e4901dde | 5490 | case EVENT_RING_OPCODE_START_TRAFFIC: |
51c1a580 | 5491 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
6ffa39f2 | 5492 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
6debea87 DK |
5493 | if (f_obj->complete_cmd(bp, f_obj, |
5494 | BNX2X_F_CMD_TX_START)) | |
5495 | break; | |
e4901dde | 5496 | goto next_spqe; |
55c11941 | 5497 | |
a3348722 | 5498 | case EVENT_RING_OPCODE_FUNCTION_UPDATE: |
55c11941 MS |
5499 | echo = elem->message.data.function_update_event.echo; |
5500 | if (echo == SWITCH_UPDATE) { | |
5501 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, | |
5502 | "got FUNC_SWITCH_UPDATE ramrod\n"); | |
5503 | if (f_obj->complete_cmd( | |
5504 | bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) | |
5505 | break; | |
a3348722 | 5506 | |
55c11941 | 5507 | } else { |
230bb0f3 YM |
5508 | int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE; |
5509 | ||
55c11941 MS |
5510 | DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, |
5511 | "AFEX: ramrod completed FUNCTION_UPDATE\n"); | |
5512 | f_obj->complete_cmd(bp, f_obj, | |
5513 | BNX2X_F_CMD_AFEX_UPDATE); | |
5514 | ||
5515 | /* We will perform the Queues update from | |
5516 | * sp_rtnl task as all Queue SP operations | |
5517 | * should run under rtnl_lock. | |
5518 | */ | |
230bb0f3 | 5519 | bnx2x_schedule_sp_rtnl(bp, cmd, 0); |
55c11941 | 5520 | } |
a3348722 | 5521 | |
a3348722 BW |
5522 | goto next_spqe; |
5523 | ||
5524 | case EVENT_RING_OPCODE_AFEX_VIF_LISTS: | |
5525 | f_obj->complete_cmd(bp, f_obj, | |
5526 | BNX2X_F_CMD_AFEX_VIFLISTS); | |
5527 | bnx2x_after_afex_vif_lists(bp, elem); | |
5528 | goto next_spqe; | |
619c5cb6 | 5529 | case EVENT_RING_OPCODE_FUNCTION_START: |
51c1a580 MS |
5530 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5531 | "got FUNC_START ramrod\n"); | |
619c5cb6 VZ |
5532 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
5533 | break; | |
5534 | ||
5535 | goto next_spqe; | |
5536 | ||
5537 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
51c1a580 MS |
5538 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5539 | "got FUNC_STOP ramrod\n"); | |
619c5cb6 VZ |
5540 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
5541 | break; | |
5542 | ||
5543 | goto next_spqe; | |
eeed018c MK |
5544 | |
5545 | case EVENT_RING_OPCODE_SET_TIMESYNC: | |
5546 | DP(BNX2X_MSG_SP | BNX2X_MSG_PTP, | |
5547 | "got set_timesync ramrod completion\n"); | |
5548 | if (f_obj->complete_cmd(bp, f_obj, | |
5549 | BNX2X_F_CMD_SET_TIMESYNC)) | |
5550 | break; | |
5551 | goto next_spqe; | |
523224a3 DK |
5552 | } |
5553 | ||
5554 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
5555 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
5556 | BNX2X_STATE_OPEN): | |
5557 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 5558 | BNX2X_STATE_OPENING_WAIT4_PORT): |
619c5cb6 VZ |
5559 | cid = elem->message.data.eth_event.echo & |
5560 | BNX2X_SWCID_MASK; | |
d6cae238 | 5561 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
619c5cb6 VZ |
5562 | cid); |
5563 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
5564 | break; |
5565 | ||
619c5cb6 VZ |
5566 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
5567 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
5568 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 5569 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
5570 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
5571 | BNX2X_STATE_OPEN): | |
5572 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5573 | BNX2X_STATE_DIAG): | |
5574 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5575 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5576 | DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); |
619c5cb6 | 5577 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
5578 | break; |
5579 | ||
619c5cb6 VZ |
5580 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
5581 | BNX2X_STATE_OPEN): | |
5582 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5583 | BNX2X_STATE_DIAG): | |
5584 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5585 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5586 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 5587 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
5588 | break; |
5589 | ||
619c5cb6 VZ |
5590 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
5591 | BNX2X_STATE_OPEN): | |
5592 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
5593 | BNX2X_STATE_DIAG): | |
5594 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 5595 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 5596 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 5597 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
5598 | break; |
5599 | default: | |
5600 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
5601 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
5602 | elem->message.opcode, bp->state); | |
523224a3 DK |
5603 | } |
5604 | next_spqe: | |
5605 | spqe_cnt++; | |
5606 | } /* for */ | |
5607 | ||
4e857c58 | 5608 | smp_mb__before_atomic(); |
6e30dd4e | 5609 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
5610 | |
5611 | bp->eq_cons = sw_cons; | |
5612 | bp->eq_prod = sw_prod; | |
5613 | /* Make sure that above mem writes were issued towards the memory */ | |
5614 | smp_wmb(); | |
5615 | ||
5616 | /* update producer */ | |
5617 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
5618 | } | |
5619 | ||
a2fbb9ea ET |
5620 | static void bnx2x_sp_task(struct work_struct *work) |
5621 | { | |
1cf167f2 | 5622 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea | 5623 | |
fd1fc79d | 5624 | DP(BNX2X_MSG_SP, "sp task invoked\n"); |
a2fbb9ea | 5625 | |
16a5fd92 | 5626 | /* make sure the atomic interrupt_occurred has been written */ |
fd1fc79d AE |
5627 | smp_rmb(); |
5628 | if (atomic_read(&bp->interrupt_occurred)) { | |
a2fbb9ea | 5629 | |
fd1fc79d AE |
5630 | /* what work needs to be performed? */ |
5631 | u16 status = bnx2x_update_dsb_idx(bp); | |
cdaa7cb8 | 5632 | |
fd1fc79d AE |
5633 | DP(BNX2X_MSG_SP, "status %x\n", status); |
5634 | DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); | |
5635 | atomic_set(&bp->interrupt_occurred, 0); | |
5636 | ||
5637 | /* HW attentions */ | |
5638 | if (status & BNX2X_DEF_SB_ATT_IDX) { | |
5639 | bnx2x_attn_int(bp); | |
5640 | status &= ~BNX2X_DEF_SB_ATT_IDX; | |
5641 | } | |
5642 | ||
5643 | /* SP events: STAT_QUERY and others */ | |
5644 | if (status & BNX2X_DEF_SB_IDX) { | |
5645 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 5646 | |
55c11941 | 5647 | if (FCOE_INIT(bp) && |
fd1fc79d AE |
5648 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
5649 | /* Prevent local bottom-halves from running as | |
5650 | * we are going to change the local NAPI list. | |
5651 | */ | |
5652 | local_bh_disable(); | |
5653 | napi_schedule(&bnx2x_fcoe(bp, napi)); | |
5654 | local_bh_enable(); | |
5655 | } | |
5656 | ||
5657 | /* Handle EQ completions */ | |
5658 | bnx2x_eq_int(bp); | |
5659 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
5660 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
5661 | ||
5662 | status &= ~BNX2X_DEF_SB_IDX; | |
019dbb4c | 5663 | } |
55c11941 | 5664 | |
fd1fc79d AE |
5665 | /* if status is non zero then perhaps something went wrong */ |
5666 | if (unlikely(status)) | |
5667 | DP(BNX2X_MSG_SP, | |
5668 | "got an unknown interrupt! (status 0x%x)\n", status); | |
523224a3 | 5669 | |
fd1fc79d AE |
5670 | /* ack status block only if something was actually handled */ |
5671 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, | |
5672 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
cdaa7cb8 VZ |
5673 | } |
5674 | ||
a3348722 BW |
5675 | /* afex - poll to check if VIFSET_ACK should be sent to MFW */ |
5676 | if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, | |
5677 | &bp->sp_state)) { | |
5678 | bnx2x_link_report(bp); | |
5679 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5680 | } | |
a2fbb9ea ET |
5681 | } |
5682 | ||
9f6c9258 | 5683 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
5684 | { |
5685 | struct net_device *dev = dev_instance; | |
5686 | struct bnx2x *bp = netdev_priv(dev); | |
5687 | ||
523224a3 DK |
5688 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
5689 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
5690 | |
5691 | #ifdef BNX2X_STOP_ON_ERROR | |
5692 | if (unlikely(bp->panic)) | |
5693 | return IRQ_HANDLED; | |
5694 | #endif | |
5695 | ||
55c11941 | 5696 | if (CNIC_LOADED(bp)) { |
993ac7b5 MC |
5697 | struct cnic_ops *c_ops; |
5698 | ||
5699 | rcu_read_lock(); | |
5700 | c_ops = rcu_dereference(bp->cnic_ops); | |
5701 | if (c_ops) | |
5702 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
5703 | rcu_read_unlock(); | |
5704 | } | |
55c11941 | 5705 | |
fd1fc79d AE |
5706 | /* schedule sp task to perform default status block work, ack |
5707 | * attentions and enable interrupts. | |
5708 | */ | |
5709 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
5710 | |
5711 | return IRQ_HANDLED; | |
5712 | } | |
5713 | ||
5714 | /* end of slow path */ | |
5715 | ||
619c5cb6 VZ |
5716 | void bnx2x_drv_pulse(struct bnx2x *bp) |
5717 | { | |
5718 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
5719 | bp->fw_drv_pulse_wr_seq); | |
5720 | } | |
5721 | ||
a2fbb9ea ET |
5722 | static void bnx2x_timer(unsigned long data) |
5723 | { | |
5724 | struct bnx2x *bp = (struct bnx2x *) data; | |
5725 | ||
5726 | if (!netif_running(bp->dev)) | |
5727 | return; | |
5728 | ||
67c431a5 AE |
5729 | if (IS_PF(bp) && |
5730 | !BP_NOMCP(bp)) { | |
f2e0899f | 5731 | int mb_idx = BP_FW_MB_IDX(bp); |
4c868664 EG |
5732 | u16 drv_pulse; |
5733 | u16 mcp_pulse; | |
a2fbb9ea ET |
5734 | |
5735 | ++bp->fw_drv_pulse_wr_seq; | |
5736 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
a2fbb9ea | 5737 | drv_pulse = bp->fw_drv_pulse_wr_seq; |
619c5cb6 | 5738 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 5739 | |
f2e0899f | 5740 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
5741 | MCP_PULSE_SEQ_MASK); |
5742 | /* The delta between driver pulse and mcp response | |
4c868664 EG |
5743 | * should not get too big. If the MFW is more than 5 pulses |
5744 | * behind, we should worry about it enough to generate an error | |
5745 | * log. | |
a2fbb9ea | 5746 | */ |
4c868664 EG |
5747 | if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5) |
5748 | BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
a2fbb9ea | 5749 | drv_pulse, mcp_pulse); |
a2fbb9ea ET |
5750 | } |
5751 | ||
f34d28ea | 5752 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 5753 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 5754 | |
abc5a021 | 5755 | /* sample pf vf bulletin board for new posts from pf */ |
37173488 YM |
5756 | if (IS_VF(bp)) |
5757 | bnx2x_timer_sriov(bp); | |
78c3bcc5 | 5758 | |
a2fbb9ea ET |
5759 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
5760 | } | |
5761 | ||
5762 | /* end of Statistics */ | |
5763 | ||
5764 | /* nic init */ | |
5765 | ||
5766 | /* | |
5767 | * nic init service functions | |
5768 | */ | |
5769 | ||
1191cb83 | 5770 | static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 5771 | { |
523224a3 DK |
5772 | u32 i; |
5773 | if (!(len%4) && !(addr%4)) | |
5774 | for (i = 0; i < len; i += 4) | |
5775 | REG_WR(bp, addr + i, fill); | |
5776 | else | |
5777 | for (i = 0; i < len; i++) | |
5778 | REG_WR8(bp, addr + i, fill); | |
34f80b04 EG |
5779 | } |
5780 | ||
523224a3 | 5781 | /* helper: writes FP SP data to FW - data_size in dwords */ |
1191cb83 ED |
5782 | static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, |
5783 | int fw_sb_id, | |
5784 | u32 *sb_data_p, | |
5785 | u32 data_size) | |
34f80b04 | 5786 | { |
a2fbb9ea | 5787 | int index; |
523224a3 DK |
5788 | for (index = 0; index < data_size; index++) |
5789 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5790 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
5791 | sizeof(u32)*index, | |
5792 | *(sb_data_p + index)); | |
5793 | } | |
a2fbb9ea | 5794 | |
1191cb83 | 5795 | static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
523224a3 DK |
5796 | { |
5797 | u32 *sb_data_p; | |
5798 | u32 data_size = 0; | |
f2e0899f | 5799 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 5800 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 5801 | |
523224a3 | 5802 | /* disable the function first */ |
619c5cb6 | 5803 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5804 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5805 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
5806 | sb_data_e2.common.p_func.vf_valid = false; |
5807 | sb_data_p = (u32 *)&sb_data_e2; | |
5808 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
5809 | } else { | |
5810 | memset(&sb_data_e1x, 0, | |
5811 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5812 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
5813 | sb_data_e1x.common.p_func.vf_valid = false; |
5814 | sb_data_p = (u32 *)&sb_data_e1x; | |
5815 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
5816 | } | |
523224a3 | 5817 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 5818 | |
523224a3 DK |
5819 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
5820 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
5821 | CSTORM_STATUS_BLOCK_SIZE); | |
5822 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5823 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
5824 | CSTORM_SYNC_BLOCK_SIZE); | |
5825 | } | |
34f80b04 | 5826 | |
523224a3 | 5827 | /* helper: writes SP SB data to FW */ |
1191cb83 | 5828 | static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, |
523224a3 DK |
5829 | struct hc_sp_status_block_data *sp_sb_data) |
5830 | { | |
5831 | int func = BP_FUNC(bp); | |
5832 | int i; | |
5833 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
5834 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5835 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
5836 | i*sizeof(u32), | |
5837 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
5838 | } |
5839 | ||
1191cb83 | 5840 | static void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
5841 | { |
5842 | int func = BP_FUNC(bp); | |
523224a3 DK |
5843 | struct hc_sp_status_block_data sp_sb_data; |
5844 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 5845 | |
619c5cb6 | 5846 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
5847 | sp_sb_data.p_func.vf_valid = false; |
5848 | ||
5849 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
5850 | ||
5851 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5852 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
5853 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
5854 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5855 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
5856 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
523224a3 DK |
5857 | } |
5858 | ||
1191cb83 | 5859 | static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, |
523224a3 DK |
5860 | int igu_sb_id, int igu_seg_id) |
5861 | { | |
5862 | hc_sm->igu_sb_id = igu_sb_id; | |
5863 | hc_sm->igu_seg_id = igu_seg_id; | |
5864 | hc_sm->timer_value = 0xFF; | |
5865 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
5866 | } |
5867 | ||
150966ad | 5868 | /* allocates state machine ids. */ |
1191cb83 | 5869 | static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) |
150966ad AE |
5870 | { |
5871 | /* zero out state machine indices */ | |
5872 | /* rx indices */ | |
5873 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5874 | ||
5875 | /* tx indices */ | |
5876 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5877 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
5878 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
5879 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
5880 | ||
5881 | /* map indices */ | |
5882 | /* rx indices */ | |
5883 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
5884 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5885 | ||
5886 | /* tx indices */ | |
5887 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
5888 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5889 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
5890 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5891 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
5892 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5893 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
5894 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5895 | } | |
5896 | ||
b93288d5 | 5897 | void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 5898 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 5899 | { |
523224a3 DK |
5900 | int igu_seg_id; |
5901 | ||
f2e0899f | 5902 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
5903 | struct hc_status_block_data_e1x sb_data_e1x; |
5904 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
5905 | int data_size; |
5906 | u32 *sb_data_p; | |
5907 | ||
f2e0899f DK |
5908 | if (CHIP_INT_MODE_IS_BC(bp)) |
5909 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
5910 | else | |
5911 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
5912 | |
5913 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
5914 | ||
619c5cb6 | 5915 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5916 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5917 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
5918 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
5919 | sb_data_e2.common.p_func.vf_id = vfid; | |
5920 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
5921 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
5922 | sb_data_e2.common.same_igu_sb_1b = true; | |
5923 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
5924 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
5925 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
5926 | sb_data_p = (u32 *)&sb_data_e2; |
5927 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 5928 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
5929 | } else { |
5930 | memset(&sb_data_e1x, 0, | |
5931 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5932 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
5933 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
5934 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
5935 | sb_data_e1x.common.p_func.vf_valid = false; | |
5936 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
5937 | sb_data_e1x.common.same_igu_sb_1b = true; | |
5938 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
5939 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
5940 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
5941 | sb_data_p = (u32 *)&sb_data_e1x; |
5942 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 5943 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 5944 | } |
523224a3 DK |
5945 | |
5946 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
5947 | igu_sb_id, igu_seg_id); | |
5948 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
5949 | igu_sb_id, igu_seg_id); | |
5950 | ||
51c1a580 | 5951 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
523224a3 | 5952 | |
86564c3f | 5953 | /* write indices to HW - PCI guarantees endianity of regpairs */ |
523224a3 DK |
5954 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
5955 | } | |
5956 | ||
619c5cb6 | 5957 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
5958 | u16 tx_usec, u16 rx_usec) |
5959 | { | |
6383c0b3 | 5960 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 5961 | false, rx_usec); |
6383c0b3 AE |
5962 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
5963 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
5964 | tx_usec); | |
5965 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5966 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
5967 | tx_usec); | |
5968 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5969 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
5970 | tx_usec); | |
523224a3 | 5971 | } |
f2e0899f | 5972 | |
523224a3 DK |
5973 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
5974 | { | |
5975 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
5976 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
5977 | int igu_sp_sb_index; | |
5978 | int igu_seg_id; | |
34f80b04 EG |
5979 | int port = BP_PORT(bp); |
5980 | int func = BP_FUNC(bp); | |
f2eaeb58 | 5981 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 5982 | u64 section; |
523224a3 DK |
5983 | int index; |
5984 | struct hc_sp_status_block_data sp_sb_data; | |
5985 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
5986 | ||
f2e0899f DK |
5987 | if (CHIP_INT_MODE_IS_BC(bp)) { |
5988 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
5989 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
5990 | } else { | |
5991 | igu_sp_sb_index = bp->igu_dsb_id; | |
5992 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
5993 | } | |
a2fbb9ea ET |
5994 | |
5995 | /* ATTN */ | |
523224a3 | 5996 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 5997 | atten_status_block); |
523224a3 | 5998 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 5999 | |
49d66772 ET |
6000 | bp->attn_state = 0; |
6001 | ||
a2fbb9ea ET |
6002 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
6003 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
6004 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
6005 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 6006 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
6007 | int sindex; |
6008 | /* take care of sig[0]..sig[4] */ | |
6009 | for (sindex = 0; sindex < 4; sindex++) | |
6010 | bp->attn_group[index].sig[sindex] = | |
6011 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 6012 | |
619c5cb6 | 6013 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6014 | /* |
6015 | * enable5 is separate from the rest of the registers, | |
6016 | * and therefore the address skip is 4 | |
6017 | * and not 16 between the different groups | |
6018 | */ | |
6019 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 6020 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
6021 | else |
6022 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
6023 | } |
6024 | ||
f2e0899f DK |
6025 | if (bp->common.int_block == INT_BLOCK_HC) { |
6026 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
6027 | HC_REG_ATTN_MSG0_ADDR_L); | |
6028 | ||
6029 | REG_WR(bp, reg_offset, U64_LO(section)); | |
6030 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 6031 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6032 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
6033 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
6034 | } | |
a2fbb9ea | 6035 | |
523224a3 DK |
6036 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
6037 | sp_sb); | |
a2fbb9ea | 6038 | |
523224a3 | 6039 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 6040 | |
86564c3f | 6041 | /* PCI guarantees endianity of regpairs */ |
619c5cb6 | 6042 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
6043 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
6044 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
6045 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
6046 | sp_sb_data.igu_seg_id = igu_seg_id; | |
6047 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 6048 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 6049 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 6050 | |
523224a3 | 6051 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 6052 | |
523224a3 | 6053 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
6054 | } |
6055 | ||
9f6c9258 | 6056 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 6057 | { |
a2fbb9ea ET |
6058 | int i; |
6059 | ||
ec6ba945 | 6060 | for_each_eth_queue(bp, i) |
523224a3 | 6061 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 6062 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
6063 | } |
6064 | ||
a2fbb9ea ET |
6065 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
6066 | { | |
a2fbb9ea | 6067 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 6068 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 6069 | |
a2fbb9ea | 6070 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
6071 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
6072 | bp->spq_prod_bd = bp->spq; | |
6073 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
6074 | } |
6075 | ||
523224a3 | 6076 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
6077 | { |
6078 | int i; | |
523224a3 DK |
6079 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
6080 | union event_ring_elem *elem = | |
6081 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 6082 | |
523224a3 DK |
6083 | elem->next_page.addr.hi = |
6084 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
6085 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
6086 | elem->next_page.addr.lo = | |
6087 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
6088 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 6089 | } |
523224a3 DK |
6090 | bp->eq_cons = 0; |
6091 | bp->eq_prod = NUM_EQ_DESC; | |
6092 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
16a5fd92 | 6093 | /* we want a warning message before it gets wrought... */ |
6e30dd4e VZ |
6094 | atomic_set(&bp->eq_spq_left, |
6095 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
6096 | } |
6097 | ||
619c5cb6 | 6098 | /* called with netif_addr_lock_bh() */ |
a8f47eb7 | 6099 | static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
6100 | unsigned long rx_mode_flags, | |
6101 | unsigned long rx_accept_flags, | |
6102 | unsigned long tx_accept_flags, | |
6103 | unsigned long ramrod_flags) | |
ab532cf3 | 6104 | { |
619c5cb6 VZ |
6105 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
6106 | int rc; | |
6107 | ||
6108 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
6109 | ||
6110 | /* Prepare ramrod parameters */ | |
6111 | ramrod_param.cid = 0; | |
6112 | ramrod_param.cl_id = cl_id; | |
6113 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
6114 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 6115 | |
619c5cb6 VZ |
6116 | ramrod_param.pstate = &bp->sp_state; |
6117 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 6118 | |
619c5cb6 VZ |
6119 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
6120 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
6121 | ||
6122 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
6123 | ||
6124 | ramrod_param.ramrod_flags = ramrod_flags; | |
6125 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
6126 | ||
6127 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
6128 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
6129 | ||
6130 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
6131 | if (rc < 0) { | |
6132 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
924d75ab | 6133 | return rc; |
619c5cb6 | 6134 | } |
924d75ab YM |
6135 | |
6136 | return 0; | |
a2fbb9ea ET |
6137 | } |
6138 | ||
86564c3f YM |
6139 | static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, |
6140 | unsigned long *rx_accept_flags, | |
6141 | unsigned long *tx_accept_flags) | |
471de716 | 6142 | { |
924d75ab YM |
6143 | /* Clear the flags first */ |
6144 | *rx_accept_flags = 0; | |
6145 | *tx_accept_flags = 0; | |
619c5cb6 | 6146 | |
924d75ab | 6147 | switch (rx_mode) { |
619c5cb6 VZ |
6148 | case BNX2X_RX_MODE_NONE: |
6149 | /* | |
6150 | * 'drop all' supersedes any accept flags that may have been | |
6151 | * passed to the function. | |
6152 | */ | |
6153 | break; | |
6154 | case BNX2X_RX_MODE_NORMAL: | |
924d75ab YM |
6155 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
6156 | __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags); | |
6157 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
6158 | |
6159 | /* internal switching mode */ | |
924d75ab YM |
6160 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
6161 | __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags); | |
6162 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 VZ |
6163 | |
6164 | break; | |
6165 | case BNX2X_RX_MODE_ALLMULTI: | |
924d75ab YM |
6166 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
6167 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); | |
6168 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
6169 | |
6170 | /* internal switching mode */ | |
924d75ab YM |
6171 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
6172 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); | |
6173 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 VZ |
6174 | |
6175 | break; | |
6176 | case BNX2X_RX_MODE_PROMISC: | |
16a5fd92 | 6177 | /* According to definition of SI mode, iface in promisc mode |
619c5cb6 VZ |
6178 | * should receive matched and unmatched (in resolution of port) |
6179 | * unicast packets. | |
6180 | */ | |
924d75ab YM |
6181 | __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags); |
6182 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); | |
6183 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); | |
6184 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
6185 | |
6186 | /* internal switching mode */ | |
924d75ab YM |
6187 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); |
6188 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 VZ |
6189 | |
6190 | if (IS_MF_SI(bp)) | |
924d75ab | 6191 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags); |
619c5cb6 | 6192 | else |
924d75ab | 6193 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
619c5cb6 VZ |
6194 | |
6195 | break; | |
6196 | default: | |
924d75ab YM |
6197 | BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode); |
6198 | return -EINVAL; | |
619c5cb6 | 6199 | } |
de832a55 | 6200 | |
924d75ab | 6201 | /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */ |
0c23ad37 | 6202 | if (rx_mode != BNX2X_RX_MODE_NONE) { |
924d75ab YM |
6203 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); |
6204 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); | |
34f80b04 EG |
6205 | } |
6206 | ||
924d75ab YM |
6207 | return 0; |
6208 | } | |
6209 | ||
6210 | /* called with netif_addr_lock_bh() */ | |
a8f47eb7 | 6211 | static int bnx2x_set_storm_rx_mode(struct bnx2x *bp) |
924d75ab YM |
6212 | { |
6213 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; | |
6214 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
6215 | int rc; | |
6216 | ||
6217 | if (!NO_FCOE(bp)) | |
6218 | /* Configure rx_mode of FCoE Queue */ | |
6219 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
6220 | ||
6221 | rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, | |
6222 | &tx_accept_flags); | |
6223 | if (rc) | |
6224 | return rc; | |
6225 | ||
619c5cb6 VZ |
6226 | __set_bit(RAMROD_RX, &ramrod_flags); |
6227 | __set_bit(RAMROD_TX, &ramrod_flags); | |
6228 | ||
924d75ab YM |
6229 | return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, |
6230 | rx_accept_flags, tx_accept_flags, | |
6231 | ramrod_flags); | |
619c5cb6 VZ |
6232 | } |
6233 | ||
6234 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
6235 | { | |
6236 | int i; | |
6237 | ||
523224a3 DK |
6238 | /* Zero this manually as its initialization is |
6239 | currently missing in the initTool */ | |
6240 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 6241 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 6242 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 6243 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6244 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
6245 | CHIP_INT_MODE_IS_BC(bp) ? | |
6246 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
6247 | } | |
523224a3 | 6248 | } |
8a1c38d1 | 6249 | |
471de716 EG |
6250 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
6251 | { | |
6252 | switch (load_code) { | |
6253 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 6254 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
6255 | bnx2x_init_internal_common(bp); |
6256 | /* no break */ | |
6257 | ||
6258 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 6259 | /* nothing to do */ |
471de716 EG |
6260 | /* no break */ |
6261 | ||
6262 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
6263 | /* internal memory per function is |
6264 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
6265 | break; |
6266 | ||
6267 | default: | |
6268 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
6269 | break; | |
6270 | } | |
6271 | } | |
6272 | ||
619c5cb6 | 6273 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 6274 | { |
55c11941 | 6275 | return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 | 6276 | } |
523224a3 | 6277 | |
619c5cb6 VZ |
6278 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
6279 | { | |
55c11941 | 6280 | return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 VZ |
6281 | } |
6282 | ||
1191cb83 | 6283 | static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) |
619c5cb6 VZ |
6284 | { |
6285 | if (CHIP_IS_E1x(fp->bp)) | |
6286 | return BP_L_ID(fp->bp) + fp->index; | |
6287 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
6288 | return bnx2x_fp_igu_sb_id(fp); | |
6289 | } | |
6290 | ||
6383c0b3 | 6291 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
6292 | { |
6293 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 6294 | u8 cos; |
619c5cb6 | 6295 | unsigned long q_type = 0; |
6383c0b3 | 6296 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 6297 | fp->rx_queue = fp_idx; |
b3b83c3f | 6298 | fp->cid = fp_idx; |
619c5cb6 VZ |
6299 | fp->cl_id = bnx2x_fp_cl_id(fp); |
6300 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
6301 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 6302 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
6303 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
6304 | ||
523224a3 | 6305 | /* init shortcut */ |
619c5cb6 | 6306 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
7a752993 | 6307 | |
16a5fd92 | 6308 | /* Setup SB indices */ |
523224a3 | 6309 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; |
523224a3 | 6310 | |
619c5cb6 VZ |
6311 | /* Configure Queue State object */ |
6312 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
6313 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
6314 | |
6315 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
6316 | ||
6317 | /* init tx data */ | |
6318 | for_each_cos_in_tx_queue(fp, cos) { | |
65565884 MS |
6319 | bnx2x_init_txdata(bp, fp->txdata_ptr[cos], |
6320 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), | |
6321 | FP_COS_TO_TXQ(fp, cos, bp), | |
6322 | BNX2X_TX_SB_INDEX_BASE + cos, fp); | |
6323 | cids[cos] = fp->txdata_ptr[cos]->cid; | |
6383c0b3 AE |
6324 | } |
6325 | ||
ad5afc89 AE |
6326 | /* nothing more for vf to do here */ |
6327 | if (IS_VF(bp)) | |
6328 | return; | |
6329 | ||
6330 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
6331 | fp->fw_sb_id, fp->igu_sb_id); | |
6332 | bnx2x_update_fpsb_idx(fp); | |
15192a8c BW |
6333 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, |
6334 | fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 6335 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 VZ |
6336 | |
6337 | /** | |
6338 | * Configure classification DBs: Always enable Tx switching | |
6339 | */ | |
6340 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
6341 | ||
ad5afc89 AE |
6342 | DP(NETIF_MSG_IFUP, |
6343 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
6344 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
6345 | fp->igu_sb_id); | |
523224a3 DK |
6346 | } |
6347 | ||
1191cb83 ED |
6348 | static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) |
6349 | { | |
6350 | int i; | |
6351 | ||
6352 | for (i = 1; i <= NUM_TX_RINGS; i++) { | |
6353 | struct eth_tx_next_bd *tx_next_bd = | |
6354 | &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
6355 | ||
6356 | tx_next_bd->addr_hi = | |
6357 | cpu_to_le32(U64_HI(txdata->tx_desc_mapping + | |
6358 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
6359 | tx_next_bd->addr_lo = | |
6360 | cpu_to_le32(U64_LO(txdata->tx_desc_mapping + | |
6361 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
6362 | } | |
6363 | ||
639d65b8 YM |
6364 | *txdata->tx_cons_sb = cpu_to_le16(0); |
6365 | ||
1191cb83 ED |
6366 | SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); |
6367 | txdata->tx_db.data.zero_fill1 = 0; | |
6368 | txdata->tx_db.data.prod = 0; | |
6369 | ||
6370 | txdata->tx_pkt_prod = 0; | |
6371 | txdata->tx_pkt_cons = 0; | |
6372 | txdata->tx_bd_prod = 0; | |
6373 | txdata->tx_bd_cons = 0; | |
6374 | txdata->tx_pkt = 0; | |
6375 | } | |
6376 | ||
55c11941 MS |
6377 | static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) |
6378 | { | |
6379 | int i; | |
6380 | ||
6381 | for_each_tx_queue_cnic(bp, i) | |
6382 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); | |
6383 | } | |
d76a6111 | 6384 | |
1191cb83 ED |
6385 | static void bnx2x_init_tx_rings(struct bnx2x *bp) |
6386 | { | |
6387 | int i; | |
6388 | u8 cos; | |
6389 | ||
55c11941 | 6390 | for_each_eth_queue(bp, i) |
1191cb83 | 6391 | for_each_cos_in_tx_queue(&bp->fp[i], cos) |
65565884 | 6392 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); |
1191cb83 ED |
6393 | } |
6394 | ||
a8f47eb7 | 6395 | static void bnx2x_init_fcoe_fp(struct bnx2x *bp) |
6396 | { | |
6397 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
6398 | unsigned long q_type = 0; | |
6399 | ||
6400 | bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); | |
6401 | bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, | |
6402 | BNX2X_FCOE_ETH_CL_ID_IDX); | |
6403 | bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); | |
6404 | bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; | |
6405 | bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; | |
6406 | bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; | |
6407 | bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), | |
6408 | fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, | |
6409 | fp); | |
6410 | ||
6411 | DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); | |
6412 | ||
6413 | /* qZone id equals to FW (per path) client id */ | |
6414 | bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); | |
6415 | /* init shortcut */ | |
6416 | bnx2x_fcoe(bp, ustorm_rx_prods_offset) = | |
6417 | bnx2x_rx_ustorm_prods_offset(fp); | |
6418 | ||
6419 | /* Configure Queue State object */ | |
6420 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
6421 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6422 | ||
6423 | /* No multi-CoS for FCoE L2 client */ | |
6424 | BUG_ON(fp->max_cos != 1); | |
6425 | ||
6426 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, | |
6427 | &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6428 | bnx2x_sp_mapping(bp, q_rdata), q_type); | |
6429 | ||
6430 | DP(NETIF_MSG_IFUP, | |
6431 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
6432 | fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
6433 | fp->igu_sb_id); | |
6434 | } | |
6435 | ||
55c11941 | 6436 | void bnx2x_nic_init_cnic(struct bnx2x *bp) |
a2fbb9ea | 6437 | { |
ec6ba945 VZ |
6438 | if (!NO_FCOE(bp)) |
6439 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
6440 | |
6441 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
6442 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 6443 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 6444 | |
55c11941 MS |
6445 | /* ensure status block indices were read */ |
6446 | rmb(); | |
6447 | bnx2x_init_rx_rings_cnic(bp); | |
6448 | bnx2x_init_tx_rings_cnic(bp); | |
6449 | ||
6450 | /* flush all */ | |
6451 | mb(); | |
6452 | mmiowb(); | |
6453 | } | |
a2fbb9ea | 6454 | |
ecf01c22 | 6455 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp) |
55c11941 MS |
6456 | { |
6457 | int i; | |
6458 | ||
ecf01c22 | 6459 | /* Setup NIC internals and enable interrupts */ |
55c11941 MS |
6460 | for_each_eth_queue(bp, i) |
6461 | bnx2x_init_eth_fp(bp, i); | |
ad5afc89 AE |
6462 | |
6463 | /* ensure status block indices were read */ | |
6464 | rmb(); | |
6465 | bnx2x_init_rx_rings(bp); | |
6466 | bnx2x_init_tx_rings(bp); | |
6467 | ||
ecf01c22 YM |
6468 | if (IS_PF(bp)) { |
6469 | /* Initialize MOD_ABS interrupts */ | |
6470 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
6471 | bp->common.shmem_base, | |
6472 | bp->common.shmem2_base, BP_PORT(bp)); | |
ad5afc89 | 6473 | |
ecf01c22 YM |
6474 | /* initialize the default status block and sp ring */ |
6475 | bnx2x_init_def_sb(bp); | |
6476 | bnx2x_update_dsb_idx(bp); | |
6477 | bnx2x_init_sp_ring(bp); | |
3cdeec22 YM |
6478 | } else { |
6479 | bnx2x_memset_stats(bp); | |
ecf01c22 YM |
6480 | } |
6481 | } | |
16119785 | 6482 | |
ecf01c22 YM |
6483 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) |
6484 | { | |
523224a3 | 6485 | bnx2x_init_eq_ring(bp); |
471de716 | 6486 | bnx2x_init_internal(bp, load_code); |
523224a3 | 6487 | bnx2x_pf_init(bp); |
0ef00459 EG |
6488 | bnx2x_stats_init(bp); |
6489 | ||
0ef00459 EG |
6490 | /* flush all before enabling interrupts */ |
6491 | mb(); | |
6492 | mmiowb(); | |
6493 | ||
615f8fd9 | 6494 | bnx2x_int_enable(bp); |
eb8da205 EG |
6495 | |
6496 | /* Check for SPIO5 */ | |
6497 | bnx2x_attn_int_deasserted0(bp, | |
6498 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
6499 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
6500 | } |
6501 | ||
ecf01c22 | 6502 | /* gzip service functions */ |
a2fbb9ea ET |
6503 | static int bnx2x_gunzip_init(struct bnx2x *bp) |
6504 | { | |
1a983142 FT |
6505 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
6506 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
6507 | if (bp->gunzip_buf == NULL) |
6508 | goto gunzip_nomem1; | |
6509 | ||
6510 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
6511 | if (bp->strm == NULL) | |
6512 | goto gunzip_nomem2; | |
6513 | ||
7ab24bfd | 6514 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
6515 | if (bp->strm->workspace == NULL) |
6516 | goto gunzip_nomem3; | |
6517 | ||
6518 | return 0; | |
6519 | ||
6520 | gunzip_nomem3: | |
6521 | kfree(bp->strm); | |
6522 | bp->strm = NULL; | |
6523 | ||
6524 | gunzip_nomem2: | |
1a983142 FT |
6525 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6526 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6527 | bp->gunzip_buf = NULL; |
6528 | ||
6529 | gunzip_nomem1: | |
51c1a580 | 6530 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
a2fbb9ea ET |
6531 | return -ENOMEM; |
6532 | } | |
6533 | ||
6534 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
6535 | { | |
b3b83c3f | 6536 | if (bp->strm) { |
7ab24bfd | 6537 | vfree(bp->strm->workspace); |
b3b83c3f DK |
6538 | kfree(bp->strm); |
6539 | bp->strm = NULL; | |
6540 | } | |
a2fbb9ea ET |
6541 | |
6542 | if (bp->gunzip_buf) { | |
1a983142 FT |
6543 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6544 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6545 | bp->gunzip_buf = NULL; |
6546 | } | |
6547 | } | |
6548 | ||
94a78b79 | 6549 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
6550 | { |
6551 | int n, rc; | |
6552 | ||
6553 | /* check gzip header */ | |
94a78b79 VZ |
6554 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
6555 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 6556 | return -EINVAL; |
94a78b79 | 6557 | } |
a2fbb9ea ET |
6558 | |
6559 | n = 10; | |
6560 | ||
34f80b04 | 6561 | #define FNAME 0x8 |
a2fbb9ea ET |
6562 | |
6563 | if (zbuf[3] & FNAME) | |
6564 | while ((zbuf[n++] != 0) && (n < len)); | |
6565 | ||
94a78b79 | 6566 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
6567 | bp->strm->avail_in = len - n; |
6568 | bp->strm->next_out = bp->gunzip_buf; | |
6569 | bp->strm->avail_out = FW_BUF_SIZE; | |
6570 | ||
6571 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
6572 | if (rc != Z_OK) | |
6573 | return rc; | |
6574 | ||
6575 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
6576 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
6577 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
6578 | bp->strm->msg); | |
a2fbb9ea ET |
6579 | |
6580 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
6581 | if (bp->gunzip_outlen & 0x3) | |
51c1a580 MS |
6582 | netdev_err(bp->dev, |
6583 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", | |
cdaa7cb8 | 6584 | bp->gunzip_outlen); |
a2fbb9ea ET |
6585 | bp->gunzip_outlen >>= 2; |
6586 | ||
6587 | zlib_inflateEnd(bp->strm); | |
6588 | ||
6589 | if (rc == Z_STREAM_END) | |
6590 | return 0; | |
6591 | ||
6592 | return rc; | |
6593 | } | |
6594 | ||
6595 | /* nic load/unload */ | |
6596 | ||
6597 | /* | |
34f80b04 | 6598 | * General service functions |
a2fbb9ea ET |
6599 | */ |
6600 | ||
6601 | /* send a NIG loopback debug packet */ | |
6602 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
6603 | { | |
a2fbb9ea | 6604 | u32 wb_write[3]; |
a2fbb9ea ET |
6605 | |
6606 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
6607 | wb_write[0] = 0x55555555; |
6608 | wb_write[1] = 0x55555555; | |
34f80b04 | 6609 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 6610 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6611 | |
6612 | /* NON-IP protocol */ | |
a2fbb9ea ET |
6613 | wb_write[0] = 0x09000000; |
6614 | wb_write[1] = 0x55555555; | |
34f80b04 | 6615 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 6616 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6617 | } |
6618 | ||
6619 | /* some of the internal memories | |
6620 | * are not directly readable from the driver | |
6621 | * to test them we send debug packets | |
6622 | */ | |
6623 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
6624 | { | |
6625 | int factor; | |
6626 | int count, i; | |
6627 | u32 val = 0; | |
6628 | ||
ad8d3948 | 6629 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 6630 | factor = 120; |
ad8d3948 EG |
6631 | else if (CHIP_REV_IS_EMUL(bp)) |
6632 | factor = 200; | |
6633 | else | |
a2fbb9ea | 6634 | factor = 1; |
a2fbb9ea | 6635 | |
a2fbb9ea ET |
6636 | /* Disable inputs of parser neighbor blocks */ |
6637 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6638 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6639 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6640 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6641 | |
6642 | /* Write 0 to parser credits for CFC search request */ | |
6643 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6644 | ||
6645 | /* send Ethernet packet */ | |
6646 | bnx2x_lb_pckt(bp); | |
6647 | ||
6648 | /* TODO do i reset NIG statistic? */ | |
6649 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6650 | count = 1000 * factor; | |
6651 | while (count) { | |
34f80b04 | 6652 | |
a2fbb9ea ET |
6653 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6654 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6655 | if (val == 0x10) |
6656 | break; | |
6657 | ||
639d65b8 | 6658 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6659 | count--; |
6660 | } | |
6661 | if (val != 0x10) { | |
6662 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6663 | return -1; | |
6664 | } | |
6665 | ||
6666 | /* Wait until PRS register shows 1 packet */ | |
6667 | count = 1000 * factor; | |
6668 | while (count) { | |
6669 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
6670 | if (val == 1) |
6671 | break; | |
6672 | ||
639d65b8 | 6673 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6674 | count--; |
6675 | } | |
6676 | if (val != 0x1) { | |
6677 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6678 | return -2; | |
6679 | } | |
6680 | ||
6681 | /* Reset and init BRB, PRS */ | |
34f80b04 | 6682 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 6683 | msleep(50); |
34f80b04 | 6684 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 6685 | msleep(50); |
619c5cb6 VZ |
6686 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6687 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
6688 | |
6689 | DP(NETIF_MSG_HW, "part2\n"); | |
6690 | ||
6691 | /* Disable inputs of parser neighbor blocks */ | |
6692 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6693 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6694 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6695 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6696 | |
6697 | /* Write 0 to parser credits for CFC search request */ | |
6698 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6699 | ||
6700 | /* send 10 Ethernet packets */ | |
6701 | for (i = 0; i < 10; i++) | |
6702 | bnx2x_lb_pckt(bp); | |
6703 | ||
6704 | /* Wait until NIG register shows 10 + 1 | |
6705 | packets of size 11*0x10 = 0xb0 */ | |
6706 | count = 1000 * factor; | |
6707 | while (count) { | |
34f80b04 | 6708 | |
a2fbb9ea ET |
6709 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6710 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6711 | if (val == 0xb0) |
6712 | break; | |
6713 | ||
639d65b8 | 6714 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6715 | count--; |
6716 | } | |
6717 | if (val != 0xb0) { | |
6718 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6719 | return -3; | |
6720 | } | |
6721 | ||
6722 | /* Wait until PRS register shows 2 packets */ | |
6723 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6724 | if (val != 2) | |
6725 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6726 | ||
6727 | /* Write 1 to parser credits for CFC search request */ | |
6728 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
6729 | ||
6730 | /* Wait until PRS register shows 3 packets */ | |
6731 | msleep(10 * factor); | |
6732 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6733 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6734 | if (val != 3) | |
6735 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6736 | ||
6737 | /* clear NIG EOP FIFO */ | |
6738 | for (i = 0; i < 11; i++) | |
6739 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
6740 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
6741 | if (val != 1) { | |
6742 | BNX2X_ERR("clear of NIG failed\n"); | |
6743 | return -4; | |
6744 | } | |
6745 | ||
6746 | /* Reset and init BRB, PRS, NIG */ | |
6747 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
6748 | msleep(50); | |
6749 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
6750 | msleep(50); | |
619c5cb6 VZ |
6751 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6752 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
55c11941 MS |
6753 | if (!CNIC_SUPPORT(bp)) |
6754 | /* set NIC mode */ | |
6755 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
a2fbb9ea ET |
6756 | |
6757 | /* Enable inputs of parser neighbor blocks */ | |
6758 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
6759 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
6760 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 6761 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
6762 | |
6763 | DP(NETIF_MSG_HW, "done\n"); | |
6764 | ||
6765 | return 0; /* OK */ | |
6766 | } | |
6767 | ||
4a33bc03 | 6768 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea | 6769 | { |
b343d002 YM |
6770 | u32 val; |
6771 | ||
a2fbb9ea | 6772 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); |
619c5cb6 | 6773 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6774 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
6775 | else | |
6776 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
6777 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
6778 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
6779 | /* |
6780 | * mask read length error interrupts in brb for parser | |
6781 | * (parsing unit and 'checksum and crc' unit) | |
6782 | * these errors are legal (PU reads fixed length and CAC can cause | |
6783 | * read length error on truncated packets) | |
6784 | */ | |
6785 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
6786 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
6787 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
6788 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
6789 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
6790 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
6791 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
6792 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6793 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
6794 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
6795 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
6796 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
6797 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6798 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
6799 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
6800 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
6801 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
6802 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
6803 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 6804 | |
b343d002 YM |
6805 | val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
6806 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | | |
6807 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; | |
6808 | if (!CHIP_IS_E1x(bp)) | |
6809 | val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | | |
6810 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; | |
6811 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); | |
6812 | ||
a2fbb9ea ET |
6813 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
6814 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
6815 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 6816 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
6817 | |
6818 | if (!CHIP_IS_E1x(bp)) | |
6819 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
6820 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
6821 | ||
a2fbb9ea ET |
6822 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
6823 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 6824 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 6825 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
6826 | } |
6827 | ||
81f75bbf EG |
6828 | static void bnx2x_reset_common(struct bnx2x *bp) |
6829 | { | |
619c5cb6 VZ |
6830 | u32 val = 0x1400; |
6831 | ||
81f75bbf EG |
6832 | /* reset_common */ |
6833 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6834 | 0xd3ffff7f); | |
619c5cb6 VZ |
6835 | |
6836 | if (CHIP_IS_E3(bp)) { | |
6837 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6838 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6839 | } | |
6840 | ||
6841 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
6842 | } | |
6843 | ||
6844 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
6845 | { | |
6846 | bp->dmae_ready = 0; | |
6847 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
6848 | } |
6849 | ||
573f2035 EG |
6850 | static void bnx2x_init_pxp(struct bnx2x *bp) |
6851 | { | |
6852 | u16 devctl; | |
6853 | int r_order, w_order; | |
6854 | ||
2a80eebc | 6855 | pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
6856 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
6857 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
6858 | if (bp->mrrs == -1) | |
6859 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
6860 | else { | |
6861 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
6862 | r_order = bp->mrrs; | |
6863 | } | |
6864 | ||
6865 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
6866 | } | |
fd4ef40d EG |
6867 | |
6868 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
6869 | { | |
2145a920 | 6870 | int is_required; |
fd4ef40d | 6871 | u32 val; |
2145a920 | 6872 | int port; |
fd4ef40d | 6873 | |
2145a920 VZ |
6874 | if (BP_NOMCP(bp)) |
6875 | return; | |
6876 | ||
6877 | is_required = 0; | |
fd4ef40d EG |
6878 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
6879 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
6880 | ||
6881 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
6882 | is_required = 1; | |
6883 | ||
6884 | /* | |
6885 | * The fan failure mechanism is usually related to the PHY type since | |
6886 | * the power consumption of the board is affected by the PHY. Currently, | |
6887 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
6888 | */ | |
6889 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
6890 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 6891 | is_required |= |
d90d96ba YR |
6892 | bnx2x_fan_failure_det_req( |
6893 | bp, | |
6894 | bp->common.shmem_base, | |
a22f0788 | 6895 | bp->common.shmem2_base, |
d90d96ba | 6896 | port); |
fd4ef40d EG |
6897 | } |
6898 | ||
6899 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
6900 | ||
6901 | if (is_required == 0) | |
6902 | return; | |
6903 | ||
6904 | /* Fan failure is indicated by SPIO 5 */ | |
d6d99a3f | 6905 | bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); |
fd4ef40d EG |
6906 | |
6907 | /* set to active low mode */ | |
6908 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
d6d99a3f | 6909 | val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
6910 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
6911 | ||
6912 | /* enable interrupt to signal the IGU */ | |
6913 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 6914 | val |= MISC_SPIO_SPIO5; |
fd4ef40d EG |
6915 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); |
6916 | } | |
6917 | ||
c9ee9206 | 6918 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
6919 | { |
6920 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
6921 | val &= ~IGU_PF_CONF_FUNC_EN; | |
6922 | ||
6923 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
6924 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6925 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
6926 | } | |
6927 | ||
1191cb83 | 6928 | static void bnx2x__common_init_phy(struct bnx2x *bp) |
619c5cb6 VZ |
6929 | { |
6930 | u32 shmem_base[2], shmem2_base[2]; | |
b884d95b YR |
6931 | /* Avoid common init in case MFW supports LFA */ |
6932 | if (SHMEM2_RD(bp, size) > | |
6933 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
6934 | return; | |
619c5cb6 VZ |
6935 | shmem_base[0] = bp->common.shmem_base; |
6936 | shmem2_base[0] = bp->common.shmem2_base; | |
6937 | if (!CHIP_IS_E1x(bp)) { | |
6938 | shmem_base[1] = | |
6939 | SHMEM2_RD(bp, other_shmem_base_addr); | |
6940 | shmem2_base[1] = | |
6941 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
6942 | } | |
6943 | bnx2x_acquire_phy_lock(bp); | |
6944 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
6945 | bp->common.chip_id); | |
6946 | bnx2x_release_phy_lock(bp); | |
6947 | } | |
6948 | ||
04860eb7 MC |
6949 | static void bnx2x_config_endianity(struct bnx2x *bp, u32 val) |
6950 | { | |
6951 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); | |
6952 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); | |
6953 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); | |
6954 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); | |
6955 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); | |
6956 | ||
6957 | /* make sure this value is 0 */ | |
6958 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
6959 | ||
6960 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); | |
6961 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); | |
6962 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); | |
6963 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); | |
6964 | } | |
6965 | ||
6966 | static void bnx2x_set_endianity(struct bnx2x *bp) | |
6967 | { | |
6968 | #ifdef __BIG_ENDIAN | |
6969 | bnx2x_config_endianity(bp, 1); | |
6970 | #else | |
6971 | bnx2x_config_endianity(bp, 0); | |
6972 | #endif | |
6973 | } | |
6974 | ||
6975 | static void bnx2x_reset_endianity(struct bnx2x *bp) | |
6976 | { | |
6977 | bnx2x_config_endianity(bp, 0); | |
6978 | } | |
6979 | ||
619c5cb6 VZ |
6980 | /** |
6981 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
6982 | * | |
6983 | * @bp: driver handle | |
6984 | */ | |
6985 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 6986 | { |
619c5cb6 | 6987 | u32 val; |
a2fbb9ea | 6988 | |
51c1a580 | 6989 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 6990 | |
2031bd3a | 6991 | /* |
2de67439 | 6992 | * take the RESET lock to protect undi_unload flow from accessing |
2031bd3a DK |
6993 | * registers while we're resetting the chip |
6994 | */ | |
7a06a122 | 6995 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6996 | |
81f75bbf | 6997 | bnx2x_reset_common(bp); |
34f80b04 | 6998 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 6999 | |
619c5cb6 VZ |
7000 | val = 0xfffc; |
7001 | if (CHIP_IS_E3(bp)) { | |
7002 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
7003 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
7004 | } | |
7005 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
7006 | ||
7a06a122 | 7007 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 7008 | |
619c5cb6 | 7009 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 7010 | |
619c5cb6 VZ |
7011 | if (!CHIP_IS_E1x(bp)) { |
7012 | u8 abs_func_id; | |
f2e0899f DK |
7013 | |
7014 | /** | |
7015 | * 4-port mode or 2-port mode we need to turn of master-enable | |
7016 | * for everyone, after that, turn it back on for self. | |
7017 | * so, we disregard multi-function or not, and always disable | |
7018 | * for all functions on the given path, this means 0,2,4,6 for | |
7019 | * path 0 and 1,3,5,7 for path 1 | |
7020 | */ | |
619c5cb6 VZ |
7021 | for (abs_func_id = BP_PATH(bp); |
7022 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
7023 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
7024 | REG_WR(bp, |
7025 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
7026 | 1); | |
7027 | continue; | |
7028 | } | |
7029 | ||
619c5cb6 | 7030 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
7031 | /* clear pf enable */ |
7032 | bnx2x_pf_disable(bp); | |
7033 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
7034 | } | |
7035 | } | |
a2fbb9ea | 7036 | |
619c5cb6 | 7037 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
7038 | if (CHIP_IS_E1(bp)) { |
7039 | /* enable HW interrupt from PXP on USDM overflow | |
7040 | bit 16 on INT_MASK_0 */ | |
7041 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
7042 | } | |
a2fbb9ea | 7043 | |
619c5cb6 | 7044 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 7045 | bnx2x_init_pxp(bp); |
04860eb7 | 7046 | bnx2x_set_endianity(bp); |
523224a3 DK |
7047 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
7048 | ||
34f80b04 EG |
7049 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
7050 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 7051 | |
34f80b04 EG |
7052 | /* let the HW do it's magic ... */ |
7053 | msleep(100); | |
7054 | /* finish PXP init */ | |
7055 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
7056 | if (val != 1) { | |
7057 | BNX2X_ERR("PXP2 CFG failed\n"); | |
7058 | return -EBUSY; | |
7059 | } | |
7060 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
7061 | if (val != 1) { | |
7062 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
7063 | return -EBUSY; | |
7064 | } | |
a2fbb9ea | 7065 | |
f2e0899f DK |
7066 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
7067 | * have entries with value "0" and valid bit on. | |
7068 | * This needs to be done by the first PF that is loaded in a path | |
7069 | * (i.e. common phase) | |
7070 | */ | |
619c5cb6 VZ |
7071 | if (!CHIP_IS_E1x(bp)) { |
7072 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
7073 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
7074 | * This occurs when a different function (func2,3) is being marked | |
7075 | * as "scan-off". Real-life scenario for example: if a driver is being | |
7076 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
7077 | * the ilt, translate to a logical address and send a request to read/write. | |
7078 | * Since the ilt for the function that is down is not valid, this will cause | |
7079 | * a translation error which is unrecoverable. | |
7080 | * The Workaround is intended to make sure that when this happens nothing fatal | |
7081 | * will occur. The workaround: | |
7082 | * 1. First PF driver which loads on a path will: | |
7083 | * a. After taking the chip out of reset, by using pretend, | |
7084 | * it will write "0" to the following registers of | |
7085 | * the other vnics. | |
7086 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
7087 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
7088 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
7089 | * And for itself it will write '1' to | |
7090 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
7091 | * dmae-operations (writing to pram for example.) | |
7092 | * note: can be done for only function 6,7 but cleaner this | |
7093 | * way. | |
7094 | * b. Write zero+valid to the entire ILT. | |
7095 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
7096 | * VNIC3 (of that port). The range allocated will be the | |
7097 | * entire ILT. This is needed to prevent ILT range error. | |
7098 | * 2. Any PF driver load flow: | |
7099 | * a. ILT update with the physical addresses of the allocated | |
7100 | * logical pages. | |
7101 | * b. Wait 20msec. - note that this timeout is needed to make | |
7102 | * sure there are no requests in one of the PXP internal | |
7103 | * queues with "old" ILT addresses. | |
7104 | * c. PF enable in the PGLC. | |
7105 | * d. Clear the was_error of the PF in the PGLC. (could have | |
2de67439 | 7106 | * occurred while driver was down) |
619c5cb6 VZ |
7107 | * e. PF enable in the CFC (WEAK + STRONG) |
7108 | * f. Timers scan enable | |
7109 | * 3. PF driver unload flow: | |
7110 | * a. Clear the Timers scan_en. | |
7111 | * b. Polling for scan_on=0 for that PF. | |
7112 | * c. Clear the PF enable bit in the PXP. | |
7113 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
7114 | * e. Write zero+valid to all ILT entries (The valid bit must | |
7115 | * stay set) | |
7116 | * f. If this is VNIC 3 of a port then also init | |
7117 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
16a5fd92 | 7118 | * to the last entry in the ILT. |
619c5cb6 VZ |
7119 | * |
7120 | * Notes: | |
7121 | * Currently the PF error in the PGLC is non recoverable. | |
7122 | * In the future the there will be a recovery routine for this error. | |
7123 | * Currently attention is masked. | |
7124 | * Having an MCP lock on the load/unload process does not guarantee that | |
7125 | * there is no Timer disable during Func6/7 enable. This is because the | |
7126 | * Timers scan is currently being cleared by the MCP on FLR. | |
7127 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
7128 | * there is error before clearing it. But the flow above is simpler and | |
7129 | * more general. | |
7130 | * All ILT entries are written by zero+valid and not just PF6/7 | |
7131 | * ILT entries since in the future the ILT entries allocation for | |
7132 | * PF-s might be dynamic. | |
7133 | */ | |
f2e0899f DK |
7134 | struct ilt_client_info ilt_cli; |
7135 | struct bnx2x_ilt ilt; | |
7136 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
7137 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
7138 | ||
b595076a | 7139 | /* initialize dummy TM client */ |
f2e0899f DK |
7140 | ilt_cli.start = 0; |
7141 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
7142 | ilt_cli.client_num = ILT_CLIENT_TM; | |
7143 | ||
7144 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
7145 | * Step 2: set the timers first/last ilt entry to point | |
7146 | * to the entire range to prevent ILT range error for 3rd/4th | |
2de67439 | 7147 | * vnic (this code assumes existence of the vnic) |
f2e0899f DK |
7148 | * |
7149 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
7150 | * with dummy TM client | |
7151 | * | |
7152 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
7153 | * and his brother are split registers | |
7154 | */ | |
7155 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
7156 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
7157 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
7158 | ||
7159 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
7160 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
7161 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
7162 | } | |
7163 | ||
34f80b04 EG |
7164 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
7165 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 7166 | |
619c5cb6 | 7167 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7168 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
7169 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 7170 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 7171 | |
619c5cb6 | 7172 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
7173 | |
7174 | /* let the HW do it's magic ... */ | |
7175 | do { | |
7176 | msleep(200); | |
7177 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
7178 | } while (factor-- && (val != 1)); | |
7179 | ||
7180 | if (val != 1) { | |
7181 | BNX2X_ERR("ATC_INIT failed\n"); | |
7182 | return -EBUSY; | |
7183 | } | |
7184 | } | |
7185 | ||
619c5cb6 | 7186 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 7187 | |
b56e9670 AE |
7188 | bnx2x_iov_init_dmae(bp); |
7189 | ||
34f80b04 EG |
7190 | /* clean the DMAE memory */ |
7191 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
7192 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
7193 | ||
7194 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
7195 | ||
7196 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
7197 | ||
7198 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 7199 | |
619c5cb6 | 7200 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 7201 | |
34f80b04 EG |
7202 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
7203 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
7204 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
7205 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
7206 | ||
619c5cb6 | 7207 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 7208 | |
523224a3 DK |
7209 | /* QM queues pointers table */ |
7210 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
7211 | ||
34f80b04 EG |
7212 | /* soft reset pulse */ |
7213 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
7214 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 7215 | |
55c11941 MS |
7216 | if (CNIC_SUPPORT(bp)) |
7217 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); | |
a2fbb9ea | 7218 | |
619c5cb6 | 7219 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
b9871bcf | 7220 | |
619c5cb6 | 7221 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
7222 | /* enable hw interrupt from doorbell Q */ |
7223 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 7224 | |
619c5cb6 | 7225 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 7226 | |
619c5cb6 | 7227 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 7228 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 7229 | |
f2e0899f | 7230 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 7231 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 7232 | |
a3348722 BW |
7233 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { |
7234 | if (IS_MF_AFEX(bp)) { | |
7235 | /* configure that VNTag and VLAN headers must be | |
7236 | * received in afex mode | |
7237 | */ | |
7238 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); | |
7239 | REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); | |
7240 | REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); | |
7241 | REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); | |
7242 | REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); | |
7243 | } else { | |
7244 | /* Bit-map indicating which L2 hdrs may appear | |
7245 | * after the basic Ethernet header | |
7246 | */ | |
7247 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
7248 | bp->path_has_ovlan ? 7 : 6); | |
7249 | } | |
7250 | } | |
a2fbb9ea | 7251 | |
619c5cb6 VZ |
7252 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
7253 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
7254 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
7255 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 7256 | |
619c5cb6 VZ |
7257 | if (!CHIP_IS_E1x(bp)) { |
7258 | /* reset VFC memories */ | |
7259 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
7260 | VFC_MEMORIES_RST_REG_CAM_RST | | |
7261 | VFC_MEMORIES_RST_REG_RAM_RST); | |
7262 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
7263 | VFC_MEMORIES_RST_REG_CAM_RST | | |
7264 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 7265 | |
619c5cb6 VZ |
7266 | msleep(20); |
7267 | } | |
a2fbb9ea | 7268 | |
619c5cb6 VZ |
7269 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
7270 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
7271 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
7272 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 7273 | |
34f80b04 EG |
7274 | /* sync semi rtc */ |
7275 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
7276 | 0x80000000); | |
7277 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
7278 | 0x80000000); | |
a2fbb9ea | 7279 | |
619c5cb6 VZ |
7280 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
7281 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
7282 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 7283 | |
a3348722 BW |
7284 | if (!CHIP_IS_E1x(bp)) { |
7285 | if (IS_MF_AFEX(bp)) { | |
7286 | /* configure that VNTag and VLAN headers must be | |
7287 | * sent in afex mode | |
7288 | */ | |
7289 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); | |
7290 | REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); | |
7291 | REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); | |
7292 | REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); | |
7293 | REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); | |
7294 | } else { | |
7295 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
7296 | bp->path_has_ovlan ? 7 : 6); | |
7297 | } | |
7298 | } | |
f2e0899f | 7299 | |
34f80b04 | 7300 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 7301 | |
619c5cb6 VZ |
7302 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
7303 | ||
55c11941 MS |
7304 | if (CNIC_SUPPORT(bp)) { |
7305 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
7306 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
7307 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
7308 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
7309 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
7310 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
7311 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
7312 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
7313 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
7314 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
7315 | } | |
34f80b04 | 7316 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 7317 | |
34f80b04 EG |
7318 | if (sizeof(union cdu_context) != 1024) |
7319 | /* we currently assume that a context is 1024 bytes */ | |
51c1a580 MS |
7320 | dev_alert(&bp->pdev->dev, |
7321 | "please adjust the size of cdu_context(%ld)\n", | |
7322 | (long)sizeof(union cdu_context)); | |
a2fbb9ea | 7323 | |
619c5cb6 | 7324 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
7325 | val = (4 << 24) + (0 << 12) + 1024; |
7326 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 7327 | |
619c5cb6 | 7328 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 7329 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
7330 | /* enable context validation interrupt from CFC */ |
7331 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
7332 | ||
7333 | /* set the thresholds to prevent CFC/CDU race */ | |
7334 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 7335 | |
619c5cb6 | 7336 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 7337 | |
619c5cb6 | 7338 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
7339 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
7340 | ||
619c5cb6 VZ |
7341 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
7342 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 7343 | |
34f80b04 EG |
7344 | /* Reset PCIE errors for debug */ |
7345 | REG_WR(bp, 0x2814, 0xffffffff); | |
7346 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 7347 | |
619c5cb6 | 7348 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7349 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
7350 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
7351 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
7352 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
7353 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
7354 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
7355 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
7356 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
7357 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
7358 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
7359 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
7360 | } | |
7361 | ||
619c5cb6 | 7362 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 7363 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
7364 | /* in E3 this done in per-port section */ |
7365 | if (!CHIP_IS_E3(bp)) | |
7366 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 7367 | } |
619c5cb6 VZ |
7368 | if (CHIP_IS_E1H(bp)) |
7369 | /* not applicable for E2 (and above ...) */ | |
7370 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
7371 | |
7372 | if (CHIP_REV_IS_SLOW(bp)) | |
7373 | msleep(200); | |
7374 | ||
7375 | /* finish CFC init */ | |
7376 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
7377 | if (val != 1) { | |
7378 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
7379 | return -EBUSY; | |
7380 | } | |
7381 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
7382 | if (val != 1) { | |
7383 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
7384 | return -EBUSY; | |
7385 | } | |
7386 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
7387 | if (val != 1) { | |
7388 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
7389 | return -EBUSY; | |
7390 | } | |
7391 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 7392 | |
f2e0899f DK |
7393 | if (CHIP_IS_E1(bp)) { |
7394 | /* read NIG statistic | |
7395 | to see if this is our first up since powerup */ | |
7396 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
7397 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 7398 | |
f2e0899f DK |
7399 | /* do internal memory self test */ |
7400 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
7401 | BNX2X_ERR("internal mem self test failed\n"); | |
7402 | return -EBUSY; | |
7403 | } | |
34f80b04 EG |
7404 | } |
7405 | ||
fd4ef40d EG |
7406 | bnx2x_setup_fan_failure_detection(bp); |
7407 | ||
34f80b04 EG |
7408 | /* clear PXP2 attentions */ |
7409 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 7410 | |
4a33bc03 | 7411 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 7412 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 7413 | |
6bbca910 | 7414 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
7415 | if (CHIP_IS_E1x(bp)) |
7416 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
7417 | } else |
7418 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
7419 | ||
34f80b04 EG |
7420 | return 0; |
7421 | } | |
a2fbb9ea | 7422 | |
619c5cb6 VZ |
7423 | /** |
7424 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
7425 | * | |
7426 | * @bp: driver handle | |
7427 | */ | |
7428 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
7429 | { | |
7430 | int rc = bnx2x_init_hw_common(bp); | |
7431 | ||
7432 | if (rc) | |
7433 | return rc; | |
7434 | ||
7435 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
7436 | if (!BP_NOMCP(bp)) | |
7437 | bnx2x__common_init_phy(bp); | |
7438 | ||
7439 | return 0; | |
7440 | } | |
7441 | ||
523224a3 | 7442 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
7443 | { |
7444 | int port = BP_PORT(bp); | |
619c5cb6 | 7445 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 7446 | u32 low, high; |
4293b9f5 | 7447 | u32 val, reg; |
a2fbb9ea | 7448 | |
51c1a580 | 7449 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
34f80b04 EG |
7450 | |
7451 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 7452 | |
619c5cb6 VZ |
7453 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
7454 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
7455 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 7456 | |
f2e0899f DK |
7457 | /* Timers bug workaround: disables the pf_master bit in pglue at |
7458 | * common phase, we need to enable it here before any dmae access are | |
7459 | * attempted. Therefore we manually added the enable-master to the | |
7460 | * port phase (it also happens in the function phase) | |
7461 | */ | |
619c5cb6 | 7462 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7463 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
7464 | ||
619c5cb6 VZ |
7465 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7466 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7467 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
7468 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7469 | ||
7470 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7471 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7472 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7473 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 7474 | |
523224a3 DK |
7475 | /* QM cid (connection) count */ |
7476 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 7477 | |
55c11941 MS |
7478 | if (CNIC_SUPPORT(bp)) { |
7479 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7480 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); | |
7481 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
7482 | } | |
cdaa7cb8 | 7483 | |
619c5cb6 | 7484 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f | 7485 | |
2b674047 DK |
7486 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
7487 | ||
f2e0899f | 7488 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { |
619c5cb6 VZ |
7489 | |
7490 | if (IS_MF(bp)) | |
7491 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
7492 | else if (bp->dev->mtu > 4096) { | |
7493 | if (bp->flags & ONE_PORT_FLAG) | |
7494 | low = 160; | |
7495 | else { | |
7496 | val = bp->dev->mtu; | |
7497 | /* (24*1024 + val*4)/256 */ | |
7498 | low = 96 + (val/64) + | |
7499 | ((val % 64) ? 1 : 0); | |
7500 | } | |
7501 | } else | |
7502 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
7503 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
7504 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
7505 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 7506 | } |
1c06328c | 7507 | |
619c5cb6 VZ |
7508 | if (CHIP_MODE_IS_4_PORT(bp)) |
7509 | REG_WR(bp, (BP_PORT(bp) ? | |
7510 | BRB1_REG_MAC_GUARANTIED_1 : | |
7511 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 7512 | |
619c5cb6 | 7513 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
a3348722 BW |
7514 | if (CHIP_IS_E3B0(bp)) { |
7515 | if (IS_MF_AFEX(bp)) { | |
7516 | /* configure headers for AFEX mode */ | |
7517 | REG_WR(bp, BP_PORT(bp) ? | |
7518 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7519 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); | |
7520 | REG_WR(bp, BP_PORT(bp) ? | |
7521 | PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : | |
7522 | PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); | |
7523 | REG_WR(bp, BP_PORT(bp) ? | |
7524 | PRS_REG_MUST_HAVE_HDRS_PORT_1 : | |
7525 | PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); | |
7526 | } else { | |
7527 | /* Ovlan exists only if we are in multi-function + | |
7528 | * switch-dependent mode, in switch-independent there | |
7529 | * is no ovlan headers | |
7530 | */ | |
7531 | REG_WR(bp, BP_PORT(bp) ? | |
7532 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7533 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
7534 | (bp->path_has_ovlan ? 7 : 6)); | |
7535 | } | |
7536 | } | |
356e2385 | 7537 | |
619c5cb6 VZ |
7538 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
7539 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7540 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7541 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 7542 | |
619c5cb6 VZ |
7543 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
7544 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7545 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7546 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 7547 | |
619c5cb6 VZ |
7548 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
7549 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 7550 | |
619c5cb6 VZ |
7551 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
7552 | ||
7553 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
7554 | /* configure PBF to work without PAUSE mtu 9000 */ |
7555 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 7556 | |
f2e0899f DK |
7557 | /* update threshold */ |
7558 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
7559 | /* update init credit */ | |
7560 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 7561 | |
f2e0899f DK |
7562 | /* probe changes */ |
7563 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
7564 | udelay(50); | |
7565 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
7566 | } | |
a2fbb9ea | 7567 | |
55c11941 MS |
7568 | if (CNIC_SUPPORT(bp)) |
7569 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7570 | ||
619c5cb6 VZ |
7571 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
7572 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
7573 | |
7574 | if (CHIP_IS_E1(bp)) { | |
7575 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7576 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7577 | } | |
619c5cb6 | 7578 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 7579 | |
619c5cb6 | 7580 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7581 | |
619c5cb6 | 7582 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 | 7583 | /* init aeu_mask_attn_func_0/1: |
16a5fd92 YM |
7584 | * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use |
7585 | * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF | |
34f80b04 | 7586 | * bits 4-7 are used for "per vn group attention" */ |
e4901dde VZ |
7587 | val = IS_MF(bp) ? 0xF7 : 0x7; |
7588 | /* Enable DCBX attention for all but E1 */ | |
7589 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
7590 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 7591 | |
4293b9f5 DK |
7592 | /* SCPAD_PARITY should NOT trigger close the gates */ |
7593 | reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0; | |
7594 | REG_WR(bp, reg, | |
7595 | REG_RD(bp, reg) & | |
7596 | ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); | |
7597 | ||
7598 | reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0; | |
7599 | REG_WR(bp, reg, | |
7600 | REG_RD(bp, reg) & | |
7601 | ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); | |
7602 | ||
619c5cb6 VZ |
7603 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
7604 | ||
7605 | if (!CHIP_IS_E1x(bp)) { | |
7606 | /* Bit-map indicating which L2 hdrs may appear after the | |
7607 | * basic Ethernet header | |
7608 | */ | |
a3348722 BW |
7609 | if (IS_MF_AFEX(bp)) |
7610 | REG_WR(bp, BP_PORT(bp) ? | |
7611 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7612 | NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); | |
7613 | else | |
7614 | REG_WR(bp, BP_PORT(bp) ? | |
7615 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7616 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
7617 | IS_MF_SD(bp) ? 7 : 6); | |
619c5cb6 VZ |
7618 | |
7619 | if (CHIP_IS_E3(bp)) | |
7620 | REG_WR(bp, BP_PORT(bp) ? | |
7621 | NIG_REG_LLH1_MF_MODE : | |
7622 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
7623 | } | |
7624 | if (!CHIP_IS_E3(bp)) | |
7625 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 7626 | |
f2e0899f | 7627 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 7628 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 7629 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 7630 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 7631 | |
619c5cb6 | 7632 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7633 | val = 0; |
7634 | switch (bp->mf_mode) { | |
7635 | case MULTI_FUNCTION_SD: | |
7636 | val = 1; | |
7637 | break; | |
7638 | case MULTI_FUNCTION_SI: | |
a3348722 | 7639 | case MULTI_FUNCTION_AFEX: |
f2e0899f DK |
7640 | val = 2; |
7641 | break; | |
7642 | } | |
7643 | ||
7644 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
7645 | NIG_REG_LLH0_CLS_TYPE), val); | |
7646 | } | |
1c06328c EG |
7647 | { |
7648 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
7649 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
7650 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
7651 | } | |
34f80b04 EG |
7652 | } |
7653 | ||
619c5cb6 VZ |
7654 | /* If SPIO5 is set to generate interrupts, enable it for this port */ |
7655 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 7656 | if (val & MISC_SPIO_SPIO5) { |
4d295db0 EG |
7657 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
7658 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
7659 | val = REG_RD(bp, reg_addr); | |
f1410647 | 7660 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 7661 | REG_WR(bp, reg_addr, val); |
f1410647 | 7662 | } |
a2fbb9ea | 7663 | |
34f80b04 EG |
7664 | return 0; |
7665 | } | |
7666 | ||
34f80b04 EG |
7667 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
7668 | { | |
7669 | int reg; | |
32d68de1 | 7670 | u32 wb_write[2]; |
34f80b04 | 7671 | |
f2e0899f | 7672 | if (CHIP_IS_E1(bp)) |
34f80b04 | 7673 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
7674 | else |
7675 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 | 7676 | |
32d68de1 YM |
7677 | wb_write[0] = ONCHIP_ADDR1(addr); |
7678 | wb_write[1] = ONCHIP_ADDR2(addr); | |
7679 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
34f80b04 EG |
7680 | } |
7681 | ||
b56e9670 | 7682 | void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) |
1191cb83 ED |
7683 | { |
7684 | u32 data, ctl, cnt = 100; | |
7685 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
7686 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
7687 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
7688 | u32 sb_bit = 1 << (idu_sb_id%32); | |
b56e9670 | 7689 | u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; |
1191cb83 ED |
7690 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; |
7691 | ||
7692 | /* Not supported in BC mode */ | |
7693 | if (CHIP_INT_MODE_IS_BC(bp)) | |
7694 | return; | |
7695 | ||
7696 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
7697 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
7698 | IGU_REGULAR_CLEANUP_SET | | |
7699 | IGU_REGULAR_BCLEANUP; | |
7700 | ||
7701 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
7702 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
7703 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
7704 | ||
7705 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7706 | data, igu_addr_data); | |
7707 | REG_WR(bp, igu_addr_data, data); | |
7708 | mmiowb(); | |
7709 | barrier(); | |
7710 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7711 | ctl, igu_addr_ctl); | |
7712 | REG_WR(bp, igu_addr_ctl, ctl); | |
7713 | mmiowb(); | |
7714 | barrier(); | |
7715 | ||
7716 | /* wait for clean up to finish */ | |
7717 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
7718 | msleep(20); | |
7719 | ||
1191cb83 ED |
7720 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { |
7721 | DP(NETIF_MSG_HW, | |
7722 | "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
7723 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
7724 | } | |
7725 | } | |
7726 | ||
7727 | static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) | |
f2e0899f | 7728 | { |
619c5cb6 | 7729 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
7730 | } |
7731 | ||
1191cb83 | 7732 | static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) |
f2e0899f DK |
7733 | { |
7734 | u32 i, base = FUNC_ILT_BASE(func); | |
7735 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
7736 | bnx2x_ilt_wr(bp, i, 0); | |
7737 | } | |
7738 | ||
910cc727 | 7739 | static void bnx2x_init_searcher(struct bnx2x *bp) |
55c11941 MS |
7740 | { |
7741 | int port = BP_PORT(bp); | |
7742 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
7743 | /* T1 hash bits value determines the T1 number of entries */ | |
7744 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
7745 | } | |
7746 | ||
7747 | static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) | |
7748 | { | |
7749 | int rc; | |
7750 | struct bnx2x_func_state_params func_params = {NULL}; | |
7751 | struct bnx2x_func_switch_update_params *switch_update_params = | |
7752 | &func_params.params.switch_update; | |
7753 | ||
7754 | /* Prepare parameters for function state transitions */ | |
7755 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7756 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
7757 | ||
7758 | func_params.f_obj = &bp->func_obj; | |
7759 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
7760 | ||
7761 | /* Function parameters */ | |
e42780b6 DK |
7762 | __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, |
7763 | &switch_update_params->changes); | |
7764 | if (suspend) | |
7765 | __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND, | |
7766 | &switch_update_params->changes); | |
55c11941 MS |
7767 | |
7768 | rc = bnx2x_func_state_change(bp, &func_params); | |
7769 | ||
7770 | return rc; | |
7771 | } | |
7772 | ||
910cc727 | 7773 | static int bnx2x_reset_nic_mode(struct bnx2x *bp) |
55c11941 MS |
7774 | { |
7775 | int rc, i, port = BP_PORT(bp); | |
7776 | int vlan_en = 0, mac_en[NUM_MACS]; | |
7777 | ||
55c11941 MS |
7778 | /* Close input from network */ |
7779 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7780 | bnx2x_set_rx_filter(&bp->link_params, 0); | |
7781 | } else { | |
7782 | vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7783 | NIG_REG_LLH0_FUNC_EN); | |
7784 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7785 | NIG_REG_LLH0_FUNC_EN, 0); | |
7786 | for (i = 0; i < NUM_MACS; i++) { | |
7787 | mac_en[i] = REG_RD(bp, port ? | |
7788 | (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7789 | 4 * i) : | |
7790 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + | |
7791 | 4 * i)); | |
7792 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7793 | 4 * i) : | |
7794 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); | |
7795 | } | |
7796 | } | |
7797 | ||
7798 | /* Close BMC to host */ | |
7799 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7800 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); | |
7801 | ||
7802 | /* Suspend Tx switching to the PF. Completion of this ramrod | |
7803 | * further guarantees that all the packets of that PF / child | |
7804 | * VFs in BRB were processed by the Parser, so it is safe to | |
7805 | * change the NIC_MODE register. | |
7806 | */ | |
7807 | rc = bnx2x_func_switch_update(bp, 1); | |
7808 | if (rc) { | |
7809 | BNX2X_ERR("Can't suspend tx-switching!\n"); | |
7810 | return rc; | |
7811 | } | |
7812 | ||
7813 | /* Change NIC_MODE register */ | |
7814 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7815 | ||
7816 | /* Open input from network */ | |
7817 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7818 | bnx2x_set_rx_filter(&bp->link_params, 1); | |
7819 | } else { | |
7820 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7821 | NIG_REG_LLH0_FUNC_EN, vlan_en); | |
7822 | for (i = 0; i < NUM_MACS; i++) { | |
7823 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7824 | 4 * i) : | |
7825 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), | |
7826 | mac_en[i]); | |
7827 | } | |
7828 | } | |
7829 | ||
7830 | /* Enable BMC to host */ | |
7831 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7832 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); | |
7833 | ||
7834 | /* Resume Tx switching to the PF */ | |
7835 | rc = bnx2x_func_switch_update(bp, 0); | |
7836 | if (rc) { | |
7837 | BNX2X_ERR("Can't resume tx-switching!\n"); | |
7838 | return rc; | |
7839 | } | |
7840 | ||
7841 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7842 | return 0; | |
7843 | } | |
7844 | ||
7845 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp) | |
7846 | { | |
7847 | int rc; | |
7848 | ||
7849 | bnx2x_ilt_init_op_cnic(bp, INITOP_SET); | |
7850 | ||
7851 | if (CONFIGURE_NIC_MODE(bp)) { | |
16a5fd92 | 7852 | /* Configure searcher as part of function hw init */ |
55c11941 MS |
7853 | bnx2x_init_searcher(bp); |
7854 | ||
7855 | /* Reset NIC mode */ | |
7856 | rc = bnx2x_reset_nic_mode(bp); | |
7857 | if (rc) | |
7858 | BNX2X_ERR("Can't change NIC mode!\n"); | |
7859 | return rc; | |
7860 | } | |
7861 | ||
7862 | return 0; | |
7863 | } | |
7864 | ||
da254fbc YM |
7865 | /* previous driver DMAE transaction may have occurred when pre-boot stage ended |
7866 | * and boot began, or when kdump kernel was loaded. Either case would invalidate | |
7867 | * the addresses of the transaction, resulting in was-error bit set in the pci | |
7868 | * causing all hw-to-host pcie transactions to timeout. If this happened we want | |
7869 | * to clear the interrupt which detected this from the pglueb and the was done | |
7870 | * bit | |
7871 | */ | |
7872 | static void bnx2x_clean_pglue_errors(struct bnx2x *bp) | |
7873 | { | |
7874 | if (!CHIP_IS_E1x(bp)) | |
7875 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, | |
7876 | 1 << BP_ABS_FUNC(bp)); | |
7877 | } | |
7878 | ||
523224a3 | 7879 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
7880 | { |
7881 | int port = BP_PORT(bp); | |
7882 | int func = BP_FUNC(bp); | |
619c5cb6 | 7883 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
7884 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
7885 | u16 cdu_ilt_start; | |
8badd27a | 7886 | u32 addr, val; |
f4a66897 | 7887 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
89db4ad8 | 7888 | int i, main_mem_width, rc; |
34f80b04 | 7889 | |
51c1a580 | 7890 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
34f80b04 | 7891 | |
619c5cb6 | 7892 | /* FLR cleanup - hmmm */ |
89db4ad8 AE |
7893 | if (!CHIP_IS_E1x(bp)) { |
7894 | rc = bnx2x_pf_flr_clnup(bp); | |
04c46736 YM |
7895 | if (rc) { |
7896 | bnx2x_fw_dump(bp); | |
89db4ad8 | 7897 | return rc; |
04c46736 | 7898 | } |
89db4ad8 | 7899 | } |
619c5cb6 | 7900 | |
8badd27a | 7901 | /* set MSI reconfigure capability */ |
f2e0899f DK |
7902 | if (bp->common.int_block == INT_BLOCK_HC) { |
7903 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
7904 | val = REG_RD(bp, addr); | |
7905 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
7906 | REG_WR(bp, addr, val); | |
7907 | } | |
8badd27a | 7908 | |
619c5cb6 VZ |
7909 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
7910 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
7911 | ||
523224a3 DK |
7912 | ilt = BP_ILT(bp); |
7913 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 7914 | |
290ca2bb AE |
7915 | if (IS_SRIOV(bp)) |
7916 | cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; | |
7917 | cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); | |
7918 | ||
7919 | /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes | |
7920 | * those of the VFs, so start line should be reset | |
7921 | */ | |
7922 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
523224a3 | 7923 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
a052997e | 7924 | ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; |
523224a3 | 7925 | ilt->lines[cdu_ilt_start + i].page_mapping = |
a052997e MS |
7926 | bp->context[i].cxt_mapping; |
7927 | ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; | |
37b091ba | 7928 | } |
290ca2bb | 7929 | |
523224a3 | 7930 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 7931 | |
55c11941 MS |
7932 | if (!CONFIGURE_NIC_MODE(bp)) { |
7933 | bnx2x_init_searcher(bp); | |
7934 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7935 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7936 | } else { | |
7937 | /* Set NIC mode */ | |
7938 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6bf07b8e | 7939 | DP(NETIF_MSG_IFUP, "NIC MODE configured\n"); |
55c11941 | 7940 | } |
37b091ba | 7941 | |
619c5cb6 | 7942 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7943 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
7944 | ||
7945 | /* Turn on a single ISR mode in IGU if driver is going to use | |
7946 | * INT#x or MSI | |
7947 | */ | |
7948 | if (!(bp->flags & USING_MSIX_FLAG)) | |
7949 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
7950 | /* | |
7951 | * Timers workaround bug: function init part. | |
7952 | * Need to wait 20msec after initializing ILT, | |
7953 | * needed to make sure there are no requests in | |
7954 | * one of the PXP internal queues with "old" ILT addresses | |
7955 | */ | |
7956 | msleep(20); | |
7957 | /* | |
7958 | * Master enable - Due to WB DMAE writes performed before this | |
7959 | * register is re-initialized as part of the regular function | |
7960 | * init | |
7961 | */ | |
7962 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
7963 | /* Enable the function in IGU */ | |
7964 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
7965 | } | |
7966 | ||
523224a3 | 7967 | bp->dmae_ready = 1; |
34f80b04 | 7968 | |
619c5cb6 | 7969 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 7970 | |
da254fbc | 7971 | bnx2x_clean_pglue_errors(bp); |
f2e0899f | 7972 | |
619c5cb6 VZ |
7973 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7974 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7975 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
7976 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7977 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
7978 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7979 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7980 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7981 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
7982 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
7983 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7984 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7985 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
7986 | ||
7987 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7988 | REG_WR(bp, QM_REG_PF_EN, 1); |
7989 | ||
619c5cb6 VZ |
7990 | if (!CHIP_IS_E1x(bp)) { |
7991 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7992 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7993 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7994 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7995 | } | |
7996 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7997 | ||
7998 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7999 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
c19d65c9 | 8000 | REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ |
b56e9670 AE |
8001 | |
8002 | bnx2x_iov_init_dq(bp); | |
8003 | ||
619c5cb6 VZ |
8004 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
8005 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
8006 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
8007 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
8008 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
8009 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
8010 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
8011 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
8012 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
8013 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
8014 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
8015 | ||
619c5cb6 | 8016 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 8017 | |
619c5cb6 | 8018 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 8019 | |
619c5cb6 | 8020 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
8021 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
8022 | ||
fb3bff17 | 8023 | if (IS_MF(bp)) { |
7609647e YM |
8024 | if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) { |
8025 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); | |
8026 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, | |
8027 | bp->mf_ov); | |
8028 | } | |
34f80b04 EG |
8029 | } |
8030 | ||
619c5cb6 | 8031 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 8032 | |
34f80b04 | 8033 | /* HC init per function */ |
f2e0899f DK |
8034 | if (bp->common.int_block == INT_BLOCK_HC) { |
8035 | if (CHIP_IS_E1H(bp)) { | |
8036 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
8037 | ||
8038 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
8039 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
8040 | } | |
619c5cb6 | 8041 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
8042 | |
8043 | } else { | |
8044 | int num_segs, sb_idx, prod_offset; | |
8045 | ||
34f80b04 EG |
8046 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
8047 | ||
619c5cb6 | 8048 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8049 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
8050 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
8051 | } | |
8052 | ||
619c5cb6 | 8053 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 8054 | |
619c5cb6 | 8055 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8056 | int dsb_idx = 0; |
8057 | /** | |
8058 | * Producer memory: | |
8059 | * E2 mode: address 0-135 match to the mapping memory; | |
8060 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
8061 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
8062 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
8063 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
8064 | * 144-147 reserved. | |
8065 | * | |
8066 | * E1.5 mode - In backward compatible mode; | |
8067 | * for non default SB; each even line in the memory | |
8068 | * holds the U producer and each odd line hold | |
8069 | * the C producer. The first 128 producers are for | |
8070 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
8071 | * producers are for the DSB for each PF. | |
8072 | * Each PF has five segments: (the order inside each | |
8073 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
8074 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
8075 | * 144-147 attn prods; | |
8076 | */ | |
8077 | /* non-default-status-blocks */ | |
8078 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
8079 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
8080 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
8081 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
8082 | num_segs; | |
8083 | ||
8084 | for (i = 0; i < num_segs; i++) { | |
8085 | addr = IGU_REG_PROD_CONS_MEMORY + | |
8086 | (prod_offset + i) * 4; | |
8087 | REG_WR(bp, addr, 0); | |
8088 | } | |
8089 | /* send consumer update with value 0 */ | |
8090 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
8091 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
8092 | bnx2x_igu_clear_sb(bp, | |
8093 | bp->igu_base_sb + sb_idx); | |
8094 | } | |
8095 | ||
8096 | /* default-status-blocks */ | |
8097 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
8098 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
8099 | ||
8100 | if (CHIP_MODE_IS_4_PORT(bp)) | |
8101 | dsb_idx = BP_FUNC(bp); | |
8102 | else | |
3395a033 | 8103 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
8104 | |
8105 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
8106 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
8107 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
8108 | ||
3395a033 DK |
8109 | /* |
8110 | * igu prods come in chunks of E1HVN_MAX (4) - | |
8111 | * does not matters what is the current chip mode | |
8112 | */ | |
f2e0899f DK |
8113 | for (i = 0; i < (num_segs * E1HVN_MAX); |
8114 | i += E1HVN_MAX) { | |
8115 | addr = IGU_REG_PROD_CONS_MEMORY + | |
8116 | (prod_offset + i)*4; | |
8117 | REG_WR(bp, addr, 0); | |
8118 | } | |
8119 | /* send consumer update with 0 */ | |
8120 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
8121 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8122 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
8123 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8124 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
8125 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8126 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
8127 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8128 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
8129 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8130 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
8131 | } else { | |
8132 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8133 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
8134 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8135 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
8136 | } | |
8137 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
8138 | ||
16a5fd92 | 8139 | /* !!! These should become driver const once |
f2e0899f DK |
8140 | rf-tool supports split-68 const */ |
8141 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
8142 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
8143 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
8144 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
8145 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
8146 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
8147 | } | |
34f80b04 | 8148 | } |
34f80b04 | 8149 | |
c14423fe | 8150 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
8151 | REG_WR(bp, 0x2114, 0xffffffff); |
8152 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 8153 | |
f4a66897 VZ |
8154 | if (CHIP_IS_E1x(bp)) { |
8155 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
8156 | main_mem_base = HC_REG_MAIN_MEMORY + | |
8157 | BP_PORT(bp) * (main_mem_size * 4); | |
8158 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
8159 | main_mem_width = 8; | |
8160 | ||
8161 | val = REG_RD(bp, main_mem_prty_clr); | |
8162 | if (val) | |
51c1a580 MS |
8163 | DP(NETIF_MSG_HW, |
8164 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", | |
8165 | val); | |
f4a66897 VZ |
8166 | |
8167 | /* Clear "false" parity errors in MSI-X table */ | |
8168 | for (i = main_mem_base; | |
8169 | i < main_mem_base + main_mem_size * 4; | |
8170 | i += main_mem_width) { | |
8171 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
8172 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
8173 | i, main_mem_width / 4); | |
8174 | } | |
8175 | /* Clear HC parity attention */ | |
8176 | REG_RD(bp, main_mem_prty_clr); | |
8177 | } | |
8178 | ||
619c5cb6 VZ |
8179 | #ifdef BNX2X_STOP_ON_ERROR |
8180 | /* Enable STORMs SP logging */ | |
8181 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
8182 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8183 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
8184 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8185 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
8186 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8187 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
8188 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8189 | #endif | |
8190 | ||
b7737c9b | 8191 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 8192 | |
34f80b04 EG |
8193 | return 0; |
8194 | } | |
8195 | ||
55c11941 MS |
8196 | void bnx2x_free_mem_cnic(struct bnx2x *bp) |
8197 | { | |
8198 | bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); | |
8199 | ||
8200 | if (!CHIP_IS_E1x(bp)) | |
8201 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, | |
8202 | sizeof(struct host_hc_status_block_e2)); | |
8203 | else | |
8204 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
8205 | sizeof(struct host_hc_status_block_e1x)); | |
8206 | ||
8207 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); | |
8208 | } | |
8209 | ||
9f6c9258 | 8210 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 8211 | { |
a052997e MS |
8212 | int i; |
8213 | ||
619c5cb6 VZ |
8214 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
8215 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
8216 | ||
b4cddbd6 AE |
8217 | if (IS_VF(bp)) |
8218 | return; | |
8219 | ||
8220 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
8221 | sizeof(struct host_sp_status_block)); | |
8222 | ||
a2fbb9ea | 8223 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 8224 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 8225 | |
a052997e MS |
8226 | for (i = 0; i < L2_ILT_LINES(bp); i++) |
8227 | BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, | |
8228 | bp->context[i].size); | |
523224a3 DK |
8229 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); |
8230 | ||
8231 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 8232 | |
7a9b2557 | 8233 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 8234 | |
523224a3 DK |
8235 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
8236 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
580d9d08 | 8237 | |
05952246 YM |
8238 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
8239 | ||
580d9d08 | 8240 | bnx2x_iov_free_mem(bp); |
619c5cb6 VZ |
8241 | } |
8242 | ||
55c11941 | 8243 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp) |
a2fbb9ea | 8244 | { |
cd2b0389 | 8245 | if (!CHIP_IS_E1x(bp)) { |
619c5cb6 | 8246 | /* size = the status block + ramrod buffers */ |
cd2b0389 JP |
8247 | bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, |
8248 | sizeof(struct host_hc_status_block_e2)); | |
8249 | if (!bp->cnic_sb.e2_sb) | |
8250 | goto alloc_mem_err; | |
8251 | } else { | |
8252 | bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, | |
8253 | sizeof(struct host_hc_status_block_e1x)); | |
8254 | if (!bp->cnic_sb.e1x_sb) | |
8255 | goto alloc_mem_err; | |
8256 | } | |
8badd27a | 8257 | |
cd2b0389 | 8258 | if (CONFIGURE_NIC_MODE(bp) && !bp->t2) { |
16a5fd92 | 8259 | /* allocate searcher T2 table, as it wasn't allocated before */ |
cd2b0389 JP |
8260 | bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); |
8261 | if (!bp->t2) | |
8262 | goto alloc_mem_err; | |
8263 | } | |
55c11941 MS |
8264 | |
8265 | /* write address to which L5 should insert its values */ | |
8266 | bp->cnic_eth_dev.addr_drv_info_to_mcp = | |
8267 | &bp->slowpath->drv_info_to_mcp; | |
8268 | ||
8269 | if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) | |
8270 | goto alloc_mem_err; | |
8271 | ||
8272 | return 0; | |
8273 | ||
8274 | alloc_mem_err: | |
8275 | bnx2x_free_mem_cnic(bp); | |
8276 | BNX2X_ERR("Can't allocate memory\n"); | |
8277 | return -ENOMEM; | |
8278 | } | |
8279 | ||
8280 | int bnx2x_alloc_mem(struct bnx2x *bp) | |
8281 | { | |
8282 | int i, allocated, context_size; | |
a2fbb9ea | 8283 | |
cd2b0389 | 8284 | if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) { |
55c11941 | 8285 | /* allocate searcher T2 table */ |
cd2b0389 JP |
8286 | bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); |
8287 | if (!bp->t2) | |
8288 | goto alloc_mem_err; | |
8289 | } | |
8badd27a | 8290 | |
cd2b0389 JP |
8291 | bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping, |
8292 | sizeof(struct host_sp_status_block)); | |
8293 | if (!bp->def_status_blk) | |
8294 | goto alloc_mem_err; | |
a2fbb9ea | 8295 | |
cd2b0389 JP |
8296 | bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping, |
8297 | sizeof(struct bnx2x_slowpath)); | |
8298 | if (!bp->slowpath) | |
8299 | goto alloc_mem_err; | |
a2fbb9ea | 8300 | |
a052997e MS |
8301 | /* Allocate memory for CDU context: |
8302 | * This memory is allocated separately and not in the generic ILT | |
8303 | * functions because CDU differs in few aspects: | |
8304 | * 1. There are multiple entities allocating memory for context - | |
8305 | * 'regular' driver, CNIC and SRIOV driver. Each separately controls | |
8306 | * its own ILT lines. | |
8307 | * 2. Since CDU page-size is not a single 4KB page (which is the case | |
8308 | * for the other ILT clients), to be efficient we want to support | |
8309 | * allocation of sub-page-size in the last entry. | |
8310 | * 3. Context pointers are used by the driver to pass to FW / update | |
8311 | * the context (for the other ILT clients the pointers are used just to | |
8312 | * free the memory during unload). | |
8313 | */ | |
8314 | context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); | |
65abd74d | 8315 | |
a052997e MS |
8316 | for (i = 0, allocated = 0; allocated < context_size; i++) { |
8317 | bp->context[i].size = min(CDU_ILT_PAGE_SZ, | |
8318 | (context_size - allocated)); | |
cd2b0389 JP |
8319 | bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping, |
8320 | bp->context[i].size); | |
8321 | if (!bp->context[i].vcxt) | |
8322 | goto alloc_mem_err; | |
a052997e MS |
8323 | allocated += bp->context[i].size; |
8324 | } | |
cd2b0389 JP |
8325 | bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line), |
8326 | GFP_KERNEL); | |
8327 | if (!bp->ilt->lines) | |
8328 | goto alloc_mem_err; | |
65abd74d | 8329 | |
523224a3 DK |
8330 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
8331 | goto alloc_mem_err; | |
65abd74d | 8332 | |
67c431a5 AE |
8333 | if (bnx2x_iov_alloc_mem(bp)) |
8334 | goto alloc_mem_err; | |
8335 | ||
9f6c9258 | 8336 | /* Slow path ring */ |
cd2b0389 JP |
8337 | bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE); |
8338 | if (!bp->spq) | |
8339 | goto alloc_mem_err; | |
65abd74d | 8340 | |
523224a3 | 8341 | /* EQ */ |
cd2b0389 JP |
8342 | bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping, |
8343 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
8344 | if (!bp->eq_ring) | |
8345 | goto alloc_mem_err; | |
ab532cf3 | 8346 | |
9f6c9258 | 8347 | return 0; |
e1510706 | 8348 | |
9f6c9258 DK |
8349 | alloc_mem_err: |
8350 | bnx2x_free_mem(bp); | |
51c1a580 | 8351 | BNX2X_ERR("Can't allocate memory\n"); |
9f6c9258 | 8352 | return -ENOMEM; |
65abd74d YG |
8353 | } |
8354 | ||
a2fbb9ea ET |
8355 | /* |
8356 | * Init service functions | |
8357 | */ | |
a2fbb9ea | 8358 | |
619c5cb6 VZ |
8359 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
8360 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
8361 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 8362 | { |
619c5cb6 VZ |
8363 | int rc; |
8364 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 8365 | |
619c5cb6 | 8366 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 8367 | |
619c5cb6 VZ |
8368 | /* Fill general parameters */ |
8369 | ramrod_param.vlan_mac_obj = obj; | |
8370 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 8371 | |
619c5cb6 VZ |
8372 | /* Fill a user request section if needed */ |
8373 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
8374 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 8375 | |
619c5cb6 | 8376 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 8377 | |
619c5cb6 VZ |
8378 | /* Set the command: ADD or DEL */ |
8379 | if (set) | |
8380 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
8381 | else | |
8382 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
8383 | } |
8384 | ||
619c5cb6 | 8385 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7b5342d9 YM |
8386 | |
8387 | if (rc == -EEXIST) { | |
8388 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); | |
8389 | /* do not treat adding same MAC as error */ | |
8390 | rc = 0; | |
8391 | } else if (rc < 0) | |
619c5cb6 | 8392 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); |
7b5342d9 | 8393 | |
619c5cb6 | 8394 | return rc; |
a2fbb9ea ET |
8395 | } |
8396 | ||
619c5cb6 VZ |
8397 | int bnx2x_del_all_macs(struct bnx2x *bp, |
8398 | struct bnx2x_vlan_mac_obj *mac_obj, | |
8399 | int mac_type, bool wait_for_comp) | |
e665bfda | 8400 | { |
619c5cb6 VZ |
8401 | int rc; |
8402 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 8403 | |
619c5cb6 VZ |
8404 | /* Wait for completion of requested */ |
8405 | if (wait_for_comp) | |
8406 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 8407 | |
619c5cb6 VZ |
8408 | /* Set the mac type of addresses we want to clear */ |
8409 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 8410 | |
619c5cb6 VZ |
8411 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
8412 | if (rc < 0) | |
8413 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 8414 | |
619c5cb6 | 8415 | return rc; |
0793f83f DK |
8416 | } |
8417 | ||
619c5cb6 | 8418 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 8419 | { |
f8f4f61a DK |
8420 | if (IS_PF(bp)) { |
8421 | unsigned long ramrod_flags = 0; | |
0793f83f | 8422 | |
f8f4f61a DK |
8423 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
8424 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
8425 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, | |
8426 | &bp->sp_objs->mac_obj, set, | |
8427 | BNX2X_ETH_MAC, &ramrod_flags); | |
8428 | } else { /* vf */ | |
8429 | return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, | |
8430 | bp->fp->index, true); | |
8431 | } | |
e665bfda | 8432 | } |
6e30dd4e | 8433 | |
619c5cb6 | 8434 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 8435 | { |
60cad4e6 AE |
8436 | if (IS_PF(bp)) |
8437 | return bnx2x_setup_queue(bp, &bp->fp[0], true); | |
8438 | else /* VF */ | |
8439 | return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); | |
993ac7b5 | 8440 | } |
a2fbb9ea | 8441 | |
d6214d7a | 8442 | /** |
e8920674 | 8443 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 8444 | * |
e8920674 | 8445 | * @bp: driver handle |
d6214d7a | 8446 | * |
e8920674 | 8447 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 8448 | */ |
1ab4434c | 8449 | int bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 8450 | { |
1ab4434c AE |
8451 | int rc = 0; |
8452 | ||
60cad4e6 AE |
8453 | if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) { |
8454 | BNX2X_ERR("VF not loaded since interrupt mode not msix\n"); | |
1ab4434c | 8455 | return -EINVAL; |
60cad4e6 | 8456 | } |
1ab4434c | 8457 | |
9ee3d37b | 8458 | switch (int_mode) { |
1ab4434c AE |
8459 | case BNX2X_INT_MODE_MSIX: |
8460 | /* attempt to enable msix */ | |
8461 | rc = bnx2x_enable_msix(bp); | |
8462 | ||
8463 | /* msix attained */ | |
8464 | if (!rc) | |
8465 | return 0; | |
8466 | ||
8467 | /* vfs use only msix */ | |
8468 | if (rc && IS_VF(bp)) | |
8469 | return rc; | |
8470 | ||
8471 | /* failed to enable multiple MSI-X */ | |
8472 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", | |
8473 | bp->num_queues, | |
8474 | 1 + bp->num_cnic_queues); | |
8475 | ||
8476 | /* falling through... */ | |
8477 | case BNX2X_INT_MODE_MSI: | |
d6214d7a | 8478 | bnx2x_enable_msi(bp); |
1ab4434c | 8479 | |
d6214d7a | 8480 | /* falling through... */ |
1ab4434c | 8481 | case BNX2X_INT_MODE_INTX: |
55c11941 MS |
8482 | bp->num_ethernet_queues = 1; |
8483 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; | |
51c1a580 | 8484 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
ca00392c | 8485 | break; |
d6214d7a | 8486 | default: |
1ab4434c AE |
8487 | BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); |
8488 | return -EINVAL; | |
9f6c9258 | 8489 | } |
1ab4434c | 8490 | return 0; |
a2fbb9ea ET |
8491 | } |
8492 | ||
1ab4434c | 8493 | /* must be called prior to any HW initializations */ |
c2bff63f DK |
8494 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) |
8495 | { | |
290ca2bb AE |
8496 | if (IS_SRIOV(bp)) |
8497 | return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; | |
c2bff63f DK |
8498 | return L2_ILT_LINES(bp); |
8499 | } | |
8500 | ||
523224a3 DK |
8501 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
8502 | { | |
8503 | struct ilt_client_info *ilt_client; | |
8504 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
8505 | u16 line = 0; | |
8506 | ||
8507 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
8508 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
8509 | ||
8510 | /* CDU */ | |
8511 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
8512 | ilt_client->client_num = ILT_CLIENT_CDU; | |
8513 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
8514 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
8515 | ilt_client->start = line; | |
619c5cb6 | 8516 | line += bnx2x_cid_ilt_lines(bp); |
55c11941 MS |
8517 | |
8518 | if (CNIC_SUPPORT(bp)) | |
8519 | line += CNIC_ILT_LINES; | |
523224a3 DK |
8520 | ilt_client->end = line - 1; |
8521 | ||
51c1a580 | 8522 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
523224a3 DK |
8523 | ilt_client->start, |
8524 | ilt_client->end, | |
8525 | ilt_client->page_size, | |
8526 | ilt_client->flags, | |
8527 | ilog2(ilt_client->page_size >> 12)); | |
8528 | ||
8529 | /* QM */ | |
8530 | if (QM_INIT(bp->qm_cid_count)) { | |
8531 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
8532 | ilt_client->client_num = ILT_CLIENT_QM; | |
8533 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
8534 | ilt_client->flags = 0; | |
8535 | ilt_client->start = line; | |
8536 | ||
8537 | /* 4 bytes for each cid */ | |
8538 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
8539 | QM_ILT_PAGE_SZ); | |
8540 | ||
8541 | ilt_client->end = line - 1; | |
8542 | ||
51c1a580 MS |
8543 | DP(NETIF_MSG_IFUP, |
8544 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
8545 | ilt_client->start, |
8546 | ilt_client->end, | |
8547 | ilt_client->page_size, | |
8548 | ilt_client->flags, | |
8549 | ilog2(ilt_client->page_size >> 12)); | |
523224a3 | 8550 | } |
523224a3 | 8551 | |
55c11941 MS |
8552 | if (CNIC_SUPPORT(bp)) { |
8553 | /* SRC */ | |
8554 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
8555 | ilt_client->client_num = ILT_CLIENT_SRC; | |
8556 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
8557 | ilt_client->flags = 0; | |
8558 | ilt_client->start = line; | |
8559 | line += SRC_ILT_LINES; | |
8560 | ilt_client->end = line - 1; | |
523224a3 | 8561 | |
55c11941 MS |
8562 | DP(NETIF_MSG_IFUP, |
8563 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8564 | ilt_client->start, | |
8565 | ilt_client->end, | |
8566 | ilt_client->page_size, | |
8567 | ilt_client->flags, | |
8568 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 8569 | |
55c11941 MS |
8570 | /* TM */ |
8571 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
8572 | ilt_client->client_num = ILT_CLIENT_TM; | |
8573 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
8574 | ilt_client->flags = 0; | |
8575 | ilt_client->start = line; | |
8576 | line += TM_ILT_LINES; | |
8577 | ilt_client->end = line - 1; | |
523224a3 | 8578 | |
55c11941 MS |
8579 | DP(NETIF_MSG_IFUP, |
8580 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8581 | ilt_client->start, | |
8582 | ilt_client->end, | |
8583 | ilt_client->page_size, | |
8584 | ilt_client->flags, | |
8585 | ilog2(ilt_client->page_size >> 12)); | |
8586 | } | |
9f6c9258 | 8587 | |
619c5cb6 | 8588 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 8589 | } |
f85582f8 | 8590 | |
619c5cb6 VZ |
8591 | /** |
8592 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
8593 | * | |
8594 | * @bp: driver handle | |
8595 | * @fp: pointer to fastpath | |
8596 | * @init_params: pointer to parameters structure | |
8597 | * | |
8598 | * parameters configured: | |
8599 | * - HC configuration | |
8600 | * - Queue's CDU context | |
8601 | */ | |
1191cb83 | 8602 | static void bnx2x_pf_q_prep_init(struct bnx2x *bp, |
619c5cb6 | 8603 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) |
a2fbb9ea | 8604 | { |
6383c0b3 | 8605 | u8 cos; |
a052997e MS |
8606 | int cxt_index, cxt_offset; |
8607 | ||
619c5cb6 VZ |
8608 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
8609 | if (!IS_FCOE_FP(fp)) { | |
8610 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
8611 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
8612 | ||
16a5fd92 | 8613 | /* If HC is supported, enable host coalescing in the transition |
619c5cb6 VZ |
8614 | * to INIT state. |
8615 | */ | |
8616 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
8617 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
8618 | ||
8619 | /* HC rate */ | |
8620 | init_params->rx.hc_rate = bp->rx_ticks ? | |
8621 | (1000000 / bp->rx_ticks) : 0; | |
8622 | init_params->tx.hc_rate = bp->tx_ticks ? | |
8623 | (1000000 / bp->tx_ticks) : 0; | |
8624 | ||
8625 | /* FW SB ID */ | |
8626 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
8627 | fp->fw_sb_id; | |
8628 | ||
8629 | /* | |
8630 | * CQ index among the SB indices: FCoE clients uses the default | |
8631 | * SB, therefore it's different. | |
8632 | */ | |
6383c0b3 AE |
8633 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
8634 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
8635 | } |
8636 | ||
6383c0b3 AE |
8637 | /* set maximum number of COSs supported by this queue */ |
8638 | init_params->max_cos = fp->max_cos; | |
8639 | ||
51c1a580 | 8640 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
8641 | fp->index, init_params->max_cos); |
8642 | ||
8643 | /* set the context pointers queue object */ | |
a052997e | 8644 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { |
65565884 MS |
8645 | cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; |
8646 | cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * | |
a052997e | 8647 | ILT_PAGE_CIDS); |
6383c0b3 | 8648 | init_params->cxts[cos] = |
a052997e MS |
8649 | &bp->context[cxt_index].vcxt[cxt_offset].eth; |
8650 | } | |
619c5cb6 VZ |
8651 | } |
8652 | ||
910cc727 | 8653 | static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
6383c0b3 AE |
8654 | struct bnx2x_queue_state_params *q_params, |
8655 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
8656 | int tx_index, bool leading) | |
8657 | { | |
8658 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
8659 | ||
8660 | /* Set the command */ | |
8661 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
8662 | ||
8663 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
8664 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
8665 | ||
8666 | /* choose the index of the cid to send the slow path on */ | |
8667 | tx_only_params->cid_index = tx_index; | |
8668 | ||
8669 | /* Set general TX_ONLY_SETUP parameters */ | |
8670 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
8671 | ||
8672 | /* Set Tx TX_ONLY_SETUP parameters */ | |
8673 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
8674 | ||
51c1a580 MS |
8675 | DP(NETIF_MSG_IFUP, |
8676 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", | |
6383c0b3 AE |
8677 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
8678 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
8679 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
8680 | ||
8681 | /* send the ramrod */ | |
8682 | return bnx2x_queue_state_change(bp, q_params); | |
8683 | } | |
8684 | ||
619c5cb6 VZ |
8685 | /** |
8686 | * bnx2x_setup_queue - setup queue | |
8687 | * | |
8688 | * @bp: driver handle | |
8689 | * @fp: pointer to fastpath | |
8690 | * @leading: is leading | |
8691 | * | |
8692 | * This function performs 2 steps in a Queue state machine | |
8693 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
8694 | */ | |
8695 | ||
8696 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
8697 | bool leading) | |
8698 | { | |
3b603066 | 8699 | struct bnx2x_queue_state_params q_params = {NULL}; |
619c5cb6 VZ |
8700 | struct bnx2x_queue_setup_params *setup_params = |
8701 | &q_params.params.setup; | |
6383c0b3 AE |
8702 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
8703 | &q_params.params.tx_only; | |
a2fbb9ea | 8704 | int rc; |
6383c0b3 AE |
8705 | u8 tx_index; |
8706 | ||
51c1a580 | 8707 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 8708 | |
ec6ba945 VZ |
8709 | /* reset IGU state skip FCoE L2 queue */ |
8710 | if (!IS_FCOE_FP(fp)) | |
8711 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 8712 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 8713 | |
15192a8c | 8714 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8715 | /* We want to wait for completion in this context */ |
8716 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8717 | |
619c5cb6 VZ |
8718 | /* Prepare the INIT parameters */ |
8719 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 8720 | |
619c5cb6 VZ |
8721 | /* Set the command */ |
8722 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
8723 | ||
8724 | /* Change the state to INIT */ | |
8725 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8726 | if (rc) { | |
6383c0b3 | 8727 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
8728 | return rc; |
8729 | } | |
ec6ba945 | 8730 | |
51c1a580 | 8731 | DP(NETIF_MSG_IFUP, "init complete\n"); |
6383c0b3 | 8732 | |
619c5cb6 VZ |
8733 | /* Now move the Queue to the SETUP state... */ |
8734 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 8735 | |
619c5cb6 VZ |
8736 | /* Set QUEUE flags */ |
8737 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 8738 | |
619c5cb6 | 8739 | /* Set general SETUP parameters */ |
6383c0b3 AE |
8740 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
8741 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 8742 | |
6383c0b3 | 8743 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
8744 | &setup_params->rxq_params); |
8745 | ||
6383c0b3 AE |
8746 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
8747 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
8748 | |
8749 | /* Set the command */ | |
8750 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
8751 | ||
55c11941 MS |
8752 | if (IS_FCOE_FP(fp)) |
8753 | bp->fcoe_init = true; | |
8754 | ||
619c5cb6 VZ |
8755 | /* Change the state to SETUP */ |
8756 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
8757 | if (rc) { |
8758 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
8759 | return rc; | |
8760 | } | |
8761 | ||
8762 | /* loop through the relevant tx-only indices */ | |
8763 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8764 | tx_index < fp->max_cos; | |
8765 | tx_index++) { | |
8766 | ||
8767 | /* prepare and send tx-only ramrod*/ | |
8768 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
8769 | tx_only_params, tx_index, leading); | |
8770 | if (rc) { | |
8771 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
8772 | fp->index, tx_index); | |
8773 | return rc; | |
8774 | } | |
8775 | } | |
523224a3 | 8776 | |
34f80b04 | 8777 | return rc; |
a2fbb9ea ET |
8778 | } |
8779 | ||
619c5cb6 | 8780 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 8781 | { |
619c5cb6 | 8782 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 8783 | struct bnx2x_fp_txdata *txdata; |
3b603066 | 8784 | struct bnx2x_queue_state_params q_params = {NULL}; |
6383c0b3 AE |
8785 | int rc, tx_index; |
8786 | ||
51c1a580 | 8787 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 8788 | |
15192a8c | 8789 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8790 | /* We want to wait for completion in this context */ |
8791 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8792 | |
6383c0b3 AE |
8793 | /* close tx-only connections */ |
8794 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8795 | tx_index < fp->max_cos; | |
8796 | tx_index++){ | |
8797 | ||
8798 | /* ascertain this is a normal queue*/ | |
65565884 | 8799 | txdata = fp->txdata_ptr[tx_index]; |
6383c0b3 | 8800 | |
51c1a580 | 8801 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
6383c0b3 AE |
8802 | txdata->txq_index); |
8803 | ||
8804 | /* send halt terminate on tx-only connection */ | |
8805 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
8806 | memset(&q_params.params.terminate, 0, | |
8807 | sizeof(q_params.params.terminate)); | |
8808 | q_params.params.terminate.cid_index = tx_index; | |
8809 | ||
8810 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8811 | if (rc) | |
8812 | return rc; | |
8813 | ||
8814 | /* send halt terminate on tx-only connection */ | |
8815 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
8816 | memset(&q_params.params.cfc_del, 0, | |
8817 | sizeof(q_params.params.cfc_del)); | |
8818 | q_params.params.cfc_del.cid_index = tx_index; | |
8819 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8820 | if (rc) | |
8821 | return rc; | |
8822 | } | |
8823 | /* Stop the primary connection: */ | |
8824 | /* ...halt the connection */ | |
619c5cb6 VZ |
8825 | q_params.cmd = BNX2X_Q_CMD_HALT; |
8826 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8827 | if (rc) | |
da5a662a | 8828 | return rc; |
a2fbb9ea | 8829 | |
6383c0b3 | 8830 | /* ...terminate the connection */ |
619c5cb6 | 8831 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
8832 | memset(&q_params.params.terminate, 0, |
8833 | sizeof(q_params.params.terminate)); | |
8834 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
8835 | rc = bnx2x_queue_state_change(bp, &q_params); |
8836 | if (rc) | |
523224a3 | 8837 | return rc; |
6383c0b3 | 8838 | /* ...delete cfc entry */ |
619c5cb6 | 8839 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
8840 | memset(&q_params.params.cfc_del, 0, |
8841 | sizeof(q_params.params.cfc_del)); | |
8842 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 8843 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
8844 | } |
8845 | ||
34f80b04 EG |
8846 | static void bnx2x_reset_func(struct bnx2x *bp) |
8847 | { | |
8848 | int port = BP_PORT(bp); | |
8849 | int func = BP_FUNC(bp); | |
f2e0899f | 8850 | int i; |
523224a3 DK |
8851 | |
8852 | /* Disable the function in the FW */ | |
8853 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
8854 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
8855 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
8856 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
8857 | ||
8858 | /* FP SBs */ | |
ec6ba945 | 8859 | for_each_eth_queue(bp, i) { |
523224a3 | 8860 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 8861 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8862 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
8863 | SB_DISABLED); | |
523224a3 DK |
8864 | } |
8865 | ||
55c11941 MS |
8866 | if (CNIC_LOADED(bp)) |
8867 | /* CNIC SB */ | |
8868 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
8869 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET | |
8870 | (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); | |
8871 | ||
523224a3 | 8872 | /* SP SB */ |
619c5cb6 | 8873 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
2de67439 YM |
8874 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
8875 | SB_DISABLED); | |
523224a3 DK |
8876 | |
8877 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
8878 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
8879 | 0); | |
34f80b04 EG |
8880 | |
8881 | /* Configure IGU */ | |
f2e0899f DK |
8882 | if (bp->common.int_block == INT_BLOCK_HC) { |
8883 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
8884 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
8885 | } else { | |
8886 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
8887 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
8888 | } | |
34f80b04 | 8889 | |
55c11941 MS |
8890 | if (CNIC_LOADED(bp)) { |
8891 | /* Disable Timer scan */ | |
8892 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
8893 | /* | |
8894 | * Wait for at least 10ms and up to 2 second for the timers | |
8895 | * scan to complete | |
8896 | */ | |
8897 | for (i = 0; i < 200; i++) { | |
639d65b8 | 8898 | usleep_range(10000, 20000); |
55c11941 MS |
8899 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) |
8900 | break; | |
8901 | } | |
37b091ba | 8902 | } |
34f80b04 | 8903 | /* Clear ILT */ |
f2e0899f DK |
8904 | bnx2x_clear_func_ilt(bp, func); |
8905 | ||
8906 | /* Timers workaround bug for E2: if this is vnic-3, | |
8907 | * we need to set the entire ilt range for this timers. | |
8908 | */ | |
619c5cb6 | 8909 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
8910 | struct ilt_client_info ilt_cli; |
8911 | /* use dummy TM client */ | |
8912 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
8913 | ilt_cli.start = 0; | |
8914 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
8915 | ilt_cli.client_num = ILT_CLIENT_TM; | |
8916 | ||
8917 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
8918 | } | |
8919 | ||
8920 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 8921 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 8922 | bnx2x_pf_disable(bp); |
523224a3 DK |
8923 | |
8924 | bp->dmae_ready = 0; | |
34f80b04 EG |
8925 | } |
8926 | ||
8927 | static void bnx2x_reset_port(struct bnx2x *bp) | |
8928 | { | |
8929 | int port = BP_PORT(bp); | |
8930 | u32 val; | |
8931 | ||
619c5cb6 VZ |
8932 | /* Reset physical Link */ |
8933 | bnx2x__link_reset(bp); | |
8934 | ||
34f80b04 EG |
8935 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
8936 | ||
8937 | /* Do not rcv packets to BRB */ | |
8938 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
8939 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
8940 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
8941 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
8942 | ||
8943 | /* Configure AEU */ | |
8944 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
8945 | ||
8946 | msleep(100); | |
8947 | /* Check for BRB port occupancy */ | |
8948 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
8949 | if (val) | |
8950 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 8951 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
8952 | |
8953 | /* TODO: Close Doorbell port? */ | |
8954 | } | |
8955 | ||
1191cb83 | 8956 | static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 8957 | { |
3b603066 | 8958 | struct bnx2x_func_state_params func_params = {NULL}; |
34f80b04 | 8959 | |
619c5cb6 VZ |
8960 | /* Prepare parameters for function state transitions */ |
8961 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 8962 | |
619c5cb6 VZ |
8963 | func_params.f_obj = &bp->func_obj; |
8964 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 8965 | |
619c5cb6 | 8966 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 8967 | |
619c5cb6 | 8968 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
8969 | } |
8970 | ||
1191cb83 | 8971 | static int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 8972 | { |
3b603066 | 8973 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 | 8974 | int rc; |
228241eb | 8975 | |
619c5cb6 VZ |
8976 | /* Prepare parameters for function state transitions */ |
8977 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
8978 | func_params.f_obj = &bp->func_obj; | |
8979 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 8980 | |
619c5cb6 VZ |
8981 | /* |
8982 | * Try to stop the function the 'good way'. If fails (in case | |
8983 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
8984 | * not in a debug mode, perform a state transaction in order to | |
8985 | * enable further HW_RESET transaction. | |
8986 | */ | |
8987 | rc = bnx2x_func_state_change(bp, &func_params); | |
8988 | if (rc) { | |
34f80b04 | 8989 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 8990 | return rc; |
34f80b04 | 8991 | #else |
51c1a580 | 8992 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
619c5cb6 VZ |
8993 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
8994 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 8995 | #endif |
228241eb | 8996 | } |
a2fbb9ea | 8997 | |
619c5cb6 VZ |
8998 | return 0; |
8999 | } | |
523224a3 | 9000 | |
619c5cb6 VZ |
9001 | /** |
9002 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
9003 | * | |
9004 | * @bp: driver handle | |
9005 | * @unload_mode: requested function's unload mode | |
9006 | * | |
9007 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
9008 | */ | |
9009 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
9010 | { | |
9011 | u32 reset_code = 0; | |
9012 | int port = BP_PORT(bp); | |
3101c2bc | 9013 | |
619c5cb6 | 9014 | /* Select the UNLOAD request mode */ |
65abd74d YG |
9015 | if (unload_mode == UNLOAD_NORMAL) |
9016 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
9017 | ||
7d0446c2 | 9018 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 9019 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 9020 | |
7d0446c2 | 9021 | else if (bp->wol) { |
65abd74d YG |
9022 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
9023 | u8 *mac_addr = bp->dev->dev_addr; | |
29ed74c3 | 9024 | struct pci_dev *pdev = bp->pdev; |
65abd74d | 9025 | u32 val; |
f9977903 DK |
9026 | u16 pmc; |
9027 | ||
65abd74d | 9028 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
9029 | * preserve entry 0 which is used by the PMF |
9030 | */ | |
3395a033 | 9031 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
9032 | |
9033 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
9034 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
9035 | ||
9036 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
9037 | (mac_addr[4] << 8) | mac_addr[5]; | |
9038 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
9039 | ||
f9977903 | 9040 | /* Enable the PME and clear the status */ |
29ed74c3 | 9041 | pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc); |
f9977903 | 9042 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; |
29ed74c3 | 9043 | pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc); |
f9977903 | 9044 | |
65abd74d YG |
9045 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
9046 | ||
9047 | } else | |
9048 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 9049 | |
619c5cb6 VZ |
9050 | /* Send the request to the MCP */ |
9051 | if (!BP_NOMCP(bp)) | |
9052 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
9053 | else { | |
9054 | int path = BP_PATH(bp); | |
9055 | ||
51c1a580 | 9056 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
a8f47eb7 | 9057 | path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], |
9058 | bnx2x_load_count[path][2]); | |
9059 | bnx2x_load_count[path][0]--; | |
9060 | bnx2x_load_count[path][1 + port]--; | |
51c1a580 | 9061 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
a8f47eb7 | 9062 | path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], |
9063 | bnx2x_load_count[path][2]); | |
9064 | if (bnx2x_load_count[path][0] == 0) | |
619c5cb6 | 9065 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; |
a8f47eb7 | 9066 | else if (bnx2x_load_count[path][1 + port] == 0) |
619c5cb6 VZ |
9067 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; |
9068 | else | |
9069 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
9070 | } | |
9071 | ||
9072 | return reset_code; | |
9073 | } | |
9074 | ||
9075 | /** | |
9076 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
9077 | * | |
9078 | * @bp: driver handle | |
5d07d868 | 9079 | * @keep_link: true iff link should be kept up |
619c5cb6 | 9080 | */ |
5d07d868 | 9081 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) |
619c5cb6 | 9082 | { |
5d07d868 YM |
9083 | u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; |
9084 | ||
619c5cb6 VZ |
9085 | /* Report UNLOAD_DONE to MCP */ |
9086 | if (!BP_NOMCP(bp)) | |
5d07d868 | 9087 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); |
619c5cb6 VZ |
9088 | } |
9089 | ||
1191cb83 | 9090 | static int bnx2x_func_wait_started(struct bnx2x *bp) |
6debea87 DK |
9091 | { |
9092 | int tout = 50; | |
9093 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
9094 | ||
9095 | if (!bp->port.pmf) | |
9096 | return 0; | |
9097 | ||
9098 | /* | |
9099 | * (assumption: No Attention from MCP at this stage) | |
16a5fd92 | 9100 | * PMF probably in the middle of TX disable/enable transaction |
6debea87 | 9101 | * 1. Sync IRS for default SB |
16a5fd92 YM |
9102 | * 2. Sync SP queue - this guarantees us that attention handling started |
9103 | * 3. Wait, that TX disable/enable transaction completes | |
6debea87 | 9104 | * |
16a5fd92 YM |
9105 | * 1+2 guarantee that if DCBx attention was scheduled it already changed |
9106 | * pending bit of transaction from STARTED-->TX_STOPPED, if we already | |
9107 | * received completion for the transaction the state is TX_STOPPED. | |
6debea87 DK |
9108 | * State will return to STARTED after completion of TX_STOPPED-->STARTED |
9109 | * transaction. | |
9110 | */ | |
9111 | ||
9112 | /* make sure default SB ISR is done */ | |
9113 | if (msix) | |
9114 | synchronize_irq(bp->msix_table[0].vector); | |
9115 | else | |
9116 | synchronize_irq(bp->pdev->irq); | |
9117 | ||
9118 | flush_workqueue(bnx2x_wq); | |
370d4a26 | 9119 | flush_workqueue(bnx2x_iov_wq); |
6debea87 DK |
9120 | |
9121 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
9122 | BNX2X_F_STATE_STARTED && tout--) | |
9123 | msleep(20); | |
9124 | ||
9125 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
9126 | BNX2X_F_STATE_STARTED) { | |
9127 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 9128 | BNX2X_ERR("Wrong function state\n"); |
6debea87 DK |
9129 | return -EBUSY; |
9130 | #else | |
9131 | /* | |
9132 | * Failed to complete the transaction in a "good way" | |
9133 | * Force both transactions with CLR bit | |
9134 | */ | |
3b603066 | 9135 | struct bnx2x_func_state_params func_params = {NULL}; |
6debea87 | 9136 | |
51c1a580 | 9137 | DP(NETIF_MSG_IFDOWN, |
0c23ad37 | 9138 | "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n"); |
6debea87 DK |
9139 | |
9140 | func_params.f_obj = &bp->func_obj; | |
9141 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
9142 | &func_params.ramrod_flags); | |
9143 | ||
9144 | /* STARTED-->TX_ST0PPED */ | |
9145 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
9146 | bnx2x_func_state_change(bp, &func_params); | |
9147 | ||
9148 | /* TX_ST0PPED-->STARTED */ | |
9149 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
9150 | return bnx2x_func_state_change(bp, &func_params); | |
9151 | #endif | |
9152 | } | |
9153 | ||
9154 | return 0; | |
9155 | } | |
9156 | ||
eeed018c MK |
9157 | static void bnx2x_disable_ptp(struct bnx2x *bp) |
9158 | { | |
9159 | int port = BP_PORT(bp); | |
9160 | ||
9161 | /* Disable sending PTP packets to host */ | |
9162 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : | |
9163 | NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); | |
9164 | ||
9165 | /* Reset PTP event detection rules */ | |
9166 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
9167 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); | |
9168 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
9169 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); | |
9170 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : | |
9171 | NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); | |
9172 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : | |
9173 | NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); | |
9174 | ||
9175 | /* Disable the PTP feature */ | |
9176 | REG_WR(bp, port ? NIG_REG_P1_PTP_EN : | |
9177 | NIG_REG_P0_PTP_EN, 0x0); | |
9178 | } | |
9179 | ||
9180 | /* Called during unload, to stop PTP-related stuff */ | |
1444c301 | 9181 | static void bnx2x_stop_ptp(struct bnx2x *bp) |
eeed018c MK |
9182 | { |
9183 | /* Cancel PTP work queue. Should be done after the Tx queues are | |
9184 | * drained to prevent additional scheduling. | |
9185 | */ | |
9186 | cancel_work_sync(&bp->ptp_task); | |
9187 | ||
9188 | if (bp->ptp_tx_skb) { | |
9189 | dev_kfree_skb_any(bp->ptp_tx_skb); | |
9190 | bp->ptp_tx_skb = NULL; | |
9191 | } | |
9192 | ||
9193 | /* Disable PTP in HW */ | |
9194 | bnx2x_disable_ptp(bp); | |
9195 | ||
9196 | DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n"); | |
9197 | } | |
9198 | ||
5d07d868 | 9199 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) |
619c5cb6 VZ |
9200 | { |
9201 | int port = BP_PORT(bp); | |
6383c0b3 AE |
9202 | int i, rc = 0; |
9203 | u8 cos; | |
3b603066 | 9204 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 VZ |
9205 | u32 reset_code; |
9206 | ||
9207 | /* Wait until tx fastpath tasks complete */ | |
9208 | for_each_tx_queue(bp, i) { | |
9209 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
9210 | ||
6383c0b3 | 9211 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 9212 | rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); |
619c5cb6 VZ |
9213 | #ifdef BNX2X_STOP_ON_ERROR |
9214 | if (rc) | |
9215 | return; | |
9216 | #endif | |
9217 | } | |
9218 | ||
9219 | /* Give HW time to discard old tx messages */ | |
0926d499 | 9220 | usleep_range(1000, 2000); |
619c5cb6 VZ |
9221 | |
9222 | /* Clean all ETH MACs */ | |
15192a8c BW |
9223 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, |
9224 | false); | |
619c5cb6 VZ |
9225 | if (rc < 0) |
9226 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
9227 | ||
9228 | /* Clean up UC list */ | |
15192a8c | 9229 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, |
619c5cb6 VZ |
9230 | true); |
9231 | if (rc < 0) | |
51c1a580 MS |
9232 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
9233 | rc); | |
619c5cb6 VZ |
9234 | |
9235 | /* Disable LLH */ | |
9236 | if (!CHIP_IS_E1(bp)) | |
9237 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
9238 | ||
9239 | /* Set "drop all" (stop Rx). | |
9240 | * We need to take a netif_addr_lock() here in order to prevent | |
9241 | * a race between the completion code and this code. | |
9242 | */ | |
9243 | netif_addr_lock_bh(bp->dev); | |
9244 | /* Schedule the rx_mode command */ | |
9245 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
9246 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
9247 | else | |
9248 | bnx2x_set_storm_rx_mode(bp); | |
9249 | ||
9250 | /* Cleanup multicast configuration */ | |
9251 | rparam.mcast_obj = &bp->mcast_obj; | |
9252 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
9253 | if (rc < 0) | |
9254 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
9255 | ||
9256 | netif_addr_unlock_bh(bp->dev); | |
9257 | ||
f1929b01 | 9258 | bnx2x_iov_chip_cleanup(bp); |
619c5cb6 | 9259 | |
6debea87 DK |
9260 | /* |
9261 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
9262 | * this function should perform FUNC, PORT or COMMON HW | |
9263 | * reset. | |
9264 | */ | |
9265 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
9266 | ||
9267 | /* | |
9268 | * (assumption: No Attention from MCP at this stage) | |
16a5fd92 | 9269 | * PMF probably in the middle of TX disable/enable transaction |
6debea87 DK |
9270 | */ |
9271 | rc = bnx2x_func_wait_started(bp); | |
9272 | if (rc) { | |
9273 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
9274 | #ifdef BNX2X_STOP_ON_ERROR | |
9275 | return; | |
9276 | #endif | |
9277 | } | |
9278 | ||
34f80b04 | 9279 | /* Close multi and leading connections |
619c5cb6 VZ |
9280 | * Completions for ramrods are collected in a synchronous way |
9281 | */ | |
55c11941 | 9282 | for_each_eth_queue(bp, i) |
619c5cb6 | 9283 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
9284 | #ifdef BNX2X_STOP_ON_ERROR |
9285 | return; | |
9286 | #else | |
228241eb | 9287 | goto unload_error; |
523224a3 | 9288 | #endif |
55c11941 MS |
9289 | |
9290 | if (CNIC_LOADED(bp)) { | |
9291 | for_each_cnic_queue(bp, i) | |
9292 | if (bnx2x_stop_queue(bp, i)) | |
9293 | #ifdef BNX2X_STOP_ON_ERROR | |
9294 | return; | |
9295 | #else | |
9296 | goto unload_error; | |
9297 | #endif | |
9298 | } | |
9299 | ||
619c5cb6 VZ |
9300 | /* If SP settings didn't get completed so far - something |
9301 | * very wrong has happen. | |
9302 | */ | |
9303 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
9304 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 9305 | |
619c5cb6 VZ |
9306 | #ifndef BNX2X_STOP_ON_ERROR |
9307 | unload_error: | |
9308 | #endif | |
523224a3 | 9309 | rc = bnx2x_func_stop(bp); |
da5a662a | 9310 | if (rc) { |
523224a3 | 9311 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 9312 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 9313 | return; |
523224a3 | 9314 | #endif |
34f80b04 | 9315 | } |
a2fbb9ea | 9316 | |
eeed018c MK |
9317 | /* stop_ptp should be after the Tx queues are drained to prevent |
9318 | * scheduling to the cancelled PTP work queue. It should also be after | |
9319 | * function stop ramrod is sent, since as part of this ramrod FW access | |
9320 | * PTP registers. | |
9321 | */ | |
9322 | bnx2x_stop_ptp(bp); | |
9323 | ||
523224a3 DK |
9324 | /* Disable HW interrupts, NAPI */ |
9325 | bnx2x_netif_stop(bp, 1); | |
26614ba5 MS |
9326 | /* Delete all NAPI objects */ |
9327 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
9328 | if (CNIC_LOADED(bp)) |
9329 | bnx2x_del_all_napi_cnic(bp); | |
523224a3 DK |
9330 | |
9331 | /* Release IRQs */ | |
d6214d7a | 9332 | bnx2x_free_irq(bp); |
523224a3 | 9333 | |
a2fbb9ea | 9334 | /* Reset the chip */ |
619c5cb6 VZ |
9335 | rc = bnx2x_reset_hw(bp, reset_code); |
9336 | if (rc) | |
9337 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 9338 | |
619c5cb6 | 9339 | /* Report UNLOAD_DONE to MCP */ |
5d07d868 | 9340 | bnx2x_send_unload_done(bp, keep_link); |
72fd0718 VZ |
9341 | } |
9342 | ||
9f6c9258 | 9343 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
9344 | { |
9345 | u32 val; | |
9346 | ||
51c1a580 | 9347 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
72fd0718 VZ |
9348 | |
9349 | if (CHIP_IS_E1(bp)) { | |
9350 | int port = BP_PORT(bp); | |
9351 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
9352 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
9353 | ||
9354 | val = REG_RD(bp, addr); | |
9355 | val &= ~(0x300); | |
9356 | REG_WR(bp, addr, val); | |
619c5cb6 | 9357 | } else { |
72fd0718 VZ |
9358 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
9359 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
9360 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
9361 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
9362 | } | |
9363 | } | |
9364 | ||
72fd0718 VZ |
9365 | /* Close gates #2, #3 and #4: */ |
9366 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
9367 | { | |
c9ee9206 | 9368 | u32 val; |
72fd0718 VZ |
9369 | |
9370 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
9371 | if (!CHIP_IS_E1(bp)) { | |
9372 | /* #4 */ | |
c9ee9206 | 9373 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 9374 | /* #2 */ |
c9ee9206 | 9375 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
9376 | } |
9377 | ||
9378 | /* #3 */ | |
c9ee9206 VZ |
9379 | if (CHIP_IS_E1x(bp)) { |
9380 | /* Prevent interrupts from HC on both ports */ | |
9381 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
9382 | REG_WR(bp, HC_REG_CONFIG_1, | |
9383 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
9384 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
9385 | ||
9386 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
9387 | REG_WR(bp, HC_REG_CONFIG_0, | |
9388 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
9389 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
9390 | } else { | |
d82603c6 | 9391 | /* Prevent incoming interrupts in IGU */ |
c9ee9206 VZ |
9392 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
9393 | ||
9394 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
9395 | (!close) ? | |
9396 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
9397 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
9398 | } | |
72fd0718 | 9399 | |
51c1a580 | 9400 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
72fd0718 VZ |
9401 | close ? "closing" : "opening"); |
9402 | mmiowb(); | |
9403 | } | |
9404 | ||
9405 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
9406 | ||
9407 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
9408 | { | |
9409 | /* Do some magic... */ | |
9410 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
9411 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
9412 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
9413 | } | |
9414 | ||
e8920674 DK |
9415 | /** |
9416 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 9417 | * |
e8920674 DK |
9418 | * @bp: driver handle |
9419 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
9420 | */ |
9421 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
9422 | { | |
9423 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
9424 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
9425 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
9426 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
9427 | } | |
9428 | ||
f85582f8 | 9429 | /** |
e8920674 | 9430 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 9431 | * |
e8920674 DK |
9432 | * @bp: driver handle |
9433 | * @magic_val: old value of 'magic' bit. | |
9434 | * | |
9435 | * Takes care of CLP configurations. | |
72fd0718 VZ |
9436 | */ |
9437 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
9438 | { | |
9439 | u32 shmem; | |
9440 | u32 validity_offset; | |
9441 | ||
51c1a580 | 9442 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
72fd0718 VZ |
9443 | |
9444 | /* Set `magic' bit in order to save MF config */ | |
9445 | if (!CHIP_IS_E1(bp)) | |
9446 | bnx2x_clp_reset_prep(bp, magic_val); | |
9447 | ||
9448 | /* Get shmem offset */ | |
9449 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
c55e771b BW |
9450 | validity_offset = |
9451 | offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); | |
72fd0718 VZ |
9452 | |
9453 | /* Clear validity map flags */ | |
9454 | if (shmem > 0) | |
9455 | REG_WR(bp, shmem + validity_offset, 0); | |
9456 | } | |
9457 | ||
9458 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
9459 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
9460 | ||
e8920674 DK |
9461 | /** |
9462 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 9463 | * |
e8920674 | 9464 | * @bp: driver handle |
72fd0718 | 9465 | */ |
1191cb83 | 9466 | static void bnx2x_mcp_wait_one(struct bnx2x *bp) |
72fd0718 VZ |
9467 | { |
9468 | /* special handling for emulation and FPGA, | |
9469 | wait 10 times longer */ | |
9470 | if (CHIP_REV_IS_SLOW(bp)) | |
9471 | msleep(MCP_ONE_TIMEOUT*10); | |
9472 | else | |
9473 | msleep(MCP_ONE_TIMEOUT); | |
9474 | } | |
9475 | ||
1b6e2ceb DK |
9476 | /* |
9477 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
9478 | */ | |
9479 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 9480 | { |
1b6e2ceb DK |
9481 | int cnt = 0; |
9482 | u32 val = 0; | |
72fd0718 | 9483 | |
1b6e2ceb DK |
9484 | do { |
9485 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
9486 | if (bp->common.shmem_base) { | |
9487 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
9488 | if (val & SHR_MEM_VALIDITY_MB) | |
9489 | return 0; | |
9490 | } | |
72fd0718 | 9491 | |
1b6e2ceb | 9492 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 9493 | |
1b6e2ceb | 9494 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 9495 | |
1b6e2ceb | 9496 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 9497 | |
1b6e2ceb DK |
9498 | return -ENODEV; |
9499 | } | |
72fd0718 | 9500 | |
1b6e2ceb DK |
9501 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
9502 | { | |
9503 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 9504 | |
72fd0718 VZ |
9505 | /* Restore the `magic' bit value */ |
9506 | if (!CHIP_IS_E1(bp)) | |
9507 | bnx2x_clp_reset_done(bp, magic_val); | |
9508 | ||
9509 | return rc; | |
9510 | } | |
9511 | ||
9512 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
9513 | { | |
9514 | if (!CHIP_IS_E1(bp)) { | |
9515 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
9516 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
9517 | mmiowb(); |
9518 | } | |
9519 | } | |
9520 | ||
9521 | /* | |
9522 | * Reset the whole chip except for: | |
9523 | * - PCIE core | |
9524 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
9525 | * one reset bit) | |
9526 | * - IGU | |
9527 | * - MISC (including AEU) | |
9528 | * - GRC | |
9529 | * - RBCN, RBCP | |
9530 | */ | |
c9ee9206 | 9531 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
9532 | { |
9533 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 9534 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
9535 | |
9536 | /* | |
9537 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
9538 | * (per chip) blocks. | |
9539 | */ | |
9540 | global_bits2 = | |
9541 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
9542 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 9543 | |
c55e771b BW |
9544 | /* Don't reset the following blocks. |
9545 | * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be | |
9546 | * reset, as in 4 port device they might still be owned | |
9547 | * by the MCP (there is only one leader per path). | |
9548 | */ | |
72fd0718 VZ |
9549 | not_reset_mask1 = |
9550 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
9551 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
9552 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
9553 | ||
9554 | not_reset_mask2 = | |
c9ee9206 | 9555 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
9556 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
9557 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
9558 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
9559 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
9560 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
9561 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
9562 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
9563 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
c55e771b BW |
9564 | MISC_REGISTERS_RESET_REG_2_PGLC | |
9565 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
9566 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
9567 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
9568 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
9569 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
9570 | MISC_REGISTERS_RESET_REG_2_UMAC1; | |
72fd0718 | 9571 | |
8736c826 VZ |
9572 | /* |
9573 | * Keep the following blocks in reset: | |
9574 | * - all xxMACs are handled by the bnx2x_link code. | |
9575 | */ | |
9576 | stay_reset2 = | |
8736c826 VZ |
9577 | MISC_REGISTERS_RESET_REG_2_XMAC | |
9578 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
9579 | ||
9580 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
9581 | reset_mask1 = 0xffffffff; |
9582 | ||
9583 | if (CHIP_IS_E1(bp)) | |
9584 | reset_mask2 = 0xffff; | |
8736c826 | 9585 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 9586 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
9587 | else if (CHIP_IS_E2(bp)) |
9588 | reset_mask2 = 0xfffff; | |
9589 | else /* CHIP_IS_E3 */ | |
9590 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
9591 | |
9592 | /* Don't reset global blocks unless we need to */ | |
9593 | if (!global) | |
9594 | reset_mask2 &= ~global_bits2; | |
9595 | ||
9596 | /* | |
9597 | * In case of attention in the QM, we need to reset PXP | |
9598 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
9599 | * because otherwise QM reset would release 'close the gates' shortly | |
9600 | * before resetting the PXP, then the PSWRQ would send a write | |
9601 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
9602 | * read the payload data from PSWWR, but PSWWR would not | |
9603 | * respond. The write queue in PGLUE would stuck, dmae commands | |
9604 | * would not return. Therefore it's important to reset the second | |
9605 | * reset register (containing the | |
9606 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
9607 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
9608 | * bit). | |
9609 | */ | |
72fd0718 VZ |
9610 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
9611 | reset_mask2 & (~not_reset_mask2)); | |
9612 | ||
c9ee9206 VZ |
9613 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
9614 | reset_mask1 & (~not_reset_mask1)); | |
9615 | ||
72fd0718 VZ |
9616 | barrier(); |
9617 | mmiowb(); | |
9618 | ||
8736c826 VZ |
9619 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
9620 | reset_mask2 & (~stay_reset2)); | |
9621 | ||
9622 | barrier(); | |
9623 | mmiowb(); | |
9624 | ||
c9ee9206 | 9625 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
9626 | mmiowb(); |
9627 | } | |
9628 | ||
c9ee9206 VZ |
9629 | /** |
9630 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
9631 | * It should get cleared in no more than 1s. | |
9632 | * | |
9633 | * @bp: driver handle | |
9634 | * | |
9635 | * It should get cleared in no more than 1s. Returns 0 if | |
9636 | * pending writes bit gets cleared. | |
9637 | */ | |
9638 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
9639 | { | |
9640 | u32 cnt = 1000; | |
9641 | u32 pend_bits = 0; | |
9642 | ||
9643 | do { | |
9644 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
9645 | ||
9646 | if (pend_bits == 0) | |
9647 | break; | |
9648 | ||
0926d499 | 9649 | usleep_range(1000, 2000); |
c9ee9206 VZ |
9650 | } while (cnt-- > 0); |
9651 | ||
9652 | if (cnt <= 0) { | |
9653 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
9654 | pend_bits); | |
9655 | return -EBUSY; | |
9656 | } | |
9657 | ||
9658 | return 0; | |
9659 | } | |
9660 | ||
9661 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
9662 | { |
9663 | int cnt = 1000; | |
9664 | u32 val = 0; | |
9665 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
2de67439 | 9666 | u32 tags_63_32 = 0; |
72fd0718 VZ |
9667 | |
9668 | /* Empty the Tetris buffer, wait for 1s */ | |
9669 | do { | |
9670 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
9671 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
9672 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
9673 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
9674 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
c55e771b BW |
9675 | if (CHIP_IS_E3(bp)) |
9676 | tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); | |
9677 | ||
72fd0718 VZ |
9678 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && |
9679 | ((port_is_idle_0 & 0x1) == 0x1) && | |
9680 | ((port_is_idle_1 & 0x1) == 0x1) && | |
c55e771b BW |
9681 | (pgl_exp_rom2 == 0xffffffff) && |
9682 | (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) | |
72fd0718 | 9683 | break; |
0926d499 | 9684 | usleep_range(1000, 2000); |
72fd0718 VZ |
9685 | } while (cnt-- > 0); |
9686 | ||
9687 | if (cnt <= 0) { | |
51c1a580 MS |
9688 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
9689 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
72fd0718 VZ |
9690 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
9691 | pgl_exp_rom2); | |
9692 | return -EAGAIN; | |
9693 | } | |
9694 | ||
9695 | barrier(); | |
9696 | ||
9697 | /* Close gates #2, #3 and #4 */ | |
9698 | bnx2x_set_234_gates(bp, true); | |
9699 | ||
c9ee9206 VZ |
9700 | /* Poll for IGU VQs for 57712 and newer chips */ |
9701 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
9702 | return -EAGAIN; | |
9703 | ||
72fd0718 VZ |
9704 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
9705 | ||
9706 | /* Clear "unprepared" bit */ | |
9707 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
9708 | barrier(); | |
9709 | ||
9710 | /* Make sure all is written to the chip before the reset */ | |
9711 | mmiowb(); | |
9712 | ||
9713 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
9714 | * PSWHST, GRC and PSWRD Tetris buffer. | |
9715 | */ | |
0926d499 | 9716 | usleep_range(1000, 2000); |
72fd0718 VZ |
9717 | |
9718 | /* Prepare to chip reset: */ | |
9719 | /* MCP */ | |
c9ee9206 VZ |
9720 | if (global) |
9721 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
9722 | |
9723 | /* PXP */ | |
9724 | bnx2x_pxp_prep(bp); | |
9725 | barrier(); | |
9726 | ||
9727 | /* reset the chip */ | |
c9ee9206 | 9728 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
9729 | barrier(); |
9730 | ||
9dcd9acd DK |
9731 | /* clear errors in PGB */ |
9732 | if (!CHIP_IS_E1x(bp)) | |
9733 | REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); | |
9734 | ||
72fd0718 VZ |
9735 | /* Recover after reset: */ |
9736 | /* MCP */ | |
c9ee9206 | 9737 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
9738 | return -EAGAIN; |
9739 | ||
c9ee9206 VZ |
9740 | /* TBD: Add resetting the NO_MCP mode DB here */ |
9741 | ||
72fd0718 VZ |
9742 | /* Open the gates #2, #3 and #4 */ |
9743 | bnx2x_set_234_gates(bp, false); | |
9744 | ||
9745 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
9746 | * reset state, re-enable attentions. */ | |
9747 | ||
a2fbb9ea ET |
9748 | return 0; |
9749 | } | |
9750 | ||
910cc727 | 9751 | static int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
9752 | { |
9753 | int rc = 0; | |
c9ee9206 | 9754 | bool global = bnx2x_reset_is_global(bp); |
95c6c616 AE |
9755 | u32 load_code; |
9756 | ||
9757 | /* if not going to reset MCP - load "fake" driver to reset HW while | |
9758 | * driver is owner of the HW | |
9759 | */ | |
9760 | if (!global && !BP_NOMCP(bp)) { | |
5d07d868 YM |
9761 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, |
9762 | DRV_MSG_CODE_LOAD_REQ_WITH_LFA); | |
95c6c616 AE |
9763 | if (!load_code) { |
9764 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9765 | rc = -EAGAIN; | |
9766 | goto exit_leader_reset; | |
9767 | } | |
9768 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && | |
9769 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { | |
9770 | BNX2X_ERR("MCP unexpected resp, aborting\n"); | |
9771 | rc = -EAGAIN; | |
9772 | goto exit_leader_reset2; | |
9773 | } | |
9774 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
9775 | if (!load_code) { | |
9776 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9777 | rc = -EAGAIN; | |
9778 | goto exit_leader_reset2; | |
9779 | } | |
9780 | } | |
c9ee9206 | 9781 | |
72fd0718 | 9782 | /* Try to recover after the failure */ |
c9ee9206 | 9783 | if (bnx2x_process_kill(bp, global)) { |
51c1a580 MS |
9784 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
9785 | BP_PATH(bp)); | |
72fd0718 | 9786 | rc = -EAGAIN; |
95c6c616 | 9787 | goto exit_leader_reset2; |
72fd0718 VZ |
9788 | } |
9789 | ||
c9ee9206 VZ |
9790 | /* |
9791 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
9792 | * state. | |
9793 | */ | |
72fd0718 | 9794 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
9795 | if (global) |
9796 | bnx2x_clear_reset_global(bp); | |
72fd0718 | 9797 | |
95c6c616 AE |
9798 | exit_leader_reset2: |
9799 | /* unload "fake driver" if it was loaded */ | |
9800 | if (!global && !BP_NOMCP(bp)) { | |
9801 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); | |
9802 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
9803 | } | |
72fd0718 VZ |
9804 | exit_leader_reset: |
9805 | bp->is_leader = 0; | |
c9ee9206 VZ |
9806 | bnx2x_release_leader_lock(bp); |
9807 | smp_mb(); | |
72fd0718 VZ |
9808 | return rc; |
9809 | } | |
9810 | ||
1191cb83 | 9811 | static void bnx2x_recovery_failed(struct bnx2x *bp) |
c9ee9206 VZ |
9812 | { |
9813 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
9814 | ||
9815 | /* Disconnect this device */ | |
9816 | netif_device_detach(bp->dev); | |
9817 | ||
9818 | /* | |
9819 | * Block ifup for all function on this engine until "process kill" | |
9820 | * or power cycle. | |
9821 | */ | |
9822 | bnx2x_set_reset_in_progress(bp); | |
9823 | ||
9824 | /* Shut down the power */ | |
9825 | bnx2x_set_power_state(bp, PCI_D3hot); | |
9826 | ||
9827 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
9828 | ||
9829 | smp_mb(); | |
9830 | } | |
9831 | ||
9832 | /* | |
9833 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 9834 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
9835 | * will never be called when netif_running(bp->dev) is false. |
9836 | */ | |
9837 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
9838 | { | |
c9ee9206 | 9839 | bool global = false; |
7a752993 | 9840 | u32 error_recovered, error_unrecovered; |
95c6c616 | 9841 | bool is_parity; |
c9ee9206 | 9842 | |
72fd0718 VZ |
9843 | DP(NETIF_MSG_HW, "Handling parity\n"); |
9844 | while (1) { | |
9845 | switch (bp->recovery_state) { | |
9846 | case BNX2X_RECOVERY_INIT: | |
9847 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
95c6c616 AE |
9848 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
9849 | WARN_ON(!is_parity); | |
c9ee9206 | 9850 | |
72fd0718 | 9851 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
9852 | if (bnx2x_trylock_leader_lock(bp)) { |
9853 | bnx2x_set_reset_in_progress(bp); | |
9854 | /* | |
9855 | * Check if there is a global attention and if | |
9856 | * there was a global attention, set the global | |
9857 | * reset bit. | |
9858 | */ | |
9859 | ||
9860 | if (global) | |
9861 | bnx2x_set_reset_global(bp); | |
9862 | ||
72fd0718 | 9863 | bp->is_leader = 1; |
c9ee9206 | 9864 | } |
72fd0718 VZ |
9865 | |
9866 | /* Stop the driver */ | |
9867 | /* If interface has been removed - break */ | |
5d07d868 | 9868 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) |
72fd0718 VZ |
9869 | return; |
9870 | ||
9871 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 | 9872 | |
c9ee9206 VZ |
9873 | /* Ensure "is_leader", MCP command sequence and |
9874 | * "recovery_state" update values are seen on other | |
9875 | * CPUs. | |
72fd0718 | 9876 | */ |
c9ee9206 | 9877 | smp_mb(); |
72fd0718 VZ |
9878 | break; |
9879 | ||
9880 | case BNX2X_RECOVERY_WAIT: | |
9881 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
9882 | if (bp->is_leader) { | |
c9ee9206 | 9883 | int other_engine = BP_PATH(bp) ? 0 : 1; |
889b9af3 AE |
9884 | bool other_load_status = |
9885 | bnx2x_get_load_status(bp, other_engine); | |
9886 | bool load_status = | |
9887 | bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
9888 | global = bnx2x_reset_is_global(bp); |
9889 | ||
9890 | /* | |
9891 | * In case of a parity in a global block, let | |
9892 | * the first leader that performs a | |
9893 | * leader_reset() reset the global blocks in | |
9894 | * order to clear global attentions. Otherwise | |
16a5fd92 | 9895 | * the gates will remain closed for that |
c9ee9206 VZ |
9896 | * engine. |
9897 | */ | |
889b9af3 AE |
9898 | if (load_status || |
9899 | (global && other_load_status)) { | |
72fd0718 VZ |
9900 | /* Wait until all other functions get |
9901 | * down. | |
9902 | */ | |
7be08a72 | 9903 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9904 | HZ/10); |
9905 | return; | |
9906 | } else { | |
9907 | /* If all other functions got down - | |
9908 | * try to bring the chip back to | |
9909 | * normal. In any case it's an exit | |
9910 | * point for a leader. | |
9911 | */ | |
c9ee9206 VZ |
9912 | if (bnx2x_leader_reset(bp)) { |
9913 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
9914 | return; |
9915 | } | |
9916 | ||
c9ee9206 VZ |
9917 | /* If we are here, means that the |
9918 | * leader has succeeded and doesn't | |
9919 | * want to be a leader any more. Try | |
9920 | * to continue as a none-leader. | |
9921 | */ | |
9922 | break; | |
72fd0718 VZ |
9923 | } |
9924 | } else { /* non-leader */ | |
c9ee9206 | 9925 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
9926 | /* Try to get a LEADER_LOCK HW lock as |
9927 | * long as a former leader may have | |
9928 | * been unloaded by the user or | |
9929 | * released a leadership by another | |
9930 | * reason. | |
9931 | */ | |
c9ee9206 | 9932 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
9933 | /* I'm a leader now! Restart a |
9934 | * switch case. | |
9935 | */ | |
9936 | bp->is_leader = 1; | |
9937 | break; | |
9938 | } | |
9939 | ||
7be08a72 | 9940 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9941 | HZ/10); |
9942 | return; | |
9943 | ||
c9ee9206 VZ |
9944 | } else { |
9945 | /* | |
9946 | * If there was a global attention, wait | |
9947 | * for it to be cleared. | |
9948 | */ | |
9949 | if (bnx2x_reset_is_global(bp)) { | |
9950 | schedule_delayed_work( | |
7be08a72 AE |
9951 | &bp->sp_rtnl_task, |
9952 | HZ/10); | |
c9ee9206 VZ |
9953 | return; |
9954 | } | |
9955 | ||
7a752993 AE |
9956 | error_recovered = |
9957 | bp->eth_stats.recoverable_error; | |
9958 | error_unrecovered = | |
9959 | bp->eth_stats.unrecoverable_error; | |
95c6c616 AE |
9960 | bp->recovery_state = |
9961 | BNX2X_RECOVERY_NIC_LOADING; | |
9962 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { | |
7a752993 | 9963 | error_unrecovered++; |
95c6c616 | 9964 | netdev_err(bp->dev, |
51c1a580 | 9965 | "Recovery failed. Power cycle needed\n"); |
95c6c616 AE |
9966 | /* Disconnect this device */ |
9967 | netif_device_detach(bp->dev); | |
9968 | /* Shut down the power */ | |
9969 | bnx2x_set_power_state( | |
9970 | bp, PCI_D3hot); | |
9971 | smp_mb(); | |
9972 | } else { | |
c9ee9206 VZ |
9973 | bp->recovery_state = |
9974 | BNX2X_RECOVERY_DONE; | |
7a752993 | 9975 | error_recovered++; |
c9ee9206 VZ |
9976 | smp_mb(); |
9977 | } | |
7a752993 AE |
9978 | bp->eth_stats.recoverable_error = |
9979 | error_recovered; | |
9980 | bp->eth_stats.unrecoverable_error = | |
9981 | error_unrecovered; | |
c9ee9206 | 9982 | |
72fd0718 VZ |
9983 | return; |
9984 | } | |
9985 | } | |
9986 | default: | |
9987 | return; | |
9988 | } | |
9989 | } | |
9990 | } | |
9991 | ||
56ad3152 MS |
9992 | static int bnx2x_close(struct net_device *dev); |
9993 | ||
72fd0718 VZ |
9994 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
9995 | * scheduled on a general queue in order to prevent a dead lock. | |
9996 | */ | |
7be08a72 | 9997 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 9998 | { |
7be08a72 | 9999 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
10000 | |
10001 | rtnl_lock(); | |
10002 | ||
8395be5e AE |
10003 | if (!netif_running(bp->dev)) { |
10004 | rtnl_unlock(); | |
10005 | return; | |
10006 | } | |
7be08a72 | 10007 | |
6bf07b8e | 10008 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
7be08a72 | 10009 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e YM |
10010 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
10011 | "you will need to reboot when done\n"); | |
10012 | goto sp_rtnl_not_reset; | |
7be08a72 | 10013 | #endif |
7be08a72 | 10014 | /* |
b1fb8740 VZ |
10015 | * Clear all pending SP commands as we are going to reset the |
10016 | * function anyway. | |
7be08a72 | 10017 | */ |
b1fb8740 VZ |
10018 | bp->sp_rtnl_state = 0; |
10019 | smp_mb(); | |
10020 | ||
72fd0718 | 10021 | bnx2x_parity_recover(bp); |
b1fb8740 | 10022 | |
8395be5e AE |
10023 | rtnl_unlock(); |
10024 | return; | |
b1fb8740 VZ |
10025 | } |
10026 | ||
10027 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
6bf07b8e YM |
10028 | #ifdef BNX2X_STOP_ON_ERROR |
10029 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" | |
10030 | "you will need to reboot when done\n"); | |
10031 | goto sp_rtnl_not_reset; | |
10032 | #endif | |
10033 | ||
b1fb8740 VZ |
10034 | /* |
10035 | * Clear all pending SP commands as we are going to reset the | |
10036 | * function anyway. | |
10037 | */ | |
10038 | bp->sp_rtnl_state = 0; | |
10039 | smp_mb(); | |
10040 | ||
5d07d868 | 10041 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); |
72fd0718 | 10042 | bnx2x_nic_load(bp, LOAD_NORMAL); |
b1fb8740 | 10043 | |
8395be5e AE |
10044 | rtnl_unlock(); |
10045 | return; | |
72fd0718 | 10046 | } |
b1fb8740 VZ |
10047 | #ifdef BNX2X_STOP_ON_ERROR |
10048 | sp_rtnl_not_reset: | |
10049 | #endif | |
10050 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
10051 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
a3348722 BW |
10052 | if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) |
10053 | bnx2x_after_function_update(bp); | |
8304859a AE |
10054 | /* |
10055 | * in case of fan failure we need to reset id if the "stop on error" | |
10056 | * debug flag is set, since we trying to prevent permanent overheating | |
10057 | * damage | |
10058 | */ | |
10059 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { | |
51c1a580 | 10060 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
8304859a AE |
10061 | netif_device_detach(bp->dev); |
10062 | bnx2x_close(bp->dev); | |
8395be5e AE |
10063 | rtnl_unlock(); |
10064 | return; | |
8304859a AE |
10065 | } |
10066 | ||
381ac16b AE |
10067 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { |
10068 | DP(BNX2X_MSG_SP, | |
10069 | "sending set mcast vf pf channel message from rtnl sp-task\n"); | |
10070 | bnx2x_vfpf_set_mcast(bp->dev); | |
10071 | } | |
78c3bcc5 AE |
10072 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, |
10073 | &bp->sp_rtnl_state)){ | |
10074 | if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) { | |
10075 | bnx2x_tx_disable(bp); | |
10076 | BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n"); | |
10077 | } | |
10078 | } | |
381ac16b | 10079 | |
8b09be5f YM |
10080 | if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { |
10081 | DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n"); | |
10082 | bnx2x_set_rx_mode_inner(bp); | |
381ac16b AE |
10083 | } |
10084 | ||
3ec9f9ca AE |
10085 | if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, |
10086 | &bp->sp_rtnl_state)) | |
10087 | bnx2x_pf_set_vfs_vlan(bp); | |
10088 | ||
6ffa39f2 | 10089 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) { |
07b4eb3b | 10090 | bnx2x_dcbx_stop_hw_tx(bp); |
07b4eb3b | 10091 | bnx2x_dcbx_resume_hw_tx(bp); |
6ffa39f2 | 10092 | } |
07b4eb3b | 10093 | |
42f8277f YM |
10094 | if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION, |
10095 | &bp->sp_rtnl_state)) | |
10096 | bnx2x_update_mng_version(bp); | |
10097 | ||
8395be5e AE |
10098 | /* work which needs rtnl lock not-taken (as it takes the lock itself and |
10099 | * can be called from other contexts as well) | |
10100 | */ | |
34f80b04 | 10101 | rtnl_unlock(); |
8395be5e | 10102 | |
6411280a | 10103 | /* enable SR-IOV if applicable */ |
8395be5e | 10104 | if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, |
3c76feff AE |
10105 | &bp->sp_rtnl_state)) { |
10106 | bnx2x_disable_sriov(bp); | |
6411280a | 10107 | bnx2x_enable_sriov(bp); |
3c76feff | 10108 | } |
34f80b04 EG |
10109 | } |
10110 | ||
3deb8167 YR |
10111 | static void bnx2x_period_task(struct work_struct *work) |
10112 | { | |
10113 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
10114 | ||
10115 | if (!netif_running(bp->dev)) | |
10116 | goto period_task_exit; | |
10117 | ||
10118 | if (CHIP_REV_IS_SLOW(bp)) { | |
10119 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
10120 | goto period_task_exit; | |
10121 | } | |
10122 | ||
10123 | bnx2x_acquire_phy_lock(bp); | |
10124 | /* | |
10125 | * The barrier is needed to ensure the ordering between the writing to | |
10126 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
10127 | * the reading here. | |
10128 | */ | |
10129 | smp_mb(); | |
10130 | if (bp->port.pmf) { | |
10131 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
10132 | ||
10133 | /* Re-queue task in 1 sec */ | |
10134 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
10135 | } | |
10136 | ||
10137 | bnx2x_release_phy_lock(bp); | |
10138 | period_task_exit: | |
10139 | return; | |
10140 | } | |
10141 | ||
a2fbb9ea ET |
10142 | /* |
10143 | * Init service functions | |
10144 | */ | |
10145 | ||
a8f47eb7 | 10146 | static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
10147 | { |
10148 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
10149 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
10150 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
10151 | } |
10152 | ||
3d6b7253 YM |
10153 | static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp, |
10154 | u8 port, u32 reset_reg, | |
10155 | struct bnx2x_mac_vals *vals) | |
10156 | { | |
10157 | u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; | |
10158 | u32 base_addr; | |
10159 | ||
10160 | if (!(mask & reset_reg)) | |
10161 | return false; | |
10162 | ||
10163 | BNX2X_DEV_INFO("Disable umac Rx %02x\n", port); | |
10164 | base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
10165 | vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG; | |
10166 | vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]); | |
10167 | REG_WR(bp, vals->umac_addr[port], 0); | |
10168 | ||
10169 | return true; | |
10170 | } | |
10171 | ||
1ef1d45a BW |
10172 | static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, |
10173 | struct bnx2x_mac_vals *vals) | |
34f80b04 | 10174 | { |
452427b0 YM |
10175 | u32 val, base_addr, offset, mask, reset_reg; |
10176 | bool mac_stopped = false; | |
10177 | u8 port = BP_PORT(bp); | |
34f80b04 | 10178 | |
1ef1d45a | 10179 | /* reset addresses as they also mark which values were changed */ |
3d6b7253 | 10180 | memset(vals, 0, sizeof(*vals)); |
1ef1d45a | 10181 | |
452427b0 | 10182 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
f16da43b | 10183 | |
452427b0 YM |
10184 | if (!CHIP_IS_E3(bp)) { |
10185 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
10186 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; | |
10187 | if ((mask & reset_reg) && val) { | |
10188 | u32 wb_data[2]; | |
10189 | BNX2X_DEV_INFO("Disable bmac Rx\n"); | |
10190 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM | |
10191 | : NIG_REG_INGRESS_BMAC0_MEM; | |
10192 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL | |
10193 | : BIGMAC_REGISTER_BMAC_CONTROL; | |
7a06a122 | 10194 | |
452427b0 YM |
10195 | /* |
10196 | * use rd/wr since we cannot use dmae. This is safe | |
10197 | * since MCP won't access the bus due to the request | |
10198 | * to unload, and no function on the path can be | |
10199 | * loaded at this time. | |
10200 | */ | |
10201 | wb_data[0] = REG_RD(bp, base_addr + offset); | |
10202 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); | |
1ef1d45a BW |
10203 | vals->bmac_addr = base_addr + offset; |
10204 | vals->bmac_val[0] = wb_data[0]; | |
10205 | vals->bmac_val[1] = wb_data[1]; | |
452427b0 | 10206 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
1ef1d45a BW |
10207 | REG_WR(bp, vals->bmac_addr, wb_data[0]); |
10208 | REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); | |
452427b0 YM |
10209 | } |
10210 | BNX2X_DEV_INFO("Disable emac Rx\n"); | |
1ef1d45a BW |
10211 | vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; |
10212 | vals->emac_val = REG_RD(bp, vals->emac_addr); | |
10213 | REG_WR(bp, vals->emac_addr, 0); | |
452427b0 YM |
10214 | mac_stopped = true; |
10215 | } else { | |
10216 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
10217 | BNX2X_DEV_INFO("Disable xmac Rx\n"); | |
10218 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
10219 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); | |
10220 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
10221 | val & ~(1 << 1)); | |
10222 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
10223 | val | (1 << 1)); | |
1ef1d45a BW |
10224 | vals->xmac_addr = base_addr + XMAC_REG_CTRL; |
10225 | vals->xmac_val = REG_RD(bp, vals->xmac_addr); | |
10226 | REG_WR(bp, vals->xmac_addr, 0); | |
452427b0 YM |
10227 | mac_stopped = true; |
10228 | } | |
3d6b7253 YM |
10229 | |
10230 | mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0, | |
10231 | reset_reg, vals); | |
10232 | mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1, | |
10233 | reset_reg, vals); | |
452427b0 YM |
10234 | } |
10235 | ||
10236 | if (mac_stopped) | |
10237 | msleep(20); | |
452427b0 YM |
10238 | } |
10239 | ||
10240 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) | |
7c3afd85 YM |
10241 | #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \ |
10242 | 0x1848 + ((f) << 4)) | |
452427b0 YM |
10243 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) |
10244 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) | |
10245 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) | |
10246 | ||
91ebb929 YM |
10247 | #define BCM_5710_UNDI_FW_MF_MAJOR (0x07) |
10248 | #define BCM_5710_UNDI_FW_MF_MINOR (0x08) | |
10249 | #define BCM_5710_UNDI_FW_MF_VERS (0x05) | |
b17b0ca1 YM |
10250 | |
10251 | static bool bnx2x_prev_is_after_undi(struct bnx2x *bp) | |
10252 | { | |
10253 | /* UNDI marks its presence in DORQ - | |
10254 | * it initializes CID offset for normal bell to 0x7 | |
10255 | */ | |
10256 | if (!(REG_RD(bp, MISC_REG_RESET_REG_1) & | |
10257 | MISC_REGISTERS_RESET_REG_1_RST_DORQ)) | |
10258 | return false; | |
10259 | ||
10260 | if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) { | |
10261 | BNX2X_DEV_INFO("UNDI previously loaded\n"); | |
10262 | return true; | |
10263 | } | |
10264 | ||
10265 | return false; | |
10266 | } | |
10267 | ||
7c3afd85 | 10268 | static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc) |
452427b0 YM |
10269 | { |
10270 | u16 rcq, bd; | |
7c3afd85 | 10271 | u32 addr, tmp_reg; |
452427b0 | 10272 | |
7c3afd85 YM |
10273 | if (BP_FUNC(bp) < 2) |
10274 | addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp)); | |
10275 | else | |
10276 | addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2); | |
10277 | ||
10278 | tmp_reg = REG_RD(bp, addr); | |
452427b0 YM |
10279 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; |
10280 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; | |
10281 | ||
10282 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); | |
7c3afd85 | 10283 | REG_WR(bp, addr, tmp_reg); |
452427b0 | 10284 | |
7c3afd85 YM |
10285 | BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n", |
10286 | BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq); | |
452427b0 YM |
10287 | } |
10288 | ||
0329aba1 | 10289 | static int bnx2x_prev_mcp_done(struct bnx2x *bp) |
452427b0 | 10290 | { |
5d07d868 YM |
10291 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, |
10292 | DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); | |
452427b0 YM |
10293 | if (!rc) { |
10294 | BNX2X_ERR("MCP response failure, aborting\n"); | |
10295 | return -EBUSY; | |
10296 | } | |
10297 | ||
10298 | return 0; | |
10299 | } | |
10300 | ||
c63da990 BW |
10301 | static struct bnx2x_prev_path_list * |
10302 | bnx2x_prev_path_get_entry(struct bnx2x *bp) | |
10303 | { | |
10304 | struct bnx2x_prev_path_list *tmp_list; | |
10305 | ||
10306 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) | |
10307 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
10308 | bp->pdev->bus->number == tmp_list->bus && | |
10309 | BP_PATH(bp) == tmp_list->path) | |
10310 | return tmp_list; | |
10311 | ||
10312 | return NULL; | |
10313 | } | |
10314 | ||
7fa6f340 YM |
10315 | static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) |
10316 | { | |
10317 | struct bnx2x_prev_path_list *tmp_list; | |
10318 | int rc; | |
10319 | ||
10320 | rc = down_interruptible(&bnx2x_prev_sem); | |
10321 | if (rc) { | |
10322 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
10323 | return rc; | |
10324 | } | |
10325 | ||
10326 | tmp_list = bnx2x_prev_path_get_entry(bp); | |
10327 | if (tmp_list) { | |
10328 | tmp_list->aer = 1; | |
10329 | rc = 0; | |
10330 | } else { | |
10331 | BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n", | |
10332 | BP_PATH(bp)); | |
10333 | } | |
10334 | ||
10335 | up(&bnx2x_prev_sem); | |
10336 | ||
10337 | return rc; | |
10338 | } | |
10339 | ||
0329aba1 | 10340 | static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) |
452427b0 YM |
10341 | { |
10342 | struct bnx2x_prev_path_list *tmp_list; | |
b85d717c | 10343 | bool rc = false; |
452427b0 YM |
10344 | |
10345 | if (down_trylock(&bnx2x_prev_sem)) | |
10346 | return false; | |
10347 | ||
7fa6f340 YM |
10348 | tmp_list = bnx2x_prev_path_get_entry(bp); |
10349 | if (tmp_list) { | |
10350 | if (tmp_list->aer) { | |
10351 | DP(NETIF_MSG_HW, "Path %d was marked by AER\n", | |
10352 | BP_PATH(bp)); | |
10353 | } else { | |
452427b0 YM |
10354 | rc = true; |
10355 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | |
10356 | BP_PATH(bp)); | |
452427b0 YM |
10357 | } |
10358 | } | |
10359 | ||
10360 | up(&bnx2x_prev_sem); | |
10361 | ||
10362 | return rc; | |
10363 | } | |
10364 | ||
178135c1 DK |
10365 | bool bnx2x_port_after_undi(struct bnx2x *bp) |
10366 | { | |
10367 | struct bnx2x_prev_path_list *entry; | |
10368 | bool val; | |
10369 | ||
10370 | down(&bnx2x_prev_sem); | |
10371 | ||
10372 | entry = bnx2x_prev_path_get_entry(bp); | |
10373 | val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); | |
10374 | ||
10375 | up(&bnx2x_prev_sem); | |
10376 | ||
10377 | return val; | |
10378 | } | |
10379 | ||
c63da990 | 10380 | static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) |
452427b0 YM |
10381 | { |
10382 | struct bnx2x_prev_path_list *tmp_list; | |
10383 | int rc; | |
10384 | ||
7fa6f340 YM |
10385 | rc = down_interruptible(&bnx2x_prev_sem); |
10386 | if (rc) { | |
10387 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
10388 | return rc; | |
10389 | } | |
10390 | ||
10391 | /* Check whether the entry for this path already exists */ | |
10392 | tmp_list = bnx2x_prev_path_get_entry(bp); | |
10393 | if (tmp_list) { | |
10394 | if (!tmp_list->aer) { | |
10395 | BNX2X_ERR("Re-Marking the path.\n"); | |
10396 | } else { | |
10397 | DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", | |
10398 | BP_PATH(bp)); | |
10399 | tmp_list->aer = 0; | |
10400 | } | |
10401 | up(&bnx2x_prev_sem); | |
10402 | return 0; | |
10403 | } | |
10404 | up(&bnx2x_prev_sem); | |
10405 | ||
10406 | /* Create an entry for this path and add it */ | |
ea4b3857 | 10407 | tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); |
452427b0 YM |
10408 | if (!tmp_list) { |
10409 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | |
10410 | return -ENOMEM; | |
10411 | } | |
10412 | ||
10413 | tmp_list->bus = bp->pdev->bus->number; | |
10414 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | |
10415 | tmp_list->path = BP_PATH(bp); | |
7fa6f340 | 10416 | tmp_list->aer = 0; |
c63da990 | 10417 | tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; |
452427b0 YM |
10418 | |
10419 | rc = down_interruptible(&bnx2x_prev_sem); | |
10420 | if (rc) { | |
10421 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
10422 | kfree(tmp_list); | |
10423 | } else { | |
7fa6f340 YM |
10424 | DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", |
10425 | BP_PATH(bp)); | |
452427b0 YM |
10426 | list_add(&tmp_list->list, &bnx2x_prev_list); |
10427 | up(&bnx2x_prev_sem); | |
10428 | } | |
10429 | ||
10430 | return rc; | |
10431 | } | |
10432 | ||
0329aba1 | 10433 | static int bnx2x_do_flr(struct bnx2x *bp) |
452427b0 | 10434 | { |
452427b0 YM |
10435 | struct pci_dev *dev = bp->pdev; |
10436 | ||
8eee694c YM |
10437 | if (CHIP_IS_E1x(bp)) { |
10438 | BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); | |
10439 | return -EINVAL; | |
10440 | } | |
10441 | ||
10442 | /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ | |
10443 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | |
10444 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | |
10445 | bp->common.bc_ver); | |
10446 | return -EINVAL; | |
10447 | } | |
452427b0 | 10448 | |
8903b9eb CL |
10449 | if (!pci_wait_for_pending_transaction(dev)) |
10450 | dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); | |
452427b0 | 10451 | |
8eee694c | 10452 | BNX2X_DEV_INFO("Initiating FLR\n"); |
452427b0 YM |
10453 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); |
10454 | ||
10455 | return 0; | |
10456 | } | |
10457 | ||
0329aba1 | 10458 | static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) |
452427b0 YM |
10459 | { |
10460 | int rc; | |
10461 | ||
10462 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); | |
10463 | ||
10464 | /* Test if previous unload process was already finished for this path */ | |
10465 | if (bnx2x_prev_is_path_marked(bp)) | |
10466 | return bnx2x_prev_mcp_done(bp); | |
10467 | ||
04c46736 YM |
10468 | BNX2X_DEV_INFO("Path is unmarked\n"); |
10469 | ||
b17b0ca1 YM |
10470 | /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */ |
10471 | if (bnx2x_prev_is_after_undi(bp)) | |
10472 | goto out; | |
10473 | ||
452427b0 YM |
10474 | /* If function has FLR capabilities, and existing FW version matches |
10475 | * the one required, then FLR will be sufficient to clean any residue | |
10476 | * left by previous driver | |
10477 | */ | |
91ebb929 | 10478 | rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false); |
8eee694c YM |
10479 | |
10480 | if (!rc) { | |
10481 | /* fw version is good */ | |
10482 | BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); | |
10483 | rc = bnx2x_do_flr(bp); | |
10484 | } | |
10485 | ||
10486 | if (!rc) { | |
10487 | /* FLR was performed */ | |
10488 | BNX2X_DEV_INFO("FLR successful\n"); | |
10489 | return 0; | |
10490 | } | |
10491 | ||
10492 | BNX2X_DEV_INFO("Could not FLR\n"); | |
452427b0 | 10493 | |
b17b0ca1 | 10494 | out: |
452427b0 YM |
10495 | /* Close the MCP request, return failure*/ |
10496 | rc = bnx2x_prev_mcp_done(bp); | |
10497 | if (!rc) | |
10498 | rc = BNX2X_PREV_WAIT_NEEDED; | |
10499 | ||
10500 | return rc; | |
10501 | } | |
10502 | ||
0329aba1 | 10503 | static int bnx2x_prev_unload_common(struct bnx2x *bp) |
452427b0 YM |
10504 | { |
10505 | u32 reset_reg, tmp_reg = 0, rc; | |
c63da990 | 10506 | bool prev_undi = false; |
1ef1d45a BW |
10507 | struct bnx2x_mac_vals mac_vals; |
10508 | ||
452427b0 YM |
10509 | /* It is possible a previous function received 'common' answer, |
10510 | * but hasn't loaded yet, therefore creating a scenario of | |
10511 | * multiple functions receiving 'common' on the same path. | |
10512 | */ | |
10513 | BNX2X_DEV_INFO("Common unload Flow\n"); | |
10514 | ||
1ef1d45a BW |
10515 | memset(&mac_vals, 0, sizeof(mac_vals)); |
10516 | ||
452427b0 YM |
10517 | if (bnx2x_prev_is_path_marked(bp)) |
10518 | return bnx2x_prev_mcp_done(bp); | |
10519 | ||
10520 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); | |
10521 | ||
10522 | /* Reset should be performed after BRB is emptied */ | |
10523 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { | |
10524 | u32 timer_count = 1000; | |
452427b0 YM |
10525 | |
10526 | /* Close the MAC Rx to prevent BRB from filling up */ | |
1ef1d45a BW |
10527 | bnx2x_prev_unload_close_mac(bp, &mac_vals); |
10528 | ||
3d6b7253 | 10529 | /* close LLH filters for both ports towards the BRB */ |
1ef1d45a | 10530 | bnx2x_set_rx_filter(&bp->link_params, 0); |
3d6b7253 | 10531 | bp->link_params.port ^= 1; |
1ef1d45a | 10532 | bnx2x_set_rx_filter(&bp->link_params, 0); |
3d6b7253 | 10533 | bp->link_params.port ^= 1; |
452427b0 | 10534 | |
b17b0ca1 YM |
10535 | /* Check if the UNDI driver was previously loaded */ |
10536 | if (bnx2x_prev_is_after_undi(bp)) { | |
10537 | prev_undi = true; | |
10538 | /* clear the UNDI indication */ | |
10539 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
10540 | /* clear possible idle check errors */ | |
10541 | REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); | |
452427b0 | 10542 | } |
d46f7c4d DK |
10543 | if (!CHIP_IS_E1x(bp)) |
10544 | /* block FW from writing to host */ | |
10545 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
10546 | ||
452427b0 YM |
10547 | /* wait until BRB is empty */ |
10548 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); | |
10549 | while (timer_count) { | |
10550 | u32 prev_brb = tmp_reg; | |
34f80b04 | 10551 | |
452427b0 YM |
10552 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
10553 | if (!tmp_reg) | |
10554 | break; | |
619c5cb6 | 10555 | |
452427b0 | 10556 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
619c5cb6 | 10557 | |
452427b0 YM |
10558 | /* reset timer as long as BRB actually gets emptied */ |
10559 | if (prev_brb > tmp_reg) | |
10560 | timer_count = 1000; | |
10561 | else | |
10562 | timer_count--; | |
da5a662a | 10563 | |
7c3afd85 YM |
10564 | /* If UNDI resides in memory, manually increment it */ |
10565 | if (prev_undi) | |
10566 | bnx2x_prev_unload_undi_inc(bp, 1); | |
10567 | ||
452427b0 | 10568 | udelay(10); |
7a06a122 | 10569 | } |
452427b0 YM |
10570 | |
10571 | if (!timer_count) | |
10572 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); | |
34f80b04 | 10573 | } |
f16da43b | 10574 | |
452427b0 YM |
10575 | /* No packets are in the pipeline, path is ready for reset */ |
10576 | bnx2x_reset_common(bp); | |
10577 | ||
1ef1d45a BW |
10578 | if (mac_vals.xmac_addr) |
10579 | REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); | |
3d6b7253 YM |
10580 | if (mac_vals.umac_addr[0]) |
10581 | REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); | |
10582 | if (mac_vals.umac_addr[1]) | |
10583 | REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); | |
1ef1d45a BW |
10584 | if (mac_vals.emac_addr) |
10585 | REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); | |
10586 | if (mac_vals.bmac_addr) { | |
10587 | REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); | |
10588 | REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); | |
10589 | } | |
10590 | ||
c63da990 | 10591 | rc = bnx2x_prev_mark_path(bp, prev_undi); |
452427b0 YM |
10592 | if (rc) { |
10593 | bnx2x_prev_mcp_done(bp); | |
10594 | return rc; | |
10595 | } | |
10596 | ||
10597 | return bnx2x_prev_mcp_done(bp); | |
10598 | } | |
10599 | ||
0329aba1 | 10600 | static int bnx2x_prev_unload(struct bnx2x *bp) |
452427b0 YM |
10601 | { |
10602 | int time_counter = 10; | |
10603 | u32 rc, fw, hw_lock_reg, hw_lock_val; | |
10604 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); | |
10605 | ||
24f06716 AE |
10606 | /* clear hw from errors which may have resulted from an interrupted |
10607 | * dmae transaction. | |
10608 | */ | |
da254fbc | 10609 | bnx2x_clean_pglue_errors(bp); |
24f06716 AE |
10610 | |
10611 | /* Release previously held locks */ | |
452427b0 YM |
10612 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? |
10613 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : | |
10614 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); | |
10615 | ||
3cdeec22 | 10616 | hw_lock_val = REG_RD(bp, hw_lock_reg); |
452427b0 YM |
10617 | if (hw_lock_val) { |
10618 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { | |
10619 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); | |
10620 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
10621 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); | |
10622 | } | |
10623 | ||
10624 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); | |
10625 | REG_WR(bp, hw_lock_reg, 0xffffffff); | |
10626 | } else | |
10627 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); | |
10628 | ||
10629 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { | |
10630 | BNX2X_DEV_INFO("Release previously held alr\n"); | |
3cdeec22 | 10631 | bnx2x_release_alr(bp); |
452427b0 YM |
10632 | } |
10633 | ||
452427b0 | 10634 | do { |
7fa6f340 | 10635 | int aer = 0; |
452427b0 YM |
10636 | /* Lock MCP using an unload request */ |
10637 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | |
10638 | if (!fw) { | |
10639 | BNX2X_ERR("MCP response failure, aborting\n"); | |
10640 | rc = -EBUSY; | |
10641 | break; | |
10642 | } | |
10643 | ||
7fa6f340 YM |
10644 | rc = down_interruptible(&bnx2x_prev_sem); |
10645 | if (rc) { | |
10646 | BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n", | |
10647 | rc); | |
10648 | } else { | |
10649 | /* If Path is marked by EEH, ignore unload status */ | |
10650 | aer = !!(bnx2x_prev_path_get_entry(bp) && | |
10651 | bnx2x_prev_path_get_entry(bp)->aer); | |
60cde81f | 10652 | up(&bnx2x_prev_sem); |
7fa6f340 | 10653 | } |
7fa6f340 YM |
10654 | |
10655 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) { | |
452427b0 YM |
10656 | rc = bnx2x_prev_unload_common(bp); |
10657 | break; | |
10658 | } | |
10659 | ||
16a5fd92 | 10660 | /* non-common reply from MCP might require looping */ |
452427b0 YM |
10661 | rc = bnx2x_prev_unload_uncommon(bp); |
10662 | if (rc != BNX2X_PREV_WAIT_NEEDED) | |
10663 | break; | |
10664 | ||
10665 | msleep(20); | |
10666 | } while (--time_counter); | |
10667 | ||
10668 | if (!time_counter || rc) { | |
91ebb929 YM |
10669 | BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n"); |
10670 | rc = -EPROBE_DEFER; | |
452427b0 YM |
10671 | } |
10672 | ||
c63da990 | 10673 | /* Mark function if its port was used to boot from SAN */ |
178135c1 | 10674 | if (bnx2x_port_after_undi(bp)) |
c63da990 BW |
10675 | bp->link_params.feature_config_flags |= |
10676 | FEATURE_CONFIG_BOOT_FROM_SAN; | |
10677 | ||
452427b0 YM |
10678 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); |
10679 | ||
10680 | return rc; | |
34f80b04 EG |
10681 | } |
10682 | ||
0329aba1 | 10683 | static void bnx2x_get_common_hwinfo(struct bnx2x *bp) |
34f80b04 | 10684 | { |
1d187b34 | 10685 | u32 val, val2, val3, val4, id, boot_mode; |
72ce58c3 | 10686 | u16 pmc; |
34f80b04 EG |
10687 | |
10688 | /* Get the chip revision id and number. */ | |
10689 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
10690 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
10691 | id = ((val & 0xffff) << 16); | |
10692 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
10693 | id |= ((val & 0xf) << 12); | |
f22fdf25 YM |
10694 | |
10695 | /* Metal is read from PCI regs, but we can't access >=0x400 from | |
10696 | * the configuration space (so we need to reg_rd) | |
10697 | */ | |
10698 | val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); | |
10699 | id |= (((val >> 24) & 0xf) << 4); | |
5a40e08e | 10700 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
10701 | id |= (val & 0xf); |
10702 | bp->common.chip_id = id; | |
523224a3 | 10703 | |
7e8e02df BW |
10704 | /* force 57811 according to MISC register */ |
10705 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { | |
10706 | if (CHIP_IS_57810(bp)) | |
10707 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | | |
10708 | (bp->common.chip_id & 0x0000FFFF); | |
10709 | else if (CHIP_IS_57810_MF(bp)) | |
10710 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | | |
10711 | (bp->common.chip_id & 0x0000FFFF); | |
10712 | bp->common.chip_id |= 0x1; | |
10713 | } | |
10714 | ||
523224a3 DK |
10715 | /* Set doorbell size */ |
10716 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
10717 | ||
619c5cb6 | 10718 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
10719 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
10720 | if ((val & 1) == 0) | |
10721 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
10722 | else | |
10723 | val = (val >> 1) & 1; | |
10724 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
10725 | "2_PORT_MODE"); | |
10726 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
10727 | CHIP_2_PORT_MODE; | |
10728 | ||
10729 | if (CHIP_MODE_IS_4_PORT(bp)) | |
10730 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
10731 | else | |
10732 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
10733 | } else { | |
10734 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
10735 | bp->pfid = bp->pf_num; /* 0..7 */ | |
10736 | } | |
10737 | ||
51c1a580 MS |
10738 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
10739 | ||
f2e0899f DK |
10740 | bp->link_params.chip_id = bp->common.chip_id; |
10741 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 10742 | |
1c06328c EG |
10743 | val = (REG_RD(bp, 0x2874) & 0x55); |
10744 | if ((bp->common.chip_id & 0x1) || | |
10745 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
10746 | bp->flags |= ONE_PORT_FLAG; | |
10747 | BNX2X_DEV_INFO("single port device\n"); | |
10748 | } | |
10749 | ||
34f80b04 | 10750 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 10751 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
10752 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
10753 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
10754 | bp->common.flash_size, bp->common.flash_size); | |
10755 | ||
1b6e2ceb DK |
10756 | bnx2x_init_shmem(bp); |
10757 | ||
f2e0899f DK |
10758 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
10759 | MISC_REG_GENERIC_CR_1 : | |
10760 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 10761 | |
34f80b04 | 10762 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 10763 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
b884d95b YR |
10764 | if (SHMEM2_RD(bp, size) > |
10765 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
10766 | bp->link_params.lfa_base = | |
10767 | REG_RD(bp, bp->common.shmem2_base + | |
10768 | (u32)offsetof(struct shmem2_region, | |
10769 | lfa_host_addr[BP_PORT(bp)])); | |
10770 | else | |
10771 | bp->link_params.lfa_base = 0; | |
2691d51d EG |
10772 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
10773 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 10774 | |
f2e0899f | 10775 | if (!bp->common.shmem_base) { |
34f80b04 EG |
10776 | BNX2X_DEV_INFO("MCP not active\n"); |
10777 | bp->flags |= NO_MCP_FLAG; | |
10778 | return; | |
10779 | } | |
10780 | ||
34f80b04 | 10781 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 10782 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
10783 | |
10784 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
10785 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
10786 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
10787 | ||
c2c8b03e EG |
10788 | bp->link_params.feature_config_flags = 0; |
10789 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
10790 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
10791 | bp->link_params.feature_config_flags |= | |
10792 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
10793 | else | |
10794 | bp->link_params.feature_config_flags &= | |
10795 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
10796 | ||
34f80b04 EG |
10797 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
10798 | bp->common.bc_ver = val; | |
10799 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
10800 | if (val < BNX2X_BC_VER) { | |
10801 | /* for now only warn | |
10802 | * later we might need to enforce this */ | |
51c1a580 MS |
10803 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
10804 | BNX2X_BC_VER, val); | |
34f80b04 | 10805 | } |
4d295db0 | 10806 | bp->link_params.feature_config_flags |= |
a22f0788 | 10807 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
10808 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
10809 | ||
a22f0788 YR |
10810 | bp->link_params.feature_config_flags |= |
10811 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
10812 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
a3348722 BW |
10813 | bp->link_params.feature_config_flags |= |
10814 | (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? | |
10815 | FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; | |
85242eea YR |
10816 | bp->link_params.feature_config_flags |= |
10817 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
10818 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
55386fe8 YR |
10819 | |
10820 | bp->link_params.feature_config_flags |= | |
10821 | (val >= REQ_BC_VER_4_MT_SUPPORTED) ? | |
10822 | FEATURE_CONFIG_MT_SUPPORT : 0; | |
10823 | ||
0e898dd7 BW |
10824 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
10825 | BC_SUPPORTS_PFC_STATS : 0; | |
85242eea | 10826 | |
2e499d3c BW |
10827 | bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? |
10828 | BC_SUPPORTS_FCOE_FEATURES : 0; | |
10829 | ||
9876879f BW |
10830 | bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? |
10831 | BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; | |
a6d3a5ba BW |
10832 | |
10833 | bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? | |
10834 | BC_SUPPORTS_RMMOD_CMD : 0; | |
10835 | ||
1d187b34 BW |
10836 | boot_mode = SHMEM_RD(bp, |
10837 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & | |
10838 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; | |
10839 | switch (boot_mode) { | |
10840 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: | |
10841 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; | |
10842 | break; | |
10843 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: | |
10844 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; | |
10845 | break; | |
10846 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: | |
10847 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; | |
10848 | break; | |
10849 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: | |
10850 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; | |
10851 | break; | |
10852 | } | |
10853 | ||
29ed74c3 | 10854 | pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc); |
f9a3ebbe DK |
10855 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; |
10856 | ||
72ce58c3 | 10857 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 10858 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
10859 | |
10860 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
10861 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
10862 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
10863 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
10864 | ||
cdaa7cb8 VZ |
10865 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
10866 | val, val2, val3, val4); | |
34f80b04 EG |
10867 | } |
10868 | ||
f2e0899f DK |
10869 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
10870 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
10871 | ||
0329aba1 | 10872 | static int bnx2x_get_igu_cam_info(struct bnx2x *bp) |
f2e0899f DK |
10873 | { |
10874 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
10875 | int igu_sb_id; |
10876 | u32 val; | |
6383c0b3 | 10877 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
10878 | |
10879 | bp->igu_base_sb = 0xff; | |
f2e0899f | 10880 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 10881 | int vn = BP_VN(bp); |
6383c0b3 | 10882 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
10883 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
10884 | FP_SB_MAX_E1x; | |
10885 | ||
10886 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
10887 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
10888 | ||
9b341bb1 | 10889 | return 0; |
f2e0899f DK |
10890 | } |
10891 | ||
10892 | /* IGU in normal mode - read CAM */ | |
10893 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
10894 | igu_sb_id++) { | |
10895 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
10896 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
10897 | continue; | |
10898 | fid = IGU_FID(val); | |
10899 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
10900 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
10901 | continue; | |
10902 | if (IGU_VEC(val) == 0) | |
10903 | /* default status block */ | |
10904 | bp->igu_dsb_id = igu_sb_id; | |
10905 | else { | |
10906 | if (bp->igu_base_sb == 0xff) | |
10907 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 10908 | igu_sb_cnt++; |
f2e0899f DK |
10909 | } |
10910 | } | |
10911 | } | |
619c5cb6 | 10912 | |
6383c0b3 | 10913 | #ifdef CONFIG_PCI_MSI |
185d4c8b AE |
10914 | /* Due to new PF resource allocation by MFW T7.4 and above, it's |
10915 | * optional that number of CAM entries will not be equal to the value | |
10916 | * advertised in PCI. | |
10917 | * Driver should use the minimal value of both as the actual status | |
10918 | * block count | |
619c5cb6 | 10919 | */ |
185d4c8b | 10920 | bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); |
6383c0b3 | 10921 | #endif |
619c5cb6 | 10922 | |
9b341bb1 | 10923 | if (igu_sb_cnt == 0) { |
f2e0899f | 10924 | BNX2X_ERR("CAM configuration error\n"); |
9b341bb1 BW |
10925 | return -EINVAL; |
10926 | } | |
10927 | ||
10928 | return 0; | |
f2e0899f DK |
10929 | } |
10930 | ||
1dd06ae8 | 10931 | static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) |
a2fbb9ea | 10932 | { |
a22f0788 YR |
10933 | int cfg_size = 0, idx, port = BP_PORT(bp); |
10934 | ||
10935 | /* Aggregation of supported attributes of all external phys */ | |
10936 | bp->port.supported[0] = 0; | |
10937 | bp->port.supported[1] = 0; | |
b7737c9b YR |
10938 | switch (bp->link_params.num_phys) { |
10939 | case 1: | |
a22f0788 YR |
10940 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
10941 | cfg_size = 1; | |
10942 | break; | |
b7737c9b | 10943 | case 2: |
a22f0788 YR |
10944 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
10945 | cfg_size = 1; | |
10946 | break; | |
10947 | case 3: | |
10948 | if (bp->link_params.multi_phy_config & | |
10949 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
10950 | bp->port.supported[1] = | |
10951 | bp->link_params.phy[EXT_PHY1].supported; | |
10952 | bp->port.supported[0] = | |
10953 | bp->link_params.phy[EXT_PHY2].supported; | |
10954 | } else { | |
10955 | bp->port.supported[0] = | |
10956 | bp->link_params.phy[EXT_PHY1].supported; | |
10957 | bp->port.supported[1] = | |
10958 | bp->link_params.phy[EXT_PHY2].supported; | |
10959 | } | |
10960 | cfg_size = 2; | |
10961 | break; | |
b7737c9b | 10962 | } |
a2fbb9ea | 10963 | |
a22f0788 | 10964 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
51c1a580 | 10965 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 10966 | SHMEM_RD(bp, |
a22f0788 YR |
10967 | dev_info.port_hw_config[port].external_phy_config), |
10968 | SHMEM_RD(bp, | |
10969 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 10970 | return; |
f85582f8 | 10971 | } |
a2fbb9ea | 10972 | |
619c5cb6 VZ |
10973 | if (CHIP_IS_E3(bp)) |
10974 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
10975 | else { | |
10976 | switch (switch_cfg) { | |
10977 | case SWITCH_CFG_1G: | |
10978 | bp->port.phy_addr = REG_RD( | |
10979 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
10980 | break; | |
10981 | case SWITCH_CFG_10G: | |
10982 | bp->port.phy_addr = REG_RD( | |
10983 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
10984 | break; | |
10985 | default: | |
10986 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
10987 | bp->port.link_config[0]); | |
10988 | return; | |
10989 | } | |
a2fbb9ea | 10990 | } |
619c5cb6 | 10991 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
10992 | /* mask what we support according to speed_cap_mask per configuration */ |
10993 | for (idx = 0; idx < cfg_size; idx++) { | |
10994 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 10995 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 10996 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 10997 | |
a22f0788 | 10998 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10999 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 11000 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 11001 | |
a22f0788 | 11002 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11003 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 11004 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 11005 | |
a22f0788 | 11006 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11007 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 11008 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 11009 | |
a22f0788 | 11010 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11011 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 11012 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 11013 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 11014 | |
a22f0788 | 11015 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11016 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 11017 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 11018 | |
a22f0788 | 11019 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11020 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 | 11021 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
b8e0d884 YR |
11022 | |
11023 | if (!(bp->link_params.speed_cap_mask[idx] & | |
11024 | PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) | |
11025 | bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; | |
a22f0788 | 11026 | } |
a2fbb9ea | 11027 | |
a22f0788 YR |
11028 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
11029 | bp->port.supported[1]); | |
a2fbb9ea ET |
11030 | } |
11031 | ||
0329aba1 | 11032 | static void bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 11033 | { |
a22f0788 YR |
11034 | u32 link_config, idx, cfg_size = 0; |
11035 | bp->port.advertising[0] = 0; | |
11036 | bp->port.advertising[1] = 0; | |
11037 | switch (bp->link_params.num_phys) { | |
11038 | case 1: | |
11039 | case 2: | |
11040 | cfg_size = 1; | |
11041 | break; | |
11042 | case 3: | |
11043 | cfg_size = 2; | |
11044 | break; | |
11045 | } | |
11046 | for (idx = 0; idx < cfg_size; idx++) { | |
11047 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
11048 | link_config = bp->port.link_config[idx]; | |
11049 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 11050 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
11051 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
11052 | bp->link_params.req_line_speed[idx] = | |
11053 | SPEED_AUTO_NEG; | |
11054 | bp->port.advertising[idx] |= | |
11055 | bp->port.supported[idx]; | |
10bd1f24 MY |
11056 | if (bp->link_params.phy[EXT_PHY1].type == |
11057 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
11058 | bp->port.advertising[idx] |= | |
11059 | (SUPPORTED_100baseT_Half | | |
11060 | SUPPORTED_100baseT_Full); | |
f85582f8 DK |
11061 | } else { |
11062 | /* force 10G, no AN */ | |
a22f0788 YR |
11063 | bp->link_params.req_line_speed[idx] = |
11064 | SPEED_10000; | |
11065 | bp->port.advertising[idx] |= | |
11066 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 11067 | ADVERTISED_FIBRE); |
a22f0788 | 11068 | continue; |
f85582f8 DK |
11069 | } |
11070 | break; | |
a2fbb9ea | 11071 | |
f85582f8 | 11072 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
11073 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
11074 | bp->link_params.req_line_speed[idx] = | |
11075 | SPEED_10; | |
11076 | bp->port.advertising[idx] |= | |
11077 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
11078 | ADVERTISED_TP); |
11079 | } else { | |
51c1a580 | 11080 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 | 11081 | link_config, |
a22f0788 | 11082 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
11083 | return; |
11084 | } | |
11085 | break; | |
a2fbb9ea | 11086 | |
f85582f8 | 11087 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
11088 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
11089 | bp->link_params.req_line_speed[idx] = | |
11090 | SPEED_10; | |
11091 | bp->link_params.req_duplex[idx] = | |
11092 | DUPLEX_HALF; | |
11093 | bp->port.advertising[idx] |= | |
11094 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
11095 | ADVERTISED_TP); |
11096 | } else { | |
51c1a580 | 11097 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
11098 | link_config, |
11099 | bp->link_params.speed_cap_mask[idx]); | |
11100 | return; | |
11101 | } | |
11102 | break; | |
a2fbb9ea | 11103 | |
f85582f8 DK |
11104 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
11105 | if (bp->port.supported[idx] & | |
11106 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
11107 | bp->link_params.req_line_speed[idx] = |
11108 | SPEED_100; | |
11109 | bp->port.advertising[idx] |= | |
11110 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
11111 | ADVERTISED_TP); |
11112 | } else { | |
51c1a580 | 11113 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
11114 | link_config, |
11115 | bp->link_params.speed_cap_mask[idx]); | |
11116 | return; | |
11117 | } | |
11118 | break; | |
a2fbb9ea | 11119 | |
f85582f8 DK |
11120 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
11121 | if (bp->port.supported[idx] & | |
11122 | SUPPORTED_100baseT_Half) { | |
11123 | bp->link_params.req_line_speed[idx] = | |
11124 | SPEED_100; | |
11125 | bp->link_params.req_duplex[idx] = | |
11126 | DUPLEX_HALF; | |
a22f0788 YR |
11127 | bp->port.advertising[idx] |= |
11128 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
11129 | ADVERTISED_TP); |
11130 | } else { | |
51c1a580 | 11131 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
11132 | link_config, |
11133 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
11134 | return; |
11135 | } | |
11136 | break; | |
a2fbb9ea | 11137 | |
f85582f8 | 11138 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
11139 | if (bp->port.supported[idx] & |
11140 | SUPPORTED_1000baseT_Full) { | |
11141 | bp->link_params.req_line_speed[idx] = | |
11142 | SPEED_1000; | |
11143 | bp->port.advertising[idx] |= | |
11144 | (ADVERTISED_1000baseT_Full | | |
f85582f8 | 11145 | ADVERTISED_TP); |
5d67c1c5 YM |
11146 | } else if (bp->port.supported[idx] & |
11147 | SUPPORTED_1000baseKX_Full) { | |
11148 | bp->link_params.req_line_speed[idx] = | |
11149 | SPEED_1000; | |
11150 | bp->port.advertising[idx] |= | |
11151 | ADVERTISED_1000baseKX_Full; | |
f85582f8 | 11152 | } else { |
51c1a580 | 11153 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
11154 | link_config, |
11155 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
11156 | return; |
11157 | } | |
11158 | break; | |
a2fbb9ea | 11159 | |
f85582f8 | 11160 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
11161 | if (bp->port.supported[idx] & |
11162 | SUPPORTED_2500baseX_Full) { | |
11163 | bp->link_params.req_line_speed[idx] = | |
11164 | SPEED_2500; | |
11165 | bp->port.advertising[idx] |= | |
11166 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 11167 | ADVERTISED_TP); |
f85582f8 | 11168 | } else { |
51c1a580 | 11169 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 11170 | link_config, |
f85582f8 DK |
11171 | bp->link_params.speed_cap_mask[idx]); |
11172 | return; | |
11173 | } | |
11174 | break; | |
a2fbb9ea | 11175 | |
f85582f8 | 11176 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
11177 | if (bp->port.supported[idx] & |
11178 | SUPPORTED_10000baseT_Full) { | |
11179 | bp->link_params.req_line_speed[idx] = | |
11180 | SPEED_10000; | |
11181 | bp->port.advertising[idx] |= | |
11182 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 11183 | ADVERTISED_FIBRE); |
5d67c1c5 YM |
11184 | } else if (bp->port.supported[idx] & |
11185 | SUPPORTED_10000baseKR_Full) { | |
11186 | bp->link_params.req_line_speed[idx] = | |
11187 | SPEED_10000; | |
11188 | bp->port.advertising[idx] |= | |
11189 | (ADVERTISED_10000baseKR_Full | | |
11190 | ADVERTISED_FIBRE); | |
f85582f8 | 11191 | } else { |
51c1a580 | 11192 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 11193 | link_config, |
f85582f8 DK |
11194 | bp->link_params.speed_cap_mask[idx]); |
11195 | return; | |
11196 | } | |
11197 | break; | |
3c9ada22 YR |
11198 | case PORT_FEATURE_LINK_SPEED_20G: |
11199 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 11200 | |
3c9ada22 | 11201 | break; |
f85582f8 | 11202 | default: |
51c1a580 | 11203 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
754a2f52 | 11204 | link_config); |
f85582f8 DK |
11205 | bp->link_params.req_line_speed[idx] = |
11206 | SPEED_AUTO_NEG; | |
11207 | bp->port.advertising[idx] = | |
11208 | bp->port.supported[idx]; | |
11209 | break; | |
11210 | } | |
a2fbb9ea | 11211 | |
a22f0788 | 11212 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 11213 | PORT_FEATURE_FLOW_CONTROL_MASK); |
cd1dfce2 YM |
11214 | if (bp->link_params.req_flow_ctrl[idx] == |
11215 | BNX2X_FLOW_CTRL_AUTO) { | |
11216 | if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) | |
11217 | bp->link_params.req_flow_ctrl[idx] = | |
11218 | BNX2X_FLOW_CTRL_NONE; | |
11219 | else | |
11220 | bnx2x_set_requested_fc(bp); | |
a22f0788 | 11221 | } |
a2fbb9ea | 11222 | |
51c1a580 | 11223 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
a22f0788 YR |
11224 | bp->link_params.req_line_speed[idx], |
11225 | bp->link_params.req_duplex[idx], | |
11226 | bp->link_params.req_flow_ctrl[idx], | |
11227 | bp->port.advertising[idx]); | |
11228 | } | |
a2fbb9ea ET |
11229 | } |
11230 | ||
0329aba1 | 11231 | static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
e665bfda | 11232 | { |
86564c3f YM |
11233 | __be16 mac_hi_be = cpu_to_be16(mac_hi); |
11234 | __be32 mac_lo_be = cpu_to_be32(mac_lo); | |
11235 | memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be)); | |
11236 | memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be)); | |
e665bfda MC |
11237 | } |
11238 | ||
0329aba1 | 11239 | static void bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 11240 | { |
34f80b04 | 11241 | int port = BP_PORT(bp); |
589abe3a | 11242 | u32 config; |
c8c60d88 | 11243 | u32 ext_phy_type, ext_phy_config, eee_mode; |
a2fbb9ea | 11244 | |
c18487ee | 11245 | bp->link_params.bp = bp; |
34f80b04 | 11246 | bp->link_params.port = port; |
c18487ee | 11247 | |
c18487ee | 11248 | bp->link_params.lane_config = |
a2fbb9ea | 11249 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 11250 | |
a22f0788 | 11251 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea | 11252 | SHMEM_RD(bp, |
b0261926 YR |
11253 | dev_info.port_hw_config[port].speed_capability_mask) & |
11254 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | |
a22f0788 YR |
11255 | bp->link_params.speed_cap_mask[1] = |
11256 | SHMEM_RD(bp, | |
b0261926 YR |
11257 | dev_info.port_hw_config[port].speed_capability_mask2) & |
11258 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | |
a22f0788 | 11259 | bp->port.link_config[0] = |
a2fbb9ea ET |
11260 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
11261 | ||
a22f0788 YR |
11262 | bp->port.link_config[1] = |
11263 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 11264 | |
a22f0788 YR |
11265 | bp->link_params.multi_phy_config = |
11266 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
11267 | /* If the device is capable of WoL, set the default state according |
11268 | * to the HW | |
11269 | */ | |
4d295db0 | 11270 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
11271 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
11272 | (config & PORT_FEATURE_WOL_ENABLED)); | |
11273 | ||
4ba7699b YM |
11274 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == |
11275 | PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) | |
11276 | bp->flags |= NO_ISCSI_FLAG; | |
11277 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == | |
11278 | PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) | |
11279 | bp->flags |= NO_FCOE_FLAG; | |
11280 | ||
51c1a580 | 11281 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 11282 | bp->link_params.lane_config, |
a22f0788 YR |
11283 | bp->link_params.speed_cap_mask[0], |
11284 | bp->port.link_config[0]); | |
a2fbb9ea | 11285 | |
a22f0788 | 11286 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 11287 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 11288 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 11289 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
11290 | |
11291 | bnx2x_link_settings_requested(bp); | |
11292 | ||
01cd4528 EG |
11293 | /* |
11294 | * If connected directly, work with the internal PHY, otherwise, work | |
11295 | * with the external PHY | |
11296 | */ | |
b7737c9b YR |
11297 | ext_phy_config = |
11298 | SHMEM_RD(bp, | |
11299 | dev_info.port_hw_config[port].external_phy_config); | |
11300 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 11301 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 11302 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
11303 | |
11304 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
11305 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
11306 | bp->mdio.prtad = | |
b7737c9b | 11307 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d | 11308 | |
c8c60d88 YM |
11309 | /* Configure link feature according to nvram value */ |
11310 | eee_mode = (((SHMEM_RD(bp, dev_info. | |
11311 | port_feature_config[port].eee_power_mode)) & | |
11312 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
11313 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
11314 | if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { | |
11315 | bp->link_params.eee_mode = EEE_MODE_ADV_LPI | | |
11316 | EEE_MODE_ENABLE_LPI | | |
11317 | EEE_MODE_OUTPUT_TIME; | |
11318 | } else { | |
11319 | bp->link_params.eee_mode = 0; | |
11320 | } | |
0793f83f | 11321 | } |
01cd4528 | 11322 | |
b306f5ed | 11323 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 11324 | { |
9e62e912 | 11325 | u32 no_flags = NO_ISCSI_FLAG; |
bf61ee14 | 11326 | int port = BP_PORT(bp); |
2ba45142 | 11327 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 11328 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 11329 | |
55c11941 MS |
11330 | if (!CNIC_SUPPORT(bp)) { |
11331 | bp->flags |= no_flags; | |
11332 | return; | |
11333 | } | |
11334 | ||
b306f5ed | 11335 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
11336 | bp->cnic_eth_dev.max_iscsi_conn = |
11337 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
11338 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
11339 | ||
b306f5ed DK |
11340 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
11341 | bp->cnic_eth_dev.max_iscsi_conn); | |
11342 | ||
11343 | /* | |
11344 | * If maximum allowed number of connections is zero - | |
11345 | * disable the feature. | |
11346 | */ | |
11347 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9e62e912 | 11348 | bp->flags |= no_flags; |
b306f5ed DK |
11349 | } |
11350 | ||
0329aba1 | 11351 | static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) |
9e62e912 DK |
11352 | { |
11353 | /* Port info */ | |
11354 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
11355 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); | |
11356 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
11357 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); | |
11358 | ||
11359 | /* Node info */ | |
11360 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
11361 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); | |
11362 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
11363 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); | |
11364 | } | |
86800194 DK |
11365 | |
11366 | static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) | |
11367 | { | |
11368 | u8 count = 0; | |
11369 | ||
11370 | if (IS_MF(bp)) { | |
11371 | u8 fid; | |
11372 | ||
11373 | /* iterate over absolute function ids for this path: */ | |
11374 | for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { | |
11375 | if (IS_MF_SD(bp)) { | |
11376 | u32 cfg = MF_CFG_RD(bp, | |
11377 | func_mf_config[fid].config); | |
11378 | ||
11379 | if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) && | |
11380 | ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) == | |
11381 | FUNC_MF_CFG_PROTOCOL_FCOE)) | |
11382 | count++; | |
11383 | } else { | |
11384 | u32 cfg = MF_CFG_RD(bp, | |
11385 | func_ext_config[fid]. | |
11386 | func_cfg); | |
11387 | ||
11388 | if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) && | |
11389 | (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)) | |
11390 | count++; | |
11391 | } | |
11392 | } | |
11393 | } else { /* SF */ | |
11394 | int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; | |
11395 | ||
11396 | for (port = 0; port < port_cnt; port++) { | |
11397 | u32 lic = SHMEM_RD(bp, | |
11398 | drv_lic_key[port].max_fcoe_conn) ^ | |
11399 | FW_ENCODE_32BIT_PATTERN; | |
11400 | if (lic) | |
11401 | count++; | |
11402 | } | |
11403 | } | |
11404 | ||
11405 | return count; | |
11406 | } | |
11407 | ||
0329aba1 | 11408 | static void bnx2x_get_fcoe_info(struct bnx2x *bp) |
b306f5ed DK |
11409 | { |
11410 | int port = BP_PORT(bp); | |
11411 | int func = BP_ABS_FUNC(bp); | |
b306f5ed DK |
11412 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
11413 | drv_lic_key[port].max_fcoe_conn); | |
86800194 | 11414 | u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); |
b306f5ed | 11415 | |
55c11941 MS |
11416 | if (!CNIC_SUPPORT(bp)) { |
11417 | bp->flags |= NO_FCOE_FLAG; | |
11418 | return; | |
11419 | } | |
11420 | ||
b306f5ed | 11421 | /* Get the number of maximum allowed FCoE connections */ |
2ba45142 VZ |
11422 | bp->cnic_eth_dev.max_fcoe_conn = |
11423 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
11424 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
11425 | ||
0eb43b4b BPG |
11426 | /* Calculate the number of maximum allowed FCoE tasks */ |
11427 | bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; | |
86800194 DK |
11428 | |
11429 | /* check if FCoE resources must be shared between different functions */ | |
11430 | if (num_fcoe_func) | |
11431 | bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; | |
0eb43b4b | 11432 | |
bf61ee14 VZ |
11433 | /* Read the WWN: */ |
11434 | if (!IS_MF(bp)) { | |
11435 | /* Port info */ | |
11436 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
11437 | SHMEM_RD(bp, | |
2de67439 | 11438 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11439 | fcoe_wwn_port_name_upper); |
11440 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
11441 | SHMEM_RD(bp, | |
2de67439 | 11442 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11443 | fcoe_wwn_port_name_lower); |
11444 | ||
11445 | /* Node info */ | |
11446 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
11447 | SHMEM_RD(bp, | |
2de67439 | 11448 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11449 | fcoe_wwn_node_name_upper); |
11450 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
11451 | SHMEM_RD(bp, | |
2de67439 | 11452 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11453 | fcoe_wwn_node_name_lower); |
11454 | } else if (!IS_MF_SD(bp)) { | |
2e98ffc2 | 11455 | /* Read the WWN info only if the FCoE feature is enabled for |
bf61ee14 VZ |
11456 | * this function. |
11457 | */ | |
2e98ffc2 DK |
11458 | if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp)) |
11459 | bnx2x_get_ext_wwn_info(bp, func); | |
11460 | } else { | |
11461 | if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) | |
9e62e912 | 11462 | bnx2x_get_ext_wwn_info(bp, func); |
382e513a | 11463 | } |
bf61ee14 | 11464 | |
b306f5ed | 11465 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 11466 | |
bf61ee14 VZ |
11467 | /* |
11468 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
11469 | * disable the feature. |
11470 | */ | |
2ba45142 VZ |
11471 | if (!bp->cnic_eth_dev.max_fcoe_conn) |
11472 | bp->flags |= NO_FCOE_FLAG; | |
11473 | } | |
b306f5ed | 11474 | |
0329aba1 | 11475 | static void bnx2x_get_cnic_info(struct bnx2x *bp) |
b306f5ed DK |
11476 | { |
11477 | /* | |
11478 | * iSCSI may be dynamically disabled but reading | |
11479 | * info here we will decrease memory usage by driver | |
11480 | * if the feature is disabled for good | |
11481 | */ | |
11482 | bnx2x_get_iscsi_info(bp); | |
11483 | bnx2x_get_fcoe_info(bp); | |
11484 | } | |
2ba45142 | 11485 | |
0329aba1 | 11486 | static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) |
0793f83f DK |
11487 | { |
11488 | u32 val, val2; | |
11489 | int func = BP_ABS_FUNC(bp); | |
11490 | int port = BP_PORT(bp); | |
2ba45142 VZ |
11491 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; |
11492 | u8 *fip_mac = bp->fip_mac; | |
0793f83f | 11493 | |
55c11941 MS |
11494 | if (IS_MF(bp)) { |
11495 | /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or | |
2ba45142 | 11496 | * FCoE MAC then the appropriate feature should be disabled. |
55c11941 MS |
11497 | * In non SD mode features configuration comes from struct |
11498 | * func_ext_config. | |
2ba45142 | 11499 | */ |
2e98ffc2 | 11500 | if (!IS_MF_SD(bp)) { |
0793f83f DK |
11501 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
11502 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
11503 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 11504 | iscsi_mac_addr_upper); |
0793f83f | 11505 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 11506 | iscsi_mac_addr_lower); |
2ba45142 | 11507 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
55c11941 MS |
11508 | BNX2X_DEV_INFO |
11509 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
11510 | } else { | |
2ba45142 | 11511 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
55c11941 | 11512 | } |
2ba45142 VZ |
11513 | |
11514 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
11515 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 11516 | fcoe_mac_addr_upper); |
2ba45142 | 11517 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 11518 | fcoe_mac_addr_lower); |
2ba45142 | 11519 | bnx2x_set_mac_buf(fip_mac, val, val2); |
55c11941 MS |
11520 | BNX2X_DEV_INFO |
11521 | ("Read FCoE L2 MAC: %pM\n", fip_mac); | |
11522 | } else { | |
2ba45142 | 11523 | bp->flags |= NO_FCOE_FLAG; |
55c11941 | 11524 | } |
a3348722 BW |
11525 | |
11526 | bp->mf_ext_config = cfg; | |
11527 | ||
9e62e912 | 11528 | } else { /* SD MODE */ |
55c11941 MS |
11529 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { |
11530 | /* use primary mac as iscsi mac */ | |
11531 | memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); | |
11532 | ||
11533 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); | |
11534 | BNX2X_DEV_INFO | |
11535 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
11536 | } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { | |
11537 | /* use primary mac as fip mac */ | |
11538 | memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); | |
11539 | BNX2X_DEV_INFO("SD FCoE MODE\n"); | |
11540 | BNX2X_DEV_INFO | |
11541 | ("Read FIP MAC: %pM\n", fip_mac); | |
614c76df | 11542 | } |
0793f83f | 11543 | } |
a3348722 | 11544 | |
82594f8f YM |
11545 | /* If this is a storage-only interface, use SAN mac as |
11546 | * primary MAC. Notice that for SD this is already the case, | |
11547 | * as the SAN mac was copied from the primary MAC. | |
11548 | */ | |
11549 | if (IS_MF_FCOE_AFEX(bp)) | |
a3348722 | 11550 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); |
0793f83f | 11551 | } else { |
0793f83f | 11552 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11553 | iscsi_mac_upper); |
0793f83f | 11554 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11555 | iscsi_mac_lower); |
2ba45142 | 11556 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
11557 | |
11558 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
55c11941 | 11559 | fcoe_fip_mac_upper); |
c03bd39c | 11560 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11561 | fcoe_fip_mac_lower); |
c03bd39c | 11562 | bnx2x_set_mac_buf(fip_mac, val, val2); |
0793f83f DK |
11563 | } |
11564 | ||
55c11941 | 11565 | /* Disable iSCSI OOO if MAC configuration is invalid. */ |
426b9241 | 11566 | if (!is_valid_ether_addr(iscsi_mac)) { |
55c11941 | 11567 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
c7bf7169 | 11568 | eth_zero_addr(iscsi_mac); |
426b9241 DK |
11569 | } |
11570 | ||
55c11941 | 11571 | /* Disable FCoE if MAC configuration is invalid. */ |
426b9241 DK |
11572 | if (!is_valid_ether_addr(fip_mac)) { |
11573 | bp->flags |= NO_FCOE_FLAG; | |
c7bf7169 | 11574 | eth_zero_addr(bp->fip_mac); |
426b9241 | 11575 | } |
55c11941 MS |
11576 | } |
11577 | ||
0329aba1 | 11578 | static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
55c11941 MS |
11579 | { |
11580 | u32 val, val2; | |
11581 | int func = BP_ABS_FUNC(bp); | |
11582 | int port = BP_PORT(bp); | |
11583 | ||
11584 | /* Zero primary MAC configuration */ | |
c7bf7169 | 11585 | eth_zero_addr(bp->dev->dev_addr); |
55c11941 MS |
11586 | |
11587 | if (BP_NOMCP(bp)) { | |
11588 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
11589 | eth_hw_addr_random(bp->dev); | |
11590 | } else if (IS_MF(bp)) { | |
11591 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
11592 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
11593 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
11594 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
11595 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
11596 | ||
11597 | if (CNIC_SUPPORT(bp)) | |
11598 | bnx2x_get_cnic_mac_hwinfo(bp); | |
11599 | } else { | |
11600 | /* in SF read MACs from port configuration */ | |
11601 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
11602 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
11603 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
11604 | ||
11605 | if (CNIC_SUPPORT(bp)) | |
11606 | bnx2x_get_cnic_mac_hwinfo(bp); | |
11607 | } | |
11608 | ||
3d7d562c YM |
11609 | if (!BP_NOMCP(bp)) { |
11610 | /* Read physical port identifier from shmem */ | |
11611 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
11612 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
11613 | bnx2x_set_mac_buf(bp->phys_port_id, val, val2); | |
11614 | bp->flags |= HAS_PHYS_PORT_ID; | |
11615 | } | |
11616 | ||
55c11941 | 11617 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); |
619c5cb6 | 11618 | |
2e98ffc2 | 11619 | if (!is_valid_ether_addr(bp->dev->dev_addr)) |
619c5cb6 | 11620 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11621 | "bad Ethernet MAC address configuration: %pM\n" |
11622 | "change it manually before bringing up the appropriate network interface\n", | |
0f9dad10 | 11623 | bp->dev->dev_addr); |
7964211d | 11624 | } |
51c1a580 | 11625 | |
0329aba1 | 11626 | static bool bnx2x_get_dropless_info(struct bnx2x *bp) |
7964211d YM |
11627 | { |
11628 | int tmp; | |
11629 | u32 cfg; | |
51c1a580 | 11630 | |
aeeddb8b | 11631 | if (IS_VF(bp)) |
4e833c59 | 11632 | return false; |
aeeddb8b | 11633 | |
7964211d YM |
11634 | if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { |
11635 | /* Take function: tmp = func */ | |
11636 | tmp = BP_ABS_FUNC(bp); | |
11637 | cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); | |
11638 | cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); | |
11639 | } else { | |
11640 | /* Take port: tmp = port */ | |
11641 | tmp = BP_PORT(bp); | |
11642 | cfg = SHMEM_RD(bp, | |
11643 | dev_info.port_hw_config[tmp].generic_features); | |
11644 | cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); | |
11645 | } | |
11646 | return cfg; | |
34f80b04 EG |
11647 | } |
11648 | ||
83bad206 YM |
11649 | static void validate_set_si_mode(struct bnx2x *bp) |
11650 | { | |
11651 | u8 func = BP_ABS_FUNC(bp); | |
11652 | u32 val; | |
11653 | ||
11654 | val = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
11655 | ||
11656 | /* check for legal mac (upper bytes) */ | |
11657 | if (val != 0xffff) { | |
11658 | bp->mf_mode = MULTI_FUNCTION_SI; | |
11659 | bp->mf_config[BP_VN(bp)] = | |
11660 | MF_CFG_RD(bp, func_mf_config[func].config); | |
11661 | } else | |
11662 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); | |
11663 | } | |
11664 | ||
0329aba1 | 11665 | static int bnx2x_get_hwinfo(struct bnx2x *bp) |
34f80b04 | 11666 | { |
0793f83f | 11667 | int /*abs*/func = BP_ABS_FUNC(bp); |
b8ee8328 | 11668 | int vn; |
83bad206 | 11669 | u32 val = 0, val2 = 0; |
34f80b04 | 11670 | int rc = 0; |
a2fbb9ea | 11671 | |
0f587f1b YM |
11672 | /* Validate that chip access is feasible */ |
11673 | if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) { | |
11674 | dev_err(&bp->pdev->dev, | |
11675 | "Chip read returns all Fs. Preventing probe from continuing\n"); | |
11676 | return -EINVAL; | |
11677 | } | |
11678 | ||
34f80b04 | 11679 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 11680 | |
6383c0b3 AE |
11681 | /* |
11682 | * initialize IGU parameters | |
11683 | */ | |
f2e0899f DK |
11684 | if (CHIP_IS_E1x(bp)) { |
11685 | bp->common.int_block = INT_BLOCK_HC; | |
11686 | ||
11687 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
11688 | bp->igu_base_sb = 0; | |
f2e0899f DK |
11689 | } else { |
11690 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 | 11691 | |
16a5fd92 | 11692 | /* do not allow device reset during IGU info processing */ |
7a06a122 DK |
11693 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
11694 | ||
f2e0899f | 11695 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
11696 | |
11697 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
11698 | int tout = 5000; | |
11699 | ||
11700 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
11701 | ||
11702 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
11703 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
11704 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
11705 | ||
11706 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
11707 | tout--; | |
0926d499 | 11708 | usleep_range(1000, 2000); |
619c5cb6 VZ |
11709 | } |
11710 | ||
11711 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
11712 | dev_err(&bp->pdev->dev, | |
11713 | "FORCING Normal Mode failed!!!\n"); | |
9b341bb1 BW |
11714 | bnx2x_release_hw_lock(bp, |
11715 | HW_LOCK_RESOURCE_RESET); | |
619c5cb6 VZ |
11716 | return -EPERM; |
11717 | } | |
11718 | } | |
11719 | ||
f2e0899f | 11720 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 11721 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
11722 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
11723 | } else | |
619c5cb6 | 11724 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 11725 | |
9b341bb1 | 11726 | rc = bnx2x_get_igu_cam_info(bp); |
7a06a122 | 11727 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
9b341bb1 BW |
11728 | if (rc) |
11729 | return rc; | |
f2e0899f | 11730 | } |
619c5cb6 VZ |
11731 | |
11732 | /* | |
11733 | * set base FW non-default (fast path) status block id, this value is | |
11734 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
11735 | * determine the id used by the FW. | |
11736 | */ | |
11737 | if (CHIP_IS_E1x(bp)) | |
11738 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
11739 | else /* | |
11740 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
11741 | * the same queue are indicated on the same IGU SB). So we prefer | |
11742 | * FW and IGU SBs to be the same value. | |
11743 | */ | |
11744 | bp->base_fw_ndsb = bp->igu_base_sb; | |
11745 | ||
11746 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
11747 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
11748 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
11749 | |
11750 | /* | |
11751 | * Initialize MF configuration | |
11752 | */ | |
523224a3 | 11753 | |
fb3bff17 DK |
11754 | bp->mf_ov = 0; |
11755 | bp->mf_mode = 0; | |
7609647e | 11756 | bp->mf_sub_mode = 0; |
3395a033 | 11757 | vn = BP_VN(bp); |
0793f83f | 11758 | |
f2e0899f | 11759 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
11760 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
11761 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
11762 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
11763 | ||
f2e0899f DK |
11764 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
11765 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
11766 | else | |
11767 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
11768 | offsetof(struct shmem_region, func_mb) + |
11769 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
11770 | /* |
11771 | * get mf configuration: | |
16a5fd92 | 11772 | * 1. Existence of MF configuration |
0793f83f DK |
11773 | * 2. MAC address must be legal (check only upper bytes) |
11774 | * for Switch-Independent mode; | |
11775 | * OVLAN must be legal for Switch-Dependent mode | |
11776 | * 3. SF_MODE configures specific MF mode | |
11777 | */ | |
11778 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
11779 | /* get mf configuration */ | |
11780 | val = SHMEM_RD(bp, | |
11781 | dev_info.shared_feature_config.config); | |
11782 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
11783 | ||
11784 | switch (val) { | |
11785 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
83bad206 | 11786 | validate_set_si_mode(bp); |
0793f83f | 11787 | break; |
a3348722 BW |
11788 | case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: |
11789 | if ((!CHIP_IS_E1x(bp)) && | |
11790 | (MF_CFG_RD(bp, func_mf_config[func]. | |
11791 | mac_upper) != 0xffff) && | |
11792 | (SHMEM2_HAS(bp, | |
11793 | afex_driver_support))) { | |
11794 | bp->mf_mode = MULTI_FUNCTION_AFEX; | |
11795 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
11796 | func_mf_config[func].config); | |
11797 | } else { | |
11798 | BNX2X_DEV_INFO("can not configure afex mode\n"); | |
11799 | } | |
11800 | break; | |
0793f83f DK |
11801 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: |
11802 | /* get OV configuration */ | |
11803 | val = MF_CFG_RD(bp, | |
11804 | func_mf_config[FUNC_0].e1hov_tag); | |
11805 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
11806 | ||
11807 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
11808 | bp->mf_mode = MULTI_FUNCTION_SD; | |
11809 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
11810 | func_mf_config[func].config); | |
11811 | } else | |
754a2f52 | 11812 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f | 11813 | break; |
7609647e YM |
11814 | case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE: |
11815 | bp->mf_mode = MULTI_FUNCTION_SD; | |
11816 | bp->mf_sub_mode = SUB_MF_MODE_UFP; | |
11817 | bp->mf_config[vn] = | |
11818 | MF_CFG_RD(bp, | |
11819 | func_mf_config[func].config); | |
11820 | break; | |
3786b942 AE |
11821 | case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: |
11822 | bp->mf_config[vn] = 0; | |
11823 | break; | |
83bad206 YM |
11824 | case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE: |
11825 | val2 = SHMEM_RD(bp, | |
11826 | dev_info.shared_hw_config.config_3); | |
11827 | val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK; | |
11828 | switch (val2) { | |
11829 | case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5: | |
11830 | validate_set_si_mode(bp); | |
11831 | bp->mf_sub_mode = | |
11832 | SUB_MF_MODE_NPAR1_DOT_5; | |
11833 | break; | |
11834 | default: | |
11835 | /* Unknown configuration */ | |
11836 | bp->mf_config[vn] = 0; | |
11837 | BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n", | |
11838 | val); | |
11839 | } | |
11840 | break; | |
0793f83f DK |
11841 | default: |
11842 | /* Unknown configuration: reset mf_config */ | |
11843 | bp->mf_config[vn] = 0; | |
51c1a580 | 11844 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
0793f83f DK |
11845 | } |
11846 | } | |
a2fbb9ea | 11847 | |
2691d51d | 11848 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 11849 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 11850 | |
0793f83f DK |
11851 | switch (bp->mf_mode) { |
11852 | case MULTI_FUNCTION_SD: | |
11853 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
11854 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 11855 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 11856 | bp->mf_ov = val; |
619c5cb6 VZ |
11857 | bp->path_has_ovlan = true; |
11858 | ||
51c1a580 MS |
11859 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
11860 | func, bp->mf_ov, bp->mf_ov); | |
7609647e YM |
11861 | } else if (bp->mf_sub_mode == SUB_MF_MODE_UFP) { |
11862 | dev_err(&bp->pdev->dev, | |
11863 | "Unexpected - no valid MF OV for func %d in UFP mode\n", | |
11864 | func); | |
11865 | bp->path_has_ovlan = true; | |
2691d51d | 11866 | } else { |
619c5cb6 | 11867 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11868 | "No valid MF OV for func %d, aborting\n", |
11869 | func); | |
619c5cb6 | 11870 | return -EPERM; |
34f80b04 | 11871 | } |
0793f83f | 11872 | break; |
a3348722 BW |
11873 | case MULTI_FUNCTION_AFEX: |
11874 | BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); | |
11875 | break; | |
0793f83f | 11876 | case MULTI_FUNCTION_SI: |
51c1a580 MS |
11877 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
11878 | func); | |
0793f83f DK |
11879 | break; |
11880 | default: | |
11881 | if (vn) { | |
619c5cb6 | 11882 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11883 | "VN %d is in a single function mode, aborting\n", |
11884 | vn); | |
619c5cb6 | 11885 | return -EPERM; |
2691d51d | 11886 | } |
0793f83f | 11887 | break; |
34f80b04 | 11888 | } |
0793f83f | 11889 | |
619c5cb6 VZ |
11890 | /* check if other port on the path needs ovlan: |
11891 | * Since MF configuration is shared between ports | |
11892 | * Possible mixed modes are only | |
11893 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
11894 | */ | |
11895 | if (CHIP_MODE_IS_4_PORT(bp) && | |
11896 | !bp->path_has_ovlan && | |
11897 | !IS_MF(bp) && | |
11898 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
11899 | u8 other_port = !BP_PORT(bp); | |
11900 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
11901 | val = MF_CFG_RD(bp, | |
11902 | func_mf_config[other_func].e1hov_tag); | |
11903 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
11904 | bp->path_has_ovlan = true; | |
11905 | } | |
34f80b04 | 11906 | } |
a2fbb9ea | 11907 | |
e848582c DK |
11908 | /* adjust igu_sb_cnt to MF for E1H */ |
11909 | if (CHIP_IS_E1H(bp) && IS_MF(bp)) | |
11910 | bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT); | |
523224a3 | 11911 | |
619c5cb6 VZ |
11912 | /* port info */ |
11913 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 11914 | |
0793f83f DK |
11915 | /* Get MAC addresses */ |
11916 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 11917 | |
2ba45142 | 11918 | bnx2x_get_cnic_info(bp); |
2ba45142 | 11919 | |
34f80b04 EG |
11920 | return rc; |
11921 | } | |
11922 | ||
0329aba1 | 11923 | static void bnx2x_read_fwinfo(struct bnx2x *bp) |
34f24c7f VZ |
11924 | { |
11925 | int cnt, i, block_end, rodi; | |
fcdf95cb | 11926 | char vpd_start[BNX2X_VPD_LEN+1]; |
34f24c7f VZ |
11927 | char str_id_reg[VENDOR_ID_LEN+1]; |
11928 | char str_id_cap[VENDOR_ID_LEN+1]; | |
fcdf95cb BW |
11929 | char *vpd_data; |
11930 | char *vpd_extended_data = NULL; | |
34f24c7f VZ |
11931 | u8 len; |
11932 | ||
fcdf95cb | 11933 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); |
34f24c7f VZ |
11934 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
11935 | ||
11936 | if (cnt < BNX2X_VPD_LEN) | |
11937 | goto out_not_found; | |
11938 | ||
fcdf95cb BW |
11939 | /* VPD RO tag should be first tag after identifier string, hence |
11940 | * we should be able to find it in first BNX2X_VPD_LEN chars | |
11941 | */ | |
11942 | i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, | |
34f24c7f VZ |
11943 | PCI_VPD_LRDT_RO_DATA); |
11944 | if (i < 0) | |
11945 | goto out_not_found; | |
11946 | ||
34f24c7f | 11947 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + |
fcdf95cb | 11948 | pci_vpd_lrdt_size(&vpd_start[i]); |
34f24c7f VZ |
11949 | |
11950 | i += PCI_VPD_LRDT_TAG_SIZE; | |
11951 | ||
fcdf95cb BW |
11952 | if (block_end > BNX2X_VPD_LEN) { |
11953 | vpd_extended_data = kmalloc(block_end, GFP_KERNEL); | |
11954 | if (vpd_extended_data == NULL) | |
11955 | goto out_not_found; | |
11956 | ||
11957 | /* read rest of vpd image into vpd_extended_data */ | |
11958 | memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); | |
11959 | cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, | |
11960 | block_end - BNX2X_VPD_LEN, | |
11961 | vpd_extended_data + BNX2X_VPD_LEN); | |
11962 | if (cnt < (block_end - BNX2X_VPD_LEN)) | |
11963 | goto out_not_found; | |
11964 | vpd_data = vpd_extended_data; | |
11965 | } else | |
11966 | vpd_data = vpd_start; | |
11967 | ||
11968 | /* now vpd_data holds full vpd content in both cases */ | |
34f24c7f VZ |
11969 | |
11970 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
11971 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
11972 | if (rodi < 0) | |
11973 | goto out_not_found; | |
11974 | ||
11975 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
11976 | ||
11977 | if (len != VENDOR_ID_LEN) | |
11978 | goto out_not_found; | |
11979 | ||
11980 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11981 | ||
11982 | /* vendor specific info */ | |
11983 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
11984 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
11985 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
11986 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
11987 | ||
11988 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
11989 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
11990 | if (rodi >= 0) { | |
11991 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
11992 | ||
11993 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11994 | ||
11995 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
11996 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
11997 | bp->fw_ver[len] = ' '; | |
11998 | } | |
11999 | } | |
fcdf95cb | 12000 | kfree(vpd_extended_data); |
34f24c7f VZ |
12001 | return; |
12002 | } | |
12003 | out_not_found: | |
fcdf95cb | 12004 | kfree(vpd_extended_data); |
34f24c7f VZ |
12005 | return; |
12006 | } | |
12007 | ||
0329aba1 | 12008 | static void bnx2x_set_modes_bitmap(struct bnx2x *bp) |
619c5cb6 VZ |
12009 | { |
12010 | u32 flags = 0; | |
12011 | ||
12012 | if (CHIP_REV_IS_FPGA(bp)) | |
12013 | SET_FLAGS(flags, MODE_FPGA); | |
12014 | else if (CHIP_REV_IS_EMUL(bp)) | |
12015 | SET_FLAGS(flags, MODE_EMUL); | |
12016 | else | |
12017 | SET_FLAGS(flags, MODE_ASIC); | |
12018 | ||
12019 | if (CHIP_MODE_IS_4_PORT(bp)) | |
12020 | SET_FLAGS(flags, MODE_PORT4); | |
12021 | else | |
12022 | SET_FLAGS(flags, MODE_PORT2); | |
12023 | ||
12024 | if (CHIP_IS_E2(bp)) | |
12025 | SET_FLAGS(flags, MODE_E2); | |
12026 | else if (CHIP_IS_E3(bp)) { | |
12027 | SET_FLAGS(flags, MODE_E3); | |
12028 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
12029 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
12030 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
12031 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
12032 | } |
12033 | ||
12034 | if (IS_MF(bp)) { | |
12035 | SET_FLAGS(flags, MODE_MF); | |
12036 | switch (bp->mf_mode) { | |
12037 | case MULTI_FUNCTION_SD: | |
12038 | SET_FLAGS(flags, MODE_MF_SD); | |
12039 | break; | |
12040 | case MULTI_FUNCTION_SI: | |
12041 | SET_FLAGS(flags, MODE_MF_SI); | |
12042 | break; | |
a3348722 BW |
12043 | case MULTI_FUNCTION_AFEX: |
12044 | SET_FLAGS(flags, MODE_MF_AFEX); | |
12045 | break; | |
619c5cb6 VZ |
12046 | } |
12047 | } else | |
12048 | SET_FLAGS(flags, MODE_SF); | |
12049 | ||
12050 | #if defined(__LITTLE_ENDIAN) | |
12051 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
12052 | #else /*(__BIG_ENDIAN)*/ | |
12053 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
12054 | #endif | |
12055 | INIT_MODE_FLAGS(bp) = flags; | |
12056 | } | |
12057 | ||
0329aba1 | 12058 | static int bnx2x_init_bp(struct bnx2x *bp) |
34f80b04 | 12059 | { |
f2e0899f | 12060 | int func; |
34f80b04 EG |
12061 | int rc; |
12062 | ||
34f80b04 | 12063 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 12064 | mutex_init(&bp->fw_mb_mutex); |
42f8277f | 12065 | mutex_init(&bp->drv_info_mutex); |
c6e36d8c | 12066 | sema_init(&bp->stats_lock, 1); |
42f8277f | 12067 | bp->drv_info_mng_owner = false; |
55c11941 | 12068 | |
1cf167f2 | 12069 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 12070 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 12071 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
370d4a26 | 12072 | INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task); |
1ab4434c AE |
12073 | if (IS_PF(bp)) { |
12074 | rc = bnx2x_get_hwinfo(bp); | |
12075 | if (rc) | |
12076 | return rc; | |
12077 | } else { | |
e09b74d0 | 12078 | eth_zero_addr(bp->dev->dev_addr); |
1ab4434c | 12079 | } |
34f80b04 | 12080 | |
619c5cb6 VZ |
12081 | bnx2x_set_modes_bitmap(bp); |
12082 | ||
12083 | rc = bnx2x_alloc_mem_bp(bp); | |
12084 | if (rc) | |
12085 | return rc; | |
523224a3 | 12086 | |
34f24c7f | 12087 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
12088 | |
12089 | func = BP_FUNC(bp); | |
12090 | ||
34f80b04 | 12091 | /* need to reset chip if undi was active */ |
1ab4434c | 12092 | if (IS_PF(bp) && !BP_NOMCP(bp)) { |
452427b0 YM |
12093 | /* init fw_seq */ |
12094 | bp->fw_seq = | |
12095 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
12096 | DRV_MSG_SEQ_NUMBER_MASK; | |
12097 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
12098 | ||
91ebb929 YM |
12099 | rc = bnx2x_prev_unload(bp); |
12100 | if (rc) { | |
12101 | bnx2x_free_mem_bp(bp); | |
12102 | return rc; | |
12103 | } | |
452427b0 YM |
12104 | } |
12105 | ||
34f80b04 | 12106 | if (CHIP_REV_IS_FPGA(bp)) |
cdaa7cb8 | 12107 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
12108 | |
12109 | if (BP_NOMCP(bp) && (func == 0)) | |
51c1a580 | 12110 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
34f80b04 | 12111 | |
614c76df | 12112 | bp->disable_tpa = disable_tpa; |
2e98ffc2 | 12113 | bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp); |
94d9de3c | 12114 | /* Reduce memory usage in kdump environment by disabling TPA */ |
c9931896 | 12115 | bp->disable_tpa |= is_kdump_kernel(); |
614c76df | 12116 | |
7a9b2557 | 12117 | /* Set TPA flags */ |
614c76df | 12118 | if (bp->disable_tpa) { |
d9b9e860 | 12119 | bp->dev->hw_features &= ~NETIF_F_LRO; |
7a9b2557 | 12120 | bp->dev->features &= ~NETIF_F_LRO; |
7a9b2557 VZ |
12121 | } |
12122 | ||
a18f5128 EG |
12123 | if (CHIP_IS_E1(bp)) |
12124 | bp->dropless_fc = 0; | |
12125 | else | |
7964211d | 12126 | bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); |
a18f5128 | 12127 | |
8d5726c4 | 12128 | bp->mrrs = mrrs; |
7a9b2557 | 12129 | |
2e98ffc2 | 12130 | bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL; |
1ab4434c AE |
12131 | if (IS_VF(bp)) |
12132 | bp->rx_ring_size = MAX_RX_AVAIL; | |
34f80b04 | 12133 | |
7d323bfd | 12134 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
12135 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
12136 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 12137 | |
fc543637 | 12138 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
34f80b04 EG |
12139 | |
12140 | init_timer(&bp->timer); | |
12141 | bp->timer.expires = jiffies + bp->current_interval; | |
12142 | bp->timer.data = (unsigned long) bp; | |
12143 | bp->timer.function = bnx2x_timer; | |
12144 | ||
0370cf90 BW |
12145 | if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && |
12146 | SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && | |
12147 | SHMEM2_RD(bp, dcbx_lldp_params_offset) && | |
12148 | SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) { | |
12149 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); | |
12150 | bnx2x_dcbx_init_params(bp); | |
12151 | } else { | |
12152 | bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); | |
12153 | } | |
e4901dde | 12154 | |
619c5cb6 VZ |
12155 | if (CHIP_IS_E1x(bp)) |
12156 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
12157 | else | |
12158 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
619c5cb6 | 12159 | |
6383c0b3 | 12160 | /* multiple tx priority */ |
1ab4434c AE |
12161 | if (IS_VF(bp)) |
12162 | bp->max_cos = 1; | |
12163 | else if (CHIP_IS_E1x(bp)) | |
6383c0b3 | 12164 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; |
1ab4434c | 12165 | else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) |
6383c0b3 | 12166 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; |
1ab4434c | 12167 | else if (CHIP_IS_E3B0(bp)) |
6383c0b3 | 12168 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; |
1ab4434c AE |
12169 | else |
12170 | BNX2X_ERR("unknown chip %x revision %x\n", | |
12171 | CHIP_NUM(bp), CHIP_REV(bp)); | |
12172 | BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); | |
6383c0b3 | 12173 | |
55c11941 MS |
12174 | /* We need at least one default status block for slow-path events, |
12175 | * second status block for the L2 queue, and a third status block for | |
16a5fd92 | 12176 | * CNIC if supported. |
55c11941 | 12177 | */ |
60cad4e6 AE |
12178 | if (IS_VF(bp)) |
12179 | bp->min_msix_vec_cnt = 1; | |
12180 | else if (CNIC_SUPPORT(bp)) | |
55c11941 | 12181 | bp->min_msix_vec_cnt = 3; |
60cad4e6 | 12182 | else /* PF w/o cnic */ |
55c11941 MS |
12183 | bp->min_msix_vec_cnt = 2; |
12184 | BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); | |
12185 | ||
5bb680d6 MS |
12186 | bp->dump_preset_idx = 1; |
12187 | ||
eeed018c MK |
12188 | if (CHIP_IS_E3B0(bp)) |
12189 | bp->flags |= PTP_SUPPORTED; | |
12190 | ||
34f80b04 | 12191 | return rc; |
a2fbb9ea ET |
12192 | } |
12193 | ||
de0c62db DK |
12194 | /**************************************************************************** |
12195 | * General service functions | |
12196 | ****************************************************************************/ | |
a2fbb9ea | 12197 | |
619c5cb6 VZ |
12198 | /* |
12199 | * net_device service functions | |
12200 | */ | |
12201 | ||
bb2a0f7a | 12202 | /* called with rtnl_lock */ |
a2fbb9ea ET |
12203 | static int bnx2x_open(struct net_device *dev) |
12204 | { | |
12205 | struct bnx2x *bp = netdev_priv(dev); | |
8395be5e | 12206 | int rc; |
a2fbb9ea | 12207 | |
1355b704 MY |
12208 | bp->stats_init = true; |
12209 | ||
6eccabb3 EG |
12210 | netif_carrier_off(dev); |
12211 | ||
a2fbb9ea ET |
12212 | bnx2x_set_power_state(bp, PCI_D0); |
12213 | ||
ad5afc89 | 12214 | /* If parity had happen during the unload, then attentions |
c9ee9206 VZ |
12215 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we |
12216 | * want the first function loaded on the current engine to | |
12217 | * complete the recovery. | |
ad5afc89 | 12218 | * Parity recovery is only relevant for PF driver. |
c9ee9206 | 12219 | */ |
ad5afc89 | 12220 | if (IS_PF(bp)) { |
1a6974b2 YM |
12221 | int other_engine = BP_PATH(bp) ? 0 : 1; |
12222 | bool other_load_status, load_status; | |
12223 | bool global = false; | |
12224 | ||
ad5afc89 AE |
12225 | other_load_status = bnx2x_get_load_status(bp, other_engine); |
12226 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); | |
12227 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
12228 | bnx2x_chk_parity_attn(bp, &global, true)) { | |
12229 | do { | |
12230 | /* If there are attentions and they are in a | |
12231 | * global blocks, set the GLOBAL_RESET bit | |
12232 | * regardless whether it will be this function | |
12233 | * that will complete the recovery or not. | |
12234 | */ | |
12235 | if (global) | |
12236 | bnx2x_set_reset_global(bp); | |
72fd0718 | 12237 | |
ad5afc89 AE |
12238 | /* Only the first function on the current |
12239 | * engine should try to recover in open. In case | |
12240 | * of attentions in global blocks only the first | |
12241 | * in the chip should try to recover. | |
12242 | */ | |
12243 | if ((!load_status && | |
12244 | (!global || !other_load_status)) && | |
12245 | bnx2x_trylock_leader_lock(bp) && | |
12246 | !bnx2x_leader_reset(bp)) { | |
12247 | netdev_info(bp->dev, | |
12248 | "Recovered in open\n"); | |
12249 | break; | |
12250 | } | |
72fd0718 | 12251 | |
ad5afc89 AE |
12252 | /* recovery has failed... */ |
12253 | bnx2x_set_power_state(bp, PCI_D3hot); | |
12254 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
72fd0718 | 12255 | |
ad5afc89 AE |
12256 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
12257 | "If you still see this message after a few retries then power cycle is required.\n"); | |
72fd0718 | 12258 | |
ad5afc89 AE |
12259 | return -EAGAIN; |
12260 | } while (0); | |
12261 | } | |
12262 | } | |
72fd0718 VZ |
12263 | |
12264 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
8395be5e AE |
12265 | rc = bnx2x_nic_load(bp, LOAD_OPEN); |
12266 | if (rc) | |
12267 | return rc; | |
9a8130bc | 12268 | return 0; |
a2fbb9ea ET |
12269 | } |
12270 | ||
bb2a0f7a | 12271 | /* called with rtnl_lock */ |
56ad3152 | 12272 | static int bnx2x_close(struct net_device *dev) |
a2fbb9ea | 12273 | { |
a2fbb9ea ET |
12274 | struct bnx2x *bp = netdev_priv(dev); |
12275 | ||
12276 | /* Unload the driver, release IRQs */ | |
5d07d868 | 12277 | bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); |
c9ee9206 | 12278 | |
a2fbb9ea ET |
12279 | return 0; |
12280 | } | |
12281 | ||
1191cb83 ED |
12282 | static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
12283 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 12284 | { |
619c5cb6 VZ |
12285 | int mc_count = netdev_mc_count(bp->dev); |
12286 | struct bnx2x_mcast_list_elem *mc_mac = | |
cd2b0389 | 12287 | kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC); |
619c5cb6 | 12288 | struct netdev_hw_addr *ha; |
6e30dd4e | 12289 | |
619c5cb6 VZ |
12290 | if (!mc_mac) |
12291 | return -ENOMEM; | |
6e30dd4e | 12292 | |
619c5cb6 | 12293 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 12294 | |
619c5cb6 VZ |
12295 | netdev_for_each_mc_addr(ha, bp->dev) { |
12296 | mc_mac->mac = bnx2x_mc_addr(ha); | |
12297 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
12298 | mc_mac++; | |
6e30dd4e | 12299 | } |
619c5cb6 VZ |
12300 | |
12301 | p->mcast_list_len = mc_count; | |
12302 | ||
12303 | return 0; | |
6e30dd4e VZ |
12304 | } |
12305 | ||
1191cb83 | 12306 | static void bnx2x_free_mcast_macs_list( |
619c5cb6 VZ |
12307 | struct bnx2x_mcast_ramrod_params *p) |
12308 | { | |
12309 | struct bnx2x_mcast_list_elem *mc_mac = | |
12310 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
12311 | link); | |
12312 | ||
12313 | WARN_ON(!mc_mac); | |
12314 | kfree(mc_mac); | |
12315 | } | |
12316 | ||
12317 | /** | |
12318 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
12319 | * | |
12320 | * @bp: driver handle | |
6e30dd4e | 12321 | * |
619c5cb6 | 12322 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 12323 | */ |
1191cb83 | 12324 | static int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 12325 | { |
619c5cb6 | 12326 | int rc; |
6e30dd4e | 12327 | struct net_device *dev = bp->dev; |
6e30dd4e | 12328 | struct netdev_hw_addr *ha; |
15192a8c | 12329 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; |
619c5cb6 | 12330 | unsigned long ramrod_flags = 0; |
6e30dd4e | 12331 | |
619c5cb6 VZ |
12332 | /* First schedule a cleanup up of old configuration */ |
12333 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
12334 | if (rc < 0) { | |
12335 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
12336 | return rc; | |
12337 | } | |
6e30dd4e VZ |
12338 | |
12339 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
12340 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
12341 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
7b5342d9 YM |
12342 | if (rc == -EEXIST) { |
12343 | DP(BNX2X_MSG_SP, | |
12344 | "Failed to schedule ADD operations: %d\n", rc); | |
12345 | /* do not treat adding same MAC as error */ | |
12346 | rc = 0; | |
12347 | ||
12348 | } else if (rc < 0) { | |
12349 | ||
619c5cb6 VZ |
12350 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", |
12351 | rc); | |
12352 | return rc; | |
6e30dd4e VZ |
12353 | } |
12354 | } | |
12355 | ||
619c5cb6 VZ |
12356 | /* Execute the pending commands */ |
12357 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
12358 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
12359 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
12360 | } |
12361 | ||
1191cb83 | 12362 | static int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 12363 | { |
619c5cb6 | 12364 | struct net_device *dev = bp->dev; |
3b603066 | 12365 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 | 12366 | int rc = 0; |
6e30dd4e | 12367 | |
619c5cb6 | 12368 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 12369 | |
619c5cb6 VZ |
12370 | /* first, clear all configured multicast MACs */ |
12371 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
12372 | if (rc < 0) { | |
51c1a580 | 12373 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
619c5cb6 VZ |
12374 | return rc; |
12375 | } | |
6e30dd4e | 12376 | |
619c5cb6 VZ |
12377 | /* then, configure a new MACs list */ |
12378 | if (netdev_mc_count(dev)) { | |
12379 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
12380 | if (rc) { | |
51c1a580 MS |
12381 | BNX2X_ERR("Failed to create multicast MACs list: %d\n", |
12382 | rc); | |
619c5cb6 VZ |
12383 | return rc; |
12384 | } | |
6e30dd4e | 12385 | |
619c5cb6 VZ |
12386 | /* Now add the new MACs */ |
12387 | rc = bnx2x_config_mcast(bp, &rparam, | |
12388 | BNX2X_MCAST_CMD_ADD); | |
12389 | if (rc < 0) | |
51c1a580 MS |
12390 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
12391 | rc); | |
6e30dd4e | 12392 | |
619c5cb6 VZ |
12393 | bnx2x_free_mcast_macs_list(&rparam); |
12394 | } | |
6e30dd4e | 12395 | |
619c5cb6 | 12396 | return rc; |
6e30dd4e VZ |
12397 | } |
12398 | ||
619c5cb6 | 12399 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
a8f47eb7 | 12400 | static void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
12401 | { |
12402 | struct bnx2x *bp = netdev_priv(dev); | |
34f80b04 EG |
12403 | |
12404 | if (bp->state != BNX2X_STATE_OPEN) { | |
12405 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
12406 | return; | |
8b09be5f YM |
12407 | } else { |
12408 | /* Schedule an SP task to handle rest of change */ | |
230bb0f3 YM |
12409 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE, |
12410 | NETIF_MSG_IFUP); | |
34f80b04 | 12411 | } |
8b09be5f YM |
12412 | } |
12413 | ||
12414 | void bnx2x_set_rx_mode_inner(struct bnx2x *bp) | |
12415 | { | |
12416 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 | 12417 | |
619c5cb6 | 12418 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 | 12419 | |
8b09be5f YM |
12420 | netif_addr_lock_bh(bp->dev); |
12421 | ||
12422 | if (bp->dev->flags & IFF_PROMISC) { | |
34f80b04 | 12423 | rx_mode = BNX2X_RX_MODE_PROMISC; |
8b09be5f YM |
12424 | } else if ((bp->dev->flags & IFF_ALLMULTI) || |
12425 | ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && | |
12426 | CHIP_IS_E1(bp))) { | |
34f80b04 | 12427 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
8b09be5f | 12428 | } else { |
381ac16b AE |
12429 | if (IS_PF(bp)) { |
12430 | /* some multicasts */ | |
12431 | if (bnx2x_set_mc_list(bp) < 0) | |
12432 | rx_mode = BNX2X_RX_MODE_ALLMULTI; | |
34f80b04 | 12433 | |
8b09be5f YM |
12434 | /* release bh lock, as bnx2x_set_uc_list might sleep */ |
12435 | netif_addr_unlock_bh(bp->dev); | |
381ac16b AE |
12436 | if (bnx2x_set_uc_list(bp) < 0) |
12437 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
8b09be5f | 12438 | netif_addr_lock_bh(bp->dev); |
381ac16b AE |
12439 | } else { |
12440 | /* configuring mcast to a vf involves sleeping (when we | |
8b09be5f | 12441 | * wait for the pf's response). |
381ac16b | 12442 | */ |
230bb0f3 YM |
12443 | bnx2x_schedule_sp_rtnl(bp, |
12444 | BNX2X_SP_RTNL_VFPF_MCAST, 0); | |
381ac16b | 12445 | } |
34f80b04 EG |
12446 | } |
12447 | ||
12448 | bp->rx_mode = rx_mode; | |
614c76df | 12449 | /* handle ISCSI SD mode */ |
2e98ffc2 | 12450 | if (IS_MF_ISCSI_ONLY(bp)) |
614c76df | 12451 | bp->rx_mode = BNX2X_RX_MODE_NONE; |
619c5cb6 VZ |
12452 | |
12453 | /* Schedule the rx_mode command */ | |
12454 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
12455 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
8b09be5f | 12456 | netif_addr_unlock_bh(bp->dev); |
619c5cb6 VZ |
12457 | return; |
12458 | } | |
12459 | ||
381ac16b AE |
12460 | if (IS_PF(bp)) { |
12461 | bnx2x_set_storm_rx_mode(bp); | |
8b09be5f | 12462 | netif_addr_unlock_bh(bp->dev); |
381ac16b | 12463 | } else { |
8b09be5f YM |
12464 | /* VF will need to request the PF to make this change, and so |
12465 | * the VF needs to release the bottom-half lock prior to the | |
12466 | * request (as it will likely require sleep on the VF side) | |
381ac16b | 12467 | */ |
8b09be5f YM |
12468 | netif_addr_unlock_bh(bp->dev); |
12469 | bnx2x_vfpf_storm_rx_mode(bp); | |
381ac16b | 12470 | } |
34f80b04 EG |
12471 | } |
12472 | ||
c18487ee | 12473 | /* called with rtnl_lock */ |
01cd4528 EG |
12474 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
12475 | int devad, u16 addr) | |
a2fbb9ea | 12476 | { |
01cd4528 EG |
12477 | struct bnx2x *bp = netdev_priv(netdev); |
12478 | u16 value; | |
12479 | int rc; | |
a2fbb9ea | 12480 | |
01cd4528 EG |
12481 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
12482 | prtad, devad, addr); | |
a2fbb9ea | 12483 | |
01cd4528 EG |
12484 | /* The HW expects different devad if CL22 is used */ |
12485 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 12486 | |
01cd4528 | 12487 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 12488 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
12489 | bnx2x_release_phy_lock(bp); |
12490 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 12491 | |
01cd4528 EG |
12492 | if (!rc) |
12493 | rc = value; | |
12494 | return rc; | |
12495 | } | |
a2fbb9ea | 12496 | |
01cd4528 EG |
12497 | /* called with rtnl_lock */ |
12498 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
12499 | u16 addr, u16 value) | |
12500 | { | |
12501 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
12502 | int rc; |
12503 | ||
51c1a580 MS |
12504 | DP(NETIF_MSG_LINK, |
12505 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", | |
12506 | prtad, devad, addr, value); | |
01cd4528 | 12507 | |
01cd4528 EG |
12508 | /* The HW expects different devad if CL22 is used */ |
12509 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 12510 | |
01cd4528 | 12511 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 12512 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
12513 | bnx2x_release_phy_lock(bp); |
12514 | return rc; | |
12515 | } | |
c18487ee | 12516 | |
01cd4528 EG |
12517 | /* called with rtnl_lock */ |
12518 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
12519 | { | |
12520 | struct bnx2x *bp = netdev_priv(dev); | |
12521 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 12522 | |
01cd4528 EG |
12523 | if (!netif_running(dev)) |
12524 | return -EAGAIN; | |
12525 | ||
eeed018c MK |
12526 | switch (cmd) { |
12527 | case SIOCSHWTSTAMP: | |
12528 | return bnx2x_hwtstamp_ioctl(bp, ifr); | |
12529 | default: | |
12530 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", | |
12531 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
12532 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
12533 | } | |
a2fbb9ea ET |
12534 | } |
12535 | ||
257ddbda | 12536 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
12537 | static void poll_bnx2x(struct net_device *dev) |
12538 | { | |
12539 | struct bnx2x *bp = netdev_priv(dev); | |
14a15d61 | 12540 | int i; |
a2fbb9ea | 12541 | |
14a15d61 MS |
12542 | for_each_eth_queue(bp, i) { |
12543 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
12544 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); | |
12545 | } | |
a2fbb9ea ET |
12546 | } |
12547 | #endif | |
12548 | ||
614c76df DK |
12549 | static int bnx2x_validate_addr(struct net_device *dev) |
12550 | { | |
12551 | struct bnx2x *bp = netdev_priv(dev); | |
12552 | ||
e09b74d0 AE |
12553 | /* query the bulletin board for mac address configured by the PF */ |
12554 | if (IS_VF(bp)) | |
12555 | bnx2x_sample_bulletin(bp); | |
12556 | ||
2e98ffc2 | 12557 | if (!is_valid_ether_addr(dev->dev_addr)) { |
51c1a580 | 12558 | BNX2X_ERR("Non-valid Ethernet address\n"); |
614c76df | 12559 | return -EADDRNOTAVAIL; |
51c1a580 | 12560 | } |
614c76df DK |
12561 | return 0; |
12562 | } | |
12563 | ||
3d7d562c | 12564 | static int bnx2x_get_phys_port_id(struct net_device *netdev, |
02637fce | 12565 | struct netdev_phys_item_id *ppid) |
3d7d562c YM |
12566 | { |
12567 | struct bnx2x *bp = netdev_priv(netdev); | |
12568 | ||
12569 | if (!(bp->flags & HAS_PHYS_PORT_ID)) | |
12570 | return -EOPNOTSUPP; | |
12571 | ||
12572 | ppid->id_len = sizeof(bp->phys_port_id); | |
12573 | memcpy(ppid->id, bp->phys_port_id, ppid->id_len); | |
12574 | ||
12575 | return 0; | |
12576 | } | |
12577 | ||
5f35227e JG |
12578 | static netdev_features_t bnx2x_features_check(struct sk_buff *skb, |
12579 | struct net_device *dev, | |
12580 | netdev_features_t features) | |
51de7bb9 | 12581 | { |
8cb65d00 | 12582 | features = vlan_features_check(skb, features); |
5f35227e | 12583 | return vxlan_features_check(skb, features); |
51de7bb9 JS |
12584 | } |
12585 | ||
c64213cd SH |
12586 | static const struct net_device_ops bnx2x_netdev_ops = { |
12587 | .ndo_open = bnx2x_open, | |
12588 | .ndo_stop = bnx2x_close, | |
12589 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 12590 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 12591 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd | 12592 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
614c76df | 12593 | .ndo_validate_addr = bnx2x_validate_addr, |
c64213cd SH |
12594 | .ndo_do_ioctl = bnx2x_ioctl, |
12595 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
12596 | .ndo_fix_features = bnx2x_fix_features, |
12597 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 12598 | .ndo_tx_timeout = bnx2x_tx_timeout, |
257ddbda | 12599 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
12600 | .ndo_poll_controller = poll_bnx2x, |
12601 | #endif | |
6383c0b3 | 12602 | .ndo_setup_tc = bnx2x_setup_tc, |
6411280a | 12603 | #ifdef CONFIG_BNX2X_SRIOV |
abc5a021 | 12604 | .ndo_set_vf_mac = bnx2x_set_vf_mac, |
3cdeec22 | 12605 | .ndo_set_vf_vlan = bnx2x_set_vf_vlan, |
3ec9f9ca | 12606 | .ndo_get_vf_config = bnx2x_get_vf_config, |
6411280a | 12607 | #endif |
55c11941 | 12608 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
12609 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, |
12610 | #endif | |
8f20aa57 | 12611 | |
e0d1095a | 12612 | #ifdef CONFIG_NET_RX_BUSY_POLL |
8b80cda5 | 12613 | .ndo_busy_poll = bnx2x_low_latency_recv, |
8f20aa57 | 12614 | #endif |
3d7d562c | 12615 | .ndo_get_phys_port_id = bnx2x_get_phys_port_id, |
6495d15a | 12616 | .ndo_set_vf_link_state = bnx2x_set_vf_link_state, |
5f35227e | 12617 | .ndo_features_check = bnx2x_features_check, |
c64213cd SH |
12618 | }; |
12619 | ||
1191cb83 | 12620 | static int bnx2x_set_coherency_mask(struct bnx2x *bp) |
619c5cb6 VZ |
12621 | { |
12622 | struct device *dev = &bp->pdev->dev; | |
12623 | ||
8ceafbfa LT |
12624 | if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 && |
12625 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) { | |
619c5cb6 VZ |
12626 | dev_err(dev, "System does not support DMA, aborting\n"); |
12627 | return -EIO; | |
12628 | } | |
12629 | ||
12630 | return 0; | |
12631 | } | |
12632 | ||
33d8e6a5 YM |
12633 | static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp) |
12634 | { | |
12635 | if (bp->flags & AER_ENABLED) { | |
12636 | pci_disable_pcie_error_reporting(bp->pdev); | |
12637 | bp->flags &= ~AER_ENABLED; | |
12638 | } | |
12639 | } | |
12640 | ||
1ab4434c AE |
12641 | static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, |
12642 | struct net_device *dev, unsigned long board_type) | |
a2fbb9ea | 12643 | { |
a2fbb9ea | 12644 | int rc; |
c22610d0 | 12645 | u32 pci_cfg_dword; |
65087cfe AE |
12646 | bool chip_is_e1x = (board_type == BCM57710 || |
12647 | board_type == BCM57711 || | |
12648 | board_type == BCM57711E); | |
a2fbb9ea ET |
12649 | |
12650 | SET_NETDEV_DEV(dev, &pdev->dev); | |
a2fbb9ea | 12651 | |
34f80b04 EG |
12652 | bp->dev = dev; |
12653 | bp->pdev = pdev; | |
a2fbb9ea ET |
12654 | |
12655 | rc = pci_enable_device(pdev); | |
12656 | if (rc) { | |
cdaa7cb8 VZ |
12657 | dev_err(&bp->pdev->dev, |
12658 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
12659 | goto err_out; |
12660 | } | |
12661 | ||
12662 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
12663 | dev_err(&bp->pdev->dev, |
12664 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
12665 | rc = -ENODEV; |
12666 | goto err_out_disable; | |
12667 | } | |
12668 | ||
1ab4434c AE |
12669 | if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { |
12670 | dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); | |
a2fbb9ea ET |
12671 | rc = -ENODEV; |
12672 | goto err_out_disable; | |
12673 | } | |
12674 | ||
092a5fc9 YR |
12675 | pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); |
12676 | if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == | |
12677 | PCICFG_REVESION_ID_ERROR_VAL) { | |
12678 | pr_err("PCI device error, probably due to fan failure, aborting\n"); | |
12679 | rc = -ENODEV; | |
12680 | goto err_out_disable; | |
12681 | } | |
12682 | ||
34f80b04 EG |
12683 | if (atomic_read(&pdev->enable_cnt) == 1) { |
12684 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
12685 | if (rc) { | |
cdaa7cb8 VZ |
12686 | dev_err(&bp->pdev->dev, |
12687 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
12688 | goto err_out_disable; |
12689 | } | |
a2fbb9ea | 12690 | |
34f80b04 EG |
12691 | pci_set_master(pdev); |
12692 | pci_save_state(pdev); | |
12693 | } | |
a2fbb9ea | 12694 | |
1ab4434c | 12695 | if (IS_PF(bp)) { |
29ed74c3 | 12696 | if (!pdev->pm_cap) { |
1ab4434c AE |
12697 | dev_err(&bp->pdev->dev, |
12698 | "Cannot find power management capability, aborting\n"); | |
12699 | rc = -EIO; | |
12700 | goto err_out_release; | |
12701 | } | |
a2fbb9ea ET |
12702 | } |
12703 | ||
77c98e6a | 12704 | if (!pci_is_pcie(pdev)) { |
51c1a580 | 12705 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
a2fbb9ea ET |
12706 | rc = -EIO; |
12707 | goto err_out_release; | |
12708 | } | |
12709 | ||
619c5cb6 VZ |
12710 | rc = bnx2x_set_coherency_mask(bp); |
12711 | if (rc) | |
a2fbb9ea | 12712 | goto err_out_release; |
a2fbb9ea | 12713 | |
34f80b04 EG |
12714 | dev->mem_start = pci_resource_start(pdev, 0); |
12715 | dev->base_addr = dev->mem_start; | |
12716 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
12717 | |
12718 | dev->irq = pdev->irq; | |
12719 | ||
275f165f | 12720 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 12721 | if (!bp->regview) { |
cdaa7cb8 VZ |
12722 | dev_err(&bp->pdev->dev, |
12723 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
12724 | rc = -ENOMEM; |
12725 | goto err_out_release; | |
12726 | } | |
12727 | ||
c22610d0 AE |
12728 | /* In E1/E1H use pci device function given by kernel. |
12729 | * In E2/E3 read physical function from ME register since these chips | |
12730 | * support Physical Device Assignment where kernel BDF maybe arbitrary | |
12731 | * (depending on hypervisor). | |
12732 | */ | |
2de67439 | 12733 | if (chip_is_e1x) { |
c22610d0 | 12734 | bp->pf_num = PCI_FUNC(pdev->devfn); |
2de67439 YM |
12735 | } else { |
12736 | /* chip is E2/3*/ | |
c22610d0 AE |
12737 | pci_read_config_dword(bp->pdev, |
12738 | PCICFG_ME_REGISTER, &pci_cfg_dword); | |
12739 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> | |
2de67439 | 12740 | ME_REG_ABS_PF_NUM_SHIFT); |
c22610d0 | 12741 | } |
51c1a580 | 12742 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
c22610d0 | 12743 | |
34f80b04 EG |
12744 | /* clean indirect addresses */ |
12745 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
12746 | PCICFG_VENDOR_ID_OFFSET); | |
33d8e6a5 | 12747 | |
da293700 BK |
12748 | /* Set PCIe reset type to fundamental for EEH recovery */ |
12749 | pdev->needs_freset = 1; | |
12750 | ||
33d8e6a5 YM |
12751 | /* AER (Advanced Error reporting) configuration */ |
12752 | rc = pci_enable_pcie_error_reporting(pdev); | |
12753 | if (!rc) | |
12754 | bp->flags |= AER_ENABLED; | |
12755 | else | |
12756 | BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc); | |
12757 | ||
a5c53dbc DK |
12758 | /* |
12759 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
12760 | * is not used by the driver. |
12761 | */ | |
1ab4434c AE |
12762 | if (IS_PF(bp)) { |
12763 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
12764 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
12765 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
12766 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
12767 | ||
12768 | if (chip_is_e1x) { | |
12769 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); | |
12770 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
12771 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
12772 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
12773 | } | |
a5c53dbc | 12774 | |
1ab4434c AE |
12775 | /* Enable internal target-read (in case we are probed after PF |
12776 | * FLR). Must be done prior to any BAR read access. Only for | |
12777 | * 57712 and up | |
12778 | */ | |
12779 | if (!chip_is_e1x) | |
12780 | REG_WR(bp, | |
12781 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
a5c53dbc | 12782 | } |
a2fbb9ea | 12783 | |
34f80b04 | 12784 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 12785 | |
c64213cd | 12786 | dev->netdev_ops = &bnx2x_netdev_ops; |
005a07ba | 12787 | bnx2x_set_ethtool_ops(bp, dev); |
5316bc0b | 12788 | |
01789349 JP |
12789 | dev->priv_flags |= IFF_UNICAST_FLT; |
12790 | ||
66371c44 | 12791 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
621b4d66 DK |
12792 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
12793 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | | |
f646968f | 12794 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX; |
a8e0c246 | 12795 | if (!chip_is_e1x) { |
117401ee | 12796 | dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL | |
2e3bd6a4 | 12797 | NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT; |
a848ade4 DK |
12798 | dev->hw_enc_features = |
12799 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | | |
12800 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | | |
117401ee | 12801 | NETIF_F_GSO_IPIP | |
2e3bd6a4 | 12802 | NETIF_F_GSO_SIT | |
65bc0cfe | 12803 | NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL; |
a848ade4 | 12804 | } |
66371c44 MM |
12805 | |
12806 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
12807 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
12808 | ||
f646968f | 12809 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; |
edd31476 | 12810 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 12811 | |
538dd2e3 MB |
12812 | /* Add Loopback capability to the device */ |
12813 | dev->hw_features |= NETIF_F_LOOPBACK; | |
12814 | ||
98507672 | 12815 | #ifdef BCM_DCBNL |
785b9b1a SR |
12816 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
12817 | #endif | |
12818 | ||
01cd4528 EG |
12819 | /* get_port_hwinfo() will set prtad and mmds properly */ |
12820 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
12821 | bp->mdio.mmds = 0; | |
12822 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
12823 | bp->mdio.dev = dev; | |
12824 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
12825 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
12826 | ||
a2fbb9ea ET |
12827 | return 0; |
12828 | ||
a2fbb9ea | 12829 | err_out_release: |
34f80b04 EG |
12830 | if (atomic_read(&pdev->enable_cnt) == 1) |
12831 | pci_release_regions(pdev); | |
a2fbb9ea ET |
12832 | |
12833 | err_out_disable: | |
12834 | pci_disable_device(pdev); | |
a2fbb9ea ET |
12835 | |
12836 | err_out: | |
12837 | return rc; | |
12838 | } | |
12839 | ||
6891dd25 | 12840 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 12841 | { |
37f9ce62 | 12842 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
12843 | struct bnx2x_fw_file_hdr *fw_hdr; |
12844 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 12845 | u32 offset, len, num_ops; |
86564c3f | 12846 | __be16 *ops_offsets; |
94a78b79 | 12847 | int i; |
37f9ce62 | 12848 | const u8 *fw_ver; |
94a78b79 | 12849 | |
51c1a580 MS |
12850 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
12851 | BNX2X_ERR("Wrong FW size\n"); | |
94a78b79 | 12852 | return -EINVAL; |
51c1a580 | 12853 | } |
94a78b79 VZ |
12854 | |
12855 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
12856 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
12857 | ||
12858 | /* Make sure none of the offsets and sizes make us read beyond | |
12859 | * the end of the firmware data */ | |
12860 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
12861 | offset = be32_to_cpu(sections[i].offset); | |
12862 | len = be32_to_cpu(sections[i].len); | |
12863 | if (offset + len > firmware->size) { | |
51c1a580 | 12864 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
94a78b79 VZ |
12865 | return -EINVAL; |
12866 | } | |
12867 | } | |
12868 | ||
12869 | /* Likewise for the init_ops offsets */ | |
12870 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
86564c3f | 12871 | ops_offsets = (__force __be16 *)(firmware->data + offset); |
94a78b79 VZ |
12872 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); |
12873 | ||
12874 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
12875 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
51c1a580 | 12876 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
94a78b79 VZ |
12877 | return -EINVAL; |
12878 | } | |
12879 | } | |
12880 | ||
12881 | /* Check FW version */ | |
12882 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
12883 | fw_ver = firmware->data + offset; | |
12884 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
12885 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
12886 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
12887 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
51c1a580 MS |
12888 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
12889 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], | |
12890 | BCM_5710_FW_MAJOR_VERSION, | |
94a78b79 VZ |
12891 | BCM_5710_FW_MINOR_VERSION, |
12892 | BCM_5710_FW_REVISION_VERSION, | |
12893 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 12894 | return -EINVAL; |
94a78b79 VZ |
12895 | } |
12896 | ||
12897 | return 0; | |
12898 | } | |
12899 | ||
1191cb83 | 12900 | static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 12901 | { |
ab6ad5a4 EG |
12902 | const __be32 *source = (const __be32 *)_source; |
12903 | u32 *target = (u32 *)_target; | |
94a78b79 | 12904 | u32 i; |
94a78b79 VZ |
12905 | |
12906 | for (i = 0; i < n/4; i++) | |
12907 | target[i] = be32_to_cpu(source[i]); | |
12908 | } | |
12909 | ||
12910 | /* | |
12911 | Ops array is stored in the following format: | |
12912 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
12913 | */ | |
1191cb83 | 12914 | static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 12915 | { |
ab6ad5a4 EG |
12916 | const __be32 *source = (const __be32 *)_source; |
12917 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 12918 | u32 i, j, tmp; |
94a78b79 | 12919 | |
ab6ad5a4 | 12920 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
12921 | tmp = be32_to_cpu(source[j]); |
12922 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
12923 | target[i].offset = tmp & 0xffffff; |
12924 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
12925 | } |
12926 | } | |
ab6ad5a4 | 12927 | |
1aa8b471 | 12928 | /* IRO array is stored in the following format: |
523224a3 DK |
12929 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } |
12930 | */ | |
1191cb83 | 12931 | static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) |
523224a3 DK |
12932 | { |
12933 | const __be32 *source = (const __be32 *)_source; | |
12934 | struct iro *target = (struct iro *)_target; | |
12935 | u32 i, j, tmp; | |
12936 | ||
12937 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
12938 | target[i].base = be32_to_cpu(source[j]); | |
12939 | j++; | |
12940 | tmp = be32_to_cpu(source[j]); | |
12941 | target[i].m1 = (tmp >> 16) & 0xffff; | |
12942 | target[i].m2 = tmp & 0xffff; | |
12943 | j++; | |
12944 | tmp = be32_to_cpu(source[j]); | |
12945 | target[i].m3 = (tmp >> 16) & 0xffff; | |
12946 | target[i].size = tmp & 0xffff; | |
12947 | j++; | |
12948 | } | |
12949 | } | |
12950 | ||
1191cb83 | 12951 | static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 12952 | { |
ab6ad5a4 EG |
12953 | const __be16 *source = (const __be16 *)_source; |
12954 | u16 *target = (u16 *)_target; | |
94a78b79 | 12955 | u32 i; |
94a78b79 VZ |
12956 | |
12957 | for (i = 0; i < n/2; i++) | |
12958 | target[i] = be16_to_cpu(source[i]); | |
12959 | } | |
12960 | ||
7995c64e JP |
12961 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
12962 | do { \ | |
12963 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
12964 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
e404decb | 12965 | if (!bp->arr) \ |
7995c64e | 12966 | goto lbl; \ |
7995c64e JP |
12967 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
12968 | (u8 *)bp->arr, len); \ | |
12969 | } while (0) | |
94a78b79 | 12970 | |
3b603066 | 12971 | static int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 12972 | { |
c0ea452e | 12973 | const char *fw_file_name; |
94a78b79 | 12974 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 12975 | int rc; |
94a78b79 | 12976 | |
c0ea452e MS |
12977 | if (bp->firmware) |
12978 | return 0; | |
94a78b79 | 12979 | |
c0ea452e MS |
12980 | if (CHIP_IS_E1(bp)) |
12981 | fw_file_name = FW_FILE_NAME_E1; | |
12982 | else if (CHIP_IS_E1H(bp)) | |
12983 | fw_file_name = FW_FILE_NAME_E1H; | |
12984 | else if (!CHIP_IS_E1x(bp)) | |
12985 | fw_file_name = FW_FILE_NAME_E2; | |
12986 | else { | |
12987 | BNX2X_ERR("Unsupported chip revision\n"); | |
12988 | return -EINVAL; | |
12989 | } | |
12990 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); | |
94a78b79 | 12991 | |
c0ea452e MS |
12992 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
12993 | if (rc) { | |
12994 | BNX2X_ERR("Can't load firmware file %s\n", | |
12995 | fw_file_name); | |
12996 | goto request_firmware_exit; | |
12997 | } | |
eb2afd4a | 12998 | |
c0ea452e MS |
12999 | rc = bnx2x_check_firmware(bp); |
13000 | if (rc) { | |
13001 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); | |
13002 | goto request_firmware_exit; | |
94a78b79 VZ |
13003 | } |
13004 | ||
13005 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
13006 | ||
13007 | /* Initialize the pointers to the init arrays */ | |
13008 | /* Blob */ | |
13009 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
13010 | ||
13011 | /* Opcodes */ | |
13012 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
13013 | ||
13014 | /* Offsets */ | |
ab6ad5a4 EG |
13015 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
13016 | be16_to_cpu_n); | |
94a78b79 VZ |
13017 | |
13018 | /* STORMs firmware */ | |
573f2035 EG |
13019 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
13020 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
13021 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
13022 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
13023 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
13024 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
13025 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
13026 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
13027 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
13028 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
13029 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
13030 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
13031 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
13032 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
13033 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
13034 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
13035 | /* IRO */ |
13036 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
13037 | |
13038 | return 0; | |
ab6ad5a4 | 13039 | |
523224a3 DK |
13040 | iro_alloc_err: |
13041 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
13042 | init_offsets_alloc_err: |
13043 | kfree(bp->init_ops); | |
13044 | init_ops_alloc_err: | |
13045 | kfree(bp->init_data); | |
13046 | request_firmware_exit: | |
13047 | release_firmware(bp->firmware); | |
127d0a19 | 13048 | bp->firmware = NULL; |
94a78b79 VZ |
13049 | |
13050 | return rc; | |
13051 | } | |
13052 | ||
619c5cb6 VZ |
13053 | static void bnx2x_release_firmware(struct bnx2x *bp) |
13054 | { | |
13055 | kfree(bp->init_ops_offsets); | |
13056 | kfree(bp->init_ops); | |
13057 | kfree(bp->init_data); | |
13058 | release_firmware(bp->firmware); | |
eb2afd4a | 13059 | bp->firmware = NULL; |
619c5cb6 VZ |
13060 | } |
13061 | ||
619c5cb6 VZ |
13062 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { |
13063 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
13064 | .init_hw_cmn = bnx2x_init_hw_common, | |
13065 | .init_hw_port = bnx2x_init_hw_port, | |
13066 | .init_hw_func = bnx2x_init_hw_func, | |
13067 | ||
13068 | .reset_hw_cmn = bnx2x_reset_common, | |
13069 | .reset_hw_port = bnx2x_reset_port, | |
13070 | .reset_hw_func = bnx2x_reset_func, | |
13071 | ||
13072 | .gunzip_init = bnx2x_gunzip_init, | |
13073 | .gunzip_end = bnx2x_gunzip_end, | |
13074 | ||
13075 | .init_fw = bnx2x_init_firmware, | |
13076 | .release_fw = bnx2x_release_firmware, | |
13077 | }; | |
13078 | ||
13079 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
13080 | { | |
13081 | /* Prepare DMAE related driver resources */ | |
13082 | bnx2x_setup_dmae(bp); | |
13083 | ||
13084 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
13085 | bnx2x_sp(bp, func_rdata), | |
13086 | bnx2x_sp_mapping(bp, func_rdata), | |
a3348722 BW |
13087 | bnx2x_sp(bp, func_afex_rdata), |
13088 | bnx2x_sp_mapping(bp, func_afex_rdata), | |
619c5cb6 VZ |
13089 | &bnx2x_func_sp_drv); |
13090 | } | |
13091 | ||
13092 | /* must be called after sriov-enable */ | |
1191cb83 | 13093 | static int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 13094 | { |
37ae41a9 | 13095 | int cid_count = BNX2X_L2_MAX_CID(bp); |
94a78b79 | 13096 | |
290ca2bb AE |
13097 | if (IS_SRIOV(bp)) |
13098 | cid_count += BNX2X_VF_CIDS; | |
13099 | ||
55c11941 MS |
13100 | if (CNIC_SUPPORT(bp)) |
13101 | cid_count += CNIC_CID_MAX; | |
290ca2bb | 13102 | |
523224a3 DK |
13103 | return roundup(cid_count, QM_CID_ROUND); |
13104 | } | |
f85582f8 | 13105 | |
619c5cb6 | 13106 | /** |
6383c0b3 | 13107 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
13108 | * |
13109 | * @dev: pci device | |
13110 | * | |
13111 | */ | |
60cad4e6 | 13112 | static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt) |
619c5cb6 | 13113 | { |
ae2104be | 13114 | int index; |
1ab4434c | 13115 | u16 control = 0; |
619c5cb6 | 13116 | |
6383c0b3 AE |
13117 | /* |
13118 | * If MSI-X is not supported - return number of SBs needed to support | |
13119 | * one fast path queue: one FP queue + SB for CNIC | |
13120 | */ | |
ae2104be | 13121 | if (!pdev->msix_cap) { |
1ab4434c | 13122 | dev_info(&pdev->dev, "no msix capability found\n"); |
55c11941 | 13123 | return 1 + cnic_cnt; |
1ab4434c AE |
13124 | } |
13125 | dev_info(&pdev->dev, "msix capability found\n"); | |
619c5cb6 | 13126 | |
6383c0b3 AE |
13127 | /* |
13128 | * The value in the PCI configuration space is the index of the last | |
13129 | * entry, namely one less than the actual size of the table, which is | |
13130 | * exactly what we want to return from this function: number of all SBs | |
13131 | * without the default SB. | |
1ab4434c | 13132 | * For VFs there is no default SB, then we return (index+1). |
6383c0b3 | 13133 | */ |
73413ffa | 13134 | pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control); |
619c5cb6 | 13135 | |
1ab4434c | 13136 | index = control & PCI_MSIX_FLAGS_QSIZE; |
4bd9b0ff | 13137 | |
60cad4e6 | 13138 | return index; |
1ab4434c | 13139 | } |
523224a3 | 13140 | |
1ab4434c AE |
13141 | static int set_max_cos_est(int chip_id) |
13142 | { | |
13143 | switch (chip_id) { | |
f2e0899f DK |
13144 | case BCM57710: |
13145 | case BCM57711: | |
13146 | case BCM57711E: | |
1ab4434c | 13147 | return BNX2X_MULTI_TX_COS_E1X; |
f2e0899f | 13148 | case BCM57712: |
619c5cb6 | 13149 | case BCM57712_MF: |
1ab4434c | 13150 | return BNX2X_MULTI_TX_COS_E2_E3A0; |
619c5cb6 VZ |
13151 | case BCM57800: |
13152 | case BCM57800_MF: | |
13153 | case BCM57810: | |
13154 | case BCM57810_MF: | |
c3def943 YM |
13155 | case BCM57840_4_10: |
13156 | case BCM57840_2_20: | |
1ab4434c | 13157 | case BCM57840_O: |
c3def943 | 13158 | case BCM57840_MFO: |
619c5cb6 | 13159 | case BCM57840_MF: |
7e8e02df BW |
13160 | case BCM57811: |
13161 | case BCM57811_MF: | |
1ab4434c | 13162 | return BNX2X_MULTI_TX_COS_E3B0; |
b1239723 YM |
13163 | case BCM57712_VF: |
13164 | case BCM57800_VF: | |
13165 | case BCM57810_VF: | |
13166 | case BCM57840_VF: | |
13167 | case BCM57811_VF: | |
1ab4434c | 13168 | return 1; |
f2e0899f | 13169 | default: |
1ab4434c | 13170 | pr_err("Unknown board_type (%d), aborting\n", chip_id); |
870634b0 | 13171 | return -ENODEV; |
f2e0899f | 13172 | } |
1ab4434c | 13173 | } |
f2e0899f | 13174 | |
1ab4434c AE |
13175 | static int set_is_vf(int chip_id) |
13176 | { | |
13177 | switch (chip_id) { | |
13178 | case BCM57712_VF: | |
13179 | case BCM57800_VF: | |
13180 | case BCM57810_VF: | |
13181 | case BCM57840_VF: | |
13182 | case BCM57811_VF: | |
13183 | return true; | |
13184 | default: | |
13185 | return false; | |
13186 | } | |
13187 | } | |
6383c0b3 | 13188 | |
eeed018c MK |
13189 | /* nig_tsgen registers relative address */ |
13190 | #define tsgen_ctrl 0x0 | |
13191 | #define tsgen_freecount 0x10 | |
13192 | #define tsgen_synctime_t0 0x20 | |
13193 | #define tsgen_offset_t0 0x28 | |
13194 | #define tsgen_drift_t0 0x30 | |
13195 | #define tsgen_synctime_t1 0x58 | |
13196 | #define tsgen_offset_t1 0x60 | |
13197 | #define tsgen_drift_t1 0x68 | |
13198 | ||
13199 | /* FW workaround for setting drift */ | |
13200 | static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir, | |
13201 | int best_val, int best_period) | |
13202 | { | |
13203 | struct bnx2x_func_state_params func_params = {NULL}; | |
13204 | struct bnx2x_func_set_timesync_params *set_timesync_params = | |
13205 | &func_params.params.set_timesync; | |
13206 | ||
13207 | /* Prepare parameters for function state transitions */ | |
13208 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
13209 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
13210 | ||
13211 | func_params.f_obj = &bp->func_obj; | |
13212 | func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; | |
13213 | ||
13214 | /* Function parameters */ | |
13215 | set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET; | |
13216 | set_timesync_params->offset_cmd = TS_OFFSET_KEEP; | |
13217 | set_timesync_params->add_sub_drift_adjust_value = | |
13218 | drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE; | |
13219 | set_timesync_params->drift_adjust_value = best_val; | |
13220 | set_timesync_params->drift_adjust_period = best_period; | |
13221 | ||
13222 | return bnx2x_func_state_change(bp, &func_params); | |
13223 | } | |
13224 | ||
13225 | static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) | |
13226 | { | |
13227 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13228 | int rc; | |
13229 | int drift_dir = 1; | |
13230 | int val, period, period1, period2, dif, dif1, dif2; | |
13231 | int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0; | |
13232 | ||
13233 | DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb); | |
13234 | ||
13235 | if (!netif_running(bp->dev)) { | |
13236 | DP(BNX2X_MSG_PTP, | |
13237 | "PTP adjfreq called while the interface is down\n"); | |
13238 | return -EFAULT; | |
13239 | } | |
13240 | ||
13241 | if (ppb < 0) { | |
13242 | ppb = -ppb; | |
13243 | drift_dir = 0; | |
13244 | } | |
13245 | ||
13246 | if (ppb == 0) { | |
13247 | best_val = 1; | |
13248 | best_period = 0x1FFFFFF; | |
13249 | } else if (ppb >= BNX2X_MAX_PHC_DRIFT) { | |
13250 | best_val = 31; | |
13251 | best_period = 1; | |
13252 | } else { | |
13253 | /* Changed not to allow val = 8, 16, 24 as these values | |
13254 | * are not supported in workaround. | |
13255 | */ | |
13256 | for (val = 0; val <= 31; val++) { | |
13257 | if ((val & 0x7) == 0) | |
13258 | continue; | |
13259 | period1 = val * 1000000 / ppb; | |
13260 | period2 = period1 + 1; | |
13261 | if (period1 != 0) | |
13262 | dif1 = ppb - (val * 1000000 / period1); | |
13263 | else | |
13264 | dif1 = BNX2X_MAX_PHC_DRIFT; | |
13265 | if (dif1 < 0) | |
13266 | dif1 = -dif1; | |
13267 | dif2 = ppb - (val * 1000000 / period2); | |
13268 | if (dif2 < 0) | |
13269 | dif2 = -dif2; | |
13270 | dif = (dif1 < dif2) ? dif1 : dif2; | |
13271 | period = (dif1 < dif2) ? period1 : period2; | |
13272 | if (dif < best_dif) { | |
13273 | best_dif = dif; | |
13274 | best_val = val; | |
13275 | best_period = period; | |
13276 | } | |
13277 | } | |
13278 | } | |
13279 | ||
13280 | rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val, | |
13281 | best_period); | |
13282 | if (rc) { | |
13283 | BNX2X_ERR("Failed to set drift\n"); | |
13284 | return -EFAULT; | |
13285 | } | |
13286 | ||
bf27c353 | 13287 | DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val, |
eeed018c MK |
13288 | best_period); |
13289 | ||
13290 | return 0; | |
13291 | } | |
13292 | ||
13293 | static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) | |
13294 | { | |
13295 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
eeed018c MK |
13296 | |
13297 | DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta); | |
13298 | ||
2e5601f9 | 13299 | timecounter_adjtime(&bp->timecounter, delta); |
eeed018c MK |
13300 | |
13301 | return 0; | |
13302 | } | |
13303 | ||
5d45186b | 13304 | static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) |
eeed018c MK |
13305 | { |
13306 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13307 | u64 ns; | |
eeed018c MK |
13308 | |
13309 | ns = timecounter_read(&bp->timecounter); | |
13310 | ||
13311 | DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns); | |
13312 | ||
f7dcdefe | 13313 | *ts = ns_to_timespec64(ns); |
eeed018c MK |
13314 | |
13315 | return 0; | |
13316 | } | |
13317 | ||
13318 | static int bnx2x_ptp_settime(struct ptp_clock_info *ptp, | |
5d45186b | 13319 | const struct timespec64 *ts) |
eeed018c MK |
13320 | { |
13321 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13322 | u64 ns; | |
13323 | ||
f7dcdefe | 13324 | ns = timespec64_to_ns(ts); |
eeed018c MK |
13325 | |
13326 | DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns); | |
13327 | ||
13328 | /* Re-init the timecounter */ | |
13329 | timecounter_init(&bp->timecounter, &bp->cyclecounter, ns); | |
13330 | ||
13331 | return 0; | |
13332 | } | |
13333 | ||
13334 | /* Enable (or disable) ancillary features of the phc subsystem */ | |
13335 | static int bnx2x_ptp_enable(struct ptp_clock_info *ptp, | |
13336 | struct ptp_clock_request *rq, int on) | |
13337 | { | |
13338 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13339 | ||
13340 | BNX2X_ERR("PHC ancillary features are not supported\n"); | |
13341 | return -ENOTSUPP; | |
13342 | } | |
13343 | ||
1444c301 | 13344 | static void bnx2x_register_phc(struct bnx2x *bp) |
eeed018c MK |
13345 | { |
13346 | /* Fill the ptp_clock_info struct and register PTP clock*/ | |
13347 | bp->ptp_clock_info.owner = THIS_MODULE; | |
13348 | snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name); | |
13349 | bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */ | |
13350 | bp->ptp_clock_info.n_alarm = 0; | |
13351 | bp->ptp_clock_info.n_ext_ts = 0; | |
13352 | bp->ptp_clock_info.n_per_out = 0; | |
13353 | bp->ptp_clock_info.pps = 0; | |
13354 | bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq; | |
13355 | bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime; | |
5d45186b RC |
13356 | bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime; |
13357 | bp->ptp_clock_info.settime64 = bnx2x_ptp_settime; | |
eeed018c MK |
13358 | bp->ptp_clock_info.enable = bnx2x_ptp_enable; |
13359 | ||
13360 | bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev); | |
13361 | if (IS_ERR(bp->ptp_clock)) { | |
13362 | bp->ptp_clock = NULL; | |
13363 | BNX2X_ERR("PTP clock registeration failed\n"); | |
13364 | } | |
13365 | } | |
13366 | ||
1ab4434c AE |
13367 | static int bnx2x_init_one(struct pci_dev *pdev, |
13368 | const struct pci_device_id *ent) | |
13369 | { | |
13370 | struct net_device *dev = NULL; | |
13371 | struct bnx2x *bp; | |
b91e1a1a YM |
13372 | enum pcie_link_width pcie_width; |
13373 | enum pci_bus_speed pcie_speed; | |
1ab4434c AE |
13374 | int rc, max_non_def_sbs; |
13375 | int rx_count, tx_count, rss_count, doorbell_size; | |
13376 | int max_cos_est; | |
13377 | bool is_vf; | |
13378 | int cnic_cnt; | |
13379 | ||
12a8541d YM |
13380 | /* Management FW 'remembers' living interfaces. Allow it some time |
13381 | * to forget previously living interfaces, allowing a proper re-load. | |
13382 | */ | |
cd9c3997 MS |
13383 | if (is_kdump_kernel()) { |
13384 | ktime_t now = ktime_get_boottime(); | |
13385 | ktime_t fw_ready_time = ktime_set(5, 0); | |
13386 | ||
13387 | if (ktime_before(now, fw_ready_time)) | |
13388 | msleep(ktime_ms_delta(fw_ready_time, now)); | |
13389 | } | |
12a8541d | 13390 | |
1ab4434c AE |
13391 | /* An estimated maximum supported CoS number according to the chip |
13392 | * version. | |
13393 | * We will try to roughly estimate the maximum number of CoSes this chip | |
13394 | * may support in order to minimize the memory allocated for Tx | |
13395 | * netdev_queue's. This number will be accurately calculated during the | |
13396 | * initialization of bp->max_cos based on the chip versions AND chip | |
13397 | * revision in the bnx2x_init_bp(). | |
13398 | */ | |
13399 | max_cos_est = set_max_cos_est(ent->driver_data); | |
13400 | if (max_cos_est < 0) | |
13401 | return max_cos_est; | |
13402 | is_vf = set_is_vf(ent->driver_data); | |
13403 | cnic_cnt = is_vf ? 0 : 1; | |
13404 | ||
60cad4e6 AE |
13405 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt); |
13406 | ||
13407 | /* add another SB for VF as it has no default SB */ | |
13408 | max_non_def_sbs += is_vf ? 1 : 0; | |
6383c0b3 AE |
13409 | |
13410 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
60cad4e6 | 13411 | rss_count = max_non_def_sbs - cnic_cnt; |
1ab4434c AE |
13412 | |
13413 | if (rss_count < 1) | |
13414 | return -EINVAL; | |
6383c0b3 AE |
13415 | |
13416 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
55c11941 | 13417 | rx_count = rss_count + cnic_cnt; |
6383c0b3 | 13418 | |
1ab4434c | 13419 | /* Maximum number of netdev Tx queues: |
37ae41a9 | 13420 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 |
6383c0b3 | 13421 | */ |
55c11941 | 13422 | tx_count = rss_count * max_cos_est + cnic_cnt; |
f85582f8 | 13423 | |
a2fbb9ea | 13424 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 13425 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
41de8d4c | 13426 | if (!dev) |
a2fbb9ea ET |
13427 | return -ENOMEM; |
13428 | ||
a2fbb9ea | 13429 | bp = netdev_priv(dev); |
a2fbb9ea | 13430 | |
1ab4434c AE |
13431 | bp->flags = 0; |
13432 | if (is_vf) | |
13433 | bp->flags |= IS_VF_FLAG; | |
13434 | ||
6383c0b3 | 13435 | bp->igu_sb_cnt = max_non_def_sbs; |
1ab4434c | 13436 | bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; |
6383c0b3 | 13437 | bp->msg_enable = debug; |
55c11941 | 13438 | bp->cnic_support = cnic_cnt; |
4bd9b0ff | 13439 | bp->cnic_probe = bnx2x_cnic_probe; |
55c11941 | 13440 | |
6383c0b3 | 13441 | pci_set_drvdata(pdev, dev); |
523224a3 | 13442 | |
1ab4434c | 13443 | rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); |
a2fbb9ea ET |
13444 | if (rc < 0) { |
13445 | free_netdev(dev); | |
13446 | return rc; | |
13447 | } | |
13448 | ||
1ab4434c AE |
13449 | BNX2X_DEV_INFO("This is a %s function\n", |
13450 | IS_PF(bp) ? "physical" : "virtual"); | |
55c11941 | 13451 | BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); |
1ab4434c | 13452 | BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); |
60aa0509 | 13453 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
2de67439 | 13454 | tx_count, rx_count); |
60aa0509 | 13455 | |
34f80b04 | 13456 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
13457 | if (rc) |
13458 | goto init_one_exit; | |
13459 | ||
1ab4434c AE |
13460 | /* Map doorbells here as we need the real value of bp->max_cos which |
13461 | * is initialized in bnx2x_init_bp() to determine the number of | |
13462 | * l2 connections. | |
6383c0b3 | 13463 | */ |
1ab4434c | 13464 | if (IS_VF(bp)) { |
1d6f3cd8 | 13465 | bp->doorbells = bnx2x_vf_doorbells(bp); |
6411280a AE |
13466 | rc = bnx2x_vf_pci_alloc(bp); |
13467 | if (rc) | |
13468 | goto init_one_exit; | |
1ab4434c AE |
13469 | } else { |
13470 | doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); | |
13471 | if (doorbell_size > pci_resource_len(pdev, 2)) { | |
13472 | dev_err(&bp->pdev->dev, | |
13473 | "Cannot map doorbells, bar size too small, aborting\n"); | |
13474 | rc = -ENOMEM; | |
13475 | goto init_one_exit; | |
13476 | } | |
13477 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), | |
13478 | doorbell_size); | |
37ae41a9 | 13479 | } |
6383c0b3 AE |
13480 | if (!bp->doorbells) { |
13481 | dev_err(&bp->pdev->dev, | |
13482 | "Cannot map doorbell space, aborting\n"); | |
13483 | rc = -ENOMEM; | |
13484 | goto init_one_exit; | |
13485 | } | |
13486 | ||
be1f1ffa AE |
13487 | if (IS_VF(bp)) { |
13488 | rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); | |
13489 | if (rc) | |
13490 | goto init_one_exit; | |
13491 | } | |
13492 | ||
3c76feff AE |
13493 | /* Enable SRIOV if capability found in configuration space */ |
13494 | rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); | |
290ca2bb AE |
13495 | if (rc) |
13496 | goto init_one_exit; | |
13497 | ||
523224a3 | 13498 | /* calc qm_cid_count */ |
6383c0b3 | 13499 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
1ab4434c | 13500 | BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); |
523224a3 | 13501 | |
55c11941 | 13502 | /* disable FCOE L2 queue for E1x*/ |
62ac0dc9 | 13503 | if (CHIP_IS_E1x(bp)) |
ec6ba945 VZ |
13504 | bp->flags |= NO_FCOE_FLAG; |
13505 | ||
0e8d2ec5 MS |
13506 | /* Set bp->num_queues for MSI-X mode*/ |
13507 | bnx2x_set_num_queues(bp); | |
13508 | ||
25985edc | 13509 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
0e8d2ec5 | 13510 | * needed. |
d6214d7a | 13511 | */ |
1ab4434c AE |
13512 | rc = bnx2x_set_int_mode(bp); |
13513 | if (rc) { | |
13514 | dev_err(&pdev->dev, "Cannot set interrupts\n"); | |
13515 | goto init_one_exit; | |
13516 | } | |
04c46736 | 13517 | BNX2X_DEV_INFO("set interrupts successfully\n"); |
d6214d7a | 13518 | |
1ab4434c | 13519 | /* register the net device */ |
b340007f VZ |
13520 | rc = register_netdev(dev); |
13521 | if (rc) { | |
13522 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
13523 | goto init_one_exit; | |
13524 | } | |
1ab4434c | 13525 | BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); |
b340007f | 13526 | |
ec6ba945 VZ |
13527 | if (!NO_FCOE(bp)) { |
13528 | /* Add storage MAC address */ | |
13529 | rtnl_lock(); | |
13530 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
13531 | rtnl_unlock(); | |
13532 | } | |
b91e1a1a YM |
13533 | if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) || |
13534 | pcie_speed == PCI_SPEED_UNKNOWN || | |
13535 | pcie_width == PCIE_LNK_WIDTH_UNKNOWN) | |
13536 | BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n"); | |
13537 | else | |
13538 | BNX2X_DEV_INFO( | |
13539 | "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", | |
ca1ee4b2 DK |
13540 | board_info[ent->driver_data].name, |
13541 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
13542 | pcie_width, | |
b91e1a1a YM |
13543 | pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" : |
13544 | pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" : | |
13545 | pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" : | |
ca1ee4b2 DK |
13546 | "Unknown", |
13547 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
c016201c | 13548 | |
eeed018c MK |
13549 | bnx2x_register_phc(bp); |
13550 | ||
a2fbb9ea | 13551 | return 0; |
34f80b04 EG |
13552 | |
13553 | init_one_exit: | |
33d8e6a5 YM |
13554 | bnx2x_disable_pcie_error_reporting(bp); |
13555 | ||
34f80b04 EG |
13556 | if (bp->regview) |
13557 | iounmap(bp->regview); | |
13558 | ||
1ab4434c | 13559 | if (IS_PF(bp) && bp->doorbells) |
34f80b04 EG |
13560 | iounmap(bp->doorbells); |
13561 | ||
13562 | free_netdev(dev); | |
13563 | ||
13564 | if (atomic_read(&pdev->enable_cnt) == 1) | |
13565 | pci_release_regions(pdev); | |
13566 | ||
13567 | pci_disable_device(pdev); | |
34f80b04 EG |
13568 | |
13569 | return rc; | |
a2fbb9ea ET |
13570 | } |
13571 | ||
b030ed2f YM |
13572 | static void __bnx2x_remove(struct pci_dev *pdev, |
13573 | struct net_device *dev, | |
13574 | struct bnx2x *bp, | |
13575 | bool remove_netdev) | |
a2fbb9ea | 13576 | { |
eeed018c MK |
13577 | if (bp->ptp_clock) { |
13578 | ptp_clock_unregister(bp->ptp_clock); | |
13579 | bp->ptp_clock = NULL; | |
13580 | } | |
13581 | ||
ec6ba945 VZ |
13582 | /* Delete storage MAC address */ |
13583 | if (!NO_FCOE(bp)) { | |
13584 | rtnl_lock(); | |
13585 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
13586 | rtnl_unlock(); | |
13587 | } | |
ec6ba945 | 13588 | |
98507672 SR |
13589 | #ifdef BCM_DCBNL |
13590 | /* Delete app tlvs from dcbnl */ | |
13591 | bnx2x_dcbnl_update_applist(bp, true); | |
13592 | #endif | |
13593 | ||
a6d3a5ba BW |
13594 | if (IS_PF(bp) && |
13595 | !BP_NOMCP(bp) && | |
13596 | (bp->flags & BC_SUPPORTS_RMMOD_CMD)) | |
13597 | bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); | |
13598 | ||
b030ed2f YM |
13599 | /* Close the interface - either directly or implicitly */ |
13600 | if (remove_netdev) { | |
13601 | unregister_netdev(dev); | |
13602 | } else { | |
13603 | rtnl_lock(); | |
6ef5a92c | 13604 | dev_close(dev); |
b030ed2f YM |
13605 | rtnl_unlock(); |
13606 | } | |
a2fbb9ea | 13607 | |
78c3bcc5 AE |
13608 | bnx2x_iov_remove_one(bp); |
13609 | ||
084d6cbb | 13610 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
04860eb7 | 13611 | if (IS_PF(bp)) { |
1ab4434c | 13612 | bnx2x_set_power_state(bp, PCI_D0); |
084d6cbb | 13613 | |
04860eb7 MC |
13614 | /* Set endianity registers to reset values in case next driver |
13615 | * boots in different endianty environment. | |
13616 | */ | |
13617 | bnx2x_reset_endianity(bp); | |
13618 | } | |
13619 | ||
d6214d7a DK |
13620 | /* Disable MSI/MSI-X */ |
13621 | bnx2x_disable_msi(bp); | |
f85582f8 | 13622 | |
084d6cbb | 13623 | /* Power off */ |
1ab4434c AE |
13624 | if (IS_PF(bp)) |
13625 | bnx2x_set_power_state(bp, PCI_D3hot); | |
084d6cbb | 13626 | |
72fd0718 | 13627 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 13628 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
290ca2bb | 13629 | |
4513f925 AE |
13630 | /* send message via vfpf channel to release the resources of this vf */ |
13631 | if (IS_VF(bp)) | |
13632 | bnx2x_vfpf_release(bp); | |
72fd0718 | 13633 | |
b030ed2f YM |
13634 | /* Assumes no further PCIe PM changes will occur */ |
13635 | if (system_state == SYSTEM_POWER_OFF) { | |
13636 | pci_wake_from_d3(pdev, bp->wol); | |
13637 | pci_set_power_state(pdev, PCI_D3hot); | |
13638 | } | |
13639 | ||
33d8e6a5 | 13640 | bnx2x_disable_pcie_error_reporting(bp); |
d9aee591 YM |
13641 | if (remove_netdev) { |
13642 | if (bp->regview) | |
13643 | iounmap(bp->regview); | |
33d8e6a5 | 13644 | |
d9aee591 YM |
13645 | /* For vfs, doorbells are part of the regview and were unmapped |
13646 | * along with it. FW is only loaded by PF. | |
13647 | */ | |
13648 | if (IS_PF(bp)) { | |
13649 | if (bp->doorbells) | |
13650 | iounmap(bp->doorbells); | |
eb2afd4a | 13651 | |
d9aee591 | 13652 | bnx2x_release_firmware(bp); |
e2a367f8 YM |
13653 | } else { |
13654 | bnx2x_vf_pci_dealloc(bp); | |
d9aee591 YM |
13655 | } |
13656 | bnx2x_free_mem_bp(bp); | |
523224a3 | 13657 | |
b030ed2f | 13658 | free_netdev(dev); |
34f80b04 | 13659 | |
d9aee591 YM |
13660 | if (atomic_read(&pdev->enable_cnt) == 1) |
13661 | pci_release_regions(pdev); | |
34f80b04 | 13662 | |
5f6db130 YM |
13663 | pci_disable_device(pdev); |
13664 | } | |
a2fbb9ea ET |
13665 | } |
13666 | ||
b030ed2f YM |
13667 | static void bnx2x_remove_one(struct pci_dev *pdev) |
13668 | { | |
13669 | struct net_device *dev = pci_get_drvdata(pdev); | |
13670 | struct bnx2x *bp; | |
13671 | ||
13672 | if (!dev) { | |
13673 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); | |
13674 | return; | |
13675 | } | |
13676 | bp = netdev_priv(dev); | |
13677 | ||
13678 | __bnx2x_remove(pdev, dev, bp, true); | |
13679 | } | |
13680 | ||
f8ef6e44 YG |
13681 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
13682 | { | |
7fa6f340 | 13683 | bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; |
f8ef6e44 YG |
13684 | |
13685 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
13686 | ||
55c11941 MS |
13687 | if (CNIC_LOADED(bp)) |
13688 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
13689 | ||
619c5cb6 VZ |
13690 | /* Stop Tx */ |
13691 | bnx2x_tx_disable(bp); | |
26614ba5 MS |
13692 | /* Delete all NAPI objects */ |
13693 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
13694 | if (CNIC_LOADED(bp)) |
13695 | bnx2x_del_all_napi_cnic(bp); | |
7fa6f340 | 13696 | netdev_reset_tc(bp->dev); |
f8ef6e44 YG |
13697 | |
13698 | del_timer_sync(&bp->timer); | |
0c0e6341 | 13699 | cancel_delayed_work_sync(&bp->sp_task); |
13700 | cancel_delayed_work_sync(&bp->period_task); | |
619c5cb6 | 13701 | |
c6e36d8c YM |
13702 | if (!down_timeout(&bp->stats_lock, HZ / 10)) { |
13703 | bp->stats_state = STATS_STATE_DISABLED; | |
13704 | up(&bp->stats_lock); | |
13705 | } | |
f8ef6e44 | 13706 | |
7fa6f340 | 13707 | bnx2x_save_statistics(bp); |
f8ef6e44 | 13708 | |
619c5cb6 VZ |
13709 | netif_carrier_off(bp->dev); |
13710 | ||
f8ef6e44 YG |
13711 | return 0; |
13712 | } | |
13713 | ||
493adb1f WX |
13714 | /** |
13715 | * bnx2x_io_error_detected - called when PCI error is detected | |
13716 | * @pdev: Pointer to PCI device | |
13717 | * @state: The current pci connection state | |
13718 | * | |
13719 | * This function is called after a PCI bus error affecting | |
13720 | * this device has been detected. | |
13721 | */ | |
13722 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
13723 | pci_channel_state_t state) | |
13724 | { | |
13725 | struct net_device *dev = pci_get_drvdata(pdev); | |
13726 | struct bnx2x *bp = netdev_priv(dev); | |
13727 | ||
13728 | rtnl_lock(); | |
13729 | ||
7fa6f340 YM |
13730 | BNX2X_ERR("IO error detected\n"); |
13731 | ||
493adb1f WX |
13732 | netif_device_detach(dev); |
13733 | ||
07ce50e4 DN |
13734 | if (state == pci_channel_io_perm_failure) { |
13735 | rtnl_unlock(); | |
13736 | return PCI_ERS_RESULT_DISCONNECT; | |
13737 | } | |
13738 | ||
493adb1f | 13739 | if (netif_running(dev)) |
f8ef6e44 | 13740 | bnx2x_eeh_nic_unload(bp); |
493adb1f | 13741 | |
7fa6f340 YM |
13742 | bnx2x_prev_path_mark_eeh(bp); |
13743 | ||
493adb1f WX |
13744 | pci_disable_device(pdev); |
13745 | ||
13746 | rtnl_unlock(); | |
13747 | ||
13748 | /* Request a slot reset */ | |
13749 | return PCI_ERS_RESULT_NEED_RESET; | |
13750 | } | |
13751 | ||
13752 | /** | |
13753 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
13754 | * @pdev: Pointer to PCI device | |
13755 | * | |
13756 | * Restart the card from scratch, as if from a cold-boot. | |
13757 | */ | |
13758 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
13759 | { | |
13760 | struct net_device *dev = pci_get_drvdata(pdev); | |
13761 | struct bnx2x *bp = netdev_priv(dev); | |
7fa6f340 | 13762 | int i; |
493adb1f WX |
13763 | |
13764 | rtnl_lock(); | |
7fa6f340 | 13765 | BNX2X_ERR("IO slot reset initializing...\n"); |
493adb1f WX |
13766 | if (pci_enable_device(pdev)) { |
13767 | dev_err(&pdev->dev, | |
13768 | "Cannot re-enable PCI device after reset\n"); | |
13769 | rtnl_unlock(); | |
13770 | return PCI_ERS_RESULT_DISCONNECT; | |
13771 | } | |
13772 | ||
13773 | pci_set_master(pdev); | |
13774 | pci_restore_state(pdev); | |
70632d0a | 13775 | pci_save_state(pdev); |
493adb1f WX |
13776 | |
13777 | if (netif_running(dev)) | |
13778 | bnx2x_set_power_state(bp, PCI_D0); | |
13779 | ||
7fa6f340 YM |
13780 | if (netif_running(dev)) { |
13781 | BNX2X_ERR("IO slot reset --> driver unload\n"); | |
e68072ef YM |
13782 | |
13783 | /* MCP should have been reset; Need to wait for validity */ | |
13784 | bnx2x_init_shmem(bp); | |
13785 | ||
7fa6f340 YM |
13786 | if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { |
13787 | u32 v; | |
13788 | ||
13789 | v = SHMEM2_RD(bp, | |
13790 | drv_capabilities_flag[BP_FW_MB_IDX(bp)]); | |
13791 | SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], | |
13792 | v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); | |
13793 | } | |
13794 | bnx2x_drain_tx_queues(bp); | |
13795 | bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); | |
13796 | bnx2x_netif_stop(bp, 1); | |
13797 | bnx2x_free_irq(bp); | |
13798 | ||
13799 | /* Report UNLOAD_DONE to MCP */ | |
13800 | bnx2x_send_unload_done(bp, true); | |
13801 | ||
13802 | bp->sp_state = 0; | |
13803 | bp->port.pmf = 0; | |
13804 | ||
13805 | bnx2x_prev_unload(bp); | |
13806 | ||
16a5fd92 | 13807 | /* We should have reseted the engine, so It's fair to |
7fa6f340 YM |
13808 | * assume the FW will no longer write to the bnx2x driver. |
13809 | */ | |
13810 | bnx2x_squeeze_objects(bp); | |
13811 | bnx2x_free_skbs(bp); | |
13812 | for_each_rx_queue(bp, i) | |
13813 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); | |
13814 | bnx2x_free_fp_mem(bp); | |
13815 | bnx2x_free_mem(bp); | |
13816 | ||
13817 | bp->state = BNX2X_STATE_CLOSED; | |
13818 | } | |
13819 | ||
493adb1f WX |
13820 | rtnl_unlock(); |
13821 | ||
33d8e6a5 YM |
13822 | /* If AER, perform cleanup of the PCIe registers */ |
13823 | if (bp->flags & AER_ENABLED) { | |
13824 | if (pci_cleanup_aer_uncorrect_error_status(pdev)) | |
13825 | BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n"); | |
13826 | else | |
13827 | DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n"); | |
13828 | } | |
13829 | ||
493adb1f WX |
13830 | return PCI_ERS_RESULT_RECOVERED; |
13831 | } | |
13832 | ||
13833 | /** | |
13834 | * bnx2x_io_resume - called when traffic can start flowing again | |
13835 | * @pdev: Pointer to PCI device | |
13836 | * | |
13837 | * This callback is called when the error recovery driver tells us that | |
13838 | * its OK to resume normal operation. | |
13839 | */ | |
13840 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
13841 | { | |
13842 | struct net_device *dev = pci_get_drvdata(pdev); | |
13843 | struct bnx2x *bp = netdev_priv(dev); | |
13844 | ||
72fd0718 | 13845 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 13846 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
72fd0718 VZ |
13847 | return; |
13848 | } | |
13849 | ||
493adb1f WX |
13850 | rtnl_lock(); |
13851 | ||
7fa6f340 YM |
13852 | bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & |
13853 | DRV_MSG_SEQ_NUMBER_MASK; | |
13854 | ||
493adb1f | 13855 | if (netif_running(dev)) |
f8ef6e44 | 13856 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
13857 | |
13858 | netif_device_attach(dev); | |
13859 | ||
13860 | rtnl_unlock(); | |
13861 | } | |
13862 | ||
3646f0e5 | 13863 | static const struct pci_error_handlers bnx2x_err_handler = { |
493adb1f | 13864 | .error_detected = bnx2x_io_error_detected, |
356e2385 EG |
13865 | .slot_reset = bnx2x_io_slot_reset, |
13866 | .resume = bnx2x_io_resume, | |
493adb1f WX |
13867 | }; |
13868 | ||
b030ed2f YM |
13869 | static void bnx2x_shutdown(struct pci_dev *pdev) |
13870 | { | |
13871 | struct net_device *dev = pci_get_drvdata(pdev); | |
13872 | struct bnx2x *bp; | |
13873 | ||
13874 | if (!dev) | |
13875 | return; | |
13876 | ||
13877 | bp = netdev_priv(dev); | |
13878 | if (!bp) | |
13879 | return; | |
13880 | ||
13881 | rtnl_lock(); | |
13882 | netif_device_detach(dev); | |
13883 | rtnl_unlock(); | |
13884 | ||
13885 | /* Don't remove the netdevice, as there are scenarios which will cause | |
13886 | * the kernel to hang, e.g., when trying to remove bnx2i while the | |
13887 | * rootfs is mounted from SAN. | |
13888 | */ | |
13889 | __bnx2x_remove(pdev, dev, bp, false); | |
13890 | } | |
13891 | ||
a2fbb9ea | 13892 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
13893 | .name = DRV_MODULE_NAME, |
13894 | .id_table = bnx2x_pci_tbl, | |
13895 | .probe = bnx2x_init_one, | |
0329aba1 | 13896 | .remove = bnx2x_remove_one, |
493adb1f WX |
13897 | .suspend = bnx2x_suspend, |
13898 | .resume = bnx2x_resume, | |
13899 | .err_handler = &bnx2x_err_handler, | |
3c76feff AE |
13900 | #ifdef CONFIG_BNX2X_SRIOV |
13901 | .sriov_configure = bnx2x_sriov_configure, | |
13902 | #endif | |
b030ed2f | 13903 | .shutdown = bnx2x_shutdown, |
a2fbb9ea ET |
13904 | }; |
13905 | ||
13906 | static int __init bnx2x_init(void) | |
13907 | { | |
dd21ca6d SG |
13908 | int ret; |
13909 | ||
7995c64e | 13910 | pr_info("%s", version); |
938cf541 | 13911 | |
1cf167f2 EG |
13912 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
13913 | if (bnx2x_wq == NULL) { | |
7995c64e | 13914 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
13915 | return -ENOMEM; |
13916 | } | |
370d4a26 YM |
13917 | bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov"); |
13918 | if (!bnx2x_iov_wq) { | |
13919 | pr_err("Cannot create iov workqueue\n"); | |
13920 | destroy_workqueue(bnx2x_wq); | |
13921 | return -ENOMEM; | |
13922 | } | |
1cf167f2 | 13923 | |
dd21ca6d SG |
13924 | ret = pci_register_driver(&bnx2x_pci_driver); |
13925 | if (ret) { | |
7995c64e | 13926 | pr_err("Cannot register driver\n"); |
dd21ca6d | 13927 | destroy_workqueue(bnx2x_wq); |
370d4a26 | 13928 | destroy_workqueue(bnx2x_iov_wq); |
dd21ca6d SG |
13929 | } |
13930 | return ret; | |
a2fbb9ea ET |
13931 | } |
13932 | ||
13933 | static void __exit bnx2x_cleanup(void) | |
13934 | { | |
452427b0 | 13935 | struct list_head *pos, *q; |
d76a6111 | 13936 | |
a2fbb9ea | 13937 | pci_unregister_driver(&bnx2x_pci_driver); |
1cf167f2 EG |
13938 | |
13939 | destroy_workqueue(bnx2x_wq); | |
370d4a26 | 13940 | destroy_workqueue(bnx2x_iov_wq); |
452427b0 | 13941 | |
16a5fd92 | 13942 | /* Free globally allocated resources */ |
452427b0 YM |
13943 | list_for_each_safe(pos, q, &bnx2x_prev_list) { |
13944 | struct bnx2x_prev_path_list *tmp = | |
13945 | list_entry(pos, struct bnx2x_prev_path_list, list); | |
13946 | list_del(pos); | |
13947 | kfree(tmp); | |
13948 | } | |
a2fbb9ea ET |
13949 | } |
13950 | ||
3deb8167 YR |
13951 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
13952 | { | |
13953 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
13954 | } | |
13955 | ||
a2fbb9ea ET |
13956 | module_init(bnx2x_init); |
13957 | module_exit(bnx2x_cleanup); | |
13958 | ||
619c5cb6 VZ |
13959 | /** |
13960 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
13961 | * | |
13962 | * @bp: driver handle | |
13963 | * @set: set or clear the CAM entry | |
13964 | * | |
16a5fd92 | 13965 | * This function will wait until the ramrod completion returns. |
619c5cb6 VZ |
13966 | * Return 0 if success, -ENODEV if ramrod doesn't return. |
13967 | */ | |
1191cb83 | 13968 | static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) |
619c5cb6 VZ |
13969 | { |
13970 | unsigned long ramrod_flags = 0; | |
13971 | ||
13972 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
13973 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
13974 | &bp->iscsi_l2_mac_obj, true, | |
13975 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
13976 | } | |
993ac7b5 MC |
13977 | |
13978 | /* count denotes the number of new completions we have seen */ | |
13979 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
13980 | { | |
13981 | struct eth_spe *spe; | |
a052997e | 13982 | int cxt_index, cxt_offset; |
993ac7b5 MC |
13983 | |
13984 | #ifdef BNX2X_STOP_ON_ERROR | |
13985 | if (unlikely(bp->panic)) | |
13986 | return; | |
13987 | #endif | |
13988 | ||
13989 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 13990 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
13991 | bp->cnic_spq_pending -= count; |
13992 | ||
c2bff63f DK |
13993 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
13994 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
13995 | & SPE_HDR_CONN_TYPE) >> | |
13996 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
13997 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
13998 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
13999 | |
14000 | /* Set validation for iSCSI L2 client before sending SETUP | |
14001 | * ramrod | |
14002 | */ | |
14003 | if (type == ETH_CONNECTION_TYPE) { | |
a052997e | 14004 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { |
37ae41a9 | 14005 | cxt_index = BNX2X_ISCSI_ETH_CID(bp) / |
a052997e | 14006 | ILT_PAGE_CIDS; |
37ae41a9 | 14007 | cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - |
a052997e MS |
14008 | (cxt_index * ILT_PAGE_CIDS); |
14009 | bnx2x_set_ctx_validation(bp, | |
14010 | &bp->context[cxt_index]. | |
14011 | vcxt[cxt_offset].eth, | |
37ae41a9 | 14012 | BNX2X_ISCSI_ETH_CID(bp)); |
a052997e | 14013 | } |
c2bff63f DK |
14014 | } |
14015 | ||
619c5cb6 VZ |
14016 | /* |
14017 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
14018 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
14019 | * COMMON ramrods is not more than the EQ and SPQ can |
14020 | * accommodate. | |
c2bff63f | 14021 | */ |
6e30dd4e VZ |
14022 | if (type == ETH_CONNECTION_TYPE) { |
14023 | if (!atomic_read(&bp->cq_spq_left)) | |
14024 | break; | |
14025 | else | |
14026 | atomic_dec(&bp->cq_spq_left); | |
14027 | } else if (type == NONE_CONNECTION_TYPE) { | |
14028 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
14029 | break; |
14030 | else | |
6e30dd4e | 14031 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
14032 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
14033 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
14034 | if (bp->cnic_spq_pending >= |
14035 | bp->cnic_eth_dev.max_kwqe_pending) | |
14036 | break; | |
14037 | else | |
14038 | bp->cnic_spq_pending++; | |
14039 | } else { | |
14040 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
14041 | bnx2x_panic(); | |
993ac7b5 | 14042 | break; |
c2bff63f | 14043 | } |
993ac7b5 MC |
14044 | |
14045 | spe = bnx2x_sp_get_next(bp); | |
14046 | *spe = *bp->cnic_kwq_cons; | |
14047 | ||
51c1a580 | 14048 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
993ac7b5 MC |
14049 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
14050 | ||
14051 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
14052 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
14053 | else | |
14054 | bp->cnic_kwq_cons++; | |
14055 | } | |
14056 | bnx2x_sp_prod_update(bp); | |
14057 | spin_unlock_bh(&bp->spq_lock); | |
14058 | } | |
14059 | ||
14060 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
14061 | struct kwqe_16 *kwqes[], u32 count) | |
14062 | { | |
14063 | struct bnx2x *bp = netdev_priv(dev); | |
14064 | int i; | |
14065 | ||
14066 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 MS |
14067 | if (unlikely(bp->panic)) { |
14068 | BNX2X_ERR("Can't post to SP queue while panic\n"); | |
993ac7b5 | 14069 | return -EIO; |
51c1a580 | 14070 | } |
993ac7b5 MC |
14071 | #endif |
14072 | ||
95c6c616 AE |
14073 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
14074 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
51c1a580 | 14075 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
95c6c616 AE |
14076 | return -EAGAIN; |
14077 | } | |
14078 | ||
993ac7b5 MC |
14079 | spin_lock_bh(&bp->spq_lock); |
14080 | ||
14081 | for (i = 0; i < count; i++) { | |
14082 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
14083 | ||
14084 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
14085 | break; | |
14086 | ||
14087 | *bp->cnic_kwq_prod = *spe; | |
14088 | ||
14089 | bp->cnic_kwq_pending++; | |
14090 | ||
51c1a580 | 14091 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
993ac7b5 | 14092 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
523224a3 DK |
14093 | spe->data.update_data_addr.hi, |
14094 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
14095 | bp->cnic_kwq_pending); |
14096 | ||
14097 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
14098 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
14099 | else | |
14100 | bp->cnic_kwq_prod++; | |
14101 | } | |
14102 | ||
14103 | spin_unlock_bh(&bp->spq_lock); | |
14104 | ||
14105 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
14106 | bnx2x_cnic_sp_post(bp, 0); | |
14107 | ||
14108 | return i; | |
14109 | } | |
14110 | ||
14111 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
14112 | { | |
14113 | struct cnic_ops *c_ops; | |
14114 | int rc = 0; | |
14115 | ||
14116 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
14117 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
14118 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
14119 | if (c_ops) |
14120 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
14121 | mutex_unlock(&bp->cnic_mutex); | |
14122 | ||
14123 | return rc; | |
14124 | } | |
14125 | ||
14126 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
14127 | { | |
14128 | struct cnic_ops *c_ops; | |
14129 | int rc = 0; | |
14130 | ||
14131 | rcu_read_lock(); | |
14132 | c_ops = rcu_dereference(bp->cnic_ops); | |
14133 | if (c_ops) | |
14134 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
14135 | rcu_read_unlock(); | |
14136 | ||
14137 | return rc; | |
14138 | } | |
14139 | ||
14140 | /* | |
14141 | * for commands that have no data | |
14142 | */ | |
9f6c9258 | 14143 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
14144 | { |
14145 | struct cnic_ctl_info ctl = {0}; | |
14146 | ||
14147 | ctl.cmd = cmd; | |
14148 | ||
14149 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
14150 | } | |
14151 | ||
619c5cb6 | 14152 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 14153 | { |
619c5cb6 | 14154 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
14155 | |
14156 | /* first we tell CNIC and only then we count this as a completion */ | |
14157 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
14158 | ctl.data.comp.cid = cid; | |
619c5cb6 | 14159 | ctl.data.comp.error = err; |
993ac7b5 MC |
14160 | |
14161 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 14162 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
14163 | } |
14164 | ||
619c5cb6 VZ |
14165 | /* Called with netif_addr_lock_bh() taken. |
14166 | * Sets an rx_mode config for an iSCSI ETH client. | |
14167 | * Doesn't block. | |
14168 | * Completion should be checked outside. | |
14169 | */ | |
14170 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
14171 | { | |
14172 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
14173 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
14174 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
14175 | ||
14176 | if (start) { | |
14177 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
14178 | * because it's the only way for UIO Queue to accept | |
14179 | * multicasts (in non-promiscuous mode only one Queue per | |
14180 | * function will receive multicast packets (leading in our | |
14181 | * case). | |
14182 | */ | |
14183 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
14184 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
14185 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
14186 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
14187 | ||
14188 | /* Clear STOP_PENDING bit if START is requested */ | |
14189 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
14190 | ||
14191 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
14192 | } else | |
14193 | /* Clear START_PENDING bit if STOP is requested */ | |
14194 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
14195 | ||
14196 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
14197 | set_bit(sched_state, &bp->sp_state); | |
14198 | else { | |
14199 | __set_bit(RAMROD_RX, &ramrod_flags); | |
14200 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
14201 | ramrod_flags); | |
14202 | } | |
14203 | } | |
14204 | ||
993ac7b5 MC |
14205 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
14206 | { | |
14207 | struct bnx2x *bp = netdev_priv(dev); | |
14208 | int rc = 0; | |
14209 | ||
14210 | switch (ctl->cmd) { | |
14211 | case DRV_CTL_CTXTBL_WR_CMD: { | |
14212 | u32 index = ctl->data.io.offset; | |
14213 | dma_addr_t addr = ctl->data.io.dma_addr; | |
14214 | ||
14215 | bnx2x_ilt_wr(bp, index, addr); | |
14216 | break; | |
14217 | } | |
14218 | ||
c2bff63f DK |
14219 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
14220 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
14221 | |
14222 | bnx2x_cnic_sp_post(bp, count); | |
14223 | break; | |
14224 | } | |
14225 | ||
14226 | /* rtnl_lock is held. */ | |
14227 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
14228 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
14229 | unsigned long sp_bits = 0; | |
14230 | ||
14231 | /* Configure the iSCSI classification object */ | |
14232 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
14233 | cp->iscsi_l2_client_id, | |
14234 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
14235 | bnx2x_sp(bp, mac_rdata), | |
14236 | bnx2x_sp_mapping(bp, mac_rdata), | |
14237 | BNX2X_FILTER_MAC_PENDING, | |
14238 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
14239 | &bp->macs_pool); | |
ec6ba945 | 14240 | |
523224a3 | 14241 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
14242 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
14243 | if (rc) | |
14244 | break; | |
523224a3 DK |
14245 | |
14246 | mmiowb(); | |
14247 | barrier(); | |
14248 | ||
619c5cb6 VZ |
14249 | /* Start accepting on iSCSI L2 ring */ |
14250 | ||
14251 | netif_addr_lock_bh(dev); | |
14252 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
14253 | netif_addr_unlock_bh(dev); | |
14254 | ||
14255 | /* bits to wait on */ | |
14256 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
14257 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
14258 | ||
14259 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
14260 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 14261 | |
993ac7b5 MC |
14262 | break; |
14263 | } | |
14264 | ||
14265 | /* rtnl_lock is held. */ | |
14266 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 14267 | unsigned long sp_bits = 0; |
993ac7b5 | 14268 | |
523224a3 | 14269 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
14270 | netif_addr_lock_bh(dev); |
14271 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
14272 | netif_addr_unlock_bh(dev); | |
14273 | ||
14274 | /* bits to wait on */ | |
14275 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
14276 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
14277 | ||
14278 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
14279 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
14280 | |
14281 | mmiowb(); | |
14282 | barrier(); | |
14283 | ||
14284 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
14285 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
14286 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
14287 | break; |
14288 | } | |
c2bff63f DK |
14289 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
14290 | int count = ctl->data.credit.credit_count; | |
14291 | ||
4e857c58 | 14292 | smp_mb__before_atomic(); |
6e30dd4e | 14293 | atomic_add(count, &bp->cq_spq_left); |
4e857c58 | 14294 | smp_mb__after_atomic(); |
c2bff63f DK |
14295 | break; |
14296 | } | |
1d187b34 | 14297 | case DRV_CTL_ULP_REGISTER_CMD: { |
2e499d3c | 14298 | int ulp_type = ctl->data.register_data.ulp_type; |
1d187b34 BW |
14299 | |
14300 | if (CHIP_IS_E3(bp)) { | |
14301 | int idx = BP_FW_MB_IDX(bp); | |
2e499d3c BW |
14302 | u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); |
14303 | int path = BP_PATH(bp); | |
14304 | int port = BP_PORT(bp); | |
14305 | int i; | |
14306 | u32 scratch_offset; | |
14307 | u32 *host_addr; | |
1d187b34 | 14308 | |
2e499d3c | 14309 | /* first write capability to shmem2 */ |
1d187b34 BW |
14310 | if (ulp_type == CNIC_ULP_ISCSI) |
14311 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
14312 | else if (ulp_type == CNIC_ULP_FCOE) | |
14313 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
14314 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
2e499d3c BW |
14315 | |
14316 | if ((ulp_type != CNIC_ULP_FCOE) || | |
14317 | (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || | |
14318 | (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) | |
14319 | break; | |
14320 | ||
14321 | /* if reached here - should write fcoe capabilities */ | |
14322 | scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); | |
14323 | if (!scratch_offset) | |
14324 | break; | |
14325 | scratch_offset += offsetof(struct glob_ncsi_oem_data, | |
14326 | fcoe_features[path][port]); | |
14327 | host_addr = (u32 *) &(ctl->data.register_data. | |
14328 | fcoe_features); | |
14329 | for (i = 0; i < sizeof(struct fcoe_capabilities); | |
14330 | i += 4) | |
14331 | REG_WR(bp, scratch_offset + i, | |
14332 | *(host_addr + i/4)); | |
1d187b34 | 14333 | } |
42f8277f | 14334 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); |
1d187b34 BW |
14335 | break; |
14336 | } | |
2e499d3c | 14337 | |
1d187b34 BW |
14338 | case DRV_CTL_ULP_UNREGISTER_CMD: { |
14339 | int ulp_type = ctl->data.ulp_type; | |
14340 | ||
14341 | if (CHIP_IS_E3(bp)) { | |
14342 | int idx = BP_FW_MB_IDX(bp); | |
14343 | u32 cap; | |
14344 | ||
14345 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
14346 | if (ulp_type == CNIC_ULP_ISCSI) | |
14347 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
14348 | else if (ulp_type == CNIC_ULP_FCOE) | |
14349 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
14350 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
14351 | } | |
42f8277f | 14352 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); |
1d187b34 BW |
14353 | break; |
14354 | } | |
993ac7b5 MC |
14355 | |
14356 | default: | |
14357 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
14358 | rc = -EINVAL; | |
14359 | } | |
14360 | ||
14361 | return rc; | |
14362 | } | |
14363 | ||
9f6c9258 | 14364 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
14365 | { |
14366 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
14367 | ||
14368 | if (bp->flags & USING_MSIX_FLAG) { | |
14369 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
14370 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
14371 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
14372 | } else { | |
14373 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
14374 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
14375 | } | |
619c5cb6 | 14376 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
14377 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
14378 | else | |
14379 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
14380 | ||
619c5cb6 VZ |
14381 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
14382 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
14383 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
14384 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 14385 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
14386 | |
14387 | cp->num_irq = 2; | |
14388 | } | |
14389 | ||
37ae41a9 MS |
14390 | void bnx2x_setup_cnic_info(struct bnx2x *bp) |
14391 | { | |
14392 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
14393 | ||
37ae41a9 MS |
14394 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
14395 | bnx2x_cid_ilt_lines(bp); | |
14396 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; | |
14397 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); | |
14398 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); | |
14399 | ||
f78afb35 MC |
14400 | DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n", |
14401 | BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid, | |
14402 | cp->iscsi_l2_cid); | |
14403 | ||
37ae41a9 MS |
14404 | if (NO_ISCSI_OOO(bp)) |
14405 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
14406 | } | |
14407 | ||
993ac7b5 MC |
14408 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, |
14409 | void *data) | |
14410 | { | |
14411 | struct bnx2x *bp = netdev_priv(dev); | |
14412 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
55c11941 MS |
14413 | int rc; |
14414 | ||
14415 | DP(NETIF_MSG_IFUP, "Register_cnic called\n"); | |
993ac7b5 | 14416 | |
51c1a580 MS |
14417 | if (ops == NULL) { |
14418 | BNX2X_ERR("NULL ops received\n"); | |
993ac7b5 | 14419 | return -EINVAL; |
51c1a580 | 14420 | } |
993ac7b5 | 14421 | |
55c11941 MS |
14422 | if (!CNIC_SUPPORT(bp)) { |
14423 | BNX2X_ERR("Can't register CNIC when not supported\n"); | |
14424 | return -EOPNOTSUPP; | |
14425 | } | |
14426 | ||
14427 | if (!CNIC_LOADED(bp)) { | |
14428 | rc = bnx2x_load_cnic(bp); | |
14429 | if (rc) { | |
14430 | BNX2X_ERR("CNIC-related load failed\n"); | |
14431 | return rc; | |
14432 | } | |
55c11941 MS |
14433 | } |
14434 | ||
14435 | bp->cnic_enabled = true; | |
14436 | ||
993ac7b5 MC |
14437 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
14438 | if (!bp->cnic_kwq) | |
14439 | return -ENOMEM; | |
14440 | ||
14441 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
14442 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
14443 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
14444 | ||
14445 | bp->cnic_spq_pending = 0; | |
14446 | bp->cnic_kwq_pending = 0; | |
14447 | ||
14448 | bp->cnic_data = data; | |
14449 | ||
14450 | cp->num_irq = 0; | |
619c5cb6 | 14451 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 14452 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 14453 | |
993ac7b5 | 14454 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 14455 | |
993ac7b5 MC |
14456 | rcu_assign_pointer(bp->cnic_ops, ops); |
14457 | ||
42f8277f YM |
14458 | /* Schedule driver to read CNIC driver versions */ |
14459 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); | |
14460 | ||
993ac7b5 MC |
14461 | return 0; |
14462 | } | |
14463 | ||
14464 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
14465 | { | |
14466 | struct bnx2x *bp = netdev_priv(dev); | |
14467 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
14468 | ||
14469 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 | 14470 | cp->drv_state = 0; |
2cfa5a04 | 14471 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
993ac7b5 MC |
14472 | mutex_unlock(&bp->cnic_mutex); |
14473 | synchronize_rcu(); | |
fea75645 | 14474 | bp->cnic_enabled = false; |
993ac7b5 MC |
14475 | kfree(bp->cnic_kwq); |
14476 | bp->cnic_kwq = NULL; | |
14477 | ||
14478 | return 0; | |
14479 | } | |
14480 | ||
a8f47eb7 | 14481 | static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) |
993ac7b5 MC |
14482 | { |
14483 | struct bnx2x *bp = netdev_priv(dev); | |
14484 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
14485 | ||
2ba45142 VZ |
14486 | /* If both iSCSI and FCoE are disabled - return NULL in |
14487 | * order to indicate CNIC that it should not try to work | |
14488 | * with this device. | |
14489 | */ | |
14490 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
14491 | return NULL; | |
14492 | ||
993ac7b5 MC |
14493 | cp->drv_owner = THIS_MODULE; |
14494 | cp->chip_id = CHIP_ID(bp); | |
14495 | cp->pdev = bp->pdev; | |
14496 | cp->io_base = bp->regview; | |
14497 | cp->io_base2 = bp->doorbells; | |
14498 | cp->max_kwqe_pending = 8; | |
523224a3 | 14499 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
14500 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
14501 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 14502 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 14503 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
14504 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
14505 | cp->drv_ctl = bnx2x_drv_ctl; | |
14506 | cp->drv_register_cnic = bnx2x_register_cnic; | |
14507 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
37ae41a9 | 14508 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); |
619c5cb6 VZ |
14509 | cp->iscsi_l2_client_id = |
14510 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
37ae41a9 | 14511 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); |
c2bff63f | 14512 | |
2ba45142 VZ |
14513 | if (NO_ISCSI_OOO(bp)) |
14514 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
14515 | ||
14516 | if (NO_ISCSI(bp)) | |
14517 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
14518 | ||
14519 | if (NO_FCOE(bp)) | |
14520 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
14521 | ||
51c1a580 MS |
14522 | BNX2X_DEV_INFO( |
14523 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", | |
c2bff63f DK |
14524 | cp->ctx_blk_size, |
14525 | cp->ctx_tbl_offset, | |
14526 | cp->ctx_tbl_len, | |
14527 | cp->starting_cid); | |
993ac7b5 MC |
14528 | return cp; |
14529 | } | |
993ac7b5 | 14530 | |
a8f47eb7 | 14531 | static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) |
9b176b6b | 14532 | { |
6411280a AE |
14533 | struct bnx2x *bp = fp->bp; |
14534 | u32 offset = BAR_USTRORM_INTMEM; | |
abc5a021 | 14535 | |
6411280a AE |
14536 | if (IS_VF(bp)) |
14537 | return bnx2x_vf_ustorm_prods_offset(bp, fp); | |
14538 | else if (!CHIP_IS_E1x(bp)) | |
14539 | offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); | |
14540 | else | |
14541 | offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); | |
8d9ac297 | 14542 | |
6411280a | 14543 | return offset; |
8d9ac297 | 14544 | } |
381ac16b | 14545 | |
6411280a AE |
14546 | /* called only on E1H or E2. |
14547 | * When pretending to be PF, the pretend value is the function number 0...7 | |
14548 | * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID | |
14549 | * combination | |
14550 | */ | |
14551 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) | |
381ac16b | 14552 | { |
6411280a | 14553 | u32 pretend_reg; |
381ac16b | 14554 | |
23826850 | 14555 | if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) |
6411280a | 14556 | return -1; |
381ac16b | 14557 | |
6411280a AE |
14558 | /* get my own pretend register */ |
14559 | pretend_reg = bnx2x_get_pretend_reg(bp); | |
14560 | REG_WR(bp, pretend_reg, pretend_func_val); | |
14561 | REG_RD(bp, pretend_reg); | |
381ac16b AE |
14562 | return 0; |
14563 | } | |
eeed018c MK |
14564 | |
14565 | static void bnx2x_ptp_task(struct work_struct *work) | |
14566 | { | |
14567 | struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task); | |
14568 | int port = BP_PORT(bp); | |
14569 | u32 val_seq; | |
14570 | u64 timestamp, ns; | |
14571 | struct skb_shared_hwtstamps shhwtstamps; | |
14572 | ||
14573 | /* Read Tx timestamp registers */ | |
14574 | val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : | |
14575 | NIG_REG_P0_TLLH_PTP_BUF_SEQID); | |
14576 | if (val_seq & 0x10000) { | |
14577 | /* There is a valid timestamp value */ | |
14578 | timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB : | |
14579 | NIG_REG_P0_TLLH_PTP_BUF_TS_MSB); | |
14580 | timestamp <<= 32; | |
14581 | timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB : | |
14582 | NIG_REG_P0_TLLH_PTP_BUF_TS_LSB); | |
14583 | /* Reset timestamp register to allow new timestamp */ | |
14584 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : | |
14585 | NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); | |
14586 | ns = timecounter_cyc2time(&bp->timecounter, timestamp); | |
14587 | ||
14588 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
14589 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
14590 | skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps); | |
14591 | dev_kfree_skb_any(bp->ptp_tx_skb); | |
14592 | bp->ptp_tx_skb = NULL; | |
14593 | ||
14594 | DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n", | |
14595 | timestamp, ns); | |
14596 | } else { | |
14597 | DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n"); | |
14598 | /* Reschedule to keep checking for a valid timestamp value */ | |
14599 | schedule_work(&bp->ptp_task); | |
14600 | } | |
14601 | } | |
14602 | ||
14603 | void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb) | |
14604 | { | |
14605 | int port = BP_PORT(bp); | |
14606 | u64 timestamp, ns; | |
14607 | ||
14608 | timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB : | |
14609 | NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB); | |
14610 | timestamp <<= 32; | |
14611 | timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB : | |
14612 | NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB); | |
14613 | ||
14614 | /* Reset timestamp register to allow new timestamp */ | |
14615 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : | |
14616 | NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); | |
14617 | ||
14618 | ns = timecounter_cyc2time(&bp->timecounter, timestamp); | |
14619 | ||
14620 | skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); | |
14621 | ||
14622 | DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n", | |
14623 | timestamp, ns); | |
14624 | } | |
14625 | ||
14626 | /* Read the PHC */ | |
14627 | static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc) | |
14628 | { | |
14629 | struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter); | |
14630 | int port = BP_PORT(bp); | |
14631 | u32 wb_data[2]; | |
14632 | u64 phc_cycles; | |
14633 | ||
14634 | REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 : | |
14635 | NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2); | |
14636 | phc_cycles = wb_data[1]; | |
14637 | phc_cycles = (phc_cycles << 32) + wb_data[0]; | |
14638 | ||
14639 | DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles); | |
14640 | ||
14641 | return phc_cycles; | |
14642 | } | |
14643 | ||
14644 | static void bnx2x_init_cyclecounter(struct bnx2x *bp) | |
14645 | { | |
14646 | memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter)); | |
14647 | bp->cyclecounter.read = bnx2x_cyclecounter_read; | |
f28ba401 | 14648 | bp->cyclecounter.mask = CYCLECOUNTER_MASK(64); |
eeed018c MK |
14649 | bp->cyclecounter.shift = 1; |
14650 | bp->cyclecounter.mult = 1; | |
14651 | } | |
14652 | ||
14653 | static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp) | |
14654 | { | |
14655 | struct bnx2x_func_state_params func_params = {NULL}; | |
14656 | struct bnx2x_func_set_timesync_params *set_timesync_params = | |
14657 | &func_params.params.set_timesync; | |
14658 | ||
14659 | /* Prepare parameters for function state transitions */ | |
14660 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
14661 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
14662 | ||
14663 | func_params.f_obj = &bp->func_obj; | |
14664 | func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; | |
14665 | ||
14666 | /* Function parameters */ | |
14667 | set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET; | |
14668 | set_timesync_params->offset_cmd = TS_OFFSET_KEEP; | |
14669 | ||
14670 | return bnx2x_func_state_change(bp, &func_params); | |
14671 | } | |
14672 | ||
1444c301 | 14673 | static int bnx2x_enable_ptp_packets(struct bnx2x *bp) |
eeed018c MK |
14674 | { |
14675 | struct bnx2x_queue_state_params q_params; | |
14676 | int rc, i; | |
14677 | ||
14678 | /* send queue update ramrod to enable PTP packets */ | |
14679 | memset(&q_params, 0, sizeof(q_params)); | |
14680 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
14681 | q_params.cmd = BNX2X_Q_CMD_UPDATE; | |
14682 | __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, | |
14683 | &q_params.params.update.update_flags); | |
14684 | __set_bit(BNX2X_Q_UPDATE_PTP_PKTS, | |
14685 | &q_params.params.update.update_flags); | |
14686 | ||
14687 | /* send the ramrod on all the queues of the PF */ | |
14688 | for_each_eth_queue(bp, i) { | |
14689 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
14690 | ||
14691 | /* Set the appropriate Queue object */ | |
14692 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; | |
14693 | ||
14694 | /* Update the Queue state */ | |
14695 | rc = bnx2x_queue_state_change(bp, &q_params); | |
14696 | if (rc) { | |
14697 | BNX2X_ERR("Failed to enable PTP packets\n"); | |
14698 | return rc; | |
14699 | } | |
14700 | } | |
14701 | ||
14702 | return 0; | |
14703 | } | |
14704 | ||
14705 | int bnx2x_configure_ptp_filters(struct bnx2x *bp) | |
14706 | { | |
14707 | int port = BP_PORT(bp); | |
14708 | int rc; | |
14709 | ||
14710 | if (!bp->hwtstamp_ioctl_called) | |
14711 | return 0; | |
14712 | ||
14713 | switch (bp->tx_type) { | |
14714 | case HWTSTAMP_TX_ON: | |
14715 | bp->flags |= TX_TIMESTAMPING_EN; | |
14716 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : | |
14717 | NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA); | |
14718 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : | |
14719 | NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE); | |
14720 | break; | |
14721 | case HWTSTAMP_TX_ONESTEP_SYNC: | |
14722 | BNX2X_ERR("One-step timestamping is not supported\n"); | |
14723 | return -ERANGE; | |
14724 | } | |
14725 | ||
14726 | switch (bp->rx_filter) { | |
14727 | case HWTSTAMP_FILTER_NONE: | |
14728 | break; | |
14729 | case HWTSTAMP_FILTER_ALL: | |
14730 | case HWTSTAMP_FILTER_SOME: | |
14731 | bp->rx_filter = HWTSTAMP_FILTER_NONE; | |
14732 | break; | |
14733 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
14734 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
14735 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
14736 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
14737 | /* Initialize PTP detection for UDP/IPv4 events */ | |
14738 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
14739 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE); | |
14740 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
14741 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE); | |
14742 | break; | |
14743 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
14744 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
14745 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
14746 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; | |
14747 | /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */ | |
14748 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
14749 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA); | |
14750 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
14751 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE); | |
14752 | break; | |
14753 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
14754 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
14755 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
14756 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; | |
14757 | /* Initialize PTP detection L2 events */ | |
14758 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
14759 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF); | |
14760 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
14761 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF); | |
14762 | ||
14763 | break; | |
14764 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
14765 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
14766 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
14767 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
14768 | /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */ | |
14769 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
14770 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA); | |
14771 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
14772 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE); | |
14773 | break; | |
14774 | } | |
14775 | ||
14776 | /* Indicate to FW that this PF expects recorded PTP packets */ | |
14777 | rc = bnx2x_enable_ptp_packets(bp); | |
14778 | if (rc) | |
14779 | return rc; | |
14780 | ||
14781 | /* Enable sending PTP packets to host */ | |
14782 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : | |
14783 | NIG_REG_P0_LLH_PTP_TO_HOST, 0x1); | |
14784 | ||
14785 | return 0; | |
14786 | } | |
14787 | ||
14788 | static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr) | |
14789 | { | |
14790 | struct hwtstamp_config config; | |
14791 | int rc; | |
14792 | ||
14793 | DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n"); | |
14794 | ||
14795 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
14796 | return -EFAULT; | |
14797 | ||
14798 | DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n", | |
14799 | config.tx_type, config.rx_filter); | |
14800 | ||
14801 | if (config.flags) { | |
14802 | BNX2X_ERR("config.flags is reserved for future use\n"); | |
14803 | return -EINVAL; | |
14804 | } | |
14805 | ||
14806 | bp->hwtstamp_ioctl_called = 1; | |
14807 | bp->tx_type = config.tx_type; | |
14808 | bp->rx_filter = config.rx_filter; | |
14809 | ||
14810 | rc = bnx2x_configure_ptp_filters(bp); | |
14811 | if (rc) | |
14812 | return rc; | |
14813 | ||
14814 | config.rx_filter = bp->rx_filter; | |
14815 | ||
14816 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
14817 | -EFAULT : 0; | |
14818 | } | |
14819 | ||
bf27c353 | 14820 | /* Configures HW for PTP */ |
eeed018c MK |
14821 | static int bnx2x_configure_ptp(struct bnx2x *bp) |
14822 | { | |
14823 | int rc, port = BP_PORT(bp); | |
14824 | u32 wb_data[2]; | |
14825 | ||
14826 | /* Reset PTP event detection rules - will be configured in the IOCTL */ | |
14827 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
14828 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); | |
14829 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
14830 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); | |
14831 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : | |
14832 | NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); | |
14833 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : | |
14834 | NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); | |
14835 | ||
14836 | /* Disable PTP packets to host - will be configured in the IOCTL*/ | |
14837 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : | |
14838 | NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); | |
14839 | ||
14840 | /* Enable the PTP feature */ | |
14841 | REG_WR(bp, port ? NIG_REG_P1_PTP_EN : | |
14842 | NIG_REG_P0_PTP_EN, 0x3F); | |
14843 | ||
14844 | /* Enable the free-running counter */ | |
14845 | wb_data[0] = 0; | |
14846 | wb_data[1] = 0; | |
14847 | REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2); | |
14848 | ||
14849 | /* Reset drift register (offset register is not reset) */ | |
14850 | rc = bnx2x_send_reset_timesync_ramrod(bp); | |
14851 | if (rc) { | |
14852 | BNX2X_ERR("Failed to reset PHC drift register\n"); | |
14853 | return -EFAULT; | |
14854 | } | |
14855 | ||
14856 | /* Reset possibly old timestamps */ | |
14857 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : | |
14858 | NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); | |
14859 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : | |
14860 | NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); | |
14861 | ||
14862 | return 0; | |
14863 | } | |
14864 | ||
14865 | /* Called during load, to initialize PTP-related stuff */ | |
14866 | void bnx2x_init_ptp(struct bnx2x *bp) | |
14867 | { | |
14868 | int rc; | |
14869 | ||
14870 | /* Configure PTP in HW */ | |
14871 | rc = bnx2x_configure_ptp(bp); | |
14872 | if (rc) { | |
14873 | BNX2X_ERR("Stopping PTP initialization\n"); | |
14874 | return; | |
14875 | } | |
14876 | ||
14877 | /* Init work queue for Tx timestamping */ | |
14878 | INIT_WORK(&bp->ptp_task, bnx2x_ptp_task); | |
14879 | ||
14880 | /* Init cyclecounter and timecounter. This is done only in the first | |
14881 | * load. If done in every load, PTP application will fail when doing | |
14882 | * unload / load (e.g. MTU change) while it is running. | |
14883 | */ | |
14884 | if (!bp->timecounter_init_done) { | |
14885 | bnx2x_init_cyclecounter(bp); | |
14886 | timecounter_init(&bp->timecounter, &bp->cyclecounter, | |
14887 | ktime_to_ns(ktime_get_real())); | |
14888 | bp->timecounter_init_done = 1; | |
14889 | } | |
14890 | ||
14891 | DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n"); | |
14892 | } |