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Commit | Line | Data |
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34f80b04 | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
a2fbb9ea | 2 | * |
5de92408 | 3 | * Copyright (c) 2007-2011 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 14 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
15 | * |
16 | */ | |
17 | ||
f1deab50 JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
a2fbb9ea ET |
20 | #include <linux/module.h> |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/device.h> /* for dev_info() */ | |
24 | #include <linux/timer.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/slab.h> | |
a2fbb9ea ET |
28 | #include <linux/interrupt.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/bitops.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/byteorder.h> | |
39 | #include <linux/time.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/mii.h> | |
01789349 | 42 | #include <linux/if.h> |
0c6671b0 | 43 | #include <linux/if_vlan.h> |
a2fbb9ea | 44 | #include <net/ip.h> |
619c5cb6 | 45 | #include <net/ipv6.h> |
a2fbb9ea ET |
46 | #include <net/tcp.h> |
47 | #include <net/checksum.h> | |
34f80b04 | 48 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
49 | #include <linux/workqueue.h> |
50 | #include <linux/crc32.h> | |
34f80b04 | 51 | #include <linux/crc32c.h> |
a2fbb9ea ET |
52 | #include <linux/prefetch.h> |
53 | #include <linux/zlib.h> | |
a2fbb9ea | 54 | #include <linux/io.h> |
45229b42 | 55 | #include <linux/stringify.h> |
7ab24bfd | 56 | #include <linux/vmalloc.h> |
a2fbb9ea | 57 | |
a2fbb9ea ET |
58 | #include "bnx2x.h" |
59 | #include "bnx2x_init.h" | |
94a78b79 | 60 | #include "bnx2x_init_ops.h" |
9f6c9258 | 61 | #include "bnx2x_cmn.h" |
e4901dde | 62 | #include "bnx2x_dcb.h" |
042181f5 | 63 | #include "bnx2x_sp.h" |
a2fbb9ea | 64 | |
94a78b79 VZ |
65 | #include <linux/firmware.h> |
66 | #include "bnx2x_fw_file_hdr.h" | |
67 | /* FW files */ | |
45229b42 BH |
68 | #define FW_FILE_VERSION \ |
69 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
70 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
71 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
72 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
73 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
74 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 75 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 76 | |
34f80b04 EG |
77 | /* Time in jiffies before concluding the transmitter is hung */ |
78 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 79 | |
53a10565 | 80 | static char version[] __devinitdata = |
619c5cb6 | 81 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
82 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
83 | ||
24e3fcef | 84 | MODULE_AUTHOR("Eliezer Tamir"); |
f2e0899f | 85 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
619c5cb6 VZ |
86 | "BCM57710/57711/57711E/" |
87 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
88 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
89 | MODULE_LICENSE("GPL"); |
90 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
91 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
92 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 93 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 94 | |
555f6c78 EG |
95 | static int multi_mode = 1; |
96 | module_param(multi_mode, int, 0); | |
ca00392c EG |
97 | MODULE_PARM_DESC(multi_mode, " Multi queue mode " |
98 | "(0 Disable; 1 Enable (default))"); | |
99 | ||
d6214d7a | 100 | int num_queues; |
54b9ddaa VZ |
101 | module_param(num_queues, int, 0); |
102 | MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" | |
103 | " (default is as a number of CPUs)"); | |
555f6c78 | 104 | |
19680c48 | 105 | static int disable_tpa; |
19680c48 | 106 | module_param(disable_tpa, int, 0); |
9898f86d | 107 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 108 | |
9ee3d37b DK |
109 | #define INT_MODE_INTx 1 |
110 | #define INT_MODE_MSI 2 | |
8badd27a EG |
111 | static int int_mode; |
112 | module_param(int_mode, int, 0); | |
619c5cb6 | 113 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 114 | "(1 INT#x; 2 MSI)"); |
8badd27a | 115 | |
a18f5128 EG |
116 | static int dropless_fc; |
117 | module_param(dropless_fc, int, 0); | |
118 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); | |
119 | ||
9898f86d | 120 | static int poll; |
a2fbb9ea | 121 | module_param(poll, int, 0); |
9898f86d | 122 | MODULE_PARM_DESC(poll, " Use polling (for debug)"); |
8d5726c4 EG |
123 | |
124 | static int mrrs = -1; | |
125 | module_param(mrrs, int, 0); | |
126 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); | |
127 | ||
9898f86d | 128 | static int debug; |
a2fbb9ea | 129 | module_param(debug, int, 0); |
9898f86d EG |
130 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
131 | ||
a2fbb9ea | 132 | |
619c5cb6 VZ |
133 | |
134 | struct workqueue_struct *bnx2x_wq; | |
ec6ba945 | 135 | |
a2fbb9ea ET |
136 | enum bnx2x_board_type { |
137 | BCM57710 = 0, | |
619c5cb6 VZ |
138 | BCM57711, |
139 | BCM57711E, | |
140 | BCM57712, | |
141 | BCM57712_MF, | |
142 | BCM57800, | |
143 | BCM57800_MF, | |
144 | BCM57810, | |
145 | BCM57810_MF, | |
146 | BCM57840, | |
147 | BCM57840_MF | |
a2fbb9ea ET |
148 | }; |
149 | ||
34f80b04 | 150 | /* indexed by board_type, above */ |
53a10565 | 151 | static struct { |
a2fbb9ea ET |
152 | char *name; |
153 | } board_info[] __devinitdata = { | |
619c5cb6 VZ |
154 | { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
155 | { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, | |
156 | { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, | |
157 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, | |
158 | { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, | |
159 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, | |
160 | { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, | |
161 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, | |
162 | { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, | |
163 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, | |
164 | { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " | |
165 | "Ethernet Multi Function"} | |
a2fbb9ea ET |
166 | }; |
167 | ||
619c5cb6 VZ |
168 | #ifndef PCI_DEVICE_ID_NX2_57710 |
169 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
170 | #endif | |
171 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
172 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
173 | #endif | |
174 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
175 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
176 | #endif | |
177 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
178 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
179 | #endif | |
180 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
181 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
182 | #endif | |
183 | #ifndef PCI_DEVICE_ID_NX2_57800 | |
184 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
185 | #endif | |
186 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
187 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
188 | #endif | |
189 | #ifndef PCI_DEVICE_ID_NX2_57810 | |
190 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
191 | #endif | |
192 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
193 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
194 | #endif | |
195 | #ifndef PCI_DEVICE_ID_NX2_57840 | |
196 | #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 | |
197 | #endif | |
198 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
199 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
200 | #endif | |
a3aa1884 | 201 | static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { |
e4ed7113 EG |
202 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
203 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
204 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 205 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 VZ |
206 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
207 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, | |
208 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
209 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, | |
210 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
211 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, | |
212 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, | |
a2fbb9ea ET |
213 | { 0 } |
214 | }; | |
215 | ||
216 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
217 | ||
218 | /**************************************************************************** | |
219 | * General service functions | |
220 | ****************************************************************************/ | |
221 | ||
619c5cb6 VZ |
222 | static inline void __storm_memset_dma_mapping(struct bnx2x *bp, |
223 | u32 addr, dma_addr_t mapping) | |
224 | { | |
225 | REG_WR(bp, addr, U64_LO(mapping)); | |
226 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
227 | } | |
228 | ||
229 | static inline void storm_memset_spq_addr(struct bnx2x *bp, | |
230 | dma_addr_t mapping, u16 abs_fid) | |
231 | { | |
232 | u32 addr = XSEM_REG_FAST_MEMORY + | |
233 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
234 | ||
235 | __storm_memset_dma_mapping(bp, addr, mapping); | |
236 | } | |
237 | ||
238 | static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, | |
239 | u16 pf_id) | |
523224a3 | 240 | { |
619c5cb6 VZ |
241 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
242 | pf_id); | |
243 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
244 | pf_id); | |
245 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
246 | pf_id); | |
247 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
248 | pf_id); | |
523224a3 DK |
249 | } |
250 | ||
619c5cb6 VZ |
251 | static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
252 | u8 enable) | |
253 | { | |
254 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
255 | enable); | |
256 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
257 | enable); | |
258 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
259 | enable); | |
260 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
261 | enable); | |
262 | } | |
523224a3 DK |
263 | |
264 | static inline void storm_memset_eq_data(struct bnx2x *bp, | |
265 | struct event_ring_data *eq_data, | |
266 | u16 pfid) | |
267 | { | |
268 | size_t size = sizeof(struct event_ring_data); | |
269 | ||
270 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
271 | ||
272 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
273 | } | |
274 | ||
275 | static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, | |
276 | u16 pfid) | |
277 | { | |
278 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
279 | REG_WR16(bp, addr, eq_prod); | |
280 | } | |
281 | ||
a2fbb9ea ET |
282 | /* used only at init |
283 | * locking is done by mcp | |
284 | */ | |
8d96286a | 285 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
286 | { |
287 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
288 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
289 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
290 | PCICFG_VENDOR_ID_OFFSET); | |
291 | } | |
292 | ||
a2fbb9ea ET |
293 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
294 | { | |
295 | u32 val; | |
296 | ||
297 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
298 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
299 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
300 | PCICFG_VENDOR_ID_OFFSET); | |
301 | ||
302 | return val; | |
303 | } | |
a2fbb9ea | 304 | |
f2e0899f DK |
305 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
306 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
307 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
308 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
309 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
310 | ||
8d96286a | 311 | static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, |
312 | int msglvl) | |
f2e0899f DK |
313 | { |
314 | u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; | |
315 | ||
316 | switch (dmae->opcode & DMAE_COMMAND_DST) { | |
317 | case DMAE_CMD_DST_PCI: | |
318 | if (src_type == DMAE_CMD_SRC_PCI) | |
319 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
320 | "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" | |
321 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
322 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
323 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
324 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
325 | dmae->comp_val); | |
326 | else | |
327 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
328 | "src [%08x], len [%d*4], dst [%x:%08x]\n" | |
329 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
330 | dmae->opcode, dmae->src_addr_lo >> 2, | |
331 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
332 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
333 | dmae->comp_val); | |
334 | break; | |
335 | case DMAE_CMD_DST_GRC: | |
336 | if (src_type == DMAE_CMD_SRC_PCI) | |
337 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
338 | "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" | |
339 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
340 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
341 | dmae->len, dmae->dst_addr_lo >> 2, | |
342 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
343 | dmae->comp_val); | |
344 | else | |
345 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
346 | "src [%08x], len [%d*4], dst [%08x]\n" | |
347 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
348 | dmae->opcode, dmae->src_addr_lo >> 2, | |
349 | dmae->len, dmae->dst_addr_lo >> 2, | |
350 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
351 | dmae->comp_val); | |
352 | break; | |
353 | default: | |
354 | if (src_type == DMAE_CMD_SRC_PCI) | |
355 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
f1deab50 JP |
356 | "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" |
357 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
f2e0899f DK |
358 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, |
359 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
360 | dmae->comp_val); | |
361 | else | |
362 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
f1deab50 JP |
363 | "src_addr [%08x] len [%d * 4] dst_addr [none]\n" |
364 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
f2e0899f DK |
365 | dmae->opcode, dmae->src_addr_lo >> 2, |
366 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
367 | dmae->comp_val); | |
368 | break; | |
369 | } | |
370 | ||
371 | } | |
372 | ||
a2fbb9ea | 373 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 374 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
375 | { |
376 | u32 cmd_offset; | |
377 | int i; | |
378 | ||
379 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
380 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
381 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
382 | ||
ad8d3948 EG |
383 | DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", |
384 | idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
385 | } |
386 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
387 | } | |
388 | ||
f2e0899f | 389 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 390 | { |
f2e0899f DK |
391 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
392 | DMAE_CMD_C_ENABLE); | |
393 | } | |
ad8d3948 | 394 | |
f2e0899f DK |
395 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
396 | { | |
397 | return opcode & ~DMAE_CMD_SRC_RESET; | |
398 | } | |
ad8d3948 | 399 | |
f2e0899f DK |
400 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
401 | bool with_comp, u8 comp_type) | |
402 | { | |
403 | u32 opcode = 0; | |
404 | ||
405 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
406 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 407 | |
f2e0899f DK |
408 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
409 | ||
410 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
411 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
412 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 413 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 414 | |
a2fbb9ea | 415 | #ifdef __BIG_ENDIAN |
f2e0899f | 416 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 417 | #else |
f2e0899f | 418 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 419 | #endif |
f2e0899f DK |
420 | if (with_comp) |
421 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
422 | return opcode; | |
423 | } | |
424 | ||
8d96286a | 425 | static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
426 | struct dmae_command *dmae, | |
427 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
428 | { |
429 | memset(dmae, 0, sizeof(struct dmae_command)); | |
430 | ||
431 | /* set the opcode */ | |
432 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
433 | true, DMAE_COMP_PCI); | |
434 | ||
435 | /* fill in the completion parameters */ | |
436 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
437 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
438 | dmae->comp_val = DMAE_COMP_VAL; | |
439 | } | |
440 | ||
441 | /* issue a dmae command over the init-channel and wailt for completion */ | |
8d96286a | 442 | static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, |
443 | struct dmae_command *dmae) | |
f2e0899f DK |
444 | { |
445 | u32 *wb_comp = bnx2x_sp(bp, wb_comp); | |
5e374b5a | 446 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
447 | int rc = 0; |
448 | ||
449 | DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", | |
a2fbb9ea ET |
450 | bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], |
451 | bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); | |
a2fbb9ea | 452 | |
619c5cb6 VZ |
453 | /* |
454 | * Lock the dmae channel. Disable BHs to prevent a dead-lock | |
455 | * as long as this code is called both from syscall context and | |
456 | * from ndo_set_rx_mode() flow that may be called from BH. | |
457 | */ | |
6e30dd4e | 458 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 459 | |
f2e0899f | 460 | /* reset completion */ |
a2fbb9ea ET |
461 | *wb_comp = 0; |
462 | ||
f2e0899f DK |
463 | /* post the command on the channel used for initializations */ |
464 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 465 | |
f2e0899f | 466 | /* wait for completion */ |
a2fbb9ea | 467 | udelay(5); |
f2e0899f | 468 | while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 EG |
469 | DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); |
470 | ||
ad8d3948 | 471 | if (!cnt) { |
c3eefaf6 | 472 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
473 | rc = DMAE_TIMEOUT; |
474 | goto unlock; | |
a2fbb9ea | 475 | } |
ad8d3948 | 476 | cnt--; |
f2e0899f | 477 | udelay(50); |
a2fbb9ea | 478 | } |
f2e0899f DK |
479 | if (*wb_comp & DMAE_PCI_ERR_FLAG) { |
480 | BNX2X_ERR("DMAE PCI error!\n"); | |
481 | rc = DMAE_PCI_ERROR; | |
482 | } | |
483 | ||
484 | DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", | |
485 | bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], | |
486 | bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); | |
ad8d3948 | 487 | |
f2e0899f | 488 | unlock: |
6e30dd4e | 489 | spin_unlock_bh(&bp->dmae_lock); |
f2e0899f DK |
490 | return rc; |
491 | } | |
492 | ||
493 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
494 | u32 len32) | |
495 | { | |
496 | struct dmae_command dmae; | |
497 | ||
498 | if (!bp->dmae_ready) { | |
499 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
500 | ||
501 | DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)" | |
502 | " using indirect\n", dst_addr, len32); | |
503 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
504 | return; | |
505 | } | |
506 | ||
507 | /* set opcode and fixed command fields */ | |
508 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
509 | ||
510 | /* fill in addresses and len */ | |
511 | dmae.src_addr_lo = U64_LO(dma_addr); | |
512 | dmae.src_addr_hi = U64_HI(dma_addr); | |
513 | dmae.dst_addr_lo = dst_addr >> 2; | |
514 | dmae.dst_addr_hi = 0; | |
515 | dmae.len = len32; | |
516 | ||
517 | bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); | |
518 | ||
519 | /* issue the command and wait for completion */ | |
520 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
a2fbb9ea ET |
521 | } |
522 | ||
c18487ee | 523 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 524 | { |
5ff7b6d4 | 525 | struct dmae_command dmae; |
ad8d3948 EG |
526 | |
527 | if (!bp->dmae_ready) { | |
528 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
529 | int i; | |
530 | ||
531 | DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)" | |
532 | " using indirect\n", src_addr, len32); | |
533 | for (i = 0; i < len32; i++) | |
534 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
535 | return; | |
536 | } | |
537 | ||
f2e0899f DK |
538 | /* set opcode and fixed command fields */ |
539 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 540 | |
f2e0899f | 541 | /* fill in addresses and len */ |
5ff7b6d4 EG |
542 | dmae.src_addr_lo = src_addr >> 2; |
543 | dmae.src_addr_hi = 0; | |
544 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
545 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
546 | dmae.len = len32; | |
ad8d3948 | 547 | |
f2e0899f | 548 | bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); |
ad8d3948 | 549 | |
f2e0899f DK |
550 | /* issue the command and wait for completion */ |
551 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
ad8d3948 EG |
552 | } |
553 | ||
8d96286a | 554 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
555 | u32 addr, u32 len) | |
573f2035 | 556 | { |
02e3c6cb | 557 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
558 | int offset = 0; |
559 | ||
02e3c6cb | 560 | while (len > dmae_wr_max) { |
573f2035 | 561 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
562 | addr + offset, dmae_wr_max); |
563 | offset += dmae_wr_max * 4; | |
564 | len -= dmae_wr_max; | |
573f2035 EG |
565 | } |
566 | ||
567 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
568 | } | |
569 | ||
ad8d3948 EG |
570 | /* used only for slowpath so not inlined */ |
571 | static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) | |
572 | { | |
573 | u32 wb_write[2]; | |
574 | ||
575 | wb_write[0] = val_hi; | |
576 | wb_write[1] = val_lo; | |
577 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
a2fbb9ea | 578 | } |
a2fbb9ea | 579 | |
ad8d3948 EG |
580 | #ifdef USE_WB_RD |
581 | static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) | |
582 | { | |
583 | u32 wb_data[2]; | |
584 | ||
585 | REG_RD_DMAE(bp, reg, wb_data, 2); | |
586 | ||
587 | return HILO_U64(wb_data[0], wb_data[1]); | |
588 | } | |
589 | #endif | |
590 | ||
a2fbb9ea ET |
591 | static int bnx2x_mc_assert(struct bnx2x *bp) |
592 | { | |
a2fbb9ea | 593 | char last_idx; |
34f80b04 EG |
594 | int i, rc = 0; |
595 | u32 row0, row1, row2, row3; | |
596 | ||
597 | /* XSTORM */ | |
598 | last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + | |
599 | XSTORM_ASSERT_LIST_INDEX_OFFSET); | |
600 | if (last_idx) | |
601 | BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
602 | ||
603 | /* print the asserts */ | |
604 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
605 | ||
606 | row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
607 | XSTORM_ASSERT_LIST_OFFSET(i)); | |
608 | row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
609 | XSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
610 | row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
611 | XSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
612 | row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
613 | XSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
614 | ||
615 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
616 | BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" | |
617 | " 0x%08x 0x%08x 0x%08x\n", | |
618 | i, row3, row2, row1, row0); | |
619 | rc++; | |
620 | } else { | |
621 | break; | |
622 | } | |
623 | } | |
624 | ||
625 | /* TSTORM */ | |
626 | last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + | |
627 | TSTORM_ASSERT_LIST_INDEX_OFFSET); | |
628 | if (last_idx) | |
629 | BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
630 | ||
631 | /* print the asserts */ | |
632 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
633 | ||
634 | row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
635 | TSTORM_ASSERT_LIST_OFFSET(i)); | |
636 | row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
637 | TSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
638 | row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
639 | TSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
640 | row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
641 | TSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
642 | ||
643 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
644 | BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" | |
645 | " 0x%08x 0x%08x 0x%08x\n", | |
646 | i, row3, row2, row1, row0); | |
647 | rc++; | |
648 | } else { | |
649 | break; | |
650 | } | |
651 | } | |
652 | ||
653 | /* CSTORM */ | |
654 | last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + | |
655 | CSTORM_ASSERT_LIST_INDEX_OFFSET); | |
656 | if (last_idx) | |
657 | BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
658 | ||
659 | /* print the asserts */ | |
660 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
661 | ||
662 | row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
663 | CSTORM_ASSERT_LIST_OFFSET(i)); | |
664 | row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
665 | CSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
666 | row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
667 | CSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
668 | row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
669 | CSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
670 | ||
671 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
672 | BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" | |
673 | " 0x%08x 0x%08x 0x%08x\n", | |
674 | i, row3, row2, row1, row0); | |
675 | rc++; | |
676 | } else { | |
677 | break; | |
678 | } | |
679 | } | |
680 | ||
681 | /* USTORM */ | |
682 | last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + | |
683 | USTORM_ASSERT_LIST_INDEX_OFFSET); | |
684 | if (last_idx) | |
685 | BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
686 | ||
687 | /* print the asserts */ | |
688 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
689 | ||
690 | row0 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
691 | USTORM_ASSERT_LIST_OFFSET(i)); | |
692 | row1 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
693 | USTORM_ASSERT_LIST_OFFSET(i) + 4); | |
694 | row2 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
695 | USTORM_ASSERT_LIST_OFFSET(i) + 8); | |
696 | row3 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
697 | USTORM_ASSERT_LIST_OFFSET(i) + 12); | |
698 | ||
699 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
700 | BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" | |
701 | " 0x%08x 0x%08x 0x%08x\n", | |
702 | i, row3, row2, row1, row0); | |
703 | rc++; | |
704 | } else { | |
705 | break; | |
a2fbb9ea ET |
706 | } |
707 | } | |
34f80b04 | 708 | |
a2fbb9ea ET |
709 | return rc; |
710 | } | |
c14423fe | 711 | |
7a25cc73 | 712 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 713 | { |
7a25cc73 | 714 | u32 addr, val; |
a2fbb9ea | 715 | u32 mark, offset; |
4781bfad | 716 | __be32 data[9]; |
a2fbb9ea | 717 | int word; |
f2e0899f | 718 | u32 trace_shmem_base; |
2145a920 VZ |
719 | if (BP_NOMCP(bp)) { |
720 | BNX2X_ERR("NO MCP - can not dump\n"); | |
721 | return; | |
722 | } | |
7a25cc73 DK |
723 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
724 | (bp->common.bc_ver & 0xff0000) >> 16, | |
725 | (bp->common.bc_ver & 0xff00) >> 8, | |
726 | (bp->common.bc_ver & 0xff)); | |
727 | ||
728 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
729 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
730 | printk("%s" "MCP PC at 0x%x\n", lvl, val); | |
cdaa7cb8 | 731 | |
f2e0899f DK |
732 | if (BP_PATH(bp) == 0) |
733 | trace_shmem_base = bp->common.shmem_base; | |
734 | else | |
735 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
736 | addr = trace_shmem_base - 0x0800 + 4; | |
cdaa7cb8 | 737 | mark = REG_RD(bp, addr); |
f2e0899f DK |
738 | mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) |
739 | + ((mark + 0x3) & ~0x3) - 0x08000000; | |
7a25cc73 | 740 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 741 | |
7a25cc73 | 742 | printk("%s", lvl); |
f2e0899f | 743 | for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 744 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 745 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 746 | data[8] = 0x0; |
7995c64e | 747 | pr_cont("%s", (char *)data); |
a2fbb9ea | 748 | } |
cdaa7cb8 | 749 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 750 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 751 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 752 | data[8] = 0x0; |
7995c64e | 753 | pr_cont("%s", (char *)data); |
a2fbb9ea | 754 | } |
7a25cc73 DK |
755 | printk("%s" "end of fw dump\n", lvl); |
756 | } | |
757 | ||
758 | static inline void bnx2x_fw_dump(struct bnx2x *bp) | |
759 | { | |
760 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
761 | } |
762 | ||
6c719d00 | 763 | void bnx2x_panic_dump(struct bnx2x *bp) |
a2fbb9ea ET |
764 | { |
765 | int i; | |
523224a3 DK |
766 | u16 j; |
767 | struct hc_sp_status_block_data sp_sb_data; | |
768 | int func = BP_FUNC(bp); | |
769 | #ifdef BNX2X_STOP_ON_ERROR | |
770 | u16 start = 0, end = 0; | |
6383c0b3 | 771 | u8 cos; |
523224a3 | 772 | #endif |
a2fbb9ea | 773 | |
66e855f3 YG |
774 | bp->stats_state = STATS_STATE_DISABLED; |
775 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); | |
776 | ||
a2fbb9ea ET |
777 | BNX2X_ERR("begin crash dump -----------------\n"); |
778 | ||
8440d2b6 EG |
779 | /* Indices */ |
780 | /* Common */ | |
523224a3 | 781 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" |
619c5cb6 VZ |
782 | " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", |
783 | bp->def_idx, bp->def_att_idx, bp->attn_state, | |
784 | bp->spq_prod_idx, bp->stats_counter); | |
523224a3 DK |
785 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", |
786 | bp->def_status_blk->atten_status_block.attn_bits, | |
787 | bp->def_status_blk->atten_status_block.attn_bits_ack, | |
788 | bp->def_status_blk->atten_status_block.status_block_id, | |
789 | bp->def_status_blk->atten_status_block.attn_bits_index); | |
790 | BNX2X_ERR(" def ("); | |
791 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
792 | pr_cont("0x%x%s", | |
f1deab50 JP |
793 | bp->def_status_blk->sp_sb.index_values[i], |
794 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
523224a3 DK |
795 | |
796 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
797 | *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
798 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
799 | i*sizeof(u32)); | |
800 | ||
f1deab50 | 801 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", |
523224a3 DK |
802 | sp_sb_data.igu_sb_id, |
803 | sp_sb_data.igu_seg_id, | |
804 | sp_sb_data.p_func.pf_id, | |
805 | sp_sb_data.p_func.vnic_id, | |
806 | sp_sb_data.p_func.vf_id, | |
619c5cb6 VZ |
807 | sp_sb_data.p_func.vf_valid, |
808 | sp_sb_data.state); | |
523224a3 | 809 | |
8440d2b6 | 810 | |
ec6ba945 | 811 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 812 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 813 | int loop; |
f2e0899f | 814 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
815 | struct hc_status_block_data_e1x sb_data_e1x; |
816 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
817 | CHIP_IS_E1x(bp) ? |
818 | sb_data_e1x.common.state_machine : | |
819 | sb_data_e2.common.state_machine; | |
523224a3 | 820 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
821 | CHIP_IS_E1x(bp) ? |
822 | sb_data_e1x.index_data : | |
823 | sb_data_e2.index_data; | |
6383c0b3 | 824 | u8 data_size, cos; |
523224a3 | 825 | u32 *sb_data_p; |
6383c0b3 | 826 | struct bnx2x_fp_txdata txdata; |
523224a3 DK |
827 | |
828 | /* Rx */ | |
cdaa7cb8 | 829 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" |
523224a3 | 830 | " rx_comp_prod(0x%x)" |
cdaa7cb8 | 831 | " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 832 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 833 | fp->rx_comp_prod, |
66e855f3 | 834 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
cdaa7cb8 | 835 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" |
523224a3 | 836 | " fp_hc_idx(0x%x)\n", |
8440d2b6 | 837 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 838 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 839 | |
523224a3 | 840 | /* Tx */ |
6383c0b3 AE |
841 | for_each_cos_in_tx_queue(fp, cos) |
842 | { | |
843 | txdata = fp->txdata[cos]; | |
844 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" | |
845 | " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" | |
846 | " *tx_cons_sb(0x%x)\n", | |
847 | i, txdata.tx_pkt_prod, | |
848 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
849 | txdata.tx_bd_cons, | |
850 | le16_to_cpu(*txdata.tx_cons_sb)); | |
851 | } | |
523224a3 | 852 | |
619c5cb6 VZ |
853 | loop = CHIP_IS_E1x(bp) ? |
854 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
855 | |
856 | /* host sb data */ | |
857 | ||
ec6ba945 VZ |
858 | #ifdef BCM_CNIC |
859 | if (IS_FCOE_FP(fp)) | |
860 | continue; | |
861 | #endif | |
523224a3 DK |
862 | BNX2X_ERR(" run indexes ("); |
863 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
864 | pr_cont("0x%x%s", | |
865 | fp->sb_running_index[j], | |
866 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
867 | ||
868 | BNX2X_ERR(" indexes ("); | |
869 | for (j = 0; j < loop; j++) | |
870 | pr_cont("0x%x%s", | |
871 | fp->sb_index_values[j], | |
872 | (j == loop - 1) ? ")" : " "); | |
873 | /* fw sb data */ | |
619c5cb6 VZ |
874 | data_size = CHIP_IS_E1x(bp) ? |
875 | sizeof(struct hc_status_block_data_e1x) : | |
876 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 877 | data_size /= sizeof(u32); |
619c5cb6 VZ |
878 | sb_data_p = CHIP_IS_E1x(bp) ? |
879 | (u32 *)&sb_data_e1x : | |
880 | (u32 *)&sb_data_e2; | |
523224a3 DK |
881 | /* copy sb data in here */ |
882 | for (j = 0; j < data_size; j++) | |
883 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
884 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
885 | j * sizeof(u32)); | |
886 | ||
619c5cb6 VZ |
887 | if (!CHIP_IS_E1x(bp)) { |
888 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " | |
889 | "vnic_id(0x%x) same_igu_sb_1b(0x%x) " | |
890 | "state(0x%x)\n", | |
f2e0899f DK |
891 | sb_data_e2.common.p_func.pf_id, |
892 | sb_data_e2.common.p_func.vf_id, | |
893 | sb_data_e2.common.p_func.vf_valid, | |
894 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
895 | sb_data_e2.common.same_igu_sb_1b, |
896 | sb_data_e2.common.state); | |
f2e0899f | 897 | } else { |
619c5cb6 VZ |
898 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " |
899 | "vnic_id(0x%x) same_igu_sb_1b(0x%x) " | |
900 | "state(0x%x)\n", | |
f2e0899f DK |
901 | sb_data_e1x.common.p_func.pf_id, |
902 | sb_data_e1x.common.p_func.vf_id, | |
903 | sb_data_e1x.common.p_func.vf_valid, | |
904 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
905 | sb_data_e1x.common.same_igu_sb_1b, |
906 | sb_data_e1x.common.state); | |
f2e0899f | 907 | } |
523224a3 DK |
908 | |
909 | /* SB_SMs data */ | |
910 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
911 | pr_cont("SM[%d] __flags (0x%x) " | |
912 | "igu_sb_id (0x%x) igu_seg_id(0x%x) " | |
913 | "time_to_expire (0x%x) " | |
914 | "timer_value(0x%x)\n", j, | |
915 | hc_sm_p[j].__flags, | |
916 | hc_sm_p[j].igu_sb_id, | |
917 | hc_sm_p[j].igu_seg_id, | |
918 | hc_sm_p[j].time_to_expire, | |
919 | hc_sm_p[j].timer_value); | |
920 | } | |
921 | ||
922 | /* Indecies data */ | |
923 | for (j = 0; j < loop; j++) { | |
924 | pr_cont("INDEX[%d] flags (0x%x) " | |
925 | "timeout (0x%x)\n", j, | |
926 | hc_index_p[j].flags, | |
927 | hc_index_p[j].timeout); | |
928 | } | |
8440d2b6 | 929 | } |
a2fbb9ea | 930 | |
523224a3 | 931 | #ifdef BNX2X_STOP_ON_ERROR |
8440d2b6 EG |
932 | /* Rings */ |
933 | /* Rx */ | |
ec6ba945 | 934 | for_each_rx_queue(bp, i) { |
8440d2b6 | 935 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea ET |
936 | |
937 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); | |
938 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 939 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
940 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
941 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
942 | ||
c3eefaf6 EG |
943 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
944 | i, j, rx_bd[1], rx_bd[0], sw_bd->skb); | |
a2fbb9ea ET |
945 | } |
946 | ||
3196a88a EG |
947 | start = RX_SGE(fp->rx_sge_prod); |
948 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 949 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
950 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
951 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
952 | ||
c3eefaf6 EG |
953 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
954 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
955 | } |
956 | ||
a2fbb9ea ET |
957 | start = RCQ_BD(fp->rx_comp_cons - 10); |
958 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 959 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
960 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
961 | ||
c3eefaf6 EG |
962 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
963 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
964 | } |
965 | } | |
966 | ||
8440d2b6 | 967 | /* Tx */ |
ec6ba945 | 968 | for_each_tx_queue(bp, i) { |
8440d2b6 | 969 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
6383c0b3 AE |
970 | for_each_cos_in_tx_queue(fp, cos) { |
971 | struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; | |
972 | ||
973 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); | |
974 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
975 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
976 | struct sw_tx_bd *sw_bd = | |
977 | &txdata->tx_buf_ring[j]; | |
978 | ||
979 | BNX2X_ERR("fp%d: txdata %d, " | |
980 | "packet[%x]=[%p,%x]\n", | |
981 | i, cos, j, sw_bd->skb, | |
982 | sw_bd->first_bd); | |
983 | } | |
8440d2b6 | 984 | |
6383c0b3 AE |
985 | start = TX_BD(txdata->tx_bd_cons - 10); |
986 | end = TX_BD(txdata->tx_bd_cons + 254); | |
987 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
988 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 989 | |
6383c0b3 AE |
990 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" |
991 | "[%x:%x:%x:%x]\n", | |
992 | i, cos, j, tx_bd[0], tx_bd[1], | |
993 | tx_bd[2], tx_bd[3]); | |
994 | } | |
8440d2b6 EG |
995 | } |
996 | } | |
523224a3 | 997 | #endif |
34f80b04 | 998 | bnx2x_fw_dump(bp); |
a2fbb9ea ET |
999 | bnx2x_mc_assert(bp); |
1000 | BNX2X_ERR("end crash dump -----------------\n"); | |
a2fbb9ea ET |
1001 | } |
1002 | ||
619c5cb6 VZ |
1003 | /* |
1004 | * FLR Support for E2 | |
1005 | * | |
1006 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
1007 | * initialization. | |
1008 | */ | |
1009 | #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ | |
1010 | #define FLR_WAIT_INTERAVAL 50 /* usec */ | |
1011 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */ | |
1012 | ||
1013 | struct pbf_pN_buf_regs { | |
1014 | int pN; | |
1015 | u32 init_crd; | |
1016 | u32 crd; | |
1017 | u32 crd_freed; | |
1018 | }; | |
1019 | ||
1020 | struct pbf_pN_cmd_regs { | |
1021 | int pN; | |
1022 | u32 lines_occup; | |
1023 | u32 lines_freed; | |
1024 | }; | |
1025 | ||
1026 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
1027 | struct pbf_pN_buf_regs *regs, | |
1028 | u32 poll_count) | |
1029 | { | |
1030 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
1031 | u32 cur_cnt = poll_count; | |
1032 | ||
1033 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
1034 | crd = crd_start = REG_RD(bp, regs->crd); | |
1035 | init_crd = REG_RD(bp, regs->init_crd); | |
1036 | ||
1037 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
1038 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
1039 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
1040 | ||
1041 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
1042 | (init_crd - crd_start))) { | |
1043 | if (cur_cnt--) { | |
1044 | udelay(FLR_WAIT_INTERAVAL); | |
1045 | crd = REG_RD(bp, regs->crd); | |
1046 | crd_freed = REG_RD(bp, regs->crd_freed); | |
1047 | } else { | |
1048 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
1049 | regs->pN); | |
1050 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
1051 | regs->pN, crd); | |
1052 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
1053 | regs->pN, crd_freed); | |
1054 | break; | |
1055 | } | |
1056 | } | |
1057 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
1058 | poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); | |
1059 | } | |
1060 | ||
1061 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
1062 | struct pbf_pN_cmd_regs *regs, | |
1063 | u32 poll_count) | |
1064 | { | |
1065 | u32 occup, to_free, freed, freed_start; | |
1066 | u32 cur_cnt = poll_count; | |
1067 | ||
1068 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
1069 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
1070 | ||
1071 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
1072 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
1073 | ||
1074 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
1075 | if (cur_cnt--) { | |
1076 | udelay(FLR_WAIT_INTERAVAL); | |
1077 | occup = REG_RD(bp, regs->lines_occup); | |
1078 | freed = REG_RD(bp, regs->lines_freed); | |
1079 | } else { | |
1080 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
1081 | regs->pN); | |
1082 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
1083 | regs->pN, occup); | |
1084 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
1085 | regs->pN, freed); | |
1086 | break; | |
1087 | } | |
1088 | } | |
1089 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
1090 | poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); | |
1091 | } | |
1092 | ||
1093 | static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, | |
1094 | u32 expected, u32 poll_count) | |
1095 | { | |
1096 | u32 cur_cnt = poll_count; | |
1097 | u32 val; | |
1098 | ||
1099 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
1100 | udelay(FLR_WAIT_INTERAVAL); | |
1101 | ||
1102 | return val; | |
1103 | } | |
1104 | ||
1105 | static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, | |
1106 | char *msg, u32 poll_cnt) | |
1107 | { | |
1108 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1109 | if (val != 0) { | |
1110 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1111 | return 1; | |
1112 | } | |
1113 | return 0; | |
1114 | } | |
1115 | ||
1116 | static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
1117 | { | |
1118 | /* adjust polling timeout */ | |
1119 | if (CHIP_REV_IS_EMUL(bp)) | |
1120 | return FLR_POLL_CNT * 2000; | |
1121 | ||
1122 | if (CHIP_REV_IS_FPGA(bp)) | |
1123 | return FLR_POLL_CNT * 120; | |
1124 | ||
1125 | return FLR_POLL_CNT; | |
1126 | } | |
1127 | ||
1128 | static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) | |
1129 | { | |
1130 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1131 | {0, (CHIP_IS_E3B0(bp)) ? | |
1132 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1133 | PBF_REG_P0_TQ_OCCUPANCY, | |
1134 | (CHIP_IS_E3B0(bp)) ? | |
1135 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1136 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1137 | {1, (CHIP_IS_E3B0(bp)) ? | |
1138 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1139 | PBF_REG_P1_TQ_OCCUPANCY, | |
1140 | (CHIP_IS_E3B0(bp)) ? | |
1141 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1142 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1143 | {4, (CHIP_IS_E3B0(bp)) ? | |
1144 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1145 | PBF_REG_P4_TQ_OCCUPANCY, | |
1146 | (CHIP_IS_E3B0(bp)) ? | |
1147 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1148 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1149 | }; | |
1150 | ||
1151 | struct pbf_pN_buf_regs buf_regs[] = { | |
1152 | {0, (CHIP_IS_E3B0(bp)) ? | |
1153 | PBF_REG_INIT_CRD_Q0 : | |
1154 | PBF_REG_P0_INIT_CRD , | |
1155 | (CHIP_IS_E3B0(bp)) ? | |
1156 | PBF_REG_CREDIT_Q0 : | |
1157 | PBF_REG_P0_CREDIT, | |
1158 | (CHIP_IS_E3B0(bp)) ? | |
1159 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1160 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1161 | {1, (CHIP_IS_E3B0(bp)) ? | |
1162 | PBF_REG_INIT_CRD_Q1 : | |
1163 | PBF_REG_P1_INIT_CRD, | |
1164 | (CHIP_IS_E3B0(bp)) ? | |
1165 | PBF_REG_CREDIT_Q1 : | |
1166 | PBF_REG_P1_CREDIT, | |
1167 | (CHIP_IS_E3B0(bp)) ? | |
1168 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1169 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1170 | {4, (CHIP_IS_E3B0(bp)) ? | |
1171 | PBF_REG_INIT_CRD_LB_Q : | |
1172 | PBF_REG_P4_INIT_CRD, | |
1173 | (CHIP_IS_E3B0(bp)) ? | |
1174 | PBF_REG_CREDIT_LB_Q : | |
1175 | PBF_REG_P4_CREDIT, | |
1176 | (CHIP_IS_E3B0(bp)) ? | |
1177 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1178 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1179 | }; | |
1180 | ||
1181 | int i; | |
1182 | ||
1183 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1184 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1185 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1186 | ||
1187 | ||
1188 | /* Verify the transmission buffers are flushed P0, P1, P4 */ | |
1189 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1190 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1191 | } | |
1192 | ||
1193 | #define OP_GEN_PARAM(param) \ | |
1194 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1195 | ||
1196 | #define OP_GEN_TYPE(type) \ | |
1197 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1198 | ||
1199 | #define OP_GEN_AGG_VECT(index) \ | |
1200 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1201 | ||
1202 | ||
1203 | static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, | |
1204 | u32 poll_cnt) | |
1205 | { | |
1206 | struct sdm_op_gen op_gen = {0}; | |
1207 | ||
1208 | u32 comp_addr = BAR_CSTRORM_INTMEM + | |
1209 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1210 | int ret = 0; | |
1211 | ||
1212 | if (REG_RD(bp, comp_addr)) { | |
1213 | BNX2X_ERR("Cleanup complete is not 0\n"); | |
1214 | return 1; | |
1215 | } | |
1216 | ||
1217 | op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); | |
1218 | op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1219 | op_gen.command |= OP_GEN_AGG_VECT(clnup_func); | |
1220 | op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
1221 | ||
1222 | DP(BNX2X_MSG_SP, "FW Final cleanup\n"); | |
1223 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); | |
1224 | ||
1225 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1226 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
1227 | ret = 1; | |
1228 | } | |
1229 | /* Zero completion for nxt FLR */ | |
1230 | REG_WR(bp, comp_addr, 0); | |
1231 | ||
1232 | return ret; | |
1233 | } | |
1234 | ||
1235 | static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) | |
1236 | { | |
1237 | int pos; | |
1238 | u16 status; | |
1239 | ||
77c98e6a | 1240 | pos = pci_pcie_cap(dev); |
619c5cb6 VZ |
1241 | if (!pos) |
1242 | return false; | |
1243 | ||
1244 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); | |
1245 | return status & PCI_EXP_DEVSTA_TRPND; | |
1246 | } | |
1247 | ||
1248 | /* PF FLR specific routines | |
1249 | */ | |
1250 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1251 | { | |
1252 | ||
1253 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ | |
1254 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1255 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1256 | "CFC PF usage counter timed out", | |
1257 | poll_cnt)) | |
1258 | return 1; | |
1259 | ||
1260 | ||
1261 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ | |
1262 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1263 | DORQ_REG_PF_USAGE_CNT, | |
1264 | "DQ PF usage counter timed out", | |
1265 | poll_cnt)) | |
1266 | return 1; | |
1267 | ||
1268 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1269 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1270 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1271 | "QM PF usage counter timed out", | |
1272 | poll_cnt)) | |
1273 | return 1; | |
1274 | ||
1275 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1276 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1277 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1278 | "Timers VNIC usage counter timed out", | |
1279 | poll_cnt)) | |
1280 | return 1; | |
1281 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1282 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1283 | "Timers NUM_SCANS usage counter timed out", | |
1284 | poll_cnt)) | |
1285 | return 1; | |
1286 | ||
1287 | /* Wait DMAE PF usage counter to zero */ | |
1288 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1289 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
1290 | "DMAE dommand register timed out", | |
1291 | poll_cnt)) | |
1292 | return 1; | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1298 | { | |
1299 | u32 val; | |
1300 | ||
1301 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1302 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1303 | ||
1304 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1305 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1306 | ||
1307 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1308 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1309 | ||
1310 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1311 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1312 | ||
1313 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1314 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1315 | ||
1316 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1317 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1318 | ||
1319 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1320 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1321 | ||
1322 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1323 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1324 | val); | |
1325 | } | |
1326 | ||
1327 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1328 | { | |
1329 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1330 | ||
1331 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1332 | ||
1333 | /* Re-enable PF target read access */ | |
1334 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1335 | ||
1336 | /* Poll HW usage counters */ | |
1337 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) | |
1338 | return -EBUSY; | |
1339 | ||
1340 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1341 | ||
1342 | /* Send the FW cleanup command */ | |
1343 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1344 | return -EBUSY; | |
1345 | ||
1346 | /* ATC cleanup */ | |
1347 | ||
1348 | /* Verify TX hw is flushed */ | |
1349 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1350 | ||
1351 | /* Wait 100ms (not adjusted according to platform) */ | |
1352 | msleep(100); | |
1353 | ||
1354 | /* Verify no pending pci transactions */ | |
1355 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1356 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1357 | ||
1358 | /* Debug */ | |
1359 | bnx2x_hw_enable_status(bp); | |
1360 | ||
1361 | /* | |
1362 | * Master enable - Due to WB DMAE writes performed before this | |
1363 | * register is re-initialized as part of the regular function init | |
1364 | */ | |
1365 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1366 | ||
1367 | return 0; | |
1368 | } | |
1369 | ||
f2e0899f | 1370 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1371 | { |
34f80b04 | 1372 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1373 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1374 | u32 val = REG_RD(bp, addr); | |
1375 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
8badd27a | 1376 | int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; |
a2fbb9ea ET |
1377 | |
1378 | if (msix) { | |
8badd27a EG |
1379 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1380 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1381 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1382 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
8badd27a EG |
1383 | } else if (msi) { |
1384 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1385 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1386 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1387 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1388 | } else { |
1389 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1390 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1391 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1392 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1393 | |
a0fd065c DK |
1394 | if (!CHIP_IS_E1(bp)) { |
1395 | DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", | |
1396 | val, port, addr); | |
615f8fd9 | 1397 | |
a0fd065c | 1398 | REG_WR(bp, addr, val); |
615f8fd9 | 1399 | |
a0fd065c DK |
1400 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1401 | } | |
a2fbb9ea ET |
1402 | } |
1403 | ||
a0fd065c DK |
1404 | if (CHIP_IS_E1(bp)) |
1405 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1406 | ||
8badd27a EG |
1407 | DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", |
1408 | val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1409 | |
1410 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1411 | /* |
1412 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1413 | */ | |
1414 | mmiowb(); | |
1415 | barrier(); | |
34f80b04 | 1416 | |
f2e0899f | 1417 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1418 | /* init leading/trailing edge */ |
fb3bff17 | 1419 | if (IS_MF(bp)) { |
3395a033 | 1420 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1421 | if (bp->port.pmf) |
4acac6a5 EG |
1422 | /* enable nig and gpio3 attention */ |
1423 | val |= 0x1100; | |
34f80b04 EG |
1424 | } else |
1425 | val = 0xffff; | |
1426 | ||
1427 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1428 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1429 | } | |
37dbbf32 EG |
1430 | |
1431 | /* Make sure that interrupts are indeed enabled from here on */ | |
1432 | mmiowb(); | |
a2fbb9ea ET |
1433 | } |
1434 | ||
f2e0899f DK |
1435 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1436 | { | |
1437 | u32 val; | |
1438 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
1439 | int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; | |
1440 | ||
1441 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1442 | ||
1443 | if (msix) { | |
1444 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1445 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1446 | val |= (IGU_PF_CONF_FUNC_EN | | |
1447 | IGU_PF_CONF_MSI_MSIX_EN | | |
1448 | IGU_PF_CONF_ATTN_BIT_EN); | |
1449 | } else if (msi) { | |
1450 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
1451 | val |= (IGU_PF_CONF_FUNC_EN | | |
1452 | IGU_PF_CONF_MSI_MSIX_EN | | |
1453 | IGU_PF_CONF_ATTN_BIT_EN | | |
1454 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1455 | } else { | |
1456 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
1457 | val |= (IGU_PF_CONF_FUNC_EN | | |
1458 | IGU_PF_CONF_INT_LINE_EN | | |
1459 | IGU_PF_CONF_ATTN_BIT_EN | | |
1460 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1461 | } | |
1462 | ||
1463 | DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", | |
1464 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
1465 | ||
1466 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1467 | ||
1468 | barrier(); | |
1469 | ||
1470 | /* init leading/trailing edge */ | |
1471 | if (IS_MF(bp)) { | |
3395a033 | 1472 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1473 | if (bp->port.pmf) |
1474 | /* enable nig and gpio3 attention */ | |
1475 | val |= 0x1100; | |
1476 | } else | |
1477 | val = 0xffff; | |
1478 | ||
1479 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1480 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1481 | ||
1482 | /* Make sure that interrupts are indeed enabled from here on */ | |
1483 | mmiowb(); | |
1484 | } | |
1485 | ||
1486 | void bnx2x_int_enable(struct bnx2x *bp) | |
1487 | { | |
1488 | if (bp->common.int_block == INT_BLOCK_HC) | |
1489 | bnx2x_hc_int_enable(bp); | |
1490 | else | |
1491 | bnx2x_igu_int_enable(bp); | |
1492 | } | |
1493 | ||
1494 | static void bnx2x_hc_int_disable(struct bnx2x *bp) | |
a2fbb9ea | 1495 | { |
34f80b04 | 1496 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1497 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1498 | u32 val = REG_RD(bp, addr); | |
1499 | ||
a0fd065c DK |
1500 | /* |
1501 | * in E1 we must use only PCI configuration space to disable | |
1502 | * MSI/MSIX capablility | |
1503 | * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
1504 | */ | |
1505 | if (CHIP_IS_E1(bp)) { | |
1506 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
1507 | * Use mask register to prevent from HC sending interrupts | |
1508 | * after we exit the function | |
1509 | */ | |
1510 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
1511 | ||
1512 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1513 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1514 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
1515 | } else | |
1516 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1517 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1518 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1519 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1520 | |
1521 | DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", | |
1522 | val, port, addr); | |
1523 | ||
8badd27a EG |
1524 | /* flush all outstanding writes */ |
1525 | mmiowb(); | |
1526 | ||
a2fbb9ea ET |
1527 | REG_WR(bp, addr, val); |
1528 | if (REG_RD(bp, addr) != val) | |
1529 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1530 | } | |
1531 | ||
f2e0899f DK |
1532 | static void bnx2x_igu_int_disable(struct bnx2x *bp) |
1533 | { | |
1534 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1535 | ||
1536 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
1537 | IGU_PF_CONF_INT_LINE_EN | | |
1538 | IGU_PF_CONF_ATTN_BIT_EN); | |
1539 | ||
1540 | DP(NETIF_MSG_INTR, "write %x to IGU\n", val); | |
1541 | ||
1542 | /* flush all outstanding writes */ | |
1543 | mmiowb(); | |
1544 | ||
1545 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1546 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
1547 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1548 | } | |
1549 | ||
6383c0b3 | 1550 | void bnx2x_int_disable(struct bnx2x *bp) |
f2e0899f DK |
1551 | { |
1552 | if (bp->common.int_block == INT_BLOCK_HC) | |
1553 | bnx2x_hc_int_disable(bp); | |
1554 | else | |
1555 | bnx2x_igu_int_disable(bp); | |
1556 | } | |
1557 | ||
9f6c9258 | 1558 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1559 | { |
a2fbb9ea | 1560 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1561 | int i, offset; |
a2fbb9ea | 1562 | |
f8ef6e44 YG |
1563 | if (disable_hw) |
1564 | /* prevent the HW from sending interrupts */ | |
1565 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1566 | |
1567 | /* make sure all ISRs are done */ | |
1568 | if (msix) { | |
8badd27a EG |
1569 | synchronize_irq(bp->msix_table[0].vector); |
1570 | offset = 1; | |
37b091ba MC |
1571 | #ifdef BCM_CNIC |
1572 | offset++; | |
1573 | #endif | |
ec6ba945 | 1574 | for_each_eth_queue(bp, i) |
754a2f52 | 1575 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1576 | } else |
1577 | synchronize_irq(bp->pdev->irq); | |
1578 | ||
1579 | /* make sure sp_task is not running */ | |
1cf167f2 | 1580 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1581 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1582 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1583 | } |
1584 | ||
34f80b04 | 1585 | /* fast path */ |
a2fbb9ea ET |
1586 | |
1587 | /* | |
34f80b04 | 1588 | * General service functions |
a2fbb9ea ET |
1589 | */ |
1590 | ||
72fd0718 VZ |
1591 | /* Return true if succeeded to acquire the lock */ |
1592 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1593 | { | |
1594 | u32 lock_status; | |
1595 | u32 resource_bit = (1 << resource); | |
1596 | int func = BP_FUNC(bp); | |
1597 | u32 hw_lock_control_reg; | |
1598 | ||
1599 | DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); | |
1600 | ||
1601 | /* Validating that the resource is within range */ | |
1602 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
1603 | DP(NETIF_MSG_HW, | |
1604 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", | |
1605 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1606 | return false; |
72fd0718 VZ |
1607 | } |
1608 | ||
1609 | if (func <= 5) | |
1610 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1611 | else | |
1612 | hw_lock_control_reg = | |
1613 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1614 | ||
1615 | /* Try to acquire the lock */ | |
1616 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1617 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1618 | if (lock_status & resource_bit) | |
1619 | return true; | |
1620 | ||
1621 | DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); | |
1622 | return false; | |
1623 | } | |
1624 | ||
c9ee9206 VZ |
1625 | /** |
1626 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1627 | * | |
1628 | * @bp: driver handle | |
1629 | * | |
1630 | * Returns the recovery leader resource id according to the engine this function | |
1631 | * belongs to. Currently only only 2 engines is supported. | |
1632 | */ | |
1633 | static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) | |
1634 | { | |
1635 | if (BP_PATH(bp)) | |
1636 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1637 | else | |
1638 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1639 | } | |
1640 | ||
1641 | /** | |
1642 | * bnx2x_trylock_leader_lock- try to aquire a leader lock. | |
1643 | * | |
1644 | * @bp: driver handle | |
1645 | * | |
1646 | * Tries to aquire a leader lock for cuurent engine. | |
1647 | */ | |
1648 | static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) | |
1649 | { | |
1650 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1651 | } | |
1652 | ||
993ac7b5 | 1653 | #ifdef BCM_CNIC |
619c5cb6 | 1654 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
993ac7b5 | 1655 | #endif |
3196a88a | 1656 | |
619c5cb6 | 1657 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1658 | { |
1659 | struct bnx2x *bp = fp->bp; | |
1660 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1661 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 VZ |
1662 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
1663 | struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; | |
a2fbb9ea | 1664 | |
34f80b04 | 1665 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1666 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1667 | fp->index, cid, command, bp->state, |
34f80b04 | 1668 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1669 | |
619c5cb6 VZ |
1670 | switch (command) { |
1671 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1672 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1673 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1674 | break; | |
d6cae238 | 1675 | |
619c5cb6 | 1676 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1677 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1678 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1679 | break; |
1680 | ||
6383c0b3 AE |
1681 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
1682 | DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); | |
1683 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
1684 | break; | |
1685 | ||
619c5cb6 | 1686 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1687 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1688 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1689 | break; |
1690 | ||
619c5cb6 | 1691 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
d6cae238 | 1692 | DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); |
619c5cb6 | 1693 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1694 | break; |
1695 | ||
619c5cb6 | 1696 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1697 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1698 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1699 | break; |
619c5cb6 VZ |
1700 | |
1701 | default: | |
1702 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1703 | command, fp->index); | |
1704 | return; | |
523224a3 | 1705 | } |
3196a88a | 1706 | |
619c5cb6 VZ |
1707 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1708 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1709 | /* q_obj->complete_cmd() failure means that this was | |
1710 | * an unexpected completion. | |
1711 | * | |
1712 | * In this case we don't want to increase the bp->spq_left | |
1713 | * because apparently we haven't sent this command the first | |
1714 | * place. | |
1715 | */ | |
1716 | #ifdef BNX2X_STOP_ON_ERROR | |
1717 | bnx2x_panic(); | |
1718 | #else | |
1719 | return; | |
1720 | #endif | |
1721 | ||
8fe23fbd | 1722 | smp_mb__before_atomic_inc(); |
6e30dd4e | 1723 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 VZ |
1724 | /* push the change in bp->spq_left and towards the memory */ |
1725 | smp_mb__after_atomic_inc(); | |
49d66772 | 1726 | |
d6cae238 VZ |
1727 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1728 | ||
523224a3 | 1729 | return; |
a2fbb9ea ET |
1730 | } |
1731 | ||
619c5cb6 VZ |
1732 | void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
1733 | u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) | |
1734 | { | |
1735 | u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; | |
1736 | ||
1737 | bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, | |
1738 | start); | |
1739 | } | |
1740 | ||
9f6c9258 | 1741 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1742 | { |
555f6c78 | 1743 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1744 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1745 | u16 mask; |
ca00392c | 1746 | int i; |
6383c0b3 | 1747 | u8 cos; |
a2fbb9ea | 1748 | |
34f80b04 | 1749 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1750 | if (unlikely(status == 0)) { |
1751 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1752 | return IRQ_NONE; | |
1753 | } | |
f5372251 | 1754 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1755 | |
3196a88a EG |
1756 | #ifdef BNX2X_STOP_ON_ERROR |
1757 | if (unlikely(bp->panic)) | |
1758 | return IRQ_HANDLED; | |
1759 | #endif | |
1760 | ||
ec6ba945 | 1761 | for_each_eth_queue(bp, i) { |
ca00392c | 1762 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1763 | |
6383c0b3 | 1764 | mask = 0x2 << (fp->index + CNIC_PRESENT); |
ca00392c | 1765 | if (status & mask) { |
619c5cb6 | 1766 | /* Handle Rx or Tx according to SB id */ |
54b9ddaa | 1767 | prefetch(fp->rx_cons_sb); |
6383c0b3 AE |
1768 | for_each_cos_in_tx_queue(fp, cos) |
1769 | prefetch(fp->txdata[cos].tx_cons_sb); | |
523224a3 | 1770 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
54b9ddaa | 1771 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1772 | status &= ~mask; |
1773 | } | |
a2fbb9ea ET |
1774 | } |
1775 | ||
993ac7b5 | 1776 | #ifdef BCM_CNIC |
523224a3 | 1777 | mask = 0x2; |
993ac7b5 MC |
1778 | if (status & (mask | 0x1)) { |
1779 | struct cnic_ops *c_ops = NULL; | |
1780 | ||
619c5cb6 VZ |
1781 | if (likely(bp->state == BNX2X_STATE_OPEN)) { |
1782 | rcu_read_lock(); | |
1783 | c_ops = rcu_dereference(bp->cnic_ops); | |
1784 | if (c_ops) | |
1785 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1786 | rcu_read_unlock(); | |
1787 | } | |
993ac7b5 MC |
1788 | |
1789 | status &= ~mask; | |
1790 | } | |
1791 | #endif | |
a2fbb9ea | 1792 | |
34f80b04 | 1793 | if (unlikely(status & 0x1)) { |
1cf167f2 | 1794 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
1795 | |
1796 | status &= ~0x1; | |
1797 | if (!status) | |
1798 | return IRQ_HANDLED; | |
1799 | } | |
1800 | ||
cdaa7cb8 VZ |
1801 | if (unlikely(status)) |
1802 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1803 | status); |
a2fbb9ea | 1804 | |
c18487ee | 1805 | return IRQ_HANDLED; |
a2fbb9ea ET |
1806 | } |
1807 | ||
c18487ee YR |
1808 | /* Link */ |
1809 | ||
1810 | /* | |
1811 | * General service functions | |
1812 | */ | |
a2fbb9ea | 1813 | |
9f6c9258 | 1814 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1815 | { |
1816 | u32 lock_status; | |
1817 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1818 | int func = BP_FUNC(bp); |
1819 | u32 hw_lock_control_reg; | |
c18487ee | 1820 | int cnt; |
a2fbb9ea | 1821 | |
c18487ee YR |
1822 | /* Validating that the resource is within range */ |
1823 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
1824 | DP(NETIF_MSG_HW, | |
1825 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", | |
1826 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
1827 | return -EINVAL; | |
1828 | } | |
a2fbb9ea | 1829 | |
4a37fb66 YG |
1830 | if (func <= 5) { |
1831 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1832 | } else { | |
1833 | hw_lock_control_reg = | |
1834 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1835 | } | |
1836 | ||
c18487ee | 1837 | /* Validating that the resource is not already taken */ |
4a37fb66 | 1838 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee YR |
1839 | if (lock_status & resource_bit) { |
1840 | DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", | |
1841 | lock_status, resource_bit); | |
1842 | return -EEXIST; | |
1843 | } | |
a2fbb9ea | 1844 | |
46230476 EG |
1845 | /* Try for 5 second every 5ms */ |
1846 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 1847 | /* Try to acquire the lock */ |
4a37fb66 YG |
1848 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
1849 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
1850 | if (lock_status & resource_bit) |
1851 | return 0; | |
a2fbb9ea | 1852 | |
c18487ee | 1853 | msleep(5); |
a2fbb9ea | 1854 | } |
c18487ee YR |
1855 | DP(NETIF_MSG_HW, "Timeout\n"); |
1856 | return -EAGAIN; | |
1857 | } | |
a2fbb9ea | 1858 | |
c9ee9206 VZ |
1859 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
1860 | { | |
1861 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1862 | } | |
1863 | ||
9f6c9258 | 1864 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1865 | { |
1866 | u32 lock_status; | |
1867 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1868 | int func = BP_FUNC(bp); |
1869 | u32 hw_lock_control_reg; | |
a2fbb9ea | 1870 | |
72fd0718 VZ |
1871 | DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); |
1872 | ||
c18487ee YR |
1873 | /* Validating that the resource is within range */ |
1874 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
1875 | DP(NETIF_MSG_HW, | |
1876 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", | |
1877 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
1878 | return -EINVAL; | |
1879 | } | |
1880 | ||
4a37fb66 YG |
1881 | if (func <= 5) { |
1882 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1883 | } else { | |
1884 | hw_lock_control_reg = | |
1885 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1886 | } | |
1887 | ||
c18487ee | 1888 | /* Validating that the resource is currently taken */ |
4a37fb66 | 1889 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee YR |
1890 | if (!(lock_status & resource_bit)) { |
1891 | DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", | |
1892 | lock_status, resource_bit); | |
1893 | return -EFAULT; | |
a2fbb9ea ET |
1894 | } |
1895 | ||
9f6c9258 DK |
1896 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
1897 | return 0; | |
c18487ee | 1898 | } |
a2fbb9ea | 1899 | |
9f6c9258 | 1900 | |
4acac6a5 EG |
1901 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
1902 | { | |
1903 | /* The GPIO should be swapped if swap register is set and active */ | |
1904 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1905 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1906 | int gpio_shift = gpio_num + | |
1907 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1908 | u32 gpio_mask = (1 << gpio_shift); | |
1909 | u32 gpio_reg; | |
1910 | int value; | |
1911 | ||
1912 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1913 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1914 | return -EINVAL; | |
1915 | } | |
1916 | ||
1917 | /* read GPIO value */ | |
1918 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1919 | ||
1920 | /* get the requested pin value */ | |
1921 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
1922 | value = 1; | |
1923 | else | |
1924 | value = 0; | |
1925 | ||
1926 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); | |
1927 | ||
1928 | return value; | |
1929 | } | |
1930 | ||
17de50b7 | 1931 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
1932 | { |
1933 | /* The GPIO should be swapped if swap register is set and active */ | |
1934 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 1935 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
1936 | int gpio_shift = gpio_num + |
1937 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1938 | u32 gpio_mask = (1 << gpio_shift); | |
1939 | u32 gpio_reg; | |
a2fbb9ea | 1940 | |
c18487ee YR |
1941 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
1942 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1943 | return -EINVAL; | |
1944 | } | |
a2fbb9ea | 1945 | |
4a37fb66 | 1946 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
1947 | /* read GPIO and mask except the float bits */ |
1948 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 1949 | |
c18487ee YR |
1950 | switch (mode) { |
1951 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
1952 | DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", | |
1953 | gpio_num, gpio_shift); | |
1954 | /* clear FLOAT and set CLR */ | |
1955 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1956 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
1957 | break; | |
a2fbb9ea | 1958 | |
c18487ee YR |
1959 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
1960 | DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", | |
1961 | gpio_num, gpio_shift); | |
1962 | /* clear FLOAT and set SET */ | |
1963 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1964 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
1965 | break; | |
a2fbb9ea | 1966 | |
17de50b7 | 1967 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
c18487ee YR |
1968 | DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", |
1969 | gpio_num, gpio_shift); | |
1970 | /* set FLOAT */ | |
1971 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1972 | break; | |
a2fbb9ea | 1973 | |
c18487ee YR |
1974 | default: |
1975 | break; | |
a2fbb9ea ET |
1976 | } |
1977 | ||
c18487ee | 1978 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 1979 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 1980 | |
c18487ee | 1981 | return 0; |
a2fbb9ea ET |
1982 | } |
1983 | ||
0d40f0d4 YR |
1984 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
1985 | { | |
1986 | u32 gpio_reg = 0; | |
1987 | int rc = 0; | |
1988 | ||
1989 | /* Any port swapping should be handled by caller. */ | |
1990 | ||
1991 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1992 | /* read GPIO and mask except the float bits */ | |
1993 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1994 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1995 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1996 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
1997 | ||
1998 | switch (mode) { | |
1999 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
2000 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
2001 | /* set CLR */ | |
2002 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2003 | break; | |
2004 | ||
2005 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
2006 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
2007 | /* set SET */ | |
2008 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
2009 | break; | |
2010 | ||
2011 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
2012 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
2013 | /* set FLOAT */ | |
2014 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2015 | break; | |
2016 | ||
2017 | default: | |
2018 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
2019 | rc = -EINVAL; | |
2020 | break; | |
2021 | } | |
2022 | ||
2023 | if (rc == 0) | |
2024 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
2025 | ||
2026 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2027 | ||
2028 | return rc; | |
2029 | } | |
2030 | ||
4acac6a5 EG |
2031 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
2032 | { | |
2033 | /* The GPIO should be swapped if swap register is set and active */ | |
2034 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2035 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2036 | int gpio_shift = gpio_num + | |
2037 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2038 | u32 gpio_mask = (1 << gpio_shift); | |
2039 | u32 gpio_reg; | |
2040 | ||
2041 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2042 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2043 | return -EINVAL; | |
2044 | } | |
2045 | ||
2046 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2047 | /* read GPIO int */ | |
2048 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
2049 | ||
2050 | switch (mode) { | |
2051 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
2052 | DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " | |
2053 | "output low\n", gpio_num, gpio_shift); | |
2054 | /* clear SET and set CLR */ | |
2055 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2056 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2057 | break; | |
2058 | ||
2059 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
2060 | DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " | |
2061 | "output high\n", gpio_num, gpio_shift); | |
2062 | /* clear CLR and set SET */ | |
2063 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2064 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2065 | break; | |
2066 | ||
2067 | default: | |
2068 | break; | |
2069 | } | |
2070 | ||
2071 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2072 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2073 | ||
2074 | return 0; | |
2075 | } | |
2076 | ||
c18487ee | 2077 | static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) |
a2fbb9ea | 2078 | { |
c18487ee YR |
2079 | u32 spio_mask = (1 << spio_num); |
2080 | u32 spio_reg; | |
a2fbb9ea | 2081 | |
c18487ee YR |
2082 | if ((spio_num < MISC_REGISTERS_SPIO_4) || |
2083 | (spio_num > MISC_REGISTERS_SPIO_7)) { | |
2084 | BNX2X_ERR("Invalid SPIO %d\n", spio_num); | |
2085 | return -EINVAL; | |
a2fbb9ea ET |
2086 | } |
2087 | ||
4a37fb66 | 2088 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee YR |
2089 | /* read SPIO and mask except the float bits */ |
2090 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); | |
a2fbb9ea | 2091 | |
c18487ee | 2092 | switch (mode) { |
6378c025 | 2093 | case MISC_REGISTERS_SPIO_OUTPUT_LOW: |
c18487ee YR |
2094 | DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); |
2095 | /* clear FLOAT and set CLR */ | |
2096 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2097 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); | |
2098 | break; | |
a2fbb9ea | 2099 | |
6378c025 | 2100 | case MISC_REGISTERS_SPIO_OUTPUT_HIGH: |
c18487ee YR |
2101 | DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); |
2102 | /* clear FLOAT and set SET */ | |
2103 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2104 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); | |
2105 | break; | |
a2fbb9ea | 2106 | |
c18487ee YR |
2107 | case MISC_REGISTERS_SPIO_INPUT_HI_Z: |
2108 | DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); | |
2109 | /* set FLOAT */ | |
2110 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | |
2111 | break; | |
a2fbb9ea | 2112 | |
c18487ee YR |
2113 | default: |
2114 | break; | |
a2fbb9ea ET |
2115 | } |
2116 | ||
c18487ee | 2117 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2118 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2119 | |
a2fbb9ea ET |
2120 | return 0; |
2121 | } | |
2122 | ||
9f6c9258 | 2123 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2124 | { |
a22f0788 | 2125 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
ad33ea3a EG |
2126 | switch (bp->link_vars.ieee_fc & |
2127 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2128 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: |
a22f0788 | 2129 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2130 | ADVERTISED_Pause); |
c18487ee | 2131 | break; |
356e2385 | 2132 | |
c18487ee | 2133 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2134 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2135 | ADVERTISED_Pause); |
c18487ee | 2136 | break; |
356e2385 | 2137 | |
c18487ee | 2138 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2139 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2140 | break; |
356e2385 | 2141 | |
c18487ee | 2142 | default: |
a22f0788 | 2143 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2144 | ADVERTISED_Pause); |
c18487ee YR |
2145 | break; |
2146 | } | |
2147 | } | |
f1410647 | 2148 | |
9f6c9258 | 2149 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
c18487ee | 2150 | { |
19680c48 EG |
2151 | if (!BP_NOMCP(bp)) { |
2152 | u8 rc; | |
a22f0788 YR |
2153 | int cfx_idx = bnx2x_get_link_cfg_idx(bp); |
2154 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
1cb0c788 YR |
2155 | /* |
2156 | * Initialize link parameters structure variables | |
2157 | * It is recommended to turn off RX FC for jumbo frames | |
2158 | * for better performance | |
2159 | */ | |
2160 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
c0700f90 | 2161 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; |
8c99e7b0 | 2162 | else |
c0700f90 | 2163 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; |
a2fbb9ea | 2164 | |
4a37fb66 | 2165 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2166 | |
a22f0788 | 2167 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2168 | struct link_params *lp = &bp->link_params; |
2169 | lp->loopback_mode = LOOPBACK_XGXS; | |
2170 | /* do PHY loopback at 10G speed, if possible */ | |
2171 | if (lp->req_line_speed[cfx_idx] < SPEED_10000) { | |
2172 | if (lp->speed_cap_mask[cfx_idx] & | |
2173 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2174 | lp->req_line_speed[cfx_idx] = | |
2175 | SPEED_10000; | |
2176 | else | |
2177 | lp->req_line_speed[cfx_idx] = | |
2178 | SPEED_1000; | |
2179 | } | |
a22f0788 | 2180 | } |
b5bf9068 | 2181 | |
19680c48 | 2182 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2183 | |
4a37fb66 | 2184 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2185 | |
3c96c68b EG |
2186 | bnx2x_calc_fc_adv(bp); |
2187 | ||
b5bf9068 EG |
2188 | if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { |
2189 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
19680c48 | 2190 | bnx2x_link_report(bp); |
3deb8167 YR |
2191 | } else |
2192 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2193 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2194 | return rc; |
2195 | } | |
f5372251 | 2196 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2197 | return -EINVAL; |
a2fbb9ea ET |
2198 | } |
2199 | ||
9f6c9258 | 2200 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2201 | { |
19680c48 | 2202 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2203 | bnx2x_acquire_phy_lock(bp); |
54c2fb78 | 2204 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
19680c48 | 2205 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2206 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2207 | |
19680c48 EG |
2208 | bnx2x_calc_fc_adv(bp); |
2209 | } else | |
f5372251 | 2210 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2211 | } |
a2fbb9ea | 2212 | |
c18487ee YR |
2213 | static void bnx2x__link_reset(struct bnx2x *bp) |
2214 | { | |
19680c48 | 2215 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2216 | bnx2x_acquire_phy_lock(bp); |
589abe3a | 2217 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
4a37fb66 | 2218 | bnx2x_release_phy_lock(bp); |
19680c48 | 2219 | } else |
f5372251 | 2220 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2221 | } |
a2fbb9ea | 2222 | |
a22f0788 | 2223 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2224 | { |
2145a920 | 2225 | u8 rc = 0; |
a2fbb9ea | 2226 | |
2145a920 VZ |
2227 | if (!BP_NOMCP(bp)) { |
2228 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2229 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2230 | is_serdes); | |
2145a920 VZ |
2231 | bnx2x_release_phy_lock(bp); |
2232 | } else | |
2233 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2234 | |
c18487ee YR |
2235 | return rc; |
2236 | } | |
a2fbb9ea | 2237 | |
8a1c38d1 | 2238 | static void bnx2x_init_port_minmax(struct bnx2x *bp) |
34f80b04 | 2239 | { |
8a1c38d1 EG |
2240 | u32 r_param = bp->link_vars.line_speed / 8; |
2241 | u32 fair_periodic_timeout_usec; | |
2242 | u32 t_fair; | |
34f80b04 | 2243 | |
8a1c38d1 EG |
2244 | memset(&(bp->cmng.rs_vars), 0, |
2245 | sizeof(struct rate_shaping_vars_per_port)); | |
2246 | memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); | |
34f80b04 | 2247 | |
8a1c38d1 EG |
2248 | /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ |
2249 | bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; | |
34f80b04 | 2250 | |
8a1c38d1 EG |
2251 | /* this is the threshold below which no timer arming will occur |
2252 | 1.25 coefficient is for the threshold to be a little bigger | |
2253 | than the real time, to compensate for timer in-accuracy */ | |
2254 | bp->cmng.rs_vars.rs_threshold = | |
34f80b04 EG |
2255 | (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; |
2256 | ||
8a1c38d1 EG |
2257 | /* resolution of fairness timer */ |
2258 | fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; | |
2259 | /* for 10G it is 1000usec. for 1G it is 10000usec. */ | |
2260 | t_fair = T_FAIR_COEF / bp->link_vars.line_speed; | |
34f80b04 | 2261 | |
8a1c38d1 EG |
2262 | /* this is the threshold below which we won't arm the timer anymore */ |
2263 | bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; | |
34f80b04 | 2264 | |
8a1c38d1 EG |
2265 | /* we multiply by 1e3/8 to get bytes/msec. |
2266 | We don't want the credits to pass a credit | |
2267 | of the t_fair*FAIR_MEM (algorithm resolution) */ | |
2268 | bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; | |
2269 | /* since each tick is 4 usec */ | |
2270 | bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; | |
34f80b04 EG |
2271 | } |
2272 | ||
2691d51d EG |
2273 | /* Calculates the sum of vn_min_rates. |
2274 | It's needed for further normalizing of the min_rates. | |
2275 | Returns: | |
2276 | sum of vn_min_rates. | |
2277 | or | |
2278 | 0 - if all the min_rates are 0. | |
2279 | In the later case fainess algorithm should be deactivated. | |
2280 | If not all min_rates are zero then those that are zeroes will be set to 1. | |
2281 | */ | |
2282 | static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) | |
2283 | { | |
2284 | int all_zero = 1; | |
2691d51d EG |
2285 | int vn; |
2286 | ||
2287 | bp->vn_weight_sum = 0; | |
3395a033 | 2288 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2289 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2290 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2291 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2292 | ||
2293 | /* Skip hidden vns */ | |
2294 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
2295 | continue; | |
2296 | ||
2297 | /* If min rate is zero - set it to 1 */ | |
2298 | if (!vn_min_rate) | |
2299 | vn_min_rate = DEF_MIN_RATE; | |
2300 | else | |
2301 | all_zero = 0; | |
2302 | ||
2303 | bp->vn_weight_sum += vn_min_rate; | |
2304 | } | |
2305 | ||
30ae438b DK |
2306 | /* if ETS or all min rates are zeros - disable fairness */ |
2307 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
2308 | bp->cmng.flags.cmng_enables &= | |
2309 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | |
2310 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2311 | } else if (all_zero) { | |
b015e3d1 EG |
2312 | bp->cmng.flags.cmng_enables &= |
2313 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | |
2314 | DP(NETIF_MSG_IFUP, "All MIN values are zeroes" | |
2315 | " fairness will be disabled\n"); | |
2316 | } else | |
2317 | bp->cmng.flags.cmng_enables |= | |
2318 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | |
2691d51d EG |
2319 | } |
2320 | ||
3395a033 DK |
2321 | /* returns func by VN for current port */ |
2322 | static inline int func_by_vn(struct bnx2x *bp, int vn) | |
2323 | { | |
2324 | return 2 * vn + BP_PORT(bp); | |
2325 | } | |
2326 | ||
f2e0899f | 2327 | static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) |
34f80b04 EG |
2328 | { |
2329 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2330 | struct fairness_vars_per_vn m_fair_vn; | |
f2e0899f | 2331 | u32 vn_cfg = bp->mf_config[vn]; |
3395a033 | 2332 | int func = func_by_vn(bp, vn); |
34f80b04 EG |
2333 | u16 vn_min_rate, vn_max_rate; |
2334 | int i; | |
2335 | ||
2336 | /* If function is hidden - set min and max to zeroes */ | |
2337 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { | |
2338 | vn_min_rate = 0; | |
2339 | vn_max_rate = 0; | |
2340 | ||
2341 | } else { | |
faa6fcbb DK |
2342 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2343 | ||
34f80b04 EG |
2344 | vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2345 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
faa6fcbb DK |
2346 | /* If fairness is enabled (not all min rates are zeroes) and |
2347 | if current min rate is zero - set it to 1. | |
2348 | This is a requirement of the algorithm. */ | |
f2e0899f | 2349 | if (bp->vn_weight_sum && (vn_min_rate == 0)) |
34f80b04 | 2350 | vn_min_rate = DEF_MIN_RATE; |
faa6fcbb DK |
2351 | |
2352 | if (IS_MF_SI(bp)) | |
2353 | /* maxCfg in percents of linkspeed */ | |
2354 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
2355 | else | |
2356 | /* maxCfg is absolute in 100Mb units */ | |
2357 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2358 | } |
f85582f8 | 2359 | |
8a1c38d1 | 2360 | DP(NETIF_MSG_IFUP, |
b015e3d1 | 2361 | "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", |
8a1c38d1 | 2362 | func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); |
34f80b04 EG |
2363 | |
2364 | memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); | |
2365 | memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); | |
2366 | ||
2367 | /* global vn counter - maximal Mbps for this vn */ | |
2368 | m_rs_vn.vn_counter.rate = vn_max_rate; | |
2369 | ||
2370 | /* quota - number of bytes transmitted in this period */ | |
2371 | m_rs_vn.vn_counter.quota = | |
2372 | (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2373 | ||
8a1c38d1 | 2374 | if (bp->vn_weight_sum) { |
34f80b04 EG |
2375 | /* credit for each period of the fairness algorithm: |
2376 | number of bytes in T_FAIR (the vn share the port rate). | |
8a1c38d1 EG |
2377 | vn_weight_sum should not be larger than 10000, thus |
2378 | T_FAIR_COEF / (8 * vn_weight_sum) will always be greater | |
2379 | than zero */ | |
34f80b04 | 2380 | m_fair_vn.vn_credit_delta = |
cdaa7cb8 VZ |
2381 | max_t(u32, (vn_min_rate * (T_FAIR_COEF / |
2382 | (8 * bp->vn_weight_sum))), | |
ff80ee02 DK |
2383 | (bp->cmng.fair_vars.fair_threshold + |
2384 | MIN_ABOVE_THRESH)); | |
cdaa7cb8 | 2385 | DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", |
34f80b04 EG |
2386 | m_fair_vn.vn_credit_delta); |
2387 | } | |
2388 | ||
34f80b04 EG |
2389 | /* Store it to internal memory */ |
2390 | for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) | |
2391 | REG_WR(bp, BAR_XSTRORM_INTMEM + | |
2392 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, | |
2393 | ((u32 *)(&m_rs_vn))[i]); | |
2394 | ||
2395 | for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) | |
2396 | REG_WR(bp, BAR_XSTRORM_INTMEM + | |
2397 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, | |
2398 | ((u32 *)(&m_fair_vn))[i]); | |
2399 | } | |
f85582f8 | 2400 | |
523224a3 DK |
2401 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2402 | { | |
2403 | if (CHIP_REV_IS_SLOW(bp)) | |
2404 | return CMNG_FNS_NONE; | |
fb3bff17 | 2405 | if (IS_MF(bp)) |
523224a3 DK |
2406 | return CMNG_FNS_MINMAX; |
2407 | ||
2408 | return CMNG_FNS_NONE; | |
2409 | } | |
2410 | ||
2ae17f66 | 2411 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2412 | { |
0793f83f | 2413 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2414 | |
2415 | if (BP_NOMCP(bp)) | |
2416 | return; /* what should be the default bvalue in this case */ | |
2417 | ||
0793f83f DK |
2418 | /* For 2 port configuration the absolute function number formula |
2419 | * is: | |
2420 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2421 | * | |
2422 | * and there are 4 functions per port | |
2423 | * | |
2424 | * For 4 port configuration it is | |
2425 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2426 | * | |
2427 | * and there are 2 functions per port | |
2428 | */ | |
3395a033 | 2429 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2430 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2431 | ||
2432 | if (func >= E1H_FUNC_MAX) | |
2433 | break; | |
2434 | ||
f2e0899f | 2435 | bp->mf_config[vn] = |
523224a3 DK |
2436 | MF_CFG_RD(bp, func_mf_config[func].config); |
2437 | } | |
2438 | } | |
2439 | ||
2440 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2441 | { | |
2442 | ||
2443 | if (cmng_type == CMNG_FNS_MINMAX) { | |
2444 | int vn; | |
2445 | ||
2446 | /* clear cmng_enables */ | |
2447 | bp->cmng.flags.cmng_enables = 0; | |
2448 | ||
2449 | /* read mf conf from shmem */ | |
2450 | if (read_cfg) | |
2451 | bnx2x_read_mf_cfg(bp); | |
2452 | ||
2453 | /* Init rate shaping and fairness contexts */ | |
2454 | bnx2x_init_port_minmax(bp); | |
2455 | ||
2456 | /* vn_weight_sum and enable fairness if not 0 */ | |
2457 | bnx2x_calc_vn_weight_sum(bp); | |
2458 | ||
2459 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2460 | if (bp->port.pmf) |
3395a033 | 2461 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
c4154f25 | 2462 | bnx2x_init_vn_minmax(bp, vn); |
523224a3 DK |
2463 | |
2464 | /* always enable rate shaping and fairness */ | |
2465 | bp->cmng.flags.cmng_enables |= | |
2466 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; | |
2467 | if (!bp->vn_weight_sum) | |
2468 | DP(NETIF_MSG_IFUP, "All MIN values are zeroes" | |
2469 | " fairness will be disabled\n"); | |
2470 | return; | |
2471 | } | |
2472 | ||
2473 | /* rate shaping and fairness are disabled */ | |
2474 | DP(NETIF_MSG_IFUP, | |
2475 | "rate shaping and fairness are disabled\n"); | |
2476 | } | |
34f80b04 | 2477 | |
523224a3 DK |
2478 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) |
2479 | { | |
523224a3 DK |
2480 | int func; |
2481 | int vn; | |
2482 | ||
2483 | /* Set the attention towards other drivers on the same port */ | |
3395a033 DK |
2484 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
2485 | if (vn == BP_VN(bp)) | |
523224a3 DK |
2486 | continue; |
2487 | ||
3395a033 | 2488 | func = func_by_vn(bp, vn); |
523224a3 DK |
2489 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + |
2490 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); | |
2491 | } | |
2492 | } | |
8a1c38d1 | 2493 | |
c18487ee YR |
2494 | /* This function is called upon link interrupt */ |
2495 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2496 | { | |
bb2a0f7a YG |
2497 | /* Make sure that we are synced with the current statistics */ |
2498 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2499 | ||
c18487ee | 2500 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2501 | |
bb2a0f7a YG |
2502 | if (bp->link_vars.link_up) { |
2503 | ||
1c06328c | 2504 | /* dropless flow control */ |
f2e0899f | 2505 | if (!CHIP_IS_E1(bp) && bp->dropless_fc) { |
1c06328c EG |
2506 | int port = BP_PORT(bp); |
2507 | u32 pause_enabled = 0; | |
2508 | ||
2509 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2510 | pause_enabled = 1; | |
2511 | ||
2512 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
ca00392c | 2513 | USTORM_ETH_PAUSE_ENABLED_OFFSET(port), |
1c06328c EG |
2514 | pause_enabled); |
2515 | } | |
2516 | ||
619c5cb6 | 2517 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2518 | struct host_port_stats *pstats; |
2519 | ||
2520 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2521 | /* reset old mac stats */ |
bb2a0f7a YG |
2522 | memset(&(pstats->mac_stx[0]), 0, |
2523 | sizeof(struct mac_stx)); | |
2524 | } | |
f34d28ea | 2525 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2526 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2527 | } | |
2528 | ||
f2e0899f DK |
2529 | if (bp->link_vars.link_up && bp->link_vars.line_speed) { |
2530 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
8a1c38d1 | 2531 | |
f2e0899f DK |
2532 | if (cmng_fns != CMNG_FNS_NONE) { |
2533 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2534 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2535 | } else | |
2536 | /* rate shaping and fairness are disabled */ | |
2537 | DP(NETIF_MSG_IFUP, | |
2538 | "single function mode without fairness\n"); | |
34f80b04 | 2539 | } |
9fdc3e95 | 2540 | |
2ae17f66 VZ |
2541 | __bnx2x_link_report(bp); |
2542 | ||
9fdc3e95 DK |
2543 | if (IS_MF(bp)) |
2544 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2545 | } |
a2fbb9ea | 2546 | |
9f6c9258 | 2547 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2548 | { |
2ae17f66 | 2549 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2550 | return; |
a2fbb9ea | 2551 | |
c18487ee | 2552 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2553 | |
bb2a0f7a YG |
2554 | if (bp->link_vars.link_up) |
2555 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2556 | else | |
2557 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2558 | ||
c18487ee YR |
2559 | /* indicate link status */ |
2560 | bnx2x_link_report(bp); | |
a2fbb9ea | 2561 | } |
a2fbb9ea | 2562 | |
34f80b04 EG |
2563 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2564 | { | |
2565 | int port = BP_PORT(bp); | |
2566 | u32 val; | |
2567 | ||
2568 | bp->port.pmf = 1; | |
2569 | DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); | |
2570 | ||
3deb8167 YR |
2571 | /* |
2572 | * We need the mb() to ensure the ordering between the writing to | |
2573 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2574 | */ | |
2575 | smp_mb(); | |
2576 | ||
2577 | /* queue a periodic task */ | |
2578 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2579 | ||
ef01854e DK |
2580 | bnx2x_dcbx_pmf_update(bp); |
2581 | ||
34f80b04 | 2582 | /* enable nig attention */ |
3395a033 | 2583 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
2584 | if (bp->common.int_block == INT_BLOCK_HC) { |
2585 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2586 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2587 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2588 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2589 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2590 | } | |
bb2a0f7a YG |
2591 | |
2592 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2593 | } |
2594 | ||
c18487ee | 2595 | /* end of Link */ |
a2fbb9ea ET |
2596 | |
2597 | /* slow path */ | |
2598 | ||
2599 | /* | |
2600 | * General service functions | |
2601 | */ | |
2602 | ||
2691d51d | 2603 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 2604 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 2605 | { |
f2e0899f | 2606 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 2607 | u32 seq; |
2691d51d EG |
2608 | u32 rc = 0; |
2609 | u32 cnt = 1; | |
2610 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
2611 | ||
c4ff7cbf | 2612 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 2613 | seq = ++bp->fw_seq; |
f2e0899f DK |
2614 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
2615 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
2616 | ||
754a2f52 DK |
2617 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
2618 | (command | seq), param); | |
2691d51d EG |
2619 | |
2620 | do { | |
2621 | /* let the FW do it's magic ... */ | |
2622 | msleep(delay); | |
2623 | ||
f2e0899f | 2624 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 2625 | |
c4ff7cbf EG |
2626 | /* Give the FW up to 5 second (500*10ms) */ |
2627 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
2628 | |
2629 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
2630 | cnt*delay, rc, seq); | |
2631 | ||
2632 | /* is this a reply to our command? */ | |
2633 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
2634 | rc &= FW_MSG_CODE_MASK; | |
2635 | else { | |
2636 | /* FW BUG! */ | |
2637 | BNX2X_ERR("FW failed to respond!\n"); | |
2638 | bnx2x_fw_dump(bp); | |
2639 | rc = 0; | |
2640 | } | |
c4ff7cbf | 2641 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
2642 | |
2643 | return rc; | |
2644 | } | |
2645 | ||
ec6ba945 VZ |
2646 | static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp) |
2647 | { | |
2648 | #ifdef BCM_CNIC | |
619c5cb6 VZ |
2649 | /* Statistics are not supported for CNIC Clients at the moment */ |
2650 | if (IS_FCOE_FP(fp)) | |
ec6ba945 VZ |
2651 | return false; |
2652 | #endif | |
2653 | return true; | |
2654 | } | |
2655 | ||
619c5cb6 VZ |
2656 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
2657 | { | |
2658 | if (CHIP_IS_E1x(bp)) { | |
2659 | struct tstorm_eth_function_common_config tcfg = {0}; | |
2660 | ||
2661 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
2662 | } | |
2663 | ||
2664 | /* Enable the function in the FW */ | |
2665 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
2666 | storm_memset_func_en(bp, p->func_id, 1); | |
2667 | ||
2668 | /* spq */ | |
2669 | if (p->func_flgs & FUNC_FLG_SPQ) { | |
2670 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); | |
2671 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
2672 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
2673 | } | |
2674 | } | |
2675 | ||
6383c0b3 AE |
2676 | /** |
2677 | * bnx2x_get_tx_only_flags - Return common flags | |
2678 | * | |
2679 | * @bp device handle | |
2680 | * @fp queue handle | |
2681 | * @zero_stats TRUE if statistics zeroing is needed | |
2682 | * | |
2683 | * Return the flags that are common for the Tx-only and not normal connections. | |
2684 | */ | |
2685 | static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, | |
2686 | struct bnx2x_fastpath *fp, | |
2687 | bool zero_stats) | |
28912902 | 2688 | { |
619c5cb6 VZ |
2689 | unsigned long flags = 0; |
2690 | ||
2691 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
2692 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 2693 | |
6383c0b3 AE |
2694 | /* tx only connections collect statistics (on the same index as the |
2695 | * parent connection). The statistics are zeroed when the parent | |
2696 | * connection is initialized. | |
2697 | */ | |
2698 | if (stat_counter_valid(bp, fp)) { | |
2699 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
2700 | if (zero_stats) | |
2701 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
2702 | } | |
2703 | ||
2704 | return flags; | |
2705 | } | |
2706 | ||
2707 | static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, | |
2708 | struct bnx2x_fastpath *fp, | |
2709 | bool leading) | |
2710 | { | |
2711 | unsigned long flags = 0; | |
2712 | ||
619c5cb6 VZ |
2713 | /* calculate other queue flags */ |
2714 | if (IS_MF_SD(bp)) | |
2715 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 2716 | |
619c5cb6 VZ |
2717 | if (IS_FCOE_FP(fp)) |
2718 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); | |
523224a3 | 2719 | |
f5219d8e | 2720 | if (!fp->disable_tpa) { |
619c5cb6 | 2721 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e VZ |
2722 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
2723 | } | |
619c5cb6 | 2724 | |
619c5cb6 VZ |
2725 | if (leading) { |
2726 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
2727 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
2728 | } | |
523224a3 | 2729 | |
619c5cb6 VZ |
2730 | /* Always set HW VLAN stripping */ |
2731 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 2732 | |
6383c0b3 AE |
2733 | |
2734 | return flags | bnx2x_get_common_flags(bp, fp, true); | |
523224a3 DK |
2735 | } |
2736 | ||
619c5cb6 | 2737 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
2738 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
2739 | u8 cos) | |
619c5cb6 VZ |
2740 | { |
2741 | gen_init->stat_id = bnx2x_stats_id(fp); | |
2742 | gen_init->spcl_id = fp->cl_id; | |
2743 | ||
2744 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
2745 | if (IS_FCOE_FP(fp)) | |
2746 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
2747 | else | |
2748 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
2749 | |
2750 | gen_init->cos = cos; | |
619c5cb6 VZ |
2751 | } |
2752 | ||
2753 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 2754 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 2755 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 2756 | { |
619c5cb6 | 2757 | u8 max_sge = 0; |
523224a3 DK |
2758 | u16 sge_sz = 0; |
2759 | u16 tpa_agg_size = 0; | |
2760 | ||
523224a3 | 2761 | if (!fp->disable_tpa) { |
dfacf138 DK |
2762 | pause->sge_th_lo = SGE_TH_LO(bp); |
2763 | pause->sge_th_hi = SGE_TH_HI(bp); | |
2764 | ||
2765 | /* validate SGE ring has enough to cross high threshold */ | |
2766 | WARN_ON(bp->dropless_fc && | |
2767 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
2768 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
2769 | ||
523224a3 DK |
2770 | tpa_agg_size = min_t(u32, |
2771 | (min_t(u32, 8, MAX_SKB_FRAGS) * | |
2772 | SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); | |
2773 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> | |
2774 | SGE_PAGE_SHIFT; | |
2775 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
2776 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
2777 | sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, | |
2778 | 0xffff); | |
2779 | } | |
2780 | ||
2781 | /* pause - not for e1 */ | |
2782 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
2783 | pause->bd_th_lo = BD_TH_LO(bp); |
2784 | pause->bd_th_hi = BD_TH_HI(bp); | |
2785 | ||
2786 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
2787 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
2788 | /* | |
2789 | * validate that rings have enough entries to cross | |
2790 | * high thresholds | |
2791 | */ | |
2792 | WARN_ON(bp->dropless_fc && | |
2793 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
2794 | bp->rx_ring_size); | |
2795 | WARN_ON(bp->dropless_fc && | |
2796 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
2797 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 2798 | |
523224a3 DK |
2799 | pause->pri_map = 1; |
2800 | } | |
2801 | ||
2802 | /* rxq setup */ | |
523224a3 DK |
2803 | rxq_init->dscr_map = fp->rx_desc_mapping; |
2804 | rxq_init->sge_map = fp->rx_sge_mapping; | |
2805 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
2806 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 2807 | |
619c5cb6 VZ |
2808 | /* This should be a maximum number of data bytes that may be |
2809 | * placed on the BD (not including paddings). | |
2810 | */ | |
2811 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN - | |
2812 | IP_HEADER_ALIGNMENT_PADDING; | |
a8c94b91 | 2813 | |
523224a3 | 2814 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
2815 | rxq_init->tpa_agg_sz = tpa_agg_size; |
2816 | rxq_init->sge_buf_sz = sge_sz; | |
2817 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 VZ |
2818 | rxq_init->rss_engine_id = BP_FUNC(bp); |
2819 | ||
2820 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
2821 | * | |
2822 | * For PF Clients it should be the maximum avaliable number. | |
2823 | * VF driver(s) may want to define it to a smaller value. | |
2824 | */ | |
dfacf138 | 2825 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 2826 | |
523224a3 DK |
2827 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
2828 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
2829 | ||
ec6ba945 VZ |
2830 | if (IS_FCOE_FP(fp)) |
2831 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
2832 | else | |
6383c0b3 | 2833 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
523224a3 DK |
2834 | } |
2835 | ||
619c5cb6 | 2836 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
2837 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
2838 | u8 cos) | |
523224a3 | 2839 | { |
6383c0b3 AE |
2840 | txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; |
2841 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; | |
523224a3 DK |
2842 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
2843 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 2844 | |
619c5cb6 VZ |
2845 | /* |
2846 | * set the tss leading client id for TX classfication == | |
2847 | * leading RSS client id | |
2848 | */ | |
2849 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
2850 | ||
ec6ba945 VZ |
2851 | if (IS_FCOE_FP(fp)) { |
2852 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
2853 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
2854 | } | |
523224a3 DK |
2855 | } |
2856 | ||
8d96286a | 2857 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
2858 | { |
2859 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 DK |
2860 | struct event_ring_data eq_data = { {0} }; |
2861 | u16 flags; | |
2862 | ||
619c5cb6 | 2863 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2864 | /* reset IGU PF statistics: MSIX + ATTN */ |
2865 | /* PF */ | |
2866 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2867 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2868 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2869 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2870 | /* ATTN */ | |
2871 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
2872 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
2873 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
2874 | (CHIP_MODE_IS_4_PORT(bp) ? | |
2875 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
2876 | } | |
2877 | ||
523224a3 DK |
2878 | /* function setup flags */ |
2879 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | |
2880 | ||
619c5cb6 VZ |
2881 | /* This flag is relevant for E1x only. |
2882 | * E2 doesn't have a TPA configuration in a function level. | |
523224a3 | 2883 | */ |
619c5cb6 | 2884 | flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; |
523224a3 DK |
2885 | |
2886 | func_init.func_flgs = flags; | |
2887 | func_init.pf_id = BP_FUNC(bp); | |
2888 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
2889 | func_init.spq_map = bp->spq_mapping; |
2890 | func_init.spq_prod = bp->spq_prod_idx; | |
2891 | ||
2892 | bnx2x_func_init(bp, &func_init); | |
2893 | ||
2894 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
2895 | ||
2896 | /* | |
619c5cb6 VZ |
2897 | * Congestion management values depend on the link rate |
2898 | * There is no active link so initial link rate is set to 10 Gbps. | |
2899 | * When the link comes up The congestion management values are | |
2900 | * re-calculated according to the actual link rate. | |
2901 | */ | |
523224a3 DK |
2902 | bp->link_vars.line_speed = SPEED_10000; |
2903 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
2904 | ||
2905 | /* Only the PMF sets the HW */ | |
2906 | if (bp->port.pmf) | |
2907 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2908 | ||
523224a3 DK |
2909 | /* init Event Queue */ |
2910 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); | |
2911 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
2912 | eq_data.producer = bp->eq_prod; | |
2913 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
2914 | eq_data.sb_id = DEF_SB_ID; | |
2915 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
2916 | } | |
2917 | ||
2918 | ||
2919 | static void bnx2x_e1h_disable(struct bnx2x *bp) | |
2920 | { | |
2921 | int port = BP_PORT(bp); | |
2922 | ||
619c5cb6 | 2923 | bnx2x_tx_disable(bp); |
523224a3 DK |
2924 | |
2925 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
2926 | } |
2927 | ||
2928 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
2929 | { | |
2930 | int port = BP_PORT(bp); | |
2931 | ||
2932 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); | |
2933 | ||
2934 | /* Tx queue should be only reenabled */ | |
2935 | netif_tx_wake_all_queues(bp->dev); | |
2936 | ||
2937 | /* | |
2938 | * Should not call netif_carrier_on since it will be called if the link | |
2939 | * is up when checking for link state | |
2940 | */ | |
2941 | } | |
2942 | ||
0793f83f DK |
2943 | /* called due to MCP event (on pmf): |
2944 | * reread new bandwidth configuration | |
2945 | * configure FW | |
2946 | * notify others function about the change | |
2947 | */ | |
2948 | static inline void bnx2x_config_mf_bw(struct bnx2x *bp) | |
2949 | { | |
2950 | if (bp->link_vars.link_up) { | |
2951 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
2952 | bnx2x_link_sync_notify(bp); | |
2953 | } | |
2954 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2955 | } | |
2956 | ||
2957 | static inline void bnx2x_set_mf_bw(struct bnx2x *bp) | |
2958 | { | |
2959 | bnx2x_config_mf_bw(bp); | |
2960 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
2961 | } | |
2962 | ||
523224a3 DK |
2963 | static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) |
2964 | { | |
2965 | DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); | |
2966 | ||
2967 | if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { | |
2968 | ||
2969 | /* | |
2970 | * This is the only place besides the function initialization | |
2971 | * where the bp->flags can change so it is done without any | |
2972 | * locks | |
2973 | */ | |
f2e0899f | 2974 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
523224a3 DK |
2975 | DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); |
2976 | bp->flags |= MF_FUNC_DIS; | |
2977 | ||
2978 | bnx2x_e1h_disable(bp); | |
2979 | } else { | |
2980 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2981 | bp->flags &= ~MF_FUNC_DIS; | |
2982 | ||
2983 | bnx2x_e1h_enable(bp); | |
2984 | } | |
2985 | dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; | |
2986 | } | |
2987 | if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { | |
0793f83f | 2988 | bnx2x_config_mf_bw(bp); |
523224a3 DK |
2989 | dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; |
2990 | } | |
2991 | ||
2992 | /* Report results to MCP */ | |
2993 | if (dcc_event) | |
2994 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); | |
2995 | else | |
2996 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); | |
2997 | } | |
2998 | ||
2999 | /* must be called under the spq lock */ | |
3000 | static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) | |
3001 | { | |
3002 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3003 | ||
3004 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3005 | bp->spq_prod_bd = bp->spq; | |
3006 | bp->spq_prod_idx = 0; | |
3007 | DP(NETIF_MSG_TIMER, "end of spq\n"); | |
3008 | } else { | |
3009 | bp->spq_prod_bd++; | |
3010 | bp->spq_prod_idx++; | |
3011 | } | |
3012 | return next_spe; | |
3013 | } | |
3014 | ||
3015 | /* must be called under the spq lock */ | |
28912902 MC |
3016 | static inline void bnx2x_sp_prod_update(struct bnx2x *bp) |
3017 | { | |
3018 | int func = BP_FUNC(bp); | |
3019 | ||
53e51e2f VZ |
3020 | /* |
3021 | * Make sure that BD data is updated before writing the producer: | |
3022 | * BD data is written to the memory, the producer is read from the | |
3023 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3024 | */ | |
3025 | mb(); | |
28912902 | 3026 | |
523224a3 | 3027 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3028 | bp->spq_prod_idx); |
28912902 MC |
3029 | mmiowb(); |
3030 | } | |
3031 | ||
619c5cb6 VZ |
3032 | /** |
3033 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3034 | * | |
3035 | * @cmd: command to check | |
3036 | * @cmd_type: command type | |
3037 | */ | |
3038 | static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) | |
3039 | { | |
3040 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3041 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3042 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3043 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3044 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3045 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3046 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3047 | return true; | |
3048 | else | |
3049 | return false; | |
3050 | ||
3051 | } | |
3052 | ||
3053 | ||
3054 | /** | |
3055 | * bnx2x_sp_post - place a single command on an SP ring | |
3056 | * | |
3057 | * @bp: driver handle | |
3058 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3059 | * @cid: SW CID the command is related to | |
3060 | * @data_hi: command private data address (high 32 bits) | |
3061 | * @data_lo: command private data address (low 32 bits) | |
3062 | * @cmd_type: command type (e.g. NONE, ETH) | |
3063 | * | |
3064 | * SP data is handled as if it's always an address pair, thus data fields are | |
3065 | * not swapped to little endian in upper functions. Instead this function swaps | |
3066 | * data as if it's two u32 fields. | |
3067 | */ | |
9f6c9258 | 3068 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3069 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3070 | { |
28912902 | 3071 | struct eth_spe *spe; |
523224a3 | 3072 | u16 type; |
619c5cb6 | 3073 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3074 | |
a2fbb9ea ET |
3075 | #ifdef BNX2X_STOP_ON_ERROR |
3076 | if (unlikely(bp->panic)) | |
3077 | return -EIO; | |
3078 | #endif | |
3079 | ||
34f80b04 | 3080 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3081 | |
6e30dd4e VZ |
3082 | if (common) { |
3083 | if (!atomic_read(&bp->eq_spq_left)) { | |
3084 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3085 | spin_unlock_bh(&bp->spq_lock); | |
3086 | bnx2x_panic(); | |
3087 | return -EBUSY; | |
3088 | } | |
3089 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3090 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3091 | spin_unlock_bh(&bp->spq_lock); | |
3092 | bnx2x_panic(); | |
3093 | return -EBUSY; | |
a2fbb9ea | 3094 | } |
f1410647 | 3095 | |
28912902 MC |
3096 | spe = bnx2x_sp_get_next(bp); |
3097 | ||
a2fbb9ea | 3098 | /* CID needs port number to be encoded int it */ |
28912902 | 3099 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3100 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3101 | HW_CID(bp, cid)); | |
523224a3 | 3102 | |
619c5cb6 | 3103 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; |
a2fbb9ea | 3104 | |
523224a3 DK |
3105 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & |
3106 | SPE_HDR_FUNCTION_ID); | |
a2fbb9ea | 3107 | |
523224a3 DK |
3108 | spe->hdr.type = cpu_to_le16(type); |
3109 | ||
3110 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3111 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3112 | ||
d6cae238 VZ |
3113 | /* |
3114 | * It's ok if the actual decrement is issued towards the memory | |
3115 | * somewhere between the spin_lock and spin_unlock. Thus no | |
3116 | * more explict memory barrier is needed. | |
3117 | */ | |
3118 | if (common) | |
3119 | atomic_dec(&bp->eq_spq_left); | |
3120 | else | |
3121 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3122 | |
a2fbb9ea | 3123 | |
cdaa7cb8 | 3124 | DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, |
d6cae238 VZ |
3125 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " |
3126 | "type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3127 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3128 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3129 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3130 | HW_CID(bp, cid), data_hi, data_lo, type, |
3131 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3132 | |
28912902 | 3133 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3134 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3135 | return 0; |
3136 | } | |
3137 | ||
3138 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3139 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3140 | { |
72fd0718 | 3141 | u32 j, val; |
34f80b04 | 3142 | int rc = 0; |
a2fbb9ea ET |
3143 | |
3144 | might_sleep(); | |
72fd0718 | 3145 | for (j = 0; j < 1000; j++) { |
a2fbb9ea ET |
3146 | val = (1UL << 31); |
3147 | REG_WR(bp, GRCBASE_MCP + 0x9c, val); | |
3148 | val = REG_RD(bp, GRCBASE_MCP + 0x9c); | |
3149 | if (val & (1L << 31)) | |
3150 | break; | |
3151 | ||
3152 | msleep(5); | |
3153 | } | |
a2fbb9ea | 3154 | if (!(val & (1L << 31))) { |
19680c48 | 3155 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3156 | rc = -EBUSY; |
3157 | } | |
3158 | ||
3159 | return rc; | |
3160 | } | |
3161 | ||
4a37fb66 YG |
3162 | /* release split MCP access lock register */ |
3163 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3164 | { |
72fd0718 | 3165 | REG_WR(bp, GRCBASE_MCP + 0x9c, 0); |
a2fbb9ea ET |
3166 | } |
3167 | ||
523224a3 DK |
3168 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3169 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3170 | ||
a2fbb9ea ET |
3171 | static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
3172 | { | |
523224a3 | 3173 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3174 | u16 rc = 0; |
3175 | ||
3176 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3177 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3178 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3179 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3180 | } |
523224a3 DK |
3181 | |
3182 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3183 | bp->def_idx = def_sb->sp_sb.running_index; | |
3184 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3185 | } |
523224a3 DK |
3186 | |
3187 | /* Do not reorder: indecies reading should complete before handling */ | |
3188 | barrier(); | |
a2fbb9ea ET |
3189 | return rc; |
3190 | } | |
3191 | ||
3192 | /* | |
3193 | * slow path service functions | |
3194 | */ | |
3195 | ||
3196 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3197 | { | |
34f80b04 | 3198 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3199 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3200 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3201 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3202 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3203 | u32 aeu_mask; |
87942b46 | 3204 | u32 nig_mask = 0; |
f2e0899f | 3205 | u32 reg_addr; |
a2fbb9ea | 3206 | |
a2fbb9ea ET |
3207 | if (bp->attn_state & asserted) |
3208 | BNX2X_ERR("IGU ERROR\n"); | |
3209 | ||
3fcaf2e5 EG |
3210 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
3211 | aeu_mask = REG_RD(bp, aeu_addr); | |
3212 | ||
a2fbb9ea | 3213 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 3214 | aeu_mask, asserted); |
72fd0718 | 3215 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 3216 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 3217 | |
3fcaf2e5 EG |
3218 | REG_WR(bp, aeu_addr, aeu_mask); |
3219 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 3220 | |
3fcaf2e5 | 3221 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 3222 | bp->attn_state |= asserted; |
3fcaf2e5 | 3223 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
3224 | |
3225 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
3226 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 3227 | |
a5e9a7cf EG |
3228 | bnx2x_acquire_phy_lock(bp); |
3229 | ||
877e9aa4 | 3230 | /* save nig interrupt mask */ |
87942b46 | 3231 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 3232 | |
361c391e YR |
3233 | /* If nig_mask is not set, no need to call the update |
3234 | * function. | |
3235 | */ | |
3236 | if (nig_mask) { | |
3237 | REG_WR(bp, nig_int_mask_addr, 0); | |
3238 | ||
3239 | bnx2x_link_attn(bp); | |
3240 | } | |
a2fbb9ea ET |
3241 | |
3242 | /* handle unicore attn? */ | |
3243 | } | |
3244 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
3245 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
3246 | ||
3247 | if (asserted & GPIO_2_FUNC) | |
3248 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
3249 | ||
3250 | if (asserted & GPIO_3_FUNC) | |
3251 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
3252 | ||
3253 | if (asserted & GPIO_4_FUNC) | |
3254 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
3255 | ||
3256 | if (port == 0) { | |
3257 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
3258 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
3259 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
3260 | } | |
3261 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
3262 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
3263 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
3264 | } | |
3265 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
3266 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
3267 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
3268 | } | |
3269 | } else { | |
3270 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
3271 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
3272 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
3273 | } | |
3274 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
3275 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
3276 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
3277 | } | |
3278 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
3279 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
3280 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
3281 | } | |
3282 | } | |
3283 | ||
3284 | } /* if hardwired */ | |
3285 | ||
f2e0899f DK |
3286 | if (bp->common.int_block == INT_BLOCK_HC) |
3287 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
3288 | COMMAND_REG_ATTN_BITS_SET); | |
3289 | else | |
3290 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
3291 | ||
3292 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
3293 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
3294 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
3295 | |
3296 | /* now set back the mask */ | |
a5e9a7cf | 3297 | if (asserted & ATTN_NIG_FOR_FUNC) { |
87942b46 | 3298 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
3299 | bnx2x_release_phy_lock(bp); |
3300 | } | |
a2fbb9ea ET |
3301 | } |
3302 | ||
fd4ef40d EG |
3303 | static inline void bnx2x_fan_failure(struct bnx2x *bp) |
3304 | { | |
3305 | int port = BP_PORT(bp); | |
b7737c9b | 3306 | u32 ext_phy_config; |
fd4ef40d | 3307 | /* mark the failure */ |
b7737c9b YR |
3308 | ext_phy_config = |
3309 | SHMEM_RD(bp, | |
3310 | dev_info.port_hw_config[port].external_phy_config); | |
3311 | ||
3312 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
3313 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 3314 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 3315 | ext_phy_config); |
fd4ef40d EG |
3316 | |
3317 | /* log the failure */ | |
cdaa7cb8 VZ |
3318 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused" |
3319 | " the driver to shutdown the card to prevent permanent" | |
3320 | " damage. Please contact OEM Support for assistance\n"); | |
fd4ef40d | 3321 | } |
ab6ad5a4 | 3322 | |
877e9aa4 | 3323 | static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 3324 | { |
34f80b04 | 3325 | int port = BP_PORT(bp); |
877e9aa4 | 3326 | int reg_offset; |
d90d96ba | 3327 | u32 val; |
877e9aa4 | 3328 | |
34f80b04 EG |
3329 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
3330 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 3331 | |
34f80b04 | 3332 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
3333 | |
3334 | val = REG_RD(bp, reg_offset); | |
3335 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
3336 | REG_WR(bp, reg_offset, val); | |
3337 | ||
3338 | BNX2X_ERR("SPIO5 hw attention\n"); | |
3339 | ||
fd4ef40d | 3340 | /* Fan failure attention */ |
d90d96ba | 3341 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 3342 | bnx2x_fan_failure(bp); |
877e9aa4 | 3343 | } |
34f80b04 | 3344 | |
3deb8167 | 3345 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
3346 | bnx2x_acquire_phy_lock(bp); |
3347 | bnx2x_handle_module_detect_int(&bp->link_params); | |
3348 | bnx2x_release_phy_lock(bp); | |
3349 | } | |
3350 | ||
34f80b04 EG |
3351 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
3352 | ||
3353 | val = REG_RD(bp, reg_offset); | |
3354 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
3355 | REG_WR(bp, reg_offset, val); | |
3356 | ||
3357 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 3358 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
3359 | bnx2x_panic(); |
3360 | } | |
877e9aa4 ET |
3361 | } |
3362 | ||
3363 | static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) | |
3364 | { | |
3365 | u32 val; | |
3366 | ||
0626b899 | 3367 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
3368 | |
3369 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
3370 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
3371 | /* DORQ discard attention */ | |
3372 | if (val & 0x2) | |
3373 | BNX2X_ERR("FATAL error from DORQ\n"); | |
3374 | } | |
34f80b04 EG |
3375 | |
3376 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
3377 | ||
3378 | int port = BP_PORT(bp); | |
3379 | int reg_offset; | |
3380 | ||
3381 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
3382 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
3383 | ||
3384 | val = REG_RD(bp, reg_offset); | |
3385 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
3386 | REG_WR(bp, reg_offset, val); | |
3387 | ||
3388 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 3389 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
3390 | bnx2x_panic(); |
3391 | } | |
877e9aa4 ET |
3392 | } |
3393 | ||
3394 | static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) | |
3395 | { | |
3396 | u32 val; | |
3397 | ||
3398 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
3399 | ||
3400 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
3401 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
3402 | /* CFC error attention */ | |
3403 | if (val & 0x2) | |
3404 | BNX2X_ERR("FATAL error from CFC\n"); | |
3405 | } | |
3406 | ||
3407 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 3408 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 3409 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
3410 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
3411 | if (val & 0x18000) | |
3412 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
3413 | |
3414 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
3415 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
3416 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
3417 | } | |
877e9aa4 | 3418 | } |
34f80b04 EG |
3419 | |
3420 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
3421 | ||
3422 | int port = BP_PORT(bp); | |
3423 | int reg_offset; | |
3424 | ||
3425 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
3426 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
3427 | ||
3428 | val = REG_RD(bp, reg_offset); | |
3429 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
3430 | REG_WR(bp, reg_offset, val); | |
3431 | ||
3432 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 3433 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
3434 | bnx2x_panic(); |
3435 | } | |
877e9aa4 ET |
3436 | } |
3437 | ||
3438 | static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) | |
3439 | { | |
34f80b04 EG |
3440 | u32 val; |
3441 | ||
877e9aa4 ET |
3442 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
3443 | ||
34f80b04 EG |
3444 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
3445 | int func = BP_FUNC(bp); | |
3446 | ||
3447 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
f2e0899f DK |
3448 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
3449 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
3450 | val = SHMEM_RD(bp, | |
3451 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
2691d51d EG |
3452 | if (val & DRV_STATUS_DCC_EVENT_MASK) |
3453 | bnx2x_dcc_event(bp, | |
3454 | (val & DRV_STATUS_DCC_EVENT_MASK)); | |
0793f83f DK |
3455 | |
3456 | if (val & DRV_STATUS_SET_MF_BW) | |
3457 | bnx2x_set_mf_bw(bp); | |
3458 | ||
2691d51d | 3459 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
3460 | bnx2x_pmf_update(bp); |
3461 | ||
e4901dde | 3462 | if (bp->port.pmf && |
785b9b1a SR |
3463 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
3464 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
3465 | /* start dcbx state machine */ |
3466 | bnx2x_dcbx_set_params(bp, | |
3467 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
3deb8167 YR |
3468 | if (bp->link_vars.periodic_flags & |
3469 | PERIODIC_FLAGS_LINK_EVENT) { | |
3470 | /* sync with link */ | |
3471 | bnx2x_acquire_phy_lock(bp); | |
3472 | bp->link_vars.periodic_flags &= | |
3473 | ~PERIODIC_FLAGS_LINK_EVENT; | |
3474 | bnx2x_release_phy_lock(bp); | |
3475 | if (IS_MF(bp)) | |
3476 | bnx2x_link_sync_notify(bp); | |
3477 | bnx2x_link_report(bp); | |
3478 | } | |
3479 | /* Always call it here: bnx2x_link_report() will | |
3480 | * prevent the link indication duplication. | |
3481 | */ | |
3482 | bnx2x__link_status_update(bp); | |
34f80b04 | 3483 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
3484 | |
3485 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 3486 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
3487 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
3488 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
3489 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
3490 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
3491 | bnx2x_panic(); | |
3492 | ||
3493 | } else if (attn & BNX2X_MCP_ASSERT) { | |
3494 | ||
3495 | BNX2X_ERR("MCP assert!\n"); | |
3496 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 3497 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
3498 | |
3499 | } else | |
3500 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
3501 | } | |
3502 | ||
3503 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
3504 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
3505 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
3506 | val = CHIP_IS_E1(bp) ? 0 : |
3507 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
3508 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
3509 | } | |
3510 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
3511 | val = CHIP_IS_E1(bp) ? 0 : |
3512 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
3513 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
3514 | } | |
877e9aa4 | 3515 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
3516 | } |
3517 | } | |
3518 | ||
c9ee9206 VZ |
3519 | /* |
3520 | * Bits map: | |
3521 | * 0-7 - Engine0 load counter. | |
3522 | * 8-15 - Engine1 load counter. | |
3523 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
3524 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
3525 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
3526 | * on the engine | |
3527 | * 19 - Engine1 ONE_IS_LOADED. | |
3528 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
3529 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
3530 | * just the one belonging to its engine). | |
3531 | * | |
3532 | */ | |
3533 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
3534 | ||
3535 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
3536 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
3537 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
3538 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
3539 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
3540 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
3541 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
3542 | ||
3543 | /* | |
3544 | * Set the GLOBAL_RESET bit. | |
3545 | * | |
3546 | * Should be run under rtnl lock | |
3547 | */ | |
3548 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
3549 | { | |
3550 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3551 | ||
3552 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); | |
3553 | barrier(); | |
3554 | mmiowb(); | |
3555 | } | |
3556 | ||
3557 | /* | |
3558 | * Clear the GLOBAL_RESET bit. | |
3559 | * | |
3560 | * Should be run under rtnl lock | |
3561 | */ | |
3562 | static inline void bnx2x_clear_reset_global(struct bnx2x *bp) | |
3563 | { | |
3564 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3565 | ||
3566 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); | |
3567 | barrier(); | |
3568 | mmiowb(); | |
3569 | } | |
f85582f8 | 3570 | |
72fd0718 | 3571 | /* |
c9ee9206 VZ |
3572 | * Checks the GLOBAL_RESET bit. |
3573 | * | |
72fd0718 VZ |
3574 | * should be run under rtnl lock |
3575 | */ | |
c9ee9206 VZ |
3576 | static inline bool bnx2x_reset_is_global(struct bnx2x *bp) |
3577 | { | |
3578 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3579 | ||
3580 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
3581 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
3582 | } | |
3583 | ||
3584 | /* | |
3585 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
3586 | * | |
3587 | * Should be run under rtnl lock | |
3588 | */ | |
72fd0718 VZ |
3589 | static inline void bnx2x_set_reset_done(struct bnx2x *bp) |
3590 | { | |
c9ee9206 VZ |
3591 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3592 | u32 bit = BP_PATH(bp) ? | |
3593 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3594 | ||
3595 | /* Clear the bit */ | |
3596 | val &= ~bit; | |
3597 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
72fd0718 VZ |
3598 | barrier(); |
3599 | mmiowb(); | |
3600 | } | |
3601 | ||
3602 | /* | |
c9ee9206 VZ |
3603 | * Set RESET_IN_PROGRESS for the current engine. |
3604 | * | |
72fd0718 VZ |
3605 | * should be run under rtnl lock |
3606 | */ | |
c9ee9206 | 3607 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 3608 | { |
c9ee9206 VZ |
3609 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3610 | u32 bit = BP_PATH(bp) ? | |
3611 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3612 | ||
3613 | /* Set the bit */ | |
3614 | val |= bit; | |
3615 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
72fd0718 VZ |
3616 | barrier(); |
3617 | mmiowb(); | |
3618 | } | |
3619 | ||
3620 | /* | |
c9ee9206 | 3621 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
3622 | * should be run under rtnl lock |
3623 | */ | |
c9ee9206 | 3624 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 3625 | { |
c9ee9206 VZ |
3626 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3627 | u32 bit = engine ? | |
3628 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
3629 | ||
3630 | /* return false if bit is set */ | |
3631 | return (val & bit) ? false : true; | |
72fd0718 VZ |
3632 | } |
3633 | ||
3634 | /* | |
c9ee9206 VZ |
3635 | * Increment the load counter for the current engine. |
3636 | * | |
72fd0718 VZ |
3637 | * should be run under rtnl lock |
3638 | */ | |
c9ee9206 | 3639 | void bnx2x_inc_load_cnt(struct bnx2x *bp) |
72fd0718 | 3640 | { |
c9ee9206 VZ |
3641 | u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3642 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : | |
3643 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3644 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3645 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 VZ |
3646 | |
3647 | DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); | |
3648 | ||
c9ee9206 VZ |
3649 | /* get the current counter value */ |
3650 | val1 = (val & mask) >> shift; | |
3651 | ||
3652 | /* increment... */ | |
3653 | val1++; | |
3654 | ||
3655 | /* clear the old value */ | |
3656 | val &= ~mask; | |
3657 | ||
3658 | /* set the new one */ | |
3659 | val |= ((val1 << shift) & mask); | |
3660 | ||
3661 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
72fd0718 VZ |
3662 | barrier(); |
3663 | mmiowb(); | |
3664 | } | |
3665 | ||
c9ee9206 VZ |
3666 | /** |
3667 | * bnx2x_dec_load_cnt - decrement the load counter | |
3668 | * | |
3669 | * @bp: driver handle | |
3670 | * | |
3671 | * Should be run under rtnl lock. | |
3672 | * Decrements the load counter for the current engine. Returns | |
3673 | * the new counter value. | |
72fd0718 | 3674 | */ |
9f6c9258 | 3675 | u32 bnx2x_dec_load_cnt(struct bnx2x *bp) |
72fd0718 | 3676 | { |
c9ee9206 VZ |
3677 | u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3678 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : | |
3679 | BNX2X_PATH0_LOAD_CNT_MASK; | |
3680 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3681 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 VZ |
3682 | |
3683 | DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); | |
3684 | ||
c9ee9206 VZ |
3685 | /* get the current counter value */ |
3686 | val1 = (val & mask) >> shift; | |
3687 | ||
3688 | /* decrement... */ | |
3689 | val1--; | |
3690 | ||
3691 | /* clear the old value */ | |
3692 | val &= ~mask; | |
3693 | ||
3694 | /* set the new one */ | |
3695 | val |= ((val1 << shift) & mask); | |
3696 | ||
3697 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
72fd0718 VZ |
3698 | barrier(); |
3699 | mmiowb(); | |
3700 | ||
3701 | return val1; | |
3702 | } | |
3703 | ||
3704 | /* | |
c9ee9206 VZ |
3705 | * Read the load counter for the current engine. |
3706 | * | |
72fd0718 VZ |
3707 | * should be run under rtnl lock |
3708 | */ | |
c9ee9206 | 3709 | static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine) |
72fd0718 | 3710 | { |
c9ee9206 VZ |
3711 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
3712 | BNX2X_PATH0_LOAD_CNT_MASK); | |
3713 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
3714 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
3715 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3716 | ||
3717 | DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); | |
3718 | ||
3719 | val = (val & mask) >> shift; | |
3720 | ||
3721 | DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val); | |
3722 | ||
3723 | return val; | |
72fd0718 VZ |
3724 | } |
3725 | ||
c9ee9206 VZ |
3726 | /* |
3727 | * Reset the load counter for the current engine. | |
3728 | * | |
3729 | * should be run under rtnl lock | |
3730 | */ | |
72fd0718 VZ |
3731 | static inline void bnx2x_clear_load_cnt(struct bnx2x *bp) |
3732 | { | |
c9ee9206 VZ |
3733 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
3734 | u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : | |
3735 | BNX2X_PATH0_LOAD_CNT_MASK); | |
3736 | ||
3737 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); | |
72fd0718 VZ |
3738 | } |
3739 | ||
3740 | static inline void _print_next_block(int idx, const char *blk) | |
3741 | { | |
f1deab50 | 3742 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
3743 | } |
3744 | ||
c9ee9206 VZ |
3745 | static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, |
3746 | bool print) | |
72fd0718 VZ |
3747 | { |
3748 | int i = 0; | |
3749 | u32 cur_bit = 0; | |
3750 | for (i = 0; sig; i++) { | |
3751 | cur_bit = ((u32)0x1 << i); | |
3752 | if (sig & cur_bit) { | |
3753 | switch (cur_bit) { | |
3754 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
c9ee9206 VZ |
3755 | if (print) |
3756 | _print_next_block(par_num++, "BRB"); | |
72fd0718 VZ |
3757 | break; |
3758 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
c9ee9206 VZ |
3759 | if (print) |
3760 | _print_next_block(par_num++, "PARSER"); | |
72fd0718 VZ |
3761 | break; |
3762 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
c9ee9206 VZ |
3763 | if (print) |
3764 | _print_next_block(par_num++, "TSDM"); | |
72fd0718 VZ |
3765 | break; |
3766 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
c9ee9206 VZ |
3767 | if (print) |
3768 | _print_next_block(par_num++, | |
3769 | "SEARCHER"); | |
3770 | break; | |
3771 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
3772 | if (print) | |
3773 | _print_next_block(par_num++, "TCM"); | |
72fd0718 VZ |
3774 | break; |
3775 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3776 | if (print) |
3777 | _print_next_block(par_num++, "TSEMI"); | |
3778 | break; | |
3779 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
3780 | if (print) | |
3781 | _print_next_block(par_num++, "XPB"); | |
72fd0718 VZ |
3782 | break; |
3783 | } | |
3784 | ||
3785 | /* Clear the bit */ | |
3786 | sig &= ~cur_bit; | |
3787 | } | |
3788 | } | |
3789 | ||
3790 | return par_num; | |
3791 | } | |
3792 | ||
c9ee9206 VZ |
3793 | static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, |
3794 | bool *global, bool print) | |
72fd0718 VZ |
3795 | { |
3796 | int i = 0; | |
3797 | u32 cur_bit = 0; | |
3798 | for (i = 0; sig; i++) { | |
3799 | cur_bit = ((u32)0x1 << i); | |
3800 | if (sig & cur_bit) { | |
3801 | switch (cur_bit) { | |
c9ee9206 VZ |
3802 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
3803 | if (print) | |
3804 | _print_next_block(par_num++, "PBF"); | |
72fd0718 VZ |
3805 | break; |
3806 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
c9ee9206 VZ |
3807 | if (print) |
3808 | _print_next_block(par_num++, "QM"); | |
3809 | break; | |
3810 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
3811 | if (print) | |
3812 | _print_next_block(par_num++, "TM"); | |
72fd0718 VZ |
3813 | break; |
3814 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
c9ee9206 VZ |
3815 | if (print) |
3816 | _print_next_block(par_num++, "XSDM"); | |
3817 | break; | |
3818 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
3819 | if (print) | |
3820 | _print_next_block(par_num++, "XCM"); | |
72fd0718 VZ |
3821 | break; |
3822 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3823 | if (print) |
3824 | _print_next_block(par_num++, "XSEMI"); | |
72fd0718 VZ |
3825 | break; |
3826 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
c9ee9206 VZ |
3827 | if (print) |
3828 | _print_next_block(par_num++, | |
3829 | "DOORBELLQ"); | |
3830 | break; | |
3831 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
3832 | if (print) | |
3833 | _print_next_block(par_num++, "NIG"); | |
72fd0718 VZ |
3834 | break; |
3835 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 VZ |
3836 | if (print) |
3837 | _print_next_block(par_num++, | |
3838 | "VAUX PCI CORE"); | |
3839 | *global = true; | |
72fd0718 VZ |
3840 | break; |
3841 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
c9ee9206 VZ |
3842 | if (print) |
3843 | _print_next_block(par_num++, "DEBUG"); | |
72fd0718 VZ |
3844 | break; |
3845 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
c9ee9206 VZ |
3846 | if (print) |
3847 | _print_next_block(par_num++, "USDM"); | |
72fd0718 | 3848 | break; |
8736c826 VZ |
3849 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
3850 | if (print) | |
3851 | _print_next_block(par_num++, "UCM"); | |
3852 | break; | |
72fd0718 | 3853 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
c9ee9206 VZ |
3854 | if (print) |
3855 | _print_next_block(par_num++, "USEMI"); | |
72fd0718 VZ |
3856 | break; |
3857 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
c9ee9206 VZ |
3858 | if (print) |
3859 | _print_next_block(par_num++, "UPB"); | |
72fd0718 VZ |
3860 | break; |
3861 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
c9ee9206 VZ |
3862 | if (print) |
3863 | _print_next_block(par_num++, "CSDM"); | |
72fd0718 | 3864 | break; |
8736c826 VZ |
3865 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
3866 | if (print) | |
3867 | _print_next_block(par_num++, "CCM"); | |
3868 | break; | |
72fd0718 VZ |
3869 | } |
3870 | ||
3871 | /* Clear the bit */ | |
3872 | sig &= ~cur_bit; | |
3873 | } | |
3874 | } | |
3875 | ||
3876 | return par_num; | |
3877 | } | |
3878 | ||
c9ee9206 VZ |
3879 | static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, |
3880 | bool print) | |
72fd0718 VZ |
3881 | { |
3882 | int i = 0; | |
3883 | u32 cur_bit = 0; | |
3884 | for (i = 0; sig; i++) { | |
3885 | cur_bit = ((u32)0x1 << i); | |
3886 | if (sig & cur_bit) { | |
3887 | switch (cur_bit) { | |
3888 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
3889 | if (print) |
3890 | _print_next_block(par_num++, "CSEMI"); | |
72fd0718 VZ |
3891 | break; |
3892 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
c9ee9206 VZ |
3893 | if (print) |
3894 | _print_next_block(par_num++, "PXP"); | |
72fd0718 VZ |
3895 | break; |
3896 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
c9ee9206 VZ |
3897 | if (print) |
3898 | _print_next_block(par_num++, | |
72fd0718 VZ |
3899 | "PXPPCICLOCKCLIENT"); |
3900 | break; | |
3901 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
c9ee9206 VZ |
3902 | if (print) |
3903 | _print_next_block(par_num++, "CFC"); | |
72fd0718 VZ |
3904 | break; |
3905 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
c9ee9206 VZ |
3906 | if (print) |
3907 | _print_next_block(par_num++, "CDU"); | |
3908 | break; | |
3909 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
3910 | if (print) | |
3911 | _print_next_block(par_num++, "DMAE"); | |
72fd0718 VZ |
3912 | break; |
3913 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
c9ee9206 VZ |
3914 | if (print) |
3915 | _print_next_block(par_num++, "IGU"); | |
72fd0718 VZ |
3916 | break; |
3917 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
c9ee9206 VZ |
3918 | if (print) |
3919 | _print_next_block(par_num++, "MISC"); | |
72fd0718 VZ |
3920 | break; |
3921 | } | |
3922 | ||
3923 | /* Clear the bit */ | |
3924 | sig &= ~cur_bit; | |
3925 | } | |
3926 | } | |
3927 | ||
3928 | return par_num; | |
3929 | } | |
3930 | ||
c9ee9206 VZ |
3931 | static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, |
3932 | bool *global, bool print) | |
72fd0718 VZ |
3933 | { |
3934 | int i = 0; | |
3935 | u32 cur_bit = 0; | |
3936 | for (i = 0; sig; i++) { | |
3937 | cur_bit = ((u32)0x1 << i); | |
3938 | if (sig & cur_bit) { | |
3939 | switch (cur_bit) { | |
3940 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 VZ |
3941 | if (print) |
3942 | _print_next_block(par_num++, "MCP ROM"); | |
3943 | *global = true; | |
72fd0718 VZ |
3944 | break; |
3945 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 VZ |
3946 | if (print) |
3947 | _print_next_block(par_num++, | |
3948 | "MCP UMP RX"); | |
3949 | *global = true; | |
72fd0718 VZ |
3950 | break; |
3951 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 VZ |
3952 | if (print) |
3953 | _print_next_block(par_num++, | |
3954 | "MCP UMP TX"); | |
3955 | *global = true; | |
72fd0718 VZ |
3956 | break; |
3957 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
c9ee9206 VZ |
3958 | if (print) |
3959 | _print_next_block(par_num++, | |
3960 | "MCP SCPAD"); | |
3961 | *global = true; | |
72fd0718 VZ |
3962 | break; |
3963 | } | |
3964 | ||
3965 | /* Clear the bit */ | |
3966 | sig &= ~cur_bit; | |
3967 | } | |
3968 | } | |
3969 | ||
3970 | return par_num; | |
3971 | } | |
3972 | ||
8736c826 VZ |
3973 | static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, |
3974 | bool print) | |
3975 | { | |
3976 | int i = 0; | |
3977 | u32 cur_bit = 0; | |
3978 | for (i = 0; sig; i++) { | |
3979 | cur_bit = ((u32)0x1 << i); | |
3980 | if (sig & cur_bit) { | |
3981 | switch (cur_bit) { | |
3982 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
3983 | if (print) | |
3984 | _print_next_block(par_num++, "PGLUE_B"); | |
3985 | break; | |
3986 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
3987 | if (print) | |
3988 | _print_next_block(par_num++, "ATC"); | |
3989 | break; | |
3990 | } | |
3991 | ||
3992 | /* Clear the bit */ | |
3993 | sig &= ~cur_bit; | |
3994 | } | |
3995 | } | |
3996 | ||
3997 | return par_num; | |
3998 | } | |
3999 | ||
c9ee9206 | 4000 | static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
8736c826 | 4001 | u32 *sig) |
72fd0718 | 4002 | { |
8736c826 VZ |
4003 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4004 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4005 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4006 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4007 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 VZ |
4008 | int par_num = 0; |
4009 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " | |
8736c826 VZ |
4010 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " |
4011 | "[4]:0x%08x\n", | |
4012 | sig[0] & HW_PRTY_ASSERT_SET_0, | |
4013 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4014 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4015 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4016 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
c9ee9206 VZ |
4017 | if (print) |
4018 | netdev_err(bp->dev, | |
4019 | "Parity errors detected in blocks: "); | |
4020 | par_num = bnx2x_check_blocks_with_parity0( | |
8736c826 | 4021 | sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); |
c9ee9206 | 4022 | par_num = bnx2x_check_blocks_with_parity1( |
8736c826 | 4023 | sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); |
c9ee9206 | 4024 | par_num = bnx2x_check_blocks_with_parity2( |
8736c826 | 4025 | sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); |
c9ee9206 | 4026 | par_num = bnx2x_check_blocks_with_parity3( |
8736c826 VZ |
4027 | sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); |
4028 | par_num = bnx2x_check_blocks_with_parity4( | |
4029 | sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); | |
4030 | ||
c9ee9206 VZ |
4031 | if (print) |
4032 | pr_cont("\n"); | |
8736c826 | 4033 | |
72fd0718 VZ |
4034 | return true; |
4035 | } else | |
4036 | return false; | |
4037 | } | |
4038 | ||
c9ee9206 VZ |
4039 | /** |
4040 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
4041 | * | |
4042 | * @bp: driver handle | |
4043 | * @global: true if there was a global attention | |
4044 | * @print: show parity attention in syslog | |
4045 | */ | |
4046 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 4047 | { |
8736c826 | 4048 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
4049 | int port = BP_PORT(bp); |
4050 | ||
4051 | attn.sig[0] = REG_RD(bp, | |
4052 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
4053 | port*4); | |
4054 | attn.sig[1] = REG_RD(bp, | |
4055 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
4056 | port*4); | |
4057 | attn.sig[2] = REG_RD(bp, | |
4058 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
4059 | port*4); | |
4060 | attn.sig[3] = REG_RD(bp, | |
4061 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
4062 | port*4); | |
4063 | ||
8736c826 VZ |
4064 | if (!CHIP_IS_E1x(bp)) |
4065 | attn.sig[4] = REG_RD(bp, | |
4066 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
4067 | port*4); | |
4068 | ||
4069 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
4070 | } |
4071 | ||
f2e0899f DK |
4072 | |
4073 | static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) | |
4074 | { | |
4075 | u32 val; | |
4076 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
4077 | ||
4078 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
4079 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
4080 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
4081 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4082 | "ADDRESS_ERROR\n"); | |
4083 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) | |
4084 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4085 | "INCORRECT_RCV_BEHAVIOR\n"); | |
4086 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) | |
4087 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4088 | "WAS_ERROR_ATTN\n"); | |
4089 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) | |
4090 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4091 | "VF_LENGTH_VIOLATION_ATTN\n"); | |
4092 | if (val & | |
4093 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
4094 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4095 | "VF_GRC_SPACE_VIOLATION_ATTN\n"); | |
4096 | if (val & | |
4097 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
4098 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4099 | "VF_MSIX_BAR_VIOLATION_ATTN\n"); | |
4100 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) | |
4101 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4102 | "TCPL_ERROR_ATTN\n"); | |
4103 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) | |
4104 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4105 | "TCPL_IN_TWO_RCBS_ATTN\n"); | |
4106 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) | |
4107 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" | |
4108 | "CSSNOOP_FIFO_OVERFLOW\n"); | |
4109 | } | |
4110 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
4111 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
4112 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
4113 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
4114 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
4115 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
4116 | BNX2X_ERR("ATC_ATC_INT_STS_REG" | |
4117 | "_ATC_TCPL_TO_NOT_PEND\n"); | |
4118 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) | |
4119 | BNX2X_ERR("ATC_ATC_INT_STS_REG_" | |
4120 | "ATC_GPA_MULTIPLE_HITS\n"); | |
4121 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) | |
4122 | BNX2X_ERR("ATC_ATC_INT_STS_REG_" | |
4123 | "ATC_RCPL_TO_EMPTY_CNT\n"); | |
4124 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) | |
4125 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
4126 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
4127 | BNX2X_ERR("ATC_ATC_INT_STS_REG_" | |
4128 | "ATC_IREQ_LESS_THAN_STU\n"); | |
4129 | } | |
4130 | ||
4131 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4132 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
4133 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
4134 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4135 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
4136 | } | |
4137 | ||
4138 | } | |
4139 | ||
72fd0718 VZ |
4140 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
4141 | { | |
4142 | struct attn_route attn, *group_mask; | |
34f80b04 | 4143 | int port = BP_PORT(bp); |
877e9aa4 | 4144 | int index; |
a2fbb9ea ET |
4145 | u32 reg_addr; |
4146 | u32 val; | |
3fcaf2e5 | 4147 | u32 aeu_mask; |
c9ee9206 | 4148 | bool global = false; |
a2fbb9ea ET |
4149 | |
4150 | /* need to take HW lock because MCP or other port might also | |
4151 | try to handle this event */ | |
4a37fb66 | 4152 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 4153 | |
c9ee9206 VZ |
4154 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
4155 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 4156 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 4157 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
4158 | /* Disable HW interrupts */ |
4159 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
4160 | /* In case of parity errors don't handle attentions so that |
4161 | * other function would "see" parity errors. | |
4162 | */ | |
c9ee9206 VZ |
4163 | #else |
4164 | bnx2x_panic(); | |
4165 | #endif | |
4166 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
4167 | return; |
4168 | } | |
4169 | ||
a2fbb9ea ET |
4170 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
4171 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
4172 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
4173 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 4174 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4175 | attn.sig[4] = |
4176 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
4177 | else | |
4178 | attn.sig[4] = 0; | |
4179 | ||
4180 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
4181 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
4182 | |
4183 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
4184 | if (deasserted & (1 << index)) { | |
72fd0718 | 4185 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 4186 | |
f2e0899f DK |
4187 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x " |
4188 | "%08x %08x %08x\n", | |
4189 | index, | |
4190 | group_mask->sig[0], group_mask->sig[1], | |
4191 | group_mask->sig[2], group_mask->sig[3], | |
4192 | group_mask->sig[4]); | |
a2fbb9ea | 4193 | |
f2e0899f DK |
4194 | bnx2x_attn_int_deasserted4(bp, |
4195 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 4196 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 4197 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 4198 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 4199 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 4200 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 4201 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 4202 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 4203 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
4204 | } |
4205 | } | |
4206 | ||
4a37fb66 | 4207 | bnx2x_release_alr(bp); |
a2fbb9ea | 4208 | |
f2e0899f DK |
4209 | if (bp->common.int_block == INT_BLOCK_HC) |
4210 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4211 | COMMAND_REG_ATTN_BITS_CLR); | |
4212 | else | |
4213 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
4214 | |
4215 | val = ~deasserted; | |
f2e0899f DK |
4216 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
4217 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 4218 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 4219 | |
a2fbb9ea | 4220 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 4221 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
4222 | |
4223 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
4224 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
4225 | ||
3fcaf2e5 EG |
4226 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4227 | aeu_mask = REG_RD(bp, reg_addr); | |
4228 | ||
4229 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
4230 | aeu_mask, deasserted); | |
72fd0718 | 4231 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 4232 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4233 | |
3fcaf2e5 EG |
4234 | REG_WR(bp, reg_addr, aeu_mask); |
4235 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
4236 | |
4237 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
4238 | bp->attn_state &= ~deasserted; | |
4239 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
4240 | } | |
4241 | ||
4242 | static void bnx2x_attn_int(struct bnx2x *bp) | |
4243 | { | |
4244 | /* read local copy of bits */ | |
68d59484 EG |
4245 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
4246 | attn_bits); | |
4247 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
4248 | attn_bits_ack); | |
a2fbb9ea ET |
4249 | u32 attn_state = bp->attn_state; |
4250 | ||
4251 | /* look for changed bits */ | |
4252 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
4253 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
4254 | ||
4255 | DP(NETIF_MSG_HW, | |
4256 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
4257 | attn_bits, attn_ack, asserted, deasserted); | |
4258 | ||
4259 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 4260 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
4261 | |
4262 | /* handle bits that were raised */ | |
4263 | if (asserted) | |
4264 | bnx2x_attn_int_asserted(bp, asserted); | |
4265 | ||
4266 | if (deasserted) | |
4267 | bnx2x_attn_int_deasserted(bp, deasserted); | |
4268 | } | |
4269 | ||
619c5cb6 VZ |
4270 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
4271 | u16 index, u8 op, u8 update) | |
4272 | { | |
4273 | u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
4274 | ||
4275 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, | |
4276 | igu_addr); | |
4277 | } | |
4278 | ||
523224a3 DK |
4279 | static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
4280 | { | |
4281 | /* No memory barriers */ | |
4282 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
4283 | mmiowb(); /* keep prod updates ordered */ | |
4284 | } | |
4285 | ||
4286 | #ifdef BCM_CNIC | |
4287 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, | |
4288 | union event_ring_elem *elem) | |
4289 | { | |
619c5cb6 VZ |
4290 | u8 err = elem->message.error; |
4291 | ||
523224a3 | 4292 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
4293 | (cid < bp->cnic_eth_dev.starting_cid && |
4294 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
4295 | return 1; |
4296 | ||
4297 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
4298 | ||
619c5cb6 VZ |
4299 | if (unlikely(err)) { |
4300 | ||
523224a3 DK |
4301 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
4302 | cid); | |
4303 | bnx2x_panic_dump(bp); | |
4304 | } | |
619c5cb6 | 4305 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
4306 | return 0; |
4307 | } | |
4308 | #endif | |
4309 | ||
619c5cb6 VZ |
4310 | static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
4311 | { | |
4312 | struct bnx2x_mcast_ramrod_params rparam; | |
4313 | int rc; | |
4314 | ||
4315 | memset(&rparam, 0, sizeof(rparam)); | |
4316 | ||
4317 | rparam.mcast_obj = &bp->mcast_obj; | |
4318 | ||
4319 | netif_addr_lock_bh(bp->dev); | |
4320 | ||
4321 | /* Clear pending state for the last command */ | |
4322 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
4323 | ||
4324 | /* If there are pending mcast commands - send them */ | |
4325 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
4326 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
4327 | if (rc < 0) | |
4328 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
4329 | rc); | |
4330 | } | |
4331 | ||
4332 | netif_addr_unlock_bh(bp->dev); | |
4333 | } | |
4334 | ||
4335 | static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, | |
4336 | union event_ring_elem *elem) | |
4337 | { | |
4338 | unsigned long ramrod_flags = 0; | |
4339 | int rc = 0; | |
4340 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
4341 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
4342 | ||
4343 | /* Always push next commands out, don't wait here */ | |
4344 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
4345 | ||
4346 | switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { | |
4347 | case BNX2X_FILTER_MAC_PENDING: | |
4348 | #ifdef BCM_CNIC | |
4349 | if (cid == BNX2X_ISCSI_ETH_CID) | |
4350 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; | |
4351 | else | |
4352 | #endif | |
4353 | vlan_mac_obj = &bp->fp[cid].mac_obj; | |
4354 | ||
4355 | break; | |
619c5cb6 VZ |
4356 | case BNX2X_FILTER_MCAST_PENDING: |
4357 | /* This is only relevant for 57710 where multicast MACs are | |
4358 | * configured as unicast MACs using the same ramrod. | |
4359 | */ | |
4360 | bnx2x_handle_mcast_eqe(bp); | |
4361 | return; | |
4362 | default: | |
4363 | BNX2X_ERR("Unsupported classification command: %d\n", | |
4364 | elem->message.data.eth_event.echo); | |
4365 | return; | |
4366 | } | |
4367 | ||
4368 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
4369 | ||
4370 | if (rc < 0) | |
4371 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
4372 | else if (rc > 0) | |
4373 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
4374 | ||
4375 | } | |
4376 | ||
4377 | #ifdef BCM_CNIC | |
4378 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); | |
4379 | #endif | |
4380 | ||
4381 | static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) | |
4382 | { | |
4383 | netif_addr_lock_bh(bp->dev); | |
4384 | ||
4385 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
4386 | ||
4387 | /* Send rx_mode command again if was requested */ | |
4388 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
4389 | bnx2x_set_storm_rx_mode(bp); | |
4390 | #ifdef BCM_CNIC | |
4391 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, | |
4392 | &bp->sp_state)) | |
4393 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
4394 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
4395 | &bp->sp_state)) | |
4396 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
4397 | #endif | |
4398 | ||
4399 | netif_addr_unlock_bh(bp->dev); | |
4400 | } | |
4401 | ||
4402 | static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( | |
4403 | struct bnx2x *bp, u32 cid) | |
4404 | { | |
94f05b0f | 4405 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
619c5cb6 VZ |
4406 | #ifdef BCM_CNIC |
4407 | if (cid == BNX2X_FCOE_ETH_CID) | |
4408 | return &bnx2x_fcoe(bp, q_obj); | |
4409 | else | |
4410 | #endif | |
6383c0b3 | 4411 | return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); |
619c5cb6 VZ |
4412 | } |
4413 | ||
523224a3 DK |
4414 | static void bnx2x_eq_int(struct bnx2x *bp) |
4415 | { | |
4416 | u16 hw_cons, sw_cons, sw_prod; | |
4417 | union event_ring_elem *elem; | |
4418 | u32 cid; | |
4419 | u8 opcode; | |
4420 | int spqe_cnt = 0; | |
619c5cb6 VZ |
4421 | struct bnx2x_queue_sp_obj *q_obj; |
4422 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
4423 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
4424 | |
4425 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
4426 | ||
4427 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
4428 | * when we get the the next-page we nned to adjust so the loop | |
4429 | * condition below will be met. The next element is the size of a | |
4430 | * regular element and hence incrementing by 1 | |
4431 | */ | |
4432 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
4433 | hw_cons++; | |
4434 | ||
25985edc | 4435 | /* This function may never run in parallel with itself for a |
523224a3 DK |
4436 | * specific bp, thus there is no need in "paired" read memory |
4437 | * barrier here. | |
4438 | */ | |
4439 | sw_cons = bp->eq_cons; | |
4440 | sw_prod = bp->eq_prod; | |
4441 | ||
d6cae238 | 4442 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 4443 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
4444 | |
4445 | for (; sw_cons != hw_cons; | |
4446 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
4447 | ||
4448 | ||
4449 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; | |
4450 | ||
4451 | cid = SW_CID(elem->message.data.cfc_del_event.cid); | |
4452 | opcode = elem->message.opcode; | |
4453 | ||
4454 | ||
4455 | /* handle eq element */ | |
4456 | switch (opcode) { | |
4457 | case EVENT_RING_OPCODE_STAT_QUERY: | |
619c5cb6 VZ |
4458 | DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", |
4459 | bp->stats_comp++); | |
523224a3 | 4460 | /* nothing to do with stats comp */ |
d6cae238 | 4461 | goto next_spqe; |
523224a3 DK |
4462 | |
4463 | case EVENT_RING_OPCODE_CFC_DEL: | |
4464 | /* handle according to cid range */ | |
4465 | /* | |
4466 | * we may want to verify here that the bp state is | |
4467 | * HALTING | |
4468 | */ | |
d6cae238 | 4469 | DP(BNX2X_MSG_SP, |
523224a3 DK |
4470 | "got delete ramrod for MULTI[%d]\n", cid); |
4471 | #ifdef BCM_CNIC | |
4472 | if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
4473 | goto next_spqe; | |
4474 | #endif | |
619c5cb6 VZ |
4475 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
4476 | ||
4477 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
4478 | break; | |
4479 | ||
4480 | ||
523224a3 DK |
4481 | |
4482 | goto next_spqe; | |
e4901dde VZ |
4483 | |
4484 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
d6cae238 | 4485 | DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); |
6debea87 DK |
4486 | if (f_obj->complete_cmd(bp, f_obj, |
4487 | BNX2X_F_CMD_TX_STOP)) | |
4488 | break; | |
e4901dde VZ |
4489 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
4490 | goto next_spqe; | |
619c5cb6 | 4491 | |
e4901dde | 4492 | case EVENT_RING_OPCODE_START_TRAFFIC: |
d6cae238 | 4493 | DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); |
6debea87 DK |
4494 | if (f_obj->complete_cmd(bp, f_obj, |
4495 | BNX2X_F_CMD_TX_START)) | |
4496 | break; | |
e4901dde VZ |
4497 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
4498 | goto next_spqe; | |
619c5cb6 | 4499 | case EVENT_RING_OPCODE_FUNCTION_START: |
d6cae238 | 4500 | DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); |
619c5cb6 VZ |
4501 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
4502 | break; | |
4503 | ||
4504 | goto next_spqe; | |
4505 | ||
4506 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
d6cae238 | 4507 | DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); |
619c5cb6 VZ |
4508 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
4509 | break; | |
4510 | ||
4511 | goto next_spqe; | |
523224a3 DK |
4512 | } |
4513 | ||
4514 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
4515 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
4516 | BNX2X_STATE_OPEN): | |
4517 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 4518 | BNX2X_STATE_OPENING_WAIT4_PORT): |
619c5cb6 VZ |
4519 | cid = elem->message.data.eth_event.echo & |
4520 | BNX2X_SWCID_MASK; | |
d6cae238 | 4521 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
619c5cb6 VZ |
4522 | cid); |
4523 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
4524 | break; |
4525 | ||
619c5cb6 VZ |
4526 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
4527 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
4528 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 4529 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
4530 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
4531 | BNX2X_STATE_OPEN): | |
4532 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4533 | BNX2X_STATE_DIAG): | |
4534 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4535 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 4536 | DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); |
619c5cb6 | 4537 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
4538 | break; |
4539 | ||
619c5cb6 VZ |
4540 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
4541 | BNX2X_STATE_OPEN): | |
4542 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4543 | BNX2X_STATE_DIAG): | |
4544 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
4545 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 4546 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 4547 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
4548 | break; |
4549 | ||
619c5cb6 VZ |
4550 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
4551 | BNX2X_STATE_OPEN): | |
4552 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
4553 | BNX2X_STATE_DIAG): | |
4554 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 4555 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 4556 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 4557 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
4558 | break; |
4559 | default: | |
4560 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
4561 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
4562 | elem->message.opcode, bp->state); | |
523224a3 DK |
4563 | } |
4564 | next_spqe: | |
4565 | spqe_cnt++; | |
4566 | } /* for */ | |
4567 | ||
8fe23fbd | 4568 | smp_mb__before_atomic_inc(); |
6e30dd4e | 4569 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
4570 | |
4571 | bp->eq_cons = sw_cons; | |
4572 | bp->eq_prod = sw_prod; | |
4573 | /* Make sure that above mem writes were issued towards the memory */ | |
4574 | smp_wmb(); | |
4575 | ||
4576 | /* update producer */ | |
4577 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
4578 | } | |
4579 | ||
a2fbb9ea ET |
4580 | static void bnx2x_sp_task(struct work_struct *work) |
4581 | { | |
1cf167f2 | 4582 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea ET |
4583 | u16 status; |
4584 | ||
a2fbb9ea | 4585 | status = bnx2x_update_dsb_idx(bp); |
34f80b04 EG |
4586 | /* if (status == 0) */ |
4587 | /* BNX2X_ERR("spurious slowpath interrupt!\n"); */ | |
a2fbb9ea | 4588 | |
cdaa7cb8 | 4589 | DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); |
a2fbb9ea | 4590 | |
877e9aa4 | 4591 | /* HW attentions */ |
523224a3 | 4592 | if (status & BNX2X_DEF_SB_ATT_IDX) { |
a2fbb9ea | 4593 | bnx2x_attn_int(bp); |
523224a3 | 4594 | status &= ~BNX2X_DEF_SB_ATT_IDX; |
cdaa7cb8 VZ |
4595 | } |
4596 | ||
523224a3 DK |
4597 | /* SP events: STAT_QUERY and others */ |
4598 | if (status & BNX2X_DEF_SB_IDX) { | |
ec6ba945 VZ |
4599 | #ifdef BCM_CNIC |
4600 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 4601 | |
ec6ba945 | 4602 | if ((!NO_FCOE(bp)) && |
019dbb4c VZ |
4603 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
4604 | /* | |
4605 | * Prevent local bottom-halves from running as | |
4606 | * we are going to change the local NAPI list. | |
4607 | */ | |
4608 | local_bh_disable(); | |
ec6ba945 | 4609 | napi_schedule(&bnx2x_fcoe(bp, napi)); |
019dbb4c VZ |
4610 | local_bh_enable(); |
4611 | } | |
ec6ba945 | 4612 | #endif |
523224a3 DK |
4613 | /* Handle EQ completions */ |
4614 | bnx2x_eq_int(bp); | |
4615 | ||
4616 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
4617 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
4618 | ||
4619 | status &= ~BNX2X_DEF_SB_IDX; | |
cdaa7cb8 VZ |
4620 | } |
4621 | ||
4622 | if (unlikely(status)) | |
4623 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
4624 | status); | |
a2fbb9ea | 4625 | |
523224a3 DK |
4626 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, |
4627 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
a2fbb9ea ET |
4628 | } |
4629 | ||
9f6c9258 | 4630 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
4631 | { |
4632 | struct net_device *dev = dev_instance; | |
4633 | struct bnx2x *bp = netdev_priv(dev); | |
4634 | ||
523224a3 DK |
4635 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
4636 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
4637 | |
4638 | #ifdef BNX2X_STOP_ON_ERROR | |
4639 | if (unlikely(bp->panic)) | |
4640 | return IRQ_HANDLED; | |
4641 | #endif | |
4642 | ||
993ac7b5 MC |
4643 | #ifdef BCM_CNIC |
4644 | { | |
4645 | struct cnic_ops *c_ops; | |
4646 | ||
4647 | rcu_read_lock(); | |
4648 | c_ops = rcu_dereference(bp->cnic_ops); | |
4649 | if (c_ops) | |
4650 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
4651 | rcu_read_unlock(); | |
4652 | } | |
4653 | #endif | |
1cf167f2 | 4654 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
4655 | |
4656 | return IRQ_HANDLED; | |
4657 | } | |
4658 | ||
4659 | /* end of slow path */ | |
4660 | ||
619c5cb6 VZ |
4661 | |
4662 | void bnx2x_drv_pulse(struct bnx2x *bp) | |
4663 | { | |
4664 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
4665 | bp->fw_drv_pulse_wr_seq); | |
4666 | } | |
4667 | ||
4668 | ||
a2fbb9ea ET |
4669 | static void bnx2x_timer(unsigned long data) |
4670 | { | |
6383c0b3 | 4671 | u8 cos; |
a2fbb9ea ET |
4672 | struct bnx2x *bp = (struct bnx2x *) data; |
4673 | ||
4674 | if (!netif_running(bp->dev)) | |
4675 | return; | |
4676 | ||
a2fbb9ea ET |
4677 | if (poll) { |
4678 | struct bnx2x_fastpath *fp = &bp->fp[0]; | |
a2fbb9ea | 4679 | |
6383c0b3 AE |
4680 | for_each_cos_in_tx_queue(fp, cos) |
4681 | bnx2x_tx_int(bp, &fp->txdata[cos]); | |
b8ee8328 | 4682 | bnx2x_rx_int(fp, 1000); |
a2fbb9ea ET |
4683 | } |
4684 | ||
34f80b04 | 4685 | if (!BP_NOMCP(bp)) { |
f2e0899f | 4686 | int mb_idx = BP_FW_MB_IDX(bp); |
a2fbb9ea ET |
4687 | u32 drv_pulse; |
4688 | u32 mcp_pulse; | |
4689 | ||
4690 | ++bp->fw_drv_pulse_wr_seq; | |
4691 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
4692 | /* TBD - add SYSTEM_TIME */ | |
4693 | drv_pulse = bp->fw_drv_pulse_wr_seq; | |
619c5cb6 | 4694 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 4695 | |
f2e0899f | 4696 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
4697 | MCP_PULSE_SEQ_MASK); |
4698 | /* The delta between driver pulse and mcp response | |
4699 | * should be 1 (before mcp response) or 0 (after mcp response) | |
4700 | */ | |
4701 | if ((drv_pulse != mcp_pulse) && | |
4702 | (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { | |
4703 | /* someone lost a heartbeat... */ | |
4704 | BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
4705 | drv_pulse, mcp_pulse); | |
4706 | } | |
4707 | } | |
4708 | ||
f34d28ea | 4709 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 4710 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 4711 | |
a2fbb9ea ET |
4712 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
4713 | } | |
4714 | ||
4715 | /* end of Statistics */ | |
4716 | ||
4717 | /* nic init */ | |
4718 | ||
4719 | /* | |
4720 | * nic init service functions | |
4721 | */ | |
4722 | ||
523224a3 | 4723 | static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 4724 | { |
523224a3 DK |
4725 | u32 i; |
4726 | if (!(len%4) && !(addr%4)) | |
4727 | for (i = 0; i < len; i += 4) | |
4728 | REG_WR(bp, addr + i, fill); | |
4729 | else | |
4730 | for (i = 0; i < len; i++) | |
4731 | REG_WR8(bp, addr + i, fill); | |
34f80b04 | 4732 | |
34f80b04 EG |
4733 | } |
4734 | ||
523224a3 DK |
4735 | /* helper: writes FP SP data to FW - data_size in dwords */ |
4736 | static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, | |
4737 | int fw_sb_id, | |
4738 | u32 *sb_data_p, | |
4739 | u32 data_size) | |
34f80b04 | 4740 | { |
a2fbb9ea | 4741 | int index; |
523224a3 DK |
4742 | for (index = 0; index < data_size; index++) |
4743 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
4744 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
4745 | sizeof(u32)*index, | |
4746 | *(sb_data_p + index)); | |
4747 | } | |
a2fbb9ea | 4748 | |
523224a3 DK |
4749 | static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
4750 | { | |
4751 | u32 *sb_data_p; | |
4752 | u32 data_size = 0; | |
f2e0899f | 4753 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 4754 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 4755 | |
523224a3 | 4756 | /* disable the function first */ |
619c5cb6 | 4757 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 4758 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 4759 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
4760 | sb_data_e2.common.p_func.vf_valid = false; |
4761 | sb_data_p = (u32 *)&sb_data_e2; | |
4762 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
4763 | } else { | |
4764 | memset(&sb_data_e1x, 0, | |
4765 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 4766 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
4767 | sb_data_e1x.common.p_func.vf_valid = false; |
4768 | sb_data_p = (u32 *)&sb_data_e1x; | |
4769 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
4770 | } | |
523224a3 | 4771 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 4772 | |
523224a3 DK |
4773 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
4774 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
4775 | CSTORM_STATUS_BLOCK_SIZE); | |
4776 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
4777 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
4778 | CSTORM_SYNC_BLOCK_SIZE); | |
4779 | } | |
34f80b04 | 4780 | |
523224a3 DK |
4781 | /* helper: writes SP SB data to FW */ |
4782 | static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, | |
4783 | struct hc_sp_status_block_data *sp_sb_data) | |
4784 | { | |
4785 | int func = BP_FUNC(bp); | |
4786 | int i; | |
4787 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
4788 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
4789 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
4790 | i*sizeof(u32), | |
4791 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
4792 | } |
4793 | ||
523224a3 | 4794 | static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
4795 | { |
4796 | int func = BP_FUNC(bp); | |
523224a3 DK |
4797 | struct hc_sp_status_block_data sp_sb_data; |
4798 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 4799 | |
619c5cb6 | 4800 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
4801 | sp_sb_data.p_func.vf_valid = false; |
4802 | ||
4803 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
4804 | ||
4805 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
4806 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
4807 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
4808 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
4809 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
4810 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
4811 | ||
4812 | } | |
4813 | ||
4814 | ||
4815 | static inline | |
4816 | void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, | |
4817 | int igu_sb_id, int igu_seg_id) | |
4818 | { | |
4819 | hc_sm->igu_sb_id = igu_sb_id; | |
4820 | hc_sm->igu_seg_id = igu_seg_id; | |
4821 | hc_sm->timer_value = 0xFF; | |
4822 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
4823 | } |
4824 | ||
150966ad AE |
4825 | |
4826 | /* allocates state machine ids. */ | |
4827 | static inline | |
4828 | void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) | |
4829 | { | |
4830 | /* zero out state machine indices */ | |
4831 | /* rx indices */ | |
4832 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
4833 | ||
4834 | /* tx indices */ | |
4835 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
4836 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
4837 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
4838 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
4839 | ||
4840 | /* map indices */ | |
4841 | /* rx indices */ | |
4842 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
4843 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
4844 | ||
4845 | /* tx indices */ | |
4846 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
4847 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
4848 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
4849 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
4850 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
4851 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
4852 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
4853 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
4854 | } | |
4855 | ||
8d96286a | 4856 | static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 4857 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 4858 | { |
523224a3 DK |
4859 | int igu_seg_id; |
4860 | ||
f2e0899f | 4861 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
4862 | struct hc_status_block_data_e1x sb_data_e1x; |
4863 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
4864 | int data_size; |
4865 | u32 *sb_data_p; | |
4866 | ||
f2e0899f DK |
4867 | if (CHIP_INT_MODE_IS_BC(bp)) |
4868 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
4869 | else | |
4870 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
4871 | |
4872 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
4873 | ||
619c5cb6 | 4874 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 4875 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 4876 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
4877 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
4878 | sb_data_e2.common.p_func.vf_id = vfid; | |
4879 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
4880 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
4881 | sb_data_e2.common.same_igu_sb_1b = true; | |
4882 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
4883 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
4884 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
4885 | sb_data_p = (u32 *)&sb_data_e2; |
4886 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 4887 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
4888 | } else { |
4889 | memset(&sb_data_e1x, 0, | |
4890 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 4891 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
4892 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
4893 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
4894 | sb_data_e1x.common.p_func.vf_valid = false; | |
4895 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
4896 | sb_data_e1x.common.same_igu_sb_1b = true; | |
4897 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
4898 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
4899 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
4900 | sb_data_p = (u32 *)&sb_data_e1x; |
4901 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 4902 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 4903 | } |
523224a3 DK |
4904 | |
4905 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
4906 | igu_sb_id, igu_seg_id); | |
4907 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
4908 | igu_sb_id, igu_seg_id); | |
4909 | ||
4910 | DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); | |
4911 | ||
4912 | /* write indecies to HW */ | |
4913 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); | |
4914 | } | |
4915 | ||
619c5cb6 | 4916 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
4917 | u16 tx_usec, u16 rx_usec) |
4918 | { | |
6383c0b3 | 4919 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 4920 | false, rx_usec); |
6383c0b3 AE |
4921 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
4922 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
4923 | tx_usec); | |
4924 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
4925 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
4926 | tx_usec); | |
4927 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
4928 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
4929 | tx_usec); | |
523224a3 | 4930 | } |
f2e0899f | 4931 | |
523224a3 DK |
4932 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
4933 | { | |
4934 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
4935 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
4936 | int igu_sp_sb_index; | |
4937 | int igu_seg_id; | |
34f80b04 EG |
4938 | int port = BP_PORT(bp); |
4939 | int func = BP_FUNC(bp); | |
f2eaeb58 | 4940 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 4941 | u64 section; |
523224a3 DK |
4942 | int index; |
4943 | struct hc_sp_status_block_data sp_sb_data; | |
4944 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
4945 | ||
f2e0899f DK |
4946 | if (CHIP_INT_MODE_IS_BC(bp)) { |
4947 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
4948 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
4949 | } else { | |
4950 | igu_sp_sb_index = bp->igu_dsb_id; | |
4951 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
4952 | } | |
a2fbb9ea ET |
4953 | |
4954 | /* ATTN */ | |
523224a3 | 4955 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 4956 | atten_status_block); |
523224a3 | 4957 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 4958 | |
49d66772 ET |
4959 | bp->attn_state = 0; |
4960 | ||
a2fbb9ea ET |
4961 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
4962 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
4963 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
4964 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 4965 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
4966 | int sindex; |
4967 | /* take care of sig[0]..sig[4] */ | |
4968 | for (sindex = 0; sindex < 4; sindex++) | |
4969 | bp->attn_group[index].sig[sindex] = | |
4970 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 4971 | |
619c5cb6 | 4972 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4973 | /* |
4974 | * enable5 is separate from the rest of the registers, | |
4975 | * and therefore the address skip is 4 | |
4976 | * and not 16 between the different groups | |
4977 | */ | |
4978 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 4979 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
4980 | else |
4981 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
4982 | } |
4983 | ||
f2e0899f DK |
4984 | if (bp->common.int_block == INT_BLOCK_HC) { |
4985 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
4986 | HC_REG_ATTN_MSG0_ADDR_L); | |
4987 | ||
4988 | REG_WR(bp, reg_offset, U64_LO(section)); | |
4989 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 4990 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
4991 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
4992 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
4993 | } | |
a2fbb9ea | 4994 | |
523224a3 DK |
4995 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
4996 | sp_sb); | |
a2fbb9ea | 4997 | |
523224a3 | 4998 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 4999 | |
619c5cb6 | 5000 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
5001 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
5002 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
5003 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
5004 | sp_sb_data.igu_seg_id = igu_seg_id; | |
5005 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 5006 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 5007 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 5008 | |
523224a3 | 5009 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 5010 | |
523224a3 | 5011 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
5012 | } |
5013 | ||
9f6c9258 | 5014 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 5015 | { |
a2fbb9ea ET |
5016 | int i; |
5017 | ||
ec6ba945 | 5018 | for_each_eth_queue(bp, i) |
523224a3 | 5019 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 5020 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
5021 | } |
5022 | ||
a2fbb9ea ET |
5023 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
5024 | { | |
a2fbb9ea | 5025 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 5026 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 5027 | |
a2fbb9ea | 5028 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
5029 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
5030 | bp->spq_prod_bd = bp->spq; | |
5031 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
5032 | } |
5033 | ||
523224a3 | 5034 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
5035 | { |
5036 | int i; | |
523224a3 DK |
5037 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
5038 | union event_ring_elem *elem = | |
5039 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 5040 | |
523224a3 DK |
5041 | elem->next_page.addr.hi = |
5042 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
5043 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
5044 | elem->next_page.addr.lo = | |
5045 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
5046 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 5047 | } |
523224a3 DK |
5048 | bp->eq_cons = 0; |
5049 | bp->eq_prod = NUM_EQ_DESC; | |
5050 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
6e30dd4e VZ |
5051 | /* we want a warning message before it gets rought... */ |
5052 | atomic_set(&bp->eq_spq_left, | |
5053 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
5054 | } |
5055 | ||
619c5cb6 VZ |
5056 | |
5057 | /* called with netif_addr_lock_bh() */ | |
5058 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, | |
5059 | unsigned long rx_mode_flags, | |
5060 | unsigned long rx_accept_flags, | |
5061 | unsigned long tx_accept_flags, | |
5062 | unsigned long ramrod_flags) | |
ab532cf3 | 5063 | { |
619c5cb6 VZ |
5064 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
5065 | int rc; | |
5066 | ||
5067 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
5068 | ||
5069 | /* Prepare ramrod parameters */ | |
5070 | ramrod_param.cid = 0; | |
5071 | ramrod_param.cl_id = cl_id; | |
5072 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
5073 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 5074 | |
619c5cb6 VZ |
5075 | ramrod_param.pstate = &bp->sp_state; |
5076 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 5077 | |
619c5cb6 VZ |
5078 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
5079 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
5080 | ||
5081 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5082 | ||
5083 | ramrod_param.ramrod_flags = ramrod_flags; | |
5084 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
5085 | ||
5086 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
5087 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
5088 | ||
5089 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
5090 | if (rc < 0) { | |
5091 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
5092 | return; | |
5093 | } | |
a2fbb9ea ET |
5094 | } |
5095 | ||
619c5cb6 VZ |
5096 | /* called with netif_addr_lock_bh() */ |
5097 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |
471de716 | 5098 | { |
619c5cb6 VZ |
5099 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; |
5100 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
471de716 | 5101 | |
619c5cb6 VZ |
5102 | #ifdef BCM_CNIC |
5103 | if (!NO_FCOE(bp)) | |
5104 | ||
5105 | /* Configure rx_mode of FCoE Queue */ | |
5106 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
5107 | #endif | |
5108 | ||
5109 | switch (bp->rx_mode) { | |
5110 | case BNX2X_RX_MODE_NONE: | |
5111 | /* | |
5112 | * 'drop all' supersedes any accept flags that may have been | |
5113 | * passed to the function. | |
5114 | */ | |
5115 | break; | |
5116 | case BNX2X_RX_MODE_NORMAL: | |
5117 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5118 | __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); | |
5119 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5120 | ||
5121 | /* internal switching mode */ | |
5122 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5123 | __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); | |
5124 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5125 | ||
5126 | break; | |
5127 | case BNX2X_RX_MODE_ALLMULTI: | |
5128 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5129 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5130 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5131 | ||
5132 | /* internal switching mode */ | |
5133 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5134 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5135 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5136 | ||
5137 | break; | |
5138 | case BNX2X_RX_MODE_PROMISC: | |
5139 | /* According to deffinition of SI mode, iface in promisc mode | |
5140 | * should receive matched and unmatched (in resolution of port) | |
5141 | * unicast packets. | |
5142 | */ | |
5143 | __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); | |
5144 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5145 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5146 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5147 | ||
5148 | /* internal switching mode */ | |
5149 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5150 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5151 | ||
5152 | if (IS_MF_SI(bp)) | |
5153 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); | |
5154 | else | |
5155 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5156 | ||
5157 | break; | |
5158 | default: | |
5159 | BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); | |
5160 | return; | |
5161 | } | |
de832a55 | 5162 | |
619c5cb6 VZ |
5163 | if (bp->rx_mode != BNX2X_RX_MODE_NONE) { |
5164 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); | |
5165 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); | |
34f80b04 EG |
5166 | } |
5167 | ||
619c5cb6 VZ |
5168 | __set_bit(RAMROD_RX, &ramrod_flags); |
5169 | __set_bit(RAMROD_TX, &ramrod_flags); | |
5170 | ||
5171 | bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, | |
5172 | tx_accept_flags, ramrod_flags); | |
5173 | } | |
5174 | ||
5175 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
5176 | { | |
5177 | int i; | |
5178 | ||
0793f83f DK |
5179 | if (IS_MF_SI(bp)) |
5180 | /* | |
5181 | * In switch independent mode, the TSTORM needs to accept | |
5182 | * packets that failed classification, since approximate match | |
5183 | * mac addresses aren't written to NIG LLH | |
5184 | */ | |
5185 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5186 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); | |
619c5cb6 VZ |
5187 | else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ |
5188 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5189 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); | |
0793f83f | 5190 | |
523224a3 DK |
5191 | /* Zero this manually as its initialization is |
5192 | currently missing in the initTool */ | |
5193 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 5194 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 5195 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 5196 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5197 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
5198 | CHIP_INT_MODE_IS_BC(bp) ? | |
5199 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
5200 | } | |
523224a3 | 5201 | } |
8a1c38d1 | 5202 | |
471de716 EG |
5203 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
5204 | { | |
5205 | switch (load_code) { | |
5206 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 5207 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
5208 | bnx2x_init_internal_common(bp); |
5209 | /* no break */ | |
5210 | ||
5211 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 5212 | /* nothing to do */ |
471de716 EG |
5213 | /* no break */ |
5214 | ||
5215 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
5216 | /* internal memory per function is |
5217 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
5218 | break; |
5219 | ||
5220 | default: | |
5221 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
5222 | break; | |
5223 | } | |
5224 | } | |
5225 | ||
619c5cb6 | 5226 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 5227 | { |
6383c0b3 | 5228 | return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; |
619c5cb6 | 5229 | } |
523224a3 | 5230 | |
619c5cb6 VZ |
5231 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
5232 | { | |
6383c0b3 | 5233 | return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; |
619c5cb6 VZ |
5234 | } |
5235 | ||
5236 | static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) | |
5237 | { | |
5238 | if (CHIP_IS_E1x(fp->bp)) | |
5239 | return BP_L_ID(fp->bp) + fp->index; | |
5240 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
5241 | return bnx2x_fp_igu_sb_id(fp); | |
5242 | } | |
5243 | ||
6383c0b3 | 5244 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
5245 | { |
5246 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 5247 | u8 cos; |
619c5cb6 | 5248 | unsigned long q_type = 0; |
6383c0b3 | 5249 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 5250 | fp->rx_queue = fp_idx; |
b3b83c3f | 5251 | fp->cid = fp_idx; |
619c5cb6 VZ |
5252 | fp->cl_id = bnx2x_fp_cl_id(fp); |
5253 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
5254 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 5255 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
5256 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
5257 | ||
523224a3 | 5258 | /* init shortcut */ |
619c5cb6 | 5259 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
523224a3 DK |
5260 | /* Setup SB indicies */ |
5261 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; | |
523224a3 | 5262 | |
619c5cb6 VZ |
5263 | /* Configure Queue State object */ |
5264 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
5265 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
5266 | |
5267 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
5268 | ||
5269 | /* init tx data */ | |
5270 | for_each_cos_in_tx_queue(fp, cos) { | |
5271 | bnx2x_init_txdata(bp, &fp->txdata[cos], | |
5272 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos), | |
5273 | FP_COS_TO_TXQ(fp, cos), | |
5274 | BNX2X_TX_SB_INDEX_BASE + cos); | |
5275 | cids[cos] = fp->txdata[cos].cid; | |
5276 | } | |
5277 | ||
5278 | bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, | |
5279 | BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
5280 | bnx2x_sp_mapping(bp, q_rdata), q_type); | |
619c5cb6 VZ |
5281 | |
5282 | /** | |
5283 | * Configure classification DBs: Always enable Tx switching | |
5284 | */ | |
5285 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
5286 | ||
523224a3 DK |
5287 | DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " |
5288 | "cl_id %d fw_sb %d igu_sb %d\n", | |
619c5cb6 | 5289 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, |
523224a3 DK |
5290 | fp->igu_sb_id); |
5291 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
5292 | fp->fw_sb_id, fp->igu_sb_id); | |
5293 | ||
5294 | bnx2x_update_fpsb_idx(fp); | |
5295 | } | |
5296 | ||
9f6c9258 | 5297 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) |
a2fbb9ea ET |
5298 | { |
5299 | int i; | |
5300 | ||
ec6ba945 | 5301 | for_each_eth_queue(bp, i) |
6383c0b3 | 5302 | bnx2x_init_eth_fp(bp, i); |
37b091ba | 5303 | #ifdef BCM_CNIC |
ec6ba945 VZ |
5304 | if (!NO_FCOE(bp)) |
5305 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
5306 | |
5307 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
5308 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 5309 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 5310 | |
37b091ba | 5311 | #endif |
a2fbb9ea | 5312 | |
020c7e3f YR |
5313 | /* Initialize MOD_ABS interrupts */ |
5314 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
5315 | bp->common.shmem_base, bp->common.shmem2_base, | |
5316 | BP_PORT(bp)); | |
16119785 EG |
5317 | /* ensure status block indices were read */ |
5318 | rmb(); | |
5319 | ||
523224a3 | 5320 | bnx2x_init_def_sb(bp); |
5c862848 | 5321 | bnx2x_update_dsb_idx(bp); |
a2fbb9ea | 5322 | bnx2x_init_rx_rings(bp); |
523224a3 | 5323 | bnx2x_init_tx_rings(bp); |
a2fbb9ea | 5324 | bnx2x_init_sp_ring(bp); |
523224a3 | 5325 | bnx2x_init_eq_ring(bp); |
471de716 | 5326 | bnx2x_init_internal(bp, load_code); |
523224a3 | 5327 | bnx2x_pf_init(bp); |
0ef00459 EG |
5328 | bnx2x_stats_init(bp); |
5329 | ||
0ef00459 EG |
5330 | /* flush all before enabling interrupts */ |
5331 | mb(); | |
5332 | mmiowb(); | |
5333 | ||
615f8fd9 | 5334 | bnx2x_int_enable(bp); |
eb8da205 EG |
5335 | |
5336 | /* Check for SPIO5 */ | |
5337 | bnx2x_attn_int_deasserted0(bp, | |
5338 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
5339 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
5340 | } |
5341 | ||
5342 | /* end of nic init */ | |
5343 | ||
5344 | /* | |
5345 | * gzip service functions | |
5346 | */ | |
5347 | ||
5348 | static int bnx2x_gunzip_init(struct bnx2x *bp) | |
5349 | { | |
1a983142 FT |
5350 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
5351 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
5352 | if (bp->gunzip_buf == NULL) |
5353 | goto gunzip_nomem1; | |
5354 | ||
5355 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
5356 | if (bp->strm == NULL) | |
5357 | goto gunzip_nomem2; | |
5358 | ||
7ab24bfd | 5359 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
5360 | if (bp->strm->workspace == NULL) |
5361 | goto gunzip_nomem3; | |
5362 | ||
5363 | return 0; | |
5364 | ||
5365 | gunzip_nomem3: | |
5366 | kfree(bp->strm); | |
5367 | bp->strm = NULL; | |
5368 | ||
5369 | gunzip_nomem2: | |
1a983142 FT |
5370 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5371 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5372 | bp->gunzip_buf = NULL; |
5373 | ||
5374 | gunzip_nomem1: | |
cdaa7cb8 VZ |
5375 | netdev_err(bp->dev, "Cannot allocate firmware buffer for" |
5376 | " un-compression\n"); | |
a2fbb9ea ET |
5377 | return -ENOMEM; |
5378 | } | |
5379 | ||
5380 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
5381 | { | |
b3b83c3f | 5382 | if (bp->strm) { |
7ab24bfd | 5383 | vfree(bp->strm->workspace); |
b3b83c3f DK |
5384 | kfree(bp->strm); |
5385 | bp->strm = NULL; | |
5386 | } | |
a2fbb9ea ET |
5387 | |
5388 | if (bp->gunzip_buf) { | |
1a983142 FT |
5389 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5390 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5391 | bp->gunzip_buf = NULL; |
5392 | } | |
5393 | } | |
5394 | ||
94a78b79 | 5395 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
5396 | { |
5397 | int n, rc; | |
5398 | ||
5399 | /* check gzip header */ | |
94a78b79 VZ |
5400 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
5401 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 5402 | return -EINVAL; |
94a78b79 | 5403 | } |
a2fbb9ea ET |
5404 | |
5405 | n = 10; | |
5406 | ||
34f80b04 | 5407 | #define FNAME 0x8 |
a2fbb9ea ET |
5408 | |
5409 | if (zbuf[3] & FNAME) | |
5410 | while ((zbuf[n++] != 0) && (n < len)); | |
5411 | ||
94a78b79 | 5412 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
5413 | bp->strm->avail_in = len - n; |
5414 | bp->strm->next_out = bp->gunzip_buf; | |
5415 | bp->strm->avail_out = FW_BUF_SIZE; | |
5416 | ||
5417 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
5418 | if (rc != Z_OK) | |
5419 | return rc; | |
5420 | ||
5421 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
5422 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
5423 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
5424 | bp->strm->msg); | |
a2fbb9ea ET |
5425 | |
5426 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
5427 | if (bp->gunzip_outlen & 0x3) | |
cdaa7cb8 VZ |
5428 | netdev_err(bp->dev, "Firmware decompression error:" |
5429 | " gunzip_outlen (%d) not aligned\n", | |
5430 | bp->gunzip_outlen); | |
a2fbb9ea ET |
5431 | bp->gunzip_outlen >>= 2; |
5432 | ||
5433 | zlib_inflateEnd(bp->strm); | |
5434 | ||
5435 | if (rc == Z_STREAM_END) | |
5436 | return 0; | |
5437 | ||
5438 | return rc; | |
5439 | } | |
5440 | ||
5441 | /* nic load/unload */ | |
5442 | ||
5443 | /* | |
34f80b04 | 5444 | * General service functions |
a2fbb9ea ET |
5445 | */ |
5446 | ||
5447 | /* send a NIG loopback debug packet */ | |
5448 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
5449 | { | |
a2fbb9ea | 5450 | u32 wb_write[3]; |
a2fbb9ea ET |
5451 | |
5452 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
5453 | wb_write[0] = 0x55555555; |
5454 | wb_write[1] = 0x55555555; | |
34f80b04 | 5455 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 5456 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5457 | |
5458 | /* NON-IP protocol */ | |
a2fbb9ea ET |
5459 | wb_write[0] = 0x09000000; |
5460 | wb_write[1] = 0x55555555; | |
34f80b04 | 5461 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 5462 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5463 | } |
5464 | ||
5465 | /* some of the internal memories | |
5466 | * are not directly readable from the driver | |
5467 | * to test them we send debug packets | |
5468 | */ | |
5469 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
5470 | { | |
5471 | int factor; | |
5472 | int count, i; | |
5473 | u32 val = 0; | |
5474 | ||
ad8d3948 | 5475 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 5476 | factor = 120; |
ad8d3948 EG |
5477 | else if (CHIP_REV_IS_EMUL(bp)) |
5478 | factor = 200; | |
5479 | else | |
a2fbb9ea | 5480 | factor = 1; |
a2fbb9ea | 5481 | |
a2fbb9ea ET |
5482 | /* Disable inputs of parser neighbor blocks */ |
5483 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5484 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5485 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5486 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5487 | |
5488 | /* Write 0 to parser credits for CFC search request */ | |
5489 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5490 | ||
5491 | /* send Ethernet packet */ | |
5492 | bnx2x_lb_pckt(bp); | |
5493 | ||
5494 | /* TODO do i reset NIG statistic? */ | |
5495 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
5496 | count = 1000 * factor; | |
5497 | while (count) { | |
34f80b04 | 5498 | |
a2fbb9ea ET |
5499 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5500 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5501 | if (val == 0x10) |
5502 | break; | |
5503 | ||
5504 | msleep(10); | |
5505 | count--; | |
5506 | } | |
5507 | if (val != 0x10) { | |
5508 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5509 | return -1; | |
5510 | } | |
5511 | ||
5512 | /* Wait until PRS register shows 1 packet */ | |
5513 | count = 1000 * factor; | |
5514 | while (count) { | |
5515 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
5516 | if (val == 1) |
5517 | break; | |
5518 | ||
5519 | msleep(10); | |
5520 | count--; | |
5521 | } | |
5522 | if (val != 0x1) { | |
5523 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5524 | return -2; | |
5525 | } | |
5526 | ||
5527 | /* Reset and init BRB, PRS */ | |
34f80b04 | 5528 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 5529 | msleep(50); |
34f80b04 | 5530 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 5531 | msleep(50); |
619c5cb6 VZ |
5532 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
5533 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
5534 | |
5535 | DP(NETIF_MSG_HW, "part2\n"); | |
5536 | ||
5537 | /* Disable inputs of parser neighbor blocks */ | |
5538 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
5539 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
5540 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 5541 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
5542 | |
5543 | /* Write 0 to parser credits for CFC search request */ | |
5544 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
5545 | ||
5546 | /* send 10 Ethernet packets */ | |
5547 | for (i = 0; i < 10; i++) | |
5548 | bnx2x_lb_pckt(bp); | |
5549 | ||
5550 | /* Wait until NIG register shows 10 + 1 | |
5551 | packets of size 11*0x10 = 0xb0 */ | |
5552 | count = 1000 * factor; | |
5553 | while (count) { | |
34f80b04 | 5554 | |
a2fbb9ea ET |
5555 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
5556 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
5557 | if (val == 0xb0) |
5558 | break; | |
5559 | ||
5560 | msleep(10); | |
5561 | count--; | |
5562 | } | |
5563 | if (val != 0xb0) { | |
5564 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
5565 | return -3; | |
5566 | } | |
5567 | ||
5568 | /* Wait until PRS register shows 2 packets */ | |
5569 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
5570 | if (val != 2) | |
5571 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5572 | ||
5573 | /* Write 1 to parser credits for CFC search request */ | |
5574 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
5575 | ||
5576 | /* Wait until PRS register shows 3 packets */ | |
5577 | msleep(10 * factor); | |
5578 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
5579 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
5580 | if (val != 3) | |
5581 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
5582 | ||
5583 | /* clear NIG EOP FIFO */ | |
5584 | for (i = 0; i < 11; i++) | |
5585 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
5586 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
5587 | if (val != 1) { | |
5588 | BNX2X_ERR("clear of NIG failed\n"); | |
5589 | return -4; | |
5590 | } | |
5591 | ||
5592 | /* Reset and init BRB, PRS, NIG */ | |
5593 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
5594 | msleep(50); | |
5595 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
5596 | msleep(50); | |
619c5cb6 VZ |
5597 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
5598 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
37b091ba | 5599 | #ifndef BCM_CNIC |
a2fbb9ea ET |
5600 | /* set NIC mode */ |
5601 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
5602 | #endif | |
5603 | ||
5604 | /* Enable inputs of parser neighbor blocks */ | |
5605 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
5606 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
5607 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 5608 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
5609 | |
5610 | DP(NETIF_MSG_HW, "done\n"); | |
5611 | ||
5612 | return 0; /* OK */ | |
5613 | } | |
5614 | ||
4a33bc03 | 5615 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea ET |
5616 | { |
5617 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
619c5cb6 | 5618 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5619 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
5620 | else | |
5621 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
5622 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
5623 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
5624 | /* |
5625 | * mask read length error interrupts in brb for parser | |
5626 | * (parsing unit and 'checksum and crc' unit) | |
5627 | * these errors are legal (PU reads fixed length and CAC can cause | |
5628 | * read length error on truncated packets) | |
5629 | */ | |
5630 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
5631 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
5632 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
5633 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
5634 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
5635 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
5636 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
5637 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
5638 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
5639 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
5640 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
5641 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
5642 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
5643 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
5644 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
5645 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
5646 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
5647 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
5648 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 5649 | |
34f80b04 EG |
5650 | if (CHIP_REV_IS_FPGA(bp)) |
5651 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); | |
619c5cb6 | 5652 | else if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5653 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, |
5654 | (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | |
5655 | | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
5656 | | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN | |
5657 | | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | |
5658 | | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); | |
34f80b04 EG |
5659 | else |
5660 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); | |
a2fbb9ea ET |
5661 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
5662 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
5663 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 5664 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
5665 | |
5666 | if (!CHIP_IS_E1x(bp)) | |
5667 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
5668 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
5669 | ||
a2fbb9ea ET |
5670 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
5671 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 5672 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 5673 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
5674 | } |
5675 | ||
81f75bbf EG |
5676 | static void bnx2x_reset_common(struct bnx2x *bp) |
5677 | { | |
619c5cb6 VZ |
5678 | u32 val = 0x1400; |
5679 | ||
81f75bbf EG |
5680 | /* reset_common */ |
5681 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
5682 | 0xd3ffff7f); | |
619c5cb6 VZ |
5683 | |
5684 | if (CHIP_IS_E3(bp)) { | |
5685 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
5686 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
5687 | } | |
5688 | ||
5689 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
5690 | } | |
5691 | ||
5692 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
5693 | { | |
5694 | bp->dmae_ready = 0; | |
5695 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
5696 | } |
5697 | ||
573f2035 EG |
5698 | static void bnx2x_init_pxp(struct bnx2x *bp) |
5699 | { | |
5700 | u16 devctl; | |
5701 | int r_order, w_order; | |
5702 | ||
5703 | pci_read_config_word(bp->pdev, | |
b6c2f86e | 5704 | pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
5705 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
5706 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
5707 | if (bp->mrrs == -1) | |
5708 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
5709 | else { | |
5710 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
5711 | r_order = bp->mrrs; | |
5712 | } | |
5713 | ||
5714 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
5715 | } | |
fd4ef40d EG |
5716 | |
5717 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
5718 | { | |
2145a920 | 5719 | int is_required; |
fd4ef40d | 5720 | u32 val; |
2145a920 | 5721 | int port; |
fd4ef40d | 5722 | |
2145a920 VZ |
5723 | if (BP_NOMCP(bp)) |
5724 | return; | |
5725 | ||
5726 | is_required = 0; | |
fd4ef40d EG |
5727 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
5728 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
5729 | ||
5730 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
5731 | is_required = 1; | |
5732 | ||
5733 | /* | |
5734 | * The fan failure mechanism is usually related to the PHY type since | |
5735 | * the power consumption of the board is affected by the PHY. Currently, | |
5736 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
5737 | */ | |
5738 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
5739 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 5740 | is_required |= |
d90d96ba YR |
5741 | bnx2x_fan_failure_det_req( |
5742 | bp, | |
5743 | bp->common.shmem_base, | |
a22f0788 | 5744 | bp->common.shmem2_base, |
d90d96ba | 5745 | port); |
fd4ef40d EG |
5746 | } |
5747 | ||
5748 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
5749 | ||
5750 | if (is_required == 0) | |
5751 | return; | |
5752 | ||
5753 | /* Fan failure is indicated by SPIO 5 */ | |
5754 | bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, | |
5755 | MISC_REGISTERS_SPIO_INPUT_HI_Z); | |
5756 | ||
5757 | /* set to active low mode */ | |
5758 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
5759 | val |= ((1 << MISC_REGISTERS_SPIO_5) << | |
cdaa7cb8 | 5760 | MISC_REGISTERS_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
5761 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
5762 | ||
5763 | /* enable interrupt to signal the IGU */ | |
5764 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
5765 | val |= (1 << MISC_REGISTERS_SPIO_5); | |
5766 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); | |
5767 | } | |
5768 | ||
f2e0899f DK |
5769 | static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) |
5770 | { | |
5771 | u32 offset = 0; | |
5772 | ||
5773 | if (CHIP_IS_E1(bp)) | |
5774 | return; | |
5775 | if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) | |
5776 | return; | |
5777 | ||
5778 | switch (BP_ABS_FUNC(bp)) { | |
5779 | case 0: | |
5780 | offset = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
5781 | break; | |
5782 | case 1: | |
5783 | offset = PXP2_REG_PGL_PRETEND_FUNC_F1; | |
5784 | break; | |
5785 | case 2: | |
5786 | offset = PXP2_REG_PGL_PRETEND_FUNC_F2; | |
5787 | break; | |
5788 | case 3: | |
5789 | offset = PXP2_REG_PGL_PRETEND_FUNC_F3; | |
5790 | break; | |
5791 | case 4: | |
5792 | offset = PXP2_REG_PGL_PRETEND_FUNC_F4; | |
5793 | break; | |
5794 | case 5: | |
5795 | offset = PXP2_REG_PGL_PRETEND_FUNC_F5; | |
5796 | break; | |
5797 | case 6: | |
5798 | offset = PXP2_REG_PGL_PRETEND_FUNC_F6; | |
5799 | break; | |
5800 | case 7: | |
5801 | offset = PXP2_REG_PGL_PRETEND_FUNC_F7; | |
5802 | break; | |
5803 | default: | |
5804 | return; | |
5805 | } | |
5806 | ||
5807 | REG_WR(bp, offset, pretend_func_num); | |
5808 | REG_RD(bp, offset); | |
5809 | DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); | |
5810 | } | |
5811 | ||
c9ee9206 | 5812 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
5813 | { |
5814 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
5815 | val &= ~IGU_PF_CONF_FUNC_EN; | |
5816 | ||
5817 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
5818 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
5819 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
5820 | } | |
5821 | ||
619c5cb6 VZ |
5822 | static inline void bnx2x__common_init_phy(struct bnx2x *bp) |
5823 | { | |
5824 | u32 shmem_base[2], shmem2_base[2]; | |
5825 | shmem_base[0] = bp->common.shmem_base; | |
5826 | shmem2_base[0] = bp->common.shmem2_base; | |
5827 | if (!CHIP_IS_E1x(bp)) { | |
5828 | shmem_base[1] = | |
5829 | SHMEM2_RD(bp, other_shmem_base_addr); | |
5830 | shmem2_base[1] = | |
5831 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
5832 | } | |
5833 | bnx2x_acquire_phy_lock(bp); | |
5834 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
5835 | bp->common.chip_id); | |
5836 | bnx2x_release_phy_lock(bp); | |
5837 | } | |
5838 | ||
5839 | /** | |
5840 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
5841 | * | |
5842 | * @bp: driver handle | |
5843 | */ | |
5844 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 5845 | { |
619c5cb6 | 5846 | u32 val; |
a2fbb9ea | 5847 | |
f2e0899f | 5848 | DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 5849 | |
2031bd3a DK |
5850 | /* |
5851 | * take the UNDI lock to protect undi_unload flow from accessing | |
5852 | * registers while we're resetting the chip | |
5853 | */ | |
7a06a122 | 5854 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 5855 | |
81f75bbf | 5856 | bnx2x_reset_common(bp); |
34f80b04 | 5857 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 5858 | |
619c5cb6 VZ |
5859 | val = 0xfffc; |
5860 | if (CHIP_IS_E3(bp)) { | |
5861 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
5862 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
5863 | } | |
5864 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
5865 | ||
7a06a122 | 5866 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 5867 | |
619c5cb6 | 5868 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 5869 | |
619c5cb6 VZ |
5870 | if (!CHIP_IS_E1x(bp)) { |
5871 | u8 abs_func_id; | |
f2e0899f DK |
5872 | |
5873 | /** | |
5874 | * 4-port mode or 2-port mode we need to turn of master-enable | |
5875 | * for everyone, after that, turn it back on for self. | |
5876 | * so, we disregard multi-function or not, and always disable | |
5877 | * for all functions on the given path, this means 0,2,4,6 for | |
5878 | * path 0 and 1,3,5,7 for path 1 | |
5879 | */ | |
619c5cb6 VZ |
5880 | for (abs_func_id = BP_PATH(bp); |
5881 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
5882 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
5883 | REG_WR(bp, |
5884 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
5885 | 1); | |
5886 | continue; | |
5887 | } | |
5888 | ||
619c5cb6 | 5889 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
5890 | /* clear pf enable */ |
5891 | bnx2x_pf_disable(bp); | |
5892 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
5893 | } | |
5894 | } | |
a2fbb9ea | 5895 | |
619c5cb6 | 5896 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
5897 | if (CHIP_IS_E1(bp)) { |
5898 | /* enable HW interrupt from PXP on USDM overflow | |
5899 | bit 16 on INT_MASK_0 */ | |
5900 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
5901 | } | |
a2fbb9ea | 5902 | |
619c5cb6 | 5903 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 5904 | bnx2x_init_pxp(bp); |
a2fbb9ea ET |
5905 | |
5906 | #ifdef __BIG_ENDIAN | |
34f80b04 EG |
5907 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); |
5908 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); | |
5909 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); | |
5910 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); | |
5911 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); | |
8badd27a EG |
5912 | /* make sure this value is 0 */ |
5913 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
34f80b04 EG |
5914 | |
5915 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ | |
5916 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); | |
5917 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); | |
5918 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); | |
5919 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); | |
a2fbb9ea ET |
5920 | #endif |
5921 | ||
523224a3 DK |
5922 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
5923 | ||
34f80b04 EG |
5924 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
5925 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 5926 | |
34f80b04 EG |
5927 | /* let the HW do it's magic ... */ |
5928 | msleep(100); | |
5929 | /* finish PXP init */ | |
5930 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
5931 | if (val != 1) { | |
5932 | BNX2X_ERR("PXP2 CFG failed\n"); | |
5933 | return -EBUSY; | |
5934 | } | |
5935 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
5936 | if (val != 1) { | |
5937 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
5938 | return -EBUSY; | |
5939 | } | |
a2fbb9ea | 5940 | |
f2e0899f DK |
5941 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
5942 | * have entries with value "0" and valid bit on. | |
5943 | * This needs to be done by the first PF that is loaded in a path | |
5944 | * (i.e. common phase) | |
5945 | */ | |
619c5cb6 VZ |
5946 | if (!CHIP_IS_E1x(bp)) { |
5947 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
5948 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
5949 | * This occurs when a different function (func2,3) is being marked | |
5950 | * as "scan-off". Real-life scenario for example: if a driver is being | |
5951 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
5952 | * the ilt, translate to a logical address and send a request to read/write. | |
5953 | * Since the ilt for the function that is down is not valid, this will cause | |
5954 | * a translation error which is unrecoverable. | |
5955 | * The Workaround is intended to make sure that when this happens nothing fatal | |
5956 | * will occur. The workaround: | |
5957 | * 1. First PF driver which loads on a path will: | |
5958 | * a. After taking the chip out of reset, by using pretend, | |
5959 | * it will write "0" to the following registers of | |
5960 | * the other vnics. | |
5961 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
5962 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
5963 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
5964 | * And for itself it will write '1' to | |
5965 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
5966 | * dmae-operations (writing to pram for example.) | |
5967 | * note: can be done for only function 6,7 but cleaner this | |
5968 | * way. | |
5969 | * b. Write zero+valid to the entire ILT. | |
5970 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
5971 | * VNIC3 (of that port). The range allocated will be the | |
5972 | * entire ILT. This is needed to prevent ILT range error. | |
5973 | * 2. Any PF driver load flow: | |
5974 | * a. ILT update with the physical addresses of the allocated | |
5975 | * logical pages. | |
5976 | * b. Wait 20msec. - note that this timeout is needed to make | |
5977 | * sure there are no requests in one of the PXP internal | |
5978 | * queues with "old" ILT addresses. | |
5979 | * c. PF enable in the PGLC. | |
5980 | * d. Clear the was_error of the PF in the PGLC. (could have | |
5981 | * occured while driver was down) | |
5982 | * e. PF enable in the CFC (WEAK + STRONG) | |
5983 | * f. Timers scan enable | |
5984 | * 3. PF driver unload flow: | |
5985 | * a. Clear the Timers scan_en. | |
5986 | * b. Polling for scan_on=0 for that PF. | |
5987 | * c. Clear the PF enable bit in the PXP. | |
5988 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
5989 | * e. Write zero+valid to all ILT entries (The valid bit must | |
5990 | * stay set) | |
5991 | * f. If this is VNIC 3 of a port then also init | |
5992 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
5993 | * to the last enrty in the ILT. | |
5994 | * | |
5995 | * Notes: | |
5996 | * Currently the PF error in the PGLC is non recoverable. | |
5997 | * In the future the there will be a recovery routine for this error. | |
5998 | * Currently attention is masked. | |
5999 | * Having an MCP lock on the load/unload process does not guarantee that | |
6000 | * there is no Timer disable during Func6/7 enable. This is because the | |
6001 | * Timers scan is currently being cleared by the MCP on FLR. | |
6002 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
6003 | * there is error before clearing it. But the flow above is simpler and | |
6004 | * more general. | |
6005 | * All ILT entries are written by zero+valid and not just PF6/7 | |
6006 | * ILT entries since in the future the ILT entries allocation for | |
6007 | * PF-s might be dynamic. | |
6008 | */ | |
f2e0899f DK |
6009 | struct ilt_client_info ilt_cli; |
6010 | struct bnx2x_ilt ilt; | |
6011 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
6012 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
6013 | ||
b595076a | 6014 | /* initialize dummy TM client */ |
f2e0899f DK |
6015 | ilt_cli.start = 0; |
6016 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
6017 | ilt_cli.client_num = ILT_CLIENT_TM; | |
6018 | ||
6019 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
6020 | * Step 2: set the timers first/last ilt entry to point | |
6021 | * to the entire range to prevent ILT range error for 3rd/4th | |
619c5cb6 | 6022 | * vnic (this code assumes existance of the vnic) |
f2e0899f DK |
6023 | * |
6024 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
6025 | * with dummy TM client | |
6026 | * | |
6027 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
6028 | * and his brother are split registers | |
6029 | */ | |
6030 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
6031 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
6032 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6033 | ||
6034 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
6035 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
6036 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
6037 | } | |
6038 | ||
6039 | ||
34f80b04 EG |
6040 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
6041 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 6042 | |
619c5cb6 | 6043 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6044 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
6045 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 6046 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 6047 | |
619c5cb6 | 6048 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
6049 | |
6050 | /* let the HW do it's magic ... */ | |
6051 | do { | |
6052 | msleep(200); | |
6053 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
6054 | } while (factor-- && (val != 1)); | |
6055 | ||
6056 | if (val != 1) { | |
6057 | BNX2X_ERR("ATC_INIT failed\n"); | |
6058 | return -EBUSY; | |
6059 | } | |
6060 | } | |
6061 | ||
619c5cb6 | 6062 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 6063 | |
34f80b04 EG |
6064 | /* clean the DMAE memory */ |
6065 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
6066 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
6067 | ||
6068 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
6069 | ||
6070 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
6071 | ||
6072 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 6073 | |
619c5cb6 | 6074 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 6075 | |
34f80b04 EG |
6076 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
6077 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
6078 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
6079 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
6080 | ||
619c5cb6 | 6081 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 6082 | |
f85582f8 | 6083 | |
523224a3 DK |
6084 | /* QM queues pointers table */ |
6085 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
6086 | ||
34f80b04 EG |
6087 | /* soft reset pulse */ |
6088 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
6089 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 6090 | |
37b091ba | 6091 | #ifdef BCM_CNIC |
619c5cb6 | 6092 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); |
a2fbb9ea | 6093 | #endif |
a2fbb9ea | 6094 | |
619c5cb6 | 6095 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
523224a3 | 6096 | REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); |
619c5cb6 | 6097 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
6098 | /* enable hw interrupt from doorbell Q */ |
6099 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 6100 | |
619c5cb6 | 6101 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 6102 | |
619c5cb6 | 6103 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 6104 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 6105 | |
f2e0899f | 6106 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 6107 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 6108 | |
619c5cb6 VZ |
6109 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) |
6110 | /* Bit-map indicating which L2 hdrs may appear | |
6111 | * after the basic Ethernet header | |
6112 | */ | |
6113 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
6114 | bp->path_has_ovlan ? 7 : 6); | |
a2fbb9ea | 6115 | |
619c5cb6 VZ |
6116 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
6117 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
6118 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
6119 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 6120 | |
619c5cb6 VZ |
6121 | if (!CHIP_IS_E1x(bp)) { |
6122 | /* reset VFC memories */ | |
6123 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6124 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6125 | VFC_MEMORIES_RST_REG_RAM_RST); | |
6126 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6127 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6128 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 6129 | |
619c5cb6 VZ |
6130 | msleep(20); |
6131 | } | |
a2fbb9ea | 6132 | |
619c5cb6 VZ |
6133 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
6134 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
6135 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
6136 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 6137 | |
34f80b04 EG |
6138 | /* sync semi rtc */ |
6139 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6140 | 0x80000000); | |
6141 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
6142 | 0x80000000); | |
a2fbb9ea | 6143 | |
619c5cb6 VZ |
6144 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
6145 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
6146 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 6147 | |
619c5cb6 VZ |
6148 | if (!CHIP_IS_E1x(bp)) |
6149 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
6150 | bp->path_has_ovlan ? 7 : 6); | |
f2e0899f | 6151 | |
34f80b04 | 6152 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 6153 | |
619c5cb6 VZ |
6154 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
6155 | ||
37b091ba MC |
6156 | #ifdef BCM_CNIC |
6157 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
6158 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
6159 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
6160 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
6161 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
6162 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
6163 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
6164 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
6165 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
6166 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
6167 | #endif | |
34f80b04 | 6168 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 6169 | |
34f80b04 EG |
6170 | if (sizeof(union cdu_context) != 1024) |
6171 | /* we currently assume that a context is 1024 bytes */ | |
cdaa7cb8 VZ |
6172 | dev_alert(&bp->pdev->dev, "please adjust the size " |
6173 | "of cdu_context(%ld)\n", | |
7995c64e | 6174 | (long)sizeof(union cdu_context)); |
a2fbb9ea | 6175 | |
619c5cb6 | 6176 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
6177 | val = (4 << 24) + (0 << 12) + 1024; |
6178 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 6179 | |
619c5cb6 | 6180 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 6181 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
6182 | /* enable context validation interrupt from CFC */ |
6183 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
6184 | ||
6185 | /* set the thresholds to prevent CFC/CDU race */ | |
6186 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 6187 | |
619c5cb6 | 6188 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 6189 | |
619c5cb6 | 6190 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
6191 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
6192 | ||
619c5cb6 VZ |
6193 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
6194 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 6195 | |
34f80b04 EG |
6196 | /* Reset PCIE errors for debug */ |
6197 | REG_WR(bp, 0x2814, 0xffffffff); | |
6198 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 6199 | |
619c5cb6 | 6200 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6201 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
6202 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
6203 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
6204 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
6205 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
6206 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
6207 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
6208 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
6209 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
6210 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
6211 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
6212 | } | |
6213 | ||
619c5cb6 | 6214 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 6215 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
6216 | /* in E3 this done in per-port section */ |
6217 | if (!CHIP_IS_E3(bp)) | |
6218 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 6219 | } |
619c5cb6 VZ |
6220 | if (CHIP_IS_E1H(bp)) |
6221 | /* not applicable for E2 (and above ...) */ | |
6222 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
6223 | |
6224 | if (CHIP_REV_IS_SLOW(bp)) | |
6225 | msleep(200); | |
6226 | ||
6227 | /* finish CFC init */ | |
6228 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
6229 | if (val != 1) { | |
6230 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
6231 | return -EBUSY; | |
6232 | } | |
6233 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
6234 | if (val != 1) { | |
6235 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
6236 | return -EBUSY; | |
6237 | } | |
6238 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
6239 | if (val != 1) { | |
6240 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
6241 | return -EBUSY; | |
6242 | } | |
6243 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 6244 | |
f2e0899f DK |
6245 | if (CHIP_IS_E1(bp)) { |
6246 | /* read NIG statistic | |
6247 | to see if this is our first up since powerup */ | |
6248 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
6249 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 6250 | |
f2e0899f DK |
6251 | /* do internal memory self test */ |
6252 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
6253 | BNX2X_ERR("internal mem self test failed\n"); | |
6254 | return -EBUSY; | |
6255 | } | |
34f80b04 EG |
6256 | } |
6257 | ||
fd4ef40d EG |
6258 | bnx2x_setup_fan_failure_detection(bp); |
6259 | ||
34f80b04 EG |
6260 | /* clear PXP2 attentions */ |
6261 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 6262 | |
4a33bc03 | 6263 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 6264 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 6265 | |
6bbca910 | 6266 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
6267 | if (CHIP_IS_E1x(bp)) |
6268 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
6269 | } else |
6270 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
6271 | ||
34f80b04 EG |
6272 | return 0; |
6273 | } | |
a2fbb9ea | 6274 | |
619c5cb6 VZ |
6275 | /** |
6276 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
6277 | * | |
6278 | * @bp: driver handle | |
6279 | */ | |
6280 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
6281 | { | |
6282 | int rc = bnx2x_init_hw_common(bp); | |
6283 | ||
6284 | if (rc) | |
6285 | return rc; | |
6286 | ||
6287 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
6288 | if (!BP_NOMCP(bp)) | |
6289 | bnx2x__common_init_phy(bp); | |
6290 | ||
6291 | return 0; | |
6292 | } | |
6293 | ||
523224a3 | 6294 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
6295 | { |
6296 | int port = BP_PORT(bp); | |
619c5cb6 | 6297 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 6298 | u32 low, high; |
34f80b04 | 6299 | u32 val; |
a2fbb9ea | 6300 | |
619c5cb6 VZ |
6301 | bnx2x__link_reset(bp); |
6302 | ||
cdaa7cb8 | 6303 | DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); |
34f80b04 EG |
6304 | |
6305 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 6306 | |
619c5cb6 VZ |
6307 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
6308 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
6309 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 6310 | |
f2e0899f DK |
6311 | /* Timers bug workaround: disables the pf_master bit in pglue at |
6312 | * common phase, we need to enable it here before any dmae access are | |
6313 | * attempted. Therefore we manually added the enable-master to the | |
6314 | * port phase (it also happens in the function phase) | |
6315 | */ | |
619c5cb6 | 6316 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6317 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
6318 | ||
619c5cb6 VZ |
6319 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6320 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6321 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
6322 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6323 | ||
6324 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6325 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6326 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6327 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 6328 | |
523224a3 DK |
6329 | /* QM cid (connection) count */ |
6330 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 6331 | |
523224a3 | 6332 | #ifdef BCM_CNIC |
619c5cb6 | 6333 | bnx2x_init_block(bp, BLOCK_TM, init_phase); |
37b091ba MC |
6334 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); |
6335 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
a2fbb9ea | 6336 | #endif |
cdaa7cb8 | 6337 | |
619c5cb6 | 6338 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f DK |
6339 | |
6340 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { | |
619c5cb6 VZ |
6341 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
6342 | ||
6343 | if (IS_MF(bp)) | |
6344 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
6345 | else if (bp->dev->mtu > 4096) { | |
6346 | if (bp->flags & ONE_PORT_FLAG) | |
6347 | low = 160; | |
6348 | else { | |
6349 | val = bp->dev->mtu; | |
6350 | /* (24*1024 + val*4)/256 */ | |
6351 | low = 96 + (val/64) + | |
6352 | ((val % 64) ? 1 : 0); | |
6353 | } | |
6354 | } else | |
6355 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
6356 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
6357 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
6358 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 6359 | } |
1c06328c | 6360 | |
619c5cb6 VZ |
6361 | if (CHIP_MODE_IS_4_PORT(bp)) |
6362 | REG_WR(bp, (BP_PORT(bp) ? | |
6363 | BRB1_REG_MAC_GUARANTIED_1 : | |
6364 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 6365 | |
ca00392c | 6366 | |
619c5cb6 VZ |
6367 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
6368 | if (CHIP_IS_E3B0(bp)) | |
6369 | /* Ovlan exists only if we are in multi-function + | |
6370 | * switch-dependent mode, in switch-independent there | |
6371 | * is no ovlan headers | |
6372 | */ | |
6373 | REG_WR(bp, BP_PORT(bp) ? | |
6374 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
6375 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
6376 | (bp->path_has_ovlan ? 7 : 6)); | |
356e2385 | 6377 | |
619c5cb6 VZ |
6378 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
6379 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
6380 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
6381 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 6382 | |
619c5cb6 VZ |
6383 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
6384 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6385 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6386 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 6387 | |
619c5cb6 VZ |
6388 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
6389 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 6390 | |
619c5cb6 VZ |
6391 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
6392 | ||
6393 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
6394 | /* configure PBF to work without PAUSE mtu 9000 */ |
6395 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 6396 | |
f2e0899f DK |
6397 | /* update threshold */ |
6398 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
6399 | /* update init credit */ | |
6400 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 6401 | |
f2e0899f DK |
6402 | /* probe changes */ |
6403 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
6404 | udelay(50); | |
6405 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
6406 | } | |
a2fbb9ea | 6407 | |
37b091ba | 6408 | #ifdef BCM_CNIC |
619c5cb6 | 6409 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); |
a2fbb9ea | 6410 | #endif |
619c5cb6 VZ |
6411 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
6412 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
6413 | |
6414 | if (CHIP_IS_E1(bp)) { | |
6415 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
6416 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
6417 | } | |
619c5cb6 | 6418 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 6419 | |
619c5cb6 | 6420 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 6421 | |
619c5cb6 | 6422 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 EG |
6423 | /* init aeu_mask_attn_func_0/1: |
6424 | * - SF mode: bits 3-7 are masked. only bits 0-2 are in use | |
6425 | * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF | |
6426 | * bits 4-7 are used for "per vn group attention" */ | |
e4901dde VZ |
6427 | val = IS_MF(bp) ? 0xF7 : 0x7; |
6428 | /* Enable DCBX attention for all but E1 */ | |
6429 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
6430 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 6431 | |
619c5cb6 VZ |
6432 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
6433 | ||
6434 | if (!CHIP_IS_E1x(bp)) { | |
6435 | /* Bit-map indicating which L2 hdrs may appear after the | |
6436 | * basic Ethernet header | |
6437 | */ | |
6438 | REG_WR(bp, BP_PORT(bp) ? | |
6439 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
6440 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
6441 | IS_MF_SD(bp) ? 7 : 6); | |
6442 | ||
6443 | if (CHIP_IS_E3(bp)) | |
6444 | REG_WR(bp, BP_PORT(bp) ? | |
6445 | NIG_REG_LLH1_MF_MODE : | |
6446 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
6447 | } | |
6448 | if (!CHIP_IS_E3(bp)) | |
6449 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 6450 | |
f2e0899f | 6451 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 6452 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 6453 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 6454 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 6455 | |
619c5cb6 | 6456 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6457 | val = 0; |
6458 | switch (bp->mf_mode) { | |
6459 | case MULTI_FUNCTION_SD: | |
6460 | val = 1; | |
6461 | break; | |
6462 | case MULTI_FUNCTION_SI: | |
6463 | val = 2; | |
6464 | break; | |
6465 | } | |
6466 | ||
6467 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
6468 | NIG_REG_LLH0_CLS_TYPE), val); | |
6469 | } | |
1c06328c EG |
6470 | { |
6471 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
6472 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
6473 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
6474 | } | |
34f80b04 EG |
6475 | } |
6476 | ||
619c5cb6 VZ |
6477 | |
6478 | /* If SPIO5 is set to generate interrupts, enable it for this port */ | |
6479 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
6480 | if (val & (1 << MISC_REGISTERS_SPIO_5)) { | |
4d295db0 EG |
6481 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
6482 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
6483 | val = REG_RD(bp, reg_addr); | |
f1410647 | 6484 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 6485 | REG_WR(bp, reg_addr, val); |
f1410647 | 6486 | } |
a2fbb9ea | 6487 | |
34f80b04 EG |
6488 | return 0; |
6489 | } | |
6490 | ||
34f80b04 EG |
6491 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
6492 | { | |
6493 | int reg; | |
6494 | ||
f2e0899f | 6495 | if (CHIP_IS_E1(bp)) |
34f80b04 | 6496 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
6497 | else |
6498 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 EG |
6499 | |
6500 | bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); | |
6501 | } | |
6502 | ||
f2e0899f DK |
6503 | static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) |
6504 | { | |
619c5cb6 | 6505 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
6506 | } |
6507 | ||
6508 | static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) | |
6509 | { | |
6510 | u32 i, base = FUNC_ILT_BASE(func); | |
6511 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
6512 | bnx2x_ilt_wr(bp, i, 0); | |
6513 | } | |
6514 | ||
523224a3 | 6515 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
6516 | { |
6517 | int port = BP_PORT(bp); | |
6518 | int func = BP_FUNC(bp); | |
619c5cb6 | 6519 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
6520 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
6521 | u16 cdu_ilt_start; | |
8badd27a | 6522 | u32 addr, val; |
f4a66897 VZ |
6523 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
6524 | int i, main_mem_width; | |
34f80b04 | 6525 | |
cdaa7cb8 | 6526 | DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); |
34f80b04 | 6527 | |
619c5cb6 VZ |
6528 | /* FLR cleanup - hmmm */ |
6529 | if (!CHIP_IS_E1x(bp)) | |
6530 | bnx2x_pf_flr_clnup(bp); | |
6531 | ||
8badd27a | 6532 | /* set MSI reconfigure capability */ |
f2e0899f DK |
6533 | if (bp->common.int_block == INT_BLOCK_HC) { |
6534 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
6535 | val = REG_RD(bp, addr); | |
6536 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
6537 | REG_WR(bp, addr, val); | |
6538 | } | |
8badd27a | 6539 | |
619c5cb6 VZ |
6540 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
6541 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
6542 | ||
523224a3 DK |
6543 | ilt = BP_ILT(bp); |
6544 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 6545 | |
523224a3 DK |
6546 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
6547 | ilt->lines[cdu_ilt_start + i].page = | |
6548 | bp->context.vcxt + (ILT_PAGE_CIDS * i); | |
6549 | ilt->lines[cdu_ilt_start + i].page_mapping = | |
6550 | bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); | |
6551 | /* cdu ilt pages are allocated manually so there's no need to | |
6552 | set the size */ | |
37b091ba | 6553 | } |
523224a3 | 6554 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 6555 | |
523224a3 DK |
6556 | #ifdef BCM_CNIC |
6557 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
37b091ba | 6558 | |
523224a3 DK |
6559 | /* T1 hash bits value determines the T1 number of entries */ |
6560 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
6561 | #endif | |
37b091ba | 6562 | |
523224a3 DK |
6563 | #ifndef BCM_CNIC |
6564 | /* set NIC mode */ | |
6565 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6566 | #endif /* BCM_CNIC */ | |
37b091ba | 6567 | |
619c5cb6 | 6568 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6569 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
6570 | ||
6571 | /* Turn on a single ISR mode in IGU if driver is going to use | |
6572 | * INT#x or MSI | |
6573 | */ | |
6574 | if (!(bp->flags & USING_MSIX_FLAG)) | |
6575 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
6576 | /* | |
6577 | * Timers workaround bug: function init part. | |
6578 | * Need to wait 20msec after initializing ILT, | |
6579 | * needed to make sure there are no requests in | |
6580 | * one of the PXP internal queues with "old" ILT addresses | |
6581 | */ | |
6582 | msleep(20); | |
6583 | /* | |
6584 | * Master enable - Due to WB DMAE writes performed before this | |
6585 | * register is re-initialized as part of the regular function | |
6586 | * init | |
6587 | */ | |
6588 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
6589 | /* Enable the function in IGU */ | |
6590 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
6591 | } | |
6592 | ||
523224a3 | 6593 | bp->dmae_ready = 1; |
34f80b04 | 6594 | |
619c5cb6 | 6595 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 6596 | |
619c5cb6 | 6597 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6598 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); |
6599 | ||
619c5cb6 VZ |
6600 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6601 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6602 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
6603 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
6604 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
6605 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6606 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6607 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6608 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
6609 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
6610 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6611 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6612 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
6613 | ||
6614 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
6615 | REG_WR(bp, QM_REG_PF_EN, 1); |
6616 | ||
619c5cb6 VZ |
6617 | if (!CHIP_IS_E1x(bp)) { |
6618 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6619 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6620 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6621 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
6622 | } | |
6623 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6624 | ||
6625 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
6626 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
6627 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); | |
6628 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
6629 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
6630 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
6631 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
6632 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
6633 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
6634 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
6635 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
6636 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
6637 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
6638 | ||
619c5cb6 | 6639 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 6640 | |
619c5cb6 | 6641 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 6642 | |
619c5cb6 | 6643 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6644 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
6645 | ||
fb3bff17 | 6646 | if (IS_MF(bp)) { |
34f80b04 | 6647 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
fb3bff17 | 6648 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
34f80b04 EG |
6649 | } |
6650 | ||
619c5cb6 | 6651 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 6652 | |
34f80b04 | 6653 | /* HC init per function */ |
f2e0899f DK |
6654 | if (bp->common.int_block == INT_BLOCK_HC) { |
6655 | if (CHIP_IS_E1H(bp)) { | |
6656 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
6657 | ||
6658 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
6659 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
6660 | } | |
619c5cb6 | 6661 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
6662 | |
6663 | } else { | |
6664 | int num_segs, sb_idx, prod_offset; | |
6665 | ||
34f80b04 EG |
6666 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
6667 | ||
619c5cb6 | 6668 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6669 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
6670 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
6671 | } | |
6672 | ||
619c5cb6 | 6673 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 6674 | |
619c5cb6 | 6675 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6676 | int dsb_idx = 0; |
6677 | /** | |
6678 | * Producer memory: | |
6679 | * E2 mode: address 0-135 match to the mapping memory; | |
6680 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
6681 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
6682 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
6683 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
6684 | * 144-147 reserved. | |
6685 | * | |
6686 | * E1.5 mode - In backward compatible mode; | |
6687 | * for non default SB; each even line in the memory | |
6688 | * holds the U producer and each odd line hold | |
6689 | * the C producer. The first 128 producers are for | |
6690 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
6691 | * producers are for the DSB for each PF. | |
6692 | * Each PF has five segments: (the order inside each | |
6693 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
6694 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
6695 | * 144-147 attn prods; | |
6696 | */ | |
6697 | /* non-default-status-blocks */ | |
6698 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
6699 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
6700 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
6701 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
6702 | num_segs; | |
6703 | ||
6704 | for (i = 0; i < num_segs; i++) { | |
6705 | addr = IGU_REG_PROD_CONS_MEMORY + | |
6706 | (prod_offset + i) * 4; | |
6707 | REG_WR(bp, addr, 0); | |
6708 | } | |
6709 | /* send consumer update with value 0 */ | |
6710 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
6711 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
6712 | bnx2x_igu_clear_sb(bp, | |
6713 | bp->igu_base_sb + sb_idx); | |
6714 | } | |
6715 | ||
6716 | /* default-status-blocks */ | |
6717 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
6718 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
6719 | ||
6720 | if (CHIP_MODE_IS_4_PORT(bp)) | |
6721 | dsb_idx = BP_FUNC(bp); | |
6722 | else | |
3395a033 | 6723 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
6724 | |
6725 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
6726 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
6727 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
6728 | ||
3395a033 DK |
6729 | /* |
6730 | * igu prods come in chunks of E1HVN_MAX (4) - | |
6731 | * does not matters what is the current chip mode | |
6732 | */ | |
f2e0899f DK |
6733 | for (i = 0; i < (num_segs * E1HVN_MAX); |
6734 | i += E1HVN_MAX) { | |
6735 | addr = IGU_REG_PROD_CONS_MEMORY + | |
6736 | (prod_offset + i)*4; | |
6737 | REG_WR(bp, addr, 0); | |
6738 | } | |
6739 | /* send consumer update with 0 */ | |
6740 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
6741 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6742 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
6743 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6744 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
6745 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6746 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
6747 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6748 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
6749 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6750 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
6751 | } else { | |
6752 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6753 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
6754 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
6755 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
6756 | } | |
6757 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
6758 | ||
6759 | /* !!! these should become driver const once | |
6760 | rf-tool supports split-68 const */ | |
6761 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
6762 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
6763 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
6764 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
6765 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
6766 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
6767 | } | |
34f80b04 | 6768 | } |
34f80b04 | 6769 | |
c14423fe | 6770 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
6771 | REG_WR(bp, 0x2114, 0xffffffff); |
6772 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 6773 | |
f4a66897 VZ |
6774 | if (CHIP_IS_E1x(bp)) { |
6775 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
6776 | main_mem_base = HC_REG_MAIN_MEMORY + | |
6777 | BP_PORT(bp) * (main_mem_size * 4); | |
6778 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
6779 | main_mem_width = 8; | |
6780 | ||
6781 | val = REG_RD(bp, main_mem_prty_clr); | |
6782 | if (val) | |
6783 | DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " | |
6784 | "block during " | |
6785 | "function init (0x%x)!\n", val); | |
6786 | ||
6787 | /* Clear "false" parity errors in MSI-X table */ | |
6788 | for (i = main_mem_base; | |
6789 | i < main_mem_base + main_mem_size * 4; | |
6790 | i += main_mem_width) { | |
6791 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
6792 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
6793 | i, main_mem_width / 4); | |
6794 | } | |
6795 | /* Clear HC parity attention */ | |
6796 | REG_RD(bp, main_mem_prty_clr); | |
6797 | } | |
6798 | ||
619c5cb6 VZ |
6799 | #ifdef BNX2X_STOP_ON_ERROR |
6800 | /* Enable STORMs SP logging */ | |
6801 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
6802 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6803 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
6804 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6805 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
6806 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6807 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
6808 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
6809 | #endif | |
6810 | ||
b7737c9b | 6811 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 6812 | |
34f80b04 EG |
6813 | return 0; |
6814 | } | |
6815 | ||
a2fbb9ea | 6816 | |
9f6c9258 | 6817 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 6818 | { |
a2fbb9ea | 6819 | /* fastpath */ |
b3b83c3f | 6820 | bnx2x_free_fp_mem(bp); |
a2fbb9ea ET |
6821 | /* end of fastpath */ |
6822 | ||
6823 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
523224a3 | 6824 | sizeof(struct host_sp_status_block)); |
a2fbb9ea | 6825 | |
619c5cb6 VZ |
6826 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
6827 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
6828 | ||
a2fbb9ea | 6829 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 6830 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 6831 | |
523224a3 DK |
6832 | BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, |
6833 | bp->context.size); | |
6834 | ||
6835 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); | |
6836 | ||
6837 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 6838 | |
37b091ba | 6839 | #ifdef BCM_CNIC |
619c5cb6 | 6840 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6841 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, |
6842 | sizeof(struct host_hc_status_block_e2)); | |
6843 | else | |
6844 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
6845 | sizeof(struct host_hc_status_block_e1x)); | |
f85582f8 | 6846 | |
523224a3 | 6847 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
a2fbb9ea | 6848 | #endif |
f85582f8 | 6849 | |
7a9b2557 | 6850 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 6851 | |
523224a3 DK |
6852 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
6853 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
619c5cb6 VZ |
6854 | } |
6855 | ||
6856 | static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) | |
6857 | { | |
6858 | int num_groups; | |
6859 | ||
6860 | /* number of eth_queues */ | |
6861 | u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp); | |
6862 | ||
6863 | /* Total number of FW statistics requests = | |
6864 | * 1 for port stats + 1 for PF stats + num_eth_queues */ | |
6865 | bp->fw_stats_num = 2 + num_queue_stats; | |
523224a3 | 6866 | |
619c5cb6 VZ |
6867 | |
6868 | /* Request is built from stats_query_header and an array of | |
6869 | * stats_query_cmd_group each of which contains | |
6870 | * STATS_QUERY_CMD_COUNT rules. The real number or requests is | |
6871 | * configured in the stats_query_header. | |
6872 | */ | |
6873 | num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT + | |
6874 | (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0); | |
6875 | ||
6876 | bp->fw_stats_req_sz = sizeof(struct stats_query_header) + | |
6877 | num_groups * sizeof(struct stats_query_cmd_group); | |
6878 | ||
6879 | /* Data for statistics requests + stats_conter | |
6880 | * | |
6881 | * stats_counter holds per-STORM counters that are incremented | |
6882 | * when STORM has finished with the current request. | |
6883 | */ | |
6884 | bp->fw_stats_data_sz = sizeof(struct per_port_stats) + | |
6885 | sizeof(struct per_pf_stats) + | |
6886 | sizeof(struct per_queue_stats) * num_queue_stats + | |
6887 | sizeof(struct stats_counter); | |
6888 | ||
6889 | BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, | |
6890 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
6891 | ||
6892 | /* Set shortcuts */ | |
6893 | bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; | |
6894 | bp->fw_stats_req_mapping = bp->fw_stats_mapping; | |
6895 | ||
6896 | bp->fw_stats_data = (struct bnx2x_fw_stats_data *) | |
6897 | ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); | |
6898 | ||
6899 | bp->fw_stats_data_mapping = bp->fw_stats_mapping + | |
6900 | bp->fw_stats_req_sz; | |
6901 | return 0; | |
6902 | ||
6903 | alloc_mem_err: | |
6904 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, | |
6905 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
6906 | return -ENOMEM; | |
a2fbb9ea ET |
6907 | } |
6908 | ||
f2e0899f | 6909 | |
9f6c9258 | 6910 | int bnx2x_alloc_mem(struct bnx2x *bp) |
a2fbb9ea | 6911 | { |
523224a3 | 6912 | #ifdef BCM_CNIC |
619c5cb6 VZ |
6913 | if (!CHIP_IS_E1x(bp)) |
6914 | /* size = the status block + ramrod buffers */ | |
f2e0899f DK |
6915 | BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, |
6916 | sizeof(struct host_hc_status_block_e2)); | |
6917 | else | |
6918 | BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, | |
6919 | sizeof(struct host_hc_status_block_e1x)); | |
8badd27a | 6920 | |
523224a3 DK |
6921 | /* allocate searcher T2 table */ |
6922 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
6923 | #endif | |
a2fbb9ea | 6924 | |
8badd27a | 6925 | |
523224a3 DK |
6926 | BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, |
6927 | sizeof(struct host_sp_status_block)); | |
a2fbb9ea | 6928 | |
523224a3 DK |
6929 | BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, |
6930 | sizeof(struct bnx2x_slowpath)); | |
a2fbb9ea | 6931 | |
619c5cb6 VZ |
6932 | /* Allocated memory for FW statistics */ |
6933 | if (bnx2x_alloc_fw_stats_mem(bp)) | |
6934 | goto alloc_mem_err; | |
6935 | ||
6383c0b3 | 6936 | bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); |
f85582f8 | 6937 | |
523224a3 DK |
6938 | BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, |
6939 | bp->context.size); | |
65abd74d | 6940 | |
523224a3 | 6941 | BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); |
65abd74d | 6942 | |
523224a3 DK |
6943 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
6944 | goto alloc_mem_err; | |
65abd74d | 6945 | |
9f6c9258 DK |
6946 | /* Slow path ring */ |
6947 | BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); | |
65abd74d | 6948 | |
523224a3 DK |
6949 | /* EQ */ |
6950 | BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, | |
6951 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
ab532cf3 | 6952 | |
b3b83c3f DK |
6953 | |
6954 | /* fastpath */ | |
6955 | /* need to be done at the end, since it's self adjusting to amount | |
6956 | * of memory available for RSS queues | |
6957 | */ | |
6958 | if (bnx2x_alloc_fp_mem(bp)) | |
6959 | goto alloc_mem_err; | |
9f6c9258 | 6960 | return 0; |
e1510706 | 6961 | |
9f6c9258 DK |
6962 | alloc_mem_err: |
6963 | bnx2x_free_mem(bp); | |
6964 | return -ENOMEM; | |
65abd74d YG |
6965 | } |
6966 | ||
a2fbb9ea ET |
6967 | /* |
6968 | * Init service functions | |
6969 | */ | |
a2fbb9ea | 6970 | |
619c5cb6 VZ |
6971 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
6972 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
6973 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 6974 | { |
619c5cb6 VZ |
6975 | int rc; |
6976 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 6977 | |
619c5cb6 | 6978 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 6979 | |
619c5cb6 VZ |
6980 | /* Fill general parameters */ |
6981 | ramrod_param.vlan_mac_obj = obj; | |
6982 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 6983 | |
619c5cb6 VZ |
6984 | /* Fill a user request section if needed */ |
6985 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
6986 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 6987 | |
619c5cb6 | 6988 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 6989 | |
619c5cb6 VZ |
6990 | /* Set the command: ADD or DEL */ |
6991 | if (set) | |
6992 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
6993 | else | |
6994 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
6995 | } |
6996 | ||
619c5cb6 VZ |
6997 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
6998 | if (rc < 0) | |
6999 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); | |
7000 | return rc; | |
a2fbb9ea ET |
7001 | } |
7002 | ||
619c5cb6 VZ |
7003 | int bnx2x_del_all_macs(struct bnx2x *bp, |
7004 | struct bnx2x_vlan_mac_obj *mac_obj, | |
7005 | int mac_type, bool wait_for_comp) | |
e665bfda | 7006 | { |
619c5cb6 VZ |
7007 | int rc; |
7008 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 7009 | |
619c5cb6 VZ |
7010 | /* Wait for completion of requested */ |
7011 | if (wait_for_comp) | |
7012 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 7013 | |
619c5cb6 VZ |
7014 | /* Set the mac type of addresses we want to clear */ |
7015 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 7016 | |
619c5cb6 VZ |
7017 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
7018 | if (rc < 0) | |
7019 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 7020 | |
619c5cb6 | 7021 | return rc; |
0793f83f DK |
7022 | } |
7023 | ||
619c5cb6 | 7024 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 7025 | { |
619c5cb6 | 7026 | unsigned long ramrod_flags = 0; |
e665bfda | 7027 | |
619c5cb6 | 7028 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
0793f83f | 7029 | |
619c5cb6 VZ |
7030 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
7031 | /* Eth MAC is set on RSS leading client (fp[0]) */ | |
7032 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, | |
7033 | BNX2X_ETH_MAC, &ramrod_flags); | |
e665bfda | 7034 | } |
6e30dd4e | 7035 | |
619c5cb6 | 7036 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 7037 | { |
619c5cb6 | 7038 | return bnx2x_setup_queue(bp, &bp->fp[0], 1); |
993ac7b5 | 7039 | } |
a2fbb9ea | 7040 | |
d6214d7a | 7041 | /** |
e8920674 | 7042 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 7043 | * |
e8920674 | 7044 | * @bp: driver handle |
d6214d7a | 7045 | * |
e8920674 | 7046 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 7047 | */ |
9ee3d37b | 7048 | static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 7049 | { |
9ee3d37b | 7050 | switch (int_mode) { |
d6214d7a DK |
7051 | case INT_MODE_MSI: |
7052 | bnx2x_enable_msi(bp); | |
7053 | /* falling through... */ | |
7054 | case INT_MODE_INTx: | |
6383c0b3 | 7055 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; |
d6214d7a | 7056 | DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); |
ca00392c | 7057 | break; |
d6214d7a DK |
7058 | default: |
7059 | /* Set number of queues according to bp->multi_mode value */ | |
7060 | bnx2x_set_num_queues(bp); | |
ca00392c | 7061 | |
d6214d7a DK |
7062 | DP(NETIF_MSG_IFUP, "set number of queues to %d\n", |
7063 | bp->num_queues); | |
ca00392c | 7064 | |
d6214d7a DK |
7065 | /* if we can't use MSI-X we only need one fp, |
7066 | * so try to enable MSI-X with the requested number of fp's | |
7067 | * and fallback to MSI or legacy INTx with one fp | |
7068 | */ | |
9ee3d37b | 7069 | if (bnx2x_enable_msix(bp)) { |
d6214d7a DK |
7070 | /* failed to enable MSI-X */ |
7071 | if (bp->multi_mode) | |
7072 | DP(NETIF_MSG_IFUP, | |
7073 | "Multi requested but failed to " | |
7074 | "enable MSI-X (%d), " | |
7075 | "set number of queues to %d\n", | |
7076 | bp->num_queues, | |
6383c0b3 AE |
7077 | 1 + NON_ETH_CONTEXT_USE); |
7078 | bp->num_queues = 1 + NON_ETH_CONTEXT_USE; | |
d6214d7a | 7079 | |
9ee3d37b | 7080 | /* Try to enable MSI */ |
d6214d7a DK |
7081 | if (!(bp->flags & DISABLE_MSI_FLAG)) |
7082 | bnx2x_enable_msi(bp); | |
7083 | } | |
9f6c9258 DK |
7084 | break; |
7085 | } | |
a2fbb9ea ET |
7086 | } |
7087 | ||
c2bff63f DK |
7088 | /* must be called prioir to any HW initializations */ |
7089 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) | |
7090 | { | |
7091 | return L2_ILT_LINES(bp); | |
7092 | } | |
7093 | ||
523224a3 DK |
7094 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
7095 | { | |
7096 | struct ilt_client_info *ilt_client; | |
7097 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
7098 | u16 line = 0; | |
7099 | ||
7100 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
7101 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
7102 | ||
7103 | /* CDU */ | |
7104 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
7105 | ilt_client->client_num = ILT_CLIENT_CDU; | |
7106 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
7107 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
7108 | ilt_client->start = line; | |
619c5cb6 | 7109 | line += bnx2x_cid_ilt_lines(bp); |
523224a3 DK |
7110 | #ifdef BCM_CNIC |
7111 | line += CNIC_ILT_LINES; | |
7112 | #endif | |
7113 | ilt_client->end = line - 1; | |
7114 | ||
7115 | DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " | |
7116 | "flags 0x%x, hw psz %d\n", | |
7117 | ilt_client->start, | |
7118 | ilt_client->end, | |
7119 | ilt_client->page_size, | |
7120 | ilt_client->flags, | |
7121 | ilog2(ilt_client->page_size >> 12)); | |
7122 | ||
7123 | /* QM */ | |
7124 | if (QM_INIT(bp->qm_cid_count)) { | |
7125 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
7126 | ilt_client->client_num = ILT_CLIENT_QM; | |
7127 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
7128 | ilt_client->flags = 0; | |
7129 | ilt_client->start = line; | |
7130 | ||
7131 | /* 4 bytes for each cid */ | |
7132 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
7133 | QM_ILT_PAGE_SZ); | |
7134 | ||
7135 | ilt_client->end = line - 1; | |
7136 | ||
7137 | DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " | |
7138 | "flags 0x%x, hw psz %d\n", | |
7139 | ilt_client->start, | |
7140 | ilt_client->end, | |
7141 | ilt_client->page_size, | |
7142 | ilt_client->flags, | |
7143 | ilog2(ilt_client->page_size >> 12)); | |
7144 | ||
7145 | } | |
7146 | /* SRC */ | |
7147 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
7148 | #ifdef BCM_CNIC | |
7149 | ilt_client->client_num = ILT_CLIENT_SRC; | |
7150 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
7151 | ilt_client->flags = 0; | |
7152 | ilt_client->start = line; | |
7153 | line += SRC_ILT_LINES; | |
7154 | ilt_client->end = line - 1; | |
7155 | ||
7156 | DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " | |
7157 | "flags 0x%x, hw psz %d\n", | |
7158 | ilt_client->start, | |
7159 | ilt_client->end, | |
7160 | ilt_client->page_size, | |
7161 | ilt_client->flags, | |
7162 | ilog2(ilt_client->page_size >> 12)); | |
7163 | ||
7164 | #else | |
7165 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7166 | #endif | |
9f6c9258 | 7167 | |
523224a3 DK |
7168 | /* TM */ |
7169 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
7170 | #ifdef BCM_CNIC | |
7171 | ilt_client->client_num = ILT_CLIENT_TM; | |
7172 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
7173 | ilt_client->flags = 0; | |
7174 | ilt_client->start = line; | |
7175 | line += TM_ILT_LINES; | |
7176 | ilt_client->end = line - 1; | |
7177 | ||
7178 | DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " | |
7179 | "flags 0x%x, hw psz %d\n", | |
7180 | ilt_client->start, | |
7181 | ilt_client->end, | |
7182 | ilt_client->page_size, | |
7183 | ilt_client->flags, | |
7184 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 7185 | |
523224a3 DK |
7186 | #else |
7187 | ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); | |
7188 | #endif | |
619c5cb6 | 7189 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 7190 | } |
f85582f8 | 7191 | |
619c5cb6 VZ |
7192 | /** |
7193 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
7194 | * | |
7195 | * @bp: driver handle | |
7196 | * @fp: pointer to fastpath | |
7197 | * @init_params: pointer to parameters structure | |
7198 | * | |
7199 | * parameters configured: | |
7200 | * - HC configuration | |
7201 | * - Queue's CDU context | |
7202 | */ | |
7203 | static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, | |
7204 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) | |
a2fbb9ea | 7205 | { |
6383c0b3 AE |
7206 | |
7207 | u8 cos; | |
619c5cb6 VZ |
7208 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
7209 | if (!IS_FCOE_FP(fp)) { | |
7210 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
7211 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
7212 | ||
7213 | /* If HC is supporterd, enable host coalescing in the transition | |
7214 | * to INIT state. | |
7215 | */ | |
7216 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
7217 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
7218 | ||
7219 | /* HC rate */ | |
7220 | init_params->rx.hc_rate = bp->rx_ticks ? | |
7221 | (1000000 / bp->rx_ticks) : 0; | |
7222 | init_params->tx.hc_rate = bp->tx_ticks ? | |
7223 | (1000000 / bp->tx_ticks) : 0; | |
7224 | ||
7225 | /* FW SB ID */ | |
7226 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
7227 | fp->fw_sb_id; | |
7228 | ||
7229 | /* | |
7230 | * CQ index among the SB indices: FCoE clients uses the default | |
7231 | * SB, therefore it's different. | |
7232 | */ | |
6383c0b3 AE |
7233 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
7234 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
7235 | } |
7236 | ||
6383c0b3 AE |
7237 | /* set maximum number of COSs supported by this queue */ |
7238 | init_params->max_cos = fp->max_cos; | |
7239 | ||
94f05b0f | 7240 | DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
7241 | fp->index, init_params->max_cos); |
7242 | ||
7243 | /* set the context pointers queue object */ | |
7244 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) | |
7245 | init_params->cxts[cos] = | |
7246 | &bp->context.vcxt[fp->txdata[cos].cid].eth; | |
619c5cb6 VZ |
7247 | } |
7248 | ||
6383c0b3 AE |
7249 | int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
7250 | struct bnx2x_queue_state_params *q_params, | |
7251 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
7252 | int tx_index, bool leading) | |
7253 | { | |
7254 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
7255 | ||
7256 | /* Set the command */ | |
7257 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
7258 | ||
7259 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
7260 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
7261 | ||
7262 | /* choose the index of the cid to send the slow path on */ | |
7263 | tx_only_params->cid_index = tx_index; | |
7264 | ||
7265 | /* Set general TX_ONLY_SETUP parameters */ | |
7266 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
7267 | ||
7268 | /* Set Tx TX_ONLY_SETUP parameters */ | |
7269 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
7270 | ||
7271 | DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" | |
7272 | "cos %d, primary cid %d, cid %d, " | |
94f05b0f | 7273 | "client id %d, sp-client id %d, flags %lx\n", |
6383c0b3 AE |
7274 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
7275 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
7276 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
7277 | ||
7278 | /* send the ramrod */ | |
7279 | return bnx2x_queue_state_change(bp, q_params); | |
7280 | } | |
7281 | ||
7282 | ||
619c5cb6 VZ |
7283 | /** |
7284 | * bnx2x_setup_queue - setup queue | |
7285 | * | |
7286 | * @bp: driver handle | |
7287 | * @fp: pointer to fastpath | |
7288 | * @leading: is leading | |
7289 | * | |
7290 | * This function performs 2 steps in a Queue state machine | |
7291 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
7292 | */ | |
7293 | ||
7294 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
7295 | bool leading) | |
7296 | { | |
7297 | struct bnx2x_queue_state_params q_params = {0}; | |
7298 | struct bnx2x_queue_setup_params *setup_params = | |
7299 | &q_params.params.setup; | |
6383c0b3 AE |
7300 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
7301 | &q_params.params.tx_only; | |
a2fbb9ea | 7302 | int rc; |
6383c0b3 AE |
7303 | u8 tx_index; |
7304 | ||
94f05b0f | 7305 | DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 7306 | |
ec6ba945 VZ |
7307 | /* reset IGU state skip FCoE L2 queue */ |
7308 | if (!IS_FCOE_FP(fp)) | |
7309 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 7310 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 7311 | |
619c5cb6 VZ |
7312 | q_params.q_obj = &fp->q_obj; |
7313 | /* We want to wait for completion in this context */ | |
7314 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7315 | |
619c5cb6 VZ |
7316 | /* Prepare the INIT parameters */ |
7317 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 7318 | |
619c5cb6 VZ |
7319 | /* Set the command */ |
7320 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
7321 | ||
7322 | /* Change the state to INIT */ | |
7323 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7324 | if (rc) { | |
6383c0b3 | 7325 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
7326 | return rc; |
7327 | } | |
ec6ba945 | 7328 | |
94f05b0f | 7329 | DP(BNX2X_MSG_SP, "init complete\n"); |
6383c0b3 AE |
7330 | |
7331 | ||
619c5cb6 VZ |
7332 | /* Now move the Queue to the SETUP state... */ |
7333 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 7334 | |
619c5cb6 VZ |
7335 | /* Set QUEUE flags */ |
7336 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 7337 | |
619c5cb6 | 7338 | /* Set general SETUP parameters */ |
6383c0b3 AE |
7339 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
7340 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 7341 | |
6383c0b3 | 7342 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
7343 | &setup_params->rxq_params); |
7344 | ||
6383c0b3 AE |
7345 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
7346 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
7347 | |
7348 | /* Set the command */ | |
7349 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
7350 | ||
7351 | /* Change the state to SETUP */ | |
7352 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
7353 | if (rc) { |
7354 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
7355 | return rc; | |
7356 | } | |
7357 | ||
7358 | /* loop through the relevant tx-only indices */ | |
7359 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7360 | tx_index < fp->max_cos; | |
7361 | tx_index++) { | |
7362 | ||
7363 | /* prepare and send tx-only ramrod*/ | |
7364 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
7365 | tx_only_params, tx_index, leading); | |
7366 | if (rc) { | |
7367 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
7368 | fp->index, tx_index); | |
7369 | return rc; | |
7370 | } | |
7371 | } | |
523224a3 | 7372 | |
34f80b04 | 7373 | return rc; |
a2fbb9ea ET |
7374 | } |
7375 | ||
619c5cb6 | 7376 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 7377 | { |
619c5cb6 | 7378 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 7379 | struct bnx2x_fp_txdata *txdata; |
619c5cb6 | 7380 | struct bnx2x_queue_state_params q_params = {0}; |
6383c0b3 AE |
7381 | int rc, tx_index; |
7382 | ||
94f05b0f | 7383 | DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 7384 | |
619c5cb6 VZ |
7385 | q_params.q_obj = &fp->q_obj; |
7386 | /* We want to wait for completion in this context */ | |
7387 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 7388 | |
6383c0b3 AE |
7389 | |
7390 | /* close tx-only connections */ | |
7391 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
7392 | tx_index < fp->max_cos; | |
7393 | tx_index++){ | |
7394 | ||
7395 | /* ascertain this is a normal queue*/ | |
7396 | txdata = &fp->txdata[tx_index]; | |
7397 | ||
94f05b0f | 7398 | DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n", |
6383c0b3 AE |
7399 | txdata->txq_index); |
7400 | ||
7401 | /* send halt terminate on tx-only connection */ | |
7402 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
7403 | memset(&q_params.params.terminate, 0, | |
7404 | sizeof(q_params.params.terminate)); | |
7405 | q_params.params.terminate.cid_index = tx_index; | |
7406 | ||
7407 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7408 | if (rc) | |
7409 | return rc; | |
7410 | ||
7411 | /* send halt terminate on tx-only connection */ | |
7412 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
7413 | memset(&q_params.params.cfc_del, 0, | |
7414 | sizeof(q_params.params.cfc_del)); | |
7415 | q_params.params.cfc_del.cid_index = tx_index; | |
7416 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7417 | if (rc) | |
7418 | return rc; | |
7419 | } | |
7420 | /* Stop the primary connection: */ | |
7421 | /* ...halt the connection */ | |
619c5cb6 VZ |
7422 | q_params.cmd = BNX2X_Q_CMD_HALT; |
7423 | rc = bnx2x_queue_state_change(bp, &q_params); | |
7424 | if (rc) | |
da5a662a | 7425 | return rc; |
a2fbb9ea | 7426 | |
6383c0b3 | 7427 | /* ...terminate the connection */ |
619c5cb6 | 7428 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
7429 | memset(&q_params.params.terminate, 0, |
7430 | sizeof(q_params.params.terminate)); | |
7431 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
7432 | rc = bnx2x_queue_state_change(bp, &q_params); |
7433 | if (rc) | |
523224a3 | 7434 | return rc; |
6383c0b3 | 7435 | /* ...delete cfc entry */ |
619c5cb6 | 7436 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
7437 | memset(&q_params.params.cfc_del, 0, |
7438 | sizeof(q_params.params.cfc_del)); | |
7439 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 7440 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
7441 | } |
7442 | ||
7443 | ||
34f80b04 EG |
7444 | static void bnx2x_reset_func(struct bnx2x *bp) |
7445 | { | |
7446 | int port = BP_PORT(bp); | |
7447 | int func = BP_FUNC(bp); | |
f2e0899f | 7448 | int i; |
523224a3 DK |
7449 | |
7450 | /* Disable the function in the FW */ | |
7451 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
7452 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
7453 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
7454 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
7455 | ||
7456 | /* FP SBs */ | |
ec6ba945 | 7457 | for_each_eth_queue(bp, i) { |
523224a3 | 7458 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 7459 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
7460 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
7461 | SB_DISABLED); | |
523224a3 DK |
7462 | } |
7463 | ||
619c5cb6 VZ |
7464 | #ifdef BCM_CNIC |
7465 | /* CNIC SB */ | |
7466 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
7467 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), | |
7468 | SB_DISABLED); | |
7469 | #endif | |
523224a3 | 7470 | /* SP SB */ |
619c5cb6 | 7471 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
7472 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
7473 | SB_DISABLED); | |
523224a3 DK |
7474 | |
7475 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
7476 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
7477 | 0); | |
34f80b04 EG |
7478 | |
7479 | /* Configure IGU */ | |
f2e0899f DK |
7480 | if (bp->common.int_block == INT_BLOCK_HC) { |
7481 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7482 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7483 | } else { | |
7484 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
7485 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
7486 | } | |
34f80b04 | 7487 | |
37b091ba MC |
7488 | #ifdef BCM_CNIC |
7489 | /* Disable Timer scan */ | |
7490 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
7491 | /* | |
7492 | * Wait for at least 10ms and up to 2 second for the timers scan to | |
7493 | * complete | |
7494 | */ | |
7495 | for (i = 0; i < 200; i++) { | |
7496 | msleep(10); | |
7497 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) | |
7498 | break; | |
7499 | } | |
7500 | #endif | |
34f80b04 | 7501 | /* Clear ILT */ |
f2e0899f DK |
7502 | bnx2x_clear_func_ilt(bp, func); |
7503 | ||
7504 | /* Timers workaround bug for E2: if this is vnic-3, | |
7505 | * we need to set the entire ilt range for this timers. | |
7506 | */ | |
619c5cb6 | 7507 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
7508 | struct ilt_client_info ilt_cli; |
7509 | /* use dummy TM client */ | |
7510 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
7511 | ilt_cli.start = 0; | |
7512 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
7513 | ilt_cli.client_num = ILT_CLIENT_TM; | |
7514 | ||
7515 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
7516 | } | |
7517 | ||
7518 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 7519 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 7520 | bnx2x_pf_disable(bp); |
523224a3 DK |
7521 | |
7522 | bp->dmae_ready = 0; | |
34f80b04 EG |
7523 | } |
7524 | ||
7525 | static void bnx2x_reset_port(struct bnx2x *bp) | |
7526 | { | |
7527 | int port = BP_PORT(bp); | |
7528 | u32 val; | |
7529 | ||
619c5cb6 VZ |
7530 | /* Reset physical Link */ |
7531 | bnx2x__link_reset(bp); | |
7532 | ||
34f80b04 EG |
7533 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
7534 | ||
7535 | /* Do not rcv packets to BRB */ | |
7536 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
7537 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
7538 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
7539 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
7540 | ||
7541 | /* Configure AEU */ | |
7542 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
7543 | ||
7544 | msleep(100); | |
7545 | /* Check for BRB port occupancy */ | |
7546 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
7547 | if (val) | |
7548 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 7549 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
7550 | |
7551 | /* TODO: Close Doorbell port? */ | |
7552 | } | |
7553 | ||
619c5cb6 | 7554 | static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 7555 | { |
619c5cb6 | 7556 | struct bnx2x_func_state_params func_params = {0}; |
34f80b04 | 7557 | |
619c5cb6 VZ |
7558 | /* Prepare parameters for function state transitions */ |
7559 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 7560 | |
619c5cb6 VZ |
7561 | func_params.f_obj = &bp->func_obj; |
7562 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 7563 | |
619c5cb6 | 7564 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 7565 | |
619c5cb6 | 7566 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
7567 | } |
7568 | ||
619c5cb6 | 7569 | static inline int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 7570 | { |
619c5cb6 VZ |
7571 | struct bnx2x_func_state_params func_params = {0}; |
7572 | int rc; | |
228241eb | 7573 | |
619c5cb6 VZ |
7574 | /* Prepare parameters for function state transitions */ |
7575 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7576 | func_params.f_obj = &bp->func_obj; | |
7577 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 7578 | |
619c5cb6 VZ |
7579 | /* |
7580 | * Try to stop the function the 'good way'. If fails (in case | |
7581 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
7582 | * not in a debug mode, perform a state transaction in order to | |
7583 | * enable further HW_RESET transaction. | |
7584 | */ | |
7585 | rc = bnx2x_func_state_change(bp, &func_params); | |
7586 | if (rc) { | |
34f80b04 | 7587 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 7588 | return rc; |
34f80b04 | 7589 | #else |
619c5cb6 VZ |
7590 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " |
7591 | "transaction\n"); | |
7592 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); | |
7593 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 7594 | #endif |
228241eb | 7595 | } |
a2fbb9ea | 7596 | |
619c5cb6 VZ |
7597 | return 0; |
7598 | } | |
523224a3 | 7599 | |
619c5cb6 VZ |
7600 | /** |
7601 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
7602 | * | |
7603 | * @bp: driver handle | |
7604 | * @unload_mode: requested function's unload mode | |
7605 | * | |
7606 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
7607 | */ | |
7608 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
7609 | { | |
7610 | u32 reset_code = 0; | |
7611 | int port = BP_PORT(bp); | |
3101c2bc | 7612 | |
619c5cb6 | 7613 | /* Select the UNLOAD request mode */ |
65abd74d YG |
7614 | if (unload_mode == UNLOAD_NORMAL) |
7615 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
7616 | ||
7d0446c2 | 7617 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 7618 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 7619 | |
7d0446c2 | 7620 | else if (bp->wol) { |
65abd74d YG |
7621 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
7622 | u8 *mac_addr = bp->dev->dev_addr; | |
7623 | u32 val; | |
f9977903 DK |
7624 | u16 pmc; |
7625 | ||
65abd74d | 7626 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
7627 | * preserve entry 0 which is used by the PMF |
7628 | */ | |
3395a033 | 7629 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
7630 | |
7631 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
7632 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
7633 | ||
7634 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
7635 | (mac_addr[4] << 8) | mac_addr[5]; | |
7636 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
7637 | ||
f9977903 DK |
7638 | /* Enable the PME and clear the status */ |
7639 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); | |
7640 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; | |
7641 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); | |
7642 | ||
65abd74d YG |
7643 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
7644 | ||
7645 | } else | |
7646 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 7647 | |
619c5cb6 VZ |
7648 | /* Send the request to the MCP */ |
7649 | if (!BP_NOMCP(bp)) | |
7650 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
7651 | else { | |
7652 | int path = BP_PATH(bp); | |
7653 | ||
7654 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " | |
7655 | "%d, %d, %d\n", | |
7656 | path, load_count[path][0], load_count[path][1], | |
7657 | load_count[path][2]); | |
7658 | load_count[path][0]--; | |
7659 | load_count[path][1 + port]--; | |
7660 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " | |
7661 | "%d, %d, %d\n", | |
7662 | path, load_count[path][0], load_count[path][1], | |
7663 | load_count[path][2]); | |
7664 | if (load_count[path][0] == 0) | |
7665 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; | |
7666 | else if (load_count[path][1 + port] == 0) | |
7667 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; | |
7668 | else | |
7669 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
7670 | } | |
7671 | ||
7672 | return reset_code; | |
7673 | } | |
7674 | ||
7675 | /** | |
7676 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
7677 | * | |
7678 | * @bp: driver handle | |
7679 | */ | |
7680 | void bnx2x_send_unload_done(struct bnx2x *bp) | |
7681 | { | |
7682 | /* Report UNLOAD_DONE to MCP */ | |
7683 | if (!BP_NOMCP(bp)) | |
7684 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
7685 | } | |
7686 | ||
6debea87 DK |
7687 | static inline int bnx2x_func_wait_started(struct bnx2x *bp) |
7688 | { | |
7689 | int tout = 50; | |
7690 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
7691 | ||
7692 | if (!bp->port.pmf) | |
7693 | return 0; | |
7694 | ||
7695 | /* | |
7696 | * (assumption: No Attention from MCP at this stage) | |
7697 | * PMF probably in the middle of TXdisable/enable transaction | |
7698 | * 1. Sync IRS for default SB | |
7699 | * 2. Sync SP queue - this guarantes us that attention handling started | |
7700 | * 3. Wait, that TXdisable/enable transaction completes | |
7701 | * | |
7702 | * 1+2 guranty that if DCBx attention was scheduled it already changed | |
7703 | * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy | |
7704 | * received complettion for the transaction the state is TX_STOPPED. | |
7705 | * State will return to STARTED after completion of TX_STOPPED-->STARTED | |
7706 | * transaction. | |
7707 | */ | |
7708 | ||
7709 | /* make sure default SB ISR is done */ | |
7710 | if (msix) | |
7711 | synchronize_irq(bp->msix_table[0].vector); | |
7712 | else | |
7713 | synchronize_irq(bp->pdev->irq); | |
7714 | ||
7715 | flush_workqueue(bnx2x_wq); | |
7716 | ||
7717 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
7718 | BNX2X_F_STATE_STARTED && tout--) | |
7719 | msleep(20); | |
7720 | ||
7721 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
7722 | BNX2X_F_STATE_STARTED) { | |
7723 | #ifdef BNX2X_STOP_ON_ERROR | |
7724 | return -EBUSY; | |
7725 | #else | |
7726 | /* | |
7727 | * Failed to complete the transaction in a "good way" | |
7728 | * Force both transactions with CLR bit | |
7729 | */ | |
7730 | struct bnx2x_func_state_params func_params = {0}; | |
7731 | ||
7732 | DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " | |
7733 | "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); | |
7734 | ||
7735 | func_params.f_obj = &bp->func_obj; | |
7736 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
7737 | &func_params.ramrod_flags); | |
7738 | ||
7739 | /* STARTED-->TX_ST0PPED */ | |
7740 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
7741 | bnx2x_func_state_change(bp, &func_params); | |
7742 | ||
7743 | /* TX_ST0PPED-->STARTED */ | |
7744 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
7745 | return bnx2x_func_state_change(bp, &func_params); | |
7746 | #endif | |
7747 | } | |
7748 | ||
7749 | return 0; | |
7750 | } | |
7751 | ||
619c5cb6 VZ |
7752 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) |
7753 | { | |
7754 | int port = BP_PORT(bp); | |
6383c0b3 AE |
7755 | int i, rc = 0; |
7756 | u8 cos; | |
619c5cb6 VZ |
7757 | struct bnx2x_mcast_ramrod_params rparam = {0}; |
7758 | u32 reset_code; | |
7759 | ||
7760 | /* Wait until tx fastpath tasks complete */ | |
7761 | for_each_tx_queue(bp, i) { | |
7762 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
7763 | ||
6383c0b3 AE |
7764 | for_each_cos_in_tx_queue(fp, cos) |
7765 | rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); | |
619c5cb6 VZ |
7766 | #ifdef BNX2X_STOP_ON_ERROR |
7767 | if (rc) | |
7768 | return; | |
7769 | #endif | |
7770 | } | |
7771 | ||
7772 | /* Give HW time to discard old tx messages */ | |
7773 | usleep_range(1000, 1000); | |
7774 | ||
7775 | /* Clean all ETH MACs */ | |
7776 | rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); | |
7777 | if (rc < 0) | |
7778 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
7779 | ||
7780 | /* Clean up UC list */ | |
7781 | rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, | |
7782 | true); | |
7783 | if (rc < 0) | |
7784 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " | |
7785 | "%d\n", rc); | |
7786 | ||
7787 | /* Disable LLH */ | |
7788 | if (!CHIP_IS_E1(bp)) | |
7789 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
7790 | ||
7791 | /* Set "drop all" (stop Rx). | |
7792 | * We need to take a netif_addr_lock() here in order to prevent | |
7793 | * a race between the completion code and this code. | |
7794 | */ | |
7795 | netif_addr_lock_bh(bp->dev); | |
7796 | /* Schedule the rx_mode command */ | |
7797 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
7798 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
7799 | else | |
7800 | bnx2x_set_storm_rx_mode(bp); | |
7801 | ||
7802 | /* Cleanup multicast configuration */ | |
7803 | rparam.mcast_obj = &bp->mcast_obj; | |
7804 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
7805 | if (rc < 0) | |
7806 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
7807 | ||
7808 | netif_addr_unlock_bh(bp->dev); | |
7809 | ||
7810 | ||
6debea87 DK |
7811 | |
7812 | /* | |
7813 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
7814 | * this function should perform FUNC, PORT or COMMON HW | |
7815 | * reset. | |
7816 | */ | |
7817 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
7818 | ||
7819 | /* | |
7820 | * (assumption: No Attention from MCP at this stage) | |
7821 | * PMF probably in the middle of TXdisable/enable transaction | |
7822 | */ | |
7823 | rc = bnx2x_func_wait_started(bp); | |
7824 | if (rc) { | |
7825 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
7826 | #ifdef BNX2X_STOP_ON_ERROR | |
7827 | return; | |
7828 | #endif | |
7829 | } | |
7830 | ||
34f80b04 | 7831 | /* Close multi and leading connections |
619c5cb6 VZ |
7832 | * Completions for ramrods are collected in a synchronous way |
7833 | */ | |
523224a3 | 7834 | for_each_queue(bp, i) |
619c5cb6 | 7835 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
7836 | #ifdef BNX2X_STOP_ON_ERROR |
7837 | return; | |
7838 | #else | |
228241eb | 7839 | goto unload_error; |
523224a3 | 7840 | #endif |
619c5cb6 VZ |
7841 | /* If SP settings didn't get completed so far - something |
7842 | * very wrong has happen. | |
7843 | */ | |
7844 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
7845 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 7846 | |
619c5cb6 VZ |
7847 | #ifndef BNX2X_STOP_ON_ERROR |
7848 | unload_error: | |
7849 | #endif | |
523224a3 | 7850 | rc = bnx2x_func_stop(bp); |
da5a662a | 7851 | if (rc) { |
523224a3 | 7852 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 7853 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 7854 | return; |
523224a3 | 7855 | #endif |
34f80b04 | 7856 | } |
a2fbb9ea | 7857 | |
523224a3 DK |
7858 | /* Disable HW interrupts, NAPI */ |
7859 | bnx2x_netif_stop(bp, 1); | |
7860 | ||
7861 | /* Release IRQs */ | |
d6214d7a | 7862 | bnx2x_free_irq(bp); |
523224a3 | 7863 | |
a2fbb9ea | 7864 | /* Reset the chip */ |
619c5cb6 VZ |
7865 | rc = bnx2x_reset_hw(bp, reset_code); |
7866 | if (rc) | |
7867 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 7868 | |
356e2385 | 7869 | |
619c5cb6 VZ |
7870 | /* Report UNLOAD_DONE to MCP */ |
7871 | bnx2x_send_unload_done(bp); | |
72fd0718 VZ |
7872 | } |
7873 | ||
9f6c9258 | 7874 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
7875 | { |
7876 | u32 val; | |
7877 | ||
7878 | DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); | |
7879 | ||
7880 | if (CHIP_IS_E1(bp)) { | |
7881 | int port = BP_PORT(bp); | |
7882 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
7883 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
7884 | ||
7885 | val = REG_RD(bp, addr); | |
7886 | val &= ~(0x300); | |
7887 | REG_WR(bp, addr, val); | |
619c5cb6 | 7888 | } else { |
72fd0718 VZ |
7889 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
7890 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
7891 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
7892 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
7893 | } | |
7894 | } | |
7895 | ||
72fd0718 VZ |
7896 | /* Close gates #2, #3 and #4: */ |
7897 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
7898 | { | |
c9ee9206 | 7899 | u32 val; |
72fd0718 VZ |
7900 | |
7901 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
7902 | if (!CHIP_IS_E1(bp)) { | |
7903 | /* #4 */ | |
c9ee9206 | 7904 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 7905 | /* #2 */ |
c9ee9206 | 7906 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
7907 | } |
7908 | ||
7909 | /* #3 */ | |
c9ee9206 VZ |
7910 | if (CHIP_IS_E1x(bp)) { |
7911 | /* Prevent interrupts from HC on both ports */ | |
7912 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
7913 | REG_WR(bp, HC_REG_CONFIG_1, | |
7914 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
7915 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
7916 | ||
7917 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
7918 | REG_WR(bp, HC_REG_CONFIG_0, | |
7919 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
7920 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
7921 | } else { | |
7922 | /* Prevent incomming interrupts in IGU */ | |
7923 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); | |
7924 | ||
7925 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
7926 | (!close) ? | |
7927 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
7928 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
7929 | } | |
72fd0718 VZ |
7930 | |
7931 | DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", | |
7932 | close ? "closing" : "opening"); | |
7933 | mmiowb(); | |
7934 | } | |
7935 | ||
7936 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
7937 | ||
7938 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
7939 | { | |
7940 | /* Do some magic... */ | |
7941 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
7942 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
7943 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
7944 | } | |
7945 | ||
e8920674 DK |
7946 | /** |
7947 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 7948 | * |
e8920674 DK |
7949 | * @bp: driver handle |
7950 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
7951 | */ |
7952 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
7953 | { | |
7954 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
7955 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
7956 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
7957 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
7958 | } | |
7959 | ||
f85582f8 | 7960 | /** |
e8920674 | 7961 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 7962 | * |
e8920674 DK |
7963 | * @bp: driver handle |
7964 | * @magic_val: old value of 'magic' bit. | |
7965 | * | |
7966 | * Takes care of CLP configurations. | |
72fd0718 VZ |
7967 | */ |
7968 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
7969 | { | |
7970 | u32 shmem; | |
7971 | u32 validity_offset; | |
7972 | ||
7973 | DP(NETIF_MSG_HW, "Starting\n"); | |
7974 | ||
7975 | /* Set `magic' bit in order to save MF config */ | |
7976 | if (!CHIP_IS_E1(bp)) | |
7977 | bnx2x_clp_reset_prep(bp, magic_val); | |
7978 | ||
7979 | /* Get shmem offset */ | |
7980 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
7981 | validity_offset = offsetof(struct shmem_region, validity_map[0]); | |
7982 | ||
7983 | /* Clear validity map flags */ | |
7984 | if (shmem > 0) | |
7985 | REG_WR(bp, shmem + validity_offset, 0); | |
7986 | } | |
7987 | ||
7988 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
7989 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
7990 | ||
e8920674 DK |
7991 | /** |
7992 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 7993 | * |
e8920674 | 7994 | * @bp: driver handle |
72fd0718 VZ |
7995 | */ |
7996 | static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) | |
7997 | { | |
7998 | /* special handling for emulation and FPGA, | |
7999 | wait 10 times longer */ | |
8000 | if (CHIP_REV_IS_SLOW(bp)) | |
8001 | msleep(MCP_ONE_TIMEOUT*10); | |
8002 | else | |
8003 | msleep(MCP_ONE_TIMEOUT); | |
8004 | } | |
8005 | ||
1b6e2ceb DK |
8006 | /* |
8007 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
8008 | */ | |
8009 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 8010 | { |
1b6e2ceb DK |
8011 | int cnt = 0; |
8012 | u32 val = 0; | |
72fd0718 | 8013 | |
1b6e2ceb DK |
8014 | do { |
8015 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
8016 | if (bp->common.shmem_base) { | |
8017 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
8018 | if (val & SHR_MEM_VALIDITY_MB) | |
8019 | return 0; | |
8020 | } | |
72fd0718 | 8021 | |
1b6e2ceb | 8022 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 8023 | |
1b6e2ceb | 8024 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 8025 | |
1b6e2ceb | 8026 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 8027 | |
1b6e2ceb DK |
8028 | return -ENODEV; |
8029 | } | |
72fd0718 | 8030 | |
1b6e2ceb DK |
8031 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
8032 | { | |
8033 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 8034 | |
72fd0718 VZ |
8035 | /* Restore the `magic' bit value */ |
8036 | if (!CHIP_IS_E1(bp)) | |
8037 | bnx2x_clp_reset_done(bp, magic_val); | |
8038 | ||
8039 | return rc; | |
8040 | } | |
8041 | ||
8042 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
8043 | { | |
8044 | if (!CHIP_IS_E1(bp)) { | |
8045 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
8046 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
8047 | mmiowb(); |
8048 | } | |
8049 | } | |
8050 | ||
8051 | /* | |
8052 | * Reset the whole chip except for: | |
8053 | * - PCIE core | |
8054 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
8055 | * one reset bit) | |
8056 | * - IGU | |
8057 | * - MISC (including AEU) | |
8058 | * - GRC | |
8059 | * - RBCN, RBCP | |
8060 | */ | |
c9ee9206 | 8061 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
8062 | { |
8063 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 8064 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
8065 | |
8066 | /* | |
8067 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
8068 | * (per chip) blocks. | |
8069 | */ | |
8070 | global_bits2 = | |
8071 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
8072 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 8073 | |
8736c826 | 8074 | /* Don't reset the following blocks */ |
72fd0718 VZ |
8075 | not_reset_mask1 = |
8076 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
8077 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
8078 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
8079 | ||
8080 | not_reset_mask2 = | |
c9ee9206 | 8081 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
8082 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
8083 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
8084 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
8085 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
8086 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
8087 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
8088 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
8089 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
8090 | MISC_REGISTERS_RESET_REG_2_PGLC; | |
72fd0718 | 8091 | |
8736c826 VZ |
8092 | /* |
8093 | * Keep the following blocks in reset: | |
8094 | * - all xxMACs are handled by the bnx2x_link code. | |
8095 | */ | |
8096 | stay_reset2 = | |
8097 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
8098 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
8099 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
8100 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
8101 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
8102 | MISC_REGISTERS_RESET_REG_2_UMAC1 | | |
8103 | MISC_REGISTERS_RESET_REG_2_XMAC | | |
8104 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
8105 | ||
8106 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
8107 | reset_mask1 = 0xffffffff; |
8108 | ||
8109 | if (CHIP_IS_E1(bp)) | |
8110 | reset_mask2 = 0xffff; | |
8736c826 | 8111 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 8112 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
8113 | else if (CHIP_IS_E2(bp)) |
8114 | reset_mask2 = 0xfffff; | |
8115 | else /* CHIP_IS_E3 */ | |
8116 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
8117 | |
8118 | /* Don't reset global blocks unless we need to */ | |
8119 | if (!global) | |
8120 | reset_mask2 &= ~global_bits2; | |
8121 | ||
8122 | /* | |
8123 | * In case of attention in the QM, we need to reset PXP | |
8124 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
8125 | * because otherwise QM reset would release 'close the gates' shortly | |
8126 | * before resetting the PXP, then the PSWRQ would send a write | |
8127 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
8128 | * read the payload data from PSWWR, but PSWWR would not | |
8129 | * respond. The write queue in PGLUE would stuck, dmae commands | |
8130 | * would not return. Therefore it's important to reset the second | |
8131 | * reset register (containing the | |
8132 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
8133 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
8134 | * bit). | |
8135 | */ | |
72fd0718 VZ |
8136 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
8137 | reset_mask2 & (~not_reset_mask2)); | |
8138 | ||
c9ee9206 VZ |
8139 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
8140 | reset_mask1 & (~not_reset_mask1)); | |
8141 | ||
72fd0718 VZ |
8142 | barrier(); |
8143 | mmiowb(); | |
8144 | ||
8736c826 VZ |
8145 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
8146 | reset_mask2 & (~stay_reset2)); | |
8147 | ||
8148 | barrier(); | |
8149 | mmiowb(); | |
8150 | ||
c9ee9206 | 8151 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
8152 | mmiowb(); |
8153 | } | |
8154 | ||
c9ee9206 VZ |
8155 | /** |
8156 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
8157 | * It should get cleared in no more than 1s. | |
8158 | * | |
8159 | * @bp: driver handle | |
8160 | * | |
8161 | * It should get cleared in no more than 1s. Returns 0 if | |
8162 | * pending writes bit gets cleared. | |
8163 | */ | |
8164 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
8165 | { | |
8166 | u32 cnt = 1000; | |
8167 | u32 pend_bits = 0; | |
8168 | ||
8169 | do { | |
8170 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
8171 | ||
8172 | if (pend_bits == 0) | |
8173 | break; | |
8174 | ||
8175 | usleep_range(1000, 1000); | |
8176 | } while (cnt-- > 0); | |
8177 | ||
8178 | if (cnt <= 0) { | |
8179 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
8180 | pend_bits); | |
8181 | return -EBUSY; | |
8182 | } | |
8183 | ||
8184 | return 0; | |
8185 | } | |
8186 | ||
8187 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
8188 | { |
8189 | int cnt = 1000; | |
8190 | u32 val = 0; | |
8191 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
8192 | ||
8193 | ||
8194 | /* Empty the Tetris buffer, wait for 1s */ | |
8195 | do { | |
8196 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
8197 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
8198 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
8199 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
8200 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
8201 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && | |
8202 | ((port_is_idle_0 & 0x1) == 0x1) && | |
8203 | ((port_is_idle_1 & 0x1) == 0x1) && | |
8204 | (pgl_exp_rom2 == 0xffffffff)) | |
8205 | break; | |
c9ee9206 | 8206 | usleep_range(1000, 1000); |
72fd0718 VZ |
8207 | } while (cnt-- > 0); |
8208 | ||
8209 | if (cnt <= 0) { | |
8210 | DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" | |
8211 | " are still" | |
8212 | " outstanding read requests after 1s!\n"); | |
8213 | DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," | |
8214 | " port_is_idle_0=0x%08x," | |
8215 | " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
8216 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, | |
8217 | pgl_exp_rom2); | |
8218 | return -EAGAIN; | |
8219 | } | |
8220 | ||
8221 | barrier(); | |
8222 | ||
8223 | /* Close gates #2, #3 and #4 */ | |
8224 | bnx2x_set_234_gates(bp, true); | |
8225 | ||
c9ee9206 VZ |
8226 | /* Poll for IGU VQs for 57712 and newer chips */ |
8227 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
8228 | return -EAGAIN; | |
8229 | ||
8230 | ||
72fd0718 VZ |
8231 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
8232 | ||
8233 | /* Clear "unprepared" bit */ | |
8234 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
8235 | barrier(); | |
8236 | ||
8237 | /* Make sure all is written to the chip before the reset */ | |
8238 | mmiowb(); | |
8239 | ||
8240 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
8241 | * PSWHST, GRC and PSWRD Tetris buffer. | |
8242 | */ | |
c9ee9206 | 8243 | usleep_range(1000, 1000); |
72fd0718 VZ |
8244 | |
8245 | /* Prepare to chip reset: */ | |
8246 | /* MCP */ | |
c9ee9206 VZ |
8247 | if (global) |
8248 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
8249 | |
8250 | /* PXP */ | |
8251 | bnx2x_pxp_prep(bp); | |
8252 | barrier(); | |
8253 | ||
8254 | /* reset the chip */ | |
c9ee9206 | 8255 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
8256 | barrier(); |
8257 | ||
8258 | /* Recover after reset: */ | |
8259 | /* MCP */ | |
c9ee9206 | 8260 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
8261 | return -EAGAIN; |
8262 | ||
c9ee9206 VZ |
8263 | /* TBD: Add resetting the NO_MCP mode DB here */ |
8264 | ||
72fd0718 VZ |
8265 | /* PXP */ |
8266 | bnx2x_pxp_prep(bp); | |
8267 | ||
8268 | /* Open the gates #2, #3 and #4 */ | |
8269 | bnx2x_set_234_gates(bp, false); | |
8270 | ||
8271 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
8272 | * reset state, re-enable attentions. */ | |
8273 | ||
a2fbb9ea ET |
8274 | return 0; |
8275 | } | |
8276 | ||
c9ee9206 | 8277 | int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
8278 | { |
8279 | int rc = 0; | |
c9ee9206 VZ |
8280 | bool global = bnx2x_reset_is_global(bp); |
8281 | ||
72fd0718 | 8282 | /* Try to recover after the failure */ |
c9ee9206 VZ |
8283 | if (bnx2x_process_kill(bp, global)) { |
8284 | netdev_err(bp->dev, "Something bad had happen on engine %d! " | |
8285 | "Aii!\n", BP_PATH(bp)); | |
72fd0718 VZ |
8286 | rc = -EAGAIN; |
8287 | goto exit_leader_reset; | |
8288 | } | |
8289 | ||
c9ee9206 VZ |
8290 | /* |
8291 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
8292 | * state. | |
8293 | */ | |
72fd0718 | 8294 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
8295 | if (global) |
8296 | bnx2x_clear_reset_global(bp); | |
72fd0718 VZ |
8297 | |
8298 | exit_leader_reset: | |
8299 | bp->is_leader = 0; | |
c9ee9206 VZ |
8300 | bnx2x_release_leader_lock(bp); |
8301 | smp_mb(); | |
72fd0718 VZ |
8302 | return rc; |
8303 | } | |
8304 | ||
c9ee9206 VZ |
8305 | static inline void bnx2x_recovery_failed(struct bnx2x *bp) |
8306 | { | |
8307 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
8308 | ||
8309 | /* Disconnect this device */ | |
8310 | netif_device_detach(bp->dev); | |
8311 | ||
8312 | /* | |
8313 | * Block ifup for all function on this engine until "process kill" | |
8314 | * or power cycle. | |
8315 | */ | |
8316 | bnx2x_set_reset_in_progress(bp); | |
8317 | ||
8318 | /* Shut down the power */ | |
8319 | bnx2x_set_power_state(bp, PCI_D3hot); | |
8320 | ||
8321 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
8322 | ||
8323 | smp_mb(); | |
8324 | } | |
8325 | ||
8326 | /* | |
8327 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 8328 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
8329 | * will never be called when netif_running(bp->dev) is false. |
8330 | */ | |
8331 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
8332 | { | |
c9ee9206 VZ |
8333 | bool global = false; |
8334 | ||
72fd0718 VZ |
8335 | DP(NETIF_MSG_HW, "Handling parity\n"); |
8336 | while (1) { | |
8337 | switch (bp->recovery_state) { | |
8338 | case BNX2X_RECOVERY_INIT: | |
8339 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
c9ee9206 VZ |
8340 | bnx2x_chk_parity_attn(bp, &global, false); |
8341 | ||
72fd0718 | 8342 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
8343 | if (bnx2x_trylock_leader_lock(bp)) { |
8344 | bnx2x_set_reset_in_progress(bp); | |
8345 | /* | |
8346 | * Check if there is a global attention and if | |
8347 | * there was a global attention, set the global | |
8348 | * reset bit. | |
8349 | */ | |
8350 | ||
8351 | if (global) | |
8352 | bnx2x_set_reset_global(bp); | |
8353 | ||
72fd0718 | 8354 | bp->is_leader = 1; |
c9ee9206 | 8355 | } |
72fd0718 VZ |
8356 | |
8357 | /* Stop the driver */ | |
8358 | /* If interface has been removed - break */ | |
8359 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) | |
8360 | return; | |
8361 | ||
8362 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 VZ |
8363 | |
8364 | /* | |
8365 | * Reset MCP command sequence number and MCP mail box | |
8366 | * sequence as we are going to reset the MCP. | |
8367 | */ | |
8368 | if (global) { | |
8369 | bp->fw_seq = 0; | |
8370 | bp->fw_drv_pulse_wr_seq = 0; | |
8371 | } | |
8372 | ||
8373 | /* Ensure "is_leader", MCP command sequence and | |
8374 | * "recovery_state" update values are seen on other | |
8375 | * CPUs. | |
72fd0718 | 8376 | */ |
c9ee9206 | 8377 | smp_mb(); |
72fd0718 VZ |
8378 | break; |
8379 | ||
8380 | case BNX2X_RECOVERY_WAIT: | |
8381 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
8382 | if (bp->is_leader) { | |
c9ee9206 VZ |
8383 | int other_engine = BP_PATH(bp) ? 0 : 1; |
8384 | u32 other_load_counter = | |
8385 | bnx2x_get_load_cnt(bp, other_engine); | |
8386 | u32 load_counter = | |
8387 | bnx2x_get_load_cnt(bp, BP_PATH(bp)); | |
8388 | global = bnx2x_reset_is_global(bp); | |
8389 | ||
8390 | /* | |
8391 | * In case of a parity in a global block, let | |
8392 | * the first leader that performs a | |
8393 | * leader_reset() reset the global blocks in | |
8394 | * order to clear global attentions. Otherwise | |
8395 | * the the gates will remain closed for that | |
8396 | * engine. | |
8397 | */ | |
8398 | if (load_counter || | |
8399 | (global && other_load_counter)) { | |
72fd0718 VZ |
8400 | /* Wait until all other functions get |
8401 | * down. | |
8402 | */ | |
7be08a72 | 8403 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
8404 | HZ/10); |
8405 | return; | |
8406 | } else { | |
8407 | /* If all other functions got down - | |
8408 | * try to bring the chip back to | |
8409 | * normal. In any case it's an exit | |
8410 | * point for a leader. | |
8411 | */ | |
c9ee9206 VZ |
8412 | if (bnx2x_leader_reset(bp)) { |
8413 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
8414 | return; |
8415 | } | |
8416 | ||
c9ee9206 VZ |
8417 | /* If we are here, means that the |
8418 | * leader has succeeded and doesn't | |
8419 | * want to be a leader any more. Try | |
8420 | * to continue as a none-leader. | |
8421 | */ | |
8422 | break; | |
72fd0718 VZ |
8423 | } |
8424 | } else { /* non-leader */ | |
c9ee9206 | 8425 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
8426 | /* Try to get a LEADER_LOCK HW lock as |
8427 | * long as a former leader may have | |
8428 | * been unloaded by the user or | |
8429 | * released a leadership by another | |
8430 | * reason. | |
8431 | */ | |
c9ee9206 | 8432 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
8433 | /* I'm a leader now! Restart a |
8434 | * switch case. | |
8435 | */ | |
8436 | bp->is_leader = 1; | |
8437 | break; | |
8438 | } | |
8439 | ||
7be08a72 | 8440 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
8441 | HZ/10); |
8442 | return; | |
8443 | ||
c9ee9206 VZ |
8444 | } else { |
8445 | /* | |
8446 | * If there was a global attention, wait | |
8447 | * for it to be cleared. | |
8448 | */ | |
8449 | if (bnx2x_reset_is_global(bp)) { | |
8450 | schedule_delayed_work( | |
7be08a72 AE |
8451 | &bp->sp_rtnl_task, |
8452 | HZ/10); | |
c9ee9206 VZ |
8453 | return; |
8454 | } | |
8455 | ||
8456 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) | |
8457 | bnx2x_recovery_failed(bp); | |
8458 | else { | |
8459 | bp->recovery_state = | |
8460 | BNX2X_RECOVERY_DONE; | |
8461 | smp_mb(); | |
8462 | } | |
8463 | ||
72fd0718 VZ |
8464 | return; |
8465 | } | |
8466 | } | |
8467 | default: | |
8468 | return; | |
8469 | } | |
8470 | } | |
8471 | } | |
8472 | ||
8473 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is | |
8474 | * scheduled on a general queue in order to prevent a dead lock. | |
8475 | */ | |
7be08a72 | 8476 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 8477 | { |
7be08a72 | 8478 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
8479 | |
8480 | rtnl_lock(); | |
8481 | ||
8482 | if (!netif_running(bp->dev)) | |
7be08a72 AE |
8483 | goto sp_rtnl_exit; |
8484 | ||
8485 | /* if stop on error is defined no recovery flows should be executed */ | |
8486 | #ifdef BNX2X_STOP_ON_ERROR | |
8487 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " | |
8488 | "so reset not done to allow debug dump,\n" | |
8489 | "you will need to reboot when done\n"); | |
b1fb8740 | 8490 | goto sp_rtnl_not_reset; |
7be08a72 | 8491 | #endif |
34f80b04 | 8492 | |
7be08a72 AE |
8493 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
8494 | /* | |
b1fb8740 VZ |
8495 | * Clear all pending SP commands as we are going to reset the |
8496 | * function anyway. | |
7be08a72 | 8497 | */ |
b1fb8740 VZ |
8498 | bp->sp_rtnl_state = 0; |
8499 | smp_mb(); | |
8500 | ||
72fd0718 | 8501 | bnx2x_parity_recover(bp); |
b1fb8740 VZ |
8502 | |
8503 | goto sp_rtnl_exit; | |
8504 | } | |
8505 | ||
8506 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
8507 | /* | |
8508 | * Clear all pending SP commands as we are going to reset the | |
8509 | * function anyway. | |
8510 | */ | |
8511 | bp->sp_rtnl_state = 0; | |
8512 | smp_mb(); | |
8513 | ||
72fd0718 VZ |
8514 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); |
8515 | bnx2x_nic_load(bp, LOAD_NORMAL); | |
b1fb8740 VZ |
8516 | |
8517 | goto sp_rtnl_exit; | |
72fd0718 | 8518 | } |
b1fb8740 VZ |
8519 | #ifdef BNX2X_STOP_ON_ERROR |
8520 | sp_rtnl_not_reset: | |
8521 | #endif | |
8522 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
8523 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
34f80b04 | 8524 | |
7be08a72 | 8525 | sp_rtnl_exit: |
34f80b04 EG |
8526 | rtnl_unlock(); |
8527 | } | |
8528 | ||
a2fbb9ea ET |
8529 | /* end of nic load/unload */ |
8530 | ||
3deb8167 YR |
8531 | static void bnx2x_period_task(struct work_struct *work) |
8532 | { | |
8533 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
8534 | ||
8535 | if (!netif_running(bp->dev)) | |
8536 | goto period_task_exit; | |
8537 | ||
8538 | if (CHIP_REV_IS_SLOW(bp)) { | |
8539 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
8540 | goto period_task_exit; | |
8541 | } | |
8542 | ||
8543 | bnx2x_acquire_phy_lock(bp); | |
8544 | /* | |
8545 | * The barrier is needed to ensure the ordering between the writing to | |
8546 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
8547 | * the reading here. | |
8548 | */ | |
8549 | smp_mb(); | |
8550 | if (bp->port.pmf) { | |
8551 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
8552 | ||
8553 | /* Re-queue task in 1 sec */ | |
8554 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
8555 | } | |
8556 | ||
8557 | bnx2x_release_phy_lock(bp); | |
8558 | period_task_exit: | |
8559 | return; | |
8560 | } | |
8561 | ||
a2fbb9ea ET |
8562 | /* |
8563 | * Init service functions | |
8564 | */ | |
8565 | ||
8d96286a | 8566 | static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
8567 | { |
8568 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
8569 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
8570 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
8571 | } |
8572 | ||
f2e0899f | 8573 | static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) |
f1ef27ef | 8574 | { |
f2e0899f | 8575 | u32 reg = bnx2x_get_pretend_reg(bp); |
f1ef27ef EG |
8576 | |
8577 | /* Flush all outstanding writes */ | |
8578 | mmiowb(); | |
8579 | ||
8580 | /* Pretend to be function 0 */ | |
8581 | REG_WR(bp, reg, 0); | |
f2e0899f | 8582 | REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ |
f1ef27ef EG |
8583 | |
8584 | /* From now we are in the "like-E1" mode */ | |
8585 | bnx2x_int_disable(bp); | |
8586 | ||
8587 | /* Flush all outstanding writes */ | |
8588 | mmiowb(); | |
8589 | ||
f2e0899f DK |
8590 | /* Restore the original function */ |
8591 | REG_WR(bp, reg, BP_ABS_FUNC(bp)); | |
8592 | REG_RD(bp, reg); | |
f1ef27ef EG |
8593 | } |
8594 | ||
f2e0899f | 8595 | static inline void bnx2x_undi_int_disable(struct bnx2x *bp) |
f1ef27ef | 8596 | { |
f2e0899f | 8597 | if (CHIP_IS_E1(bp)) |
f1ef27ef | 8598 | bnx2x_int_disable(bp); |
f2e0899f DK |
8599 | else |
8600 | bnx2x_undi_int_disable_e1h(bp); | |
f1ef27ef EG |
8601 | } |
8602 | ||
34f80b04 EG |
8603 | static void __devinit bnx2x_undi_unload(struct bnx2x *bp) |
8604 | { | |
8605 | u32 val; | |
8606 | ||
8607 | /* Check if there is any driver already loaded */ | |
8608 | val = REG_RD(bp, MISC_REG_UNPREPARED); | |
8609 | if (val == 0x1) { | |
7a06a122 DK |
8610 | |
8611 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | |
8612 | /* | |
8613 | * Check if it is the UNDI driver | |
34f80b04 EG |
8614 | * UNDI driver initializes CID offset for normal bell to 0x7 |
8615 | */ | |
8616 | val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); | |
8617 | if (val == 0x7) { | |
8618 | u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
f2e0899f DK |
8619 | /* save our pf_num */ |
8620 | int orig_pf_num = bp->pf_num; | |
619c5cb6 VZ |
8621 | int port; |
8622 | u32 swap_en, swap_val, value; | |
34f80b04 | 8623 | |
b4661739 EG |
8624 | /* clear the UNDI indication */ |
8625 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
8626 | ||
34f80b04 EG |
8627 | BNX2X_DEV_INFO("UNDI is active! reset device\n"); |
8628 | ||
8629 | /* try unload UNDI on port 0 */ | |
f2e0899f | 8630 | bp->pf_num = 0; |
da5a662a | 8631 | bp->fw_seq = |
f2e0899f | 8632 | (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & |
da5a662a | 8633 | DRV_MSG_SEQ_NUMBER_MASK); |
a22f0788 | 8634 | reset_code = bnx2x_fw_command(bp, reset_code, 0); |
34f80b04 EG |
8635 | |
8636 | /* if UNDI is loaded on the other port */ | |
8637 | if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { | |
8638 | ||
da5a662a | 8639 | /* send "DONE" for previous unload */ |
a22f0788 YR |
8640 | bnx2x_fw_command(bp, |
8641 | DRV_MSG_CODE_UNLOAD_DONE, 0); | |
da5a662a VZ |
8642 | |
8643 | /* unload UNDI on port 1 */ | |
f2e0899f | 8644 | bp->pf_num = 1; |
da5a662a | 8645 | bp->fw_seq = |
f2e0899f | 8646 | (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & |
da5a662a VZ |
8647 | DRV_MSG_SEQ_NUMBER_MASK); |
8648 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
8649 | ||
a22f0788 | 8650 | bnx2x_fw_command(bp, reset_code, 0); |
34f80b04 EG |
8651 | } |
8652 | ||
f2e0899f | 8653 | bnx2x_undi_int_disable(bp); |
619c5cb6 | 8654 | port = BP_PORT(bp); |
da5a662a VZ |
8655 | |
8656 | /* close input traffic and wait for it */ | |
8657 | /* Do not rcv packets to BRB */ | |
619c5cb6 VZ |
8658 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : |
8659 | NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); | |
da5a662a VZ |
8660 | /* Do not direct rcv packets that are not for MCP to |
8661 | * the BRB */ | |
619c5cb6 VZ |
8662 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : |
8663 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
da5a662a | 8664 | /* clear AEU */ |
619c5cb6 VZ |
8665 | REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
8666 | MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); | |
da5a662a VZ |
8667 | msleep(10); |
8668 | ||
8669 | /* save NIG port swap info */ | |
8670 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
8671 | swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
34f80b04 EG |
8672 | /* reset device */ |
8673 | REG_WR(bp, | |
8674 | GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
da5a662a | 8675 | 0xd3ffffff); |
619c5cb6 VZ |
8676 | |
8677 | value = 0x1400; | |
8678 | if (CHIP_IS_E3(bp)) { | |
8679 | value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
8680 | value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
8681 | } | |
8682 | ||
34f80b04 EG |
8683 | REG_WR(bp, |
8684 | GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
619c5cb6 VZ |
8685 | value); |
8686 | ||
da5a662a VZ |
8687 | /* take the NIG out of reset and restore swap values */ |
8688 | REG_WR(bp, | |
8689 | GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
8690 | MISC_REGISTERS_RESET_REG_1_RST_NIG); | |
8691 | REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); | |
8692 | REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); | |
8693 | ||
8694 | /* send unload done to the MCP */ | |
a22f0788 | 8695 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); |
da5a662a VZ |
8696 | |
8697 | /* restore our func and fw_seq */ | |
f2e0899f | 8698 | bp->pf_num = orig_pf_num; |
da5a662a | 8699 | bp->fw_seq = |
f2e0899f | 8700 | (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & |
da5a662a | 8701 | DRV_MSG_SEQ_NUMBER_MASK); |
7a06a122 DK |
8702 | } |
8703 | ||
8704 | /* now it's safe to release the lock */ | |
8705 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | |
34f80b04 EG |
8706 | } |
8707 | } | |
8708 | ||
8709 | static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) | |
8710 | { | |
8711 | u32 val, val2, val3, val4, id; | |
72ce58c3 | 8712 | u16 pmc; |
34f80b04 EG |
8713 | |
8714 | /* Get the chip revision id and number. */ | |
8715 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
8716 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
8717 | id = ((val & 0xffff) << 16); | |
8718 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
8719 | id |= ((val & 0xf) << 12); | |
8720 | val = REG_RD(bp, MISC_REG_CHIP_METAL); | |
8721 | id |= ((val & 0xff) << 4); | |
5a40e08e | 8722 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
8723 | id |= (val & 0xf); |
8724 | bp->common.chip_id = id; | |
523224a3 DK |
8725 | |
8726 | /* Set doorbell size */ | |
8727 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
8728 | ||
619c5cb6 | 8729 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8730 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
8731 | if ((val & 1) == 0) | |
8732 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
8733 | else | |
8734 | val = (val >> 1) & 1; | |
8735 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
8736 | "2_PORT_MODE"); | |
8737 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
8738 | CHIP_2_PORT_MODE; | |
8739 | ||
8740 | if (CHIP_MODE_IS_4_PORT(bp)) | |
8741 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
8742 | else | |
8743 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
8744 | } else { | |
8745 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
8746 | bp->pfid = bp->pf_num; /* 0..7 */ | |
8747 | } | |
8748 | ||
f2e0899f DK |
8749 | bp->link_params.chip_id = bp->common.chip_id; |
8750 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 8751 | |
1c06328c EG |
8752 | val = (REG_RD(bp, 0x2874) & 0x55); |
8753 | if ((bp->common.chip_id & 0x1) || | |
8754 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
8755 | bp->flags |= ONE_PORT_FLAG; | |
8756 | BNX2X_DEV_INFO("single port device\n"); | |
8757 | } | |
8758 | ||
34f80b04 | 8759 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 8760 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
8761 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
8762 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
8763 | bp->common.flash_size, bp->common.flash_size); | |
8764 | ||
1b6e2ceb DK |
8765 | bnx2x_init_shmem(bp); |
8766 | ||
619c5cb6 VZ |
8767 | |
8768 | ||
f2e0899f DK |
8769 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
8770 | MISC_REG_GENERIC_CR_1 : | |
8771 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 8772 | |
34f80b04 | 8773 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 8774 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
2691d51d EG |
8775 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
8776 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 8777 | |
f2e0899f | 8778 | if (!bp->common.shmem_base) { |
34f80b04 EG |
8779 | BNX2X_DEV_INFO("MCP not active\n"); |
8780 | bp->flags |= NO_MCP_FLAG; | |
8781 | return; | |
8782 | } | |
8783 | ||
34f80b04 | 8784 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 8785 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
8786 | |
8787 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
8788 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
8789 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
8790 | ||
c2c8b03e EG |
8791 | bp->link_params.feature_config_flags = 0; |
8792 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
8793 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
8794 | bp->link_params.feature_config_flags |= | |
8795 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
8796 | else | |
8797 | bp->link_params.feature_config_flags &= | |
8798 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
8799 | ||
34f80b04 EG |
8800 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
8801 | bp->common.bc_ver = val; | |
8802 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
8803 | if (val < BNX2X_BC_VER) { | |
8804 | /* for now only warn | |
8805 | * later we might need to enforce this */ | |
f2e0899f DK |
8806 | BNX2X_ERR("This driver needs bc_ver %X but found %X, " |
8807 | "please upgrade BC\n", BNX2X_BC_VER, val); | |
34f80b04 | 8808 | } |
4d295db0 | 8809 | bp->link_params.feature_config_flags |= |
a22f0788 | 8810 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
8811 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
8812 | ||
a22f0788 YR |
8813 | bp->link_params.feature_config_flags |= |
8814 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
8815 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
72ce58c3 | 8816 | |
85242eea YR |
8817 | bp->link_params.feature_config_flags |= |
8818 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
8819 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
8820 | ||
f9a3ebbe DK |
8821 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); |
8822 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; | |
8823 | ||
72ce58c3 | 8824 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 8825 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
8826 | |
8827 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
8828 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
8829 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
8830 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
8831 | ||
cdaa7cb8 VZ |
8832 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
8833 | val, val2, val3, val4); | |
34f80b04 EG |
8834 | } |
8835 | ||
f2e0899f DK |
8836 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
8837 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
8838 | ||
8839 | static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) | |
8840 | { | |
8841 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
8842 | int igu_sb_id; |
8843 | u32 val; | |
6383c0b3 | 8844 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
8845 | |
8846 | bp->igu_base_sb = 0xff; | |
f2e0899f | 8847 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 8848 | int vn = BP_VN(bp); |
6383c0b3 | 8849 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
8850 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
8851 | FP_SB_MAX_E1x; | |
8852 | ||
8853 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
8854 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
8855 | ||
8856 | return; | |
8857 | } | |
8858 | ||
8859 | /* IGU in normal mode - read CAM */ | |
8860 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
8861 | igu_sb_id++) { | |
8862 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
8863 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
8864 | continue; | |
8865 | fid = IGU_FID(val); | |
8866 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
8867 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
8868 | continue; | |
8869 | if (IGU_VEC(val) == 0) | |
8870 | /* default status block */ | |
8871 | bp->igu_dsb_id = igu_sb_id; | |
8872 | else { | |
8873 | if (bp->igu_base_sb == 0xff) | |
8874 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 8875 | igu_sb_cnt++; |
f2e0899f DK |
8876 | } |
8877 | } | |
8878 | } | |
619c5cb6 | 8879 | |
6383c0b3 AE |
8880 | #ifdef CONFIG_PCI_MSI |
8881 | /* | |
8882 | * It's expected that number of CAM entries for this functions is equal | |
8883 | * to the number evaluated based on the MSI-X table size. We want a | |
8884 | * harsh warning if these values are different! | |
619c5cb6 | 8885 | */ |
6383c0b3 AE |
8886 | WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); |
8887 | #endif | |
619c5cb6 | 8888 | |
6383c0b3 | 8889 | if (igu_sb_cnt == 0) |
f2e0899f DK |
8890 | BNX2X_ERR("CAM configuration error\n"); |
8891 | } | |
8892 | ||
34f80b04 EG |
8893 | static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, |
8894 | u32 switch_cfg) | |
a2fbb9ea | 8895 | { |
a22f0788 YR |
8896 | int cfg_size = 0, idx, port = BP_PORT(bp); |
8897 | ||
8898 | /* Aggregation of supported attributes of all external phys */ | |
8899 | bp->port.supported[0] = 0; | |
8900 | bp->port.supported[1] = 0; | |
b7737c9b YR |
8901 | switch (bp->link_params.num_phys) { |
8902 | case 1: | |
a22f0788 YR |
8903 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
8904 | cfg_size = 1; | |
8905 | break; | |
b7737c9b | 8906 | case 2: |
a22f0788 YR |
8907 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
8908 | cfg_size = 1; | |
8909 | break; | |
8910 | case 3: | |
8911 | if (bp->link_params.multi_phy_config & | |
8912 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
8913 | bp->port.supported[1] = | |
8914 | bp->link_params.phy[EXT_PHY1].supported; | |
8915 | bp->port.supported[0] = | |
8916 | bp->link_params.phy[EXT_PHY2].supported; | |
8917 | } else { | |
8918 | bp->port.supported[0] = | |
8919 | bp->link_params.phy[EXT_PHY1].supported; | |
8920 | bp->port.supported[1] = | |
8921 | bp->link_params.phy[EXT_PHY2].supported; | |
8922 | } | |
8923 | cfg_size = 2; | |
8924 | break; | |
b7737c9b | 8925 | } |
a2fbb9ea | 8926 | |
a22f0788 | 8927 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
b7737c9b | 8928 | BNX2X_ERR("NVRAM config error. BAD phy config." |
a22f0788 | 8929 | "PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 8930 | SHMEM_RD(bp, |
a22f0788 YR |
8931 | dev_info.port_hw_config[port].external_phy_config), |
8932 | SHMEM_RD(bp, | |
8933 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 8934 | return; |
f85582f8 | 8935 | } |
a2fbb9ea | 8936 | |
619c5cb6 VZ |
8937 | if (CHIP_IS_E3(bp)) |
8938 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
8939 | else { | |
8940 | switch (switch_cfg) { | |
8941 | case SWITCH_CFG_1G: | |
8942 | bp->port.phy_addr = REG_RD( | |
8943 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
8944 | break; | |
8945 | case SWITCH_CFG_10G: | |
8946 | bp->port.phy_addr = REG_RD( | |
8947 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
8948 | break; | |
8949 | default: | |
8950 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
8951 | bp->port.link_config[0]); | |
8952 | return; | |
8953 | } | |
a2fbb9ea | 8954 | } |
619c5cb6 | 8955 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
8956 | /* mask what we support according to speed_cap_mask per configuration */ |
8957 | for (idx = 0; idx < cfg_size; idx++) { | |
8958 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 8959 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 8960 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 8961 | |
a22f0788 | 8962 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8963 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 8964 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 8965 | |
a22f0788 | 8966 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8967 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 8968 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 8969 | |
a22f0788 | 8970 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8971 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 8972 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 8973 | |
a22f0788 | 8974 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8975 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 8976 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 8977 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 8978 | |
a22f0788 | 8979 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8980 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 8981 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 8982 | |
a22f0788 | 8983 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 8984 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 YR |
8985 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
8986 | ||
8987 | } | |
a2fbb9ea | 8988 | |
a22f0788 YR |
8989 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
8990 | bp->port.supported[1]); | |
a2fbb9ea ET |
8991 | } |
8992 | ||
34f80b04 | 8993 | static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 8994 | { |
a22f0788 YR |
8995 | u32 link_config, idx, cfg_size = 0; |
8996 | bp->port.advertising[0] = 0; | |
8997 | bp->port.advertising[1] = 0; | |
8998 | switch (bp->link_params.num_phys) { | |
8999 | case 1: | |
9000 | case 2: | |
9001 | cfg_size = 1; | |
9002 | break; | |
9003 | case 3: | |
9004 | cfg_size = 2; | |
9005 | break; | |
9006 | } | |
9007 | for (idx = 0; idx < cfg_size; idx++) { | |
9008 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
9009 | link_config = bp->port.link_config[idx]; | |
9010 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 9011 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
9012 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
9013 | bp->link_params.req_line_speed[idx] = | |
9014 | SPEED_AUTO_NEG; | |
9015 | bp->port.advertising[idx] |= | |
9016 | bp->port.supported[idx]; | |
f85582f8 DK |
9017 | } else { |
9018 | /* force 10G, no AN */ | |
a22f0788 YR |
9019 | bp->link_params.req_line_speed[idx] = |
9020 | SPEED_10000; | |
9021 | bp->port.advertising[idx] |= | |
9022 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 9023 | ADVERTISED_FIBRE); |
a22f0788 | 9024 | continue; |
f85582f8 DK |
9025 | } |
9026 | break; | |
a2fbb9ea | 9027 | |
f85582f8 | 9028 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
9029 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
9030 | bp->link_params.req_line_speed[idx] = | |
9031 | SPEED_10; | |
9032 | bp->port.advertising[idx] |= | |
9033 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
9034 | ADVERTISED_TP); |
9035 | } else { | |
754a2f52 | 9036 | BNX2X_ERR("NVRAM config error. " |
f85582f8 DK |
9037 | "Invalid link_config 0x%x" |
9038 | " speed_cap_mask 0x%x\n", | |
9039 | link_config, | |
a22f0788 | 9040 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
9041 | return; |
9042 | } | |
9043 | break; | |
a2fbb9ea | 9044 | |
f85582f8 | 9045 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
9046 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
9047 | bp->link_params.req_line_speed[idx] = | |
9048 | SPEED_10; | |
9049 | bp->link_params.req_duplex[idx] = | |
9050 | DUPLEX_HALF; | |
9051 | bp->port.advertising[idx] |= | |
9052 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
9053 | ADVERTISED_TP); |
9054 | } else { | |
754a2f52 | 9055 | BNX2X_ERR("NVRAM config error. " |
f85582f8 DK |
9056 | "Invalid link_config 0x%x" |
9057 | " speed_cap_mask 0x%x\n", | |
9058 | link_config, | |
9059 | bp->link_params.speed_cap_mask[idx]); | |
9060 | return; | |
9061 | } | |
9062 | break; | |
a2fbb9ea | 9063 | |
f85582f8 DK |
9064 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
9065 | if (bp->port.supported[idx] & | |
9066 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
9067 | bp->link_params.req_line_speed[idx] = |
9068 | SPEED_100; | |
9069 | bp->port.advertising[idx] |= | |
9070 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
9071 | ADVERTISED_TP); |
9072 | } else { | |
754a2f52 | 9073 | BNX2X_ERR("NVRAM config error. " |
f85582f8 DK |
9074 | "Invalid link_config 0x%x" |
9075 | " speed_cap_mask 0x%x\n", | |
9076 | link_config, | |
9077 | bp->link_params.speed_cap_mask[idx]); | |
9078 | return; | |
9079 | } | |
9080 | break; | |
a2fbb9ea | 9081 | |
f85582f8 DK |
9082 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
9083 | if (bp->port.supported[idx] & | |
9084 | SUPPORTED_100baseT_Half) { | |
9085 | bp->link_params.req_line_speed[idx] = | |
9086 | SPEED_100; | |
9087 | bp->link_params.req_duplex[idx] = | |
9088 | DUPLEX_HALF; | |
a22f0788 YR |
9089 | bp->port.advertising[idx] |= |
9090 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
9091 | ADVERTISED_TP); |
9092 | } else { | |
754a2f52 | 9093 | BNX2X_ERR("NVRAM config error. " |
cdaa7cb8 VZ |
9094 | "Invalid link_config 0x%x" |
9095 | " speed_cap_mask 0x%x\n", | |
a22f0788 YR |
9096 | link_config, |
9097 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
9098 | return; |
9099 | } | |
9100 | break; | |
a2fbb9ea | 9101 | |
f85582f8 | 9102 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
9103 | if (bp->port.supported[idx] & |
9104 | SUPPORTED_1000baseT_Full) { | |
9105 | bp->link_params.req_line_speed[idx] = | |
9106 | SPEED_1000; | |
9107 | bp->port.advertising[idx] |= | |
9108 | (ADVERTISED_1000baseT_Full | | |
f85582f8 DK |
9109 | ADVERTISED_TP); |
9110 | } else { | |
754a2f52 | 9111 | BNX2X_ERR("NVRAM config error. " |
cdaa7cb8 VZ |
9112 | "Invalid link_config 0x%x" |
9113 | " speed_cap_mask 0x%x\n", | |
a22f0788 YR |
9114 | link_config, |
9115 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
9116 | return; |
9117 | } | |
9118 | break; | |
a2fbb9ea | 9119 | |
f85582f8 | 9120 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
9121 | if (bp->port.supported[idx] & |
9122 | SUPPORTED_2500baseX_Full) { | |
9123 | bp->link_params.req_line_speed[idx] = | |
9124 | SPEED_2500; | |
9125 | bp->port.advertising[idx] |= | |
9126 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 9127 | ADVERTISED_TP); |
f85582f8 | 9128 | } else { |
754a2f52 | 9129 | BNX2X_ERR("NVRAM config error. " |
cdaa7cb8 VZ |
9130 | "Invalid link_config 0x%x" |
9131 | " speed_cap_mask 0x%x\n", | |
a22f0788 | 9132 | link_config, |
f85582f8 DK |
9133 | bp->link_params.speed_cap_mask[idx]); |
9134 | return; | |
9135 | } | |
9136 | break; | |
a2fbb9ea | 9137 | |
f85582f8 | 9138 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
9139 | if (bp->port.supported[idx] & |
9140 | SUPPORTED_10000baseT_Full) { | |
9141 | bp->link_params.req_line_speed[idx] = | |
9142 | SPEED_10000; | |
9143 | bp->port.advertising[idx] |= | |
9144 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 9145 | ADVERTISED_FIBRE); |
f85582f8 | 9146 | } else { |
754a2f52 | 9147 | BNX2X_ERR("NVRAM config error. " |
cdaa7cb8 VZ |
9148 | "Invalid link_config 0x%x" |
9149 | " speed_cap_mask 0x%x\n", | |
a22f0788 | 9150 | link_config, |
f85582f8 DK |
9151 | bp->link_params.speed_cap_mask[idx]); |
9152 | return; | |
9153 | } | |
9154 | break; | |
3c9ada22 YR |
9155 | case PORT_FEATURE_LINK_SPEED_20G: |
9156 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 9157 | |
3c9ada22 | 9158 | break; |
f85582f8 | 9159 | default: |
754a2f52 DK |
9160 | BNX2X_ERR("NVRAM config error. " |
9161 | "BAD link speed link_config 0x%x\n", | |
9162 | link_config); | |
f85582f8 DK |
9163 | bp->link_params.req_line_speed[idx] = |
9164 | SPEED_AUTO_NEG; | |
9165 | bp->port.advertising[idx] = | |
9166 | bp->port.supported[idx]; | |
9167 | break; | |
9168 | } | |
a2fbb9ea | 9169 | |
a22f0788 | 9170 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 9171 | PORT_FEATURE_FLOW_CONTROL_MASK); |
a22f0788 YR |
9172 | if ((bp->link_params.req_flow_ctrl[idx] == |
9173 | BNX2X_FLOW_CTRL_AUTO) && | |
9174 | !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { | |
9175 | bp->link_params.req_flow_ctrl[idx] = | |
9176 | BNX2X_FLOW_CTRL_NONE; | |
9177 | } | |
a2fbb9ea | 9178 | |
a22f0788 YR |
9179 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" |
9180 | " 0x%x advertising 0x%x\n", | |
9181 | bp->link_params.req_line_speed[idx], | |
9182 | bp->link_params.req_duplex[idx], | |
9183 | bp->link_params.req_flow_ctrl[idx], | |
9184 | bp->port.advertising[idx]); | |
9185 | } | |
a2fbb9ea ET |
9186 | } |
9187 | ||
e665bfda MC |
9188 | static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
9189 | { | |
9190 | mac_hi = cpu_to_be16(mac_hi); | |
9191 | mac_lo = cpu_to_be32(mac_lo); | |
9192 | memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); | |
9193 | memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); | |
9194 | } | |
9195 | ||
34f80b04 | 9196 | static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 9197 | { |
34f80b04 | 9198 | int port = BP_PORT(bp); |
589abe3a | 9199 | u32 config; |
6f38ad93 | 9200 | u32 ext_phy_type, ext_phy_config; |
a2fbb9ea | 9201 | |
c18487ee | 9202 | bp->link_params.bp = bp; |
34f80b04 | 9203 | bp->link_params.port = port; |
c18487ee | 9204 | |
c18487ee | 9205 | bp->link_params.lane_config = |
a2fbb9ea | 9206 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 9207 | |
a22f0788 | 9208 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea ET |
9209 | SHMEM_RD(bp, |
9210 | dev_info.port_hw_config[port].speed_capability_mask); | |
a22f0788 YR |
9211 | bp->link_params.speed_cap_mask[1] = |
9212 | SHMEM_RD(bp, | |
9213 | dev_info.port_hw_config[port].speed_capability_mask2); | |
9214 | bp->port.link_config[0] = | |
a2fbb9ea ET |
9215 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
9216 | ||
a22f0788 YR |
9217 | bp->port.link_config[1] = |
9218 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 9219 | |
a22f0788 YR |
9220 | bp->link_params.multi_phy_config = |
9221 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
9222 | /* If the device is capable of WoL, set the default state according |
9223 | * to the HW | |
9224 | */ | |
4d295db0 | 9225 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
9226 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
9227 | (config & PORT_FEATURE_WOL_ENABLED)); | |
9228 | ||
f85582f8 | 9229 | BNX2X_DEV_INFO("lane_config 0x%08x " |
a22f0788 | 9230 | "speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 9231 | bp->link_params.lane_config, |
a22f0788 YR |
9232 | bp->link_params.speed_cap_mask[0], |
9233 | bp->port.link_config[0]); | |
a2fbb9ea | 9234 | |
a22f0788 | 9235 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 9236 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 9237 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 9238 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
9239 | |
9240 | bnx2x_link_settings_requested(bp); | |
9241 | ||
01cd4528 EG |
9242 | /* |
9243 | * If connected directly, work with the internal PHY, otherwise, work | |
9244 | * with the external PHY | |
9245 | */ | |
b7737c9b YR |
9246 | ext_phy_config = |
9247 | SHMEM_RD(bp, | |
9248 | dev_info.port_hw_config[port].external_phy_config); | |
9249 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 9250 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 9251 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
9252 | |
9253 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
9254 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
9255 | bp->mdio.prtad = | |
b7737c9b | 9256 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d YR |
9257 | |
9258 | /* | |
9259 | * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) | |
9260 | * In MF mode, it is set to cover self test cases | |
9261 | */ | |
9262 | if (IS_MF(bp)) | |
9263 | bp->port.need_hw_lock = 1; | |
9264 | else | |
9265 | bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, | |
9266 | bp->common.shmem_base, | |
9267 | bp->common.shmem2_base); | |
0793f83f | 9268 | } |
01cd4528 | 9269 | |
2ba45142 | 9270 | #ifdef BCM_CNIC |
b306f5ed | 9271 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 9272 | { |
bf61ee14 | 9273 | int port = BP_PORT(bp); |
bf61ee14 | 9274 | |
2ba45142 | 9275 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 9276 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 9277 | |
b306f5ed | 9278 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
9279 | bp->cnic_eth_dev.max_iscsi_conn = |
9280 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
9281 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
9282 | ||
b306f5ed DK |
9283 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
9284 | bp->cnic_eth_dev.max_iscsi_conn); | |
9285 | ||
9286 | /* | |
9287 | * If maximum allowed number of connections is zero - | |
9288 | * disable the feature. | |
9289 | */ | |
9290 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9291 | bp->flags |= NO_ISCSI_FLAG; | |
9292 | } | |
9293 | ||
9294 | static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) | |
9295 | { | |
9296 | int port = BP_PORT(bp); | |
9297 | int func = BP_ABS_FUNC(bp); | |
9298 | ||
9299 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, | |
9300 | drv_lic_key[port].max_fcoe_conn); | |
9301 | ||
9302 | /* Get the number of maximum allowed FCoE connections */ | |
2ba45142 VZ |
9303 | bp->cnic_eth_dev.max_fcoe_conn = |
9304 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
9305 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
9306 | ||
bf61ee14 VZ |
9307 | /* Read the WWN: */ |
9308 | if (!IS_MF(bp)) { | |
9309 | /* Port info */ | |
9310 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
9311 | SHMEM_RD(bp, | |
9312 | dev_info.port_hw_config[port]. | |
9313 | fcoe_wwn_port_name_upper); | |
9314 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
9315 | SHMEM_RD(bp, | |
9316 | dev_info.port_hw_config[port]. | |
9317 | fcoe_wwn_port_name_lower); | |
9318 | ||
9319 | /* Node info */ | |
9320 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
9321 | SHMEM_RD(bp, | |
9322 | dev_info.port_hw_config[port]. | |
9323 | fcoe_wwn_node_name_upper); | |
9324 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
9325 | SHMEM_RD(bp, | |
9326 | dev_info.port_hw_config[port]. | |
9327 | fcoe_wwn_node_name_lower); | |
9328 | } else if (!IS_MF_SD(bp)) { | |
9329 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); | |
9330 | ||
9331 | /* | |
9332 | * Read the WWN info only if the FCoE feature is enabled for | |
9333 | * this function. | |
9334 | */ | |
9335 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
9336 | /* Port info */ | |
9337 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
9338 | MF_CFG_RD(bp, func_ext_config[func]. | |
9339 | fcoe_wwn_port_name_upper); | |
9340 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
9341 | MF_CFG_RD(bp, func_ext_config[func]. | |
9342 | fcoe_wwn_port_name_lower); | |
9343 | ||
9344 | /* Node info */ | |
9345 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
9346 | MF_CFG_RD(bp, func_ext_config[func]. | |
9347 | fcoe_wwn_node_name_upper); | |
9348 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
9349 | MF_CFG_RD(bp, func_ext_config[func]. | |
9350 | fcoe_wwn_node_name_lower); | |
9351 | } | |
9352 | } | |
9353 | ||
b306f5ed | 9354 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 9355 | |
bf61ee14 VZ |
9356 | /* |
9357 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
9358 | * disable the feature. |
9359 | */ | |
2ba45142 VZ |
9360 | if (!bp->cnic_eth_dev.max_fcoe_conn) |
9361 | bp->flags |= NO_FCOE_FLAG; | |
9362 | } | |
b306f5ed DK |
9363 | |
9364 | static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) | |
9365 | { | |
9366 | /* | |
9367 | * iSCSI may be dynamically disabled but reading | |
9368 | * info here we will decrease memory usage by driver | |
9369 | * if the feature is disabled for good | |
9370 | */ | |
9371 | bnx2x_get_iscsi_info(bp); | |
9372 | bnx2x_get_fcoe_info(bp); | |
9373 | } | |
2ba45142 VZ |
9374 | #endif |
9375 | ||
0793f83f DK |
9376 | static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
9377 | { | |
9378 | u32 val, val2; | |
9379 | int func = BP_ABS_FUNC(bp); | |
9380 | int port = BP_PORT(bp); | |
2ba45142 VZ |
9381 | #ifdef BCM_CNIC |
9382 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; | |
9383 | u8 *fip_mac = bp->fip_mac; | |
9384 | #endif | |
0793f83f | 9385 | |
619c5cb6 VZ |
9386 | /* Zero primary MAC configuration */ |
9387 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
9388 | ||
0793f83f DK |
9389 | if (BP_NOMCP(bp)) { |
9390 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
9391 | random_ether_addr(bp->dev->dev_addr); | |
9392 | } else if (IS_MF(bp)) { | |
9393 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
9394 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
9395 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
9396 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
9397 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
37b091ba MC |
9398 | |
9399 | #ifdef BCM_CNIC | |
2ba45142 VZ |
9400 | /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or |
9401 | * FCoE MAC then the appropriate feature should be disabled. | |
9402 | */ | |
0793f83f DK |
9403 | if (IS_MF_SI(bp)) { |
9404 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); | |
9405 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
9406 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
9407 | iscsi_mac_addr_upper); | |
9408 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
9409 | iscsi_mac_addr_lower); | |
2ba45142 | 9410 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
0f9dad10 JP |
9411 | BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", |
9412 | iscsi_mac); | |
2ba45142 VZ |
9413 | } else |
9414 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; | |
9415 | ||
9416 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
9417 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
9418 | fcoe_mac_addr_upper); | |
9419 | val = MF_CFG_RD(bp, func_ext_config[func]. | |
9420 | fcoe_mac_addr_lower); | |
2ba45142 | 9421 | bnx2x_set_mac_buf(fip_mac, val, val2); |
0f9dad10 JP |
9422 | BNX2X_DEV_INFO("Read FCoE L2 MAC to %pM\n", |
9423 | fip_mac); | |
2ba45142 | 9424 | |
2ba45142 VZ |
9425 | } else |
9426 | bp->flags |= NO_FCOE_FLAG; | |
0793f83f | 9427 | } |
37b091ba | 9428 | #endif |
0793f83f DK |
9429 | } else { |
9430 | /* in SF read MACs from port configuration */ | |
9431 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
9432 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
9433 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
9434 | ||
9435 | #ifdef BCM_CNIC | |
9436 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9437 | iscsi_mac_upper); | |
9438 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9439 | iscsi_mac_lower); | |
2ba45142 | 9440 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
9441 | |
9442 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9443 | fcoe_fip_mac_upper); | |
9444 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
9445 | fcoe_fip_mac_lower); | |
9446 | bnx2x_set_mac_buf(fip_mac, val, val2); | |
0793f83f DK |
9447 | #endif |
9448 | } | |
9449 | ||
9450 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); | |
9451 | memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); | |
9452 | ||
ec6ba945 | 9453 | #ifdef BCM_CNIC |
c03bd39c VZ |
9454 | /* Set the FCoE MAC in MF_SD mode */ |
9455 | if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp)) | |
9456 | memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); | |
426b9241 DK |
9457 | |
9458 | /* Disable iSCSI if MAC configuration is | |
9459 | * invalid. | |
9460 | */ | |
9461 | if (!is_valid_ether_addr(iscsi_mac)) { | |
9462 | bp->flags |= NO_ISCSI_FLAG; | |
9463 | memset(iscsi_mac, 0, ETH_ALEN); | |
9464 | } | |
9465 | ||
9466 | /* Disable FCoE if MAC configuration is | |
9467 | * invalid. | |
9468 | */ | |
9469 | if (!is_valid_ether_addr(fip_mac)) { | |
9470 | bp->flags |= NO_FCOE_FLAG; | |
9471 | memset(bp->fip_mac, 0, ETH_ALEN); | |
9472 | } | |
ec6ba945 | 9473 | #endif |
619c5cb6 VZ |
9474 | |
9475 | if (!is_valid_ether_addr(bp->dev->dev_addr)) | |
9476 | dev_err(&bp->pdev->dev, | |
9477 | "bad Ethernet MAC address configuration: " | |
0f9dad10 | 9478 | "%pM, change it manually before bringing up " |
619c5cb6 | 9479 | "the appropriate network interface\n", |
0f9dad10 | 9480 | bp->dev->dev_addr); |
34f80b04 EG |
9481 | } |
9482 | ||
9483 | static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |
9484 | { | |
0793f83f | 9485 | int /*abs*/func = BP_ABS_FUNC(bp); |
b8ee8328 | 9486 | int vn; |
0793f83f | 9487 | u32 val = 0; |
34f80b04 | 9488 | int rc = 0; |
a2fbb9ea | 9489 | |
34f80b04 | 9490 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 9491 | |
6383c0b3 AE |
9492 | /* |
9493 | * initialize IGU parameters | |
9494 | */ | |
f2e0899f DK |
9495 | if (CHIP_IS_E1x(bp)) { |
9496 | bp->common.int_block = INT_BLOCK_HC; | |
9497 | ||
9498 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
9499 | bp->igu_base_sb = 0; | |
f2e0899f DK |
9500 | } else { |
9501 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 DK |
9502 | |
9503 | /* do not allow device reset during IGU info preocessing */ | |
9504 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | |
9505 | ||
f2e0899f | 9506 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
9507 | |
9508 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
9509 | int tout = 5000; | |
9510 | ||
9511 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
9512 | ||
9513 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
9514 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
9515 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
9516 | ||
9517 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
9518 | tout--; | |
9519 | usleep_range(1000, 1000); | |
9520 | } | |
9521 | ||
9522 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
9523 | dev_err(&bp->pdev->dev, | |
9524 | "FORCING Normal Mode failed!!!\n"); | |
9525 | return -EPERM; | |
9526 | } | |
9527 | } | |
9528 | ||
f2e0899f | 9529 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 9530 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
9531 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
9532 | } else | |
619c5cb6 | 9533 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 9534 | |
f2e0899f DK |
9535 | bnx2x_get_igu_cam_info(bp); |
9536 | ||
7a06a122 | 9537 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
f2e0899f | 9538 | } |
619c5cb6 VZ |
9539 | |
9540 | /* | |
9541 | * set base FW non-default (fast path) status block id, this value is | |
9542 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
9543 | * determine the id used by the FW. | |
9544 | */ | |
9545 | if (CHIP_IS_E1x(bp)) | |
9546 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
9547 | else /* | |
9548 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
9549 | * the same queue are indicated on the same IGU SB). So we prefer | |
9550 | * FW and IGU SBs to be the same value. | |
9551 | */ | |
9552 | bp->base_fw_ndsb = bp->igu_base_sb; | |
9553 | ||
9554 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
9555 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
9556 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
9557 | |
9558 | /* | |
9559 | * Initialize MF configuration | |
9560 | */ | |
523224a3 | 9561 | |
fb3bff17 DK |
9562 | bp->mf_ov = 0; |
9563 | bp->mf_mode = 0; | |
3395a033 | 9564 | vn = BP_VN(bp); |
0793f83f | 9565 | |
f2e0899f | 9566 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
9567 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
9568 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
9569 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
9570 | ||
f2e0899f DK |
9571 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
9572 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
9573 | else | |
9574 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
9575 | offsetof(struct shmem_region, func_mb) + |
9576 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
9577 | /* |
9578 | * get mf configuration: | |
25985edc | 9579 | * 1. existence of MF configuration |
0793f83f DK |
9580 | * 2. MAC address must be legal (check only upper bytes) |
9581 | * for Switch-Independent mode; | |
9582 | * OVLAN must be legal for Switch-Dependent mode | |
9583 | * 3. SF_MODE configures specific MF mode | |
9584 | */ | |
9585 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
9586 | /* get mf configuration */ | |
9587 | val = SHMEM_RD(bp, | |
9588 | dev_info.shared_feature_config.config); | |
9589 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
9590 | ||
9591 | switch (val) { | |
9592 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
9593 | val = MF_CFG_RD(bp, func_mf_config[func]. | |
9594 | mac_upper); | |
9595 | /* check for legal mac (upper bytes)*/ | |
9596 | if (val != 0xffff) { | |
9597 | bp->mf_mode = MULTI_FUNCTION_SI; | |
9598 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
9599 | func_mf_config[func].config); | |
9600 | } else | |
619c5cb6 VZ |
9601 | BNX2X_DEV_INFO("illegal MAC address " |
9602 | "for SI\n"); | |
0793f83f DK |
9603 | break; |
9604 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: | |
9605 | /* get OV configuration */ | |
9606 | val = MF_CFG_RD(bp, | |
9607 | func_mf_config[FUNC_0].e1hov_tag); | |
9608 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
9609 | ||
9610 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
9611 | bp->mf_mode = MULTI_FUNCTION_SD; | |
9612 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
9613 | func_mf_config[func].config); | |
9614 | } else | |
754a2f52 | 9615 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f DK |
9616 | break; |
9617 | default: | |
9618 | /* Unknown configuration: reset mf_config */ | |
9619 | bp->mf_config[vn] = 0; | |
754a2f52 | 9620 | BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); |
0793f83f DK |
9621 | } |
9622 | } | |
a2fbb9ea | 9623 | |
2691d51d | 9624 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 9625 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 9626 | |
0793f83f DK |
9627 | switch (bp->mf_mode) { |
9628 | case MULTI_FUNCTION_SD: | |
9629 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
9630 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 9631 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 9632 | bp->mf_ov = val; |
619c5cb6 VZ |
9633 | bp->path_has_ovlan = true; |
9634 | ||
9635 | BNX2X_DEV_INFO("MF OV for func %d is %d " | |
9636 | "(0x%04x)\n", func, bp->mf_ov, | |
9637 | bp->mf_ov); | |
2691d51d | 9638 | } else { |
619c5cb6 VZ |
9639 | dev_err(&bp->pdev->dev, |
9640 | "No valid MF OV for func %d, " | |
9641 | "aborting\n", func); | |
9642 | return -EPERM; | |
34f80b04 | 9643 | } |
0793f83f DK |
9644 | break; |
9645 | case MULTI_FUNCTION_SI: | |
9646 | BNX2X_DEV_INFO("func %d is in MF " | |
9647 | "switch-independent mode\n", func); | |
9648 | break; | |
9649 | default: | |
9650 | if (vn) { | |
619c5cb6 VZ |
9651 | dev_err(&bp->pdev->dev, |
9652 | "VN %d is in a single function mode, " | |
9653 | "aborting\n", vn); | |
9654 | return -EPERM; | |
2691d51d | 9655 | } |
0793f83f | 9656 | break; |
34f80b04 | 9657 | } |
0793f83f | 9658 | |
619c5cb6 VZ |
9659 | /* check if other port on the path needs ovlan: |
9660 | * Since MF configuration is shared between ports | |
9661 | * Possible mixed modes are only | |
9662 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
9663 | */ | |
9664 | if (CHIP_MODE_IS_4_PORT(bp) && | |
9665 | !bp->path_has_ovlan && | |
9666 | !IS_MF(bp) && | |
9667 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
9668 | u8 other_port = !BP_PORT(bp); | |
9669 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
9670 | val = MF_CFG_RD(bp, | |
9671 | func_mf_config[other_func].e1hov_tag); | |
9672 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
9673 | bp->path_has_ovlan = true; | |
9674 | } | |
34f80b04 | 9675 | } |
a2fbb9ea | 9676 | |
f2e0899f DK |
9677 | /* adjust igu_sb_cnt to MF for E1x */ |
9678 | if (CHIP_IS_E1x(bp) && IS_MF(bp)) | |
523224a3 DK |
9679 | bp->igu_sb_cnt /= E1HVN_MAX; |
9680 | ||
619c5cb6 VZ |
9681 | /* port info */ |
9682 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 9683 | |
0793f83f DK |
9684 | /* Get MAC addresses */ |
9685 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 9686 | |
2ba45142 VZ |
9687 | #ifdef BCM_CNIC |
9688 | bnx2x_get_cnic_info(bp); | |
9689 | #endif | |
9690 | ||
619c5cb6 VZ |
9691 | /* Get current FW pulse sequence */ |
9692 | if (!BP_NOMCP(bp)) { | |
9693 | int mb_idx = BP_FW_MB_IDX(bp); | |
9694 | ||
9695 | bp->fw_drv_pulse_wr_seq = | |
9696 | (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) & | |
9697 | DRV_PULSE_SEQ_MASK); | |
9698 | BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); | |
9699 | } | |
9700 | ||
34f80b04 EG |
9701 | return rc; |
9702 | } | |
9703 | ||
34f24c7f VZ |
9704 | static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) |
9705 | { | |
9706 | int cnt, i, block_end, rodi; | |
9707 | char vpd_data[BNX2X_VPD_LEN+1]; | |
9708 | char str_id_reg[VENDOR_ID_LEN+1]; | |
9709 | char str_id_cap[VENDOR_ID_LEN+1]; | |
9710 | u8 len; | |
9711 | ||
9712 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data); | |
9713 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); | |
9714 | ||
9715 | if (cnt < BNX2X_VPD_LEN) | |
9716 | goto out_not_found; | |
9717 | ||
9718 | i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN, | |
9719 | PCI_VPD_LRDT_RO_DATA); | |
9720 | if (i < 0) | |
9721 | goto out_not_found; | |
9722 | ||
9723 | ||
9724 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + | |
9725 | pci_vpd_lrdt_size(&vpd_data[i]); | |
9726 | ||
9727 | i += PCI_VPD_LRDT_TAG_SIZE; | |
9728 | ||
9729 | if (block_end > BNX2X_VPD_LEN) | |
9730 | goto out_not_found; | |
9731 | ||
9732 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
9733 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
9734 | if (rodi < 0) | |
9735 | goto out_not_found; | |
9736 | ||
9737 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
9738 | ||
9739 | if (len != VENDOR_ID_LEN) | |
9740 | goto out_not_found; | |
9741 | ||
9742 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
9743 | ||
9744 | /* vendor specific info */ | |
9745 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
9746 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
9747 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
9748 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
9749 | ||
9750 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
9751 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
9752 | if (rodi >= 0) { | |
9753 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
9754 | ||
9755 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
9756 | ||
9757 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
9758 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
9759 | bp->fw_ver[len] = ' '; | |
9760 | } | |
9761 | } | |
9762 | return; | |
9763 | } | |
9764 | out_not_found: | |
9765 | return; | |
9766 | } | |
9767 | ||
619c5cb6 VZ |
9768 | static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) |
9769 | { | |
9770 | u32 flags = 0; | |
9771 | ||
9772 | if (CHIP_REV_IS_FPGA(bp)) | |
9773 | SET_FLAGS(flags, MODE_FPGA); | |
9774 | else if (CHIP_REV_IS_EMUL(bp)) | |
9775 | SET_FLAGS(flags, MODE_EMUL); | |
9776 | else | |
9777 | SET_FLAGS(flags, MODE_ASIC); | |
9778 | ||
9779 | if (CHIP_MODE_IS_4_PORT(bp)) | |
9780 | SET_FLAGS(flags, MODE_PORT4); | |
9781 | else | |
9782 | SET_FLAGS(flags, MODE_PORT2); | |
9783 | ||
9784 | if (CHIP_IS_E2(bp)) | |
9785 | SET_FLAGS(flags, MODE_E2); | |
9786 | else if (CHIP_IS_E3(bp)) { | |
9787 | SET_FLAGS(flags, MODE_E3); | |
9788 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
9789 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
9790 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
9791 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
9792 | } |
9793 | ||
9794 | if (IS_MF(bp)) { | |
9795 | SET_FLAGS(flags, MODE_MF); | |
9796 | switch (bp->mf_mode) { | |
9797 | case MULTI_FUNCTION_SD: | |
9798 | SET_FLAGS(flags, MODE_MF_SD); | |
9799 | break; | |
9800 | case MULTI_FUNCTION_SI: | |
9801 | SET_FLAGS(flags, MODE_MF_SI); | |
9802 | break; | |
9803 | } | |
9804 | } else | |
9805 | SET_FLAGS(flags, MODE_SF); | |
9806 | ||
9807 | #if defined(__LITTLE_ENDIAN) | |
9808 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
9809 | #else /*(__BIG_ENDIAN)*/ | |
9810 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
9811 | #endif | |
9812 | INIT_MODE_FLAGS(bp) = flags; | |
9813 | } | |
9814 | ||
34f80b04 EG |
9815 | static int __devinit bnx2x_init_bp(struct bnx2x *bp) |
9816 | { | |
f2e0899f | 9817 | int func; |
87942b46 | 9818 | int timer_interval; |
34f80b04 EG |
9819 | int rc; |
9820 | ||
34f80b04 | 9821 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 9822 | mutex_init(&bp->fw_mb_mutex); |
bb7e95c8 | 9823 | spin_lock_init(&bp->stats_lock); |
993ac7b5 MC |
9824 | #ifdef BCM_CNIC |
9825 | mutex_init(&bp->cnic_mutex); | |
9826 | #endif | |
a2fbb9ea | 9827 | |
1cf167f2 | 9828 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 9829 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 9830 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
34f80b04 | 9831 | rc = bnx2x_get_hwinfo(bp); |
619c5cb6 VZ |
9832 | if (rc) |
9833 | return rc; | |
34f80b04 | 9834 | |
619c5cb6 VZ |
9835 | bnx2x_set_modes_bitmap(bp); |
9836 | ||
9837 | rc = bnx2x_alloc_mem_bp(bp); | |
9838 | if (rc) | |
9839 | return rc; | |
523224a3 | 9840 | |
34f24c7f | 9841 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
9842 | |
9843 | func = BP_FUNC(bp); | |
9844 | ||
34f80b04 EG |
9845 | /* need to reset chip if undi was active */ |
9846 | if (!BP_NOMCP(bp)) | |
9847 | bnx2x_undi_unload(bp); | |
9848 | ||
0735f2fc DK |
9849 | /* init fw_seq after undi_unload! */ |
9850 | if (!BP_NOMCP(bp)) { | |
9851 | bp->fw_seq = | |
9852 | (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
9853 | DRV_MSG_SEQ_NUMBER_MASK); | |
9854 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
9855 | } | |
9856 | ||
34f80b04 | 9857 | if (CHIP_REV_IS_FPGA(bp)) |
cdaa7cb8 | 9858 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
9859 | |
9860 | if (BP_NOMCP(bp) && (func == 0)) | |
cdaa7cb8 VZ |
9861 | dev_err(&bp->pdev->dev, "MCP disabled, " |
9862 | "must load devices in order!\n"); | |
34f80b04 | 9863 | |
555f6c78 | 9864 | bp->multi_mode = multi_mode; |
555f6c78 | 9865 | |
7a9b2557 VZ |
9866 | /* Set TPA flags */ |
9867 | if (disable_tpa) { | |
9868 | bp->flags &= ~TPA_ENABLE_FLAG; | |
9869 | bp->dev->features &= ~NETIF_F_LRO; | |
9870 | } else { | |
9871 | bp->flags |= TPA_ENABLE_FLAG; | |
9872 | bp->dev->features |= NETIF_F_LRO; | |
9873 | } | |
5d7cd496 | 9874 | bp->disable_tpa = disable_tpa; |
7a9b2557 | 9875 | |
a18f5128 EG |
9876 | if (CHIP_IS_E1(bp)) |
9877 | bp->dropless_fc = 0; | |
9878 | else | |
9879 | bp->dropless_fc = dropless_fc; | |
9880 | ||
8d5726c4 | 9881 | bp->mrrs = mrrs; |
7a9b2557 | 9882 | |
34f80b04 | 9883 | bp->tx_ring_size = MAX_TX_AVAIL; |
34f80b04 | 9884 | |
7d323bfd | 9885 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
9886 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
9887 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 9888 | |
87942b46 EG |
9889 | timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); |
9890 | bp->current_interval = (poll ? poll : timer_interval); | |
34f80b04 EG |
9891 | |
9892 | init_timer(&bp->timer); | |
9893 | bp->timer.expires = jiffies + bp->current_interval; | |
9894 | bp->timer.data = (unsigned long) bp; | |
9895 | bp->timer.function = bnx2x_timer; | |
9896 | ||
785b9b1a | 9897 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); |
e4901dde VZ |
9898 | bnx2x_dcbx_init_params(bp); |
9899 | ||
619c5cb6 VZ |
9900 | #ifdef BCM_CNIC |
9901 | if (CHIP_IS_E1x(bp)) | |
9902 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
9903 | else | |
9904 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
9905 | #endif | |
9906 | ||
6383c0b3 AE |
9907 | /* multiple tx priority */ |
9908 | if (CHIP_IS_E1x(bp)) | |
9909 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; | |
9910 | if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) | |
9911 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; | |
9912 | if (CHIP_IS_E3B0(bp)) | |
9913 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; | |
9914 | ||
34f80b04 | 9915 | return rc; |
a2fbb9ea ET |
9916 | } |
9917 | ||
a2fbb9ea | 9918 | |
de0c62db DK |
9919 | /**************************************************************************** |
9920 | * General service functions | |
9921 | ****************************************************************************/ | |
a2fbb9ea | 9922 | |
619c5cb6 VZ |
9923 | /* |
9924 | * net_device service functions | |
9925 | */ | |
9926 | ||
bb2a0f7a | 9927 | /* called with rtnl_lock */ |
a2fbb9ea ET |
9928 | static int bnx2x_open(struct net_device *dev) |
9929 | { | |
9930 | struct bnx2x *bp = netdev_priv(dev); | |
c9ee9206 VZ |
9931 | bool global = false; |
9932 | int other_engine = BP_PATH(bp) ? 0 : 1; | |
9933 | u32 other_load_counter, load_counter; | |
a2fbb9ea | 9934 | |
6eccabb3 EG |
9935 | netif_carrier_off(dev); |
9936 | ||
a2fbb9ea ET |
9937 | bnx2x_set_power_state(bp, PCI_D0); |
9938 | ||
c9ee9206 VZ |
9939 | other_load_counter = bnx2x_get_load_cnt(bp, other_engine); |
9940 | load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp)); | |
9941 | ||
9942 | /* | |
9943 | * If parity had happen during the unload, then attentions | |
9944 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we | |
9945 | * want the first function loaded on the current engine to | |
9946 | * complete the recovery. | |
9947 | */ | |
9948 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
9949 | bnx2x_chk_parity_attn(bp, &global, true)) | |
72fd0718 | 9950 | do { |
c9ee9206 VZ |
9951 | /* |
9952 | * If there are attentions and they are in a global | |
9953 | * blocks, set the GLOBAL_RESET bit regardless whether | |
9954 | * it will be this function that will complete the | |
9955 | * recovery or not. | |
72fd0718 | 9956 | */ |
c9ee9206 VZ |
9957 | if (global) |
9958 | bnx2x_set_reset_global(bp); | |
72fd0718 | 9959 | |
c9ee9206 VZ |
9960 | /* |
9961 | * Only the first function on the current engine should | |
9962 | * try to recover in open. In case of attentions in | |
9963 | * global blocks only the first in the chip should try | |
9964 | * to recover. | |
72fd0718 | 9965 | */ |
c9ee9206 VZ |
9966 | if ((!load_counter && |
9967 | (!global || !other_load_counter)) && | |
9968 | bnx2x_trylock_leader_lock(bp) && | |
9969 | !bnx2x_leader_reset(bp)) { | |
9970 | netdev_info(bp->dev, "Recovered in open\n"); | |
72fd0718 VZ |
9971 | break; |
9972 | } | |
9973 | ||
c9ee9206 | 9974 | /* recovery has failed... */ |
72fd0718 | 9975 | bnx2x_set_power_state(bp, PCI_D3hot); |
c9ee9206 | 9976 | bp->recovery_state = BNX2X_RECOVERY_FAILED; |
72fd0718 | 9977 | |
c9ee9206 | 9978 | netdev_err(bp->dev, "Recovery flow hasn't been properly" |
72fd0718 VZ |
9979 | " completed yet. Try again later. If u still see this" |
9980 | " message after a few retries then power cycle is" | |
c9ee9206 | 9981 | " required.\n"); |
72fd0718 VZ |
9982 | |
9983 | return -EAGAIN; | |
9984 | } while (0); | |
72fd0718 VZ |
9985 | |
9986 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
bb2a0f7a | 9987 | return bnx2x_nic_load(bp, LOAD_OPEN); |
a2fbb9ea ET |
9988 | } |
9989 | ||
bb2a0f7a | 9990 | /* called with rtnl_lock */ |
a2fbb9ea ET |
9991 | static int bnx2x_close(struct net_device *dev) |
9992 | { | |
a2fbb9ea ET |
9993 | struct bnx2x *bp = netdev_priv(dev); |
9994 | ||
9995 | /* Unload the driver, release IRQs */ | |
bb2a0f7a | 9996 | bnx2x_nic_unload(bp, UNLOAD_CLOSE); |
c9ee9206 VZ |
9997 | |
9998 | /* Power off */ | |
d3dbfee0 | 9999 | bnx2x_set_power_state(bp, PCI_D3hot); |
a2fbb9ea ET |
10000 | |
10001 | return 0; | |
10002 | } | |
10003 | ||
619c5cb6 VZ |
10004 | static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
10005 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 10006 | { |
619c5cb6 VZ |
10007 | int mc_count = netdev_mc_count(bp->dev); |
10008 | struct bnx2x_mcast_list_elem *mc_mac = | |
10009 | kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); | |
10010 | struct netdev_hw_addr *ha; | |
6e30dd4e | 10011 | |
619c5cb6 VZ |
10012 | if (!mc_mac) |
10013 | return -ENOMEM; | |
6e30dd4e | 10014 | |
619c5cb6 | 10015 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 10016 | |
619c5cb6 VZ |
10017 | netdev_for_each_mc_addr(ha, bp->dev) { |
10018 | mc_mac->mac = bnx2x_mc_addr(ha); | |
10019 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
10020 | mc_mac++; | |
6e30dd4e | 10021 | } |
619c5cb6 VZ |
10022 | |
10023 | p->mcast_list_len = mc_count; | |
10024 | ||
10025 | return 0; | |
6e30dd4e VZ |
10026 | } |
10027 | ||
619c5cb6 VZ |
10028 | static inline void bnx2x_free_mcast_macs_list( |
10029 | struct bnx2x_mcast_ramrod_params *p) | |
10030 | { | |
10031 | struct bnx2x_mcast_list_elem *mc_mac = | |
10032 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
10033 | link); | |
10034 | ||
10035 | WARN_ON(!mc_mac); | |
10036 | kfree(mc_mac); | |
10037 | } | |
10038 | ||
10039 | /** | |
10040 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
10041 | * | |
10042 | * @bp: driver handle | |
6e30dd4e | 10043 | * |
619c5cb6 | 10044 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 10045 | */ |
619c5cb6 | 10046 | static inline int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 10047 | { |
619c5cb6 | 10048 | int rc; |
6e30dd4e | 10049 | struct net_device *dev = bp->dev; |
6e30dd4e | 10050 | struct netdev_hw_addr *ha; |
619c5cb6 VZ |
10051 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; |
10052 | unsigned long ramrod_flags = 0; | |
6e30dd4e | 10053 | |
619c5cb6 VZ |
10054 | /* First schedule a cleanup up of old configuration */ |
10055 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
10056 | if (rc < 0) { | |
10057 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
10058 | return rc; | |
10059 | } | |
6e30dd4e VZ |
10060 | |
10061 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
10062 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
10063 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
10064 | if (rc < 0) { | |
10065 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", | |
10066 | rc); | |
10067 | return rc; | |
6e30dd4e VZ |
10068 | } |
10069 | } | |
10070 | ||
619c5cb6 VZ |
10071 | /* Execute the pending commands */ |
10072 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
10073 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
10074 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
10075 | } |
10076 | ||
619c5cb6 | 10077 | static inline int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 10078 | { |
619c5cb6 VZ |
10079 | struct net_device *dev = bp->dev; |
10080 | struct bnx2x_mcast_ramrod_params rparam = {0}; | |
10081 | int rc = 0; | |
6e30dd4e | 10082 | |
619c5cb6 | 10083 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 10084 | |
619c5cb6 VZ |
10085 | /* first, clear all configured multicast MACs */ |
10086 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
10087 | if (rc < 0) { | |
10088 | BNX2X_ERR("Failed to clear multicast " | |
10089 | "configuration: %d\n", rc); | |
10090 | return rc; | |
10091 | } | |
6e30dd4e | 10092 | |
619c5cb6 VZ |
10093 | /* then, configure a new MACs list */ |
10094 | if (netdev_mc_count(dev)) { | |
10095 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
10096 | if (rc) { | |
10097 | BNX2X_ERR("Failed to create multicast MACs " | |
10098 | "list: %d\n", rc); | |
10099 | return rc; | |
10100 | } | |
6e30dd4e | 10101 | |
619c5cb6 VZ |
10102 | /* Now add the new MACs */ |
10103 | rc = bnx2x_config_mcast(bp, &rparam, | |
10104 | BNX2X_MCAST_CMD_ADD); | |
10105 | if (rc < 0) | |
10106 | BNX2X_ERR("Failed to set a new multicast " | |
10107 | "configuration: %d\n", rc); | |
6e30dd4e | 10108 | |
619c5cb6 VZ |
10109 | bnx2x_free_mcast_macs_list(&rparam); |
10110 | } | |
6e30dd4e | 10111 | |
619c5cb6 | 10112 | return rc; |
6e30dd4e VZ |
10113 | } |
10114 | ||
6e30dd4e | 10115 | |
619c5cb6 | 10116 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
9f6c9258 | 10117 | void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
10118 | { |
10119 | struct bnx2x *bp = netdev_priv(dev); | |
10120 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 EG |
10121 | |
10122 | if (bp->state != BNX2X_STATE_OPEN) { | |
10123 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
10124 | return; | |
10125 | } | |
10126 | ||
619c5cb6 | 10127 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 EG |
10128 | |
10129 | if (dev->flags & IFF_PROMISC) | |
10130 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
619c5cb6 VZ |
10131 | else if ((dev->flags & IFF_ALLMULTI) || |
10132 | ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && | |
10133 | CHIP_IS_E1(bp))) | |
34f80b04 | 10134 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
6e30dd4e VZ |
10135 | else { |
10136 | /* some multicasts */ | |
619c5cb6 | 10137 | if (bnx2x_set_mc_list(bp) < 0) |
6e30dd4e | 10138 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
34f80b04 | 10139 | |
619c5cb6 | 10140 | if (bnx2x_set_uc_list(bp) < 0) |
6e30dd4e | 10141 | rx_mode = BNX2X_RX_MODE_PROMISC; |
34f80b04 EG |
10142 | } |
10143 | ||
10144 | bp->rx_mode = rx_mode; | |
619c5cb6 VZ |
10145 | |
10146 | /* Schedule the rx_mode command */ | |
10147 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
10148 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
10149 | return; | |
10150 | } | |
10151 | ||
34f80b04 EG |
10152 | bnx2x_set_storm_rx_mode(bp); |
10153 | } | |
10154 | ||
c18487ee | 10155 | /* called with rtnl_lock */ |
01cd4528 EG |
10156 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
10157 | int devad, u16 addr) | |
a2fbb9ea | 10158 | { |
01cd4528 EG |
10159 | struct bnx2x *bp = netdev_priv(netdev); |
10160 | u16 value; | |
10161 | int rc; | |
a2fbb9ea | 10162 | |
01cd4528 EG |
10163 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
10164 | prtad, devad, addr); | |
a2fbb9ea | 10165 | |
01cd4528 EG |
10166 | /* The HW expects different devad if CL22 is used */ |
10167 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 10168 | |
01cd4528 | 10169 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 10170 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
10171 | bnx2x_release_phy_lock(bp); |
10172 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 10173 | |
01cd4528 EG |
10174 | if (!rc) |
10175 | rc = value; | |
10176 | return rc; | |
10177 | } | |
a2fbb9ea | 10178 | |
01cd4528 EG |
10179 | /* called with rtnl_lock */ |
10180 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
10181 | u16 addr, u16 value) | |
10182 | { | |
10183 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
10184 | int rc; |
10185 | ||
10186 | DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," | |
10187 | " value 0x%x\n", prtad, devad, addr, value); | |
10188 | ||
01cd4528 EG |
10189 | /* The HW expects different devad if CL22 is used */ |
10190 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 10191 | |
01cd4528 | 10192 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 10193 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
10194 | bnx2x_release_phy_lock(bp); |
10195 | return rc; | |
10196 | } | |
c18487ee | 10197 | |
01cd4528 EG |
10198 | /* called with rtnl_lock */ |
10199 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
10200 | { | |
10201 | struct bnx2x *bp = netdev_priv(dev); | |
10202 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 10203 | |
01cd4528 EG |
10204 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", |
10205 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
a2fbb9ea | 10206 | |
01cd4528 EG |
10207 | if (!netif_running(dev)) |
10208 | return -EAGAIN; | |
10209 | ||
10210 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
a2fbb9ea ET |
10211 | } |
10212 | ||
257ddbda | 10213 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
10214 | static void poll_bnx2x(struct net_device *dev) |
10215 | { | |
10216 | struct bnx2x *bp = netdev_priv(dev); | |
10217 | ||
10218 | disable_irq(bp->pdev->irq); | |
10219 | bnx2x_interrupt(bp->pdev->irq, dev); | |
10220 | enable_irq(bp->pdev->irq); | |
10221 | } | |
10222 | #endif | |
10223 | ||
c64213cd SH |
10224 | static const struct net_device_ops bnx2x_netdev_ops = { |
10225 | .ndo_open = bnx2x_open, | |
10226 | .ndo_stop = bnx2x_close, | |
10227 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 10228 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 10229 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd SH |
10230 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
10231 | .ndo_validate_addr = eth_validate_addr, | |
10232 | .ndo_do_ioctl = bnx2x_ioctl, | |
10233 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
10234 | .ndo_fix_features = bnx2x_fix_features, |
10235 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 10236 | .ndo_tx_timeout = bnx2x_tx_timeout, |
257ddbda | 10237 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
10238 | .ndo_poll_controller = poll_bnx2x, |
10239 | #endif | |
6383c0b3 AE |
10240 | .ndo_setup_tc = bnx2x_setup_tc, |
10241 | ||
bf61ee14 VZ |
10242 | #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) |
10243 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, | |
10244 | #endif | |
c64213cd SH |
10245 | }; |
10246 | ||
619c5cb6 VZ |
10247 | static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) |
10248 | { | |
10249 | struct device *dev = &bp->pdev->dev; | |
10250 | ||
10251 | if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { | |
10252 | bp->flags |= USING_DAC_FLAG; | |
10253 | if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { | |
10254 | dev_err(dev, "dma_set_coherent_mask failed, " | |
10255 | "aborting\n"); | |
10256 | return -EIO; | |
10257 | } | |
10258 | } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { | |
10259 | dev_err(dev, "System does not support DMA, aborting\n"); | |
10260 | return -EIO; | |
10261 | } | |
10262 | ||
10263 | return 0; | |
10264 | } | |
10265 | ||
34f80b04 | 10266 | static int __devinit bnx2x_init_dev(struct pci_dev *pdev, |
619c5cb6 VZ |
10267 | struct net_device *dev, |
10268 | unsigned long board_type) | |
a2fbb9ea ET |
10269 | { |
10270 | struct bnx2x *bp; | |
10271 | int rc; | |
10272 | ||
10273 | SET_NETDEV_DEV(dev, &pdev->dev); | |
10274 | bp = netdev_priv(dev); | |
10275 | ||
34f80b04 EG |
10276 | bp->dev = dev; |
10277 | bp->pdev = pdev; | |
a2fbb9ea | 10278 | bp->flags = 0; |
f2e0899f | 10279 | bp->pf_num = PCI_FUNC(pdev->devfn); |
a2fbb9ea ET |
10280 | |
10281 | rc = pci_enable_device(pdev); | |
10282 | if (rc) { | |
cdaa7cb8 VZ |
10283 | dev_err(&bp->pdev->dev, |
10284 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
10285 | goto err_out; |
10286 | } | |
10287 | ||
10288 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
10289 | dev_err(&bp->pdev->dev, |
10290 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
10291 | rc = -ENODEV; |
10292 | goto err_out_disable; | |
10293 | } | |
10294 | ||
10295 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
10296 | dev_err(&bp->pdev->dev, "Cannot find second PCI device" |
10297 | " base address, aborting\n"); | |
a2fbb9ea ET |
10298 | rc = -ENODEV; |
10299 | goto err_out_disable; | |
10300 | } | |
10301 | ||
34f80b04 EG |
10302 | if (atomic_read(&pdev->enable_cnt) == 1) { |
10303 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
10304 | if (rc) { | |
cdaa7cb8 VZ |
10305 | dev_err(&bp->pdev->dev, |
10306 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
10307 | goto err_out_disable; |
10308 | } | |
a2fbb9ea | 10309 | |
34f80b04 EG |
10310 | pci_set_master(pdev); |
10311 | pci_save_state(pdev); | |
10312 | } | |
a2fbb9ea ET |
10313 | |
10314 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
10315 | if (bp->pm_cap == 0) { | |
cdaa7cb8 VZ |
10316 | dev_err(&bp->pdev->dev, |
10317 | "Cannot find power management capability, aborting\n"); | |
a2fbb9ea ET |
10318 | rc = -EIO; |
10319 | goto err_out_release; | |
10320 | } | |
10321 | ||
77c98e6a JM |
10322 | if (!pci_is_pcie(pdev)) { |
10323 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); | |
a2fbb9ea ET |
10324 | rc = -EIO; |
10325 | goto err_out_release; | |
10326 | } | |
10327 | ||
619c5cb6 VZ |
10328 | rc = bnx2x_set_coherency_mask(bp); |
10329 | if (rc) | |
a2fbb9ea | 10330 | goto err_out_release; |
a2fbb9ea | 10331 | |
34f80b04 EG |
10332 | dev->mem_start = pci_resource_start(pdev, 0); |
10333 | dev->base_addr = dev->mem_start; | |
10334 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
10335 | |
10336 | dev->irq = pdev->irq; | |
10337 | ||
275f165f | 10338 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 10339 | if (!bp->regview) { |
cdaa7cb8 VZ |
10340 | dev_err(&bp->pdev->dev, |
10341 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
10342 | rc = -ENOMEM; |
10343 | goto err_out_release; | |
10344 | } | |
10345 | ||
a2fbb9ea ET |
10346 | bnx2x_set_power_state(bp, PCI_D0); |
10347 | ||
34f80b04 EG |
10348 | /* clean indirect addresses */ |
10349 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
10350 | PCICFG_VENDOR_ID_OFFSET); | |
a5c53dbc DK |
10351 | /* |
10352 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
10353 | * is not used by the driver. |
10354 | */ | |
10355 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
10356 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
10357 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
10358 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
a5c53dbc DK |
10359 | |
10360 | if (CHIP_IS_E1x(bp)) { | |
10361 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); | |
10362 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
10363 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
10364 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
10365 | } | |
a2fbb9ea | 10366 | |
2189400b | 10367 | /* |
619c5cb6 | 10368 | * Enable internal target-read (in case we are probed after PF FLR). |
2189400b | 10369 | * Must be done prior to any BAR read access. Only for 57712 and up |
619c5cb6 | 10370 | */ |
2189400b SR |
10371 | if (board_type != BCM57710 && |
10372 | board_type != BCM57711 && | |
10373 | board_type != BCM57711E) | |
10374 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
619c5cb6 | 10375 | |
72fd0718 VZ |
10376 | /* Reset the load counter */ |
10377 | bnx2x_clear_load_cnt(bp); | |
10378 | ||
34f80b04 | 10379 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 10380 | |
c64213cd | 10381 | dev->netdev_ops = &bnx2x_netdev_ops; |
de0c62db | 10382 | bnx2x_set_ethtool_ops(dev); |
5316bc0b | 10383 | |
01789349 JP |
10384 | dev->priv_flags |= IFF_UNICAST_FLT; |
10385 | ||
66371c44 | 10386 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
6e68c912 MS |
10387 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO | |
10388 | NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; | |
66371c44 MM |
10389 | |
10390 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
10391 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
10392 | ||
10393 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; | |
5316bc0b | 10394 | if (bp->flags & USING_DAC_FLAG) |
66371c44 | 10395 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 10396 | |
538dd2e3 MB |
10397 | /* Add Loopback capability to the device */ |
10398 | dev->hw_features |= NETIF_F_LOOPBACK; | |
10399 | ||
98507672 | 10400 | #ifdef BCM_DCBNL |
785b9b1a SR |
10401 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
10402 | #endif | |
10403 | ||
01cd4528 EG |
10404 | /* get_port_hwinfo() will set prtad and mmds properly */ |
10405 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
10406 | bp->mdio.mmds = 0; | |
10407 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
10408 | bp->mdio.dev = dev; | |
10409 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
10410 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
10411 | ||
a2fbb9ea ET |
10412 | return 0; |
10413 | ||
a2fbb9ea | 10414 | err_out_release: |
34f80b04 EG |
10415 | if (atomic_read(&pdev->enable_cnt) == 1) |
10416 | pci_release_regions(pdev); | |
a2fbb9ea ET |
10417 | |
10418 | err_out_disable: | |
10419 | pci_disable_device(pdev); | |
10420 | pci_set_drvdata(pdev, NULL); | |
10421 | ||
10422 | err_out: | |
10423 | return rc; | |
10424 | } | |
10425 | ||
37f9ce62 EG |
10426 | static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, |
10427 | int *width, int *speed) | |
25047950 ET |
10428 | { |
10429 | u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); | |
10430 | ||
37f9ce62 | 10431 | *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; |
25047950 | 10432 | |
37f9ce62 EG |
10433 | /* return value of 1=2.5GHz 2=5GHz */ |
10434 | *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; | |
25047950 | 10435 | } |
37f9ce62 | 10436 | |
6891dd25 | 10437 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 10438 | { |
37f9ce62 | 10439 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
10440 | struct bnx2x_fw_file_hdr *fw_hdr; |
10441 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 10442 | u32 offset, len, num_ops; |
37f9ce62 | 10443 | u16 *ops_offsets; |
94a78b79 | 10444 | int i; |
37f9ce62 | 10445 | const u8 *fw_ver; |
94a78b79 VZ |
10446 | |
10447 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) | |
10448 | return -EINVAL; | |
10449 | ||
10450 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
10451 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
10452 | ||
10453 | /* Make sure none of the offsets and sizes make us read beyond | |
10454 | * the end of the firmware data */ | |
10455 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
10456 | offset = be32_to_cpu(sections[i].offset); | |
10457 | len = be32_to_cpu(sections[i].len); | |
10458 | if (offset + len > firmware->size) { | |
cdaa7cb8 VZ |
10459 | dev_err(&bp->pdev->dev, |
10460 | "Section %d length is out of bounds\n", i); | |
94a78b79 VZ |
10461 | return -EINVAL; |
10462 | } | |
10463 | } | |
10464 | ||
10465 | /* Likewise for the init_ops offsets */ | |
10466 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
10467 | ops_offsets = (u16 *)(firmware->data + offset); | |
10468 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); | |
10469 | ||
10470 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
10471 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
cdaa7cb8 VZ |
10472 | dev_err(&bp->pdev->dev, |
10473 | "Section offset %d is out of bounds\n", i); | |
94a78b79 VZ |
10474 | return -EINVAL; |
10475 | } | |
10476 | } | |
10477 | ||
10478 | /* Check FW version */ | |
10479 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
10480 | fw_ver = firmware->data + offset; | |
10481 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
10482 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
10483 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
10484 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
cdaa7cb8 VZ |
10485 | dev_err(&bp->pdev->dev, |
10486 | "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", | |
94a78b79 VZ |
10487 | fw_ver[0], fw_ver[1], fw_ver[2], |
10488 | fw_ver[3], BCM_5710_FW_MAJOR_VERSION, | |
10489 | BCM_5710_FW_MINOR_VERSION, | |
10490 | BCM_5710_FW_REVISION_VERSION, | |
10491 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 10492 | return -EINVAL; |
94a78b79 VZ |
10493 | } |
10494 | ||
10495 | return 0; | |
10496 | } | |
10497 | ||
ab6ad5a4 | 10498 | static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 10499 | { |
ab6ad5a4 EG |
10500 | const __be32 *source = (const __be32 *)_source; |
10501 | u32 *target = (u32 *)_target; | |
94a78b79 | 10502 | u32 i; |
94a78b79 VZ |
10503 | |
10504 | for (i = 0; i < n/4; i++) | |
10505 | target[i] = be32_to_cpu(source[i]); | |
10506 | } | |
10507 | ||
10508 | /* | |
10509 | Ops array is stored in the following format: | |
10510 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
10511 | */ | |
ab6ad5a4 | 10512 | static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 10513 | { |
ab6ad5a4 EG |
10514 | const __be32 *source = (const __be32 *)_source; |
10515 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 10516 | u32 i, j, tmp; |
94a78b79 | 10517 | |
ab6ad5a4 | 10518 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
10519 | tmp = be32_to_cpu(source[j]); |
10520 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
10521 | target[i].offset = tmp & 0xffffff; |
10522 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
10523 | } |
10524 | } | |
ab6ad5a4 | 10525 | |
523224a3 DK |
10526 | /** |
10527 | * IRO array is stored in the following format: | |
10528 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } | |
10529 | */ | |
10530 | static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) | |
10531 | { | |
10532 | const __be32 *source = (const __be32 *)_source; | |
10533 | struct iro *target = (struct iro *)_target; | |
10534 | u32 i, j, tmp; | |
10535 | ||
10536 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
10537 | target[i].base = be32_to_cpu(source[j]); | |
10538 | j++; | |
10539 | tmp = be32_to_cpu(source[j]); | |
10540 | target[i].m1 = (tmp >> 16) & 0xffff; | |
10541 | target[i].m2 = tmp & 0xffff; | |
10542 | j++; | |
10543 | tmp = be32_to_cpu(source[j]); | |
10544 | target[i].m3 = (tmp >> 16) & 0xffff; | |
10545 | target[i].size = tmp & 0xffff; | |
10546 | j++; | |
10547 | } | |
10548 | } | |
10549 | ||
ab6ad5a4 | 10550 | static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 10551 | { |
ab6ad5a4 EG |
10552 | const __be16 *source = (const __be16 *)_source; |
10553 | u16 *target = (u16 *)_target; | |
94a78b79 | 10554 | u32 i; |
94a78b79 VZ |
10555 | |
10556 | for (i = 0; i < n/2; i++) | |
10557 | target[i] = be16_to_cpu(source[i]); | |
10558 | } | |
10559 | ||
7995c64e JP |
10560 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
10561 | do { \ | |
10562 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
10563 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
10564 | if (!bp->arr) { \ | |
10565 | pr_err("Failed to allocate %d bytes for "#arr"\n", len); \ | |
10566 | goto lbl; \ | |
10567 | } \ | |
10568 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ | |
10569 | (u8 *)bp->arr, len); \ | |
10570 | } while (0) | |
94a78b79 | 10571 | |
6891dd25 | 10572 | int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 10573 | { |
45229b42 | 10574 | const char *fw_file_name; |
94a78b79 | 10575 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 10576 | int rc; |
94a78b79 | 10577 | |
94a78b79 | 10578 | if (CHIP_IS_E1(bp)) |
45229b42 | 10579 | fw_file_name = FW_FILE_NAME_E1; |
cdaa7cb8 | 10580 | else if (CHIP_IS_E1H(bp)) |
45229b42 | 10581 | fw_file_name = FW_FILE_NAME_E1H; |
619c5cb6 | 10582 | else if (!CHIP_IS_E1x(bp)) |
f2e0899f | 10583 | fw_file_name = FW_FILE_NAME_E2; |
cdaa7cb8 | 10584 | else { |
6891dd25 | 10585 | BNX2X_ERR("Unsupported chip revision\n"); |
cdaa7cb8 VZ |
10586 | return -EINVAL; |
10587 | } | |
94a78b79 | 10588 | |
6891dd25 | 10589 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); |
94a78b79 | 10590 | |
6891dd25 | 10591 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
94a78b79 | 10592 | if (rc) { |
6891dd25 | 10593 | BNX2X_ERR("Can't load firmware file %s\n", fw_file_name); |
94a78b79 VZ |
10594 | goto request_firmware_exit; |
10595 | } | |
10596 | ||
10597 | rc = bnx2x_check_firmware(bp); | |
10598 | if (rc) { | |
6891dd25 | 10599 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); |
94a78b79 VZ |
10600 | goto request_firmware_exit; |
10601 | } | |
10602 | ||
10603 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
10604 | ||
10605 | /* Initialize the pointers to the init arrays */ | |
10606 | /* Blob */ | |
10607 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
10608 | ||
10609 | /* Opcodes */ | |
10610 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
10611 | ||
10612 | /* Offsets */ | |
ab6ad5a4 EG |
10613 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
10614 | be16_to_cpu_n); | |
94a78b79 VZ |
10615 | |
10616 | /* STORMs firmware */ | |
573f2035 EG |
10617 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
10618 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
10619 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
10620 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
10621 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
10622 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
10623 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
10624 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
10625 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
10626 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
10627 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
10628 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
10629 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
10630 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
10631 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
10632 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
10633 | /* IRO */ |
10634 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
10635 | |
10636 | return 0; | |
ab6ad5a4 | 10637 | |
523224a3 DK |
10638 | iro_alloc_err: |
10639 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
10640 | init_offsets_alloc_err: |
10641 | kfree(bp->init_ops); | |
10642 | init_ops_alloc_err: | |
10643 | kfree(bp->init_data); | |
10644 | request_firmware_exit: | |
10645 | release_firmware(bp->firmware); | |
10646 | ||
10647 | return rc; | |
10648 | } | |
10649 | ||
619c5cb6 VZ |
10650 | static void bnx2x_release_firmware(struct bnx2x *bp) |
10651 | { | |
10652 | kfree(bp->init_ops_offsets); | |
10653 | kfree(bp->init_ops); | |
10654 | kfree(bp->init_data); | |
10655 | release_firmware(bp->firmware); | |
10656 | } | |
10657 | ||
10658 | ||
10659 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { | |
10660 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
10661 | .init_hw_cmn = bnx2x_init_hw_common, | |
10662 | .init_hw_port = bnx2x_init_hw_port, | |
10663 | .init_hw_func = bnx2x_init_hw_func, | |
10664 | ||
10665 | .reset_hw_cmn = bnx2x_reset_common, | |
10666 | .reset_hw_port = bnx2x_reset_port, | |
10667 | .reset_hw_func = bnx2x_reset_func, | |
10668 | ||
10669 | .gunzip_init = bnx2x_gunzip_init, | |
10670 | .gunzip_end = bnx2x_gunzip_end, | |
10671 | ||
10672 | .init_fw = bnx2x_init_firmware, | |
10673 | .release_fw = bnx2x_release_firmware, | |
10674 | }; | |
10675 | ||
10676 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
10677 | { | |
10678 | /* Prepare DMAE related driver resources */ | |
10679 | bnx2x_setup_dmae(bp); | |
10680 | ||
10681 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
10682 | bnx2x_sp(bp, func_rdata), | |
10683 | bnx2x_sp_mapping(bp, func_rdata), | |
10684 | &bnx2x_func_sp_drv); | |
10685 | } | |
10686 | ||
10687 | /* must be called after sriov-enable */ | |
6383c0b3 | 10688 | static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 10689 | { |
6383c0b3 | 10690 | int cid_count = BNX2X_L2_CID_COUNT(bp); |
94a78b79 | 10691 | |
523224a3 DK |
10692 | #ifdef BCM_CNIC |
10693 | cid_count += CNIC_CID_MAX; | |
10694 | #endif | |
10695 | return roundup(cid_count, QM_CID_ROUND); | |
10696 | } | |
f85582f8 | 10697 | |
619c5cb6 | 10698 | /** |
6383c0b3 | 10699 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
10700 | * |
10701 | * @dev: pci device | |
10702 | * | |
10703 | */ | |
6383c0b3 | 10704 | static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) |
619c5cb6 VZ |
10705 | { |
10706 | int pos; | |
10707 | u16 control; | |
10708 | ||
10709 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); | |
6383c0b3 AE |
10710 | |
10711 | /* | |
10712 | * If MSI-X is not supported - return number of SBs needed to support | |
10713 | * one fast path queue: one FP queue + SB for CNIC | |
10714 | */ | |
619c5cb6 | 10715 | if (!pos) |
6383c0b3 | 10716 | return 1 + CNIC_PRESENT; |
619c5cb6 | 10717 | |
6383c0b3 AE |
10718 | /* |
10719 | * The value in the PCI configuration space is the index of the last | |
10720 | * entry, namely one less than the actual size of the table, which is | |
10721 | * exactly what we want to return from this function: number of all SBs | |
10722 | * without the default SB. | |
10723 | */ | |
619c5cb6 | 10724 | pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); |
6383c0b3 | 10725 | return control & PCI_MSIX_FLAGS_QSIZE; |
619c5cb6 VZ |
10726 | } |
10727 | ||
a2fbb9ea ET |
10728 | static int __devinit bnx2x_init_one(struct pci_dev *pdev, |
10729 | const struct pci_device_id *ent) | |
10730 | { | |
a2fbb9ea ET |
10731 | struct net_device *dev = NULL; |
10732 | struct bnx2x *bp; | |
37f9ce62 | 10733 | int pcie_width, pcie_speed; |
6383c0b3 AE |
10734 | int rc, max_non_def_sbs; |
10735 | int rx_count, tx_count, rss_count; | |
10736 | /* | |
10737 | * An estimated maximum supported CoS number according to the chip | |
10738 | * version. | |
10739 | * We will try to roughly estimate the maximum number of CoSes this chip | |
10740 | * may support in order to minimize the memory allocated for Tx | |
10741 | * netdev_queue's. This number will be accurately calculated during the | |
10742 | * initialization of bp->max_cos based on the chip versions AND chip | |
10743 | * revision in the bnx2x_init_bp(). | |
10744 | */ | |
10745 | u8 max_cos_est = 0; | |
523224a3 | 10746 | |
f2e0899f DK |
10747 | switch (ent->driver_data) { |
10748 | case BCM57710: | |
10749 | case BCM57711: | |
10750 | case BCM57711E: | |
6383c0b3 AE |
10751 | max_cos_est = BNX2X_MULTI_TX_COS_E1X; |
10752 | break; | |
10753 | ||
f2e0899f | 10754 | case BCM57712: |
619c5cb6 | 10755 | case BCM57712_MF: |
6383c0b3 AE |
10756 | max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; |
10757 | break; | |
10758 | ||
619c5cb6 VZ |
10759 | case BCM57800: |
10760 | case BCM57800_MF: | |
10761 | case BCM57810: | |
10762 | case BCM57810_MF: | |
10763 | case BCM57840: | |
10764 | case BCM57840_MF: | |
6383c0b3 | 10765 | max_cos_est = BNX2X_MULTI_TX_COS_E3B0; |
f2e0899f | 10766 | break; |
a2fbb9ea | 10767 | |
f2e0899f DK |
10768 | default: |
10769 | pr_err("Unknown board_type (%ld), aborting\n", | |
10770 | ent->driver_data); | |
870634b0 | 10771 | return -ENODEV; |
f2e0899f DK |
10772 | } |
10773 | ||
6383c0b3 AE |
10774 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); |
10775 | ||
10776 | /* !!! FIXME !!! | |
10777 | * Do not allow the maximum SB count to grow above 16 | |
10778 | * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. | |
10779 | * We will use the FP_SB_MAX_E1x macro for this matter. | |
10780 | */ | |
10781 | max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); | |
10782 | ||
10783 | WARN_ON(!max_non_def_sbs); | |
10784 | ||
10785 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
10786 | rss_count = max_non_def_sbs - CNIC_PRESENT; | |
10787 | ||
10788 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
10789 | rx_count = rss_count + FCOE_PRESENT; | |
10790 | ||
10791 | /* | |
10792 | * Maximum number of netdev Tx queues: | |
10793 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 | |
10794 | */ | |
10795 | tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; | |
f85582f8 | 10796 | |
a2fbb9ea | 10797 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 10798 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
34f80b04 | 10799 | if (!dev) { |
cdaa7cb8 | 10800 | dev_err(&pdev->dev, "Cannot allocate net device\n"); |
a2fbb9ea | 10801 | return -ENOMEM; |
34f80b04 | 10802 | } |
a2fbb9ea | 10803 | |
a2fbb9ea | 10804 | bp = netdev_priv(dev); |
a2fbb9ea | 10805 | |
6383c0b3 AE |
10806 | DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", |
10807 | tx_count, rx_count); | |
df4770de | 10808 | |
6383c0b3 AE |
10809 | bp->igu_sb_cnt = max_non_def_sbs; |
10810 | bp->msg_enable = debug; | |
10811 | pci_set_drvdata(pdev, dev); | |
523224a3 | 10812 | |
619c5cb6 | 10813 | rc = bnx2x_init_dev(pdev, dev, ent->driver_data); |
a2fbb9ea ET |
10814 | if (rc < 0) { |
10815 | free_netdev(dev); | |
10816 | return rc; | |
10817 | } | |
10818 | ||
94f05b0f | 10819 | DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs); |
619c5cb6 | 10820 | |
34f80b04 | 10821 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
10822 | if (rc) |
10823 | goto init_one_exit; | |
10824 | ||
6383c0b3 AE |
10825 | /* |
10826 | * Map doorbels here as we need the real value of bp->max_cos which | |
10827 | * is initialized in bnx2x_init_bp(). | |
10828 | */ | |
10829 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), | |
10830 | min_t(u64, BNX2X_DB_SIZE(bp), | |
10831 | pci_resource_len(pdev, 2))); | |
10832 | if (!bp->doorbells) { | |
10833 | dev_err(&bp->pdev->dev, | |
10834 | "Cannot map doorbell space, aborting\n"); | |
10835 | rc = -ENOMEM; | |
10836 | goto init_one_exit; | |
10837 | } | |
10838 | ||
523224a3 | 10839 | /* calc qm_cid_count */ |
6383c0b3 | 10840 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
523224a3 | 10841 | |
ec6ba945 | 10842 | #ifdef BCM_CNIC |
62ac0dc9 DK |
10843 | /* disable FCOE L2 queue for E1x */ |
10844 | if (CHIP_IS_E1x(bp)) | |
ec6ba945 VZ |
10845 | bp->flags |= NO_FCOE_FLAG; |
10846 | ||
10847 | #endif | |
10848 | ||
25985edc | 10849 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
d6214d7a DK |
10850 | * needed, set bp->num_queues appropriately. |
10851 | */ | |
10852 | bnx2x_set_int_mode(bp); | |
10853 | ||
10854 | /* Add all NAPI objects */ | |
10855 | bnx2x_add_all_napi(bp); | |
10856 | ||
b340007f VZ |
10857 | rc = register_netdev(dev); |
10858 | if (rc) { | |
10859 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
10860 | goto init_one_exit; | |
10861 | } | |
10862 | ||
ec6ba945 VZ |
10863 | #ifdef BCM_CNIC |
10864 | if (!NO_FCOE(bp)) { | |
10865 | /* Add storage MAC address */ | |
10866 | rtnl_lock(); | |
10867 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
10868 | rtnl_unlock(); | |
10869 | } | |
10870 | #endif | |
10871 | ||
37f9ce62 | 10872 | bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); |
d6214d7a | 10873 | |
94f05b0f JP |
10874 | netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", |
10875 | board_info[ent->driver_data].name, | |
10876 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
10877 | pcie_width, | |
10878 | ((!CHIP_IS_E2(bp) && pcie_speed == 2) || | |
10879 | (CHIP_IS_E2(bp) && pcie_speed == 1)) ? | |
10880 | "5GHz (Gen2)" : "2.5GHz", | |
10881 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
c016201c | 10882 | |
a2fbb9ea | 10883 | return 0; |
34f80b04 EG |
10884 | |
10885 | init_one_exit: | |
10886 | if (bp->regview) | |
10887 | iounmap(bp->regview); | |
10888 | ||
10889 | if (bp->doorbells) | |
10890 | iounmap(bp->doorbells); | |
10891 | ||
10892 | free_netdev(dev); | |
10893 | ||
10894 | if (atomic_read(&pdev->enable_cnt) == 1) | |
10895 | pci_release_regions(pdev); | |
10896 | ||
10897 | pci_disable_device(pdev); | |
10898 | pci_set_drvdata(pdev, NULL); | |
10899 | ||
10900 | return rc; | |
a2fbb9ea ET |
10901 | } |
10902 | ||
10903 | static void __devexit bnx2x_remove_one(struct pci_dev *pdev) | |
10904 | { | |
10905 | struct net_device *dev = pci_get_drvdata(pdev); | |
228241eb ET |
10906 | struct bnx2x *bp; |
10907 | ||
10908 | if (!dev) { | |
cdaa7cb8 | 10909 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); |
228241eb ET |
10910 | return; |
10911 | } | |
228241eb | 10912 | bp = netdev_priv(dev); |
a2fbb9ea | 10913 | |
ec6ba945 VZ |
10914 | #ifdef BCM_CNIC |
10915 | /* Delete storage MAC address */ | |
10916 | if (!NO_FCOE(bp)) { | |
10917 | rtnl_lock(); | |
10918 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
10919 | rtnl_unlock(); | |
10920 | } | |
10921 | #endif | |
10922 | ||
98507672 SR |
10923 | #ifdef BCM_DCBNL |
10924 | /* Delete app tlvs from dcbnl */ | |
10925 | bnx2x_dcbnl_update_applist(bp, true); | |
10926 | #endif | |
10927 | ||
a2fbb9ea ET |
10928 | unregister_netdev(dev); |
10929 | ||
d6214d7a DK |
10930 | /* Delete all NAPI objects */ |
10931 | bnx2x_del_all_napi(bp); | |
10932 | ||
084d6cbb VZ |
10933 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
10934 | bnx2x_set_power_state(bp, PCI_D0); | |
10935 | ||
d6214d7a DK |
10936 | /* Disable MSI/MSI-X */ |
10937 | bnx2x_disable_msi(bp); | |
f85582f8 | 10938 | |
084d6cbb VZ |
10939 | /* Power off */ |
10940 | bnx2x_set_power_state(bp, PCI_D3hot); | |
10941 | ||
72fd0718 | 10942 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 10943 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
72fd0718 | 10944 | |
a2fbb9ea ET |
10945 | if (bp->regview) |
10946 | iounmap(bp->regview); | |
10947 | ||
10948 | if (bp->doorbells) | |
10949 | iounmap(bp->doorbells); | |
10950 | ||
523224a3 DK |
10951 | bnx2x_free_mem_bp(bp); |
10952 | ||
a2fbb9ea | 10953 | free_netdev(dev); |
34f80b04 EG |
10954 | |
10955 | if (atomic_read(&pdev->enable_cnt) == 1) | |
10956 | pci_release_regions(pdev); | |
10957 | ||
a2fbb9ea ET |
10958 | pci_disable_device(pdev); |
10959 | pci_set_drvdata(pdev, NULL); | |
10960 | } | |
10961 | ||
f8ef6e44 YG |
10962 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
10963 | { | |
10964 | int i; | |
10965 | ||
10966 | bp->state = BNX2X_STATE_ERROR; | |
10967 | ||
10968 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
10969 | ||
619c5cb6 VZ |
10970 | #ifdef BCM_CNIC |
10971 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
10972 | #endif | |
10973 | /* Stop Tx */ | |
10974 | bnx2x_tx_disable(bp); | |
10975 | ||
f8ef6e44 YG |
10976 | bnx2x_netif_stop(bp, 0); |
10977 | ||
10978 | del_timer_sync(&bp->timer); | |
619c5cb6 VZ |
10979 | |
10980 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
f8ef6e44 YG |
10981 | |
10982 | /* Release IRQs */ | |
d6214d7a | 10983 | bnx2x_free_irq(bp); |
f8ef6e44 | 10984 | |
f8ef6e44 YG |
10985 | /* Free SKBs, SGEs, TPA pool and driver internals */ |
10986 | bnx2x_free_skbs(bp); | |
523224a3 | 10987 | |
ec6ba945 | 10988 | for_each_rx_queue(bp, i) |
f8ef6e44 | 10989 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); |
d6214d7a | 10990 | |
f8ef6e44 YG |
10991 | bnx2x_free_mem(bp); |
10992 | ||
10993 | bp->state = BNX2X_STATE_CLOSED; | |
10994 | ||
619c5cb6 VZ |
10995 | netif_carrier_off(bp->dev); |
10996 | ||
f8ef6e44 YG |
10997 | return 0; |
10998 | } | |
10999 | ||
11000 | static void bnx2x_eeh_recover(struct bnx2x *bp) | |
11001 | { | |
11002 | u32 val; | |
11003 | ||
11004 | mutex_init(&bp->port.phy_mutex); | |
11005 | ||
11006 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
11007 | bp->link_params.shmem_base = bp->common.shmem_base; | |
11008 | BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base); | |
11009 | ||
11010 | if (!bp->common.shmem_base || | |
11011 | (bp->common.shmem_base < 0xA0000) || | |
11012 | (bp->common.shmem_base >= 0xC0000)) { | |
11013 | BNX2X_DEV_INFO("MCP not active\n"); | |
11014 | bp->flags |= NO_MCP_FLAG; | |
11015 | return; | |
11016 | } | |
11017 | ||
11018 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
11019 | if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
11020 | != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
11021 | BNX2X_ERR("BAD MCP validity signature\n"); | |
11022 | ||
11023 | if (!BP_NOMCP(bp)) { | |
f2e0899f DK |
11024 | bp->fw_seq = |
11025 | (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
11026 | DRV_MSG_SEQ_NUMBER_MASK); | |
f8ef6e44 YG |
11027 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); |
11028 | } | |
11029 | } | |
11030 | ||
493adb1f WX |
11031 | /** |
11032 | * bnx2x_io_error_detected - called when PCI error is detected | |
11033 | * @pdev: Pointer to PCI device | |
11034 | * @state: The current pci connection state | |
11035 | * | |
11036 | * This function is called after a PCI bus error affecting | |
11037 | * this device has been detected. | |
11038 | */ | |
11039 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
11040 | pci_channel_state_t state) | |
11041 | { | |
11042 | struct net_device *dev = pci_get_drvdata(pdev); | |
11043 | struct bnx2x *bp = netdev_priv(dev); | |
11044 | ||
11045 | rtnl_lock(); | |
11046 | ||
11047 | netif_device_detach(dev); | |
11048 | ||
07ce50e4 DN |
11049 | if (state == pci_channel_io_perm_failure) { |
11050 | rtnl_unlock(); | |
11051 | return PCI_ERS_RESULT_DISCONNECT; | |
11052 | } | |
11053 | ||
493adb1f | 11054 | if (netif_running(dev)) |
f8ef6e44 | 11055 | bnx2x_eeh_nic_unload(bp); |
493adb1f WX |
11056 | |
11057 | pci_disable_device(pdev); | |
11058 | ||
11059 | rtnl_unlock(); | |
11060 | ||
11061 | /* Request a slot reset */ | |
11062 | return PCI_ERS_RESULT_NEED_RESET; | |
11063 | } | |
11064 | ||
11065 | /** | |
11066 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
11067 | * @pdev: Pointer to PCI device | |
11068 | * | |
11069 | * Restart the card from scratch, as if from a cold-boot. | |
11070 | */ | |
11071 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
11072 | { | |
11073 | struct net_device *dev = pci_get_drvdata(pdev); | |
11074 | struct bnx2x *bp = netdev_priv(dev); | |
11075 | ||
11076 | rtnl_lock(); | |
11077 | ||
11078 | if (pci_enable_device(pdev)) { | |
11079 | dev_err(&pdev->dev, | |
11080 | "Cannot re-enable PCI device after reset\n"); | |
11081 | rtnl_unlock(); | |
11082 | return PCI_ERS_RESULT_DISCONNECT; | |
11083 | } | |
11084 | ||
11085 | pci_set_master(pdev); | |
11086 | pci_restore_state(pdev); | |
11087 | ||
11088 | if (netif_running(dev)) | |
11089 | bnx2x_set_power_state(bp, PCI_D0); | |
11090 | ||
11091 | rtnl_unlock(); | |
11092 | ||
11093 | return PCI_ERS_RESULT_RECOVERED; | |
11094 | } | |
11095 | ||
11096 | /** | |
11097 | * bnx2x_io_resume - called when traffic can start flowing again | |
11098 | * @pdev: Pointer to PCI device | |
11099 | * | |
11100 | * This callback is called when the error recovery driver tells us that | |
11101 | * its OK to resume normal operation. | |
11102 | */ | |
11103 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
11104 | { | |
11105 | struct net_device *dev = pci_get_drvdata(pdev); | |
11106 | struct bnx2x *bp = netdev_priv(dev); | |
11107 | ||
72fd0718 | 11108 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
754a2f52 DK |
11109 | netdev_err(bp->dev, "Handling parity error recovery. " |
11110 | "Try again later\n"); | |
72fd0718 VZ |
11111 | return; |
11112 | } | |
11113 | ||
493adb1f WX |
11114 | rtnl_lock(); |
11115 | ||
f8ef6e44 YG |
11116 | bnx2x_eeh_recover(bp); |
11117 | ||
493adb1f | 11118 | if (netif_running(dev)) |
f8ef6e44 | 11119 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
11120 | |
11121 | netif_device_attach(dev); | |
11122 | ||
11123 | rtnl_unlock(); | |
11124 | } | |
11125 | ||
11126 | static struct pci_error_handlers bnx2x_err_handler = { | |
11127 | .error_detected = bnx2x_io_error_detected, | |
356e2385 EG |
11128 | .slot_reset = bnx2x_io_slot_reset, |
11129 | .resume = bnx2x_io_resume, | |
493adb1f WX |
11130 | }; |
11131 | ||
a2fbb9ea | 11132 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
11133 | .name = DRV_MODULE_NAME, |
11134 | .id_table = bnx2x_pci_tbl, | |
11135 | .probe = bnx2x_init_one, | |
11136 | .remove = __devexit_p(bnx2x_remove_one), | |
11137 | .suspend = bnx2x_suspend, | |
11138 | .resume = bnx2x_resume, | |
11139 | .err_handler = &bnx2x_err_handler, | |
a2fbb9ea ET |
11140 | }; |
11141 | ||
11142 | static int __init bnx2x_init(void) | |
11143 | { | |
dd21ca6d SG |
11144 | int ret; |
11145 | ||
7995c64e | 11146 | pr_info("%s", version); |
938cf541 | 11147 | |
1cf167f2 EG |
11148 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
11149 | if (bnx2x_wq == NULL) { | |
7995c64e | 11150 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
11151 | return -ENOMEM; |
11152 | } | |
11153 | ||
dd21ca6d SG |
11154 | ret = pci_register_driver(&bnx2x_pci_driver); |
11155 | if (ret) { | |
7995c64e | 11156 | pr_err("Cannot register driver\n"); |
dd21ca6d SG |
11157 | destroy_workqueue(bnx2x_wq); |
11158 | } | |
11159 | return ret; | |
a2fbb9ea ET |
11160 | } |
11161 | ||
11162 | static void __exit bnx2x_cleanup(void) | |
11163 | { | |
11164 | pci_unregister_driver(&bnx2x_pci_driver); | |
1cf167f2 EG |
11165 | |
11166 | destroy_workqueue(bnx2x_wq); | |
a2fbb9ea ET |
11167 | } |
11168 | ||
3deb8167 YR |
11169 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
11170 | { | |
11171 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
11172 | } | |
11173 | ||
a2fbb9ea ET |
11174 | module_init(bnx2x_init); |
11175 | module_exit(bnx2x_cleanup); | |
11176 | ||
993ac7b5 | 11177 | #ifdef BCM_CNIC |
619c5cb6 VZ |
11178 | /** |
11179 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
11180 | * | |
11181 | * @bp: driver handle | |
11182 | * @set: set or clear the CAM entry | |
11183 | * | |
11184 | * This function will wait until the ramdord completion returns. | |
11185 | * Return 0 if success, -ENODEV if ramrod doesn't return. | |
11186 | */ | |
11187 | static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) | |
11188 | { | |
11189 | unsigned long ramrod_flags = 0; | |
11190 | ||
11191 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
11192 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
11193 | &bp->iscsi_l2_mac_obj, true, | |
11194 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
11195 | } | |
993ac7b5 MC |
11196 | |
11197 | /* count denotes the number of new completions we have seen */ | |
11198 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
11199 | { | |
11200 | struct eth_spe *spe; | |
11201 | ||
11202 | #ifdef BNX2X_STOP_ON_ERROR | |
11203 | if (unlikely(bp->panic)) | |
11204 | return; | |
11205 | #endif | |
11206 | ||
11207 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 11208 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
11209 | bp->cnic_spq_pending -= count; |
11210 | ||
993ac7b5 | 11211 | |
c2bff63f DK |
11212 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
11213 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
11214 | & SPE_HDR_CONN_TYPE) >> | |
11215 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
11216 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
11217 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
11218 | |
11219 | /* Set validation for iSCSI L2 client before sending SETUP | |
11220 | * ramrod | |
11221 | */ | |
11222 | if (type == ETH_CONNECTION_TYPE) { | |
c2bff63f | 11223 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) |
619c5cb6 VZ |
11224 | bnx2x_set_ctx_validation(bp, &bp->context. |
11225 | vcxt[BNX2X_ISCSI_ETH_CID].eth, | |
11226 | BNX2X_ISCSI_ETH_CID); | |
c2bff63f DK |
11227 | } |
11228 | ||
619c5cb6 VZ |
11229 | /* |
11230 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
11231 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
11232 | * COMMON ramrods is not more than the EQ and SPQ can |
11233 | * accommodate. | |
c2bff63f | 11234 | */ |
6e30dd4e VZ |
11235 | if (type == ETH_CONNECTION_TYPE) { |
11236 | if (!atomic_read(&bp->cq_spq_left)) | |
11237 | break; | |
11238 | else | |
11239 | atomic_dec(&bp->cq_spq_left); | |
11240 | } else if (type == NONE_CONNECTION_TYPE) { | |
11241 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
11242 | break; |
11243 | else | |
6e30dd4e | 11244 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
11245 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
11246 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
11247 | if (bp->cnic_spq_pending >= |
11248 | bp->cnic_eth_dev.max_kwqe_pending) | |
11249 | break; | |
11250 | else | |
11251 | bp->cnic_spq_pending++; | |
11252 | } else { | |
11253 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
11254 | bnx2x_panic(); | |
993ac7b5 | 11255 | break; |
c2bff63f | 11256 | } |
993ac7b5 MC |
11257 | |
11258 | spe = bnx2x_sp_get_next(bp); | |
11259 | *spe = *bp->cnic_kwq_cons; | |
11260 | ||
993ac7b5 MC |
11261 | DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", |
11262 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); | |
11263 | ||
11264 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
11265 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
11266 | else | |
11267 | bp->cnic_kwq_cons++; | |
11268 | } | |
11269 | bnx2x_sp_prod_update(bp); | |
11270 | spin_unlock_bh(&bp->spq_lock); | |
11271 | } | |
11272 | ||
11273 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
11274 | struct kwqe_16 *kwqes[], u32 count) | |
11275 | { | |
11276 | struct bnx2x *bp = netdev_priv(dev); | |
11277 | int i; | |
11278 | ||
11279 | #ifdef BNX2X_STOP_ON_ERROR | |
11280 | if (unlikely(bp->panic)) | |
11281 | return -EIO; | |
11282 | #endif | |
11283 | ||
11284 | spin_lock_bh(&bp->spq_lock); | |
11285 | ||
11286 | for (i = 0; i < count; i++) { | |
11287 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
11288 | ||
11289 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
11290 | break; | |
11291 | ||
11292 | *bp->cnic_kwq_prod = *spe; | |
11293 | ||
11294 | bp->cnic_kwq_pending++; | |
11295 | ||
11296 | DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", | |
11297 | spe->hdr.conn_and_cmd_data, spe->hdr.type, | |
523224a3 DK |
11298 | spe->data.update_data_addr.hi, |
11299 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
11300 | bp->cnic_kwq_pending); |
11301 | ||
11302 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
11303 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
11304 | else | |
11305 | bp->cnic_kwq_prod++; | |
11306 | } | |
11307 | ||
11308 | spin_unlock_bh(&bp->spq_lock); | |
11309 | ||
11310 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
11311 | bnx2x_cnic_sp_post(bp, 0); | |
11312 | ||
11313 | return i; | |
11314 | } | |
11315 | ||
11316 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
11317 | { | |
11318 | struct cnic_ops *c_ops; | |
11319 | int rc = 0; | |
11320 | ||
11321 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
11322 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
11323 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
11324 | if (c_ops) |
11325 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
11326 | mutex_unlock(&bp->cnic_mutex); | |
11327 | ||
11328 | return rc; | |
11329 | } | |
11330 | ||
11331 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
11332 | { | |
11333 | struct cnic_ops *c_ops; | |
11334 | int rc = 0; | |
11335 | ||
11336 | rcu_read_lock(); | |
11337 | c_ops = rcu_dereference(bp->cnic_ops); | |
11338 | if (c_ops) | |
11339 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
11340 | rcu_read_unlock(); | |
11341 | ||
11342 | return rc; | |
11343 | } | |
11344 | ||
11345 | /* | |
11346 | * for commands that have no data | |
11347 | */ | |
9f6c9258 | 11348 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
11349 | { |
11350 | struct cnic_ctl_info ctl = {0}; | |
11351 | ||
11352 | ctl.cmd = cmd; | |
11353 | ||
11354 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
11355 | } | |
11356 | ||
619c5cb6 | 11357 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 11358 | { |
619c5cb6 | 11359 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
11360 | |
11361 | /* first we tell CNIC and only then we count this as a completion */ | |
11362 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
11363 | ctl.data.comp.cid = cid; | |
619c5cb6 | 11364 | ctl.data.comp.error = err; |
993ac7b5 MC |
11365 | |
11366 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 11367 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
11368 | } |
11369 | ||
619c5cb6 VZ |
11370 | |
11371 | /* Called with netif_addr_lock_bh() taken. | |
11372 | * Sets an rx_mode config for an iSCSI ETH client. | |
11373 | * Doesn't block. | |
11374 | * Completion should be checked outside. | |
11375 | */ | |
11376 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
11377 | { | |
11378 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
11379 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
11380 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
11381 | ||
11382 | if (start) { | |
11383 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
11384 | * because it's the only way for UIO Queue to accept | |
11385 | * multicasts (in non-promiscuous mode only one Queue per | |
11386 | * function will receive multicast packets (leading in our | |
11387 | * case). | |
11388 | */ | |
11389 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
11390 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
11391 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
11392 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
11393 | ||
11394 | /* Clear STOP_PENDING bit if START is requested */ | |
11395 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
11396 | ||
11397 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
11398 | } else | |
11399 | /* Clear START_PENDING bit if STOP is requested */ | |
11400 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
11401 | ||
11402 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
11403 | set_bit(sched_state, &bp->sp_state); | |
11404 | else { | |
11405 | __set_bit(RAMROD_RX, &ramrod_flags); | |
11406 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
11407 | ramrod_flags); | |
11408 | } | |
11409 | } | |
11410 | ||
11411 | ||
993ac7b5 MC |
11412 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
11413 | { | |
11414 | struct bnx2x *bp = netdev_priv(dev); | |
11415 | int rc = 0; | |
11416 | ||
11417 | switch (ctl->cmd) { | |
11418 | case DRV_CTL_CTXTBL_WR_CMD: { | |
11419 | u32 index = ctl->data.io.offset; | |
11420 | dma_addr_t addr = ctl->data.io.dma_addr; | |
11421 | ||
11422 | bnx2x_ilt_wr(bp, index, addr); | |
11423 | break; | |
11424 | } | |
11425 | ||
c2bff63f DK |
11426 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
11427 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
11428 | |
11429 | bnx2x_cnic_sp_post(bp, count); | |
11430 | break; | |
11431 | } | |
11432 | ||
11433 | /* rtnl_lock is held. */ | |
11434 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
11435 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
11436 | unsigned long sp_bits = 0; | |
11437 | ||
11438 | /* Configure the iSCSI classification object */ | |
11439 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
11440 | cp->iscsi_l2_client_id, | |
11441 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
11442 | bnx2x_sp(bp, mac_rdata), | |
11443 | bnx2x_sp_mapping(bp, mac_rdata), | |
11444 | BNX2X_FILTER_MAC_PENDING, | |
11445 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
11446 | &bp->macs_pool); | |
ec6ba945 | 11447 | |
523224a3 | 11448 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
11449 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
11450 | if (rc) | |
11451 | break; | |
523224a3 DK |
11452 | |
11453 | mmiowb(); | |
11454 | barrier(); | |
11455 | ||
619c5cb6 VZ |
11456 | /* Start accepting on iSCSI L2 ring */ |
11457 | ||
11458 | netif_addr_lock_bh(dev); | |
11459 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
11460 | netif_addr_unlock_bh(dev); | |
11461 | ||
11462 | /* bits to wait on */ | |
11463 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
11464 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
11465 | ||
11466 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
11467 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 11468 | |
993ac7b5 MC |
11469 | break; |
11470 | } | |
11471 | ||
11472 | /* rtnl_lock is held. */ | |
11473 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 11474 | unsigned long sp_bits = 0; |
993ac7b5 | 11475 | |
523224a3 | 11476 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
11477 | netif_addr_lock_bh(dev); |
11478 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
11479 | netif_addr_unlock_bh(dev); | |
11480 | ||
11481 | /* bits to wait on */ | |
11482 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
11483 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
11484 | ||
11485 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
11486 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
11487 | |
11488 | mmiowb(); | |
11489 | barrier(); | |
11490 | ||
11491 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
11492 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
11493 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
11494 | break; |
11495 | } | |
c2bff63f DK |
11496 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
11497 | int count = ctl->data.credit.credit_count; | |
11498 | ||
11499 | smp_mb__before_atomic_inc(); | |
6e30dd4e | 11500 | atomic_add(count, &bp->cq_spq_left); |
c2bff63f DK |
11501 | smp_mb__after_atomic_inc(); |
11502 | break; | |
11503 | } | |
993ac7b5 MC |
11504 | |
11505 | default: | |
11506 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
11507 | rc = -EINVAL; | |
11508 | } | |
11509 | ||
11510 | return rc; | |
11511 | } | |
11512 | ||
9f6c9258 | 11513 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
11514 | { |
11515 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
11516 | ||
11517 | if (bp->flags & USING_MSIX_FLAG) { | |
11518 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
11519 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
11520 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
11521 | } else { | |
11522 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
11523 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
11524 | } | |
619c5cb6 | 11525 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
11526 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
11527 | else | |
11528 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
11529 | ||
619c5cb6 VZ |
11530 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
11531 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
11532 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
11533 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 11534 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
11535 | |
11536 | cp->num_irq = 2; | |
11537 | } | |
11538 | ||
11539 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, | |
11540 | void *data) | |
11541 | { | |
11542 | struct bnx2x *bp = netdev_priv(dev); | |
11543 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
11544 | ||
11545 | if (ops == NULL) | |
11546 | return -EINVAL; | |
11547 | ||
993ac7b5 MC |
11548 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
11549 | if (!bp->cnic_kwq) | |
11550 | return -ENOMEM; | |
11551 | ||
11552 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
11553 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
11554 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
11555 | ||
11556 | bp->cnic_spq_pending = 0; | |
11557 | bp->cnic_kwq_pending = 0; | |
11558 | ||
11559 | bp->cnic_data = data; | |
11560 | ||
11561 | cp->num_irq = 0; | |
619c5cb6 | 11562 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 11563 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 11564 | |
993ac7b5 | 11565 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 11566 | |
993ac7b5 MC |
11567 | rcu_assign_pointer(bp->cnic_ops, ops); |
11568 | ||
11569 | return 0; | |
11570 | } | |
11571 | ||
11572 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
11573 | { | |
11574 | struct bnx2x *bp = netdev_priv(dev); | |
11575 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
11576 | ||
11577 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 MC |
11578 | cp->drv_state = 0; |
11579 | rcu_assign_pointer(bp->cnic_ops, NULL); | |
11580 | mutex_unlock(&bp->cnic_mutex); | |
11581 | synchronize_rcu(); | |
11582 | kfree(bp->cnic_kwq); | |
11583 | bp->cnic_kwq = NULL; | |
11584 | ||
11585 | return 0; | |
11586 | } | |
11587 | ||
11588 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) | |
11589 | { | |
11590 | struct bnx2x *bp = netdev_priv(dev); | |
11591 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
11592 | ||
2ba45142 VZ |
11593 | /* If both iSCSI and FCoE are disabled - return NULL in |
11594 | * order to indicate CNIC that it should not try to work | |
11595 | * with this device. | |
11596 | */ | |
11597 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
11598 | return NULL; | |
11599 | ||
993ac7b5 MC |
11600 | cp->drv_owner = THIS_MODULE; |
11601 | cp->chip_id = CHIP_ID(bp); | |
11602 | cp->pdev = bp->pdev; | |
11603 | cp->io_base = bp->regview; | |
11604 | cp->io_base2 = bp->doorbells; | |
11605 | cp->max_kwqe_pending = 8; | |
523224a3 | 11606 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
11607 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
11608 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 11609 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 11610 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
11611 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
11612 | cp->drv_ctl = bnx2x_drv_ctl; | |
11613 | cp->drv_register_cnic = bnx2x_register_cnic; | |
11614 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
ec6ba945 | 11615 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; |
619c5cb6 VZ |
11616 | cp->iscsi_l2_client_id = |
11617 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
c2bff63f DK |
11618 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; |
11619 | ||
2ba45142 VZ |
11620 | if (NO_ISCSI_OOO(bp)) |
11621 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
11622 | ||
11623 | if (NO_ISCSI(bp)) | |
11624 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
11625 | ||
11626 | if (NO_FCOE(bp)) | |
11627 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
11628 | ||
c2bff63f DK |
11629 | DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " |
11630 | "starting cid %d\n", | |
11631 | cp->ctx_blk_size, | |
11632 | cp->ctx_tbl_offset, | |
11633 | cp->ctx_tbl_len, | |
11634 | cp->starting_cid); | |
993ac7b5 MC |
11635 | return cp; |
11636 | } | |
11637 | EXPORT_SYMBOL(bnx2x_cnic_probe); | |
11638 | ||
11639 | #endif /* BCM_CNIC */ | |
94a78b79 | 11640 |