]>
Commit | Line | Data |
---|---|---|
4ad79e13 | 1 | /* bnx2x_main.c: QLogic Everest network driver. |
a2fbb9ea | 2 | * |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
4ad79e13 YM |
4 | * Copyright (c) 2014 QLogic Corporation |
5 | * All rights reserved | |
a2fbb9ea ET |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
08f6dd89 | 11 | * Maintained by: Ariel Elior <ariel.elior@qlogic.com> |
24e3fcef | 12 | * Written by: Eliezer Tamir |
a2fbb9ea ET |
13 | * Based on code from Michael Chan's bnx2 driver |
14 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 15 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 16 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
17 | * |
18 | */ | |
19 | ||
f1deab50 JP |
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
21 | ||
a2fbb9ea ET |
22 | #include <linux/module.h> |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/device.h> /* for dev_info() */ | |
26 | #include <linux/timer.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/slab.h> | |
a2fbb9ea ET |
30 | #include <linux/interrupt.h> |
31 | #include <linux/pci.h> | |
33d8e6a5 | 32 | #include <linux/aer.h> |
a2fbb9ea ET |
33 | #include <linux/init.h> |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/etherdevice.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/dma-mapping.h> | |
38 | #include <linux/bitops.h> | |
39 | #include <linux/irq.h> | |
40 | #include <linux/delay.h> | |
41 | #include <asm/byteorder.h> | |
42 | #include <linux/time.h> | |
43 | #include <linux/ethtool.h> | |
44 | #include <linux/mii.h> | |
0c6671b0 | 45 | #include <linux/if_vlan.h> |
c9931896 | 46 | #include <linux/crash_dump.h> |
a2fbb9ea | 47 | #include <net/ip.h> |
619c5cb6 | 48 | #include <net/ipv6.h> |
a2fbb9ea | 49 | #include <net/tcp.h> |
51de7bb9 | 50 | #include <net/vxlan.h> |
a2fbb9ea | 51 | #include <net/checksum.h> |
34f80b04 | 52 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
53 | #include <linux/workqueue.h> |
54 | #include <linux/crc32.h> | |
34f80b04 | 55 | #include <linux/crc32c.h> |
a2fbb9ea ET |
56 | #include <linux/prefetch.h> |
57 | #include <linux/zlib.h> | |
a2fbb9ea | 58 | #include <linux/io.h> |
452427b0 | 59 | #include <linux/semaphore.h> |
45229b42 | 60 | #include <linux/stringify.h> |
7ab24bfd | 61 | #include <linux/vmalloc.h> |
a2fbb9ea ET |
62 | #include "bnx2x.h" |
63 | #include "bnx2x_init.h" | |
94a78b79 | 64 | #include "bnx2x_init_ops.h" |
9f6c9258 | 65 | #include "bnx2x_cmn.h" |
1ab4434c | 66 | #include "bnx2x_vfpf.h" |
e4901dde | 67 | #include "bnx2x_dcb.h" |
042181f5 | 68 | #include "bnx2x_sp.h" |
94a78b79 VZ |
69 | #include <linux/firmware.h> |
70 | #include "bnx2x_fw_file_hdr.h" | |
71 | /* FW files */ | |
45229b42 BH |
72 | #define FW_FILE_VERSION \ |
73 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
74 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
75 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
76 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
77 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
78 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 79 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 80 | |
34f80b04 EG |
81 | /* Time in jiffies before concluding the transmitter is hung */ |
82 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 83 | |
0329aba1 | 84 | static char version[] = |
4ad79e13 | 85 | "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
86 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
87 | ||
24e3fcef | 88 | MODULE_AUTHOR("Eliezer Tamir"); |
4ad79e13 | 89 | MODULE_DESCRIPTION("QLogic " |
619c5cb6 VZ |
90 | "BCM57710/57711/57711E/" |
91 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
92 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
93 | MODULE_LICENSE("GPL"); |
94 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
95 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
96 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 97 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 98 | |
a8f47eb7 | 99 | int bnx2x_num_queues; |
1c8bb760 | 100 | module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO); |
96305234 DK |
101 | MODULE_PARM_DESC(num_queues, |
102 | " Set number of queues (default is as a number of CPUs)"); | |
555f6c78 | 103 | |
19680c48 | 104 | static int disable_tpa; |
1c8bb760 | 105 | module_param(disable_tpa, int, S_IRUGO); |
9898f86d | 106 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 107 | |
a8f47eb7 | 108 | static int int_mode; |
1c8bb760 | 109 | module_param(int_mode, int, S_IRUGO); |
619c5cb6 | 110 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 111 | "(1 INT#x; 2 MSI)"); |
8badd27a | 112 | |
a18f5128 | 113 | static int dropless_fc; |
1c8bb760 | 114 | module_param(dropless_fc, int, S_IRUGO); |
a18f5128 EG |
115 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); |
116 | ||
8d5726c4 | 117 | static int mrrs = -1; |
1c8bb760 | 118 | module_param(mrrs, int, S_IRUGO); |
8d5726c4 EG |
119 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); |
120 | ||
9898f86d | 121 | static int debug; |
1c8bb760 | 122 | module_param(debug, int, S_IRUGO); |
9898f86d EG |
123 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
124 | ||
370d4a26 YM |
125 | static struct workqueue_struct *bnx2x_wq; |
126 | struct workqueue_struct *bnx2x_iov_wq; | |
ec6ba945 | 127 | |
1ef1d45a BW |
128 | struct bnx2x_mac_vals { |
129 | u32 xmac_addr; | |
130 | u32 xmac_val; | |
131 | u32 emac_addr; | |
132 | u32 emac_val; | |
3d6b7253 YM |
133 | u32 umac_addr[2]; |
134 | u32 umac_val[2]; | |
1ef1d45a BW |
135 | u32 bmac_addr; |
136 | u32 bmac_val[2]; | |
137 | }; | |
138 | ||
a2fbb9ea ET |
139 | enum bnx2x_board_type { |
140 | BCM57710 = 0, | |
619c5cb6 VZ |
141 | BCM57711, |
142 | BCM57711E, | |
143 | BCM57712, | |
144 | BCM57712_MF, | |
1ab4434c | 145 | BCM57712_VF, |
619c5cb6 VZ |
146 | BCM57800, |
147 | BCM57800_MF, | |
1ab4434c | 148 | BCM57800_VF, |
619c5cb6 VZ |
149 | BCM57810, |
150 | BCM57810_MF, | |
1ab4434c | 151 | BCM57810_VF, |
c3def943 YM |
152 | BCM57840_4_10, |
153 | BCM57840_2_20, | |
7e8e02df | 154 | BCM57840_MF, |
1ab4434c | 155 | BCM57840_VF, |
7e8e02df | 156 | BCM57811, |
1ab4434c AE |
157 | BCM57811_MF, |
158 | BCM57840_O, | |
159 | BCM57840_MFO, | |
160 | BCM57811_VF | |
a2fbb9ea ET |
161 | }; |
162 | ||
34f80b04 | 163 | /* indexed by board_type, above */ |
53a10565 | 164 | static struct { |
a2fbb9ea | 165 | char *name; |
0329aba1 | 166 | } board_info[] = { |
4ad79e13 YM |
167 | [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" }, |
168 | [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" }, | |
169 | [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" }, | |
170 | [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" }, | |
171 | [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" }, | |
172 | [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" }, | |
173 | [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" }, | |
174 | [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" }, | |
175 | [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" }, | |
176 | [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" }, | |
177 | [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" }, | |
178 | [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" }, | |
179 | [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" }, | |
180 | [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" }, | |
181 | [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
182 | [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }, | |
183 | [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" }, | |
184 | [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" }, | |
185 | [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" }, | |
186 | [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
187 | [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" } | |
a2fbb9ea ET |
188 | }; |
189 | ||
619c5cb6 VZ |
190 | #ifndef PCI_DEVICE_ID_NX2_57710 |
191 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
192 | #endif | |
193 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
194 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
195 | #endif | |
196 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
197 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
198 | #endif | |
199 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
200 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
201 | #endif | |
202 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
203 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
204 | #endif | |
8395be5e AE |
205 | #ifndef PCI_DEVICE_ID_NX2_57712_VF |
206 | #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF | |
207 | #endif | |
619c5cb6 VZ |
208 | #ifndef PCI_DEVICE_ID_NX2_57800 |
209 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
210 | #endif | |
211 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
212 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
213 | #endif | |
8395be5e AE |
214 | #ifndef PCI_DEVICE_ID_NX2_57800_VF |
215 | #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF | |
216 | #endif | |
619c5cb6 VZ |
217 | #ifndef PCI_DEVICE_ID_NX2_57810 |
218 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
219 | #endif | |
220 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
221 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
222 | #endif | |
c3def943 YM |
223 | #ifndef PCI_DEVICE_ID_NX2_57840_O |
224 | #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE | |
225 | #endif | |
8395be5e AE |
226 | #ifndef PCI_DEVICE_ID_NX2_57810_VF |
227 | #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF | |
228 | #endif | |
c3def943 YM |
229 | #ifndef PCI_DEVICE_ID_NX2_57840_4_10 |
230 | #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 | |
231 | #endif | |
232 | #ifndef PCI_DEVICE_ID_NX2_57840_2_20 | |
233 | #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 | |
234 | #endif | |
235 | #ifndef PCI_DEVICE_ID_NX2_57840_MFO | |
236 | #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE | |
619c5cb6 VZ |
237 | #endif |
238 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
239 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
240 | #endif | |
8395be5e AE |
241 | #ifndef PCI_DEVICE_ID_NX2_57840_VF |
242 | #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF | |
243 | #endif | |
7e8e02df BW |
244 | #ifndef PCI_DEVICE_ID_NX2_57811 |
245 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 | |
246 | #endif | |
247 | #ifndef PCI_DEVICE_ID_NX2_57811_MF | |
248 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF | |
249 | #endif | |
8395be5e AE |
250 | #ifndef PCI_DEVICE_ID_NX2_57811_VF |
251 | #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF | |
252 | #endif | |
253 | ||
9baa3c34 | 254 | static const struct pci_device_id bnx2x_pci_tbl[] = { |
e4ed7113 EG |
255 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
256 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
257 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 258 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 | 259 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
8395be5e | 260 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, |
619c5cb6 VZ |
261 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, |
262 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
8395be5e | 263 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, |
619c5cb6 VZ |
264 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, |
265 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
c3def943 YM |
266 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, |
267 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, | |
9c9a6524 | 268 | { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, |
c3def943 | 269 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, |
8395be5e | 270 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, |
c3def943 | 271 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, |
619c5cb6 | 272 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, |
9c9a6524 | 273 | { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, |
8395be5e | 274 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, |
9c9a6524 | 275 | { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, |
7e8e02df BW |
276 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
277 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, | |
8395be5e | 278 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, |
a2fbb9ea ET |
279 | { 0 } |
280 | }; | |
281 | ||
282 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
283 | ||
452427b0 YM |
284 | /* Global resources for unloading a previously loaded device */ |
285 | #define BNX2X_PREV_WAIT_NEEDED 1 | |
286 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); | |
287 | static LIST_HEAD(bnx2x_prev_list); | |
a8f47eb7 | 288 | |
289 | /* Forward declaration */ | |
290 | static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); | |
291 | static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); | |
292 | static int bnx2x_set_storm_rx_mode(struct bnx2x *bp); | |
293 | ||
a2fbb9ea ET |
294 | /**************************************************************************** |
295 | * General service functions | |
296 | ****************************************************************************/ | |
297 | ||
eeed018c MK |
298 | static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr); |
299 | ||
1191cb83 | 300 | static void __storm_memset_dma_mapping(struct bnx2x *bp, |
619c5cb6 VZ |
301 | u32 addr, dma_addr_t mapping) |
302 | { | |
303 | REG_WR(bp, addr, U64_LO(mapping)); | |
304 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
305 | } | |
306 | ||
1191cb83 ED |
307 | static void storm_memset_spq_addr(struct bnx2x *bp, |
308 | dma_addr_t mapping, u16 abs_fid) | |
619c5cb6 VZ |
309 | { |
310 | u32 addr = XSEM_REG_FAST_MEMORY + | |
311 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
312 | ||
313 | __storm_memset_dma_mapping(bp, addr, mapping); | |
314 | } | |
315 | ||
1191cb83 ED |
316 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, |
317 | u16 pf_id) | |
523224a3 | 318 | { |
619c5cb6 VZ |
319 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
320 | pf_id); | |
321 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
322 | pf_id); | |
323 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
324 | pf_id); | |
325 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
326 | pf_id); | |
523224a3 DK |
327 | } |
328 | ||
1191cb83 ED |
329 | static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
330 | u8 enable) | |
619c5cb6 VZ |
331 | { |
332 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
333 | enable); | |
334 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
335 | enable); | |
336 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
337 | enable); | |
338 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
339 | enable); | |
340 | } | |
523224a3 | 341 | |
1191cb83 ED |
342 | static void storm_memset_eq_data(struct bnx2x *bp, |
343 | struct event_ring_data *eq_data, | |
523224a3 DK |
344 | u16 pfid) |
345 | { | |
346 | size_t size = sizeof(struct event_ring_data); | |
347 | ||
348 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
349 | ||
350 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
351 | } | |
352 | ||
1191cb83 ED |
353 | static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, |
354 | u16 pfid) | |
523224a3 DK |
355 | { |
356 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
357 | REG_WR16(bp, addr, eq_prod); | |
358 | } | |
359 | ||
a2fbb9ea ET |
360 | /* used only at init |
361 | * locking is done by mcp | |
362 | */ | |
8d96286a | 363 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
364 | { |
365 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
366 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
367 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
368 | PCICFG_VENDOR_ID_OFFSET); | |
369 | } | |
370 | ||
a2fbb9ea ET |
371 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
372 | { | |
373 | u32 val; | |
374 | ||
375 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
376 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
377 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
378 | PCICFG_VENDOR_ID_OFFSET); | |
379 | ||
380 | return val; | |
381 | } | |
a2fbb9ea | 382 | |
f2e0899f DK |
383 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
384 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
385 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
386 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
387 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
388 | ||
6bf07b8e YM |
389 | static void bnx2x_dp_dmae(struct bnx2x *bp, |
390 | struct dmae_command *dmae, int msglvl) | |
fd1fc79d AE |
391 | { |
392 | u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; | |
6bf07b8e | 393 | int i; |
fd1fc79d AE |
394 | |
395 | switch (dmae->opcode & DMAE_COMMAND_DST) { | |
396 | case DMAE_CMD_DST_PCI: | |
397 | if (src_type == DMAE_CMD_SRC_PCI) | |
398 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
399 | "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" | |
400 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
401 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
402 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
403 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
404 | dmae->comp_val); | |
405 | else | |
406 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
407 | "src [%08x], len [%d*4], dst [%x:%08x]\n" | |
408 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
409 | dmae->opcode, dmae->src_addr_lo >> 2, | |
410 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
411 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
412 | dmae->comp_val); | |
413 | break; | |
414 | case DMAE_CMD_DST_GRC: | |
415 | if (src_type == DMAE_CMD_SRC_PCI) | |
416 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
417 | "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" | |
418 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
419 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
420 | dmae->len, dmae->dst_addr_lo >> 2, | |
421 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
422 | dmae->comp_val); | |
423 | else | |
424 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
425 | "src [%08x], len [%d*4], dst [%08x]\n" | |
426 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
427 | dmae->opcode, dmae->src_addr_lo >> 2, | |
428 | dmae->len, dmae->dst_addr_lo >> 2, | |
429 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
430 | dmae->comp_val); | |
431 | break; | |
432 | default: | |
433 | if (src_type == DMAE_CMD_SRC_PCI) | |
434 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
435 | "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" | |
436 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
437 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
438 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
439 | dmae->comp_val); | |
440 | else | |
441 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
442 | "src_addr [%08x] len [%d * 4] dst_addr [none]\n" | |
443 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
444 | dmae->opcode, dmae->src_addr_lo >> 2, | |
445 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
446 | dmae->comp_val); | |
447 | break; | |
448 | } | |
6bf07b8e YM |
449 | |
450 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) | |
451 | DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", | |
452 | i, *(((u32 *)dmae) + i)); | |
fd1fc79d | 453 | } |
f2e0899f | 454 | |
a2fbb9ea | 455 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 456 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
457 | { |
458 | u32 cmd_offset; | |
459 | int i; | |
460 | ||
461 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
462 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
463 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
464 | } |
465 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
466 | } | |
467 | ||
f2e0899f | 468 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 469 | { |
f2e0899f DK |
470 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
471 | DMAE_CMD_C_ENABLE); | |
472 | } | |
ad8d3948 | 473 | |
f2e0899f DK |
474 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
475 | { | |
476 | return opcode & ~DMAE_CMD_SRC_RESET; | |
477 | } | |
ad8d3948 | 478 | |
f2e0899f DK |
479 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
480 | bool with_comp, u8 comp_type) | |
481 | { | |
482 | u32 opcode = 0; | |
483 | ||
484 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
485 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 486 | |
f2e0899f DK |
487 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
488 | ||
489 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
490 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
491 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 492 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 493 | |
a2fbb9ea | 494 | #ifdef __BIG_ENDIAN |
f2e0899f | 495 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 496 | #else |
f2e0899f | 497 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 498 | #endif |
f2e0899f DK |
499 | if (with_comp) |
500 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
501 | return opcode; | |
502 | } | |
503 | ||
fd1fc79d | 504 | void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
8d96286a | 505 | struct dmae_command *dmae, |
506 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
507 | { |
508 | memset(dmae, 0, sizeof(struct dmae_command)); | |
509 | ||
510 | /* set the opcode */ | |
511 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
512 | true, DMAE_COMP_PCI); | |
513 | ||
514 | /* fill in the completion parameters */ | |
515 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
516 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
517 | dmae->comp_val = DMAE_COMP_VAL; | |
518 | } | |
519 | ||
fd1fc79d | 520 | /* issue a dmae command over the init-channel and wait for completion */ |
32316a46 AE |
521 | int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, |
522 | u32 *comp) | |
f2e0899f | 523 | { |
5e374b5a | 524 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
525 | int rc = 0; |
526 | ||
6bf07b8e YM |
527 | bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); |
528 | ||
529 | /* Lock the dmae channel. Disable BHs to prevent a dead-lock | |
619c5cb6 VZ |
530 | * as long as this code is called both from syscall context and |
531 | * from ndo_set_rx_mode() flow that may be called from BH. | |
532 | */ | |
eeed018c | 533 | |
6e30dd4e | 534 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 535 | |
f2e0899f | 536 | /* reset completion */ |
32316a46 | 537 | *comp = 0; |
a2fbb9ea | 538 | |
f2e0899f DK |
539 | /* post the command on the channel used for initializations */ |
540 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 541 | |
f2e0899f | 542 | /* wait for completion */ |
a2fbb9ea | 543 | udelay(5); |
32316a46 | 544 | while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 | 545 | |
95c6c616 AE |
546 | if (!cnt || |
547 | (bp->recovery_state != BNX2X_RECOVERY_DONE && | |
548 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
c3eefaf6 | 549 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
550 | rc = DMAE_TIMEOUT; |
551 | goto unlock; | |
a2fbb9ea | 552 | } |
ad8d3948 | 553 | cnt--; |
f2e0899f | 554 | udelay(50); |
a2fbb9ea | 555 | } |
32316a46 | 556 | if (*comp & DMAE_PCI_ERR_FLAG) { |
f2e0899f DK |
557 | BNX2X_ERR("DMAE PCI error!\n"); |
558 | rc = DMAE_PCI_ERROR; | |
559 | } | |
560 | ||
f2e0899f | 561 | unlock: |
eeed018c | 562 | |
6e30dd4e | 563 | spin_unlock_bh(&bp->dmae_lock); |
eeed018c | 564 | |
f2e0899f DK |
565 | return rc; |
566 | } | |
567 | ||
568 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
569 | u32 len32) | |
570 | { | |
6bf07b8e | 571 | int rc; |
f2e0899f DK |
572 | struct dmae_command dmae; |
573 | ||
574 | if (!bp->dmae_ready) { | |
575 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
576 | ||
127a425e AE |
577 | if (CHIP_IS_E1(bp)) |
578 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
579 | else | |
580 | bnx2x_init_str_wr(bp, dst_addr, data, len32); | |
f2e0899f DK |
581 | return; |
582 | } | |
583 | ||
584 | /* set opcode and fixed command fields */ | |
585 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
586 | ||
587 | /* fill in addresses and len */ | |
588 | dmae.src_addr_lo = U64_LO(dma_addr); | |
589 | dmae.src_addr_hi = U64_HI(dma_addr); | |
590 | dmae.dst_addr_lo = dst_addr >> 2; | |
591 | dmae.dst_addr_hi = 0; | |
592 | dmae.len = len32; | |
593 | ||
f2e0899f | 594 | /* issue the command and wait for completion */ |
32316a46 | 595 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); |
6bf07b8e YM |
596 | if (rc) { |
597 | BNX2X_ERR("DMAE returned failure %d\n", rc); | |
9dcd9acd | 598 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e | 599 | bnx2x_panic(); |
9dcd9acd | 600 | #endif |
6bf07b8e | 601 | } |
a2fbb9ea ET |
602 | } |
603 | ||
c18487ee | 604 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 605 | { |
6bf07b8e | 606 | int rc; |
5ff7b6d4 | 607 | struct dmae_command dmae; |
ad8d3948 EG |
608 | |
609 | if (!bp->dmae_ready) { | |
610 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
611 | int i; | |
612 | ||
51c1a580 | 613 | if (CHIP_IS_E1(bp)) |
127a425e AE |
614 | for (i = 0; i < len32; i++) |
615 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
51c1a580 | 616 | else |
127a425e AE |
617 | for (i = 0; i < len32; i++) |
618 | data[i] = REG_RD(bp, src_addr + i*4); | |
619 | ||
ad8d3948 EG |
620 | return; |
621 | } | |
622 | ||
f2e0899f DK |
623 | /* set opcode and fixed command fields */ |
624 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 625 | |
f2e0899f | 626 | /* fill in addresses and len */ |
5ff7b6d4 EG |
627 | dmae.src_addr_lo = src_addr >> 2; |
628 | dmae.src_addr_hi = 0; | |
629 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
630 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
631 | dmae.len = len32; | |
ad8d3948 | 632 | |
f2e0899f | 633 | /* issue the command and wait for completion */ |
32316a46 | 634 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); |
6bf07b8e YM |
635 | if (rc) { |
636 | BNX2X_ERR("DMAE returned failure %d\n", rc); | |
9dcd9acd | 637 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e | 638 | bnx2x_panic(); |
9dcd9acd | 639 | #endif |
c957d09f | 640 | } |
ad8d3948 EG |
641 | } |
642 | ||
8d96286a | 643 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
644 | u32 addr, u32 len) | |
573f2035 | 645 | { |
02e3c6cb | 646 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
647 | int offset = 0; |
648 | ||
02e3c6cb | 649 | while (len > dmae_wr_max) { |
573f2035 | 650 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
651 | addr + offset, dmae_wr_max); |
652 | offset += dmae_wr_max * 4; | |
653 | len -= dmae_wr_max; | |
573f2035 EG |
654 | } |
655 | ||
656 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
657 | } | |
658 | ||
97539f1e AE |
659 | enum storms { |
660 | XSTORM, | |
661 | TSTORM, | |
662 | CSTORM, | |
663 | USTORM, | |
664 | MAX_STORMS | |
665 | }; | |
34f80b04 | 666 | |
97539f1e AE |
667 | #define STORMS_NUM 4 |
668 | #define REGS_IN_ENTRY 4 | |
34f80b04 | 669 | |
97539f1e AE |
670 | static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp, |
671 | enum storms storm, | |
672 | int entry) | |
673 | { | |
674 | switch (storm) { | |
675 | case XSTORM: | |
676 | return XSTORM_ASSERT_LIST_OFFSET(entry); | |
677 | case TSTORM: | |
678 | return TSTORM_ASSERT_LIST_OFFSET(entry); | |
679 | case CSTORM: | |
680 | return CSTORM_ASSERT_LIST_OFFSET(entry); | |
681 | case USTORM: | |
682 | return USTORM_ASSERT_LIST_OFFSET(entry); | |
683 | case MAX_STORMS: | |
684 | default: | |
685 | BNX2X_ERR("unknown storm\n"); | |
34f80b04 | 686 | } |
97539f1e AE |
687 | return -EINVAL; |
688 | } | |
34f80b04 | 689 | |
97539f1e AE |
690 | static int bnx2x_mc_assert(struct bnx2x *bp) |
691 | { | |
692 | char last_idx; | |
693 | int i, j, rc = 0; | |
694 | enum storms storm; | |
695 | u32 regs[REGS_IN_ENTRY]; | |
696 | u32 bar_storm_intmem[STORMS_NUM] = { | |
697 | BAR_XSTRORM_INTMEM, | |
698 | BAR_TSTRORM_INTMEM, | |
699 | BAR_CSTRORM_INTMEM, | |
700 | BAR_USTRORM_INTMEM | |
701 | }; | |
702 | u32 storm_assert_list_index[STORMS_NUM] = { | |
703 | XSTORM_ASSERT_LIST_INDEX_OFFSET, | |
704 | TSTORM_ASSERT_LIST_INDEX_OFFSET, | |
705 | CSTORM_ASSERT_LIST_INDEX_OFFSET, | |
706 | USTORM_ASSERT_LIST_INDEX_OFFSET | |
707 | }; | |
708 | char *storms_string[STORMS_NUM] = { | |
709 | "XSTORM", | |
710 | "TSTORM", | |
711 | "CSTORM", | |
712 | "USTORM" | |
713 | }; | |
714 | ||
715 | for (storm = XSTORM; storm < MAX_STORMS; storm++) { | |
716 | last_idx = REG_RD8(bp, bar_storm_intmem[storm] + | |
717 | storm_assert_list_index[storm]); | |
718 | if (last_idx) | |
719 | BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n", | |
720 | storms_string[storm], last_idx); | |
721 | ||
722 | /* print the asserts */ | |
723 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
724 | /* read a single assert entry */ | |
725 | for (j = 0; j < REGS_IN_ENTRY; j++) | |
726 | regs[j] = REG_RD(bp, bar_storm_intmem[storm] + | |
727 | bnx2x_get_assert_list_entry(bp, | |
728 | storm, | |
729 | i) + | |
730 | sizeof(u32) * j); | |
731 | ||
732 | /* log entry if it contains a valid assert */ | |
733 | if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
734 | BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
735 | storms_string[storm], i, regs[3], | |
736 | regs[2], regs[1], regs[0]); | |
737 | rc++; | |
738 | } else { | |
739 | break; | |
740 | } | |
a2fbb9ea ET |
741 | } |
742 | } | |
34f80b04 | 743 | |
97539f1e AE |
744 | BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n", |
745 | CHIP_IS_E1(bp) ? "everest1" : | |
746 | CHIP_IS_E1H(bp) ? "everest1h" : | |
747 | CHIP_IS_E2(bp) ? "everest2" : "everest3", | |
748 | BCM_5710_FW_MAJOR_VERSION, | |
749 | BCM_5710_FW_MINOR_VERSION, | |
750 | BCM_5710_FW_REVISION_VERSION); | |
751 | ||
a2fbb9ea ET |
752 | return rc; |
753 | } | |
c14423fe | 754 | |
1a6974b2 YM |
755 | #define MCPR_TRACE_BUFFER_SIZE (0x800) |
756 | #define SCRATCH_BUFFER_SIZE(bp) \ | |
757 | (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000)) | |
758 | ||
7a25cc73 | 759 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 760 | { |
7a25cc73 | 761 | u32 addr, val; |
a2fbb9ea | 762 | u32 mark, offset; |
4781bfad | 763 | __be32 data[9]; |
a2fbb9ea | 764 | int word; |
f2e0899f | 765 | u32 trace_shmem_base; |
2145a920 VZ |
766 | if (BP_NOMCP(bp)) { |
767 | BNX2X_ERR("NO MCP - can not dump\n"); | |
768 | return; | |
769 | } | |
7a25cc73 DK |
770 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
771 | (bp->common.bc_ver & 0xff0000) >> 16, | |
772 | (bp->common.bc_ver & 0xff00) >> 8, | |
773 | (bp->common.bc_ver & 0xff)); | |
774 | ||
b44e108b GP |
775 | if (pci_channel_offline(bp->pdev)) { |
776 | BNX2X_ERR("Cannot dump MCP info while in PCI error\n"); | |
777 | return; | |
778 | } | |
779 | ||
7a25cc73 DK |
780 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); |
781 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
51c1a580 | 782 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
cdaa7cb8 | 783 | |
f2e0899f DK |
784 | if (BP_PATH(bp) == 0) |
785 | trace_shmem_base = bp->common.shmem_base; | |
786 | else | |
787 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
1a6974b2 YM |
788 | |
789 | /* sanity */ | |
790 | if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE || | |
791 | trace_shmem_base >= MCPR_SCRATCH_BASE(bp) + | |
792 | SCRATCH_BUFFER_SIZE(bp)) { | |
793 | BNX2X_ERR("Unable to dump trace buffer (mark %x)\n", | |
794 | trace_shmem_base); | |
795 | return; | |
796 | } | |
797 | ||
798 | addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE; | |
de128804 DK |
799 | |
800 | /* validate TRCB signature */ | |
801 | mark = REG_RD(bp, addr); | |
802 | if (mark != MFW_TRACE_SIGNATURE) { | |
803 | BNX2X_ERR("Trace buffer signature is missing."); | |
804 | return ; | |
805 | } | |
806 | ||
807 | /* read cyclic buffer pointer */ | |
808 | addr += 4; | |
cdaa7cb8 | 809 | mark = REG_RD(bp, addr); |
1a6974b2 YM |
810 | mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000; |
811 | if (mark >= trace_shmem_base || mark < addr + 4) { | |
812 | BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n"); | |
813 | return; | |
814 | } | |
7a25cc73 | 815 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 816 | |
7a25cc73 | 817 | printk("%s", lvl); |
2de67439 YM |
818 | |
819 | /* dump buffer after the mark */ | |
1a6974b2 | 820 | for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 821 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 822 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 823 | data[8] = 0x0; |
7995c64e | 824 | pr_cont("%s", (char *)data); |
a2fbb9ea | 825 | } |
2de67439 YM |
826 | |
827 | /* dump buffer before the mark */ | |
cdaa7cb8 | 828 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 829 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 830 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 831 | data[8] = 0x0; |
7995c64e | 832 | pr_cont("%s", (char *)data); |
a2fbb9ea | 833 | } |
7a25cc73 DK |
834 | printk("%s" "end of fw dump\n", lvl); |
835 | } | |
836 | ||
1191cb83 | 837 | static void bnx2x_fw_dump(struct bnx2x *bp) |
7a25cc73 DK |
838 | { |
839 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
840 | } |
841 | ||
823e1d90 YM |
842 | static void bnx2x_hc_int_disable(struct bnx2x *bp) |
843 | { | |
844 | int port = BP_PORT(bp); | |
845 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; | |
846 | u32 val = REG_RD(bp, addr); | |
847 | ||
848 | /* in E1 we must use only PCI configuration space to disable | |
16a5fd92 YM |
849 | * MSI/MSIX capability |
850 | * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
823e1d90 YM |
851 | */ |
852 | if (CHIP_IS_E1(bp)) { | |
853 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
854 | * Use mask register to prevent from HC sending interrupts | |
855 | * after we exit the function | |
856 | */ | |
857 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
858 | ||
859 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
860 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
861 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
862 | } else | |
863 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
864 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
865 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
866 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
867 | ||
868 | DP(NETIF_MSG_IFDOWN, | |
869 | "write %x to HC %d (addr 0x%x)\n", | |
870 | val, port, addr); | |
871 | ||
872 | /* flush all outstanding writes */ | |
873 | mmiowb(); | |
874 | ||
875 | REG_WR(bp, addr, val); | |
876 | if (REG_RD(bp, addr) != val) | |
6bf07b8e | 877 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
823e1d90 YM |
878 | } |
879 | ||
880 | static void bnx2x_igu_int_disable(struct bnx2x *bp) | |
881 | { | |
882 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
883 | ||
884 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
885 | IGU_PF_CONF_INT_LINE_EN | | |
886 | IGU_PF_CONF_ATTN_BIT_EN); | |
887 | ||
888 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); | |
889 | ||
890 | /* flush all outstanding writes */ | |
891 | mmiowb(); | |
892 | ||
893 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
894 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
6bf07b8e | 895 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
823e1d90 YM |
896 | } |
897 | ||
898 | static void bnx2x_int_disable(struct bnx2x *bp) | |
899 | { | |
900 | if (bp->common.int_block == INT_BLOCK_HC) | |
901 | bnx2x_hc_int_disable(bp); | |
902 | else | |
903 | bnx2x_igu_int_disable(bp); | |
904 | } | |
905 | ||
906 | void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) | |
a2fbb9ea ET |
907 | { |
908 | int i; | |
523224a3 DK |
909 | u16 j; |
910 | struct hc_sp_status_block_data sp_sb_data; | |
911 | int func = BP_FUNC(bp); | |
912 | #ifdef BNX2X_STOP_ON_ERROR | |
913 | u16 start = 0, end = 0; | |
6383c0b3 | 914 | u8 cos; |
523224a3 | 915 | #endif |
0155a27c | 916 | if (IS_PF(bp) && disable_int) |
823e1d90 | 917 | bnx2x_int_disable(bp); |
a2fbb9ea | 918 | |
66e855f3 | 919 | bp->stats_state = STATS_STATE_DISABLED; |
7a752993 | 920 | bp->eth_stats.unrecoverable_error++; |
66e855f3 YG |
921 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
922 | ||
a2fbb9ea ET |
923 | BNX2X_ERR("begin crash dump -----------------\n"); |
924 | ||
8440d2b6 EG |
925 | /* Indices */ |
926 | /* Common */ | |
0155a27c YM |
927 | if (IS_PF(bp)) { |
928 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
929 | int data_size, cstorm_offset; | |
930 | ||
931 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", | |
932 | bp->def_idx, bp->def_att_idx, bp->attn_state, | |
933 | bp->spq_prod_idx, bp->stats_counter); | |
934 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", | |
935 | def_sb->atten_status_block.attn_bits, | |
936 | def_sb->atten_status_block.attn_bits_ack, | |
937 | def_sb->atten_status_block.status_block_id, | |
938 | def_sb->atten_status_block.attn_bits_index); | |
939 | BNX2X_ERR(" def ("); | |
940 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
941 | pr_cont("0x%x%s", | |
942 | def_sb->sp_sb.index_values[i], | |
943 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
944 | ||
945 | data_size = sizeof(struct hc_sp_status_block_data) / | |
946 | sizeof(u32); | |
947 | cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func); | |
948 | for (i = 0; i < data_size; i++) | |
949 | *((u32 *)&sp_sb_data + i) = | |
950 | REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset + | |
951 | i * sizeof(u32)); | |
952 | ||
953 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", | |
954 | sp_sb_data.igu_sb_id, | |
955 | sp_sb_data.igu_seg_id, | |
956 | sp_sb_data.p_func.pf_id, | |
957 | sp_sb_data.p_func.vnic_id, | |
958 | sp_sb_data.p_func.vf_id, | |
959 | sp_sb_data.p_func.vf_valid, | |
960 | sp_sb_data.state); | |
961 | } | |
523224a3 | 962 | |
ec6ba945 | 963 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 964 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 965 | int loop; |
f2e0899f | 966 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
967 | struct hc_status_block_data_e1x sb_data_e1x; |
968 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
969 | CHIP_IS_E1x(bp) ? |
970 | sb_data_e1x.common.state_machine : | |
971 | sb_data_e2.common.state_machine; | |
523224a3 | 972 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
973 | CHIP_IS_E1x(bp) ? |
974 | sb_data_e1x.index_data : | |
975 | sb_data_e2.index_data; | |
6383c0b3 | 976 | u8 data_size, cos; |
523224a3 | 977 | u32 *sb_data_p; |
6383c0b3 | 978 | struct bnx2x_fp_txdata txdata; |
523224a3 | 979 | |
e2611998 YM |
980 | if (!bp->fp) |
981 | break; | |
982 | ||
983 | if (!fp->rx_cons_sb) | |
984 | continue; | |
985 | ||
523224a3 | 986 | /* Rx */ |
51c1a580 | 987 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 988 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 989 | fp->rx_comp_prod, |
66e855f3 | 990 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
51c1a580 | 991 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
8440d2b6 | 992 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 993 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 994 | |
523224a3 | 995 | /* Tx */ |
6383c0b3 AE |
996 | for_each_cos_in_tx_queue(fp, cos) |
997 | { | |
1fc3de94 | 998 | if (!fp->txdata_ptr[cos]) |
e2611998 YM |
999 | break; |
1000 | ||
65565884 | 1001 | txdata = *fp->txdata_ptr[cos]; |
e2611998 YM |
1002 | |
1003 | if (!txdata.tx_cons_sb) | |
1004 | continue; | |
1005 | ||
51c1a580 | 1006 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
6383c0b3 AE |
1007 | i, txdata.tx_pkt_prod, |
1008 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
1009 | txdata.tx_bd_cons, | |
1010 | le16_to_cpu(*txdata.tx_cons_sb)); | |
1011 | } | |
523224a3 | 1012 | |
619c5cb6 VZ |
1013 | loop = CHIP_IS_E1x(bp) ? |
1014 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
1015 | |
1016 | /* host sb data */ | |
1017 | ||
ec6ba945 VZ |
1018 | if (IS_FCOE_FP(fp)) |
1019 | continue; | |
55c11941 | 1020 | |
523224a3 DK |
1021 | BNX2X_ERR(" run indexes ("); |
1022 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
1023 | pr_cont("0x%x%s", | |
1024 | fp->sb_running_index[j], | |
1025 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
1026 | ||
1027 | BNX2X_ERR(" indexes ("); | |
1028 | for (j = 0; j < loop; j++) | |
1029 | pr_cont("0x%x%s", | |
1030 | fp->sb_index_values[j], | |
1031 | (j == loop - 1) ? ")" : " "); | |
0155a27c YM |
1032 | |
1033 | /* VF cannot access FW refelection for status block */ | |
1034 | if (IS_VF(bp)) | |
1035 | continue; | |
1036 | ||
523224a3 | 1037 | /* fw sb data */ |
619c5cb6 VZ |
1038 | data_size = CHIP_IS_E1x(bp) ? |
1039 | sizeof(struct hc_status_block_data_e1x) : | |
1040 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 1041 | data_size /= sizeof(u32); |
619c5cb6 VZ |
1042 | sb_data_p = CHIP_IS_E1x(bp) ? |
1043 | (u32 *)&sb_data_e1x : | |
1044 | (u32 *)&sb_data_e2; | |
523224a3 DK |
1045 | /* copy sb data in here */ |
1046 | for (j = 0; j < data_size; j++) | |
1047 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
1048 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
1049 | j * sizeof(u32)); | |
1050 | ||
619c5cb6 | 1051 | if (!CHIP_IS_E1x(bp)) { |
51c1a580 | 1052 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
1053 | sb_data_e2.common.p_func.pf_id, |
1054 | sb_data_e2.common.p_func.vf_id, | |
1055 | sb_data_e2.common.p_func.vf_valid, | |
1056 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
1057 | sb_data_e2.common.same_igu_sb_1b, |
1058 | sb_data_e2.common.state); | |
f2e0899f | 1059 | } else { |
51c1a580 | 1060 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
1061 | sb_data_e1x.common.p_func.pf_id, |
1062 | sb_data_e1x.common.p_func.vf_id, | |
1063 | sb_data_e1x.common.p_func.vf_valid, | |
1064 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
1065 | sb_data_e1x.common.same_igu_sb_1b, |
1066 | sb_data_e1x.common.state); | |
f2e0899f | 1067 | } |
523224a3 DK |
1068 | |
1069 | /* SB_SMs data */ | |
1070 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
51c1a580 MS |
1071 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
1072 | j, hc_sm_p[j].__flags, | |
1073 | hc_sm_p[j].igu_sb_id, | |
1074 | hc_sm_p[j].igu_seg_id, | |
1075 | hc_sm_p[j].time_to_expire, | |
1076 | hc_sm_p[j].timer_value); | |
523224a3 DK |
1077 | } |
1078 | ||
16a5fd92 | 1079 | /* Indices data */ |
523224a3 | 1080 | for (j = 0; j < loop; j++) { |
51c1a580 | 1081 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
523224a3 DK |
1082 | hc_index_p[j].flags, |
1083 | hc_index_p[j].timeout); | |
1084 | } | |
8440d2b6 | 1085 | } |
a2fbb9ea | 1086 | |
523224a3 | 1087 | #ifdef BNX2X_STOP_ON_ERROR |
0155a27c YM |
1088 | if (IS_PF(bp)) { |
1089 | /* event queue */ | |
1090 | BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); | |
1091 | for (i = 0; i < NUM_EQ_DESC; i++) { | |
1092 | u32 *data = (u32 *)&bp->eq_ring[i].message.data; | |
1093 | ||
1094 | BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n", | |
1095 | i, bp->eq_ring[i].message.opcode, | |
1096 | bp->eq_ring[i].message.error); | |
1097 | BNX2X_ERR("data: %x %x %x\n", | |
1098 | data[0], data[1], data[2]); | |
1099 | } | |
04c46736 YM |
1100 | } |
1101 | ||
8440d2b6 EG |
1102 | /* Rings */ |
1103 | /* Rx */ | |
55c11941 | 1104 | for_each_valid_rx_queue(bp, i) { |
8440d2b6 | 1105 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1106 | |
e2611998 YM |
1107 | if (!bp->fp) |
1108 | break; | |
1109 | ||
1110 | if (!fp->rx_cons_sb) | |
1111 | continue; | |
1112 | ||
a2fbb9ea ET |
1113 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); |
1114 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 1115 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
1116 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
1117 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
1118 | ||
c3eefaf6 | 1119 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
44151acb | 1120 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
a2fbb9ea ET |
1121 | } |
1122 | ||
3196a88a EG |
1123 | start = RX_SGE(fp->rx_sge_prod); |
1124 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 1125 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
1126 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
1127 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
1128 | ||
c3eefaf6 EG |
1129 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
1130 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
1131 | } |
1132 | ||
a2fbb9ea ET |
1133 | start = RCQ_BD(fp->rx_comp_cons - 10); |
1134 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 1135 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
1136 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
1137 | ||
c3eefaf6 EG |
1138 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
1139 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
1140 | } |
1141 | } | |
1142 | ||
8440d2b6 | 1143 | /* Tx */ |
55c11941 | 1144 | for_each_valid_tx_queue(bp, i) { |
8440d2b6 | 1145 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
e2611998 YM |
1146 | |
1147 | if (!bp->fp) | |
1148 | break; | |
1149 | ||
6383c0b3 | 1150 | for_each_cos_in_tx_queue(fp, cos) { |
65565884 | 1151 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
6383c0b3 | 1152 | |
1fc3de94 | 1153 | if (!fp->txdata_ptr[cos]) |
e2611998 YM |
1154 | break; |
1155 | ||
ea36475a | 1156 | if (!txdata->tx_cons_sb) |
e2611998 YM |
1157 | continue; |
1158 | ||
6383c0b3 AE |
1159 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); |
1160 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
1161 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1162 | struct sw_tx_bd *sw_bd = | |
1163 | &txdata->tx_buf_ring[j]; | |
1164 | ||
51c1a580 | 1165 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
6383c0b3 AE |
1166 | i, cos, j, sw_bd->skb, |
1167 | sw_bd->first_bd); | |
1168 | } | |
8440d2b6 | 1169 | |
6383c0b3 AE |
1170 | start = TX_BD(txdata->tx_bd_cons - 10); |
1171 | end = TX_BD(txdata->tx_bd_cons + 254); | |
1172 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1173 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 1174 | |
51c1a580 | 1175 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
6383c0b3 AE |
1176 | i, cos, j, tx_bd[0], tx_bd[1], |
1177 | tx_bd[2], tx_bd[3]); | |
1178 | } | |
8440d2b6 EG |
1179 | } |
1180 | } | |
523224a3 | 1181 | #endif |
0155a27c YM |
1182 | if (IS_PF(bp)) { |
1183 | bnx2x_fw_dump(bp); | |
1184 | bnx2x_mc_assert(bp); | |
1185 | } | |
a2fbb9ea | 1186 | BNX2X_ERR("end crash dump -----------------\n"); |
a2fbb9ea ET |
1187 | } |
1188 | ||
619c5cb6 VZ |
1189 | /* |
1190 | * FLR Support for E2 | |
1191 | * | |
1192 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
1193 | * initialization. | |
1194 | */ | |
16a5fd92 | 1195 | #define FLR_WAIT_USEC 10000 /* 10 milliseconds */ |
89db4ad8 AE |
1196 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
1197 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ | |
619c5cb6 VZ |
1198 | |
1199 | struct pbf_pN_buf_regs { | |
1200 | int pN; | |
1201 | u32 init_crd; | |
1202 | u32 crd; | |
1203 | u32 crd_freed; | |
1204 | }; | |
1205 | ||
1206 | struct pbf_pN_cmd_regs { | |
1207 | int pN; | |
1208 | u32 lines_occup; | |
1209 | u32 lines_freed; | |
1210 | }; | |
1211 | ||
1212 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
1213 | struct pbf_pN_buf_regs *regs, | |
1214 | u32 poll_count) | |
1215 | { | |
1216 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
1217 | u32 cur_cnt = poll_count; | |
1218 | ||
1219 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
1220 | crd = crd_start = REG_RD(bp, regs->crd); | |
1221 | init_crd = REG_RD(bp, regs->init_crd); | |
1222 | ||
1223 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
1224 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
1225 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
1226 | ||
1227 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
1228 | (init_crd - crd_start))) { | |
1229 | if (cur_cnt--) { | |
89db4ad8 | 1230 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1231 | crd = REG_RD(bp, regs->crd); |
1232 | crd_freed = REG_RD(bp, regs->crd_freed); | |
1233 | } else { | |
1234 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
1235 | regs->pN); | |
1236 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
1237 | regs->pN, crd); | |
1238 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
1239 | regs->pN, crd_freed); | |
1240 | break; | |
1241 | } | |
1242 | } | |
1243 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
89db4ad8 | 1244 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1245 | } |
1246 | ||
1247 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
1248 | struct pbf_pN_cmd_regs *regs, | |
1249 | u32 poll_count) | |
1250 | { | |
1251 | u32 occup, to_free, freed, freed_start; | |
1252 | u32 cur_cnt = poll_count; | |
1253 | ||
1254 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
1255 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
1256 | ||
1257 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
1258 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
1259 | ||
1260 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
1261 | if (cur_cnt--) { | |
89db4ad8 | 1262 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1263 | occup = REG_RD(bp, regs->lines_occup); |
1264 | freed = REG_RD(bp, regs->lines_freed); | |
1265 | } else { | |
1266 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
1267 | regs->pN); | |
1268 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
1269 | regs->pN, occup); | |
1270 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
1271 | regs->pN, freed); | |
1272 | break; | |
1273 | } | |
1274 | } | |
1275 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
89db4ad8 | 1276 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1277 | } |
1278 | ||
1191cb83 ED |
1279 | static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, |
1280 | u32 expected, u32 poll_count) | |
619c5cb6 VZ |
1281 | { |
1282 | u32 cur_cnt = poll_count; | |
1283 | u32 val; | |
1284 | ||
1285 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
89db4ad8 | 1286 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1287 | |
1288 | return val; | |
1289 | } | |
1290 | ||
d16132ce AE |
1291 | int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, |
1292 | char *msg, u32 poll_cnt) | |
619c5cb6 VZ |
1293 | { |
1294 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1295 | if (val != 0) { | |
1296 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1297 | return 1; | |
1298 | } | |
1299 | return 0; | |
1300 | } | |
1301 | ||
d16132ce AE |
1302 | /* Common routines with VF FLR cleanup */ |
1303 | u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
619c5cb6 VZ |
1304 | { |
1305 | /* adjust polling timeout */ | |
1306 | if (CHIP_REV_IS_EMUL(bp)) | |
1307 | return FLR_POLL_CNT * 2000; | |
1308 | ||
1309 | if (CHIP_REV_IS_FPGA(bp)) | |
1310 | return FLR_POLL_CNT * 120; | |
1311 | ||
1312 | return FLR_POLL_CNT; | |
1313 | } | |
1314 | ||
d16132ce | 1315 | void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) |
619c5cb6 VZ |
1316 | { |
1317 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1318 | {0, (CHIP_IS_E3B0(bp)) ? | |
1319 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1320 | PBF_REG_P0_TQ_OCCUPANCY, | |
1321 | (CHIP_IS_E3B0(bp)) ? | |
1322 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1323 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1324 | {1, (CHIP_IS_E3B0(bp)) ? | |
1325 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1326 | PBF_REG_P1_TQ_OCCUPANCY, | |
1327 | (CHIP_IS_E3B0(bp)) ? | |
1328 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1329 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1330 | {4, (CHIP_IS_E3B0(bp)) ? | |
1331 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1332 | PBF_REG_P4_TQ_OCCUPANCY, | |
1333 | (CHIP_IS_E3B0(bp)) ? | |
1334 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1335 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1336 | }; | |
1337 | ||
1338 | struct pbf_pN_buf_regs buf_regs[] = { | |
1339 | {0, (CHIP_IS_E3B0(bp)) ? | |
1340 | PBF_REG_INIT_CRD_Q0 : | |
1341 | PBF_REG_P0_INIT_CRD , | |
1342 | (CHIP_IS_E3B0(bp)) ? | |
1343 | PBF_REG_CREDIT_Q0 : | |
1344 | PBF_REG_P0_CREDIT, | |
1345 | (CHIP_IS_E3B0(bp)) ? | |
1346 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1347 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1348 | {1, (CHIP_IS_E3B0(bp)) ? | |
1349 | PBF_REG_INIT_CRD_Q1 : | |
1350 | PBF_REG_P1_INIT_CRD, | |
1351 | (CHIP_IS_E3B0(bp)) ? | |
1352 | PBF_REG_CREDIT_Q1 : | |
1353 | PBF_REG_P1_CREDIT, | |
1354 | (CHIP_IS_E3B0(bp)) ? | |
1355 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1356 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1357 | {4, (CHIP_IS_E3B0(bp)) ? | |
1358 | PBF_REG_INIT_CRD_LB_Q : | |
1359 | PBF_REG_P4_INIT_CRD, | |
1360 | (CHIP_IS_E3B0(bp)) ? | |
1361 | PBF_REG_CREDIT_LB_Q : | |
1362 | PBF_REG_P4_CREDIT, | |
1363 | (CHIP_IS_E3B0(bp)) ? | |
1364 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1365 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1366 | }; | |
1367 | ||
1368 | int i; | |
1369 | ||
1370 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1371 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1372 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1373 | ||
619c5cb6 VZ |
1374 | /* Verify the transmission buffers are flushed P0, P1, P4 */ |
1375 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1376 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1377 | } | |
1378 | ||
1379 | #define OP_GEN_PARAM(param) \ | |
1380 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1381 | ||
1382 | #define OP_GEN_TYPE(type) \ | |
1383 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1384 | ||
1385 | #define OP_GEN_AGG_VECT(index) \ | |
1386 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1387 | ||
d16132ce | 1388 | int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) |
619c5cb6 | 1389 | { |
86564c3f | 1390 | u32 op_gen_command = 0; |
619c5cb6 VZ |
1391 | u32 comp_addr = BAR_CSTRORM_INTMEM + |
1392 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1393 | int ret = 0; | |
1394 | ||
1395 | if (REG_RD(bp, comp_addr)) { | |
89db4ad8 | 1396 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
619c5cb6 VZ |
1397 | return 1; |
1398 | } | |
1399 | ||
86564c3f YM |
1400 | op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); |
1401 | op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1402 | op_gen_command |= OP_GEN_AGG_VECT(clnup_func); | |
1403 | op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
619c5cb6 | 1404 | |
89db4ad8 | 1405 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
86564c3f | 1406 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); |
619c5cb6 VZ |
1407 | |
1408 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1409 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
51c1a580 MS |
1410 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
1411 | (REG_RD(bp, comp_addr))); | |
d16132ce AE |
1412 | bnx2x_panic(); |
1413 | return 1; | |
619c5cb6 | 1414 | } |
16a5fd92 | 1415 | /* Zero completion for next FLR */ |
619c5cb6 VZ |
1416 | REG_WR(bp, comp_addr, 0); |
1417 | ||
1418 | return ret; | |
1419 | } | |
1420 | ||
b56e9670 | 1421 | u8 bnx2x_is_pcie_pending(struct pci_dev *dev) |
619c5cb6 | 1422 | { |
619c5cb6 VZ |
1423 | u16 status; |
1424 | ||
2a80eebc | 1425 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
619c5cb6 VZ |
1426 | return status & PCI_EXP_DEVSTA_TRPND; |
1427 | } | |
1428 | ||
1429 | /* PF FLR specific routines | |
1430 | */ | |
1431 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1432 | { | |
619c5cb6 VZ |
1433 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ |
1434 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1435 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1436 | "CFC PF usage counter timed out", | |
1437 | poll_cnt)) | |
1438 | return 1; | |
1439 | ||
619c5cb6 VZ |
1440 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ |
1441 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1442 | DORQ_REG_PF_USAGE_CNT, | |
1443 | "DQ PF usage counter timed out", | |
1444 | poll_cnt)) | |
1445 | return 1; | |
1446 | ||
1447 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1448 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1449 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1450 | "QM PF usage counter timed out", | |
1451 | poll_cnt)) | |
1452 | return 1; | |
1453 | ||
1454 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1455 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1456 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1457 | "Timers VNIC usage counter timed out", | |
1458 | poll_cnt)) | |
1459 | return 1; | |
1460 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1461 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1462 | "Timers NUM_SCANS usage counter timed out", | |
1463 | poll_cnt)) | |
1464 | return 1; | |
1465 | ||
1466 | /* Wait DMAE PF usage counter to zero */ | |
1467 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1468 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
6bf07b8e | 1469 | "DMAE command register timed out", |
619c5cb6 VZ |
1470 | poll_cnt)) |
1471 | return 1; | |
1472 | ||
1473 | return 0; | |
1474 | } | |
1475 | ||
1476 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1477 | { | |
1478 | u32 val; | |
1479 | ||
1480 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1481 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1482 | ||
1483 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1484 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1485 | ||
1486 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1487 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1488 | ||
1489 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1490 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1491 | ||
1492 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1493 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1494 | ||
1495 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1496 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1497 | ||
1498 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1499 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1500 | ||
1501 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1502 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1503 | val); | |
1504 | } | |
1505 | ||
1506 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1507 | { | |
1508 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1509 | ||
1510 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1511 | ||
1512 | /* Re-enable PF target read access */ | |
1513 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1514 | ||
1515 | /* Poll HW usage counters */ | |
89db4ad8 | 1516 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
619c5cb6 VZ |
1517 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
1518 | return -EBUSY; | |
1519 | ||
1520 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1521 | ||
1522 | /* Send the FW cleanup command */ | |
1523 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1524 | return -EBUSY; | |
1525 | ||
1526 | /* ATC cleanup */ | |
1527 | ||
1528 | /* Verify TX hw is flushed */ | |
1529 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1530 | ||
1531 | /* Wait 100ms (not adjusted according to platform) */ | |
1532 | msleep(100); | |
1533 | ||
1534 | /* Verify no pending pci transactions */ | |
1535 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1536 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1537 | ||
1538 | /* Debug */ | |
1539 | bnx2x_hw_enable_status(bp); | |
1540 | ||
1541 | /* | |
1542 | * Master enable - Due to WB DMAE writes performed before this | |
1543 | * register is re-initialized as part of the regular function init | |
1544 | */ | |
1545 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1546 | ||
1547 | return 0; | |
1548 | } | |
1549 | ||
f2e0899f | 1550 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1551 | { |
34f80b04 | 1552 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1553 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1554 | u32 val = REG_RD(bp, addr); | |
69c326b3 DK |
1555 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1556 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1557 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
a2fbb9ea ET |
1558 | |
1559 | if (msix) { | |
8badd27a EG |
1560 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1561 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1562 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1563 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
69c326b3 DK |
1564 | if (single_msix) |
1565 | val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; | |
8badd27a EG |
1566 | } else if (msi) { |
1567 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1568 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1569 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1570 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1571 | } else { |
1572 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1573 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1574 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1575 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1576 | |
a0fd065c | 1577 | if (!CHIP_IS_E1(bp)) { |
51c1a580 MS |
1578 | DP(NETIF_MSG_IFUP, |
1579 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); | |
615f8fd9 | 1580 | |
a0fd065c | 1581 | REG_WR(bp, addr, val); |
615f8fd9 | 1582 | |
a0fd065c DK |
1583 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1584 | } | |
a2fbb9ea ET |
1585 | } |
1586 | ||
a0fd065c DK |
1587 | if (CHIP_IS_E1(bp)) |
1588 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1589 | ||
51c1a580 MS |
1590 | DP(NETIF_MSG_IFUP, |
1591 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, | |
1592 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1593 | |
1594 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1595 | /* |
1596 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1597 | */ | |
1598 | mmiowb(); | |
1599 | barrier(); | |
34f80b04 | 1600 | |
f2e0899f | 1601 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1602 | /* init leading/trailing edge */ |
fb3bff17 | 1603 | if (IS_MF(bp)) { |
3395a033 | 1604 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1605 | if (bp->port.pmf) |
4acac6a5 EG |
1606 | /* enable nig and gpio3 attention */ |
1607 | val |= 0x1100; | |
34f80b04 EG |
1608 | } else |
1609 | val = 0xffff; | |
1610 | ||
1611 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1612 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1613 | } | |
37dbbf32 EG |
1614 | |
1615 | /* Make sure that interrupts are indeed enabled from here on */ | |
1616 | mmiowb(); | |
a2fbb9ea ET |
1617 | } |
1618 | ||
f2e0899f DK |
1619 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1620 | { | |
1621 | u32 val; | |
30a5de77 DK |
1622 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1623 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1624 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
f2e0899f DK |
1625 | |
1626 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1627 | ||
1628 | if (msix) { | |
1629 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1630 | IGU_PF_CONF_SINGLE_ISR_EN); | |
ebe61d80 | 1631 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
f2e0899f | 1632 | IGU_PF_CONF_ATTN_BIT_EN); |
30a5de77 DK |
1633 | |
1634 | if (single_msix) | |
1635 | val |= IGU_PF_CONF_SINGLE_ISR_EN; | |
f2e0899f DK |
1636 | } else if (msi) { |
1637 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
ebe61d80 | 1638 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
f2e0899f DK |
1639 | IGU_PF_CONF_ATTN_BIT_EN | |
1640 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1641 | } else { | |
1642 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
ebe61d80 | 1643 | val |= (IGU_PF_CONF_INT_LINE_EN | |
f2e0899f DK |
1644 | IGU_PF_CONF_ATTN_BIT_EN | |
1645 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1646 | } | |
1647 | ||
ebe61d80 YM |
1648 | /* Clean previous status - need to configure igu prior to ack*/ |
1649 | if ((!msix) || single_msix) { | |
1650 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1651 | bnx2x_ack_int(bp); | |
1652 | } | |
1653 | ||
1654 | val |= IGU_PF_CONF_FUNC_EN; | |
1655 | ||
51c1a580 | 1656 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
f2e0899f DK |
1657 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
1658 | ||
1659 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1660 | ||
79a8557a YM |
1661 | if (val & IGU_PF_CONF_INT_LINE_EN) |
1662 | pci_intx(bp->pdev, true); | |
1663 | ||
f2e0899f DK |
1664 | barrier(); |
1665 | ||
1666 | /* init leading/trailing edge */ | |
1667 | if (IS_MF(bp)) { | |
3395a033 | 1668 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1669 | if (bp->port.pmf) |
1670 | /* enable nig and gpio3 attention */ | |
1671 | val |= 0x1100; | |
1672 | } else | |
1673 | val = 0xffff; | |
1674 | ||
1675 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1676 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1677 | ||
1678 | /* Make sure that interrupts are indeed enabled from here on */ | |
1679 | mmiowb(); | |
1680 | } | |
1681 | ||
1682 | void bnx2x_int_enable(struct bnx2x *bp) | |
1683 | { | |
1684 | if (bp->common.int_block == INT_BLOCK_HC) | |
1685 | bnx2x_hc_int_enable(bp); | |
1686 | else | |
1687 | bnx2x_igu_int_enable(bp); | |
1688 | } | |
1689 | ||
9f6c9258 | 1690 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1691 | { |
a2fbb9ea | 1692 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1693 | int i, offset; |
a2fbb9ea | 1694 | |
f8ef6e44 YG |
1695 | if (disable_hw) |
1696 | /* prevent the HW from sending interrupts */ | |
1697 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1698 | |
1699 | /* make sure all ISRs are done */ | |
1700 | if (msix) { | |
8badd27a EG |
1701 | synchronize_irq(bp->msix_table[0].vector); |
1702 | offset = 1; | |
55c11941 MS |
1703 | if (CNIC_SUPPORT(bp)) |
1704 | offset++; | |
ec6ba945 | 1705 | for_each_eth_queue(bp, i) |
754a2f52 | 1706 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1707 | } else |
1708 | synchronize_irq(bp->pdev->irq); | |
1709 | ||
1710 | /* make sure sp_task is not running */ | |
1cf167f2 | 1711 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1712 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1713 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1714 | } |
1715 | ||
34f80b04 | 1716 | /* fast path */ |
a2fbb9ea ET |
1717 | |
1718 | /* | |
34f80b04 | 1719 | * General service functions |
a2fbb9ea ET |
1720 | */ |
1721 | ||
72fd0718 VZ |
1722 | /* Return true if succeeded to acquire the lock */ |
1723 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1724 | { | |
1725 | u32 lock_status; | |
1726 | u32 resource_bit = (1 << resource); | |
1727 | int func = BP_FUNC(bp); | |
1728 | u32 hw_lock_control_reg; | |
1729 | ||
51c1a580 MS |
1730 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1731 | "Trying to take a lock on resource %d\n", resource); | |
72fd0718 VZ |
1732 | |
1733 | /* Validating that the resource is within range */ | |
1734 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1735 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
72fd0718 VZ |
1736 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
1737 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1738 | return false; |
72fd0718 VZ |
1739 | } |
1740 | ||
1741 | if (func <= 5) | |
1742 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1743 | else | |
1744 | hw_lock_control_reg = | |
1745 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1746 | ||
1747 | /* Try to acquire the lock */ | |
1748 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1749 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1750 | if (lock_status & resource_bit) | |
1751 | return true; | |
1752 | ||
51c1a580 MS |
1753 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1754 | "Failed to get a lock on resource %d\n", resource); | |
72fd0718 VZ |
1755 | return false; |
1756 | } | |
1757 | ||
c9ee9206 VZ |
1758 | /** |
1759 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1760 | * | |
1761 | * @bp: driver handle | |
1762 | * | |
1763 | * Returns the recovery leader resource id according to the engine this function | |
1764 | * belongs to. Currently only only 2 engines is supported. | |
1765 | */ | |
1191cb83 | 1766 | static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) |
c9ee9206 VZ |
1767 | { |
1768 | if (BP_PATH(bp)) | |
1769 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1770 | else | |
1771 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1772 | } | |
1773 | ||
1774 | /** | |
2de67439 | 1775 | * bnx2x_trylock_leader_lock- try to acquire a leader lock. |
c9ee9206 VZ |
1776 | * |
1777 | * @bp: driver handle | |
1778 | * | |
2de67439 | 1779 | * Tries to acquire a leader lock for current engine. |
c9ee9206 | 1780 | */ |
1191cb83 | 1781 | static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) |
c9ee9206 VZ |
1782 | { |
1783 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1784 | } | |
1785 | ||
619c5cb6 | 1786 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
55c11941 | 1787 | |
fd1fc79d AE |
1788 | /* schedule the sp task and mark that interrupt occurred (runs from ISR) */ |
1789 | static int bnx2x_schedule_sp_task(struct bnx2x *bp) | |
1790 | { | |
1791 | /* Set the interrupt occurred bit for the sp-task to recognize it | |
1792 | * must ack the interrupt and transition according to the IGU | |
1793 | * state machine. | |
1794 | */ | |
1795 | atomic_set(&bp->interrupt_occurred, 1); | |
1796 | ||
1797 | /* The sp_task must execute only after this bit | |
1798 | * is set, otherwise we will get out of sync and miss all | |
1799 | * further interrupts. Hence, the barrier. | |
1800 | */ | |
1801 | smp_wmb(); | |
1802 | ||
1803 | /* schedule sp_task to workqueue */ | |
1804 | return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); | |
1805 | } | |
3196a88a | 1806 | |
619c5cb6 | 1807 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1808 | { |
1809 | struct bnx2x *bp = fp->bp; | |
1810 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1811 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 | 1812 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
15192a8c | 1813 | struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a2fbb9ea | 1814 | |
34f80b04 | 1815 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1816 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1817 | fp->index, cid, command, bp->state, |
34f80b04 | 1818 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1819 | |
fd1fc79d AE |
1820 | /* If cid is within VF range, replace the slowpath object with the |
1821 | * one corresponding to this VF | |
1822 | */ | |
1823 | if (cid >= BNX2X_FIRST_VF_CID && | |
1824 | cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) | |
1825 | bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); | |
1826 | ||
619c5cb6 VZ |
1827 | switch (command) { |
1828 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1829 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1830 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1831 | break; | |
d6cae238 | 1832 | |
619c5cb6 | 1833 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1834 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1835 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1836 | break; |
1837 | ||
6383c0b3 | 1838 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
51c1a580 | 1839 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
6383c0b3 AE |
1840 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
1841 | break; | |
1842 | ||
619c5cb6 | 1843 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1844 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1845 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1846 | break; |
1847 | ||
619c5cb6 | 1848 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
6bf07b8e | 1849 | DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid); |
619c5cb6 | 1850 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1851 | break; |
1852 | ||
619c5cb6 | 1853 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1854 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1855 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1856 | break; |
619c5cb6 | 1857 | |
14a94ebd MK |
1858 | case (RAMROD_CMD_ID_ETH_TPA_UPDATE): |
1859 | DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid); | |
1860 | drv_cmd = BNX2X_Q_CMD_UPDATE_TPA; | |
1861 | break; | |
1862 | ||
619c5cb6 VZ |
1863 | default: |
1864 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1865 | command, fp->index); | |
1866 | return; | |
523224a3 | 1867 | } |
3196a88a | 1868 | |
619c5cb6 VZ |
1869 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1870 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1871 | /* q_obj->complete_cmd() failure means that this was | |
1872 | * an unexpected completion. | |
1873 | * | |
1874 | * In this case we don't want to increase the bp->spq_left | |
1875 | * because apparently we haven't sent this command the first | |
1876 | * place. | |
1877 | */ | |
1878 | #ifdef BNX2X_STOP_ON_ERROR | |
1879 | bnx2x_panic(); | |
1880 | #else | |
1881 | return; | |
1882 | #endif | |
1883 | ||
4e857c58 | 1884 | smp_mb__before_atomic(); |
6e30dd4e | 1885 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 | 1886 | /* push the change in bp->spq_left and towards the memory */ |
4e857c58 | 1887 | smp_mb__after_atomic(); |
49d66772 | 1888 | |
d6cae238 VZ |
1889 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1890 | ||
a3348722 BW |
1891 | if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && |
1892 | (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { | |
1893 | /* if Q update ramrod is completed for last Q in AFEX vif set | |
1894 | * flow, then ACK MCP at the end | |
1895 | * | |
1896 | * mark pending ACK to MCP bit. | |
1897 | * prevent case that both bits are cleared. | |
1898 | * At the end of load/unload driver checks that | |
2de67439 | 1899 | * sp_state is cleared, and this order prevents |
a3348722 BW |
1900 | * races |
1901 | */ | |
4e857c58 | 1902 | smp_mb__before_atomic(); |
a3348722 BW |
1903 | set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); |
1904 | wmb(); | |
1905 | clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
4e857c58 | 1906 | smp_mb__after_atomic(); |
a3348722 | 1907 | |
fd1fc79d AE |
1908 | /* schedule the sp task as mcp ack is required */ |
1909 | bnx2x_schedule_sp_task(bp); | |
a3348722 BW |
1910 | } |
1911 | ||
523224a3 | 1912 | return; |
a2fbb9ea ET |
1913 | } |
1914 | ||
9f6c9258 | 1915 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1916 | { |
555f6c78 | 1917 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1918 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1919 | u16 mask; |
ca00392c | 1920 | int i; |
6383c0b3 | 1921 | u8 cos; |
a2fbb9ea | 1922 | |
34f80b04 | 1923 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1924 | if (unlikely(status == 0)) { |
1925 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1926 | return IRQ_NONE; | |
1927 | } | |
f5372251 | 1928 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1929 | |
3196a88a EG |
1930 | #ifdef BNX2X_STOP_ON_ERROR |
1931 | if (unlikely(bp->panic)) | |
1932 | return IRQ_HANDLED; | |
1933 | #endif | |
1934 | ||
ec6ba945 | 1935 | for_each_eth_queue(bp, i) { |
ca00392c | 1936 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1937 | |
55c11941 | 1938 | mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); |
ca00392c | 1939 | if (status & mask) { |
619c5cb6 | 1940 | /* Handle Rx or Tx according to SB id */ |
6383c0b3 | 1941 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 1942 | prefetch(fp->txdata_ptr[cos]->tx_cons_sb); |
523224a3 | 1943 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
f5fbf115 | 1944 | napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1945 | status &= ~mask; |
1946 | } | |
a2fbb9ea ET |
1947 | } |
1948 | ||
55c11941 MS |
1949 | if (CNIC_SUPPORT(bp)) { |
1950 | mask = 0x2; | |
1951 | if (status & (mask | 0x1)) { | |
1952 | struct cnic_ops *c_ops = NULL; | |
993ac7b5 | 1953 | |
ad9b4359 MC |
1954 | rcu_read_lock(); |
1955 | c_ops = rcu_dereference(bp->cnic_ops); | |
1956 | if (c_ops && (bp->cnic_eth_dev.drv_state & | |
1957 | CNIC_DRV_STATE_HANDLES_IRQ)) | |
1958 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1959 | rcu_read_unlock(); | |
993ac7b5 | 1960 | |
55c11941 MS |
1961 | status &= ~mask; |
1962 | } | |
993ac7b5 | 1963 | } |
a2fbb9ea | 1964 | |
34f80b04 | 1965 | if (unlikely(status & 0x1)) { |
fd1fc79d AE |
1966 | |
1967 | /* schedule sp task to perform default status block work, ack | |
1968 | * attentions and enable interrupts. | |
1969 | */ | |
1970 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
1971 | |
1972 | status &= ~0x1; | |
1973 | if (!status) | |
1974 | return IRQ_HANDLED; | |
1975 | } | |
1976 | ||
cdaa7cb8 VZ |
1977 | if (unlikely(status)) |
1978 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1979 | status); |
a2fbb9ea | 1980 | |
c18487ee | 1981 | return IRQ_HANDLED; |
a2fbb9ea ET |
1982 | } |
1983 | ||
c18487ee YR |
1984 | /* Link */ |
1985 | ||
1986 | /* | |
1987 | * General service functions | |
1988 | */ | |
a2fbb9ea | 1989 | |
9f6c9258 | 1990 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1991 | { |
1992 | u32 lock_status; | |
1993 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1994 | int func = BP_FUNC(bp); |
1995 | u32 hw_lock_control_reg; | |
c18487ee | 1996 | int cnt; |
a2fbb9ea | 1997 | |
c18487ee YR |
1998 | /* Validating that the resource is within range */ |
1999 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 2000 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
2001 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
2002 | return -EINVAL; | |
2003 | } | |
a2fbb9ea | 2004 | |
4a37fb66 YG |
2005 | if (func <= 5) { |
2006 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
2007 | } else { | |
2008 | hw_lock_control_reg = | |
2009 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
2010 | } | |
2011 | ||
c18487ee | 2012 | /* Validating that the resource is not already taken */ |
4a37fb66 | 2013 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 2014 | if (lock_status & resource_bit) { |
51c1a580 | 2015 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
c18487ee YR |
2016 | lock_status, resource_bit); |
2017 | return -EEXIST; | |
2018 | } | |
a2fbb9ea | 2019 | |
46230476 EG |
2020 | /* Try for 5 second every 5ms */ |
2021 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 2022 | /* Try to acquire the lock */ |
4a37fb66 YG |
2023 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
2024 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
2025 | if (lock_status & resource_bit) |
2026 | return 0; | |
a2fbb9ea | 2027 | |
639d65b8 | 2028 | usleep_range(5000, 10000); |
a2fbb9ea | 2029 | } |
51c1a580 | 2030 | BNX2X_ERR("Timeout\n"); |
c18487ee YR |
2031 | return -EAGAIN; |
2032 | } | |
a2fbb9ea | 2033 | |
c9ee9206 VZ |
2034 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
2035 | { | |
2036 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
2037 | } | |
2038 | ||
9f6c9258 | 2039 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
2040 | { |
2041 | u32 lock_status; | |
2042 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
2043 | int func = BP_FUNC(bp); |
2044 | u32 hw_lock_control_reg; | |
a2fbb9ea | 2045 | |
c18487ee YR |
2046 | /* Validating that the resource is within range */ |
2047 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 2048 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
2049 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
2050 | return -EINVAL; | |
2051 | } | |
2052 | ||
4a37fb66 YG |
2053 | if (func <= 5) { |
2054 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
2055 | } else { | |
2056 | hw_lock_control_reg = | |
2057 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
2058 | } | |
2059 | ||
c18487ee | 2060 | /* Validating that the resource is currently taken */ |
4a37fb66 | 2061 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 2062 | if (!(lock_status & resource_bit)) { |
6bf07b8e YM |
2063 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n", |
2064 | lock_status, resource_bit); | |
c18487ee | 2065 | return -EFAULT; |
a2fbb9ea ET |
2066 | } |
2067 | ||
9f6c9258 DK |
2068 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
2069 | return 0; | |
c18487ee | 2070 | } |
a2fbb9ea | 2071 | |
4acac6a5 EG |
2072 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
2073 | { | |
2074 | /* The GPIO should be swapped if swap register is set and active */ | |
2075 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2076 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2077 | int gpio_shift = gpio_num + | |
2078 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2079 | u32 gpio_mask = (1 << gpio_shift); | |
2080 | u32 gpio_reg; | |
2081 | int value; | |
2082 | ||
2083 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2084 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2085 | return -EINVAL; | |
2086 | } | |
2087 | ||
2088 | /* read GPIO value */ | |
2089 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2090 | ||
2091 | /* get the requested pin value */ | |
2092 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
2093 | value = 1; | |
2094 | else | |
2095 | value = 0; | |
2096 | ||
4acac6a5 EG |
2097 | return value; |
2098 | } | |
2099 | ||
17de50b7 | 2100 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
2101 | { |
2102 | /* The GPIO should be swapped if swap register is set and active */ | |
2103 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 2104 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
2105 | int gpio_shift = gpio_num + |
2106 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2107 | u32 gpio_mask = (1 << gpio_shift); | |
2108 | u32 gpio_reg; | |
a2fbb9ea | 2109 | |
c18487ee YR |
2110 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
2111 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2112 | return -EINVAL; | |
2113 | } | |
a2fbb9ea | 2114 | |
4a37fb66 | 2115 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
2116 | /* read GPIO and mask except the float bits */ |
2117 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 2118 | |
c18487ee YR |
2119 | switch (mode) { |
2120 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
51c1a580 MS |
2121 | DP(NETIF_MSG_LINK, |
2122 | "Set GPIO %d (shift %d) -> output low\n", | |
c18487ee YR |
2123 | gpio_num, gpio_shift); |
2124 | /* clear FLOAT and set CLR */ | |
2125 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2126 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
2127 | break; | |
a2fbb9ea | 2128 | |
c18487ee | 2129 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
51c1a580 MS |
2130 | DP(NETIF_MSG_LINK, |
2131 | "Set GPIO %d (shift %d) -> output high\n", | |
c18487ee YR |
2132 | gpio_num, gpio_shift); |
2133 | /* clear FLOAT and set SET */ | |
2134 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2135 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
2136 | break; | |
a2fbb9ea | 2137 | |
17de50b7 | 2138 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
51c1a580 MS |
2139 | DP(NETIF_MSG_LINK, |
2140 | "Set GPIO %d (shift %d) -> input\n", | |
c18487ee YR |
2141 | gpio_num, gpio_shift); |
2142 | /* set FLOAT */ | |
2143 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2144 | break; | |
a2fbb9ea | 2145 | |
c18487ee YR |
2146 | default: |
2147 | break; | |
a2fbb9ea ET |
2148 | } |
2149 | ||
c18487ee | 2150 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 2151 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 2152 | |
c18487ee | 2153 | return 0; |
a2fbb9ea ET |
2154 | } |
2155 | ||
0d40f0d4 YR |
2156 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
2157 | { | |
2158 | u32 gpio_reg = 0; | |
2159 | int rc = 0; | |
2160 | ||
2161 | /* Any port swapping should be handled by caller. */ | |
2162 | ||
2163 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2164 | /* read GPIO and mask except the float bits */ | |
2165 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2166 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2167 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2168 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
2169 | ||
2170 | switch (mode) { | |
2171 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
2172 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
2173 | /* set CLR */ | |
2174 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2175 | break; | |
2176 | ||
2177 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
2178 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
2179 | /* set SET */ | |
2180 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
2181 | break; | |
2182 | ||
2183 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
2184 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
2185 | /* set FLOAT */ | |
2186 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2187 | break; | |
2188 | ||
2189 | default: | |
2190 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
2191 | rc = -EINVAL; | |
2192 | break; | |
2193 | } | |
2194 | ||
2195 | if (rc == 0) | |
2196 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
2197 | ||
2198 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2199 | ||
2200 | return rc; | |
2201 | } | |
2202 | ||
4acac6a5 EG |
2203 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
2204 | { | |
2205 | /* The GPIO should be swapped if swap register is set and active */ | |
2206 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2207 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2208 | int gpio_shift = gpio_num + | |
2209 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2210 | u32 gpio_mask = (1 << gpio_shift); | |
2211 | u32 gpio_reg; | |
2212 | ||
2213 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2214 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2215 | return -EINVAL; | |
2216 | } | |
2217 | ||
2218 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2219 | /* read GPIO int */ | |
2220 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
2221 | ||
2222 | switch (mode) { | |
2223 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
51c1a580 MS |
2224 | DP(NETIF_MSG_LINK, |
2225 | "Clear GPIO INT %d (shift %d) -> output low\n", | |
2226 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2227 | /* clear SET and set CLR */ |
2228 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2229 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2230 | break; | |
2231 | ||
2232 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
51c1a580 MS |
2233 | DP(NETIF_MSG_LINK, |
2234 | "Set GPIO INT %d (shift %d) -> output high\n", | |
2235 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2236 | /* clear CLR and set SET */ |
2237 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2238 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2239 | break; | |
2240 | ||
2241 | default: | |
2242 | break; | |
2243 | } | |
2244 | ||
2245 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2246 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2247 | ||
2248 | return 0; | |
2249 | } | |
2250 | ||
d6d99a3f | 2251 | static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) |
a2fbb9ea | 2252 | { |
c18487ee | 2253 | u32 spio_reg; |
a2fbb9ea | 2254 | |
d6d99a3f YM |
2255 | /* Only 2 SPIOs are configurable */ |
2256 | if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { | |
2257 | BNX2X_ERR("Invalid SPIO 0x%x\n", spio); | |
c18487ee | 2258 | return -EINVAL; |
a2fbb9ea ET |
2259 | } |
2260 | ||
4a37fb66 | 2261 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2262 | /* read SPIO and mask except the float bits */ |
d6d99a3f | 2263 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); |
a2fbb9ea | 2264 | |
c18487ee | 2265 | switch (mode) { |
d6d99a3f YM |
2266 | case MISC_SPIO_OUTPUT_LOW: |
2267 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); | |
c18487ee | 2268 | /* clear FLOAT and set CLR */ |
d6d99a3f YM |
2269 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2270 | spio_reg |= (spio << MISC_SPIO_CLR_POS); | |
c18487ee | 2271 | break; |
a2fbb9ea | 2272 | |
d6d99a3f YM |
2273 | case MISC_SPIO_OUTPUT_HIGH: |
2274 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); | |
c18487ee | 2275 | /* clear FLOAT and set SET */ |
d6d99a3f YM |
2276 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2277 | spio_reg |= (spio << MISC_SPIO_SET_POS); | |
c18487ee | 2278 | break; |
a2fbb9ea | 2279 | |
d6d99a3f YM |
2280 | case MISC_SPIO_INPUT_HI_Z: |
2281 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); | |
c18487ee | 2282 | /* set FLOAT */ |
d6d99a3f | 2283 | spio_reg |= (spio << MISC_SPIO_FLOAT_POS); |
c18487ee | 2284 | break; |
a2fbb9ea | 2285 | |
c18487ee YR |
2286 | default: |
2287 | break; | |
a2fbb9ea ET |
2288 | } |
2289 | ||
c18487ee | 2290 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2291 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2292 | |
a2fbb9ea ET |
2293 | return 0; |
2294 | } | |
2295 | ||
9f6c9258 | 2296 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2297 | { |
a22f0788 | 2298 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
1359d73c YM |
2299 | |
2300 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | | |
2301 | ADVERTISED_Pause); | |
ad33ea3a EG |
2302 | switch (bp->link_vars.ieee_fc & |
2303 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2304 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2305 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2306 | ADVERTISED_Pause); |
c18487ee | 2307 | break; |
356e2385 | 2308 | |
c18487ee | 2309 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2310 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2311 | break; |
356e2385 | 2312 | |
c18487ee | 2313 | default: |
c18487ee YR |
2314 | break; |
2315 | } | |
2316 | } | |
f1410647 | 2317 | |
cd1dfce2 | 2318 | static void bnx2x_set_requested_fc(struct bnx2x *bp) |
c18487ee | 2319 | { |
cd1dfce2 YM |
2320 | /* Initialize link parameters structure variables |
2321 | * It is recommended to turn off RX FC for jumbo frames | |
2322 | * for better performance | |
2323 | */ | |
2324 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
2325 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; | |
2326 | else | |
2327 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; | |
2328 | } | |
a2fbb9ea | 2329 | |
9156b30b DK |
2330 | static void bnx2x_init_dropless_fc(struct bnx2x *bp) |
2331 | { | |
2332 | u32 pause_enabled = 0; | |
2333 | ||
2334 | if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { | |
2335 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2336 | pause_enabled = 1; | |
2337 | ||
2338 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
2339 | USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), | |
2340 | pause_enabled); | |
2341 | } | |
2342 | ||
2343 | DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n", | |
2344 | pause_enabled ? "enabled" : "disabled"); | |
2345 | } | |
2346 | ||
cd1dfce2 YM |
2347 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
2348 | { | |
2349 | int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); | |
2350 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
2351 | ||
2352 | if (!BP_NOMCP(bp)) { | |
2353 | bnx2x_set_requested_fc(bp); | |
4a37fb66 | 2354 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2355 | |
a22f0788 | 2356 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2357 | struct link_params *lp = &bp->link_params; |
2358 | lp->loopback_mode = LOOPBACK_XGXS; | |
2f43b821 YM |
2359 | /* Prefer doing PHY loopback at highest speed */ |
2360 | if (lp->req_line_speed[cfx_idx] < SPEED_20000) { | |
1cb0c788 | 2361 | if (lp->speed_cap_mask[cfx_idx] & |
2f43b821 | 2362 | PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) |
1cb0c788 | 2363 | lp->req_line_speed[cfx_idx] = |
2f43b821 YM |
2364 | SPEED_20000; |
2365 | else if (lp->speed_cap_mask[cfx_idx] & | |
2366 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2367 | lp->req_line_speed[cfx_idx] = | |
2368 | SPEED_10000; | |
1cb0c788 YR |
2369 | else |
2370 | lp->req_line_speed[cfx_idx] = | |
2371 | SPEED_1000; | |
2372 | } | |
a22f0788 | 2373 | } |
b5bf9068 | 2374 | |
8970b2e4 MS |
2375 | if (load_mode == LOAD_LOOPBACK_EXT) { |
2376 | struct link_params *lp = &bp->link_params; | |
2377 | lp->loopback_mode = LOOPBACK_EXT; | |
2378 | } | |
2379 | ||
19680c48 | 2380 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2381 | |
4a37fb66 | 2382 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2383 | |
9156b30b DK |
2384 | bnx2x_init_dropless_fc(bp); |
2385 | ||
3c96c68b EG |
2386 | bnx2x_calc_fc_adv(bp); |
2387 | ||
cd1dfce2 | 2388 | if (bp->link_vars.link_up) { |
b5bf9068 | 2389 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
19680c48 | 2390 | bnx2x_link_report(bp); |
cd1dfce2 YM |
2391 | } |
2392 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2393 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2394 | return rc; |
2395 | } | |
f5372251 | 2396 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2397 | return -EINVAL; |
a2fbb9ea ET |
2398 | } |
2399 | ||
9f6c9258 | 2400 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2401 | { |
19680c48 | 2402 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2403 | bnx2x_acquire_phy_lock(bp); |
19680c48 | 2404 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2405 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2406 | |
9156b30b DK |
2407 | bnx2x_init_dropless_fc(bp); |
2408 | ||
19680c48 EG |
2409 | bnx2x_calc_fc_adv(bp); |
2410 | } else | |
f5372251 | 2411 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2412 | } |
a2fbb9ea | 2413 | |
c18487ee YR |
2414 | static void bnx2x__link_reset(struct bnx2x *bp) |
2415 | { | |
19680c48 | 2416 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2417 | bnx2x_acquire_phy_lock(bp); |
5d07d868 | 2418 | bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2419 | bnx2x_release_phy_lock(bp); |
19680c48 | 2420 | } else |
f5372251 | 2421 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2422 | } |
a2fbb9ea | 2423 | |
5d07d868 YM |
2424 | void bnx2x_force_link_reset(struct bnx2x *bp) |
2425 | { | |
2426 | bnx2x_acquire_phy_lock(bp); | |
2427 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); | |
2428 | bnx2x_release_phy_lock(bp); | |
2429 | } | |
2430 | ||
a22f0788 | 2431 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2432 | { |
2145a920 | 2433 | u8 rc = 0; |
a2fbb9ea | 2434 | |
2145a920 VZ |
2435 | if (!BP_NOMCP(bp)) { |
2436 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2437 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2438 | is_serdes); | |
2145a920 VZ |
2439 | bnx2x_release_phy_lock(bp); |
2440 | } else | |
2441 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2442 | |
c18487ee YR |
2443 | return rc; |
2444 | } | |
a2fbb9ea | 2445 | |
2691d51d EG |
2446 | /* Calculates the sum of vn_min_rates. |
2447 | It's needed for further normalizing of the min_rates. | |
2448 | Returns: | |
2449 | sum of vn_min_rates. | |
2450 | or | |
2451 | 0 - if all the min_rates are 0. | |
16a5fd92 | 2452 | In the later case fairness algorithm should be deactivated. |
2691d51d EG |
2453 | If not all min_rates are zero then those that are zeroes will be set to 1. |
2454 | */ | |
b475d78f YM |
2455 | static void bnx2x_calc_vn_min(struct bnx2x *bp, |
2456 | struct cmng_init_input *input) | |
2691d51d EG |
2457 | { |
2458 | int all_zero = 1; | |
2691d51d EG |
2459 | int vn; |
2460 | ||
3395a033 | 2461 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2462 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2463 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2464 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2465 | ||
2466 | /* Skip hidden vns */ | |
2467 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
b475d78f | 2468 | vn_min_rate = 0; |
2691d51d | 2469 | /* If min rate is zero - set it to 1 */ |
b475d78f | 2470 | else if (!vn_min_rate) |
2691d51d EG |
2471 | vn_min_rate = DEF_MIN_RATE; |
2472 | else | |
2473 | all_zero = 0; | |
2474 | ||
b475d78f | 2475 | input->vnic_min_rate[vn] = vn_min_rate; |
2691d51d EG |
2476 | } |
2477 | ||
30ae438b DK |
2478 | /* if ETS or all min rates are zeros - disable fairness */ |
2479 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
b475d78f | 2480 | input->flags.cmng_enables &= |
30ae438b DK |
2481 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2482 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2483 | } else if (all_zero) { | |
b475d78f | 2484 | input->flags.cmng_enables &= |
b015e3d1 | 2485 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
b475d78f YM |
2486 | DP(NETIF_MSG_IFUP, |
2487 | "All MIN values are zeroes fairness will be disabled\n"); | |
b015e3d1 | 2488 | } else |
b475d78f | 2489 | input->flags.cmng_enables |= |
b015e3d1 | 2490 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2691d51d EG |
2491 | } |
2492 | ||
b475d78f YM |
2493 | static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, |
2494 | struct cmng_init_input *input) | |
34f80b04 | 2495 | { |
b475d78f | 2496 | u16 vn_max_rate; |
f2e0899f | 2497 | u32 vn_cfg = bp->mf_config[vn]; |
34f80b04 | 2498 | |
b475d78f | 2499 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
34f80b04 | 2500 | vn_max_rate = 0; |
b475d78f | 2501 | else { |
faa6fcbb DK |
2502 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2503 | ||
da3cc2da | 2504 | if (IS_MF_PERCENT_BW(bp)) { |
faa6fcbb DK |
2505 | /* maxCfg in percents of linkspeed */ |
2506 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
b475d78f | 2507 | } else /* SD modes */ |
faa6fcbb DK |
2508 | /* maxCfg is absolute in 100Mb units */ |
2509 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2510 | } |
f85582f8 | 2511 | |
b475d78f | 2512 | DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); |
34f80b04 | 2513 | |
b475d78f | 2514 | input->vnic_max_rate[vn] = vn_max_rate; |
34f80b04 | 2515 | } |
f85582f8 | 2516 | |
523224a3 DK |
2517 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2518 | { | |
2519 | if (CHIP_REV_IS_SLOW(bp)) | |
2520 | return CMNG_FNS_NONE; | |
fb3bff17 | 2521 | if (IS_MF(bp)) |
523224a3 DK |
2522 | return CMNG_FNS_MINMAX; |
2523 | ||
2524 | return CMNG_FNS_NONE; | |
2525 | } | |
2526 | ||
2ae17f66 | 2527 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2528 | { |
0793f83f | 2529 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2530 | |
2531 | if (BP_NOMCP(bp)) | |
16a5fd92 | 2532 | return; /* what should be the default value in this case */ |
523224a3 | 2533 | |
0793f83f DK |
2534 | /* For 2 port configuration the absolute function number formula |
2535 | * is: | |
2536 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2537 | * | |
2538 | * and there are 4 functions per port | |
2539 | * | |
2540 | * For 4 port configuration it is | |
2541 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2542 | * | |
2543 | * and there are 2 functions per port | |
2544 | */ | |
3395a033 | 2545 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2546 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2547 | ||
2548 | if (func >= E1H_FUNC_MAX) | |
2549 | break; | |
2550 | ||
f2e0899f | 2551 | bp->mf_config[vn] = |
523224a3 DK |
2552 | MF_CFG_RD(bp, func_mf_config[func].config); |
2553 | } | |
a3348722 BW |
2554 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
2555 | DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); | |
2556 | bp->flags |= MF_FUNC_DIS; | |
2557 | } else { | |
2558 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2559 | bp->flags &= ~MF_FUNC_DIS; | |
2560 | } | |
523224a3 DK |
2561 | } |
2562 | ||
2563 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2564 | { | |
b475d78f YM |
2565 | struct cmng_init_input input; |
2566 | memset(&input, 0, sizeof(struct cmng_init_input)); | |
2567 | ||
2568 | input.port_rate = bp->link_vars.line_speed; | |
523224a3 | 2569 | |
568e2426 | 2570 | if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) { |
523224a3 DK |
2571 | int vn; |
2572 | ||
523224a3 DK |
2573 | /* read mf conf from shmem */ |
2574 | if (read_cfg) | |
2575 | bnx2x_read_mf_cfg(bp); | |
2576 | ||
523224a3 | 2577 | /* vn_weight_sum and enable fairness if not 0 */ |
b475d78f | 2578 | bnx2x_calc_vn_min(bp, &input); |
523224a3 DK |
2579 | |
2580 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2581 | if (bp->port.pmf) |
3395a033 | 2582 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
b475d78f | 2583 | bnx2x_calc_vn_max(bp, vn, &input); |
523224a3 DK |
2584 | |
2585 | /* always enable rate shaping and fairness */ | |
b475d78f | 2586 | input.flags.cmng_enables |= |
523224a3 | 2587 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; |
b475d78f YM |
2588 | |
2589 | bnx2x_init_cmng(&input, &bp->cmng); | |
523224a3 DK |
2590 | return; |
2591 | } | |
2592 | ||
2593 | /* rate shaping and fairness are disabled */ | |
2594 | DP(NETIF_MSG_IFUP, | |
2595 | "rate shaping and fairness are disabled\n"); | |
2596 | } | |
34f80b04 | 2597 | |
1191cb83 ED |
2598 | static void storm_memset_cmng(struct bnx2x *bp, |
2599 | struct cmng_init *cmng, | |
2600 | u8 port) | |
2601 | { | |
2602 | int vn; | |
2603 | size_t size = sizeof(struct cmng_struct_per_port); | |
2604 | ||
2605 | u32 addr = BAR_XSTRORM_INTMEM + | |
2606 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
2607 | ||
2608 | __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); | |
2609 | ||
2610 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
2611 | int func = func_by_vn(bp, vn); | |
2612 | ||
2613 | addr = BAR_XSTRORM_INTMEM + | |
2614 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); | |
2615 | size = sizeof(struct rate_shaping_vars_per_vn); | |
2616 | __storm_memset_struct(bp, addr, size, | |
2617 | (u32 *)&cmng->vnic.vnic_max_rate[vn]); | |
2618 | ||
2619 | addr = BAR_XSTRORM_INTMEM + | |
2620 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); | |
2621 | size = sizeof(struct fairness_vars_per_vn); | |
2622 | __storm_memset_struct(bp, addr, size, | |
2623 | (u32 *)&cmng->vnic.vnic_min_rate[vn]); | |
2624 | } | |
2625 | } | |
2626 | ||
568e2426 DK |
2627 | /* init cmng mode in HW according to local configuration */ |
2628 | void bnx2x_set_local_cmng(struct bnx2x *bp) | |
2629 | { | |
2630 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
2631 | ||
2632 | if (cmng_fns != CMNG_FNS_NONE) { | |
2633 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2634 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2635 | } else { | |
2636 | /* rate shaping and fairness are disabled */ | |
2637 | DP(NETIF_MSG_IFUP, | |
2638 | "single function mode without fairness\n"); | |
2639 | } | |
2640 | } | |
2641 | ||
c18487ee YR |
2642 | /* This function is called upon link interrupt */ |
2643 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2644 | { | |
bb2a0f7a YG |
2645 | /* Make sure that we are synced with the current statistics */ |
2646 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2647 | ||
c18487ee | 2648 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2649 | |
9156b30b | 2650 | bnx2x_init_dropless_fc(bp); |
1c06328c | 2651 | |
9156b30b | 2652 | if (bp->link_vars.link_up) { |
1c06328c | 2653 | |
619c5cb6 | 2654 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2655 | struct host_port_stats *pstats; |
2656 | ||
2657 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2658 | /* reset old mac stats */ |
bb2a0f7a YG |
2659 | memset(&(pstats->mac_stx[0]), 0, |
2660 | sizeof(struct mac_stx)); | |
2661 | } | |
f34d28ea | 2662 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2663 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2664 | } | |
2665 | ||
568e2426 DK |
2666 | if (bp->link_vars.link_up && bp->link_vars.line_speed) |
2667 | bnx2x_set_local_cmng(bp); | |
9fdc3e95 | 2668 | |
2ae17f66 VZ |
2669 | __bnx2x_link_report(bp); |
2670 | ||
9fdc3e95 DK |
2671 | if (IS_MF(bp)) |
2672 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2673 | } |
a2fbb9ea | 2674 | |
9f6c9258 | 2675 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2676 | { |
2ae17f66 | 2677 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2678 | return; |
a2fbb9ea | 2679 | |
00253a8c | 2680 | /* read updated dcb configuration */ |
ad5afc89 AE |
2681 | if (IS_PF(bp)) { |
2682 | bnx2x_dcbx_pmf_update(bp); | |
2683 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); | |
2684 | if (bp->link_vars.link_up) | |
2685 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2686 | else | |
2687 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2688 | /* indicate link status */ | |
2689 | bnx2x_link_report(bp); | |
a2fbb9ea | 2690 | |
ad5afc89 AE |
2691 | } else { /* VF */ |
2692 | bp->port.supported[0] |= (SUPPORTED_10baseT_Half | | |
2693 | SUPPORTED_10baseT_Full | | |
2694 | SUPPORTED_100baseT_Half | | |
2695 | SUPPORTED_100baseT_Full | | |
2696 | SUPPORTED_1000baseT_Full | | |
2697 | SUPPORTED_2500baseX_Full | | |
2698 | SUPPORTED_10000baseT_Full | | |
2699 | SUPPORTED_TP | | |
2700 | SUPPORTED_FIBRE | | |
2701 | SUPPORTED_Autoneg | | |
2702 | SUPPORTED_Pause | | |
2703 | SUPPORTED_Asym_Pause); | |
2704 | bp->port.advertising[0] = bp->port.supported[0]; | |
2705 | ||
2706 | bp->link_params.bp = bp; | |
2707 | bp->link_params.port = BP_PORT(bp); | |
2708 | bp->link_params.req_duplex[0] = DUPLEX_FULL; | |
2709 | bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; | |
2710 | bp->link_params.req_line_speed[0] = SPEED_10000; | |
2711 | bp->link_params.speed_cap_mask[0] = 0x7f0000; | |
2712 | bp->link_params.switch_cfg = SWITCH_CFG_10G; | |
2713 | bp->link_vars.mac_type = MAC_TYPE_BMAC; | |
2714 | bp->link_vars.line_speed = SPEED_10000; | |
2715 | bp->link_vars.link_status = | |
2716 | (LINK_STATUS_LINK_UP | | |
2717 | LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); | |
2718 | bp->link_vars.link_up = 1; | |
2719 | bp->link_vars.duplex = DUPLEX_FULL; | |
2720 | bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
2721 | __bnx2x_link_report(bp); | |
6495d15a DK |
2722 | |
2723 | bnx2x_sample_bulletin(bp); | |
2724 | ||
2725 | /* if bulletin board did not have an update for link status | |
2726 | * __bnx2x_link_report will report current status | |
2727 | * but it will NOT duplicate report in case of already reported | |
2728 | * during sampling bulletin board. | |
2729 | */ | |
bb2a0f7a | 2730 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
ad5afc89 | 2731 | } |
a2fbb9ea | 2732 | } |
a2fbb9ea | 2733 | |
a3348722 BW |
2734 | static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, |
2735 | u16 vlan_val, u8 allowed_prio) | |
2736 | { | |
86564c3f | 2737 | struct bnx2x_func_state_params func_params = {NULL}; |
a3348722 BW |
2738 | struct bnx2x_func_afex_update_params *f_update_params = |
2739 | &func_params.params.afex_update; | |
2740 | ||
2741 | func_params.f_obj = &bp->func_obj; | |
2742 | func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; | |
2743 | ||
2744 | /* no need to wait for RAMROD completion, so don't | |
2745 | * set RAMROD_COMP_WAIT flag | |
2746 | */ | |
2747 | ||
2748 | f_update_params->vif_id = vifid; | |
2749 | f_update_params->afex_default_vlan = vlan_val; | |
2750 | f_update_params->allowed_priorities = allowed_prio; | |
2751 | ||
2752 | /* if ramrod can not be sent, response to MCP immediately */ | |
2753 | if (bnx2x_func_state_change(bp, &func_params) < 0) | |
2754 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
2755 | ||
2756 | return 0; | |
2757 | } | |
2758 | ||
2759 | static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, | |
2760 | u16 vif_index, u8 func_bit_map) | |
2761 | { | |
86564c3f | 2762 | struct bnx2x_func_state_params func_params = {NULL}; |
a3348722 BW |
2763 | struct bnx2x_func_afex_viflists_params *update_params = |
2764 | &func_params.params.afex_viflists; | |
2765 | int rc; | |
2766 | u32 drv_msg_code; | |
2767 | ||
2768 | /* validate only LIST_SET and LIST_GET are received from switch */ | |
2769 | if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) | |
2770 | BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", | |
2771 | cmd_type); | |
2772 | ||
2773 | func_params.f_obj = &bp->func_obj; | |
2774 | func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; | |
2775 | ||
2776 | /* set parameters according to cmd_type */ | |
2777 | update_params->afex_vif_list_command = cmd_type; | |
86564c3f | 2778 | update_params->vif_list_index = vif_index; |
a3348722 BW |
2779 | update_params->func_bit_map = |
2780 | (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; | |
2781 | update_params->func_to_clear = 0; | |
2782 | drv_msg_code = | |
2783 | (cmd_type == VIF_LIST_RULE_GET) ? | |
2784 | DRV_MSG_CODE_AFEX_LISTGET_ACK : | |
2785 | DRV_MSG_CODE_AFEX_LISTSET_ACK; | |
2786 | ||
2787 | /* if ramrod can not be sent, respond to MCP immediately for | |
2788 | * SET and GET requests (other are not triggered from MCP) | |
2789 | */ | |
2790 | rc = bnx2x_func_state_change(bp, &func_params); | |
2791 | if (rc < 0) | |
2792 | bnx2x_fw_command(bp, drv_msg_code, 0); | |
2793 | ||
2794 | return 0; | |
2795 | } | |
2796 | ||
2797 | static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) | |
2798 | { | |
2799 | struct afex_stats afex_stats; | |
2800 | u32 func = BP_ABS_FUNC(bp); | |
2801 | u32 mf_config; | |
2802 | u16 vlan_val; | |
2803 | u32 vlan_prio; | |
2804 | u16 vif_id; | |
2805 | u8 allowed_prio; | |
2806 | u8 vlan_mode; | |
2807 | u32 addr_to_write, vifid, addrs, stats_type, i; | |
2808 | ||
2809 | if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { | |
2810 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2811 | DP(BNX2X_MSG_MCP, | |
2812 | "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); | |
2813 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); | |
2814 | } | |
2815 | ||
2816 | if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { | |
2817 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2818 | addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); | |
2819 | DP(BNX2X_MSG_MCP, | |
2820 | "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", | |
2821 | vifid, addrs); | |
2822 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, | |
2823 | addrs); | |
2824 | } | |
2825 | ||
2826 | if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { | |
2827 | addr_to_write = SHMEM2_RD(bp, | |
2828 | afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); | |
2829 | stats_type = SHMEM2_RD(bp, | |
2830 | afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2831 | ||
2832 | DP(BNX2X_MSG_MCP, | |
2833 | "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", | |
2834 | addr_to_write); | |
2835 | ||
2836 | bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); | |
2837 | ||
2838 | /* write response to scratchpad, for MCP */ | |
2839 | for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) | |
2840 | REG_WR(bp, addr_to_write + i*sizeof(u32), | |
2841 | *(((u32 *)(&afex_stats))+i)); | |
2842 | ||
2843 | /* send ack message to MCP */ | |
2844 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); | |
2845 | } | |
2846 | ||
2847 | if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { | |
2848 | mf_config = MF_CFG_RD(bp, func_mf_config[func].config); | |
2849 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2850 | DP(BNX2X_MSG_MCP, | |
2851 | "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", | |
2852 | mf_config); | |
2853 | ||
2854 | /* if VIF_SET is "enabled" */ | |
2855 | if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { | |
2856 | /* set rate limit directly to internal RAM */ | |
2857 | struct cmng_init_input cmng_input; | |
2858 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2859 | size_t size = sizeof(struct rate_shaping_vars_per_vn); | |
2860 | u32 addr = BAR_XSTRORM_INTMEM + | |
2861 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); | |
2862 | ||
2863 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2864 | ||
2865 | bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); | |
2866 | m_rs_vn.vn_counter.rate = | |
2867 | cmng_input.vnic_max_rate[BP_VN(bp)]; | |
2868 | m_rs_vn.vn_counter.quota = | |
2869 | (m_rs_vn.vn_counter.rate * | |
2870 | RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2871 | ||
2872 | __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); | |
2873 | ||
2874 | /* read relevant values from mf_cfg struct in shmem */ | |
2875 | vif_id = | |
2876 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2877 | FUNC_MF_CFG_E1HOV_TAG_MASK) >> | |
2878 | FUNC_MF_CFG_E1HOV_TAG_SHIFT; | |
2879 | vlan_val = | |
2880 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2881 | FUNC_MF_CFG_AFEX_VLAN_MASK) >> | |
2882 | FUNC_MF_CFG_AFEX_VLAN_SHIFT; | |
2883 | vlan_prio = (mf_config & | |
2884 | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> | |
2885 | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; | |
2886 | vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); | |
2887 | vlan_mode = | |
2888 | (MF_CFG_RD(bp, | |
2889 | func_mf_config[func].afex_config) & | |
2890 | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> | |
2891 | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; | |
2892 | allowed_prio = | |
2893 | (MF_CFG_RD(bp, | |
2894 | func_mf_config[func].afex_config) & | |
2895 | FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> | |
2896 | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; | |
2897 | ||
2898 | /* send ramrod to FW, return in case of failure */ | |
2899 | if (bnx2x_afex_func_update(bp, vif_id, vlan_val, | |
2900 | allowed_prio)) | |
2901 | return; | |
2902 | ||
2903 | bp->afex_def_vlan_tag = vlan_val; | |
2904 | bp->afex_vlan_mode = vlan_mode; | |
2905 | } else { | |
2906 | /* notify link down because BP->flags is disabled */ | |
2907 | bnx2x_link_report(bp); | |
2908 | ||
2909 | /* send INVALID VIF ramrod to FW */ | |
2910 | bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); | |
2911 | ||
2912 | /* Reset the default afex VLAN */ | |
2913 | bp->afex_def_vlan_tag = -1; | |
2914 | } | |
2915 | } | |
2916 | } | |
2917 | ||
7609647e YM |
2918 | static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp) |
2919 | { | |
2920 | struct bnx2x_func_switch_update_params *switch_update_params; | |
2921 | struct bnx2x_func_state_params func_params; | |
2922 | ||
2923 | memset(&func_params, 0, sizeof(struct bnx2x_func_state_params)); | |
2924 | switch_update_params = &func_params.params.switch_update; | |
2925 | func_params.f_obj = &bp->func_obj; | |
2926 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
2927 | ||
ebbdb4b5 SRK |
2928 | /* Prepare parameters for function state transitions */ |
2929 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
2930 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
2931 | ||
230d00eb | 2932 | if (IS_MF_UFP(bp) || IS_MF_BD(bp)) { |
7609647e YM |
2933 | int func = BP_ABS_FUNC(bp); |
2934 | u32 val; | |
2935 | ||
2936 | /* Re-learn the S-tag from shmem */ | |
2937 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2938 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2939 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
2940 | bp->mf_ov = val; | |
2941 | } else { | |
2942 | BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n"); | |
2943 | goto fail; | |
2944 | } | |
2945 | ||
2946 | /* Configure new S-tag in LLH */ | |
2947 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, | |
2948 | bp->mf_ov); | |
2949 | ||
2950 | /* Send Ramrod to update FW of change */ | |
2951 | __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG, | |
2952 | &switch_update_params->changes); | |
2953 | switch_update_params->vlan = bp->mf_ov; | |
2954 | ||
2955 | if (bnx2x_func_state_change(bp, &func_params) < 0) { | |
2956 | BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n", | |
2957 | bp->mf_ov); | |
2958 | goto fail; | |
230d00eb YM |
2959 | } else { |
2960 | DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", | |
2961 | bp->mf_ov); | |
7609647e | 2962 | } |
230d00eb YM |
2963 | } else { |
2964 | goto fail; | |
7609647e YM |
2965 | } |
2966 | ||
230d00eb YM |
2967 | bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0); |
2968 | return; | |
7609647e YM |
2969 | fail: |
2970 | bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0); | |
2971 | } | |
2972 | ||
34f80b04 EG |
2973 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2974 | { | |
2975 | int port = BP_PORT(bp); | |
2976 | u32 val; | |
2977 | ||
2978 | bp->port.pmf = 1; | |
51c1a580 | 2979 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
34f80b04 | 2980 | |
3deb8167 YR |
2981 | /* |
2982 | * We need the mb() to ensure the ordering between the writing to | |
2983 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2984 | */ | |
2985 | smp_mb(); | |
2986 | ||
2987 | /* queue a periodic task */ | |
2988 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2989 | ||
ef01854e DK |
2990 | bnx2x_dcbx_pmf_update(bp); |
2991 | ||
34f80b04 | 2992 | /* enable nig attention */ |
3395a033 | 2993 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
2994 | if (bp->common.int_block == INT_BLOCK_HC) { |
2995 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2996 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2997 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2998 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2999 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
3000 | } | |
bb2a0f7a YG |
3001 | |
3002 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
3003 | } |
3004 | ||
c18487ee | 3005 | /* end of Link */ |
a2fbb9ea ET |
3006 | |
3007 | /* slow path */ | |
3008 | ||
3009 | /* | |
3010 | * General service functions | |
3011 | */ | |
3012 | ||
2691d51d | 3013 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 3014 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 3015 | { |
f2e0899f | 3016 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 3017 | u32 seq; |
2691d51d EG |
3018 | u32 rc = 0; |
3019 | u32 cnt = 1; | |
3020 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
3021 | ||
c4ff7cbf | 3022 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 3023 | seq = ++bp->fw_seq; |
f2e0899f DK |
3024 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
3025 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
3026 | ||
754a2f52 DK |
3027 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
3028 | (command | seq), param); | |
2691d51d EG |
3029 | |
3030 | do { | |
3031 | /* let the FW do it's magic ... */ | |
3032 | msleep(delay); | |
3033 | ||
f2e0899f | 3034 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 3035 | |
c4ff7cbf EG |
3036 | /* Give the FW up to 5 second (500*10ms) */ |
3037 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
3038 | |
3039 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
3040 | cnt*delay, rc, seq); | |
3041 | ||
3042 | /* is this a reply to our command? */ | |
3043 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
3044 | rc &= FW_MSG_CODE_MASK; | |
3045 | else { | |
3046 | /* FW BUG! */ | |
3047 | BNX2X_ERR("FW failed to respond!\n"); | |
3048 | bnx2x_fw_dump(bp); | |
3049 | rc = 0; | |
3050 | } | |
c4ff7cbf | 3051 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
3052 | |
3053 | return rc; | |
3054 | } | |
3055 | ||
1191cb83 ED |
3056 | static void storm_memset_func_cfg(struct bnx2x *bp, |
3057 | struct tstorm_eth_function_common_config *tcfg, | |
3058 | u16 abs_fid) | |
3059 | { | |
3060 | size_t size = sizeof(struct tstorm_eth_function_common_config); | |
3061 | ||
3062 | u32 addr = BAR_TSTRORM_INTMEM + | |
3063 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); | |
3064 | ||
3065 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); | |
3066 | } | |
3067 | ||
619c5cb6 VZ |
3068 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
3069 | { | |
3070 | if (CHIP_IS_E1x(bp)) { | |
3071 | struct tstorm_eth_function_common_config tcfg = {0}; | |
3072 | ||
3073 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
3074 | } | |
3075 | ||
3076 | /* Enable the function in the FW */ | |
3077 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
3078 | storm_memset_func_en(bp, p->func_id, 1); | |
3079 | ||
3080 | /* spq */ | |
05cc5a39 | 3081 | if (p->spq_active) { |
619c5cb6 VZ |
3082 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); |
3083 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
3084 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
3085 | } | |
3086 | } | |
3087 | ||
6383c0b3 | 3088 | /** |
16a5fd92 | 3089 | * bnx2x_get_common_flags - Return common flags |
6383c0b3 AE |
3090 | * |
3091 | * @bp device handle | |
3092 | * @fp queue handle | |
3093 | * @zero_stats TRUE if statistics zeroing is needed | |
3094 | * | |
3095 | * Return the flags that are common for the Tx-only and not normal connections. | |
3096 | */ | |
1191cb83 ED |
3097 | static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, |
3098 | struct bnx2x_fastpath *fp, | |
3099 | bool zero_stats) | |
28912902 | 3100 | { |
619c5cb6 VZ |
3101 | unsigned long flags = 0; |
3102 | ||
3103 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
3104 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 3105 | |
6383c0b3 | 3106 | /* tx only connections collect statistics (on the same index as the |
91226790 DK |
3107 | * parent connection). The statistics are zeroed when the parent |
3108 | * connection is initialized. | |
6383c0b3 | 3109 | */ |
50f0a562 BW |
3110 | |
3111 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
3112 | if (zero_stats) | |
3113 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
3114 | ||
c14db202 YM |
3115 | if (bp->flags & TX_SWITCHING) |
3116 | __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags); | |
3117 | ||
91226790 | 3118 | __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags); |
e287a75c | 3119 | __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags); |
6383c0b3 | 3120 | |
823e1d90 YM |
3121 | #ifdef BNX2X_STOP_ON_ERROR |
3122 | __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); | |
3123 | #endif | |
3124 | ||
6383c0b3 AE |
3125 | return flags; |
3126 | } | |
3127 | ||
1191cb83 ED |
3128 | static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, |
3129 | struct bnx2x_fastpath *fp, | |
3130 | bool leading) | |
6383c0b3 AE |
3131 | { |
3132 | unsigned long flags = 0; | |
3133 | ||
619c5cb6 VZ |
3134 | /* calculate other queue flags */ |
3135 | if (IS_MF_SD(bp)) | |
3136 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 3137 | |
a3348722 | 3138 | if (IS_FCOE_FP(fp)) { |
619c5cb6 | 3139 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); |
a3348722 BW |
3140 | /* For FCoE - force usage of default priority (for afex) */ |
3141 | __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); | |
3142 | } | |
523224a3 | 3143 | |
7e6b4d44 | 3144 | if (fp->mode != TPA_MODE_DISABLED) { |
619c5cb6 | 3145 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e | 3146 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
621b4d66 DK |
3147 | if (fp->mode == TPA_MODE_GRO) |
3148 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); | |
f5219d8e | 3149 | } |
619c5cb6 | 3150 | |
619c5cb6 VZ |
3151 | if (leading) { |
3152 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
3153 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
3154 | } | |
523224a3 | 3155 | |
619c5cb6 VZ |
3156 | /* Always set HW VLAN stripping */ |
3157 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 3158 | |
a3348722 BW |
3159 | /* configure silent vlan removal */ |
3160 | if (IS_MF_AFEX(bp)) | |
3161 | __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); | |
3162 | ||
6383c0b3 | 3163 | return flags | bnx2x_get_common_flags(bp, fp, true); |
523224a3 DK |
3164 | } |
3165 | ||
619c5cb6 | 3166 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
3167 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
3168 | u8 cos) | |
619c5cb6 VZ |
3169 | { |
3170 | gen_init->stat_id = bnx2x_stats_id(fp); | |
3171 | gen_init->spcl_id = fp->cl_id; | |
3172 | ||
3173 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
3174 | if (IS_FCOE_FP(fp)) | |
3175 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
3176 | else | |
3177 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
3178 | |
3179 | gen_init->cos = cos; | |
02dc4025 YM |
3180 | |
3181 | gen_init->fp_hsi = ETH_FP_HSI_VERSION; | |
619c5cb6 VZ |
3182 | } |
3183 | ||
3184 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 3185 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 3186 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 3187 | { |
619c5cb6 | 3188 | u8 max_sge = 0; |
523224a3 DK |
3189 | u16 sge_sz = 0; |
3190 | u16 tpa_agg_size = 0; | |
3191 | ||
7e6b4d44 | 3192 | if (fp->mode != TPA_MODE_DISABLED) { |
dfacf138 DK |
3193 | pause->sge_th_lo = SGE_TH_LO(bp); |
3194 | pause->sge_th_hi = SGE_TH_HI(bp); | |
3195 | ||
3196 | /* validate SGE ring has enough to cross high threshold */ | |
3197 | WARN_ON(bp->dropless_fc && | |
3198 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
3199 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
3200 | ||
924d75ab | 3201 | tpa_agg_size = TPA_AGG_SIZE; |
523224a3 DK |
3202 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> |
3203 | SGE_PAGE_SHIFT; | |
3204 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
3205 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
924d75ab | 3206 | sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); |
523224a3 DK |
3207 | } |
3208 | ||
3209 | /* pause - not for e1 */ | |
3210 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
3211 | pause->bd_th_lo = BD_TH_LO(bp); |
3212 | pause->bd_th_hi = BD_TH_HI(bp); | |
3213 | ||
3214 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
3215 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
3216 | /* | |
3217 | * validate that rings have enough entries to cross | |
3218 | * high thresholds | |
3219 | */ | |
3220 | WARN_ON(bp->dropless_fc && | |
3221 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
3222 | bp->rx_ring_size); | |
3223 | WARN_ON(bp->dropless_fc && | |
3224 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
3225 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 3226 | |
523224a3 DK |
3227 | pause->pri_map = 1; |
3228 | } | |
3229 | ||
3230 | /* rxq setup */ | |
523224a3 DK |
3231 | rxq_init->dscr_map = fp->rx_desc_mapping; |
3232 | rxq_init->sge_map = fp->rx_sge_mapping; | |
3233 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
3234 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 3235 | |
619c5cb6 VZ |
3236 | /* This should be a maximum number of data bytes that may be |
3237 | * placed on the BD (not including paddings). | |
3238 | */ | |
e52fcb24 | 3239 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
3cdeec22 | 3240 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; |
a8c94b91 | 3241 | |
523224a3 | 3242 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
3243 | rxq_init->tpa_agg_sz = tpa_agg_size; |
3244 | rxq_init->sge_buf_sz = sge_sz; | |
3245 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 | 3246 | rxq_init->rss_engine_id = BP_FUNC(bp); |
259afa1f | 3247 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
619c5cb6 VZ |
3248 | |
3249 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
3250 | * | |
2de67439 | 3251 | * For PF Clients it should be the maximum available number. |
619c5cb6 VZ |
3252 | * VF driver(s) may want to define it to a smaller value. |
3253 | */ | |
dfacf138 | 3254 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 3255 | |
523224a3 DK |
3256 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
3257 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
3258 | ||
ec6ba945 VZ |
3259 | if (IS_FCOE_FP(fp)) |
3260 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
3261 | else | |
6383c0b3 | 3262 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
a3348722 BW |
3263 | /* configure silent vlan removal |
3264 | * if multi function mode is afex, then mask default vlan | |
3265 | */ | |
3266 | if (IS_MF_AFEX(bp)) { | |
3267 | rxq_init->silent_removal_value = bp->afex_def_vlan_tag; | |
3268 | rxq_init->silent_removal_mask = VLAN_VID_MASK; | |
3269 | } | |
523224a3 DK |
3270 | } |
3271 | ||
619c5cb6 | 3272 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
3273 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
3274 | u8 cos) | |
523224a3 | 3275 | { |
65565884 | 3276 | txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; |
6383c0b3 | 3277 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; |
523224a3 DK |
3278 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
3279 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 3280 | |
619c5cb6 | 3281 | /* |
16a5fd92 | 3282 | * set the tss leading client id for TX classification == |
619c5cb6 VZ |
3283 | * leading RSS client id |
3284 | */ | |
3285 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
3286 | ||
ec6ba945 VZ |
3287 | if (IS_FCOE_FP(fp)) { |
3288 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
3289 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
3290 | } | |
523224a3 DK |
3291 | } |
3292 | ||
8d96286a | 3293 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
3294 | { |
3295 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 | 3296 | struct event_ring_data eq_data = { {0} }; |
523224a3 | 3297 | |
619c5cb6 | 3298 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
3299 | /* reset IGU PF statistics: MSIX + ATTN */ |
3300 | /* PF */ | |
3301 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3302 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3303 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3304 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3305 | /* ATTN */ | |
3306 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3307 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3308 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
3309 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3310 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3311 | } | |
3312 | ||
05cc5a39 | 3313 | func_init.spq_active = true; |
523224a3 DK |
3314 | func_init.pf_id = BP_FUNC(bp); |
3315 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
3316 | func_init.spq_map = bp->spq_mapping; |
3317 | func_init.spq_prod = bp->spq_prod_idx; | |
3318 | ||
3319 | bnx2x_func_init(bp, &func_init); | |
3320 | ||
3321 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
3322 | ||
3323 | /* | |
619c5cb6 VZ |
3324 | * Congestion management values depend on the link rate |
3325 | * There is no active link so initial link rate is set to 10 Gbps. | |
3326 | * When the link comes up The congestion management values are | |
3327 | * re-calculated according to the actual link rate. | |
3328 | */ | |
523224a3 DK |
3329 | bp->link_vars.line_speed = SPEED_10000; |
3330 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
3331 | ||
3332 | /* Only the PMF sets the HW */ | |
3333 | if (bp->port.pmf) | |
3334 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3335 | ||
86564c3f | 3336 | /* init Event Queue - PCI bus guarantees correct endianity*/ |
523224a3 DK |
3337 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); |
3338 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
3339 | eq_data.producer = bp->eq_prod; | |
3340 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
3341 | eq_data.sb_id = DEF_SB_ID; | |
3342 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
3343 | } | |
3344 | ||
523224a3 DK |
3345 | static void bnx2x_e1h_disable(struct bnx2x *bp) |
3346 | { | |
3347 | int port = BP_PORT(bp); | |
3348 | ||
619c5cb6 | 3349 | bnx2x_tx_disable(bp); |
523224a3 DK |
3350 | |
3351 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
3352 | } |
3353 | ||
3354 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
3355 | { | |
3356 | int port = BP_PORT(bp); | |
3357 | ||
7609647e YM |
3358 | if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) |
3359 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); | |
523224a3 | 3360 | |
16a5fd92 | 3361 | /* Tx queue should be only re-enabled */ |
523224a3 DK |
3362 | netif_tx_wake_all_queues(bp->dev); |
3363 | ||
3364 | /* | |
3365 | * Should not call netif_carrier_on since it will be called if the link | |
3366 | * is up when checking for link state | |
3367 | */ | |
3368 | } | |
3369 | ||
1d187b34 BW |
3370 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
3371 | ||
3372 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) | |
3373 | { | |
3374 | struct eth_stats_info *ether_stat = | |
3375 | &bp->slowpath->drv_info_to_mcp.ether_stat; | |
3ec9f9ca AE |
3376 | struct bnx2x_vlan_mac_obj *mac_obj = |
3377 | &bp->sp_objs->mac_obj; | |
3378 | int i; | |
1d187b34 | 3379 | |
786fdf0b DC |
3380 | strlcpy(ether_stat->version, DRV_MODULE_VERSION, |
3381 | ETH_STAT_INFO_VERSION_LEN); | |
1d187b34 | 3382 | |
3ec9f9ca AE |
3383 | /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the |
3384 | * mac_local field in ether_stat struct. The base address is offset by 2 | |
3385 | * bytes to account for the field being 8 bytes but a mac address is | |
3386 | * only 6 bytes. Likewise, the stride for the get_n_elements function is | |
3387 | * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes | |
3388 | * allocated by the ether_stat struct, so the macs will land in their | |
3389 | * proper positions. | |
3390 | */ | |
3391 | for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) | |
3392 | memset(ether_stat->mac_local + i, 0, | |
3393 | sizeof(ether_stat->mac_local[0])); | |
3394 | mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, | |
3395 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | |
3396 | ether_stat->mac_local + MAC_PAD, MAC_PAD, | |
3397 | ETH_ALEN); | |
1d187b34 | 3398 | ether_stat->mtu_size = bp->dev->mtu; |
1d187b34 BW |
3399 | if (bp->dev->features & NETIF_F_RXCSUM) |
3400 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | |
3401 | if (bp->dev->features & NETIF_F_TSO) | |
3402 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; | |
3403 | ether_stat->feature_flags |= bp->common.boot_mode; | |
3404 | ||
3405 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; | |
3406 | ||
3407 | ether_stat->txq_size = bp->tx_ring_size; | |
3408 | ether_stat->rxq_size = bp->rx_ring_size; | |
0c757dee | 3409 | |
fcf93a0a | 3410 | #ifdef CONFIG_BNX2X_SRIOV |
0c757dee | 3411 | ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0; |
fcf93a0a | 3412 | #endif |
1d187b34 BW |
3413 | } |
3414 | ||
3415 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) | |
3416 | { | |
3417 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3418 | struct fcoe_stats_info *fcoe_stat = | |
3419 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; | |
3420 | ||
55c11941 MS |
3421 | if (!CNIC_LOADED(bp)) |
3422 | return; | |
3423 | ||
3ec9f9ca | 3424 | memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); |
1d187b34 BW |
3425 | |
3426 | fcoe_stat->qos_priority = | |
3427 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | |
3428 | ||
3429 | /* insert FCoE stats from ramrod response */ | |
3430 | if (!NO_FCOE(bp)) { | |
3431 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = | |
65565884 | 3432 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3433 | tstorm_queue_statistics; |
3434 | ||
3435 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = | |
65565884 | 3436 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3437 | xstorm_queue_statistics; |
3438 | ||
3439 | struct fcoe_statistics_params *fw_fcoe_stat = | |
3440 | &bp->fw_stats_data->fcoe; | |
3441 | ||
86564c3f YM |
3442 | ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, |
3443 | fcoe_stat->rx_bytes_lo, | |
3444 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); | |
1d187b34 | 3445 | |
86564c3f YM |
3446 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3447 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, | |
3448 | fcoe_stat->rx_bytes_lo, | |
3449 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); | |
1d187b34 | 3450 | |
86564c3f YM |
3451 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3452 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, | |
3453 | fcoe_stat->rx_bytes_lo, | |
3454 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); | |
1d187b34 | 3455 | |
86564c3f YM |
3456 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3457 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, | |
3458 | fcoe_stat->rx_bytes_lo, | |
3459 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); | |
1d187b34 | 3460 | |
86564c3f YM |
3461 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3462 | fcoe_stat->rx_frames_lo, | |
3463 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); | |
1d187b34 | 3464 | |
86564c3f YM |
3465 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3466 | fcoe_stat->rx_frames_lo, | |
3467 | fcoe_q_tstorm_stats->rcv_ucast_pkts); | |
1d187b34 | 3468 | |
86564c3f YM |
3469 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3470 | fcoe_stat->rx_frames_lo, | |
3471 | fcoe_q_tstorm_stats->rcv_bcast_pkts); | |
1d187b34 | 3472 | |
86564c3f YM |
3473 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3474 | fcoe_stat->rx_frames_lo, | |
3475 | fcoe_q_tstorm_stats->rcv_mcast_pkts); | |
1d187b34 | 3476 | |
86564c3f YM |
3477 | ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, |
3478 | fcoe_stat->tx_bytes_lo, | |
3479 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); | |
1d187b34 | 3480 | |
86564c3f YM |
3481 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3482 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, | |
3483 | fcoe_stat->tx_bytes_lo, | |
3484 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); | |
1d187b34 | 3485 | |
86564c3f YM |
3486 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3487 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, | |
3488 | fcoe_stat->tx_bytes_lo, | |
3489 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); | |
1d187b34 | 3490 | |
86564c3f YM |
3491 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3492 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, | |
3493 | fcoe_stat->tx_bytes_lo, | |
3494 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); | |
1d187b34 | 3495 | |
86564c3f YM |
3496 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3497 | fcoe_stat->tx_frames_lo, | |
3498 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); | |
1d187b34 | 3499 | |
86564c3f YM |
3500 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3501 | fcoe_stat->tx_frames_lo, | |
3502 | fcoe_q_xstorm_stats->ucast_pkts_sent); | |
1d187b34 | 3503 | |
86564c3f YM |
3504 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3505 | fcoe_stat->tx_frames_lo, | |
3506 | fcoe_q_xstorm_stats->bcast_pkts_sent); | |
1d187b34 | 3507 | |
86564c3f YM |
3508 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3509 | fcoe_stat->tx_frames_lo, | |
3510 | fcoe_q_xstorm_stats->mcast_pkts_sent); | |
1d187b34 BW |
3511 | } |
3512 | ||
1d187b34 BW |
3513 | /* ask L5 driver to add data to the struct */ |
3514 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); | |
1d187b34 BW |
3515 | } |
3516 | ||
3517 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) | |
3518 | { | |
3519 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3520 | struct iscsi_stats_info *iscsi_stat = | |
3521 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; | |
3522 | ||
55c11941 MS |
3523 | if (!CNIC_LOADED(bp)) |
3524 | return; | |
3525 | ||
3ec9f9ca AE |
3526 | memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, |
3527 | ETH_ALEN); | |
1d187b34 BW |
3528 | |
3529 | iscsi_stat->qos_priority = | |
3530 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | |
3531 | ||
1d187b34 BW |
3532 | /* ask L5 driver to add data to the struct */ |
3533 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); | |
1d187b34 BW |
3534 | } |
3535 | ||
0793f83f DK |
3536 | /* called due to MCP event (on pmf): |
3537 | * reread new bandwidth configuration | |
3538 | * configure FW | |
3539 | * notify others function about the change | |
3540 | */ | |
1191cb83 | 3541 | static void bnx2x_config_mf_bw(struct bnx2x *bp) |
0793f83f | 3542 | { |
115b7000 SS |
3543 | /* Workaround for MFW bug. |
3544 | * MFW is not supposed to generate BW attention in | |
3545 | * single function mode. | |
3546 | */ | |
3547 | if (!IS_MF(bp)) { | |
3548 | DP(BNX2X_MSG_MCP, | |
3549 | "Ignoring MF BW config in single function mode\n"); | |
3550 | return; | |
3551 | } | |
3552 | ||
0793f83f DK |
3553 | if (bp->link_vars.link_up) { |
3554 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
3555 | bnx2x_link_sync_notify(bp); | |
3556 | } | |
3557 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3558 | } | |
3559 | ||
1191cb83 | 3560 | static void bnx2x_set_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3561 | { |
3562 | bnx2x_config_mf_bw(bp); | |
3563 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
3564 | } | |
3565 | ||
c8c60d88 YM |
3566 | static void bnx2x_handle_eee_event(struct bnx2x *bp) |
3567 | { | |
3568 | DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); | |
3569 | bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); | |
3570 | } | |
3571 | ||
42f8277f YM |
3572 | #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20) |
3573 | #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25) | |
3574 | ||
1d187b34 BW |
3575 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
3576 | { | |
3577 | enum drv_info_opcode op_code; | |
3578 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); | |
42f8277f YM |
3579 | bool release = false; |
3580 | int wait; | |
1d187b34 BW |
3581 | |
3582 | /* if drv_info version supported by MFW doesn't match - send NACK */ | |
3583 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { | |
3584 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3585 | return; | |
3586 | } | |
3587 | ||
3588 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> | |
3589 | DRV_INFO_CONTROL_OP_CODE_SHIFT; | |
3590 | ||
42f8277f YM |
3591 | /* Must prevent other flows from accessing drv_info_to_mcp */ |
3592 | mutex_lock(&bp->drv_info_mutex); | |
3593 | ||
1d187b34 BW |
3594 | memset(&bp->slowpath->drv_info_to_mcp, 0, |
3595 | sizeof(union drv_info_to_mcp)); | |
3596 | ||
3597 | switch (op_code) { | |
3598 | case ETH_STATS_OPCODE: | |
3599 | bnx2x_drv_info_ether_stat(bp); | |
3600 | break; | |
3601 | case FCOE_STATS_OPCODE: | |
3602 | bnx2x_drv_info_fcoe_stat(bp); | |
3603 | break; | |
3604 | case ISCSI_STATS_OPCODE: | |
3605 | bnx2x_drv_info_iscsi_stat(bp); | |
3606 | break; | |
3607 | default: | |
3608 | /* if op code isn't supported - send NACK */ | |
3609 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
42f8277f | 3610 | goto out; |
1d187b34 BW |
3611 | } |
3612 | ||
3613 | /* if we got drv_info attn from MFW then these fields are defined in | |
3614 | * shmem2 for sure | |
3615 | */ | |
3616 | SHMEM2_WR(bp, drv_info_host_addr_lo, | |
3617 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3618 | SHMEM2_WR(bp, drv_info_host_addr_hi, | |
3619 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3620 | ||
3621 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); | |
42f8277f YM |
3622 | |
3623 | /* Since possible management wants both this and get_driver_version | |
3624 | * need to wait until management notifies us it finished utilizing | |
3625 | * the buffer. | |
3626 | */ | |
3627 | if (!SHMEM2_HAS(bp, mfw_drv_indication)) { | |
3628 | DP(BNX2X_MSG_MCP, "Management does not support indication\n"); | |
3629 | } else if (!bp->drv_info_mng_owner) { | |
3630 | u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1)); | |
3631 | ||
3632 | for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) { | |
3633 | u32 indication = SHMEM2_RD(bp, mfw_drv_indication); | |
3634 | ||
3635 | /* Management is done; need to clear indication */ | |
3636 | if (indication & bit) { | |
3637 | SHMEM2_WR(bp, mfw_drv_indication, | |
3638 | indication & ~bit); | |
3639 | release = true; | |
3640 | break; | |
3641 | } | |
3642 | ||
3643 | msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH); | |
3644 | } | |
3645 | } | |
3646 | if (!release) { | |
3647 | DP(BNX2X_MSG_MCP, "Management did not release indication\n"); | |
3648 | bp->drv_info_mng_owner = true; | |
3649 | } | |
3650 | ||
3651 | out: | |
3652 | mutex_unlock(&bp->drv_info_mutex); | |
3653 | } | |
3654 | ||
3655 | static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format) | |
3656 | { | |
3657 | u8 vals[4]; | |
3658 | int i = 0; | |
3659 | ||
3660 | if (bnx2x_format) { | |
3661 | i = sscanf(version, "1.%c%hhd.%hhd.%hhd", | |
3662 | &vals[0], &vals[1], &vals[2], &vals[3]); | |
3663 | if (i > 0) | |
3664 | vals[0] -= '0'; | |
3665 | } else { | |
3666 | i = sscanf(version, "%hhd.%hhd.%hhd.%hhd", | |
3667 | &vals[0], &vals[1], &vals[2], &vals[3]); | |
3668 | } | |
3669 | ||
3670 | while (i < 4) | |
3671 | vals[i++] = 0; | |
3672 | ||
3673 | return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3]; | |
3674 | } | |
3675 | ||
3676 | void bnx2x_update_mng_version(struct bnx2x *bp) | |
3677 | { | |
3678 | u32 iscsiver = DRV_VER_NOT_LOADED; | |
3679 | u32 fcoever = DRV_VER_NOT_LOADED; | |
3680 | u32 ethver = DRV_VER_NOT_LOADED; | |
3681 | int idx = BP_FW_MB_IDX(bp); | |
3682 | u8 *version; | |
3683 | ||
3684 | if (!SHMEM2_HAS(bp, func_os_drv_ver)) | |
3685 | return; | |
3686 | ||
3687 | mutex_lock(&bp->drv_info_mutex); | |
3688 | /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */ | |
3689 | if (bp->drv_info_mng_owner) | |
3690 | goto out; | |
3691 | ||
3692 | if (bp->state != BNX2X_STATE_OPEN) | |
3693 | goto out; | |
3694 | ||
3695 | /* Parse ethernet driver version */ | |
3696 | ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); | |
3697 | if (!CNIC_LOADED(bp)) | |
3698 | goto out; | |
3699 | ||
3700 | /* Try getting storage driver version via cnic */ | |
3701 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3702 | sizeof(union drv_info_to_mcp)); | |
3703 | bnx2x_drv_info_iscsi_stat(bp); | |
3704 | version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version; | |
3705 | iscsiver = bnx2x_update_mng_version_utility(version, false); | |
3706 | ||
3707 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3708 | sizeof(union drv_info_to_mcp)); | |
3709 | bnx2x_drv_info_fcoe_stat(bp); | |
3710 | version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version; | |
3711 | fcoever = bnx2x_update_mng_version_utility(version, false); | |
3712 | ||
3713 | out: | |
3714 | SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver); | |
3715 | SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver); | |
3716 | SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever); | |
3717 | ||
3718 | mutex_unlock(&bp->drv_info_mutex); | |
3719 | ||
3720 | DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n", | |
3721 | ethver, iscsiver, fcoever); | |
1d187b34 BW |
3722 | } |
3723 | ||
c48f350f YM |
3724 | void bnx2x_update_mfw_dump(struct bnx2x *bp) |
3725 | { | |
c48f350f YM |
3726 | u32 drv_ver; |
3727 | u32 valid_dump; | |
3728 | ||
3729 | if (!SHMEM2_HAS(bp, drv_info)) | |
3730 | return; | |
3731 | ||
a19a19de AB |
3732 | /* Update Driver load time, possibly broken in y2038 */ |
3733 | SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds()); | |
c48f350f YM |
3734 | |
3735 | drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); | |
3736 | SHMEM2_WR(bp, drv_info.drv_ver, drv_ver); | |
3737 | ||
3738 | SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM)); | |
3739 | ||
3740 | /* Check & notify On-Chip dump. */ | |
3741 | valid_dump = SHMEM2_RD(bp, drv_info.valid_dump); | |
3742 | ||
3743 | if (valid_dump & FIRST_DUMP_VALID) | |
3744 | DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n"); | |
3745 | ||
3746 | if (valid_dump & SECOND_DUMP_VALID) | |
3747 | DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n"); | |
3748 | } | |
3749 | ||
7609647e | 3750 | static void bnx2x_oem_event(struct bnx2x *bp, u32 event) |
523224a3 | 3751 | { |
7609647e YM |
3752 | u32 cmd_ok, cmd_fail; |
3753 | ||
3754 | /* sanity */ | |
3755 | if (event & DRV_STATUS_DCC_EVENT_MASK && | |
3756 | event & DRV_STATUS_OEM_EVENT_MASK) { | |
3757 | BNX2X_ERR("Received simultaneous events %08x\n", event); | |
3758 | return; | |
3759 | } | |
523224a3 | 3760 | |
7609647e YM |
3761 | if (event & DRV_STATUS_DCC_EVENT_MASK) { |
3762 | cmd_fail = DRV_MSG_CODE_DCC_FAILURE; | |
3763 | cmd_ok = DRV_MSG_CODE_DCC_OK; | |
3764 | } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ { | |
3765 | cmd_fail = DRV_MSG_CODE_OEM_FAILURE; | |
3766 | cmd_ok = DRV_MSG_CODE_OEM_OK; | |
3767 | } | |
523224a3 | 3768 | |
7609647e YM |
3769 | DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event); |
3770 | ||
3771 | if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF | | |
3772 | DRV_STATUS_OEM_DISABLE_ENABLE_PF)) { | |
3773 | /* This is the only place besides the function initialization | |
523224a3 DK |
3774 | * where the bp->flags can change so it is done without any |
3775 | * locks | |
3776 | */ | |
f2e0899f | 3777 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
51c1a580 | 3778 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
523224a3 DK |
3779 | bp->flags |= MF_FUNC_DIS; |
3780 | ||
3781 | bnx2x_e1h_disable(bp); | |
3782 | } else { | |
51c1a580 | 3783 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
523224a3 DK |
3784 | bp->flags &= ~MF_FUNC_DIS; |
3785 | ||
3786 | bnx2x_e1h_enable(bp); | |
3787 | } | |
7609647e YM |
3788 | event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF | |
3789 | DRV_STATUS_OEM_DISABLE_ENABLE_PF); | |
523224a3 | 3790 | } |
7609647e YM |
3791 | |
3792 | if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | | |
3793 | DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) { | |
0793f83f | 3794 | bnx2x_config_mf_bw(bp); |
7609647e YM |
3795 | event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | |
3796 | DRV_STATUS_OEM_BANDWIDTH_ALLOCATION); | |
523224a3 DK |
3797 | } |
3798 | ||
3799 | /* Report results to MCP */ | |
7609647e YM |
3800 | if (event) |
3801 | bnx2x_fw_command(bp, cmd_fail, 0); | |
523224a3 | 3802 | else |
7609647e | 3803 | bnx2x_fw_command(bp, cmd_ok, 0); |
523224a3 DK |
3804 | } |
3805 | ||
3806 | /* must be called under the spq lock */ | |
1191cb83 | 3807 | static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) |
523224a3 DK |
3808 | { |
3809 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3810 | ||
3811 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3812 | bp->spq_prod_bd = bp->spq; | |
3813 | bp->spq_prod_idx = 0; | |
51c1a580 | 3814 | DP(BNX2X_MSG_SP, "end of spq\n"); |
523224a3 DK |
3815 | } else { |
3816 | bp->spq_prod_bd++; | |
3817 | bp->spq_prod_idx++; | |
3818 | } | |
3819 | return next_spe; | |
3820 | } | |
3821 | ||
3822 | /* must be called under the spq lock */ | |
1191cb83 | 3823 | static void bnx2x_sp_prod_update(struct bnx2x *bp) |
28912902 MC |
3824 | { |
3825 | int func = BP_FUNC(bp); | |
3826 | ||
53e51e2f VZ |
3827 | /* |
3828 | * Make sure that BD data is updated before writing the producer: | |
3829 | * BD data is written to the memory, the producer is read from the | |
3830 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3831 | */ | |
3832 | mb(); | |
28912902 | 3833 | |
523224a3 | 3834 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3835 | bp->spq_prod_idx); |
28912902 MC |
3836 | mmiowb(); |
3837 | } | |
3838 | ||
619c5cb6 VZ |
3839 | /** |
3840 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3841 | * | |
3842 | * @cmd: command to check | |
3843 | * @cmd_type: command type | |
3844 | */ | |
1191cb83 | 3845 | static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) |
619c5cb6 VZ |
3846 | { |
3847 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3848 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3849 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3850 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3851 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3852 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3853 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3854 | return true; | |
3855 | else | |
3856 | return false; | |
619c5cb6 VZ |
3857 | } |
3858 | ||
619c5cb6 VZ |
3859 | /** |
3860 | * bnx2x_sp_post - place a single command on an SP ring | |
3861 | * | |
3862 | * @bp: driver handle | |
3863 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3864 | * @cid: SW CID the command is related to | |
3865 | * @data_hi: command private data address (high 32 bits) | |
3866 | * @data_lo: command private data address (low 32 bits) | |
3867 | * @cmd_type: command type (e.g. NONE, ETH) | |
3868 | * | |
3869 | * SP data is handled as if it's always an address pair, thus data fields are | |
3870 | * not swapped to little endian in upper functions. Instead this function swaps | |
3871 | * data as if it's two u32 fields. | |
3872 | */ | |
9f6c9258 | 3873 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3874 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3875 | { |
28912902 | 3876 | struct eth_spe *spe; |
523224a3 | 3877 | u16 type; |
619c5cb6 | 3878 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3879 | |
a2fbb9ea | 3880 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
3881 | if (unlikely(bp->panic)) { |
3882 | BNX2X_ERR("Can't post SP when there is panic\n"); | |
a2fbb9ea | 3883 | return -EIO; |
51c1a580 | 3884 | } |
a2fbb9ea ET |
3885 | #endif |
3886 | ||
34f80b04 | 3887 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3888 | |
6e30dd4e VZ |
3889 | if (common) { |
3890 | if (!atomic_read(&bp->eq_spq_left)) { | |
3891 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3892 | spin_unlock_bh(&bp->spq_lock); | |
3893 | bnx2x_panic(); | |
3894 | return -EBUSY; | |
3895 | } | |
3896 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3897 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3898 | spin_unlock_bh(&bp->spq_lock); | |
3899 | bnx2x_panic(); | |
3900 | return -EBUSY; | |
a2fbb9ea | 3901 | } |
f1410647 | 3902 | |
28912902 MC |
3903 | spe = bnx2x_sp_get_next(bp); |
3904 | ||
a2fbb9ea | 3905 | /* CID needs port number to be encoded int it */ |
28912902 | 3906 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3907 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3908 | HW_CID(bp, cid)); | |
523224a3 | 3909 | |
14a94ebd MK |
3910 | /* In some cases, type may already contain the func-id |
3911 | * mainly in SRIOV related use cases, so we add it here only | |
3912 | * if it's not already set. | |
3913 | */ | |
3914 | if (!(cmd_type & SPE_HDR_FUNCTION_ID)) { | |
3915 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & | |
3916 | SPE_HDR_CONN_TYPE; | |
3917 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & | |
3918 | SPE_HDR_FUNCTION_ID); | |
3919 | } else { | |
3920 | type = cmd_type; | |
3921 | } | |
a2fbb9ea | 3922 | |
523224a3 DK |
3923 | spe->hdr.type = cpu_to_le16(type); |
3924 | ||
3925 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3926 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3927 | ||
d6cae238 VZ |
3928 | /* |
3929 | * It's ok if the actual decrement is issued towards the memory | |
3930 | * somewhere between the spin_lock and spin_unlock. Thus no | |
16a5fd92 | 3931 | * more explicit memory barrier is needed. |
d6cae238 VZ |
3932 | */ |
3933 | if (common) | |
3934 | atomic_dec(&bp->eq_spq_left); | |
3935 | else | |
3936 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3937 | |
51c1a580 MS |
3938 | DP(BNX2X_MSG_SP, |
3939 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3940 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3941 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3942 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3943 | HW_CID(bp, cid), data_hi, data_lo, type, |
3944 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3945 | |
28912902 | 3946 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3947 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3948 | return 0; |
3949 | } | |
3950 | ||
3951 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3952 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3953 | { |
72fd0718 | 3954 | u32 j, val; |
34f80b04 | 3955 | int rc = 0; |
a2fbb9ea ET |
3956 | |
3957 | might_sleep(); | |
72fd0718 | 3958 | for (j = 0; j < 1000; j++) { |
3cdeec22 YM |
3959 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); |
3960 | val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); | |
3961 | if (val & MCPR_ACCESS_LOCK_LOCK) | |
a2fbb9ea ET |
3962 | break; |
3963 | ||
639d65b8 | 3964 | usleep_range(5000, 10000); |
a2fbb9ea | 3965 | } |
3cdeec22 | 3966 | if (!(val & MCPR_ACCESS_LOCK_LOCK)) { |
19680c48 | 3967 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3968 | rc = -EBUSY; |
3969 | } | |
3970 | ||
3971 | return rc; | |
3972 | } | |
3973 | ||
4a37fb66 YG |
3974 | /* release split MCP access lock register */ |
3975 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3976 | { |
3cdeec22 | 3977 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); |
a2fbb9ea ET |
3978 | } |
3979 | ||
523224a3 DK |
3980 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3981 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3982 | ||
1191cb83 | 3983 | static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
a2fbb9ea | 3984 | { |
523224a3 | 3985 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3986 | u16 rc = 0; |
3987 | ||
3988 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3989 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3990 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3991 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3992 | } |
523224a3 DK |
3993 | |
3994 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3995 | bp->def_idx = def_sb->sp_sb.running_index; | |
3996 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3997 | } |
523224a3 | 3998 | |
16a5fd92 | 3999 | /* Do not reorder: indices reading should complete before handling */ |
523224a3 | 4000 | barrier(); |
a2fbb9ea ET |
4001 | return rc; |
4002 | } | |
4003 | ||
4004 | /* | |
4005 | * slow path service functions | |
4006 | */ | |
4007 | ||
4008 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
4009 | { | |
34f80b04 | 4010 | int port = BP_PORT(bp); |
a2fbb9ea ET |
4011 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
4012 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
4013 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
4014 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 4015 | u32 aeu_mask; |
87942b46 | 4016 | u32 nig_mask = 0; |
f2e0899f | 4017 | u32 reg_addr; |
a2fbb9ea | 4018 | |
a2fbb9ea ET |
4019 | if (bp->attn_state & asserted) |
4020 | BNX2X_ERR("IGU ERROR\n"); | |
4021 | ||
3fcaf2e5 EG |
4022 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4023 | aeu_mask = REG_RD(bp, aeu_addr); | |
4024 | ||
a2fbb9ea | 4025 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 4026 | aeu_mask, asserted); |
72fd0718 | 4027 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 4028 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4029 | |
3fcaf2e5 EG |
4030 | REG_WR(bp, aeu_addr, aeu_mask); |
4031 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 4032 | |
3fcaf2e5 | 4033 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 4034 | bp->attn_state |= asserted; |
3fcaf2e5 | 4035 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
4036 | |
4037 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
4038 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 4039 | |
a5e9a7cf EG |
4040 | bnx2x_acquire_phy_lock(bp); |
4041 | ||
877e9aa4 | 4042 | /* save nig interrupt mask */ |
87942b46 | 4043 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 4044 | |
361c391e YR |
4045 | /* If nig_mask is not set, no need to call the update |
4046 | * function. | |
4047 | */ | |
4048 | if (nig_mask) { | |
4049 | REG_WR(bp, nig_int_mask_addr, 0); | |
4050 | ||
4051 | bnx2x_link_attn(bp); | |
4052 | } | |
a2fbb9ea ET |
4053 | |
4054 | /* handle unicore attn? */ | |
4055 | } | |
4056 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
4057 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
4058 | ||
4059 | if (asserted & GPIO_2_FUNC) | |
4060 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
4061 | ||
4062 | if (asserted & GPIO_3_FUNC) | |
4063 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
4064 | ||
4065 | if (asserted & GPIO_4_FUNC) | |
4066 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
4067 | ||
4068 | if (port == 0) { | |
4069 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
4070 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
4071 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
4072 | } | |
4073 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
4074 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
4075 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
4076 | } | |
4077 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
4078 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
4079 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
4080 | } | |
4081 | } else { | |
4082 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
4083 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
4084 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
4085 | } | |
4086 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
4087 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
4088 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
4089 | } | |
4090 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
4091 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
4092 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
4093 | } | |
4094 | } | |
4095 | ||
4096 | } /* if hardwired */ | |
4097 | ||
f2e0899f DK |
4098 | if (bp->common.int_block == INT_BLOCK_HC) |
4099 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4100 | COMMAND_REG_ATTN_BITS_SET); | |
4101 | else | |
4102 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
4103 | ||
4104 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
4105 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
4106 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
4107 | |
4108 | /* now set back the mask */ | |
a5e9a7cf | 4109 | if (asserted & ATTN_NIG_FOR_FUNC) { |
27c1151c YR |
4110 | /* Verify that IGU ack through BAR was written before restoring |
4111 | * NIG mask. This loop should exit after 2-3 iterations max. | |
4112 | */ | |
4113 | if (bp->common.int_block != INT_BLOCK_HC) { | |
4114 | u32 cnt = 0, igu_acked; | |
4115 | do { | |
4116 | igu_acked = REG_RD(bp, | |
4117 | IGU_REG_ATTENTION_ACK_BITS); | |
4118 | } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && | |
4119 | (++cnt < MAX_IGU_ATTN_ACK_TO)); | |
4120 | if (!igu_acked) | |
4121 | DP(NETIF_MSG_HW, | |
4122 | "Failed to verify IGU ack on time\n"); | |
4123 | barrier(); | |
4124 | } | |
87942b46 | 4125 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
4126 | bnx2x_release_phy_lock(bp); |
4127 | } | |
a2fbb9ea ET |
4128 | } |
4129 | ||
1191cb83 | 4130 | static void bnx2x_fan_failure(struct bnx2x *bp) |
fd4ef40d EG |
4131 | { |
4132 | int port = BP_PORT(bp); | |
b7737c9b | 4133 | u32 ext_phy_config; |
fd4ef40d | 4134 | /* mark the failure */ |
b7737c9b YR |
4135 | ext_phy_config = |
4136 | SHMEM_RD(bp, | |
4137 | dev_info.port_hw_config[port].external_phy_config); | |
4138 | ||
4139 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
4140 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 4141 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 4142 | ext_phy_config); |
fd4ef40d EG |
4143 | |
4144 | /* log the failure */ | |
51c1a580 MS |
4145 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
4146 | "Please contact OEM Support for assistance\n"); | |
8304859a | 4147 | |
16a5fd92 | 4148 | /* Schedule device reset (unload) |
8304859a AE |
4149 | * This is due to some boards consuming sufficient power when driver is |
4150 | * up to overheat if fan fails. | |
4151 | */ | |
230bb0f3 | 4152 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0); |
fd4ef40d | 4153 | } |
ab6ad5a4 | 4154 | |
1191cb83 | 4155 | static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 4156 | { |
34f80b04 | 4157 | int port = BP_PORT(bp); |
877e9aa4 | 4158 | int reg_offset; |
d90d96ba | 4159 | u32 val; |
877e9aa4 | 4160 | |
34f80b04 EG |
4161 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
4162 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 4163 | |
34f80b04 | 4164 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
4165 | |
4166 | val = REG_RD(bp, reg_offset); | |
4167 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
4168 | REG_WR(bp, reg_offset, val); | |
4169 | ||
4170 | BNX2X_ERR("SPIO5 hw attention\n"); | |
4171 | ||
fd4ef40d | 4172 | /* Fan failure attention */ |
d90d96ba | 4173 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 4174 | bnx2x_fan_failure(bp); |
877e9aa4 | 4175 | } |
34f80b04 | 4176 | |
3deb8167 | 4177 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
4178 | bnx2x_acquire_phy_lock(bp); |
4179 | bnx2x_handle_module_detect_int(&bp->link_params); | |
4180 | bnx2x_release_phy_lock(bp); | |
4181 | } | |
4182 | ||
a8919661 | 4183 | if (attn & HW_INTERRUPT_ASSERT_SET_0) { |
34f80b04 EG |
4184 | |
4185 | val = REG_RD(bp, reg_offset); | |
a8919661 | 4186 | val &= ~(attn & HW_INTERRUPT_ASSERT_SET_0); |
34f80b04 EG |
4187 | REG_WR(bp, reg_offset, val); |
4188 | ||
4189 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
a8919661 | 4190 | (u32)(attn & HW_INTERRUPT_ASSERT_SET_0)); |
34f80b04 EG |
4191 | bnx2x_panic(); |
4192 | } | |
877e9aa4 ET |
4193 | } |
4194 | ||
1191cb83 | 4195 | static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
4196 | { |
4197 | u32 val; | |
4198 | ||
0626b899 | 4199 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
4200 | |
4201 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
4202 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
4203 | /* DORQ discard attention */ | |
4204 | if (val & 0x2) | |
4205 | BNX2X_ERR("FATAL error from DORQ\n"); | |
4206 | } | |
34f80b04 | 4207 | |
a8919661 | 4208 | if (attn & HW_INTERRUPT_ASSERT_SET_1) { |
34f80b04 EG |
4209 | |
4210 | int port = BP_PORT(bp); | |
4211 | int reg_offset; | |
4212 | ||
4213 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
4214 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
4215 | ||
4216 | val = REG_RD(bp, reg_offset); | |
a8919661 | 4217 | val &= ~(attn & HW_INTERRUPT_ASSERT_SET_1); |
34f80b04 EG |
4218 | REG_WR(bp, reg_offset, val); |
4219 | ||
4220 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
a8919661 | 4221 | (u32)(attn & HW_INTERRUPT_ASSERT_SET_1)); |
34f80b04 EG |
4222 | bnx2x_panic(); |
4223 | } | |
877e9aa4 ET |
4224 | } |
4225 | ||
1191cb83 | 4226 | static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
4227 | { |
4228 | u32 val; | |
4229 | ||
4230 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
4231 | ||
4232 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
4233 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
4234 | /* CFC error attention */ | |
4235 | if (val & 0x2) | |
4236 | BNX2X_ERR("FATAL error from CFC\n"); | |
4237 | } | |
4238 | ||
4239 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 4240 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 4241 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
4242 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
4243 | if (val & 0x18000) | |
4244 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
4245 | |
4246 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
4247 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
4248 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
4249 | } | |
877e9aa4 | 4250 | } |
34f80b04 | 4251 | |
a8919661 | 4252 | if (attn & HW_INTERRUPT_ASSERT_SET_2) { |
34f80b04 EG |
4253 | |
4254 | int port = BP_PORT(bp); | |
4255 | int reg_offset; | |
4256 | ||
4257 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
4258 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
4259 | ||
4260 | val = REG_RD(bp, reg_offset); | |
a8919661 | 4261 | val &= ~(attn & HW_INTERRUPT_ASSERT_SET_2); |
34f80b04 EG |
4262 | REG_WR(bp, reg_offset, val); |
4263 | ||
4264 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
a8919661 | 4265 | (u32)(attn & HW_INTERRUPT_ASSERT_SET_2)); |
34f80b04 EG |
4266 | bnx2x_panic(); |
4267 | } | |
877e9aa4 ET |
4268 | } |
4269 | ||
1191cb83 | 4270 | static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) |
877e9aa4 | 4271 | { |
34f80b04 EG |
4272 | u32 val; |
4273 | ||
877e9aa4 ET |
4274 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
4275 | ||
34f80b04 EG |
4276 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
4277 | int func = BP_FUNC(bp); | |
4278 | ||
4279 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
a3348722 | 4280 | bnx2x_read_mf_cfg(bp); |
f2e0899f DK |
4281 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
4282 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
4283 | val = SHMEM_RD(bp, | |
4284 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
7609647e YM |
4285 | |
4286 | if (val & (DRV_STATUS_DCC_EVENT_MASK | | |
4287 | DRV_STATUS_OEM_EVENT_MASK)) | |
4288 | bnx2x_oem_event(bp, | |
4289 | (val & (DRV_STATUS_DCC_EVENT_MASK | | |
4290 | DRV_STATUS_OEM_EVENT_MASK))); | |
0793f83f DK |
4291 | |
4292 | if (val & DRV_STATUS_SET_MF_BW) | |
4293 | bnx2x_set_mf_bw(bp); | |
4294 | ||
1d187b34 BW |
4295 | if (val & DRV_STATUS_DRV_INFO_REQ) |
4296 | bnx2x_handle_drv_info_req(bp); | |
d16132ce AE |
4297 | |
4298 | if (val & DRV_STATUS_VF_DISABLED) | |
370d4a26 YM |
4299 | bnx2x_schedule_iov_task(bp, |
4300 | BNX2X_IOV_HANDLE_FLR); | |
d16132ce | 4301 | |
2691d51d | 4302 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
4303 | bnx2x_pmf_update(bp); |
4304 | ||
e4901dde | 4305 | if (bp->port.pmf && |
785b9b1a SR |
4306 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
4307 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
4308 | /* start dcbx state machine */ |
4309 | bnx2x_dcbx_set_params(bp, | |
4310 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
a3348722 BW |
4311 | if (val & DRV_STATUS_AFEX_EVENT_MASK) |
4312 | bnx2x_handle_afex_cmd(bp, | |
4313 | val & DRV_STATUS_AFEX_EVENT_MASK); | |
c8c60d88 YM |
4314 | if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) |
4315 | bnx2x_handle_eee_event(bp); | |
7609647e YM |
4316 | |
4317 | if (val & DRV_STATUS_OEM_UPDATE_SVID) | |
ebbdb4b5 SRK |
4318 | bnx2x_schedule_sp_rtnl(bp, |
4319 | BNX2X_SP_RTNL_UPDATE_SVID, 0); | |
7609647e | 4320 | |
3deb8167 YR |
4321 | if (bp->link_vars.periodic_flags & |
4322 | PERIODIC_FLAGS_LINK_EVENT) { | |
4323 | /* sync with link */ | |
4324 | bnx2x_acquire_phy_lock(bp); | |
4325 | bp->link_vars.periodic_flags &= | |
4326 | ~PERIODIC_FLAGS_LINK_EVENT; | |
4327 | bnx2x_release_phy_lock(bp); | |
4328 | if (IS_MF(bp)) | |
4329 | bnx2x_link_sync_notify(bp); | |
4330 | bnx2x_link_report(bp); | |
4331 | } | |
4332 | /* Always call it here: bnx2x_link_report() will | |
4333 | * prevent the link indication duplication. | |
4334 | */ | |
4335 | bnx2x__link_status_update(bp); | |
34f80b04 | 4336 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
4337 | |
4338 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 4339 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
4340 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
4341 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
4342 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
4343 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
4344 | bnx2x_panic(); | |
4345 | ||
4346 | } else if (attn & BNX2X_MCP_ASSERT) { | |
4347 | ||
4348 | BNX2X_ERR("MCP assert!\n"); | |
4349 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 4350 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
4351 | |
4352 | } else | |
4353 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
4354 | } | |
4355 | ||
4356 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
4357 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
4358 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
4359 | val = CHIP_IS_E1(bp) ? 0 : |
4360 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
4361 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
4362 | } | |
4363 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
4364 | val = CHIP_IS_E1(bp) ? 0 : |
4365 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
4366 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
4367 | } | |
877e9aa4 | 4368 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
4369 | } |
4370 | } | |
4371 | ||
c9ee9206 VZ |
4372 | /* |
4373 | * Bits map: | |
4374 | * 0-7 - Engine0 load counter. | |
4375 | * 8-15 - Engine1 load counter. | |
4376 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
4377 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
4378 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
4379 | * on the engine | |
4380 | * 19 - Engine1 ONE_IS_LOADED. | |
4381 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
4382 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
4383 | * just the one belonging to its engine). | |
4384 | * | |
4385 | */ | |
4386 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
4387 | ||
4388 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
4389 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
4390 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
4391 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
4392 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
4393 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
4394 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
4395 | ||
4396 | /* | |
4397 | * Set the GLOBAL_RESET bit. | |
4398 | * | |
4399 | * Should be run under rtnl lock | |
4400 | */ | |
4401 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
4402 | { | |
f16da43b AE |
4403 | u32 val; |
4404 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4405 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4406 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
f16da43b | 4407 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 VZ |
4408 | } |
4409 | ||
4410 | /* | |
4411 | * Clear the GLOBAL_RESET bit. | |
4412 | * | |
4413 | * Should be run under rtnl lock | |
4414 | */ | |
1191cb83 | 4415 | static void bnx2x_clear_reset_global(struct bnx2x *bp) |
c9ee9206 | 4416 | { |
f16da43b AE |
4417 | u32 val; |
4418 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4419 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4420 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
f16da43b | 4421 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 | 4422 | } |
f85582f8 | 4423 | |
72fd0718 | 4424 | /* |
c9ee9206 VZ |
4425 | * Checks the GLOBAL_RESET bit. |
4426 | * | |
72fd0718 VZ |
4427 | * should be run under rtnl lock |
4428 | */ | |
1191cb83 | 4429 | static bool bnx2x_reset_is_global(struct bnx2x *bp) |
c9ee9206 | 4430 | { |
3cdeec22 | 4431 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
c9ee9206 VZ |
4432 | |
4433 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
4434 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
4435 | } | |
4436 | ||
4437 | /* | |
4438 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
4439 | * | |
4440 | * Should be run under rtnl lock | |
4441 | */ | |
1191cb83 | 4442 | static void bnx2x_set_reset_done(struct bnx2x *bp) |
72fd0718 | 4443 | { |
f16da43b | 4444 | u32 val; |
c9ee9206 VZ |
4445 | u32 bit = BP_PATH(bp) ? |
4446 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4447 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4448 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4449 | |
4450 | /* Clear the bit */ | |
4451 | val &= ~bit; | |
4452 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4453 | |
4454 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
72fd0718 VZ |
4455 | } |
4456 | ||
4457 | /* | |
c9ee9206 VZ |
4458 | * Set RESET_IN_PROGRESS for the current engine. |
4459 | * | |
72fd0718 VZ |
4460 | * should be run under rtnl lock |
4461 | */ | |
c9ee9206 | 4462 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 4463 | { |
f16da43b | 4464 | u32 val; |
c9ee9206 VZ |
4465 | u32 bit = BP_PATH(bp) ? |
4466 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4467 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4468 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4469 | |
4470 | /* Set the bit */ | |
4471 | val |= bit; | |
4472 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4473 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4474 | } |
4475 | ||
4476 | /* | |
c9ee9206 | 4477 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
4478 | * should be run under rtnl lock |
4479 | */ | |
c9ee9206 | 4480 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 4481 | { |
3cdeec22 | 4482 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
c9ee9206 VZ |
4483 | u32 bit = engine ? |
4484 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
4485 | ||
4486 | /* return false if bit is set */ | |
4487 | return (val & bit) ? false : true; | |
72fd0718 VZ |
4488 | } |
4489 | ||
4490 | /* | |
889b9af3 | 4491 | * set pf load for the current pf. |
c9ee9206 | 4492 | * |
72fd0718 VZ |
4493 | * should be run under rtnl lock |
4494 | */ | |
889b9af3 | 4495 | void bnx2x_set_pf_load(struct bnx2x *bp) |
72fd0718 | 4496 | { |
f16da43b | 4497 | u32 val1, val; |
c9ee9206 VZ |
4498 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4499 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4500 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4501 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4502 | |
f16da43b AE |
4503 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4504 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4505 | ||
51c1a580 | 4506 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4507 | |
c9ee9206 VZ |
4508 | /* get the current counter value */ |
4509 | val1 = (val & mask) >> shift; | |
4510 | ||
889b9af3 AE |
4511 | /* set bit of that PF */ |
4512 | val1 |= (1 << bp->pf_num); | |
c9ee9206 VZ |
4513 | |
4514 | /* clear the old value */ | |
4515 | val &= ~mask; | |
4516 | ||
4517 | /* set the new one */ | |
4518 | val |= ((val1 << shift) & mask); | |
4519 | ||
4520 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4521 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4522 | } |
4523 | ||
c9ee9206 | 4524 | /** |
889b9af3 | 4525 | * bnx2x_clear_pf_load - clear pf load mark |
c9ee9206 VZ |
4526 | * |
4527 | * @bp: driver handle | |
4528 | * | |
4529 | * Should be run under rtnl lock. | |
4530 | * Decrements the load counter for the current engine. Returns | |
889b9af3 | 4531 | * whether other functions are still loaded |
72fd0718 | 4532 | */ |
889b9af3 | 4533 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
72fd0718 | 4534 | { |
f16da43b | 4535 | u32 val1, val; |
c9ee9206 VZ |
4536 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4537 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4538 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4539 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4540 | |
f16da43b AE |
4541 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4542 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
51c1a580 | 4543 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4544 | |
c9ee9206 VZ |
4545 | /* get the current counter value */ |
4546 | val1 = (val & mask) >> shift; | |
4547 | ||
889b9af3 AE |
4548 | /* clear bit of that PF */ |
4549 | val1 &= ~(1 << bp->pf_num); | |
c9ee9206 VZ |
4550 | |
4551 | /* clear the old value */ | |
4552 | val &= ~mask; | |
4553 | ||
4554 | /* set the new one */ | |
4555 | val |= ((val1 << shift) & mask); | |
4556 | ||
4557 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4558 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4559 | return val1 != 0; | |
72fd0718 VZ |
4560 | } |
4561 | ||
4562 | /* | |
889b9af3 | 4563 | * Read the load status for the current engine. |
c9ee9206 | 4564 | * |
72fd0718 VZ |
4565 | * should be run under rtnl lock |
4566 | */ | |
1191cb83 | 4567 | static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
72fd0718 | 4568 | { |
c9ee9206 VZ |
4569 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
4570 | BNX2X_PATH0_LOAD_CNT_MASK); | |
4571 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4572 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
4573 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4574 | ||
51c1a580 | 4575 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
c9ee9206 VZ |
4576 | |
4577 | val = (val & mask) >> shift; | |
4578 | ||
51c1a580 MS |
4579 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
4580 | engine, val); | |
c9ee9206 | 4581 | |
889b9af3 | 4582 | return val != 0; |
72fd0718 VZ |
4583 | } |
4584 | ||
6bf07b8e YM |
4585 | static void _print_parity(struct bnx2x *bp, u32 reg) |
4586 | { | |
4587 | pr_cont(" [0x%08x] ", REG_RD(bp, reg)); | |
4588 | } | |
4589 | ||
1191cb83 | 4590 | static void _print_next_block(int idx, const char *blk) |
72fd0718 | 4591 | { |
f1deab50 | 4592 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
4593 | } |
4594 | ||
4293b9f5 DK |
4595 | static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, |
4596 | int *par_num, bool print) | |
72fd0718 | 4597 | { |
4293b9f5 DK |
4598 | u32 cur_bit; |
4599 | bool res; | |
4600 | int i; | |
4601 | ||
4602 | res = false; | |
4603 | ||
72fd0718 | 4604 | for (i = 0; sig; i++) { |
4293b9f5 | 4605 | cur_bit = (0x1UL << i); |
72fd0718 | 4606 | if (sig & cur_bit) { |
4293b9f5 DK |
4607 | res |= true; /* Each bit is real error! */ |
4608 | ||
4609 | if (print) { | |
4610 | switch (cur_bit) { | |
4611 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
4612 | _print_next_block((*par_num)++, "BRB"); | |
6bf07b8e YM |
4613 | _print_parity(bp, |
4614 | BRB1_REG_BRB1_PRTY_STS); | |
4293b9f5 DK |
4615 | break; |
4616 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
4617 | _print_next_block((*par_num)++, | |
4618 | "PARSER"); | |
6bf07b8e | 4619 | _print_parity(bp, PRS_REG_PRS_PRTY_STS); |
4293b9f5 DK |
4620 | break; |
4621 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
4622 | _print_next_block((*par_num)++, "TSDM"); | |
6bf07b8e YM |
4623 | _print_parity(bp, |
4624 | TSDM_REG_TSDM_PRTY_STS); | |
4293b9f5 DK |
4625 | break; |
4626 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
4627 | _print_next_block((*par_num)++, | |
c9ee9206 | 4628 | "SEARCHER"); |
6bf07b8e | 4629 | _print_parity(bp, SRC_REG_SRC_PRTY_STS); |
4293b9f5 DK |
4630 | break; |
4631 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
4632 | _print_next_block((*par_num)++, "TCM"); | |
4633 | _print_parity(bp, TCM_REG_TCM_PRTY_STS); | |
4634 | break; | |
4635 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
4636 | _print_next_block((*par_num)++, | |
4637 | "TSEMI"); | |
6bf07b8e YM |
4638 | _print_parity(bp, |
4639 | TSEM_REG_TSEM_PRTY_STS_0); | |
4640 | _print_parity(bp, | |
4641 | TSEM_REG_TSEM_PRTY_STS_1); | |
4293b9f5 DK |
4642 | break; |
4643 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
4644 | _print_next_block((*par_num)++, "XPB"); | |
6bf07b8e YM |
4645 | _print_parity(bp, GRCBASE_XPB + |
4646 | PB_REG_PB_PRTY_STS); | |
4293b9f5 | 4647 | break; |
6bf07b8e | 4648 | } |
72fd0718 VZ |
4649 | } |
4650 | ||
4651 | /* Clear the bit */ | |
4652 | sig &= ~cur_bit; | |
4653 | } | |
4654 | } | |
4655 | ||
4293b9f5 | 4656 | return res; |
72fd0718 VZ |
4657 | } |
4658 | ||
4293b9f5 DK |
4659 | static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, |
4660 | int *par_num, bool *global, | |
6bf07b8e | 4661 | bool print) |
72fd0718 | 4662 | { |
4293b9f5 DK |
4663 | u32 cur_bit; |
4664 | bool res; | |
4665 | int i; | |
4666 | ||
4667 | res = false; | |
4668 | ||
72fd0718 | 4669 | for (i = 0; sig; i++) { |
4293b9f5 | 4670 | cur_bit = (0x1UL << i); |
72fd0718 | 4671 | if (sig & cur_bit) { |
4293b9f5 | 4672 | res |= true; /* Each bit is real error! */ |
72fd0718 | 4673 | switch (cur_bit) { |
c9ee9206 | 4674 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
6bf07b8e | 4675 | if (print) { |
4293b9f5 | 4676 | _print_next_block((*par_num)++, "PBF"); |
6bf07b8e YM |
4677 | _print_parity(bp, PBF_REG_PBF_PRTY_STS); |
4678 | } | |
72fd0718 VZ |
4679 | break; |
4680 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
6bf07b8e | 4681 | if (print) { |
4293b9f5 | 4682 | _print_next_block((*par_num)++, "QM"); |
6bf07b8e YM |
4683 | _print_parity(bp, QM_REG_QM_PRTY_STS); |
4684 | } | |
c9ee9206 VZ |
4685 | break; |
4686 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
6bf07b8e | 4687 | if (print) { |
4293b9f5 | 4688 | _print_next_block((*par_num)++, "TM"); |
6bf07b8e YM |
4689 | _print_parity(bp, TM_REG_TM_PRTY_STS); |
4690 | } | |
72fd0718 VZ |
4691 | break; |
4692 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
6bf07b8e | 4693 | if (print) { |
4293b9f5 | 4694 | _print_next_block((*par_num)++, "XSDM"); |
6bf07b8e YM |
4695 | _print_parity(bp, |
4696 | XSDM_REG_XSDM_PRTY_STS); | |
4697 | } | |
c9ee9206 VZ |
4698 | break; |
4699 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
6bf07b8e | 4700 | if (print) { |
4293b9f5 | 4701 | _print_next_block((*par_num)++, "XCM"); |
6bf07b8e YM |
4702 | _print_parity(bp, XCM_REG_XCM_PRTY_STS); |
4703 | } | |
72fd0718 VZ |
4704 | break; |
4705 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
6bf07b8e | 4706 | if (print) { |
4293b9f5 DK |
4707 | _print_next_block((*par_num)++, |
4708 | "XSEMI"); | |
6bf07b8e YM |
4709 | _print_parity(bp, |
4710 | XSEM_REG_XSEM_PRTY_STS_0); | |
4711 | _print_parity(bp, | |
4712 | XSEM_REG_XSEM_PRTY_STS_1); | |
4713 | } | |
72fd0718 VZ |
4714 | break; |
4715 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
6bf07b8e | 4716 | if (print) { |
4293b9f5 | 4717 | _print_next_block((*par_num)++, |
c9ee9206 | 4718 | "DOORBELLQ"); |
6bf07b8e YM |
4719 | _print_parity(bp, |
4720 | DORQ_REG_DORQ_PRTY_STS); | |
4721 | } | |
c9ee9206 VZ |
4722 | break; |
4723 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
6bf07b8e | 4724 | if (print) { |
4293b9f5 | 4725 | _print_next_block((*par_num)++, "NIG"); |
6bf07b8e YM |
4726 | if (CHIP_IS_E1x(bp)) { |
4727 | _print_parity(bp, | |
4728 | NIG_REG_NIG_PRTY_STS); | |
4729 | } else { | |
4730 | _print_parity(bp, | |
4731 | NIG_REG_NIG_PRTY_STS_0); | |
4732 | _print_parity(bp, | |
4733 | NIG_REG_NIG_PRTY_STS_1); | |
4734 | } | |
4735 | } | |
72fd0718 VZ |
4736 | break; |
4737 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 | 4738 | if (print) |
4293b9f5 | 4739 | _print_next_block((*par_num)++, |
c9ee9206 VZ |
4740 | "VAUX PCI CORE"); |
4741 | *global = true; | |
72fd0718 VZ |
4742 | break; |
4743 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
6bf07b8e | 4744 | if (print) { |
4293b9f5 DK |
4745 | _print_next_block((*par_num)++, |
4746 | "DEBUG"); | |
6bf07b8e YM |
4747 | _print_parity(bp, DBG_REG_DBG_PRTY_STS); |
4748 | } | |
72fd0718 VZ |
4749 | break; |
4750 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
6bf07b8e | 4751 | if (print) { |
4293b9f5 | 4752 | _print_next_block((*par_num)++, "USDM"); |
6bf07b8e YM |
4753 | _print_parity(bp, |
4754 | USDM_REG_USDM_PRTY_STS); | |
4755 | } | |
72fd0718 | 4756 | break; |
8736c826 | 4757 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
6bf07b8e | 4758 | if (print) { |
4293b9f5 | 4759 | _print_next_block((*par_num)++, "UCM"); |
6bf07b8e YM |
4760 | _print_parity(bp, UCM_REG_UCM_PRTY_STS); |
4761 | } | |
8736c826 | 4762 | break; |
72fd0718 | 4763 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
6bf07b8e | 4764 | if (print) { |
4293b9f5 DK |
4765 | _print_next_block((*par_num)++, |
4766 | "USEMI"); | |
6bf07b8e YM |
4767 | _print_parity(bp, |
4768 | USEM_REG_USEM_PRTY_STS_0); | |
4769 | _print_parity(bp, | |
4770 | USEM_REG_USEM_PRTY_STS_1); | |
4771 | } | |
72fd0718 VZ |
4772 | break; |
4773 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
6bf07b8e | 4774 | if (print) { |
4293b9f5 | 4775 | _print_next_block((*par_num)++, "UPB"); |
6bf07b8e YM |
4776 | _print_parity(bp, GRCBASE_UPB + |
4777 | PB_REG_PB_PRTY_STS); | |
4778 | } | |
72fd0718 VZ |
4779 | break; |
4780 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
6bf07b8e | 4781 | if (print) { |
4293b9f5 | 4782 | _print_next_block((*par_num)++, "CSDM"); |
6bf07b8e YM |
4783 | _print_parity(bp, |
4784 | CSDM_REG_CSDM_PRTY_STS); | |
4785 | } | |
72fd0718 | 4786 | break; |
8736c826 | 4787 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
6bf07b8e | 4788 | if (print) { |
4293b9f5 | 4789 | _print_next_block((*par_num)++, "CCM"); |
6bf07b8e YM |
4790 | _print_parity(bp, CCM_REG_CCM_PRTY_STS); |
4791 | } | |
8736c826 | 4792 | break; |
72fd0718 VZ |
4793 | } |
4794 | ||
4795 | /* Clear the bit */ | |
4796 | sig &= ~cur_bit; | |
4797 | } | |
4798 | } | |
4799 | ||
4293b9f5 | 4800 | return res; |
72fd0718 VZ |
4801 | } |
4802 | ||
4293b9f5 DK |
4803 | static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, |
4804 | int *par_num, bool print) | |
72fd0718 | 4805 | { |
4293b9f5 DK |
4806 | u32 cur_bit; |
4807 | bool res; | |
4808 | int i; | |
4809 | ||
4810 | res = false; | |
4811 | ||
72fd0718 | 4812 | for (i = 0; sig; i++) { |
4293b9f5 | 4813 | cur_bit = (0x1UL << i); |
72fd0718 | 4814 | if (sig & cur_bit) { |
0c23ad37 | 4815 | res = true; /* Each bit is real error! */ |
4293b9f5 DK |
4816 | if (print) { |
4817 | switch (cur_bit) { | |
4818 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
4819 | _print_next_block((*par_num)++, | |
4820 | "CSEMI"); | |
6bf07b8e YM |
4821 | _print_parity(bp, |
4822 | CSEM_REG_CSEM_PRTY_STS_0); | |
4823 | _print_parity(bp, | |
4824 | CSEM_REG_CSEM_PRTY_STS_1); | |
4293b9f5 DK |
4825 | break; |
4826 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
4827 | _print_next_block((*par_num)++, "PXP"); | |
6bf07b8e YM |
4828 | _print_parity(bp, PXP_REG_PXP_PRTY_STS); |
4829 | _print_parity(bp, | |
4830 | PXP2_REG_PXP2_PRTY_STS_0); | |
4831 | _print_parity(bp, | |
4832 | PXP2_REG_PXP2_PRTY_STS_1); | |
4293b9f5 DK |
4833 | break; |
4834 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
4835 | _print_next_block((*par_num)++, | |
4836 | "PXPPCICLOCKCLIENT"); | |
4837 | break; | |
4838 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
4839 | _print_next_block((*par_num)++, "CFC"); | |
6bf07b8e YM |
4840 | _print_parity(bp, |
4841 | CFC_REG_CFC_PRTY_STS); | |
4293b9f5 DK |
4842 | break; |
4843 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
4844 | _print_next_block((*par_num)++, "CDU"); | |
6bf07b8e | 4845 | _print_parity(bp, CDU_REG_CDU_PRTY_STS); |
4293b9f5 DK |
4846 | break; |
4847 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
4848 | _print_next_block((*par_num)++, "DMAE"); | |
6bf07b8e YM |
4849 | _print_parity(bp, |
4850 | DMAE_REG_DMAE_PRTY_STS); | |
4293b9f5 DK |
4851 | break; |
4852 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
4853 | _print_next_block((*par_num)++, "IGU"); | |
6bf07b8e YM |
4854 | if (CHIP_IS_E1x(bp)) |
4855 | _print_parity(bp, | |
4856 | HC_REG_HC_PRTY_STS); | |
4857 | else | |
4858 | _print_parity(bp, | |
4859 | IGU_REG_IGU_PRTY_STS); | |
4293b9f5 DK |
4860 | break; |
4861 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
4862 | _print_next_block((*par_num)++, "MISC"); | |
6bf07b8e YM |
4863 | _print_parity(bp, |
4864 | MISC_REG_MISC_PRTY_STS); | |
4293b9f5 | 4865 | break; |
6bf07b8e | 4866 | } |
72fd0718 VZ |
4867 | } |
4868 | ||
4869 | /* Clear the bit */ | |
4870 | sig &= ~cur_bit; | |
4871 | } | |
4872 | } | |
4873 | ||
4293b9f5 | 4874 | return res; |
72fd0718 VZ |
4875 | } |
4876 | ||
4293b9f5 DK |
4877 | static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig, |
4878 | int *par_num, bool *global, | |
4879 | bool print) | |
72fd0718 | 4880 | { |
4293b9f5 DK |
4881 | bool res = false; |
4882 | u32 cur_bit; | |
4883 | int i; | |
4884 | ||
72fd0718 | 4885 | for (i = 0; sig; i++) { |
4293b9f5 | 4886 | cur_bit = (0x1UL << i); |
72fd0718 VZ |
4887 | if (sig & cur_bit) { |
4888 | switch (cur_bit) { | |
4889 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 | 4890 | if (print) |
4293b9f5 DK |
4891 | _print_next_block((*par_num)++, |
4892 | "MCP ROM"); | |
c9ee9206 | 4893 | *global = true; |
0c23ad37 | 4894 | res = true; |
72fd0718 VZ |
4895 | break; |
4896 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 | 4897 | if (print) |
4293b9f5 | 4898 | _print_next_block((*par_num)++, |
c9ee9206 VZ |
4899 | "MCP UMP RX"); |
4900 | *global = true; | |
0c23ad37 | 4901 | res = true; |
72fd0718 VZ |
4902 | break; |
4903 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 | 4904 | if (print) |
4293b9f5 | 4905 | _print_next_block((*par_num)++, |
c9ee9206 VZ |
4906 | "MCP UMP TX"); |
4907 | *global = true; | |
0c23ad37 | 4908 | res = true; |
72fd0718 VZ |
4909 | break; |
4910 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
ad6afbe9 | 4911 | (*par_num)++; |
4293b9f5 DK |
4912 | /* clear latched SCPAD PATIRY from MCP */ |
4913 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, | |
4914 | 1UL << 10); | |
72fd0718 VZ |
4915 | break; |
4916 | } | |
4917 | ||
4918 | /* Clear the bit */ | |
4919 | sig &= ~cur_bit; | |
4920 | } | |
4921 | } | |
4922 | ||
4293b9f5 | 4923 | return res; |
72fd0718 VZ |
4924 | } |
4925 | ||
4293b9f5 DK |
4926 | static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, |
4927 | int *par_num, bool print) | |
8736c826 | 4928 | { |
4293b9f5 DK |
4929 | u32 cur_bit; |
4930 | bool res; | |
4931 | int i; | |
4932 | ||
4933 | res = false; | |
4934 | ||
8736c826 | 4935 | for (i = 0; sig; i++) { |
4293b9f5 | 4936 | cur_bit = (0x1UL << i); |
8736c826 | 4937 | if (sig & cur_bit) { |
0c23ad37 | 4938 | res = true; /* Each bit is real error! */ |
4293b9f5 DK |
4939 | if (print) { |
4940 | switch (cur_bit) { | |
4941 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
4942 | _print_next_block((*par_num)++, | |
4943 | "PGLUE_B"); | |
6bf07b8e | 4944 | _print_parity(bp, |
4293b9f5 DK |
4945 | PGLUE_B_REG_PGLUE_B_PRTY_STS); |
4946 | break; | |
4947 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
4948 | _print_next_block((*par_num)++, "ATC"); | |
6bf07b8e YM |
4949 | _print_parity(bp, |
4950 | ATC_REG_ATC_PRTY_STS); | |
4293b9f5 | 4951 | break; |
6bf07b8e | 4952 | } |
8736c826 | 4953 | } |
8736c826 VZ |
4954 | /* Clear the bit */ |
4955 | sig &= ~cur_bit; | |
4956 | } | |
4957 | } | |
4958 | ||
4293b9f5 | 4959 | return res; |
8736c826 VZ |
4960 | } |
4961 | ||
1191cb83 ED |
4962 | static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
4963 | u32 *sig) | |
72fd0718 | 4964 | { |
4293b9f5 DK |
4965 | bool res = false; |
4966 | ||
8736c826 VZ |
4967 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4968 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4969 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4970 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4971 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 | 4972 | int par_num = 0; |
ad6afbe9 | 4973 | |
51c1a580 MS |
4974 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
4975 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", | |
8736c826 VZ |
4976 | sig[0] & HW_PRTY_ASSERT_SET_0, |
4977 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4978 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4979 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4980 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
ad6afbe9 MC |
4981 | if (print) { |
4982 | if (((sig[0] & HW_PRTY_ASSERT_SET_0) || | |
4983 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4984 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4985 | (sig[4] & HW_PRTY_ASSERT_SET_4)) || | |
4986 | (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) { | |
4987 | netdev_err(bp->dev, | |
4988 | "Parity errors detected in blocks: "); | |
4989 | } else { | |
4990 | print = false; | |
4991 | } | |
4992 | } | |
4293b9f5 DK |
4993 | res |= bnx2x_check_blocks_with_parity0(bp, |
4994 | sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print); | |
4995 | res |= bnx2x_check_blocks_with_parity1(bp, | |
4996 | sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print); | |
4997 | res |= bnx2x_check_blocks_with_parity2(bp, | |
4998 | sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print); | |
4999 | res |= bnx2x_check_blocks_with_parity3(bp, | |
5000 | sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print); | |
5001 | res |= bnx2x_check_blocks_with_parity4(bp, | |
5002 | sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print); | |
8736c826 | 5003 | |
c9ee9206 VZ |
5004 | if (print) |
5005 | pr_cont("\n"); | |
4293b9f5 | 5006 | } |
8736c826 | 5007 | |
4293b9f5 | 5008 | return res; |
72fd0718 VZ |
5009 | } |
5010 | ||
c9ee9206 VZ |
5011 | /** |
5012 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
5013 | * | |
5014 | * @bp: driver handle | |
5015 | * @global: true if there was a global attention | |
5016 | * @print: show parity attention in syslog | |
5017 | */ | |
5018 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 5019 | { |
8736c826 | 5020 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
5021 | int port = BP_PORT(bp); |
5022 | ||
5023 | attn.sig[0] = REG_RD(bp, | |
5024 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
5025 | port*4); | |
5026 | attn.sig[1] = REG_RD(bp, | |
5027 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
5028 | port*4); | |
5029 | attn.sig[2] = REG_RD(bp, | |
5030 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
5031 | port*4); | |
5032 | attn.sig[3] = REG_RD(bp, | |
5033 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
5034 | port*4); | |
0a5ccb75 YM |
5035 | /* Since MCP attentions can't be disabled inside the block, we need to |
5036 | * read AEU registers to see whether they're currently disabled | |
5037 | */ | |
5038 | attn.sig[3] &= ((REG_RD(bp, | |
5039 | !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 | |
5040 | : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) & | |
5041 | MISC_AEU_ENABLE_MCP_PRTY_BITS) | | |
5042 | ~MISC_AEU_ENABLE_MCP_PRTY_BITS); | |
72fd0718 | 5043 | |
8736c826 VZ |
5044 | if (!CHIP_IS_E1x(bp)) |
5045 | attn.sig[4] = REG_RD(bp, | |
5046 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
5047 | port*4); | |
5048 | ||
5049 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
5050 | } |
5051 | ||
1191cb83 | 5052 | static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) |
f2e0899f DK |
5053 | { |
5054 | u32 val; | |
5055 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
5056 | ||
5057 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
5058 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
5059 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
51c1a580 | 5060 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
f2e0899f | 5061 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
51c1a580 | 5062 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
f2e0899f | 5063 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
51c1a580 | 5064 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
f2e0899f | 5065 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
51c1a580 | 5066 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
f2e0899f DK |
5067 | if (val & |
5068 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
51c1a580 | 5069 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
f2e0899f DK |
5070 | if (val & |
5071 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
51c1a580 | 5072 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
f2e0899f | 5073 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
51c1a580 | 5074 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
f2e0899f | 5075 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
51c1a580 | 5076 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
f2e0899f | 5077 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
51c1a580 | 5078 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
f2e0899f DK |
5079 | } |
5080 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
5081 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
5082 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
5083 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
5084 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
5085 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
51c1a580 | 5086 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
f2e0899f | 5087 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
51c1a580 | 5088 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
f2e0899f | 5089 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
51c1a580 | 5090 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
f2e0899f DK |
5091 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
5092 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
5093 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
51c1a580 | 5094 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
f2e0899f DK |
5095 | } |
5096 | ||
5097 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
5098 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
5099 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
5100 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
5101 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
5102 | } | |
f2e0899f DK |
5103 | } |
5104 | ||
72fd0718 VZ |
5105 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
5106 | { | |
5107 | struct attn_route attn, *group_mask; | |
34f80b04 | 5108 | int port = BP_PORT(bp); |
877e9aa4 | 5109 | int index; |
a2fbb9ea ET |
5110 | u32 reg_addr; |
5111 | u32 val; | |
3fcaf2e5 | 5112 | u32 aeu_mask; |
c9ee9206 | 5113 | bool global = false; |
a2fbb9ea ET |
5114 | |
5115 | /* need to take HW lock because MCP or other port might also | |
5116 | try to handle this event */ | |
4a37fb66 | 5117 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 5118 | |
c9ee9206 VZ |
5119 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
5120 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 5121 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 5122 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
5123 | /* Disable HW interrupts */ |
5124 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
5125 | /* In case of parity errors don't handle attentions so that |
5126 | * other function would "see" parity errors. | |
5127 | */ | |
c9ee9206 VZ |
5128 | #else |
5129 | bnx2x_panic(); | |
5130 | #endif | |
5131 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
5132 | return; |
5133 | } | |
5134 | ||
a2fbb9ea ET |
5135 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
5136 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
5137 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
5138 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 5139 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5140 | attn.sig[4] = |
5141 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
5142 | else | |
5143 | attn.sig[4] = 0; | |
5144 | ||
5145 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
5146 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
5147 | |
5148 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
5149 | if (deasserted & (1 << index)) { | |
72fd0718 | 5150 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 5151 | |
51c1a580 | 5152 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
f2e0899f DK |
5153 | index, |
5154 | group_mask->sig[0], group_mask->sig[1], | |
5155 | group_mask->sig[2], group_mask->sig[3], | |
5156 | group_mask->sig[4]); | |
a2fbb9ea | 5157 | |
f2e0899f DK |
5158 | bnx2x_attn_int_deasserted4(bp, |
5159 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 5160 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 5161 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 5162 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 5163 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 5164 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 5165 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 5166 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 5167 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
5168 | } |
5169 | } | |
5170 | ||
4a37fb66 | 5171 | bnx2x_release_alr(bp); |
a2fbb9ea | 5172 | |
f2e0899f DK |
5173 | if (bp->common.int_block == INT_BLOCK_HC) |
5174 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
5175 | COMMAND_REG_ATTN_BITS_CLR); | |
5176 | else | |
5177 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
5178 | |
5179 | val = ~deasserted; | |
f2e0899f DK |
5180 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
5181 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 5182 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 5183 | |
a2fbb9ea | 5184 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 5185 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
5186 | |
5187 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
5188 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
5189 | ||
3fcaf2e5 EG |
5190 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
5191 | aeu_mask = REG_RD(bp, reg_addr); | |
5192 | ||
5193 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
5194 | aeu_mask, deasserted); | |
72fd0718 | 5195 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 5196 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 5197 | |
3fcaf2e5 EG |
5198 | REG_WR(bp, reg_addr, aeu_mask); |
5199 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
5200 | |
5201 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
5202 | bp->attn_state &= ~deasserted; | |
5203 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
5204 | } | |
5205 | ||
5206 | static void bnx2x_attn_int(struct bnx2x *bp) | |
5207 | { | |
5208 | /* read local copy of bits */ | |
68d59484 EG |
5209 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
5210 | attn_bits); | |
5211 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
5212 | attn_bits_ack); | |
a2fbb9ea ET |
5213 | u32 attn_state = bp->attn_state; |
5214 | ||
5215 | /* look for changed bits */ | |
5216 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
5217 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
5218 | ||
5219 | DP(NETIF_MSG_HW, | |
5220 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
5221 | attn_bits, attn_ack, asserted, deasserted); | |
5222 | ||
5223 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 5224 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
5225 | |
5226 | /* handle bits that were raised */ | |
5227 | if (asserted) | |
5228 | bnx2x_attn_int_asserted(bp, asserted); | |
5229 | ||
5230 | if (deasserted) | |
5231 | bnx2x_attn_int_deasserted(bp, deasserted); | |
5232 | } | |
5233 | ||
619c5cb6 VZ |
5234 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
5235 | u16 index, u8 op, u8 update) | |
5236 | { | |
dc1ba591 AE |
5237 | u32 igu_addr = bp->igu_base_addr; |
5238 | igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
619c5cb6 VZ |
5239 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, |
5240 | igu_addr); | |
5241 | } | |
5242 | ||
1191cb83 | 5243 | static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
523224a3 DK |
5244 | { |
5245 | /* No memory barriers */ | |
5246 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
5247 | mmiowb(); /* keep prod updates ordered */ | |
5248 | } | |
5249 | ||
523224a3 DK |
5250 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, |
5251 | union event_ring_elem *elem) | |
5252 | { | |
619c5cb6 VZ |
5253 | u8 err = elem->message.error; |
5254 | ||
523224a3 | 5255 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
5256 | (cid < bp->cnic_eth_dev.starting_cid && |
5257 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
5258 | return 1; |
5259 | ||
5260 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
5261 | ||
619c5cb6 VZ |
5262 | if (unlikely(err)) { |
5263 | ||
523224a3 DK |
5264 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
5265 | cid); | |
823e1d90 | 5266 | bnx2x_panic_dump(bp, false); |
523224a3 | 5267 | } |
619c5cb6 | 5268 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
5269 | return 0; |
5270 | } | |
523224a3 | 5271 | |
1191cb83 | 5272 | static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
5273 | { |
5274 | struct bnx2x_mcast_ramrod_params rparam; | |
5275 | int rc; | |
5276 | ||
5277 | memset(&rparam, 0, sizeof(rparam)); | |
5278 | ||
5279 | rparam.mcast_obj = &bp->mcast_obj; | |
5280 | ||
5281 | netif_addr_lock_bh(bp->dev); | |
5282 | ||
5283 | /* Clear pending state for the last command */ | |
5284 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
5285 | ||
5286 | /* If there are pending mcast commands - send them */ | |
5287 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
5288 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
5289 | if (rc < 0) | |
5290 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
5291 | rc); | |
5292 | } | |
5293 | ||
5294 | netif_addr_unlock_bh(bp->dev); | |
5295 | } | |
5296 | ||
1191cb83 ED |
5297 | static void bnx2x_handle_classification_eqe(struct bnx2x *bp, |
5298 | union event_ring_elem *elem) | |
619c5cb6 VZ |
5299 | { |
5300 | unsigned long ramrod_flags = 0; | |
5301 | int rc = 0; | |
9cd753a1 MS |
5302 | u32 echo = le32_to_cpu(elem->message.data.eth_event.echo); |
5303 | u32 cid = echo & BNX2X_SWCID_MASK; | |
619c5cb6 VZ |
5304 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; |
5305 | ||
5306 | /* Always push next commands out, don't wait here */ | |
5307 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
5308 | ||
9cd753a1 | 5309 | switch (echo >> BNX2X_SWCID_SHIFT) { |
619c5cb6 | 5310 | case BNX2X_FILTER_MAC_PENDING: |
51c1a580 | 5311 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
55c11941 | 5312 | if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) |
619c5cb6 VZ |
5313 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; |
5314 | else | |
15192a8c | 5315 | vlan_mac_obj = &bp->sp_objs[cid].mac_obj; |
619c5cb6 | 5316 | |
05cc5a39 YM |
5317 | break; |
5318 | case BNX2X_FILTER_VLAN_PENDING: | |
5319 | DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n"); | |
5320 | vlan_mac_obj = &bp->sp_objs[cid].vlan_obj; | |
619c5cb6 | 5321 | break; |
619c5cb6 | 5322 | case BNX2X_FILTER_MCAST_PENDING: |
51c1a580 | 5323 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
619c5cb6 VZ |
5324 | /* This is only relevant for 57710 where multicast MACs are |
5325 | * configured as unicast MACs using the same ramrod. | |
5326 | */ | |
5327 | bnx2x_handle_mcast_eqe(bp); | |
5328 | return; | |
5329 | default: | |
9cd753a1 | 5330 | BNX2X_ERR("Unsupported classification command: 0x%x\n", echo); |
619c5cb6 VZ |
5331 | return; |
5332 | } | |
5333 | ||
5334 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
5335 | ||
5336 | if (rc < 0) | |
5337 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
5338 | else if (rc > 0) | |
5339 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
619c5cb6 VZ |
5340 | } |
5341 | ||
619c5cb6 | 5342 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); |
619c5cb6 | 5343 | |
1191cb83 | 5344 | static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
5345 | { |
5346 | netif_addr_lock_bh(bp->dev); | |
5347 | ||
5348 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5349 | ||
5350 | /* Send rx_mode command again if was requested */ | |
5351 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
5352 | bnx2x_set_storm_rx_mode(bp); | |
619c5cb6 VZ |
5353 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, |
5354 | &bp->sp_state)) | |
5355 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
5356 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
5357 | &bp->sp_state)) | |
5358 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
619c5cb6 VZ |
5359 | |
5360 | netif_addr_unlock_bh(bp->dev); | |
5361 | } | |
5362 | ||
1191cb83 | 5363 | static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, |
a3348722 BW |
5364 | union event_ring_elem *elem) |
5365 | { | |
5366 | if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { | |
5367 | DP(BNX2X_MSG_SP, | |
5368 | "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", | |
5369 | elem->message.data.vif_list_event.func_bit_map); | |
5370 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, | |
5371 | elem->message.data.vif_list_event.func_bit_map); | |
5372 | } else if (elem->message.data.vif_list_event.echo == | |
5373 | VIF_LIST_RULE_SET) { | |
5374 | DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); | |
5375 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); | |
5376 | } | |
5377 | } | |
5378 | ||
5379 | /* called with rtnl_lock */ | |
1191cb83 | 5380 | static void bnx2x_after_function_update(struct bnx2x *bp) |
a3348722 BW |
5381 | { |
5382 | int q, rc; | |
5383 | struct bnx2x_fastpath *fp; | |
5384 | struct bnx2x_queue_state_params queue_params = {NULL}; | |
5385 | struct bnx2x_queue_update_params *q_update_params = | |
5386 | &queue_params.params.update; | |
5387 | ||
2de67439 | 5388 | /* Send Q update command with afex vlan removal values for all Qs */ |
a3348722 BW |
5389 | queue_params.cmd = BNX2X_Q_CMD_UPDATE; |
5390 | ||
5391 | /* set silent vlan removal values according to vlan mode */ | |
5392 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | |
5393 | &q_update_params->update_flags); | |
5394 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
5395 | &q_update_params->update_flags); | |
5396 | __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
5397 | ||
5398 | /* in access mode mark mask and value are 0 to strip all vlans */ | |
5399 | if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { | |
5400 | q_update_params->silent_removal_value = 0; | |
5401 | q_update_params->silent_removal_mask = 0; | |
5402 | } else { | |
5403 | q_update_params->silent_removal_value = | |
5404 | (bp->afex_def_vlan_tag & VLAN_VID_MASK); | |
5405 | q_update_params->silent_removal_mask = VLAN_VID_MASK; | |
5406 | } | |
5407 | ||
5408 | for_each_eth_queue(bp, q) { | |
5409 | /* Set the appropriate Queue object */ | |
5410 | fp = &bp->fp[q]; | |
15192a8c | 5411 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
5412 | |
5413 | /* send the ramrod */ | |
5414 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
5415 | if (rc < 0) | |
5416 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
5417 | q); | |
5418 | } | |
5419 | ||
fea75645 | 5420 | if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { |
65565884 | 5421 | fp = &bp->fp[FCOE_IDX(bp)]; |
15192a8c | 5422 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
5423 | |
5424 | /* clear pending completion bit */ | |
5425 | __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
5426 | ||
5427 | /* mark latest Q bit */ | |
4e857c58 | 5428 | smp_mb__before_atomic(); |
a3348722 | 5429 | set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); |
4e857c58 | 5430 | smp_mb__after_atomic(); |
a3348722 BW |
5431 | |
5432 | /* send Q update ramrod for FCoE Q */ | |
5433 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
5434 | if (rc < 0) | |
5435 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
5436 | q); | |
5437 | } else { | |
5438 | /* If no FCoE ring - ACK MCP now */ | |
5439 | bnx2x_link_report(bp); | |
5440 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5441 | } | |
a3348722 BW |
5442 | } |
5443 | ||
1191cb83 | 5444 | static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( |
619c5cb6 VZ |
5445 | struct bnx2x *bp, u32 cid) |
5446 | { | |
94f05b0f | 5447 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
55c11941 MS |
5448 | |
5449 | if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) | |
15192a8c | 5450 | return &bnx2x_fcoe_sp_obj(bp, q_obj); |
619c5cb6 | 5451 | else |
15192a8c | 5452 | return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; |
619c5cb6 VZ |
5453 | } |
5454 | ||
523224a3 DK |
5455 | static void bnx2x_eq_int(struct bnx2x *bp) |
5456 | { | |
5457 | u16 hw_cons, sw_cons, sw_prod; | |
5458 | union event_ring_elem *elem; | |
55c11941 | 5459 | u8 echo; |
523224a3 DK |
5460 | u32 cid; |
5461 | u8 opcode; | |
fd1fc79d | 5462 | int rc, spqe_cnt = 0; |
619c5cb6 VZ |
5463 | struct bnx2x_queue_sp_obj *q_obj; |
5464 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
5465 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
5466 | |
5467 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
5468 | ||
5469 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
16a5fd92 | 5470 | * when we get the next-page we need to adjust so the loop |
523224a3 DK |
5471 | * condition below will be met. The next element is the size of a |
5472 | * regular element and hence incrementing by 1 | |
5473 | */ | |
5474 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
5475 | hw_cons++; | |
5476 | ||
25985edc | 5477 | /* This function may never run in parallel with itself for a |
523224a3 DK |
5478 | * specific bp, thus there is no need in "paired" read memory |
5479 | * barrier here. | |
5480 | */ | |
5481 | sw_cons = bp->eq_cons; | |
5482 | sw_prod = bp->eq_prod; | |
5483 | ||
d6cae238 | 5484 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 5485 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
5486 | |
5487 | for (; sw_cons != hw_cons; | |
5488 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
5489 | ||
523224a3 DK |
5490 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; |
5491 | ||
fd1fc79d AE |
5492 | rc = bnx2x_iov_eq_sp_event(bp, elem); |
5493 | if (!rc) { | |
5494 | DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", | |
5495 | rc); | |
5496 | goto next_spqe; | |
5497 | } | |
523224a3 | 5498 | |
86564c3f | 5499 | opcode = elem->message.opcode; |
523224a3 DK |
5500 | |
5501 | /* handle eq element */ | |
5502 | switch (opcode) { | |
fd1fc79d | 5503 | case EVENT_RING_OPCODE_VF_PF_CHANNEL: |
370d4a26 YM |
5504 | bnx2x_vf_mbx_schedule(bp, |
5505 | &elem->message.data.vf_pf_event); | |
fd1fc79d AE |
5506 | continue; |
5507 | ||
523224a3 | 5508 | case EVENT_RING_OPCODE_STAT_QUERY: |
76ca70fa YM |
5509 | DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS), |
5510 | "got statistics comp event %d\n", | |
5511 | bp->stats_comp++); | |
523224a3 | 5512 | /* nothing to do with stats comp */ |
d6cae238 | 5513 | goto next_spqe; |
523224a3 DK |
5514 | |
5515 | case EVENT_RING_OPCODE_CFC_DEL: | |
5516 | /* handle according to cid range */ | |
5517 | /* | |
5518 | * we may want to verify here that the bp state is | |
5519 | * HALTING | |
5520 | */ | |
ca4f2d50 MS |
5521 | |
5522 | /* elem CID originates from FW; actually LE */ | |
da472731 | 5523 | cid = SW_CID(elem->message.data.cfc_del_event.cid); |
ca4f2d50 | 5524 | |
d6cae238 | 5525 | DP(BNX2X_MSG_SP, |
523224a3 | 5526 | "got delete ramrod for MULTI[%d]\n", cid); |
55c11941 MS |
5527 | |
5528 | if (CNIC_LOADED(bp) && | |
5529 | !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
523224a3 | 5530 | goto next_spqe; |
55c11941 | 5531 | |
619c5cb6 VZ |
5532 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
5533 | ||
5534 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
5535 | break; | |
5536 | ||
523224a3 | 5537 | goto next_spqe; |
e4901dde VZ |
5538 | |
5539 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
51c1a580 | 5540 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
6ffa39f2 | 5541 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
6debea87 DK |
5542 | if (f_obj->complete_cmd(bp, f_obj, |
5543 | BNX2X_F_CMD_TX_STOP)) | |
5544 | break; | |
e4901dde | 5545 | goto next_spqe; |
619c5cb6 | 5546 | |
e4901dde | 5547 | case EVENT_RING_OPCODE_START_TRAFFIC: |
51c1a580 | 5548 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
6ffa39f2 | 5549 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
6debea87 DK |
5550 | if (f_obj->complete_cmd(bp, f_obj, |
5551 | BNX2X_F_CMD_TX_START)) | |
5552 | break; | |
e4901dde | 5553 | goto next_spqe; |
55c11941 | 5554 | |
a3348722 | 5555 | case EVENT_RING_OPCODE_FUNCTION_UPDATE: |
55c11941 MS |
5556 | echo = elem->message.data.function_update_event.echo; |
5557 | if (echo == SWITCH_UPDATE) { | |
5558 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, | |
5559 | "got FUNC_SWITCH_UPDATE ramrod\n"); | |
5560 | if (f_obj->complete_cmd( | |
5561 | bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) | |
5562 | break; | |
a3348722 | 5563 | |
55c11941 | 5564 | } else { |
230bb0f3 YM |
5565 | int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE; |
5566 | ||
55c11941 MS |
5567 | DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, |
5568 | "AFEX: ramrod completed FUNCTION_UPDATE\n"); | |
5569 | f_obj->complete_cmd(bp, f_obj, | |
5570 | BNX2X_F_CMD_AFEX_UPDATE); | |
5571 | ||
5572 | /* We will perform the Queues update from | |
5573 | * sp_rtnl task as all Queue SP operations | |
5574 | * should run under rtnl_lock. | |
5575 | */ | |
230bb0f3 | 5576 | bnx2x_schedule_sp_rtnl(bp, cmd, 0); |
55c11941 | 5577 | } |
a3348722 | 5578 | |
a3348722 BW |
5579 | goto next_spqe; |
5580 | ||
5581 | case EVENT_RING_OPCODE_AFEX_VIF_LISTS: | |
5582 | f_obj->complete_cmd(bp, f_obj, | |
5583 | BNX2X_F_CMD_AFEX_VIFLISTS); | |
5584 | bnx2x_after_afex_vif_lists(bp, elem); | |
5585 | goto next_spqe; | |
619c5cb6 | 5586 | case EVENT_RING_OPCODE_FUNCTION_START: |
51c1a580 MS |
5587 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5588 | "got FUNC_START ramrod\n"); | |
619c5cb6 VZ |
5589 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
5590 | break; | |
5591 | ||
5592 | goto next_spqe; | |
5593 | ||
5594 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
51c1a580 MS |
5595 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5596 | "got FUNC_STOP ramrod\n"); | |
619c5cb6 VZ |
5597 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
5598 | break; | |
5599 | ||
5600 | goto next_spqe; | |
eeed018c MK |
5601 | |
5602 | case EVENT_RING_OPCODE_SET_TIMESYNC: | |
5603 | DP(BNX2X_MSG_SP | BNX2X_MSG_PTP, | |
5604 | "got set_timesync ramrod completion\n"); | |
5605 | if (f_obj->complete_cmd(bp, f_obj, | |
5606 | BNX2X_F_CMD_SET_TIMESYNC)) | |
5607 | break; | |
5608 | goto next_spqe; | |
523224a3 DK |
5609 | } |
5610 | ||
5611 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
5612 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
5613 | BNX2X_STATE_OPEN): | |
5614 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 5615 | BNX2X_STATE_OPENING_WAIT4_PORT): |
28311f8e YM |
5616 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
5617 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5618 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
9cd753a1 | 5619 | SW_CID(elem->message.data.eth_event.echo)); |
619c5cb6 | 5620 | rss_raw->clear_pending(rss_raw); |
523224a3 DK |
5621 | break; |
5622 | ||
619c5cb6 VZ |
5623 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
5624 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
5625 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 5626 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
5627 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
5628 | BNX2X_STATE_OPEN): | |
5629 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5630 | BNX2X_STATE_DIAG): | |
5631 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5632 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
05cc5a39 | 5633 | DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n"); |
619c5cb6 | 5634 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
5635 | break; |
5636 | ||
619c5cb6 VZ |
5637 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
5638 | BNX2X_STATE_OPEN): | |
5639 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5640 | BNX2X_STATE_DIAG): | |
5641 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5642 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5643 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 5644 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
5645 | break; |
5646 | ||
619c5cb6 VZ |
5647 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
5648 | BNX2X_STATE_OPEN): | |
5649 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
5650 | BNX2X_STATE_DIAG): | |
5651 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 5652 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 5653 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 5654 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
5655 | break; |
5656 | default: | |
5657 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
5658 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
5659 | elem->message.opcode, bp->state); | |
523224a3 DK |
5660 | } |
5661 | next_spqe: | |
5662 | spqe_cnt++; | |
5663 | } /* for */ | |
5664 | ||
4e857c58 | 5665 | smp_mb__before_atomic(); |
6e30dd4e | 5666 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
5667 | |
5668 | bp->eq_cons = sw_cons; | |
5669 | bp->eq_prod = sw_prod; | |
5670 | /* Make sure that above mem writes were issued towards the memory */ | |
5671 | smp_wmb(); | |
5672 | ||
5673 | /* update producer */ | |
5674 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
5675 | } | |
5676 | ||
a2fbb9ea ET |
5677 | static void bnx2x_sp_task(struct work_struct *work) |
5678 | { | |
1cf167f2 | 5679 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea | 5680 | |
fd1fc79d | 5681 | DP(BNX2X_MSG_SP, "sp task invoked\n"); |
a2fbb9ea | 5682 | |
16a5fd92 | 5683 | /* make sure the atomic interrupt_occurred has been written */ |
fd1fc79d AE |
5684 | smp_rmb(); |
5685 | if (atomic_read(&bp->interrupt_occurred)) { | |
a2fbb9ea | 5686 | |
fd1fc79d AE |
5687 | /* what work needs to be performed? */ |
5688 | u16 status = bnx2x_update_dsb_idx(bp); | |
cdaa7cb8 | 5689 | |
fd1fc79d AE |
5690 | DP(BNX2X_MSG_SP, "status %x\n", status); |
5691 | DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); | |
5692 | atomic_set(&bp->interrupt_occurred, 0); | |
5693 | ||
5694 | /* HW attentions */ | |
5695 | if (status & BNX2X_DEF_SB_ATT_IDX) { | |
5696 | bnx2x_attn_int(bp); | |
5697 | status &= ~BNX2X_DEF_SB_ATT_IDX; | |
5698 | } | |
5699 | ||
5700 | /* SP events: STAT_QUERY and others */ | |
5701 | if (status & BNX2X_DEF_SB_IDX) { | |
5702 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 5703 | |
7e88009b | 5704 | if (FCOE_INIT(bp) && |
fd1fc79d AE |
5705 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
5706 | /* Prevent local bottom-halves from running as | |
5707 | * we are going to change the local NAPI list. | |
5708 | */ | |
5709 | local_bh_disable(); | |
5710 | napi_schedule(&bnx2x_fcoe(bp, napi)); | |
5711 | local_bh_enable(); | |
5712 | } | |
5713 | ||
5714 | /* Handle EQ completions */ | |
5715 | bnx2x_eq_int(bp); | |
5716 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
5717 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
5718 | ||
5719 | status &= ~BNX2X_DEF_SB_IDX; | |
019dbb4c | 5720 | } |
55c11941 | 5721 | |
fd1fc79d AE |
5722 | /* if status is non zero then perhaps something went wrong */ |
5723 | if (unlikely(status)) | |
5724 | DP(BNX2X_MSG_SP, | |
5725 | "got an unknown interrupt! (status 0x%x)\n", status); | |
523224a3 | 5726 | |
fd1fc79d AE |
5727 | /* ack status block only if something was actually handled */ |
5728 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, | |
5729 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
cdaa7cb8 VZ |
5730 | } |
5731 | ||
a3348722 BW |
5732 | /* afex - poll to check if VIFSET_ACK should be sent to MFW */ |
5733 | if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, | |
5734 | &bp->sp_state)) { | |
5735 | bnx2x_link_report(bp); | |
5736 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5737 | } | |
a2fbb9ea ET |
5738 | } |
5739 | ||
9f6c9258 | 5740 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
5741 | { |
5742 | struct net_device *dev = dev_instance; | |
5743 | struct bnx2x *bp = netdev_priv(dev); | |
5744 | ||
523224a3 DK |
5745 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
5746 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
5747 | |
5748 | #ifdef BNX2X_STOP_ON_ERROR | |
5749 | if (unlikely(bp->panic)) | |
5750 | return IRQ_HANDLED; | |
5751 | #endif | |
5752 | ||
55c11941 | 5753 | if (CNIC_LOADED(bp)) { |
993ac7b5 MC |
5754 | struct cnic_ops *c_ops; |
5755 | ||
5756 | rcu_read_lock(); | |
5757 | c_ops = rcu_dereference(bp->cnic_ops); | |
5758 | if (c_ops) | |
5759 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
5760 | rcu_read_unlock(); | |
5761 | } | |
55c11941 | 5762 | |
fd1fc79d AE |
5763 | /* schedule sp task to perform default status block work, ack |
5764 | * attentions and enable interrupts. | |
5765 | */ | |
5766 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
5767 | |
5768 | return IRQ_HANDLED; | |
5769 | } | |
5770 | ||
5771 | /* end of slow path */ | |
5772 | ||
619c5cb6 VZ |
5773 | void bnx2x_drv_pulse(struct bnx2x *bp) |
5774 | { | |
5775 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
5776 | bp->fw_drv_pulse_wr_seq); | |
5777 | } | |
5778 | ||
e99e88a9 | 5779 | static void bnx2x_timer(struct timer_list *t) |
a2fbb9ea | 5780 | { |
e99e88a9 | 5781 | struct bnx2x *bp = from_timer(bp, t, timer); |
a2fbb9ea ET |
5782 | |
5783 | if (!netif_running(bp->dev)) | |
5784 | return; | |
5785 | ||
67c431a5 AE |
5786 | if (IS_PF(bp) && |
5787 | !BP_NOMCP(bp)) { | |
f2e0899f | 5788 | int mb_idx = BP_FW_MB_IDX(bp); |
4c868664 EG |
5789 | u16 drv_pulse; |
5790 | u16 mcp_pulse; | |
a2fbb9ea ET |
5791 | |
5792 | ++bp->fw_drv_pulse_wr_seq; | |
5793 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
a2fbb9ea | 5794 | drv_pulse = bp->fw_drv_pulse_wr_seq; |
619c5cb6 | 5795 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 5796 | |
f2e0899f | 5797 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
5798 | MCP_PULSE_SEQ_MASK); |
5799 | /* The delta between driver pulse and mcp response | |
4c868664 EG |
5800 | * should not get too big. If the MFW is more than 5 pulses |
5801 | * behind, we should worry about it enough to generate an error | |
5802 | * log. | |
a2fbb9ea | 5803 | */ |
4c868664 EG |
5804 | if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5) |
5805 | BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
a2fbb9ea | 5806 | drv_pulse, mcp_pulse); |
a2fbb9ea ET |
5807 | } |
5808 | ||
f34d28ea | 5809 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 5810 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 5811 | |
abc5a021 | 5812 | /* sample pf vf bulletin board for new posts from pf */ |
37173488 YM |
5813 | if (IS_VF(bp)) |
5814 | bnx2x_timer_sriov(bp); | |
78c3bcc5 | 5815 | |
a2fbb9ea ET |
5816 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
5817 | } | |
5818 | ||
5819 | /* end of Statistics */ | |
5820 | ||
5821 | /* nic init */ | |
5822 | ||
5823 | /* | |
5824 | * nic init service functions | |
5825 | */ | |
5826 | ||
1191cb83 | 5827 | static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 5828 | { |
523224a3 DK |
5829 | u32 i; |
5830 | if (!(len%4) && !(addr%4)) | |
5831 | for (i = 0; i < len; i += 4) | |
5832 | REG_WR(bp, addr + i, fill); | |
5833 | else | |
5834 | for (i = 0; i < len; i++) | |
5835 | REG_WR8(bp, addr + i, fill); | |
34f80b04 EG |
5836 | } |
5837 | ||
523224a3 | 5838 | /* helper: writes FP SP data to FW - data_size in dwords */ |
1191cb83 ED |
5839 | static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, |
5840 | int fw_sb_id, | |
5841 | u32 *sb_data_p, | |
5842 | u32 data_size) | |
34f80b04 | 5843 | { |
a2fbb9ea | 5844 | int index; |
523224a3 DK |
5845 | for (index = 0; index < data_size; index++) |
5846 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5847 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
5848 | sizeof(u32)*index, | |
5849 | *(sb_data_p + index)); | |
5850 | } | |
a2fbb9ea | 5851 | |
1191cb83 | 5852 | static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
523224a3 DK |
5853 | { |
5854 | u32 *sb_data_p; | |
5855 | u32 data_size = 0; | |
f2e0899f | 5856 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 5857 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 5858 | |
523224a3 | 5859 | /* disable the function first */ |
619c5cb6 | 5860 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5861 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5862 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
5863 | sb_data_e2.common.p_func.vf_valid = false; |
5864 | sb_data_p = (u32 *)&sb_data_e2; | |
5865 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
5866 | } else { | |
5867 | memset(&sb_data_e1x, 0, | |
5868 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5869 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
5870 | sb_data_e1x.common.p_func.vf_valid = false; |
5871 | sb_data_p = (u32 *)&sb_data_e1x; | |
5872 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
5873 | } | |
523224a3 | 5874 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 5875 | |
523224a3 DK |
5876 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
5877 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
5878 | CSTORM_STATUS_BLOCK_SIZE); | |
5879 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5880 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
5881 | CSTORM_SYNC_BLOCK_SIZE); | |
5882 | } | |
34f80b04 | 5883 | |
523224a3 | 5884 | /* helper: writes SP SB data to FW */ |
1191cb83 | 5885 | static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, |
523224a3 DK |
5886 | struct hc_sp_status_block_data *sp_sb_data) |
5887 | { | |
5888 | int func = BP_FUNC(bp); | |
5889 | int i; | |
5890 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
5891 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5892 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
5893 | i*sizeof(u32), | |
5894 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
5895 | } |
5896 | ||
1191cb83 | 5897 | static void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
5898 | { |
5899 | int func = BP_FUNC(bp); | |
523224a3 DK |
5900 | struct hc_sp_status_block_data sp_sb_data; |
5901 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 5902 | |
619c5cb6 | 5903 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
5904 | sp_sb_data.p_func.vf_valid = false; |
5905 | ||
5906 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
5907 | ||
5908 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5909 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
5910 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
5911 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5912 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
5913 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
523224a3 DK |
5914 | } |
5915 | ||
1191cb83 | 5916 | static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, |
523224a3 DK |
5917 | int igu_sb_id, int igu_seg_id) |
5918 | { | |
5919 | hc_sm->igu_sb_id = igu_sb_id; | |
5920 | hc_sm->igu_seg_id = igu_seg_id; | |
5921 | hc_sm->timer_value = 0xFF; | |
5922 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
5923 | } |
5924 | ||
150966ad | 5925 | /* allocates state machine ids. */ |
1191cb83 | 5926 | static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) |
150966ad AE |
5927 | { |
5928 | /* zero out state machine indices */ | |
5929 | /* rx indices */ | |
5930 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5931 | ||
5932 | /* tx indices */ | |
5933 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5934 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
5935 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
5936 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
5937 | ||
5938 | /* map indices */ | |
5939 | /* rx indices */ | |
5940 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
5941 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5942 | ||
5943 | /* tx indices */ | |
5944 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
5945 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5946 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
5947 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5948 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
5949 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5950 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
5951 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5952 | } | |
5953 | ||
b93288d5 | 5954 | void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 5955 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 5956 | { |
523224a3 DK |
5957 | int igu_seg_id; |
5958 | ||
f2e0899f | 5959 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
5960 | struct hc_status_block_data_e1x sb_data_e1x; |
5961 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
5962 | int data_size; |
5963 | u32 *sb_data_p; | |
5964 | ||
f2e0899f DK |
5965 | if (CHIP_INT_MODE_IS_BC(bp)) |
5966 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
5967 | else | |
5968 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
5969 | |
5970 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
5971 | ||
619c5cb6 | 5972 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5973 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5974 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
5975 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
5976 | sb_data_e2.common.p_func.vf_id = vfid; | |
5977 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
5978 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
5979 | sb_data_e2.common.same_igu_sb_1b = true; | |
5980 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
5981 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
5982 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
5983 | sb_data_p = (u32 *)&sb_data_e2; |
5984 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 5985 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
5986 | } else { |
5987 | memset(&sb_data_e1x, 0, | |
5988 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5989 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
5990 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
5991 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
5992 | sb_data_e1x.common.p_func.vf_valid = false; | |
5993 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
5994 | sb_data_e1x.common.same_igu_sb_1b = true; | |
5995 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
5996 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
5997 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
5998 | sb_data_p = (u32 *)&sb_data_e1x; |
5999 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 6000 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 6001 | } |
523224a3 DK |
6002 | |
6003 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
6004 | igu_sb_id, igu_seg_id); | |
6005 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
6006 | igu_sb_id, igu_seg_id); | |
6007 | ||
51c1a580 | 6008 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
523224a3 | 6009 | |
86564c3f | 6010 | /* write indices to HW - PCI guarantees endianity of regpairs */ |
523224a3 DK |
6011 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
6012 | } | |
6013 | ||
619c5cb6 | 6014 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
6015 | u16 tx_usec, u16 rx_usec) |
6016 | { | |
6383c0b3 | 6017 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 6018 | false, rx_usec); |
6383c0b3 AE |
6019 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
6020 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
6021 | tx_usec); | |
6022 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
6023 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
6024 | tx_usec); | |
6025 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
6026 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
6027 | tx_usec); | |
523224a3 | 6028 | } |
f2e0899f | 6029 | |
523224a3 DK |
6030 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
6031 | { | |
6032 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
6033 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
6034 | int igu_sp_sb_index; | |
6035 | int igu_seg_id; | |
34f80b04 EG |
6036 | int port = BP_PORT(bp); |
6037 | int func = BP_FUNC(bp); | |
f2eaeb58 | 6038 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 6039 | u64 section; |
523224a3 DK |
6040 | int index; |
6041 | struct hc_sp_status_block_data sp_sb_data; | |
6042 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
6043 | ||
f2e0899f DK |
6044 | if (CHIP_INT_MODE_IS_BC(bp)) { |
6045 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
6046 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
6047 | } else { | |
6048 | igu_sp_sb_index = bp->igu_dsb_id; | |
6049 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
6050 | } | |
a2fbb9ea ET |
6051 | |
6052 | /* ATTN */ | |
523224a3 | 6053 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 6054 | atten_status_block); |
523224a3 | 6055 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 6056 | |
49d66772 ET |
6057 | bp->attn_state = 0; |
6058 | ||
a2fbb9ea ET |
6059 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
6060 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
6061 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
6062 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 6063 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
6064 | int sindex; |
6065 | /* take care of sig[0]..sig[4] */ | |
6066 | for (sindex = 0; sindex < 4; sindex++) | |
6067 | bp->attn_group[index].sig[sindex] = | |
6068 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 6069 | |
619c5cb6 | 6070 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6071 | /* |
6072 | * enable5 is separate from the rest of the registers, | |
6073 | * and therefore the address skip is 4 | |
6074 | * and not 16 between the different groups | |
6075 | */ | |
6076 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 6077 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
6078 | else |
6079 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
6080 | } |
6081 | ||
f2e0899f DK |
6082 | if (bp->common.int_block == INT_BLOCK_HC) { |
6083 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
6084 | HC_REG_ATTN_MSG0_ADDR_L); | |
6085 | ||
6086 | REG_WR(bp, reg_offset, U64_LO(section)); | |
6087 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 6088 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6089 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
6090 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
6091 | } | |
a2fbb9ea | 6092 | |
523224a3 DK |
6093 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
6094 | sp_sb); | |
a2fbb9ea | 6095 | |
523224a3 | 6096 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 6097 | |
86564c3f | 6098 | /* PCI guarantees endianity of regpairs */ |
619c5cb6 | 6099 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
6100 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
6101 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
6102 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
6103 | sp_sb_data.igu_seg_id = igu_seg_id; | |
6104 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 6105 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 6106 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 6107 | |
523224a3 | 6108 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 6109 | |
523224a3 | 6110 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
6111 | } |
6112 | ||
9f6c9258 | 6113 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 6114 | { |
a2fbb9ea ET |
6115 | int i; |
6116 | ||
ec6ba945 | 6117 | for_each_eth_queue(bp, i) |
523224a3 | 6118 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 6119 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
6120 | } |
6121 | ||
a2fbb9ea ET |
6122 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
6123 | { | |
a2fbb9ea | 6124 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 6125 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 6126 | |
a2fbb9ea | 6127 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
6128 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
6129 | bp->spq_prod_bd = bp->spq; | |
6130 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
6131 | } |
6132 | ||
523224a3 | 6133 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
6134 | { |
6135 | int i; | |
523224a3 DK |
6136 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
6137 | union event_ring_elem *elem = | |
6138 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 6139 | |
523224a3 DK |
6140 | elem->next_page.addr.hi = |
6141 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
6142 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
6143 | elem->next_page.addr.lo = | |
6144 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
6145 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 6146 | } |
523224a3 DK |
6147 | bp->eq_cons = 0; |
6148 | bp->eq_prod = NUM_EQ_DESC; | |
6149 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
16a5fd92 | 6150 | /* we want a warning message before it gets wrought... */ |
6e30dd4e VZ |
6151 | atomic_set(&bp->eq_spq_left, |
6152 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
6153 | } |
6154 | ||
619c5cb6 | 6155 | /* called with netif_addr_lock_bh() */ |
a8f47eb7 | 6156 | static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
6157 | unsigned long rx_mode_flags, | |
6158 | unsigned long rx_accept_flags, | |
6159 | unsigned long tx_accept_flags, | |
6160 | unsigned long ramrod_flags) | |
ab532cf3 | 6161 | { |
619c5cb6 VZ |
6162 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
6163 | int rc; | |
6164 | ||
6165 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
6166 | ||
6167 | /* Prepare ramrod parameters */ | |
6168 | ramrod_param.cid = 0; | |
6169 | ramrod_param.cl_id = cl_id; | |
6170 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
6171 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 6172 | |
619c5cb6 VZ |
6173 | ramrod_param.pstate = &bp->sp_state; |
6174 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 6175 | |
619c5cb6 VZ |
6176 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
6177 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
6178 | ||
6179 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
6180 | ||
6181 | ramrod_param.ramrod_flags = ramrod_flags; | |
6182 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
6183 | ||
6184 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
6185 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
6186 | ||
6187 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
6188 | if (rc < 0) { | |
6189 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
924d75ab | 6190 | return rc; |
619c5cb6 | 6191 | } |
924d75ab YM |
6192 | |
6193 | return 0; | |
a2fbb9ea ET |
6194 | } |
6195 | ||
86564c3f YM |
6196 | static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, |
6197 | unsigned long *rx_accept_flags, | |
6198 | unsigned long *tx_accept_flags) | |
471de716 | 6199 | { |
924d75ab YM |
6200 | /* Clear the flags first */ |
6201 | *rx_accept_flags = 0; | |
6202 | *tx_accept_flags = 0; | |
619c5cb6 | 6203 | |
924d75ab | 6204 | switch (rx_mode) { |
619c5cb6 VZ |
6205 | case BNX2X_RX_MODE_NONE: |
6206 | /* | |
6207 | * 'drop all' supersedes any accept flags that may have been | |
6208 | * passed to the function. | |
6209 | */ | |
6210 | break; | |
6211 | case BNX2X_RX_MODE_NORMAL: | |
924d75ab YM |
6212 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
6213 | __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags); | |
6214 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
6215 | |
6216 | /* internal switching mode */ | |
924d75ab YM |
6217 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
6218 | __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags); | |
6219 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 | 6220 | |
05cc5a39 YM |
6221 | if (bp->accept_any_vlan) { |
6222 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); | |
6223 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); | |
6224 | } | |
6225 | ||
619c5cb6 VZ |
6226 | break; |
6227 | case BNX2X_RX_MODE_ALLMULTI: | |
924d75ab YM |
6228 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
6229 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); | |
6230 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
6231 | |
6232 | /* internal switching mode */ | |
924d75ab YM |
6233 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
6234 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); | |
6235 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 | 6236 | |
05cc5a39 YM |
6237 | if (bp->accept_any_vlan) { |
6238 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); | |
6239 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); | |
6240 | } | |
6241 | ||
619c5cb6 VZ |
6242 | break; |
6243 | case BNX2X_RX_MODE_PROMISC: | |
16a5fd92 | 6244 | /* According to definition of SI mode, iface in promisc mode |
619c5cb6 VZ |
6245 | * should receive matched and unmatched (in resolution of port) |
6246 | * unicast packets. | |
6247 | */ | |
924d75ab YM |
6248 | __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags); |
6249 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); | |
6250 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); | |
6251 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
6252 | |
6253 | /* internal switching mode */ | |
924d75ab YM |
6254 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); |
6255 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 VZ |
6256 | |
6257 | if (IS_MF_SI(bp)) | |
924d75ab | 6258 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags); |
619c5cb6 | 6259 | else |
924d75ab | 6260 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
619c5cb6 | 6261 | |
05cc5a39 YM |
6262 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); |
6263 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); | |
6264 | ||
619c5cb6 VZ |
6265 | break; |
6266 | default: | |
924d75ab YM |
6267 | BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode); |
6268 | return -EINVAL; | |
619c5cb6 | 6269 | } |
de832a55 | 6270 | |
924d75ab YM |
6271 | return 0; |
6272 | } | |
6273 | ||
6274 | /* called with netif_addr_lock_bh() */ | |
a8f47eb7 | 6275 | static int bnx2x_set_storm_rx_mode(struct bnx2x *bp) |
924d75ab YM |
6276 | { |
6277 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; | |
6278 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
6279 | int rc; | |
6280 | ||
6281 | if (!NO_FCOE(bp)) | |
6282 | /* Configure rx_mode of FCoE Queue */ | |
6283 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
6284 | ||
6285 | rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, | |
6286 | &tx_accept_flags); | |
6287 | if (rc) | |
6288 | return rc; | |
6289 | ||
619c5cb6 VZ |
6290 | __set_bit(RAMROD_RX, &ramrod_flags); |
6291 | __set_bit(RAMROD_TX, &ramrod_flags); | |
6292 | ||
924d75ab YM |
6293 | return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, |
6294 | rx_accept_flags, tx_accept_flags, | |
6295 | ramrod_flags); | |
619c5cb6 VZ |
6296 | } |
6297 | ||
6298 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
6299 | { | |
6300 | int i; | |
6301 | ||
523224a3 DK |
6302 | /* Zero this manually as its initialization is |
6303 | currently missing in the initTool */ | |
6304 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 6305 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 6306 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 6307 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6308 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
6309 | CHIP_INT_MODE_IS_BC(bp) ? | |
6310 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
6311 | } | |
523224a3 | 6312 | } |
8a1c38d1 | 6313 | |
471de716 EG |
6314 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
6315 | { | |
6316 | switch (load_code) { | |
6317 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 6318 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
6319 | bnx2x_init_internal_common(bp); |
6320 | /* no break */ | |
6321 | ||
6322 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 6323 | /* nothing to do */ |
471de716 EG |
6324 | /* no break */ |
6325 | ||
6326 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
6327 | /* internal memory per function is |
6328 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
6329 | break; |
6330 | ||
6331 | default: | |
6332 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
6333 | break; | |
6334 | } | |
6335 | } | |
6336 | ||
619c5cb6 | 6337 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 6338 | { |
55c11941 | 6339 | return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 | 6340 | } |
523224a3 | 6341 | |
619c5cb6 VZ |
6342 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
6343 | { | |
55c11941 | 6344 | return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 VZ |
6345 | } |
6346 | ||
1191cb83 | 6347 | static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) |
619c5cb6 VZ |
6348 | { |
6349 | if (CHIP_IS_E1x(fp->bp)) | |
6350 | return BP_L_ID(fp->bp) + fp->index; | |
6351 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
6352 | return bnx2x_fp_igu_sb_id(fp); | |
6353 | } | |
6354 | ||
6383c0b3 | 6355 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
6356 | { |
6357 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 6358 | u8 cos; |
619c5cb6 | 6359 | unsigned long q_type = 0; |
6383c0b3 | 6360 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 6361 | fp->rx_queue = fp_idx; |
b3b83c3f | 6362 | fp->cid = fp_idx; |
619c5cb6 VZ |
6363 | fp->cl_id = bnx2x_fp_cl_id(fp); |
6364 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
6365 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 6366 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
6367 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
6368 | ||
523224a3 | 6369 | /* init shortcut */ |
619c5cb6 | 6370 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
7a752993 | 6371 | |
16a5fd92 | 6372 | /* Setup SB indices */ |
523224a3 | 6373 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; |
523224a3 | 6374 | |
619c5cb6 VZ |
6375 | /* Configure Queue State object */ |
6376 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
6377 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
6378 | |
6379 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
6380 | ||
6381 | /* init tx data */ | |
6382 | for_each_cos_in_tx_queue(fp, cos) { | |
65565884 MS |
6383 | bnx2x_init_txdata(bp, fp->txdata_ptr[cos], |
6384 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), | |
6385 | FP_COS_TO_TXQ(fp, cos, bp), | |
6386 | BNX2X_TX_SB_INDEX_BASE + cos, fp); | |
6387 | cids[cos] = fp->txdata_ptr[cos]->cid; | |
6383c0b3 AE |
6388 | } |
6389 | ||
ad5afc89 AE |
6390 | /* nothing more for vf to do here */ |
6391 | if (IS_VF(bp)) | |
6392 | return; | |
6393 | ||
6394 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
6395 | fp->fw_sb_id, fp->igu_sb_id); | |
6396 | bnx2x_update_fpsb_idx(fp); | |
15192a8c BW |
6397 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, |
6398 | fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 6399 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 VZ |
6400 | |
6401 | /** | |
6402 | * Configure classification DBs: Always enable Tx switching | |
6403 | */ | |
6404 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
6405 | ||
ad5afc89 AE |
6406 | DP(NETIF_MSG_IFUP, |
6407 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
6408 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
6409 | fp->igu_sb_id); | |
523224a3 DK |
6410 | } |
6411 | ||
1191cb83 ED |
6412 | static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) |
6413 | { | |
6414 | int i; | |
6415 | ||
6416 | for (i = 1; i <= NUM_TX_RINGS; i++) { | |
6417 | struct eth_tx_next_bd *tx_next_bd = | |
6418 | &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
6419 | ||
6420 | tx_next_bd->addr_hi = | |
6421 | cpu_to_le32(U64_HI(txdata->tx_desc_mapping + | |
6422 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
6423 | tx_next_bd->addr_lo = | |
6424 | cpu_to_le32(U64_LO(txdata->tx_desc_mapping + | |
6425 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
6426 | } | |
6427 | ||
639d65b8 YM |
6428 | *txdata->tx_cons_sb = cpu_to_le16(0); |
6429 | ||
1191cb83 ED |
6430 | SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); |
6431 | txdata->tx_db.data.zero_fill1 = 0; | |
6432 | txdata->tx_db.data.prod = 0; | |
6433 | ||
6434 | txdata->tx_pkt_prod = 0; | |
6435 | txdata->tx_pkt_cons = 0; | |
6436 | txdata->tx_bd_prod = 0; | |
6437 | txdata->tx_bd_cons = 0; | |
6438 | txdata->tx_pkt = 0; | |
6439 | } | |
6440 | ||
55c11941 MS |
6441 | static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) |
6442 | { | |
6443 | int i; | |
6444 | ||
6445 | for_each_tx_queue_cnic(bp, i) | |
6446 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); | |
6447 | } | |
d76a6111 | 6448 | |
1191cb83 ED |
6449 | static void bnx2x_init_tx_rings(struct bnx2x *bp) |
6450 | { | |
6451 | int i; | |
6452 | u8 cos; | |
6453 | ||
55c11941 | 6454 | for_each_eth_queue(bp, i) |
1191cb83 | 6455 | for_each_cos_in_tx_queue(&bp->fp[i], cos) |
65565884 | 6456 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); |
1191cb83 ED |
6457 | } |
6458 | ||
a8f47eb7 | 6459 | static void bnx2x_init_fcoe_fp(struct bnx2x *bp) |
6460 | { | |
6461 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
6462 | unsigned long q_type = 0; | |
6463 | ||
6464 | bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); | |
6465 | bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, | |
6466 | BNX2X_FCOE_ETH_CL_ID_IDX); | |
6467 | bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); | |
6468 | bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; | |
6469 | bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; | |
6470 | bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; | |
6471 | bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), | |
6472 | fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, | |
6473 | fp); | |
6474 | ||
6475 | DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); | |
6476 | ||
6477 | /* qZone id equals to FW (per path) client id */ | |
6478 | bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); | |
6479 | /* init shortcut */ | |
6480 | bnx2x_fcoe(bp, ustorm_rx_prods_offset) = | |
6481 | bnx2x_rx_ustorm_prods_offset(fp); | |
6482 | ||
6483 | /* Configure Queue State object */ | |
6484 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
6485 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6486 | ||
6487 | /* No multi-CoS for FCoE L2 client */ | |
6488 | BUG_ON(fp->max_cos != 1); | |
6489 | ||
6490 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, | |
6491 | &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6492 | bnx2x_sp_mapping(bp, q_rdata), q_type); | |
6493 | ||
6494 | DP(NETIF_MSG_IFUP, | |
6495 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
6496 | fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
6497 | fp->igu_sb_id); | |
6498 | } | |
6499 | ||
55c11941 | 6500 | void bnx2x_nic_init_cnic(struct bnx2x *bp) |
a2fbb9ea | 6501 | { |
ec6ba945 VZ |
6502 | if (!NO_FCOE(bp)) |
6503 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
6504 | |
6505 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
6506 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 6507 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 6508 | |
55c11941 MS |
6509 | /* ensure status block indices were read */ |
6510 | rmb(); | |
6511 | bnx2x_init_rx_rings_cnic(bp); | |
6512 | bnx2x_init_tx_rings_cnic(bp); | |
6513 | ||
6514 | /* flush all */ | |
6515 | mb(); | |
6516 | mmiowb(); | |
6517 | } | |
a2fbb9ea | 6518 | |
ecf01c22 | 6519 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp) |
55c11941 MS |
6520 | { |
6521 | int i; | |
6522 | ||
ecf01c22 | 6523 | /* Setup NIC internals and enable interrupts */ |
55c11941 MS |
6524 | for_each_eth_queue(bp, i) |
6525 | bnx2x_init_eth_fp(bp, i); | |
ad5afc89 AE |
6526 | |
6527 | /* ensure status block indices were read */ | |
6528 | rmb(); | |
6529 | bnx2x_init_rx_rings(bp); | |
6530 | bnx2x_init_tx_rings(bp); | |
6531 | ||
ecf01c22 YM |
6532 | if (IS_PF(bp)) { |
6533 | /* Initialize MOD_ABS interrupts */ | |
6534 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
6535 | bp->common.shmem_base, | |
6536 | bp->common.shmem2_base, BP_PORT(bp)); | |
ad5afc89 | 6537 | |
ecf01c22 YM |
6538 | /* initialize the default status block and sp ring */ |
6539 | bnx2x_init_def_sb(bp); | |
6540 | bnx2x_update_dsb_idx(bp); | |
6541 | bnx2x_init_sp_ring(bp); | |
3cdeec22 YM |
6542 | } else { |
6543 | bnx2x_memset_stats(bp); | |
ecf01c22 YM |
6544 | } |
6545 | } | |
16119785 | 6546 | |
ecf01c22 YM |
6547 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) |
6548 | { | |
523224a3 | 6549 | bnx2x_init_eq_ring(bp); |
471de716 | 6550 | bnx2x_init_internal(bp, load_code); |
523224a3 | 6551 | bnx2x_pf_init(bp); |
0ef00459 EG |
6552 | bnx2x_stats_init(bp); |
6553 | ||
0ef00459 EG |
6554 | /* flush all before enabling interrupts */ |
6555 | mb(); | |
6556 | mmiowb(); | |
6557 | ||
615f8fd9 | 6558 | bnx2x_int_enable(bp); |
eb8da205 EG |
6559 | |
6560 | /* Check for SPIO5 */ | |
6561 | bnx2x_attn_int_deasserted0(bp, | |
6562 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
6563 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
6564 | } |
6565 | ||
ecf01c22 | 6566 | /* gzip service functions */ |
a2fbb9ea ET |
6567 | static int bnx2x_gunzip_init(struct bnx2x *bp) |
6568 | { | |
1a983142 FT |
6569 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
6570 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
6571 | if (bp->gunzip_buf == NULL) |
6572 | goto gunzip_nomem1; | |
6573 | ||
6574 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
6575 | if (bp->strm == NULL) | |
6576 | goto gunzip_nomem2; | |
6577 | ||
7ab24bfd | 6578 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
6579 | if (bp->strm->workspace == NULL) |
6580 | goto gunzip_nomem3; | |
6581 | ||
6582 | return 0; | |
6583 | ||
6584 | gunzip_nomem3: | |
6585 | kfree(bp->strm); | |
6586 | bp->strm = NULL; | |
6587 | ||
6588 | gunzip_nomem2: | |
1a983142 FT |
6589 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6590 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6591 | bp->gunzip_buf = NULL; |
6592 | ||
6593 | gunzip_nomem1: | |
51c1a580 | 6594 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
a2fbb9ea ET |
6595 | return -ENOMEM; |
6596 | } | |
6597 | ||
6598 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
6599 | { | |
b3b83c3f | 6600 | if (bp->strm) { |
7ab24bfd | 6601 | vfree(bp->strm->workspace); |
b3b83c3f DK |
6602 | kfree(bp->strm); |
6603 | bp->strm = NULL; | |
6604 | } | |
a2fbb9ea ET |
6605 | |
6606 | if (bp->gunzip_buf) { | |
1a983142 FT |
6607 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6608 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6609 | bp->gunzip_buf = NULL; |
6610 | } | |
6611 | } | |
6612 | ||
94a78b79 | 6613 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
6614 | { |
6615 | int n, rc; | |
6616 | ||
6617 | /* check gzip header */ | |
94a78b79 VZ |
6618 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
6619 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 6620 | return -EINVAL; |
94a78b79 | 6621 | } |
a2fbb9ea ET |
6622 | |
6623 | n = 10; | |
6624 | ||
34f80b04 | 6625 | #define FNAME 0x8 |
a2fbb9ea ET |
6626 | |
6627 | if (zbuf[3] & FNAME) | |
6628 | while ((zbuf[n++] != 0) && (n < len)); | |
6629 | ||
94a78b79 | 6630 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
6631 | bp->strm->avail_in = len - n; |
6632 | bp->strm->next_out = bp->gunzip_buf; | |
6633 | bp->strm->avail_out = FW_BUF_SIZE; | |
6634 | ||
6635 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
6636 | if (rc != Z_OK) | |
6637 | return rc; | |
6638 | ||
6639 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
6640 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
6641 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
6642 | bp->strm->msg); | |
a2fbb9ea ET |
6643 | |
6644 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
6645 | if (bp->gunzip_outlen & 0x3) | |
51c1a580 MS |
6646 | netdev_err(bp->dev, |
6647 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", | |
cdaa7cb8 | 6648 | bp->gunzip_outlen); |
a2fbb9ea ET |
6649 | bp->gunzip_outlen >>= 2; |
6650 | ||
6651 | zlib_inflateEnd(bp->strm); | |
6652 | ||
6653 | if (rc == Z_STREAM_END) | |
6654 | return 0; | |
6655 | ||
6656 | return rc; | |
6657 | } | |
6658 | ||
6659 | /* nic load/unload */ | |
6660 | ||
6661 | /* | |
34f80b04 | 6662 | * General service functions |
a2fbb9ea ET |
6663 | */ |
6664 | ||
6665 | /* send a NIG loopback debug packet */ | |
6666 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
6667 | { | |
a2fbb9ea | 6668 | u32 wb_write[3]; |
a2fbb9ea ET |
6669 | |
6670 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
6671 | wb_write[0] = 0x55555555; |
6672 | wb_write[1] = 0x55555555; | |
34f80b04 | 6673 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 6674 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6675 | |
6676 | /* NON-IP protocol */ | |
a2fbb9ea ET |
6677 | wb_write[0] = 0x09000000; |
6678 | wb_write[1] = 0x55555555; | |
34f80b04 | 6679 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 6680 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6681 | } |
6682 | ||
6683 | /* some of the internal memories | |
6684 | * are not directly readable from the driver | |
6685 | * to test them we send debug packets | |
6686 | */ | |
6687 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
6688 | { | |
6689 | int factor; | |
6690 | int count, i; | |
6691 | u32 val = 0; | |
6692 | ||
ad8d3948 | 6693 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 6694 | factor = 120; |
ad8d3948 EG |
6695 | else if (CHIP_REV_IS_EMUL(bp)) |
6696 | factor = 200; | |
6697 | else | |
a2fbb9ea | 6698 | factor = 1; |
a2fbb9ea | 6699 | |
a2fbb9ea ET |
6700 | /* Disable inputs of parser neighbor blocks */ |
6701 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6702 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6703 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6704 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6705 | |
6706 | /* Write 0 to parser credits for CFC search request */ | |
6707 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6708 | ||
6709 | /* send Ethernet packet */ | |
6710 | bnx2x_lb_pckt(bp); | |
6711 | ||
6712 | /* TODO do i reset NIG statistic? */ | |
6713 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6714 | count = 1000 * factor; | |
6715 | while (count) { | |
34f80b04 | 6716 | |
a2fbb9ea ET |
6717 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6718 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6719 | if (val == 0x10) |
6720 | break; | |
6721 | ||
639d65b8 | 6722 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6723 | count--; |
6724 | } | |
6725 | if (val != 0x10) { | |
6726 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6727 | return -1; | |
6728 | } | |
6729 | ||
6730 | /* Wait until PRS register shows 1 packet */ | |
6731 | count = 1000 * factor; | |
6732 | while (count) { | |
6733 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
6734 | if (val == 1) |
6735 | break; | |
6736 | ||
639d65b8 | 6737 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6738 | count--; |
6739 | } | |
6740 | if (val != 0x1) { | |
6741 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6742 | return -2; | |
6743 | } | |
6744 | ||
6745 | /* Reset and init BRB, PRS */ | |
34f80b04 | 6746 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 6747 | msleep(50); |
34f80b04 | 6748 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 6749 | msleep(50); |
619c5cb6 VZ |
6750 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6751 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
6752 | |
6753 | DP(NETIF_MSG_HW, "part2\n"); | |
6754 | ||
6755 | /* Disable inputs of parser neighbor blocks */ | |
6756 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6757 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6758 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6759 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6760 | |
6761 | /* Write 0 to parser credits for CFC search request */ | |
6762 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6763 | ||
6764 | /* send 10 Ethernet packets */ | |
6765 | for (i = 0; i < 10; i++) | |
6766 | bnx2x_lb_pckt(bp); | |
6767 | ||
6768 | /* Wait until NIG register shows 10 + 1 | |
6769 | packets of size 11*0x10 = 0xb0 */ | |
6770 | count = 1000 * factor; | |
6771 | while (count) { | |
34f80b04 | 6772 | |
a2fbb9ea ET |
6773 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6774 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6775 | if (val == 0xb0) |
6776 | break; | |
6777 | ||
639d65b8 | 6778 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6779 | count--; |
6780 | } | |
6781 | if (val != 0xb0) { | |
6782 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6783 | return -3; | |
6784 | } | |
6785 | ||
6786 | /* Wait until PRS register shows 2 packets */ | |
6787 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6788 | if (val != 2) | |
6789 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6790 | ||
6791 | /* Write 1 to parser credits for CFC search request */ | |
6792 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
6793 | ||
6794 | /* Wait until PRS register shows 3 packets */ | |
6795 | msleep(10 * factor); | |
6796 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6797 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6798 | if (val != 3) | |
6799 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6800 | ||
6801 | /* clear NIG EOP FIFO */ | |
6802 | for (i = 0; i < 11; i++) | |
6803 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
6804 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
6805 | if (val != 1) { | |
6806 | BNX2X_ERR("clear of NIG failed\n"); | |
6807 | return -4; | |
6808 | } | |
6809 | ||
6810 | /* Reset and init BRB, PRS, NIG */ | |
6811 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
6812 | msleep(50); | |
6813 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
6814 | msleep(50); | |
619c5cb6 VZ |
6815 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6816 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
55c11941 MS |
6817 | if (!CNIC_SUPPORT(bp)) |
6818 | /* set NIC mode */ | |
6819 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
a2fbb9ea ET |
6820 | |
6821 | /* Enable inputs of parser neighbor blocks */ | |
6822 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
6823 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
6824 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 6825 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
6826 | |
6827 | DP(NETIF_MSG_HW, "done\n"); | |
6828 | ||
6829 | return 0; /* OK */ | |
6830 | } | |
6831 | ||
4a33bc03 | 6832 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea | 6833 | { |
b343d002 YM |
6834 | u32 val; |
6835 | ||
a2fbb9ea | 6836 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); |
619c5cb6 | 6837 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6838 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
6839 | else | |
6840 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
6841 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
6842 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
6843 | /* |
6844 | * mask read length error interrupts in brb for parser | |
6845 | * (parsing unit and 'checksum and crc' unit) | |
6846 | * these errors are legal (PU reads fixed length and CAC can cause | |
6847 | * read length error on truncated packets) | |
6848 | */ | |
6849 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
6850 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
6851 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
6852 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
6853 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
6854 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
6855 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
6856 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6857 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
6858 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
6859 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
6860 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
6861 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6862 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
6863 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
6864 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
6865 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
6866 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
6867 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 6868 | |
b343d002 YM |
6869 | val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
6870 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | | |
6871 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; | |
6872 | if (!CHIP_IS_E1x(bp)) | |
6873 | val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | | |
6874 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; | |
6875 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); | |
6876 | ||
a2fbb9ea ET |
6877 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
6878 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
6879 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 6880 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
6881 | |
6882 | if (!CHIP_IS_E1x(bp)) | |
6883 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
6884 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
6885 | ||
a2fbb9ea ET |
6886 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
6887 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 6888 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 6889 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
6890 | } |
6891 | ||
81f75bbf EG |
6892 | static void bnx2x_reset_common(struct bnx2x *bp) |
6893 | { | |
619c5cb6 VZ |
6894 | u32 val = 0x1400; |
6895 | ||
81f75bbf EG |
6896 | /* reset_common */ |
6897 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6898 | 0xd3ffff7f); | |
619c5cb6 VZ |
6899 | |
6900 | if (CHIP_IS_E3(bp)) { | |
6901 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6902 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6903 | } | |
6904 | ||
6905 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
6906 | } | |
6907 | ||
6908 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
6909 | { | |
6910 | bp->dmae_ready = 0; | |
6911 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
6912 | } |
6913 | ||
573f2035 EG |
6914 | static void bnx2x_init_pxp(struct bnx2x *bp) |
6915 | { | |
6916 | u16 devctl; | |
6917 | int r_order, w_order; | |
6918 | ||
2a80eebc | 6919 | pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
6920 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
6921 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
6922 | if (bp->mrrs == -1) | |
6923 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
6924 | else { | |
6925 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
6926 | r_order = bp->mrrs; | |
6927 | } | |
6928 | ||
6929 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
6930 | } | |
fd4ef40d EG |
6931 | |
6932 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
6933 | { | |
2145a920 | 6934 | int is_required; |
fd4ef40d | 6935 | u32 val; |
2145a920 | 6936 | int port; |
fd4ef40d | 6937 | |
2145a920 VZ |
6938 | if (BP_NOMCP(bp)) |
6939 | return; | |
6940 | ||
6941 | is_required = 0; | |
fd4ef40d EG |
6942 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
6943 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
6944 | ||
6945 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
6946 | is_required = 1; | |
6947 | ||
6948 | /* | |
6949 | * The fan failure mechanism is usually related to the PHY type since | |
6950 | * the power consumption of the board is affected by the PHY. Currently, | |
6951 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
6952 | */ | |
6953 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
6954 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 6955 | is_required |= |
d90d96ba YR |
6956 | bnx2x_fan_failure_det_req( |
6957 | bp, | |
6958 | bp->common.shmem_base, | |
a22f0788 | 6959 | bp->common.shmem2_base, |
d90d96ba | 6960 | port); |
fd4ef40d EG |
6961 | } |
6962 | ||
6963 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
6964 | ||
6965 | if (is_required == 0) | |
6966 | return; | |
6967 | ||
6968 | /* Fan failure is indicated by SPIO 5 */ | |
d6d99a3f | 6969 | bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); |
fd4ef40d EG |
6970 | |
6971 | /* set to active low mode */ | |
6972 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
d6d99a3f | 6973 | val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
6974 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
6975 | ||
6976 | /* enable interrupt to signal the IGU */ | |
6977 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 6978 | val |= MISC_SPIO_SPIO5; |
fd4ef40d EG |
6979 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); |
6980 | } | |
6981 | ||
c9ee9206 | 6982 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
6983 | { |
6984 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
6985 | val &= ~IGU_PF_CONF_FUNC_EN; | |
6986 | ||
6987 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
6988 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6989 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
6990 | } | |
6991 | ||
1191cb83 | 6992 | static void bnx2x__common_init_phy(struct bnx2x *bp) |
619c5cb6 VZ |
6993 | { |
6994 | u32 shmem_base[2], shmem2_base[2]; | |
b884d95b YR |
6995 | /* Avoid common init in case MFW supports LFA */ |
6996 | if (SHMEM2_RD(bp, size) > | |
6997 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
6998 | return; | |
619c5cb6 VZ |
6999 | shmem_base[0] = bp->common.shmem_base; |
7000 | shmem2_base[0] = bp->common.shmem2_base; | |
7001 | if (!CHIP_IS_E1x(bp)) { | |
7002 | shmem_base[1] = | |
7003 | SHMEM2_RD(bp, other_shmem_base_addr); | |
7004 | shmem2_base[1] = | |
7005 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
7006 | } | |
7007 | bnx2x_acquire_phy_lock(bp); | |
7008 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
7009 | bp->common.chip_id); | |
7010 | bnx2x_release_phy_lock(bp); | |
7011 | } | |
7012 | ||
04860eb7 MC |
7013 | static void bnx2x_config_endianity(struct bnx2x *bp, u32 val) |
7014 | { | |
7015 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); | |
7016 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); | |
7017 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); | |
7018 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); | |
7019 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); | |
7020 | ||
7021 | /* make sure this value is 0 */ | |
7022 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
7023 | ||
7024 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); | |
7025 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); | |
7026 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); | |
7027 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); | |
7028 | } | |
7029 | ||
7030 | static void bnx2x_set_endianity(struct bnx2x *bp) | |
7031 | { | |
7032 | #ifdef __BIG_ENDIAN | |
7033 | bnx2x_config_endianity(bp, 1); | |
7034 | #else | |
7035 | bnx2x_config_endianity(bp, 0); | |
7036 | #endif | |
7037 | } | |
7038 | ||
7039 | static void bnx2x_reset_endianity(struct bnx2x *bp) | |
7040 | { | |
7041 | bnx2x_config_endianity(bp, 0); | |
7042 | } | |
7043 | ||
619c5cb6 VZ |
7044 | /** |
7045 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
7046 | * | |
7047 | * @bp: driver handle | |
7048 | */ | |
7049 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 7050 | { |
619c5cb6 | 7051 | u32 val; |
a2fbb9ea | 7052 | |
51c1a580 | 7053 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 7054 | |
2031bd3a | 7055 | /* |
2de67439 | 7056 | * take the RESET lock to protect undi_unload flow from accessing |
2031bd3a DK |
7057 | * registers while we're resetting the chip |
7058 | */ | |
7a06a122 | 7059 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 7060 | |
81f75bbf | 7061 | bnx2x_reset_common(bp); |
34f80b04 | 7062 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 7063 | |
619c5cb6 VZ |
7064 | val = 0xfffc; |
7065 | if (CHIP_IS_E3(bp)) { | |
7066 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
7067 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
7068 | } | |
7069 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
7070 | ||
7a06a122 | 7071 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 7072 | |
619c5cb6 | 7073 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 7074 | |
619c5cb6 VZ |
7075 | if (!CHIP_IS_E1x(bp)) { |
7076 | u8 abs_func_id; | |
f2e0899f DK |
7077 | |
7078 | /** | |
7079 | * 4-port mode or 2-port mode we need to turn of master-enable | |
7080 | * for everyone, after that, turn it back on for self. | |
7081 | * so, we disregard multi-function or not, and always disable | |
7082 | * for all functions on the given path, this means 0,2,4,6 for | |
7083 | * path 0 and 1,3,5,7 for path 1 | |
7084 | */ | |
619c5cb6 VZ |
7085 | for (abs_func_id = BP_PATH(bp); |
7086 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
7087 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
7088 | REG_WR(bp, |
7089 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
7090 | 1); | |
7091 | continue; | |
7092 | } | |
7093 | ||
619c5cb6 | 7094 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
7095 | /* clear pf enable */ |
7096 | bnx2x_pf_disable(bp); | |
7097 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
7098 | } | |
7099 | } | |
a2fbb9ea | 7100 | |
619c5cb6 | 7101 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
7102 | if (CHIP_IS_E1(bp)) { |
7103 | /* enable HW interrupt from PXP on USDM overflow | |
7104 | bit 16 on INT_MASK_0 */ | |
7105 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
7106 | } | |
a2fbb9ea | 7107 | |
619c5cb6 | 7108 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 7109 | bnx2x_init_pxp(bp); |
04860eb7 | 7110 | bnx2x_set_endianity(bp); |
523224a3 DK |
7111 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
7112 | ||
34f80b04 EG |
7113 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
7114 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 7115 | |
34f80b04 EG |
7116 | /* let the HW do it's magic ... */ |
7117 | msleep(100); | |
7118 | /* finish PXP init */ | |
7119 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
7120 | if (val != 1) { | |
7121 | BNX2X_ERR("PXP2 CFG failed\n"); | |
7122 | return -EBUSY; | |
7123 | } | |
7124 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
7125 | if (val != 1) { | |
7126 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
7127 | return -EBUSY; | |
7128 | } | |
a2fbb9ea | 7129 | |
f2e0899f DK |
7130 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
7131 | * have entries with value "0" and valid bit on. | |
7132 | * This needs to be done by the first PF that is loaded in a path | |
7133 | * (i.e. common phase) | |
7134 | */ | |
619c5cb6 VZ |
7135 | if (!CHIP_IS_E1x(bp)) { |
7136 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
7137 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
7138 | * This occurs when a different function (func2,3) is being marked | |
7139 | * as "scan-off". Real-life scenario for example: if a driver is being | |
7140 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
7141 | * the ilt, translate to a logical address and send a request to read/write. | |
7142 | * Since the ilt for the function that is down is not valid, this will cause | |
7143 | * a translation error which is unrecoverable. | |
7144 | * The Workaround is intended to make sure that when this happens nothing fatal | |
7145 | * will occur. The workaround: | |
7146 | * 1. First PF driver which loads on a path will: | |
7147 | * a. After taking the chip out of reset, by using pretend, | |
7148 | * it will write "0" to the following registers of | |
7149 | * the other vnics. | |
7150 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
7151 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
7152 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
7153 | * And for itself it will write '1' to | |
7154 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
7155 | * dmae-operations (writing to pram for example.) | |
7156 | * note: can be done for only function 6,7 but cleaner this | |
7157 | * way. | |
7158 | * b. Write zero+valid to the entire ILT. | |
7159 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
7160 | * VNIC3 (of that port). The range allocated will be the | |
7161 | * entire ILT. This is needed to prevent ILT range error. | |
7162 | * 2. Any PF driver load flow: | |
7163 | * a. ILT update with the physical addresses of the allocated | |
7164 | * logical pages. | |
7165 | * b. Wait 20msec. - note that this timeout is needed to make | |
7166 | * sure there are no requests in one of the PXP internal | |
7167 | * queues with "old" ILT addresses. | |
7168 | * c. PF enable in the PGLC. | |
7169 | * d. Clear the was_error of the PF in the PGLC. (could have | |
2de67439 | 7170 | * occurred while driver was down) |
619c5cb6 VZ |
7171 | * e. PF enable in the CFC (WEAK + STRONG) |
7172 | * f. Timers scan enable | |
7173 | * 3. PF driver unload flow: | |
7174 | * a. Clear the Timers scan_en. | |
7175 | * b. Polling for scan_on=0 for that PF. | |
7176 | * c. Clear the PF enable bit in the PXP. | |
7177 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
7178 | * e. Write zero+valid to all ILT entries (The valid bit must | |
7179 | * stay set) | |
7180 | * f. If this is VNIC 3 of a port then also init | |
7181 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
16a5fd92 | 7182 | * to the last entry in the ILT. |
619c5cb6 VZ |
7183 | * |
7184 | * Notes: | |
7185 | * Currently the PF error in the PGLC is non recoverable. | |
7186 | * In the future the there will be a recovery routine for this error. | |
7187 | * Currently attention is masked. | |
7188 | * Having an MCP lock on the load/unload process does not guarantee that | |
7189 | * there is no Timer disable during Func6/7 enable. This is because the | |
7190 | * Timers scan is currently being cleared by the MCP on FLR. | |
7191 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
7192 | * there is error before clearing it. But the flow above is simpler and | |
7193 | * more general. | |
7194 | * All ILT entries are written by zero+valid and not just PF6/7 | |
7195 | * ILT entries since in the future the ILT entries allocation for | |
7196 | * PF-s might be dynamic. | |
7197 | */ | |
f2e0899f DK |
7198 | struct ilt_client_info ilt_cli; |
7199 | struct bnx2x_ilt ilt; | |
7200 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
7201 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
7202 | ||
b595076a | 7203 | /* initialize dummy TM client */ |
f2e0899f DK |
7204 | ilt_cli.start = 0; |
7205 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
7206 | ilt_cli.client_num = ILT_CLIENT_TM; | |
7207 | ||
7208 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
7209 | * Step 2: set the timers first/last ilt entry to point | |
7210 | * to the entire range to prevent ILT range error for 3rd/4th | |
2de67439 | 7211 | * vnic (this code assumes existence of the vnic) |
f2e0899f DK |
7212 | * |
7213 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
7214 | * with dummy TM client | |
7215 | * | |
7216 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
7217 | * and his brother are split registers | |
7218 | */ | |
7219 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
7220 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
7221 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
7222 | ||
7223 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
7224 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
7225 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
7226 | } | |
7227 | ||
34f80b04 EG |
7228 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
7229 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 7230 | |
619c5cb6 | 7231 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7232 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
7233 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 7234 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 7235 | |
619c5cb6 | 7236 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
7237 | |
7238 | /* let the HW do it's magic ... */ | |
7239 | do { | |
7240 | msleep(200); | |
7241 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
7242 | } while (factor-- && (val != 1)); | |
7243 | ||
7244 | if (val != 1) { | |
7245 | BNX2X_ERR("ATC_INIT failed\n"); | |
7246 | return -EBUSY; | |
7247 | } | |
7248 | } | |
7249 | ||
619c5cb6 | 7250 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 7251 | |
b56e9670 AE |
7252 | bnx2x_iov_init_dmae(bp); |
7253 | ||
34f80b04 EG |
7254 | /* clean the DMAE memory */ |
7255 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
7256 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
7257 | ||
7258 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
7259 | ||
7260 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
7261 | ||
7262 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 7263 | |
619c5cb6 | 7264 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 7265 | |
34f80b04 EG |
7266 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
7267 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
7268 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
7269 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
7270 | ||
619c5cb6 | 7271 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 7272 | |
523224a3 DK |
7273 | /* QM queues pointers table */ |
7274 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
7275 | ||
34f80b04 EG |
7276 | /* soft reset pulse */ |
7277 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
7278 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 7279 | |
55c11941 MS |
7280 | if (CNIC_SUPPORT(bp)) |
7281 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); | |
a2fbb9ea | 7282 | |
619c5cb6 | 7283 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
b9871bcf | 7284 | |
619c5cb6 | 7285 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
7286 | /* enable hw interrupt from doorbell Q */ |
7287 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 7288 | |
619c5cb6 | 7289 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 7290 | |
619c5cb6 | 7291 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 7292 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 7293 | |
f2e0899f | 7294 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 7295 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 7296 | |
a3348722 BW |
7297 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { |
7298 | if (IS_MF_AFEX(bp)) { | |
7299 | /* configure that VNTag and VLAN headers must be | |
7300 | * received in afex mode | |
7301 | */ | |
7302 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); | |
7303 | REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); | |
7304 | REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); | |
7305 | REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); | |
7306 | REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); | |
7307 | } else { | |
7308 | /* Bit-map indicating which L2 hdrs may appear | |
7309 | * after the basic Ethernet header | |
7310 | */ | |
7311 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
7312 | bp->path_has_ovlan ? 7 : 6); | |
7313 | } | |
7314 | } | |
a2fbb9ea | 7315 | |
619c5cb6 VZ |
7316 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
7317 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
7318 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
7319 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 7320 | |
619c5cb6 VZ |
7321 | if (!CHIP_IS_E1x(bp)) { |
7322 | /* reset VFC memories */ | |
7323 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
7324 | VFC_MEMORIES_RST_REG_CAM_RST | | |
7325 | VFC_MEMORIES_RST_REG_RAM_RST); | |
7326 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
7327 | VFC_MEMORIES_RST_REG_CAM_RST | | |
7328 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 7329 | |
619c5cb6 VZ |
7330 | msleep(20); |
7331 | } | |
a2fbb9ea | 7332 | |
619c5cb6 VZ |
7333 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
7334 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
7335 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
7336 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 7337 | |
34f80b04 EG |
7338 | /* sync semi rtc */ |
7339 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
7340 | 0x80000000); | |
7341 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
7342 | 0x80000000); | |
a2fbb9ea | 7343 | |
619c5cb6 VZ |
7344 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
7345 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
7346 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 7347 | |
a3348722 BW |
7348 | if (!CHIP_IS_E1x(bp)) { |
7349 | if (IS_MF_AFEX(bp)) { | |
7350 | /* configure that VNTag and VLAN headers must be | |
7351 | * sent in afex mode | |
7352 | */ | |
7353 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); | |
7354 | REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); | |
7355 | REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); | |
7356 | REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); | |
7357 | REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); | |
7358 | } else { | |
7359 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
7360 | bp->path_has_ovlan ? 7 : 6); | |
7361 | } | |
7362 | } | |
f2e0899f | 7363 | |
34f80b04 | 7364 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 7365 | |
619c5cb6 VZ |
7366 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
7367 | ||
55c11941 MS |
7368 | if (CNIC_SUPPORT(bp)) { |
7369 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
7370 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
7371 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
7372 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
7373 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
7374 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
7375 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
7376 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
7377 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
7378 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
7379 | } | |
34f80b04 | 7380 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 7381 | |
34f80b04 EG |
7382 | if (sizeof(union cdu_context) != 1024) |
7383 | /* we currently assume that a context is 1024 bytes */ | |
51c1a580 MS |
7384 | dev_alert(&bp->pdev->dev, |
7385 | "please adjust the size of cdu_context(%ld)\n", | |
7386 | (long)sizeof(union cdu_context)); | |
a2fbb9ea | 7387 | |
619c5cb6 | 7388 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
7389 | val = (4 << 24) + (0 << 12) + 1024; |
7390 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 7391 | |
619c5cb6 | 7392 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 7393 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
7394 | /* enable context validation interrupt from CFC */ |
7395 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
7396 | ||
7397 | /* set the thresholds to prevent CFC/CDU race */ | |
7398 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 7399 | |
619c5cb6 | 7400 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 7401 | |
619c5cb6 | 7402 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
7403 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
7404 | ||
619c5cb6 VZ |
7405 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
7406 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 7407 | |
34f80b04 EG |
7408 | /* Reset PCIE errors for debug */ |
7409 | REG_WR(bp, 0x2814, 0xffffffff); | |
7410 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 7411 | |
619c5cb6 | 7412 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7413 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
7414 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
7415 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
7416 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
7417 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
7418 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
7419 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
7420 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
7421 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
7422 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
7423 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
7424 | } | |
7425 | ||
619c5cb6 | 7426 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 7427 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
7428 | /* in E3 this done in per-port section */ |
7429 | if (!CHIP_IS_E3(bp)) | |
7430 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 7431 | } |
619c5cb6 VZ |
7432 | if (CHIP_IS_E1H(bp)) |
7433 | /* not applicable for E2 (and above ...) */ | |
7434 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
7435 | |
7436 | if (CHIP_REV_IS_SLOW(bp)) | |
7437 | msleep(200); | |
7438 | ||
7439 | /* finish CFC init */ | |
7440 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
7441 | if (val != 1) { | |
7442 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
7443 | return -EBUSY; | |
7444 | } | |
7445 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
7446 | if (val != 1) { | |
7447 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
7448 | return -EBUSY; | |
7449 | } | |
7450 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
7451 | if (val != 1) { | |
7452 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
7453 | return -EBUSY; | |
7454 | } | |
7455 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 7456 | |
f2e0899f DK |
7457 | if (CHIP_IS_E1(bp)) { |
7458 | /* read NIG statistic | |
7459 | to see if this is our first up since powerup */ | |
7460 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
7461 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 7462 | |
f2e0899f DK |
7463 | /* do internal memory self test */ |
7464 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
7465 | BNX2X_ERR("internal mem self test failed\n"); | |
7466 | return -EBUSY; | |
7467 | } | |
34f80b04 EG |
7468 | } |
7469 | ||
fd4ef40d EG |
7470 | bnx2x_setup_fan_failure_detection(bp); |
7471 | ||
34f80b04 EG |
7472 | /* clear PXP2 attentions */ |
7473 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 7474 | |
4a33bc03 | 7475 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 7476 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 7477 | |
6bbca910 | 7478 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
7479 | if (CHIP_IS_E1x(bp)) |
7480 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
7481 | } else |
7482 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
7483 | ||
230d00eb YM |
7484 | if (SHMEM2_HAS(bp, netproc_fw_ver)) |
7485 | SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM)); | |
7486 | ||
34f80b04 EG |
7487 | return 0; |
7488 | } | |
a2fbb9ea | 7489 | |
619c5cb6 VZ |
7490 | /** |
7491 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
7492 | * | |
7493 | * @bp: driver handle | |
7494 | */ | |
7495 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
7496 | { | |
7497 | int rc = bnx2x_init_hw_common(bp); | |
7498 | ||
7499 | if (rc) | |
7500 | return rc; | |
7501 | ||
7502 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
7503 | if (!BP_NOMCP(bp)) | |
7504 | bnx2x__common_init_phy(bp); | |
7505 | ||
7506 | return 0; | |
7507 | } | |
7508 | ||
523224a3 | 7509 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
7510 | { |
7511 | int port = BP_PORT(bp); | |
619c5cb6 | 7512 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 7513 | u32 low, high; |
4293b9f5 | 7514 | u32 val, reg; |
a2fbb9ea | 7515 | |
51c1a580 | 7516 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
34f80b04 EG |
7517 | |
7518 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 7519 | |
619c5cb6 VZ |
7520 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
7521 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
7522 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 7523 | |
f2e0899f DK |
7524 | /* Timers bug workaround: disables the pf_master bit in pglue at |
7525 | * common phase, we need to enable it here before any dmae access are | |
7526 | * attempted. Therefore we manually added the enable-master to the | |
7527 | * port phase (it also happens in the function phase) | |
7528 | */ | |
619c5cb6 | 7529 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7530 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
7531 | ||
619c5cb6 VZ |
7532 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7533 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7534 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
7535 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7536 | ||
7537 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7538 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7539 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7540 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 7541 | |
523224a3 DK |
7542 | /* QM cid (connection) count */ |
7543 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 7544 | |
55c11941 MS |
7545 | if (CNIC_SUPPORT(bp)) { |
7546 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7547 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); | |
7548 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
7549 | } | |
cdaa7cb8 | 7550 | |
619c5cb6 | 7551 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f | 7552 | |
2b674047 DK |
7553 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
7554 | ||
f2e0899f | 7555 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { |
619c5cb6 VZ |
7556 | |
7557 | if (IS_MF(bp)) | |
7558 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
7559 | else if (bp->dev->mtu > 4096) { | |
7560 | if (bp->flags & ONE_PORT_FLAG) | |
7561 | low = 160; | |
7562 | else { | |
7563 | val = bp->dev->mtu; | |
7564 | /* (24*1024 + val*4)/256 */ | |
7565 | low = 96 + (val/64) + | |
7566 | ((val % 64) ? 1 : 0); | |
7567 | } | |
7568 | } else | |
7569 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
7570 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
7571 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
7572 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 7573 | } |
1c06328c | 7574 | |
619c5cb6 VZ |
7575 | if (CHIP_MODE_IS_4_PORT(bp)) |
7576 | REG_WR(bp, (BP_PORT(bp) ? | |
7577 | BRB1_REG_MAC_GUARANTIED_1 : | |
7578 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 7579 | |
619c5cb6 | 7580 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
a3348722 BW |
7581 | if (CHIP_IS_E3B0(bp)) { |
7582 | if (IS_MF_AFEX(bp)) { | |
7583 | /* configure headers for AFEX mode */ | |
7584 | REG_WR(bp, BP_PORT(bp) ? | |
7585 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7586 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); | |
7587 | REG_WR(bp, BP_PORT(bp) ? | |
7588 | PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : | |
7589 | PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); | |
7590 | REG_WR(bp, BP_PORT(bp) ? | |
7591 | PRS_REG_MUST_HAVE_HDRS_PORT_1 : | |
7592 | PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); | |
7593 | } else { | |
7594 | /* Ovlan exists only if we are in multi-function + | |
7595 | * switch-dependent mode, in switch-independent there | |
7596 | * is no ovlan headers | |
7597 | */ | |
7598 | REG_WR(bp, BP_PORT(bp) ? | |
7599 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7600 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
7601 | (bp->path_has_ovlan ? 7 : 6)); | |
7602 | } | |
7603 | } | |
356e2385 | 7604 | |
619c5cb6 VZ |
7605 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
7606 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7607 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7608 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 7609 | |
619c5cb6 VZ |
7610 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
7611 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7612 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7613 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 7614 | |
619c5cb6 VZ |
7615 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
7616 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 7617 | |
619c5cb6 VZ |
7618 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
7619 | ||
7620 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
7621 | /* configure PBF to work without PAUSE mtu 9000 */ |
7622 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 7623 | |
f2e0899f DK |
7624 | /* update threshold */ |
7625 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
7626 | /* update init credit */ | |
7627 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 7628 | |
f2e0899f DK |
7629 | /* probe changes */ |
7630 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
7631 | udelay(50); | |
7632 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
7633 | } | |
a2fbb9ea | 7634 | |
55c11941 MS |
7635 | if (CNIC_SUPPORT(bp)) |
7636 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7637 | ||
619c5cb6 VZ |
7638 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
7639 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
7640 | |
7641 | if (CHIP_IS_E1(bp)) { | |
7642 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7643 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7644 | } | |
619c5cb6 | 7645 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 7646 | |
619c5cb6 | 7647 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7648 | |
619c5cb6 | 7649 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 | 7650 | /* init aeu_mask_attn_func_0/1: |
16a5fd92 YM |
7651 | * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use |
7652 | * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF | |
34f80b04 | 7653 | * bits 4-7 are used for "per vn group attention" */ |
e4901dde VZ |
7654 | val = IS_MF(bp) ? 0xF7 : 0x7; |
7655 | /* Enable DCBX attention for all but E1 */ | |
7656 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
7657 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 7658 | |
4293b9f5 DK |
7659 | /* SCPAD_PARITY should NOT trigger close the gates */ |
7660 | reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0; | |
7661 | REG_WR(bp, reg, | |
7662 | REG_RD(bp, reg) & | |
7663 | ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); | |
7664 | ||
7665 | reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0; | |
7666 | REG_WR(bp, reg, | |
7667 | REG_RD(bp, reg) & | |
7668 | ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); | |
7669 | ||
619c5cb6 VZ |
7670 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
7671 | ||
7672 | if (!CHIP_IS_E1x(bp)) { | |
7673 | /* Bit-map indicating which L2 hdrs may appear after the | |
7674 | * basic Ethernet header | |
7675 | */ | |
a3348722 BW |
7676 | if (IS_MF_AFEX(bp)) |
7677 | REG_WR(bp, BP_PORT(bp) ? | |
7678 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7679 | NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); | |
7680 | else | |
7681 | REG_WR(bp, BP_PORT(bp) ? | |
7682 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7683 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
7684 | IS_MF_SD(bp) ? 7 : 6); | |
619c5cb6 VZ |
7685 | |
7686 | if (CHIP_IS_E3(bp)) | |
7687 | REG_WR(bp, BP_PORT(bp) ? | |
7688 | NIG_REG_LLH1_MF_MODE : | |
7689 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
7690 | } | |
7691 | if (!CHIP_IS_E3(bp)) | |
7692 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 7693 | |
f2e0899f | 7694 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 7695 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 7696 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 7697 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 7698 | |
619c5cb6 | 7699 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7700 | val = 0; |
7701 | switch (bp->mf_mode) { | |
7702 | case MULTI_FUNCTION_SD: | |
7703 | val = 1; | |
7704 | break; | |
7705 | case MULTI_FUNCTION_SI: | |
a3348722 | 7706 | case MULTI_FUNCTION_AFEX: |
f2e0899f DK |
7707 | val = 2; |
7708 | break; | |
7709 | } | |
7710 | ||
7711 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
7712 | NIG_REG_LLH0_CLS_TYPE), val); | |
7713 | } | |
1c06328c EG |
7714 | { |
7715 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
7716 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
7717 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
7718 | } | |
34f80b04 EG |
7719 | } |
7720 | ||
619c5cb6 VZ |
7721 | /* If SPIO5 is set to generate interrupts, enable it for this port */ |
7722 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 7723 | if (val & MISC_SPIO_SPIO5) { |
4d295db0 EG |
7724 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
7725 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
7726 | val = REG_RD(bp, reg_addr); | |
f1410647 | 7727 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 7728 | REG_WR(bp, reg_addr, val); |
f1410647 | 7729 | } |
a2fbb9ea | 7730 | |
34f80b04 EG |
7731 | return 0; |
7732 | } | |
7733 | ||
34f80b04 EG |
7734 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
7735 | { | |
7736 | int reg; | |
32d68de1 | 7737 | u32 wb_write[2]; |
34f80b04 | 7738 | |
f2e0899f | 7739 | if (CHIP_IS_E1(bp)) |
34f80b04 | 7740 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
7741 | else |
7742 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 | 7743 | |
32d68de1 YM |
7744 | wb_write[0] = ONCHIP_ADDR1(addr); |
7745 | wb_write[1] = ONCHIP_ADDR2(addr); | |
7746 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
34f80b04 EG |
7747 | } |
7748 | ||
b56e9670 | 7749 | void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) |
1191cb83 ED |
7750 | { |
7751 | u32 data, ctl, cnt = 100; | |
7752 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
7753 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
7754 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
7755 | u32 sb_bit = 1 << (idu_sb_id%32); | |
b56e9670 | 7756 | u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; |
1191cb83 ED |
7757 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; |
7758 | ||
7759 | /* Not supported in BC mode */ | |
7760 | if (CHIP_INT_MODE_IS_BC(bp)) | |
7761 | return; | |
7762 | ||
7763 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
7764 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
7765 | IGU_REGULAR_CLEANUP_SET | | |
7766 | IGU_REGULAR_BCLEANUP; | |
7767 | ||
7768 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
7769 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
7770 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
7771 | ||
7772 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7773 | data, igu_addr_data); | |
7774 | REG_WR(bp, igu_addr_data, data); | |
7775 | mmiowb(); | |
7776 | barrier(); | |
7777 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7778 | ctl, igu_addr_ctl); | |
7779 | REG_WR(bp, igu_addr_ctl, ctl); | |
7780 | mmiowb(); | |
7781 | barrier(); | |
7782 | ||
7783 | /* wait for clean up to finish */ | |
7784 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
7785 | msleep(20); | |
7786 | ||
1191cb83 ED |
7787 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { |
7788 | DP(NETIF_MSG_HW, | |
7789 | "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
7790 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
7791 | } | |
7792 | } | |
7793 | ||
7794 | static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) | |
f2e0899f | 7795 | { |
619c5cb6 | 7796 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
7797 | } |
7798 | ||
1191cb83 | 7799 | static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) |
f2e0899f DK |
7800 | { |
7801 | u32 i, base = FUNC_ILT_BASE(func); | |
7802 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
7803 | bnx2x_ilt_wr(bp, i, 0); | |
7804 | } | |
7805 | ||
910cc727 | 7806 | static void bnx2x_init_searcher(struct bnx2x *bp) |
55c11941 MS |
7807 | { |
7808 | int port = BP_PORT(bp); | |
7809 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
7810 | /* T1 hash bits value determines the T1 number of entries */ | |
7811 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
7812 | } | |
7813 | ||
7814 | static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) | |
7815 | { | |
7816 | int rc; | |
7817 | struct bnx2x_func_state_params func_params = {NULL}; | |
7818 | struct bnx2x_func_switch_update_params *switch_update_params = | |
7819 | &func_params.params.switch_update; | |
7820 | ||
7821 | /* Prepare parameters for function state transitions */ | |
7822 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7823 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
7824 | ||
7825 | func_params.f_obj = &bp->func_obj; | |
7826 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
7827 | ||
7828 | /* Function parameters */ | |
e42780b6 DK |
7829 | __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, |
7830 | &switch_update_params->changes); | |
7831 | if (suspend) | |
7832 | __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND, | |
7833 | &switch_update_params->changes); | |
55c11941 MS |
7834 | |
7835 | rc = bnx2x_func_state_change(bp, &func_params); | |
7836 | ||
7837 | return rc; | |
7838 | } | |
7839 | ||
910cc727 | 7840 | static int bnx2x_reset_nic_mode(struct bnx2x *bp) |
55c11941 MS |
7841 | { |
7842 | int rc, i, port = BP_PORT(bp); | |
7843 | int vlan_en = 0, mac_en[NUM_MACS]; | |
7844 | ||
55c11941 MS |
7845 | /* Close input from network */ |
7846 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7847 | bnx2x_set_rx_filter(&bp->link_params, 0); | |
7848 | } else { | |
7849 | vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7850 | NIG_REG_LLH0_FUNC_EN); | |
7851 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7852 | NIG_REG_LLH0_FUNC_EN, 0); | |
7853 | for (i = 0; i < NUM_MACS; i++) { | |
7854 | mac_en[i] = REG_RD(bp, port ? | |
7855 | (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7856 | 4 * i) : | |
7857 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + | |
7858 | 4 * i)); | |
7859 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7860 | 4 * i) : | |
7861 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); | |
7862 | } | |
7863 | } | |
7864 | ||
7865 | /* Close BMC to host */ | |
7866 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7867 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); | |
7868 | ||
7869 | /* Suspend Tx switching to the PF. Completion of this ramrod | |
7870 | * further guarantees that all the packets of that PF / child | |
7871 | * VFs in BRB were processed by the Parser, so it is safe to | |
7872 | * change the NIC_MODE register. | |
7873 | */ | |
7874 | rc = bnx2x_func_switch_update(bp, 1); | |
7875 | if (rc) { | |
7876 | BNX2X_ERR("Can't suspend tx-switching!\n"); | |
7877 | return rc; | |
7878 | } | |
7879 | ||
7880 | /* Change NIC_MODE register */ | |
7881 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7882 | ||
7883 | /* Open input from network */ | |
7884 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7885 | bnx2x_set_rx_filter(&bp->link_params, 1); | |
7886 | } else { | |
7887 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7888 | NIG_REG_LLH0_FUNC_EN, vlan_en); | |
7889 | for (i = 0; i < NUM_MACS; i++) { | |
7890 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7891 | 4 * i) : | |
7892 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), | |
7893 | mac_en[i]); | |
7894 | } | |
7895 | } | |
7896 | ||
7897 | /* Enable BMC to host */ | |
7898 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7899 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); | |
7900 | ||
7901 | /* Resume Tx switching to the PF */ | |
7902 | rc = bnx2x_func_switch_update(bp, 0); | |
7903 | if (rc) { | |
7904 | BNX2X_ERR("Can't resume tx-switching!\n"); | |
7905 | return rc; | |
7906 | } | |
7907 | ||
7908 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7909 | return 0; | |
7910 | } | |
7911 | ||
7912 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp) | |
7913 | { | |
7914 | int rc; | |
7915 | ||
7916 | bnx2x_ilt_init_op_cnic(bp, INITOP_SET); | |
7917 | ||
7918 | if (CONFIGURE_NIC_MODE(bp)) { | |
16a5fd92 | 7919 | /* Configure searcher as part of function hw init */ |
55c11941 MS |
7920 | bnx2x_init_searcher(bp); |
7921 | ||
7922 | /* Reset NIC mode */ | |
7923 | rc = bnx2x_reset_nic_mode(bp); | |
7924 | if (rc) | |
7925 | BNX2X_ERR("Can't change NIC mode!\n"); | |
7926 | return rc; | |
7927 | } | |
7928 | ||
7929 | return 0; | |
7930 | } | |
7931 | ||
da254fbc YM |
7932 | /* previous driver DMAE transaction may have occurred when pre-boot stage ended |
7933 | * and boot began, or when kdump kernel was loaded. Either case would invalidate | |
7934 | * the addresses of the transaction, resulting in was-error bit set in the pci | |
7935 | * causing all hw-to-host pcie transactions to timeout. If this happened we want | |
7936 | * to clear the interrupt which detected this from the pglueb and the was done | |
7937 | * bit | |
7938 | */ | |
7939 | static void bnx2x_clean_pglue_errors(struct bnx2x *bp) | |
7940 | { | |
7941 | if (!CHIP_IS_E1x(bp)) | |
7942 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, | |
7943 | 1 << BP_ABS_FUNC(bp)); | |
7944 | } | |
7945 | ||
523224a3 | 7946 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
7947 | { |
7948 | int port = BP_PORT(bp); | |
7949 | int func = BP_FUNC(bp); | |
619c5cb6 | 7950 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
7951 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
7952 | u16 cdu_ilt_start; | |
8badd27a | 7953 | u32 addr, val; |
f4a66897 | 7954 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
89db4ad8 | 7955 | int i, main_mem_width, rc; |
34f80b04 | 7956 | |
51c1a580 | 7957 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
34f80b04 | 7958 | |
619c5cb6 | 7959 | /* FLR cleanup - hmmm */ |
89db4ad8 AE |
7960 | if (!CHIP_IS_E1x(bp)) { |
7961 | rc = bnx2x_pf_flr_clnup(bp); | |
04c46736 YM |
7962 | if (rc) { |
7963 | bnx2x_fw_dump(bp); | |
89db4ad8 | 7964 | return rc; |
04c46736 | 7965 | } |
89db4ad8 | 7966 | } |
619c5cb6 | 7967 | |
8badd27a | 7968 | /* set MSI reconfigure capability */ |
f2e0899f DK |
7969 | if (bp->common.int_block == INT_BLOCK_HC) { |
7970 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
7971 | val = REG_RD(bp, addr); | |
7972 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
7973 | REG_WR(bp, addr, val); | |
7974 | } | |
8badd27a | 7975 | |
619c5cb6 VZ |
7976 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
7977 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
7978 | ||
523224a3 DK |
7979 | ilt = BP_ILT(bp); |
7980 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 7981 | |
290ca2bb AE |
7982 | if (IS_SRIOV(bp)) |
7983 | cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; | |
7984 | cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); | |
7985 | ||
7986 | /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes | |
7987 | * those of the VFs, so start line should be reset | |
7988 | */ | |
7989 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
523224a3 | 7990 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
a052997e | 7991 | ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; |
523224a3 | 7992 | ilt->lines[cdu_ilt_start + i].page_mapping = |
a052997e MS |
7993 | bp->context[i].cxt_mapping; |
7994 | ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; | |
37b091ba | 7995 | } |
290ca2bb | 7996 | |
523224a3 | 7997 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 7998 | |
55c11941 MS |
7999 | if (!CONFIGURE_NIC_MODE(bp)) { |
8000 | bnx2x_init_searcher(bp); | |
8001 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
8002 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
8003 | } else { | |
8004 | /* Set NIC mode */ | |
8005 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6bf07b8e | 8006 | DP(NETIF_MSG_IFUP, "NIC MODE configured\n"); |
55c11941 | 8007 | } |
37b091ba | 8008 | |
619c5cb6 | 8009 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8010 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
8011 | ||
8012 | /* Turn on a single ISR mode in IGU if driver is going to use | |
8013 | * INT#x or MSI | |
8014 | */ | |
8015 | if (!(bp->flags & USING_MSIX_FLAG)) | |
8016 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
8017 | /* | |
8018 | * Timers workaround bug: function init part. | |
8019 | * Need to wait 20msec after initializing ILT, | |
8020 | * needed to make sure there are no requests in | |
8021 | * one of the PXP internal queues with "old" ILT addresses | |
8022 | */ | |
8023 | msleep(20); | |
8024 | /* | |
8025 | * Master enable - Due to WB DMAE writes performed before this | |
8026 | * register is re-initialized as part of the regular function | |
8027 | * init | |
8028 | */ | |
8029 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
8030 | /* Enable the function in IGU */ | |
8031 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
8032 | } | |
8033 | ||
523224a3 | 8034 | bp->dmae_ready = 1; |
34f80b04 | 8035 | |
619c5cb6 | 8036 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 8037 | |
da254fbc | 8038 | bnx2x_clean_pglue_errors(bp); |
f2e0899f | 8039 | |
619c5cb6 VZ |
8040 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
8041 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
8042 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
8043 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
8044 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
8045 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
8046 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
8047 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
8048 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
8049 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
8050 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
8051 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
8052 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
8053 | ||
8054 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
8055 | REG_WR(bp, QM_REG_PF_EN, 1); |
8056 | ||
619c5cb6 VZ |
8057 | if (!CHIP_IS_E1x(bp)) { |
8058 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
8059 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
8060 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
8061 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
8062 | } | |
8063 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
8064 | ||
8065 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
8066 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
c19d65c9 | 8067 | REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ |
b56e9670 AE |
8068 | |
8069 | bnx2x_iov_init_dq(bp); | |
8070 | ||
619c5cb6 VZ |
8071 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
8072 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
8073 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
8074 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
8075 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
8076 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
8077 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
8078 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
8079 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
8080 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
8081 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
8082 | ||
619c5cb6 | 8083 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 8084 | |
619c5cb6 | 8085 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 8086 | |
619c5cb6 | 8087 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
8088 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
8089 | ||
fb3bff17 | 8090 | if (IS_MF(bp)) { |
7609647e YM |
8091 | if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) { |
8092 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); | |
8093 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, | |
8094 | bp->mf_ov); | |
8095 | } | |
34f80b04 EG |
8096 | } |
8097 | ||
619c5cb6 | 8098 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 8099 | |
34f80b04 | 8100 | /* HC init per function */ |
f2e0899f DK |
8101 | if (bp->common.int_block == INT_BLOCK_HC) { |
8102 | if (CHIP_IS_E1H(bp)) { | |
8103 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
8104 | ||
8105 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
8106 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
8107 | } | |
619c5cb6 | 8108 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
8109 | |
8110 | } else { | |
8111 | int num_segs, sb_idx, prod_offset; | |
8112 | ||
34f80b04 EG |
8113 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
8114 | ||
619c5cb6 | 8115 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8116 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
8117 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
8118 | } | |
8119 | ||
619c5cb6 | 8120 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 8121 | |
619c5cb6 | 8122 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8123 | int dsb_idx = 0; |
8124 | /** | |
8125 | * Producer memory: | |
8126 | * E2 mode: address 0-135 match to the mapping memory; | |
8127 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
8128 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
8129 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
8130 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
8131 | * 144-147 reserved. | |
8132 | * | |
8133 | * E1.5 mode - In backward compatible mode; | |
8134 | * for non default SB; each even line in the memory | |
8135 | * holds the U producer and each odd line hold | |
8136 | * the C producer. The first 128 producers are for | |
8137 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
8138 | * producers are for the DSB for each PF. | |
8139 | * Each PF has five segments: (the order inside each | |
8140 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
8141 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
8142 | * 144-147 attn prods; | |
8143 | */ | |
8144 | /* non-default-status-blocks */ | |
8145 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
8146 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
8147 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
8148 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
8149 | num_segs; | |
8150 | ||
8151 | for (i = 0; i < num_segs; i++) { | |
8152 | addr = IGU_REG_PROD_CONS_MEMORY + | |
8153 | (prod_offset + i) * 4; | |
8154 | REG_WR(bp, addr, 0); | |
8155 | } | |
8156 | /* send consumer update with value 0 */ | |
8157 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
8158 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
8159 | bnx2x_igu_clear_sb(bp, | |
8160 | bp->igu_base_sb + sb_idx); | |
8161 | } | |
8162 | ||
8163 | /* default-status-blocks */ | |
8164 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
8165 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
8166 | ||
8167 | if (CHIP_MODE_IS_4_PORT(bp)) | |
8168 | dsb_idx = BP_FUNC(bp); | |
8169 | else | |
3395a033 | 8170 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
8171 | |
8172 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
8173 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
8174 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
8175 | ||
3395a033 DK |
8176 | /* |
8177 | * igu prods come in chunks of E1HVN_MAX (4) - | |
8178 | * does not matters what is the current chip mode | |
8179 | */ | |
f2e0899f DK |
8180 | for (i = 0; i < (num_segs * E1HVN_MAX); |
8181 | i += E1HVN_MAX) { | |
8182 | addr = IGU_REG_PROD_CONS_MEMORY + | |
8183 | (prod_offset + i)*4; | |
8184 | REG_WR(bp, addr, 0); | |
8185 | } | |
8186 | /* send consumer update with 0 */ | |
8187 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
8188 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8189 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
8190 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8191 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
8192 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8193 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
8194 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8195 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
8196 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8197 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
8198 | } else { | |
8199 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8200 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
8201 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8202 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
8203 | } | |
8204 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
8205 | ||
16a5fd92 | 8206 | /* !!! These should become driver const once |
f2e0899f DK |
8207 | rf-tool supports split-68 const */ |
8208 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
8209 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
8210 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
8211 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
8212 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
8213 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
8214 | } | |
34f80b04 | 8215 | } |
34f80b04 | 8216 | |
c14423fe | 8217 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
8218 | REG_WR(bp, 0x2114, 0xffffffff); |
8219 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 8220 | |
f4a66897 VZ |
8221 | if (CHIP_IS_E1x(bp)) { |
8222 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
8223 | main_mem_base = HC_REG_MAIN_MEMORY + | |
8224 | BP_PORT(bp) * (main_mem_size * 4); | |
8225 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
8226 | main_mem_width = 8; | |
8227 | ||
8228 | val = REG_RD(bp, main_mem_prty_clr); | |
8229 | if (val) | |
51c1a580 MS |
8230 | DP(NETIF_MSG_HW, |
8231 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", | |
8232 | val); | |
f4a66897 VZ |
8233 | |
8234 | /* Clear "false" parity errors in MSI-X table */ | |
8235 | for (i = main_mem_base; | |
8236 | i < main_mem_base + main_mem_size * 4; | |
8237 | i += main_mem_width) { | |
8238 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
8239 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
8240 | i, main_mem_width / 4); | |
8241 | } | |
8242 | /* Clear HC parity attention */ | |
8243 | REG_RD(bp, main_mem_prty_clr); | |
8244 | } | |
8245 | ||
619c5cb6 VZ |
8246 | #ifdef BNX2X_STOP_ON_ERROR |
8247 | /* Enable STORMs SP logging */ | |
8248 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
8249 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8250 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
8251 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8252 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
8253 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8254 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
8255 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8256 | #endif | |
8257 | ||
b7737c9b | 8258 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 8259 | |
34f80b04 EG |
8260 | return 0; |
8261 | } | |
8262 | ||
55c11941 MS |
8263 | void bnx2x_free_mem_cnic(struct bnx2x *bp) |
8264 | { | |
8265 | bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); | |
8266 | ||
8267 | if (!CHIP_IS_E1x(bp)) | |
8268 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, | |
8269 | sizeof(struct host_hc_status_block_e2)); | |
8270 | else | |
8271 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
8272 | sizeof(struct host_hc_status_block_e1x)); | |
8273 | ||
8274 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); | |
8275 | } | |
8276 | ||
9f6c9258 | 8277 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 8278 | { |
a052997e MS |
8279 | int i; |
8280 | ||
619c5cb6 VZ |
8281 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
8282 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
8283 | ||
b4cddbd6 AE |
8284 | if (IS_VF(bp)) |
8285 | return; | |
8286 | ||
8287 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
8288 | sizeof(struct host_sp_status_block)); | |
8289 | ||
a2fbb9ea | 8290 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 8291 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 8292 | |
a052997e MS |
8293 | for (i = 0; i < L2_ILT_LINES(bp); i++) |
8294 | BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, | |
8295 | bp->context[i].size); | |
523224a3 DK |
8296 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); |
8297 | ||
8298 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 8299 | |
7a9b2557 | 8300 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 8301 | |
523224a3 DK |
8302 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
8303 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
580d9d08 | 8304 | |
05952246 YM |
8305 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
8306 | ||
580d9d08 | 8307 | bnx2x_iov_free_mem(bp); |
619c5cb6 VZ |
8308 | } |
8309 | ||
55c11941 | 8310 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp) |
a2fbb9ea | 8311 | { |
cd2b0389 | 8312 | if (!CHIP_IS_E1x(bp)) { |
619c5cb6 | 8313 | /* size = the status block + ramrod buffers */ |
cd2b0389 JP |
8314 | bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, |
8315 | sizeof(struct host_hc_status_block_e2)); | |
8316 | if (!bp->cnic_sb.e2_sb) | |
8317 | goto alloc_mem_err; | |
8318 | } else { | |
8319 | bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, | |
8320 | sizeof(struct host_hc_status_block_e1x)); | |
8321 | if (!bp->cnic_sb.e1x_sb) | |
8322 | goto alloc_mem_err; | |
8323 | } | |
8badd27a | 8324 | |
cd2b0389 | 8325 | if (CONFIGURE_NIC_MODE(bp) && !bp->t2) { |
16a5fd92 | 8326 | /* allocate searcher T2 table, as it wasn't allocated before */ |
cd2b0389 JP |
8327 | bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); |
8328 | if (!bp->t2) | |
8329 | goto alloc_mem_err; | |
8330 | } | |
55c11941 MS |
8331 | |
8332 | /* write address to which L5 should insert its values */ | |
8333 | bp->cnic_eth_dev.addr_drv_info_to_mcp = | |
8334 | &bp->slowpath->drv_info_to_mcp; | |
8335 | ||
8336 | if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) | |
8337 | goto alloc_mem_err; | |
8338 | ||
8339 | return 0; | |
8340 | ||
8341 | alloc_mem_err: | |
8342 | bnx2x_free_mem_cnic(bp); | |
8343 | BNX2X_ERR("Can't allocate memory\n"); | |
8344 | return -ENOMEM; | |
8345 | } | |
8346 | ||
8347 | int bnx2x_alloc_mem(struct bnx2x *bp) | |
8348 | { | |
8349 | int i, allocated, context_size; | |
a2fbb9ea | 8350 | |
cd2b0389 | 8351 | if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) { |
55c11941 | 8352 | /* allocate searcher T2 table */ |
cd2b0389 JP |
8353 | bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); |
8354 | if (!bp->t2) | |
8355 | goto alloc_mem_err; | |
8356 | } | |
8badd27a | 8357 | |
cd2b0389 JP |
8358 | bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping, |
8359 | sizeof(struct host_sp_status_block)); | |
8360 | if (!bp->def_status_blk) | |
8361 | goto alloc_mem_err; | |
a2fbb9ea | 8362 | |
cd2b0389 JP |
8363 | bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping, |
8364 | sizeof(struct bnx2x_slowpath)); | |
8365 | if (!bp->slowpath) | |
8366 | goto alloc_mem_err; | |
a2fbb9ea | 8367 | |
a052997e MS |
8368 | /* Allocate memory for CDU context: |
8369 | * This memory is allocated separately and not in the generic ILT | |
8370 | * functions because CDU differs in few aspects: | |
8371 | * 1. There are multiple entities allocating memory for context - | |
8372 | * 'regular' driver, CNIC and SRIOV driver. Each separately controls | |
8373 | * its own ILT lines. | |
8374 | * 2. Since CDU page-size is not a single 4KB page (which is the case | |
8375 | * for the other ILT clients), to be efficient we want to support | |
8376 | * allocation of sub-page-size in the last entry. | |
8377 | * 3. Context pointers are used by the driver to pass to FW / update | |
8378 | * the context (for the other ILT clients the pointers are used just to | |
8379 | * free the memory during unload). | |
8380 | */ | |
8381 | context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); | |
65abd74d | 8382 | |
a052997e MS |
8383 | for (i = 0, allocated = 0; allocated < context_size; i++) { |
8384 | bp->context[i].size = min(CDU_ILT_PAGE_SZ, | |
8385 | (context_size - allocated)); | |
cd2b0389 JP |
8386 | bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping, |
8387 | bp->context[i].size); | |
8388 | if (!bp->context[i].vcxt) | |
8389 | goto alloc_mem_err; | |
a052997e MS |
8390 | allocated += bp->context[i].size; |
8391 | } | |
cd2b0389 JP |
8392 | bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line), |
8393 | GFP_KERNEL); | |
8394 | if (!bp->ilt->lines) | |
8395 | goto alloc_mem_err; | |
65abd74d | 8396 | |
523224a3 DK |
8397 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
8398 | goto alloc_mem_err; | |
65abd74d | 8399 | |
67c431a5 AE |
8400 | if (bnx2x_iov_alloc_mem(bp)) |
8401 | goto alloc_mem_err; | |
8402 | ||
9f6c9258 | 8403 | /* Slow path ring */ |
cd2b0389 JP |
8404 | bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE); |
8405 | if (!bp->spq) | |
8406 | goto alloc_mem_err; | |
65abd74d | 8407 | |
523224a3 | 8408 | /* EQ */ |
cd2b0389 JP |
8409 | bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping, |
8410 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
8411 | if (!bp->eq_ring) | |
8412 | goto alloc_mem_err; | |
ab532cf3 | 8413 | |
9f6c9258 | 8414 | return 0; |
e1510706 | 8415 | |
9f6c9258 DK |
8416 | alloc_mem_err: |
8417 | bnx2x_free_mem(bp); | |
51c1a580 | 8418 | BNX2X_ERR("Can't allocate memory\n"); |
9f6c9258 | 8419 | return -ENOMEM; |
65abd74d YG |
8420 | } |
8421 | ||
a2fbb9ea ET |
8422 | /* |
8423 | * Init service functions | |
8424 | */ | |
a2fbb9ea | 8425 | |
619c5cb6 VZ |
8426 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
8427 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
8428 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 8429 | { |
619c5cb6 VZ |
8430 | int rc; |
8431 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 8432 | |
619c5cb6 | 8433 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 8434 | |
619c5cb6 VZ |
8435 | /* Fill general parameters */ |
8436 | ramrod_param.vlan_mac_obj = obj; | |
8437 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 8438 | |
619c5cb6 VZ |
8439 | /* Fill a user request section if needed */ |
8440 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
8441 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 8442 | |
619c5cb6 | 8443 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 8444 | |
619c5cb6 VZ |
8445 | /* Set the command: ADD or DEL */ |
8446 | if (set) | |
8447 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
8448 | else | |
8449 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
8450 | } |
8451 | ||
619c5cb6 | 8452 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7b5342d9 YM |
8453 | |
8454 | if (rc == -EEXIST) { | |
8455 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); | |
8456 | /* do not treat adding same MAC as error */ | |
8457 | rc = 0; | |
8458 | } else if (rc < 0) | |
619c5cb6 | 8459 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); |
7b5342d9 | 8460 | |
619c5cb6 | 8461 | return rc; |
a2fbb9ea ET |
8462 | } |
8463 | ||
05cc5a39 YM |
8464 | int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan, |
8465 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
8466 | unsigned long *ramrod_flags) | |
8467 | { | |
8468 | int rc; | |
8469 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
8470 | ||
8471 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
8472 | ||
8473 | /* Fill general parameters */ | |
8474 | ramrod_param.vlan_mac_obj = obj; | |
8475 | ramrod_param.ramrod_flags = *ramrod_flags; | |
8476 | ||
8477 | /* Fill a user request section if needed */ | |
8478 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
8479 | ramrod_param.user_req.u.vlan.vlan = vlan; | |
66c6934a | 8480 | __set_bit(BNX2X_VLAN, &ramrod_param.user_req.vlan_mac_flags); |
05cc5a39 YM |
8481 | /* Set the command: ADD or DEL */ |
8482 | if (set) | |
8483 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
8484 | else | |
8485 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
8486 | } | |
8487 | ||
8488 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); | |
8489 | ||
8490 | if (rc == -EEXIST) { | |
8491 | /* Do not treat adding same vlan as error. */ | |
8492 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); | |
8493 | rc = 0; | |
8494 | } else if (rc < 0) { | |
8495 | BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del")); | |
8496 | } | |
8497 | ||
8498 | return rc; | |
8499 | } | |
8500 | ||
c99ec777 MC |
8501 | void bnx2x_clear_vlan_info(struct bnx2x *bp) |
8502 | { | |
8503 | struct bnx2x_vlan_entry *vlan; | |
8504 | ||
8505 | /* Mark that hw forgot all entries */ | |
8506 | list_for_each_entry(vlan, &bp->vlan_reg, link) | |
8507 | vlan->hw = false; | |
8508 | ||
8509 | bp->vlan_cnt = 0; | |
8510 | } | |
8511 | ||
66c6934a SRK |
8512 | static int bnx2x_del_all_vlans(struct bnx2x *bp) |
8513 | { | |
8514 | struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj; | |
8515 | unsigned long ramrod_flags = 0, vlan_flags = 0; | |
66c6934a SRK |
8516 | int rc; |
8517 | ||
8518 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
8519 | __set_bit(BNX2X_VLAN, &vlan_flags); | |
8520 | rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags); | |
8521 | if (rc) | |
8522 | return rc; | |
8523 | ||
c99ec777 | 8524 | bnx2x_clear_vlan_info(bp); |
66c6934a SRK |
8525 | |
8526 | return 0; | |
8527 | } | |
8528 | ||
619c5cb6 VZ |
8529 | int bnx2x_del_all_macs(struct bnx2x *bp, |
8530 | struct bnx2x_vlan_mac_obj *mac_obj, | |
8531 | int mac_type, bool wait_for_comp) | |
e665bfda | 8532 | { |
619c5cb6 VZ |
8533 | int rc; |
8534 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 8535 | |
619c5cb6 VZ |
8536 | /* Wait for completion of requested */ |
8537 | if (wait_for_comp) | |
8538 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 8539 | |
619c5cb6 VZ |
8540 | /* Set the mac type of addresses we want to clear */ |
8541 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 8542 | |
619c5cb6 VZ |
8543 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
8544 | if (rc < 0) | |
8545 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 8546 | |
619c5cb6 | 8547 | return rc; |
0793f83f DK |
8548 | } |
8549 | ||
619c5cb6 | 8550 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 8551 | { |
f8f4f61a DK |
8552 | if (IS_PF(bp)) { |
8553 | unsigned long ramrod_flags = 0; | |
0793f83f | 8554 | |
f8f4f61a DK |
8555 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
8556 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
8557 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, | |
8558 | &bp->sp_objs->mac_obj, set, | |
8559 | BNX2X_ETH_MAC, &ramrod_flags); | |
8560 | } else { /* vf */ | |
8561 | return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, | |
bb9e9c1d | 8562 | bp->fp->index, set); |
f8f4f61a | 8563 | } |
e665bfda | 8564 | } |
6e30dd4e | 8565 | |
619c5cb6 | 8566 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 8567 | { |
60cad4e6 AE |
8568 | if (IS_PF(bp)) |
8569 | return bnx2x_setup_queue(bp, &bp->fp[0], true); | |
8570 | else /* VF */ | |
8571 | return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); | |
993ac7b5 | 8572 | } |
a2fbb9ea | 8573 | |
d6214d7a | 8574 | /** |
e8920674 | 8575 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 8576 | * |
e8920674 | 8577 | * @bp: driver handle |
d6214d7a | 8578 | * |
e8920674 | 8579 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 8580 | */ |
1ab4434c | 8581 | int bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 8582 | { |
1ab4434c AE |
8583 | int rc = 0; |
8584 | ||
60cad4e6 AE |
8585 | if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) { |
8586 | BNX2X_ERR("VF not loaded since interrupt mode not msix\n"); | |
1ab4434c | 8587 | return -EINVAL; |
60cad4e6 | 8588 | } |
1ab4434c | 8589 | |
9ee3d37b | 8590 | switch (int_mode) { |
1ab4434c AE |
8591 | case BNX2X_INT_MODE_MSIX: |
8592 | /* attempt to enable msix */ | |
8593 | rc = bnx2x_enable_msix(bp); | |
8594 | ||
8595 | /* msix attained */ | |
8596 | if (!rc) | |
8597 | return 0; | |
8598 | ||
8599 | /* vfs use only msix */ | |
8600 | if (rc && IS_VF(bp)) | |
8601 | return rc; | |
8602 | ||
8603 | /* failed to enable multiple MSI-X */ | |
8604 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", | |
8605 | bp->num_queues, | |
8606 | 1 + bp->num_cnic_queues); | |
8607 | ||
8608 | /* falling through... */ | |
8609 | case BNX2X_INT_MODE_MSI: | |
d6214d7a | 8610 | bnx2x_enable_msi(bp); |
1ab4434c | 8611 | |
d6214d7a | 8612 | /* falling through... */ |
1ab4434c | 8613 | case BNX2X_INT_MODE_INTX: |
55c11941 MS |
8614 | bp->num_ethernet_queues = 1; |
8615 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; | |
51c1a580 | 8616 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
ca00392c | 8617 | break; |
d6214d7a | 8618 | default: |
1ab4434c AE |
8619 | BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); |
8620 | return -EINVAL; | |
9f6c9258 | 8621 | } |
1ab4434c | 8622 | return 0; |
a2fbb9ea ET |
8623 | } |
8624 | ||
1ab4434c | 8625 | /* must be called prior to any HW initializations */ |
c2bff63f DK |
8626 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) |
8627 | { | |
290ca2bb AE |
8628 | if (IS_SRIOV(bp)) |
8629 | return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; | |
c2bff63f DK |
8630 | return L2_ILT_LINES(bp); |
8631 | } | |
8632 | ||
523224a3 DK |
8633 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
8634 | { | |
8635 | struct ilt_client_info *ilt_client; | |
8636 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
8637 | u16 line = 0; | |
8638 | ||
8639 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
8640 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
8641 | ||
8642 | /* CDU */ | |
8643 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
8644 | ilt_client->client_num = ILT_CLIENT_CDU; | |
8645 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
8646 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
8647 | ilt_client->start = line; | |
619c5cb6 | 8648 | line += bnx2x_cid_ilt_lines(bp); |
55c11941 MS |
8649 | |
8650 | if (CNIC_SUPPORT(bp)) | |
8651 | line += CNIC_ILT_LINES; | |
523224a3 DK |
8652 | ilt_client->end = line - 1; |
8653 | ||
51c1a580 | 8654 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
523224a3 DK |
8655 | ilt_client->start, |
8656 | ilt_client->end, | |
8657 | ilt_client->page_size, | |
8658 | ilt_client->flags, | |
8659 | ilog2(ilt_client->page_size >> 12)); | |
8660 | ||
8661 | /* QM */ | |
8662 | if (QM_INIT(bp->qm_cid_count)) { | |
8663 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
8664 | ilt_client->client_num = ILT_CLIENT_QM; | |
8665 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
8666 | ilt_client->flags = 0; | |
8667 | ilt_client->start = line; | |
8668 | ||
8669 | /* 4 bytes for each cid */ | |
8670 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
8671 | QM_ILT_PAGE_SZ); | |
8672 | ||
8673 | ilt_client->end = line - 1; | |
8674 | ||
51c1a580 MS |
8675 | DP(NETIF_MSG_IFUP, |
8676 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
8677 | ilt_client->start, |
8678 | ilt_client->end, | |
8679 | ilt_client->page_size, | |
8680 | ilt_client->flags, | |
8681 | ilog2(ilt_client->page_size >> 12)); | |
523224a3 | 8682 | } |
523224a3 | 8683 | |
55c11941 MS |
8684 | if (CNIC_SUPPORT(bp)) { |
8685 | /* SRC */ | |
8686 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
8687 | ilt_client->client_num = ILT_CLIENT_SRC; | |
8688 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
8689 | ilt_client->flags = 0; | |
8690 | ilt_client->start = line; | |
8691 | line += SRC_ILT_LINES; | |
8692 | ilt_client->end = line - 1; | |
523224a3 | 8693 | |
55c11941 MS |
8694 | DP(NETIF_MSG_IFUP, |
8695 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8696 | ilt_client->start, | |
8697 | ilt_client->end, | |
8698 | ilt_client->page_size, | |
8699 | ilt_client->flags, | |
8700 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 8701 | |
55c11941 MS |
8702 | /* TM */ |
8703 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
8704 | ilt_client->client_num = ILT_CLIENT_TM; | |
8705 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
8706 | ilt_client->flags = 0; | |
8707 | ilt_client->start = line; | |
8708 | line += TM_ILT_LINES; | |
8709 | ilt_client->end = line - 1; | |
523224a3 | 8710 | |
55c11941 MS |
8711 | DP(NETIF_MSG_IFUP, |
8712 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8713 | ilt_client->start, | |
8714 | ilt_client->end, | |
8715 | ilt_client->page_size, | |
8716 | ilt_client->flags, | |
8717 | ilog2(ilt_client->page_size >> 12)); | |
8718 | } | |
9f6c9258 | 8719 | |
619c5cb6 | 8720 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 8721 | } |
f85582f8 | 8722 | |
619c5cb6 VZ |
8723 | /** |
8724 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
8725 | * | |
8726 | * @bp: driver handle | |
8727 | * @fp: pointer to fastpath | |
8728 | * @init_params: pointer to parameters structure | |
8729 | * | |
8730 | * parameters configured: | |
8731 | * - HC configuration | |
8732 | * - Queue's CDU context | |
8733 | */ | |
1191cb83 | 8734 | static void bnx2x_pf_q_prep_init(struct bnx2x *bp, |
619c5cb6 | 8735 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) |
a2fbb9ea | 8736 | { |
6383c0b3 | 8737 | u8 cos; |
a052997e MS |
8738 | int cxt_index, cxt_offset; |
8739 | ||
619c5cb6 VZ |
8740 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
8741 | if (!IS_FCOE_FP(fp)) { | |
8742 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
8743 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
8744 | ||
16a5fd92 | 8745 | /* If HC is supported, enable host coalescing in the transition |
619c5cb6 VZ |
8746 | * to INIT state. |
8747 | */ | |
8748 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
8749 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
8750 | ||
8751 | /* HC rate */ | |
8752 | init_params->rx.hc_rate = bp->rx_ticks ? | |
8753 | (1000000 / bp->rx_ticks) : 0; | |
8754 | init_params->tx.hc_rate = bp->tx_ticks ? | |
8755 | (1000000 / bp->tx_ticks) : 0; | |
8756 | ||
8757 | /* FW SB ID */ | |
8758 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
8759 | fp->fw_sb_id; | |
8760 | ||
8761 | /* | |
8762 | * CQ index among the SB indices: FCoE clients uses the default | |
8763 | * SB, therefore it's different. | |
8764 | */ | |
6383c0b3 AE |
8765 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
8766 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
8767 | } |
8768 | ||
6383c0b3 AE |
8769 | /* set maximum number of COSs supported by this queue */ |
8770 | init_params->max_cos = fp->max_cos; | |
8771 | ||
51c1a580 | 8772 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
8773 | fp->index, init_params->max_cos); |
8774 | ||
8775 | /* set the context pointers queue object */ | |
a052997e | 8776 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { |
65565884 MS |
8777 | cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; |
8778 | cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * | |
a052997e | 8779 | ILT_PAGE_CIDS); |
6383c0b3 | 8780 | init_params->cxts[cos] = |
a052997e MS |
8781 | &bp->context[cxt_index].vcxt[cxt_offset].eth; |
8782 | } | |
619c5cb6 VZ |
8783 | } |
8784 | ||
910cc727 | 8785 | static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
6383c0b3 AE |
8786 | struct bnx2x_queue_state_params *q_params, |
8787 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
8788 | int tx_index, bool leading) | |
8789 | { | |
8790 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
8791 | ||
8792 | /* Set the command */ | |
8793 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
8794 | ||
8795 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
8796 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
8797 | ||
8798 | /* choose the index of the cid to send the slow path on */ | |
8799 | tx_only_params->cid_index = tx_index; | |
8800 | ||
8801 | /* Set general TX_ONLY_SETUP parameters */ | |
8802 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
8803 | ||
8804 | /* Set Tx TX_ONLY_SETUP parameters */ | |
8805 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
8806 | ||
51c1a580 MS |
8807 | DP(NETIF_MSG_IFUP, |
8808 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", | |
6383c0b3 AE |
8809 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
8810 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
8811 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
8812 | ||
8813 | /* send the ramrod */ | |
8814 | return bnx2x_queue_state_change(bp, q_params); | |
8815 | } | |
8816 | ||
619c5cb6 VZ |
8817 | /** |
8818 | * bnx2x_setup_queue - setup queue | |
8819 | * | |
8820 | * @bp: driver handle | |
8821 | * @fp: pointer to fastpath | |
8822 | * @leading: is leading | |
8823 | * | |
8824 | * This function performs 2 steps in a Queue state machine | |
8825 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
8826 | */ | |
8827 | ||
8828 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
8829 | bool leading) | |
8830 | { | |
3b603066 | 8831 | struct bnx2x_queue_state_params q_params = {NULL}; |
619c5cb6 VZ |
8832 | struct bnx2x_queue_setup_params *setup_params = |
8833 | &q_params.params.setup; | |
6383c0b3 AE |
8834 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
8835 | &q_params.params.tx_only; | |
a2fbb9ea | 8836 | int rc; |
6383c0b3 AE |
8837 | u8 tx_index; |
8838 | ||
51c1a580 | 8839 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 8840 | |
ec6ba945 VZ |
8841 | /* reset IGU state skip FCoE L2 queue */ |
8842 | if (!IS_FCOE_FP(fp)) | |
8843 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 8844 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 8845 | |
15192a8c | 8846 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8847 | /* We want to wait for completion in this context */ |
8848 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8849 | |
619c5cb6 VZ |
8850 | /* Prepare the INIT parameters */ |
8851 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 8852 | |
619c5cb6 VZ |
8853 | /* Set the command */ |
8854 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
8855 | ||
8856 | /* Change the state to INIT */ | |
8857 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8858 | if (rc) { | |
6383c0b3 | 8859 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
8860 | return rc; |
8861 | } | |
ec6ba945 | 8862 | |
51c1a580 | 8863 | DP(NETIF_MSG_IFUP, "init complete\n"); |
6383c0b3 | 8864 | |
619c5cb6 VZ |
8865 | /* Now move the Queue to the SETUP state... */ |
8866 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 8867 | |
619c5cb6 VZ |
8868 | /* Set QUEUE flags */ |
8869 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 8870 | |
619c5cb6 | 8871 | /* Set general SETUP parameters */ |
6383c0b3 AE |
8872 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
8873 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 8874 | |
6383c0b3 | 8875 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
8876 | &setup_params->rxq_params); |
8877 | ||
6383c0b3 AE |
8878 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
8879 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
8880 | |
8881 | /* Set the command */ | |
8882 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
8883 | ||
55c11941 MS |
8884 | if (IS_FCOE_FP(fp)) |
8885 | bp->fcoe_init = true; | |
8886 | ||
619c5cb6 VZ |
8887 | /* Change the state to SETUP */ |
8888 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
8889 | if (rc) { |
8890 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
8891 | return rc; | |
8892 | } | |
8893 | ||
8894 | /* loop through the relevant tx-only indices */ | |
8895 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8896 | tx_index < fp->max_cos; | |
8897 | tx_index++) { | |
8898 | ||
8899 | /* prepare and send tx-only ramrod*/ | |
8900 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
8901 | tx_only_params, tx_index, leading); | |
8902 | if (rc) { | |
8903 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
8904 | fp->index, tx_index); | |
8905 | return rc; | |
8906 | } | |
8907 | } | |
523224a3 | 8908 | |
34f80b04 | 8909 | return rc; |
a2fbb9ea ET |
8910 | } |
8911 | ||
619c5cb6 | 8912 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 8913 | { |
619c5cb6 | 8914 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 8915 | struct bnx2x_fp_txdata *txdata; |
3b603066 | 8916 | struct bnx2x_queue_state_params q_params = {NULL}; |
6383c0b3 AE |
8917 | int rc, tx_index; |
8918 | ||
51c1a580 | 8919 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 8920 | |
15192a8c | 8921 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8922 | /* We want to wait for completion in this context */ |
8923 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8924 | |
6383c0b3 AE |
8925 | /* close tx-only connections */ |
8926 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8927 | tx_index < fp->max_cos; | |
8928 | tx_index++){ | |
8929 | ||
8930 | /* ascertain this is a normal queue*/ | |
65565884 | 8931 | txdata = fp->txdata_ptr[tx_index]; |
6383c0b3 | 8932 | |
51c1a580 | 8933 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
6383c0b3 AE |
8934 | txdata->txq_index); |
8935 | ||
8936 | /* send halt terminate on tx-only connection */ | |
8937 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
8938 | memset(&q_params.params.terminate, 0, | |
8939 | sizeof(q_params.params.terminate)); | |
8940 | q_params.params.terminate.cid_index = tx_index; | |
8941 | ||
8942 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8943 | if (rc) | |
8944 | return rc; | |
8945 | ||
8946 | /* send halt terminate on tx-only connection */ | |
8947 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
8948 | memset(&q_params.params.cfc_del, 0, | |
8949 | sizeof(q_params.params.cfc_del)); | |
8950 | q_params.params.cfc_del.cid_index = tx_index; | |
8951 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8952 | if (rc) | |
8953 | return rc; | |
8954 | } | |
8955 | /* Stop the primary connection: */ | |
8956 | /* ...halt the connection */ | |
619c5cb6 VZ |
8957 | q_params.cmd = BNX2X_Q_CMD_HALT; |
8958 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8959 | if (rc) | |
da5a662a | 8960 | return rc; |
a2fbb9ea | 8961 | |
6383c0b3 | 8962 | /* ...terminate the connection */ |
619c5cb6 | 8963 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
8964 | memset(&q_params.params.terminate, 0, |
8965 | sizeof(q_params.params.terminate)); | |
8966 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
8967 | rc = bnx2x_queue_state_change(bp, &q_params); |
8968 | if (rc) | |
523224a3 | 8969 | return rc; |
6383c0b3 | 8970 | /* ...delete cfc entry */ |
619c5cb6 | 8971 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
8972 | memset(&q_params.params.cfc_del, 0, |
8973 | sizeof(q_params.params.cfc_del)); | |
8974 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 8975 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
8976 | } |
8977 | ||
34f80b04 EG |
8978 | static void bnx2x_reset_func(struct bnx2x *bp) |
8979 | { | |
8980 | int port = BP_PORT(bp); | |
8981 | int func = BP_FUNC(bp); | |
f2e0899f | 8982 | int i; |
523224a3 DK |
8983 | |
8984 | /* Disable the function in the FW */ | |
8985 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
8986 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
8987 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
8988 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
8989 | ||
8990 | /* FP SBs */ | |
ec6ba945 | 8991 | for_each_eth_queue(bp, i) { |
523224a3 | 8992 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 8993 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8994 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
8995 | SB_DISABLED); | |
523224a3 DK |
8996 | } |
8997 | ||
55c11941 MS |
8998 | if (CNIC_LOADED(bp)) |
8999 | /* CNIC SB */ | |
9000 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
9001 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET | |
9002 | (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); | |
9003 | ||
523224a3 | 9004 | /* SP SB */ |
619c5cb6 | 9005 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
2de67439 YM |
9006 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
9007 | SB_DISABLED); | |
523224a3 DK |
9008 | |
9009 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
9010 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
9011 | 0); | |
34f80b04 EG |
9012 | |
9013 | /* Configure IGU */ | |
f2e0899f DK |
9014 | if (bp->common.int_block == INT_BLOCK_HC) { |
9015 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
9016 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
9017 | } else { | |
9018 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
9019 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
9020 | } | |
34f80b04 | 9021 | |
55c11941 MS |
9022 | if (CNIC_LOADED(bp)) { |
9023 | /* Disable Timer scan */ | |
9024 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
9025 | /* | |
9026 | * Wait for at least 10ms and up to 2 second for the timers | |
9027 | * scan to complete | |
9028 | */ | |
9029 | for (i = 0; i < 200; i++) { | |
639d65b8 | 9030 | usleep_range(10000, 20000); |
55c11941 MS |
9031 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) |
9032 | break; | |
9033 | } | |
37b091ba | 9034 | } |
34f80b04 | 9035 | /* Clear ILT */ |
f2e0899f DK |
9036 | bnx2x_clear_func_ilt(bp, func); |
9037 | ||
9038 | /* Timers workaround bug for E2: if this is vnic-3, | |
9039 | * we need to set the entire ilt range for this timers. | |
9040 | */ | |
619c5cb6 | 9041 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
9042 | struct ilt_client_info ilt_cli; |
9043 | /* use dummy TM client */ | |
9044 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
9045 | ilt_cli.start = 0; | |
9046 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
9047 | ilt_cli.client_num = ILT_CLIENT_TM; | |
9048 | ||
9049 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
9050 | } | |
9051 | ||
9052 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 9053 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 9054 | bnx2x_pf_disable(bp); |
523224a3 DK |
9055 | |
9056 | bp->dmae_ready = 0; | |
34f80b04 EG |
9057 | } |
9058 | ||
9059 | static void bnx2x_reset_port(struct bnx2x *bp) | |
9060 | { | |
9061 | int port = BP_PORT(bp); | |
9062 | u32 val; | |
9063 | ||
619c5cb6 VZ |
9064 | /* Reset physical Link */ |
9065 | bnx2x__link_reset(bp); | |
9066 | ||
34f80b04 EG |
9067 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
9068 | ||
9069 | /* Do not rcv packets to BRB */ | |
9070 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
9071 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
9072 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
9073 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
9074 | ||
9075 | /* Configure AEU */ | |
9076 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
9077 | ||
9078 | msleep(100); | |
9079 | /* Check for BRB port occupancy */ | |
9080 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
9081 | if (val) | |
9082 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 9083 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
9084 | |
9085 | /* TODO: Close Doorbell port? */ | |
9086 | } | |
9087 | ||
1191cb83 | 9088 | static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 9089 | { |
3b603066 | 9090 | struct bnx2x_func_state_params func_params = {NULL}; |
34f80b04 | 9091 | |
619c5cb6 VZ |
9092 | /* Prepare parameters for function state transitions */ |
9093 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 9094 | |
619c5cb6 VZ |
9095 | func_params.f_obj = &bp->func_obj; |
9096 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 9097 | |
619c5cb6 | 9098 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 9099 | |
619c5cb6 | 9100 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
9101 | } |
9102 | ||
1191cb83 | 9103 | static int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 9104 | { |
3b603066 | 9105 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 | 9106 | int rc; |
228241eb | 9107 | |
619c5cb6 VZ |
9108 | /* Prepare parameters for function state transitions */ |
9109 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
9110 | func_params.f_obj = &bp->func_obj; | |
9111 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 9112 | |
619c5cb6 VZ |
9113 | /* |
9114 | * Try to stop the function the 'good way'. If fails (in case | |
9115 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
9116 | * not in a debug mode, perform a state transaction in order to | |
9117 | * enable further HW_RESET transaction. | |
9118 | */ | |
9119 | rc = bnx2x_func_state_change(bp, &func_params); | |
9120 | if (rc) { | |
34f80b04 | 9121 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 9122 | return rc; |
34f80b04 | 9123 | #else |
51c1a580 | 9124 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
619c5cb6 VZ |
9125 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
9126 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 9127 | #endif |
228241eb | 9128 | } |
a2fbb9ea | 9129 | |
619c5cb6 VZ |
9130 | return 0; |
9131 | } | |
523224a3 | 9132 | |
619c5cb6 VZ |
9133 | /** |
9134 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
9135 | * | |
9136 | * @bp: driver handle | |
9137 | * @unload_mode: requested function's unload mode | |
9138 | * | |
9139 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
9140 | */ | |
9141 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
9142 | { | |
9143 | u32 reset_code = 0; | |
9144 | int port = BP_PORT(bp); | |
3101c2bc | 9145 | |
619c5cb6 | 9146 | /* Select the UNLOAD request mode */ |
65abd74d YG |
9147 | if (unload_mode == UNLOAD_NORMAL) |
9148 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
9149 | ||
7d0446c2 | 9150 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 9151 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 9152 | |
7d0446c2 | 9153 | else if (bp->wol) { |
65abd74d YG |
9154 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
9155 | u8 *mac_addr = bp->dev->dev_addr; | |
29ed74c3 | 9156 | struct pci_dev *pdev = bp->pdev; |
65abd74d | 9157 | u32 val; |
f9977903 DK |
9158 | u16 pmc; |
9159 | ||
65abd74d | 9160 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
9161 | * preserve entry 0 which is used by the PMF |
9162 | */ | |
3395a033 | 9163 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
9164 | |
9165 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
9166 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
9167 | ||
9168 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
9169 | (mac_addr[4] << 8) | mac_addr[5]; | |
9170 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
9171 | ||
f9977903 | 9172 | /* Enable the PME and clear the status */ |
29ed74c3 | 9173 | pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc); |
f9977903 | 9174 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; |
29ed74c3 | 9175 | pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc); |
f9977903 | 9176 | |
65abd74d YG |
9177 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
9178 | ||
9179 | } else | |
9180 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 9181 | |
619c5cb6 VZ |
9182 | /* Send the request to the MCP */ |
9183 | if (!BP_NOMCP(bp)) | |
9184 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
9185 | else { | |
9186 | int path = BP_PATH(bp); | |
9187 | ||
51c1a580 | 9188 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
a8f47eb7 | 9189 | path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], |
9190 | bnx2x_load_count[path][2]); | |
9191 | bnx2x_load_count[path][0]--; | |
9192 | bnx2x_load_count[path][1 + port]--; | |
51c1a580 | 9193 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
a8f47eb7 | 9194 | path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], |
9195 | bnx2x_load_count[path][2]); | |
9196 | if (bnx2x_load_count[path][0] == 0) | |
619c5cb6 | 9197 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; |
a8f47eb7 | 9198 | else if (bnx2x_load_count[path][1 + port] == 0) |
619c5cb6 VZ |
9199 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; |
9200 | else | |
9201 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
9202 | } | |
9203 | ||
9204 | return reset_code; | |
9205 | } | |
9206 | ||
9207 | /** | |
9208 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
9209 | * | |
9210 | * @bp: driver handle | |
5d07d868 | 9211 | * @keep_link: true iff link should be kept up |
619c5cb6 | 9212 | */ |
5d07d868 | 9213 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) |
619c5cb6 | 9214 | { |
5d07d868 YM |
9215 | u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; |
9216 | ||
619c5cb6 VZ |
9217 | /* Report UNLOAD_DONE to MCP */ |
9218 | if (!BP_NOMCP(bp)) | |
5d07d868 | 9219 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); |
619c5cb6 VZ |
9220 | } |
9221 | ||
1191cb83 | 9222 | static int bnx2x_func_wait_started(struct bnx2x *bp) |
6debea87 DK |
9223 | { |
9224 | int tout = 50; | |
9225 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
9226 | ||
9227 | if (!bp->port.pmf) | |
9228 | return 0; | |
9229 | ||
9230 | /* | |
9231 | * (assumption: No Attention from MCP at this stage) | |
16a5fd92 | 9232 | * PMF probably in the middle of TX disable/enable transaction |
6debea87 | 9233 | * 1. Sync IRS for default SB |
16a5fd92 YM |
9234 | * 2. Sync SP queue - this guarantees us that attention handling started |
9235 | * 3. Wait, that TX disable/enable transaction completes | |
6debea87 | 9236 | * |
16a5fd92 YM |
9237 | * 1+2 guarantee that if DCBx attention was scheduled it already changed |
9238 | * pending bit of transaction from STARTED-->TX_STOPPED, if we already | |
9239 | * received completion for the transaction the state is TX_STOPPED. | |
6debea87 DK |
9240 | * State will return to STARTED after completion of TX_STOPPED-->STARTED |
9241 | * transaction. | |
9242 | */ | |
9243 | ||
9244 | /* make sure default SB ISR is done */ | |
9245 | if (msix) | |
9246 | synchronize_irq(bp->msix_table[0].vector); | |
9247 | else | |
9248 | synchronize_irq(bp->pdev->irq); | |
9249 | ||
9250 | flush_workqueue(bnx2x_wq); | |
370d4a26 | 9251 | flush_workqueue(bnx2x_iov_wq); |
6debea87 DK |
9252 | |
9253 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
9254 | BNX2X_F_STATE_STARTED && tout--) | |
9255 | msleep(20); | |
9256 | ||
9257 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
9258 | BNX2X_F_STATE_STARTED) { | |
9259 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 9260 | BNX2X_ERR("Wrong function state\n"); |
6debea87 DK |
9261 | return -EBUSY; |
9262 | #else | |
9263 | /* | |
9264 | * Failed to complete the transaction in a "good way" | |
9265 | * Force both transactions with CLR bit | |
9266 | */ | |
3b603066 | 9267 | struct bnx2x_func_state_params func_params = {NULL}; |
6debea87 | 9268 | |
51c1a580 | 9269 | DP(NETIF_MSG_IFDOWN, |
0c23ad37 | 9270 | "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n"); |
6debea87 DK |
9271 | |
9272 | func_params.f_obj = &bp->func_obj; | |
9273 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
9274 | &func_params.ramrod_flags); | |
9275 | ||
9276 | /* STARTED-->TX_ST0PPED */ | |
9277 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
9278 | bnx2x_func_state_change(bp, &func_params); | |
9279 | ||
9280 | /* TX_ST0PPED-->STARTED */ | |
9281 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
9282 | return bnx2x_func_state_change(bp, &func_params); | |
9283 | #endif | |
9284 | } | |
9285 | ||
9286 | return 0; | |
9287 | } | |
9288 | ||
eeed018c MK |
9289 | static void bnx2x_disable_ptp(struct bnx2x *bp) |
9290 | { | |
9291 | int port = BP_PORT(bp); | |
9292 | ||
9293 | /* Disable sending PTP packets to host */ | |
9294 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : | |
9295 | NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); | |
9296 | ||
9297 | /* Reset PTP event detection rules */ | |
9298 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
9299 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); | |
9300 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
9301 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); | |
9302 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : | |
9303 | NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); | |
9304 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : | |
9305 | NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); | |
9306 | ||
9307 | /* Disable the PTP feature */ | |
9308 | REG_WR(bp, port ? NIG_REG_P1_PTP_EN : | |
9309 | NIG_REG_P0_PTP_EN, 0x0); | |
9310 | } | |
9311 | ||
9312 | /* Called during unload, to stop PTP-related stuff */ | |
1444c301 | 9313 | static void bnx2x_stop_ptp(struct bnx2x *bp) |
eeed018c MK |
9314 | { |
9315 | /* Cancel PTP work queue. Should be done after the Tx queues are | |
9316 | * drained to prevent additional scheduling. | |
9317 | */ | |
9318 | cancel_work_sync(&bp->ptp_task); | |
9319 | ||
9320 | if (bp->ptp_tx_skb) { | |
9321 | dev_kfree_skb_any(bp->ptp_tx_skb); | |
9322 | bp->ptp_tx_skb = NULL; | |
9323 | } | |
9324 | ||
9325 | /* Disable PTP in HW */ | |
9326 | bnx2x_disable_ptp(bp); | |
9327 | ||
9328 | DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n"); | |
9329 | } | |
9330 | ||
5d07d868 | 9331 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) |
619c5cb6 VZ |
9332 | { |
9333 | int port = BP_PORT(bp); | |
6383c0b3 AE |
9334 | int i, rc = 0; |
9335 | u8 cos; | |
3b603066 | 9336 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 VZ |
9337 | u32 reset_code; |
9338 | ||
9339 | /* Wait until tx fastpath tasks complete */ | |
9340 | for_each_tx_queue(bp, i) { | |
9341 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
9342 | ||
6383c0b3 | 9343 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 9344 | rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); |
619c5cb6 VZ |
9345 | #ifdef BNX2X_STOP_ON_ERROR |
9346 | if (rc) | |
9347 | return; | |
9348 | #endif | |
9349 | } | |
9350 | ||
9351 | /* Give HW time to discard old tx messages */ | |
0926d499 | 9352 | usleep_range(1000, 2000); |
619c5cb6 VZ |
9353 | |
9354 | /* Clean all ETH MACs */ | |
15192a8c BW |
9355 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, |
9356 | false); | |
619c5cb6 VZ |
9357 | if (rc < 0) |
9358 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
9359 | ||
9360 | /* Clean up UC list */ | |
15192a8c | 9361 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, |
619c5cb6 VZ |
9362 | true); |
9363 | if (rc < 0) | |
51c1a580 MS |
9364 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
9365 | rc); | |
619c5cb6 | 9366 | |
77c52156 IM |
9367 | /* The whole *vlan_obj structure may be not initialized if VLAN |
9368 | * filtering offload is not supported by hardware. Currently this is | |
9369 | * true for all hardware covered by CHIP_IS_E1x(). | |
9370 | */ | |
9371 | if (!CHIP_IS_E1x(bp)) { | |
9372 | /* Remove all currently configured VLANs */ | |
9373 | rc = bnx2x_del_all_vlans(bp); | |
9374 | if (rc < 0) | |
9375 | BNX2X_ERR("Failed to delete all VLANs\n"); | |
9376 | } | |
66c6934a | 9377 | |
619c5cb6 VZ |
9378 | /* Disable LLH */ |
9379 | if (!CHIP_IS_E1(bp)) | |
9380 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
9381 | ||
9382 | /* Set "drop all" (stop Rx). | |
9383 | * We need to take a netif_addr_lock() here in order to prevent | |
9384 | * a race between the completion code and this code. | |
9385 | */ | |
9386 | netif_addr_lock_bh(bp->dev); | |
9387 | /* Schedule the rx_mode command */ | |
9388 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
9389 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
442866ff | 9390 | else if (bp->slowpath) |
619c5cb6 VZ |
9391 | bnx2x_set_storm_rx_mode(bp); |
9392 | ||
9393 | /* Cleanup multicast configuration */ | |
9394 | rparam.mcast_obj = &bp->mcast_obj; | |
9395 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
9396 | if (rc < 0) | |
9397 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
9398 | ||
9399 | netif_addr_unlock_bh(bp->dev); | |
9400 | ||
f1929b01 | 9401 | bnx2x_iov_chip_cleanup(bp); |
619c5cb6 | 9402 | |
6debea87 DK |
9403 | /* |
9404 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
9405 | * this function should perform FUNC, PORT or COMMON HW | |
9406 | * reset. | |
9407 | */ | |
9408 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
9409 | ||
9410 | /* | |
9411 | * (assumption: No Attention from MCP at this stage) | |
16a5fd92 | 9412 | * PMF probably in the middle of TX disable/enable transaction |
6debea87 DK |
9413 | */ |
9414 | rc = bnx2x_func_wait_started(bp); | |
9415 | if (rc) { | |
9416 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
9417 | #ifdef BNX2X_STOP_ON_ERROR | |
9418 | return; | |
9419 | #endif | |
9420 | } | |
9421 | ||
34f80b04 | 9422 | /* Close multi and leading connections |
619c5cb6 VZ |
9423 | * Completions for ramrods are collected in a synchronous way |
9424 | */ | |
55c11941 | 9425 | for_each_eth_queue(bp, i) |
619c5cb6 | 9426 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
9427 | #ifdef BNX2X_STOP_ON_ERROR |
9428 | return; | |
9429 | #else | |
228241eb | 9430 | goto unload_error; |
523224a3 | 9431 | #endif |
55c11941 MS |
9432 | |
9433 | if (CNIC_LOADED(bp)) { | |
9434 | for_each_cnic_queue(bp, i) | |
9435 | if (bnx2x_stop_queue(bp, i)) | |
9436 | #ifdef BNX2X_STOP_ON_ERROR | |
9437 | return; | |
9438 | #else | |
9439 | goto unload_error; | |
9440 | #endif | |
9441 | } | |
9442 | ||
619c5cb6 VZ |
9443 | /* If SP settings didn't get completed so far - something |
9444 | * very wrong has happen. | |
9445 | */ | |
9446 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
9447 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 9448 | |
619c5cb6 VZ |
9449 | #ifndef BNX2X_STOP_ON_ERROR |
9450 | unload_error: | |
9451 | #endif | |
523224a3 | 9452 | rc = bnx2x_func_stop(bp); |
da5a662a | 9453 | if (rc) { |
523224a3 | 9454 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 9455 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 9456 | return; |
523224a3 | 9457 | #endif |
34f80b04 | 9458 | } |
a2fbb9ea | 9459 | |
eeed018c MK |
9460 | /* stop_ptp should be after the Tx queues are drained to prevent |
9461 | * scheduling to the cancelled PTP work queue. It should also be after | |
9462 | * function stop ramrod is sent, since as part of this ramrod FW access | |
9463 | * PTP registers. | |
9464 | */ | |
d53c66a5 ED |
9465 | if (bp->flags & PTP_SUPPORTED) |
9466 | bnx2x_stop_ptp(bp); | |
eeed018c | 9467 | |
523224a3 DK |
9468 | /* Disable HW interrupts, NAPI */ |
9469 | bnx2x_netif_stop(bp, 1); | |
26614ba5 MS |
9470 | /* Delete all NAPI objects */ |
9471 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
9472 | if (CNIC_LOADED(bp)) |
9473 | bnx2x_del_all_napi_cnic(bp); | |
523224a3 DK |
9474 | |
9475 | /* Release IRQs */ | |
d6214d7a | 9476 | bnx2x_free_irq(bp); |
523224a3 | 9477 | |
b44e108b GP |
9478 | /* Reset the chip, unless PCI function is offline. If we reach this |
9479 | * point following a PCI error handling, it means device is really | |
9480 | * in a bad state and we're about to remove it, so reset the chip | |
9481 | * is not a good idea. | |
9482 | */ | |
9483 | if (!pci_channel_offline(bp->pdev)) { | |
9484 | rc = bnx2x_reset_hw(bp, reset_code); | |
9485 | if (rc) | |
9486 | BNX2X_ERR("HW_RESET failed\n"); | |
9487 | } | |
a2fbb9ea | 9488 | |
619c5cb6 | 9489 | /* Report UNLOAD_DONE to MCP */ |
5d07d868 | 9490 | bnx2x_send_unload_done(bp, keep_link); |
72fd0718 VZ |
9491 | } |
9492 | ||
9f6c9258 | 9493 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
9494 | { |
9495 | u32 val; | |
9496 | ||
51c1a580 | 9497 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
72fd0718 VZ |
9498 | |
9499 | if (CHIP_IS_E1(bp)) { | |
9500 | int port = BP_PORT(bp); | |
9501 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
9502 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
9503 | ||
9504 | val = REG_RD(bp, addr); | |
9505 | val &= ~(0x300); | |
9506 | REG_WR(bp, addr, val); | |
619c5cb6 | 9507 | } else { |
72fd0718 VZ |
9508 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
9509 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
9510 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
9511 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
9512 | } | |
9513 | } | |
9514 | ||
72fd0718 VZ |
9515 | /* Close gates #2, #3 and #4: */ |
9516 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
9517 | { | |
c9ee9206 | 9518 | u32 val; |
72fd0718 VZ |
9519 | |
9520 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
9521 | if (!CHIP_IS_E1(bp)) { | |
9522 | /* #4 */ | |
c9ee9206 | 9523 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 9524 | /* #2 */ |
c9ee9206 | 9525 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
9526 | } |
9527 | ||
9528 | /* #3 */ | |
c9ee9206 VZ |
9529 | if (CHIP_IS_E1x(bp)) { |
9530 | /* Prevent interrupts from HC on both ports */ | |
9531 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
9532 | REG_WR(bp, HC_REG_CONFIG_1, | |
9533 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
9534 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
9535 | ||
9536 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
9537 | REG_WR(bp, HC_REG_CONFIG_0, | |
9538 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
9539 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
9540 | } else { | |
d82603c6 | 9541 | /* Prevent incoming interrupts in IGU */ |
c9ee9206 VZ |
9542 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
9543 | ||
9544 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
9545 | (!close) ? | |
9546 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
9547 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
9548 | } | |
72fd0718 | 9549 | |
51c1a580 | 9550 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
72fd0718 VZ |
9551 | close ? "closing" : "opening"); |
9552 | mmiowb(); | |
9553 | } | |
9554 | ||
9555 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
9556 | ||
9557 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
9558 | { | |
9559 | /* Do some magic... */ | |
9560 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
9561 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
9562 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
9563 | } | |
9564 | ||
e8920674 DK |
9565 | /** |
9566 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 9567 | * |
e8920674 DK |
9568 | * @bp: driver handle |
9569 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
9570 | */ |
9571 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
9572 | { | |
9573 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
9574 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
9575 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
9576 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
9577 | } | |
9578 | ||
f85582f8 | 9579 | /** |
e8920674 | 9580 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 9581 | * |
e8920674 DK |
9582 | * @bp: driver handle |
9583 | * @magic_val: old value of 'magic' bit. | |
9584 | * | |
9585 | * Takes care of CLP configurations. | |
72fd0718 VZ |
9586 | */ |
9587 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
9588 | { | |
9589 | u32 shmem; | |
9590 | u32 validity_offset; | |
9591 | ||
51c1a580 | 9592 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
72fd0718 VZ |
9593 | |
9594 | /* Set `magic' bit in order to save MF config */ | |
9595 | if (!CHIP_IS_E1(bp)) | |
9596 | bnx2x_clp_reset_prep(bp, magic_val); | |
9597 | ||
9598 | /* Get shmem offset */ | |
9599 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
c55e771b BW |
9600 | validity_offset = |
9601 | offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); | |
72fd0718 VZ |
9602 | |
9603 | /* Clear validity map flags */ | |
9604 | if (shmem > 0) | |
9605 | REG_WR(bp, shmem + validity_offset, 0); | |
9606 | } | |
9607 | ||
9608 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
9609 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
9610 | ||
e8920674 DK |
9611 | /** |
9612 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 9613 | * |
e8920674 | 9614 | * @bp: driver handle |
72fd0718 | 9615 | */ |
1191cb83 | 9616 | static void bnx2x_mcp_wait_one(struct bnx2x *bp) |
72fd0718 VZ |
9617 | { |
9618 | /* special handling for emulation and FPGA, | |
9619 | wait 10 times longer */ | |
9620 | if (CHIP_REV_IS_SLOW(bp)) | |
9621 | msleep(MCP_ONE_TIMEOUT*10); | |
9622 | else | |
9623 | msleep(MCP_ONE_TIMEOUT); | |
9624 | } | |
9625 | ||
1b6e2ceb DK |
9626 | /* |
9627 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
9628 | */ | |
9629 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 9630 | { |
1b6e2ceb DK |
9631 | int cnt = 0; |
9632 | u32 val = 0; | |
72fd0718 | 9633 | |
1b6e2ceb DK |
9634 | do { |
9635 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
f7084059 GP |
9636 | |
9637 | /* If we read all 0xFFs, means we are in PCI error state and | |
9638 | * should bail out to avoid crashes on adapter's FW reads. | |
9639 | */ | |
9640 | if (bp->common.shmem_base == 0xFFFFFFFF) { | |
9641 | bp->flags |= NO_MCP_FLAG; | |
9642 | return -ENODEV; | |
9643 | } | |
9644 | ||
1b6e2ceb DK |
9645 | if (bp->common.shmem_base) { |
9646 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
9647 | if (val & SHR_MEM_VALIDITY_MB) | |
9648 | return 0; | |
9649 | } | |
72fd0718 | 9650 | |
1b6e2ceb | 9651 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 9652 | |
1b6e2ceb | 9653 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 9654 | |
1b6e2ceb | 9655 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 9656 | |
1b6e2ceb DK |
9657 | return -ENODEV; |
9658 | } | |
72fd0718 | 9659 | |
1b6e2ceb DK |
9660 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
9661 | { | |
9662 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 9663 | |
72fd0718 VZ |
9664 | /* Restore the `magic' bit value */ |
9665 | if (!CHIP_IS_E1(bp)) | |
9666 | bnx2x_clp_reset_done(bp, magic_val); | |
9667 | ||
9668 | return rc; | |
9669 | } | |
9670 | ||
9671 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
9672 | { | |
9673 | if (!CHIP_IS_E1(bp)) { | |
9674 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
9675 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
9676 | mmiowb(); |
9677 | } | |
9678 | } | |
9679 | ||
9680 | /* | |
9681 | * Reset the whole chip except for: | |
9682 | * - PCIE core | |
9683 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
9684 | * one reset bit) | |
9685 | * - IGU | |
9686 | * - MISC (including AEU) | |
9687 | * - GRC | |
9688 | * - RBCN, RBCP | |
9689 | */ | |
c9ee9206 | 9690 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
9691 | { |
9692 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 9693 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
9694 | |
9695 | /* | |
9696 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
9697 | * (per chip) blocks. | |
9698 | */ | |
9699 | global_bits2 = | |
9700 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
9701 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 9702 | |
c55e771b BW |
9703 | /* Don't reset the following blocks. |
9704 | * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be | |
9705 | * reset, as in 4 port device they might still be owned | |
9706 | * by the MCP (there is only one leader per path). | |
9707 | */ | |
72fd0718 VZ |
9708 | not_reset_mask1 = |
9709 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
9710 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
9711 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
9712 | ||
9713 | not_reset_mask2 = | |
c9ee9206 | 9714 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
9715 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
9716 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
9717 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
9718 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
9719 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
9720 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
9721 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
9722 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
c55e771b BW |
9723 | MISC_REGISTERS_RESET_REG_2_PGLC | |
9724 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
9725 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
9726 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
9727 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
9728 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
9729 | MISC_REGISTERS_RESET_REG_2_UMAC1; | |
72fd0718 | 9730 | |
8736c826 VZ |
9731 | /* |
9732 | * Keep the following blocks in reset: | |
9733 | * - all xxMACs are handled by the bnx2x_link code. | |
9734 | */ | |
9735 | stay_reset2 = | |
8736c826 VZ |
9736 | MISC_REGISTERS_RESET_REG_2_XMAC | |
9737 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
9738 | ||
9739 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
9740 | reset_mask1 = 0xffffffff; |
9741 | ||
9742 | if (CHIP_IS_E1(bp)) | |
9743 | reset_mask2 = 0xffff; | |
8736c826 | 9744 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 9745 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
9746 | else if (CHIP_IS_E2(bp)) |
9747 | reset_mask2 = 0xfffff; | |
9748 | else /* CHIP_IS_E3 */ | |
9749 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
9750 | |
9751 | /* Don't reset global blocks unless we need to */ | |
9752 | if (!global) | |
9753 | reset_mask2 &= ~global_bits2; | |
9754 | ||
9755 | /* | |
9756 | * In case of attention in the QM, we need to reset PXP | |
9757 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
9758 | * because otherwise QM reset would release 'close the gates' shortly | |
9759 | * before resetting the PXP, then the PSWRQ would send a write | |
9760 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
9761 | * read the payload data from PSWWR, but PSWWR would not | |
9762 | * respond. The write queue in PGLUE would stuck, dmae commands | |
9763 | * would not return. Therefore it's important to reset the second | |
9764 | * reset register (containing the | |
9765 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
9766 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
9767 | * bit). | |
9768 | */ | |
72fd0718 VZ |
9769 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
9770 | reset_mask2 & (~not_reset_mask2)); | |
9771 | ||
c9ee9206 VZ |
9772 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
9773 | reset_mask1 & (~not_reset_mask1)); | |
9774 | ||
72fd0718 VZ |
9775 | barrier(); |
9776 | mmiowb(); | |
9777 | ||
8736c826 VZ |
9778 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
9779 | reset_mask2 & (~stay_reset2)); | |
9780 | ||
9781 | barrier(); | |
9782 | mmiowb(); | |
9783 | ||
c9ee9206 | 9784 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
9785 | mmiowb(); |
9786 | } | |
9787 | ||
c9ee9206 VZ |
9788 | /** |
9789 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
9790 | * It should get cleared in no more than 1s. | |
9791 | * | |
9792 | * @bp: driver handle | |
9793 | * | |
9794 | * It should get cleared in no more than 1s. Returns 0 if | |
9795 | * pending writes bit gets cleared. | |
9796 | */ | |
9797 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
9798 | { | |
9799 | u32 cnt = 1000; | |
9800 | u32 pend_bits = 0; | |
9801 | ||
9802 | do { | |
9803 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
9804 | ||
9805 | if (pend_bits == 0) | |
9806 | break; | |
9807 | ||
0926d499 | 9808 | usleep_range(1000, 2000); |
c9ee9206 VZ |
9809 | } while (cnt-- > 0); |
9810 | ||
9811 | if (cnt <= 0) { | |
9812 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
9813 | pend_bits); | |
9814 | return -EBUSY; | |
9815 | } | |
9816 | ||
9817 | return 0; | |
9818 | } | |
9819 | ||
9820 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
9821 | { |
9822 | int cnt = 1000; | |
9823 | u32 val = 0; | |
9824 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
2de67439 | 9825 | u32 tags_63_32 = 0; |
72fd0718 VZ |
9826 | |
9827 | /* Empty the Tetris buffer, wait for 1s */ | |
9828 | do { | |
9829 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
9830 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
9831 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
9832 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
9833 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
c55e771b BW |
9834 | if (CHIP_IS_E3(bp)) |
9835 | tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); | |
9836 | ||
72fd0718 VZ |
9837 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && |
9838 | ((port_is_idle_0 & 0x1) == 0x1) && | |
9839 | ((port_is_idle_1 & 0x1) == 0x1) && | |
c55e771b BW |
9840 | (pgl_exp_rom2 == 0xffffffff) && |
9841 | (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) | |
72fd0718 | 9842 | break; |
0926d499 | 9843 | usleep_range(1000, 2000); |
72fd0718 VZ |
9844 | } while (cnt-- > 0); |
9845 | ||
9846 | if (cnt <= 0) { | |
51c1a580 MS |
9847 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
9848 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
72fd0718 VZ |
9849 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
9850 | pgl_exp_rom2); | |
9851 | return -EAGAIN; | |
9852 | } | |
9853 | ||
9854 | barrier(); | |
9855 | ||
9856 | /* Close gates #2, #3 and #4 */ | |
9857 | bnx2x_set_234_gates(bp, true); | |
9858 | ||
c9ee9206 VZ |
9859 | /* Poll for IGU VQs for 57712 and newer chips */ |
9860 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
9861 | return -EAGAIN; | |
9862 | ||
72fd0718 VZ |
9863 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
9864 | ||
9865 | /* Clear "unprepared" bit */ | |
9866 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
9867 | barrier(); | |
9868 | ||
9869 | /* Make sure all is written to the chip before the reset */ | |
9870 | mmiowb(); | |
9871 | ||
9872 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
9873 | * PSWHST, GRC and PSWRD Tetris buffer. | |
9874 | */ | |
0926d499 | 9875 | usleep_range(1000, 2000); |
72fd0718 VZ |
9876 | |
9877 | /* Prepare to chip reset: */ | |
9878 | /* MCP */ | |
c9ee9206 VZ |
9879 | if (global) |
9880 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
9881 | |
9882 | /* PXP */ | |
9883 | bnx2x_pxp_prep(bp); | |
9884 | barrier(); | |
9885 | ||
9886 | /* reset the chip */ | |
c9ee9206 | 9887 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
9888 | barrier(); |
9889 | ||
9dcd9acd DK |
9890 | /* clear errors in PGB */ |
9891 | if (!CHIP_IS_E1x(bp)) | |
9892 | REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); | |
9893 | ||
72fd0718 VZ |
9894 | /* Recover after reset: */ |
9895 | /* MCP */ | |
c9ee9206 | 9896 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
9897 | return -EAGAIN; |
9898 | ||
c9ee9206 VZ |
9899 | /* TBD: Add resetting the NO_MCP mode DB here */ |
9900 | ||
72fd0718 VZ |
9901 | /* Open the gates #2, #3 and #4 */ |
9902 | bnx2x_set_234_gates(bp, false); | |
9903 | ||
9904 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
9905 | * reset state, re-enable attentions. */ | |
9906 | ||
a2fbb9ea ET |
9907 | return 0; |
9908 | } | |
9909 | ||
910cc727 | 9910 | static int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
9911 | { |
9912 | int rc = 0; | |
c9ee9206 | 9913 | bool global = bnx2x_reset_is_global(bp); |
95c6c616 AE |
9914 | u32 load_code; |
9915 | ||
9916 | /* if not going to reset MCP - load "fake" driver to reset HW while | |
9917 | * driver is owner of the HW | |
9918 | */ | |
9919 | if (!global && !BP_NOMCP(bp)) { | |
5d07d868 YM |
9920 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, |
9921 | DRV_MSG_CODE_LOAD_REQ_WITH_LFA); | |
95c6c616 AE |
9922 | if (!load_code) { |
9923 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9924 | rc = -EAGAIN; | |
9925 | goto exit_leader_reset; | |
9926 | } | |
9927 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && | |
9928 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { | |
9929 | BNX2X_ERR("MCP unexpected resp, aborting\n"); | |
9930 | rc = -EAGAIN; | |
9931 | goto exit_leader_reset2; | |
9932 | } | |
9933 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
9934 | if (!load_code) { | |
9935 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9936 | rc = -EAGAIN; | |
9937 | goto exit_leader_reset2; | |
9938 | } | |
9939 | } | |
c9ee9206 | 9940 | |
72fd0718 | 9941 | /* Try to recover after the failure */ |
c9ee9206 | 9942 | if (bnx2x_process_kill(bp, global)) { |
51c1a580 MS |
9943 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
9944 | BP_PATH(bp)); | |
72fd0718 | 9945 | rc = -EAGAIN; |
95c6c616 | 9946 | goto exit_leader_reset2; |
72fd0718 VZ |
9947 | } |
9948 | ||
c9ee9206 VZ |
9949 | /* |
9950 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
9951 | * state. | |
9952 | */ | |
72fd0718 | 9953 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
9954 | if (global) |
9955 | bnx2x_clear_reset_global(bp); | |
72fd0718 | 9956 | |
95c6c616 AE |
9957 | exit_leader_reset2: |
9958 | /* unload "fake driver" if it was loaded */ | |
9959 | if (!global && !BP_NOMCP(bp)) { | |
9960 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); | |
9961 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
9962 | } | |
72fd0718 VZ |
9963 | exit_leader_reset: |
9964 | bp->is_leader = 0; | |
c9ee9206 VZ |
9965 | bnx2x_release_leader_lock(bp); |
9966 | smp_mb(); | |
72fd0718 VZ |
9967 | return rc; |
9968 | } | |
9969 | ||
1191cb83 | 9970 | static void bnx2x_recovery_failed(struct bnx2x *bp) |
c9ee9206 VZ |
9971 | { |
9972 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
9973 | ||
9974 | /* Disconnect this device */ | |
9975 | netif_device_detach(bp->dev); | |
9976 | ||
9977 | /* | |
9978 | * Block ifup for all function on this engine until "process kill" | |
9979 | * or power cycle. | |
9980 | */ | |
9981 | bnx2x_set_reset_in_progress(bp); | |
9982 | ||
9983 | /* Shut down the power */ | |
9984 | bnx2x_set_power_state(bp, PCI_D3hot); | |
9985 | ||
9986 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
9987 | ||
9988 | smp_mb(); | |
9989 | } | |
9990 | ||
9991 | /* | |
9992 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 9993 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
9994 | * will never be called when netif_running(bp->dev) is false. |
9995 | */ | |
9996 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
9997 | { | |
7a752993 | 9998 | u32 error_recovered, error_unrecovered; |
6014d640 MC |
9999 | bool is_parity, global = false; |
10000 | #ifdef CONFIG_BNX2X_SRIOV | |
10001 | int vf_idx; | |
10002 | ||
10003 | for (vf_idx = 0; vf_idx < bp->requested_nr_virtfn; vf_idx++) { | |
10004 | struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); | |
c9ee9206 | 10005 | |
6014d640 MC |
10006 | if (vf) |
10007 | vf->state = VF_LOST; | |
10008 | } | |
10009 | #endif | |
72fd0718 VZ |
10010 | DP(NETIF_MSG_HW, "Handling parity\n"); |
10011 | while (1) { | |
10012 | switch (bp->recovery_state) { | |
10013 | case BNX2X_RECOVERY_INIT: | |
10014 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
95c6c616 AE |
10015 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
10016 | WARN_ON(!is_parity); | |
c9ee9206 | 10017 | |
72fd0718 | 10018 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
10019 | if (bnx2x_trylock_leader_lock(bp)) { |
10020 | bnx2x_set_reset_in_progress(bp); | |
10021 | /* | |
10022 | * Check if there is a global attention and if | |
10023 | * there was a global attention, set the global | |
10024 | * reset bit. | |
10025 | */ | |
10026 | ||
10027 | if (global) | |
10028 | bnx2x_set_reset_global(bp); | |
10029 | ||
72fd0718 | 10030 | bp->is_leader = 1; |
c9ee9206 | 10031 | } |
72fd0718 VZ |
10032 | |
10033 | /* Stop the driver */ | |
10034 | /* If interface has been removed - break */ | |
5d07d868 | 10035 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) |
72fd0718 VZ |
10036 | return; |
10037 | ||
10038 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 | 10039 | |
c9ee9206 VZ |
10040 | /* Ensure "is_leader", MCP command sequence and |
10041 | * "recovery_state" update values are seen on other | |
10042 | * CPUs. | |
72fd0718 | 10043 | */ |
c9ee9206 | 10044 | smp_mb(); |
72fd0718 VZ |
10045 | break; |
10046 | ||
10047 | case BNX2X_RECOVERY_WAIT: | |
10048 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
10049 | if (bp->is_leader) { | |
c9ee9206 | 10050 | int other_engine = BP_PATH(bp) ? 0 : 1; |
889b9af3 AE |
10051 | bool other_load_status = |
10052 | bnx2x_get_load_status(bp, other_engine); | |
10053 | bool load_status = | |
10054 | bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
10055 | global = bnx2x_reset_is_global(bp); |
10056 | ||
10057 | /* | |
10058 | * In case of a parity in a global block, let | |
10059 | * the first leader that performs a | |
10060 | * leader_reset() reset the global blocks in | |
10061 | * order to clear global attentions. Otherwise | |
16a5fd92 | 10062 | * the gates will remain closed for that |
c9ee9206 VZ |
10063 | * engine. |
10064 | */ | |
889b9af3 AE |
10065 | if (load_status || |
10066 | (global && other_load_status)) { | |
72fd0718 VZ |
10067 | /* Wait until all other functions get |
10068 | * down. | |
10069 | */ | |
7be08a72 | 10070 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
10071 | HZ/10); |
10072 | return; | |
10073 | } else { | |
10074 | /* If all other functions got down - | |
10075 | * try to bring the chip back to | |
10076 | * normal. In any case it's an exit | |
10077 | * point for a leader. | |
10078 | */ | |
c9ee9206 VZ |
10079 | if (bnx2x_leader_reset(bp)) { |
10080 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
10081 | return; |
10082 | } | |
10083 | ||
c9ee9206 VZ |
10084 | /* If we are here, means that the |
10085 | * leader has succeeded and doesn't | |
10086 | * want to be a leader any more. Try | |
10087 | * to continue as a none-leader. | |
10088 | */ | |
10089 | break; | |
72fd0718 VZ |
10090 | } |
10091 | } else { /* non-leader */ | |
c9ee9206 | 10092 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
10093 | /* Try to get a LEADER_LOCK HW lock as |
10094 | * long as a former leader may have | |
10095 | * been unloaded by the user or | |
10096 | * released a leadership by another | |
10097 | * reason. | |
10098 | */ | |
c9ee9206 | 10099 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
10100 | /* I'm a leader now! Restart a |
10101 | * switch case. | |
10102 | */ | |
10103 | bp->is_leader = 1; | |
10104 | break; | |
10105 | } | |
10106 | ||
7be08a72 | 10107 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
10108 | HZ/10); |
10109 | return; | |
10110 | ||
c9ee9206 VZ |
10111 | } else { |
10112 | /* | |
10113 | * If there was a global attention, wait | |
10114 | * for it to be cleared. | |
10115 | */ | |
10116 | if (bnx2x_reset_is_global(bp)) { | |
10117 | schedule_delayed_work( | |
7be08a72 AE |
10118 | &bp->sp_rtnl_task, |
10119 | HZ/10); | |
c9ee9206 VZ |
10120 | return; |
10121 | } | |
10122 | ||
7a752993 AE |
10123 | error_recovered = |
10124 | bp->eth_stats.recoverable_error; | |
10125 | error_unrecovered = | |
10126 | bp->eth_stats.unrecoverable_error; | |
95c6c616 AE |
10127 | bp->recovery_state = |
10128 | BNX2X_RECOVERY_NIC_LOADING; | |
10129 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { | |
7a752993 | 10130 | error_unrecovered++; |
95c6c616 | 10131 | netdev_err(bp->dev, |
51c1a580 | 10132 | "Recovery failed. Power cycle needed\n"); |
95c6c616 AE |
10133 | /* Disconnect this device */ |
10134 | netif_device_detach(bp->dev); | |
10135 | /* Shut down the power */ | |
10136 | bnx2x_set_power_state( | |
10137 | bp, PCI_D3hot); | |
10138 | smp_mb(); | |
10139 | } else { | |
c9ee9206 VZ |
10140 | bp->recovery_state = |
10141 | BNX2X_RECOVERY_DONE; | |
7a752993 | 10142 | error_recovered++; |
c9ee9206 VZ |
10143 | smp_mb(); |
10144 | } | |
7a752993 AE |
10145 | bp->eth_stats.recoverable_error = |
10146 | error_recovered; | |
10147 | bp->eth_stats.unrecoverable_error = | |
10148 | error_unrecovered; | |
c9ee9206 | 10149 | |
72fd0718 VZ |
10150 | return; |
10151 | } | |
10152 | } | |
10153 | default: | |
10154 | return; | |
10155 | } | |
10156 | } | |
10157 | } | |
10158 | ||
883ce97d | 10159 | static int bnx2x_udp_port_update(struct bnx2x *bp) |
f34fa14c RB |
10160 | { |
10161 | struct bnx2x_func_switch_update_params *switch_update_params; | |
10162 | struct bnx2x_func_state_params func_params = {NULL}; | |
883ce97d YM |
10163 | struct bnx2x_udp_tunnel *udp_tunnel; |
10164 | u16 vxlan_port = 0, geneve_port = 0; | |
f34fa14c RB |
10165 | int rc; |
10166 | ||
10167 | switch_update_params = &func_params.params.switch_update; | |
10168 | ||
10169 | /* Prepare parameters for function state transitions */ | |
10170 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
10171 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
10172 | ||
10173 | func_params.f_obj = &bp->func_obj; | |
10174 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
10175 | ||
10176 | /* Function parameters */ | |
10177 | __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG, | |
10178 | &switch_update_params->changes); | |
883ce97d YM |
10179 | |
10180 | if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) { | |
10181 | udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]; | |
10182 | geneve_port = udp_tunnel->dst_port; | |
10183 | switch_update_params->geneve_dst_port = geneve_port; | |
10184 | } | |
10185 | ||
10186 | if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) { | |
10187 | udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]; | |
10188 | vxlan_port = udp_tunnel->dst_port; | |
10189 | switch_update_params->vxlan_dst_port = vxlan_port; | |
10190 | } | |
10191 | ||
10192 | /* Re-enable inner-rss for the offloaded UDP tunnels */ | |
10193 | __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS, | |
10194 | &switch_update_params->changes); | |
10195 | ||
f34fa14c RB |
10196 | rc = bnx2x_func_state_change(bp, &func_params); |
10197 | if (rc) | |
883ce97d YM |
10198 | BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n", |
10199 | vxlan_port, geneve_port, rc); | |
10200 | else | |
10201 | DP(BNX2X_MSG_SP, | |
10202 | "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n", | |
10203 | vxlan_port, geneve_port); | |
10204 | ||
f34fa14c RB |
10205 | return rc; |
10206 | } | |
10207 | ||
883ce97d YM |
10208 | static void __bnx2x_add_udp_port(struct bnx2x *bp, u16 port, |
10209 | enum bnx2x_udp_port_type type) | |
f34fa14c | 10210 | { |
883ce97d YM |
10211 | struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type]; |
10212 | ||
360d9df2 | 10213 | if (!netif_running(bp->dev) || !IS_PF(bp) || CHIP_IS_E1x(bp)) |
883ce97d YM |
10214 | return; |
10215 | ||
10216 | if (udp_port->count && udp_port->dst_port == port) { | |
10217 | udp_port->count++; | |
f34fa14c | 10218 | return; |
883ce97d | 10219 | } |
f34fa14c | 10220 | |
883ce97d YM |
10221 | if (udp_port->count) { |
10222 | DP(BNX2X_MSG_SP, | |
10223 | "UDP tunnel [%d] - destination port limit reached\n", | |
10224 | type); | |
ac7eccd4 JB |
10225 | return; |
10226 | } | |
10227 | ||
883ce97d YM |
10228 | udp_port->dst_port = port; |
10229 | udp_port->count = 1; | |
10230 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0); | |
10231 | } | |
10232 | ||
10233 | static void __bnx2x_del_udp_port(struct bnx2x *bp, u16 port, | |
10234 | enum bnx2x_udp_port_type type) | |
10235 | { | |
10236 | struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type]; | |
10237 | ||
360d9df2 | 10238 | if (!IS_PF(bp) || CHIP_IS_E1x(bp)) |
883ce97d YM |
10239 | return; |
10240 | ||
10241 | if (!udp_port->count || udp_port->dst_port != port) { | |
10242 | DP(BNX2X_MSG_SP, "Invalid UDP tunnel [%d] port\n", | |
10243 | type); | |
f34fa14c RB |
10244 | return; |
10245 | } | |
10246 | ||
883ce97d YM |
10247 | /* Remove reference, and make certain it's no longer in use */ |
10248 | udp_port->count--; | |
10249 | if (udp_port->count) | |
10250 | return; | |
10251 | udp_port->dst_port = 0; | |
10252 | ||
10253 | if (netif_running(bp->dev)) | |
10254 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0); | |
10255 | else | |
10256 | DP(BNX2X_MSG_SP, "Deleted UDP tunnel [%d] port %d\n", | |
10257 | type, port); | |
f34fa14c | 10258 | } |
883ce97d | 10259 | |
6b352912 AD |
10260 | static void bnx2x_udp_tunnel_add(struct net_device *netdev, |
10261 | struct udp_tunnel_info *ti) | |
883ce97d YM |
10262 | { |
10263 | struct bnx2x *bp = netdev_priv(netdev); | |
6b352912 | 10264 | u16 t_port = ntohs(ti->port); |
883ce97d | 10265 | |
6b352912 AD |
10266 | switch (ti->type) { |
10267 | case UDP_TUNNEL_TYPE_VXLAN: | |
10268 | __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN); | |
10269 | break; | |
10270 | case UDP_TUNNEL_TYPE_GENEVE: | |
10271 | __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE); | |
10272 | break; | |
10273 | default: | |
10274 | break; | |
10275 | } | |
f34fa14c RB |
10276 | } |
10277 | ||
6b352912 AD |
10278 | static void bnx2x_udp_tunnel_del(struct net_device *netdev, |
10279 | struct udp_tunnel_info *ti) | |
f34fa14c RB |
10280 | { |
10281 | struct bnx2x *bp = netdev_priv(netdev); | |
6b352912 | 10282 | u16 t_port = ntohs(ti->port); |
f34fa14c | 10283 | |
6b352912 AD |
10284 | switch (ti->type) { |
10285 | case UDP_TUNNEL_TYPE_VXLAN: | |
10286 | __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN); | |
10287 | break; | |
10288 | case UDP_TUNNEL_TYPE_GENEVE: | |
10289 | __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE); | |
10290 | break; | |
10291 | default: | |
10292 | break; | |
10293 | } | |
f34fa14c | 10294 | } |
f34fa14c | 10295 | |
56ad3152 MS |
10296 | static int bnx2x_close(struct net_device *dev); |
10297 | ||
72fd0718 VZ |
10298 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
10299 | * scheduled on a general queue in order to prevent a dead lock. | |
10300 | */ | |
7be08a72 | 10301 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 10302 | { |
7be08a72 | 10303 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
10304 | |
10305 | rtnl_lock(); | |
10306 | ||
8395be5e AE |
10307 | if (!netif_running(bp->dev)) { |
10308 | rtnl_unlock(); | |
10309 | return; | |
10310 | } | |
7be08a72 | 10311 | |
6bf07b8e | 10312 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
7be08a72 | 10313 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e YM |
10314 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
10315 | "you will need to reboot when done\n"); | |
10316 | goto sp_rtnl_not_reset; | |
7be08a72 | 10317 | #endif |
7be08a72 | 10318 | /* |
b1fb8740 VZ |
10319 | * Clear all pending SP commands as we are going to reset the |
10320 | * function anyway. | |
7be08a72 | 10321 | */ |
b1fb8740 VZ |
10322 | bp->sp_rtnl_state = 0; |
10323 | smp_mb(); | |
10324 | ||
72fd0718 | 10325 | bnx2x_parity_recover(bp); |
b1fb8740 | 10326 | |
8395be5e AE |
10327 | rtnl_unlock(); |
10328 | return; | |
b1fb8740 VZ |
10329 | } |
10330 | ||
10331 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
6bf07b8e YM |
10332 | #ifdef BNX2X_STOP_ON_ERROR |
10333 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" | |
10334 | "you will need to reboot when done\n"); | |
10335 | goto sp_rtnl_not_reset; | |
10336 | #endif | |
10337 | ||
b1fb8740 VZ |
10338 | /* |
10339 | * Clear all pending SP commands as we are going to reset the | |
10340 | * function anyway. | |
10341 | */ | |
10342 | bp->sp_rtnl_state = 0; | |
10343 | smp_mb(); | |
10344 | ||
6a9f0ecb SRK |
10345 | /* Immediately indicate link as down */ |
10346 | bp->link_vars.link_up = 0; | |
10347 | bp->force_link_down = true; | |
10348 | netif_carrier_off(bp->dev); | |
10349 | BNX2X_ERR("Indicating link is down due to Tx-timeout\n"); | |
10350 | ||
5d07d868 | 10351 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); |
442866ff ZY |
10352 | /* When ret value shows failure of allocation failure, |
10353 | * the nic is rebooted again. If open still fails, a error | |
10354 | * message to notify the user. | |
10355 | */ | |
10356 | if (bnx2x_nic_load(bp, LOAD_NORMAL) == -ENOMEM) { | |
10357 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); | |
10358 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) | |
10359 | BNX2X_ERR("Open the NIC fails again!\n"); | |
10360 | } | |
8395be5e AE |
10361 | rtnl_unlock(); |
10362 | return; | |
72fd0718 | 10363 | } |
b1fb8740 VZ |
10364 | #ifdef BNX2X_STOP_ON_ERROR |
10365 | sp_rtnl_not_reset: | |
10366 | #endif | |
10367 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
10368 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
a3348722 BW |
10369 | if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) |
10370 | bnx2x_after_function_update(bp); | |
8304859a AE |
10371 | /* |
10372 | * in case of fan failure we need to reset id if the "stop on error" | |
10373 | * debug flag is set, since we trying to prevent permanent overheating | |
10374 | * damage | |
10375 | */ | |
10376 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { | |
51c1a580 | 10377 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
8304859a AE |
10378 | netif_device_detach(bp->dev); |
10379 | bnx2x_close(bp->dev); | |
8395be5e AE |
10380 | rtnl_unlock(); |
10381 | return; | |
8304859a AE |
10382 | } |
10383 | ||
381ac16b AE |
10384 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { |
10385 | DP(BNX2X_MSG_SP, | |
10386 | "sending set mcast vf pf channel message from rtnl sp-task\n"); | |
10387 | bnx2x_vfpf_set_mcast(bp->dev); | |
10388 | } | |
78c3bcc5 AE |
10389 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, |
10390 | &bp->sp_rtnl_state)){ | |
3fdd34c1 | 10391 | if (netif_carrier_ok(bp->dev)) { |
78c3bcc5 AE |
10392 | bnx2x_tx_disable(bp); |
10393 | BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n"); | |
10394 | } | |
10395 | } | |
381ac16b | 10396 | |
8b09be5f YM |
10397 | if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { |
10398 | DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n"); | |
10399 | bnx2x_set_rx_mode_inner(bp); | |
381ac16b AE |
10400 | } |
10401 | ||
3ec9f9ca AE |
10402 | if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, |
10403 | &bp->sp_rtnl_state)) | |
10404 | bnx2x_pf_set_vfs_vlan(bp); | |
10405 | ||
6ffa39f2 | 10406 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) { |
07b4eb3b | 10407 | bnx2x_dcbx_stop_hw_tx(bp); |
07b4eb3b | 10408 | bnx2x_dcbx_resume_hw_tx(bp); |
6ffa39f2 | 10409 | } |
07b4eb3b | 10410 | |
42f8277f YM |
10411 | if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION, |
10412 | &bp->sp_rtnl_state)) | |
10413 | bnx2x_update_mng_version(bp); | |
10414 | ||
ebbdb4b5 SRK |
10415 | if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state)) |
10416 | bnx2x_handle_update_svid_cmd(bp); | |
10417 | ||
883ce97d | 10418 | if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT, |
f34fa14c | 10419 | &bp->sp_rtnl_state)) { |
883ce97d YM |
10420 | if (bnx2x_udp_port_update(bp)) { |
10421 | /* On error, forget configuration */ | |
10422 | memset(bp->udp_tunnel_ports, 0, | |
10423 | sizeof(struct bnx2x_udp_tunnel) * | |
10424 | BNX2X_UDP_PORT_MAX); | |
10425 | } else { | |
10426 | /* Since we don't store additional port information, | |
6b352912 | 10427 | * if no ports are configured for any feature ask for |
883ce97d YM |
10428 | * information about currently configured ports. |
10429 | */ | |
6b352912 AD |
10430 | if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count && |
10431 | !bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) | |
10432 | udp_tunnel_get_rx_info(bp->dev); | |
f34fa14c RB |
10433 | } |
10434 | } | |
f34fa14c | 10435 | |
8395be5e AE |
10436 | /* work which needs rtnl lock not-taken (as it takes the lock itself and |
10437 | * can be called from other contexts as well) | |
10438 | */ | |
34f80b04 | 10439 | rtnl_unlock(); |
8395be5e | 10440 | |
6411280a | 10441 | /* enable SR-IOV if applicable */ |
8395be5e | 10442 | if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, |
3c76feff AE |
10443 | &bp->sp_rtnl_state)) { |
10444 | bnx2x_disable_sriov(bp); | |
6411280a | 10445 | bnx2x_enable_sriov(bp); |
3c76feff | 10446 | } |
34f80b04 EG |
10447 | } |
10448 | ||
3deb8167 YR |
10449 | static void bnx2x_period_task(struct work_struct *work) |
10450 | { | |
10451 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
10452 | ||
10453 | if (!netif_running(bp->dev)) | |
10454 | goto period_task_exit; | |
10455 | ||
10456 | if (CHIP_REV_IS_SLOW(bp)) { | |
10457 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
10458 | goto period_task_exit; | |
10459 | } | |
10460 | ||
10461 | bnx2x_acquire_phy_lock(bp); | |
10462 | /* | |
10463 | * The barrier is needed to ensure the ordering between the writing to | |
10464 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
10465 | * the reading here. | |
10466 | */ | |
10467 | smp_mb(); | |
10468 | if (bp->port.pmf) { | |
10469 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
10470 | ||
10471 | /* Re-queue task in 1 sec */ | |
10472 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
10473 | } | |
10474 | ||
10475 | bnx2x_release_phy_lock(bp); | |
10476 | period_task_exit: | |
10477 | return; | |
10478 | } | |
10479 | ||
a2fbb9ea ET |
10480 | /* |
10481 | * Init service functions | |
10482 | */ | |
10483 | ||
a8f47eb7 | 10484 | static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
10485 | { |
10486 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
10487 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
10488 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
10489 | } |
10490 | ||
3d6b7253 YM |
10491 | static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp, |
10492 | u8 port, u32 reset_reg, | |
10493 | struct bnx2x_mac_vals *vals) | |
10494 | { | |
10495 | u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; | |
10496 | u32 base_addr; | |
10497 | ||
10498 | if (!(mask & reset_reg)) | |
10499 | return false; | |
10500 | ||
10501 | BNX2X_DEV_INFO("Disable umac Rx %02x\n", port); | |
10502 | base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
10503 | vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG; | |
10504 | vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]); | |
10505 | REG_WR(bp, vals->umac_addr[port], 0); | |
10506 | ||
10507 | return true; | |
10508 | } | |
10509 | ||
1ef1d45a BW |
10510 | static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, |
10511 | struct bnx2x_mac_vals *vals) | |
34f80b04 | 10512 | { |
452427b0 YM |
10513 | u32 val, base_addr, offset, mask, reset_reg; |
10514 | bool mac_stopped = false; | |
10515 | u8 port = BP_PORT(bp); | |
34f80b04 | 10516 | |
1ef1d45a | 10517 | /* reset addresses as they also mark which values were changed */ |
3d6b7253 | 10518 | memset(vals, 0, sizeof(*vals)); |
1ef1d45a | 10519 | |
452427b0 | 10520 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
f16da43b | 10521 | |
452427b0 YM |
10522 | if (!CHIP_IS_E3(bp)) { |
10523 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
10524 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; | |
10525 | if ((mask & reset_reg) && val) { | |
10526 | u32 wb_data[2]; | |
10527 | BNX2X_DEV_INFO("Disable bmac Rx\n"); | |
10528 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM | |
10529 | : NIG_REG_INGRESS_BMAC0_MEM; | |
10530 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL | |
10531 | : BIGMAC_REGISTER_BMAC_CONTROL; | |
7a06a122 | 10532 | |
452427b0 YM |
10533 | /* |
10534 | * use rd/wr since we cannot use dmae. This is safe | |
10535 | * since MCP won't access the bus due to the request | |
10536 | * to unload, and no function on the path can be | |
10537 | * loaded at this time. | |
10538 | */ | |
10539 | wb_data[0] = REG_RD(bp, base_addr + offset); | |
10540 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); | |
1ef1d45a BW |
10541 | vals->bmac_addr = base_addr + offset; |
10542 | vals->bmac_val[0] = wb_data[0]; | |
10543 | vals->bmac_val[1] = wb_data[1]; | |
452427b0 | 10544 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
1ef1d45a BW |
10545 | REG_WR(bp, vals->bmac_addr, wb_data[0]); |
10546 | REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); | |
452427b0 YM |
10547 | } |
10548 | BNX2X_DEV_INFO("Disable emac Rx\n"); | |
1ef1d45a BW |
10549 | vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; |
10550 | vals->emac_val = REG_RD(bp, vals->emac_addr); | |
10551 | REG_WR(bp, vals->emac_addr, 0); | |
452427b0 YM |
10552 | mac_stopped = true; |
10553 | } else { | |
10554 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
10555 | BNX2X_DEV_INFO("Disable xmac Rx\n"); | |
10556 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
10557 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); | |
10558 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
10559 | val & ~(1 << 1)); | |
10560 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
10561 | val | (1 << 1)); | |
1ef1d45a BW |
10562 | vals->xmac_addr = base_addr + XMAC_REG_CTRL; |
10563 | vals->xmac_val = REG_RD(bp, vals->xmac_addr); | |
10564 | REG_WR(bp, vals->xmac_addr, 0); | |
452427b0 YM |
10565 | mac_stopped = true; |
10566 | } | |
3d6b7253 YM |
10567 | |
10568 | mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0, | |
10569 | reset_reg, vals); | |
10570 | mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1, | |
10571 | reset_reg, vals); | |
452427b0 YM |
10572 | } |
10573 | ||
10574 | if (mac_stopped) | |
10575 | msleep(20); | |
452427b0 YM |
10576 | } |
10577 | ||
10578 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) | |
7c3afd85 YM |
10579 | #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \ |
10580 | 0x1848 + ((f) << 4)) | |
452427b0 YM |
10581 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) |
10582 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) | |
10583 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) | |
10584 | ||
91ebb929 YM |
10585 | #define BCM_5710_UNDI_FW_MF_MAJOR (0x07) |
10586 | #define BCM_5710_UNDI_FW_MF_MINOR (0x08) | |
10587 | #define BCM_5710_UNDI_FW_MF_VERS (0x05) | |
b17b0ca1 YM |
10588 | |
10589 | static bool bnx2x_prev_is_after_undi(struct bnx2x *bp) | |
10590 | { | |
10591 | /* UNDI marks its presence in DORQ - | |
10592 | * it initializes CID offset for normal bell to 0x7 | |
10593 | */ | |
10594 | if (!(REG_RD(bp, MISC_REG_RESET_REG_1) & | |
10595 | MISC_REGISTERS_RESET_REG_1_RST_DORQ)) | |
10596 | return false; | |
10597 | ||
10598 | if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) { | |
10599 | BNX2X_DEV_INFO("UNDI previously loaded\n"); | |
10600 | return true; | |
10601 | } | |
10602 | ||
10603 | return false; | |
10604 | } | |
10605 | ||
7c3afd85 | 10606 | static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc) |
452427b0 YM |
10607 | { |
10608 | u16 rcq, bd; | |
7c3afd85 | 10609 | u32 addr, tmp_reg; |
452427b0 | 10610 | |
7c3afd85 YM |
10611 | if (BP_FUNC(bp) < 2) |
10612 | addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp)); | |
10613 | else | |
10614 | addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2); | |
10615 | ||
10616 | tmp_reg = REG_RD(bp, addr); | |
452427b0 YM |
10617 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; |
10618 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; | |
10619 | ||
10620 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); | |
7c3afd85 | 10621 | REG_WR(bp, addr, tmp_reg); |
452427b0 | 10622 | |
7c3afd85 YM |
10623 | BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n", |
10624 | BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq); | |
452427b0 YM |
10625 | } |
10626 | ||
0329aba1 | 10627 | static int bnx2x_prev_mcp_done(struct bnx2x *bp) |
452427b0 | 10628 | { |
5d07d868 YM |
10629 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, |
10630 | DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); | |
452427b0 YM |
10631 | if (!rc) { |
10632 | BNX2X_ERR("MCP response failure, aborting\n"); | |
10633 | return -EBUSY; | |
10634 | } | |
10635 | ||
10636 | return 0; | |
10637 | } | |
10638 | ||
c63da990 BW |
10639 | static struct bnx2x_prev_path_list * |
10640 | bnx2x_prev_path_get_entry(struct bnx2x *bp) | |
10641 | { | |
10642 | struct bnx2x_prev_path_list *tmp_list; | |
10643 | ||
10644 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) | |
10645 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
10646 | bp->pdev->bus->number == tmp_list->bus && | |
10647 | BP_PATH(bp) == tmp_list->path) | |
10648 | return tmp_list; | |
10649 | ||
10650 | return NULL; | |
10651 | } | |
10652 | ||
7fa6f340 YM |
10653 | static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) |
10654 | { | |
10655 | struct bnx2x_prev_path_list *tmp_list; | |
10656 | int rc; | |
10657 | ||
10658 | rc = down_interruptible(&bnx2x_prev_sem); | |
10659 | if (rc) { | |
10660 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
10661 | return rc; | |
10662 | } | |
10663 | ||
10664 | tmp_list = bnx2x_prev_path_get_entry(bp); | |
10665 | if (tmp_list) { | |
10666 | tmp_list->aer = 1; | |
10667 | rc = 0; | |
10668 | } else { | |
10669 | BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n", | |
10670 | BP_PATH(bp)); | |
10671 | } | |
10672 | ||
10673 | up(&bnx2x_prev_sem); | |
10674 | ||
10675 | return rc; | |
10676 | } | |
10677 | ||
0329aba1 | 10678 | static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) |
452427b0 YM |
10679 | { |
10680 | struct bnx2x_prev_path_list *tmp_list; | |
b85d717c | 10681 | bool rc = false; |
452427b0 YM |
10682 | |
10683 | if (down_trylock(&bnx2x_prev_sem)) | |
10684 | return false; | |
10685 | ||
7fa6f340 YM |
10686 | tmp_list = bnx2x_prev_path_get_entry(bp); |
10687 | if (tmp_list) { | |
10688 | if (tmp_list->aer) { | |
10689 | DP(NETIF_MSG_HW, "Path %d was marked by AER\n", | |
10690 | BP_PATH(bp)); | |
10691 | } else { | |
452427b0 YM |
10692 | rc = true; |
10693 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | |
10694 | BP_PATH(bp)); | |
452427b0 YM |
10695 | } |
10696 | } | |
10697 | ||
10698 | up(&bnx2x_prev_sem); | |
10699 | ||
10700 | return rc; | |
10701 | } | |
10702 | ||
178135c1 DK |
10703 | bool bnx2x_port_after_undi(struct bnx2x *bp) |
10704 | { | |
10705 | struct bnx2x_prev_path_list *entry; | |
10706 | bool val; | |
10707 | ||
10708 | down(&bnx2x_prev_sem); | |
10709 | ||
10710 | entry = bnx2x_prev_path_get_entry(bp); | |
10711 | val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); | |
10712 | ||
10713 | up(&bnx2x_prev_sem); | |
10714 | ||
10715 | return val; | |
10716 | } | |
10717 | ||
c63da990 | 10718 | static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) |
452427b0 YM |
10719 | { |
10720 | struct bnx2x_prev_path_list *tmp_list; | |
10721 | int rc; | |
10722 | ||
7fa6f340 YM |
10723 | rc = down_interruptible(&bnx2x_prev_sem); |
10724 | if (rc) { | |
10725 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
10726 | return rc; | |
10727 | } | |
10728 | ||
10729 | /* Check whether the entry for this path already exists */ | |
10730 | tmp_list = bnx2x_prev_path_get_entry(bp); | |
10731 | if (tmp_list) { | |
10732 | if (!tmp_list->aer) { | |
10733 | BNX2X_ERR("Re-Marking the path.\n"); | |
10734 | } else { | |
10735 | DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", | |
10736 | BP_PATH(bp)); | |
10737 | tmp_list->aer = 0; | |
10738 | } | |
10739 | up(&bnx2x_prev_sem); | |
10740 | return 0; | |
10741 | } | |
10742 | up(&bnx2x_prev_sem); | |
10743 | ||
10744 | /* Create an entry for this path and add it */ | |
ea4b3857 | 10745 | tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); |
452427b0 YM |
10746 | if (!tmp_list) { |
10747 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | |
10748 | return -ENOMEM; | |
10749 | } | |
10750 | ||
10751 | tmp_list->bus = bp->pdev->bus->number; | |
10752 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | |
10753 | tmp_list->path = BP_PATH(bp); | |
7fa6f340 | 10754 | tmp_list->aer = 0; |
c63da990 | 10755 | tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; |
452427b0 YM |
10756 | |
10757 | rc = down_interruptible(&bnx2x_prev_sem); | |
10758 | if (rc) { | |
10759 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
10760 | kfree(tmp_list); | |
10761 | } else { | |
7fa6f340 YM |
10762 | DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", |
10763 | BP_PATH(bp)); | |
452427b0 YM |
10764 | list_add(&tmp_list->list, &bnx2x_prev_list); |
10765 | up(&bnx2x_prev_sem); | |
10766 | } | |
10767 | ||
10768 | return rc; | |
10769 | } | |
10770 | ||
0329aba1 | 10771 | static int bnx2x_do_flr(struct bnx2x *bp) |
452427b0 | 10772 | { |
452427b0 YM |
10773 | struct pci_dev *dev = bp->pdev; |
10774 | ||
8eee694c YM |
10775 | if (CHIP_IS_E1x(bp)) { |
10776 | BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); | |
10777 | return -EINVAL; | |
10778 | } | |
10779 | ||
10780 | /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ | |
10781 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | |
10782 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | |
10783 | bp->common.bc_ver); | |
10784 | return -EINVAL; | |
10785 | } | |
452427b0 | 10786 | |
8903b9eb CL |
10787 | if (!pci_wait_for_pending_transaction(dev)) |
10788 | dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); | |
452427b0 | 10789 | |
8eee694c | 10790 | BNX2X_DEV_INFO("Initiating FLR\n"); |
452427b0 YM |
10791 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); |
10792 | ||
10793 | return 0; | |
10794 | } | |
10795 | ||
0329aba1 | 10796 | static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) |
452427b0 YM |
10797 | { |
10798 | int rc; | |
10799 | ||
10800 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); | |
10801 | ||
10802 | /* Test if previous unload process was already finished for this path */ | |
10803 | if (bnx2x_prev_is_path_marked(bp)) | |
10804 | return bnx2x_prev_mcp_done(bp); | |
10805 | ||
04c46736 YM |
10806 | BNX2X_DEV_INFO("Path is unmarked\n"); |
10807 | ||
b17b0ca1 YM |
10808 | /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */ |
10809 | if (bnx2x_prev_is_after_undi(bp)) | |
10810 | goto out; | |
10811 | ||
452427b0 YM |
10812 | /* If function has FLR capabilities, and existing FW version matches |
10813 | * the one required, then FLR will be sufficient to clean any residue | |
10814 | * left by previous driver | |
10815 | */ | |
91ebb929 | 10816 | rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false); |
8eee694c YM |
10817 | |
10818 | if (!rc) { | |
10819 | /* fw version is good */ | |
10820 | BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); | |
10821 | rc = bnx2x_do_flr(bp); | |
10822 | } | |
10823 | ||
10824 | if (!rc) { | |
10825 | /* FLR was performed */ | |
10826 | BNX2X_DEV_INFO("FLR successful\n"); | |
10827 | return 0; | |
10828 | } | |
10829 | ||
10830 | BNX2X_DEV_INFO("Could not FLR\n"); | |
452427b0 | 10831 | |
b17b0ca1 | 10832 | out: |
452427b0 YM |
10833 | /* Close the MCP request, return failure*/ |
10834 | rc = bnx2x_prev_mcp_done(bp); | |
10835 | if (!rc) | |
10836 | rc = BNX2X_PREV_WAIT_NEEDED; | |
10837 | ||
10838 | return rc; | |
10839 | } | |
10840 | ||
0329aba1 | 10841 | static int bnx2x_prev_unload_common(struct bnx2x *bp) |
452427b0 YM |
10842 | { |
10843 | u32 reset_reg, tmp_reg = 0, rc; | |
c63da990 | 10844 | bool prev_undi = false; |
1ef1d45a BW |
10845 | struct bnx2x_mac_vals mac_vals; |
10846 | ||
452427b0 YM |
10847 | /* It is possible a previous function received 'common' answer, |
10848 | * but hasn't loaded yet, therefore creating a scenario of | |
10849 | * multiple functions receiving 'common' on the same path. | |
10850 | */ | |
10851 | BNX2X_DEV_INFO("Common unload Flow\n"); | |
10852 | ||
1ef1d45a BW |
10853 | memset(&mac_vals, 0, sizeof(mac_vals)); |
10854 | ||
452427b0 YM |
10855 | if (bnx2x_prev_is_path_marked(bp)) |
10856 | return bnx2x_prev_mcp_done(bp); | |
10857 | ||
10858 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); | |
10859 | ||
10860 | /* Reset should be performed after BRB is emptied */ | |
10861 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { | |
10862 | u32 timer_count = 1000; | |
452427b0 YM |
10863 | |
10864 | /* Close the MAC Rx to prevent BRB from filling up */ | |
1ef1d45a BW |
10865 | bnx2x_prev_unload_close_mac(bp, &mac_vals); |
10866 | ||
3d6b7253 | 10867 | /* close LLH filters for both ports towards the BRB */ |
1ef1d45a | 10868 | bnx2x_set_rx_filter(&bp->link_params, 0); |
3d6b7253 | 10869 | bp->link_params.port ^= 1; |
1ef1d45a | 10870 | bnx2x_set_rx_filter(&bp->link_params, 0); |
3d6b7253 | 10871 | bp->link_params.port ^= 1; |
452427b0 | 10872 | |
b17b0ca1 YM |
10873 | /* Check if the UNDI driver was previously loaded */ |
10874 | if (bnx2x_prev_is_after_undi(bp)) { | |
10875 | prev_undi = true; | |
10876 | /* clear the UNDI indication */ | |
10877 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
10878 | /* clear possible idle check errors */ | |
10879 | REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); | |
452427b0 | 10880 | } |
d46f7c4d DK |
10881 | if (!CHIP_IS_E1x(bp)) |
10882 | /* block FW from writing to host */ | |
10883 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
10884 | ||
452427b0 YM |
10885 | /* wait until BRB is empty */ |
10886 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); | |
10887 | while (timer_count) { | |
10888 | u32 prev_brb = tmp_reg; | |
34f80b04 | 10889 | |
452427b0 YM |
10890 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
10891 | if (!tmp_reg) | |
10892 | break; | |
619c5cb6 | 10893 | |
452427b0 | 10894 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
619c5cb6 | 10895 | |
452427b0 YM |
10896 | /* reset timer as long as BRB actually gets emptied */ |
10897 | if (prev_brb > tmp_reg) | |
10898 | timer_count = 1000; | |
10899 | else | |
10900 | timer_count--; | |
da5a662a | 10901 | |
7c3afd85 YM |
10902 | /* If UNDI resides in memory, manually increment it */ |
10903 | if (prev_undi) | |
10904 | bnx2x_prev_unload_undi_inc(bp, 1); | |
10905 | ||
452427b0 | 10906 | udelay(10); |
7a06a122 | 10907 | } |
452427b0 YM |
10908 | |
10909 | if (!timer_count) | |
10910 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); | |
34f80b04 | 10911 | } |
f16da43b | 10912 | |
452427b0 YM |
10913 | /* No packets are in the pipeline, path is ready for reset */ |
10914 | bnx2x_reset_common(bp); | |
10915 | ||
1ef1d45a BW |
10916 | if (mac_vals.xmac_addr) |
10917 | REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); | |
3d6b7253 YM |
10918 | if (mac_vals.umac_addr[0]) |
10919 | REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); | |
10920 | if (mac_vals.umac_addr[1]) | |
10921 | REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); | |
1ef1d45a BW |
10922 | if (mac_vals.emac_addr) |
10923 | REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); | |
10924 | if (mac_vals.bmac_addr) { | |
10925 | REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); | |
10926 | REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); | |
10927 | } | |
10928 | ||
c63da990 | 10929 | rc = bnx2x_prev_mark_path(bp, prev_undi); |
452427b0 YM |
10930 | if (rc) { |
10931 | bnx2x_prev_mcp_done(bp); | |
10932 | return rc; | |
10933 | } | |
10934 | ||
10935 | return bnx2x_prev_mcp_done(bp); | |
10936 | } | |
10937 | ||
0329aba1 | 10938 | static int bnx2x_prev_unload(struct bnx2x *bp) |
452427b0 YM |
10939 | { |
10940 | int time_counter = 10; | |
10941 | u32 rc, fw, hw_lock_reg, hw_lock_val; | |
10942 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); | |
10943 | ||
24f06716 AE |
10944 | /* clear hw from errors which may have resulted from an interrupted |
10945 | * dmae transaction. | |
10946 | */ | |
da254fbc | 10947 | bnx2x_clean_pglue_errors(bp); |
24f06716 AE |
10948 | |
10949 | /* Release previously held locks */ | |
452427b0 YM |
10950 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? |
10951 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : | |
10952 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); | |
10953 | ||
3cdeec22 | 10954 | hw_lock_val = REG_RD(bp, hw_lock_reg); |
452427b0 YM |
10955 | if (hw_lock_val) { |
10956 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { | |
10957 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); | |
10958 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
10959 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); | |
10960 | } | |
10961 | ||
10962 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); | |
10963 | REG_WR(bp, hw_lock_reg, 0xffffffff); | |
10964 | } else | |
10965 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); | |
10966 | ||
10967 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { | |
10968 | BNX2X_DEV_INFO("Release previously held alr\n"); | |
3cdeec22 | 10969 | bnx2x_release_alr(bp); |
452427b0 YM |
10970 | } |
10971 | ||
452427b0 | 10972 | do { |
7fa6f340 | 10973 | int aer = 0; |
452427b0 YM |
10974 | /* Lock MCP using an unload request */ |
10975 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | |
10976 | if (!fw) { | |
10977 | BNX2X_ERR("MCP response failure, aborting\n"); | |
10978 | rc = -EBUSY; | |
10979 | break; | |
10980 | } | |
10981 | ||
7fa6f340 YM |
10982 | rc = down_interruptible(&bnx2x_prev_sem); |
10983 | if (rc) { | |
10984 | BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n", | |
10985 | rc); | |
10986 | } else { | |
10987 | /* If Path is marked by EEH, ignore unload status */ | |
10988 | aer = !!(bnx2x_prev_path_get_entry(bp) && | |
10989 | bnx2x_prev_path_get_entry(bp)->aer); | |
60cde81f | 10990 | up(&bnx2x_prev_sem); |
7fa6f340 | 10991 | } |
7fa6f340 YM |
10992 | |
10993 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) { | |
452427b0 YM |
10994 | rc = bnx2x_prev_unload_common(bp); |
10995 | break; | |
10996 | } | |
10997 | ||
16a5fd92 | 10998 | /* non-common reply from MCP might require looping */ |
452427b0 YM |
10999 | rc = bnx2x_prev_unload_uncommon(bp); |
11000 | if (rc != BNX2X_PREV_WAIT_NEEDED) | |
11001 | break; | |
11002 | ||
11003 | msleep(20); | |
11004 | } while (--time_counter); | |
11005 | ||
11006 | if (!time_counter || rc) { | |
91ebb929 YM |
11007 | BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n"); |
11008 | rc = -EPROBE_DEFER; | |
452427b0 YM |
11009 | } |
11010 | ||
c63da990 | 11011 | /* Mark function if its port was used to boot from SAN */ |
178135c1 | 11012 | if (bnx2x_port_after_undi(bp)) |
c63da990 BW |
11013 | bp->link_params.feature_config_flags |= |
11014 | FEATURE_CONFIG_BOOT_FROM_SAN; | |
11015 | ||
452427b0 YM |
11016 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); |
11017 | ||
11018 | return rc; | |
34f80b04 EG |
11019 | } |
11020 | ||
0329aba1 | 11021 | static void bnx2x_get_common_hwinfo(struct bnx2x *bp) |
34f80b04 | 11022 | { |
1d187b34 | 11023 | u32 val, val2, val3, val4, id, boot_mode; |
72ce58c3 | 11024 | u16 pmc; |
34f80b04 EG |
11025 | |
11026 | /* Get the chip revision id and number. */ | |
11027 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
11028 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
11029 | id = ((val & 0xffff) << 16); | |
11030 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
11031 | id |= ((val & 0xf) << 12); | |
f22fdf25 YM |
11032 | |
11033 | /* Metal is read from PCI regs, but we can't access >=0x400 from | |
11034 | * the configuration space (so we need to reg_rd) | |
11035 | */ | |
11036 | val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); | |
11037 | id |= (((val >> 24) & 0xf) << 4); | |
5a40e08e | 11038 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
11039 | id |= (val & 0xf); |
11040 | bp->common.chip_id = id; | |
523224a3 | 11041 | |
7e8e02df BW |
11042 | /* force 57811 according to MISC register */ |
11043 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { | |
11044 | if (CHIP_IS_57810(bp)) | |
11045 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | | |
11046 | (bp->common.chip_id & 0x0000FFFF); | |
11047 | else if (CHIP_IS_57810_MF(bp)) | |
11048 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | | |
11049 | (bp->common.chip_id & 0x0000FFFF); | |
11050 | bp->common.chip_id |= 0x1; | |
11051 | } | |
11052 | ||
523224a3 DK |
11053 | /* Set doorbell size */ |
11054 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
11055 | ||
619c5cb6 | 11056 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
11057 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
11058 | if ((val & 1) == 0) | |
11059 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
11060 | else | |
11061 | val = (val >> 1) & 1; | |
11062 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
11063 | "2_PORT_MODE"); | |
11064 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
11065 | CHIP_2_PORT_MODE; | |
11066 | ||
11067 | if (CHIP_MODE_IS_4_PORT(bp)) | |
11068 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
11069 | else | |
11070 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
11071 | } else { | |
11072 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
11073 | bp->pfid = bp->pf_num; /* 0..7 */ | |
11074 | } | |
11075 | ||
51c1a580 MS |
11076 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
11077 | ||
f2e0899f DK |
11078 | bp->link_params.chip_id = bp->common.chip_id; |
11079 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 11080 | |
1c06328c EG |
11081 | val = (REG_RD(bp, 0x2874) & 0x55); |
11082 | if ((bp->common.chip_id & 0x1) || | |
11083 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
11084 | bp->flags |= ONE_PORT_FLAG; | |
11085 | BNX2X_DEV_INFO("single port device\n"); | |
11086 | } | |
11087 | ||
34f80b04 | 11088 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 11089 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
11090 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
11091 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
11092 | bp->common.flash_size, bp->common.flash_size); | |
11093 | ||
1b6e2ceb DK |
11094 | bnx2x_init_shmem(bp); |
11095 | ||
f2e0899f DK |
11096 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
11097 | MISC_REG_GENERIC_CR_1 : | |
11098 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 11099 | |
34f80b04 | 11100 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 11101 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
b884d95b YR |
11102 | if (SHMEM2_RD(bp, size) > |
11103 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
11104 | bp->link_params.lfa_base = | |
11105 | REG_RD(bp, bp->common.shmem2_base + | |
11106 | (u32)offsetof(struct shmem2_region, | |
11107 | lfa_host_addr[BP_PORT(bp)])); | |
11108 | else | |
11109 | bp->link_params.lfa_base = 0; | |
2691d51d EG |
11110 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
11111 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 11112 | |
f2e0899f | 11113 | if (!bp->common.shmem_base) { |
34f80b04 EG |
11114 | BNX2X_DEV_INFO("MCP not active\n"); |
11115 | bp->flags |= NO_MCP_FLAG; | |
11116 | return; | |
11117 | } | |
11118 | ||
34f80b04 | 11119 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 11120 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
11121 | |
11122 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
11123 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
11124 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
11125 | ||
c2c8b03e EG |
11126 | bp->link_params.feature_config_flags = 0; |
11127 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
11128 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
11129 | bp->link_params.feature_config_flags |= | |
11130 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
11131 | else | |
11132 | bp->link_params.feature_config_flags &= | |
11133 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
11134 | ||
34f80b04 EG |
11135 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
11136 | bp->common.bc_ver = val; | |
11137 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
11138 | if (val < BNX2X_BC_VER) { | |
11139 | /* for now only warn | |
11140 | * later we might need to enforce this */ | |
51c1a580 MS |
11141 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
11142 | BNX2X_BC_VER, val); | |
34f80b04 | 11143 | } |
4d295db0 | 11144 | bp->link_params.feature_config_flags |= |
a22f0788 | 11145 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
11146 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
11147 | ||
a22f0788 YR |
11148 | bp->link_params.feature_config_flags |= |
11149 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
11150 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
a3348722 BW |
11151 | bp->link_params.feature_config_flags |= |
11152 | (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? | |
11153 | FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; | |
85242eea YR |
11154 | bp->link_params.feature_config_flags |= |
11155 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
11156 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
55386fe8 YR |
11157 | |
11158 | bp->link_params.feature_config_flags |= | |
11159 | (val >= REQ_BC_VER_4_MT_SUPPORTED) ? | |
11160 | FEATURE_CONFIG_MT_SUPPORT : 0; | |
11161 | ||
0e898dd7 BW |
11162 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
11163 | BC_SUPPORTS_PFC_STATS : 0; | |
85242eea | 11164 | |
2e499d3c BW |
11165 | bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? |
11166 | BC_SUPPORTS_FCOE_FEATURES : 0; | |
11167 | ||
9876879f BW |
11168 | bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? |
11169 | BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; | |
a6d3a5ba BW |
11170 | |
11171 | bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? | |
11172 | BC_SUPPORTS_RMMOD_CMD : 0; | |
11173 | ||
1d187b34 BW |
11174 | boot_mode = SHMEM_RD(bp, |
11175 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & | |
11176 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; | |
11177 | switch (boot_mode) { | |
11178 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: | |
11179 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; | |
11180 | break; | |
11181 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: | |
11182 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; | |
11183 | break; | |
11184 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: | |
11185 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; | |
11186 | break; | |
11187 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: | |
11188 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; | |
11189 | break; | |
11190 | } | |
11191 | ||
29ed74c3 | 11192 | pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc); |
f9a3ebbe DK |
11193 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; |
11194 | ||
72ce58c3 | 11195 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 11196 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
11197 | |
11198 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
11199 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
11200 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
11201 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
11202 | ||
cdaa7cb8 VZ |
11203 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
11204 | val, val2, val3, val4); | |
34f80b04 EG |
11205 | } |
11206 | ||
f2e0899f DK |
11207 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
11208 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
11209 | ||
0329aba1 | 11210 | static int bnx2x_get_igu_cam_info(struct bnx2x *bp) |
f2e0899f DK |
11211 | { |
11212 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
11213 | int igu_sb_id; |
11214 | u32 val; | |
6383c0b3 | 11215 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
11216 | |
11217 | bp->igu_base_sb = 0xff; | |
f2e0899f | 11218 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 11219 | int vn = BP_VN(bp); |
6383c0b3 | 11220 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
11221 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
11222 | FP_SB_MAX_E1x; | |
11223 | ||
11224 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
11225 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
11226 | ||
9b341bb1 | 11227 | return 0; |
f2e0899f DK |
11228 | } |
11229 | ||
11230 | /* IGU in normal mode - read CAM */ | |
11231 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
11232 | igu_sb_id++) { | |
11233 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
11234 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
11235 | continue; | |
11236 | fid = IGU_FID(val); | |
11237 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
11238 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
11239 | continue; | |
11240 | if (IGU_VEC(val) == 0) | |
11241 | /* default status block */ | |
11242 | bp->igu_dsb_id = igu_sb_id; | |
11243 | else { | |
11244 | if (bp->igu_base_sb == 0xff) | |
11245 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 11246 | igu_sb_cnt++; |
f2e0899f DK |
11247 | } |
11248 | } | |
11249 | } | |
619c5cb6 | 11250 | |
6383c0b3 | 11251 | #ifdef CONFIG_PCI_MSI |
185d4c8b AE |
11252 | /* Due to new PF resource allocation by MFW T7.4 and above, it's |
11253 | * optional that number of CAM entries will not be equal to the value | |
11254 | * advertised in PCI. | |
11255 | * Driver should use the minimal value of both as the actual status | |
11256 | * block count | |
619c5cb6 | 11257 | */ |
185d4c8b | 11258 | bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); |
6383c0b3 | 11259 | #endif |
619c5cb6 | 11260 | |
9b341bb1 | 11261 | if (igu_sb_cnt == 0) { |
f2e0899f | 11262 | BNX2X_ERR("CAM configuration error\n"); |
9b341bb1 BW |
11263 | return -EINVAL; |
11264 | } | |
11265 | ||
11266 | return 0; | |
f2e0899f DK |
11267 | } |
11268 | ||
1dd06ae8 | 11269 | static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) |
a2fbb9ea | 11270 | { |
a22f0788 YR |
11271 | int cfg_size = 0, idx, port = BP_PORT(bp); |
11272 | ||
11273 | /* Aggregation of supported attributes of all external phys */ | |
11274 | bp->port.supported[0] = 0; | |
11275 | bp->port.supported[1] = 0; | |
b7737c9b YR |
11276 | switch (bp->link_params.num_phys) { |
11277 | case 1: | |
a22f0788 YR |
11278 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
11279 | cfg_size = 1; | |
11280 | break; | |
b7737c9b | 11281 | case 2: |
a22f0788 YR |
11282 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
11283 | cfg_size = 1; | |
11284 | break; | |
11285 | case 3: | |
11286 | if (bp->link_params.multi_phy_config & | |
11287 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
11288 | bp->port.supported[1] = | |
11289 | bp->link_params.phy[EXT_PHY1].supported; | |
11290 | bp->port.supported[0] = | |
11291 | bp->link_params.phy[EXT_PHY2].supported; | |
11292 | } else { | |
11293 | bp->port.supported[0] = | |
11294 | bp->link_params.phy[EXT_PHY1].supported; | |
11295 | bp->port.supported[1] = | |
11296 | bp->link_params.phy[EXT_PHY2].supported; | |
11297 | } | |
11298 | cfg_size = 2; | |
11299 | break; | |
b7737c9b | 11300 | } |
a2fbb9ea | 11301 | |
a22f0788 | 11302 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
51c1a580 | 11303 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 11304 | SHMEM_RD(bp, |
a22f0788 YR |
11305 | dev_info.port_hw_config[port].external_phy_config), |
11306 | SHMEM_RD(bp, | |
11307 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 11308 | return; |
f85582f8 | 11309 | } |
a2fbb9ea | 11310 | |
619c5cb6 VZ |
11311 | if (CHIP_IS_E3(bp)) |
11312 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
11313 | else { | |
11314 | switch (switch_cfg) { | |
11315 | case SWITCH_CFG_1G: | |
11316 | bp->port.phy_addr = REG_RD( | |
11317 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
11318 | break; | |
11319 | case SWITCH_CFG_10G: | |
11320 | bp->port.phy_addr = REG_RD( | |
11321 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
11322 | break; | |
11323 | default: | |
11324 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
11325 | bp->port.link_config[0]); | |
11326 | return; | |
11327 | } | |
a2fbb9ea | 11328 | } |
619c5cb6 | 11329 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
11330 | /* mask what we support according to speed_cap_mask per configuration */ |
11331 | for (idx = 0; idx < cfg_size; idx++) { | |
11332 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 11333 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 11334 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 11335 | |
a22f0788 | 11336 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11337 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 11338 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 11339 | |
a22f0788 | 11340 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11341 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 11342 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 11343 | |
a22f0788 | 11344 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11345 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 11346 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 11347 | |
a22f0788 | 11348 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11349 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 11350 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 11351 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 11352 | |
a22f0788 | 11353 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11354 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 11355 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 11356 | |
a22f0788 | 11357 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11358 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 | 11359 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
b8e0d884 YR |
11360 | |
11361 | if (!(bp->link_params.speed_cap_mask[idx] & | |
11362 | PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) | |
11363 | bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; | |
a22f0788 | 11364 | } |
a2fbb9ea | 11365 | |
a22f0788 YR |
11366 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
11367 | bp->port.supported[1]); | |
a2fbb9ea ET |
11368 | } |
11369 | ||
0329aba1 | 11370 | static void bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 11371 | { |
a22f0788 YR |
11372 | u32 link_config, idx, cfg_size = 0; |
11373 | bp->port.advertising[0] = 0; | |
11374 | bp->port.advertising[1] = 0; | |
11375 | switch (bp->link_params.num_phys) { | |
11376 | case 1: | |
11377 | case 2: | |
11378 | cfg_size = 1; | |
11379 | break; | |
11380 | case 3: | |
11381 | cfg_size = 2; | |
11382 | break; | |
11383 | } | |
11384 | for (idx = 0; idx < cfg_size; idx++) { | |
11385 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
11386 | link_config = bp->port.link_config[idx]; | |
11387 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 11388 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
11389 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
11390 | bp->link_params.req_line_speed[idx] = | |
11391 | SPEED_AUTO_NEG; | |
11392 | bp->port.advertising[idx] |= | |
11393 | bp->port.supported[idx]; | |
10bd1f24 MY |
11394 | if (bp->link_params.phy[EXT_PHY1].type == |
11395 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
11396 | bp->port.advertising[idx] |= | |
11397 | (SUPPORTED_100baseT_Half | | |
11398 | SUPPORTED_100baseT_Full); | |
f85582f8 DK |
11399 | } else { |
11400 | /* force 10G, no AN */ | |
a22f0788 YR |
11401 | bp->link_params.req_line_speed[idx] = |
11402 | SPEED_10000; | |
11403 | bp->port.advertising[idx] |= | |
11404 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 11405 | ADVERTISED_FIBRE); |
a22f0788 | 11406 | continue; |
f85582f8 DK |
11407 | } |
11408 | break; | |
a2fbb9ea | 11409 | |
f85582f8 | 11410 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
11411 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
11412 | bp->link_params.req_line_speed[idx] = | |
11413 | SPEED_10; | |
11414 | bp->port.advertising[idx] |= | |
11415 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
11416 | ADVERTISED_TP); |
11417 | } else { | |
51c1a580 | 11418 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 | 11419 | link_config, |
a22f0788 | 11420 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
11421 | return; |
11422 | } | |
11423 | break; | |
a2fbb9ea | 11424 | |
f85582f8 | 11425 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
11426 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
11427 | bp->link_params.req_line_speed[idx] = | |
11428 | SPEED_10; | |
11429 | bp->link_params.req_duplex[idx] = | |
11430 | DUPLEX_HALF; | |
11431 | bp->port.advertising[idx] |= | |
11432 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
11433 | ADVERTISED_TP); |
11434 | } else { | |
51c1a580 | 11435 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
11436 | link_config, |
11437 | bp->link_params.speed_cap_mask[idx]); | |
11438 | return; | |
11439 | } | |
11440 | break; | |
a2fbb9ea | 11441 | |
f85582f8 DK |
11442 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
11443 | if (bp->port.supported[idx] & | |
11444 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
11445 | bp->link_params.req_line_speed[idx] = |
11446 | SPEED_100; | |
11447 | bp->port.advertising[idx] |= | |
11448 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
11449 | ADVERTISED_TP); |
11450 | } else { | |
51c1a580 | 11451 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
11452 | link_config, |
11453 | bp->link_params.speed_cap_mask[idx]); | |
11454 | return; | |
11455 | } | |
11456 | break; | |
a2fbb9ea | 11457 | |
f85582f8 DK |
11458 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
11459 | if (bp->port.supported[idx] & | |
11460 | SUPPORTED_100baseT_Half) { | |
11461 | bp->link_params.req_line_speed[idx] = | |
11462 | SPEED_100; | |
11463 | bp->link_params.req_duplex[idx] = | |
11464 | DUPLEX_HALF; | |
a22f0788 YR |
11465 | bp->port.advertising[idx] |= |
11466 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
11467 | ADVERTISED_TP); |
11468 | } else { | |
51c1a580 | 11469 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
11470 | link_config, |
11471 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
11472 | return; |
11473 | } | |
11474 | break; | |
a2fbb9ea | 11475 | |
f85582f8 | 11476 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
11477 | if (bp->port.supported[idx] & |
11478 | SUPPORTED_1000baseT_Full) { | |
11479 | bp->link_params.req_line_speed[idx] = | |
11480 | SPEED_1000; | |
11481 | bp->port.advertising[idx] |= | |
11482 | (ADVERTISED_1000baseT_Full | | |
f85582f8 | 11483 | ADVERTISED_TP); |
5d67c1c5 YM |
11484 | } else if (bp->port.supported[idx] & |
11485 | SUPPORTED_1000baseKX_Full) { | |
11486 | bp->link_params.req_line_speed[idx] = | |
11487 | SPEED_1000; | |
11488 | bp->port.advertising[idx] |= | |
11489 | ADVERTISED_1000baseKX_Full; | |
f85582f8 | 11490 | } else { |
51c1a580 | 11491 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
11492 | link_config, |
11493 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
11494 | return; |
11495 | } | |
11496 | break; | |
a2fbb9ea | 11497 | |
f85582f8 | 11498 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
11499 | if (bp->port.supported[idx] & |
11500 | SUPPORTED_2500baseX_Full) { | |
11501 | bp->link_params.req_line_speed[idx] = | |
11502 | SPEED_2500; | |
11503 | bp->port.advertising[idx] |= | |
11504 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 11505 | ADVERTISED_TP); |
f85582f8 | 11506 | } else { |
51c1a580 | 11507 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 11508 | link_config, |
f85582f8 DK |
11509 | bp->link_params.speed_cap_mask[idx]); |
11510 | return; | |
11511 | } | |
11512 | break; | |
a2fbb9ea | 11513 | |
f85582f8 | 11514 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
11515 | if (bp->port.supported[idx] & |
11516 | SUPPORTED_10000baseT_Full) { | |
11517 | bp->link_params.req_line_speed[idx] = | |
11518 | SPEED_10000; | |
11519 | bp->port.advertising[idx] |= | |
11520 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 11521 | ADVERTISED_FIBRE); |
5d67c1c5 YM |
11522 | } else if (bp->port.supported[idx] & |
11523 | SUPPORTED_10000baseKR_Full) { | |
11524 | bp->link_params.req_line_speed[idx] = | |
11525 | SPEED_10000; | |
11526 | bp->port.advertising[idx] |= | |
11527 | (ADVERTISED_10000baseKR_Full | | |
11528 | ADVERTISED_FIBRE); | |
f85582f8 | 11529 | } else { |
51c1a580 | 11530 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 11531 | link_config, |
f85582f8 DK |
11532 | bp->link_params.speed_cap_mask[idx]); |
11533 | return; | |
11534 | } | |
11535 | break; | |
3c9ada22 YR |
11536 | case PORT_FEATURE_LINK_SPEED_20G: |
11537 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 11538 | |
3c9ada22 | 11539 | break; |
f85582f8 | 11540 | default: |
51c1a580 | 11541 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
754a2f52 | 11542 | link_config); |
f85582f8 DK |
11543 | bp->link_params.req_line_speed[idx] = |
11544 | SPEED_AUTO_NEG; | |
11545 | bp->port.advertising[idx] = | |
11546 | bp->port.supported[idx]; | |
11547 | break; | |
11548 | } | |
a2fbb9ea | 11549 | |
a22f0788 | 11550 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 11551 | PORT_FEATURE_FLOW_CONTROL_MASK); |
cd1dfce2 YM |
11552 | if (bp->link_params.req_flow_ctrl[idx] == |
11553 | BNX2X_FLOW_CTRL_AUTO) { | |
11554 | if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) | |
11555 | bp->link_params.req_flow_ctrl[idx] = | |
11556 | BNX2X_FLOW_CTRL_NONE; | |
11557 | else | |
11558 | bnx2x_set_requested_fc(bp); | |
a22f0788 | 11559 | } |
a2fbb9ea | 11560 | |
51c1a580 | 11561 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
a22f0788 YR |
11562 | bp->link_params.req_line_speed[idx], |
11563 | bp->link_params.req_duplex[idx], | |
11564 | bp->link_params.req_flow_ctrl[idx], | |
11565 | bp->port.advertising[idx]); | |
11566 | } | |
a2fbb9ea ET |
11567 | } |
11568 | ||
0329aba1 | 11569 | static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
e665bfda | 11570 | { |
86564c3f YM |
11571 | __be16 mac_hi_be = cpu_to_be16(mac_hi); |
11572 | __be32 mac_lo_be = cpu_to_be32(mac_lo); | |
11573 | memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be)); | |
11574 | memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be)); | |
e665bfda MC |
11575 | } |
11576 | ||
0329aba1 | 11577 | static void bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 11578 | { |
34f80b04 | 11579 | int port = BP_PORT(bp); |
589abe3a | 11580 | u32 config; |
c8c60d88 | 11581 | u32 ext_phy_type, ext_phy_config, eee_mode; |
a2fbb9ea | 11582 | |
c18487ee | 11583 | bp->link_params.bp = bp; |
34f80b04 | 11584 | bp->link_params.port = port; |
c18487ee | 11585 | |
c18487ee | 11586 | bp->link_params.lane_config = |
a2fbb9ea | 11587 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 11588 | |
a22f0788 | 11589 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea | 11590 | SHMEM_RD(bp, |
b0261926 YR |
11591 | dev_info.port_hw_config[port].speed_capability_mask) & |
11592 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | |
a22f0788 YR |
11593 | bp->link_params.speed_cap_mask[1] = |
11594 | SHMEM_RD(bp, | |
b0261926 YR |
11595 | dev_info.port_hw_config[port].speed_capability_mask2) & |
11596 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | |
a22f0788 | 11597 | bp->port.link_config[0] = |
a2fbb9ea ET |
11598 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
11599 | ||
a22f0788 YR |
11600 | bp->port.link_config[1] = |
11601 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 11602 | |
a22f0788 YR |
11603 | bp->link_params.multi_phy_config = |
11604 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
11605 | /* If the device is capable of WoL, set the default state according |
11606 | * to the HW | |
11607 | */ | |
4d295db0 | 11608 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
11609 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
11610 | (config & PORT_FEATURE_WOL_ENABLED)); | |
11611 | ||
4ba7699b YM |
11612 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == |
11613 | PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) | |
11614 | bp->flags |= NO_ISCSI_FLAG; | |
11615 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == | |
11616 | PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) | |
11617 | bp->flags |= NO_FCOE_FLAG; | |
11618 | ||
51c1a580 | 11619 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 11620 | bp->link_params.lane_config, |
a22f0788 YR |
11621 | bp->link_params.speed_cap_mask[0], |
11622 | bp->port.link_config[0]); | |
a2fbb9ea | 11623 | |
a22f0788 | 11624 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 11625 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 11626 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 11627 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
11628 | |
11629 | bnx2x_link_settings_requested(bp); | |
11630 | ||
01cd4528 EG |
11631 | /* |
11632 | * If connected directly, work with the internal PHY, otherwise, work | |
11633 | * with the external PHY | |
11634 | */ | |
b7737c9b YR |
11635 | ext_phy_config = |
11636 | SHMEM_RD(bp, | |
11637 | dev_info.port_hw_config[port].external_phy_config); | |
11638 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 11639 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 11640 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
11641 | |
11642 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
11643 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
11644 | bp->mdio.prtad = | |
b7737c9b | 11645 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d | 11646 | |
c8c60d88 YM |
11647 | /* Configure link feature according to nvram value */ |
11648 | eee_mode = (((SHMEM_RD(bp, dev_info. | |
11649 | port_feature_config[port].eee_power_mode)) & | |
11650 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
11651 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
11652 | if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { | |
11653 | bp->link_params.eee_mode = EEE_MODE_ADV_LPI | | |
11654 | EEE_MODE_ENABLE_LPI | | |
11655 | EEE_MODE_OUTPUT_TIME; | |
11656 | } else { | |
11657 | bp->link_params.eee_mode = 0; | |
11658 | } | |
0793f83f | 11659 | } |
01cd4528 | 11660 | |
b306f5ed | 11661 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 11662 | { |
9e62e912 | 11663 | u32 no_flags = NO_ISCSI_FLAG; |
bf61ee14 | 11664 | int port = BP_PORT(bp); |
2ba45142 | 11665 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 11666 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 11667 | |
55c11941 MS |
11668 | if (!CNIC_SUPPORT(bp)) { |
11669 | bp->flags |= no_flags; | |
11670 | return; | |
11671 | } | |
11672 | ||
b306f5ed | 11673 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
11674 | bp->cnic_eth_dev.max_iscsi_conn = |
11675 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
11676 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
11677 | ||
b306f5ed DK |
11678 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
11679 | bp->cnic_eth_dev.max_iscsi_conn); | |
11680 | ||
11681 | /* | |
11682 | * If maximum allowed number of connections is zero - | |
11683 | * disable the feature. | |
11684 | */ | |
11685 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9e62e912 | 11686 | bp->flags |= no_flags; |
b306f5ed DK |
11687 | } |
11688 | ||
0329aba1 | 11689 | static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) |
9e62e912 DK |
11690 | { |
11691 | /* Port info */ | |
11692 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
11693 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); | |
11694 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
11695 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); | |
11696 | ||
11697 | /* Node info */ | |
11698 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
11699 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); | |
11700 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
11701 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); | |
11702 | } | |
86800194 DK |
11703 | |
11704 | static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) | |
11705 | { | |
11706 | u8 count = 0; | |
11707 | ||
11708 | if (IS_MF(bp)) { | |
11709 | u8 fid; | |
11710 | ||
11711 | /* iterate over absolute function ids for this path: */ | |
11712 | for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { | |
11713 | if (IS_MF_SD(bp)) { | |
11714 | u32 cfg = MF_CFG_RD(bp, | |
11715 | func_mf_config[fid].config); | |
11716 | ||
11717 | if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) && | |
11718 | ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) == | |
11719 | FUNC_MF_CFG_PROTOCOL_FCOE)) | |
11720 | count++; | |
11721 | } else { | |
11722 | u32 cfg = MF_CFG_RD(bp, | |
11723 | func_ext_config[fid]. | |
11724 | func_cfg); | |
11725 | ||
11726 | if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) && | |
11727 | (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)) | |
11728 | count++; | |
11729 | } | |
11730 | } | |
11731 | } else { /* SF */ | |
11732 | int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; | |
11733 | ||
11734 | for (port = 0; port < port_cnt; port++) { | |
11735 | u32 lic = SHMEM_RD(bp, | |
11736 | drv_lic_key[port].max_fcoe_conn) ^ | |
11737 | FW_ENCODE_32BIT_PATTERN; | |
11738 | if (lic) | |
11739 | count++; | |
11740 | } | |
11741 | } | |
11742 | ||
11743 | return count; | |
11744 | } | |
11745 | ||
0329aba1 | 11746 | static void bnx2x_get_fcoe_info(struct bnx2x *bp) |
b306f5ed DK |
11747 | { |
11748 | int port = BP_PORT(bp); | |
11749 | int func = BP_ABS_FUNC(bp); | |
b306f5ed DK |
11750 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
11751 | drv_lic_key[port].max_fcoe_conn); | |
86800194 | 11752 | u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); |
b306f5ed | 11753 | |
55c11941 MS |
11754 | if (!CNIC_SUPPORT(bp)) { |
11755 | bp->flags |= NO_FCOE_FLAG; | |
11756 | return; | |
11757 | } | |
11758 | ||
b306f5ed | 11759 | /* Get the number of maximum allowed FCoE connections */ |
2ba45142 VZ |
11760 | bp->cnic_eth_dev.max_fcoe_conn = |
11761 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
11762 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
11763 | ||
0eb43b4b BPG |
11764 | /* Calculate the number of maximum allowed FCoE tasks */ |
11765 | bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; | |
86800194 DK |
11766 | |
11767 | /* check if FCoE resources must be shared between different functions */ | |
11768 | if (num_fcoe_func) | |
11769 | bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; | |
0eb43b4b | 11770 | |
bf61ee14 VZ |
11771 | /* Read the WWN: */ |
11772 | if (!IS_MF(bp)) { | |
11773 | /* Port info */ | |
11774 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
11775 | SHMEM_RD(bp, | |
2de67439 | 11776 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11777 | fcoe_wwn_port_name_upper); |
11778 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
11779 | SHMEM_RD(bp, | |
2de67439 | 11780 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11781 | fcoe_wwn_port_name_lower); |
11782 | ||
11783 | /* Node info */ | |
11784 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
11785 | SHMEM_RD(bp, | |
2de67439 | 11786 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11787 | fcoe_wwn_node_name_upper); |
11788 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
11789 | SHMEM_RD(bp, | |
2de67439 | 11790 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11791 | fcoe_wwn_node_name_lower); |
11792 | } else if (!IS_MF_SD(bp)) { | |
2e98ffc2 | 11793 | /* Read the WWN info only if the FCoE feature is enabled for |
bf61ee14 VZ |
11794 | * this function. |
11795 | */ | |
2e98ffc2 DK |
11796 | if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp)) |
11797 | bnx2x_get_ext_wwn_info(bp, func); | |
11798 | } else { | |
11799 | if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) | |
9e62e912 | 11800 | bnx2x_get_ext_wwn_info(bp, func); |
382e513a | 11801 | } |
bf61ee14 | 11802 | |
b306f5ed | 11803 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 11804 | |
bf61ee14 VZ |
11805 | /* |
11806 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
11807 | * disable the feature. |
11808 | */ | |
8cc13659 | 11809 | if (!bp->cnic_eth_dev.max_fcoe_conn) { |
2ba45142 | 11810 | bp->flags |= NO_FCOE_FLAG; |
8cc13659 SRK |
11811 | eth_zero_addr(bp->fip_mac); |
11812 | } | |
2ba45142 | 11813 | } |
b306f5ed | 11814 | |
0329aba1 | 11815 | static void bnx2x_get_cnic_info(struct bnx2x *bp) |
b306f5ed DK |
11816 | { |
11817 | /* | |
11818 | * iSCSI may be dynamically disabled but reading | |
11819 | * info here we will decrease memory usage by driver | |
11820 | * if the feature is disabled for good | |
11821 | */ | |
11822 | bnx2x_get_iscsi_info(bp); | |
11823 | bnx2x_get_fcoe_info(bp); | |
11824 | } | |
2ba45142 | 11825 | |
0329aba1 | 11826 | static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) |
0793f83f DK |
11827 | { |
11828 | u32 val, val2; | |
11829 | int func = BP_ABS_FUNC(bp); | |
11830 | int port = BP_PORT(bp); | |
2ba45142 VZ |
11831 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; |
11832 | u8 *fip_mac = bp->fip_mac; | |
0793f83f | 11833 | |
55c11941 MS |
11834 | if (IS_MF(bp)) { |
11835 | /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or | |
2ba45142 | 11836 | * FCoE MAC then the appropriate feature should be disabled. |
55c11941 MS |
11837 | * In non SD mode features configuration comes from struct |
11838 | * func_ext_config. | |
2ba45142 | 11839 | */ |
2e98ffc2 | 11840 | if (!IS_MF_SD(bp)) { |
0793f83f DK |
11841 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
11842 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
11843 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 11844 | iscsi_mac_addr_upper); |
0793f83f | 11845 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 11846 | iscsi_mac_addr_lower); |
2ba45142 | 11847 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
55c11941 MS |
11848 | BNX2X_DEV_INFO |
11849 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
11850 | } else { | |
2ba45142 | 11851 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
55c11941 | 11852 | } |
2ba45142 VZ |
11853 | |
11854 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
11855 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 11856 | fcoe_mac_addr_upper); |
2ba45142 | 11857 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 11858 | fcoe_mac_addr_lower); |
2ba45142 | 11859 | bnx2x_set_mac_buf(fip_mac, val, val2); |
55c11941 MS |
11860 | BNX2X_DEV_INFO |
11861 | ("Read FCoE L2 MAC: %pM\n", fip_mac); | |
11862 | } else { | |
2ba45142 | 11863 | bp->flags |= NO_FCOE_FLAG; |
55c11941 | 11864 | } |
a3348722 BW |
11865 | |
11866 | bp->mf_ext_config = cfg; | |
11867 | ||
9e62e912 | 11868 | } else { /* SD MODE */ |
55c11941 MS |
11869 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { |
11870 | /* use primary mac as iscsi mac */ | |
11871 | memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); | |
11872 | ||
11873 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); | |
11874 | BNX2X_DEV_INFO | |
11875 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
11876 | } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { | |
11877 | /* use primary mac as fip mac */ | |
11878 | memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); | |
11879 | BNX2X_DEV_INFO("SD FCoE MODE\n"); | |
11880 | BNX2X_DEV_INFO | |
11881 | ("Read FIP MAC: %pM\n", fip_mac); | |
614c76df | 11882 | } |
0793f83f | 11883 | } |
a3348722 | 11884 | |
82594f8f YM |
11885 | /* If this is a storage-only interface, use SAN mac as |
11886 | * primary MAC. Notice that for SD this is already the case, | |
11887 | * as the SAN mac was copied from the primary MAC. | |
11888 | */ | |
11889 | if (IS_MF_FCOE_AFEX(bp)) | |
a3348722 | 11890 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); |
0793f83f | 11891 | } else { |
0793f83f | 11892 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11893 | iscsi_mac_upper); |
0793f83f | 11894 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11895 | iscsi_mac_lower); |
2ba45142 | 11896 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
11897 | |
11898 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
55c11941 | 11899 | fcoe_fip_mac_upper); |
c03bd39c | 11900 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11901 | fcoe_fip_mac_lower); |
c03bd39c | 11902 | bnx2x_set_mac_buf(fip_mac, val, val2); |
0793f83f DK |
11903 | } |
11904 | ||
55c11941 | 11905 | /* Disable iSCSI OOO if MAC configuration is invalid. */ |
426b9241 | 11906 | if (!is_valid_ether_addr(iscsi_mac)) { |
55c11941 | 11907 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
c7bf7169 | 11908 | eth_zero_addr(iscsi_mac); |
426b9241 DK |
11909 | } |
11910 | ||
55c11941 | 11911 | /* Disable FCoE if MAC configuration is invalid. */ |
426b9241 DK |
11912 | if (!is_valid_ether_addr(fip_mac)) { |
11913 | bp->flags |= NO_FCOE_FLAG; | |
c7bf7169 | 11914 | eth_zero_addr(bp->fip_mac); |
426b9241 | 11915 | } |
55c11941 MS |
11916 | } |
11917 | ||
0329aba1 | 11918 | static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
55c11941 MS |
11919 | { |
11920 | u32 val, val2; | |
11921 | int func = BP_ABS_FUNC(bp); | |
11922 | int port = BP_PORT(bp); | |
11923 | ||
11924 | /* Zero primary MAC configuration */ | |
c7bf7169 | 11925 | eth_zero_addr(bp->dev->dev_addr); |
55c11941 MS |
11926 | |
11927 | if (BP_NOMCP(bp)) { | |
11928 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
11929 | eth_hw_addr_random(bp->dev); | |
11930 | } else if (IS_MF(bp)) { | |
11931 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
11932 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
11933 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
11934 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
11935 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
11936 | ||
11937 | if (CNIC_SUPPORT(bp)) | |
11938 | bnx2x_get_cnic_mac_hwinfo(bp); | |
11939 | } else { | |
11940 | /* in SF read MACs from port configuration */ | |
11941 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
11942 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
11943 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
11944 | ||
11945 | if (CNIC_SUPPORT(bp)) | |
11946 | bnx2x_get_cnic_mac_hwinfo(bp); | |
11947 | } | |
11948 | ||
3d7d562c YM |
11949 | if (!BP_NOMCP(bp)) { |
11950 | /* Read physical port identifier from shmem */ | |
11951 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
11952 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
11953 | bnx2x_set_mac_buf(bp->phys_port_id, val, val2); | |
11954 | bp->flags |= HAS_PHYS_PORT_ID; | |
11955 | } | |
11956 | ||
55c11941 | 11957 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); |
619c5cb6 | 11958 | |
2e98ffc2 | 11959 | if (!is_valid_ether_addr(bp->dev->dev_addr)) |
619c5cb6 | 11960 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11961 | "bad Ethernet MAC address configuration: %pM\n" |
11962 | "change it manually before bringing up the appropriate network interface\n", | |
0f9dad10 | 11963 | bp->dev->dev_addr); |
7964211d | 11964 | } |
51c1a580 | 11965 | |
0329aba1 | 11966 | static bool bnx2x_get_dropless_info(struct bnx2x *bp) |
7964211d YM |
11967 | { |
11968 | int tmp; | |
11969 | u32 cfg; | |
51c1a580 | 11970 | |
aeeddb8b | 11971 | if (IS_VF(bp)) |
4e833c59 | 11972 | return false; |
aeeddb8b | 11973 | |
7964211d YM |
11974 | if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { |
11975 | /* Take function: tmp = func */ | |
11976 | tmp = BP_ABS_FUNC(bp); | |
11977 | cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); | |
11978 | cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); | |
11979 | } else { | |
11980 | /* Take port: tmp = port */ | |
11981 | tmp = BP_PORT(bp); | |
11982 | cfg = SHMEM_RD(bp, | |
11983 | dev_info.port_hw_config[tmp].generic_features); | |
11984 | cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); | |
11985 | } | |
11986 | return cfg; | |
34f80b04 EG |
11987 | } |
11988 | ||
83bad206 YM |
11989 | static void validate_set_si_mode(struct bnx2x *bp) |
11990 | { | |
11991 | u8 func = BP_ABS_FUNC(bp); | |
11992 | u32 val; | |
11993 | ||
11994 | val = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
11995 | ||
11996 | /* check for legal mac (upper bytes) */ | |
11997 | if (val != 0xffff) { | |
11998 | bp->mf_mode = MULTI_FUNCTION_SI; | |
11999 | bp->mf_config[BP_VN(bp)] = | |
12000 | MF_CFG_RD(bp, func_mf_config[func].config); | |
12001 | } else | |
12002 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); | |
12003 | } | |
12004 | ||
0329aba1 | 12005 | static int bnx2x_get_hwinfo(struct bnx2x *bp) |
34f80b04 | 12006 | { |
0793f83f | 12007 | int /*abs*/func = BP_ABS_FUNC(bp); |
230d00eb | 12008 | int vn, mfw_vn; |
83bad206 | 12009 | u32 val = 0, val2 = 0; |
34f80b04 | 12010 | int rc = 0; |
a2fbb9ea | 12011 | |
0f587f1b YM |
12012 | /* Validate that chip access is feasible */ |
12013 | if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) { | |
12014 | dev_err(&bp->pdev->dev, | |
12015 | "Chip read returns all Fs. Preventing probe from continuing\n"); | |
12016 | return -EINVAL; | |
12017 | } | |
12018 | ||
34f80b04 | 12019 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 12020 | |
6383c0b3 AE |
12021 | /* |
12022 | * initialize IGU parameters | |
12023 | */ | |
f2e0899f DK |
12024 | if (CHIP_IS_E1x(bp)) { |
12025 | bp->common.int_block = INT_BLOCK_HC; | |
12026 | ||
12027 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
12028 | bp->igu_base_sb = 0; | |
f2e0899f DK |
12029 | } else { |
12030 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 | 12031 | |
16a5fd92 | 12032 | /* do not allow device reset during IGU info processing */ |
7a06a122 DK |
12033 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
12034 | ||
f2e0899f | 12035 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
12036 | |
12037 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
12038 | int tout = 5000; | |
12039 | ||
12040 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
12041 | ||
12042 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
12043 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
12044 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
12045 | ||
12046 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
12047 | tout--; | |
0926d499 | 12048 | usleep_range(1000, 2000); |
619c5cb6 VZ |
12049 | } |
12050 | ||
12051 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
12052 | dev_err(&bp->pdev->dev, | |
12053 | "FORCING Normal Mode failed!!!\n"); | |
9b341bb1 BW |
12054 | bnx2x_release_hw_lock(bp, |
12055 | HW_LOCK_RESOURCE_RESET); | |
619c5cb6 VZ |
12056 | return -EPERM; |
12057 | } | |
12058 | } | |
12059 | ||
f2e0899f | 12060 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 12061 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
12062 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
12063 | } else | |
619c5cb6 | 12064 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 12065 | |
9b341bb1 | 12066 | rc = bnx2x_get_igu_cam_info(bp); |
7a06a122 | 12067 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
9b341bb1 BW |
12068 | if (rc) |
12069 | return rc; | |
f2e0899f | 12070 | } |
619c5cb6 VZ |
12071 | |
12072 | /* | |
12073 | * set base FW non-default (fast path) status block id, this value is | |
12074 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
12075 | * determine the id used by the FW. | |
12076 | */ | |
12077 | if (CHIP_IS_E1x(bp)) | |
12078 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
12079 | else /* | |
12080 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
12081 | * the same queue are indicated on the same IGU SB). So we prefer | |
12082 | * FW and IGU SBs to be the same value. | |
12083 | */ | |
12084 | bp->base_fw_ndsb = bp->igu_base_sb; | |
12085 | ||
12086 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
12087 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
12088 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
12089 | |
12090 | /* | |
12091 | * Initialize MF configuration | |
12092 | */ | |
523224a3 | 12093 | |
fb3bff17 DK |
12094 | bp->mf_ov = 0; |
12095 | bp->mf_mode = 0; | |
7609647e | 12096 | bp->mf_sub_mode = 0; |
3395a033 | 12097 | vn = BP_VN(bp); |
230d00eb | 12098 | mfw_vn = BP_FW_MB_IDX(bp); |
0793f83f | 12099 | |
f2e0899f | 12100 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
12101 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
12102 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
12103 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
12104 | ||
f2e0899f DK |
12105 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
12106 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
12107 | else | |
12108 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
12109 | offsetof(struct shmem_region, func_mb) + |
12110 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
12111 | /* |
12112 | * get mf configuration: | |
16a5fd92 | 12113 | * 1. Existence of MF configuration |
0793f83f DK |
12114 | * 2. MAC address must be legal (check only upper bytes) |
12115 | * for Switch-Independent mode; | |
12116 | * OVLAN must be legal for Switch-Dependent mode | |
12117 | * 3. SF_MODE configures specific MF mode | |
12118 | */ | |
12119 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
12120 | /* get mf configuration */ | |
12121 | val = SHMEM_RD(bp, | |
12122 | dev_info.shared_feature_config.config); | |
12123 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
12124 | ||
12125 | switch (val) { | |
12126 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
83bad206 | 12127 | validate_set_si_mode(bp); |
0793f83f | 12128 | break; |
a3348722 BW |
12129 | case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: |
12130 | if ((!CHIP_IS_E1x(bp)) && | |
12131 | (MF_CFG_RD(bp, func_mf_config[func]. | |
12132 | mac_upper) != 0xffff) && | |
12133 | (SHMEM2_HAS(bp, | |
12134 | afex_driver_support))) { | |
12135 | bp->mf_mode = MULTI_FUNCTION_AFEX; | |
12136 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
12137 | func_mf_config[func].config); | |
12138 | } else { | |
12139 | BNX2X_DEV_INFO("can not configure afex mode\n"); | |
12140 | } | |
12141 | break; | |
0793f83f DK |
12142 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: |
12143 | /* get OV configuration */ | |
12144 | val = MF_CFG_RD(bp, | |
12145 | func_mf_config[FUNC_0].e1hov_tag); | |
12146 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
12147 | ||
12148 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
12149 | bp->mf_mode = MULTI_FUNCTION_SD; | |
12150 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
12151 | func_mf_config[func].config); | |
12152 | } else | |
754a2f52 | 12153 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f | 12154 | break; |
230d00eb YM |
12155 | case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE: |
12156 | bp->mf_mode = MULTI_FUNCTION_SD; | |
12157 | bp->mf_sub_mode = SUB_MF_MODE_BD; | |
12158 | bp->mf_config[vn] = | |
12159 | MF_CFG_RD(bp, | |
12160 | func_mf_config[func].config); | |
12161 | ||
12162 | if (SHMEM2_HAS(bp, mtu_size)) { | |
12163 | int mtu_idx = BP_FW_MB_IDX(bp); | |
12164 | u16 mtu_size; | |
12165 | u32 mtu; | |
12166 | ||
12167 | mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]); | |
12168 | mtu_size = (u16)mtu; | |
12169 | DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n", | |
12170 | mtu_size, mtu); | |
12171 | ||
12172 | /* if valid: update device mtu */ | |
e1c6dcca | 12173 | if ((mtu_size >= ETH_MIN_PACKET_SIZE) && |
230d00eb YM |
12174 | (mtu_size <= |
12175 | ETH_MAX_JUMBO_PACKET_SIZE)) | |
12176 | bp->dev->mtu = mtu_size; | |
12177 | } | |
12178 | break; | |
7609647e YM |
12179 | case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE: |
12180 | bp->mf_mode = MULTI_FUNCTION_SD; | |
12181 | bp->mf_sub_mode = SUB_MF_MODE_UFP; | |
12182 | bp->mf_config[vn] = | |
12183 | MF_CFG_RD(bp, | |
12184 | func_mf_config[func].config); | |
12185 | break; | |
3786b942 AE |
12186 | case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: |
12187 | bp->mf_config[vn] = 0; | |
12188 | break; | |
83bad206 YM |
12189 | case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE: |
12190 | val2 = SHMEM_RD(bp, | |
12191 | dev_info.shared_hw_config.config_3); | |
12192 | val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK; | |
12193 | switch (val2) { | |
12194 | case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5: | |
12195 | validate_set_si_mode(bp); | |
12196 | bp->mf_sub_mode = | |
12197 | SUB_MF_MODE_NPAR1_DOT_5; | |
12198 | break; | |
12199 | default: | |
12200 | /* Unknown configuration */ | |
12201 | bp->mf_config[vn] = 0; | |
12202 | BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n", | |
12203 | val); | |
12204 | } | |
12205 | break; | |
0793f83f DK |
12206 | default: |
12207 | /* Unknown configuration: reset mf_config */ | |
12208 | bp->mf_config[vn] = 0; | |
51c1a580 | 12209 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
0793f83f DK |
12210 | } |
12211 | } | |
a2fbb9ea | 12212 | |
2691d51d | 12213 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 12214 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 12215 | |
0793f83f DK |
12216 | switch (bp->mf_mode) { |
12217 | case MULTI_FUNCTION_SD: | |
12218 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
12219 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 12220 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 12221 | bp->mf_ov = val; |
619c5cb6 VZ |
12222 | bp->path_has_ovlan = true; |
12223 | ||
51c1a580 MS |
12224 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
12225 | func, bp->mf_ov, bp->mf_ov); | |
230d00eb YM |
12226 | } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) || |
12227 | (bp->mf_sub_mode == SUB_MF_MODE_BD)) { | |
7609647e | 12228 | dev_err(&bp->pdev->dev, |
230d00eb | 12229 | "Unexpected - no valid MF OV for func %d in UFP/BD mode\n", |
7609647e YM |
12230 | func); |
12231 | bp->path_has_ovlan = true; | |
2691d51d | 12232 | } else { |
619c5cb6 | 12233 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
12234 | "No valid MF OV for func %d, aborting\n", |
12235 | func); | |
619c5cb6 | 12236 | return -EPERM; |
34f80b04 | 12237 | } |
0793f83f | 12238 | break; |
a3348722 BW |
12239 | case MULTI_FUNCTION_AFEX: |
12240 | BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); | |
12241 | break; | |
0793f83f | 12242 | case MULTI_FUNCTION_SI: |
51c1a580 MS |
12243 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
12244 | func); | |
0793f83f DK |
12245 | break; |
12246 | default: | |
12247 | if (vn) { | |
619c5cb6 | 12248 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
12249 | "VN %d is in a single function mode, aborting\n", |
12250 | vn); | |
619c5cb6 | 12251 | return -EPERM; |
2691d51d | 12252 | } |
0793f83f | 12253 | break; |
34f80b04 | 12254 | } |
0793f83f | 12255 | |
619c5cb6 VZ |
12256 | /* check if other port on the path needs ovlan: |
12257 | * Since MF configuration is shared between ports | |
12258 | * Possible mixed modes are only | |
12259 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
12260 | */ | |
12261 | if (CHIP_MODE_IS_4_PORT(bp) && | |
12262 | !bp->path_has_ovlan && | |
12263 | !IS_MF(bp) && | |
12264 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
12265 | u8 other_port = !BP_PORT(bp); | |
12266 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
12267 | val = MF_CFG_RD(bp, | |
12268 | func_mf_config[other_func].e1hov_tag); | |
12269 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
12270 | bp->path_has_ovlan = true; | |
12271 | } | |
34f80b04 | 12272 | } |
a2fbb9ea | 12273 | |
e848582c DK |
12274 | /* adjust igu_sb_cnt to MF for E1H */ |
12275 | if (CHIP_IS_E1H(bp) && IS_MF(bp)) | |
12276 | bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT); | |
523224a3 | 12277 | |
619c5cb6 VZ |
12278 | /* port info */ |
12279 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 12280 | |
0793f83f DK |
12281 | /* Get MAC addresses */ |
12282 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 12283 | |
2ba45142 | 12284 | bnx2x_get_cnic_info(bp); |
2ba45142 | 12285 | |
34f80b04 EG |
12286 | return rc; |
12287 | } | |
12288 | ||
0329aba1 | 12289 | static void bnx2x_read_fwinfo(struct bnx2x *bp) |
34f24c7f VZ |
12290 | { |
12291 | int cnt, i, block_end, rodi; | |
fcdf95cb | 12292 | char vpd_start[BNX2X_VPD_LEN+1]; |
34f24c7f VZ |
12293 | char str_id_reg[VENDOR_ID_LEN+1]; |
12294 | char str_id_cap[VENDOR_ID_LEN+1]; | |
fcdf95cb BW |
12295 | char *vpd_data; |
12296 | char *vpd_extended_data = NULL; | |
34f24c7f VZ |
12297 | u8 len; |
12298 | ||
fcdf95cb | 12299 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); |
34f24c7f VZ |
12300 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
12301 | ||
12302 | if (cnt < BNX2X_VPD_LEN) | |
12303 | goto out_not_found; | |
12304 | ||
fcdf95cb BW |
12305 | /* VPD RO tag should be first tag after identifier string, hence |
12306 | * we should be able to find it in first BNX2X_VPD_LEN chars | |
12307 | */ | |
12308 | i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, | |
34f24c7f VZ |
12309 | PCI_VPD_LRDT_RO_DATA); |
12310 | if (i < 0) | |
12311 | goto out_not_found; | |
12312 | ||
34f24c7f | 12313 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + |
fcdf95cb | 12314 | pci_vpd_lrdt_size(&vpd_start[i]); |
34f24c7f VZ |
12315 | |
12316 | i += PCI_VPD_LRDT_TAG_SIZE; | |
12317 | ||
fcdf95cb BW |
12318 | if (block_end > BNX2X_VPD_LEN) { |
12319 | vpd_extended_data = kmalloc(block_end, GFP_KERNEL); | |
12320 | if (vpd_extended_data == NULL) | |
12321 | goto out_not_found; | |
12322 | ||
12323 | /* read rest of vpd image into vpd_extended_data */ | |
12324 | memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); | |
12325 | cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, | |
12326 | block_end - BNX2X_VPD_LEN, | |
12327 | vpd_extended_data + BNX2X_VPD_LEN); | |
12328 | if (cnt < (block_end - BNX2X_VPD_LEN)) | |
12329 | goto out_not_found; | |
12330 | vpd_data = vpd_extended_data; | |
12331 | } else | |
12332 | vpd_data = vpd_start; | |
12333 | ||
12334 | /* now vpd_data holds full vpd content in both cases */ | |
34f24c7f VZ |
12335 | |
12336 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
12337 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
12338 | if (rodi < 0) | |
12339 | goto out_not_found; | |
12340 | ||
12341 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
12342 | ||
12343 | if (len != VENDOR_ID_LEN) | |
12344 | goto out_not_found; | |
12345 | ||
12346 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
12347 | ||
12348 | /* vendor specific info */ | |
12349 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
12350 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
12351 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
12352 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
12353 | ||
12354 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
12355 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
12356 | if (rodi >= 0) { | |
12357 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
12358 | ||
12359 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
12360 | ||
12361 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
12362 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
12363 | bp->fw_ver[len] = ' '; | |
12364 | } | |
12365 | } | |
fcdf95cb | 12366 | kfree(vpd_extended_data); |
34f24c7f VZ |
12367 | return; |
12368 | } | |
12369 | out_not_found: | |
fcdf95cb | 12370 | kfree(vpd_extended_data); |
34f24c7f VZ |
12371 | return; |
12372 | } | |
12373 | ||
0329aba1 | 12374 | static void bnx2x_set_modes_bitmap(struct bnx2x *bp) |
619c5cb6 VZ |
12375 | { |
12376 | u32 flags = 0; | |
12377 | ||
12378 | if (CHIP_REV_IS_FPGA(bp)) | |
12379 | SET_FLAGS(flags, MODE_FPGA); | |
12380 | else if (CHIP_REV_IS_EMUL(bp)) | |
12381 | SET_FLAGS(flags, MODE_EMUL); | |
12382 | else | |
12383 | SET_FLAGS(flags, MODE_ASIC); | |
12384 | ||
12385 | if (CHIP_MODE_IS_4_PORT(bp)) | |
12386 | SET_FLAGS(flags, MODE_PORT4); | |
12387 | else | |
12388 | SET_FLAGS(flags, MODE_PORT2); | |
12389 | ||
12390 | if (CHIP_IS_E2(bp)) | |
12391 | SET_FLAGS(flags, MODE_E2); | |
12392 | else if (CHIP_IS_E3(bp)) { | |
12393 | SET_FLAGS(flags, MODE_E3); | |
12394 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
12395 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
12396 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
12397 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
12398 | } |
12399 | ||
12400 | if (IS_MF(bp)) { | |
12401 | SET_FLAGS(flags, MODE_MF); | |
12402 | switch (bp->mf_mode) { | |
12403 | case MULTI_FUNCTION_SD: | |
12404 | SET_FLAGS(flags, MODE_MF_SD); | |
12405 | break; | |
12406 | case MULTI_FUNCTION_SI: | |
12407 | SET_FLAGS(flags, MODE_MF_SI); | |
12408 | break; | |
a3348722 BW |
12409 | case MULTI_FUNCTION_AFEX: |
12410 | SET_FLAGS(flags, MODE_MF_AFEX); | |
12411 | break; | |
619c5cb6 VZ |
12412 | } |
12413 | } else | |
12414 | SET_FLAGS(flags, MODE_SF); | |
12415 | ||
12416 | #if defined(__LITTLE_ENDIAN) | |
12417 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
12418 | #else /*(__BIG_ENDIAN)*/ | |
12419 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
12420 | #endif | |
12421 | INIT_MODE_FLAGS(bp) = flags; | |
12422 | } | |
12423 | ||
0329aba1 | 12424 | static int bnx2x_init_bp(struct bnx2x *bp) |
34f80b04 | 12425 | { |
f2e0899f | 12426 | int func; |
34f80b04 EG |
12427 | int rc; |
12428 | ||
34f80b04 | 12429 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 12430 | mutex_init(&bp->fw_mb_mutex); |
42f8277f | 12431 | mutex_init(&bp->drv_info_mutex); |
c6e36d8c | 12432 | sema_init(&bp->stats_lock, 1); |
42f8277f | 12433 | bp->drv_info_mng_owner = false; |
05cc5a39 | 12434 | INIT_LIST_HEAD(&bp->vlan_reg); |
55c11941 | 12435 | |
1cf167f2 | 12436 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 12437 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 12438 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
370d4a26 | 12439 | INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task); |
1ab4434c AE |
12440 | if (IS_PF(bp)) { |
12441 | rc = bnx2x_get_hwinfo(bp); | |
12442 | if (rc) | |
12443 | return rc; | |
12444 | } else { | |
e09b74d0 | 12445 | eth_zero_addr(bp->dev->dev_addr); |
1ab4434c | 12446 | } |
34f80b04 | 12447 | |
619c5cb6 VZ |
12448 | bnx2x_set_modes_bitmap(bp); |
12449 | ||
12450 | rc = bnx2x_alloc_mem_bp(bp); | |
12451 | if (rc) | |
12452 | return rc; | |
523224a3 | 12453 | |
34f24c7f | 12454 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
12455 | |
12456 | func = BP_FUNC(bp); | |
12457 | ||
34f80b04 | 12458 | /* need to reset chip if undi was active */ |
1ab4434c | 12459 | if (IS_PF(bp) && !BP_NOMCP(bp)) { |
452427b0 YM |
12460 | /* init fw_seq */ |
12461 | bp->fw_seq = | |
12462 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
12463 | DRV_MSG_SEQ_NUMBER_MASK; | |
12464 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
12465 | ||
91ebb929 YM |
12466 | rc = bnx2x_prev_unload(bp); |
12467 | if (rc) { | |
12468 | bnx2x_free_mem_bp(bp); | |
12469 | return rc; | |
12470 | } | |
452427b0 YM |
12471 | } |
12472 | ||
34f80b04 | 12473 | if (CHIP_REV_IS_FPGA(bp)) |
cdaa7cb8 | 12474 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
12475 | |
12476 | if (BP_NOMCP(bp) && (func == 0)) | |
51c1a580 | 12477 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
34f80b04 | 12478 | |
614c76df | 12479 | bp->disable_tpa = disable_tpa; |
2e98ffc2 | 12480 | bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp); |
94d9de3c | 12481 | /* Reduce memory usage in kdump environment by disabling TPA */ |
c9931896 | 12482 | bp->disable_tpa |= is_kdump_kernel(); |
614c76df | 12483 | |
7a9b2557 | 12484 | /* Set TPA flags */ |
614c76df | 12485 | if (bp->disable_tpa) { |
d9b9e860 | 12486 | bp->dev->hw_features &= ~NETIF_F_LRO; |
7a9b2557 | 12487 | bp->dev->features &= ~NETIF_F_LRO; |
7a9b2557 VZ |
12488 | } |
12489 | ||
a18f5128 EG |
12490 | if (CHIP_IS_E1(bp)) |
12491 | bp->dropless_fc = 0; | |
12492 | else | |
7964211d | 12493 | bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); |
a18f5128 | 12494 | |
8d5726c4 | 12495 | bp->mrrs = mrrs; |
7a9b2557 | 12496 | |
2e98ffc2 | 12497 | bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL; |
1ab4434c AE |
12498 | if (IS_VF(bp)) |
12499 | bp->rx_ring_size = MAX_RX_AVAIL; | |
34f80b04 | 12500 | |
7d323bfd | 12501 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
12502 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
12503 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 12504 | |
fc543637 | 12505 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
34f80b04 | 12506 | |
e99e88a9 | 12507 | timer_setup(&bp->timer, bnx2x_timer, 0); |
34f80b04 | 12508 | bp->timer.expires = jiffies + bp->current_interval; |
34f80b04 | 12509 | |
0370cf90 BW |
12510 | if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && |
12511 | SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && | |
9c73267d | 12512 | SHMEM2_HAS(bp, dcbx_en) && |
0370cf90 | 12513 | SHMEM2_RD(bp, dcbx_lldp_params_offset) && |
9c73267d YM |
12514 | SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) && |
12515 | SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) { | |
0370cf90 BW |
12516 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); |
12517 | bnx2x_dcbx_init_params(bp); | |
12518 | } else { | |
12519 | bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); | |
12520 | } | |
e4901dde | 12521 | |
619c5cb6 VZ |
12522 | if (CHIP_IS_E1x(bp)) |
12523 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
12524 | else | |
12525 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
619c5cb6 | 12526 | |
6383c0b3 | 12527 | /* multiple tx priority */ |
1ab4434c AE |
12528 | if (IS_VF(bp)) |
12529 | bp->max_cos = 1; | |
12530 | else if (CHIP_IS_E1x(bp)) | |
6383c0b3 | 12531 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; |
1ab4434c | 12532 | else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) |
6383c0b3 | 12533 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; |
1ab4434c | 12534 | else if (CHIP_IS_E3B0(bp)) |
6383c0b3 | 12535 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; |
1ab4434c AE |
12536 | else |
12537 | BNX2X_ERR("unknown chip %x revision %x\n", | |
12538 | CHIP_NUM(bp), CHIP_REV(bp)); | |
12539 | BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); | |
6383c0b3 | 12540 | |
55c11941 MS |
12541 | /* We need at least one default status block for slow-path events, |
12542 | * second status block for the L2 queue, and a third status block for | |
16a5fd92 | 12543 | * CNIC if supported. |
55c11941 | 12544 | */ |
60cad4e6 AE |
12545 | if (IS_VF(bp)) |
12546 | bp->min_msix_vec_cnt = 1; | |
12547 | else if (CNIC_SUPPORT(bp)) | |
55c11941 | 12548 | bp->min_msix_vec_cnt = 3; |
60cad4e6 | 12549 | else /* PF w/o cnic */ |
55c11941 MS |
12550 | bp->min_msix_vec_cnt = 2; |
12551 | BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); | |
12552 | ||
5bb680d6 MS |
12553 | bp->dump_preset_idx = 1; |
12554 | ||
eeed018c MK |
12555 | if (CHIP_IS_E3B0(bp)) |
12556 | bp->flags |= PTP_SUPPORTED; | |
12557 | ||
34f80b04 | 12558 | return rc; |
a2fbb9ea ET |
12559 | } |
12560 | ||
de0c62db DK |
12561 | /**************************************************************************** |
12562 | * General service functions | |
12563 | ****************************************************************************/ | |
a2fbb9ea | 12564 | |
619c5cb6 VZ |
12565 | /* |
12566 | * net_device service functions | |
12567 | */ | |
12568 | ||
bb2a0f7a | 12569 | /* called with rtnl_lock */ |
a2fbb9ea ET |
12570 | static int bnx2x_open(struct net_device *dev) |
12571 | { | |
12572 | struct bnx2x *bp = netdev_priv(dev); | |
8395be5e | 12573 | int rc; |
a2fbb9ea | 12574 | |
1355b704 MY |
12575 | bp->stats_init = true; |
12576 | ||
6eccabb3 EG |
12577 | netif_carrier_off(dev); |
12578 | ||
a2fbb9ea ET |
12579 | bnx2x_set_power_state(bp, PCI_D0); |
12580 | ||
ad5afc89 | 12581 | /* If parity had happen during the unload, then attentions |
c9ee9206 VZ |
12582 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we |
12583 | * want the first function loaded on the current engine to | |
12584 | * complete the recovery. | |
ad5afc89 | 12585 | * Parity recovery is only relevant for PF driver. |
c9ee9206 | 12586 | */ |
ad5afc89 | 12587 | if (IS_PF(bp)) { |
1a6974b2 YM |
12588 | int other_engine = BP_PATH(bp) ? 0 : 1; |
12589 | bool other_load_status, load_status; | |
12590 | bool global = false; | |
12591 | ||
ad5afc89 AE |
12592 | other_load_status = bnx2x_get_load_status(bp, other_engine); |
12593 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); | |
12594 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
12595 | bnx2x_chk_parity_attn(bp, &global, true)) { | |
12596 | do { | |
12597 | /* If there are attentions and they are in a | |
12598 | * global blocks, set the GLOBAL_RESET bit | |
12599 | * regardless whether it will be this function | |
12600 | * that will complete the recovery or not. | |
12601 | */ | |
12602 | if (global) | |
12603 | bnx2x_set_reset_global(bp); | |
72fd0718 | 12604 | |
ad5afc89 AE |
12605 | /* Only the first function on the current |
12606 | * engine should try to recover in open. In case | |
12607 | * of attentions in global blocks only the first | |
12608 | * in the chip should try to recover. | |
12609 | */ | |
12610 | if ((!load_status && | |
12611 | (!global || !other_load_status)) && | |
12612 | bnx2x_trylock_leader_lock(bp) && | |
12613 | !bnx2x_leader_reset(bp)) { | |
12614 | netdev_info(bp->dev, | |
12615 | "Recovered in open\n"); | |
12616 | break; | |
12617 | } | |
72fd0718 | 12618 | |
ad5afc89 AE |
12619 | /* recovery has failed... */ |
12620 | bnx2x_set_power_state(bp, PCI_D3hot); | |
12621 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
72fd0718 | 12622 | |
ad5afc89 AE |
12623 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
12624 | "If you still see this message after a few retries then power cycle is required.\n"); | |
72fd0718 | 12625 | |
ad5afc89 AE |
12626 | return -EAGAIN; |
12627 | } while (0); | |
12628 | } | |
12629 | } | |
72fd0718 VZ |
12630 | |
12631 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
8395be5e AE |
12632 | rc = bnx2x_nic_load(bp, LOAD_OPEN); |
12633 | if (rc) | |
12634 | return rc; | |
f34fa14c | 12635 | |
883ce97d | 12636 | if (IS_PF(bp)) |
6b352912 | 12637 | udp_tunnel_get_rx_info(dev); |
f34fa14c | 12638 | |
9a8130bc | 12639 | return 0; |
a2fbb9ea ET |
12640 | } |
12641 | ||
bb2a0f7a | 12642 | /* called with rtnl_lock */ |
56ad3152 | 12643 | static int bnx2x_close(struct net_device *dev) |
a2fbb9ea | 12644 | { |
a2fbb9ea ET |
12645 | struct bnx2x *bp = netdev_priv(dev); |
12646 | ||
12647 | /* Unload the driver, release IRQs */ | |
5d07d868 | 12648 | bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); |
c9ee9206 | 12649 | |
a2fbb9ea ET |
12650 | return 0; |
12651 | } | |
12652 | ||
e8c6ae9f | 12653 | struct bnx2x_mcast_list_elem_group |
6e30dd4e | 12654 | { |
e8c6ae9f JB |
12655 | struct list_head mcast_group_link; |
12656 | struct bnx2x_mcast_list_elem mcast_elems[]; | |
12657 | }; | |
6e30dd4e | 12658 | |
e8c6ae9f JB |
12659 | #define MCAST_ELEMS_PER_PG \ |
12660 | ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \ | |
12661 | sizeof(struct bnx2x_mcast_list_elem)) | |
12662 | ||
12663 | static void bnx2x_free_mcast_macs_list(struct list_head *mcast_group_list) | |
12664 | { | |
12665 | struct bnx2x_mcast_list_elem_group *current_mcast_group; | |
12666 | ||
12667 | while (!list_empty(mcast_group_list)) { | |
12668 | current_mcast_group = list_first_entry(mcast_group_list, | |
12669 | struct bnx2x_mcast_list_elem_group, | |
12670 | mcast_group_link); | |
12671 | list_del(¤t_mcast_group->mcast_group_link); | |
12672 | free_page((unsigned long)current_mcast_group); | |
c7b7b483 | 12673 | } |
e8c6ae9f | 12674 | } |
6e30dd4e | 12675 | |
e8c6ae9f JB |
12676 | static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
12677 | struct bnx2x_mcast_ramrod_params *p, | |
12678 | struct list_head *mcast_group_list) | |
12679 | { | |
12680 | struct bnx2x_mcast_list_elem *mc_mac; | |
12681 | struct netdev_hw_addr *ha; | |
12682 | struct bnx2x_mcast_list_elem_group *current_mcast_group = NULL; | |
12683 | int mc_count = netdev_mc_count(bp->dev); | |
12684 | int offset = 0; | |
6e30dd4e | 12685 | |
e8c6ae9f | 12686 | INIT_LIST_HEAD(&p->mcast_list); |
619c5cb6 | 12687 | netdev_for_each_mc_addr(ha, bp->dev) { |
e8c6ae9f JB |
12688 | if (!offset) { |
12689 | current_mcast_group = | |
12690 | (struct bnx2x_mcast_list_elem_group *) | |
12691 | __get_free_page(GFP_ATOMIC); | |
12692 | if (!current_mcast_group) { | |
12693 | bnx2x_free_mcast_macs_list(mcast_group_list); | |
12694 | BNX2X_ERR("Failed to allocate mc MAC list\n"); | |
12695 | return -ENOMEM; | |
12696 | } | |
12697 | list_add(¤t_mcast_group->mcast_group_link, | |
12698 | mcast_group_list); | |
12699 | } | |
12700 | mc_mac = ¤t_mcast_group->mcast_elems[offset]; | |
619c5cb6 VZ |
12701 | mc_mac->mac = bnx2x_mc_addr(ha); |
12702 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
e8c6ae9f JB |
12703 | offset++; |
12704 | if (offset == MCAST_ELEMS_PER_PG) | |
12705 | offset = 0; | |
6e30dd4e | 12706 | } |
619c5cb6 | 12707 | p->mcast_list_len = mc_count; |
619c5cb6 | 12708 | return 0; |
6e30dd4e VZ |
12709 | } |
12710 | ||
619c5cb6 VZ |
12711 | /** |
12712 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
12713 | * | |
12714 | * @bp: driver handle | |
6e30dd4e | 12715 | * |
619c5cb6 | 12716 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 12717 | */ |
1191cb83 | 12718 | static int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 12719 | { |
619c5cb6 | 12720 | int rc; |
6e30dd4e | 12721 | struct net_device *dev = bp->dev; |
6e30dd4e | 12722 | struct netdev_hw_addr *ha; |
15192a8c | 12723 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; |
619c5cb6 | 12724 | unsigned long ramrod_flags = 0; |
6e30dd4e | 12725 | |
619c5cb6 VZ |
12726 | /* First schedule a cleanup up of old configuration */ |
12727 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
12728 | if (rc < 0) { | |
12729 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
12730 | return rc; | |
12731 | } | |
6e30dd4e VZ |
12732 | |
12733 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
12734 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
12735 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
7b5342d9 YM |
12736 | if (rc == -EEXIST) { |
12737 | DP(BNX2X_MSG_SP, | |
12738 | "Failed to schedule ADD operations: %d\n", rc); | |
12739 | /* do not treat adding same MAC as error */ | |
12740 | rc = 0; | |
12741 | ||
12742 | } else if (rc < 0) { | |
12743 | ||
619c5cb6 VZ |
12744 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", |
12745 | rc); | |
12746 | return rc; | |
6e30dd4e VZ |
12747 | } |
12748 | } | |
12749 | ||
619c5cb6 VZ |
12750 | /* Execute the pending commands */ |
12751 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
12752 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
12753 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
12754 | } |
12755 | ||
c7b7b483 | 12756 | static int bnx2x_set_mc_list_e1x(struct bnx2x *bp) |
6e30dd4e | 12757 | { |
e8c6ae9f | 12758 | LIST_HEAD(mcast_group_list); |
619c5cb6 | 12759 | struct net_device *dev = bp->dev; |
3b603066 | 12760 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 | 12761 | int rc = 0; |
6e30dd4e | 12762 | |
619c5cb6 | 12763 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 12764 | |
619c5cb6 VZ |
12765 | /* first, clear all configured multicast MACs */ |
12766 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
12767 | if (rc < 0) { | |
51c1a580 | 12768 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
619c5cb6 VZ |
12769 | return rc; |
12770 | } | |
6e30dd4e | 12771 | |
619c5cb6 VZ |
12772 | /* then, configure a new MACs list */ |
12773 | if (netdev_mc_count(dev)) { | |
e8c6ae9f | 12774 | rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); |
c7b7b483 | 12775 | if (rc) |
619c5cb6 | 12776 | return rc; |
6e30dd4e | 12777 | |
619c5cb6 VZ |
12778 | /* Now add the new MACs */ |
12779 | rc = bnx2x_config_mcast(bp, &rparam, | |
12780 | BNX2X_MCAST_CMD_ADD); | |
12781 | if (rc < 0) | |
51c1a580 MS |
12782 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
12783 | rc); | |
6e30dd4e | 12784 | |
e8c6ae9f | 12785 | bnx2x_free_mcast_macs_list(&mcast_group_list); |
619c5cb6 | 12786 | } |
6e30dd4e | 12787 | |
619c5cb6 | 12788 | return rc; |
6e30dd4e VZ |
12789 | } |
12790 | ||
c7b7b483 YM |
12791 | static int bnx2x_set_mc_list(struct bnx2x *bp) |
12792 | { | |
e8c6ae9f | 12793 | LIST_HEAD(mcast_group_list); |
c7b7b483 YM |
12794 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
12795 | struct net_device *dev = bp->dev; | |
12796 | int rc = 0; | |
12797 | ||
12798 | /* On older adapters, we need to flush and re-add filters */ | |
12799 | if (CHIP_IS_E1x(bp)) | |
12800 | return bnx2x_set_mc_list_e1x(bp); | |
12801 | ||
12802 | rparam.mcast_obj = &bp->mcast_obj; | |
12803 | ||
12804 | if (netdev_mc_count(dev)) { | |
e8c6ae9f | 12805 | rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); |
c7b7b483 YM |
12806 | if (rc) |
12807 | return rc; | |
12808 | ||
12809 | /* Override the curently configured set of mc filters */ | |
12810 | rc = bnx2x_config_mcast(bp, &rparam, | |
12811 | BNX2X_MCAST_CMD_SET); | |
12812 | if (rc < 0) | |
12813 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", | |
12814 | rc); | |
12815 | ||
e8c6ae9f | 12816 | bnx2x_free_mcast_macs_list(&mcast_group_list); |
c7b7b483 YM |
12817 | } else { |
12818 | /* If no mc addresses are required, flush the configuration */ | |
12819 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
d0c32a16 | 12820 | if (rc < 0) |
c7b7b483 YM |
12821 | BNX2X_ERR("Failed to clear multicast configuration %d\n", |
12822 | rc); | |
12823 | } | |
12824 | ||
12825 | return rc; | |
12826 | } | |
12827 | ||
619c5cb6 | 12828 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
a8f47eb7 | 12829 | static void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
12830 | { |
12831 | struct bnx2x *bp = netdev_priv(dev); | |
34f80b04 EG |
12832 | |
12833 | if (bp->state != BNX2X_STATE_OPEN) { | |
12834 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
12835 | return; | |
8b09be5f YM |
12836 | } else { |
12837 | /* Schedule an SP task to handle rest of change */ | |
230bb0f3 YM |
12838 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE, |
12839 | NETIF_MSG_IFUP); | |
34f80b04 | 12840 | } |
8b09be5f YM |
12841 | } |
12842 | ||
12843 | void bnx2x_set_rx_mode_inner(struct bnx2x *bp) | |
12844 | { | |
12845 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 | 12846 | |
619c5cb6 | 12847 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 | 12848 | |
8b09be5f YM |
12849 | netif_addr_lock_bh(bp->dev); |
12850 | ||
12851 | if (bp->dev->flags & IFF_PROMISC) { | |
34f80b04 | 12852 | rx_mode = BNX2X_RX_MODE_PROMISC; |
8b09be5f YM |
12853 | } else if ((bp->dev->flags & IFF_ALLMULTI) || |
12854 | ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && | |
12855 | CHIP_IS_E1(bp))) { | |
34f80b04 | 12856 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
8b09be5f | 12857 | } else { |
381ac16b AE |
12858 | if (IS_PF(bp)) { |
12859 | /* some multicasts */ | |
12860 | if (bnx2x_set_mc_list(bp) < 0) | |
12861 | rx_mode = BNX2X_RX_MODE_ALLMULTI; | |
34f80b04 | 12862 | |
8b09be5f YM |
12863 | /* release bh lock, as bnx2x_set_uc_list might sleep */ |
12864 | netif_addr_unlock_bh(bp->dev); | |
381ac16b AE |
12865 | if (bnx2x_set_uc_list(bp) < 0) |
12866 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
8b09be5f | 12867 | netif_addr_lock_bh(bp->dev); |
381ac16b AE |
12868 | } else { |
12869 | /* configuring mcast to a vf involves sleeping (when we | |
8b09be5f | 12870 | * wait for the pf's response). |
381ac16b | 12871 | */ |
230bb0f3 YM |
12872 | bnx2x_schedule_sp_rtnl(bp, |
12873 | BNX2X_SP_RTNL_VFPF_MCAST, 0); | |
381ac16b | 12874 | } |
34f80b04 EG |
12875 | } |
12876 | ||
12877 | bp->rx_mode = rx_mode; | |
614c76df | 12878 | /* handle ISCSI SD mode */ |
2e98ffc2 | 12879 | if (IS_MF_ISCSI_ONLY(bp)) |
614c76df | 12880 | bp->rx_mode = BNX2X_RX_MODE_NONE; |
619c5cb6 VZ |
12881 | |
12882 | /* Schedule the rx_mode command */ | |
12883 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
12884 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
8b09be5f | 12885 | netif_addr_unlock_bh(bp->dev); |
619c5cb6 VZ |
12886 | return; |
12887 | } | |
12888 | ||
381ac16b AE |
12889 | if (IS_PF(bp)) { |
12890 | bnx2x_set_storm_rx_mode(bp); | |
8b09be5f | 12891 | netif_addr_unlock_bh(bp->dev); |
381ac16b | 12892 | } else { |
8b09be5f YM |
12893 | /* VF will need to request the PF to make this change, and so |
12894 | * the VF needs to release the bottom-half lock prior to the | |
12895 | * request (as it will likely require sleep on the VF side) | |
381ac16b | 12896 | */ |
8b09be5f YM |
12897 | netif_addr_unlock_bh(bp->dev); |
12898 | bnx2x_vfpf_storm_rx_mode(bp); | |
381ac16b | 12899 | } |
34f80b04 EG |
12900 | } |
12901 | ||
c18487ee | 12902 | /* called with rtnl_lock */ |
01cd4528 EG |
12903 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
12904 | int devad, u16 addr) | |
a2fbb9ea | 12905 | { |
01cd4528 EG |
12906 | struct bnx2x *bp = netdev_priv(netdev); |
12907 | u16 value; | |
12908 | int rc; | |
a2fbb9ea | 12909 | |
01cd4528 EG |
12910 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
12911 | prtad, devad, addr); | |
a2fbb9ea | 12912 | |
01cd4528 EG |
12913 | /* The HW expects different devad if CL22 is used */ |
12914 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 12915 | |
01cd4528 | 12916 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 12917 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
12918 | bnx2x_release_phy_lock(bp); |
12919 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 12920 | |
01cd4528 EG |
12921 | if (!rc) |
12922 | rc = value; | |
12923 | return rc; | |
12924 | } | |
a2fbb9ea | 12925 | |
01cd4528 EG |
12926 | /* called with rtnl_lock */ |
12927 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
12928 | u16 addr, u16 value) | |
12929 | { | |
12930 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
12931 | int rc; |
12932 | ||
51c1a580 MS |
12933 | DP(NETIF_MSG_LINK, |
12934 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", | |
12935 | prtad, devad, addr, value); | |
01cd4528 | 12936 | |
01cd4528 EG |
12937 | /* The HW expects different devad if CL22 is used */ |
12938 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 12939 | |
01cd4528 | 12940 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 12941 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
12942 | bnx2x_release_phy_lock(bp); |
12943 | return rc; | |
12944 | } | |
c18487ee | 12945 | |
01cd4528 EG |
12946 | /* called with rtnl_lock */ |
12947 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
12948 | { | |
12949 | struct bnx2x *bp = netdev_priv(dev); | |
12950 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 12951 | |
01cd4528 EG |
12952 | if (!netif_running(dev)) |
12953 | return -EAGAIN; | |
12954 | ||
eeed018c MK |
12955 | switch (cmd) { |
12956 | case SIOCSHWTSTAMP: | |
12957 | return bnx2x_hwtstamp_ioctl(bp, ifr); | |
12958 | default: | |
12959 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", | |
12960 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
12961 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
12962 | } | |
a2fbb9ea ET |
12963 | } |
12964 | ||
257ddbda | 12965 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
12966 | static void poll_bnx2x(struct net_device *dev) |
12967 | { | |
12968 | struct bnx2x *bp = netdev_priv(dev); | |
14a15d61 | 12969 | int i; |
a2fbb9ea | 12970 | |
14a15d61 MS |
12971 | for_each_eth_queue(bp, i) { |
12972 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
12973 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); | |
12974 | } | |
a2fbb9ea ET |
12975 | } |
12976 | #endif | |
12977 | ||
614c76df DK |
12978 | static int bnx2x_validate_addr(struct net_device *dev) |
12979 | { | |
12980 | struct bnx2x *bp = netdev_priv(dev); | |
12981 | ||
e09b74d0 AE |
12982 | /* query the bulletin board for mac address configured by the PF */ |
12983 | if (IS_VF(bp)) | |
12984 | bnx2x_sample_bulletin(bp); | |
12985 | ||
2e98ffc2 | 12986 | if (!is_valid_ether_addr(dev->dev_addr)) { |
51c1a580 | 12987 | BNX2X_ERR("Non-valid Ethernet address\n"); |
614c76df | 12988 | return -EADDRNOTAVAIL; |
51c1a580 | 12989 | } |
614c76df DK |
12990 | return 0; |
12991 | } | |
12992 | ||
3d7d562c | 12993 | static int bnx2x_get_phys_port_id(struct net_device *netdev, |
02637fce | 12994 | struct netdev_phys_item_id *ppid) |
3d7d562c YM |
12995 | { |
12996 | struct bnx2x *bp = netdev_priv(netdev); | |
12997 | ||
12998 | if (!(bp->flags & HAS_PHYS_PORT_ID)) | |
12999 | return -EOPNOTSUPP; | |
13000 | ||
13001 | ppid->id_len = sizeof(bp->phys_port_id); | |
13002 | memcpy(ppid->id, bp->phys_port_id, ppid->id_len); | |
13003 | ||
13004 | return 0; | |
13005 | } | |
13006 | ||
5f35227e JG |
13007 | static netdev_features_t bnx2x_features_check(struct sk_buff *skb, |
13008 | struct net_device *dev, | |
13009 | netdev_features_t features) | |
51de7bb9 | 13010 | { |
fb134fcb DA |
13011 | /* |
13012 | * A skb with gso_size + header length > 9700 will cause a | |
13013 | * firmware panic. Drop GSO support. | |
13014 | * | |
13015 | * Eventually the upper layer should not pass these packets down. | |
13016 | * | |
13017 | * For speed, if the gso_size is <= 9000, assume there will | |
13018 | * not be 700 bytes of headers and pass it through. Only do a | |
13019 | * full (slow) validation if the gso_size is > 9000. | |
13020 | * | |
13021 | * (Due to the way SKB_BY_FRAGS works this will also do a full | |
13022 | * validation in that case.) | |
13023 | */ | |
13024 | if (unlikely(skb_is_gso(skb) && | |
13025 | (skb_shinfo(skb)->gso_size > 9000) && | |
13026 | !skb_gso_validate_mac_len(skb, 9700))) | |
13027 | features &= ~NETIF_F_GSO_MASK; | |
13028 | ||
8cb65d00 | 13029 | features = vlan_features_check(skb, features); |
5f35227e | 13030 | return vxlan_features_check(skb, features); |
51de7bb9 JS |
13031 | } |
13032 | ||
05cc5a39 YM |
13033 | static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add) |
13034 | { | |
13035 | int rc; | |
13036 | ||
13037 | if (IS_PF(bp)) { | |
13038 | unsigned long ramrod_flags = 0; | |
13039 | ||
13040 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
13041 | rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj, | |
13042 | add, &ramrod_flags); | |
13043 | } else { | |
13044 | rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add); | |
13045 | } | |
13046 | ||
13047 | return rc; | |
13048 | } | |
13049 | ||
a02cc9d3 | 13050 | static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp) |
05cc5a39 YM |
13051 | { |
13052 | struct bnx2x_vlan_entry *vlan; | |
13053 | int rc = 0; | |
13054 | ||
a02cc9d3 | 13055 | /* Configure all non-configured entries */ |
05cc5a39 | 13056 | list_for_each_entry(vlan, &bp->vlan_reg, link) { |
a02cc9d3 | 13057 | if (vlan->hw) |
05cc5a39 YM |
13058 | continue; |
13059 | ||
a02cc9d3 MS |
13060 | if (bp->vlan_cnt >= bp->vlan_credit) |
13061 | return -ENOBUFS; | |
05cc5a39 YM |
13062 | |
13063 | rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true); | |
13064 | if (rc) { | |
a02cc9d3 MS |
13065 | BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid); |
13066 | return rc; | |
05cc5a39 | 13067 | } |
a02cc9d3 MS |
13068 | |
13069 | DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid); | |
13070 | vlan->hw = true; | |
13071 | bp->vlan_cnt++; | |
05cc5a39 YM |
13072 | } |
13073 | ||
a02cc9d3 MS |
13074 | return 0; |
13075 | } | |
13076 | ||
13077 | static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode) | |
13078 | { | |
13079 | bool need_accept_any_vlan; | |
13080 | ||
13081 | need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp); | |
13082 | ||
13083 | if (bp->accept_any_vlan != need_accept_any_vlan) { | |
13084 | bp->accept_any_vlan = need_accept_any_vlan; | |
13085 | DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n", | |
13086 | bp->accept_any_vlan ? "raised" : "cleared"); | |
13087 | if (set_rx_mode) { | |
13088 | if (IS_PF(bp)) | |
13089 | bnx2x_set_rx_mode_inner(bp); | |
13090 | else | |
13091 | bnx2x_vfpf_storm_rx_mode(bp); | |
13092 | } | |
13093 | } | |
13094 | } | |
13095 | ||
13096 | int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp) | |
13097 | { | |
a02cc9d3 MS |
13098 | /* Don't set rx mode here. Our caller will do it. */ |
13099 | bnx2x_vlan_configure(bp, false); | |
13100 | ||
13101 | return 0; | |
05cc5a39 YM |
13102 | } |
13103 | ||
13104 | static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) | |
13105 | { | |
13106 | struct bnx2x *bp = netdev_priv(dev); | |
13107 | struct bnx2x_vlan_entry *vlan; | |
05cc5a39 YM |
13108 | |
13109 | DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid); | |
13110 | ||
13111 | vlan = kmalloc(sizeof(*vlan), GFP_KERNEL); | |
13112 | if (!vlan) | |
13113 | return -ENOMEM; | |
13114 | ||
05cc5a39 | 13115 | vlan->vid = vid; |
a02cc9d3 MS |
13116 | vlan->hw = false; |
13117 | list_add_tail(&vlan->link, &bp->vlan_reg); | |
05cc5a39 | 13118 | |
a02cc9d3 MS |
13119 | if (netif_running(dev)) |
13120 | bnx2x_vlan_configure(bp, true); | |
05cc5a39 | 13121 | |
a02cc9d3 | 13122 | return 0; |
05cc5a39 YM |
13123 | } |
13124 | ||
13125 | static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) | |
13126 | { | |
13127 | struct bnx2x *bp = netdev_priv(dev); | |
13128 | struct bnx2x_vlan_entry *vlan; | |
a02cc9d3 | 13129 | bool found = false; |
05cc5a39 YM |
13130 | int rc = 0; |
13131 | ||
05cc5a39 YM |
13132 | DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid); |
13133 | ||
05cc5a39 | 13134 | list_for_each_entry(vlan, &bp->vlan_reg, link) |
a02cc9d3 MS |
13135 | if (vlan->vid == vid) { |
13136 | found = true; | |
05cc5a39 | 13137 | break; |
a02cc9d3 | 13138 | } |
05cc5a39 | 13139 | |
a02cc9d3 | 13140 | if (!found) { |
05cc5a39 YM |
13141 | BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid); |
13142 | return -EINVAL; | |
13143 | } | |
13144 | ||
a02cc9d3 | 13145 | if (netif_running(dev) && vlan->hw) { |
05cc5a39 | 13146 | rc = __bnx2x_vlan_configure_vid(bp, vid, false); |
a02cc9d3 MS |
13147 | DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid); |
13148 | bp->vlan_cnt--; | |
13149 | } | |
05cc5a39 YM |
13150 | |
13151 | list_del(&vlan->link); | |
13152 | kfree(vlan); | |
13153 | ||
a02cc9d3 MS |
13154 | if (netif_running(dev)) |
13155 | bnx2x_vlan_configure(bp, true); | |
05cc5a39 YM |
13156 | |
13157 | DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc); | |
13158 | ||
13159 | return rc; | |
13160 | } | |
13161 | ||
c64213cd SH |
13162 | static const struct net_device_ops bnx2x_netdev_ops = { |
13163 | .ndo_open = bnx2x_open, | |
13164 | .ndo_stop = bnx2x_close, | |
13165 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 13166 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 13167 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd | 13168 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
614c76df | 13169 | .ndo_validate_addr = bnx2x_validate_addr, |
c64213cd SH |
13170 | .ndo_do_ioctl = bnx2x_ioctl, |
13171 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
13172 | .ndo_fix_features = bnx2x_fix_features, |
13173 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 13174 | .ndo_tx_timeout = bnx2x_tx_timeout, |
05cc5a39 YM |
13175 | .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid, |
13176 | .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid, | |
257ddbda | 13177 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
13178 | .ndo_poll_controller = poll_bnx2x, |
13179 | #endif | |
e4c6734e | 13180 | .ndo_setup_tc = __bnx2x_setup_tc, |
6411280a | 13181 | #ifdef CONFIG_BNX2X_SRIOV |
abc5a021 | 13182 | .ndo_set_vf_mac = bnx2x_set_vf_mac, |
3cdeec22 | 13183 | .ndo_set_vf_vlan = bnx2x_set_vf_vlan, |
3ec9f9ca | 13184 | .ndo_get_vf_config = bnx2x_get_vf_config, |
6411280a | 13185 | #endif |
55c11941 | 13186 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
13187 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, |
13188 | #endif | |
8f20aa57 | 13189 | |
3d7d562c | 13190 | .ndo_get_phys_port_id = bnx2x_get_phys_port_id, |
6495d15a | 13191 | .ndo_set_vf_link_state = bnx2x_set_vf_link_state, |
5f35227e | 13192 | .ndo_features_check = bnx2x_features_check, |
6b352912 AD |
13193 | .ndo_udp_tunnel_add = bnx2x_udp_tunnel_add, |
13194 | .ndo_udp_tunnel_del = bnx2x_udp_tunnel_del, | |
c64213cd SH |
13195 | }; |
13196 | ||
1191cb83 | 13197 | static int bnx2x_set_coherency_mask(struct bnx2x *bp) |
619c5cb6 VZ |
13198 | { |
13199 | struct device *dev = &bp->pdev->dev; | |
13200 | ||
8ceafbfa LT |
13201 | if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 && |
13202 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) { | |
619c5cb6 VZ |
13203 | dev_err(dev, "System does not support DMA, aborting\n"); |
13204 | return -EIO; | |
13205 | } | |
13206 | ||
13207 | return 0; | |
13208 | } | |
13209 | ||
33d8e6a5 YM |
13210 | static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp) |
13211 | { | |
13212 | if (bp->flags & AER_ENABLED) { | |
13213 | pci_disable_pcie_error_reporting(bp->pdev); | |
13214 | bp->flags &= ~AER_ENABLED; | |
13215 | } | |
13216 | } | |
13217 | ||
1ab4434c AE |
13218 | static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, |
13219 | struct net_device *dev, unsigned long board_type) | |
a2fbb9ea | 13220 | { |
a2fbb9ea | 13221 | int rc; |
c22610d0 | 13222 | u32 pci_cfg_dword; |
65087cfe AE |
13223 | bool chip_is_e1x = (board_type == BCM57710 || |
13224 | board_type == BCM57711 || | |
13225 | board_type == BCM57711E); | |
a2fbb9ea ET |
13226 | |
13227 | SET_NETDEV_DEV(dev, &pdev->dev); | |
a2fbb9ea | 13228 | |
34f80b04 EG |
13229 | bp->dev = dev; |
13230 | bp->pdev = pdev; | |
a2fbb9ea ET |
13231 | |
13232 | rc = pci_enable_device(pdev); | |
13233 | if (rc) { | |
cdaa7cb8 VZ |
13234 | dev_err(&bp->pdev->dev, |
13235 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
13236 | goto err_out; |
13237 | } | |
13238 | ||
13239 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
13240 | dev_err(&bp->pdev->dev, |
13241 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
13242 | rc = -ENODEV; |
13243 | goto err_out_disable; | |
13244 | } | |
13245 | ||
1ab4434c AE |
13246 | if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { |
13247 | dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); | |
a2fbb9ea ET |
13248 | rc = -ENODEV; |
13249 | goto err_out_disable; | |
13250 | } | |
13251 | ||
092a5fc9 YR |
13252 | pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); |
13253 | if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == | |
13254 | PCICFG_REVESION_ID_ERROR_VAL) { | |
13255 | pr_err("PCI device error, probably due to fan failure, aborting\n"); | |
13256 | rc = -ENODEV; | |
13257 | goto err_out_disable; | |
13258 | } | |
13259 | ||
34f80b04 EG |
13260 | if (atomic_read(&pdev->enable_cnt) == 1) { |
13261 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
13262 | if (rc) { | |
cdaa7cb8 VZ |
13263 | dev_err(&bp->pdev->dev, |
13264 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
13265 | goto err_out_disable; |
13266 | } | |
a2fbb9ea | 13267 | |
34f80b04 EG |
13268 | pci_set_master(pdev); |
13269 | pci_save_state(pdev); | |
13270 | } | |
a2fbb9ea | 13271 | |
1ab4434c | 13272 | if (IS_PF(bp)) { |
29ed74c3 | 13273 | if (!pdev->pm_cap) { |
1ab4434c AE |
13274 | dev_err(&bp->pdev->dev, |
13275 | "Cannot find power management capability, aborting\n"); | |
13276 | rc = -EIO; | |
13277 | goto err_out_release; | |
13278 | } | |
a2fbb9ea ET |
13279 | } |
13280 | ||
77c98e6a | 13281 | if (!pci_is_pcie(pdev)) { |
51c1a580 | 13282 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
a2fbb9ea ET |
13283 | rc = -EIO; |
13284 | goto err_out_release; | |
13285 | } | |
13286 | ||
619c5cb6 VZ |
13287 | rc = bnx2x_set_coherency_mask(bp); |
13288 | if (rc) | |
a2fbb9ea | 13289 | goto err_out_release; |
a2fbb9ea | 13290 | |
34f80b04 EG |
13291 | dev->mem_start = pci_resource_start(pdev, 0); |
13292 | dev->base_addr = dev->mem_start; | |
13293 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
13294 | |
13295 | dev->irq = pdev->irq; | |
13296 | ||
275f165f | 13297 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 13298 | if (!bp->regview) { |
cdaa7cb8 VZ |
13299 | dev_err(&bp->pdev->dev, |
13300 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
13301 | rc = -ENOMEM; |
13302 | goto err_out_release; | |
13303 | } | |
13304 | ||
c22610d0 AE |
13305 | /* In E1/E1H use pci device function given by kernel. |
13306 | * In E2/E3 read physical function from ME register since these chips | |
13307 | * support Physical Device Assignment where kernel BDF maybe arbitrary | |
13308 | * (depending on hypervisor). | |
13309 | */ | |
2de67439 | 13310 | if (chip_is_e1x) { |
c22610d0 | 13311 | bp->pf_num = PCI_FUNC(pdev->devfn); |
2de67439 YM |
13312 | } else { |
13313 | /* chip is E2/3*/ | |
c22610d0 AE |
13314 | pci_read_config_dword(bp->pdev, |
13315 | PCICFG_ME_REGISTER, &pci_cfg_dword); | |
13316 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> | |
2de67439 | 13317 | ME_REG_ABS_PF_NUM_SHIFT); |
c22610d0 | 13318 | } |
51c1a580 | 13319 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
c22610d0 | 13320 | |
34f80b04 EG |
13321 | /* clean indirect addresses */ |
13322 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
13323 | PCICFG_VENDOR_ID_OFFSET); | |
33d8e6a5 | 13324 | |
da293700 BK |
13325 | /* Set PCIe reset type to fundamental for EEH recovery */ |
13326 | pdev->needs_freset = 1; | |
13327 | ||
33d8e6a5 YM |
13328 | /* AER (Advanced Error reporting) configuration */ |
13329 | rc = pci_enable_pcie_error_reporting(pdev); | |
13330 | if (!rc) | |
13331 | bp->flags |= AER_ENABLED; | |
13332 | else | |
13333 | BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc); | |
13334 | ||
a5c53dbc DK |
13335 | /* |
13336 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
13337 | * is not used by the driver. |
13338 | */ | |
1ab4434c AE |
13339 | if (IS_PF(bp)) { |
13340 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
13341 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
13342 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
13343 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
13344 | ||
13345 | if (chip_is_e1x) { | |
13346 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); | |
13347 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
13348 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
13349 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
13350 | } | |
a5c53dbc | 13351 | |
1ab4434c AE |
13352 | /* Enable internal target-read (in case we are probed after PF |
13353 | * FLR). Must be done prior to any BAR read access. Only for | |
13354 | * 57712 and up | |
13355 | */ | |
13356 | if (!chip_is_e1x) | |
13357 | REG_WR(bp, | |
13358 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
a5c53dbc | 13359 | } |
a2fbb9ea | 13360 | |
34f80b04 | 13361 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 13362 | |
c64213cd | 13363 | dev->netdev_ops = &bnx2x_netdev_ops; |
005a07ba | 13364 | bnx2x_set_ethtool_ops(bp, dev); |
5316bc0b | 13365 | |
01789349 JP |
13366 | dev->priv_flags |= IFF_UNICAST_FLT; |
13367 | ||
66371c44 | 13368 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
621b4d66 DK |
13369 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
13370 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | | |
f646968f | 13371 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX; |
a8e0c246 | 13372 | if (!chip_is_e1x) { |
736c4c1d AD |
13373 | dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | |
13374 | NETIF_F_GSO_IPXIP4 | | |
13375 | NETIF_F_GSO_UDP_TUNNEL | | |
13376 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
13377 | NETIF_F_GSO_PARTIAL; | |
13378 | ||
a848ade4 DK |
13379 | dev->hw_enc_features = |
13380 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | | |
13381 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | | |
7e13318d | 13382 | NETIF_F_GSO_IPXIP4 | |
736c4c1d AD |
13383 | NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | |
13384 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
13385 | NETIF_F_GSO_PARTIAL; | |
13386 | ||
13387 | dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM | | |
13388 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
a848ade4 | 13389 | } |
66371c44 MM |
13390 | |
13391 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
13392 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
13393 | ||
05cc5a39 | 13394 | if (IS_PF(bp)) { |
ab6d7846 | 13395 | if (chip_is_e1x) |
05cc5a39 YM |
13396 | bp->accept_any_vlan = true; |
13397 | else | |
13398 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
05cc5a39 | 13399 | } |
83bd9eb8 MS |
13400 | /* For VF we'll know whether to enable VLAN filtering after |
13401 | * getting a response to CHANNEL_TLV_ACQUIRE from PF. | |
13402 | */ | |
05cc5a39 | 13403 | |
f646968f | 13404 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; |
edd31476 | 13405 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 13406 | |
538dd2e3 MB |
13407 | /* Add Loopback capability to the device */ |
13408 | dev->hw_features |= NETIF_F_LOOPBACK; | |
13409 | ||
98507672 | 13410 | #ifdef BCM_DCBNL |
785b9b1a SR |
13411 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
13412 | #endif | |
13413 | ||
e1c6dcca JW |
13414 | /* MTU range, 46 - 9600 */ |
13415 | dev->min_mtu = ETH_MIN_PACKET_SIZE; | |
13416 | dev->max_mtu = ETH_MAX_JUMBO_PACKET_SIZE; | |
13417 | ||
01cd4528 EG |
13418 | /* get_port_hwinfo() will set prtad and mmds properly */ |
13419 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
13420 | bp->mdio.mmds = 0; | |
13421 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
13422 | bp->mdio.dev = dev; | |
13423 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
13424 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
13425 | ||
a2fbb9ea ET |
13426 | return 0; |
13427 | ||
a2fbb9ea | 13428 | err_out_release: |
34f80b04 EG |
13429 | if (atomic_read(&pdev->enable_cnt) == 1) |
13430 | pci_release_regions(pdev); | |
a2fbb9ea ET |
13431 | |
13432 | err_out_disable: | |
13433 | pci_disable_device(pdev); | |
a2fbb9ea ET |
13434 | |
13435 | err_out: | |
13436 | return rc; | |
13437 | } | |
13438 | ||
6891dd25 | 13439 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 13440 | { |
37f9ce62 | 13441 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
13442 | struct bnx2x_fw_file_hdr *fw_hdr; |
13443 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 13444 | u32 offset, len, num_ops; |
86564c3f | 13445 | __be16 *ops_offsets; |
94a78b79 | 13446 | int i; |
37f9ce62 | 13447 | const u8 *fw_ver; |
94a78b79 | 13448 | |
51c1a580 MS |
13449 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
13450 | BNX2X_ERR("Wrong FW size\n"); | |
94a78b79 | 13451 | return -EINVAL; |
51c1a580 | 13452 | } |
94a78b79 VZ |
13453 | |
13454 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
13455 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
13456 | ||
13457 | /* Make sure none of the offsets and sizes make us read beyond | |
13458 | * the end of the firmware data */ | |
13459 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
13460 | offset = be32_to_cpu(sections[i].offset); | |
13461 | len = be32_to_cpu(sections[i].len); | |
13462 | if (offset + len > firmware->size) { | |
51c1a580 | 13463 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
94a78b79 VZ |
13464 | return -EINVAL; |
13465 | } | |
13466 | } | |
13467 | ||
13468 | /* Likewise for the init_ops offsets */ | |
13469 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
86564c3f | 13470 | ops_offsets = (__force __be16 *)(firmware->data + offset); |
94a78b79 VZ |
13471 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); |
13472 | ||
13473 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
13474 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
51c1a580 | 13475 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
94a78b79 VZ |
13476 | return -EINVAL; |
13477 | } | |
13478 | } | |
13479 | ||
13480 | /* Check FW version */ | |
13481 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
13482 | fw_ver = firmware->data + offset; | |
13483 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
13484 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
13485 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
13486 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
51c1a580 MS |
13487 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
13488 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], | |
13489 | BCM_5710_FW_MAJOR_VERSION, | |
94a78b79 VZ |
13490 | BCM_5710_FW_MINOR_VERSION, |
13491 | BCM_5710_FW_REVISION_VERSION, | |
13492 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 13493 | return -EINVAL; |
94a78b79 VZ |
13494 | } |
13495 | ||
13496 | return 0; | |
13497 | } | |
13498 | ||
1191cb83 | 13499 | static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 13500 | { |
ab6ad5a4 EG |
13501 | const __be32 *source = (const __be32 *)_source; |
13502 | u32 *target = (u32 *)_target; | |
94a78b79 | 13503 | u32 i; |
94a78b79 VZ |
13504 | |
13505 | for (i = 0; i < n/4; i++) | |
13506 | target[i] = be32_to_cpu(source[i]); | |
13507 | } | |
13508 | ||
13509 | /* | |
13510 | Ops array is stored in the following format: | |
13511 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
13512 | */ | |
1191cb83 | 13513 | static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 13514 | { |
ab6ad5a4 EG |
13515 | const __be32 *source = (const __be32 *)_source; |
13516 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 13517 | u32 i, j, tmp; |
94a78b79 | 13518 | |
ab6ad5a4 | 13519 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
13520 | tmp = be32_to_cpu(source[j]); |
13521 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
13522 | target[i].offset = tmp & 0xffffff; |
13523 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
13524 | } |
13525 | } | |
ab6ad5a4 | 13526 | |
1aa8b471 | 13527 | /* IRO array is stored in the following format: |
523224a3 DK |
13528 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } |
13529 | */ | |
1191cb83 | 13530 | static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) |
523224a3 DK |
13531 | { |
13532 | const __be32 *source = (const __be32 *)_source; | |
13533 | struct iro *target = (struct iro *)_target; | |
13534 | u32 i, j, tmp; | |
13535 | ||
13536 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
13537 | target[i].base = be32_to_cpu(source[j]); | |
13538 | j++; | |
13539 | tmp = be32_to_cpu(source[j]); | |
13540 | target[i].m1 = (tmp >> 16) & 0xffff; | |
13541 | target[i].m2 = tmp & 0xffff; | |
13542 | j++; | |
13543 | tmp = be32_to_cpu(source[j]); | |
13544 | target[i].m3 = (tmp >> 16) & 0xffff; | |
13545 | target[i].size = tmp & 0xffff; | |
13546 | j++; | |
13547 | } | |
13548 | } | |
13549 | ||
1191cb83 | 13550 | static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 13551 | { |
ab6ad5a4 EG |
13552 | const __be16 *source = (const __be16 *)_source; |
13553 | u16 *target = (u16 *)_target; | |
94a78b79 | 13554 | u32 i; |
94a78b79 VZ |
13555 | |
13556 | for (i = 0; i < n/2; i++) | |
13557 | target[i] = be16_to_cpu(source[i]); | |
13558 | } | |
13559 | ||
7995c64e JP |
13560 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
13561 | do { \ | |
13562 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
13563 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
e404decb | 13564 | if (!bp->arr) \ |
7995c64e | 13565 | goto lbl; \ |
7995c64e JP |
13566 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
13567 | (u8 *)bp->arr, len); \ | |
13568 | } while (0) | |
94a78b79 | 13569 | |
3b603066 | 13570 | static int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 13571 | { |
c0ea452e | 13572 | const char *fw_file_name; |
94a78b79 | 13573 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 13574 | int rc; |
94a78b79 | 13575 | |
c0ea452e MS |
13576 | if (bp->firmware) |
13577 | return 0; | |
94a78b79 | 13578 | |
c0ea452e MS |
13579 | if (CHIP_IS_E1(bp)) |
13580 | fw_file_name = FW_FILE_NAME_E1; | |
13581 | else if (CHIP_IS_E1H(bp)) | |
13582 | fw_file_name = FW_FILE_NAME_E1H; | |
13583 | else if (!CHIP_IS_E1x(bp)) | |
13584 | fw_file_name = FW_FILE_NAME_E2; | |
13585 | else { | |
13586 | BNX2X_ERR("Unsupported chip revision\n"); | |
13587 | return -EINVAL; | |
13588 | } | |
13589 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); | |
94a78b79 | 13590 | |
c0ea452e MS |
13591 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
13592 | if (rc) { | |
13593 | BNX2X_ERR("Can't load firmware file %s\n", | |
13594 | fw_file_name); | |
13595 | goto request_firmware_exit; | |
13596 | } | |
eb2afd4a | 13597 | |
c0ea452e MS |
13598 | rc = bnx2x_check_firmware(bp); |
13599 | if (rc) { | |
13600 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); | |
13601 | goto request_firmware_exit; | |
94a78b79 VZ |
13602 | } |
13603 | ||
13604 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
13605 | ||
13606 | /* Initialize the pointers to the init arrays */ | |
13607 | /* Blob */ | |
005f7e68 | 13608 | rc = -ENOMEM; |
94a78b79 VZ |
13609 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); |
13610 | ||
13611 | /* Opcodes */ | |
13612 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
13613 | ||
13614 | /* Offsets */ | |
ab6ad5a4 EG |
13615 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
13616 | be16_to_cpu_n); | |
94a78b79 VZ |
13617 | |
13618 | /* STORMs firmware */ | |
573f2035 EG |
13619 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
13620 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
13621 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
13622 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
13623 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
13624 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
13625 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
13626 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
13627 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
13628 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
13629 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
13630 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
13631 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
13632 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
13633 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
13634 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
13635 | /* IRO */ |
13636 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
13637 | |
13638 | return 0; | |
ab6ad5a4 | 13639 | |
523224a3 DK |
13640 | iro_alloc_err: |
13641 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
13642 | init_offsets_alloc_err: |
13643 | kfree(bp->init_ops); | |
13644 | init_ops_alloc_err: | |
13645 | kfree(bp->init_data); | |
13646 | request_firmware_exit: | |
13647 | release_firmware(bp->firmware); | |
127d0a19 | 13648 | bp->firmware = NULL; |
94a78b79 VZ |
13649 | |
13650 | return rc; | |
13651 | } | |
13652 | ||
619c5cb6 VZ |
13653 | static void bnx2x_release_firmware(struct bnx2x *bp) |
13654 | { | |
13655 | kfree(bp->init_ops_offsets); | |
13656 | kfree(bp->init_ops); | |
13657 | kfree(bp->init_data); | |
13658 | release_firmware(bp->firmware); | |
eb2afd4a | 13659 | bp->firmware = NULL; |
619c5cb6 VZ |
13660 | } |
13661 | ||
619c5cb6 VZ |
13662 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { |
13663 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
13664 | .init_hw_cmn = bnx2x_init_hw_common, | |
13665 | .init_hw_port = bnx2x_init_hw_port, | |
13666 | .init_hw_func = bnx2x_init_hw_func, | |
13667 | ||
13668 | .reset_hw_cmn = bnx2x_reset_common, | |
13669 | .reset_hw_port = bnx2x_reset_port, | |
13670 | .reset_hw_func = bnx2x_reset_func, | |
13671 | ||
13672 | .gunzip_init = bnx2x_gunzip_init, | |
13673 | .gunzip_end = bnx2x_gunzip_end, | |
13674 | ||
13675 | .init_fw = bnx2x_init_firmware, | |
13676 | .release_fw = bnx2x_release_firmware, | |
13677 | }; | |
13678 | ||
13679 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
13680 | { | |
13681 | /* Prepare DMAE related driver resources */ | |
13682 | bnx2x_setup_dmae(bp); | |
13683 | ||
13684 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
13685 | bnx2x_sp(bp, func_rdata), | |
13686 | bnx2x_sp_mapping(bp, func_rdata), | |
a3348722 BW |
13687 | bnx2x_sp(bp, func_afex_rdata), |
13688 | bnx2x_sp_mapping(bp, func_afex_rdata), | |
619c5cb6 VZ |
13689 | &bnx2x_func_sp_drv); |
13690 | } | |
13691 | ||
13692 | /* must be called after sriov-enable */ | |
1191cb83 | 13693 | static int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 13694 | { |
37ae41a9 | 13695 | int cid_count = BNX2X_L2_MAX_CID(bp); |
94a78b79 | 13696 | |
290ca2bb AE |
13697 | if (IS_SRIOV(bp)) |
13698 | cid_count += BNX2X_VF_CIDS; | |
13699 | ||
55c11941 MS |
13700 | if (CNIC_SUPPORT(bp)) |
13701 | cid_count += CNIC_CID_MAX; | |
290ca2bb | 13702 | |
523224a3 DK |
13703 | return roundup(cid_count, QM_CID_ROUND); |
13704 | } | |
f85582f8 | 13705 | |
619c5cb6 | 13706 | /** |
6383c0b3 | 13707 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
13708 | * |
13709 | * @dev: pci device | |
13710 | * | |
13711 | */ | |
60cad4e6 | 13712 | static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt) |
619c5cb6 | 13713 | { |
ae2104be | 13714 | int index; |
1ab4434c | 13715 | u16 control = 0; |
619c5cb6 | 13716 | |
6383c0b3 AE |
13717 | /* |
13718 | * If MSI-X is not supported - return number of SBs needed to support | |
13719 | * one fast path queue: one FP queue + SB for CNIC | |
13720 | */ | |
ae2104be | 13721 | if (!pdev->msix_cap) { |
1ab4434c | 13722 | dev_info(&pdev->dev, "no msix capability found\n"); |
55c11941 | 13723 | return 1 + cnic_cnt; |
1ab4434c AE |
13724 | } |
13725 | dev_info(&pdev->dev, "msix capability found\n"); | |
619c5cb6 | 13726 | |
6383c0b3 AE |
13727 | /* |
13728 | * The value in the PCI configuration space is the index of the last | |
13729 | * entry, namely one less than the actual size of the table, which is | |
13730 | * exactly what we want to return from this function: number of all SBs | |
13731 | * without the default SB. | |
1ab4434c | 13732 | * For VFs there is no default SB, then we return (index+1). |
6383c0b3 | 13733 | */ |
73413ffa | 13734 | pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control); |
619c5cb6 | 13735 | |
1ab4434c | 13736 | index = control & PCI_MSIX_FLAGS_QSIZE; |
4bd9b0ff | 13737 | |
60cad4e6 | 13738 | return index; |
1ab4434c | 13739 | } |
523224a3 | 13740 | |
1ab4434c AE |
13741 | static int set_max_cos_est(int chip_id) |
13742 | { | |
13743 | switch (chip_id) { | |
f2e0899f DK |
13744 | case BCM57710: |
13745 | case BCM57711: | |
13746 | case BCM57711E: | |
1ab4434c | 13747 | return BNX2X_MULTI_TX_COS_E1X; |
f2e0899f | 13748 | case BCM57712: |
619c5cb6 | 13749 | case BCM57712_MF: |
1ab4434c | 13750 | return BNX2X_MULTI_TX_COS_E2_E3A0; |
619c5cb6 VZ |
13751 | case BCM57800: |
13752 | case BCM57800_MF: | |
13753 | case BCM57810: | |
13754 | case BCM57810_MF: | |
c3def943 YM |
13755 | case BCM57840_4_10: |
13756 | case BCM57840_2_20: | |
1ab4434c | 13757 | case BCM57840_O: |
c3def943 | 13758 | case BCM57840_MFO: |
619c5cb6 | 13759 | case BCM57840_MF: |
7e8e02df BW |
13760 | case BCM57811: |
13761 | case BCM57811_MF: | |
1ab4434c | 13762 | return BNX2X_MULTI_TX_COS_E3B0; |
b1239723 YM |
13763 | case BCM57712_VF: |
13764 | case BCM57800_VF: | |
13765 | case BCM57810_VF: | |
13766 | case BCM57840_VF: | |
13767 | case BCM57811_VF: | |
1ab4434c | 13768 | return 1; |
f2e0899f | 13769 | default: |
1ab4434c | 13770 | pr_err("Unknown board_type (%d), aborting\n", chip_id); |
870634b0 | 13771 | return -ENODEV; |
f2e0899f | 13772 | } |
1ab4434c | 13773 | } |
f2e0899f | 13774 | |
1ab4434c AE |
13775 | static int set_is_vf(int chip_id) |
13776 | { | |
13777 | switch (chip_id) { | |
13778 | case BCM57712_VF: | |
13779 | case BCM57800_VF: | |
13780 | case BCM57810_VF: | |
13781 | case BCM57840_VF: | |
13782 | case BCM57811_VF: | |
13783 | return true; | |
13784 | default: | |
13785 | return false; | |
13786 | } | |
13787 | } | |
6383c0b3 | 13788 | |
eeed018c MK |
13789 | /* nig_tsgen registers relative address */ |
13790 | #define tsgen_ctrl 0x0 | |
13791 | #define tsgen_freecount 0x10 | |
13792 | #define tsgen_synctime_t0 0x20 | |
13793 | #define tsgen_offset_t0 0x28 | |
13794 | #define tsgen_drift_t0 0x30 | |
13795 | #define tsgen_synctime_t1 0x58 | |
13796 | #define tsgen_offset_t1 0x60 | |
13797 | #define tsgen_drift_t1 0x68 | |
13798 | ||
13799 | /* FW workaround for setting drift */ | |
13800 | static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir, | |
13801 | int best_val, int best_period) | |
13802 | { | |
13803 | struct bnx2x_func_state_params func_params = {NULL}; | |
13804 | struct bnx2x_func_set_timesync_params *set_timesync_params = | |
13805 | &func_params.params.set_timesync; | |
13806 | ||
13807 | /* Prepare parameters for function state transitions */ | |
13808 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
13809 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
13810 | ||
13811 | func_params.f_obj = &bp->func_obj; | |
13812 | func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; | |
13813 | ||
13814 | /* Function parameters */ | |
13815 | set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET; | |
13816 | set_timesync_params->offset_cmd = TS_OFFSET_KEEP; | |
13817 | set_timesync_params->add_sub_drift_adjust_value = | |
13818 | drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE; | |
13819 | set_timesync_params->drift_adjust_value = best_val; | |
13820 | set_timesync_params->drift_adjust_period = best_period; | |
13821 | ||
13822 | return bnx2x_func_state_change(bp, &func_params); | |
13823 | } | |
13824 | ||
13825 | static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) | |
13826 | { | |
13827 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13828 | int rc; | |
13829 | int drift_dir = 1; | |
13830 | int val, period, period1, period2, dif, dif1, dif2; | |
13831 | int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0; | |
13832 | ||
13833 | DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb); | |
13834 | ||
13835 | if (!netif_running(bp->dev)) { | |
13836 | DP(BNX2X_MSG_PTP, | |
13837 | "PTP adjfreq called while the interface is down\n"); | |
466e8bf1 | 13838 | return -ENETDOWN; |
eeed018c MK |
13839 | } |
13840 | ||
13841 | if (ppb < 0) { | |
13842 | ppb = -ppb; | |
13843 | drift_dir = 0; | |
13844 | } | |
13845 | ||
13846 | if (ppb == 0) { | |
13847 | best_val = 1; | |
13848 | best_period = 0x1FFFFFF; | |
13849 | } else if (ppb >= BNX2X_MAX_PHC_DRIFT) { | |
13850 | best_val = 31; | |
13851 | best_period = 1; | |
13852 | } else { | |
13853 | /* Changed not to allow val = 8, 16, 24 as these values | |
13854 | * are not supported in workaround. | |
13855 | */ | |
13856 | for (val = 0; val <= 31; val++) { | |
13857 | if ((val & 0x7) == 0) | |
13858 | continue; | |
13859 | period1 = val * 1000000 / ppb; | |
13860 | period2 = period1 + 1; | |
13861 | if (period1 != 0) | |
13862 | dif1 = ppb - (val * 1000000 / period1); | |
13863 | else | |
13864 | dif1 = BNX2X_MAX_PHC_DRIFT; | |
13865 | if (dif1 < 0) | |
13866 | dif1 = -dif1; | |
13867 | dif2 = ppb - (val * 1000000 / period2); | |
13868 | if (dif2 < 0) | |
13869 | dif2 = -dif2; | |
13870 | dif = (dif1 < dif2) ? dif1 : dif2; | |
13871 | period = (dif1 < dif2) ? period1 : period2; | |
13872 | if (dif < best_dif) { | |
13873 | best_dif = dif; | |
13874 | best_val = val; | |
13875 | best_period = period; | |
13876 | } | |
13877 | } | |
13878 | } | |
13879 | ||
13880 | rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val, | |
13881 | best_period); | |
13882 | if (rc) { | |
13883 | BNX2X_ERR("Failed to set drift\n"); | |
13884 | return -EFAULT; | |
13885 | } | |
13886 | ||
bf27c353 | 13887 | DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val, |
eeed018c MK |
13888 | best_period); |
13889 | ||
13890 | return 0; | |
13891 | } | |
13892 | ||
13893 | static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) | |
13894 | { | |
13895 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
eeed018c | 13896 | |
466e8bf1 MS |
13897 | if (!netif_running(bp->dev)) { |
13898 | DP(BNX2X_MSG_PTP, | |
13899 | "PTP adjtime called while the interface is down\n"); | |
13900 | return -ENETDOWN; | |
13901 | } | |
13902 | ||
eeed018c MK |
13903 | DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta); |
13904 | ||
2e5601f9 | 13905 | timecounter_adjtime(&bp->timecounter, delta); |
eeed018c MK |
13906 | |
13907 | return 0; | |
13908 | } | |
13909 | ||
5d45186b | 13910 | static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) |
eeed018c MK |
13911 | { |
13912 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13913 | u64 ns; | |
eeed018c | 13914 | |
466e8bf1 MS |
13915 | if (!netif_running(bp->dev)) { |
13916 | DP(BNX2X_MSG_PTP, | |
13917 | "PTP gettime called while the interface is down\n"); | |
13918 | return -ENETDOWN; | |
13919 | } | |
13920 | ||
eeed018c MK |
13921 | ns = timecounter_read(&bp->timecounter); |
13922 | ||
13923 | DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns); | |
13924 | ||
f7dcdefe | 13925 | *ts = ns_to_timespec64(ns); |
eeed018c MK |
13926 | |
13927 | return 0; | |
13928 | } | |
13929 | ||
13930 | static int bnx2x_ptp_settime(struct ptp_clock_info *ptp, | |
5d45186b | 13931 | const struct timespec64 *ts) |
eeed018c MK |
13932 | { |
13933 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13934 | u64 ns; | |
13935 | ||
466e8bf1 MS |
13936 | if (!netif_running(bp->dev)) { |
13937 | DP(BNX2X_MSG_PTP, | |
13938 | "PTP settime called while the interface is down\n"); | |
13939 | return -ENETDOWN; | |
13940 | } | |
13941 | ||
f7dcdefe | 13942 | ns = timespec64_to_ns(ts); |
eeed018c MK |
13943 | |
13944 | DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns); | |
13945 | ||
13946 | /* Re-init the timecounter */ | |
13947 | timecounter_init(&bp->timecounter, &bp->cyclecounter, ns); | |
13948 | ||
13949 | return 0; | |
13950 | } | |
13951 | ||
13952 | /* Enable (or disable) ancillary features of the phc subsystem */ | |
13953 | static int bnx2x_ptp_enable(struct ptp_clock_info *ptp, | |
13954 | struct ptp_clock_request *rq, int on) | |
13955 | { | |
13956 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13957 | ||
13958 | BNX2X_ERR("PHC ancillary features are not supported\n"); | |
13959 | return -ENOTSUPP; | |
13960 | } | |
13961 | ||
1444c301 | 13962 | static void bnx2x_register_phc(struct bnx2x *bp) |
eeed018c MK |
13963 | { |
13964 | /* Fill the ptp_clock_info struct and register PTP clock*/ | |
13965 | bp->ptp_clock_info.owner = THIS_MODULE; | |
13966 | snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name); | |
13967 | bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */ | |
13968 | bp->ptp_clock_info.n_alarm = 0; | |
13969 | bp->ptp_clock_info.n_ext_ts = 0; | |
13970 | bp->ptp_clock_info.n_per_out = 0; | |
13971 | bp->ptp_clock_info.pps = 0; | |
13972 | bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq; | |
13973 | bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime; | |
5d45186b RC |
13974 | bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime; |
13975 | bp->ptp_clock_info.settime64 = bnx2x_ptp_settime; | |
eeed018c MK |
13976 | bp->ptp_clock_info.enable = bnx2x_ptp_enable; |
13977 | ||
13978 | bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev); | |
13979 | if (IS_ERR(bp->ptp_clock)) { | |
13980 | bp->ptp_clock = NULL; | |
13981 | BNX2X_ERR("PTP clock registeration failed\n"); | |
13982 | } | |
13983 | } | |
13984 | ||
1ab4434c AE |
13985 | static int bnx2x_init_one(struct pci_dev *pdev, |
13986 | const struct pci_device_id *ent) | |
13987 | { | |
13988 | struct net_device *dev = NULL; | |
13989 | struct bnx2x *bp; | |
b91e1a1a YM |
13990 | enum pcie_link_width pcie_width; |
13991 | enum pci_bus_speed pcie_speed; | |
1ab4434c AE |
13992 | int rc, max_non_def_sbs; |
13993 | int rx_count, tx_count, rss_count, doorbell_size; | |
13994 | int max_cos_est; | |
13995 | bool is_vf; | |
13996 | int cnic_cnt; | |
13997 | ||
12a8541d YM |
13998 | /* Management FW 'remembers' living interfaces. Allow it some time |
13999 | * to forget previously living interfaces, allowing a proper re-load. | |
14000 | */ | |
cd9c3997 MS |
14001 | if (is_kdump_kernel()) { |
14002 | ktime_t now = ktime_get_boottime(); | |
14003 | ktime_t fw_ready_time = ktime_set(5, 0); | |
14004 | ||
14005 | if (ktime_before(now, fw_ready_time)) | |
14006 | msleep(ktime_ms_delta(fw_ready_time, now)); | |
14007 | } | |
12a8541d | 14008 | |
1ab4434c AE |
14009 | /* An estimated maximum supported CoS number according to the chip |
14010 | * version. | |
14011 | * We will try to roughly estimate the maximum number of CoSes this chip | |
14012 | * may support in order to minimize the memory allocated for Tx | |
14013 | * netdev_queue's. This number will be accurately calculated during the | |
14014 | * initialization of bp->max_cos based on the chip versions AND chip | |
14015 | * revision in the bnx2x_init_bp(). | |
14016 | */ | |
14017 | max_cos_est = set_max_cos_est(ent->driver_data); | |
14018 | if (max_cos_est < 0) | |
14019 | return max_cos_est; | |
14020 | is_vf = set_is_vf(ent->driver_data); | |
14021 | cnic_cnt = is_vf ? 0 : 1; | |
14022 | ||
60cad4e6 AE |
14023 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt); |
14024 | ||
14025 | /* add another SB for VF as it has no default SB */ | |
14026 | max_non_def_sbs += is_vf ? 1 : 0; | |
6383c0b3 AE |
14027 | |
14028 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
60cad4e6 | 14029 | rss_count = max_non_def_sbs - cnic_cnt; |
1ab4434c AE |
14030 | |
14031 | if (rss_count < 1) | |
14032 | return -EINVAL; | |
6383c0b3 AE |
14033 | |
14034 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
55c11941 | 14035 | rx_count = rss_count + cnic_cnt; |
6383c0b3 | 14036 | |
1ab4434c | 14037 | /* Maximum number of netdev Tx queues: |
37ae41a9 | 14038 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 |
6383c0b3 | 14039 | */ |
55c11941 | 14040 | tx_count = rss_count * max_cos_est + cnic_cnt; |
f85582f8 | 14041 | |
a2fbb9ea | 14042 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 14043 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
41de8d4c | 14044 | if (!dev) |
a2fbb9ea ET |
14045 | return -ENOMEM; |
14046 | ||
a2fbb9ea | 14047 | bp = netdev_priv(dev); |
a2fbb9ea | 14048 | |
1ab4434c AE |
14049 | bp->flags = 0; |
14050 | if (is_vf) | |
14051 | bp->flags |= IS_VF_FLAG; | |
14052 | ||
6383c0b3 | 14053 | bp->igu_sb_cnt = max_non_def_sbs; |
1ab4434c | 14054 | bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; |
6383c0b3 | 14055 | bp->msg_enable = debug; |
55c11941 | 14056 | bp->cnic_support = cnic_cnt; |
4bd9b0ff | 14057 | bp->cnic_probe = bnx2x_cnic_probe; |
55c11941 | 14058 | |
6383c0b3 | 14059 | pci_set_drvdata(pdev, dev); |
523224a3 | 14060 | |
1ab4434c | 14061 | rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); |
a2fbb9ea ET |
14062 | if (rc < 0) { |
14063 | free_netdev(dev); | |
14064 | return rc; | |
14065 | } | |
14066 | ||
1ab4434c AE |
14067 | BNX2X_DEV_INFO("This is a %s function\n", |
14068 | IS_PF(bp) ? "physical" : "virtual"); | |
55c11941 | 14069 | BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); |
1ab4434c | 14070 | BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); |
60aa0509 | 14071 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
2de67439 | 14072 | tx_count, rx_count); |
60aa0509 | 14073 | |
34f80b04 | 14074 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
14075 | if (rc) |
14076 | goto init_one_exit; | |
14077 | ||
1ab4434c AE |
14078 | /* Map doorbells here as we need the real value of bp->max_cos which |
14079 | * is initialized in bnx2x_init_bp() to determine the number of | |
14080 | * l2 connections. | |
6383c0b3 | 14081 | */ |
1ab4434c | 14082 | if (IS_VF(bp)) { |
1d6f3cd8 | 14083 | bp->doorbells = bnx2x_vf_doorbells(bp); |
6411280a AE |
14084 | rc = bnx2x_vf_pci_alloc(bp); |
14085 | if (rc) | |
bae5499c | 14086 | goto init_one_freemem; |
1ab4434c AE |
14087 | } else { |
14088 | doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); | |
14089 | if (doorbell_size > pci_resource_len(pdev, 2)) { | |
14090 | dev_err(&bp->pdev->dev, | |
14091 | "Cannot map doorbells, bar size too small, aborting\n"); | |
14092 | rc = -ENOMEM; | |
bae5499c | 14093 | goto init_one_freemem; |
1ab4434c AE |
14094 | } |
14095 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), | |
14096 | doorbell_size); | |
37ae41a9 | 14097 | } |
6383c0b3 AE |
14098 | if (!bp->doorbells) { |
14099 | dev_err(&bp->pdev->dev, | |
14100 | "Cannot map doorbell space, aborting\n"); | |
14101 | rc = -ENOMEM; | |
bae5499c | 14102 | goto init_one_freemem; |
6383c0b3 AE |
14103 | } |
14104 | ||
be1f1ffa AE |
14105 | if (IS_VF(bp)) { |
14106 | rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); | |
14107 | if (rc) | |
bae5499c | 14108 | goto init_one_freemem; |
83bd9eb8 MS |
14109 | |
14110 | #ifdef CONFIG_BNX2X_SRIOV | |
14111 | /* VF with OLD Hypervisor or old PF do not support filtering */ | |
14112 | if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) { | |
14113 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
14114 | dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
14115 | } | |
14116 | #endif | |
be1f1ffa AE |
14117 | } |
14118 | ||
3c76feff AE |
14119 | /* Enable SRIOV if capability found in configuration space */ |
14120 | rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); | |
290ca2bb | 14121 | if (rc) |
bae5499c | 14122 | goto init_one_freemem; |
290ca2bb | 14123 | |
523224a3 | 14124 | /* calc qm_cid_count */ |
6383c0b3 | 14125 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
1ab4434c | 14126 | BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); |
523224a3 | 14127 | |
55c11941 | 14128 | /* disable FCOE L2 queue for E1x*/ |
62ac0dc9 | 14129 | if (CHIP_IS_E1x(bp)) |
ec6ba945 VZ |
14130 | bp->flags |= NO_FCOE_FLAG; |
14131 | ||
0e8d2ec5 MS |
14132 | /* Set bp->num_queues for MSI-X mode*/ |
14133 | bnx2x_set_num_queues(bp); | |
14134 | ||
25985edc | 14135 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
0e8d2ec5 | 14136 | * needed. |
d6214d7a | 14137 | */ |
1ab4434c AE |
14138 | rc = bnx2x_set_int_mode(bp); |
14139 | if (rc) { | |
14140 | dev_err(&pdev->dev, "Cannot set interrupts\n"); | |
bae5499c | 14141 | goto init_one_freemem; |
1ab4434c | 14142 | } |
04c46736 | 14143 | BNX2X_DEV_INFO("set interrupts successfully\n"); |
d6214d7a | 14144 | |
1ab4434c | 14145 | /* register the net device */ |
b340007f VZ |
14146 | rc = register_netdev(dev); |
14147 | if (rc) { | |
14148 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
bae5499c | 14149 | goto init_one_freemem; |
b340007f | 14150 | } |
1ab4434c | 14151 | BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); |
b340007f | 14152 | |
ec6ba945 VZ |
14153 | if (!NO_FCOE(bp)) { |
14154 | /* Add storage MAC address */ | |
14155 | rtnl_lock(); | |
14156 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
14157 | rtnl_unlock(); | |
14158 | } | |
b91e1a1a YM |
14159 | if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) || |
14160 | pcie_speed == PCI_SPEED_UNKNOWN || | |
14161 | pcie_width == PCIE_LNK_WIDTH_UNKNOWN) | |
14162 | BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n"); | |
14163 | else | |
14164 | BNX2X_DEV_INFO( | |
14165 | "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", | |
ca1ee4b2 DK |
14166 | board_info[ent->driver_data].name, |
14167 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
14168 | pcie_width, | |
b91e1a1a YM |
14169 | pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" : |
14170 | pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" : | |
14171 | pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" : | |
ca1ee4b2 DK |
14172 | "Unknown", |
14173 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
c016201c | 14174 | |
eeed018c MK |
14175 | bnx2x_register_phc(bp); |
14176 | ||
230d00eb YM |
14177 | if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) |
14178 | bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED); | |
14179 | ||
a2fbb9ea | 14180 | return 0; |
34f80b04 | 14181 | |
bae5499c VK |
14182 | init_one_freemem: |
14183 | bnx2x_free_mem_bp(bp); | |
14184 | ||
34f80b04 | 14185 | init_one_exit: |
33d8e6a5 YM |
14186 | bnx2x_disable_pcie_error_reporting(bp); |
14187 | ||
34f80b04 EG |
14188 | if (bp->regview) |
14189 | iounmap(bp->regview); | |
14190 | ||
1ab4434c | 14191 | if (IS_PF(bp) && bp->doorbells) |
34f80b04 EG |
14192 | iounmap(bp->doorbells); |
14193 | ||
14194 | free_netdev(dev); | |
14195 | ||
14196 | if (atomic_read(&pdev->enable_cnt) == 1) | |
14197 | pci_release_regions(pdev); | |
14198 | ||
14199 | pci_disable_device(pdev); | |
34f80b04 EG |
14200 | |
14201 | return rc; | |
a2fbb9ea ET |
14202 | } |
14203 | ||
b030ed2f YM |
14204 | static void __bnx2x_remove(struct pci_dev *pdev, |
14205 | struct net_device *dev, | |
14206 | struct bnx2x *bp, | |
14207 | bool remove_netdev) | |
a2fbb9ea | 14208 | { |
eeed018c MK |
14209 | if (bp->ptp_clock) { |
14210 | ptp_clock_unregister(bp->ptp_clock); | |
14211 | bp->ptp_clock = NULL; | |
14212 | } | |
14213 | ||
ec6ba945 VZ |
14214 | /* Delete storage MAC address */ |
14215 | if (!NO_FCOE(bp)) { | |
14216 | rtnl_lock(); | |
14217 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
14218 | rtnl_unlock(); | |
14219 | } | |
ec6ba945 | 14220 | |
98507672 SR |
14221 | #ifdef BCM_DCBNL |
14222 | /* Delete app tlvs from dcbnl */ | |
14223 | bnx2x_dcbnl_update_applist(bp, true); | |
14224 | #endif | |
14225 | ||
a6d3a5ba BW |
14226 | if (IS_PF(bp) && |
14227 | !BP_NOMCP(bp) && | |
14228 | (bp->flags & BC_SUPPORTS_RMMOD_CMD)) | |
14229 | bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); | |
14230 | ||
b030ed2f YM |
14231 | /* Close the interface - either directly or implicitly */ |
14232 | if (remove_netdev) { | |
14233 | unregister_netdev(dev); | |
14234 | } else { | |
14235 | rtnl_lock(); | |
6ef5a92c | 14236 | dev_close(dev); |
b030ed2f YM |
14237 | rtnl_unlock(); |
14238 | } | |
a2fbb9ea | 14239 | |
78c3bcc5 AE |
14240 | bnx2x_iov_remove_one(bp); |
14241 | ||
084d6cbb | 14242 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
04860eb7 | 14243 | if (IS_PF(bp)) { |
1ab4434c | 14244 | bnx2x_set_power_state(bp, PCI_D0); |
230d00eb | 14245 | bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED); |
084d6cbb | 14246 | |
04860eb7 MC |
14247 | /* Set endianity registers to reset values in case next driver |
14248 | * boots in different endianty environment. | |
14249 | */ | |
14250 | bnx2x_reset_endianity(bp); | |
14251 | } | |
14252 | ||
d6214d7a DK |
14253 | /* Disable MSI/MSI-X */ |
14254 | bnx2x_disable_msi(bp); | |
f85582f8 | 14255 | |
084d6cbb | 14256 | /* Power off */ |
1ab4434c AE |
14257 | if (IS_PF(bp)) |
14258 | bnx2x_set_power_state(bp, PCI_D3hot); | |
084d6cbb | 14259 | |
72fd0718 | 14260 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 14261 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
290ca2bb | 14262 | |
4513f925 AE |
14263 | /* send message via vfpf channel to release the resources of this vf */ |
14264 | if (IS_VF(bp)) | |
14265 | bnx2x_vfpf_release(bp); | |
72fd0718 | 14266 | |
b030ed2f YM |
14267 | /* Assumes no further PCIe PM changes will occur */ |
14268 | if (system_state == SYSTEM_POWER_OFF) { | |
14269 | pci_wake_from_d3(pdev, bp->wol); | |
14270 | pci_set_power_state(pdev, PCI_D3hot); | |
14271 | } | |
14272 | ||
33d8e6a5 | 14273 | bnx2x_disable_pcie_error_reporting(bp); |
d9aee591 YM |
14274 | if (remove_netdev) { |
14275 | if (bp->regview) | |
14276 | iounmap(bp->regview); | |
33d8e6a5 | 14277 | |
d9aee591 YM |
14278 | /* For vfs, doorbells are part of the regview and were unmapped |
14279 | * along with it. FW is only loaded by PF. | |
14280 | */ | |
14281 | if (IS_PF(bp)) { | |
14282 | if (bp->doorbells) | |
14283 | iounmap(bp->doorbells); | |
eb2afd4a | 14284 | |
d9aee591 | 14285 | bnx2x_release_firmware(bp); |
e2a367f8 YM |
14286 | } else { |
14287 | bnx2x_vf_pci_dealloc(bp); | |
d9aee591 YM |
14288 | } |
14289 | bnx2x_free_mem_bp(bp); | |
523224a3 | 14290 | |
b030ed2f | 14291 | free_netdev(dev); |
34f80b04 | 14292 | |
d9aee591 YM |
14293 | if (atomic_read(&pdev->enable_cnt) == 1) |
14294 | pci_release_regions(pdev); | |
34f80b04 | 14295 | |
5f6db130 YM |
14296 | pci_disable_device(pdev); |
14297 | } | |
a2fbb9ea ET |
14298 | } |
14299 | ||
b030ed2f YM |
14300 | static void bnx2x_remove_one(struct pci_dev *pdev) |
14301 | { | |
14302 | struct net_device *dev = pci_get_drvdata(pdev); | |
14303 | struct bnx2x *bp; | |
14304 | ||
14305 | if (!dev) { | |
14306 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); | |
14307 | return; | |
14308 | } | |
14309 | bp = netdev_priv(dev); | |
14310 | ||
14311 | __bnx2x_remove(pdev, dev, bp, true); | |
14312 | } | |
14313 | ||
f8ef6e44 YG |
14314 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
14315 | { | |
7fa6f340 | 14316 | bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; |
f8ef6e44 YG |
14317 | |
14318 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
14319 | ||
55c11941 MS |
14320 | if (CNIC_LOADED(bp)) |
14321 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
14322 | ||
619c5cb6 VZ |
14323 | /* Stop Tx */ |
14324 | bnx2x_tx_disable(bp); | |
26614ba5 MS |
14325 | /* Delete all NAPI objects */ |
14326 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
14327 | if (CNIC_LOADED(bp)) |
14328 | bnx2x_del_all_napi_cnic(bp); | |
7fa6f340 | 14329 | netdev_reset_tc(bp->dev); |
f8ef6e44 YG |
14330 | |
14331 | del_timer_sync(&bp->timer); | |
0c0e6341 | 14332 | cancel_delayed_work_sync(&bp->sp_task); |
14333 | cancel_delayed_work_sync(&bp->period_task); | |
619c5cb6 | 14334 | |
c6e36d8c YM |
14335 | if (!down_timeout(&bp->stats_lock, HZ / 10)) { |
14336 | bp->stats_state = STATS_STATE_DISABLED; | |
14337 | up(&bp->stats_lock); | |
14338 | } | |
f8ef6e44 | 14339 | |
7fa6f340 | 14340 | bnx2x_save_statistics(bp); |
f8ef6e44 | 14341 | |
619c5cb6 VZ |
14342 | netif_carrier_off(bp->dev); |
14343 | ||
f8ef6e44 YG |
14344 | return 0; |
14345 | } | |
14346 | ||
493adb1f WX |
14347 | /** |
14348 | * bnx2x_io_error_detected - called when PCI error is detected | |
14349 | * @pdev: Pointer to PCI device | |
14350 | * @state: The current pci connection state | |
14351 | * | |
14352 | * This function is called after a PCI bus error affecting | |
14353 | * this device has been detected. | |
14354 | */ | |
14355 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
14356 | pci_channel_state_t state) | |
14357 | { | |
14358 | struct net_device *dev = pci_get_drvdata(pdev); | |
14359 | struct bnx2x *bp = netdev_priv(dev); | |
14360 | ||
14361 | rtnl_lock(); | |
14362 | ||
7fa6f340 YM |
14363 | BNX2X_ERR("IO error detected\n"); |
14364 | ||
493adb1f WX |
14365 | netif_device_detach(dev); |
14366 | ||
07ce50e4 DN |
14367 | if (state == pci_channel_io_perm_failure) { |
14368 | rtnl_unlock(); | |
14369 | return PCI_ERS_RESULT_DISCONNECT; | |
14370 | } | |
14371 | ||
493adb1f | 14372 | if (netif_running(dev)) |
f8ef6e44 | 14373 | bnx2x_eeh_nic_unload(bp); |
493adb1f | 14374 | |
7fa6f340 YM |
14375 | bnx2x_prev_path_mark_eeh(bp); |
14376 | ||
493adb1f WX |
14377 | pci_disable_device(pdev); |
14378 | ||
14379 | rtnl_unlock(); | |
14380 | ||
14381 | /* Request a slot reset */ | |
14382 | return PCI_ERS_RESULT_NEED_RESET; | |
14383 | } | |
14384 | ||
14385 | /** | |
14386 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
14387 | * @pdev: Pointer to PCI device | |
14388 | * | |
14389 | * Restart the card from scratch, as if from a cold-boot. | |
14390 | */ | |
14391 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
14392 | { | |
14393 | struct net_device *dev = pci_get_drvdata(pdev); | |
14394 | struct bnx2x *bp = netdev_priv(dev); | |
7fa6f340 | 14395 | int i; |
493adb1f WX |
14396 | |
14397 | rtnl_lock(); | |
7fa6f340 | 14398 | BNX2X_ERR("IO slot reset initializing...\n"); |
493adb1f WX |
14399 | if (pci_enable_device(pdev)) { |
14400 | dev_err(&pdev->dev, | |
14401 | "Cannot re-enable PCI device after reset\n"); | |
14402 | rtnl_unlock(); | |
14403 | return PCI_ERS_RESULT_DISCONNECT; | |
14404 | } | |
14405 | ||
14406 | pci_set_master(pdev); | |
14407 | pci_restore_state(pdev); | |
70632d0a | 14408 | pci_save_state(pdev); |
493adb1f WX |
14409 | |
14410 | if (netif_running(dev)) | |
14411 | bnx2x_set_power_state(bp, PCI_D0); | |
14412 | ||
7fa6f340 YM |
14413 | if (netif_running(dev)) { |
14414 | BNX2X_ERR("IO slot reset --> driver unload\n"); | |
e68072ef YM |
14415 | |
14416 | /* MCP should have been reset; Need to wait for validity */ | |
f7084059 GP |
14417 | if (bnx2x_init_shmem(bp)) { |
14418 | rtnl_unlock(); | |
14419 | return PCI_ERS_RESULT_DISCONNECT; | |
14420 | } | |
e68072ef | 14421 | |
7fa6f340 YM |
14422 | if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { |
14423 | u32 v; | |
14424 | ||
14425 | v = SHMEM2_RD(bp, | |
14426 | drv_capabilities_flag[BP_FW_MB_IDX(bp)]); | |
14427 | SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], | |
14428 | v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); | |
14429 | } | |
14430 | bnx2x_drain_tx_queues(bp); | |
14431 | bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); | |
14432 | bnx2x_netif_stop(bp, 1); | |
14433 | bnx2x_free_irq(bp); | |
14434 | ||
14435 | /* Report UNLOAD_DONE to MCP */ | |
14436 | bnx2x_send_unload_done(bp, true); | |
14437 | ||
14438 | bp->sp_state = 0; | |
14439 | bp->port.pmf = 0; | |
14440 | ||
14441 | bnx2x_prev_unload(bp); | |
14442 | ||
16a5fd92 | 14443 | /* We should have reseted the engine, so It's fair to |
7fa6f340 YM |
14444 | * assume the FW will no longer write to the bnx2x driver. |
14445 | */ | |
14446 | bnx2x_squeeze_objects(bp); | |
14447 | bnx2x_free_skbs(bp); | |
14448 | for_each_rx_queue(bp, i) | |
14449 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); | |
14450 | bnx2x_free_fp_mem(bp); | |
14451 | bnx2x_free_mem(bp); | |
14452 | ||
14453 | bp->state = BNX2X_STATE_CLOSED; | |
14454 | } | |
14455 | ||
493adb1f WX |
14456 | rtnl_unlock(); |
14457 | ||
33d8e6a5 YM |
14458 | /* If AER, perform cleanup of the PCIe registers */ |
14459 | if (bp->flags & AER_ENABLED) { | |
14460 | if (pci_cleanup_aer_uncorrect_error_status(pdev)) | |
14461 | BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n"); | |
14462 | else | |
14463 | DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n"); | |
14464 | } | |
14465 | ||
493adb1f WX |
14466 | return PCI_ERS_RESULT_RECOVERED; |
14467 | } | |
14468 | ||
14469 | /** | |
14470 | * bnx2x_io_resume - called when traffic can start flowing again | |
14471 | * @pdev: Pointer to PCI device | |
14472 | * | |
14473 | * This callback is called when the error recovery driver tells us that | |
14474 | * its OK to resume normal operation. | |
14475 | */ | |
14476 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
14477 | { | |
14478 | struct net_device *dev = pci_get_drvdata(pdev); | |
14479 | struct bnx2x *bp = netdev_priv(dev); | |
14480 | ||
72fd0718 | 14481 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 14482 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
72fd0718 VZ |
14483 | return; |
14484 | } | |
14485 | ||
493adb1f WX |
14486 | rtnl_lock(); |
14487 | ||
7fa6f340 YM |
14488 | bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & |
14489 | DRV_MSG_SEQ_NUMBER_MASK; | |
14490 | ||
493adb1f | 14491 | if (netif_running(dev)) |
f8ef6e44 | 14492 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
14493 | |
14494 | netif_device_attach(dev); | |
14495 | ||
14496 | rtnl_unlock(); | |
14497 | } | |
14498 | ||
3646f0e5 | 14499 | static const struct pci_error_handlers bnx2x_err_handler = { |
493adb1f | 14500 | .error_detected = bnx2x_io_error_detected, |
356e2385 EG |
14501 | .slot_reset = bnx2x_io_slot_reset, |
14502 | .resume = bnx2x_io_resume, | |
493adb1f WX |
14503 | }; |
14504 | ||
b030ed2f YM |
14505 | static void bnx2x_shutdown(struct pci_dev *pdev) |
14506 | { | |
14507 | struct net_device *dev = pci_get_drvdata(pdev); | |
14508 | struct bnx2x *bp; | |
14509 | ||
14510 | if (!dev) | |
14511 | return; | |
14512 | ||
14513 | bp = netdev_priv(dev); | |
14514 | if (!bp) | |
14515 | return; | |
14516 | ||
14517 | rtnl_lock(); | |
14518 | netif_device_detach(dev); | |
14519 | rtnl_unlock(); | |
14520 | ||
14521 | /* Don't remove the netdevice, as there are scenarios which will cause | |
14522 | * the kernel to hang, e.g., when trying to remove bnx2i while the | |
14523 | * rootfs is mounted from SAN. | |
14524 | */ | |
14525 | __bnx2x_remove(pdev, dev, bp, false); | |
14526 | } | |
14527 | ||
a2fbb9ea | 14528 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
14529 | .name = DRV_MODULE_NAME, |
14530 | .id_table = bnx2x_pci_tbl, | |
14531 | .probe = bnx2x_init_one, | |
0329aba1 | 14532 | .remove = bnx2x_remove_one, |
493adb1f WX |
14533 | .suspend = bnx2x_suspend, |
14534 | .resume = bnx2x_resume, | |
14535 | .err_handler = &bnx2x_err_handler, | |
3c76feff AE |
14536 | #ifdef CONFIG_BNX2X_SRIOV |
14537 | .sriov_configure = bnx2x_sriov_configure, | |
14538 | #endif | |
b030ed2f | 14539 | .shutdown = bnx2x_shutdown, |
a2fbb9ea ET |
14540 | }; |
14541 | ||
14542 | static int __init bnx2x_init(void) | |
14543 | { | |
dd21ca6d SG |
14544 | int ret; |
14545 | ||
7995c64e | 14546 | pr_info("%s", version); |
938cf541 | 14547 | |
1cf167f2 EG |
14548 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
14549 | if (bnx2x_wq == NULL) { | |
7995c64e | 14550 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
14551 | return -ENOMEM; |
14552 | } | |
370d4a26 YM |
14553 | bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov"); |
14554 | if (!bnx2x_iov_wq) { | |
14555 | pr_err("Cannot create iov workqueue\n"); | |
14556 | destroy_workqueue(bnx2x_wq); | |
14557 | return -ENOMEM; | |
14558 | } | |
1cf167f2 | 14559 | |
dd21ca6d SG |
14560 | ret = pci_register_driver(&bnx2x_pci_driver); |
14561 | if (ret) { | |
7995c64e | 14562 | pr_err("Cannot register driver\n"); |
dd21ca6d | 14563 | destroy_workqueue(bnx2x_wq); |
370d4a26 | 14564 | destroy_workqueue(bnx2x_iov_wq); |
dd21ca6d SG |
14565 | } |
14566 | return ret; | |
a2fbb9ea ET |
14567 | } |
14568 | ||
14569 | static void __exit bnx2x_cleanup(void) | |
14570 | { | |
452427b0 | 14571 | struct list_head *pos, *q; |
d76a6111 | 14572 | |
a2fbb9ea | 14573 | pci_unregister_driver(&bnx2x_pci_driver); |
1cf167f2 EG |
14574 | |
14575 | destroy_workqueue(bnx2x_wq); | |
370d4a26 | 14576 | destroy_workqueue(bnx2x_iov_wq); |
452427b0 | 14577 | |
16a5fd92 | 14578 | /* Free globally allocated resources */ |
452427b0 YM |
14579 | list_for_each_safe(pos, q, &bnx2x_prev_list) { |
14580 | struct bnx2x_prev_path_list *tmp = | |
14581 | list_entry(pos, struct bnx2x_prev_path_list, list); | |
14582 | list_del(pos); | |
14583 | kfree(tmp); | |
14584 | } | |
a2fbb9ea ET |
14585 | } |
14586 | ||
3deb8167 YR |
14587 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
14588 | { | |
14589 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
14590 | } | |
14591 | ||
a2fbb9ea ET |
14592 | module_init(bnx2x_init); |
14593 | module_exit(bnx2x_cleanup); | |
14594 | ||
619c5cb6 VZ |
14595 | /** |
14596 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
14597 | * | |
14598 | * @bp: driver handle | |
14599 | * @set: set or clear the CAM entry | |
14600 | * | |
16a5fd92 | 14601 | * This function will wait until the ramrod completion returns. |
619c5cb6 VZ |
14602 | * Return 0 if success, -ENODEV if ramrod doesn't return. |
14603 | */ | |
1191cb83 | 14604 | static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) |
619c5cb6 VZ |
14605 | { |
14606 | unsigned long ramrod_flags = 0; | |
14607 | ||
14608 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
14609 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
14610 | &bp->iscsi_l2_mac_obj, true, | |
14611 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
14612 | } | |
993ac7b5 MC |
14613 | |
14614 | /* count denotes the number of new completions we have seen */ | |
14615 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
14616 | { | |
14617 | struct eth_spe *spe; | |
a052997e | 14618 | int cxt_index, cxt_offset; |
993ac7b5 MC |
14619 | |
14620 | #ifdef BNX2X_STOP_ON_ERROR | |
14621 | if (unlikely(bp->panic)) | |
14622 | return; | |
14623 | #endif | |
14624 | ||
14625 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 14626 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
14627 | bp->cnic_spq_pending -= count; |
14628 | ||
c2bff63f DK |
14629 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
14630 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
14631 | & SPE_HDR_CONN_TYPE) >> | |
14632 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
14633 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
14634 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
14635 | |
14636 | /* Set validation for iSCSI L2 client before sending SETUP | |
14637 | * ramrod | |
14638 | */ | |
14639 | if (type == ETH_CONNECTION_TYPE) { | |
a052997e | 14640 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { |
37ae41a9 | 14641 | cxt_index = BNX2X_ISCSI_ETH_CID(bp) / |
a052997e | 14642 | ILT_PAGE_CIDS; |
37ae41a9 | 14643 | cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - |
a052997e MS |
14644 | (cxt_index * ILT_PAGE_CIDS); |
14645 | bnx2x_set_ctx_validation(bp, | |
14646 | &bp->context[cxt_index]. | |
14647 | vcxt[cxt_offset].eth, | |
37ae41a9 | 14648 | BNX2X_ISCSI_ETH_CID(bp)); |
a052997e | 14649 | } |
c2bff63f DK |
14650 | } |
14651 | ||
619c5cb6 VZ |
14652 | /* |
14653 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
14654 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
14655 | * COMMON ramrods is not more than the EQ and SPQ can |
14656 | * accommodate. | |
c2bff63f | 14657 | */ |
6e30dd4e VZ |
14658 | if (type == ETH_CONNECTION_TYPE) { |
14659 | if (!atomic_read(&bp->cq_spq_left)) | |
14660 | break; | |
14661 | else | |
14662 | atomic_dec(&bp->cq_spq_left); | |
14663 | } else if (type == NONE_CONNECTION_TYPE) { | |
14664 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
14665 | break; |
14666 | else | |
6e30dd4e | 14667 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
14668 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
14669 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
14670 | if (bp->cnic_spq_pending >= |
14671 | bp->cnic_eth_dev.max_kwqe_pending) | |
14672 | break; | |
14673 | else | |
14674 | bp->cnic_spq_pending++; | |
14675 | } else { | |
14676 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
14677 | bnx2x_panic(); | |
993ac7b5 | 14678 | break; |
c2bff63f | 14679 | } |
993ac7b5 MC |
14680 | |
14681 | spe = bnx2x_sp_get_next(bp); | |
14682 | *spe = *bp->cnic_kwq_cons; | |
14683 | ||
51c1a580 | 14684 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
993ac7b5 MC |
14685 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
14686 | ||
14687 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
14688 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
14689 | else | |
14690 | bp->cnic_kwq_cons++; | |
14691 | } | |
14692 | bnx2x_sp_prod_update(bp); | |
14693 | spin_unlock_bh(&bp->spq_lock); | |
14694 | } | |
14695 | ||
14696 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
14697 | struct kwqe_16 *kwqes[], u32 count) | |
14698 | { | |
14699 | struct bnx2x *bp = netdev_priv(dev); | |
14700 | int i; | |
14701 | ||
14702 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 MS |
14703 | if (unlikely(bp->panic)) { |
14704 | BNX2X_ERR("Can't post to SP queue while panic\n"); | |
993ac7b5 | 14705 | return -EIO; |
51c1a580 | 14706 | } |
993ac7b5 MC |
14707 | #endif |
14708 | ||
95c6c616 AE |
14709 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
14710 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
51c1a580 | 14711 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
95c6c616 AE |
14712 | return -EAGAIN; |
14713 | } | |
14714 | ||
993ac7b5 MC |
14715 | spin_lock_bh(&bp->spq_lock); |
14716 | ||
14717 | for (i = 0; i < count; i++) { | |
14718 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
14719 | ||
14720 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
14721 | break; | |
14722 | ||
14723 | *bp->cnic_kwq_prod = *spe; | |
14724 | ||
14725 | bp->cnic_kwq_pending++; | |
14726 | ||
51c1a580 | 14727 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
993ac7b5 | 14728 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
523224a3 DK |
14729 | spe->data.update_data_addr.hi, |
14730 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
14731 | bp->cnic_kwq_pending); |
14732 | ||
14733 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
14734 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
14735 | else | |
14736 | bp->cnic_kwq_prod++; | |
14737 | } | |
14738 | ||
14739 | spin_unlock_bh(&bp->spq_lock); | |
14740 | ||
14741 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
14742 | bnx2x_cnic_sp_post(bp, 0); | |
14743 | ||
14744 | return i; | |
14745 | } | |
14746 | ||
14747 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
14748 | { | |
14749 | struct cnic_ops *c_ops; | |
14750 | int rc = 0; | |
14751 | ||
14752 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
14753 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
14754 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
14755 | if (c_ops) |
14756 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
14757 | mutex_unlock(&bp->cnic_mutex); | |
14758 | ||
14759 | return rc; | |
14760 | } | |
14761 | ||
14762 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
14763 | { | |
14764 | struct cnic_ops *c_ops; | |
14765 | int rc = 0; | |
14766 | ||
14767 | rcu_read_lock(); | |
14768 | c_ops = rcu_dereference(bp->cnic_ops); | |
14769 | if (c_ops) | |
14770 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
14771 | rcu_read_unlock(); | |
14772 | ||
14773 | return rc; | |
14774 | } | |
14775 | ||
14776 | /* | |
14777 | * for commands that have no data | |
14778 | */ | |
9f6c9258 | 14779 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
14780 | { |
14781 | struct cnic_ctl_info ctl = {0}; | |
14782 | ||
14783 | ctl.cmd = cmd; | |
14784 | ||
14785 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
14786 | } | |
14787 | ||
619c5cb6 | 14788 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 14789 | { |
619c5cb6 | 14790 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
14791 | |
14792 | /* first we tell CNIC and only then we count this as a completion */ | |
14793 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
14794 | ctl.data.comp.cid = cid; | |
619c5cb6 | 14795 | ctl.data.comp.error = err; |
993ac7b5 MC |
14796 | |
14797 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 14798 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
14799 | } |
14800 | ||
619c5cb6 VZ |
14801 | /* Called with netif_addr_lock_bh() taken. |
14802 | * Sets an rx_mode config for an iSCSI ETH client. | |
14803 | * Doesn't block. | |
14804 | * Completion should be checked outside. | |
14805 | */ | |
14806 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
14807 | { | |
14808 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
14809 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
14810 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
14811 | ||
14812 | if (start) { | |
14813 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
14814 | * because it's the only way for UIO Queue to accept | |
14815 | * multicasts (in non-promiscuous mode only one Queue per | |
14816 | * function will receive multicast packets (leading in our | |
14817 | * case). | |
14818 | */ | |
14819 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
14820 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
14821 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
14822 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
14823 | ||
14824 | /* Clear STOP_PENDING bit if START is requested */ | |
14825 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
14826 | ||
14827 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
14828 | } else | |
14829 | /* Clear START_PENDING bit if STOP is requested */ | |
14830 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
14831 | ||
14832 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
14833 | set_bit(sched_state, &bp->sp_state); | |
14834 | else { | |
14835 | __set_bit(RAMROD_RX, &ramrod_flags); | |
14836 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
14837 | ramrod_flags); | |
14838 | } | |
14839 | } | |
14840 | ||
993ac7b5 MC |
14841 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
14842 | { | |
14843 | struct bnx2x *bp = netdev_priv(dev); | |
14844 | int rc = 0; | |
14845 | ||
14846 | switch (ctl->cmd) { | |
14847 | case DRV_CTL_CTXTBL_WR_CMD: { | |
14848 | u32 index = ctl->data.io.offset; | |
14849 | dma_addr_t addr = ctl->data.io.dma_addr; | |
14850 | ||
14851 | bnx2x_ilt_wr(bp, index, addr); | |
14852 | break; | |
14853 | } | |
14854 | ||
c2bff63f DK |
14855 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
14856 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
14857 | |
14858 | bnx2x_cnic_sp_post(bp, count); | |
14859 | break; | |
14860 | } | |
14861 | ||
14862 | /* rtnl_lock is held. */ | |
14863 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
14864 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
14865 | unsigned long sp_bits = 0; | |
14866 | ||
14867 | /* Configure the iSCSI classification object */ | |
14868 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
14869 | cp->iscsi_l2_client_id, | |
14870 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
14871 | bnx2x_sp(bp, mac_rdata), | |
14872 | bnx2x_sp_mapping(bp, mac_rdata), | |
14873 | BNX2X_FILTER_MAC_PENDING, | |
14874 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
14875 | &bp->macs_pool); | |
ec6ba945 | 14876 | |
523224a3 | 14877 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
14878 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
14879 | if (rc) | |
14880 | break; | |
523224a3 DK |
14881 | |
14882 | mmiowb(); | |
14883 | barrier(); | |
14884 | ||
619c5cb6 VZ |
14885 | /* Start accepting on iSCSI L2 ring */ |
14886 | ||
14887 | netif_addr_lock_bh(dev); | |
14888 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
14889 | netif_addr_unlock_bh(dev); | |
14890 | ||
14891 | /* bits to wait on */ | |
14892 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
14893 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
14894 | ||
14895 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
14896 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 14897 | |
993ac7b5 MC |
14898 | break; |
14899 | } | |
14900 | ||
14901 | /* rtnl_lock is held. */ | |
14902 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 14903 | unsigned long sp_bits = 0; |
993ac7b5 | 14904 | |
523224a3 | 14905 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
14906 | netif_addr_lock_bh(dev); |
14907 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
14908 | netif_addr_unlock_bh(dev); | |
14909 | ||
14910 | /* bits to wait on */ | |
14911 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
14912 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
14913 | ||
14914 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
14915 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
14916 | |
14917 | mmiowb(); | |
14918 | barrier(); | |
14919 | ||
14920 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
14921 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
14922 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
14923 | break; |
14924 | } | |
c2bff63f DK |
14925 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
14926 | int count = ctl->data.credit.credit_count; | |
14927 | ||
4e857c58 | 14928 | smp_mb__before_atomic(); |
6e30dd4e | 14929 | atomic_add(count, &bp->cq_spq_left); |
4e857c58 | 14930 | smp_mb__after_atomic(); |
c2bff63f DK |
14931 | break; |
14932 | } | |
1d187b34 | 14933 | case DRV_CTL_ULP_REGISTER_CMD: { |
2e499d3c | 14934 | int ulp_type = ctl->data.register_data.ulp_type; |
1d187b34 BW |
14935 | |
14936 | if (CHIP_IS_E3(bp)) { | |
14937 | int idx = BP_FW_MB_IDX(bp); | |
2e499d3c BW |
14938 | u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); |
14939 | int path = BP_PATH(bp); | |
14940 | int port = BP_PORT(bp); | |
14941 | int i; | |
14942 | u32 scratch_offset; | |
14943 | u32 *host_addr; | |
1d187b34 | 14944 | |
2e499d3c | 14945 | /* first write capability to shmem2 */ |
1d187b34 BW |
14946 | if (ulp_type == CNIC_ULP_ISCSI) |
14947 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
14948 | else if (ulp_type == CNIC_ULP_FCOE) | |
14949 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
14950 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
2e499d3c BW |
14951 | |
14952 | if ((ulp_type != CNIC_ULP_FCOE) || | |
14953 | (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || | |
14954 | (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) | |
14955 | break; | |
14956 | ||
14957 | /* if reached here - should write fcoe capabilities */ | |
14958 | scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); | |
14959 | if (!scratch_offset) | |
14960 | break; | |
14961 | scratch_offset += offsetof(struct glob_ncsi_oem_data, | |
14962 | fcoe_features[path][port]); | |
14963 | host_addr = (u32 *) &(ctl->data.register_data. | |
14964 | fcoe_features); | |
14965 | for (i = 0; i < sizeof(struct fcoe_capabilities); | |
14966 | i += 4) | |
14967 | REG_WR(bp, scratch_offset + i, | |
14968 | *(host_addr + i/4)); | |
1d187b34 | 14969 | } |
42f8277f | 14970 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); |
1d187b34 BW |
14971 | break; |
14972 | } | |
2e499d3c | 14973 | |
1d187b34 BW |
14974 | case DRV_CTL_ULP_UNREGISTER_CMD: { |
14975 | int ulp_type = ctl->data.ulp_type; | |
14976 | ||
14977 | if (CHIP_IS_E3(bp)) { | |
14978 | int idx = BP_FW_MB_IDX(bp); | |
14979 | u32 cap; | |
14980 | ||
14981 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
14982 | if (ulp_type == CNIC_ULP_ISCSI) | |
14983 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
14984 | else if (ulp_type == CNIC_ULP_FCOE) | |
14985 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
14986 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
14987 | } | |
42f8277f | 14988 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); |
1d187b34 BW |
14989 | break; |
14990 | } | |
993ac7b5 MC |
14991 | |
14992 | default: | |
14993 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
14994 | rc = -EINVAL; | |
14995 | } | |
14996 | ||
97ac4ef7 YM |
14997 | /* For storage-only interfaces, change driver state */ |
14998 | if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) { | |
14999 | switch (ctl->drv_state) { | |
15000 | case DRV_NOP: | |
15001 | break; | |
15002 | case DRV_ACTIVE: | |
15003 | bnx2x_set_os_driver_state(bp, | |
15004 | OS_DRIVER_STATE_ACTIVE); | |
15005 | break; | |
15006 | case DRV_INACTIVE: | |
15007 | bnx2x_set_os_driver_state(bp, | |
15008 | OS_DRIVER_STATE_DISABLED); | |
15009 | break; | |
15010 | case DRV_UNLOADED: | |
15011 | bnx2x_set_os_driver_state(bp, | |
15012 | OS_DRIVER_STATE_NOT_LOADED); | |
15013 | break; | |
15014 | default: | |
15015 | BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state); | |
15016 | } | |
15017 | } | |
15018 | ||
15019 | return rc; | |
15020 | } | |
15021 | ||
15022 | static int bnx2x_get_fc_npiv(struct net_device *dev, | |
15023 | struct cnic_fc_npiv_tbl *cnic_tbl) | |
15024 | { | |
15025 | struct bnx2x *bp = netdev_priv(dev); | |
15026 | struct bdn_fc_npiv_tbl *tbl = NULL; | |
15027 | u32 offset, entries; | |
15028 | int rc = -EINVAL; | |
15029 | int i; | |
15030 | ||
15031 | if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0])) | |
15032 | goto out; | |
15033 | ||
15034 | DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n"); | |
15035 | ||
15036 | tbl = kmalloc(sizeof(*tbl), GFP_KERNEL); | |
15037 | if (!tbl) { | |
15038 | BNX2X_ERR("Failed to allocate fc_npiv table\n"); | |
15039 | goto out; | |
15040 | } | |
15041 | ||
15042 | offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]); | |
1e6bb1a3 YM |
15043 | if (!offset) { |
15044 | DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n"); | |
15045 | goto out; | |
15046 | } | |
97ac4ef7 YM |
15047 | DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset); |
15048 | ||
15049 | /* Read the table contents from nvram */ | |
15050 | if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) { | |
15051 | BNX2X_ERR("Failed to read FC-NPIV table\n"); | |
15052 | goto out; | |
15053 | } | |
15054 | ||
15055 | /* Since bnx2x_nvram_read() returns data in be32, we need to convert | |
15056 | * the number of entries back to cpu endianness. | |
15057 | */ | |
15058 | entries = tbl->fc_npiv_cfg.num_of_npiv; | |
15059 | entries = (__force u32)be32_to_cpu((__force __be32)entries); | |
15060 | tbl->fc_npiv_cfg.num_of_npiv = entries; | |
15061 | ||
15062 | if (!tbl->fc_npiv_cfg.num_of_npiv) { | |
15063 | DP(BNX2X_MSG_MCP, | |
15064 | "No FC-NPIV table [valid, simply not present]\n"); | |
15065 | goto out; | |
15066 | } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) { | |
15067 | BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n", | |
15068 | tbl->fc_npiv_cfg.num_of_npiv); | |
15069 | goto out; | |
15070 | } else { | |
15071 | DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n", | |
15072 | tbl->fc_npiv_cfg.num_of_npiv); | |
15073 | } | |
15074 | ||
15075 | /* Copy the data into cnic-provided struct */ | |
15076 | cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv; | |
15077 | for (i = 0; i < cnic_tbl->count; i++) { | |
15078 | memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8); | |
15079 | memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8); | |
15080 | } | |
15081 | ||
15082 | rc = 0; | |
15083 | out: | |
15084 | kfree(tbl); | |
993ac7b5 MC |
15085 | return rc; |
15086 | } | |
15087 | ||
9f6c9258 | 15088 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
15089 | { |
15090 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
15091 | ||
15092 | if (bp->flags & USING_MSIX_FLAG) { | |
15093 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
15094 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
15095 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
15096 | } else { | |
15097 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
15098 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
15099 | } | |
619c5cb6 | 15100 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
15101 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
15102 | else | |
15103 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
15104 | ||
619c5cb6 VZ |
15105 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
15106 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
15107 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
15108 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 15109 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
15110 | |
15111 | cp->num_irq = 2; | |
15112 | } | |
15113 | ||
37ae41a9 MS |
15114 | void bnx2x_setup_cnic_info(struct bnx2x *bp) |
15115 | { | |
15116 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
15117 | ||
37ae41a9 MS |
15118 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
15119 | bnx2x_cid_ilt_lines(bp); | |
15120 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; | |
15121 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); | |
15122 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); | |
15123 | ||
f78afb35 MC |
15124 | DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n", |
15125 | BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid, | |
15126 | cp->iscsi_l2_cid); | |
15127 | ||
37ae41a9 MS |
15128 | if (NO_ISCSI_OOO(bp)) |
15129 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
15130 | } | |
15131 | ||
993ac7b5 MC |
15132 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, |
15133 | void *data) | |
15134 | { | |
15135 | struct bnx2x *bp = netdev_priv(dev); | |
15136 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
55c11941 MS |
15137 | int rc; |
15138 | ||
15139 | DP(NETIF_MSG_IFUP, "Register_cnic called\n"); | |
993ac7b5 | 15140 | |
51c1a580 MS |
15141 | if (ops == NULL) { |
15142 | BNX2X_ERR("NULL ops received\n"); | |
993ac7b5 | 15143 | return -EINVAL; |
51c1a580 | 15144 | } |
993ac7b5 | 15145 | |
55c11941 MS |
15146 | if (!CNIC_SUPPORT(bp)) { |
15147 | BNX2X_ERR("Can't register CNIC when not supported\n"); | |
15148 | return -EOPNOTSUPP; | |
15149 | } | |
15150 | ||
15151 | if (!CNIC_LOADED(bp)) { | |
15152 | rc = bnx2x_load_cnic(bp); | |
15153 | if (rc) { | |
15154 | BNX2X_ERR("CNIC-related load failed\n"); | |
15155 | return rc; | |
15156 | } | |
55c11941 MS |
15157 | } |
15158 | ||
15159 | bp->cnic_enabled = true; | |
15160 | ||
993ac7b5 MC |
15161 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
15162 | if (!bp->cnic_kwq) | |
15163 | return -ENOMEM; | |
15164 | ||
15165 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
15166 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
15167 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
15168 | ||
15169 | bp->cnic_spq_pending = 0; | |
15170 | bp->cnic_kwq_pending = 0; | |
15171 | ||
15172 | bp->cnic_data = data; | |
15173 | ||
15174 | cp->num_irq = 0; | |
619c5cb6 | 15175 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 15176 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 15177 | |
993ac7b5 | 15178 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 15179 | |
993ac7b5 MC |
15180 | rcu_assign_pointer(bp->cnic_ops, ops); |
15181 | ||
42f8277f YM |
15182 | /* Schedule driver to read CNIC driver versions */ |
15183 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); | |
15184 | ||
993ac7b5 MC |
15185 | return 0; |
15186 | } | |
15187 | ||
15188 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
15189 | { | |
15190 | struct bnx2x *bp = netdev_priv(dev); | |
15191 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
15192 | ||
15193 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 | 15194 | cp->drv_state = 0; |
2cfa5a04 | 15195 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
993ac7b5 MC |
15196 | mutex_unlock(&bp->cnic_mutex); |
15197 | synchronize_rcu(); | |
fea75645 | 15198 | bp->cnic_enabled = false; |
993ac7b5 MC |
15199 | kfree(bp->cnic_kwq); |
15200 | bp->cnic_kwq = NULL; | |
15201 | ||
15202 | return 0; | |
15203 | } | |
15204 | ||
a8f47eb7 | 15205 | static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) |
993ac7b5 MC |
15206 | { |
15207 | struct bnx2x *bp = netdev_priv(dev); | |
15208 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
15209 | ||
2ba45142 VZ |
15210 | /* If both iSCSI and FCoE are disabled - return NULL in |
15211 | * order to indicate CNIC that it should not try to work | |
15212 | * with this device. | |
15213 | */ | |
15214 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
15215 | return NULL; | |
15216 | ||
993ac7b5 MC |
15217 | cp->drv_owner = THIS_MODULE; |
15218 | cp->chip_id = CHIP_ID(bp); | |
15219 | cp->pdev = bp->pdev; | |
15220 | cp->io_base = bp->regview; | |
15221 | cp->io_base2 = bp->doorbells; | |
15222 | cp->max_kwqe_pending = 8; | |
523224a3 | 15223 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
15224 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
15225 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 15226 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 15227 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
15228 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
15229 | cp->drv_ctl = bnx2x_drv_ctl; | |
97ac4ef7 | 15230 | cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv; |
993ac7b5 MC |
15231 | cp->drv_register_cnic = bnx2x_register_cnic; |
15232 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
37ae41a9 | 15233 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); |
619c5cb6 VZ |
15234 | cp->iscsi_l2_client_id = |
15235 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
37ae41a9 | 15236 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); |
c2bff63f | 15237 | |
2ba45142 VZ |
15238 | if (NO_ISCSI_OOO(bp)) |
15239 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
15240 | ||
15241 | if (NO_ISCSI(bp)) | |
15242 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
15243 | ||
15244 | if (NO_FCOE(bp)) | |
15245 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
15246 | ||
51c1a580 MS |
15247 | BNX2X_DEV_INFO( |
15248 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", | |
c2bff63f DK |
15249 | cp->ctx_blk_size, |
15250 | cp->ctx_tbl_offset, | |
15251 | cp->ctx_tbl_len, | |
15252 | cp->starting_cid); | |
993ac7b5 MC |
15253 | return cp; |
15254 | } | |
993ac7b5 | 15255 | |
a8f47eb7 | 15256 | static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) |
9b176b6b | 15257 | { |
6411280a AE |
15258 | struct bnx2x *bp = fp->bp; |
15259 | u32 offset = BAR_USTRORM_INTMEM; | |
abc5a021 | 15260 | |
6411280a AE |
15261 | if (IS_VF(bp)) |
15262 | return bnx2x_vf_ustorm_prods_offset(bp, fp); | |
15263 | else if (!CHIP_IS_E1x(bp)) | |
15264 | offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); | |
15265 | else | |
15266 | offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); | |
8d9ac297 | 15267 | |
6411280a | 15268 | return offset; |
8d9ac297 | 15269 | } |
381ac16b | 15270 | |
6411280a AE |
15271 | /* called only on E1H or E2. |
15272 | * When pretending to be PF, the pretend value is the function number 0...7 | |
15273 | * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID | |
15274 | * combination | |
15275 | */ | |
15276 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) | |
381ac16b | 15277 | { |
6411280a | 15278 | u32 pretend_reg; |
381ac16b | 15279 | |
23826850 | 15280 | if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) |
6411280a | 15281 | return -1; |
381ac16b | 15282 | |
6411280a AE |
15283 | /* get my own pretend register */ |
15284 | pretend_reg = bnx2x_get_pretend_reg(bp); | |
15285 | REG_WR(bp, pretend_reg, pretend_func_val); | |
15286 | REG_RD(bp, pretend_reg); | |
381ac16b AE |
15287 | return 0; |
15288 | } | |
eeed018c MK |
15289 | |
15290 | static void bnx2x_ptp_task(struct work_struct *work) | |
15291 | { | |
15292 | struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task); | |
15293 | int port = BP_PORT(bp); | |
15294 | u32 val_seq; | |
15295 | u64 timestamp, ns; | |
15296 | struct skb_shared_hwtstamps shhwtstamps; | |
8e3020b2 GP |
15297 | bool bail = true; |
15298 | int i; | |
15299 | ||
15300 | /* FW may take a while to complete timestamping; try a bit and if it's | |
15301 | * still not complete, may indicate an error state - bail out then. | |
15302 | */ | |
15303 | for (i = 0; i < 10; i++) { | |
15304 | /* Read Tx timestamp registers */ | |
15305 | val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : | |
15306 | NIG_REG_P0_TLLH_PTP_BUF_SEQID); | |
15307 | if (val_seq & 0x10000) { | |
15308 | bail = false; | |
15309 | break; | |
15310 | } | |
15311 | msleep(1 << i); | |
15312 | } | |
eeed018c | 15313 | |
8e3020b2 | 15314 | if (!bail) { |
eeed018c MK |
15315 | /* There is a valid timestamp value */ |
15316 | timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB : | |
15317 | NIG_REG_P0_TLLH_PTP_BUF_TS_MSB); | |
15318 | timestamp <<= 32; | |
15319 | timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB : | |
15320 | NIG_REG_P0_TLLH_PTP_BUF_TS_LSB); | |
15321 | /* Reset timestamp register to allow new timestamp */ | |
15322 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : | |
15323 | NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); | |
15324 | ns = timecounter_cyc2time(&bp->timecounter, timestamp); | |
15325 | ||
15326 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
15327 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
15328 | skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps); | |
eeed018c MK |
15329 | |
15330 | DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n", | |
15331 | timestamp, ns); | |
15332 | } else { | |
8e3020b2 GP |
15333 | DP(BNX2X_MSG_PTP, |
15334 | "Tx timestamp is not recorded (register read=%u)\n", | |
15335 | val_seq); | |
15336 | bp->eth_stats.ptp_skip_tx_ts++; | |
eeed018c | 15337 | } |
8e3020b2 GP |
15338 | |
15339 | dev_kfree_skb_any(bp->ptp_tx_skb); | |
15340 | bp->ptp_tx_skb = NULL; | |
eeed018c MK |
15341 | } |
15342 | ||
15343 | void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb) | |
15344 | { | |
15345 | int port = BP_PORT(bp); | |
15346 | u64 timestamp, ns; | |
15347 | ||
15348 | timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB : | |
15349 | NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB); | |
15350 | timestamp <<= 32; | |
15351 | timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB : | |
15352 | NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB); | |
15353 | ||
15354 | /* Reset timestamp register to allow new timestamp */ | |
15355 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : | |
15356 | NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); | |
15357 | ||
15358 | ns = timecounter_cyc2time(&bp->timecounter, timestamp); | |
15359 | ||
15360 | skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); | |
15361 | ||
15362 | DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n", | |
15363 | timestamp, ns); | |
15364 | } | |
15365 | ||
15366 | /* Read the PHC */ | |
a5a1d1c2 | 15367 | static u64 bnx2x_cyclecounter_read(const struct cyclecounter *cc) |
eeed018c MK |
15368 | { |
15369 | struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter); | |
15370 | int port = BP_PORT(bp); | |
15371 | u32 wb_data[2]; | |
15372 | u64 phc_cycles; | |
15373 | ||
15374 | REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 : | |
15375 | NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2); | |
15376 | phc_cycles = wb_data[1]; | |
15377 | phc_cycles = (phc_cycles << 32) + wb_data[0]; | |
15378 | ||
15379 | DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles); | |
15380 | ||
15381 | return phc_cycles; | |
15382 | } | |
15383 | ||
15384 | static void bnx2x_init_cyclecounter(struct bnx2x *bp) | |
15385 | { | |
15386 | memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter)); | |
15387 | bp->cyclecounter.read = bnx2x_cyclecounter_read; | |
f28ba401 | 15388 | bp->cyclecounter.mask = CYCLECOUNTER_MASK(64); |
a6e2846c | 15389 | bp->cyclecounter.shift = 0; |
eeed018c MK |
15390 | bp->cyclecounter.mult = 1; |
15391 | } | |
15392 | ||
15393 | static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp) | |
15394 | { | |
15395 | struct bnx2x_func_state_params func_params = {NULL}; | |
15396 | struct bnx2x_func_set_timesync_params *set_timesync_params = | |
15397 | &func_params.params.set_timesync; | |
15398 | ||
15399 | /* Prepare parameters for function state transitions */ | |
15400 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
15401 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
15402 | ||
15403 | func_params.f_obj = &bp->func_obj; | |
15404 | func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; | |
15405 | ||
15406 | /* Function parameters */ | |
15407 | set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET; | |
15408 | set_timesync_params->offset_cmd = TS_OFFSET_KEEP; | |
15409 | ||
15410 | return bnx2x_func_state_change(bp, &func_params); | |
15411 | } | |
15412 | ||
1444c301 | 15413 | static int bnx2x_enable_ptp_packets(struct bnx2x *bp) |
eeed018c MK |
15414 | { |
15415 | struct bnx2x_queue_state_params q_params; | |
15416 | int rc, i; | |
15417 | ||
15418 | /* send queue update ramrod to enable PTP packets */ | |
15419 | memset(&q_params, 0, sizeof(q_params)); | |
15420 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
15421 | q_params.cmd = BNX2X_Q_CMD_UPDATE; | |
15422 | __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, | |
15423 | &q_params.params.update.update_flags); | |
15424 | __set_bit(BNX2X_Q_UPDATE_PTP_PKTS, | |
15425 | &q_params.params.update.update_flags); | |
15426 | ||
15427 | /* send the ramrod on all the queues of the PF */ | |
15428 | for_each_eth_queue(bp, i) { | |
15429 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
15430 | ||
15431 | /* Set the appropriate Queue object */ | |
15432 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; | |
15433 | ||
15434 | /* Update the Queue state */ | |
15435 | rc = bnx2x_queue_state_change(bp, &q_params); | |
15436 | if (rc) { | |
15437 | BNX2X_ERR("Failed to enable PTP packets\n"); | |
15438 | return rc; | |
15439 | } | |
15440 | } | |
15441 | ||
15442 | return 0; | |
15443 | } | |
15444 | ||
15445 | int bnx2x_configure_ptp_filters(struct bnx2x *bp) | |
15446 | { | |
15447 | int port = BP_PORT(bp); | |
15448 | int rc; | |
15449 | ||
15450 | if (!bp->hwtstamp_ioctl_called) | |
15451 | return 0; | |
15452 | ||
15453 | switch (bp->tx_type) { | |
15454 | case HWTSTAMP_TX_ON: | |
15455 | bp->flags |= TX_TIMESTAMPING_EN; | |
15456 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : | |
15457 | NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA); | |
15458 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : | |
15459 | NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE); | |
15460 | break; | |
15461 | case HWTSTAMP_TX_ONESTEP_SYNC: | |
15462 | BNX2X_ERR("One-step timestamping is not supported\n"); | |
15463 | return -ERANGE; | |
15464 | } | |
15465 | ||
15466 | switch (bp->rx_filter) { | |
15467 | case HWTSTAMP_FILTER_NONE: | |
15468 | break; | |
15469 | case HWTSTAMP_FILTER_ALL: | |
15470 | case HWTSTAMP_FILTER_SOME: | |
e3412575 | 15471 | case HWTSTAMP_FILTER_NTP_ALL: |
eeed018c MK |
15472 | bp->rx_filter = HWTSTAMP_FILTER_NONE; |
15473 | break; | |
15474 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
15475 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
15476 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
15477 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
15478 | /* Initialize PTP detection for UDP/IPv4 events */ | |
15479 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
15480 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE); | |
15481 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
15482 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE); | |
15483 | break; | |
15484 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
15485 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
15486 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
15487 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; | |
15488 | /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */ | |
15489 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
15490 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA); | |
15491 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
15492 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE); | |
15493 | break; | |
15494 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
15495 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
15496 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
15497 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; | |
15498 | /* Initialize PTP detection L2 events */ | |
15499 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
15500 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF); | |
15501 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
15502 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF); | |
15503 | ||
15504 | break; | |
15505 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
15506 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
15507 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
15508 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
15509 | /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */ | |
15510 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
15511 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA); | |
15512 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
15513 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE); | |
15514 | break; | |
15515 | } | |
15516 | ||
15517 | /* Indicate to FW that this PF expects recorded PTP packets */ | |
15518 | rc = bnx2x_enable_ptp_packets(bp); | |
15519 | if (rc) | |
15520 | return rc; | |
15521 | ||
15522 | /* Enable sending PTP packets to host */ | |
15523 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : | |
15524 | NIG_REG_P0_LLH_PTP_TO_HOST, 0x1); | |
15525 | ||
15526 | return 0; | |
15527 | } | |
15528 | ||
15529 | static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr) | |
15530 | { | |
15531 | struct hwtstamp_config config; | |
15532 | int rc; | |
15533 | ||
15534 | DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n"); | |
15535 | ||
15536 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
15537 | return -EFAULT; | |
15538 | ||
15539 | DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n", | |
15540 | config.tx_type, config.rx_filter); | |
15541 | ||
15542 | if (config.flags) { | |
15543 | BNX2X_ERR("config.flags is reserved for future use\n"); | |
15544 | return -EINVAL; | |
15545 | } | |
15546 | ||
15547 | bp->hwtstamp_ioctl_called = 1; | |
15548 | bp->tx_type = config.tx_type; | |
15549 | bp->rx_filter = config.rx_filter; | |
15550 | ||
15551 | rc = bnx2x_configure_ptp_filters(bp); | |
15552 | if (rc) | |
15553 | return rc; | |
15554 | ||
15555 | config.rx_filter = bp->rx_filter; | |
15556 | ||
15557 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
15558 | -EFAULT : 0; | |
15559 | } | |
15560 | ||
bf27c353 | 15561 | /* Configures HW for PTP */ |
eeed018c MK |
15562 | static int bnx2x_configure_ptp(struct bnx2x *bp) |
15563 | { | |
15564 | int rc, port = BP_PORT(bp); | |
15565 | u32 wb_data[2]; | |
15566 | ||
15567 | /* Reset PTP event detection rules - will be configured in the IOCTL */ | |
15568 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
15569 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); | |
15570 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
15571 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); | |
15572 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : | |
15573 | NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); | |
15574 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : | |
15575 | NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); | |
15576 | ||
15577 | /* Disable PTP packets to host - will be configured in the IOCTL*/ | |
15578 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : | |
15579 | NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); | |
15580 | ||
15581 | /* Enable the PTP feature */ | |
15582 | REG_WR(bp, port ? NIG_REG_P1_PTP_EN : | |
15583 | NIG_REG_P0_PTP_EN, 0x3F); | |
15584 | ||
15585 | /* Enable the free-running counter */ | |
15586 | wb_data[0] = 0; | |
15587 | wb_data[1] = 0; | |
15588 | REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2); | |
15589 | ||
15590 | /* Reset drift register (offset register is not reset) */ | |
15591 | rc = bnx2x_send_reset_timesync_ramrod(bp); | |
15592 | if (rc) { | |
15593 | BNX2X_ERR("Failed to reset PHC drift register\n"); | |
15594 | return -EFAULT; | |
15595 | } | |
15596 | ||
15597 | /* Reset possibly old timestamps */ | |
15598 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : | |
15599 | NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); | |
15600 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : | |
15601 | NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); | |
15602 | ||
15603 | return 0; | |
15604 | } | |
15605 | ||
15606 | /* Called during load, to initialize PTP-related stuff */ | |
15607 | void bnx2x_init_ptp(struct bnx2x *bp) | |
15608 | { | |
15609 | int rc; | |
15610 | ||
15611 | /* Configure PTP in HW */ | |
15612 | rc = bnx2x_configure_ptp(bp); | |
15613 | if (rc) { | |
15614 | BNX2X_ERR("Stopping PTP initialization\n"); | |
15615 | return; | |
15616 | } | |
15617 | ||
15618 | /* Init work queue for Tx timestamping */ | |
15619 | INIT_WORK(&bp->ptp_task, bnx2x_ptp_task); | |
15620 | ||
15621 | /* Init cyclecounter and timecounter. This is done only in the first | |
15622 | * load. If done in every load, PTP application will fail when doing | |
15623 | * unload / load (e.g. MTU change) while it is running. | |
15624 | */ | |
15625 | if (!bp->timecounter_init_done) { | |
15626 | bnx2x_init_cyclecounter(bp); | |
15627 | timecounter_init(&bp->timecounter, &bp->cyclecounter, | |
15628 | ktime_to_ns(ktime_get_real())); | |
15629 | bp->timecounter_init_done = 1; | |
15630 | } | |
15631 | ||
15632 | DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n"); | |
15633 | } |