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Commit | Line | Data |
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4ad79e13 | 1 | /* bnx2x_main.c: QLogic Everest network driver. |
a2fbb9ea | 2 | * |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
4ad79e13 YM |
4 | * Copyright (c) 2014 QLogic Corporation |
5 | * All rights reserved | |
a2fbb9ea ET |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
08f6dd89 | 11 | * Maintained by: Ariel Elior <ariel.elior@qlogic.com> |
24e3fcef | 12 | * Written by: Eliezer Tamir |
a2fbb9ea ET |
13 | * Based on code from Michael Chan's bnx2 driver |
14 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 15 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 16 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
17 | * |
18 | */ | |
19 | ||
f1deab50 JP |
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
21 | ||
a2fbb9ea ET |
22 | #include <linux/module.h> |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/device.h> /* for dev_info() */ | |
26 | #include <linux/timer.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/slab.h> | |
a2fbb9ea ET |
30 | #include <linux/interrupt.h> |
31 | #include <linux/pci.h> | |
33d8e6a5 | 32 | #include <linux/aer.h> |
a2fbb9ea ET |
33 | #include <linux/init.h> |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/etherdevice.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/dma-mapping.h> | |
38 | #include <linux/bitops.h> | |
39 | #include <linux/irq.h> | |
40 | #include <linux/delay.h> | |
41 | #include <asm/byteorder.h> | |
42 | #include <linux/time.h> | |
43 | #include <linux/ethtool.h> | |
44 | #include <linux/mii.h> | |
0c6671b0 | 45 | #include <linux/if_vlan.h> |
c9931896 | 46 | #include <linux/crash_dump.h> |
a2fbb9ea | 47 | #include <net/ip.h> |
619c5cb6 | 48 | #include <net/ipv6.h> |
a2fbb9ea | 49 | #include <net/tcp.h> |
51de7bb9 | 50 | #include <net/vxlan.h> |
a2fbb9ea | 51 | #include <net/checksum.h> |
34f80b04 | 52 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
53 | #include <linux/workqueue.h> |
54 | #include <linux/crc32.h> | |
34f80b04 | 55 | #include <linux/crc32c.h> |
a2fbb9ea ET |
56 | #include <linux/prefetch.h> |
57 | #include <linux/zlib.h> | |
a2fbb9ea | 58 | #include <linux/io.h> |
452427b0 | 59 | #include <linux/semaphore.h> |
45229b42 | 60 | #include <linux/stringify.h> |
7ab24bfd | 61 | #include <linux/vmalloc.h> |
a2fbb9ea ET |
62 | #include "bnx2x.h" |
63 | #include "bnx2x_init.h" | |
94a78b79 | 64 | #include "bnx2x_init_ops.h" |
9f6c9258 | 65 | #include "bnx2x_cmn.h" |
1ab4434c | 66 | #include "bnx2x_vfpf.h" |
e4901dde | 67 | #include "bnx2x_dcb.h" |
042181f5 | 68 | #include "bnx2x_sp.h" |
94a78b79 VZ |
69 | #include <linux/firmware.h> |
70 | #include "bnx2x_fw_file_hdr.h" | |
71 | /* FW files */ | |
45229b42 BH |
72 | #define FW_FILE_VERSION \ |
73 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
74 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
75 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
76 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
18bf8ca6 MC |
77 | |
78 | #define FW_FILE_VERSION_V15 \ | |
79 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
80 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
81 | __stringify(BCM_5710_FW_REVISION_VERSION_V15) "." \ | |
82 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
83 | ||
560131f3 DK |
84 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
85 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 86 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
18bf8ca6 MC |
87 | #define FW_FILE_NAME_E1_V15 "bnx2x/bnx2x-e1-" FW_FILE_VERSION_V15 ".fw" |
88 | #define FW_FILE_NAME_E1H_V15 "bnx2x/bnx2x-e1h-" FW_FILE_VERSION_V15 ".fw" | |
89 | #define FW_FILE_NAME_E2_V15 "bnx2x/bnx2x-e2-" FW_FILE_VERSION_V15 ".fw" | |
94a78b79 | 90 | |
34f80b04 EG |
91 | /* Time in jiffies before concluding the transmitter is hung */ |
92 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 93 | |
24e3fcef | 94 | MODULE_AUTHOR("Eliezer Tamir"); |
4ad79e13 | 95 | MODULE_DESCRIPTION("QLogic " |
619c5cb6 VZ |
96 | "BCM57710/57711/57711E/" |
97 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
98 | "57840/57840_MF Driver"); | |
a2fbb9ea | 99 | MODULE_LICENSE("GPL"); |
45229b42 BH |
100 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
101 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 102 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
afc08221 MC |
103 | MODULE_FIRMWARE(FW_FILE_NAME_E1_V15); |
104 | MODULE_FIRMWARE(FW_FILE_NAME_E1H_V15); | |
105 | MODULE_FIRMWARE(FW_FILE_NAME_E2_V15); | |
a2fbb9ea | 106 | |
a8f47eb7 | 107 | int bnx2x_num_queues; |
d3757ba4 | 108 | module_param_named(num_queues, bnx2x_num_queues, int, 0444); |
96305234 DK |
109 | MODULE_PARM_DESC(num_queues, |
110 | " Set number of queues (default is as a number of CPUs)"); | |
555f6c78 | 111 | |
19680c48 | 112 | static int disable_tpa; |
d3757ba4 | 113 | module_param(disable_tpa, int, 0444); |
9898f86d | 114 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 115 | |
a8f47eb7 | 116 | static int int_mode; |
d3757ba4 | 117 | module_param(int_mode, int, 0444); |
619c5cb6 | 118 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 119 | "(1 INT#x; 2 MSI)"); |
8badd27a | 120 | |
a18f5128 | 121 | static int dropless_fc; |
d3757ba4 | 122 | module_param(dropless_fc, int, 0444); |
a18f5128 EG |
123 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); |
124 | ||
8d5726c4 | 125 | static int mrrs = -1; |
d3757ba4 | 126 | module_param(mrrs, int, 0444); |
8d5726c4 EG |
127 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); |
128 | ||
9898f86d | 129 | static int debug; |
d3757ba4 | 130 | module_param(debug, int, 0444); |
9898f86d EG |
131 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
132 | ||
370d4a26 YM |
133 | static struct workqueue_struct *bnx2x_wq; |
134 | struct workqueue_struct *bnx2x_iov_wq; | |
ec6ba945 | 135 | |
1ef1d45a BW |
136 | struct bnx2x_mac_vals { |
137 | u32 xmac_addr; | |
138 | u32 xmac_val; | |
139 | u32 emac_addr; | |
140 | u32 emac_val; | |
3d6b7253 YM |
141 | u32 umac_addr[2]; |
142 | u32 umac_val[2]; | |
1ef1d45a BW |
143 | u32 bmac_addr; |
144 | u32 bmac_val[2]; | |
145 | }; | |
146 | ||
a2fbb9ea ET |
147 | enum bnx2x_board_type { |
148 | BCM57710 = 0, | |
619c5cb6 VZ |
149 | BCM57711, |
150 | BCM57711E, | |
151 | BCM57712, | |
152 | BCM57712_MF, | |
1ab4434c | 153 | BCM57712_VF, |
619c5cb6 VZ |
154 | BCM57800, |
155 | BCM57800_MF, | |
1ab4434c | 156 | BCM57800_VF, |
619c5cb6 VZ |
157 | BCM57810, |
158 | BCM57810_MF, | |
1ab4434c | 159 | BCM57810_VF, |
c3def943 YM |
160 | BCM57840_4_10, |
161 | BCM57840_2_20, | |
7e8e02df | 162 | BCM57840_MF, |
1ab4434c | 163 | BCM57840_VF, |
7e8e02df | 164 | BCM57811, |
1ab4434c AE |
165 | BCM57811_MF, |
166 | BCM57840_O, | |
167 | BCM57840_MFO, | |
168 | BCM57811_VF | |
a2fbb9ea ET |
169 | }; |
170 | ||
34f80b04 | 171 | /* indexed by board_type, above */ |
53a10565 | 172 | static struct { |
a2fbb9ea | 173 | char *name; |
0329aba1 | 174 | } board_info[] = { |
4ad79e13 YM |
175 | [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" }, |
176 | [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" }, | |
177 | [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" }, | |
178 | [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" }, | |
179 | [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" }, | |
180 | [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" }, | |
181 | [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" }, | |
182 | [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" }, | |
183 | [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" }, | |
184 | [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" }, | |
185 | [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" }, | |
186 | [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" }, | |
187 | [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" }, | |
188 | [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" }, | |
189 | [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
190 | [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }, | |
191 | [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" }, | |
192 | [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" }, | |
193 | [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" }, | |
194 | [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
195 | [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" } | |
a2fbb9ea ET |
196 | }; |
197 | ||
619c5cb6 VZ |
198 | #ifndef PCI_DEVICE_ID_NX2_57710 |
199 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
200 | #endif | |
201 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
202 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
203 | #endif | |
204 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
205 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
206 | #endif | |
207 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
208 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
209 | #endif | |
210 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
211 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
212 | #endif | |
8395be5e AE |
213 | #ifndef PCI_DEVICE_ID_NX2_57712_VF |
214 | #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF | |
215 | #endif | |
619c5cb6 VZ |
216 | #ifndef PCI_DEVICE_ID_NX2_57800 |
217 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
218 | #endif | |
219 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
220 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
221 | #endif | |
8395be5e AE |
222 | #ifndef PCI_DEVICE_ID_NX2_57800_VF |
223 | #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF | |
224 | #endif | |
619c5cb6 VZ |
225 | #ifndef PCI_DEVICE_ID_NX2_57810 |
226 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
227 | #endif | |
228 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
229 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
230 | #endif | |
c3def943 YM |
231 | #ifndef PCI_DEVICE_ID_NX2_57840_O |
232 | #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE | |
233 | #endif | |
8395be5e AE |
234 | #ifndef PCI_DEVICE_ID_NX2_57810_VF |
235 | #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF | |
236 | #endif | |
c3def943 YM |
237 | #ifndef PCI_DEVICE_ID_NX2_57840_4_10 |
238 | #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 | |
239 | #endif | |
240 | #ifndef PCI_DEVICE_ID_NX2_57840_2_20 | |
241 | #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 | |
242 | #endif | |
243 | #ifndef PCI_DEVICE_ID_NX2_57840_MFO | |
244 | #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE | |
619c5cb6 VZ |
245 | #endif |
246 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
247 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
248 | #endif | |
8395be5e AE |
249 | #ifndef PCI_DEVICE_ID_NX2_57840_VF |
250 | #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF | |
251 | #endif | |
7e8e02df BW |
252 | #ifndef PCI_DEVICE_ID_NX2_57811 |
253 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 | |
254 | #endif | |
255 | #ifndef PCI_DEVICE_ID_NX2_57811_MF | |
256 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF | |
257 | #endif | |
8395be5e AE |
258 | #ifndef PCI_DEVICE_ID_NX2_57811_VF |
259 | #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF | |
260 | #endif | |
261 | ||
9baa3c34 | 262 | static const struct pci_device_id bnx2x_pci_tbl[] = { |
e4ed7113 EG |
263 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
264 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
265 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 266 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 | 267 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
8395be5e | 268 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, |
619c5cb6 VZ |
269 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, |
270 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
8395be5e | 271 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, |
619c5cb6 VZ |
272 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, |
273 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
c3def943 YM |
274 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, |
275 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, | |
9c9a6524 | 276 | { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, |
c3def943 | 277 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, |
8395be5e | 278 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, |
c3def943 | 279 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, |
619c5cb6 | 280 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, |
9c9a6524 | 281 | { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, |
8395be5e | 282 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, |
9c9a6524 | 283 | { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, |
7e8e02df BW |
284 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
285 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, | |
8395be5e | 286 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, |
a2fbb9ea ET |
287 | { 0 } |
288 | }; | |
289 | ||
290 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
291 | ||
cdf711f2 SRK |
292 | const u32 dmae_reg_go_c[] = { |
293 | DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, | |
294 | DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, | |
295 | DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, | |
296 | DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 | |
297 | }; | |
298 | ||
452427b0 YM |
299 | /* Global resources for unloading a previously loaded device */ |
300 | #define BNX2X_PREV_WAIT_NEEDED 1 | |
301 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); | |
302 | static LIST_HEAD(bnx2x_prev_list); | |
a8f47eb7 | 303 | |
304 | /* Forward declaration */ | |
305 | static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); | |
306 | static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); | |
307 | static int bnx2x_set_storm_rx_mode(struct bnx2x *bp); | |
308 | ||
a2fbb9ea ET |
309 | /**************************************************************************** |
310 | * General service functions | |
311 | ****************************************************************************/ | |
312 | ||
eeed018c MK |
313 | static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr); |
314 | ||
1191cb83 | 315 | static void __storm_memset_dma_mapping(struct bnx2x *bp, |
619c5cb6 VZ |
316 | u32 addr, dma_addr_t mapping) |
317 | { | |
318 | REG_WR(bp, addr, U64_LO(mapping)); | |
319 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
320 | } | |
321 | ||
1191cb83 ED |
322 | static void storm_memset_spq_addr(struct bnx2x *bp, |
323 | dma_addr_t mapping, u16 abs_fid) | |
619c5cb6 VZ |
324 | { |
325 | u32 addr = XSEM_REG_FAST_MEMORY + | |
326 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
327 | ||
328 | __storm_memset_dma_mapping(bp, addr, mapping); | |
329 | } | |
330 | ||
1191cb83 ED |
331 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, |
332 | u16 pf_id) | |
523224a3 | 333 | { |
619c5cb6 VZ |
334 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
335 | pf_id); | |
336 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
337 | pf_id); | |
338 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
339 | pf_id); | |
340 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
341 | pf_id); | |
523224a3 DK |
342 | } |
343 | ||
1191cb83 ED |
344 | static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
345 | u8 enable) | |
619c5cb6 VZ |
346 | { |
347 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
348 | enable); | |
349 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
350 | enable); | |
351 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
352 | enable); | |
353 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
354 | enable); | |
355 | } | |
523224a3 | 356 | |
1191cb83 ED |
357 | static void storm_memset_eq_data(struct bnx2x *bp, |
358 | struct event_ring_data *eq_data, | |
523224a3 DK |
359 | u16 pfid) |
360 | { | |
361 | size_t size = sizeof(struct event_ring_data); | |
362 | ||
363 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
364 | ||
365 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
366 | } | |
367 | ||
1191cb83 ED |
368 | static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, |
369 | u16 pfid) | |
523224a3 DK |
370 | { |
371 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
372 | REG_WR16(bp, addr, eq_prod); | |
373 | } | |
374 | ||
a2fbb9ea ET |
375 | /* used only at init |
376 | * locking is done by mcp | |
377 | */ | |
8d96286a | 378 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
379 | { |
380 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
381 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
382 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
383 | PCICFG_VENDOR_ID_OFFSET); | |
384 | } | |
385 | ||
a2fbb9ea ET |
386 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
387 | { | |
388 | u32 val; | |
389 | ||
390 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
391 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
392 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
393 | PCICFG_VENDOR_ID_OFFSET); | |
394 | ||
395 | return val; | |
396 | } | |
a2fbb9ea | 397 | |
f2e0899f DK |
398 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
399 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
400 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
401 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
402 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
403 | ||
6bf07b8e YM |
404 | static void bnx2x_dp_dmae(struct bnx2x *bp, |
405 | struct dmae_command *dmae, int msglvl) | |
fd1fc79d AE |
406 | { |
407 | u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; | |
6bf07b8e | 408 | int i; |
fd1fc79d AE |
409 | |
410 | switch (dmae->opcode & DMAE_COMMAND_DST) { | |
411 | case DMAE_CMD_DST_PCI: | |
412 | if (src_type == DMAE_CMD_SRC_PCI) | |
413 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
414 | "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" | |
415 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
416 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
417 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
418 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
419 | dmae->comp_val); | |
420 | else | |
421 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
422 | "src [%08x], len [%d*4], dst [%x:%08x]\n" | |
423 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
424 | dmae->opcode, dmae->src_addr_lo >> 2, | |
425 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
426 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
427 | dmae->comp_val); | |
428 | break; | |
429 | case DMAE_CMD_DST_GRC: | |
430 | if (src_type == DMAE_CMD_SRC_PCI) | |
431 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
432 | "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" | |
433 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
434 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
435 | dmae->len, dmae->dst_addr_lo >> 2, | |
436 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
437 | dmae->comp_val); | |
438 | else | |
439 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
440 | "src [%08x], len [%d*4], dst [%08x]\n" | |
441 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
442 | dmae->opcode, dmae->src_addr_lo >> 2, | |
443 | dmae->len, dmae->dst_addr_lo >> 2, | |
444 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
445 | dmae->comp_val); | |
446 | break; | |
447 | default: | |
448 | if (src_type == DMAE_CMD_SRC_PCI) | |
449 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
450 | "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" | |
451 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
452 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
453 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
454 | dmae->comp_val); | |
455 | else | |
456 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
457 | "src_addr [%08x] len [%d * 4] dst_addr [none]\n" | |
458 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
459 | dmae->opcode, dmae->src_addr_lo >> 2, | |
460 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
461 | dmae->comp_val); | |
462 | break; | |
463 | } | |
6bf07b8e YM |
464 | |
465 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) | |
466 | DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", | |
467 | i, *(((u32 *)dmae) + i)); | |
fd1fc79d | 468 | } |
f2e0899f | 469 | |
a2fbb9ea | 470 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 471 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
472 | { |
473 | u32 cmd_offset; | |
474 | int i; | |
475 | ||
476 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
477 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
478 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
479 | } |
480 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
481 | } | |
482 | ||
f2e0899f | 483 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 484 | { |
f2e0899f DK |
485 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
486 | DMAE_CMD_C_ENABLE); | |
487 | } | |
ad8d3948 | 488 | |
f2e0899f DK |
489 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
490 | { | |
491 | return opcode & ~DMAE_CMD_SRC_RESET; | |
492 | } | |
ad8d3948 | 493 | |
f2e0899f DK |
494 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
495 | bool with_comp, u8 comp_type) | |
496 | { | |
497 | u32 opcode = 0; | |
498 | ||
499 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
500 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 501 | |
f2e0899f DK |
502 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
503 | ||
504 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
505 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
506 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 507 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 508 | |
a2fbb9ea | 509 | #ifdef __BIG_ENDIAN |
f2e0899f | 510 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 511 | #else |
f2e0899f | 512 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 513 | #endif |
f2e0899f DK |
514 | if (with_comp) |
515 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
516 | return opcode; | |
517 | } | |
518 | ||
fd1fc79d | 519 | void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
8d96286a | 520 | struct dmae_command *dmae, |
521 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
522 | { |
523 | memset(dmae, 0, sizeof(struct dmae_command)); | |
524 | ||
525 | /* set the opcode */ | |
526 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
527 | true, DMAE_COMP_PCI); | |
528 | ||
529 | /* fill in the completion parameters */ | |
530 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
531 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
532 | dmae->comp_val = DMAE_COMP_VAL; | |
533 | } | |
534 | ||
fd1fc79d | 535 | /* issue a dmae command over the init-channel and wait for completion */ |
32316a46 AE |
536 | int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, |
537 | u32 *comp) | |
f2e0899f | 538 | { |
5e374b5a | 539 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
540 | int rc = 0; |
541 | ||
6bf07b8e YM |
542 | bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); |
543 | ||
544 | /* Lock the dmae channel. Disable BHs to prevent a dead-lock | |
619c5cb6 VZ |
545 | * as long as this code is called both from syscall context and |
546 | * from ndo_set_rx_mode() flow that may be called from BH. | |
547 | */ | |
eeed018c | 548 | |
6e30dd4e | 549 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 550 | |
f2e0899f | 551 | /* reset completion */ |
32316a46 | 552 | *comp = 0; |
a2fbb9ea | 553 | |
f2e0899f DK |
554 | /* post the command on the channel used for initializations */ |
555 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 556 | |
f2e0899f | 557 | /* wait for completion */ |
a2fbb9ea | 558 | udelay(5); |
32316a46 | 559 | while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 | 560 | |
95c6c616 AE |
561 | if (!cnt || |
562 | (bp->recovery_state != BNX2X_RECOVERY_DONE && | |
563 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
c3eefaf6 | 564 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
565 | rc = DMAE_TIMEOUT; |
566 | goto unlock; | |
a2fbb9ea | 567 | } |
ad8d3948 | 568 | cnt--; |
f2e0899f | 569 | udelay(50); |
a2fbb9ea | 570 | } |
32316a46 | 571 | if (*comp & DMAE_PCI_ERR_FLAG) { |
f2e0899f DK |
572 | BNX2X_ERR("DMAE PCI error!\n"); |
573 | rc = DMAE_PCI_ERROR; | |
574 | } | |
575 | ||
f2e0899f | 576 | unlock: |
eeed018c | 577 | |
6e30dd4e | 578 | spin_unlock_bh(&bp->dmae_lock); |
eeed018c | 579 | |
f2e0899f DK |
580 | return rc; |
581 | } | |
582 | ||
583 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
584 | u32 len32) | |
585 | { | |
6bf07b8e | 586 | int rc; |
f2e0899f DK |
587 | struct dmae_command dmae; |
588 | ||
589 | if (!bp->dmae_ready) { | |
590 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
591 | ||
127a425e AE |
592 | if (CHIP_IS_E1(bp)) |
593 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
594 | else | |
595 | bnx2x_init_str_wr(bp, dst_addr, data, len32); | |
f2e0899f DK |
596 | return; |
597 | } | |
598 | ||
599 | /* set opcode and fixed command fields */ | |
600 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
601 | ||
602 | /* fill in addresses and len */ | |
603 | dmae.src_addr_lo = U64_LO(dma_addr); | |
604 | dmae.src_addr_hi = U64_HI(dma_addr); | |
605 | dmae.dst_addr_lo = dst_addr >> 2; | |
606 | dmae.dst_addr_hi = 0; | |
607 | dmae.len = len32; | |
608 | ||
f2e0899f | 609 | /* issue the command and wait for completion */ |
32316a46 | 610 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); |
6bf07b8e YM |
611 | if (rc) { |
612 | BNX2X_ERR("DMAE returned failure %d\n", rc); | |
9dcd9acd | 613 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e | 614 | bnx2x_panic(); |
9dcd9acd | 615 | #endif |
6bf07b8e | 616 | } |
a2fbb9ea ET |
617 | } |
618 | ||
c18487ee | 619 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 620 | { |
6bf07b8e | 621 | int rc; |
5ff7b6d4 | 622 | struct dmae_command dmae; |
ad8d3948 EG |
623 | |
624 | if (!bp->dmae_ready) { | |
625 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
626 | int i; | |
627 | ||
51c1a580 | 628 | if (CHIP_IS_E1(bp)) |
127a425e AE |
629 | for (i = 0; i < len32; i++) |
630 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
51c1a580 | 631 | else |
127a425e AE |
632 | for (i = 0; i < len32; i++) |
633 | data[i] = REG_RD(bp, src_addr + i*4); | |
634 | ||
ad8d3948 EG |
635 | return; |
636 | } | |
637 | ||
f2e0899f DK |
638 | /* set opcode and fixed command fields */ |
639 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 640 | |
f2e0899f | 641 | /* fill in addresses and len */ |
5ff7b6d4 EG |
642 | dmae.src_addr_lo = src_addr >> 2; |
643 | dmae.src_addr_hi = 0; | |
644 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
645 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
646 | dmae.len = len32; | |
ad8d3948 | 647 | |
f2e0899f | 648 | /* issue the command and wait for completion */ |
32316a46 | 649 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); |
6bf07b8e YM |
650 | if (rc) { |
651 | BNX2X_ERR("DMAE returned failure %d\n", rc); | |
9dcd9acd | 652 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e | 653 | bnx2x_panic(); |
9dcd9acd | 654 | #endif |
c957d09f | 655 | } |
ad8d3948 EG |
656 | } |
657 | ||
8d96286a | 658 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
659 | u32 addr, u32 len) | |
573f2035 | 660 | { |
02e3c6cb | 661 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
662 | int offset = 0; |
663 | ||
02e3c6cb | 664 | while (len > dmae_wr_max) { |
573f2035 | 665 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
666 | addr + offset, dmae_wr_max); |
667 | offset += dmae_wr_max * 4; | |
668 | len -= dmae_wr_max; | |
573f2035 EG |
669 | } |
670 | ||
671 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
672 | } | |
673 | ||
97539f1e AE |
674 | enum storms { |
675 | XSTORM, | |
676 | TSTORM, | |
677 | CSTORM, | |
678 | USTORM, | |
679 | MAX_STORMS | |
680 | }; | |
34f80b04 | 681 | |
97539f1e AE |
682 | #define STORMS_NUM 4 |
683 | #define REGS_IN_ENTRY 4 | |
34f80b04 | 684 | |
97539f1e AE |
685 | static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp, |
686 | enum storms storm, | |
687 | int entry) | |
688 | { | |
689 | switch (storm) { | |
690 | case XSTORM: | |
691 | return XSTORM_ASSERT_LIST_OFFSET(entry); | |
692 | case TSTORM: | |
693 | return TSTORM_ASSERT_LIST_OFFSET(entry); | |
694 | case CSTORM: | |
695 | return CSTORM_ASSERT_LIST_OFFSET(entry); | |
696 | case USTORM: | |
697 | return USTORM_ASSERT_LIST_OFFSET(entry); | |
698 | case MAX_STORMS: | |
699 | default: | |
700 | BNX2X_ERR("unknown storm\n"); | |
34f80b04 | 701 | } |
97539f1e AE |
702 | return -EINVAL; |
703 | } | |
34f80b04 | 704 | |
97539f1e AE |
705 | static int bnx2x_mc_assert(struct bnx2x *bp) |
706 | { | |
707 | char last_idx; | |
708 | int i, j, rc = 0; | |
709 | enum storms storm; | |
710 | u32 regs[REGS_IN_ENTRY]; | |
711 | u32 bar_storm_intmem[STORMS_NUM] = { | |
712 | BAR_XSTRORM_INTMEM, | |
713 | BAR_TSTRORM_INTMEM, | |
714 | BAR_CSTRORM_INTMEM, | |
715 | BAR_USTRORM_INTMEM | |
716 | }; | |
717 | u32 storm_assert_list_index[STORMS_NUM] = { | |
718 | XSTORM_ASSERT_LIST_INDEX_OFFSET, | |
719 | TSTORM_ASSERT_LIST_INDEX_OFFSET, | |
720 | CSTORM_ASSERT_LIST_INDEX_OFFSET, | |
721 | USTORM_ASSERT_LIST_INDEX_OFFSET | |
722 | }; | |
723 | char *storms_string[STORMS_NUM] = { | |
724 | "XSTORM", | |
725 | "TSTORM", | |
726 | "CSTORM", | |
727 | "USTORM" | |
728 | }; | |
729 | ||
730 | for (storm = XSTORM; storm < MAX_STORMS; storm++) { | |
731 | last_idx = REG_RD8(bp, bar_storm_intmem[storm] + | |
732 | storm_assert_list_index[storm]); | |
733 | if (last_idx) | |
734 | BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n", | |
735 | storms_string[storm], last_idx); | |
736 | ||
737 | /* print the asserts */ | |
738 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
739 | /* read a single assert entry */ | |
740 | for (j = 0; j < REGS_IN_ENTRY; j++) | |
741 | regs[j] = REG_RD(bp, bar_storm_intmem[storm] + | |
742 | bnx2x_get_assert_list_entry(bp, | |
743 | storm, | |
744 | i) + | |
745 | sizeof(u32) * j); | |
746 | ||
747 | /* log entry if it contains a valid assert */ | |
748 | if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
749 | BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
750 | storms_string[storm], i, regs[3], | |
751 | regs[2], regs[1], regs[0]); | |
752 | rc++; | |
753 | } else { | |
754 | break; | |
755 | } | |
a2fbb9ea ET |
756 | } |
757 | } | |
34f80b04 | 758 | |
97539f1e AE |
759 | BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n", |
760 | CHIP_IS_E1(bp) ? "everest1" : | |
761 | CHIP_IS_E1H(bp) ? "everest1h" : | |
762 | CHIP_IS_E2(bp) ? "everest2" : "everest3", | |
18bf8ca6 | 763 | bp->fw_major, bp->fw_minor, bp->fw_rev); |
97539f1e | 764 | |
a2fbb9ea ET |
765 | return rc; |
766 | } | |
c14423fe | 767 | |
1a6974b2 YM |
768 | #define MCPR_TRACE_BUFFER_SIZE (0x800) |
769 | #define SCRATCH_BUFFER_SIZE(bp) \ | |
770 | (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000)) | |
771 | ||
7a25cc73 | 772 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 773 | { |
7a25cc73 | 774 | u32 addr, val; |
a2fbb9ea | 775 | u32 mark, offset; |
4781bfad | 776 | __be32 data[9]; |
a2fbb9ea | 777 | int word; |
f2e0899f | 778 | u32 trace_shmem_base; |
2145a920 VZ |
779 | if (BP_NOMCP(bp)) { |
780 | BNX2X_ERR("NO MCP - can not dump\n"); | |
781 | return; | |
782 | } | |
7a25cc73 DK |
783 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
784 | (bp->common.bc_ver & 0xff0000) >> 16, | |
785 | (bp->common.bc_ver & 0xff00) >> 8, | |
786 | (bp->common.bc_ver & 0xff)); | |
787 | ||
b44e108b GP |
788 | if (pci_channel_offline(bp->pdev)) { |
789 | BNX2X_ERR("Cannot dump MCP info while in PCI error\n"); | |
790 | return; | |
791 | } | |
792 | ||
7a25cc73 DK |
793 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); |
794 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
51c1a580 | 795 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
cdaa7cb8 | 796 | |
f2e0899f DK |
797 | if (BP_PATH(bp) == 0) |
798 | trace_shmem_base = bp->common.shmem_base; | |
799 | else | |
800 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
1a6974b2 YM |
801 | |
802 | /* sanity */ | |
803 | if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE || | |
804 | trace_shmem_base >= MCPR_SCRATCH_BASE(bp) + | |
805 | SCRATCH_BUFFER_SIZE(bp)) { | |
806 | BNX2X_ERR("Unable to dump trace buffer (mark %x)\n", | |
807 | trace_shmem_base); | |
808 | return; | |
809 | } | |
810 | ||
811 | addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE; | |
de128804 DK |
812 | |
813 | /* validate TRCB signature */ | |
814 | mark = REG_RD(bp, addr); | |
815 | if (mark != MFW_TRACE_SIGNATURE) { | |
816 | BNX2X_ERR("Trace buffer signature is missing."); | |
817 | return ; | |
818 | } | |
819 | ||
820 | /* read cyclic buffer pointer */ | |
821 | addr += 4; | |
cdaa7cb8 | 822 | mark = REG_RD(bp, addr); |
1a6974b2 YM |
823 | mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000; |
824 | if (mark >= trace_shmem_base || mark < addr + 4) { | |
825 | BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n"); | |
826 | return; | |
827 | } | |
7a25cc73 | 828 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 829 | |
7a25cc73 | 830 | printk("%s", lvl); |
2de67439 YM |
831 | |
832 | /* dump buffer after the mark */ | |
1a6974b2 | 833 | for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 834 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 835 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 836 | data[8] = 0x0; |
7995c64e | 837 | pr_cont("%s", (char *)data); |
a2fbb9ea | 838 | } |
2de67439 YM |
839 | |
840 | /* dump buffer before the mark */ | |
cdaa7cb8 | 841 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 842 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 843 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 844 | data[8] = 0x0; |
7995c64e | 845 | pr_cont("%s", (char *)data); |
a2fbb9ea | 846 | } |
7a25cc73 DK |
847 | printk("%s" "end of fw dump\n", lvl); |
848 | } | |
849 | ||
1191cb83 | 850 | static void bnx2x_fw_dump(struct bnx2x *bp) |
7a25cc73 DK |
851 | { |
852 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
853 | } |
854 | ||
823e1d90 YM |
855 | static void bnx2x_hc_int_disable(struct bnx2x *bp) |
856 | { | |
857 | int port = BP_PORT(bp); | |
858 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; | |
859 | u32 val = REG_RD(bp, addr); | |
860 | ||
861 | /* in E1 we must use only PCI configuration space to disable | |
16a5fd92 YM |
862 | * MSI/MSIX capability |
863 | * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
823e1d90 YM |
864 | */ |
865 | if (CHIP_IS_E1(bp)) { | |
866 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
867 | * Use mask register to prevent from HC sending interrupts | |
868 | * after we exit the function | |
869 | */ | |
870 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
871 | ||
872 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
873 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
874 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
875 | } else | |
876 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
877 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
878 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
879 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
880 | ||
881 | DP(NETIF_MSG_IFDOWN, | |
882 | "write %x to HC %d (addr 0x%x)\n", | |
883 | val, port, addr); | |
884 | ||
823e1d90 YM |
885 | REG_WR(bp, addr, val); |
886 | if (REG_RD(bp, addr) != val) | |
6bf07b8e | 887 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
823e1d90 YM |
888 | } |
889 | ||
890 | static void bnx2x_igu_int_disable(struct bnx2x *bp) | |
891 | { | |
892 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
893 | ||
894 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
895 | IGU_PF_CONF_INT_LINE_EN | | |
896 | IGU_PF_CONF_ATTN_BIT_EN); | |
897 | ||
898 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); | |
899 | ||
823e1d90 YM |
900 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); |
901 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
6bf07b8e | 902 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
823e1d90 YM |
903 | } |
904 | ||
905 | static void bnx2x_int_disable(struct bnx2x *bp) | |
906 | { | |
907 | if (bp->common.int_block == INT_BLOCK_HC) | |
908 | bnx2x_hc_int_disable(bp); | |
909 | else | |
910 | bnx2x_igu_int_disable(bp); | |
911 | } | |
912 | ||
913 | void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) | |
a2fbb9ea ET |
914 | { |
915 | int i; | |
523224a3 DK |
916 | u16 j; |
917 | struct hc_sp_status_block_data sp_sb_data; | |
918 | int func = BP_FUNC(bp); | |
919 | #ifdef BNX2X_STOP_ON_ERROR | |
920 | u16 start = 0, end = 0; | |
6383c0b3 | 921 | u8 cos; |
523224a3 | 922 | #endif |
0155a27c | 923 | if (IS_PF(bp) && disable_int) |
823e1d90 | 924 | bnx2x_int_disable(bp); |
a2fbb9ea | 925 | |
66e855f3 | 926 | bp->stats_state = STATS_STATE_DISABLED; |
7a752993 | 927 | bp->eth_stats.unrecoverable_error++; |
66e855f3 YG |
928 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
929 | ||
a2fbb9ea ET |
930 | BNX2X_ERR("begin crash dump -----------------\n"); |
931 | ||
8440d2b6 EG |
932 | /* Indices */ |
933 | /* Common */ | |
0155a27c YM |
934 | if (IS_PF(bp)) { |
935 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
936 | int data_size, cstorm_offset; | |
937 | ||
938 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", | |
939 | bp->def_idx, bp->def_att_idx, bp->attn_state, | |
940 | bp->spq_prod_idx, bp->stats_counter); | |
941 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", | |
942 | def_sb->atten_status_block.attn_bits, | |
943 | def_sb->atten_status_block.attn_bits_ack, | |
944 | def_sb->atten_status_block.status_block_id, | |
945 | def_sb->atten_status_block.attn_bits_index); | |
946 | BNX2X_ERR(" def ("); | |
947 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
948 | pr_cont("0x%x%s", | |
949 | def_sb->sp_sb.index_values[i], | |
950 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
951 | ||
952 | data_size = sizeof(struct hc_sp_status_block_data) / | |
953 | sizeof(u32); | |
954 | cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func); | |
955 | for (i = 0; i < data_size; i++) | |
956 | *((u32 *)&sp_sb_data + i) = | |
957 | REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset + | |
958 | i * sizeof(u32)); | |
959 | ||
960 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", | |
961 | sp_sb_data.igu_sb_id, | |
962 | sp_sb_data.igu_seg_id, | |
963 | sp_sb_data.p_func.pf_id, | |
964 | sp_sb_data.p_func.vnic_id, | |
965 | sp_sb_data.p_func.vf_id, | |
966 | sp_sb_data.p_func.vf_valid, | |
967 | sp_sb_data.state); | |
968 | } | |
523224a3 | 969 | |
ec6ba945 | 970 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 971 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 972 | int loop; |
f2e0899f | 973 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
974 | struct hc_status_block_data_e1x sb_data_e1x; |
975 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
976 | CHIP_IS_E1x(bp) ? |
977 | sb_data_e1x.common.state_machine : | |
978 | sb_data_e2.common.state_machine; | |
523224a3 | 979 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
980 | CHIP_IS_E1x(bp) ? |
981 | sb_data_e1x.index_data : | |
982 | sb_data_e2.index_data; | |
6383c0b3 | 983 | u8 data_size, cos; |
523224a3 | 984 | u32 *sb_data_p; |
6383c0b3 | 985 | struct bnx2x_fp_txdata txdata; |
523224a3 | 986 | |
e2611998 YM |
987 | if (!bp->fp) |
988 | break; | |
989 | ||
990 | if (!fp->rx_cons_sb) | |
991 | continue; | |
992 | ||
523224a3 | 993 | /* Rx */ |
51c1a580 | 994 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 995 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 996 | fp->rx_comp_prod, |
66e855f3 | 997 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
51c1a580 | 998 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
8440d2b6 | 999 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 1000 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 1001 | |
523224a3 | 1002 | /* Tx */ |
6383c0b3 AE |
1003 | for_each_cos_in_tx_queue(fp, cos) |
1004 | { | |
1fc3de94 | 1005 | if (!fp->txdata_ptr[cos]) |
e2611998 YM |
1006 | break; |
1007 | ||
65565884 | 1008 | txdata = *fp->txdata_ptr[cos]; |
e2611998 YM |
1009 | |
1010 | if (!txdata.tx_cons_sb) | |
1011 | continue; | |
1012 | ||
51c1a580 | 1013 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
6383c0b3 AE |
1014 | i, txdata.tx_pkt_prod, |
1015 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
1016 | txdata.tx_bd_cons, | |
1017 | le16_to_cpu(*txdata.tx_cons_sb)); | |
1018 | } | |
523224a3 | 1019 | |
619c5cb6 VZ |
1020 | loop = CHIP_IS_E1x(bp) ? |
1021 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
1022 | |
1023 | /* host sb data */ | |
1024 | ||
ec6ba945 VZ |
1025 | if (IS_FCOE_FP(fp)) |
1026 | continue; | |
55c11941 | 1027 | |
523224a3 DK |
1028 | BNX2X_ERR(" run indexes ("); |
1029 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
1030 | pr_cont("0x%x%s", | |
1031 | fp->sb_running_index[j], | |
1032 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
1033 | ||
1034 | BNX2X_ERR(" indexes ("); | |
1035 | for (j = 0; j < loop; j++) | |
1036 | pr_cont("0x%x%s", | |
1037 | fp->sb_index_values[j], | |
1038 | (j == loop - 1) ? ")" : " "); | |
0155a27c YM |
1039 | |
1040 | /* VF cannot access FW refelection for status block */ | |
1041 | if (IS_VF(bp)) | |
1042 | continue; | |
1043 | ||
523224a3 | 1044 | /* fw sb data */ |
619c5cb6 VZ |
1045 | data_size = CHIP_IS_E1x(bp) ? |
1046 | sizeof(struct hc_status_block_data_e1x) : | |
1047 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 1048 | data_size /= sizeof(u32); |
619c5cb6 VZ |
1049 | sb_data_p = CHIP_IS_E1x(bp) ? |
1050 | (u32 *)&sb_data_e1x : | |
1051 | (u32 *)&sb_data_e2; | |
523224a3 DK |
1052 | /* copy sb data in here */ |
1053 | for (j = 0; j < data_size; j++) | |
1054 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
1055 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
1056 | j * sizeof(u32)); | |
1057 | ||
619c5cb6 | 1058 | if (!CHIP_IS_E1x(bp)) { |
51c1a580 | 1059 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
1060 | sb_data_e2.common.p_func.pf_id, |
1061 | sb_data_e2.common.p_func.vf_id, | |
1062 | sb_data_e2.common.p_func.vf_valid, | |
1063 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
1064 | sb_data_e2.common.same_igu_sb_1b, |
1065 | sb_data_e2.common.state); | |
f2e0899f | 1066 | } else { |
51c1a580 | 1067 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
1068 | sb_data_e1x.common.p_func.pf_id, |
1069 | sb_data_e1x.common.p_func.vf_id, | |
1070 | sb_data_e1x.common.p_func.vf_valid, | |
1071 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
1072 | sb_data_e1x.common.same_igu_sb_1b, |
1073 | sb_data_e1x.common.state); | |
f2e0899f | 1074 | } |
523224a3 DK |
1075 | |
1076 | /* SB_SMs data */ | |
1077 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
51c1a580 MS |
1078 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
1079 | j, hc_sm_p[j].__flags, | |
1080 | hc_sm_p[j].igu_sb_id, | |
1081 | hc_sm_p[j].igu_seg_id, | |
1082 | hc_sm_p[j].time_to_expire, | |
1083 | hc_sm_p[j].timer_value); | |
523224a3 DK |
1084 | } |
1085 | ||
16a5fd92 | 1086 | /* Indices data */ |
523224a3 | 1087 | for (j = 0; j < loop; j++) { |
51c1a580 | 1088 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
523224a3 DK |
1089 | hc_index_p[j].flags, |
1090 | hc_index_p[j].timeout); | |
1091 | } | |
8440d2b6 | 1092 | } |
a2fbb9ea | 1093 | |
523224a3 | 1094 | #ifdef BNX2X_STOP_ON_ERROR |
0155a27c YM |
1095 | if (IS_PF(bp)) { |
1096 | /* event queue */ | |
1097 | BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); | |
1098 | for (i = 0; i < NUM_EQ_DESC; i++) { | |
1099 | u32 *data = (u32 *)&bp->eq_ring[i].message.data; | |
1100 | ||
1101 | BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n", | |
1102 | i, bp->eq_ring[i].message.opcode, | |
1103 | bp->eq_ring[i].message.error); | |
1104 | BNX2X_ERR("data: %x %x %x\n", | |
1105 | data[0], data[1], data[2]); | |
1106 | } | |
04c46736 YM |
1107 | } |
1108 | ||
8440d2b6 EG |
1109 | /* Rings */ |
1110 | /* Rx */ | |
55c11941 | 1111 | for_each_valid_rx_queue(bp, i) { |
8440d2b6 | 1112 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1113 | |
e2611998 YM |
1114 | if (!bp->fp) |
1115 | break; | |
1116 | ||
1117 | if (!fp->rx_cons_sb) | |
1118 | continue; | |
1119 | ||
a2fbb9ea ET |
1120 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); |
1121 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 1122 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
1123 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
1124 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
1125 | ||
c3eefaf6 | 1126 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
44151acb | 1127 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
a2fbb9ea ET |
1128 | } |
1129 | ||
3196a88a EG |
1130 | start = RX_SGE(fp->rx_sge_prod); |
1131 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 1132 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
1133 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
1134 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
1135 | ||
c3eefaf6 EG |
1136 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
1137 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
1138 | } |
1139 | ||
a2fbb9ea ET |
1140 | start = RCQ_BD(fp->rx_comp_cons - 10); |
1141 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 1142 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
1143 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
1144 | ||
c3eefaf6 EG |
1145 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
1146 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
1147 | } |
1148 | } | |
1149 | ||
8440d2b6 | 1150 | /* Tx */ |
55c11941 | 1151 | for_each_valid_tx_queue(bp, i) { |
8440d2b6 | 1152 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
e2611998 YM |
1153 | |
1154 | if (!bp->fp) | |
1155 | break; | |
1156 | ||
6383c0b3 | 1157 | for_each_cos_in_tx_queue(fp, cos) { |
65565884 | 1158 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
6383c0b3 | 1159 | |
1fc3de94 | 1160 | if (!fp->txdata_ptr[cos]) |
e2611998 YM |
1161 | break; |
1162 | ||
ea36475a | 1163 | if (!txdata->tx_cons_sb) |
e2611998 YM |
1164 | continue; |
1165 | ||
6383c0b3 AE |
1166 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); |
1167 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
1168 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1169 | struct sw_tx_bd *sw_bd = | |
1170 | &txdata->tx_buf_ring[j]; | |
1171 | ||
51c1a580 | 1172 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
6383c0b3 AE |
1173 | i, cos, j, sw_bd->skb, |
1174 | sw_bd->first_bd); | |
1175 | } | |
8440d2b6 | 1176 | |
6383c0b3 AE |
1177 | start = TX_BD(txdata->tx_bd_cons - 10); |
1178 | end = TX_BD(txdata->tx_bd_cons + 254); | |
1179 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1180 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 1181 | |
51c1a580 | 1182 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
6383c0b3 AE |
1183 | i, cos, j, tx_bd[0], tx_bd[1], |
1184 | tx_bd[2], tx_bd[3]); | |
1185 | } | |
8440d2b6 EG |
1186 | } |
1187 | } | |
523224a3 | 1188 | #endif |
0155a27c | 1189 | if (IS_PF(bp)) { |
a4666570 SRK |
1190 | int tmp_msg_en = bp->msg_enable; |
1191 | ||
0155a27c | 1192 | bnx2x_fw_dump(bp); |
a4666570 SRK |
1193 | bp->msg_enable |= NETIF_MSG_HW; |
1194 | BNX2X_ERR("Idle check (1st round) ----------\n"); | |
1195 | bnx2x_idle_chk(bp); | |
1196 | BNX2X_ERR("Idle check (2nd round) ----------\n"); | |
1197 | bnx2x_idle_chk(bp); | |
1198 | bp->msg_enable = tmp_msg_en; | |
0155a27c YM |
1199 | bnx2x_mc_assert(bp); |
1200 | } | |
a4666570 | 1201 | |
a2fbb9ea | 1202 | BNX2X_ERR("end crash dump -----------------\n"); |
a2fbb9ea ET |
1203 | } |
1204 | ||
619c5cb6 VZ |
1205 | /* |
1206 | * FLR Support for E2 | |
1207 | * | |
1208 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
1209 | * initialization. | |
1210 | */ | |
16a5fd92 | 1211 | #define FLR_WAIT_USEC 10000 /* 10 milliseconds */ |
89db4ad8 AE |
1212 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
1213 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ | |
619c5cb6 VZ |
1214 | |
1215 | struct pbf_pN_buf_regs { | |
1216 | int pN; | |
1217 | u32 init_crd; | |
1218 | u32 crd; | |
1219 | u32 crd_freed; | |
1220 | }; | |
1221 | ||
1222 | struct pbf_pN_cmd_regs { | |
1223 | int pN; | |
1224 | u32 lines_occup; | |
1225 | u32 lines_freed; | |
1226 | }; | |
1227 | ||
1228 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
1229 | struct pbf_pN_buf_regs *regs, | |
1230 | u32 poll_count) | |
1231 | { | |
1232 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
1233 | u32 cur_cnt = poll_count; | |
1234 | ||
1235 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
1236 | crd = crd_start = REG_RD(bp, regs->crd); | |
1237 | init_crd = REG_RD(bp, regs->init_crd); | |
1238 | ||
1239 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
1240 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
1241 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
1242 | ||
1243 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
1244 | (init_crd - crd_start))) { | |
1245 | if (cur_cnt--) { | |
89db4ad8 | 1246 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1247 | crd = REG_RD(bp, regs->crd); |
1248 | crd_freed = REG_RD(bp, regs->crd_freed); | |
1249 | } else { | |
1250 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
1251 | regs->pN); | |
1252 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
1253 | regs->pN, crd); | |
1254 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
1255 | regs->pN, crd_freed); | |
1256 | break; | |
1257 | } | |
1258 | } | |
1259 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
89db4ad8 | 1260 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1261 | } |
1262 | ||
1263 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
1264 | struct pbf_pN_cmd_regs *regs, | |
1265 | u32 poll_count) | |
1266 | { | |
1267 | u32 occup, to_free, freed, freed_start; | |
1268 | u32 cur_cnt = poll_count; | |
1269 | ||
1270 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
1271 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
1272 | ||
1273 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
1274 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
1275 | ||
1276 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
1277 | if (cur_cnt--) { | |
89db4ad8 | 1278 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1279 | occup = REG_RD(bp, regs->lines_occup); |
1280 | freed = REG_RD(bp, regs->lines_freed); | |
1281 | } else { | |
1282 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
1283 | regs->pN); | |
1284 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
1285 | regs->pN, occup); | |
1286 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
1287 | regs->pN, freed); | |
1288 | break; | |
1289 | } | |
1290 | } | |
1291 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
89db4ad8 | 1292 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1293 | } |
1294 | ||
1191cb83 ED |
1295 | static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, |
1296 | u32 expected, u32 poll_count) | |
619c5cb6 VZ |
1297 | { |
1298 | u32 cur_cnt = poll_count; | |
1299 | u32 val; | |
1300 | ||
1301 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
89db4ad8 | 1302 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1303 | |
1304 | return val; | |
1305 | } | |
1306 | ||
d16132ce AE |
1307 | int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, |
1308 | char *msg, u32 poll_cnt) | |
619c5cb6 VZ |
1309 | { |
1310 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1311 | if (val != 0) { | |
1312 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1313 | return 1; | |
1314 | } | |
1315 | return 0; | |
1316 | } | |
1317 | ||
d16132ce AE |
1318 | /* Common routines with VF FLR cleanup */ |
1319 | u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
619c5cb6 VZ |
1320 | { |
1321 | /* adjust polling timeout */ | |
1322 | if (CHIP_REV_IS_EMUL(bp)) | |
1323 | return FLR_POLL_CNT * 2000; | |
1324 | ||
1325 | if (CHIP_REV_IS_FPGA(bp)) | |
1326 | return FLR_POLL_CNT * 120; | |
1327 | ||
1328 | return FLR_POLL_CNT; | |
1329 | } | |
1330 | ||
d16132ce | 1331 | void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) |
619c5cb6 VZ |
1332 | { |
1333 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1334 | {0, (CHIP_IS_E3B0(bp)) ? | |
1335 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1336 | PBF_REG_P0_TQ_OCCUPANCY, | |
1337 | (CHIP_IS_E3B0(bp)) ? | |
1338 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1339 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1340 | {1, (CHIP_IS_E3B0(bp)) ? | |
1341 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1342 | PBF_REG_P1_TQ_OCCUPANCY, | |
1343 | (CHIP_IS_E3B0(bp)) ? | |
1344 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1345 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1346 | {4, (CHIP_IS_E3B0(bp)) ? | |
1347 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1348 | PBF_REG_P4_TQ_OCCUPANCY, | |
1349 | (CHIP_IS_E3B0(bp)) ? | |
1350 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1351 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1352 | }; | |
1353 | ||
1354 | struct pbf_pN_buf_regs buf_regs[] = { | |
1355 | {0, (CHIP_IS_E3B0(bp)) ? | |
1356 | PBF_REG_INIT_CRD_Q0 : | |
1357 | PBF_REG_P0_INIT_CRD , | |
1358 | (CHIP_IS_E3B0(bp)) ? | |
1359 | PBF_REG_CREDIT_Q0 : | |
1360 | PBF_REG_P0_CREDIT, | |
1361 | (CHIP_IS_E3B0(bp)) ? | |
1362 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1363 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1364 | {1, (CHIP_IS_E3B0(bp)) ? | |
1365 | PBF_REG_INIT_CRD_Q1 : | |
1366 | PBF_REG_P1_INIT_CRD, | |
1367 | (CHIP_IS_E3B0(bp)) ? | |
1368 | PBF_REG_CREDIT_Q1 : | |
1369 | PBF_REG_P1_CREDIT, | |
1370 | (CHIP_IS_E3B0(bp)) ? | |
1371 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1372 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1373 | {4, (CHIP_IS_E3B0(bp)) ? | |
1374 | PBF_REG_INIT_CRD_LB_Q : | |
1375 | PBF_REG_P4_INIT_CRD, | |
1376 | (CHIP_IS_E3B0(bp)) ? | |
1377 | PBF_REG_CREDIT_LB_Q : | |
1378 | PBF_REG_P4_CREDIT, | |
1379 | (CHIP_IS_E3B0(bp)) ? | |
1380 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1381 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1382 | }; | |
1383 | ||
1384 | int i; | |
1385 | ||
1386 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1387 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1388 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1389 | ||
619c5cb6 VZ |
1390 | /* Verify the transmission buffers are flushed P0, P1, P4 */ |
1391 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1392 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1393 | } | |
1394 | ||
1395 | #define OP_GEN_PARAM(param) \ | |
1396 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1397 | ||
1398 | #define OP_GEN_TYPE(type) \ | |
1399 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1400 | ||
1401 | #define OP_GEN_AGG_VECT(index) \ | |
1402 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1403 | ||
d16132ce | 1404 | int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) |
619c5cb6 | 1405 | { |
86564c3f | 1406 | u32 op_gen_command = 0; |
619c5cb6 VZ |
1407 | u32 comp_addr = BAR_CSTRORM_INTMEM + |
1408 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
619c5cb6 VZ |
1409 | |
1410 | if (REG_RD(bp, comp_addr)) { | |
89db4ad8 | 1411 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
619c5cb6 VZ |
1412 | return 1; |
1413 | } | |
1414 | ||
86564c3f YM |
1415 | op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); |
1416 | op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1417 | op_gen_command |= OP_GEN_AGG_VECT(clnup_func); | |
1418 | op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
619c5cb6 | 1419 | |
89db4ad8 | 1420 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
86564c3f | 1421 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); |
619c5cb6 VZ |
1422 | |
1423 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1424 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
51c1a580 MS |
1425 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
1426 | (REG_RD(bp, comp_addr))); | |
d16132ce AE |
1427 | bnx2x_panic(); |
1428 | return 1; | |
619c5cb6 | 1429 | } |
16a5fd92 | 1430 | /* Zero completion for next FLR */ |
619c5cb6 VZ |
1431 | REG_WR(bp, comp_addr, 0); |
1432 | ||
f0744a84 | 1433 | return 0; |
619c5cb6 VZ |
1434 | } |
1435 | ||
b56e9670 | 1436 | u8 bnx2x_is_pcie_pending(struct pci_dev *dev) |
619c5cb6 | 1437 | { |
619c5cb6 VZ |
1438 | u16 status; |
1439 | ||
2a80eebc | 1440 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
619c5cb6 VZ |
1441 | return status & PCI_EXP_DEVSTA_TRPND; |
1442 | } | |
1443 | ||
1444 | /* PF FLR specific routines | |
1445 | */ | |
1446 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1447 | { | |
619c5cb6 VZ |
1448 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ |
1449 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1450 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1451 | "CFC PF usage counter timed out", | |
1452 | poll_cnt)) | |
1453 | return 1; | |
1454 | ||
619c5cb6 VZ |
1455 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ |
1456 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1457 | DORQ_REG_PF_USAGE_CNT, | |
1458 | "DQ PF usage counter timed out", | |
1459 | poll_cnt)) | |
1460 | return 1; | |
1461 | ||
1462 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1463 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1464 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1465 | "QM PF usage counter timed out", | |
1466 | poll_cnt)) | |
1467 | return 1; | |
1468 | ||
1469 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1470 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1471 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1472 | "Timers VNIC usage counter timed out", | |
1473 | poll_cnt)) | |
1474 | return 1; | |
1475 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1476 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1477 | "Timers NUM_SCANS usage counter timed out", | |
1478 | poll_cnt)) | |
1479 | return 1; | |
1480 | ||
1481 | /* Wait DMAE PF usage counter to zero */ | |
1482 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1483 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
6bf07b8e | 1484 | "DMAE command register timed out", |
619c5cb6 VZ |
1485 | poll_cnt)) |
1486 | return 1; | |
1487 | ||
1488 | return 0; | |
1489 | } | |
1490 | ||
1491 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1492 | { | |
1493 | u32 val; | |
1494 | ||
1495 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1496 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1497 | ||
1498 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1499 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1500 | ||
1501 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1502 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1503 | ||
1504 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1505 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1506 | ||
1507 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1508 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1509 | ||
1510 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1511 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1512 | ||
1513 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1514 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1515 | ||
1516 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1517 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1518 | val); | |
1519 | } | |
1520 | ||
1521 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1522 | { | |
1523 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1524 | ||
1525 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1526 | ||
1527 | /* Re-enable PF target read access */ | |
1528 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1529 | ||
1530 | /* Poll HW usage counters */ | |
89db4ad8 | 1531 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
619c5cb6 VZ |
1532 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
1533 | return -EBUSY; | |
1534 | ||
1535 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1536 | ||
1537 | /* Send the FW cleanup command */ | |
1538 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1539 | return -EBUSY; | |
1540 | ||
1541 | /* ATC cleanup */ | |
1542 | ||
1543 | /* Verify TX hw is flushed */ | |
1544 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1545 | ||
1546 | /* Wait 100ms (not adjusted according to platform) */ | |
1547 | msleep(100); | |
1548 | ||
1549 | /* Verify no pending pci transactions */ | |
1550 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1551 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1552 | ||
1553 | /* Debug */ | |
1554 | bnx2x_hw_enable_status(bp); | |
1555 | ||
1556 | /* | |
1557 | * Master enable - Due to WB DMAE writes performed before this | |
1558 | * register is re-initialized as part of the regular function init | |
1559 | */ | |
1560 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1561 | ||
1562 | return 0; | |
1563 | } | |
1564 | ||
f2e0899f | 1565 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1566 | { |
34f80b04 | 1567 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1568 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1569 | u32 val = REG_RD(bp, addr); | |
69c326b3 DK |
1570 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1571 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1572 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
a2fbb9ea ET |
1573 | |
1574 | if (msix) { | |
8badd27a EG |
1575 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1576 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1577 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1578 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
69c326b3 DK |
1579 | if (single_msix) |
1580 | val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; | |
8badd27a EG |
1581 | } else if (msi) { |
1582 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1583 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1584 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1585 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1586 | } else { |
1587 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1588 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1589 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1590 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1591 | |
a0fd065c | 1592 | if (!CHIP_IS_E1(bp)) { |
51c1a580 MS |
1593 | DP(NETIF_MSG_IFUP, |
1594 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); | |
615f8fd9 | 1595 | |
a0fd065c | 1596 | REG_WR(bp, addr, val); |
615f8fd9 | 1597 | |
a0fd065c DK |
1598 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1599 | } | |
a2fbb9ea ET |
1600 | } |
1601 | ||
a0fd065c DK |
1602 | if (CHIP_IS_E1(bp)) |
1603 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1604 | ||
51c1a580 MS |
1605 | DP(NETIF_MSG_IFUP, |
1606 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, | |
1607 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1608 | |
1609 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1610 | /* |
1611 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1612 | */ | |
37dbbf32 | 1613 | barrier(); |
34f80b04 | 1614 | |
f2e0899f | 1615 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1616 | /* init leading/trailing edge */ |
fb3bff17 | 1617 | if (IS_MF(bp)) { |
3395a033 | 1618 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1619 | if (bp->port.pmf) |
4acac6a5 EG |
1620 | /* enable nig and gpio3 attention */ |
1621 | val |= 0x1100; | |
34f80b04 EG |
1622 | } else |
1623 | val = 0xffff; | |
1624 | ||
1625 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1626 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1627 | } | |
a2fbb9ea ET |
1628 | } |
1629 | ||
f2e0899f DK |
1630 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1631 | { | |
1632 | u32 val; | |
30a5de77 DK |
1633 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1634 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1635 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
f2e0899f DK |
1636 | |
1637 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1638 | ||
1639 | if (msix) { | |
1640 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1641 | IGU_PF_CONF_SINGLE_ISR_EN); | |
ebe61d80 | 1642 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
f2e0899f | 1643 | IGU_PF_CONF_ATTN_BIT_EN); |
30a5de77 DK |
1644 | |
1645 | if (single_msix) | |
1646 | val |= IGU_PF_CONF_SINGLE_ISR_EN; | |
f2e0899f DK |
1647 | } else if (msi) { |
1648 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
ebe61d80 | 1649 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
f2e0899f DK |
1650 | IGU_PF_CONF_ATTN_BIT_EN | |
1651 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1652 | } else { | |
1653 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
ebe61d80 | 1654 | val |= (IGU_PF_CONF_INT_LINE_EN | |
f2e0899f DK |
1655 | IGU_PF_CONF_ATTN_BIT_EN | |
1656 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1657 | } | |
1658 | ||
ebe61d80 YM |
1659 | /* Clean previous status - need to configure igu prior to ack*/ |
1660 | if ((!msix) || single_msix) { | |
1661 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1662 | bnx2x_ack_int(bp); | |
1663 | } | |
1664 | ||
1665 | val |= IGU_PF_CONF_FUNC_EN; | |
1666 | ||
51c1a580 | 1667 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
f2e0899f DK |
1668 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
1669 | ||
1670 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1671 | ||
79a8557a YM |
1672 | if (val & IGU_PF_CONF_INT_LINE_EN) |
1673 | pci_intx(bp->pdev, true); | |
1674 | ||
f2e0899f DK |
1675 | barrier(); |
1676 | ||
1677 | /* init leading/trailing edge */ | |
1678 | if (IS_MF(bp)) { | |
3395a033 | 1679 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1680 | if (bp->port.pmf) |
1681 | /* enable nig and gpio3 attention */ | |
1682 | val |= 0x1100; | |
1683 | } else | |
1684 | val = 0xffff; | |
1685 | ||
1686 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1687 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
f2e0899f DK |
1688 | } |
1689 | ||
1690 | void bnx2x_int_enable(struct bnx2x *bp) | |
1691 | { | |
1692 | if (bp->common.int_block == INT_BLOCK_HC) | |
1693 | bnx2x_hc_int_enable(bp); | |
1694 | else | |
1695 | bnx2x_igu_int_enable(bp); | |
1696 | } | |
1697 | ||
9f6c9258 | 1698 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1699 | { |
a2fbb9ea | 1700 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1701 | int i, offset; |
a2fbb9ea | 1702 | |
f8ef6e44 YG |
1703 | if (disable_hw) |
1704 | /* prevent the HW from sending interrupts */ | |
1705 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1706 | |
1707 | /* make sure all ISRs are done */ | |
1708 | if (msix) { | |
8badd27a EG |
1709 | synchronize_irq(bp->msix_table[0].vector); |
1710 | offset = 1; | |
55c11941 MS |
1711 | if (CNIC_SUPPORT(bp)) |
1712 | offset++; | |
ec6ba945 | 1713 | for_each_eth_queue(bp, i) |
754a2f52 | 1714 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1715 | } else |
1716 | synchronize_irq(bp->pdev->irq); | |
1717 | ||
1718 | /* make sure sp_task is not running */ | |
1cf167f2 | 1719 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1720 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1721 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1722 | } |
1723 | ||
34f80b04 | 1724 | /* fast path */ |
a2fbb9ea ET |
1725 | |
1726 | /* | |
34f80b04 | 1727 | * General service functions |
a2fbb9ea ET |
1728 | */ |
1729 | ||
72fd0718 VZ |
1730 | /* Return true if succeeded to acquire the lock */ |
1731 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1732 | { | |
1733 | u32 lock_status; | |
1734 | u32 resource_bit = (1 << resource); | |
1735 | int func = BP_FUNC(bp); | |
1736 | u32 hw_lock_control_reg; | |
1737 | ||
51c1a580 MS |
1738 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1739 | "Trying to take a lock on resource %d\n", resource); | |
72fd0718 VZ |
1740 | |
1741 | /* Validating that the resource is within range */ | |
1742 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1743 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
72fd0718 VZ |
1744 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
1745 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1746 | return false; |
72fd0718 VZ |
1747 | } |
1748 | ||
1749 | if (func <= 5) | |
1750 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1751 | else | |
1752 | hw_lock_control_reg = | |
1753 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1754 | ||
1755 | /* Try to acquire the lock */ | |
1756 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1757 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1758 | if (lock_status & resource_bit) | |
1759 | return true; | |
1760 | ||
51c1a580 MS |
1761 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1762 | "Failed to get a lock on resource %d\n", resource); | |
72fd0718 VZ |
1763 | return false; |
1764 | } | |
1765 | ||
c9ee9206 VZ |
1766 | /** |
1767 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1768 | * | |
1769 | * @bp: driver handle | |
1770 | * | |
1771 | * Returns the recovery leader resource id according to the engine this function | |
1772 | * belongs to. Currently only only 2 engines is supported. | |
1773 | */ | |
1191cb83 | 1774 | static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) |
c9ee9206 VZ |
1775 | { |
1776 | if (BP_PATH(bp)) | |
1777 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1778 | else | |
1779 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1780 | } | |
1781 | ||
1782 | /** | |
2de67439 | 1783 | * bnx2x_trylock_leader_lock- try to acquire a leader lock. |
c9ee9206 VZ |
1784 | * |
1785 | * @bp: driver handle | |
1786 | * | |
2de67439 | 1787 | * Tries to acquire a leader lock for current engine. |
c9ee9206 | 1788 | */ |
1191cb83 | 1789 | static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) |
c9ee9206 VZ |
1790 | { |
1791 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1792 | } | |
1793 | ||
619c5cb6 | 1794 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
55c11941 | 1795 | |
fd1fc79d AE |
1796 | /* schedule the sp task and mark that interrupt occurred (runs from ISR) */ |
1797 | static int bnx2x_schedule_sp_task(struct bnx2x *bp) | |
1798 | { | |
1799 | /* Set the interrupt occurred bit for the sp-task to recognize it | |
1800 | * must ack the interrupt and transition according to the IGU | |
1801 | * state machine. | |
1802 | */ | |
1803 | atomic_set(&bp->interrupt_occurred, 1); | |
1804 | ||
1805 | /* The sp_task must execute only after this bit | |
1806 | * is set, otherwise we will get out of sync and miss all | |
1807 | * further interrupts. Hence, the barrier. | |
1808 | */ | |
1809 | smp_wmb(); | |
1810 | ||
1811 | /* schedule sp_task to workqueue */ | |
1812 | return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); | |
1813 | } | |
3196a88a | 1814 | |
619c5cb6 | 1815 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1816 | { |
1817 | struct bnx2x *bp = fp->bp; | |
1818 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1819 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 | 1820 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
15192a8c | 1821 | struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a2fbb9ea | 1822 | |
34f80b04 | 1823 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1824 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1825 | fp->index, cid, command, bp->state, |
34f80b04 | 1826 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1827 | |
fd1fc79d AE |
1828 | /* If cid is within VF range, replace the slowpath object with the |
1829 | * one corresponding to this VF | |
1830 | */ | |
1831 | if (cid >= BNX2X_FIRST_VF_CID && | |
1832 | cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) | |
1833 | bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); | |
1834 | ||
619c5cb6 VZ |
1835 | switch (command) { |
1836 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1837 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1838 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1839 | break; | |
d6cae238 | 1840 | |
619c5cb6 | 1841 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1842 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1843 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1844 | break; |
1845 | ||
6383c0b3 | 1846 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
51c1a580 | 1847 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
6383c0b3 AE |
1848 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
1849 | break; | |
1850 | ||
619c5cb6 | 1851 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1852 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1853 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1854 | break; |
1855 | ||
619c5cb6 | 1856 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
6bf07b8e | 1857 | DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid); |
619c5cb6 | 1858 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1859 | break; |
1860 | ||
619c5cb6 | 1861 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1862 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1863 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1864 | break; |
619c5cb6 | 1865 | |
14a94ebd MK |
1866 | case (RAMROD_CMD_ID_ETH_TPA_UPDATE): |
1867 | DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid); | |
1868 | drv_cmd = BNX2X_Q_CMD_UPDATE_TPA; | |
1869 | break; | |
1870 | ||
619c5cb6 VZ |
1871 | default: |
1872 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1873 | command, fp->index); | |
1874 | return; | |
523224a3 | 1875 | } |
3196a88a | 1876 | |
619c5cb6 VZ |
1877 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1878 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1879 | /* q_obj->complete_cmd() failure means that this was | |
1880 | * an unexpected completion. | |
1881 | * | |
1882 | * In this case we don't want to increase the bp->spq_left | |
1883 | * because apparently we haven't sent this command the first | |
1884 | * place. | |
1885 | */ | |
1886 | #ifdef BNX2X_STOP_ON_ERROR | |
1887 | bnx2x_panic(); | |
1888 | #else | |
1889 | return; | |
1890 | #endif | |
1891 | ||
4e857c58 | 1892 | smp_mb__before_atomic(); |
6e30dd4e | 1893 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 | 1894 | /* push the change in bp->spq_left and towards the memory */ |
4e857c58 | 1895 | smp_mb__after_atomic(); |
49d66772 | 1896 | |
d6cae238 VZ |
1897 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1898 | ||
a3348722 BW |
1899 | if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && |
1900 | (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { | |
1901 | /* if Q update ramrod is completed for last Q in AFEX vif set | |
1902 | * flow, then ACK MCP at the end | |
1903 | * | |
1904 | * mark pending ACK to MCP bit. | |
1905 | * prevent case that both bits are cleared. | |
1906 | * At the end of load/unload driver checks that | |
2de67439 | 1907 | * sp_state is cleared, and this order prevents |
a3348722 BW |
1908 | * races |
1909 | */ | |
4e857c58 | 1910 | smp_mb__before_atomic(); |
a3348722 BW |
1911 | set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); |
1912 | wmb(); | |
1913 | clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
4e857c58 | 1914 | smp_mb__after_atomic(); |
a3348722 | 1915 | |
fd1fc79d AE |
1916 | /* schedule the sp task as mcp ack is required */ |
1917 | bnx2x_schedule_sp_task(bp); | |
a3348722 BW |
1918 | } |
1919 | ||
523224a3 | 1920 | return; |
a2fbb9ea ET |
1921 | } |
1922 | ||
9f6c9258 | 1923 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1924 | { |
555f6c78 | 1925 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1926 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1927 | u16 mask; |
ca00392c | 1928 | int i; |
6383c0b3 | 1929 | u8 cos; |
a2fbb9ea | 1930 | |
34f80b04 | 1931 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1932 | if (unlikely(status == 0)) { |
1933 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1934 | return IRQ_NONE; | |
1935 | } | |
f5372251 | 1936 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1937 | |
3196a88a EG |
1938 | #ifdef BNX2X_STOP_ON_ERROR |
1939 | if (unlikely(bp->panic)) | |
1940 | return IRQ_HANDLED; | |
1941 | #endif | |
1942 | ||
ec6ba945 | 1943 | for_each_eth_queue(bp, i) { |
ca00392c | 1944 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1945 | |
55c11941 | 1946 | mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); |
ca00392c | 1947 | if (status & mask) { |
619c5cb6 | 1948 | /* Handle Rx or Tx according to SB id */ |
6383c0b3 | 1949 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 1950 | prefetch(fp->txdata_ptr[cos]->tx_cons_sb); |
523224a3 | 1951 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
f5fbf115 | 1952 | napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1953 | status &= ~mask; |
1954 | } | |
a2fbb9ea ET |
1955 | } |
1956 | ||
55c11941 MS |
1957 | if (CNIC_SUPPORT(bp)) { |
1958 | mask = 0x2; | |
1959 | if (status & (mask | 0x1)) { | |
1960 | struct cnic_ops *c_ops = NULL; | |
993ac7b5 | 1961 | |
ad9b4359 MC |
1962 | rcu_read_lock(); |
1963 | c_ops = rcu_dereference(bp->cnic_ops); | |
1964 | if (c_ops && (bp->cnic_eth_dev.drv_state & | |
1965 | CNIC_DRV_STATE_HANDLES_IRQ)) | |
1966 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1967 | rcu_read_unlock(); | |
993ac7b5 | 1968 | |
55c11941 MS |
1969 | status &= ~mask; |
1970 | } | |
993ac7b5 | 1971 | } |
a2fbb9ea | 1972 | |
34f80b04 | 1973 | if (unlikely(status & 0x1)) { |
fd1fc79d AE |
1974 | |
1975 | /* schedule sp task to perform default status block work, ack | |
1976 | * attentions and enable interrupts. | |
1977 | */ | |
1978 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
1979 | |
1980 | status &= ~0x1; | |
1981 | if (!status) | |
1982 | return IRQ_HANDLED; | |
1983 | } | |
1984 | ||
cdaa7cb8 VZ |
1985 | if (unlikely(status)) |
1986 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1987 | status); |
a2fbb9ea | 1988 | |
c18487ee | 1989 | return IRQ_HANDLED; |
a2fbb9ea ET |
1990 | } |
1991 | ||
c18487ee YR |
1992 | /* Link */ |
1993 | ||
1994 | /* | |
1995 | * General service functions | |
1996 | */ | |
a2fbb9ea | 1997 | |
9f6c9258 | 1998 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1999 | { |
2000 | u32 lock_status; | |
2001 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
2002 | int func = BP_FUNC(bp); |
2003 | u32 hw_lock_control_reg; | |
c18487ee | 2004 | int cnt; |
a2fbb9ea | 2005 | |
c18487ee YR |
2006 | /* Validating that the resource is within range */ |
2007 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 2008 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
2009 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
2010 | return -EINVAL; | |
2011 | } | |
a2fbb9ea | 2012 | |
4a37fb66 YG |
2013 | if (func <= 5) { |
2014 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
2015 | } else { | |
2016 | hw_lock_control_reg = | |
2017 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
2018 | } | |
2019 | ||
c18487ee | 2020 | /* Validating that the resource is not already taken */ |
4a37fb66 | 2021 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 2022 | if (lock_status & resource_bit) { |
51c1a580 | 2023 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
c18487ee YR |
2024 | lock_status, resource_bit); |
2025 | return -EEXIST; | |
2026 | } | |
a2fbb9ea | 2027 | |
46230476 EG |
2028 | /* Try for 5 second every 5ms */ |
2029 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 2030 | /* Try to acquire the lock */ |
4a37fb66 YG |
2031 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
2032 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
2033 | if (lock_status & resource_bit) |
2034 | return 0; | |
a2fbb9ea | 2035 | |
639d65b8 | 2036 | usleep_range(5000, 10000); |
a2fbb9ea | 2037 | } |
51c1a580 | 2038 | BNX2X_ERR("Timeout\n"); |
c18487ee YR |
2039 | return -EAGAIN; |
2040 | } | |
a2fbb9ea | 2041 | |
c9ee9206 VZ |
2042 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
2043 | { | |
2044 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
2045 | } | |
2046 | ||
9f6c9258 | 2047 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
2048 | { |
2049 | u32 lock_status; | |
2050 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
2051 | int func = BP_FUNC(bp); |
2052 | u32 hw_lock_control_reg; | |
a2fbb9ea | 2053 | |
c18487ee YR |
2054 | /* Validating that the resource is within range */ |
2055 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 2056 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
2057 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
2058 | return -EINVAL; | |
2059 | } | |
2060 | ||
4a37fb66 YG |
2061 | if (func <= 5) { |
2062 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
2063 | } else { | |
2064 | hw_lock_control_reg = | |
2065 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
2066 | } | |
2067 | ||
c18487ee | 2068 | /* Validating that the resource is currently taken */ |
4a37fb66 | 2069 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 2070 | if (!(lock_status & resource_bit)) { |
6bf07b8e YM |
2071 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n", |
2072 | lock_status, resource_bit); | |
c18487ee | 2073 | return -EFAULT; |
a2fbb9ea ET |
2074 | } |
2075 | ||
9f6c9258 DK |
2076 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
2077 | return 0; | |
c18487ee | 2078 | } |
a2fbb9ea | 2079 | |
4acac6a5 EG |
2080 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
2081 | { | |
2082 | /* The GPIO should be swapped if swap register is set and active */ | |
2083 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2084 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2085 | int gpio_shift = gpio_num + | |
2086 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2087 | u32 gpio_mask = (1 << gpio_shift); | |
2088 | u32 gpio_reg; | |
2089 | int value; | |
2090 | ||
2091 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2092 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2093 | return -EINVAL; | |
2094 | } | |
2095 | ||
2096 | /* read GPIO value */ | |
2097 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2098 | ||
2099 | /* get the requested pin value */ | |
2100 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
2101 | value = 1; | |
2102 | else | |
2103 | value = 0; | |
2104 | ||
4acac6a5 EG |
2105 | return value; |
2106 | } | |
2107 | ||
17de50b7 | 2108 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
2109 | { |
2110 | /* The GPIO should be swapped if swap register is set and active */ | |
2111 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 2112 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
2113 | int gpio_shift = gpio_num + |
2114 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2115 | u32 gpio_mask = (1 << gpio_shift); | |
2116 | u32 gpio_reg; | |
a2fbb9ea | 2117 | |
c18487ee YR |
2118 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
2119 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2120 | return -EINVAL; | |
2121 | } | |
a2fbb9ea | 2122 | |
4a37fb66 | 2123 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
2124 | /* read GPIO and mask except the float bits */ |
2125 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 2126 | |
c18487ee YR |
2127 | switch (mode) { |
2128 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
51c1a580 MS |
2129 | DP(NETIF_MSG_LINK, |
2130 | "Set GPIO %d (shift %d) -> output low\n", | |
c18487ee YR |
2131 | gpio_num, gpio_shift); |
2132 | /* clear FLOAT and set CLR */ | |
2133 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2134 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
2135 | break; | |
a2fbb9ea | 2136 | |
c18487ee | 2137 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
51c1a580 MS |
2138 | DP(NETIF_MSG_LINK, |
2139 | "Set GPIO %d (shift %d) -> output high\n", | |
c18487ee YR |
2140 | gpio_num, gpio_shift); |
2141 | /* clear FLOAT and set SET */ | |
2142 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2143 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
2144 | break; | |
a2fbb9ea | 2145 | |
17de50b7 | 2146 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
51c1a580 MS |
2147 | DP(NETIF_MSG_LINK, |
2148 | "Set GPIO %d (shift %d) -> input\n", | |
c18487ee YR |
2149 | gpio_num, gpio_shift); |
2150 | /* set FLOAT */ | |
2151 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2152 | break; | |
a2fbb9ea | 2153 | |
c18487ee YR |
2154 | default: |
2155 | break; | |
a2fbb9ea ET |
2156 | } |
2157 | ||
c18487ee | 2158 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 2159 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 2160 | |
c18487ee | 2161 | return 0; |
a2fbb9ea ET |
2162 | } |
2163 | ||
0d40f0d4 YR |
2164 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
2165 | { | |
2166 | u32 gpio_reg = 0; | |
2167 | int rc = 0; | |
2168 | ||
2169 | /* Any port swapping should be handled by caller. */ | |
2170 | ||
2171 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2172 | /* read GPIO and mask except the float bits */ | |
2173 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2174 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2175 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2176 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
2177 | ||
2178 | switch (mode) { | |
2179 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
2180 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
2181 | /* set CLR */ | |
2182 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2183 | break; | |
2184 | ||
2185 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
2186 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
2187 | /* set SET */ | |
2188 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
2189 | break; | |
2190 | ||
2191 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
2192 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
2193 | /* set FLOAT */ | |
2194 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2195 | break; | |
2196 | ||
2197 | default: | |
2198 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
2199 | rc = -EINVAL; | |
2200 | break; | |
2201 | } | |
2202 | ||
2203 | if (rc == 0) | |
2204 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
2205 | ||
2206 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2207 | ||
2208 | return rc; | |
2209 | } | |
2210 | ||
4acac6a5 EG |
2211 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
2212 | { | |
2213 | /* The GPIO should be swapped if swap register is set and active */ | |
2214 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2215 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2216 | int gpio_shift = gpio_num + | |
2217 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2218 | u32 gpio_mask = (1 << gpio_shift); | |
2219 | u32 gpio_reg; | |
2220 | ||
2221 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2222 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2223 | return -EINVAL; | |
2224 | } | |
2225 | ||
2226 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2227 | /* read GPIO int */ | |
2228 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
2229 | ||
2230 | switch (mode) { | |
2231 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
51c1a580 MS |
2232 | DP(NETIF_MSG_LINK, |
2233 | "Clear GPIO INT %d (shift %d) -> output low\n", | |
2234 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2235 | /* clear SET and set CLR */ |
2236 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2237 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2238 | break; | |
2239 | ||
2240 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
51c1a580 MS |
2241 | DP(NETIF_MSG_LINK, |
2242 | "Set GPIO INT %d (shift %d) -> output high\n", | |
2243 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2244 | /* clear CLR and set SET */ |
2245 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2246 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2247 | break; | |
2248 | ||
2249 | default: | |
2250 | break; | |
2251 | } | |
2252 | ||
2253 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2254 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2255 | ||
2256 | return 0; | |
2257 | } | |
2258 | ||
d6d99a3f | 2259 | static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) |
a2fbb9ea | 2260 | { |
c18487ee | 2261 | u32 spio_reg; |
a2fbb9ea | 2262 | |
d6d99a3f YM |
2263 | /* Only 2 SPIOs are configurable */ |
2264 | if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { | |
2265 | BNX2X_ERR("Invalid SPIO 0x%x\n", spio); | |
c18487ee | 2266 | return -EINVAL; |
a2fbb9ea ET |
2267 | } |
2268 | ||
4a37fb66 | 2269 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2270 | /* read SPIO and mask except the float bits */ |
d6d99a3f | 2271 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); |
a2fbb9ea | 2272 | |
c18487ee | 2273 | switch (mode) { |
d6d99a3f YM |
2274 | case MISC_SPIO_OUTPUT_LOW: |
2275 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); | |
c18487ee | 2276 | /* clear FLOAT and set CLR */ |
d6d99a3f YM |
2277 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2278 | spio_reg |= (spio << MISC_SPIO_CLR_POS); | |
c18487ee | 2279 | break; |
a2fbb9ea | 2280 | |
d6d99a3f YM |
2281 | case MISC_SPIO_OUTPUT_HIGH: |
2282 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); | |
c18487ee | 2283 | /* clear FLOAT and set SET */ |
d6d99a3f YM |
2284 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2285 | spio_reg |= (spio << MISC_SPIO_SET_POS); | |
c18487ee | 2286 | break; |
a2fbb9ea | 2287 | |
d6d99a3f YM |
2288 | case MISC_SPIO_INPUT_HI_Z: |
2289 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); | |
c18487ee | 2290 | /* set FLOAT */ |
d6d99a3f | 2291 | spio_reg |= (spio << MISC_SPIO_FLOAT_POS); |
c18487ee | 2292 | break; |
a2fbb9ea | 2293 | |
c18487ee YR |
2294 | default: |
2295 | break; | |
a2fbb9ea ET |
2296 | } |
2297 | ||
c18487ee | 2298 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2299 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2300 | |
a2fbb9ea ET |
2301 | return 0; |
2302 | } | |
2303 | ||
9f6c9258 | 2304 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2305 | { |
a22f0788 | 2306 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
1359d73c YM |
2307 | |
2308 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | | |
2309 | ADVERTISED_Pause); | |
ad33ea3a EG |
2310 | switch (bp->link_vars.ieee_fc & |
2311 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2312 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2313 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2314 | ADVERTISED_Pause); |
c18487ee | 2315 | break; |
356e2385 | 2316 | |
c18487ee | 2317 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2318 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2319 | break; |
356e2385 | 2320 | |
c18487ee | 2321 | default: |
c18487ee YR |
2322 | break; |
2323 | } | |
2324 | } | |
f1410647 | 2325 | |
cd1dfce2 | 2326 | static void bnx2x_set_requested_fc(struct bnx2x *bp) |
c18487ee | 2327 | { |
cd1dfce2 YM |
2328 | /* Initialize link parameters structure variables |
2329 | * It is recommended to turn off RX FC for jumbo frames | |
2330 | * for better performance | |
2331 | */ | |
2332 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
2333 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; | |
2334 | else | |
2335 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; | |
2336 | } | |
a2fbb9ea | 2337 | |
9156b30b DK |
2338 | static void bnx2x_init_dropless_fc(struct bnx2x *bp) |
2339 | { | |
2340 | u32 pause_enabled = 0; | |
2341 | ||
2342 | if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { | |
2343 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2344 | pause_enabled = 1; | |
2345 | ||
2346 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
2347 | USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), | |
2348 | pause_enabled); | |
2349 | } | |
2350 | ||
2351 | DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n", | |
2352 | pause_enabled ? "enabled" : "disabled"); | |
2353 | } | |
2354 | ||
cd1dfce2 YM |
2355 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
2356 | { | |
2357 | int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); | |
2358 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
2359 | ||
2360 | if (!BP_NOMCP(bp)) { | |
2361 | bnx2x_set_requested_fc(bp); | |
4a37fb66 | 2362 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2363 | |
a22f0788 | 2364 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2365 | struct link_params *lp = &bp->link_params; |
2366 | lp->loopback_mode = LOOPBACK_XGXS; | |
2f43b821 YM |
2367 | /* Prefer doing PHY loopback at highest speed */ |
2368 | if (lp->req_line_speed[cfx_idx] < SPEED_20000) { | |
1cb0c788 | 2369 | if (lp->speed_cap_mask[cfx_idx] & |
2f43b821 | 2370 | PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) |
1cb0c788 | 2371 | lp->req_line_speed[cfx_idx] = |
2f43b821 YM |
2372 | SPEED_20000; |
2373 | else if (lp->speed_cap_mask[cfx_idx] & | |
2374 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2375 | lp->req_line_speed[cfx_idx] = | |
2376 | SPEED_10000; | |
1cb0c788 YR |
2377 | else |
2378 | lp->req_line_speed[cfx_idx] = | |
2379 | SPEED_1000; | |
2380 | } | |
a22f0788 | 2381 | } |
b5bf9068 | 2382 | |
8970b2e4 MS |
2383 | if (load_mode == LOAD_LOOPBACK_EXT) { |
2384 | struct link_params *lp = &bp->link_params; | |
2385 | lp->loopback_mode = LOOPBACK_EXT; | |
2386 | } | |
2387 | ||
19680c48 | 2388 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2389 | |
4a37fb66 | 2390 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2391 | |
9156b30b DK |
2392 | bnx2x_init_dropless_fc(bp); |
2393 | ||
3c96c68b EG |
2394 | bnx2x_calc_fc_adv(bp); |
2395 | ||
cd1dfce2 | 2396 | if (bp->link_vars.link_up) { |
b5bf9068 | 2397 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
19680c48 | 2398 | bnx2x_link_report(bp); |
cd1dfce2 YM |
2399 | } |
2400 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2401 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2402 | return rc; |
2403 | } | |
f5372251 | 2404 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2405 | return -EINVAL; |
a2fbb9ea ET |
2406 | } |
2407 | ||
9f6c9258 | 2408 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2409 | { |
19680c48 | 2410 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2411 | bnx2x_acquire_phy_lock(bp); |
19680c48 | 2412 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2413 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2414 | |
9156b30b DK |
2415 | bnx2x_init_dropless_fc(bp); |
2416 | ||
19680c48 EG |
2417 | bnx2x_calc_fc_adv(bp); |
2418 | } else | |
f5372251 | 2419 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2420 | } |
a2fbb9ea | 2421 | |
c18487ee YR |
2422 | static void bnx2x__link_reset(struct bnx2x *bp) |
2423 | { | |
19680c48 | 2424 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2425 | bnx2x_acquire_phy_lock(bp); |
5d07d868 | 2426 | bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2427 | bnx2x_release_phy_lock(bp); |
19680c48 | 2428 | } else |
f5372251 | 2429 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2430 | } |
a2fbb9ea | 2431 | |
5d07d868 YM |
2432 | void bnx2x_force_link_reset(struct bnx2x *bp) |
2433 | { | |
2434 | bnx2x_acquire_phy_lock(bp); | |
2435 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); | |
2436 | bnx2x_release_phy_lock(bp); | |
2437 | } | |
2438 | ||
a22f0788 | 2439 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2440 | { |
2145a920 | 2441 | u8 rc = 0; |
a2fbb9ea | 2442 | |
2145a920 VZ |
2443 | if (!BP_NOMCP(bp)) { |
2444 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2445 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2446 | is_serdes); | |
2145a920 VZ |
2447 | bnx2x_release_phy_lock(bp); |
2448 | } else | |
2449 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2450 | |
c18487ee YR |
2451 | return rc; |
2452 | } | |
a2fbb9ea | 2453 | |
2691d51d EG |
2454 | /* Calculates the sum of vn_min_rates. |
2455 | It's needed for further normalizing of the min_rates. | |
2456 | Returns: | |
2457 | sum of vn_min_rates. | |
2458 | or | |
2459 | 0 - if all the min_rates are 0. | |
16a5fd92 | 2460 | In the later case fairness algorithm should be deactivated. |
2691d51d EG |
2461 | If not all min_rates are zero then those that are zeroes will be set to 1. |
2462 | */ | |
b475d78f YM |
2463 | static void bnx2x_calc_vn_min(struct bnx2x *bp, |
2464 | struct cmng_init_input *input) | |
2691d51d EG |
2465 | { |
2466 | int all_zero = 1; | |
2691d51d EG |
2467 | int vn; |
2468 | ||
3395a033 | 2469 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2470 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2471 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2472 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2473 | ||
2474 | /* Skip hidden vns */ | |
2475 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
b475d78f | 2476 | vn_min_rate = 0; |
2691d51d | 2477 | /* If min rate is zero - set it to 1 */ |
b475d78f | 2478 | else if (!vn_min_rate) |
2691d51d EG |
2479 | vn_min_rate = DEF_MIN_RATE; |
2480 | else | |
2481 | all_zero = 0; | |
2482 | ||
b475d78f | 2483 | input->vnic_min_rate[vn] = vn_min_rate; |
2691d51d EG |
2484 | } |
2485 | ||
30ae438b DK |
2486 | /* if ETS or all min rates are zeros - disable fairness */ |
2487 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
b475d78f | 2488 | input->flags.cmng_enables &= |
30ae438b DK |
2489 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2490 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2491 | } else if (all_zero) { | |
b475d78f | 2492 | input->flags.cmng_enables &= |
b015e3d1 | 2493 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
b475d78f YM |
2494 | DP(NETIF_MSG_IFUP, |
2495 | "All MIN values are zeroes fairness will be disabled\n"); | |
b015e3d1 | 2496 | } else |
b475d78f | 2497 | input->flags.cmng_enables |= |
b015e3d1 | 2498 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2691d51d EG |
2499 | } |
2500 | ||
b475d78f YM |
2501 | static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, |
2502 | struct cmng_init_input *input) | |
34f80b04 | 2503 | { |
b475d78f | 2504 | u16 vn_max_rate; |
f2e0899f | 2505 | u32 vn_cfg = bp->mf_config[vn]; |
34f80b04 | 2506 | |
b475d78f | 2507 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
34f80b04 | 2508 | vn_max_rate = 0; |
b475d78f | 2509 | else { |
faa6fcbb DK |
2510 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2511 | ||
da3cc2da | 2512 | if (IS_MF_PERCENT_BW(bp)) { |
faa6fcbb DK |
2513 | /* maxCfg in percents of linkspeed */ |
2514 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
b475d78f | 2515 | } else /* SD modes */ |
faa6fcbb DK |
2516 | /* maxCfg is absolute in 100Mb units */ |
2517 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2518 | } |
f85582f8 | 2519 | |
b475d78f | 2520 | DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); |
34f80b04 | 2521 | |
b475d78f | 2522 | input->vnic_max_rate[vn] = vn_max_rate; |
34f80b04 | 2523 | } |
f85582f8 | 2524 | |
523224a3 DK |
2525 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2526 | { | |
2527 | if (CHIP_REV_IS_SLOW(bp)) | |
2528 | return CMNG_FNS_NONE; | |
fb3bff17 | 2529 | if (IS_MF(bp)) |
523224a3 DK |
2530 | return CMNG_FNS_MINMAX; |
2531 | ||
2532 | return CMNG_FNS_NONE; | |
2533 | } | |
2534 | ||
2ae17f66 | 2535 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2536 | { |
0793f83f | 2537 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2538 | |
2539 | if (BP_NOMCP(bp)) | |
16a5fd92 | 2540 | return; /* what should be the default value in this case */ |
523224a3 | 2541 | |
0793f83f DK |
2542 | /* For 2 port configuration the absolute function number formula |
2543 | * is: | |
2544 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2545 | * | |
2546 | * and there are 4 functions per port | |
2547 | * | |
2548 | * For 4 port configuration it is | |
2549 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2550 | * | |
2551 | * and there are 2 functions per port | |
2552 | */ | |
3395a033 | 2553 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2554 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2555 | ||
2556 | if (func >= E1H_FUNC_MAX) | |
2557 | break; | |
2558 | ||
f2e0899f | 2559 | bp->mf_config[vn] = |
523224a3 DK |
2560 | MF_CFG_RD(bp, func_mf_config[func].config); |
2561 | } | |
a3348722 BW |
2562 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
2563 | DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); | |
2564 | bp->flags |= MF_FUNC_DIS; | |
2565 | } else { | |
2566 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2567 | bp->flags &= ~MF_FUNC_DIS; | |
2568 | } | |
523224a3 DK |
2569 | } |
2570 | ||
2571 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2572 | { | |
b475d78f YM |
2573 | struct cmng_init_input input; |
2574 | memset(&input, 0, sizeof(struct cmng_init_input)); | |
2575 | ||
2576 | input.port_rate = bp->link_vars.line_speed; | |
523224a3 | 2577 | |
568e2426 | 2578 | if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) { |
523224a3 DK |
2579 | int vn; |
2580 | ||
523224a3 DK |
2581 | /* read mf conf from shmem */ |
2582 | if (read_cfg) | |
2583 | bnx2x_read_mf_cfg(bp); | |
2584 | ||
523224a3 | 2585 | /* vn_weight_sum and enable fairness if not 0 */ |
b475d78f | 2586 | bnx2x_calc_vn_min(bp, &input); |
523224a3 DK |
2587 | |
2588 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2589 | if (bp->port.pmf) |
3395a033 | 2590 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
b475d78f | 2591 | bnx2x_calc_vn_max(bp, vn, &input); |
523224a3 DK |
2592 | |
2593 | /* always enable rate shaping and fairness */ | |
b475d78f | 2594 | input.flags.cmng_enables |= |
523224a3 | 2595 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; |
b475d78f YM |
2596 | |
2597 | bnx2x_init_cmng(&input, &bp->cmng); | |
523224a3 DK |
2598 | return; |
2599 | } | |
2600 | ||
2601 | /* rate shaping and fairness are disabled */ | |
2602 | DP(NETIF_MSG_IFUP, | |
2603 | "rate shaping and fairness are disabled\n"); | |
2604 | } | |
34f80b04 | 2605 | |
1191cb83 ED |
2606 | static void storm_memset_cmng(struct bnx2x *bp, |
2607 | struct cmng_init *cmng, | |
2608 | u8 port) | |
2609 | { | |
2610 | int vn; | |
2611 | size_t size = sizeof(struct cmng_struct_per_port); | |
2612 | ||
2613 | u32 addr = BAR_XSTRORM_INTMEM + | |
2614 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
2615 | ||
2616 | __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); | |
2617 | ||
2618 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
2619 | int func = func_by_vn(bp, vn); | |
2620 | ||
2621 | addr = BAR_XSTRORM_INTMEM + | |
2622 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); | |
2623 | size = sizeof(struct rate_shaping_vars_per_vn); | |
2624 | __storm_memset_struct(bp, addr, size, | |
2625 | (u32 *)&cmng->vnic.vnic_max_rate[vn]); | |
2626 | ||
2627 | addr = BAR_XSTRORM_INTMEM + | |
2628 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); | |
2629 | size = sizeof(struct fairness_vars_per_vn); | |
2630 | __storm_memset_struct(bp, addr, size, | |
2631 | (u32 *)&cmng->vnic.vnic_min_rate[vn]); | |
2632 | } | |
2633 | } | |
2634 | ||
568e2426 DK |
2635 | /* init cmng mode in HW according to local configuration */ |
2636 | void bnx2x_set_local_cmng(struct bnx2x *bp) | |
2637 | { | |
2638 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
2639 | ||
2640 | if (cmng_fns != CMNG_FNS_NONE) { | |
2641 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2642 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2643 | } else { | |
2644 | /* rate shaping and fairness are disabled */ | |
2645 | DP(NETIF_MSG_IFUP, | |
2646 | "single function mode without fairness\n"); | |
2647 | } | |
2648 | } | |
2649 | ||
c18487ee YR |
2650 | /* This function is called upon link interrupt */ |
2651 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2652 | { | |
bb2a0f7a YG |
2653 | /* Make sure that we are synced with the current statistics */ |
2654 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2655 | ||
c18487ee | 2656 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2657 | |
9156b30b | 2658 | bnx2x_init_dropless_fc(bp); |
1c06328c | 2659 | |
9156b30b | 2660 | if (bp->link_vars.link_up) { |
1c06328c | 2661 | |
619c5cb6 | 2662 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2663 | struct host_port_stats *pstats; |
2664 | ||
2665 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2666 | /* reset old mac stats */ |
bb2a0f7a YG |
2667 | memset(&(pstats->mac_stx[0]), 0, |
2668 | sizeof(struct mac_stx)); | |
2669 | } | |
f34d28ea | 2670 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2671 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2672 | } | |
2673 | ||
568e2426 DK |
2674 | if (bp->link_vars.link_up && bp->link_vars.line_speed) |
2675 | bnx2x_set_local_cmng(bp); | |
9fdc3e95 | 2676 | |
2ae17f66 VZ |
2677 | __bnx2x_link_report(bp); |
2678 | ||
9fdc3e95 DK |
2679 | if (IS_MF(bp)) |
2680 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2681 | } |
a2fbb9ea | 2682 | |
9f6c9258 | 2683 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2684 | { |
2ae17f66 | 2685 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2686 | return; |
a2fbb9ea | 2687 | |
00253a8c | 2688 | /* read updated dcb configuration */ |
ad5afc89 AE |
2689 | if (IS_PF(bp)) { |
2690 | bnx2x_dcbx_pmf_update(bp); | |
2691 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); | |
2692 | if (bp->link_vars.link_up) | |
2693 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2694 | else | |
2695 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2696 | /* indicate link status */ | |
2697 | bnx2x_link_report(bp); | |
a2fbb9ea | 2698 | |
ad5afc89 AE |
2699 | } else { /* VF */ |
2700 | bp->port.supported[0] |= (SUPPORTED_10baseT_Half | | |
2701 | SUPPORTED_10baseT_Full | | |
2702 | SUPPORTED_100baseT_Half | | |
2703 | SUPPORTED_100baseT_Full | | |
2704 | SUPPORTED_1000baseT_Full | | |
2705 | SUPPORTED_2500baseX_Full | | |
2706 | SUPPORTED_10000baseT_Full | | |
2707 | SUPPORTED_TP | | |
2708 | SUPPORTED_FIBRE | | |
2709 | SUPPORTED_Autoneg | | |
2710 | SUPPORTED_Pause | | |
2711 | SUPPORTED_Asym_Pause); | |
2712 | bp->port.advertising[0] = bp->port.supported[0]; | |
2713 | ||
2714 | bp->link_params.bp = bp; | |
2715 | bp->link_params.port = BP_PORT(bp); | |
2716 | bp->link_params.req_duplex[0] = DUPLEX_FULL; | |
2717 | bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; | |
2718 | bp->link_params.req_line_speed[0] = SPEED_10000; | |
2719 | bp->link_params.speed_cap_mask[0] = 0x7f0000; | |
2720 | bp->link_params.switch_cfg = SWITCH_CFG_10G; | |
2721 | bp->link_vars.mac_type = MAC_TYPE_BMAC; | |
2722 | bp->link_vars.line_speed = SPEED_10000; | |
2723 | bp->link_vars.link_status = | |
2724 | (LINK_STATUS_LINK_UP | | |
2725 | LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); | |
2726 | bp->link_vars.link_up = 1; | |
2727 | bp->link_vars.duplex = DUPLEX_FULL; | |
2728 | bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
2729 | __bnx2x_link_report(bp); | |
6495d15a DK |
2730 | |
2731 | bnx2x_sample_bulletin(bp); | |
2732 | ||
2733 | /* if bulletin board did not have an update for link status | |
2734 | * __bnx2x_link_report will report current status | |
2735 | * but it will NOT duplicate report in case of already reported | |
2736 | * during sampling bulletin board. | |
2737 | */ | |
bb2a0f7a | 2738 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
ad5afc89 | 2739 | } |
a2fbb9ea | 2740 | } |
a2fbb9ea | 2741 | |
a3348722 BW |
2742 | static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, |
2743 | u16 vlan_val, u8 allowed_prio) | |
2744 | { | |
86564c3f | 2745 | struct bnx2x_func_state_params func_params = {NULL}; |
a3348722 BW |
2746 | struct bnx2x_func_afex_update_params *f_update_params = |
2747 | &func_params.params.afex_update; | |
2748 | ||
2749 | func_params.f_obj = &bp->func_obj; | |
2750 | func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; | |
2751 | ||
2752 | /* no need to wait for RAMROD completion, so don't | |
2753 | * set RAMROD_COMP_WAIT flag | |
2754 | */ | |
2755 | ||
2756 | f_update_params->vif_id = vifid; | |
2757 | f_update_params->afex_default_vlan = vlan_val; | |
2758 | f_update_params->allowed_priorities = allowed_prio; | |
2759 | ||
2760 | /* if ramrod can not be sent, response to MCP immediately */ | |
2761 | if (bnx2x_func_state_change(bp, &func_params) < 0) | |
2762 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
2763 | ||
2764 | return 0; | |
2765 | } | |
2766 | ||
2767 | static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, | |
2768 | u16 vif_index, u8 func_bit_map) | |
2769 | { | |
86564c3f | 2770 | struct bnx2x_func_state_params func_params = {NULL}; |
a3348722 BW |
2771 | struct bnx2x_func_afex_viflists_params *update_params = |
2772 | &func_params.params.afex_viflists; | |
2773 | int rc; | |
2774 | u32 drv_msg_code; | |
2775 | ||
2776 | /* validate only LIST_SET and LIST_GET are received from switch */ | |
2777 | if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) | |
2778 | BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", | |
2779 | cmd_type); | |
2780 | ||
2781 | func_params.f_obj = &bp->func_obj; | |
2782 | func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; | |
2783 | ||
2784 | /* set parameters according to cmd_type */ | |
2785 | update_params->afex_vif_list_command = cmd_type; | |
86564c3f | 2786 | update_params->vif_list_index = vif_index; |
a3348722 BW |
2787 | update_params->func_bit_map = |
2788 | (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; | |
2789 | update_params->func_to_clear = 0; | |
2790 | drv_msg_code = | |
2791 | (cmd_type == VIF_LIST_RULE_GET) ? | |
2792 | DRV_MSG_CODE_AFEX_LISTGET_ACK : | |
2793 | DRV_MSG_CODE_AFEX_LISTSET_ACK; | |
2794 | ||
2795 | /* if ramrod can not be sent, respond to MCP immediately for | |
2796 | * SET and GET requests (other are not triggered from MCP) | |
2797 | */ | |
2798 | rc = bnx2x_func_state_change(bp, &func_params); | |
2799 | if (rc < 0) | |
2800 | bnx2x_fw_command(bp, drv_msg_code, 0); | |
2801 | ||
2802 | return 0; | |
2803 | } | |
2804 | ||
2805 | static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) | |
2806 | { | |
2807 | struct afex_stats afex_stats; | |
2808 | u32 func = BP_ABS_FUNC(bp); | |
2809 | u32 mf_config; | |
2810 | u16 vlan_val; | |
2811 | u32 vlan_prio; | |
2812 | u16 vif_id; | |
2813 | u8 allowed_prio; | |
2814 | u8 vlan_mode; | |
2815 | u32 addr_to_write, vifid, addrs, stats_type, i; | |
2816 | ||
2817 | if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { | |
2818 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2819 | DP(BNX2X_MSG_MCP, | |
2820 | "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); | |
2821 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); | |
2822 | } | |
2823 | ||
2824 | if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { | |
2825 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2826 | addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); | |
2827 | DP(BNX2X_MSG_MCP, | |
2828 | "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", | |
2829 | vifid, addrs); | |
2830 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, | |
2831 | addrs); | |
2832 | } | |
2833 | ||
2834 | if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { | |
2835 | addr_to_write = SHMEM2_RD(bp, | |
2836 | afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); | |
2837 | stats_type = SHMEM2_RD(bp, | |
2838 | afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2839 | ||
2840 | DP(BNX2X_MSG_MCP, | |
2841 | "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", | |
2842 | addr_to_write); | |
2843 | ||
2844 | bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); | |
2845 | ||
2846 | /* write response to scratchpad, for MCP */ | |
2847 | for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) | |
2848 | REG_WR(bp, addr_to_write + i*sizeof(u32), | |
2849 | *(((u32 *)(&afex_stats))+i)); | |
2850 | ||
2851 | /* send ack message to MCP */ | |
2852 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); | |
2853 | } | |
2854 | ||
2855 | if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { | |
2856 | mf_config = MF_CFG_RD(bp, func_mf_config[func].config); | |
2857 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2858 | DP(BNX2X_MSG_MCP, | |
2859 | "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", | |
2860 | mf_config); | |
2861 | ||
2862 | /* if VIF_SET is "enabled" */ | |
2863 | if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { | |
2864 | /* set rate limit directly to internal RAM */ | |
2865 | struct cmng_init_input cmng_input; | |
2866 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2867 | size_t size = sizeof(struct rate_shaping_vars_per_vn); | |
2868 | u32 addr = BAR_XSTRORM_INTMEM + | |
2869 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); | |
2870 | ||
2871 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2872 | ||
2873 | bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); | |
2874 | m_rs_vn.vn_counter.rate = | |
2875 | cmng_input.vnic_max_rate[BP_VN(bp)]; | |
2876 | m_rs_vn.vn_counter.quota = | |
2877 | (m_rs_vn.vn_counter.rate * | |
2878 | RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2879 | ||
2880 | __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); | |
2881 | ||
2882 | /* read relevant values from mf_cfg struct in shmem */ | |
2883 | vif_id = | |
2884 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2885 | FUNC_MF_CFG_E1HOV_TAG_MASK) >> | |
2886 | FUNC_MF_CFG_E1HOV_TAG_SHIFT; | |
2887 | vlan_val = | |
2888 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2889 | FUNC_MF_CFG_AFEX_VLAN_MASK) >> | |
2890 | FUNC_MF_CFG_AFEX_VLAN_SHIFT; | |
2891 | vlan_prio = (mf_config & | |
2892 | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> | |
2893 | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; | |
2894 | vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); | |
2895 | vlan_mode = | |
2896 | (MF_CFG_RD(bp, | |
2897 | func_mf_config[func].afex_config) & | |
2898 | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> | |
2899 | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; | |
2900 | allowed_prio = | |
2901 | (MF_CFG_RD(bp, | |
2902 | func_mf_config[func].afex_config) & | |
2903 | FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> | |
2904 | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; | |
2905 | ||
2906 | /* send ramrod to FW, return in case of failure */ | |
2907 | if (bnx2x_afex_func_update(bp, vif_id, vlan_val, | |
2908 | allowed_prio)) | |
2909 | return; | |
2910 | ||
2911 | bp->afex_def_vlan_tag = vlan_val; | |
2912 | bp->afex_vlan_mode = vlan_mode; | |
2913 | } else { | |
2914 | /* notify link down because BP->flags is disabled */ | |
2915 | bnx2x_link_report(bp); | |
2916 | ||
2917 | /* send INVALID VIF ramrod to FW */ | |
2918 | bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); | |
2919 | ||
2920 | /* Reset the default afex VLAN */ | |
2921 | bp->afex_def_vlan_tag = -1; | |
2922 | } | |
2923 | } | |
2924 | } | |
2925 | ||
7609647e YM |
2926 | static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp) |
2927 | { | |
2928 | struct bnx2x_func_switch_update_params *switch_update_params; | |
2929 | struct bnx2x_func_state_params func_params; | |
2930 | ||
2931 | memset(&func_params, 0, sizeof(struct bnx2x_func_state_params)); | |
2932 | switch_update_params = &func_params.params.switch_update; | |
2933 | func_params.f_obj = &bp->func_obj; | |
2934 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
2935 | ||
9061193c SRK |
2936 | /* Prepare parameters for function state transitions */ |
2937 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
2938 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
2939 | ||
230d00eb | 2940 | if (IS_MF_UFP(bp) || IS_MF_BD(bp)) { |
7609647e YM |
2941 | int func = BP_ABS_FUNC(bp); |
2942 | u32 val; | |
2943 | ||
2944 | /* Re-learn the S-tag from shmem */ | |
2945 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2946 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2947 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
2948 | bp->mf_ov = val; | |
2949 | } else { | |
2950 | BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n"); | |
2951 | goto fail; | |
2952 | } | |
2953 | ||
2954 | /* Configure new S-tag in LLH */ | |
2955 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, | |
2956 | bp->mf_ov); | |
2957 | ||
2958 | /* Send Ramrod to update FW of change */ | |
2959 | __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG, | |
2960 | &switch_update_params->changes); | |
2961 | switch_update_params->vlan = bp->mf_ov; | |
2962 | ||
2963 | if (bnx2x_func_state_change(bp, &func_params) < 0) { | |
2964 | BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n", | |
2965 | bp->mf_ov); | |
2966 | goto fail; | |
230d00eb YM |
2967 | } else { |
2968 | DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", | |
2969 | bp->mf_ov); | |
7609647e | 2970 | } |
230d00eb YM |
2971 | } else { |
2972 | goto fail; | |
7609647e YM |
2973 | } |
2974 | ||
230d00eb YM |
2975 | bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0); |
2976 | return; | |
7609647e YM |
2977 | fail: |
2978 | bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0); | |
2979 | } | |
2980 | ||
34f80b04 EG |
2981 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2982 | { | |
2983 | int port = BP_PORT(bp); | |
2984 | u32 val; | |
2985 | ||
2986 | bp->port.pmf = 1; | |
51c1a580 | 2987 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
34f80b04 | 2988 | |
3deb8167 YR |
2989 | /* |
2990 | * We need the mb() to ensure the ordering between the writing to | |
2991 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2992 | */ | |
2993 | smp_mb(); | |
2994 | ||
2995 | /* queue a periodic task */ | |
2996 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2997 | ||
ef01854e DK |
2998 | bnx2x_dcbx_pmf_update(bp); |
2999 | ||
34f80b04 | 3000 | /* enable nig attention */ |
3395a033 | 3001 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
3002 | if (bp->common.int_block == INT_BLOCK_HC) { |
3003 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
3004 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 3005 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
3006 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
3007 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
3008 | } | |
bb2a0f7a YG |
3009 | |
3010 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
3011 | } |
3012 | ||
c18487ee | 3013 | /* end of Link */ |
a2fbb9ea ET |
3014 | |
3015 | /* slow path */ | |
3016 | ||
3017 | /* | |
3018 | * General service functions | |
3019 | */ | |
3020 | ||
2691d51d | 3021 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 3022 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 3023 | { |
f2e0899f | 3024 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 3025 | u32 seq; |
2691d51d EG |
3026 | u32 rc = 0; |
3027 | u32 cnt = 1; | |
3028 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
3029 | ||
c4ff7cbf | 3030 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 3031 | seq = ++bp->fw_seq; |
f2e0899f DK |
3032 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
3033 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
3034 | ||
754a2f52 DK |
3035 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
3036 | (command | seq), param); | |
2691d51d EG |
3037 | |
3038 | do { | |
3039 | /* let the FW do it's magic ... */ | |
3040 | msleep(delay); | |
3041 | ||
f2e0899f | 3042 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 3043 | |
c4ff7cbf EG |
3044 | /* Give the FW up to 5 second (500*10ms) */ |
3045 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
3046 | |
3047 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
3048 | cnt*delay, rc, seq); | |
3049 | ||
3050 | /* is this a reply to our command? */ | |
3051 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
3052 | rc &= FW_MSG_CODE_MASK; | |
3053 | else { | |
3054 | /* FW BUG! */ | |
3055 | BNX2X_ERR("FW failed to respond!\n"); | |
3056 | bnx2x_fw_dump(bp); | |
3057 | rc = 0; | |
3058 | } | |
c4ff7cbf | 3059 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
3060 | |
3061 | return rc; | |
3062 | } | |
3063 | ||
1191cb83 ED |
3064 | static void storm_memset_func_cfg(struct bnx2x *bp, |
3065 | struct tstorm_eth_function_common_config *tcfg, | |
3066 | u16 abs_fid) | |
3067 | { | |
3068 | size_t size = sizeof(struct tstorm_eth_function_common_config); | |
3069 | ||
3070 | u32 addr = BAR_TSTRORM_INTMEM + | |
3071 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); | |
3072 | ||
3073 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); | |
3074 | } | |
3075 | ||
619c5cb6 VZ |
3076 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
3077 | { | |
3078 | if (CHIP_IS_E1x(bp)) { | |
3079 | struct tstorm_eth_function_common_config tcfg = {0}; | |
3080 | ||
3081 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
3082 | } | |
3083 | ||
3084 | /* Enable the function in the FW */ | |
3085 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
3086 | storm_memset_func_en(bp, p->func_id, 1); | |
3087 | ||
3088 | /* spq */ | |
05cc5a39 | 3089 | if (p->spq_active) { |
619c5cb6 VZ |
3090 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); |
3091 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
3092 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
3093 | } | |
3094 | } | |
3095 | ||
6383c0b3 | 3096 | /** |
16a5fd92 | 3097 | * bnx2x_get_common_flags - Return common flags |
6383c0b3 | 3098 | * |
d0ea5cbd JB |
3099 | * @bp: device handle |
3100 | * @fp: queue handle | |
3101 | * @zero_stats: TRUE if statistics zeroing is needed | |
6383c0b3 AE |
3102 | * |
3103 | * Return the flags that are common for the Tx-only and not normal connections. | |
3104 | */ | |
1191cb83 ED |
3105 | static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, |
3106 | struct bnx2x_fastpath *fp, | |
3107 | bool zero_stats) | |
28912902 | 3108 | { |
619c5cb6 VZ |
3109 | unsigned long flags = 0; |
3110 | ||
3111 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
3112 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 3113 | |
6383c0b3 | 3114 | /* tx only connections collect statistics (on the same index as the |
91226790 DK |
3115 | * parent connection). The statistics are zeroed when the parent |
3116 | * connection is initialized. | |
6383c0b3 | 3117 | */ |
50f0a562 BW |
3118 | |
3119 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
3120 | if (zero_stats) | |
3121 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
3122 | ||
c14db202 YM |
3123 | if (bp->flags & TX_SWITCHING) |
3124 | __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags); | |
3125 | ||
91226790 | 3126 | __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags); |
e287a75c | 3127 | __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags); |
6383c0b3 | 3128 | |
823e1d90 YM |
3129 | #ifdef BNX2X_STOP_ON_ERROR |
3130 | __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); | |
3131 | #endif | |
3132 | ||
6383c0b3 AE |
3133 | return flags; |
3134 | } | |
3135 | ||
1191cb83 ED |
3136 | static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, |
3137 | struct bnx2x_fastpath *fp, | |
3138 | bool leading) | |
6383c0b3 AE |
3139 | { |
3140 | unsigned long flags = 0; | |
3141 | ||
619c5cb6 VZ |
3142 | /* calculate other queue flags */ |
3143 | if (IS_MF_SD(bp)) | |
3144 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 3145 | |
a3348722 | 3146 | if (IS_FCOE_FP(fp)) { |
619c5cb6 | 3147 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); |
a3348722 BW |
3148 | /* For FCoE - force usage of default priority (for afex) */ |
3149 | __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); | |
3150 | } | |
523224a3 | 3151 | |
7e6b4d44 | 3152 | if (fp->mode != TPA_MODE_DISABLED) { |
619c5cb6 | 3153 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e | 3154 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
621b4d66 DK |
3155 | if (fp->mode == TPA_MODE_GRO) |
3156 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); | |
f5219d8e | 3157 | } |
619c5cb6 | 3158 | |
619c5cb6 VZ |
3159 | if (leading) { |
3160 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
3161 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
3162 | } | |
523224a3 | 3163 | |
619c5cb6 VZ |
3164 | /* Always set HW VLAN stripping */ |
3165 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 3166 | |
a3348722 BW |
3167 | /* configure silent vlan removal */ |
3168 | if (IS_MF_AFEX(bp)) | |
3169 | __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); | |
3170 | ||
6383c0b3 | 3171 | return flags | bnx2x_get_common_flags(bp, fp, true); |
523224a3 DK |
3172 | } |
3173 | ||
619c5cb6 | 3174 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
3175 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
3176 | u8 cos) | |
619c5cb6 VZ |
3177 | { |
3178 | gen_init->stat_id = bnx2x_stats_id(fp); | |
3179 | gen_init->spcl_id = fp->cl_id; | |
3180 | ||
3181 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
3182 | if (IS_FCOE_FP(fp)) | |
3183 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
3184 | else | |
3185 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
3186 | |
3187 | gen_init->cos = cos; | |
02dc4025 YM |
3188 | |
3189 | gen_init->fp_hsi = ETH_FP_HSI_VERSION; | |
619c5cb6 VZ |
3190 | } |
3191 | ||
3192 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 3193 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 3194 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 3195 | { |
619c5cb6 | 3196 | u8 max_sge = 0; |
523224a3 DK |
3197 | u16 sge_sz = 0; |
3198 | u16 tpa_agg_size = 0; | |
3199 | ||
7e6b4d44 | 3200 | if (fp->mode != TPA_MODE_DISABLED) { |
dfacf138 DK |
3201 | pause->sge_th_lo = SGE_TH_LO(bp); |
3202 | pause->sge_th_hi = SGE_TH_HI(bp); | |
3203 | ||
3204 | /* validate SGE ring has enough to cross high threshold */ | |
3205 | WARN_ON(bp->dropless_fc && | |
3206 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
3207 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
3208 | ||
924d75ab | 3209 | tpa_agg_size = TPA_AGG_SIZE; |
523224a3 DK |
3210 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> |
3211 | SGE_PAGE_SHIFT; | |
3212 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
3213 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
924d75ab | 3214 | sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); |
523224a3 DK |
3215 | } |
3216 | ||
3217 | /* pause - not for e1 */ | |
3218 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
3219 | pause->bd_th_lo = BD_TH_LO(bp); |
3220 | pause->bd_th_hi = BD_TH_HI(bp); | |
3221 | ||
3222 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
3223 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
3224 | /* | |
3225 | * validate that rings have enough entries to cross | |
3226 | * high thresholds | |
3227 | */ | |
3228 | WARN_ON(bp->dropless_fc && | |
3229 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
3230 | bp->rx_ring_size); | |
3231 | WARN_ON(bp->dropless_fc && | |
3232 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
3233 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 3234 | |
523224a3 DK |
3235 | pause->pri_map = 1; |
3236 | } | |
3237 | ||
3238 | /* rxq setup */ | |
523224a3 DK |
3239 | rxq_init->dscr_map = fp->rx_desc_mapping; |
3240 | rxq_init->sge_map = fp->rx_sge_mapping; | |
3241 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
3242 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 3243 | |
619c5cb6 VZ |
3244 | /* This should be a maximum number of data bytes that may be |
3245 | * placed on the BD (not including paddings). | |
3246 | */ | |
e52fcb24 | 3247 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
3cdeec22 | 3248 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; |
a8c94b91 | 3249 | |
523224a3 | 3250 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
3251 | rxq_init->tpa_agg_sz = tpa_agg_size; |
3252 | rxq_init->sge_buf_sz = sge_sz; | |
3253 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 | 3254 | rxq_init->rss_engine_id = BP_FUNC(bp); |
259afa1f | 3255 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
619c5cb6 VZ |
3256 | |
3257 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
3258 | * | |
2de67439 | 3259 | * For PF Clients it should be the maximum available number. |
619c5cb6 VZ |
3260 | * VF driver(s) may want to define it to a smaller value. |
3261 | */ | |
dfacf138 | 3262 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 3263 | |
523224a3 DK |
3264 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
3265 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
3266 | ||
ec6ba945 VZ |
3267 | if (IS_FCOE_FP(fp)) |
3268 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
3269 | else | |
6383c0b3 | 3270 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
a3348722 BW |
3271 | /* configure silent vlan removal |
3272 | * if multi function mode is afex, then mask default vlan | |
3273 | */ | |
3274 | if (IS_MF_AFEX(bp)) { | |
3275 | rxq_init->silent_removal_value = bp->afex_def_vlan_tag; | |
3276 | rxq_init->silent_removal_mask = VLAN_VID_MASK; | |
3277 | } | |
523224a3 DK |
3278 | } |
3279 | ||
619c5cb6 | 3280 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
3281 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
3282 | u8 cos) | |
523224a3 | 3283 | { |
65565884 | 3284 | txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; |
6383c0b3 | 3285 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; |
523224a3 DK |
3286 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
3287 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 3288 | |
619c5cb6 | 3289 | /* |
16a5fd92 | 3290 | * set the tss leading client id for TX classification == |
619c5cb6 VZ |
3291 | * leading RSS client id |
3292 | */ | |
3293 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
3294 | ||
ec6ba945 VZ |
3295 | if (IS_FCOE_FP(fp)) { |
3296 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
3297 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
3298 | } | |
523224a3 DK |
3299 | } |
3300 | ||
8d96286a | 3301 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
3302 | { |
3303 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 | 3304 | struct event_ring_data eq_data = { {0} }; |
523224a3 | 3305 | |
619c5cb6 | 3306 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
3307 | /* reset IGU PF statistics: MSIX + ATTN */ |
3308 | /* PF */ | |
3309 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3310 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3311 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3312 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3313 | /* ATTN */ | |
3314 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3315 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3316 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
3317 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3318 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3319 | } | |
3320 | ||
05cc5a39 | 3321 | func_init.spq_active = true; |
523224a3 DK |
3322 | func_init.pf_id = BP_FUNC(bp); |
3323 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
3324 | func_init.spq_map = bp->spq_mapping; |
3325 | func_init.spq_prod = bp->spq_prod_idx; | |
3326 | ||
3327 | bnx2x_func_init(bp, &func_init); | |
3328 | ||
3329 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
3330 | ||
3331 | /* | |
619c5cb6 VZ |
3332 | * Congestion management values depend on the link rate |
3333 | * There is no active link so initial link rate is set to 10 Gbps. | |
3334 | * When the link comes up The congestion management values are | |
3335 | * re-calculated according to the actual link rate. | |
3336 | */ | |
523224a3 DK |
3337 | bp->link_vars.line_speed = SPEED_10000; |
3338 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
3339 | ||
3340 | /* Only the PMF sets the HW */ | |
3341 | if (bp->port.pmf) | |
3342 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3343 | ||
86564c3f | 3344 | /* init Event Queue - PCI bus guarantees correct endianity*/ |
523224a3 DK |
3345 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); |
3346 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
3347 | eq_data.producer = bp->eq_prod; | |
3348 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
3349 | eq_data.sb_id = DEF_SB_ID; | |
3350 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
3351 | } | |
3352 | ||
523224a3 DK |
3353 | static void bnx2x_e1h_disable(struct bnx2x *bp) |
3354 | { | |
3355 | int port = BP_PORT(bp); | |
3356 | ||
619c5cb6 | 3357 | bnx2x_tx_disable(bp); |
523224a3 DK |
3358 | |
3359 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
3360 | } |
3361 | ||
3362 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
3363 | { | |
3364 | int port = BP_PORT(bp); | |
3365 | ||
7609647e YM |
3366 | if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) |
3367 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); | |
523224a3 | 3368 | |
16a5fd92 | 3369 | /* Tx queue should be only re-enabled */ |
523224a3 DK |
3370 | netif_tx_wake_all_queues(bp->dev); |
3371 | ||
3372 | /* | |
3373 | * Should not call netif_carrier_on since it will be called if the link | |
3374 | * is up when checking for link state | |
3375 | */ | |
3376 | } | |
3377 | ||
1d187b34 BW |
3378 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
3379 | ||
3380 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) | |
3381 | { | |
3382 | struct eth_stats_info *ether_stat = | |
3383 | &bp->slowpath->drv_info_to_mcp.ether_stat; | |
3ec9f9ca AE |
3384 | struct bnx2x_vlan_mac_obj *mac_obj = |
3385 | &bp->sp_objs->mac_obj; | |
3386 | int i; | |
1d187b34 | 3387 | |
786fdf0b DC |
3388 | strlcpy(ether_stat->version, DRV_MODULE_VERSION, |
3389 | ETH_STAT_INFO_VERSION_LEN); | |
1d187b34 | 3390 | |
3ec9f9ca AE |
3391 | /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the |
3392 | * mac_local field in ether_stat struct. The base address is offset by 2 | |
3393 | * bytes to account for the field being 8 bytes but a mac address is | |
3394 | * only 6 bytes. Likewise, the stride for the get_n_elements function is | |
3395 | * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes | |
3396 | * allocated by the ether_stat struct, so the macs will land in their | |
3397 | * proper positions. | |
3398 | */ | |
3399 | for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) | |
3400 | memset(ether_stat->mac_local + i, 0, | |
3401 | sizeof(ether_stat->mac_local[0])); | |
3402 | mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, | |
3403 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | |
3404 | ether_stat->mac_local + MAC_PAD, MAC_PAD, | |
3405 | ETH_ALEN); | |
1d187b34 | 3406 | ether_stat->mtu_size = bp->dev->mtu; |
1d187b34 BW |
3407 | if (bp->dev->features & NETIF_F_RXCSUM) |
3408 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | |
3409 | if (bp->dev->features & NETIF_F_TSO) | |
3410 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; | |
3411 | ether_stat->feature_flags |= bp->common.boot_mode; | |
3412 | ||
3413 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; | |
3414 | ||
3415 | ether_stat->txq_size = bp->tx_ring_size; | |
3416 | ether_stat->rxq_size = bp->rx_ring_size; | |
0c757dee | 3417 | |
fcf93a0a | 3418 | #ifdef CONFIG_BNX2X_SRIOV |
0c757dee | 3419 | ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0; |
fcf93a0a | 3420 | #endif |
1d187b34 BW |
3421 | } |
3422 | ||
3423 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) | |
3424 | { | |
3425 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3426 | struct fcoe_stats_info *fcoe_stat = | |
3427 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; | |
3428 | ||
55c11941 MS |
3429 | if (!CNIC_LOADED(bp)) |
3430 | return; | |
3431 | ||
3ec9f9ca | 3432 | memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); |
1d187b34 BW |
3433 | |
3434 | fcoe_stat->qos_priority = | |
3435 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | |
3436 | ||
3437 | /* insert FCoE stats from ramrod response */ | |
3438 | if (!NO_FCOE(bp)) { | |
3439 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = | |
65565884 | 3440 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3441 | tstorm_queue_statistics; |
3442 | ||
3443 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = | |
65565884 | 3444 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3445 | xstorm_queue_statistics; |
3446 | ||
3447 | struct fcoe_statistics_params *fw_fcoe_stat = | |
3448 | &bp->fw_stats_data->fcoe; | |
3449 | ||
86564c3f YM |
3450 | ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, |
3451 | fcoe_stat->rx_bytes_lo, | |
3452 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); | |
1d187b34 | 3453 | |
86564c3f YM |
3454 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3455 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, | |
3456 | fcoe_stat->rx_bytes_lo, | |
3457 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); | |
1d187b34 | 3458 | |
86564c3f YM |
3459 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3460 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, | |
3461 | fcoe_stat->rx_bytes_lo, | |
3462 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); | |
1d187b34 | 3463 | |
86564c3f YM |
3464 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3465 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, | |
3466 | fcoe_stat->rx_bytes_lo, | |
3467 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); | |
1d187b34 | 3468 | |
86564c3f YM |
3469 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3470 | fcoe_stat->rx_frames_lo, | |
3471 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); | |
1d187b34 | 3472 | |
86564c3f YM |
3473 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3474 | fcoe_stat->rx_frames_lo, | |
3475 | fcoe_q_tstorm_stats->rcv_ucast_pkts); | |
1d187b34 | 3476 | |
86564c3f YM |
3477 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3478 | fcoe_stat->rx_frames_lo, | |
3479 | fcoe_q_tstorm_stats->rcv_bcast_pkts); | |
1d187b34 | 3480 | |
86564c3f YM |
3481 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3482 | fcoe_stat->rx_frames_lo, | |
3483 | fcoe_q_tstorm_stats->rcv_mcast_pkts); | |
1d187b34 | 3484 | |
86564c3f YM |
3485 | ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, |
3486 | fcoe_stat->tx_bytes_lo, | |
3487 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); | |
1d187b34 | 3488 | |
86564c3f YM |
3489 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3490 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, | |
3491 | fcoe_stat->tx_bytes_lo, | |
3492 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); | |
1d187b34 | 3493 | |
86564c3f YM |
3494 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3495 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, | |
3496 | fcoe_stat->tx_bytes_lo, | |
3497 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); | |
1d187b34 | 3498 | |
86564c3f YM |
3499 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3500 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, | |
3501 | fcoe_stat->tx_bytes_lo, | |
3502 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); | |
1d187b34 | 3503 | |
86564c3f YM |
3504 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3505 | fcoe_stat->tx_frames_lo, | |
3506 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); | |
1d187b34 | 3507 | |
86564c3f YM |
3508 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3509 | fcoe_stat->tx_frames_lo, | |
3510 | fcoe_q_xstorm_stats->ucast_pkts_sent); | |
1d187b34 | 3511 | |
86564c3f YM |
3512 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3513 | fcoe_stat->tx_frames_lo, | |
3514 | fcoe_q_xstorm_stats->bcast_pkts_sent); | |
1d187b34 | 3515 | |
86564c3f YM |
3516 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3517 | fcoe_stat->tx_frames_lo, | |
3518 | fcoe_q_xstorm_stats->mcast_pkts_sent); | |
1d187b34 BW |
3519 | } |
3520 | ||
1d187b34 BW |
3521 | /* ask L5 driver to add data to the struct */ |
3522 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); | |
1d187b34 BW |
3523 | } |
3524 | ||
3525 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) | |
3526 | { | |
3527 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3528 | struct iscsi_stats_info *iscsi_stat = | |
3529 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; | |
3530 | ||
55c11941 MS |
3531 | if (!CNIC_LOADED(bp)) |
3532 | return; | |
3533 | ||
3ec9f9ca AE |
3534 | memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, |
3535 | ETH_ALEN); | |
1d187b34 BW |
3536 | |
3537 | iscsi_stat->qos_priority = | |
3538 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | |
3539 | ||
1d187b34 BW |
3540 | /* ask L5 driver to add data to the struct */ |
3541 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); | |
1d187b34 BW |
3542 | } |
3543 | ||
0793f83f DK |
3544 | /* called due to MCP event (on pmf): |
3545 | * reread new bandwidth configuration | |
3546 | * configure FW | |
3547 | * notify others function about the change | |
3548 | */ | |
1191cb83 | 3549 | static void bnx2x_config_mf_bw(struct bnx2x *bp) |
0793f83f | 3550 | { |
75a110a1 SS |
3551 | /* Workaround for MFW bug. |
3552 | * MFW is not supposed to generate BW attention in | |
3553 | * single function mode. | |
3554 | */ | |
3555 | if (!IS_MF(bp)) { | |
3556 | DP(BNX2X_MSG_MCP, | |
3557 | "Ignoring MF BW config in single function mode\n"); | |
3558 | return; | |
3559 | } | |
3560 | ||
0793f83f DK |
3561 | if (bp->link_vars.link_up) { |
3562 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
3563 | bnx2x_link_sync_notify(bp); | |
3564 | } | |
3565 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3566 | } | |
3567 | ||
1191cb83 | 3568 | static void bnx2x_set_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3569 | { |
3570 | bnx2x_config_mf_bw(bp); | |
3571 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
3572 | } | |
3573 | ||
c8c60d88 YM |
3574 | static void bnx2x_handle_eee_event(struct bnx2x *bp) |
3575 | { | |
3576 | DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); | |
3577 | bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); | |
3578 | } | |
3579 | ||
42f8277f YM |
3580 | #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20) |
3581 | #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25) | |
3582 | ||
1d187b34 BW |
3583 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
3584 | { | |
3585 | enum drv_info_opcode op_code; | |
3586 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); | |
42f8277f YM |
3587 | bool release = false; |
3588 | int wait; | |
1d187b34 BW |
3589 | |
3590 | /* if drv_info version supported by MFW doesn't match - send NACK */ | |
3591 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { | |
3592 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3593 | return; | |
3594 | } | |
3595 | ||
3596 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> | |
3597 | DRV_INFO_CONTROL_OP_CODE_SHIFT; | |
3598 | ||
42f8277f YM |
3599 | /* Must prevent other flows from accessing drv_info_to_mcp */ |
3600 | mutex_lock(&bp->drv_info_mutex); | |
3601 | ||
1d187b34 BW |
3602 | memset(&bp->slowpath->drv_info_to_mcp, 0, |
3603 | sizeof(union drv_info_to_mcp)); | |
3604 | ||
3605 | switch (op_code) { | |
3606 | case ETH_STATS_OPCODE: | |
3607 | bnx2x_drv_info_ether_stat(bp); | |
3608 | break; | |
3609 | case FCOE_STATS_OPCODE: | |
3610 | bnx2x_drv_info_fcoe_stat(bp); | |
3611 | break; | |
3612 | case ISCSI_STATS_OPCODE: | |
3613 | bnx2x_drv_info_iscsi_stat(bp); | |
3614 | break; | |
3615 | default: | |
3616 | /* if op code isn't supported - send NACK */ | |
3617 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
42f8277f | 3618 | goto out; |
1d187b34 BW |
3619 | } |
3620 | ||
3621 | /* if we got drv_info attn from MFW then these fields are defined in | |
3622 | * shmem2 for sure | |
3623 | */ | |
3624 | SHMEM2_WR(bp, drv_info_host_addr_lo, | |
3625 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3626 | SHMEM2_WR(bp, drv_info_host_addr_hi, | |
3627 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3628 | ||
3629 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); | |
42f8277f YM |
3630 | |
3631 | /* Since possible management wants both this and get_driver_version | |
3632 | * need to wait until management notifies us it finished utilizing | |
3633 | * the buffer. | |
3634 | */ | |
3635 | if (!SHMEM2_HAS(bp, mfw_drv_indication)) { | |
3636 | DP(BNX2X_MSG_MCP, "Management does not support indication\n"); | |
3637 | } else if (!bp->drv_info_mng_owner) { | |
3638 | u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1)); | |
3639 | ||
3640 | for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) { | |
3641 | u32 indication = SHMEM2_RD(bp, mfw_drv_indication); | |
3642 | ||
3643 | /* Management is done; need to clear indication */ | |
3644 | if (indication & bit) { | |
3645 | SHMEM2_WR(bp, mfw_drv_indication, | |
3646 | indication & ~bit); | |
3647 | release = true; | |
3648 | break; | |
3649 | } | |
3650 | ||
3651 | msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH); | |
3652 | } | |
3653 | } | |
3654 | if (!release) { | |
3655 | DP(BNX2X_MSG_MCP, "Management did not release indication\n"); | |
3656 | bp->drv_info_mng_owner = true; | |
3657 | } | |
3658 | ||
3659 | out: | |
3660 | mutex_unlock(&bp->drv_info_mutex); | |
3661 | } | |
3662 | ||
3663 | static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format) | |
3664 | { | |
3665 | u8 vals[4]; | |
3666 | int i = 0; | |
3667 | ||
3668 | if (bnx2x_format) { | |
3669 | i = sscanf(version, "1.%c%hhd.%hhd.%hhd", | |
3670 | &vals[0], &vals[1], &vals[2], &vals[3]); | |
3671 | if (i > 0) | |
3672 | vals[0] -= '0'; | |
3673 | } else { | |
3674 | i = sscanf(version, "%hhd.%hhd.%hhd.%hhd", | |
3675 | &vals[0], &vals[1], &vals[2], &vals[3]); | |
3676 | } | |
3677 | ||
3678 | while (i < 4) | |
3679 | vals[i++] = 0; | |
3680 | ||
3681 | return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3]; | |
3682 | } | |
3683 | ||
3684 | void bnx2x_update_mng_version(struct bnx2x *bp) | |
3685 | { | |
3686 | u32 iscsiver = DRV_VER_NOT_LOADED; | |
3687 | u32 fcoever = DRV_VER_NOT_LOADED; | |
3688 | u32 ethver = DRV_VER_NOT_LOADED; | |
3689 | int idx = BP_FW_MB_IDX(bp); | |
3690 | u8 *version; | |
3691 | ||
3692 | if (!SHMEM2_HAS(bp, func_os_drv_ver)) | |
3693 | return; | |
3694 | ||
3695 | mutex_lock(&bp->drv_info_mutex); | |
3696 | /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */ | |
3697 | if (bp->drv_info_mng_owner) | |
3698 | goto out; | |
3699 | ||
3700 | if (bp->state != BNX2X_STATE_OPEN) | |
3701 | goto out; | |
3702 | ||
3703 | /* Parse ethernet driver version */ | |
3704 | ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); | |
3705 | if (!CNIC_LOADED(bp)) | |
3706 | goto out; | |
3707 | ||
3708 | /* Try getting storage driver version via cnic */ | |
3709 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3710 | sizeof(union drv_info_to_mcp)); | |
3711 | bnx2x_drv_info_iscsi_stat(bp); | |
3712 | version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version; | |
3713 | iscsiver = bnx2x_update_mng_version_utility(version, false); | |
3714 | ||
3715 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3716 | sizeof(union drv_info_to_mcp)); | |
3717 | bnx2x_drv_info_fcoe_stat(bp); | |
3718 | version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version; | |
3719 | fcoever = bnx2x_update_mng_version_utility(version, false); | |
3720 | ||
3721 | out: | |
3722 | SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver); | |
3723 | SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver); | |
3724 | SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever); | |
3725 | ||
3726 | mutex_unlock(&bp->drv_info_mutex); | |
3727 | ||
3728 | DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n", | |
3729 | ethver, iscsiver, fcoever); | |
1d187b34 BW |
3730 | } |
3731 | ||
c48f350f YM |
3732 | void bnx2x_update_mfw_dump(struct bnx2x *bp) |
3733 | { | |
c48f350f YM |
3734 | u32 drv_ver; |
3735 | u32 valid_dump; | |
3736 | ||
3737 | if (!SHMEM2_HAS(bp, drv_info)) | |
3738 | return; | |
3739 | ||
a19a19de AB |
3740 | /* Update Driver load time, possibly broken in y2038 */ |
3741 | SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds()); | |
c48f350f YM |
3742 | |
3743 | drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); | |
3744 | SHMEM2_WR(bp, drv_info.drv_ver, drv_ver); | |
3745 | ||
3746 | SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM)); | |
3747 | ||
3748 | /* Check & notify On-Chip dump. */ | |
3749 | valid_dump = SHMEM2_RD(bp, drv_info.valid_dump); | |
3750 | ||
3751 | if (valid_dump & FIRST_DUMP_VALID) | |
3752 | DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n"); | |
3753 | ||
3754 | if (valid_dump & SECOND_DUMP_VALID) | |
3755 | DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n"); | |
3756 | } | |
3757 | ||
7609647e | 3758 | static void bnx2x_oem_event(struct bnx2x *bp, u32 event) |
523224a3 | 3759 | { |
7609647e YM |
3760 | u32 cmd_ok, cmd_fail; |
3761 | ||
3762 | /* sanity */ | |
3763 | if (event & DRV_STATUS_DCC_EVENT_MASK && | |
3764 | event & DRV_STATUS_OEM_EVENT_MASK) { | |
3765 | BNX2X_ERR("Received simultaneous events %08x\n", event); | |
3766 | return; | |
3767 | } | |
523224a3 | 3768 | |
7609647e YM |
3769 | if (event & DRV_STATUS_DCC_EVENT_MASK) { |
3770 | cmd_fail = DRV_MSG_CODE_DCC_FAILURE; | |
3771 | cmd_ok = DRV_MSG_CODE_DCC_OK; | |
3772 | } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ { | |
3773 | cmd_fail = DRV_MSG_CODE_OEM_FAILURE; | |
3774 | cmd_ok = DRV_MSG_CODE_OEM_OK; | |
3775 | } | |
523224a3 | 3776 | |
7609647e YM |
3777 | DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event); |
3778 | ||
3779 | if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF | | |
3780 | DRV_STATUS_OEM_DISABLE_ENABLE_PF)) { | |
3781 | /* This is the only place besides the function initialization | |
523224a3 DK |
3782 | * where the bp->flags can change so it is done without any |
3783 | * locks | |
3784 | */ | |
f2e0899f | 3785 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
51c1a580 | 3786 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
523224a3 DK |
3787 | bp->flags |= MF_FUNC_DIS; |
3788 | ||
3789 | bnx2x_e1h_disable(bp); | |
3790 | } else { | |
51c1a580 | 3791 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
523224a3 DK |
3792 | bp->flags &= ~MF_FUNC_DIS; |
3793 | ||
3794 | bnx2x_e1h_enable(bp); | |
3795 | } | |
7609647e YM |
3796 | event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF | |
3797 | DRV_STATUS_OEM_DISABLE_ENABLE_PF); | |
523224a3 | 3798 | } |
7609647e YM |
3799 | |
3800 | if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | | |
3801 | DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) { | |
0793f83f | 3802 | bnx2x_config_mf_bw(bp); |
7609647e YM |
3803 | event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | |
3804 | DRV_STATUS_OEM_BANDWIDTH_ALLOCATION); | |
523224a3 DK |
3805 | } |
3806 | ||
3807 | /* Report results to MCP */ | |
7609647e YM |
3808 | if (event) |
3809 | bnx2x_fw_command(bp, cmd_fail, 0); | |
523224a3 | 3810 | else |
7609647e | 3811 | bnx2x_fw_command(bp, cmd_ok, 0); |
523224a3 DK |
3812 | } |
3813 | ||
3814 | /* must be called under the spq lock */ | |
1191cb83 | 3815 | static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) |
523224a3 DK |
3816 | { |
3817 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3818 | ||
3819 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3820 | bp->spq_prod_bd = bp->spq; | |
3821 | bp->spq_prod_idx = 0; | |
51c1a580 | 3822 | DP(BNX2X_MSG_SP, "end of spq\n"); |
523224a3 DK |
3823 | } else { |
3824 | bp->spq_prod_bd++; | |
3825 | bp->spq_prod_idx++; | |
3826 | } | |
3827 | return next_spe; | |
3828 | } | |
3829 | ||
3830 | /* must be called under the spq lock */ | |
1191cb83 | 3831 | static void bnx2x_sp_prod_update(struct bnx2x *bp) |
28912902 MC |
3832 | { |
3833 | int func = BP_FUNC(bp); | |
3834 | ||
53e51e2f VZ |
3835 | /* |
3836 | * Make sure that BD data is updated before writing the producer: | |
3837 | * BD data is written to the memory, the producer is read from the | |
3838 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3839 | */ | |
3840 | mb(); | |
28912902 | 3841 | |
7f883c77 SK |
3842 | REG_WR16_RELAXED(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
3843 | bp->spq_prod_idx); | |
28912902 MC |
3844 | } |
3845 | ||
619c5cb6 VZ |
3846 | /** |
3847 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3848 | * | |
3849 | * @cmd: command to check | |
3850 | * @cmd_type: command type | |
3851 | */ | |
1191cb83 | 3852 | static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) |
619c5cb6 VZ |
3853 | { |
3854 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3855 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3856 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3857 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3858 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3859 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3860 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3861 | return true; | |
3862 | else | |
3863 | return false; | |
619c5cb6 VZ |
3864 | } |
3865 | ||
619c5cb6 VZ |
3866 | /** |
3867 | * bnx2x_sp_post - place a single command on an SP ring | |
3868 | * | |
3869 | * @bp: driver handle | |
3870 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3871 | * @cid: SW CID the command is related to | |
3872 | * @data_hi: command private data address (high 32 bits) | |
3873 | * @data_lo: command private data address (low 32 bits) | |
3874 | * @cmd_type: command type (e.g. NONE, ETH) | |
3875 | * | |
3876 | * SP data is handled as if it's always an address pair, thus data fields are | |
3877 | * not swapped to little endian in upper functions. Instead this function swaps | |
3878 | * data as if it's two u32 fields. | |
3879 | */ | |
9f6c9258 | 3880 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3881 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3882 | { |
28912902 | 3883 | struct eth_spe *spe; |
523224a3 | 3884 | u16 type; |
619c5cb6 | 3885 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3886 | |
a2fbb9ea | 3887 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
3888 | if (unlikely(bp->panic)) { |
3889 | BNX2X_ERR("Can't post SP when there is panic\n"); | |
a2fbb9ea | 3890 | return -EIO; |
51c1a580 | 3891 | } |
a2fbb9ea ET |
3892 | #endif |
3893 | ||
34f80b04 | 3894 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3895 | |
6e30dd4e VZ |
3896 | if (common) { |
3897 | if (!atomic_read(&bp->eq_spq_left)) { | |
3898 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3899 | spin_unlock_bh(&bp->spq_lock); | |
3900 | bnx2x_panic(); | |
3901 | return -EBUSY; | |
3902 | } | |
3903 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3904 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3905 | spin_unlock_bh(&bp->spq_lock); | |
3906 | bnx2x_panic(); | |
3907 | return -EBUSY; | |
a2fbb9ea | 3908 | } |
f1410647 | 3909 | |
28912902 MC |
3910 | spe = bnx2x_sp_get_next(bp); |
3911 | ||
a2fbb9ea | 3912 | /* CID needs port number to be encoded int it */ |
28912902 | 3913 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3914 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3915 | HW_CID(bp, cid)); | |
523224a3 | 3916 | |
14a94ebd MK |
3917 | /* In some cases, type may already contain the func-id |
3918 | * mainly in SRIOV related use cases, so we add it here only | |
3919 | * if it's not already set. | |
3920 | */ | |
3921 | if (!(cmd_type & SPE_HDR_FUNCTION_ID)) { | |
3922 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & | |
3923 | SPE_HDR_CONN_TYPE; | |
3924 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & | |
3925 | SPE_HDR_FUNCTION_ID); | |
3926 | } else { | |
3927 | type = cmd_type; | |
3928 | } | |
a2fbb9ea | 3929 | |
523224a3 DK |
3930 | spe->hdr.type = cpu_to_le16(type); |
3931 | ||
3932 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3933 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3934 | ||
d6cae238 VZ |
3935 | /* |
3936 | * It's ok if the actual decrement is issued towards the memory | |
3937 | * somewhere between the spin_lock and spin_unlock. Thus no | |
16a5fd92 | 3938 | * more explicit memory barrier is needed. |
d6cae238 VZ |
3939 | */ |
3940 | if (common) | |
3941 | atomic_dec(&bp->eq_spq_left); | |
3942 | else | |
3943 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3944 | |
51c1a580 MS |
3945 | DP(BNX2X_MSG_SP, |
3946 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3947 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3948 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3949 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3950 | HW_CID(bp, cid), data_hi, data_lo, type, |
3951 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3952 | |
28912902 | 3953 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3954 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3955 | return 0; |
3956 | } | |
3957 | ||
3958 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3959 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3960 | { |
72fd0718 | 3961 | u32 j, val; |
34f80b04 | 3962 | int rc = 0; |
a2fbb9ea ET |
3963 | |
3964 | might_sleep(); | |
72fd0718 | 3965 | for (j = 0; j < 1000; j++) { |
3cdeec22 YM |
3966 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); |
3967 | val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); | |
3968 | if (val & MCPR_ACCESS_LOCK_LOCK) | |
a2fbb9ea ET |
3969 | break; |
3970 | ||
639d65b8 | 3971 | usleep_range(5000, 10000); |
a2fbb9ea | 3972 | } |
3cdeec22 | 3973 | if (!(val & MCPR_ACCESS_LOCK_LOCK)) { |
19680c48 | 3974 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3975 | rc = -EBUSY; |
3976 | } | |
3977 | ||
3978 | return rc; | |
3979 | } | |
3980 | ||
4a37fb66 YG |
3981 | /* release split MCP access lock register */ |
3982 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3983 | { |
3cdeec22 | 3984 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); |
a2fbb9ea ET |
3985 | } |
3986 | ||
523224a3 DK |
3987 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3988 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3989 | ||
1191cb83 | 3990 | static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
a2fbb9ea | 3991 | { |
523224a3 | 3992 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3993 | u16 rc = 0; |
3994 | ||
3995 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3996 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3997 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3998 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3999 | } |
523224a3 DK |
4000 | |
4001 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
4002 | bp->def_idx = def_sb->sp_sb.running_index; | |
4003 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 4004 | } |
523224a3 | 4005 | |
16a5fd92 | 4006 | /* Do not reorder: indices reading should complete before handling */ |
523224a3 | 4007 | barrier(); |
a2fbb9ea ET |
4008 | return rc; |
4009 | } | |
4010 | ||
4011 | /* | |
4012 | * slow path service functions | |
4013 | */ | |
4014 | ||
4015 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
4016 | { | |
34f80b04 | 4017 | int port = BP_PORT(bp); |
a2fbb9ea ET |
4018 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
4019 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
4020 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
4021 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 4022 | u32 aeu_mask; |
87942b46 | 4023 | u32 nig_mask = 0; |
f2e0899f | 4024 | u32 reg_addr; |
a2fbb9ea | 4025 | |
a2fbb9ea ET |
4026 | if (bp->attn_state & asserted) |
4027 | BNX2X_ERR("IGU ERROR\n"); | |
4028 | ||
3fcaf2e5 EG |
4029 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4030 | aeu_mask = REG_RD(bp, aeu_addr); | |
4031 | ||
a2fbb9ea | 4032 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 4033 | aeu_mask, asserted); |
72fd0718 | 4034 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 4035 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4036 | |
3fcaf2e5 EG |
4037 | REG_WR(bp, aeu_addr, aeu_mask); |
4038 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 4039 | |
3fcaf2e5 | 4040 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 4041 | bp->attn_state |= asserted; |
3fcaf2e5 | 4042 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
4043 | |
4044 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
4045 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 4046 | |
a5e9a7cf EG |
4047 | bnx2x_acquire_phy_lock(bp); |
4048 | ||
877e9aa4 | 4049 | /* save nig interrupt mask */ |
87942b46 | 4050 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 4051 | |
361c391e YR |
4052 | /* If nig_mask is not set, no need to call the update |
4053 | * function. | |
4054 | */ | |
4055 | if (nig_mask) { | |
4056 | REG_WR(bp, nig_int_mask_addr, 0); | |
4057 | ||
4058 | bnx2x_link_attn(bp); | |
4059 | } | |
a2fbb9ea ET |
4060 | |
4061 | /* handle unicore attn? */ | |
4062 | } | |
4063 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
4064 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
4065 | ||
4066 | if (asserted & GPIO_2_FUNC) | |
4067 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
4068 | ||
4069 | if (asserted & GPIO_3_FUNC) | |
4070 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
4071 | ||
4072 | if (asserted & GPIO_4_FUNC) | |
4073 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
4074 | ||
4075 | if (port == 0) { | |
4076 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
4077 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
4078 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
4079 | } | |
4080 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
4081 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
4082 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
4083 | } | |
4084 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
4085 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
4086 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
4087 | } | |
4088 | } else { | |
4089 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
4090 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
4091 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
4092 | } | |
4093 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
4094 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
4095 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
4096 | } | |
4097 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
4098 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
4099 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
4100 | } | |
4101 | } | |
4102 | ||
4103 | } /* if hardwired */ | |
4104 | ||
f2e0899f DK |
4105 | if (bp->common.int_block == INT_BLOCK_HC) |
4106 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4107 | COMMAND_REG_ATTN_BITS_SET); | |
4108 | else | |
4109 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
4110 | ||
4111 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
4112 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
4113 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
4114 | |
4115 | /* now set back the mask */ | |
a5e9a7cf | 4116 | if (asserted & ATTN_NIG_FOR_FUNC) { |
27c1151c YR |
4117 | /* Verify that IGU ack through BAR was written before restoring |
4118 | * NIG mask. This loop should exit after 2-3 iterations max. | |
4119 | */ | |
4120 | if (bp->common.int_block != INT_BLOCK_HC) { | |
4121 | u32 cnt = 0, igu_acked; | |
4122 | do { | |
4123 | igu_acked = REG_RD(bp, | |
4124 | IGU_REG_ATTENTION_ACK_BITS); | |
4125 | } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && | |
4126 | (++cnt < MAX_IGU_ATTN_ACK_TO)); | |
4127 | if (!igu_acked) | |
4128 | DP(NETIF_MSG_HW, | |
4129 | "Failed to verify IGU ack on time\n"); | |
4130 | barrier(); | |
4131 | } | |
87942b46 | 4132 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
4133 | bnx2x_release_phy_lock(bp); |
4134 | } | |
a2fbb9ea ET |
4135 | } |
4136 | ||
1191cb83 | 4137 | static void bnx2x_fan_failure(struct bnx2x *bp) |
fd4ef40d EG |
4138 | { |
4139 | int port = BP_PORT(bp); | |
b7737c9b | 4140 | u32 ext_phy_config; |
fd4ef40d | 4141 | /* mark the failure */ |
b7737c9b YR |
4142 | ext_phy_config = |
4143 | SHMEM_RD(bp, | |
4144 | dev_info.port_hw_config[port].external_phy_config); | |
4145 | ||
4146 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
4147 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 4148 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 4149 | ext_phy_config); |
fd4ef40d EG |
4150 | |
4151 | /* log the failure */ | |
51c1a580 MS |
4152 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
4153 | "Please contact OEM Support for assistance\n"); | |
8304859a | 4154 | |
16a5fd92 | 4155 | /* Schedule device reset (unload) |
8304859a AE |
4156 | * This is due to some boards consuming sufficient power when driver is |
4157 | * up to overheat if fan fails. | |
4158 | */ | |
230bb0f3 | 4159 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0); |
fd4ef40d | 4160 | } |
ab6ad5a4 | 4161 | |
1191cb83 | 4162 | static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 4163 | { |
34f80b04 | 4164 | int port = BP_PORT(bp); |
877e9aa4 | 4165 | int reg_offset; |
d90d96ba | 4166 | u32 val; |
877e9aa4 | 4167 | |
34f80b04 EG |
4168 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
4169 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 4170 | |
34f80b04 | 4171 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
4172 | |
4173 | val = REG_RD(bp, reg_offset); | |
4174 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
4175 | REG_WR(bp, reg_offset, val); | |
4176 | ||
4177 | BNX2X_ERR("SPIO5 hw attention\n"); | |
4178 | ||
fd4ef40d | 4179 | /* Fan failure attention */ |
d90d96ba | 4180 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 4181 | bnx2x_fan_failure(bp); |
877e9aa4 | 4182 | } |
34f80b04 | 4183 | |
3deb8167 | 4184 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
4185 | bnx2x_acquire_phy_lock(bp); |
4186 | bnx2x_handle_module_detect_int(&bp->link_params); | |
4187 | bnx2x_release_phy_lock(bp); | |
4188 | } | |
4189 | ||
a8919661 | 4190 | if (attn & HW_INTERRUPT_ASSERT_SET_0) { |
34f80b04 EG |
4191 | |
4192 | val = REG_RD(bp, reg_offset); | |
a8919661 | 4193 | val &= ~(attn & HW_INTERRUPT_ASSERT_SET_0); |
34f80b04 EG |
4194 | REG_WR(bp, reg_offset, val); |
4195 | ||
4196 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
a8919661 | 4197 | (u32)(attn & HW_INTERRUPT_ASSERT_SET_0)); |
34f80b04 EG |
4198 | bnx2x_panic(); |
4199 | } | |
877e9aa4 ET |
4200 | } |
4201 | ||
1191cb83 | 4202 | static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
4203 | { |
4204 | u32 val; | |
4205 | ||
0626b899 | 4206 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
4207 | |
4208 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
4209 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
4210 | /* DORQ discard attention */ | |
4211 | if (val & 0x2) | |
4212 | BNX2X_ERR("FATAL error from DORQ\n"); | |
4213 | } | |
34f80b04 | 4214 | |
a8919661 | 4215 | if (attn & HW_INTERRUPT_ASSERT_SET_1) { |
34f80b04 EG |
4216 | |
4217 | int port = BP_PORT(bp); | |
4218 | int reg_offset; | |
4219 | ||
4220 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
4221 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
4222 | ||
4223 | val = REG_RD(bp, reg_offset); | |
a8919661 | 4224 | val &= ~(attn & HW_INTERRUPT_ASSERT_SET_1); |
34f80b04 EG |
4225 | REG_WR(bp, reg_offset, val); |
4226 | ||
4227 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
a8919661 | 4228 | (u32)(attn & HW_INTERRUPT_ASSERT_SET_1)); |
34f80b04 EG |
4229 | bnx2x_panic(); |
4230 | } | |
877e9aa4 ET |
4231 | } |
4232 | ||
1191cb83 | 4233 | static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
4234 | { |
4235 | u32 val; | |
4236 | ||
4237 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
4238 | ||
4239 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
4240 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
4241 | /* CFC error attention */ | |
4242 | if (val & 0x2) | |
4243 | BNX2X_ERR("FATAL error from CFC\n"); | |
4244 | } | |
4245 | ||
4246 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 4247 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 4248 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
4249 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
4250 | if (val & 0x18000) | |
4251 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
4252 | |
4253 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
4254 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
4255 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
4256 | } | |
877e9aa4 | 4257 | } |
34f80b04 | 4258 | |
a8919661 | 4259 | if (attn & HW_INTERRUPT_ASSERT_SET_2) { |
34f80b04 EG |
4260 | |
4261 | int port = BP_PORT(bp); | |
4262 | int reg_offset; | |
4263 | ||
4264 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
4265 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
4266 | ||
4267 | val = REG_RD(bp, reg_offset); | |
a8919661 | 4268 | val &= ~(attn & HW_INTERRUPT_ASSERT_SET_2); |
34f80b04 EG |
4269 | REG_WR(bp, reg_offset, val); |
4270 | ||
4271 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
a8919661 | 4272 | (u32)(attn & HW_INTERRUPT_ASSERT_SET_2)); |
34f80b04 EG |
4273 | bnx2x_panic(); |
4274 | } | |
877e9aa4 ET |
4275 | } |
4276 | ||
1191cb83 | 4277 | static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) |
877e9aa4 | 4278 | { |
34f80b04 EG |
4279 | u32 val; |
4280 | ||
877e9aa4 ET |
4281 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
4282 | ||
34f80b04 EG |
4283 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
4284 | int func = BP_FUNC(bp); | |
4285 | ||
4286 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
a3348722 | 4287 | bnx2x_read_mf_cfg(bp); |
f2e0899f DK |
4288 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
4289 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
4290 | val = SHMEM_RD(bp, | |
4291 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
7609647e YM |
4292 | |
4293 | if (val & (DRV_STATUS_DCC_EVENT_MASK | | |
4294 | DRV_STATUS_OEM_EVENT_MASK)) | |
4295 | bnx2x_oem_event(bp, | |
4296 | (val & (DRV_STATUS_DCC_EVENT_MASK | | |
4297 | DRV_STATUS_OEM_EVENT_MASK))); | |
0793f83f DK |
4298 | |
4299 | if (val & DRV_STATUS_SET_MF_BW) | |
4300 | bnx2x_set_mf_bw(bp); | |
4301 | ||
1d187b34 BW |
4302 | if (val & DRV_STATUS_DRV_INFO_REQ) |
4303 | bnx2x_handle_drv_info_req(bp); | |
d16132ce AE |
4304 | |
4305 | if (val & DRV_STATUS_VF_DISABLED) | |
370d4a26 YM |
4306 | bnx2x_schedule_iov_task(bp, |
4307 | BNX2X_IOV_HANDLE_FLR); | |
d16132ce | 4308 | |
2691d51d | 4309 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
4310 | bnx2x_pmf_update(bp); |
4311 | ||
e4901dde | 4312 | if (bp->port.pmf && |
785b9b1a SR |
4313 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
4314 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
4315 | /* start dcbx state machine */ |
4316 | bnx2x_dcbx_set_params(bp, | |
4317 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
a3348722 BW |
4318 | if (val & DRV_STATUS_AFEX_EVENT_MASK) |
4319 | bnx2x_handle_afex_cmd(bp, | |
4320 | val & DRV_STATUS_AFEX_EVENT_MASK); | |
c8c60d88 YM |
4321 | if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) |
4322 | bnx2x_handle_eee_event(bp); | |
7609647e YM |
4323 | |
4324 | if (val & DRV_STATUS_OEM_UPDATE_SVID) | |
9061193c SRK |
4325 | bnx2x_schedule_sp_rtnl(bp, |
4326 | BNX2X_SP_RTNL_UPDATE_SVID, 0); | |
7609647e | 4327 | |
3deb8167 YR |
4328 | if (bp->link_vars.periodic_flags & |
4329 | PERIODIC_FLAGS_LINK_EVENT) { | |
4330 | /* sync with link */ | |
4331 | bnx2x_acquire_phy_lock(bp); | |
4332 | bp->link_vars.periodic_flags &= | |
4333 | ~PERIODIC_FLAGS_LINK_EVENT; | |
4334 | bnx2x_release_phy_lock(bp); | |
4335 | if (IS_MF(bp)) | |
4336 | bnx2x_link_sync_notify(bp); | |
4337 | bnx2x_link_report(bp); | |
4338 | } | |
4339 | /* Always call it here: bnx2x_link_report() will | |
4340 | * prevent the link indication duplication. | |
4341 | */ | |
4342 | bnx2x__link_status_update(bp); | |
34f80b04 | 4343 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
4344 | |
4345 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 4346 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
4347 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
4348 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
4349 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
4350 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
4351 | bnx2x_panic(); | |
4352 | ||
4353 | } else if (attn & BNX2X_MCP_ASSERT) { | |
4354 | ||
4355 | BNX2X_ERR("MCP assert!\n"); | |
4356 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 4357 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
4358 | |
4359 | } else | |
4360 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
4361 | } | |
4362 | ||
4363 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
4364 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
4365 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
4366 | val = CHIP_IS_E1(bp) ? 0 : |
4367 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
4368 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
4369 | } | |
4370 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
4371 | val = CHIP_IS_E1(bp) ? 0 : |
4372 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
4373 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
4374 | } | |
877e9aa4 | 4375 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
4376 | } |
4377 | } | |
4378 | ||
c9ee9206 VZ |
4379 | /* |
4380 | * Bits map: | |
4381 | * 0-7 - Engine0 load counter. | |
4382 | * 8-15 - Engine1 load counter. | |
4383 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
4384 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
4385 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
4386 | * on the engine | |
4387 | * 19 - Engine1 ONE_IS_LOADED. | |
4388 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
4389 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
4390 | * just the one belonging to its engine). | |
4391 | * | |
4392 | */ | |
4393 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
4394 | ||
4395 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
4396 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
4397 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
4398 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
4399 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
4400 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
4401 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
4402 | ||
4403 | /* | |
4404 | * Set the GLOBAL_RESET bit. | |
4405 | * | |
4406 | * Should be run under rtnl lock | |
4407 | */ | |
4408 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
4409 | { | |
f16da43b AE |
4410 | u32 val; |
4411 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4412 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4413 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
f16da43b | 4414 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 VZ |
4415 | } |
4416 | ||
4417 | /* | |
4418 | * Clear the GLOBAL_RESET bit. | |
4419 | * | |
4420 | * Should be run under rtnl lock | |
4421 | */ | |
1191cb83 | 4422 | static void bnx2x_clear_reset_global(struct bnx2x *bp) |
c9ee9206 | 4423 | { |
f16da43b AE |
4424 | u32 val; |
4425 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4426 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4427 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
f16da43b | 4428 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 | 4429 | } |
f85582f8 | 4430 | |
72fd0718 | 4431 | /* |
c9ee9206 VZ |
4432 | * Checks the GLOBAL_RESET bit. |
4433 | * | |
72fd0718 VZ |
4434 | * should be run under rtnl lock |
4435 | */ | |
1191cb83 | 4436 | static bool bnx2x_reset_is_global(struct bnx2x *bp) |
c9ee9206 | 4437 | { |
3cdeec22 | 4438 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
c9ee9206 VZ |
4439 | |
4440 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
4441 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
4442 | } | |
4443 | ||
4444 | /* | |
4445 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
4446 | * | |
4447 | * Should be run under rtnl lock | |
4448 | */ | |
1191cb83 | 4449 | static void bnx2x_set_reset_done(struct bnx2x *bp) |
72fd0718 | 4450 | { |
f16da43b | 4451 | u32 val; |
c9ee9206 VZ |
4452 | u32 bit = BP_PATH(bp) ? |
4453 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4454 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4455 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4456 | |
4457 | /* Clear the bit */ | |
4458 | val &= ~bit; | |
4459 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4460 | |
4461 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
72fd0718 VZ |
4462 | } |
4463 | ||
4464 | /* | |
c9ee9206 VZ |
4465 | * Set RESET_IN_PROGRESS for the current engine. |
4466 | * | |
72fd0718 VZ |
4467 | * should be run under rtnl lock |
4468 | */ | |
c9ee9206 | 4469 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 4470 | { |
f16da43b | 4471 | u32 val; |
c9ee9206 VZ |
4472 | u32 bit = BP_PATH(bp) ? |
4473 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4474 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4475 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4476 | |
4477 | /* Set the bit */ | |
4478 | val |= bit; | |
4479 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4480 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4481 | } |
4482 | ||
4483 | /* | |
c9ee9206 | 4484 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
4485 | * should be run under rtnl lock |
4486 | */ | |
c9ee9206 | 4487 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 4488 | { |
3cdeec22 | 4489 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
c9ee9206 VZ |
4490 | u32 bit = engine ? |
4491 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
4492 | ||
4493 | /* return false if bit is set */ | |
4494 | return (val & bit) ? false : true; | |
72fd0718 VZ |
4495 | } |
4496 | ||
4497 | /* | |
889b9af3 | 4498 | * set pf load for the current pf. |
c9ee9206 | 4499 | * |
72fd0718 VZ |
4500 | * should be run under rtnl lock |
4501 | */ | |
889b9af3 | 4502 | void bnx2x_set_pf_load(struct bnx2x *bp) |
72fd0718 | 4503 | { |
f16da43b | 4504 | u32 val1, val; |
c9ee9206 VZ |
4505 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4506 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4507 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4508 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4509 | |
f16da43b AE |
4510 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4511 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4512 | ||
51c1a580 | 4513 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4514 | |
c9ee9206 VZ |
4515 | /* get the current counter value */ |
4516 | val1 = (val & mask) >> shift; | |
4517 | ||
889b9af3 AE |
4518 | /* set bit of that PF */ |
4519 | val1 |= (1 << bp->pf_num); | |
c9ee9206 VZ |
4520 | |
4521 | /* clear the old value */ | |
4522 | val &= ~mask; | |
4523 | ||
4524 | /* set the new one */ | |
4525 | val |= ((val1 << shift) & mask); | |
4526 | ||
4527 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4528 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4529 | } |
4530 | ||
c9ee9206 | 4531 | /** |
889b9af3 | 4532 | * bnx2x_clear_pf_load - clear pf load mark |
c9ee9206 VZ |
4533 | * |
4534 | * @bp: driver handle | |
4535 | * | |
4536 | * Should be run under rtnl lock. | |
4537 | * Decrements the load counter for the current engine. Returns | |
889b9af3 | 4538 | * whether other functions are still loaded |
72fd0718 | 4539 | */ |
889b9af3 | 4540 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
72fd0718 | 4541 | { |
f16da43b | 4542 | u32 val1, val; |
c9ee9206 VZ |
4543 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4544 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4545 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4546 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4547 | |
f16da43b AE |
4548 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4549 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
51c1a580 | 4550 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4551 | |
c9ee9206 VZ |
4552 | /* get the current counter value */ |
4553 | val1 = (val & mask) >> shift; | |
4554 | ||
889b9af3 AE |
4555 | /* clear bit of that PF */ |
4556 | val1 &= ~(1 << bp->pf_num); | |
c9ee9206 VZ |
4557 | |
4558 | /* clear the old value */ | |
4559 | val &= ~mask; | |
4560 | ||
4561 | /* set the new one */ | |
4562 | val |= ((val1 << shift) & mask); | |
4563 | ||
4564 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4565 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4566 | return val1 != 0; | |
72fd0718 VZ |
4567 | } |
4568 | ||
4569 | /* | |
889b9af3 | 4570 | * Read the load status for the current engine. |
c9ee9206 | 4571 | * |
72fd0718 VZ |
4572 | * should be run under rtnl lock |
4573 | */ | |
1191cb83 | 4574 | static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
72fd0718 | 4575 | { |
c9ee9206 VZ |
4576 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
4577 | BNX2X_PATH0_LOAD_CNT_MASK); | |
4578 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4579 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
4580 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4581 | ||
51c1a580 | 4582 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
c9ee9206 VZ |
4583 | |
4584 | val = (val & mask) >> shift; | |
4585 | ||
51c1a580 MS |
4586 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
4587 | engine, val); | |
c9ee9206 | 4588 | |
889b9af3 | 4589 | return val != 0; |
72fd0718 VZ |
4590 | } |
4591 | ||
6bf07b8e YM |
4592 | static void _print_parity(struct bnx2x *bp, u32 reg) |
4593 | { | |
4594 | pr_cont(" [0x%08x] ", REG_RD(bp, reg)); | |
4595 | } | |
4596 | ||
1191cb83 | 4597 | static void _print_next_block(int idx, const char *blk) |
72fd0718 | 4598 | { |
f1deab50 | 4599 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
4600 | } |
4601 | ||
4293b9f5 DK |
4602 | static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, |
4603 | int *par_num, bool print) | |
72fd0718 | 4604 | { |
4293b9f5 DK |
4605 | u32 cur_bit; |
4606 | bool res; | |
4607 | int i; | |
4608 | ||
4609 | res = false; | |
4610 | ||
72fd0718 | 4611 | for (i = 0; sig; i++) { |
4293b9f5 | 4612 | cur_bit = (0x1UL << i); |
72fd0718 | 4613 | if (sig & cur_bit) { |
4293b9f5 DK |
4614 | res |= true; /* Each bit is real error! */ |
4615 | ||
4616 | if (print) { | |
4617 | switch (cur_bit) { | |
4618 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
4619 | _print_next_block((*par_num)++, "BRB"); | |
6bf07b8e YM |
4620 | _print_parity(bp, |
4621 | BRB1_REG_BRB1_PRTY_STS); | |
4293b9f5 DK |
4622 | break; |
4623 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
4624 | _print_next_block((*par_num)++, | |
4625 | "PARSER"); | |
6bf07b8e | 4626 | _print_parity(bp, PRS_REG_PRS_PRTY_STS); |
4293b9f5 DK |
4627 | break; |
4628 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
4629 | _print_next_block((*par_num)++, "TSDM"); | |
6bf07b8e YM |
4630 | _print_parity(bp, |
4631 | TSDM_REG_TSDM_PRTY_STS); | |
4293b9f5 DK |
4632 | break; |
4633 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
4634 | _print_next_block((*par_num)++, | |
c9ee9206 | 4635 | "SEARCHER"); |
6bf07b8e | 4636 | _print_parity(bp, SRC_REG_SRC_PRTY_STS); |
4293b9f5 DK |
4637 | break; |
4638 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
4639 | _print_next_block((*par_num)++, "TCM"); | |
4640 | _print_parity(bp, TCM_REG_TCM_PRTY_STS); | |
4641 | break; | |
4642 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
4643 | _print_next_block((*par_num)++, | |
4644 | "TSEMI"); | |
6bf07b8e YM |
4645 | _print_parity(bp, |
4646 | TSEM_REG_TSEM_PRTY_STS_0); | |
4647 | _print_parity(bp, | |
4648 | TSEM_REG_TSEM_PRTY_STS_1); | |
4293b9f5 DK |
4649 | break; |
4650 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
4651 | _print_next_block((*par_num)++, "XPB"); | |
6bf07b8e YM |
4652 | _print_parity(bp, GRCBASE_XPB + |
4653 | PB_REG_PB_PRTY_STS); | |
4293b9f5 | 4654 | break; |
6bf07b8e | 4655 | } |
72fd0718 VZ |
4656 | } |
4657 | ||
4658 | /* Clear the bit */ | |
4659 | sig &= ~cur_bit; | |
4660 | } | |
4661 | } | |
4662 | ||
4293b9f5 | 4663 | return res; |
72fd0718 VZ |
4664 | } |
4665 | ||
4293b9f5 DK |
4666 | static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, |
4667 | int *par_num, bool *global, | |
6bf07b8e | 4668 | bool print) |
72fd0718 | 4669 | { |
4293b9f5 DK |
4670 | u32 cur_bit; |
4671 | bool res; | |
4672 | int i; | |
4673 | ||
4674 | res = false; | |
4675 | ||
72fd0718 | 4676 | for (i = 0; sig; i++) { |
4293b9f5 | 4677 | cur_bit = (0x1UL << i); |
72fd0718 | 4678 | if (sig & cur_bit) { |
4293b9f5 | 4679 | res |= true; /* Each bit is real error! */ |
72fd0718 | 4680 | switch (cur_bit) { |
c9ee9206 | 4681 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
6bf07b8e | 4682 | if (print) { |
4293b9f5 | 4683 | _print_next_block((*par_num)++, "PBF"); |
6bf07b8e YM |
4684 | _print_parity(bp, PBF_REG_PBF_PRTY_STS); |
4685 | } | |
72fd0718 VZ |
4686 | break; |
4687 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
6bf07b8e | 4688 | if (print) { |
4293b9f5 | 4689 | _print_next_block((*par_num)++, "QM"); |
6bf07b8e YM |
4690 | _print_parity(bp, QM_REG_QM_PRTY_STS); |
4691 | } | |
c9ee9206 VZ |
4692 | break; |
4693 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
6bf07b8e | 4694 | if (print) { |
4293b9f5 | 4695 | _print_next_block((*par_num)++, "TM"); |
6bf07b8e YM |
4696 | _print_parity(bp, TM_REG_TM_PRTY_STS); |
4697 | } | |
72fd0718 VZ |
4698 | break; |
4699 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
6bf07b8e | 4700 | if (print) { |
4293b9f5 | 4701 | _print_next_block((*par_num)++, "XSDM"); |
6bf07b8e YM |
4702 | _print_parity(bp, |
4703 | XSDM_REG_XSDM_PRTY_STS); | |
4704 | } | |
c9ee9206 VZ |
4705 | break; |
4706 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
6bf07b8e | 4707 | if (print) { |
4293b9f5 | 4708 | _print_next_block((*par_num)++, "XCM"); |
6bf07b8e YM |
4709 | _print_parity(bp, XCM_REG_XCM_PRTY_STS); |
4710 | } | |
72fd0718 VZ |
4711 | break; |
4712 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
6bf07b8e | 4713 | if (print) { |
4293b9f5 DK |
4714 | _print_next_block((*par_num)++, |
4715 | "XSEMI"); | |
6bf07b8e YM |
4716 | _print_parity(bp, |
4717 | XSEM_REG_XSEM_PRTY_STS_0); | |
4718 | _print_parity(bp, | |
4719 | XSEM_REG_XSEM_PRTY_STS_1); | |
4720 | } | |
72fd0718 VZ |
4721 | break; |
4722 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
6bf07b8e | 4723 | if (print) { |
4293b9f5 | 4724 | _print_next_block((*par_num)++, |
c9ee9206 | 4725 | "DOORBELLQ"); |
6bf07b8e YM |
4726 | _print_parity(bp, |
4727 | DORQ_REG_DORQ_PRTY_STS); | |
4728 | } | |
c9ee9206 VZ |
4729 | break; |
4730 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
6bf07b8e | 4731 | if (print) { |
4293b9f5 | 4732 | _print_next_block((*par_num)++, "NIG"); |
6bf07b8e YM |
4733 | if (CHIP_IS_E1x(bp)) { |
4734 | _print_parity(bp, | |
4735 | NIG_REG_NIG_PRTY_STS); | |
4736 | } else { | |
4737 | _print_parity(bp, | |
4738 | NIG_REG_NIG_PRTY_STS_0); | |
4739 | _print_parity(bp, | |
4740 | NIG_REG_NIG_PRTY_STS_1); | |
4741 | } | |
4742 | } | |
72fd0718 VZ |
4743 | break; |
4744 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 | 4745 | if (print) |
4293b9f5 | 4746 | _print_next_block((*par_num)++, |
c9ee9206 VZ |
4747 | "VAUX PCI CORE"); |
4748 | *global = true; | |
72fd0718 VZ |
4749 | break; |
4750 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
6bf07b8e | 4751 | if (print) { |
4293b9f5 DK |
4752 | _print_next_block((*par_num)++, |
4753 | "DEBUG"); | |
6bf07b8e YM |
4754 | _print_parity(bp, DBG_REG_DBG_PRTY_STS); |
4755 | } | |
72fd0718 VZ |
4756 | break; |
4757 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
6bf07b8e | 4758 | if (print) { |
4293b9f5 | 4759 | _print_next_block((*par_num)++, "USDM"); |
6bf07b8e YM |
4760 | _print_parity(bp, |
4761 | USDM_REG_USDM_PRTY_STS); | |
4762 | } | |
72fd0718 | 4763 | break; |
8736c826 | 4764 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
6bf07b8e | 4765 | if (print) { |
4293b9f5 | 4766 | _print_next_block((*par_num)++, "UCM"); |
6bf07b8e YM |
4767 | _print_parity(bp, UCM_REG_UCM_PRTY_STS); |
4768 | } | |
8736c826 | 4769 | break; |
72fd0718 | 4770 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
6bf07b8e | 4771 | if (print) { |
4293b9f5 DK |
4772 | _print_next_block((*par_num)++, |
4773 | "USEMI"); | |
6bf07b8e YM |
4774 | _print_parity(bp, |
4775 | USEM_REG_USEM_PRTY_STS_0); | |
4776 | _print_parity(bp, | |
4777 | USEM_REG_USEM_PRTY_STS_1); | |
4778 | } | |
72fd0718 VZ |
4779 | break; |
4780 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
6bf07b8e | 4781 | if (print) { |
4293b9f5 | 4782 | _print_next_block((*par_num)++, "UPB"); |
6bf07b8e YM |
4783 | _print_parity(bp, GRCBASE_UPB + |
4784 | PB_REG_PB_PRTY_STS); | |
4785 | } | |
72fd0718 VZ |
4786 | break; |
4787 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
6bf07b8e | 4788 | if (print) { |
4293b9f5 | 4789 | _print_next_block((*par_num)++, "CSDM"); |
6bf07b8e YM |
4790 | _print_parity(bp, |
4791 | CSDM_REG_CSDM_PRTY_STS); | |
4792 | } | |
72fd0718 | 4793 | break; |
8736c826 | 4794 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
6bf07b8e | 4795 | if (print) { |
4293b9f5 | 4796 | _print_next_block((*par_num)++, "CCM"); |
6bf07b8e YM |
4797 | _print_parity(bp, CCM_REG_CCM_PRTY_STS); |
4798 | } | |
8736c826 | 4799 | break; |
72fd0718 VZ |
4800 | } |
4801 | ||
4802 | /* Clear the bit */ | |
4803 | sig &= ~cur_bit; | |
4804 | } | |
4805 | } | |
4806 | ||
4293b9f5 | 4807 | return res; |
72fd0718 VZ |
4808 | } |
4809 | ||
4293b9f5 DK |
4810 | static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, |
4811 | int *par_num, bool print) | |
72fd0718 | 4812 | { |
4293b9f5 DK |
4813 | u32 cur_bit; |
4814 | bool res; | |
4815 | int i; | |
4816 | ||
4817 | res = false; | |
4818 | ||
72fd0718 | 4819 | for (i = 0; sig; i++) { |
4293b9f5 | 4820 | cur_bit = (0x1UL << i); |
72fd0718 | 4821 | if (sig & cur_bit) { |
0c23ad37 | 4822 | res = true; /* Each bit is real error! */ |
4293b9f5 DK |
4823 | if (print) { |
4824 | switch (cur_bit) { | |
4825 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
4826 | _print_next_block((*par_num)++, | |
4827 | "CSEMI"); | |
6bf07b8e YM |
4828 | _print_parity(bp, |
4829 | CSEM_REG_CSEM_PRTY_STS_0); | |
4830 | _print_parity(bp, | |
4831 | CSEM_REG_CSEM_PRTY_STS_1); | |
4293b9f5 DK |
4832 | break; |
4833 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
4834 | _print_next_block((*par_num)++, "PXP"); | |
6bf07b8e YM |
4835 | _print_parity(bp, PXP_REG_PXP_PRTY_STS); |
4836 | _print_parity(bp, | |
4837 | PXP2_REG_PXP2_PRTY_STS_0); | |
4838 | _print_parity(bp, | |
4839 | PXP2_REG_PXP2_PRTY_STS_1); | |
4293b9f5 DK |
4840 | break; |
4841 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
4842 | _print_next_block((*par_num)++, | |
4843 | "PXPPCICLOCKCLIENT"); | |
4844 | break; | |
4845 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
4846 | _print_next_block((*par_num)++, "CFC"); | |
6bf07b8e YM |
4847 | _print_parity(bp, |
4848 | CFC_REG_CFC_PRTY_STS); | |
4293b9f5 DK |
4849 | break; |
4850 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
4851 | _print_next_block((*par_num)++, "CDU"); | |
6bf07b8e | 4852 | _print_parity(bp, CDU_REG_CDU_PRTY_STS); |
4293b9f5 DK |
4853 | break; |
4854 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
4855 | _print_next_block((*par_num)++, "DMAE"); | |
6bf07b8e YM |
4856 | _print_parity(bp, |
4857 | DMAE_REG_DMAE_PRTY_STS); | |
4293b9f5 DK |
4858 | break; |
4859 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
4860 | _print_next_block((*par_num)++, "IGU"); | |
6bf07b8e YM |
4861 | if (CHIP_IS_E1x(bp)) |
4862 | _print_parity(bp, | |
4863 | HC_REG_HC_PRTY_STS); | |
4864 | else | |
4865 | _print_parity(bp, | |
4866 | IGU_REG_IGU_PRTY_STS); | |
4293b9f5 DK |
4867 | break; |
4868 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
4869 | _print_next_block((*par_num)++, "MISC"); | |
6bf07b8e YM |
4870 | _print_parity(bp, |
4871 | MISC_REG_MISC_PRTY_STS); | |
4293b9f5 | 4872 | break; |
6bf07b8e | 4873 | } |
72fd0718 VZ |
4874 | } |
4875 | ||
4876 | /* Clear the bit */ | |
4877 | sig &= ~cur_bit; | |
4878 | } | |
4879 | } | |
4880 | ||
4293b9f5 | 4881 | return res; |
72fd0718 VZ |
4882 | } |
4883 | ||
4293b9f5 DK |
4884 | static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig, |
4885 | int *par_num, bool *global, | |
4886 | bool print) | |
72fd0718 | 4887 | { |
4293b9f5 DK |
4888 | bool res = false; |
4889 | u32 cur_bit; | |
4890 | int i; | |
4891 | ||
72fd0718 | 4892 | for (i = 0; sig; i++) { |
4293b9f5 | 4893 | cur_bit = (0x1UL << i); |
72fd0718 VZ |
4894 | if (sig & cur_bit) { |
4895 | switch (cur_bit) { | |
4896 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 | 4897 | if (print) |
4293b9f5 DK |
4898 | _print_next_block((*par_num)++, |
4899 | "MCP ROM"); | |
c9ee9206 | 4900 | *global = true; |
0c23ad37 | 4901 | res = true; |
72fd0718 VZ |
4902 | break; |
4903 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 | 4904 | if (print) |
4293b9f5 | 4905 | _print_next_block((*par_num)++, |
c9ee9206 VZ |
4906 | "MCP UMP RX"); |
4907 | *global = true; | |
0c23ad37 | 4908 | res = true; |
72fd0718 VZ |
4909 | break; |
4910 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 | 4911 | if (print) |
4293b9f5 | 4912 | _print_next_block((*par_num)++, |
c9ee9206 VZ |
4913 | "MCP UMP TX"); |
4914 | *global = true; | |
0c23ad37 | 4915 | res = true; |
72fd0718 VZ |
4916 | break; |
4917 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
ad6afbe9 | 4918 | (*par_num)++; |
4293b9f5 DK |
4919 | /* clear latched SCPAD PATIRY from MCP */ |
4920 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, | |
4921 | 1UL << 10); | |
72fd0718 VZ |
4922 | break; |
4923 | } | |
4924 | ||
4925 | /* Clear the bit */ | |
4926 | sig &= ~cur_bit; | |
4927 | } | |
4928 | } | |
4929 | ||
4293b9f5 | 4930 | return res; |
72fd0718 VZ |
4931 | } |
4932 | ||
4293b9f5 DK |
4933 | static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, |
4934 | int *par_num, bool print) | |
8736c826 | 4935 | { |
4293b9f5 DK |
4936 | u32 cur_bit; |
4937 | bool res; | |
4938 | int i; | |
4939 | ||
4940 | res = false; | |
4941 | ||
8736c826 | 4942 | for (i = 0; sig; i++) { |
4293b9f5 | 4943 | cur_bit = (0x1UL << i); |
8736c826 | 4944 | if (sig & cur_bit) { |
0c23ad37 | 4945 | res = true; /* Each bit is real error! */ |
4293b9f5 DK |
4946 | if (print) { |
4947 | switch (cur_bit) { | |
4948 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
4949 | _print_next_block((*par_num)++, | |
4950 | "PGLUE_B"); | |
6bf07b8e | 4951 | _print_parity(bp, |
4293b9f5 DK |
4952 | PGLUE_B_REG_PGLUE_B_PRTY_STS); |
4953 | break; | |
4954 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
4955 | _print_next_block((*par_num)++, "ATC"); | |
6bf07b8e YM |
4956 | _print_parity(bp, |
4957 | ATC_REG_ATC_PRTY_STS); | |
4293b9f5 | 4958 | break; |
6bf07b8e | 4959 | } |
8736c826 | 4960 | } |
8736c826 VZ |
4961 | /* Clear the bit */ |
4962 | sig &= ~cur_bit; | |
4963 | } | |
4964 | } | |
4965 | ||
4293b9f5 | 4966 | return res; |
8736c826 VZ |
4967 | } |
4968 | ||
1191cb83 ED |
4969 | static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
4970 | u32 *sig) | |
72fd0718 | 4971 | { |
4293b9f5 DK |
4972 | bool res = false; |
4973 | ||
8736c826 VZ |
4974 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4975 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4976 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4977 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4978 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 | 4979 | int par_num = 0; |
ad6afbe9 | 4980 | |
51c1a580 MS |
4981 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
4982 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", | |
8736c826 VZ |
4983 | sig[0] & HW_PRTY_ASSERT_SET_0, |
4984 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4985 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4986 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4987 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
ad6afbe9 MC |
4988 | if (print) { |
4989 | if (((sig[0] & HW_PRTY_ASSERT_SET_0) || | |
4990 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4991 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4992 | (sig[4] & HW_PRTY_ASSERT_SET_4)) || | |
4993 | (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) { | |
4994 | netdev_err(bp->dev, | |
4995 | "Parity errors detected in blocks: "); | |
4996 | } else { | |
4997 | print = false; | |
4998 | } | |
4999 | } | |
4293b9f5 DK |
5000 | res |= bnx2x_check_blocks_with_parity0(bp, |
5001 | sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print); | |
5002 | res |= bnx2x_check_blocks_with_parity1(bp, | |
5003 | sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print); | |
5004 | res |= bnx2x_check_blocks_with_parity2(bp, | |
5005 | sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print); | |
5006 | res |= bnx2x_check_blocks_with_parity3(bp, | |
5007 | sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print); | |
5008 | res |= bnx2x_check_blocks_with_parity4(bp, | |
5009 | sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print); | |
8736c826 | 5010 | |
c9ee9206 VZ |
5011 | if (print) |
5012 | pr_cont("\n"); | |
4293b9f5 | 5013 | } |
8736c826 | 5014 | |
4293b9f5 | 5015 | return res; |
72fd0718 VZ |
5016 | } |
5017 | ||
c9ee9206 VZ |
5018 | /** |
5019 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
5020 | * | |
5021 | * @bp: driver handle | |
5022 | * @global: true if there was a global attention | |
5023 | * @print: show parity attention in syslog | |
5024 | */ | |
5025 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 5026 | { |
8736c826 | 5027 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
5028 | int port = BP_PORT(bp); |
5029 | ||
5030 | attn.sig[0] = REG_RD(bp, | |
5031 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
5032 | port*4); | |
5033 | attn.sig[1] = REG_RD(bp, | |
5034 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
5035 | port*4); | |
5036 | attn.sig[2] = REG_RD(bp, | |
5037 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
5038 | port*4); | |
5039 | attn.sig[3] = REG_RD(bp, | |
5040 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
5041 | port*4); | |
0a5ccb75 YM |
5042 | /* Since MCP attentions can't be disabled inside the block, we need to |
5043 | * read AEU registers to see whether they're currently disabled | |
5044 | */ | |
5045 | attn.sig[3] &= ((REG_RD(bp, | |
5046 | !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 | |
5047 | : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) & | |
5048 | MISC_AEU_ENABLE_MCP_PRTY_BITS) | | |
5049 | ~MISC_AEU_ENABLE_MCP_PRTY_BITS); | |
72fd0718 | 5050 | |
8736c826 VZ |
5051 | if (!CHIP_IS_E1x(bp)) |
5052 | attn.sig[4] = REG_RD(bp, | |
5053 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
5054 | port*4); | |
5055 | ||
5056 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
5057 | } |
5058 | ||
1191cb83 | 5059 | static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) |
f2e0899f DK |
5060 | { |
5061 | u32 val; | |
5062 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
5063 | ||
5064 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
5065 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
5066 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
51c1a580 | 5067 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
f2e0899f | 5068 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
51c1a580 | 5069 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
f2e0899f | 5070 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
51c1a580 | 5071 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
f2e0899f | 5072 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
51c1a580 | 5073 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
f2e0899f DK |
5074 | if (val & |
5075 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
51c1a580 | 5076 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
f2e0899f DK |
5077 | if (val & |
5078 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
51c1a580 | 5079 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
f2e0899f | 5080 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
51c1a580 | 5081 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
f2e0899f | 5082 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
51c1a580 | 5083 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
f2e0899f | 5084 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
51c1a580 | 5085 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
f2e0899f DK |
5086 | } |
5087 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
5088 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
5089 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
5090 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
5091 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
5092 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
51c1a580 | 5093 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
f2e0899f | 5094 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
51c1a580 | 5095 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
f2e0899f | 5096 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
51c1a580 | 5097 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
f2e0899f DK |
5098 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
5099 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
5100 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
51c1a580 | 5101 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
f2e0899f DK |
5102 | } |
5103 | ||
5104 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
5105 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
5106 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
5107 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
5108 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
5109 | } | |
f2e0899f DK |
5110 | } |
5111 | ||
72fd0718 VZ |
5112 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
5113 | { | |
5114 | struct attn_route attn, *group_mask; | |
34f80b04 | 5115 | int port = BP_PORT(bp); |
877e9aa4 | 5116 | int index; |
a2fbb9ea ET |
5117 | u32 reg_addr; |
5118 | u32 val; | |
3fcaf2e5 | 5119 | u32 aeu_mask; |
c9ee9206 | 5120 | bool global = false; |
a2fbb9ea ET |
5121 | |
5122 | /* need to take HW lock because MCP or other port might also | |
5123 | try to handle this event */ | |
4a37fb66 | 5124 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 5125 | |
c9ee9206 VZ |
5126 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
5127 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 5128 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 5129 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
5130 | /* Disable HW interrupts */ |
5131 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
5132 | /* In case of parity errors don't handle attentions so that |
5133 | * other function would "see" parity errors. | |
5134 | */ | |
c9ee9206 VZ |
5135 | #else |
5136 | bnx2x_panic(); | |
5137 | #endif | |
5138 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
5139 | return; |
5140 | } | |
5141 | ||
a2fbb9ea ET |
5142 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
5143 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
5144 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
5145 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 5146 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5147 | attn.sig[4] = |
5148 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
5149 | else | |
5150 | attn.sig[4] = 0; | |
5151 | ||
5152 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
5153 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
5154 | |
5155 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
5156 | if (deasserted & (1 << index)) { | |
72fd0718 | 5157 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 5158 | |
51c1a580 | 5159 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
f2e0899f DK |
5160 | index, |
5161 | group_mask->sig[0], group_mask->sig[1], | |
5162 | group_mask->sig[2], group_mask->sig[3], | |
5163 | group_mask->sig[4]); | |
a2fbb9ea | 5164 | |
f2e0899f DK |
5165 | bnx2x_attn_int_deasserted4(bp, |
5166 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 5167 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 5168 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 5169 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 5170 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 5171 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 5172 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 5173 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 5174 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
5175 | } |
5176 | } | |
5177 | ||
4a37fb66 | 5178 | bnx2x_release_alr(bp); |
a2fbb9ea | 5179 | |
f2e0899f DK |
5180 | if (bp->common.int_block == INT_BLOCK_HC) |
5181 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
5182 | COMMAND_REG_ATTN_BITS_CLR); | |
5183 | else | |
5184 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
5185 | |
5186 | val = ~deasserted; | |
f2e0899f DK |
5187 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
5188 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 5189 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 5190 | |
a2fbb9ea | 5191 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 5192 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
5193 | |
5194 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
5195 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
5196 | ||
3fcaf2e5 EG |
5197 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
5198 | aeu_mask = REG_RD(bp, reg_addr); | |
5199 | ||
5200 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
5201 | aeu_mask, deasserted); | |
72fd0718 | 5202 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 5203 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 5204 | |
3fcaf2e5 EG |
5205 | REG_WR(bp, reg_addr, aeu_mask); |
5206 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
5207 | |
5208 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
5209 | bp->attn_state &= ~deasserted; | |
5210 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
5211 | } | |
5212 | ||
5213 | static void bnx2x_attn_int(struct bnx2x *bp) | |
5214 | { | |
5215 | /* read local copy of bits */ | |
68d59484 EG |
5216 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
5217 | attn_bits); | |
5218 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
5219 | attn_bits_ack); | |
a2fbb9ea ET |
5220 | u32 attn_state = bp->attn_state; |
5221 | ||
5222 | /* look for changed bits */ | |
5223 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
5224 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
5225 | ||
5226 | DP(NETIF_MSG_HW, | |
5227 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
5228 | attn_bits, attn_ack, asserted, deasserted); | |
5229 | ||
5230 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 5231 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
5232 | |
5233 | /* handle bits that were raised */ | |
5234 | if (asserted) | |
5235 | bnx2x_attn_int_asserted(bp, asserted); | |
5236 | ||
5237 | if (deasserted) | |
5238 | bnx2x_attn_int_deasserted(bp, deasserted); | |
5239 | } | |
5240 | ||
619c5cb6 VZ |
5241 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
5242 | u16 index, u8 op, u8 update) | |
5243 | { | |
dc1ba591 AE |
5244 | u32 igu_addr = bp->igu_base_addr; |
5245 | igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
619c5cb6 VZ |
5246 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, |
5247 | igu_addr); | |
5248 | } | |
5249 | ||
1191cb83 | 5250 | static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
523224a3 DK |
5251 | { |
5252 | /* No memory barriers */ | |
5253 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
523224a3 DK |
5254 | } |
5255 | ||
523224a3 DK |
5256 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, |
5257 | union event_ring_elem *elem) | |
5258 | { | |
619c5cb6 VZ |
5259 | u8 err = elem->message.error; |
5260 | ||
523224a3 | 5261 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
5262 | (cid < bp->cnic_eth_dev.starting_cid && |
5263 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
5264 | return 1; |
5265 | ||
5266 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
5267 | ||
619c5cb6 VZ |
5268 | if (unlikely(err)) { |
5269 | ||
523224a3 DK |
5270 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
5271 | cid); | |
823e1d90 | 5272 | bnx2x_panic_dump(bp, false); |
523224a3 | 5273 | } |
619c5cb6 | 5274 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
5275 | return 0; |
5276 | } | |
523224a3 | 5277 | |
1191cb83 | 5278 | static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
5279 | { |
5280 | struct bnx2x_mcast_ramrod_params rparam; | |
5281 | int rc; | |
5282 | ||
5283 | memset(&rparam, 0, sizeof(rparam)); | |
5284 | ||
5285 | rparam.mcast_obj = &bp->mcast_obj; | |
5286 | ||
5287 | netif_addr_lock_bh(bp->dev); | |
5288 | ||
5289 | /* Clear pending state for the last command */ | |
5290 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
5291 | ||
5292 | /* If there are pending mcast commands - send them */ | |
5293 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
5294 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
5295 | if (rc < 0) | |
5296 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
5297 | rc); | |
5298 | } | |
5299 | ||
5300 | netif_addr_unlock_bh(bp->dev); | |
5301 | } | |
5302 | ||
1191cb83 ED |
5303 | static void bnx2x_handle_classification_eqe(struct bnx2x *bp, |
5304 | union event_ring_elem *elem) | |
619c5cb6 VZ |
5305 | { |
5306 | unsigned long ramrod_flags = 0; | |
5307 | int rc = 0; | |
9cd753a1 MS |
5308 | u32 echo = le32_to_cpu(elem->message.data.eth_event.echo); |
5309 | u32 cid = echo & BNX2X_SWCID_MASK; | |
619c5cb6 VZ |
5310 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; |
5311 | ||
5312 | /* Always push next commands out, don't wait here */ | |
5313 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
5314 | ||
9cd753a1 | 5315 | switch (echo >> BNX2X_SWCID_SHIFT) { |
619c5cb6 | 5316 | case BNX2X_FILTER_MAC_PENDING: |
51c1a580 | 5317 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
55c11941 | 5318 | if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) |
619c5cb6 VZ |
5319 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; |
5320 | else | |
15192a8c | 5321 | vlan_mac_obj = &bp->sp_objs[cid].mac_obj; |
619c5cb6 | 5322 | |
05cc5a39 YM |
5323 | break; |
5324 | case BNX2X_FILTER_VLAN_PENDING: | |
5325 | DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n"); | |
5326 | vlan_mac_obj = &bp->sp_objs[cid].vlan_obj; | |
619c5cb6 | 5327 | break; |
619c5cb6 | 5328 | case BNX2X_FILTER_MCAST_PENDING: |
51c1a580 | 5329 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
619c5cb6 VZ |
5330 | /* This is only relevant for 57710 where multicast MACs are |
5331 | * configured as unicast MACs using the same ramrod. | |
5332 | */ | |
5333 | bnx2x_handle_mcast_eqe(bp); | |
5334 | return; | |
5335 | default: | |
9cd753a1 | 5336 | BNX2X_ERR("Unsupported classification command: 0x%x\n", echo); |
619c5cb6 VZ |
5337 | return; |
5338 | } | |
5339 | ||
5340 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
5341 | ||
5342 | if (rc < 0) | |
5343 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
5344 | else if (rc > 0) | |
5345 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
619c5cb6 VZ |
5346 | } |
5347 | ||
619c5cb6 | 5348 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); |
619c5cb6 | 5349 | |
1191cb83 | 5350 | static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
5351 | { |
5352 | netif_addr_lock_bh(bp->dev); | |
5353 | ||
5354 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5355 | ||
5356 | /* Send rx_mode command again if was requested */ | |
5357 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
5358 | bnx2x_set_storm_rx_mode(bp); | |
619c5cb6 VZ |
5359 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, |
5360 | &bp->sp_state)) | |
5361 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
5362 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
5363 | &bp->sp_state)) | |
5364 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
619c5cb6 VZ |
5365 | |
5366 | netif_addr_unlock_bh(bp->dev); | |
5367 | } | |
5368 | ||
1191cb83 | 5369 | static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, |
a3348722 BW |
5370 | union event_ring_elem *elem) |
5371 | { | |
5372 | if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { | |
5373 | DP(BNX2X_MSG_SP, | |
5374 | "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", | |
5375 | elem->message.data.vif_list_event.func_bit_map); | |
5376 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, | |
5377 | elem->message.data.vif_list_event.func_bit_map); | |
5378 | } else if (elem->message.data.vif_list_event.echo == | |
5379 | VIF_LIST_RULE_SET) { | |
5380 | DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); | |
5381 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); | |
5382 | } | |
5383 | } | |
5384 | ||
5385 | /* called with rtnl_lock */ | |
1191cb83 | 5386 | static void bnx2x_after_function_update(struct bnx2x *bp) |
a3348722 BW |
5387 | { |
5388 | int q, rc; | |
5389 | struct bnx2x_fastpath *fp; | |
5390 | struct bnx2x_queue_state_params queue_params = {NULL}; | |
5391 | struct bnx2x_queue_update_params *q_update_params = | |
5392 | &queue_params.params.update; | |
5393 | ||
2de67439 | 5394 | /* Send Q update command with afex vlan removal values for all Qs */ |
a3348722 BW |
5395 | queue_params.cmd = BNX2X_Q_CMD_UPDATE; |
5396 | ||
5397 | /* set silent vlan removal values according to vlan mode */ | |
5398 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | |
5399 | &q_update_params->update_flags); | |
5400 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
5401 | &q_update_params->update_flags); | |
5402 | __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
5403 | ||
5404 | /* in access mode mark mask and value are 0 to strip all vlans */ | |
5405 | if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { | |
5406 | q_update_params->silent_removal_value = 0; | |
5407 | q_update_params->silent_removal_mask = 0; | |
5408 | } else { | |
5409 | q_update_params->silent_removal_value = | |
5410 | (bp->afex_def_vlan_tag & VLAN_VID_MASK); | |
5411 | q_update_params->silent_removal_mask = VLAN_VID_MASK; | |
5412 | } | |
5413 | ||
5414 | for_each_eth_queue(bp, q) { | |
5415 | /* Set the appropriate Queue object */ | |
5416 | fp = &bp->fp[q]; | |
15192a8c | 5417 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
5418 | |
5419 | /* send the ramrod */ | |
5420 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
5421 | if (rc < 0) | |
5422 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
5423 | q); | |
5424 | } | |
5425 | ||
fea75645 | 5426 | if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { |
65565884 | 5427 | fp = &bp->fp[FCOE_IDX(bp)]; |
15192a8c | 5428 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
5429 | |
5430 | /* clear pending completion bit */ | |
5431 | __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
5432 | ||
5433 | /* mark latest Q bit */ | |
4e857c58 | 5434 | smp_mb__before_atomic(); |
a3348722 | 5435 | set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); |
4e857c58 | 5436 | smp_mb__after_atomic(); |
a3348722 BW |
5437 | |
5438 | /* send Q update ramrod for FCoE Q */ | |
5439 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
5440 | if (rc < 0) | |
5441 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
5442 | q); | |
5443 | } else { | |
5444 | /* If no FCoE ring - ACK MCP now */ | |
5445 | bnx2x_link_report(bp); | |
5446 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5447 | } | |
a3348722 BW |
5448 | } |
5449 | ||
1191cb83 | 5450 | static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( |
619c5cb6 VZ |
5451 | struct bnx2x *bp, u32 cid) |
5452 | { | |
94f05b0f | 5453 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
55c11941 MS |
5454 | |
5455 | if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) | |
15192a8c | 5456 | return &bnx2x_fcoe_sp_obj(bp, q_obj); |
619c5cb6 | 5457 | else |
15192a8c | 5458 | return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; |
619c5cb6 VZ |
5459 | } |
5460 | ||
523224a3 DK |
5461 | static void bnx2x_eq_int(struct bnx2x *bp) |
5462 | { | |
5463 | u16 hw_cons, sw_cons, sw_prod; | |
5464 | union event_ring_elem *elem; | |
55c11941 | 5465 | u8 echo; |
523224a3 DK |
5466 | u32 cid; |
5467 | u8 opcode; | |
fd1fc79d | 5468 | int rc, spqe_cnt = 0; |
619c5cb6 VZ |
5469 | struct bnx2x_queue_sp_obj *q_obj; |
5470 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
5471 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
5472 | |
5473 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
5474 | ||
5475 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
16a5fd92 | 5476 | * when we get the next-page we need to adjust so the loop |
523224a3 DK |
5477 | * condition below will be met. The next element is the size of a |
5478 | * regular element and hence incrementing by 1 | |
5479 | */ | |
5480 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
5481 | hw_cons++; | |
5482 | ||
25985edc | 5483 | /* This function may never run in parallel with itself for a |
523224a3 DK |
5484 | * specific bp, thus there is no need in "paired" read memory |
5485 | * barrier here. | |
5486 | */ | |
5487 | sw_cons = bp->eq_cons; | |
5488 | sw_prod = bp->eq_prod; | |
5489 | ||
d6cae238 | 5490 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 5491 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
5492 | |
5493 | for (; sw_cons != hw_cons; | |
5494 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
5495 | ||
523224a3 DK |
5496 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; |
5497 | ||
fd1fc79d AE |
5498 | rc = bnx2x_iov_eq_sp_event(bp, elem); |
5499 | if (!rc) { | |
5500 | DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", | |
5501 | rc); | |
5502 | goto next_spqe; | |
5503 | } | |
523224a3 | 5504 | |
86564c3f | 5505 | opcode = elem->message.opcode; |
523224a3 DK |
5506 | |
5507 | /* handle eq element */ | |
5508 | switch (opcode) { | |
fd1fc79d | 5509 | case EVENT_RING_OPCODE_VF_PF_CHANNEL: |
370d4a26 YM |
5510 | bnx2x_vf_mbx_schedule(bp, |
5511 | &elem->message.data.vf_pf_event); | |
fd1fc79d AE |
5512 | continue; |
5513 | ||
523224a3 | 5514 | case EVENT_RING_OPCODE_STAT_QUERY: |
76ca70fa YM |
5515 | DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS), |
5516 | "got statistics comp event %d\n", | |
5517 | bp->stats_comp++); | |
523224a3 | 5518 | /* nothing to do with stats comp */ |
d6cae238 | 5519 | goto next_spqe; |
523224a3 DK |
5520 | |
5521 | case EVENT_RING_OPCODE_CFC_DEL: | |
5522 | /* handle according to cid range */ | |
5523 | /* | |
5524 | * we may want to verify here that the bp state is | |
5525 | * HALTING | |
5526 | */ | |
ca4f2d50 MS |
5527 | |
5528 | /* elem CID originates from FW; actually LE */ | |
da472731 | 5529 | cid = SW_CID(elem->message.data.cfc_del_event.cid); |
ca4f2d50 | 5530 | |
d6cae238 | 5531 | DP(BNX2X_MSG_SP, |
523224a3 | 5532 | "got delete ramrod for MULTI[%d]\n", cid); |
55c11941 MS |
5533 | |
5534 | if (CNIC_LOADED(bp) && | |
5535 | !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
523224a3 | 5536 | goto next_spqe; |
55c11941 | 5537 | |
619c5cb6 VZ |
5538 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
5539 | ||
5540 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
5541 | break; | |
5542 | ||
523224a3 | 5543 | goto next_spqe; |
e4901dde VZ |
5544 | |
5545 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
51c1a580 | 5546 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
6ffa39f2 | 5547 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
6debea87 DK |
5548 | if (f_obj->complete_cmd(bp, f_obj, |
5549 | BNX2X_F_CMD_TX_STOP)) | |
5550 | break; | |
e4901dde | 5551 | goto next_spqe; |
619c5cb6 | 5552 | |
e4901dde | 5553 | case EVENT_RING_OPCODE_START_TRAFFIC: |
51c1a580 | 5554 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
6ffa39f2 | 5555 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
6debea87 DK |
5556 | if (f_obj->complete_cmd(bp, f_obj, |
5557 | BNX2X_F_CMD_TX_START)) | |
5558 | break; | |
e4901dde | 5559 | goto next_spqe; |
55c11941 | 5560 | |
a3348722 | 5561 | case EVENT_RING_OPCODE_FUNCTION_UPDATE: |
55c11941 MS |
5562 | echo = elem->message.data.function_update_event.echo; |
5563 | if (echo == SWITCH_UPDATE) { | |
5564 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, | |
5565 | "got FUNC_SWITCH_UPDATE ramrod\n"); | |
5566 | if (f_obj->complete_cmd( | |
5567 | bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) | |
5568 | break; | |
a3348722 | 5569 | |
55c11941 | 5570 | } else { |
230bb0f3 YM |
5571 | int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE; |
5572 | ||
55c11941 MS |
5573 | DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, |
5574 | "AFEX: ramrod completed FUNCTION_UPDATE\n"); | |
5575 | f_obj->complete_cmd(bp, f_obj, | |
5576 | BNX2X_F_CMD_AFEX_UPDATE); | |
5577 | ||
5578 | /* We will perform the Queues update from | |
5579 | * sp_rtnl task as all Queue SP operations | |
5580 | * should run under rtnl_lock. | |
5581 | */ | |
230bb0f3 | 5582 | bnx2x_schedule_sp_rtnl(bp, cmd, 0); |
55c11941 | 5583 | } |
a3348722 | 5584 | |
a3348722 BW |
5585 | goto next_spqe; |
5586 | ||
5587 | case EVENT_RING_OPCODE_AFEX_VIF_LISTS: | |
5588 | f_obj->complete_cmd(bp, f_obj, | |
5589 | BNX2X_F_CMD_AFEX_VIFLISTS); | |
5590 | bnx2x_after_afex_vif_lists(bp, elem); | |
5591 | goto next_spqe; | |
619c5cb6 | 5592 | case EVENT_RING_OPCODE_FUNCTION_START: |
51c1a580 MS |
5593 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5594 | "got FUNC_START ramrod\n"); | |
619c5cb6 VZ |
5595 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
5596 | break; | |
5597 | ||
5598 | goto next_spqe; | |
5599 | ||
5600 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
51c1a580 MS |
5601 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5602 | "got FUNC_STOP ramrod\n"); | |
619c5cb6 VZ |
5603 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
5604 | break; | |
5605 | ||
5606 | goto next_spqe; | |
eeed018c MK |
5607 | |
5608 | case EVENT_RING_OPCODE_SET_TIMESYNC: | |
5609 | DP(BNX2X_MSG_SP | BNX2X_MSG_PTP, | |
5610 | "got set_timesync ramrod completion\n"); | |
5611 | if (f_obj->complete_cmd(bp, f_obj, | |
5612 | BNX2X_F_CMD_SET_TIMESYNC)) | |
5613 | break; | |
5614 | goto next_spqe; | |
523224a3 DK |
5615 | } |
5616 | ||
5617 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
5618 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
5619 | BNX2X_STATE_OPEN): | |
5620 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 5621 | BNX2X_STATE_OPENING_WAIT4_PORT): |
28311f8e YM |
5622 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
5623 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5624 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
9cd753a1 | 5625 | SW_CID(elem->message.data.eth_event.echo)); |
619c5cb6 | 5626 | rss_raw->clear_pending(rss_raw); |
523224a3 DK |
5627 | break; |
5628 | ||
619c5cb6 VZ |
5629 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
5630 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
5631 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 5632 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
5633 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
5634 | BNX2X_STATE_OPEN): | |
5635 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5636 | BNX2X_STATE_DIAG): | |
5637 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5638 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
05cc5a39 | 5639 | DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n"); |
619c5cb6 | 5640 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
5641 | break; |
5642 | ||
619c5cb6 VZ |
5643 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
5644 | BNX2X_STATE_OPEN): | |
5645 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5646 | BNX2X_STATE_DIAG): | |
5647 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5648 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5649 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 5650 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
5651 | break; |
5652 | ||
619c5cb6 VZ |
5653 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
5654 | BNX2X_STATE_OPEN): | |
5655 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
5656 | BNX2X_STATE_DIAG): | |
5657 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 5658 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 5659 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 5660 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
5661 | break; |
5662 | default: | |
5663 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
5664 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
5665 | elem->message.opcode, bp->state); | |
523224a3 DK |
5666 | } |
5667 | next_spqe: | |
5668 | spqe_cnt++; | |
5669 | } /* for */ | |
5670 | ||
4e857c58 | 5671 | smp_mb__before_atomic(); |
6e30dd4e | 5672 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
5673 | |
5674 | bp->eq_cons = sw_cons; | |
5675 | bp->eq_prod = sw_prod; | |
5676 | /* Make sure that above mem writes were issued towards the memory */ | |
5677 | smp_wmb(); | |
5678 | ||
5679 | /* update producer */ | |
5680 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
5681 | } | |
5682 | ||
a2fbb9ea ET |
5683 | static void bnx2x_sp_task(struct work_struct *work) |
5684 | { | |
1cf167f2 | 5685 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea | 5686 | |
fd1fc79d | 5687 | DP(BNX2X_MSG_SP, "sp task invoked\n"); |
a2fbb9ea | 5688 | |
16a5fd92 | 5689 | /* make sure the atomic interrupt_occurred has been written */ |
fd1fc79d AE |
5690 | smp_rmb(); |
5691 | if (atomic_read(&bp->interrupt_occurred)) { | |
a2fbb9ea | 5692 | |
fd1fc79d AE |
5693 | /* what work needs to be performed? */ |
5694 | u16 status = bnx2x_update_dsb_idx(bp); | |
cdaa7cb8 | 5695 | |
fd1fc79d AE |
5696 | DP(BNX2X_MSG_SP, "status %x\n", status); |
5697 | DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); | |
5698 | atomic_set(&bp->interrupt_occurred, 0); | |
5699 | ||
5700 | /* HW attentions */ | |
5701 | if (status & BNX2X_DEF_SB_ATT_IDX) { | |
5702 | bnx2x_attn_int(bp); | |
5703 | status &= ~BNX2X_DEF_SB_ATT_IDX; | |
5704 | } | |
5705 | ||
5706 | /* SP events: STAT_QUERY and others */ | |
5707 | if (status & BNX2X_DEF_SB_IDX) { | |
5708 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 5709 | |
7e88009b | 5710 | if (FCOE_INIT(bp) && |
fd1fc79d AE |
5711 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
5712 | /* Prevent local bottom-halves from running as | |
5713 | * we are going to change the local NAPI list. | |
5714 | */ | |
5715 | local_bh_disable(); | |
5716 | napi_schedule(&bnx2x_fcoe(bp, napi)); | |
5717 | local_bh_enable(); | |
5718 | } | |
5719 | ||
5720 | /* Handle EQ completions */ | |
5721 | bnx2x_eq_int(bp); | |
5722 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
5723 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
5724 | ||
5725 | status &= ~BNX2X_DEF_SB_IDX; | |
019dbb4c | 5726 | } |
55c11941 | 5727 | |
fd1fc79d AE |
5728 | /* if status is non zero then perhaps something went wrong */ |
5729 | if (unlikely(status)) | |
5730 | DP(BNX2X_MSG_SP, | |
5731 | "got an unknown interrupt! (status 0x%x)\n", status); | |
523224a3 | 5732 | |
fd1fc79d AE |
5733 | /* ack status block only if something was actually handled */ |
5734 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, | |
5735 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
cdaa7cb8 VZ |
5736 | } |
5737 | ||
a3348722 BW |
5738 | /* afex - poll to check if VIFSET_ACK should be sent to MFW */ |
5739 | if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, | |
5740 | &bp->sp_state)) { | |
5741 | bnx2x_link_report(bp); | |
5742 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5743 | } | |
a2fbb9ea ET |
5744 | } |
5745 | ||
9f6c9258 | 5746 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
5747 | { |
5748 | struct net_device *dev = dev_instance; | |
5749 | struct bnx2x *bp = netdev_priv(dev); | |
5750 | ||
523224a3 DK |
5751 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
5752 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
5753 | |
5754 | #ifdef BNX2X_STOP_ON_ERROR | |
5755 | if (unlikely(bp->panic)) | |
5756 | return IRQ_HANDLED; | |
5757 | #endif | |
5758 | ||
55c11941 | 5759 | if (CNIC_LOADED(bp)) { |
993ac7b5 MC |
5760 | struct cnic_ops *c_ops; |
5761 | ||
5762 | rcu_read_lock(); | |
5763 | c_ops = rcu_dereference(bp->cnic_ops); | |
5764 | if (c_ops) | |
5765 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
5766 | rcu_read_unlock(); | |
5767 | } | |
55c11941 | 5768 | |
fd1fc79d AE |
5769 | /* schedule sp task to perform default status block work, ack |
5770 | * attentions and enable interrupts. | |
5771 | */ | |
5772 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
5773 | |
5774 | return IRQ_HANDLED; | |
5775 | } | |
5776 | ||
5777 | /* end of slow path */ | |
5778 | ||
619c5cb6 VZ |
5779 | void bnx2x_drv_pulse(struct bnx2x *bp) |
5780 | { | |
5781 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
5782 | bp->fw_drv_pulse_wr_seq); | |
5783 | } | |
5784 | ||
e99e88a9 | 5785 | static void bnx2x_timer(struct timer_list *t) |
a2fbb9ea | 5786 | { |
e99e88a9 | 5787 | struct bnx2x *bp = from_timer(bp, t, timer); |
a2fbb9ea ET |
5788 | |
5789 | if (!netif_running(bp->dev)) | |
5790 | return; | |
5791 | ||
67c431a5 AE |
5792 | if (IS_PF(bp) && |
5793 | !BP_NOMCP(bp)) { | |
f2e0899f | 5794 | int mb_idx = BP_FW_MB_IDX(bp); |
4c868664 EG |
5795 | u16 drv_pulse; |
5796 | u16 mcp_pulse; | |
a2fbb9ea ET |
5797 | |
5798 | ++bp->fw_drv_pulse_wr_seq; | |
5799 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
a2fbb9ea | 5800 | drv_pulse = bp->fw_drv_pulse_wr_seq; |
619c5cb6 | 5801 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 5802 | |
f2e0899f | 5803 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
5804 | MCP_PULSE_SEQ_MASK); |
5805 | /* The delta between driver pulse and mcp response | |
4c868664 EG |
5806 | * should not get too big. If the MFW is more than 5 pulses |
5807 | * behind, we should worry about it enough to generate an error | |
5808 | * log. | |
a2fbb9ea | 5809 | */ |
4c868664 EG |
5810 | if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5) |
5811 | BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
a2fbb9ea | 5812 | drv_pulse, mcp_pulse); |
a2fbb9ea ET |
5813 | } |
5814 | ||
f34d28ea | 5815 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 5816 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 5817 | |
abc5a021 | 5818 | /* sample pf vf bulletin board for new posts from pf */ |
37173488 YM |
5819 | if (IS_VF(bp)) |
5820 | bnx2x_timer_sriov(bp); | |
78c3bcc5 | 5821 | |
a2fbb9ea ET |
5822 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
5823 | } | |
5824 | ||
5825 | /* end of Statistics */ | |
5826 | ||
5827 | /* nic init */ | |
5828 | ||
5829 | /* | |
5830 | * nic init service functions | |
5831 | */ | |
5832 | ||
1191cb83 | 5833 | static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 5834 | { |
523224a3 DK |
5835 | u32 i; |
5836 | if (!(len%4) && !(addr%4)) | |
5837 | for (i = 0; i < len; i += 4) | |
5838 | REG_WR(bp, addr + i, fill); | |
5839 | else | |
5840 | for (i = 0; i < len; i++) | |
5841 | REG_WR8(bp, addr + i, fill); | |
34f80b04 EG |
5842 | } |
5843 | ||
523224a3 | 5844 | /* helper: writes FP SP data to FW - data_size in dwords */ |
1191cb83 ED |
5845 | static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, |
5846 | int fw_sb_id, | |
5847 | u32 *sb_data_p, | |
5848 | u32 data_size) | |
34f80b04 | 5849 | { |
a2fbb9ea | 5850 | int index; |
523224a3 DK |
5851 | for (index = 0; index < data_size; index++) |
5852 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5853 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
5854 | sizeof(u32)*index, | |
5855 | *(sb_data_p + index)); | |
5856 | } | |
a2fbb9ea | 5857 | |
1191cb83 | 5858 | static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
523224a3 DK |
5859 | { |
5860 | u32 *sb_data_p; | |
5861 | u32 data_size = 0; | |
f2e0899f | 5862 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 5863 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 5864 | |
523224a3 | 5865 | /* disable the function first */ |
619c5cb6 | 5866 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5867 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5868 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
5869 | sb_data_e2.common.p_func.vf_valid = false; |
5870 | sb_data_p = (u32 *)&sb_data_e2; | |
5871 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
5872 | } else { | |
5873 | memset(&sb_data_e1x, 0, | |
5874 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5875 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
5876 | sb_data_e1x.common.p_func.vf_valid = false; |
5877 | sb_data_p = (u32 *)&sb_data_e1x; | |
5878 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
5879 | } | |
523224a3 | 5880 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 5881 | |
523224a3 DK |
5882 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
5883 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
5884 | CSTORM_STATUS_BLOCK_SIZE); | |
5885 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5886 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
5887 | CSTORM_SYNC_BLOCK_SIZE); | |
5888 | } | |
34f80b04 | 5889 | |
523224a3 | 5890 | /* helper: writes SP SB data to FW */ |
1191cb83 | 5891 | static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, |
523224a3 DK |
5892 | struct hc_sp_status_block_data *sp_sb_data) |
5893 | { | |
5894 | int func = BP_FUNC(bp); | |
5895 | int i; | |
5896 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
5897 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5898 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
5899 | i*sizeof(u32), | |
5900 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
5901 | } |
5902 | ||
1191cb83 | 5903 | static void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
5904 | { |
5905 | int func = BP_FUNC(bp); | |
523224a3 DK |
5906 | struct hc_sp_status_block_data sp_sb_data; |
5907 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 5908 | |
619c5cb6 | 5909 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
5910 | sp_sb_data.p_func.vf_valid = false; |
5911 | ||
5912 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
5913 | ||
5914 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5915 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
5916 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
5917 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5918 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
5919 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
523224a3 DK |
5920 | } |
5921 | ||
1191cb83 | 5922 | static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, |
523224a3 DK |
5923 | int igu_sb_id, int igu_seg_id) |
5924 | { | |
5925 | hc_sm->igu_sb_id = igu_sb_id; | |
5926 | hc_sm->igu_seg_id = igu_seg_id; | |
5927 | hc_sm->timer_value = 0xFF; | |
5928 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
5929 | } |
5930 | ||
150966ad | 5931 | /* allocates state machine ids. */ |
1191cb83 | 5932 | static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) |
150966ad AE |
5933 | { |
5934 | /* zero out state machine indices */ | |
5935 | /* rx indices */ | |
5936 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5937 | ||
5938 | /* tx indices */ | |
5939 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5940 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
5941 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
5942 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
5943 | ||
5944 | /* map indices */ | |
5945 | /* rx indices */ | |
5946 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
5947 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5948 | ||
5949 | /* tx indices */ | |
5950 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
5951 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5952 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
5953 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5954 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
5955 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5956 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
5957 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5958 | } | |
5959 | ||
b93288d5 | 5960 | void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 5961 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 5962 | { |
523224a3 DK |
5963 | int igu_seg_id; |
5964 | ||
f2e0899f | 5965 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
5966 | struct hc_status_block_data_e1x sb_data_e1x; |
5967 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
5968 | int data_size; |
5969 | u32 *sb_data_p; | |
5970 | ||
f2e0899f DK |
5971 | if (CHIP_INT_MODE_IS_BC(bp)) |
5972 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
5973 | else | |
5974 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
5975 | |
5976 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
5977 | ||
619c5cb6 | 5978 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5979 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5980 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
5981 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
5982 | sb_data_e2.common.p_func.vf_id = vfid; | |
5983 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
5984 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
5985 | sb_data_e2.common.same_igu_sb_1b = true; | |
5986 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
5987 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
5988 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
5989 | sb_data_p = (u32 *)&sb_data_e2; |
5990 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 5991 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
5992 | } else { |
5993 | memset(&sb_data_e1x, 0, | |
5994 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5995 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
5996 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
5997 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
5998 | sb_data_e1x.common.p_func.vf_valid = false; | |
5999 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
6000 | sb_data_e1x.common.same_igu_sb_1b = true; | |
6001 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
6002 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
6003 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
6004 | sb_data_p = (u32 *)&sb_data_e1x; |
6005 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 6006 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 6007 | } |
523224a3 DK |
6008 | |
6009 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
6010 | igu_sb_id, igu_seg_id); | |
6011 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
6012 | igu_sb_id, igu_seg_id); | |
6013 | ||
51c1a580 | 6014 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
523224a3 | 6015 | |
86564c3f | 6016 | /* write indices to HW - PCI guarantees endianity of regpairs */ |
523224a3 DK |
6017 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
6018 | } | |
6019 | ||
619c5cb6 | 6020 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
6021 | u16 tx_usec, u16 rx_usec) |
6022 | { | |
6383c0b3 | 6023 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 6024 | false, rx_usec); |
6383c0b3 AE |
6025 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
6026 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
6027 | tx_usec); | |
6028 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
6029 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
6030 | tx_usec); | |
6031 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
6032 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
6033 | tx_usec); | |
523224a3 | 6034 | } |
f2e0899f | 6035 | |
523224a3 DK |
6036 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
6037 | { | |
6038 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
6039 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
6040 | int igu_sp_sb_index; | |
6041 | int igu_seg_id; | |
34f80b04 EG |
6042 | int port = BP_PORT(bp); |
6043 | int func = BP_FUNC(bp); | |
f2eaeb58 | 6044 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 6045 | u64 section; |
523224a3 DK |
6046 | int index; |
6047 | struct hc_sp_status_block_data sp_sb_data; | |
6048 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
6049 | ||
f2e0899f DK |
6050 | if (CHIP_INT_MODE_IS_BC(bp)) { |
6051 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
6052 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
6053 | } else { | |
6054 | igu_sp_sb_index = bp->igu_dsb_id; | |
6055 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
6056 | } | |
a2fbb9ea ET |
6057 | |
6058 | /* ATTN */ | |
523224a3 | 6059 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 6060 | atten_status_block); |
523224a3 | 6061 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 6062 | |
49d66772 ET |
6063 | bp->attn_state = 0; |
6064 | ||
a2fbb9ea ET |
6065 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
6066 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
6067 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
6068 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 6069 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
6070 | int sindex; |
6071 | /* take care of sig[0]..sig[4] */ | |
6072 | for (sindex = 0; sindex < 4; sindex++) | |
6073 | bp->attn_group[index].sig[sindex] = | |
6074 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 6075 | |
619c5cb6 | 6076 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6077 | /* |
6078 | * enable5 is separate from the rest of the registers, | |
6079 | * and therefore the address skip is 4 | |
6080 | * and not 16 between the different groups | |
6081 | */ | |
6082 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 6083 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
6084 | else |
6085 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
6086 | } |
6087 | ||
f2e0899f DK |
6088 | if (bp->common.int_block == INT_BLOCK_HC) { |
6089 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
6090 | HC_REG_ATTN_MSG0_ADDR_L); | |
6091 | ||
6092 | REG_WR(bp, reg_offset, U64_LO(section)); | |
6093 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 6094 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6095 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
6096 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
6097 | } | |
a2fbb9ea | 6098 | |
523224a3 DK |
6099 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
6100 | sp_sb); | |
a2fbb9ea | 6101 | |
523224a3 | 6102 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 6103 | |
86564c3f | 6104 | /* PCI guarantees endianity of regpairs */ |
619c5cb6 | 6105 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
6106 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
6107 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
6108 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
6109 | sp_sb_data.igu_seg_id = igu_seg_id; | |
6110 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 6111 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 6112 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 6113 | |
523224a3 | 6114 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 6115 | |
523224a3 | 6116 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
6117 | } |
6118 | ||
9f6c9258 | 6119 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 6120 | { |
a2fbb9ea ET |
6121 | int i; |
6122 | ||
ec6ba945 | 6123 | for_each_eth_queue(bp, i) |
523224a3 | 6124 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 6125 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
6126 | } |
6127 | ||
a2fbb9ea ET |
6128 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
6129 | { | |
a2fbb9ea | 6130 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 6131 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 6132 | |
a2fbb9ea | 6133 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
6134 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
6135 | bp->spq_prod_bd = bp->spq; | |
6136 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
6137 | } |
6138 | ||
523224a3 | 6139 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
6140 | { |
6141 | int i; | |
523224a3 DK |
6142 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
6143 | union event_ring_elem *elem = | |
6144 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 6145 | |
523224a3 DK |
6146 | elem->next_page.addr.hi = |
6147 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
6148 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
6149 | elem->next_page.addr.lo = | |
6150 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
6151 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 6152 | } |
523224a3 DK |
6153 | bp->eq_cons = 0; |
6154 | bp->eq_prod = NUM_EQ_DESC; | |
6155 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
16a5fd92 | 6156 | /* we want a warning message before it gets wrought... */ |
6e30dd4e VZ |
6157 | atomic_set(&bp->eq_spq_left, |
6158 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
6159 | } |
6160 | ||
619c5cb6 | 6161 | /* called with netif_addr_lock_bh() */ |
a8f47eb7 | 6162 | static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
6163 | unsigned long rx_mode_flags, | |
6164 | unsigned long rx_accept_flags, | |
6165 | unsigned long tx_accept_flags, | |
6166 | unsigned long ramrod_flags) | |
ab532cf3 | 6167 | { |
619c5cb6 VZ |
6168 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
6169 | int rc; | |
6170 | ||
6171 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
6172 | ||
6173 | /* Prepare ramrod parameters */ | |
6174 | ramrod_param.cid = 0; | |
6175 | ramrod_param.cl_id = cl_id; | |
6176 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
6177 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 6178 | |
619c5cb6 VZ |
6179 | ramrod_param.pstate = &bp->sp_state; |
6180 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 6181 | |
619c5cb6 VZ |
6182 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
6183 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
6184 | ||
6185 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
6186 | ||
6187 | ramrod_param.ramrod_flags = ramrod_flags; | |
6188 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
6189 | ||
6190 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
6191 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
6192 | ||
6193 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
6194 | if (rc < 0) { | |
6195 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
924d75ab | 6196 | return rc; |
619c5cb6 | 6197 | } |
924d75ab YM |
6198 | |
6199 | return 0; | |
a2fbb9ea ET |
6200 | } |
6201 | ||
86564c3f YM |
6202 | static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, |
6203 | unsigned long *rx_accept_flags, | |
6204 | unsigned long *tx_accept_flags) | |
471de716 | 6205 | { |
924d75ab YM |
6206 | /* Clear the flags first */ |
6207 | *rx_accept_flags = 0; | |
6208 | *tx_accept_flags = 0; | |
619c5cb6 | 6209 | |
924d75ab | 6210 | switch (rx_mode) { |
619c5cb6 VZ |
6211 | case BNX2X_RX_MODE_NONE: |
6212 | /* | |
6213 | * 'drop all' supersedes any accept flags that may have been | |
6214 | * passed to the function. | |
6215 | */ | |
6216 | break; | |
6217 | case BNX2X_RX_MODE_NORMAL: | |
924d75ab YM |
6218 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
6219 | __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags); | |
6220 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
6221 | |
6222 | /* internal switching mode */ | |
924d75ab YM |
6223 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
6224 | __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags); | |
6225 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 | 6226 | |
05cc5a39 YM |
6227 | if (bp->accept_any_vlan) { |
6228 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); | |
6229 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); | |
6230 | } | |
6231 | ||
619c5cb6 VZ |
6232 | break; |
6233 | case BNX2X_RX_MODE_ALLMULTI: | |
924d75ab YM |
6234 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
6235 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); | |
6236 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
6237 | |
6238 | /* internal switching mode */ | |
924d75ab YM |
6239 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
6240 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); | |
6241 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 | 6242 | |
05cc5a39 YM |
6243 | if (bp->accept_any_vlan) { |
6244 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); | |
6245 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); | |
6246 | } | |
6247 | ||
619c5cb6 VZ |
6248 | break; |
6249 | case BNX2X_RX_MODE_PROMISC: | |
16a5fd92 | 6250 | /* According to definition of SI mode, iface in promisc mode |
619c5cb6 VZ |
6251 | * should receive matched and unmatched (in resolution of port) |
6252 | * unicast packets. | |
6253 | */ | |
924d75ab YM |
6254 | __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags); |
6255 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); | |
6256 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); | |
6257 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
6258 | |
6259 | /* internal switching mode */ | |
924d75ab YM |
6260 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); |
6261 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 VZ |
6262 | |
6263 | if (IS_MF_SI(bp)) | |
924d75ab | 6264 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags); |
619c5cb6 | 6265 | else |
924d75ab | 6266 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
619c5cb6 | 6267 | |
05cc5a39 YM |
6268 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); |
6269 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); | |
6270 | ||
619c5cb6 VZ |
6271 | break; |
6272 | default: | |
924d75ab YM |
6273 | BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode); |
6274 | return -EINVAL; | |
619c5cb6 | 6275 | } |
de832a55 | 6276 | |
924d75ab YM |
6277 | return 0; |
6278 | } | |
6279 | ||
6280 | /* called with netif_addr_lock_bh() */ | |
a8f47eb7 | 6281 | static int bnx2x_set_storm_rx_mode(struct bnx2x *bp) |
924d75ab YM |
6282 | { |
6283 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; | |
6284 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
6285 | int rc; | |
6286 | ||
6287 | if (!NO_FCOE(bp)) | |
6288 | /* Configure rx_mode of FCoE Queue */ | |
6289 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
6290 | ||
6291 | rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, | |
6292 | &tx_accept_flags); | |
6293 | if (rc) | |
6294 | return rc; | |
6295 | ||
619c5cb6 VZ |
6296 | __set_bit(RAMROD_RX, &ramrod_flags); |
6297 | __set_bit(RAMROD_TX, &ramrod_flags); | |
6298 | ||
924d75ab YM |
6299 | return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, |
6300 | rx_accept_flags, tx_accept_flags, | |
6301 | ramrod_flags); | |
619c5cb6 VZ |
6302 | } |
6303 | ||
6304 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
6305 | { | |
6306 | int i; | |
6307 | ||
523224a3 DK |
6308 | /* Zero this manually as its initialization is |
6309 | currently missing in the initTool */ | |
6310 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 6311 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 6312 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 6313 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6314 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
6315 | CHIP_INT_MODE_IS_BC(bp) ? | |
6316 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
6317 | } | |
523224a3 | 6318 | } |
8a1c38d1 | 6319 | |
471de716 EG |
6320 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
6321 | { | |
6322 | switch (load_code) { | |
6323 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 6324 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 | 6325 | bnx2x_init_internal_common(bp); |
93e6664e | 6326 | fallthrough; |
471de716 EG |
6327 | |
6328 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 6329 | /* nothing to do */ |
93e6664e | 6330 | fallthrough; |
471de716 EG |
6331 | |
6332 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
6333 | /* internal memory per function is |
6334 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
6335 | break; |
6336 | ||
6337 | default: | |
6338 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
6339 | break; | |
6340 | } | |
6341 | } | |
6342 | ||
619c5cb6 | 6343 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 6344 | { |
55c11941 | 6345 | return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 | 6346 | } |
523224a3 | 6347 | |
619c5cb6 VZ |
6348 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
6349 | { | |
55c11941 | 6350 | return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 VZ |
6351 | } |
6352 | ||
1191cb83 | 6353 | static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) |
619c5cb6 VZ |
6354 | { |
6355 | if (CHIP_IS_E1x(fp->bp)) | |
6356 | return BP_L_ID(fp->bp) + fp->index; | |
6357 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
6358 | return bnx2x_fp_igu_sb_id(fp); | |
6359 | } | |
6360 | ||
6383c0b3 | 6361 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
6362 | { |
6363 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 6364 | u8 cos; |
619c5cb6 | 6365 | unsigned long q_type = 0; |
6383c0b3 | 6366 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 6367 | fp->rx_queue = fp_idx; |
b3b83c3f | 6368 | fp->cid = fp_idx; |
619c5cb6 VZ |
6369 | fp->cl_id = bnx2x_fp_cl_id(fp); |
6370 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
6371 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 6372 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
6373 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
6374 | ||
523224a3 | 6375 | /* init shortcut */ |
619c5cb6 | 6376 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
7a752993 | 6377 | |
16a5fd92 | 6378 | /* Setup SB indices */ |
523224a3 | 6379 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; |
523224a3 | 6380 | |
619c5cb6 VZ |
6381 | /* Configure Queue State object */ |
6382 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
6383 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
6384 | |
6385 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
6386 | ||
6387 | /* init tx data */ | |
6388 | for_each_cos_in_tx_queue(fp, cos) { | |
65565884 MS |
6389 | bnx2x_init_txdata(bp, fp->txdata_ptr[cos], |
6390 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), | |
6391 | FP_COS_TO_TXQ(fp, cos, bp), | |
6392 | BNX2X_TX_SB_INDEX_BASE + cos, fp); | |
6393 | cids[cos] = fp->txdata_ptr[cos]->cid; | |
6383c0b3 AE |
6394 | } |
6395 | ||
ad5afc89 AE |
6396 | /* nothing more for vf to do here */ |
6397 | if (IS_VF(bp)) | |
6398 | return; | |
6399 | ||
6400 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
6401 | fp->fw_sb_id, fp->igu_sb_id); | |
6402 | bnx2x_update_fpsb_idx(fp); | |
15192a8c BW |
6403 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, |
6404 | fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 6405 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 VZ |
6406 | |
6407 | /** | |
6408 | * Configure classification DBs: Always enable Tx switching | |
6409 | */ | |
6410 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
6411 | ||
ad5afc89 AE |
6412 | DP(NETIF_MSG_IFUP, |
6413 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
6414 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
6415 | fp->igu_sb_id); | |
523224a3 DK |
6416 | } |
6417 | ||
1191cb83 ED |
6418 | static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) |
6419 | { | |
6420 | int i; | |
6421 | ||
6422 | for (i = 1; i <= NUM_TX_RINGS; i++) { | |
6423 | struct eth_tx_next_bd *tx_next_bd = | |
6424 | &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
6425 | ||
6426 | tx_next_bd->addr_hi = | |
6427 | cpu_to_le32(U64_HI(txdata->tx_desc_mapping + | |
6428 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
6429 | tx_next_bd->addr_lo = | |
6430 | cpu_to_le32(U64_LO(txdata->tx_desc_mapping + | |
6431 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
6432 | } | |
6433 | ||
639d65b8 YM |
6434 | *txdata->tx_cons_sb = cpu_to_le16(0); |
6435 | ||
1191cb83 ED |
6436 | SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); |
6437 | txdata->tx_db.data.zero_fill1 = 0; | |
6438 | txdata->tx_db.data.prod = 0; | |
6439 | ||
6440 | txdata->tx_pkt_prod = 0; | |
6441 | txdata->tx_pkt_cons = 0; | |
6442 | txdata->tx_bd_prod = 0; | |
6443 | txdata->tx_bd_cons = 0; | |
6444 | txdata->tx_pkt = 0; | |
6445 | } | |
6446 | ||
55c11941 MS |
6447 | static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) |
6448 | { | |
6449 | int i; | |
6450 | ||
6451 | for_each_tx_queue_cnic(bp, i) | |
6452 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); | |
6453 | } | |
d76a6111 | 6454 | |
1191cb83 ED |
6455 | static void bnx2x_init_tx_rings(struct bnx2x *bp) |
6456 | { | |
6457 | int i; | |
6458 | u8 cos; | |
6459 | ||
55c11941 | 6460 | for_each_eth_queue(bp, i) |
1191cb83 | 6461 | for_each_cos_in_tx_queue(&bp->fp[i], cos) |
65565884 | 6462 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); |
1191cb83 ED |
6463 | } |
6464 | ||
a8f47eb7 | 6465 | static void bnx2x_init_fcoe_fp(struct bnx2x *bp) |
6466 | { | |
6467 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
6468 | unsigned long q_type = 0; | |
6469 | ||
6470 | bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); | |
6471 | bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, | |
6472 | BNX2X_FCOE_ETH_CL_ID_IDX); | |
6473 | bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); | |
6474 | bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; | |
6475 | bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; | |
6476 | bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; | |
6477 | bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), | |
6478 | fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, | |
6479 | fp); | |
6480 | ||
6481 | DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); | |
6482 | ||
6483 | /* qZone id equals to FW (per path) client id */ | |
6484 | bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); | |
6485 | /* init shortcut */ | |
6486 | bnx2x_fcoe(bp, ustorm_rx_prods_offset) = | |
6487 | bnx2x_rx_ustorm_prods_offset(fp); | |
6488 | ||
6489 | /* Configure Queue State object */ | |
6490 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
6491 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6492 | ||
6493 | /* No multi-CoS for FCoE L2 client */ | |
6494 | BUG_ON(fp->max_cos != 1); | |
6495 | ||
6496 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, | |
6497 | &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6498 | bnx2x_sp_mapping(bp, q_rdata), q_type); | |
6499 | ||
6500 | DP(NETIF_MSG_IFUP, | |
6501 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
6502 | fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
6503 | fp->igu_sb_id); | |
6504 | } | |
6505 | ||
55c11941 | 6506 | void bnx2x_nic_init_cnic(struct bnx2x *bp) |
a2fbb9ea | 6507 | { |
ec6ba945 VZ |
6508 | if (!NO_FCOE(bp)) |
6509 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
6510 | |
6511 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
6512 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 6513 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 6514 | |
55c11941 MS |
6515 | /* ensure status block indices were read */ |
6516 | rmb(); | |
6517 | bnx2x_init_rx_rings_cnic(bp); | |
6518 | bnx2x_init_tx_rings_cnic(bp); | |
6519 | ||
6520 | /* flush all */ | |
6521 | mb(); | |
55c11941 | 6522 | } |
a2fbb9ea | 6523 | |
ecf01c22 | 6524 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp) |
55c11941 MS |
6525 | { |
6526 | int i; | |
6527 | ||
ecf01c22 | 6528 | /* Setup NIC internals and enable interrupts */ |
55c11941 MS |
6529 | for_each_eth_queue(bp, i) |
6530 | bnx2x_init_eth_fp(bp, i); | |
ad5afc89 AE |
6531 | |
6532 | /* ensure status block indices were read */ | |
6533 | rmb(); | |
6534 | bnx2x_init_rx_rings(bp); | |
6535 | bnx2x_init_tx_rings(bp); | |
6536 | ||
ecf01c22 YM |
6537 | if (IS_PF(bp)) { |
6538 | /* Initialize MOD_ABS interrupts */ | |
6539 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
6540 | bp->common.shmem_base, | |
6541 | bp->common.shmem2_base, BP_PORT(bp)); | |
ad5afc89 | 6542 | |
ecf01c22 YM |
6543 | /* initialize the default status block and sp ring */ |
6544 | bnx2x_init_def_sb(bp); | |
6545 | bnx2x_update_dsb_idx(bp); | |
6546 | bnx2x_init_sp_ring(bp); | |
3cdeec22 YM |
6547 | } else { |
6548 | bnx2x_memset_stats(bp); | |
ecf01c22 YM |
6549 | } |
6550 | } | |
16119785 | 6551 | |
ecf01c22 YM |
6552 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) |
6553 | { | |
523224a3 | 6554 | bnx2x_init_eq_ring(bp); |
471de716 | 6555 | bnx2x_init_internal(bp, load_code); |
523224a3 | 6556 | bnx2x_pf_init(bp); |
0ef00459 EG |
6557 | bnx2x_stats_init(bp); |
6558 | ||
0ef00459 EG |
6559 | /* flush all before enabling interrupts */ |
6560 | mb(); | |
0ef00459 | 6561 | |
615f8fd9 | 6562 | bnx2x_int_enable(bp); |
eb8da205 EG |
6563 | |
6564 | /* Check for SPIO5 */ | |
6565 | bnx2x_attn_int_deasserted0(bp, | |
6566 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
6567 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
6568 | } |
6569 | ||
ecf01c22 | 6570 | /* gzip service functions */ |
a2fbb9ea ET |
6571 | static int bnx2x_gunzip_init(struct bnx2x *bp) |
6572 | { | |
1a983142 FT |
6573 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
6574 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
6575 | if (bp->gunzip_buf == NULL) |
6576 | goto gunzip_nomem1; | |
6577 | ||
6578 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
6579 | if (bp->strm == NULL) | |
6580 | goto gunzip_nomem2; | |
6581 | ||
7ab24bfd | 6582 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
6583 | if (bp->strm->workspace == NULL) |
6584 | goto gunzip_nomem3; | |
6585 | ||
6586 | return 0; | |
6587 | ||
6588 | gunzip_nomem3: | |
6589 | kfree(bp->strm); | |
6590 | bp->strm = NULL; | |
6591 | ||
6592 | gunzip_nomem2: | |
1a983142 FT |
6593 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6594 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6595 | bp->gunzip_buf = NULL; |
6596 | ||
6597 | gunzip_nomem1: | |
51c1a580 | 6598 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
a2fbb9ea ET |
6599 | return -ENOMEM; |
6600 | } | |
6601 | ||
6602 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
6603 | { | |
b3b83c3f | 6604 | if (bp->strm) { |
7ab24bfd | 6605 | vfree(bp->strm->workspace); |
b3b83c3f DK |
6606 | kfree(bp->strm); |
6607 | bp->strm = NULL; | |
6608 | } | |
a2fbb9ea ET |
6609 | |
6610 | if (bp->gunzip_buf) { | |
1a983142 FT |
6611 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6612 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6613 | bp->gunzip_buf = NULL; |
6614 | } | |
6615 | } | |
6616 | ||
94a78b79 | 6617 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
6618 | { |
6619 | int n, rc; | |
6620 | ||
6621 | /* check gzip header */ | |
94a78b79 VZ |
6622 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
6623 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 6624 | return -EINVAL; |
94a78b79 | 6625 | } |
a2fbb9ea ET |
6626 | |
6627 | n = 10; | |
6628 | ||
34f80b04 | 6629 | #define FNAME 0x8 |
a2fbb9ea ET |
6630 | |
6631 | if (zbuf[3] & FNAME) | |
6632 | while ((zbuf[n++] != 0) && (n < len)); | |
6633 | ||
94a78b79 | 6634 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
6635 | bp->strm->avail_in = len - n; |
6636 | bp->strm->next_out = bp->gunzip_buf; | |
6637 | bp->strm->avail_out = FW_BUF_SIZE; | |
6638 | ||
6639 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
6640 | if (rc != Z_OK) | |
6641 | return rc; | |
6642 | ||
6643 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
6644 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
6645 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
6646 | bp->strm->msg); | |
a2fbb9ea ET |
6647 | |
6648 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
6649 | if (bp->gunzip_outlen & 0x3) | |
51c1a580 MS |
6650 | netdev_err(bp->dev, |
6651 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", | |
cdaa7cb8 | 6652 | bp->gunzip_outlen); |
a2fbb9ea ET |
6653 | bp->gunzip_outlen >>= 2; |
6654 | ||
6655 | zlib_inflateEnd(bp->strm); | |
6656 | ||
6657 | if (rc == Z_STREAM_END) | |
6658 | return 0; | |
6659 | ||
6660 | return rc; | |
6661 | } | |
6662 | ||
6663 | /* nic load/unload */ | |
6664 | ||
6665 | /* | |
34f80b04 | 6666 | * General service functions |
a2fbb9ea ET |
6667 | */ |
6668 | ||
6669 | /* send a NIG loopback debug packet */ | |
6670 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
6671 | { | |
a2fbb9ea | 6672 | u32 wb_write[3]; |
a2fbb9ea ET |
6673 | |
6674 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
6675 | wb_write[0] = 0x55555555; |
6676 | wb_write[1] = 0x55555555; | |
34f80b04 | 6677 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 6678 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6679 | |
6680 | /* NON-IP protocol */ | |
a2fbb9ea ET |
6681 | wb_write[0] = 0x09000000; |
6682 | wb_write[1] = 0x55555555; | |
34f80b04 | 6683 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 6684 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6685 | } |
6686 | ||
6687 | /* some of the internal memories | |
6688 | * are not directly readable from the driver | |
6689 | * to test them we send debug packets | |
6690 | */ | |
6691 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
6692 | { | |
6693 | int factor; | |
6694 | int count, i; | |
6695 | u32 val = 0; | |
6696 | ||
ad8d3948 | 6697 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 6698 | factor = 120; |
ad8d3948 EG |
6699 | else if (CHIP_REV_IS_EMUL(bp)) |
6700 | factor = 200; | |
6701 | else | |
a2fbb9ea | 6702 | factor = 1; |
a2fbb9ea | 6703 | |
a2fbb9ea ET |
6704 | /* Disable inputs of parser neighbor blocks */ |
6705 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6706 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6707 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6708 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6709 | |
6710 | /* Write 0 to parser credits for CFC search request */ | |
6711 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6712 | ||
6713 | /* send Ethernet packet */ | |
6714 | bnx2x_lb_pckt(bp); | |
6715 | ||
6716 | /* TODO do i reset NIG statistic? */ | |
6717 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6718 | count = 1000 * factor; | |
6719 | while (count) { | |
34f80b04 | 6720 | |
a2fbb9ea ET |
6721 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6722 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6723 | if (val == 0x10) |
6724 | break; | |
6725 | ||
639d65b8 | 6726 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6727 | count--; |
6728 | } | |
6729 | if (val != 0x10) { | |
6730 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6731 | return -1; | |
6732 | } | |
6733 | ||
6734 | /* Wait until PRS register shows 1 packet */ | |
6735 | count = 1000 * factor; | |
6736 | while (count) { | |
6737 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
6738 | if (val == 1) |
6739 | break; | |
6740 | ||
639d65b8 | 6741 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6742 | count--; |
6743 | } | |
6744 | if (val != 0x1) { | |
6745 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6746 | return -2; | |
6747 | } | |
6748 | ||
6749 | /* Reset and init BRB, PRS */ | |
34f80b04 | 6750 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 6751 | msleep(50); |
34f80b04 | 6752 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 6753 | msleep(50); |
619c5cb6 VZ |
6754 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6755 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
6756 | |
6757 | DP(NETIF_MSG_HW, "part2\n"); | |
6758 | ||
6759 | /* Disable inputs of parser neighbor blocks */ | |
6760 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6761 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6762 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6763 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6764 | |
6765 | /* Write 0 to parser credits for CFC search request */ | |
6766 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6767 | ||
6768 | /* send 10 Ethernet packets */ | |
6769 | for (i = 0; i < 10; i++) | |
6770 | bnx2x_lb_pckt(bp); | |
6771 | ||
6772 | /* Wait until NIG register shows 10 + 1 | |
6773 | packets of size 11*0x10 = 0xb0 */ | |
6774 | count = 1000 * factor; | |
6775 | while (count) { | |
34f80b04 | 6776 | |
a2fbb9ea ET |
6777 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6778 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6779 | if (val == 0xb0) |
6780 | break; | |
6781 | ||
639d65b8 | 6782 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6783 | count--; |
6784 | } | |
6785 | if (val != 0xb0) { | |
6786 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6787 | return -3; | |
6788 | } | |
6789 | ||
6790 | /* Wait until PRS register shows 2 packets */ | |
6791 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6792 | if (val != 2) | |
6793 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6794 | ||
6795 | /* Write 1 to parser credits for CFC search request */ | |
6796 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
6797 | ||
6798 | /* Wait until PRS register shows 3 packets */ | |
6799 | msleep(10 * factor); | |
6800 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6801 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6802 | if (val != 3) | |
6803 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6804 | ||
6805 | /* clear NIG EOP FIFO */ | |
6806 | for (i = 0; i < 11; i++) | |
6807 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
6808 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
6809 | if (val != 1) { | |
6810 | BNX2X_ERR("clear of NIG failed\n"); | |
6811 | return -4; | |
6812 | } | |
6813 | ||
6814 | /* Reset and init BRB, PRS, NIG */ | |
6815 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
6816 | msleep(50); | |
6817 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
6818 | msleep(50); | |
619c5cb6 VZ |
6819 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6820 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
55c11941 MS |
6821 | if (!CNIC_SUPPORT(bp)) |
6822 | /* set NIC mode */ | |
6823 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
a2fbb9ea ET |
6824 | |
6825 | /* Enable inputs of parser neighbor blocks */ | |
6826 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
6827 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
6828 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 6829 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
6830 | |
6831 | DP(NETIF_MSG_HW, "done\n"); | |
6832 | ||
6833 | return 0; /* OK */ | |
6834 | } | |
6835 | ||
4a33bc03 | 6836 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea | 6837 | { |
b343d002 YM |
6838 | u32 val; |
6839 | ||
a2fbb9ea | 6840 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); |
619c5cb6 | 6841 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6842 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
6843 | else | |
6844 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
6845 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
6846 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
6847 | /* |
6848 | * mask read length error interrupts in brb for parser | |
6849 | * (parsing unit and 'checksum and crc' unit) | |
6850 | * these errors are legal (PU reads fixed length and CAC can cause | |
6851 | * read length error on truncated packets) | |
6852 | */ | |
6853 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
6854 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
6855 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
6856 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
6857 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
6858 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
6859 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
6860 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6861 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
6862 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
6863 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
6864 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
6865 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6866 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
6867 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
6868 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
6869 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
6870 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
6871 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 6872 | |
b343d002 YM |
6873 | val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
6874 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | | |
6875 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; | |
6876 | if (!CHIP_IS_E1x(bp)) | |
6877 | val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | | |
6878 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; | |
6879 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); | |
6880 | ||
a2fbb9ea ET |
6881 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
6882 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
6883 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 6884 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
6885 | |
6886 | if (!CHIP_IS_E1x(bp)) | |
6887 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
6888 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
6889 | ||
a2fbb9ea ET |
6890 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
6891 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 6892 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 6893 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
6894 | } |
6895 | ||
81f75bbf EG |
6896 | static void bnx2x_reset_common(struct bnx2x *bp) |
6897 | { | |
619c5cb6 VZ |
6898 | u32 val = 0x1400; |
6899 | ||
81f75bbf EG |
6900 | /* reset_common */ |
6901 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6902 | 0xd3ffff7f); | |
619c5cb6 VZ |
6903 | |
6904 | if (CHIP_IS_E3(bp)) { | |
6905 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6906 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6907 | } | |
6908 | ||
6909 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
6910 | } | |
6911 | ||
6912 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
6913 | { | |
6914 | bp->dmae_ready = 0; | |
6915 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
6916 | } |
6917 | ||
573f2035 EG |
6918 | static void bnx2x_init_pxp(struct bnx2x *bp) |
6919 | { | |
6920 | u16 devctl; | |
6921 | int r_order, w_order; | |
6922 | ||
2a80eebc | 6923 | pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
6924 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
6925 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
6926 | if (bp->mrrs == -1) | |
6927 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
6928 | else { | |
6929 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
6930 | r_order = bp->mrrs; | |
6931 | } | |
6932 | ||
6933 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
6934 | } | |
fd4ef40d EG |
6935 | |
6936 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
6937 | { | |
2145a920 | 6938 | int is_required; |
fd4ef40d | 6939 | u32 val; |
2145a920 | 6940 | int port; |
fd4ef40d | 6941 | |
2145a920 VZ |
6942 | if (BP_NOMCP(bp)) |
6943 | return; | |
6944 | ||
6945 | is_required = 0; | |
fd4ef40d EG |
6946 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
6947 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
6948 | ||
6949 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
6950 | is_required = 1; | |
6951 | ||
6952 | /* | |
6953 | * The fan failure mechanism is usually related to the PHY type since | |
6954 | * the power consumption of the board is affected by the PHY. Currently, | |
6955 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
6956 | */ | |
6957 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
6958 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 6959 | is_required |= |
d90d96ba YR |
6960 | bnx2x_fan_failure_det_req( |
6961 | bp, | |
6962 | bp->common.shmem_base, | |
a22f0788 | 6963 | bp->common.shmem2_base, |
d90d96ba | 6964 | port); |
fd4ef40d EG |
6965 | } |
6966 | ||
6967 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
6968 | ||
6969 | if (is_required == 0) | |
6970 | return; | |
6971 | ||
6972 | /* Fan failure is indicated by SPIO 5 */ | |
d6d99a3f | 6973 | bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); |
fd4ef40d EG |
6974 | |
6975 | /* set to active low mode */ | |
6976 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
d6d99a3f | 6977 | val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
6978 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
6979 | ||
6980 | /* enable interrupt to signal the IGU */ | |
6981 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 6982 | val |= MISC_SPIO_SPIO5; |
fd4ef40d EG |
6983 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); |
6984 | } | |
6985 | ||
c9ee9206 | 6986 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
6987 | { |
6988 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
6989 | val &= ~IGU_PF_CONF_FUNC_EN; | |
6990 | ||
6991 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
6992 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6993 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
6994 | } | |
6995 | ||
1191cb83 | 6996 | static void bnx2x__common_init_phy(struct bnx2x *bp) |
619c5cb6 VZ |
6997 | { |
6998 | u32 shmem_base[2], shmem2_base[2]; | |
b884d95b YR |
6999 | /* Avoid common init in case MFW supports LFA */ |
7000 | if (SHMEM2_RD(bp, size) > | |
7001 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
7002 | return; | |
619c5cb6 VZ |
7003 | shmem_base[0] = bp->common.shmem_base; |
7004 | shmem2_base[0] = bp->common.shmem2_base; | |
7005 | if (!CHIP_IS_E1x(bp)) { | |
7006 | shmem_base[1] = | |
7007 | SHMEM2_RD(bp, other_shmem_base_addr); | |
7008 | shmem2_base[1] = | |
7009 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
7010 | } | |
7011 | bnx2x_acquire_phy_lock(bp); | |
7012 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
7013 | bp->common.chip_id); | |
7014 | bnx2x_release_phy_lock(bp); | |
7015 | } | |
7016 | ||
04860eb7 MC |
7017 | static void bnx2x_config_endianity(struct bnx2x *bp, u32 val) |
7018 | { | |
7019 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); | |
7020 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); | |
7021 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); | |
7022 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); | |
7023 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); | |
7024 | ||
7025 | /* make sure this value is 0 */ | |
7026 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
7027 | ||
7028 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); | |
7029 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); | |
7030 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); | |
7031 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); | |
7032 | } | |
7033 | ||
7034 | static void bnx2x_set_endianity(struct bnx2x *bp) | |
7035 | { | |
7036 | #ifdef __BIG_ENDIAN | |
7037 | bnx2x_config_endianity(bp, 1); | |
7038 | #else | |
7039 | bnx2x_config_endianity(bp, 0); | |
7040 | #endif | |
7041 | } | |
7042 | ||
7043 | static void bnx2x_reset_endianity(struct bnx2x *bp) | |
7044 | { | |
7045 | bnx2x_config_endianity(bp, 0); | |
7046 | } | |
7047 | ||
619c5cb6 VZ |
7048 | /** |
7049 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
7050 | * | |
7051 | * @bp: driver handle | |
7052 | */ | |
7053 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 7054 | { |
619c5cb6 | 7055 | u32 val; |
a2fbb9ea | 7056 | |
51c1a580 | 7057 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 7058 | |
2031bd3a | 7059 | /* |
2de67439 | 7060 | * take the RESET lock to protect undi_unload flow from accessing |
2031bd3a DK |
7061 | * registers while we're resetting the chip |
7062 | */ | |
7a06a122 | 7063 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 7064 | |
81f75bbf | 7065 | bnx2x_reset_common(bp); |
34f80b04 | 7066 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 7067 | |
619c5cb6 VZ |
7068 | val = 0xfffc; |
7069 | if (CHIP_IS_E3(bp)) { | |
7070 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
7071 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
7072 | } | |
7073 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
7074 | ||
7a06a122 | 7075 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 7076 | |
619c5cb6 | 7077 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 7078 | |
619c5cb6 VZ |
7079 | if (!CHIP_IS_E1x(bp)) { |
7080 | u8 abs_func_id; | |
f2e0899f DK |
7081 | |
7082 | /** | |
7083 | * 4-port mode or 2-port mode we need to turn of master-enable | |
7084 | * for everyone, after that, turn it back on for self. | |
7085 | * so, we disregard multi-function or not, and always disable | |
7086 | * for all functions on the given path, this means 0,2,4,6 for | |
7087 | * path 0 and 1,3,5,7 for path 1 | |
7088 | */ | |
619c5cb6 VZ |
7089 | for (abs_func_id = BP_PATH(bp); |
7090 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
7091 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
7092 | REG_WR(bp, |
7093 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
7094 | 1); | |
7095 | continue; | |
7096 | } | |
7097 | ||
619c5cb6 | 7098 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
7099 | /* clear pf enable */ |
7100 | bnx2x_pf_disable(bp); | |
7101 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
7102 | } | |
7103 | } | |
a2fbb9ea | 7104 | |
619c5cb6 | 7105 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
7106 | if (CHIP_IS_E1(bp)) { |
7107 | /* enable HW interrupt from PXP on USDM overflow | |
7108 | bit 16 on INT_MASK_0 */ | |
7109 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
7110 | } | |
a2fbb9ea | 7111 | |
619c5cb6 | 7112 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 7113 | bnx2x_init_pxp(bp); |
04860eb7 | 7114 | bnx2x_set_endianity(bp); |
523224a3 DK |
7115 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
7116 | ||
34f80b04 EG |
7117 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
7118 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 7119 | |
34f80b04 EG |
7120 | /* let the HW do it's magic ... */ |
7121 | msleep(100); | |
7122 | /* finish PXP init */ | |
7123 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
7124 | if (val != 1) { | |
7125 | BNX2X_ERR("PXP2 CFG failed\n"); | |
7126 | return -EBUSY; | |
7127 | } | |
7128 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
7129 | if (val != 1) { | |
7130 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
7131 | return -EBUSY; | |
7132 | } | |
a2fbb9ea | 7133 | |
f2e0899f DK |
7134 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
7135 | * have entries with value "0" and valid bit on. | |
7136 | * This needs to be done by the first PF that is loaded in a path | |
7137 | * (i.e. common phase) | |
7138 | */ | |
619c5cb6 VZ |
7139 | if (!CHIP_IS_E1x(bp)) { |
7140 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
7141 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
7142 | * This occurs when a different function (func2,3) is being marked | |
7143 | * as "scan-off". Real-life scenario for example: if a driver is being | |
7144 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
7145 | * the ilt, translate to a logical address and send a request to read/write. | |
7146 | * Since the ilt for the function that is down is not valid, this will cause | |
7147 | * a translation error which is unrecoverable. | |
7148 | * The Workaround is intended to make sure that when this happens nothing fatal | |
7149 | * will occur. The workaround: | |
7150 | * 1. First PF driver which loads on a path will: | |
7151 | * a. After taking the chip out of reset, by using pretend, | |
7152 | * it will write "0" to the following registers of | |
7153 | * the other vnics. | |
7154 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
7155 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
7156 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
7157 | * And for itself it will write '1' to | |
7158 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
7159 | * dmae-operations (writing to pram for example.) | |
7160 | * note: can be done for only function 6,7 but cleaner this | |
7161 | * way. | |
7162 | * b. Write zero+valid to the entire ILT. | |
7163 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
7164 | * VNIC3 (of that port). The range allocated will be the | |
7165 | * entire ILT. This is needed to prevent ILT range error. | |
7166 | * 2. Any PF driver load flow: | |
7167 | * a. ILT update with the physical addresses of the allocated | |
7168 | * logical pages. | |
7169 | * b. Wait 20msec. - note that this timeout is needed to make | |
7170 | * sure there are no requests in one of the PXP internal | |
7171 | * queues with "old" ILT addresses. | |
7172 | * c. PF enable in the PGLC. | |
7173 | * d. Clear the was_error of the PF in the PGLC. (could have | |
2de67439 | 7174 | * occurred while driver was down) |
619c5cb6 VZ |
7175 | * e. PF enable in the CFC (WEAK + STRONG) |
7176 | * f. Timers scan enable | |
7177 | * 3. PF driver unload flow: | |
7178 | * a. Clear the Timers scan_en. | |
7179 | * b. Polling for scan_on=0 for that PF. | |
7180 | * c. Clear the PF enable bit in the PXP. | |
7181 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
7182 | * e. Write zero+valid to all ILT entries (The valid bit must | |
7183 | * stay set) | |
7184 | * f. If this is VNIC 3 of a port then also init | |
7185 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
16a5fd92 | 7186 | * to the last entry in the ILT. |
619c5cb6 VZ |
7187 | * |
7188 | * Notes: | |
7189 | * Currently the PF error in the PGLC is non recoverable. | |
7190 | * In the future the there will be a recovery routine for this error. | |
7191 | * Currently attention is masked. | |
7192 | * Having an MCP lock on the load/unload process does not guarantee that | |
7193 | * there is no Timer disable during Func6/7 enable. This is because the | |
7194 | * Timers scan is currently being cleared by the MCP on FLR. | |
7195 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
7196 | * there is error before clearing it. But the flow above is simpler and | |
7197 | * more general. | |
7198 | * All ILT entries are written by zero+valid and not just PF6/7 | |
7199 | * ILT entries since in the future the ILT entries allocation for | |
7200 | * PF-s might be dynamic. | |
7201 | */ | |
f2e0899f DK |
7202 | struct ilt_client_info ilt_cli; |
7203 | struct bnx2x_ilt ilt; | |
7204 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
7205 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
7206 | ||
b595076a | 7207 | /* initialize dummy TM client */ |
f2e0899f DK |
7208 | ilt_cli.start = 0; |
7209 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
7210 | ilt_cli.client_num = ILT_CLIENT_TM; | |
7211 | ||
7212 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
7213 | * Step 2: set the timers first/last ilt entry to point | |
7214 | * to the entire range to prevent ILT range error for 3rd/4th | |
2de67439 | 7215 | * vnic (this code assumes existence of the vnic) |
f2e0899f DK |
7216 | * |
7217 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
7218 | * with dummy TM client | |
7219 | * | |
7220 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
7221 | * and his brother are split registers | |
7222 | */ | |
7223 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
7224 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
7225 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
7226 | ||
7227 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
7228 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
7229 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
7230 | } | |
7231 | ||
34f80b04 EG |
7232 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
7233 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 7234 | |
619c5cb6 | 7235 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7236 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
7237 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 7238 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 7239 | |
619c5cb6 | 7240 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
7241 | |
7242 | /* let the HW do it's magic ... */ | |
7243 | do { | |
7244 | msleep(200); | |
7245 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
7246 | } while (factor-- && (val != 1)); | |
7247 | ||
7248 | if (val != 1) { | |
7249 | BNX2X_ERR("ATC_INIT failed\n"); | |
7250 | return -EBUSY; | |
7251 | } | |
7252 | } | |
7253 | ||
619c5cb6 | 7254 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 7255 | |
b56e9670 AE |
7256 | bnx2x_iov_init_dmae(bp); |
7257 | ||
34f80b04 EG |
7258 | /* clean the DMAE memory */ |
7259 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
7260 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
7261 | ||
7262 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
7263 | ||
7264 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
7265 | ||
7266 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 7267 | |
619c5cb6 | 7268 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 7269 | |
34f80b04 EG |
7270 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
7271 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
7272 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
7273 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
7274 | ||
619c5cb6 | 7275 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 7276 | |
523224a3 DK |
7277 | /* QM queues pointers table */ |
7278 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
7279 | ||
34f80b04 EG |
7280 | /* soft reset pulse */ |
7281 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
7282 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 7283 | |
55c11941 MS |
7284 | if (CNIC_SUPPORT(bp)) |
7285 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); | |
a2fbb9ea | 7286 | |
619c5cb6 | 7287 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
b9871bcf | 7288 | |
619c5cb6 | 7289 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
7290 | /* enable hw interrupt from doorbell Q */ |
7291 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 7292 | |
619c5cb6 | 7293 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 7294 | |
619c5cb6 | 7295 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 7296 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 7297 | |
f2e0899f | 7298 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 7299 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 7300 | |
a3348722 BW |
7301 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { |
7302 | if (IS_MF_AFEX(bp)) { | |
7303 | /* configure that VNTag and VLAN headers must be | |
7304 | * received in afex mode | |
7305 | */ | |
7306 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); | |
7307 | REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); | |
7308 | REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); | |
7309 | REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); | |
7310 | REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); | |
7311 | } else { | |
7312 | /* Bit-map indicating which L2 hdrs may appear | |
7313 | * after the basic Ethernet header | |
7314 | */ | |
7315 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
7316 | bp->path_has_ovlan ? 7 : 6); | |
7317 | } | |
7318 | } | |
a2fbb9ea | 7319 | |
619c5cb6 VZ |
7320 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
7321 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
7322 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
7323 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 7324 | |
619c5cb6 VZ |
7325 | if (!CHIP_IS_E1x(bp)) { |
7326 | /* reset VFC memories */ | |
7327 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
7328 | VFC_MEMORIES_RST_REG_CAM_RST | | |
7329 | VFC_MEMORIES_RST_REG_RAM_RST); | |
7330 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
7331 | VFC_MEMORIES_RST_REG_CAM_RST | | |
7332 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 7333 | |
619c5cb6 VZ |
7334 | msleep(20); |
7335 | } | |
a2fbb9ea | 7336 | |
619c5cb6 VZ |
7337 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
7338 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
7339 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
7340 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 7341 | |
34f80b04 EG |
7342 | /* sync semi rtc */ |
7343 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
7344 | 0x80000000); | |
7345 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
7346 | 0x80000000); | |
a2fbb9ea | 7347 | |
619c5cb6 VZ |
7348 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
7349 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
7350 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 7351 | |
a3348722 BW |
7352 | if (!CHIP_IS_E1x(bp)) { |
7353 | if (IS_MF_AFEX(bp)) { | |
7354 | /* configure that VNTag and VLAN headers must be | |
7355 | * sent in afex mode | |
7356 | */ | |
7357 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); | |
7358 | REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); | |
7359 | REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); | |
7360 | REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); | |
7361 | REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); | |
7362 | } else { | |
7363 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
7364 | bp->path_has_ovlan ? 7 : 6); | |
7365 | } | |
7366 | } | |
f2e0899f | 7367 | |
34f80b04 | 7368 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 7369 | |
619c5cb6 VZ |
7370 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
7371 | ||
55c11941 MS |
7372 | if (CNIC_SUPPORT(bp)) { |
7373 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
7374 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
7375 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
7376 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
7377 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
7378 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
7379 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
7380 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
7381 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
7382 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
7383 | } | |
34f80b04 | 7384 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 7385 | |
34f80b04 EG |
7386 | if (sizeof(union cdu_context) != 1024) |
7387 | /* we currently assume that a context is 1024 bytes */ | |
51c1a580 MS |
7388 | dev_alert(&bp->pdev->dev, |
7389 | "please adjust the size of cdu_context(%ld)\n", | |
7390 | (long)sizeof(union cdu_context)); | |
a2fbb9ea | 7391 | |
619c5cb6 | 7392 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
7393 | val = (4 << 24) + (0 << 12) + 1024; |
7394 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 7395 | |
619c5cb6 | 7396 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 7397 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
7398 | /* enable context validation interrupt from CFC */ |
7399 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
7400 | ||
7401 | /* set the thresholds to prevent CFC/CDU race */ | |
7402 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 7403 | |
619c5cb6 | 7404 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 7405 | |
619c5cb6 | 7406 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
7407 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
7408 | ||
619c5cb6 VZ |
7409 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
7410 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 7411 | |
34f80b04 EG |
7412 | /* Reset PCIE errors for debug */ |
7413 | REG_WR(bp, 0x2814, 0xffffffff); | |
7414 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 7415 | |
619c5cb6 | 7416 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7417 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
7418 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
7419 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
7420 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
7421 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
7422 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
7423 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
7424 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
7425 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
7426 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
7427 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
7428 | } | |
7429 | ||
619c5cb6 | 7430 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 7431 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
7432 | /* in E3 this done in per-port section */ |
7433 | if (!CHIP_IS_E3(bp)) | |
7434 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 7435 | } |
619c5cb6 VZ |
7436 | if (CHIP_IS_E1H(bp)) |
7437 | /* not applicable for E2 (and above ...) */ | |
7438 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
7439 | |
7440 | if (CHIP_REV_IS_SLOW(bp)) | |
7441 | msleep(200); | |
7442 | ||
7443 | /* finish CFC init */ | |
7444 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
7445 | if (val != 1) { | |
7446 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
7447 | return -EBUSY; | |
7448 | } | |
7449 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
7450 | if (val != 1) { | |
7451 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
7452 | return -EBUSY; | |
7453 | } | |
7454 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
7455 | if (val != 1) { | |
7456 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
7457 | return -EBUSY; | |
7458 | } | |
7459 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 7460 | |
f2e0899f DK |
7461 | if (CHIP_IS_E1(bp)) { |
7462 | /* read NIG statistic | |
7463 | to see if this is our first up since powerup */ | |
7464 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
7465 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 7466 | |
f2e0899f DK |
7467 | /* do internal memory self test */ |
7468 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
7469 | BNX2X_ERR("internal mem self test failed\n"); | |
7470 | return -EBUSY; | |
7471 | } | |
34f80b04 EG |
7472 | } |
7473 | ||
fd4ef40d EG |
7474 | bnx2x_setup_fan_failure_detection(bp); |
7475 | ||
34f80b04 EG |
7476 | /* clear PXP2 attentions */ |
7477 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 7478 | |
4a33bc03 | 7479 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 7480 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 7481 | |
6bbca910 | 7482 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
7483 | if (CHIP_IS_E1x(bp)) |
7484 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
7485 | } else |
7486 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
7487 | ||
230d00eb YM |
7488 | if (SHMEM2_HAS(bp, netproc_fw_ver)) |
7489 | SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM)); | |
7490 | ||
34f80b04 EG |
7491 | return 0; |
7492 | } | |
a2fbb9ea | 7493 | |
619c5cb6 VZ |
7494 | /** |
7495 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
7496 | * | |
7497 | * @bp: driver handle | |
7498 | */ | |
7499 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
7500 | { | |
7501 | int rc = bnx2x_init_hw_common(bp); | |
7502 | ||
7503 | if (rc) | |
7504 | return rc; | |
7505 | ||
7506 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
7507 | if (!BP_NOMCP(bp)) | |
7508 | bnx2x__common_init_phy(bp); | |
7509 | ||
7510 | return 0; | |
7511 | } | |
7512 | ||
523224a3 | 7513 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
7514 | { |
7515 | int port = BP_PORT(bp); | |
619c5cb6 | 7516 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 7517 | u32 low, high; |
4293b9f5 | 7518 | u32 val, reg; |
a2fbb9ea | 7519 | |
51c1a580 | 7520 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
34f80b04 EG |
7521 | |
7522 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 7523 | |
619c5cb6 VZ |
7524 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
7525 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
7526 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 7527 | |
f2e0899f DK |
7528 | /* Timers bug workaround: disables the pf_master bit in pglue at |
7529 | * common phase, we need to enable it here before any dmae access are | |
7530 | * attempted. Therefore we manually added the enable-master to the | |
7531 | * port phase (it also happens in the function phase) | |
7532 | */ | |
619c5cb6 | 7533 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7534 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
7535 | ||
619c5cb6 VZ |
7536 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7537 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7538 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
7539 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7540 | ||
7541 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7542 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7543 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7544 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 7545 | |
523224a3 DK |
7546 | /* QM cid (connection) count */ |
7547 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 7548 | |
55c11941 MS |
7549 | if (CNIC_SUPPORT(bp)) { |
7550 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7551 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); | |
7552 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
7553 | } | |
cdaa7cb8 | 7554 | |
619c5cb6 | 7555 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f | 7556 | |
2b674047 DK |
7557 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
7558 | ||
f2e0899f | 7559 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { |
619c5cb6 VZ |
7560 | |
7561 | if (IS_MF(bp)) | |
7562 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
7563 | else if (bp->dev->mtu > 4096) { | |
7564 | if (bp->flags & ONE_PORT_FLAG) | |
7565 | low = 160; | |
7566 | else { | |
7567 | val = bp->dev->mtu; | |
7568 | /* (24*1024 + val*4)/256 */ | |
7569 | low = 96 + (val/64) + | |
7570 | ((val % 64) ? 1 : 0); | |
7571 | } | |
7572 | } else | |
7573 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
7574 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
7575 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
7576 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 7577 | } |
1c06328c | 7578 | |
619c5cb6 VZ |
7579 | if (CHIP_MODE_IS_4_PORT(bp)) |
7580 | REG_WR(bp, (BP_PORT(bp) ? | |
7581 | BRB1_REG_MAC_GUARANTIED_1 : | |
7582 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 7583 | |
619c5cb6 | 7584 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
a3348722 BW |
7585 | if (CHIP_IS_E3B0(bp)) { |
7586 | if (IS_MF_AFEX(bp)) { | |
7587 | /* configure headers for AFEX mode */ | |
7588 | REG_WR(bp, BP_PORT(bp) ? | |
7589 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7590 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); | |
7591 | REG_WR(bp, BP_PORT(bp) ? | |
7592 | PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : | |
7593 | PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); | |
7594 | REG_WR(bp, BP_PORT(bp) ? | |
7595 | PRS_REG_MUST_HAVE_HDRS_PORT_1 : | |
7596 | PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); | |
7597 | } else { | |
7598 | /* Ovlan exists only if we are in multi-function + | |
7599 | * switch-dependent mode, in switch-independent there | |
7600 | * is no ovlan headers | |
7601 | */ | |
7602 | REG_WR(bp, BP_PORT(bp) ? | |
7603 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7604 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
7605 | (bp->path_has_ovlan ? 7 : 6)); | |
7606 | } | |
7607 | } | |
356e2385 | 7608 | |
619c5cb6 VZ |
7609 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
7610 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7611 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7612 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 7613 | |
619c5cb6 VZ |
7614 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
7615 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7616 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7617 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 7618 | |
619c5cb6 VZ |
7619 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
7620 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 7621 | |
619c5cb6 VZ |
7622 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
7623 | ||
7624 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
7625 | /* configure PBF to work without PAUSE mtu 9000 */ |
7626 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 7627 | |
f2e0899f DK |
7628 | /* update threshold */ |
7629 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
7630 | /* update init credit */ | |
7631 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 7632 | |
f2e0899f DK |
7633 | /* probe changes */ |
7634 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
7635 | udelay(50); | |
7636 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
7637 | } | |
a2fbb9ea | 7638 | |
55c11941 MS |
7639 | if (CNIC_SUPPORT(bp)) |
7640 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7641 | ||
619c5cb6 VZ |
7642 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
7643 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
7644 | |
7645 | if (CHIP_IS_E1(bp)) { | |
7646 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7647 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7648 | } | |
619c5cb6 | 7649 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 7650 | |
619c5cb6 | 7651 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7652 | |
619c5cb6 | 7653 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 | 7654 | /* init aeu_mask_attn_func_0/1: |
16a5fd92 YM |
7655 | * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use |
7656 | * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF | |
34f80b04 | 7657 | * bits 4-7 are used for "per vn group attention" */ |
e4901dde VZ |
7658 | val = IS_MF(bp) ? 0xF7 : 0x7; |
7659 | /* Enable DCBX attention for all but E1 */ | |
7660 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
7661 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 7662 | |
4293b9f5 DK |
7663 | /* SCPAD_PARITY should NOT trigger close the gates */ |
7664 | reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0; | |
7665 | REG_WR(bp, reg, | |
7666 | REG_RD(bp, reg) & | |
7667 | ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); | |
7668 | ||
7669 | reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0; | |
7670 | REG_WR(bp, reg, | |
7671 | REG_RD(bp, reg) & | |
7672 | ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); | |
7673 | ||
619c5cb6 VZ |
7674 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
7675 | ||
7676 | if (!CHIP_IS_E1x(bp)) { | |
7677 | /* Bit-map indicating which L2 hdrs may appear after the | |
7678 | * basic Ethernet header | |
7679 | */ | |
a3348722 BW |
7680 | if (IS_MF_AFEX(bp)) |
7681 | REG_WR(bp, BP_PORT(bp) ? | |
7682 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7683 | NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); | |
7684 | else | |
7685 | REG_WR(bp, BP_PORT(bp) ? | |
7686 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7687 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
7688 | IS_MF_SD(bp) ? 7 : 6); | |
619c5cb6 VZ |
7689 | |
7690 | if (CHIP_IS_E3(bp)) | |
7691 | REG_WR(bp, BP_PORT(bp) ? | |
7692 | NIG_REG_LLH1_MF_MODE : | |
7693 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
7694 | } | |
7695 | if (!CHIP_IS_E3(bp)) | |
7696 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 7697 | |
f2e0899f | 7698 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 7699 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 7700 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 7701 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 7702 | |
619c5cb6 | 7703 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7704 | val = 0; |
7705 | switch (bp->mf_mode) { | |
7706 | case MULTI_FUNCTION_SD: | |
7707 | val = 1; | |
7708 | break; | |
7709 | case MULTI_FUNCTION_SI: | |
a3348722 | 7710 | case MULTI_FUNCTION_AFEX: |
f2e0899f DK |
7711 | val = 2; |
7712 | break; | |
7713 | } | |
7714 | ||
7715 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
7716 | NIG_REG_LLH0_CLS_TYPE), val); | |
7717 | } | |
1c06328c EG |
7718 | { |
7719 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
7720 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
7721 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
7722 | } | |
34f80b04 EG |
7723 | } |
7724 | ||
619c5cb6 VZ |
7725 | /* If SPIO5 is set to generate interrupts, enable it for this port */ |
7726 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 7727 | if (val & MISC_SPIO_SPIO5) { |
4d295db0 EG |
7728 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
7729 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
7730 | val = REG_RD(bp, reg_addr); | |
f1410647 | 7731 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 7732 | REG_WR(bp, reg_addr, val); |
f1410647 | 7733 | } |
a2fbb9ea | 7734 | |
07f12622 SRK |
7735 | if (CHIP_IS_E3B0(bp)) |
7736 | bp->flags |= PTP_SUPPORTED; | |
7737 | ||
34f80b04 EG |
7738 | return 0; |
7739 | } | |
7740 | ||
34f80b04 EG |
7741 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
7742 | { | |
7743 | int reg; | |
32d68de1 | 7744 | u32 wb_write[2]; |
34f80b04 | 7745 | |
f2e0899f | 7746 | if (CHIP_IS_E1(bp)) |
34f80b04 | 7747 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
7748 | else |
7749 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 | 7750 | |
32d68de1 YM |
7751 | wb_write[0] = ONCHIP_ADDR1(addr); |
7752 | wb_write[1] = ONCHIP_ADDR2(addr); | |
7753 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
34f80b04 EG |
7754 | } |
7755 | ||
b56e9670 | 7756 | void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) |
1191cb83 ED |
7757 | { |
7758 | u32 data, ctl, cnt = 100; | |
7759 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
7760 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
7761 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
7762 | u32 sb_bit = 1 << (idu_sb_id%32); | |
b56e9670 | 7763 | u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; |
1191cb83 ED |
7764 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; |
7765 | ||
7766 | /* Not supported in BC mode */ | |
7767 | if (CHIP_INT_MODE_IS_BC(bp)) | |
7768 | return; | |
7769 | ||
7770 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
7771 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
7772 | IGU_REGULAR_CLEANUP_SET | | |
7773 | IGU_REGULAR_BCLEANUP; | |
7774 | ||
7775 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
7776 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
7777 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
7778 | ||
7779 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7780 | data, igu_addr_data); | |
7781 | REG_WR(bp, igu_addr_data, data); | |
1191cb83 ED |
7782 | barrier(); |
7783 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7784 | ctl, igu_addr_ctl); | |
7785 | REG_WR(bp, igu_addr_ctl, ctl); | |
1191cb83 ED |
7786 | barrier(); |
7787 | ||
7788 | /* wait for clean up to finish */ | |
7789 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
7790 | msleep(20); | |
7791 | ||
1191cb83 ED |
7792 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { |
7793 | DP(NETIF_MSG_HW, | |
7794 | "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
7795 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
7796 | } | |
7797 | } | |
7798 | ||
7799 | static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) | |
f2e0899f | 7800 | { |
619c5cb6 | 7801 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
7802 | } |
7803 | ||
1191cb83 | 7804 | static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) |
f2e0899f DK |
7805 | { |
7806 | u32 i, base = FUNC_ILT_BASE(func); | |
7807 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
7808 | bnx2x_ilt_wr(bp, i, 0); | |
7809 | } | |
7810 | ||
910cc727 | 7811 | static void bnx2x_init_searcher(struct bnx2x *bp) |
55c11941 MS |
7812 | { |
7813 | int port = BP_PORT(bp); | |
7814 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
7815 | /* T1 hash bits value determines the T1 number of entries */ | |
7816 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
7817 | } | |
7818 | ||
7819 | static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) | |
7820 | { | |
7821 | int rc; | |
7822 | struct bnx2x_func_state_params func_params = {NULL}; | |
7823 | struct bnx2x_func_switch_update_params *switch_update_params = | |
7824 | &func_params.params.switch_update; | |
7825 | ||
7826 | /* Prepare parameters for function state transitions */ | |
7827 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7828 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
7829 | ||
7830 | func_params.f_obj = &bp->func_obj; | |
7831 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
7832 | ||
7833 | /* Function parameters */ | |
e42780b6 DK |
7834 | __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, |
7835 | &switch_update_params->changes); | |
7836 | if (suspend) | |
7837 | __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND, | |
7838 | &switch_update_params->changes); | |
55c11941 MS |
7839 | |
7840 | rc = bnx2x_func_state_change(bp, &func_params); | |
7841 | ||
7842 | return rc; | |
7843 | } | |
7844 | ||
910cc727 | 7845 | static int bnx2x_reset_nic_mode(struct bnx2x *bp) |
55c11941 MS |
7846 | { |
7847 | int rc, i, port = BP_PORT(bp); | |
7848 | int vlan_en = 0, mac_en[NUM_MACS]; | |
7849 | ||
55c11941 MS |
7850 | /* Close input from network */ |
7851 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7852 | bnx2x_set_rx_filter(&bp->link_params, 0); | |
7853 | } else { | |
7854 | vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7855 | NIG_REG_LLH0_FUNC_EN); | |
7856 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7857 | NIG_REG_LLH0_FUNC_EN, 0); | |
7858 | for (i = 0; i < NUM_MACS; i++) { | |
7859 | mac_en[i] = REG_RD(bp, port ? | |
7860 | (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7861 | 4 * i) : | |
7862 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + | |
7863 | 4 * i)); | |
7864 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7865 | 4 * i) : | |
7866 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); | |
7867 | } | |
7868 | } | |
7869 | ||
7870 | /* Close BMC to host */ | |
7871 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7872 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); | |
7873 | ||
7874 | /* Suspend Tx switching to the PF. Completion of this ramrod | |
7875 | * further guarantees that all the packets of that PF / child | |
7876 | * VFs in BRB were processed by the Parser, so it is safe to | |
7877 | * change the NIC_MODE register. | |
7878 | */ | |
7879 | rc = bnx2x_func_switch_update(bp, 1); | |
7880 | if (rc) { | |
7881 | BNX2X_ERR("Can't suspend tx-switching!\n"); | |
7882 | return rc; | |
7883 | } | |
7884 | ||
7885 | /* Change NIC_MODE register */ | |
7886 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7887 | ||
7888 | /* Open input from network */ | |
7889 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7890 | bnx2x_set_rx_filter(&bp->link_params, 1); | |
7891 | } else { | |
7892 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7893 | NIG_REG_LLH0_FUNC_EN, vlan_en); | |
7894 | for (i = 0; i < NUM_MACS; i++) { | |
7895 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7896 | 4 * i) : | |
7897 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), | |
7898 | mac_en[i]); | |
7899 | } | |
7900 | } | |
7901 | ||
7902 | /* Enable BMC to host */ | |
7903 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7904 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); | |
7905 | ||
7906 | /* Resume Tx switching to the PF */ | |
7907 | rc = bnx2x_func_switch_update(bp, 0); | |
7908 | if (rc) { | |
7909 | BNX2X_ERR("Can't resume tx-switching!\n"); | |
7910 | return rc; | |
7911 | } | |
7912 | ||
7913 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7914 | return 0; | |
7915 | } | |
7916 | ||
7917 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp) | |
7918 | { | |
7919 | int rc; | |
7920 | ||
7921 | bnx2x_ilt_init_op_cnic(bp, INITOP_SET); | |
7922 | ||
7923 | if (CONFIGURE_NIC_MODE(bp)) { | |
16a5fd92 | 7924 | /* Configure searcher as part of function hw init */ |
55c11941 MS |
7925 | bnx2x_init_searcher(bp); |
7926 | ||
7927 | /* Reset NIC mode */ | |
7928 | rc = bnx2x_reset_nic_mode(bp); | |
7929 | if (rc) | |
7930 | BNX2X_ERR("Can't change NIC mode!\n"); | |
7931 | return rc; | |
7932 | } | |
7933 | ||
7934 | return 0; | |
7935 | } | |
7936 | ||
da254fbc YM |
7937 | /* previous driver DMAE transaction may have occurred when pre-boot stage ended |
7938 | * and boot began, or when kdump kernel was loaded. Either case would invalidate | |
7939 | * the addresses of the transaction, resulting in was-error bit set in the pci | |
7940 | * causing all hw-to-host pcie transactions to timeout. If this happened we want | |
7941 | * to clear the interrupt which detected this from the pglueb and the was done | |
7942 | * bit | |
7943 | */ | |
7944 | static void bnx2x_clean_pglue_errors(struct bnx2x *bp) | |
7945 | { | |
7946 | if (!CHIP_IS_E1x(bp)) | |
7947 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, | |
7948 | 1 << BP_ABS_FUNC(bp)); | |
7949 | } | |
7950 | ||
523224a3 | 7951 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
7952 | { |
7953 | int port = BP_PORT(bp); | |
7954 | int func = BP_FUNC(bp); | |
619c5cb6 | 7955 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
7956 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
7957 | u16 cdu_ilt_start; | |
8badd27a | 7958 | u32 addr, val; |
f4a66897 | 7959 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
89db4ad8 | 7960 | int i, main_mem_width, rc; |
34f80b04 | 7961 | |
51c1a580 | 7962 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
34f80b04 | 7963 | |
619c5cb6 | 7964 | /* FLR cleanup - hmmm */ |
89db4ad8 AE |
7965 | if (!CHIP_IS_E1x(bp)) { |
7966 | rc = bnx2x_pf_flr_clnup(bp); | |
04c46736 YM |
7967 | if (rc) { |
7968 | bnx2x_fw_dump(bp); | |
89db4ad8 | 7969 | return rc; |
04c46736 | 7970 | } |
89db4ad8 | 7971 | } |
619c5cb6 | 7972 | |
8badd27a | 7973 | /* set MSI reconfigure capability */ |
f2e0899f DK |
7974 | if (bp->common.int_block == INT_BLOCK_HC) { |
7975 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
7976 | val = REG_RD(bp, addr); | |
7977 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
7978 | REG_WR(bp, addr, val); | |
7979 | } | |
8badd27a | 7980 | |
619c5cb6 VZ |
7981 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
7982 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
7983 | ||
523224a3 DK |
7984 | ilt = BP_ILT(bp); |
7985 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 7986 | |
290ca2bb AE |
7987 | if (IS_SRIOV(bp)) |
7988 | cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; | |
7989 | cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); | |
7990 | ||
7991 | /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes | |
7992 | * those of the VFs, so start line should be reset | |
7993 | */ | |
7994 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
523224a3 | 7995 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
a052997e | 7996 | ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; |
523224a3 | 7997 | ilt->lines[cdu_ilt_start + i].page_mapping = |
a052997e MS |
7998 | bp->context[i].cxt_mapping; |
7999 | ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; | |
37b091ba | 8000 | } |
290ca2bb | 8001 | |
523224a3 | 8002 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 8003 | |
55c11941 MS |
8004 | if (!CONFIGURE_NIC_MODE(bp)) { |
8005 | bnx2x_init_searcher(bp); | |
8006 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
8007 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
8008 | } else { | |
8009 | /* Set NIC mode */ | |
8010 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6bf07b8e | 8011 | DP(NETIF_MSG_IFUP, "NIC MODE configured\n"); |
55c11941 | 8012 | } |
37b091ba | 8013 | |
619c5cb6 | 8014 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8015 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
8016 | ||
8017 | /* Turn on a single ISR mode in IGU if driver is going to use | |
8018 | * INT#x or MSI | |
8019 | */ | |
8020 | if (!(bp->flags & USING_MSIX_FLAG)) | |
8021 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
8022 | /* | |
8023 | * Timers workaround bug: function init part. | |
8024 | * Need to wait 20msec after initializing ILT, | |
8025 | * needed to make sure there are no requests in | |
8026 | * one of the PXP internal queues with "old" ILT addresses | |
8027 | */ | |
8028 | msleep(20); | |
8029 | /* | |
8030 | * Master enable - Due to WB DMAE writes performed before this | |
8031 | * register is re-initialized as part of the regular function | |
8032 | * init | |
8033 | */ | |
8034 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
8035 | /* Enable the function in IGU */ | |
8036 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
8037 | } | |
8038 | ||
523224a3 | 8039 | bp->dmae_ready = 1; |
34f80b04 | 8040 | |
619c5cb6 | 8041 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 8042 | |
da254fbc | 8043 | bnx2x_clean_pglue_errors(bp); |
f2e0899f | 8044 | |
619c5cb6 VZ |
8045 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
8046 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
8047 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
8048 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
8049 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
8050 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
8051 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
8052 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
8053 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
8054 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
8055 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
8056 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
8057 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
8058 | ||
8059 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
8060 | REG_WR(bp, QM_REG_PF_EN, 1); |
8061 | ||
619c5cb6 VZ |
8062 | if (!CHIP_IS_E1x(bp)) { |
8063 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
8064 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
8065 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
8066 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
8067 | } | |
8068 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
8069 | ||
8070 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
8071 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
c19d65c9 | 8072 | REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ |
b56e9670 AE |
8073 | |
8074 | bnx2x_iov_init_dq(bp); | |
8075 | ||
619c5cb6 VZ |
8076 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
8077 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
8078 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
8079 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
8080 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
8081 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
8082 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
8083 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
8084 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
8085 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
8086 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
8087 | ||
619c5cb6 | 8088 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 8089 | |
619c5cb6 | 8090 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 8091 | |
619c5cb6 | 8092 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
8093 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
8094 | ||
fb3bff17 | 8095 | if (IS_MF(bp)) { |
7609647e YM |
8096 | if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) { |
8097 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); | |
8098 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, | |
8099 | bp->mf_ov); | |
8100 | } | |
34f80b04 EG |
8101 | } |
8102 | ||
619c5cb6 | 8103 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 8104 | |
34f80b04 | 8105 | /* HC init per function */ |
f2e0899f DK |
8106 | if (bp->common.int_block == INT_BLOCK_HC) { |
8107 | if (CHIP_IS_E1H(bp)) { | |
8108 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
8109 | ||
8110 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
8111 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
8112 | } | |
619c5cb6 | 8113 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
8114 | |
8115 | } else { | |
8116 | int num_segs, sb_idx, prod_offset; | |
8117 | ||
34f80b04 EG |
8118 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
8119 | ||
619c5cb6 | 8120 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8121 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
8122 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
8123 | } | |
8124 | ||
619c5cb6 | 8125 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 8126 | |
619c5cb6 | 8127 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
8128 | int dsb_idx = 0; |
8129 | /** | |
8130 | * Producer memory: | |
8131 | * E2 mode: address 0-135 match to the mapping memory; | |
8132 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
8133 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
8134 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
8135 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
8136 | * 144-147 reserved. | |
8137 | * | |
8138 | * E1.5 mode - In backward compatible mode; | |
8139 | * for non default SB; each even line in the memory | |
8140 | * holds the U producer and each odd line hold | |
8141 | * the C producer. The first 128 producers are for | |
8142 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
8143 | * producers are for the DSB for each PF. | |
8144 | * Each PF has five segments: (the order inside each | |
8145 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
8146 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
8147 | * 144-147 attn prods; | |
8148 | */ | |
8149 | /* non-default-status-blocks */ | |
8150 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
8151 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
8152 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
8153 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
8154 | num_segs; | |
8155 | ||
8156 | for (i = 0; i < num_segs; i++) { | |
8157 | addr = IGU_REG_PROD_CONS_MEMORY + | |
8158 | (prod_offset + i) * 4; | |
8159 | REG_WR(bp, addr, 0); | |
8160 | } | |
8161 | /* send consumer update with value 0 */ | |
8162 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
8163 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
8164 | bnx2x_igu_clear_sb(bp, | |
8165 | bp->igu_base_sb + sb_idx); | |
8166 | } | |
8167 | ||
8168 | /* default-status-blocks */ | |
8169 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
8170 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
8171 | ||
8172 | if (CHIP_MODE_IS_4_PORT(bp)) | |
8173 | dsb_idx = BP_FUNC(bp); | |
8174 | else | |
3395a033 | 8175 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
8176 | |
8177 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
8178 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
8179 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
8180 | ||
3395a033 DK |
8181 | /* |
8182 | * igu prods come in chunks of E1HVN_MAX (4) - | |
8183 | * does not matters what is the current chip mode | |
8184 | */ | |
f2e0899f DK |
8185 | for (i = 0; i < (num_segs * E1HVN_MAX); |
8186 | i += E1HVN_MAX) { | |
8187 | addr = IGU_REG_PROD_CONS_MEMORY + | |
8188 | (prod_offset + i)*4; | |
8189 | REG_WR(bp, addr, 0); | |
8190 | } | |
8191 | /* send consumer update with 0 */ | |
8192 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
8193 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8194 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
8195 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8196 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
8197 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8198 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
8199 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8200 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
8201 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8202 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
8203 | } else { | |
8204 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8205 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
8206 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
8207 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
8208 | } | |
8209 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
8210 | ||
16a5fd92 | 8211 | /* !!! These should become driver const once |
f2e0899f DK |
8212 | rf-tool supports split-68 const */ |
8213 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
8214 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
8215 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
8216 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
8217 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
8218 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
8219 | } | |
34f80b04 | 8220 | } |
34f80b04 | 8221 | |
c14423fe | 8222 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
8223 | REG_WR(bp, 0x2114, 0xffffffff); |
8224 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 8225 | |
f4a66897 VZ |
8226 | if (CHIP_IS_E1x(bp)) { |
8227 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
8228 | main_mem_base = HC_REG_MAIN_MEMORY + | |
8229 | BP_PORT(bp) * (main_mem_size * 4); | |
8230 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
8231 | main_mem_width = 8; | |
8232 | ||
8233 | val = REG_RD(bp, main_mem_prty_clr); | |
8234 | if (val) | |
51c1a580 MS |
8235 | DP(NETIF_MSG_HW, |
8236 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", | |
8237 | val); | |
f4a66897 VZ |
8238 | |
8239 | /* Clear "false" parity errors in MSI-X table */ | |
8240 | for (i = main_mem_base; | |
8241 | i < main_mem_base + main_mem_size * 4; | |
8242 | i += main_mem_width) { | |
8243 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
8244 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
8245 | i, main_mem_width / 4); | |
8246 | } | |
8247 | /* Clear HC parity attention */ | |
8248 | REG_RD(bp, main_mem_prty_clr); | |
8249 | } | |
8250 | ||
619c5cb6 VZ |
8251 | #ifdef BNX2X_STOP_ON_ERROR |
8252 | /* Enable STORMs SP logging */ | |
8253 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
8254 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8255 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
8256 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8257 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
8258 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8259 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
8260 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
8261 | #endif | |
8262 | ||
b7737c9b | 8263 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 8264 | |
34f80b04 EG |
8265 | return 0; |
8266 | } | |
8267 | ||
55c11941 MS |
8268 | void bnx2x_free_mem_cnic(struct bnx2x *bp) |
8269 | { | |
8270 | bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); | |
8271 | ||
8272 | if (!CHIP_IS_E1x(bp)) | |
8273 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, | |
8274 | sizeof(struct host_hc_status_block_e2)); | |
8275 | else | |
8276 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
8277 | sizeof(struct host_hc_status_block_e1x)); | |
8278 | ||
8279 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); | |
8280 | } | |
8281 | ||
9f6c9258 | 8282 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 8283 | { |
a052997e MS |
8284 | int i; |
8285 | ||
619c5cb6 VZ |
8286 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
8287 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
8288 | ||
b4cddbd6 AE |
8289 | if (IS_VF(bp)) |
8290 | return; | |
8291 | ||
8292 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
8293 | sizeof(struct host_sp_status_block)); | |
8294 | ||
a2fbb9ea | 8295 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 8296 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 8297 | |
a052997e MS |
8298 | for (i = 0; i < L2_ILT_LINES(bp); i++) |
8299 | BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, | |
8300 | bp->context[i].size); | |
523224a3 DK |
8301 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); |
8302 | ||
8303 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 8304 | |
7a9b2557 | 8305 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 8306 | |
523224a3 DK |
8307 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
8308 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
580d9d08 | 8309 | |
05952246 YM |
8310 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
8311 | ||
580d9d08 | 8312 | bnx2x_iov_free_mem(bp); |
619c5cb6 VZ |
8313 | } |
8314 | ||
55c11941 | 8315 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp) |
a2fbb9ea | 8316 | { |
cd2b0389 | 8317 | if (!CHIP_IS_E1x(bp)) { |
619c5cb6 | 8318 | /* size = the status block + ramrod buffers */ |
cd2b0389 JP |
8319 | bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, |
8320 | sizeof(struct host_hc_status_block_e2)); | |
8321 | if (!bp->cnic_sb.e2_sb) | |
8322 | goto alloc_mem_err; | |
8323 | } else { | |
8324 | bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, | |
8325 | sizeof(struct host_hc_status_block_e1x)); | |
8326 | if (!bp->cnic_sb.e1x_sb) | |
8327 | goto alloc_mem_err; | |
8328 | } | |
8badd27a | 8329 | |
cd2b0389 | 8330 | if (CONFIGURE_NIC_MODE(bp) && !bp->t2) { |
16a5fd92 | 8331 | /* allocate searcher T2 table, as it wasn't allocated before */ |
cd2b0389 JP |
8332 | bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); |
8333 | if (!bp->t2) | |
8334 | goto alloc_mem_err; | |
8335 | } | |
55c11941 MS |
8336 | |
8337 | /* write address to which L5 should insert its values */ | |
8338 | bp->cnic_eth_dev.addr_drv_info_to_mcp = | |
8339 | &bp->slowpath->drv_info_to_mcp; | |
8340 | ||
8341 | if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) | |
8342 | goto alloc_mem_err; | |
8343 | ||
8344 | return 0; | |
8345 | ||
8346 | alloc_mem_err: | |
8347 | bnx2x_free_mem_cnic(bp); | |
8348 | BNX2X_ERR("Can't allocate memory\n"); | |
8349 | return -ENOMEM; | |
8350 | } | |
8351 | ||
8352 | int bnx2x_alloc_mem(struct bnx2x *bp) | |
8353 | { | |
8354 | int i, allocated, context_size; | |
a2fbb9ea | 8355 | |
cd2b0389 | 8356 | if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) { |
55c11941 | 8357 | /* allocate searcher T2 table */ |
cd2b0389 JP |
8358 | bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); |
8359 | if (!bp->t2) | |
8360 | goto alloc_mem_err; | |
8361 | } | |
8badd27a | 8362 | |
cd2b0389 JP |
8363 | bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping, |
8364 | sizeof(struct host_sp_status_block)); | |
8365 | if (!bp->def_status_blk) | |
8366 | goto alloc_mem_err; | |
a2fbb9ea | 8367 | |
cd2b0389 JP |
8368 | bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping, |
8369 | sizeof(struct bnx2x_slowpath)); | |
8370 | if (!bp->slowpath) | |
8371 | goto alloc_mem_err; | |
a2fbb9ea | 8372 | |
a052997e MS |
8373 | /* Allocate memory for CDU context: |
8374 | * This memory is allocated separately and not in the generic ILT | |
8375 | * functions because CDU differs in few aspects: | |
8376 | * 1. There are multiple entities allocating memory for context - | |
8377 | * 'regular' driver, CNIC and SRIOV driver. Each separately controls | |
8378 | * its own ILT lines. | |
8379 | * 2. Since CDU page-size is not a single 4KB page (which is the case | |
8380 | * for the other ILT clients), to be efficient we want to support | |
8381 | * allocation of sub-page-size in the last entry. | |
8382 | * 3. Context pointers are used by the driver to pass to FW / update | |
8383 | * the context (for the other ILT clients the pointers are used just to | |
8384 | * free the memory during unload). | |
8385 | */ | |
8386 | context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); | |
65abd74d | 8387 | |
a052997e MS |
8388 | for (i = 0, allocated = 0; allocated < context_size; i++) { |
8389 | bp->context[i].size = min(CDU_ILT_PAGE_SZ, | |
8390 | (context_size - allocated)); | |
cd2b0389 JP |
8391 | bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping, |
8392 | bp->context[i].size); | |
8393 | if (!bp->context[i].vcxt) | |
8394 | goto alloc_mem_err; | |
a052997e MS |
8395 | allocated += bp->context[i].size; |
8396 | } | |
cd2b0389 JP |
8397 | bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line), |
8398 | GFP_KERNEL); | |
8399 | if (!bp->ilt->lines) | |
8400 | goto alloc_mem_err; | |
65abd74d | 8401 | |
523224a3 DK |
8402 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
8403 | goto alloc_mem_err; | |
65abd74d | 8404 | |
67c431a5 AE |
8405 | if (bnx2x_iov_alloc_mem(bp)) |
8406 | goto alloc_mem_err; | |
8407 | ||
9f6c9258 | 8408 | /* Slow path ring */ |
cd2b0389 JP |
8409 | bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE); |
8410 | if (!bp->spq) | |
8411 | goto alloc_mem_err; | |
65abd74d | 8412 | |
523224a3 | 8413 | /* EQ */ |
cd2b0389 JP |
8414 | bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping, |
8415 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
8416 | if (!bp->eq_ring) | |
8417 | goto alloc_mem_err; | |
ab532cf3 | 8418 | |
9f6c9258 | 8419 | return 0; |
e1510706 | 8420 | |
9f6c9258 DK |
8421 | alloc_mem_err: |
8422 | bnx2x_free_mem(bp); | |
51c1a580 | 8423 | BNX2X_ERR("Can't allocate memory\n"); |
9f6c9258 | 8424 | return -ENOMEM; |
65abd74d YG |
8425 | } |
8426 | ||
a2fbb9ea ET |
8427 | /* |
8428 | * Init service functions | |
8429 | */ | |
a2fbb9ea | 8430 | |
619c5cb6 VZ |
8431 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
8432 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
8433 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 8434 | { |
619c5cb6 VZ |
8435 | int rc; |
8436 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 8437 | |
619c5cb6 | 8438 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 8439 | |
619c5cb6 VZ |
8440 | /* Fill general parameters */ |
8441 | ramrod_param.vlan_mac_obj = obj; | |
8442 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 8443 | |
619c5cb6 VZ |
8444 | /* Fill a user request section if needed */ |
8445 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
8446 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 8447 | |
619c5cb6 | 8448 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 8449 | |
619c5cb6 VZ |
8450 | /* Set the command: ADD or DEL */ |
8451 | if (set) | |
8452 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
8453 | else | |
8454 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
8455 | } |
8456 | ||
619c5cb6 | 8457 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7b5342d9 YM |
8458 | |
8459 | if (rc == -EEXIST) { | |
8460 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); | |
8461 | /* do not treat adding same MAC as error */ | |
8462 | rc = 0; | |
8463 | } else if (rc < 0) | |
619c5cb6 | 8464 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); |
7b5342d9 | 8465 | |
619c5cb6 | 8466 | return rc; |
a2fbb9ea ET |
8467 | } |
8468 | ||
05cc5a39 YM |
8469 | int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan, |
8470 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
8471 | unsigned long *ramrod_flags) | |
8472 | { | |
8473 | int rc; | |
8474 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
8475 | ||
8476 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
8477 | ||
8478 | /* Fill general parameters */ | |
8479 | ramrod_param.vlan_mac_obj = obj; | |
8480 | ramrod_param.ramrod_flags = *ramrod_flags; | |
8481 | ||
8482 | /* Fill a user request section if needed */ | |
8483 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
8484 | ramrod_param.user_req.u.vlan.vlan = vlan; | |
04f05230 | 8485 | __set_bit(BNX2X_VLAN, &ramrod_param.user_req.vlan_mac_flags); |
05cc5a39 YM |
8486 | /* Set the command: ADD or DEL */ |
8487 | if (set) | |
8488 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
8489 | else | |
8490 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
8491 | } | |
8492 | ||
8493 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); | |
8494 | ||
8495 | if (rc == -EEXIST) { | |
8496 | /* Do not treat adding same vlan as error. */ | |
8497 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); | |
8498 | rc = 0; | |
8499 | } else if (rc < 0) { | |
8500 | BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del")); | |
8501 | } | |
8502 | ||
8503 | return rc; | |
8504 | } | |
8505 | ||
4a4d2d37 MC |
8506 | void bnx2x_clear_vlan_info(struct bnx2x *bp) |
8507 | { | |
8508 | struct bnx2x_vlan_entry *vlan; | |
8509 | ||
8510 | /* Mark that hw forgot all entries */ | |
8511 | list_for_each_entry(vlan, &bp->vlan_reg, link) | |
8512 | vlan->hw = false; | |
8513 | ||
8514 | bp->vlan_cnt = 0; | |
8515 | } | |
8516 | ||
04f05230 SRK |
8517 | static int bnx2x_del_all_vlans(struct bnx2x *bp) |
8518 | { | |
8519 | struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj; | |
8520 | unsigned long ramrod_flags = 0, vlan_flags = 0; | |
04f05230 SRK |
8521 | int rc; |
8522 | ||
8523 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
8524 | __set_bit(BNX2X_VLAN, &vlan_flags); | |
8525 | rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags); | |
8526 | if (rc) | |
8527 | return rc; | |
8528 | ||
4a4d2d37 | 8529 | bnx2x_clear_vlan_info(bp); |
04f05230 SRK |
8530 | |
8531 | return 0; | |
8532 | } | |
8533 | ||
619c5cb6 VZ |
8534 | int bnx2x_del_all_macs(struct bnx2x *bp, |
8535 | struct bnx2x_vlan_mac_obj *mac_obj, | |
8536 | int mac_type, bool wait_for_comp) | |
e665bfda | 8537 | { |
619c5cb6 VZ |
8538 | int rc; |
8539 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 8540 | |
619c5cb6 VZ |
8541 | /* Wait for completion of requested */ |
8542 | if (wait_for_comp) | |
8543 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 8544 | |
619c5cb6 VZ |
8545 | /* Set the mac type of addresses we want to clear */ |
8546 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 8547 | |
619c5cb6 VZ |
8548 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
8549 | if (rc < 0) | |
8550 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 8551 | |
619c5cb6 | 8552 | return rc; |
0793f83f DK |
8553 | } |
8554 | ||
619c5cb6 | 8555 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 8556 | { |
f8f4f61a DK |
8557 | if (IS_PF(bp)) { |
8558 | unsigned long ramrod_flags = 0; | |
0793f83f | 8559 | |
f8f4f61a DK |
8560 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
8561 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
8562 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, | |
8563 | &bp->sp_objs->mac_obj, set, | |
8564 | BNX2X_ETH_MAC, &ramrod_flags); | |
8565 | } else { /* vf */ | |
8566 | return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, | |
bb9e9c1d | 8567 | bp->fp->index, set); |
f8f4f61a | 8568 | } |
e665bfda | 8569 | } |
6e30dd4e | 8570 | |
619c5cb6 | 8571 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 8572 | { |
60cad4e6 AE |
8573 | if (IS_PF(bp)) |
8574 | return bnx2x_setup_queue(bp, &bp->fp[0], true); | |
8575 | else /* VF */ | |
8576 | return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); | |
993ac7b5 | 8577 | } |
a2fbb9ea | 8578 | |
d6214d7a | 8579 | /** |
e8920674 | 8580 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 8581 | * |
e8920674 | 8582 | * @bp: driver handle |
d6214d7a | 8583 | * |
e8920674 | 8584 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 8585 | */ |
1ab4434c | 8586 | int bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 8587 | { |
1ab4434c AE |
8588 | int rc = 0; |
8589 | ||
60cad4e6 AE |
8590 | if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) { |
8591 | BNX2X_ERR("VF not loaded since interrupt mode not msix\n"); | |
1ab4434c | 8592 | return -EINVAL; |
60cad4e6 | 8593 | } |
1ab4434c | 8594 | |
9ee3d37b | 8595 | switch (int_mode) { |
1ab4434c AE |
8596 | case BNX2X_INT_MODE_MSIX: |
8597 | /* attempt to enable msix */ | |
8598 | rc = bnx2x_enable_msix(bp); | |
8599 | ||
8600 | /* msix attained */ | |
8601 | if (!rc) | |
8602 | return 0; | |
8603 | ||
8604 | /* vfs use only msix */ | |
8605 | if (rc && IS_VF(bp)) | |
8606 | return rc; | |
8607 | ||
8608 | /* failed to enable multiple MSI-X */ | |
8609 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", | |
8610 | bp->num_queues, | |
8611 | 1 + bp->num_cnic_queues); | |
8612 | ||
df561f66 | 8613 | fallthrough; |
1ab4434c | 8614 | case BNX2X_INT_MODE_MSI: |
d6214d7a | 8615 | bnx2x_enable_msi(bp); |
1ab4434c | 8616 | |
df561f66 | 8617 | fallthrough; |
1ab4434c | 8618 | case BNX2X_INT_MODE_INTX: |
55c11941 MS |
8619 | bp->num_ethernet_queues = 1; |
8620 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; | |
51c1a580 | 8621 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
ca00392c | 8622 | break; |
d6214d7a | 8623 | default: |
1ab4434c AE |
8624 | BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); |
8625 | return -EINVAL; | |
9f6c9258 | 8626 | } |
1ab4434c | 8627 | return 0; |
a2fbb9ea ET |
8628 | } |
8629 | ||
1ab4434c | 8630 | /* must be called prior to any HW initializations */ |
c2bff63f DK |
8631 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) |
8632 | { | |
290ca2bb AE |
8633 | if (IS_SRIOV(bp)) |
8634 | return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; | |
c2bff63f DK |
8635 | return L2_ILT_LINES(bp); |
8636 | } | |
8637 | ||
523224a3 DK |
8638 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
8639 | { | |
8640 | struct ilt_client_info *ilt_client; | |
8641 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
8642 | u16 line = 0; | |
8643 | ||
8644 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
8645 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
8646 | ||
8647 | /* CDU */ | |
8648 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
8649 | ilt_client->client_num = ILT_CLIENT_CDU; | |
8650 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
8651 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
8652 | ilt_client->start = line; | |
619c5cb6 | 8653 | line += bnx2x_cid_ilt_lines(bp); |
55c11941 MS |
8654 | |
8655 | if (CNIC_SUPPORT(bp)) | |
8656 | line += CNIC_ILT_LINES; | |
523224a3 DK |
8657 | ilt_client->end = line - 1; |
8658 | ||
51c1a580 | 8659 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
523224a3 DK |
8660 | ilt_client->start, |
8661 | ilt_client->end, | |
8662 | ilt_client->page_size, | |
8663 | ilt_client->flags, | |
8664 | ilog2(ilt_client->page_size >> 12)); | |
8665 | ||
8666 | /* QM */ | |
8667 | if (QM_INIT(bp->qm_cid_count)) { | |
8668 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
8669 | ilt_client->client_num = ILT_CLIENT_QM; | |
8670 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
8671 | ilt_client->flags = 0; | |
8672 | ilt_client->start = line; | |
8673 | ||
8674 | /* 4 bytes for each cid */ | |
8675 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
8676 | QM_ILT_PAGE_SZ); | |
8677 | ||
8678 | ilt_client->end = line - 1; | |
8679 | ||
51c1a580 MS |
8680 | DP(NETIF_MSG_IFUP, |
8681 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
8682 | ilt_client->start, |
8683 | ilt_client->end, | |
8684 | ilt_client->page_size, | |
8685 | ilt_client->flags, | |
8686 | ilog2(ilt_client->page_size >> 12)); | |
523224a3 | 8687 | } |
523224a3 | 8688 | |
55c11941 MS |
8689 | if (CNIC_SUPPORT(bp)) { |
8690 | /* SRC */ | |
8691 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
8692 | ilt_client->client_num = ILT_CLIENT_SRC; | |
8693 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
8694 | ilt_client->flags = 0; | |
8695 | ilt_client->start = line; | |
8696 | line += SRC_ILT_LINES; | |
8697 | ilt_client->end = line - 1; | |
523224a3 | 8698 | |
55c11941 MS |
8699 | DP(NETIF_MSG_IFUP, |
8700 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8701 | ilt_client->start, | |
8702 | ilt_client->end, | |
8703 | ilt_client->page_size, | |
8704 | ilt_client->flags, | |
8705 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 8706 | |
55c11941 MS |
8707 | /* TM */ |
8708 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
8709 | ilt_client->client_num = ILT_CLIENT_TM; | |
8710 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
8711 | ilt_client->flags = 0; | |
8712 | ilt_client->start = line; | |
8713 | line += TM_ILT_LINES; | |
8714 | ilt_client->end = line - 1; | |
523224a3 | 8715 | |
55c11941 MS |
8716 | DP(NETIF_MSG_IFUP, |
8717 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8718 | ilt_client->start, | |
8719 | ilt_client->end, | |
8720 | ilt_client->page_size, | |
8721 | ilt_client->flags, | |
8722 | ilog2(ilt_client->page_size >> 12)); | |
8723 | } | |
9f6c9258 | 8724 | |
619c5cb6 | 8725 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 8726 | } |
f85582f8 | 8727 | |
619c5cb6 VZ |
8728 | /** |
8729 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
8730 | * | |
8731 | * @bp: driver handle | |
8732 | * @fp: pointer to fastpath | |
8733 | * @init_params: pointer to parameters structure | |
8734 | * | |
8735 | * parameters configured: | |
8736 | * - HC configuration | |
8737 | * - Queue's CDU context | |
8738 | */ | |
1191cb83 | 8739 | static void bnx2x_pf_q_prep_init(struct bnx2x *bp, |
619c5cb6 | 8740 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) |
a2fbb9ea | 8741 | { |
6383c0b3 | 8742 | u8 cos; |
a052997e MS |
8743 | int cxt_index, cxt_offset; |
8744 | ||
619c5cb6 VZ |
8745 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
8746 | if (!IS_FCOE_FP(fp)) { | |
8747 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
8748 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
8749 | ||
16a5fd92 | 8750 | /* If HC is supported, enable host coalescing in the transition |
619c5cb6 VZ |
8751 | * to INIT state. |
8752 | */ | |
8753 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
8754 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
8755 | ||
8756 | /* HC rate */ | |
8757 | init_params->rx.hc_rate = bp->rx_ticks ? | |
8758 | (1000000 / bp->rx_ticks) : 0; | |
8759 | init_params->tx.hc_rate = bp->tx_ticks ? | |
8760 | (1000000 / bp->tx_ticks) : 0; | |
8761 | ||
8762 | /* FW SB ID */ | |
8763 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
8764 | fp->fw_sb_id; | |
8765 | ||
8766 | /* | |
8767 | * CQ index among the SB indices: FCoE clients uses the default | |
8768 | * SB, therefore it's different. | |
8769 | */ | |
6383c0b3 AE |
8770 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
8771 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
8772 | } |
8773 | ||
6383c0b3 AE |
8774 | /* set maximum number of COSs supported by this queue */ |
8775 | init_params->max_cos = fp->max_cos; | |
8776 | ||
51c1a580 | 8777 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
8778 | fp->index, init_params->max_cos); |
8779 | ||
8780 | /* set the context pointers queue object */ | |
a052997e | 8781 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { |
65565884 MS |
8782 | cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; |
8783 | cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * | |
a052997e | 8784 | ILT_PAGE_CIDS); |
6383c0b3 | 8785 | init_params->cxts[cos] = |
a052997e MS |
8786 | &bp->context[cxt_index].vcxt[cxt_offset].eth; |
8787 | } | |
619c5cb6 VZ |
8788 | } |
8789 | ||
910cc727 | 8790 | static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
6383c0b3 AE |
8791 | struct bnx2x_queue_state_params *q_params, |
8792 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
8793 | int tx_index, bool leading) | |
8794 | { | |
8795 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
8796 | ||
8797 | /* Set the command */ | |
8798 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
8799 | ||
8800 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
8801 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
8802 | ||
8803 | /* choose the index of the cid to send the slow path on */ | |
8804 | tx_only_params->cid_index = tx_index; | |
8805 | ||
8806 | /* Set general TX_ONLY_SETUP parameters */ | |
8807 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
8808 | ||
8809 | /* Set Tx TX_ONLY_SETUP parameters */ | |
8810 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
8811 | ||
51c1a580 MS |
8812 | DP(NETIF_MSG_IFUP, |
8813 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", | |
6383c0b3 AE |
8814 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
8815 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
8816 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
8817 | ||
8818 | /* send the ramrod */ | |
8819 | return bnx2x_queue_state_change(bp, q_params); | |
8820 | } | |
8821 | ||
619c5cb6 VZ |
8822 | /** |
8823 | * bnx2x_setup_queue - setup queue | |
8824 | * | |
8825 | * @bp: driver handle | |
8826 | * @fp: pointer to fastpath | |
8827 | * @leading: is leading | |
8828 | * | |
8829 | * This function performs 2 steps in a Queue state machine | |
8830 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
8831 | */ | |
8832 | ||
8833 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
8834 | bool leading) | |
8835 | { | |
3b603066 | 8836 | struct bnx2x_queue_state_params q_params = {NULL}; |
619c5cb6 VZ |
8837 | struct bnx2x_queue_setup_params *setup_params = |
8838 | &q_params.params.setup; | |
6383c0b3 AE |
8839 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
8840 | &q_params.params.tx_only; | |
a2fbb9ea | 8841 | int rc; |
6383c0b3 AE |
8842 | u8 tx_index; |
8843 | ||
51c1a580 | 8844 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 8845 | |
ec6ba945 VZ |
8846 | /* reset IGU state skip FCoE L2 queue */ |
8847 | if (!IS_FCOE_FP(fp)) | |
8848 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 8849 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 8850 | |
15192a8c | 8851 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8852 | /* We want to wait for completion in this context */ |
8853 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8854 | |
619c5cb6 VZ |
8855 | /* Prepare the INIT parameters */ |
8856 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 8857 | |
619c5cb6 VZ |
8858 | /* Set the command */ |
8859 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
8860 | ||
8861 | /* Change the state to INIT */ | |
8862 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8863 | if (rc) { | |
6383c0b3 | 8864 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
8865 | return rc; |
8866 | } | |
ec6ba945 | 8867 | |
51c1a580 | 8868 | DP(NETIF_MSG_IFUP, "init complete\n"); |
6383c0b3 | 8869 | |
619c5cb6 VZ |
8870 | /* Now move the Queue to the SETUP state... */ |
8871 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 8872 | |
619c5cb6 VZ |
8873 | /* Set QUEUE flags */ |
8874 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 8875 | |
619c5cb6 | 8876 | /* Set general SETUP parameters */ |
6383c0b3 AE |
8877 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
8878 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 8879 | |
6383c0b3 | 8880 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
8881 | &setup_params->rxq_params); |
8882 | ||
6383c0b3 AE |
8883 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
8884 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
8885 | |
8886 | /* Set the command */ | |
8887 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
8888 | ||
55c11941 MS |
8889 | if (IS_FCOE_FP(fp)) |
8890 | bp->fcoe_init = true; | |
8891 | ||
619c5cb6 VZ |
8892 | /* Change the state to SETUP */ |
8893 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
8894 | if (rc) { |
8895 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
8896 | return rc; | |
8897 | } | |
8898 | ||
8899 | /* loop through the relevant tx-only indices */ | |
8900 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8901 | tx_index < fp->max_cos; | |
8902 | tx_index++) { | |
8903 | ||
8904 | /* prepare and send tx-only ramrod*/ | |
8905 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
8906 | tx_only_params, tx_index, leading); | |
8907 | if (rc) { | |
8908 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
8909 | fp->index, tx_index); | |
8910 | return rc; | |
8911 | } | |
8912 | } | |
523224a3 | 8913 | |
34f80b04 | 8914 | return rc; |
a2fbb9ea ET |
8915 | } |
8916 | ||
619c5cb6 | 8917 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 8918 | { |
619c5cb6 | 8919 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 8920 | struct bnx2x_fp_txdata *txdata; |
3b603066 | 8921 | struct bnx2x_queue_state_params q_params = {NULL}; |
6383c0b3 AE |
8922 | int rc, tx_index; |
8923 | ||
51c1a580 | 8924 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 8925 | |
15192a8c | 8926 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8927 | /* We want to wait for completion in this context */ |
8928 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8929 | |
6383c0b3 AE |
8930 | /* close tx-only connections */ |
8931 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8932 | tx_index < fp->max_cos; | |
8933 | tx_index++){ | |
8934 | ||
8935 | /* ascertain this is a normal queue*/ | |
65565884 | 8936 | txdata = fp->txdata_ptr[tx_index]; |
6383c0b3 | 8937 | |
51c1a580 | 8938 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
6383c0b3 AE |
8939 | txdata->txq_index); |
8940 | ||
8941 | /* send halt terminate on tx-only connection */ | |
8942 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
8943 | memset(&q_params.params.terminate, 0, | |
8944 | sizeof(q_params.params.terminate)); | |
8945 | q_params.params.terminate.cid_index = tx_index; | |
8946 | ||
8947 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8948 | if (rc) | |
8949 | return rc; | |
8950 | ||
8951 | /* send halt terminate on tx-only connection */ | |
8952 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
8953 | memset(&q_params.params.cfc_del, 0, | |
8954 | sizeof(q_params.params.cfc_del)); | |
8955 | q_params.params.cfc_del.cid_index = tx_index; | |
8956 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8957 | if (rc) | |
8958 | return rc; | |
8959 | } | |
8960 | /* Stop the primary connection: */ | |
8961 | /* ...halt the connection */ | |
619c5cb6 VZ |
8962 | q_params.cmd = BNX2X_Q_CMD_HALT; |
8963 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8964 | if (rc) | |
da5a662a | 8965 | return rc; |
a2fbb9ea | 8966 | |
6383c0b3 | 8967 | /* ...terminate the connection */ |
619c5cb6 | 8968 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
8969 | memset(&q_params.params.terminate, 0, |
8970 | sizeof(q_params.params.terminate)); | |
8971 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
8972 | rc = bnx2x_queue_state_change(bp, &q_params); |
8973 | if (rc) | |
523224a3 | 8974 | return rc; |
6383c0b3 | 8975 | /* ...delete cfc entry */ |
619c5cb6 | 8976 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
8977 | memset(&q_params.params.cfc_del, 0, |
8978 | sizeof(q_params.params.cfc_del)); | |
8979 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 8980 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
8981 | } |
8982 | ||
34f80b04 EG |
8983 | static void bnx2x_reset_func(struct bnx2x *bp) |
8984 | { | |
8985 | int port = BP_PORT(bp); | |
8986 | int func = BP_FUNC(bp); | |
f2e0899f | 8987 | int i; |
523224a3 DK |
8988 | |
8989 | /* Disable the function in the FW */ | |
8990 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
8991 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
8992 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
8993 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
8994 | ||
8995 | /* FP SBs */ | |
ec6ba945 | 8996 | for_each_eth_queue(bp, i) { |
523224a3 | 8997 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 8998 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8999 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
9000 | SB_DISABLED); | |
523224a3 DK |
9001 | } |
9002 | ||
55c11941 MS |
9003 | if (CNIC_LOADED(bp)) |
9004 | /* CNIC SB */ | |
9005 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
9006 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET | |
9007 | (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); | |
9008 | ||
523224a3 | 9009 | /* SP SB */ |
619c5cb6 | 9010 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
2de67439 YM |
9011 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
9012 | SB_DISABLED); | |
523224a3 DK |
9013 | |
9014 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
9015 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
9016 | 0); | |
34f80b04 EG |
9017 | |
9018 | /* Configure IGU */ | |
f2e0899f DK |
9019 | if (bp->common.int_block == INT_BLOCK_HC) { |
9020 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
9021 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
9022 | } else { | |
9023 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
9024 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
9025 | } | |
34f80b04 | 9026 | |
55c11941 MS |
9027 | if (CNIC_LOADED(bp)) { |
9028 | /* Disable Timer scan */ | |
9029 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
9030 | /* | |
9031 | * Wait for at least 10ms and up to 2 second for the timers | |
9032 | * scan to complete | |
9033 | */ | |
9034 | for (i = 0; i < 200; i++) { | |
639d65b8 | 9035 | usleep_range(10000, 20000); |
55c11941 MS |
9036 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) |
9037 | break; | |
9038 | } | |
37b091ba | 9039 | } |
34f80b04 | 9040 | /* Clear ILT */ |
f2e0899f DK |
9041 | bnx2x_clear_func_ilt(bp, func); |
9042 | ||
9043 | /* Timers workaround bug for E2: if this is vnic-3, | |
9044 | * we need to set the entire ilt range for this timers. | |
9045 | */ | |
619c5cb6 | 9046 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
9047 | struct ilt_client_info ilt_cli; |
9048 | /* use dummy TM client */ | |
9049 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
9050 | ilt_cli.start = 0; | |
9051 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
9052 | ilt_cli.client_num = ILT_CLIENT_TM; | |
9053 | ||
9054 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
9055 | } | |
9056 | ||
9057 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 9058 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 9059 | bnx2x_pf_disable(bp); |
523224a3 DK |
9060 | |
9061 | bp->dmae_ready = 0; | |
34f80b04 EG |
9062 | } |
9063 | ||
9064 | static void bnx2x_reset_port(struct bnx2x *bp) | |
9065 | { | |
9066 | int port = BP_PORT(bp); | |
9067 | u32 val; | |
9068 | ||
619c5cb6 VZ |
9069 | /* Reset physical Link */ |
9070 | bnx2x__link_reset(bp); | |
9071 | ||
34f80b04 EG |
9072 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
9073 | ||
9074 | /* Do not rcv packets to BRB */ | |
9075 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
9076 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
9077 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
9078 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
9079 | ||
9080 | /* Configure AEU */ | |
9081 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
9082 | ||
9083 | msleep(100); | |
9084 | /* Check for BRB port occupancy */ | |
9085 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
9086 | if (val) | |
9087 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 9088 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
9089 | |
9090 | /* TODO: Close Doorbell port? */ | |
9091 | } | |
9092 | ||
1191cb83 | 9093 | static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 9094 | { |
3b603066 | 9095 | struct bnx2x_func_state_params func_params = {NULL}; |
34f80b04 | 9096 | |
619c5cb6 VZ |
9097 | /* Prepare parameters for function state transitions */ |
9098 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 9099 | |
619c5cb6 VZ |
9100 | func_params.f_obj = &bp->func_obj; |
9101 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 9102 | |
619c5cb6 | 9103 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 9104 | |
619c5cb6 | 9105 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
9106 | } |
9107 | ||
1191cb83 | 9108 | static int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 9109 | { |
3b603066 | 9110 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 | 9111 | int rc; |
228241eb | 9112 | |
619c5cb6 VZ |
9113 | /* Prepare parameters for function state transitions */ |
9114 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
9115 | func_params.f_obj = &bp->func_obj; | |
9116 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 9117 | |
619c5cb6 VZ |
9118 | /* |
9119 | * Try to stop the function the 'good way'. If fails (in case | |
9120 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
9121 | * not in a debug mode, perform a state transaction in order to | |
9122 | * enable further HW_RESET transaction. | |
9123 | */ | |
9124 | rc = bnx2x_func_state_change(bp, &func_params); | |
9125 | if (rc) { | |
34f80b04 | 9126 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 9127 | return rc; |
34f80b04 | 9128 | #else |
51c1a580 | 9129 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
619c5cb6 VZ |
9130 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
9131 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 9132 | #endif |
228241eb | 9133 | } |
a2fbb9ea | 9134 | |
619c5cb6 VZ |
9135 | return 0; |
9136 | } | |
523224a3 | 9137 | |
619c5cb6 VZ |
9138 | /** |
9139 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
9140 | * | |
9141 | * @bp: driver handle | |
9142 | * @unload_mode: requested function's unload mode | |
9143 | * | |
9144 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
9145 | */ | |
9146 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
9147 | { | |
9148 | u32 reset_code = 0; | |
9149 | int port = BP_PORT(bp); | |
3101c2bc | 9150 | |
619c5cb6 | 9151 | /* Select the UNLOAD request mode */ |
65abd74d YG |
9152 | if (unload_mode == UNLOAD_NORMAL) |
9153 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
9154 | ||
7d0446c2 | 9155 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 9156 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 9157 | |
7d0446c2 | 9158 | else if (bp->wol) { |
65abd74d YG |
9159 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
9160 | u8 *mac_addr = bp->dev->dev_addr; | |
29ed74c3 | 9161 | struct pci_dev *pdev = bp->pdev; |
65abd74d | 9162 | u32 val; |
f9977903 DK |
9163 | u16 pmc; |
9164 | ||
65abd74d | 9165 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
9166 | * preserve entry 0 which is used by the PMF |
9167 | */ | |
3395a033 | 9168 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
9169 | |
9170 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
9171 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
9172 | ||
9173 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
9174 | (mac_addr[4] << 8) | mac_addr[5]; | |
9175 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
9176 | ||
f9977903 | 9177 | /* Enable the PME and clear the status */ |
29ed74c3 | 9178 | pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc); |
f9977903 | 9179 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; |
29ed74c3 | 9180 | pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc); |
f9977903 | 9181 | |
65abd74d YG |
9182 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
9183 | ||
9184 | } else | |
9185 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 9186 | |
619c5cb6 VZ |
9187 | /* Send the request to the MCP */ |
9188 | if (!BP_NOMCP(bp)) | |
9189 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
9190 | else { | |
9191 | int path = BP_PATH(bp); | |
9192 | ||
51c1a580 | 9193 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
a8f47eb7 | 9194 | path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], |
9195 | bnx2x_load_count[path][2]); | |
9196 | bnx2x_load_count[path][0]--; | |
9197 | bnx2x_load_count[path][1 + port]--; | |
51c1a580 | 9198 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
a8f47eb7 | 9199 | path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], |
9200 | bnx2x_load_count[path][2]); | |
9201 | if (bnx2x_load_count[path][0] == 0) | |
619c5cb6 | 9202 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; |
a8f47eb7 | 9203 | else if (bnx2x_load_count[path][1 + port] == 0) |
619c5cb6 VZ |
9204 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; |
9205 | else | |
9206 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
9207 | } | |
9208 | ||
9209 | return reset_code; | |
9210 | } | |
9211 | ||
9212 | /** | |
9213 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
9214 | * | |
9215 | * @bp: driver handle | |
5d07d868 | 9216 | * @keep_link: true iff link should be kept up |
619c5cb6 | 9217 | */ |
5d07d868 | 9218 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) |
619c5cb6 | 9219 | { |
5d07d868 YM |
9220 | u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; |
9221 | ||
619c5cb6 VZ |
9222 | /* Report UNLOAD_DONE to MCP */ |
9223 | if (!BP_NOMCP(bp)) | |
5d07d868 | 9224 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); |
619c5cb6 VZ |
9225 | } |
9226 | ||
1191cb83 | 9227 | static int bnx2x_func_wait_started(struct bnx2x *bp) |
6debea87 DK |
9228 | { |
9229 | int tout = 50; | |
9230 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
9231 | ||
9232 | if (!bp->port.pmf) | |
9233 | return 0; | |
9234 | ||
9235 | /* | |
9236 | * (assumption: No Attention from MCP at this stage) | |
16a5fd92 | 9237 | * PMF probably in the middle of TX disable/enable transaction |
6debea87 | 9238 | * 1. Sync IRS for default SB |
16a5fd92 YM |
9239 | * 2. Sync SP queue - this guarantees us that attention handling started |
9240 | * 3. Wait, that TX disable/enable transaction completes | |
6debea87 | 9241 | * |
16a5fd92 YM |
9242 | * 1+2 guarantee that if DCBx attention was scheduled it already changed |
9243 | * pending bit of transaction from STARTED-->TX_STOPPED, if we already | |
9244 | * received completion for the transaction the state is TX_STOPPED. | |
6debea87 DK |
9245 | * State will return to STARTED after completion of TX_STOPPED-->STARTED |
9246 | * transaction. | |
9247 | */ | |
9248 | ||
9249 | /* make sure default SB ISR is done */ | |
9250 | if (msix) | |
9251 | synchronize_irq(bp->msix_table[0].vector); | |
9252 | else | |
9253 | synchronize_irq(bp->pdev->irq); | |
9254 | ||
9255 | flush_workqueue(bnx2x_wq); | |
370d4a26 | 9256 | flush_workqueue(bnx2x_iov_wq); |
6debea87 DK |
9257 | |
9258 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
9259 | BNX2X_F_STATE_STARTED && tout--) | |
9260 | msleep(20); | |
9261 | ||
9262 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
9263 | BNX2X_F_STATE_STARTED) { | |
9264 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 9265 | BNX2X_ERR("Wrong function state\n"); |
6debea87 DK |
9266 | return -EBUSY; |
9267 | #else | |
9268 | /* | |
9269 | * Failed to complete the transaction in a "good way" | |
9270 | * Force both transactions with CLR bit | |
9271 | */ | |
3b603066 | 9272 | struct bnx2x_func_state_params func_params = {NULL}; |
6debea87 | 9273 | |
51c1a580 | 9274 | DP(NETIF_MSG_IFDOWN, |
0c23ad37 | 9275 | "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n"); |
6debea87 DK |
9276 | |
9277 | func_params.f_obj = &bp->func_obj; | |
9278 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
9279 | &func_params.ramrod_flags); | |
9280 | ||
9281 | /* STARTED-->TX_ST0PPED */ | |
9282 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
9283 | bnx2x_func_state_change(bp, &func_params); | |
9284 | ||
9285 | /* TX_ST0PPED-->STARTED */ | |
9286 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
9287 | return bnx2x_func_state_change(bp, &func_params); | |
9288 | #endif | |
9289 | } | |
9290 | ||
9291 | return 0; | |
9292 | } | |
9293 | ||
eeed018c MK |
9294 | static void bnx2x_disable_ptp(struct bnx2x *bp) |
9295 | { | |
9296 | int port = BP_PORT(bp); | |
9297 | ||
9298 | /* Disable sending PTP packets to host */ | |
9299 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : | |
9300 | NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); | |
9301 | ||
9302 | /* Reset PTP event detection rules */ | |
9303 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
9304 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); | |
9305 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
9306 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); | |
9307 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : | |
9308 | NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); | |
9309 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : | |
9310 | NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); | |
9311 | ||
9312 | /* Disable the PTP feature */ | |
9313 | REG_WR(bp, port ? NIG_REG_P1_PTP_EN : | |
9314 | NIG_REG_P0_PTP_EN, 0x0); | |
9315 | } | |
9316 | ||
9317 | /* Called during unload, to stop PTP-related stuff */ | |
1444c301 | 9318 | static void bnx2x_stop_ptp(struct bnx2x *bp) |
eeed018c MK |
9319 | { |
9320 | /* Cancel PTP work queue. Should be done after the Tx queues are | |
9321 | * drained to prevent additional scheduling. | |
9322 | */ | |
9323 | cancel_work_sync(&bp->ptp_task); | |
9324 | ||
9325 | if (bp->ptp_tx_skb) { | |
9326 | dev_kfree_skb_any(bp->ptp_tx_skb); | |
9327 | bp->ptp_tx_skb = NULL; | |
9328 | } | |
9329 | ||
9330 | /* Disable PTP in HW */ | |
9331 | bnx2x_disable_ptp(bp); | |
9332 | ||
9333 | DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n"); | |
9334 | } | |
9335 | ||
5d07d868 | 9336 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) |
619c5cb6 VZ |
9337 | { |
9338 | int port = BP_PORT(bp); | |
6383c0b3 AE |
9339 | int i, rc = 0; |
9340 | u8 cos; | |
3b603066 | 9341 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 VZ |
9342 | u32 reset_code; |
9343 | ||
9344 | /* Wait until tx fastpath tasks complete */ | |
9345 | for_each_tx_queue(bp, i) { | |
9346 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
9347 | ||
6383c0b3 | 9348 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 9349 | rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); |
619c5cb6 VZ |
9350 | #ifdef BNX2X_STOP_ON_ERROR |
9351 | if (rc) | |
9352 | return; | |
9353 | #endif | |
9354 | } | |
9355 | ||
9356 | /* Give HW time to discard old tx messages */ | |
0926d499 | 9357 | usleep_range(1000, 2000); |
619c5cb6 VZ |
9358 | |
9359 | /* Clean all ETH MACs */ | |
15192a8c BW |
9360 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, |
9361 | false); | |
619c5cb6 VZ |
9362 | if (rc < 0) |
9363 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
9364 | ||
9365 | /* Clean up UC list */ | |
15192a8c | 9366 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, |
619c5cb6 VZ |
9367 | true); |
9368 | if (rc < 0) | |
51c1a580 MS |
9369 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
9370 | rc); | |
619c5cb6 | 9371 | |
38355a5f IM |
9372 | /* The whole *vlan_obj structure may be not initialized if VLAN |
9373 | * filtering offload is not supported by hardware. Currently this is | |
9374 | * true for all hardware covered by CHIP_IS_E1x(). | |
9375 | */ | |
9376 | if (!CHIP_IS_E1x(bp)) { | |
9377 | /* Remove all currently configured VLANs */ | |
9378 | rc = bnx2x_del_all_vlans(bp); | |
9379 | if (rc < 0) | |
9380 | BNX2X_ERR("Failed to delete all VLANs\n"); | |
9381 | } | |
04f05230 | 9382 | |
619c5cb6 VZ |
9383 | /* Disable LLH */ |
9384 | if (!CHIP_IS_E1(bp)) | |
9385 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
9386 | ||
9387 | /* Set "drop all" (stop Rx). | |
9388 | * We need to take a netif_addr_lock() here in order to prevent | |
9389 | * a race between the completion code and this code. | |
9390 | */ | |
9391 | netif_addr_lock_bh(bp->dev); | |
9392 | /* Schedule the rx_mode command */ | |
9393 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
9394 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
442866ff | 9395 | else if (bp->slowpath) |
619c5cb6 VZ |
9396 | bnx2x_set_storm_rx_mode(bp); |
9397 | ||
9398 | /* Cleanup multicast configuration */ | |
9399 | rparam.mcast_obj = &bp->mcast_obj; | |
9400 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
9401 | if (rc < 0) | |
9402 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
9403 | ||
9404 | netif_addr_unlock_bh(bp->dev); | |
9405 | ||
f1929b01 | 9406 | bnx2x_iov_chip_cleanup(bp); |
619c5cb6 | 9407 | |
6debea87 DK |
9408 | /* |
9409 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
9410 | * this function should perform FUNC, PORT or COMMON HW | |
9411 | * reset. | |
9412 | */ | |
9413 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
9414 | ||
9415 | /* | |
9416 | * (assumption: No Attention from MCP at this stage) | |
16a5fd92 | 9417 | * PMF probably in the middle of TX disable/enable transaction |
6debea87 DK |
9418 | */ |
9419 | rc = bnx2x_func_wait_started(bp); | |
9420 | if (rc) { | |
9421 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
9422 | #ifdef BNX2X_STOP_ON_ERROR | |
9423 | return; | |
9424 | #endif | |
9425 | } | |
9426 | ||
34f80b04 | 9427 | /* Close multi and leading connections |
619c5cb6 VZ |
9428 | * Completions for ramrods are collected in a synchronous way |
9429 | */ | |
55c11941 | 9430 | for_each_eth_queue(bp, i) |
619c5cb6 | 9431 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
9432 | #ifdef BNX2X_STOP_ON_ERROR |
9433 | return; | |
9434 | #else | |
228241eb | 9435 | goto unload_error; |
523224a3 | 9436 | #endif |
55c11941 MS |
9437 | |
9438 | if (CNIC_LOADED(bp)) { | |
9439 | for_each_cnic_queue(bp, i) | |
9440 | if (bnx2x_stop_queue(bp, i)) | |
9441 | #ifdef BNX2X_STOP_ON_ERROR | |
9442 | return; | |
9443 | #else | |
9444 | goto unload_error; | |
9445 | #endif | |
9446 | } | |
9447 | ||
619c5cb6 VZ |
9448 | /* If SP settings didn't get completed so far - something |
9449 | * very wrong has happen. | |
9450 | */ | |
9451 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
9452 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 9453 | |
619c5cb6 VZ |
9454 | #ifndef BNX2X_STOP_ON_ERROR |
9455 | unload_error: | |
9456 | #endif | |
523224a3 | 9457 | rc = bnx2x_func_stop(bp); |
da5a662a | 9458 | if (rc) { |
523224a3 | 9459 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 9460 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 9461 | return; |
523224a3 | 9462 | #endif |
34f80b04 | 9463 | } |
a2fbb9ea | 9464 | |
eeed018c MK |
9465 | /* stop_ptp should be after the Tx queues are drained to prevent |
9466 | * scheduling to the cancelled PTP work queue. It should also be after | |
9467 | * function stop ramrod is sent, since as part of this ramrod FW access | |
9468 | * PTP registers. | |
9469 | */ | |
07f12622 | 9470 | if (bp->flags & PTP_SUPPORTED) { |
d53c66a5 | 9471 | bnx2x_stop_ptp(bp); |
07f12622 SRK |
9472 | if (bp->ptp_clock) { |
9473 | ptp_clock_unregister(bp->ptp_clock); | |
9474 | bp->ptp_clock = NULL; | |
9475 | } | |
9476 | } | |
eeed018c | 9477 | |
523224a3 DK |
9478 | /* Disable HW interrupts, NAPI */ |
9479 | bnx2x_netif_stop(bp, 1); | |
26614ba5 MS |
9480 | /* Delete all NAPI objects */ |
9481 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
9482 | if (CNIC_LOADED(bp)) |
9483 | bnx2x_del_all_napi_cnic(bp); | |
523224a3 DK |
9484 | |
9485 | /* Release IRQs */ | |
d6214d7a | 9486 | bnx2x_free_irq(bp); |
523224a3 | 9487 | |
b44e108b GP |
9488 | /* Reset the chip, unless PCI function is offline. If we reach this |
9489 | * point following a PCI error handling, it means device is really | |
9490 | * in a bad state and we're about to remove it, so reset the chip | |
9491 | * is not a good idea. | |
9492 | */ | |
9493 | if (!pci_channel_offline(bp->pdev)) { | |
9494 | rc = bnx2x_reset_hw(bp, reset_code); | |
9495 | if (rc) | |
9496 | BNX2X_ERR("HW_RESET failed\n"); | |
9497 | } | |
a2fbb9ea | 9498 | |
619c5cb6 | 9499 | /* Report UNLOAD_DONE to MCP */ |
5d07d868 | 9500 | bnx2x_send_unload_done(bp, keep_link); |
72fd0718 VZ |
9501 | } |
9502 | ||
9f6c9258 | 9503 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
9504 | { |
9505 | u32 val; | |
9506 | ||
51c1a580 | 9507 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
72fd0718 VZ |
9508 | |
9509 | if (CHIP_IS_E1(bp)) { | |
9510 | int port = BP_PORT(bp); | |
9511 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
9512 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
9513 | ||
9514 | val = REG_RD(bp, addr); | |
9515 | val &= ~(0x300); | |
9516 | REG_WR(bp, addr, val); | |
619c5cb6 | 9517 | } else { |
72fd0718 VZ |
9518 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
9519 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
9520 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
9521 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
9522 | } | |
9523 | } | |
9524 | ||
72fd0718 VZ |
9525 | /* Close gates #2, #3 and #4: */ |
9526 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
9527 | { | |
c9ee9206 | 9528 | u32 val; |
72fd0718 VZ |
9529 | |
9530 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
9531 | if (!CHIP_IS_E1(bp)) { | |
9532 | /* #4 */ | |
c9ee9206 | 9533 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 9534 | /* #2 */ |
c9ee9206 | 9535 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
9536 | } |
9537 | ||
9538 | /* #3 */ | |
c9ee9206 VZ |
9539 | if (CHIP_IS_E1x(bp)) { |
9540 | /* Prevent interrupts from HC on both ports */ | |
9541 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
9542 | REG_WR(bp, HC_REG_CONFIG_1, | |
9543 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
9544 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
9545 | ||
9546 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
9547 | REG_WR(bp, HC_REG_CONFIG_0, | |
9548 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
9549 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
9550 | } else { | |
d82603c6 | 9551 | /* Prevent incoming interrupts in IGU */ |
c9ee9206 VZ |
9552 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
9553 | ||
9554 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
9555 | (!close) ? | |
9556 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
9557 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
9558 | } | |
72fd0718 | 9559 | |
51c1a580 | 9560 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
72fd0718 | 9561 | close ? "closing" : "opening"); |
72fd0718 VZ |
9562 | } |
9563 | ||
9564 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
9565 | ||
9566 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
9567 | { | |
9568 | /* Do some magic... */ | |
9569 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
9570 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
9571 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
9572 | } | |
9573 | ||
e8920674 DK |
9574 | /** |
9575 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 9576 | * |
e8920674 DK |
9577 | * @bp: driver handle |
9578 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
9579 | */ |
9580 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
9581 | { | |
9582 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
9583 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
9584 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
9585 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
9586 | } | |
9587 | ||
f85582f8 | 9588 | /** |
e8920674 | 9589 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 9590 | * |
e8920674 DK |
9591 | * @bp: driver handle |
9592 | * @magic_val: old value of 'magic' bit. | |
9593 | * | |
9594 | * Takes care of CLP configurations. | |
72fd0718 VZ |
9595 | */ |
9596 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
9597 | { | |
9598 | u32 shmem; | |
9599 | u32 validity_offset; | |
9600 | ||
51c1a580 | 9601 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
72fd0718 VZ |
9602 | |
9603 | /* Set `magic' bit in order to save MF config */ | |
9604 | if (!CHIP_IS_E1(bp)) | |
9605 | bnx2x_clp_reset_prep(bp, magic_val); | |
9606 | ||
9607 | /* Get shmem offset */ | |
9608 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
c55e771b BW |
9609 | validity_offset = |
9610 | offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); | |
72fd0718 VZ |
9611 | |
9612 | /* Clear validity map flags */ | |
9613 | if (shmem > 0) | |
9614 | REG_WR(bp, shmem + validity_offset, 0); | |
9615 | } | |
9616 | ||
9617 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
9618 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
9619 | ||
e8920674 DK |
9620 | /** |
9621 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 9622 | * |
e8920674 | 9623 | * @bp: driver handle |
72fd0718 | 9624 | */ |
1191cb83 | 9625 | static void bnx2x_mcp_wait_one(struct bnx2x *bp) |
72fd0718 VZ |
9626 | { |
9627 | /* special handling for emulation and FPGA, | |
9628 | wait 10 times longer */ | |
9629 | if (CHIP_REV_IS_SLOW(bp)) | |
9630 | msleep(MCP_ONE_TIMEOUT*10); | |
9631 | else | |
9632 | msleep(MCP_ONE_TIMEOUT); | |
9633 | } | |
9634 | ||
1b6e2ceb DK |
9635 | /* |
9636 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
9637 | */ | |
9638 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 9639 | { |
1b6e2ceb DK |
9640 | int cnt = 0; |
9641 | u32 val = 0; | |
72fd0718 | 9642 | |
1b6e2ceb DK |
9643 | do { |
9644 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
f7084059 GP |
9645 | |
9646 | /* If we read all 0xFFs, means we are in PCI error state and | |
9647 | * should bail out to avoid crashes on adapter's FW reads. | |
9648 | */ | |
9649 | if (bp->common.shmem_base == 0xFFFFFFFF) { | |
9650 | bp->flags |= NO_MCP_FLAG; | |
9651 | return -ENODEV; | |
9652 | } | |
9653 | ||
1b6e2ceb DK |
9654 | if (bp->common.shmem_base) { |
9655 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
9656 | if (val & SHR_MEM_VALIDITY_MB) | |
9657 | return 0; | |
9658 | } | |
72fd0718 | 9659 | |
1b6e2ceb | 9660 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 9661 | |
1b6e2ceb | 9662 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 9663 | |
1b6e2ceb | 9664 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 9665 | |
1b6e2ceb DK |
9666 | return -ENODEV; |
9667 | } | |
72fd0718 | 9668 | |
1b6e2ceb DK |
9669 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
9670 | { | |
9671 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 9672 | |
72fd0718 VZ |
9673 | /* Restore the `magic' bit value */ |
9674 | if (!CHIP_IS_E1(bp)) | |
9675 | bnx2x_clp_reset_done(bp, magic_val); | |
9676 | ||
9677 | return rc; | |
9678 | } | |
9679 | ||
9680 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
9681 | { | |
9682 | if (!CHIP_IS_E1(bp)) { | |
9683 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
9684 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
9685 | } |
9686 | } | |
9687 | ||
9688 | /* | |
9689 | * Reset the whole chip except for: | |
9690 | * - PCIE core | |
9691 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
9692 | * one reset bit) | |
9693 | * - IGU | |
9694 | * - MISC (including AEU) | |
9695 | * - GRC | |
9696 | * - RBCN, RBCP | |
9697 | */ | |
c9ee9206 | 9698 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
9699 | { |
9700 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 9701 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
9702 | |
9703 | /* | |
9704 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
9705 | * (per chip) blocks. | |
9706 | */ | |
9707 | global_bits2 = | |
9708 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
9709 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 9710 | |
c55e771b BW |
9711 | /* Don't reset the following blocks. |
9712 | * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be | |
9713 | * reset, as in 4 port device they might still be owned | |
9714 | * by the MCP (there is only one leader per path). | |
9715 | */ | |
72fd0718 VZ |
9716 | not_reset_mask1 = |
9717 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
9718 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
9719 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
9720 | ||
9721 | not_reset_mask2 = | |
c9ee9206 | 9722 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
9723 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
9724 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
9725 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
9726 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
9727 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
9728 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
9729 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
9730 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
c55e771b BW |
9731 | MISC_REGISTERS_RESET_REG_2_PGLC | |
9732 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
9733 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
9734 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
9735 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
9736 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
9737 | MISC_REGISTERS_RESET_REG_2_UMAC1; | |
72fd0718 | 9738 | |
8736c826 VZ |
9739 | /* |
9740 | * Keep the following blocks in reset: | |
9741 | * - all xxMACs are handled by the bnx2x_link code. | |
9742 | */ | |
9743 | stay_reset2 = | |
8736c826 VZ |
9744 | MISC_REGISTERS_RESET_REG_2_XMAC | |
9745 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
9746 | ||
9747 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
9748 | reset_mask1 = 0xffffffff; |
9749 | ||
9750 | if (CHIP_IS_E1(bp)) | |
9751 | reset_mask2 = 0xffff; | |
8736c826 | 9752 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 9753 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
9754 | else if (CHIP_IS_E2(bp)) |
9755 | reset_mask2 = 0xfffff; | |
9756 | else /* CHIP_IS_E3 */ | |
9757 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
9758 | |
9759 | /* Don't reset global blocks unless we need to */ | |
9760 | if (!global) | |
9761 | reset_mask2 &= ~global_bits2; | |
9762 | ||
9763 | /* | |
9764 | * In case of attention in the QM, we need to reset PXP | |
9765 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
9766 | * because otherwise QM reset would release 'close the gates' shortly | |
9767 | * before resetting the PXP, then the PSWRQ would send a write | |
9768 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
9769 | * read the payload data from PSWWR, but PSWWR would not | |
9770 | * respond. The write queue in PGLUE would stuck, dmae commands | |
9771 | * would not return. Therefore it's important to reset the second | |
9772 | * reset register (containing the | |
9773 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
9774 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
9775 | * bit). | |
9776 | */ | |
72fd0718 VZ |
9777 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
9778 | reset_mask2 & (~not_reset_mask2)); | |
9779 | ||
c9ee9206 VZ |
9780 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
9781 | reset_mask1 & (~not_reset_mask1)); | |
9782 | ||
72fd0718 | 9783 | barrier(); |
72fd0718 | 9784 | |
8736c826 VZ |
9785 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
9786 | reset_mask2 & (~stay_reset2)); | |
9787 | ||
9788 | barrier(); | |
8736c826 | 9789 | |
c9ee9206 | 9790 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
9791 | } |
9792 | ||
c9ee9206 VZ |
9793 | /** |
9794 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
9795 | * It should get cleared in no more than 1s. | |
9796 | * | |
9797 | * @bp: driver handle | |
9798 | * | |
9799 | * It should get cleared in no more than 1s. Returns 0 if | |
9800 | * pending writes bit gets cleared. | |
9801 | */ | |
9802 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
9803 | { | |
9804 | u32 cnt = 1000; | |
9805 | u32 pend_bits = 0; | |
9806 | ||
9807 | do { | |
9808 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
9809 | ||
9810 | if (pend_bits == 0) | |
9811 | break; | |
9812 | ||
0926d499 | 9813 | usleep_range(1000, 2000); |
c9ee9206 VZ |
9814 | } while (cnt-- > 0); |
9815 | ||
9816 | if (cnt <= 0) { | |
9817 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
9818 | pend_bits); | |
9819 | return -EBUSY; | |
9820 | } | |
9821 | ||
9822 | return 0; | |
9823 | } | |
9824 | ||
9825 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
9826 | { |
9827 | int cnt = 1000; | |
9828 | u32 val = 0; | |
9829 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
2de67439 | 9830 | u32 tags_63_32 = 0; |
72fd0718 VZ |
9831 | |
9832 | /* Empty the Tetris buffer, wait for 1s */ | |
9833 | do { | |
9834 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
9835 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
9836 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
9837 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
9838 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
c55e771b BW |
9839 | if (CHIP_IS_E3(bp)) |
9840 | tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); | |
9841 | ||
72fd0718 VZ |
9842 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && |
9843 | ((port_is_idle_0 & 0x1) == 0x1) && | |
9844 | ((port_is_idle_1 & 0x1) == 0x1) && | |
c55e771b BW |
9845 | (pgl_exp_rom2 == 0xffffffff) && |
9846 | (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) | |
72fd0718 | 9847 | break; |
0926d499 | 9848 | usleep_range(1000, 2000); |
72fd0718 VZ |
9849 | } while (cnt-- > 0); |
9850 | ||
9851 | if (cnt <= 0) { | |
51c1a580 MS |
9852 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
9853 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
72fd0718 VZ |
9854 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
9855 | pgl_exp_rom2); | |
9856 | return -EAGAIN; | |
9857 | } | |
9858 | ||
9859 | barrier(); | |
9860 | ||
9861 | /* Close gates #2, #3 and #4 */ | |
9862 | bnx2x_set_234_gates(bp, true); | |
9863 | ||
c9ee9206 VZ |
9864 | /* Poll for IGU VQs for 57712 and newer chips */ |
9865 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
9866 | return -EAGAIN; | |
9867 | ||
72fd0718 VZ |
9868 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
9869 | ||
9870 | /* Clear "unprepared" bit */ | |
9871 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
9872 | barrier(); | |
9873 | ||
72fd0718 VZ |
9874 | /* Wait for 1ms to empty GLUE and PCI-E core queues, |
9875 | * PSWHST, GRC and PSWRD Tetris buffer. | |
9876 | */ | |
0926d499 | 9877 | usleep_range(1000, 2000); |
72fd0718 VZ |
9878 | |
9879 | /* Prepare to chip reset: */ | |
9880 | /* MCP */ | |
c9ee9206 VZ |
9881 | if (global) |
9882 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
9883 | |
9884 | /* PXP */ | |
9885 | bnx2x_pxp_prep(bp); | |
9886 | barrier(); | |
9887 | ||
9888 | /* reset the chip */ | |
c9ee9206 | 9889 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
9890 | barrier(); |
9891 | ||
9dcd9acd DK |
9892 | /* clear errors in PGB */ |
9893 | if (!CHIP_IS_E1x(bp)) | |
9894 | REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); | |
9895 | ||
72fd0718 VZ |
9896 | /* Recover after reset: */ |
9897 | /* MCP */ | |
c9ee9206 | 9898 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
9899 | return -EAGAIN; |
9900 | ||
c9ee9206 VZ |
9901 | /* TBD: Add resetting the NO_MCP mode DB here */ |
9902 | ||
72fd0718 VZ |
9903 | /* Open the gates #2, #3 and #4 */ |
9904 | bnx2x_set_234_gates(bp, false); | |
9905 | ||
9906 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
9907 | * reset state, re-enable attentions. */ | |
9908 | ||
a2fbb9ea ET |
9909 | return 0; |
9910 | } | |
9911 | ||
910cc727 | 9912 | static int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
9913 | { |
9914 | int rc = 0; | |
c9ee9206 | 9915 | bool global = bnx2x_reset_is_global(bp); |
95c6c616 AE |
9916 | u32 load_code; |
9917 | ||
9918 | /* if not going to reset MCP - load "fake" driver to reset HW while | |
9919 | * driver is owner of the HW | |
9920 | */ | |
9921 | if (!global && !BP_NOMCP(bp)) { | |
5d07d868 YM |
9922 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, |
9923 | DRV_MSG_CODE_LOAD_REQ_WITH_LFA); | |
95c6c616 AE |
9924 | if (!load_code) { |
9925 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9926 | rc = -EAGAIN; | |
9927 | goto exit_leader_reset; | |
9928 | } | |
9929 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && | |
9930 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { | |
9931 | BNX2X_ERR("MCP unexpected resp, aborting\n"); | |
9932 | rc = -EAGAIN; | |
9933 | goto exit_leader_reset2; | |
9934 | } | |
9935 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
9936 | if (!load_code) { | |
9937 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9938 | rc = -EAGAIN; | |
9939 | goto exit_leader_reset2; | |
9940 | } | |
9941 | } | |
c9ee9206 | 9942 | |
72fd0718 | 9943 | /* Try to recover after the failure */ |
c9ee9206 | 9944 | if (bnx2x_process_kill(bp, global)) { |
51c1a580 MS |
9945 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
9946 | BP_PATH(bp)); | |
72fd0718 | 9947 | rc = -EAGAIN; |
95c6c616 | 9948 | goto exit_leader_reset2; |
72fd0718 VZ |
9949 | } |
9950 | ||
c9ee9206 VZ |
9951 | /* |
9952 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
9953 | * state. | |
9954 | */ | |
72fd0718 | 9955 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
9956 | if (global) |
9957 | bnx2x_clear_reset_global(bp); | |
72fd0718 | 9958 | |
95c6c616 AE |
9959 | exit_leader_reset2: |
9960 | /* unload "fake driver" if it was loaded */ | |
9961 | if (!global && !BP_NOMCP(bp)) { | |
9962 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); | |
9963 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
9964 | } | |
72fd0718 VZ |
9965 | exit_leader_reset: |
9966 | bp->is_leader = 0; | |
c9ee9206 VZ |
9967 | bnx2x_release_leader_lock(bp); |
9968 | smp_mb(); | |
72fd0718 VZ |
9969 | return rc; |
9970 | } | |
9971 | ||
1191cb83 | 9972 | static void bnx2x_recovery_failed(struct bnx2x *bp) |
c9ee9206 VZ |
9973 | { |
9974 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
9975 | ||
9976 | /* Disconnect this device */ | |
9977 | netif_device_detach(bp->dev); | |
9978 | ||
9979 | /* | |
9980 | * Block ifup for all function on this engine until "process kill" | |
9981 | * or power cycle. | |
9982 | */ | |
9983 | bnx2x_set_reset_in_progress(bp); | |
9984 | ||
9985 | /* Shut down the power */ | |
9986 | bnx2x_set_power_state(bp, PCI_D3hot); | |
9987 | ||
9988 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
9989 | ||
9990 | smp_mb(); | |
9991 | } | |
9992 | ||
9993 | /* | |
9994 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 9995 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
9996 | * will never be called when netif_running(bp->dev) is false. |
9997 | */ | |
9998 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
9999 | { | |
7a752993 | 10000 | u32 error_recovered, error_unrecovered; |
7113f796 MC |
10001 | bool is_parity, global = false; |
10002 | #ifdef CONFIG_BNX2X_SRIOV | |
10003 | int vf_idx; | |
10004 | ||
10005 | for (vf_idx = 0; vf_idx < bp->requested_nr_virtfn; vf_idx++) { | |
10006 | struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); | |
c9ee9206 | 10007 | |
7113f796 MC |
10008 | if (vf) |
10009 | vf->state = VF_LOST; | |
10010 | } | |
10011 | #endif | |
72fd0718 VZ |
10012 | DP(NETIF_MSG_HW, "Handling parity\n"); |
10013 | while (1) { | |
10014 | switch (bp->recovery_state) { | |
10015 | case BNX2X_RECOVERY_INIT: | |
10016 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
95c6c616 AE |
10017 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
10018 | WARN_ON(!is_parity); | |
c9ee9206 | 10019 | |
72fd0718 | 10020 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
10021 | if (bnx2x_trylock_leader_lock(bp)) { |
10022 | bnx2x_set_reset_in_progress(bp); | |
10023 | /* | |
10024 | * Check if there is a global attention and if | |
10025 | * there was a global attention, set the global | |
10026 | * reset bit. | |
10027 | */ | |
10028 | ||
10029 | if (global) | |
10030 | bnx2x_set_reset_global(bp); | |
10031 | ||
72fd0718 | 10032 | bp->is_leader = 1; |
c9ee9206 | 10033 | } |
72fd0718 VZ |
10034 | |
10035 | /* Stop the driver */ | |
10036 | /* If interface has been removed - break */ | |
5d07d868 | 10037 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) |
72fd0718 VZ |
10038 | return; |
10039 | ||
10040 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 | 10041 | |
c9ee9206 VZ |
10042 | /* Ensure "is_leader", MCP command sequence and |
10043 | * "recovery_state" update values are seen on other | |
10044 | * CPUs. | |
72fd0718 | 10045 | */ |
c9ee9206 | 10046 | smp_mb(); |
72fd0718 VZ |
10047 | break; |
10048 | ||
10049 | case BNX2X_RECOVERY_WAIT: | |
10050 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
10051 | if (bp->is_leader) { | |
c9ee9206 | 10052 | int other_engine = BP_PATH(bp) ? 0 : 1; |
889b9af3 AE |
10053 | bool other_load_status = |
10054 | bnx2x_get_load_status(bp, other_engine); | |
10055 | bool load_status = | |
10056 | bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
10057 | global = bnx2x_reset_is_global(bp); |
10058 | ||
10059 | /* | |
10060 | * In case of a parity in a global block, let | |
10061 | * the first leader that performs a | |
10062 | * leader_reset() reset the global blocks in | |
10063 | * order to clear global attentions. Otherwise | |
16a5fd92 | 10064 | * the gates will remain closed for that |
c9ee9206 VZ |
10065 | * engine. |
10066 | */ | |
889b9af3 AE |
10067 | if (load_status || |
10068 | (global && other_load_status)) { | |
72fd0718 VZ |
10069 | /* Wait until all other functions get |
10070 | * down. | |
10071 | */ | |
7be08a72 | 10072 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
10073 | HZ/10); |
10074 | return; | |
10075 | } else { | |
10076 | /* If all other functions got down - | |
10077 | * try to bring the chip back to | |
10078 | * normal. In any case it's an exit | |
10079 | * point for a leader. | |
10080 | */ | |
c9ee9206 VZ |
10081 | if (bnx2x_leader_reset(bp)) { |
10082 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
10083 | return; |
10084 | } | |
10085 | ||
c9ee9206 VZ |
10086 | /* If we are here, means that the |
10087 | * leader has succeeded and doesn't | |
10088 | * want to be a leader any more. Try | |
10089 | * to continue as a none-leader. | |
10090 | */ | |
10091 | break; | |
72fd0718 VZ |
10092 | } |
10093 | } else { /* non-leader */ | |
c9ee9206 | 10094 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
10095 | /* Try to get a LEADER_LOCK HW lock as |
10096 | * long as a former leader may have | |
10097 | * been unloaded by the user or | |
10098 | * released a leadership by another | |
10099 | * reason. | |
10100 | */ | |
c9ee9206 | 10101 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
10102 | /* I'm a leader now! Restart a |
10103 | * switch case. | |
10104 | */ | |
10105 | bp->is_leader = 1; | |
10106 | break; | |
10107 | } | |
10108 | ||
7be08a72 | 10109 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
10110 | HZ/10); |
10111 | return; | |
10112 | ||
c9ee9206 VZ |
10113 | } else { |
10114 | /* | |
10115 | * If there was a global attention, wait | |
10116 | * for it to be cleared. | |
10117 | */ | |
10118 | if (bnx2x_reset_is_global(bp)) { | |
10119 | schedule_delayed_work( | |
7be08a72 AE |
10120 | &bp->sp_rtnl_task, |
10121 | HZ/10); | |
c9ee9206 VZ |
10122 | return; |
10123 | } | |
10124 | ||
7a752993 AE |
10125 | error_recovered = |
10126 | bp->eth_stats.recoverable_error; | |
10127 | error_unrecovered = | |
10128 | bp->eth_stats.unrecoverable_error; | |
95c6c616 AE |
10129 | bp->recovery_state = |
10130 | BNX2X_RECOVERY_NIC_LOADING; | |
10131 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { | |
7a752993 | 10132 | error_unrecovered++; |
95c6c616 | 10133 | netdev_err(bp->dev, |
51c1a580 | 10134 | "Recovery failed. Power cycle needed\n"); |
95c6c616 AE |
10135 | /* Disconnect this device */ |
10136 | netif_device_detach(bp->dev); | |
10137 | /* Shut down the power */ | |
10138 | bnx2x_set_power_state( | |
10139 | bp, PCI_D3hot); | |
10140 | smp_mb(); | |
10141 | } else { | |
c9ee9206 VZ |
10142 | bp->recovery_state = |
10143 | BNX2X_RECOVERY_DONE; | |
7a752993 | 10144 | error_recovered++; |
c9ee9206 VZ |
10145 | smp_mb(); |
10146 | } | |
7a752993 AE |
10147 | bp->eth_stats.recoverable_error = |
10148 | error_recovered; | |
10149 | bp->eth_stats.unrecoverable_error = | |
10150 | error_unrecovered; | |
c9ee9206 | 10151 | |
72fd0718 VZ |
10152 | return; |
10153 | } | |
10154 | } | |
10155 | default: | |
10156 | return; | |
10157 | } | |
10158 | } | |
10159 | } | |
10160 | ||
883ce97d | 10161 | static int bnx2x_udp_port_update(struct bnx2x *bp) |
f34fa14c RB |
10162 | { |
10163 | struct bnx2x_func_switch_update_params *switch_update_params; | |
10164 | struct bnx2x_func_state_params func_params = {NULL}; | |
883ce97d | 10165 | u16 vxlan_port = 0, geneve_port = 0; |
f34fa14c RB |
10166 | int rc; |
10167 | ||
10168 | switch_update_params = &func_params.params.switch_update; | |
10169 | ||
10170 | /* Prepare parameters for function state transitions */ | |
10171 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
10172 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
10173 | ||
10174 | func_params.f_obj = &bp->func_obj; | |
10175 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
10176 | ||
10177 | /* Function parameters */ | |
10178 | __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG, | |
10179 | &switch_update_params->changes); | |
883ce97d | 10180 | |
085c5c42 JK |
10181 | if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]) { |
10182 | geneve_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]; | |
883ce97d YM |
10183 | switch_update_params->geneve_dst_port = geneve_port; |
10184 | } | |
10185 | ||
085c5c42 JK |
10186 | if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]) { |
10187 | vxlan_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]; | |
883ce97d YM |
10188 | switch_update_params->vxlan_dst_port = vxlan_port; |
10189 | } | |
10190 | ||
10191 | /* Re-enable inner-rss for the offloaded UDP tunnels */ | |
10192 | __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS, | |
10193 | &switch_update_params->changes); | |
10194 | ||
f34fa14c RB |
10195 | rc = bnx2x_func_state_change(bp, &func_params); |
10196 | if (rc) | |
883ce97d YM |
10197 | BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n", |
10198 | vxlan_port, geneve_port, rc); | |
10199 | else | |
10200 | DP(BNX2X_MSG_SP, | |
10201 | "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n", | |
10202 | vxlan_port, geneve_port); | |
10203 | ||
f34fa14c RB |
10204 | return rc; |
10205 | } | |
10206 | ||
085c5c42 | 10207 | static int bnx2x_udp_tunnel_sync(struct net_device *netdev, unsigned int table) |
883ce97d YM |
10208 | { |
10209 | struct bnx2x *bp = netdev_priv(netdev); | |
085c5c42 | 10210 | struct udp_tunnel_info ti; |
883ce97d | 10211 | |
085c5c42 JK |
10212 | udp_tunnel_nic_get_port(netdev, table, 0, &ti); |
10213 | bp->udp_tunnel_ports[table] = be16_to_cpu(ti.port); | |
f34fa14c | 10214 | |
085c5c42 | 10215 | return bnx2x_udp_port_update(bp); |
f34fa14c | 10216 | } |
f34fa14c | 10217 | |
085c5c42 JK |
10218 | static const struct udp_tunnel_nic_info bnx2x_udp_tunnels = { |
10219 | .sync_table = bnx2x_udp_tunnel_sync, | |
10220 | .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP | | |
10221 | UDP_TUNNEL_NIC_INFO_OPEN_ONLY, | |
10222 | .tables = { | |
10223 | { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, | |
10224 | { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, | |
10225 | }, | |
10226 | }; | |
10227 | ||
56ad3152 MS |
10228 | static int bnx2x_close(struct net_device *dev); |
10229 | ||
72fd0718 VZ |
10230 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
10231 | * scheduled on a general queue in order to prevent a dead lock. | |
10232 | */ | |
7be08a72 | 10233 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 10234 | { |
7be08a72 | 10235 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
10236 | |
10237 | rtnl_lock(); | |
10238 | ||
8395be5e AE |
10239 | if (!netif_running(bp->dev)) { |
10240 | rtnl_unlock(); | |
10241 | return; | |
10242 | } | |
7be08a72 | 10243 | |
6bf07b8e | 10244 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
7be08a72 | 10245 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e YM |
10246 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
10247 | "you will need to reboot when done\n"); | |
10248 | goto sp_rtnl_not_reset; | |
7be08a72 | 10249 | #endif |
7be08a72 | 10250 | /* |
b1fb8740 VZ |
10251 | * Clear all pending SP commands as we are going to reset the |
10252 | * function anyway. | |
7be08a72 | 10253 | */ |
b1fb8740 VZ |
10254 | bp->sp_rtnl_state = 0; |
10255 | smp_mb(); | |
10256 | ||
72fd0718 | 10257 | bnx2x_parity_recover(bp); |
b1fb8740 | 10258 | |
8395be5e AE |
10259 | rtnl_unlock(); |
10260 | return; | |
b1fb8740 VZ |
10261 | } |
10262 | ||
10263 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
6bf07b8e YM |
10264 | #ifdef BNX2X_STOP_ON_ERROR |
10265 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" | |
10266 | "you will need to reboot when done\n"); | |
10267 | goto sp_rtnl_not_reset; | |
10268 | #endif | |
10269 | ||
b1fb8740 VZ |
10270 | /* |
10271 | * Clear all pending SP commands as we are going to reset the | |
10272 | * function anyway. | |
10273 | */ | |
10274 | bp->sp_rtnl_state = 0; | |
10275 | smp_mb(); | |
10276 | ||
484c016d SRK |
10277 | /* Immediately indicate link as down */ |
10278 | bp->link_vars.link_up = 0; | |
10279 | bp->force_link_down = true; | |
10280 | netif_carrier_off(bp->dev); | |
10281 | BNX2X_ERR("Indicating link is down due to Tx-timeout\n"); | |
10282 | ||
5d07d868 | 10283 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); |
442866ff ZY |
10284 | /* When ret value shows failure of allocation failure, |
10285 | * the nic is rebooted again. If open still fails, a error | |
10286 | * message to notify the user. | |
10287 | */ | |
10288 | if (bnx2x_nic_load(bp, LOAD_NORMAL) == -ENOMEM) { | |
10289 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); | |
10290 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) | |
10291 | BNX2X_ERR("Open the NIC fails again!\n"); | |
10292 | } | |
8395be5e AE |
10293 | rtnl_unlock(); |
10294 | return; | |
72fd0718 | 10295 | } |
b1fb8740 VZ |
10296 | #ifdef BNX2X_STOP_ON_ERROR |
10297 | sp_rtnl_not_reset: | |
10298 | #endif | |
10299 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
10300 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
a3348722 BW |
10301 | if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) |
10302 | bnx2x_after_function_update(bp); | |
8304859a AE |
10303 | /* |
10304 | * in case of fan failure we need to reset id if the "stop on error" | |
10305 | * debug flag is set, since we trying to prevent permanent overheating | |
10306 | * damage | |
10307 | */ | |
10308 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { | |
51c1a580 | 10309 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
8304859a AE |
10310 | netif_device_detach(bp->dev); |
10311 | bnx2x_close(bp->dev); | |
8395be5e AE |
10312 | rtnl_unlock(); |
10313 | return; | |
8304859a AE |
10314 | } |
10315 | ||
381ac16b AE |
10316 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { |
10317 | DP(BNX2X_MSG_SP, | |
10318 | "sending set mcast vf pf channel message from rtnl sp-task\n"); | |
10319 | bnx2x_vfpf_set_mcast(bp->dev); | |
10320 | } | |
78c3bcc5 AE |
10321 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, |
10322 | &bp->sp_rtnl_state)){ | |
3fdd34c1 | 10323 | if (netif_carrier_ok(bp->dev)) { |
78c3bcc5 AE |
10324 | bnx2x_tx_disable(bp); |
10325 | BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n"); | |
10326 | } | |
10327 | } | |
381ac16b | 10328 | |
8b09be5f YM |
10329 | if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { |
10330 | DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n"); | |
10331 | bnx2x_set_rx_mode_inner(bp); | |
381ac16b AE |
10332 | } |
10333 | ||
3ec9f9ca AE |
10334 | if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, |
10335 | &bp->sp_rtnl_state)) | |
10336 | bnx2x_pf_set_vfs_vlan(bp); | |
10337 | ||
6ffa39f2 | 10338 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) { |
07b4eb3b | 10339 | bnx2x_dcbx_stop_hw_tx(bp); |
07b4eb3b | 10340 | bnx2x_dcbx_resume_hw_tx(bp); |
6ffa39f2 | 10341 | } |
07b4eb3b | 10342 | |
42f8277f YM |
10343 | if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION, |
10344 | &bp->sp_rtnl_state)) | |
10345 | bnx2x_update_mng_version(bp); | |
10346 | ||
9061193c SRK |
10347 | if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state)) |
10348 | bnx2x_handle_update_svid_cmd(bp); | |
10349 | ||
8395be5e AE |
10350 | /* work which needs rtnl lock not-taken (as it takes the lock itself and |
10351 | * can be called from other contexts as well) | |
10352 | */ | |
34f80b04 | 10353 | rtnl_unlock(); |
8395be5e | 10354 | |
6411280a | 10355 | /* enable SR-IOV if applicable */ |
8395be5e | 10356 | if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, |
3c76feff AE |
10357 | &bp->sp_rtnl_state)) { |
10358 | bnx2x_disable_sriov(bp); | |
6411280a | 10359 | bnx2x_enable_sriov(bp); |
3c76feff | 10360 | } |
34f80b04 EG |
10361 | } |
10362 | ||
3deb8167 YR |
10363 | static void bnx2x_period_task(struct work_struct *work) |
10364 | { | |
10365 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
10366 | ||
10367 | if (!netif_running(bp->dev)) | |
10368 | goto period_task_exit; | |
10369 | ||
10370 | if (CHIP_REV_IS_SLOW(bp)) { | |
10371 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
10372 | goto period_task_exit; | |
10373 | } | |
10374 | ||
10375 | bnx2x_acquire_phy_lock(bp); | |
10376 | /* | |
10377 | * The barrier is needed to ensure the ordering between the writing to | |
10378 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
10379 | * the reading here. | |
10380 | */ | |
10381 | smp_mb(); | |
10382 | if (bp->port.pmf) { | |
10383 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
10384 | ||
10385 | /* Re-queue task in 1 sec */ | |
10386 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
10387 | } | |
10388 | ||
10389 | bnx2x_release_phy_lock(bp); | |
10390 | period_task_exit: | |
10391 | return; | |
10392 | } | |
10393 | ||
a2fbb9ea ET |
10394 | /* |
10395 | * Init service functions | |
10396 | */ | |
10397 | ||
a8f47eb7 | 10398 | static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
10399 | { |
10400 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
10401 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
10402 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
10403 | } |
10404 | ||
3d6b7253 YM |
10405 | static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp, |
10406 | u8 port, u32 reset_reg, | |
10407 | struct bnx2x_mac_vals *vals) | |
10408 | { | |
10409 | u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; | |
10410 | u32 base_addr; | |
10411 | ||
10412 | if (!(mask & reset_reg)) | |
10413 | return false; | |
10414 | ||
10415 | BNX2X_DEV_INFO("Disable umac Rx %02x\n", port); | |
10416 | base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
10417 | vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG; | |
10418 | vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]); | |
10419 | REG_WR(bp, vals->umac_addr[port], 0); | |
10420 | ||
10421 | return true; | |
10422 | } | |
10423 | ||
1ef1d45a BW |
10424 | static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, |
10425 | struct bnx2x_mac_vals *vals) | |
34f80b04 | 10426 | { |
452427b0 YM |
10427 | u32 val, base_addr, offset, mask, reset_reg; |
10428 | bool mac_stopped = false; | |
10429 | u8 port = BP_PORT(bp); | |
34f80b04 | 10430 | |
1ef1d45a | 10431 | /* reset addresses as they also mark which values were changed */ |
3d6b7253 | 10432 | memset(vals, 0, sizeof(*vals)); |
1ef1d45a | 10433 | |
452427b0 | 10434 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
f16da43b | 10435 | |
452427b0 YM |
10436 | if (!CHIP_IS_E3(bp)) { |
10437 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
10438 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; | |
10439 | if ((mask & reset_reg) && val) { | |
10440 | u32 wb_data[2]; | |
10441 | BNX2X_DEV_INFO("Disable bmac Rx\n"); | |
10442 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM | |
10443 | : NIG_REG_INGRESS_BMAC0_MEM; | |
10444 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL | |
10445 | : BIGMAC_REGISTER_BMAC_CONTROL; | |
7a06a122 | 10446 | |
452427b0 YM |
10447 | /* |
10448 | * use rd/wr since we cannot use dmae. This is safe | |
10449 | * since MCP won't access the bus due to the request | |
10450 | * to unload, and no function on the path can be | |
10451 | * loaded at this time. | |
10452 | */ | |
10453 | wb_data[0] = REG_RD(bp, base_addr + offset); | |
10454 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); | |
1ef1d45a BW |
10455 | vals->bmac_addr = base_addr + offset; |
10456 | vals->bmac_val[0] = wb_data[0]; | |
10457 | vals->bmac_val[1] = wb_data[1]; | |
452427b0 | 10458 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
1ef1d45a BW |
10459 | REG_WR(bp, vals->bmac_addr, wb_data[0]); |
10460 | REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); | |
452427b0 YM |
10461 | } |
10462 | BNX2X_DEV_INFO("Disable emac Rx\n"); | |
1ef1d45a BW |
10463 | vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; |
10464 | vals->emac_val = REG_RD(bp, vals->emac_addr); | |
10465 | REG_WR(bp, vals->emac_addr, 0); | |
452427b0 YM |
10466 | mac_stopped = true; |
10467 | } else { | |
10468 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
10469 | BNX2X_DEV_INFO("Disable xmac Rx\n"); | |
10470 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
10471 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); | |
10472 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
10473 | val & ~(1 << 1)); | |
10474 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
10475 | val | (1 << 1)); | |
1ef1d45a BW |
10476 | vals->xmac_addr = base_addr + XMAC_REG_CTRL; |
10477 | vals->xmac_val = REG_RD(bp, vals->xmac_addr); | |
10478 | REG_WR(bp, vals->xmac_addr, 0); | |
452427b0 YM |
10479 | mac_stopped = true; |
10480 | } | |
3d6b7253 YM |
10481 | |
10482 | mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0, | |
10483 | reset_reg, vals); | |
10484 | mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1, | |
10485 | reset_reg, vals); | |
452427b0 YM |
10486 | } |
10487 | ||
10488 | if (mac_stopped) | |
10489 | msleep(20); | |
452427b0 YM |
10490 | } |
10491 | ||
10492 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) | |
7c3afd85 YM |
10493 | #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \ |
10494 | 0x1848 + ((f) << 4)) | |
452427b0 YM |
10495 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) |
10496 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) | |
10497 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) | |
10498 | ||
91ebb929 YM |
10499 | #define BCM_5710_UNDI_FW_MF_MAJOR (0x07) |
10500 | #define BCM_5710_UNDI_FW_MF_MINOR (0x08) | |
10501 | #define BCM_5710_UNDI_FW_MF_VERS (0x05) | |
b17b0ca1 YM |
10502 | |
10503 | static bool bnx2x_prev_is_after_undi(struct bnx2x *bp) | |
10504 | { | |
10505 | /* UNDI marks its presence in DORQ - | |
10506 | * it initializes CID offset for normal bell to 0x7 | |
10507 | */ | |
10508 | if (!(REG_RD(bp, MISC_REG_RESET_REG_1) & | |
10509 | MISC_REGISTERS_RESET_REG_1_RST_DORQ)) | |
10510 | return false; | |
10511 | ||
10512 | if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) { | |
10513 | BNX2X_DEV_INFO("UNDI previously loaded\n"); | |
10514 | return true; | |
10515 | } | |
10516 | ||
10517 | return false; | |
10518 | } | |
10519 | ||
7c3afd85 | 10520 | static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc) |
452427b0 YM |
10521 | { |
10522 | u16 rcq, bd; | |
7c3afd85 | 10523 | u32 addr, tmp_reg; |
452427b0 | 10524 | |
7c3afd85 YM |
10525 | if (BP_FUNC(bp) < 2) |
10526 | addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp)); | |
10527 | else | |
10528 | addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2); | |
10529 | ||
10530 | tmp_reg = REG_RD(bp, addr); | |
452427b0 YM |
10531 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; |
10532 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; | |
10533 | ||
10534 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); | |
7c3afd85 | 10535 | REG_WR(bp, addr, tmp_reg); |
452427b0 | 10536 | |
7c3afd85 YM |
10537 | BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n", |
10538 | BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq); | |
452427b0 YM |
10539 | } |
10540 | ||
0329aba1 | 10541 | static int bnx2x_prev_mcp_done(struct bnx2x *bp) |
452427b0 | 10542 | { |
5d07d868 YM |
10543 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, |
10544 | DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); | |
452427b0 YM |
10545 | if (!rc) { |
10546 | BNX2X_ERR("MCP response failure, aborting\n"); | |
10547 | return -EBUSY; | |
10548 | } | |
10549 | ||
10550 | return 0; | |
10551 | } | |
10552 | ||
c63da990 BW |
10553 | static struct bnx2x_prev_path_list * |
10554 | bnx2x_prev_path_get_entry(struct bnx2x *bp) | |
10555 | { | |
10556 | struct bnx2x_prev_path_list *tmp_list; | |
10557 | ||
10558 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) | |
10559 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
10560 | bp->pdev->bus->number == tmp_list->bus && | |
10561 | BP_PATH(bp) == tmp_list->path) | |
10562 | return tmp_list; | |
10563 | ||
10564 | return NULL; | |
10565 | } | |
10566 | ||
7fa6f340 YM |
10567 | static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) |
10568 | { | |
10569 | struct bnx2x_prev_path_list *tmp_list; | |
10570 | int rc; | |
10571 | ||
10572 | rc = down_interruptible(&bnx2x_prev_sem); | |
10573 | if (rc) { | |
10574 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
10575 | return rc; | |
10576 | } | |
10577 | ||
10578 | tmp_list = bnx2x_prev_path_get_entry(bp); | |
10579 | if (tmp_list) { | |
10580 | tmp_list->aer = 1; | |
10581 | rc = 0; | |
10582 | } else { | |
10583 | BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n", | |
10584 | BP_PATH(bp)); | |
10585 | } | |
10586 | ||
10587 | up(&bnx2x_prev_sem); | |
10588 | ||
10589 | return rc; | |
10590 | } | |
10591 | ||
0329aba1 | 10592 | static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) |
452427b0 YM |
10593 | { |
10594 | struct bnx2x_prev_path_list *tmp_list; | |
b85d717c | 10595 | bool rc = false; |
452427b0 YM |
10596 | |
10597 | if (down_trylock(&bnx2x_prev_sem)) | |
10598 | return false; | |
10599 | ||
7fa6f340 YM |
10600 | tmp_list = bnx2x_prev_path_get_entry(bp); |
10601 | if (tmp_list) { | |
10602 | if (tmp_list->aer) { | |
10603 | DP(NETIF_MSG_HW, "Path %d was marked by AER\n", | |
10604 | BP_PATH(bp)); | |
10605 | } else { | |
452427b0 YM |
10606 | rc = true; |
10607 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | |
10608 | BP_PATH(bp)); | |
452427b0 YM |
10609 | } |
10610 | } | |
10611 | ||
10612 | up(&bnx2x_prev_sem); | |
10613 | ||
10614 | return rc; | |
10615 | } | |
10616 | ||
178135c1 DK |
10617 | bool bnx2x_port_after_undi(struct bnx2x *bp) |
10618 | { | |
10619 | struct bnx2x_prev_path_list *entry; | |
10620 | bool val; | |
10621 | ||
10622 | down(&bnx2x_prev_sem); | |
10623 | ||
10624 | entry = bnx2x_prev_path_get_entry(bp); | |
10625 | val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); | |
10626 | ||
10627 | up(&bnx2x_prev_sem); | |
10628 | ||
10629 | return val; | |
10630 | } | |
10631 | ||
c63da990 | 10632 | static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) |
452427b0 YM |
10633 | { |
10634 | struct bnx2x_prev_path_list *tmp_list; | |
10635 | int rc; | |
10636 | ||
7fa6f340 YM |
10637 | rc = down_interruptible(&bnx2x_prev_sem); |
10638 | if (rc) { | |
10639 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
10640 | return rc; | |
10641 | } | |
10642 | ||
10643 | /* Check whether the entry for this path already exists */ | |
10644 | tmp_list = bnx2x_prev_path_get_entry(bp); | |
10645 | if (tmp_list) { | |
10646 | if (!tmp_list->aer) { | |
10647 | BNX2X_ERR("Re-Marking the path.\n"); | |
10648 | } else { | |
10649 | DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", | |
10650 | BP_PATH(bp)); | |
10651 | tmp_list->aer = 0; | |
10652 | } | |
10653 | up(&bnx2x_prev_sem); | |
10654 | return 0; | |
10655 | } | |
10656 | up(&bnx2x_prev_sem); | |
10657 | ||
10658 | /* Create an entry for this path and add it */ | |
ea4b3857 | 10659 | tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); |
452427b0 YM |
10660 | if (!tmp_list) { |
10661 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | |
10662 | return -ENOMEM; | |
10663 | } | |
10664 | ||
10665 | tmp_list->bus = bp->pdev->bus->number; | |
10666 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | |
10667 | tmp_list->path = BP_PATH(bp); | |
7fa6f340 | 10668 | tmp_list->aer = 0; |
c63da990 | 10669 | tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; |
452427b0 YM |
10670 | |
10671 | rc = down_interruptible(&bnx2x_prev_sem); | |
10672 | if (rc) { | |
10673 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
10674 | kfree(tmp_list); | |
10675 | } else { | |
7fa6f340 YM |
10676 | DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", |
10677 | BP_PATH(bp)); | |
452427b0 YM |
10678 | list_add(&tmp_list->list, &bnx2x_prev_list); |
10679 | up(&bnx2x_prev_sem); | |
10680 | } | |
10681 | ||
10682 | return rc; | |
10683 | } | |
10684 | ||
0329aba1 | 10685 | static int bnx2x_do_flr(struct bnx2x *bp) |
452427b0 | 10686 | { |
452427b0 YM |
10687 | struct pci_dev *dev = bp->pdev; |
10688 | ||
8eee694c YM |
10689 | if (CHIP_IS_E1x(bp)) { |
10690 | BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); | |
10691 | return -EINVAL; | |
10692 | } | |
10693 | ||
10694 | /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ | |
10695 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | |
10696 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | |
10697 | bp->common.bc_ver); | |
10698 | return -EINVAL; | |
10699 | } | |
452427b0 | 10700 | |
8903b9eb CL |
10701 | if (!pci_wait_for_pending_transaction(dev)) |
10702 | dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); | |
452427b0 | 10703 | |
8eee694c | 10704 | BNX2X_DEV_INFO("Initiating FLR\n"); |
452427b0 YM |
10705 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); |
10706 | ||
10707 | return 0; | |
10708 | } | |
10709 | ||
0329aba1 | 10710 | static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) |
452427b0 YM |
10711 | { |
10712 | int rc; | |
10713 | ||
10714 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); | |
10715 | ||
10716 | /* Test if previous unload process was already finished for this path */ | |
10717 | if (bnx2x_prev_is_path_marked(bp)) | |
10718 | return bnx2x_prev_mcp_done(bp); | |
10719 | ||
04c46736 YM |
10720 | BNX2X_DEV_INFO("Path is unmarked\n"); |
10721 | ||
b17b0ca1 YM |
10722 | /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */ |
10723 | if (bnx2x_prev_is_after_undi(bp)) | |
10724 | goto out; | |
10725 | ||
452427b0 YM |
10726 | /* If function has FLR capabilities, and existing FW version matches |
10727 | * the one required, then FLR will be sufficient to clean any residue | |
10728 | * left by previous driver | |
10729 | */ | |
91ebb929 | 10730 | rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false); |
8eee694c YM |
10731 | |
10732 | if (!rc) { | |
10733 | /* fw version is good */ | |
10734 | BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); | |
10735 | rc = bnx2x_do_flr(bp); | |
10736 | } | |
10737 | ||
10738 | if (!rc) { | |
10739 | /* FLR was performed */ | |
10740 | BNX2X_DEV_INFO("FLR successful\n"); | |
10741 | return 0; | |
10742 | } | |
10743 | ||
10744 | BNX2X_DEV_INFO("Could not FLR\n"); | |
452427b0 | 10745 | |
b17b0ca1 | 10746 | out: |
452427b0 YM |
10747 | /* Close the MCP request, return failure*/ |
10748 | rc = bnx2x_prev_mcp_done(bp); | |
10749 | if (!rc) | |
10750 | rc = BNX2X_PREV_WAIT_NEEDED; | |
10751 | ||
10752 | return rc; | |
10753 | } | |
10754 | ||
0329aba1 | 10755 | static int bnx2x_prev_unload_common(struct bnx2x *bp) |
452427b0 YM |
10756 | { |
10757 | u32 reset_reg, tmp_reg = 0, rc; | |
c63da990 | 10758 | bool prev_undi = false; |
1ef1d45a BW |
10759 | struct bnx2x_mac_vals mac_vals; |
10760 | ||
452427b0 YM |
10761 | /* It is possible a previous function received 'common' answer, |
10762 | * but hasn't loaded yet, therefore creating a scenario of | |
10763 | * multiple functions receiving 'common' on the same path. | |
10764 | */ | |
10765 | BNX2X_DEV_INFO("Common unload Flow\n"); | |
10766 | ||
1ef1d45a BW |
10767 | memset(&mac_vals, 0, sizeof(mac_vals)); |
10768 | ||
452427b0 YM |
10769 | if (bnx2x_prev_is_path_marked(bp)) |
10770 | return bnx2x_prev_mcp_done(bp); | |
10771 | ||
10772 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); | |
10773 | ||
10774 | /* Reset should be performed after BRB is emptied */ | |
10775 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { | |
10776 | u32 timer_count = 1000; | |
452427b0 YM |
10777 | |
10778 | /* Close the MAC Rx to prevent BRB from filling up */ | |
1ef1d45a BW |
10779 | bnx2x_prev_unload_close_mac(bp, &mac_vals); |
10780 | ||
3d6b7253 | 10781 | /* close LLH filters for both ports towards the BRB */ |
1ef1d45a | 10782 | bnx2x_set_rx_filter(&bp->link_params, 0); |
3d6b7253 | 10783 | bp->link_params.port ^= 1; |
1ef1d45a | 10784 | bnx2x_set_rx_filter(&bp->link_params, 0); |
3d6b7253 | 10785 | bp->link_params.port ^= 1; |
452427b0 | 10786 | |
b17b0ca1 YM |
10787 | /* Check if the UNDI driver was previously loaded */ |
10788 | if (bnx2x_prev_is_after_undi(bp)) { | |
10789 | prev_undi = true; | |
10790 | /* clear the UNDI indication */ | |
10791 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
10792 | /* clear possible idle check errors */ | |
10793 | REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); | |
452427b0 | 10794 | } |
d46f7c4d DK |
10795 | if (!CHIP_IS_E1x(bp)) |
10796 | /* block FW from writing to host */ | |
10797 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
10798 | ||
452427b0 YM |
10799 | /* wait until BRB is empty */ |
10800 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); | |
10801 | while (timer_count) { | |
10802 | u32 prev_brb = tmp_reg; | |
34f80b04 | 10803 | |
452427b0 YM |
10804 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
10805 | if (!tmp_reg) | |
10806 | break; | |
619c5cb6 | 10807 | |
452427b0 | 10808 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
619c5cb6 | 10809 | |
452427b0 YM |
10810 | /* reset timer as long as BRB actually gets emptied */ |
10811 | if (prev_brb > tmp_reg) | |
10812 | timer_count = 1000; | |
10813 | else | |
10814 | timer_count--; | |
da5a662a | 10815 | |
7c3afd85 YM |
10816 | /* If UNDI resides in memory, manually increment it */ |
10817 | if (prev_undi) | |
10818 | bnx2x_prev_unload_undi_inc(bp, 1); | |
10819 | ||
452427b0 | 10820 | udelay(10); |
7a06a122 | 10821 | } |
452427b0 YM |
10822 | |
10823 | if (!timer_count) | |
10824 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); | |
34f80b04 | 10825 | } |
f16da43b | 10826 | |
452427b0 YM |
10827 | /* No packets are in the pipeline, path is ready for reset */ |
10828 | bnx2x_reset_common(bp); | |
10829 | ||
1ef1d45a BW |
10830 | if (mac_vals.xmac_addr) |
10831 | REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); | |
3d6b7253 YM |
10832 | if (mac_vals.umac_addr[0]) |
10833 | REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); | |
10834 | if (mac_vals.umac_addr[1]) | |
10835 | REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); | |
1ef1d45a BW |
10836 | if (mac_vals.emac_addr) |
10837 | REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); | |
10838 | if (mac_vals.bmac_addr) { | |
10839 | REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); | |
10840 | REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); | |
10841 | } | |
10842 | ||
c63da990 | 10843 | rc = bnx2x_prev_mark_path(bp, prev_undi); |
452427b0 YM |
10844 | if (rc) { |
10845 | bnx2x_prev_mcp_done(bp); | |
10846 | return rc; | |
10847 | } | |
10848 | ||
10849 | return bnx2x_prev_mcp_done(bp); | |
10850 | } | |
10851 | ||
0329aba1 | 10852 | static int bnx2x_prev_unload(struct bnx2x *bp) |
452427b0 YM |
10853 | { |
10854 | int time_counter = 10; | |
10855 | u32 rc, fw, hw_lock_reg, hw_lock_val; | |
10856 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); | |
10857 | ||
24f06716 AE |
10858 | /* clear hw from errors which may have resulted from an interrupted |
10859 | * dmae transaction. | |
10860 | */ | |
da254fbc | 10861 | bnx2x_clean_pglue_errors(bp); |
24f06716 AE |
10862 | |
10863 | /* Release previously held locks */ | |
452427b0 YM |
10864 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? |
10865 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : | |
10866 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); | |
10867 | ||
3cdeec22 | 10868 | hw_lock_val = REG_RD(bp, hw_lock_reg); |
452427b0 YM |
10869 | if (hw_lock_val) { |
10870 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { | |
10871 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); | |
10872 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
10873 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); | |
10874 | } | |
10875 | ||
10876 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); | |
10877 | REG_WR(bp, hw_lock_reg, 0xffffffff); | |
10878 | } else | |
10879 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); | |
10880 | ||
10881 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { | |
10882 | BNX2X_DEV_INFO("Release previously held alr\n"); | |
3cdeec22 | 10883 | bnx2x_release_alr(bp); |
452427b0 YM |
10884 | } |
10885 | ||
452427b0 | 10886 | do { |
7fa6f340 | 10887 | int aer = 0; |
452427b0 YM |
10888 | /* Lock MCP using an unload request */ |
10889 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | |
10890 | if (!fw) { | |
10891 | BNX2X_ERR("MCP response failure, aborting\n"); | |
10892 | rc = -EBUSY; | |
10893 | break; | |
10894 | } | |
10895 | ||
7fa6f340 YM |
10896 | rc = down_interruptible(&bnx2x_prev_sem); |
10897 | if (rc) { | |
10898 | BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n", | |
10899 | rc); | |
10900 | } else { | |
10901 | /* If Path is marked by EEH, ignore unload status */ | |
10902 | aer = !!(bnx2x_prev_path_get_entry(bp) && | |
10903 | bnx2x_prev_path_get_entry(bp)->aer); | |
60cde81f | 10904 | up(&bnx2x_prev_sem); |
7fa6f340 | 10905 | } |
7fa6f340 YM |
10906 | |
10907 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) { | |
452427b0 YM |
10908 | rc = bnx2x_prev_unload_common(bp); |
10909 | break; | |
10910 | } | |
10911 | ||
16a5fd92 | 10912 | /* non-common reply from MCP might require looping */ |
452427b0 YM |
10913 | rc = bnx2x_prev_unload_uncommon(bp); |
10914 | if (rc != BNX2X_PREV_WAIT_NEEDED) | |
10915 | break; | |
10916 | ||
10917 | msleep(20); | |
10918 | } while (--time_counter); | |
10919 | ||
10920 | if (!time_counter || rc) { | |
91ebb929 YM |
10921 | BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n"); |
10922 | rc = -EPROBE_DEFER; | |
452427b0 YM |
10923 | } |
10924 | ||
c63da990 | 10925 | /* Mark function if its port was used to boot from SAN */ |
178135c1 | 10926 | if (bnx2x_port_after_undi(bp)) |
c63da990 BW |
10927 | bp->link_params.feature_config_flags |= |
10928 | FEATURE_CONFIG_BOOT_FROM_SAN; | |
10929 | ||
452427b0 YM |
10930 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); |
10931 | ||
10932 | return rc; | |
34f80b04 EG |
10933 | } |
10934 | ||
0329aba1 | 10935 | static void bnx2x_get_common_hwinfo(struct bnx2x *bp) |
34f80b04 | 10936 | { |
1d187b34 | 10937 | u32 val, val2, val3, val4, id, boot_mode; |
72ce58c3 | 10938 | u16 pmc; |
34f80b04 EG |
10939 | |
10940 | /* Get the chip revision id and number. */ | |
10941 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
10942 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
10943 | id = ((val & 0xffff) << 16); | |
10944 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
10945 | id |= ((val & 0xf) << 12); | |
f22fdf25 YM |
10946 | |
10947 | /* Metal is read from PCI regs, but we can't access >=0x400 from | |
10948 | * the configuration space (so we need to reg_rd) | |
10949 | */ | |
10950 | val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); | |
10951 | id |= (((val >> 24) & 0xf) << 4); | |
5a40e08e | 10952 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
10953 | id |= (val & 0xf); |
10954 | bp->common.chip_id = id; | |
523224a3 | 10955 | |
7e8e02df BW |
10956 | /* force 57811 according to MISC register */ |
10957 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { | |
10958 | if (CHIP_IS_57810(bp)) | |
10959 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | | |
10960 | (bp->common.chip_id & 0x0000FFFF); | |
10961 | else if (CHIP_IS_57810_MF(bp)) | |
10962 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | | |
10963 | (bp->common.chip_id & 0x0000FFFF); | |
10964 | bp->common.chip_id |= 0x1; | |
10965 | } | |
10966 | ||
523224a3 DK |
10967 | /* Set doorbell size */ |
10968 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
10969 | ||
619c5cb6 | 10970 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
10971 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
10972 | if ((val & 1) == 0) | |
10973 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
10974 | else | |
10975 | val = (val >> 1) & 1; | |
10976 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
10977 | "2_PORT_MODE"); | |
10978 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
10979 | CHIP_2_PORT_MODE; | |
10980 | ||
10981 | if (CHIP_MODE_IS_4_PORT(bp)) | |
10982 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
10983 | else | |
10984 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
10985 | } else { | |
10986 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
10987 | bp->pfid = bp->pf_num; /* 0..7 */ | |
10988 | } | |
10989 | ||
51c1a580 MS |
10990 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
10991 | ||
f2e0899f DK |
10992 | bp->link_params.chip_id = bp->common.chip_id; |
10993 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 10994 | |
1c06328c EG |
10995 | val = (REG_RD(bp, 0x2874) & 0x55); |
10996 | if ((bp->common.chip_id & 0x1) || | |
10997 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
10998 | bp->flags |= ONE_PORT_FLAG; | |
10999 | BNX2X_DEV_INFO("single port device\n"); | |
11000 | } | |
11001 | ||
34f80b04 | 11002 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 11003 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
11004 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
11005 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
11006 | bp->common.flash_size, bp->common.flash_size); | |
11007 | ||
1b6e2ceb DK |
11008 | bnx2x_init_shmem(bp); |
11009 | ||
f2e0899f DK |
11010 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
11011 | MISC_REG_GENERIC_CR_1 : | |
11012 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 11013 | |
34f80b04 | 11014 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 11015 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
b884d95b YR |
11016 | if (SHMEM2_RD(bp, size) > |
11017 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
11018 | bp->link_params.lfa_base = | |
11019 | REG_RD(bp, bp->common.shmem2_base + | |
11020 | (u32)offsetof(struct shmem2_region, | |
11021 | lfa_host_addr[BP_PORT(bp)])); | |
11022 | else | |
11023 | bp->link_params.lfa_base = 0; | |
2691d51d EG |
11024 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
11025 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 11026 | |
f2e0899f | 11027 | if (!bp->common.shmem_base) { |
34f80b04 EG |
11028 | BNX2X_DEV_INFO("MCP not active\n"); |
11029 | bp->flags |= NO_MCP_FLAG; | |
11030 | return; | |
11031 | } | |
11032 | ||
34f80b04 | 11033 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 11034 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
11035 | |
11036 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
11037 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
11038 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
11039 | ||
c2c8b03e EG |
11040 | bp->link_params.feature_config_flags = 0; |
11041 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
11042 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
11043 | bp->link_params.feature_config_flags |= | |
11044 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
11045 | else | |
11046 | bp->link_params.feature_config_flags &= | |
11047 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
11048 | ||
34f80b04 EG |
11049 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
11050 | bp->common.bc_ver = val; | |
11051 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
11052 | if (val < BNX2X_BC_VER) { | |
11053 | /* for now only warn | |
11054 | * later we might need to enforce this */ | |
51c1a580 MS |
11055 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
11056 | BNX2X_BC_VER, val); | |
34f80b04 | 11057 | } |
4d295db0 | 11058 | bp->link_params.feature_config_flags |= |
a22f0788 | 11059 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
11060 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
11061 | ||
a22f0788 YR |
11062 | bp->link_params.feature_config_flags |= |
11063 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
11064 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
a3348722 BW |
11065 | bp->link_params.feature_config_flags |= |
11066 | (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? | |
11067 | FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; | |
85242eea YR |
11068 | bp->link_params.feature_config_flags |= |
11069 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
11070 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
55386fe8 YR |
11071 | |
11072 | bp->link_params.feature_config_flags |= | |
11073 | (val >= REQ_BC_VER_4_MT_SUPPORTED) ? | |
11074 | FEATURE_CONFIG_MT_SUPPORT : 0; | |
11075 | ||
0e898dd7 BW |
11076 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
11077 | BC_SUPPORTS_PFC_STATS : 0; | |
85242eea | 11078 | |
2e499d3c BW |
11079 | bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? |
11080 | BC_SUPPORTS_FCOE_FEATURES : 0; | |
11081 | ||
9876879f BW |
11082 | bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? |
11083 | BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; | |
a6d3a5ba BW |
11084 | |
11085 | bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? | |
11086 | BC_SUPPORTS_RMMOD_CMD : 0; | |
11087 | ||
1d187b34 BW |
11088 | boot_mode = SHMEM_RD(bp, |
11089 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & | |
11090 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; | |
11091 | switch (boot_mode) { | |
11092 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: | |
11093 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; | |
11094 | break; | |
11095 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: | |
11096 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; | |
11097 | break; | |
11098 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: | |
11099 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; | |
11100 | break; | |
11101 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: | |
11102 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; | |
11103 | break; | |
11104 | } | |
11105 | ||
29ed74c3 | 11106 | pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc); |
f9a3ebbe DK |
11107 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; |
11108 | ||
72ce58c3 | 11109 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 11110 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
11111 | |
11112 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
11113 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
11114 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
11115 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
11116 | ||
cdaa7cb8 VZ |
11117 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
11118 | val, val2, val3, val4); | |
34f80b04 EG |
11119 | } |
11120 | ||
f2e0899f DK |
11121 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
11122 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
11123 | ||
0329aba1 | 11124 | static int bnx2x_get_igu_cam_info(struct bnx2x *bp) |
f2e0899f DK |
11125 | { |
11126 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
11127 | int igu_sb_id; |
11128 | u32 val; | |
6383c0b3 | 11129 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
11130 | |
11131 | bp->igu_base_sb = 0xff; | |
f2e0899f | 11132 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 11133 | int vn = BP_VN(bp); |
6383c0b3 | 11134 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
11135 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
11136 | FP_SB_MAX_E1x; | |
11137 | ||
11138 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
11139 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
11140 | ||
9b341bb1 | 11141 | return 0; |
f2e0899f DK |
11142 | } |
11143 | ||
11144 | /* IGU in normal mode - read CAM */ | |
11145 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
11146 | igu_sb_id++) { | |
11147 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
11148 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
11149 | continue; | |
11150 | fid = IGU_FID(val); | |
11151 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
11152 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
11153 | continue; | |
11154 | if (IGU_VEC(val) == 0) | |
11155 | /* default status block */ | |
11156 | bp->igu_dsb_id = igu_sb_id; | |
11157 | else { | |
11158 | if (bp->igu_base_sb == 0xff) | |
11159 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 11160 | igu_sb_cnt++; |
f2e0899f DK |
11161 | } |
11162 | } | |
11163 | } | |
619c5cb6 | 11164 | |
6383c0b3 | 11165 | #ifdef CONFIG_PCI_MSI |
185d4c8b AE |
11166 | /* Due to new PF resource allocation by MFW T7.4 and above, it's |
11167 | * optional that number of CAM entries will not be equal to the value | |
11168 | * advertised in PCI. | |
11169 | * Driver should use the minimal value of both as the actual status | |
11170 | * block count | |
619c5cb6 | 11171 | */ |
185d4c8b | 11172 | bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); |
6383c0b3 | 11173 | #endif |
619c5cb6 | 11174 | |
9b341bb1 | 11175 | if (igu_sb_cnt == 0) { |
f2e0899f | 11176 | BNX2X_ERR("CAM configuration error\n"); |
9b341bb1 BW |
11177 | return -EINVAL; |
11178 | } | |
11179 | ||
11180 | return 0; | |
f2e0899f DK |
11181 | } |
11182 | ||
1dd06ae8 | 11183 | static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) |
a2fbb9ea | 11184 | { |
a22f0788 YR |
11185 | int cfg_size = 0, idx, port = BP_PORT(bp); |
11186 | ||
11187 | /* Aggregation of supported attributes of all external phys */ | |
11188 | bp->port.supported[0] = 0; | |
11189 | bp->port.supported[1] = 0; | |
b7737c9b YR |
11190 | switch (bp->link_params.num_phys) { |
11191 | case 1: | |
a22f0788 YR |
11192 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
11193 | cfg_size = 1; | |
11194 | break; | |
b7737c9b | 11195 | case 2: |
a22f0788 YR |
11196 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
11197 | cfg_size = 1; | |
11198 | break; | |
11199 | case 3: | |
11200 | if (bp->link_params.multi_phy_config & | |
11201 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
11202 | bp->port.supported[1] = | |
11203 | bp->link_params.phy[EXT_PHY1].supported; | |
11204 | bp->port.supported[0] = | |
11205 | bp->link_params.phy[EXT_PHY2].supported; | |
11206 | } else { | |
11207 | bp->port.supported[0] = | |
11208 | bp->link_params.phy[EXT_PHY1].supported; | |
11209 | bp->port.supported[1] = | |
11210 | bp->link_params.phy[EXT_PHY2].supported; | |
11211 | } | |
11212 | cfg_size = 2; | |
11213 | break; | |
b7737c9b | 11214 | } |
a2fbb9ea | 11215 | |
a22f0788 | 11216 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
51c1a580 | 11217 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 11218 | SHMEM_RD(bp, |
a22f0788 YR |
11219 | dev_info.port_hw_config[port].external_phy_config), |
11220 | SHMEM_RD(bp, | |
11221 | dev_info.port_hw_config[port].external_phy_config2)); | |
9fb0969f | 11222 | return; |
f85582f8 | 11223 | } |
a2fbb9ea | 11224 | |
619c5cb6 VZ |
11225 | if (CHIP_IS_E3(bp)) |
11226 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
11227 | else { | |
11228 | switch (switch_cfg) { | |
11229 | case SWITCH_CFG_1G: | |
11230 | bp->port.phy_addr = REG_RD( | |
11231 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
11232 | break; | |
11233 | case SWITCH_CFG_10G: | |
11234 | bp->port.phy_addr = REG_RD( | |
11235 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
11236 | break; | |
11237 | default: | |
11238 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
11239 | bp->port.link_config[0]); | |
11240 | return; | |
11241 | } | |
a2fbb9ea | 11242 | } |
619c5cb6 | 11243 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
11244 | /* mask what we support according to speed_cap_mask per configuration */ |
11245 | for (idx = 0; idx < cfg_size; idx++) { | |
11246 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 11247 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 11248 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 11249 | |
a22f0788 | 11250 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11251 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 11252 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 11253 | |
a22f0788 | 11254 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11255 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 11256 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 11257 | |
a22f0788 | 11258 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11259 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 11260 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 11261 | |
a22f0788 | 11262 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11263 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 11264 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 11265 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 11266 | |
a22f0788 | 11267 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11268 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 11269 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 11270 | |
a22f0788 | 11271 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 11272 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 | 11273 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
b8e0d884 YR |
11274 | |
11275 | if (!(bp->link_params.speed_cap_mask[idx] & | |
11276 | PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) | |
11277 | bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; | |
a22f0788 | 11278 | } |
a2fbb9ea | 11279 | |
a22f0788 YR |
11280 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
11281 | bp->port.supported[1]); | |
a2fbb9ea ET |
11282 | } |
11283 | ||
0329aba1 | 11284 | static void bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 11285 | { |
a22f0788 YR |
11286 | u32 link_config, idx, cfg_size = 0; |
11287 | bp->port.advertising[0] = 0; | |
11288 | bp->port.advertising[1] = 0; | |
11289 | switch (bp->link_params.num_phys) { | |
11290 | case 1: | |
11291 | case 2: | |
11292 | cfg_size = 1; | |
11293 | break; | |
11294 | case 3: | |
11295 | cfg_size = 2; | |
11296 | break; | |
11297 | } | |
11298 | for (idx = 0; idx < cfg_size; idx++) { | |
11299 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
11300 | link_config = bp->port.link_config[idx]; | |
11301 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 11302 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
11303 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
11304 | bp->link_params.req_line_speed[idx] = | |
11305 | SPEED_AUTO_NEG; | |
11306 | bp->port.advertising[idx] |= | |
11307 | bp->port.supported[idx]; | |
10bd1f24 MY |
11308 | if (bp->link_params.phy[EXT_PHY1].type == |
11309 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
11310 | bp->port.advertising[idx] |= | |
11311 | (SUPPORTED_100baseT_Half | | |
11312 | SUPPORTED_100baseT_Full); | |
f85582f8 DK |
11313 | } else { |
11314 | /* force 10G, no AN */ | |
a22f0788 YR |
11315 | bp->link_params.req_line_speed[idx] = |
11316 | SPEED_10000; | |
11317 | bp->port.advertising[idx] |= | |
11318 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 11319 | ADVERTISED_FIBRE); |
a22f0788 | 11320 | continue; |
f85582f8 DK |
11321 | } |
11322 | break; | |
a2fbb9ea | 11323 | |
f85582f8 | 11324 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
11325 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
11326 | bp->link_params.req_line_speed[idx] = | |
11327 | SPEED_10; | |
11328 | bp->port.advertising[idx] |= | |
11329 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
11330 | ADVERTISED_TP); |
11331 | } else { | |
51c1a580 | 11332 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 | 11333 | link_config, |
a22f0788 | 11334 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
11335 | return; |
11336 | } | |
11337 | break; | |
a2fbb9ea | 11338 | |
f85582f8 | 11339 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
11340 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
11341 | bp->link_params.req_line_speed[idx] = | |
11342 | SPEED_10; | |
11343 | bp->link_params.req_duplex[idx] = | |
11344 | DUPLEX_HALF; | |
11345 | bp->port.advertising[idx] |= | |
11346 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
11347 | ADVERTISED_TP); |
11348 | } else { | |
51c1a580 | 11349 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
11350 | link_config, |
11351 | bp->link_params.speed_cap_mask[idx]); | |
11352 | return; | |
11353 | } | |
11354 | break; | |
a2fbb9ea | 11355 | |
f85582f8 DK |
11356 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
11357 | if (bp->port.supported[idx] & | |
11358 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
11359 | bp->link_params.req_line_speed[idx] = |
11360 | SPEED_100; | |
11361 | bp->port.advertising[idx] |= | |
11362 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
11363 | ADVERTISED_TP); |
11364 | } else { | |
51c1a580 | 11365 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
11366 | link_config, |
11367 | bp->link_params.speed_cap_mask[idx]); | |
11368 | return; | |
11369 | } | |
11370 | break; | |
a2fbb9ea | 11371 | |
f85582f8 DK |
11372 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
11373 | if (bp->port.supported[idx] & | |
11374 | SUPPORTED_100baseT_Half) { | |
11375 | bp->link_params.req_line_speed[idx] = | |
11376 | SPEED_100; | |
11377 | bp->link_params.req_duplex[idx] = | |
11378 | DUPLEX_HALF; | |
a22f0788 YR |
11379 | bp->port.advertising[idx] |= |
11380 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
11381 | ADVERTISED_TP); |
11382 | } else { | |
51c1a580 | 11383 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
11384 | link_config, |
11385 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
11386 | return; |
11387 | } | |
11388 | break; | |
a2fbb9ea | 11389 | |
f85582f8 | 11390 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
11391 | if (bp->port.supported[idx] & |
11392 | SUPPORTED_1000baseT_Full) { | |
11393 | bp->link_params.req_line_speed[idx] = | |
11394 | SPEED_1000; | |
11395 | bp->port.advertising[idx] |= | |
11396 | (ADVERTISED_1000baseT_Full | | |
f85582f8 | 11397 | ADVERTISED_TP); |
5d67c1c5 YM |
11398 | } else if (bp->port.supported[idx] & |
11399 | SUPPORTED_1000baseKX_Full) { | |
11400 | bp->link_params.req_line_speed[idx] = | |
11401 | SPEED_1000; | |
11402 | bp->port.advertising[idx] |= | |
11403 | ADVERTISED_1000baseKX_Full; | |
f85582f8 | 11404 | } else { |
51c1a580 | 11405 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
11406 | link_config, |
11407 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
11408 | return; |
11409 | } | |
11410 | break; | |
a2fbb9ea | 11411 | |
f85582f8 | 11412 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
11413 | if (bp->port.supported[idx] & |
11414 | SUPPORTED_2500baseX_Full) { | |
11415 | bp->link_params.req_line_speed[idx] = | |
11416 | SPEED_2500; | |
11417 | bp->port.advertising[idx] |= | |
11418 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 11419 | ADVERTISED_TP); |
f85582f8 | 11420 | } else { |
51c1a580 | 11421 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 11422 | link_config, |
f85582f8 DK |
11423 | bp->link_params.speed_cap_mask[idx]); |
11424 | return; | |
11425 | } | |
11426 | break; | |
a2fbb9ea | 11427 | |
f85582f8 | 11428 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
11429 | if (bp->port.supported[idx] & |
11430 | SUPPORTED_10000baseT_Full) { | |
11431 | bp->link_params.req_line_speed[idx] = | |
11432 | SPEED_10000; | |
11433 | bp->port.advertising[idx] |= | |
11434 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 11435 | ADVERTISED_FIBRE); |
5d67c1c5 YM |
11436 | } else if (bp->port.supported[idx] & |
11437 | SUPPORTED_10000baseKR_Full) { | |
11438 | bp->link_params.req_line_speed[idx] = | |
11439 | SPEED_10000; | |
11440 | bp->port.advertising[idx] |= | |
11441 | (ADVERTISED_10000baseKR_Full | | |
11442 | ADVERTISED_FIBRE); | |
f85582f8 | 11443 | } else { |
51c1a580 | 11444 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 11445 | link_config, |
f85582f8 DK |
11446 | bp->link_params.speed_cap_mask[idx]); |
11447 | return; | |
11448 | } | |
11449 | break; | |
3c9ada22 YR |
11450 | case PORT_FEATURE_LINK_SPEED_20G: |
11451 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 11452 | |
3c9ada22 | 11453 | break; |
f85582f8 | 11454 | default: |
51c1a580 | 11455 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
754a2f52 | 11456 | link_config); |
f85582f8 DK |
11457 | bp->link_params.req_line_speed[idx] = |
11458 | SPEED_AUTO_NEG; | |
11459 | bp->port.advertising[idx] = | |
11460 | bp->port.supported[idx]; | |
11461 | break; | |
11462 | } | |
a2fbb9ea | 11463 | |
a22f0788 | 11464 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 11465 | PORT_FEATURE_FLOW_CONTROL_MASK); |
cd1dfce2 YM |
11466 | if (bp->link_params.req_flow_ctrl[idx] == |
11467 | BNX2X_FLOW_CTRL_AUTO) { | |
11468 | if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) | |
11469 | bp->link_params.req_flow_ctrl[idx] = | |
11470 | BNX2X_FLOW_CTRL_NONE; | |
11471 | else | |
11472 | bnx2x_set_requested_fc(bp); | |
a22f0788 | 11473 | } |
a2fbb9ea | 11474 | |
51c1a580 | 11475 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
a22f0788 YR |
11476 | bp->link_params.req_line_speed[idx], |
11477 | bp->link_params.req_duplex[idx], | |
11478 | bp->link_params.req_flow_ctrl[idx], | |
11479 | bp->port.advertising[idx]); | |
11480 | } | |
a2fbb9ea ET |
11481 | } |
11482 | ||
0329aba1 | 11483 | static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
e665bfda | 11484 | { |
86564c3f YM |
11485 | __be16 mac_hi_be = cpu_to_be16(mac_hi); |
11486 | __be32 mac_lo_be = cpu_to_be32(mac_lo); | |
11487 | memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be)); | |
11488 | memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be)); | |
e665bfda MC |
11489 | } |
11490 | ||
0329aba1 | 11491 | static void bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 11492 | { |
34f80b04 | 11493 | int port = BP_PORT(bp); |
589abe3a | 11494 | u32 config; |
c8c60d88 | 11495 | u32 ext_phy_type, ext_phy_config, eee_mode; |
a2fbb9ea | 11496 | |
c18487ee | 11497 | bp->link_params.bp = bp; |
34f80b04 | 11498 | bp->link_params.port = port; |
c18487ee | 11499 | |
c18487ee | 11500 | bp->link_params.lane_config = |
a2fbb9ea | 11501 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 11502 | |
a22f0788 | 11503 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea | 11504 | SHMEM_RD(bp, |
b0261926 YR |
11505 | dev_info.port_hw_config[port].speed_capability_mask) & |
11506 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | |
a22f0788 YR |
11507 | bp->link_params.speed_cap_mask[1] = |
11508 | SHMEM_RD(bp, | |
b0261926 YR |
11509 | dev_info.port_hw_config[port].speed_capability_mask2) & |
11510 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | |
a22f0788 | 11511 | bp->port.link_config[0] = |
a2fbb9ea ET |
11512 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
11513 | ||
a22f0788 YR |
11514 | bp->port.link_config[1] = |
11515 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 11516 | |
a22f0788 YR |
11517 | bp->link_params.multi_phy_config = |
11518 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
11519 | /* If the device is capable of WoL, set the default state according |
11520 | * to the HW | |
11521 | */ | |
4d295db0 | 11522 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
11523 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
11524 | (config & PORT_FEATURE_WOL_ENABLED)); | |
11525 | ||
4ba7699b YM |
11526 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == |
11527 | PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) | |
11528 | bp->flags |= NO_ISCSI_FLAG; | |
11529 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == | |
11530 | PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) | |
11531 | bp->flags |= NO_FCOE_FLAG; | |
11532 | ||
51c1a580 | 11533 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 11534 | bp->link_params.lane_config, |
a22f0788 YR |
11535 | bp->link_params.speed_cap_mask[0], |
11536 | bp->port.link_config[0]); | |
a2fbb9ea | 11537 | |
a22f0788 | 11538 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 11539 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 11540 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 11541 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
11542 | |
11543 | bnx2x_link_settings_requested(bp); | |
11544 | ||
01cd4528 EG |
11545 | /* |
11546 | * If connected directly, work with the internal PHY, otherwise, work | |
11547 | * with the external PHY | |
11548 | */ | |
b7737c9b YR |
11549 | ext_phy_config = |
11550 | SHMEM_RD(bp, | |
11551 | dev_info.port_hw_config[port].external_phy_config); | |
11552 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 11553 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 11554 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
11555 | |
11556 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
11557 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
11558 | bp->mdio.prtad = | |
b7737c9b | 11559 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d | 11560 | |
c8c60d88 YM |
11561 | /* Configure link feature according to nvram value */ |
11562 | eee_mode = (((SHMEM_RD(bp, dev_info. | |
11563 | port_feature_config[port].eee_power_mode)) & | |
11564 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
11565 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
11566 | if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { | |
11567 | bp->link_params.eee_mode = EEE_MODE_ADV_LPI | | |
11568 | EEE_MODE_ENABLE_LPI | | |
11569 | EEE_MODE_OUTPUT_TIME; | |
11570 | } else { | |
11571 | bp->link_params.eee_mode = 0; | |
11572 | } | |
0793f83f | 11573 | } |
01cd4528 | 11574 | |
b306f5ed | 11575 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 11576 | { |
9e62e912 | 11577 | u32 no_flags = NO_ISCSI_FLAG; |
bf61ee14 | 11578 | int port = BP_PORT(bp); |
2ba45142 | 11579 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 11580 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 11581 | |
55c11941 MS |
11582 | if (!CNIC_SUPPORT(bp)) { |
11583 | bp->flags |= no_flags; | |
11584 | return; | |
11585 | } | |
11586 | ||
b306f5ed | 11587 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
11588 | bp->cnic_eth_dev.max_iscsi_conn = |
11589 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
11590 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
11591 | ||
b306f5ed DK |
11592 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
11593 | bp->cnic_eth_dev.max_iscsi_conn); | |
11594 | ||
11595 | /* | |
11596 | * If maximum allowed number of connections is zero - | |
11597 | * disable the feature. | |
11598 | */ | |
11599 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9e62e912 | 11600 | bp->flags |= no_flags; |
b306f5ed DK |
11601 | } |
11602 | ||
0329aba1 | 11603 | static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) |
9e62e912 DK |
11604 | { |
11605 | /* Port info */ | |
11606 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
11607 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); | |
11608 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
11609 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); | |
11610 | ||
11611 | /* Node info */ | |
11612 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
11613 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); | |
11614 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
11615 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); | |
11616 | } | |
86800194 DK |
11617 | |
11618 | static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) | |
11619 | { | |
11620 | u8 count = 0; | |
11621 | ||
11622 | if (IS_MF(bp)) { | |
11623 | u8 fid; | |
11624 | ||
11625 | /* iterate over absolute function ids for this path: */ | |
11626 | for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { | |
11627 | if (IS_MF_SD(bp)) { | |
11628 | u32 cfg = MF_CFG_RD(bp, | |
11629 | func_mf_config[fid].config); | |
11630 | ||
11631 | if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) && | |
11632 | ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) == | |
11633 | FUNC_MF_CFG_PROTOCOL_FCOE)) | |
11634 | count++; | |
11635 | } else { | |
11636 | u32 cfg = MF_CFG_RD(bp, | |
11637 | func_ext_config[fid]. | |
11638 | func_cfg); | |
11639 | ||
11640 | if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) && | |
11641 | (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)) | |
11642 | count++; | |
11643 | } | |
11644 | } | |
11645 | } else { /* SF */ | |
11646 | int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; | |
11647 | ||
11648 | for (port = 0; port < port_cnt; port++) { | |
11649 | u32 lic = SHMEM_RD(bp, | |
11650 | drv_lic_key[port].max_fcoe_conn) ^ | |
11651 | FW_ENCODE_32BIT_PATTERN; | |
11652 | if (lic) | |
11653 | count++; | |
11654 | } | |
11655 | } | |
11656 | ||
11657 | return count; | |
11658 | } | |
11659 | ||
0329aba1 | 11660 | static void bnx2x_get_fcoe_info(struct bnx2x *bp) |
b306f5ed DK |
11661 | { |
11662 | int port = BP_PORT(bp); | |
11663 | int func = BP_ABS_FUNC(bp); | |
b306f5ed DK |
11664 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
11665 | drv_lic_key[port].max_fcoe_conn); | |
86800194 | 11666 | u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); |
b306f5ed | 11667 | |
55c11941 MS |
11668 | if (!CNIC_SUPPORT(bp)) { |
11669 | bp->flags |= NO_FCOE_FLAG; | |
11670 | return; | |
11671 | } | |
11672 | ||
b306f5ed | 11673 | /* Get the number of maximum allowed FCoE connections */ |
2ba45142 VZ |
11674 | bp->cnic_eth_dev.max_fcoe_conn = |
11675 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
11676 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
11677 | ||
0eb43b4b BPG |
11678 | /* Calculate the number of maximum allowed FCoE tasks */ |
11679 | bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; | |
86800194 DK |
11680 | |
11681 | /* check if FCoE resources must be shared between different functions */ | |
11682 | if (num_fcoe_func) | |
11683 | bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; | |
0eb43b4b | 11684 | |
bf61ee14 VZ |
11685 | /* Read the WWN: */ |
11686 | if (!IS_MF(bp)) { | |
11687 | /* Port info */ | |
11688 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
11689 | SHMEM_RD(bp, | |
2de67439 | 11690 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11691 | fcoe_wwn_port_name_upper); |
11692 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
11693 | SHMEM_RD(bp, | |
2de67439 | 11694 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11695 | fcoe_wwn_port_name_lower); |
11696 | ||
11697 | /* Node info */ | |
11698 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
11699 | SHMEM_RD(bp, | |
2de67439 | 11700 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11701 | fcoe_wwn_node_name_upper); |
11702 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
11703 | SHMEM_RD(bp, | |
2de67439 | 11704 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
11705 | fcoe_wwn_node_name_lower); |
11706 | } else if (!IS_MF_SD(bp)) { | |
2e98ffc2 | 11707 | /* Read the WWN info only if the FCoE feature is enabled for |
bf61ee14 VZ |
11708 | * this function. |
11709 | */ | |
2e98ffc2 DK |
11710 | if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp)) |
11711 | bnx2x_get_ext_wwn_info(bp, func); | |
11712 | } else { | |
11713 | if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) | |
9e62e912 | 11714 | bnx2x_get_ext_wwn_info(bp, func); |
382e513a | 11715 | } |
bf61ee14 | 11716 | |
b306f5ed | 11717 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 11718 | |
bf61ee14 VZ |
11719 | /* |
11720 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
11721 | * disable the feature. |
11722 | */ | |
bbf666c1 | 11723 | if (!bp->cnic_eth_dev.max_fcoe_conn) { |
2ba45142 | 11724 | bp->flags |= NO_FCOE_FLAG; |
bbf666c1 SRK |
11725 | eth_zero_addr(bp->fip_mac); |
11726 | } | |
2ba45142 | 11727 | } |
b306f5ed | 11728 | |
0329aba1 | 11729 | static void bnx2x_get_cnic_info(struct bnx2x *bp) |
b306f5ed DK |
11730 | { |
11731 | /* | |
11732 | * iSCSI may be dynamically disabled but reading | |
11733 | * info here we will decrease memory usage by driver | |
11734 | * if the feature is disabled for good | |
11735 | */ | |
11736 | bnx2x_get_iscsi_info(bp); | |
11737 | bnx2x_get_fcoe_info(bp); | |
11738 | } | |
2ba45142 | 11739 | |
0329aba1 | 11740 | static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) |
0793f83f DK |
11741 | { |
11742 | u32 val, val2; | |
11743 | int func = BP_ABS_FUNC(bp); | |
11744 | int port = BP_PORT(bp); | |
2ba45142 VZ |
11745 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; |
11746 | u8 *fip_mac = bp->fip_mac; | |
0793f83f | 11747 | |
55c11941 MS |
11748 | if (IS_MF(bp)) { |
11749 | /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or | |
2ba45142 | 11750 | * FCoE MAC then the appropriate feature should be disabled. |
55c11941 MS |
11751 | * In non SD mode features configuration comes from struct |
11752 | * func_ext_config. | |
2ba45142 | 11753 | */ |
2e98ffc2 | 11754 | if (!IS_MF_SD(bp)) { |
0793f83f DK |
11755 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
11756 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
11757 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 11758 | iscsi_mac_addr_upper); |
0793f83f | 11759 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 11760 | iscsi_mac_addr_lower); |
2ba45142 | 11761 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
55c11941 MS |
11762 | BNX2X_DEV_INFO |
11763 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
11764 | } else { | |
2ba45142 | 11765 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
55c11941 | 11766 | } |
2ba45142 VZ |
11767 | |
11768 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
11769 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 11770 | fcoe_mac_addr_upper); |
2ba45142 | 11771 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 11772 | fcoe_mac_addr_lower); |
2ba45142 | 11773 | bnx2x_set_mac_buf(fip_mac, val, val2); |
55c11941 MS |
11774 | BNX2X_DEV_INFO |
11775 | ("Read FCoE L2 MAC: %pM\n", fip_mac); | |
11776 | } else { | |
2ba45142 | 11777 | bp->flags |= NO_FCOE_FLAG; |
55c11941 | 11778 | } |
a3348722 BW |
11779 | |
11780 | bp->mf_ext_config = cfg; | |
11781 | ||
9e62e912 | 11782 | } else { /* SD MODE */ |
55c11941 MS |
11783 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { |
11784 | /* use primary mac as iscsi mac */ | |
11785 | memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); | |
11786 | ||
11787 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); | |
11788 | BNX2X_DEV_INFO | |
11789 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
11790 | } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { | |
11791 | /* use primary mac as fip mac */ | |
11792 | memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); | |
11793 | BNX2X_DEV_INFO("SD FCoE MODE\n"); | |
11794 | BNX2X_DEV_INFO | |
11795 | ("Read FIP MAC: %pM\n", fip_mac); | |
614c76df | 11796 | } |
0793f83f | 11797 | } |
a3348722 | 11798 | |
82594f8f YM |
11799 | /* If this is a storage-only interface, use SAN mac as |
11800 | * primary MAC. Notice that for SD this is already the case, | |
11801 | * as the SAN mac was copied from the primary MAC. | |
11802 | */ | |
11803 | if (IS_MF_FCOE_AFEX(bp)) | |
a3348722 | 11804 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); |
0793f83f | 11805 | } else { |
0793f83f | 11806 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11807 | iscsi_mac_upper); |
0793f83f | 11808 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11809 | iscsi_mac_lower); |
2ba45142 | 11810 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
11811 | |
11812 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
55c11941 | 11813 | fcoe_fip_mac_upper); |
c03bd39c | 11814 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11815 | fcoe_fip_mac_lower); |
c03bd39c | 11816 | bnx2x_set_mac_buf(fip_mac, val, val2); |
0793f83f DK |
11817 | } |
11818 | ||
55c11941 | 11819 | /* Disable iSCSI OOO if MAC configuration is invalid. */ |
426b9241 | 11820 | if (!is_valid_ether_addr(iscsi_mac)) { |
55c11941 | 11821 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
c7bf7169 | 11822 | eth_zero_addr(iscsi_mac); |
426b9241 DK |
11823 | } |
11824 | ||
55c11941 | 11825 | /* Disable FCoE if MAC configuration is invalid. */ |
426b9241 DK |
11826 | if (!is_valid_ether_addr(fip_mac)) { |
11827 | bp->flags |= NO_FCOE_FLAG; | |
c7bf7169 | 11828 | eth_zero_addr(bp->fip_mac); |
426b9241 | 11829 | } |
55c11941 MS |
11830 | } |
11831 | ||
0329aba1 | 11832 | static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
55c11941 MS |
11833 | { |
11834 | u32 val, val2; | |
11835 | int func = BP_ABS_FUNC(bp); | |
11836 | int port = BP_PORT(bp); | |
11837 | ||
11838 | /* Zero primary MAC configuration */ | |
c7bf7169 | 11839 | eth_zero_addr(bp->dev->dev_addr); |
55c11941 MS |
11840 | |
11841 | if (BP_NOMCP(bp)) { | |
11842 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
11843 | eth_hw_addr_random(bp->dev); | |
11844 | } else if (IS_MF(bp)) { | |
11845 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
11846 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
11847 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
11848 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
11849 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
11850 | ||
11851 | if (CNIC_SUPPORT(bp)) | |
11852 | bnx2x_get_cnic_mac_hwinfo(bp); | |
11853 | } else { | |
11854 | /* in SF read MACs from port configuration */ | |
11855 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
11856 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
11857 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
11858 | ||
11859 | if (CNIC_SUPPORT(bp)) | |
11860 | bnx2x_get_cnic_mac_hwinfo(bp); | |
11861 | } | |
11862 | ||
3d7d562c YM |
11863 | if (!BP_NOMCP(bp)) { |
11864 | /* Read physical port identifier from shmem */ | |
11865 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
11866 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
11867 | bnx2x_set_mac_buf(bp->phys_port_id, val, val2); | |
11868 | bp->flags |= HAS_PHYS_PORT_ID; | |
11869 | } | |
11870 | ||
55c11941 | 11871 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); |
619c5cb6 | 11872 | |
2e98ffc2 | 11873 | if (!is_valid_ether_addr(bp->dev->dev_addr)) |
619c5cb6 | 11874 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11875 | "bad Ethernet MAC address configuration: %pM\n" |
11876 | "change it manually before bringing up the appropriate network interface\n", | |
0f9dad10 | 11877 | bp->dev->dev_addr); |
7964211d | 11878 | } |
51c1a580 | 11879 | |
0329aba1 | 11880 | static bool bnx2x_get_dropless_info(struct bnx2x *bp) |
7964211d YM |
11881 | { |
11882 | int tmp; | |
11883 | u32 cfg; | |
51c1a580 | 11884 | |
aeeddb8b | 11885 | if (IS_VF(bp)) |
4e833c59 | 11886 | return false; |
aeeddb8b | 11887 | |
7964211d YM |
11888 | if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { |
11889 | /* Take function: tmp = func */ | |
11890 | tmp = BP_ABS_FUNC(bp); | |
11891 | cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); | |
11892 | cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); | |
11893 | } else { | |
11894 | /* Take port: tmp = port */ | |
11895 | tmp = BP_PORT(bp); | |
11896 | cfg = SHMEM_RD(bp, | |
11897 | dev_info.port_hw_config[tmp].generic_features); | |
11898 | cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); | |
11899 | } | |
11900 | return cfg; | |
34f80b04 EG |
11901 | } |
11902 | ||
83bad206 YM |
11903 | static void validate_set_si_mode(struct bnx2x *bp) |
11904 | { | |
11905 | u8 func = BP_ABS_FUNC(bp); | |
11906 | u32 val; | |
11907 | ||
11908 | val = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
11909 | ||
11910 | /* check for legal mac (upper bytes) */ | |
11911 | if (val != 0xffff) { | |
11912 | bp->mf_mode = MULTI_FUNCTION_SI; | |
11913 | bp->mf_config[BP_VN(bp)] = | |
11914 | MF_CFG_RD(bp, func_mf_config[func].config); | |
11915 | } else | |
11916 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); | |
11917 | } | |
11918 | ||
0329aba1 | 11919 | static int bnx2x_get_hwinfo(struct bnx2x *bp) |
34f80b04 | 11920 | { |
0793f83f | 11921 | int /*abs*/func = BP_ABS_FUNC(bp); |
c9b747db | 11922 | int vn; |
83bad206 | 11923 | u32 val = 0, val2 = 0; |
34f80b04 | 11924 | int rc = 0; |
a2fbb9ea | 11925 | |
0f587f1b YM |
11926 | /* Validate that chip access is feasible */ |
11927 | if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) { | |
11928 | dev_err(&bp->pdev->dev, | |
11929 | "Chip read returns all Fs. Preventing probe from continuing\n"); | |
11930 | return -EINVAL; | |
11931 | } | |
11932 | ||
34f80b04 | 11933 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 11934 | |
6383c0b3 AE |
11935 | /* |
11936 | * initialize IGU parameters | |
11937 | */ | |
f2e0899f DK |
11938 | if (CHIP_IS_E1x(bp)) { |
11939 | bp->common.int_block = INT_BLOCK_HC; | |
11940 | ||
11941 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
11942 | bp->igu_base_sb = 0; | |
f2e0899f DK |
11943 | } else { |
11944 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 | 11945 | |
16a5fd92 | 11946 | /* do not allow device reset during IGU info processing */ |
7a06a122 DK |
11947 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
11948 | ||
f2e0899f | 11949 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
11950 | |
11951 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
11952 | int tout = 5000; | |
11953 | ||
11954 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
11955 | ||
11956 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
11957 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
11958 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
11959 | ||
11960 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
11961 | tout--; | |
0926d499 | 11962 | usleep_range(1000, 2000); |
619c5cb6 VZ |
11963 | } |
11964 | ||
11965 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
11966 | dev_err(&bp->pdev->dev, | |
11967 | "FORCING Normal Mode failed!!!\n"); | |
9b341bb1 BW |
11968 | bnx2x_release_hw_lock(bp, |
11969 | HW_LOCK_RESOURCE_RESET); | |
619c5cb6 VZ |
11970 | return -EPERM; |
11971 | } | |
11972 | } | |
11973 | ||
f2e0899f | 11974 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 11975 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
11976 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
11977 | } else | |
619c5cb6 | 11978 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 11979 | |
9b341bb1 | 11980 | rc = bnx2x_get_igu_cam_info(bp); |
7a06a122 | 11981 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
9b341bb1 BW |
11982 | if (rc) |
11983 | return rc; | |
f2e0899f | 11984 | } |
619c5cb6 VZ |
11985 | |
11986 | /* | |
11987 | * set base FW non-default (fast path) status block id, this value is | |
11988 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
11989 | * determine the id used by the FW. | |
11990 | */ | |
11991 | if (CHIP_IS_E1x(bp)) | |
11992 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
11993 | else /* | |
11994 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
11995 | * the same queue are indicated on the same IGU SB). So we prefer | |
11996 | * FW and IGU SBs to be the same value. | |
11997 | */ | |
11998 | bp->base_fw_ndsb = bp->igu_base_sb; | |
11999 | ||
12000 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
12001 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
12002 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
12003 | |
12004 | /* | |
12005 | * Initialize MF configuration | |
12006 | */ | |
fb3bff17 DK |
12007 | bp->mf_ov = 0; |
12008 | bp->mf_mode = 0; | |
7609647e | 12009 | bp->mf_sub_mode = 0; |
3395a033 | 12010 | vn = BP_VN(bp); |
0793f83f | 12011 | |
f2e0899f | 12012 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
12013 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
12014 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
12015 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
12016 | ||
f2e0899f DK |
12017 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
12018 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
12019 | else | |
12020 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
12021 | offsetof(struct shmem_region, func_mb) + |
12022 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
12023 | /* |
12024 | * get mf configuration: | |
16a5fd92 | 12025 | * 1. Existence of MF configuration |
0793f83f DK |
12026 | * 2. MAC address must be legal (check only upper bytes) |
12027 | * for Switch-Independent mode; | |
12028 | * OVLAN must be legal for Switch-Dependent mode | |
12029 | * 3. SF_MODE configures specific MF mode | |
12030 | */ | |
12031 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
12032 | /* get mf configuration */ | |
12033 | val = SHMEM_RD(bp, | |
12034 | dev_info.shared_feature_config.config); | |
12035 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
12036 | ||
12037 | switch (val) { | |
12038 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
83bad206 | 12039 | validate_set_si_mode(bp); |
0793f83f | 12040 | break; |
a3348722 BW |
12041 | case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: |
12042 | if ((!CHIP_IS_E1x(bp)) && | |
12043 | (MF_CFG_RD(bp, func_mf_config[func]. | |
12044 | mac_upper) != 0xffff) && | |
12045 | (SHMEM2_HAS(bp, | |
12046 | afex_driver_support))) { | |
12047 | bp->mf_mode = MULTI_FUNCTION_AFEX; | |
12048 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
12049 | func_mf_config[func].config); | |
12050 | } else { | |
12051 | BNX2X_DEV_INFO("can not configure afex mode\n"); | |
12052 | } | |
12053 | break; | |
0793f83f DK |
12054 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: |
12055 | /* get OV configuration */ | |
12056 | val = MF_CFG_RD(bp, | |
12057 | func_mf_config[FUNC_0].e1hov_tag); | |
12058 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
12059 | ||
12060 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
12061 | bp->mf_mode = MULTI_FUNCTION_SD; | |
12062 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
12063 | func_mf_config[func].config); | |
12064 | } else | |
754a2f52 | 12065 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f | 12066 | break; |
230d00eb YM |
12067 | case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE: |
12068 | bp->mf_mode = MULTI_FUNCTION_SD; | |
12069 | bp->mf_sub_mode = SUB_MF_MODE_BD; | |
12070 | bp->mf_config[vn] = | |
12071 | MF_CFG_RD(bp, | |
12072 | func_mf_config[func].config); | |
12073 | ||
12074 | if (SHMEM2_HAS(bp, mtu_size)) { | |
12075 | int mtu_idx = BP_FW_MB_IDX(bp); | |
12076 | u16 mtu_size; | |
12077 | u32 mtu; | |
12078 | ||
12079 | mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]); | |
12080 | mtu_size = (u16)mtu; | |
12081 | DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n", | |
12082 | mtu_size, mtu); | |
12083 | ||
12084 | /* if valid: update device mtu */ | |
e1c6dcca | 12085 | if ((mtu_size >= ETH_MIN_PACKET_SIZE) && |
230d00eb YM |
12086 | (mtu_size <= |
12087 | ETH_MAX_JUMBO_PACKET_SIZE)) | |
12088 | bp->dev->mtu = mtu_size; | |
12089 | } | |
12090 | break; | |
7609647e YM |
12091 | case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE: |
12092 | bp->mf_mode = MULTI_FUNCTION_SD; | |
12093 | bp->mf_sub_mode = SUB_MF_MODE_UFP; | |
12094 | bp->mf_config[vn] = | |
12095 | MF_CFG_RD(bp, | |
12096 | func_mf_config[func].config); | |
12097 | break; | |
3786b942 AE |
12098 | case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: |
12099 | bp->mf_config[vn] = 0; | |
12100 | break; | |
83bad206 YM |
12101 | case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE: |
12102 | val2 = SHMEM_RD(bp, | |
12103 | dev_info.shared_hw_config.config_3); | |
12104 | val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK; | |
12105 | switch (val2) { | |
12106 | case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5: | |
12107 | validate_set_si_mode(bp); | |
12108 | bp->mf_sub_mode = | |
12109 | SUB_MF_MODE_NPAR1_DOT_5; | |
12110 | break; | |
12111 | default: | |
12112 | /* Unknown configuration */ | |
12113 | bp->mf_config[vn] = 0; | |
12114 | BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n", | |
12115 | val); | |
12116 | } | |
12117 | break; | |
0793f83f DK |
12118 | default: |
12119 | /* Unknown configuration: reset mf_config */ | |
12120 | bp->mf_config[vn] = 0; | |
51c1a580 | 12121 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
0793f83f DK |
12122 | } |
12123 | } | |
a2fbb9ea | 12124 | |
2691d51d | 12125 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 12126 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 12127 | |
0793f83f DK |
12128 | switch (bp->mf_mode) { |
12129 | case MULTI_FUNCTION_SD: | |
12130 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
12131 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 12132 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 12133 | bp->mf_ov = val; |
619c5cb6 VZ |
12134 | bp->path_has_ovlan = true; |
12135 | ||
51c1a580 MS |
12136 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
12137 | func, bp->mf_ov, bp->mf_ov); | |
230d00eb YM |
12138 | } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) || |
12139 | (bp->mf_sub_mode == SUB_MF_MODE_BD)) { | |
7609647e | 12140 | dev_err(&bp->pdev->dev, |
230d00eb | 12141 | "Unexpected - no valid MF OV for func %d in UFP/BD mode\n", |
7609647e YM |
12142 | func); |
12143 | bp->path_has_ovlan = true; | |
2691d51d | 12144 | } else { |
619c5cb6 | 12145 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
12146 | "No valid MF OV for func %d, aborting\n", |
12147 | func); | |
619c5cb6 | 12148 | return -EPERM; |
34f80b04 | 12149 | } |
0793f83f | 12150 | break; |
a3348722 BW |
12151 | case MULTI_FUNCTION_AFEX: |
12152 | BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); | |
12153 | break; | |
0793f83f | 12154 | case MULTI_FUNCTION_SI: |
51c1a580 MS |
12155 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
12156 | func); | |
0793f83f DK |
12157 | break; |
12158 | default: | |
12159 | if (vn) { | |
619c5cb6 | 12160 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
12161 | "VN %d is in a single function mode, aborting\n", |
12162 | vn); | |
619c5cb6 | 12163 | return -EPERM; |
2691d51d | 12164 | } |
0793f83f | 12165 | break; |
34f80b04 | 12166 | } |
0793f83f | 12167 | |
619c5cb6 VZ |
12168 | /* check if other port on the path needs ovlan: |
12169 | * Since MF configuration is shared between ports | |
12170 | * Possible mixed modes are only | |
12171 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
12172 | */ | |
12173 | if (CHIP_MODE_IS_4_PORT(bp) && | |
12174 | !bp->path_has_ovlan && | |
12175 | !IS_MF(bp) && | |
12176 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
12177 | u8 other_port = !BP_PORT(bp); | |
12178 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
12179 | val = MF_CFG_RD(bp, | |
12180 | func_mf_config[other_func].e1hov_tag); | |
12181 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
12182 | bp->path_has_ovlan = true; | |
12183 | } | |
34f80b04 | 12184 | } |
a2fbb9ea | 12185 | |
e848582c DK |
12186 | /* adjust igu_sb_cnt to MF for E1H */ |
12187 | if (CHIP_IS_E1H(bp) && IS_MF(bp)) | |
12188 | bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT); | |
523224a3 | 12189 | |
619c5cb6 VZ |
12190 | /* port info */ |
12191 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 12192 | |
0793f83f DK |
12193 | /* Get MAC addresses */ |
12194 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 12195 | |
2ba45142 | 12196 | bnx2x_get_cnic_info(bp); |
2ba45142 | 12197 | |
34f80b04 EG |
12198 | return rc; |
12199 | } | |
12200 | ||
0329aba1 | 12201 | static void bnx2x_read_fwinfo(struct bnx2x *bp) |
34f24c7f | 12202 | { |
3831cba0 HK |
12203 | char str_id[VENDOR_ID_LEN + 1]; |
12204 | unsigned int vpd_len, kw_len; | |
12205 | u8 *vpd_data; | |
12206 | int rodi; | |
4fb2c383 | 12207 | |
34f24c7f | 12208 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
4a55c34e | 12209 | |
df875894 HK |
12210 | vpd_data = pci_vpd_alloc(bp->pdev, &vpd_len); |
12211 | if (IS_ERR(vpd_data)) | |
12212 | return; | |
4a55c34e | 12213 | |
3831cba0 HK |
12214 | rodi = pci_vpd_find_ro_info_keyword(vpd_data, vpd_len, |
12215 | PCI_VPD_RO_KEYWORD_MFR_ID, &kw_len); | |
12216 | if (rodi < 0 || kw_len != VENDOR_ID_LEN) | |
34f24c7f VZ |
12217 | goto out_not_found; |
12218 | ||
34f24c7f | 12219 | /* vendor specific info */ |
3831cba0 HK |
12220 | snprintf(str_id, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); |
12221 | if (!strncasecmp(str_id, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
12222 | rodi = pci_vpd_find_ro_info_keyword(vpd_data, vpd_len, | |
12223 | PCI_VPD_RO_KEYWORD_VENDOR0, | |
12224 | &kw_len); | |
12225 | if (rodi >= 0 && kw_len < sizeof(bp->fw_ver)) { | |
12226 | memcpy(bp->fw_ver, &vpd_data[rodi], kw_len); | |
12227 | bp->fw_ver[kw_len] = ' '; | |
34f24c7f | 12228 | } |
34f24c7f VZ |
12229 | } |
12230 | out_not_found: | |
df875894 | 12231 | kfree(vpd_data); |
34f24c7f VZ |
12232 | } |
12233 | ||
0329aba1 | 12234 | static void bnx2x_set_modes_bitmap(struct bnx2x *bp) |
619c5cb6 VZ |
12235 | { |
12236 | u32 flags = 0; | |
12237 | ||
12238 | if (CHIP_REV_IS_FPGA(bp)) | |
12239 | SET_FLAGS(flags, MODE_FPGA); | |
12240 | else if (CHIP_REV_IS_EMUL(bp)) | |
12241 | SET_FLAGS(flags, MODE_EMUL); | |
12242 | else | |
12243 | SET_FLAGS(flags, MODE_ASIC); | |
12244 | ||
12245 | if (CHIP_MODE_IS_4_PORT(bp)) | |
12246 | SET_FLAGS(flags, MODE_PORT4); | |
12247 | else | |
12248 | SET_FLAGS(flags, MODE_PORT2); | |
12249 | ||
12250 | if (CHIP_IS_E2(bp)) | |
12251 | SET_FLAGS(flags, MODE_E2); | |
12252 | else if (CHIP_IS_E3(bp)) { | |
12253 | SET_FLAGS(flags, MODE_E3); | |
12254 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
12255 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
12256 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
12257 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
12258 | } |
12259 | ||
12260 | if (IS_MF(bp)) { | |
12261 | SET_FLAGS(flags, MODE_MF); | |
12262 | switch (bp->mf_mode) { | |
12263 | case MULTI_FUNCTION_SD: | |
12264 | SET_FLAGS(flags, MODE_MF_SD); | |
12265 | break; | |
12266 | case MULTI_FUNCTION_SI: | |
12267 | SET_FLAGS(flags, MODE_MF_SI); | |
12268 | break; | |
a3348722 BW |
12269 | case MULTI_FUNCTION_AFEX: |
12270 | SET_FLAGS(flags, MODE_MF_AFEX); | |
12271 | break; | |
619c5cb6 VZ |
12272 | } |
12273 | } else | |
12274 | SET_FLAGS(flags, MODE_SF); | |
12275 | ||
12276 | #if defined(__LITTLE_ENDIAN) | |
12277 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
12278 | #else /*(__BIG_ENDIAN)*/ | |
12279 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
12280 | #endif | |
12281 | INIT_MODE_FLAGS(bp) = flags; | |
12282 | } | |
12283 | ||
0329aba1 | 12284 | static int bnx2x_init_bp(struct bnx2x *bp) |
34f80b04 | 12285 | { |
f2e0899f | 12286 | int func; |
34f80b04 EG |
12287 | int rc; |
12288 | ||
34f80b04 | 12289 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 12290 | mutex_init(&bp->fw_mb_mutex); |
42f8277f | 12291 | mutex_init(&bp->drv_info_mutex); |
c6e36d8c | 12292 | sema_init(&bp->stats_lock, 1); |
42f8277f | 12293 | bp->drv_info_mng_owner = false; |
05cc5a39 | 12294 | INIT_LIST_HEAD(&bp->vlan_reg); |
55c11941 | 12295 | |
1cf167f2 | 12296 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 12297 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 12298 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
370d4a26 | 12299 | INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task); |
1ab4434c AE |
12300 | if (IS_PF(bp)) { |
12301 | rc = bnx2x_get_hwinfo(bp); | |
12302 | if (rc) | |
12303 | return rc; | |
12304 | } else { | |
e09b74d0 | 12305 | eth_zero_addr(bp->dev->dev_addr); |
1ab4434c | 12306 | } |
34f80b04 | 12307 | |
619c5cb6 VZ |
12308 | bnx2x_set_modes_bitmap(bp); |
12309 | ||
12310 | rc = bnx2x_alloc_mem_bp(bp); | |
12311 | if (rc) | |
12312 | return rc; | |
523224a3 | 12313 | |
34f24c7f | 12314 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
12315 | |
12316 | func = BP_FUNC(bp); | |
12317 | ||
34f80b04 | 12318 | /* need to reset chip if undi was active */ |
1ab4434c | 12319 | if (IS_PF(bp) && !BP_NOMCP(bp)) { |
452427b0 YM |
12320 | /* init fw_seq */ |
12321 | bp->fw_seq = | |
12322 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
12323 | DRV_MSG_SEQ_NUMBER_MASK; | |
12324 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
12325 | ||
91ebb929 YM |
12326 | rc = bnx2x_prev_unload(bp); |
12327 | if (rc) { | |
12328 | bnx2x_free_mem_bp(bp); | |
12329 | return rc; | |
12330 | } | |
452427b0 YM |
12331 | } |
12332 | ||
34f80b04 | 12333 | if (CHIP_REV_IS_FPGA(bp)) |
cdaa7cb8 | 12334 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
12335 | |
12336 | if (BP_NOMCP(bp) && (func == 0)) | |
51c1a580 | 12337 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
34f80b04 | 12338 | |
614c76df | 12339 | bp->disable_tpa = disable_tpa; |
2e98ffc2 | 12340 | bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp); |
94d9de3c | 12341 | /* Reduce memory usage in kdump environment by disabling TPA */ |
c9931896 | 12342 | bp->disable_tpa |= is_kdump_kernel(); |
614c76df | 12343 | |
7a9b2557 | 12344 | /* Set TPA flags */ |
614c76df | 12345 | if (bp->disable_tpa) { |
3c3def5f MC |
12346 | bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); |
12347 | bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); | |
7a9b2557 VZ |
12348 | } |
12349 | ||
a18f5128 | 12350 | if (CHIP_IS_E1(bp)) |
f3a3f346 | 12351 | bp->dropless_fc = false; |
a18f5128 | 12352 | else |
7964211d | 12353 | bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); |
a18f5128 | 12354 | |
8d5726c4 | 12355 | bp->mrrs = mrrs; |
7a9b2557 | 12356 | |
2e98ffc2 | 12357 | bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL; |
1ab4434c AE |
12358 | if (IS_VF(bp)) |
12359 | bp->rx_ring_size = MAX_RX_AVAIL; | |
34f80b04 | 12360 | |
7d323bfd | 12361 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
12362 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
12363 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 12364 | |
fc543637 | 12365 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
34f80b04 | 12366 | |
e99e88a9 | 12367 | timer_setup(&bp->timer, bnx2x_timer, 0); |
34f80b04 | 12368 | bp->timer.expires = jiffies + bp->current_interval; |
34f80b04 | 12369 | |
0370cf90 BW |
12370 | if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && |
12371 | SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && | |
9c73267d | 12372 | SHMEM2_HAS(bp, dcbx_en) && |
0370cf90 | 12373 | SHMEM2_RD(bp, dcbx_lldp_params_offset) && |
9c73267d YM |
12374 | SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) && |
12375 | SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) { | |
0370cf90 BW |
12376 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); |
12377 | bnx2x_dcbx_init_params(bp); | |
12378 | } else { | |
12379 | bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); | |
12380 | } | |
e4901dde | 12381 | |
619c5cb6 VZ |
12382 | if (CHIP_IS_E1x(bp)) |
12383 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
12384 | else | |
12385 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
619c5cb6 | 12386 | |
6383c0b3 | 12387 | /* multiple tx priority */ |
1ab4434c AE |
12388 | if (IS_VF(bp)) |
12389 | bp->max_cos = 1; | |
12390 | else if (CHIP_IS_E1x(bp)) | |
6383c0b3 | 12391 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; |
1ab4434c | 12392 | else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) |
6383c0b3 | 12393 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; |
1ab4434c | 12394 | else if (CHIP_IS_E3B0(bp)) |
6383c0b3 | 12395 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; |
1ab4434c AE |
12396 | else |
12397 | BNX2X_ERR("unknown chip %x revision %x\n", | |
12398 | CHIP_NUM(bp), CHIP_REV(bp)); | |
12399 | BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); | |
6383c0b3 | 12400 | |
55c11941 MS |
12401 | /* We need at least one default status block for slow-path events, |
12402 | * second status block for the L2 queue, and a third status block for | |
16a5fd92 | 12403 | * CNIC if supported. |
55c11941 | 12404 | */ |
60cad4e6 AE |
12405 | if (IS_VF(bp)) |
12406 | bp->min_msix_vec_cnt = 1; | |
12407 | else if (CNIC_SUPPORT(bp)) | |
55c11941 | 12408 | bp->min_msix_vec_cnt = 3; |
60cad4e6 | 12409 | else /* PF w/o cnic */ |
55c11941 MS |
12410 | bp->min_msix_vec_cnt = 2; |
12411 | BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); | |
12412 | ||
5bb680d6 MS |
12413 | bp->dump_preset_idx = 1; |
12414 | ||
34f80b04 | 12415 | return rc; |
a2fbb9ea ET |
12416 | } |
12417 | ||
de0c62db DK |
12418 | /**************************************************************************** |
12419 | * General service functions | |
12420 | ****************************************************************************/ | |
a2fbb9ea | 12421 | |
619c5cb6 VZ |
12422 | /* |
12423 | * net_device service functions | |
12424 | */ | |
12425 | ||
bb2a0f7a | 12426 | /* called with rtnl_lock */ |
a2fbb9ea ET |
12427 | static int bnx2x_open(struct net_device *dev) |
12428 | { | |
12429 | struct bnx2x *bp = netdev_priv(dev); | |
8395be5e | 12430 | int rc; |
a2fbb9ea | 12431 | |
1355b704 MY |
12432 | bp->stats_init = true; |
12433 | ||
6eccabb3 EG |
12434 | netif_carrier_off(dev); |
12435 | ||
a2fbb9ea ET |
12436 | bnx2x_set_power_state(bp, PCI_D0); |
12437 | ||
ad5afc89 | 12438 | /* If parity had happen during the unload, then attentions |
c9ee9206 VZ |
12439 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we |
12440 | * want the first function loaded on the current engine to | |
12441 | * complete the recovery. | |
ad5afc89 | 12442 | * Parity recovery is only relevant for PF driver. |
c9ee9206 | 12443 | */ |
ad5afc89 | 12444 | if (IS_PF(bp)) { |
1a6974b2 YM |
12445 | int other_engine = BP_PATH(bp) ? 0 : 1; |
12446 | bool other_load_status, load_status; | |
12447 | bool global = false; | |
12448 | ||
ad5afc89 AE |
12449 | other_load_status = bnx2x_get_load_status(bp, other_engine); |
12450 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); | |
12451 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
12452 | bnx2x_chk_parity_attn(bp, &global, true)) { | |
12453 | do { | |
12454 | /* If there are attentions and they are in a | |
12455 | * global blocks, set the GLOBAL_RESET bit | |
12456 | * regardless whether it will be this function | |
12457 | * that will complete the recovery or not. | |
12458 | */ | |
12459 | if (global) | |
12460 | bnx2x_set_reset_global(bp); | |
72fd0718 | 12461 | |
ad5afc89 AE |
12462 | /* Only the first function on the current |
12463 | * engine should try to recover in open. In case | |
12464 | * of attentions in global blocks only the first | |
12465 | * in the chip should try to recover. | |
12466 | */ | |
12467 | if ((!load_status && | |
12468 | (!global || !other_load_status)) && | |
12469 | bnx2x_trylock_leader_lock(bp) && | |
12470 | !bnx2x_leader_reset(bp)) { | |
12471 | netdev_info(bp->dev, | |
12472 | "Recovered in open\n"); | |
12473 | break; | |
12474 | } | |
72fd0718 | 12475 | |
ad5afc89 AE |
12476 | /* recovery has failed... */ |
12477 | bnx2x_set_power_state(bp, PCI_D3hot); | |
12478 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
72fd0718 | 12479 | |
ad5afc89 AE |
12480 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
12481 | "If you still see this message after a few retries then power cycle is required.\n"); | |
72fd0718 | 12482 | |
ad5afc89 AE |
12483 | return -EAGAIN; |
12484 | } while (0); | |
12485 | } | |
12486 | } | |
72fd0718 VZ |
12487 | |
12488 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
8395be5e AE |
12489 | rc = bnx2x_nic_load(bp, LOAD_OPEN); |
12490 | if (rc) | |
12491 | return rc; | |
f34fa14c | 12492 | |
9a8130bc | 12493 | return 0; |
a2fbb9ea ET |
12494 | } |
12495 | ||
bb2a0f7a | 12496 | /* called with rtnl_lock */ |
56ad3152 | 12497 | static int bnx2x_close(struct net_device *dev) |
a2fbb9ea | 12498 | { |
a2fbb9ea ET |
12499 | struct bnx2x *bp = netdev_priv(dev); |
12500 | ||
12501 | /* Unload the driver, release IRQs */ | |
5d07d868 | 12502 | bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); |
c9ee9206 | 12503 | |
a2fbb9ea ET |
12504 | return 0; |
12505 | } | |
12506 | ||
e8c6ae9f | 12507 | struct bnx2x_mcast_list_elem_group |
6e30dd4e | 12508 | { |
e8c6ae9f JB |
12509 | struct list_head mcast_group_link; |
12510 | struct bnx2x_mcast_list_elem mcast_elems[]; | |
12511 | }; | |
6e30dd4e | 12512 | |
e8c6ae9f JB |
12513 | #define MCAST_ELEMS_PER_PG \ |
12514 | ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \ | |
12515 | sizeof(struct bnx2x_mcast_list_elem)) | |
12516 | ||
12517 | static void bnx2x_free_mcast_macs_list(struct list_head *mcast_group_list) | |
12518 | { | |
12519 | struct bnx2x_mcast_list_elem_group *current_mcast_group; | |
12520 | ||
12521 | while (!list_empty(mcast_group_list)) { | |
12522 | current_mcast_group = list_first_entry(mcast_group_list, | |
12523 | struct bnx2x_mcast_list_elem_group, | |
12524 | mcast_group_link); | |
12525 | list_del(¤t_mcast_group->mcast_group_link); | |
12526 | free_page((unsigned long)current_mcast_group); | |
c7b7b483 | 12527 | } |
e8c6ae9f | 12528 | } |
6e30dd4e | 12529 | |
e8c6ae9f JB |
12530 | static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
12531 | struct bnx2x_mcast_ramrod_params *p, | |
12532 | struct list_head *mcast_group_list) | |
12533 | { | |
12534 | struct bnx2x_mcast_list_elem *mc_mac; | |
12535 | struct netdev_hw_addr *ha; | |
12536 | struct bnx2x_mcast_list_elem_group *current_mcast_group = NULL; | |
12537 | int mc_count = netdev_mc_count(bp->dev); | |
12538 | int offset = 0; | |
6e30dd4e | 12539 | |
e8c6ae9f | 12540 | INIT_LIST_HEAD(&p->mcast_list); |
619c5cb6 | 12541 | netdev_for_each_mc_addr(ha, bp->dev) { |
e8c6ae9f JB |
12542 | if (!offset) { |
12543 | current_mcast_group = | |
12544 | (struct bnx2x_mcast_list_elem_group *) | |
12545 | __get_free_page(GFP_ATOMIC); | |
12546 | if (!current_mcast_group) { | |
12547 | bnx2x_free_mcast_macs_list(mcast_group_list); | |
12548 | BNX2X_ERR("Failed to allocate mc MAC list\n"); | |
12549 | return -ENOMEM; | |
12550 | } | |
12551 | list_add(¤t_mcast_group->mcast_group_link, | |
12552 | mcast_group_list); | |
12553 | } | |
12554 | mc_mac = ¤t_mcast_group->mcast_elems[offset]; | |
619c5cb6 VZ |
12555 | mc_mac->mac = bnx2x_mc_addr(ha); |
12556 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
e8c6ae9f JB |
12557 | offset++; |
12558 | if (offset == MCAST_ELEMS_PER_PG) | |
12559 | offset = 0; | |
6e30dd4e | 12560 | } |
619c5cb6 | 12561 | p->mcast_list_len = mc_count; |
619c5cb6 | 12562 | return 0; |
6e30dd4e VZ |
12563 | } |
12564 | ||
619c5cb6 VZ |
12565 | /** |
12566 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
12567 | * | |
12568 | * @bp: driver handle | |
6e30dd4e | 12569 | * |
619c5cb6 | 12570 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 12571 | */ |
1191cb83 | 12572 | static int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 12573 | { |
619c5cb6 | 12574 | int rc; |
6e30dd4e | 12575 | struct net_device *dev = bp->dev; |
6e30dd4e | 12576 | struct netdev_hw_addr *ha; |
15192a8c | 12577 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; |
619c5cb6 | 12578 | unsigned long ramrod_flags = 0; |
6e30dd4e | 12579 | |
619c5cb6 VZ |
12580 | /* First schedule a cleanup up of old configuration */ |
12581 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
12582 | if (rc < 0) { | |
12583 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
12584 | return rc; | |
12585 | } | |
6e30dd4e VZ |
12586 | |
12587 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
12588 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
12589 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
7b5342d9 YM |
12590 | if (rc == -EEXIST) { |
12591 | DP(BNX2X_MSG_SP, | |
12592 | "Failed to schedule ADD operations: %d\n", rc); | |
12593 | /* do not treat adding same MAC as error */ | |
12594 | rc = 0; | |
12595 | ||
12596 | } else if (rc < 0) { | |
12597 | ||
619c5cb6 VZ |
12598 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", |
12599 | rc); | |
12600 | return rc; | |
6e30dd4e VZ |
12601 | } |
12602 | } | |
12603 | ||
619c5cb6 VZ |
12604 | /* Execute the pending commands */ |
12605 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
12606 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
12607 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
12608 | } |
12609 | ||
c7b7b483 | 12610 | static int bnx2x_set_mc_list_e1x(struct bnx2x *bp) |
6e30dd4e | 12611 | { |
e8c6ae9f | 12612 | LIST_HEAD(mcast_group_list); |
619c5cb6 | 12613 | struct net_device *dev = bp->dev; |
3b603066 | 12614 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 | 12615 | int rc = 0; |
6e30dd4e | 12616 | |
619c5cb6 | 12617 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 12618 | |
619c5cb6 VZ |
12619 | /* first, clear all configured multicast MACs */ |
12620 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
12621 | if (rc < 0) { | |
51c1a580 | 12622 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
619c5cb6 VZ |
12623 | return rc; |
12624 | } | |
6e30dd4e | 12625 | |
619c5cb6 VZ |
12626 | /* then, configure a new MACs list */ |
12627 | if (netdev_mc_count(dev)) { | |
e8c6ae9f | 12628 | rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); |
c7b7b483 | 12629 | if (rc) |
619c5cb6 | 12630 | return rc; |
6e30dd4e | 12631 | |
619c5cb6 VZ |
12632 | /* Now add the new MACs */ |
12633 | rc = bnx2x_config_mcast(bp, &rparam, | |
12634 | BNX2X_MCAST_CMD_ADD); | |
12635 | if (rc < 0) | |
51c1a580 MS |
12636 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
12637 | rc); | |
6e30dd4e | 12638 | |
e8c6ae9f | 12639 | bnx2x_free_mcast_macs_list(&mcast_group_list); |
619c5cb6 | 12640 | } |
6e30dd4e | 12641 | |
619c5cb6 | 12642 | return rc; |
6e30dd4e VZ |
12643 | } |
12644 | ||
c7b7b483 YM |
12645 | static int bnx2x_set_mc_list(struct bnx2x *bp) |
12646 | { | |
e8c6ae9f | 12647 | LIST_HEAD(mcast_group_list); |
c7b7b483 YM |
12648 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
12649 | struct net_device *dev = bp->dev; | |
12650 | int rc = 0; | |
12651 | ||
12652 | /* On older adapters, we need to flush and re-add filters */ | |
12653 | if (CHIP_IS_E1x(bp)) | |
12654 | return bnx2x_set_mc_list_e1x(bp); | |
12655 | ||
12656 | rparam.mcast_obj = &bp->mcast_obj; | |
12657 | ||
12658 | if (netdev_mc_count(dev)) { | |
e8c6ae9f | 12659 | rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); |
c7b7b483 YM |
12660 | if (rc) |
12661 | return rc; | |
12662 | ||
12663 | /* Override the curently configured set of mc filters */ | |
12664 | rc = bnx2x_config_mcast(bp, &rparam, | |
12665 | BNX2X_MCAST_CMD_SET); | |
12666 | if (rc < 0) | |
12667 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", | |
12668 | rc); | |
12669 | ||
e8c6ae9f | 12670 | bnx2x_free_mcast_macs_list(&mcast_group_list); |
c7b7b483 YM |
12671 | } else { |
12672 | /* If no mc addresses are required, flush the configuration */ | |
12673 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
d0c32a16 | 12674 | if (rc < 0) |
c7b7b483 YM |
12675 | BNX2X_ERR("Failed to clear multicast configuration %d\n", |
12676 | rc); | |
12677 | } | |
12678 | ||
12679 | return rc; | |
12680 | } | |
12681 | ||
619c5cb6 | 12682 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
a8f47eb7 | 12683 | static void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
12684 | { |
12685 | struct bnx2x *bp = netdev_priv(dev); | |
34f80b04 EG |
12686 | |
12687 | if (bp->state != BNX2X_STATE_OPEN) { | |
12688 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
12689 | return; | |
8b09be5f YM |
12690 | } else { |
12691 | /* Schedule an SP task to handle rest of change */ | |
230bb0f3 YM |
12692 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE, |
12693 | NETIF_MSG_IFUP); | |
34f80b04 | 12694 | } |
8b09be5f YM |
12695 | } |
12696 | ||
12697 | void bnx2x_set_rx_mode_inner(struct bnx2x *bp) | |
12698 | { | |
12699 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 | 12700 | |
619c5cb6 | 12701 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 | 12702 | |
8b09be5f YM |
12703 | netif_addr_lock_bh(bp->dev); |
12704 | ||
12705 | if (bp->dev->flags & IFF_PROMISC) { | |
34f80b04 | 12706 | rx_mode = BNX2X_RX_MODE_PROMISC; |
8b09be5f YM |
12707 | } else if ((bp->dev->flags & IFF_ALLMULTI) || |
12708 | ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && | |
12709 | CHIP_IS_E1(bp))) { | |
34f80b04 | 12710 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
8b09be5f | 12711 | } else { |
381ac16b AE |
12712 | if (IS_PF(bp)) { |
12713 | /* some multicasts */ | |
12714 | if (bnx2x_set_mc_list(bp) < 0) | |
12715 | rx_mode = BNX2X_RX_MODE_ALLMULTI; | |
34f80b04 | 12716 | |
8b09be5f YM |
12717 | /* release bh lock, as bnx2x_set_uc_list might sleep */ |
12718 | netif_addr_unlock_bh(bp->dev); | |
381ac16b AE |
12719 | if (bnx2x_set_uc_list(bp) < 0) |
12720 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
8b09be5f | 12721 | netif_addr_lock_bh(bp->dev); |
381ac16b AE |
12722 | } else { |
12723 | /* configuring mcast to a vf involves sleeping (when we | |
8b09be5f | 12724 | * wait for the pf's response). |
381ac16b | 12725 | */ |
230bb0f3 YM |
12726 | bnx2x_schedule_sp_rtnl(bp, |
12727 | BNX2X_SP_RTNL_VFPF_MCAST, 0); | |
381ac16b | 12728 | } |
34f80b04 EG |
12729 | } |
12730 | ||
12731 | bp->rx_mode = rx_mode; | |
614c76df | 12732 | /* handle ISCSI SD mode */ |
2e98ffc2 | 12733 | if (IS_MF_ISCSI_ONLY(bp)) |
614c76df | 12734 | bp->rx_mode = BNX2X_RX_MODE_NONE; |
619c5cb6 VZ |
12735 | |
12736 | /* Schedule the rx_mode command */ | |
12737 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
12738 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
8b09be5f | 12739 | netif_addr_unlock_bh(bp->dev); |
619c5cb6 VZ |
12740 | return; |
12741 | } | |
12742 | ||
381ac16b AE |
12743 | if (IS_PF(bp)) { |
12744 | bnx2x_set_storm_rx_mode(bp); | |
8b09be5f | 12745 | netif_addr_unlock_bh(bp->dev); |
381ac16b | 12746 | } else { |
8b09be5f YM |
12747 | /* VF will need to request the PF to make this change, and so |
12748 | * the VF needs to release the bottom-half lock prior to the | |
12749 | * request (as it will likely require sleep on the VF side) | |
381ac16b | 12750 | */ |
8b09be5f YM |
12751 | netif_addr_unlock_bh(bp->dev); |
12752 | bnx2x_vfpf_storm_rx_mode(bp); | |
381ac16b | 12753 | } |
34f80b04 EG |
12754 | } |
12755 | ||
c18487ee | 12756 | /* called with rtnl_lock */ |
01cd4528 EG |
12757 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
12758 | int devad, u16 addr) | |
a2fbb9ea | 12759 | { |
01cd4528 EG |
12760 | struct bnx2x *bp = netdev_priv(netdev); |
12761 | u16 value; | |
12762 | int rc; | |
a2fbb9ea | 12763 | |
01cd4528 EG |
12764 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
12765 | prtad, devad, addr); | |
a2fbb9ea | 12766 | |
01cd4528 EG |
12767 | /* The HW expects different devad if CL22 is used */ |
12768 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 12769 | |
01cd4528 | 12770 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 12771 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
12772 | bnx2x_release_phy_lock(bp); |
12773 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 12774 | |
01cd4528 EG |
12775 | if (!rc) |
12776 | rc = value; | |
12777 | return rc; | |
12778 | } | |
a2fbb9ea | 12779 | |
01cd4528 EG |
12780 | /* called with rtnl_lock */ |
12781 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
12782 | u16 addr, u16 value) | |
12783 | { | |
12784 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
12785 | int rc; |
12786 | ||
51c1a580 MS |
12787 | DP(NETIF_MSG_LINK, |
12788 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", | |
12789 | prtad, devad, addr, value); | |
01cd4528 | 12790 | |
01cd4528 EG |
12791 | /* The HW expects different devad if CL22 is used */ |
12792 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 12793 | |
01cd4528 | 12794 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 12795 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
12796 | bnx2x_release_phy_lock(bp); |
12797 | return rc; | |
12798 | } | |
c18487ee | 12799 | |
01cd4528 EG |
12800 | /* called with rtnl_lock */ |
12801 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
12802 | { | |
12803 | struct bnx2x *bp = netdev_priv(dev); | |
12804 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 12805 | |
01cd4528 EG |
12806 | if (!netif_running(dev)) |
12807 | return -EAGAIN; | |
12808 | ||
eeed018c MK |
12809 | switch (cmd) { |
12810 | case SIOCSHWTSTAMP: | |
12811 | return bnx2x_hwtstamp_ioctl(bp, ifr); | |
12812 | default: | |
12813 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", | |
12814 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
12815 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
12816 | } | |
a2fbb9ea ET |
12817 | } |
12818 | ||
614c76df DK |
12819 | static int bnx2x_validate_addr(struct net_device *dev) |
12820 | { | |
12821 | struct bnx2x *bp = netdev_priv(dev); | |
12822 | ||
e09b74d0 AE |
12823 | /* query the bulletin board for mac address configured by the PF */ |
12824 | if (IS_VF(bp)) | |
12825 | bnx2x_sample_bulletin(bp); | |
12826 | ||
2e98ffc2 | 12827 | if (!is_valid_ether_addr(dev->dev_addr)) { |
51c1a580 | 12828 | BNX2X_ERR("Non-valid Ethernet address\n"); |
614c76df | 12829 | return -EADDRNOTAVAIL; |
51c1a580 | 12830 | } |
614c76df DK |
12831 | return 0; |
12832 | } | |
12833 | ||
3d7d562c | 12834 | static int bnx2x_get_phys_port_id(struct net_device *netdev, |
02637fce | 12835 | struct netdev_phys_item_id *ppid) |
3d7d562c YM |
12836 | { |
12837 | struct bnx2x *bp = netdev_priv(netdev); | |
12838 | ||
12839 | if (!(bp->flags & HAS_PHYS_PORT_ID)) | |
12840 | return -EOPNOTSUPP; | |
12841 | ||
12842 | ppid->id_len = sizeof(bp->phys_port_id); | |
12843 | memcpy(ppid->id, bp->phys_port_id, ppid->id_len); | |
12844 | ||
12845 | return 0; | |
12846 | } | |
12847 | ||
5f35227e JG |
12848 | static netdev_features_t bnx2x_features_check(struct sk_buff *skb, |
12849 | struct net_device *dev, | |
12850 | netdev_features_t features) | |
51de7bb9 | 12851 | { |
8914a595 DA |
12852 | /* |
12853 | * A skb with gso_size + header length > 9700 will cause a | |
12854 | * firmware panic. Drop GSO support. | |
12855 | * | |
12856 | * Eventually the upper layer should not pass these packets down. | |
12857 | * | |
12858 | * For speed, if the gso_size is <= 9000, assume there will | |
12859 | * not be 700 bytes of headers and pass it through. Only do a | |
12860 | * full (slow) validation if the gso_size is > 9000. | |
12861 | * | |
12862 | * (Due to the way SKB_BY_FRAGS works this will also do a full | |
12863 | * validation in that case.) | |
12864 | */ | |
12865 | if (unlikely(skb_is_gso(skb) && | |
12866 | (skb_shinfo(skb)->gso_size > 9000) && | |
12867 | !skb_gso_validate_mac_len(skb, 9700))) | |
12868 | features &= ~NETIF_F_GSO_MASK; | |
12869 | ||
8cb65d00 | 12870 | features = vlan_features_check(skb, features); |
5f35227e | 12871 | return vxlan_features_check(skb, features); |
51de7bb9 JS |
12872 | } |
12873 | ||
05cc5a39 YM |
12874 | static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add) |
12875 | { | |
12876 | int rc; | |
12877 | ||
12878 | if (IS_PF(bp)) { | |
12879 | unsigned long ramrod_flags = 0; | |
12880 | ||
12881 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
12882 | rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj, | |
12883 | add, &ramrod_flags); | |
12884 | } else { | |
12885 | rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add); | |
12886 | } | |
12887 | ||
12888 | return rc; | |
12889 | } | |
12890 | ||
a02cc9d3 | 12891 | static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp) |
05cc5a39 YM |
12892 | { |
12893 | struct bnx2x_vlan_entry *vlan; | |
12894 | int rc = 0; | |
12895 | ||
a02cc9d3 | 12896 | /* Configure all non-configured entries */ |
05cc5a39 | 12897 | list_for_each_entry(vlan, &bp->vlan_reg, link) { |
a02cc9d3 | 12898 | if (vlan->hw) |
05cc5a39 YM |
12899 | continue; |
12900 | ||
a02cc9d3 MS |
12901 | if (bp->vlan_cnt >= bp->vlan_credit) |
12902 | return -ENOBUFS; | |
05cc5a39 YM |
12903 | |
12904 | rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true); | |
12905 | if (rc) { | |
a02cc9d3 MS |
12906 | BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid); |
12907 | return rc; | |
05cc5a39 | 12908 | } |
a02cc9d3 MS |
12909 | |
12910 | DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid); | |
12911 | vlan->hw = true; | |
12912 | bp->vlan_cnt++; | |
05cc5a39 YM |
12913 | } |
12914 | ||
a02cc9d3 MS |
12915 | return 0; |
12916 | } | |
12917 | ||
12918 | static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode) | |
12919 | { | |
12920 | bool need_accept_any_vlan; | |
12921 | ||
12922 | need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp); | |
12923 | ||
12924 | if (bp->accept_any_vlan != need_accept_any_vlan) { | |
12925 | bp->accept_any_vlan = need_accept_any_vlan; | |
12926 | DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n", | |
12927 | bp->accept_any_vlan ? "raised" : "cleared"); | |
12928 | if (set_rx_mode) { | |
12929 | if (IS_PF(bp)) | |
12930 | bnx2x_set_rx_mode_inner(bp); | |
12931 | else | |
12932 | bnx2x_vfpf_storm_rx_mode(bp); | |
12933 | } | |
12934 | } | |
12935 | } | |
12936 | ||
12937 | int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp) | |
12938 | { | |
a02cc9d3 MS |
12939 | /* Don't set rx mode here. Our caller will do it. */ |
12940 | bnx2x_vlan_configure(bp, false); | |
12941 | ||
12942 | return 0; | |
05cc5a39 YM |
12943 | } |
12944 | ||
12945 | static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) | |
12946 | { | |
12947 | struct bnx2x *bp = netdev_priv(dev); | |
12948 | struct bnx2x_vlan_entry *vlan; | |
05cc5a39 YM |
12949 | |
12950 | DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid); | |
12951 | ||
12952 | vlan = kmalloc(sizeof(*vlan), GFP_KERNEL); | |
12953 | if (!vlan) | |
12954 | return -ENOMEM; | |
12955 | ||
05cc5a39 | 12956 | vlan->vid = vid; |
a02cc9d3 MS |
12957 | vlan->hw = false; |
12958 | list_add_tail(&vlan->link, &bp->vlan_reg); | |
05cc5a39 | 12959 | |
a02cc9d3 MS |
12960 | if (netif_running(dev)) |
12961 | bnx2x_vlan_configure(bp, true); | |
05cc5a39 | 12962 | |
a02cc9d3 | 12963 | return 0; |
05cc5a39 YM |
12964 | } |
12965 | ||
12966 | static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) | |
12967 | { | |
12968 | struct bnx2x *bp = netdev_priv(dev); | |
12969 | struct bnx2x_vlan_entry *vlan; | |
a02cc9d3 | 12970 | bool found = false; |
05cc5a39 YM |
12971 | int rc = 0; |
12972 | ||
05cc5a39 YM |
12973 | DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid); |
12974 | ||
05cc5a39 | 12975 | list_for_each_entry(vlan, &bp->vlan_reg, link) |
a02cc9d3 MS |
12976 | if (vlan->vid == vid) { |
12977 | found = true; | |
05cc5a39 | 12978 | break; |
a02cc9d3 | 12979 | } |
05cc5a39 | 12980 | |
a02cc9d3 | 12981 | if (!found) { |
05cc5a39 YM |
12982 | BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid); |
12983 | return -EINVAL; | |
12984 | } | |
12985 | ||
a02cc9d3 | 12986 | if (netif_running(dev) && vlan->hw) { |
05cc5a39 | 12987 | rc = __bnx2x_vlan_configure_vid(bp, vid, false); |
a02cc9d3 MS |
12988 | DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid); |
12989 | bp->vlan_cnt--; | |
12990 | } | |
05cc5a39 YM |
12991 | |
12992 | list_del(&vlan->link); | |
12993 | kfree(vlan); | |
12994 | ||
a02cc9d3 MS |
12995 | if (netif_running(dev)) |
12996 | bnx2x_vlan_configure(bp, true); | |
05cc5a39 YM |
12997 | |
12998 | DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc); | |
12999 | ||
13000 | return rc; | |
13001 | } | |
13002 | ||
c64213cd SH |
13003 | static const struct net_device_ops bnx2x_netdev_ops = { |
13004 | .ndo_open = bnx2x_open, | |
13005 | .ndo_stop = bnx2x_close, | |
13006 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 13007 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 13008 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd | 13009 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
614c76df | 13010 | .ndo_validate_addr = bnx2x_validate_addr, |
a7605370 | 13011 | .ndo_eth_ioctl = bnx2x_ioctl, |
c64213cd | 13012 | .ndo_change_mtu = bnx2x_change_mtu, |
66371c44 MM |
13013 | .ndo_fix_features = bnx2x_fix_features, |
13014 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 13015 | .ndo_tx_timeout = bnx2x_tx_timeout, |
05cc5a39 YM |
13016 | .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid, |
13017 | .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid, | |
e4c6734e | 13018 | .ndo_setup_tc = __bnx2x_setup_tc, |
6411280a | 13019 | #ifdef CONFIG_BNX2X_SRIOV |
abc5a021 | 13020 | .ndo_set_vf_mac = bnx2x_set_vf_mac, |
3cdeec22 | 13021 | .ndo_set_vf_vlan = bnx2x_set_vf_vlan, |
3ec9f9ca | 13022 | .ndo_get_vf_config = bnx2x_get_vf_config, |
75303965 | 13023 | .ndo_set_vf_spoofchk = bnx2x_set_vf_spoofchk, |
6411280a | 13024 | #endif |
55c11941 | 13025 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
13026 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, |
13027 | #endif | |
8f20aa57 | 13028 | |
3d7d562c | 13029 | .ndo_get_phys_port_id = bnx2x_get_phys_port_id, |
6495d15a | 13030 | .ndo_set_vf_link_state = bnx2x_set_vf_link_state, |
5f35227e | 13031 | .ndo_features_check = bnx2x_features_check, |
c64213cd SH |
13032 | }; |
13033 | ||
1191cb83 | 13034 | static int bnx2x_set_coherency_mask(struct bnx2x *bp) |
619c5cb6 VZ |
13035 | { |
13036 | struct device *dev = &bp->pdev->dev; | |
13037 | ||
8ceafbfa LT |
13038 | if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 && |
13039 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) { | |
619c5cb6 VZ |
13040 | dev_err(dev, "System does not support DMA, aborting\n"); |
13041 | return -EIO; | |
13042 | } | |
13043 | ||
13044 | return 0; | |
13045 | } | |
13046 | ||
33d8e6a5 YM |
13047 | static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp) |
13048 | { | |
13049 | if (bp->flags & AER_ENABLED) { | |
13050 | pci_disable_pcie_error_reporting(bp->pdev); | |
13051 | bp->flags &= ~AER_ENABLED; | |
13052 | } | |
13053 | } | |
13054 | ||
1ab4434c AE |
13055 | static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, |
13056 | struct net_device *dev, unsigned long board_type) | |
a2fbb9ea | 13057 | { |
a2fbb9ea | 13058 | int rc; |
c22610d0 | 13059 | u32 pci_cfg_dword; |
65087cfe AE |
13060 | bool chip_is_e1x = (board_type == BCM57710 || |
13061 | board_type == BCM57711 || | |
13062 | board_type == BCM57711E); | |
a2fbb9ea ET |
13063 | |
13064 | SET_NETDEV_DEV(dev, &pdev->dev); | |
a2fbb9ea | 13065 | |
34f80b04 EG |
13066 | bp->dev = dev; |
13067 | bp->pdev = pdev; | |
a2fbb9ea ET |
13068 | |
13069 | rc = pci_enable_device(pdev); | |
13070 | if (rc) { | |
cdaa7cb8 VZ |
13071 | dev_err(&bp->pdev->dev, |
13072 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
13073 | goto err_out; |
13074 | } | |
13075 | ||
13076 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
13077 | dev_err(&bp->pdev->dev, |
13078 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
13079 | rc = -ENODEV; |
13080 | goto err_out_disable; | |
13081 | } | |
13082 | ||
1ab4434c AE |
13083 | if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { |
13084 | dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); | |
a2fbb9ea ET |
13085 | rc = -ENODEV; |
13086 | goto err_out_disable; | |
13087 | } | |
13088 | ||
092a5fc9 YR |
13089 | pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); |
13090 | if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == | |
13091 | PCICFG_REVESION_ID_ERROR_VAL) { | |
13092 | pr_err("PCI device error, probably due to fan failure, aborting\n"); | |
13093 | rc = -ENODEV; | |
13094 | goto err_out_disable; | |
13095 | } | |
13096 | ||
34f80b04 EG |
13097 | if (atomic_read(&pdev->enable_cnt) == 1) { |
13098 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
13099 | if (rc) { | |
cdaa7cb8 VZ |
13100 | dev_err(&bp->pdev->dev, |
13101 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
13102 | goto err_out_disable; |
13103 | } | |
a2fbb9ea | 13104 | |
34f80b04 EG |
13105 | pci_set_master(pdev); |
13106 | pci_save_state(pdev); | |
13107 | } | |
a2fbb9ea | 13108 | |
1ab4434c | 13109 | if (IS_PF(bp)) { |
29ed74c3 | 13110 | if (!pdev->pm_cap) { |
1ab4434c AE |
13111 | dev_err(&bp->pdev->dev, |
13112 | "Cannot find power management capability, aborting\n"); | |
13113 | rc = -EIO; | |
13114 | goto err_out_release; | |
13115 | } | |
a2fbb9ea ET |
13116 | } |
13117 | ||
77c98e6a | 13118 | if (!pci_is_pcie(pdev)) { |
51c1a580 | 13119 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
a2fbb9ea ET |
13120 | rc = -EIO; |
13121 | goto err_out_release; | |
13122 | } | |
13123 | ||
619c5cb6 VZ |
13124 | rc = bnx2x_set_coherency_mask(bp); |
13125 | if (rc) | |
a2fbb9ea | 13126 | goto err_out_release; |
a2fbb9ea | 13127 | |
34f80b04 EG |
13128 | dev->mem_start = pci_resource_start(pdev, 0); |
13129 | dev->base_addr = dev->mem_start; | |
13130 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
13131 | |
13132 | dev->irq = pdev->irq; | |
13133 | ||
275f165f | 13134 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 13135 | if (!bp->regview) { |
cdaa7cb8 VZ |
13136 | dev_err(&bp->pdev->dev, |
13137 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
13138 | rc = -ENOMEM; |
13139 | goto err_out_release; | |
13140 | } | |
13141 | ||
c22610d0 AE |
13142 | /* In E1/E1H use pci device function given by kernel. |
13143 | * In E2/E3 read physical function from ME register since these chips | |
13144 | * support Physical Device Assignment where kernel BDF maybe arbitrary | |
13145 | * (depending on hypervisor). | |
13146 | */ | |
2de67439 | 13147 | if (chip_is_e1x) { |
c22610d0 | 13148 | bp->pf_num = PCI_FUNC(pdev->devfn); |
2de67439 YM |
13149 | } else { |
13150 | /* chip is E2/3*/ | |
c22610d0 AE |
13151 | pci_read_config_dword(bp->pdev, |
13152 | PCICFG_ME_REGISTER, &pci_cfg_dword); | |
13153 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> | |
2de67439 | 13154 | ME_REG_ABS_PF_NUM_SHIFT); |
c22610d0 | 13155 | } |
51c1a580 | 13156 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
c22610d0 | 13157 | |
34f80b04 EG |
13158 | /* clean indirect addresses */ |
13159 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
13160 | PCICFG_VENDOR_ID_OFFSET); | |
33d8e6a5 | 13161 | |
da293700 BK |
13162 | /* Set PCIe reset type to fundamental for EEH recovery */ |
13163 | pdev->needs_freset = 1; | |
13164 | ||
33d8e6a5 YM |
13165 | /* AER (Advanced Error reporting) configuration */ |
13166 | rc = pci_enable_pcie_error_reporting(pdev); | |
13167 | if (!rc) | |
13168 | bp->flags |= AER_ENABLED; | |
13169 | else | |
13170 | BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc); | |
13171 | ||
a5c53dbc DK |
13172 | /* |
13173 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
13174 | * is not used by the driver. |
13175 | */ | |
1ab4434c AE |
13176 | if (IS_PF(bp)) { |
13177 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
13178 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
13179 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
13180 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
13181 | ||
13182 | if (chip_is_e1x) { | |
13183 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); | |
13184 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
13185 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
13186 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
13187 | } | |
a5c53dbc | 13188 | |
1ab4434c AE |
13189 | /* Enable internal target-read (in case we are probed after PF |
13190 | * FLR). Must be done prior to any BAR read access. Only for | |
13191 | * 57712 and up | |
13192 | */ | |
13193 | if (!chip_is_e1x) | |
13194 | REG_WR(bp, | |
13195 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
a5c53dbc | 13196 | } |
a2fbb9ea | 13197 | |
34f80b04 | 13198 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 13199 | |
c64213cd | 13200 | dev->netdev_ops = &bnx2x_netdev_ops; |
005a07ba | 13201 | bnx2x_set_ethtool_ops(bp, dev); |
5316bc0b | 13202 | |
01789349 JP |
13203 | dev->priv_flags |= IFF_UNICAST_FLT; |
13204 | ||
66371c44 | 13205 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
621b4d66 | 13206 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
3c3def5f | 13207 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | NETIF_F_GRO_HW | |
f646968f | 13208 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX; |
a8e0c246 | 13209 | if (!chip_is_e1x) { |
736c4c1d AD |
13210 | dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | |
13211 | NETIF_F_GSO_IPXIP4 | | |
13212 | NETIF_F_GSO_UDP_TUNNEL | | |
13213 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
13214 | NETIF_F_GSO_PARTIAL; | |
13215 | ||
a848ade4 DK |
13216 | dev->hw_enc_features = |
13217 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | | |
13218 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | | |
7e13318d | 13219 | NETIF_F_GSO_IPXIP4 | |
736c4c1d AD |
13220 | NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | |
13221 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
13222 | NETIF_F_GSO_PARTIAL; | |
13223 | ||
13224 | dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM | | |
13225 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
085c5c42 JK |
13226 | |
13227 | if (IS_PF(bp)) | |
13228 | dev->udp_tunnel_nic_info = &bnx2x_udp_tunnels; | |
a848ade4 | 13229 | } |
66371c44 MM |
13230 | |
13231 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
13232 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
13233 | ||
05cc5a39 | 13234 | if (IS_PF(bp)) { |
ab6d7846 | 13235 | if (chip_is_e1x) |
05cc5a39 YM |
13236 | bp->accept_any_vlan = true; |
13237 | else | |
13238 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
05cc5a39 | 13239 | } |
83bd9eb8 MS |
13240 | /* For VF we'll know whether to enable VLAN filtering after |
13241 | * getting a response to CHANNEL_TLV_ACQUIRE from PF. | |
13242 | */ | |
05cc5a39 | 13243 | |
f646968f | 13244 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; |
edd31476 | 13245 | dev->features |= NETIF_F_HIGHDMA; |
3c3def5f MC |
13246 | if (dev->features & NETIF_F_LRO) |
13247 | dev->features &= ~NETIF_F_GRO_HW; | |
a2fbb9ea | 13248 | |
538dd2e3 MB |
13249 | /* Add Loopback capability to the device */ |
13250 | dev->hw_features |= NETIF_F_LOOPBACK; | |
13251 | ||
98507672 | 13252 | #ifdef BCM_DCBNL |
785b9b1a SR |
13253 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
13254 | #endif | |
13255 | ||
e1c6dcca JW |
13256 | /* MTU range, 46 - 9600 */ |
13257 | dev->min_mtu = ETH_MIN_PACKET_SIZE; | |
13258 | dev->max_mtu = ETH_MAX_JUMBO_PACKET_SIZE; | |
13259 | ||
01cd4528 EG |
13260 | /* get_port_hwinfo() will set prtad and mmds properly */ |
13261 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
13262 | bp->mdio.mmds = 0; | |
13263 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
13264 | bp->mdio.dev = dev; | |
13265 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
13266 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
13267 | ||
a2fbb9ea ET |
13268 | return 0; |
13269 | ||
a2fbb9ea | 13270 | err_out_release: |
34f80b04 EG |
13271 | if (atomic_read(&pdev->enable_cnt) == 1) |
13272 | pci_release_regions(pdev); | |
a2fbb9ea ET |
13273 | |
13274 | err_out_disable: | |
13275 | pci_disable_device(pdev); | |
a2fbb9ea ET |
13276 | |
13277 | err_out: | |
13278 | return rc; | |
13279 | } | |
13280 | ||
6891dd25 | 13281 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 13282 | { |
37f9ce62 | 13283 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
13284 | struct bnx2x_fw_file_hdr *fw_hdr; |
13285 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 13286 | u32 offset, len, num_ops; |
86564c3f | 13287 | __be16 *ops_offsets; |
94a78b79 | 13288 | int i; |
37f9ce62 | 13289 | const u8 *fw_ver; |
94a78b79 | 13290 | |
51c1a580 MS |
13291 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
13292 | BNX2X_ERR("Wrong FW size\n"); | |
94a78b79 | 13293 | return -EINVAL; |
51c1a580 | 13294 | } |
94a78b79 VZ |
13295 | |
13296 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
13297 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
13298 | ||
13299 | /* Make sure none of the offsets and sizes make us read beyond | |
13300 | * the end of the firmware data */ | |
13301 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
13302 | offset = be32_to_cpu(sections[i].offset); | |
13303 | len = be32_to_cpu(sections[i].len); | |
13304 | if (offset + len > firmware->size) { | |
51c1a580 | 13305 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
94a78b79 VZ |
13306 | return -EINVAL; |
13307 | } | |
13308 | } | |
13309 | ||
13310 | /* Likewise for the init_ops offsets */ | |
13311 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
86564c3f | 13312 | ops_offsets = (__force __be16 *)(firmware->data + offset); |
94a78b79 VZ |
13313 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); |
13314 | ||
13315 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
13316 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
51c1a580 | 13317 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
94a78b79 VZ |
13318 | return -EINVAL; |
13319 | } | |
13320 | } | |
13321 | ||
13322 | /* Check FW version */ | |
13323 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
13324 | fw_ver = firmware->data + offset; | |
18bf8ca6 MC |
13325 | if (fw_ver[0] != bp->fw_major || fw_ver[1] != bp->fw_minor || |
13326 | fw_ver[2] != bp->fw_rev || fw_ver[3] != bp->fw_eng) { | |
51c1a580 | 13327 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
18bf8ca6 MC |
13328 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], |
13329 | bp->fw_major, bp->fw_minor, bp->fw_rev, bp->fw_eng); | |
ab6ad5a4 | 13330 | return -EINVAL; |
94a78b79 VZ |
13331 | } |
13332 | ||
13333 | return 0; | |
13334 | } | |
13335 | ||
1191cb83 | 13336 | static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 13337 | { |
ab6ad5a4 EG |
13338 | const __be32 *source = (const __be32 *)_source; |
13339 | u32 *target = (u32 *)_target; | |
94a78b79 | 13340 | u32 i; |
94a78b79 VZ |
13341 | |
13342 | for (i = 0; i < n/4; i++) | |
13343 | target[i] = be32_to_cpu(source[i]); | |
13344 | } | |
13345 | ||
13346 | /* | |
13347 | Ops array is stored in the following format: | |
13348 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
13349 | */ | |
1191cb83 | 13350 | static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 13351 | { |
ab6ad5a4 EG |
13352 | const __be32 *source = (const __be32 *)_source; |
13353 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 13354 | u32 i, j, tmp; |
94a78b79 | 13355 | |
ab6ad5a4 | 13356 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
13357 | tmp = be32_to_cpu(source[j]); |
13358 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
13359 | target[i].offset = tmp & 0xffffff; |
13360 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
13361 | } |
13362 | } | |
ab6ad5a4 | 13363 | |
1aa8b471 | 13364 | /* IRO array is stored in the following format: |
523224a3 DK |
13365 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } |
13366 | */ | |
1191cb83 | 13367 | static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) |
523224a3 DK |
13368 | { |
13369 | const __be32 *source = (const __be32 *)_source; | |
13370 | struct iro *target = (struct iro *)_target; | |
13371 | u32 i, j, tmp; | |
13372 | ||
13373 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
13374 | target[i].base = be32_to_cpu(source[j]); | |
13375 | j++; | |
13376 | tmp = be32_to_cpu(source[j]); | |
13377 | target[i].m1 = (tmp >> 16) & 0xffff; | |
13378 | target[i].m2 = tmp & 0xffff; | |
13379 | j++; | |
13380 | tmp = be32_to_cpu(source[j]); | |
13381 | target[i].m3 = (tmp >> 16) & 0xffff; | |
13382 | target[i].size = tmp & 0xffff; | |
13383 | j++; | |
13384 | } | |
13385 | } | |
13386 | ||
1191cb83 | 13387 | static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 13388 | { |
ab6ad5a4 EG |
13389 | const __be16 *source = (const __be16 *)_source; |
13390 | u16 *target = (u16 *)_target; | |
94a78b79 | 13391 | u32 i; |
94a78b79 VZ |
13392 | |
13393 | for (i = 0; i < n/2; i++) | |
13394 | target[i] = be16_to_cpu(source[i]); | |
13395 | } | |
13396 | ||
7995c64e JP |
13397 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
13398 | do { \ | |
13399 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
13400 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
e404decb | 13401 | if (!bp->arr) \ |
7995c64e | 13402 | goto lbl; \ |
7995c64e JP |
13403 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
13404 | (u8 *)bp->arr, len); \ | |
13405 | } while (0) | |
94a78b79 | 13406 | |
82dcb061 | 13407 | static int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 13408 | { |
18bf8ca6 | 13409 | const char *fw_file_name, *fw_file_name_v15; |
94a78b79 | 13410 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 13411 | int rc; |
94a78b79 | 13412 | |
c0ea452e MS |
13413 | if (bp->firmware) |
13414 | return 0; | |
94a78b79 | 13415 | |
18bf8ca6 | 13416 | if (CHIP_IS_E1(bp)) { |
c0ea452e | 13417 | fw_file_name = FW_FILE_NAME_E1; |
18bf8ca6 MC |
13418 | fw_file_name_v15 = FW_FILE_NAME_E1_V15; |
13419 | } else if (CHIP_IS_E1H(bp)) { | |
c0ea452e | 13420 | fw_file_name = FW_FILE_NAME_E1H; |
18bf8ca6 MC |
13421 | fw_file_name_v15 = FW_FILE_NAME_E1H_V15; |
13422 | } else if (!CHIP_IS_E1x(bp)) { | |
c0ea452e | 13423 | fw_file_name = FW_FILE_NAME_E2; |
18bf8ca6 MC |
13424 | fw_file_name_v15 = FW_FILE_NAME_E2_V15; |
13425 | } else { | |
c0ea452e MS |
13426 | BNX2X_ERR("Unsupported chip revision\n"); |
13427 | return -EINVAL; | |
13428 | } | |
18bf8ca6 | 13429 | |
c0ea452e | 13430 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); |
94a78b79 | 13431 | |
c0ea452e MS |
13432 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
13433 | if (rc) { | |
18bf8ca6 MC |
13434 | BNX2X_DEV_INFO("Trying to load older fw %s\n", fw_file_name_v15); |
13435 | ||
13436 | /* try to load prev version */ | |
13437 | rc = request_firmware(&bp->firmware, fw_file_name_v15, &bp->pdev->dev); | |
13438 | ||
13439 | if (rc) | |
13440 | goto request_firmware_exit; | |
13441 | ||
13442 | bp->fw_rev = BCM_5710_FW_REVISION_VERSION_V15; | |
13443 | } else { | |
13444 | bp->fw_cap |= FW_CAP_INVALIDATE_VF_FP_HSI; | |
13445 | bp->fw_rev = BCM_5710_FW_REVISION_VERSION; | |
c0ea452e | 13446 | } |
eb2afd4a | 13447 | |
18bf8ca6 MC |
13448 | bp->fw_major = BCM_5710_FW_MAJOR_VERSION; |
13449 | bp->fw_minor = BCM_5710_FW_MINOR_VERSION; | |
13450 | bp->fw_eng = BCM_5710_FW_ENGINEERING_VERSION; | |
13451 | ||
c0ea452e MS |
13452 | rc = bnx2x_check_firmware(bp); |
13453 | if (rc) { | |
13454 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); | |
13455 | goto request_firmware_exit; | |
94a78b79 VZ |
13456 | } |
13457 | ||
13458 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
13459 | ||
13460 | /* Initialize the pointers to the init arrays */ | |
13461 | /* Blob */ | |
005f7e68 | 13462 | rc = -ENOMEM; |
94a78b79 VZ |
13463 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); |
13464 | ||
13465 | /* Opcodes */ | |
13466 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
13467 | ||
13468 | /* Offsets */ | |
ab6ad5a4 EG |
13469 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
13470 | be16_to_cpu_n); | |
94a78b79 VZ |
13471 | |
13472 | /* STORMs firmware */ | |
573f2035 EG |
13473 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
13474 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
13475 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
13476 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
13477 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
13478 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
13479 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
13480 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
13481 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
13482 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
13483 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
13484 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
13485 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
13486 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
13487 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
13488 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
13489 | /* IRO */ |
13490 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
13491 | |
13492 | return 0; | |
ab6ad5a4 | 13493 | |
523224a3 DK |
13494 | iro_alloc_err: |
13495 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
13496 | init_offsets_alloc_err: |
13497 | kfree(bp->init_ops); | |
13498 | init_ops_alloc_err: | |
13499 | kfree(bp->init_data); | |
13500 | request_firmware_exit: | |
13501 | release_firmware(bp->firmware); | |
127d0a19 | 13502 | bp->firmware = NULL; |
94a78b79 VZ |
13503 | |
13504 | return rc; | |
13505 | } | |
13506 | ||
82dcb061 | 13507 | static void bnx2x_release_firmware(struct bnx2x *bp) |
619c5cb6 VZ |
13508 | { |
13509 | kfree(bp->init_ops_offsets); | |
13510 | kfree(bp->init_ops); | |
13511 | kfree(bp->init_data); | |
13512 | release_firmware(bp->firmware); | |
eb2afd4a | 13513 | bp->firmware = NULL; |
619c5cb6 VZ |
13514 | } |
13515 | ||
619c5cb6 VZ |
13516 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { |
13517 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
13518 | .init_hw_cmn = bnx2x_init_hw_common, | |
13519 | .init_hw_port = bnx2x_init_hw_port, | |
13520 | .init_hw_func = bnx2x_init_hw_func, | |
13521 | ||
13522 | .reset_hw_cmn = bnx2x_reset_common, | |
13523 | .reset_hw_port = bnx2x_reset_port, | |
13524 | .reset_hw_func = bnx2x_reset_func, | |
13525 | ||
13526 | .gunzip_init = bnx2x_gunzip_init, | |
13527 | .gunzip_end = bnx2x_gunzip_end, | |
13528 | ||
13529 | .init_fw = bnx2x_init_firmware, | |
13530 | .release_fw = bnx2x_release_firmware, | |
13531 | }; | |
13532 | ||
13533 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
13534 | { | |
13535 | /* Prepare DMAE related driver resources */ | |
13536 | bnx2x_setup_dmae(bp); | |
13537 | ||
13538 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
13539 | bnx2x_sp(bp, func_rdata), | |
13540 | bnx2x_sp_mapping(bp, func_rdata), | |
a3348722 BW |
13541 | bnx2x_sp(bp, func_afex_rdata), |
13542 | bnx2x_sp_mapping(bp, func_afex_rdata), | |
619c5cb6 VZ |
13543 | &bnx2x_func_sp_drv); |
13544 | } | |
13545 | ||
13546 | /* must be called after sriov-enable */ | |
1191cb83 | 13547 | static int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 13548 | { |
37ae41a9 | 13549 | int cid_count = BNX2X_L2_MAX_CID(bp); |
94a78b79 | 13550 | |
290ca2bb AE |
13551 | if (IS_SRIOV(bp)) |
13552 | cid_count += BNX2X_VF_CIDS; | |
13553 | ||
55c11941 MS |
13554 | if (CNIC_SUPPORT(bp)) |
13555 | cid_count += CNIC_CID_MAX; | |
290ca2bb | 13556 | |
523224a3 DK |
13557 | return roundup(cid_count, QM_CID_ROUND); |
13558 | } | |
f85582f8 | 13559 | |
619c5cb6 | 13560 | /** |
76d85049 | 13561 | * bnx2x_get_num_non_def_sbs - return the number of none default SBs |
d0ea5cbd JB |
13562 | * @pdev: pci device |
13563 | * @cnic_cnt: count | |
619c5cb6 VZ |
13564 | * |
13565 | */ | |
60cad4e6 | 13566 | static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt) |
619c5cb6 | 13567 | { |
ae2104be | 13568 | int index; |
1ab4434c | 13569 | u16 control = 0; |
619c5cb6 | 13570 | |
6383c0b3 AE |
13571 | /* |
13572 | * If MSI-X is not supported - return number of SBs needed to support | |
13573 | * one fast path queue: one FP queue + SB for CNIC | |
13574 | */ | |
ae2104be | 13575 | if (!pdev->msix_cap) { |
1ab4434c | 13576 | dev_info(&pdev->dev, "no msix capability found\n"); |
55c11941 | 13577 | return 1 + cnic_cnt; |
1ab4434c AE |
13578 | } |
13579 | dev_info(&pdev->dev, "msix capability found\n"); | |
619c5cb6 | 13580 | |
6383c0b3 AE |
13581 | /* |
13582 | * The value in the PCI configuration space is the index of the last | |
13583 | * entry, namely one less than the actual size of the table, which is | |
13584 | * exactly what we want to return from this function: number of all SBs | |
13585 | * without the default SB. | |
1ab4434c | 13586 | * For VFs there is no default SB, then we return (index+1). |
6383c0b3 | 13587 | */ |
73413ffa | 13588 | pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control); |
619c5cb6 | 13589 | |
1ab4434c | 13590 | index = control & PCI_MSIX_FLAGS_QSIZE; |
4bd9b0ff | 13591 | |
60cad4e6 | 13592 | return index; |
1ab4434c | 13593 | } |
523224a3 | 13594 | |
1ab4434c AE |
13595 | static int set_max_cos_est(int chip_id) |
13596 | { | |
13597 | switch (chip_id) { | |
f2e0899f DK |
13598 | case BCM57710: |
13599 | case BCM57711: | |
13600 | case BCM57711E: | |
1ab4434c | 13601 | return BNX2X_MULTI_TX_COS_E1X; |
f2e0899f | 13602 | case BCM57712: |
619c5cb6 | 13603 | case BCM57712_MF: |
1ab4434c | 13604 | return BNX2X_MULTI_TX_COS_E2_E3A0; |
619c5cb6 VZ |
13605 | case BCM57800: |
13606 | case BCM57800_MF: | |
13607 | case BCM57810: | |
13608 | case BCM57810_MF: | |
c3def943 YM |
13609 | case BCM57840_4_10: |
13610 | case BCM57840_2_20: | |
1ab4434c | 13611 | case BCM57840_O: |
c3def943 | 13612 | case BCM57840_MFO: |
619c5cb6 | 13613 | case BCM57840_MF: |
7e8e02df BW |
13614 | case BCM57811: |
13615 | case BCM57811_MF: | |
1ab4434c | 13616 | return BNX2X_MULTI_TX_COS_E3B0; |
b1239723 YM |
13617 | case BCM57712_VF: |
13618 | case BCM57800_VF: | |
13619 | case BCM57810_VF: | |
13620 | case BCM57840_VF: | |
13621 | case BCM57811_VF: | |
1ab4434c | 13622 | return 1; |
f2e0899f | 13623 | default: |
1ab4434c | 13624 | pr_err("Unknown board_type (%d), aborting\n", chip_id); |
870634b0 | 13625 | return -ENODEV; |
f2e0899f | 13626 | } |
1ab4434c | 13627 | } |
f2e0899f | 13628 | |
1ab4434c AE |
13629 | static int set_is_vf(int chip_id) |
13630 | { | |
13631 | switch (chip_id) { | |
13632 | case BCM57712_VF: | |
13633 | case BCM57800_VF: | |
13634 | case BCM57810_VF: | |
13635 | case BCM57840_VF: | |
13636 | case BCM57811_VF: | |
13637 | return true; | |
13638 | default: | |
13639 | return false; | |
13640 | } | |
13641 | } | |
6383c0b3 | 13642 | |
eeed018c MK |
13643 | /* nig_tsgen registers relative address */ |
13644 | #define tsgen_ctrl 0x0 | |
13645 | #define tsgen_freecount 0x10 | |
13646 | #define tsgen_synctime_t0 0x20 | |
13647 | #define tsgen_offset_t0 0x28 | |
13648 | #define tsgen_drift_t0 0x30 | |
13649 | #define tsgen_synctime_t1 0x58 | |
13650 | #define tsgen_offset_t1 0x60 | |
13651 | #define tsgen_drift_t1 0x68 | |
13652 | ||
13653 | /* FW workaround for setting drift */ | |
13654 | static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir, | |
13655 | int best_val, int best_period) | |
13656 | { | |
13657 | struct bnx2x_func_state_params func_params = {NULL}; | |
13658 | struct bnx2x_func_set_timesync_params *set_timesync_params = | |
13659 | &func_params.params.set_timesync; | |
13660 | ||
13661 | /* Prepare parameters for function state transitions */ | |
13662 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
13663 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
13664 | ||
13665 | func_params.f_obj = &bp->func_obj; | |
13666 | func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; | |
13667 | ||
13668 | /* Function parameters */ | |
13669 | set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET; | |
13670 | set_timesync_params->offset_cmd = TS_OFFSET_KEEP; | |
13671 | set_timesync_params->add_sub_drift_adjust_value = | |
13672 | drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE; | |
13673 | set_timesync_params->drift_adjust_value = best_val; | |
13674 | set_timesync_params->drift_adjust_period = best_period; | |
13675 | ||
13676 | return bnx2x_func_state_change(bp, &func_params); | |
13677 | } | |
13678 | ||
13679 | static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) | |
13680 | { | |
13681 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13682 | int rc; | |
13683 | int drift_dir = 1; | |
13684 | int val, period, period1, period2, dif, dif1, dif2; | |
13685 | int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0; | |
13686 | ||
13687 | DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb); | |
13688 | ||
13689 | if (!netif_running(bp->dev)) { | |
13690 | DP(BNX2X_MSG_PTP, | |
13691 | "PTP adjfreq called while the interface is down\n"); | |
466e8bf1 | 13692 | return -ENETDOWN; |
eeed018c MK |
13693 | } |
13694 | ||
13695 | if (ppb < 0) { | |
13696 | ppb = -ppb; | |
13697 | drift_dir = 0; | |
13698 | } | |
13699 | ||
13700 | if (ppb == 0) { | |
13701 | best_val = 1; | |
13702 | best_period = 0x1FFFFFF; | |
13703 | } else if (ppb >= BNX2X_MAX_PHC_DRIFT) { | |
13704 | best_val = 31; | |
13705 | best_period = 1; | |
13706 | } else { | |
13707 | /* Changed not to allow val = 8, 16, 24 as these values | |
13708 | * are not supported in workaround. | |
13709 | */ | |
13710 | for (val = 0; val <= 31; val++) { | |
13711 | if ((val & 0x7) == 0) | |
13712 | continue; | |
13713 | period1 = val * 1000000 / ppb; | |
13714 | period2 = period1 + 1; | |
13715 | if (period1 != 0) | |
13716 | dif1 = ppb - (val * 1000000 / period1); | |
13717 | else | |
13718 | dif1 = BNX2X_MAX_PHC_DRIFT; | |
13719 | if (dif1 < 0) | |
13720 | dif1 = -dif1; | |
13721 | dif2 = ppb - (val * 1000000 / period2); | |
13722 | if (dif2 < 0) | |
13723 | dif2 = -dif2; | |
13724 | dif = (dif1 < dif2) ? dif1 : dif2; | |
13725 | period = (dif1 < dif2) ? period1 : period2; | |
13726 | if (dif < best_dif) { | |
13727 | best_dif = dif; | |
13728 | best_val = val; | |
13729 | best_period = period; | |
13730 | } | |
13731 | } | |
13732 | } | |
13733 | ||
13734 | rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val, | |
13735 | best_period); | |
13736 | if (rc) { | |
13737 | BNX2X_ERR("Failed to set drift\n"); | |
13738 | return -EFAULT; | |
13739 | } | |
13740 | ||
bf27c353 | 13741 | DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val, |
eeed018c MK |
13742 | best_period); |
13743 | ||
13744 | return 0; | |
13745 | } | |
13746 | ||
13747 | static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) | |
13748 | { | |
13749 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
eeed018c | 13750 | |
466e8bf1 MS |
13751 | if (!netif_running(bp->dev)) { |
13752 | DP(BNX2X_MSG_PTP, | |
13753 | "PTP adjtime called while the interface is down\n"); | |
13754 | return -ENETDOWN; | |
13755 | } | |
13756 | ||
eeed018c MK |
13757 | DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta); |
13758 | ||
2e5601f9 | 13759 | timecounter_adjtime(&bp->timecounter, delta); |
eeed018c MK |
13760 | |
13761 | return 0; | |
13762 | } | |
13763 | ||
5d45186b | 13764 | static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) |
eeed018c MK |
13765 | { |
13766 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13767 | u64 ns; | |
eeed018c | 13768 | |
466e8bf1 MS |
13769 | if (!netif_running(bp->dev)) { |
13770 | DP(BNX2X_MSG_PTP, | |
13771 | "PTP gettime called while the interface is down\n"); | |
13772 | return -ENETDOWN; | |
13773 | } | |
13774 | ||
eeed018c MK |
13775 | ns = timecounter_read(&bp->timecounter); |
13776 | ||
13777 | DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns); | |
13778 | ||
f7dcdefe | 13779 | *ts = ns_to_timespec64(ns); |
eeed018c MK |
13780 | |
13781 | return 0; | |
13782 | } | |
13783 | ||
13784 | static int bnx2x_ptp_settime(struct ptp_clock_info *ptp, | |
5d45186b | 13785 | const struct timespec64 *ts) |
eeed018c MK |
13786 | { |
13787 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13788 | u64 ns; | |
13789 | ||
466e8bf1 MS |
13790 | if (!netif_running(bp->dev)) { |
13791 | DP(BNX2X_MSG_PTP, | |
13792 | "PTP settime called while the interface is down\n"); | |
13793 | return -ENETDOWN; | |
13794 | } | |
13795 | ||
f7dcdefe | 13796 | ns = timespec64_to_ns(ts); |
eeed018c MK |
13797 | |
13798 | DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns); | |
13799 | ||
13800 | /* Re-init the timecounter */ | |
13801 | timecounter_init(&bp->timecounter, &bp->cyclecounter, ns); | |
13802 | ||
13803 | return 0; | |
13804 | } | |
13805 | ||
13806 | /* Enable (or disable) ancillary features of the phc subsystem */ | |
13807 | static int bnx2x_ptp_enable(struct ptp_clock_info *ptp, | |
13808 | struct ptp_clock_request *rq, int on) | |
13809 | { | |
13810 | struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); | |
13811 | ||
13812 | BNX2X_ERR("PHC ancillary features are not supported\n"); | |
13813 | return -ENOTSUPP; | |
13814 | } | |
13815 | ||
07f12622 | 13816 | void bnx2x_register_phc(struct bnx2x *bp) |
eeed018c MK |
13817 | { |
13818 | /* Fill the ptp_clock_info struct and register PTP clock*/ | |
13819 | bp->ptp_clock_info.owner = THIS_MODULE; | |
13820 | snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name); | |
13821 | bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */ | |
13822 | bp->ptp_clock_info.n_alarm = 0; | |
13823 | bp->ptp_clock_info.n_ext_ts = 0; | |
13824 | bp->ptp_clock_info.n_per_out = 0; | |
13825 | bp->ptp_clock_info.pps = 0; | |
13826 | bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq; | |
13827 | bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime; | |
5d45186b RC |
13828 | bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime; |
13829 | bp->ptp_clock_info.settime64 = bnx2x_ptp_settime; | |
eeed018c MK |
13830 | bp->ptp_clock_info.enable = bnx2x_ptp_enable; |
13831 | ||
13832 | bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev); | |
13833 | if (IS_ERR(bp->ptp_clock)) { | |
13834 | bp->ptp_clock = NULL; | |
924613d3 | 13835 | BNX2X_ERR("PTP clock registration failed\n"); |
eeed018c MK |
13836 | } |
13837 | } | |
13838 | ||
1ab4434c AE |
13839 | static int bnx2x_init_one(struct pci_dev *pdev, |
13840 | const struct pci_device_id *ent) | |
13841 | { | |
13842 | struct net_device *dev = NULL; | |
13843 | struct bnx2x *bp; | |
1ab4434c AE |
13844 | int rc, max_non_def_sbs; |
13845 | int rx_count, tx_count, rss_count, doorbell_size; | |
13846 | int max_cos_est; | |
13847 | bool is_vf; | |
13848 | int cnic_cnt; | |
13849 | ||
12a8541d YM |
13850 | /* Management FW 'remembers' living interfaces. Allow it some time |
13851 | * to forget previously living interfaces, allowing a proper re-load. | |
13852 | */ | |
cd9c3997 MS |
13853 | if (is_kdump_kernel()) { |
13854 | ktime_t now = ktime_get_boottime(); | |
13855 | ktime_t fw_ready_time = ktime_set(5, 0); | |
13856 | ||
13857 | if (ktime_before(now, fw_ready_time)) | |
13858 | msleep(ktime_ms_delta(fw_ready_time, now)); | |
13859 | } | |
12a8541d | 13860 | |
1ab4434c AE |
13861 | /* An estimated maximum supported CoS number according to the chip |
13862 | * version. | |
13863 | * We will try to roughly estimate the maximum number of CoSes this chip | |
13864 | * may support in order to minimize the memory allocated for Tx | |
13865 | * netdev_queue's. This number will be accurately calculated during the | |
13866 | * initialization of bp->max_cos based on the chip versions AND chip | |
13867 | * revision in the bnx2x_init_bp(). | |
13868 | */ | |
13869 | max_cos_est = set_max_cos_est(ent->driver_data); | |
13870 | if (max_cos_est < 0) | |
13871 | return max_cos_est; | |
13872 | is_vf = set_is_vf(ent->driver_data); | |
13873 | cnic_cnt = is_vf ? 0 : 1; | |
13874 | ||
60cad4e6 AE |
13875 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt); |
13876 | ||
13877 | /* add another SB for VF as it has no default SB */ | |
13878 | max_non_def_sbs += is_vf ? 1 : 0; | |
6383c0b3 AE |
13879 | |
13880 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
60cad4e6 | 13881 | rss_count = max_non_def_sbs - cnic_cnt; |
1ab4434c AE |
13882 | |
13883 | if (rss_count < 1) | |
13884 | return -EINVAL; | |
6383c0b3 AE |
13885 | |
13886 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
55c11941 | 13887 | rx_count = rss_count + cnic_cnt; |
6383c0b3 | 13888 | |
1ab4434c | 13889 | /* Maximum number of netdev Tx queues: |
37ae41a9 | 13890 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 |
6383c0b3 | 13891 | */ |
55c11941 | 13892 | tx_count = rss_count * max_cos_est + cnic_cnt; |
f85582f8 | 13893 | |
a2fbb9ea | 13894 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 13895 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
41de8d4c | 13896 | if (!dev) |
a2fbb9ea ET |
13897 | return -ENOMEM; |
13898 | ||
a2fbb9ea | 13899 | bp = netdev_priv(dev); |
a2fbb9ea | 13900 | |
1ab4434c AE |
13901 | bp->flags = 0; |
13902 | if (is_vf) | |
13903 | bp->flags |= IS_VF_FLAG; | |
13904 | ||
6383c0b3 | 13905 | bp->igu_sb_cnt = max_non_def_sbs; |
1ab4434c | 13906 | bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; |
6383c0b3 | 13907 | bp->msg_enable = debug; |
55c11941 | 13908 | bp->cnic_support = cnic_cnt; |
4bd9b0ff | 13909 | bp->cnic_probe = bnx2x_cnic_probe; |
55c11941 | 13910 | |
6383c0b3 | 13911 | pci_set_drvdata(pdev, dev); |
523224a3 | 13912 | |
1ab4434c | 13913 | rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); |
a2fbb9ea ET |
13914 | if (rc < 0) { |
13915 | free_netdev(dev); | |
13916 | return rc; | |
13917 | } | |
13918 | ||
1ab4434c AE |
13919 | BNX2X_DEV_INFO("This is a %s function\n", |
13920 | IS_PF(bp) ? "physical" : "virtual"); | |
55c11941 | 13921 | BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); |
1ab4434c | 13922 | BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); |
60aa0509 | 13923 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
2de67439 | 13924 | tx_count, rx_count); |
60aa0509 | 13925 | |
34f80b04 | 13926 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
13927 | if (rc) |
13928 | goto init_one_exit; | |
13929 | ||
1ab4434c AE |
13930 | /* Map doorbells here as we need the real value of bp->max_cos which |
13931 | * is initialized in bnx2x_init_bp() to determine the number of | |
13932 | * l2 connections. | |
6383c0b3 | 13933 | */ |
1ab4434c | 13934 | if (IS_VF(bp)) { |
1d6f3cd8 | 13935 | bp->doorbells = bnx2x_vf_doorbells(bp); |
6411280a AE |
13936 | rc = bnx2x_vf_pci_alloc(bp); |
13937 | if (rc) | |
bae5499c | 13938 | goto init_one_freemem; |
1ab4434c AE |
13939 | } else { |
13940 | doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); | |
13941 | if (doorbell_size > pci_resource_len(pdev, 2)) { | |
13942 | dev_err(&bp->pdev->dev, | |
13943 | "Cannot map doorbells, bar size too small, aborting\n"); | |
13944 | rc = -ENOMEM; | |
bae5499c | 13945 | goto init_one_freemem; |
1ab4434c | 13946 | } |
4bdc0d67 | 13947 | bp->doorbells = ioremap(pci_resource_start(pdev, 2), |
1ab4434c | 13948 | doorbell_size); |
37ae41a9 | 13949 | } |
6383c0b3 AE |
13950 | if (!bp->doorbells) { |
13951 | dev_err(&bp->pdev->dev, | |
13952 | "Cannot map doorbell space, aborting\n"); | |
13953 | rc = -ENOMEM; | |
bae5499c | 13954 | goto init_one_freemem; |
6383c0b3 AE |
13955 | } |
13956 | ||
be1f1ffa AE |
13957 | if (IS_VF(bp)) { |
13958 | rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); | |
13959 | if (rc) | |
bae5499c | 13960 | goto init_one_freemem; |
83bd9eb8 MS |
13961 | |
13962 | #ifdef CONFIG_BNX2X_SRIOV | |
13963 | /* VF with OLD Hypervisor or old PF do not support filtering */ | |
13964 | if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) { | |
13965 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
13966 | dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
13967 | } | |
13968 | #endif | |
be1f1ffa AE |
13969 | } |
13970 | ||
3c76feff AE |
13971 | /* Enable SRIOV if capability found in configuration space */ |
13972 | rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); | |
290ca2bb | 13973 | if (rc) |
bae5499c | 13974 | goto init_one_freemem; |
290ca2bb | 13975 | |
523224a3 | 13976 | /* calc qm_cid_count */ |
6383c0b3 | 13977 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
1ab4434c | 13978 | BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); |
523224a3 | 13979 | |
55c11941 | 13980 | /* disable FCOE L2 queue for E1x*/ |
62ac0dc9 | 13981 | if (CHIP_IS_E1x(bp)) |
ec6ba945 VZ |
13982 | bp->flags |= NO_FCOE_FLAG; |
13983 | ||
0e8d2ec5 MS |
13984 | /* Set bp->num_queues for MSI-X mode*/ |
13985 | bnx2x_set_num_queues(bp); | |
13986 | ||
25985edc | 13987 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
0e8d2ec5 | 13988 | * needed. |
d6214d7a | 13989 | */ |
1ab4434c AE |
13990 | rc = bnx2x_set_int_mode(bp); |
13991 | if (rc) { | |
13992 | dev_err(&pdev->dev, "Cannot set interrupts\n"); | |
bae5499c | 13993 | goto init_one_freemem; |
1ab4434c | 13994 | } |
04c46736 | 13995 | BNX2X_DEV_INFO("set interrupts successfully\n"); |
d6214d7a | 13996 | |
1ab4434c | 13997 | /* register the net device */ |
b340007f VZ |
13998 | rc = register_netdev(dev); |
13999 | if (rc) { | |
14000 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
bae5499c | 14001 | goto init_one_freemem; |
b340007f | 14002 | } |
1ab4434c | 14003 | BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); |
b340007f | 14004 | |
ec6ba945 VZ |
14005 | if (!NO_FCOE(bp)) { |
14006 | /* Add storage MAC address */ | |
14007 | rtnl_lock(); | |
14008 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
14009 | rtnl_unlock(); | |
14010 | } | |
cc04a1dd BH |
14011 | BNX2X_DEV_INFO( |
14012 | "%s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM\n", | |
14013 | board_info[ent->driver_data].name, | |
14014 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
14015 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
14016 | pcie_print_link_status(bp->pdev); | |
c016201c | 14017 | |
230d00eb YM |
14018 | if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) |
14019 | bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED); | |
14020 | ||
a2fbb9ea | 14021 | return 0; |
34f80b04 | 14022 | |
bae5499c VK |
14023 | init_one_freemem: |
14024 | bnx2x_free_mem_bp(bp); | |
14025 | ||
34f80b04 | 14026 | init_one_exit: |
33d8e6a5 YM |
14027 | bnx2x_disable_pcie_error_reporting(bp); |
14028 | ||
34f80b04 EG |
14029 | if (bp->regview) |
14030 | iounmap(bp->regview); | |
14031 | ||
1ab4434c | 14032 | if (IS_PF(bp) && bp->doorbells) |
34f80b04 EG |
14033 | iounmap(bp->doorbells); |
14034 | ||
14035 | free_netdev(dev); | |
14036 | ||
14037 | if (atomic_read(&pdev->enable_cnt) == 1) | |
14038 | pci_release_regions(pdev); | |
14039 | ||
14040 | pci_disable_device(pdev); | |
34f80b04 EG |
14041 | |
14042 | return rc; | |
a2fbb9ea ET |
14043 | } |
14044 | ||
b030ed2f YM |
14045 | static void __bnx2x_remove(struct pci_dev *pdev, |
14046 | struct net_device *dev, | |
14047 | struct bnx2x *bp, | |
14048 | bool remove_netdev) | |
a2fbb9ea | 14049 | { |
ec6ba945 VZ |
14050 | /* Delete storage MAC address */ |
14051 | if (!NO_FCOE(bp)) { | |
14052 | rtnl_lock(); | |
14053 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
14054 | rtnl_unlock(); | |
14055 | } | |
ec6ba945 | 14056 | |
98507672 SR |
14057 | #ifdef BCM_DCBNL |
14058 | /* Delete app tlvs from dcbnl */ | |
14059 | bnx2x_dcbnl_update_applist(bp, true); | |
14060 | #endif | |
14061 | ||
a6d3a5ba BW |
14062 | if (IS_PF(bp) && |
14063 | !BP_NOMCP(bp) && | |
14064 | (bp->flags & BC_SUPPORTS_RMMOD_CMD)) | |
14065 | bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); | |
14066 | ||
b030ed2f YM |
14067 | /* Close the interface - either directly or implicitly */ |
14068 | if (remove_netdev) { | |
14069 | unregister_netdev(dev); | |
14070 | } else { | |
14071 | rtnl_lock(); | |
6ef5a92c | 14072 | dev_close(dev); |
b030ed2f YM |
14073 | rtnl_unlock(); |
14074 | } | |
a2fbb9ea | 14075 | |
78c3bcc5 AE |
14076 | bnx2x_iov_remove_one(bp); |
14077 | ||
084d6cbb | 14078 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
04860eb7 | 14079 | if (IS_PF(bp)) { |
1ab4434c | 14080 | bnx2x_set_power_state(bp, PCI_D0); |
230d00eb | 14081 | bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED); |
084d6cbb | 14082 | |
04860eb7 MC |
14083 | /* Set endianity registers to reset values in case next driver |
14084 | * boots in different endianty environment. | |
14085 | */ | |
14086 | bnx2x_reset_endianity(bp); | |
14087 | } | |
14088 | ||
d6214d7a DK |
14089 | /* Disable MSI/MSI-X */ |
14090 | bnx2x_disable_msi(bp); | |
f85582f8 | 14091 | |
084d6cbb | 14092 | /* Power off */ |
1ab4434c AE |
14093 | if (IS_PF(bp)) |
14094 | bnx2x_set_power_state(bp, PCI_D3hot); | |
084d6cbb | 14095 | |
72fd0718 | 14096 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 14097 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
290ca2bb | 14098 | |
4513f925 AE |
14099 | /* send message via vfpf channel to release the resources of this vf */ |
14100 | if (IS_VF(bp)) | |
14101 | bnx2x_vfpf_release(bp); | |
72fd0718 | 14102 | |
b030ed2f YM |
14103 | /* Assumes no further PCIe PM changes will occur */ |
14104 | if (system_state == SYSTEM_POWER_OFF) { | |
14105 | pci_wake_from_d3(pdev, bp->wol); | |
14106 | pci_set_power_state(pdev, PCI_D3hot); | |
14107 | } | |
14108 | ||
33d8e6a5 | 14109 | bnx2x_disable_pcie_error_reporting(bp); |
d9aee591 YM |
14110 | if (remove_netdev) { |
14111 | if (bp->regview) | |
14112 | iounmap(bp->regview); | |
33d8e6a5 | 14113 | |
d9aee591 YM |
14114 | /* For vfs, doorbells are part of the regview and were unmapped |
14115 | * along with it. FW is only loaded by PF. | |
14116 | */ | |
14117 | if (IS_PF(bp)) { | |
14118 | if (bp->doorbells) | |
14119 | iounmap(bp->doorbells); | |
eb2afd4a | 14120 | |
d9aee591 | 14121 | bnx2x_release_firmware(bp); |
e2a367f8 YM |
14122 | } else { |
14123 | bnx2x_vf_pci_dealloc(bp); | |
d9aee591 YM |
14124 | } |
14125 | bnx2x_free_mem_bp(bp); | |
523224a3 | 14126 | |
b030ed2f | 14127 | free_netdev(dev); |
34f80b04 | 14128 | |
d9aee591 YM |
14129 | if (atomic_read(&pdev->enable_cnt) == 1) |
14130 | pci_release_regions(pdev); | |
34f80b04 | 14131 | |
5f6db130 YM |
14132 | pci_disable_device(pdev); |
14133 | } | |
a2fbb9ea ET |
14134 | } |
14135 | ||
b030ed2f YM |
14136 | static void bnx2x_remove_one(struct pci_dev *pdev) |
14137 | { | |
14138 | struct net_device *dev = pci_get_drvdata(pdev); | |
14139 | struct bnx2x *bp; | |
14140 | ||
14141 | if (!dev) { | |
14142 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); | |
14143 | return; | |
14144 | } | |
14145 | bp = netdev_priv(dev); | |
14146 | ||
14147 | __bnx2x_remove(pdev, dev, bp, true); | |
14148 | } | |
14149 | ||
f8ef6e44 YG |
14150 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
14151 | { | |
7fa6f340 | 14152 | bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; |
f8ef6e44 YG |
14153 | |
14154 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
14155 | ||
55c11941 MS |
14156 | if (CNIC_LOADED(bp)) |
14157 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
14158 | ||
619c5cb6 VZ |
14159 | /* Stop Tx */ |
14160 | bnx2x_tx_disable(bp); | |
26614ba5 MS |
14161 | /* Delete all NAPI objects */ |
14162 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
14163 | if (CNIC_LOADED(bp)) |
14164 | bnx2x_del_all_napi_cnic(bp); | |
7fa6f340 | 14165 | netdev_reset_tc(bp->dev); |
f8ef6e44 YG |
14166 | |
14167 | del_timer_sync(&bp->timer); | |
0c0e6341 | 14168 | cancel_delayed_work_sync(&bp->sp_task); |
14169 | cancel_delayed_work_sync(&bp->period_task); | |
619c5cb6 | 14170 | |
c6e36d8c YM |
14171 | if (!down_timeout(&bp->stats_lock, HZ / 10)) { |
14172 | bp->stats_state = STATS_STATE_DISABLED; | |
14173 | up(&bp->stats_lock); | |
14174 | } | |
f8ef6e44 | 14175 | |
7fa6f340 | 14176 | bnx2x_save_statistics(bp); |
f8ef6e44 | 14177 | |
619c5cb6 VZ |
14178 | netif_carrier_off(bp->dev); |
14179 | ||
f8ef6e44 YG |
14180 | return 0; |
14181 | } | |
14182 | ||
493adb1f WX |
14183 | /** |
14184 | * bnx2x_io_error_detected - called when PCI error is detected | |
14185 | * @pdev: Pointer to PCI device | |
14186 | * @state: The current pci connection state | |
14187 | * | |
14188 | * This function is called after a PCI bus error affecting | |
14189 | * this device has been detected. | |
14190 | */ | |
14191 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
14192 | pci_channel_state_t state) | |
14193 | { | |
14194 | struct net_device *dev = pci_get_drvdata(pdev); | |
14195 | struct bnx2x *bp = netdev_priv(dev); | |
14196 | ||
14197 | rtnl_lock(); | |
14198 | ||
7fa6f340 YM |
14199 | BNX2X_ERR("IO error detected\n"); |
14200 | ||
493adb1f WX |
14201 | netif_device_detach(dev); |
14202 | ||
07ce50e4 DN |
14203 | if (state == pci_channel_io_perm_failure) { |
14204 | rtnl_unlock(); | |
14205 | return PCI_ERS_RESULT_DISCONNECT; | |
14206 | } | |
14207 | ||
493adb1f | 14208 | if (netif_running(dev)) |
f8ef6e44 | 14209 | bnx2x_eeh_nic_unload(bp); |
493adb1f | 14210 | |
7fa6f340 YM |
14211 | bnx2x_prev_path_mark_eeh(bp); |
14212 | ||
493adb1f WX |
14213 | pci_disable_device(pdev); |
14214 | ||
14215 | rtnl_unlock(); | |
14216 | ||
14217 | /* Request a slot reset */ | |
14218 | return PCI_ERS_RESULT_NEED_RESET; | |
14219 | } | |
14220 | ||
14221 | /** | |
14222 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
14223 | * @pdev: Pointer to PCI device | |
14224 | * | |
14225 | * Restart the card from scratch, as if from a cold-boot. | |
14226 | */ | |
14227 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
14228 | { | |
14229 | struct net_device *dev = pci_get_drvdata(pdev); | |
14230 | struct bnx2x *bp = netdev_priv(dev); | |
7fa6f340 | 14231 | int i; |
493adb1f WX |
14232 | |
14233 | rtnl_lock(); | |
7fa6f340 | 14234 | BNX2X_ERR("IO slot reset initializing...\n"); |
493adb1f WX |
14235 | if (pci_enable_device(pdev)) { |
14236 | dev_err(&pdev->dev, | |
14237 | "Cannot re-enable PCI device after reset\n"); | |
14238 | rtnl_unlock(); | |
14239 | return PCI_ERS_RESULT_DISCONNECT; | |
14240 | } | |
14241 | ||
14242 | pci_set_master(pdev); | |
14243 | pci_restore_state(pdev); | |
70632d0a | 14244 | pci_save_state(pdev); |
493adb1f WX |
14245 | |
14246 | if (netif_running(dev)) | |
14247 | bnx2x_set_power_state(bp, PCI_D0); | |
14248 | ||
7fa6f340 YM |
14249 | if (netif_running(dev)) { |
14250 | BNX2X_ERR("IO slot reset --> driver unload\n"); | |
e68072ef YM |
14251 | |
14252 | /* MCP should have been reset; Need to wait for validity */ | |
f7084059 GP |
14253 | if (bnx2x_init_shmem(bp)) { |
14254 | rtnl_unlock(); | |
14255 | return PCI_ERS_RESULT_DISCONNECT; | |
14256 | } | |
e68072ef | 14257 | |
7fa6f340 YM |
14258 | if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { |
14259 | u32 v; | |
14260 | ||
14261 | v = SHMEM2_RD(bp, | |
14262 | drv_capabilities_flag[BP_FW_MB_IDX(bp)]); | |
14263 | SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], | |
14264 | v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); | |
14265 | } | |
14266 | bnx2x_drain_tx_queues(bp); | |
14267 | bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); | |
14268 | bnx2x_netif_stop(bp, 1); | |
14269 | bnx2x_free_irq(bp); | |
14270 | ||
14271 | /* Report UNLOAD_DONE to MCP */ | |
14272 | bnx2x_send_unload_done(bp, true); | |
14273 | ||
14274 | bp->sp_state = 0; | |
14275 | bp->port.pmf = 0; | |
14276 | ||
14277 | bnx2x_prev_unload(bp); | |
14278 | ||
16a5fd92 | 14279 | /* We should have reseted the engine, so It's fair to |
7fa6f340 YM |
14280 | * assume the FW will no longer write to the bnx2x driver. |
14281 | */ | |
14282 | bnx2x_squeeze_objects(bp); | |
14283 | bnx2x_free_skbs(bp); | |
14284 | for_each_rx_queue(bp, i) | |
14285 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); | |
14286 | bnx2x_free_fp_mem(bp); | |
14287 | bnx2x_free_mem(bp); | |
14288 | ||
14289 | bp->state = BNX2X_STATE_CLOSED; | |
14290 | } | |
14291 | ||
493adb1f WX |
14292 | rtnl_unlock(); |
14293 | ||
14294 | return PCI_ERS_RESULT_RECOVERED; | |
14295 | } | |
14296 | ||
14297 | /** | |
14298 | * bnx2x_io_resume - called when traffic can start flowing again | |
14299 | * @pdev: Pointer to PCI device | |
14300 | * | |
14301 | * This callback is called when the error recovery driver tells us that | |
14302 | * its OK to resume normal operation. | |
14303 | */ | |
14304 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
14305 | { | |
14306 | struct net_device *dev = pci_get_drvdata(pdev); | |
14307 | struct bnx2x *bp = netdev_priv(dev); | |
14308 | ||
72fd0718 | 14309 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 14310 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
72fd0718 VZ |
14311 | return; |
14312 | } | |
14313 | ||
493adb1f WX |
14314 | rtnl_lock(); |
14315 | ||
7fa6f340 YM |
14316 | bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & |
14317 | DRV_MSG_SEQ_NUMBER_MASK; | |
14318 | ||
493adb1f | 14319 | if (netif_running(dev)) |
f8ef6e44 | 14320 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
14321 | |
14322 | netif_device_attach(dev); | |
14323 | ||
14324 | rtnl_unlock(); | |
14325 | } | |
14326 | ||
3646f0e5 | 14327 | static const struct pci_error_handlers bnx2x_err_handler = { |
493adb1f | 14328 | .error_detected = bnx2x_io_error_detected, |
356e2385 EG |
14329 | .slot_reset = bnx2x_io_slot_reset, |
14330 | .resume = bnx2x_io_resume, | |
493adb1f WX |
14331 | }; |
14332 | ||
b030ed2f YM |
14333 | static void bnx2x_shutdown(struct pci_dev *pdev) |
14334 | { | |
14335 | struct net_device *dev = pci_get_drvdata(pdev); | |
14336 | struct bnx2x *bp; | |
14337 | ||
14338 | if (!dev) | |
14339 | return; | |
14340 | ||
14341 | bp = netdev_priv(dev); | |
14342 | if (!bp) | |
14343 | return; | |
14344 | ||
14345 | rtnl_lock(); | |
14346 | netif_device_detach(dev); | |
14347 | rtnl_unlock(); | |
14348 | ||
14349 | /* Don't remove the netdevice, as there are scenarios which will cause | |
14350 | * the kernel to hang, e.g., when trying to remove bnx2i while the | |
14351 | * rootfs is mounted from SAN. | |
14352 | */ | |
14353 | __bnx2x_remove(pdev, dev, bp, false); | |
14354 | } | |
14355 | ||
a2fbb9ea | 14356 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
14357 | .name = DRV_MODULE_NAME, |
14358 | .id_table = bnx2x_pci_tbl, | |
14359 | .probe = bnx2x_init_one, | |
0329aba1 | 14360 | .remove = bnx2x_remove_one, |
4ced637b | 14361 | .driver.pm = &bnx2x_pm_ops, |
493adb1f | 14362 | .err_handler = &bnx2x_err_handler, |
3c76feff AE |
14363 | #ifdef CONFIG_BNX2X_SRIOV |
14364 | .sriov_configure = bnx2x_sriov_configure, | |
14365 | #endif | |
b030ed2f | 14366 | .shutdown = bnx2x_shutdown, |
a2fbb9ea ET |
14367 | }; |
14368 | ||
14369 | static int __init bnx2x_init(void) | |
14370 | { | |
dd21ca6d SG |
14371 | int ret; |
14372 | ||
1cf167f2 EG |
14373 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
14374 | if (bnx2x_wq == NULL) { | |
7995c64e | 14375 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
14376 | return -ENOMEM; |
14377 | } | |
370d4a26 YM |
14378 | bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov"); |
14379 | if (!bnx2x_iov_wq) { | |
14380 | pr_err("Cannot create iov workqueue\n"); | |
14381 | destroy_workqueue(bnx2x_wq); | |
14382 | return -ENOMEM; | |
14383 | } | |
1cf167f2 | 14384 | |
dd21ca6d SG |
14385 | ret = pci_register_driver(&bnx2x_pci_driver); |
14386 | if (ret) { | |
7995c64e | 14387 | pr_err("Cannot register driver\n"); |
dd21ca6d | 14388 | destroy_workqueue(bnx2x_wq); |
370d4a26 | 14389 | destroy_workqueue(bnx2x_iov_wq); |
dd21ca6d SG |
14390 | } |
14391 | return ret; | |
a2fbb9ea ET |
14392 | } |
14393 | ||
14394 | static void __exit bnx2x_cleanup(void) | |
14395 | { | |
452427b0 | 14396 | struct list_head *pos, *q; |
d76a6111 | 14397 | |
a2fbb9ea | 14398 | pci_unregister_driver(&bnx2x_pci_driver); |
1cf167f2 EG |
14399 | |
14400 | destroy_workqueue(bnx2x_wq); | |
370d4a26 | 14401 | destroy_workqueue(bnx2x_iov_wq); |
452427b0 | 14402 | |
16a5fd92 | 14403 | /* Free globally allocated resources */ |
452427b0 YM |
14404 | list_for_each_safe(pos, q, &bnx2x_prev_list) { |
14405 | struct bnx2x_prev_path_list *tmp = | |
14406 | list_entry(pos, struct bnx2x_prev_path_list, list); | |
14407 | list_del(pos); | |
14408 | kfree(tmp); | |
14409 | } | |
a2fbb9ea ET |
14410 | } |
14411 | ||
3deb8167 YR |
14412 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
14413 | { | |
14414 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
14415 | } | |
14416 | ||
a2fbb9ea ET |
14417 | module_init(bnx2x_init); |
14418 | module_exit(bnx2x_cleanup); | |
14419 | ||
619c5cb6 VZ |
14420 | /** |
14421 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
619c5cb6 | 14422 | * @bp: driver handle |
619c5cb6 | 14423 | * |
16a5fd92 | 14424 | * This function will wait until the ramrod completion returns. |
619c5cb6 VZ |
14425 | * Return 0 if success, -ENODEV if ramrod doesn't return. |
14426 | */ | |
1191cb83 | 14427 | static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) |
619c5cb6 VZ |
14428 | { |
14429 | unsigned long ramrod_flags = 0; | |
14430 | ||
14431 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
14432 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
14433 | &bp->iscsi_l2_mac_obj, true, | |
14434 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
14435 | } | |
993ac7b5 MC |
14436 | |
14437 | /* count denotes the number of new completions we have seen */ | |
14438 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
14439 | { | |
14440 | struct eth_spe *spe; | |
a052997e | 14441 | int cxt_index, cxt_offset; |
993ac7b5 MC |
14442 | |
14443 | #ifdef BNX2X_STOP_ON_ERROR | |
14444 | if (unlikely(bp->panic)) | |
14445 | return; | |
14446 | #endif | |
14447 | ||
14448 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 14449 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
14450 | bp->cnic_spq_pending -= count; |
14451 | ||
c2bff63f DK |
14452 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
14453 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
14454 | & SPE_HDR_CONN_TYPE) >> | |
14455 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
14456 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
14457 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
14458 | |
14459 | /* Set validation for iSCSI L2 client before sending SETUP | |
14460 | * ramrod | |
14461 | */ | |
14462 | if (type == ETH_CONNECTION_TYPE) { | |
a052997e | 14463 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { |
37ae41a9 | 14464 | cxt_index = BNX2X_ISCSI_ETH_CID(bp) / |
a052997e | 14465 | ILT_PAGE_CIDS; |
37ae41a9 | 14466 | cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - |
a052997e MS |
14467 | (cxt_index * ILT_PAGE_CIDS); |
14468 | bnx2x_set_ctx_validation(bp, | |
14469 | &bp->context[cxt_index]. | |
14470 | vcxt[cxt_offset].eth, | |
37ae41a9 | 14471 | BNX2X_ISCSI_ETH_CID(bp)); |
a052997e | 14472 | } |
c2bff63f DK |
14473 | } |
14474 | ||
619c5cb6 VZ |
14475 | /* |
14476 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
14477 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
14478 | * COMMON ramrods is not more than the EQ and SPQ can |
14479 | * accommodate. | |
c2bff63f | 14480 | */ |
6e30dd4e VZ |
14481 | if (type == ETH_CONNECTION_TYPE) { |
14482 | if (!atomic_read(&bp->cq_spq_left)) | |
14483 | break; | |
14484 | else | |
14485 | atomic_dec(&bp->cq_spq_left); | |
14486 | } else if (type == NONE_CONNECTION_TYPE) { | |
14487 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
14488 | break; |
14489 | else | |
6e30dd4e | 14490 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
14491 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
14492 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
14493 | if (bp->cnic_spq_pending >= |
14494 | bp->cnic_eth_dev.max_kwqe_pending) | |
14495 | break; | |
14496 | else | |
14497 | bp->cnic_spq_pending++; | |
14498 | } else { | |
14499 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
14500 | bnx2x_panic(); | |
993ac7b5 | 14501 | break; |
c2bff63f | 14502 | } |
993ac7b5 MC |
14503 | |
14504 | spe = bnx2x_sp_get_next(bp); | |
14505 | *spe = *bp->cnic_kwq_cons; | |
14506 | ||
51c1a580 | 14507 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
993ac7b5 MC |
14508 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
14509 | ||
14510 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
14511 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
14512 | else | |
14513 | bp->cnic_kwq_cons++; | |
14514 | } | |
14515 | bnx2x_sp_prod_update(bp); | |
14516 | spin_unlock_bh(&bp->spq_lock); | |
14517 | } | |
14518 | ||
14519 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
14520 | struct kwqe_16 *kwqes[], u32 count) | |
14521 | { | |
14522 | struct bnx2x *bp = netdev_priv(dev); | |
14523 | int i; | |
14524 | ||
14525 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 MS |
14526 | if (unlikely(bp->panic)) { |
14527 | BNX2X_ERR("Can't post to SP queue while panic\n"); | |
993ac7b5 | 14528 | return -EIO; |
51c1a580 | 14529 | } |
993ac7b5 MC |
14530 | #endif |
14531 | ||
95c6c616 AE |
14532 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
14533 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
51c1a580 | 14534 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
95c6c616 AE |
14535 | return -EAGAIN; |
14536 | } | |
14537 | ||
993ac7b5 MC |
14538 | spin_lock_bh(&bp->spq_lock); |
14539 | ||
14540 | for (i = 0; i < count; i++) { | |
14541 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
14542 | ||
14543 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
14544 | break; | |
14545 | ||
14546 | *bp->cnic_kwq_prod = *spe; | |
14547 | ||
14548 | bp->cnic_kwq_pending++; | |
14549 | ||
51c1a580 | 14550 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
993ac7b5 | 14551 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
523224a3 DK |
14552 | spe->data.update_data_addr.hi, |
14553 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
14554 | bp->cnic_kwq_pending); |
14555 | ||
14556 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
14557 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
14558 | else | |
14559 | bp->cnic_kwq_prod++; | |
14560 | } | |
14561 | ||
14562 | spin_unlock_bh(&bp->spq_lock); | |
14563 | ||
14564 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
14565 | bnx2x_cnic_sp_post(bp, 0); | |
14566 | ||
14567 | return i; | |
14568 | } | |
14569 | ||
14570 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
14571 | { | |
14572 | struct cnic_ops *c_ops; | |
14573 | int rc = 0; | |
14574 | ||
14575 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
14576 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
14577 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
14578 | if (c_ops) |
14579 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
14580 | mutex_unlock(&bp->cnic_mutex); | |
14581 | ||
14582 | return rc; | |
14583 | } | |
14584 | ||
14585 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
14586 | { | |
14587 | struct cnic_ops *c_ops; | |
14588 | int rc = 0; | |
14589 | ||
14590 | rcu_read_lock(); | |
14591 | c_ops = rcu_dereference(bp->cnic_ops); | |
14592 | if (c_ops) | |
14593 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
14594 | rcu_read_unlock(); | |
14595 | ||
14596 | return rc; | |
14597 | } | |
14598 | ||
14599 | /* | |
14600 | * for commands that have no data | |
14601 | */ | |
9f6c9258 | 14602 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
14603 | { |
14604 | struct cnic_ctl_info ctl = {0}; | |
14605 | ||
14606 | ctl.cmd = cmd; | |
14607 | ||
14608 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
14609 | } | |
14610 | ||
619c5cb6 | 14611 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 14612 | { |
619c5cb6 | 14613 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
14614 | |
14615 | /* first we tell CNIC and only then we count this as a completion */ | |
14616 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
14617 | ctl.data.comp.cid = cid; | |
619c5cb6 | 14618 | ctl.data.comp.error = err; |
993ac7b5 MC |
14619 | |
14620 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 14621 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
14622 | } |
14623 | ||
619c5cb6 VZ |
14624 | /* Called with netif_addr_lock_bh() taken. |
14625 | * Sets an rx_mode config for an iSCSI ETH client. | |
14626 | * Doesn't block. | |
14627 | * Completion should be checked outside. | |
14628 | */ | |
14629 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
14630 | { | |
14631 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
14632 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
14633 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
14634 | ||
14635 | if (start) { | |
14636 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
14637 | * because it's the only way for UIO Queue to accept | |
14638 | * multicasts (in non-promiscuous mode only one Queue per | |
14639 | * function will receive multicast packets (leading in our | |
14640 | * case). | |
14641 | */ | |
14642 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
14643 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
14644 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
14645 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
14646 | ||
14647 | /* Clear STOP_PENDING bit if START is requested */ | |
14648 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
14649 | ||
14650 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
14651 | } else | |
14652 | /* Clear START_PENDING bit if STOP is requested */ | |
14653 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
14654 | ||
14655 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
14656 | set_bit(sched_state, &bp->sp_state); | |
14657 | else { | |
14658 | __set_bit(RAMROD_RX, &ramrod_flags); | |
14659 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
14660 | ramrod_flags); | |
14661 | } | |
14662 | } | |
14663 | ||
993ac7b5 MC |
14664 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
14665 | { | |
14666 | struct bnx2x *bp = netdev_priv(dev); | |
14667 | int rc = 0; | |
14668 | ||
14669 | switch (ctl->cmd) { | |
14670 | case DRV_CTL_CTXTBL_WR_CMD: { | |
14671 | u32 index = ctl->data.io.offset; | |
14672 | dma_addr_t addr = ctl->data.io.dma_addr; | |
14673 | ||
14674 | bnx2x_ilt_wr(bp, index, addr); | |
14675 | break; | |
14676 | } | |
14677 | ||
c2bff63f DK |
14678 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
14679 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
14680 | |
14681 | bnx2x_cnic_sp_post(bp, count); | |
14682 | break; | |
14683 | } | |
14684 | ||
14685 | /* rtnl_lock is held. */ | |
14686 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
14687 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
14688 | unsigned long sp_bits = 0; | |
14689 | ||
14690 | /* Configure the iSCSI classification object */ | |
14691 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
14692 | cp->iscsi_l2_client_id, | |
14693 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
14694 | bnx2x_sp(bp, mac_rdata), | |
14695 | bnx2x_sp_mapping(bp, mac_rdata), | |
14696 | BNX2X_FILTER_MAC_PENDING, | |
14697 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
14698 | &bp->macs_pool); | |
ec6ba945 | 14699 | |
523224a3 | 14700 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
14701 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
14702 | if (rc) | |
14703 | break; | |
523224a3 | 14704 | |
523224a3 DK |
14705 | barrier(); |
14706 | ||
619c5cb6 VZ |
14707 | /* Start accepting on iSCSI L2 ring */ |
14708 | ||
14709 | netif_addr_lock_bh(dev); | |
14710 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
14711 | netif_addr_unlock_bh(dev); | |
14712 | ||
14713 | /* bits to wait on */ | |
14714 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
14715 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
14716 | ||
14717 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
14718 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 14719 | |
993ac7b5 MC |
14720 | break; |
14721 | } | |
14722 | ||
14723 | /* rtnl_lock is held. */ | |
14724 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 14725 | unsigned long sp_bits = 0; |
993ac7b5 | 14726 | |
523224a3 | 14727 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
14728 | netif_addr_lock_bh(dev); |
14729 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
14730 | netif_addr_unlock_bh(dev); | |
14731 | ||
14732 | /* bits to wait on */ | |
14733 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
14734 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
14735 | ||
14736 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
14737 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 14738 | |
523224a3 DK |
14739 | barrier(); |
14740 | ||
14741 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
14742 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
14743 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
14744 | break; |
14745 | } | |
c2bff63f DK |
14746 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
14747 | int count = ctl->data.credit.credit_count; | |
14748 | ||
4e857c58 | 14749 | smp_mb__before_atomic(); |
6e30dd4e | 14750 | atomic_add(count, &bp->cq_spq_left); |
4e857c58 | 14751 | smp_mb__after_atomic(); |
c2bff63f DK |
14752 | break; |
14753 | } | |
1d187b34 | 14754 | case DRV_CTL_ULP_REGISTER_CMD: { |
2e499d3c | 14755 | int ulp_type = ctl->data.register_data.ulp_type; |
1d187b34 BW |
14756 | |
14757 | if (CHIP_IS_E3(bp)) { | |
14758 | int idx = BP_FW_MB_IDX(bp); | |
2e499d3c BW |
14759 | u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); |
14760 | int path = BP_PATH(bp); | |
14761 | int port = BP_PORT(bp); | |
14762 | int i; | |
14763 | u32 scratch_offset; | |
14764 | u32 *host_addr; | |
1d187b34 | 14765 | |
2e499d3c | 14766 | /* first write capability to shmem2 */ |
1d187b34 BW |
14767 | if (ulp_type == CNIC_ULP_ISCSI) |
14768 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
14769 | else if (ulp_type == CNIC_ULP_FCOE) | |
14770 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
14771 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
2e499d3c BW |
14772 | |
14773 | if ((ulp_type != CNIC_ULP_FCOE) || | |
14774 | (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || | |
14775 | (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) | |
14776 | break; | |
14777 | ||
14778 | /* if reached here - should write fcoe capabilities */ | |
14779 | scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); | |
14780 | if (!scratch_offset) | |
14781 | break; | |
14782 | scratch_offset += offsetof(struct glob_ncsi_oem_data, | |
14783 | fcoe_features[path][port]); | |
14784 | host_addr = (u32 *) &(ctl->data.register_data. | |
14785 | fcoe_features); | |
14786 | for (i = 0; i < sizeof(struct fcoe_capabilities); | |
14787 | i += 4) | |
14788 | REG_WR(bp, scratch_offset + i, | |
14789 | *(host_addr + i/4)); | |
1d187b34 | 14790 | } |
42f8277f | 14791 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); |
1d187b34 BW |
14792 | break; |
14793 | } | |
2e499d3c | 14794 | |
1d187b34 BW |
14795 | case DRV_CTL_ULP_UNREGISTER_CMD: { |
14796 | int ulp_type = ctl->data.ulp_type; | |
14797 | ||
14798 | if (CHIP_IS_E3(bp)) { | |
14799 | int idx = BP_FW_MB_IDX(bp); | |
14800 | u32 cap; | |
14801 | ||
14802 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
14803 | if (ulp_type == CNIC_ULP_ISCSI) | |
14804 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
14805 | else if (ulp_type == CNIC_ULP_FCOE) | |
14806 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
14807 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
14808 | } | |
42f8277f | 14809 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); |
1d187b34 BW |
14810 | break; |
14811 | } | |
993ac7b5 MC |
14812 | |
14813 | default: | |
14814 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
14815 | rc = -EINVAL; | |
14816 | } | |
14817 | ||
97ac4ef7 YM |
14818 | /* For storage-only interfaces, change driver state */ |
14819 | if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) { | |
14820 | switch (ctl->drv_state) { | |
14821 | case DRV_NOP: | |
14822 | break; | |
14823 | case DRV_ACTIVE: | |
14824 | bnx2x_set_os_driver_state(bp, | |
14825 | OS_DRIVER_STATE_ACTIVE); | |
14826 | break; | |
14827 | case DRV_INACTIVE: | |
14828 | bnx2x_set_os_driver_state(bp, | |
14829 | OS_DRIVER_STATE_DISABLED); | |
14830 | break; | |
14831 | case DRV_UNLOADED: | |
14832 | bnx2x_set_os_driver_state(bp, | |
14833 | OS_DRIVER_STATE_NOT_LOADED); | |
14834 | break; | |
14835 | default: | |
14836 | BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state); | |
14837 | } | |
14838 | } | |
14839 | ||
14840 | return rc; | |
14841 | } | |
14842 | ||
14843 | static int bnx2x_get_fc_npiv(struct net_device *dev, | |
14844 | struct cnic_fc_npiv_tbl *cnic_tbl) | |
14845 | { | |
14846 | struct bnx2x *bp = netdev_priv(dev); | |
14847 | struct bdn_fc_npiv_tbl *tbl = NULL; | |
14848 | u32 offset, entries; | |
14849 | int rc = -EINVAL; | |
14850 | int i; | |
14851 | ||
14852 | if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0])) | |
14853 | goto out; | |
14854 | ||
14855 | DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n"); | |
14856 | ||
14857 | tbl = kmalloc(sizeof(*tbl), GFP_KERNEL); | |
14858 | if (!tbl) { | |
14859 | BNX2X_ERR("Failed to allocate fc_npiv table\n"); | |
14860 | goto out; | |
14861 | } | |
14862 | ||
14863 | offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]); | |
1e6bb1a3 YM |
14864 | if (!offset) { |
14865 | DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n"); | |
14866 | goto out; | |
14867 | } | |
97ac4ef7 YM |
14868 | DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset); |
14869 | ||
14870 | /* Read the table contents from nvram */ | |
14871 | if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) { | |
14872 | BNX2X_ERR("Failed to read FC-NPIV table\n"); | |
14873 | goto out; | |
14874 | } | |
14875 | ||
14876 | /* Since bnx2x_nvram_read() returns data in be32, we need to convert | |
14877 | * the number of entries back to cpu endianness. | |
14878 | */ | |
14879 | entries = tbl->fc_npiv_cfg.num_of_npiv; | |
14880 | entries = (__force u32)be32_to_cpu((__force __be32)entries); | |
14881 | tbl->fc_npiv_cfg.num_of_npiv = entries; | |
14882 | ||
14883 | if (!tbl->fc_npiv_cfg.num_of_npiv) { | |
14884 | DP(BNX2X_MSG_MCP, | |
14885 | "No FC-NPIV table [valid, simply not present]\n"); | |
14886 | goto out; | |
14887 | } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) { | |
14888 | BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n", | |
14889 | tbl->fc_npiv_cfg.num_of_npiv); | |
14890 | goto out; | |
14891 | } else { | |
14892 | DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n", | |
14893 | tbl->fc_npiv_cfg.num_of_npiv); | |
14894 | } | |
14895 | ||
14896 | /* Copy the data into cnic-provided struct */ | |
14897 | cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv; | |
14898 | for (i = 0; i < cnic_tbl->count; i++) { | |
14899 | memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8); | |
14900 | memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8); | |
14901 | } | |
14902 | ||
14903 | rc = 0; | |
14904 | out: | |
14905 | kfree(tbl); | |
993ac7b5 MC |
14906 | return rc; |
14907 | } | |
14908 | ||
9f6c9258 | 14909 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
14910 | { |
14911 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
14912 | ||
14913 | if (bp->flags & USING_MSIX_FLAG) { | |
14914 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
14915 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
14916 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
14917 | } else { | |
14918 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
14919 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
14920 | } | |
619c5cb6 | 14921 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
14922 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
14923 | else | |
14924 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
14925 | ||
619c5cb6 VZ |
14926 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
14927 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
14928 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
14929 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 14930 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
14931 | |
14932 | cp->num_irq = 2; | |
14933 | } | |
14934 | ||
37ae41a9 MS |
14935 | void bnx2x_setup_cnic_info(struct bnx2x *bp) |
14936 | { | |
14937 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
14938 | ||
37ae41a9 MS |
14939 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
14940 | bnx2x_cid_ilt_lines(bp); | |
14941 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; | |
14942 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); | |
14943 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); | |
14944 | ||
f78afb35 MC |
14945 | DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n", |
14946 | BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid, | |
14947 | cp->iscsi_l2_cid); | |
14948 | ||
37ae41a9 MS |
14949 | if (NO_ISCSI_OOO(bp)) |
14950 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
14951 | } | |
14952 | ||
993ac7b5 MC |
14953 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, |
14954 | void *data) | |
14955 | { | |
14956 | struct bnx2x *bp = netdev_priv(dev); | |
14957 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
55c11941 MS |
14958 | int rc; |
14959 | ||
14960 | DP(NETIF_MSG_IFUP, "Register_cnic called\n"); | |
993ac7b5 | 14961 | |
51c1a580 MS |
14962 | if (ops == NULL) { |
14963 | BNX2X_ERR("NULL ops received\n"); | |
993ac7b5 | 14964 | return -EINVAL; |
51c1a580 | 14965 | } |
993ac7b5 | 14966 | |
55c11941 MS |
14967 | if (!CNIC_SUPPORT(bp)) { |
14968 | BNX2X_ERR("Can't register CNIC when not supported\n"); | |
14969 | return -EOPNOTSUPP; | |
14970 | } | |
14971 | ||
14972 | if (!CNIC_LOADED(bp)) { | |
14973 | rc = bnx2x_load_cnic(bp); | |
14974 | if (rc) { | |
14975 | BNX2X_ERR("CNIC-related load failed\n"); | |
14976 | return rc; | |
14977 | } | |
55c11941 MS |
14978 | } |
14979 | ||
14980 | bp->cnic_enabled = true; | |
14981 | ||
993ac7b5 MC |
14982 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
14983 | if (!bp->cnic_kwq) | |
14984 | return -ENOMEM; | |
14985 | ||
14986 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
14987 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
14988 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
14989 | ||
14990 | bp->cnic_spq_pending = 0; | |
14991 | bp->cnic_kwq_pending = 0; | |
14992 | ||
14993 | bp->cnic_data = data; | |
14994 | ||
14995 | cp->num_irq = 0; | |
619c5cb6 | 14996 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 14997 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 14998 | |
993ac7b5 | 14999 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 15000 | |
993ac7b5 MC |
15001 | rcu_assign_pointer(bp->cnic_ops, ops); |
15002 | ||
42f8277f YM |
15003 | /* Schedule driver to read CNIC driver versions */ |
15004 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); | |
15005 | ||
993ac7b5 MC |
15006 | return 0; |
15007 | } | |
15008 | ||
15009 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
15010 | { | |
15011 | struct bnx2x *bp = netdev_priv(dev); | |
15012 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
15013 | ||
15014 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 | 15015 | cp->drv_state = 0; |
2cfa5a04 | 15016 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
993ac7b5 MC |
15017 | mutex_unlock(&bp->cnic_mutex); |
15018 | synchronize_rcu(); | |
fea75645 | 15019 | bp->cnic_enabled = false; |
993ac7b5 MC |
15020 | kfree(bp->cnic_kwq); |
15021 | bp->cnic_kwq = NULL; | |
15022 | ||
15023 | return 0; | |
15024 | } | |
15025 | ||
a8f47eb7 | 15026 | static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) |
993ac7b5 MC |
15027 | { |
15028 | struct bnx2x *bp = netdev_priv(dev); | |
15029 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
15030 | ||
2ba45142 VZ |
15031 | /* If both iSCSI and FCoE are disabled - return NULL in |
15032 | * order to indicate CNIC that it should not try to work | |
15033 | * with this device. | |
15034 | */ | |
15035 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
15036 | return NULL; | |
15037 | ||
993ac7b5 MC |
15038 | cp->drv_owner = THIS_MODULE; |
15039 | cp->chip_id = CHIP_ID(bp); | |
15040 | cp->pdev = bp->pdev; | |
15041 | cp->io_base = bp->regview; | |
15042 | cp->io_base2 = bp->doorbells; | |
15043 | cp->max_kwqe_pending = 8; | |
523224a3 | 15044 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
15045 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
15046 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 15047 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 15048 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
15049 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
15050 | cp->drv_ctl = bnx2x_drv_ctl; | |
97ac4ef7 | 15051 | cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv; |
993ac7b5 MC |
15052 | cp->drv_register_cnic = bnx2x_register_cnic; |
15053 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
37ae41a9 | 15054 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); |
619c5cb6 VZ |
15055 | cp->iscsi_l2_client_id = |
15056 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
37ae41a9 | 15057 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); |
c2bff63f | 15058 | |
2ba45142 VZ |
15059 | if (NO_ISCSI_OOO(bp)) |
15060 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
15061 | ||
15062 | if (NO_ISCSI(bp)) | |
15063 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
15064 | ||
15065 | if (NO_FCOE(bp)) | |
15066 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
15067 | ||
51c1a580 MS |
15068 | BNX2X_DEV_INFO( |
15069 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", | |
c2bff63f DK |
15070 | cp->ctx_blk_size, |
15071 | cp->ctx_tbl_offset, | |
15072 | cp->ctx_tbl_len, | |
15073 | cp->starting_cid); | |
993ac7b5 MC |
15074 | return cp; |
15075 | } | |
993ac7b5 | 15076 | |
a8f47eb7 | 15077 | static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) |
9b176b6b | 15078 | { |
6411280a AE |
15079 | struct bnx2x *bp = fp->bp; |
15080 | u32 offset = BAR_USTRORM_INTMEM; | |
abc5a021 | 15081 | |
6411280a AE |
15082 | if (IS_VF(bp)) |
15083 | return bnx2x_vf_ustorm_prods_offset(bp, fp); | |
15084 | else if (!CHIP_IS_E1x(bp)) | |
15085 | offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); | |
15086 | else | |
15087 | offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); | |
8d9ac297 | 15088 | |
6411280a | 15089 | return offset; |
8d9ac297 | 15090 | } |
381ac16b | 15091 | |
6411280a AE |
15092 | /* called only on E1H or E2. |
15093 | * When pretending to be PF, the pretend value is the function number 0...7 | |
15094 | * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID | |
15095 | * combination | |
15096 | */ | |
15097 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) | |
381ac16b | 15098 | { |
6411280a | 15099 | u32 pretend_reg; |
381ac16b | 15100 | |
23826850 | 15101 | if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) |
6411280a | 15102 | return -1; |
381ac16b | 15103 | |
6411280a AE |
15104 | /* get my own pretend register */ |
15105 | pretend_reg = bnx2x_get_pretend_reg(bp); | |
15106 | REG_WR(bp, pretend_reg, pretend_func_val); | |
15107 | REG_RD(bp, pretend_reg); | |
381ac16b AE |
15108 | return 0; |
15109 | } | |
eeed018c MK |
15110 | |
15111 | static void bnx2x_ptp_task(struct work_struct *work) | |
15112 | { | |
15113 | struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task); | |
15114 | int port = BP_PORT(bp); | |
15115 | u32 val_seq; | |
15116 | u64 timestamp, ns; | |
15117 | struct skb_shared_hwtstamps shhwtstamps; | |
3c91f25c GP |
15118 | bool bail = true; |
15119 | int i; | |
15120 | ||
15121 | /* FW may take a while to complete timestamping; try a bit and if it's | |
15122 | * still not complete, may indicate an error state - bail out then. | |
15123 | */ | |
15124 | for (i = 0; i < 10; i++) { | |
15125 | /* Read Tx timestamp registers */ | |
15126 | val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : | |
15127 | NIG_REG_P0_TLLH_PTP_BUF_SEQID); | |
15128 | if (val_seq & 0x10000) { | |
15129 | bail = false; | |
15130 | break; | |
15131 | } | |
15132 | msleep(1 << i); | |
15133 | } | |
eeed018c | 15134 | |
3c91f25c | 15135 | if (!bail) { |
eeed018c MK |
15136 | /* There is a valid timestamp value */ |
15137 | timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB : | |
15138 | NIG_REG_P0_TLLH_PTP_BUF_TS_MSB); | |
15139 | timestamp <<= 32; | |
15140 | timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB : | |
15141 | NIG_REG_P0_TLLH_PTP_BUF_TS_LSB); | |
15142 | /* Reset timestamp register to allow new timestamp */ | |
15143 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : | |
15144 | NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); | |
15145 | ns = timecounter_cyc2time(&bp->timecounter, timestamp); | |
15146 | ||
15147 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
15148 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
15149 | skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps); | |
eeed018c MK |
15150 | |
15151 | DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n", | |
15152 | timestamp, ns); | |
15153 | } else { | |
3c91f25c GP |
15154 | DP(BNX2X_MSG_PTP, |
15155 | "Tx timestamp is not recorded (register read=%u)\n", | |
15156 | val_seq); | |
15157 | bp->eth_stats.ptp_skip_tx_ts++; | |
eeed018c | 15158 | } |
3c91f25c GP |
15159 | |
15160 | dev_kfree_skb_any(bp->ptp_tx_skb); | |
15161 | bp->ptp_tx_skb = NULL; | |
eeed018c MK |
15162 | } |
15163 | ||
15164 | void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb) | |
15165 | { | |
15166 | int port = BP_PORT(bp); | |
15167 | u64 timestamp, ns; | |
15168 | ||
15169 | timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB : | |
15170 | NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB); | |
15171 | timestamp <<= 32; | |
15172 | timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB : | |
15173 | NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB); | |
15174 | ||
15175 | /* Reset timestamp register to allow new timestamp */ | |
15176 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : | |
15177 | NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); | |
15178 | ||
15179 | ns = timecounter_cyc2time(&bp->timecounter, timestamp); | |
15180 | ||
15181 | skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); | |
15182 | ||
15183 | DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n", | |
15184 | timestamp, ns); | |
15185 | } | |
15186 | ||
15187 | /* Read the PHC */ | |
a5a1d1c2 | 15188 | static u64 bnx2x_cyclecounter_read(const struct cyclecounter *cc) |
eeed018c MK |
15189 | { |
15190 | struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter); | |
15191 | int port = BP_PORT(bp); | |
15192 | u32 wb_data[2]; | |
15193 | u64 phc_cycles; | |
15194 | ||
15195 | REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 : | |
15196 | NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2); | |
15197 | phc_cycles = wb_data[1]; | |
15198 | phc_cycles = (phc_cycles << 32) + wb_data[0]; | |
15199 | ||
15200 | DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles); | |
15201 | ||
15202 | return phc_cycles; | |
15203 | } | |
15204 | ||
15205 | static void bnx2x_init_cyclecounter(struct bnx2x *bp) | |
15206 | { | |
15207 | memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter)); | |
15208 | bp->cyclecounter.read = bnx2x_cyclecounter_read; | |
f28ba401 | 15209 | bp->cyclecounter.mask = CYCLECOUNTER_MASK(64); |
a6e2846c | 15210 | bp->cyclecounter.shift = 0; |
eeed018c MK |
15211 | bp->cyclecounter.mult = 1; |
15212 | } | |
15213 | ||
15214 | static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp) | |
15215 | { | |
15216 | struct bnx2x_func_state_params func_params = {NULL}; | |
15217 | struct bnx2x_func_set_timesync_params *set_timesync_params = | |
15218 | &func_params.params.set_timesync; | |
15219 | ||
15220 | /* Prepare parameters for function state transitions */ | |
15221 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
15222 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
15223 | ||
15224 | func_params.f_obj = &bp->func_obj; | |
15225 | func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; | |
15226 | ||
15227 | /* Function parameters */ | |
15228 | set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET; | |
15229 | set_timesync_params->offset_cmd = TS_OFFSET_KEEP; | |
15230 | ||
15231 | return bnx2x_func_state_change(bp, &func_params); | |
15232 | } | |
15233 | ||
1444c301 | 15234 | static int bnx2x_enable_ptp_packets(struct bnx2x *bp) |
eeed018c MK |
15235 | { |
15236 | struct bnx2x_queue_state_params q_params; | |
15237 | int rc, i; | |
15238 | ||
15239 | /* send queue update ramrod to enable PTP packets */ | |
15240 | memset(&q_params, 0, sizeof(q_params)); | |
15241 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
15242 | q_params.cmd = BNX2X_Q_CMD_UPDATE; | |
15243 | __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, | |
15244 | &q_params.params.update.update_flags); | |
15245 | __set_bit(BNX2X_Q_UPDATE_PTP_PKTS, | |
15246 | &q_params.params.update.update_flags); | |
15247 | ||
15248 | /* send the ramrod on all the queues of the PF */ | |
15249 | for_each_eth_queue(bp, i) { | |
15250 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
15251 | ||
15252 | /* Set the appropriate Queue object */ | |
15253 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; | |
15254 | ||
15255 | /* Update the Queue state */ | |
15256 | rc = bnx2x_queue_state_change(bp, &q_params); | |
15257 | if (rc) { | |
15258 | BNX2X_ERR("Failed to enable PTP packets\n"); | |
15259 | return rc; | |
15260 | } | |
15261 | } | |
15262 | ||
15263 | return 0; | |
15264 | } | |
15265 | ||
00165c25 SRK |
15266 | #define BNX2X_P2P_DETECT_PARAM_MASK 0x5F5 |
15267 | #define BNX2X_P2P_DETECT_RULE_MASK 0x3DBB | |
15268 | #define BNX2X_PTP_TX_ON_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA) | |
15269 | #define BNX2X_PTP_TX_ON_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE) | |
15270 | #define BNX2X_PTP_V1_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EE) | |
15271 | #define BNX2X_PTP_V1_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FFE) | |
15272 | #define BNX2X_PTP_V2_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EA) | |
15273 | #define BNX2X_PTP_V2_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FEE) | |
15274 | #define BNX2X_PTP_V2_L2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6BF) | |
15275 | #define BNX2X_PTP_V2_L2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EFF) | |
15276 | #define BNX2X_PTP_V2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA) | |
15277 | #define BNX2X_PTP_V2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE) | |
b320532c | 15278 | |
eeed018c MK |
15279 | int bnx2x_configure_ptp_filters(struct bnx2x *bp) |
15280 | { | |
15281 | int port = BP_PORT(bp); | |
b320532c | 15282 | u32 param, rule; |
eeed018c MK |
15283 | int rc; |
15284 | ||
15285 | if (!bp->hwtstamp_ioctl_called) | |
15286 | return 0; | |
15287 | ||
b320532c SRK |
15288 | param = port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : |
15289 | NIG_REG_P0_TLLH_PTP_PARAM_MASK; | |
15290 | rule = port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : | |
15291 | NIG_REG_P0_TLLH_PTP_RULE_MASK; | |
eeed018c MK |
15292 | switch (bp->tx_type) { |
15293 | case HWTSTAMP_TX_ON: | |
15294 | bp->flags |= TX_TIMESTAMPING_EN; | |
b320532c SRK |
15295 | REG_WR(bp, param, BNX2X_PTP_TX_ON_PARAM_MASK); |
15296 | REG_WR(bp, rule, BNX2X_PTP_TX_ON_RULE_MASK); | |
eeed018c MK |
15297 | break; |
15298 | case HWTSTAMP_TX_ONESTEP_SYNC: | |
b6fd7b96 | 15299 | case HWTSTAMP_TX_ONESTEP_P2P: |
eeed018c MK |
15300 | BNX2X_ERR("One-step timestamping is not supported\n"); |
15301 | return -ERANGE; | |
15302 | } | |
15303 | ||
b320532c SRK |
15304 | param = port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : |
15305 | NIG_REG_P0_LLH_PTP_PARAM_MASK; | |
15306 | rule = port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
15307 | NIG_REG_P0_LLH_PTP_RULE_MASK; | |
eeed018c MK |
15308 | switch (bp->rx_filter) { |
15309 | case HWTSTAMP_FILTER_NONE: | |
15310 | break; | |
15311 | case HWTSTAMP_FILTER_ALL: | |
15312 | case HWTSTAMP_FILTER_SOME: | |
e3412575 | 15313 | case HWTSTAMP_FILTER_NTP_ALL: |
eeed018c MK |
15314 | bp->rx_filter = HWTSTAMP_FILTER_NONE; |
15315 | break; | |
15316 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
15317 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
15318 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
15319 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
15320 | /* Initialize PTP detection for UDP/IPv4 events */ | |
b320532c SRK |
15321 | REG_WR(bp, param, BNX2X_PTP_V1_L4_PARAM_MASK); |
15322 | REG_WR(bp, rule, BNX2X_PTP_V1_L4_RULE_MASK); | |
eeed018c MK |
15323 | break; |
15324 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
15325 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
15326 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
15327 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; | |
15328 | /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */ | |
b320532c SRK |
15329 | REG_WR(bp, param, BNX2X_PTP_V2_L4_PARAM_MASK); |
15330 | REG_WR(bp, rule, BNX2X_PTP_V2_L4_RULE_MASK); | |
eeed018c MK |
15331 | break; |
15332 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
15333 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
15334 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
15335 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; | |
15336 | /* Initialize PTP detection L2 events */ | |
b320532c SRK |
15337 | REG_WR(bp, param, BNX2X_PTP_V2_L2_PARAM_MASK); |
15338 | REG_WR(bp, rule, BNX2X_PTP_V2_L2_RULE_MASK); | |
eeed018c MK |
15339 | |
15340 | break; | |
15341 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
15342 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
15343 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
15344 | bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
15345 | /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */ | |
b320532c SRK |
15346 | REG_WR(bp, param, BNX2X_PTP_V2_PARAM_MASK); |
15347 | REG_WR(bp, rule, BNX2X_PTP_V2_RULE_MASK); | |
eeed018c MK |
15348 | break; |
15349 | } | |
15350 | ||
15351 | /* Indicate to FW that this PF expects recorded PTP packets */ | |
15352 | rc = bnx2x_enable_ptp_packets(bp); | |
15353 | if (rc) | |
15354 | return rc; | |
15355 | ||
15356 | /* Enable sending PTP packets to host */ | |
15357 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : | |
15358 | NIG_REG_P0_LLH_PTP_TO_HOST, 0x1); | |
15359 | ||
15360 | return 0; | |
15361 | } | |
15362 | ||
15363 | static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr) | |
15364 | { | |
15365 | struct hwtstamp_config config; | |
15366 | int rc; | |
15367 | ||
15368 | DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n"); | |
15369 | ||
15370 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
15371 | return -EFAULT; | |
15372 | ||
15373 | DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n", | |
15374 | config.tx_type, config.rx_filter); | |
15375 | ||
15376 | if (config.flags) { | |
15377 | BNX2X_ERR("config.flags is reserved for future use\n"); | |
15378 | return -EINVAL; | |
15379 | } | |
15380 | ||
f3a3f346 | 15381 | bp->hwtstamp_ioctl_called = true; |
eeed018c MK |
15382 | bp->tx_type = config.tx_type; |
15383 | bp->rx_filter = config.rx_filter; | |
15384 | ||
15385 | rc = bnx2x_configure_ptp_filters(bp); | |
15386 | if (rc) | |
15387 | return rc; | |
15388 | ||
15389 | config.rx_filter = bp->rx_filter; | |
15390 | ||
15391 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
15392 | -EFAULT : 0; | |
15393 | } | |
15394 | ||
bf27c353 | 15395 | /* Configures HW for PTP */ |
eeed018c MK |
15396 | static int bnx2x_configure_ptp(struct bnx2x *bp) |
15397 | { | |
15398 | int rc, port = BP_PORT(bp); | |
15399 | u32 wb_data[2]; | |
15400 | ||
15401 | /* Reset PTP event detection rules - will be configured in the IOCTL */ | |
15402 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : | |
15403 | NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); | |
15404 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : | |
15405 | NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); | |
15406 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : | |
15407 | NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); | |
15408 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : | |
15409 | NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); | |
15410 | ||
15411 | /* Disable PTP packets to host - will be configured in the IOCTL*/ | |
15412 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : | |
15413 | NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); | |
15414 | ||
15415 | /* Enable the PTP feature */ | |
15416 | REG_WR(bp, port ? NIG_REG_P1_PTP_EN : | |
15417 | NIG_REG_P0_PTP_EN, 0x3F); | |
15418 | ||
15419 | /* Enable the free-running counter */ | |
15420 | wb_data[0] = 0; | |
15421 | wb_data[1] = 0; | |
15422 | REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2); | |
15423 | ||
15424 | /* Reset drift register (offset register is not reset) */ | |
15425 | rc = bnx2x_send_reset_timesync_ramrod(bp); | |
15426 | if (rc) { | |
15427 | BNX2X_ERR("Failed to reset PHC drift register\n"); | |
15428 | return -EFAULT; | |
15429 | } | |
15430 | ||
15431 | /* Reset possibly old timestamps */ | |
15432 | REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : | |
15433 | NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); | |
15434 | REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : | |
15435 | NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); | |
15436 | ||
15437 | return 0; | |
15438 | } | |
15439 | ||
15440 | /* Called during load, to initialize PTP-related stuff */ | |
15441 | void bnx2x_init_ptp(struct bnx2x *bp) | |
15442 | { | |
15443 | int rc; | |
15444 | ||
15445 | /* Configure PTP in HW */ | |
15446 | rc = bnx2x_configure_ptp(bp); | |
15447 | if (rc) { | |
15448 | BNX2X_ERR("Stopping PTP initialization\n"); | |
15449 | return; | |
15450 | } | |
15451 | ||
15452 | /* Init work queue for Tx timestamping */ | |
15453 | INIT_WORK(&bp->ptp_task, bnx2x_ptp_task); | |
15454 | ||
15455 | /* Init cyclecounter and timecounter. This is done only in the first | |
15456 | * load. If done in every load, PTP application will fail when doing | |
15457 | * unload / load (e.g. MTU change) while it is running. | |
15458 | */ | |
15459 | if (!bp->timecounter_init_done) { | |
15460 | bnx2x_init_cyclecounter(bp); | |
15461 | timecounter_init(&bp->timecounter, &bp->cyclecounter, | |
15462 | ktime_to_ns(ktime_get_real())); | |
f3a3f346 | 15463 | bp->timecounter_init_done = true; |
eeed018c MK |
15464 | } |
15465 | ||
15466 | DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n"); | |
15467 | } |