]>
Commit | Line | Data |
---|---|---|
619c5cb6 VZ |
1 | /* bnx2x_sp.h: Broadcom Everest network driver. |
2 | * | |
247fa82b | 3 | * Copyright (c) 2011-2013 Broadcom Corporation |
619c5cb6 VZ |
4 | * |
5 | * Unless you and Broadcom execute a separate written software license | |
6 | * agreement governing use of this software, this software is licensed to you | |
7 | * under the terms of the GNU General Public License version 2, available | |
8 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
9 | * | |
10 | * Notwithstanding the above, under no circumstances may you combine this | |
11 | * software in any way with any other Broadcom software provided under a | |
12 | * license other than the GPL, without Broadcom's express prior written | |
13 | * consent. | |
14 | * | |
08f6dd89 | 15 | * Maintained by: Ariel Elior <ariel.elior@qlogic.com> |
619c5cb6 VZ |
16 | * Written by: Vladislav Zolotarov |
17 | * | |
18 | */ | |
19 | #ifndef BNX2X_SP_VERBS | |
20 | #define BNX2X_SP_VERBS | |
21 | ||
22 | struct bnx2x; | |
23 | struct eth_context; | |
24 | ||
25 | /* Bits representing general command's configuration */ | |
26 | enum { | |
27 | RAMROD_TX, | |
28 | RAMROD_RX, | |
29 | /* Wait until all pending commands complete */ | |
30 | RAMROD_COMP_WAIT, | |
31 | /* Don't send a ramrod, only update a registry */ | |
32 | RAMROD_DRV_CLR_ONLY, | |
33 | /* Configure HW according to the current object state */ | |
34 | RAMROD_RESTORE, | |
35 | /* Execute the next command now */ | |
36 | RAMROD_EXEC, | |
16a5fd92 | 37 | /* Don't add a new command and continue execution of postponed |
619c5cb6 VZ |
38 | * commands. If not set a new command will be added to the |
39 | * pending commands list. | |
40 | */ | |
41 | RAMROD_CONT, | |
55c11941 MS |
42 | /* If there is another pending ramrod, wait until it finishes and |
43 | * re-try to submit this one. This flag can be set only in sleepable | |
44 | * context, and should not be set from the context that completes the | |
45 | * ramrods as deadlock will occur. | |
46 | */ | |
47 | RAMROD_RETRY, | |
619c5cb6 VZ |
48 | }; |
49 | ||
50 | typedef enum { | |
51 | BNX2X_OBJ_TYPE_RX, | |
52 | BNX2X_OBJ_TYPE_TX, | |
53 | BNX2X_OBJ_TYPE_RX_TX, | |
54 | } bnx2x_obj_type; | |
55 | ||
2de67439 | 56 | /* Public slow path states */ |
619c5cb6 VZ |
57 | enum { |
58 | BNX2X_FILTER_MAC_PENDING, | |
59 | BNX2X_FILTER_VLAN_PENDING, | |
60 | BNX2X_FILTER_VLAN_MAC_PENDING, | |
61 | BNX2X_FILTER_RX_MODE_PENDING, | |
62 | BNX2X_FILTER_RX_MODE_SCHED, | |
63 | BNX2X_FILTER_ISCSI_ETH_START_SCHED, | |
64 | BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
65 | BNX2X_FILTER_FCOE_ETH_START_SCHED, | |
66 | BNX2X_FILTER_FCOE_ETH_STOP_SCHED, | |
67 | BNX2X_FILTER_MCAST_PENDING, | |
68 | BNX2X_FILTER_MCAST_SCHED, | |
69 | BNX2X_FILTER_RSS_CONF_PENDING, | |
a3348722 BW |
70 | BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, |
71 | BNX2X_AFEX_PENDING_VIFSET_MCP_ACK | |
619c5cb6 VZ |
72 | }; |
73 | ||
74 | struct bnx2x_raw_obj { | |
75 | u8 func_id; | |
76 | ||
77 | /* Queue params */ | |
78 | u8 cl_id; | |
79 | u32 cid; | |
80 | ||
81 | /* Ramrod data buffer params */ | |
82 | void *rdata; | |
83 | dma_addr_t rdata_mapping; | |
84 | ||
85 | /* Ramrod state params */ | |
86 | int state; /* "ramrod is pending" state bit */ | |
87 | unsigned long *pstate; /* pointer to state buffer */ | |
88 | ||
89 | bnx2x_obj_type obj_type; | |
90 | ||
91 | int (*wait_comp)(struct bnx2x *bp, | |
92 | struct bnx2x_raw_obj *o); | |
93 | ||
94 | bool (*check_pending)(struct bnx2x_raw_obj *o); | |
95 | void (*clear_pending)(struct bnx2x_raw_obj *o); | |
96 | void (*set_pending)(struct bnx2x_raw_obj *o); | |
97 | }; | |
98 | ||
99 | /************************* VLAN-MAC commands related parameters ***************/ | |
100 | struct bnx2x_mac_ramrod_data { | |
101 | u8 mac[ETH_ALEN]; | |
91226790 | 102 | u8 is_inner_mac; |
619c5cb6 VZ |
103 | }; |
104 | ||
105 | struct bnx2x_vlan_ramrod_data { | |
106 | u16 vlan; | |
107 | }; | |
108 | ||
109 | struct bnx2x_vlan_mac_ramrod_data { | |
110 | u8 mac[ETH_ALEN]; | |
91226790 | 111 | u8 is_inner_mac; |
619c5cb6 VZ |
112 | u16 vlan; |
113 | }; | |
114 | ||
115 | union bnx2x_classification_ramrod_data { | |
116 | struct bnx2x_mac_ramrod_data mac; | |
117 | struct bnx2x_vlan_ramrod_data vlan; | |
118 | struct bnx2x_vlan_mac_ramrod_data vlan_mac; | |
119 | }; | |
120 | ||
121 | /* VLAN_MAC commands */ | |
122 | enum bnx2x_vlan_mac_cmd { | |
123 | BNX2X_VLAN_MAC_ADD, | |
124 | BNX2X_VLAN_MAC_DEL, | |
125 | BNX2X_VLAN_MAC_MOVE, | |
126 | }; | |
127 | ||
128 | struct bnx2x_vlan_mac_data { | |
129 | /* Requested command: BNX2X_VLAN_MAC_XX */ | |
130 | enum bnx2x_vlan_mac_cmd cmd; | |
16a5fd92 | 131 | /* used to contain the data related vlan_mac_flags bits from |
619c5cb6 VZ |
132 | * ramrod parameters. |
133 | */ | |
134 | unsigned long vlan_mac_flags; | |
135 | ||
136 | /* Needed for MOVE command */ | |
137 | struct bnx2x_vlan_mac_obj *target_obj; | |
138 | ||
139 | union bnx2x_classification_ramrod_data u; | |
140 | }; | |
141 | ||
142 | /*************************** Exe Queue obj ************************************/ | |
143 | union bnx2x_exe_queue_cmd_data { | |
144 | struct bnx2x_vlan_mac_data vlan_mac; | |
145 | ||
146 | struct { | |
147 | /* TODO */ | |
148 | } mcast; | |
149 | }; | |
150 | ||
151 | struct bnx2x_exeq_elem { | |
152 | struct list_head link; | |
153 | ||
154 | /* Length of this element in the exe_chunk. */ | |
155 | int cmd_len; | |
156 | ||
157 | union bnx2x_exe_queue_cmd_data cmd_data; | |
158 | }; | |
159 | ||
160 | union bnx2x_qable_obj; | |
161 | ||
162 | union bnx2x_exeq_comp_elem { | |
163 | union event_ring_elem *elem; | |
164 | }; | |
165 | ||
166 | struct bnx2x_exe_queue_obj; | |
167 | ||
168 | typedef int (*exe_q_validate)(struct bnx2x *bp, | |
169 | union bnx2x_qable_obj *o, | |
170 | struct bnx2x_exeq_elem *elem); | |
171 | ||
460a25cd YM |
172 | typedef int (*exe_q_remove)(struct bnx2x *bp, |
173 | union bnx2x_qable_obj *o, | |
174 | struct bnx2x_exeq_elem *elem); | |
175 | ||
1aa8b471 BH |
176 | /* Return positive if entry was optimized, 0 - if not, negative |
177 | * in case of an error. | |
619c5cb6 VZ |
178 | */ |
179 | typedef int (*exe_q_optimize)(struct bnx2x *bp, | |
180 | union bnx2x_qable_obj *o, | |
181 | struct bnx2x_exeq_elem *elem); | |
182 | typedef int (*exe_q_execute)(struct bnx2x *bp, | |
183 | union bnx2x_qable_obj *o, | |
184 | struct list_head *exe_chunk, | |
185 | unsigned long *ramrod_flags); | |
186 | typedef struct bnx2x_exeq_elem * | |
187 | (*exe_q_get)(struct bnx2x_exe_queue_obj *o, | |
188 | struct bnx2x_exeq_elem *elem); | |
189 | ||
190 | struct bnx2x_exe_queue_obj { | |
16a5fd92 | 191 | /* Commands pending for an execution. */ |
619c5cb6 VZ |
192 | struct list_head exe_queue; |
193 | ||
16a5fd92 | 194 | /* Commands pending for an completion. */ |
619c5cb6 VZ |
195 | struct list_head pending_comp; |
196 | ||
197 | spinlock_t lock; | |
198 | ||
199 | /* Maximum length of commands' list for one execution */ | |
200 | int exe_chunk_len; | |
201 | ||
202 | union bnx2x_qable_obj *owner; | |
203 | ||
204 | /****** Virtual functions ******/ | |
205 | /** | |
206 | * Called before commands execution for commands that are really | |
207 | * going to be executed (after 'optimize'). | |
208 | * | |
209 | * Must run under exe_queue->lock | |
210 | */ | |
211 | exe_q_validate validate; | |
212 | ||
460a25cd YM |
213 | /** |
214 | * Called before removing pending commands, cleaning allocated | |
215 | * resources (e.g., credits from validate) | |
216 | */ | |
217 | exe_q_remove remove; | |
619c5cb6 VZ |
218 | |
219 | /** | |
220 | * This will try to cancel the current pending commands list | |
221 | * considering the new command. | |
222 | * | |
460a25cd YM |
223 | * Returns the number of optimized commands or a negative error code |
224 | * | |
619c5cb6 VZ |
225 | * Must run under exe_queue->lock |
226 | */ | |
227 | exe_q_optimize optimize; | |
228 | ||
229 | /** | |
230 | * Run the next commands chunk (owner specific). | |
231 | */ | |
232 | exe_q_execute execute; | |
233 | ||
234 | /** | |
235 | * Return the exe_queue element containing the specific command | |
236 | * if any. Otherwise return NULL. | |
237 | */ | |
238 | exe_q_get get; | |
239 | }; | |
240 | /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ | |
241 | /* | |
16a5fd92 | 242 | * Element in the VLAN_MAC registry list having all currently configured |
619c5cb6 VZ |
243 | * rules. |
244 | */ | |
245 | struct bnx2x_vlan_mac_registry_elem { | |
246 | struct list_head link; | |
247 | ||
16a5fd92 | 248 | /* Used to store the cam offset used for the mac/vlan/vlan-mac. |
619c5cb6 VZ |
249 | * Relevant for 57710 and 57711 only. VLANs and MACs share the |
250 | * same CAM for these chips. | |
251 | */ | |
252 | int cam_offset; | |
253 | ||
254 | /* Needed for DEL and RESTORE flows */ | |
255 | unsigned long vlan_mac_flags; | |
256 | ||
257 | union bnx2x_classification_ramrod_data u; | |
258 | }; | |
259 | ||
260 | /* Bits representing VLAN_MAC commands specific flags */ | |
261 | enum { | |
262 | BNX2X_UC_LIST_MAC, | |
263 | BNX2X_ETH_MAC, | |
264 | BNX2X_ISCSI_ETH_MAC, | |
265 | BNX2X_NETQ_ETH_MAC, | |
266 | BNX2X_DONT_CONSUME_CAM_CREDIT, | |
267 | BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, | |
268 | }; | |
e8379c79 YM |
269 | /* When looking for matching filters, some flags are not interesting */ |
270 | #define BNX2X_VLAN_MAC_CMP_MASK (1 << BNX2X_UC_LIST_MAC | \ | |
271 | 1 << BNX2X_ETH_MAC | \ | |
272 | 1 << BNX2X_ISCSI_ETH_MAC | \ | |
273 | 1 << BNX2X_NETQ_ETH_MAC) | |
274 | #define BNX2X_VLAN_MAC_CMP_FLAGS(flags) \ | |
275 | ((flags) & BNX2X_VLAN_MAC_CMP_MASK) | |
619c5cb6 VZ |
276 | |
277 | struct bnx2x_vlan_mac_ramrod_params { | |
278 | /* Object to run the command from */ | |
279 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
280 | ||
281 | /* General command flags: COMP_WAIT, etc. */ | |
282 | unsigned long ramrod_flags; | |
283 | ||
284 | /* Command specific configuration request */ | |
285 | struct bnx2x_vlan_mac_data user_req; | |
286 | }; | |
287 | ||
288 | struct bnx2x_vlan_mac_obj { | |
289 | struct bnx2x_raw_obj raw; | |
290 | ||
291 | /* Bookkeeping list: will prevent the addition of already existing | |
292 | * entries. | |
293 | */ | |
294 | struct list_head head; | |
8b09be5f YM |
295 | /* Implement a simple reader/writer lock on the head list. |
296 | * all these fields should only be accessed under the exe_queue lock | |
297 | */ | |
298 | u8 head_reader; /* Num. of readers accessing head list */ | |
299 | bool head_exe_request; /* Pending execution request. */ | |
300 | unsigned long saved_ramrod_flags; /* Ramrods of pending execution */ | |
619c5cb6 VZ |
301 | |
302 | /* TODO: Add it's initialization in the init functions */ | |
303 | struct bnx2x_exe_queue_obj exe_queue; | |
304 | ||
305 | /* MACs credit pool */ | |
306 | struct bnx2x_credit_pool_obj *macs_pool; | |
307 | ||
308 | /* VLANs credit pool */ | |
309 | struct bnx2x_credit_pool_obj *vlans_pool; | |
310 | ||
311 | /* RAMROD command to be used */ | |
312 | int ramrod_cmd; | |
313 | ||
ed5162a0 AE |
314 | /* copy first n elements onto preallocated buffer |
315 | * | |
316 | * @param n number of elements to get | |
317 | * @param buf buffer preallocated by caller into which elements | |
318 | * will be copied. Note elements are 4-byte aligned | |
16a5fd92 | 319 | * so buffer size must be able to accommodate the |
ed5162a0 AE |
320 | * aligned elements. |
321 | * | |
322 | * @return number of copied bytes | |
323 | */ | |
3ec9f9ca AE |
324 | int (*get_n_elements)(struct bnx2x *bp, |
325 | struct bnx2x_vlan_mac_obj *o, int n, u8 *base, | |
326 | u8 stride, u8 size); | |
ed5162a0 | 327 | |
619c5cb6 VZ |
328 | /** |
329 | * Checks if ADD-ramrod with the given params may be performed. | |
330 | * | |
331 | * @return zero if the element may be added | |
332 | */ | |
333 | ||
51c1a580 MS |
334 | int (*check_add)(struct bnx2x *bp, |
335 | struct bnx2x_vlan_mac_obj *o, | |
619c5cb6 VZ |
336 | union bnx2x_classification_ramrod_data *data); |
337 | ||
338 | /** | |
339 | * Checks if DEL-ramrod with the given params may be performed. | |
340 | * | |
341 | * @return true if the element may be deleted | |
342 | */ | |
343 | struct bnx2x_vlan_mac_registry_elem * | |
51c1a580 MS |
344 | (*check_del)(struct bnx2x *bp, |
345 | struct bnx2x_vlan_mac_obj *o, | |
619c5cb6 VZ |
346 | union bnx2x_classification_ramrod_data *data); |
347 | ||
348 | /** | |
349 | * Checks if DEL-ramrod with the given params may be performed. | |
350 | * | |
351 | * @return true if the element may be deleted | |
352 | */ | |
51c1a580 MS |
353 | bool (*check_move)(struct bnx2x *bp, |
354 | struct bnx2x_vlan_mac_obj *src_o, | |
619c5cb6 VZ |
355 | struct bnx2x_vlan_mac_obj *dst_o, |
356 | union bnx2x_classification_ramrod_data *data); | |
357 | ||
358 | /** | |
359 | * Update the relevant credit object(s) (consume/return | |
360 | * correspondingly). | |
361 | */ | |
362 | bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); | |
363 | bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); | |
364 | bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); | |
365 | bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); | |
366 | ||
367 | /** | |
368 | * Configures one rule in the ramrod data buffer. | |
369 | */ | |
370 | void (*set_one_rule)(struct bnx2x *bp, | |
371 | struct bnx2x_vlan_mac_obj *o, | |
372 | struct bnx2x_exeq_elem *elem, int rule_idx, | |
373 | int cam_offset); | |
374 | ||
375 | /** | |
376 | * Delete all configured elements having the given | |
377 | * vlan_mac_flags specification. Assumes no pending for | |
378 | * execution commands. Will schedule all all currently | |
379 | * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags | |
380 | * specification for deletion and will use the given | |
381 | * ramrod_flags for the last DEL operation. | |
382 | * | |
383 | * @param bp | |
384 | * @param o | |
385 | * @param ramrod_flags RAMROD_XX flags | |
386 | * | |
387 | * @return 0 if the last operation has completed successfully | |
388 | * and there are no more elements left, positive value | |
389 | * if there are pending for completion commands, | |
390 | * negative value in case of failure. | |
391 | */ | |
392 | int (*delete_all)(struct bnx2x *bp, | |
393 | struct bnx2x_vlan_mac_obj *o, | |
394 | unsigned long *vlan_mac_flags, | |
395 | unsigned long *ramrod_flags); | |
396 | ||
397 | /** | |
398 | * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously | |
399 | * configured elements list. | |
400 | * | |
401 | * @param bp | |
402 | * @param p Command parameters (RAMROD_COMP_WAIT bit in | |
403 | * ramrod_flags is only taken into an account) | |
16a5fd92 | 404 | * @param ppos a pointer to the cookie that should be given back in the |
619c5cb6 VZ |
405 | * next call to make function handle the next element. If |
406 | * *ppos is set to NULL it will restart the iterator. | |
407 | * If returned *ppos == NULL this means that the last | |
408 | * element has been handled. | |
409 | * | |
410 | * @return int | |
411 | */ | |
412 | int (*restore)(struct bnx2x *bp, | |
413 | struct bnx2x_vlan_mac_ramrod_params *p, | |
414 | struct bnx2x_vlan_mac_registry_elem **ppos); | |
415 | ||
416 | /** | |
16a5fd92 | 417 | * Should be called on a completion arrival. |
619c5cb6 VZ |
418 | * |
419 | * @param bp | |
420 | * @param o | |
421 | * @param cqe Completion element we are handling | |
422 | * @param ramrod_flags if RAMROD_CONT is set the next bulk of | |
423 | * pending commands will be executed. | |
424 | * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE | |
425 | * may also be set if needed. | |
426 | * | |
427 | * @return 0 if there are neither pending nor waiting for | |
428 | * completion commands. Positive value if there are | |
429 | * pending for execution or for completion commands. | |
430 | * Negative value in case of an error (including an | |
431 | * error in the cqe). | |
432 | */ | |
433 | int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, | |
434 | union event_ring_elem *cqe, | |
435 | unsigned long *ramrod_flags); | |
436 | ||
437 | /** | |
438 | * Wait for completion of all commands. Don't schedule new ones, | |
439 | * just wait. It assumes that the completion code will schedule | |
440 | * for new commands. | |
441 | */ | |
442 | int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); | |
443 | }; | |
444 | ||
0a52fd01 YM |
445 | enum { |
446 | BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, | |
447 | BNX2X_LLH_CAM_ETH_LINE, | |
448 | BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 | |
449 | }; | |
450 | ||
619c5cb6 VZ |
451 | /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ |
452 | ||
16a5fd92 | 453 | /* RX_MODE ramrod special flags: set in rx_mode_flags field in |
619c5cb6 VZ |
454 | * a bnx2x_rx_mode_ramrod_params. |
455 | */ | |
456 | enum { | |
457 | BNX2X_RX_MODE_FCOE_ETH, | |
458 | BNX2X_RX_MODE_ISCSI_ETH, | |
459 | }; | |
460 | ||
461 | enum { | |
462 | BNX2X_ACCEPT_UNICAST, | |
463 | BNX2X_ACCEPT_MULTICAST, | |
464 | BNX2X_ACCEPT_ALL_UNICAST, | |
465 | BNX2X_ACCEPT_ALL_MULTICAST, | |
466 | BNX2X_ACCEPT_BROADCAST, | |
467 | BNX2X_ACCEPT_UNMATCHED, | |
468 | BNX2X_ACCEPT_ANY_VLAN | |
469 | }; | |
470 | ||
471 | struct bnx2x_rx_mode_ramrod_params { | |
472 | struct bnx2x_rx_mode_obj *rx_mode_obj; | |
473 | unsigned long *pstate; | |
474 | int state; | |
475 | u8 cl_id; | |
476 | u32 cid; | |
477 | u8 func_id; | |
478 | unsigned long ramrod_flags; | |
479 | unsigned long rx_mode_flags; | |
480 | ||
16a5fd92 | 481 | /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to |
619c5cb6 VZ |
482 | * a tstorm_eth_mac_filter_config (e1x). |
483 | */ | |
484 | void *rdata; | |
485 | dma_addr_t rdata_mapping; | |
486 | ||
487 | /* Rx mode settings */ | |
488 | unsigned long rx_accept_flags; | |
489 | ||
490 | /* internal switching settings */ | |
491 | unsigned long tx_accept_flags; | |
492 | }; | |
493 | ||
494 | struct bnx2x_rx_mode_obj { | |
495 | int (*config_rx_mode)(struct bnx2x *bp, | |
496 | struct bnx2x_rx_mode_ramrod_params *p); | |
497 | ||
498 | int (*wait_comp)(struct bnx2x *bp, | |
499 | struct bnx2x_rx_mode_ramrod_params *p); | |
500 | }; | |
501 | ||
502 | /********************** Set multicast group ***********************************/ | |
503 | ||
504 | struct bnx2x_mcast_list_elem { | |
505 | struct list_head link; | |
506 | u8 *mac; | |
507 | }; | |
508 | ||
509 | union bnx2x_mcast_config_data { | |
510 | u8 *mac; | |
511 | u8 bin; /* used in a RESTORE flow */ | |
512 | }; | |
513 | ||
514 | struct bnx2x_mcast_ramrod_params { | |
515 | struct bnx2x_mcast_obj *mcast_obj; | |
516 | ||
517 | /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ | |
518 | unsigned long ramrod_flags; | |
519 | ||
520 | struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ | |
521 | /** TODO: | |
522 | * - rename it to macs_num. | |
523 | * - Add a new command type for handling pending commands | |
524 | * (remove "zero semantics"). | |
525 | * | |
526 | * Length of mcast_list. If zero and ADD_CONT command - post | |
527 | * pending commands. | |
528 | */ | |
529 | int mcast_list_len; | |
530 | }; | |
531 | ||
86564c3f | 532 | enum bnx2x_mcast_cmd { |
619c5cb6 VZ |
533 | BNX2X_MCAST_CMD_ADD, |
534 | BNX2X_MCAST_CMD_CONT, | |
535 | BNX2X_MCAST_CMD_DEL, | |
536 | BNX2X_MCAST_CMD_RESTORE, | |
537 | }; | |
538 | ||
539 | struct bnx2x_mcast_obj { | |
540 | struct bnx2x_raw_obj raw; | |
541 | ||
542 | union { | |
543 | struct { | |
544 | #define BNX2X_MCAST_BINS_NUM 256 | |
545 | #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) | |
546 | u64 vec[BNX2X_MCAST_VEC_SZ]; | |
547 | ||
548 | /** Number of BINs to clear. Should be updated | |
549 | * immediately when a command arrives in order to | |
550 | * properly create DEL commands. | |
551 | */ | |
552 | int num_bins_set; | |
553 | } aprox_match; | |
554 | ||
555 | struct { | |
556 | struct list_head macs; | |
557 | int num_macs_set; | |
558 | } exact_match; | |
559 | } registry; | |
560 | ||
561 | /* Pending commands */ | |
562 | struct list_head pending_cmds_head; | |
563 | ||
564 | /* A state that is set in raw.pstate, when there are pending commands */ | |
565 | int sched_state; | |
566 | ||
567 | /* Maximal number of mcast MACs configured in one command */ | |
568 | int max_cmd_len; | |
569 | ||
570 | /* Total number of currently pending MACs to configure: both | |
571 | * in the pending commands list and in the current command. | |
572 | */ | |
573 | int total_pending_num; | |
574 | ||
575 | u8 engine_id; | |
576 | ||
577 | /** | |
578 | * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) | |
579 | */ | |
580 | int (*config_mcast)(struct bnx2x *bp, | |
86564c3f YM |
581 | struct bnx2x_mcast_ramrod_params *p, |
582 | enum bnx2x_mcast_cmd cmd); | |
619c5cb6 VZ |
583 | |
584 | /** | |
585 | * Fills the ramrod data during the RESTORE flow. | |
586 | * | |
587 | * @param bp | |
588 | * @param o | |
589 | * @param start_idx Registry index to start from | |
590 | * @param rdata_idx Index in the ramrod data to start from | |
591 | * | |
592 | * @return -1 if we handled the whole registry or index of the last | |
593 | * handled registry element. | |
594 | */ | |
595 | int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, | |
596 | int start_bin, int *rdata_idx); | |
597 | ||
598 | int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, | |
86564c3f YM |
599 | struct bnx2x_mcast_ramrod_params *p, |
600 | enum bnx2x_mcast_cmd cmd); | |
619c5cb6 VZ |
601 | |
602 | void (*set_one_rule)(struct bnx2x *bp, | |
603 | struct bnx2x_mcast_obj *o, int idx, | |
86564c3f YM |
604 | union bnx2x_mcast_config_data *cfg_data, |
605 | enum bnx2x_mcast_cmd cmd); | |
619c5cb6 VZ |
606 | |
607 | /** Checks if there are more mcast MACs to be set or a previous | |
608 | * command is still pending. | |
609 | */ | |
610 | bool (*check_pending)(struct bnx2x_mcast_obj *o); | |
611 | ||
612 | /** | |
613 | * Set/Clear/Check SCHEDULED state of the object | |
614 | */ | |
615 | void (*set_sched)(struct bnx2x_mcast_obj *o); | |
616 | void (*clear_sched)(struct bnx2x_mcast_obj *o); | |
617 | bool (*check_sched)(struct bnx2x_mcast_obj *o); | |
618 | ||
619 | /* Wait until all pending commands complete */ | |
620 | int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); | |
621 | ||
622 | /** | |
623 | * Handle the internal object counters needed for proper | |
624 | * commands handling. Checks that the provided parameters are | |
625 | * feasible. | |
626 | */ | |
627 | int (*validate)(struct bnx2x *bp, | |
86564c3f YM |
628 | struct bnx2x_mcast_ramrod_params *p, |
629 | enum bnx2x_mcast_cmd cmd); | |
619c5cb6 VZ |
630 | |
631 | /** | |
632 | * Restore the values of internal counters in case of a failure. | |
633 | */ | |
634 | void (*revert)(struct bnx2x *bp, | |
635 | struct bnx2x_mcast_ramrod_params *p, | |
636 | int old_num_bins); | |
637 | ||
638 | int (*get_registry_size)(struct bnx2x_mcast_obj *o); | |
639 | void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); | |
640 | }; | |
641 | ||
642 | /*************************** Credit handling **********************************/ | |
643 | struct bnx2x_credit_pool_obj { | |
644 | ||
645 | /* Current amount of credit in the pool */ | |
646 | atomic_t credit; | |
647 | ||
648 | /* Maximum allowed credit. put() will check against it. */ | |
649 | int pool_sz; | |
650 | ||
16a5fd92 | 651 | /* Allocate a pool table statically. |
619c5cb6 | 652 | * |
16a5fd92 | 653 | * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) |
619c5cb6 | 654 | * |
16a5fd92 | 655 | * The set bit in the table will mean that the entry is available. |
619c5cb6 VZ |
656 | */ |
657 | #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) | |
658 | u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; | |
659 | ||
660 | /* Base pool offset (initialized differently */ | |
661 | int base_pool_offset; | |
662 | ||
663 | /** | |
664 | * Get the next free pool entry. | |
665 | * | |
666 | * @return true if there was a free entry in the pool | |
667 | */ | |
668 | bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); | |
669 | ||
670 | /** | |
671 | * Return the entry back to the pool. | |
672 | * | |
673 | * @return true if entry is legal and has been successfully | |
674 | * returned to the pool. | |
675 | */ | |
676 | bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); | |
677 | ||
678 | /** | |
679 | * Get the requested amount of credit from the pool. | |
680 | * | |
681 | * @param cnt Amount of requested credit | |
682 | * @return true if the operation is successful | |
683 | */ | |
684 | bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); | |
685 | ||
686 | /** | |
687 | * Returns the credit to the pool. | |
688 | * | |
689 | * @param cnt Amount of credit to return | |
690 | * @return true if the operation is successful | |
691 | */ | |
692 | bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); | |
693 | ||
694 | /** | |
695 | * Reads the current amount of credit. | |
696 | */ | |
697 | int (*check)(struct bnx2x_credit_pool_obj *o); | |
698 | }; | |
699 | ||
700 | /*************************** RSS configuration ********************************/ | |
701 | enum { | |
702 | /* RSS_MODE bits are mutually exclusive */ | |
703 | BNX2X_RSS_MODE_DISABLED, | |
704 | BNX2X_RSS_MODE_REGULAR, | |
619c5cb6 VZ |
705 | |
706 | BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ | |
707 | ||
708 | BNX2X_RSS_IPV4, | |
709 | BNX2X_RSS_IPV4_TCP, | |
5d317c6a | 710 | BNX2X_RSS_IPV4_UDP, |
619c5cb6 VZ |
711 | BNX2X_RSS_IPV6, |
712 | BNX2X_RSS_IPV6_TCP, | |
5d317c6a | 713 | BNX2X_RSS_IPV6_UDP, |
619c5cb6 VZ |
714 | }; |
715 | ||
716 | struct bnx2x_config_rss_params { | |
717 | struct bnx2x_rss_config_obj *rss_obj; | |
718 | ||
719 | /* may have RAMROD_COMP_WAIT set only */ | |
720 | unsigned long ramrod_flags; | |
721 | ||
722 | /* BNX2X_RSS_X bits */ | |
723 | unsigned long rss_flags; | |
724 | ||
725 | /* Number hash bits to take into an account */ | |
726 | u8 rss_result_mask; | |
727 | ||
728 | /* Indirection table */ | |
729 | u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; | |
730 | ||
731 | /* RSS hash values */ | |
732 | u32 rss_key[10]; | |
733 | ||
734 | /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ | |
735 | u16 toe_rss_bitmap; | |
736 | }; | |
737 | ||
738 | struct bnx2x_rss_config_obj { | |
739 | struct bnx2x_raw_obj raw; | |
740 | ||
741 | /* RSS engine to use */ | |
742 | u8 engine_id; | |
743 | ||
744 | /* Last configured indirection table */ | |
745 | u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; | |
746 | ||
5d317c6a MS |
747 | /* flags for enabling 4-tupple hash on UDP */ |
748 | u8 udp_rss_v4; | |
749 | u8 udp_rss_v6; | |
750 | ||
619c5cb6 VZ |
751 | int (*config_rss)(struct bnx2x *bp, |
752 | struct bnx2x_config_rss_params *p); | |
753 | }; | |
754 | ||
755 | /*********************** Queue state update ***********************************/ | |
756 | ||
757 | /* UPDATE command options */ | |
758 | enum { | |
759 | BNX2X_Q_UPDATE_IN_VLAN_REM, | |
760 | BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, | |
761 | BNX2X_Q_UPDATE_OUT_VLAN_REM, | |
762 | BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, | |
763 | BNX2X_Q_UPDATE_ANTI_SPOOF, | |
764 | BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, | |
765 | BNX2X_Q_UPDATE_ACTIVATE, | |
766 | BNX2X_Q_UPDATE_ACTIVATE_CHNG, | |
767 | BNX2X_Q_UPDATE_DEF_VLAN_EN, | |
768 | BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, | |
769 | BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | |
c14db202 YM |
770 | BNX2X_Q_UPDATE_SILENT_VLAN_REM, |
771 | BNX2X_Q_UPDATE_TX_SWITCHING_CHNG, | |
772 | BNX2X_Q_UPDATE_TX_SWITCHING | |
619c5cb6 VZ |
773 | }; |
774 | ||
775 | /* Allowed Queue states */ | |
776 | enum bnx2x_q_state { | |
777 | BNX2X_Q_STATE_RESET, | |
778 | BNX2X_Q_STATE_INITIALIZED, | |
779 | BNX2X_Q_STATE_ACTIVE, | |
6383c0b3 AE |
780 | BNX2X_Q_STATE_MULTI_COS, |
781 | BNX2X_Q_STATE_MCOS_TERMINATED, | |
619c5cb6 VZ |
782 | BNX2X_Q_STATE_INACTIVE, |
783 | BNX2X_Q_STATE_STOPPED, | |
784 | BNX2X_Q_STATE_TERMINATED, | |
785 | BNX2X_Q_STATE_FLRED, | |
786 | BNX2X_Q_STATE_MAX, | |
787 | }; | |
788 | ||
67c431a5 AE |
789 | /* Allowed Queue states */ |
790 | enum bnx2x_q_logical_state { | |
791 | BNX2X_Q_LOGICAL_STATE_ACTIVE, | |
792 | BNX2X_Q_LOGICAL_STATE_STOPPED, | |
793 | }; | |
794 | ||
619c5cb6 VZ |
795 | /* Allowed commands */ |
796 | enum bnx2x_queue_cmd { | |
797 | BNX2X_Q_CMD_INIT, | |
798 | BNX2X_Q_CMD_SETUP, | |
6383c0b3 | 799 | BNX2X_Q_CMD_SETUP_TX_ONLY, |
619c5cb6 VZ |
800 | BNX2X_Q_CMD_DEACTIVATE, |
801 | BNX2X_Q_CMD_ACTIVATE, | |
802 | BNX2X_Q_CMD_UPDATE, | |
803 | BNX2X_Q_CMD_UPDATE_TPA, | |
804 | BNX2X_Q_CMD_HALT, | |
805 | BNX2X_Q_CMD_CFC_DEL, | |
806 | BNX2X_Q_CMD_TERMINATE, | |
807 | BNX2X_Q_CMD_EMPTY, | |
808 | BNX2X_Q_CMD_MAX, | |
809 | }; | |
810 | ||
811 | /* queue SETUP + INIT flags */ | |
812 | enum { | |
813 | BNX2X_Q_FLG_TPA, | |
f5219d8e | 814 | BNX2X_Q_FLG_TPA_IPV6, |
621b4d66 | 815 | BNX2X_Q_FLG_TPA_GRO, |
619c5cb6 VZ |
816 | BNX2X_Q_FLG_STATS, |
817 | BNX2X_Q_FLG_ZERO_STATS, | |
818 | BNX2X_Q_FLG_ACTIVE, | |
819 | BNX2X_Q_FLG_OV, | |
820 | BNX2X_Q_FLG_VLAN, | |
821 | BNX2X_Q_FLG_COS, | |
822 | BNX2X_Q_FLG_HC, | |
823 | BNX2X_Q_FLG_HC_EN, | |
824 | BNX2X_Q_FLG_DHC, | |
825 | BNX2X_Q_FLG_FCOE, | |
826 | BNX2X_Q_FLG_LEADING_RSS, | |
827 | BNX2X_Q_FLG_MCAST, | |
828 | BNX2X_Q_FLG_DEF_VLAN, | |
829 | BNX2X_Q_FLG_TX_SWITCH, | |
830 | BNX2X_Q_FLG_TX_SEC, | |
831 | BNX2X_Q_FLG_ANTI_SPOOF, | |
a3348722 | 832 | BNX2X_Q_FLG_SILENT_VLAN_REM, |
91226790 | 833 | BNX2X_Q_FLG_FORCE_DEFAULT_PRI, |
e287a75c DK |
834 | BNX2X_Q_FLG_PCSUM_ON_PKT, |
835 | BNX2X_Q_FLG_TUN_INC_INNER_IP_ID | |
619c5cb6 VZ |
836 | }; |
837 | ||
16a5fd92 | 838 | /* Queue type options: queue type may be a combination of below. */ |
619c5cb6 VZ |
839 | enum bnx2x_q_type { |
840 | /** TODO: Consider moving both these flags into the init() | |
841 | * ramrod params. | |
842 | */ | |
843 | BNX2X_Q_TYPE_HAS_RX, | |
844 | BNX2X_Q_TYPE_HAS_TX, | |
845 | }; | |
846 | ||
6383c0b3 | 847 | #define BNX2X_PRIMARY_CID_INDEX 0 |
8d7b0278 | 848 | #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ |
6383c0b3 AE |
849 | #define BNX2X_MULTI_TX_COS_E2_E3A0 2 |
850 | #define BNX2X_MULTI_TX_COS_E3B0 3 | |
8d7b0278 | 851 | #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ |
6383c0b3 | 852 | |
3ec9f9ca | 853 | #define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) |
6383c0b3 | 854 | |
619c5cb6 VZ |
855 | struct bnx2x_queue_init_params { |
856 | struct { | |
857 | unsigned long flags; | |
858 | u16 hc_rate; | |
859 | u8 fw_sb_id; | |
860 | u8 sb_cq_index; | |
861 | } tx; | |
862 | ||
863 | struct { | |
864 | unsigned long flags; | |
865 | u16 hc_rate; | |
866 | u8 fw_sb_id; | |
867 | u8 sb_cq_index; | |
868 | } rx; | |
869 | ||
870 | /* CID context in the host memory */ | |
6383c0b3 AE |
871 | struct eth_context *cxts[BNX2X_MULTI_TX_COS]; |
872 | ||
873 | /* maximum number of cos supported by hardware */ | |
874 | u8 max_cos; | |
875 | }; | |
876 | ||
877 | struct bnx2x_queue_terminate_params { | |
878 | /* index within the tx_only cids of this queue object */ | |
879 | u8 cid_index; | |
880 | }; | |
881 | ||
882 | struct bnx2x_queue_cfc_del_params { | |
883 | /* index within the tx_only cids of this queue object */ | |
884 | u8 cid_index; | |
619c5cb6 VZ |
885 | }; |
886 | ||
887 | struct bnx2x_queue_update_params { | |
888 | unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ | |
889 | u16 def_vlan; | |
890 | u16 silent_removal_value; | |
891 | u16 silent_removal_mask; | |
6383c0b3 AE |
892 | /* index within the tx_only cids of this queue object */ |
893 | u8 cid_index; | |
619c5cb6 VZ |
894 | }; |
895 | ||
14a94ebd MK |
896 | struct bnx2x_queue_update_tpa_params { |
897 | dma_addr_t sge_map; | |
898 | u8 update_ipv4; | |
899 | u8 update_ipv6; | |
900 | u8 max_tpa_queues; | |
901 | u8 max_sges_pkt; | |
902 | u8 complete_on_both_clients; | |
903 | u8 dont_verify_thr; | |
904 | u8 tpa_mode; | |
905 | u8 _pad; | |
906 | ||
907 | u16 sge_buff_sz; | |
908 | u16 max_agg_sz; | |
909 | ||
910 | u16 sge_pause_thr_low; | |
911 | u16 sge_pause_thr_high; | |
912 | }; | |
913 | ||
619c5cb6 VZ |
914 | struct rxq_pause_params { |
915 | u16 bd_th_lo; | |
916 | u16 bd_th_hi; | |
917 | u16 rcq_th_lo; | |
918 | u16 rcq_th_hi; | |
919 | u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ | |
920 | u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ | |
921 | u16 pri_map; | |
922 | }; | |
923 | ||
924 | /* general */ | |
925 | struct bnx2x_general_setup_params { | |
926 | /* valid iff BNX2X_Q_FLG_STATS */ | |
927 | u8 stat_id; | |
928 | ||
929 | u8 spcl_id; | |
930 | u16 mtu; | |
6383c0b3 | 931 | u8 cos; |
619c5cb6 VZ |
932 | }; |
933 | ||
934 | struct bnx2x_rxq_setup_params { | |
935 | /* dma */ | |
936 | dma_addr_t dscr_map; | |
937 | dma_addr_t sge_map; | |
938 | dma_addr_t rcq_map; | |
939 | dma_addr_t rcq_np_map; | |
940 | ||
941 | u16 drop_flags; | |
942 | u16 buf_sz; | |
943 | u8 fw_sb_id; | |
944 | u8 cl_qzone_id; | |
945 | ||
946 | /* valid iff BNX2X_Q_FLG_TPA */ | |
947 | u16 tpa_agg_sz; | |
948 | u16 sge_buf_sz; | |
949 | u8 max_sges_pkt; | |
950 | u8 max_tpa_queues; | |
951 | u8 rss_engine_id; | |
952 | ||
259afa1f YM |
953 | /* valid iff BNX2X_Q_FLG_MCAST */ |
954 | u8 mcast_engine_id; | |
955 | ||
619c5cb6 VZ |
956 | u8 cache_line_log; |
957 | ||
958 | u8 sb_cq_index; | |
959 | ||
960 | /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ | |
961 | u16 silent_removal_value; | |
962 | u16 silent_removal_mask; | |
963 | }; | |
964 | ||
965 | struct bnx2x_txq_setup_params { | |
966 | /* dma */ | |
967 | dma_addr_t dscr_map; | |
968 | ||
969 | u8 fw_sb_id; | |
970 | u8 sb_cq_index; | |
971 | u8 cos; /* valid iff BNX2X_Q_FLG_COS */ | |
972 | u16 traffic_type; | |
973 | /* equals to the leading rss client id, used for TX classification*/ | |
974 | u8 tss_leading_cl_id; | |
975 | ||
976 | /* valid iff BNX2X_Q_FLG_DEF_VLAN */ | |
977 | u16 default_vlan; | |
978 | }; | |
979 | ||
980 | struct bnx2x_queue_setup_params { | |
619c5cb6 | 981 | struct bnx2x_general_setup_params gen_params; |
619c5cb6 | 982 | struct bnx2x_txq_setup_params txq_params; |
6383c0b3 AE |
983 | struct bnx2x_rxq_setup_params rxq_params; |
984 | struct rxq_pause_params pause_params; | |
619c5cb6 VZ |
985 | unsigned long flags; |
986 | }; | |
987 | ||
6383c0b3 AE |
988 | struct bnx2x_queue_setup_tx_only_params { |
989 | struct bnx2x_general_setup_params gen_params; | |
990 | struct bnx2x_txq_setup_params txq_params; | |
991 | unsigned long flags; | |
992 | /* index within the tx_only cids of this queue object */ | |
993 | u8 cid_index; | |
994 | }; | |
619c5cb6 VZ |
995 | |
996 | struct bnx2x_queue_state_params { | |
997 | struct bnx2x_queue_sp_obj *q_obj; | |
998 | ||
999 | /* Current command */ | |
1000 | enum bnx2x_queue_cmd cmd; | |
1001 | ||
1002 | /* may have RAMROD_COMP_WAIT set only */ | |
6383c0b3 | 1003 | unsigned long ramrod_flags; |
619c5cb6 VZ |
1004 | |
1005 | /* Params according to the current command */ | |
1006 | union { | |
6383c0b3 | 1007 | struct bnx2x_queue_update_params update; |
14a94ebd | 1008 | struct bnx2x_queue_update_tpa_params update_tpa; |
6383c0b3 AE |
1009 | struct bnx2x_queue_setup_params setup; |
1010 | struct bnx2x_queue_init_params init; | |
1011 | struct bnx2x_queue_setup_tx_only_params tx_only; | |
1012 | struct bnx2x_queue_terminate_params terminate; | |
1013 | struct bnx2x_queue_cfc_del_params cfc_del; | |
619c5cb6 VZ |
1014 | } params; |
1015 | }; | |
1016 | ||
a3348722 BW |
1017 | struct bnx2x_viflist_params { |
1018 | u8 echo_res; | |
1019 | u8 func_bit_map_res; | |
1020 | }; | |
1021 | ||
619c5cb6 | 1022 | struct bnx2x_queue_sp_obj { |
6383c0b3 | 1023 | u32 cids[BNX2X_MULTI_TX_COS]; |
619c5cb6 VZ |
1024 | u8 cl_id; |
1025 | u8 func_id; | |
1026 | ||
16a5fd92 YM |
1027 | /* number of traffic classes supported by queue. |
1028 | * The primary connection of the queue supports the first traffic | |
1029 | * class. Any further traffic class is supported by a tx-only | |
6383c0b3 AE |
1030 | * connection. |
1031 | * | |
1032 | * Therefore max_cos is also a number of valid entries in the cids | |
1033 | * array. | |
1034 | */ | |
1035 | u8 max_cos; | |
1036 | u8 num_tx_only, next_tx_only; | |
1037 | ||
619c5cb6 VZ |
1038 | enum bnx2x_q_state state, next_state; |
1039 | ||
1040 | /* bits from enum bnx2x_q_type */ | |
1041 | unsigned long type; | |
1042 | ||
1043 | /* BNX2X_Q_CMD_XX bits. This object implements "one | |
1044 | * pending" paradigm but for debug and tracing purposes it's | |
16a5fd92 | 1045 | * more convenient to have different bits for different |
619c5cb6 VZ |
1046 | * commands. |
1047 | */ | |
1048 | unsigned long pending; | |
1049 | ||
1050 | /* Buffer to use as a ramrod data and its mapping */ | |
1051 | void *rdata; | |
1052 | dma_addr_t rdata_mapping; | |
1053 | ||
1054 | /** | |
1055 | * Performs one state change according to the given parameters. | |
1056 | * | |
1057 | * @return 0 in case of success and negative value otherwise. | |
1058 | */ | |
1059 | int (*send_cmd)(struct bnx2x *bp, | |
1060 | struct bnx2x_queue_state_params *params); | |
1061 | ||
1062 | /** | |
1063 | * Sets the pending bit according to the requested transition. | |
1064 | */ | |
1065 | int (*set_pending)(struct bnx2x_queue_sp_obj *o, | |
1066 | struct bnx2x_queue_state_params *params); | |
1067 | ||
1068 | /** | |
1069 | * Checks that the requested state transition is legal. | |
1070 | */ | |
1071 | int (*check_transition)(struct bnx2x *bp, | |
1072 | struct bnx2x_queue_sp_obj *o, | |
1073 | struct bnx2x_queue_state_params *params); | |
1074 | ||
1075 | /** | |
1076 | * Completes the pending command. | |
1077 | */ | |
1078 | int (*complete_cmd)(struct bnx2x *bp, | |
1079 | struct bnx2x_queue_sp_obj *o, | |
1080 | enum bnx2x_queue_cmd); | |
1081 | ||
1082 | int (*wait_comp)(struct bnx2x *bp, | |
1083 | struct bnx2x_queue_sp_obj *o, | |
1084 | enum bnx2x_queue_cmd cmd); | |
1085 | }; | |
1086 | ||
1087 | /********************** Function state update *********************************/ | |
1088 | /* Allowed Function states */ | |
1089 | enum bnx2x_func_state { | |
1090 | BNX2X_F_STATE_RESET, | |
1091 | BNX2X_F_STATE_INITIALIZED, | |
1092 | BNX2X_F_STATE_STARTED, | |
6debea87 | 1093 | BNX2X_F_STATE_TX_STOPPED, |
619c5cb6 VZ |
1094 | BNX2X_F_STATE_MAX, |
1095 | }; | |
1096 | ||
1097 | /* Allowed Function commands */ | |
1098 | enum bnx2x_func_cmd { | |
1099 | BNX2X_F_CMD_HW_INIT, | |
1100 | BNX2X_F_CMD_START, | |
1101 | BNX2X_F_CMD_STOP, | |
1102 | BNX2X_F_CMD_HW_RESET, | |
a3348722 BW |
1103 | BNX2X_F_CMD_AFEX_UPDATE, |
1104 | BNX2X_F_CMD_AFEX_VIFLISTS, | |
6debea87 DK |
1105 | BNX2X_F_CMD_TX_STOP, |
1106 | BNX2X_F_CMD_TX_START, | |
55c11941 | 1107 | BNX2X_F_CMD_SWITCH_UPDATE, |
619c5cb6 VZ |
1108 | BNX2X_F_CMD_MAX, |
1109 | }; | |
1110 | ||
1111 | struct bnx2x_func_hw_init_params { | |
1112 | /* A load phase returned by MCP. | |
1113 | * | |
1114 | * May be: | |
1115 | * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP | |
1116 | * FW_MSG_CODE_DRV_LOAD_COMMON | |
1117 | * FW_MSG_CODE_DRV_LOAD_PORT | |
1118 | * FW_MSG_CODE_DRV_LOAD_FUNCTION | |
1119 | */ | |
1120 | u32 load_phase; | |
1121 | }; | |
1122 | ||
1123 | struct bnx2x_func_hw_reset_params { | |
1124 | /* A load phase returned by MCP. | |
1125 | * | |
1126 | * May be: | |
1127 | * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP | |
1128 | * FW_MSG_CODE_DRV_LOAD_COMMON | |
1129 | * FW_MSG_CODE_DRV_LOAD_PORT | |
1130 | * FW_MSG_CODE_DRV_LOAD_FUNCTION | |
1131 | */ | |
1132 | u32 reset_phase; | |
1133 | }; | |
1134 | ||
1135 | struct bnx2x_func_start_params { | |
1136 | /* Multi Function mode: | |
1137 | * - Single Function | |
1138 | * - Switch Dependent | |
1139 | * - Switch Independent | |
1140 | */ | |
1141 | u16 mf_mode; | |
1142 | ||
1143 | /* Switch Dependent mode outer VLAN tag */ | |
1144 | u16 sd_vlan_tag; | |
1145 | ||
1146 | /* Function cos mode */ | |
1147 | u8 network_cos_mode; | |
1bc277f7 DK |
1148 | |
1149 | /* NVGRE classification enablement */ | |
1150 | u8 nvgre_clss_en; | |
1151 | ||
1152 | /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */ | |
1153 | u8 gre_tunnel_mode; | |
1154 | ||
1155 | /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */ | |
1156 | u8 gre_tunnel_rss; | |
619c5cb6 VZ |
1157 | }; |
1158 | ||
55c11941 MS |
1159 | struct bnx2x_func_switch_update_params { |
1160 | u8 suspend; | |
1161 | }; | |
1162 | ||
a3348722 BW |
1163 | struct bnx2x_func_afex_update_params { |
1164 | u16 vif_id; | |
1165 | u16 afex_default_vlan; | |
1166 | u8 allowed_priorities; | |
1167 | }; | |
1168 | ||
1169 | struct bnx2x_func_afex_viflists_params { | |
1170 | u16 vif_list_index; | |
1171 | u8 func_bit_map; | |
1172 | u8 afex_vif_list_command; | |
1173 | u8 func_to_clear; | |
1174 | }; | |
6debea87 DK |
1175 | struct bnx2x_func_tx_start_params { |
1176 | struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; | |
1177 | u8 dcb_enabled; | |
1178 | u8 dcb_version; | |
1179 | u8 dont_add_pri_0_en; | |
1180 | }; | |
1181 | ||
619c5cb6 VZ |
1182 | struct bnx2x_func_state_params { |
1183 | struct bnx2x_func_sp_obj *f_obj; | |
1184 | ||
1185 | /* Current command */ | |
1186 | enum bnx2x_func_cmd cmd; | |
1187 | ||
1188 | /* may have RAMROD_COMP_WAIT set only */ | |
1189 | unsigned long ramrod_flags; | |
1190 | ||
1191 | /* Params according to the current command */ | |
1192 | union { | |
1193 | struct bnx2x_func_hw_init_params hw_init; | |
1194 | struct bnx2x_func_hw_reset_params hw_reset; | |
1195 | struct bnx2x_func_start_params start; | |
55c11941 | 1196 | struct bnx2x_func_switch_update_params switch_update; |
a3348722 BW |
1197 | struct bnx2x_func_afex_update_params afex_update; |
1198 | struct bnx2x_func_afex_viflists_params afex_viflists; | |
6debea87 | 1199 | struct bnx2x_func_tx_start_params tx_start; |
619c5cb6 VZ |
1200 | } params; |
1201 | }; | |
1202 | ||
1203 | struct bnx2x_func_sp_drv_ops { | |
1204 | /* Init tool + runtime initialization: | |
1205 | * - Common Chip | |
1206 | * - Common (per Path) | |
1207 | * - Port | |
1208 | * - Function phases | |
1209 | */ | |
1210 | int (*init_hw_cmn_chip)(struct bnx2x *bp); | |
1211 | int (*init_hw_cmn)(struct bnx2x *bp); | |
1212 | int (*init_hw_port)(struct bnx2x *bp); | |
1213 | int (*init_hw_func)(struct bnx2x *bp); | |
1214 | ||
1215 | /* Reset Function HW: Common, Port, Function phases. */ | |
1216 | void (*reset_hw_cmn)(struct bnx2x *bp); | |
1217 | void (*reset_hw_port)(struct bnx2x *bp); | |
1218 | void (*reset_hw_func)(struct bnx2x *bp); | |
1219 | ||
1220 | /* Init/Free GUNZIP resources */ | |
1221 | int (*gunzip_init)(struct bnx2x *bp); | |
1222 | void (*gunzip_end)(struct bnx2x *bp); | |
1223 | ||
1224 | /* Prepare/Release FW resources */ | |
1225 | int (*init_fw)(struct bnx2x *bp); | |
1226 | void (*release_fw)(struct bnx2x *bp); | |
1227 | }; | |
1228 | ||
1229 | struct bnx2x_func_sp_obj { | |
1230 | enum bnx2x_func_state state, next_state; | |
1231 | ||
1232 | /* BNX2X_FUNC_CMD_XX bits. This object implements "one | |
1233 | * pending" paradigm but for debug and tracing purposes it's | |
16a5fd92 | 1234 | * more convenient to have different bits for different |
619c5cb6 VZ |
1235 | * commands. |
1236 | */ | |
1237 | unsigned long pending; | |
1238 | ||
1239 | /* Buffer to use as a ramrod data and its mapping */ | |
1240 | void *rdata; | |
1241 | dma_addr_t rdata_mapping; | |
1242 | ||
a3348722 BW |
1243 | /* Buffer to use as a afex ramrod data and its mapping. |
1244 | * This can't be same rdata as above because afex ramrod requests | |
1245 | * can arrive to the object in parallel to other ramrod requests. | |
1246 | */ | |
1247 | void *afex_rdata; | |
1248 | dma_addr_t afex_rdata_mapping; | |
1249 | ||
619c5cb6 VZ |
1250 | /* this mutex validates that when pending flag is taken, the next |
1251 | * ramrod to be sent will be the one set the pending bit | |
1252 | */ | |
1253 | struct mutex one_pending_mutex; | |
1254 | ||
1255 | /* Driver interface */ | |
1256 | struct bnx2x_func_sp_drv_ops *drv; | |
1257 | ||
1258 | /** | |
1259 | * Performs one state change according to the given parameters. | |
1260 | * | |
1261 | * @return 0 in case of success and negative value otherwise. | |
1262 | */ | |
1263 | int (*send_cmd)(struct bnx2x *bp, | |
1264 | struct bnx2x_func_state_params *params); | |
1265 | ||
1266 | /** | |
1267 | * Checks that the requested state transition is legal. | |
1268 | */ | |
1269 | int (*check_transition)(struct bnx2x *bp, | |
1270 | struct bnx2x_func_sp_obj *o, | |
1271 | struct bnx2x_func_state_params *params); | |
1272 | ||
1273 | /** | |
1274 | * Completes the pending command. | |
1275 | */ | |
1276 | int (*complete_cmd)(struct bnx2x *bp, | |
1277 | struct bnx2x_func_sp_obj *o, | |
1278 | enum bnx2x_func_cmd cmd); | |
1279 | ||
1280 | int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, | |
1281 | enum bnx2x_func_cmd cmd); | |
1282 | }; | |
1283 | ||
1284 | /********************** Interfaces ********************************************/ | |
1285 | /* Queueable objects set */ | |
1286 | union bnx2x_qable_obj { | |
1287 | struct bnx2x_vlan_mac_obj vlan_mac; | |
1288 | }; | |
1289 | /************** Function state update *********/ | |
1290 | void bnx2x_init_func_obj(struct bnx2x *bp, | |
1291 | struct bnx2x_func_sp_obj *obj, | |
1292 | void *rdata, dma_addr_t rdata_mapping, | |
a3348722 | 1293 | void *afex_rdata, dma_addr_t afex_rdata_mapping, |
619c5cb6 VZ |
1294 | struct bnx2x_func_sp_drv_ops *drv_iface); |
1295 | ||
1296 | int bnx2x_func_state_change(struct bnx2x *bp, | |
1297 | struct bnx2x_func_state_params *params); | |
1298 | ||
6debea87 DK |
1299 | enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, |
1300 | struct bnx2x_func_sp_obj *o); | |
619c5cb6 VZ |
1301 | /******************* Queue State **************/ |
1302 | void bnx2x_init_queue_obj(struct bnx2x *bp, | |
6383c0b3 AE |
1303 | struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, |
1304 | u8 cid_cnt, u8 func_id, void *rdata, | |
1305 | dma_addr_t rdata_mapping, unsigned long type); | |
619c5cb6 VZ |
1306 | |
1307 | int bnx2x_queue_state_change(struct bnx2x *bp, | |
1308 | struct bnx2x_queue_state_params *params); | |
1309 | ||
67c431a5 AE |
1310 | int bnx2x_get_q_logical_state(struct bnx2x *bp, |
1311 | struct bnx2x_queue_sp_obj *obj); | |
1312 | ||
619c5cb6 VZ |
1313 | /********************* VLAN-MAC ****************/ |
1314 | void bnx2x_init_mac_obj(struct bnx2x *bp, | |
1315 | struct bnx2x_vlan_mac_obj *mac_obj, | |
1316 | u8 cl_id, u32 cid, u8 func_id, void *rdata, | |
1317 | dma_addr_t rdata_mapping, int state, | |
1318 | unsigned long *pstate, bnx2x_obj_type type, | |
1319 | struct bnx2x_credit_pool_obj *macs_pool); | |
1320 | ||
1321 | void bnx2x_init_vlan_obj(struct bnx2x *bp, | |
1322 | struct bnx2x_vlan_mac_obj *vlan_obj, | |
1323 | u8 cl_id, u32 cid, u8 func_id, void *rdata, | |
1324 | dma_addr_t rdata_mapping, int state, | |
1325 | unsigned long *pstate, bnx2x_obj_type type, | |
1326 | struct bnx2x_credit_pool_obj *vlans_pool); | |
1327 | ||
8b09be5f YM |
1328 | int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp, |
1329 | struct bnx2x_vlan_mac_obj *o); | |
1330 | void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp, | |
1331 | struct bnx2x_vlan_mac_obj *o); | |
1332 | int bnx2x_vlan_mac_h_write_lock(struct bnx2x *bp, | |
1333 | struct bnx2x_vlan_mac_obj *o); | |
619c5cb6 | 1334 | int bnx2x_config_vlan_mac(struct bnx2x *bp, |
8b09be5f | 1335 | struct bnx2x_vlan_mac_ramrod_params *p); |
619c5cb6 VZ |
1336 | |
1337 | int bnx2x_vlan_mac_move(struct bnx2x *bp, | |
1338 | struct bnx2x_vlan_mac_ramrod_params *p, | |
1339 | struct bnx2x_vlan_mac_obj *dest_o); | |
1340 | ||
1341 | /********************* RX MODE ****************/ | |
1342 | ||
1343 | void bnx2x_init_rx_mode_obj(struct bnx2x *bp, | |
1344 | struct bnx2x_rx_mode_obj *o); | |
1345 | ||
1346 | /** | |
1aa8b471 | 1347 | * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. |
619c5cb6 | 1348 | * |
1aa8b471 | 1349 | * @p: Command parameters |
619c5cb6 | 1350 | * |
16a5fd92 | 1351 | * Return: 0 - if operation was successful and there is no pending completions, |
619c5cb6 VZ |
1352 | * positive number - if there are pending completions, |
1353 | * negative - if there were errors | |
1354 | */ | |
1355 | int bnx2x_config_rx_mode(struct bnx2x *bp, | |
1356 | struct bnx2x_rx_mode_ramrod_params *p); | |
1357 | ||
1358 | /****************** MULTICASTS ****************/ | |
1359 | ||
1360 | void bnx2x_init_mcast_obj(struct bnx2x *bp, | |
1361 | struct bnx2x_mcast_obj *mcast_obj, | |
1362 | u8 mcast_cl_id, u32 mcast_cid, u8 func_id, | |
1363 | u8 engine_id, void *rdata, dma_addr_t rdata_mapping, | |
1364 | int state, unsigned long *pstate, | |
1365 | bnx2x_obj_type type); | |
1366 | ||
1367 | /** | |
1aa8b471 BH |
1368 | * bnx2x_config_mcast - Configure multicast MACs list. |
1369 | * | |
1370 | * @cmd: command to execute: BNX2X_MCAST_CMD_X | |
1371 | * | |
1372 | * May configure a new list | |
619c5cb6 VZ |
1373 | * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up |
1374 | * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current | |
1375 | * configuration, continue to execute the pending commands | |
1376 | * (BNX2X_MCAST_CMD_CONT). | |
1377 | * | |
1378 | * If previous command is still pending or if number of MACs to | |
1379 | * configure is more that maximum number of MACs in one command, | |
1380 | * the current command will be enqueued to the tail of the | |
1381 | * pending commands list. | |
1382 | * | |
16a5fd92 | 1383 | * Return: 0 is operation was successful and there are no pending completions, |
619c5cb6 VZ |
1384 | * negative if there were errors, positive if there are pending |
1385 | * completions. | |
1386 | */ | |
1387 | int bnx2x_config_mcast(struct bnx2x *bp, | |
86564c3f YM |
1388 | struct bnx2x_mcast_ramrod_params *p, |
1389 | enum bnx2x_mcast_cmd cmd); | |
619c5cb6 VZ |
1390 | |
1391 | /****************** CREDIT POOL ****************/ | |
1392 | void bnx2x_init_mac_credit_pool(struct bnx2x *bp, | |
1393 | struct bnx2x_credit_pool_obj *p, u8 func_id, | |
1394 | u8 func_num); | |
1395 | void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, | |
1396 | struct bnx2x_credit_pool_obj *p, u8 func_id, | |
1397 | u8 func_num); | |
1398 | ||
619c5cb6 VZ |
1399 | /****************** RSS CONFIGURATION ****************/ |
1400 | void bnx2x_init_rss_config_obj(struct bnx2x *bp, | |
1401 | struct bnx2x_rss_config_obj *rss_obj, | |
1402 | u8 cl_id, u32 cid, u8 func_id, u8 engine_id, | |
1403 | void *rdata, dma_addr_t rdata_mapping, | |
1404 | int state, unsigned long *pstate, | |
1405 | bnx2x_obj_type type); | |
1406 | ||
1407 | /** | |
1aa8b471 | 1408 | * bnx2x_config_rss - Updates RSS configuration according to provided parameters |
619c5cb6 | 1409 | * |
1aa8b471 | 1410 | * Return: 0 in case of success |
619c5cb6 VZ |
1411 | */ |
1412 | int bnx2x_config_rss(struct bnx2x *bp, | |
1413 | struct bnx2x_config_rss_params *p); | |
1414 | ||
1415 | /** | |
1aa8b471 | 1416 | * bnx2x_get_rss_ind_table - Return the current ind_table configuration. |
619c5cb6 | 1417 | * |
1aa8b471 | 1418 | * @ind_table: buffer to fill with the current indirection |
619c5cb6 VZ |
1419 | * table content. Should be at least |
1420 | * T_ETH_INDIRECTION_TABLE_SIZE bytes long. | |
1421 | */ | |
1422 | void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, | |
1423 | u8 *ind_table); | |
1424 | ||
1425 | #endif /* BNX2X_SP_VERBS */ |