]>
Commit | Line | Data |
---|---|---|
4ad79e13 | 1 | /* bnx2x_sriov.c: QLogic Everest network driver. |
290ca2bb | 2 | * |
247fa82b | 3 | * Copyright 2009-2013 Broadcom Corporation |
4ad79e13 YM |
4 | * Copyright 2014 QLogic Corporation |
5 | * All rights reserved | |
290ca2bb | 6 | * |
4ad79e13 | 7 | * Unless you and QLogic execute a separate written software license |
290ca2bb AE |
8 | * agreement governing use of this software, this software is licensed to you |
9 | * under the terms of the GNU General Public License version 2, available | |
10 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
11 | * | |
12 | * Notwithstanding the above, under no circumstances may you combine this | |
4ad79e13 YM |
13 | * software in any way with any other QLogic software provided under a |
14 | * license other than the GPL, without QLogic's express prior written | |
290ca2bb AE |
15 | * consent. |
16 | * | |
08f6dd89 AE |
17 | * Maintained by: Ariel Elior <ariel.elior@qlogic.com> |
18 | * Written by: Shmulik Ravid | |
19 | * Ariel Elior <ariel.elior@qlogic.com> | |
290ca2bb AE |
20 | * |
21 | */ | |
22 | #include "bnx2x.h" | |
23 | #include "bnx2x_init.h" | |
b56e9670 | 24 | #include "bnx2x_cmn.h" |
3ec9f9ca | 25 | #include "bnx2x_sp.h" |
6411280a | 26 | #include <linux/crc32.h> |
3ec9f9ca | 27 | #include <linux/if_vlan.h> |
b56e9670 | 28 | |
6495d15a DK |
29 | static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx, |
30 | struct bnx2x_virtf **vf, | |
31 | struct pf_vf_bulletin_content **bulletin, | |
32 | bool test_queue); | |
33 | ||
b56e9670 AE |
34 | /* General service functions */ |
35 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, | |
36 | u16 pf_id) | |
37 | { | |
38 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), | |
39 | pf_id); | |
40 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
41 | pf_id); | |
42 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
43 | pf_id); | |
44 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
45 | pf_id); | |
46 | } | |
47 | ||
48 | static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, | |
49 | u8 enable) | |
50 | { | |
51 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
52 | enable); | |
53 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
54 | enable); | |
55 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
56 | enable); | |
57 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
58 | enable); | |
59 | } | |
60 | ||
290ca2bb AE |
61 | int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) |
62 | { | |
63 | int idx; | |
64 | ||
65 | for_each_vf(bp, idx) | |
66 | if (bnx2x_vf(bp, idx, abs_vfid) == abs_vfid) | |
67 | break; | |
68 | return idx; | |
69 | } | |
70 | ||
71 | static | |
72 | struct bnx2x_virtf *bnx2x_vf_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) | |
73 | { | |
74 | u16 idx = (u16)bnx2x_vf_idx_by_abs_fid(bp, abs_vfid); | |
75 | return (idx < BNX2X_NR_VIRTFN(bp)) ? BP_VF(bp, idx) : NULL; | |
76 | } | |
77 | ||
b93288d5 AE |
78 | static void bnx2x_vf_igu_ack_sb(struct bnx2x *bp, struct bnx2x_virtf *vf, |
79 | u8 igu_sb_id, u8 segment, u16 index, u8 op, | |
80 | u8 update) | |
81 | { | |
82 | /* acking a VF sb through the PF - use the GRC */ | |
83 | u32 ctl; | |
84 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
85 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
86 | u32 func_encode = vf->abs_vfid; | |
87 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id; | |
88 | struct igu_regular cmd_data = {0}; | |
89 | ||
90 | cmd_data.sb_id_and_flags = | |
91 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
92 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
93 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
94 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
95 | ||
96 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
97 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
98 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
99 | ||
100 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
101 | cmd_data.sb_id_and_flags, igu_addr_data); | |
102 | REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags); | |
103 | mmiowb(); | |
104 | barrier(); | |
105 | ||
106 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
107 | ctl, igu_addr_ctl); | |
108 | REG_WR(bp, igu_addr_ctl, ctl); | |
109 | mmiowb(); | |
110 | barrier(); | |
111 | } | |
3a3534ec YM |
112 | |
113 | static bool bnx2x_validate_vf_sp_objs(struct bnx2x *bp, | |
114 | struct bnx2x_virtf *vf, | |
115 | bool print_err) | |
116 | { | |
117 | if (!bnx2x_leading_vfq(vf, sp_initialized)) { | |
118 | if (print_err) | |
119 | BNX2X_ERR("Slowpath objects not yet initialized!\n"); | |
120 | else | |
121 | DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n"); | |
122 | return false; | |
123 | } | |
124 | return true; | |
125 | } | |
126 | ||
8db573ba | 127 | /* VFOP operations states */ |
8db573ba AE |
128 | void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf, |
129 | struct bnx2x_queue_init_params *init_params, | |
130 | struct bnx2x_queue_setup_params *setup_params, | |
131 | u16 q_idx, u16 sb_idx) | |
290ca2bb | 132 | { |
8db573ba AE |
133 | DP(BNX2X_MSG_IOV, |
134 | "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d", | |
135 | vf->abs_vfid, | |
136 | q_idx, | |
137 | sb_idx, | |
138 | init_params->tx.sb_cq_index, | |
139 | init_params->tx.hc_rate, | |
140 | setup_params->flags, | |
141 | setup_params->txq_params.traffic_type); | |
290ca2bb AE |
142 | } |
143 | ||
8db573ba AE |
144 | void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf, |
145 | struct bnx2x_queue_init_params *init_params, | |
146 | struct bnx2x_queue_setup_params *setup_params, | |
147 | u16 q_idx, u16 sb_idx) | |
290ca2bb | 148 | { |
8db573ba AE |
149 | struct bnx2x_rxq_setup_params *rxq_params = &setup_params->rxq_params; |
150 | ||
151 | DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n" | |
152 | "sge-size=%d, max_sge_pkt=%d, tpa-agg-size=%d, flags=0x%lx, drop-flags=0x%x, cache-log=%d\n", | |
153 | vf->abs_vfid, | |
154 | q_idx, | |
155 | sb_idx, | |
156 | init_params->rx.sb_cq_index, | |
157 | init_params->rx.hc_rate, | |
158 | setup_params->gen_params.mtu, | |
159 | rxq_params->buf_sz, | |
160 | rxq_params->sge_buf_sz, | |
161 | rxq_params->max_sges_pkt, | |
162 | rxq_params->tpa_agg_sz, | |
163 | setup_params->flags, | |
164 | rxq_params->drop_flags, | |
165 | rxq_params->cache_line_log); | |
290ca2bb AE |
166 | } |
167 | ||
8db573ba AE |
168 | void bnx2x_vfop_qctor_prep(struct bnx2x *bp, |
169 | struct bnx2x_virtf *vf, | |
170 | struct bnx2x_vf_queue *q, | |
2dc33bbc | 171 | struct bnx2x_vf_queue_construct_params *p, |
8db573ba | 172 | unsigned long q_type) |
290ca2bb | 173 | { |
8db573ba AE |
174 | struct bnx2x_queue_init_params *init_p = &p->qstate.params.init; |
175 | struct bnx2x_queue_setup_params *setup_p = &p->prep_qsetup; | |
290ca2bb | 176 | |
8db573ba | 177 | /* INIT */ |
290ca2bb | 178 | |
8db573ba AE |
179 | /* Enable host coalescing in the transition to INIT state */ |
180 | if (test_bit(BNX2X_Q_FLG_HC, &init_p->rx.flags)) | |
181 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->rx.flags); | |
182 | ||
183 | if (test_bit(BNX2X_Q_FLG_HC, &init_p->tx.flags)) | |
184 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->tx.flags); | |
185 | ||
186 | /* FW SB ID */ | |
187 | init_p->rx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); | |
188 | init_p->tx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); | |
189 | ||
190 | /* context */ | |
191 | init_p->cxts[0] = q->cxt; | |
192 | ||
193 | /* SETUP */ | |
194 | ||
195 | /* Setup-op general parameters */ | |
196 | setup_p->gen_params.spcl_id = vf->sp_cl_id; | |
197 | setup_p->gen_params.stat_id = vfq_stat_id(vf, q); | |
02dc4025 | 198 | setup_p->gen_params.fp_hsi = vf->fp_hsi; |
8db573ba | 199 | |
8db573ba AE |
200 | /* Setup-op flags: |
201 | * collect statistics, zero statistics, local-switching, security, | |
202 | * OV for Flex10, RSS and MCAST for leading | |
203 | */ | |
204 | if (test_bit(BNX2X_Q_FLG_STATS, &setup_p->flags)) | |
205 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &setup_p->flags); | |
206 | ||
207 | /* for VFs, enable tx switching, bd coherency, and mac address | |
208 | * anti-spoofing | |
209 | */ | |
210 | __set_bit(BNX2X_Q_FLG_TX_SWITCH, &setup_p->flags); | |
211 | __set_bit(BNX2X_Q_FLG_TX_SEC, &setup_p->flags); | |
212 | __set_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags); | |
213 | ||
8db573ba AE |
214 | /* Setup-op rx parameters */ |
215 | if (test_bit(BNX2X_Q_TYPE_HAS_RX, &q_type)) { | |
216 | struct bnx2x_rxq_setup_params *rxq_p = &setup_p->rxq_params; | |
217 | ||
218 | rxq_p->cl_qzone_id = vfq_qzone_id(vf, q); | |
219 | rxq_p->fw_sb_id = vf_igu_sb(vf, q->sb_idx); | |
220 | rxq_p->rss_engine_id = FW_VF_HANDLE(vf->abs_vfid); | |
221 | ||
222 | if (test_bit(BNX2X_Q_FLG_TPA, &setup_p->flags)) | |
223 | rxq_p->max_tpa_queues = BNX2X_VF_MAX_TPA_AGG_QUEUES; | |
224 | } | |
225 | ||
226 | /* Setup-op tx parameters */ | |
227 | if (test_bit(BNX2X_Q_TYPE_HAS_TX, &q_type)) { | |
228 | setup_p->txq_params.tss_leading_cl_id = vf->leading_rss; | |
229 | setup_p->txq_params.fw_sb_id = vf_igu_sb(vf, q->sb_idx); | |
290ca2bb AE |
230 | } |
231 | } | |
232 | ||
2dc33bbc YM |
233 | static int bnx2x_vf_queue_create(struct bnx2x *bp, |
234 | struct bnx2x_virtf *vf, int qid, | |
235 | struct bnx2x_vf_queue_construct_params *qctor) | |
290ca2bb | 236 | { |
2dc33bbc YM |
237 | struct bnx2x_queue_state_params *q_params; |
238 | int rc = 0; | |
8db573ba | 239 | |
2dc33bbc | 240 | DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); |
8db573ba | 241 | |
2dc33bbc YM |
242 | /* Prepare ramrod information */ |
243 | q_params = &qctor->qstate; | |
244 | q_params->q_obj = &bnx2x_vfq(vf, qid, sp_obj); | |
245 | set_bit(RAMROD_COMP_WAIT, &q_params->ramrod_flags); | |
8db573ba | 246 | |
2dc33bbc YM |
247 | if (bnx2x_get_q_logical_state(bp, q_params->q_obj) == |
248 | BNX2X_Q_LOGICAL_STATE_ACTIVE) { | |
249 | DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n"); | |
250 | goto out; | |
290ca2bb | 251 | } |
290ca2bb | 252 | |
2dc33bbc YM |
253 | /* Run Queue 'construction' ramrods */ |
254 | q_params->cmd = BNX2X_Q_CMD_INIT; | |
255 | rc = bnx2x_queue_state_change(bp, q_params); | |
256 | if (rc) | |
257 | goto out; | |
290ca2bb | 258 | |
2dc33bbc YM |
259 | memcpy(&q_params->params.setup, &qctor->prep_qsetup, |
260 | sizeof(struct bnx2x_queue_setup_params)); | |
261 | q_params->cmd = BNX2X_Q_CMD_SETUP; | |
262 | rc = bnx2x_queue_state_change(bp, q_params); | |
263 | if (rc) | |
264 | goto out; | |
290ca2bb | 265 | |
2dc33bbc YM |
266 | /* enable interrupts */ |
267 | bnx2x_vf_igu_ack_sb(bp, vf, vf_igu_sb(vf, bnx2x_vfq(vf, qid, sb_idx)), | |
268 | USTORM_ID, 0, IGU_INT_ENABLE, 0); | |
269 | out: | |
270 | return rc; | |
290ca2bb AE |
271 | } |
272 | ||
2dc33bbc YM |
273 | static int bnx2x_vf_queue_destroy(struct bnx2x *bp, struct bnx2x_virtf *vf, |
274 | int qid) | |
463a68a7 | 275 | { |
2dc33bbc YM |
276 | enum bnx2x_queue_cmd cmds[] = {BNX2X_Q_CMD_HALT, |
277 | BNX2X_Q_CMD_TERMINATE, | |
278 | BNX2X_Q_CMD_CFC_DEL}; | |
279 | struct bnx2x_queue_state_params q_params; | |
280 | int rc, i; | |
463a68a7 | 281 | |
2dc33bbc | 282 | DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); |
463a68a7 | 283 | |
2dc33bbc YM |
284 | /* Prepare ramrod information */ |
285 | memset(&q_params, 0, sizeof(struct bnx2x_queue_state_params)); | |
286 | q_params.q_obj = &bnx2x_vfq(vf, qid, sp_obj); | |
287 | set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
463a68a7 | 288 | |
2dc33bbc YM |
289 | if (bnx2x_get_q_logical_state(bp, q_params.q_obj) == |
290 | BNX2X_Q_LOGICAL_STATE_STOPPED) { | |
291 | DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n"); | |
292 | goto out; | |
293 | } | |
463a68a7 | 294 | |
2dc33bbc YM |
295 | /* Run Queue 'destruction' ramrods */ |
296 | for (i = 0; i < ARRAY_SIZE(cmds); i++) { | |
297 | q_params.cmd = cmds[i]; | |
298 | rc = bnx2x_queue_state_change(bp, &q_params); | |
299 | if (rc) { | |
300 | BNX2X_ERR("Failed to run Queue command %d\n", cmds[i]); | |
301 | return rc; | |
b9871bcf | 302 | } |
463a68a7 | 303 | } |
2dc33bbc YM |
304 | out: |
305 | /* Clean Context */ | |
306 | if (bnx2x_vfq(vf, qid, cxt)) { | |
307 | bnx2x_vfq(vf, qid, cxt)->ustorm_ag_context.cdu_usage = 0; | |
308 | bnx2x_vfq(vf, qid, cxt)->xstorm_ag_context.cdu_reserved = 0; | |
463a68a7 | 309 | } |
2dc33bbc YM |
310 | |
311 | return 0; | |
463a68a7 AE |
312 | } |
313 | ||
8db573ba AE |
314 | static void |
315 | bnx2x_vf_set_igu_info(struct bnx2x *bp, u8 igu_sb_id, u8 abs_vfid) | |
290ca2bb | 316 | { |
8db573ba AE |
317 | struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); |
318 | if (vf) { | |
b9871bcf AE |
319 | /* the first igu entry belonging to VFs of this PF */ |
320 | if (!BP_VFDB(bp)->first_vf_igu_entry) | |
321 | BP_VFDB(bp)->first_vf_igu_entry = igu_sb_id; | |
322 | ||
323 | /* the first igu entry belonging to this VF */ | |
8db573ba AE |
324 | if (!vf_sb_count(vf)) |
325 | vf->igu_base_id = igu_sb_id; | |
b9871bcf | 326 | |
8db573ba | 327 | ++vf_sb_count(vf); |
b9871bcf | 328 | ++vf->sb_count; |
8db573ba | 329 | } |
b9871bcf | 330 | BP_VFDB(bp)->vf_sbs_pool++; |
8db573ba | 331 | } |
290ca2bb | 332 | |
2dc33bbc YM |
333 | static inline void bnx2x_vf_vlan_credit(struct bnx2x *bp, |
334 | struct bnx2x_vlan_mac_obj *obj, | |
335 | atomic_t *counter) | |
8db573ba | 336 | { |
2dc33bbc YM |
337 | struct list_head *pos; |
338 | int read_lock; | |
339 | int cnt = 0; | |
8b09be5f | 340 | |
2dc33bbc YM |
341 | read_lock = bnx2x_vlan_mac_h_read_lock(bp, obj); |
342 | if (read_lock) | |
343 | DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n"); | |
290ca2bb | 344 | |
2dc33bbc YM |
345 | list_for_each(pos, &obj->head) |
346 | cnt++; | |
290ca2bb | 347 | |
2dc33bbc YM |
348 | if (!read_lock) |
349 | bnx2x_vlan_mac_h_read_unlock(bp, obj); | |
8b09be5f | 350 | |
2dc33bbc | 351 | atomic_set(counter, cnt); |
8db573ba | 352 | } |
290ca2bb | 353 | |
2dc33bbc | 354 | static int bnx2x_vf_vlan_mac_clear(struct bnx2x *bp, struct bnx2x_virtf *vf, |
05cc5a39 | 355 | int qid, bool drv_only, int type) |
8db573ba | 356 | { |
2dc33bbc YM |
357 | struct bnx2x_vlan_mac_ramrod_params ramrod; |
358 | int rc; | |
290ca2bb | 359 | |
2dc33bbc | 360 | DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid, |
05cc5a39 YM |
361 | (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" : |
362 | (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs"); | |
290ca2bb | 363 | |
2dc33bbc YM |
364 | /* Prepare ramrod params */ |
365 | memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); | |
05cc5a39 YM |
366 | if (type == BNX2X_VF_FILTER_VLAN_MAC) { |
367 | set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); | |
368 | ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj); | |
369 | } else if (type == BNX2X_VF_FILTER_MAC) { | |
2dc33bbc YM |
370 | set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); |
371 | ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); | |
372 | } else { | |
2dc33bbc | 373 | ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); |
290ca2bb | 374 | } |
2dc33bbc | 375 | ramrod.user_req.cmd = BNX2X_VLAN_MAC_DEL; |
8db573ba | 376 | |
2dc33bbc YM |
377 | set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); |
378 | if (drv_only) | |
379 | set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); | |
380 | else | |
381 | set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); | |
8db573ba | 382 | |
2dc33bbc YM |
383 | /* Start deleting */ |
384 | rc = ramrod.vlan_mac_obj->delete_all(bp, | |
385 | ramrod.vlan_mac_obj, | |
386 | &ramrod.user_req.vlan_mac_flags, | |
387 | &ramrod.ramrod_flags); | |
388 | if (rc) { | |
389 | BNX2X_ERR("Failed to delete all %s\n", | |
05cc5a39 YM |
390 | (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" : |
391 | (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs"); | |
2dc33bbc | 392 | return rc; |
290ca2bb | 393 | } |
290ca2bb | 394 | |
2dc33bbc | 395 | return 0; |
954ea748 AE |
396 | } |
397 | ||
2dc33bbc YM |
398 | static int bnx2x_vf_mac_vlan_config(struct bnx2x *bp, |
399 | struct bnx2x_virtf *vf, int qid, | |
400 | struct bnx2x_vf_mac_vlan_filter *filter, | |
401 | bool drv_only) | |
463a68a7 | 402 | { |
2dc33bbc YM |
403 | struct bnx2x_vlan_mac_ramrod_params ramrod; |
404 | int rc; | |
463a68a7 | 405 | |
2dc33bbc YM |
406 | DP(BNX2X_MSG_IOV, "vf[%d] - %s a %s filter\n", |
407 | vf->abs_vfid, filter->add ? "Adding" : "Deleting", | |
05cc5a39 YM |
408 | (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MAC" : |
409 | (filter->type == BNX2X_VF_FILTER_MAC) ? "MAC" : "VLAN"); | |
2dc33bbc YM |
410 | |
411 | /* Prepare ramrod params */ | |
412 | memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); | |
05cc5a39 YM |
413 | if (filter->type == BNX2X_VF_FILTER_VLAN_MAC) { |
414 | ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj); | |
415 | ramrod.user_req.u.vlan.vlan = filter->vid; | |
416 | memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN); | |
417 | set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); | |
418 | } else if (filter->type == BNX2X_VF_FILTER_VLAN) { | |
2dc33bbc YM |
419 | ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); |
420 | ramrod.user_req.u.vlan.vlan = filter->vid; | |
421 | } else { | |
422 | set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); | |
423 | ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); | |
424 | memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN); | |
425 | } | |
426 | ramrod.user_req.cmd = filter->add ? BNX2X_VLAN_MAC_ADD : | |
427 | BNX2X_VLAN_MAC_DEL; | |
428 | ||
2dc33bbc YM |
429 | set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); |
430 | if (drv_only) | |
431 | set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); | |
432 | else | |
433 | set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); | |
434 | ||
435 | /* Add/Remove the filter */ | |
436 | rc = bnx2x_config_vlan_mac(bp, &ramrod); | |
78d55054 MS |
437 | if (rc == -EEXIST) |
438 | return 0; | |
439 | if (rc) { | |
2dc33bbc YM |
440 | BNX2X_ERR("Failed to %s %s\n", |
441 | filter->add ? "add" : "delete", | |
05cc5a39 YM |
442 | (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ? |
443 | "VLAN-MAC" : | |
444 | (filter->type == BNX2X_VF_FILTER_MAC) ? | |
445 | "MAC" : "VLAN"); | |
2dc33bbc | 446 | return rc; |
954ea748 | 447 | } |
3a3534ec | 448 | |
78d55054 MS |
449 | filter->applied = true; |
450 | ||
2dc33bbc | 451 | return 0; |
8db573ba | 452 | } |
290ca2bb | 453 | |
2dc33bbc YM |
454 | int bnx2x_vf_mac_vlan_config_list(struct bnx2x *bp, struct bnx2x_virtf *vf, |
455 | struct bnx2x_vf_mac_vlan_filters *filters, | |
456 | int qid, bool drv_only) | |
463a68a7 | 457 | { |
2dc33bbc | 458 | int rc = 0, i; |
463a68a7 | 459 | |
2dc33bbc | 460 | DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); |
3a3534ec YM |
461 | |
462 | if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) | |
463 | return -EINVAL; | |
954ea748 | 464 | |
2dc33bbc YM |
465 | /* Prepare ramrod params */ |
466 | for (i = 0; i < filters->count; i++) { | |
467 | rc = bnx2x_vf_mac_vlan_config(bp, vf, qid, | |
468 | &filters->filters[i], drv_only); | |
469 | if (rc) | |
470 | break; | |
954ea748 | 471 | } |
290ca2bb | 472 | |
2dc33bbc YM |
473 | /* Rollback if needed */ |
474 | if (i != filters->count) { | |
475 | BNX2X_ERR("Managed only %d/%d filters - rolling back\n", | |
74bcbeb7 | 476 | i, filters->count); |
2dc33bbc | 477 | while (--i >= 0) { |
78d55054 MS |
478 | if (!filters->filters[i].applied) |
479 | continue; | |
2dc33bbc YM |
480 | filters->filters[i].add = !filters->filters[i].add; |
481 | bnx2x_vf_mac_vlan_config(bp, vf, qid, | |
482 | &filters->filters[i], | |
483 | drv_only); | |
484 | } | |
290ca2bb | 485 | } |
8db573ba | 486 | |
2dc33bbc YM |
487 | /* It's our responsibility to free the filters */ |
488 | kfree(filters); | |
8db573ba | 489 | |
2dc33bbc | 490 | return rc; |
290ca2bb | 491 | } |
8db573ba | 492 | |
2dc33bbc YM |
493 | int bnx2x_vf_queue_setup(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid, |
494 | struct bnx2x_vf_queue_construct_params *qctor) | |
d16132ce | 495 | { |
2dc33bbc | 496 | int rc; |
d16132ce | 497 | |
2dc33bbc | 498 | DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); |
d16132ce | 499 | |
2dc33bbc YM |
500 | rc = bnx2x_vf_queue_create(bp, vf, qid, qctor); |
501 | if (rc) | |
d16132ce AE |
502 | goto op_err; |
503 | ||
2dc33bbc | 504 | /* Schedule the configuration of any pending vlan filters */ |
2dc33bbc YM |
505 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_HYPERVISOR_VLAN, |
506 | BNX2X_MSG_IOV); | |
507 | return 0; | |
d16132ce | 508 | op_err: |
2dc33bbc YM |
509 | BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); |
510 | return rc; | |
d16132ce AE |
511 | } |
512 | ||
2dc33bbc | 513 | static int bnx2x_vf_queue_flr(struct bnx2x *bp, struct bnx2x_virtf *vf, |
d16132ce AE |
514 | int qid) |
515 | { | |
2dc33bbc | 516 | int rc; |
954ea748 | 517 | |
2dc33bbc | 518 | DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); |
954ea748 | 519 | |
2dc33bbc YM |
520 | /* If needed, clean the filtering data base */ |
521 | if ((qid == LEADING_IDX) && | |
522 | bnx2x_validate_vf_sp_objs(bp, vf, false)) { | |
05cc5a39 YM |
523 | rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, |
524 | BNX2X_VF_FILTER_VLAN_MAC); | |
525 | if (rc) | |
526 | goto op_err; | |
527 | rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, | |
528 | BNX2X_VF_FILTER_VLAN); | |
2dc33bbc YM |
529 | if (rc) |
530 | goto op_err; | |
05cc5a39 YM |
531 | rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, |
532 | BNX2X_VF_FILTER_MAC); | |
2dc33bbc YM |
533 | if (rc) |
534 | goto op_err; | |
535 | } | |
954ea748 | 536 | |
2dc33bbc YM |
537 | /* Terminate queue */ |
538 | if (bnx2x_vfq(vf, qid, sp_obj).state != BNX2X_Q_STATE_RESET) { | |
539 | struct bnx2x_queue_state_params qstate; | |
858f4deb | 540 | |
2dc33bbc YM |
541 | memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); |
542 | qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); | |
543 | qstate.q_obj->state = BNX2X_Q_STATE_STOPPED; | |
544 | qstate.cmd = BNX2X_Q_CMD_TERMINATE; | |
545 | set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); | |
546 | rc = bnx2x_queue_state_change(bp, &qstate); | |
547 | if (rc) | |
548 | goto op_err; | |
954ea748 | 549 | } |
954ea748 | 550 | |
2dc33bbc YM |
551 | return 0; |
552 | op_err: | |
553 | BNX2X_ERR("vf[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); | |
554 | return rc; | |
954ea748 AE |
555 | } |
556 | ||
2dc33bbc YM |
557 | int bnx2x_vf_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf, |
558 | bnx2x_mac_addr_t *mcasts, int mc_num, bool drv_only) | |
954ea748 | 559 | { |
2dc33bbc YM |
560 | struct bnx2x_mcast_list_elem *mc = NULL; |
561 | struct bnx2x_mcast_ramrod_params mcast; | |
562 | int rc, i; | |
954ea748 | 563 | |
2dc33bbc | 564 | DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); |
954ea748 | 565 | |
2dc33bbc YM |
566 | /* Prepare Multicast command */ |
567 | memset(&mcast, 0, sizeof(struct bnx2x_mcast_ramrod_params)); | |
568 | mcast.mcast_obj = &vf->mcast_obj; | |
569 | if (drv_only) | |
570 | set_bit(RAMROD_DRV_CLR_ONLY, &mcast.ramrod_flags); | |
571 | else | |
572 | set_bit(RAMROD_COMP_WAIT, &mcast.ramrod_flags); | |
573 | if (mc_num) { | |
574 | mc = kzalloc(mc_num * sizeof(struct bnx2x_mcast_list_elem), | |
575 | GFP_KERNEL); | |
576 | if (!mc) { | |
d939be3a | 577 | BNX2X_ERR("Cannot Configure multicasts due to lack of memory\n"); |
2dc33bbc YM |
578 | return -ENOMEM; |
579 | } | |
580 | } | |
954ea748 | 581 | |
2dc33bbc YM |
582 | if (mc_num) { |
583 | INIT_LIST_HEAD(&mcast.mcast_list); | |
584 | for (i = 0; i < mc_num; i++) { | |
585 | mc[i].mac = mcasts[i]; | |
586 | list_add_tail(&mc[i].link, | |
587 | &mcast.mcast_list); | |
588 | } | |
954ea748 | 589 | |
2dc33bbc | 590 | /* add new mcasts */ |
ab15f86b | 591 | mcast.mcast_list_len = mc_num; |
c7b7b483 | 592 | rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_SET); |
2dc33bbc | 593 | if (rc) |
9165dabb | 594 | BNX2X_ERR("Failed to set multicasts\n"); |
c7b7b483 YM |
595 | } else { |
596 | /* clear existing mcasts */ | |
597 | rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_DEL); | |
598 | if (rc) | |
599 | BNX2X_ERR("Failed to remove multicasts\n"); | |
954ea748 | 600 | } |
2dc33bbc | 601 | |
c7b7b483 YM |
602 | kfree(mc); |
603 | ||
2dc33bbc | 604 | return rc; |
954ea748 AE |
605 | } |
606 | ||
e8379c79 YM |
607 | static void bnx2x_vf_prep_rx_mode(struct bnx2x *bp, u8 qid, |
608 | struct bnx2x_rx_mode_ramrod_params *ramrod, | |
609 | struct bnx2x_virtf *vf, | |
610 | unsigned long accept_flags) | |
611 | { | |
612 | struct bnx2x_vf_queue *vfq = vfq_get(vf, qid); | |
613 | ||
614 | memset(ramrod, 0, sizeof(*ramrod)); | |
615 | ramrod->cid = vfq->cid; | |
616 | ramrod->cl_id = vfq_cl_id(vf, vfq); | |
617 | ramrod->rx_mode_obj = &bp->rx_mode_obj; | |
618 | ramrod->func_id = FW_VF_HANDLE(vf->abs_vfid); | |
619 | ramrod->rx_accept_flags = accept_flags; | |
620 | ramrod->tx_accept_flags = accept_flags; | |
621 | ramrod->pstate = &vf->filter_state; | |
622 | ramrod->state = BNX2X_FILTER_RX_MODE_PENDING; | |
623 | ||
624 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); | |
625 | set_bit(RAMROD_RX, &ramrod->ramrod_flags); | |
626 | set_bit(RAMROD_TX, &ramrod->ramrod_flags); | |
627 | ||
628 | ramrod->rdata = bnx2x_vf_sp(bp, vf, rx_mode_rdata.e2); | |
629 | ramrod->rdata_mapping = bnx2x_vf_sp_map(bp, vf, rx_mode_rdata.e2); | |
630 | } | |
631 | ||
2dc33bbc YM |
632 | int bnx2x_vf_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf, |
633 | int qid, unsigned long accept_flags) | |
954ea748 | 634 | { |
2dc33bbc | 635 | struct bnx2x_rx_mode_ramrod_params ramrod; |
954ea748 | 636 | |
2dc33bbc | 637 | DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); |
954ea748 | 638 | |
2dc33bbc YM |
639 | bnx2x_vf_prep_rx_mode(bp, qid, &ramrod, vf, accept_flags); |
640 | set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); | |
641 | vfq_get(vf, qid)->accept_flags = ramrod.rx_accept_flags; | |
642 | return bnx2x_config_rx_mode(bp, &ramrod); | |
954ea748 AE |
643 | } |
644 | ||
2dc33bbc | 645 | int bnx2x_vf_queue_teardown(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid) |
463a68a7 | 646 | { |
2dc33bbc | 647 | int rc; |
463a68a7 | 648 | |
2dc33bbc | 649 | DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); |
858f4deb | 650 | |
2dc33bbc YM |
651 | /* Remove all classification configuration for leading queue */ |
652 | if (qid == LEADING_IDX) { | |
653 | rc = bnx2x_vf_rxmode(bp, vf, qid, 0); | |
654 | if (rc) | |
463a68a7 | 655 | goto op_err; |
463a68a7 | 656 | |
2dc33bbc YM |
657 | /* Remove filtering if feasible */ |
658 | if (bnx2x_validate_vf_sp_objs(bp, vf, true)) { | |
659 | rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, | |
05cc5a39 YM |
660 | false, |
661 | BNX2X_VF_FILTER_VLAN_MAC); | |
662 | if (rc) | |
663 | goto op_err; | |
664 | rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, | |
665 | false, | |
666 | BNX2X_VF_FILTER_VLAN); | |
2dc33bbc YM |
667 | if (rc) |
668 | goto op_err; | |
669 | rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, | |
05cc5a39 YM |
670 | false, |
671 | BNX2X_VF_FILTER_MAC); | |
2dc33bbc YM |
672 | if (rc) |
673 | goto op_err; | |
674 | rc = bnx2x_vf_mcast(bp, vf, NULL, 0, false); | |
675 | if (rc) | |
676 | goto op_err; | |
677 | } | |
463a68a7 AE |
678 | } |
679 | ||
2dc33bbc YM |
680 | /* Destroy queue */ |
681 | rc = bnx2x_vf_queue_destroy(bp, vf, qid); | |
682 | if (rc) | |
683 | goto op_err; | |
684 | return rc; | |
685 | op_err: | |
686 | BNX2X_ERR("vf[%d:%d] error: rc %d\n", | |
687 | vf->abs_vfid, qid, rc); | |
688 | return rc; | |
463a68a7 AE |
689 | } |
690 | ||
b56e9670 AE |
691 | /* VF enable primitives |
692 | * when pretend is required the caller is responsible | |
693 | * for calling pretend prior to calling these routines | |
694 | */ | |
695 | ||
b56e9670 | 696 | /* internal vf enable - until vf is enabled internally all transactions |
16a5fd92 | 697 | * are blocked. This routine should always be called last with pretend. |
b56e9670 AE |
698 | */ |
699 | static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable) | |
700 | { | |
701 | REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0); | |
702 | } | |
703 | ||
704 | /* clears vf error in all semi blocks */ | |
705 | static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid) | |
706 | { | |
707 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid); | |
708 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid); | |
709 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid); | |
710 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid); | |
711 | } | |
712 | ||
713 | static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid) | |
714 | { | |
715 | u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5; | |
716 | u32 was_err_reg = 0; | |
717 | ||
718 | switch (was_err_group) { | |
719 | case 0: | |
720 | was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR; | |
721 | break; | |
722 | case 1: | |
723 | was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR; | |
724 | break; | |
725 | case 2: | |
726 | was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR; | |
727 | break; | |
728 | case 3: | |
729 | was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR; | |
730 | break; | |
731 | } | |
732 | REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f)); | |
733 | } | |
734 | ||
b93288d5 AE |
735 | static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf) |
736 | { | |
737 | int i; | |
738 | u32 val; | |
739 | ||
740 | /* Set VF masks and configuration - pretend */ | |
741 | bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); | |
742 | ||
743 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
744 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
745 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
746 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
747 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
748 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
749 | ||
750 | val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); | |
751 | val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN); | |
b93288d5 | 752 | val &= ~IGU_VF_CONF_PARENT_MASK; |
656493d6 | 753 | val |= (BP_ABS_FUNC(bp) >> 1) << IGU_VF_CONF_PARENT_SHIFT; |
b93288d5 AE |
754 | REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); |
755 | ||
756 | DP(BNX2X_MSG_IOV, | |
656493d6 YM |
757 | "value in IGU_REG_VF_CONFIGURATION of vf %d after write is 0x%08x\n", |
758 | vf->abs_vfid, val); | |
b93288d5 AE |
759 | |
760 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
761 | ||
762 | /* iterate over all queues, clear sb consumer */ | |
763 | for (i = 0; i < vf_sb_count(vf); i++) { | |
764 | u8 igu_sb_id = vf_igu_sb(vf, i); | |
765 | ||
766 | /* zero prod memory */ | |
767 | REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0); | |
768 | ||
769 | /* clear sb state machine */ | |
770 | bnx2x_igu_clear_sb_gen(bp, vf->abs_vfid, igu_sb_id, | |
771 | false /* VF */); | |
772 | ||
773 | /* disable + update */ | |
774 | bnx2x_vf_igu_ack_sb(bp, vf, igu_sb_id, USTORM_ID, 0, | |
775 | IGU_INT_DISABLE, 1); | |
776 | } | |
777 | } | |
778 | ||
b56e9670 AE |
779 | void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid) |
780 | { | |
781 | /* set the VF-PF association in the FW */ | |
782 | storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp)); | |
783 | storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1); | |
784 | ||
785 | /* clear vf errors*/ | |
786 | bnx2x_vf_semi_clear_err(bp, abs_vfid); | |
787 | bnx2x_vf_pglue_clear_err(bp, abs_vfid); | |
788 | ||
789 | /* internal vf-enable - pretend */ | |
790 | bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid)); | |
791 | DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid); | |
792 | bnx2x_vf_enable_internal(bp, true); | |
793 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
794 | } | |
795 | ||
b93288d5 AE |
796 | static void bnx2x_vf_enable_traffic(struct bnx2x *bp, struct bnx2x_virtf *vf) |
797 | { | |
798 | /* Reset vf in IGU interrupts are still disabled */ | |
799 | bnx2x_vf_igu_reset(bp, vf); | |
800 | ||
801 | /* pretend to enable the vf with the PBF */ | |
802 | bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); | |
803 | REG_WR(bp, PBF_REG_DISABLE_VF, 0); | |
804 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
805 | } | |
806 | ||
b56e9670 AE |
807 | static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid) |
808 | { | |
809 | struct pci_dev *dev; | |
810 | struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); | |
811 | ||
812 | if (!vf) | |
78c3bcc5 | 813 | return false; |
b56e9670 AE |
814 | |
815 | dev = pci_get_bus_and_slot(vf->bus, vf->devfn); | |
816 | if (dev) | |
817 | return bnx2x_is_pcie_pending(dev); | |
b56e9670 AE |
818 | return false; |
819 | } | |
820 | ||
821 | int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid) | |
822 | { | |
b56e9670 AE |
823 | /* Verify no pending pci transactions */ |
824 | if (bnx2x_vf_is_pcie_pending(bp, abs_vfid)) | |
825 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
826 | ||
827 | return 0; | |
828 | } | |
829 | ||
830 | /* must be called after the number of PF queues and the number of VFs are | |
831 | * both known | |
832 | */ | |
833 | static void | |
b9871bcf | 834 | bnx2x_iov_static_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) |
b56e9670 | 835 | { |
b9871bcf | 836 | struct vf_pf_resc_request *resc = &vf->alloc_resc; |
b56e9670 AE |
837 | |
838 | /* will be set only during VF-ACQUIRE */ | |
839 | resc->num_rxqs = 0; | |
840 | resc->num_txqs = 0; | |
841 | ||
05cc5a39 YM |
842 | resc->num_mac_filters = VF_MAC_CREDIT_CNT; |
843 | resc->num_vlan_filters = VF_VLAN_CREDIT_CNT; | |
b56e9670 AE |
844 | |
845 | /* no real limitation */ | |
846 | resc->num_mc_filters = 0; | |
847 | ||
848 | /* num_sbs already set */ | |
b9871bcf | 849 | resc->num_sbs = vf->sb_count; |
b56e9670 AE |
850 | } |
851 | ||
f1929b01 AE |
852 | /* FLR routines: */ |
853 | static void bnx2x_vf_free_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) | |
854 | { | |
855 | /* reset the state variables */ | |
b9871bcf | 856 | bnx2x_iov_static_resc(bp, vf); |
f1929b01 AE |
857 | vf->state = VF_FREE; |
858 | } | |
859 | ||
d16132ce AE |
860 | static void bnx2x_vf_flr_clnup_hw(struct bnx2x *bp, struct bnx2x_virtf *vf) |
861 | { | |
862 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
863 | ||
864 | /* DQ usage counter */ | |
865 | bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); | |
866 | bnx2x_flr_clnup_poll_hw_counter(bp, DORQ_REG_VF_USAGE_CNT, | |
867 | "DQ VF usage counter timed out", | |
868 | poll_cnt); | |
869 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
870 | ||
871 | /* FW cleanup command - poll for the results */ | |
872 | if (bnx2x_send_final_clnup(bp, (u8)FW_VF_HANDLE(vf->abs_vfid), | |
873 | poll_cnt)) | |
874 | BNX2X_ERR("VF[%d] Final cleanup timed-out\n", vf->abs_vfid); | |
875 | ||
876 | /* verify TX hw is flushed */ | |
877 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
878 | } | |
879 | ||
2dc33bbc | 880 | static void bnx2x_vf_flr(struct bnx2x *bp, struct bnx2x_virtf *vf) |
d16132ce | 881 | { |
2dc33bbc | 882 | int rc, i; |
d16132ce | 883 | |
2dc33bbc | 884 | DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); |
d16132ce | 885 | |
2dc33bbc YM |
886 | /* the cleanup operations are valid if and only if the VF |
887 | * was first acquired. | |
888 | */ | |
889 | for (i = 0; i < vf_rxq_count(vf); i++) { | |
890 | rc = bnx2x_vf_queue_flr(bp, vf, i); | |
891 | if (rc) | |
892 | goto out; | |
893 | } | |
d16132ce | 894 | |
2dc33bbc YM |
895 | /* remove multicasts */ |
896 | bnx2x_vf_mcast(bp, vf, NULL, 0, true); | |
d16132ce | 897 | |
2dc33bbc YM |
898 | /* dispatch final cleanup and wait for HW queues to flush */ |
899 | bnx2x_vf_flr_clnup_hw(bp, vf); | |
d16132ce | 900 | |
2dc33bbc YM |
901 | /* release VF resources */ |
902 | bnx2x_vf_free_resc(bp, vf); | |
d16132ce | 903 | |
2dc33bbc YM |
904 | /* re-open the mailbox */ |
905 | bnx2x_vf_enable_mbx(bp, vf->abs_vfid); | |
906 | return; | |
907 | out: | |
908 | BNX2X_ERR("vf[%d:%d] failed flr: rc %d\n", | |
909 | vf->abs_vfid, i, rc); | |
d16132ce AE |
910 | } |
911 | ||
2dc33bbc | 912 | static void bnx2x_vf_flr_clnup(struct bnx2x *bp) |
d16132ce | 913 | { |
d16132ce | 914 | struct bnx2x_virtf *vf; |
2dc33bbc | 915 | int i; |
d16132ce | 916 | |
2dc33bbc YM |
917 | for (i = 0; i < BNX2X_NR_VIRTFN(bp); i++) { |
918 | /* VF should be RESET & in FLR cleanup states */ | |
919 | if (bnx2x_vf(bp, i, state) != VF_RESET || | |
920 | !bnx2x_vf(bp, i, flr_clnup_stage)) | |
921 | continue; | |
d16132ce | 922 | |
2dc33bbc YM |
923 | DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n", |
924 | i, BNX2X_NR_VIRTFN(bp)); | |
d16132ce | 925 | |
d16132ce AE |
926 | vf = BP_VF(bp, i); |
927 | ||
928 | /* lock the vf pf channel */ | |
929 | bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); | |
930 | ||
931 | /* invoke the VF FLR SM */ | |
2dc33bbc | 932 | bnx2x_vf_flr(bp, vf); |
d16132ce | 933 | |
2dc33bbc YM |
934 | /* mark the VF to be ACKED and continue */ |
935 | vf->flr_clnup_stage = false; | |
936 | bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); | |
d16132ce AE |
937 | } |
938 | ||
939 | /* Acknowledge the handled VFs. | |
940 | * we are acknowledge all the vfs which an flr was requested for, even | |
941 | * if amongst them there are such that we never opened, since the mcp | |
942 | * will interrupt us immediately again if we only ack some of the bits, | |
943 | * resulting in an endless loop. This can happen for example in KVM | |
944 | * where an 'all ones' flr request is sometimes given by hyper visor | |
945 | */ | |
946 | DP(BNX2X_MSG_MCP, "DRV_STATUS_VF_DISABLED ACK for vfs 0x%x 0x%x\n", | |
947 | bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); | |
948 | for (i = 0; i < FLRD_VFS_DWORDS; i++) | |
949 | SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], | |
950 | bp->vfdb->flrd_vfs[i]); | |
951 | ||
952 | bnx2x_fw_command(bp, DRV_MSG_CODE_VF_DISABLED_DONE, 0); | |
953 | ||
954 | /* clear the acked bits - better yet if the MCP implemented | |
955 | * write to clear semantics | |
956 | */ | |
957 | for (i = 0; i < FLRD_VFS_DWORDS; i++) | |
958 | SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 0); | |
959 | } | |
960 | ||
961 | void bnx2x_vf_handle_flr_event(struct bnx2x *bp) | |
962 | { | |
963 | int i; | |
964 | ||
965 | /* Read FLR'd VFs */ | |
966 | for (i = 0; i < FLRD_VFS_DWORDS; i++) | |
967 | bp->vfdb->flrd_vfs[i] = SHMEM2_RD(bp, mcp_vf_disabled[i]); | |
968 | ||
969 | DP(BNX2X_MSG_MCP, | |
970 | "DRV_STATUS_VF_DISABLED received for vfs 0x%x 0x%x\n", | |
971 | bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); | |
972 | ||
973 | for_each_vf(bp, i) { | |
974 | struct bnx2x_virtf *vf = BP_VF(bp, i); | |
975 | u32 reset = 0; | |
976 | ||
977 | if (vf->abs_vfid < 32) | |
978 | reset = bp->vfdb->flrd_vfs[0] & (1 << vf->abs_vfid); | |
979 | else | |
980 | reset = bp->vfdb->flrd_vfs[1] & | |
981 | (1 << (vf->abs_vfid - 32)); | |
982 | ||
983 | if (reset) { | |
984 | /* set as reset and ready for cleanup */ | |
985 | vf->state = VF_RESET; | |
2dc33bbc | 986 | vf->flr_clnup_stage = true; |
d16132ce AE |
987 | |
988 | DP(BNX2X_MSG_IOV, | |
989 | "Initiating Final cleanup for VF %d\n", | |
990 | vf->abs_vfid); | |
991 | } | |
992 | } | |
993 | ||
994 | /* do the FLR cleanup for all marked VFs*/ | |
2dc33bbc | 995 | bnx2x_vf_flr_clnup(bp); |
d16132ce AE |
996 | } |
997 | ||
b56e9670 AE |
998 | /* IOV global initialization routines */ |
999 | void bnx2x_iov_init_dq(struct bnx2x *bp) | |
1000 | { | |
1001 | if (!IS_SRIOV(bp)) | |
1002 | return; | |
1003 | ||
1004 | /* Set the DQ such that the CID reflect the abs_vfid */ | |
1005 | REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0); | |
1006 | REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS)); | |
1007 | ||
1008 | /* Set VFs starting CID. If its > 0 the preceding CIDs are belong to | |
1009 | * the PF L2 queues | |
1010 | */ | |
1011 | REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID); | |
1012 | ||
1013 | /* The VF window size is the log2 of the max number of CIDs per VF */ | |
1014 | REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND); | |
1015 | ||
1016 | /* The VF doorbell size 0 - *B, 4 - 128B. We set it here to match | |
1017 | * the Pf doorbell size although the 2 are independent. | |
1018 | */ | |
b9871bcf | 1019 | REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3); |
b56e9670 AE |
1020 | |
1021 | /* No security checks for now - | |
1022 | * configure single rule (out of 16) mask = 0x1, value = 0x0, | |
1023 | * CID range 0 - 0x1ffff | |
1024 | */ | |
1025 | REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1); | |
1026 | REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0); | |
1027 | REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0); | |
1028 | REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff); | |
1029 | ||
f2cfa997 AE |
1030 | /* set the VF doorbell threshold. This threshold represents the amount |
1031 | * of doorbells allowed in the main DORQ fifo for a specific VF. | |
1032 | */ | |
1033 | REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64); | |
b56e9670 AE |
1034 | } |
1035 | ||
1036 | void bnx2x_iov_init_dmae(struct bnx2x *bp) | |
1037 | { | |
49baea88 AE |
1038 | if (pci_find_ext_capability(bp->pdev, PCI_EXT_CAP_ID_SRIOV)) |
1039 | REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0); | |
b56e9670 AE |
1040 | } |
1041 | ||
1042 | static int bnx2x_vf_bus(struct bnx2x *bp, int vfid) | |
1043 | { | |
1044 | struct pci_dev *dev = bp->pdev; | |
1045 | struct bnx2x_sriov *iov = &bp->vfdb->sriov; | |
1046 | ||
1047 | return dev->bus->number + ((dev->devfn + iov->offset + | |
1048 | iov->stride * vfid) >> 8); | |
1049 | } | |
1050 | ||
1051 | static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid) | |
1052 | { | |
1053 | struct pci_dev *dev = bp->pdev; | |
1054 | struct bnx2x_sriov *iov = &bp->vfdb->sriov; | |
1055 | ||
1056 | return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff; | |
1057 | } | |
1058 | ||
1059 | static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf) | |
1060 | { | |
1061 | int i, n; | |
1062 | struct pci_dev *dev = bp->pdev; | |
1063 | struct bnx2x_sriov *iov = &bp->vfdb->sriov; | |
1064 | ||
1065 | for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) { | |
1066 | u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i); | |
1067 | u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i); | |
1068 | ||
6411280a | 1069 | size /= iov->total; |
b56e9670 AE |
1070 | vf->bars[n].bar = start + size * vf->abs_vfid; |
1071 | vf->bars[n].size = size; | |
1072 | } | |
1073 | } | |
1074 | ||
8db573ba AE |
1075 | static int bnx2x_ari_enabled(struct pci_dev *dev) |
1076 | { | |
1077 | return dev->bus->self && dev->bus->self->ari_enabled; | |
1078 | } | |
1079 | ||
0d8de80f | 1080 | static int |
8db573ba AE |
1081 | bnx2x_get_vf_igu_cam_info(struct bnx2x *bp) |
1082 | { | |
1083 | int sb_id; | |
1084 | u32 val; | |
b9871bcf | 1085 | u8 fid, current_pf = 0; |
8db573ba AE |
1086 | |
1087 | /* IGU in normal mode - read CAM */ | |
1088 | for (sb_id = 0; sb_id < IGU_REG_MAPPING_MEMORY_SIZE; sb_id++) { | |
1089 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4); | |
1090 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
1091 | continue; | |
1092 | fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID); | |
b9871bcf AE |
1093 | if (fid & IGU_FID_ENCODE_IS_PF) |
1094 | current_pf = fid & IGU_FID_PF_NUM_MASK; | |
9ea75ded | 1095 | else if (current_pf == BP_FUNC(bp)) |
8db573ba AE |
1096 | bnx2x_vf_set_igu_info(bp, sb_id, |
1097 | (fid & IGU_FID_VF_NUM_MASK)); | |
8db573ba AE |
1098 | DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n", |
1099 | ((fid & IGU_FID_ENCODE_IS_PF) ? "PF" : "VF"), | |
1100 | ((fid & IGU_FID_ENCODE_IS_PF) ? (fid & IGU_FID_PF_NUM_MASK) : | |
1101 | (fid & IGU_FID_VF_NUM_MASK)), sb_id, | |
1102 | GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)); | |
1103 | } | |
b9871bcf | 1104 | DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool); |
0d8de80f | 1105 | return BP_VFDB(bp)->vf_sbs_pool; |
8db573ba AE |
1106 | } |
1107 | ||
1108 | static void __bnx2x_iov_free_vfdb(struct bnx2x *bp) | |
1109 | { | |
1110 | if (bp->vfdb) { | |
1111 | kfree(bp->vfdb->vfqs); | |
1112 | kfree(bp->vfdb->vfs); | |
1113 | kfree(bp->vfdb); | |
1114 | } | |
1115 | bp->vfdb = NULL; | |
1116 | } | |
1117 | ||
1118 | static int bnx2x_sriov_pci_cfg_info(struct bnx2x *bp, struct bnx2x_sriov *iov) | |
1119 | { | |
1120 | int pos; | |
1121 | struct pci_dev *dev = bp->pdev; | |
1122 | ||
1123 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); | |
1124 | if (!pos) { | |
1125 | BNX2X_ERR("failed to find SRIOV capability in device\n"); | |
1126 | return -ENODEV; | |
1127 | } | |
1128 | ||
1129 | iov->pos = pos; | |
1130 | DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos); | |
1131 | pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &iov->ctrl); | |
1132 | pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &iov->total); | |
1133 | pci_read_config_word(dev, pos + PCI_SRIOV_INITIAL_VF, &iov->initial); | |
1134 | pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &iov->offset); | |
1135 | pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &iov->stride); | |
1136 | pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz); | |
1137 | pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap); | |
1138 | pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | static int bnx2x_sriov_info(struct bnx2x *bp, struct bnx2x_sriov *iov) | |
1144 | { | |
1145 | u32 val; | |
1146 | ||
1147 | /* read the SRIOV capability structure | |
1148 | * The fields can be read via configuration read or | |
1149 | * directly from the device (starting at offset PCICFG_OFFSET) | |
1150 | */ | |
1151 | if (bnx2x_sriov_pci_cfg_info(bp, iov)) | |
1152 | return -ENODEV; | |
1153 | ||
1154 | /* get the number of SRIOV bars */ | |
1155 | iov->nres = 0; | |
1156 | ||
1157 | /* read the first_vfid */ | |
1158 | val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); | |
1159 | iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK) | |
1160 | * 8) - (BNX2X_MAX_NUM_OF_VFS * BP_PATH(bp)); | |
1161 | ||
1162 | DP(BNX2X_MSG_IOV, | |
1163 | "IOV info[%d]: first vf %d, nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n", | |
1164 | BP_FUNC(bp), | |
1165 | iov->first_vf_in_pf, iov->nres, iov->cap, iov->ctrl, iov->total, | |
1166 | iov->initial, iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz); | |
1167 | ||
1168 | return 0; | |
1169 | } | |
1170 | ||
8db573ba AE |
1171 | /* must be called after PF bars are mapped */ |
1172 | int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param, | |
b9871bcf | 1173 | int num_vfs_param) |
8db573ba | 1174 | { |
b9871bcf | 1175 | int err, i; |
8db573ba AE |
1176 | struct bnx2x_sriov *iov; |
1177 | struct pci_dev *dev = bp->pdev; | |
1178 | ||
1179 | bp->vfdb = NULL; | |
1180 | ||
1181 | /* verify is pf */ | |
1182 | if (IS_VF(bp)) | |
1183 | return 0; | |
1184 | ||
1185 | /* verify sriov capability is present in configuration space */ | |
1186 | if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV)) | |
1187 | return 0; | |
1188 | ||
1189 | /* verify chip revision */ | |
1190 | if (CHIP_IS_E1x(bp)) | |
1191 | return 0; | |
1192 | ||
1193 | /* check if SRIOV support is turned off */ | |
1194 | if (!num_vfs_param) | |
1195 | return 0; | |
1196 | ||
1197 | /* SRIOV assumes that num of PF CIDs < BNX2X_FIRST_VF_CID */ | |
1198 | if (BNX2X_L2_MAX_CID(bp) >= BNX2X_FIRST_VF_CID) { | |
1199 | BNX2X_ERR("PF cids %d are overspilling into vf space (starts at %d). Abort SRIOV\n", | |
1200 | BNX2X_L2_MAX_CID(bp), BNX2X_FIRST_VF_CID); | |
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | /* SRIOV can be enabled only with MSIX */ | |
1205 | if (int_mode_param == BNX2X_INT_MODE_MSI || | |
10938604 | 1206 | int_mode_param == BNX2X_INT_MODE_INTX) { |
8db573ba | 1207 | BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n"); |
10938604 AE |
1208 | return 0; |
1209 | } | |
8db573ba AE |
1210 | |
1211 | err = -EIO; | |
1212 | /* verify ari is enabled */ | |
1213 | if (!bnx2x_ari_enabled(bp->pdev)) { | |
10938604 AE |
1214 | BNX2X_ERR("ARI not supported (check pci bridge ARI forwarding), SRIOV can not be enabled\n"); |
1215 | return 0; | |
8db573ba AE |
1216 | } |
1217 | ||
1218 | /* verify igu is in normal mode */ | |
1219 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
1220 | BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n"); | |
10938604 | 1221 | return 0; |
8db573ba AE |
1222 | } |
1223 | ||
1224 | /* allocate the vfs database */ | |
1225 | bp->vfdb = kzalloc(sizeof(*(bp->vfdb)), GFP_KERNEL); | |
1226 | if (!bp->vfdb) { | |
1227 | BNX2X_ERR("failed to allocate vf database\n"); | |
1228 | err = -ENOMEM; | |
1229 | goto failed; | |
1230 | } | |
1231 | ||
1232 | /* get the sriov info - Linux already collected all the pertinent | |
1233 | * information, however the sriov structure is for the private use | |
1234 | * of the pci module. Also we want this information regardless | |
1235 | * of the hyper-visor. | |
1236 | */ | |
1237 | iov = &(bp->vfdb->sriov); | |
1238 | err = bnx2x_sriov_info(bp, iov); | |
1239 | if (err) | |
1240 | goto failed; | |
1241 | ||
1242 | /* SR-IOV capability was enabled but there are no VFs*/ | |
1243 | if (iov->total == 0) | |
1244 | goto failed; | |
1245 | ||
3c76feff AE |
1246 | iov->nr_virtfn = min_t(u16, iov->total, num_vfs_param); |
1247 | ||
1248 | DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n", | |
1249 | num_vfs_param, iov->nr_virtfn); | |
8db573ba AE |
1250 | |
1251 | /* allocate the vf array */ | |
1252 | bp->vfdb->vfs = kzalloc(sizeof(struct bnx2x_virtf) * | |
1253 | BNX2X_NR_VIRTFN(bp), GFP_KERNEL); | |
1254 | if (!bp->vfdb->vfs) { | |
1255 | BNX2X_ERR("failed to allocate vf array\n"); | |
1256 | err = -ENOMEM; | |
1257 | goto failed; | |
1258 | } | |
1259 | ||
1260 | /* Initial VF init - index and abs_vfid - nr_virtfn must be set */ | |
1261 | for_each_vf(bp, i) { | |
1262 | bnx2x_vf(bp, i, index) = i; | |
1263 | bnx2x_vf(bp, i, abs_vfid) = iov->first_vf_in_pf + i; | |
1264 | bnx2x_vf(bp, i, state) = VF_FREE; | |
8db573ba AE |
1265 | mutex_init(&bnx2x_vf(bp, i, op_mutex)); |
1266 | bnx2x_vf(bp, i, op_current) = CHANNEL_TLV_NONE; | |
1267 | } | |
1268 | ||
1269 | /* re-read the IGU CAM for VFs - index and abs_vfid must be set */ | |
0d8de80f YM |
1270 | if (!bnx2x_get_vf_igu_cam_info(bp)) { |
1271 | BNX2X_ERR("No entries in IGU CAM for vfs\n"); | |
1272 | err = -EINVAL; | |
1273 | goto failed; | |
1274 | } | |
8db573ba | 1275 | |
8db573ba | 1276 | /* allocate the queue arrays for all VFs */ |
b9871bcf AE |
1277 | bp->vfdb->vfqs = kzalloc( |
1278 | BNX2X_MAX_NUM_VF_QUEUES * sizeof(struct bnx2x_vf_queue), | |
1279 | GFP_KERNEL); | |
1280 | ||
8db573ba AE |
1281 | if (!bp->vfdb->vfqs) { |
1282 | BNX2X_ERR("failed to allocate vf queue array\n"); | |
1283 | err = -ENOMEM; | |
1284 | goto failed; | |
1285 | } | |
1286 | ||
370d4a26 YM |
1287 | /* Prepare the VFs event synchronization mechanism */ |
1288 | mutex_init(&bp->vfdb->event_mutex); | |
1289 | ||
6495d15a DK |
1290 | mutex_init(&bp->vfdb->bulletin_mutex); |
1291 | ||
230d00eb YM |
1292 | if (SHMEM2_HAS(bp, sriov_switch_mode)) |
1293 | SHMEM2_WR(bp, sriov_switch_mode, SRIOV_SWITCH_MODE_VEB); | |
1294 | ||
8db573ba AE |
1295 | return 0; |
1296 | failed: | |
1297 | DP(BNX2X_MSG_IOV, "Failed err=%d\n", err); | |
1298 | __bnx2x_iov_free_vfdb(bp); | |
1299 | return err; | |
1300 | } | |
1301 | ||
fd1fc79d AE |
1302 | void bnx2x_iov_remove_one(struct bnx2x *bp) |
1303 | { | |
826cb7b4 AE |
1304 | int vf_idx; |
1305 | ||
fd1fc79d AE |
1306 | /* if SRIOV is not enabled there's nothing to do */ |
1307 | if (!IS_SRIOV(bp)) | |
1308 | return; | |
1309 | ||
a345ce71 | 1310 | bnx2x_disable_sriov(bp); |
8395be5e | 1311 | |
826cb7b4 AE |
1312 | /* disable access to all VFs */ |
1313 | for (vf_idx = 0; vf_idx < bp->vfdb->sriov.total; vf_idx++) { | |
1314 | bnx2x_pretend_func(bp, | |
1315 | HW_VF_HANDLE(bp, | |
1316 | bp->vfdb->sriov.first_vf_in_pf + | |
1317 | vf_idx)); | |
1318 | DP(BNX2X_MSG_IOV, "disabling internal access for vf %d\n", | |
1319 | bp->vfdb->sriov.first_vf_in_pf + vf_idx); | |
1320 | bnx2x_vf_enable_internal(bp, 0); | |
1321 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
1322 | } | |
1323 | ||
fd1fc79d AE |
1324 | /* free vf database */ |
1325 | __bnx2x_iov_free_vfdb(bp); | |
1326 | } | |
1327 | ||
b56e9670 AE |
1328 | void bnx2x_iov_free_mem(struct bnx2x *bp) |
1329 | { | |
1330 | int i; | |
1331 | ||
1332 | if (!IS_SRIOV(bp)) | |
1333 | return; | |
1334 | ||
1335 | /* free vfs hw contexts */ | |
1336 | for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { | |
1337 | struct hw_dma *cxt = &bp->vfdb->context[i]; | |
1338 | BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size); | |
1339 | } | |
1340 | ||
1341 | BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr, | |
1342 | BP_VFDB(bp)->sp_dma.mapping, | |
1343 | BP_VFDB(bp)->sp_dma.size); | |
1344 | ||
1345 | BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr, | |
1346 | BP_VF_MBX_DMA(bp)->mapping, | |
1347 | BP_VF_MBX_DMA(bp)->size); | |
abc5a021 AE |
1348 | |
1349 | BNX2X_PCI_FREE(BP_VF_BULLETIN_DMA(bp)->addr, | |
1350 | BP_VF_BULLETIN_DMA(bp)->mapping, | |
1351 | BP_VF_BULLETIN_DMA(bp)->size); | |
b56e9670 AE |
1352 | } |
1353 | ||
1354 | int bnx2x_iov_alloc_mem(struct bnx2x *bp) | |
1355 | { | |
1356 | size_t tot_size; | |
1357 | int i, rc = 0; | |
1358 | ||
1359 | if (!IS_SRIOV(bp)) | |
1360 | return rc; | |
1361 | ||
1362 | /* allocate vfs hw contexts */ | |
1363 | tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) * | |
1364 | BNX2X_CIDS_PER_VF * sizeof(union cdu_context); | |
1365 | ||
1366 | for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { | |
1367 | struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i); | |
1368 | cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ); | |
1369 | ||
1370 | if (cxt->size) { | |
cd2b0389 JP |
1371 | cxt->addr = BNX2X_PCI_ALLOC(&cxt->mapping, cxt->size); |
1372 | if (!cxt->addr) | |
1373 | goto alloc_mem_err; | |
b56e9670 AE |
1374 | } else { |
1375 | cxt->addr = NULL; | |
1376 | cxt->mapping = 0; | |
1377 | } | |
1378 | tot_size -= cxt->size; | |
1379 | } | |
1380 | ||
1381 | /* allocate vfs ramrods dma memory - client_init and set_mac */ | |
1382 | tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp); | |
cd2b0389 JP |
1383 | BP_VFDB(bp)->sp_dma.addr = BNX2X_PCI_ALLOC(&BP_VFDB(bp)->sp_dma.mapping, |
1384 | tot_size); | |
1385 | if (!BP_VFDB(bp)->sp_dma.addr) | |
1386 | goto alloc_mem_err; | |
b56e9670 AE |
1387 | BP_VFDB(bp)->sp_dma.size = tot_size; |
1388 | ||
1389 | /* allocate mailboxes */ | |
1390 | tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE; | |
cd2b0389 JP |
1391 | BP_VF_MBX_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_MBX_DMA(bp)->mapping, |
1392 | tot_size); | |
1393 | if (!BP_VF_MBX_DMA(bp)->addr) | |
1394 | goto alloc_mem_err; | |
1395 | ||
b56e9670 AE |
1396 | BP_VF_MBX_DMA(bp)->size = tot_size; |
1397 | ||
abc5a021 AE |
1398 | /* allocate local bulletin boards */ |
1399 | tot_size = BNX2X_NR_VIRTFN(bp) * BULLETIN_CONTENT_SIZE; | |
cd2b0389 JP |
1400 | BP_VF_BULLETIN_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_BULLETIN_DMA(bp)->mapping, |
1401 | tot_size); | |
1402 | if (!BP_VF_BULLETIN_DMA(bp)->addr) | |
1403 | goto alloc_mem_err; | |
1404 | ||
abc5a021 AE |
1405 | BP_VF_BULLETIN_DMA(bp)->size = tot_size; |
1406 | ||
b56e9670 AE |
1407 | return 0; |
1408 | ||
1409 | alloc_mem_err: | |
1410 | return -ENOMEM; | |
1411 | } | |
1412 | ||
8ca5e17e AE |
1413 | static void bnx2x_vfq_init(struct bnx2x *bp, struct bnx2x_virtf *vf, |
1414 | struct bnx2x_vf_queue *q) | |
1415 | { | |
1416 | u8 cl_id = vfq_cl_id(vf, q); | |
1417 | u8 func_id = FW_VF_HANDLE(vf->abs_vfid); | |
1418 | unsigned long q_type = 0; | |
1419 | ||
1420 | set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
1421 | set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
1422 | ||
1423 | /* Queue State object */ | |
1424 | bnx2x_init_queue_obj(bp, &q->sp_obj, | |
1425 | cl_id, &q->cid, 1, func_id, | |
1426 | bnx2x_vf_sp(bp, vf, q_data), | |
1427 | bnx2x_vf_sp_map(bp, vf, q_data), | |
1428 | q_type); | |
1429 | ||
3a3534ec YM |
1430 | /* sp indication is set only when vlan/mac/etc. are initialized */ |
1431 | q->sp_initialized = false; | |
1432 | ||
8ca5e17e | 1433 | DP(BNX2X_MSG_IOV, |
b9871bcf AE |
1434 | "initialized vf %d's queue object. func id set to %d. cid set to 0x%x\n", |
1435 | vf->abs_vfid, q->sp_obj.func_id, q->cid); | |
8ca5e17e AE |
1436 | } |
1437 | ||
6495d15a DK |
1438 | static int bnx2x_max_speed_cap(struct bnx2x *bp) |
1439 | { | |
1440 | u32 supported = bp->port.supported[bnx2x_get_link_cfg_idx(bp)]; | |
1441 | ||
1442 | if (supported & | |
1443 | (SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full)) | |
1444 | return 20000; | |
1445 | ||
1446 | return 10000; /* assume lowest supported speed is 10G */ | |
1447 | } | |
1448 | ||
1449 | int bnx2x_iov_link_update_vf(struct bnx2x *bp, int idx) | |
1450 | { | |
1451 | struct bnx2x_link_report_data *state = &bp->last_reported_link; | |
1452 | struct pf_vf_bulletin_content *bulletin; | |
1453 | struct bnx2x_virtf *vf; | |
1454 | bool update = true; | |
1455 | int rc = 0; | |
1456 | ||
1457 | /* sanity and init */ | |
1458 | rc = bnx2x_vf_op_prep(bp, idx, &vf, &bulletin, false); | |
1459 | if (rc) | |
1460 | return rc; | |
1461 | ||
1462 | mutex_lock(&bp->vfdb->bulletin_mutex); | |
1463 | ||
1464 | if (vf->link_cfg == IFLA_VF_LINK_STATE_AUTO) { | |
1465 | bulletin->valid_bitmap |= 1 << LINK_VALID; | |
1466 | ||
1467 | bulletin->link_speed = state->line_speed; | |
1468 | bulletin->link_flags = 0; | |
1469 | if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN, | |
1470 | &state->link_report_flags)) | |
1471 | bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN; | |
1472 | if (test_bit(BNX2X_LINK_REPORT_FD, | |
1473 | &state->link_report_flags)) | |
1474 | bulletin->link_flags |= VFPF_LINK_REPORT_FULL_DUPLEX; | |
1475 | if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON, | |
1476 | &state->link_report_flags)) | |
1477 | bulletin->link_flags |= VFPF_LINK_REPORT_RX_FC_ON; | |
1478 | if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON, | |
1479 | &state->link_report_flags)) | |
1480 | bulletin->link_flags |= VFPF_LINK_REPORT_TX_FC_ON; | |
1481 | } else if (vf->link_cfg == IFLA_VF_LINK_STATE_DISABLE && | |
1482 | !(bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) { | |
1483 | bulletin->valid_bitmap |= 1 << LINK_VALID; | |
1484 | bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN; | |
1485 | } else if (vf->link_cfg == IFLA_VF_LINK_STATE_ENABLE && | |
1486 | (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) { | |
1487 | bulletin->valid_bitmap |= 1 << LINK_VALID; | |
1488 | bulletin->link_speed = bnx2x_max_speed_cap(bp); | |
1489 | bulletin->link_flags &= ~VFPF_LINK_REPORT_LINK_DOWN; | |
1490 | } else { | |
1491 | update = false; | |
1492 | } | |
1493 | ||
1494 | if (update) { | |
1495 | DP(NETIF_MSG_LINK | BNX2X_MSG_IOV, | |
1496 | "vf %d mode %u speed %d flags %x\n", idx, | |
1497 | vf->link_cfg, bulletin->link_speed, bulletin->link_flags); | |
1498 | ||
1499 | /* Post update on VF's bulletin board */ | |
1500 | rc = bnx2x_post_vf_bulletin(bp, idx); | |
1501 | if (rc) { | |
1502 | BNX2X_ERR("failed to update VF[%d] bulletin\n", idx); | |
1503 | goto out; | |
1504 | } | |
1505 | } | |
1506 | ||
1507 | out: | |
1508 | mutex_unlock(&bp->vfdb->bulletin_mutex); | |
1509 | return rc; | |
1510 | } | |
1511 | ||
1512 | int bnx2x_set_vf_link_state(struct net_device *dev, int idx, int link_state) | |
1513 | { | |
1514 | struct bnx2x *bp = netdev_priv(dev); | |
1515 | struct bnx2x_virtf *vf = BP_VF(bp, idx); | |
1516 | ||
1517 | if (!vf) | |
1518 | return -EINVAL; | |
1519 | ||
1520 | if (vf->link_cfg == link_state) | |
1521 | return 0; /* nothing todo */ | |
1522 | ||
1523 | vf->link_cfg = link_state; | |
1524 | ||
1525 | return bnx2x_iov_link_update_vf(bp, idx); | |
1526 | } | |
1527 | ||
1528 | void bnx2x_iov_link_update(struct bnx2x *bp) | |
1529 | { | |
1530 | int vfid; | |
1531 | ||
1532 | if (!IS_SRIOV(bp)) | |
1533 | return; | |
1534 | ||
1535 | for_each_vf(bp, vfid) | |
1536 | bnx2x_iov_link_update_vf(bp, vfid); | |
1537 | } | |
1538 | ||
b56e9670 AE |
1539 | /* called by bnx2x_nic_load */ |
1540 | int bnx2x_iov_nic_init(struct bnx2x *bp) | |
1541 | { | |
b9871bcf | 1542 | int vfid; |
b56e9670 AE |
1543 | |
1544 | if (!IS_SRIOV(bp)) { | |
1545 | DP(BNX2X_MSG_IOV, "vfdb was not allocated\n"); | |
1546 | return 0; | |
1547 | } | |
1548 | ||
1549 | DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn); | |
1550 | ||
03c22ea3 AE |
1551 | /* let FLR complete ... */ |
1552 | msleep(100); | |
1553 | ||
b56e9670 AE |
1554 | /* initialize vf database */ |
1555 | for_each_vf(bp, vfid) { | |
1556 | struct bnx2x_virtf *vf = BP_VF(bp, vfid); | |
1557 | ||
1558 | int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) * | |
1559 | BNX2X_CIDS_PER_VF; | |
1560 | ||
1561 | union cdu_context *base_cxt = (union cdu_context *) | |
1562 | BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + | |
1563 | (base_vf_cid & (ILT_PAGE_CIDS-1)); | |
1564 | ||
1565 | DP(BNX2X_MSG_IOV, | |
1566 | "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n", | |
1567 | vf->abs_vfid, vf_sb_count(vf), base_vf_cid, | |
1568 | BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt); | |
1569 | ||
1570 | /* init statically provisioned resources */ | |
b9871bcf | 1571 | bnx2x_iov_static_resc(bp, vf); |
b56e9670 AE |
1572 | |
1573 | /* queues are initialized during VF-ACQUIRE */ | |
b56e9670 AE |
1574 | vf->filter_state = 0; |
1575 | vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id); | |
1576 | ||
05cc5a39 YM |
1577 | bnx2x_init_credit_pool(&vf->vf_vlans_pool, 0, |
1578 | vf_vlan_rules_cnt(vf)); | |
1579 | bnx2x_init_credit_pool(&vf->vf_macs_pool, 0, | |
1580 | vf_mac_rules_cnt(vf)); | |
1581 | ||
b56e9670 AE |
1582 | /* init mcast object - This object will be re-initialized |
1583 | * during VF-ACQUIRE with the proper cl_id and cid. | |
1584 | * It needs to be initialized here so that it can be safely | |
1585 | * handled by a subsequent FLR flow. | |
1586 | */ | |
1587 | bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF, | |
1588 | 0xFF, 0xFF, 0xFF, | |
1589 | bnx2x_vf_sp(bp, vf, mcast_rdata), | |
1590 | bnx2x_vf_sp_map(bp, vf, mcast_rdata), | |
1591 | BNX2X_FILTER_MCAST_PENDING, | |
1592 | &vf->filter_state, | |
1593 | BNX2X_OBJ_TYPE_RX_TX); | |
1594 | ||
1595 | /* set the mailbox message addresses */ | |
1596 | BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *) | |
1597 | (((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid * | |
1598 | MBX_MSG_ALIGNED_SIZE); | |
1599 | ||
1600 | BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping + | |
1601 | vfid * MBX_MSG_ALIGNED_SIZE; | |
1602 | ||
1603 | /* Enable vf mailbox */ | |
1604 | bnx2x_vf_enable_mbx(bp, vf->abs_vfid); | |
1605 | } | |
1606 | ||
1607 | /* Final VF init */ | |
b9871bcf AE |
1608 | for_each_vf(bp, vfid) { |
1609 | struct bnx2x_virtf *vf = BP_VF(bp, vfid); | |
b56e9670 AE |
1610 | |
1611 | /* fill in the BDF and bars */ | |
b9871bcf AE |
1612 | vf->bus = bnx2x_vf_bus(bp, vfid); |
1613 | vf->devfn = bnx2x_vf_devfn(bp, vfid); | |
b56e9670 AE |
1614 | bnx2x_vf_set_bars(bp, vf); |
1615 | ||
1616 | DP(BNX2X_MSG_IOV, | |
1617 | "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n", | |
1618 | vf->abs_vfid, vf->bus, vf->devfn, | |
1619 | (unsigned)vf->bars[0].bar, vf->bars[0].size, | |
1620 | (unsigned)vf->bars[1].bar, vf->bars[1].size, | |
1621 | (unsigned)vf->bars[2].bar, vf->bars[2].size); | |
b56e9670 AE |
1622 | } |
1623 | ||
1624 | return 0; | |
1625 | } | |
290ca2bb | 1626 | |
f1929b01 AE |
1627 | /* called by bnx2x_chip_cleanup */ |
1628 | int bnx2x_iov_chip_cleanup(struct bnx2x *bp) | |
1629 | { | |
1630 | int i; | |
1631 | ||
1632 | if (!IS_SRIOV(bp)) | |
1633 | return 0; | |
1634 | ||
1635 | /* release all the VFs */ | |
1636 | for_each_vf(bp, i) | |
2dc33bbc | 1637 | bnx2x_vf_release(bp, BP_VF(bp, i)); |
f1929b01 AE |
1638 | |
1639 | return 0; | |
1640 | } | |
1641 | ||
290ca2bb AE |
1642 | /* called by bnx2x_init_hw_func, returns the next ilt line */ |
1643 | int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line) | |
1644 | { | |
1645 | int i; | |
1646 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
1647 | ||
1648 | if (!IS_SRIOV(bp)) | |
1649 | return line; | |
1650 | ||
1651 | /* set vfs ilt lines */ | |
1652 | for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { | |
1653 | struct hw_dma *hw_cxt = BP_VF_CXT_PAGE(bp, i); | |
1654 | ||
1655 | ilt->lines[line+i].page = hw_cxt->addr; | |
1656 | ilt->lines[line+i].page_mapping = hw_cxt->mapping; | |
1657 | ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */ | |
1658 | } | |
1659 | return line + i; | |
1660 | } | |
1661 | ||
fd1fc79d | 1662 | static u8 bnx2x_iov_is_vf_cid(struct bnx2x *bp, u16 cid) |
290ca2bb | 1663 | { |
fd1fc79d AE |
1664 | return ((cid >= BNX2X_FIRST_VF_CID) && |
1665 | ((cid - BNX2X_FIRST_VF_CID) < BNX2X_VF_CIDS)); | |
1666 | } | |
1667 | ||
1668 | static | |
1669 | void bnx2x_vf_handle_classification_eqe(struct bnx2x *bp, | |
1670 | struct bnx2x_vf_queue *vfq, | |
1671 | union event_ring_elem *elem) | |
1672 | { | |
1673 | unsigned long ramrod_flags = 0; | |
1674 | int rc = 0; | |
9cd753a1 | 1675 | u32 echo = le32_to_cpu(elem->message.data.eth_event.echo); |
fd1fc79d AE |
1676 | |
1677 | /* Always push next commands out, don't wait here */ | |
1678 | set_bit(RAMROD_CONT, &ramrod_flags); | |
1679 | ||
9cd753a1 | 1680 | switch (echo >> BNX2X_SWCID_SHIFT) { |
fd1fc79d AE |
1681 | case BNX2X_FILTER_MAC_PENDING: |
1682 | rc = vfq->mac_obj.complete(bp, &vfq->mac_obj, elem, | |
1683 | &ramrod_flags); | |
1684 | break; | |
1685 | case BNX2X_FILTER_VLAN_PENDING: | |
1686 | rc = vfq->vlan_obj.complete(bp, &vfq->vlan_obj, elem, | |
1687 | &ramrod_flags); | |
1688 | break; | |
1689 | default: | |
9cd753a1 | 1690 | BNX2X_ERR("Unsupported classification command: 0x%x\n", echo); |
fd1fc79d AE |
1691 | return; |
1692 | } | |
1693 | if (rc < 0) | |
1694 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
1695 | else if (rc > 0) | |
1696 | DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n"); | |
1697 | } | |
1698 | ||
1699 | static | |
1700 | void bnx2x_vf_handle_mcast_eqe(struct bnx2x *bp, | |
1701 | struct bnx2x_virtf *vf) | |
1702 | { | |
1703 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; | |
1704 | int rc; | |
1705 | ||
1706 | rparam.mcast_obj = &vf->mcast_obj; | |
1707 | vf->mcast_obj.raw.clear_pending(&vf->mcast_obj.raw); | |
1708 | ||
1709 | /* If there are pending mcast commands - send them */ | |
1710 | if (vf->mcast_obj.check_pending(&vf->mcast_obj)) { | |
1711 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
1712 | if (rc < 0) | |
1713 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
1714 | rc); | |
1715 | } | |
1716 | } | |
1717 | ||
1718 | static | |
1719 | void bnx2x_vf_handle_filters_eqe(struct bnx2x *bp, | |
1720 | struct bnx2x_virtf *vf) | |
1721 | { | |
4e857c58 | 1722 | smp_mb__before_atomic(); |
fd1fc79d | 1723 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); |
4e857c58 | 1724 | smp_mb__after_atomic(); |
fd1fc79d AE |
1725 | } |
1726 | ||
2dc33bbc YM |
1727 | static void bnx2x_vf_handle_rss_update_eqe(struct bnx2x *bp, |
1728 | struct bnx2x_virtf *vf) | |
1729 | { | |
1730 | vf->rss_conf_obj.raw.clear_pending(&vf->rss_conf_obj.raw); | |
1731 | } | |
1732 | ||
fd1fc79d AE |
1733 | int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem) |
1734 | { | |
1735 | struct bnx2x_virtf *vf; | |
1736 | int qidx = 0, abs_vfid; | |
1737 | u8 opcode; | |
1738 | u16 cid = 0xffff; | |
1739 | ||
1740 | if (!IS_SRIOV(bp)) | |
1741 | return 1; | |
1742 | ||
1743 | /* first get the cid - the only events we handle here are cfc-delete | |
1744 | * and set-mac completion | |
1745 | */ | |
1746 | opcode = elem->message.opcode; | |
1747 | ||
1748 | switch (opcode) { | |
1749 | case EVENT_RING_OPCODE_CFC_DEL: | |
da472731 | 1750 | cid = SW_CID(elem->message.data.cfc_del_event.cid); |
fd1fc79d AE |
1751 | DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid); |
1752 | break; | |
1753 | case EVENT_RING_OPCODE_CLASSIFICATION_RULES: | |
1754 | case EVENT_RING_OPCODE_MULTICAST_RULES: | |
1755 | case EVENT_RING_OPCODE_FILTERS_RULES: | |
2dc33bbc | 1756 | case EVENT_RING_OPCODE_RSS_UPDATE_RULES: |
9cd753a1 | 1757 | cid = SW_CID(elem->message.data.eth_event.echo); |
fd1fc79d AE |
1758 | DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid); |
1759 | break; | |
1760 | case EVENT_RING_OPCODE_VF_FLR: | |
1761 | abs_vfid = elem->message.data.vf_flr_event.vf_id; | |
1762 | DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n", | |
1763 | abs_vfid); | |
1764 | goto get_vf; | |
1765 | case EVENT_RING_OPCODE_MALICIOUS_VF: | |
1766 | abs_vfid = elem->message.data.malicious_vf_event.vf_id; | |
076d1329 AE |
1767 | BNX2X_ERR("Got VF MALICIOUS notification abs_vfid=%d err_id=0x%x\n", |
1768 | abs_vfid, | |
1769 | elem->message.data.malicious_vf_event.err_id); | |
fd1fc79d AE |
1770 | goto get_vf; |
1771 | default: | |
1772 | return 1; | |
1773 | } | |
1774 | ||
1775 | /* check if the cid is the VF range */ | |
1776 | if (!bnx2x_iov_is_vf_cid(bp, cid)) { | |
1777 | DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid); | |
1778 | return 1; | |
1779 | } | |
1780 | ||
1781 | /* extract vf and rxq index from vf_cid - relies on the following: | |
1782 | * 1. vfid on cid reflects the true abs_vfid | |
16a5fd92 | 1783 | * 2. The max number of VFs (per path) is 64 |
fd1fc79d AE |
1784 | */ |
1785 | qidx = cid & ((1 << BNX2X_VF_CID_WND)-1); | |
1786 | abs_vfid = (cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); | |
1787 | get_vf: | |
1788 | vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); | |
1789 | ||
1790 | if (!vf) { | |
1791 | BNX2X_ERR("EQ completion for unknown VF, cid %d, abs_vfid %d\n", | |
1792 | cid, abs_vfid); | |
1793 | return 0; | |
1794 | } | |
1795 | ||
1796 | switch (opcode) { | |
1797 | case EVENT_RING_OPCODE_CFC_DEL: | |
1798 | DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n", | |
1799 | vf->abs_vfid, qidx); | |
1800 | vfq_get(vf, qidx)->sp_obj.complete_cmd(bp, | |
1801 | &vfq_get(vf, | |
1802 | qidx)->sp_obj, | |
1803 | BNX2X_Q_CMD_CFC_DEL); | |
1804 | break; | |
1805 | case EVENT_RING_OPCODE_CLASSIFICATION_RULES: | |
1806 | DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n", | |
1807 | vf->abs_vfid, qidx); | |
1808 | bnx2x_vf_handle_classification_eqe(bp, vfq_get(vf, qidx), elem); | |
1809 | break; | |
1810 | case EVENT_RING_OPCODE_MULTICAST_RULES: | |
1811 | DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n", | |
1812 | vf->abs_vfid, qidx); | |
1813 | bnx2x_vf_handle_mcast_eqe(bp, vf); | |
1814 | break; | |
1815 | case EVENT_RING_OPCODE_FILTERS_RULES: | |
1816 | DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n", | |
1817 | vf->abs_vfid, qidx); | |
1818 | bnx2x_vf_handle_filters_eqe(bp, vf); | |
1819 | break; | |
2dc33bbc YM |
1820 | case EVENT_RING_OPCODE_RSS_UPDATE_RULES: |
1821 | DP(BNX2X_MSG_IOV, "got VF [%d:%d] RSS update ramrod\n", | |
1822 | vf->abs_vfid, qidx); | |
1823 | bnx2x_vf_handle_rss_update_eqe(bp, vf); | |
fd1fc79d | 1824 | case EVENT_RING_OPCODE_VF_FLR: |
fd1fc79d | 1825 | case EVENT_RING_OPCODE_MALICIOUS_VF: |
fd1fc79d | 1826 | /* Do nothing for now */ |
076d1329 | 1827 | return 0; |
fd1fc79d | 1828 | } |
fd1fc79d AE |
1829 | |
1830 | return 0; | |
1831 | } | |
1832 | ||
1833 | static struct bnx2x_virtf *bnx2x_vf_by_cid(struct bnx2x *bp, int vf_cid) | |
1834 | { | |
1835 | /* extract the vf from vf_cid - relies on the following: | |
1836 | * 1. vfid on cid reflects the true abs_vfid | |
16a5fd92 | 1837 | * 2. The max number of VFs (per path) is 64 |
fd1fc79d AE |
1838 | */ |
1839 | int abs_vfid = (vf_cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); | |
1840 | return bnx2x_vf_by_abs_fid(bp, abs_vfid); | |
1841 | } | |
1842 | ||
1843 | void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid, | |
1844 | struct bnx2x_queue_sp_obj **q_obj) | |
1845 | { | |
1846 | struct bnx2x_virtf *vf; | |
1847 | ||
290ca2bb AE |
1848 | if (!IS_SRIOV(bp)) |
1849 | return; | |
1850 | ||
fd1fc79d AE |
1851 | vf = bnx2x_vf_by_cid(bp, vf_cid); |
1852 | ||
1853 | if (vf) { | |
1854 | /* extract queue index from vf_cid - relies on the following: | |
1855 | * 1. vfid on cid reflects the true abs_vfid | |
16a5fd92 | 1856 | * 2. The max number of VFs (per path) is 64 |
fd1fc79d AE |
1857 | */ |
1858 | int q_index = vf_cid & ((1 << BNX2X_VF_CID_WND)-1); | |
1859 | *q_obj = &bnx2x_vfq(vf, q_index, sp_obj); | |
1860 | } else { | |
1861 | BNX2X_ERR("No vf matching cid %d\n", vf_cid); | |
1862 | } | |
1863 | } | |
1864 | ||
67c431a5 AE |
1865 | void bnx2x_iov_adjust_stats_req(struct bnx2x *bp) |
1866 | { | |
1867 | int i; | |
1868 | int first_queue_query_index, num_queues_req; | |
1869 | dma_addr_t cur_data_offset; | |
1870 | struct stats_query_entry *cur_query_entry; | |
1871 | u8 stats_count = 0; | |
1872 | bool is_fcoe = false; | |
1873 | ||
1874 | if (!IS_SRIOV(bp)) | |
1875 | return; | |
1876 | ||
1877 | if (!NO_FCOE(bp)) | |
1878 | is_fcoe = true; | |
1879 | ||
1880 | /* fcoe adds one global request and one queue request */ | |
1881 | num_queues_req = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe; | |
1882 | first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX - | |
1883 | (is_fcoe ? 0 : 1); | |
1884 | ||
76ca70fa YM |
1885 | DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), |
1886 | "BNX2X_NUM_ETH_QUEUES %d, is_fcoe %d, first_queue_query_index %d => determined the last non virtual statistics query index is %d. Will add queries on top of that\n", | |
1887 | BNX2X_NUM_ETH_QUEUES(bp), is_fcoe, first_queue_query_index, | |
1888 | first_queue_query_index + num_queues_req); | |
67c431a5 AE |
1889 | |
1890 | cur_data_offset = bp->fw_stats_data_mapping + | |
1891 | offsetof(struct bnx2x_fw_stats_data, queue_stats) + | |
1892 | num_queues_req * sizeof(struct per_queue_stats); | |
1893 | ||
1894 | cur_query_entry = &bp->fw_stats_req-> | |
1895 | query[first_queue_query_index + num_queues_req]; | |
1896 | ||
1897 | for_each_vf(bp, i) { | |
1898 | int j; | |
1899 | struct bnx2x_virtf *vf = BP_VF(bp, i); | |
1900 | ||
1901 | if (vf->state != VF_ENABLED) { | |
76ca70fa YM |
1902 | DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), |
1903 | "vf %d not enabled so no stats for it\n", | |
1904 | vf->abs_vfid); | |
67c431a5 AE |
1905 | continue; |
1906 | } | |
1907 | ||
850268d3 MS |
1908 | DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), |
1909 | "add addresses for vf %d\n", vf->abs_vfid); | |
67c431a5 AE |
1910 | for_each_vfq(vf, j) { |
1911 | struct bnx2x_vf_queue *rxq = vfq_get(vf, j); | |
1912 | ||
b9871bcf AE |
1913 | dma_addr_t q_stats_addr = |
1914 | vf->fw_stat_map + j * vf->stats_stride; | |
1915 | ||
67c431a5 AE |
1916 | /* collect stats fro active queues only */ |
1917 | if (bnx2x_get_q_logical_state(bp, &rxq->sp_obj) == | |
1918 | BNX2X_Q_LOGICAL_STATE_STOPPED) | |
1919 | continue; | |
1920 | ||
1921 | /* create stats query entry for this queue */ | |
1922 | cur_query_entry->kind = STATS_TYPE_QUEUE; | |
b9871bcf | 1923 | cur_query_entry->index = vfq_stat_id(vf, rxq); |
67c431a5 AE |
1924 | cur_query_entry->funcID = |
1925 | cpu_to_le16(FW_VF_HANDLE(vf->abs_vfid)); | |
1926 | cur_query_entry->address.hi = | |
b9871bcf | 1927 | cpu_to_le32(U64_HI(q_stats_addr)); |
67c431a5 | 1928 | cur_query_entry->address.lo = |
b9871bcf | 1929 | cpu_to_le32(U64_LO(q_stats_addr)); |
850268d3 MS |
1930 | DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), |
1931 | "added address %x %x for vf %d queue %d client %d\n", | |
1932 | cur_query_entry->address.hi, | |
1933 | cur_query_entry->address.lo, | |
1934 | cur_query_entry->funcID, | |
1935 | j, cur_query_entry->index); | |
67c431a5 AE |
1936 | cur_query_entry++; |
1937 | cur_data_offset += sizeof(struct per_queue_stats); | |
1938 | stats_count++; | |
b9871bcf AE |
1939 | |
1940 | /* all stats are coalesced to the leading queue */ | |
1941 | if (vf->cfg_flags & VF_CFG_STATS_COALESCE) | |
1942 | break; | |
67c431a5 AE |
1943 | } |
1944 | } | |
1945 | bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count; | |
1946 | } | |
1947 | ||
67c431a5 | 1948 | /* VF API helpers */ |
b93288d5 AE |
1949 | static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid, |
1950 | u8 enable) | |
1951 | { | |
1952 | u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4; | |
1953 | u32 val = enable ? (abs_vfid | (1 << 6)) : 0; | |
1954 | ||
1955 | REG_WR(bp, reg, val); | |
1956 | } | |
8ca5e17e | 1957 | |
99e9d211 AE |
1958 | static void bnx2x_vf_clr_qtbl(struct bnx2x *bp, struct bnx2x_virtf *vf) |
1959 | { | |
1960 | int i; | |
1961 | ||
1962 | for_each_vfq(vf, i) | |
1963 | bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, | |
1964 | vfq_qzone_id(vf, vfq_get(vf, i)), false); | |
1965 | } | |
1966 | ||
1967 | static void bnx2x_vf_igu_disable(struct bnx2x *bp, struct bnx2x_virtf *vf) | |
1968 | { | |
1969 | u32 val; | |
1970 | ||
1971 | /* clear the VF configuration - pretend */ | |
1972 | bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); | |
1973 | val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); | |
1974 | val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN | | |
1975 | IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_PARENT_MASK); | |
1976 | REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); | |
1977 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
1978 | } | |
1979 | ||
8ca5e17e AE |
1980 | u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf) |
1981 | { | |
1982 | return min_t(u8, min_t(u8, vf_sb_count(vf), BNX2X_CIDS_PER_VF), | |
1983 | BNX2X_VF_MAX_QUEUES); | |
1984 | } | |
1985 | ||
1986 | static | |
1987 | int bnx2x_vf_chk_avail_resc(struct bnx2x *bp, struct bnx2x_virtf *vf, | |
1988 | struct vf_pf_resc_request *req_resc) | |
1989 | { | |
1990 | u8 rxq_cnt = vf_rxq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); | |
1991 | u8 txq_cnt = vf_txq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); | |
1992 | ||
1993 | return ((req_resc->num_rxqs <= rxq_cnt) && | |
1994 | (req_resc->num_txqs <= txq_cnt) && | |
1995 | (req_resc->num_sbs <= vf_sb_count(vf)) && | |
1996 | (req_resc->num_mac_filters <= vf_mac_rules_cnt(vf)) && | |
05cc5a39 | 1997 | (req_resc->num_vlan_filters <= vf_vlan_rules_cnt(vf))); |
8ca5e17e AE |
1998 | } |
1999 | ||
2000 | /* CORE VF API */ | |
2001 | int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf, | |
2002 | struct vf_pf_resc_request *resc) | |
2003 | { | |
2004 | int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vf->index) * | |
2005 | BNX2X_CIDS_PER_VF; | |
2006 | ||
2007 | union cdu_context *base_cxt = (union cdu_context *) | |
2008 | BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + | |
2009 | (base_vf_cid & (ILT_PAGE_CIDS-1)); | |
2010 | int i; | |
2011 | ||
2012 | /* if state is 'acquired' the VF was not released or FLR'd, in | |
2013 | * this case the returned resources match the acquired already | |
2014 | * acquired resources. Verify that the requested numbers do | |
2015 | * not exceed the already acquired numbers. | |
2016 | */ | |
2017 | if (vf->state == VF_ACQUIRED) { | |
2018 | DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n", | |
2019 | vf->abs_vfid); | |
2020 | ||
2021 | if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { | |
2022 | BNX2X_ERR("VF[%d] When re-acquiring resources, requested numbers must be <= then previously acquired numbers\n", | |
2023 | vf->abs_vfid); | |
2024 | return -EINVAL; | |
2025 | } | |
2026 | return 0; | |
2027 | } | |
2028 | ||
2029 | /* Otherwise vf state must be 'free' or 'reset' */ | |
2030 | if (vf->state != VF_FREE && vf->state != VF_RESET) { | |
2031 | BNX2X_ERR("VF[%d] Can not acquire a VF with state %d\n", | |
2032 | vf->abs_vfid, vf->state); | |
2033 | return -EINVAL; | |
2034 | } | |
2035 | ||
2036 | /* static allocation: | |
16a5fd92 | 2037 | * the global maximum number are fixed per VF. Fail the request if |
8ca5e17e AE |
2038 | * requested number exceed these globals |
2039 | */ | |
2040 | if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { | |
2041 | DP(BNX2X_MSG_IOV, | |
2042 | "cannot fulfill vf resource request. Placing maximal available values in response\n"); | |
2043 | /* set the max resource in the vf */ | |
2044 | return -ENOMEM; | |
2045 | } | |
2046 | ||
2047 | /* Set resources counters - 0 request means max available */ | |
2048 | vf_sb_count(vf) = resc->num_sbs; | |
2049 | vf_rxq_count(vf) = resc->num_rxqs ? : bnx2x_vf_max_queue_cnt(bp, vf); | |
2050 | vf_txq_count(vf) = resc->num_txqs ? : bnx2x_vf_max_queue_cnt(bp, vf); | |
8ca5e17e AE |
2051 | |
2052 | DP(BNX2X_MSG_IOV, | |
2053 | "Fulfilling vf request: sb count %d, tx_count %d, rx_count %d, mac_rules_count %d, vlan_rules_count %d\n", | |
2054 | vf_sb_count(vf), vf_rxq_count(vf), | |
2055 | vf_txq_count(vf), vf_mac_rules_cnt(vf), | |
05cc5a39 | 2056 | vf_vlan_rules_cnt(vf)); |
8ca5e17e AE |
2057 | |
2058 | /* Initialize the queues */ | |
2059 | if (!vf->vfqs) { | |
2060 | DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n"); | |
2061 | return -EINVAL; | |
2062 | } | |
2063 | ||
2064 | for_each_vfq(vf, i) { | |
2065 | struct bnx2x_vf_queue *q = vfq_get(vf, i); | |
2066 | ||
2067 | if (!q) { | |
b9871bcf | 2068 | BNX2X_ERR("q number %d was not allocated\n", i); |
8ca5e17e AE |
2069 | return -EINVAL; |
2070 | } | |
2071 | ||
2072 | q->index = i; | |
2073 | q->cxt = &((base_cxt + i)->eth); | |
2074 | q->cid = BNX2X_FIRST_VF_CID + base_vf_cid + i; | |
2075 | ||
2076 | DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n", | |
2077 | vf->abs_vfid, i, q->index, q->cid, q->cxt); | |
2078 | ||
2079 | /* init SP objects */ | |
2080 | bnx2x_vfq_init(bp, vf, q); | |
2081 | } | |
2082 | vf->state = VF_ACQUIRED; | |
2083 | return 0; | |
2084 | } | |
2085 | ||
b93288d5 AE |
2086 | int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf, dma_addr_t *sb_map) |
2087 | { | |
2088 | struct bnx2x_func_init_params func_init = {0}; | |
b93288d5 AE |
2089 | int i; |
2090 | ||
2091 | /* the sb resources are initialized at this point, do the | |
2092 | * FW/HW initializations | |
2093 | */ | |
2094 | for_each_vf_sb(vf, i) | |
2095 | bnx2x_init_sb(bp, (dma_addr_t)sb_map[i], vf->abs_vfid, true, | |
2096 | vf_igu_sb(vf, i), vf_igu_sb(vf, i)); | |
2097 | ||
2098 | /* Sanity checks */ | |
2099 | if (vf->state != VF_ACQUIRED) { | |
2100 | DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n", | |
2101 | vf->abs_vfid, vf->state); | |
2102 | return -EINVAL; | |
2103 | } | |
03c22ea3 AE |
2104 | |
2105 | /* let FLR complete ... */ | |
2106 | msleep(100); | |
2107 | ||
b93288d5 AE |
2108 | /* FLR cleanup epilogue */ |
2109 | if (bnx2x_vf_flr_clnup_epilog(bp, vf->abs_vfid)) | |
2110 | return -EBUSY; | |
2111 | ||
2112 | /* reset IGU VF statistics: MSIX */ | |
2113 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0); | |
2114 | ||
b93288d5 | 2115 | /* function setup */ |
b93288d5 AE |
2116 | func_init.pf_id = BP_FUNC(bp); |
2117 | func_init.func_id = FW_VF_HANDLE(vf->abs_vfid); | |
b93288d5 AE |
2118 | bnx2x_func_init(bp, &func_init); |
2119 | ||
2120 | /* Enable the vf */ | |
2121 | bnx2x_vf_enable_access(bp, vf->abs_vfid); | |
2122 | bnx2x_vf_enable_traffic(bp, vf); | |
2123 | ||
2124 | /* queue protection table */ | |
2125 | for_each_vfq(vf, i) | |
2126 | bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, | |
2127 | vfq_qzone_id(vf, vfq_get(vf, i)), true); | |
2128 | ||
2129 | vf->state = VF_ENABLED; | |
2130 | ||
abc5a021 AE |
2131 | /* update vf bulletin board */ |
2132 | bnx2x_post_vf_bulletin(bp, vf->index); | |
2133 | ||
b93288d5 AE |
2134 | return 0; |
2135 | } | |
2136 | ||
a3097bda AE |
2137 | struct set_vf_state_cookie { |
2138 | struct bnx2x_virtf *vf; | |
2139 | u8 state; | |
2140 | }; | |
2141 | ||
8e61777d | 2142 | static void bnx2x_set_vf_state(void *cookie) |
a3097bda AE |
2143 | { |
2144 | struct set_vf_state_cookie *p = (struct set_vf_state_cookie *)cookie; | |
2145 | ||
2146 | p->vf->state = p->state; | |
2147 | } | |
2148 | ||
2dc33bbc | 2149 | int bnx2x_vf_close(struct bnx2x *bp, struct bnx2x_virtf *vf) |
99e9d211 | 2150 | { |
2dc33bbc | 2151 | int rc = 0, i; |
99e9d211 | 2152 | |
2dc33bbc | 2153 | DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); |
99e9d211 | 2154 | |
2dc33bbc YM |
2155 | /* Close all queues */ |
2156 | for (i = 0; i < vf_rxq_count(vf); i++) { | |
2157 | rc = bnx2x_vf_queue_teardown(bp, vf, i); | |
2158 | if (rc) | |
2159 | goto op_err; | |
2160 | } | |
99e9d211 | 2161 | |
2dc33bbc YM |
2162 | /* disable the interrupts */ |
2163 | DP(BNX2X_MSG_IOV, "disabling igu\n"); | |
2164 | bnx2x_vf_igu_disable(bp, vf); | |
99e9d211 | 2165 | |
2dc33bbc YM |
2166 | /* disable the VF */ |
2167 | DP(BNX2X_MSG_IOV, "clearing qtbl\n"); | |
2168 | bnx2x_vf_clr_qtbl(bp, vf); | |
a3097bda AE |
2169 | |
2170 | /* need to make sure there are no outstanding stats ramrods which may | |
2171 | * cause the device to access the VF's stats buffer which it will free | |
2172 | * as soon as we return from the close flow. | |
2173 | */ | |
2174 | { | |
2175 | struct set_vf_state_cookie cookie; | |
2176 | ||
2177 | cookie.vf = vf; | |
2178 | cookie.state = VF_ACQUIRED; | |
dff173de YM |
2179 | rc = bnx2x_stats_safe_exec(bp, bnx2x_set_vf_state, &cookie); |
2180 | if (rc) | |
2181 | goto op_err; | |
a3097bda AE |
2182 | } |
2183 | ||
99e9d211 | 2184 | DP(BNX2X_MSG_IOV, "set state to acquired\n"); |
99e9d211 | 2185 | |
2dc33bbc YM |
2186 | return 0; |
2187 | op_err: | |
2188 | BNX2X_ERR("vf[%d] CLOSE error: rc %d\n", vf->abs_vfid, rc); | |
2189 | return rc; | |
99e9d211 AE |
2190 | } |
2191 | ||
16a5fd92 | 2192 | /* VF release can be called either: 1. The VF was acquired but |
f1929b01 AE |
2193 | * not enabled 2. the vf was enabled or in the process of being |
2194 | * enabled | |
2195 | */ | |
2dc33bbc | 2196 | int bnx2x_vf_free(struct bnx2x *bp, struct bnx2x_virtf *vf) |
f1929b01 | 2197 | { |
2dc33bbc | 2198 | int rc; |
f1929b01 AE |
2199 | |
2200 | DP(BNX2X_MSG_IOV, "VF[%d] STATE: %s\n", vf->abs_vfid, | |
2201 | vf->state == VF_FREE ? "Free" : | |
2202 | vf->state == VF_ACQUIRED ? "Acquired" : | |
2203 | vf->state == VF_ENABLED ? "Enabled" : | |
2204 | vf->state == VF_RESET ? "Reset" : | |
2205 | "Unknown"); | |
2206 | ||
2207 | switch (vf->state) { | |
2208 | case VF_ENABLED: | |
2dc33bbc YM |
2209 | rc = bnx2x_vf_close(bp, vf); |
2210 | if (rc) | |
f1929b01 | 2211 | goto op_err; |
2dc33bbc | 2212 | /* Fallthrough to release resources */ |
f1929b01 AE |
2213 | case VF_ACQUIRED: |
2214 | DP(BNX2X_MSG_IOV, "about to free resources\n"); | |
2215 | bnx2x_vf_free_resc(bp, vf); | |
2dc33bbc | 2216 | break; |
f1929b01 AE |
2217 | |
2218 | case VF_FREE: | |
2219 | case VF_RESET: | |
f1929b01 | 2220 | default: |
2dc33bbc | 2221 | break; |
b9871bcf | 2222 | } |
2dc33bbc | 2223 | return 0; |
b9871bcf | 2224 | op_err: |
2dc33bbc YM |
2225 | BNX2X_ERR("VF[%d] RELEASE error: rc %d\n", vf->abs_vfid, rc); |
2226 | return rc; | |
f1929b01 AE |
2227 | } |
2228 | ||
2dc33bbc YM |
2229 | int bnx2x_vf_rss_update(struct bnx2x *bp, struct bnx2x_virtf *vf, |
2230 | struct bnx2x_config_rss_params *rss) | |
b9871bcf | 2231 | { |
2dc33bbc YM |
2232 | DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); |
2233 | set_bit(RAMROD_COMP_WAIT, &rss->ramrod_flags); | |
2234 | return bnx2x_config_rss(bp, rss); | |
b9871bcf AE |
2235 | } |
2236 | ||
2dc33bbc YM |
2237 | int bnx2x_vf_tpa_update(struct bnx2x *bp, struct bnx2x_virtf *vf, |
2238 | struct vfpf_tpa_tlv *tlv, | |
2239 | struct bnx2x_queue_update_tpa_params *params) | |
14a94ebd | 2240 | { |
2dc33bbc YM |
2241 | aligned_u64 *sge_addr = tlv->tpa_client_info.sge_addr; |
2242 | struct bnx2x_queue_state_params qstate; | |
2243 | int qid, rc = 0; | |
14a94ebd | 2244 | |
2dc33bbc | 2245 | DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); |
14a94ebd | 2246 | |
2dc33bbc YM |
2247 | /* Set ramrod params */ |
2248 | memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); | |
2249 | memcpy(&qstate.params.update_tpa, params, | |
2250 | sizeof(struct bnx2x_queue_update_tpa_params)); | |
2251 | qstate.cmd = BNX2X_Q_CMD_UPDATE_TPA; | |
2252 | set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); | |
14a94ebd | 2253 | |
2dc33bbc YM |
2254 | for (qid = 0; qid < vf_rxq_count(vf); qid++) { |
2255 | qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); | |
2256 | qstate.params.update_tpa.sge_map = sge_addr[qid]; | |
2257 | DP(BNX2X_MSG_IOV, "sge_addr[%d:%d] %08x:%08x\n", | |
2258 | vf->abs_vfid, qid, U64_HI(sge_addr[qid]), | |
2259 | U64_LO(sge_addr[qid])); | |
2260 | rc = bnx2x_queue_state_change(bp, &qstate); | |
2261 | if (rc) { | |
2262 | BNX2X_ERR("Failed to configure sge_addr %08x:%08x for [%d:%d]\n", | |
2263 | U64_HI(sge_addr[qid]), U64_LO(sge_addr[qid]), | |
2264 | vf->abs_vfid, qid); | |
2265 | return rc; | |
14a94ebd | 2266 | } |
14a94ebd | 2267 | } |
14a94ebd | 2268 | |
2dc33bbc | 2269 | return rc; |
14a94ebd MK |
2270 | } |
2271 | ||
f1929b01 AE |
2272 | /* VF release ~ VF close + VF release-resources |
2273 | * Release is the ultimate SW shutdown and is called whenever an | |
2274 | * irrecoverable error is encountered. | |
2275 | */ | |
2dc33bbc | 2276 | int bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf) |
f1929b01 | 2277 | { |
f1929b01 | 2278 | int rc; |
b9871bcf AE |
2279 | |
2280 | DP(BNX2X_MSG_IOV, "PF releasing vf %d\n", vf->abs_vfid); | |
f1929b01 AE |
2281 | bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); |
2282 | ||
2dc33bbc | 2283 | rc = bnx2x_vf_free(bp, vf); |
f1929b01 AE |
2284 | if (rc) |
2285 | WARN(rc, | |
2286 | "VF[%d] Failed to allocate resources for release op- rc=%d\n", | |
2287 | vf->abs_vfid, rc); | |
2dc33bbc YM |
2288 | bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); |
2289 | return rc; | |
f1929b01 AE |
2290 | } |
2291 | ||
8ca5e17e AE |
2292 | void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, |
2293 | enum channel_tlvs tlv) | |
2294 | { | |
b9871bcf AE |
2295 | /* we don't lock the channel for unsupported tlvs */ |
2296 | if (!bnx2x_tlv_supported(tlv)) { | |
2297 | BNX2X_ERR("attempting to lock with unsupported tlv. Aborting\n"); | |
2298 | return; | |
2299 | } | |
2300 | ||
8ca5e17e AE |
2301 | /* lock the channel */ |
2302 | mutex_lock(&vf->op_mutex); | |
2303 | ||
2304 | /* record the locking op */ | |
2305 | vf->op_current = tlv; | |
2306 | ||
2307 | /* log the lock */ | |
2308 | DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n", | |
2309 | vf->abs_vfid, tlv); | |
2310 | } | |
2311 | ||
2312 | void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, | |
2313 | enum channel_tlvs expected_tlv) | |
2314 | { | |
b9871bcf AE |
2315 | enum channel_tlvs current_tlv; |
2316 | ||
2317 | if (!vf) { | |
2318 | BNX2X_ERR("VF was %p\n", vf); | |
2319 | return; | |
2320 | } | |
2321 | ||
2322 | current_tlv = vf->op_current; | |
2323 | ||
2324 | /* we don't unlock the channel for unsupported tlvs */ | |
2325 | if (!bnx2x_tlv_supported(expected_tlv)) | |
2326 | return; | |
2327 | ||
8ca5e17e AE |
2328 | WARN(expected_tlv != vf->op_current, |
2329 | "lock mismatch: expected %d found %d", expected_tlv, | |
2330 | vf->op_current); | |
2331 | ||
b9871bcf AE |
2332 | /* record the locking op */ |
2333 | vf->op_current = CHANNEL_TLV_NONE; | |
2334 | ||
8ca5e17e AE |
2335 | /* lock the channel */ |
2336 | mutex_unlock(&vf->op_mutex); | |
2337 | ||
2338 | /* log the unlock */ | |
2339 | DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n", | |
0c23ad37 | 2340 | vf->abs_vfid, current_tlv); |
8ca5e17e | 2341 | } |
6411280a | 2342 | |
c14db202 YM |
2343 | static int bnx2x_set_pf_tx_switching(struct bnx2x *bp, bool enable) |
2344 | { | |
2345 | struct bnx2x_queue_state_params q_params; | |
2346 | u32 prev_flags; | |
2347 | int i, rc; | |
2348 | ||
2349 | /* Verify changes are needed and record current Tx switching state */ | |
2350 | prev_flags = bp->flags; | |
2351 | if (enable) | |
2352 | bp->flags |= TX_SWITCHING; | |
2353 | else | |
2354 | bp->flags &= ~TX_SWITCHING; | |
2355 | if (prev_flags == bp->flags) | |
2356 | return 0; | |
2357 | ||
2358 | /* Verify state enables the sending of queue ramrods */ | |
2359 | if ((bp->state != BNX2X_STATE_OPEN) || | |
2360 | (bnx2x_get_q_logical_state(bp, | |
2361 | &bnx2x_sp_obj(bp, &bp->fp[0]).q_obj) != | |
2362 | BNX2X_Q_LOGICAL_STATE_ACTIVE)) | |
2363 | return 0; | |
2364 | ||
2365 | /* send q. update ramrod to configure Tx switching */ | |
2366 | memset(&q_params, 0, sizeof(q_params)); | |
2367 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
2368 | q_params.cmd = BNX2X_Q_CMD_UPDATE; | |
2369 | __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG, | |
2370 | &q_params.params.update.update_flags); | |
2371 | if (enable) | |
2372 | __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING, | |
2373 | &q_params.params.update.update_flags); | |
2374 | else | |
2375 | __clear_bit(BNX2X_Q_UPDATE_TX_SWITCHING, | |
2376 | &q_params.params.update.update_flags); | |
2377 | ||
2378 | /* send the ramrod on all the queues of the PF */ | |
2379 | for_each_eth_queue(bp, i) { | |
2380 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
2381 | ||
2382 | /* Set the appropriate Queue object */ | |
2383 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; | |
2384 | ||
2385 | /* Update the Queue state */ | |
2386 | rc = bnx2x_queue_state_change(bp, &q_params); | |
2387 | if (rc) { | |
2388 | BNX2X_ERR("Failed to configure Tx switching\n"); | |
2389 | return rc; | |
2390 | } | |
2391 | } | |
2392 | ||
2393 | DP(BNX2X_MSG_IOV, "%s Tx Switching\n", enable ? "Enabled" : "Disabled"); | |
2394 | return 0; | |
2395 | } | |
2396 | ||
3c76feff | 2397 | int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param) |
6411280a | 2398 | { |
3c76feff | 2399 | struct bnx2x *bp = netdev_priv(pci_get_drvdata(dev)); |
6411280a | 2400 | |
c8781cf4 MK |
2401 | if (!IS_SRIOV(bp)) { |
2402 | BNX2X_ERR("failed to configure SR-IOV since vfdb was not allocated. Check dmesg for errors in probe stage\n"); | |
2403 | return -EINVAL; | |
2404 | } | |
2405 | ||
3c76feff AE |
2406 | DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n", |
2407 | num_vfs_param, BNX2X_NR_VIRTFN(bp)); | |
2408 | ||
2409 | /* HW channel is only operational when PF is up */ | |
2410 | if (bp->state != BNX2X_STATE_OPEN) { | |
6bf07b8e | 2411 | BNX2X_ERR("VF num configuration via sysfs not supported while PF is down\n"); |
3c76feff AE |
2412 | return -EINVAL; |
2413 | } | |
2414 | ||
2415 | /* we are always bound by the total_vfs in the configuration space */ | |
2416 | if (num_vfs_param > BNX2X_NR_VIRTFN(bp)) { | |
2417 | BNX2X_ERR("truncating requested number of VFs (%d) down to maximum allowed (%d)\n", | |
2418 | num_vfs_param, BNX2X_NR_VIRTFN(bp)); | |
2419 | num_vfs_param = BNX2X_NR_VIRTFN(bp); | |
2420 | } | |
2421 | ||
2422 | bp->requested_nr_virtfn = num_vfs_param; | |
2423 | if (num_vfs_param == 0) { | |
c14db202 | 2424 | bnx2x_set_pf_tx_switching(bp, false); |
a345ce71 | 2425 | bnx2x_disable_sriov(bp); |
3c76feff AE |
2426 | return 0; |
2427 | } else { | |
2428 | return bnx2x_enable_sriov(bp); | |
2429 | } | |
2430 | } | |
c14db202 | 2431 | |
b9871bcf | 2432 | #define IGU_ENTRY_SIZE 4 |
3c76feff AE |
2433 | |
2434 | int bnx2x_enable_sriov(struct bnx2x *bp) | |
2435 | { | |
2436 | int rc = 0, req_vfs = bp->requested_nr_virtfn; | |
b9871bcf AE |
2437 | int vf_idx, sb_idx, vfq_idx, qcount, first_vf; |
2438 | u32 igu_entry, address; | |
2439 | u16 num_vf_queues; | |
3c76feff | 2440 | |
b9871bcf AE |
2441 | if (req_vfs == 0) |
2442 | return 0; | |
2443 | ||
2444 | first_vf = bp->vfdb->sriov.first_vf_in_pf; | |
2445 | ||
2446 | /* statically distribute vf sb pool between VFs */ | |
2447 | num_vf_queues = min_t(u16, BNX2X_VF_MAX_QUEUES, | |
2448 | BP_VFDB(bp)->vf_sbs_pool / req_vfs); | |
2449 | ||
2450 | /* zero previous values learned from igu cam */ | |
2451 | for (vf_idx = 0; vf_idx < req_vfs; vf_idx++) { | |
2452 | struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); | |
2453 | ||
2454 | vf->sb_count = 0; | |
2455 | vf_sb_count(BP_VF(bp, vf_idx)) = 0; | |
2456 | } | |
2457 | bp->vfdb->vf_sbs_pool = 0; | |
2458 | ||
2459 | /* prepare IGU cam */ | |
2460 | sb_idx = BP_VFDB(bp)->first_vf_igu_entry; | |
2461 | address = IGU_REG_MAPPING_MEMORY + sb_idx * IGU_ENTRY_SIZE; | |
2462 | for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { | |
2463 | for (vfq_idx = 0; vfq_idx < num_vf_queues; vfq_idx++) { | |
2464 | igu_entry = vf_idx << IGU_REG_MAPPING_MEMORY_FID_SHIFT | | |
2465 | vfq_idx << IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT | | |
2466 | IGU_REG_MAPPING_MEMORY_VALID; | |
2467 | DP(BNX2X_MSG_IOV, "assigning sb %d to vf %d\n", | |
2468 | sb_idx, vf_idx); | |
2469 | REG_WR(bp, address, igu_entry); | |
2470 | sb_idx++; | |
2471 | address += IGU_ENTRY_SIZE; | |
2472 | } | |
2473 | } | |
2474 | ||
2475 | /* Reinitialize vf database according to igu cam */ | |
2476 | bnx2x_get_vf_igu_cam_info(bp); | |
2477 | ||
2478 | DP(BNX2X_MSG_IOV, "vf_sbs_pool %d, num_vf_queues %d\n", | |
2479 | BP_VFDB(bp)->vf_sbs_pool, num_vf_queues); | |
2480 | ||
2481 | qcount = 0; | |
2482 | for_each_vf(bp, vf_idx) { | |
2483 | struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); | |
2484 | ||
2485 | /* set local queue arrays */ | |
2486 | vf->vfqs = &bp->vfdb->vfqs[qcount]; | |
2487 | qcount += vf_sb_count(vf); | |
717fa2b9 | 2488 | bnx2x_iov_static_resc(bp, vf); |
b9871bcf AE |
2489 | } |
2490 | ||
89e18ae6 MK |
2491 | /* prepare msix vectors in VF configuration space - the value in the |
2492 | * PCI configuration space should be the index of the last entry, | |
2493 | * namely one less than the actual size of the table | |
2494 | */ | |
b9871bcf AE |
2495 | for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { |
2496 | bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx)); | |
2497 | REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL, | |
89e18ae6 | 2498 | num_vf_queues - 1); |
717fa2b9 | 2499 | DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n", |
89e18ae6 | 2500 | vf_idx, num_vf_queues - 1); |
b9871bcf AE |
2501 | } |
2502 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
2503 | ||
2504 | /* enable sriov. This will probe all the VFs, and consequentially cause | |
2505 | * the "acquire" messages to appear on the VF PF channel. | |
2506 | */ | |
2507 | DP(BNX2X_MSG_IOV, "about to call enable sriov\n"); | |
826cb7b4 | 2508 | bnx2x_disable_sriov(bp); |
c14db202 YM |
2509 | |
2510 | rc = bnx2x_set_pf_tx_switching(bp, true); | |
2511 | if (rc) | |
2512 | return rc; | |
2513 | ||
3c76feff AE |
2514 | rc = pci_enable_sriov(bp->pdev, req_vfs); |
2515 | if (rc) { | |
6411280a | 2516 | BNX2X_ERR("pci_enable_sriov failed with %d\n", rc); |
3c76feff AE |
2517 | return rc; |
2518 | } | |
2519 | DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs); | |
2520 | return req_vfs; | |
6411280a AE |
2521 | } |
2522 | ||
3ec9f9ca AE |
2523 | void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp) |
2524 | { | |
2525 | int vfidx; | |
2526 | struct pf_vf_bulletin_content *bulletin; | |
2527 | ||
2528 | DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n"); | |
2529 | for_each_vf(bp, vfidx) { | |
05cc5a39 | 2530 | bulletin = BP_VF_BULLETIN(bp, vfidx); |
c46309c7 | 2531 | if (bulletin->valid_bitmap & (1 << VLAN_VALID)) |
79aab093 MS |
2532 | bnx2x_set_vf_vlan(bp->dev, vfidx, bulletin->vlan, 0, |
2533 | htons(ETH_P_8021Q)); | |
3ec9f9ca AE |
2534 | } |
2535 | } | |
2536 | ||
3c76feff AE |
2537 | void bnx2x_disable_sriov(struct bnx2x *bp) |
2538 | { | |
a345ce71 YM |
2539 | if (pci_vfs_assigned(bp->pdev)) { |
2540 | DP(BNX2X_MSG_IOV, | |
2541 | "Unloading driver while VFs are assigned - VFs will not be deallocated\n"); | |
2542 | return; | |
2543 | } | |
2544 | ||
3c76feff AE |
2545 | pci_disable_sriov(bp->pdev); |
2546 | } | |
2547 | ||
6495d15a DK |
2548 | static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx, |
2549 | struct bnx2x_virtf **vf, | |
2550 | struct pf_vf_bulletin_content **bulletin, | |
2551 | bool test_queue) | |
3ec9f9ca | 2552 | { |
af902ae4 | 2553 | if (bp->state != BNX2X_STATE_OPEN) { |
6495d15a | 2554 | BNX2X_ERR("PF is down - can't utilize iov-related functionality\n"); |
af902ae4 AE |
2555 | return -EINVAL; |
2556 | } | |
2557 | ||
3ec9f9ca | 2558 | if (!IS_SRIOV(bp)) { |
0c23ad37 | 2559 | BNX2X_ERR("sriov is disabled - can't utilize iov-related functionality\n"); |
3ec9f9ca AE |
2560 | return -EINVAL; |
2561 | } | |
2562 | ||
2563 | if (vfidx >= BNX2X_NR_VIRTFN(bp)) { | |
6495d15a | 2564 | BNX2X_ERR("VF is uninitialized - can't utilize iov-related functionality. vfidx was %d BNX2X_NR_VIRTFN was %d\n", |
3ec9f9ca AE |
2565 | vfidx, BNX2X_NR_VIRTFN(bp)); |
2566 | return -EINVAL; | |
2567 | } | |
2568 | ||
5ae30d78 AE |
2569 | /* init members */ |
2570 | *vf = BP_VF(bp, vfidx); | |
2571 | *bulletin = BP_VF_BULLETIN(bp, vfidx); | |
2572 | ||
2573 | if (!*vf) { | |
6495d15a | 2574 | BNX2X_ERR("Unable to get VF structure for vfidx %d\n", vfidx); |
b9871bcf AE |
2575 | return -EINVAL; |
2576 | } | |
2577 | ||
6495d15a DK |
2578 | if (test_queue && !(*vf)->vfqs) { |
2579 | BNX2X_ERR("vfqs struct is null. Was this invoked before dynamically enabling SR-IOV? vfidx was %d\n", | |
3ec9f9ca AE |
2580 | vfidx); |
2581 | return -EINVAL; | |
2582 | } | |
2583 | ||
5ae30d78 | 2584 | if (!*bulletin) { |
6495d15a | 2585 | BNX2X_ERR("Bulletin Board struct is null for vfidx %d\n", |
5ae30d78 AE |
2586 | vfidx); |
2587 | return -EINVAL; | |
2588 | } | |
2589 | ||
3ec9f9ca AE |
2590 | return 0; |
2591 | } | |
2592 | ||
2593 | int bnx2x_get_vf_config(struct net_device *dev, int vfidx, | |
2594 | struct ifla_vf_info *ivi) | |
2595 | { | |
2596 | struct bnx2x *bp = netdev_priv(dev); | |
5ae30d78 AE |
2597 | struct bnx2x_virtf *vf = NULL; |
2598 | struct pf_vf_bulletin_content *bulletin = NULL; | |
2599 | struct bnx2x_vlan_mac_obj *mac_obj; | |
2600 | struct bnx2x_vlan_mac_obj *vlan_obj; | |
3ec9f9ca AE |
2601 | int rc; |
2602 | ||
5ae30d78 | 2603 | /* sanity and init */ |
6495d15a | 2604 | rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); |
3ec9f9ca AE |
2605 | if (rc) |
2606 | return rc; | |
6495d15a | 2607 | |
b9871bcf AE |
2608 | mac_obj = &bnx2x_leading_vfq(vf, mac_obj); |
2609 | vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); | |
5ae30d78 | 2610 | if (!mac_obj || !vlan_obj) { |
3c76feff AE |
2611 | BNX2X_ERR("VF partially initialized\n"); |
2612 | return -EINVAL; | |
2613 | } | |
3ec9f9ca AE |
2614 | |
2615 | ivi->vf = vfidx; | |
2616 | ivi->qos = 0; | |
ed616689 SC |
2617 | ivi->max_tx_rate = 10000; /* always 10G. TBA take from link struct */ |
2618 | ivi->min_tx_rate = 0; | |
3ec9f9ca AE |
2619 | ivi->spoofchk = 1; /*always enabled */ |
2620 | if (vf->state == VF_ENABLED) { | |
2621 | /* mac and vlan are in vlan_mac objects */ | |
3a3534ec | 2622 | if (bnx2x_validate_vf_sp_objs(bp, vf, false)) { |
b9871bcf AE |
2623 | mac_obj->get_n_elements(bp, mac_obj, 1, (u8 *)&ivi->mac, |
2624 | 0, ETH_ALEN); | |
b9871bcf AE |
2625 | vlan_obj->get_n_elements(bp, vlan_obj, 1, |
2626 | (u8 *)&ivi->vlan, 0, | |
2627 | VLAN_HLEN); | |
3a3534ec | 2628 | } |
3ec9f9ca | 2629 | } else { |
6495d15a | 2630 | mutex_lock(&bp->vfdb->bulletin_mutex); |
3ec9f9ca AE |
2631 | /* mac */ |
2632 | if (bulletin->valid_bitmap & (1 << MAC_ADDR_VALID)) | |
2633 | /* mac configured by ndo so its in bulletin board */ | |
2634 | memcpy(&ivi->mac, bulletin->mac, ETH_ALEN); | |
2635 | else | |
16a5fd92 | 2636 | /* function has not been loaded yet. Show mac as 0s */ |
c7bf7169 | 2637 | eth_zero_addr(ivi->mac); |
3ec9f9ca AE |
2638 | |
2639 | /* vlan */ | |
2640 | if (bulletin->valid_bitmap & (1 << VLAN_VALID)) | |
2641 | /* vlan configured by ndo so its in bulletin board */ | |
2642 | memcpy(&ivi->vlan, &bulletin->vlan, VLAN_HLEN); | |
2643 | else | |
16a5fd92 | 2644 | /* function has not been loaded yet. Show vlans as 0s */ |
3ec9f9ca | 2645 | memset(&ivi->vlan, 0, VLAN_HLEN); |
6495d15a DK |
2646 | |
2647 | mutex_unlock(&bp->vfdb->bulletin_mutex); | |
3ec9f9ca AE |
2648 | } |
2649 | ||
2650 | return 0; | |
2651 | } | |
2652 | ||
6411280a AE |
2653 | /* New mac for VF. Consider these cases: |
2654 | * 1. VF hasn't been acquired yet - save the mac in local bulletin board and | |
2655 | * supply at acquire. | |
2656 | * 2. VF has already been acquired but has not yet initialized - store in local | |
2657 | * bulletin board. mac will be posted on VF bulletin board after VF init. VF | |
2658 | * will configure this mac when it is ready. | |
2659 | * 3. VF has already initialized but has not yet setup a queue - post the new | |
2660 | * mac on VF's bulletin board right now. VF will configure this mac when it | |
2661 | * is ready. | |
2662 | * 4. VF has already set a queue - delete any macs already configured for this | |
2663 | * queue and manually config the new mac. | |
2664 | * In any event, once this function has been called refuse any attempts by the | |
2665 | * VF to configure any mac for itself except for this mac. In case of a race | |
2666 | * where the VF fails to see the new post on its bulletin board before sending a | |
2667 | * mac configuration request, the PF will simply fail the request and VF can try | |
3ec9f9ca | 2668 | * again after consulting its bulletin board. |
6411280a | 2669 | */ |
3ec9f9ca | 2670 | int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac) |
6411280a AE |
2671 | { |
2672 | struct bnx2x *bp = netdev_priv(dev); | |
3ec9f9ca | 2673 | int rc, q_logical_state; |
5ae30d78 AE |
2674 | struct bnx2x_virtf *vf = NULL; |
2675 | struct pf_vf_bulletin_content *bulletin = NULL; | |
6411280a | 2676 | |
6411280a AE |
2677 | if (!is_valid_ether_addr(mac)) { |
2678 | BNX2X_ERR("mac address invalid\n"); | |
2679 | return -EINVAL; | |
2680 | } | |
2681 | ||
6495d15a DK |
2682 | /* sanity and init */ |
2683 | rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); | |
2684 | if (rc) | |
2685 | return rc; | |
2686 | ||
2687 | mutex_lock(&bp->vfdb->bulletin_mutex); | |
2688 | ||
16a5fd92 | 2689 | /* update PF's copy of the VF's bulletin. Will no longer accept mac |
6411280a AE |
2690 | * configuration requests from vf unless match this mac |
2691 | */ | |
2692 | bulletin->valid_bitmap |= 1 << MAC_ADDR_VALID; | |
2693 | memcpy(bulletin->mac, mac, ETH_ALEN); | |
2694 | ||
2695 | /* Post update on VF's bulletin board */ | |
2696 | rc = bnx2x_post_vf_bulletin(bp, vfidx); | |
6495d15a DK |
2697 | |
2698 | /* release lock before checking return code */ | |
2699 | mutex_unlock(&bp->vfdb->bulletin_mutex); | |
2700 | ||
6411280a AE |
2701 | if (rc) { |
2702 | BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx); | |
2703 | return rc; | |
2704 | } | |
2705 | ||
6411280a | 2706 | q_logical_state = |
b9871bcf | 2707 | bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)); |
6411280a AE |
2708 | if (vf->state == VF_ENABLED && |
2709 | q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) { | |
2710 | /* configure the mac in device on this vf's queue */ | |
3ec9f9ca | 2711 | unsigned long ramrod_flags = 0; |
3a3534ec | 2712 | struct bnx2x_vlan_mac_obj *mac_obj; |
b9871bcf | 2713 | |
3a3534ec YM |
2714 | /* User should be able to see failure reason in system logs */ |
2715 | if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) | |
2716 | return -EINVAL; | |
6411280a AE |
2717 | |
2718 | /* must lock vfpf channel to protect against vf flows */ | |
2719 | bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); | |
2720 | ||
2721 | /* remove existing eth macs */ | |
3a3534ec | 2722 | mac_obj = &bnx2x_leading_vfq(vf, mac_obj); |
6411280a AE |
2723 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true); |
2724 | if (rc) { | |
2725 | BNX2X_ERR("failed to delete eth macs\n"); | |
31329afd AE |
2726 | rc = -EINVAL; |
2727 | goto out; | |
6411280a AE |
2728 | } |
2729 | ||
2730 | /* remove existing uc list macs */ | |
2731 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true); | |
2732 | if (rc) { | |
2733 | BNX2X_ERR("failed to delete uc_list macs\n"); | |
31329afd AE |
2734 | rc = -EINVAL; |
2735 | goto out; | |
6411280a AE |
2736 | } |
2737 | ||
2738 | /* configure the new mac to device */ | |
3ec9f9ca | 2739 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
6411280a | 2740 | bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true, |
3ec9f9ca | 2741 | BNX2X_ETH_MAC, &ramrod_flags); |
6411280a | 2742 | |
31329afd | 2743 | out: |
6411280a AE |
2744 | bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); |
2745 | } | |
2746 | ||
02948344 | 2747 | return rc; |
3ec9f9ca AE |
2748 | } |
2749 | ||
05cc5a39 YM |
2750 | static void bnx2x_set_vf_vlan_acceptance(struct bnx2x *bp, |
2751 | struct bnx2x_virtf *vf, bool accept) | |
2752 | { | |
2753 | struct bnx2x_rx_mode_ramrod_params rx_ramrod; | |
2754 | unsigned long accept_flags; | |
2755 | ||
2756 | /* need to remove/add the VF's accept_any_vlan bit */ | |
2757 | accept_flags = bnx2x_leading_vfq(vf, accept_flags); | |
2758 | if (accept) | |
2759 | set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
2760 | else | |
2761 | clear_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
2762 | ||
2763 | bnx2x_vf_prep_rx_mode(bp, LEADING_IDX, &rx_ramrod, vf, | |
2764 | accept_flags); | |
2765 | bnx2x_leading_vfq(vf, accept_flags) = accept_flags; | |
2766 | bnx2x_config_rx_mode(bp, &rx_ramrod); | |
2767 | } | |
2768 | ||
2769 | static int bnx2x_set_vf_vlan_filter(struct bnx2x *bp, struct bnx2x_virtf *vf, | |
2770 | u16 vlan, bool add) | |
3ec9f9ca | 2771 | { |
e8379c79 | 2772 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; |
05cc5a39 YM |
2773 | unsigned long ramrod_flags = 0; |
2774 | int rc = 0; | |
2775 | ||
2776 | /* configure the new vlan to device */ | |
2777 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
2778 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
2779 | ramrod_param.vlan_mac_obj = &bnx2x_leading_vfq(vf, vlan_obj); | |
2780 | ramrod_param.ramrod_flags = ramrod_flags; | |
2781 | ramrod_param.user_req.u.vlan.vlan = vlan; | |
2782 | ramrod_param.user_req.cmd = add ? BNX2X_VLAN_MAC_ADD | |
2783 | : BNX2X_VLAN_MAC_DEL; | |
2784 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); | |
2785 | if (rc) { | |
2786 | BNX2X_ERR("failed to configure vlan\n"); | |
2787 | return -EINVAL; | |
2788 | } | |
2789 | ||
2790 | return 0; | |
2791 | } | |
2792 | ||
79aab093 MS |
2793 | int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos, |
2794 | __be16 vlan_proto) | |
05cc5a39 | 2795 | { |
e8379c79 | 2796 | struct pf_vf_bulletin_content *bulletin = NULL; |
3ec9f9ca | 2797 | struct bnx2x *bp = netdev_priv(dev); |
e8379c79 YM |
2798 | struct bnx2x_vlan_mac_obj *vlan_obj; |
2799 | unsigned long vlan_mac_flags = 0; | |
2800 | unsigned long ramrod_flags = 0; | |
5ae30d78 | 2801 | struct bnx2x_virtf *vf = NULL; |
05cc5a39 | 2802 | int i, rc; |
3ec9f9ca | 2803 | |
3ec9f9ca AE |
2804 | if (vlan > 4095) { |
2805 | BNX2X_ERR("illegal vlan value %d\n", vlan); | |
2806 | return -EINVAL; | |
2807 | } | |
2808 | ||
79aab093 MS |
2809 | if (vlan_proto != htons(ETH_P_8021Q)) |
2810 | return -EPROTONOSUPPORT; | |
2811 | ||
3ec9f9ca AE |
2812 | DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n", |
2813 | vfidx, vlan, 0); | |
2814 | ||
6495d15a DK |
2815 | /* sanity and init */ |
2816 | rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); | |
2817 | if (rc) | |
2818 | return rc; | |
2819 | ||
3ec9f9ca AE |
2820 | /* update PF's copy of the VF's bulletin. No point in posting the vlan |
2821 | * to the VF since it doesn't have anything to do with it. But it useful | |
2822 | * to store it here in case the VF is not up yet and we can only | |
e8379c79 YM |
2823 | * configure the vlan later when it does. Treat vlan id 0 as remove the |
2824 | * Host tag. | |
3ec9f9ca | 2825 | */ |
6495d15a DK |
2826 | mutex_lock(&bp->vfdb->bulletin_mutex); |
2827 | ||
e8379c79 YM |
2828 | if (vlan > 0) |
2829 | bulletin->valid_bitmap |= 1 << VLAN_VALID; | |
2830 | else | |
2831 | bulletin->valid_bitmap &= ~(1 << VLAN_VALID); | |
3ec9f9ca AE |
2832 | bulletin->vlan = vlan; |
2833 | ||
05cc5a39 YM |
2834 | /* Post update on VF's bulletin board */ |
2835 | rc = bnx2x_post_vf_bulletin(bp, vfidx); | |
2836 | if (rc) | |
2837 | BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx); | |
6495d15a DK |
2838 | mutex_unlock(&bp->vfdb->bulletin_mutex); |
2839 | ||
3ec9f9ca | 2840 | /* is vf initialized and queue set up? */ |
e8379c79 YM |
2841 | if (vf->state != VF_ENABLED || |
2842 | bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)) != | |
2843 | BNX2X_Q_LOGICAL_STATE_ACTIVE) | |
2844 | return rc; | |
3ec9f9ca | 2845 | |
3a3534ec YM |
2846 | /* User should be able to see error in system logs */ |
2847 | if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) | |
2848 | return -EINVAL; | |
3ec9f9ca | 2849 | |
e8379c79 YM |
2850 | /* must lock vfpf channel to protect against vf flows */ |
2851 | bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); | |
3ec9f9ca | 2852 | |
e8379c79 YM |
2853 | /* remove existing vlans */ |
2854 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
3a3534ec | 2855 | vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); |
e8379c79 YM |
2856 | rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_mac_flags, |
2857 | &ramrod_flags); | |
2858 | if (rc) { | |
2859 | BNX2X_ERR("failed to delete vlans\n"); | |
2860 | rc = -EINVAL; | |
2861 | goto out; | |
2862 | } | |
2863 | ||
05cc5a39 YM |
2864 | /* clear accept_any_vlan when HV forces vlan, otherwise |
2865 | * according to VF capabilities | |
2866 | */ | |
2867 | if (vlan || !(vf->cfg_flags & VF_CFG_VLAN_FILTER)) | |
2868 | bnx2x_set_vf_vlan_acceptance(bp, vf, !vlan); | |
e8379c79 | 2869 | |
05cc5a39 YM |
2870 | rc = bnx2x_set_vf_vlan_filter(bp, vf, vlan, true); |
2871 | if (rc) | |
e8379c79 | 2872 | goto out; |
3ec9f9ca | 2873 | |
05cc5a39 YM |
2874 | /* send queue update ramrods to configure default vlan and |
2875 | * silent vlan removal | |
e8379c79 | 2876 | */ |
05cc5a39 YM |
2877 | for_each_vfq(vf, i) { |
2878 | struct bnx2x_queue_state_params q_params = {NULL}; | |
2879 | struct bnx2x_queue_update_params *update_params; | |
2880 | ||
2881 | q_params.q_obj = &bnx2x_vfq(vf, i, sp_obj); | |
2882 | ||
2883 | /* validate the Q is UP */ | |
2884 | if (bnx2x_get_q_logical_state(bp, q_params.q_obj) != | |
2885 | BNX2X_Q_LOGICAL_STATE_ACTIVE) | |
2886 | continue; | |
2887 | ||
2888 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
2889 | q_params.cmd = BNX2X_Q_CMD_UPDATE; | |
2890 | update_params = &q_params.params.update; | |
2891 | __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, | |
3ec9f9ca | 2892 | &update_params->update_flags); |
05cc5a39 | 2893 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, |
3ec9f9ca | 2894 | &update_params->update_flags); |
05cc5a39 YM |
2895 | if (vlan == 0) { |
2896 | /* if vlan is 0 then we want to leave the VF traffic | |
2897 | * untagged, and leave the incoming traffic untouched | |
2898 | * (i.e. do not remove any vlan tags). | |
2899 | */ | |
2900 | __clear_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, | |
2901 | &update_params->update_flags); | |
2902 | __clear_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
2903 | &update_params->update_flags); | |
2904 | } else { | |
2905 | /* configure default vlan to vf queue and set silent | |
2906 | * vlan removal (the vf remains unaware of this vlan). | |
2907 | */ | |
2908 | __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, | |
2909 | &update_params->update_flags); | |
2910 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
2911 | &update_params->update_flags); | |
2912 | update_params->def_vlan = vlan; | |
2913 | update_params->silent_removal_value = | |
2914 | vlan & VLAN_VID_MASK; | |
2915 | update_params->silent_removal_mask = VLAN_VID_MASK; | |
2916 | } | |
3ec9f9ca | 2917 | |
05cc5a39 YM |
2918 | /* Update the Queue state */ |
2919 | rc = bnx2x_queue_state_change(bp, &q_params); | |
2920 | if (rc) { | |
2921 | BNX2X_ERR("Failed to configure default VLAN queue %d\n", | |
2922 | i); | |
2923 | goto out; | |
2924 | } | |
e8379c79 | 2925 | } |
31329afd | 2926 | out: |
e8379c79 YM |
2927 | bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); |
2928 | ||
05cc5a39 YM |
2929 | if (rc) |
2930 | DP(BNX2X_MSG_IOV, | |
2931 | "updated VF[%d] vlan configuration (vlan = %d)\n", | |
2932 | vfidx, vlan); | |
2933 | ||
31329afd | 2934 | return rc; |
6411280a AE |
2935 | } |
2936 | ||
16a5fd92 YM |
2937 | /* crc is the first field in the bulletin board. Compute the crc over the |
2938 | * entire bulletin board excluding the crc field itself. Use the length field | |
2939 | * as the Bulletin Board was posted by a PF with possibly a different version | |
2940 | * from the vf which will sample it. Therefore, the length is computed by the | |
6495d15a | 2941 | * PF and then used blindly by the VF. |
6411280a | 2942 | */ |
6495d15a | 2943 | u32 bnx2x_crc_vf_bulletin(struct pf_vf_bulletin_content *bulletin) |
6411280a AE |
2944 | { |
2945 | return crc32(BULLETIN_CRC_SEED, | |
2946 | ((u8 *)bulletin) + sizeof(bulletin->crc), | |
4c133c39 | 2947 | bulletin->length - sizeof(bulletin->crc)); |
6411280a AE |
2948 | } |
2949 | ||
2950 | /* Check for new posts on the bulletin board */ | |
2951 | enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp) | |
2952 | { | |
6495d15a | 2953 | struct pf_vf_bulletin_content *bulletin; |
6411280a AE |
2954 | int attempts; |
2955 | ||
6495d15a DK |
2956 | /* sampling structure in mid post may result with corrupted data |
2957 | * validate crc to ensure coherency. | |
2958 | */ | |
2959 | for (attempts = 0; attempts < BULLETIN_ATTEMPTS; attempts++) { | |
2960 | u32 crc; | |
6411280a | 2961 | |
6495d15a DK |
2962 | /* sample the bulletin board */ |
2963 | memcpy(&bp->shadow_bulletin, bp->pf2vf_bulletin, | |
2964 | sizeof(union pf_vf_bulletin)); | |
2965 | ||
2966 | crc = bnx2x_crc_vf_bulletin(&bp->shadow_bulletin.content); | |
2967 | ||
2968 | if (bp->shadow_bulletin.content.crc == crc) | |
2969 | break; | |
2970 | ||
2971 | BNX2X_ERR("bad crc on bulletin board. Contained %x computed %x\n", | |
2972 | bp->shadow_bulletin.content.crc, crc); | |
2973 | } | |
2974 | ||
2975 | if (attempts >= BULLETIN_ATTEMPTS) { | |
2976 | BNX2X_ERR("pf to vf bulletin board crc was wrong %d consecutive times. Aborting\n", | |
2977 | attempts); | |
2978 | return PFVF_BULLETIN_CRC_ERR; | |
6411280a | 2979 | } |
6495d15a DK |
2980 | bulletin = &bp->shadow_bulletin.content; |
2981 | ||
2982 | /* bulletin board hasn't changed since last sample */ | |
2983 | if (bp->old_bulletin.version == bulletin->version) | |
2984 | return PFVF_BULLETIN_UNCHANGED; | |
6411280a AE |
2985 | |
2986 | /* the mac address in bulletin board is valid and is new */ | |
6495d15a DK |
2987 | if (bulletin->valid_bitmap & 1 << MAC_ADDR_VALID && |
2988 | !ether_addr_equal(bulletin->mac, bp->old_bulletin.mac)) { | |
6411280a | 2989 | /* update new mac to net device */ |
6495d15a DK |
2990 | memcpy(bp->dev->dev_addr, bulletin->mac, ETH_ALEN); |
2991 | } | |
2992 | ||
2993 | if (bulletin->valid_bitmap & (1 << LINK_VALID)) { | |
2994 | DP(BNX2X_MSG_IOV, "link update speed %d flags %x\n", | |
2995 | bulletin->link_speed, bulletin->link_flags); | |
2996 | ||
2997 | bp->vf_link_vars.line_speed = bulletin->link_speed; | |
2998 | bp->vf_link_vars.link_report_flags = 0; | |
2999 | /* Link is down */ | |
3000 | if (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN) | |
3001 | __set_bit(BNX2X_LINK_REPORT_LINK_DOWN, | |
3002 | &bp->vf_link_vars.link_report_flags); | |
3003 | /* Full DUPLEX */ | |
3004 | if (bulletin->link_flags & VFPF_LINK_REPORT_FULL_DUPLEX) | |
3005 | __set_bit(BNX2X_LINK_REPORT_FD, | |
3006 | &bp->vf_link_vars.link_report_flags); | |
3007 | /* Rx Flow Control is ON */ | |
3008 | if (bulletin->link_flags & VFPF_LINK_REPORT_RX_FC_ON) | |
3009 | __set_bit(BNX2X_LINK_REPORT_RX_FC_ON, | |
3010 | &bp->vf_link_vars.link_report_flags); | |
3011 | /* Tx Flow Control is ON */ | |
3012 | if (bulletin->link_flags & VFPF_LINK_REPORT_TX_FC_ON) | |
3013 | __set_bit(BNX2X_LINK_REPORT_TX_FC_ON, | |
3014 | &bp->vf_link_vars.link_report_flags); | |
3015 | __bnx2x_link_report(bp); | |
6411280a AE |
3016 | } |
3017 | ||
3018 | /* copy new bulletin board to bp */ | |
6495d15a DK |
3019 | memcpy(&bp->old_bulletin, bulletin, |
3020 | sizeof(struct pf_vf_bulletin_content)); | |
6411280a AE |
3021 | |
3022 | return PFVF_BULLETIN_UPDATED; | |
3023 | } | |
3024 | ||
37173488 YM |
3025 | void bnx2x_timer_sriov(struct bnx2x *bp) |
3026 | { | |
3027 | bnx2x_sample_bulletin(bp); | |
3028 | ||
3029 | /* if channel is down we need to self destruct */ | |
230bb0f3 YM |
3030 | if (bp->old_bulletin.valid_bitmap & 1 << CHANNEL_DOWN) |
3031 | bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, | |
3032 | BNX2X_MSG_IOV); | |
37173488 YM |
3033 | } |
3034 | ||
1d6f3cd8 | 3035 | void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp) |
6411280a AE |
3036 | { |
3037 | /* vf doorbells are embedded within the regview */ | |
1d6f3cd8 | 3038 | return bp->regview + PXP_VF_ADDR_DB_START; |
6411280a AE |
3039 | } |
3040 | ||
e2a367f8 YM |
3041 | void bnx2x_vf_pci_dealloc(struct bnx2x *bp) |
3042 | { | |
3043 | BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping, | |
3044 | sizeof(struct bnx2x_vf_mbx_msg)); | |
3045 | BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->pf2vf_bulletin_mapping, | |
3046 | sizeof(union pf_vf_bulletin)); | |
3047 | } | |
3048 | ||
6411280a AE |
3049 | int bnx2x_vf_pci_alloc(struct bnx2x *bp) |
3050 | { | |
8b49a4c7 DK |
3051 | mutex_init(&bp->vf2pf_mutex); |
3052 | ||
6411280a | 3053 | /* allocate vf2pf mailbox for vf to pf channel */ |
cd2b0389 JP |
3054 | bp->vf2pf_mbox = BNX2X_PCI_ALLOC(&bp->vf2pf_mbox_mapping, |
3055 | sizeof(struct bnx2x_vf_mbx_msg)); | |
3056 | if (!bp->vf2pf_mbox) | |
3057 | goto alloc_mem_err; | |
6411280a AE |
3058 | |
3059 | /* allocate pf 2 vf bulletin board */ | |
cd2b0389 JP |
3060 | bp->pf2vf_bulletin = BNX2X_PCI_ALLOC(&bp->pf2vf_bulletin_mapping, |
3061 | sizeof(union pf_vf_bulletin)); | |
3062 | if (!bp->pf2vf_bulletin) | |
3063 | goto alloc_mem_err; | |
6411280a | 3064 | |
6495d15a DK |
3065 | bnx2x_vf_bulletin_finalize(&bp->pf2vf_bulletin->content, true); |
3066 | ||
6411280a AE |
3067 | return 0; |
3068 | ||
3069 | alloc_mem_err: | |
e2a367f8 | 3070 | bnx2x_vf_pci_dealloc(bp); |
6411280a AE |
3071 | return -ENOMEM; |
3072 | } | |
3c76feff | 3073 | |
78c3bcc5 AE |
3074 | void bnx2x_iov_channel_down(struct bnx2x *bp) |
3075 | { | |
3076 | int vf_idx; | |
3077 | struct pf_vf_bulletin_content *bulletin; | |
3078 | ||
3079 | if (!IS_SRIOV(bp)) | |
3080 | return; | |
3081 | ||
3082 | for_each_vf(bp, vf_idx) { | |
3083 | /* locate this VFs bulletin board and update the channel down | |
3084 | * bit | |
3085 | */ | |
3086 | bulletin = BP_VF_BULLETIN(bp, vf_idx); | |
3087 | bulletin->valid_bitmap |= 1 << CHANNEL_DOWN; | |
3088 | ||
3089 | /* update vf bulletin board */ | |
3090 | bnx2x_post_vf_bulletin(bp, vf_idx); | |
3091 | } | |
3092 | } | |
370d4a26 YM |
3093 | |
3094 | void bnx2x_iov_task(struct work_struct *work) | |
3095 | { | |
3096 | struct bnx2x *bp = container_of(work, struct bnx2x, iov_task.work); | |
3097 | ||
3098 | if (!netif_running(bp->dev)) | |
3099 | return; | |
3100 | ||
3101 | if (test_and_clear_bit(BNX2X_IOV_HANDLE_FLR, | |
3102 | &bp->iov_task_state)) | |
3103 | bnx2x_vf_handle_flr_event(bp); | |
3104 | ||
370d4a26 YM |
3105 | if (test_and_clear_bit(BNX2X_IOV_HANDLE_VF_MSG, |
3106 | &bp->iov_task_state)) | |
3107 | bnx2x_vf_mbx(bp); | |
3108 | } | |
3109 | ||
3110 | void bnx2x_schedule_iov_task(struct bnx2x *bp, enum bnx2x_iov_flag flag) | |
3111 | { | |
4e857c58 | 3112 | smp_mb__before_atomic(); |
370d4a26 | 3113 | set_bit(flag, &bp->iov_task_state); |
4e857c58 | 3114 | smp_mb__after_atomic(); |
370d4a26 YM |
3115 | DP(BNX2X_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag); |
3116 | queue_delayed_work(bnx2x_iov_wq, &bp->iov_task, 0); | |
3117 | } |